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ee86248c 1/* tc-i386.c -- Assemble Intel syntax code for ix86/x86-64
d87bef3a 2 Copyright (C) 2009-2023 Free Software Foundation, Inc.
ee86248c
JB
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21static struct
22 {
23 operatorT op_modifier; /* Operand modifier. */
24 int is_mem; /* 1 if operand is memory reference. */
25303607 25 int is_indirect; /* 1 if operand is indirect reference. */
6cee4cda 26 int has_offset; /* 1 if operand has offset. */
ee86248c
JB
27 unsigned int in_offset; /* >=1 if processing operand of offset. */
28 unsigned int in_bracket; /* >=1 if processing operand in brackets. */
33eaf5de 29 unsigned int in_scale; /* >=1 if processing multiplication operand
ee86248c
JB
30 * in brackets. */
31 i386_operand_type reloc_types; /* Value obtained from lex_got(). */
32 const reg_entry *base; /* Base register (if any). */
33 const reg_entry *index; /* Index register (if any). */
34 offsetT scale_factor; /* Accumulated scale factor. */
35 symbolS *seg;
36 }
37intel_state;
38
39/* offset X_add_symbol */
40#define O_offset O_md32
7ac3eb25
L
41/* offset X_add_symbol */
42#define O_short O_md31
43/* near ptr X_add_symbol */
44#define O_near_ptr O_md30
45/* far ptr X_add_symbol */
46#define O_far_ptr O_md29
ee86248c 47/* byte ptr X_add_symbol */
7ac3eb25 48#define O_byte_ptr O_md28
ee86248c 49/* word ptr X_add_symbol */
7ac3eb25 50#define O_word_ptr O_md27
ee86248c 51/* dword ptr X_add_symbol */
7ac3eb25 52#define O_dword_ptr O_md26
ee86248c 53/* qword ptr X_add_symbol */
7ac3eb25 54#define O_qword_ptr O_md25
f2f5811f
JB
55/* mmword ptr X_add_symbol */
56#define O_mmword_ptr O_qword_ptr
ee86248c 57/* fword ptr X_add_symbol */
7456d03d 58#define O_fword_ptr O_md24
ee86248c 59/* tbyte ptr X_add_symbol */
7456d03d
JB
60#define O_tbyte_ptr O_md23
61/* oword ptr X_add_symbol */
62#define O_oword_ptr O_md22
ee86248c 63/* xmmword ptr X_add_symbol */
7456d03d 64#define O_xmmword_ptr O_oword_ptr
ee86248c 65/* ymmword ptr X_add_symbol */
7456d03d 66#define O_ymmword_ptr O_md21
43234a1e 67/* zmmword ptr X_add_symbol */
7456d03d 68#define O_zmmword_ptr O_md20
ee86248c
JB
69
70static struct
71 {
72 const char *name;
1e9cc1c2 73 operatorT op;
ee86248c
JB
74 unsigned int operands;
75 }
76const i386_operators[] =
77 {
78 { "and", O_bit_and, 2 },
79 { "eq", O_eq, 2 },
80 { "ge", O_ge, 2 },
81 { "gt", O_gt, 2 },
82 { "le", O_le, 2 },
83 { "lt", O_lt, 2 },
84 { "mod", O_modulus, 2 },
85 { "ne", O_ne, 2 },
86 { "not", O_bit_not, 1 },
87 { "offset", O_offset, 1 },
88 { "or", O_bit_inclusive_or, 2 },
89 { "shl", O_left_shift, 2 },
90 { "short", O_short, 1 },
91 { "shr", O_right_shift, 2 },
92 { "xor", O_bit_exclusive_or, 2 },
93 { NULL, O_illegal, 0 }
94 };
95
96static struct
97 {
98 const char *name;
1e9cc1c2 99 operatorT op;
ee86248c
JB
100 unsigned short sz[3];
101 }
102const i386_types[] =
103 {
104#define I386_TYPE(t, n) { #t, O_##t##_ptr, { n, n, n } }
105 I386_TYPE(byte, 1),
106 I386_TYPE(word, 2),
107 I386_TYPE(dword, 4),
108 I386_TYPE(fword, 6),
109 I386_TYPE(qword, 8),
f2f5811f 110 I386_TYPE(mmword, 8),
ee86248c
JB
111 I386_TYPE(tbyte, 10),
112 I386_TYPE(oword, 16),
113 I386_TYPE(xmmword, 16),
114 I386_TYPE(ymmword, 32),
43234a1e 115 I386_TYPE(zmmword, 64),
ee86248c
JB
116#undef I386_TYPE
117 { "near", O_near_ptr, { 0xff04, 0xff02, 0xff08 } },
118 { "far", O_far_ptr, { 0xff06, 0xff05, 0xff06 } },
119 { NULL, O_illegal, { 0, 0, 0 } }
120 };
121
122operatorT i386_operator (const char *name, unsigned int operands, char *pc)
123{
124 unsigned int j;
125
b3983e5f
JB
126#ifdef SVR4_COMMENT_CHARS
127 if (!name && operands == 2 && *input_line_pointer == '\\')
128 switch (input_line_pointer[1])
129 {
130 case '/': input_line_pointer += 2; return O_divide;
131 case '%': input_line_pointer += 2; return O_modulus;
132 case '*': input_line_pointer += 2; return O_multiply;
133 }
134#endif
135
ee86248c
JB
136 if (!intel_syntax)
137 return O_absent;
138
139 if (!name)
140 {
141 if (operands != 2)
142 return O_illegal;
143 switch (*input_line_pointer)
144 {
145 case ':':
146 ++input_line_pointer;
147 return O_full_ptr;
148 case '[':
149 ++input_line_pointer;
150 return O_index;
151 case '@':
152 if (this_operand >= 0 && i.reloc[this_operand] == NO_RELOC)
153 {
154 int adjust = 0;
155 char *gotfree_input_line = lex_got (&i.reloc[this_operand],
156 &adjust,
d258b828 157 &intel_state.reloc_types);
ee86248c
JB
158
159 if (!gotfree_input_line)
160 break;
161 free (gotfree_input_line);
162 *input_line_pointer++ = '+';
163 memset (input_line_pointer, '0', adjust - 1);
164 input_line_pointer[adjust - 1] = ' ';
165 return O_add;
166 }
167 break;
168 }
169 return O_illegal;
170 }
171
6acf9130
JB
172 /* See the quotation related comment in i386_parse_name(). */
173 if (*pc == '"')
174 return O_absent;
175
ee86248c 176 for (j = 0; i386_operators[j].name; ++j)
91d6fa6a 177 if (strcasecmp (i386_operators[j].name, name) == 0)
ee86248c
JB
178 {
179 if (i386_operators[j].operands
180 && i386_operators[j].operands != operands)
181 return O_illegal;
1e9cc1c2 182 return i386_operators[j].op;
ee86248c
JB
183 }
184
185 for (j = 0; i386_types[j].name; ++j)
91d6fa6a 186 if (strcasecmp (i386_types[j].name, name) == 0)
ee86248c 187 break;
d02603dc 188
ee86248c
JB
189 if (i386_types[j].name && *pc == ' ')
190 {
a4f8c177 191 const char *start = ++input_line_pointer;
d02603dc 192 char *pname;
a4f8c177 193 char c = get_symbol_name (&pname);
d02603dc 194
a4f8c177 195 if (strcasecmp (pname, "ptr") == 0 && (c != '"' || pname == start))
ee86248c 196 {
91d6fa6a 197 pname[-1] = *pc;
ee86248c
JB
198 *pc = c;
199 if (intel_syntax > 0 || operands != 1)
200 return O_illegal;
1e9cc1c2 201 return i386_types[j].op;
ee86248c
JB
202 }
203
a4f8c177 204 if (strcasecmp (pname, "bcst") == 0 && (c != '"' || pname == start))
a5748e0d 205 {
a5748e0d
JB
206 pname[-1] = *pc;
207 *pc = c;
208 if (intel_syntax > 0 || operands != 1
209 || i386_types[j].sz[0] > 8
210 || (i386_types[j].sz[0] & (i386_types[j].sz[0] - 1)))
211 return O_illegal;
212 if (!i.broadcast.bytes && !i.broadcast.type)
213 {
214 i.broadcast.bytes = i386_types[j].sz[0];
215 i.broadcast.operand = this_operand;
216 }
217 return i386_types[j].op;
218 }
219
d02603dc 220 (void) restore_line_pointer (c);
91d6fa6a 221 input_line_pointer = pname - 1;
ee86248c
JB
222 }
223
224 return O_absent;
225}
226
227static int i386_intel_parse_name (const char *name, expressionS *e)
228{
91d6fa6a 229 unsigned int j;
ee86248c 230
b7adb16d
JB
231 if (! strcmp (name, "$"))
232 {
233 current_location (e);
234 return 1;
235 }
236
91d6fa6a
NC
237 for (j = 0; i386_types[j].name; ++j)
238 if (strcasecmp(i386_types[j].name, name) == 0)
ee86248c
JB
239 {
240 e->X_op = O_constant;
91d6fa6a 241 e->X_add_number = i386_types[j].sz[flag_code];
ee86248c
JB
242 e->X_add_symbol = NULL;
243 e->X_op_symbol = NULL;
244 return 1;
245 }
246
247 return 0;
248}
249
91d6fa6a 250static INLINE int i386_intel_check (const reg_entry *rreg,
ee86248c 251 const reg_entry *base,
91d6fa6a 252 const reg_entry *iindex)
ee86248c 253{
f09c1772
L
254 if ((this_operand >= 0
255 && rreg != i.op[this_operand].regs)
256 || base != intel_state.base
257 || iindex != intel_state.index)
ee86248c
JB
258 {
259 as_bad (_("invalid use of register"));
260 return 0;
261 }
262 return 1;
263}
264
265static INLINE void i386_intel_fold (expressionS *e, symbolS *sym)
266{
27dee630 267 expressionS *exp = symbol_get_value_expression (sym);
ee86248c
JB
268 if (S_GET_SEGMENT (sym) == absolute_section)
269 {
270 offsetT val = e->X_add_number;
271
27dee630 272 *e = *exp;
ee86248c
JB
273 e->X_add_number += val;
274 }
275 else
276 {
27dee630
L
277 if (exp->X_op == O_symbol
278 && strcmp (S_GET_NAME (exp->X_add_symbol),
279 GLOBAL_OFFSET_TABLE_NAME) == 0)
280 sym = exp->X_add_symbol;
ee86248c
JB
281 e->X_add_symbol = sym;
282 e->X_op_symbol = NULL;
283 e->X_op = O_symbol;
284 }
285}
286
3c7b9c2c
L
287static int
288i386_intel_simplify_register (expressionS *e)
289{
290 int reg_num;
291
292 if (this_operand < 0 || intel_state.in_offset)
293 {
294 as_bad (_("invalid use of register"));
295 return 0;
296 }
297
298 if (e->X_op == O_register)
299 reg_num = e->X_add_number;
300 else
301 reg_num = e->X_md - 1;
302
35015cd1
NC
303 if (reg_num < 0 || reg_num >= (int) i386_regtab_size)
304 {
305 as_bad (_("invalid register number"));
306 return 0;
307 }
308
4faaa10f
JB
309 if (!check_register (&i386_regtab[reg_num]))
310 {
311 as_bad (_("register '%s%s' cannot be used here"),
312 register_prefix, i386_regtab[reg_num].reg_name);
313 return 0;
314 }
315
3c7b9c2c
L
316 if (!intel_state.in_bracket)
317 {
318 if (i.op[this_operand].regs)
319 {
320 as_bad (_("invalid use of register"));
321 return 0;
322 }
0ff3b7d0
JB
323 if ((i386_regtab[reg_num].reg_type.bitfield.class == SReg
324 && i386_regtab[reg_num].reg_num == RegFlat)
325 || (dot_insn ()
326 && i386_regtab[reg_num].reg_type.bitfield.class == ClassNone))
3c7b9c2c
L
327 {
328 as_bad (_("invalid use of pseudo-register"));
329 return 0;
330 }
331 i.op[this_operand].regs = i386_regtab + reg_num;
332 }
9e2934f7 333 else if (!intel_state.index
1b54b8d7
JB
334 && (i386_regtab[reg_num].reg_type.bitfield.xmmword
335 || i386_regtab[reg_num].reg_type.bitfield.ymmword
336 || i386_regtab[reg_num].reg_type.bitfield.zmmword
e968fc9b 337 || i386_regtab[reg_num].reg_num == RegIZ))
9e2934f7 338 intel_state.index = i386_regtab + reg_num;
3c7b9c2c
L
339 else if (!intel_state.base && !intel_state.in_scale)
340 intel_state.base = i386_regtab + reg_num;
341 else if (!intel_state.index)
9e2934f7 342 {
a152332d
JB
343 const insn_template *t = current_templates->start;
344
9e2934f7 345 if (intel_state.in_scale
c47b4d71 346 || i386_regtab[reg_num].reg_type.bitfield.baseindex
0ff3b7d0 347 || dot_insn ()
c47b4d71
JB
348 || t->mnem_off == MN_bndmk
349 || t->mnem_off == MN_bndldx
350 || t->mnem_off == MN_bndstx)
9e2934f7
JB
351 intel_state.index = i386_regtab + reg_num;
352 else
353 {
354 /* Convert base to index and make ESP/RSP the base. */
355 intel_state.index = intel_state.base;
356 intel_state.base = i386_regtab + reg_num;
357 }
358 }
3c7b9c2c
L
359 else
360 {
361 /* esp is invalid as index */
34684862 362 intel_state.index = reg_eax + ESP_REG_NUM;
3c7b9c2c
L
363 }
364 return 2;
365}
366
ee86248c
JB
367static int i386_intel_simplify (expressionS *);
368
369static INLINE int i386_intel_simplify_symbol(symbolS *sym)
370{
371 int ret = i386_intel_simplify (symbol_get_value_expression (sym));
372
373 if (ret == 2)
374 {
375 S_SET_SEGMENT(sym, absolute_section);
376 ret = 1;
377 }
378 return ret;
379}
380
381static int i386_intel_simplify (expressionS *e)
382{
f09c1772
L
383 const reg_entry *the_reg = (this_operand >= 0
384 ? i.op[this_operand].regs : NULL);
ee86248c 385 const reg_entry *base = intel_state.base;
91d6fa6a 386 const reg_entry *state_index = intel_state.index;
ee86248c
JB
387 int ret;
388
389 if (!intel_syntax)
390 return 1;
391
392 switch (e->X_op)
393 {
394 case O_index:
395 if (e->X_add_symbol)
396 {
397 if (!i386_intel_simplify_symbol (e->X_add_symbol)
f09c1772
L
398 || !i386_intel_check(the_reg, intel_state.base,
399 intel_state.index))
5bb3703f 400 return 0;
ee86248c
JB
401 }
402 if (!intel_state.in_offset)
403 ++intel_state.in_bracket;
404 ret = i386_intel_simplify_symbol (e->X_op_symbol);
405 if (!intel_state.in_offset)
406 --intel_state.in_bracket;
407 if (!ret)
408 return 0;
409 if (e->X_add_symbol)
410 e->X_op = O_add;
411 else
412 i386_intel_fold (e, e->X_op_symbol);
413 break;
414
415 case O_offset:
6cee4cda 416 intel_state.has_offset = 1;
ee86248c
JB
417 ++intel_state.in_offset;
418 ret = i386_intel_simplify_symbol (e->X_add_symbol);
419 --intel_state.in_offset;
91d6fa6a 420 if (!ret || !i386_intel_check(the_reg, base, state_index))
ee86248c
JB
421 return 0;
422 i386_intel_fold (e, e->X_add_symbol);
423 return ret;
424
425 case O_byte_ptr:
426 case O_word_ptr:
427 case O_dword_ptr:
428 case O_fword_ptr:
f2f5811f 429 case O_qword_ptr: /* O_mmword_ptr */
ee86248c 430 case O_tbyte_ptr:
7456d03d 431 case O_oword_ptr: /* O_xmmword_ptr */
ee86248c 432 case O_ymmword_ptr:
43234a1e 433 case O_zmmword_ptr:
ee86248c
JB
434 case O_near_ptr:
435 case O_far_ptr:
436 if (intel_state.op_modifier == O_absent)
437 intel_state.op_modifier = e->X_op;
438 /* FALLTHROUGH */
439 case O_short:
f09c1772
L
440 if (symbol_get_value_expression (e->X_add_symbol)->X_op
441 == O_register)
ee86248c
JB
442 {
443 as_bad (_("invalid use of register"));
444 return 0;
445 }
446 if (!i386_intel_simplify_symbol (e->X_add_symbol))
447 return 0;
448 i386_intel_fold (e, e->X_add_symbol);
449 break;
450
451 case O_full_ptr:
f09c1772
L
452 if (symbol_get_value_expression (e->X_op_symbol)->X_op
453 == O_register)
ee86248c
JB
454 {
455 as_bad (_("invalid use of register"));
456 return 0;
457 }
458 if (!i386_intel_simplify_symbol (e->X_op_symbol)
f09c1772
L
459 || !i386_intel_check(the_reg, intel_state.base,
460 intel_state.index))
ee86248c
JB
461 return 0;
462 if (!intel_state.in_offset)
fd4e0347
JB
463 {
464 if (!intel_state.seg)
465 intel_state.seg = e->X_add_symbol;
466 else
467 {
468 expressionS exp;
469
470 exp.X_op = O_full_ptr;
471 exp.X_add_symbol = e->X_add_symbol;
472 exp.X_op_symbol = intel_state.seg;
473 intel_state.seg = make_expr_symbol (&exp);
474 }
475 }
ee86248c
JB
476 i386_intel_fold (e, e->X_op_symbol);
477 break;
478
ee86248c
JB
479 case O_multiply:
480 if (this_operand >= 0 && intel_state.in_bracket)
481 {
482 expressionS *scale = NULL;
c2a5914e 483 int has_index = (intel_state.index != NULL);
ee86248c
JB
484
485 if (!intel_state.in_scale++)
486 intel_state.scale_factor = 1;
487
488 ret = i386_intel_simplify_symbol (e->X_add_symbol);
c2a5914e 489 if (ret && !has_index && intel_state.index)
ee86248c
JB
490 scale = symbol_get_value_expression (e->X_op_symbol);
491
492 if (ret)
493 ret = i386_intel_simplify_symbol (e->X_op_symbol);
c2a5914e 494 if (ret && !scale && !has_index && intel_state.index)
ee86248c
JB
495 scale = symbol_get_value_expression (e->X_add_symbol);
496
c2a5914e 497 if (ret && scale)
ee86248c
JB
498 {
499 resolve_expression (scale);
500 if (scale->X_op != O_constant
dc821c5f 501 || intel_state.index->reg_type.bitfield.word)
ee86248c
JB
502 scale->X_add_number = 0;
503 intel_state.scale_factor *= scale->X_add_number;
504 }
505
506 --intel_state.in_scale;
507 if (!ret)
508 return 0;
509
510 if (!intel_state.in_scale)
511 switch (intel_state.scale_factor)
512 {
513 case 1:
514 i.log2_scale_factor = 0;
515 break;
516 case 2:
517 i.log2_scale_factor = 1;
518 break;
519 case 4:
520 i.log2_scale_factor = 2;
521 break;
522 case 8:
523 i.log2_scale_factor = 3;
524 break;
525 default:
526 /* esp is invalid as index */
34684862 527 intel_state.index = reg_eax + ESP_REG_NUM;
ee86248c
JB
528 break;
529 }
530
531 break;
532 }
92b4f90c 533 goto fallthrough;
3c7b9c2c
L
534
535 case O_register:
536 ret = i386_intel_simplify_register (e);
537 if (ret == 2)
538 {
539 gas_assert (e->X_add_number < (unsigned short) -1);
540 e->X_md = (unsigned short) e->X_add_number + 1;
541 e->X_op = O_constant;
542 e->X_add_number = 0;
543 }
544 return ret;
545
546 case O_constant:
547 if (e->X_md)
548 return i386_intel_simplify_register (e);
549
ee86248c
JB
550 /* FALLTHROUGH */
551 default:
dc1e8a47 552 fallthrough:
f09c1772
L
553 if (e->X_add_symbol
554 && !i386_intel_simplify_symbol (e->X_add_symbol))
ee86248c 555 return 0;
64d23078
JB
556 if (!the_reg && this_operand >= 0
557 && e->X_op == O_symbol && !e->X_add_number)
558 the_reg = i.op[this_operand].regs;
ee86248c
JB
559 if (e->X_op == O_add || e->X_op == O_subtract)
560 {
561 base = intel_state.base;
91d6fa6a 562 state_index = intel_state.index;
ee86248c 563 }
91d6fa6a 564 if (!i386_intel_check (the_reg, base, state_index)
f09c1772
L
565 || (e->X_op_symbol
566 && !i386_intel_simplify_symbol (e->X_op_symbol))
91d6fa6a 567 || !i386_intel_check (the_reg,
f09c1772
L
568 (e->X_op != O_add
569 ? base : intel_state.base),
570 (e->X_op != O_add
571 ? state_index : intel_state.index)))
ee86248c
JB
572 return 0;
573 break;
574 }
575
f09c1772
L
576 if (this_operand >= 0
577 && e->X_op == O_symbol
578 && !intel_state.in_offset)
ee86248c
JB
579 {
580 segT seg = S_GET_SEGMENT (e->X_add_symbol);
581
582 if (seg != absolute_section
583 && seg != reg_section
584 && seg != expr_section)
585 intel_state.is_mem |= 2 - !intel_state.in_bracket;
586 }
587
588 return 1;
589}
590
591int i386_need_index_operator (void)
592{
593 return intel_syntax < 0;
594}
595
596static int
597i386_intel_operand (char *operand_string, int got_a_float)
598{
599 char *saved_input_line_pointer, *buf;
600 segT exp_seg;
601 expressionS exp, *expP;
602 char suffix = 0;
7063667e 603 bool rc_sae_modifier = i.rounding.type != rc_none && i.rounding.modifier;
ee86248c
JB
604 int ret;
605
43234a1e
L
606 /* Handle vector immediates. */
607 if (RC_SAE_immediate (operand_string))
cf665fee
JB
608 {
609 if (i.imm_operands)
610 {
611 as_bad (_("`%s': RC/SAE operand must precede immediate operands"),
76d3f746 612 insn_name (current_templates->start));
cf665fee
JB
613 return 0;
614 }
615
616 return 1;
617 }
43234a1e 618
ee86248c
JB
619 /* Initialize state structure. */
620 intel_state.op_modifier = O_absent;
621 intel_state.is_mem = 0;
25303607 622 intel_state.is_indirect = 0;
1acf546e 623 intel_state.has_offset = 0;
ee86248c
JB
624 intel_state.base = NULL;
625 intel_state.index = NULL;
626 intel_state.seg = NULL;
627 operand_type_set (&intel_state.reloc_types, ~0);
9c2799c2
NC
628 gas_assert (!intel_state.in_offset);
629 gas_assert (!intel_state.in_bracket);
630 gas_assert (!intel_state.in_scale);
ee86248c
JB
631
632 saved_input_line_pointer = input_line_pointer;
633 input_line_pointer = buf = xstrdup (operand_string);
634
635 intel_syntax = -1;
5cc00775 636 expr_mode = expr_operator_none;
ee86248c
JB
637 memset (&exp, 0, sizeof(exp));
638 exp_seg = expression (&exp);
639 ret = i386_intel_simplify (&exp);
640 intel_syntax = 1;
641
642 SKIP_WHITESPACE ();
43234a1e
L
643
644 /* Handle vector operations. */
645 if (*input_line_pointer == '{')
646 {
f70c6814 647 char *end = check_VecOperations (input_line_pointer);
43234a1e
L
648 if (end)
649 input_line_pointer = end;
650 else
651 ret = 0;
652 }
653
ee86248c
JB
654 if (!is_end_of_line[(unsigned char) *input_line_pointer])
655 {
38bf5113
JB
656 if (ret)
657 as_bad (_("junk `%s' after expression"), input_line_pointer);
ee86248c
JB
658 ret = 0;
659 }
660 else if (exp.X_op == O_illegal || exp.X_op == O_absent)
661 {
38bf5113
JB
662 if (ret)
663 as_bad (_("invalid expression"));
ee86248c
JB
664 ret = 0;
665 }
6cee4cda
L
666 else if (!intel_state.has_offset
667 && input_line_pointer > buf
668 && *(input_line_pointer - 1) == ']')
25303607
L
669 {
670 intel_state.is_mem |= 1;
671 intel_state.is_indirect = 1;
672 }
ee86248c
JB
673
674 input_line_pointer = saved_input_line_pointer;
675 free (buf);
676
9c2799c2
NC
677 gas_assert (!intel_state.in_offset);
678 gas_assert (!intel_state.in_bracket);
679 gas_assert (!intel_state.in_scale);
ee86248c
JB
680
681 if (!ret)
682 return 0;
683
684 if (intel_state.op_modifier != O_absent
c47b4d71 685 && current_templates->start->mnem_off != MN_lea)
ee86248c
JB
686 {
687 i.types[this_operand].bitfield.unspecified = 0;
688
689 switch (intel_state.op_modifier)
690 {
691 case O_byte_ptr:
692 i.types[this_operand].bitfield.byte = 1;
693 suffix = BYTE_MNEM_SUFFIX;
694 break;
695
696 case O_word_ptr:
697 i.types[this_operand].bitfield.word = 1;
37404387 698 if (got_a_float == 2) /* "fi..." */
ee86248c 699 suffix = SHORT_MNEM_SUFFIX;
c47b4d71 700 else if (current_templates->start->mnem_off != MN_lar
5eeeafe0
JB
701 && current_templates->start->mnem_off != MN_lsl
702 && current_templates->start->mnem_off != MN_arpl)
ee86248c
JB
703 suffix = WORD_MNEM_SUFFIX;
704 break;
705
706 case O_dword_ptr:
707 i.types[this_operand].bitfield.dword = 1;
76d3f746
JB
708 if ((insn_name (current_templates->start)[0] == 'l'
709 && insn_name (current_templates->start)[2] == 's'
710 && insn_name (current_templates->start)[3] == 0)
c47b4d71 711 || current_templates->start->mnem_off == MN_bound)
ee86248c 712 suffix = WORD_MNEM_SUFFIX;
d488367a 713 else if (flag_code != CODE_32BIT
0cfa3eb3
JB
714 && (current_templates->start->opcode_modifier.jump == JUMP
715 || current_templates->start->opcode_modifier.jump
716 == JUMP_DWORD))
a4d3acd2
JB
717 {
718 i.far_branch = true;
719 suffix = WORD_MNEM_SUFFIX;
720 }
ee86248c
JB
721 else if (got_a_float == 1) /* "f..." */
722 suffix = SHORT_MNEM_SUFFIX;
723 else
724 suffix = LONG_MNEM_SUFFIX;
725 break;
726
727 case O_fword_ptr:
728 i.types[this_operand].bitfield.fword = 1;
c47b4d71
JB
729 if (current_templates->start->mnem_off == MN_les
730 || current_templates->start->mnem_off == MN_lds
731 || current_templates->start->mnem_off == MN_lss
732 || current_templates->start->mnem_off == MN_lfs
733 || current_templates->start->mnem_off == MN_lgs)
ee86248c
JB
734 suffix = LONG_MNEM_SUFFIX;
735 else if (!got_a_float)
736 {
737 if (flag_code == CODE_16BIT)
738 add_prefix (DATA_PREFIX_OPCODE);
a4d3acd2 739 i.far_branch = true;
ee86248c 740 }
ee86248c
JB
741 break;
742
f2f5811f 743 case O_qword_ptr: /* O_mmword_ptr */
ee86248c 744 i.types[this_operand].bitfield.qword = 1;
c47b4d71 745 if (current_templates->start->mnem_off == MN_bound
ee86248c
JB
746 || got_a_float == 1) /* "f..." */
747 suffix = LONG_MNEM_SUFFIX;
748 else
749 suffix = QWORD_MNEM_SUFFIX;
750 break;
751
752 case O_tbyte_ptr:
753 i.types[this_operand].bitfield.tbyte = 1;
f210f0a0
JB
754 if (got_a_float)
755 break;
756 if (flag_code == CODE_64BIT
757 && (current_templates->start->operand_types[0].bitfield.fword
758 || current_templates->start->operand_types[0].bitfield.tbyte
759 || current_templates->start->opcode_modifier.jump == JUMP_DWORD
760 || current_templates->start->opcode_modifier.jump == JUMP))
5990e377 761 suffix = QWORD_MNEM_SUFFIX; /* l[fgs]s, [ls][gi]dt, call, jmp */
ee86248c 762 else
a8f4f6b9 763 i.types[this_operand].bitfield.byte = 1; /* cause an error */
ee86248c
JB
764 break;
765
7456d03d 766 case O_oword_ptr: /* O_xmmword_ptr */
ee86248c 767 i.types[this_operand].bitfield.xmmword = 1;
ee86248c
JB
768 break;
769
770 case O_ymmword_ptr:
771 i.types[this_operand].bitfield.ymmword = 1;
ee86248c
JB
772 break;
773
43234a1e
L
774 case O_zmmword_ptr:
775 i.types[this_operand].bitfield.zmmword = 1;
43234a1e
L
776 break;
777
ee86248c 778 case O_far_ptr:
a4d3acd2 779 i.far_branch = true;
ee86248c
JB
780 /* FALLTHROUGH */
781 case O_near_ptr:
0cfa3eb3
JB
782 if (current_templates->start->opcode_modifier.jump != JUMP
783 && current_templates->start->opcode_modifier.jump != JUMP_DWORD)
164d49cb
JB
784 {
785 /* cause an error */
786 i.types[this_operand].bitfield.byte = 1;
787 i.types[this_operand].bitfield.tbyte = 1;
788 suffix = i.suffix;
789 }
ee86248c
JB
790 break;
791
792 default:
793 BAD_CASE (intel_state.op_modifier);
794 break;
795 }
796
1cb0ab18
JB
797 /* Now check whether we actually want to infer an AT&T-like suffix.
798 We really only need to do this when operand size determination (incl.
799 REX.W) is going to be derived from it. For this we check whether the
800 given suffix is valid for any of the candidate templates. */
801 if (suffix && suffix != i.suffix
c47b4d71 802 && current_templates->start->mnem_off != MN_bound)
1cb0ab18
JB
803 {
804 const insn_template *t;
805
806 for (t = current_templates->start; t < current_templates->end; ++t)
807 {
808 /* Operands haven't been swapped yet. */
809 unsigned int op = t->operands - 1 - this_operand;
810
811 /* Easy checks to skip templates which won't match anyway. */
812 if (this_operand >= t->operands || t->opcode_modifier.attsyntax)
813 continue;
814
815 switch (suffix)
816 {
817 case BYTE_MNEM_SUFFIX:
818 if (t->opcode_modifier.no_bsuf)
819 continue;
820 break;
821 case WORD_MNEM_SUFFIX:
822 if (t->opcode_modifier.no_wsuf)
823 continue;
824 break;
825 case LONG_MNEM_SUFFIX:
826 if (t->opcode_modifier.no_lsuf)
827 continue;
828 break;
829 case QWORD_MNEM_SUFFIX:
9db83a32 830 if (t->opcode_modifier.no_qsuf || !q_suffix_allowed (t))
1cb0ab18
JB
831 continue;
832 break;
833 case SHORT_MNEM_SUFFIX:
834 if (t->opcode_modifier.no_ssuf)
835 continue;
836 break;
1cb0ab18
JB
837 default:
838 abort ();
839 }
840
fcaf78fe
JB
841 /* We can skip templates with swappable operands here, as one
842 operand will be a register, which operand size can be
843 determined from. */
844 if (t->opcode_modifier.d)
845 continue;
846
1cb0ab18
JB
847 /* In a few cases suffixes are permitted, but we can nevertheless
848 derive that these aren't going to be needed. This is only of
fcaf78fe
JB
849 interest for insns using ModR/M. */
850 if (!t->opcode_modifier.modrm)
1cb0ab18
JB
851 break;
852
853 if (!t->operand_types[op].bitfield.baseindex)
854 continue;
855
856 switch (t->operand_types[op].bitfield.class)
857 {
858 case RegMMX:
859 case RegSIMD:
860 case RegMask:
861 continue;
862 }
863
864 break;
865 }
866
867 if (t == current_templates->end)
868 suffix = 0;
869 }
870
ee86248c
JB
871 if (!i.suffix)
872 i.suffix = suffix;
1cb0ab18 873 else if (suffix && i.suffix != suffix)
ee86248c
JB
874 {
875 as_bad (_("conflicting operand size modifiers"));
876 return 0;
877 }
878 }
879
880 /* Operands for jump/call need special consideration. */
0cfa3eb3
JB
881 if (current_templates->start->opcode_modifier.jump == JUMP
882 || current_templates->start->opcode_modifier.jump == JUMP_DWORD
883 || current_templates->start->opcode_modifier.jump == JUMP_INTERSEGMENT)
ee86248c 884 {
5b7c81bd 885 bool jumpabsolute = false;
6f2f06be 886
f09c1772
L
887 if (i.op[this_operand].regs
888 || intel_state.base
889 || intel_state.index
ee86248c 890 || intel_state.is_mem > 1)
5b7c81bd 891 jumpabsolute = true;
ee86248c
JB
892 else
893 switch (intel_state.op_modifier)
894 {
895 case O_near_ptr:
896 if (intel_state.seg)
5b7c81bd 897 jumpabsolute = true;
ee86248c
JB
898 else
899 intel_state.is_mem = 1;
900 break;
901 case O_far_ptr:
902 case O_absent:
903 if (!intel_state.seg)
904 {
905 intel_state.is_mem = 1;
906 if (intel_state.op_modifier == O_absent)
25303607
L
907 {
908 if (intel_state.is_indirect == 1)
5b7c81bd 909 jumpabsolute = true;
25303607
L
910 break;
911 }
ee86248c
JB
912 as_bad (_("cannot infer the segment part of the operand"));
913 return 0;
914 }
915 else if (S_GET_SEGMENT (intel_state.seg) == reg_section)
a4d3acd2
JB
916 {
917 jumpabsolute = true;
918 if (intel_state.op_modifier == O_far_ptr)
919 i.far_branch = true;
920 }
ee86248c
JB
921 else
922 {
923 i386_operand_type types;
924
925 if (i.imm_operands >= MAX_IMMEDIATE_OPERANDS)
926 {
927 as_bad (_("at most %d immediate operands are allowed"),
928 MAX_IMMEDIATE_OPERANDS);
929 return 0;
930 }
931 expP = &im_expressions[i.imm_operands++];
932 memset (expP, 0, sizeof(*expP));
933 expP->X_op = O_symbol;
934 expP->X_add_symbol = intel_state.seg;
935 i.op[this_operand].imms = expP;
936
937 resolve_expression (expP);
938 operand_type_set (&types, ~0);
939 if (!i386_finalize_immediate (S_GET_SEGMENT (intel_state.seg),
940 expP, types, operand_string))
941 return 0;
942 if (i.operands < MAX_OPERANDS)
943 {
944 this_operand = i.operands++;
945 i.types[this_operand].bitfield.unspecified = 1;
946 }
ee86248c
JB
947 intel_state.seg = NULL;
948 intel_state.is_mem = 0;
949 }
950 break;
951 default:
5b7c81bd 952 jumpabsolute = true;
ee86248c
JB
953 break;
954 }
6f2f06be
JB
955 if (jumpabsolute)
956 {
5b7c81bd 957 i.jumpabsolute = true;
6f2f06be
JB
958 intel_state.is_mem |= 1;
959 }
ee86248c
JB
960 }
961 else if (intel_state.seg)
962 intel_state.is_mem |= 1;
963
964 if (i.op[this_operand].regs)
965 {
966 i386_operand_type temp;
967
968 /* Register operand. */
c032bc4f
JB
969 if (intel_state.base || intel_state.index || intel_state.seg
970 || i.imm_bits[this_operand])
ee86248c
JB
971 {
972 as_bad (_("invalid operand"));
973 return 0;
974 }
975
976 temp = i.op[this_operand].regs->reg_type;
977 temp.bitfield.baseindex = 0;
f09c1772
L
978 i.types[this_operand] = operand_type_or (i.types[this_operand],
979 temp);
ee86248c
JB
980 i.types[this_operand].bitfield.unspecified = 0;
981 ++i.reg_operands;
cf665fee 982
7063667e
JB
983 if ((i.rounding.type != rc_none && !i.rounding.modifier
984 && temp.bitfield.class != Reg)
985 || rc_sae_modifier)
cf665fee
JB
986 {
987 unsigned int j;
988
989 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j)
990 if (i.rounding.type == RC_NamesTable[j].type)
991 break;
992 as_bad (_("`%s': misplaced `{%s}'"),
76d3f746 993 insn_name (current_templates->start), RC_NamesTable[j].name);
cf665fee
JB
994 return 0;
995 }
ee86248c 996 }
f09c1772
L
997 else if (intel_state.base
998 || intel_state.index
999 || intel_state.seg
ee86248c
JB
1000 || intel_state.is_mem)
1001 {
1002 /* Memory operand. */
c032bc4f
JB
1003 if (i.imm_bits[this_operand])
1004 {
1005 as_bad (_("invalid operand"));
1006 return 0;
1007 }
1008
04784e33 1009 if (i.mem_operands)
ee86248c 1010 {
313c53d1
L
1011 /* Handle
1012
1013 call 0x9090,0x90909090
1014 lcall 0x9090,0x90909090
1015 jmp 0x9090,0x90909090
1016 ljmp 0x9090,0x90909090
1017 */
1018
0cfa3eb3
JB
1019 if ((current_templates->start->opcode_modifier.jump == JUMP_INTERSEGMENT
1020 || current_templates->start->opcode_modifier.jump == JUMP_DWORD
1021 || current_templates->start->opcode_modifier.jump == JUMP)
313c53d1
L
1022 && this_operand == 1
1023 && intel_state.seg == NULL
1024 && i.mem_operands == 1
1025 && i.disp_operands == 1
1026 && intel_state.op_modifier == O_absent)
1027 {
1028 /* Try to process the first operand as immediate, */
1029 this_operand = 0;
1030 if (i386_finalize_immediate (exp_seg, i.op[0].imms,
1031 intel_state.reloc_types,
1032 NULL))
1033 {
1034 this_operand = 1;
1035 expP = &im_expressions[0];
1036 i.op[this_operand].imms = expP;
1037 *expP = exp;
1038
1039 /* Try to process the second operand as immediate, */
1040 if (i386_finalize_immediate (exp_seg, expP,
1041 intel_state.reloc_types,
1042 NULL))
1043 {
1044 i.mem_operands = 0;
1045 i.disp_operands = 0;
1046 i.imm_operands = 2;
c48dadc9 1047 i.flags[0] &= ~Operand_Mem;
313c53d1
L
1048 i.types[0].bitfield.disp16 = 0;
1049 i.types[0].bitfield.disp32 = 0;
313c53d1
L
1050 return 1;
1051 }
1052 }
1053 }
ee86248c
JB
1054 }
1055
2abc2bec
JB
1056 /* Swap base and index in 16-bit memory operands like
1057 [si+bx]. Since i386_index_check is also used in AT&T
1058 mode we have to do this here. */
1059 if (intel_state.base
1060 && intel_state.index
dc821c5f
JB
1061 && intel_state.base->reg_type.bitfield.word
1062 && intel_state.index->reg_type.bitfield.word
2abc2bec
JB
1063 && intel_state.base->reg_num >= 6
1064 && intel_state.index->reg_num < 6)
1065 {
1066 i.base_reg = intel_state.index;
1067 i.index_reg = intel_state.base;
1068 }
1069 else
1070 {
1071 i.base_reg = intel_state.base;
1072 i.index_reg = intel_state.index;
1073 }
1074
1075 if (i.base_reg || i.index_reg)
1076 i.types[this_operand].bitfield.baseindex = 1;
1077
ee86248c
JB
1078 expP = &disp_expressions[i.disp_operands];
1079 memcpy (expP, &exp, sizeof(exp));
1080 resolve_expression (expP);
1081
f09c1772
L
1082 if (expP->X_op != O_constant
1083 || expP->X_add_number
2abc2bec 1084 || !i.types[this_operand].bitfield.baseindex)
ee86248c
JB
1085 {
1086 i.op[this_operand].disps = expP;
1087 i.disp_operands++;
1088
2abc2bec
JB
1089 i386_addressing_mode ();
1090
ee86248c
JB
1091 if (flag_code == CODE_64BIT)
1092 {
a775efc8 1093 i.types[this_operand].bitfield.disp32 = 1;
ee86248c 1094 if (!i.prefix[ADDR_PREFIX])
a775efc8 1095 i.types[this_operand].bitfield.disp64 = 1;
ee86248c
JB
1096 }
1097 else if (!i.prefix[ADDR_PREFIX] ^ (flag_code == CODE_16BIT))
1098 i.types[this_operand].bitfield.disp32 = 1;
1099 else
1100 i.types[this_operand].bitfield.disp16 = 1;
1101
1102#if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)
1103 /*
1104 * exp_seg is used only for verification in
1105 * i386_finalize_displacement, and we can end up seeing reg_section
1106 * here - but we know we removed all registers from the expression
1107 * (or error-ed on any remaining ones) in i386_intel_simplify. I
1108 * consider the check in i386_finalize_displacement bogus anyway, in
1109 * particular because it doesn't allow for expr_section, so I'd
1110 * rather see that check (and the similar one in
1111 * i386_finalize_immediate) use SEG_NORMAL(), but not being an a.out
1112 * expert I can't really say whether that would have other bad side
1113 * effects.
1114 */
1115 if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1116 && exp_seg == reg_section)
1117 exp_seg = expP->X_op != O_constant ? undefined_section
1118 : absolute_section;
1119#endif
1120
1121 if (!i386_finalize_displacement (exp_seg, expP,
1122 intel_state.reloc_types,
1123 operand_string))
1124 return 0;
1125 }
1126
ee86248c
JB
1127 if (intel_state.seg)
1128 {
fd4e0347 1129 for (ret = check_none; ; ret = operand_check)
e21440ba
JB
1130 {
1131 expP = symbol_get_value_expression (intel_state.seg);
fd4e0347
JB
1132 if (expP->X_op != O_full_ptr
1133 || symbol_get_value_expression (expP->X_op_symbol)->X_op
1134 != O_register)
e21440ba
JB
1135 break;
1136 intel_state.seg = expP->X_add_symbol;
1137 }
0398aac5 1138 if (expP->X_op != O_register)
ee86248c
JB
1139 {
1140 as_bad (_("segment register name expected"));
1141 return 0;
1142 }
00cee14f 1143 if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
ee86248c
JB
1144 {
1145 as_bad (_("invalid use of register"));
1146 return 0;
1147 }
fd4e0347
JB
1148 switch (ret)
1149 {
1150 case check_error:
1151 as_bad (_("redundant segment overrides"));
1152 return 0;
1153 case check_warning:
1154 as_warn (_("redundant segment overrides"));
1155 break;
1156 }
5e042380
JB
1157 if (i386_regtab[expP->X_add_number].reg_num == RegFlat)
1158 i.seg[i.mem_operands] = NULL;
1159 else
1160 i.seg[i.mem_operands] = &i386_regtab[expP->X_add_number];
ee86248c
JB
1161 }
1162
ee86248c
JB
1163 if (!i386_index_check (operand_string))
1164 return 0;
1165
c48dadc9 1166 i.flags[this_operand] |= Operand_Mem;
ee86248c
JB
1167 ++i.mem_operands;
1168 }
1169 else
1170 {
1171 /* Immediate. */
1172 if (i.imm_operands >= MAX_IMMEDIATE_OPERANDS)
1173 {
1174 as_bad (_("at most %d immediate operands are allowed"),
1175 MAX_IMMEDIATE_OPERANDS);
1176 return 0;
1177 }
1178
1179 expP = &im_expressions[i.imm_operands++];
1180 i.op[this_operand].imms = expP;
1181 *expP = exp;
1182
1183 return i386_finalize_immediate (exp_seg, expP, intel_state.reloc_types,
1184 operand_string);
1185 }
1186
1187 return 1;
1188}