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ee86248c 1/* tc-i386.c -- Assemble Intel syntax code for ix86/x86-64
d87bef3a 2 Copyright (C) 2009-2023 Free Software Foundation, Inc.
ee86248c
JB
3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
20
21static struct
22 {
23 operatorT op_modifier; /* Operand modifier. */
24 int is_mem; /* 1 if operand is memory reference. */
25303607 25 int is_indirect; /* 1 if operand is indirect reference. */
6cee4cda 26 int has_offset; /* 1 if operand has offset. */
ee86248c
JB
27 unsigned int in_offset; /* >=1 if processing operand of offset. */
28 unsigned int in_bracket; /* >=1 if processing operand in brackets. */
33eaf5de 29 unsigned int in_scale; /* >=1 if processing multiplication operand
ee86248c
JB
30 * in brackets. */
31 i386_operand_type reloc_types; /* Value obtained from lex_got(). */
32 const reg_entry *base; /* Base register (if any). */
33 const reg_entry *index; /* Index register (if any). */
34 offsetT scale_factor; /* Accumulated scale factor. */
35 symbolS *seg;
36 }
37intel_state;
38
39/* offset X_add_symbol */
40#define O_offset O_md32
7ac3eb25
L
41/* offset X_add_symbol */
42#define O_short O_md31
43/* near ptr X_add_symbol */
44#define O_near_ptr O_md30
45/* far ptr X_add_symbol */
46#define O_far_ptr O_md29
ee86248c 47/* byte ptr X_add_symbol */
7ac3eb25 48#define O_byte_ptr O_md28
ee86248c 49/* word ptr X_add_symbol */
7ac3eb25 50#define O_word_ptr O_md27
ee86248c 51/* dword ptr X_add_symbol */
7ac3eb25 52#define O_dword_ptr O_md26
ee86248c 53/* qword ptr X_add_symbol */
7ac3eb25 54#define O_qword_ptr O_md25
f2f5811f
JB
55/* mmword ptr X_add_symbol */
56#define O_mmword_ptr O_qword_ptr
ee86248c 57/* fword ptr X_add_symbol */
7456d03d 58#define O_fword_ptr O_md24
ee86248c 59/* tbyte ptr X_add_symbol */
7456d03d
JB
60#define O_tbyte_ptr O_md23
61/* oword ptr X_add_symbol */
62#define O_oword_ptr O_md22
ee86248c 63/* xmmword ptr X_add_symbol */
7456d03d 64#define O_xmmword_ptr O_oword_ptr
ee86248c 65/* ymmword ptr X_add_symbol */
7456d03d 66#define O_ymmword_ptr O_md21
43234a1e 67/* zmmword ptr X_add_symbol */
7456d03d 68#define O_zmmword_ptr O_md20
ee86248c
JB
69
70static struct
71 {
72 const char *name;
1e9cc1c2 73 operatorT op;
ee86248c
JB
74 unsigned int operands;
75 }
76const i386_operators[] =
77 {
78 { "and", O_bit_and, 2 },
79 { "eq", O_eq, 2 },
80 { "ge", O_ge, 2 },
81 { "gt", O_gt, 2 },
82 { "le", O_le, 2 },
83 { "lt", O_lt, 2 },
84 { "mod", O_modulus, 2 },
85 { "ne", O_ne, 2 },
86 { "not", O_bit_not, 1 },
87 { "offset", O_offset, 1 },
88 { "or", O_bit_inclusive_or, 2 },
89 { "shl", O_left_shift, 2 },
90 { "short", O_short, 1 },
91 { "shr", O_right_shift, 2 },
92 { "xor", O_bit_exclusive_or, 2 },
93 { NULL, O_illegal, 0 }
94 };
95
96static struct
97 {
98 const char *name;
1e9cc1c2 99 operatorT op;
ee86248c
JB
100 unsigned short sz[3];
101 }
102const i386_types[] =
103 {
104#define I386_TYPE(t, n) { #t, O_##t##_ptr, { n, n, n } }
105 I386_TYPE(byte, 1),
106 I386_TYPE(word, 2),
107 I386_TYPE(dword, 4),
108 I386_TYPE(fword, 6),
109 I386_TYPE(qword, 8),
f2f5811f 110 I386_TYPE(mmword, 8),
ee86248c
JB
111 I386_TYPE(tbyte, 10),
112 I386_TYPE(oword, 16),
113 I386_TYPE(xmmword, 16),
114 I386_TYPE(ymmword, 32),
43234a1e 115 I386_TYPE(zmmword, 64),
ee86248c
JB
116#undef I386_TYPE
117 { "near", O_near_ptr, { 0xff04, 0xff02, 0xff08 } },
118 { "far", O_far_ptr, { 0xff06, 0xff05, 0xff06 } },
119 { NULL, O_illegal, { 0, 0, 0 } }
120 };
121
122operatorT i386_operator (const char *name, unsigned int operands, char *pc)
123{
124 unsigned int j;
125
b3983e5f
JB
126#ifdef SVR4_COMMENT_CHARS
127 if (!name && operands == 2 && *input_line_pointer == '\\')
128 switch (input_line_pointer[1])
129 {
130 case '/': input_line_pointer += 2; return O_divide;
131 case '%': input_line_pointer += 2; return O_modulus;
132 case '*': input_line_pointer += 2; return O_multiply;
133 }
134#endif
135
ee86248c
JB
136 if (!intel_syntax)
137 return O_absent;
138
139 if (!name)
140 {
141 if (operands != 2)
142 return O_illegal;
143 switch (*input_line_pointer)
144 {
145 case ':':
146 ++input_line_pointer;
147 return O_full_ptr;
148 case '[':
149 ++input_line_pointer;
150 return O_index;
151 case '@':
152 if (this_operand >= 0 && i.reloc[this_operand] == NO_RELOC)
153 {
154 int adjust = 0;
155 char *gotfree_input_line = lex_got (&i.reloc[this_operand],
156 &adjust,
d258b828 157 &intel_state.reloc_types);
ee86248c
JB
158
159 if (!gotfree_input_line)
160 break;
161 free (gotfree_input_line);
162 *input_line_pointer++ = '+';
163 memset (input_line_pointer, '0', adjust - 1);
164 input_line_pointer[adjust - 1] = ' ';
165 return O_add;
166 }
167 break;
168 }
169 return O_illegal;
170 }
171
172 for (j = 0; i386_operators[j].name; ++j)
91d6fa6a 173 if (strcasecmp (i386_operators[j].name, name) == 0)
ee86248c
JB
174 {
175 if (i386_operators[j].operands
176 && i386_operators[j].operands != operands)
177 return O_illegal;
1e9cc1c2 178 return i386_operators[j].op;
ee86248c
JB
179 }
180
181 for (j = 0; i386_types[j].name; ++j)
91d6fa6a 182 if (strcasecmp (i386_types[j].name, name) == 0)
ee86248c 183 break;
d02603dc 184
ee86248c
JB
185 if (i386_types[j].name && *pc == ' ')
186 {
d02603dc
NC
187 char *pname;
188 char c;
189
190 ++input_line_pointer;
191 c = get_symbol_name (&pname);
ee86248c 192
91d6fa6a 193 if (strcasecmp (pname, "ptr") == 0)
ee86248c 194 {
d02603dc 195 /* FIXME: What if c == '"' ? */
91d6fa6a 196 pname[-1] = *pc;
ee86248c
JB
197 *pc = c;
198 if (intel_syntax > 0 || operands != 1)
199 return O_illegal;
1e9cc1c2 200 return i386_types[j].op;
ee86248c
JB
201 }
202
a5748e0d
JB
203 if (strcasecmp (pname, "bcst") == 0)
204 {
205 /* FIXME: Again, what if c == '"' ? */
206 pname[-1] = *pc;
207 *pc = c;
208 if (intel_syntax > 0 || operands != 1
209 || i386_types[j].sz[0] > 8
210 || (i386_types[j].sz[0] & (i386_types[j].sz[0] - 1)))
211 return O_illegal;
212 if (!i.broadcast.bytes && !i.broadcast.type)
213 {
214 i.broadcast.bytes = i386_types[j].sz[0];
215 i.broadcast.operand = this_operand;
216 }
217 return i386_types[j].op;
218 }
219
d02603dc 220 (void) restore_line_pointer (c);
91d6fa6a 221 input_line_pointer = pname - 1;
ee86248c
JB
222 }
223
224 return O_absent;
225}
226
227static int i386_intel_parse_name (const char *name, expressionS *e)
228{
91d6fa6a 229 unsigned int j;
ee86248c 230
b7adb16d
JB
231 if (! strcmp (name, "$"))
232 {
233 current_location (e);
234 return 1;
235 }
236
91d6fa6a
NC
237 for (j = 0; i386_types[j].name; ++j)
238 if (strcasecmp(i386_types[j].name, name) == 0)
ee86248c
JB
239 {
240 e->X_op = O_constant;
91d6fa6a 241 e->X_add_number = i386_types[j].sz[flag_code];
ee86248c
JB
242 e->X_add_symbol = NULL;
243 e->X_op_symbol = NULL;
244 return 1;
245 }
246
247 return 0;
248}
249
91d6fa6a 250static INLINE int i386_intel_check (const reg_entry *rreg,
ee86248c 251 const reg_entry *base,
91d6fa6a 252 const reg_entry *iindex)
ee86248c 253{
f09c1772
L
254 if ((this_operand >= 0
255 && rreg != i.op[this_operand].regs)
256 || base != intel_state.base
257 || iindex != intel_state.index)
ee86248c
JB
258 {
259 as_bad (_("invalid use of register"));
260 return 0;
261 }
262 return 1;
263}
264
265static INLINE void i386_intel_fold (expressionS *e, symbolS *sym)
266{
27dee630 267 expressionS *exp = symbol_get_value_expression (sym);
ee86248c
JB
268 if (S_GET_SEGMENT (sym) == absolute_section)
269 {
270 offsetT val = e->X_add_number;
271
27dee630 272 *e = *exp;
ee86248c
JB
273 e->X_add_number += val;
274 }
275 else
276 {
27dee630
L
277 if (exp->X_op == O_symbol
278 && strcmp (S_GET_NAME (exp->X_add_symbol),
279 GLOBAL_OFFSET_TABLE_NAME) == 0)
280 sym = exp->X_add_symbol;
ee86248c
JB
281 e->X_add_symbol = sym;
282 e->X_op_symbol = NULL;
283 e->X_op = O_symbol;
284 }
285}
286
3c7b9c2c
L
287static int
288i386_intel_simplify_register (expressionS *e)
289{
290 int reg_num;
291
292 if (this_operand < 0 || intel_state.in_offset)
293 {
294 as_bad (_("invalid use of register"));
295 return 0;
296 }
297
298 if (e->X_op == O_register)
299 reg_num = e->X_add_number;
300 else
301 reg_num = e->X_md - 1;
302
35015cd1
NC
303 if (reg_num < 0 || reg_num >= (int) i386_regtab_size)
304 {
305 as_bad (_("invalid register number"));
306 return 0;
307 }
308
4faaa10f
JB
309 if (!check_register (&i386_regtab[reg_num]))
310 {
311 as_bad (_("register '%s%s' cannot be used here"),
312 register_prefix, i386_regtab[reg_num].reg_name);
313 return 0;
314 }
315
3c7b9c2c
L
316 if (!intel_state.in_bracket)
317 {
318 if (i.op[this_operand].regs)
319 {
320 as_bad (_("invalid use of register"));
321 return 0;
322 }
00cee14f 323 if (i386_regtab[reg_num].reg_type.bitfield.class == SReg
3c7b9c2c
L
324 && i386_regtab[reg_num].reg_num == RegFlat)
325 {
326 as_bad (_("invalid use of pseudo-register"));
327 return 0;
328 }
329 i.op[this_operand].regs = i386_regtab + reg_num;
330 }
9e2934f7 331 else if (!intel_state.index
1b54b8d7
JB
332 && (i386_regtab[reg_num].reg_type.bitfield.xmmword
333 || i386_regtab[reg_num].reg_type.bitfield.ymmword
334 || i386_regtab[reg_num].reg_type.bitfield.zmmword
e968fc9b 335 || i386_regtab[reg_num].reg_num == RegIZ))
9e2934f7 336 intel_state.index = i386_regtab + reg_num;
3c7b9c2c
L
337 else if (!intel_state.base && !intel_state.in_scale)
338 intel_state.base = i386_regtab + reg_num;
339 else if (!intel_state.index)
9e2934f7 340 {
a152332d
JB
341 const insn_template *t = current_templates->start;
342
9e2934f7 343 if (intel_state.in_scale
c47b4d71
JB
344 || i386_regtab[reg_num].reg_type.bitfield.baseindex
345 || t->mnem_off == MN_bndmk
346 || t->mnem_off == MN_bndldx
347 || t->mnem_off == MN_bndstx)
9e2934f7
JB
348 intel_state.index = i386_regtab + reg_num;
349 else
350 {
351 /* Convert base to index and make ESP/RSP the base. */
352 intel_state.index = intel_state.base;
353 intel_state.base = i386_regtab + reg_num;
354 }
355 }
3c7b9c2c
L
356 else
357 {
358 /* esp is invalid as index */
34684862 359 intel_state.index = reg_eax + ESP_REG_NUM;
3c7b9c2c
L
360 }
361 return 2;
362}
363
ee86248c
JB
364static int i386_intel_simplify (expressionS *);
365
366static INLINE int i386_intel_simplify_symbol(symbolS *sym)
367{
368 int ret = i386_intel_simplify (symbol_get_value_expression (sym));
369
370 if (ret == 2)
371 {
372 S_SET_SEGMENT(sym, absolute_section);
373 ret = 1;
374 }
375 return ret;
376}
377
378static int i386_intel_simplify (expressionS *e)
379{
f09c1772
L
380 const reg_entry *the_reg = (this_operand >= 0
381 ? i.op[this_operand].regs : NULL);
ee86248c 382 const reg_entry *base = intel_state.base;
91d6fa6a 383 const reg_entry *state_index = intel_state.index;
ee86248c
JB
384 int ret;
385
386 if (!intel_syntax)
387 return 1;
388
389 switch (e->X_op)
390 {
391 case O_index:
392 if (e->X_add_symbol)
393 {
394 if (!i386_intel_simplify_symbol (e->X_add_symbol)
f09c1772
L
395 || !i386_intel_check(the_reg, intel_state.base,
396 intel_state.index))
5bb3703f 397 return 0;
ee86248c
JB
398 }
399 if (!intel_state.in_offset)
400 ++intel_state.in_bracket;
401 ret = i386_intel_simplify_symbol (e->X_op_symbol);
402 if (!intel_state.in_offset)
403 --intel_state.in_bracket;
404 if (!ret)
405 return 0;
406 if (e->X_add_symbol)
407 e->X_op = O_add;
408 else
409 i386_intel_fold (e, e->X_op_symbol);
410 break;
411
412 case O_offset:
6cee4cda 413 intel_state.has_offset = 1;
ee86248c
JB
414 ++intel_state.in_offset;
415 ret = i386_intel_simplify_symbol (e->X_add_symbol);
416 --intel_state.in_offset;
91d6fa6a 417 if (!ret || !i386_intel_check(the_reg, base, state_index))
ee86248c
JB
418 return 0;
419 i386_intel_fold (e, e->X_add_symbol);
420 return ret;
421
422 case O_byte_ptr:
423 case O_word_ptr:
424 case O_dword_ptr:
425 case O_fword_ptr:
f2f5811f 426 case O_qword_ptr: /* O_mmword_ptr */
ee86248c 427 case O_tbyte_ptr:
7456d03d 428 case O_oword_ptr: /* O_xmmword_ptr */
ee86248c 429 case O_ymmword_ptr:
43234a1e 430 case O_zmmword_ptr:
ee86248c
JB
431 case O_near_ptr:
432 case O_far_ptr:
433 if (intel_state.op_modifier == O_absent)
434 intel_state.op_modifier = e->X_op;
435 /* FALLTHROUGH */
436 case O_short:
f09c1772
L
437 if (symbol_get_value_expression (e->X_add_symbol)->X_op
438 == O_register)
ee86248c
JB
439 {
440 as_bad (_("invalid use of register"));
441 return 0;
442 }
443 if (!i386_intel_simplify_symbol (e->X_add_symbol))
444 return 0;
445 i386_intel_fold (e, e->X_add_symbol);
446 break;
447
448 case O_full_ptr:
f09c1772
L
449 if (symbol_get_value_expression (e->X_op_symbol)->X_op
450 == O_register)
ee86248c
JB
451 {
452 as_bad (_("invalid use of register"));
453 return 0;
454 }
455 if (!i386_intel_simplify_symbol (e->X_op_symbol)
f09c1772
L
456 || !i386_intel_check(the_reg, intel_state.base,
457 intel_state.index))
ee86248c
JB
458 return 0;
459 if (!intel_state.in_offset)
fd4e0347
JB
460 {
461 if (!intel_state.seg)
462 intel_state.seg = e->X_add_symbol;
463 else
464 {
465 expressionS exp;
466
467 exp.X_op = O_full_ptr;
468 exp.X_add_symbol = e->X_add_symbol;
469 exp.X_op_symbol = intel_state.seg;
470 intel_state.seg = make_expr_symbol (&exp);
471 }
472 }
ee86248c
JB
473 i386_intel_fold (e, e->X_op_symbol);
474 break;
475
ee86248c
JB
476 case O_multiply:
477 if (this_operand >= 0 && intel_state.in_bracket)
478 {
479 expressionS *scale = NULL;
c2a5914e 480 int has_index = (intel_state.index != NULL);
ee86248c
JB
481
482 if (!intel_state.in_scale++)
483 intel_state.scale_factor = 1;
484
485 ret = i386_intel_simplify_symbol (e->X_add_symbol);
c2a5914e 486 if (ret && !has_index && intel_state.index)
ee86248c
JB
487 scale = symbol_get_value_expression (e->X_op_symbol);
488
489 if (ret)
490 ret = i386_intel_simplify_symbol (e->X_op_symbol);
c2a5914e 491 if (ret && !scale && !has_index && intel_state.index)
ee86248c
JB
492 scale = symbol_get_value_expression (e->X_add_symbol);
493
c2a5914e 494 if (ret && scale)
ee86248c
JB
495 {
496 resolve_expression (scale);
497 if (scale->X_op != O_constant
dc821c5f 498 || intel_state.index->reg_type.bitfield.word)
ee86248c
JB
499 scale->X_add_number = 0;
500 intel_state.scale_factor *= scale->X_add_number;
501 }
502
503 --intel_state.in_scale;
504 if (!ret)
505 return 0;
506
507 if (!intel_state.in_scale)
508 switch (intel_state.scale_factor)
509 {
510 case 1:
511 i.log2_scale_factor = 0;
512 break;
513 case 2:
514 i.log2_scale_factor = 1;
515 break;
516 case 4:
517 i.log2_scale_factor = 2;
518 break;
519 case 8:
520 i.log2_scale_factor = 3;
521 break;
522 default:
523 /* esp is invalid as index */
34684862 524 intel_state.index = reg_eax + ESP_REG_NUM;
ee86248c
JB
525 break;
526 }
527
528 break;
529 }
92b4f90c 530 goto fallthrough;
3c7b9c2c
L
531
532 case O_register:
533 ret = i386_intel_simplify_register (e);
534 if (ret == 2)
535 {
536 gas_assert (e->X_add_number < (unsigned short) -1);
537 e->X_md = (unsigned short) e->X_add_number + 1;
538 e->X_op = O_constant;
539 e->X_add_number = 0;
540 }
541 return ret;
542
543 case O_constant:
544 if (e->X_md)
545 return i386_intel_simplify_register (e);
546
ee86248c
JB
547 /* FALLTHROUGH */
548 default:
dc1e8a47 549 fallthrough:
f09c1772
L
550 if (e->X_add_symbol
551 && !i386_intel_simplify_symbol (e->X_add_symbol))
ee86248c 552 return 0;
64d23078
JB
553 if (!the_reg && this_operand >= 0
554 && e->X_op == O_symbol && !e->X_add_number)
555 the_reg = i.op[this_operand].regs;
ee86248c
JB
556 if (e->X_op == O_add || e->X_op == O_subtract)
557 {
558 base = intel_state.base;
91d6fa6a 559 state_index = intel_state.index;
ee86248c 560 }
91d6fa6a 561 if (!i386_intel_check (the_reg, base, state_index)
f09c1772
L
562 || (e->X_op_symbol
563 && !i386_intel_simplify_symbol (e->X_op_symbol))
91d6fa6a 564 || !i386_intel_check (the_reg,
f09c1772
L
565 (e->X_op != O_add
566 ? base : intel_state.base),
567 (e->X_op != O_add
568 ? state_index : intel_state.index)))
ee86248c
JB
569 return 0;
570 break;
571 }
572
f09c1772
L
573 if (this_operand >= 0
574 && e->X_op == O_symbol
575 && !intel_state.in_offset)
ee86248c
JB
576 {
577 segT seg = S_GET_SEGMENT (e->X_add_symbol);
578
579 if (seg != absolute_section
580 && seg != reg_section
581 && seg != expr_section)
582 intel_state.is_mem |= 2 - !intel_state.in_bracket;
583 }
584
585 return 1;
586}
587
588int i386_need_index_operator (void)
589{
590 return intel_syntax < 0;
591}
592
593static int
594i386_intel_operand (char *operand_string, int got_a_float)
595{
596 char *saved_input_line_pointer, *buf;
597 segT exp_seg;
598 expressionS exp, *expP;
599 char suffix = 0;
7063667e 600 bool rc_sae_modifier = i.rounding.type != rc_none && i.rounding.modifier;
ee86248c
JB
601 int ret;
602
43234a1e
L
603 /* Handle vector immediates. */
604 if (RC_SAE_immediate (operand_string))
cf665fee
JB
605 {
606 if (i.imm_operands)
607 {
608 as_bad (_("`%s': RC/SAE operand must precede immediate operands"),
76d3f746 609 insn_name (current_templates->start));
cf665fee
JB
610 return 0;
611 }
612
613 return 1;
614 }
43234a1e 615
ee86248c
JB
616 /* Initialize state structure. */
617 intel_state.op_modifier = O_absent;
618 intel_state.is_mem = 0;
25303607 619 intel_state.is_indirect = 0;
1acf546e 620 intel_state.has_offset = 0;
ee86248c
JB
621 intel_state.base = NULL;
622 intel_state.index = NULL;
623 intel_state.seg = NULL;
624 operand_type_set (&intel_state.reloc_types, ~0);
9c2799c2
NC
625 gas_assert (!intel_state.in_offset);
626 gas_assert (!intel_state.in_bracket);
627 gas_assert (!intel_state.in_scale);
ee86248c
JB
628
629 saved_input_line_pointer = input_line_pointer;
630 input_line_pointer = buf = xstrdup (operand_string);
631
632 intel_syntax = -1;
633 memset (&exp, 0, sizeof(exp));
634 exp_seg = expression (&exp);
635 ret = i386_intel_simplify (&exp);
636 intel_syntax = 1;
637
638 SKIP_WHITESPACE ();
43234a1e
L
639
640 /* Handle vector operations. */
641 if (*input_line_pointer == '{')
642 {
f70c6814 643 char *end = check_VecOperations (input_line_pointer);
43234a1e
L
644 if (end)
645 input_line_pointer = end;
646 else
647 ret = 0;
648 }
649
ee86248c
JB
650 if (!is_end_of_line[(unsigned char) *input_line_pointer])
651 {
38bf5113
JB
652 if (ret)
653 as_bad (_("junk `%s' after expression"), input_line_pointer);
ee86248c
JB
654 ret = 0;
655 }
656 else if (exp.X_op == O_illegal || exp.X_op == O_absent)
657 {
38bf5113
JB
658 if (ret)
659 as_bad (_("invalid expression"));
ee86248c
JB
660 ret = 0;
661 }
6cee4cda
L
662 else if (!intel_state.has_offset
663 && input_line_pointer > buf
664 && *(input_line_pointer - 1) == ']')
25303607
L
665 {
666 intel_state.is_mem |= 1;
667 intel_state.is_indirect = 1;
668 }
ee86248c
JB
669
670 input_line_pointer = saved_input_line_pointer;
671 free (buf);
672
9c2799c2
NC
673 gas_assert (!intel_state.in_offset);
674 gas_assert (!intel_state.in_bracket);
675 gas_assert (!intel_state.in_scale);
ee86248c
JB
676
677 if (!ret)
678 return 0;
679
680 if (intel_state.op_modifier != O_absent
c47b4d71 681 && current_templates->start->mnem_off != MN_lea)
ee86248c
JB
682 {
683 i.types[this_operand].bitfield.unspecified = 0;
684
685 switch (intel_state.op_modifier)
686 {
687 case O_byte_ptr:
688 i.types[this_operand].bitfield.byte = 1;
689 suffix = BYTE_MNEM_SUFFIX;
690 break;
691
692 case O_word_ptr:
693 i.types[this_operand].bitfield.word = 1;
37404387 694 if (got_a_float == 2) /* "fi..." */
ee86248c 695 suffix = SHORT_MNEM_SUFFIX;
c47b4d71 696 else if (current_templates->start->mnem_off != MN_lar
5eeeafe0
JB
697 && current_templates->start->mnem_off != MN_lsl
698 && current_templates->start->mnem_off != MN_arpl)
ee86248c
JB
699 suffix = WORD_MNEM_SUFFIX;
700 break;
701
702 case O_dword_ptr:
703 i.types[this_operand].bitfield.dword = 1;
76d3f746
JB
704 if ((insn_name (current_templates->start)[0] == 'l'
705 && insn_name (current_templates->start)[2] == 's'
706 && insn_name (current_templates->start)[3] == 0)
c47b4d71 707 || current_templates->start->mnem_off == MN_bound)
ee86248c 708 suffix = WORD_MNEM_SUFFIX;
d488367a 709 else if (flag_code != CODE_32BIT
0cfa3eb3
JB
710 && (current_templates->start->opcode_modifier.jump == JUMP
711 || current_templates->start->opcode_modifier.jump
712 == JUMP_DWORD))
a4d3acd2
JB
713 {
714 i.far_branch = true;
715 suffix = WORD_MNEM_SUFFIX;
716 }
ee86248c
JB
717 else if (got_a_float == 1) /* "f..." */
718 suffix = SHORT_MNEM_SUFFIX;
719 else
720 suffix = LONG_MNEM_SUFFIX;
721 break;
722
723 case O_fword_ptr:
724 i.types[this_operand].bitfield.fword = 1;
c47b4d71
JB
725 if (current_templates->start->mnem_off == MN_les
726 || current_templates->start->mnem_off == MN_lds
727 || current_templates->start->mnem_off == MN_lss
728 || current_templates->start->mnem_off == MN_lfs
729 || current_templates->start->mnem_off == MN_lgs)
ee86248c
JB
730 suffix = LONG_MNEM_SUFFIX;
731 else if (!got_a_float)
732 {
733 if (flag_code == CODE_16BIT)
734 add_prefix (DATA_PREFIX_OPCODE);
a4d3acd2 735 i.far_branch = true;
ee86248c 736 }
ee86248c
JB
737 break;
738
f2f5811f 739 case O_qword_ptr: /* O_mmword_ptr */
ee86248c 740 i.types[this_operand].bitfield.qword = 1;
c47b4d71 741 if (current_templates->start->mnem_off == MN_bound
ee86248c
JB
742 || got_a_float == 1) /* "f..." */
743 suffix = LONG_MNEM_SUFFIX;
744 else
745 suffix = QWORD_MNEM_SUFFIX;
746 break;
747
748 case O_tbyte_ptr:
749 i.types[this_operand].bitfield.tbyte = 1;
f210f0a0
JB
750 if (got_a_float)
751 break;
752 if (flag_code == CODE_64BIT
753 && (current_templates->start->operand_types[0].bitfield.fword
754 || current_templates->start->operand_types[0].bitfield.tbyte
755 || current_templates->start->opcode_modifier.jump == JUMP_DWORD
756 || current_templates->start->opcode_modifier.jump == JUMP))
5990e377 757 suffix = QWORD_MNEM_SUFFIX; /* l[fgs]s, [ls][gi]dt, call, jmp */
ee86248c 758 else
a8f4f6b9 759 i.types[this_operand].bitfield.byte = 1; /* cause an error */
ee86248c
JB
760 break;
761
7456d03d 762 case O_oword_ptr: /* O_xmmword_ptr */
ee86248c 763 i.types[this_operand].bitfield.xmmword = 1;
ee86248c
JB
764 break;
765
766 case O_ymmword_ptr:
767 i.types[this_operand].bitfield.ymmword = 1;
ee86248c
JB
768 break;
769
43234a1e
L
770 case O_zmmword_ptr:
771 i.types[this_operand].bitfield.zmmword = 1;
43234a1e
L
772 break;
773
ee86248c 774 case O_far_ptr:
a4d3acd2 775 i.far_branch = true;
ee86248c
JB
776 /* FALLTHROUGH */
777 case O_near_ptr:
0cfa3eb3
JB
778 if (current_templates->start->opcode_modifier.jump != JUMP
779 && current_templates->start->opcode_modifier.jump != JUMP_DWORD)
164d49cb
JB
780 {
781 /* cause an error */
782 i.types[this_operand].bitfield.byte = 1;
783 i.types[this_operand].bitfield.tbyte = 1;
784 suffix = i.suffix;
785 }
ee86248c
JB
786 break;
787
788 default:
789 BAD_CASE (intel_state.op_modifier);
790 break;
791 }
792
1cb0ab18
JB
793 /* Now check whether we actually want to infer an AT&T-like suffix.
794 We really only need to do this when operand size determination (incl.
795 REX.W) is going to be derived from it. For this we check whether the
796 given suffix is valid for any of the candidate templates. */
797 if (suffix && suffix != i.suffix
c47b4d71 798 && current_templates->start->mnem_off != MN_bound)
1cb0ab18
JB
799 {
800 const insn_template *t;
801
802 for (t = current_templates->start; t < current_templates->end; ++t)
803 {
804 /* Operands haven't been swapped yet. */
805 unsigned int op = t->operands - 1 - this_operand;
806
807 /* Easy checks to skip templates which won't match anyway. */
808 if (this_operand >= t->operands || t->opcode_modifier.attsyntax)
809 continue;
810
811 switch (suffix)
812 {
813 case BYTE_MNEM_SUFFIX:
814 if (t->opcode_modifier.no_bsuf)
815 continue;
816 break;
817 case WORD_MNEM_SUFFIX:
818 if (t->opcode_modifier.no_wsuf)
819 continue;
820 break;
821 case LONG_MNEM_SUFFIX:
822 if (t->opcode_modifier.no_lsuf)
823 continue;
824 break;
825 case QWORD_MNEM_SUFFIX:
9db83a32 826 if (t->opcode_modifier.no_qsuf || !q_suffix_allowed (t))
1cb0ab18
JB
827 continue;
828 break;
829 case SHORT_MNEM_SUFFIX:
830 if (t->opcode_modifier.no_ssuf)
831 continue;
832 break;
1cb0ab18
JB
833 default:
834 abort ();
835 }
836
fcaf78fe
JB
837 /* We can skip templates with swappable operands here, as one
838 operand will be a register, which operand size can be
839 determined from. */
840 if (t->opcode_modifier.d)
841 continue;
842
1cb0ab18
JB
843 /* In a few cases suffixes are permitted, but we can nevertheless
844 derive that these aren't going to be needed. This is only of
fcaf78fe
JB
845 interest for insns using ModR/M. */
846 if (!t->opcode_modifier.modrm)
1cb0ab18
JB
847 break;
848
849 if (!t->operand_types[op].bitfield.baseindex)
850 continue;
851
852 switch (t->operand_types[op].bitfield.class)
853 {
854 case RegMMX:
855 case RegSIMD:
856 case RegMask:
857 continue;
858 }
859
860 break;
861 }
862
863 if (t == current_templates->end)
864 suffix = 0;
865 }
866
ee86248c
JB
867 if (!i.suffix)
868 i.suffix = suffix;
1cb0ab18 869 else if (suffix && i.suffix != suffix)
ee86248c
JB
870 {
871 as_bad (_("conflicting operand size modifiers"));
872 return 0;
873 }
874 }
875
876 /* Operands for jump/call need special consideration. */
0cfa3eb3
JB
877 if (current_templates->start->opcode_modifier.jump == JUMP
878 || current_templates->start->opcode_modifier.jump == JUMP_DWORD
879 || current_templates->start->opcode_modifier.jump == JUMP_INTERSEGMENT)
ee86248c 880 {
5b7c81bd 881 bool jumpabsolute = false;
6f2f06be 882
f09c1772
L
883 if (i.op[this_operand].regs
884 || intel_state.base
885 || intel_state.index
ee86248c 886 || intel_state.is_mem > 1)
5b7c81bd 887 jumpabsolute = true;
ee86248c
JB
888 else
889 switch (intel_state.op_modifier)
890 {
891 case O_near_ptr:
892 if (intel_state.seg)
5b7c81bd 893 jumpabsolute = true;
ee86248c
JB
894 else
895 intel_state.is_mem = 1;
896 break;
897 case O_far_ptr:
898 case O_absent:
899 if (!intel_state.seg)
900 {
901 intel_state.is_mem = 1;
902 if (intel_state.op_modifier == O_absent)
25303607
L
903 {
904 if (intel_state.is_indirect == 1)
5b7c81bd 905 jumpabsolute = true;
25303607
L
906 break;
907 }
ee86248c
JB
908 as_bad (_("cannot infer the segment part of the operand"));
909 return 0;
910 }
911 else if (S_GET_SEGMENT (intel_state.seg) == reg_section)
a4d3acd2
JB
912 {
913 jumpabsolute = true;
914 if (intel_state.op_modifier == O_far_ptr)
915 i.far_branch = true;
916 }
ee86248c
JB
917 else
918 {
919 i386_operand_type types;
920
921 if (i.imm_operands >= MAX_IMMEDIATE_OPERANDS)
922 {
923 as_bad (_("at most %d immediate operands are allowed"),
924 MAX_IMMEDIATE_OPERANDS);
925 return 0;
926 }
927 expP = &im_expressions[i.imm_operands++];
928 memset (expP, 0, sizeof(*expP));
929 expP->X_op = O_symbol;
930 expP->X_add_symbol = intel_state.seg;
931 i.op[this_operand].imms = expP;
932
933 resolve_expression (expP);
934 operand_type_set (&types, ~0);
935 if (!i386_finalize_immediate (S_GET_SEGMENT (intel_state.seg),
936 expP, types, operand_string))
937 return 0;
938 if (i.operands < MAX_OPERANDS)
939 {
940 this_operand = i.operands++;
941 i.types[this_operand].bitfield.unspecified = 1;
942 }
ee86248c
JB
943 intel_state.seg = NULL;
944 intel_state.is_mem = 0;
945 }
946 break;
947 default:
5b7c81bd 948 jumpabsolute = true;
ee86248c
JB
949 break;
950 }
6f2f06be
JB
951 if (jumpabsolute)
952 {
5b7c81bd 953 i.jumpabsolute = true;
6f2f06be
JB
954 intel_state.is_mem |= 1;
955 }
ee86248c
JB
956 }
957 else if (intel_state.seg)
958 intel_state.is_mem |= 1;
959
960 if (i.op[this_operand].regs)
961 {
962 i386_operand_type temp;
963
964 /* Register operand. */
965 if (intel_state.base || intel_state.index || intel_state.seg)
966 {
967 as_bad (_("invalid operand"));
968 return 0;
969 }
970
971 temp = i.op[this_operand].regs->reg_type;
972 temp.bitfield.baseindex = 0;
f09c1772
L
973 i.types[this_operand] = operand_type_or (i.types[this_operand],
974 temp);
ee86248c
JB
975 i.types[this_operand].bitfield.unspecified = 0;
976 ++i.reg_operands;
cf665fee 977
7063667e
JB
978 if ((i.rounding.type != rc_none && !i.rounding.modifier
979 && temp.bitfield.class != Reg)
980 || rc_sae_modifier)
cf665fee
JB
981 {
982 unsigned int j;
983
984 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j)
985 if (i.rounding.type == RC_NamesTable[j].type)
986 break;
987 as_bad (_("`%s': misplaced `{%s}'"),
76d3f746 988 insn_name (current_templates->start), RC_NamesTable[j].name);
cf665fee
JB
989 return 0;
990 }
ee86248c 991 }
f09c1772
L
992 else if (intel_state.base
993 || intel_state.index
994 || intel_state.seg
ee86248c
JB
995 || intel_state.is_mem)
996 {
997 /* Memory operand. */
04784e33 998 if (i.mem_operands)
ee86248c 999 {
313c53d1
L
1000 /* Handle
1001
1002 call 0x9090,0x90909090
1003 lcall 0x9090,0x90909090
1004 jmp 0x9090,0x90909090
1005 ljmp 0x9090,0x90909090
1006 */
1007
0cfa3eb3
JB
1008 if ((current_templates->start->opcode_modifier.jump == JUMP_INTERSEGMENT
1009 || current_templates->start->opcode_modifier.jump == JUMP_DWORD
1010 || current_templates->start->opcode_modifier.jump == JUMP)
313c53d1
L
1011 && this_operand == 1
1012 && intel_state.seg == NULL
1013 && i.mem_operands == 1
1014 && i.disp_operands == 1
1015 && intel_state.op_modifier == O_absent)
1016 {
1017 /* Try to process the first operand as immediate, */
1018 this_operand = 0;
1019 if (i386_finalize_immediate (exp_seg, i.op[0].imms,
1020 intel_state.reloc_types,
1021 NULL))
1022 {
1023 this_operand = 1;
1024 expP = &im_expressions[0];
1025 i.op[this_operand].imms = expP;
1026 *expP = exp;
1027
1028 /* Try to process the second operand as immediate, */
1029 if (i386_finalize_immediate (exp_seg, expP,
1030 intel_state.reloc_types,
1031 NULL))
1032 {
1033 i.mem_operands = 0;
1034 i.disp_operands = 0;
1035 i.imm_operands = 2;
c48dadc9 1036 i.flags[0] &= ~Operand_Mem;
313c53d1
L
1037 i.types[0].bitfield.disp16 = 0;
1038 i.types[0].bitfield.disp32 = 0;
313c53d1
L
1039 return 1;
1040 }
1041 }
1042 }
ee86248c
JB
1043 }
1044
2abc2bec
JB
1045 /* Swap base and index in 16-bit memory operands like
1046 [si+bx]. Since i386_index_check is also used in AT&T
1047 mode we have to do this here. */
1048 if (intel_state.base
1049 && intel_state.index
dc821c5f
JB
1050 && intel_state.base->reg_type.bitfield.word
1051 && intel_state.index->reg_type.bitfield.word
2abc2bec
JB
1052 && intel_state.base->reg_num >= 6
1053 && intel_state.index->reg_num < 6)
1054 {
1055 i.base_reg = intel_state.index;
1056 i.index_reg = intel_state.base;
1057 }
1058 else
1059 {
1060 i.base_reg = intel_state.base;
1061 i.index_reg = intel_state.index;
1062 }
1063
1064 if (i.base_reg || i.index_reg)
1065 i.types[this_operand].bitfield.baseindex = 1;
1066
ee86248c
JB
1067 expP = &disp_expressions[i.disp_operands];
1068 memcpy (expP, &exp, sizeof(exp));
1069 resolve_expression (expP);
1070
f09c1772
L
1071 if (expP->X_op != O_constant
1072 || expP->X_add_number
2abc2bec 1073 || !i.types[this_operand].bitfield.baseindex)
ee86248c
JB
1074 {
1075 i.op[this_operand].disps = expP;
1076 i.disp_operands++;
1077
2abc2bec
JB
1078 i386_addressing_mode ();
1079
ee86248c
JB
1080 if (flag_code == CODE_64BIT)
1081 {
a775efc8 1082 i.types[this_operand].bitfield.disp32 = 1;
ee86248c 1083 if (!i.prefix[ADDR_PREFIX])
a775efc8 1084 i.types[this_operand].bitfield.disp64 = 1;
ee86248c
JB
1085 }
1086 else if (!i.prefix[ADDR_PREFIX] ^ (flag_code == CODE_16BIT))
1087 i.types[this_operand].bitfield.disp32 = 1;
1088 else
1089 i.types[this_operand].bitfield.disp16 = 1;
1090
1091#if defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)
1092 /*
1093 * exp_seg is used only for verification in
1094 * i386_finalize_displacement, and we can end up seeing reg_section
1095 * here - but we know we removed all registers from the expression
1096 * (or error-ed on any remaining ones) in i386_intel_simplify. I
1097 * consider the check in i386_finalize_displacement bogus anyway, in
1098 * particular because it doesn't allow for expr_section, so I'd
1099 * rather see that check (and the similar one in
1100 * i386_finalize_immediate) use SEG_NORMAL(), but not being an a.out
1101 * expert I can't really say whether that would have other bad side
1102 * effects.
1103 */
1104 if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1105 && exp_seg == reg_section)
1106 exp_seg = expP->X_op != O_constant ? undefined_section
1107 : absolute_section;
1108#endif
1109
1110 if (!i386_finalize_displacement (exp_seg, expP,
1111 intel_state.reloc_types,
1112 operand_string))
1113 return 0;
1114 }
1115
ee86248c
JB
1116 if (intel_state.seg)
1117 {
fd4e0347 1118 for (ret = check_none; ; ret = operand_check)
e21440ba
JB
1119 {
1120 expP = symbol_get_value_expression (intel_state.seg);
fd4e0347
JB
1121 if (expP->X_op != O_full_ptr
1122 || symbol_get_value_expression (expP->X_op_symbol)->X_op
1123 != O_register)
e21440ba
JB
1124 break;
1125 intel_state.seg = expP->X_add_symbol;
1126 }
0398aac5 1127 if (expP->X_op != O_register)
ee86248c
JB
1128 {
1129 as_bad (_("segment register name expected"));
1130 return 0;
1131 }
00cee14f 1132 if (i386_regtab[expP->X_add_number].reg_type.bitfield.class != SReg)
ee86248c
JB
1133 {
1134 as_bad (_("invalid use of register"));
1135 return 0;
1136 }
fd4e0347
JB
1137 switch (ret)
1138 {
1139 case check_error:
1140 as_bad (_("redundant segment overrides"));
1141 return 0;
1142 case check_warning:
1143 as_warn (_("redundant segment overrides"));
1144 break;
1145 }
5e042380
JB
1146 if (i386_regtab[expP->X_add_number].reg_num == RegFlat)
1147 i.seg[i.mem_operands] = NULL;
1148 else
1149 i.seg[i.mem_operands] = &i386_regtab[expP->X_add_number];
ee86248c
JB
1150 }
1151
ee86248c
JB
1152 if (!i386_index_check (operand_string))
1153 return 0;
1154
c48dadc9 1155 i.flags[this_operand] |= Operand_Mem;
ee86248c
JB
1156 ++i.mem_operands;
1157 }
1158 else
1159 {
1160 /* Immediate. */
1161 if (i.imm_operands >= MAX_IMMEDIATE_OPERANDS)
1162 {
1163 as_bad (_("at most %d immediate operands are allowed"),
1164 MAX_IMMEDIATE_OPERANDS);
1165 return 0;
1166 }
1167
1168 expP = &im_expressions[i.imm_operands++];
1169 i.op[this_operand].imms = expP;
1170 *expP = exp;
1171
1172 return i386_finalize_immediate (exp_seg, expP, intel_state.reloc_types,
1173 operand_string);
1174 }
1175
1176 return 1;
1177}