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Fix handling of relocs for the MeP target.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
b90efa5b 2 Copyright (C) 1989-2015 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
89e7505f
L		 36#ifdef TE_LINUX
37/* Default to compress debug sections for Linux. */
151411f8
L		 38enum compressed_debug_section_type flag_compress_debug
39 = COMPRESS_DEBUG_ZLIB;
89e7505f
L		 40#endif
41
252b5132
RH		 42#ifndef REGISTER_WARNINGS
43#define REGISTER_WARNINGS 1
44#endif
45
c3332e24 46#ifndef INFER_ADDR_PREFIX
eecb386c 47#define INFER_ADDR_PREFIX 1
c3332e24
AM		 48#endif
49
29b0f896
AM		 50#ifndef DEFAULT_ARCH
51#define DEFAULT_ARCH "i386"
246fcdee 52#endif
252b5132 53
edde18a5
AM		 54#ifndef INLINE
55#if __GNUC__ >= 2
56#define INLINE __inline__
57#else
58#define INLINE
59#endif
60#endif
61
6305a203
L		 62/* Prefixes will be emitted in the order defined below.
63 WAIT_PREFIX must be the first prefix since FWAIT is really is an
64 instruction, and so must come before any prefixes.
65 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 66 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 67#define WAIT_PREFIX 0
68#define SEG_PREFIX 1
69#define ADDR_PREFIX 2
70#define DATA_PREFIX 3
c32fa91d 71#define REP_PREFIX 4
42164a71 72#define HLE_PREFIX REP_PREFIX
7e8b059b 73#define BND_PREFIX REP_PREFIX
c32fa91d
L		 74#define LOCK_PREFIX 5
75#define REX_PREFIX 6 /* must come last. */
76#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 77
78/* we define the syntax here (modulo base,index,scale syntax) */
79#define REGISTER_PREFIX '%'
80#define IMMEDIATE_PREFIX '$'
81#define ABSOLUTE_PREFIX '*'
82
83/* these are the instruction mnemonic suffixes in AT&T syntax or
84 memory operand size in Intel syntax. */
85#define WORD_MNEM_SUFFIX 'w'
86#define BYTE_MNEM_SUFFIX 'b'
87#define SHORT_MNEM_SUFFIX 's'
88#define LONG_MNEM_SUFFIX 'l'
89#define QWORD_MNEM_SUFFIX 'q'
90#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 91#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 92#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 93/* Intel Syntax. Use a non-ascii letter since since it never appears
94 in instructions. */
95#define LONG_DOUBLE_MNEM_SUFFIX '\1'
96
97#define END_OF_INSN '\0'
98
99/*
100 'templates' is for grouping together 'template' structures for opcodes
101 of the same name. This is only used for storing the insns in the grand
102 ole hash table of insns.
103 The templates themselves start at START and range up to (but not including)
104 END.
105 */
106typedef struct
107{
d3ce72d0
NC		 108 const insn_template *start;
109 const insn_template *end;
6305a203
L		 110}
111templates;
112
113/* 386 operand encoding bytes: see 386 book for details of this. */
114typedef struct
115{
116 unsigned int regmem; /* codes register or memory operand */
117 unsigned int reg; /* codes register operand (or extended opcode) */
118 unsigned int mode; /* how to interpret regmem & reg */
119}
120modrm_byte;
121
122/* x86-64 extension prefix. */
123typedef int rex_byte;
124
6305a203
L		 125/* 386 opcode byte to code indirect addressing. */
126typedef struct
127{
128 unsigned base;
129 unsigned index;
130 unsigned scale;
131}
132sib_byte;
133
6305a203
L		 134/* x86 arch names, types and features */
135typedef struct
136{
137 const char *name; /* arch name */
8a2c8fef 138 unsigned int len; /* arch string length */
6305a203
L		 139 enum processor_type type; /* arch type */
140 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 141 unsigned int skip; /* show_arch should skip this. */
22109423 142 unsigned int negated; /* turn off indicated flags. */
6305a203
L		 143}
144arch_entry;
145
78f12dd3 146static void update_code_flag (int, int);
e3bb37b5
L		 147static void set_code_flag (int);
148static void set_16bit_gcc_code_flag (int);
149static void set_intel_syntax (int);
1efbbeb4 150static void set_intel_mnemonic (int);
db51cc60 151static void set_allow_index_reg (int);
7bab8ab5 152static void set_check (int);
e3bb37b5 153static void set_cpu_arch (int);
6482c264 154#ifdef TE_PE
e3bb37b5 155static void pe_directive_secrel (int);
6482c264 156#endif
e3bb37b5
L		 157static void signed_cons (int);
158static char *output_invalid (int c);
ee86248c
JB		 159static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
160 const char *);
161static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
162 const char *);
a7619375 163static int i386_att_operand (char *);
e3bb37b5 164static int i386_intel_operand (char *, int);
ee86248c
JB		 165static int i386_intel_simplify (expressionS *);
166static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 167static const reg_entry *parse_register (char *, char **);
168static char *parse_insn (char *, char *);
169static char *parse_operands (char *, const char *);
170static void swap_operands (void);
4d456e3d 171static void swap_2_operands (int, int);
e3bb37b5
L		 172static void optimize_imm (void);
173static void optimize_disp (void);
d3ce72d0 174static const insn_template *match_template (void);
e3bb37b5
L		 175static int check_string (void);
176static int process_suffix (void);
177static int check_byte_reg (void);
178static int check_long_reg (void);
179static int check_qword_reg (void);
180static int check_word_reg (void);
181static int finalize_imm (void);
182static int process_operands (void);
183static const seg_entry *build_modrm_byte (void);
184static void output_insn (void);
185static void output_imm (fragS *, offsetT);
186static void output_disp (fragS *, offsetT);
29b0f896 187#ifndef I386COFF
e3bb37b5 188static void s_bss (int);
252b5132 189#endif
17d4e2a2
L		 190#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
191static void handle_large_common (int small ATTRIBUTE_UNUSED);
192#endif
252b5132 193
a847613f 194static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 195
43234a1e
L		 196/* This struct describes rounding control and SAE in the instruction. */
197struct RC_Operation
198{
199 enum rc_type
200 {
201 rne = 0,
202 rd,
203 ru,
204 rz,
205 saeonly
206 } type;
207 int operand;
208};
209
210static struct RC_Operation rc_op;
211
212/* The struct describes masking, applied to OPERAND in the instruction.
213 MASK is a pointer to the corresponding mask register. ZEROING tells
214 whether merging or zeroing mask is used. */
215struct Mask_Operation
216{
217 const reg_entry *mask;
218 unsigned int zeroing;
219 /* The operand where this operation is associated. */
220 int operand;
221};
222
223static struct Mask_Operation mask_op;
224
225/* The struct describes broadcasting, applied to OPERAND. FACTOR is
226 broadcast factor. */
227struct Broadcast_Operation
228{
229 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
230 int type;
231
232 /* Index of broadcasted operand. */
233 int operand;
234};
235
236static struct Broadcast_Operation broadcast_op;
237
c0f3af97
L		 238/* VEX prefix. */
239typedef struct
240{
43234a1e
L		 241 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
242 unsigned char bytes[4];
c0f3af97
L		 243 unsigned int length;
244 /* Destination or source register specifier. */
245 const reg_entry *register_specifier;
246} vex_prefix;
247
252b5132 248/* 'md_assemble ()' gathers together information and puts it into a
47926f60 249 i386_insn. */
252b5132 250
520dc8e8
AM		 251union i386_op
252 {
253 expressionS *disps;
254 expressionS *imms;
255 const reg_entry *regs;
256 };
257
a65babc9
L		 258enum i386_error
259 {
86e026a4 260 operand_size_mismatch,
a65babc9
L		 261 operand_type_mismatch,
262 register_type_mismatch,
263 number_of_operands_mismatch,
264 invalid_instruction_suffix,
265 bad_imm4,
266 old_gcc_only,
267 unsupported_with_intel_mnemonic,
268 unsupported_syntax,
6c30d220
L		 269 unsupported,
270 invalid_vsib_address,
7bab8ab5 271 invalid_vector_register_set,
43234a1e
L		 272 unsupported_vector_index_register,
273 unsupported_broadcast,
274 broadcast_not_on_src_operand,
275 broadcast_needed,
276 unsupported_masking,
277 mask_not_on_destination,
278 no_default_mask,
279 unsupported_rc_sae,
280 rc_sae_operand_not_last_imm,
281 invalid_register_operand,
282 try_vector_disp8
a65babc9
L		 283 };
284
252b5132
RH		 285struct _i386_insn
286 {
47926f60 287 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 288 insn_template tm;
252b5132 289
7d5e4556
L		 290 /* SUFFIX holds the instruction size suffix for byte, word, dword
291 or qword, if given. */
252b5132
RH		 292 char suffix;
293
47926f60 294 /* OPERANDS gives the number of given operands. */
252b5132
RH		 295 unsigned int operands;
296
297 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
298 of given register, displacement, memory operands and immediate
47926f60 299 operands. */
252b5132
RH		 300 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
301
302 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 303 use OP[i] for the corresponding operand. */
40fb9820 304 i386_operand_type types[MAX_OPERANDS];
252b5132 305
520dc8e8
AM		 306 /* Displacement expression, immediate expression, or register for each
307 operand. */
308 union i386_op op[MAX_OPERANDS];
252b5132 309
3e73aa7c
JH		 310 /* Flags for operands. */
311 unsigned int flags[MAX_OPERANDS];
312#define Operand_PCrel 1
313
252b5132 314 /* Relocation type for operand */
f86103b7 315 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 316
252b5132
RH		 317 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
318 the base index byte below. */
319 const reg_entry *base_reg;
320 const reg_entry *index_reg;
321 unsigned int log2_scale_factor;
322
323 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 324 explicit segment overrides are given. */
ce8a8b2f 325 const seg_entry *seg[2];
252b5132
RH		 326
327 /* PREFIX holds all the given prefix opcodes (usually null).
328 PREFIXES is the number of prefix opcodes. */
329 unsigned int prefixes;
330 unsigned char prefix[MAX_PREFIXES];
331
332 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 333 addressing modes of this insn are encoded. */
252b5132 334 modrm_byte rm;
3e73aa7c 335 rex_byte rex;
43234a1e 336 rex_byte vrex;
252b5132 337 sib_byte sib;
c0f3af97 338 vex_prefix vex;
b6169b20 339
43234a1e
L		 340 /* Masking attributes. */
341 struct Mask_Operation *mask;
342
343 /* Rounding control and SAE attributes. */
344 struct RC_Operation *rounding;
345
346 /* Broadcasting attributes. */
347 struct Broadcast_Operation *broadcast;
348
349 /* Compressed disp8*N attribute. */
350 unsigned int memshift;
351
b6169b20 352 /* Swap operand in encoding. */
4473e004 353 unsigned int swap_operand;
891edac4 354
a501d77e
L		 355 /* Prefer 8bit or 32bit displacement in encoding. */
356 enum
357 {
358 disp_encoding_default = 0,
359 disp_encoding_8bit,
360 disp_encoding_32bit
361 } disp_encoding;
f8a5c266 362
d5de92cf
L		 363 /* REP prefix. */
364 const char *rep_prefix;
365
165de32a
L		 366 /* HLE prefix. */
367 const char *hle_prefix;
42164a71 368
7e8b059b
L		 369 /* Have BND prefix. */
370 const char *bnd_prefix;
371
43234a1e
L		 372 /* Need VREX to support upper 16 registers. */
373 int need_vrex;
374
891edac4 375 /* Error message. */
a65babc9 376 enum i386_error error;
252b5132
RH		 377 };
378
379typedef struct _i386_insn i386_insn;
380
43234a1e
L		 381/* Link RC type with corresponding string, that'll be looked for in
382 asm. */
383struct RC_name
384{
385 enum rc_type type;
386 const char *name;
387 unsigned int len;
388};
389
390static const struct RC_name RC_NamesTable[] =
391{
392 { rne, STRING_COMMA_LEN ("rn-sae") },
393 { rd, STRING_COMMA_LEN ("rd-sae") },
394 { ru, STRING_COMMA_LEN ("ru-sae") },
395 { rz, STRING_COMMA_LEN ("rz-sae") },
396 { saeonly, STRING_COMMA_LEN ("sae") },
397};
398
252b5132
RH		 399/* List of chars besides those in app.c:symbol_chars that can start an
400 operand. Used to prevent the scrubber eating vital white-space. */
43234a1e 401const char extra_symbol_chars[] = "*%-([{"
252b5132 402#ifdef LEX_AT
32137342
NC		 403 "@"
404#endif
405#ifdef LEX_QM
406 "?"
252b5132 407#endif
32137342 408 ;
252b5132 409
29b0f896
AM		 410#if (defined (TE_I386AIX) \
411 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 412 && !defined (TE_GNU) \
29b0f896 413 && !defined (TE_LINUX) \
8d63c93e
RM		 414 && !defined (TE_NACL) \
415 && !defined (TE_NETWARE) \
29b0f896 416 && !defined (TE_FreeBSD) \
5b806d27 417 && !defined (TE_DragonFly) \
29b0f896 418 && !defined (TE_NetBSD)))
252b5132 419/* This array holds the chars that always start a comment. If the
b3b91714
AM		 420 pre-processor is disabled, these aren't very useful. The option
421 --divide will remove '/' from this list. */
422const char *i386_comment_chars = "#/";
423#define SVR4_COMMENT_CHARS 1
252b5132 424#define PREFIX_SEPARATOR '\\'
252b5132 425
b3b91714
AM		 426#else
427const char *i386_comment_chars = "#";
428#define PREFIX_SEPARATOR '/'
429#endif
430
252b5132
RH		 431/* This array holds the chars that only start a comment at the beginning of
432 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 433 .line and .file directives will appear in the pre-processed output.
434 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 435 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 436 #NO_APP at the beginning of its output.
437 Also note that comments started like this one will always work if
252b5132 438 '/' isn't otherwise defined. */
b3b91714 439const char line_comment_chars[] = "#/";
252b5132 440
63a0b638 441const char line_separator_chars[] = ";";
252b5132 442
ce8a8b2f
AM		 443/* Chars that can be used to separate mant from exp in floating point
444 nums. */
252b5132
RH		 445const char EXP_CHARS[] = "eE";
446
ce8a8b2f
AM		 447/* Chars that mean this number is a floating point constant
448 As in 0f12.456
449 or 0d1.2345e12. */
252b5132
RH		 450const char FLT_CHARS[] = "fFdDxX";
451
ce8a8b2f 452/* Tables for lexical analysis. */
252b5132
RH		 453static char mnemonic_chars[256];
454static char register_chars[256];
455static char operand_chars[256];
456static char identifier_chars[256];
457static char digit_chars[256];
458
ce8a8b2f 459/* Lexical macros. */
252b5132
RH		 460#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
461#define is_operand_char(x) (operand_chars[(unsigned char) x])
462#define is_register_char(x) (register_chars[(unsigned char) x])
463#define is_space_char(x) ((x) == ' ')
464#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
465#define is_digit_char(x) (digit_chars[(unsigned char) x])
466
0234cb7c 467/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 468static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
469
470/* md_assemble() always leaves the strings it's passed unaltered. To
471 effect this we maintain a stack of saved characters that we've smashed
472 with '\0's (indicating end of strings for various sub-fields of the
47926f60 473 assembler instruction). */
252b5132 474static char save_stack[32];
ce8a8b2f 475static char *save_stack_p;
252b5132
RH		 476#define END_STRING_AND_SAVE(s) \
477 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
478#define RESTORE_END_STRING(s) \
479 do { *(s) = *--save_stack_p; } while (0)
480
47926f60 481/* The instruction we're assembling. */
252b5132
RH		 482static i386_insn i;
483
484/* Possible templates for current insn. */
485static const templates *current_templates;
486
31b2323c
L		 487/* Per instruction expressionS buffers: max displacements & immediates. */
488static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
489static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 490
47926f60 491/* Current operand we are working on. */
ee86248c 492static int this_operand = -1;
252b5132 493
3e73aa7c
JH		 494/* We support four different modes. FLAG_CODE variable is used to distinguish
495 these. */
496
497enum flag_code {
498 CODE_32BIT,
499 CODE_16BIT,
500 CODE_64BIT };
501
502static enum flag_code flag_code;
4fa24527 503static unsigned int object_64bit;
862be3fb 504static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 505static int use_rela_relocations = 0;
506
7af8ed2d
NC		 507#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
508 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
509 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
510
351f65ca
L		 511/* The ELF ABI to use. */
512enum x86_elf_abi
513{
514 I386_ABI,
7f56bc95
L		 515 X86_64_ABI,
516 X86_64_X32_ABI
351f65ca
L		 517};
518
519static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 520#endif
351f65ca 521
167ad85b
TG		 522#if defined (TE_PE) || defined (TE_PEP)
523/* Use big object file format. */
524static int use_big_obj = 0;
525#endif
526
47926f60
KH		 527/* 1 for intel syntax,
528 0 if att syntax. */
529static int intel_syntax = 0;
252b5132 530
1efbbeb4
L		 531/* 1 for intel mnemonic,
532 0 if att mnemonic. */
533static int intel_mnemonic = !SYSV386_COMPAT;
534
5209009a 535/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 536static int old_gcc = OLDGCC_COMPAT;
537
a60de03c
JB		 538/* 1 if pseudo registers are permitted. */
539static int allow_pseudo_reg = 0;
540
47926f60
KH		 541/* 1 if register prefix % not required. */
542static int allow_naked_reg = 0;
252b5132 543
7e8b059b
L		 544/* 1 if the assembler should add BND prefix for all control-tranferring
545 instructions supporting it, even if this prefix wasn't specified
546 explicitly. */
547static int add_bnd_prefix = 0;
548
ba104c83 549/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 550static int allow_index_reg = 0;
551
d022bddd
IT		 552/* 1 if the assembler should ignore LOCK prefix, even if it was
553 specified explicitly. */
554static int omit_lock_prefix = 0;
555
7bab8ab5 556static enum check_kind
daf50ae7 557 {
7bab8ab5
JB		 558 check_none = 0,
559 check_warning,
560 check_error
daf50ae7 561 }
7bab8ab5 562sse_check, operand_check = check_warning;
daf50ae7 563
2ca3ace5
L		 564/* Register prefix used for error message. */
565static const char *register_prefix = "%";
566
47926f60
KH		 567/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
568 leave, push, and pop instructions so that gcc has the same stack
569 frame as in 32 bit mode. */
570static char stackop_size = '\0';
eecb386c 571
12b55ccc
L		 572/* Non-zero to optimize code alignment. */
573int optimize_align_code = 1;
574
47926f60
KH		 575/* Non-zero to quieten some warnings. */
576static int quiet_warnings = 0;
a38cf1db 577
47926f60
KH		 578/* CPU name. */
579static const char *cpu_arch_name = NULL;
6305a203 580static char *cpu_sub_arch_name = NULL;
a38cf1db 581
47926f60 582/* CPU feature flags. */
40fb9820
L		 583static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
584
ccc9c027
L		 585/* If we have selected a cpu we are generating instructions for. */
586static int cpu_arch_tune_set = 0;
587
9103f4f4 588/* Cpu we are generating instructions for. */
fbf3f584 589enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 590
591/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 592static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 593
ccc9c027 594/* CPU instruction set architecture used. */
fbf3f584 595enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 596
9103f4f4 597/* CPU feature flags of instruction set architecture used. */
fbf3f584 598i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 599
fddf5b5b
AM		 600/* If set, conditional jumps are not automatically promoted to handle
601 larger than a byte offset. */
602static unsigned int no_cond_jump_promotion = 0;
603
c0f3af97
L		 604/* Encode SSE instructions with VEX prefix. */
605static unsigned int sse2avx;
606
539f890d
L		 607/* Encode scalar AVX instructions with specific vector length. */
608static enum
609 {
610 vex128 = 0,
611 vex256
612 } avxscalar;
613
43234a1e
L		 614/* Encode scalar EVEX LIG instructions with specific vector length. */
615static enum
616 {
617 evexl128 = 0,
618 evexl256,
619 evexl512
620 } evexlig;
621
622/* Encode EVEX WIG instructions with specific evex.w. */
623static enum
624 {
625 evexw0 = 0,
626 evexw1
627 } evexwig;
628
d3d3c6db
IT		 629/* Value to encode in EVEX RC bits, for SAE-only instructions. */
630static enum rc_type evexrcig = rne;
631
29b0f896 632/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 633static symbolS *GOT_symbol;
29b0f896 634
a4447b93
RH		 635/* The dwarf2 return column, adjusted for 32 or 64 bit. */
636unsigned int x86_dwarf2_return_column;
637
638/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
639int x86_cie_data_alignment;
640
252b5132 641/* Interface to relax_segment.
fddf5b5b
AM		 642 There are 3 major relax states for 386 jump insns because the
643 different types of jumps add different sizes to frags when we're
644 figuring out what sort of jump to choose to reach a given label. */
252b5132 645
47926f60 646/* Types. */
93c2a809
AM		 647#define UNCOND_JUMP 0
648#define COND_JUMP 1
649#define COND_JUMP86 2
fddf5b5b 650
47926f60 651/* Sizes. */
252b5132
RH		 652#define CODE16 1
653#define SMALL 0
29b0f896 654#define SMALL16 (SMALL | CODE16)
252b5132 655#define BIG 2
29b0f896 656#define BIG16 (BIG | CODE16)
252b5132
RH		 657
658#ifndef INLINE
659#ifdef __GNUC__
660#define INLINE __inline__
661#else
662#define INLINE
663#endif
664#endif
665
fddf5b5b
AM		 666#define ENCODE_RELAX_STATE(type, size) \
667 ((relax_substateT) (((type) << 2) | (size)))
668#define TYPE_FROM_RELAX_STATE(s) \
669 ((s) >> 2)
670#define DISP_SIZE_FROM_RELAX_STATE(s) \
671 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 672
673/* This table is used by relax_frag to promote short jumps to long
674 ones where necessary. SMALL (short) jumps may be promoted to BIG
675 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
676 don't allow a short jump in a 32 bit code segment to be promoted to
677 a 16 bit offset jump because it's slower (requires data size
678 prefix), and doesn't work, unless the destination is in the bottom
679 64k of the code segment (The top 16 bits of eip are zeroed). */
680
681const relax_typeS md_relax_table[] =
682{
24eab124
AM		 683 /* The fields are:
684 1) most positive reach of this state,
685 2) most negative reach of this state,
93c2a809 686 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 687 4) which index into the table to try if we can't fit into this one. */
252b5132 688
fddf5b5b 689 /* UNCOND_JUMP states. */
93c2a809
AM		 690 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
691 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
692 /* dword jmp adds 4 bytes to frag:
693 0 extra opcode bytes, 4 displacement bytes. */
252b5132 694 {0, 0, 4, 0},
93c2a809
AM		 695 /* word jmp adds 2 byte2 to frag:
696 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 697 {0, 0, 2, 0},
698
93c2a809
AM		 699 /* COND_JUMP states. */
700 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
701 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
702 /* dword conditionals adds 5 bytes to frag:
703 1 extra opcode byte, 4 displacement bytes. */
704 {0, 0, 5, 0},
fddf5b5b 705 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 706 1 extra opcode byte, 2 displacement bytes. */
707 {0, 0, 3, 0},
708
709 /* COND_JUMP86 states. */
710 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
711 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
712 /* dword conditionals adds 5 bytes to frag:
713 1 extra opcode byte, 4 displacement bytes. */
714 {0, 0, 5, 0},
715 /* word conditionals add 4 bytes to frag:
716 1 displacement byte and a 3 byte long branch insn. */
717 {0, 0, 4, 0}
252b5132
RH		 718};
719
9103f4f4
L		 720static const arch_entry cpu_arch[] =
721{
89507696
JB		 722 /* Do not replace the first two entries - i386_target_format()
723 relies on them being there in this order. */
8a2c8fef 724 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
22109423 725 CPU_GENERIC32_FLAGS, 0, 0 },
8a2c8fef 726 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
22109423 727 CPU_GENERIC64_FLAGS, 0, 0 },
8a2c8fef 728 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
22109423 729 CPU_NONE_FLAGS, 0, 0 },
8a2c8fef 730 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
22109423 731 CPU_I186_FLAGS, 0, 0 },
8a2c8fef 732 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
22109423 733 CPU_I286_FLAGS, 0, 0 },
8a2c8fef 734 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
22109423 735 CPU_I386_FLAGS, 0, 0 },
8a2c8fef 736 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
22109423 737 CPU_I486_FLAGS, 0, 0 },
8a2c8fef 738 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
22109423 739 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 740 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
22109423 741 CPU_I686_FLAGS, 0, 0 },
8a2c8fef 742 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
22109423 743 CPU_I586_FLAGS, 0, 0 },
8a2c8fef 744 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
22109423 745 CPU_PENTIUMPRO_FLAGS, 0, 0 },
8a2c8fef 746 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
22109423 747 CPU_P2_FLAGS, 0, 0 },
8a2c8fef 748 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
22109423 749 CPU_P3_FLAGS, 0, 0 },
8a2c8fef 750 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
22109423 751 CPU_P4_FLAGS, 0, 0 },
8a2c8fef 752 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
22109423 753 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 754 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
22109423 755 CPU_NOCONA_FLAGS, 0, 0 },
8a2c8fef 756 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
22109423 757 CPU_CORE_FLAGS, 1, 0 },
8a2c8fef 758 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
22109423 759 CPU_CORE_FLAGS, 0, 0 },
8a2c8fef 760 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
22109423 761 CPU_CORE2_FLAGS, 1, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
22109423 763 CPU_CORE2_FLAGS, 0, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
22109423 765 CPU_COREI7_FLAGS, 0, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
22109423 767 CPU_L1OM_FLAGS, 0, 0 },
7a9068fe
L		 768 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
769 CPU_K1OM_FLAGS, 0, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
22109423 771 CPU_K6_FLAGS, 0, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
22109423 773 CPU_K6_2_FLAGS, 0, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
22109423 775 CPU_ATHLON_FLAGS, 0, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
22109423 777 CPU_K8_FLAGS, 1, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
22109423 779 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
22109423 781 CPU_K8_FLAGS, 0, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
22109423 783 CPU_AMDFAM10_FLAGS, 0, 0 },
8aedb9fe 784 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
22109423 785 CPU_BDVER1_FLAGS, 0, 0 },
8aedb9fe 786 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
af2f724e 787 CPU_BDVER2_FLAGS, 0, 0 },
5e5c50d3
NE		 788 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
789 CPU_BDVER3_FLAGS, 0, 0 },
c7b0bd56
SE		 790 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
791 CPU_BDVER4_FLAGS, 0, 0 },
029f3522
GG		 792 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
793 CPU_ZNVER1_FLAGS, 0, 0 },
7b458c12
L		 794 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
795 CPU_BTVER1_FLAGS, 0, 0 },
796 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
797 CPU_BTVER2_FLAGS, 0, 0 },
8a2c8fef 798 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
22109423 799 CPU_8087_FLAGS, 0, 0 },
8a2c8fef 800 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
22109423 801 CPU_287_FLAGS, 0, 0 },
8a2c8fef 802 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
22109423 803 CPU_387_FLAGS, 0, 0 },
8a2c8fef 804 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
22109423 805 CPU_ANY87_FLAGS, 0, 1 },
8a2c8fef 806 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
22109423 807 CPU_MMX_FLAGS, 0, 0 },
8a2c8fef 808 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
22109423 809 CPU_3DNOWA_FLAGS, 0, 1 },
8a2c8fef 810 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
22109423 811 CPU_SSE_FLAGS, 0, 0 },
8a2c8fef 812 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
22109423 813 CPU_SSE2_FLAGS, 0, 0 },
8a2c8fef 814 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
22109423 815 CPU_SSE3_FLAGS, 0, 0 },
8a2c8fef 816 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
22109423 817 CPU_SSSE3_FLAGS, 0, 0 },
8a2c8fef 818 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
22109423 819 CPU_SSE4_1_FLAGS, 0, 0 },
8a2c8fef 820 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
22109423 821 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 822 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
22109423 823 CPU_SSE4_2_FLAGS, 0, 0 },
8a2c8fef 824 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
22109423 825 CPU_ANY_SSE_FLAGS, 0, 1 },
8a2c8fef 826 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
22109423 827 CPU_AVX_FLAGS, 0, 0 },
6c30d220
L		 828 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
829 CPU_AVX2_FLAGS, 0, 0 },
43234a1e
L		 830 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
831 CPU_AVX512F_FLAGS, 0, 0 },
832 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
833 CPU_AVX512CD_FLAGS, 0, 0 },
834 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
835 CPU_AVX512ER_FLAGS, 0, 0 },
836 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
837 CPU_AVX512PF_FLAGS, 0, 0 },
1dfc6506
L		 838 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
839 CPU_AVX512DQ_FLAGS, 0, 0 },
840 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
841 CPU_AVX512BW_FLAGS, 0, 0 },
842 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
843 CPU_AVX512VL_FLAGS, 0, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
22109423 845 CPU_ANY_AVX_FLAGS, 0, 1 },
8a2c8fef 846 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
22109423 847 CPU_VMX_FLAGS, 0, 0 },
8729a6f6
L		 848 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
849 CPU_VMFUNC_FLAGS, 0, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
22109423 851 CPU_SMX_FLAGS, 0, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
22109423 853 CPU_XSAVE_FLAGS, 0, 0 },
c7b8aa3a 854 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
22109423 855 CPU_XSAVEOPT_FLAGS, 0, 0 },
1dfc6506
L		 856 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
857 CPU_XSAVEC_FLAGS, 0, 0 },
858 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
859 CPU_XSAVES_FLAGS, 0, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
22109423 861 CPU_AES_FLAGS, 0, 0 },
8a2c8fef 862 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
22109423 863 CPU_PCLMUL_FLAGS, 0, 0 },
8a2c8fef 864 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
22109423 865 CPU_PCLMUL_FLAGS, 1, 0 },
c7b8aa3a 866 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
22109423 867 CPU_FSGSBASE_FLAGS, 0, 0 },
c7b8aa3a 868 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
22109423 869 CPU_RDRND_FLAGS, 0, 0 },
c7b8aa3a 870 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
22109423 871 CPU_F16C_FLAGS, 0, 0 },
6c30d220
L		 872 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
873 CPU_BMI2_FLAGS, 0, 0 },
8a2c8fef 874 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
22109423 875 CPU_FMA_FLAGS, 0, 0 },
8a2c8fef 876 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
22109423 877 CPU_FMA4_FLAGS, 0, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
22109423 879 CPU_XOP_FLAGS, 0, 0 },
8a2c8fef 880 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
22109423 881 CPU_LWP_FLAGS, 0, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
22109423 883 CPU_MOVBE_FLAGS, 0, 0 },
60aa667e
L		 884 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
885 CPU_CX16_FLAGS, 0, 0 },
8a2c8fef 886 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
22109423 887 CPU_EPT_FLAGS, 0, 0 },
6c30d220
L		 888 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
889 CPU_LZCNT_FLAGS, 0, 0 },
42164a71
L		 890 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
891 CPU_HLE_FLAGS, 0, 0 },
892 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
893 CPU_RTM_FLAGS, 0, 0 },
6c30d220
L		 894 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
895 CPU_INVPCID_FLAGS, 0, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
22109423
L		 897 CPU_CLFLUSH_FLAGS, 0, 0 },
898 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
899 CPU_NOP_FLAGS, 0, 0 },
8a2c8fef 900 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
22109423 901 CPU_SYSCALL_FLAGS, 0, 0 },
8a2c8fef 902 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
22109423 903 CPU_RDTSCP_FLAGS, 0, 0 },
8a2c8fef 904 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
22109423 905 CPU_3DNOW_FLAGS, 0, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
22109423 907 CPU_3DNOWA_FLAGS, 0, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
22109423 909 CPU_PADLOCK_FLAGS, 0, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
22109423 911 CPU_SVME_FLAGS, 1, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
22109423 913 CPU_SVME_FLAGS, 0, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
22109423 915 CPU_SSE4A_FLAGS, 0, 0 },
8a2c8fef 916 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
22109423 917 CPU_ABM_FLAGS, 0, 0 },
87973e9f
QN		 918 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
919 CPU_BMI_FLAGS, 0, 0 },
2a2a0f38
QN		 920 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
921 CPU_TBM_FLAGS, 0, 0 },
e2e1fcde
L		 922 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
923 CPU_ADX_FLAGS, 0, 0 },
924 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
925 CPU_RDSEED_FLAGS, 0, 0 },
926 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
927 CPU_PRFCHW_FLAGS, 0, 0 },
5c111e37
L		 928 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
929 CPU_SMAP_FLAGS, 0, 0 },
7e8b059b
L		 930 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
931 CPU_MPX_FLAGS, 0, 0 },
a0046408
L		 932 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
933 CPU_SHA_FLAGS, 0, 0 },
963f3586
IT		 934 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
935 CPU_CLFLUSHOPT_FLAGS, 0, 0 },
dcf893b5
IT		 936 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
937 CPU_PREFETCHWT1_FLAGS, 0, 0 },
2cf200a4
IT		 938 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
939 CPU_SE1_FLAGS, 0, 0 },
c5e7287a
IT		 940 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
941 CPU_CLWB_FLAGS, 0, 0 },
9d8596f0
IT		 942 { STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
943 CPU_PCOMMIT_FLAGS, 0, 0 },
2cc1b5aa
IT		 944 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
945 CPU_AVX512IFMA_FLAGS, 0, 0 },
14f195c9
IT		 946 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
947 CPU_AVX512VBMI_FLAGS, 0, 0 },
029f3522
GG		 948 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
949 CPU_CLZERO_FLAGS, 0, 0 },
e413e4e9
AM		 950};
951
704209c0 952#ifdef I386COFF
a6c24e68
NC		 953/* Like s_lcomm_internal in gas/read.c but the alignment string
954 is allowed to be optional. */
955
956static symbolS *
957pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
958{
959 addressT align = 0;
960
961 SKIP_WHITESPACE ();
962
7ab9ffdd 963 if (needs_align
a6c24e68
NC		 964 && *input_line_pointer == ',')
965 {
966 align = parse_align (needs_align - 1);
7ab9ffdd 967
a6c24e68
NC		 968 if (align == (addressT) -1)
969 return NULL;
970 }
971 else
972 {
973 if (size >= 8)
974 align = 3;
975 else if (size >= 4)
976 align = 2;
977 else if (size >= 2)
978 align = 1;
979 else
980 align = 0;
981 }
982
983 bss_alloc (symbolP, size, align);
984 return symbolP;
985}
986
704209c0 987static void
a6c24e68
NC		 988pe_lcomm (int needs_align)
989{
990 s_comm_internal (needs_align * 2, pe_lcomm_internal);
991}
704209c0 992#endif
a6c24e68 993
29b0f896
AM		 994const pseudo_typeS md_pseudo_table[] =
995{
996#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
997 {"align", s_align_bytes, 0},
998#else
999 {"align", s_align_ptwo, 0},
1000#endif
1001 {"arch", set_cpu_arch, 0},
1002#ifndef I386COFF
1003 {"bss", s_bss, 0},
a6c24e68
NC		 1004#else
1005 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1006#endif
1007 {"ffloat", float_cons, 'f'},
1008 {"dfloat", float_cons, 'd'},
1009 {"tfloat", float_cons, 'x'},
1010 {"value", cons, 2},
d182319b 1011 {"slong", signed_cons, 4},
29b0f896
AM		 1012 {"noopt", s_ignore, 0},
1013 {"optim", s_ignore, 0},
1014 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1015 {"code16", set_code_flag, CODE_16BIT},
1016 {"code32", set_code_flag, CODE_32BIT},
1017 {"code64", set_code_flag, CODE_64BIT},
1018 {"intel_syntax", set_intel_syntax, 1},
1019 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1020 {"intel_mnemonic", set_intel_mnemonic, 1},
1021 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1022 {"allow_index_reg", set_allow_index_reg, 1},
1023 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1024 {"sse_check", set_check, 0},
1025 {"operand_check", set_check, 1},
3b22753a
L		 1026#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1027 {"largecomm", handle_large_common, 0},
07a53e5c 1028#else
e3bb37b5 1029 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1030 {"loc", dwarf2_directive_loc, 0},
1031 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1032#endif
6482c264
NC		 1033#ifdef TE_PE
1034 {"secrel32", pe_directive_secrel, 0},
1035#endif
29b0f896
AM		 1036 {0, 0, 0}
1037};
1038
1039/* For interface with expression (). */
1040extern char *input_line_pointer;
1041
1042/* Hash table for instruction mnemonic lookup. */
1043static struct hash_control *op_hash;
1044
1045/* Hash table for register lookup. */
1046static struct hash_control *reg_hash;
1047\f
252b5132 1048void
e3bb37b5 1049i386_align_code (fragS *fragP, int count)
252b5132 1050{
ce8a8b2f
AM		 1051 /* Various efficient no-op patterns for aligning code labels.
1052 Note: Don't try to assemble the instructions in the comments.
1053 0L and 0w are not legal. */
252b5132
RH		 1054 static const char f32_1[] =
1055 {0x90}; /* nop */
1056 static const char f32_2[] =
ccc9c027 1057 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 1058 static const char f32_3[] =
1059 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1060 static const char f32_4[] =
1061 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1062 static const char f32_5[] =
1063 {0x90, /* nop */
1064 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1065 static const char f32_6[] =
1066 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1067 static const char f32_7[] =
1068 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1069 static const char f32_8[] =
1070 {0x90, /* nop */
1071 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1072 static const char f32_9[] =
1073 {0x89,0xf6, /* movl %esi,%esi */
1074 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1075 static const char f32_10[] =
1076 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1077 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1078 static const char f32_11[] =
1079 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1080 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1081 static const char f32_12[] =
1082 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1083 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1084 static const char f32_13[] =
1085 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1086 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1087 static const char f32_14[] =
1088 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1089 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 1090 static const char f16_3[] =
1091 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 1092 static const char f16_4[] =
1093 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1094 static const char f16_5[] =
1095 {0x90, /* nop */
1096 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1097 static const char f16_6[] =
1098 {0x89,0xf6, /* mov %si,%si */
1099 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1100 static const char f16_7[] =
1101 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1102 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1103 static const char f16_8[] =
1104 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1105 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 1106 static const char jump_31[] =
1107 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1108 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1109 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1110 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 1111 static const char *const f32_patt[] = {
1112 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1113 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 1114 };
1115 static const char *const f16_patt[] = {
76bc74dc 1116 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1117 };
ccc9c027
L		 1118 /* nopl (%[re]ax) */
1119 static const char alt_3[] =
1120 {0x0f,0x1f,0x00};
1121 /* nopl 0(%[re]ax) */
1122 static const char alt_4[] =
1123 {0x0f,0x1f,0x40,0x00};
1124 /* nopl 0(%[re]ax,%[re]ax,1) */
1125 static const char alt_5[] =
1126 {0x0f,0x1f,0x44,0x00,0x00};
1127 /* nopw 0(%[re]ax,%[re]ax,1) */
1128 static const char alt_6[] =
1129 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1130 /* nopl 0L(%[re]ax) */
1131 static const char alt_7[] =
1132 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1133 /* nopl 0L(%[re]ax,%[re]ax,1) */
1134 static const char alt_8[] =
1135 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 /* nopw 0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_9[] =
1138 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1139 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1140 static const char alt_10[] =
1141 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
80b8656c 1142 static const char *const alt_patt[] = {
ccc9c027 1143 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1144 alt_9, alt_10
ccc9c027 1145 };
252b5132 1146
76bc74dc
L		 1147 /* Only align for at least a positive non-zero boundary. */
1148 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1149 return;
3e73aa7c 1150
ccc9c027
L		 1151 /* We need to decide which NOP sequence to use for 32bit and
1152 64bit. When -mtune= is used:
4eed87de 1153
76bc74dc
L		 1154 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1155 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1156 2. For the rest, alt_patt will be used.
1157
1158 When -mtune= isn't used, alt_patt will be used if
22109423 1159 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1160 be used.
ccc9c027
L		 1161
1162 When -march= or .arch is used, we can't use anything beyond
1163 cpu_arch_isa_flags. */
1164
1165 if (flag_code == CODE_16BIT)
1166 {
ccc9c027 1167 if (count > 8)
33fef721 1168 {
76bc74dc
L		 1169 memcpy (fragP->fr_literal + fragP->fr_fix,
1170 jump_31, count);
1171 /* Adjust jump offset. */
1172 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1173 }
76bc74dc
L		 1174 else
1175 memcpy (fragP->fr_literal + fragP->fr_fix,
1176 f16_patt[count - 1], count);
252b5132 1177 }
33fef721 1178 else
ccc9c027
L		 1179 {
1180 const char *const *patt = NULL;
1181
fbf3f584 1182 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1183 {
1184 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1185 switch (cpu_arch_tune)
1186 {
1187 case PROCESSOR_UNKNOWN:
1188 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1189 optimize with nops. */
1190 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1191 patt = alt_patt;
ccc9c027
L		 1192 else
1193 patt = f32_patt;
1194 break;
ccc9c027
L		 1195 case PROCESSOR_PENTIUM4:
1196 case PROCESSOR_NOCONA:
ef05d495 1197 case PROCESSOR_CORE:
76bc74dc 1198 case PROCESSOR_CORE2:
bd5295b2 1199 case PROCESSOR_COREI7:
3632d14b 1200 case PROCESSOR_L1OM:
7a9068fe 1201 case PROCESSOR_K1OM:
76bc74dc 1202 case PROCESSOR_GENERIC64:
ccc9c027
L		 1203 case PROCESSOR_K6:
1204 case PROCESSOR_ATHLON:
1205 case PROCESSOR_K8:
4eed87de 1206 case PROCESSOR_AMDFAM10:
8aedb9fe 1207 case PROCESSOR_BD:
029f3522 1208 case PROCESSOR_ZNVER:
7b458c12 1209 case PROCESSOR_BT:
80b8656c 1210 patt = alt_patt;
ccc9c027 1211 break;
76bc74dc 1212 case PROCESSOR_I386:
ccc9c027
L		 1213 case PROCESSOR_I486:
1214 case PROCESSOR_PENTIUM:
2dde1948 1215 case PROCESSOR_PENTIUMPRO:
ccc9c027
L		 1216 case PROCESSOR_GENERIC32:
1217 patt = f32_patt;
1218 break;
4eed87de 1219 }
ccc9c027
L		 1220 }
1221 else
1222 {
fbf3f584 1223 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1224 {
1225 case PROCESSOR_UNKNOWN:
e6a14101 1226 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1227 PROCESSOR_UNKNOWN. */
1228 abort ();
1229 break;
1230
76bc74dc 1231 case PROCESSOR_I386:
ccc9c027
L		 1232 case PROCESSOR_I486:
1233 case PROCESSOR_PENTIUM:
ccc9c027
L		 1234 case PROCESSOR_K6:
1235 case PROCESSOR_ATHLON:
1236 case PROCESSOR_K8:
4eed87de 1237 case PROCESSOR_AMDFAM10:
8aedb9fe 1238 case PROCESSOR_BD:
029f3522 1239 case PROCESSOR_ZNVER:
7b458c12 1240 case PROCESSOR_BT:
ccc9c027
L		 1241 case PROCESSOR_GENERIC32:
1242 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1243 with nops. */
1244 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1245 patt = alt_patt;
ccc9c027
L		 1246 else
1247 patt = f32_patt;
1248 break;
76bc74dc
L		 1249 case PROCESSOR_PENTIUMPRO:
1250 case PROCESSOR_PENTIUM4:
1251 case PROCESSOR_NOCONA:
1252 case PROCESSOR_CORE:
ef05d495 1253 case PROCESSOR_CORE2:
bd5295b2 1254 case PROCESSOR_COREI7:
3632d14b 1255 case PROCESSOR_L1OM:
7a9068fe 1256 case PROCESSOR_K1OM:
22109423 1257 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1258 patt = alt_patt;
ccc9c027
L		 1259 else
1260 patt = f32_patt;
1261 break;
1262 case PROCESSOR_GENERIC64:
80b8656c 1263 patt = alt_patt;
ccc9c027 1264 break;
4eed87de 1265 }
ccc9c027
L		 1266 }
1267
76bc74dc
L		 1268 if (patt == f32_patt)
1269 {
1270 /* If the padding is less than 15 bytes, we use the normal
1271 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1272 its offset. */
1273 int limit;
76ba9986 1274
711eedef
L		 1275 /* For 64bit, the limit is 3 bytes. */
1276 if (flag_code == CODE_64BIT
1277 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1278 limit = 3;
1279 else
1280 limit = 15;
1281 if (count < limit)
76bc74dc
L		 1282 memcpy (fragP->fr_literal + fragP->fr_fix,
1283 patt[count - 1], count);
1284 else
1285 {
1286 memcpy (fragP->fr_literal + fragP->fr_fix,
1287 jump_31, count);
1288 /* Adjust jump offset. */
1289 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1290 }
1291 }
1292 else
1293 {
80b8656c
L		 1294 /* Maximum length of an instruction is 10 byte. If the
1295 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1296 we have to break it into smaller pieces. */
1297 int padding = count;
80b8656c 1298 while (padding > 10)
76bc74dc 1299 {
80b8656c 1300 padding -= 10;
76bc74dc 1301 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1302 patt [9], 10);
76bc74dc
L		 1303 }
1304
1305 if (padding)
1306 memcpy (fragP->fr_literal + fragP->fr_fix,
1307 patt [padding - 1], padding);
1308 }
ccc9c027 1309 }
33fef721 1310 fragP->fr_var = count;
252b5132
RH		 1311}
1312
c6fb90c8 1313static INLINE int
0dfbf9d7 1314operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1315{
0dfbf9d7 1316 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1317 {
1318 case 3:
0dfbf9d7 1319 if (x->array[2])
c6fb90c8
L		 1320 return 0;
1321 case 2:
0dfbf9d7 1322 if (x->array[1])
c6fb90c8
L		 1323 return 0;
1324 case 1:
0dfbf9d7 1325 return !x->array[0];
c6fb90c8
L		 1326 default:
1327 abort ();
1328 }
40fb9820
L		 1329}
1330
c6fb90c8 1331static INLINE void
0dfbf9d7 1332operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1333{
0dfbf9d7 1334 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1335 {
1336 case 3:
0dfbf9d7 1337 x->array[2] = v;
c6fb90c8 1338 case 2:
0dfbf9d7 1339 x->array[1] = v;
c6fb90c8 1340 case 1:
0dfbf9d7 1341 x->array[0] = v;
c6fb90c8
L		 1342 break;
1343 default:
1344 abort ();
1345 }
1346}
40fb9820 1347
c6fb90c8 1348static INLINE int
0dfbf9d7
L		 1349operand_type_equal (const union i386_operand_type *x,
1350 const union i386_operand_type *y)
c6fb90c8 1351{
0dfbf9d7 1352 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1353 {
1354 case 3:
0dfbf9d7 1355 if (x->array[2] != y->array[2])
c6fb90c8
L		 1356 return 0;
1357 case 2:
0dfbf9d7 1358 if (x->array[1] != y->array[1])
c6fb90c8
L		 1359 return 0;
1360 case 1:
0dfbf9d7 1361 return x->array[0] == y->array[0];
c6fb90c8
L		 1362 break;
1363 default:
1364 abort ();
1365 }
1366}
40fb9820 1367
0dfbf9d7
L		 1368static INLINE int
1369cpu_flags_all_zero (const union i386_cpu_flags *x)
1370{
1371 switch (ARRAY_SIZE(x->array))
1372 {
1373 case 3:
1374 if (x->array[2])
1375 return 0;
1376 case 2:
1377 if (x->array[1])
1378 return 0;
1379 case 1:
1380 return !x->array[0];
1381 default:
1382 abort ();
1383 }
1384}
1385
0dfbf9d7
L		 1386static INLINE int
1387cpu_flags_equal (const union i386_cpu_flags *x,
1388 const union i386_cpu_flags *y)
1389{
1390 switch (ARRAY_SIZE(x->array))
1391 {
1392 case 3:
1393 if (x->array[2] != y->array[2])
1394 return 0;
1395 case 2:
1396 if (x->array[1] != y->array[1])
1397 return 0;
1398 case 1:
1399 return x->array[0] == y->array[0];
1400 break;
1401 default:
1402 abort ();
1403 }
1404}
c6fb90c8
L		 1405
1406static INLINE int
1407cpu_flags_check_cpu64 (i386_cpu_flags f)
1408{
1409 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1410 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1411}
1412
c6fb90c8
L		 1413static INLINE i386_cpu_flags
1414cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1415{
c6fb90c8
L		 1416 switch (ARRAY_SIZE (x.array))
1417 {
1418 case 3:
1419 x.array [2] &= y.array [2];
1420 case 2:
1421 x.array [1] &= y.array [1];
1422 case 1:
1423 x.array [0] &= y.array [0];
1424 break;
1425 default:
1426 abort ();
1427 }
1428 return x;
1429}
40fb9820 1430
c6fb90c8
L		 1431static INLINE i386_cpu_flags
1432cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1433{
c6fb90c8 1434 switch (ARRAY_SIZE (x.array))
40fb9820 1435 {
c6fb90c8
L		 1436 case 3:
1437 x.array [2] |= y.array [2];
1438 case 2:
1439 x.array [1] |= y.array [1];
1440 case 1:
1441 x.array [0] |= y.array [0];
40fb9820
L		 1442 break;
1443 default:
1444 abort ();
1445 }
40fb9820
L		 1446 return x;
1447}
1448
309d3373
JB		 1449static INLINE i386_cpu_flags
1450cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1451{
1452 switch (ARRAY_SIZE (x.array))
1453 {
1454 case 3:
1455 x.array [2] &= ~y.array [2];
1456 case 2:
1457 x.array [1] &= ~y.array [1];
1458 case 1:
1459 x.array [0] &= ~y.array [0];
1460 break;
1461 default:
1462 abort ();
1463 }
1464 return x;
1465}
1466
c0f3af97
L		 1467#define CPU_FLAGS_ARCH_MATCH 0x1
1468#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1469#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1470#define CPU_FLAGS_PCLMUL_MATCH 0x8
1471#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1472
a5ff0eb2 1473#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1474 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1475 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1476#define CPU_FLAGS_PERFECT_MATCH \
1477 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1478
1479/* Return CPU flags match bits. */
3629bb00 1480
40fb9820 1481static int
d3ce72d0 1482cpu_flags_match (const insn_template *t)
40fb9820 1483{
c0f3af97
L		 1484 i386_cpu_flags x = t->cpu_flags;
1485 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1486
1487 x.bitfield.cpu64 = 0;
1488 x.bitfield.cpuno64 = 0;
1489
0dfbf9d7 1490 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1491 {
1492 /* This instruction is available on all archs. */
1493 match |= CPU_FLAGS_32BIT_MATCH;
1494 }
3629bb00
L		 1495 else
1496 {
c0f3af97 1497 /* This instruction is available only on some archs. */
3629bb00
L		 1498 i386_cpu_flags cpu = cpu_arch_flags;
1499
1500 cpu.bitfield.cpu64 = 0;
1501 cpu.bitfield.cpuno64 = 0;
1502 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1503 if (!cpu_flags_all_zero (&cpu))
1504 {
a5ff0eb2
L		 1505 if (x.bitfield.cpuavx)
1506 {
ce2f5b3c 1507 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1508 if (cpu.bitfield.cpuavx)
1509 {
1510 /* Check SSE2AVX. */
1511 if (!t->opcode_modifier.sse2avx|| sse2avx)
1512 {
1513 match |= (CPU_FLAGS_ARCH_MATCH
1514 | CPU_FLAGS_AVX_MATCH);
1515 /* Check AES. */
1516 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1517 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1518 /* Check PCLMUL. */
1519 if (!x.bitfield.cpupclmul
1520 || cpu.bitfield.cpupclmul)
1521 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1522 }
1523 }
1524 else
1525 match |= CPU_FLAGS_ARCH_MATCH;
1526 }
1527 else
c0f3af97
L		 1528 match |= CPU_FLAGS_32BIT_MATCH;
1529 }
3629bb00 1530 }
c0f3af97 1531 return match;
40fb9820
L		 1532}
1533
c6fb90c8
L		 1534static INLINE i386_operand_type
1535operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1536{
c6fb90c8
L		 1537 switch (ARRAY_SIZE (x.array))
1538 {
1539 case 3:
1540 x.array [2] &= y.array [2];
1541 case 2:
1542 x.array [1] &= y.array [1];
1543 case 1:
1544 x.array [0] &= y.array [0];
1545 break;
1546 default:
1547 abort ();
1548 }
1549 return x;
40fb9820
L		 1550}
1551
c6fb90c8
L		 1552static INLINE i386_operand_type
1553operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1554{
c6fb90c8 1555 switch (ARRAY_SIZE (x.array))
40fb9820 1556 {
c6fb90c8
L		 1557 case 3:
1558 x.array [2] |= y.array [2];
1559 case 2:
1560 x.array [1] |= y.array [1];
1561 case 1:
1562 x.array [0] |= y.array [0];
40fb9820
L		 1563 break;
1564 default:
1565 abort ();
1566 }
c6fb90c8
L		 1567 return x;
1568}
40fb9820 1569
c6fb90c8
L		 1570static INLINE i386_operand_type
1571operand_type_xor (i386_operand_type x, i386_operand_type y)
1572{
1573 switch (ARRAY_SIZE (x.array))
1574 {
1575 case 3:
1576 x.array [2] ^= y.array [2];
1577 case 2:
1578 x.array [1] ^= y.array [1];
1579 case 1:
1580 x.array [0] ^= y.array [0];
1581 break;
1582 default:
1583 abort ();
1584 }
40fb9820
L		 1585 return x;
1586}
1587
1588static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1589static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1590static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1591static const i386_operand_type inoutportreg
1592 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1593static const i386_operand_type reg16_inoutportreg
1594 = OPERAND_TYPE_REG16_INOUTPORTREG;
1595static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1596static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1597static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1598static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1599static const i386_operand_type anydisp
1600 = OPERAND_TYPE_ANYDISP;
40fb9820 1601static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1602static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1603static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1604static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1605static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1606static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1607static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1608static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1609static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1610static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1611static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1612static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1613static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1614static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1615
1616enum operand_type
1617{
1618 reg,
40fb9820
L		 1619 imm,
1620 disp,
1621 anymem
1622};
1623
c6fb90c8 1624static INLINE int
40fb9820
L		 1625operand_type_check (i386_operand_type t, enum operand_type c)
1626{
1627 switch (c)
1628 {
1629 case reg:
1630 return (t.bitfield.reg8
1631 || t.bitfield.reg16
1632 || t.bitfield.reg32
1633 || t.bitfield.reg64);
1634
40fb9820
L		 1635 case imm:
1636 return (t.bitfield.imm8
1637 || t.bitfield.imm8s
1638 || t.bitfield.imm16
1639 || t.bitfield.imm32
1640 || t.bitfield.imm32s
1641 || t.bitfield.imm64);
1642
1643 case disp:
1644 return (t.bitfield.disp8
1645 || t.bitfield.disp16
1646 || t.bitfield.disp32
1647 || t.bitfield.disp32s
1648 || t.bitfield.disp64);
1649
1650 case anymem:
1651 return (t.bitfield.disp8
1652 || t.bitfield.disp16
1653 || t.bitfield.disp32
1654 || t.bitfield.disp32s
1655 || t.bitfield.disp64
1656 || t.bitfield.baseindex);
1657
1658 default:
1659 abort ();
1660 }
2cfe26b6
AM		 1661
1662 return 0;
40fb9820
L		 1663}
1664
5c07affc
L		 1665/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1666 operand J for instruction template T. */
1667
1668static INLINE int
d3ce72d0 1669match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1670{
1671 return !((i.types[j].bitfield.byte
1672 && !t->operand_types[j].bitfield.byte)
1673 || (i.types[j].bitfield.word
1674 && !t->operand_types[j].bitfield.word)
1675 || (i.types[j].bitfield.dword
1676 && !t->operand_types[j].bitfield.dword)
1677 || (i.types[j].bitfield.qword
1678 && !t->operand_types[j].bitfield.qword));
1679}
1680
1681/* Return 1 if there is no conflict in any size on operand J for
1682 instruction template T. */
1683
1684static INLINE int
d3ce72d0 1685match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1686{
1687 return (match_reg_size (t, j)
1688 && !((i.types[j].bitfield.unspecified
af508cb9 1689 && !i.broadcast
5c07affc
L		 1690 && !t->operand_types[j].bitfield.unspecified)
1691 || (i.types[j].bitfield.fword
1692 && !t->operand_types[j].bitfield.fword)
1693 || (i.types[j].bitfield.tbyte
1694 && !t->operand_types[j].bitfield.tbyte)
1695 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1696 && !t->operand_types[j].bitfield.xmmword)
1697 || (i.types[j].bitfield.ymmword
43234a1e
L		 1698 && !t->operand_types[j].bitfield.ymmword)
1699 || (i.types[j].bitfield.zmmword
1700 && !t->operand_types[j].bitfield.zmmword)));
5c07affc
L		 1701}
1702
1703/* Return 1 if there is no size conflict on any operands for
1704 instruction template T. */
1705
1706static INLINE int
d3ce72d0 1707operand_size_match (const insn_template *t)
5c07affc
L		 1708{
1709 unsigned int j;
1710 int match = 1;
1711
1712 /* Don't check jump instructions. */
1713 if (t->opcode_modifier.jump
1714 || t->opcode_modifier.jumpbyte
1715 || t->opcode_modifier.jumpdword
1716 || t->opcode_modifier.jumpintersegment)
1717 return match;
1718
1719 /* Check memory and accumulator operand size. */
1720 for (j = 0; j < i.operands; j++)
1721 {
1722 if (t->operand_types[j].bitfield.anysize)
1723 continue;
1724
1725 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1726 {
1727 match = 0;
1728 break;
1729 }
1730
1731 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1732 {
1733 match = 0;
1734 break;
1735 }
1736 }
1737
891edac4 1738 if (match)
5c07affc 1739 return match;
891edac4
L		 1740 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1741 {
1742mismatch:
86e026a4 1743 i.error = operand_size_mismatch;
891edac4
L		 1744 return 0;
1745 }
5c07affc
L		 1746
1747 /* Check reverse. */
9c2799c2 1748 gas_assert (i.operands == 2);
5c07affc
L		 1749
1750 match = 1;
1751 for (j = 0; j < 2; j++)
1752 {
1753 if (t->operand_types[j].bitfield.acc
1754 && !match_reg_size (t, j ? 0 : 1))
891edac4 1755 goto mismatch;
5c07affc
L		 1756
1757 if (i.types[j].bitfield.mem
1758 && !match_mem_size (t, j ? 0 : 1))
891edac4 1759 goto mismatch;
5c07affc
L		 1760 }
1761
1762 return match;
1763}
1764
c6fb90c8 1765static INLINE int
40fb9820
L		 1766operand_type_match (i386_operand_type overlap,
1767 i386_operand_type given)
1768{
1769 i386_operand_type temp = overlap;
1770
1771 temp.bitfield.jumpabsolute = 0;
7d5e4556 1772 temp.bitfield.unspecified = 0;
5c07affc
L		 1773 temp.bitfield.byte = 0;
1774 temp.bitfield.word = 0;
1775 temp.bitfield.dword = 0;
1776 temp.bitfield.fword = 0;
1777 temp.bitfield.qword = 0;
1778 temp.bitfield.tbyte = 0;
1779 temp.bitfield.xmmword = 0;
c0f3af97 1780 temp.bitfield.ymmword = 0;
43234a1e 1781 temp.bitfield.zmmword = 0;
0dfbf9d7 1782 if (operand_type_all_zero (&temp))
891edac4 1783 goto mismatch;
40fb9820 1784
891edac4
L		 1785 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1786 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1787 return 1;
1788
1789mismatch:
a65babc9 1790 i.error = operand_type_mismatch;
891edac4 1791 return 0;
40fb9820
L		 1792}
1793
7d5e4556 1794/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1795 unless the expected operand type register overlap is null.
1796 Note that Acc in a template matches every size of reg. */
1797
c6fb90c8 1798static INLINE int
40fb9820
L		 1799operand_type_register_match (i386_operand_type m0,
1800 i386_operand_type g0,
1801 i386_operand_type t0,
1802 i386_operand_type m1,
1803 i386_operand_type g1,
1804 i386_operand_type t1)
1805{
1806 if (!operand_type_check (g0, reg))
1807 return 1;
1808
1809 if (!operand_type_check (g1, reg))
1810 return 1;
1811
1812 if (g0.bitfield.reg8 == g1.bitfield.reg8
1813 && g0.bitfield.reg16 == g1.bitfield.reg16
1814 && g0.bitfield.reg32 == g1.bitfield.reg32
1815 && g0.bitfield.reg64 == g1.bitfield.reg64)
1816 return 1;
1817
1818 if (m0.bitfield.acc)
1819 {
1820 t0.bitfield.reg8 = 1;
1821 t0.bitfield.reg16 = 1;
1822 t0.bitfield.reg32 = 1;
1823 t0.bitfield.reg64 = 1;
1824 }
1825
1826 if (m1.bitfield.acc)
1827 {
1828 t1.bitfield.reg8 = 1;
1829 t1.bitfield.reg16 = 1;
1830 t1.bitfield.reg32 = 1;
1831 t1.bitfield.reg64 = 1;
1832 }
1833
891edac4
L		 1834 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1835 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1836 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1837 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1838 return 1;
1839
a65babc9 1840 i.error = register_type_mismatch;
891edac4
L		 1841
1842 return 0;
40fb9820
L		 1843}
1844
4c692bc7
JB		 1845static INLINE unsigned int
1846register_number (const reg_entry *r)
1847{
1848 unsigned int nr = r->reg_num;
1849
1850 if (r->reg_flags & RegRex)
1851 nr += 8;
1852
1853 return nr;
1854}
1855
252b5132 1856static INLINE unsigned int
40fb9820 1857mode_from_disp_size (i386_operand_type t)
252b5132 1858{
43234a1e 1859 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
40fb9820
L		 1860 return 1;
1861 else if (t.bitfield.disp16
1862 || t.bitfield.disp32
1863 || t.bitfield.disp32s)
1864 return 2;
1865 else
1866 return 0;
252b5132
RH		 1867}
1868
1869static INLINE int
65879393 1870fits_in_signed_byte (addressT num)
252b5132 1871{
65879393 1872 return num + 0x80 <= 0xff;
47926f60 1873}
252b5132
RH		 1874
1875static INLINE int
65879393 1876fits_in_unsigned_byte (addressT num)
252b5132 1877{
65879393 1878 return num <= 0xff;
47926f60 1879}
252b5132
RH		 1880
1881static INLINE int
65879393 1882fits_in_unsigned_word (addressT num)
252b5132 1883{
65879393 1884 return num <= 0xffff;
47926f60 1885}
252b5132
RH		 1886
1887static INLINE int
65879393 1888fits_in_signed_word (addressT num)
252b5132 1889{
65879393 1890 return num + 0x8000 <= 0xffff;
47926f60 1891}
2a962e6d 1892
3e73aa7c 1893static INLINE int
65879393 1894fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1895{
1896#ifndef BFD64
1897 return 1;
1898#else
65879393 1899 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 1900#endif
1901} /* fits_in_signed_long() */
2a962e6d 1902
3e73aa7c 1903static INLINE int
65879393 1904fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1905{
1906#ifndef BFD64
1907 return 1;
1908#else
65879393 1909 return num <= 0xffffffff;
3e73aa7c
JH		 1910#endif
1911} /* fits_in_unsigned_long() */
252b5132 1912
43234a1e
L		 1913static INLINE int
1914fits_in_vec_disp8 (offsetT num)
1915{
1916 int shift = i.memshift;
1917 unsigned int mask;
1918
1919 if (shift == -1)
1920 abort ();
1921
1922 mask = (1 << shift) - 1;
1923
1924 /* Return 0 if NUM isn't properly aligned. */
1925 if ((num & mask))
1926 return 0;
1927
1928 /* Check if NUM will fit in 8bit after shift. */
1929 return fits_in_signed_byte (num >> shift);
1930}
1931
a683cc34
SP		 1932static INLINE int
1933fits_in_imm4 (offsetT num)
1934{
1935 return (num & 0xf) == num;
1936}
1937
40fb9820 1938static i386_operand_type
e3bb37b5 1939smallest_imm_type (offsetT num)
252b5132 1940{
40fb9820 1941 i386_operand_type t;
7ab9ffdd 1942
0dfbf9d7 1943 operand_type_set (&t, 0);
40fb9820
L		 1944 t.bitfield.imm64 = 1;
1945
1946 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1947 {
1948 /* This code is disabled on the 486 because all the Imm1 forms
1949 in the opcode table are slower on the i486. They're the
1950 versions with the implicitly specified single-position
1951 displacement, which has another syntax if you really want to
1952 use that form. */
40fb9820
L		 1953 t.bitfield.imm1 = 1;
1954 t.bitfield.imm8 = 1;
1955 t.bitfield.imm8s = 1;
1956 t.bitfield.imm16 = 1;
1957 t.bitfield.imm32 = 1;
1958 t.bitfield.imm32s = 1;
1959 }
1960 else if (fits_in_signed_byte (num))
1961 {
1962 t.bitfield.imm8 = 1;
1963 t.bitfield.imm8s = 1;
1964 t.bitfield.imm16 = 1;
1965 t.bitfield.imm32 = 1;
1966 t.bitfield.imm32s = 1;
1967 }
1968 else if (fits_in_unsigned_byte (num))
1969 {
1970 t.bitfield.imm8 = 1;
1971 t.bitfield.imm16 = 1;
1972 t.bitfield.imm32 = 1;
1973 t.bitfield.imm32s = 1;
1974 }
1975 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1976 {
1977 t.bitfield.imm16 = 1;
1978 t.bitfield.imm32 = 1;
1979 t.bitfield.imm32s = 1;
1980 }
1981 else if (fits_in_signed_long (num))
1982 {
1983 t.bitfield.imm32 = 1;
1984 t.bitfield.imm32s = 1;
1985 }
1986 else if (fits_in_unsigned_long (num))
1987 t.bitfield.imm32 = 1;
1988
1989 return t;
47926f60 1990}
252b5132 1991
847f7ad4 1992static offsetT
e3bb37b5 1993offset_in_range (offsetT val, int size)
847f7ad4 1994{
508866be 1995 addressT mask;
ba2adb93 1996
847f7ad4
AM		 1997 switch (size)
1998 {
508866be
L		 1999 case 1: mask = ((addressT) 1 << 8) - 1; break;
2000 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2001 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2002#ifdef BFD64
2003 case 8: mask = ((addressT) 2 << 63) - 1; break;
2004#endif
47926f60 2005 default: abort ();
847f7ad4
AM		 2006 }
2007
9de868bf
L		 2008#ifdef BFD64
2009 /* If BFD64, sign extend val for 32bit address mode. */
2010 if (flag_code != CODE_64BIT
2011 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2012 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2013 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2014#endif
ba2adb93 2015
47926f60 2016 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2017 {
2018 char buf1[40], buf2[40];
2019
2020 sprint_value (buf1, val);
2021 sprint_value (buf2, val & mask);
2022 as_warn (_("%s shortened to %s"), buf1, buf2);
2023 }
2024 return val & mask;
2025}
2026
c32fa91d
L		 2027enum PREFIX_GROUP
2028{
2029 PREFIX_EXIST = 0,
2030 PREFIX_LOCK,
2031 PREFIX_REP,
2032 PREFIX_OTHER
2033};
2034
2035/* Returns
2036 a. PREFIX_EXIST if attempting to add a prefix where one from the
2037 same class already exists.
2038 b. PREFIX_LOCK if lock prefix is added.
2039 c. PREFIX_REP if rep/repne prefix is added.
2040 d. PREFIX_OTHER if other prefix is added.
2041 */
2042
2043static enum PREFIX_GROUP
e3bb37b5 2044add_prefix (unsigned int prefix)
252b5132 2045{
c32fa91d 2046 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2047 unsigned int q;
252b5132 2048
29b0f896
AM		 2049 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2050 && flag_code == CODE_64BIT)
b1905489 2051 {
161a04f6
L		 2052 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2053 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2054 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2055 ret = PREFIX_EXIST;
b1905489
JB		 2056 q = REX_PREFIX;
2057 }
3e73aa7c 2058 else
b1905489
JB		 2059 {
2060 switch (prefix)
2061 {
2062 default:
2063 abort ();
2064
2065 case CS_PREFIX_OPCODE:
2066 case DS_PREFIX_OPCODE:
2067 case ES_PREFIX_OPCODE:
2068 case FS_PREFIX_OPCODE:
2069 case GS_PREFIX_OPCODE:
2070 case SS_PREFIX_OPCODE:
2071 q = SEG_PREFIX;
2072 break;
2073
2074 case REPNE_PREFIX_OPCODE:
2075 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2076 q = REP_PREFIX;
2077 ret = PREFIX_REP;
2078 break;
2079
b1905489 2080 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2081 q = LOCK_PREFIX;
2082 ret = PREFIX_LOCK;
b1905489
JB		 2083 break;
2084
2085 case FWAIT_OPCODE:
2086 q = WAIT_PREFIX;
2087 break;
2088
2089 case ADDR_PREFIX_OPCODE:
2090 q = ADDR_PREFIX;
2091 break;
2092
2093 case DATA_PREFIX_OPCODE:
2094 q = DATA_PREFIX;
2095 break;
2096 }
2097 if (i.prefix[q] != 0)
c32fa91d 2098 ret = PREFIX_EXIST;
b1905489 2099 }
252b5132 2100
b1905489 2101 if (ret)
252b5132 2102 {
b1905489
JB		 2103 if (!i.prefix[q])
2104 ++i.prefixes;
2105 i.prefix[q] |= prefix;
252b5132 2106 }
b1905489
JB		 2107 else
2108 as_bad (_("same type of prefix used twice"));
252b5132 2109
252b5132
RH		 2110 return ret;
2111}
2112
2113static void
78f12dd3 2114update_code_flag (int value, int check)
eecb386c 2115{
78f12dd3
L		 2116 PRINTF_LIKE ((*as_error));
2117
1e9cc1c2 2118 flag_code = (enum flag_code) value;
40fb9820
L		 2119 if (flag_code == CODE_64BIT)
2120 {
2121 cpu_arch_flags.bitfield.cpu64 = 1;
2122 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2123 }
2124 else
2125 {
2126 cpu_arch_flags.bitfield.cpu64 = 0;
2127 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2128 }
2129 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2130 {
78f12dd3
L		 2131 if (check)
2132 as_error = as_fatal;
2133 else
2134 as_error = as_bad;
2135 (*as_error) (_("64bit mode not supported on `%s'."),
2136 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2137 }
40fb9820 2138 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2139 {
78f12dd3
L		 2140 if (check)
2141 as_error = as_fatal;
2142 else
2143 as_error = as_bad;
2144 (*as_error) (_("32bit mode not supported on `%s'."),
2145 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2146 }
eecb386c
AM		 2147 stackop_size = '\0';
2148}
2149
78f12dd3
L		 2150static void
2151set_code_flag (int value)
2152{
2153 update_code_flag (value, 0);
2154}
2155
eecb386c 2156static void
e3bb37b5 2157set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2158{
1e9cc1c2 2159 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2160 if (flag_code != CODE_16BIT)
2161 abort ();
2162 cpu_arch_flags.bitfield.cpu64 = 0;
2163 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2164 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2165}
2166
2167static void
e3bb37b5 2168set_intel_syntax (int syntax_flag)
252b5132
RH		 2169{
2170 /* Find out if register prefixing is specified. */
2171 int ask_naked_reg = 0;
2172
2173 SKIP_WHITESPACE ();
29b0f896 2174 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 2175 {
2176 char *string = input_line_pointer;
2177 int e = get_symbol_end ();
2178
47926f60 2179 if (strcmp (string, "prefix") == 0)
252b5132 2180 ask_naked_reg = 1;
47926f60 2181 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2182 ask_naked_reg = -1;
2183 else
d0b47220 2184 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 2185 *input_line_pointer = e;
2186 }
2187 demand_empty_rest_of_line ();
c3332e24 2188
252b5132
RH		 2189 intel_syntax = syntax_flag;
2190
2191 if (ask_naked_reg == 0)
f86103b7
AM		 2192 allow_naked_reg = (intel_syntax
2193 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2194 else
2195 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2196
ee86248c 2197 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2198
e4a3b5a4 2199 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2200 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2201 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2202}
2203
1efbbeb4
L		 2204static void
2205set_intel_mnemonic (int mnemonic_flag)
2206{
e1d4d893 2207 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2208}
2209
db51cc60
L		 2210static void
2211set_allow_index_reg (int flag)
2212{
2213 allow_index_reg = flag;
2214}
2215
cb19c032 2216static void
7bab8ab5 2217set_check (int what)
cb19c032 2218{
7bab8ab5
JB		 2219 enum check_kind *kind;
2220 const char *str;
2221
2222 if (what)
2223 {
2224 kind = &operand_check;
2225 str = "operand";
2226 }
2227 else
2228 {
2229 kind = &sse_check;
2230 str = "sse";
2231 }
2232
cb19c032
L		 2233 SKIP_WHITESPACE ();
2234
2235 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2236 {
2237 char *string = input_line_pointer;
2238 int e = get_symbol_end ();
2239
2240 if (strcmp (string, "none") == 0)
7bab8ab5 2241 *kind = check_none;
cb19c032 2242 else if (strcmp (string, "warning") == 0)
7bab8ab5 2243 *kind = check_warning;
cb19c032 2244 else if (strcmp (string, "error") == 0)
7bab8ab5 2245 *kind = check_error;
cb19c032 2246 else
7bab8ab5 2247 as_bad (_("bad argument to %s_check directive."), str);
cb19c032
L		 2248 *input_line_pointer = e;
2249 }
2250 else
7bab8ab5 2251 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2252
2253 demand_empty_rest_of_line ();
2254}
2255
8a9036a4
L		 2256static void
2257check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2258 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2259{
2260#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2261 static const char *arch;
2262
2263 /* Intel LIOM is only supported on ELF. */
2264 if (!IS_ELF)
2265 return;
2266
2267 if (!arch)
2268 {
2269 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2270 use default_arch. */
2271 arch = cpu_arch_name;
2272 if (!arch)
2273 arch = default_arch;
2274 }
2275
3632d14b 2276 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2277 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2278 || new_flag.bitfield.cpul1om)
8a9036a4 2279 return;
76ba9986 2280
7a9068fe
L		 2281 /* If we are targeting Intel K1OM, we must enable it. */
2282 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2283 || new_flag.bitfield.cpuk1om)
2284 return;
2285
8a9036a4
L		 2286 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2287#endif
2288}
2289
e413e4e9 2290static void
e3bb37b5 2291set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2292{
47926f60 2293 SKIP_WHITESPACE ();
e413e4e9 2294
29b0f896 2295 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 2296 {
2297 char *string = input_line_pointer;
2298 int e = get_symbol_end ();
91d6fa6a 2299 unsigned int j;
40fb9820 2300 i386_cpu_flags flags;
e413e4e9 2301
91d6fa6a 2302 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2303 {
91d6fa6a 2304 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2305 {
91d6fa6a 2306 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2307
5c6af06e
JB		 2308 if (*string != '.')
2309 {
91d6fa6a 2310 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2311 cpu_sub_arch_name = NULL;
91d6fa6a 2312 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2313 if (flag_code == CODE_64BIT)
2314 {
2315 cpu_arch_flags.bitfield.cpu64 = 1;
2316 cpu_arch_flags.bitfield.cpuno64 = 0;
2317 }
2318 else
2319 {
2320 cpu_arch_flags.bitfield.cpu64 = 0;
2321 cpu_arch_flags.bitfield.cpuno64 = 1;
2322 }
91d6fa6a
NC		 2323 cpu_arch_isa = cpu_arch[j].type;
2324 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2325 if (!cpu_arch_tune_set)
2326 {
2327 cpu_arch_tune = cpu_arch_isa;
2328 cpu_arch_tune_flags = cpu_arch_isa_flags;
2329 }
5c6af06e
JB		 2330 break;
2331 }
40fb9820 2332
22109423 2333 if (!cpu_arch[j].negated)
309d3373 2334 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 2335 cpu_arch[j].flags);
309d3373
JB		 2336 else
2337 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 2338 cpu_arch[j].flags);
0dfbf9d7 2339 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2340 {
6305a203
L		 2341 if (cpu_sub_arch_name)
2342 {
2343 char *name = cpu_sub_arch_name;
2344 cpu_sub_arch_name = concat (name,
91d6fa6a 2345 cpu_arch[j].name,
1bf57e9f 2346 (const char *) NULL);
6305a203
L		 2347 free (name);
2348 }
2349 else
91d6fa6a 2350 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2351 cpu_arch_flags = flags;
a586129e 2352 cpu_arch_isa_flags = flags;
5c6af06e
JB		 2353 }
2354 *input_line_pointer = e;
2355 demand_empty_rest_of_line ();
2356 return;
e413e4e9
AM		 2357 }
2358 }
91d6fa6a 2359 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2360 as_bad (_("no such architecture: `%s'"), string);
2361
2362 *input_line_pointer = e;
2363 }
2364 else
2365 as_bad (_("missing cpu architecture"));
2366
fddf5b5b
AM		 2367 no_cond_jump_promotion = 0;
2368 if (*input_line_pointer == ','
29b0f896 2369 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2370 {
2371 char *string = ++input_line_pointer;
2372 int e = get_symbol_end ();
2373
2374 if (strcmp (string, "nojumps") == 0)
2375 no_cond_jump_promotion = 1;
2376 else if (strcmp (string, "jumps") == 0)
2377 ;
2378 else
2379 as_bad (_("no such architecture modifier: `%s'"), string);
2380
2381 *input_line_pointer = e;
2382 }
2383
e413e4e9
AM		 2384 demand_empty_rest_of_line ();
2385}
2386
8a9036a4
L		 2387enum bfd_architecture
2388i386_arch (void)
2389{
3632d14b 2390 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2391 {
2392 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2393 || flag_code != CODE_64BIT)
2394 as_fatal (_("Intel L1OM is 64bit ELF only"));
2395 return bfd_arch_l1om;
2396 }
7a9068fe
L		 2397 else if (cpu_arch_isa == PROCESSOR_K1OM)
2398 {
2399 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2400 || flag_code != CODE_64BIT)
2401 as_fatal (_("Intel K1OM is 64bit ELF only"));
2402 return bfd_arch_k1om;
2403 }
8a9036a4
L		 2404 else
2405 return bfd_arch_i386;
2406}
2407
b9d79e03 2408unsigned long
7016a5d5 2409i386_mach (void)
b9d79e03 2410{
351f65ca 2411 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2412 {
3632d14b 2413 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2414 {
351f65ca
L		 2415 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2416 || default_arch[6] != '\0')
8a9036a4
L		 2417 as_fatal (_("Intel L1OM is 64bit ELF only"));
2418 return bfd_mach_l1om;
2419 }
7a9068fe
L		 2420 else if (cpu_arch_isa == PROCESSOR_K1OM)
2421 {
2422 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2423 || default_arch[6] != '\0')
2424 as_fatal (_("Intel K1OM is 64bit ELF only"));
2425 return bfd_mach_k1om;
2426 }
351f65ca 2427 else if (default_arch[6] == '\0')
8a9036a4 2428 return bfd_mach_x86_64;
351f65ca
L		 2429 else
2430 return bfd_mach_x64_32;
8a9036a4 2431 }
b9d79e03
JH		 2432 else if (!strcmp (default_arch, "i386"))
2433 return bfd_mach_i386_i386;
2434 else
2b5d6a91 2435 as_fatal (_("unknown architecture"));
b9d79e03 2436}
b9d79e03 2437\f
252b5132 2438void
7016a5d5 2439md_begin (void)
252b5132
RH		 2440{
2441 const char *hash_err;
2442
47926f60 2443 /* Initialize op_hash hash table. */
252b5132
RH		 2444 op_hash = hash_new ();
2445
2446 {
d3ce72d0 2447 const insn_template *optab;
29b0f896 2448 templates *core_optab;
252b5132 2449
47926f60
KH		 2450 /* Setup for loop. */
2451 optab = i386_optab;
252b5132
RH		 2452 core_optab = (templates *) xmalloc (sizeof (templates));
2453 core_optab->start = optab;
2454
2455 while (1)
2456 {
2457 ++optab;
2458 if (optab->name == NULL
2459 || strcmp (optab->name, (optab - 1)->name) != 0)
2460 {
2461 /* different name --> ship out current template list;
47926f60 2462 add to hash table; & begin anew. */
252b5132
RH		 2463 core_optab->end = optab;
2464 hash_err = hash_insert (op_hash,
2465 (optab - 1)->name,
5a49b8ac 2466 (void *) core_optab);
252b5132
RH		 2467 if (hash_err)
2468 {
b37df7c4 2469 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2470 (optab - 1)->name,
2471 hash_err);
2472 }
2473 if (optab->name == NULL)
2474 break;
2475 core_optab = (templates *) xmalloc (sizeof (templates));
2476 core_optab->start = optab;
2477 }
2478 }
2479 }
2480
47926f60 2481 /* Initialize reg_hash hash table. */
252b5132
RH		 2482 reg_hash = hash_new ();
2483 {
29b0f896 2484 const reg_entry *regtab;
c3fe08fa 2485 unsigned int regtab_size = i386_regtab_size;
252b5132 2486
c3fe08fa 2487 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2488 {
5a49b8ac 2489 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2490 if (hash_err)
b37df7c4 2491 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2492 regtab->reg_name,
2493 hash_err);
252b5132
RH		 2494 }
2495 }
2496
47926f60 2497 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2498 {
29b0f896
AM		 2499 int c;
2500 char *p;
252b5132
RH		 2501
2502 for (c = 0; c < 256; c++)
2503 {
3882b010 2504 if (ISDIGIT (c))
252b5132
RH		 2505 {
2506 digit_chars[c] = c;
2507 mnemonic_chars[c] = c;
2508 register_chars[c] = c;
2509 operand_chars[c] = c;
2510 }
3882b010 2511 else if (ISLOWER (c))
252b5132
RH		 2512 {
2513 mnemonic_chars[c] = c;
2514 register_chars[c] = c;
2515 operand_chars[c] = c;
2516 }
3882b010 2517 else if (ISUPPER (c))
252b5132 2518 {
3882b010 2519 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2520 register_chars[c] = mnemonic_chars[c];
2521 operand_chars[c] = c;
2522 }
43234a1e
L		 2523 else if (c == '{' || c == '}')
2524 operand_chars[c] = c;
252b5132 2525
3882b010 2526 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2527 identifier_chars[c] = c;
2528 else if (c >= 128)
2529 {
2530 identifier_chars[c] = c;
2531 operand_chars[c] = c;
2532 }
2533 }
2534
2535#ifdef LEX_AT
2536 identifier_chars['@'] = '@';
32137342
NC		 2537#endif
2538#ifdef LEX_QM
2539 identifier_chars['?'] = '?';
2540 operand_chars['?'] = '?';
252b5132 2541#endif
252b5132 2542 digit_chars['-'] = '-';
c0f3af97 2543 mnemonic_chars['_'] = '_';
791fe849 2544 mnemonic_chars['-'] = '-';
0003779b 2545 mnemonic_chars['.'] = '.';
252b5132
RH		 2546 identifier_chars['_'] = '_';
2547 identifier_chars['.'] = '.';
2548
2549 for (p = operand_special_chars; *p != '\0'; p++)
2550 operand_chars[(unsigned char) *p] = *p;
2551 }
2552
a4447b93
RH		 2553 if (flag_code == CODE_64BIT)
2554 {
ca19b261
KT		 2555#if defined (OBJ_COFF) && defined (TE_PE)
2556 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2557 ? 32 : 16);
2558#else
a4447b93 2559 x86_dwarf2_return_column = 16;
ca19b261 2560#endif
61ff971f 2561 x86_cie_data_alignment = -8;
a4447b93
RH		 2562 }
2563 else
2564 {
2565 x86_dwarf2_return_column = 8;
2566 x86_cie_data_alignment = -4;
2567 }
252b5132
RH		 2568}
2569
2570void
e3bb37b5 2571i386_print_statistics (FILE *file)
252b5132
RH		 2572{
2573 hash_print_statistics (file, "i386 opcode", op_hash);
2574 hash_print_statistics (file, "i386 register", reg_hash);
2575}
2576\f
252b5132
RH		 2577#ifdef DEBUG386
2578
ce8a8b2f 2579/* Debugging routines for md_assemble. */
d3ce72d0 2580static void pte (insn_template *);
40fb9820 2581static void pt (i386_operand_type);
e3bb37b5
L		 2582static void pe (expressionS *);
2583static void ps (symbolS *);
252b5132
RH		 2584
2585static void
e3bb37b5 2586pi (char *line, i386_insn *x)
252b5132 2587{
09137c09 2588 unsigned int j;
252b5132
RH		 2589
2590 fprintf (stdout, "%s: template ", line);
2591 pte (&x->tm);
09f131f2
JH		 2592 fprintf (stdout, " address: base %s index %s scale %x\n",
2593 x->base_reg ? x->base_reg->reg_name : "none",
2594 x->index_reg ? x->index_reg->reg_name : "none",
2595 x->log2_scale_factor);
2596 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2597 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2598 fprintf (stdout, " sib: base %x index %x scale %x\n",
2599 x->sib.base, x->sib.index, x->sib.scale);
2600 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2601 (x->rex & REX_W) != 0,
2602 (x->rex & REX_R) != 0,
2603 (x->rex & REX_X) != 0,
2604 (x->rex & REX_B) != 0);
09137c09 2605 for (j = 0; j < x->operands; j++)
252b5132 2606 {
09137c09
SP		 2607 fprintf (stdout, " #%d: ", j + 1);
2608 pt (x->types[j]);
252b5132 2609 fprintf (stdout, "\n");
09137c09
SP		 2610 if (x->types[j].bitfield.reg8
2611 || x->types[j].bitfield.reg16
2612 || x->types[j].bitfield.reg32
2613 || x->types[j].bitfield.reg64
2614 || x->types[j].bitfield.regmmx
2615 || x->types[j].bitfield.regxmm
2616 || x->types[j].bitfield.regymm
43234a1e 2617 || x->types[j].bitfield.regzmm
09137c09
SP		 2618 || x->types[j].bitfield.sreg2
2619 || x->types[j].bitfield.sreg3
2620 || x->types[j].bitfield.control
2621 || x->types[j].bitfield.debug
2622 || x->types[j].bitfield.test)
2623 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2624 if (operand_type_check (x->types[j], imm))
2625 pe (x->op[j].imms);
2626 if (operand_type_check (x->types[j], disp))
2627 pe (x->op[j].disps);
252b5132
RH		 2628 }
2629}
2630
2631static void
d3ce72d0 2632pte (insn_template *t)
252b5132 2633{
09137c09 2634 unsigned int j;
252b5132 2635 fprintf (stdout, " %d operands ", t->operands);
47926f60 2636 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2637 if (t->extension_opcode != None)
2638 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2639 if (t->opcode_modifier.d)
252b5132 2640 fprintf (stdout, "D");
40fb9820 2641 if (t->opcode_modifier.w)
252b5132
RH		 2642 fprintf (stdout, "W");
2643 fprintf (stdout, "\n");
09137c09 2644 for (j = 0; j < t->operands; j++)
252b5132 2645 {
09137c09
SP		 2646 fprintf (stdout, " #%d type ", j + 1);
2647 pt (t->operand_types[j]);
252b5132
RH		 2648 fprintf (stdout, "\n");
2649 }
2650}
2651
2652static void
e3bb37b5 2653pe (expressionS *e)
252b5132 2654{
24eab124 2655 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2656 fprintf (stdout, " add_number %ld (%lx)\n",
2657 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2658 if (e->X_add_symbol)
2659 {
2660 fprintf (stdout, " add_symbol ");
2661 ps (e->X_add_symbol);
2662 fprintf (stdout, "\n");
2663 }
2664 if (e->X_op_symbol)
2665 {
2666 fprintf (stdout, " op_symbol ");
2667 ps (e->X_op_symbol);
2668 fprintf (stdout, "\n");
2669 }
2670}
2671
2672static void
e3bb37b5 2673ps (symbolS *s)
252b5132
RH		 2674{
2675 fprintf (stdout, "%s type %s%s",
2676 S_GET_NAME (s),
2677 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2678 segment_name (S_GET_SEGMENT (s)));
2679}
2680
7b81dfbb 2681static struct type_name
252b5132 2682 {
40fb9820
L		 2683 i386_operand_type mask;
2684 const char *name;
252b5132 2685 }
7b81dfbb 2686const type_names[] =
252b5132 2687{
40fb9820
L		 2688 { OPERAND_TYPE_REG8, "r8" },
2689 { OPERAND_TYPE_REG16, "r16" },
2690 { OPERAND_TYPE_REG32, "r32" },
2691 { OPERAND_TYPE_REG64, "r64" },
2692 { OPERAND_TYPE_IMM8, "i8" },
2693 { OPERAND_TYPE_IMM8, "i8s" },
2694 { OPERAND_TYPE_IMM16, "i16" },
2695 { OPERAND_TYPE_IMM32, "i32" },
2696 { OPERAND_TYPE_IMM32S, "i32s" },
2697 { OPERAND_TYPE_IMM64, "i64" },
2698 { OPERAND_TYPE_IMM1, "i1" },
2699 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2700 { OPERAND_TYPE_DISP8, "d8" },
2701 { OPERAND_TYPE_DISP16, "d16" },
2702 { OPERAND_TYPE_DISP32, "d32" },
2703 { OPERAND_TYPE_DISP32S, "d32s" },
2704 { OPERAND_TYPE_DISP64, "d64" },
43234a1e 2705 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
40fb9820
L		 2706 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2707 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2708 { OPERAND_TYPE_CONTROL, "control reg" },
2709 { OPERAND_TYPE_TEST, "test reg" },
2710 { OPERAND_TYPE_DEBUG, "debug reg" },
2711 { OPERAND_TYPE_FLOATREG, "FReg" },
2712 { OPERAND_TYPE_FLOATACC, "FAcc" },
2713 { OPERAND_TYPE_SREG2, "SReg2" },
2714 { OPERAND_TYPE_SREG3, "SReg3" },
2715 { OPERAND_TYPE_ACC, "Acc" },
2716 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2717 { OPERAND_TYPE_REGMMX, "rMMX" },
2718 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2719 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2720 { OPERAND_TYPE_REGZMM, "rZMM" },
2721 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2722 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2723};
2724
2725static void
40fb9820 2726pt (i386_operand_type t)
252b5132 2727{
40fb9820 2728 unsigned int j;
c6fb90c8 2729 i386_operand_type a;
252b5132 2730
40fb9820 2731 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2732 {
2733 a = operand_type_and (t, type_names[j].mask);
0349dc08 2734 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2735 fprintf (stdout, "%s, ", type_names[j].name);
2736 }
252b5132
RH		 2737 fflush (stdout);
2738}
2739
2740#endif /* DEBUG386 */
2741\f
252b5132 2742static bfd_reloc_code_real_type
3956db08 2743reloc (unsigned int size,
64e74474
AM		 2744 int pcrel,
2745 int sign,
2746 bfd_reloc_code_real_type other)
252b5132 2747{
47926f60 2748 if (other != NO_RELOC)
3956db08 2749 {
91d6fa6a 2750 reloc_howto_type *rel;
3956db08
JB		 2751
2752 if (size == 8)
2753 switch (other)
2754 {
64e74474
AM		 2755 case BFD_RELOC_X86_64_GOT32:
2756 return BFD_RELOC_X86_64_GOT64;
2757 break;
553d1284
L		 2758 case BFD_RELOC_X86_64_GOTPLT64:
2759 return BFD_RELOC_X86_64_GOTPLT64;
2760 break;
64e74474
AM		 2761 case BFD_RELOC_X86_64_PLTOFF64:
2762 return BFD_RELOC_X86_64_PLTOFF64;
2763 break;
2764 case BFD_RELOC_X86_64_GOTPC32:
2765 other = BFD_RELOC_X86_64_GOTPC64;
2766 break;
2767 case BFD_RELOC_X86_64_GOTPCREL:
2768 other = BFD_RELOC_X86_64_GOTPCREL64;
2769 break;
2770 case BFD_RELOC_X86_64_TPOFF32:
2771 other = BFD_RELOC_X86_64_TPOFF64;
2772 break;
2773 case BFD_RELOC_X86_64_DTPOFF32:
2774 other = BFD_RELOC_X86_64_DTPOFF64;
2775 break;
2776 default:
2777 break;
3956db08 2778 }
e05278af 2779
8ce3d284 2780#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 2781 if (other == BFD_RELOC_SIZE32)
2782 {
2783 if (size == 8)
1ab668bf 2784 other = BFD_RELOC_SIZE64;
8fd4256d 2785 if (pcrel)
1ab668bf
AM		 2786 {
2787 as_bad (_("there are no pc-relative size relocations"));
2788 return NO_RELOC;
2789 }
8fd4256d 2790 }
8ce3d284 2791#endif
8fd4256d 2792
e05278af 2793 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 2794 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 2795 sign = -1;
2796
91d6fa6a
NC		 2797 rel = bfd_reloc_type_lookup (stdoutput, other);
2798 if (!rel)
3956db08 2799 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 2800 else if (size != bfd_get_reloc_size (rel))
3956db08 2801 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 2802 bfd_get_reloc_size (rel),
3956db08 2803 size);
91d6fa6a 2804 else if (pcrel && !rel->pc_relative)
3956db08 2805 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 2806 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 2807 && !sign)
91d6fa6a 2808 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 2809 && sign > 0))
3956db08
JB		 2810 as_bad (_("relocated field and relocation type differ in signedness"));
2811 else
2812 return other;
2813 return NO_RELOC;
2814 }
252b5132
RH		 2815
2816 if (pcrel)
2817 {
3e73aa7c 2818 if (!sign)
3956db08 2819 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2820 switch (size)
2821 {
2822 case 1: return BFD_RELOC_8_PCREL;
2823 case 2: return BFD_RELOC_16_PCREL;
d258b828 2824 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2825 case 8: return BFD_RELOC_64_PCREL;
252b5132 2826 }
3956db08 2827 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2828 }
2829 else
2830 {
3956db08 2831 if (sign > 0)
e5cb08ac 2832 switch (size)
3e73aa7c
JH		 2833 {
2834 case 4: return BFD_RELOC_X86_64_32S;
2835 }
2836 else
2837 switch (size)
2838 {
2839 case 1: return BFD_RELOC_8;
2840 case 2: return BFD_RELOC_16;
2841 case 4: return BFD_RELOC_32;
2842 case 8: return BFD_RELOC_64;
2843 }
3956db08
JB		 2844 as_bad (_("cannot do %s %u byte relocation"),
2845 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2846 }
2847
0cc9e1d3 2848 return NO_RELOC;
252b5132
RH		 2849}
2850
47926f60
KH		 2851/* Here we decide which fixups can be adjusted to make them relative to
2852 the beginning of the section instead of the symbol. Basically we need
2853 to make sure that the dynamic relocations are done correctly, so in
2854 some cases we force the original symbol to be used. */
2855
252b5132 2856int
e3bb37b5 2857tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2858{
6d249963 2859#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2860 if (!IS_ELF)
31312f95
AM		 2861 return 1;
2862
a161fe53
AM		 2863 /* Don't adjust pc-relative references to merge sections in 64-bit
2864 mode. */
2865 if (use_rela_relocations
2866 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2867 && fixP->fx_pcrel)
252b5132 2868 return 0;
31312f95 2869
8d01d9a9
AJ		 2870 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2871 and changed later by validate_fix. */
2872 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2873 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2874 return 0;
2875
8fd4256d
L		 2876 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2877 for size relocations. */
2878 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2879 || fixP->fx_r_type == BFD_RELOC_SIZE64
2880 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 2881 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2882 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2883 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2884 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2885 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2886 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2887 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2888 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2889 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2890 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2891 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2892 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2893 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2894 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2895 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2896 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2897 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2898 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2899 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2900 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2901 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2902 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2903 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2904 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2905 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2906 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2907 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2908 return 0;
31312f95 2909#endif
252b5132
RH		 2910 return 1;
2911}
252b5132 2912
b4cac588 2913static int
e3bb37b5 2914intel_float_operand (const char *mnemonic)
252b5132 2915{
9306ca4a
JB		 2916 /* Note that the value returned is meaningful only for opcodes with (memory)
2917 operands, hence the code here is free to improperly handle opcodes that
2918 have no operands (for better performance and smaller code). */
2919
2920 if (mnemonic[0] != 'f')
2921 return 0; /* non-math */
2922
2923 switch (mnemonic[1])
2924 {
2925 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2926 the fs segment override prefix not currently handled because no
2927 call path can make opcodes without operands get here */
2928 case 'i':
2929 return 2 /* integer op */;
2930 case 'l':
2931 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2932 return 3; /* fldcw/fldenv */
2933 break;
2934 case 'n':
2935 if (mnemonic[2] != 'o' /* fnop */)
2936 return 3; /* non-waiting control op */
2937 break;
2938 case 'r':
2939 if (mnemonic[2] == 's')
2940 return 3; /* frstor/frstpm */
2941 break;
2942 case 's':
2943 if (mnemonic[2] == 'a')
2944 return 3; /* fsave */
2945 if (mnemonic[2] == 't')
2946 {
2947 switch (mnemonic[3])
2948 {
2949 case 'c': /* fstcw */
2950 case 'd': /* fstdw */
2951 case 'e': /* fstenv */
2952 case 's': /* fsts[gw] */
2953 return 3;
2954 }
2955 }
2956 break;
2957 case 'x':
2958 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2959 return 0; /* fxsave/fxrstor are not really math ops */
2960 break;
2961 }
252b5132 2962
9306ca4a 2963 return 1;
252b5132
RH		 2964}
2965
c0f3af97
L		 2966/* Build the VEX prefix. */
2967
2968static void
d3ce72d0 2969build_vex_prefix (const insn_template *t)
c0f3af97
L		 2970{
2971 unsigned int register_specifier;
2972 unsigned int implied_prefix;
2973 unsigned int vector_length;
2974
2975 /* Check register specifier. */
2976 if (i.vex.register_specifier)
43234a1e
L		 2977 {
2978 register_specifier =
2979 ~register_number (i.vex.register_specifier) & 0xf;
2980 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
2981 }
c0f3af97
L		 2982 else
2983 register_specifier = 0xf;
2984
fa99fab2
L		 2985 /* Use 2-byte VEX prefix by swappping destination and source
2986 operand. */
2987 if (!i.swap_operand
2988 && i.operands == i.reg_operands
7f399153 2989 && i.tm.opcode_modifier.vexopcode == VEX0F
fa99fab2
L		 2990 && i.tm.opcode_modifier.s
2991 && i.rex == REX_B)
2992 {
2993 unsigned int xchg = i.operands - 1;
2994 union i386_op temp_op;
2995 i386_operand_type temp_type;
2996
2997 temp_type = i.types[xchg];
2998 i.types[xchg] = i.types[0];
2999 i.types[0] = temp_type;
3000 temp_op = i.op[xchg];
3001 i.op[xchg] = i.op[0];
3002 i.op[0] = temp_op;
3003
9c2799c2 3004 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3005
3006 i.rex = REX_R;
3007 xchg = i.rm.regmem;
3008 i.rm.regmem = i.rm.reg;
3009 i.rm.reg = xchg;
3010
3011 /* Use the next insn. */
3012 i.tm = t[1];
3013 }
3014
539f890d
L		 3015 if (i.tm.opcode_modifier.vex == VEXScalar)
3016 vector_length = avxscalar;
3017 else
3018 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3019
3020 switch ((i.tm.base_opcode >> 8) & 0xff)
3021 {
3022 case 0:
3023 implied_prefix = 0;
3024 break;
3025 case DATA_PREFIX_OPCODE:
3026 implied_prefix = 1;
3027 break;
3028 case REPE_PREFIX_OPCODE:
3029 implied_prefix = 2;
3030 break;
3031 case REPNE_PREFIX_OPCODE:
3032 implied_prefix = 3;
3033 break;
3034 default:
3035 abort ();
3036 }
3037
3038 /* Use 2-byte VEX prefix if possible. */
7f399153 3039 if (i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3040 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3041 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3042 {
3043 /* 2-byte VEX prefix. */
3044 unsigned int r;
3045
3046 i.vex.length = 2;
3047 i.vex.bytes[0] = 0xc5;
3048
3049 /* Check the REX.R bit. */
3050 r = (i.rex & REX_R) ? 0 : 1;
3051 i.vex.bytes[1] = (r << 7
3052 | register_specifier << 3
3053 | vector_length << 2
3054 | implied_prefix);
3055 }
3056 else
3057 {
3058 /* 3-byte VEX prefix. */
3059 unsigned int m, w;
3060
f88c9eb0 3061 i.vex.length = 3;
f88c9eb0 3062
7f399153 3063 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3064 {
7f399153
L		 3065 case VEX0F:
3066 m = 0x1;
80de6e00 3067 i.vex.bytes[0] = 0xc4;
7f399153
L		 3068 break;
3069 case VEX0F38:
3070 m = 0x2;
80de6e00 3071 i.vex.bytes[0] = 0xc4;
7f399153
L		 3072 break;
3073 case VEX0F3A:
3074 m = 0x3;
80de6e00 3075 i.vex.bytes[0] = 0xc4;
7f399153
L		 3076 break;
3077 case XOP08:
5dd85c99
SP		 3078 m = 0x8;
3079 i.vex.bytes[0] = 0x8f;
7f399153
L		 3080 break;
3081 case XOP09:
f88c9eb0
SP		 3082 m = 0x9;
3083 i.vex.bytes[0] = 0x8f;
7f399153
L		 3084 break;
3085 case XOP0A:
f88c9eb0
SP		 3086 m = 0xa;
3087 i.vex.bytes[0] = 0x8f;
7f399153
L		 3088 break;
3089 default:
3090 abort ();
f88c9eb0 3091 }
c0f3af97 3092
c0f3af97
L		 3093 /* The high 3 bits of the second VEX byte are 1's compliment
3094 of RXB bits from REX. */
3095 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3096
3097 /* Check the REX.W bit. */
3098 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3099 if (i.tm.opcode_modifier.vexw == VEXW1)
3100 w = 1;
c0f3af97
L		 3101
3102 i.vex.bytes[2] = (w << 7
3103 | register_specifier << 3
3104 | vector_length << 2
3105 | implied_prefix);
3106 }
3107}
3108
43234a1e
L		 3109/* Build the EVEX prefix. */
3110
3111static void
3112build_evex_prefix (void)
3113{
3114 unsigned int register_specifier;
3115 unsigned int implied_prefix;
3116 unsigned int m, w;
3117 rex_byte vrex_used = 0;
3118
3119 /* Check register specifier. */
3120 if (i.vex.register_specifier)
3121 {
3122 gas_assert ((i.vrex & REX_X) == 0);
3123
3124 register_specifier = i.vex.register_specifier->reg_num;
3125 if ((i.vex.register_specifier->reg_flags & RegRex))
3126 register_specifier += 8;
3127 /* The upper 16 registers are encoded in the fourth byte of the
3128 EVEX prefix. */
3129 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3130 i.vex.bytes[3] = 0x8;
3131 register_specifier = ~register_specifier & 0xf;
3132 }
3133 else
3134 {
3135 register_specifier = 0xf;
3136
3137 /* Encode upper 16 vector index register in the fourth byte of
3138 the EVEX prefix. */
3139 if (!(i.vrex & REX_X))
3140 i.vex.bytes[3] = 0x8;
3141 else
3142 vrex_used |= REX_X;
3143 }
3144
3145 switch ((i.tm.base_opcode >> 8) & 0xff)
3146 {
3147 case 0:
3148 implied_prefix = 0;
3149 break;
3150 case DATA_PREFIX_OPCODE:
3151 implied_prefix = 1;
3152 break;
3153 case REPE_PREFIX_OPCODE:
3154 implied_prefix = 2;
3155 break;
3156 case REPNE_PREFIX_OPCODE:
3157 implied_prefix = 3;
3158 break;
3159 default:
3160 abort ();
3161 }
3162
3163 /* 4 byte EVEX prefix. */
3164 i.vex.length = 4;
3165 i.vex.bytes[0] = 0x62;
3166
3167 /* mmmm bits. */
3168 switch (i.tm.opcode_modifier.vexopcode)
3169 {
3170 case VEX0F:
3171 m = 1;
3172 break;
3173 case VEX0F38:
3174 m = 2;
3175 break;
3176 case VEX0F3A:
3177 m = 3;
3178 break;
3179 default:
3180 abort ();
3181 break;
3182 }
3183
3184 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3185 bits from REX. */
3186 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3187
3188 /* The fifth bit of the second EVEX byte is 1's compliment of the
3189 REX_R bit in VREX. */
3190 if (!(i.vrex & REX_R))
3191 i.vex.bytes[1] |= 0x10;
3192 else
3193 vrex_used |= REX_R;
3194
3195 if ((i.reg_operands + i.imm_operands) == i.operands)
3196 {
3197 /* When all operands are registers, the REX_X bit in REX is not
3198 used. We reuse it to encode the upper 16 registers, which is
3199 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3200 as 1's compliment. */
3201 if ((i.vrex & REX_B))
3202 {
3203 vrex_used |= REX_B;
3204 i.vex.bytes[1] &= ~0x40;
3205 }
3206 }
3207
3208 /* EVEX instructions shouldn't need the REX prefix. */
3209 i.vrex &= ~vrex_used;
3210 gas_assert (i.vrex == 0);
3211
3212 /* Check the REX.W bit. */
3213 w = (i.rex & REX_W) ? 1 : 0;
3214 if (i.tm.opcode_modifier.vexw)
3215 {
3216 if (i.tm.opcode_modifier.vexw == VEXW1)
3217 w = 1;
3218 }
3219 /* If w is not set it means we are dealing with WIG instruction. */
3220 else if (!w)
3221 {
3222 if (evexwig == evexw1)
3223 w = 1;
3224 }
3225
3226 /* Encode the U bit. */
3227 implied_prefix |= 0x4;
3228
3229 /* The third byte of the EVEX prefix. */
3230 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3231
3232 /* The fourth byte of the EVEX prefix. */
3233 /* The zeroing-masking bit. */
3234 if (i.mask && i.mask->zeroing)
3235 i.vex.bytes[3] |= 0x80;
3236
3237 /* Don't always set the broadcast bit if there is no RC. */
3238 if (!i.rounding)
3239 {
3240 /* Encode the vector length. */
3241 unsigned int vec_length;
3242
3243 switch (i.tm.opcode_modifier.evex)
3244 {
3245 case EVEXLIG: /* LL' is ignored */
3246 vec_length = evexlig << 5;
3247 break;
3248 case EVEX128:
3249 vec_length = 0 << 5;
3250 break;
3251 case EVEX256:
3252 vec_length = 1 << 5;
3253 break;
3254 case EVEX512:
3255 vec_length = 2 << 5;
3256 break;
3257 default:
3258 abort ();
3259 break;
3260 }
3261 i.vex.bytes[3] |= vec_length;
3262 /* Encode the broadcast bit. */
3263 if (i.broadcast)
3264 i.vex.bytes[3] |= 0x10;
3265 }
3266 else
3267 {
3268 if (i.rounding->type != saeonly)
3269 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3270 else
d3d3c6db 3271 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3272 }
3273
3274 if (i.mask && i.mask->mask)
3275 i.vex.bytes[3] |= i.mask->mask->reg_num;
3276}
3277
65da13b5
L		 3278static void
3279process_immext (void)
3280{
3281 expressionS *exp;
3282
4c692bc7
JB		 3283 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3284 && i.operands > 0)
65da13b5 3285 {
4c692bc7
JB		 3286 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3287 with an opcode suffix which is coded in the same place as an
3288 8-bit immediate field would be.
3289 Here we check those operands and remove them afterwards. */
65da13b5
L		 3290 unsigned int x;
3291
3292 for (x = 0; x < i.operands; x++)
4c692bc7 3293 if (register_number (i.op[x].regs) != x)
65da13b5 3294 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3295 register_prefix, i.op[x].regs->reg_name, x + 1,
3296 i.tm.name);
3297
3298 i.operands = 0;
65da13b5
L		 3299 }
3300
c0f3af97 3301 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3302 which is coded in the same place as an 8-bit immediate field
3303 would be. Here we fake an 8-bit immediate operand from the
3304 opcode suffix stored in tm.extension_opcode.
3305
c1e679ec 3306 AVX instructions also use this encoding, for some of
c0f3af97 3307 3 argument instructions. */
65da13b5 3308
43234a1e 3309 gas_assert (i.imm_operands <= 1
7ab9ffdd 3310 && (i.operands <= 2
43234a1e
L		 3311 || ((i.tm.opcode_modifier.vex
3312 || i.tm.opcode_modifier.evex)
7ab9ffdd 3313 && i.operands <= 4)));
65da13b5
L		 3314
3315 exp = &im_expressions[i.imm_operands++];
3316 i.op[i.operands].imms = exp;
3317 i.types[i.operands] = imm8;
3318 i.operands++;
3319 exp->X_op = O_constant;
3320 exp->X_add_number = i.tm.extension_opcode;
3321 i.tm.extension_opcode = None;
3322}
3323
42164a71
L		 3324
3325static int
3326check_hle (void)
3327{
3328 switch (i.tm.opcode_modifier.hleprefixok)
3329 {
3330 default:
3331 abort ();
82c2def5 3332 case HLEPrefixNone:
165de32a
L		 3333 as_bad (_("invalid instruction `%s' after `%s'"),
3334 i.tm.name, i.hle_prefix);
42164a71 3335 return 0;
82c2def5 3336 case HLEPrefixLock:
42164a71
L		 3337 if (i.prefix[LOCK_PREFIX])
3338 return 1;
165de32a 3339 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3340 return 0;
82c2def5 3341 case HLEPrefixAny:
42164a71 3342 return 1;
82c2def5 3343 case HLEPrefixRelease:
42164a71
L		 3344 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3345 {
3346 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3347 i.tm.name);
3348 return 0;
3349 }
3350 if (i.mem_operands == 0
3351 || !operand_type_check (i.types[i.operands - 1], anymem))
3352 {
3353 as_bad (_("memory destination needed for instruction `%s'"
3354 " after `xrelease'"), i.tm.name);
3355 return 0;
3356 }
3357 return 1;
3358 }
3359}
3360
252b5132
RH		 3361/* This is the guts of the machine-dependent assembler. LINE points to a
3362 machine dependent instruction. This function is supposed to emit
3363 the frags/bytes it assembles to. */
3364
3365void
65da13b5 3366md_assemble (char *line)
252b5132 3367{
40fb9820 3368 unsigned int j;
252b5132 3369 char mnemonic[MAX_MNEM_SIZE];
d3ce72d0 3370 const insn_template *t;
252b5132 3371
47926f60 3372 /* Initialize globals. */
252b5132
RH		 3373 memset (&i, '\0', sizeof (i));
3374 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3375 i.reloc[j] = NO_RELOC;
252b5132
RH		 3376 memset (disp_expressions, '\0', sizeof (disp_expressions));
3377 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3378 save_stack_p = save_stack;
252b5132
RH		 3379
3380 /* First parse an instruction mnemonic & call i386_operand for the operands.
3381 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3382 start of a (possibly prefixed) mnemonic. */
252b5132 3383
29b0f896
AM		 3384 line = parse_insn (line, mnemonic);
3385 if (line == NULL)
3386 return;
252b5132 3387
29b0f896 3388 line = parse_operands (line, mnemonic);
ee86248c 3389 this_operand = -1;
29b0f896
AM		 3390 if (line == NULL)
3391 return;
252b5132 3392
29b0f896
AM		 3393 /* Now we've parsed the mnemonic into a set of templates, and have the
3394 operands at hand. */
3395
3396 /* All intel opcodes have reversed operands except for "bound" and
3397 "enter". We also don't reverse intersegment "jmp" and "call"
3398 instructions with 2 immediate operands so that the immediate segment
050dfa73 3399 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3400 if (intel_syntax
3401 && i.operands > 1
29b0f896 3402 && (strcmp (mnemonic, "bound") != 0)
30123838 3403 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3404 && !(operand_type_check (i.types[0], imm)
3405 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3406 swap_operands ();
3407
ec56d5c0
JB		 3408 /* The order of the immediates should be reversed
3409 for 2 immediates extrq and insertq instructions */
3410 if (i.imm_operands == 2
3411 && (strcmp (mnemonic, "extrq") == 0
3412 || strcmp (mnemonic, "insertq") == 0))
3413 swap_2_operands (0, 1);
3414
29b0f896
AM		 3415 if (i.imm_operands)
3416 optimize_imm ();
3417
b300c311
L		 3418 /* Don't optimize displacement for movabs since it only takes 64bit
3419 displacement. */
3420 if (i.disp_operands
a501d77e 3421 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3422 && (flag_code != CODE_64BIT
3423 || strcmp (mnemonic, "movabs") != 0))
3424 optimize_disp ();
29b0f896
AM		 3425
3426 /* Next, we find a template that matches the given insn,
3427 making sure the overlap of the given operands types is consistent
3428 with the template operand types. */
252b5132 3429
fa99fab2 3430 if (!(t = match_template ()))
29b0f896 3431 return;
252b5132 3432
7bab8ab5 3433 if (sse_check != check_none
81f8a913 3434 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3435 && (i.tm.cpu_flags.bitfield.cpusse
3436 || i.tm.cpu_flags.bitfield.cpusse2
3437 || i.tm.cpu_flags.bitfield.cpusse3
3438 || i.tm.cpu_flags.bitfield.cpussse3
3439 || i.tm.cpu_flags.bitfield.cpusse4_1
3440 || i.tm.cpu_flags.bitfield.cpusse4_2))
3441 {
7bab8ab5 3442 (sse_check == check_warning
daf50ae7
L		 3443 ? as_warn
3444 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3445 }
3446
321fd21e
L		 3447 /* Zap movzx and movsx suffix. The suffix has been set from
3448 "word ptr" or "byte ptr" on the source operand in Intel syntax
3449 or extracted from mnemonic in AT&T syntax. But we'll use
3450 the destination register to choose the suffix for encoding. */
3451 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3452 {
321fd21e
L		 3453 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3454 there is no suffix, the default will be byte extension. */
3455 if (i.reg_operands != 2
3456 && !i.suffix
7ab9ffdd 3457 && intel_syntax)
321fd21e
L		 3458 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3459
3460 i.suffix = 0;
cd61ebfe 3461 }
24eab124 3462
40fb9820 3463 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3464 if (!add_prefix (FWAIT_OPCODE))
3465 return;
252b5132 3466
d5de92cf
L		 3467 /* Check if REP prefix is OK. */
3468 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3469 {
3470 as_bad (_("invalid instruction `%s' after `%s'"),
3471 i.tm.name, i.rep_prefix);
3472 return;
3473 }
3474
c1ba0266
L		 3475 /* Check for lock without a lockable instruction. Destination operand
3476 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3477 if (i.prefix[LOCK_PREFIX]
3478 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3479 || i.mem_operands == 0
3480 || (i.tm.base_opcode != 0x86
3481 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3482 {
3483 as_bad (_("expecting lockable instruction after `lock'"));
3484 return;
3485 }
3486
42164a71 3487 /* Check if HLE prefix is OK. */
165de32a 3488 if (i.hle_prefix && !check_hle ())
42164a71
L		 3489 return;
3490
7e8b059b
L		 3491 /* Check BND prefix. */
3492 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3493 as_bad (_("expecting valid branch instruction after `bnd'"));
3494
3495 if (i.tm.cpu_flags.bitfield.cpumpx
3496 && flag_code == CODE_64BIT
3497 && i.prefix[ADDR_PREFIX])
3498 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3499
3500 /* Insert BND prefix. */
3501 if (add_bnd_prefix
3502 && i.tm.opcode_modifier.bndprefixok
3503 && !i.prefix[BND_PREFIX])
3504 add_prefix (BND_PREFIX_OPCODE);
3505
29b0f896 3506 /* Check string instruction segment overrides. */
40fb9820 3507 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3508 {
3509 if (!check_string ())
5dd0794d 3510 return;
fc0763e6 3511 i.disp_operands = 0;
29b0f896 3512 }
5dd0794d 3513
29b0f896
AM		 3514 if (!process_suffix ())
3515 return;
e413e4e9 3516
bc0844ae
L		 3517 /* Update operand types. */
3518 for (j = 0; j < i.operands; j++)
3519 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3520
29b0f896
AM		 3521 /* Make still unresolved immediate matches conform to size of immediate
3522 given in i.suffix. */
3523 if (!finalize_imm ())
3524 return;
252b5132 3525
40fb9820 3526 if (i.types[0].bitfield.imm1)
29b0f896 3527 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3528
9afe6eb8
L		 3529 /* We only need to check those implicit registers for instructions
3530 with 3 operands or less. */
3531 if (i.operands <= 3)
3532 for (j = 0; j < i.operands; j++)
3533 if (i.types[j].bitfield.inoutportreg
3534 || i.types[j].bitfield.shiftcount
3535 || i.types[j].bitfield.acc
3536 || i.types[j].bitfield.floatacc)
3537 i.reg_operands--;
40fb9820 3538
c0f3af97
L		 3539 /* ImmExt should be processed after SSE2AVX. */
3540 if (!i.tm.opcode_modifier.sse2avx
3541 && i.tm.opcode_modifier.immext)
65da13b5 3542 process_immext ();
252b5132 3543
29b0f896
AM		 3544 /* For insns with operands there are more diddles to do to the opcode. */
3545 if (i.operands)
3546 {
3547 if (!process_operands ())
3548 return;
3549 }
40fb9820 3550 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3551 {
3552 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3553 as_warn (_("translating to `%sp'"), i.tm.name);
3554 }
252b5132 3555
9e5e5283
L		 3556 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3557 {
3558 if (flag_code == CODE_16BIT)
3559 {
3560 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3561 i.tm.name);
3562 return;
3563 }
c0f3af97 3564
9e5e5283
L		 3565 if (i.tm.opcode_modifier.vex)
3566 build_vex_prefix (t);
3567 else
3568 build_evex_prefix ();
3569 }
43234a1e 3570
5dd85c99
SP		 3571 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3572 instructions may define INT_OPCODE as well, so avoid this corner
3573 case for those instructions that use MODRM. */
3574 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3575 && !i.tm.opcode_modifier.modrm
3576 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3577 {
3578 i.tm.base_opcode = INT3_OPCODE;
3579 i.imm_operands = 0;
3580 }
252b5132 3581
40fb9820
L		 3582 if ((i.tm.opcode_modifier.jump
3583 || i.tm.opcode_modifier.jumpbyte
3584 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3585 && i.op[0].disps->X_op == O_constant)
3586 {
3587 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3588 the absolute address given by the constant. Since ix86 jumps and
3589 calls are pc relative, we need to generate a reloc. */
3590 i.op[0].disps->X_add_symbol = &abs_symbol;
3591 i.op[0].disps->X_op = O_symbol;
3592 }
252b5132 3593
40fb9820 3594 if (i.tm.opcode_modifier.rex64)
161a04f6 3595 i.rex |= REX_W;
252b5132 3596
29b0f896
AM		 3597 /* For 8 bit registers we need an empty rex prefix. Also if the
3598 instruction already has a prefix, we need to convert old
3599 registers to new ones. */
773f551c 3600
40fb9820 3601 if ((i.types[0].bitfield.reg8
29b0f896 3602 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 3603 || (i.types[1].bitfield.reg8
29b0f896 3604 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 3605 || ((i.types[0].bitfield.reg8
3606 || i.types[1].bitfield.reg8)
29b0f896
AM		 3607 && i.rex != 0))
3608 {
3609 int x;
726c5dcd 3610
29b0f896
AM		 3611 i.rex |= REX_OPCODE;
3612 for (x = 0; x < 2; x++)
3613 {
3614 /* Look for 8 bit operand that uses old registers. */
40fb9820 3615 if (i.types[x].bitfield.reg8
29b0f896 3616 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3617 {
29b0f896
AM		 3618 /* In case it is "hi" register, give up. */
3619 if (i.op[x].regs->reg_num > 3)
a540244d 3620 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3621 "instruction requiring REX prefix."),
a540244d 3622 register_prefix, i.op[x].regs->reg_name);
773f551c 3623
29b0f896
AM		 3624 /* Otherwise it is equivalent to the extended register.
3625 Since the encoding doesn't change this is merely
3626 cosmetic cleanup for debug output. */
3627
3628 i.op[x].regs = i.op[x].regs + 8;
773f551c 3629 }
29b0f896
AM		 3630 }
3631 }
773f551c 3632
7ab9ffdd 3633 if (i.rex != 0)
29b0f896
AM		 3634 add_prefix (REX_OPCODE | i.rex);
3635
3636 /* We are ready to output the insn. */
3637 output_insn ();
3638}
3639
3640static char *
e3bb37b5 3641parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3642{
3643 char *l = line;
3644 char *token_start = l;
3645 char *mnem_p;
5c6af06e 3646 int supported;
d3ce72d0 3647 const insn_template *t;
b6169b20 3648 char *dot_p = NULL;
29b0f896 3649
29b0f896
AM		 3650 while (1)
3651 {
3652 mnem_p = mnemonic;
3653 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3654 {
b6169b20
L		 3655 if (*mnem_p == '.')
3656 dot_p = mnem_p;
29b0f896
AM		 3657 mnem_p++;
3658 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3659 {
29b0f896
AM		 3660 as_bad (_("no such instruction: `%s'"), token_start);
3661 return NULL;
3662 }
3663 l++;
3664 }
3665 if (!is_space_char (*l)
3666 && *l != END_OF_INSN
e44823cf
JB		 3667 && (intel_syntax
3668 || (*l != PREFIX_SEPARATOR
3669 && *l != ',')))
29b0f896
AM		 3670 {
3671 as_bad (_("invalid character %s in mnemonic"),
3672 output_invalid (*l));
3673 return NULL;
3674 }
3675 if (token_start == l)
3676 {
e44823cf 3677 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3678 as_bad (_("expecting prefix; got nothing"));
3679 else
3680 as_bad (_("expecting mnemonic; got nothing"));
3681 return NULL;
3682 }
45288df1 3683
29b0f896 3684 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3685 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3686
29b0f896
AM		 3687 if (*l != END_OF_INSN
3688 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3689 && current_templates
40fb9820 3690 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3691 {
c6fb90c8 3692 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3693 {
3694 as_bad ((flag_code != CODE_64BIT
3695 ? _("`%s' is only supported in 64-bit mode")
3696 : _("`%s' is not supported in 64-bit mode")),
3697 current_templates->start->name);
3698 return NULL;
3699 }
29b0f896
AM		 3700 /* If we are in 16-bit mode, do not allow addr16 or data16.
3701 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3702 if ((current_templates->start->opcode_modifier.size16
3703 || current_templates->start->opcode_modifier.size32)
29b0f896 3704 && flag_code != CODE_64BIT
40fb9820 3705 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3706 ^ (flag_code == CODE_16BIT)))
3707 {
3708 as_bad (_("redundant %s prefix"),
3709 current_templates->start->name);
3710 return NULL;
45288df1 3711 }
29b0f896
AM		 3712 /* Add prefix, checking for repeated prefixes. */
3713 switch (add_prefix (current_templates->start->base_opcode))
3714 {
c32fa91d 3715 case PREFIX_EXIST:
29b0f896 3716 return NULL;
c32fa91d 3717 case PREFIX_REP:
42164a71 3718 if (current_templates->start->cpu_flags.bitfield.cpuhle)
165de32a 3719 i.hle_prefix = current_templates->start->name;
7e8b059b
L		 3720 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3721 i.bnd_prefix = current_templates->start->name;
42164a71 3722 else
d5de92cf 3723 i.rep_prefix = current_templates->start->name;
29b0f896 3724 break;
c32fa91d
L		 3725 default:
3726 break;
29b0f896
AM		 3727 }
3728 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3729 token_start = ++l;
3730 }
3731 else
3732 break;
3733 }
45288df1 3734
30a55f88 3735 if (!current_templates)
b6169b20 3736 {
f8a5c266
L		 3737 /* Check if we should swap operand or force 32bit displacement in
3738 encoding. */
30a55f88
L		 3739 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3740 i.swap_operand = 1;
8d63c93e 3741 else if (mnem_p - 3 == dot_p
a501d77e
L		 3742 && dot_p[1] == 'd'
3743 && dot_p[2] == '8')
3744 i.disp_encoding = disp_encoding_8bit;
8d63c93e 3745 else if (mnem_p - 4 == dot_p
f8a5c266
L		 3746 && dot_p[1] == 'd'
3747 && dot_p[2] == '3'
3748 && dot_p[3] == '2')
a501d77e 3749 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 3750 else
3751 goto check_suffix;
3752 mnem_p = dot_p;
3753 *dot_p = '\0';
d3ce72d0 3754 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 3755 }
3756
29b0f896
AM		 3757 if (!current_templates)
3758 {
b6169b20 3759check_suffix:
29b0f896
AM		 3760 /* See if we can get a match by trimming off a suffix. */
3761 switch (mnem_p[-1])
3762 {
3763 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3764 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3765 i.suffix = SHORT_MNEM_SUFFIX;
3766 else
29b0f896
AM		 3767 case BYTE_MNEM_SUFFIX:
3768 case QWORD_MNEM_SUFFIX:
3769 i.suffix = mnem_p[-1];
3770 mnem_p[-1] = '\0';
d3ce72d0
NC		 3771 current_templates = (const templates *) hash_find (op_hash,
3772 mnemonic);
29b0f896
AM		 3773 break;
3774 case SHORT_MNEM_SUFFIX:
3775 case LONG_MNEM_SUFFIX:
3776 if (!intel_syntax)
3777 {
3778 i.suffix = mnem_p[-1];
3779 mnem_p[-1] = '\0';
d3ce72d0
NC		 3780 current_templates = (const templates *) hash_find (op_hash,
3781 mnemonic);
29b0f896
AM		 3782 }
3783 break;
252b5132 3784
29b0f896
AM		 3785 /* Intel Syntax. */
3786 case 'd':
3787 if (intel_syntax)
3788 {
9306ca4a 3789 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3790 i.suffix = SHORT_MNEM_SUFFIX;
3791 else
3792 i.suffix = LONG_MNEM_SUFFIX;
3793 mnem_p[-1] = '\0';
d3ce72d0
NC		 3794 current_templates = (const templates *) hash_find (op_hash,
3795 mnemonic);
29b0f896
AM		 3796 }
3797 break;
3798 }
3799 if (!current_templates)
3800 {
3801 as_bad (_("no such instruction: `%s'"), token_start);
3802 return NULL;
3803 }
3804 }
252b5132 3805
40fb9820
L		 3806 if (current_templates->start->opcode_modifier.jump
3807 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3808 {
3809 /* Check for a branch hint. We allow ",pt" and ",pn" for
3810 predict taken and predict not taken respectively.
3811 I'm not sure that branch hints actually do anything on loop
3812 and jcxz insns (JumpByte) for current Pentium4 chips. They
3813 may work in the future and it doesn't hurt to accept them
3814 now. */
3815 if (l[0] == ',' && l[1] == 'p')
3816 {
3817 if (l[2] == 't')
3818 {
3819 if (!add_prefix (DS_PREFIX_OPCODE))
3820 return NULL;
3821 l += 3;
3822 }
3823 else if (l[2] == 'n')
3824 {
3825 if (!add_prefix (CS_PREFIX_OPCODE))
3826 return NULL;
3827 l += 3;
3828 }
3829 }
3830 }
3831 /* Any other comma loses. */
3832 if (*l == ',')
3833 {
3834 as_bad (_("invalid character %s in mnemonic"),
3835 output_invalid (*l));
3836 return NULL;
3837 }
252b5132 3838
29b0f896 3839 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3840 supported = 0;
3841 for (t = current_templates->start; t < current_templates->end; ++t)
3842 {
c0f3af97
L		 3843 supported |= cpu_flags_match (t);
3844 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3845 goto skip;
5c6af06e 3846 }
3629bb00 3847
c0f3af97 3848 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3849 {
3850 as_bad (flag_code == CODE_64BIT
3851 ? _("`%s' is not supported in 64-bit mode")
3852 : _("`%s' is only supported in 64-bit mode"),
3853 current_templates->start->name);
3854 return NULL;
3855 }
c0f3af97 3856 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3857 {
3629bb00 3858 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 3859 current_templates->start->name,
41aacd83 3860 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3861 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3862 return NULL;
29b0f896 3863 }
3629bb00
L		 3864
3865skip:
3866 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3867 && (flag_code != CODE_16BIT))
29b0f896
AM		 3868 {
3869 as_warn (_("use .code16 to ensure correct addressing mode"));
3870 }
252b5132 3871
29b0f896
AM		 3872 return l;
3873}
252b5132 3874
29b0f896 3875static char *
e3bb37b5 3876parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3877{
3878 char *token_start;
3138f287 3879
29b0f896
AM		 3880 /* 1 if operand is pending after ','. */
3881 unsigned int expecting_operand = 0;
252b5132 3882
29b0f896
AM		 3883 /* Non-zero if operand parens not balanced. */
3884 unsigned int paren_not_balanced;
3885
3886 while (*l != END_OF_INSN)
3887 {
3888 /* Skip optional white space before operand. */
3889 if (is_space_char (*l))
3890 ++l;
3891 if (!is_operand_char (*l) && *l != END_OF_INSN)
3892 {
3893 as_bad (_("invalid character %s before operand %d"),
3894 output_invalid (*l),
3895 i.operands + 1);
3896 return NULL;
3897 }
3898 token_start = l; /* after white space */
3899 paren_not_balanced = 0;
3900 while (paren_not_balanced || *l != ',')
3901 {
3902 if (*l == END_OF_INSN)
3903 {
3904 if (paren_not_balanced)
3905 {
3906 if (!intel_syntax)
3907 as_bad (_("unbalanced parenthesis in operand %d."),
3908 i.operands + 1);
3909 else
3910 as_bad (_("unbalanced brackets in operand %d."),
3911 i.operands + 1);
3912 return NULL;
3913 }
3914 else
3915 break; /* we are done */
3916 }
3917 else if (!is_operand_char (*l) && !is_space_char (*l))
3918 {
3919 as_bad (_("invalid character %s in operand %d"),
3920 output_invalid (*l),
3921 i.operands + 1);
3922 return NULL;
3923 }
3924 if (!intel_syntax)
3925 {
3926 if (*l == '(')
3927 ++paren_not_balanced;
3928 if (*l == ')')
3929 --paren_not_balanced;
3930 }
3931 else
3932 {
3933 if (*l == '[')
3934 ++paren_not_balanced;
3935 if (*l == ']')
3936 --paren_not_balanced;
3937 }
3938 l++;
3939 }
3940 if (l != token_start)
3941 { /* Yes, we've read in another operand. */
3942 unsigned int operand_ok;
3943 this_operand = i.operands++;
7d5e4556 3944 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3945 if (i.operands > MAX_OPERANDS)
3946 {
3947 as_bad (_("spurious operands; (%d operands/instruction max)"),
3948 MAX_OPERANDS);
3949 return NULL;
3950 }
3951 /* Now parse operand adding info to 'i' as we go along. */
3952 END_STRING_AND_SAVE (l);
3953
3954 if (intel_syntax)
3955 operand_ok =
3956 i386_intel_operand (token_start,
3957 intel_float_operand (mnemonic));
3958 else
a7619375 3959 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3960
3961 RESTORE_END_STRING (l);
3962 if (!operand_ok)
3963 return NULL;
3964 }
3965 else
3966 {
3967 if (expecting_operand)
3968 {
3969 expecting_operand_after_comma:
3970 as_bad (_("expecting operand after ','; got nothing"));
3971 return NULL;
3972 }
3973 if (*l == ',')
3974 {
3975 as_bad (_("expecting operand before ','; got nothing"));
3976 return NULL;
3977 }
3978 }
7f3f1ea2 3979
29b0f896
AM		 3980 /* Now *l must be either ',' or END_OF_INSN. */
3981 if (*l == ',')
3982 {
3983 if (*++l == END_OF_INSN)
3984 {
3985 /* Just skip it, if it's \n complain. */
3986 goto expecting_operand_after_comma;
3987 }
3988 expecting_operand = 1;
3989 }
3990 }
3991 return l;
3992}
7f3f1ea2 3993
050dfa73 3994static void
4d456e3d 3995swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3996{
3997 union i386_op temp_op;
40fb9820 3998 i386_operand_type temp_type;
050dfa73 3999 enum bfd_reloc_code_real temp_reloc;
4eed87de 4000
050dfa73
MM		 4001 temp_type = i.types[xchg2];
4002 i.types[xchg2] = i.types[xchg1];
4003 i.types[xchg1] = temp_type;
4004 temp_op = i.op[xchg2];
4005 i.op[xchg2] = i.op[xchg1];
4006 i.op[xchg1] = temp_op;
4007 temp_reloc = i.reloc[xchg2];
4008 i.reloc[xchg2] = i.reloc[xchg1];
4009 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4010
4011 if (i.mask)
4012 {
4013 if (i.mask->operand == xchg1)
4014 i.mask->operand = xchg2;
4015 else if (i.mask->operand == xchg2)
4016 i.mask->operand = xchg1;
4017 }
4018 if (i.broadcast)
4019 {
4020 if (i.broadcast->operand == xchg1)
4021 i.broadcast->operand = xchg2;
4022 else if (i.broadcast->operand == xchg2)
4023 i.broadcast->operand = xchg1;
4024 }
4025 if (i.rounding)
4026 {
4027 if (i.rounding->operand == xchg1)
4028 i.rounding->operand = xchg2;
4029 else if (i.rounding->operand == xchg2)
4030 i.rounding->operand = xchg1;
4031 }
050dfa73
MM		 4032}
4033
29b0f896 4034static void
e3bb37b5 4035swap_operands (void)
29b0f896 4036{
b7c61d9a 4037 switch (i.operands)
050dfa73 4038 {
c0f3af97 4039 case 5:
b7c61d9a 4040 case 4:
4d456e3d 4041 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 4042 case 3:
4043 case 2:
4d456e3d 4044 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4045 break;
4046 default:
4047 abort ();
29b0f896 4048 }
29b0f896
AM		 4049
4050 if (i.mem_operands == 2)
4051 {
4052 const seg_entry *temp_seg;
4053 temp_seg = i.seg[0];
4054 i.seg[0] = i.seg[1];
4055 i.seg[1] = temp_seg;
4056 }
4057}
252b5132 4058
29b0f896
AM		 4059/* Try to ensure constant immediates are represented in the smallest
4060 opcode possible. */
4061static void
e3bb37b5 4062optimize_imm (void)
29b0f896
AM		 4063{
4064 char guess_suffix = 0;
4065 int op;
252b5132 4066
29b0f896
AM		 4067 if (i.suffix)
4068 guess_suffix = i.suffix;
4069 else if (i.reg_operands)
4070 {
4071 /* Figure out a suffix from the last register operand specified.
4072 We can't do this properly yet, ie. excluding InOutPortReg,
4073 but the following works for instructions with immediates.
4074 In any case, we can't set i.suffix yet. */
4075 for (op = i.operands; --op >= 0;)
40fb9820 4076 if (i.types[op].bitfield.reg8)
7ab9ffdd 4077 {
40fb9820
L		 4078 guess_suffix = BYTE_MNEM_SUFFIX;
4079 break;
4080 }
4081 else if (i.types[op].bitfield.reg16)
252b5132 4082 {
40fb9820
L		 4083 guess_suffix = WORD_MNEM_SUFFIX;
4084 break;
4085 }
4086 else if (i.types[op].bitfield.reg32)
4087 {
4088 guess_suffix = LONG_MNEM_SUFFIX;
4089 break;
4090 }
4091 else if (i.types[op].bitfield.reg64)
4092 {
4093 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4094 break;
252b5132 4095 }
29b0f896
AM		 4096 }
4097 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4098 guess_suffix = WORD_MNEM_SUFFIX;
4099
4100 for (op = i.operands; --op >= 0;)
40fb9820 4101 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4102 {
4103 switch (i.op[op].imms->X_op)
252b5132 4104 {
29b0f896
AM		 4105 case O_constant:
4106 /* If a suffix is given, this operand may be shortened. */
4107 switch (guess_suffix)
252b5132 4108 {
29b0f896 4109 case LONG_MNEM_SUFFIX:
40fb9820
L		 4110 i.types[op].bitfield.imm32 = 1;
4111 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4112 break;
4113 case WORD_MNEM_SUFFIX:
40fb9820
L		 4114 i.types[op].bitfield.imm16 = 1;
4115 i.types[op].bitfield.imm32 = 1;
4116 i.types[op].bitfield.imm32s = 1;
4117 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4118 break;
4119 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4120 i.types[op].bitfield.imm8 = 1;
4121 i.types[op].bitfield.imm8s = 1;
4122 i.types[op].bitfield.imm16 = 1;
4123 i.types[op].bitfield.imm32 = 1;
4124 i.types[op].bitfield.imm32s = 1;
4125 i.types[op].bitfield.imm64 = 1;
29b0f896 4126 break;
252b5132 4127 }
252b5132 4128
29b0f896
AM		 4129 /* If this operand is at most 16 bits, convert it
4130 to a signed 16 bit number before trying to see
4131 whether it will fit in an even smaller size.
4132 This allows a 16-bit operand such as $0xffe0 to
4133 be recognised as within Imm8S range. */
40fb9820 4134 if ((i.types[op].bitfield.imm16)
29b0f896 4135 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4136 {
29b0f896
AM		 4137 i.op[op].imms->X_add_number =
4138 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4139 }
40fb9820 4140 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4141 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4142 == 0))
4143 {
4144 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4145 ^ ((offsetT) 1 << 31))
4146 - ((offsetT) 1 << 31));
4147 }
40fb9820 4148 i.types[op]
c6fb90c8
L		 4149 = operand_type_or (i.types[op],
4150 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4151
29b0f896
AM		 4152 /* We must avoid matching of Imm32 templates when 64bit
4153 only immediate is available. */
4154 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4155 i.types[op].bitfield.imm32 = 0;
29b0f896 4156 break;
252b5132 4157
29b0f896
AM		 4158 case O_absent:
4159 case O_register:
4160 abort ();
4161
4162 /* Symbols and expressions. */
4163 default:
9cd96992
JB		 4164 /* Convert symbolic operand to proper sizes for matching, but don't
4165 prevent matching a set of insns that only supports sizes other
4166 than those matching the insn suffix. */
4167 {
40fb9820 4168 i386_operand_type mask, allowed;
d3ce72d0 4169 const insn_template *t;
9cd96992 4170
0dfbf9d7
L		 4171 operand_type_set (&mask, 0);
4172 operand_type_set (&allowed, 0);
40fb9820 4173
4eed87de
AM		 4174 for (t = current_templates->start;
4175 t < current_templates->end;
4176 ++t)
c6fb90c8
L		 4177 allowed = operand_type_or (allowed,
4178 t->operand_types[op]);
9cd96992
JB		 4179 switch (guess_suffix)
4180 {
4181 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4182 mask.bitfield.imm64 = 1;
4183 mask.bitfield.imm32s = 1;
9cd96992
JB		 4184 break;
4185 case LONG_MNEM_SUFFIX:
40fb9820 4186 mask.bitfield.imm32 = 1;
9cd96992
JB		 4187 break;
4188 case WORD_MNEM_SUFFIX:
40fb9820 4189 mask.bitfield.imm16 = 1;
9cd96992
JB		 4190 break;
4191 case BYTE_MNEM_SUFFIX:
40fb9820 4192 mask.bitfield.imm8 = 1;
9cd96992
JB		 4193 break;
4194 default:
9cd96992
JB		 4195 break;
4196 }
c6fb90c8 4197 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4198 if (!operand_type_all_zero (&allowed))
c6fb90c8 4199 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4200 }
29b0f896 4201 break;
252b5132 4202 }
29b0f896
AM		 4203 }
4204}
47926f60 4205
29b0f896
AM		 4206/* Try to use the smallest displacement type too. */
4207static void
e3bb37b5 4208optimize_disp (void)
29b0f896
AM		 4209{
4210 int op;
3e73aa7c 4211
29b0f896 4212 for (op = i.operands; --op >= 0;)
40fb9820 4213 if (operand_type_check (i.types[op], disp))
252b5132 4214 {
b300c311 4215 if (i.op[op].disps->X_op == O_constant)
252b5132 4216 {
91d6fa6a 4217 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4218
40fb9820 4219 if (i.types[op].bitfield.disp16
91d6fa6a 4220 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4221 {
4222 /* If this operand is at most 16 bits, convert
4223 to a signed 16 bit number and don't use 64bit
4224 displacement. */
91d6fa6a 4225 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4226 i.types[op].bitfield.disp64 = 0;
b300c311 4227 }
40fb9820 4228 if (i.types[op].bitfield.disp32
91d6fa6a 4229 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4230 {
4231 /* If this operand is at most 32 bits, convert
4232 to a signed 32 bit number and don't use 64bit
4233 displacement. */
91d6fa6a
NC		 4234 op_disp &= (((offsetT) 2 << 31) - 1);
4235 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4236 i.types[op].bitfield.disp64 = 0;
b300c311 4237 }
91d6fa6a 4238 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4239 {
40fb9820
L		 4240 i.types[op].bitfield.disp8 = 0;
4241 i.types[op].bitfield.disp16 = 0;
4242 i.types[op].bitfield.disp32 = 0;
4243 i.types[op].bitfield.disp32s = 0;
4244 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4245 i.op[op].disps = 0;
4246 i.disp_operands--;
4247 }
4248 else if (flag_code == CODE_64BIT)
4249 {
91d6fa6a 4250 if (fits_in_signed_long (op_disp))
28a9d8f5 4251 {
40fb9820
L		 4252 i.types[op].bitfield.disp64 = 0;
4253 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4254 }
0e1147d9 4255 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4256 && fits_in_unsigned_long (op_disp))
40fb9820 4257 i.types[op].bitfield.disp32 = 1;
b300c311 4258 }
40fb9820
L		 4259 if ((i.types[op].bitfield.disp32
4260 || i.types[op].bitfield.disp32s
4261 || i.types[op].bitfield.disp16)
91d6fa6a 4262 && fits_in_signed_byte (op_disp))
40fb9820 4263 i.types[op].bitfield.disp8 = 1;
252b5132 4264 }
67a4f2b7
AO		 4265 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4266 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4267 {
4268 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4269 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4270 i.types[op].bitfield.disp8 = 0;
4271 i.types[op].bitfield.disp16 = 0;
4272 i.types[op].bitfield.disp32 = 0;
4273 i.types[op].bitfield.disp32s = 0;
4274 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4275 }
4276 else
b300c311 4277 /* We only support 64bit displacement on constants. */
40fb9820 4278 i.types[op].bitfield.disp64 = 0;
252b5132 4279 }
29b0f896
AM		 4280}
4281
6c30d220
L		 4282/* Check if operands are valid for the instruction. */
4283
4284static int
4285check_VecOperands (const insn_template *t)
4286{
43234a1e
L		 4287 unsigned int op;
4288
6c30d220
L		 4289 /* Without VSIB byte, we can't have a vector register for index. */
4290 if (!t->opcode_modifier.vecsib
4291 && i.index_reg
4292 && (i.index_reg->reg_type.bitfield.regxmm
43234a1e
L		 4293 || i.index_reg->reg_type.bitfield.regymm
4294 || i.index_reg->reg_type.bitfield.regzmm))
6c30d220
L		 4295 {
4296 i.error = unsupported_vector_index_register;
4297 return 1;
4298 }
4299
ad8ecc81
MZ		 4300 /* Check if default mask is allowed. */
4301 if (t->opcode_modifier.nodefmask
4302 && (!i.mask || i.mask->mask->reg_num == 0))
4303 {
4304 i.error = no_default_mask;
4305 return 1;
4306 }
4307
7bab8ab5
JB		 4308 /* For VSIB byte, we need a vector register for index, and all vector
4309 registers must be distinct. */
4310 if (t->opcode_modifier.vecsib)
4311 {
4312 if (!i.index_reg
6c30d220
L		 4313 || !((t->opcode_modifier.vecsib == VecSIB128
4314 && i.index_reg->reg_type.bitfield.regxmm)
4315 || (t->opcode_modifier.vecsib == VecSIB256
43234a1e
L		 4316 && i.index_reg->reg_type.bitfield.regymm)
4317 || (t->opcode_modifier.vecsib == VecSIB512
4318 && i.index_reg->reg_type.bitfield.regzmm)))
7bab8ab5
JB		 4319 {
4320 i.error = invalid_vsib_address;
4321 return 1;
4322 }
4323
43234a1e
L		 4324 gas_assert (i.reg_operands == 2 || i.mask);
4325 if (i.reg_operands == 2 && !i.mask)
4326 {
4327 gas_assert (i.types[0].bitfield.regxmm
7c84a0ca 4328 || i.types[0].bitfield.regymm);
43234a1e 4329 gas_assert (i.types[2].bitfield.regxmm
7c84a0ca 4330 || i.types[2].bitfield.regymm);
43234a1e
L		 4331 if (operand_check == check_none)
4332 return 0;
4333 if (register_number (i.op[0].regs)
4334 != register_number (i.index_reg)
4335 && register_number (i.op[2].regs)
4336 != register_number (i.index_reg)
4337 && register_number (i.op[0].regs)
4338 != register_number (i.op[2].regs))
4339 return 0;
4340 if (operand_check == check_error)
4341 {
4342 i.error = invalid_vector_register_set;
4343 return 1;
4344 }
4345 as_warn (_("mask, index, and destination registers should be distinct"));
4346 }
8444f82a
MZ		 4347 else if (i.reg_operands == 1 && i.mask)
4348 {
4349 if ((i.types[1].bitfield.regymm
4350 || i.types[1].bitfield.regzmm)
4351 && (register_number (i.op[1].regs)
4352 == register_number (i.index_reg)))
4353 {
4354 if (operand_check == check_error)
4355 {
4356 i.error = invalid_vector_register_set;
4357 return 1;
4358 }
4359 if (operand_check != check_none)
4360 as_warn (_("index and destination registers should be distinct"));
4361 }
4362 }
43234a1e 4363 }
7bab8ab5 4364
43234a1e
L		 4365 /* Check if broadcast is supported by the instruction and is applied
4366 to the memory operand. */
4367 if (i.broadcast)
4368 {
4369 int broadcasted_opnd_size;
4370
4371 /* Check if specified broadcast is supported in this instruction,
4372 and it's applied to memory operand of DWORD or QWORD type,
4373 depending on VecESize. */
4374 if (i.broadcast->type != t->opcode_modifier.broadcast
4375 || !i.types[i.broadcast->operand].bitfield.mem
4376 || (t->opcode_modifier.vecesize == 0
4377 && !i.types[i.broadcast->operand].bitfield.dword
4378 && !i.types[i.broadcast->operand].bitfield.unspecified)
4379 || (t->opcode_modifier.vecesize == 1
4380 && !i.types[i.broadcast->operand].bitfield.qword
4381 && !i.types[i.broadcast->operand].bitfield.unspecified))
4382 goto bad_broadcast;
4383
4384 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4385 if (i.broadcast->type == BROADCAST_1TO16)
4386 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4387 else if (i.broadcast->type == BROADCAST_1TO8)
4388 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4389 else if (i.broadcast->type == BROADCAST_1TO4)
4390 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4391 else if (i.broadcast->type == BROADCAST_1TO2)
4392 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4393 else
4394 goto bad_broadcast;
4395
4396 if ((broadcasted_opnd_size == 256
4397 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4398 || (broadcasted_opnd_size == 512
4399 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4400 {
4401 bad_broadcast:
4402 i.error = unsupported_broadcast;
4403 return 1;
4404 }
4405 }
4406 /* If broadcast is supported in this instruction, we need to check if
4407 operand of one-element size isn't specified without broadcast. */
4408 else if (t->opcode_modifier.broadcast && i.mem_operands)
4409 {
4410 /* Find memory operand. */
4411 for (op = 0; op < i.operands; op++)
4412 if (operand_type_check (i.types[op], anymem))
4413 break;
4414 gas_assert (op < i.operands);
4415 /* Check size of the memory operand. */
4416 if ((t->opcode_modifier.vecesize == 0
4417 && i.types[op].bitfield.dword)
4418 || (t->opcode_modifier.vecesize == 1
4419 && i.types[op].bitfield.qword))
4420 {
4421 i.error = broadcast_needed;
4422 return 1;
4423 }
4424 }
4425
4426 /* Check if requested masking is supported. */
4427 if (i.mask
4428 && (!t->opcode_modifier.masking
4429 || (i.mask->zeroing
4430 && t->opcode_modifier.masking == MERGING_MASKING)))
4431 {
4432 i.error = unsupported_masking;
4433 return 1;
4434 }
4435
4436 /* Check if masking is applied to dest operand. */
4437 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4438 {
4439 i.error = mask_not_on_destination;
4440 return 1;
4441 }
4442
43234a1e
L		 4443 /* Check RC/SAE. */
4444 if (i.rounding)
4445 {
4446 if ((i.rounding->type != saeonly
4447 && !t->opcode_modifier.staticrounding)
4448 || (i.rounding->type == saeonly
4449 && (t->opcode_modifier.staticrounding
4450 || !t->opcode_modifier.sae)))
4451 {
4452 i.error = unsupported_rc_sae;
4453 return 1;
4454 }
4455 /* If the instruction has several immediate operands and one of
4456 them is rounding, the rounding operand should be the last
4457 immediate operand. */
4458 if (i.imm_operands > 1
4459 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4460 {
43234a1e 4461 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4462 return 1;
4463 }
6c30d220
L		 4464 }
4465
43234a1e
L		 4466 /* Check vector Disp8 operand. */
4467 if (t->opcode_modifier.disp8memshift)
4468 {
4469 if (i.broadcast)
4470 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4471 else
4472 i.memshift = t->opcode_modifier.disp8memshift;
4473
4474 for (op = 0; op < i.operands; op++)
4475 if (operand_type_check (i.types[op], disp)
4476 && i.op[op].disps->X_op == O_constant)
4477 {
4478 offsetT value = i.op[op].disps->X_add_number;
4479 int vec_disp8_ok = fits_in_vec_disp8 (value);
4480 if (t->operand_types [op].bitfield.vec_disp8)
4481 {
4482 if (vec_disp8_ok)
4483 i.types[op].bitfield.vec_disp8 = 1;
4484 else
4485 {
4486 /* Vector insn can only have Vec_Disp8/Disp32 in
4487 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4488 mode. */
4489 i.types[op].bitfield.disp8 = 0;
4490 if (flag_code != CODE_16BIT)
4491 i.types[op].bitfield.disp16 = 0;
4492 }
4493 }
4494 else if (flag_code != CODE_16BIT)
4495 {
4496 /* One form of this instruction supports vector Disp8.
4497 Try vector Disp8 if we need to use Disp32. */
4498 if (vec_disp8_ok && !fits_in_signed_byte (value))
4499 {
4500 i.error = try_vector_disp8;
4501 return 1;
4502 }
4503 }
4504 }
4505 }
4506 else
4507 i.memshift = -1;
4508
6c30d220
L		 4509 return 0;
4510}
4511
43f3e2ee 4512/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4513 operand types. */
4514
4515static int
4516VEX_check_operands (const insn_template *t)
4517{
43234a1e
L		 4518 /* VREX is only valid with EVEX prefix. */
4519 if (i.need_vrex && !t->opcode_modifier.evex)
4520 {
4521 i.error = invalid_register_operand;
4522 return 1;
4523 }
4524
a683cc34
SP		 4525 if (!t->opcode_modifier.vex)
4526 return 0;
4527
4528 /* Only check VEX_Imm4, which must be the first operand. */
4529 if (t->operand_types[0].bitfield.vec_imm4)
4530 {
4531 if (i.op[0].imms->X_op != O_constant
4532 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4533 {
a65babc9 4534 i.error = bad_imm4;
891edac4
L		 4535 return 1;
4536 }
a683cc34
SP		 4537
4538 /* Turn off Imm8 so that update_imm won't complain. */
4539 i.types[0] = vec_imm4;
4540 }
4541
4542 return 0;
4543}
4544
d3ce72d0 4545static const insn_template *
e3bb37b5 4546match_template (void)
29b0f896
AM		 4547{
4548 /* Points to template once we've found it. */
d3ce72d0 4549 const insn_template *t;
40fb9820 4550 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4551 i386_operand_type overlap4;
29b0f896 4552 unsigned int found_reverse_match;
40fb9820
L		 4553 i386_opcode_modifier suffix_check;
4554 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4555 int addr_prefix_disp;
a5c311ca 4556 unsigned int j;
3629bb00 4557 unsigned int found_cpu_match;
45664ddb 4558 unsigned int check_register;
5614d22c 4559 enum i386_error specific_error = 0;
29b0f896 4560
c0f3af97
L		 4561#if MAX_OPERANDS != 5
4562# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4563#endif
4564
29b0f896 4565 found_reverse_match = 0;
539e75ad 4566 addr_prefix_disp = -1;
40fb9820
L		 4567
4568 memset (&suffix_check, 0, sizeof (suffix_check));
4569 if (i.suffix == BYTE_MNEM_SUFFIX)
4570 suffix_check.no_bsuf = 1;
4571 else if (i.suffix == WORD_MNEM_SUFFIX)
4572 suffix_check.no_wsuf = 1;
4573 else if (i.suffix == SHORT_MNEM_SUFFIX)
4574 suffix_check.no_ssuf = 1;
4575 else if (i.suffix == LONG_MNEM_SUFFIX)
4576 suffix_check.no_lsuf = 1;
4577 else if (i.suffix == QWORD_MNEM_SUFFIX)
4578 suffix_check.no_qsuf = 1;
4579 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4580 suffix_check.no_ldsuf = 1;
29b0f896 4581
01559ecc
L		 4582 /* Must have right number of operands. */
4583 i.error = number_of_operands_mismatch;
4584
45aa61fe 4585 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4586 {
539e75ad
L		 4587 addr_prefix_disp = -1;
4588
29b0f896
AM		 4589 if (i.operands != t->operands)
4590 continue;
4591
50aecf8c 4592 /* Check processor support. */
a65babc9 4593 i.error = unsupported;
c0f3af97
L		 4594 found_cpu_match = (cpu_flags_match (t)
4595 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4596 if (!found_cpu_match)
4597 continue;
4598
e1d4d893 4599 /* Check old gcc support. */
a65babc9 4600 i.error = old_gcc_only;
e1d4d893
L		 4601 if (!old_gcc && t->opcode_modifier.oldgcc)
4602 continue;
4603
4604 /* Check AT&T mnemonic. */
a65babc9 4605 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4606 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4607 continue;
4608
891edac4 4609 /* Check AT&T/Intel syntax. */
a65babc9 4610 i.error = unsupported_syntax;
5c07affc
L		 4611 if ((intel_syntax && t->opcode_modifier.attsyntax)
4612 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 4613 continue;
4614
20592a94 4615 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4616 i.error = invalid_instruction_suffix;
567e4e96
L		 4617 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4618 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4619 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4620 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4621 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4622 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4623 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 4624 continue;
4625
5c07affc 4626 if (!operand_size_match (t))
7d5e4556 4627 continue;
539e75ad 4628
5c07affc
L		 4629 for (j = 0; j < MAX_OPERANDS; j++)
4630 operand_types[j] = t->operand_types[j];
4631
45aa61fe
AM		 4632 /* In general, don't allow 64-bit operands in 32-bit mode. */
4633 if (i.suffix == QWORD_MNEM_SUFFIX
4634 && flag_code != CODE_64BIT
4635 && (intel_syntax
40fb9820 4636 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4637 && !intel_float_operand (t->name))
4638 : intel_float_operand (t->name) != 2)
40fb9820 4639 && ((!operand_types[0].bitfield.regmmx
c0f3af97 4640 && !operand_types[0].bitfield.regxmm
43234a1e
L		 4641 && !operand_types[0].bitfield.regymm
4642 && !operand_types[0].bitfield.regzmm)
40fb9820 4643 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736
AM		 4644 && operand_types[t->operands > 1].bitfield.regxmm
4645 && operand_types[t->operands > 1].bitfield.regymm
4646 && operand_types[t->operands > 1].bitfield.regzmm))
45aa61fe
AM		 4647 && (t->base_opcode != 0x0fc7
4648 || t->extension_opcode != 1 /* cmpxchg8b */))
4649 continue;
4650
192dc9c6
JB		 4651 /* In general, don't allow 32-bit operands on pre-386. */
4652 else if (i.suffix == LONG_MNEM_SUFFIX
4653 && !cpu_arch_flags.bitfield.cpui386
4654 && (intel_syntax
4655 ? (!t->opcode_modifier.ignoresize
4656 && !intel_float_operand (t->name))
4657 : intel_float_operand (t->name) != 2)
4658 && ((!operand_types[0].bitfield.regmmx
4659 && !operand_types[0].bitfield.regxmm)
4660 || (!operand_types[t->operands > 1].bitfield.regmmx
ac4eb736 4661 && operand_types[t->operands > 1].bitfield.regxmm)))
192dc9c6
JB		 4662 continue;
4663
29b0f896 4664 /* Do not verify operands when there are none. */
50aecf8c 4665 else
29b0f896 4666 {
c6fb90c8 4667 if (!t->operands)
2dbab7d5
L		 4668 /* We've found a match; break out of loop. */
4669 break;
29b0f896 4670 }
252b5132 4671
539e75ad
L		 4672 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4673 into Disp32/Disp16/Disp32 operand. */
4674 if (i.prefix[ADDR_PREFIX] != 0)
4675 {
40fb9820 4676 /* There should be only one Disp operand. */
539e75ad
L		 4677 switch (flag_code)
4678 {
4679 case CODE_16BIT:
40fb9820
L		 4680 for (j = 0; j < MAX_OPERANDS; j++)
4681 {
4682 if (operand_types[j].bitfield.disp16)
4683 {
4684 addr_prefix_disp = j;
4685 operand_types[j].bitfield.disp32 = 1;
4686 operand_types[j].bitfield.disp16 = 0;
4687 break;
4688 }
4689 }
539e75ad
L		 4690 break;
4691 case CODE_32BIT:
40fb9820
L		 4692 for (j = 0; j < MAX_OPERANDS; j++)
4693 {
4694 if (operand_types[j].bitfield.disp32)
4695 {
4696 addr_prefix_disp = j;
4697 operand_types[j].bitfield.disp32 = 0;
4698 operand_types[j].bitfield.disp16 = 1;
4699 break;
4700 }
4701 }
539e75ad
L		 4702 break;
4703 case CODE_64BIT:
40fb9820
L		 4704 for (j = 0; j < MAX_OPERANDS; j++)
4705 {
4706 if (operand_types[j].bitfield.disp64)
4707 {
4708 addr_prefix_disp = j;
4709 operand_types[j].bitfield.disp64 = 0;
4710 operand_types[j].bitfield.disp32 = 1;
4711 break;
4712 }
4713 }
539e75ad
L		 4714 break;
4715 }
539e75ad
L		 4716 }
4717
56ffb741
L		 4718 /* We check register size if needed. */
4719 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 4720 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 4721 switch (t->operands)
4722 {
4723 case 1:
40fb9820 4724 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 4725 continue;
4726 break;
4727 case 2:
8b38ad71
L		 4728 /* xchg %eax, %eax is a special case. It is an aliase for nop
4729 only in 32bit mode and we can use opcode 0x90. In 64bit
4730 mode, we can't use 0x90 for xchg %eax, %eax since it should
4731 zero-extend %eax to %rax. */
4732 if (flag_code == CODE_64BIT
4733 && t->base_opcode == 0x90
0dfbf9d7
L		 4734 && operand_type_equal (&i.types [0], &acc32)
4735 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 4736 continue;
b6169b20
L		 4737 if (i.swap_operand)
4738 {
4739 /* If we swap operand in encoding, we either match
4740 the next one or reverse direction of operands. */
4741 if (t->opcode_modifier.s)
4742 continue;
4743 else if (t->opcode_modifier.d)
4744 goto check_reverse;
4745 }
4746
29b0f896 4747 case 3:
fa99fab2
L		 4748 /* If we swap operand in encoding, we match the next one. */
4749 if (i.swap_operand && t->opcode_modifier.s)
4750 continue;
f48ff2ae 4751 case 4:
c0f3af97 4752 case 5:
c6fb90c8 4753 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 4754 if (!operand_type_match (overlap0, i.types[0])
4755 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4756 || (check_register
4757 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 4758 operand_types[0],
4759 overlap1, i.types[1],
4760 operand_types[1])))
29b0f896
AM		 4761 {
4762 /* Check if other direction is valid ... */
40fb9820 4763 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 4764 continue;
4765
b6169b20 4766check_reverse:
29b0f896 4767 /* Try reversing direction of operands. */
c6fb90c8
L		 4768 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4769 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 4770 if (!operand_type_match (overlap0, i.types[0])
4771 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 4772 || (check_register
4773 && !operand_type_register_match (overlap0,
4774 i.types[0],
4775 operand_types[1],
4776 overlap1,
4777 i.types[1],
4778 operand_types[0])))
29b0f896
AM		 4779 {
4780 /* Does not match either direction. */
4781 continue;
4782 }
4783 /* found_reverse_match holds which of D or FloatDR
4784 we've found. */
40fb9820 4785 if (t->opcode_modifier.d)
8a2ed489 4786 found_reverse_match = Opcode_D;
40fb9820 4787 else if (t->opcode_modifier.floatd)
8a2ed489
L		 4788 found_reverse_match = Opcode_FloatD;
4789 else
4790 found_reverse_match = 0;
40fb9820 4791 if (t->opcode_modifier.floatr)
8a2ed489 4792 found_reverse_match |= Opcode_FloatR;
29b0f896 4793 }
f48ff2ae 4794 else
29b0f896 4795 {
f48ff2ae 4796 /* Found a forward 2 operand match here. */
d1cbb4db
L		 4797 switch (t->operands)
4798 {
c0f3af97
L		 4799 case 5:
4800 overlap4 = operand_type_and (i.types[4],
4801 operand_types[4]);
d1cbb4db 4802 case 4:
c6fb90c8
L		 4803 overlap3 = operand_type_and (i.types[3],
4804 operand_types[3]);
d1cbb4db 4805 case 3:
c6fb90c8
L		 4806 overlap2 = operand_type_and (i.types[2],
4807 operand_types[2]);
d1cbb4db
L		 4808 break;
4809 }
29b0f896 4810
f48ff2ae
L		 4811 switch (t->operands)
4812 {
c0f3af97
L		 4813 case 5:
4814 if (!operand_type_match (overlap4, i.types[4])
4815 || !operand_type_register_match (overlap3,
4816 i.types[3],
4817 operand_types[3],
4818 overlap4,
4819 i.types[4],
4820 operand_types[4]))
4821 continue;
f48ff2ae 4822 case 4:
40fb9820 4823 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 4824 || (check_register
4825 && !operand_type_register_match (overlap2,
4826 i.types[2],
4827 operand_types[2],
4828 overlap3,
4829 i.types[3],
4830 operand_types[3])))
f48ff2ae
L		 4831 continue;
4832 case 3:
4833 /* Here we make use of the fact that there are no
4834 reverse match 3 operand instructions, and all 3
4835 operand instructions only need to be checked for
4836 register consistency between operands 2 and 3. */
40fb9820 4837 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 4838 || (check_register
4839 && !operand_type_register_match (overlap1,
4840 i.types[1],
4841 operand_types[1],
4842 overlap2,
4843 i.types[2],
4844 operand_types[2])))
f48ff2ae
L		 4845 continue;
4846 break;
4847 }
29b0f896 4848 }
f48ff2ae 4849 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 4850 slip through to break. */
4851 }
3629bb00 4852 if (!found_cpu_match)
29b0f896
AM		 4853 {
4854 found_reverse_match = 0;
4855 continue;
4856 }
c0f3af97 4857
5614d22c
JB		 4858 /* Check if vector and VEX operands are valid. */
4859 if (check_VecOperands (t) || VEX_check_operands (t))
4860 {
4861 specific_error = i.error;
4862 continue;
4863 }
a683cc34 4864
29b0f896
AM		 4865 /* We've found a match; break out of loop. */
4866 break;
4867 }
4868
4869 if (t == current_templates->end)
4870 {
4871 /* We found no match. */
a65babc9 4872 const char *err_msg;
5614d22c 4873 switch (specific_error ? specific_error : i.error)
a65babc9
L		 4874 {
4875 default:
4876 abort ();
86e026a4 4877 case operand_size_mismatch:
a65babc9
L		 4878 err_msg = _("operand size mismatch");
4879 break;
4880 case operand_type_mismatch:
4881 err_msg = _("operand type mismatch");
4882 break;
4883 case register_type_mismatch:
4884 err_msg = _("register type mismatch");
4885 break;
4886 case number_of_operands_mismatch:
4887 err_msg = _("number of operands mismatch");
4888 break;
4889 case invalid_instruction_suffix:
4890 err_msg = _("invalid instruction suffix");
4891 break;
4892 case bad_imm4:
4a2608e3 4893 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 4894 break;
4895 case old_gcc_only:
4896 err_msg = _("only supported with old gcc");
4897 break;
4898 case unsupported_with_intel_mnemonic:
4899 err_msg = _("unsupported with Intel mnemonic");
4900 break;
4901 case unsupported_syntax:
4902 err_msg = _("unsupported syntax");
4903 break;
4904 case unsupported:
35262a23 4905 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 4906 current_templates->start->name);
4907 return NULL;
6c30d220
L		 4908 case invalid_vsib_address:
4909 err_msg = _("invalid VSIB address");
4910 break;
7bab8ab5
JB		 4911 case invalid_vector_register_set:
4912 err_msg = _("mask, index, and destination registers must be distinct");
4913 break;
6c30d220
L		 4914 case unsupported_vector_index_register:
4915 err_msg = _("unsupported vector index register");
4916 break;
43234a1e
L		 4917 case unsupported_broadcast:
4918 err_msg = _("unsupported broadcast");
4919 break;
4920 case broadcast_not_on_src_operand:
4921 err_msg = _("broadcast not on source memory operand");
4922 break;
4923 case broadcast_needed:
4924 err_msg = _("broadcast is needed for operand of such type");
4925 break;
4926 case unsupported_masking:
4927 err_msg = _("unsupported masking");
4928 break;
4929 case mask_not_on_destination:
4930 err_msg = _("mask not on destination operand");
4931 break;
4932 case no_default_mask:
4933 err_msg = _("default mask isn't allowed");
4934 break;
4935 case unsupported_rc_sae:
4936 err_msg = _("unsupported static rounding/sae");
4937 break;
4938 case rc_sae_operand_not_last_imm:
4939 if (intel_syntax)
4940 err_msg = _("RC/SAE operand must precede immediate operands");
4941 else
4942 err_msg = _("RC/SAE operand must follow immediate operands");
4943 break;
4944 case invalid_register_operand:
4945 err_msg = _("invalid register operand");
4946 break;
a65babc9
L		 4947 }
4948 as_bad (_("%s for `%s'"), err_msg,
891edac4 4949 current_templates->start->name);
fa99fab2 4950 return NULL;
29b0f896 4951 }
252b5132 4952
29b0f896
AM		 4953 if (!quiet_warnings)
4954 {
4955 if (!intel_syntax
40fb9820
L		 4956 && (i.types[0].bitfield.jumpabsolute
4957 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 4958 {
4959 as_warn (_("indirect %s without `*'"), t->name);
4960 }
4961
40fb9820
L		 4962 if (t->opcode_modifier.isprefix
4963 && t->opcode_modifier.ignoresize)
29b0f896
AM		 4964 {
4965 /* Warn them that a data or address size prefix doesn't
4966 affect assembly of the next line of code. */
4967 as_warn (_("stand-alone `%s' prefix"), t->name);
4968 }
4969 }
4970
4971 /* Copy the template we found. */
4972 i.tm = *t;
539e75ad
L		 4973
4974 if (addr_prefix_disp != -1)
4975 i.tm.operand_types[addr_prefix_disp]
4976 = operand_types[addr_prefix_disp];
4977
29b0f896
AM		 4978 if (found_reverse_match)
4979 {
4980 /* If we found a reverse match we must alter the opcode
4981 direction bit. found_reverse_match holds bits to change
4982 (different for int & float insns). */
4983
4984 i.tm.base_opcode ^= found_reverse_match;
4985
539e75ad
L		 4986 i.tm.operand_types[0] = operand_types[1];
4987 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 4988 }
4989
fa99fab2 4990 return t;
29b0f896
AM		 4991}
4992
4993static int
e3bb37b5 4994check_string (void)
29b0f896 4995{
40fb9820
L		 4996 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
4997 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 4998 {
4999 if (i.seg[0] != NULL && i.seg[0] != &es)
5000 {
a87af027 5001 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5002 i.tm.name,
a87af027
JB		 5003 mem_op + 1,
5004 register_prefix);
29b0f896
AM		 5005 return 0;
5006 }
5007 /* There's only ever one segment override allowed per instruction.
5008 This instruction possibly has a legal segment override on the
5009 second operand, so copy the segment to where non-string
5010 instructions store it, allowing common code. */
5011 i.seg[0] = i.seg[1];
5012 }
40fb9820 5013 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5014 {
5015 if (i.seg[1] != NULL && i.seg[1] != &es)
5016 {
a87af027 5017 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5018 i.tm.name,
a87af027
JB		 5019 mem_op + 2,
5020 register_prefix);
29b0f896
AM		 5021 return 0;
5022 }
5023 }
5024 return 1;
5025}
5026
5027static int
543613e9 5028process_suffix (void)
29b0f896
AM		 5029{
5030 /* If matched instruction specifies an explicit instruction mnemonic
5031 suffix, use it. */
40fb9820
L		 5032 if (i.tm.opcode_modifier.size16)
5033 i.suffix = WORD_MNEM_SUFFIX;
5034 else if (i.tm.opcode_modifier.size32)
5035 i.suffix = LONG_MNEM_SUFFIX;
5036 else if (i.tm.opcode_modifier.size64)
5037 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5038 else if (i.reg_operands)
5039 {
5040 /* If there's no instruction mnemonic suffix we try to invent one
5041 based on register operands. */
5042 if (!i.suffix)
5043 {
5044 /* We take i.suffix from the last register operand specified,
5045 Destination register type is more significant than source
381d071f
L		 5046 register type. crc32 in SSE4.2 prefers source register
5047 type. */
5048 if (i.tm.base_opcode == 0xf20f38f1)
5049 {
40fb9820
L		 5050 if (i.types[0].bitfield.reg16)
5051 i.suffix = WORD_MNEM_SUFFIX;
5052 else if (i.types[0].bitfield.reg32)
5053 i.suffix = LONG_MNEM_SUFFIX;
5054 else if (i.types[0].bitfield.reg64)
5055 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5056 }
9344ff29 5057 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5058 {
40fb9820 5059 if (i.types[0].bitfield.reg8)
20592a94
L		 5060 i.suffix = BYTE_MNEM_SUFFIX;
5061 }
381d071f
L		 5062
5063 if (!i.suffix)
5064 {
5065 int op;
5066
20592a94
L		 5067 if (i.tm.base_opcode == 0xf20f38f1
5068 || i.tm.base_opcode == 0xf20f38f0)
5069 {
5070 /* We have to know the operand size for crc32. */
5071 as_bad (_("ambiguous memory operand size for `%s`"),
5072 i.tm.name);
5073 return 0;
5074 }
5075
381d071f 5076 for (op = i.operands; --op >= 0;)
40fb9820 5077 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 5078 {
40fb9820
L		 5079 if (i.types[op].bitfield.reg8)
5080 {
5081 i.suffix = BYTE_MNEM_SUFFIX;
5082 break;
5083 }
5084 else if (i.types[op].bitfield.reg16)
5085 {
5086 i.suffix = WORD_MNEM_SUFFIX;
5087 break;
5088 }
5089 else if (i.types[op].bitfield.reg32)
5090 {
5091 i.suffix = LONG_MNEM_SUFFIX;
5092 break;
5093 }
5094 else if (i.types[op].bitfield.reg64)
5095 {
5096 i.suffix = QWORD_MNEM_SUFFIX;
5097 break;
5098 }
381d071f
L		 5099 }
5100 }
29b0f896
AM		 5101 }
5102 else if (i.suffix == BYTE_MNEM_SUFFIX)
5103 {
2eb952a4
L		 5104 if (intel_syntax
5105 && i.tm.opcode_modifier.ignoresize
5106 && i.tm.opcode_modifier.no_bsuf)
5107 i.suffix = 0;
5108 else if (!check_byte_reg ())
29b0f896
AM		 5109 return 0;
5110 }
5111 else if (i.suffix == LONG_MNEM_SUFFIX)
5112 {
2eb952a4
L		 5113 if (intel_syntax
5114 && i.tm.opcode_modifier.ignoresize
5115 && i.tm.opcode_modifier.no_lsuf)
5116 i.suffix = 0;
5117 else if (!check_long_reg ())
29b0f896
AM		 5118 return 0;
5119 }
5120 else if (i.suffix == QWORD_MNEM_SUFFIX)
5121 {
955e1e6a
L		 5122 if (intel_syntax
5123 && i.tm.opcode_modifier.ignoresize
5124 && i.tm.opcode_modifier.no_qsuf)
5125 i.suffix = 0;
5126 else if (!check_qword_reg ())
29b0f896
AM		 5127 return 0;
5128 }
5129 else if (i.suffix == WORD_MNEM_SUFFIX)
5130 {
2eb952a4
L		 5131 if (intel_syntax
5132 && i.tm.opcode_modifier.ignoresize
5133 && i.tm.opcode_modifier.no_wsuf)
5134 i.suffix = 0;
5135 else if (!check_word_reg ())
29b0f896
AM		 5136 return 0;
5137 }
c0f3af97 5138 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5139 || i.suffix == YMMWORD_MNEM_SUFFIX
5140 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5141 {
43234a1e 5142 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5143 should check if it is a valid suffix. */
5144 }
40fb9820 5145 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5146 /* Do nothing if the instruction is going to ignore the prefix. */
5147 ;
5148 else
5149 abort ();
5150 }
40fb9820 5151 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5152 && !i.suffix
5153 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5154 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5155 {
5156 i.suffix = stackop_size;
5157 }
9306ca4a
JB		 5158 else if (intel_syntax
5159 && !i.suffix
40fb9820
L		 5160 && (i.tm.operand_types[0].bitfield.jumpabsolute
5161 || i.tm.opcode_modifier.jumpbyte
5162 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5163 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5164 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5165 {
5166 switch (flag_code)
5167 {
5168 case CODE_64BIT:
40fb9820 5169 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5170 {
5171 i.suffix = QWORD_MNEM_SUFFIX;
5172 break;
5173 }
5174 case CODE_32BIT:
40fb9820 5175 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5176 i.suffix = LONG_MNEM_SUFFIX;
5177 break;
5178 case CODE_16BIT:
40fb9820 5179 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5180 i.suffix = WORD_MNEM_SUFFIX;
5181 break;
5182 }
5183 }
252b5132 5184
9306ca4a 5185 if (!i.suffix)
29b0f896 5186 {
9306ca4a
JB		 5187 if (!intel_syntax)
5188 {
40fb9820 5189 if (i.tm.opcode_modifier.w)
9306ca4a 5190 {
4eed87de
AM		 5191 as_bad (_("no instruction mnemonic suffix given and "
5192 "no register operands; can't size instruction"));
9306ca4a
JB		 5193 return 0;
5194 }
5195 }
5196 else
5197 {
40fb9820 5198 unsigned int suffixes;
7ab9ffdd 5199
40fb9820
L		 5200 suffixes = !i.tm.opcode_modifier.no_bsuf;
5201 if (!i.tm.opcode_modifier.no_wsuf)
5202 suffixes |= 1 << 1;
5203 if (!i.tm.opcode_modifier.no_lsuf)
5204 suffixes |= 1 << 2;
fc4adea1 5205 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5206 suffixes |= 1 << 3;
5207 if (!i.tm.opcode_modifier.no_ssuf)
5208 suffixes |= 1 << 4;
5209 if (!i.tm.opcode_modifier.no_qsuf)
5210 suffixes |= 1 << 5;
5211
5212 /* There are more than suffix matches. */
5213 if (i.tm.opcode_modifier.w
9306ca4a 5214 || ((suffixes & (suffixes - 1))
40fb9820
L		 5215 && !i.tm.opcode_modifier.defaultsize
5216 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5217 {
5218 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5219 return 0;
5220 }
5221 }
29b0f896 5222 }
252b5132 5223
9306ca4a
JB		 5224 /* Change the opcode based on the operand size given by i.suffix;
5225 We don't need to change things for byte insns. */
5226
582d5edd
L		 5227 if (i.suffix
5228 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5229 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5230 && i.suffix != YMMWORD_MNEM_SUFFIX
5231 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5232 {
5233 /* It's not a byte, select word/dword operation. */
40fb9820 5234 if (i.tm.opcode_modifier.w)
29b0f896 5235 {
40fb9820 5236 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5237 i.tm.base_opcode |= 8;
5238 else
5239 i.tm.base_opcode |= 1;
5240 }
0f3f3d8b 5241
29b0f896
AM		 5242 /* Now select between word & dword operations via the operand
5243 size prefix, except for instructions that will ignore this
5244 prefix anyway. */
ca61edf2 5245 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5246 {
ca61edf2
L		 5247 /* The address size override prefix changes the size of the
5248 first operand. */
40fb9820
L		 5249 if ((flag_code == CODE_32BIT
5250 && i.op->regs[0].reg_type.bitfield.reg16)
5251 || (flag_code != CODE_32BIT
5252 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 5253 if (!add_prefix (ADDR_PREFIX_OPCODE))
5254 return 0;
5255 }
5256 else if (i.suffix != QWORD_MNEM_SUFFIX
5257 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5258 && !i.tm.opcode_modifier.ignoresize
5259 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5260 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5261 || (flag_code == CODE_64BIT
40fb9820 5262 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5263 {
5264 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5265
40fb9820 5266 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5267 prefix = ADDR_PREFIX_OPCODE;
252b5132 5268
29b0f896
AM		 5269 if (!add_prefix (prefix))
5270 return 0;
24eab124 5271 }
252b5132 5272
29b0f896
AM		 5273 /* Set mode64 for an operand. */
5274 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5275 && flag_code == CODE_64BIT
40fb9820 5276 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5277 {
5278 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5279 need rex64. cmpxchg8b is also a special case. */
5280 if (! (i.operands == 2
5281 && i.tm.base_opcode == 0x90
5282 && i.tm.extension_opcode == None
0dfbf9d7
L		 5283 && operand_type_equal (&i.types [0], &acc64)
5284 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5285 && ! (i.operands == 1
5286 && i.tm.base_opcode == 0xfc7
5287 && i.tm.extension_opcode == 1
40fb9820
L		 5288 && !operand_type_check (i.types [0], reg)
5289 && operand_type_check (i.types [0], anymem)))
f6bee062 5290 i.rex |= REX_W;
46e883c5 5291 }
3e73aa7c 5292
29b0f896
AM		 5293 /* Size floating point instruction. */
5294 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5295 if (i.tm.opcode_modifier.floatmf)
543613e9 5296 i.tm.base_opcode ^= 4;
29b0f896 5297 }
7ecd2f8b 5298
29b0f896
AM		 5299 return 1;
5300}
3e73aa7c 5301
29b0f896 5302static int
543613e9 5303check_byte_reg (void)
29b0f896
AM		 5304{
5305 int op;
543613e9 5306
29b0f896
AM		 5307 for (op = i.operands; --op >= 0;)
5308 {
5309 /* If this is an eight bit register, it's OK. If it's the 16 or
5310 32 bit version of an eight bit register, we will just use the
5311 low portion, and that's OK too. */
40fb9820 5312 if (i.types[op].bitfield.reg8)
29b0f896
AM		 5313 continue;
5314
5a819eb9
JB		 5315 /* I/O port address operands are OK too. */
5316 if (i.tm.operand_types[op].bitfield.inoutportreg)
5317 continue;
5318
9344ff29
L		 5319 /* crc32 doesn't generate this warning. */
5320 if (i.tm.base_opcode == 0xf20f38f0)
5321 continue;
5322
40fb9820
L		 5323 if ((i.types[op].bitfield.reg16
5324 || i.types[op].bitfield.reg32
5325 || i.types[op].bitfield.reg64)
5a819eb9
JB		 5326 && i.op[op].regs->reg_num < 4
5327 /* Prohibit these changes in 64bit mode, since the lowering
5328 would be more complicated. */
5329 && flag_code != CODE_64BIT)
29b0f896 5330 {
29b0f896 5331#if REGISTER_WARNINGS
5a819eb9 5332 if (!quiet_warnings)
a540244d
L		 5333 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5334 register_prefix,
40fb9820 5335 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 5336 ? REGNAM_AL - REGNAM_AX
5337 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5338 register_prefix,
29b0f896
AM		 5339 i.op[op].regs->reg_name,
5340 i.suffix);
5341#endif
5342 continue;
5343 }
5344 /* Any other register is bad. */
40fb9820
L		 5345 if (i.types[op].bitfield.reg16
5346 || i.types[op].bitfield.reg32
5347 || i.types[op].bitfield.reg64
5348 || i.types[op].bitfield.regmmx
5349 || i.types[op].bitfield.regxmm
c0f3af97 5350 || i.types[op].bitfield.regymm
43234a1e 5351 || i.types[op].bitfield.regzmm
40fb9820
L		 5352 || i.types[op].bitfield.sreg2
5353 || i.types[op].bitfield.sreg3
5354 || i.types[op].bitfield.control
5355 || i.types[op].bitfield.debug
5356 || i.types[op].bitfield.test
5357 || i.types[op].bitfield.floatreg
5358 || i.types[op].bitfield.floatacc)
29b0f896 5359 {
a540244d
L		 5360 as_bad (_("`%s%s' not allowed with `%s%c'"),
5361 register_prefix,
29b0f896
AM		 5362 i.op[op].regs->reg_name,
5363 i.tm.name,
5364 i.suffix);
5365 return 0;
5366 }
5367 }
5368 return 1;
5369}
5370
5371static int
e3bb37b5 5372check_long_reg (void)
29b0f896
AM		 5373{
5374 int op;
5375
5376 for (op = i.operands; --op >= 0;)
5377 /* Reject eight bit registers, except where the template requires
5378 them. (eg. movzb) */
40fb9820
L		 5379 if (i.types[op].bitfield.reg8
5380 && (i.tm.operand_types[op].bitfield.reg16
5381 || i.tm.operand_types[op].bitfield.reg32
5382 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5383 {
a540244d
L		 5384 as_bad (_("`%s%s' not allowed with `%s%c'"),
5385 register_prefix,
29b0f896
AM		 5386 i.op[op].regs->reg_name,
5387 i.tm.name,
5388 i.suffix);
5389 return 0;
5390 }
e4630f71 5391 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5392 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 5393 && i.types[op].bitfield.reg16
5394 && (i.tm.operand_types[op].bitfield.reg32
5395 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5396 {
5397 /* Prohibit these changes in the 64bit mode, since the
5398 lowering is more complicated. */
5399 if (flag_code == CODE_64BIT)
252b5132 5400 {
2b5d6a91 5401 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5402 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5403 i.suffix);
5404 return 0;
252b5132 5405 }
29b0f896 5406#if REGISTER_WARNINGS
cecf1424
JB		 5407 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5408 register_prefix,
5409 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5410 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5411#endif
252b5132 5412 }
e4630f71 5413 /* Warn if the r prefix on a general reg is present. */
40fb9820
L		 5414 else if (i.types[op].bitfield.reg64
5415 && (i.tm.operand_types[op].bitfield.reg32
5416 || i.tm.operand_types[op].bitfield.acc))
252b5132 5417 {
34828aad 5418 if (intel_syntax
ca61edf2 5419 && i.tm.opcode_modifier.toqword
40fb9820 5420 && !i.types[0].bitfield.regxmm)
34828aad 5421 {
ca61edf2 5422 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5423 i.suffix = QWORD_MNEM_SUFFIX;
5424 }
5425 else
5426 {
2b5d6a91 5427 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5428 register_prefix, i.op[op].regs->reg_name,
5429 i.suffix);
5430 return 0;
5431 }
29b0f896
AM		 5432 }
5433 return 1;
5434}
252b5132 5435
29b0f896 5436static int
e3bb37b5 5437check_qword_reg (void)
29b0f896
AM		 5438{
5439 int op;
252b5132 5440
29b0f896
AM		 5441 for (op = i.operands; --op >= 0; )
5442 /* Reject eight bit registers, except where the template requires
5443 them. (eg. movzb) */
40fb9820
L		 5444 if (i.types[op].bitfield.reg8
5445 && (i.tm.operand_types[op].bitfield.reg16
5446 || i.tm.operand_types[op].bitfield.reg32
5447 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5448 {
a540244d
L		 5449 as_bad (_("`%s%s' not allowed with `%s%c'"),
5450 register_prefix,
29b0f896
AM		 5451 i.op[op].regs->reg_name,
5452 i.tm.name,
5453 i.suffix);
5454 return 0;
5455 }
e4630f71 5456 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 5457 else if ((i.types[op].bitfield.reg16
5458 || i.types[op].bitfield.reg32)
5459 && (i.tm.operand_types[op].bitfield.reg32
5460 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 5461 {
5462 /* Prohibit these changes in the 64bit mode, since the
5463 lowering is more complicated. */
34828aad 5464 if (intel_syntax
ca61edf2 5465 && i.tm.opcode_modifier.todword
40fb9820 5466 && !i.types[0].bitfield.regxmm)
34828aad 5467 {
ca61edf2 5468 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5469 i.suffix = LONG_MNEM_SUFFIX;
5470 }
5471 else
5472 {
2b5d6a91 5473 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5474 register_prefix, i.op[op].regs->reg_name,
5475 i.suffix);
5476 return 0;
5477 }
252b5132 5478 }
29b0f896
AM		 5479 return 1;
5480}
252b5132 5481
29b0f896 5482static int
e3bb37b5 5483check_word_reg (void)
29b0f896
AM		 5484{
5485 int op;
5486 for (op = i.operands; --op >= 0;)
5487 /* Reject eight bit registers, except where the template requires
5488 them. (eg. movzb) */
40fb9820
L		 5489 if (i.types[op].bitfield.reg8
5490 && (i.tm.operand_types[op].bitfield.reg16
5491 || i.tm.operand_types[op].bitfield.reg32
5492 || i.tm.operand_types[op].bitfield.acc))
29b0f896 5493 {
a540244d
L		 5494 as_bad (_("`%s%s' not allowed with `%s%c'"),
5495 register_prefix,
29b0f896
AM		 5496 i.op[op].regs->reg_name,
5497 i.tm.name,
5498 i.suffix);
5499 return 0;
5500 }
e4630f71 5501 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5502 else if ((!quiet_warnings || flag_code == CODE_64BIT)
e4630f71
JB		 5503 && (i.types[op].bitfield.reg32
5504 || i.types[op].bitfield.reg64)
40fb9820
L		 5505 && (i.tm.operand_types[op].bitfield.reg16
5506 || i.tm.operand_types[op].bitfield.acc))
252b5132 5507 {
29b0f896
AM		 5508 /* Prohibit these changes in the 64bit mode, since the
5509 lowering is more complicated. */
5510 if (flag_code == CODE_64BIT)
252b5132 5511 {
2b5d6a91 5512 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5513 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5514 i.suffix);
5515 return 0;
252b5132 5516 }
29b0f896 5517#if REGISTER_WARNINGS
cecf1424
JB		 5518 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5519 register_prefix,
5520 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5521 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5522#endif
5523 }
5524 return 1;
5525}
252b5132 5526
29b0f896 5527static int
40fb9820 5528update_imm (unsigned int j)
29b0f896 5529{
bc0844ae 5530 i386_operand_type overlap = i.types[j];
40fb9820
L		 5531 if ((overlap.bitfield.imm8
5532 || overlap.bitfield.imm8s
5533 || overlap.bitfield.imm16
5534 || overlap.bitfield.imm32
5535 || overlap.bitfield.imm32s
5536 || overlap.bitfield.imm64)
0dfbf9d7
L		 5537 && !operand_type_equal (&overlap, &imm8)
5538 && !operand_type_equal (&overlap, &imm8s)
5539 && !operand_type_equal (&overlap, &imm16)
5540 && !operand_type_equal (&overlap, &imm32)
5541 && !operand_type_equal (&overlap, &imm32s)
5542 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5543 {
5544 if (i.suffix)
5545 {
40fb9820
L		 5546 i386_operand_type temp;
5547
0dfbf9d7 5548 operand_type_set (&temp, 0);
7ab9ffdd 5549 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5550 {
5551 temp.bitfield.imm8 = overlap.bitfield.imm8;
5552 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5553 }
5554 else if (i.suffix == WORD_MNEM_SUFFIX)
5555 temp.bitfield.imm16 = overlap.bitfield.imm16;
5556 else if (i.suffix == QWORD_MNEM_SUFFIX)
5557 {
5558 temp.bitfield.imm64 = overlap.bitfield.imm64;
5559 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5560 }
5561 else
5562 temp.bitfield.imm32 = overlap.bitfield.imm32;
5563 overlap = temp;
29b0f896 5564 }
0dfbf9d7
L		 5565 else if (operand_type_equal (&overlap, &imm16_32_32s)
5566 || operand_type_equal (&overlap, &imm16_32)
5567 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5568 {
40fb9820 5569 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5570 overlap = imm16;
40fb9820 5571 else
65da13b5 5572 overlap = imm32s;
29b0f896 5573 }
0dfbf9d7
L		 5574 if (!operand_type_equal (&overlap, &imm8)
5575 && !operand_type_equal (&overlap, &imm8s)
5576 && !operand_type_equal (&overlap, &imm16)
5577 && !operand_type_equal (&overlap, &imm32)
5578 && !operand_type_equal (&overlap, &imm32s)
5579 && !operand_type_equal (&overlap, &imm64))
29b0f896 5580 {
4eed87de
AM		 5581 as_bad (_("no instruction mnemonic suffix given; "
5582 "can't determine immediate size"));
29b0f896
AM		 5583 return 0;
5584 }
5585 }
40fb9820 5586 i.types[j] = overlap;
29b0f896 5587
40fb9820
L		 5588 return 1;
5589}
5590
5591static int
5592finalize_imm (void)
5593{
bc0844ae 5594 unsigned int j, n;
29b0f896 5595
bc0844ae
L		 5596 /* Update the first 2 immediate operands. */
5597 n = i.operands > 2 ? 2 : i.operands;
5598 if (n)
5599 {
5600 for (j = 0; j < n; j++)
5601 if (update_imm (j) == 0)
5602 return 0;
40fb9820 5603
bc0844ae
L		 5604 /* The 3rd operand can't be immediate operand. */
5605 gas_assert (operand_type_check (i.types[2], imm) == 0);
5606 }
29b0f896
AM		 5607
5608 return 1;
5609}
5610
c0f3af97
L		 5611static int
5612bad_implicit_operand (int xmm)
5613{
91d6fa6a
NC		 5614 const char *ireg = xmm ? "xmm0" : "ymm0";
5615
c0f3af97
L		 5616 if (intel_syntax)
5617 as_bad (_("the last operand of `%s' must be `%s%s'"),
91d6fa6a 5618 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5619 else
5620 as_bad (_("the first operand of `%s' must be `%s%s'"),
91d6fa6a 5621 i.tm.name, register_prefix, ireg);
c0f3af97
L		 5622 return 0;
5623}
5624
29b0f896 5625static int
e3bb37b5 5626process_operands (void)
29b0f896
AM		 5627{
5628 /* Default segment register this instruction will use for memory
5629 accesses. 0 means unknown. This is only for optimizing out
5630 unnecessary segment overrides. */
5631 const seg_entry *default_seg = 0;
5632
2426c15f 5633 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5634 {
91d6fa6a
NC		 5635 unsigned int dupl = i.operands;
5636 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5637 unsigned int j;
5638
c0f3af97 5639 /* The destination must be an xmm register. */
9c2799c2 5640 gas_assert (i.reg_operands
91d6fa6a 5641 && MAX_OPERANDS > dupl
7ab9ffdd 5642 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97
L		 5643
5644 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 5645 {
c0f3af97 5646 /* The first operand is implicit and must be xmm0. */
9c2799c2 5647 gas_assert (operand_type_equal (&i.types[0], &regxmm));
4c692bc7 5648 if (register_number (i.op[0].regs) != 0)
c0f3af97
L		 5649 return bad_implicit_operand (1);
5650
8cd7925b 5651 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5652 {
5653 /* Keep xmm0 for instructions with VEX prefix and 3
5654 sources. */
5655 goto duplicate;
5656 }
e2ec9d29 5657 else
c0f3af97
L		 5658 {
5659 /* We remove the first xmm0 and keep the number of
5660 operands unchanged, which in fact duplicates the
5661 destination. */
5662 for (j = 1; j < i.operands; j++)
5663 {
5664 i.op[j - 1] = i.op[j];
5665 i.types[j - 1] = i.types[j];
5666 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5667 }
5668 }
5669 }
5670 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 5671 {
91d6fa6a 5672 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 5673 && (i.tm.opcode_modifier.vexsources
5674 == VEX3SOURCES));
c0f3af97
L		 5675
5676 /* Add the implicit xmm0 for instructions with VEX prefix
5677 and 3 sources. */
5678 for (j = i.operands; j > 0; j--)
5679 {
5680 i.op[j] = i.op[j - 1];
5681 i.types[j] = i.types[j - 1];
5682 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5683 }
5684 i.op[0].regs
5685 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 5686 i.types[0] = regxmm;
c0f3af97
L		 5687 i.tm.operand_types[0] = regxmm;
5688
5689 i.operands += 2;
5690 i.reg_operands += 2;
5691 i.tm.operands += 2;
5692
91d6fa6a 5693 dupl++;
c0f3af97 5694 dest++;
91d6fa6a
NC		 5695 i.op[dupl] = i.op[dest];
5696 i.types[dupl] = i.types[dest];
5697 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 5698 }
c0f3af97
L		 5699 else
5700 {
5701duplicate:
5702 i.operands++;
5703 i.reg_operands++;
5704 i.tm.operands++;
5705
91d6fa6a
NC		 5706 i.op[dupl] = i.op[dest];
5707 i.types[dupl] = i.types[dest];
5708 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 5709 }
5710
5711 if (i.tm.opcode_modifier.immext)
5712 process_immext ();
5713 }
5714 else if (i.tm.opcode_modifier.firstxmm0)
5715 {
5716 unsigned int j;
5717
43234a1e 5718 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
9c2799c2 5719 gas_assert (i.reg_operands
7ab9ffdd 5720 && (operand_type_equal (&i.types[0], &regxmm)
43234a1e
L		 5721 || operand_type_equal (&i.types[0], &regymm)
5722 || operand_type_equal (&i.types[0], &regzmm)));
4c692bc7 5723 if (register_number (i.op[0].regs) != 0)
c0f3af97 5724 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 5725
5726 for (j = 1; j < i.operands; j++)
5727 {
5728 i.op[j - 1] = i.op[j];
5729 i.types[j - 1] = i.types[j];
5730
5731 /* We need to adjust fields in i.tm since they are used by
5732 build_modrm_byte. */
5733 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5734 }
5735
e2ec9d29
L		 5736 i.operands--;
5737 i.reg_operands--;
e2ec9d29
L		 5738 i.tm.operands--;
5739 }
5740 else if (i.tm.opcode_modifier.regkludge)
5741 {
5742 /* The imul $imm, %reg instruction is converted into
5743 imul $imm, %reg, %reg, and the clr %reg instruction
5744 is converted into xor %reg, %reg. */
5745
5746 unsigned int first_reg_op;
5747
5748 if (operand_type_check (i.types[0], reg))
5749 first_reg_op = 0;
5750 else
5751 first_reg_op = 1;
5752 /* Pretend we saw the extra register operand. */
9c2799c2 5753 gas_assert (i.reg_operands == 1
7ab9ffdd 5754 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 5755 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5756 i.types[first_reg_op + 1] = i.types[first_reg_op];
5757 i.operands++;
5758 i.reg_operands++;
29b0f896
AM		 5759 }
5760
40fb9820 5761 if (i.tm.opcode_modifier.shortform)
29b0f896 5762 {
40fb9820
L		 5763 if (i.types[0].bitfield.sreg2
5764 || i.types[0].bitfield.sreg3)
29b0f896 5765 {
4eed87de
AM		 5766 if (i.tm.base_opcode == POP_SEG_SHORT
5767 && i.op[0].regs->reg_num == 1)
29b0f896 5768 {
a87af027 5769 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5770 return 0;
29b0f896 5771 }
4eed87de
AM		 5772 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5773 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5774 i.rex |= REX_B;
4eed87de
AM		 5775 }
5776 else
5777 {
7ab9ffdd 5778 /* The register or float register operand is in operand
85f10a01 5779 0 or 1. */
40fb9820 5780 unsigned int op;
7ab9ffdd
L		 5781
5782 if (i.types[0].bitfield.floatreg
5783 || operand_type_check (i.types[0], reg))
5784 op = 0;
5785 else
5786 op = 1;
4eed87de
AM		 5787 /* Register goes in low 3 bits of opcode. */
5788 i.tm.base_opcode |= i.op[op].regs->reg_num;
5789 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5790 i.rex |= REX_B;
40fb9820 5791 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5792 {
4eed87de
AM		 5793 /* Warn about some common errors, but press on regardless.
5794 The first case can be generated by gcc (<= 2.8.1). */
5795 if (i.operands == 2)
5796 {
5797 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5798 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5799 register_prefix, i.op[!intel_syntax].regs->reg_name,
5800 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5801 }
5802 else
5803 {
5804 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5805 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5806 register_prefix, i.op[0].regs->reg_name);
4eed87de 5807 }
29b0f896
AM		 5808 }
5809 }
5810 }
40fb9820 5811 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5812 {
5813 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5814 must be put into the modrm byte). Now, we make the modrm and
5815 index base bytes based on all the info we've collected. */
29b0f896
AM		 5816
5817 default_seg = build_modrm_byte ();
5818 }
8a2ed489 5819 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5820 {
5821 default_seg = &ds;
5822 }
40fb9820 5823 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5824 {
5825 /* For the string instructions that allow a segment override
5826 on one of their operands, the default segment is ds. */
5827 default_seg = &ds;
5828 }
5829
75178d9d
L		 5830 if (i.tm.base_opcode == 0x8d /* lea */
5831 && i.seg[0]
5832 && !quiet_warnings)
30123838 5833 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5834
5835 /* If a segment was explicitly specified, and the specified segment
5836 is not the default, use an opcode prefix to select it. If we
5837 never figured out what the default segment is, then default_seg
5838 will be zero at this point, and the specified segment prefix will
5839 always be used. */
29b0f896
AM		 5840 if ((i.seg[0]) && (i.seg[0] != default_seg))
5841 {
5842 if (!add_prefix (i.seg[0]->seg_prefix))
5843 return 0;
5844 }
5845 return 1;
5846}
5847
5848static const seg_entry *
e3bb37b5 5849build_modrm_byte (void)
29b0f896
AM		 5850{
5851 const seg_entry *default_seg = 0;
c0f3af97 5852 unsigned int source, dest;
8cd7925b 5853 int vex_3_sources;
c0f3af97
L		 5854
5855 /* The first operand of instructions with VEX prefix and 3 sources
5856 must be VEX_Imm4. */
8cd7925b 5857 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 5858 if (vex_3_sources)
5859 {
91d6fa6a 5860 unsigned int nds, reg_slot;
4c2c6516 5861 expressionS *exp;
c0f3af97 5862
922d8de8 5863 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 5864 && i.tm.opcode_modifier.immext)
5865 {
5866 dest = i.operands - 2;
5867 gas_assert (dest == 3);
5868 }
922d8de8 5869 else
a683cc34 5870 dest = i.operands - 1;
c0f3af97 5871 nds = dest - 1;
922d8de8 5872
a683cc34
SP		 5873 /* There are 2 kinds of instructions:
5874 1. 5 operands: 4 register operands or 3 register operands
5875 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 5876 VexW0 or VexW1. The destination must be either XMM, YMM or
5877 ZMM register.
a683cc34
SP		 5878 2. 4 operands: 4 register operands or 3 register operands
5879 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 5880 gas_assert ((i.reg_operands == 4
a683cc34
SP		 5881 || (i.reg_operands == 3 && i.mem_operands == 1))
5882 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5883 && (i.tm.opcode_modifier.veximmext
5884 || (i.imm_operands == 1
5885 && i.types[0].bitfield.vec_imm4
5886 && (i.tm.opcode_modifier.vexw == VEXW0
5887 || i.tm.opcode_modifier.vexw == VEXW1)
5888 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 5889 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
5890 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 5891
5892 if (i.imm_operands == 0)
5893 {
5894 /* When there is no immediate operand, generate an 8bit
5895 immediate operand to encode the first operand. */
5896 exp = &im_expressions[i.imm_operands++];
5897 i.op[i.operands].imms = exp;
5898 i.types[i.operands] = imm8;
5899 i.operands++;
5900 /* If VexW1 is set, the first operand is the source and
5901 the second operand is encoded in the immediate operand. */
5902 if (i.tm.opcode_modifier.vexw == VEXW1)
5903 {
5904 source = 0;
5905 reg_slot = 1;
5906 }
5907 else
5908 {
5909 source = 1;
5910 reg_slot = 0;
5911 }
5912
5913 /* FMA swaps REG and NDS. */
5914 if (i.tm.cpu_flags.bitfield.cpufma)
5915 {
5916 unsigned int tmp;
5917 tmp = reg_slot;
5918 reg_slot = nds;
5919 nds = tmp;
5920 }
5921
24981e7b
L		 5922 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5923 &regxmm)
a683cc34 5924 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5925 &regymm)
5926 || operand_type_equal (&i.tm.operand_types[reg_slot],
5927 &regzmm));
a683cc34 5928 exp->X_op = O_constant;
4c692bc7 5929 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 5930 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5931 }
922d8de8 5932 else
a683cc34
SP		 5933 {
5934 unsigned int imm_slot;
5935
5936 if (i.tm.opcode_modifier.vexw == VEXW0)
5937 {
5938 /* If VexW0 is set, the third operand is the source and
5939 the second operand is encoded in the immediate
5940 operand. */
5941 source = 2;
5942 reg_slot = 1;
5943 }
5944 else
5945 {
5946 /* VexW1 is set, the second operand is the source and
5947 the third operand is encoded in the immediate
5948 operand. */
5949 source = 1;
5950 reg_slot = 2;
5951 }
5952
5953 if (i.tm.opcode_modifier.immext)
5954 {
5955 /* When ImmExt is set, the immdiate byte is the last
5956 operand. */
5957 imm_slot = i.operands - 1;
5958 source--;
5959 reg_slot--;
5960 }
5961 else
5962 {
5963 imm_slot = 0;
5964
5965 /* Turn on Imm8 so that output_imm will generate it. */
5966 i.types[imm_slot].bitfield.imm8 = 1;
5967 }
5968
24981e7b
L		 5969 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5970 &regxmm)
5971 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 5972 &regymm)
5973 || operand_type_equal (&i.tm.operand_types[reg_slot],
5974 &regzmm));
a683cc34 5975 i.op[imm_slot].imms->X_add_number
4c692bc7 5976 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 5977 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 5978 }
5979
5980 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5981 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 5982 &regymm)
5983 || operand_type_equal (&i.tm.operand_types[nds],
5984 &regzmm));
dae39acc 5985 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5986 }
5987 else
5988 source = dest = 0;
29b0f896
AM		 5989
5990 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5991 implicit registers do not count. If there are 3 register
5992 operands, it must be a instruction with VexNDS. For a
5993 instruction with VexNDD, the destination register is encoded
5994 in VEX prefix. If there are 4 register operands, it must be
5995 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 5996 if (i.mem_operands == 0
5997 && ((i.reg_operands == 2
2426c15f 5998 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 5999 || (i.reg_operands == 3
2426c15f 6000 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6001 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6002 {
cab737b9
L		 6003 switch (i.operands)
6004 {
6005 case 2:
6006 source = 0;
6007 break;
6008 case 3:
c81128dc
L		 6009 /* When there are 3 operands, one of them may be immediate,
6010 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6011 the first operand must be shift count register (cl) or it
6012 is an instruction with VexNDS. */
9c2799c2 6013 gas_assert (i.imm_operands == 1
7ab9ffdd 6014 || (i.imm_operands == 0
2426c15f 6015 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6016 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6017 if (operand_type_check (i.types[0], imm)
6018 || i.types[0].bitfield.shiftcount)
6019 source = 1;
6020 else
6021 source = 0;
cab737b9
L		 6022 break;
6023 case 4:
368d64cc
L		 6024 /* When there are 4 operands, the first two must be 8bit
6025 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6026 one.
6027
6028 For instructions with VexNDS, if the first operand
6029 an imm8, the source operand is the 2nd one. If the last
6030 operand is imm8, the source operand is the first one. */
9c2799c2 6031 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6032 && i.types[0].bitfield.imm8
6033 && i.types[1].bitfield.imm8)
2426c15f 6034 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6035 && i.imm_operands == 1
6036 && (i.types[0].bitfield.imm8
43234a1e
L		 6037 || i.types[i.operands - 1].bitfield.imm8
6038 || i.rounding)));
9f2670f2
L		 6039 if (i.imm_operands == 2)
6040 source = 2;
6041 else
c0f3af97
L		 6042 {
6043 if (i.types[0].bitfield.imm8)
6044 source = 1;
6045 else
6046 source = 0;
6047 }
c0f3af97
L		 6048 break;
6049 case 5:
43234a1e
L		 6050 if (i.tm.opcode_modifier.evex)
6051 {
6052 /* For EVEX instructions, when there are 5 operands, the
6053 first one must be immediate operand. If the second one
6054 is immediate operand, the source operand is the 3th
6055 one. If the last one is immediate operand, the source
6056 operand is the 2nd one. */
6057 gas_assert (i.imm_operands == 2
6058 && i.tm.opcode_modifier.sae
6059 && operand_type_check (i.types[0], imm));
6060 if (operand_type_check (i.types[1], imm))
6061 source = 2;
6062 else if (operand_type_check (i.types[4], imm))
6063 source = 1;
6064 else
6065 abort ();
6066 }
cab737b9
L		 6067 break;
6068 default:
6069 abort ();
6070 }
6071
c0f3af97
L		 6072 if (!vex_3_sources)
6073 {
6074 dest = source + 1;
6075
43234a1e
L		 6076 /* RC/SAE operand could be between DEST and SRC. That happens
6077 when one operand is GPR and the other one is XMM/YMM/ZMM
6078 register. */
6079 if (i.rounding && i.rounding->operand == (int) dest)
6080 dest++;
6081
2426c15f 6082 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6083 {
43234a1e
L		 6084 /* For instructions with VexNDS, the register-only source
6085 operand must be 32/64bit integer, XMM, YMM or ZMM
6086 register. It is encoded in VEX prefix. We need to
6087 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6088
6089 i386_operand_type op;
6090 unsigned int vvvv;
6091
6092 /* Check register-only source operand when two source
6093 operands are swapped. */
6094 if (!i.tm.operand_types[source].bitfield.baseindex
6095 && i.tm.operand_types[dest].bitfield.baseindex)
6096 {
6097 vvvv = source;
6098 source = dest;
6099 }
6100 else
6101 vvvv = dest;
6102
6103 op = i.tm.operand_types[vvvv];
fa99fab2 6104 op.bitfield.regmem = 0;
c0f3af97 6105 if ((dest + 1) >= i.operands
ac4eb736
AM		 6106 || (!op.bitfield.reg32
6107 && op.bitfield.reg64
f12dc422 6108 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6109 && !operand_type_equal (&op, &regymm)
6110 && !operand_type_equal (&op, &regzmm)
6111 && !operand_type_equal (&op, &regmask)))
c0f3af97 6112 abort ();
f12dc422 6113 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6114 dest++;
6115 }
6116 }
29b0f896
AM		 6117
6118 i.rm.mode = 3;
6119 /* One of the register operands will be encoded in the i.tm.reg
6120 field, the other in the combined i.tm.mode and i.tm.regmem
6121 fields. If no form of this instruction supports a memory
6122 destination operand, then we assume the source operand may
6123 sometimes be a memory operand and so we need to store the
6124 destination in the i.rm.reg field. */
40fb9820
L		 6125 if (!i.tm.operand_types[dest].bitfield.regmem
6126 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6127 {
6128 i.rm.reg = i.op[dest].regs->reg_num;
6129 i.rm.regmem = i.op[source].regs->reg_num;
6130 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6131 i.rex |= REX_R;
43234a1e
L		 6132 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6133 i.vrex |= REX_R;
29b0f896 6134 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6135 i.rex |= REX_B;
43234a1e
L		 6136 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6137 i.vrex |= REX_B;
29b0f896
AM		 6138 }
6139 else
6140 {
6141 i.rm.reg = i.op[source].regs->reg_num;
6142 i.rm.regmem = i.op[dest].regs->reg_num;
6143 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6144 i.rex |= REX_B;
43234a1e
L		 6145 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6146 i.vrex |= REX_B;
29b0f896 6147 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6148 i.rex |= REX_R;
43234a1e
L		 6149 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6150 i.vrex |= REX_R;
29b0f896 6151 }
161a04f6 6152 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6153 {
40fb9820
L		 6154 if (!i.types[0].bitfield.control
6155 && !i.types[1].bitfield.control)
c4a530c5 6156 abort ();
161a04f6 6157 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6158 add_prefix (LOCK_PREFIX_OPCODE);
6159 }
29b0f896
AM		 6160 }
6161 else
6162 { /* If it's not 2 reg operands... */
c0f3af97
L		 6163 unsigned int mem;
6164
29b0f896
AM		 6165 if (i.mem_operands)
6166 {
6167 unsigned int fake_zero_displacement = 0;
99018f42 6168 unsigned int op;
4eed87de 6169
7ab9ffdd
L		 6170 for (op = 0; op < i.operands; op++)
6171 if (operand_type_check (i.types[op], anymem))
6172 break;
7ab9ffdd 6173 gas_assert (op < i.operands);
29b0f896 6174
6c30d220
L		 6175 if (i.tm.opcode_modifier.vecsib)
6176 {
6177 if (i.index_reg->reg_num == RegEiz
6178 || i.index_reg->reg_num == RegRiz)
6179 abort ();
6180
6181 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6182 if (!i.base_reg)
6183 {
6184 i.sib.base = NO_BASE_REGISTER;
6185 i.sib.scale = i.log2_scale_factor;
43234a1e
L		 6186 /* No Vec_Disp8 if there is no base. */
6187 i.types[op].bitfield.vec_disp8 = 0;
6c30d220
L		 6188 i.types[op].bitfield.disp8 = 0;
6189 i.types[op].bitfield.disp16 = 0;
6190 i.types[op].bitfield.disp64 = 0;
6191 if (flag_code != CODE_64BIT)
6192 {
6193 /* Must be 32 bit */
6194 i.types[op].bitfield.disp32 = 1;
6195 i.types[op].bitfield.disp32s = 0;
6196 }
6197 else
6198 {
6199 i.types[op].bitfield.disp32 = 0;
6200 i.types[op].bitfield.disp32s = 1;
6201 }
6202 }
6203 i.sib.index = i.index_reg->reg_num;
6204 if ((i.index_reg->reg_flags & RegRex) != 0)
6205 i.rex |= REX_X;
43234a1e
L		 6206 if ((i.index_reg->reg_flags & RegVRex) != 0)
6207 i.vrex |= REX_X;
6c30d220
L		 6208 }
6209
29b0f896
AM		 6210 default_seg = &ds;
6211
6212 if (i.base_reg == 0)
6213 {
6214 i.rm.mode = 0;
6215 if (!i.disp_operands)
6c30d220
L		 6216 {
6217 fake_zero_displacement = 1;
6218 /* Instructions with VSIB byte need 32bit displacement
6219 if there is no base register. */
6220 if (i.tm.opcode_modifier.vecsib)
6221 i.types[op].bitfield.disp32 = 1;
6222 }
29b0f896
AM		 6223 if (i.index_reg == 0)
6224 {
6c30d220 6225 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6226 /* Operand is just <disp> */
20f0a1fc 6227 if (flag_code == CODE_64BIT)
29b0f896
AM		 6228 {
6229 /* 64bit mode overwrites the 32bit absolute
6230 addressing by RIP relative addressing and
6231 absolute addressing is encoded by one of the
6232 redundant SIB forms. */
6233 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6234 i.sib.base = NO_BASE_REGISTER;
6235 i.sib.index = NO_INDEX_REGISTER;
fc225355 6236 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6237 ? disp32s : disp32);
20f0a1fc 6238 }
fc225355
L		 6239 else if ((flag_code == CODE_16BIT)
6240 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6241 {
6242 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6243 i.types[op] = disp16;
20f0a1fc
NC		 6244 }
6245 else
6246 {
6247 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6248 i.types[op] = disp32;
29b0f896
AM		 6249 }
6250 }
6c30d220 6251 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6252 {
6c30d220 6253 /* !i.base_reg && i.index_reg */
db51cc60
L		 6254 if (i.index_reg->reg_num == RegEiz
6255 || i.index_reg->reg_num == RegRiz)
6256 i.sib.index = NO_INDEX_REGISTER;
6257 else
6258 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6259 i.sib.base = NO_BASE_REGISTER;
6260 i.sib.scale = i.log2_scale_factor;
6261 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
43234a1e
L		 6262 /* No Vec_Disp8 if there is no base. */
6263 i.types[op].bitfield.vec_disp8 = 0;
40fb9820
L		 6264 i.types[op].bitfield.disp8 = 0;
6265 i.types[op].bitfield.disp16 = 0;
6266 i.types[op].bitfield.disp64 = 0;
29b0f896 6267 if (flag_code != CODE_64BIT)
40fb9820
L		 6268 {
6269 /* Must be 32 bit */
6270 i.types[op].bitfield.disp32 = 1;
6271 i.types[op].bitfield.disp32s = 0;
6272 }
29b0f896 6273 else
40fb9820
L		 6274 {
6275 i.types[op].bitfield.disp32 = 0;
6276 i.types[op].bitfield.disp32s = 1;
6277 }
29b0f896 6278 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6279 i.rex |= REX_X;
29b0f896
AM		 6280 }
6281 }
6282 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6283 else if (i.base_reg->reg_num == RegRip ||
6284 i.base_reg->reg_num == RegEip)
29b0f896 6285 {
6c30d220 6286 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6287 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6288 i.types[op].bitfield.disp8 = 0;
6289 i.types[op].bitfield.disp16 = 0;
6290 i.types[op].bitfield.disp32 = 0;
6291 i.types[op].bitfield.disp32s = 1;
6292 i.types[op].bitfield.disp64 = 0;
43234a1e 6293 i.types[op].bitfield.vec_disp8 = 0;
71903a11 6294 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6295 if (! i.disp_operands)
6296 fake_zero_displacement = 1;
29b0f896 6297 }
40fb9820 6298 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896 6299 {
6c30d220 6300 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6301 switch (i.base_reg->reg_num)
6302 {
6303 case 3: /* (%bx) */
6304 if (i.index_reg == 0)
6305 i.rm.regmem = 7;
6306 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6307 i.rm.regmem = i.index_reg->reg_num - 6;
6308 break;
6309 case 5: /* (%bp) */
6310 default_seg = &ss;
6311 if (i.index_reg == 0)
6312 {
6313 i.rm.regmem = 6;
40fb9820 6314 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6315 {
6316 /* fake (%bp) into 0(%bp) */
43234a1e
L		 6317 if (i.tm.operand_types[op].bitfield.vec_disp8)
6318 i.types[op].bitfield.vec_disp8 = 1;
6319 else
6320 i.types[op].bitfield.disp8 = 1;
252b5132 6321 fake_zero_displacement = 1;
29b0f896
AM		 6322 }
6323 }
6324 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6325 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6326 break;
6327 default: /* (%si) -> 4 or (%di) -> 5 */
6328 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6329 }
6330 i.rm.mode = mode_from_disp_size (i.types[op]);
6331 }
6332 else /* i.base_reg and 32/64 bit mode */
6333 {
6334 if (flag_code == CODE_64BIT
40fb9820
L		 6335 && operand_type_check (i.types[op], disp))
6336 {
6337 i386_operand_type temp;
0dfbf9d7 6338 operand_type_set (&temp, 0);
40fb9820 6339 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
43234a1e
L		 6340 temp.bitfield.vec_disp8
6341 = i.types[op].bitfield.vec_disp8;
40fb9820
L		 6342 i.types[op] = temp;
6343 if (i.prefix[ADDR_PREFIX] == 0)
6344 i.types[op].bitfield.disp32s = 1;
6345 else
6346 i.types[op].bitfield.disp32 = 1;
6347 }
20f0a1fc 6348
6c30d220
L		 6349 if (!i.tm.opcode_modifier.vecsib)
6350 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6351 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6352 i.rex |= REX_B;
29b0f896
AM		 6353 i.sib.base = i.base_reg->reg_num;
6354 /* x86-64 ignores REX prefix bit here to avoid decoder
6355 complications. */
848930b2
JB		 6356 if (!(i.base_reg->reg_flags & RegRex)
6357 && (i.base_reg->reg_num == EBP_REG_NUM
6358 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6359 default_seg = &ss;
848930b2 6360 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6361 {
848930b2 6362 fake_zero_displacement = 1;
43234a1e
L		 6363 if (i.tm.operand_types [op].bitfield.vec_disp8)
6364 i.types[op].bitfield.vec_disp8 = 1;
6365 else
6366 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6367 }
6368 i.sib.scale = i.log2_scale_factor;
6369 if (i.index_reg == 0)
6370 {
6c30d220 6371 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6372 /* <disp>(%esp) becomes two byte modrm with no index
6373 register. We've already stored the code for esp
6374 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6375 Any base register besides %esp will not use the
6376 extra modrm byte. */
6377 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6378 }
6c30d220 6379 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6380 {
db51cc60
L		 6381 if (i.index_reg->reg_num == RegEiz
6382 || i.index_reg->reg_num == RegRiz)
6383 i.sib.index = NO_INDEX_REGISTER;
6384 else
6385 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6386 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6387 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6388 i.rex |= REX_X;
29b0f896 6389 }
67a4f2b7
AO		 6390
6391 if (i.disp_operands
6392 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6393 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6394 i.rm.mode = 0;
6395 else
a501d77e
L		 6396 {
6397 if (!fake_zero_displacement
6398 && !i.disp_operands
6399 && i.disp_encoding)
6400 {
6401 fake_zero_displacement = 1;
6402 if (i.disp_encoding == disp_encoding_8bit)
6403 i.types[op].bitfield.disp8 = 1;
6404 else
6405 i.types[op].bitfield.disp32 = 1;
6406 }
6407 i.rm.mode = mode_from_disp_size (i.types[op]);
6408 }
29b0f896 6409 }
252b5132 6410
29b0f896
AM		 6411 if (fake_zero_displacement)
6412 {
6413 /* Fakes a zero displacement assuming that i.types[op]
6414 holds the correct displacement size. */
6415 expressionS *exp;
6416
9c2799c2 6417 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6418 exp = &disp_expressions[i.disp_operands++];
6419 i.op[op].disps = exp;
6420 exp->X_op = O_constant;
6421 exp->X_add_number = 0;
6422 exp->X_add_symbol = (symbolS *) 0;
6423 exp->X_op_symbol = (symbolS *) 0;
6424 }
c0f3af97
L		 6425
6426 mem = op;
29b0f896 6427 }
c0f3af97
L		 6428 else
6429 mem = ~0;
252b5132 6430
8c43a48b 6431 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6432 {
6433 if (operand_type_check (i.types[0], imm))
6434 i.vex.register_specifier = NULL;
6435 else
6436 {
6437 /* VEX.vvvv encodes one of the sources when the first
6438 operand is not an immediate. */
1ef99a7b 6439 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6440 i.vex.register_specifier = i.op[0].regs;
6441 else
6442 i.vex.register_specifier = i.op[1].regs;
6443 }
6444
6445 /* Destination is a XMM register encoded in the ModRM.reg
6446 and VEX.R bit. */
6447 i.rm.reg = i.op[2].regs->reg_num;
6448 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6449 i.rex |= REX_R;
6450
6451 /* ModRM.rm and VEX.B encodes the other source. */
6452 if (!i.mem_operands)
6453 {
6454 i.rm.mode = 3;
6455
1ef99a7b 6456 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6457 i.rm.regmem = i.op[1].regs->reg_num;
6458 else
6459 i.rm.regmem = i.op[0].regs->reg_num;
6460
6461 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6462 i.rex |= REX_B;
6463 }
6464 }
2426c15f 6465 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6466 {
6467 i.vex.register_specifier = i.op[2].regs;
6468 if (!i.mem_operands)
6469 {
6470 i.rm.mode = 3;
6471 i.rm.regmem = i.op[1].regs->reg_num;
6472 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6473 i.rex |= REX_B;
6474 }
6475 }
29b0f896
AM		 6476 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6477 (if any) based on i.tm.extension_opcode. Again, we must be
6478 careful to make sure that segment/control/debug/test/MMX
6479 registers are coded into the i.rm.reg field. */
f88c9eb0 6480 else if (i.reg_operands)
29b0f896 6481 {
99018f42 6482 unsigned int op;
7ab9ffdd
L		 6483 unsigned int vex_reg = ~0;
6484
6485 for (op = 0; op < i.operands; op++)
6486 if (i.types[op].bitfield.reg8
6487 || i.types[op].bitfield.reg16
6488 || i.types[op].bitfield.reg32
6489 || i.types[op].bitfield.reg64
6490 || i.types[op].bitfield.regmmx
6491 || i.types[op].bitfield.regxmm
6492 || i.types[op].bitfield.regymm
7e8b059b 6493 || i.types[op].bitfield.regbnd
43234a1e
L		 6494 || i.types[op].bitfield.regzmm
6495 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6496 || i.types[op].bitfield.sreg2
6497 || i.types[op].bitfield.sreg3
6498 || i.types[op].bitfield.control
6499 || i.types[op].bitfield.debug
6500 || i.types[op].bitfield.test)
6501 break;
c0209578 6502
7ab9ffdd
L		 6503 if (vex_3_sources)
6504 op = dest;
2426c15f 6505 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6506 {
6507 /* For instructions with VexNDS, the register-only
6508 source operand is encoded in VEX prefix. */
6509 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6510
7ab9ffdd 6511 if (op > mem)
c0f3af97 6512 {
7ab9ffdd
L		 6513 vex_reg = op++;
6514 gas_assert (op < i.operands);
c0f3af97
L		 6515 }
6516 else
c0f3af97 6517 {
f12dc422
L		 6518 /* Check register-only source operand when two source
6519 operands are swapped. */
6520 if (!i.tm.operand_types[op].bitfield.baseindex
6521 && i.tm.operand_types[op + 1].bitfield.baseindex)
6522 {
6523 vex_reg = op;
6524 op += 2;
6525 gas_assert (mem == (vex_reg + 1)
6526 && op < i.operands);
6527 }
6528 else
6529 {
6530 vex_reg = op + 1;
6531 gas_assert (vex_reg < i.operands);
6532 }
c0f3af97 6533 }
7ab9ffdd 6534 }
2426c15f 6535 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6536 {
f12dc422 6537 /* For instructions with VexNDD, the register destination
7ab9ffdd 6538 is encoded in VEX prefix. */
f12dc422
L		 6539 if (i.mem_operands == 0)
6540 {
6541 /* There is no memory operand. */
6542 gas_assert ((op + 2) == i.operands);
6543 vex_reg = op + 1;
6544 }
6545 else
8d63c93e 6546 {
f12dc422
L		 6547 /* There are only 2 operands. */
6548 gas_assert (op < 2 && i.operands == 2);
6549 vex_reg = 1;
6550 }
7ab9ffdd
L		 6551 }
6552 else
6553 gas_assert (op < i.operands);
99018f42 6554
7ab9ffdd
L		 6555 if (vex_reg != (unsigned int) ~0)
6556 {
f12dc422 6557 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6558
f12dc422
L		 6559 if (type->bitfield.reg32 != 1
6560 && type->bitfield.reg64 != 1
6561 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6562 && !operand_type_equal (type, &regymm)
6563 && !operand_type_equal (type, &regzmm)
6564 && !operand_type_equal (type, &regmask))
7ab9ffdd 6565 abort ();
f88c9eb0 6566
7ab9ffdd
L		 6567 i.vex.register_specifier = i.op[vex_reg].regs;
6568 }
6569
1b9f0c97
L		 6570 /* Don't set OP operand twice. */
6571 if (vex_reg != op)
7ab9ffdd 6572 {
1b9f0c97
L		 6573 /* If there is an extension opcode to put here, the
6574 register number must be put into the regmem field. */
6575 if (i.tm.extension_opcode != None)
6576 {
6577 i.rm.regmem = i.op[op].regs->reg_num;
6578 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6579 i.rex |= REX_B;
43234a1e
L		 6580 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6581 i.vrex |= REX_B;
1b9f0c97
L		 6582 }
6583 else
6584 {
6585 i.rm.reg = i.op[op].regs->reg_num;
6586 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6587 i.rex |= REX_R;
43234a1e
L		 6588 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6589 i.vrex |= REX_R;
1b9f0c97 6590 }
7ab9ffdd 6591 }
252b5132 6592
29b0f896
AM		 6593 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6594 must set it to 3 to indicate this is a register operand
6595 in the regmem field. */
6596 if (!i.mem_operands)
6597 i.rm.mode = 3;
6598 }
252b5132 6599
29b0f896 6600 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6601 if (i.tm.extension_opcode != None)
29b0f896
AM		 6602 i.rm.reg = i.tm.extension_opcode;
6603 }
6604 return default_seg;
6605}
252b5132 6606
29b0f896 6607static void
e3bb37b5 6608output_branch (void)
29b0f896
AM		 6609{
6610 char *p;
f8a5c266 6611 int size;
29b0f896
AM		 6612 int code16;
6613 int prefix;
6614 relax_substateT subtype;
6615 symbolS *sym;
6616 offsetT off;
6617
f8a5c266 6618 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6619 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6620
6621 prefix = 0;
6622 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6623 {
29b0f896
AM		 6624 prefix = 1;
6625 i.prefixes -= 1;
6626 code16 ^= CODE16;
252b5132 6627 }
29b0f896
AM		 6628 /* Pentium4 branch hints. */
6629 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6630 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6631 {
29b0f896
AM		 6632 prefix++;
6633 i.prefixes--;
6634 }
6635 if (i.prefix[REX_PREFIX] != 0)
6636 {
6637 prefix++;
6638 i.prefixes--;
2f66722d
AM		 6639 }
6640
7e8b059b
L		 6641 /* BND prefixed jump. */
6642 if (i.prefix[BND_PREFIX] != 0)
6643 {
6644 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6645 i.prefixes -= 1;
6646 }
6647
29b0f896
AM		 6648 if (i.prefixes != 0 && !intel_syntax)
6649 as_warn (_("skipping prefixes on this instruction"));
6650
6651 /* It's always a symbol; End frag & setup for relax.
6652 Make sure there is enough room in this frag for the largest
6653 instruction we may generate in md_convert_frag. This is 2
6654 bytes for the opcode and room for the prefix and largest
6655 displacement. */
6656 frag_grow (prefix + 2 + 4);
6657 /* Prefix and 1 opcode byte go in fr_fix. */
6658 p = frag_more (prefix + 1);
6659 if (i.prefix[DATA_PREFIX] != 0)
6660 *p++ = DATA_PREFIX_OPCODE;
6661 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6662 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6663 *p++ = i.prefix[SEG_PREFIX];
6664 if (i.prefix[REX_PREFIX] != 0)
6665 *p++ = i.prefix[REX_PREFIX];
6666 *p = i.tm.base_opcode;
6667
6668 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6669 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6670 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6671 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6672 else
f8a5c266 6673 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6674 subtype |= code16;
3e73aa7c 6675
29b0f896
AM		 6676 sym = i.op[0].disps->X_add_symbol;
6677 off = i.op[0].disps->X_add_number;
3e73aa7c 6678
29b0f896
AM		 6679 if (i.op[0].disps->X_op != O_constant
6680 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 6681 {
29b0f896
AM		 6682 /* Handle complex expressions. */
6683 sym = make_expr_symbol (i.op[0].disps);
6684 off = 0;
6685 }
3e73aa7c 6686
29b0f896
AM		 6687 /* 1 possible extra opcode + 4 byte displacement go in var part.
6688 Pass reloc in fr_var. */
d258b828 6689 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 6690}
3e73aa7c 6691
29b0f896 6692static void
e3bb37b5 6693output_jump (void)
29b0f896
AM		 6694{
6695 char *p;
6696 int size;
3e02c1cc 6697 fixS *fixP;
29b0f896 6698
40fb9820 6699 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 6700 {
6701 /* This is a loop or jecxz type instruction. */
6702 size = 1;
6703 if (i.prefix[ADDR_PREFIX] != 0)
6704 {
6705 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6706 i.prefixes -= 1;
6707 }
6708 /* Pentium4 branch hints. */
6709 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6710 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6711 {
6712 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6713 i.prefixes--;
3e73aa7c
JH		 6714 }
6715 }
29b0f896
AM		 6716 else
6717 {
6718 int code16;
3e73aa7c 6719
29b0f896
AM		 6720 code16 = 0;
6721 if (flag_code == CODE_16BIT)
6722 code16 = CODE16;
3e73aa7c 6723
29b0f896
AM		 6724 if (i.prefix[DATA_PREFIX] != 0)
6725 {
6726 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6727 i.prefixes -= 1;
6728 code16 ^= CODE16;
6729 }
252b5132 6730
29b0f896
AM		 6731 size = 4;
6732 if (code16)
6733 size = 2;
6734 }
9fcc94b6 6735
29b0f896
AM		 6736 if (i.prefix[REX_PREFIX] != 0)
6737 {
6738 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6739 i.prefixes -= 1;
6740 }
252b5132 6741
7e8b059b
L		 6742 /* BND prefixed jump. */
6743 if (i.prefix[BND_PREFIX] != 0)
6744 {
6745 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6746 i.prefixes -= 1;
6747 }
6748
29b0f896
AM		 6749 if (i.prefixes != 0 && !intel_syntax)
6750 as_warn (_("skipping prefixes on this instruction"));
e0890092 6751
42164a71
L		 6752 p = frag_more (i.tm.opcode_length + size);
6753 switch (i.tm.opcode_length)
6754 {
6755 case 2:
6756 *p++ = i.tm.base_opcode >> 8;
6757 case 1:
6758 *p++ = i.tm.base_opcode;
6759 break;
6760 default:
6761 abort ();
6762 }
e0890092 6763
3e02c1cc 6764 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6765 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 6766
6767 /* All jumps handled here are signed, but don't use a signed limit
6768 check for 32 and 16 bit jumps as we want to allow wrap around at
6769 4G and 64k respectively. */
6770 if (size == 1)
6771 fixP->fx_signed = 1;
29b0f896 6772}
e0890092 6773
29b0f896 6774static void
e3bb37b5 6775output_interseg_jump (void)
29b0f896
AM		 6776{
6777 char *p;
6778 int size;
6779 int prefix;
6780 int code16;
252b5132 6781
29b0f896
AM		 6782 code16 = 0;
6783 if (flag_code == CODE_16BIT)
6784 code16 = CODE16;
a217f122 6785
29b0f896
AM		 6786 prefix = 0;
6787 if (i.prefix[DATA_PREFIX] != 0)
6788 {
6789 prefix = 1;
6790 i.prefixes -= 1;
6791 code16 ^= CODE16;
6792 }
6793 if (i.prefix[REX_PREFIX] != 0)
6794 {
6795 prefix++;
6796 i.prefixes -= 1;
6797 }
252b5132 6798
29b0f896
AM		 6799 size = 4;
6800 if (code16)
6801 size = 2;
252b5132 6802
29b0f896
AM		 6803 if (i.prefixes != 0 && !intel_syntax)
6804 as_warn (_("skipping prefixes on this instruction"));
252b5132 6805
29b0f896
AM		 6806 /* 1 opcode; 2 segment; offset */
6807 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 6808
29b0f896
AM		 6809 if (i.prefix[DATA_PREFIX] != 0)
6810 *p++ = DATA_PREFIX_OPCODE;
252b5132 6811
29b0f896
AM		 6812 if (i.prefix[REX_PREFIX] != 0)
6813 *p++ = i.prefix[REX_PREFIX];
252b5132 6814
29b0f896
AM		 6815 *p++ = i.tm.base_opcode;
6816 if (i.op[1].imms->X_op == O_constant)
6817 {
6818 offsetT n = i.op[1].imms->X_add_number;
252b5132 6819
29b0f896
AM		 6820 if (size == 2
6821 && !fits_in_unsigned_word (n)
6822 && !fits_in_signed_word (n))
6823 {
6824 as_bad (_("16-bit jump out of range"));
6825 return;
6826 }
6827 md_number_to_chars (p, n, size);
6828 }
6829 else
6830 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 6831 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 6832 if (i.op[0].imms->X_op != O_constant)
6833 as_bad (_("can't handle non absolute segment in `%s'"),
6834 i.tm.name);
6835 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6836}
a217f122 6837
29b0f896 6838static void
e3bb37b5 6839output_insn (void)
29b0f896 6840{
2bbd9c25
JJ		 6841 fragS *insn_start_frag;
6842 offsetT insn_start_off;
6843
29b0f896
AM		 6844 /* Tie dwarf2 debug info to the address at the start of the insn.
6845 We can't do this after the insn has been output as the current
6846 frag may have been closed off. eg. by frag_var. */
6847 dwarf2_emit_insn (0);
6848
2bbd9c25
JJ		 6849 insn_start_frag = frag_now;
6850 insn_start_off = frag_now_fix ();
6851
29b0f896 6852 /* Output jumps. */
40fb9820 6853 if (i.tm.opcode_modifier.jump)
29b0f896 6854 output_branch ();
40fb9820
L		 6855 else if (i.tm.opcode_modifier.jumpbyte
6856 || i.tm.opcode_modifier.jumpdword)
29b0f896 6857 output_jump ();
40fb9820 6858 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 6859 output_interseg_jump ();
6860 else
6861 {
6862 /* Output normal instructions here. */
6863 char *p;
6864 unsigned char *q;
47465058 6865 unsigned int j;
331d2d0d 6866 unsigned int prefix;
4dffcebc 6867
d022bddd
IT		 6868 /* Some processors fail on LOCK prefix. This options makes
6869 assembler ignore LOCK prefix and serves as a workaround. */
6870 if (omit_lock_prefix)
6871 {
6872 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
6873 return;
6874 i.prefix[LOCK_PREFIX] = 0;
6875 }
6876
43234a1e
L		 6877 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6878 don't need the explicit prefix. */
6879 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 6880 {
c0f3af97 6881 switch (i.tm.opcode_length)
bc4bd9ab 6882 {
c0f3af97
L		 6883 case 3:
6884 if (i.tm.base_opcode & 0xff000000)
4dffcebc 6885 {
c0f3af97
L		 6886 prefix = (i.tm.base_opcode >> 24) & 0xff;
6887 goto check_prefix;
6888 }
6889 break;
6890 case 2:
6891 if ((i.tm.base_opcode & 0xff0000) != 0)
6892 {
6893 prefix = (i.tm.base_opcode >> 16) & 0xff;
6894 if (i.tm.cpu_flags.bitfield.cpupadlock)
6895 {
4dffcebc 6896check_prefix:
c0f3af97 6897 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 6898 || (i.prefix[REP_PREFIX]
c0f3af97
L		 6899 != REPE_PREFIX_OPCODE))
6900 add_prefix (prefix);
6901 }
6902 else
4dffcebc
L		 6903 add_prefix (prefix);
6904 }
c0f3af97
L		 6905 break;
6906 case 1:
6907 break;
6908 default:
6909 abort ();
bc4bd9ab 6910 }
c0f3af97 6911
6d19a37a 6912#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 6913 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
6914 R_X86_64_GOTTPOFF relocation so that linker can safely
6915 perform IE->LE optimization. */
6916 if (x86_elf_abi == X86_64_X32_ABI
6917 && i.operands == 2
6918 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
6919 && i.prefix[REX_PREFIX] == 0)
6920 add_prefix (REX_OPCODE);
6d19a37a 6921#endif
cf61b747 6922
c0f3af97
L		 6923 /* The prefix bytes. */
6924 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6925 if (*q)
6926 FRAG_APPEND_1_CHAR (*q);
0f10071e 6927 }
ae5c1c7b 6928 else
c0f3af97
L		 6929 {
6930 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6931 if (*q)
6932 switch (j)
6933 {
6934 case REX_PREFIX:
6935 /* REX byte is encoded in VEX prefix. */
6936 break;
6937 case SEG_PREFIX:
6938 case ADDR_PREFIX:
6939 FRAG_APPEND_1_CHAR (*q);
6940 break;
6941 default:
6942 /* There should be no other prefixes for instructions
6943 with VEX prefix. */
6944 abort ();
6945 }
6946
43234a1e
L		 6947 /* For EVEX instructions i.vrex should become 0 after
6948 build_evex_prefix. For VEX instructions upper 16 registers
6949 aren't available, so VREX should be 0. */
6950 if (i.vrex)
6951 abort ();
c0f3af97
L		 6952 /* Now the VEX prefix. */
6953 p = frag_more (i.vex.length);
6954 for (j = 0; j < i.vex.length; j++)
6955 p[j] = i.vex.bytes[j];
6956 }
252b5132 6957
29b0f896 6958 /* Now the opcode; be careful about word order here! */
4dffcebc 6959 if (i.tm.opcode_length == 1)
29b0f896
AM		 6960 {
6961 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6962 }
6963 else
6964 {
4dffcebc 6965 switch (i.tm.opcode_length)
331d2d0d 6966 {
43234a1e
L		 6967 case 4:
6968 p = frag_more (4);
6969 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6970 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6971 break;
4dffcebc 6972 case 3:
331d2d0d
L		 6973 p = frag_more (3);
6974 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 6975 break;
6976 case 2:
6977 p = frag_more (2);
6978 break;
6979 default:
6980 abort ();
6981 break;
331d2d0d 6982 }
0f10071e 6983
29b0f896
AM		 6984 /* Put out high byte first: can't use md_number_to_chars! */
6985 *p++ = (i.tm.base_opcode >> 8) & 0xff;
6986 *p = i.tm.base_opcode & 0xff;
6987 }
3e73aa7c 6988
29b0f896 6989 /* Now the modrm byte and sib byte (if present). */
40fb9820 6990 if (i.tm.opcode_modifier.modrm)
29b0f896 6991 {
4a3523fa
L		 6992 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
6993 | i.rm.reg << 3
6994 | i.rm.mode << 6));
29b0f896
AM		 6995 /* If i.rm.regmem == ESP (4)
6996 && i.rm.mode != (Register mode)
6997 && not 16 bit
6998 ==> need second modrm byte. */
6999 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7000 && i.rm.mode != 3
40fb9820 7001 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 7002 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7003 | i.sib.index << 3
7004 | i.sib.scale << 6));
29b0f896 7005 }
3e73aa7c 7006
29b0f896 7007 if (i.disp_operands)
2bbd9c25 7008 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7009
29b0f896 7010 if (i.imm_operands)
2bbd9c25 7011 output_imm (insn_start_frag, insn_start_off);
29b0f896 7012 }
252b5132 7013
29b0f896
AM		 7014#ifdef DEBUG386
7015 if (flag_debug)
7016 {
7b81dfbb 7017 pi ("" /*line*/, &i);
29b0f896
AM		 7018 }
7019#endif /* DEBUG386 */
7020}
252b5132 7021
e205caa7
L		 7022/* Return the size of the displacement operand N. */
7023
7024static int
7025disp_size (unsigned int n)
7026{
7027 int size = 4;
43234a1e
L		 7028
7029 /* Vec_Disp8 has to be 8bit. */
7030 if (i.types[n].bitfield.vec_disp8)
7031 size = 1;
7032 else if (i.types[n].bitfield.disp64)
40fb9820
L		 7033 size = 8;
7034 else if (i.types[n].bitfield.disp8)
7035 size = 1;
7036 else if (i.types[n].bitfield.disp16)
7037 size = 2;
e205caa7
L		 7038 return size;
7039}
7040
7041/* Return the size of the immediate operand N. */
7042
7043static int
7044imm_size (unsigned int n)
7045{
7046 int size = 4;
40fb9820
L		 7047 if (i.types[n].bitfield.imm64)
7048 size = 8;
7049 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7050 size = 1;
7051 else if (i.types[n].bitfield.imm16)
7052 size = 2;
e205caa7
L		 7053 return size;
7054}
7055
29b0f896 7056static void
64e74474 7057output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7058{
7059 char *p;
7060 unsigned int n;
252b5132 7061
29b0f896
AM		 7062 for (n = 0; n < i.operands; n++)
7063 {
43234a1e
L		 7064 if (i.types[n].bitfield.vec_disp8
7065 || operand_type_check (i.types[n], disp))
29b0f896
AM		 7066 {
7067 if (i.op[n].disps->X_op == O_constant)
7068 {
e205caa7 7069 int size = disp_size (n);
43234a1e 7070 offsetT val = i.op[n].disps->X_add_number;
252b5132 7071
43234a1e
L		 7072 if (i.types[n].bitfield.vec_disp8)
7073 val >>= i.memshift;
7074 val = offset_in_range (val, size);
29b0f896
AM		 7075 p = frag_more (size);
7076 md_number_to_chars (p, val, size);
7077 }
7078 else
7079 {
f86103b7 7080 enum bfd_reloc_code_real reloc_type;
e205caa7 7081 int size = disp_size (n);
40fb9820 7082 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 7083 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7084
e205caa7 7085 /* We can't have 8 bit displacement here. */
9c2799c2 7086 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7087
29b0f896
AM		 7088 /* The PC relative address is computed relative
7089 to the instruction boundary, so in case immediate
7090 fields follows, we need to adjust the value. */
7091 if (pcrel && i.imm_operands)
7092 {
29b0f896 7093 unsigned int n1;
e205caa7 7094 int sz = 0;
252b5132 7095
29b0f896 7096 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7097 if (operand_type_check (i.types[n1], imm))
252b5132 7098 {
e205caa7
L		 7099 /* Only one immediate is allowed for PC
7100 relative address. */
9c2799c2 7101 gas_assert (sz == 0);
e205caa7
L		 7102 sz = imm_size (n1);
7103 i.op[n].disps->X_add_number -= sz;
252b5132 7104 }
29b0f896 7105 /* We should find the immediate. */
9c2799c2 7106 gas_assert (sz != 0);
29b0f896 7107 }
520dc8e8 7108
29b0f896 7109 p = frag_more (size);
d258b828 7110 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7111 if (GOT_symbol
2bbd9c25 7112 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7113 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7114 || reloc_type == BFD_RELOC_X86_64_32S
7115 || (reloc_type == BFD_RELOC_64
7116 && object_64bit))
d6ab8113
JB		 7117 && (i.op[n].disps->X_op == O_symbol
7118 || (i.op[n].disps->X_op == O_add
7119 && ((symbol_get_value_expression
7120 (i.op[n].disps->X_op_symbol)->X_op)
7121 == O_subtract))))
7122 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7123 {
7124 offsetT add;
7125
7126 if (insn_start_frag == frag_now)
7127 add = (p - frag_now->fr_literal) - insn_start_off;
7128 else
7129 {
7130 fragS *fr;
7131
7132 add = insn_start_frag->fr_fix - insn_start_off;
7133 for (fr = insn_start_frag->fr_next;
7134 fr && fr != frag_now; fr = fr->fr_next)
7135 add += fr->fr_fix;
7136 add += p - frag_now->fr_literal;
7137 }
7138
4fa24527 7139 if (!object_64bit)
7b81dfbb
AJ		 7140 {
7141 reloc_type = BFD_RELOC_386_GOTPC;
7142 i.op[n].imms->X_add_number += add;
7143 }
7144 else if (reloc_type == BFD_RELOC_64)
7145 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7146 else
7b81dfbb
AJ		 7147 /* Don't do the adjustment for x86-64, as there
7148 the pcrel addressing is relative to the _next_
7149 insn, and that is taken care of in other code. */
d6ab8113 7150 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7151 }
062cd5e7 7152 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 7153 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 7154 }
7155 }
7156 }
7157}
252b5132 7158
29b0f896 7159static void
64e74474 7160output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7161{
7162 char *p;
7163 unsigned int n;
252b5132 7164
29b0f896
AM		 7165 for (n = 0; n < i.operands; n++)
7166 {
43234a1e
L		 7167 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7168 if (i.rounding && (int) n == i.rounding->operand)
7169 continue;
7170
40fb9820 7171 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7172 {
7173 if (i.op[n].imms->X_op == O_constant)
7174 {
e205caa7 7175 int size = imm_size (n);
29b0f896 7176 offsetT val;
b4cac588 7177
29b0f896
AM		 7178 val = offset_in_range (i.op[n].imms->X_add_number,
7179 size);
7180 p = frag_more (size);
7181 md_number_to_chars (p, val, size);
7182 }
7183 else
7184 {
7185 /* Not absolute_section.
7186 Need a 32-bit fixup (don't support 8bit
7187 non-absolute imms). Try to support other
7188 sizes ... */
f86103b7 7189 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7190 int size = imm_size (n);
7191 int sign;
29b0f896 7192
40fb9820 7193 if (i.types[n].bitfield.imm32s
a7d61044 7194 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7195 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7196 sign = 1;
e205caa7
L		 7197 else
7198 sign = 0;
520dc8e8 7199
29b0f896 7200 p = frag_more (size);
d258b828 7201 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7202
2bbd9c25
JJ		 7203 /* This is tough to explain. We end up with this one if we
7204 * have operands that look like
7205 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7206 * obtain the absolute address of the GOT, and it is strongly
7207 * preferable from a performance point of view to avoid using
7208 * a runtime relocation for this. The actual sequence of
7209 * instructions often look something like:
7210 *
7211 * call .L66
7212 * .L66:
7213 * popl %ebx
7214 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7215 *
7216 * The call and pop essentially return the absolute address
7217 * of the label .L66 and store it in %ebx. The linker itself
7218 * will ultimately change the first operand of the addl so
7219 * that %ebx points to the GOT, but to keep things simple, the
7220 * .o file must have this operand set so that it generates not
7221 * the absolute address of .L66, but the absolute address of
7222 * itself. This allows the linker itself simply treat a GOTPC
7223 * relocation as asking for a pcrel offset to the GOT to be
7224 * added in, and the addend of the relocation is stored in the
7225 * operand field for the instruction itself.
7226 *
7227 * Our job here is to fix the operand so that it would add
7228 * the correct offset so that %ebx would point to itself. The
7229 * thing that is tricky is that .-.L66 will point to the
7230 * beginning of the instruction, so we need to further modify
7231 * the operand so that it will point to itself. There are
7232 * other cases where you have something like:
7233 *
7234 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7235 *
7236 * and here no correction would be required. Internally in
7237 * the assembler we treat operands of this form as not being
7238 * pcrel since the '.' is explicitly mentioned, and I wonder
7239 * whether it would simplify matters to do it this way. Who
7240 * knows. In earlier versions of the PIC patches, the
7241 * pcrel_adjust field was used to store the correction, but
7242 * since the expression is not pcrel, I felt it would be
7243 * confusing to do it this way. */
7244
d6ab8113 7245 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7246 || reloc_type == BFD_RELOC_X86_64_32S
7247 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7248 && GOT_symbol
7249 && GOT_symbol == i.op[n].imms->X_add_symbol
7250 && (i.op[n].imms->X_op == O_symbol
7251 || (i.op[n].imms->X_op == O_add
7252 && ((symbol_get_value_expression
7253 (i.op[n].imms->X_op_symbol)->X_op)
7254 == O_subtract))))
7255 {
2bbd9c25
JJ		 7256 offsetT add;
7257
7258 if (insn_start_frag == frag_now)
7259 add = (p - frag_now->fr_literal) - insn_start_off;
7260 else
7261 {
7262 fragS *fr;
7263
7264 add = insn_start_frag->fr_fix - insn_start_off;
7265 for (fr = insn_start_frag->fr_next;
7266 fr && fr != frag_now; fr = fr->fr_next)
7267 add += fr->fr_fix;
7268 add += p - frag_now->fr_literal;
7269 }
7270
4fa24527 7271 if (!object_64bit)
d6ab8113 7272 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7273 else if (size == 4)
d6ab8113 7274 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7275 else if (size == 8)
7276 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7277 i.op[n].imms->X_add_number += add;
29b0f896 7278 }
29b0f896
AM		 7279 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7280 i.op[n].imms, 0, reloc_type);
7281 }
7282 }
7283 }
252b5132
RH		 7284}
7285\f
d182319b
JB		 7286/* x86_cons_fix_new is called via the expression parsing code when a
7287 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7288static int cons_sign = -1;
7289
7290void
e3bb37b5 7291x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7292 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7293{
d258b828 7294 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7295
7296#ifdef TE_PE
7297 if (exp->X_op == O_secrel)
7298 {
7299 exp->X_op = O_symbol;
7300 r = BFD_RELOC_32_SECREL;
7301 }
7302#endif
7303
7304 fix_new_exp (frag, off, len, exp, 0, r);
7305}
7306
357d1bd8
L		 7307/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7308 purpose of the `.dc.a' internal pseudo-op. */
7309
7310int
7311x86_address_bytes (void)
7312{
7313 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7314 return 4;
7315 return stdoutput->arch_info->bits_per_address / 8;
7316}
7317
d382c579
TG		 7318#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7319 || defined (LEX_AT)
d258b828 7320# define lex_got(reloc, adjust, types) NULL
718ddfc0 7321#else
f3c180ae
AM		 7322/* Parse operands of the form
7323 <symbol>@GOTOFF+<nnn>
7324 and similar .plt or .got references.
7325
7326 If we find one, set up the correct relocation in RELOC and copy the
7327 input string, minus the `@GOTOFF' into a malloc'd buffer for
7328 parsing by the calling routine. Return this buffer, and if ADJUST
7329 is non-null set it to the length of the string we removed from the
7330 input line. Otherwise return NULL. */
7331static char *
91d6fa6a 7332lex_got (enum bfd_reloc_code_real *rel,
64e74474 7333 int *adjust,
d258b828 7334 i386_operand_type *types)
f3c180ae 7335{
7b81dfbb
AJ		 7336 /* Some of the relocations depend on the size of what field is to
7337 be relocated. But in our callers i386_immediate and i386_displacement
7338 we don't yet know the operand size (this will be set by insn
7339 matching). Hence we record the word32 relocation here,
7340 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7341 static const struct {
7342 const char *str;
cff8d58a 7343 int len;
4fa24527 7344 const enum bfd_reloc_code_real rel[2];
40fb9820 7345 const i386_operand_type types64;
f3c180ae 7346 } gotrel[] = {
8ce3d284 7347#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7348 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7349 BFD_RELOC_SIZE32 },
7350 OPERAND_TYPE_IMM32_64 },
8ce3d284 7351#endif
cff8d58a
L		 7352 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7353 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7354 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7355 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7356 BFD_RELOC_X86_64_PLT32 },
40fb9820 7357 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7358 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7359 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7360 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7361 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7362 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7363 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7364 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7365 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7366 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7367 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7368 BFD_RELOC_X86_64_TLSGD },
40fb9820 7369 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7370 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7371 _dummy_first_bfd_reloc_code_real },
40fb9820 7372 OPERAND_TYPE_NONE },
cff8d58a
L		 7373 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7374 BFD_RELOC_X86_64_TLSLD },
40fb9820 7375 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7376 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7377 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7378 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7379 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7380 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7381 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7382 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7383 _dummy_first_bfd_reloc_code_real },
40fb9820 7384 OPERAND_TYPE_NONE },
cff8d58a
L		 7385 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7386 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7387 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7388 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7389 _dummy_first_bfd_reloc_code_real },
40fb9820 7390 OPERAND_TYPE_NONE },
cff8d58a
L		 7391 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7392 _dummy_first_bfd_reloc_code_real },
40fb9820 7393 OPERAND_TYPE_NONE },
cff8d58a
L		 7394 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7395 BFD_RELOC_X86_64_GOT32 },
40fb9820 7396 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7397 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7398 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7399 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7400 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7401 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7402 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7403 };
7404 char *cp;
7405 unsigned int j;
7406
d382c579 7407#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7408 if (!IS_ELF)
7409 return NULL;
d382c579 7410#endif
718ddfc0 7411
f3c180ae 7412 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7413 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7414 return NULL;
7415
47465058 7416 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7417 {
cff8d58a 7418 int len = gotrel[j].len;
28f81592 7419 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7420 {
4fa24527 7421 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7422 {
28f81592
AM		 7423 int first, second;
7424 char *tmpbuf, *past_reloc;
f3c180ae 7425
91d6fa6a 7426 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7427
3956db08
JB		 7428 if (types)
7429 {
7430 if (flag_code != CODE_64BIT)
40fb9820
L		 7431 {
7432 types->bitfield.imm32 = 1;
7433 types->bitfield.disp32 = 1;
7434 }
3956db08
JB		 7435 else
7436 *types = gotrel[j].types64;
7437 }
7438
8fd4256d 7439 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7440 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7441
28f81592 7442 /* The length of the first part of our input line. */
f3c180ae 7443 first = cp - input_line_pointer;
28f81592
AM		 7444
7445 /* The second part goes from after the reloc token until
67c11a9b 7446 (and including) an end_of_line char or comma. */
28f81592 7447 past_reloc = cp + 1 + len;
67c11a9b
AM		 7448 cp = past_reloc;
7449 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7450 ++cp;
7451 second = cp + 1 - past_reloc;
28f81592
AM		 7452
7453 /* Allocate and copy string. The trailing NUL shouldn't
7454 be necessary, but be safe. */
1e9cc1c2 7455 tmpbuf = (char *) xmalloc (first + second + 2);
f3c180ae 7456 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7457 if (second != 0 && *past_reloc != ' ')
7458 /* Replace the relocation token with ' ', so that
7459 errors like foo@GOTOFF1 will be detected. */
7460 tmpbuf[first++] = ' ';
af89796a
L		 7461 else
7462 /* Increment length by 1 if the relocation token is
7463 removed. */
7464 len++;
7465 if (adjust)
7466 *adjust = len;
0787a12d
AM		 7467 memcpy (tmpbuf + first, past_reloc, second);
7468 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7469 return tmpbuf;
7470 }
7471
4fa24527
JB		 7472 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7473 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7474 return NULL;
7475 }
7476 }
7477
7478 /* Might be a symbol version string. Don't as_bad here. */
7479 return NULL;
7480}
4e4f7c87 7481#endif
f3c180ae 7482
a988325c
NC		 7483#ifdef TE_PE
7484#ifdef lex_got
7485#undef lex_got
7486#endif
7487/* Parse operands of the form
7488 <symbol>@SECREL32+<nnn>
7489
7490 If we find one, set up the correct relocation in RELOC and copy the
7491 input string, minus the `@SECREL32' into a malloc'd buffer for
7492 parsing by the calling routine. Return this buffer, and if ADJUST
7493 is non-null set it to the length of the string we removed from the
34bca508
L		 7494 input line. Otherwise return NULL.
7495
a988325c
NC		 7496 This function is copied from the ELF version above adjusted for PE targets. */
7497
7498static char *
7499lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7500 int *adjust ATTRIBUTE_UNUSED,
d258b828 7501 i386_operand_type *types)
a988325c
NC		 7502{
7503 static const struct
7504 {
7505 const char *str;
7506 int len;
7507 const enum bfd_reloc_code_real rel[2];
7508 const i386_operand_type types64;
7509 }
7510 gotrel[] =
7511 {
7512 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7513 BFD_RELOC_32_SECREL },
7514 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7515 };
7516
7517 char *cp;
7518 unsigned j;
7519
7520 for (cp = input_line_pointer; *cp != '@'; cp++)
7521 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7522 return NULL;
7523
7524 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7525 {
7526 int len = gotrel[j].len;
7527
7528 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7529 {
7530 if (gotrel[j].rel[object_64bit] != 0)
7531 {
7532 int first, second;
7533 char *tmpbuf, *past_reloc;
7534
7535 *rel = gotrel[j].rel[object_64bit];
7536 if (adjust)
7537 *adjust = len;
7538
7539 if (types)
7540 {
7541 if (flag_code != CODE_64BIT)
7542 {
7543 types->bitfield.imm32 = 1;
7544 types->bitfield.disp32 = 1;
7545 }
7546 else
7547 *types = gotrel[j].types64;
7548 }
7549
7550 /* The length of the first part of our input line. */
7551 first = cp - input_line_pointer;
7552
7553 /* The second part goes from after the reloc token until
7554 (and including) an end_of_line char or comma. */
7555 past_reloc = cp + 1 + len;
7556 cp = past_reloc;
7557 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7558 ++cp;
7559 second = cp + 1 - past_reloc;
7560
7561 /* Allocate and copy string. The trailing NUL shouldn't
7562 be necessary, but be safe. */
7563 tmpbuf = (char *) xmalloc (first + second + 2);
7564 memcpy (tmpbuf, input_line_pointer, first);
7565 if (second != 0 && *past_reloc != ' ')
7566 /* Replace the relocation token with ' ', so that
7567 errors like foo@SECLREL321 will be detected. */
7568 tmpbuf[first++] = ' ';
7569 memcpy (tmpbuf + first, past_reloc, second);
7570 tmpbuf[first + second] = '\0';
7571 return tmpbuf;
7572 }
7573
7574 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7575 gotrel[j].str, 1 << (5 + object_64bit));
7576 return NULL;
7577 }
7578 }
7579
7580 /* Might be a symbol version string. Don't as_bad here. */
7581 return NULL;
7582}
7583
7584#endif /* TE_PE */
7585
62ebcb5c 7586bfd_reloc_code_real_type
e3bb37b5 7587x86_cons (expressionS *exp, int size)
f3c180ae 7588{
62ebcb5c
AM		 7589 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7590
ee86248c
JB		 7591 intel_syntax = -intel_syntax;
7592
3c7b9c2c 7593 exp->X_md = 0;
4fa24527 7594 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7595 {
7596 /* Handle @GOTOFF and the like in an expression. */
7597 char *save;
7598 char *gotfree_input_line;
4a57f2cf 7599 int adjust = 0;
f3c180ae
AM		 7600
7601 save = input_line_pointer;
d258b828 7602 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7603 if (gotfree_input_line)
7604 input_line_pointer = gotfree_input_line;
7605
7606 expression (exp);
7607
7608 if (gotfree_input_line)
7609 {
7610 /* expression () has merrily parsed up to the end of line,
7611 or a comma - in the wrong buffer. Transfer how far
7612 input_line_pointer has moved to the right buffer. */
7613 input_line_pointer = (save
7614 + (input_line_pointer - gotfree_input_line)
7615 + adjust);
7616 free (gotfree_input_line);
3992d3b7
AM		 7617 if (exp->X_op == O_constant
7618 || exp->X_op == O_absent
7619 || exp->X_op == O_illegal
0398aac5 7620 || exp->X_op == O_register
3992d3b7
AM		 7621 || exp->X_op == O_big)
7622 {
7623 char c = *input_line_pointer;
7624 *input_line_pointer = 0;
7625 as_bad (_("missing or invalid expression `%s'"), save);
7626 *input_line_pointer = c;
7627 }
f3c180ae
AM		 7628 }
7629 }
7630 else
7631 expression (exp);
ee86248c
JB		 7632
7633 intel_syntax = -intel_syntax;
7634
7635 if (intel_syntax)
7636 i386_intel_simplify (exp);
62ebcb5c
AM		 7637
7638 return got_reloc;
f3c180ae 7639}
f3c180ae 7640
9f32dd5b
L		 7641static void
7642signed_cons (int size)
6482c264 7643{
d182319b
JB		 7644 if (flag_code == CODE_64BIT)
7645 cons_sign = 1;
7646 cons (size);
7647 cons_sign = -1;
6482c264
NC		 7648}
7649
d182319b 7650#ifdef TE_PE
6482c264 7651static void
7016a5d5 7652pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 7653{
7654 expressionS exp;
7655
7656 do
7657 {
7658 expression (&exp);
7659 if (exp.X_op == O_symbol)
7660 exp.X_op = O_secrel;
7661
7662 emit_expr (&exp, 4);
7663 }
7664 while (*input_line_pointer++ == ',');
7665
7666 input_line_pointer--;
7667 demand_empty_rest_of_line ();
7668}
6482c264
NC		 7669#endif
7670
43234a1e
L		 7671/* Handle Vector operations. */
7672
7673static char *
7674check_VecOperations (char *op_string, char *op_end)
7675{
7676 const reg_entry *mask;
7677 const char *saved;
7678 char *end_op;
7679
7680 while (*op_string
7681 && (op_end == NULL || op_string < op_end))
7682 {
7683 saved = op_string;
7684 if (*op_string == '{')
7685 {
7686 op_string++;
7687
7688 /* Check broadcasts. */
7689 if (strncmp (op_string, "1to", 3) == 0)
7690 {
7691 int bcst_type;
7692
7693 if (i.broadcast)
7694 goto duplicated_vec_op;
7695
7696 op_string += 3;
7697 if (*op_string == '8')
7698 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 7699 else if (*op_string == '4')
7700 bcst_type = BROADCAST_1TO4;
7701 else if (*op_string == '2')
7702 bcst_type = BROADCAST_1TO2;
43234a1e
L		 7703 else if (*op_string == '1'
7704 && *(op_string+1) == '6')
7705 {
7706 bcst_type = BROADCAST_1TO16;
7707 op_string++;
7708 }
7709 else
7710 {
7711 as_bad (_("Unsupported broadcast: `%s'"), saved);
7712 return NULL;
7713 }
7714 op_string++;
7715
7716 broadcast_op.type = bcst_type;
7717 broadcast_op.operand = this_operand;
7718 i.broadcast = &broadcast_op;
7719 }
7720 /* Check masking operation. */
7721 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7722 {
7723 /* k0 can't be used for write mask. */
7724 if (mask->reg_num == 0)
7725 {
7726 as_bad (_("`%s' can't be used for write mask"),
7727 op_string);
7728 return NULL;
7729 }
7730
7731 if (!i.mask)
7732 {
7733 mask_op.mask = mask;
7734 mask_op.zeroing = 0;
7735 mask_op.operand = this_operand;
7736 i.mask = &mask_op;
7737 }
7738 else
7739 {
7740 if (i.mask->mask)
7741 goto duplicated_vec_op;
7742
7743 i.mask->mask = mask;
7744
7745 /* Only "{z}" is allowed here. No need to check
7746 zeroing mask explicitly. */
7747 if (i.mask->operand != this_operand)
7748 {
7749 as_bad (_("invalid write mask `%s'"), saved);
7750 return NULL;
7751 }
7752 }
7753
7754 op_string = end_op;
7755 }
7756 /* Check zeroing-flag for masking operation. */
7757 else if (*op_string == 'z')
7758 {
7759 if (!i.mask)
7760 {
7761 mask_op.mask = NULL;
7762 mask_op.zeroing = 1;
7763 mask_op.operand = this_operand;
7764 i.mask = &mask_op;
7765 }
7766 else
7767 {
7768 if (i.mask->zeroing)
7769 {
7770 duplicated_vec_op:
7771 as_bad (_("duplicated `%s'"), saved);
7772 return NULL;
7773 }
7774
7775 i.mask->zeroing = 1;
7776
7777 /* Only "{%k}" is allowed here. No need to check mask
7778 register explicitly. */
7779 if (i.mask->operand != this_operand)
7780 {
7781 as_bad (_("invalid zeroing-masking `%s'"),
7782 saved);
7783 return NULL;
7784 }
7785 }
7786
7787 op_string++;
7788 }
7789 else
7790 goto unknown_vec_op;
7791
7792 if (*op_string != '}')
7793 {
7794 as_bad (_("missing `}' in `%s'"), saved);
7795 return NULL;
7796 }
7797 op_string++;
7798 continue;
7799 }
7800 unknown_vec_op:
7801 /* We don't know this one. */
7802 as_bad (_("unknown vector operation: `%s'"), saved);
7803 return NULL;
7804 }
7805
7806 return op_string;
7807}
7808
252b5132 7809static int
70e41ade 7810i386_immediate (char *imm_start)
252b5132
RH		 7811{
7812 char *save_input_line_pointer;
f3c180ae 7813 char *gotfree_input_line;
252b5132 7814 segT exp_seg = 0;
47926f60 7815 expressionS *exp;
40fb9820
L		 7816 i386_operand_type types;
7817
0dfbf9d7 7818 operand_type_set (&types, ~0);
252b5132
RH		 7819
7820 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7821 {
31b2323c
L		 7822 as_bad (_("at most %d immediate operands are allowed"),
7823 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 7824 return 0;
7825 }
7826
7827 exp = &im_expressions[i.imm_operands++];
520dc8e8 7828 i.op[this_operand].imms = exp;
252b5132
RH		 7829
7830 if (is_space_char (*imm_start))
7831 ++imm_start;
7832
7833 save_input_line_pointer = input_line_pointer;
7834 input_line_pointer = imm_start;
7835
d258b828 7836 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 7837 if (gotfree_input_line)
7838 input_line_pointer = gotfree_input_line;
252b5132
RH		 7839
7840 exp_seg = expression (exp);
7841
83183c0c 7842 SKIP_WHITESPACE ();
43234a1e
L		 7843
7844 /* Handle vector operations. */
7845 if (*input_line_pointer == '{')
7846 {
7847 input_line_pointer = check_VecOperations (input_line_pointer,
7848 NULL);
7849 if (input_line_pointer == NULL)
7850 return 0;
7851 }
7852
252b5132 7853 if (*input_line_pointer)
f3c180ae 7854 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 7855
7856 input_line_pointer = save_input_line_pointer;
f3c180ae 7857 if (gotfree_input_line)
ee86248c
JB		 7858 {
7859 free (gotfree_input_line);
7860
7861 if (exp->X_op == O_constant || exp->X_op == O_register)
7862 exp->X_op = O_illegal;
7863 }
7864
7865 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7866}
252b5132 7867
ee86248c
JB		 7868static int
7869i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7870 i386_operand_type types, const char *imm_start)
7871{
7872 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 7873 {
313c53d1
L		 7874 if (imm_start)
7875 as_bad (_("missing or invalid immediate expression `%s'"),
7876 imm_start);
3992d3b7 7877 return 0;
252b5132 7878 }
3e73aa7c 7879 else if (exp->X_op == O_constant)
252b5132 7880 {
47926f60 7881 /* Size it properly later. */
40fb9820 7882 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 7883 /* If not 64bit, sign extend val. */
7884 if (flag_code != CODE_64BIT
4eed87de
AM		 7885 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7886 exp->X_add_number
7887 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 7888 }
4c63da97 7889#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 7890 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 7891 && exp_seg != absolute_section
47926f60 7892 && exp_seg != text_section
24eab124
AM		 7893 && exp_seg != data_section
7894 && exp_seg != bss_section
7895 && exp_seg != undefined_section
f86103b7 7896 && !bfd_is_com_section (exp_seg))
252b5132 7897 {
d0b47220 7898 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 7899 return 0;
7900 }
7901#endif
a841bdf5 7902 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 7903 {
313c53d1
L		 7904 if (imm_start)
7905 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 7906 return 0;
7907 }
252b5132
RH		 7908 else
7909 {
7910 /* This is an address. The size of the address will be
24eab124 7911 determined later, depending on destination register,
3e73aa7c 7912 suffix, or the default for the section. */
40fb9820
L		 7913 i.types[this_operand].bitfield.imm8 = 1;
7914 i.types[this_operand].bitfield.imm16 = 1;
7915 i.types[this_operand].bitfield.imm32 = 1;
7916 i.types[this_operand].bitfield.imm32s = 1;
7917 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 7918 i.types[this_operand] = operand_type_and (i.types[this_operand],
7919 types);
252b5132
RH		 7920 }
7921
7922 return 1;
7923}
7924
551c1ca1 7925static char *
e3bb37b5 7926i386_scale (char *scale)
252b5132 7927{
551c1ca1
AM		 7928 offsetT val;
7929 char *save = input_line_pointer;
252b5132 7930
551c1ca1
AM		 7931 input_line_pointer = scale;
7932 val = get_absolute_expression ();
7933
7934 switch (val)
252b5132 7935 {
551c1ca1 7936 case 1:
252b5132
RH		 7937 i.log2_scale_factor = 0;
7938 break;
551c1ca1 7939 case 2:
252b5132
RH		 7940 i.log2_scale_factor = 1;
7941 break;
551c1ca1 7942 case 4:
252b5132
RH		 7943 i.log2_scale_factor = 2;
7944 break;
551c1ca1 7945 case 8:
252b5132
RH		 7946 i.log2_scale_factor = 3;
7947 break;
7948 default:
a724f0f4
JB		 7949 {
7950 char sep = *input_line_pointer;
7951
7952 *input_line_pointer = '\0';
7953 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7954 scale);
7955 *input_line_pointer = sep;
7956 input_line_pointer = save;
7957 return NULL;
7958 }
252b5132 7959 }
29b0f896 7960 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 7961 {
7962 as_warn (_("scale factor of %d without an index register"),
24eab124 7963 1 << i.log2_scale_factor);
252b5132 7964 i.log2_scale_factor = 0;
252b5132 7965 }
551c1ca1
AM		 7966 scale = input_line_pointer;
7967 input_line_pointer = save;
7968 return scale;
252b5132
RH		 7969}
7970
252b5132 7971static int
e3bb37b5 7972i386_displacement (char *disp_start, char *disp_end)
252b5132 7973{
29b0f896 7974 expressionS *exp;
252b5132
RH		 7975 segT exp_seg = 0;
7976 char *save_input_line_pointer;
f3c180ae 7977 char *gotfree_input_line;
40fb9820
L		 7978 int override;
7979 i386_operand_type bigdisp, types = anydisp;
3992d3b7 7980 int ret;
252b5132 7981
31b2323c
L		 7982 if (i.disp_operands == MAX_MEMORY_OPERANDS)
7983 {
7984 as_bad (_("at most %d displacement operands are allowed"),
7985 MAX_MEMORY_OPERANDS);
7986 return 0;
7987 }
7988
0dfbf9d7 7989 operand_type_set (&bigdisp, 0);
40fb9820
L		 7990 if ((i.types[this_operand].bitfield.jumpabsolute)
7991 || (!current_templates->start->opcode_modifier.jump
7992 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 7993 {
40fb9820 7994 bigdisp.bitfield.disp32 = 1;
e05278af 7995 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 7996 if (flag_code == CODE_64BIT)
7997 {
7998 if (!override)
7999 {
8000 bigdisp.bitfield.disp32s = 1;
8001 bigdisp.bitfield.disp64 = 1;
8002 }
8003 }
8004 else if ((flag_code == CODE_16BIT) ^ override)
8005 {
8006 bigdisp.bitfield.disp32 = 0;
8007 bigdisp.bitfield.disp16 = 1;
8008 }
e05278af
JB		 8009 }
8010 else
8011 {
8012 /* For PC-relative branches, the width of the displacement
8013 is dependent upon data size, not address size. */
e05278af 8014 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8015 if (flag_code == CODE_64BIT)
8016 {
8017 if (override || i.suffix == WORD_MNEM_SUFFIX)
8018 bigdisp.bitfield.disp16 = 1;
8019 else
8020 {
8021 bigdisp.bitfield.disp32 = 1;
8022 bigdisp.bitfield.disp32s = 1;
8023 }
8024 }
8025 else
e05278af
JB		 8026 {
8027 if (!override)
8028 override = (i.suffix == (flag_code != CODE_16BIT
8029 ? WORD_MNEM_SUFFIX
8030 : LONG_MNEM_SUFFIX));
40fb9820
L		 8031 bigdisp.bitfield.disp32 = 1;
8032 if ((flag_code == CODE_16BIT) ^ override)
8033 {
8034 bigdisp.bitfield.disp32 = 0;
8035 bigdisp.bitfield.disp16 = 1;
8036 }
e05278af 8037 }
e05278af 8038 }
c6fb90c8
L		 8039 i.types[this_operand] = operand_type_or (i.types[this_operand],
8040 bigdisp);
252b5132
RH		 8041
8042 exp = &disp_expressions[i.disp_operands];
520dc8e8 8043 i.op[this_operand].disps = exp;
252b5132
RH		 8044 i.disp_operands++;
8045 save_input_line_pointer = input_line_pointer;
8046 input_line_pointer = disp_start;
8047 END_STRING_AND_SAVE (disp_end);
8048
8049#ifndef GCC_ASM_O_HACK
8050#define GCC_ASM_O_HACK 0
8051#endif
8052#if GCC_ASM_O_HACK
8053 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8054 if (i.types[this_operand].bitfield.baseIndex
24eab124 8055 && displacement_string_end[-1] == '+')
252b5132
RH		 8056 {
8057 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8058 constraint within gcc asm statements.
8059 For instance:
8060
8061 #define _set_tssldt_desc(n,addr,limit,type) \
8062 __asm__ __volatile__ ( \
8063 "movw %w2,%0\n\t" \
8064 "movw %w1,2+%0\n\t" \
8065 "rorl $16,%1\n\t" \
8066 "movb %b1,4+%0\n\t" \
8067 "movb %4,5+%0\n\t" \
8068 "movb $0,6+%0\n\t" \
8069 "movb %h1,7+%0\n\t" \
8070 "rorl $16,%1" \
8071 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8072
8073 This works great except that the output assembler ends
8074 up looking a bit weird if it turns out that there is
8075 no offset. You end up producing code that looks like:
8076
8077 #APP
8078 movw $235,(%eax)
8079 movw %dx,2+(%eax)
8080 rorl $16,%edx
8081 movb %dl,4+(%eax)
8082 movb $137,5+(%eax)
8083 movb $0,6+(%eax)
8084 movb %dh,7+(%eax)
8085 rorl $16,%edx
8086 #NO_APP
8087
47926f60 8088 So here we provide the missing zero. */
24eab124
AM		 8089
8090 *displacement_string_end = '0';
252b5132
RH		 8091 }
8092#endif
d258b828 8093 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8094 if (gotfree_input_line)
8095 input_line_pointer = gotfree_input_line;
252b5132 8096
24eab124 8097 exp_seg = expression (exp);
252b5132 8098
636c26b0
AM		 8099 SKIP_WHITESPACE ();
8100 if (*input_line_pointer)
8101 as_bad (_("junk `%s' after expression"), input_line_pointer);
8102#if GCC_ASM_O_HACK
8103 RESTORE_END_STRING (disp_end + 1);
8104#endif
636c26b0 8105 input_line_pointer = save_input_line_pointer;
636c26b0 8106 if (gotfree_input_line)
ee86248c
JB		 8107 {
8108 free (gotfree_input_line);
8109
8110 if (exp->X_op == O_constant || exp->X_op == O_register)
8111 exp->X_op = O_illegal;
8112 }
8113
8114 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8115
8116 RESTORE_END_STRING (disp_end);
8117
8118 return ret;
8119}
8120
8121static int
8122i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8123 i386_operand_type types, const char *disp_start)
8124{
8125 i386_operand_type bigdisp;
8126 int ret = 1;
636c26b0 8127
24eab124
AM		 8128 /* We do this to make sure that the section symbol is in
8129 the symbol table. We will ultimately change the relocation
47926f60 8130 to be relative to the beginning of the section. */
1ae12ab7 8131 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8132 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8133 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8134 {
636c26b0 8135 if (exp->X_op != O_symbol)
3992d3b7 8136 goto inv_disp;
636c26b0 8137
e5cb08ac 8138 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8139 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8140 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8141 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8142 exp->X_op = O_subtract;
8143 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8144 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8145 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8146 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8147 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8148 else
29b0f896 8149 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8150 }
252b5132 8151
3992d3b7
AM		 8152 else if (exp->X_op == O_absent
8153 || exp->X_op == O_illegal
ee86248c 8154 || exp->X_op == O_big)
2daf4fd8 8155 {
3992d3b7
AM		 8156 inv_disp:
8157 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8158 disp_start);
3992d3b7 8159 ret = 0;
2daf4fd8
AM		 8160 }
8161
0e1147d9
L		 8162 else if (flag_code == CODE_64BIT
8163 && !i.prefix[ADDR_PREFIX]
8164 && exp->X_op == O_constant)
8165 {
8166 /* Since displacement is signed extended to 64bit, don't allow
8167 disp32 and turn off disp32s if they are out of range. */
8168 i.types[this_operand].bitfield.disp32 = 0;
8169 if (!fits_in_signed_long (exp->X_add_number))
8170 {
8171 i.types[this_operand].bitfield.disp32s = 0;
8172 if (i.types[this_operand].bitfield.baseindex)
8173 {
8174 as_bad (_("0x%lx out range of signed 32bit displacement"),
8175 (long) exp->X_add_number);
8176 ret = 0;
8177 }
8178 }
8179 }
8180
4c63da97 8181#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8182 else if (exp->X_op != O_constant
8183 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8184 && exp_seg != absolute_section
8185 && exp_seg != text_section
8186 && exp_seg != data_section
8187 && exp_seg != bss_section
8188 && exp_seg != undefined_section
8189 && !bfd_is_com_section (exp_seg))
24eab124 8190 {
d0b47220 8191 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8192 ret = 0;
24eab124 8193 }
252b5132 8194#endif
3956db08 8195
40fb9820
L		 8196 /* Check if this is a displacement only operand. */
8197 bigdisp = i.types[this_operand];
8198 bigdisp.bitfield.disp8 = 0;
8199 bigdisp.bitfield.disp16 = 0;
8200 bigdisp.bitfield.disp32 = 0;
8201 bigdisp.bitfield.disp32s = 0;
8202 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8203 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8204 i.types[this_operand] = operand_type_and (i.types[this_operand],
8205 types);
3956db08 8206
3992d3b7 8207 return ret;
252b5132
RH		 8208}
8209
eecb386c 8210/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 8211 Return 1 on success, 0 on a failure. */
8212
252b5132 8213static int
e3bb37b5 8214i386_index_check (const char *operand_string)
252b5132 8215{
fc0763e6 8216 const char *kind = "base/index";
be05d201
L		 8217 enum flag_code addr_mode;
8218
8219 if (i.prefix[ADDR_PREFIX])
8220 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8221 else
8222 {
8223 addr_mode = flag_code;
8224
24eab124 8225#if INFER_ADDR_PREFIX
be05d201
L		 8226 if (i.mem_operands == 0)
8227 {
8228 /* Infer address prefix from the first memory operand. */
8229 const reg_entry *addr_reg = i.base_reg;
8230
8231 if (addr_reg == NULL)
8232 addr_reg = i.index_reg;
eecb386c 8233
be05d201
L		 8234 if (addr_reg)
8235 {
8236 if (addr_reg->reg_num == RegEip
8237 || addr_reg->reg_num == RegEiz
8238 || addr_reg->reg_type.bitfield.reg32)
8239 addr_mode = CODE_32BIT;
8240 else if (flag_code != CODE_64BIT
8241 && addr_reg->reg_type.bitfield.reg16)
8242 addr_mode = CODE_16BIT;
8243
8244 if (addr_mode != flag_code)
8245 {
8246 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8247 i.prefixes += 1;
8248 /* Change the size of any displacement too. At most one
8249 of Disp16 or Disp32 is set.
8250 FIXME. There doesn't seem to be any real need for
8251 separate Disp16 and Disp32 flags. The same goes for
8252 Imm16 and Imm32. Removing them would probably clean
8253 up the code quite a lot. */
8254 if (flag_code != CODE_64BIT
8255 && (i.types[this_operand].bitfield.disp16
8256 || i.types[this_operand].bitfield.disp32))
8257 i.types[this_operand]
8258 = operand_type_xor (i.types[this_operand], disp16_32);
8259 }
8260 }
8261 }
24eab124 8262#endif
be05d201
L		 8263 }
8264
fc0763e6
JB		 8265 if (current_templates->start->opcode_modifier.isstring
8266 && !current_templates->start->opcode_modifier.immext
8267 && (current_templates->end[-1].opcode_modifier.isstring
8268 || i.mem_operands))
8269 {
8270 /* Memory operands of string insns are special in that they only allow
8271 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8272 const reg_entry *expected_reg;
8273 static const char *di_si[][2] =
8274 {
8275 { "esi", "edi" },
8276 { "si", "di" },
8277 { "rsi", "rdi" }
8278 };
8279 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8280
8281 kind = "string address";
8282
8283 if (current_templates->start->opcode_modifier.w)
8284 {
8285 i386_operand_type type = current_templates->end[-1].operand_types[0];
8286
8287 if (!type.bitfield.baseindex
8288 || ((!i.mem_operands != !intel_syntax)
8289 && current_templates->end[-1].operand_types[1]
8290 .bitfield.baseindex))
8291 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8292 expected_reg = hash_find (reg_hash,
8293 di_si[addr_mode][type.bitfield.esseg]);
8294
fc0763e6
JB		 8295 }
8296 else
be05d201 8297 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8298
be05d201
L		 8299 if (i.base_reg != expected_reg
8300 || i.index_reg
fc0763e6 8301 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8302 {
be05d201
L		 8303 /* The second memory operand must have the same size as
8304 the first one. */
8305 if (i.mem_operands
8306 && i.base_reg
8307 && !((addr_mode == CODE_64BIT
8308 && i.base_reg->reg_type.bitfield.reg64)
8309 || (addr_mode == CODE_32BIT
8310 ? i.base_reg->reg_type.bitfield.reg32
8311 : i.base_reg->reg_type.bitfield.reg16)))
8312 goto bad_address;
8313
fc0763e6
JB		 8314 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8315 operand_string,
8316 intel_syntax ? '[' : '(',
8317 register_prefix,
be05d201 8318 expected_reg->reg_name,
fc0763e6 8319 intel_syntax ? ']' : ')');
be05d201 8320 return 1;
fc0763e6 8321 }
be05d201
L		 8322 else
8323 return 1;
8324
8325bad_address:
8326 as_bad (_("`%s' is not a valid %s expression"),
8327 operand_string, kind);
8328 return 0;
3e73aa7c
JH		 8329 }
8330 else
8331 {
be05d201
L		 8332 if (addr_mode != CODE_16BIT)
8333 {
8334 /* 32-bit/64-bit checks. */
8335 if ((i.base_reg
8336 && (addr_mode == CODE_64BIT
8337 ? !i.base_reg->reg_type.bitfield.reg64
8338 : !i.base_reg->reg_type.bitfield.reg32)
8339 && (i.index_reg
8340 || (i.base_reg->reg_num
8341 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8342 || (i.index_reg
8343 && !i.index_reg->reg_type.bitfield.regxmm
8344 && !i.index_reg->reg_type.bitfield.regymm
43234a1e 8345 && !i.index_reg->reg_type.bitfield.regzmm
be05d201
L		 8346 && ((addr_mode == CODE_64BIT
8347 ? !(i.index_reg->reg_type.bitfield.reg64
8348 || i.index_reg->reg_num == RegRiz)
8349 : !(i.index_reg->reg_type.bitfield.reg32
8350 || i.index_reg->reg_num == RegEiz))
8351 || !i.index_reg->reg_type.bitfield.baseindex)))
8352 goto bad_address;
8353 }
8354 else
3e73aa7c 8355 {
be05d201 8356 /* 16-bit checks. */
3e73aa7c 8357 if ((i.base_reg
40fb9820
L		 8358 && (!i.base_reg->reg_type.bitfield.reg16
8359 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8360 || (i.index_reg
40fb9820
L		 8361 && (!i.index_reg->reg_type.bitfield.reg16
8362 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8363 || !(i.base_reg
8364 && i.base_reg->reg_num < 6
8365 && i.index_reg->reg_num >= 6
8366 && i.log2_scale_factor == 0))))
be05d201 8367 goto bad_address;
3e73aa7c
JH		 8368 }
8369 }
be05d201 8370 return 1;
24eab124 8371}
252b5132 8372
43234a1e
L		 8373/* Handle vector immediates. */
8374
8375static int
8376RC_SAE_immediate (const char *imm_start)
8377{
8378 unsigned int match_found, j;
8379 const char *pstr = imm_start;
8380 expressionS *exp;
8381
8382 if (*pstr != '{')
8383 return 0;
8384
8385 pstr++;
8386 match_found = 0;
8387 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8388 {
8389 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8390 {
8391 if (!i.rounding)
8392 {
8393 rc_op.type = RC_NamesTable[j].type;
8394 rc_op.operand = this_operand;
8395 i.rounding = &rc_op;
8396 }
8397 else
8398 {
8399 as_bad (_("duplicated `%s'"), imm_start);
8400 return 0;
8401 }
8402 pstr += RC_NamesTable[j].len;
8403 match_found = 1;
8404 break;
8405 }
8406 }
8407 if (!match_found)
8408 return 0;
8409
8410 if (*pstr++ != '}')
8411 {
8412 as_bad (_("Missing '}': '%s'"), imm_start);
8413 return 0;
8414 }
8415 /* RC/SAE immediate string should contain nothing more. */;
8416 if (*pstr != 0)
8417 {
8418 as_bad (_("Junk after '}': '%s'"), imm_start);
8419 return 0;
8420 }
8421
8422 exp = &im_expressions[i.imm_operands++];
8423 i.op[this_operand].imms = exp;
8424
8425 exp->X_op = O_constant;
8426 exp->X_add_number = 0;
8427 exp->X_add_symbol = (symbolS *) 0;
8428 exp->X_op_symbol = (symbolS *) 0;
8429
8430 i.types[this_operand].bitfield.imm8 = 1;
8431 return 1;
8432}
8433
fc0763e6 8434/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8435 on error. */
252b5132 8436
252b5132 8437static int
a7619375 8438i386_att_operand (char *operand_string)
252b5132 8439{
af6bdddf
AM		 8440 const reg_entry *r;
8441 char *end_op;
24eab124 8442 char *op_string = operand_string;
252b5132 8443
24eab124 8444 if (is_space_char (*op_string))
252b5132
RH		 8445 ++op_string;
8446
24eab124 8447 /* We check for an absolute prefix (differentiating,
47926f60 8448 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8449 if (*op_string == ABSOLUTE_PREFIX)
8450 {
8451 ++op_string;
8452 if (is_space_char (*op_string))
8453 ++op_string;
40fb9820 8454 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8455 }
252b5132 8456
47926f60 8457 /* Check if operand is a register. */
4d1bb795 8458 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8459 {
40fb9820
L		 8460 i386_operand_type temp;
8461
24eab124
AM		 8462 /* Check for a segment override by searching for ':' after a
8463 segment register. */
8464 op_string = end_op;
8465 if (is_space_char (*op_string))
8466 ++op_string;
40fb9820
L		 8467 if (*op_string == ':'
8468 && (r->reg_type.bitfield.sreg2
8469 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8470 {
8471 switch (r->reg_num)
8472 {
8473 case 0:
8474 i.seg[i.mem_operands] = &es;
8475 break;
8476 case 1:
8477 i.seg[i.mem_operands] = &cs;
8478 break;
8479 case 2:
8480 i.seg[i.mem_operands] = &ss;
8481 break;
8482 case 3:
8483 i.seg[i.mem_operands] = &ds;
8484 break;
8485 case 4:
8486 i.seg[i.mem_operands] = &fs;
8487 break;
8488 case 5:
8489 i.seg[i.mem_operands] = &gs;
8490 break;
8491 }
252b5132 8492
24eab124 8493 /* Skip the ':' and whitespace. */
252b5132
RH		 8494 ++op_string;
8495 if (is_space_char (*op_string))
24eab124 8496 ++op_string;
252b5132 8497
24eab124
AM		 8498 if (!is_digit_char (*op_string)
8499 && !is_identifier_char (*op_string)
8500 && *op_string != '('
8501 && *op_string != ABSOLUTE_PREFIX)
8502 {
8503 as_bad (_("bad memory operand `%s'"), op_string);
8504 return 0;
8505 }
47926f60 8506 /* Handle case of %es:*foo. */
24eab124
AM		 8507 if (*op_string == ABSOLUTE_PREFIX)
8508 {
8509 ++op_string;
8510 if (is_space_char (*op_string))
8511 ++op_string;
40fb9820 8512 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8513 }
8514 goto do_memory_reference;
8515 }
43234a1e
L		 8516
8517 /* Handle vector operations. */
8518 if (*op_string == '{')
8519 {
8520 op_string = check_VecOperations (op_string, NULL);
8521 if (op_string == NULL)
8522 return 0;
8523 }
8524
24eab124
AM		 8525 if (*op_string)
8526 {
d0b47220 8527 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8528 return 0;
8529 }
40fb9820
L		 8530 temp = r->reg_type;
8531 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8532 i.types[this_operand] = operand_type_or (i.types[this_operand],
8533 temp);
7d5e4556 8534 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8535 i.op[this_operand].regs = r;
24eab124
AM		 8536 i.reg_operands++;
8537 }
af6bdddf
AM		 8538 else if (*op_string == REGISTER_PREFIX)
8539 {
8540 as_bad (_("bad register name `%s'"), op_string);
8541 return 0;
8542 }
24eab124 8543 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8544 {
24eab124 8545 ++op_string;
40fb9820 8546 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8547 {
d0b47220 8548 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8549 return 0;
8550 }
8551 if (!i386_immediate (op_string))
8552 return 0;
8553 }
43234a1e
L		 8554 else if (RC_SAE_immediate (operand_string))
8555 {
8556 /* If it is a RC or SAE immediate, do nothing. */
8557 ;
8558 }
24eab124
AM		 8559 else if (is_digit_char (*op_string)
8560 || is_identifier_char (*op_string)
e5cb08ac 8561 || *op_string == '(')
24eab124 8562 {
47926f60 8563 /* This is a memory reference of some sort. */
af6bdddf 8564 char *base_string;
252b5132 8565
47926f60 8566 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 8567 char *displacement_string_start;
8568 char *displacement_string_end;
43234a1e 8569 char *vop_start;
252b5132 8570
24eab124 8571 do_memory_reference:
24eab124 8572 if ((i.mem_operands == 1
40fb9820 8573 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 8574 || i.mem_operands == 2)
8575 {
8576 as_bad (_("too many memory references for `%s'"),
8577 current_templates->start->name);
8578 return 0;
8579 }
252b5132 8580
24eab124
AM		 8581 /* Check for base index form. We detect the base index form by
8582 looking for an ')' at the end of the operand, searching
8583 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8584 after the '('. */
af6bdddf 8585 base_string = op_string + strlen (op_string);
c3332e24 8586
43234a1e
L		 8587 /* Handle vector operations. */
8588 vop_start = strchr (op_string, '{');
8589 if (vop_start && vop_start < base_string)
8590 {
8591 if (check_VecOperations (vop_start, base_string) == NULL)
8592 return 0;
8593 base_string = vop_start;
8594 }
8595
af6bdddf
AM		 8596 --base_string;
8597 if (is_space_char (*base_string))
8598 --base_string;
252b5132 8599
47926f60 8600 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 8601 displacement_string_start = op_string;
8602 displacement_string_end = base_string + 1;
252b5132 8603
24eab124
AM		 8604 if (*base_string == ')')
8605 {
af6bdddf 8606 char *temp_string;
24eab124
AM		 8607 unsigned int parens_balanced = 1;
8608 /* We've already checked that the number of left & right ()'s are
47926f60 8609 equal, so this loop will not be infinite. */
24eab124
AM		 8610 do
8611 {
8612 base_string--;
8613 if (*base_string == ')')
8614 parens_balanced++;
8615 if (*base_string == '(')
8616 parens_balanced--;
8617 }
8618 while (parens_balanced);
c3332e24 8619
af6bdddf 8620 temp_string = base_string;
c3332e24 8621
24eab124 8622 /* Skip past '(' and whitespace. */
252b5132
RH		 8623 ++base_string;
8624 if (is_space_char (*base_string))
24eab124 8625 ++base_string;
252b5132 8626
af6bdddf 8627 if (*base_string == ','
4eed87de
AM		 8628 || ((i.base_reg = parse_register (base_string, &end_op))
8629 != NULL))
252b5132 8630 {
af6bdddf 8631 displacement_string_end = temp_string;
252b5132 8632
40fb9820 8633 i.types[this_operand].bitfield.baseindex = 1;
252b5132 8634
af6bdddf 8635 if (i.base_reg)
24eab124 8636 {
24eab124
AM		 8637 base_string = end_op;
8638 if (is_space_char (*base_string))
8639 ++base_string;
af6bdddf
AM		 8640 }
8641
8642 /* There may be an index reg or scale factor here. */
8643 if (*base_string == ',')
8644 {
8645 ++base_string;
8646 if (is_space_char (*base_string))
8647 ++base_string;
8648
4eed87de
AM		 8649 if ((i.index_reg = parse_register (base_string, &end_op))
8650 != NULL)
24eab124 8651 {
af6bdddf 8652 base_string = end_op;
24eab124
AM		 8653 if (is_space_char (*base_string))
8654 ++base_string;
af6bdddf
AM		 8655 if (*base_string == ',')
8656 {
8657 ++base_string;
8658 if (is_space_char (*base_string))
8659 ++base_string;
8660 }
e5cb08ac 8661 else if (*base_string != ')')
af6bdddf 8662 {
4eed87de
AM		 8663 as_bad (_("expecting `,' or `)' "
8664 "after index register in `%s'"),
af6bdddf
AM		 8665 operand_string);
8666 return 0;
8667 }
24eab124 8668 }
af6bdddf 8669 else if (*base_string == REGISTER_PREFIX)
24eab124 8670 {
f76bf5e0
L		 8671 end_op = strchr (base_string, ',');
8672 if (end_op)
8673 *end_op = '\0';
af6bdddf 8674 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 8675 return 0;
8676 }
252b5132 8677
47926f60 8678 /* Check for scale factor. */
551c1ca1 8679 if (*base_string != ')')
af6bdddf 8680 {
551c1ca1
AM		 8681 char *end_scale = i386_scale (base_string);
8682
8683 if (!end_scale)
af6bdddf 8684 return 0;
24eab124 8685
551c1ca1 8686 base_string = end_scale;
af6bdddf
AM		 8687 if (is_space_char (*base_string))
8688 ++base_string;
8689 if (*base_string != ')')
8690 {
4eed87de
AM		 8691 as_bad (_("expecting `)' "
8692 "after scale factor in `%s'"),
af6bdddf
AM		 8693 operand_string);
8694 return 0;
8695 }
8696 }
8697 else if (!i.index_reg)
24eab124 8698 {
4eed87de
AM		 8699 as_bad (_("expecting index register or scale factor "
8700 "after `,'; got '%c'"),
af6bdddf 8701 *base_string);
24eab124
AM		 8702 return 0;
8703 }
8704 }
af6bdddf 8705 else if (*base_string != ')')
24eab124 8706 {
4eed87de
AM		 8707 as_bad (_("expecting `,' or `)' "
8708 "after base register in `%s'"),
af6bdddf 8709 operand_string);
24eab124
AM		 8710 return 0;
8711 }
c3332e24 8712 }
af6bdddf 8713 else if (*base_string == REGISTER_PREFIX)
c3332e24 8714 {
f76bf5e0
L		 8715 end_op = strchr (base_string, ',');
8716 if (end_op)
8717 *end_op = '\0';
af6bdddf 8718 as_bad (_("bad register name `%s'"), base_string);
24eab124 8719 return 0;
c3332e24 8720 }
24eab124
AM		 8721 }
8722
8723 /* If there's an expression beginning the operand, parse it,
8724 assuming displacement_string_start and
8725 displacement_string_end are meaningful. */
8726 if (displacement_string_start != displacement_string_end)
8727 {
8728 if (!i386_displacement (displacement_string_start,
8729 displacement_string_end))
8730 return 0;
8731 }
8732
8733 /* Special case for (%dx) while doing input/output op. */
8734 if (i.base_reg
0dfbf9d7
L		 8735 && operand_type_equal (&i.base_reg->reg_type,
8736 &reg16_inoutportreg)
24eab124
AM		 8737 && i.index_reg == 0
8738 && i.log2_scale_factor == 0
8739 && i.seg[i.mem_operands] == 0
40fb9820 8740 && !operand_type_check (i.types[this_operand], disp))
24eab124 8741 {
65da13b5 8742 i.types[this_operand] = inoutportreg;
24eab124
AM		 8743 return 1;
8744 }
8745
eecb386c
AM		 8746 if (i386_index_check (operand_string) == 0)
8747 return 0;
5c07affc 8748 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 8749 i.mem_operands++;
8750 }
8751 else
ce8a8b2f
AM		 8752 {
8753 /* It's not a memory operand; argh! */
24eab124
AM		 8754 as_bad (_("invalid char %s beginning operand %d `%s'"),
8755 output_invalid (*op_string),
8756 this_operand + 1,
8757 op_string);
8758 return 0;
8759 }
47926f60 8760 return 1; /* Normal return. */
252b5132
RH		 8761}
8762\f
fa94de6b
RM		 8763/* Calculate the maximum variable size (i.e., excluding fr_fix)
8764 that an rs_machine_dependent frag may reach. */
8765
8766unsigned int
8767i386_frag_max_var (fragS *frag)
8768{
8769 /* The only relaxable frags are for jumps.
8770 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8771 gas_assert (frag->fr_type == rs_machine_dependent);
8772 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8773}
8774
ee7fcc42
AM		 8775/* md_estimate_size_before_relax()
8776
8777 Called just before relax() for rs_machine_dependent frags. The x86
8778 assembler uses these frags to handle variable size jump
8779 instructions.
8780
8781 Any symbol that is now undefined will not become defined.
8782 Return the correct fr_subtype in the frag.
8783 Return the initial "guess for variable size of frag" to caller.
8784 The guess is actually the growth beyond the fixed part. Whatever
8785 we do to grow the fixed or variable part contributes to our
8786 returned value. */
8787
252b5132 8788int
7016a5d5 8789md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 8790{
252b5132 8791 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 8792 check for un-relaxable symbols. On an ELF system, we can't relax
8793 an externally visible symbol, because it may be overridden by a
8794 shared library. */
8795 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 8796#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 8797 || (IS_ELF
31312f95 8798 && (S_IS_EXTERNAL (fragP->fr_symbol)
915bcca5
L		 8799 || S_IS_WEAK (fragP->fr_symbol)
8800 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8801 & BSF_GNU_INDIRECT_FUNCTION))))
fbeb56a4
DK		 8802#endif
8803#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 8804 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 8805 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 8806#endif
8807 )
252b5132 8808 {
b98ef147
AM		 8809 /* Symbol is undefined in this segment, or we need to keep a
8810 reloc so that weak symbols can be overridden. */
8811 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 8812 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 8813 unsigned char *opcode;
8814 int old_fr_fix;
f6af82bd 8815
ee7fcc42 8816 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 8817 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 8818 else if (size == 2)
f6af82bd
AM		 8819 reloc_type = BFD_RELOC_16_PCREL;
8820 else
8821 reloc_type = BFD_RELOC_32_PCREL;
252b5132 8822
ee7fcc42
AM		 8823 old_fr_fix = fragP->fr_fix;
8824 opcode = (unsigned char *) fragP->fr_opcode;
8825
fddf5b5b 8826 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 8827 {
fddf5b5b
AM		 8828 case UNCOND_JUMP:
8829 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 8830 opcode[0] = 0xe9;
252b5132 8831 fragP->fr_fix += size;
062cd5e7
AS		 8832 fix_new (fragP, old_fr_fix, size,
8833 fragP->fr_symbol,
8834 fragP->fr_offset, 1,
8835 reloc_type);
252b5132
RH		 8836 break;
8837
fddf5b5b 8838 case COND_JUMP86:
412167cb
AM		 8839 if (size == 2
8840 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 8841 {
8842 /* Negate the condition, and branch past an
8843 unconditional jump. */
8844 opcode[0] ^= 1;
8845 opcode[1] = 3;
8846 /* Insert an unconditional jump. */
8847 opcode[2] = 0xe9;
8848 /* We added two extra opcode bytes, and have a two byte
8849 offset. */
8850 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 8851 fix_new (fragP, old_fr_fix + 2, 2,
8852 fragP->fr_symbol,
8853 fragP->fr_offset, 1,
8854 reloc_type);
fddf5b5b
AM		 8855 break;
8856 }
8857 /* Fall through. */
8858
8859 case COND_JUMP:
412167cb
AM		 8860 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8861 {
3e02c1cc
AM		 8862 fixS *fixP;
8863
412167cb 8864 fragP->fr_fix += 1;
3e02c1cc
AM		 8865 fixP = fix_new (fragP, old_fr_fix, 1,
8866 fragP->fr_symbol,
8867 fragP->fr_offset, 1,
8868 BFD_RELOC_8_PCREL);
8869 fixP->fx_signed = 1;
412167cb
AM		 8870 break;
8871 }
93c2a809 8872
24eab124 8873 /* This changes the byte-displacement jump 0x7N
fddf5b5b 8874 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 8875 opcode[1] = opcode[0] + 0x10;
f6af82bd 8876 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 8877 /* We've added an opcode byte. */
8878 fragP->fr_fix += 1 + size;
062cd5e7
AS		 8879 fix_new (fragP, old_fr_fix + 1, size,
8880 fragP->fr_symbol,
8881 fragP->fr_offset, 1,
8882 reloc_type);
252b5132 8883 break;
fddf5b5b
AM		 8884
8885 default:
8886 BAD_CASE (fragP->fr_subtype);
8887 break;
252b5132
RH		 8888 }
8889 frag_wane (fragP);
ee7fcc42 8890 return fragP->fr_fix - old_fr_fix;
252b5132 8891 }
93c2a809 8892
93c2a809
AM		 8893 /* Guess size depending on current relax state. Initially the relax
8894 state will correspond to a short jump and we return 1, because
8895 the variable part of the frag (the branch offset) is one byte
8896 long. However, we can relax a section more than once and in that
8897 case we must either set fr_subtype back to the unrelaxed state,
8898 or return the value for the appropriate branch. */
8899 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 8900}
8901
47926f60
KH		 8902/* Called after relax() is finished.
8903
8904 In: Address of frag.
8905 fr_type == rs_machine_dependent.
8906 fr_subtype is what the address relaxed to.
8907
8908 Out: Any fixSs and constants are set up.
8909 Caller will turn frag into a ".space 0". */
8910
252b5132 8911void
7016a5d5
TG		 8912md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8913 fragS *fragP)
252b5132 8914{
29b0f896 8915 unsigned char *opcode;
252b5132 8916 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 8917 offsetT target_address;
8918 offsetT opcode_address;
252b5132 8919 unsigned int extension = 0;
847f7ad4 8920 offsetT displacement_from_opcode_start;
252b5132
RH		 8921
8922 opcode = (unsigned char *) fragP->fr_opcode;
8923
47926f60 8924 /* Address we want to reach in file space. */
252b5132 8925 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 8926
47926f60 8927 /* Address opcode resides at in file space. */
252b5132
RH		 8928 opcode_address = fragP->fr_address + fragP->fr_fix;
8929
47926f60 8930 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 8931 displacement_from_opcode_start = target_address - opcode_address;
8932
fddf5b5b 8933 if ((fragP->fr_subtype & BIG) == 0)
252b5132 8934 {
47926f60
KH		 8935 /* Don't have to change opcode. */
8936 extension = 1; /* 1 opcode + 1 displacement */
252b5132 8937 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 8938 }
8939 else
8940 {
8941 if (no_cond_jump_promotion
8942 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 8943 as_warn_where (fragP->fr_file, fragP->fr_line,
8944 _("long jump required"));
252b5132 8945
fddf5b5b
AM		 8946 switch (fragP->fr_subtype)
8947 {
8948 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8949 extension = 4; /* 1 opcode + 4 displacement */
8950 opcode[0] = 0xe9;
8951 where_to_put_displacement = &opcode[1];
8952 break;
252b5132 8953
fddf5b5b
AM		 8954 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8955 extension = 2; /* 1 opcode + 2 displacement */
8956 opcode[0] = 0xe9;
8957 where_to_put_displacement = &opcode[1];
8958 break;
252b5132 8959
fddf5b5b
AM		 8960 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8961 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8962 extension = 5; /* 2 opcode + 4 displacement */
8963 opcode[1] = opcode[0] + 0x10;
8964 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8965 where_to_put_displacement = &opcode[2];
8966 break;
252b5132 8967
fddf5b5b
AM		 8968 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8969 extension = 3; /* 2 opcode + 2 displacement */
8970 opcode[1] = opcode[0] + 0x10;
8971 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8972 where_to_put_displacement = &opcode[2];
8973 break;
252b5132 8974
fddf5b5b
AM		 8975 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
8976 extension = 4;
8977 opcode[0] ^= 1;
8978 opcode[1] = 3;
8979 opcode[2] = 0xe9;
8980 where_to_put_displacement = &opcode[3];
8981 break;
8982
8983 default:
8984 BAD_CASE (fragP->fr_subtype);
8985 break;
8986 }
252b5132 8987 }
fddf5b5b 8988
7b81dfbb
AJ		 8989 /* If size if less then four we are sure that the operand fits,
8990 but if it's 4, then it could be that the displacement is larger
8991 then -/+ 2GB. */
8992 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
8993 && object_64bit
8994 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 8995 + ((addressT) 1 << 31))
8996 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 8997 {
8998 as_bad_where (fragP->fr_file, fragP->fr_line,
8999 _("jump target out of range"));
9000 /* Make us emit 0. */
9001 displacement_from_opcode_start = extension;
9002 }
47926f60 9003 /* Now put displacement after opcode. */
252b5132
RH		 9004 md_number_to_chars ((char *) where_to_put_displacement,
9005 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9006 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9007 fragP->fr_fix += extension;
9008}
9009\f
7016a5d5 9010/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9011 by our caller that we have all the info we need to fix it up.
9012
7016a5d5
TG		 9013 Parameter valP is the pointer to the value of the bits.
9014
252b5132
RH		 9015 On the 386, immediates, displacements, and data pointers are all in
9016 the same (little-endian) format, so we don't need to care about which
9017 we are handling. */
9018
94f592af 9019void
7016a5d5 9020md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9021{
94f592af 9022 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9023 valueT value = *valP;
252b5132 9024
f86103b7 9025#if !defined (TE_Mach)
93382f6d
AM		 9026 if (fixP->fx_pcrel)
9027 {
9028 switch (fixP->fx_r_type)
9029 {
5865bb77
ILT		 9030 default:
9031 break;
9032
d6ab8113
JB		 9033 case BFD_RELOC_64:
9034 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9035 break;
93382f6d 9036 case BFD_RELOC_32:
ae8887b5 9037 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9038 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9039 break;
9040 case BFD_RELOC_16:
9041 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9042 break;
9043 case BFD_RELOC_8:
9044 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9045 break;
9046 }
9047 }
252b5132 9048
a161fe53 9049 if (fixP->fx_addsy != NULL
31312f95 9050 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9051 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9052 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9053 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9054 && !use_rela_relocations)
252b5132 9055 {
31312f95
AM		 9056 /* This is a hack. There should be a better way to handle this.
9057 This covers for the fact that bfd_install_relocation will
9058 subtract the current location (for partial_inplace, PC relative
9059 relocations); see more below. */
252b5132 9060#ifndef OBJ_AOUT
718ddfc0 9061 if (IS_ELF
252b5132
RH		 9062#ifdef TE_PE
9063 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9064#endif
9065 )
9066 value += fixP->fx_where + fixP->fx_frag->fr_address;
9067#endif
9068#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9069 if (IS_ELF)
252b5132 9070 {
6539b54b 9071 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9072
6539b54b 9073 if ((sym_seg == seg
2f66722d 9074 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9075 && sym_seg != absolute_section))
af65af87 9076 && !generic_force_reloc (fixP))
2f66722d
AM		 9077 {
9078 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9079 bfd_install_relocation subtracts them out again. I think
9080 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9081 it. FIXME. */
9082 value += fixP->fx_where + fixP->fx_frag->fr_address;
9083 }
252b5132
RH		 9084 }
9085#endif
9086#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9087 /* For some reason, the PE format does not store a
9088 section address offset for a PC relative symbol. */
9089 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9090 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9091 value += md_pcrel_from (fixP);
9092#endif
9093 }
fbeb56a4 9094#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9095 if (fixP->fx_addsy != NULL
9096 && S_IS_WEAK (fixP->fx_addsy)
9097 /* PR 16858: Do not modify weak function references. */
9098 && ! fixP->fx_pcrel)
fbeb56a4 9099 {
296a8689
NC		 9100#if !defined (TE_PEP)
9101 /* For x86 PE weak function symbols are neither PC-relative
9102 nor do they set S_IS_FUNCTION. So the only reliable way
9103 to detect them is to check the flags of their containing
9104 section. */
9105 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9106 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9107 ;
9108 else
9109#endif
fbeb56a4
DK		 9110 value -= S_GET_VALUE (fixP->fx_addsy);
9111 }
9112#endif
252b5132
RH		 9113
9114 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9115 and we must not disappoint it. */
252b5132 9116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9117 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9118 switch (fixP->fx_r_type)
9119 {
9120 case BFD_RELOC_386_PLT32:
3e73aa7c 9121 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9122 /* Make the jump instruction point to the address of the operand. At
9123 runtime we merely add the offset to the actual PLT entry. */
9124 value = -4;
9125 break;
31312f95 9126
13ae64f3
JJ		 9127 case BFD_RELOC_386_TLS_GD:
9128 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9129 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9130 case BFD_RELOC_386_TLS_IE:
9131 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9132 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9133 case BFD_RELOC_X86_64_TLSGD:
9134 case BFD_RELOC_X86_64_TLSLD:
9135 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9136 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9137 value = 0; /* Fully resolved at runtime. No addend. */
9138 /* Fallthrough */
9139 case BFD_RELOC_386_TLS_LE:
9140 case BFD_RELOC_386_TLS_LDO_32:
9141 case BFD_RELOC_386_TLS_LE_32:
9142 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9143 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9144 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9145 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9146 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9147 break;
9148
67a4f2b7
AO		 9149 case BFD_RELOC_386_TLS_DESC_CALL:
9150 case BFD_RELOC_X86_64_TLSDESC_CALL:
9151 value = 0; /* Fully resolved at runtime. No addend. */
9152 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9153 fixP->fx_done = 0;
9154 return;
9155
00f7efb6
JJ		 9156 case BFD_RELOC_386_GOT32:
9157 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 9158 value = 0; /* Fully resolved at runtime. No addend. */
9159 break;
47926f60
KH		 9160
9161 case BFD_RELOC_VTABLE_INHERIT:
9162 case BFD_RELOC_VTABLE_ENTRY:
9163 fixP->fx_done = 0;
94f592af 9164 return;
47926f60
KH		 9165
9166 default:
9167 break;
9168 }
9169#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9170 *valP = value;
f86103b7 9171#endif /* !defined (TE_Mach) */
3e73aa7c 9172
3e73aa7c 9173 /* Are we finished with this relocation now? */
c6682705 9174 if (fixP->fx_addsy == NULL)
3e73aa7c 9175 fixP->fx_done = 1;
fbeb56a4
DK		 9176#if defined (OBJ_COFF) && defined (TE_PE)
9177 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9178 {
9179 fixP->fx_done = 0;
9180 /* Remember value for tc_gen_reloc. */
9181 fixP->fx_addnumber = value;
9182 /* Clear out the frag for now. */
9183 value = 0;
9184 }
9185#endif
3e73aa7c
JH		 9186 else if (use_rela_relocations)
9187 {
9188 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9189 /* Remember value for tc_gen_reloc. */
9190 fixP->fx_addnumber = value;
3e73aa7c
JH		 9191 value = 0;
9192 }
f86103b7 9193
94f592af 9194 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9195}
252b5132 9196\f
252b5132 9197char *
499ac353 9198md_atof (int type, char *litP, int *sizeP)
252b5132 9199{
499ac353
NC		 9200 /* This outputs the LITTLENUMs in REVERSE order;
9201 in accord with the bigendian 386. */
9202 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9203}
9204\f
2d545b82 9205static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9206
252b5132 9207static char *
e3bb37b5 9208output_invalid (int c)
252b5132 9209{
3882b010 9210 if (ISPRINT (c))
f9f21a03
L		 9211 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9212 "'%c'", c);
252b5132 9213 else
f9f21a03 9214 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9215 "(0x%x)", (unsigned char) c);
252b5132
RH		 9216 return output_invalid_buf;
9217}
9218
af6bdddf 9219/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9220
9221static const reg_entry *
4d1bb795 9222parse_real_register (char *reg_string, char **end_op)
252b5132 9223{
af6bdddf
AM		 9224 char *s = reg_string;
9225 char *p;
252b5132
RH		 9226 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9227 const reg_entry *r;
9228
9229 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9230 if (*s == REGISTER_PREFIX)
9231 ++s;
9232
9233 if (is_space_char (*s))
9234 ++s;
9235
9236 p = reg_name_given;
af6bdddf 9237 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9238 {
9239 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9240 return (const reg_entry *) NULL;
9241 s++;
252b5132
RH		 9242 }
9243
6588847e
DN		 9244 /* For naked regs, make sure that we are not dealing with an identifier.
9245 This prevents confusing an identifier like `eax_var' with register
9246 `eax'. */
9247 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9248 return (const reg_entry *) NULL;
9249
af6bdddf 9250 *end_op = s;
252b5132
RH		 9251
9252 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9253
5f47d35b 9254 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9255 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9256 {
5f47d35b
AM		 9257 if (is_space_char (*s))
9258 ++s;
9259 if (*s == '(')
9260 {
af6bdddf 9261 ++s;
5f47d35b
AM		 9262 if (is_space_char (*s))
9263 ++s;
9264 if (*s >= '0' && *s <= '7')
9265 {
db557034 9266 int fpr = *s - '0';
af6bdddf 9267 ++s;
5f47d35b
AM		 9268 if (is_space_char (*s))
9269 ++s;
9270 if (*s == ')')
9271 {
9272 *end_op = s + 1;
1e9cc1c2 9273 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9274 know (r);
9275 return r + fpr;
5f47d35b 9276 }
5f47d35b 9277 }
47926f60 9278 /* We have "%st(" then garbage. */
5f47d35b
AM		 9279 return (const reg_entry *) NULL;
9280 }
9281 }
9282
a60de03c
JB		 9283 if (r == NULL || allow_pseudo_reg)
9284 return r;
9285
0dfbf9d7 9286 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9287 return (const reg_entry *) NULL;
9288
192dc9c6
JB		 9289 if ((r->reg_type.bitfield.reg32
9290 || r->reg_type.bitfield.sreg3
9291 || r->reg_type.bitfield.control
9292 || r->reg_type.bitfield.debug
9293 || r->reg_type.bitfield.test)
9294 && !cpu_arch_flags.bitfield.cpui386)
9295 return (const reg_entry *) NULL;
9296
309d3373
JB		 9297 if (r->reg_type.bitfield.floatreg
9298 && !cpu_arch_flags.bitfield.cpu8087
9299 && !cpu_arch_flags.bitfield.cpu287
9300 && !cpu_arch_flags.bitfield.cpu387)
9301 return (const reg_entry *) NULL;
9302
192dc9c6
JB		 9303 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9304 return (const reg_entry *) NULL;
9305
9306 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9307 return (const reg_entry *) NULL;
9308
40f12533
L		 9309 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9310 return (const reg_entry *) NULL;
9311
43234a1e
L		 9312 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9313 && !cpu_arch_flags.bitfield.cpuavx512f)
9314 return (const reg_entry *) NULL;
9315
db51cc60 9316 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9317 if (!allow_index_reg
db51cc60
L		 9318 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9319 return (const reg_entry *) NULL;
9320
43234a1e
L		 9321 /* Upper 16 vector register is only available with VREX in 64bit
9322 mode. */
9323 if ((r->reg_flags & RegVRex))
9324 {
9325 if (!cpu_arch_flags.bitfield.cpuvrex
9326 || flag_code != CODE_64BIT)
9327 return (const reg_entry *) NULL;
9328
9329 i.need_vrex = 1;
9330 }
9331
a60de03c
JB		 9332 if (((r->reg_flags & (RegRex64 | RegRex))
9333 || r->reg_type.bitfield.reg64)
40fb9820 9334 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9335 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9336 && flag_code != CODE_64BIT)
20f0a1fc 9337 return (const reg_entry *) NULL;
1ae00879 9338
b7240065
JB		 9339 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9340 return (const reg_entry *) NULL;
9341
252b5132
RH		 9342 return r;
9343}
4d1bb795
JB		 9344
9345/* REG_STRING starts *before* REGISTER_PREFIX. */
9346
9347static const reg_entry *
9348parse_register (char *reg_string, char **end_op)
9349{
9350 const reg_entry *r;
9351
9352 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9353 r = parse_real_register (reg_string, end_op);
9354 else
9355 r = NULL;
9356 if (!r)
9357 {
9358 char *save = input_line_pointer;
9359 char c;
9360 symbolS *symbolP;
9361
9362 input_line_pointer = reg_string;
9363 c = get_symbol_end ();
9364 symbolP = symbol_find (reg_string);
9365 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9366 {
9367 const expressionS *e = symbol_get_value_expression (symbolP);
9368
0398aac5 9369 know (e->X_op == O_register);
4eed87de 9370 know (e->X_add_number >= 0
c3fe08fa 9371 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9372 r = i386_regtab + e->X_add_number;
d3bb6b49
IT		 9373 if ((r->reg_flags & RegVRex))
9374 i.need_vrex = 1;
4d1bb795
JB		 9375 *end_op = input_line_pointer;
9376 }
9377 *input_line_pointer = c;
9378 input_line_pointer = save;
9379 }
9380 return r;
9381}
9382
9383int
9384i386_parse_name (char *name, expressionS *e, char *nextcharP)
9385{
9386 const reg_entry *r;
9387 char *end = input_line_pointer;
9388
9389 *end = *nextcharP;
9390 r = parse_register (name, &input_line_pointer);
9391 if (r && end <= input_line_pointer)
9392 {
9393 *nextcharP = *input_line_pointer;
9394 *input_line_pointer = 0;
9395 e->X_op = O_register;
9396 e->X_add_number = r - i386_regtab;
9397 return 1;
9398 }
9399 input_line_pointer = end;
9400 *end = 0;
ee86248c 9401 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9402}
9403
9404void
9405md_operand (expressionS *e)
9406{
ee86248c
JB		 9407 char *end;
9408 const reg_entry *r;
4d1bb795 9409
ee86248c
JB		 9410 switch (*input_line_pointer)
9411 {
9412 case REGISTER_PREFIX:
9413 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9414 if (r)
9415 {
9416 e->X_op = O_register;
9417 e->X_add_number = r - i386_regtab;
9418 input_line_pointer = end;
9419 }
ee86248c
JB		 9420 break;
9421
9422 case '[':
9c2799c2 9423 gas_assert (intel_syntax);
ee86248c
JB		 9424 end = input_line_pointer++;
9425 expression (e);
9426 if (*input_line_pointer == ']')
9427 {
9428 ++input_line_pointer;
9429 e->X_op_symbol = make_expr_symbol (e);
9430 e->X_add_symbol = NULL;
9431 e->X_add_number = 0;
9432 e->X_op = O_index;
9433 }
9434 else
9435 {
9436 e->X_op = O_absent;
9437 input_line_pointer = end;
9438 }
9439 break;
4d1bb795
JB		 9440 }
9441}
9442
252b5132 9443\f
4cc782b5 9444#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9445const char *md_shortopts = "kVQ:sqn";
252b5132 9446#else
12b55ccc 9447const char *md_shortopts = "qn";
252b5132 9448#endif
6e0b89ee 9449
3e73aa7c 9450#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9451#define OPTION_64 (OPTION_MD_BASE + 1)
9452#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9453#define OPTION_MARCH (OPTION_MD_BASE + 3)
9454#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9455#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9456#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9457#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9458#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9459#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9460#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9461#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9462#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9463#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9464#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9465#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9466#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9467#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9468#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
a5094208 9469#define OPTION_OMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9470#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
b3b91714 9471
99ad8390
NC		 9472struct option md_longopts[] =
9473{
3e73aa7c 9474 {"32", no_argument, NULL, OPTION_32},
321098a5 9475#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9476 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9477 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9478#endif
9479#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9480 {"x32", no_argument, NULL, OPTION_X32},
6e0b89ee 9481#endif
b3b91714 9482 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9483 {"march", required_argument, NULL, OPTION_MARCH},
9484 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9485 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9486 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9487 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9488 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9489 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9490 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9491 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9492 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9493 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9494 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9495 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9496 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9497# if defined (TE_PE) || defined (TE_PEP)
9498 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9499#endif
a5094208 9500 {"momit-lock-prefix", required_argument, NULL, OPTION_OMIT_LOCK_PREFIX},
d3d3c6db 9501 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
252b5132
RH		 9502 {NULL, no_argument, NULL, 0}
9503};
9504size_t md_longopts_size = sizeof (md_longopts);
9505
9506int
9103f4f4 9507md_parse_option (int c, char *arg)
252b5132 9508{
91d6fa6a 9509 unsigned int j;
6305a203 9510 char *arch, *next;
9103f4f4 9511
252b5132
RH		 9512 switch (c)
9513 {
12b55ccc
L		 9514 case 'n':
9515 optimize_align_code = 0;
9516 break;
9517
a38cf1db
AM		 9518 case 'q':
9519 quiet_warnings = 1;
252b5132
RH		 9520 break;
9521
9522#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 9523 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9524 should be emitted or not. FIXME: Not implemented. */
9525 case 'Q':
252b5132
RH		 9526 break;
9527
9528 /* -V: SVR4 argument to print version ID. */
9529 case 'V':
9530 print_version_id ();
9531 break;
9532
a38cf1db
AM		 9533 /* -k: Ignore for FreeBSD compatibility. */
9534 case 'k':
252b5132 9535 break;
4cc782b5
ILT		 9536
9537 case 's':
9538 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 9539 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 9540 break;
99ad8390 9541#endif
321098a5 9542#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9543 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 9544 case OPTION_64:
9545 {
9546 const char **list, **l;
9547
3e73aa7c
JH		 9548 list = bfd_target_list ();
9549 for (l = list; *l != NULL; l++)
8620418b 9550 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 9551 || strcmp (*l, "coff-x86-64") == 0
9552 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 9553 || strcmp (*l, "pei-x86-64") == 0
9554 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 9555 {
9556 default_arch = "x86_64";
9557 break;
9558 }
3e73aa7c 9559 if (*l == NULL)
2b5d6a91 9560 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 9561 free (list);
9562 }
9563 break;
9564#endif
252b5132 9565
351f65ca 9566#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9567 case OPTION_X32:
351f65ca
L		 9568 if (IS_ELF)
9569 {
9570 const char **list, **l;
9571
9572 list = bfd_target_list ();
9573 for (l = list; *l != NULL; l++)
9574 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9575 {
9576 default_arch = "x86_64:32";
9577 break;
9578 }
9579 if (*l == NULL)
2b5d6a91 9580 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 9581 free (list);
9582 }
9583 else
9584 as_fatal (_("32bit x86_64 is only supported for ELF"));
9585 break;
9586#endif
9587
6e0b89ee
AM		 9588 case OPTION_32:
9589 default_arch = "i386";
9590 break;
9591
b3b91714
AM		 9592 case OPTION_DIVIDE:
9593#ifdef SVR4_COMMENT_CHARS
9594 {
9595 char *n, *t;
9596 const char *s;
9597
9598 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9599 t = n;
9600 for (s = i386_comment_chars; *s != '\0'; s++)
9601 if (*s != '/')
9602 *t++ = *s;
9603 *t = '\0';
9604 i386_comment_chars = n;
9605 }
9606#endif
9607 break;
9608
9103f4f4 9609 case OPTION_MARCH:
6305a203
L		 9610 arch = xstrdup (arg);
9611 do
9103f4f4 9612 {
6305a203 9613 if (*arch == '.')
2b5d6a91 9614 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9615 next = strchr (arch, '+');
9616 if (next)
9617 *next++ = '\0';
91d6fa6a 9618 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9619 {
91d6fa6a 9620 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 9621 {
6305a203 9622 /* Processor. */
1ded5609
JB		 9623 if (! cpu_arch[j].flags.bitfield.cpui386)
9624 continue;
9625
91d6fa6a 9626 cpu_arch_name = cpu_arch[j].name;
6305a203 9627 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 9628 cpu_arch_flags = cpu_arch[j].flags;
9629 cpu_arch_isa = cpu_arch[j].type;
9630 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 9631 if (!cpu_arch_tune_set)
9632 {
9633 cpu_arch_tune = cpu_arch_isa;
9634 cpu_arch_tune_flags = cpu_arch_isa_flags;
9635 }
9636 break;
9637 }
91d6fa6a
NC		 9638 else if (*cpu_arch [j].name == '.'
9639 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203
L		 9640 {
9641 /* ISA entension. */
9642 i386_cpu_flags flags;
309d3373 9643
49021df2 9644 if (!cpu_arch[j].negated)
309d3373 9645 flags = cpu_flags_or (cpu_arch_flags,
91d6fa6a 9646 cpu_arch[j].flags);
309d3373
JB		 9647 else
9648 flags = cpu_flags_and_not (cpu_arch_flags,
49021df2 9649 cpu_arch[j].flags);
0dfbf9d7 9650 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 9651 {
9652 if (cpu_sub_arch_name)
9653 {
9654 char *name = cpu_sub_arch_name;
9655 cpu_sub_arch_name = concat (name,
91d6fa6a 9656 cpu_arch[j].name,
1bf57e9f 9657 (const char *) NULL);
6305a203
L		 9658 free (name);
9659 }
9660 else
91d6fa6a 9661 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 9662 cpu_arch_flags = flags;
a586129e 9663 cpu_arch_isa_flags = flags;
6305a203
L		 9664 }
9665 break;
ccc9c027 9666 }
9103f4f4 9667 }
6305a203 9668
91d6fa6a 9669 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9670 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 9671
9672 arch = next;
9103f4f4 9673 }
6305a203 9674 while (next != NULL );
9103f4f4
L		 9675 break;
9676
9677 case OPTION_MTUNE:
9678 if (*arg == '.')
2b5d6a91 9679 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 9680 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 9681 {
91d6fa6a 9682 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 9683 {
ccc9c027 9684 cpu_arch_tune_set = 1;
91d6fa6a
NC		 9685 cpu_arch_tune = cpu_arch [j].type;
9686 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 9687 break;
9688 }
9689 }
91d6fa6a 9690 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 9691 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 9692 break;
9693
1efbbeb4
L		 9694 case OPTION_MMNEMONIC:
9695 if (strcasecmp (arg, "att") == 0)
9696 intel_mnemonic = 0;
9697 else if (strcasecmp (arg, "intel") == 0)
9698 intel_mnemonic = 1;
9699 else
2b5d6a91 9700 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 9701 break;
9702
9703 case OPTION_MSYNTAX:
9704 if (strcasecmp (arg, "att") == 0)
9705 intel_syntax = 0;
9706 else if (strcasecmp (arg, "intel") == 0)
9707 intel_syntax = 1;
9708 else
2b5d6a91 9709 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 9710 break;
9711
9712 case OPTION_MINDEX_REG:
9713 allow_index_reg = 1;
9714 break;
9715
9716 case OPTION_MNAKED_REG:
9717 allow_naked_reg = 1;
9718 break;
9719
9720 case OPTION_MOLD_GCC:
9721 old_gcc = 1;
1efbbeb4
L		 9722 break;
9723
c0f3af97
L		 9724 case OPTION_MSSE2AVX:
9725 sse2avx = 1;
9726 break;
9727
daf50ae7
L		 9728 case OPTION_MSSE_CHECK:
9729 if (strcasecmp (arg, "error") == 0)
7bab8ab5 9730 sse_check = check_error;
daf50ae7 9731 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 9732 sse_check = check_warning;
daf50ae7 9733 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 9734 sse_check = check_none;
daf50ae7 9735 else
2b5d6a91 9736 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 9737 break;
9738
7bab8ab5
JB		 9739 case OPTION_MOPERAND_CHECK:
9740 if (strcasecmp (arg, "error") == 0)
9741 operand_check = check_error;
9742 else if (strcasecmp (arg, "warning") == 0)
9743 operand_check = check_warning;
9744 else if (strcasecmp (arg, "none") == 0)
9745 operand_check = check_none;
9746 else
9747 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9748 break;
9749
539f890d
L		 9750 case OPTION_MAVXSCALAR:
9751 if (strcasecmp (arg, "128") == 0)
9752 avxscalar = vex128;
9753 else if (strcasecmp (arg, "256") == 0)
9754 avxscalar = vex256;
9755 else
2b5d6a91 9756 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 9757 break;
9758
7e8b059b
L		 9759 case OPTION_MADD_BND_PREFIX:
9760 add_bnd_prefix = 1;
9761 break;
9762
43234a1e
L		 9763 case OPTION_MEVEXLIG:
9764 if (strcmp (arg, "128") == 0)
9765 evexlig = evexl128;
9766 else if (strcmp (arg, "256") == 0)
9767 evexlig = evexl256;
9768 else if (strcmp (arg, "512") == 0)
9769 evexlig = evexl512;
9770 else
9771 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9772 break;
9773
d3d3c6db
IT		 9774 case OPTION_MEVEXRCIG:
9775 if (strcmp (arg, "rne") == 0)
9776 evexrcig = rne;
9777 else if (strcmp (arg, "rd") == 0)
9778 evexrcig = rd;
9779 else if (strcmp (arg, "ru") == 0)
9780 evexrcig = ru;
9781 else if (strcmp (arg, "rz") == 0)
9782 evexrcig = rz;
9783 else
9784 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
9785 break;
9786
43234a1e
L		 9787 case OPTION_MEVEXWIG:
9788 if (strcmp (arg, "0") == 0)
9789 evexwig = evexw0;
9790 else if (strcmp (arg, "1") == 0)
9791 evexwig = evexw1;
9792 else
9793 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9794 break;
9795
167ad85b
TG		 9796# if defined (TE_PE) || defined (TE_PEP)
9797 case OPTION_MBIG_OBJ:
9798 use_big_obj = 1;
9799 break;
9800#endif
9801
a5094208 9802 case OPTION_OMIT_LOCK_PREFIX:
d022bddd
IT		 9803 if (strcasecmp (arg, "yes") == 0)
9804 omit_lock_prefix = 1;
9805 else if (strcasecmp (arg, "no") == 0)
9806 omit_lock_prefix = 0;
9807 else
9808 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
9809 break;
9810
252b5132
RH		 9811 default:
9812 return 0;
9813 }
9814 return 1;
9815}
9816
8a2c8fef
L		 9817#define MESSAGE_TEMPLATE \
9818" "
9819
9820static void
1ded5609 9821show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 9822{
9823 static char message[] = MESSAGE_TEMPLATE;
9824 char *start = message + 27;
9825 char *p;
9826 int size = sizeof (MESSAGE_TEMPLATE);
9827 int left;
9828 const char *name;
9829 int len;
9830 unsigned int j;
9831
9832 p = start;
9833 left = size - (start - message);
9834 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9835 {
9836 /* Should it be skipped? */
9837 if (cpu_arch [j].skip)
9838 continue;
9839
9840 name = cpu_arch [j].name;
9841 len = cpu_arch [j].len;
9842 if (*name == '.')
9843 {
9844 /* It is an extension. Skip if we aren't asked to show it. */
9845 if (ext)
9846 {
9847 name++;
9848 len--;
9849 }
9850 else
9851 continue;
9852 }
9853 else if (ext)
9854 {
9855 /* It is an processor. Skip if we show only extension. */
9856 continue;
9857 }
1ded5609
JB		 9858 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9859 {
9860 /* It is an impossible processor - skip. */
9861 continue;
9862 }
8a2c8fef
L		 9863
9864 /* Reserve 2 spaces for ", " or ",\0" */
9865 left -= len + 2;
9866
9867 /* Check if there is any room. */
9868 if (left >= 0)
9869 {
9870 if (p != start)
9871 {
9872 *p++ = ',';
9873 *p++ = ' ';
9874 }
9875 p = mempcpy (p, name, len);
9876 }
9877 else
9878 {
9879 /* Output the current message now and start a new one. */
9880 *p++ = ',';
9881 *p = '\0';
9882 fprintf (stream, "%s\n", message);
9883 p = start;
9884 left = size - (start - message) - len - 2;
8d63c93e 9885
8a2c8fef
L		 9886 gas_assert (left >= 0);
9887
9888 p = mempcpy (p, name, len);
9889 }
9890 }
9891
9892 *p = '\0';
9893 fprintf (stream, "%s\n", message);
9894}
9895
252b5132 9896void
8a2c8fef 9897md_show_usage (FILE *stream)
252b5132 9898{
4cc782b5
ILT		 9899#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9900 fprintf (stream, _("\
a38cf1db
AM		 9901 -Q ignored\n\
9902 -V print assembler version number\n\
b3b91714
AM		 9903 -k ignored\n"));
9904#endif
9905 fprintf (stream, _("\
12b55ccc 9906 -n Do not optimize code alignment\n\
b3b91714
AM		 9907 -q quieten some warnings\n"));
9908#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9909 fprintf (stream, _("\
a38cf1db 9910 -s ignored\n"));
b3b91714 9911#endif
321098a5
L		 9912#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9913 || defined (TE_PE) || defined (TE_PEP))
751d281c 9914 fprintf (stream, _("\
570561f7 9915 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 9916#endif
b3b91714
AM		 9917#ifdef SVR4_COMMENT_CHARS
9918 fprintf (stream, _("\
9919 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 9920#else
9921 fprintf (stream, _("\
b3b91714 9922 --divide ignored\n"));
4cc782b5 9923#endif
9103f4f4 9924 fprintf (stream, _("\
6305a203 9925 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 9926 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 9927 show_arch (stream, 0, 1);
8a2c8fef
L		 9928 fprintf (stream, _("\
9929 EXTENSION is combination of:\n"));
1ded5609 9930 show_arch (stream, 1, 0);
6305a203 9931 fprintf (stream, _("\
8a2c8fef 9932 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 9933 show_arch (stream, 0, 0);
ba104c83 9934 fprintf (stream, _("\
c0f3af97
L		 9935 -msse2avx encode SSE instructions with VEX prefix\n"));
9936 fprintf (stream, _("\
daf50ae7
L		 9937 -msse-check=[none|error|warning]\n\
9938 check SSE instructions\n"));
9939 fprintf (stream, _("\
7bab8ab5
JB		 9940 -moperand-check=[none|error|warning]\n\
9941 check operand combinations for validity\n"));
9942 fprintf (stream, _("\
539f890d
L		 9943 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9944 length\n"));
9945 fprintf (stream, _("\
43234a1e
L		 9946 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9947 length\n"));
9948 fprintf (stream, _("\
9949 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9950 for EVEX.W bit ignored instructions\n"));
9951 fprintf (stream, _("\
d3d3c6db
IT		 9952 -mevexrcig=[rne|rd|ru|rz]\n\
9953 encode EVEX instructions with specific EVEX.RC value\n\
9954 for SAE-only ignored instructions\n"));
9955 fprintf (stream, _("\
ba104c83
L		 9956 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9957 fprintf (stream, _("\
9958 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9959 fprintf (stream, _("\
9960 -mindex-reg support pseudo index registers\n"));
9961 fprintf (stream, _("\
9962 -mnaked-reg don't require `%%' prefix for registers\n"));
9963 fprintf (stream, _("\
9964 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 9965 fprintf (stream, _("\
9966 -madd-bnd-prefix add BND prefix for all valid branches\n"));
167ad85b
TG		 9967# if defined (TE_PE) || defined (TE_PEP)
9968 fprintf (stream, _("\
9969 -mbig-obj generate big object files\n"));
9970#endif
d022bddd
IT		 9971 fprintf (stream, _("\
9972 -momit-lock-prefix=[no|yes]\n\
9973 strip all lock prefixes\n"));
252b5132
RH		 9974}
9975
3e73aa7c 9976#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 9977 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 9978 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 9979
9980/* Pick the target format to use. */
9981
47926f60 9982const char *
e3bb37b5 9983i386_target_format (void)
252b5132 9984{
351f65ca
L		 9985 if (!strncmp (default_arch, "x86_64", 6))
9986 {
9987 update_code_flag (CODE_64BIT, 1);
9988 if (default_arch[6] == '\0')
7f56bc95 9989 x86_elf_abi = X86_64_ABI;
351f65ca 9990 else
7f56bc95 9991 x86_elf_abi = X86_64_X32_ABI;
351f65ca 9992 }
3e73aa7c 9993 else if (!strcmp (default_arch, "i386"))
78f12dd3 9994 update_code_flag (CODE_32BIT, 1);
3e73aa7c 9995 else
2b5d6a91 9996 as_fatal (_("unknown architecture"));
89507696
JB		 9997
9998 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9999 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10000 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10001 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10002
252b5132
RH		 10003 switch (OUTPUT_FLAVOR)
10004 {
9384f2ff 10005#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10006 case bfd_target_aout_flavour:
47926f60 10007 return AOUT_TARGET_FORMAT;
4c63da97 10008#endif
9384f2ff
AM		 10009#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10010# if defined (TE_PE) || defined (TE_PEP)
10011 case bfd_target_coff_flavour:
167ad85b
TG		 10012 if (flag_code == CODE_64BIT)
10013 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10014 else
10015 return "pe-i386";
9384f2ff 10016# elif defined (TE_GO32)
0561d57c
JK		 10017 case bfd_target_coff_flavour:
10018 return "coff-go32";
9384f2ff 10019# else
252b5132
RH		 10020 case bfd_target_coff_flavour:
10021 return "coff-i386";
9384f2ff 10022# endif
4c63da97 10023#endif
3e73aa7c 10024#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10025 case bfd_target_elf_flavour:
3e73aa7c 10026 {
351f65ca
L		 10027 const char *format;
10028
10029 switch (x86_elf_abi)
4fa24527 10030 {
351f65ca
L		 10031 default:
10032 format = ELF_TARGET_FORMAT;
10033 break;
7f56bc95 10034 case X86_64_ABI:
351f65ca 10035 use_rela_relocations = 1;
4fa24527 10036 object_64bit = 1;
351f65ca
L		 10037 format = ELF_TARGET_FORMAT64;
10038 break;
7f56bc95 10039 case X86_64_X32_ABI:
4fa24527 10040 use_rela_relocations = 1;
351f65ca 10041 object_64bit = 1;
862be3fb 10042 disallow_64bit_reloc = 1;
351f65ca
L		 10043 format = ELF_TARGET_FORMAT32;
10044 break;
4fa24527 10045 }
3632d14b 10046 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10047 {
7f56bc95 10048 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10049 as_fatal (_("Intel L1OM is 64bit only"));
10050 return ELF_TARGET_L1OM_FORMAT;
10051 }
7a9068fe
L		 10052 if (cpu_arch_isa == PROCESSOR_K1OM)
10053 {
10054 if (x86_elf_abi != X86_64_ABI)
10055 as_fatal (_("Intel K1OM is 64bit only"));
10056 return ELF_TARGET_K1OM_FORMAT;
10057 }
8a9036a4 10058 else
351f65ca 10059 return format;
3e73aa7c 10060 }
e57f8c65
TG		 10061#endif
10062#if defined (OBJ_MACH_O)
10063 case bfd_target_mach_o_flavour:
d382c579
TG		 10064 if (flag_code == CODE_64BIT)
10065 {
10066 use_rela_relocations = 1;
10067 object_64bit = 1;
10068 return "mach-o-x86-64";
10069 }
10070 else
10071 return "mach-o-i386";
4c63da97 10072#endif
252b5132
RH		 10073 default:
10074 abort ();
10075 return NULL;
10076 }
10077}
10078
47926f60 10079#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 10080
10081#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 10082void
10083i386_elf_emit_arch_note (void)
a847613f 10084{
718ddfc0 10085 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 10086 {
10087 char *p;
10088 asection *seg = now_seg;
10089 subsegT subseg = now_subseg;
10090 Elf_Internal_Note i_note;
10091 Elf_External_Note e_note;
10092 asection *note_secp;
10093 int len;
10094
10095 /* Create the .note section. */
10096 note_secp = subseg_new (".note", 0);
10097 bfd_set_section_flags (stdoutput,
10098 note_secp,
10099 SEC_HAS_CONTENTS | SEC_READONLY);
10100
10101 /* Process the arch string. */
10102 len = strlen (cpu_arch_name);
10103
10104 i_note.namesz = len + 1;
10105 i_note.descsz = 0;
10106 i_note.type = NT_ARCH;
10107 p = frag_more (sizeof (e_note.namesz));
10108 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10109 p = frag_more (sizeof (e_note.descsz));
10110 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10111 p = frag_more (sizeof (e_note.type));
10112 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10113 p = frag_more (len + 1);
10114 strcpy (p, cpu_arch_name);
10115
10116 frag_align (2, 0, 0);
10117
10118 subseg_set (seg, subseg);
10119 }
10120}
10121#endif
252b5132 10122\f
252b5132 10123symbolS *
7016a5d5 10124md_undefined_symbol (char *name)
252b5132 10125{
18dc2407
ILT		 10126 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10127 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10128 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10129 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10130 {
10131 if (!GOT_symbol)
10132 {
10133 if (symbol_find (name))
10134 as_bad (_("GOT already in symbol table"));
10135 GOT_symbol = symbol_new (name, undefined_section,
10136 (valueT) 0, &zero_address_frag);
10137 };
10138 return GOT_symbol;
10139 }
252b5132
RH		 10140 return 0;
10141}
10142
10143/* Round up a section size to the appropriate boundary. */
47926f60 10144
252b5132 10145valueT
7016a5d5 10146md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10147{
4c63da97
AM		 10148#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10149 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10150 {
10151 /* For a.out, force the section size to be aligned. If we don't do
10152 this, BFD will align it for us, but it will not write out the
10153 final bytes of the section. This may be a bug in BFD, but it is
10154 easier to fix it here since that is how the other a.out targets
10155 work. */
10156 int align;
10157
10158 align = bfd_get_section_alignment (stdoutput, segment);
10159 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10160 }
252b5132
RH		 10161#endif
10162
10163 return size;
10164}
10165
10166/* On the i386, PC-relative offsets are relative to the start of the
10167 next instruction. That is, the address of the offset, plus its
10168 size, since the offset is always the last part of the insn. */
10169
10170long
e3bb37b5 10171md_pcrel_from (fixS *fixP)
252b5132
RH		 10172{
10173 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10174}
10175
10176#ifndef I386COFF
10177
10178static void
e3bb37b5 10179s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10180{
29b0f896 10181 int temp;
252b5132 10182
8a75718c
JB		 10183#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10184 if (IS_ELF)
10185 obj_elf_section_change_hook ();
10186#endif
252b5132
RH		 10187 temp = get_absolute_expression ();
10188 subseg_set (bss_section, (subsegT) temp);
10189 demand_empty_rest_of_line ();
10190}
10191
10192#endif
10193
252b5132 10194void
e3bb37b5 10195i386_validate_fix (fixS *fixp)
252b5132
RH		 10196{
10197 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10198 {
23df1078
JH		 10199 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10200 {
4fa24527 10201 if (!object_64bit)
23df1078
JH		 10202 abort ();
10203 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10204 }
10205 else
10206 {
4fa24527 10207 if (!object_64bit)
d6ab8113
JB		 10208 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10209 else
10210 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 10211 }
252b5132
RH		 10212 fixp->fx_subsy = 0;
10213 }
10214}
10215
252b5132 10216arelent *
7016a5d5 10217tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10218{
10219 arelent *rel;
10220 bfd_reloc_code_real_type code;
10221
10222 switch (fixp->fx_r_type)
10223 {
8ce3d284 10224#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10225 case BFD_RELOC_SIZE32:
10226 case BFD_RELOC_SIZE64:
10227 if (S_IS_DEFINED (fixp->fx_addsy)
10228 && !S_IS_EXTERNAL (fixp->fx_addsy))
10229 {
10230 /* Resolve size relocation against local symbol to size of
10231 the symbol plus addend. */
10232 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10233 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10234 && !fits_in_unsigned_long (value))
10235 as_bad_where (fixp->fx_file, fixp->fx_line,
10236 _("symbol size computation overflow"));
10237 fixp->fx_addsy = NULL;
10238 fixp->fx_subsy = NULL;
10239 md_apply_fix (fixp, (valueT *) &value, NULL);
10240 return NULL;
10241 }
8ce3d284 10242#endif
8fd4256d 10243
3e73aa7c
JH		 10244 case BFD_RELOC_X86_64_PLT32:
10245 case BFD_RELOC_X86_64_GOT32:
10246 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 10247 case BFD_RELOC_386_PLT32:
10248 case BFD_RELOC_386_GOT32:
10249 case BFD_RELOC_386_GOTOFF:
10250 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10251 case BFD_RELOC_386_TLS_GD:
10252 case BFD_RELOC_386_TLS_LDM:
10253 case BFD_RELOC_386_TLS_LDO_32:
10254 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10255 case BFD_RELOC_386_TLS_IE:
10256 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10257 case BFD_RELOC_386_TLS_LE_32:
10258 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10259 case BFD_RELOC_386_TLS_GOTDESC:
10260 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10261 case BFD_RELOC_X86_64_TLSGD:
10262 case BFD_RELOC_X86_64_TLSLD:
10263 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10264 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10265 case BFD_RELOC_X86_64_GOTTPOFF:
10266 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10267 case BFD_RELOC_X86_64_TPOFF64:
10268 case BFD_RELOC_X86_64_GOTOFF64:
10269 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10270 case BFD_RELOC_X86_64_GOT64:
10271 case BFD_RELOC_X86_64_GOTPCREL64:
10272 case BFD_RELOC_X86_64_GOTPC64:
10273 case BFD_RELOC_X86_64_GOTPLT64:
10274 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10275 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10276 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10277 case BFD_RELOC_RVA:
10278 case BFD_RELOC_VTABLE_ENTRY:
10279 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10280#ifdef TE_PE
10281 case BFD_RELOC_32_SECREL:
10282#endif
252b5132
RH		 10283 code = fixp->fx_r_type;
10284 break;
dbbaec26
L		 10285 case BFD_RELOC_X86_64_32S:
10286 if (!fixp->fx_pcrel)
10287 {
10288 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10289 code = fixp->fx_r_type;
10290 break;
10291 }
252b5132 10292 default:
93382f6d 10293 if (fixp->fx_pcrel)
252b5132 10294 {
93382f6d
AM		 10295 switch (fixp->fx_size)
10296 {
10297 default:
b091f402
AM		 10298 as_bad_where (fixp->fx_file, fixp->fx_line,
10299 _("can not do %d byte pc-relative relocation"),
10300 fixp->fx_size);
93382f6d
AM		 10301 code = BFD_RELOC_32_PCREL;
10302 break;
10303 case 1: code = BFD_RELOC_8_PCREL; break;
10304 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10305 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10306#ifdef BFD64
10307 case 8: code = BFD_RELOC_64_PCREL; break;
10308#endif
93382f6d
AM		 10309 }
10310 }
10311 else
10312 {
10313 switch (fixp->fx_size)
10314 {
10315 default:
b091f402
AM		 10316 as_bad_where (fixp->fx_file, fixp->fx_line,
10317 _("can not do %d byte relocation"),
10318 fixp->fx_size);
93382f6d
AM		 10319 code = BFD_RELOC_32;
10320 break;
10321 case 1: code = BFD_RELOC_8; break;
10322 case 2: code = BFD_RELOC_16; break;
10323 case 4: code = BFD_RELOC_32; break;
937149dd 10324#ifdef BFD64
3e73aa7c 10325 case 8: code = BFD_RELOC_64; break;
937149dd 10326#endif
93382f6d 10327 }
252b5132
RH		 10328 }
10329 break;
10330 }
252b5132 10331
d182319b
JB		 10332 if ((code == BFD_RELOC_32
10333 || code == BFD_RELOC_32_PCREL
10334 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10335 && GOT_symbol
10336 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10337 {
4fa24527 10338 if (!object_64bit)
d6ab8113
JB		 10339 code = BFD_RELOC_386_GOTPC;
10340 else
10341 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10342 }
7b81dfbb
AJ		 10343 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10344 && GOT_symbol
10345 && fixp->fx_addsy == GOT_symbol)
10346 {
10347 code = BFD_RELOC_X86_64_GOTPC64;
10348 }
252b5132
RH		 10349
10350 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 10351 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10352 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10353
10354 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10355
3e73aa7c
JH		 10356 if (!use_rela_relocations)
10357 {
10358 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10359 vtable entry to be used in the relocation's section offset. */
10360 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10361 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10362#if defined (OBJ_COFF) && defined (TE_PE)
10363 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10364 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10365 else
10366#endif
c6682705 10367 rel->addend = 0;
3e73aa7c
JH		 10368 }
10369 /* Use the rela in 64bit mode. */
252b5132 10370 else
3e73aa7c 10371 {
862be3fb
L		 10372 if (disallow_64bit_reloc)
10373 switch (code)
10374 {
862be3fb
L		 10375 case BFD_RELOC_X86_64_DTPOFF64:
10376 case BFD_RELOC_X86_64_TPOFF64:
10377 case BFD_RELOC_64_PCREL:
10378 case BFD_RELOC_X86_64_GOTOFF64:
10379 case BFD_RELOC_X86_64_GOT64:
10380 case BFD_RELOC_X86_64_GOTPCREL64:
10381 case BFD_RELOC_X86_64_GOTPC64:
10382 case BFD_RELOC_X86_64_GOTPLT64:
10383 case BFD_RELOC_X86_64_PLTOFF64:
10384 as_bad_where (fixp->fx_file, fixp->fx_line,
10385 _("cannot represent relocation type %s in x32 mode"),
10386 bfd_get_reloc_code_name (code));
10387 break;
10388 default:
10389 break;
10390 }
10391
062cd5e7
AS		 10392 if (!fixp->fx_pcrel)
10393 rel->addend = fixp->fx_offset;
10394 else
10395 switch (code)
10396 {
10397 case BFD_RELOC_X86_64_PLT32:
10398 case BFD_RELOC_X86_64_GOT32:
10399 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 10400 case BFD_RELOC_X86_64_TLSGD:
10401 case BFD_RELOC_X86_64_TLSLD:
10402 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 10403 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10404 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 10405 rel->addend = fixp->fx_offset - fixp->fx_size;
10406 break;
10407 default:
10408 rel->addend = (section->vma
10409 - fixp->fx_size
10410 + fixp->fx_addnumber
10411 + md_pcrel_from (fixp));
10412 break;
10413 }
3e73aa7c
JH		 10414 }
10415
252b5132
RH		 10416 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10417 if (rel->howto == NULL)
10418 {
10419 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 10420 _("cannot represent relocation type %s"),
252b5132
RH		 10421 bfd_get_reloc_code_name (code));
10422 /* Set howto to a garbage value so that we can keep going. */
10423 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 10424 gas_assert (rel->howto != NULL);
252b5132
RH		 10425 }
10426
10427 return rel;
10428}
10429
ee86248c 10430#include "tc-i386-intel.c"
54cfded0 10431
a60de03c
JB		 10432void
10433tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10434{
a60de03c
JB		 10435 int saved_naked_reg;
10436 char saved_register_dot;
54cfded0 10437
a60de03c
JB		 10438 saved_naked_reg = allow_naked_reg;
10439 allow_naked_reg = 1;
10440 saved_register_dot = register_chars['.'];
10441 register_chars['.'] = '.';
10442 allow_pseudo_reg = 1;
10443 expression_and_evaluate (exp);
10444 allow_pseudo_reg = 0;
10445 register_chars['.'] = saved_register_dot;
10446 allow_naked_reg = saved_naked_reg;
10447
e96d56a1 10448 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10449 {
a60de03c
JB		 10450 if ((addressT) exp->X_add_number < i386_regtab_size)
10451 {
10452 exp->X_op = O_constant;
10453 exp->X_add_number = i386_regtab[exp->X_add_number]
10454 .dw2_regnum[flag_code >> 1];
10455 }
10456 else
10457 exp->X_op = O_illegal;
54cfded0 10458 }
54cfded0
AM		 10459}
10460
10461void
10462tc_x86_frame_initial_instructions (void)
10463{
a60de03c
JB		 10464 static unsigned int sp_regno[2];
10465
10466 if (!sp_regno[flag_code >> 1])
10467 {
10468 char *saved_input = input_line_pointer;
10469 char sp[][4] = {"esp", "rsp"};
10470 expressionS exp;
a4447b93 10471
a60de03c
JB		 10472 input_line_pointer = sp[flag_code >> 1];
10473 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 10474 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 10475 sp_regno[flag_code >> 1] = exp.X_add_number;
10476 input_line_pointer = saved_input;
10477 }
a4447b93 10478
61ff971f
L		 10479 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10480 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10481}
d2b2c203 10482
d7921315
L		 10483int
10484x86_dwarf2_addr_size (void)
10485{
10486#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10487 if (x86_elf_abi == X86_64_X32_ABI)
10488 return 4;
10489#endif
10490 return bfd_arch_bits_per_address (stdoutput) / 8;
10491}
10492
d2b2c203
DJ		 10493int
10494i386_elf_section_type (const char *str, size_t len)
10495{
10496 if (flag_code == CODE_64BIT
10497 && len == sizeof ("unwind") - 1
10498 && strncmp (str, "unwind", 6) == 0)
10499 return SHT_X86_64_UNWIND;
10500
10501 return -1;
10502}
bb41ade5 10503
ad5fec3b
EB		 10504#ifdef TE_SOLARIS
10505void
10506i386_solaris_fix_up_eh_frame (segT sec)
10507{
10508 if (flag_code == CODE_64BIT)
10509 elf_section_type (sec) = SHT_X86_64_UNWIND;
10510}
10511#endif
10512
bb41ade5
AM		 10513#ifdef TE_PE
10514void
10515tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10516{
91d6fa6a 10517 expressionS exp;
bb41ade5 10518
91d6fa6a
NC		 10519 exp.X_op = O_secrel;
10520 exp.X_add_symbol = symbol;
10521 exp.X_add_number = 0;
10522 emit_expr (&exp, size);
bb41ade5
AM		 10523}
10524#endif
3b22753a
L		 10525
10526#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10527/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10528
01e1a5bc 10529bfd_vma
3b22753a
L		 10530x86_64_section_letter (int letter, char **ptr_msg)
10531{
10532 if (flag_code == CODE_64BIT)
10533 {
10534 if (letter == 'l')
10535 return SHF_X86_64_LARGE;
10536
8f3bae45 10537 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10538 }
3b22753a 10539 else
8f3bae45 10540 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10541 return -1;
10542}
10543
01e1a5bc 10544bfd_vma
3b22753a
L		 10545x86_64_section_word (char *str, size_t len)
10546{
8620418b 10547 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10548 return SHF_X86_64_LARGE;
10549
10550 return -1;
10551}
10552
10553static void
10554handle_large_common (int small ATTRIBUTE_UNUSED)
10555{
10556 if (flag_code != CODE_64BIT)
10557 {
10558 s_comm_internal (0, elf_common_parse);
10559 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10560 }
10561 else
10562 {
10563 static segT lbss_section;
10564 asection *saved_com_section_ptr = elf_com_section_ptr;
10565 asection *saved_bss_section = bss_section;
10566
10567 if (lbss_section == NULL)
10568 {
10569 flagword applicable;
10570 segT seg = now_seg;
10571 subsegT subseg = now_subseg;
10572
10573 /* The .lbss section is for local .largecomm symbols. */
10574 lbss_section = subseg_new (".lbss", 0);
10575 applicable = bfd_applicable_section_flags (stdoutput);
10576 bfd_set_section_flags (stdoutput, lbss_section,
10577 applicable & SEC_ALLOC);
10578 seg_info (lbss_section)->bss = 1;
10579
10580 subseg_set (seg, subseg);
10581 }
10582
10583 elf_com_section_ptr = &_bfd_elf_large_com_section;
10584 bss_section = lbss_section;
10585
10586 s_comm_internal (0, elf_common_parse);
10587
10588 elf_com_section_ptr = saved_com_section_ptr;
10589 bss_section = saved_bss_section;
10590 }
10591}
10592#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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