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x86: fold RegXMM/RegYMM/RegZMM into RegSIMD
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
2571583a 2 Copyright (C) 1989-2017 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
47926f60
KH		 21/* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 23 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
252b5132 27
252b5132 28#include "as.h"
3882b010 29#include "safe-ctype.h"
252b5132 30#include "subsegs.h"
316e2c05 31#include "dwarf2dbg.h"
54cfded0 32#include "dw2gencfi.h"
d2b2c203 33#include "elf/x86-64.h"
40fb9820 34#include "opcodes/i386-init.h"
252b5132 35
252b5132
RH		 36#ifndef REGISTER_WARNINGS
37#define REGISTER_WARNINGS 1
38#endif
39
c3332e24 40#ifndef INFER_ADDR_PREFIX
eecb386c 41#define INFER_ADDR_PREFIX 1
c3332e24
AM		 42#endif
43
29b0f896
AM		 44#ifndef DEFAULT_ARCH
45#define DEFAULT_ARCH "i386"
246fcdee 46#endif
252b5132 47
edde18a5
AM		 48#ifndef INLINE
49#if __GNUC__ >= 2
50#define INLINE __inline__
51#else
52#define INLINE
53#endif
54#endif
55
6305a203
L		 56/* Prefixes will be emitted in the order defined below.
57 WAIT_PREFIX must be the first prefix since FWAIT is really is an
58 instruction, and so must come before any prefixes.
59 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
42164a71 60 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
6305a203
L		 61#define WAIT_PREFIX 0
62#define SEG_PREFIX 1
63#define ADDR_PREFIX 2
64#define DATA_PREFIX 3
c32fa91d 65#define REP_PREFIX 4
42164a71 66#define HLE_PREFIX REP_PREFIX
7e8b059b 67#define BND_PREFIX REP_PREFIX
c32fa91d 68#define LOCK_PREFIX 5
4e9ac44a
L		 69#define REX_PREFIX 6 /* must come last. */
70#define MAX_PREFIXES 7 /* max prefixes per opcode */
6305a203
L		 71
72/* we define the syntax here (modulo base,index,scale syntax) */
73#define REGISTER_PREFIX '%'
74#define IMMEDIATE_PREFIX '$'
75#define ABSOLUTE_PREFIX '*'
76
77/* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79#define WORD_MNEM_SUFFIX 'w'
80#define BYTE_MNEM_SUFFIX 'b'
81#define SHORT_MNEM_SUFFIX 's'
82#define LONG_MNEM_SUFFIX 'l'
83#define QWORD_MNEM_SUFFIX 'q'
84#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 85#define YMMWORD_MNEM_SUFFIX 'y'
43234a1e 86#define ZMMWORD_MNEM_SUFFIX 'z'
6305a203
L		 87/* Intel Syntax. Use a non-ascii letter since since it never appears
88 in instructions. */
89#define LONG_DOUBLE_MNEM_SUFFIX '\1'
90
91#define END_OF_INSN '\0'
92
93/*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
100typedef struct
101{
d3ce72d0
NC		 102 const insn_template *start;
103 const insn_template *end;
6305a203
L		 104}
105templates;
106
107/* 386 operand encoding bytes: see 386 book for details of this. */
108typedef struct
109{
110 unsigned int regmem; /* codes register or memory operand */
111 unsigned int reg; /* codes register operand (or extended opcode) */
112 unsigned int mode; /* how to interpret regmem & reg */
113}
114modrm_byte;
115
116/* x86-64 extension prefix. */
117typedef int rex_byte;
118
6305a203
L		 119/* 386 opcode byte to code indirect addressing. */
120typedef struct
121{
122 unsigned base;
123 unsigned index;
124 unsigned scale;
125}
126sib_byte;
127
6305a203
L		 128/* x86 arch names, types and features */
129typedef struct
130{
131 const char *name; /* arch name */
8a2c8fef 132 unsigned int len; /* arch string length */
6305a203
L		 133 enum processor_type type; /* arch type */
134 i386_cpu_flags flags; /* cpu feature flags */
8a2c8fef 135 unsigned int skip; /* show_arch should skip this. */
6305a203
L		 136}
137arch_entry;
138
293f5f65
L		 139/* Used to turn off indicated flags. */
140typedef struct
141{
142 const char *name; /* arch name */
143 unsigned int len; /* arch string length */
144 i386_cpu_flags flags; /* cpu feature flags */
145}
146noarch_entry;
147
78f12dd3 148static void update_code_flag (int, int);
e3bb37b5
L		 149static void set_code_flag (int);
150static void set_16bit_gcc_code_flag (int);
151static void set_intel_syntax (int);
1efbbeb4 152static void set_intel_mnemonic (int);
db51cc60 153static void set_allow_index_reg (int);
7bab8ab5 154static void set_check (int);
e3bb37b5 155static void set_cpu_arch (int);
6482c264 156#ifdef TE_PE
e3bb37b5 157static void pe_directive_secrel (int);
6482c264 158#endif
e3bb37b5
L		 159static void signed_cons (int);
160static char *output_invalid (int c);
ee86248c
JB		 161static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
162 const char *);
163static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
164 const char *);
a7619375 165static int i386_att_operand (char *);
e3bb37b5 166static int i386_intel_operand (char *, int);
ee86248c
JB		 167static int i386_intel_simplify (expressionS *);
168static int i386_intel_parse_name (const char *, expressionS *);
e3bb37b5
L		 169static const reg_entry *parse_register (char *, char **);
170static char *parse_insn (char *, char *);
171static char *parse_operands (char *, const char *);
172static void swap_operands (void);
4d456e3d 173static void swap_2_operands (int, int);
e3bb37b5
L		 174static void optimize_imm (void);
175static void optimize_disp (void);
83b16ac6 176static const insn_template *match_template (char);
e3bb37b5
L		 177static int check_string (void);
178static int process_suffix (void);
179static int check_byte_reg (void);
180static int check_long_reg (void);
181static int check_qword_reg (void);
182static int check_word_reg (void);
183static int finalize_imm (void);
184static int process_operands (void);
185static const seg_entry *build_modrm_byte (void);
186static void output_insn (void);
187static void output_imm (fragS *, offsetT);
188static void output_disp (fragS *, offsetT);
29b0f896 189#ifndef I386COFF
e3bb37b5 190static void s_bss (int);
252b5132 191#endif
17d4e2a2
L		 192#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
193static void handle_large_common (int small ATTRIBUTE_UNUSED);
194#endif
252b5132 195
a847613f 196static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 197
43234a1e
L		 198/* This struct describes rounding control and SAE in the instruction. */
199struct RC_Operation
200{
201 enum rc_type
202 {
203 rne = 0,
204 rd,
205 ru,
206 rz,
207 saeonly
208 } type;
209 int operand;
210};
211
212static struct RC_Operation rc_op;
213
214/* The struct describes masking, applied to OPERAND in the instruction.
215 MASK is a pointer to the corresponding mask register. ZEROING tells
216 whether merging or zeroing mask is used. */
217struct Mask_Operation
218{
219 const reg_entry *mask;
220 unsigned int zeroing;
221 /* The operand where this operation is associated. */
222 int operand;
223};
224
225static struct Mask_Operation mask_op;
226
227/* The struct describes broadcasting, applied to OPERAND. FACTOR is
228 broadcast factor. */
229struct Broadcast_Operation
230{
231 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
232 int type;
233
234 /* Index of broadcasted operand. */
235 int operand;
236};
237
238static struct Broadcast_Operation broadcast_op;
239
c0f3af97
L		 240/* VEX prefix. */
241typedef struct
242{
43234a1e
L		 243 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
244 unsigned char bytes[4];
c0f3af97
L		 245 unsigned int length;
246 /* Destination or source register specifier. */
247 const reg_entry *register_specifier;
248} vex_prefix;
249
252b5132 250/* 'md_assemble ()' gathers together information and puts it into a
47926f60 251 i386_insn. */
252b5132 252
520dc8e8
AM		 253union i386_op
254 {
255 expressionS *disps;
256 expressionS *imms;
257 const reg_entry *regs;
258 };
259
a65babc9
L		 260enum i386_error
261 {
86e026a4 262 operand_size_mismatch,
a65babc9
L		 263 operand_type_mismatch,
264 register_type_mismatch,
265 number_of_operands_mismatch,
266 invalid_instruction_suffix,
267 bad_imm4,
268 old_gcc_only,
269 unsupported_with_intel_mnemonic,
270 unsupported_syntax,
6c30d220
L		 271 unsupported,
272 invalid_vsib_address,
7bab8ab5 273 invalid_vector_register_set,
43234a1e
L		 274 unsupported_vector_index_register,
275 unsupported_broadcast,
276 broadcast_not_on_src_operand,
277 broadcast_needed,
278 unsupported_masking,
279 mask_not_on_destination,
280 no_default_mask,
281 unsupported_rc_sae,
282 rc_sae_operand_not_last_imm,
283 invalid_register_operand,
a65babc9
L		 284 };
285
252b5132
RH		 286struct _i386_insn
287 {
47926f60 288 /* TM holds the template for the insn were currently assembling. */
d3ce72d0 289 insn_template tm;
252b5132 290
7d5e4556
L		 291 /* SUFFIX holds the instruction size suffix for byte, word, dword
292 or qword, if given. */
252b5132
RH		 293 char suffix;
294
47926f60 295 /* OPERANDS gives the number of given operands. */
252b5132
RH		 296 unsigned int operands;
297
298 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
299 of given register, displacement, memory operands and immediate
47926f60 300 operands. */
252b5132
RH		 301 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
302
303 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 304 use OP[i] for the corresponding operand. */
40fb9820 305 i386_operand_type types[MAX_OPERANDS];
252b5132 306
520dc8e8
AM		 307 /* Displacement expression, immediate expression, or register for each
308 operand. */
309 union i386_op op[MAX_OPERANDS];
252b5132 310
3e73aa7c
JH		 311 /* Flags for operands. */
312 unsigned int flags[MAX_OPERANDS];
313#define Operand_PCrel 1
314
252b5132 315 /* Relocation type for operand */
f86103b7 316 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 317
252b5132
RH		 318 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
319 the base index byte below. */
320 const reg_entry *base_reg;
321 const reg_entry *index_reg;
322 unsigned int log2_scale_factor;
323
324 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 325 explicit segment overrides are given. */
ce8a8b2f 326 const seg_entry *seg[2];
252b5132 327
8325cc63
JB		 328 /* Copied first memory operand string, for re-checking. */
329 char *memop1_string;
330
252b5132
RH		 331 /* PREFIX holds all the given prefix opcodes (usually null).
332 PREFIXES is the number of prefix opcodes. */
333 unsigned int prefixes;
334 unsigned char prefix[MAX_PREFIXES];
335
336 /* RM and SIB are the modrm byte and the sib byte where the
c1e679ec 337 addressing modes of this insn are encoded. */
252b5132 338 modrm_byte rm;
3e73aa7c 339 rex_byte rex;
43234a1e 340 rex_byte vrex;
252b5132 341 sib_byte sib;
c0f3af97 342 vex_prefix vex;
b6169b20 343
43234a1e
L		 344 /* Masking attributes. */
345 struct Mask_Operation *mask;
346
347 /* Rounding control and SAE attributes. */
348 struct RC_Operation *rounding;
349
350 /* Broadcasting attributes. */
351 struct Broadcast_Operation *broadcast;
352
353 /* Compressed disp8*N attribute. */
354 unsigned int memshift;
355
86fa6981
L		 356 /* Prefer load or store in encoding. */
357 enum
358 {
359 dir_encoding_default = 0,
360 dir_encoding_load,
361 dir_encoding_store
362 } dir_encoding;
891edac4 363
a501d77e
L		 364 /* Prefer 8bit or 32bit displacement in encoding. */
365 enum
366 {
367 disp_encoding_default = 0,
368 disp_encoding_8bit,
369 disp_encoding_32bit
370 } disp_encoding;
f8a5c266 371
86fa6981
L		 372 /* How to encode vector instructions. */
373 enum
374 {
375 vex_encoding_default = 0,
376 vex_encoding_vex2,
377 vex_encoding_vex3,
378 vex_encoding_evex
379 } vec_encoding;
380
d5de92cf
L		 381 /* REP prefix. */
382 const char *rep_prefix;
383
165de32a
L		 384 /* HLE prefix. */
385 const char *hle_prefix;
42164a71 386
7e8b059b
L		 387 /* Have BND prefix. */
388 const char *bnd_prefix;
389
04ef582a
L		 390 /* Have NOTRACK prefix. */
391 const char *notrack_prefix;
392
891edac4 393 /* Error message. */
a65babc9 394 enum i386_error error;
252b5132
RH		 395 };
396
397typedef struct _i386_insn i386_insn;
398
43234a1e
L		 399/* Link RC type with corresponding string, that'll be looked for in
400 asm. */
401struct RC_name
402{
403 enum rc_type type;
404 const char *name;
405 unsigned int len;
406};
407
408static const struct RC_name RC_NamesTable[] =
409{
410 { rne, STRING_COMMA_LEN ("rn-sae") },
411 { rd, STRING_COMMA_LEN ("rd-sae") },
412 { ru, STRING_COMMA_LEN ("ru-sae") },
413 { rz, STRING_COMMA_LEN ("rz-sae") },
414 { saeonly, STRING_COMMA_LEN ("sae") },
415};
416
252b5132
RH		 417/* List of chars besides those in app.c:symbol_chars that can start an
418 operand. Used to prevent the scrubber eating vital white-space. */
86fa6981 419const char extra_symbol_chars[] = "*%-([{}"
252b5132 420#ifdef LEX_AT
32137342
NC		 421 "@"
422#endif
423#ifdef LEX_QM
424 "?"
252b5132 425#endif
32137342 426 ;
252b5132 427
29b0f896
AM		 428#if (defined (TE_I386AIX) \
429 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 430 && !defined (TE_GNU) \
29b0f896 431 && !defined (TE_LINUX) \
8d63c93e
RM		 432 && !defined (TE_NACL) \
433 && !defined (TE_NETWARE) \
29b0f896 434 && !defined (TE_FreeBSD) \
5b806d27 435 && !defined (TE_DragonFly) \
29b0f896 436 && !defined (TE_NetBSD)))
252b5132 437/* This array holds the chars that always start a comment. If the
b3b91714
AM		 438 pre-processor is disabled, these aren't very useful. The option
439 --divide will remove '/' from this list. */
440const char *i386_comment_chars = "#/";
441#define SVR4_COMMENT_CHARS 1
252b5132 442#define PREFIX_SEPARATOR '\\'
252b5132 443
b3b91714
AM		 444#else
445const char *i386_comment_chars = "#";
446#define PREFIX_SEPARATOR '/'
447#endif
448
252b5132
RH		 449/* This array holds the chars that only start a comment at the beginning of
450 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 451 .line and .file directives will appear in the pre-processed output.
452 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 453 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 454 #NO_APP at the beginning of its output.
455 Also note that comments started like this one will always work if
252b5132 456 '/' isn't otherwise defined. */
b3b91714 457const char line_comment_chars[] = "#/";
252b5132 458
63a0b638 459const char line_separator_chars[] = ";";
252b5132 460
ce8a8b2f
AM		 461/* Chars that can be used to separate mant from exp in floating point
462 nums. */
252b5132
RH		 463const char EXP_CHARS[] = "eE";
464
ce8a8b2f
AM		 465/* Chars that mean this number is a floating point constant
466 As in 0f12.456
467 or 0d1.2345e12. */
252b5132
RH		 468const char FLT_CHARS[] = "fFdDxX";
469
ce8a8b2f 470/* Tables for lexical analysis. */
252b5132
RH		 471static char mnemonic_chars[256];
472static char register_chars[256];
473static char operand_chars[256];
474static char identifier_chars[256];
475static char digit_chars[256];
476
ce8a8b2f 477/* Lexical macros. */
252b5132
RH		 478#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
479#define is_operand_char(x) (operand_chars[(unsigned char) x])
480#define is_register_char(x) (register_chars[(unsigned char) x])
481#define is_space_char(x) ((x) == ' ')
482#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
483#define is_digit_char(x) (digit_chars[(unsigned char) x])
484
0234cb7c 485/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 486static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
487
488/* md_assemble() always leaves the strings it's passed unaltered. To
489 effect this we maintain a stack of saved characters that we've smashed
490 with '\0's (indicating end of strings for various sub-fields of the
47926f60 491 assembler instruction). */
252b5132 492static char save_stack[32];
ce8a8b2f 493static char *save_stack_p;
252b5132
RH		 494#define END_STRING_AND_SAVE(s) \
495 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
496#define RESTORE_END_STRING(s) \
497 do { *(s) = *--save_stack_p; } while (0)
498
47926f60 499/* The instruction we're assembling. */
252b5132
RH		 500static i386_insn i;
501
502/* Possible templates for current insn. */
503static const templates *current_templates;
504
31b2323c
L		 505/* Per instruction expressionS buffers: max displacements & immediates. */
506static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
507static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 508
47926f60 509/* Current operand we are working on. */
ee86248c 510static int this_operand = -1;
252b5132 511
3e73aa7c
JH		 512/* We support four different modes. FLAG_CODE variable is used to distinguish
513 these. */
514
515enum flag_code {
516 CODE_32BIT,
517 CODE_16BIT,
518 CODE_64BIT };
519
520static enum flag_code flag_code;
4fa24527 521static unsigned int object_64bit;
862be3fb 522static unsigned int disallow_64bit_reloc;
3e73aa7c
JH		 523static int use_rela_relocations = 0;
524
7af8ed2d
NC		 525#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
526 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
527 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
528
351f65ca
L		 529/* The ELF ABI to use. */
530enum x86_elf_abi
531{
532 I386_ABI,
7f56bc95
L		 533 X86_64_ABI,
534 X86_64_X32_ABI
351f65ca
L		 535};
536
537static enum x86_elf_abi x86_elf_abi = I386_ABI;
7af8ed2d 538#endif
351f65ca 539
167ad85b
TG		 540#if defined (TE_PE) || defined (TE_PEP)
541/* Use big object file format. */
542static int use_big_obj = 0;
543#endif
544
8dcea932
L		 545#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
546/* 1 if generating code for a shared library. */
547static int shared = 0;
548#endif
549
47926f60
KH		 550/* 1 for intel syntax,
551 0 if att syntax. */
552static int intel_syntax = 0;
252b5132 553
e89c5eaa
L		 554/* 1 for Intel64 ISA,
555 0 if AMD64 ISA. */
556static int intel64;
557
1efbbeb4
L		 558/* 1 for intel mnemonic,
559 0 if att mnemonic. */
560static int intel_mnemonic = !SYSV386_COMPAT;
561
5209009a 562/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 563static int old_gcc = OLDGCC_COMPAT;
564
a60de03c
JB		 565/* 1 if pseudo registers are permitted. */
566static int allow_pseudo_reg = 0;
567
47926f60
KH		 568/* 1 if register prefix % not required. */
569static int allow_naked_reg = 0;
252b5132 570
33eaf5de 571/* 1 if the assembler should add BND prefix for all control-transferring
7e8b059b
L		 572 instructions supporting it, even if this prefix wasn't specified
573 explicitly. */
574static int add_bnd_prefix = 0;
575
ba104c83 576/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 577static int allow_index_reg = 0;
578
d022bddd
IT		 579/* 1 if the assembler should ignore LOCK prefix, even if it was
580 specified explicitly. */
581static int omit_lock_prefix = 0;
582
e4e00185
AS		 583/* 1 if the assembler should encode lfence, mfence, and sfence as
584 "lock addl $0, (%{re}sp)". */
585static int avoid_fence = 0;
586
0cb4071e
L		 587/* 1 if the assembler should generate relax relocations. */
588
589static int generate_relax_relocations
590 = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS;
591
7bab8ab5 592static enum check_kind
daf50ae7 593 {
7bab8ab5
JB		 594 check_none = 0,
595 check_warning,
596 check_error
daf50ae7 597 }
7bab8ab5 598sse_check, operand_check = check_warning;
daf50ae7 599
2ca3ace5
L		 600/* Register prefix used for error message. */
601static const char *register_prefix = "%";
602
47926f60
KH		 603/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
604 leave, push, and pop instructions so that gcc has the same stack
605 frame as in 32 bit mode. */
606static char stackop_size = '\0';
eecb386c 607
12b55ccc
L		 608/* Non-zero to optimize code alignment. */
609int optimize_align_code = 1;
610
47926f60
KH		 611/* Non-zero to quieten some warnings. */
612static int quiet_warnings = 0;
a38cf1db 613
47926f60
KH		 614/* CPU name. */
615static const char *cpu_arch_name = NULL;
6305a203 616static char *cpu_sub_arch_name = NULL;
a38cf1db 617
47926f60 618/* CPU feature flags. */
40fb9820
L		 619static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
620
ccc9c027
L		 621/* If we have selected a cpu we are generating instructions for. */
622static int cpu_arch_tune_set = 0;
623
9103f4f4 624/* Cpu we are generating instructions for. */
fbf3f584 625enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 626
627/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 628static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 629
ccc9c027 630/* CPU instruction set architecture used. */
fbf3f584 631enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 632
9103f4f4 633/* CPU feature flags of instruction set architecture used. */
fbf3f584 634i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 635
fddf5b5b
AM		 636/* If set, conditional jumps are not automatically promoted to handle
637 larger than a byte offset. */
638static unsigned int no_cond_jump_promotion = 0;
639
c0f3af97
L		 640/* Encode SSE instructions with VEX prefix. */
641static unsigned int sse2avx;
642
539f890d
L		 643/* Encode scalar AVX instructions with specific vector length. */
644static enum
645 {
646 vex128 = 0,
647 vex256
648 } avxscalar;
649
43234a1e
L		 650/* Encode scalar EVEX LIG instructions with specific vector length. */
651static enum
652 {
653 evexl128 = 0,
654 evexl256,
655 evexl512
656 } evexlig;
657
658/* Encode EVEX WIG instructions with specific evex.w. */
659static enum
660 {
661 evexw0 = 0,
662 evexw1
663 } evexwig;
664
d3d3c6db
IT		 665/* Value to encode in EVEX RC bits, for SAE-only instructions. */
666static enum rc_type evexrcig = rne;
667
29b0f896 668/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 669static symbolS *GOT_symbol;
29b0f896 670
a4447b93
RH		 671/* The dwarf2 return column, adjusted for 32 or 64 bit. */
672unsigned int x86_dwarf2_return_column;
673
674/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
675int x86_cie_data_alignment;
676
252b5132 677/* Interface to relax_segment.
fddf5b5b
AM		 678 There are 3 major relax states for 386 jump insns because the
679 different types of jumps add different sizes to frags when we're
680 figuring out what sort of jump to choose to reach a given label. */
252b5132 681
47926f60 682/* Types. */
93c2a809
AM		 683#define UNCOND_JUMP 0
684#define COND_JUMP 1
685#define COND_JUMP86 2
fddf5b5b 686
47926f60 687/* Sizes. */
252b5132
RH		 688#define CODE16 1
689#define SMALL 0
29b0f896 690#define SMALL16 (SMALL | CODE16)
252b5132 691#define BIG 2
29b0f896 692#define BIG16 (BIG | CODE16)
252b5132
RH		 693
694#ifndef INLINE
695#ifdef __GNUC__
696#define INLINE __inline__
697#else
698#define INLINE
699#endif
700#endif
701
fddf5b5b
AM		 702#define ENCODE_RELAX_STATE(type, size) \
703 ((relax_substateT) (((type) << 2) | (size)))
704#define TYPE_FROM_RELAX_STATE(s) \
705 ((s) >> 2)
706#define DISP_SIZE_FROM_RELAX_STATE(s) \
707 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 708
709/* This table is used by relax_frag to promote short jumps to long
710 ones where necessary. SMALL (short) jumps may be promoted to BIG
711 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
712 don't allow a short jump in a 32 bit code segment to be promoted to
713 a 16 bit offset jump because it's slower (requires data size
714 prefix), and doesn't work, unless the destination is in the bottom
715 64k of the code segment (The top 16 bits of eip are zeroed). */
716
717const relax_typeS md_relax_table[] =
718{
24eab124
AM		 719 /* The fields are:
720 1) most positive reach of this state,
721 2) most negative reach of this state,
93c2a809 722 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 723 4) which index into the table to try if we can't fit into this one. */
252b5132 724
fddf5b5b 725 /* UNCOND_JUMP states. */
93c2a809
AM		 726 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
727 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
728 /* dword jmp adds 4 bytes to frag:
729 0 extra opcode bytes, 4 displacement bytes. */
252b5132 730 {0, 0, 4, 0},
93c2a809
AM		 731 /* word jmp adds 2 byte2 to frag:
732 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 733 {0, 0, 2, 0},
734
93c2a809
AM		 735 /* COND_JUMP states. */
736 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
737 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
738 /* dword conditionals adds 5 bytes to frag:
739 1 extra opcode byte, 4 displacement bytes. */
740 {0, 0, 5, 0},
fddf5b5b 741 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 742 1 extra opcode byte, 2 displacement bytes. */
743 {0, 0, 3, 0},
744
745 /* COND_JUMP86 states. */
746 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
747 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
748 /* dword conditionals adds 5 bytes to frag:
749 1 extra opcode byte, 4 displacement bytes. */
750 {0, 0, 5, 0},
751 /* word conditionals add 4 bytes to frag:
752 1 displacement byte and a 3 byte long branch insn. */
753 {0, 0, 4, 0}
252b5132
RH		 754};
755
9103f4f4
L		 756static const arch_entry cpu_arch[] =
757{
89507696
JB		 758 /* Do not replace the first two entries - i386_target_format()
759 relies on them being there in this order. */
8a2c8fef 760 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
293f5f65 761 CPU_GENERIC32_FLAGS, 0 },
8a2c8fef 762 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
293f5f65 763 CPU_GENERIC64_FLAGS, 0 },
8a2c8fef 764 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
293f5f65 765 CPU_NONE_FLAGS, 0 },
8a2c8fef 766 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
293f5f65 767 CPU_I186_FLAGS, 0 },
8a2c8fef 768 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
293f5f65 769 CPU_I286_FLAGS, 0 },
8a2c8fef 770 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
293f5f65 771 CPU_I386_FLAGS, 0 },
8a2c8fef 772 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
293f5f65 773 CPU_I486_FLAGS, 0 },
8a2c8fef 774 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
293f5f65 775 CPU_I586_FLAGS, 0 },
8a2c8fef 776 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
293f5f65 777 CPU_I686_FLAGS, 0 },
8a2c8fef 778 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
293f5f65 779 CPU_I586_FLAGS, 0 },
8a2c8fef 780 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
293f5f65 781 CPU_PENTIUMPRO_FLAGS, 0 },
8a2c8fef 782 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
293f5f65 783 CPU_P2_FLAGS, 0 },
8a2c8fef 784 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
293f5f65 785 CPU_P3_FLAGS, 0 },
8a2c8fef 786 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
293f5f65 787 CPU_P4_FLAGS, 0 },
8a2c8fef 788 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
293f5f65 789 CPU_CORE_FLAGS, 0 },
8a2c8fef 790 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
293f5f65 791 CPU_NOCONA_FLAGS, 0 },
8a2c8fef 792 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
293f5f65 793 CPU_CORE_FLAGS, 1 },
8a2c8fef 794 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
293f5f65 795 CPU_CORE_FLAGS, 0 },
8a2c8fef 796 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
293f5f65 797 CPU_CORE2_FLAGS, 1 },
8a2c8fef 798 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
293f5f65 799 CPU_CORE2_FLAGS, 0 },
8a2c8fef 800 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
293f5f65 801 CPU_COREI7_FLAGS, 0 },
8a2c8fef 802 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
293f5f65 803 CPU_L1OM_FLAGS, 0 },
7a9068fe 804 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
293f5f65 805 CPU_K1OM_FLAGS, 0 },
81486035 806 { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU,
293f5f65 807 CPU_IAMCU_FLAGS, 0 },
8a2c8fef 808 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
293f5f65 809 CPU_K6_FLAGS, 0 },
8a2c8fef 810 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
293f5f65 811 CPU_K6_2_FLAGS, 0 },
8a2c8fef 812 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
293f5f65 813 CPU_ATHLON_FLAGS, 0 },
8a2c8fef 814 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
293f5f65 815 CPU_K8_FLAGS, 1 },
8a2c8fef 816 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
293f5f65 817 CPU_K8_FLAGS, 0 },
8a2c8fef 818 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
293f5f65 819 CPU_K8_FLAGS, 0 },
8a2c8fef 820 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
293f5f65 821 CPU_AMDFAM10_FLAGS, 0 },
8aedb9fe 822 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
293f5f65 823 CPU_BDVER1_FLAGS, 0 },
8aedb9fe 824 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
293f5f65 825 CPU_BDVER2_FLAGS, 0 },
5e5c50d3 826 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
293f5f65 827 CPU_BDVER3_FLAGS, 0 },
c7b0bd56 828 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
293f5f65 829 CPU_BDVER4_FLAGS, 0 },
029f3522 830 { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER,
293f5f65 831 CPU_ZNVER1_FLAGS, 0 },
7b458c12 832 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
293f5f65 833 CPU_BTVER1_FLAGS, 0 },
7b458c12 834 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
293f5f65 835 CPU_BTVER2_FLAGS, 0 },
8a2c8fef 836 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
293f5f65 837 CPU_8087_FLAGS, 0 },
8a2c8fef 838 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
293f5f65 839 CPU_287_FLAGS, 0 },
8a2c8fef 840 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
293f5f65 841 CPU_387_FLAGS, 0 },
1848e567
L		 842 { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN,
843 CPU_687_FLAGS, 0 },
8a2c8fef 844 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
293f5f65 845 CPU_MMX_FLAGS, 0 },
8a2c8fef 846 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
293f5f65 847 CPU_SSE_FLAGS, 0 },
8a2c8fef 848 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
293f5f65 849 CPU_SSE2_FLAGS, 0 },
8a2c8fef 850 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
293f5f65 851 CPU_SSE3_FLAGS, 0 },
8a2c8fef 852 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
293f5f65 853 CPU_SSSE3_FLAGS, 0 },
8a2c8fef 854 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
293f5f65 855 CPU_SSE4_1_FLAGS, 0 },
8a2c8fef 856 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
293f5f65 857 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 858 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
293f5f65 859 CPU_SSE4_2_FLAGS, 0 },
8a2c8fef 860 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
293f5f65 861 CPU_AVX_FLAGS, 0 },
6c30d220 862 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
293f5f65 863 CPU_AVX2_FLAGS, 0 },
43234a1e 864 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
293f5f65 865 CPU_AVX512F_FLAGS, 0 },
43234a1e 866 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
293f5f65 867 CPU_AVX512CD_FLAGS, 0 },
43234a1e 868 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
293f5f65 869 CPU_AVX512ER_FLAGS, 0 },
43234a1e 870 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
293f5f65 871 CPU_AVX512PF_FLAGS, 0 },
1dfc6506 872 { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN,
293f5f65 873 CPU_AVX512DQ_FLAGS, 0 },
1dfc6506 874 { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
293f5f65 875 CPU_AVX512BW_FLAGS, 0 },
1dfc6506 876 { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
293f5f65 877 CPU_AVX512VL_FLAGS, 0 },
8a2c8fef 878 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
293f5f65 879 CPU_VMX_FLAGS, 0 },
8729a6f6 880 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
293f5f65 881 CPU_VMFUNC_FLAGS, 0 },
8a2c8fef 882 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
293f5f65 883 CPU_SMX_FLAGS, 0 },
8a2c8fef 884 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
293f5f65 885 CPU_XSAVE_FLAGS, 0 },
c7b8aa3a 886 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
293f5f65 887 CPU_XSAVEOPT_FLAGS, 0 },
1dfc6506 888 { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN,
293f5f65 889 CPU_XSAVEC_FLAGS, 0 },
1dfc6506 890 { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN,
293f5f65 891 CPU_XSAVES_FLAGS, 0 },
8a2c8fef 892 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
293f5f65 893 CPU_AES_FLAGS, 0 },
8a2c8fef 894 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
293f5f65 895 CPU_PCLMUL_FLAGS, 0 },
8a2c8fef 896 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
293f5f65 897 CPU_PCLMUL_FLAGS, 1 },
c7b8aa3a 898 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
293f5f65 899 CPU_FSGSBASE_FLAGS, 0 },
c7b8aa3a 900 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
293f5f65 901 CPU_RDRND_FLAGS, 0 },
c7b8aa3a 902 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
293f5f65 903 CPU_F16C_FLAGS, 0 },
6c30d220 904 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
293f5f65 905 CPU_BMI2_FLAGS, 0 },
8a2c8fef 906 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
293f5f65 907 CPU_FMA_FLAGS, 0 },
8a2c8fef 908 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
293f5f65 909 CPU_FMA4_FLAGS, 0 },
8a2c8fef 910 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
293f5f65 911 CPU_XOP_FLAGS, 0 },
8a2c8fef 912 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
293f5f65 913 CPU_LWP_FLAGS, 0 },
8a2c8fef 914 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
293f5f65 915 CPU_MOVBE_FLAGS, 0 },
60aa667e 916 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
293f5f65 917 CPU_CX16_FLAGS, 0 },
8a2c8fef 918 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
293f5f65 919 CPU_EPT_FLAGS, 0 },
6c30d220 920 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
293f5f65 921 CPU_LZCNT_FLAGS, 0 },
42164a71 922 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
293f5f65 923 CPU_HLE_FLAGS, 0 },
42164a71 924 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
293f5f65 925 CPU_RTM_FLAGS, 0 },
6c30d220 926 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
293f5f65 927 CPU_INVPCID_FLAGS, 0 },
8a2c8fef 928 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
293f5f65 929 CPU_CLFLUSH_FLAGS, 0 },
22109423 930 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
293f5f65 931 CPU_NOP_FLAGS, 0 },
8a2c8fef 932 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
293f5f65 933 CPU_SYSCALL_FLAGS, 0 },
8a2c8fef 934 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
293f5f65 935 CPU_RDTSCP_FLAGS, 0 },
8a2c8fef 936 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
293f5f65 937 CPU_3DNOW_FLAGS, 0 },
8a2c8fef 938 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
293f5f65 939 CPU_3DNOWA_FLAGS, 0 },
8a2c8fef 940 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
293f5f65 941 CPU_PADLOCK_FLAGS, 0 },
8a2c8fef 942 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
293f5f65 943 CPU_SVME_FLAGS, 1 },
8a2c8fef 944 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
293f5f65 945 CPU_SVME_FLAGS, 0 },
8a2c8fef 946 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
293f5f65 947 CPU_SSE4A_FLAGS, 0 },
8a2c8fef 948 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
293f5f65 949 CPU_ABM_FLAGS, 0 },
87973e9f 950 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
293f5f65 951 CPU_BMI_FLAGS, 0 },
2a2a0f38 952 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
293f5f65 953 CPU_TBM_FLAGS, 0 },
e2e1fcde 954 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
293f5f65 955 CPU_ADX_FLAGS, 0 },
e2e1fcde 956 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
293f5f65 957 CPU_RDSEED_FLAGS, 0 },
e2e1fcde 958 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
293f5f65 959 CPU_PRFCHW_FLAGS, 0 },
5c111e37 960 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
293f5f65 961 CPU_SMAP_FLAGS, 0 },
7e8b059b 962 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
293f5f65 963 CPU_MPX_FLAGS, 0 },
a0046408 964 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
293f5f65 965 CPU_SHA_FLAGS, 0 },
963f3586 966 { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN,
293f5f65 967 CPU_CLFLUSHOPT_FLAGS, 0 },
dcf893b5 968 { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN,
293f5f65 969 CPU_PREFETCHWT1_FLAGS, 0 },
2cf200a4 970 { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
293f5f65 971 CPU_SE1_FLAGS, 0 },
c5e7287a 972 { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN,
293f5f65 973 CPU_CLWB_FLAGS, 0 },
2cc1b5aa 974 { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
293f5f65 975 CPU_AVX512IFMA_FLAGS, 0 },
14f195c9 976 { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN,
293f5f65 977 CPU_AVX512VBMI_FLAGS, 0 },
920d2ddc
IT		 978 { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN,
979 CPU_AVX512_4FMAPS_FLAGS, 0 },
47acf0bd
IT		 980 { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN,
981 CPU_AVX512_4VNNIW_FLAGS, 0 },
620214f7
IT		 982 { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN,
983 CPU_AVX512_VPOPCNTDQ_FLAGS, 0 },
53467f57
IT		 984 { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN,
985 CPU_AVX512_VBMI2_FLAGS, 0 },
8cfcb765
IT		 986 { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN,
987 CPU_AVX512_VNNI_FLAGS, 0 },
ee6872be
IT		 988 { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN,
989 CPU_AVX512_BITALG_FLAGS, 0 },
029f3522 990 { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN,
293f5f65 991 CPU_CLZERO_FLAGS, 0 },
9916071f 992 { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN,
293f5f65 993 CPU_MWAITX_FLAGS, 0 },
8eab4136 994 { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN,
293f5f65 995 CPU_OSPKE_FLAGS, 0 },
8bc52696 996 { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN,
293f5f65 997 CPU_RDPID_FLAGS, 0 },
6b40c462
L		 998 { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN,
999 CPU_PTWRITE_FLAGS, 0 },
603555e5
L		 1000 { STRING_COMMA_LEN (".cet"), PROCESSOR_UNKNOWN,
1001 CPU_CET_FLAGS, 0 },
48521003
IT		 1002 { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN,
1003 CPU_GFNI_FLAGS, 0 },
8dcf1fad
IT		 1004 { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN,
1005 CPU_VAES_FLAGS, 0 },
ff1982d5
IT		 1006 { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN,
1007 CPU_VPCLMULQDQ_FLAGS, 0 },
293f5f65
L		 1008};
1009
1010static const noarch_entry cpu_noarch[] =
1011{
1012 { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS },
1848e567
L		 1013 { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS },
1014 { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS },
1015 { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS },
293f5f65
L		 1016 { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS },
1017 { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS },
1848e567
L		 1018 { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS },
1019 { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS },
1020 { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS },
1021 { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS },
1022 { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS },
1023 { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS },
293f5f65 1024 { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS },
1848e567 1025 { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS },
144b71e2
L		 1026 { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS },
1027 { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS },
1028 { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS },
1029 { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS },
1030 { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS },
1031 { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS },
1032 { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS },
1033 { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS },
1034 { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS },
920d2ddc 1035 { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS },
47acf0bd 1036 { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS },
620214f7 1037 { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS },
53467f57 1038 { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS },
8cfcb765 1039 { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS },
ee6872be 1040 { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS },
e413e4e9
AM		 1041};
1042
704209c0 1043#ifdef I386COFF
a6c24e68
NC		 1044/* Like s_lcomm_internal in gas/read.c but the alignment string
1045 is allowed to be optional. */
1046
1047static symbolS *
1048pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
1049{
1050 addressT align = 0;
1051
1052 SKIP_WHITESPACE ();
1053
7ab9ffdd 1054 if (needs_align
a6c24e68
NC		 1055 && *input_line_pointer == ',')
1056 {
1057 align = parse_align (needs_align - 1);
7ab9ffdd 1058
a6c24e68
NC		 1059 if (align == (addressT) -1)
1060 return NULL;
1061 }
1062 else
1063 {
1064 if (size >= 8)
1065 align = 3;
1066 else if (size >= 4)
1067 align = 2;
1068 else if (size >= 2)
1069 align = 1;
1070 else
1071 align = 0;
1072 }
1073
1074 bss_alloc (symbolP, size, align);
1075 return symbolP;
1076}
1077
704209c0 1078static void
a6c24e68
NC		 1079pe_lcomm (int needs_align)
1080{
1081 s_comm_internal (needs_align * 2, pe_lcomm_internal);
1082}
704209c0 1083#endif
a6c24e68 1084
29b0f896
AM		 1085const pseudo_typeS md_pseudo_table[] =
1086{
1087#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1088 {"align", s_align_bytes, 0},
1089#else
1090 {"align", s_align_ptwo, 0},
1091#endif
1092 {"arch", set_cpu_arch, 0},
1093#ifndef I386COFF
1094 {"bss", s_bss, 0},
a6c24e68
NC		 1095#else
1096 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 1097#endif
1098 {"ffloat", float_cons, 'f'},
1099 {"dfloat", float_cons, 'd'},
1100 {"tfloat", float_cons, 'x'},
1101 {"value", cons, 2},
d182319b 1102 {"slong", signed_cons, 4},
29b0f896
AM		 1103 {"noopt", s_ignore, 0},
1104 {"optim", s_ignore, 0},
1105 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
1106 {"code16", set_code_flag, CODE_16BIT},
1107 {"code32", set_code_flag, CODE_32BIT},
da5f19a2 1108#ifdef BFD64
29b0f896 1109 {"code64", set_code_flag, CODE_64BIT},
da5f19a2 1110#endif
29b0f896
AM		 1111 {"intel_syntax", set_intel_syntax, 1},
1112 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 1113 {"intel_mnemonic", set_intel_mnemonic, 1},
1114 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 1115 {"allow_index_reg", set_allow_index_reg, 1},
1116 {"disallow_index_reg", set_allow_index_reg, 0},
7bab8ab5
JB		 1117 {"sse_check", set_check, 0},
1118 {"operand_check", set_check, 1},
3b22753a
L		 1119#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1120 {"largecomm", handle_large_common, 0},
07a53e5c 1121#else
e3bb37b5 1122 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 1123 {"loc", dwarf2_directive_loc, 0},
1124 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 1125#endif
6482c264
NC		 1126#ifdef TE_PE
1127 {"secrel32", pe_directive_secrel, 0},
1128#endif
29b0f896
AM		 1129 {0, 0, 0}
1130};
1131
1132/* For interface with expression (). */
1133extern char *input_line_pointer;
1134
1135/* Hash table for instruction mnemonic lookup. */
1136static struct hash_control *op_hash;
1137
1138/* Hash table for register lookup. */
1139static struct hash_control *reg_hash;
1140\f
252b5132 1141void
e3bb37b5 1142i386_align_code (fragS *fragP, int count)
252b5132 1143{
ce8a8b2f
AM		 1144 /* Various efficient no-op patterns for aligning code labels.
1145 Note: Don't try to assemble the instructions in the comments.
1146 0L and 0w are not legal. */
bad6e36d 1147 static const unsigned char f32_1[] =
252b5132 1148 {0x90}; /* nop */
bad6e36d 1149 static const unsigned char f32_2[] =
ccc9c027 1150 {0x66,0x90}; /* xchg %ax,%ax */
bad6e36d 1151 static const unsigned char f32_3[] =
252b5132 1152 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
bad6e36d 1153 static const unsigned char f32_4[] =
252b5132 1154 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1155 static const unsigned char f32_5[] =
252b5132
RH		 1156 {0x90, /* nop */
1157 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
bad6e36d 1158 static const unsigned char f32_6[] =
252b5132 1159 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
bad6e36d 1160 static const unsigned char f32_7[] =
252b5132 1161 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1162 static const unsigned char f32_8[] =
252b5132
RH		 1163 {0x90, /* nop */
1164 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
bad6e36d 1165 static const unsigned char f32_9[] =
252b5132
RH		 1166 {0x89,0xf6, /* movl %esi,%esi */
1167 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1168 static const unsigned char f32_10[] =
252b5132
RH		 1169 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1170 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1171 static const unsigned char f32_11[] =
252b5132
RH		 1172 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1173 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1174 static const unsigned char f32_12[] =
252b5132
RH		 1175 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1176 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
bad6e36d 1177 static const unsigned char f32_13[] =
252b5132
RH		 1178 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1179 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1180 static const unsigned char f32_14[] =
252b5132
RH		 1181 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1182 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
bad6e36d 1183 static const unsigned char f16_3[] =
c3332e24 1184 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
bad6e36d 1185 static const unsigned char f16_4[] =
252b5132 1186 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1187 static const unsigned char f16_5[] =
252b5132
RH		 1188 {0x90, /* nop */
1189 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
bad6e36d 1190 static const unsigned char f16_6[] =
252b5132
RH		 1191 {0x89,0xf6, /* mov %si,%si */
1192 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1193 static const unsigned char f16_7[] =
252b5132
RH		 1194 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1195 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1196 static const unsigned char f16_8[] =
252b5132
RH		 1197 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1198 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
bad6e36d 1199 static const unsigned char jump_31[] =
76bc74dc
L		 1200 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1201 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1202 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1203 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
bad6e36d 1204 static const unsigned char *const f32_patt[] = {
252b5132 1205 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 1206 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132 1207 };
bad6e36d 1208 static const unsigned char *const f16_patt[] = {
76bc74dc 1209 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 1210 };
ccc9c027 1211 /* nopl (%[re]ax) */
bad6e36d 1212 static const unsigned char alt_3[] =
ccc9c027
L		 1213 {0x0f,0x1f,0x00};
1214 /* nopl 0(%[re]ax) */
bad6e36d 1215 static const unsigned char alt_4[] =
ccc9c027
L		 1216 {0x0f,0x1f,0x40,0x00};
1217 /* nopl 0(%[re]ax,%[re]ax,1) */
bad6e36d 1218 static const unsigned char alt_5[] =
ccc9c027
L		 1219 {0x0f,0x1f,0x44,0x00,0x00};
1220 /* nopw 0(%[re]ax,%[re]ax,1) */
bad6e36d 1221 static const unsigned char alt_6[] =
ccc9c027
L		 1222 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1223 /* nopl 0L(%[re]ax) */
bad6e36d 1224 static const unsigned char alt_7[] =
ccc9c027
L		 1225 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1226 /* nopl 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1227 static const unsigned char alt_8[] =
ccc9c027
L		 1228 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1229 /* nopw 0L(%[re]ax,%[re]ax,1) */
bad6e36d 1230 static const unsigned char alt_9[] =
ccc9c027
L		 1231 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1232 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
bad6e36d 1233 static const unsigned char alt_10[] =
ccc9c027 1234 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
bad6e36d 1235 static const unsigned char *const alt_patt[] = {
ccc9c027 1236 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
80b8656c 1237 alt_9, alt_10
ccc9c027 1238 };
252b5132 1239
76bc74dc
L		 1240 /* Only align for at least a positive non-zero boundary. */
1241 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 1242 return;
3e73aa7c 1243
ccc9c027
L		 1244 /* We need to decide which NOP sequence to use for 32bit and
1245 64bit. When -mtune= is used:
4eed87de 1246
76bc74dc
L		 1247 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1248 PROCESSOR_GENERIC32, f32_patt will be used.
80b8656c
L		 1249 2. For the rest, alt_patt will be used.
1250
1251 When -mtune= isn't used, alt_patt will be used if
22109423 1252 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
76bc74dc 1253 be used.
ccc9c027
L		 1254
1255 When -march= or .arch is used, we can't use anything beyond
1256 cpu_arch_isa_flags. */
1257
1258 if (flag_code == CODE_16BIT)
1259 {
ccc9c027 1260 if (count > 8)
33fef721 1261 {
76bc74dc
L		 1262 memcpy (fragP->fr_literal + fragP->fr_fix,
1263 jump_31, count);
1264 /* Adjust jump offset. */
1265 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 1266 }
76bc74dc
L		 1267 else
1268 memcpy (fragP->fr_literal + fragP->fr_fix,
1269 f16_patt[count - 1], count);
252b5132 1270 }
33fef721 1271 else
ccc9c027 1272 {
bad6e36d 1273 const unsigned char *const *patt = NULL;
ccc9c027 1274
fbf3f584 1275 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 1276 {
1277 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1278 switch (cpu_arch_tune)
1279 {
1280 case PROCESSOR_UNKNOWN:
1281 /* We use cpu_arch_isa_flags to check if we SHOULD
22109423
L		 1282 optimize with nops. */
1283 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1284 patt = alt_patt;
ccc9c027
L		 1285 else
1286 patt = f32_patt;
1287 break;
ccc9c027
L		 1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
ef05d495 1290 case PROCESSOR_CORE:
76bc74dc 1291 case PROCESSOR_CORE2:
bd5295b2 1292 case PROCESSOR_COREI7:
3632d14b 1293 case PROCESSOR_L1OM:
7a9068fe 1294 case PROCESSOR_K1OM:
76bc74dc 1295 case PROCESSOR_GENERIC64:
ccc9c027
L		 1296 case PROCESSOR_K6:
1297 case PROCESSOR_ATHLON:
1298 case PROCESSOR_K8:
4eed87de 1299 case PROCESSOR_AMDFAM10:
8aedb9fe 1300 case PROCESSOR_BD:
029f3522 1301 case PROCESSOR_ZNVER:
7b458c12 1302 case PROCESSOR_BT:
80b8656c 1303 patt = alt_patt;
ccc9c027 1304 break;
76bc74dc 1305 case PROCESSOR_I386:
ccc9c027
L		 1306 case PROCESSOR_I486:
1307 case PROCESSOR_PENTIUM:
2dde1948 1308 case PROCESSOR_PENTIUMPRO:
81486035 1309 case PROCESSOR_IAMCU:
ccc9c027
L		 1310 case PROCESSOR_GENERIC32:
1311 patt = f32_patt;
1312 break;
4eed87de 1313 }
ccc9c027
L		 1314 }
1315 else
1316 {
fbf3f584 1317 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1318 {
1319 case PROCESSOR_UNKNOWN:
e6a14101 1320 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1321 PROCESSOR_UNKNOWN. */
1322 abort ();
1323 break;
1324
76bc74dc 1325 case PROCESSOR_I386:
ccc9c027
L		 1326 case PROCESSOR_I486:
1327 case PROCESSOR_PENTIUM:
81486035 1328 case PROCESSOR_IAMCU:
ccc9c027
L		 1329 case PROCESSOR_K6:
1330 case PROCESSOR_ATHLON:
1331 case PROCESSOR_K8:
4eed87de 1332 case PROCESSOR_AMDFAM10:
8aedb9fe 1333 case PROCESSOR_BD:
029f3522 1334 case PROCESSOR_ZNVER:
7b458c12 1335 case PROCESSOR_BT:
ccc9c027
L		 1336 case PROCESSOR_GENERIC32:
1337 /* We use cpu_arch_isa_flags to check if we CAN optimize
22109423
L		 1338 with nops. */
1339 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1340 patt = alt_patt;
ccc9c027
L		 1341 else
1342 patt = f32_patt;
1343 break;
76bc74dc
L		 1344 case PROCESSOR_PENTIUMPRO:
1345 case PROCESSOR_PENTIUM4:
1346 case PROCESSOR_NOCONA:
1347 case PROCESSOR_CORE:
ef05d495 1348 case PROCESSOR_CORE2:
bd5295b2 1349 case PROCESSOR_COREI7:
3632d14b 1350 case PROCESSOR_L1OM:
7a9068fe 1351 case PROCESSOR_K1OM:
22109423 1352 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
80b8656c 1353 patt = alt_patt;
ccc9c027
L		 1354 else
1355 patt = f32_patt;
1356 break;
1357 case PROCESSOR_GENERIC64:
80b8656c 1358 patt = alt_patt;
ccc9c027 1359 break;
4eed87de 1360 }
ccc9c027
L		 1361 }
1362
76bc74dc
L		 1363 if (patt == f32_patt)
1364 {
1365 /* If the padding is less than 15 bytes, we use the normal
1366 ones. Otherwise, we use a jump instruction and adjust
711eedef
L		 1367 its offset. */
1368 int limit;
76ba9986 1369
711eedef
L		 1370 /* For 64bit, the limit is 3 bytes. */
1371 if (flag_code == CODE_64BIT
1372 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1373 limit = 3;
1374 else
1375 limit = 15;
1376 if (count < limit)
76bc74dc
L		 1377 memcpy (fragP->fr_literal + fragP->fr_fix,
1378 patt[count - 1], count);
1379 else
1380 {
1381 memcpy (fragP->fr_literal + fragP->fr_fix,
1382 jump_31, count);
1383 /* Adjust jump offset. */
1384 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1385 }
1386 }
1387 else
1388 {
80b8656c
L		 1389 /* Maximum length of an instruction is 10 byte. If the
1390 padding is greater than 10 bytes and we don't use jump,
76bc74dc
L		 1391 we have to break it into smaller pieces. */
1392 int padding = count;
80b8656c 1393 while (padding > 10)
76bc74dc 1394 {
80b8656c 1395 padding -= 10;
76bc74dc 1396 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
80b8656c 1397 patt [9], 10);
76bc74dc
L		 1398 }
1399
1400 if (padding)
1401 memcpy (fragP->fr_literal + fragP->fr_fix,
1402 patt [padding - 1], padding);
1403 }
ccc9c027 1404 }
33fef721 1405 fragP->fr_var = count;
252b5132
RH		 1406}
1407
c6fb90c8 1408static INLINE int
0dfbf9d7 1409operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1410{
0dfbf9d7 1411 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1412 {
1413 case 3:
0dfbf9d7 1414 if (x->array[2])
c6fb90c8 1415 return 0;
1a0670f3 1416 /* Fall through. */
c6fb90c8 1417 case 2:
0dfbf9d7 1418 if (x->array[1])
c6fb90c8 1419 return 0;
1a0670f3 1420 /* Fall through. */
c6fb90c8 1421 case 1:
0dfbf9d7 1422 return !x->array[0];
c6fb90c8
L		 1423 default:
1424 abort ();
1425 }
40fb9820
L		 1426}
1427
c6fb90c8 1428static INLINE void
0dfbf9d7 1429operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1430{
0dfbf9d7 1431 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1432 {
1433 case 3:
0dfbf9d7 1434 x->array[2] = v;
1a0670f3 1435 /* Fall through. */
c6fb90c8 1436 case 2:
0dfbf9d7 1437 x->array[1] = v;
1a0670f3 1438 /* Fall through. */
c6fb90c8 1439 case 1:
0dfbf9d7 1440 x->array[0] = v;
1a0670f3 1441 /* Fall through. */
c6fb90c8
L		 1442 break;
1443 default:
1444 abort ();
1445 }
1446}
40fb9820 1447
c6fb90c8 1448static INLINE int
0dfbf9d7
L		 1449operand_type_equal (const union i386_operand_type *x,
1450 const union i386_operand_type *y)
c6fb90c8 1451{
0dfbf9d7 1452 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1453 {
1454 case 3:
0dfbf9d7 1455 if (x->array[2] != y->array[2])
c6fb90c8 1456 return 0;
1a0670f3 1457 /* Fall through. */
c6fb90c8 1458 case 2:
0dfbf9d7 1459 if (x->array[1] != y->array[1])
c6fb90c8 1460 return 0;
1a0670f3 1461 /* Fall through. */
c6fb90c8 1462 case 1:
0dfbf9d7 1463 return x->array[0] == y->array[0];
c6fb90c8
L		 1464 break;
1465 default:
1466 abort ();
1467 }
1468}
40fb9820 1469
0dfbf9d7
L		 1470static INLINE int
1471cpu_flags_all_zero (const union i386_cpu_flags *x)
1472{
1473 switch (ARRAY_SIZE(x->array))
1474 {
53467f57
IT		 1475 case 4:
1476 if (x->array[3])
1477 return 0;
1478 /* Fall through. */
0dfbf9d7
L		 1479 case 3:
1480 if (x->array[2])
1481 return 0;
1a0670f3 1482 /* Fall through. */
0dfbf9d7
L		 1483 case 2:
1484 if (x->array[1])
1485 return 0;
1a0670f3 1486 /* Fall through. */
0dfbf9d7
L		 1487 case 1:
1488 return !x->array[0];
1489 default:
1490 abort ();
1491 }
1492}
1493
0dfbf9d7
L		 1494static INLINE int
1495cpu_flags_equal (const union i386_cpu_flags *x,
1496 const union i386_cpu_flags *y)
1497{
1498 switch (ARRAY_SIZE(x->array))
1499 {
53467f57
IT		 1500 case 4:
1501 if (x->array[3] != y->array[3])
1502 return 0;
1503 /* Fall through. */
0dfbf9d7
L		 1504 case 3:
1505 if (x->array[2] != y->array[2])
1506 return 0;
1a0670f3 1507 /* Fall through. */
0dfbf9d7
L		 1508 case 2:
1509 if (x->array[1] != y->array[1])
1510 return 0;
1a0670f3 1511 /* Fall through. */
0dfbf9d7
L		 1512 case 1:
1513 return x->array[0] == y->array[0];
1514 break;
1515 default:
1516 abort ();
1517 }
1518}
c6fb90c8
L		 1519
1520static INLINE int
1521cpu_flags_check_cpu64 (i386_cpu_flags f)
1522{
1523 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1524 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1525}
1526
c6fb90c8
L		 1527static INLINE i386_cpu_flags
1528cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1529{
c6fb90c8
L		 1530 switch (ARRAY_SIZE (x.array))
1531 {
53467f57
IT		 1532 case 4:
1533 x.array [3] &= y.array [3];
1534 /* Fall through. */
c6fb90c8
L		 1535 case 3:
1536 x.array [2] &= y.array [2];
1a0670f3 1537 /* Fall through. */
c6fb90c8
L		 1538 case 2:
1539 x.array [1] &= y.array [1];
1a0670f3 1540 /* Fall through. */
c6fb90c8
L		 1541 case 1:
1542 x.array [0] &= y.array [0];
1543 break;
1544 default:
1545 abort ();
1546 }
1547 return x;
1548}
40fb9820 1549
c6fb90c8
L		 1550static INLINE i386_cpu_flags
1551cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1552{
c6fb90c8 1553 switch (ARRAY_SIZE (x.array))
40fb9820 1554 {
53467f57
IT		 1555 case 4:
1556 x.array [3] |= y.array [3];
1557 /* Fall through. */
c6fb90c8
L		 1558 case 3:
1559 x.array [2] |= y.array [2];
1a0670f3 1560 /* Fall through. */
c6fb90c8
L		 1561 case 2:
1562 x.array [1] |= y.array [1];
1a0670f3 1563 /* Fall through. */
c6fb90c8
L		 1564 case 1:
1565 x.array [0] |= y.array [0];
40fb9820
L		 1566 break;
1567 default:
1568 abort ();
1569 }
40fb9820
L		 1570 return x;
1571}
1572
309d3373
JB		 1573static INLINE i386_cpu_flags
1574cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1575{
1576 switch (ARRAY_SIZE (x.array))
1577 {
53467f57
IT		 1578 case 4:
1579 x.array [3] &= ~y.array [3];
1580 /* Fall through. */
309d3373
JB		 1581 case 3:
1582 x.array [2] &= ~y.array [2];
1a0670f3 1583 /* Fall through. */
309d3373
JB		 1584 case 2:
1585 x.array [1] &= ~y.array [1];
1a0670f3 1586 /* Fall through. */
309d3373
JB		 1587 case 1:
1588 x.array [0] &= ~y.array [0];
1589 break;
1590 default:
1591 abort ();
1592 }
1593 return x;
1594}
1595
c0f3af97
L		 1596#define CPU_FLAGS_ARCH_MATCH 0x1
1597#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1598#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1599#define CPU_FLAGS_PCLMUL_MATCH 0x8
1600#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1601
a5ff0eb2 1602#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1603 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1604 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1605#define CPU_FLAGS_PERFECT_MATCH \
1606 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1607
1608/* Return CPU flags match bits. */
3629bb00 1609
40fb9820 1610static int
d3ce72d0 1611cpu_flags_match (const insn_template *t)
40fb9820 1612{
c0f3af97
L		 1613 i386_cpu_flags x = t->cpu_flags;
1614 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1615
1616 x.bitfield.cpu64 = 0;
1617 x.bitfield.cpuno64 = 0;
1618
0dfbf9d7 1619 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1620 {
1621 /* This instruction is available on all archs. */
1622 match |= CPU_FLAGS_32BIT_MATCH;
1623 }
3629bb00
L		 1624 else
1625 {
c0f3af97 1626 /* This instruction is available only on some archs. */
3629bb00
L		 1627 i386_cpu_flags cpu = cpu_arch_flags;
1628
3629bb00 1629 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1630 if (!cpu_flags_all_zero (&cpu))
1631 {
a5ff0eb2
L		 1632 if (x.bitfield.cpuavx)
1633 {
ce2f5b3c 1634 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1635 if (cpu.bitfield.cpuavx)
1636 {
1637 /* Check SSE2AVX. */
1638 if (!t->opcode_modifier.sse2avx|| sse2avx)
1639 {
1640 match |= (CPU_FLAGS_ARCH_MATCH
1641 | CPU_FLAGS_AVX_MATCH);
1642 /* Check AES. */
1643 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1644 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1645 /* Check PCLMUL. */
1646 if (!x.bitfield.cpupclmul
1647 || cpu.bitfield.cpupclmul)
1648 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1649 }
1650 }
1651 else
1652 match |= CPU_FLAGS_ARCH_MATCH;
1653 }
73b090a9
L		 1654 else if (x.bitfield.cpuavx512vl)
1655 {
1656 /* Match AVX512VL. */
1657 if (cpu.bitfield.cpuavx512vl)
1658 {
1659 /* Need another match. */
1660 cpu.bitfield.cpuavx512vl = 0;
1661 if (!cpu_flags_all_zero (&cpu))
1662 match |= CPU_FLAGS_32BIT_MATCH;
1663 else
1664 match |= CPU_FLAGS_ARCH_MATCH;
1665 }
1666 else
1667 match |= CPU_FLAGS_ARCH_MATCH;
1668 }
a5ff0eb2 1669 else
c0f3af97
L		 1670 match |= CPU_FLAGS_32BIT_MATCH;
1671 }
3629bb00 1672 }
c0f3af97 1673 return match;
40fb9820
L		 1674}
1675
c6fb90c8
L		 1676static INLINE i386_operand_type
1677operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1678{
c6fb90c8
L		 1679 switch (ARRAY_SIZE (x.array))
1680 {
1681 case 3:
1682 x.array [2] &= y.array [2];
1a0670f3 1683 /* Fall through. */
c6fb90c8
L		 1684 case 2:
1685 x.array [1] &= y.array [1];
1a0670f3 1686 /* Fall through. */
c6fb90c8
L		 1687 case 1:
1688 x.array [0] &= y.array [0];
1689 break;
1690 default:
1691 abort ();
1692 }
1693 return x;
40fb9820
L		 1694}
1695
c6fb90c8
L		 1696static INLINE i386_operand_type
1697operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1698{
c6fb90c8 1699 switch (ARRAY_SIZE (x.array))
40fb9820 1700 {
c6fb90c8
L		 1701 case 3:
1702 x.array [2] |= y.array [2];
1a0670f3 1703 /* Fall through. */
c6fb90c8
L		 1704 case 2:
1705 x.array [1] |= y.array [1];
1a0670f3 1706 /* Fall through. */
c6fb90c8
L		 1707 case 1:
1708 x.array [0] |= y.array [0];
40fb9820
L		 1709 break;
1710 default:
1711 abort ();
1712 }
c6fb90c8
L		 1713 return x;
1714}
40fb9820 1715
c6fb90c8
L		 1716static INLINE i386_operand_type
1717operand_type_xor (i386_operand_type x, i386_operand_type y)
1718{
1719 switch (ARRAY_SIZE (x.array))
1720 {
1721 case 3:
1722 x.array [2] ^= y.array [2];
1a0670f3 1723 /* Fall through. */
c6fb90c8
L		 1724 case 2:
1725 x.array [1] ^= y.array [1];
1a0670f3 1726 /* Fall through. */
c6fb90c8
L		 1727 case 1:
1728 x.array [0] ^= y.array [0];
1729 break;
1730 default:
1731 abort ();
1732 }
40fb9820
L		 1733 return x;
1734}
1735
1736static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1737static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1738static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1739static const i386_operand_type inoutportreg
1740 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1741static const i386_operand_type reg16_inoutportreg
1742 = OPERAND_TYPE_REG16_INOUTPORTREG;
1743static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1744static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1745static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1746static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1747static const i386_operand_type anydisp
1748 = OPERAND_TYPE_ANYDISP;
40fb9820 1749static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1750static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
43234a1e
L		 1751static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1752static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
40fb9820
L		 1753static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1754static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1755static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1756static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1757static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1758static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1759static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1760static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1761static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
a683cc34 1762static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
40fb9820
L		 1763
1764enum operand_type
1765{
1766 reg,
40fb9820
L		 1767 imm,
1768 disp,
1769 anymem
1770};
1771
c6fb90c8 1772static INLINE int
40fb9820
L		 1773operand_type_check (i386_operand_type t, enum operand_type c)
1774{
1775 switch (c)
1776 {
1777 case reg:
dc821c5f 1778 return t.bitfield.reg;
40fb9820 1779
40fb9820
L		 1780 case imm:
1781 return (t.bitfield.imm8
1782 || t.bitfield.imm8s
1783 || t.bitfield.imm16
1784 || t.bitfield.imm32
1785 || t.bitfield.imm32s
1786 || t.bitfield.imm64);
1787
1788 case disp:
1789 return (t.bitfield.disp8
1790 || t.bitfield.disp16
1791 || t.bitfield.disp32
1792 || t.bitfield.disp32s
1793 || t.bitfield.disp64);
1794
1795 case anymem:
1796 return (t.bitfield.disp8
1797 || t.bitfield.disp16
1798 || t.bitfield.disp32
1799 || t.bitfield.disp32s
1800 || t.bitfield.disp64
1801 || t.bitfield.baseindex);
1802
1803 default:
1804 abort ();
1805 }
2cfe26b6
AM		 1806
1807 return 0;
40fb9820
L		 1808}
1809
ca0d63fe 1810/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit on
5c07affc
L		 1811 operand J for instruction template T. */
1812
1813static INLINE int
d3ce72d0 1814match_reg_size (const insn_template *t, unsigned int j)
5c07affc
L		 1815{
1816 return !((i.types[j].bitfield.byte
1817 && !t->operand_types[j].bitfield.byte)
1818 || (i.types[j].bitfield.word
1819 && !t->operand_types[j].bitfield.word)
1820 || (i.types[j].bitfield.dword
1821 && !t->operand_types[j].bitfield.dword)
1822 || (i.types[j].bitfield.qword
ca0d63fe
JB		 1823 && !t->operand_types[j].bitfield.qword)
1824 || (i.types[j].bitfield.tbyte
1825 && !t->operand_types[j].bitfield.tbyte));
5c07affc
L		 1826}
1827
1b54b8d7
JB		 1828/* Return 1 if there is no conflict in SIMD register on
1829 operand J for instruction template T. */
1830
1831static INLINE int
1832match_simd_size (const insn_template *t, unsigned int j)
1833{
1834 return !((i.types[j].bitfield.xmmword
1835 && !t->operand_types[j].bitfield.xmmword)
1836 || (i.types[j].bitfield.ymmword
1837 && !t->operand_types[j].bitfield.ymmword)
1838 || (i.types[j].bitfield.zmmword
1839 && !t->operand_types[j].bitfield.zmmword));
1840}
1841
5c07affc
L		 1842/* Return 1 if there is no conflict in any size on operand J for
1843 instruction template T. */
1844
1845static INLINE int
d3ce72d0 1846match_mem_size (const insn_template *t, unsigned int j)
5c07affc
L		 1847{
1848 return (match_reg_size (t, j)
1849 && !((i.types[j].bitfield.unspecified
af508cb9 1850 && !i.broadcast
5c07affc
L		 1851 && !t->operand_types[j].bitfield.unspecified)
1852 || (i.types[j].bitfield.fword
1853 && !t->operand_types[j].bitfield.fword)
1b54b8d7
JB		 1854 /* For scalar opcode templates to allow register and memory
1855 operands at the same time, some special casing is needed
1856 here. */
1857 || ((t->operand_types[j].bitfield.regsimd
1858 && !t->opcode_modifier.broadcast
1859 && (t->operand_types[j].bitfield.dword
1860 || t->operand_types[j].bitfield.qword))
1861 ? (i.types[j].bitfield.xmmword
1862 || i.types[j].bitfield.ymmword
1863 || i.types[j].bitfield.zmmword)
1864 : !match_simd_size(t, j))));
5c07affc
L		 1865}
1866
1867/* Return 1 if there is no size conflict on any operands for
1868 instruction template T. */
1869
1870static INLINE int
d3ce72d0 1871operand_size_match (const insn_template *t)
5c07affc
L		 1872{
1873 unsigned int j;
1874 int match = 1;
1875
1876 /* Don't check jump instructions. */
1877 if (t->opcode_modifier.jump
1878 || t->opcode_modifier.jumpbyte
1879 || t->opcode_modifier.jumpdword
1880 || t->opcode_modifier.jumpintersegment)
1881 return match;
1882
1883 /* Check memory and accumulator operand size. */
1884 for (j = 0; j < i.operands; j++)
1885 {
1b54b8d7
JB		 1886 if (!i.types[j].bitfield.reg && !i.types[j].bitfield.regsimd
1887 && t->operand_types[j].bitfield.anysize)
5c07affc
L		 1888 continue;
1889
1b54b8d7 1890 if (t->operand_types[j].bitfield.reg
dc821c5f 1891 && !match_reg_size (t, j))
5c07affc
L		 1892 {
1893 match = 0;
1894 break;
1895 }
1896
1b54b8d7
JB		 1897 if (t->operand_types[j].bitfield.regsimd
1898 && !match_simd_size (t, j))
1899 {
1900 match = 0;
1901 break;
1902 }
1903
1904 if (t->operand_types[j].bitfield.acc
1905 && (!match_reg_size (t, j) || !match_simd_size (t, j)))
1906 {
1907 match = 0;
1908 break;
1909 }
1910
5c07affc
L		 1911 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1912 {
1913 match = 0;
1914 break;
1915 }
1916 }
1917
891edac4 1918 if (match)
5c07affc 1919 return match;
891edac4
L		 1920 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1921 {
1922mismatch:
86e026a4 1923 i.error = operand_size_mismatch;
891edac4
L		 1924 return 0;
1925 }
5c07affc
L		 1926
1927 /* Check reverse. */
9c2799c2 1928 gas_assert (i.operands == 2);
5c07affc
L		 1929
1930 match = 1;
1931 for (j = 0; j < 2; j++)
1932 {
dc821c5f
JB		 1933 if ((t->operand_types[j].bitfield.reg
1934 || t->operand_types[j].bitfield.acc)
5c07affc 1935 && !match_reg_size (t, j ? 0 : 1))
891edac4 1936 goto mismatch;
5c07affc
L		 1937
1938 if (i.types[j].bitfield.mem
1939 && !match_mem_size (t, j ? 0 : 1))
891edac4 1940 goto mismatch;
5c07affc
L		 1941 }
1942
1943 return match;
1944}
1945
c6fb90c8 1946static INLINE int
40fb9820
L		 1947operand_type_match (i386_operand_type overlap,
1948 i386_operand_type given)
1949{
1950 i386_operand_type temp = overlap;
1951
1952 temp.bitfield.jumpabsolute = 0;
7d5e4556 1953 temp.bitfield.unspecified = 0;
5c07affc
L		 1954 temp.bitfield.byte = 0;
1955 temp.bitfield.word = 0;
1956 temp.bitfield.dword = 0;
1957 temp.bitfield.fword = 0;
1958 temp.bitfield.qword = 0;
1959 temp.bitfield.tbyte = 0;
1960 temp.bitfield.xmmword = 0;
c0f3af97 1961 temp.bitfield.ymmword = 0;
43234a1e 1962 temp.bitfield.zmmword = 0;
0dfbf9d7 1963 if (operand_type_all_zero (&temp))
891edac4 1964 goto mismatch;
40fb9820 1965
891edac4
L		 1966 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1967 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1968 return 1;
1969
1970mismatch:
a65babc9 1971 i.error = operand_type_mismatch;
891edac4 1972 return 0;
40fb9820
L		 1973}
1974
7d5e4556 1975/* If given types g0 and g1 are registers they must be of the same type
dc821c5f 1976 unless the expected operand type register overlap is null. */
40fb9820 1977
c6fb90c8 1978static INLINE int
dc821c5f 1979operand_type_register_match (i386_operand_type g0,
40fb9820 1980 i386_operand_type t0,
40fb9820
L		 1981 i386_operand_type g1,
1982 i386_operand_type t1)
1983{
1984 if (!operand_type_check (g0, reg))
1985 return 1;
1986
1987 if (!operand_type_check (g1, reg))
1988 return 1;
1989
dc821c5f
JB		 1990 if (g0.bitfield.byte == g1.bitfield.byte
1991 && g0.bitfield.word == g1.bitfield.word
1992 && g0.bitfield.dword == g1.bitfield.dword
1993 && g0.bitfield.qword == g1.bitfield.qword)
40fb9820
L		 1994 return 1;
1995
dc821c5f
JB		 1996 if (!(t0.bitfield.byte & t1.bitfield.byte)
1997 && !(t0.bitfield.word & t1.bitfield.word)
1998 && !(t0.bitfield.dword & t1.bitfield.dword)
1999 && !(t0.bitfield.qword & t1.bitfield.qword))
891edac4
L		 2000 return 1;
2001
a65babc9 2002 i.error = register_type_mismatch;
891edac4
L		 2003
2004 return 0;
40fb9820
L		 2005}
2006
4c692bc7
JB		 2007static INLINE unsigned int
2008register_number (const reg_entry *r)
2009{
2010 unsigned int nr = r->reg_num;
2011
2012 if (r->reg_flags & RegRex)
2013 nr += 8;
2014
200cbe0f
L		 2015 if (r->reg_flags & RegVRex)
2016 nr += 16;
2017
4c692bc7
JB		 2018 return nr;
2019}
2020
252b5132 2021static INLINE unsigned int
40fb9820 2022mode_from_disp_size (i386_operand_type t)
252b5132 2023{
b5014f7a 2024 if (t.bitfield.disp8)
40fb9820
L		 2025 return 1;
2026 else if (t.bitfield.disp16
2027 || t.bitfield.disp32
2028 || t.bitfield.disp32s)
2029 return 2;
2030 else
2031 return 0;
252b5132
RH		 2032}
2033
2034static INLINE int
65879393 2035fits_in_signed_byte (addressT num)
252b5132 2036{
65879393 2037 return num + 0x80 <= 0xff;
47926f60 2038}
252b5132
RH		 2039
2040static INLINE int
65879393 2041fits_in_unsigned_byte (addressT num)
252b5132 2042{
65879393 2043 return num <= 0xff;
47926f60 2044}
252b5132
RH		 2045
2046static INLINE int
65879393 2047fits_in_unsigned_word (addressT num)
252b5132 2048{
65879393 2049 return num <= 0xffff;
47926f60 2050}
252b5132
RH		 2051
2052static INLINE int
65879393 2053fits_in_signed_word (addressT num)
252b5132 2054{
65879393 2055 return num + 0x8000 <= 0xffff;
47926f60 2056}
2a962e6d 2057
3e73aa7c 2058static INLINE int
65879393 2059fits_in_signed_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2060{
2061#ifndef BFD64
2062 return 1;
2063#else
65879393 2064 return num + 0x80000000 <= 0xffffffff;
3e73aa7c
JH		 2065#endif
2066} /* fits_in_signed_long() */
2a962e6d 2067
3e73aa7c 2068static INLINE int
65879393 2069fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 2070{
2071#ifndef BFD64
2072 return 1;
2073#else
65879393 2074 return num <= 0xffffffff;
3e73aa7c
JH		 2075#endif
2076} /* fits_in_unsigned_long() */
252b5132 2077
43234a1e 2078static INLINE int
b5014f7a 2079fits_in_disp8 (offsetT num)
43234a1e
L		 2080{
2081 int shift = i.memshift;
2082 unsigned int mask;
2083
2084 if (shift == -1)
2085 abort ();
2086
2087 mask = (1 << shift) - 1;
2088
2089 /* Return 0 if NUM isn't properly aligned. */
2090 if ((num & mask))
2091 return 0;
2092
2093 /* Check if NUM will fit in 8bit after shift. */
2094 return fits_in_signed_byte (num >> shift);
2095}
2096
a683cc34
SP		 2097static INLINE int
2098fits_in_imm4 (offsetT num)
2099{
2100 return (num & 0xf) == num;
2101}
2102
40fb9820 2103static i386_operand_type
e3bb37b5 2104smallest_imm_type (offsetT num)
252b5132 2105{
40fb9820 2106 i386_operand_type t;
7ab9ffdd 2107
0dfbf9d7 2108 operand_type_set (&t, 0);
40fb9820
L		 2109 t.bitfield.imm64 = 1;
2110
2111 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 2112 {
2113 /* This code is disabled on the 486 because all the Imm1 forms
2114 in the opcode table are slower on the i486. They're the
2115 versions with the implicitly specified single-position
2116 displacement, which has another syntax if you really want to
2117 use that form. */
40fb9820
L		 2118 t.bitfield.imm1 = 1;
2119 t.bitfield.imm8 = 1;
2120 t.bitfield.imm8s = 1;
2121 t.bitfield.imm16 = 1;
2122 t.bitfield.imm32 = 1;
2123 t.bitfield.imm32s = 1;
2124 }
2125 else if (fits_in_signed_byte (num))
2126 {
2127 t.bitfield.imm8 = 1;
2128 t.bitfield.imm8s = 1;
2129 t.bitfield.imm16 = 1;
2130 t.bitfield.imm32 = 1;
2131 t.bitfield.imm32s = 1;
2132 }
2133 else if (fits_in_unsigned_byte (num))
2134 {
2135 t.bitfield.imm8 = 1;
2136 t.bitfield.imm16 = 1;
2137 t.bitfield.imm32 = 1;
2138 t.bitfield.imm32s = 1;
2139 }
2140 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2141 {
2142 t.bitfield.imm16 = 1;
2143 t.bitfield.imm32 = 1;
2144 t.bitfield.imm32s = 1;
2145 }
2146 else if (fits_in_signed_long (num))
2147 {
2148 t.bitfield.imm32 = 1;
2149 t.bitfield.imm32s = 1;
2150 }
2151 else if (fits_in_unsigned_long (num))
2152 t.bitfield.imm32 = 1;
2153
2154 return t;
47926f60 2155}
252b5132 2156
847f7ad4 2157static offsetT
e3bb37b5 2158offset_in_range (offsetT val, int size)
847f7ad4 2159{
508866be 2160 addressT mask;
ba2adb93 2161
847f7ad4
AM		 2162 switch (size)
2163 {
508866be
L		 2164 case 1: mask = ((addressT) 1 << 8) - 1; break;
2165 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 2166 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 2167#ifdef BFD64
2168 case 8: mask = ((addressT) 2 << 63) - 1; break;
2169#endif
47926f60 2170 default: abort ();
847f7ad4
AM		 2171 }
2172
9de868bf
L		 2173#ifdef BFD64
2174 /* If BFD64, sign extend val for 32bit address mode. */
2175 if (flag_code != CODE_64BIT
2176 || i.prefix[ADDR_PREFIX])
3e73aa7c
JH		 2177 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2178 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
fa289fb8 2179#endif
ba2adb93 2180
47926f60 2181 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 2182 {
2183 char buf1[40], buf2[40];
2184
2185 sprint_value (buf1, val);
2186 sprint_value (buf2, val & mask);
2187 as_warn (_("%s shortened to %s"), buf1, buf2);
2188 }
2189 return val & mask;
2190}
2191
c32fa91d
L		 2192enum PREFIX_GROUP
2193{
2194 PREFIX_EXIST = 0,
2195 PREFIX_LOCK,
2196 PREFIX_REP,
04ef582a 2197 PREFIX_DS,
c32fa91d
L		 2198 PREFIX_OTHER
2199};
2200
2201/* Returns
2202 a. PREFIX_EXIST if attempting to add a prefix where one from the
2203 same class already exists.
2204 b. PREFIX_LOCK if lock prefix is added.
2205 c. PREFIX_REP if rep/repne prefix is added.
04ef582a
L		 2206 d. PREFIX_DS if ds prefix is added.
2207 e. PREFIX_OTHER if other prefix is added.
c32fa91d
L		 2208 */
2209
2210static enum PREFIX_GROUP
e3bb37b5 2211add_prefix (unsigned int prefix)
252b5132 2212{
c32fa91d 2213 enum PREFIX_GROUP ret = PREFIX_OTHER;
b1905489 2214 unsigned int q;
252b5132 2215
29b0f896
AM		 2216 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2217 && flag_code == CODE_64BIT)
b1905489 2218 {
161a04f6
L		 2219 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2220 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2221 && (prefix & (REX_R | REX_X | REX_B))))
c32fa91d 2222 ret = PREFIX_EXIST;
b1905489
JB		 2223 q = REX_PREFIX;
2224 }
3e73aa7c 2225 else
b1905489
JB		 2226 {
2227 switch (prefix)
2228 {
2229 default:
2230 abort ();
2231
b1905489 2232 case DS_PREFIX_OPCODE:
04ef582a
L		 2233 ret = PREFIX_DS;
2234 /* Fall through. */
2235 case CS_PREFIX_OPCODE:
b1905489
JB		 2236 case ES_PREFIX_OPCODE:
2237 case FS_PREFIX_OPCODE:
2238 case GS_PREFIX_OPCODE:
2239 case SS_PREFIX_OPCODE:
2240 q = SEG_PREFIX;
2241 break;
2242
2243 case REPNE_PREFIX_OPCODE:
2244 case REPE_PREFIX_OPCODE:
c32fa91d
L		 2245 q = REP_PREFIX;
2246 ret = PREFIX_REP;
2247 break;
2248
b1905489 2249 case LOCK_PREFIX_OPCODE:
c32fa91d
L		 2250 q = LOCK_PREFIX;
2251 ret = PREFIX_LOCK;
b1905489
JB		 2252 break;
2253
2254 case FWAIT_OPCODE:
2255 q = WAIT_PREFIX;
2256 break;
2257
2258 case ADDR_PREFIX_OPCODE:
2259 q = ADDR_PREFIX;
2260 break;
2261
2262 case DATA_PREFIX_OPCODE:
2263 q = DATA_PREFIX;
2264 break;
2265 }
2266 if (i.prefix[q] != 0)
c32fa91d 2267 ret = PREFIX_EXIST;
b1905489 2268 }
252b5132 2269
b1905489 2270 if (ret)
252b5132 2271 {
b1905489
JB		 2272 if (!i.prefix[q])
2273 ++i.prefixes;
2274 i.prefix[q] |= prefix;
252b5132 2275 }
b1905489
JB		 2276 else
2277 as_bad (_("same type of prefix used twice"));
252b5132 2278
252b5132
RH		 2279 return ret;
2280}
2281
2282static void
78f12dd3 2283update_code_flag (int value, int check)
eecb386c 2284{
78f12dd3
L		 2285 PRINTF_LIKE ((*as_error));
2286
1e9cc1c2 2287 flag_code = (enum flag_code) value;
40fb9820
L		 2288 if (flag_code == CODE_64BIT)
2289 {
2290 cpu_arch_flags.bitfield.cpu64 = 1;
2291 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 2292 }
2293 else
2294 {
2295 cpu_arch_flags.bitfield.cpu64 = 0;
2296 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 2297 }
2298 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c 2299 {
78f12dd3
L		 2300 if (check)
2301 as_error = as_fatal;
2302 else
2303 as_error = as_bad;
2304 (*as_error) (_("64bit mode not supported on `%s'."),
2305 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2306 }
40fb9820 2307 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c 2308 {
78f12dd3
L		 2309 if (check)
2310 as_error = as_fatal;
2311 else
2312 as_error = as_bad;
2313 (*as_error) (_("32bit mode not supported on `%s'."),
2314 cpu_arch_name ? cpu_arch_name : default_arch);
3e73aa7c 2315 }
eecb386c
AM		 2316 stackop_size = '\0';
2317}
2318
78f12dd3
L		 2319static void
2320set_code_flag (int value)
2321{
2322 update_code_flag (value, 0);
2323}
2324
eecb386c 2325static void
e3bb37b5 2326set_16bit_gcc_code_flag (int new_code_flag)
252b5132 2327{
1e9cc1c2 2328 flag_code = (enum flag_code) new_code_flag;
40fb9820
L		 2329 if (flag_code != CODE_16BIT)
2330 abort ();
2331 cpu_arch_flags.bitfield.cpu64 = 0;
2332 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 2333 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 2334}
2335
2336static void
e3bb37b5 2337set_intel_syntax (int syntax_flag)
252b5132
RH		 2338{
2339 /* Find out if register prefixing is specified. */
2340 int ask_naked_reg = 0;
2341
2342 SKIP_WHITESPACE ();
29b0f896 2343 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132 2344 {
d02603dc
NC		 2345 char *string;
2346 int e = get_symbol_name (&string);
252b5132 2347
47926f60 2348 if (strcmp (string, "prefix") == 0)
252b5132 2349 ask_naked_reg = 1;
47926f60 2350 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 2351 ask_naked_reg = -1;
2352 else
d0b47220 2353 as_bad (_("bad argument to syntax directive."));
d02603dc 2354 (void) restore_line_pointer (e);
252b5132
RH		 2355 }
2356 demand_empty_rest_of_line ();
c3332e24 2357
252b5132
RH		 2358 intel_syntax = syntax_flag;
2359
2360 if (ask_naked_reg == 0)
f86103b7
AM		 2361 allow_naked_reg = (intel_syntax
2362 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 2363 else
2364 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 2365
ee86248c 2366 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
7ab9ffdd 2367
e4a3b5a4 2368 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 2369 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 2370 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 2371}
2372
1efbbeb4
L		 2373static void
2374set_intel_mnemonic (int mnemonic_flag)
2375{
e1d4d893 2376 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 2377}
2378
db51cc60
L		 2379static void
2380set_allow_index_reg (int flag)
2381{
2382 allow_index_reg = flag;
2383}
2384
cb19c032 2385static void
7bab8ab5 2386set_check (int what)
cb19c032 2387{
7bab8ab5
JB		 2388 enum check_kind *kind;
2389 const char *str;
2390
2391 if (what)
2392 {
2393 kind = &operand_check;
2394 str = "operand";
2395 }
2396 else
2397 {
2398 kind = &sse_check;
2399 str = "sse";
2400 }
2401
cb19c032
L		 2402 SKIP_WHITESPACE ();
2403
2404 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2405 {
d02603dc
NC		 2406 char *string;
2407 int e = get_symbol_name (&string);
cb19c032
L		 2408
2409 if (strcmp (string, "none") == 0)
7bab8ab5 2410 *kind = check_none;
cb19c032 2411 else if (strcmp (string, "warning") == 0)
7bab8ab5 2412 *kind = check_warning;
cb19c032 2413 else if (strcmp (string, "error") == 0)
7bab8ab5 2414 *kind = check_error;
cb19c032 2415 else
7bab8ab5 2416 as_bad (_("bad argument to %s_check directive."), str);
d02603dc 2417 (void) restore_line_pointer (e);
cb19c032
L		 2418 }
2419 else
7bab8ab5 2420 as_bad (_("missing argument for %s_check directive"), str);
cb19c032
L		 2421
2422 demand_empty_rest_of_line ();
2423}
2424
8a9036a4
L		 2425static void
2426check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
1e9cc1c2 2427 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
8a9036a4
L		 2428{
2429#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2430 static const char *arch;
2431
2432 /* Intel LIOM is only supported on ELF. */
2433 if (!IS_ELF)
2434 return;
2435
2436 if (!arch)
2437 {
2438 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2439 use default_arch. */
2440 arch = cpu_arch_name;
2441 if (!arch)
2442 arch = default_arch;
2443 }
2444
81486035
L		 2445 /* If we are targeting Intel MCU, we must enable it. */
2446 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU
2447 || new_flag.bitfield.cpuiamcu)
2448 return;
2449
3632d14b 2450 /* If we are targeting Intel L1OM, we must enable it. */
8a9036a4 2451 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
1e9cc1c2 2452 || new_flag.bitfield.cpul1om)
8a9036a4 2453 return;
76ba9986 2454
7a9068fe
L		 2455 /* If we are targeting Intel K1OM, we must enable it. */
2456 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2457 || new_flag.bitfield.cpuk1om)
2458 return;
2459
8a9036a4
L		 2460 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2461#endif
2462}
2463
e413e4e9 2464static void
e3bb37b5 2465set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 2466{
47926f60 2467 SKIP_WHITESPACE ();
e413e4e9 2468
29b0f896 2469 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9 2470 {
d02603dc
NC		 2471 char *string;
2472 int e = get_symbol_name (&string);
91d6fa6a 2473 unsigned int j;
40fb9820 2474 i386_cpu_flags flags;
e413e4e9 2475
91d6fa6a 2476 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
e413e4e9 2477 {
91d6fa6a 2478 if (strcmp (string, cpu_arch[j].name) == 0)
e413e4e9 2479 {
91d6fa6a 2480 check_cpu_arch_compatible (string, cpu_arch[j].flags);
8a9036a4 2481
5c6af06e
JB		 2482 if (*string != '.')
2483 {
91d6fa6a 2484 cpu_arch_name = cpu_arch[j].name;
5c6af06e 2485 cpu_sub_arch_name = NULL;
91d6fa6a 2486 cpu_arch_flags = cpu_arch[j].flags;
40fb9820
L		 2487 if (flag_code == CODE_64BIT)
2488 {
2489 cpu_arch_flags.bitfield.cpu64 = 1;
2490 cpu_arch_flags.bitfield.cpuno64 = 0;
2491 }
2492 else
2493 {
2494 cpu_arch_flags.bitfield.cpu64 = 0;
2495 cpu_arch_flags.bitfield.cpuno64 = 1;
2496 }
91d6fa6a
NC		 2497 cpu_arch_isa = cpu_arch[j].type;
2498 cpu_arch_isa_flags = cpu_arch[j].flags;
ccc9c027
L		 2499 if (!cpu_arch_tune_set)
2500 {
2501 cpu_arch_tune = cpu_arch_isa;
2502 cpu_arch_tune_flags = cpu_arch_isa_flags;
2503 }
5c6af06e
JB		 2504 break;
2505 }
40fb9820 2506
293f5f65
L		 2507 flags = cpu_flags_or (cpu_arch_flags,
2508 cpu_arch[j].flags);
81486035 2509
5b64d091 2510 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 2511 {
6305a203
L		 2512 if (cpu_sub_arch_name)
2513 {
2514 char *name = cpu_sub_arch_name;
2515 cpu_sub_arch_name = concat (name,
91d6fa6a 2516 cpu_arch[j].name,
1bf57e9f 2517 (const char *) NULL);
6305a203
L		 2518 free (name);
2519 }
2520 else
91d6fa6a 2521 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
40fb9820 2522 cpu_arch_flags = flags;
a586129e 2523 cpu_arch_isa_flags = flags;
5c6af06e 2524 }
d02603dc 2525 (void) restore_line_pointer (e);
5c6af06e
JB		 2526 demand_empty_rest_of_line ();
2527 return;
e413e4e9
AM		 2528 }
2529 }
293f5f65
L		 2530
2531 if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
2532 {
33eaf5de 2533 /* Disable an ISA extension. */
293f5f65
L		 2534 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
2535 if (strcmp (string + 1, cpu_noarch [j].name) == 0)
2536 {
2537 flags = cpu_flags_and_not (cpu_arch_flags,
2538 cpu_noarch[j].flags);
2539 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2540 {
2541 if (cpu_sub_arch_name)
2542 {
2543 char *name = cpu_sub_arch_name;
2544 cpu_sub_arch_name = concat (name, string,
2545 (const char *) NULL);
2546 free (name);
2547 }
2548 else
2549 cpu_sub_arch_name = xstrdup (string);
2550 cpu_arch_flags = flags;
2551 cpu_arch_isa_flags = flags;
2552 }
2553 (void) restore_line_pointer (e);
2554 demand_empty_rest_of_line ();
2555 return;
2556 }
2557
2558 j = ARRAY_SIZE (cpu_arch);
2559 }
2560
91d6fa6a 2561 if (j >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2562 as_bad (_("no such architecture: `%s'"), string);
2563
2564 *input_line_pointer = e;
2565 }
2566 else
2567 as_bad (_("missing cpu architecture"));
2568
fddf5b5b
AM		 2569 no_cond_jump_promotion = 0;
2570 if (*input_line_pointer == ','
29b0f896 2571 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b 2572 {
d02603dc
NC		 2573 char *string;
2574 char e;
2575
2576 ++input_line_pointer;
2577 e = get_symbol_name (&string);
fddf5b5b
AM		 2578
2579 if (strcmp (string, "nojumps") == 0)
2580 no_cond_jump_promotion = 1;
2581 else if (strcmp (string, "jumps") == 0)
2582 ;
2583 else
2584 as_bad (_("no such architecture modifier: `%s'"), string);
2585
d02603dc 2586 (void) restore_line_pointer (e);
fddf5b5b
AM		 2587 }
2588
e413e4e9
AM		 2589 demand_empty_rest_of_line ();
2590}
2591
8a9036a4
L		 2592enum bfd_architecture
2593i386_arch (void)
2594{
3632d14b 2595 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4
L		 2596 {
2597 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2598 || flag_code != CODE_64BIT)
2599 as_fatal (_("Intel L1OM is 64bit ELF only"));
2600 return bfd_arch_l1om;
2601 }
7a9068fe
L		 2602 else if (cpu_arch_isa == PROCESSOR_K1OM)
2603 {
2604 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2605 || flag_code != CODE_64BIT)
2606 as_fatal (_("Intel K1OM is 64bit ELF only"));
2607 return bfd_arch_k1om;
2608 }
81486035
L		 2609 else if (cpu_arch_isa == PROCESSOR_IAMCU)
2610 {
2611 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2612 || flag_code == CODE_64BIT)
2613 as_fatal (_("Intel MCU is 32bit ELF only"));
2614 return bfd_arch_iamcu;
2615 }
8a9036a4
L		 2616 else
2617 return bfd_arch_i386;
2618}
2619
b9d79e03 2620unsigned long
7016a5d5 2621i386_mach (void)
b9d79e03 2622{
351f65ca 2623 if (!strncmp (default_arch, "x86_64", 6))
8a9036a4 2624 {
3632d14b 2625 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 2626 {
351f65ca
L		 2627 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2628 || default_arch[6] != '\0')
8a9036a4
L		 2629 as_fatal (_("Intel L1OM is 64bit ELF only"));
2630 return bfd_mach_l1om;
2631 }
7a9068fe
L		 2632 else if (cpu_arch_isa == PROCESSOR_K1OM)
2633 {
2634 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2635 || default_arch[6] != '\0')
2636 as_fatal (_("Intel K1OM is 64bit ELF only"));
2637 return bfd_mach_k1om;
2638 }
351f65ca 2639 else if (default_arch[6] == '\0')
8a9036a4 2640 return bfd_mach_x86_64;
351f65ca
L		 2641 else
2642 return bfd_mach_x64_32;
8a9036a4 2643 }
5197d474
L		 2644 else if (!strcmp (default_arch, "i386")
2645 || !strcmp (default_arch, "iamcu"))
81486035
L		 2646 {
2647 if (cpu_arch_isa == PROCESSOR_IAMCU)
2648 {
2649 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
2650 as_fatal (_("Intel MCU is 32bit ELF only"));
2651 return bfd_mach_i386_iamcu;
2652 }
2653 else
2654 return bfd_mach_i386_i386;
2655 }
b9d79e03 2656 else
2b5d6a91 2657 as_fatal (_("unknown architecture"));
b9d79e03 2658}
b9d79e03 2659\f
252b5132 2660void
7016a5d5 2661md_begin (void)
252b5132
RH		 2662{
2663 const char *hash_err;
2664
86fa6981
L		 2665 /* Support pseudo prefixes like {disp32}. */
2666 lex_type ['{'] = LEX_BEGIN_NAME;
2667
47926f60 2668 /* Initialize op_hash hash table. */
252b5132
RH		 2669 op_hash = hash_new ();
2670
2671 {
d3ce72d0 2672 const insn_template *optab;
29b0f896 2673 templates *core_optab;
252b5132 2674
47926f60
KH		 2675 /* Setup for loop. */
2676 optab = i386_optab;
add39d23 2677 core_optab = XNEW (templates);
252b5132
RH		 2678 core_optab->start = optab;
2679
2680 while (1)
2681 {
2682 ++optab;
2683 if (optab->name == NULL
2684 || strcmp (optab->name, (optab - 1)->name) != 0)
2685 {
2686 /* different name --> ship out current template list;
47926f60 2687 add to hash table; & begin anew. */
252b5132
RH		 2688 core_optab->end = optab;
2689 hash_err = hash_insert (op_hash,
2690 (optab - 1)->name,
5a49b8ac 2691 (void *) core_optab);
252b5132
RH		 2692 if (hash_err)
2693 {
b37df7c4 2694 as_fatal (_("can't hash %s: %s"),
252b5132
RH		 2695 (optab - 1)->name,
2696 hash_err);
2697 }
2698 if (optab->name == NULL)
2699 break;
add39d23 2700 core_optab = XNEW (templates);
252b5132
RH		 2701 core_optab->start = optab;
2702 }
2703 }
2704 }
2705
47926f60 2706 /* Initialize reg_hash hash table. */
252b5132
RH		 2707 reg_hash = hash_new ();
2708 {
29b0f896 2709 const reg_entry *regtab;
c3fe08fa 2710 unsigned int regtab_size = i386_regtab_size;
252b5132 2711
c3fe08fa 2712 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2713 {
5a49b8ac 2714 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2715 if (hash_err)
b37df7c4 2716 as_fatal (_("can't hash %s: %s"),
3e73aa7c
JH		 2717 regtab->reg_name,
2718 hash_err);
252b5132
RH		 2719 }
2720 }
2721
47926f60 2722 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2723 {
29b0f896
AM		 2724 int c;
2725 char *p;
252b5132
RH		 2726
2727 for (c = 0; c < 256; c++)
2728 {
3882b010 2729 if (ISDIGIT (c))
252b5132
RH		 2730 {
2731 digit_chars[c] = c;
2732 mnemonic_chars[c] = c;
2733 register_chars[c] = c;
2734 operand_chars[c] = c;
2735 }
3882b010 2736 else if (ISLOWER (c))
252b5132
RH		 2737 {
2738 mnemonic_chars[c] = c;
2739 register_chars[c] = c;
2740 operand_chars[c] = c;
2741 }
3882b010 2742 else if (ISUPPER (c))
252b5132 2743 {
3882b010 2744 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2745 register_chars[c] = mnemonic_chars[c];
2746 operand_chars[c] = c;
2747 }
43234a1e 2748 else if (c == '{' || c == '}')
86fa6981
L		 2749 {
2750 mnemonic_chars[c] = c;
2751 operand_chars[c] = c;
2752 }
252b5132 2753
3882b010 2754 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2755 identifier_chars[c] = c;
2756 else if (c >= 128)
2757 {
2758 identifier_chars[c] = c;
2759 operand_chars[c] = c;
2760 }
2761 }
2762
2763#ifdef LEX_AT
2764 identifier_chars['@'] = '@';
32137342
NC		 2765#endif
2766#ifdef LEX_QM
2767 identifier_chars['?'] = '?';
2768 operand_chars['?'] = '?';
252b5132 2769#endif
252b5132 2770 digit_chars['-'] = '-';
c0f3af97 2771 mnemonic_chars['_'] = '_';
791fe849 2772 mnemonic_chars['-'] = '-';
0003779b 2773 mnemonic_chars['.'] = '.';
252b5132
RH		 2774 identifier_chars['_'] = '_';
2775 identifier_chars['.'] = '.';
2776
2777 for (p = operand_special_chars; *p != '\0'; p++)
2778 operand_chars[(unsigned char) *p] = *p;
2779 }
2780
a4447b93
RH		 2781 if (flag_code == CODE_64BIT)
2782 {
ca19b261
KT		 2783#if defined (OBJ_COFF) && defined (TE_PE)
2784 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2785 ? 32 : 16);
2786#else
a4447b93 2787 x86_dwarf2_return_column = 16;
ca19b261 2788#endif
61ff971f 2789 x86_cie_data_alignment = -8;
a4447b93
RH		 2790 }
2791 else
2792 {
2793 x86_dwarf2_return_column = 8;
2794 x86_cie_data_alignment = -4;
2795 }
252b5132
RH		 2796}
2797
2798void
e3bb37b5 2799i386_print_statistics (FILE *file)
252b5132
RH		 2800{
2801 hash_print_statistics (file, "i386 opcode", op_hash);
2802 hash_print_statistics (file, "i386 register", reg_hash);
2803}
2804\f
252b5132
RH		 2805#ifdef DEBUG386
2806
ce8a8b2f 2807/* Debugging routines for md_assemble. */
d3ce72d0 2808static void pte (insn_template *);
40fb9820 2809static void pt (i386_operand_type);
e3bb37b5
L		 2810static void pe (expressionS *);
2811static void ps (symbolS *);
252b5132
RH		 2812
2813static void
e3bb37b5 2814pi (char *line, i386_insn *x)
252b5132 2815{
09137c09 2816 unsigned int j;
252b5132
RH		 2817
2818 fprintf (stdout, "%s: template ", line);
2819 pte (&x->tm);
09f131f2
JH		 2820 fprintf (stdout, " address: base %s index %s scale %x\n",
2821 x->base_reg ? x->base_reg->reg_name : "none",
2822 x->index_reg ? x->index_reg->reg_name : "none",
2823 x->log2_scale_factor);
2824 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2825 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2826 fprintf (stdout, " sib: base %x index %x scale %x\n",
2827 x->sib.base, x->sib.index, x->sib.scale);
2828 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2829 (x->rex & REX_W) != 0,
2830 (x->rex & REX_R) != 0,
2831 (x->rex & REX_X) != 0,
2832 (x->rex & REX_B) != 0);
09137c09 2833 for (j = 0; j < x->operands; j++)
252b5132 2834 {
09137c09
SP		 2835 fprintf (stdout, " #%d: ", j + 1);
2836 pt (x->types[j]);
252b5132 2837 fprintf (stdout, "\n");
dc821c5f 2838 if (x->types[j].bitfield.reg
09137c09 2839 || x->types[j].bitfield.regmmx
1b54b8d7 2840 || x->types[j].bitfield.regsimd
09137c09
SP		 2841 || x->types[j].bitfield.sreg2
2842 || x->types[j].bitfield.sreg3
2843 || x->types[j].bitfield.control
2844 || x->types[j].bitfield.debug
2845 || x->types[j].bitfield.test)
2846 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2847 if (operand_type_check (x->types[j], imm))
2848 pe (x->op[j].imms);
2849 if (operand_type_check (x->types[j], disp))
2850 pe (x->op[j].disps);
252b5132
RH		 2851 }
2852}
2853
2854static void
d3ce72d0 2855pte (insn_template *t)
252b5132 2856{
09137c09 2857 unsigned int j;
252b5132 2858 fprintf (stdout, " %d operands ", t->operands);
47926f60 2859 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2860 if (t->extension_opcode != None)
2861 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2862 if (t->opcode_modifier.d)
252b5132 2863 fprintf (stdout, "D");
40fb9820 2864 if (t->opcode_modifier.w)
252b5132
RH		 2865 fprintf (stdout, "W");
2866 fprintf (stdout, "\n");
09137c09 2867 for (j = 0; j < t->operands; j++)
252b5132 2868 {
09137c09
SP		 2869 fprintf (stdout, " #%d type ", j + 1);
2870 pt (t->operand_types[j]);
252b5132
RH		 2871 fprintf (stdout, "\n");
2872 }
2873}
2874
2875static void
e3bb37b5 2876pe (expressionS *e)
252b5132 2877{
24eab124 2878 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2879 fprintf (stdout, " add_number %ld (%lx)\n",
2880 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2881 if (e->X_add_symbol)
2882 {
2883 fprintf (stdout, " add_symbol ");
2884 ps (e->X_add_symbol);
2885 fprintf (stdout, "\n");
2886 }
2887 if (e->X_op_symbol)
2888 {
2889 fprintf (stdout, " op_symbol ");
2890 ps (e->X_op_symbol);
2891 fprintf (stdout, "\n");
2892 }
2893}
2894
2895static void
e3bb37b5 2896ps (symbolS *s)
252b5132
RH		 2897{
2898 fprintf (stdout, "%s type %s%s",
2899 S_GET_NAME (s),
2900 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2901 segment_name (S_GET_SEGMENT (s)));
2902}
2903
7b81dfbb 2904static struct type_name
252b5132 2905 {
40fb9820
L		 2906 i386_operand_type mask;
2907 const char *name;
252b5132 2908 }
7b81dfbb 2909const type_names[] =
252b5132 2910{
40fb9820
L		 2911 { OPERAND_TYPE_REG8, "r8" },
2912 { OPERAND_TYPE_REG16, "r16" },
2913 { OPERAND_TYPE_REG32, "r32" },
2914 { OPERAND_TYPE_REG64, "r64" },
2915 { OPERAND_TYPE_IMM8, "i8" },
2916 { OPERAND_TYPE_IMM8, "i8s" },
2917 { OPERAND_TYPE_IMM16, "i16" },
2918 { OPERAND_TYPE_IMM32, "i32" },
2919 { OPERAND_TYPE_IMM32S, "i32s" },
2920 { OPERAND_TYPE_IMM64, "i64" },
2921 { OPERAND_TYPE_IMM1, "i1" },
2922 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2923 { OPERAND_TYPE_DISP8, "d8" },
2924 { OPERAND_TYPE_DISP16, "d16" },
2925 { OPERAND_TYPE_DISP32, "d32" },
2926 { OPERAND_TYPE_DISP32S, "d32s" },
2927 { OPERAND_TYPE_DISP64, "d64" },
2928 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2929 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2930 { OPERAND_TYPE_CONTROL, "control reg" },
2931 { OPERAND_TYPE_TEST, "test reg" },
2932 { OPERAND_TYPE_DEBUG, "debug reg" },
2933 { OPERAND_TYPE_FLOATREG, "FReg" },
2934 { OPERAND_TYPE_FLOATACC, "FAcc" },
2935 { OPERAND_TYPE_SREG2, "SReg2" },
2936 { OPERAND_TYPE_SREG3, "SReg3" },
2937 { OPERAND_TYPE_ACC, "Acc" },
2938 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2939 { OPERAND_TYPE_REGMMX, "rMMX" },
2940 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2941 { OPERAND_TYPE_REGYMM, "rYMM" },
43234a1e
L		 2942 { OPERAND_TYPE_REGZMM, "rZMM" },
2943 { OPERAND_TYPE_REGMASK, "Mask reg" },
40fb9820 2944 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2945};
2946
2947static void
40fb9820 2948pt (i386_operand_type t)
252b5132 2949{
40fb9820 2950 unsigned int j;
c6fb90c8 2951 i386_operand_type a;
252b5132 2952
40fb9820 2953 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2954 {
2955 a = operand_type_and (t, type_names[j].mask);
0349dc08 2956 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2957 fprintf (stdout, "%s, ", type_names[j].name);
2958 }
252b5132
RH		 2959 fflush (stdout);
2960}
2961
2962#endif /* DEBUG386 */
2963\f
252b5132 2964static bfd_reloc_code_real_type
3956db08 2965reloc (unsigned int size,
64e74474
AM		 2966 int pcrel,
2967 int sign,
2968 bfd_reloc_code_real_type other)
252b5132 2969{
47926f60 2970 if (other != NO_RELOC)
3956db08 2971 {
91d6fa6a 2972 reloc_howto_type *rel;
3956db08
JB		 2973
2974 if (size == 8)
2975 switch (other)
2976 {
64e74474
AM		 2977 case BFD_RELOC_X86_64_GOT32:
2978 return BFD_RELOC_X86_64_GOT64;
2979 break;
553d1284
L		 2980 case BFD_RELOC_X86_64_GOTPLT64:
2981 return BFD_RELOC_X86_64_GOTPLT64;
2982 break;
64e74474
AM		 2983 case BFD_RELOC_X86_64_PLTOFF64:
2984 return BFD_RELOC_X86_64_PLTOFF64;
2985 break;
2986 case BFD_RELOC_X86_64_GOTPC32:
2987 other = BFD_RELOC_X86_64_GOTPC64;
2988 break;
2989 case BFD_RELOC_X86_64_GOTPCREL:
2990 other = BFD_RELOC_X86_64_GOTPCREL64;
2991 break;
2992 case BFD_RELOC_X86_64_TPOFF32:
2993 other = BFD_RELOC_X86_64_TPOFF64;
2994 break;
2995 case BFD_RELOC_X86_64_DTPOFF32:
2996 other = BFD_RELOC_X86_64_DTPOFF64;
2997 break;
2998 default:
2999 break;
3956db08 3000 }
e05278af 3001
8ce3d284 3002#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 3003 if (other == BFD_RELOC_SIZE32)
3004 {
3005 if (size == 8)
1ab668bf 3006 other = BFD_RELOC_SIZE64;
8fd4256d 3007 if (pcrel)
1ab668bf
AM		 3008 {
3009 as_bad (_("there are no pc-relative size relocations"));
3010 return NO_RELOC;
3011 }
8fd4256d 3012 }
8ce3d284 3013#endif
8fd4256d 3014
e05278af 3015 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
f2d8a97c 3016 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
e05278af
JB		 3017 sign = -1;
3018
91d6fa6a
NC		 3019 rel = bfd_reloc_type_lookup (stdoutput, other);
3020 if (!rel)
3956db08 3021 as_bad (_("unknown relocation (%u)"), other);
91d6fa6a 3022 else if (size != bfd_get_reloc_size (rel))
3956db08 3023 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
91d6fa6a 3024 bfd_get_reloc_size (rel),
3956db08 3025 size);
91d6fa6a 3026 else if (pcrel && !rel->pc_relative)
3956db08 3027 as_bad (_("non-pc-relative relocation for pc-relative field"));
91d6fa6a 3028 else if ((rel->complain_on_overflow == complain_overflow_signed
3956db08 3029 && !sign)
91d6fa6a 3030 || (rel->complain_on_overflow == complain_overflow_unsigned
64e74474 3031 && sign > 0))
3956db08
JB		 3032 as_bad (_("relocated field and relocation type differ in signedness"));
3033 else
3034 return other;
3035 return NO_RELOC;
3036 }
252b5132
RH		 3037
3038 if (pcrel)
3039 {
3e73aa7c 3040 if (!sign)
3956db08 3041 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 3042 switch (size)
3043 {
3044 case 1: return BFD_RELOC_8_PCREL;
3045 case 2: return BFD_RELOC_16_PCREL;
d258b828 3046 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 3047 case 8: return BFD_RELOC_64_PCREL;
252b5132 3048 }
3956db08 3049 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 3050 }
3051 else
3052 {
3956db08 3053 if (sign > 0)
e5cb08ac 3054 switch (size)
3e73aa7c
JH		 3055 {
3056 case 4: return BFD_RELOC_X86_64_32S;
3057 }
3058 else
3059 switch (size)
3060 {
3061 case 1: return BFD_RELOC_8;
3062 case 2: return BFD_RELOC_16;
3063 case 4: return BFD_RELOC_32;
3064 case 8: return BFD_RELOC_64;
3065 }
3956db08
JB		 3066 as_bad (_("cannot do %s %u byte relocation"),
3067 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 3068 }
3069
0cc9e1d3 3070 return NO_RELOC;
252b5132
RH		 3071}
3072
47926f60
KH		 3073/* Here we decide which fixups can be adjusted to make them relative to
3074 the beginning of the section instead of the symbol. Basically we need
3075 to make sure that the dynamic relocations are done correctly, so in
3076 some cases we force the original symbol to be used. */
3077
252b5132 3078int
e3bb37b5 3079tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 3080{
6d249963 3081#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 3082 if (!IS_ELF)
31312f95
AM		 3083 return 1;
3084
a161fe53
AM		 3085 /* Don't adjust pc-relative references to merge sections in 64-bit
3086 mode. */
3087 if (use_rela_relocations
3088 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
3089 && fixP->fx_pcrel)
252b5132 3090 return 0;
31312f95 3091
8d01d9a9
AJ		 3092 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3093 and changed later by validate_fix. */
3094 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
3095 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
3096 return 0;
3097
8fd4256d
L		 3098 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3099 for size relocations. */
3100 if (fixP->fx_r_type == BFD_RELOC_SIZE32
3101 || fixP->fx_r_type == BFD_RELOC_SIZE64
3102 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
252b5132
RH		 3103 || fixP->fx_r_type == BFD_RELOC_386_PLT32
3104 || fixP->fx_r_type == BFD_RELOC_386_GOT32
02a86693 3105 || fixP->fx_r_type == BFD_RELOC_386_GOT32X
13ae64f3
JJ		 3106 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
3107 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
3108 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
3109 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 3110 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
3111 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 3112 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
3113 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 3114 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
3115 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 3116 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
3117 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 3118 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
56ceb5b5
L		 3119 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX
3120 || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX
bffbf940
JJ		 3121 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
3122 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
3123 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 3124 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 3125 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
3126 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 3127 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
3128 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 3129 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
3130 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 3131 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
3132 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
3133 return 0;
31312f95 3134#endif
252b5132
RH		 3135 return 1;
3136}
252b5132 3137
b4cac588 3138static int
e3bb37b5 3139intel_float_operand (const char *mnemonic)
252b5132 3140{
9306ca4a
JB		 3141 /* Note that the value returned is meaningful only for opcodes with (memory)
3142 operands, hence the code here is free to improperly handle opcodes that
3143 have no operands (for better performance and smaller code). */
3144
3145 if (mnemonic[0] != 'f')
3146 return 0; /* non-math */
3147
3148 switch (mnemonic[1])
3149 {
3150 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3151 the fs segment override prefix not currently handled because no
3152 call path can make opcodes without operands get here */
3153 case 'i':
3154 return 2 /* integer op */;
3155 case 'l':
3156 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
3157 return 3; /* fldcw/fldenv */
3158 break;
3159 case 'n':
3160 if (mnemonic[2] != 'o' /* fnop */)
3161 return 3; /* non-waiting control op */
3162 break;
3163 case 'r':
3164 if (mnemonic[2] == 's')
3165 return 3; /* frstor/frstpm */
3166 break;
3167 case 's':
3168 if (mnemonic[2] == 'a')
3169 return 3; /* fsave */
3170 if (mnemonic[2] == 't')
3171 {
3172 switch (mnemonic[3])
3173 {
3174 case 'c': /* fstcw */
3175 case 'd': /* fstdw */
3176 case 'e': /* fstenv */
3177 case 's': /* fsts[gw] */
3178 return 3;
3179 }
3180 }
3181 break;
3182 case 'x':
3183 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3184 return 0; /* fxsave/fxrstor are not really math ops */
3185 break;
3186 }
252b5132 3187
9306ca4a 3188 return 1;
252b5132
RH		 3189}
3190
c0f3af97
L		 3191/* Build the VEX prefix. */
3192
3193static void
d3ce72d0 3194build_vex_prefix (const insn_template *t)
c0f3af97
L		 3195{
3196 unsigned int register_specifier;
3197 unsigned int implied_prefix;
3198 unsigned int vector_length;
3199
3200 /* Check register specifier. */
3201 if (i.vex.register_specifier)
43234a1e
L		 3202 {
3203 register_specifier =
3204 ~register_number (i.vex.register_specifier) & 0xf;
3205 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3206 }
c0f3af97
L		 3207 else
3208 register_specifier = 0xf;
3209
33eaf5de 3210 /* Use 2-byte VEX prefix by swapping destination and source
fa99fab2 3211 operand. */
86fa6981
L		 3212 if (i.vec_encoding != vex_encoding_vex3
3213 && i.dir_encoding == dir_encoding_default
fa99fab2 3214 && i.operands == i.reg_operands
7f399153 3215 && i.tm.opcode_modifier.vexopcode == VEX0F
86fa6981 3216 && i.tm.opcode_modifier.load
fa99fab2
L		 3217 && i.rex == REX_B)
3218 {
3219 unsigned int xchg = i.operands - 1;
3220 union i386_op temp_op;
3221 i386_operand_type temp_type;
3222
3223 temp_type = i.types[xchg];
3224 i.types[xchg] = i.types[0];
3225 i.types[0] = temp_type;
3226 temp_op = i.op[xchg];
3227 i.op[xchg] = i.op[0];
3228 i.op[0] = temp_op;
3229
9c2799c2 3230 gas_assert (i.rm.mode == 3);
fa99fab2
L		 3231
3232 i.rex = REX_R;
3233 xchg = i.rm.regmem;
3234 i.rm.regmem = i.rm.reg;
3235 i.rm.reg = xchg;
3236
3237 /* Use the next insn. */
3238 i.tm = t[1];
3239 }
3240
539f890d
L		 3241 if (i.tm.opcode_modifier.vex == VEXScalar)
3242 vector_length = avxscalar;
3243 else
3244 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
c0f3af97
L		 3245
3246 switch ((i.tm.base_opcode >> 8) & 0xff)
3247 {
3248 case 0:
3249 implied_prefix = 0;
3250 break;
3251 case DATA_PREFIX_OPCODE:
3252 implied_prefix = 1;
3253 break;
3254 case REPE_PREFIX_OPCODE:
3255 implied_prefix = 2;
3256 break;
3257 case REPNE_PREFIX_OPCODE:
3258 implied_prefix = 3;
3259 break;
3260 default:
3261 abort ();
3262 }
3263
3264 /* Use 2-byte VEX prefix if possible. */
86fa6981
L		 3265 if (i.vec_encoding != vex_encoding_vex3
3266 && i.tm.opcode_modifier.vexopcode == VEX0F
04251de0 3267 && i.tm.opcode_modifier.vexw != VEXW1
c0f3af97
L		 3268 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3269 {
3270 /* 2-byte VEX prefix. */
3271 unsigned int r;
3272
3273 i.vex.length = 2;
3274 i.vex.bytes[0] = 0xc5;
3275
3276 /* Check the REX.R bit. */
3277 r = (i.rex & REX_R) ? 0 : 1;
3278 i.vex.bytes[1] = (r << 7
3279 | register_specifier << 3
3280 | vector_length << 2
3281 | implied_prefix);
3282 }
3283 else
3284 {
3285 /* 3-byte VEX prefix. */
3286 unsigned int m, w;
3287
f88c9eb0 3288 i.vex.length = 3;
f88c9eb0 3289
7f399153 3290 switch (i.tm.opcode_modifier.vexopcode)
5dd85c99 3291 {
7f399153
L		 3292 case VEX0F:
3293 m = 0x1;
80de6e00 3294 i.vex.bytes[0] = 0xc4;
7f399153
L		 3295 break;
3296 case VEX0F38:
3297 m = 0x2;
80de6e00 3298 i.vex.bytes[0] = 0xc4;
7f399153
L		 3299 break;
3300 case VEX0F3A:
3301 m = 0x3;
80de6e00 3302 i.vex.bytes[0] = 0xc4;
7f399153
L		 3303 break;
3304 case XOP08:
5dd85c99
SP		 3305 m = 0x8;
3306 i.vex.bytes[0] = 0x8f;
7f399153
L		 3307 break;
3308 case XOP09:
f88c9eb0
SP		 3309 m = 0x9;
3310 i.vex.bytes[0] = 0x8f;
7f399153
L		 3311 break;
3312 case XOP0A:
f88c9eb0
SP		 3313 m = 0xa;
3314 i.vex.bytes[0] = 0x8f;
7f399153
L		 3315 break;
3316 default:
3317 abort ();
f88c9eb0 3318 }
c0f3af97 3319
c0f3af97
L		 3320 /* The high 3 bits of the second VEX byte are 1's compliment
3321 of RXB bits from REX. */
3322 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3323
3324 /* Check the REX.W bit. */
3325 w = (i.rex & REX_W) ? 1 : 0;
b28d1bda
IT		 3326 if (i.tm.opcode_modifier.vexw == VEXW1)
3327 w = 1;
c0f3af97
L		 3328
3329 i.vex.bytes[2] = (w << 7
3330 | register_specifier << 3
3331 | vector_length << 2
3332 | implied_prefix);
3333 }
3334}
3335
43234a1e
L		 3336/* Build the EVEX prefix. */
3337
3338static void
3339build_evex_prefix (void)
3340{
3341 unsigned int register_specifier;
3342 unsigned int implied_prefix;
3343 unsigned int m, w;
3344 rex_byte vrex_used = 0;
3345
3346 /* Check register specifier. */
3347 if (i.vex.register_specifier)
3348 {
3349 gas_assert ((i.vrex & REX_X) == 0);
3350
3351 register_specifier = i.vex.register_specifier->reg_num;
3352 if ((i.vex.register_specifier->reg_flags & RegRex))
3353 register_specifier += 8;
3354 /* The upper 16 registers are encoded in the fourth byte of the
3355 EVEX prefix. */
3356 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3357 i.vex.bytes[3] = 0x8;
3358 register_specifier = ~register_specifier & 0xf;
3359 }
3360 else
3361 {
3362 register_specifier = 0xf;
3363
3364 /* Encode upper 16 vector index register in the fourth byte of
3365 the EVEX prefix. */
3366 if (!(i.vrex & REX_X))
3367 i.vex.bytes[3] = 0x8;
3368 else
3369 vrex_used |= REX_X;
3370 }
3371
3372 switch ((i.tm.base_opcode >> 8) & 0xff)
3373 {
3374 case 0:
3375 implied_prefix = 0;
3376 break;
3377 case DATA_PREFIX_OPCODE:
3378 implied_prefix = 1;
3379 break;
3380 case REPE_PREFIX_OPCODE:
3381 implied_prefix = 2;
3382 break;
3383 case REPNE_PREFIX_OPCODE:
3384 implied_prefix = 3;
3385 break;
3386 default:
3387 abort ();
3388 }
3389
3390 /* 4 byte EVEX prefix. */
3391 i.vex.length = 4;
3392 i.vex.bytes[0] = 0x62;
3393
3394 /* mmmm bits. */
3395 switch (i.tm.opcode_modifier.vexopcode)
3396 {
3397 case VEX0F:
3398 m = 1;
3399 break;
3400 case VEX0F38:
3401 m = 2;
3402 break;
3403 case VEX0F3A:
3404 m = 3;
3405 break;
3406 default:
3407 abort ();
3408 break;
3409 }
3410
3411 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3412 bits from REX. */
3413 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3414
3415 /* The fifth bit of the second EVEX byte is 1's compliment of the
3416 REX_R bit in VREX. */
3417 if (!(i.vrex & REX_R))
3418 i.vex.bytes[1] |= 0x10;
3419 else
3420 vrex_used |= REX_R;
3421
3422 if ((i.reg_operands + i.imm_operands) == i.operands)
3423 {
3424 /* When all operands are registers, the REX_X bit in REX is not
3425 used. We reuse it to encode the upper 16 registers, which is
3426 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3427 as 1's compliment. */
3428 if ((i.vrex & REX_B))
3429 {
3430 vrex_used |= REX_B;
3431 i.vex.bytes[1] &= ~0x40;
3432 }
3433 }
3434
3435 /* EVEX instructions shouldn't need the REX prefix. */
3436 i.vrex &= ~vrex_used;
3437 gas_assert (i.vrex == 0);
3438
3439 /* Check the REX.W bit. */
3440 w = (i.rex & REX_W) ? 1 : 0;
3441 if (i.tm.opcode_modifier.vexw)
3442 {
3443 if (i.tm.opcode_modifier.vexw == VEXW1)
3444 w = 1;
3445 }
3446 /* If w is not set it means we are dealing with WIG instruction. */
3447 else if (!w)
3448 {
3449 if (evexwig == evexw1)
3450 w = 1;
3451 }
3452
3453 /* Encode the U bit. */
3454 implied_prefix |= 0x4;
3455
3456 /* The third byte of the EVEX prefix. */
3457 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3458
3459 /* The fourth byte of the EVEX prefix. */
3460 /* The zeroing-masking bit. */
3461 if (i.mask && i.mask->zeroing)
3462 i.vex.bytes[3] |= 0x80;
3463
3464 /* Don't always set the broadcast bit if there is no RC. */
3465 if (!i.rounding)
3466 {
3467 /* Encode the vector length. */
3468 unsigned int vec_length;
3469
3470 switch (i.tm.opcode_modifier.evex)
3471 {
3472 case EVEXLIG: /* LL' is ignored */
3473 vec_length = evexlig << 5;
3474 break;
3475 case EVEX128:
3476 vec_length = 0 << 5;
3477 break;
3478 case EVEX256:
3479 vec_length = 1 << 5;
3480 break;
3481 case EVEX512:
3482 vec_length = 2 << 5;
3483 break;
3484 default:
3485 abort ();
3486 break;
3487 }
3488 i.vex.bytes[3] |= vec_length;
3489 /* Encode the broadcast bit. */
3490 if (i.broadcast)
3491 i.vex.bytes[3] |= 0x10;
3492 }
3493 else
3494 {
3495 if (i.rounding->type != saeonly)
3496 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3497 else
d3d3c6db 3498 i.vex.bytes[3] |= 0x10 | (evexrcig << 5);
43234a1e
L		 3499 }
3500
3501 if (i.mask && i.mask->mask)
3502 i.vex.bytes[3] |= i.mask->mask->reg_num;
3503}
3504
65da13b5
L		 3505static void
3506process_immext (void)
3507{
3508 expressionS *exp;
3509
4c692bc7
JB		 3510 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3511 && i.operands > 0)
65da13b5 3512 {
4c692bc7
JB		 3513 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3514 with an opcode suffix which is coded in the same place as an
3515 8-bit immediate field would be.
3516 Here we check those operands and remove them afterwards. */
65da13b5
L		 3517 unsigned int x;
3518
3519 for (x = 0; x < i.operands; x++)
4c692bc7 3520 if (register_number (i.op[x].regs) != x)
65da13b5 3521 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 3522 register_prefix, i.op[x].regs->reg_name, x + 1,
3523 i.tm.name);
3524
3525 i.operands = 0;
65da13b5
L		 3526 }
3527
9916071f
AP		 3528 if (i.tm.cpu_flags.bitfield.cpumwaitx && i.operands > 0)
3529 {
3530 /* MONITORX/MWAITX instructions have fixed operands with an opcode
3531 suffix which is coded in the same place as an 8-bit immediate
3532 field would be.
3533 Here we check those operands and remove them afterwards. */
3534 unsigned int x;
3535
3536 if (i.operands != 3)
3537 abort();
3538
3539 for (x = 0; x < 2; x++)
3540 if (register_number (i.op[x].regs) != x)
3541 goto bad_register_operand;
3542
3543 /* Check for third operand for mwaitx/monitorx insn. */
3544 if (register_number (i.op[x].regs)
3545 != (x + (i.tm.extension_opcode == 0xfb)))
3546 {
3547bad_register_operand:
3548 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3549 register_prefix, i.op[x].regs->reg_name, x+1,
3550 i.tm.name);
3551 }
3552
3553 i.operands = 0;
3554 }
3555
c0f3af97 3556 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 3557 which is coded in the same place as an 8-bit immediate field
3558 would be. Here we fake an 8-bit immediate operand from the
3559 opcode suffix stored in tm.extension_opcode.
3560
c1e679ec 3561 AVX instructions also use this encoding, for some of
c0f3af97 3562 3 argument instructions. */
65da13b5 3563
43234a1e 3564 gas_assert (i.imm_operands <= 1
7ab9ffdd 3565 && (i.operands <= 2
43234a1e
L		 3566 || ((i.tm.opcode_modifier.vex
3567 || i.tm.opcode_modifier.evex)
7ab9ffdd 3568 && i.operands <= 4)));
65da13b5
L		 3569
3570 exp = &im_expressions[i.imm_operands++];
3571 i.op[i.operands].imms = exp;
3572 i.types[i.operands] = imm8;
3573 i.operands++;
3574 exp->X_op = O_constant;
3575 exp->X_add_number = i.tm.extension_opcode;
3576 i.tm.extension_opcode = None;
3577}
3578
42164a71
L		 3579
3580static int
3581check_hle (void)
3582{
3583 switch (i.tm.opcode_modifier.hleprefixok)
3584 {
3585 default:
3586 abort ();
82c2def5 3587 case HLEPrefixNone:
165de32a
L		 3588 as_bad (_("invalid instruction `%s' after `%s'"),
3589 i.tm.name, i.hle_prefix);
42164a71 3590 return 0;
82c2def5 3591 case HLEPrefixLock:
42164a71
L		 3592 if (i.prefix[LOCK_PREFIX])
3593 return 1;
165de32a 3594 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
42164a71 3595 return 0;
82c2def5 3596 case HLEPrefixAny:
42164a71 3597 return 1;
82c2def5 3598 case HLEPrefixRelease:
42164a71
L		 3599 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3600 {
3601 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3602 i.tm.name);
3603 return 0;
3604 }
3605 if (i.mem_operands == 0
3606 || !operand_type_check (i.types[i.operands - 1], anymem))
3607 {
3608 as_bad (_("memory destination needed for instruction `%s'"
3609 " after `xrelease'"), i.tm.name);
3610 return 0;
3611 }
3612 return 1;
3613 }
3614}
3615
252b5132
RH		 3616/* This is the guts of the machine-dependent assembler. LINE points to a
3617 machine dependent instruction. This function is supposed to emit
3618 the frags/bytes it assembles to. */
3619
3620void
65da13b5 3621md_assemble (char *line)
252b5132 3622{
40fb9820 3623 unsigned int j;
83b16ac6 3624 char mnemonic[MAX_MNEM_SIZE], mnem_suffix;
d3ce72d0 3625 const insn_template *t;
252b5132 3626
47926f60 3627 /* Initialize globals. */
252b5132
RH		 3628 memset (&i, '\0', sizeof (i));
3629 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 3630 i.reloc[j] = NO_RELOC;
252b5132
RH		 3631 memset (disp_expressions, '\0', sizeof (disp_expressions));
3632 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 3633 save_stack_p = save_stack;
252b5132
RH		 3634
3635 /* First parse an instruction mnemonic & call i386_operand for the operands.
3636 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 3637 start of a (possibly prefixed) mnemonic. */
252b5132 3638
29b0f896
AM		 3639 line = parse_insn (line, mnemonic);
3640 if (line == NULL)
3641 return;
83b16ac6 3642 mnem_suffix = i.suffix;
252b5132 3643
29b0f896 3644 line = parse_operands (line, mnemonic);
ee86248c 3645 this_operand = -1;
8325cc63
JB		 3646 xfree (i.memop1_string);
3647 i.memop1_string = NULL;
29b0f896
AM		 3648 if (line == NULL)
3649 return;
252b5132 3650
29b0f896
AM		 3651 /* Now we've parsed the mnemonic into a set of templates, and have the
3652 operands at hand. */
3653
3654 /* All intel opcodes have reversed operands except for "bound" and
3655 "enter". We also don't reverse intersegment "jmp" and "call"
3656 instructions with 2 immediate operands so that the immediate segment
050dfa73 3657 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 3658 if (intel_syntax
3659 && i.operands > 1
29b0f896 3660 && (strcmp (mnemonic, "bound") != 0)
30123838 3661 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 3662 && !(operand_type_check (i.types[0], imm)
3663 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 3664 swap_operands ();
3665
ec56d5c0
JB		 3666 /* The order of the immediates should be reversed
3667 for 2 immediates extrq and insertq instructions */
3668 if (i.imm_operands == 2
3669 && (strcmp (mnemonic, "extrq") == 0
3670 || strcmp (mnemonic, "insertq") == 0))
3671 swap_2_operands (0, 1);
3672
29b0f896
AM		 3673 if (i.imm_operands)
3674 optimize_imm ();
3675
b300c311
L		 3676 /* Don't optimize displacement for movabs since it only takes 64bit
3677 displacement. */
3678 if (i.disp_operands
a501d77e 3679 && i.disp_encoding != disp_encoding_32bit
862be3fb
L		 3680 && (flag_code != CODE_64BIT
3681 || strcmp (mnemonic, "movabs") != 0))
3682 optimize_disp ();
29b0f896
AM		 3683
3684 /* Next, we find a template that matches the given insn,
3685 making sure the overlap of the given operands types is consistent
3686 with the template operand types. */
252b5132 3687
83b16ac6 3688 if (!(t = match_template (mnem_suffix)))
29b0f896 3689 return;
252b5132 3690
7bab8ab5 3691 if (sse_check != check_none
81f8a913 3692 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 3693 && (i.tm.cpu_flags.bitfield.cpusse
3694 || i.tm.cpu_flags.bitfield.cpusse2
3695 || i.tm.cpu_flags.bitfield.cpusse3
3696 || i.tm.cpu_flags.bitfield.cpussse3
3697 || i.tm.cpu_flags.bitfield.cpusse4_1
3698 || i.tm.cpu_flags.bitfield.cpusse4_2))
3699 {
7bab8ab5 3700 (sse_check == check_warning
daf50ae7
L		 3701 ? as_warn
3702 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3703 }
3704
321fd21e
L		 3705 /* Zap movzx and movsx suffix. The suffix has been set from
3706 "word ptr" or "byte ptr" on the source operand in Intel syntax
3707 or extracted from mnemonic in AT&T syntax. But we'll use
3708 the destination register to choose the suffix for encoding. */
3709 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 3710 {
321fd21e
L		 3711 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3712 there is no suffix, the default will be byte extension. */
3713 if (i.reg_operands != 2
3714 && !i.suffix
7ab9ffdd 3715 && intel_syntax)
321fd21e
L		 3716 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3717
3718 i.suffix = 0;
cd61ebfe 3719 }
24eab124 3720
40fb9820 3721 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 3722 if (!add_prefix (FWAIT_OPCODE))
3723 return;
252b5132 3724
d5de92cf
L		 3725 /* Check if REP prefix is OK. */
3726 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3727 {
3728 as_bad (_("invalid instruction `%s' after `%s'"),
3729 i.tm.name, i.rep_prefix);
3730 return;
3731 }
3732
c1ba0266
L		 3733 /* Check for lock without a lockable instruction. Destination operand
3734 must be memory unless it is xchg (0x86). */
c32fa91d
L		 3735 if (i.prefix[LOCK_PREFIX]
3736 && (!i.tm.opcode_modifier.islockable
c1ba0266
L		 3737 || i.mem_operands == 0
3738 || (i.tm.base_opcode != 0x86
3739 && !operand_type_check (i.types[i.operands - 1], anymem))))
c32fa91d
L		 3740 {
3741 as_bad (_("expecting lockable instruction after `lock'"));
3742 return;
3743 }
3744
42164a71 3745 /* Check if HLE prefix is OK. */
165de32a 3746 if (i.hle_prefix && !check_hle ())
42164a71
L		 3747 return;
3748
7e8b059b
L		 3749 /* Check BND prefix. */
3750 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3751 as_bad (_("expecting valid branch instruction after `bnd'"));
3752
04ef582a 3753 /* Check NOTRACK prefix. */
9fef80d6
L		 3754 if (i.notrack_prefix && !i.tm.opcode_modifier.notrackprefixok)
3755 as_bad (_("expecting indirect branch instruction after `notrack'"));
04ef582a 3756
327e8c42
JB		 3757 if (i.tm.cpu_flags.bitfield.cpumpx)
3758 {
3759 if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX])
3760 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3761 else if (flag_code != CODE_16BIT
3762 ? i.prefix[ADDR_PREFIX]
3763 : i.mem_operands && !i.prefix[ADDR_PREFIX])
3764 as_bad (_("16-bit address isn't allowed in MPX instructions"));
3765 }
7e8b059b
L		 3766
3767 /* Insert BND prefix. */
3768 if (add_bnd_prefix
3769 && i.tm.opcode_modifier.bndprefixok
3770 && !i.prefix[BND_PREFIX])
3771 add_prefix (BND_PREFIX_OPCODE);
3772
29b0f896 3773 /* Check string instruction segment overrides. */
40fb9820 3774 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 3775 {
3776 if (!check_string ())
5dd0794d 3777 return;
fc0763e6 3778 i.disp_operands = 0;
29b0f896 3779 }
5dd0794d 3780
29b0f896
AM		 3781 if (!process_suffix ())
3782 return;
e413e4e9 3783
bc0844ae
L		 3784 /* Update operand types. */
3785 for (j = 0; j < i.operands; j++)
3786 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3787
29b0f896
AM		 3788 /* Make still unresolved immediate matches conform to size of immediate
3789 given in i.suffix. */
3790 if (!finalize_imm ())
3791 return;
252b5132 3792
40fb9820 3793 if (i.types[0].bitfield.imm1)
29b0f896 3794 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 3795
9afe6eb8
L		 3796 /* We only need to check those implicit registers for instructions
3797 with 3 operands or less. */
3798 if (i.operands <= 3)
3799 for (j = 0; j < i.operands; j++)
3800 if (i.types[j].bitfield.inoutportreg
3801 || i.types[j].bitfield.shiftcount
1b54b8d7 3802 || (i.types[j].bitfield.acc && !i.types[j].bitfield.xmmword))
9afe6eb8 3803 i.reg_operands--;
40fb9820 3804
c0f3af97
L		 3805 /* ImmExt should be processed after SSE2AVX. */
3806 if (!i.tm.opcode_modifier.sse2avx
3807 && i.tm.opcode_modifier.immext)
65da13b5 3808 process_immext ();
252b5132 3809
29b0f896
AM		 3810 /* For insns with operands there are more diddles to do to the opcode. */
3811 if (i.operands)
3812 {
3813 if (!process_operands ())
3814 return;
3815 }
40fb9820 3816 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 3817 {
3818 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3819 as_warn (_("translating to `%sp'"), i.tm.name);
3820 }
252b5132 3821
9e5e5283
L		 3822 if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex)
3823 {
3824 if (flag_code == CODE_16BIT)
3825 {
3826 as_bad (_("instruction `%s' isn't supported in 16-bit mode."),
3827 i.tm.name);
3828 return;
3829 }
c0f3af97 3830
9e5e5283
L		 3831 if (i.tm.opcode_modifier.vex)
3832 build_vex_prefix (t);
3833 else
3834 build_evex_prefix ();
3835 }
43234a1e 3836
5dd85c99
SP		 3837 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3838 instructions may define INT_OPCODE as well, so avoid this corner
3839 case for those instructions that use MODRM. */
3840 if (i.tm.base_opcode == INT_OPCODE
a6461c02
SP		 3841 && !i.tm.opcode_modifier.modrm
3842 && i.op[0].imms->X_add_number == 3)
29b0f896
AM		 3843 {
3844 i.tm.base_opcode = INT3_OPCODE;
3845 i.imm_operands = 0;
3846 }
252b5132 3847
40fb9820
L		 3848 if ((i.tm.opcode_modifier.jump
3849 || i.tm.opcode_modifier.jumpbyte
3850 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 3851 && i.op[0].disps->X_op == O_constant)
3852 {
3853 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3854 the absolute address given by the constant. Since ix86 jumps and
3855 calls are pc relative, we need to generate a reloc. */
3856 i.op[0].disps->X_add_symbol = &abs_symbol;
3857 i.op[0].disps->X_op = O_symbol;
3858 }
252b5132 3859
40fb9820 3860 if (i.tm.opcode_modifier.rex64)
161a04f6 3861 i.rex |= REX_W;
252b5132 3862
29b0f896
AM		 3863 /* For 8 bit registers we need an empty rex prefix. Also if the
3864 instruction already has a prefix, we need to convert old
3865 registers to new ones. */
773f551c 3866
dc821c5f 3867 if ((i.types[0].bitfield.reg && i.types[0].bitfield.byte
29b0f896 3868 && (i.op[0].regs->reg_flags & RegRex64) != 0)
dc821c5f 3869 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte
29b0f896 3870 && (i.op[1].regs->reg_flags & RegRex64) != 0)
dc821c5f
JB		 3871 || (((i.types[0].bitfield.reg && i.types[0].bitfield.byte)
3872 || (i.types[1].bitfield.reg && i.types[1].bitfield.byte))
29b0f896
AM		 3873 && i.rex != 0))
3874 {
3875 int x;
726c5dcd 3876
29b0f896
AM		 3877 i.rex |= REX_OPCODE;
3878 for (x = 0; x < 2; x++)
3879 {
3880 /* Look for 8 bit operand that uses old registers. */
dc821c5f 3881 if (i.types[x].bitfield.reg && i.types[x].bitfield.byte
29b0f896 3882 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 3883 {
29b0f896
AM		 3884 /* In case it is "hi" register, give up. */
3885 if (i.op[x].regs->reg_num > 3)
a540244d 3886 as_bad (_("can't encode register '%s%s' in an "
4eed87de 3887 "instruction requiring REX prefix."),
a540244d 3888 register_prefix, i.op[x].regs->reg_name);
773f551c 3889
29b0f896
AM		 3890 /* Otherwise it is equivalent to the extended register.
3891 Since the encoding doesn't change this is merely
3892 cosmetic cleanup for debug output. */
3893
3894 i.op[x].regs = i.op[x].regs + 8;
773f551c 3895 }
29b0f896
AM		 3896 }
3897 }
773f551c 3898
7ab9ffdd 3899 if (i.rex != 0)
29b0f896
AM		 3900 add_prefix (REX_OPCODE | i.rex);
3901
3902 /* We are ready to output the insn. */
3903 output_insn ();
3904}
3905
3906static char *
e3bb37b5 3907parse_insn (char *line, char *mnemonic)
29b0f896
AM		 3908{
3909 char *l = line;
3910 char *token_start = l;
3911 char *mnem_p;
5c6af06e 3912 int supported;
d3ce72d0 3913 const insn_template *t;
b6169b20 3914 char *dot_p = NULL;
29b0f896 3915
29b0f896
AM		 3916 while (1)
3917 {
3918 mnem_p = mnemonic;
3919 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3920 {
b6169b20
L		 3921 if (*mnem_p == '.')
3922 dot_p = mnem_p;
29b0f896
AM		 3923 mnem_p++;
3924 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 3925 {
29b0f896
AM		 3926 as_bad (_("no such instruction: `%s'"), token_start);
3927 return NULL;
3928 }
3929 l++;
3930 }
3931 if (!is_space_char (*l)
3932 && *l != END_OF_INSN
e44823cf
JB		 3933 && (intel_syntax
3934 || (*l != PREFIX_SEPARATOR
3935 && *l != ',')))
29b0f896
AM		 3936 {
3937 as_bad (_("invalid character %s in mnemonic"),
3938 output_invalid (*l));
3939 return NULL;
3940 }
3941 if (token_start == l)
3942 {
e44823cf 3943 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 3944 as_bad (_("expecting prefix; got nothing"));
3945 else
3946 as_bad (_("expecting mnemonic; got nothing"));
3947 return NULL;
3948 }
45288df1 3949
29b0f896 3950 /* Look up instruction (or prefix) via hash table. */
d3ce72d0 3951 current_templates = (const templates *) hash_find (op_hash, mnemonic);
47926f60 3952
29b0f896
AM		 3953 if (*l != END_OF_INSN
3954 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3955 && current_templates
40fb9820 3956 && current_templates->start->opcode_modifier.isprefix)
29b0f896 3957 {
c6fb90c8 3958 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3959 {
3960 as_bad ((flag_code != CODE_64BIT
3961 ? _("`%s' is only supported in 64-bit mode")
3962 : _("`%s' is not supported in 64-bit mode")),
3963 current_templates->start->name);
3964 return NULL;
3965 }
29b0f896
AM		 3966 /* If we are in 16-bit mode, do not allow addr16 or data16.
3967 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3968 if ((current_templates->start->opcode_modifier.size16
3969 || current_templates->start->opcode_modifier.size32)
29b0f896 3970 && flag_code != CODE_64BIT
40fb9820 3971 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3972 ^ (flag_code == CODE_16BIT)))
3973 {
3974 as_bad (_("redundant %s prefix"),
3975 current_templates->start->name);
3976 return NULL;
45288df1 3977 }
86fa6981 3978 if (current_templates->start->opcode_length == 0)
29b0f896 3979 {
86fa6981
L		 3980 /* Handle pseudo prefixes. */
3981 switch (current_templates->start->base_opcode)
3982 {
3983 case 0x0:
3984 /* {disp8} */
3985 i.disp_encoding = disp_encoding_8bit;
3986 break;
3987 case 0x1:
3988 /* {disp32} */
3989 i.disp_encoding = disp_encoding_32bit;
3990 break;
3991 case 0x2:
3992 /* {load} */
3993 i.dir_encoding = dir_encoding_load;
3994 break;
3995 case 0x3:
3996 /* {store} */
3997 i.dir_encoding = dir_encoding_store;
3998 break;
3999 case 0x4:
4000 /* {vex2} */
4001 i.vec_encoding = vex_encoding_vex2;
4002 break;
4003 case 0x5:
4004 /* {vex3} */
4005 i.vec_encoding = vex_encoding_vex3;
4006 break;
4007 case 0x6:
4008 /* {evex} */
4009 i.vec_encoding = vex_encoding_evex;
4010 break;
4011 default:
4012 abort ();
4013 }
4014 }
4015 else
4016 {
4017 /* Add prefix, checking for repeated prefixes. */
4e9ac44a 4018 switch (add_prefix (current_templates->start->base_opcode))
86fa6981 4019 {
4e9ac44a
L		 4020 case PREFIX_EXIST:
4021 return NULL;
4022 case PREFIX_DS:
4023 if (current_templates->start->cpu_flags.bitfield.cpucet)
4024 i.notrack_prefix = current_templates->start->name;
4025 break;
4026 case PREFIX_REP:
4027 if (current_templates->start->cpu_flags.bitfield.cpuhle)
4028 i.hle_prefix = current_templates->start->name;
4029 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
4030 i.bnd_prefix = current_templates->start->name;
4031 else
4032 i.rep_prefix = current_templates->start->name;
4033 break;
4034 default:
4035 break;
86fa6981 4036 }
29b0f896
AM		 4037 }
4038 /* Skip past PREFIX_SEPARATOR and reset token_start. */
4039 token_start = ++l;
4040 }
4041 else
4042 break;
4043 }
45288df1 4044
30a55f88 4045 if (!current_templates)
b6169b20 4046 {
f8a5c266
L		 4047 /* Check if we should swap operand or force 32bit displacement in
4048 encoding. */
30a55f88 4049 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
86fa6981 4050 i.dir_encoding = dir_encoding_store;
8d63c93e 4051 else if (mnem_p - 3 == dot_p
a501d77e
L		 4052 && dot_p[1] == 'd'
4053 && dot_p[2] == '8')
4054 i.disp_encoding = disp_encoding_8bit;
8d63c93e 4055 else if (mnem_p - 4 == dot_p
f8a5c266
L		 4056 && dot_p[1] == 'd'
4057 && dot_p[2] == '3'
4058 && dot_p[3] == '2')
a501d77e 4059 i.disp_encoding = disp_encoding_32bit;
30a55f88
L		 4060 else
4061 goto check_suffix;
4062 mnem_p = dot_p;
4063 *dot_p = '\0';
d3ce72d0 4064 current_templates = (const templates *) hash_find (op_hash, mnemonic);
b6169b20
L		 4065 }
4066
29b0f896
AM		 4067 if (!current_templates)
4068 {
b6169b20 4069check_suffix:
29b0f896
AM		 4070 /* See if we can get a match by trimming off a suffix. */
4071 switch (mnem_p[-1])
4072 {
4073 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 4074 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
4075 i.suffix = SHORT_MNEM_SUFFIX;
4076 else
1a0670f3 4077 /* Fall through. */
29b0f896
AM		 4078 case BYTE_MNEM_SUFFIX:
4079 case QWORD_MNEM_SUFFIX:
4080 i.suffix = mnem_p[-1];
4081 mnem_p[-1] = '\0';
d3ce72d0
NC		 4082 current_templates = (const templates *) hash_find (op_hash,
4083 mnemonic);
29b0f896
AM		 4084 break;
4085 case SHORT_MNEM_SUFFIX:
4086 case LONG_MNEM_SUFFIX:
4087 if (!intel_syntax)
4088 {
4089 i.suffix = mnem_p[-1];
4090 mnem_p[-1] = '\0';
d3ce72d0
NC		 4091 current_templates = (const templates *) hash_find (op_hash,
4092 mnemonic);
29b0f896
AM		 4093 }
4094 break;
252b5132 4095
29b0f896
AM		 4096 /* Intel Syntax. */
4097 case 'd':
4098 if (intel_syntax)
4099 {
9306ca4a 4100 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 4101 i.suffix = SHORT_MNEM_SUFFIX;
4102 else
4103 i.suffix = LONG_MNEM_SUFFIX;
4104 mnem_p[-1] = '\0';
d3ce72d0
NC		 4105 current_templates = (const templates *) hash_find (op_hash,
4106 mnemonic);
29b0f896
AM		 4107 }
4108 break;
4109 }
4110 if (!current_templates)
4111 {
4112 as_bad (_("no such instruction: `%s'"), token_start);
4113 return NULL;
4114 }
4115 }
252b5132 4116
40fb9820
L		 4117 if (current_templates->start->opcode_modifier.jump
4118 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 4119 {
4120 /* Check for a branch hint. We allow ",pt" and ",pn" for
4121 predict taken and predict not taken respectively.
4122 I'm not sure that branch hints actually do anything on loop
4123 and jcxz insns (JumpByte) for current Pentium4 chips. They
4124 may work in the future and it doesn't hurt to accept them
4125 now. */
4126 if (l[0] == ',' && l[1] == 'p')
4127 {
4128 if (l[2] == 't')
4129 {
4130 if (!add_prefix (DS_PREFIX_OPCODE))
4131 return NULL;
4132 l += 3;
4133 }
4134 else if (l[2] == 'n')
4135 {
4136 if (!add_prefix (CS_PREFIX_OPCODE))
4137 return NULL;
4138 l += 3;
4139 }
4140 }
4141 }
4142 /* Any other comma loses. */
4143 if (*l == ',')
4144 {
4145 as_bad (_("invalid character %s in mnemonic"),
4146 output_invalid (*l));
4147 return NULL;
4148 }
252b5132 4149
29b0f896 4150 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 4151 supported = 0;
4152 for (t = current_templates->start; t < current_templates->end; ++t)
4153 {
c0f3af97
L		 4154 supported |= cpu_flags_match (t);
4155 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 4156 goto skip;
5c6af06e 4157 }
3629bb00 4158
c0f3af97 4159 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 4160 {
4161 as_bad (flag_code == CODE_64BIT
4162 ? _("`%s' is not supported in 64-bit mode")
4163 : _("`%s' is only supported in 64-bit mode"),
4164 current_templates->start->name);
4165 return NULL;
4166 }
c0f3af97 4167 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 4168 {
3629bb00 4169 as_bad (_("`%s' is not supported on `%s%s'"),
7ab9ffdd 4170 current_templates->start->name,
41aacd83 4171 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 4172 cpu_sub_arch_name ? cpu_sub_arch_name : "");
4173 return NULL;
29b0f896 4174 }
3629bb00
L		 4175
4176skip:
4177 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 4178 && (flag_code != CODE_16BIT))
29b0f896
AM		 4179 {
4180 as_warn (_("use .code16 to ensure correct addressing mode"));
4181 }
252b5132 4182
29b0f896
AM		 4183 return l;
4184}
252b5132 4185
29b0f896 4186static char *
e3bb37b5 4187parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 4188{
4189 char *token_start;
3138f287 4190
29b0f896
AM		 4191 /* 1 if operand is pending after ','. */
4192 unsigned int expecting_operand = 0;
252b5132 4193
29b0f896
AM		 4194 /* Non-zero if operand parens not balanced. */
4195 unsigned int paren_not_balanced;
4196
4197 while (*l != END_OF_INSN)
4198 {
4199 /* Skip optional white space before operand. */
4200 if (is_space_char (*l))
4201 ++l;
d02603dc 4202 if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"')
29b0f896
AM		 4203 {
4204 as_bad (_("invalid character %s before operand %d"),
4205 output_invalid (*l),
4206 i.operands + 1);
4207 return NULL;
4208 }
d02603dc 4209 token_start = l; /* After white space. */
29b0f896
AM		 4210 paren_not_balanced = 0;
4211 while (paren_not_balanced || *l != ',')
4212 {
4213 if (*l == END_OF_INSN)
4214 {
4215 if (paren_not_balanced)
4216 {
4217 if (!intel_syntax)
4218 as_bad (_("unbalanced parenthesis in operand %d."),
4219 i.operands + 1);
4220 else
4221 as_bad (_("unbalanced brackets in operand %d."),
4222 i.operands + 1);
4223 return NULL;
4224 }
4225 else
4226 break; /* we are done */
4227 }
d02603dc 4228 else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"')
29b0f896
AM		 4229 {
4230 as_bad (_("invalid character %s in operand %d"),
4231 output_invalid (*l),
4232 i.operands + 1);
4233 return NULL;
4234 }
4235 if (!intel_syntax)
4236 {
4237 if (*l == '(')
4238 ++paren_not_balanced;
4239 if (*l == ')')
4240 --paren_not_balanced;
4241 }
4242 else
4243 {
4244 if (*l == '[')
4245 ++paren_not_balanced;
4246 if (*l == ']')
4247 --paren_not_balanced;
4248 }
4249 l++;
4250 }
4251 if (l != token_start)
4252 { /* Yes, we've read in another operand. */
4253 unsigned int operand_ok;
4254 this_operand = i.operands++;
4255 if (i.operands > MAX_OPERANDS)
4256 {
4257 as_bad (_("spurious operands; (%d operands/instruction max)"),
4258 MAX_OPERANDS);
4259 return NULL;
4260 }
9d46ce34 4261 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 4262 /* Now parse operand adding info to 'i' as we go along. */
4263 END_STRING_AND_SAVE (l);
4264
4265 if (intel_syntax)
4266 operand_ok =
4267 i386_intel_operand (token_start,
4268 intel_float_operand (mnemonic));
4269 else
a7619375 4270 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 4271
4272 RESTORE_END_STRING (l);
4273 if (!operand_ok)
4274 return NULL;
4275 }
4276 else
4277 {
4278 if (expecting_operand)
4279 {
4280 expecting_operand_after_comma:
4281 as_bad (_("expecting operand after ','; got nothing"));
4282 return NULL;
4283 }
4284 if (*l == ',')
4285 {
4286 as_bad (_("expecting operand before ','; got nothing"));
4287 return NULL;
4288 }
4289 }
7f3f1ea2 4290
29b0f896
AM		 4291 /* Now *l must be either ',' or END_OF_INSN. */
4292 if (*l == ',')
4293 {
4294 if (*++l == END_OF_INSN)
4295 {
4296 /* Just skip it, if it's \n complain. */
4297 goto expecting_operand_after_comma;
4298 }
4299 expecting_operand = 1;
4300 }
4301 }
4302 return l;
4303}
7f3f1ea2 4304
050dfa73 4305static void
4d456e3d 4306swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 4307{
4308 union i386_op temp_op;
40fb9820 4309 i386_operand_type temp_type;
050dfa73 4310 enum bfd_reloc_code_real temp_reloc;
4eed87de 4311
050dfa73
MM		 4312 temp_type = i.types[xchg2];
4313 i.types[xchg2] = i.types[xchg1];
4314 i.types[xchg1] = temp_type;
4315 temp_op = i.op[xchg2];
4316 i.op[xchg2] = i.op[xchg1];
4317 i.op[xchg1] = temp_op;
4318 temp_reloc = i.reloc[xchg2];
4319 i.reloc[xchg2] = i.reloc[xchg1];
4320 i.reloc[xchg1] = temp_reloc;
43234a1e
L		 4321
4322 if (i.mask)
4323 {
4324 if (i.mask->operand == xchg1)
4325 i.mask->operand = xchg2;
4326 else if (i.mask->operand == xchg2)
4327 i.mask->operand = xchg1;
4328 }
4329 if (i.broadcast)
4330 {
4331 if (i.broadcast->operand == xchg1)
4332 i.broadcast->operand = xchg2;
4333 else if (i.broadcast->operand == xchg2)
4334 i.broadcast->operand = xchg1;
4335 }
4336 if (i.rounding)
4337 {
4338 if (i.rounding->operand == xchg1)
4339 i.rounding->operand = xchg2;
4340 else if (i.rounding->operand == xchg2)
4341 i.rounding->operand = xchg1;
4342 }
050dfa73
MM		 4343}
4344
29b0f896 4345static void
e3bb37b5 4346swap_operands (void)
29b0f896 4347{
b7c61d9a 4348 switch (i.operands)
050dfa73 4349 {
c0f3af97 4350 case 5:
b7c61d9a 4351 case 4:
4d456e3d 4352 swap_2_operands (1, i.operands - 2);
1a0670f3 4353 /* Fall through. */
b7c61d9a
L		 4354 case 3:
4355 case 2:
4d456e3d 4356 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 4357 break;
4358 default:
4359 abort ();
29b0f896 4360 }
29b0f896
AM		 4361
4362 if (i.mem_operands == 2)
4363 {
4364 const seg_entry *temp_seg;
4365 temp_seg = i.seg[0];
4366 i.seg[0] = i.seg[1];
4367 i.seg[1] = temp_seg;
4368 }
4369}
252b5132 4370
29b0f896
AM		 4371/* Try to ensure constant immediates are represented in the smallest
4372 opcode possible. */
4373static void
e3bb37b5 4374optimize_imm (void)
29b0f896
AM		 4375{
4376 char guess_suffix = 0;
4377 int op;
252b5132 4378
29b0f896
AM		 4379 if (i.suffix)
4380 guess_suffix = i.suffix;
4381 else if (i.reg_operands)
4382 {
4383 /* Figure out a suffix from the last register operand specified.
4384 We can't do this properly yet, ie. excluding InOutPortReg,
4385 but the following works for instructions with immediates.
4386 In any case, we can't set i.suffix yet. */
4387 for (op = i.operands; --op >= 0;)
dc821c5f 4388 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
7ab9ffdd 4389 {
40fb9820
L		 4390 guess_suffix = BYTE_MNEM_SUFFIX;
4391 break;
4392 }
dc821c5f 4393 else if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
252b5132 4394 {
40fb9820
L		 4395 guess_suffix = WORD_MNEM_SUFFIX;
4396 break;
4397 }
dc821c5f 4398 else if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 4399 {
4400 guess_suffix = LONG_MNEM_SUFFIX;
4401 break;
4402 }
dc821c5f 4403 else if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 4404 {
4405 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 4406 break;
252b5132 4407 }
29b0f896
AM		 4408 }
4409 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4410 guess_suffix = WORD_MNEM_SUFFIX;
4411
4412 for (op = i.operands; --op >= 0;)
40fb9820 4413 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 4414 {
4415 switch (i.op[op].imms->X_op)
252b5132 4416 {
29b0f896
AM		 4417 case O_constant:
4418 /* If a suffix is given, this operand may be shortened. */
4419 switch (guess_suffix)
252b5132 4420 {
29b0f896 4421 case LONG_MNEM_SUFFIX:
40fb9820
L		 4422 i.types[op].bitfield.imm32 = 1;
4423 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4424 break;
4425 case WORD_MNEM_SUFFIX:
40fb9820
L		 4426 i.types[op].bitfield.imm16 = 1;
4427 i.types[op].bitfield.imm32 = 1;
4428 i.types[op].bitfield.imm32s = 1;
4429 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 4430 break;
4431 case BYTE_MNEM_SUFFIX:
40fb9820
L		 4432 i.types[op].bitfield.imm8 = 1;
4433 i.types[op].bitfield.imm8s = 1;
4434 i.types[op].bitfield.imm16 = 1;
4435 i.types[op].bitfield.imm32 = 1;
4436 i.types[op].bitfield.imm32s = 1;
4437 i.types[op].bitfield.imm64 = 1;
29b0f896 4438 break;
252b5132 4439 }
252b5132 4440
29b0f896
AM		 4441 /* If this operand is at most 16 bits, convert it
4442 to a signed 16 bit number before trying to see
4443 whether it will fit in an even smaller size.
4444 This allows a 16-bit operand such as $0xffe0 to
4445 be recognised as within Imm8S range. */
40fb9820 4446 if ((i.types[op].bitfield.imm16)
29b0f896 4447 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 4448 {
29b0f896
AM		 4449 i.op[op].imms->X_add_number =
4450 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4451 }
a28def75
L		 4452#ifdef BFD64
4453 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
40fb9820 4454 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 4455 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4456 == 0))
4457 {
4458 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4459 ^ ((offsetT) 1 << 31))
4460 - ((offsetT) 1 << 31));
4461 }
a28def75 4462#endif
40fb9820 4463 i.types[op]
c6fb90c8
L		 4464 = operand_type_or (i.types[op],
4465 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 4466
29b0f896
AM		 4467 /* We must avoid matching of Imm32 templates when 64bit
4468 only immediate is available. */
4469 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 4470 i.types[op].bitfield.imm32 = 0;
29b0f896 4471 break;
252b5132 4472
29b0f896
AM		 4473 case O_absent:
4474 case O_register:
4475 abort ();
4476
4477 /* Symbols and expressions. */
4478 default:
9cd96992
JB		 4479 /* Convert symbolic operand to proper sizes for matching, but don't
4480 prevent matching a set of insns that only supports sizes other
4481 than those matching the insn suffix. */
4482 {
40fb9820 4483 i386_operand_type mask, allowed;
d3ce72d0 4484 const insn_template *t;
9cd96992 4485
0dfbf9d7
L		 4486 operand_type_set (&mask, 0);
4487 operand_type_set (&allowed, 0);
40fb9820 4488
4eed87de
AM		 4489 for (t = current_templates->start;
4490 t < current_templates->end;
4491 ++t)
c6fb90c8
L		 4492 allowed = operand_type_or (allowed,
4493 t->operand_types[op]);
9cd96992
JB		 4494 switch (guess_suffix)
4495 {
4496 case QWORD_MNEM_SUFFIX:
40fb9820
L		 4497 mask.bitfield.imm64 = 1;
4498 mask.bitfield.imm32s = 1;
9cd96992
JB		 4499 break;
4500 case LONG_MNEM_SUFFIX:
40fb9820 4501 mask.bitfield.imm32 = 1;
9cd96992
JB		 4502 break;
4503 case WORD_MNEM_SUFFIX:
40fb9820 4504 mask.bitfield.imm16 = 1;
9cd96992
JB		 4505 break;
4506 case BYTE_MNEM_SUFFIX:
40fb9820 4507 mask.bitfield.imm8 = 1;
9cd96992
JB		 4508 break;
4509 default:
9cd96992
JB		 4510 break;
4511 }
c6fb90c8 4512 allowed = operand_type_and (mask, allowed);
0dfbf9d7 4513 if (!operand_type_all_zero (&allowed))
c6fb90c8 4514 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 4515 }
29b0f896 4516 break;
252b5132 4517 }
29b0f896
AM		 4518 }
4519}
47926f60 4520
29b0f896
AM		 4521/* Try to use the smallest displacement type too. */
4522static void
e3bb37b5 4523optimize_disp (void)
29b0f896
AM		 4524{
4525 int op;
3e73aa7c 4526
29b0f896 4527 for (op = i.operands; --op >= 0;)
40fb9820 4528 if (operand_type_check (i.types[op], disp))
252b5132 4529 {
b300c311 4530 if (i.op[op].disps->X_op == O_constant)
252b5132 4531 {
91d6fa6a 4532 offsetT op_disp = i.op[op].disps->X_add_number;
29b0f896 4533
40fb9820 4534 if (i.types[op].bitfield.disp16
91d6fa6a 4535 && (op_disp & ~(offsetT) 0xffff) == 0)
b300c311
L		 4536 {
4537 /* If this operand is at most 16 bits, convert
4538 to a signed 16 bit number and don't use 64bit
4539 displacement. */
91d6fa6a 4540 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 4541 i.types[op].bitfield.disp64 = 0;
b300c311 4542 }
a28def75
L		 4543#ifdef BFD64
4544 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
40fb9820 4545 if (i.types[op].bitfield.disp32
91d6fa6a 4546 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
b300c311
L		 4547 {
4548 /* If this operand is at most 32 bits, convert
4549 to a signed 32 bit number and don't use 64bit
4550 displacement. */
91d6fa6a
NC		 4551 op_disp &= (((offsetT) 2 << 31) - 1);
4552 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 4553 i.types[op].bitfield.disp64 = 0;
b300c311 4554 }
a28def75 4555#endif
91d6fa6a 4556 if (!op_disp && i.types[op].bitfield.baseindex)
b300c311 4557 {
40fb9820
L		 4558 i.types[op].bitfield.disp8 = 0;
4559 i.types[op].bitfield.disp16 = 0;
4560 i.types[op].bitfield.disp32 = 0;
4561 i.types[op].bitfield.disp32s = 0;
4562 i.types[op].bitfield.disp64 = 0;
b300c311
L		 4563 i.op[op].disps = 0;
4564 i.disp_operands--;
4565 }
4566 else if (flag_code == CODE_64BIT)
4567 {
91d6fa6a 4568 if (fits_in_signed_long (op_disp))
28a9d8f5 4569 {
40fb9820
L		 4570 i.types[op].bitfield.disp64 = 0;
4571 i.types[op].bitfield.disp32s = 1;
28a9d8f5 4572 }
0e1147d9 4573 if (i.prefix[ADDR_PREFIX]
91d6fa6a 4574 && fits_in_unsigned_long (op_disp))
40fb9820 4575 i.types[op].bitfield.disp32 = 1;
b300c311 4576 }
40fb9820
L		 4577 if ((i.types[op].bitfield.disp32
4578 || i.types[op].bitfield.disp32s
4579 || i.types[op].bitfield.disp16)
b5014f7a 4580 && fits_in_disp8 (op_disp))
40fb9820 4581 i.types[op].bitfield.disp8 = 1;
252b5132 4582 }
67a4f2b7
AO		 4583 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4584 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4585 {
4586 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4587 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 4588 i.types[op].bitfield.disp8 = 0;
4589 i.types[op].bitfield.disp16 = 0;
4590 i.types[op].bitfield.disp32 = 0;
4591 i.types[op].bitfield.disp32s = 0;
4592 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 4593 }
4594 else
b300c311 4595 /* We only support 64bit displacement on constants. */
40fb9820 4596 i.types[op].bitfield.disp64 = 0;
252b5132 4597 }
29b0f896
AM		 4598}
4599
6c30d220
L		 4600/* Check if operands are valid for the instruction. */
4601
4602static int
4603check_VecOperands (const insn_template *t)
4604{
43234a1e
L		 4605 unsigned int op;
4606
6c30d220
L		 4607 /* Without VSIB byte, we can't have a vector register for index. */
4608 if (!t->opcode_modifier.vecsib
4609 && i.index_reg
1b54b8d7
JB		 4610 && (i.index_reg->reg_type.bitfield.xmmword
4611 || i.index_reg->reg_type.bitfield.ymmword
4612 || i.index_reg->reg_type.bitfield.zmmword))
6c30d220
L		 4613 {
4614 i.error = unsupported_vector_index_register;
4615 return 1;
4616 }
4617
ad8ecc81
MZ		 4618 /* Check if default mask is allowed. */
4619 if (t->opcode_modifier.nodefmask
4620 && (!i.mask || i.mask->mask->reg_num == 0))
4621 {
4622 i.error = no_default_mask;
4623 return 1;
4624 }
4625
7bab8ab5
JB		 4626 /* For VSIB byte, we need a vector register for index, and all vector
4627 registers must be distinct. */
4628 if (t->opcode_modifier.vecsib)
4629 {
4630 if (!i.index_reg
6c30d220 4631 || !((t->opcode_modifier.vecsib == VecSIB128
1b54b8d7 4632 && i.index_reg->reg_type.bitfield.xmmword)
6c30d220 4633 || (t->opcode_modifier.vecsib == VecSIB256
1b54b8d7 4634 && i.index_reg->reg_type.bitfield.ymmword)
43234a1e 4635 || (t->opcode_modifier.vecsib == VecSIB512
1b54b8d7 4636 && i.index_reg->reg_type.bitfield.zmmword)))
7bab8ab5
JB		 4637 {
4638 i.error = invalid_vsib_address;
4639 return 1;
4640 }
4641
43234a1e
L		 4642 gas_assert (i.reg_operands == 2 || i.mask);
4643 if (i.reg_operands == 2 && !i.mask)
4644 {
1b54b8d7
JB		 4645 gas_assert (i.types[0].bitfield.regsimd);
4646 gas_assert (i.types[0].bitfield.xmmword
4647 || i.types[0].bitfield.ymmword);
4648 gas_assert (i.types[2].bitfield.regsimd);
4649 gas_assert (i.types[2].bitfield.xmmword
4650 || i.types[2].bitfield.ymmword);
43234a1e
L		 4651 if (operand_check == check_none)
4652 return 0;
4653 if (register_number (i.op[0].regs)
4654 != register_number (i.index_reg)
4655 && register_number (i.op[2].regs)
4656 != register_number (i.index_reg)
4657 && register_number (i.op[0].regs)
4658 != register_number (i.op[2].regs))
4659 return 0;
4660 if (operand_check == check_error)
4661 {
4662 i.error = invalid_vector_register_set;
4663 return 1;
4664 }
4665 as_warn (_("mask, index, and destination registers should be distinct"));
4666 }
8444f82a
MZ		 4667 else if (i.reg_operands == 1 && i.mask)
4668 {
1b54b8d7
JB		 4669 if (i.types[1].bitfield.regsimd
4670 && (i.types[1].bitfield.xmmword
4671 || i.types[1].bitfield.ymmword
4672 || i.types[1].bitfield.zmmword)
8444f82a
MZ		 4673 && (register_number (i.op[1].regs)
4674 == register_number (i.index_reg)))
4675 {
4676 if (operand_check == check_error)
4677 {
4678 i.error = invalid_vector_register_set;
4679 return 1;
4680 }
4681 if (operand_check != check_none)
4682 as_warn (_("index and destination registers should be distinct"));
4683 }
4684 }
43234a1e 4685 }
7bab8ab5 4686
43234a1e
L		 4687 /* Check if broadcast is supported by the instruction and is applied
4688 to the memory operand. */
4689 if (i.broadcast)
4690 {
4691 int broadcasted_opnd_size;
4692
4693 /* Check if specified broadcast is supported in this instruction,
4694 and it's applied to memory operand of DWORD or QWORD type,
4695 depending on VecESize. */
4696 if (i.broadcast->type != t->opcode_modifier.broadcast
4697 || !i.types[i.broadcast->operand].bitfield.mem
4698 || (t->opcode_modifier.vecesize == 0
4699 && !i.types[i.broadcast->operand].bitfield.dword
4700 && !i.types[i.broadcast->operand].bitfield.unspecified)
4701 || (t->opcode_modifier.vecesize == 1
4702 && !i.types[i.broadcast->operand].bitfield.qword
4703 && !i.types[i.broadcast->operand].bitfield.unspecified))
4704 goto bad_broadcast;
4705
4706 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4707 if (i.broadcast->type == BROADCAST_1TO16)
4708 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4709 else if (i.broadcast->type == BROADCAST_1TO8)
4710 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
b28d1bda
IT		 4711 else if (i.broadcast->type == BROADCAST_1TO4)
4712 broadcasted_opnd_size <<= 2; /* Broadcast 1to4. */
4713 else if (i.broadcast->type == BROADCAST_1TO2)
4714 broadcasted_opnd_size <<= 1; /* Broadcast 1to2. */
43234a1e
L		 4715 else
4716 goto bad_broadcast;
4717
4718 if ((broadcasted_opnd_size == 256
4719 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4720 || (broadcasted_opnd_size == 512
4721 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4722 {
4723 bad_broadcast:
4724 i.error = unsupported_broadcast;
4725 return 1;
4726 }
4727 }
4728 /* If broadcast is supported in this instruction, we need to check if
4729 operand of one-element size isn't specified without broadcast. */
4730 else if (t->opcode_modifier.broadcast && i.mem_operands)
4731 {
4732 /* Find memory operand. */
4733 for (op = 0; op < i.operands; op++)
4734 if (operand_type_check (i.types[op], anymem))
4735 break;
4736 gas_assert (op < i.operands);
4737 /* Check size of the memory operand. */
4738 if ((t->opcode_modifier.vecesize == 0
4739 && i.types[op].bitfield.dword)
4740 || (t->opcode_modifier.vecesize == 1
4741 && i.types[op].bitfield.qword))
4742 {
4743 i.error = broadcast_needed;
4744 return 1;
4745 }
4746 }
4747
4748 /* Check if requested masking is supported. */
4749 if (i.mask
4750 && (!t->opcode_modifier.masking
4751 || (i.mask->zeroing
4752 && t->opcode_modifier.masking == MERGING_MASKING)))
4753 {
4754 i.error = unsupported_masking;
4755 return 1;
4756 }
4757
4758 /* Check if masking is applied to dest operand. */
4759 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4760 {
4761 i.error = mask_not_on_destination;
4762 return 1;
4763 }
4764
43234a1e
L		 4765 /* Check RC/SAE. */
4766 if (i.rounding)
4767 {
4768 if ((i.rounding->type != saeonly
4769 && !t->opcode_modifier.staticrounding)
4770 || (i.rounding->type == saeonly
4771 && (t->opcode_modifier.staticrounding
4772 || !t->opcode_modifier.sae)))
4773 {
4774 i.error = unsupported_rc_sae;
4775 return 1;
4776 }
4777 /* If the instruction has several immediate operands and one of
4778 them is rounding, the rounding operand should be the last
4779 immediate operand. */
4780 if (i.imm_operands > 1
4781 && i.rounding->operand != (int) (i.imm_operands - 1))
7bab8ab5 4782 {
43234a1e 4783 i.error = rc_sae_operand_not_last_imm;
7bab8ab5
JB		 4784 return 1;
4785 }
6c30d220
L		 4786 }
4787
43234a1e 4788 /* Check vector Disp8 operand. */
b5014f7a
JB		 4789 if (t->opcode_modifier.disp8memshift
4790 && i.disp_encoding != disp_encoding_32bit)
43234a1e
L		 4791 {
4792 if (i.broadcast)
4793 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4794 else
4795 i.memshift = t->opcode_modifier.disp8memshift;
4796
4797 for (op = 0; op < i.operands; op++)
4798 if (operand_type_check (i.types[op], disp)
4799 && i.op[op].disps->X_op == O_constant)
4800 {
b5014f7a 4801 if (fits_in_disp8 (i.op[op].disps->X_add_number))
43234a1e 4802 {
b5014f7a
JB		 4803 i.types[op].bitfield.disp8 = 1;
4804 return 0;
43234a1e 4805 }
b5014f7a 4806 i.types[op].bitfield.disp8 = 0;
43234a1e
L		 4807 }
4808 }
b5014f7a
JB		 4809
4810 i.memshift = 0;
43234a1e 4811
6c30d220
L		 4812 return 0;
4813}
4814
43f3e2ee 4815/* Check if operands are valid for the instruction. Update VEX
a683cc34
SP		 4816 operand types. */
4817
4818static int
4819VEX_check_operands (const insn_template *t)
4820{
86fa6981 4821 if (i.vec_encoding == vex_encoding_evex)
43234a1e 4822 {
86fa6981
L		 4823 /* This instruction must be encoded with EVEX prefix. */
4824 if (!t->opcode_modifier.evex)
4825 {
4826 i.error = unsupported;
4827 return 1;
4828 }
4829 return 0;
43234a1e
L		 4830 }
4831
a683cc34 4832 if (!t->opcode_modifier.vex)
86fa6981
L		 4833 {
4834 /* This instruction template doesn't have VEX prefix. */
4835 if (i.vec_encoding != vex_encoding_default)
4836 {
4837 i.error = unsupported;
4838 return 1;
4839 }
4840 return 0;
4841 }
a683cc34
SP		 4842
4843 /* Only check VEX_Imm4, which must be the first operand. */
4844 if (t->operand_types[0].bitfield.vec_imm4)
4845 {
4846 if (i.op[0].imms->X_op != O_constant
4847 || !fits_in_imm4 (i.op[0].imms->X_add_number))
891edac4 4848 {
a65babc9 4849 i.error = bad_imm4;
891edac4
L		 4850 return 1;
4851 }
a683cc34
SP		 4852
4853 /* Turn off Imm8 so that update_imm won't complain. */
4854 i.types[0] = vec_imm4;
4855 }
4856
4857 return 0;
4858}
4859
d3ce72d0 4860static const insn_template *
83b16ac6 4861match_template (char mnem_suffix)
29b0f896
AM		 4862{
4863 /* Points to template once we've found it. */
d3ce72d0 4864 const insn_template *t;
40fb9820 4865 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 4866 i386_operand_type overlap4;
29b0f896 4867 unsigned int found_reverse_match;
83b16ac6 4868 i386_opcode_modifier suffix_check, mnemsuf_check;
40fb9820 4869 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 4870 int addr_prefix_disp;
a5c311ca 4871 unsigned int j;
3629bb00 4872 unsigned int found_cpu_match;
45664ddb 4873 unsigned int check_register;
5614d22c 4874 enum i386_error specific_error = 0;
29b0f896 4875
c0f3af97
L		 4876#if MAX_OPERANDS != 5
4877# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 4878#endif
4879
29b0f896 4880 found_reverse_match = 0;
539e75ad 4881 addr_prefix_disp = -1;
40fb9820
L		 4882
4883 memset (&suffix_check, 0, sizeof (suffix_check));
4884 if (i.suffix == BYTE_MNEM_SUFFIX)
4885 suffix_check.no_bsuf = 1;
4886 else if (i.suffix == WORD_MNEM_SUFFIX)
4887 suffix_check.no_wsuf = 1;
4888 else if (i.suffix == SHORT_MNEM_SUFFIX)
4889 suffix_check.no_ssuf = 1;
4890 else if (i.suffix == LONG_MNEM_SUFFIX)
4891 suffix_check.no_lsuf = 1;
4892 else if (i.suffix == QWORD_MNEM_SUFFIX)
4893 suffix_check.no_qsuf = 1;
4894 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 4895 suffix_check.no_ldsuf = 1;
29b0f896 4896
83b16ac6
JB		 4897 memset (&mnemsuf_check, 0, sizeof (mnemsuf_check));
4898 if (intel_syntax)
4899 {
4900 switch (mnem_suffix)
4901 {
4902 case BYTE_MNEM_SUFFIX: mnemsuf_check.no_bsuf = 1; break;
4903 case WORD_MNEM_SUFFIX: mnemsuf_check.no_wsuf = 1; break;
4904 case SHORT_MNEM_SUFFIX: mnemsuf_check.no_ssuf = 1; break;
4905 case LONG_MNEM_SUFFIX: mnemsuf_check.no_lsuf = 1; break;
4906 case QWORD_MNEM_SUFFIX: mnemsuf_check.no_qsuf = 1; break;
4907 }
4908 }
4909
01559ecc
L		 4910 /* Must have right number of operands. */
4911 i.error = number_of_operands_mismatch;
4912
45aa61fe 4913 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 4914 {
539e75ad
L		 4915 addr_prefix_disp = -1;
4916
29b0f896
AM		 4917 if (i.operands != t->operands)
4918 continue;
4919
50aecf8c 4920 /* Check processor support. */
a65babc9 4921 i.error = unsupported;
c0f3af97
L		 4922 found_cpu_match = (cpu_flags_match (t)
4923 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 4924 if (!found_cpu_match)
4925 continue;
4926
e1d4d893 4927 /* Check old gcc support. */
a65babc9 4928 i.error = old_gcc_only;
e1d4d893
L		 4929 if (!old_gcc && t->opcode_modifier.oldgcc)
4930 continue;
4931
4932 /* Check AT&T mnemonic. */
a65babc9 4933 i.error = unsupported_with_intel_mnemonic;
e1d4d893 4934 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 4935 continue;
4936
e92bae62 4937 /* Check AT&T/Intel syntax and Intel64/AMD64 ISA. */
a65babc9 4938 i.error = unsupported_syntax;
5c07affc 4939 if ((intel_syntax && t->opcode_modifier.attsyntax)
e92bae62
L		 4940 || (!intel_syntax && t->opcode_modifier.intelsyntax)
4941 || (intel64 && t->opcode_modifier.amd64)
4942 || (!intel64 && t->opcode_modifier.intel64))
1efbbeb4
L		 4943 continue;
4944
20592a94 4945 /* Check the suffix, except for some instructions in intel mode. */
a65babc9 4946 i.error = invalid_instruction_suffix;
567e4e96
L		 4947 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4948 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4949 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4950 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4951 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4952 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4953 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896 4954 continue;
83b16ac6
JB		 4955 /* In Intel mode all mnemonic suffixes must be explicitly allowed. */
4956 if ((t->opcode_modifier.no_bsuf && mnemsuf_check.no_bsuf)
4957 || (t->opcode_modifier.no_wsuf && mnemsuf_check.no_wsuf)
4958 || (t->opcode_modifier.no_lsuf && mnemsuf_check.no_lsuf)
4959 || (t->opcode_modifier.no_ssuf && mnemsuf_check.no_ssuf)
4960 || (t->opcode_modifier.no_qsuf && mnemsuf_check.no_qsuf)
4961 || (t->opcode_modifier.no_ldsuf && mnemsuf_check.no_ldsuf))
4962 continue;
29b0f896 4963
5c07affc 4964 if (!operand_size_match (t))
7d5e4556 4965 continue;
539e75ad 4966
5c07affc
L		 4967 for (j = 0; j < MAX_OPERANDS; j++)
4968 operand_types[j] = t->operand_types[j];
4969
45aa61fe
AM		 4970 /* In general, don't allow 64-bit operands in 32-bit mode. */
4971 if (i.suffix == QWORD_MNEM_SUFFIX
4972 && flag_code != CODE_64BIT
4973 && (intel_syntax
40fb9820 4974 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 4975 && !intel_float_operand (t->name))
4976 : intel_float_operand (t->name) != 2)
40fb9820 4977 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 4978 && !operand_types[0].bitfield.regsimd)
40fb9820 4979 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 4980 && !operand_types[t->operands > 1].bitfield.regsimd))
45aa61fe
AM		 4981 && (t->base_opcode != 0x0fc7
4982 || t->extension_opcode != 1 /* cmpxchg8b */))
4983 continue;
4984
192dc9c6
JB		 4985 /* In general, don't allow 32-bit operands on pre-386. */
4986 else if (i.suffix == LONG_MNEM_SUFFIX
4987 && !cpu_arch_flags.bitfield.cpui386
4988 && (intel_syntax
4989 ? (!t->opcode_modifier.ignoresize
4990 && !intel_float_operand (t->name))
4991 : intel_float_operand (t->name) != 2)
4992 && ((!operand_types[0].bitfield.regmmx
1b54b8d7 4993 && !operand_types[0].bitfield.regsimd)
192dc9c6 4994 || (!operand_types[t->operands > 1].bitfield.regmmx
1b54b8d7 4995 && !operand_types[t->operands > 1].bitfield.regsimd)))
192dc9c6
JB		 4996 continue;
4997
29b0f896 4998 /* Do not verify operands when there are none. */
50aecf8c 4999 else
29b0f896 5000 {
c6fb90c8 5001 if (!t->operands)
2dbab7d5
L		 5002 /* We've found a match; break out of loop. */
5003 break;
29b0f896 5004 }
252b5132 5005
539e75ad
L		 5006 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
5007 into Disp32/Disp16/Disp32 operand. */
5008 if (i.prefix[ADDR_PREFIX] != 0)
5009 {
40fb9820 5010 /* There should be only one Disp operand. */
539e75ad
L		 5011 switch (flag_code)
5012 {
5013 case CODE_16BIT:
40fb9820
L		 5014 for (j = 0; j < MAX_OPERANDS; j++)
5015 {
5016 if (operand_types[j].bitfield.disp16)
5017 {
5018 addr_prefix_disp = j;
5019 operand_types[j].bitfield.disp32 = 1;
5020 operand_types[j].bitfield.disp16 = 0;
5021 break;
5022 }
5023 }
539e75ad
L		 5024 break;
5025 case CODE_32BIT:
40fb9820
L		 5026 for (j = 0; j < MAX_OPERANDS; j++)
5027 {
5028 if (operand_types[j].bitfield.disp32)
5029 {
5030 addr_prefix_disp = j;
5031 operand_types[j].bitfield.disp32 = 0;
5032 operand_types[j].bitfield.disp16 = 1;
5033 break;
5034 }
5035 }
539e75ad
L		 5036 break;
5037 case CODE_64BIT:
40fb9820
L		 5038 for (j = 0; j < MAX_OPERANDS; j++)
5039 {
5040 if (operand_types[j].bitfield.disp64)
5041 {
5042 addr_prefix_disp = j;
5043 operand_types[j].bitfield.disp64 = 0;
5044 operand_types[j].bitfield.disp32 = 1;
5045 break;
5046 }
5047 }
539e75ad
L		 5048 break;
5049 }
539e75ad
L		 5050 }
5051
02a86693
L		 5052 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
5053 if (i.reloc[0] == BFD_RELOC_386_GOT32 && t->base_opcode == 0xa0)
5054 continue;
5055
56ffb741
L		 5056 /* We check register size if needed. */
5057 check_register = t->opcode_modifier.checkregsize;
c6fb90c8 5058 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 5059 switch (t->operands)
5060 {
5061 case 1:
40fb9820 5062 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 5063 continue;
5064 break;
5065 case 2:
33eaf5de 5066 /* xchg %eax, %eax is a special case. It is an alias for nop
8b38ad71
L		 5067 only in 32bit mode and we can use opcode 0x90. In 64bit
5068 mode, we can't use 0x90 for xchg %eax, %eax since it should
5069 zero-extend %eax to %rax. */
5070 if (flag_code == CODE_64BIT
5071 && t->base_opcode == 0x90
0dfbf9d7
L		 5072 && operand_type_equal (&i.types [0], &acc32)
5073 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 5074 continue;
86fa6981
L		 5075 /* If we want store form, we reverse direction of operands. */
5076 if (i.dir_encoding == dir_encoding_store
5077 && t->opcode_modifier.d)
5078 goto check_reverse;
1a0670f3 5079 /* Fall through. */
b6169b20 5080
29b0f896 5081 case 3:
86fa6981
L		 5082 /* If we want store form, we skip the current load. */
5083 if (i.dir_encoding == dir_encoding_store
5084 && i.mem_operands == 0
5085 && t->opcode_modifier.load)
fa99fab2 5086 continue;
1a0670f3 5087 /* Fall through. */
f48ff2ae 5088 case 4:
c0f3af97 5089 case 5:
c6fb90c8 5090 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 5091 if (!operand_type_match (overlap0, i.types[0])
5092 || !operand_type_match (overlap1, i.types[1])
45664ddb 5093 || (check_register
dc821c5f 5094 && !operand_type_register_match (i.types[0],
40fb9820 5095 operand_types[0],
dc821c5f 5096 i.types[1],
40fb9820 5097 operand_types[1])))
29b0f896
AM		 5098 {
5099 /* Check if other direction is valid ... */
40fb9820 5100 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 5101 continue;
5102
b6169b20 5103check_reverse:
29b0f896 5104 /* Try reversing direction of operands. */
c6fb90c8
L		 5105 overlap0 = operand_type_and (i.types[0], operand_types[1]);
5106 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 5107 if (!operand_type_match (overlap0, i.types[0])
5108 || !operand_type_match (overlap1, i.types[1])
45664ddb 5109 || (check_register
dc821c5f 5110 && !operand_type_register_match (i.types[0],
45664ddb 5111 operand_types[1],
45664ddb
L		 5112 i.types[1],
5113 operand_types[0])))
29b0f896
AM		 5114 {
5115 /* Does not match either direction. */
5116 continue;
5117 }
5118 /* found_reverse_match holds which of D or FloatDR
5119 we've found. */
40fb9820 5120 if (t->opcode_modifier.d)
8a2ed489 5121 found_reverse_match = Opcode_D;
40fb9820 5122 else if (t->opcode_modifier.floatd)
8a2ed489
L		 5123 found_reverse_match = Opcode_FloatD;
5124 else
5125 found_reverse_match = 0;
40fb9820 5126 if (t->opcode_modifier.floatr)
8a2ed489 5127 found_reverse_match |= Opcode_FloatR;
29b0f896 5128 }
f48ff2ae 5129 else
29b0f896 5130 {
f48ff2ae 5131 /* Found a forward 2 operand match here. */
d1cbb4db
L		 5132 switch (t->operands)
5133 {
c0f3af97
L		 5134 case 5:
5135 overlap4 = operand_type_and (i.types[4],
5136 operand_types[4]);
1a0670f3 5137 /* Fall through. */
d1cbb4db 5138 case 4:
c6fb90c8
L		 5139 overlap3 = operand_type_and (i.types[3],
5140 operand_types[3]);
1a0670f3 5141 /* Fall through. */
d1cbb4db 5142 case 3:
c6fb90c8
L		 5143 overlap2 = operand_type_and (i.types[2],
5144 operand_types[2]);
d1cbb4db
L		 5145 break;
5146 }
29b0f896 5147
f48ff2ae
L		 5148 switch (t->operands)
5149 {
c0f3af97
L		 5150 case 5:
5151 if (!operand_type_match (overlap4, i.types[4])
dc821c5f 5152 || !operand_type_register_match (i.types[3],
c0f3af97 5153 operand_types[3],
c0f3af97
L		 5154 i.types[4],
5155 operand_types[4]))
5156 continue;
1a0670f3 5157 /* Fall through. */
f48ff2ae 5158 case 4:
40fb9820 5159 if (!operand_type_match (overlap3, i.types[3])
45664ddb 5160 || (check_register
dc821c5f 5161 && !operand_type_register_match (i.types[2],
45664ddb 5162 operand_types[2],
45664ddb
L		 5163 i.types[3],
5164 operand_types[3])))
f48ff2ae 5165 continue;
1a0670f3 5166 /* Fall through. */
f48ff2ae
L		 5167 case 3:
5168 /* Here we make use of the fact that there are no
5169 reverse match 3 operand instructions, and all 3
5170 operand instructions only need to be checked for
5171 register consistency between operands 2 and 3. */
40fb9820 5172 if (!operand_type_match (overlap2, i.types[2])
45664ddb 5173 || (check_register
dc821c5f 5174 && !operand_type_register_match (i.types[1],
45664ddb 5175 operand_types[1],
45664ddb
L		 5176 i.types[2],
5177 operand_types[2])))
f48ff2ae
L		 5178 continue;
5179 break;
5180 }
29b0f896 5181 }
f48ff2ae 5182 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 5183 slip through to break. */
5184 }
3629bb00 5185 if (!found_cpu_match)
29b0f896
AM		 5186 {
5187 found_reverse_match = 0;
5188 continue;
5189 }
c0f3af97 5190
5614d22c
JB		 5191 /* Check if vector and VEX operands are valid. */
5192 if (check_VecOperands (t) || VEX_check_operands (t))
5193 {
5194 specific_error = i.error;
5195 continue;
5196 }
a683cc34 5197
29b0f896
AM		 5198 /* We've found a match; break out of loop. */
5199 break;
5200 }
5201
5202 if (t == current_templates->end)
5203 {
5204 /* We found no match. */
a65babc9 5205 const char *err_msg;
5614d22c 5206 switch (specific_error ? specific_error : i.error)
a65babc9
L		 5207 {
5208 default:
5209 abort ();
86e026a4 5210 case operand_size_mismatch:
a65babc9
L		 5211 err_msg = _("operand size mismatch");
5212 break;
5213 case operand_type_mismatch:
5214 err_msg = _("operand type mismatch");
5215 break;
5216 case register_type_mismatch:
5217 err_msg = _("register type mismatch");
5218 break;
5219 case number_of_operands_mismatch:
5220 err_msg = _("number of operands mismatch");
5221 break;
5222 case invalid_instruction_suffix:
5223 err_msg = _("invalid instruction suffix");
5224 break;
5225 case bad_imm4:
4a2608e3 5226 err_msg = _("constant doesn't fit in 4 bits");
a65babc9
L		 5227 break;
5228 case old_gcc_only:
5229 err_msg = _("only supported with old gcc");
5230 break;
5231 case unsupported_with_intel_mnemonic:
5232 err_msg = _("unsupported with Intel mnemonic");
5233 break;
5234 case unsupported_syntax:
5235 err_msg = _("unsupported syntax");
5236 break;
5237 case unsupported:
35262a23 5238 as_bad (_("unsupported instruction `%s'"),
10efe3f6
L		 5239 current_templates->start->name);
5240 return NULL;
6c30d220
L		 5241 case invalid_vsib_address:
5242 err_msg = _("invalid VSIB address");
5243 break;
7bab8ab5
JB		 5244 case invalid_vector_register_set:
5245 err_msg = _("mask, index, and destination registers must be distinct");
5246 break;
6c30d220
L		 5247 case unsupported_vector_index_register:
5248 err_msg = _("unsupported vector index register");
5249 break;
43234a1e
L		 5250 case unsupported_broadcast:
5251 err_msg = _("unsupported broadcast");
5252 break;
5253 case broadcast_not_on_src_operand:
5254 err_msg = _("broadcast not on source memory operand");
5255 break;
5256 case broadcast_needed:
5257 err_msg = _("broadcast is needed for operand of such type");
5258 break;
5259 case unsupported_masking:
5260 err_msg = _("unsupported masking");
5261 break;
5262 case mask_not_on_destination:
5263 err_msg = _("mask not on destination operand");
5264 break;
5265 case no_default_mask:
5266 err_msg = _("default mask isn't allowed");
5267 break;
5268 case unsupported_rc_sae:
5269 err_msg = _("unsupported static rounding/sae");
5270 break;
5271 case rc_sae_operand_not_last_imm:
5272 if (intel_syntax)
5273 err_msg = _("RC/SAE operand must precede immediate operands");
5274 else
5275 err_msg = _("RC/SAE operand must follow immediate operands");
5276 break;
5277 case invalid_register_operand:
5278 err_msg = _("invalid register operand");
5279 break;
a65babc9
L		 5280 }
5281 as_bad (_("%s for `%s'"), err_msg,
891edac4 5282 current_templates->start->name);
fa99fab2 5283 return NULL;
29b0f896 5284 }
252b5132 5285
29b0f896
AM		 5286 if (!quiet_warnings)
5287 {
5288 if (!intel_syntax
40fb9820
L		 5289 && (i.types[0].bitfield.jumpabsolute
5290 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 5291 {
5292 as_warn (_("indirect %s without `*'"), t->name);
5293 }
5294
40fb9820
L		 5295 if (t->opcode_modifier.isprefix
5296 && t->opcode_modifier.ignoresize)
29b0f896
AM		 5297 {
5298 /* Warn them that a data or address size prefix doesn't
5299 affect assembly of the next line of code. */
5300 as_warn (_("stand-alone `%s' prefix"), t->name);
5301 }
5302 }
5303
5304 /* Copy the template we found. */
5305 i.tm = *t;
539e75ad
L		 5306
5307 if (addr_prefix_disp != -1)
5308 i.tm.operand_types[addr_prefix_disp]
5309 = operand_types[addr_prefix_disp];
5310
29b0f896
AM		 5311 if (found_reverse_match)
5312 {
5313 /* If we found a reverse match we must alter the opcode
5314 direction bit. found_reverse_match holds bits to change
5315 (different for int & float insns). */
5316
5317 i.tm.base_opcode ^= found_reverse_match;
5318
539e75ad
L		 5319 i.tm.operand_types[0] = operand_types[1];
5320 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 5321 }
5322
fa99fab2 5323 return t;
29b0f896
AM		 5324}
5325
5326static int
e3bb37b5 5327check_string (void)
29b0f896 5328{
40fb9820
L		 5329 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5330 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 5331 {
5332 if (i.seg[0] != NULL && i.seg[0] != &es)
5333 {
a87af027 5334 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5335 i.tm.name,
a87af027
JB		 5336 mem_op + 1,
5337 register_prefix);
29b0f896
AM		 5338 return 0;
5339 }
5340 /* There's only ever one segment override allowed per instruction.
5341 This instruction possibly has a legal segment override on the
5342 second operand, so copy the segment to where non-string
5343 instructions store it, allowing common code. */
5344 i.seg[0] = i.seg[1];
5345 }
40fb9820 5346 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 5347 {
5348 if (i.seg[1] != NULL && i.seg[1] != &es)
5349 {
a87af027 5350 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 5351 i.tm.name,
a87af027
JB		 5352 mem_op + 2,
5353 register_prefix);
29b0f896
AM		 5354 return 0;
5355 }
5356 }
5357 return 1;
5358}
5359
5360static int
543613e9 5361process_suffix (void)
29b0f896
AM		 5362{
5363 /* If matched instruction specifies an explicit instruction mnemonic
5364 suffix, use it. */
40fb9820
L		 5365 if (i.tm.opcode_modifier.size16)
5366 i.suffix = WORD_MNEM_SUFFIX;
5367 else if (i.tm.opcode_modifier.size32)
5368 i.suffix = LONG_MNEM_SUFFIX;
5369 else if (i.tm.opcode_modifier.size64)
5370 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 5371 else if (i.reg_operands)
5372 {
5373 /* If there's no instruction mnemonic suffix we try to invent one
5374 based on register operands. */
5375 if (!i.suffix)
5376 {
5377 /* We take i.suffix from the last register operand specified,
5378 Destination register type is more significant than source
381d071f
L		 5379 register type. crc32 in SSE4.2 prefers source register
5380 type. */
5381 if (i.tm.base_opcode == 0xf20f38f1)
5382 {
dc821c5f 5383 if (i.types[0].bitfield.reg && i.types[0].bitfield.word)
40fb9820 5384 i.suffix = WORD_MNEM_SUFFIX;
dc821c5f 5385 else if (i.types[0].bitfield.reg && i.types[0].bitfield.dword)
40fb9820 5386 i.suffix = LONG_MNEM_SUFFIX;
dc821c5f 5387 else if (i.types[0].bitfield.reg && i.types[0].bitfield.qword)
40fb9820 5388 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 5389 }
9344ff29 5390 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 5391 {
dc821c5f 5392 if (i.types[0].bitfield.reg && i.types[0].bitfield.byte)
20592a94
L		 5393 i.suffix = BYTE_MNEM_SUFFIX;
5394 }
381d071f
L		 5395
5396 if (!i.suffix)
5397 {
5398 int op;
5399
20592a94
L		 5400 if (i.tm.base_opcode == 0xf20f38f1
5401 || i.tm.base_opcode == 0xf20f38f0)
5402 {
5403 /* We have to know the operand size for crc32. */
5404 as_bad (_("ambiguous memory operand size for `%s`"),
5405 i.tm.name);
5406 return 0;
5407 }
5408
381d071f 5409 for (op = i.operands; --op >= 0;)
b76bc5d5
JB		 5410 if (!i.tm.operand_types[op].bitfield.inoutportreg
5411 && !i.tm.operand_types[op].bitfield.shiftcount)
381d071f 5412 {
dc821c5f 5413 if (i.types[op].bitfield.reg && i.types[op].bitfield.byte)
40fb9820
L		 5414 {
5415 i.suffix = BYTE_MNEM_SUFFIX;
5416 break;
5417 }
dc821c5f 5418 if (i.types[op].bitfield.reg && i.types[op].bitfield.word)
40fb9820
L		 5419 {
5420 i.suffix = WORD_MNEM_SUFFIX;
5421 break;
5422 }
dc821c5f 5423 if (i.types[op].bitfield.reg && i.types[op].bitfield.dword)
40fb9820
L		 5424 {
5425 i.suffix = LONG_MNEM_SUFFIX;
5426 break;
5427 }
dc821c5f 5428 if (i.types[op].bitfield.reg && i.types[op].bitfield.qword)
40fb9820
L		 5429 {
5430 i.suffix = QWORD_MNEM_SUFFIX;
5431 break;
5432 }
381d071f
L		 5433 }
5434 }
29b0f896
AM		 5435 }
5436 else if (i.suffix == BYTE_MNEM_SUFFIX)
5437 {
2eb952a4
L		 5438 if (intel_syntax
5439 && i.tm.opcode_modifier.ignoresize
5440 && i.tm.opcode_modifier.no_bsuf)
5441 i.suffix = 0;
5442 else if (!check_byte_reg ())
29b0f896
AM		 5443 return 0;
5444 }
5445 else if (i.suffix == LONG_MNEM_SUFFIX)
5446 {
2eb952a4
L		 5447 if (intel_syntax
5448 && i.tm.opcode_modifier.ignoresize
5449 && i.tm.opcode_modifier.no_lsuf)
5450 i.suffix = 0;
5451 else if (!check_long_reg ())
29b0f896
AM		 5452 return 0;
5453 }
5454 else if (i.suffix == QWORD_MNEM_SUFFIX)
5455 {
955e1e6a
L		 5456 if (intel_syntax
5457 && i.tm.opcode_modifier.ignoresize
5458 && i.tm.opcode_modifier.no_qsuf)
5459 i.suffix = 0;
5460 else if (!check_qword_reg ())
29b0f896
AM		 5461 return 0;
5462 }
5463 else if (i.suffix == WORD_MNEM_SUFFIX)
5464 {
2eb952a4
L		 5465 if (intel_syntax
5466 && i.tm.opcode_modifier.ignoresize
5467 && i.tm.opcode_modifier.no_wsuf)
5468 i.suffix = 0;
5469 else if (!check_word_reg ())
29b0f896
AM		 5470 return 0;
5471 }
c0f3af97 5472 else if (i.suffix == XMMWORD_MNEM_SUFFIX
43234a1e
L		 5473 || i.suffix == YMMWORD_MNEM_SUFFIX
5474 || i.suffix == ZMMWORD_MNEM_SUFFIX)
582d5edd 5475 {
43234a1e 5476 /* Skip if the instruction has x/y/z suffix. match_template
582d5edd
L		 5477 should check if it is a valid suffix. */
5478 }
40fb9820 5479 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 5480 /* Do nothing if the instruction is going to ignore the prefix. */
5481 ;
5482 else
5483 abort ();
5484 }
40fb9820 5485 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 5486 && !i.suffix
5487 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 5488 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 5489 {
5490 i.suffix = stackop_size;
5491 }
9306ca4a
JB		 5492 else if (intel_syntax
5493 && !i.suffix
40fb9820
L		 5494 && (i.tm.operand_types[0].bitfield.jumpabsolute
5495 || i.tm.opcode_modifier.jumpbyte
5496 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 5497 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5498 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 5499 {
5500 switch (flag_code)
5501 {
5502 case CODE_64BIT:
40fb9820 5503 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 5504 {
5505 i.suffix = QWORD_MNEM_SUFFIX;
5506 break;
5507 }
1a0670f3 5508 /* Fall through. */
9306ca4a 5509 case CODE_32BIT:
40fb9820 5510 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 5511 i.suffix = LONG_MNEM_SUFFIX;
5512 break;
5513 case CODE_16BIT:
40fb9820 5514 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 5515 i.suffix = WORD_MNEM_SUFFIX;
5516 break;
5517 }
5518 }
252b5132 5519
9306ca4a 5520 if (!i.suffix)
29b0f896 5521 {
9306ca4a
JB		 5522 if (!intel_syntax)
5523 {
40fb9820 5524 if (i.tm.opcode_modifier.w)
9306ca4a 5525 {
4eed87de
AM		 5526 as_bad (_("no instruction mnemonic suffix given and "
5527 "no register operands; can't size instruction"));
9306ca4a
JB		 5528 return 0;
5529 }
5530 }
5531 else
5532 {
40fb9820 5533 unsigned int suffixes;
7ab9ffdd 5534
40fb9820
L		 5535 suffixes = !i.tm.opcode_modifier.no_bsuf;
5536 if (!i.tm.opcode_modifier.no_wsuf)
5537 suffixes |= 1 << 1;
5538 if (!i.tm.opcode_modifier.no_lsuf)
5539 suffixes |= 1 << 2;
fc4adea1 5540 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 5541 suffixes |= 1 << 3;
5542 if (!i.tm.opcode_modifier.no_ssuf)
5543 suffixes |= 1 << 4;
c2b9da16 5544 if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf)
40fb9820
L		 5545 suffixes |= 1 << 5;
5546
5547 /* There are more than suffix matches. */
5548 if (i.tm.opcode_modifier.w
9306ca4a 5549 || ((suffixes & (suffixes - 1))
40fb9820
L		 5550 && !i.tm.opcode_modifier.defaultsize
5551 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 5552 {
5553 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5554 return 0;
5555 }
5556 }
29b0f896 5557 }
252b5132 5558
9306ca4a
JB		 5559 /* Change the opcode based on the operand size given by i.suffix;
5560 We don't need to change things for byte insns. */
5561
582d5edd
L		 5562 if (i.suffix
5563 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97 5564 && i.suffix != XMMWORD_MNEM_SUFFIX
43234a1e
L		 5565 && i.suffix != YMMWORD_MNEM_SUFFIX
5566 && i.suffix != ZMMWORD_MNEM_SUFFIX)
29b0f896
AM		 5567 {
5568 /* It's not a byte, select word/dword operation. */
40fb9820 5569 if (i.tm.opcode_modifier.w)
29b0f896 5570 {
40fb9820 5571 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 5572 i.tm.base_opcode |= 8;
5573 else
5574 i.tm.base_opcode |= 1;
5575 }
0f3f3d8b 5576
29b0f896
AM		 5577 /* Now select between word & dword operations via the operand
5578 size prefix, except for instructions that will ignore this
5579 prefix anyway. */
ca61edf2 5580 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 5581 {
ca61edf2
L		 5582 /* The address size override prefix changes the size of the
5583 first operand. */
40fb9820 5584 if ((flag_code == CODE_32BIT
dc821c5f 5585 && i.op->regs[0].reg_type.bitfield.word)
40fb9820 5586 || (flag_code != CODE_32BIT
dc821c5f 5587 && i.op->regs[0].reg_type.bitfield.dword))
cb712a9e
L		 5588 if (!add_prefix (ADDR_PREFIX_OPCODE))
5589 return 0;
5590 }
5591 else if (i.suffix != QWORD_MNEM_SUFFIX
5592 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 5593 && !i.tm.opcode_modifier.ignoresize
5594 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 5595 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5596 || (flag_code == CODE_64BIT
40fb9820 5597 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 5598 {
5599 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 5600
40fb9820 5601 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 5602 prefix = ADDR_PREFIX_OPCODE;
252b5132 5603
29b0f896
AM		 5604 if (!add_prefix (prefix))
5605 return 0;
24eab124 5606 }
252b5132 5607
29b0f896
AM		 5608 /* Set mode64 for an operand. */
5609 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 5610 && flag_code == CODE_64BIT
40fb9820 5611 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 5612 {
5613 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 5614 need rex64. cmpxchg8b is also a special case. */
5615 if (! (i.operands == 2
5616 && i.tm.base_opcode == 0x90
5617 && i.tm.extension_opcode == None
0dfbf9d7
L		 5618 && operand_type_equal (&i.types [0], &acc64)
5619 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 5620 && ! (i.operands == 1
5621 && i.tm.base_opcode == 0xfc7
5622 && i.tm.extension_opcode == 1
40fb9820
L		 5623 && !operand_type_check (i.types [0], reg)
5624 && operand_type_check (i.types [0], anymem)))
f6bee062 5625 i.rex |= REX_W;
46e883c5 5626 }
3e73aa7c 5627
29b0f896
AM		 5628 /* Size floating point instruction. */
5629 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 5630 if (i.tm.opcode_modifier.floatmf)
543613e9 5631 i.tm.base_opcode ^= 4;
29b0f896 5632 }
7ecd2f8b 5633
29b0f896
AM		 5634 return 1;
5635}
3e73aa7c 5636
29b0f896 5637static int
543613e9 5638check_byte_reg (void)
29b0f896
AM		 5639{
5640 int op;
543613e9 5641
29b0f896
AM		 5642 for (op = i.operands; --op >= 0;)
5643 {
dc821c5f
JB		 5644 /* Skip non-register operands. */
5645 if (!i.types[op].bitfield.reg)
5646 continue;
5647
29b0f896
AM		 5648 /* If this is an eight bit register, it's OK. If it's the 16 or
5649 32 bit version of an eight bit register, we will just use the
5650 low portion, and that's OK too. */
dc821c5f 5651 if (i.types[op].bitfield.byte)
29b0f896
AM		 5652 continue;
5653
5a819eb9
JB		 5654 /* I/O port address operands are OK too. */
5655 if (i.tm.operand_types[op].bitfield.inoutportreg)
5656 continue;
5657
9344ff29
L		 5658 /* crc32 doesn't generate this warning. */
5659 if (i.tm.base_opcode == 0xf20f38f0)
5660 continue;
5661
dc821c5f
JB		 5662 if ((i.types[op].bitfield.word
5663 || i.types[op].bitfield.dword
5664 || i.types[op].bitfield.qword)
5a819eb9
JB		 5665 && i.op[op].regs->reg_num < 4
5666 /* Prohibit these changes in 64bit mode, since the lowering
5667 would be more complicated. */
5668 && flag_code != CODE_64BIT)
29b0f896 5669 {
29b0f896 5670#if REGISTER_WARNINGS
5a819eb9 5671 if (!quiet_warnings)
a540244d
L		 5672 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5673 register_prefix,
dc821c5f 5674 (i.op[op].regs + (i.types[op].bitfield.word
29b0f896
AM		 5675 ? REGNAM_AL - REGNAM_AX
5676 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 5677 register_prefix,
29b0f896
AM		 5678 i.op[op].regs->reg_name,
5679 i.suffix);
5680#endif
5681 continue;
5682 }
5683 /* Any other register is bad. */
dc821c5f 5684 if (i.types[op].bitfield.reg
40fb9820 5685 || i.types[op].bitfield.regmmx
1b54b8d7 5686 || i.types[op].bitfield.regsimd
40fb9820
L		 5687 || i.types[op].bitfield.sreg2
5688 || i.types[op].bitfield.sreg3
5689 || i.types[op].bitfield.control
5690 || i.types[op].bitfield.debug
ca0d63fe 5691 || i.types[op].bitfield.test)
29b0f896 5692 {
a540244d
L		 5693 as_bad (_("`%s%s' not allowed with `%s%c'"),
5694 register_prefix,
29b0f896
AM		 5695 i.op[op].regs->reg_name,
5696 i.tm.name,
5697 i.suffix);
5698 return 0;
5699 }
5700 }
5701 return 1;
5702}
5703
5704static int
e3bb37b5 5705check_long_reg (void)
29b0f896
AM		 5706{
5707 int op;
5708
5709 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 5710 /* Skip non-register operands. */
5711 if (!i.types[op].bitfield.reg)
5712 continue;
29b0f896
AM		 5713 /* Reject eight bit registers, except where the template requires
5714 them. (eg. movzb) */
dc821c5f
JB		 5715 else if (i.types[op].bitfield.byte
5716 && (i.tm.operand_types[op].bitfield.reg
5717 || i.tm.operand_types[op].bitfield.acc)
5718 && (i.tm.operand_types[op].bitfield.word
5719 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5720 {
a540244d
L		 5721 as_bad (_("`%s%s' not allowed with `%s%c'"),
5722 register_prefix,
29b0f896
AM		 5723 i.op[op].regs->reg_name,
5724 i.tm.name,
5725 i.suffix);
5726 return 0;
5727 }
e4630f71 5728 /* Warn if the e prefix on a general reg is missing. */
29b0f896 5729 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 5730 && i.types[op].bitfield.word
5731 && (i.tm.operand_types[op].bitfield.reg
5732 || i.tm.operand_types[op].bitfield.acc)
5733 && i.tm.operand_types[op].bitfield.dword)
29b0f896
AM		 5734 {
5735 /* Prohibit these changes in the 64bit mode, since the
5736 lowering is more complicated. */
5737 if (flag_code == CODE_64BIT)
252b5132 5738 {
2b5d6a91 5739 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5740 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5741 i.suffix);
5742 return 0;
252b5132 5743 }
29b0f896 5744#if REGISTER_WARNINGS
cecf1424
JB		 5745 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5746 register_prefix,
5747 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5748 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896 5749#endif
252b5132 5750 }
e4630f71 5751 /* Warn if the r prefix on a general reg is present. */
dc821c5f
JB		 5752 else if (i.types[op].bitfield.qword
5753 && (i.tm.operand_types[op].bitfield.reg
5754 || i.tm.operand_types[op].bitfield.acc)
5755 && i.tm.operand_types[op].bitfield.dword)
252b5132 5756 {
34828aad 5757 if (intel_syntax
ca61edf2 5758 && i.tm.opcode_modifier.toqword
1b54b8d7 5759 && !i.types[0].bitfield.regsimd)
34828aad 5760 {
ca61edf2 5761 /* Convert to QWORD. We want REX byte. */
34828aad
L		 5762 i.suffix = QWORD_MNEM_SUFFIX;
5763 }
5764 else
5765 {
2b5d6a91 5766 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5767 register_prefix, i.op[op].regs->reg_name,
5768 i.suffix);
5769 return 0;
5770 }
29b0f896
AM		 5771 }
5772 return 1;
5773}
252b5132 5774
29b0f896 5775static int
e3bb37b5 5776check_qword_reg (void)
29b0f896
AM		 5777{
5778 int op;
252b5132 5779
29b0f896 5780 for (op = i.operands; --op >= 0; )
dc821c5f
JB		 5781 /* Skip non-register operands. */
5782 if (!i.types[op].bitfield.reg)
5783 continue;
29b0f896
AM		 5784 /* Reject eight bit registers, except where the template requires
5785 them. (eg. movzb) */
dc821c5f
JB		 5786 else if (i.types[op].bitfield.byte
5787 && (i.tm.operand_types[op].bitfield.reg
5788 || i.tm.operand_types[op].bitfield.acc)
5789 && (i.tm.operand_types[op].bitfield.word
5790 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5791 {
a540244d
L		 5792 as_bad (_("`%s%s' not allowed with `%s%c'"),
5793 register_prefix,
29b0f896
AM		 5794 i.op[op].regs->reg_name,
5795 i.tm.name,
5796 i.suffix);
5797 return 0;
5798 }
e4630f71 5799 /* Warn if the r prefix on a general reg is missing. */
dc821c5f
JB		 5800 else if ((i.types[op].bitfield.word
5801 || i.types[op].bitfield.dword)
5802 && (i.tm.operand_types[op].bitfield.reg
5803 || i.tm.operand_types[op].bitfield.acc)
5804 && i.tm.operand_types[op].bitfield.qword)
29b0f896
AM		 5805 {
5806 /* Prohibit these changes in the 64bit mode, since the
5807 lowering is more complicated. */
34828aad 5808 if (intel_syntax
ca61edf2 5809 && i.tm.opcode_modifier.todword
1b54b8d7 5810 && !i.types[0].bitfield.regsimd)
34828aad 5811 {
ca61edf2 5812 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 5813 i.suffix = LONG_MNEM_SUFFIX;
5814 }
5815 else
5816 {
2b5d6a91 5817 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
34828aad
L		 5818 register_prefix, i.op[op].regs->reg_name,
5819 i.suffix);
5820 return 0;
5821 }
252b5132 5822 }
29b0f896
AM		 5823 return 1;
5824}
252b5132 5825
29b0f896 5826static int
e3bb37b5 5827check_word_reg (void)
29b0f896
AM		 5828{
5829 int op;
5830 for (op = i.operands; --op >= 0;)
dc821c5f
JB		 5831 /* Skip non-register operands. */
5832 if (!i.types[op].bitfield.reg)
5833 continue;
29b0f896
AM		 5834 /* Reject eight bit registers, except where the template requires
5835 them. (eg. movzb) */
dc821c5f
JB		 5836 else if (i.types[op].bitfield.byte
5837 && (i.tm.operand_types[op].bitfield.reg
5838 || i.tm.operand_types[op].bitfield.acc)
5839 && (i.tm.operand_types[op].bitfield.word
5840 || i.tm.operand_types[op].bitfield.dword))
29b0f896 5841 {
a540244d
L		 5842 as_bad (_("`%s%s' not allowed with `%s%c'"),
5843 register_prefix,
29b0f896
AM		 5844 i.op[op].regs->reg_name,
5845 i.tm.name,
5846 i.suffix);
5847 return 0;
5848 }
e4630f71 5849 /* Warn if the e or r prefix on a general reg is present. */
29b0f896 5850 else if ((!quiet_warnings || flag_code == CODE_64BIT)
dc821c5f
JB		 5851 && (i.types[op].bitfield.dword
5852 || i.types[op].bitfield.qword)
5853 && (i.tm.operand_types[op].bitfield.reg
5854 || i.tm.operand_types[op].bitfield.acc)
5855 && i.tm.operand_types[op].bitfield.word)
252b5132 5856 {
29b0f896
AM		 5857 /* Prohibit these changes in the 64bit mode, since the
5858 lowering is more complicated. */
5859 if (flag_code == CODE_64BIT)
252b5132 5860 {
2b5d6a91 5861 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
2ca3ace5 5862 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 5863 i.suffix);
5864 return 0;
252b5132 5865 }
29b0f896 5866#if REGISTER_WARNINGS
cecf1424
JB		 5867 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5868 register_prefix,
5869 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5870 register_prefix, i.op[op].regs->reg_name, i.suffix);
29b0f896
AM		 5871#endif
5872 }
5873 return 1;
5874}
252b5132 5875
29b0f896 5876static int
40fb9820 5877update_imm (unsigned int j)
29b0f896 5878{
bc0844ae 5879 i386_operand_type overlap = i.types[j];
40fb9820
L		 5880 if ((overlap.bitfield.imm8
5881 || overlap.bitfield.imm8s
5882 || overlap.bitfield.imm16
5883 || overlap.bitfield.imm32
5884 || overlap.bitfield.imm32s
5885 || overlap.bitfield.imm64)
0dfbf9d7
L		 5886 && !operand_type_equal (&overlap, &imm8)
5887 && !operand_type_equal (&overlap, &imm8s)
5888 && !operand_type_equal (&overlap, &imm16)
5889 && !operand_type_equal (&overlap, &imm32)
5890 && !operand_type_equal (&overlap, &imm32s)
5891 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 5892 {
5893 if (i.suffix)
5894 {
40fb9820
L		 5895 i386_operand_type temp;
5896
0dfbf9d7 5897 operand_type_set (&temp, 0);
7ab9ffdd 5898 if (i.suffix == BYTE_MNEM_SUFFIX)
40fb9820
L		 5899 {
5900 temp.bitfield.imm8 = overlap.bitfield.imm8;
5901 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5902 }
5903 else if (i.suffix == WORD_MNEM_SUFFIX)
5904 temp.bitfield.imm16 = overlap.bitfield.imm16;
5905 else if (i.suffix == QWORD_MNEM_SUFFIX)
5906 {
5907 temp.bitfield.imm64 = overlap.bitfield.imm64;
5908 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5909 }
5910 else
5911 temp.bitfield.imm32 = overlap.bitfield.imm32;
5912 overlap = temp;
29b0f896 5913 }
0dfbf9d7
L		 5914 else if (operand_type_equal (&overlap, &imm16_32_32s)
5915 || operand_type_equal (&overlap, &imm16_32)
5916 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 5917 {
40fb9820 5918 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 5919 overlap = imm16;
40fb9820 5920 else
65da13b5 5921 overlap = imm32s;
29b0f896 5922 }
0dfbf9d7
L		 5923 if (!operand_type_equal (&overlap, &imm8)
5924 && !operand_type_equal (&overlap, &imm8s)
5925 && !operand_type_equal (&overlap, &imm16)
5926 && !operand_type_equal (&overlap, &imm32)
5927 && !operand_type_equal (&overlap, &imm32s)
5928 && !operand_type_equal (&overlap, &imm64))
29b0f896 5929 {
4eed87de
AM		 5930 as_bad (_("no instruction mnemonic suffix given; "
5931 "can't determine immediate size"));
29b0f896
AM		 5932 return 0;
5933 }
5934 }
40fb9820 5935 i.types[j] = overlap;
29b0f896 5936
40fb9820
L		 5937 return 1;
5938}
5939
5940static int
5941finalize_imm (void)
5942{
bc0844ae 5943 unsigned int j, n;
29b0f896 5944
bc0844ae
L		 5945 /* Update the first 2 immediate operands. */
5946 n = i.operands > 2 ? 2 : i.operands;
5947 if (n)
5948 {
5949 for (j = 0; j < n; j++)
5950 if (update_imm (j) == 0)
5951 return 0;
40fb9820 5952
bc0844ae
L		 5953 /* The 3rd operand can't be immediate operand. */
5954 gas_assert (operand_type_check (i.types[2], imm) == 0);
5955 }
29b0f896
AM		 5956
5957 return 1;
5958}
5959
5960static int
e3bb37b5 5961process_operands (void)
29b0f896
AM		 5962{
5963 /* Default segment register this instruction will use for memory
5964 accesses. 0 means unknown. This is only for optimizing out
5965 unnecessary segment overrides. */
5966 const seg_entry *default_seg = 0;
5967
2426c15f 5968 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
29b0f896 5969 {
91d6fa6a
NC		 5970 unsigned int dupl = i.operands;
5971 unsigned int dest = dupl - 1;
9fcfb3d7
L		 5972 unsigned int j;
5973
c0f3af97 5974 /* The destination must be an xmm register. */
9c2799c2 5975 gas_assert (i.reg_operands
91d6fa6a 5976 && MAX_OPERANDS > dupl
7ab9ffdd 5977 && operand_type_equal (&i.types[dest], &regxmm));
c0f3af97 5978
1b54b8d7
JB		 5979 if (i.tm.operand_types[0].bitfield.acc
5980 && i.tm.operand_types[0].bitfield.xmmword)
e2ec9d29 5981 {
8cd7925b 5982 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
c0f3af97
L		 5983 {
5984 /* Keep xmm0 for instructions with VEX prefix and 3
5985 sources. */
1b54b8d7
JB		 5986 i.tm.operand_types[0].bitfield.acc = 0;
5987 i.tm.operand_types[0].bitfield.regsimd = 1;
c0f3af97
L		 5988 goto duplicate;
5989 }
e2ec9d29 5990 else
c0f3af97
L		 5991 {
5992 /* We remove the first xmm0 and keep the number of
5993 operands unchanged, which in fact duplicates the
5994 destination. */
5995 for (j = 1; j < i.operands; j++)
5996 {
5997 i.op[j - 1] = i.op[j];
5998 i.types[j - 1] = i.types[j];
5999 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
6000 }
6001 }
6002 }
6003 else if (i.tm.opcode_modifier.implicit1stxmm0)
7ab9ffdd 6004 {
91d6fa6a 6005 gas_assert ((MAX_OPERANDS - 1) > dupl
8cd7925b
L		 6006 && (i.tm.opcode_modifier.vexsources
6007 == VEX3SOURCES));
c0f3af97
L		 6008
6009 /* Add the implicit xmm0 for instructions with VEX prefix
6010 and 3 sources. */
6011 for (j = i.operands; j > 0; j--)
6012 {
6013 i.op[j] = i.op[j - 1];
6014 i.types[j] = i.types[j - 1];
6015 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
6016 }
6017 i.op[0].regs
6018 = (const reg_entry *) hash_find (reg_hash, "xmm0");
7ab9ffdd 6019 i.types[0] = regxmm;
c0f3af97
L		 6020 i.tm.operand_types[0] = regxmm;
6021
6022 i.operands += 2;
6023 i.reg_operands += 2;
6024 i.tm.operands += 2;
6025
91d6fa6a 6026 dupl++;
c0f3af97 6027 dest++;
91d6fa6a
NC		 6028 i.op[dupl] = i.op[dest];
6029 i.types[dupl] = i.types[dest];
6030 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
e2ec9d29 6031 }
c0f3af97
L		 6032 else
6033 {
6034duplicate:
6035 i.operands++;
6036 i.reg_operands++;
6037 i.tm.operands++;
6038
91d6fa6a
NC		 6039 i.op[dupl] = i.op[dest];
6040 i.types[dupl] = i.types[dest];
6041 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
c0f3af97
L		 6042 }
6043
6044 if (i.tm.opcode_modifier.immext)
6045 process_immext ();
6046 }
1b54b8d7
JB		 6047 else if (i.tm.operand_types[0].bitfield.acc
6048 && i.tm.operand_types[0].bitfield.xmmword)
c0f3af97
L		 6049 {
6050 unsigned int j;
6051
9fcfb3d7
L		 6052 for (j = 1; j < i.operands; j++)
6053 {
6054 i.op[j - 1] = i.op[j];
6055 i.types[j - 1] = i.types[j];
6056
6057 /* We need to adjust fields in i.tm since they are used by
6058 build_modrm_byte. */
6059 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
6060 }
6061
e2ec9d29
L		 6062 i.operands--;
6063 i.reg_operands--;
e2ec9d29
L		 6064 i.tm.operands--;
6065 }
920d2ddc
IT		 6066 else if (i.tm.opcode_modifier.implicitquadgroup)
6067 {
6068 /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */
6069 gas_assert (i.operands >= 2
6070 && (operand_type_equal (&i.types[1], &regxmm)
6071 || operand_type_equal (&i.types[1], &regymm)
6072 || operand_type_equal (&i.types[1], &regzmm)));
6073 unsigned int regnum = register_number (i.op[1].regs);
6074 unsigned int first_reg_in_group = regnum & ~3;
6075 unsigned int last_reg_in_group = first_reg_in_group + 3;
6076 if (regnum != first_reg_in_group) {
6077 as_warn (_("the second source register `%s%s' implicitly denotes"
6078 " `%s%.3s%d' to `%s%.3s%d' source group in `%s'"),
6079 register_prefix, i.op[1].regs->reg_name,
6080 register_prefix, i.op[1].regs->reg_name, first_reg_in_group,
6081 register_prefix, i.op[1].regs->reg_name, last_reg_in_group,
6082 i.tm.name);
6083 }
6084 }
e2ec9d29
L		 6085 else if (i.tm.opcode_modifier.regkludge)
6086 {
6087 /* The imul $imm, %reg instruction is converted into
6088 imul $imm, %reg, %reg, and the clr %reg instruction
6089 is converted into xor %reg, %reg. */
6090
6091 unsigned int first_reg_op;
6092
6093 if (operand_type_check (i.types[0], reg))
6094 first_reg_op = 0;
6095 else
6096 first_reg_op = 1;
6097 /* Pretend we saw the extra register operand. */
9c2799c2 6098 gas_assert (i.reg_operands == 1
7ab9ffdd 6099 && i.op[first_reg_op + 1].regs == 0);
e2ec9d29
L		 6100 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
6101 i.types[first_reg_op + 1] = i.types[first_reg_op];
6102 i.operands++;
6103 i.reg_operands++;
29b0f896
AM		 6104 }
6105
40fb9820 6106 if (i.tm.opcode_modifier.shortform)
29b0f896 6107 {
40fb9820
L		 6108 if (i.types[0].bitfield.sreg2
6109 || i.types[0].bitfield.sreg3)
29b0f896 6110 {
4eed87de
AM		 6111 if (i.tm.base_opcode == POP_SEG_SHORT
6112 && i.op[0].regs->reg_num == 1)
29b0f896 6113 {
a87af027 6114 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 6115 return 0;
29b0f896 6116 }
4eed87de
AM		 6117 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
6118 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 6119 i.rex |= REX_B;
4eed87de
AM		 6120 }
6121 else
6122 {
7ab9ffdd 6123 /* The register or float register operand is in operand
85f10a01 6124 0 or 1. */
40fb9820 6125 unsigned int op;
7ab9ffdd 6126
ca0d63fe 6127 if ((i.types[0].bitfield.reg && i.types[0].bitfield.tbyte)
7ab9ffdd
L		 6128 || operand_type_check (i.types[0], reg))
6129 op = 0;
6130 else
6131 op = 1;
4eed87de
AM		 6132 /* Register goes in low 3 bits of opcode. */
6133 i.tm.base_opcode |= i.op[op].regs->reg_num;
6134 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 6135 i.rex |= REX_B;
40fb9820 6136 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 6137 {
4eed87de
AM		 6138 /* Warn about some common errors, but press on regardless.
6139 The first case can be generated by gcc (<= 2.8.1). */
6140 if (i.operands == 2)
6141 {
6142 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 6143 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 6144 register_prefix, i.op[!intel_syntax].regs->reg_name,
6145 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 6146 }
6147 else
6148 {
6149 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 6150 as_warn (_("translating to `%s %s%s'"), i.tm.name,
6151 register_prefix, i.op[0].regs->reg_name);
4eed87de 6152 }
29b0f896
AM		 6153 }
6154 }
6155 }
40fb9820 6156 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 6157 {
6158 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 6159 must be put into the modrm byte). Now, we make the modrm and
6160 index base bytes based on all the info we've collected. */
29b0f896
AM		 6161
6162 default_seg = build_modrm_byte ();
6163 }
8a2ed489 6164 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 6165 {
6166 default_seg = &ds;
6167 }
40fb9820 6168 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 6169 {
6170 /* For the string instructions that allow a segment override
6171 on one of their operands, the default segment is ds. */
6172 default_seg = &ds;
6173 }
6174
75178d9d
L		 6175 if (i.tm.base_opcode == 0x8d /* lea */
6176 && i.seg[0]
6177 && !quiet_warnings)
30123838 6178 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 6179
6180 /* If a segment was explicitly specified, and the specified segment
6181 is not the default, use an opcode prefix to select it. If we
6182 never figured out what the default segment is, then default_seg
6183 will be zero at this point, and the specified segment prefix will
6184 always be used. */
29b0f896
AM		 6185 if ((i.seg[0]) && (i.seg[0] != default_seg))
6186 {
6187 if (!add_prefix (i.seg[0]->seg_prefix))
6188 return 0;
6189 }
6190 return 1;
6191}
6192
6193static const seg_entry *
e3bb37b5 6194build_modrm_byte (void)
29b0f896
AM		 6195{
6196 const seg_entry *default_seg = 0;
c0f3af97 6197 unsigned int source, dest;
8cd7925b 6198 int vex_3_sources;
c0f3af97
L		 6199
6200 /* The first operand of instructions with VEX prefix and 3 sources
6201 must be VEX_Imm4. */
8cd7925b 6202 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
c0f3af97
L		 6203 if (vex_3_sources)
6204 {
91d6fa6a 6205 unsigned int nds, reg_slot;
4c2c6516 6206 expressionS *exp;
c0f3af97 6207
922d8de8 6208 if (i.tm.opcode_modifier.veximmext
a683cc34
SP		 6209 && i.tm.opcode_modifier.immext)
6210 {
6211 dest = i.operands - 2;
6212 gas_assert (dest == 3);
6213 }
922d8de8 6214 else
a683cc34 6215 dest = i.operands - 1;
c0f3af97 6216 nds = dest - 1;
922d8de8 6217
a683cc34
SP		 6218 /* There are 2 kinds of instructions:
6219 1. 5 operands: 4 register operands or 3 register operands
6220 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
43234a1e
L		 6221 VexW0 or VexW1. The destination must be either XMM, YMM or
6222 ZMM register.
a683cc34
SP		 6223 2. 4 operands: 4 register operands or 3 register operands
6224 plus 1 memory operand, VexXDS, and VexImmExt */
922d8de8 6225 gas_assert ((i.reg_operands == 4
a683cc34
SP		 6226 || (i.reg_operands == 3 && i.mem_operands == 1))
6227 && i.tm.opcode_modifier.vexvvvv == VEXXDS
6228 && (i.tm.opcode_modifier.veximmext
6229 || (i.imm_operands == 1
6230 && i.types[0].bitfield.vec_imm4
6231 && (i.tm.opcode_modifier.vexw == VEXW0
6232 || i.tm.opcode_modifier.vexw == VEXW1)
6233 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
43234a1e
L		 6234 || operand_type_equal (&i.tm.operand_types[dest], &regymm)
6235 || operand_type_equal (&i.tm.operand_types[dest], &regzmm)))));
a683cc34
SP		 6236
6237 if (i.imm_operands == 0)
6238 {
6239 /* When there is no immediate operand, generate an 8bit
6240 immediate operand to encode the first operand. */
6241 exp = &im_expressions[i.imm_operands++];
6242 i.op[i.operands].imms = exp;
6243 i.types[i.operands] = imm8;
6244 i.operands++;
6245 /* If VexW1 is set, the first operand is the source and
6246 the second operand is encoded in the immediate operand. */
6247 if (i.tm.opcode_modifier.vexw == VEXW1)
6248 {
6249 source = 0;
6250 reg_slot = 1;
6251 }
6252 else
6253 {
6254 source = 1;
6255 reg_slot = 0;
6256 }
6257
6258 /* FMA swaps REG and NDS. */
6259 if (i.tm.cpu_flags.bitfield.cpufma)
6260 {
6261 unsigned int tmp;
6262 tmp = reg_slot;
6263 reg_slot = nds;
6264 nds = tmp;
6265 }
6266
24981e7b
L		 6267 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6268 &regxmm)
a683cc34 6269 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6270 &regymm)
6271 || operand_type_equal (&i.tm.operand_types[reg_slot],
6272 &regzmm));
a683cc34 6273 exp->X_op = O_constant;
4c692bc7 6274 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
43234a1e
L		 6275 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6276 }
922d8de8 6277 else
a683cc34
SP		 6278 {
6279 unsigned int imm_slot;
6280
6281 if (i.tm.opcode_modifier.vexw == VEXW0)
6282 {
6283 /* If VexW0 is set, the third operand is the source and
6284 the second operand is encoded in the immediate
6285 operand. */
6286 source = 2;
6287 reg_slot = 1;
6288 }
6289 else
6290 {
6291 /* VexW1 is set, the second operand is the source and
6292 the third operand is encoded in the immediate
6293 operand. */
6294 source = 1;
6295 reg_slot = 2;
6296 }
6297
6298 if (i.tm.opcode_modifier.immext)
6299 {
33eaf5de 6300 /* When ImmExt is set, the immediate byte is the last
a683cc34
SP		 6301 operand. */
6302 imm_slot = i.operands - 1;
6303 source--;
6304 reg_slot--;
6305 }
6306 else
6307 {
6308 imm_slot = 0;
6309
6310 /* Turn on Imm8 so that output_imm will generate it. */
6311 i.types[imm_slot].bitfield.imm8 = 1;
6312 }
6313
24981e7b
L		 6314 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6315 &regxmm)
6316 || operand_type_equal (&i.tm.operand_types[reg_slot],
43234a1e
L		 6317 &regymm)
6318 || operand_type_equal (&i.tm.operand_types[reg_slot],
6319 &regzmm));
a683cc34 6320 i.op[imm_slot].imms->X_add_number
4c692bc7 6321 |= register_number (i.op[reg_slot].regs) << 4;
43234a1e 6322 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
a683cc34
SP		 6323 }
6324
6325 gas_assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
6326 || operand_type_equal (&i.tm.operand_types[nds],
43234a1e
L		 6327 &regymm)
6328 || operand_type_equal (&i.tm.operand_types[nds],
6329 &regzmm));
dae39acc 6330 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 6331 }
6332 else
6333 source = dest = 0;
29b0f896
AM		 6334
6335 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 6336 implicit registers do not count. If there are 3 register
6337 operands, it must be a instruction with VexNDS. For a
6338 instruction with VexNDD, the destination register is encoded
6339 in VEX prefix. If there are 4 register operands, it must be
6340 a instruction with VEX prefix and 3 sources. */
7ab9ffdd
L		 6341 if (i.mem_operands == 0
6342 && ((i.reg_operands == 2
2426c15f 6343 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
7ab9ffdd 6344 || (i.reg_operands == 3
2426c15f 6345 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd 6346 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 6347 {
cab737b9
L		 6348 switch (i.operands)
6349 {
6350 case 2:
6351 source = 0;
6352 break;
6353 case 3:
c81128dc
L		 6354 /* When there are 3 operands, one of them may be immediate,
6355 which may be the first or the last operand. Otherwise,
c0f3af97
L		 6356 the first operand must be shift count register (cl) or it
6357 is an instruction with VexNDS. */
9c2799c2 6358 gas_assert (i.imm_operands == 1
7ab9ffdd 6359 || (i.imm_operands == 0
2426c15f 6360 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd 6361 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 6362 if (operand_type_check (i.types[0], imm)
6363 || i.types[0].bitfield.shiftcount)
6364 source = 1;
6365 else
6366 source = 0;
cab737b9
L		 6367 break;
6368 case 4:
368d64cc
L		 6369 /* When there are 4 operands, the first two must be 8bit
6370 immediate operands. The source operand will be the 3rd
c0f3af97
L		 6371 one.
6372
6373 For instructions with VexNDS, if the first operand
6374 an imm8, the source operand is the 2nd one. If the last
6375 operand is imm8, the source operand is the first one. */
9c2799c2 6376 gas_assert ((i.imm_operands == 2
7ab9ffdd
L		 6377 && i.types[0].bitfield.imm8
6378 && i.types[1].bitfield.imm8)
2426c15f 6379 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
7ab9ffdd
L		 6380 && i.imm_operands == 1
6381 && (i.types[0].bitfield.imm8
43234a1e
L		 6382 || i.types[i.operands - 1].bitfield.imm8
6383 || i.rounding)));
9f2670f2
L		 6384 if (i.imm_operands == 2)
6385 source = 2;
6386 else
c0f3af97
L		 6387 {
6388 if (i.types[0].bitfield.imm8)
6389 source = 1;
6390 else
6391 source = 0;
6392 }
c0f3af97
L		 6393 break;
6394 case 5:
43234a1e
L		 6395 if (i.tm.opcode_modifier.evex)
6396 {
6397 /* For EVEX instructions, when there are 5 operands, the
6398 first one must be immediate operand. If the second one
6399 is immediate operand, the source operand is the 3th
6400 one. If the last one is immediate operand, the source
6401 operand is the 2nd one. */
6402 gas_assert (i.imm_operands == 2
6403 && i.tm.opcode_modifier.sae
6404 && operand_type_check (i.types[0], imm));
6405 if (operand_type_check (i.types[1], imm))
6406 source = 2;
6407 else if (operand_type_check (i.types[4], imm))
6408 source = 1;
6409 else
6410 abort ();
6411 }
cab737b9
L		 6412 break;
6413 default:
6414 abort ();
6415 }
6416
c0f3af97
L		 6417 if (!vex_3_sources)
6418 {
6419 dest = source + 1;
6420
43234a1e
L		 6421 /* RC/SAE operand could be between DEST and SRC. That happens
6422 when one operand is GPR and the other one is XMM/YMM/ZMM
6423 register. */
6424 if (i.rounding && i.rounding->operand == (int) dest)
6425 dest++;
6426
2426c15f 6427 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
c0f3af97 6428 {
43234a1e 6429 /* For instructions with VexNDS, the register-only source
c5d0745b 6430 operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask
43234a1e
L		 6431 register. It is encoded in VEX prefix. We need to
6432 clear RegMem bit before calling operand_type_equal. */
f12dc422
L		 6433
6434 i386_operand_type op;
6435 unsigned int vvvv;
6436
6437 /* Check register-only source operand when two source
6438 operands are swapped. */
6439 if (!i.tm.operand_types[source].bitfield.baseindex
6440 && i.tm.operand_types[dest].bitfield.baseindex)
6441 {
6442 vvvv = source;
6443 source = dest;
6444 }
6445 else
6446 vvvv = dest;
6447
6448 op = i.tm.operand_types[vvvv];
fa99fab2 6449 op.bitfield.regmem = 0;
c0f3af97 6450 if ((dest + 1) >= i.operands
dc821c5f
JB		 6451 || ((!op.bitfield.reg
6452 || (!op.bitfield.dword && !op.bitfield.qword))
f12dc422 6453 && !operand_type_equal (&op, &regxmm)
43234a1e
L		 6454 && !operand_type_equal (&op, &regymm)
6455 && !operand_type_equal (&op, &regzmm)
6456 && !operand_type_equal (&op, &regmask)))
c0f3af97 6457 abort ();
f12dc422 6458 i.vex.register_specifier = i.op[vvvv].regs;
c0f3af97
L		 6459 dest++;
6460 }
6461 }
29b0f896
AM		 6462
6463 i.rm.mode = 3;
6464 /* One of the register operands will be encoded in the i.tm.reg
6465 field, the other in the combined i.tm.mode and i.tm.regmem
6466 fields. If no form of this instruction supports a memory
6467 destination operand, then we assume the source operand may
6468 sometimes be a memory operand and so we need to store the
6469 destination in the i.rm.reg field. */
40fb9820
L		 6470 if (!i.tm.operand_types[dest].bitfield.regmem
6471 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 6472 {
6473 i.rm.reg = i.op[dest].regs->reg_num;
6474 i.rm.regmem = i.op[source].regs->reg_num;
6475 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6476 i.rex |= REX_R;
43234a1e
L		 6477 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6478 i.vrex |= REX_R;
29b0f896 6479 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6480 i.rex |= REX_B;
43234a1e
L		 6481 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6482 i.vrex |= REX_B;
29b0f896
AM		 6483 }
6484 else
6485 {
6486 i.rm.reg = i.op[source].regs->reg_num;
6487 i.rm.regmem = i.op[dest].regs->reg_num;
6488 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 6489 i.rex |= REX_B;
43234a1e
L		 6490 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6491 i.vrex |= REX_B;
29b0f896 6492 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 6493 i.rex |= REX_R;
43234a1e
L		 6494 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6495 i.vrex |= REX_R;
29b0f896 6496 }
161a04f6 6497 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 6498 {
40fb9820
L		 6499 if (!i.types[0].bitfield.control
6500 && !i.types[1].bitfield.control)
c4a530c5 6501 abort ();
161a04f6 6502 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 6503 add_prefix (LOCK_PREFIX_OPCODE);
6504 }
29b0f896
AM		 6505 }
6506 else
6507 { /* If it's not 2 reg operands... */
c0f3af97
L		 6508 unsigned int mem;
6509
29b0f896
AM		 6510 if (i.mem_operands)
6511 {
6512 unsigned int fake_zero_displacement = 0;
99018f42 6513 unsigned int op;
4eed87de 6514
7ab9ffdd
L		 6515 for (op = 0; op < i.operands; op++)
6516 if (operand_type_check (i.types[op], anymem))
6517 break;
7ab9ffdd 6518 gas_assert (op < i.operands);
29b0f896 6519
6c30d220
L		 6520 if (i.tm.opcode_modifier.vecsib)
6521 {
6522 if (i.index_reg->reg_num == RegEiz
6523 || i.index_reg->reg_num == RegRiz)
6524 abort ();
6525
6526 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6527 if (!i.base_reg)
6528 {
6529 i.sib.base = NO_BASE_REGISTER;
6530 i.sib.scale = i.log2_scale_factor;
6531 i.types[op].bitfield.disp8 = 0;
6532 i.types[op].bitfield.disp16 = 0;
6533 i.types[op].bitfield.disp64 = 0;
43083a50 6534 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
6c30d220
L		 6535 {
6536 /* Must be 32 bit */
6537 i.types[op].bitfield.disp32 = 1;
6538 i.types[op].bitfield.disp32s = 0;
6539 }
6540 else
6541 {
6542 i.types[op].bitfield.disp32 = 0;
6543 i.types[op].bitfield.disp32s = 1;
6544 }
6545 }
6546 i.sib.index = i.index_reg->reg_num;
6547 if ((i.index_reg->reg_flags & RegRex) != 0)
6548 i.rex |= REX_X;
43234a1e
L		 6549 if ((i.index_reg->reg_flags & RegVRex) != 0)
6550 i.vrex |= REX_X;
6c30d220
L		 6551 }
6552
29b0f896
AM		 6553 default_seg = &ds;
6554
6555 if (i.base_reg == 0)
6556 {
6557 i.rm.mode = 0;
6558 if (!i.disp_operands)
9bb129e8 6559 fake_zero_displacement = 1;
29b0f896
AM		 6560 if (i.index_reg == 0)
6561 {
6c30d220 6562 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6563 /* Operand is just <disp> */
20f0a1fc 6564 if (flag_code == CODE_64BIT)
29b0f896
AM		 6565 {
6566 /* 64bit mode overwrites the 32bit absolute
6567 addressing by RIP relative addressing and
6568 absolute addressing is encoded by one of the
6569 redundant SIB forms. */
6570 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6571 i.sib.base = NO_BASE_REGISTER;
6572 i.sib.index = NO_INDEX_REGISTER;
fc225355 6573 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 6574 ? disp32s : disp32);
20f0a1fc 6575 }
fc225355
L		 6576 else if ((flag_code == CODE_16BIT)
6577 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 6578 {
6579 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 6580 i.types[op] = disp16;
20f0a1fc
NC		 6581 }
6582 else
6583 {
6584 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 6585 i.types[op] = disp32;
29b0f896
AM		 6586 }
6587 }
6c30d220 6588 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6589 {
6c30d220 6590 /* !i.base_reg && i.index_reg */
db51cc60
L		 6591 if (i.index_reg->reg_num == RegEiz
6592 || i.index_reg->reg_num == RegRiz)
6593 i.sib.index = NO_INDEX_REGISTER;
6594 else
6595 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6596 i.sib.base = NO_BASE_REGISTER;
6597 i.sib.scale = i.log2_scale_factor;
6598 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 6599 i.types[op].bitfield.disp8 = 0;
6600 i.types[op].bitfield.disp16 = 0;
6601 i.types[op].bitfield.disp64 = 0;
43083a50 6602 if (flag_code != CODE_64BIT || i.prefix[ADDR_PREFIX])
40fb9820
L		 6603 {
6604 /* Must be 32 bit */
6605 i.types[op].bitfield.disp32 = 1;
6606 i.types[op].bitfield.disp32s = 0;
6607 }
29b0f896 6608 else
40fb9820
L		 6609 {
6610 i.types[op].bitfield.disp32 = 0;
6611 i.types[op].bitfield.disp32s = 1;
6612 }
29b0f896 6613 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6614 i.rex |= REX_X;
29b0f896
AM		 6615 }
6616 }
6617 /* RIP addressing for 64bit mode. */
9a04903e
JB		 6618 else if (i.base_reg->reg_num == RegRip ||
6619 i.base_reg->reg_num == RegEip)
29b0f896 6620 {
6c30d220 6621 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896 6622 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 6623 i.types[op].bitfield.disp8 = 0;
6624 i.types[op].bitfield.disp16 = 0;
6625 i.types[op].bitfield.disp32 = 0;
6626 i.types[op].bitfield.disp32s = 1;
6627 i.types[op].bitfield.disp64 = 0;
71903a11 6628 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 6629 if (! i.disp_operands)
6630 fake_zero_displacement = 1;
29b0f896 6631 }
dc821c5f 6632 else if (i.base_reg->reg_type.bitfield.word)
29b0f896 6633 {
6c30d220 6634 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6635 switch (i.base_reg->reg_num)
6636 {
6637 case 3: /* (%bx) */
6638 if (i.index_reg == 0)
6639 i.rm.regmem = 7;
6640 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6641 i.rm.regmem = i.index_reg->reg_num - 6;
6642 break;
6643 case 5: /* (%bp) */
6644 default_seg = &ss;
6645 if (i.index_reg == 0)
6646 {
6647 i.rm.regmem = 6;
40fb9820 6648 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 6649 {
6650 /* fake (%bp) into 0(%bp) */
b5014f7a 6651 i.types[op].bitfield.disp8 = 1;
252b5132 6652 fake_zero_displacement = 1;
29b0f896
AM		 6653 }
6654 }
6655 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6656 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6657 break;
6658 default: /* (%si) -> 4 or (%di) -> 5 */
6659 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6660 }
6661 i.rm.mode = mode_from_disp_size (i.types[op]);
6662 }
6663 else /* i.base_reg and 32/64 bit mode */
6664 {
6665 if (flag_code == CODE_64BIT
40fb9820
L		 6666 && operand_type_check (i.types[op], disp))
6667 {
6668 i386_operand_type temp;
0dfbf9d7 6669 operand_type_set (&temp, 0);
40fb9820
L		 6670 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6671 i.types[op] = temp;
6672 if (i.prefix[ADDR_PREFIX] == 0)
6673 i.types[op].bitfield.disp32s = 1;
6674 else
6675 i.types[op].bitfield.disp32 = 1;
6676 }
20f0a1fc 6677
6c30d220
L		 6678 if (!i.tm.opcode_modifier.vecsib)
6679 i.rm.regmem = i.base_reg->reg_num;
29b0f896 6680 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 6681 i.rex |= REX_B;
29b0f896
AM		 6682 i.sib.base = i.base_reg->reg_num;
6683 /* x86-64 ignores REX prefix bit here to avoid decoder
6684 complications. */
848930b2
JB		 6685 if (!(i.base_reg->reg_flags & RegRex)
6686 && (i.base_reg->reg_num == EBP_REG_NUM
6687 || i.base_reg->reg_num == ESP_REG_NUM))
29b0f896 6688 default_seg = &ss;
848930b2 6689 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
29b0f896 6690 {
848930b2 6691 fake_zero_displacement = 1;
b5014f7a 6692 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 6693 }
6694 i.sib.scale = i.log2_scale_factor;
6695 if (i.index_reg == 0)
6696 {
6c30d220 6697 gas_assert (!i.tm.opcode_modifier.vecsib);
29b0f896
AM		 6698 /* <disp>(%esp) becomes two byte modrm with no index
6699 register. We've already stored the code for esp
6700 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6701 Any base register besides %esp will not use the
6702 extra modrm byte. */
6703 i.sib.index = NO_INDEX_REGISTER;
29b0f896 6704 }
6c30d220 6705 else if (!i.tm.opcode_modifier.vecsib)
29b0f896 6706 {
db51cc60
L		 6707 if (i.index_reg->reg_num == RegEiz
6708 || i.index_reg->reg_num == RegRiz)
6709 i.sib.index = NO_INDEX_REGISTER;
6710 else
6711 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 6712 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6713 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 6714 i.rex |= REX_X;
29b0f896 6715 }
67a4f2b7
AO		 6716
6717 if (i.disp_operands
6718 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6719 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6720 i.rm.mode = 0;
6721 else
a501d77e
L		 6722 {
6723 if (!fake_zero_displacement
6724 && !i.disp_operands
6725 && i.disp_encoding)
6726 {
6727 fake_zero_displacement = 1;
6728 if (i.disp_encoding == disp_encoding_8bit)
6729 i.types[op].bitfield.disp8 = 1;
6730 else
6731 i.types[op].bitfield.disp32 = 1;
6732 }
6733 i.rm.mode = mode_from_disp_size (i.types[op]);
6734 }
29b0f896 6735 }
252b5132 6736
29b0f896
AM		 6737 if (fake_zero_displacement)
6738 {
6739 /* Fakes a zero displacement assuming that i.types[op]
6740 holds the correct displacement size. */
6741 expressionS *exp;
6742
9c2799c2 6743 gas_assert (i.op[op].disps == 0);
29b0f896
AM		 6744 exp = &disp_expressions[i.disp_operands++];
6745 i.op[op].disps = exp;
6746 exp->X_op = O_constant;
6747 exp->X_add_number = 0;
6748 exp->X_add_symbol = (symbolS *) 0;
6749 exp->X_op_symbol = (symbolS *) 0;
6750 }
c0f3af97
L		 6751
6752 mem = op;
29b0f896 6753 }
c0f3af97
L		 6754 else
6755 mem = ~0;
252b5132 6756
8c43a48b 6757 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
5dd85c99
SP		 6758 {
6759 if (operand_type_check (i.types[0], imm))
6760 i.vex.register_specifier = NULL;
6761 else
6762 {
6763 /* VEX.vvvv encodes one of the sources when the first
6764 operand is not an immediate. */
1ef99a7b 6765 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6766 i.vex.register_specifier = i.op[0].regs;
6767 else
6768 i.vex.register_specifier = i.op[1].regs;
6769 }
6770
6771 /* Destination is a XMM register encoded in the ModRM.reg
6772 and VEX.R bit. */
6773 i.rm.reg = i.op[2].regs->reg_num;
6774 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6775 i.rex |= REX_R;
6776
6777 /* ModRM.rm and VEX.B encodes the other source. */
6778 if (!i.mem_operands)
6779 {
6780 i.rm.mode = 3;
6781
1ef99a7b 6782 if (i.tm.opcode_modifier.vexw == VEXW0)
5dd85c99
SP		 6783 i.rm.regmem = i.op[1].regs->reg_num;
6784 else
6785 i.rm.regmem = i.op[0].regs->reg_num;
6786
6787 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6788 i.rex |= REX_B;
6789 }
6790 }
2426c15f 6791 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
f88c9eb0
SP		 6792 {
6793 i.vex.register_specifier = i.op[2].regs;
6794 if (!i.mem_operands)
6795 {
6796 i.rm.mode = 3;
6797 i.rm.regmem = i.op[1].regs->reg_num;
6798 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6799 i.rex |= REX_B;
6800 }
6801 }
29b0f896
AM		 6802 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6803 (if any) based on i.tm.extension_opcode. Again, we must be
6804 careful to make sure that segment/control/debug/test/MMX
6805 registers are coded into the i.rm.reg field. */
f88c9eb0 6806 else if (i.reg_operands)
29b0f896 6807 {
99018f42 6808 unsigned int op;
7ab9ffdd
L		 6809 unsigned int vex_reg = ~0;
6810
6811 for (op = 0; op < i.operands; op++)
dc821c5f 6812 if (i.types[op].bitfield.reg
7ab9ffdd 6813 || i.types[op].bitfield.regmmx
1b54b8d7 6814 || i.types[op].bitfield.regsimd
7e8b059b 6815 || i.types[op].bitfield.regbnd
43234a1e 6816 || i.types[op].bitfield.regmask
7ab9ffdd
L		 6817 || i.types[op].bitfield.sreg2
6818 || i.types[op].bitfield.sreg3
6819 || i.types[op].bitfield.control
6820 || i.types[op].bitfield.debug
6821 || i.types[op].bitfield.test)
6822 break;
c0209578 6823
7ab9ffdd
L		 6824 if (vex_3_sources)
6825 op = dest;
2426c15f 6826 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
7ab9ffdd
L		 6827 {
6828 /* For instructions with VexNDS, the register-only
6829 source operand is encoded in VEX prefix. */
6830 gas_assert (mem != (unsigned int) ~0);
c0f3af97 6831
7ab9ffdd 6832 if (op > mem)
c0f3af97 6833 {
7ab9ffdd
L		 6834 vex_reg = op++;
6835 gas_assert (op < i.operands);
c0f3af97
L		 6836 }
6837 else
c0f3af97 6838 {
f12dc422
L		 6839 /* Check register-only source operand when two source
6840 operands are swapped. */
6841 if (!i.tm.operand_types[op].bitfield.baseindex
6842 && i.tm.operand_types[op + 1].bitfield.baseindex)
6843 {
6844 vex_reg = op;
6845 op += 2;
6846 gas_assert (mem == (vex_reg + 1)
6847 && op < i.operands);
6848 }
6849 else
6850 {
6851 vex_reg = op + 1;
6852 gas_assert (vex_reg < i.operands);
6853 }
c0f3af97 6854 }
7ab9ffdd 6855 }
2426c15f 6856 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
7ab9ffdd 6857 {
f12dc422 6858 /* For instructions with VexNDD, the register destination
7ab9ffdd 6859 is encoded in VEX prefix. */
f12dc422
L		 6860 if (i.mem_operands == 0)
6861 {
6862 /* There is no memory operand. */
6863 gas_assert ((op + 2) == i.operands);
6864 vex_reg = op + 1;
6865 }
6866 else
8d63c93e 6867 {
f12dc422
L		 6868 /* There are only 2 operands. */
6869 gas_assert (op < 2 && i.operands == 2);
6870 vex_reg = 1;
6871 }
7ab9ffdd
L		 6872 }
6873 else
6874 gas_assert (op < i.operands);
99018f42 6875
7ab9ffdd
L		 6876 if (vex_reg != (unsigned int) ~0)
6877 {
f12dc422 6878 i386_operand_type *type = &i.tm.operand_types[vex_reg];
7ab9ffdd 6879
dc821c5f
JB		 6880 if ((!type->bitfield.reg
6881 || (!type->bitfield.dword && !type->bitfield.qword))
f12dc422 6882 && !operand_type_equal (type, &regxmm)
43234a1e
L		 6883 && !operand_type_equal (type, &regymm)
6884 && !operand_type_equal (type, &regzmm)
6885 && !operand_type_equal (type, &regmask))
7ab9ffdd 6886 abort ();
f88c9eb0 6887
7ab9ffdd
L		 6888 i.vex.register_specifier = i.op[vex_reg].regs;
6889 }
6890
1b9f0c97
L		 6891 /* Don't set OP operand twice. */
6892 if (vex_reg != op)
7ab9ffdd 6893 {
1b9f0c97
L		 6894 /* If there is an extension opcode to put here, the
6895 register number must be put into the regmem field. */
6896 if (i.tm.extension_opcode != None)
6897 {
6898 i.rm.regmem = i.op[op].regs->reg_num;
6899 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6900 i.rex |= REX_B;
43234a1e
L		 6901 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6902 i.vrex |= REX_B;
1b9f0c97
L		 6903 }
6904 else
6905 {
6906 i.rm.reg = i.op[op].regs->reg_num;
6907 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6908 i.rex |= REX_R;
43234a1e
L		 6909 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6910 i.vrex |= REX_R;
1b9f0c97 6911 }
7ab9ffdd 6912 }
252b5132 6913
29b0f896
AM		 6914 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6915 must set it to 3 to indicate this is a register operand
6916 in the regmem field. */
6917 if (!i.mem_operands)
6918 i.rm.mode = 3;
6919 }
252b5132 6920
29b0f896 6921 /* Fill in i.rm.reg field with extension opcode (if any). */
c1e679ec 6922 if (i.tm.extension_opcode != None)
29b0f896
AM		 6923 i.rm.reg = i.tm.extension_opcode;
6924 }
6925 return default_seg;
6926}
252b5132 6927
29b0f896 6928static void
e3bb37b5 6929output_branch (void)
29b0f896
AM		 6930{
6931 char *p;
f8a5c266 6932 int size;
29b0f896
AM		 6933 int code16;
6934 int prefix;
6935 relax_substateT subtype;
6936 symbolS *sym;
6937 offsetT off;
6938
f8a5c266 6939 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
a501d77e 6940 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
29b0f896
AM		 6941
6942 prefix = 0;
6943 if (i.prefix[DATA_PREFIX] != 0)
252b5132 6944 {
29b0f896
AM		 6945 prefix = 1;
6946 i.prefixes -= 1;
6947 code16 ^= CODE16;
252b5132 6948 }
29b0f896
AM		 6949 /* Pentium4 branch hints. */
6950 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6951 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 6952 {
29b0f896
AM		 6953 prefix++;
6954 i.prefixes--;
6955 }
6956 if (i.prefix[REX_PREFIX] != 0)
6957 {
6958 prefix++;
6959 i.prefixes--;
2f66722d
AM		 6960 }
6961
7e8b059b
L		 6962 /* BND prefixed jump. */
6963 if (i.prefix[BND_PREFIX] != 0)
6964 {
6965 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6966 i.prefixes -= 1;
6967 }
6968
29b0f896
AM		 6969 if (i.prefixes != 0 && !intel_syntax)
6970 as_warn (_("skipping prefixes on this instruction"));
6971
6972 /* It's always a symbol; End frag & setup for relax.
6973 Make sure there is enough room in this frag for the largest
6974 instruction we may generate in md_convert_frag. This is 2
6975 bytes for the opcode and room for the prefix and largest
6976 displacement. */
6977 frag_grow (prefix + 2 + 4);
6978 /* Prefix and 1 opcode byte go in fr_fix. */
6979 p = frag_more (prefix + 1);
6980 if (i.prefix[DATA_PREFIX] != 0)
6981 *p++ = DATA_PREFIX_OPCODE;
6982 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6983 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6984 *p++ = i.prefix[SEG_PREFIX];
6985 if (i.prefix[REX_PREFIX] != 0)
6986 *p++ = i.prefix[REX_PREFIX];
6987 *p = i.tm.base_opcode;
6988
6989 if ((unsigned char) *p == JUMP_PC_RELATIVE)
f8a5c266 6990 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
40fb9820 6991 else if (cpu_arch_flags.bitfield.cpui386)
f8a5c266 6992 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
29b0f896 6993 else
f8a5c266 6994 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
29b0f896 6995 subtype |= code16;
3e73aa7c 6996
29b0f896
AM		 6997 sym = i.op[0].disps->X_add_symbol;
6998 off = i.op[0].disps->X_add_number;
3e73aa7c 6999
29b0f896
AM		 7000 if (i.op[0].disps->X_op != O_constant
7001 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 7002 {
29b0f896
AM		 7003 /* Handle complex expressions. */
7004 sym = make_expr_symbol (i.op[0].disps);
7005 off = 0;
7006 }
3e73aa7c 7007
29b0f896
AM		 7008 /* 1 possible extra opcode + 4 byte displacement go in var part.
7009 Pass reloc in fr_var. */
d258b828 7010 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
29b0f896 7011}
3e73aa7c 7012
29b0f896 7013static void
e3bb37b5 7014output_jump (void)
29b0f896
AM		 7015{
7016 char *p;
7017 int size;
3e02c1cc 7018 fixS *fixP;
29b0f896 7019
40fb9820 7020 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 7021 {
7022 /* This is a loop or jecxz type instruction. */
7023 size = 1;
7024 if (i.prefix[ADDR_PREFIX] != 0)
7025 {
7026 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
7027 i.prefixes -= 1;
7028 }
7029 /* Pentium4 branch hints. */
7030 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
7031 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
7032 {
7033 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
7034 i.prefixes--;
3e73aa7c
JH		 7035 }
7036 }
29b0f896
AM		 7037 else
7038 {
7039 int code16;
3e73aa7c 7040
29b0f896
AM		 7041 code16 = 0;
7042 if (flag_code == CODE_16BIT)
7043 code16 = CODE16;
3e73aa7c 7044
29b0f896
AM		 7045 if (i.prefix[DATA_PREFIX] != 0)
7046 {
7047 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
7048 i.prefixes -= 1;
7049 code16 ^= CODE16;
7050 }
252b5132 7051
29b0f896
AM		 7052 size = 4;
7053 if (code16)
7054 size = 2;
7055 }
9fcc94b6 7056
29b0f896
AM		 7057 if (i.prefix[REX_PREFIX] != 0)
7058 {
7059 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
7060 i.prefixes -= 1;
7061 }
252b5132 7062
7e8b059b
L		 7063 /* BND prefixed jump. */
7064 if (i.prefix[BND_PREFIX] != 0)
7065 {
7066 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
7067 i.prefixes -= 1;
7068 }
7069
29b0f896
AM		 7070 if (i.prefixes != 0 && !intel_syntax)
7071 as_warn (_("skipping prefixes on this instruction"));
e0890092 7072
42164a71
L		 7073 p = frag_more (i.tm.opcode_length + size);
7074 switch (i.tm.opcode_length)
7075 {
7076 case 2:
7077 *p++ = i.tm.base_opcode >> 8;
1a0670f3 7078 /* Fall through. */
42164a71
L		 7079 case 1:
7080 *p++ = i.tm.base_opcode;
7081 break;
7082 default:
7083 abort ();
7084 }
e0890092 7085
3e02c1cc 7086 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7087 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3e02c1cc
AM		 7088
7089 /* All jumps handled here are signed, but don't use a signed limit
7090 check for 32 and 16 bit jumps as we want to allow wrap around at
7091 4G and 64k respectively. */
7092 if (size == 1)
7093 fixP->fx_signed = 1;
29b0f896 7094}
e0890092 7095
29b0f896 7096static void
e3bb37b5 7097output_interseg_jump (void)
29b0f896
AM		 7098{
7099 char *p;
7100 int size;
7101 int prefix;
7102 int code16;
252b5132 7103
29b0f896
AM		 7104 code16 = 0;
7105 if (flag_code == CODE_16BIT)
7106 code16 = CODE16;
a217f122 7107
29b0f896
AM		 7108 prefix = 0;
7109 if (i.prefix[DATA_PREFIX] != 0)
7110 {
7111 prefix = 1;
7112 i.prefixes -= 1;
7113 code16 ^= CODE16;
7114 }
7115 if (i.prefix[REX_PREFIX] != 0)
7116 {
7117 prefix++;
7118 i.prefixes -= 1;
7119 }
252b5132 7120
29b0f896
AM		 7121 size = 4;
7122 if (code16)
7123 size = 2;
252b5132 7124
29b0f896
AM		 7125 if (i.prefixes != 0 && !intel_syntax)
7126 as_warn (_("skipping prefixes on this instruction"));
252b5132 7127
29b0f896
AM		 7128 /* 1 opcode; 2 segment; offset */
7129 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 7130
29b0f896
AM		 7131 if (i.prefix[DATA_PREFIX] != 0)
7132 *p++ = DATA_PREFIX_OPCODE;
252b5132 7133
29b0f896
AM		 7134 if (i.prefix[REX_PREFIX] != 0)
7135 *p++ = i.prefix[REX_PREFIX];
252b5132 7136
29b0f896
AM		 7137 *p++ = i.tm.base_opcode;
7138 if (i.op[1].imms->X_op == O_constant)
7139 {
7140 offsetT n = i.op[1].imms->X_add_number;
252b5132 7141
29b0f896
AM		 7142 if (size == 2
7143 && !fits_in_unsigned_word (n)
7144 && !fits_in_signed_word (n))
7145 {
7146 as_bad (_("16-bit jump out of range"));
7147 return;
7148 }
7149 md_number_to_chars (p, n, size);
7150 }
7151 else
7152 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
d258b828 7153 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
29b0f896
AM		 7154 if (i.op[0].imms->X_op != O_constant)
7155 as_bad (_("can't handle non absolute segment in `%s'"),
7156 i.tm.name);
7157 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
7158}
a217f122 7159
29b0f896 7160static void
e3bb37b5 7161output_insn (void)
29b0f896 7162{
2bbd9c25
JJ		 7163 fragS *insn_start_frag;
7164 offsetT insn_start_off;
7165
29b0f896
AM		 7166 /* Tie dwarf2 debug info to the address at the start of the insn.
7167 We can't do this after the insn has been output as the current
7168 frag may have been closed off. eg. by frag_var. */
7169 dwarf2_emit_insn (0);
7170
2bbd9c25
JJ		 7171 insn_start_frag = frag_now;
7172 insn_start_off = frag_now_fix ();
7173
29b0f896 7174 /* Output jumps. */
40fb9820 7175 if (i.tm.opcode_modifier.jump)
29b0f896 7176 output_branch ();
40fb9820
L		 7177 else if (i.tm.opcode_modifier.jumpbyte
7178 || i.tm.opcode_modifier.jumpdword)
29b0f896 7179 output_jump ();
40fb9820 7180 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 7181 output_interseg_jump ();
7182 else
7183 {
7184 /* Output normal instructions here. */
7185 char *p;
7186 unsigned char *q;
47465058 7187 unsigned int j;
331d2d0d 7188 unsigned int prefix;
4dffcebc 7189
e4e00185
AS		 7190 if (avoid_fence
7191 && i.tm.base_opcode == 0xfae
7192 && i.operands == 1
7193 && i.imm_operands == 1
7194 && (i.op[0].imms->X_add_number == 0xe8
7195 || i.op[0].imms->X_add_number == 0xf0
7196 || i.op[0].imms->X_add_number == 0xf8))
7197 {
7198 /* Encode lfence, mfence, and sfence as
7199 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
7200 offsetT val = 0x240483f0ULL;
7201 p = frag_more (5);
7202 md_number_to_chars (p, val, 5);
7203 return;
7204 }
7205
d022bddd
IT		 7206 /* Some processors fail on LOCK prefix. This options makes
7207 assembler ignore LOCK prefix and serves as a workaround. */
7208 if (omit_lock_prefix)
7209 {
7210 if (i.tm.base_opcode == LOCK_PREFIX_OPCODE)
7211 return;
7212 i.prefix[LOCK_PREFIX] = 0;
7213 }
7214
43234a1e
L		 7215 /* Since the VEX/EVEX prefix contains the implicit prefix, we
7216 don't need the explicit prefix. */
7217 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
bc4bd9ab 7218 {
c0f3af97 7219 switch (i.tm.opcode_length)
bc4bd9ab 7220 {
c0f3af97
L		 7221 case 3:
7222 if (i.tm.base_opcode & 0xff000000)
4dffcebc 7223 {
c0f3af97
L		 7224 prefix = (i.tm.base_opcode >> 24) & 0xff;
7225 goto check_prefix;
7226 }
7227 break;
7228 case 2:
7229 if ((i.tm.base_opcode & 0xff0000) != 0)
7230 {
7231 prefix = (i.tm.base_opcode >> 16) & 0xff;
7232 if (i.tm.cpu_flags.bitfield.cpupadlock)
7233 {
4dffcebc 7234check_prefix:
c0f3af97 7235 if (prefix != REPE_PREFIX_OPCODE
c32fa91d 7236 || (i.prefix[REP_PREFIX]
c0f3af97
L		 7237 != REPE_PREFIX_OPCODE))
7238 add_prefix (prefix);
7239 }
7240 else
4dffcebc
L		 7241 add_prefix (prefix);
7242 }
c0f3af97
L		 7243 break;
7244 case 1:
7245 break;
390c91cf
L		 7246 case 0:
7247 /* Check for pseudo prefixes. */
7248 as_bad_where (insn_start_frag->fr_file,
7249 insn_start_frag->fr_line,
7250 _("pseudo prefix without instruction"));
7251 return;
c0f3af97
L		 7252 default:
7253 abort ();
bc4bd9ab 7254 }
c0f3af97 7255
6d19a37a 7256#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
cf61b747
L		 7257 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
7258 R_X86_64_GOTTPOFF relocation so that linker can safely
7259 perform IE->LE optimization. */
7260 if (x86_elf_abi == X86_64_X32_ABI
7261 && i.operands == 2
7262 && i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF
7263 && i.prefix[REX_PREFIX] == 0)
7264 add_prefix (REX_OPCODE);
6d19a37a 7265#endif
cf61b747 7266
c0f3af97
L		 7267 /* The prefix bytes. */
7268 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
7269 if (*q)
7270 FRAG_APPEND_1_CHAR (*q);
0f10071e 7271 }
ae5c1c7b 7272 else
c0f3af97
L		 7273 {
7274 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
7275 if (*q)
7276 switch (j)
7277 {
7278 case REX_PREFIX:
7279 /* REX byte is encoded in VEX prefix. */
7280 break;
7281 case SEG_PREFIX:
7282 case ADDR_PREFIX:
7283 FRAG_APPEND_1_CHAR (*q);
7284 break;
7285 default:
7286 /* There should be no other prefixes for instructions
7287 with VEX prefix. */
7288 abort ();
7289 }
7290
43234a1e
L		 7291 /* For EVEX instructions i.vrex should become 0 after
7292 build_evex_prefix. For VEX instructions upper 16 registers
7293 aren't available, so VREX should be 0. */
7294 if (i.vrex)
7295 abort ();
c0f3af97
L		 7296 /* Now the VEX prefix. */
7297 p = frag_more (i.vex.length);
7298 for (j = 0; j < i.vex.length; j++)
7299 p[j] = i.vex.bytes[j];
7300 }
252b5132 7301
29b0f896 7302 /* Now the opcode; be careful about word order here! */
4dffcebc 7303 if (i.tm.opcode_length == 1)
29b0f896
AM		 7304 {
7305 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
7306 }
7307 else
7308 {
4dffcebc 7309 switch (i.tm.opcode_length)
331d2d0d 7310 {
43234a1e
L		 7311 case 4:
7312 p = frag_more (4);
7313 *p++ = (i.tm.base_opcode >> 24) & 0xff;
7314 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7315 break;
4dffcebc 7316 case 3:
331d2d0d
L		 7317 p = frag_more (3);
7318 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 7319 break;
7320 case 2:
7321 p = frag_more (2);
7322 break;
7323 default:
7324 abort ();
7325 break;
331d2d0d 7326 }
0f10071e 7327
29b0f896
AM		 7328 /* Put out high byte first: can't use md_number_to_chars! */
7329 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7330 *p = i.tm.base_opcode & 0xff;
7331 }
3e73aa7c 7332
29b0f896 7333 /* Now the modrm byte and sib byte (if present). */
40fb9820 7334 if (i.tm.opcode_modifier.modrm)
29b0f896 7335 {
4a3523fa
L		 7336 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7337 | i.rm.reg << 3
7338 | i.rm.mode << 6));
29b0f896
AM		 7339 /* If i.rm.regmem == ESP (4)
7340 && i.rm.mode != (Register mode)
7341 && not 16 bit
7342 ==> need second modrm byte. */
7343 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7344 && i.rm.mode != 3
dc821c5f 7345 && !(i.base_reg && i.base_reg->reg_type.bitfield.word))
4a3523fa
L		 7346 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7347 | i.sib.index << 3
7348 | i.sib.scale << 6));
29b0f896 7349 }
3e73aa7c 7350
29b0f896 7351 if (i.disp_operands)
2bbd9c25 7352 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 7353
29b0f896 7354 if (i.imm_operands)
2bbd9c25 7355 output_imm (insn_start_frag, insn_start_off);
29b0f896 7356 }
252b5132 7357
29b0f896
AM		 7358#ifdef DEBUG386
7359 if (flag_debug)
7360 {
7b81dfbb 7361 pi ("" /*line*/, &i);
29b0f896
AM		 7362 }
7363#endif /* DEBUG386 */
7364}
252b5132 7365
e205caa7
L		 7366/* Return the size of the displacement operand N. */
7367
7368static int
7369disp_size (unsigned int n)
7370{
7371 int size = 4;
43234a1e 7372
b5014f7a 7373 if (i.types[n].bitfield.disp64)
40fb9820
L		 7374 size = 8;
7375 else if (i.types[n].bitfield.disp8)
7376 size = 1;
7377 else if (i.types[n].bitfield.disp16)
7378 size = 2;
e205caa7
L		 7379 return size;
7380}
7381
7382/* Return the size of the immediate operand N. */
7383
7384static int
7385imm_size (unsigned int n)
7386{
7387 int size = 4;
40fb9820
L		 7388 if (i.types[n].bitfield.imm64)
7389 size = 8;
7390 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7391 size = 1;
7392 else if (i.types[n].bitfield.imm16)
7393 size = 2;
e205caa7
L		 7394 return size;
7395}
7396
29b0f896 7397static void
64e74474 7398output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7399{
7400 char *p;
7401 unsigned int n;
252b5132 7402
29b0f896
AM		 7403 for (n = 0; n < i.operands; n++)
7404 {
b5014f7a 7405 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 7406 {
7407 if (i.op[n].disps->X_op == O_constant)
7408 {
e205caa7 7409 int size = disp_size (n);
43234a1e 7410 offsetT val = i.op[n].disps->X_add_number;
252b5132 7411
b5014f7a 7412 val = offset_in_range (val >> i.memshift, size);
29b0f896
AM		 7413 p = frag_more (size);
7414 md_number_to_chars (p, val, size);
7415 }
7416 else
7417 {
f86103b7 7418 enum bfd_reloc_code_real reloc_type;
e205caa7 7419 int size = disp_size (n);
40fb9820 7420 int sign = i.types[n].bitfield.disp32s;
29b0f896 7421 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
02a86693 7422 fixS *fixP;
29b0f896 7423
e205caa7 7424 /* We can't have 8 bit displacement here. */
9c2799c2 7425 gas_assert (!i.types[n].bitfield.disp8);
e205caa7 7426
29b0f896
AM		 7427 /* The PC relative address is computed relative
7428 to the instruction boundary, so in case immediate
7429 fields follows, we need to adjust the value. */
7430 if (pcrel && i.imm_operands)
7431 {
29b0f896 7432 unsigned int n1;
e205caa7 7433 int sz = 0;
252b5132 7434
29b0f896 7435 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 7436 if (operand_type_check (i.types[n1], imm))
252b5132 7437 {
e205caa7
L		 7438 /* Only one immediate is allowed for PC
7439 relative address. */
9c2799c2 7440 gas_assert (sz == 0);
e205caa7
L		 7441 sz = imm_size (n1);
7442 i.op[n].disps->X_add_number -= sz;
252b5132 7443 }
29b0f896 7444 /* We should find the immediate. */
9c2799c2 7445 gas_assert (sz != 0);
29b0f896 7446 }
520dc8e8 7447
29b0f896 7448 p = frag_more (size);
d258b828 7449 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 7450 if (GOT_symbol
2bbd9c25 7451 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 7452 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7453 || reloc_type == BFD_RELOC_X86_64_32S
7454 || (reloc_type == BFD_RELOC_64
7455 && object_64bit))
d6ab8113
JB		 7456 && (i.op[n].disps->X_op == O_symbol
7457 || (i.op[n].disps->X_op == O_add
7458 && ((symbol_get_value_expression
7459 (i.op[n].disps->X_op_symbol)->X_op)
7460 == O_subtract))))
7461 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 7462 {
7463 offsetT add;
7464
7465 if (insn_start_frag == frag_now)
7466 add = (p - frag_now->fr_literal) - insn_start_off;
7467 else
7468 {
7469 fragS *fr;
7470
7471 add = insn_start_frag->fr_fix - insn_start_off;
7472 for (fr = insn_start_frag->fr_next;
7473 fr && fr != frag_now; fr = fr->fr_next)
7474 add += fr->fr_fix;
7475 add += p - frag_now->fr_literal;
7476 }
7477
4fa24527 7478 if (!object_64bit)
7b81dfbb
AJ		 7479 {
7480 reloc_type = BFD_RELOC_386_GOTPC;
7481 i.op[n].imms->X_add_number += add;
7482 }
7483 else if (reloc_type == BFD_RELOC_64)
7484 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 7485 else
7b81dfbb
AJ		 7486 /* Don't do the adjustment for x86-64, as there
7487 the pcrel addressing is relative to the _next_
7488 insn, and that is taken care of in other code. */
d6ab8113 7489 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 7490 }
02a86693
L		 7491 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal,
7492 size, i.op[n].disps, pcrel,
7493 reloc_type);
7494 /* Check for "call/jmp *mem", "mov mem, %reg",
7495 "test %reg, mem" and "binop mem, %reg" where binop
7496 is one of adc, add, and, cmp, or, sbb, sub, xor
0cb4071e
L		 7497 instructions. Always generate R_386_GOT32X for
7498 "sym*GOT" operand in 32-bit mode. */
7499 if ((generate_relax_relocations
7500 || (!object_64bit
7501 && i.rm.mode == 0
7502 && i.rm.regmem == 5))
7503 && (i.rm.mode == 2
7504 || (i.rm.mode == 0 && i.rm.regmem == 5))
02a86693
L		 7505 && ((i.operands == 1
7506 && i.tm.base_opcode == 0xff
7507 && (i.rm.reg == 2 || i.rm.reg == 4))
7508 || (i.operands == 2
7509 && (i.tm.base_opcode == 0x8b
7510 || i.tm.base_opcode == 0x85
7511 || (i.tm.base_opcode & 0xc7) == 0x03))))
7512 {
7513 if (object_64bit)
7514 {
7515 fixP->fx_tcbit = i.rex != 0;
7516 if (i.base_reg
7517 && (i.base_reg->reg_num == RegRip
7518 || i.base_reg->reg_num == RegEip))
7519 fixP->fx_tcbit2 = 1;
7520 }
7521 else
7522 fixP->fx_tcbit2 = 1;
7523 }
29b0f896
AM		 7524 }
7525 }
7526 }
7527}
252b5132 7528
29b0f896 7529static void
64e74474 7530output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 7531{
7532 char *p;
7533 unsigned int n;
252b5132 7534
29b0f896
AM		 7535 for (n = 0; n < i.operands; n++)
7536 {
43234a1e
L		 7537 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7538 if (i.rounding && (int) n == i.rounding->operand)
7539 continue;
7540
40fb9820 7541 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 7542 {
7543 if (i.op[n].imms->X_op == O_constant)
7544 {
e205caa7 7545 int size = imm_size (n);
29b0f896 7546 offsetT val;
b4cac588 7547
29b0f896
AM		 7548 val = offset_in_range (i.op[n].imms->X_add_number,
7549 size);
7550 p = frag_more (size);
7551 md_number_to_chars (p, val, size);
7552 }
7553 else
7554 {
7555 /* Not absolute_section.
7556 Need a 32-bit fixup (don't support 8bit
7557 non-absolute imms). Try to support other
7558 sizes ... */
f86103b7 7559 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 7560 int size = imm_size (n);
7561 int sign;
29b0f896 7562
40fb9820 7563 if (i.types[n].bitfield.imm32s
a7d61044 7564 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 7565 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 7566 sign = 1;
e205caa7
L		 7567 else
7568 sign = 0;
520dc8e8 7569
29b0f896 7570 p = frag_more (size);
d258b828 7571 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 7572
2bbd9c25
JJ		 7573 /* This is tough to explain. We end up with this one if we
7574 * have operands that look like
7575 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7576 * obtain the absolute address of the GOT, and it is strongly
7577 * preferable from a performance point of view to avoid using
7578 * a runtime relocation for this. The actual sequence of
7579 * instructions often look something like:
7580 *
7581 * call .L66
7582 * .L66:
7583 * popl %ebx
7584 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7585 *
7586 * The call and pop essentially return the absolute address
7587 * of the label .L66 and store it in %ebx. The linker itself
7588 * will ultimately change the first operand of the addl so
7589 * that %ebx points to the GOT, but to keep things simple, the
7590 * .o file must have this operand set so that it generates not
7591 * the absolute address of .L66, but the absolute address of
7592 * itself. This allows the linker itself simply treat a GOTPC
7593 * relocation as asking for a pcrel offset to the GOT to be
7594 * added in, and the addend of the relocation is stored in the
7595 * operand field for the instruction itself.
7596 *
7597 * Our job here is to fix the operand so that it would add
7598 * the correct offset so that %ebx would point to itself. The
7599 * thing that is tricky is that .-.L66 will point to the
7600 * beginning of the instruction, so we need to further modify
7601 * the operand so that it will point to itself. There are
7602 * other cases where you have something like:
7603 *
7604 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7605 *
7606 * and here no correction would be required. Internally in
7607 * the assembler we treat operands of this form as not being
7608 * pcrel since the '.' is explicitly mentioned, and I wonder
7609 * whether it would simplify matters to do it this way. Who
7610 * knows. In earlier versions of the PIC patches, the
7611 * pcrel_adjust field was used to store the correction, but
7612 * since the expression is not pcrel, I felt it would be
7613 * confusing to do it this way. */
7614
d6ab8113 7615 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 7616 || reloc_type == BFD_RELOC_X86_64_32S
7617 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 7618 && GOT_symbol
7619 && GOT_symbol == i.op[n].imms->X_add_symbol
7620 && (i.op[n].imms->X_op == O_symbol
7621 || (i.op[n].imms->X_op == O_add
7622 && ((symbol_get_value_expression
7623 (i.op[n].imms->X_op_symbol)->X_op)
7624 == O_subtract))))
7625 {
2bbd9c25
JJ		 7626 offsetT add;
7627
7628 if (insn_start_frag == frag_now)
7629 add = (p - frag_now->fr_literal) - insn_start_off;
7630 else
7631 {
7632 fragS *fr;
7633
7634 add = insn_start_frag->fr_fix - insn_start_off;
7635 for (fr = insn_start_frag->fr_next;
7636 fr && fr != frag_now; fr = fr->fr_next)
7637 add += fr->fr_fix;
7638 add += p - frag_now->fr_literal;
7639 }
7640
4fa24527 7641 if (!object_64bit)
d6ab8113 7642 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 7643 else if (size == 4)
d6ab8113 7644 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 7645 else if (size == 8)
7646 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 7647 i.op[n].imms->X_add_number += add;
29b0f896 7648 }
29b0f896
AM		 7649 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7650 i.op[n].imms, 0, reloc_type);
7651 }
7652 }
7653 }
252b5132
RH		 7654}
7655\f
d182319b
JB		 7656/* x86_cons_fix_new is called via the expression parsing code when a
7657 reloc is needed. We use this hook to get the correct .got reloc. */
d182319b
JB		 7658static int cons_sign = -1;
7659
7660void
e3bb37b5 7661x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
62ebcb5c 7662 expressionS *exp, bfd_reloc_code_real_type r)
d182319b 7663{
d258b828 7664 r = reloc (len, 0, cons_sign, r);
d182319b
JB		 7665
7666#ifdef TE_PE
7667 if (exp->X_op == O_secrel)
7668 {
7669 exp->X_op = O_symbol;
7670 r = BFD_RELOC_32_SECREL;
7671 }
7672#endif
7673
7674 fix_new_exp (frag, off, len, exp, 0, r);
7675}
7676
357d1bd8
L		 7677/* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7678 purpose of the `.dc.a' internal pseudo-op. */
7679
7680int
7681x86_address_bytes (void)
7682{
7683 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7684 return 4;
7685 return stdoutput->arch_info->bits_per_address / 8;
7686}
7687
d382c579
TG		 7688#if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7689 || defined (LEX_AT)
d258b828 7690# define lex_got(reloc, adjust, types) NULL
718ddfc0 7691#else
f3c180ae
AM		 7692/* Parse operands of the form
7693 <symbol>@GOTOFF+<nnn>
7694 and similar .plt or .got references.
7695
7696 If we find one, set up the correct relocation in RELOC and copy the
7697 input string, minus the `@GOTOFF' into a malloc'd buffer for
7698 parsing by the calling routine. Return this buffer, and if ADJUST
7699 is non-null set it to the length of the string we removed from the
7700 input line. Otherwise return NULL. */
7701static char *
91d6fa6a 7702lex_got (enum bfd_reloc_code_real *rel,
64e74474 7703 int *adjust,
d258b828 7704 i386_operand_type *types)
f3c180ae 7705{
7b81dfbb
AJ		 7706 /* Some of the relocations depend on the size of what field is to
7707 be relocated. But in our callers i386_immediate and i386_displacement
7708 we don't yet know the operand size (this will be set by insn
7709 matching). Hence we record the word32 relocation here,
7710 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 7711 static const struct {
7712 const char *str;
cff8d58a 7713 int len;
4fa24527 7714 const enum bfd_reloc_code_real rel[2];
40fb9820 7715 const i386_operand_type types64;
f3c180ae 7716 } gotrel[] = {
8ce3d284 7717#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 7718 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7719 BFD_RELOC_SIZE32 },
7720 OPERAND_TYPE_IMM32_64 },
8ce3d284 7721#endif
cff8d58a
L		 7722 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7723 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 7724 OPERAND_TYPE_IMM64 },
cff8d58a
L		 7725 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7726 BFD_RELOC_X86_64_PLT32 },
40fb9820 7727 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7728 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7729 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 7730 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7731 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7732 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 7733 OPERAND_TYPE_IMM64_DISP64 },
cff8d58a
L		 7734 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7735 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 7736 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7737 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7738 BFD_RELOC_X86_64_TLSGD },
40fb9820 7739 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7740 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7741 _dummy_first_bfd_reloc_code_real },
40fb9820 7742 OPERAND_TYPE_NONE },
cff8d58a
L		 7743 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7744 BFD_RELOC_X86_64_TLSLD },
40fb9820 7745 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7746 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7747 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 7748 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7749 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7750 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 7751 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7752 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7753 _dummy_first_bfd_reloc_code_real },
40fb9820 7754 OPERAND_TYPE_NONE },
cff8d58a
L		 7755 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7756 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820 7757 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
cff8d58a
L		 7758 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7759 _dummy_first_bfd_reloc_code_real },
40fb9820 7760 OPERAND_TYPE_NONE },
cff8d58a
L		 7761 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7762 _dummy_first_bfd_reloc_code_real },
40fb9820 7763 OPERAND_TYPE_NONE },
cff8d58a
L		 7764 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7765 BFD_RELOC_X86_64_GOT32 },
40fb9820 7766 OPERAND_TYPE_IMM32_32S_64_DISP32 },
cff8d58a
L		 7767 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7768 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 7769 OPERAND_TYPE_IMM32_32S_DISP32 },
cff8d58a
L		 7770 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7771 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 7772 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 7773 };
7774 char *cp;
7775 unsigned int j;
7776
d382c579 7777#if defined (OBJ_MAYBE_ELF)
718ddfc0
JB		 7778 if (!IS_ELF)
7779 return NULL;
d382c579 7780#endif
718ddfc0 7781
f3c180ae 7782 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 7783 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 7784 return NULL;
7785
47465058 7786 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae 7787 {
cff8d58a 7788 int len = gotrel[j].len;
28f81592 7789 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 7790 {
4fa24527 7791 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 7792 {
28f81592
AM		 7793 int first, second;
7794 char *tmpbuf, *past_reloc;
f3c180ae 7795
91d6fa6a 7796 *rel = gotrel[j].rel[object_64bit];
f3c180ae 7797
3956db08
JB		 7798 if (types)
7799 {
7800 if (flag_code != CODE_64BIT)
40fb9820
L		 7801 {
7802 types->bitfield.imm32 = 1;
7803 types->bitfield.disp32 = 1;
7804 }
3956db08
JB		 7805 else
7806 *types = gotrel[j].types64;
7807 }
7808
8fd4256d 7809 if (j != 0 && GOT_symbol == NULL)
f3c180ae
AM		 7810 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7811
28f81592 7812 /* The length of the first part of our input line. */
f3c180ae 7813 first = cp - input_line_pointer;
28f81592
AM		 7814
7815 /* The second part goes from after the reloc token until
67c11a9b 7816 (and including) an end_of_line char or comma. */
28f81592 7817 past_reloc = cp + 1 + len;
67c11a9b
AM		 7818 cp = past_reloc;
7819 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7820 ++cp;
7821 second = cp + 1 - past_reloc;
28f81592
AM		 7822
7823 /* Allocate and copy string. The trailing NUL shouldn't
7824 be necessary, but be safe. */
add39d23 7825 tmpbuf = XNEWVEC (char, first + second + 2);
f3c180ae 7826 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 7827 if (second != 0 && *past_reloc != ' ')
7828 /* Replace the relocation token with ' ', so that
7829 errors like foo@GOTOFF1 will be detected. */
7830 tmpbuf[first++] = ' ';
af89796a
L		 7831 else
7832 /* Increment length by 1 if the relocation token is
7833 removed. */
7834 len++;
7835 if (adjust)
7836 *adjust = len;
0787a12d
AM		 7837 memcpy (tmpbuf + first, past_reloc, second);
7838 tmpbuf[first + second] = '\0';
f3c180ae
AM		 7839 return tmpbuf;
7840 }
7841
4fa24527
JB		 7842 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7843 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 7844 return NULL;
7845 }
7846 }
7847
7848 /* Might be a symbol version string. Don't as_bad here. */
7849 return NULL;
7850}
4e4f7c87 7851#endif
f3c180ae 7852
a988325c
NC		 7853#ifdef TE_PE
7854#ifdef lex_got
7855#undef lex_got
7856#endif
7857/* Parse operands of the form
7858 <symbol>@SECREL32+<nnn>
7859
7860 If we find one, set up the correct relocation in RELOC and copy the
7861 input string, minus the `@SECREL32' into a malloc'd buffer for
7862 parsing by the calling routine. Return this buffer, and if ADJUST
7863 is non-null set it to the length of the string we removed from the
34bca508
L		 7864 input line. Otherwise return NULL.
7865
a988325c
NC		 7866 This function is copied from the ELF version above adjusted for PE targets. */
7867
7868static char *
7869lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7870 int *adjust ATTRIBUTE_UNUSED,
d258b828 7871 i386_operand_type *types)
a988325c
NC		 7872{
7873 static const struct
7874 {
7875 const char *str;
7876 int len;
7877 const enum bfd_reloc_code_real rel[2];
7878 const i386_operand_type types64;
7879 }
7880 gotrel[] =
7881 {
7882 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7883 BFD_RELOC_32_SECREL },
7884 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7885 };
7886
7887 char *cp;
7888 unsigned j;
7889
7890 for (cp = input_line_pointer; *cp != '@'; cp++)
7891 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7892 return NULL;
7893
7894 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7895 {
7896 int len = gotrel[j].len;
7897
7898 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7899 {
7900 if (gotrel[j].rel[object_64bit] != 0)
7901 {
7902 int first, second;
7903 char *tmpbuf, *past_reloc;
7904
7905 *rel = gotrel[j].rel[object_64bit];
7906 if (adjust)
7907 *adjust = len;
7908
7909 if (types)
7910 {
7911 if (flag_code != CODE_64BIT)
7912 {
7913 types->bitfield.imm32 = 1;
7914 types->bitfield.disp32 = 1;
7915 }
7916 else
7917 *types = gotrel[j].types64;
7918 }
7919
7920 /* The length of the first part of our input line. */
7921 first = cp - input_line_pointer;
7922
7923 /* The second part goes from after the reloc token until
7924 (and including) an end_of_line char or comma. */
7925 past_reloc = cp + 1 + len;
7926 cp = past_reloc;
7927 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7928 ++cp;
7929 second = cp + 1 - past_reloc;
7930
7931 /* Allocate and copy string. The trailing NUL shouldn't
7932 be necessary, but be safe. */
add39d23 7933 tmpbuf = XNEWVEC (char, first + second + 2);
a988325c
NC		 7934 memcpy (tmpbuf, input_line_pointer, first);
7935 if (second != 0 && *past_reloc != ' ')
7936 /* Replace the relocation token with ' ', so that
7937 errors like foo@SECLREL321 will be detected. */
7938 tmpbuf[first++] = ' ';
7939 memcpy (tmpbuf + first, past_reloc, second);
7940 tmpbuf[first + second] = '\0';
7941 return tmpbuf;
7942 }
7943
7944 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7945 gotrel[j].str, 1 << (5 + object_64bit));
7946 return NULL;
7947 }
7948 }
7949
7950 /* Might be a symbol version string. Don't as_bad here. */
7951 return NULL;
7952}
7953
7954#endif /* TE_PE */
7955
62ebcb5c 7956bfd_reloc_code_real_type
e3bb37b5 7957x86_cons (expressionS *exp, int size)
f3c180ae 7958{
62ebcb5c
AM		 7959 bfd_reloc_code_real_type got_reloc = NO_RELOC;
7960
ee86248c
JB		 7961 intel_syntax = -intel_syntax;
7962
3c7b9c2c 7963 exp->X_md = 0;
4fa24527 7964 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 7965 {
7966 /* Handle @GOTOFF and the like in an expression. */
7967 char *save;
7968 char *gotfree_input_line;
4a57f2cf 7969 int adjust = 0;
f3c180ae
AM		 7970
7971 save = input_line_pointer;
d258b828 7972 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 7973 if (gotfree_input_line)
7974 input_line_pointer = gotfree_input_line;
7975
7976 expression (exp);
7977
7978 if (gotfree_input_line)
7979 {
7980 /* expression () has merrily parsed up to the end of line,
7981 or a comma - in the wrong buffer. Transfer how far
7982 input_line_pointer has moved to the right buffer. */
7983 input_line_pointer = (save
7984 + (input_line_pointer - gotfree_input_line)
7985 + adjust);
7986 free (gotfree_input_line);
3992d3b7
AM		 7987 if (exp->X_op == O_constant
7988 || exp->X_op == O_absent
7989 || exp->X_op == O_illegal
0398aac5 7990 || exp->X_op == O_register
3992d3b7
AM		 7991 || exp->X_op == O_big)
7992 {
7993 char c = *input_line_pointer;
7994 *input_line_pointer = 0;
7995 as_bad (_("missing or invalid expression `%s'"), save);
7996 *input_line_pointer = c;
7997 }
f3c180ae
AM		 7998 }
7999 }
8000 else
8001 expression (exp);
ee86248c
JB		 8002
8003 intel_syntax = -intel_syntax;
8004
8005 if (intel_syntax)
8006 i386_intel_simplify (exp);
62ebcb5c
AM		 8007
8008 return got_reloc;
f3c180ae 8009}
f3c180ae 8010
9f32dd5b
L		 8011static void
8012signed_cons (int size)
6482c264 8013{
d182319b
JB		 8014 if (flag_code == CODE_64BIT)
8015 cons_sign = 1;
8016 cons (size);
8017 cons_sign = -1;
6482c264
NC		 8018}
8019
d182319b 8020#ifdef TE_PE
6482c264 8021static void
7016a5d5 8022pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
6482c264
NC		 8023{
8024 expressionS exp;
8025
8026 do
8027 {
8028 expression (&exp);
8029 if (exp.X_op == O_symbol)
8030 exp.X_op = O_secrel;
8031
8032 emit_expr (&exp, 4);
8033 }
8034 while (*input_line_pointer++ == ',');
8035
8036 input_line_pointer--;
8037 demand_empty_rest_of_line ();
8038}
6482c264
NC		 8039#endif
8040
43234a1e
L		 8041/* Handle Vector operations. */
8042
8043static char *
8044check_VecOperations (char *op_string, char *op_end)
8045{
8046 const reg_entry *mask;
8047 const char *saved;
8048 char *end_op;
8049
8050 while (*op_string
8051 && (op_end == NULL || op_string < op_end))
8052 {
8053 saved = op_string;
8054 if (*op_string == '{')
8055 {
8056 op_string++;
8057
8058 /* Check broadcasts. */
8059 if (strncmp (op_string, "1to", 3) == 0)
8060 {
8061 int bcst_type;
8062
8063 if (i.broadcast)
8064 goto duplicated_vec_op;
8065
8066 op_string += 3;
8067 if (*op_string == '8')
8068 bcst_type = BROADCAST_1TO8;
b28d1bda
IT		 8069 else if (*op_string == '4')
8070 bcst_type = BROADCAST_1TO4;
8071 else if (*op_string == '2')
8072 bcst_type = BROADCAST_1TO2;
43234a1e
L		 8073 else if (*op_string == '1'
8074 && *(op_string+1) == '6')
8075 {
8076 bcst_type = BROADCAST_1TO16;
8077 op_string++;
8078 }
8079 else
8080 {
8081 as_bad (_("Unsupported broadcast: `%s'"), saved);
8082 return NULL;
8083 }
8084 op_string++;
8085
8086 broadcast_op.type = bcst_type;
8087 broadcast_op.operand = this_operand;
8088 i.broadcast = &broadcast_op;
8089 }
8090 /* Check masking operation. */
8091 else if ((mask = parse_register (op_string, &end_op)) != NULL)
8092 {
8093 /* k0 can't be used for write mask. */
6d2cd6b2 8094 if (!mask->reg_type.bitfield.regmask || mask->reg_num == 0)
43234a1e 8095 {
6d2cd6b2
JB		 8096 as_bad (_("`%s%s' can't be used for write mask"),
8097 register_prefix, mask->reg_name);
43234a1e
L		 8098 return NULL;
8099 }
8100
8101 if (!i.mask)
8102 {
8103 mask_op.mask = mask;
8104 mask_op.zeroing = 0;
8105 mask_op.operand = this_operand;
8106 i.mask = &mask_op;
8107 }
8108 else
8109 {
8110 if (i.mask->mask)
8111 goto duplicated_vec_op;
8112
8113 i.mask->mask = mask;
8114
8115 /* Only "{z}" is allowed here. No need to check
8116 zeroing mask explicitly. */
8117 if (i.mask->operand != this_operand)
8118 {
8119 as_bad (_("invalid write mask `%s'"), saved);
8120 return NULL;
8121 }
8122 }
8123
8124 op_string = end_op;
8125 }
8126 /* Check zeroing-flag for masking operation. */
8127 else if (*op_string == 'z')
8128 {
8129 if (!i.mask)
8130 {
8131 mask_op.mask = NULL;
8132 mask_op.zeroing = 1;
8133 mask_op.operand = this_operand;
8134 i.mask = &mask_op;
8135 }
8136 else
8137 {
8138 if (i.mask->zeroing)
8139 {
8140 duplicated_vec_op:
8141 as_bad (_("duplicated `%s'"), saved);
8142 return NULL;
8143 }
8144
8145 i.mask->zeroing = 1;
8146
8147 /* Only "{%k}" is allowed here. No need to check mask
8148 register explicitly. */
8149 if (i.mask->operand != this_operand)
8150 {
8151 as_bad (_("invalid zeroing-masking `%s'"),
8152 saved);
8153 return NULL;
8154 }
8155 }
8156
8157 op_string++;
8158 }
8159 else
8160 goto unknown_vec_op;
8161
8162 if (*op_string != '}')
8163 {
8164 as_bad (_("missing `}' in `%s'"), saved);
8165 return NULL;
8166 }
8167 op_string++;
8168 continue;
8169 }
8170 unknown_vec_op:
8171 /* We don't know this one. */
8172 as_bad (_("unknown vector operation: `%s'"), saved);
8173 return NULL;
8174 }
8175
6d2cd6b2
JB		 8176 if (i.mask && i.mask->zeroing && !i.mask->mask)
8177 {
8178 as_bad (_("zeroing-masking only allowed with write mask"));
8179 return NULL;
8180 }
8181
43234a1e
L		 8182 return op_string;
8183}
8184
252b5132 8185static int
70e41ade 8186i386_immediate (char *imm_start)
252b5132
RH		 8187{
8188 char *save_input_line_pointer;
f3c180ae 8189 char *gotfree_input_line;
252b5132 8190 segT exp_seg = 0;
47926f60 8191 expressionS *exp;
40fb9820
L		 8192 i386_operand_type types;
8193
0dfbf9d7 8194 operand_type_set (&types, ~0);
252b5132
RH		 8195
8196 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
8197 {
31b2323c
L		 8198 as_bad (_("at most %d immediate operands are allowed"),
8199 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 8200 return 0;
8201 }
8202
8203 exp = &im_expressions[i.imm_operands++];
520dc8e8 8204 i.op[this_operand].imms = exp;
252b5132
RH		 8205
8206 if (is_space_char (*imm_start))
8207 ++imm_start;
8208
8209 save_input_line_pointer = input_line_pointer;
8210 input_line_pointer = imm_start;
8211
d258b828 8212 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8213 if (gotfree_input_line)
8214 input_line_pointer = gotfree_input_line;
252b5132
RH		 8215
8216 exp_seg = expression (exp);
8217
83183c0c 8218 SKIP_WHITESPACE ();
43234a1e
L		 8219
8220 /* Handle vector operations. */
8221 if (*input_line_pointer == '{')
8222 {
8223 input_line_pointer = check_VecOperations (input_line_pointer,
8224 NULL);
8225 if (input_line_pointer == NULL)
8226 return 0;
8227 }
8228
252b5132 8229 if (*input_line_pointer)
f3c180ae 8230 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 8231
8232 input_line_pointer = save_input_line_pointer;
f3c180ae 8233 if (gotfree_input_line)
ee86248c
JB		 8234 {
8235 free (gotfree_input_line);
8236
8237 if (exp->X_op == O_constant || exp->X_op == O_register)
8238 exp->X_op = O_illegal;
8239 }
8240
8241 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
8242}
252b5132 8243
ee86248c
JB		 8244static int
8245i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8246 i386_operand_type types, const char *imm_start)
8247{
8248 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
252b5132 8249 {
313c53d1
L		 8250 if (imm_start)
8251 as_bad (_("missing or invalid immediate expression `%s'"),
8252 imm_start);
3992d3b7 8253 return 0;
252b5132 8254 }
3e73aa7c 8255 else if (exp->X_op == O_constant)
252b5132 8256 {
47926f60 8257 /* Size it properly later. */
40fb9820 8258 i.types[this_operand].bitfield.imm64 = 1;
13f864ae
L		 8259 /* If not 64bit, sign extend val. */
8260 if (flag_code != CODE_64BIT
4eed87de
AM		 8261 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
8262 exp->X_add_number
8263 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 8264 }
4c63da97 8265#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 8266 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 8267 && exp_seg != absolute_section
47926f60 8268 && exp_seg != text_section
24eab124
AM		 8269 && exp_seg != data_section
8270 && exp_seg != bss_section
8271 && exp_seg != undefined_section
f86103b7 8272 && !bfd_is_com_section (exp_seg))
252b5132 8273 {
d0b47220 8274 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 8275 return 0;
8276 }
8277#endif
a841bdf5 8278 else if (!intel_syntax && exp_seg == reg_section)
bb8f5920 8279 {
313c53d1
L		 8280 if (imm_start)
8281 as_bad (_("illegal immediate register operand %s"), imm_start);
bb8f5920
L		 8282 return 0;
8283 }
252b5132
RH		 8284 else
8285 {
8286 /* This is an address. The size of the address will be
24eab124 8287 determined later, depending on destination register,
3e73aa7c 8288 suffix, or the default for the section. */
40fb9820
L		 8289 i.types[this_operand].bitfield.imm8 = 1;
8290 i.types[this_operand].bitfield.imm16 = 1;
8291 i.types[this_operand].bitfield.imm32 = 1;
8292 i.types[this_operand].bitfield.imm32s = 1;
8293 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 8294 i.types[this_operand] = operand_type_and (i.types[this_operand],
8295 types);
252b5132
RH		 8296 }
8297
8298 return 1;
8299}
8300
551c1ca1 8301static char *
e3bb37b5 8302i386_scale (char *scale)
252b5132 8303{
551c1ca1
AM		 8304 offsetT val;
8305 char *save = input_line_pointer;
252b5132 8306
551c1ca1
AM		 8307 input_line_pointer = scale;
8308 val = get_absolute_expression ();
8309
8310 switch (val)
252b5132 8311 {
551c1ca1 8312 case 1:
252b5132
RH		 8313 i.log2_scale_factor = 0;
8314 break;
551c1ca1 8315 case 2:
252b5132
RH		 8316 i.log2_scale_factor = 1;
8317 break;
551c1ca1 8318 case 4:
252b5132
RH		 8319 i.log2_scale_factor = 2;
8320 break;
551c1ca1 8321 case 8:
252b5132
RH		 8322 i.log2_scale_factor = 3;
8323 break;
8324 default:
a724f0f4
JB		 8325 {
8326 char sep = *input_line_pointer;
8327
8328 *input_line_pointer = '\0';
8329 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
8330 scale);
8331 *input_line_pointer = sep;
8332 input_line_pointer = save;
8333 return NULL;
8334 }
252b5132 8335 }
29b0f896 8336 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 8337 {
8338 as_warn (_("scale factor of %d without an index register"),
24eab124 8339 1 << i.log2_scale_factor);
252b5132 8340 i.log2_scale_factor = 0;
252b5132 8341 }
551c1ca1
AM		 8342 scale = input_line_pointer;
8343 input_line_pointer = save;
8344 return scale;
252b5132
RH		 8345}
8346
252b5132 8347static int
e3bb37b5 8348i386_displacement (char *disp_start, char *disp_end)
252b5132 8349{
29b0f896 8350 expressionS *exp;
252b5132
RH		 8351 segT exp_seg = 0;
8352 char *save_input_line_pointer;
f3c180ae 8353 char *gotfree_input_line;
40fb9820
L		 8354 int override;
8355 i386_operand_type bigdisp, types = anydisp;
3992d3b7 8356 int ret;
252b5132 8357
31b2323c
L		 8358 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8359 {
8360 as_bad (_("at most %d displacement operands are allowed"),
8361 MAX_MEMORY_OPERANDS);
8362 return 0;
8363 }
8364
0dfbf9d7 8365 operand_type_set (&bigdisp, 0);
40fb9820
L		 8366 if ((i.types[this_operand].bitfield.jumpabsolute)
8367 || (!current_templates->start->opcode_modifier.jump
8368 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 8369 {
40fb9820 8370 bigdisp.bitfield.disp32 = 1;
e05278af 8371 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 8372 if (flag_code == CODE_64BIT)
8373 {
8374 if (!override)
8375 {
8376 bigdisp.bitfield.disp32s = 1;
8377 bigdisp.bitfield.disp64 = 1;
8378 }
8379 }
8380 else if ((flag_code == CODE_16BIT) ^ override)
8381 {
8382 bigdisp.bitfield.disp32 = 0;
8383 bigdisp.bitfield.disp16 = 1;
8384 }
e05278af
JB		 8385 }
8386 else
8387 {
8388 /* For PC-relative branches, the width of the displacement
8389 is dependent upon data size, not address size. */
e05278af 8390 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 8391 if (flag_code == CODE_64BIT)
8392 {
8393 if (override || i.suffix == WORD_MNEM_SUFFIX)
8394 bigdisp.bitfield.disp16 = 1;
8395 else
8396 {
8397 bigdisp.bitfield.disp32 = 1;
8398 bigdisp.bitfield.disp32s = 1;
8399 }
8400 }
8401 else
e05278af
JB		 8402 {
8403 if (!override)
8404 override = (i.suffix == (flag_code != CODE_16BIT
8405 ? WORD_MNEM_SUFFIX
8406 : LONG_MNEM_SUFFIX));
40fb9820
L		 8407 bigdisp.bitfield.disp32 = 1;
8408 if ((flag_code == CODE_16BIT) ^ override)
8409 {
8410 bigdisp.bitfield.disp32 = 0;
8411 bigdisp.bitfield.disp16 = 1;
8412 }
e05278af 8413 }
e05278af 8414 }
c6fb90c8
L		 8415 i.types[this_operand] = operand_type_or (i.types[this_operand],
8416 bigdisp);
252b5132
RH		 8417
8418 exp = &disp_expressions[i.disp_operands];
520dc8e8 8419 i.op[this_operand].disps = exp;
252b5132
RH		 8420 i.disp_operands++;
8421 save_input_line_pointer = input_line_pointer;
8422 input_line_pointer = disp_start;
8423 END_STRING_AND_SAVE (disp_end);
8424
8425#ifndef GCC_ASM_O_HACK
8426#define GCC_ASM_O_HACK 0
8427#endif
8428#if GCC_ASM_O_HACK
8429 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 8430 if (i.types[this_operand].bitfield.baseIndex
24eab124 8431 && displacement_string_end[-1] == '+')
252b5132
RH		 8432 {
8433 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 8434 constraint within gcc asm statements.
8435 For instance:
8436
8437 #define _set_tssldt_desc(n,addr,limit,type) \
8438 __asm__ __volatile__ ( \
8439 "movw %w2,%0\n\t" \
8440 "movw %w1,2+%0\n\t" \
8441 "rorl $16,%1\n\t" \
8442 "movb %b1,4+%0\n\t" \
8443 "movb %4,5+%0\n\t" \
8444 "movb $0,6+%0\n\t" \
8445 "movb %h1,7+%0\n\t" \
8446 "rorl $16,%1" \
8447 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8448
8449 This works great except that the output assembler ends
8450 up looking a bit weird if it turns out that there is
8451 no offset. You end up producing code that looks like:
8452
8453 #APP
8454 movw $235,(%eax)
8455 movw %dx,2+(%eax)
8456 rorl $16,%edx
8457 movb %dl,4+(%eax)
8458 movb $137,5+(%eax)
8459 movb $0,6+(%eax)
8460 movb %dh,7+(%eax)
8461 rorl $16,%edx
8462 #NO_APP
8463
47926f60 8464 So here we provide the missing zero. */
24eab124
AM		 8465
8466 *displacement_string_end = '0';
252b5132
RH		 8467 }
8468#endif
d258b828 8469 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 8470 if (gotfree_input_line)
8471 input_line_pointer = gotfree_input_line;
252b5132 8472
24eab124 8473 exp_seg = expression (exp);
252b5132 8474
636c26b0
AM		 8475 SKIP_WHITESPACE ();
8476 if (*input_line_pointer)
8477 as_bad (_("junk `%s' after expression"), input_line_pointer);
8478#if GCC_ASM_O_HACK
8479 RESTORE_END_STRING (disp_end + 1);
8480#endif
636c26b0 8481 input_line_pointer = save_input_line_pointer;
636c26b0 8482 if (gotfree_input_line)
ee86248c
JB		 8483 {
8484 free (gotfree_input_line);
8485
8486 if (exp->X_op == O_constant || exp->X_op == O_register)
8487 exp->X_op = O_illegal;
8488 }
8489
8490 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8491
8492 RESTORE_END_STRING (disp_end);
8493
8494 return ret;
8495}
8496
8497static int
8498i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8499 i386_operand_type types, const char *disp_start)
8500{
8501 i386_operand_type bigdisp;
8502 int ret = 1;
636c26b0 8503
24eab124
AM		 8504 /* We do this to make sure that the section symbol is in
8505 the symbol table. We will ultimately change the relocation
47926f60 8506 to be relative to the beginning of the section. */
1ae12ab7 8507 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 8508 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8509 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 8510 {
636c26b0 8511 if (exp->X_op != O_symbol)
3992d3b7 8512 goto inv_disp;
636c26b0 8513
e5cb08ac 8514 if (S_IS_LOCAL (exp->X_add_symbol)
c64efb4b
L		 8515 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8516 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
24eab124 8517 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 8518 exp->X_op = O_subtract;
8519 exp->X_op_symbol = GOT_symbol;
1ae12ab7 8520 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 8521 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 8522 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8523 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 8524 else
29b0f896 8525 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 8526 }
252b5132 8527
3992d3b7
AM		 8528 else if (exp->X_op == O_absent
8529 || exp->X_op == O_illegal
ee86248c 8530 || exp->X_op == O_big)
2daf4fd8 8531 {
3992d3b7
AM		 8532 inv_disp:
8533 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 8534 disp_start);
3992d3b7 8535 ret = 0;
2daf4fd8
AM		 8536 }
8537
0e1147d9
L		 8538 else if (flag_code == CODE_64BIT
8539 && !i.prefix[ADDR_PREFIX]
8540 && exp->X_op == O_constant)
8541 {
8542 /* Since displacement is signed extended to 64bit, don't allow
8543 disp32 and turn off disp32s if they are out of range. */
8544 i.types[this_operand].bitfield.disp32 = 0;
8545 if (!fits_in_signed_long (exp->X_add_number))
8546 {
8547 i.types[this_operand].bitfield.disp32s = 0;
8548 if (i.types[this_operand].bitfield.baseindex)
8549 {
8550 as_bad (_("0x%lx out range of signed 32bit displacement"),
8551 (long) exp->X_add_number);
8552 ret = 0;
8553 }
8554 }
8555 }
8556
4c63da97 8557#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 8558 else if (exp->X_op != O_constant
8559 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8560 && exp_seg != absolute_section
8561 && exp_seg != text_section
8562 && exp_seg != data_section
8563 && exp_seg != bss_section
8564 && exp_seg != undefined_section
8565 && !bfd_is_com_section (exp_seg))
24eab124 8566 {
d0b47220 8567 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 8568 ret = 0;
24eab124 8569 }
252b5132 8570#endif
3956db08 8571
40fb9820
L		 8572 /* Check if this is a displacement only operand. */
8573 bigdisp = i.types[this_operand];
8574 bigdisp.bitfield.disp8 = 0;
8575 bigdisp.bitfield.disp16 = 0;
8576 bigdisp.bitfield.disp32 = 0;
8577 bigdisp.bitfield.disp32s = 0;
8578 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 8579 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 8580 i.types[this_operand] = operand_type_and (i.types[this_operand],
8581 types);
3956db08 8582
3992d3b7 8583 return ret;
252b5132
RH		 8584}
8585
2abc2bec
JB		 8586/* Return the active addressing mode, taking address override and
8587 registers forming the address into consideration. Update the
8588 address override prefix if necessary. */
47926f60 8589
2abc2bec
JB		 8590static enum flag_code
8591i386_addressing_mode (void)
252b5132 8592{
be05d201
L		 8593 enum flag_code addr_mode;
8594
8595 if (i.prefix[ADDR_PREFIX])
8596 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8597 else
8598 {
8599 addr_mode = flag_code;
8600
24eab124 8601#if INFER_ADDR_PREFIX
be05d201
L		 8602 if (i.mem_operands == 0)
8603 {
8604 /* Infer address prefix from the first memory operand. */
8605 const reg_entry *addr_reg = i.base_reg;
8606
8607 if (addr_reg == NULL)
8608 addr_reg = i.index_reg;
eecb386c 8609
be05d201
L		 8610 if (addr_reg)
8611 {
8612 if (addr_reg->reg_num == RegEip
8613 || addr_reg->reg_num == RegEiz
dc821c5f 8614 || addr_reg->reg_type.bitfield.dword)
be05d201
L		 8615 addr_mode = CODE_32BIT;
8616 else if (flag_code != CODE_64BIT
dc821c5f 8617 && addr_reg->reg_type.bitfield.word)
be05d201
L		 8618 addr_mode = CODE_16BIT;
8619
8620 if (addr_mode != flag_code)
8621 {
8622 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8623 i.prefixes += 1;
8624 /* Change the size of any displacement too. At most one
8625 of Disp16 or Disp32 is set.
8626 FIXME. There doesn't seem to be any real need for
8627 separate Disp16 and Disp32 flags. The same goes for
8628 Imm16 and Imm32. Removing them would probably clean
8629 up the code quite a lot. */
8630 if (flag_code != CODE_64BIT
8631 && (i.types[this_operand].bitfield.disp16
8632 || i.types[this_operand].bitfield.disp32))
8633 i.types[this_operand]
8634 = operand_type_xor (i.types[this_operand], disp16_32);
8635 }
8636 }
8637 }
24eab124 8638#endif
be05d201
L		 8639 }
8640
2abc2bec
JB		 8641 return addr_mode;
8642}
8643
8644/* Make sure the memory operand we've been dealt is valid.
8645 Return 1 on success, 0 on a failure. */
8646
8647static int
8648i386_index_check (const char *operand_string)
8649{
8650 const char *kind = "base/index";
8651 enum flag_code addr_mode = i386_addressing_mode ();
8652
fc0763e6
JB		 8653 if (current_templates->start->opcode_modifier.isstring
8654 && !current_templates->start->opcode_modifier.immext
8655 && (current_templates->end[-1].opcode_modifier.isstring
8656 || i.mem_operands))
8657 {
8658 /* Memory operands of string insns are special in that they only allow
8659 a single register (rDI, rSI, or rBX) as their memory address. */
be05d201
L		 8660 const reg_entry *expected_reg;
8661 static const char *di_si[][2] =
8662 {
8663 { "esi", "edi" },
8664 { "si", "di" },
8665 { "rsi", "rdi" }
8666 };
8667 static const char *bx[] = { "ebx", "bx", "rbx" };
fc0763e6
JB		 8668
8669 kind = "string address";
8670
8325cc63 8671 if (current_templates->start->opcode_modifier.repprefixok)
fc0763e6
JB		 8672 {
8673 i386_operand_type type = current_templates->end[-1].operand_types[0];
8674
8675 if (!type.bitfield.baseindex
8676 || ((!i.mem_operands != !intel_syntax)
8677 && current_templates->end[-1].operand_types[1]
8678 .bitfield.baseindex))
8679 type = current_templates->end[-1].operand_types[1];
be05d201
L		 8680 expected_reg = hash_find (reg_hash,
8681 di_si[addr_mode][type.bitfield.esseg]);
8682
fc0763e6
JB		 8683 }
8684 else
be05d201 8685 expected_reg = hash_find (reg_hash, bx[addr_mode]);
fc0763e6 8686
be05d201
L		 8687 if (i.base_reg != expected_reg
8688 || i.index_reg
fc0763e6 8689 || operand_type_check (i.types[this_operand], disp))
fc0763e6 8690 {
be05d201
L		 8691 /* The second memory operand must have the same size as
8692 the first one. */
8693 if (i.mem_operands
8694 && i.base_reg
8695 && !((addr_mode == CODE_64BIT
dc821c5f 8696 && i.base_reg->reg_type.bitfield.qword)
be05d201 8697 || (addr_mode == CODE_32BIT
dc821c5f
JB		 8698 ? i.base_reg->reg_type.bitfield.dword
8699 : i.base_reg->reg_type.bitfield.word)))
be05d201
L		 8700 goto bad_address;
8701
fc0763e6
JB		 8702 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8703 operand_string,
8704 intel_syntax ? '[' : '(',
8705 register_prefix,
be05d201 8706 expected_reg->reg_name,
fc0763e6 8707 intel_syntax ? ']' : ')');
be05d201 8708 return 1;
fc0763e6 8709 }
be05d201
L		 8710 else
8711 return 1;
8712
8713bad_address:
8714 as_bad (_("`%s' is not a valid %s expression"),
8715 operand_string, kind);
8716 return 0;
3e73aa7c
JH		 8717 }
8718 else
8719 {
be05d201
L		 8720 if (addr_mode != CODE_16BIT)
8721 {
8722 /* 32-bit/64-bit checks. */
8723 if ((i.base_reg
8724 && (addr_mode == CODE_64BIT
dc821c5f
JB		 8725 ? !i.base_reg->reg_type.bitfield.qword
8726 : !i.base_reg->reg_type.bitfield.dword)
be05d201
L		 8727 && (i.index_reg
8728 || (i.base_reg->reg_num
8729 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8730 || (i.index_reg
1b54b8d7
JB		 8731 && !i.index_reg->reg_type.bitfield.xmmword
8732 && !i.index_reg->reg_type.bitfield.ymmword
8733 && !i.index_reg->reg_type.bitfield.zmmword
be05d201 8734 && ((addr_mode == CODE_64BIT
dc821c5f 8735 ? !(i.index_reg->reg_type.bitfield.qword
be05d201 8736 || i.index_reg->reg_num == RegRiz)
dc821c5f 8737 : !(i.index_reg->reg_type.bitfield.dword
be05d201
L		 8738 || i.index_reg->reg_num == RegEiz))
8739 || !i.index_reg->reg_type.bitfield.baseindex)))
8740 goto bad_address;
8178be5b
JB		 8741
8742 /* bndmk, bndldx, and bndstx have special restrictions. */
8743 if (current_templates->start->base_opcode == 0xf30f1b
8744 || (current_templates->start->base_opcode & ~1) == 0x0f1a)
8745 {
8746 /* They cannot use RIP-relative addressing. */
8747 if (i.base_reg && i.base_reg->reg_num == RegRip)
8748 {
8749 as_bad (_("`%s' cannot be used here"), operand_string);
8750 return 0;
8751 }
8752
8753 /* bndldx and bndstx ignore their scale factor. */
8754 if (current_templates->start->base_opcode != 0xf30f1b
8755 && i.log2_scale_factor)
8756 as_warn (_("register scaling is being ignored here"));
8757 }
be05d201
L		 8758 }
8759 else
3e73aa7c 8760 {
be05d201 8761 /* 16-bit checks. */
3e73aa7c 8762 if ((i.base_reg
dc821c5f 8763 && (!i.base_reg->reg_type.bitfield.word
40fb9820 8764 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 8765 || (i.index_reg
dc821c5f 8766 && (!i.index_reg->reg_type.bitfield.word
40fb9820 8767 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 8768 || !(i.base_reg
8769 && i.base_reg->reg_num < 6
8770 && i.index_reg->reg_num >= 6
8771 && i.log2_scale_factor == 0))))
be05d201 8772 goto bad_address;
3e73aa7c
JH		 8773 }
8774 }
be05d201 8775 return 1;
24eab124 8776}
252b5132 8777
43234a1e
L		 8778/* Handle vector immediates. */
8779
8780static int
8781RC_SAE_immediate (const char *imm_start)
8782{
8783 unsigned int match_found, j;
8784 const char *pstr = imm_start;
8785 expressionS *exp;
8786
8787 if (*pstr != '{')
8788 return 0;
8789
8790 pstr++;
8791 match_found = 0;
8792 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8793 {
8794 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8795 {
8796 if (!i.rounding)
8797 {
8798 rc_op.type = RC_NamesTable[j].type;
8799 rc_op.operand = this_operand;
8800 i.rounding = &rc_op;
8801 }
8802 else
8803 {
8804 as_bad (_("duplicated `%s'"), imm_start);
8805 return 0;
8806 }
8807 pstr += RC_NamesTable[j].len;
8808 match_found = 1;
8809 break;
8810 }
8811 }
8812 if (!match_found)
8813 return 0;
8814
8815 if (*pstr++ != '}')
8816 {
8817 as_bad (_("Missing '}': '%s'"), imm_start);
8818 return 0;
8819 }
8820 /* RC/SAE immediate string should contain nothing more. */;
8821 if (*pstr != 0)
8822 {
8823 as_bad (_("Junk after '}': '%s'"), imm_start);
8824 return 0;
8825 }
8826
8827 exp = &im_expressions[i.imm_operands++];
8828 i.op[this_operand].imms = exp;
8829
8830 exp->X_op = O_constant;
8831 exp->X_add_number = 0;
8832 exp->X_add_symbol = (symbolS *) 0;
8833 exp->X_op_symbol = (symbolS *) 0;
8834
8835 i.types[this_operand].bitfield.imm8 = 1;
8836 return 1;
8837}
8838
8325cc63
JB		 8839/* Only string instructions can have a second memory operand, so
8840 reduce current_templates to just those if it contains any. */
8841static int
8842maybe_adjust_templates (void)
8843{
8844 const insn_template *t;
8845
8846 gas_assert (i.mem_operands == 1);
8847
8848 for (t = current_templates->start; t < current_templates->end; ++t)
8849 if (t->opcode_modifier.isstring)
8850 break;
8851
8852 if (t < current_templates->end)
8853 {
8854 static templates aux_templates;
8855 bfd_boolean recheck;
8856
8857 aux_templates.start = t;
8858 for (; t < current_templates->end; ++t)
8859 if (!t->opcode_modifier.isstring)
8860 break;
8861 aux_templates.end = t;
8862
8863 /* Determine whether to re-check the first memory operand. */
8864 recheck = (aux_templates.start != current_templates->start
8865 || t != current_templates->end);
8866
8867 current_templates = &aux_templates;
8868
8869 if (recheck)
8870 {
8871 i.mem_operands = 0;
8872 if (i.memop1_string != NULL
8873 && i386_index_check (i.memop1_string) == 0)
8874 return 0;
8875 i.mem_operands = 1;
8876 }
8877 }
8878
8879 return 1;
8880}
8881
fc0763e6 8882/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 8883 on error. */
252b5132 8884
252b5132 8885static int
a7619375 8886i386_att_operand (char *operand_string)
252b5132 8887{
af6bdddf
AM		 8888 const reg_entry *r;
8889 char *end_op;
24eab124 8890 char *op_string = operand_string;
252b5132 8891
24eab124 8892 if (is_space_char (*op_string))
252b5132
RH		 8893 ++op_string;
8894
24eab124 8895 /* We check for an absolute prefix (differentiating,
47926f60 8896 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 8897 if (*op_string == ABSOLUTE_PREFIX)
8898 {
8899 ++op_string;
8900 if (is_space_char (*op_string))
8901 ++op_string;
40fb9820 8902 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 8903 }
252b5132 8904
47926f60 8905 /* Check if operand is a register. */
4d1bb795 8906 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 8907 {
40fb9820
L		 8908 i386_operand_type temp;
8909
24eab124
AM		 8910 /* Check for a segment override by searching for ':' after a
8911 segment register. */
8912 op_string = end_op;
8913 if (is_space_char (*op_string))
8914 ++op_string;
40fb9820
L		 8915 if (*op_string == ':'
8916 && (r->reg_type.bitfield.sreg2
8917 || r->reg_type.bitfield.sreg3))
24eab124
AM		 8918 {
8919 switch (r->reg_num)
8920 {
8921 case 0:
8922 i.seg[i.mem_operands] = &es;
8923 break;
8924 case 1:
8925 i.seg[i.mem_operands] = &cs;
8926 break;
8927 case 2:
8928 i.seg[i.mem_operands] = &ss;
8929 break;
8930 case 3:
8931 i.seg[i.mem_operands] = &ds;
8932 break;
8933 case 4:
8934 i.seg[i.mem_operands] = &fs;
8935 break;
8936 case 5:
8937 i.seg[i.mem_operands] = &gs;
8938 break;
8939 }
252b5132 8940
24eab124 8941 /* Skip the ':' and whitespace. */
252b5132
RH		 8942 ++op_string;
8943 if (is_space_char (*op_string))
24eab124 8944 ++op_string;
252b5132 8945
24eab124
AM		 8946 if (!is_digit_char (*op_string)
8947 && !is_identifier_char (*op_string)
8948 && *op_string != '('
8949 && *op_string != ABSOLUTE_PREFIX)
8950 {
8951 as_bad (_("bad memory operand `%s'"), op_string);
8952 return 0;
8953 }
47926f60 8954 /* Handle case of %es:*foo. */
24eab124
AM		 8955 if (*op_string == ABSOLUTE_PREFIX)
8956 {
8957 ++op_string;
8958 if (is_space_char (*op_string))
8959 ++op_string;
40fb9820 8960 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 8961 }
8962 goto do_memory_reference;
8963 }
43234a1e
L		 8964
8965 /* Handle vector operations. */
8966 if (*op_string == '{')
8967 {
8968 op_string = check_VecOperations (op_string, NULL);
8969 if (op_string == NULL)
8970 return 0;
8971 }
8972
24eab124
AM		 8973 if (*op_string)
8974 {
d0b47220 8975 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 8976 return 0;
8977 }
40fb9820
L		 8978 temp = r->reg_type;
8979 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8980 i.types[this_operand] = operand_type_or (i.types[this_operand],
8981 temp);
7d5e4556 8982 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 8983 i.op[this_operand].regs = r;
24eab124
AM		 8984 i.reg_operands++;
8985 }
af6bdddf
AM		 8986 else if (*op_string == REGISTER_PREFIX)
8987 {
8988 as_bad (_("bad register name `%s'"), op_string);
8989 return 0;
8990 }
24eab124 8991 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 8992 {
24eab124 8993 ++op_string;
40fb9820 8994 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 8995 {
d0b47220 8996 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 8997 return 0;
8998 }
8999 if (!i386_immediate (op_string))
9000 return 0;
9001 }
43234a1e
L		 9002 else if (RC_SAE_immediate (operand_string))
9003 {
9004 /* If it is a RC or SAE immediate, do nothing. */
9005 ;
9006 }
24eab124
AM		 9007 else if (is_digit_char (*op_string)
9008 || is_identifier_char (*op_string)
d02603dc 9009 || *op_string == '"'
e5cb08ac 9010 || *op_string == '(')
24eab124 9011 {
47926f60 9012 /* This is a memory reference of some sort. */
af6bdddf 9013 char *base_string;
252b5132 9014
47926f60 9015 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 9016 char *displacement_string_start;
9017 char *displacement_string_end;
43234a1e 9018 char *vop_start;
252b5132 9019
24eab124 9020 do_memory_reference:
8325cc63
JB		 9021 if (i.mem_operands == 1 && !maybe_adjust_templates ())
9022 return 0;
24eab124 9023 if ((i.mem_operands == 1
40fb9820 9024 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 9025 || i.mem_operands == 2)
9026 {
9027 as_bad (_("too many memory references for `%s'"),
9028 current_templates->start->name);
9029 return 0;
9030 }
252b5132 9031
24eab124
AM		 9032 /* Check for base index form. We detect the base index form by
9033 looking for an ')' at the end of the operand, searching
9034 for the '(' matching it, and finding a REGISTER_PREFIX or ','
9035 after the '('. */
af6bdddf 9036 base_string = op_string + strlen (op_string);
c3332e24 9037
43234a1e
L		 9038 /* Handle vector operations. */
9039 vop_start = strchr (op_string, '{');
9040 if (vop_start && vop_start < base_string)
9041 {
9042 if (check_VecOperations (vop_start, base_string) == NULL)
9043 return 0;
9044 base_string = vop_start;
9045 }
9046
af6bdddf
AM		 9047 --base_string;
9048 if (is_space_char (*base_string))
9049 --base_string;
252b5132 9050
47926f60 9051 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 9052 displacement_string_start = op_string;
9053 displacement_string_end = base_string + 1;
252b5132 9054
24eab124
AM		 9055 if (*base_string == ')')
9056 {
af6bdddf 9057 char *temp_string;
24eab124
AM		 9058 unsigned int parens_balanced = 1;
9059 /* We've already checked that the number of left & right ()'s are
47926f60 9060 equal, so this loop will not be infinite. */
24eab124
AM		 9061 do
9062 {
9063 base_string--;
9064 if (*base_string == ')')
9065 parens_balanced++;
9066 if (*base_string == '(')
9067 parens_balanced--;
9068 }
9069 while (parens_balanced);
c3332e24 9070
af6bdddf 9071 temp_string = base_string;
c3332e24 9072
24eab124 9073 /* Skip past '(' and whitespace. */
252b5132
RH		 9074 ++base_string;
9075 if (is_space_char (*base_string))
24eab124 9076 ++base_string;
252b5132 9077
af6bdddf 9078 if (*base_string == ','
4eed87de
AM		 9079 || ((i.base_reg = parse_register (base_string, &end_op))
9080 != NULL))
252b5132 9081 {
af6bdddf 9082 displacement_string_end = temp_string;
252b5132 9083
40fb9820 9084 i.types[this_operand].bitfield.baseindex = 1;
252b5132 9085
af6bdddf 9086 if (i.base_reg)
24eab124 9087 {
24eab124
AM		 9088 base_string = end_op;
9089 if (is_space_char (*base_string))
9090 ++base_string;
af6bdddf
AM		 9091 }
9092
9093 /* There may be an index reg or scale factor here. */
9094 if (*base_string == ',')
9095 {
9096 ++base_string;
9097 if (is_space_char (*base_string))
9098 ++base_string;
9099
4eed87de
AM		 9100 if ((i.index_reg = parse_register (base_string, &end_op))
9101 != NULL)
24eab124 9102 {
af6bdddf 9103 base_string = end_op;
24eab124
AM		 9104 if (is_space_char (*base_string))
9105 ++base_string;
af6bdddf
AM		 9106 if (*base_string == ',')
9107 {
9108 ++base_string;
9109 if (is_space_char (*base_string))
9110 ++base_string;
9111 }
e5cb08ac 9112 else if (*base_string != ')')
af6bdddf 9113 {
4eed87de
AM		 9114 as_bad (_("expecting `,' or `)' "
9115 "after index register in `%s'"),
af6bdddf
AM		 9116 operand_string);
9117 return 0;
9118 }
24eab124 9119 }
af6bdddf 9120 else if (*base_string == REGISTER_PREFIX)
24eab124 9121 {
f76bf5e0
L		 9122 end_op = strchr (base_string, ',');
9123 if (end_op)
9124 *end_op = '\0';
af6bdddf 9125 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 9126 return 0;
9127 }
252b5132 9128
47926f60 9129 /* Check for scale factor. */
551c1ca1 9130 if (*base_string != ')')
af6bdddf 9131 {
551c1ca1
AM		 9132 char *end_scale = i386_scale (base_string);
9133
9134 if (!end_scale)
af6bdddf 9135 return 0;
24eab124 9136
551c1ca1 9137 base_string = end_scale;
af6bdddf
AM		 9138 if (is_space_char (*base_string))
9139 ++base_string;
9140 if (*base_string != ')')
9141 {
4eed87de
AM		 9142 as_bad (_("expecting `)' "
9143 "after scale factor in `%s'"),
af6bdddf
AM		 9144 operand_string);
9145 return 0;
9146 }
9147 }
9148 else if (!i.index_reg)
24eab124 9149 {
4eed87de
AM		 9150 as_bad (_("expecting index register or scale factor "
9151 "after `,'; got '%c'"),
af6bdddf 9152 *base_string);
24eab124
AM		 9153 return 0;
9154 }
9155 }
af6bdddf 9156 else if (*base_string != ')')
24eab124 9157 {
4eed87de
AM		 9158 as_bad (_("expecting `,' or `)' "
9159 "after base register in `%s'"),
af6bdddf 9160 operand_string);
24eab124
AM		 9161 return 0;
9162 }
c3332e24 9163 }
af6bdddf 9164 else if (*base_string == REGISTER_PREFIX)
c3332e24 9165 {
f76bf5e0
L		 9166 end_op = strchr (base_string, ',');
9167 if (end_op)
9168 *end_op = '\0';
af6bdddf 9169 as_bad (_("bad register name `%s'"), base_string);
24eab124 9170 return 0;
c3332e24 9171 }
24eab124
AM		 9172 }
9173
9174 /* If there's an expression beginning the operand, parse it,
9175 assuming displacement_string_start and
9176 displacement_string_end are meaningful. */
9177 if (displacement_string_start != displacement_string_end)
9178 {
9179 if (!i386_displacement (displacement_string_start,
9180 displacement_string_end))
9181 return 0;
9182 }
9183
9184 /* Special case for (%dx) while doing input/output op. */
9185 if (i.base_reg
0dfbf9d7
L		 9186 && operand_type_equal (&i.base_reg->reg_type,
9187 &reg16_inoutportreg)
24eab124
AM		 9188 && i.index_reg == 0
9189 && i.log2_scale_factor == 0
9190 && i.seg[i.mem_operands] == 0
40fb9820 9191 && !operand_type_check (i.types[this_operand], disp))
24eab124 9192 {
65da13b5 9193 i.types[this_operand] = inoutportreg;
24eab124
AM		 9194 return 1;
9195 }
9196
eecb386c
AM		 9197 if (i386_index_check (operand_string) == 0)
9198 return 0;
5c07affc 9199 i.types[this_operand].bitfield.mem = 1;
8325cc63
JB		 9200 if (i.mem_operands == 0)
9201 i.memop1_string = xstrdup (operand_string);
24eab124
AM		 9202 i.mem_operands++;
9203 }
9204 else
ce8a8b2f
AM		 9205 {
9206 /* It's not a memory operand; argh! */
24eab124
AM		 9207 as_bad (_("invalid char %s beginning operand %d `%s'"),
9208 output_invalid (*op_string),
9209 this_operand + 1,
9210 op_string);
9211 return 0;
9212 }
47926f60 9213 return 1; /* Normal return. */
252b5132
RH		 9214}
9215\f
fa94de6b
RM		 9216/* Calculate the maximum variable size (i.e., excluding fr_fix)
9217 that an rs_machine_dependent frag may reach. */
9218
9219unsigned int
9220i386_frag_max_var (fragS *frag)
9221{
9222 /* The only relaxable frags are for jumps.
9223 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
9224 gas_assert (frag->fr_type == rs_machine_dependent);
9225 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
9226}
9227
b084df0b
L		 9228#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9229static int
8dcea932 9230elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var)
b084df0b
L		 9231{
9232 /* STT_GNU_IFUNC symbol must go through PLT. */
9233 if ((symbol_get_bfdsym (fr_symbol)->flags
9234 & BSF_GNU_INDIRECT_FUNCTION) != 0)
9235 return 0;
9236
9237 if (!S_IS_EXTERNAL (fr_symbol))
9238 /* Symbol may be weak or local. */
9239 return !S_IS_WEAK (fr_symbol);
9240
8dcea932
L		 9241 /* Global symbols with non-default visibility can't be preempted. */
9242 if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT)
9243 return 1;
9244
9245 if (fr_var != NO_RELOC)
9246 switch ((enum bfd_reloc_code_real) fr_var)
9247 {
9248 case BFD_RELOC_386_PLT32:
9249 case BFD_RELOC_X86_64_PLT32:
33eaf5de 9250 /* Symbol with PLT relocation may be preempted. */
8dcea932
L		 9251 return 0;
9252 default:
9253 abort ();
9254 }
9255
b084df0b
L		 9256 /* Global symbols with default visibility in a shared library may be
9257 preempted by another definition. */
8dcea932 9258 return !shared;
b084df0b
L		 9259}
9260#endif
9261
ee7fcc42
AM		 9262/* md_estimate_size_before_relax()
9263
9264 Called just before relax() for rs_machine_dependent frags. The x86
9265 assembler uses these frags to handle variable size jump
9266 instructions.
9267
9268 Any symbol that is now undefined will not become defined.
9269 Return the correct fr_subtype in the frag.
9270 Return the initial "guess for variable size of frag" to caller.
9271 The guess is actually the growth beyond the fixed part. Whatever
9272 we do to grow the fixed or variable part contributes to our
9273 returned value. */
9274
252b5132 9275int
7016a5d5 9276md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 9277{
252b5132 9278 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 9279 check for un-relaxable symbols. On an ELF system, we can't relax
9280 an externally visible symbol, because it may be overridden by a
9281 shared library. */
9282 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 9283#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9284 || (IS_ELF
8dcea932
L		 9285 && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol,
9286 fragP->fr_var))
fbeb56a4
DK		 9287#endif
9288#if defined (OBJ_COFF) && defined (TE_PE)
7ab9ffdd 9289 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
fbeb56a4 9290 && S_IS_WEAK (fragP->fr_symbol))
b98ef147
AM		 9291#endif
9292 )
252b5132 9293 {
b98ef147
AM		 9294 /* Symbol is undefined in this segment, or we need to keep a
9295 reloc so that weak symbols can be overridden. */
9296 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 9297 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 9298 unsigned char *opcode;
9299 int old_fr_fix;
f6af82bd 9300
ee7fcc42 9301 if (fragP->fr_var != NO_RELOC)
1e9cc1c2 9302 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
b98ef147 9303 else if (size == 2)
f6af82bd
AM		 9304 reloc_type = BFD_RELOC_16_PCREL;
9305 else
9306 reloc_type = BFD_RELOC_32_PCREL;
252b5132 9307
ee7fcc42
AM		 9308 old_fr_fix = fragP->fr_fix;
9309 opcode = (unsigned char *) fragP->fr_opcode;
9310
fddf5b5b 9311 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 9312 {
fddf5b5b
AM		 9313 case UNCOND_JUMP:
9314 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 9315 opcode[0] = 0xe9;
252b5132 9316 fragP->fr_fix += size;
062cd5e7
AS		 9317 fix_new (fragP, old_fr_fix, size,
9318 fragP->fr_symbol,
9319 fragP->fr_offset, 1,
9320 reloc_type);
252b5132
RH		 9321 break;
9322
fddf5b5b 9323 case COND_JUMP86:
412167cb
AM		 9324 if (size == 2
9325 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 9326 {
9327 /* Negate the condition, and branch past an
9328 unconditional jump. */
9329 opcode[0] ^= 1;
9330 opcode[1] = 3;
9331 /* Insert an unconditional jump. */
9332 opcode[2] = 0xe9;
9333 /* We added two extra opcode bytes, and have a two byte
9334 offset. */
9335 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 9336 fix_new (fragP, old_fr_fix + 2, 2,
9337 fragP->fr_symbol,
9338 fragP->fr_offset, 1,
9339 reloc_type);
fddf5b5b
AM		 9340 break;
9341 }
9342 /* Fall through. */
9343
9344 case COND_JUMP:
412167cb
AM		 9345 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
9346 {
3e02c1cc
AM		 9347 fixS *fixP;
9348
412167cb 9349 fragP->fr_fix += 1;
3e02c1cc
AM		 9350 fixP = fix_new (fragP, old_fr_fix, 1,
9351 fragP->fr_symbol,
9352 fragP->fr_offset, 1,
9353 BFD_RELOC_8_PCREL);
9354 fixP->fx_signed = 1;
412167cb
AM		 9355 break;
9356 }
93c2a809 9357
24eab124 9358 /* This changes the byte-displacement jump 0x7N
fddf5b5b 9359 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 9360 opcode[1] = opcode[0] + 0x10;
f6af82bd 9361 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 9362 /* We've added an opcode byte. */
9363 fragP->fr_fix += 1 + size;
062cd5e7
AS		 9364 fix_new (fragP, old_fr_fix + 1, size,
9365 fragP->fr_symbol,
9366 fragP->fr_offset, 1,
9367 reloc_type);
252b5132 9368 break;
fddf5b5b
AM		 9369
9370 default:
9371 BAD_CASE (fragP->fr_subtype);
9372 break;
252b5132
RH		 9373 }
9374 frag_wane (fragP);
ee7fcc42 9375 return fragP->fr_fix - old_fr_fix;
252b5132 9376 }
93c2a809 9377
93c2a809
AM		 9378 /* Guess size depending on current relax state. Initially the relax
9379 state will correspond to a short jump and we return 1, because
9380 the variable part of the frag (the branch offset) is one byte
9381 long. However, we can relax a section more than once and in that
9382 case we must either set fr_subtype back to the unrelaxed state,
9383 or return the value for the appropriate branch. */
9384 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 9385}
9386
47926f60
KH		 9387/* Called after relax() is finished.
9388
9389 In: Address of frag.
9390 fr_type == rs_machine_dependent.
9391 fr_subtype is what the address relaxed to.
9392
9393 Out: Any fixSs and constants are set up.
9394 Caller will turn frag into a ".space 0". */
9395
252b5132 9396void
7016a5d5
TG		 9397md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
9398 fragS *fragP)
252b5132 9399{
29b0f896 9400 unsigned char *opcode;
252b5132 9401 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 9402 offsetT target_address;
9403 offsetT opcode_address;
252b5132 9404 unsigned int extension = 0;
847f7ad4 9405 offsetT displacement_from_opcode_start;
252b5132
RH		 9406
9407 opcode = (unsigned char *) fragP->fr_opcode;
9408
47926f60 9409 /* Address we want to reach in file space. */
252b5132 9410 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 9411
47926f60 9412 /* Address opcode resides at in file space. */
252b5132
RH		 9413 opcode_address = fragP->fr_address + fragP->fr_fix;
9414
47926f60 9415 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 9416 displacement_from_opcode_start = target_address - opcode_address;
9417
fddf5b5b 9418 if ((fragP->fr_subtype & BIG) == 0)
252b5132 9419 {
47926f60
KH		 9420 /* Don't have to change opcode. */
9421 extension = 1; /* 1 opcode + 1 displacement */
252b5132 9422 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 9423 }
9424 else
9425 {
9426 if (no_cond_jump_promotion
9427 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 9428 as_warn_where (fragP->fr_file, fragP->fr_line,
9429 _("long jump required"));
252b5132 9430
fddf5b5b
AM		 9431 switch (fragP->fr_subtype)
9432 {
9433 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
9434 extension = 4; /* 1 opcode + 4 displacement */
9435 opcode[0] = 0xe9;
9436 where_to_put_displacement = &opcode[1];
9437 break;
252b5132 9438
fddf5b5b
AM		 9439 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
9440 extension = 2; /* 1 opcode + 2 displacement */
9441 opcode[0] = 0xe9;
9442 where_to_put_displacement = &opcode[1];
9443 break;
252b5132 9444
fddf5b5b
AM		 9445 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
9446 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
9447 extension = 5; /* 2 opcode + 4 displacement */
9448 opcode[1] = opcode[0] + 0x10;
9449 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9450 where_to_put_displacement = &opcode[2];
9451 break;
252b5132 9452
fddf5b5b
AM		 9453 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
9454 extension = 3; /* 2 opcode + 2 displacement */
9455 opcode[1] = opcode[0] + 0x10;
9456 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
9457 where_to_put_displacement = &opcode[2];
9458 break;
252b5132 9459
fddf5b5b
AM		 9460 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9461 extension = 4;
9462 opcode[0] ^= 1;
9463 opcode[1] = 3;
9464 opcode[2] = 0xe9;
9465 where_to_put_displacement = &opcode[3];
9466 break;
9467
9468 default:
9469 BAD_CASE (fragP->fr_subtype);
9470 break;
9471 }
252b5132 9472 }
fddf5b5b 9473
7b81dfbb
AJ		 9474 /* If size if less then four we are sure that the operand fits,
9475 but if it's 4, then it could be that the displacement is larger
9476 then -/+ 2GB. */
9477 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9478 && object_64bit
9479 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 9480 + ((addressT) 1 << 31))
9481 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 9482 {
9483 as_bad_where (fragP->fr_file, fragP->fr_line,
9484 _("jump target out of range"));
9485 /* Make us emit 0. */
9486 displacement_from_opcode_start = extension;
9487 }
47926f60 9488 /* Now put displacement after opcode. */
252b5132
RH		 9489 md_number_to_chars ((char *) where_to_put_displacement,
9490 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 9491 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 9492 fragP->fr_fix += extension;
9493}
9494\f
7016a5d5 9495/* Apply a fixup (fixP) to segment data, once it has been determined
252b5132
RH		 9496 by our caller that we have all the info we need to fix it up.
9497
7016a5d5
TG		 9498 Parameter valP is the pointer to the value of the bits.
9499
252b5132
RH		 9500 On the 386, immediates, displacements, and data pointers are all in
9501 the same (little-endian) format, so we don't need to care about which
9502 we are handling. */
9503
94f592af 9504void
7016a5d5 9505md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 9506{
94f592af 9507 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 9508 valueT value = *valP;
252b5132 9509
f86103b7 9510#if !defined (TE_Mach)
93382f6d
AM		 9511 if (fixP->fx_pcrel)
9512 {
9513 switch (fixP->fx_r_type)
9514 {
5865bb77
ILT		 9515 default:
9516 break;
9517
d6ab8113
JB		 9518 case BFD_RELOC_64:
9519 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9520 break;
93382f6d 9521 case BFD_RELOC_32:
ae8887b5 9522 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 9523 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9524 break;
9525 case BFD_RELOC_16:
9526 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9527 break;
9528 case BFD_RELOC_8:
9529 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9530 break;
9531 }
9532 }
252b5132 9533
a161fe53 9534 if (fixP->fx_addsy != NULL
31312f95 9535 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 9536 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95 9537 || fixP->fx_r_type == BFD_RELOC_16_PCREL
d258b828 9538 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
31312f95 9539 && !use_rela_relocations)
252b5132 9540 {
31312f95
AM		 9541 /* This is a hack. There should be a better way to handle this.
9542 This covers for the fact that bfd_install_relocation will
9543 subtract the current location (for partial_inplace, PC relative
9544 relocations); see more below. */
252b5132 9545#ifndef OBJ_AOUT
718ddfc0 9546 if (IS_ELF
252b5132
RH		 9547#ifdef TE_PE
9548 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9549#endif
9550 )
9551 value += fixP->fx_where + fixP->fx_frag->fr_address;
9552#endif
9553#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9554 if (IS_ELF)
252b5132 9555 {
6539b54b 9556 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 9557
6539b54b 9558 if ((sym_seg == seg
2f66722d 9559 || (symbol_section_p (fixP->fx_addsy)
6539b54b 9560 && sym_seg != absolute_section))
af65af87 9561 && !generic_force_reloc (fixP))
2f66722d
AM		 9562 {
9563 /* Yes, we add the values in twice. This is because
6539b54b
AM		 9564 bfd_install_relocation subtracts them out again. I think
9565 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 9566 it. FIXME. */
9567 value += fixP->fx_where + fixP->fx_frag->fr_address;
9568 }
252b5132
RH		 9569 }
9570#endif
9571#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 9572 /* For some reason, the PE format does not store a
9573 section address offset for a PC relative symbol. */
9574 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 9575 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 9576 value += md_pcrel_from (fixP);
9577#endif
9578 }
fbeb56a4 9579#if defined (OBJ_COFF) && defined (TE_PE)
f01c1a09
NC		 9580 if (fixP->fx_addsy != NULL
9581 && S_IS_WEAK (fixP->fx_addsy)
9582 /* PR 16858: Do not modify weak function references. */
9583 && ! fixP->fx_pcrel)
fbeb56a4 9584 {
296a8689
NC		 9585#if !defined (TE_PEP)
9586 /* For x86 PE weak function symbols are neither PC-relative
9587 nor do they set S_IS_FUNCTION. So the only reliable way
9588 to detect them is to check the flags of their containing
9589 section. */
9590 if (S_GET_SEGMENT (fixP->fx_addsy) != NULL
9591 && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE)
9592 ;
9593 else
9594#endif
fbeb56a4
DK		 9595 value -= S_GET_VALUE (fixP->fx_addsy);
9596 }
9597#endif
252b5132
RH		 9598
9599 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 9600 and we must not disappoint it. */
252b5132 9601#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 9602 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 9603 switch (fixP->fx_r_type)
9604 {
9605 case BFD_RELOC_386_PLT32:
3e73aa7c 9606 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 9607 /* Make the jump instruction point to the address of the operand. At
9608 runtime we merely add the offset to the actual PLT entry. */
9609 value = -4;
9610 break;
31312f95 9611
13ae64f3
JJ		 9612 case BFD_RELOC_386_TLS_GD:
9613 case BFD_RELOC_386_TLS_LDM:
13ae64f3 9614 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 9615 case BFD_RELOC_386_TLS_IE:
9616 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 9617 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 9618 case BFD_RELOC_X86_64_TLSGD:
9619 case BFD_RELOC_X86_64_TLSLD:
9620 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 9621 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 9622 value = 0; /* Fully resolved at runtime. No addend. */
9623 /* Fallthrough */
9624 case BFD_RELOC_386_TLS_LE:
9625 case BFD_RELOC_386_TLS_LDO_32:
9626 case BFD_RELOC_386_TLS_LE_32:
9627 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 9628 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 9629 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 9630 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 9631 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9632 break;
9633
67a4f2b7
AO		 9634 case BFD_RELOC_386_TLS_DESC_CALL:
9635 case BFD_RELOC_X86_64_TLSDESC_CALL:
9636 value = 0; /* Fully resolved at runtime. No addend. */
9637 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9638 fixP->fx_done = 0;
9639 return;
9640
47926f60
KH		 9641 case BFD_RELOC_VTABLE_INHERIT:
9642 case BFD_RELOC_VTABLE_ENTRY:
9643 fixP->fx_done = 0;
94f592af 9644 return;
47926f60
KH		 9645
9646 default:
9647 break;
9648 }
9649#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 9650 *valP = value;
f86103b7 9651#endif /* !defined (TE_Mach) */
3e73aa7c 9652
3e73aa7c 9653 /* Are we finished with this relocation now? */
c6682705 9654 if (fixP->fx_addsy == NULL)
3e73aa7c 9655 fixP->fx_done = 1;
fbeb56a4
DK		 9656#if defined (OBJ_COFF) && defined (TE_PE)
9657 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9658 {
9659 fixP->fx_done = 0;
9660 /* Remember value for tc_gen_reloc. */
9661 fixP->fx_addnumber = value;
9662 /* Clear out the frag for now. */
9663 value = 0;
9664 }
9665#endif
3e73aa7c
JH		 9666 else if (use_rela_relocations)
9667 {
9668 fixP->fx_no_overflow = 1;
062cd5e7
AS		 9669 /* Remember value for tc_gen_reloc. */
9670 fixP->fx_addnumber = value;
3e73aa7c
JH		 9671 value = 0;
9672 }
f86103b7 9673
94f592af 9674 md_number_to_chars (p, value, fixP->fx_size);
252b5132 9675}
252b5132 9676\f
6d4af3c2 9677const char *
499ac353 9678md_atof (int type, char *litP, int *sizeP)
252b5132 9679{
499ac353
NC		 9680 /* This outputs the LITTLENUMs in REVERSE order;
9681 in accord with the bigendian 386. */
9682 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 9683}
9684\f
2d545b82 9685static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 9686
252b5132 9687static char *
e3bb37b5 9688output_invalid (int c)
252b5132 9689{
3882b010 9690 if (ISPRINT (c))
f9f21a03
L		 9691 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9692 "'%c'", c);
252b5132 9693 else
f9f21a03 9694 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 9695 "(0x%x)", (unsigned char) c);
252b5132
RH		 9696 return output_invalid_buf;
9697}
9698
af6bdddf 9699/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 9700
9701static const reg_entry *
4d1bb795 9702parse_real_register (char *reg_string, char **end_op)
252b5132 9703{
af6bdddf
AM		 9704 char *s = reg_string;
9705 char *p;
252b5132
RH		 9706 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9707 const reg_entry *r;
9708
9709 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9710 if (*s == REGISTER_PREFIX)
9711 ++s;
9712
9713 if (is_space_char (*s))
9714 ++s;
9715
9716 p = reg_name_given;
af6bdddf 9717 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 9718 {
9719 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 9720 return (const reg_entry *) NULL;
9721 s++;
252b5132
RH		 9722 }
9723
6588847e
DN		 9724 /* For naked regs, make sure that we are not dealing with an identifier.
9725 This prevents confusing an identifier like `eax_var' with register
9726 `eax'. */
9727 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9728 return (const reg_entry *) NULL;
9729
af6bdddf 9730 *end_op = s;
252b5132
RH		 9731
9732 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9733
5f47d35b 9734 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 9735 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 9736 {
5f47d35b
AM		 9737 if (is_space_char (*s))
9738 ++s;
9739 if (*s == '(')
9740 {
af6bdddf 9741 ++s;
5f47d35b
AM		 9742 if (is_space_char (*s))
9743 ++s;
9744 if (*s >= '0' && *s <= '7')
9745 {
db557034 9746 int fpr = *s - '0';
af6bdddf 9747 ++s;
5f47d35b
AM		 9748 if (is_space_char (*s))
9749 ++s;
9750 if (*s == ')')
9751 {
9752 *end_op = s + 1;
1e9cc1c2 9753 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
db557034
AM		 9754 know (r);
9755 return r + fpr;
5f47d35b 9756 }
5f47d35b 9757 }
47926f60 9758 /* We have "%st(" then garbage. */
5f47d35b
AM		 9759 return (const reg_entry *) NULL;
9760 }
9761 }
9762
a60de03c
JB		 9763 if (r == NULL || allow_pseudo_reg)
9764 return r;
9765
0dfbf9d7 9766 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 9767 return (const reg_entry *) NULL;
9768
dc821c5f 9769 if ((r->reg_type.bitfield.dword
192dc9c6
JB		 9770 || r->reg_type.bitfield.sreg3
9771 || r->reg_type.bitfield.control
9772 || r->reg_type.bitfield.debug
9773 || r->reg_type.bitfield.test)
9774 && !cpu_arch_flags.bitfield.cpui386)
9775 return (const reg_entry *) NULL;
9776
ca0d63fe 9777 if (r->reg_type.bitfield.tbyte
309d3373
JB		 9778 && !cpu_arch_flags.bitfield.cpu8087
9779 && !cpu_arch_flags.bitfield.cpu287
9780 && !cpu_arch_flags.bitfield.cpu387)
9781 return (const reg_entry *) NULL;
9782
1848e567 9783 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpuregmmx)
192dc9c6
JB		 9784 return (const reg_entry *) NULL;
9785
1b54b8d7 9786 if (r->reg_type.bitfield.xmmword && !cpu_arch_flags.bitfield.cpuregxmm)
192dc9c6
JB		 9787 return (const reg_entry *) NULL;
9788
1b54b8d7 9789 if (r->reg_type.bitfield.ymmword && !cpu_arch_flags.bitfield.cpuregymm)
40f12533
L		 9790 return (const reg_entry *) NULL;
9791
1b54b8d7 9792 if (r->reg_type.bitfield.zmmword && !cpu_arch_flags.bitfield.cpuregzmm)
1848e567
L		 9793 return (const reg_entry *) NULL;
9794
9795 if (r->reg_type.bitfield.regmask
9796 && !cpu_arch_flags.bitfield.cpuregmask)
43234a1e
L		 9797 return (const reg_entry *) NULL;
9798
db51cc60 9799 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 9800 if (!allow_index_reg
db51cc60
L		 9801 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9802 return (const reg_entry *) NULL;
9803
43234a1e
L		 9804 /* Upper 16 vector register is only available with VREX in 64bit
9805 mode. */
9806 if ((r->reg_flags & RegVRex))
9807 {
86fa6981
L		 9808 if (i.vec_encoding == vex_encoding_default)
9809 i.vec_encoding = vex_encoding_evex;
9810
43234a1e 9811 if (!cpu_arch_flags.bitfield.cpuvrex
86fa6981 9812 || i.vec_encoding != vex_encoding_evex
43234a1e
L		 9813 || flag_code != CODE_64BIT)
9814 return (const reg_entry *) NULL;
43234a1e
L		 9815 }
9816
a60de03c 9817 if (((r->reg_flags & (RegRex64 | RegRex))
dc821c5f 9818 || r->reg_type.bitfield.qword)
40fb9820 9819 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 9820 || !operand_type_equal (&r->reg_type, &control))
1ae00879 9821 && flag_code != CODE_64BIT)
20f0a1fc 9822 return (const reg_entry *) NULL;
1ae00879 9823
b7240065
JB		 9824 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9825 return (const reg_entry *) NULL;
9826
252b5132
RH		 9827 return r;
9828}
4d1bb795
JB		 9829
9830/* REG_STRING starts *before* REGISTER_PREFIX. */
9831
9832static const reg_entry *
9833parse_register (char *reg_string, char **end_op)
9834{
9835 const reg_entry *r;
9836
9837 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9838 r = parse_real_register (reg_string, end_op);
9839 else
9840 r = NULL;
9841 if (!r)
9842 {
9843 char *save = input_line_pointer;
9844 char c;
9845 symbolS *symbolP;
9846
9847 input_line_pointer = reg_string;
d02603dc 9848 c = get_symbol_name (&reg_string);
4d1bb795
JB		 9849 symbolP = symbol_find (reg_string);
9850 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9851 {
9852 const expressionS *e = symbol_get_value_expression (symbolP);
9853
0398aac5 9854 know (e->X_op == O_register);
4eed87de 9855 know (e->X_add_number >= 0
c3fe08fa 9856 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795 9857 r = i386_regtab + e->X_add_number;
d3bb6b49 9858 if ((r->reg_flags & RegVRex))
86fa6981 9859 i.vec_encoding = vex_encoding_evex;
4d1bb795
JB		 9860 *end_op = input_line_pointer;
9861 }
9862 *input_line_pointer = c;
9863 input_line_pointer = save;
9864 }
9865 return r;
9866}
9867
9868int
9869i386_parse_name (char *name, expressionS *e, char *nextcharP)
9870{
9871 const reg_entry *r;
9872 char *end = input_line_pointer;
9873
9874 *end = *nextcharP;
9875 r = parse_register (name, &input_line_pointer);
9876 if (r && end <= input_line_pointer)
9877 {
9878 *nextcharP = *input_line_pointer;
9879 *input_line_pointer = 0;
9880 e->X_op = O_register;
9881 e->X_add_number = r - i386_regtab;
9882 return 1;
9883 }
9884 input_line_pointer = end;
9885 *end = 0;
ee86248c 9886 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
4d1bb795
JB		 9887}
9888
9889void
9890md_operand (expressionS *e)
9891{
ee86248c
JB		 9892 char *end;
9893 const reg_entry *r;
4d1bb795 9894
ee86248c
JB		 9895 switch (*input_line_pointer)
9896 {
9897 case REGISTER_PREFIX:
9898 r = parse_real_register (input_line_pointer, &end);
4d1bb795
JB		 9899 if (r)
9900 {
9901 e->X_op = O_register;
9902 e->X_add_number = r - i386_regtab;
9903 input_line_pointer = end;
9904 }
ee86248c
JB		 9905 break;
9906
9907 case '[':
9c2799c2 9908 gas_assert (intel_syntax);
ee86248c
JB		 9909 end = input_line_pointer++;
9910 expression (e);
9911 if (*input_line_pointer == ']')
9912 {
9913 ++input_line_pointer;
9914 e->X_op_symbol = make_expr_symbol (e);
9915 e->X_add_symbol = NULL;
9916 e->X_add_number = 0;
9917 e->X_op = O_index;
9918 }
9919 else
9920 {
9921 e->X_op = O_absent;
9922 input_line_pointer = end;
9923 }
9924 break;
4d1bb795
JB		 9925 }
9926}
9927
252b5132 9928\f
4cc782b5 9929#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 9930const char *md_shortopts = "kVQ:sqn";
252b5132 9931#else
12b55ccc 9932const char *md_shortopts = "qn";
252b5132 9933#endif
6e0b89ee 9934
3e73aa7c 9935#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 9936#define OPTION_64 (OPTION_MD_BASE + 1)
9937#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 9938#define OPTION_MARCH (OPTION_MD_BASE + 3)
9939#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 9940#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9941#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9942#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9943#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9944#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 9945#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 9946#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7bab8ab5
JB		 9947#define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9948#define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9949#define OPTION_X32 (OPTION_MD_BASE + 14)
7e8b059b 9950#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
43234a1e
L		 9951#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9952#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
167ad85b 9953#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
d1982f93 9954#define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
d3d3c6db 9955#define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
8dcea932 9956#define OPTION_MSHARED (OPTION_MD_BASE + 21)
5db04b09
L		 9957#define OPTION_MAMD64 (OPTION_MD_BASE + 22)
9958#define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
e4e00185 9959#define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
0cb4071e 9960#define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 25)
b3b91714 9961
99ad8390
NC		 9962struct option md_longopts[] =
9963{
3e73aa7c 9964 {"32", no_argument, NULL, OPTION_32},
321098a5 9965#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 9966 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c 9967 {"64", no_argument, NULL, OPTION_64},
351f65ca
L		 9968#endif
9969#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 9970 {"x32", no_argument, NULL, OPTION_X32},
8dcea932 9971 {"mshared", no_argument, NULL, OPTION_MSHARED},
6e0b89ee 9972#endif
b3b91714 9973 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 9974 {"march", required_argument, NULL, OPTION_MARCH},
9975 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 9976 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9977 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9978 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9979 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9980 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 9981 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 9982 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
7bab8ab5 9983 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
539f890d 9984 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
7e8b059b 9985 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
43234a1e
L		 9986 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9987 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
167ad85b
TG		 9988# if defined (TE_PE) || defined (TE_PEP)
9989 {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ},
9990#endif
d1982f93 9991 {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX},
e4e00185 9992 {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD},
0cb4071e 9993 {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS},
d3d3c6db 9994 {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG},
5db04b09
L		 9995 {"mamd64", no_argument, NULL, OPTION_MAMD64},
9996 {"mintel64", no_argument, NULL, OPTION_MINTEL64},
252b5132
RH		 9997 {NULL, no_argument, NULL, 0}
9998};
9999size_t md_longopts_size = sizeof (md_longopts);
10000
10001int
17b9d67d 10002md_parse_option (int c, const char *arg)
252b5132 10003{
91d6fa6a 10004 unsigned int j;
293f5f65 10005 char *arch, *next, *saved;
9103f4f4 10006
252b5132
RH		 10007 switch (c)
10008 {
12b55ccc
L		 10009 case 'n':
10010 optimize_align_code = 0;
10011 break;
10012
a38cf1db
AM		 10013 case 'q':
10014 quiet_warnings = 1;
252b5132
RH		 10015 break;
10016
10017#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 10018 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
10019 should be emitted or not. FIXME: Not implemented. */
10020 case 'Q':
252b5132
RH		 10021 break;
10022
10023 /* -V: SVR4 argument to print version ID. */
10024 case 'V':
10025 print_version_id ();
10026 break;
10027
a38cf1db
AM		 10028 /* -k: Ignore for FreeBSD compatibility. */
10029 case 'k':
252b5132 10030 break;
4cc782b5
ILT		 10031
10032 case 's':
10033 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 10034 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 10035 break;
8dcea932
L		 10036
10037 case OPTION_MSHARED:
10038 shared = 1;
10039 break;
99ad8390 10040#endif
321098a5 10041#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
d382c579 10042 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
3e73aa7c
JH		 10043 case OPTION_64:
10044 {
10045 const char **list, **l;
10046
3e73aa7c
JH		 10047 list = bfd_target_list ();
10048 for (l = list; *l != NULL; l++)
8620418b 10049 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 10050 || strcmp (*l, "coff-x86-64") == 0
10051 || strcmp (*l, "pe-x86-64") == 0
d382c579
TG		 10052 || strcmp (*l, "pei-x86-64") == 0
10053 || strcmp (*l, "mach-o-x86-64") == 0)
6e0b89ee
AM		 10054 {
10055 default_arch = "x86_64";
10056 break;
10057 }
3e73aa7c 10058 if (*l == NULL)
2b5d6a91 10059 as_fatal (_("no compiled in support for x86_64"));
3e73aa7c
JH		 10060 free (list);
10061 }
10062 break;
10063#endif
252b5132 10064
351f65ca 10065#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
570561f7 10066 case OPTION_X32:
351f65ca
L		 10067 if (IS_ELF)
10068 {
10069 const char **list, **l;
10070
10071 list = bfd_target_list ();
10072 for (l = list; *l != NULL; l++)
10073 if (CONST_STRNEQ (*l, "elf32-x86-64"))
10074 {
10075 default_arch = "x86_64:32";
10076 break;
10077 }
10078 if (*l == NULL)
2b5d6a91 10079 as_fatal (_("no compiled in support for 32bit x86_64"));
351f65ca
L		 10080 free (list);
10081 }
10082 else
10083 as_fatal (_("32bit x86_64 is only supported for ELF"));
10084 break;
10085#endif
10086
6e0b89ee
AM		 10087 case OPTION_32:
10088 default_arch = "i386";
10089 break;
10090
b3b91714
AM		 10091 case OPTION_DIVIDE:
10092#ifdef SVR4_COMMENT_CHARS
10093 {
10094 char *n, *t;
10095 const char *s;
10096
add39d23 10097 n = XNEWVEC (char, strlen (i386_comment_chars) + 1);
b3b91714
AM		 10098 t = n;
10099 for (s = i386_comment_chars; *s != '\0'; s++)
10100 if (*s != '/')
10101 *t++ = *s;
10102 *t = '\0';
10103 i386_comment_chars = n;
10104 }
10105#endif
10106 break;
10107
9103f4f4 10108 case OPTION_MARCH:
293f5f65
L		 10109 saved = xstrdup (arg);
10110 arch = saved;
10111 /* Allow -march=+nosse. */
10112 if (*arch == '+')
10113 arch++;
6305a203 10114 do
9103f4f4 10115 {
6305a203 10116 if (*arch == '.')
2b5d6a91 10117 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10118 next = strchr (arch, '+');
10119 if (next)
10120 *next++ = '\0';
91d6fa6a 10121 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10122 {
91d6fa6a 10123 if (strcmp (arch, cpu_arch [j].name) == 0)
ccc9c027 10124 {
6305a203 10125 /* Processor. */
1ded5609
JB		 10126 if (! cpu_arch[j].flags.bitfield.cpui386)
10127 continue;
10128
91d6fa6a 10129 cpu_arch_name = cpu_arch[j].name;
6305a203 10130 cpu_sub_arch_name = NULL;
91d6fa6a
NC		 10131 cpu_arch_flags = cpu_arch[j].flags;
10132 cpu_arch_isa = cpu_arch[j].type;
10133 cpu_arch_isa_flags = cpu_arch[j].flags;
6305a203
L		 10134 if (!cpu_arch_tune_set)
10135 {
10136 cpu_arch_tune = cpu_arch_isa;
10137 cpu_arch_tune_flags = cpu_arch_isa_flags;
10138 }
10139 break;
10140 }
91d6fa6a
NC		 10141 else if (*cpu_arch [j].name == '.'
10142 && strcmp (arch, cpu_arch [j].name + 1) == 0)
6305a203 10143 {
33eaf5de 10144 /* ISA extension. */
6305a203 10145 i386_cpu_flags flags;
309d3373 10146
293f5f65
L		 10147 flags = cpu_flags_or (cpu_arch_flags,
10148 cpu_arch[j].flags);
81486035 10149
5b64d091 10150 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 10151 {
10152 if (cpu_sub_arch_name)
10153 {
10154 char *name = cpu_sub_arch_name;
10155 cpu_sub_arch_name = concat (name,
91d6fa6a 10156 cpu_arch[j].name,
1bf57e9f 10157 (const char *) NULL);
6305a203
L		 10158 free (name);
10159 }
10160 else
91d6fa6a 10161 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
6305a203 10162 cpu_arch_flags = flags;
a586129e 10163 cpu_arch_isa_flags = flags;
6305a203
L		 10164 }
10165 break;
ccc9c027 10166 }
9103f4f4 10167 }
6305a203 10168
293f5f65
L		 10169 if (j >= ARRAY_SIZE (cpu_arch))
10170 {
33eaf5de 10171 /* Disable an ISA extension. */
293f5f65
L		 10172 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10173 if (strcmp (arch, cpu_noarch [j].name) == 0)
10174 {
10175 i386_cpu_flags flags;
10176
10177 flags = cpu_flags_and_not (cpu_arch_flags,
10178 cpu_noarch[j].flags);
10179 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
10180 {
10181 if (cpu_sub_arch_name)
10182 {
10183 char *name = cpu_sub_arch_name;
10184 cpu_sub_arch_name = concat (arch,
10185 (const char *) NULL);
10186 free (name);
10187 }
10188 else
10189 cpu_sub_arch_name = xstrdup (arch);
10190 cpu_arch_flags = flags;
10191 cpu_arch_isa_flags = flags;
10192 }
10193 break;
10194 }
10195
10196 if (j >= ARRAY_SIZE (cpu_noarch))
10197 j = ARRAY_SIZE (cpu_arch);
10198 }
10199
91d6fa6a 10200 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10201 as_fatal (_("invalid -march= option: `%s'"), arg);
6305a203
L		 10202
10203 arch = next;
9103f4f4 10204 }
293f5f65
L		 10205 while (next != NULL);
10206 free (saved);
9103f4f4
L		 10207 break;
10208
10209 case OPTION_MTUNE:
10210 if (*arg == '.')
2b5d6a91 10211 as_fatal (_("invalid -mtune= option: `%s'"), arg);
91d6fa6a 10212 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9103f4f4 10213 {
91d6fa6a 10214 if (strcmp (arg, cpu_arch [j].name) == 0)
9103f4f4 10215 {
ccc9c027 10216 cpu_arch_tune_set = 1;
91d6fa6a
NC		 10217 cpu_arch_tune = cpu_arch [j].type;
10218 cpu_arch_tune_flags = cpu_arch[j].flags;
9103f4f4
L		 10219 break;
10220 }
10221 }
91d6fa6a 10222 if (j >= ARRAY_SIZE (cpu_arch))
2b5d6a91 10223 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9103f4f4
L		 10224 break;
10225
1efbbeb4
L		 10226 case OPTION_MMNEMONIC:
10227 if (strcasecmp (arg, "att") == 0)
10228 intel_mnemonic = 0;
10229 else if (strcasecmp (arg, "intel") == 0)
10230 intel_mnemonic = 1;
10231 else
2b5d6a91 10232 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
1efbbeb4
L		 10233 break;
10234
10235 case OPTION_MSYNTAX:
10236 if (strcasecmp (arg, "att") == 0)
10237 intel_syntax = 0;
10238 else if (strcasecmp (arg, "intel") == 0)
10239 intel_syntax = 1;
10240 else
2b5d6a91 10241 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
1efbbeb4
L		 10242 break;
10243
10244 case OPTION_MINDEX_REG:
10245 allow_index_reg = 1;
10246 break;
10247
10248 case OPTION_MNAKED_REG:
10249 allow_naked_reg = 1;
10250 break;
10251
10252 case OPTION_MOLD_GCC:
10253 old_gcc = 1;
1efbbeb4
L		 10254 break;
10255
c0f3af97
L		 10256 case OPTION_MSSE2AVX:
10257 sse2avx = 1;
10258 break;
10259
daf50ae7
L		 10260 case OPTION_MSSE_CHECK:
10261 if (strcasecmp (arg, "error") == 0)
7bab8ab5 10262 sse_check = check_error;
daf50ae7 10263 else if (strcasecmp (arg, "warning") == 0)
7bab8ab5 10264 sse_check = check_warning;
daf50ae7 10265 else if (strcasecmp (arg, "none") == 0)
7bab8ab5 10266 sse_check = check_none;
daf50ae7 10267 else
2b5d6a91 10268 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
daf50ae7
L		 10269 break;
10270
7bab8ab5
JB		 10271 case OPTION_MOPERAND_CHECK:
10272 if (strcasecmp (arg, "error") == 0)
10273 operand_check = check_error;
10274 else if (strcasecmp (arg, "warning") == 0)
10275 operand_check = check_warning;
10276 else if (strcasecmp (arg, "none") == 0)
10277 operand_check = check_none;
10278 else
10279 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
10280 break;
10281
539f890d
L		 10282 case OPTION_MAVXSCALAR:
10283 if (strcasecmp (arg, "128") == 0)
10284 avxscalar = vex128;
10285 else if (strcasecmp (arg, "256") == 0)
10286 avxscalar = vex256;
10287 else
2b5d6a91 10288 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
539f890d
L		 10289 break;
10290
7e8b059b
L		 10291 case OPTION_MADD_BND_PREFIX:
10292 add_bnd_prefix = 1;
10293 break;
10294
43234a1e
L		 10295 case OPTION_MEVEXLIG:
10296 if (strcmp (arg, "128") == 0)
10297 evexlig = evexl128;
10298 else if (strcmp (arg, "256") == 0)
10299 evexlig = evexl256;
10300 else if (strcmp (arg, "512") == 0)
10301 evexlig = evexl512;
10302 else
10303 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
10304 break;
10305
d3d3c6db
IT		 10306 case OPTION_MEVEXRCIG:
10307 if (strcmp (arg, "rne") == 0)
10308 evexrcig = rne;
10309 else if (strcmp (arg, "rd") == 0)
10310 evexrcig = rd;
10311 else if (strcmp (arg, "ru") == 0)
10312 evexrcig = ru;
10313 else if (strcmp (arg, "rz") == 0)
10314 evexrcig = rz;
10315 else
10316 as_fatal (_("invalid -mevexrcig= option: `%s'"), arg);
10317 break;
10318
43234a1e
L		 10319 case OPTION_MEVEXWIG:
10320 if (strcmp (arg, "0") == 0)
10321 evexwig = evexw0;
10322 else if (strcmp (arg, "1") == 0)
10323 evexwig = evexw1;
10324 else
10325 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
10326 break;
10327
167ad85b
TG		 10328# if defined (TE_PE) || defined (TE_PEP)
10329 case OPTION_MBIG_OBJ:
10330 use_big_obj = 1;
10331 break;
10332#endif
10333
d1982f93 10334 case OPTION_MOMIT_LOCK_PREFIX:
d022bddd
IT		 10335 if (strcasecmp (arg, "yes") == 0)
10336 omit_lock_prefix = 1;
10337 else if (strcasecmp (arg, "no") == 0)
10338 omit_lock_prefix = 0;
10339 else
10340 as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg);
10341 break;
10342
e4e00185
AS		 10343 case OPTION_MFENCE_AS_LOCK_ADD:
10344 if (strcasecmp (arg, "yes") == 0)
10345 avoid_fence = 1;
10346 else if (strcasecmp (arg, "no") == 0)
10347 avoid_fence = 0;
10348 else
10349 as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg);
10350 break;
10351
0cb4071e
L		 10352 case OPTION_MRELAX_RELOCATIONS:
10353 if (strcasecmp (arg, "yes") == 0)
10354 generate_relax_relocations = 1;
10355 else if (strcasecmp (arg, "no") == 0)
10356 generate_relax_relocations = 0;
10357 else
10358 as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg);
10359 break;
10360
5db04b09 10361 case OPTION_MAMD64:
e89c5eaa 10362 intel64 = 0;
5db04b09
L		 10363 break;
10364
10365 case OPTION_MINTEL64:
e89c5eaa 10366 intel64 = 1;
5db04b09
L		 10367 break;
10368
252b5132
RH		 10369 default:
10370 return 0;
10371 }
10372 return 1;
10373}
10374
8a2c8fef
L		 10375#define MESSAGE_TEMPLATE \
10376" "
10377
293f5f65
L		 10378static char *
10379output_message (FILE *stream, char *p, char *message, char *start,
10380 int *left_p, const char *name, int len)
10381{
10382 int size = sizeof (MESSAGE_TEMPLATE);
10383 int left = *left_p;
10384
10385 /* Reserve 2 spaces for ", " or ",\0" */
10386 left -= len + 2;
10387
10388 /* Check if there is any room. */
10389 if (left >= 0)
10390 {
10391 if (p != start)
10392 {
10393 *p++ = ',';
10394 *p++ = ' ';
10395 }
10396 p = mempcpy (p, name, len);
10397 }
10398 else
10399 {
10400 /* Output the current message now and start a new one. */
10401 *p++ = ',';
10402 *p = '\0';
10403 fprintf (stream, "%s\n", message);
10404 p = start;
10405 left = size - (start - message) - len - 2;
10406
10407 gas_assert (left >= 0);
10408
10409 p = mempcpy (p, name, len);
10410 }
10411
10412 *left_p = left;
10413 return p;
10414}
10415
8a2c8fef 10416static void
1ded5609 10417show_arch (FILE *stream, int ext, int check)
8a2c8fef
L		 10418{
10419 static char message[] = MESSAGE_TEMPLATE;
10420 char *start = message + 27;
10421 char *p;
10422 int size = sizeof (MESSAGE_TEMPLATE);
10423 int left;
10424 const char *name;
10425 int len;
10426 unsigned int j;
10427
10428 p = start;
10429 left = size - (start - message);
10430 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
10431 {
10432 /* Should it be skipped? */
10433 if (cpu_arch [j].skip)
10434 continue;
10435
10436 name = cpu_arch [j].name;
10437 len = cpu_arch [j].len;
10438 if (*name == '.')
10439 {
10440 /* It is an extension. Skip if we aren't asked to show it. */
10441 if (ext)
10442 {
10443 name++;
10444 len--;
10445 }
10446 else
10447 continue;
10448 }
10449 else if (ext)
10450 {
10451 /* It is an processor. Skip if we show only extension. */
10452 continue;
10453 }
1ded5609
JB		 10454 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
10455 {
10456 /* It is an impossible processor - skip. */
10457 continue;
10458 }
8a2c8fef 10459
293f5f65 10460 p = output_message (stream, p, message, start, &left, name, len);
8a2c8fef
L		 10461 }
10462
293f5f65
L		 10463 /* Display disabled extensions. */
10464 if (ext)
10465 for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
10466 {
10467 name = cpu_noarch [j].name;
10468 len = cpu_noarch [j].len;
10469 p = output_message (stream, p, message, start, &left, name,
10470 len);
10471 }
10472
8a2c8fef
L		 10473 *p = '\0';
10474 fprintf (stream, "%s\n", message);
10475}
10476
252b5132 10477void
8a2c8fef 10478md_show_usage (FILE *stream)
252b5132 10479{
4cc782b5
ILT		 10480#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10481 fprintf (stream, _("\
a38cf1db
AM		 10482 -Q ignored\n\
10483 -V print assembler version number\n\
b3b91714
AM		 10484 -k ignored\n"));
10485#endif
10486 fprintf (stream, _("\
12b55ccc 10487 -n Do not optimize code alignment\n\
b3b91714
AM		 10488 -q quieten some warnings\n"));
10489#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10490 fprintf (stream, _("\
a38cf1db 10491 -s ignored\n"));
b3b91714 10492#endif
321098a5
L		 10493#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
10494 || defined (TE_PE) || defined (TE_PEP))
751d281c 10495 fprintf (stream, _("\
570561f7 10496 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
751d281c 10497#endif
b3b91714
AM		 10498#ifdef SVR4_COMMENT_CHARS
10499 fprintf (stream, _("\
10500 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 10501#else
10502 fprintf (stream, _("\
b3b91714 10503 --divide ignored\n"));
4cc782b5 10504#endif
9103f4f4 10505 fprintf (stream, _("\
6305a203 10506 -march=CPU[,+EXTENSION...]\n\
8a2c8fef 10507 generate code for CPU and EXTENSION, CPU is one of:\n"));
1ded5609 10508 show_arch (stream, 0, 1);
8a2c8fef
L		 10509 fprintf (stream, _("\
10510 EXTENSION is combination of:\n"));
1ded5609 10511 show_arch (stream, 1, 0);
6305a203 10512 fprintf (stream, _("\
8a2c8fef 10513 -mtune=CPU optimize for CPU, CPU is one of:\n"));
1ded5609 10514 show_arch (stream, 0, 0);
ba104c83 10515 fprintf (stream, _("\
c0f3af97
L		 10516 -msse2avx encode SSE instructions with VEX prefix\n"));
10517 fprintf (stream, _("\
daf50ae7
L		 10518 -msse-check=[none|error|warning]\n\
10519 check SSE instructions\n"));
10520 fprintf (stream, _("\
7bab8ab5
JB		 10521 -moperand-check=[none|error|warning]\n\
10522 check operand combinations for validity\n"));
10523 fprintf (stream, _("\
539f890d
L		 10524 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
10525 length\n"));
10526 fprintf (stream, _("\
43234a1e
L		 10527 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
10528 length\n"));
10529 fprintf (stream, _("\
10530 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
10531 for EVEX.W bit ignored instructions\n"));
10532 fprintf (stream, _("\
d3d3c6db
IT		 10533 -mevexrcig=[rne|rd|ru|rz]\n\
10534 encode EVEX instructions with specific EVEX.RC value\n\
10535 for SAE-only ignored instructions\n"));
10536 fprintf (stream, _("\
ba104c83
L		 10537 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
10538 fprintf (stream, _("\
10539 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
10540 fprintf (stream, _("\
10541 -mindex-reg support pseudo index registers\n"));
10542 fprintf (stream, _("\
10543 -mnaked-reg don't require `%%' prefix for registers\n"));
10544 fprintf (stream, _("\
10545 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7e8b059b
L		 10546 fprintf (stream, _("\
10547 -madd-bnd-prefix add BND prefix for all valid branches\n"));
8dcea932
L		 10548 fprintf (stream, _("\
10549 -mshared disable branch optimization for shared code\n"));
167ad85b
TG		 10550# if defined (TE_PE) || defined (TE_PEP)
10551 fprintf (stream, _("\
10552 -mbig-obj generate big object files\n"));
10553#endif
d022bddd
IT		 10554 fprintf (stream, _("\
10555 -momit-lock-prefix=[no|yes]\n\
10556 strip all lock prefixes\n"));
5db04b09 10557 fprintf (stream, _("\
e4e00185
AS		 10558 -mfence-as-lock-add=[no|yes]\n\
10559 encode lfence, mfence and sfence as\n\
10560 lock addl $0x0, (%%{re}sp)\n"));
10561 fprintf (stream, _("\
0cb4071e
L		 10562 -mrelax-relocations=[no|yes]\n\
10563 generate relax relocations\n"));
10564 fprintf (stream, _("\
5db04b09
L		 10565 -mamd64 accept only AMD64 ISA\n"));
10566 fprintf (stream, _("\
10567 -mintel64 accept only Intel64 ISA\n"));
252b5132
RH		 10568}
10569
3e73aa7c 10570#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
321098a5 10571 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
e57f8c65 10572 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
252b5132
RH		 10573
10574/* Pick the target format to use. */
10575
47926f60 10576const char *
e3bb37b5 10577i386_target_format (void)
252b5132 10578{
351f65ca
L		 10579 if (!strncmp (default_arch, "x86_64", 6))
10580 {
10581 update_code_flag (CODE_64BIT, 1);
10582 if (default_arch[6] == '\0')
7f56bc95 10583 x86_elf_abi = X86_64_ABI;
351f65ca 10584 else
7f56bc95 10585 x86_elf_abi = X86_64_X32_ABI;
351f65ca 10586 }
3e73aa7c 10587 else if (!strcmp (default_arch, "i386"))
78f12dd3 10588 update_code_flag (CODE_32BIT, 1);
5197d474
L		 10589 else if (!strcmp (default_arch, "iamcu"))
10590 {
10591 update_code_flag (CODE_32BIT, 1);
10592 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
10593 {
10594 static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS;
10595 cpu_arch_name = "iamcu";
10596 cpu_sub_arch_name = NULL;
10597 cpu_arch_flags = iamcu_flags;
10598 cpu_arch_isa = PROCESSOR_IAMCU;
10599 cpu_arch_isa_flags = iamcu_flags;
10600 if (!cpu_arch_tune_set)
10601 {
10602 cpu_arch_tune = cpu_arch_isa;
10603 cpu_arch_tune_flags = cpu_arch_isa_flags;
10604 }
10605 }
8d471ec1 10606 else if (cpu_arch_isa != PROCESSOR_IAMCU)
5197d474
L		 10607 as_fatal (_("Intel MCU doesn't support `%s' architecture"),
10608 cpu_arch_name);
10609 }
3e73aa7c 10610 else
2b5d6a91 10611 as_fatal (_("unknown architecture"));
89507696
JB		 10612
10613 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
10614 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10615 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
10616 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
10617
252b5132
RH		 10618 switch (OUTPUT_FLAVOR)
10619 {
9384f2ff 10620#if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
4c63da97 10621 case bfd_target_aout_flavour:
47926f60 10622 return AOUT_TARGET_FORMAT;
4c63da97 10623#endif
9384f2ff
AM		 10624#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
10625# if defined (TE_PE) || defined (TE_PEP)
10626 case bfd_target_coff_flavour:
167ad85b
TG		 10627 if (flag_code == CODE_64BIT)
10628 return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64";
10629 else
10630 return "pe-i386";
9384f2ff 10631# elif defined (TE_GO32)
0561d57c
JK		 10632 case bfd_target_coff_flavour:
10633 return "coff-go32";
9384f2ff 10634# else
252b5132
RH		 10635 case bfd_target_coff_flavour:
10636 return "coff-i386";
9384f2ff 10637# endif
4c63da97 10638#endif
3e73aa7c 10639#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 10640 case bfd_target_elf_flavour:
3e73aa7c 10641 {
351f65ca
L		 10642 const char *format;
10643
10644 switch (x86_elf_abi)
4fa24527 10645 {
351f65ca
L		 10646 default:
10647 format = ELF_TARGET_FORMAT;
10648 break;
7f56bc95 10649 case X86_64_ABI:
351f65ca 10650 use_rela_relocations = 1;
4fa24527 10651 object_64bit = 1;
351f65ca
L		 10652 format = ELF_TARGET_FORMAT64;
10653 break;
7f56bc95 10654 case X86_64_X32_ABI:
4fa24527 10655 use_rela_relocations = 1;
351f65ca 10656 object_64bit = 1;
862be3fb 10657 disallow_64bit_reloc = 1;
351f65ca
L		 10658 format = ELF_TARGET_FORMAT32;
10659 break;
4fa24527 10660 }
3632d14b 10661 if (cpu_arch_isa == PROCESSOR_L1OM)
8a9036a4 10662 {
7f56bc95 10663 if (x86_elf_abi != X86_64_ABI)
8a9036a4
L		 10664 as_fatal (_("Intel L1OM is 64bit only"));
10665 return ELF_TARGET_L1OM_FORMAT;
10666 }
b49f93f6 10667 else if (cpu_arch_isa == PROCESSOR_K1OM)
7a9068fe
L		 10668 {
10669 if (x86_elf_abi != X86_64_ABI)
10670 as_fatal (_("Intel K1OM is 64bit only"));
10671 return ELF_TARGET_K1OM_FORMAT;
10672 }
81486035
L		 10673 else if (cpu_arch_isa == PROCESSOR_IAMCU)
10674 {
10675 if (x86_elf_abi != I386_ABI)
10676 as_fatal (_("Intel MCU is 32bit only"));
10677 return ELF_TARGET_IAMCU_FORMAT;
10678 }
8a9036a4 10679 else
351f65ca 10680 return format;
3e73aa7c 10681 }
e57f8c65
TG		 10682#endif
10683#if defined (OBJ_MACH_O)
10684 case bfd_target_mach_o_flavour:
d382c579
TG		 10685 if (flag_code == CODE_64BIT)
10686 {
10687 use_rela_relocations = 1;
10688 object_64bit = 1;
10689 return "mach-o-x86-64";
10690 }
10691 else
10692 return "mach-o-i386";
4c63da97 10693#endif
252b5132
RH		 10694 default:
10695 abort ();
10696 return NULL;
10697 }
10698}
10699
47926f60 10700#endif /* OBJ_MAYBE_ more than one */
252b5132 10701\f
252b5132 10702symbolS *
7016a5d5 10703md_undefined_symbol (char *name)
252b5132 10704{
18dc2407
ILT		 10705 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10706 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10707 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10708 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 10709 {
10710 if (!GOT_symbol)
10711 {
10712 if (symbol_find (name))
10713 as_bad (_("GOT already in symbol table"));
10714 GOT_symbol = symbol_new (name, undefined_section,
10715 (valueT) 0, &zero_address_frag);
10716 };
10717 return GOT_symbol;
10718 }
252b5132
RH		 10719 return 0;
10720}
10721
10722/* Round up a section size to the appropriate boundary. */
47926f60 10723
252b5132 10724valueT
7016a5d5 10725md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 10726{
4c63da97
AM		 10727#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10728 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10729 {
10730 /* For a.out, force the section size to be aligned. If we don't do
10731 this, BFD will align it for us, but it will not write out the
10732 final bytes of the section. This may be a bug in BFD, but it is
10733 easier to fix it here since that is how the other a.out targets
10734 work. */
10735 int align;
10736
10737 align = bfd_get_section_alignment (stdoutput, segment);
8d3842cd 10738 size = ((size + (1 << align) - 1) & (-((valueT) 1 << align)));
4c63da97 10739 }
252b5132
RH		 10740#endif
10741
10742 return size;
10743}
10744
10745/* On the i386, PC-relative offsets are relative to the start of the
10746 next instruction. That is, the address of the offset, plus its
10747 size, since the offset is always the last part of the insn. */
10748
10749long
e3bb37b5 10750md_pcrel_from (fixS *fixP)
252b5132
RH		 10751{
10752 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10753}
10754
10755#ifndef I386COFF
10756
10757static void
e3bb37b5 10758s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 10759{
29b0f896 10760 int temp;
252b5132 10761
8a75718c
JB		 10762#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10763 if (IS_ELF)
10764 obj_elf_section_change_hook ();
10765#endif
252b5132
RH		 10766 temp = get_absolute_expression ();
10767 subseg_set (bss_section, (subsegT) temp);
10768 demand_empty_rest_of_line ();
10769}
10770
10771#endif
10772
252b5132 10773void
e3bb37b5 10774i386_validate_fix (fixS *fixp)
252b5132 10775{
02a86693 10776 if (fixp->fx_subsy)
252b5132 10777 {
02a86693 10778 if (fixp->fx_subsy == GOT_symbol)
23df1078 10779 {
02a86693
L		 10780 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10781 {
10782 if (!object_64bit)
10783 abort ();
10784#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10785 if (fixp->fx_tcbit2)
56ceb5b5
L		 10786 fixp->fx_r_type = (fixp->fx_tcbit
10787 ? BFD_RELOC_X86_64_REX_GOTPCRELX
10788 : BFD_RELOC_X86_64_GOTPCRELX);
02a86693
L		 10789 else
10790#endif
10791 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10792 }
d6ab8113 10793 else
02a86693
L		 10794 {
10795 if (!object_64bit)
10796 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10797 else
10798 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10799 }
10800 fixp->fx_subsy = 0;
23df1078 10801 }
252b5132 10802 }
02a86693
L		 10803#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10804 else if (!object_64bit)
10805 {
10806 if (fixp->fx_r_type == BFD_RELOC_386_GOT32
10807 && fixp->fx_tcbit2)
10808 fixp->fx_r_type = BFD_RELOC_386_GOT32X;
10809 }
10810#endif
252b5132
RH		 10811}
10812
252b5132 10813arelent *
7016a5d5 10814tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 10815{
10816 arelent *rel;
10817 bfd_reloc_code_real_type code;
10818
10819 switch (fixp->fx_r_type)
10820 {
8ce3d284 10821#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8fd4256d
L		 10822 case BFD_RELOC_SIZE32:
10823 case BFD_RELOC_SIZE64:
10824 if (S_IS_DEFINED (fixp->fx_addsy)
10825 && !S_IS_EXTERNAL (fixp->fx_addsy))
10826 {
10827 /* Resolve size relocation against local symbol to size of
10828 the symbol plus addend. */
10829 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10830 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10831 && !fits_in_unsigned_long (value))
10832 as_bad_where (fixp->fx_file, fixp->fx_line,
10833 _("symbol size computation overflow"));
10834 fixp->fx_addsy = NULL;
10835 fixp->fx_subsy = NULL;
10836 md_apply_fix (fixp, (valueT *) &value, NULL);
10837 return NULL;
10838 }
8ce3d284 10839#endif
1a0670f3 10840 /* Fall through. */
8fd4256d 10841
3e73aa7c
JH		 10842 case BFD_RELOC_X86_64_PLT32:
10843 case BFD_RELOC_X86_64_GOT32:
10844 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 10845 case BFD_RELOC_X86_64_GOTPCRELX:
10846 case BFD_RELOC_X86_64_REX_GOTPCRELX:
252b5132
RH		 10847 case BFD_RELOC_386_PLT32:
10848 case BFD_RELOC_386_GOT32:
02a86693 10849 case BFD_RELOC_386_GOT32X:
252b5132
RH		 10850 case BFD_RELOC_386_GOTOFF:
10851 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 10852 case BFD_RELOC_386_TLS_GD:
10853 case BFD_RELOC_386_TLS_LDM:
10854 case BFD_RELOC_386_TLS_LDO_32:
10855 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 10856 case BFD_RELOC_386_TLS_IE:
10857 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 10858 case BFD_RELOC_386_TLS_LE_32:
10859 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 10860 case BFD_RELOC_386_TLS_GOTDESC:
10861 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 10862 case BFD_RELOC_X86_64_TLSGD:
10863 case BFD_RELOC_X86_64_TLSLD:
10864 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 10865 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 10866 case BFD_RELOC_X86_64_GOTTPOFF:
10867 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 10868 case BFD_RELOC_X86_64_TPOFF64:
10869 case BFD_RELOC_X86_64_GOTOFF64:
10870 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 10871 case BFD_RELOC_X86_64_GOT64:
10872 case BFD_RELOC_X86_64_GOTPCREL64:
10873 case BFD_RELOC_X86_64_GOTPC64:
10874 case BFD_RELOC_X86_64_GOTPLT64:
10875 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 10876 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10877 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 10878 case BFD_RELOC_RVA:
10879 case BFD_RELOC_VTABLE_ENTRY:
10880 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 10881#ifdef TE_PE
10882 case BFD_RELOC_32_SECREL:
10883#endif
252b5132
RH		 10884 code = fixp->fx_r_type;
10885 break;
dbbaec26
L		 10886 case BFD_RELOC_X86_64_32S:
10887 if (!fixp->fx_pcrel)
10888 {
10889 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10890 code = fixp->fx_r_type;
10891 break;
10892 }
1a0670f3 10893 /* Fall through. */
252b5132 10894 default:
93382f6d 10895 if (fixp->fx_pcrel)
252b5132 10896 {
93382f6d
AM		 10897 switch (fixp->fx_size)
10898 {
10899 default:
b091f402
AM		 10900 as_bad_where (fixp->fx_file, fixp->fx_line,
10901 _("can not do %d byte pc-relative relocation"),
10902 fixp->fx_size);
93382f6d
AM		 10903 code = BFD_RELOC_32_PCREL;
10904 break;
10905 case 1: code = BFD_RELOC_8_PCREL; break;
10906 case 2: code = BFD_RELOC_16_PCREL; break;
d258b828 10907 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 10908#ifdef BFD64
10909 case 8: code = BFD_RELOC_64_PCREL; break;
10910#endif
93382f6d
AM		 10911 }
10912 }
10913 else
10914 {
10915 switch (fixp->fx_size)
10916 {
10917 default:
b091f402
AM		 10918 as_bad_where (fixp->fx_file, fixp->fx_line,
10919 _("can not do %d byte relocation"),
10920 fixp->fx_size);
93382f6d
AM		 10921 code = BFD_RELOC_32;
10922 break;
10923 case 1: code = BFD_RELOC_8; break;
10924 case 2: code = BFD_RELOC_16; break;
10925 case 4: code = BFD_RELOC_32; break;
937149dd 10926#ifdef BFD64
3e73aa7c 10927 case 8: code = BFD_RELOC_64; break;
937149dd 10928#endif
93382f6d 10929 }
252b5132
RH		 10930 }
10931 break;
10932 }
252b5132 10933
d182319b
JB		 10934 if ((code == BFD_RELOC_32
10935 || code == BFD_RELOC_32_PCREL
10936 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 10937 && GOT_symbol
10938 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 10939 {
4fa24527 10940 if (!object_64bit)
d6ab8113
JB		 10941 code = BFD_RELOC_386_GOTPC;
10942 else
10943 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 10944 }
7b81dfbb
AJ		 10945 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10946 && GOT_symbol
10947 && fixp->fx_addsy == GOT_symbol)
10948 {
10949 code = BFD_RELOC_X86_64_GOTPC64;
10950 }
252b5132 10951
add39d23
TS		 10952 rel = XNEW (arelent);
10953 rel->sym_ptr_ptr = XNEW (asymbol *);
49309057 10954 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 10955
10956 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 10957
3e73aa7c
JH		 10958 if (!use_rela_relocations)
10959 {
10960 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10961 vtable entry to be used in the relocation's section offset. */
10962 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10963 rel->address = fixp->fx_offset;
fbeb56a4
DK		 10964#if defined (OBJ_COFF) && defined (TE_PE)
10965 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10966 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10967 else
10968#endif
c6682705 10969 rel->addend = 0;
3e73aa7c
JH		 10970 }
10971 /* Use the rela in 64bit mode. */
252b5132 10972 else
3e73aa7c 10973 {
862be3fb
L		 10974 if (disallow_64bit_reloc)
10975 switch (code)
10976 {
862be3fb
L		 10977 case BFD_RELOC_X86_64_DTPOFF64:
10978 case BFD_RELOC_X86_64_TPOFF64:
10979 case BFD_RELOC_64_PCREL:
10980 case BFD_RELOC_X86_64_GOTOFF64:
10981 case BFD_RELOC_X86_64_GOT64:
10982 case BFD_RELOC_X86_64_GOTPCREL64:
10983 case BFD_RELOC_X86_64_GOTPC64:
10984 case BFD_RELOC_X86_64_GOTPLT64:
10985 case BFD_RELOC_X86_64_PLTOFF64:
10986 as_bad_where (fixp->fx_file, fixp->fx_line,
10987 _("cannot represent relocation type %s in x32 mode"),
10988 bfd_get_reloc_code_name (code));
10989 break;
10990 default:
10991 break;
10992 }
10993
062cd5e7
AS		 10994 if (!fixp->fx_pcrel)
10995 rel->addend = fixp->fx_offset;
10996 else
10997 switch (code)
10998 {
10999 case BFD_RELOC_X86_64_PLT32:
11000 case BFD_RELOC_X86_64_GOT32:
11001 case BFD_RELOC_X86_64_GOTPCREL:
56ceb5b5
L		 11002 case BFD_RELOC_X86_64_GOTPCRELX:
11003 case BFD_RELOC_X86_64_REX_GOTPCRELX:
bffbf940
JJ		 11004 case BFD_RELOC_X86_64_TLSGD:
11005 case BFD_RELOC_X86_64_TLSLD:
11006 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 11007 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
11008 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 11009 rel->addend = fixp->fx_offset - fixp->fx_size;
11010 break;
11011 default:
11012 rel->addend = (section->vma
11013 - fixp->fx_size
11014 + fixp->fx_addnumber
11015 + md_pcrel_from (fixp));
11016 break;
11017 }
3e73aa7c
JH		 11018 }
11019
252b5132
RH		 11020 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
11021 if (rel->howto == NULL)
11022 {
11023 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 11024 _("cannot represent relocation type %s"),
252b5132
RH		 11025 bfd_get_reloc_code_name (code));
11026 /* Set howto to a garbage value so that we can keep going. */
11027 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
9c2799c2 11028 gas_assert (rel->howto != NULL);
252b5132
RH		 11029 }
11030
11031 return rel;
11032}
11033
ee86248c 11034#include "tc-i386-intel.c"
54cfded0 11035
a60de03c
JB		 11036void
11037tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 11038{
a60de03c
JB		 11039 int saved_naked_reg;
11040 char saved_register_dot;
54cfded0 11041
a60de03c
JB		 11042 saved_naked_reg = allow_naked_reg;
11043 allow_naked_reg = 1;
11044 saved_register_dot = register_chars['.'];
11045 register_chars['.'] = '.';
11046 allow_pseudo_reg = 1;
11047 expression_and_evaluate (exp);
11048 allow_pseudo_reg = 0;
11049 register_chars['.'] = saved_register_dot;
11050 allow_naked_reg = saved_naked_reg;
11051
e96d56a1 11052 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 11053 {
a60de03c
JB		 11054 if ((addressT) exp->X_add_number < i386_regtab_size)
11055 {
11056 exp->X_op = O_constant;
11057 exp->X_add_number = i386_regtab[exp->X_add_number]
11058 .dw2_regnum[flag_code >> 1];
11059 }
11060 else
11061 exp->X_op = O_illegal;
54cfded0 11062 }
54cfded0
AM		 11063}
11064
11065void
11066tc_x86_frame_initial_instructions (void)
11067{
a60de03c
JB		 11068 static unsigned int sp_regno[2];
11069
11070 if (!sp_regno[flag_code >> 1])
11071 {
11072 char *saved_input = input_line_pointer;
11073 char sp[][4] = {"esp", "rsp"};
11074 expressionS exp;
a4447b93 11075
a60de03c
JB		 11076 input_line_pointer = sp[flag_code >> 1];
11077 tc_x86_parse_to_dw2regnum (&exp);
9c2799c2 11078 gas_assert (exp.X_op == O_constant);
a60de03c
JB		 11079 sp_regno[flag_code >> 1] = exp.X_add_number;
11080 input_line_pointer = saved_input;
11081 }
a4447b93 11082
61ff971f
L		 11083 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
11084 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 11085}
d2b2c203 11086
d7921315
L		 11087int
11088x86_dwarf2_addr_size (void)
11089{
11090#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
11091 if (x86_elf_abi == X86_64_X32_ABI)
11092 return 4;
11093#endif
11094 return bfd_arch_bits_per_address (stdoutput) / 8;
11095}
11096
d2b2c203
DJ		 11097int
11098i386_elf_section_type (const char *str, size_t len)
11099{
11100 if (flag_code == CODE_64BIT
11101 && len == sizeof ("unwind") - 1
11102 && strncmp (str, "unwind", 6) == 0)
11103 return SHT_X86_64_UNWIND;
11104
11105 return -1;
11106}
bb41ade5 11107
ad5fec3b
EB		 11108#ifdef TE_SOLARIS
11109void
11110i386_solaris_fix_up_eh_frame (segT sec)
11111{
11112 if (flag_code == CODE_64BIT)
11113 elf_section_type (sec) = SHT_X86_64_UNWIND;
11114}
11115#endif
11116
bb41ade5
AM		 11117#ifdef TE_PE
11118void
11119tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
11120{
91d6fa6a 11121 expressionS exp;
bb41ade5 11122
91d6fa6a
NC		 11123 exp.X_op = O_secrel;
11124 exp.X_add_symbol = symbol;
11125 exp.X_add_number = 0;
11126 emit_expr (&exp, size);
bb41ade5
AM		 11127}
11128#endif
3b22753a
L		 11129
11130#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
11131/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
11132
01e1a5bc 11133bfd_vma
6d4af3c2 11134x86_64_section_letter (int letter, const char **ptr_msg)
3b22753a
L		 11135{
11136 if (flag_code == CODE_64BIT)
11137 {
11138 if (letter == 'l')
11139 return SHF_X86_64_LARGE;
11140
8f3bae45 11141 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 11142 }
3b22753a 11143 else
8f3bae45 11144 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 11145 return -1;
11146}
11147
01e1a5bc 11148bfd_vma
3b22753a
L		 11149x86_64_section_word (char *str, size_t len)
11150{
8620418b 11151 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 11152 return SHF_X86_64_LARGE;
11153
11154 return -1;
11155}
11156
11157static void
11158handle_large_common (int small ATTRIBUTE_UNUSED)
11159{
11160 if (flag_code != CODE_64BIT)
11161 {
11162 s_comm_internal (0, elf_common_parse);
11163 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
11164 }
11165 else
11166 {
11167 static segT lbss_section;
11168 asection *saved_com_section_ptr = elf_com_section_ptr;
11169 asection *saved_bss_section = bss_section;
11170
11171 if (lbss_section == NULL)
11172 {
11173 flagword applicable;
11174 segT seg = now_seg;
11175 subsegT subseg = now_subseg;
11176
11177 /* The .lbss section is for local .largecomm symbols. */
11178 lbss_section = subseg_new (".lbss", 0);
11179 applicable = bfd_applicable_section_flags (stdoutput);
11180 bfd_set_section_flags (stdoutput, lbss_section,
11181 applicable & SEC_ALLOC);
11182 seg_info (lbss_section)->bss = 1;
11183
11184 subseg_set (seg, subseg);
11185 }
11186
11187 elf_com_section_ptr = &_bfd_elf_large_com_section;
11188 bss_section = lbss_section;
11189
11190 s_comm_internal (0, elf_common_parse);
11191
11192 elf_com_section_ptr = saved_com_section_ptr;
11193 bss_section = saved_bss_section;
11194 }
11195}
11196#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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