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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
a2c58332 | 2 | Copyright (C) 1989-2022 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
41fd2579 | 35 | #include <limits.h> |
41fd2579 | 36 | |
c3332e24 | 37 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 38 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
39 | #endif |
40 | ||
29b0f896 AM |
41 | #ifndef DEFAULT_ARCH |
42 | #define DEFAULT_ARCH "i386" | |
246fcdee | 43 | #endif |
252b5132 | 44 | |
edde18a5 AM |
45 | #ifndef INLINE |
46 | #if __GNUC__ >= 2 | |
47 | #define INLINE __inline__ | |
48 | #else | |
49 | #define INLINE | |
50 | #endif | |
51 | #endif | |
52 | ||
6305a203 L |
53 | /* Prefixes will be emitted in the order defined below. |
54 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
55 | instruction, and so must come before any prefixes. | |
56 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 57 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
58 | #define WAIT_PREFIX 0 |
59 | #define SEG_PREFIX 1 | |
60 | #define ADDR_PREFIX 2 | |
61 | #define DATA_PREFIX 3 | |
c32fa91d | 62 | #define REP_PREFIX 4 |
42164a71 | 63 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 64 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 65 | #define LOCK_PREFIX 5 |
4e9ac44a L |
66 | #define REX_PREFIX 6 /* must come last. */ |
67 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
68 | |
69 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
70 | #define REGISTER_PREFIX '%' | |
71 | #define IMMEDIATE_PREFIX '$' | |
72 | #define ABSOLUTE_PREFIX '*' | |
73 | ||
74 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
75 | memory operand size in Intel syntax. */ | |
76 | #define WORD_MNEM_SUFFIX 'w' | |
77 | #define BYTE_MNEM_SUFFIX 'b' | |
78 | #define SHORT_MNEM_SUFFIX 's' | |
79 | #define LONG_MNEM_SUFFIX 'l' | |
80 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
81 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
82 | in instructions. */ | |
83 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
84 | ||
85 | #define END_OF_INSN '\0' | |
86 | ||
79dec6b7 JB |
87 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
88 | #define commutative staticrounding | |
89 | ||
6305a203 L |
90 | /* |
91 | 'templates' is for grouping together 'template' structures for opcodes | |
92 | of the same name. This is only used for storing the insns in the grand | |
93 | ole hash table of insns. | |
94 | The templates themselves start at START and range up to (but not including) | |
95 | END. | |
96 | */ | |
97 | typedef struct | |
98 | { | |
d3ce72d0 NC |
99 | const insn_template *start; |
100 | const insn_template *end; | |
6305a203 L |
101 | } |
102 | templates; | |
103 | ||
104 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
105 | typedef struct | |
106 | { | |
107 | unsigned int regmem; /* codes register or memory operand */ | |
108 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
109 | unsigned int mode; /* how to interpret regmem & reg */ | |
110 | } | |
111 | modrm_byte; | |
112 | ||
113 | /* x86-64 extension prefix. */ | |
114 | typedef int rex_byte; | |
115 | ||
6305a203 L |
116 | /* 386 opcode byte to code indirect addressing. */ |
117 | typedef struct | |
118 | { | |
119 | unsigned base; | |
120 | unsigned index; | |
121 | unsigned scale; | |
122 | } | |
123 | sib_byte; | |
124 | ||
6305a203 L |
125 | /* x86 arch names, types and features */ |
126 | typedef struct | |
127 | { | |
128 | const char *name; /* arch name */ | |
6ceeed25 JB |
129 | unsigned int len:8; /* arch string length */ |
130 | bool skip:1; /* show_arch should skip this. */ | |
6305a203 | 131 | enum processor_type type; /* arch type */ |
ae89daec JB |
132 | i386_cpu_flags enable; /* cpu feature enable flags */ |
133 | i386_cpu_flags disable; /* cpu feature disable flags */ | |
6305a203 L |
134 | } |
135 | arch_entry; | |
136 | ||
78f12dd3 | 137 | static void update_code_flag (int, int); |
e3bb37b5 L |
138 | static void set_code_flag (int); |
139 | static void set_16bit_gcc_code_flag (int); | |
140 | static void set_intel_syntax (int); | |
1efbbeb4 | 141 | static void set_intel_mnemonic (int); |
db51cc60 | 142 | static void set_allow_index_reg (int); |
7bab8ab5 | 143 | static void set_check (int); |
e3bb37b5 | 144 | static void set_cpu_arch (int); |
6482c264 | 145 | #ifdef TE_PE |
e3bb37b5 | 146 | static void pe_directive_secrel (int); |
145667f8 | 147 | static void pe_directive_secidx (int); |
6482c264 | 148 | #endif |
e3bb37b5 L |
149 | static void signed_cons (int); |
150 | static char *output_invalid (int c); | |
ee86248c JB |
151 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
152 | const char *); | |
153 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
154 | const char *); | |
a7619375 | 155 | static int i386_att_operand (char *); |
e3bb37b5 | 156 | static int i386_intel_operand (char *, int); |
ee86248c JB |
157 | static int i386_intel_simplify (expressionS *); |
158 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
159 | static const reg_entry *parse_register (char *, char **); |
160 | static char *parse_insn (char *, char *); | |
161 | static char *parse_operands (char *, const char *); | |
162 | static void swap_operands (void); | |
783c187b | 163 | static void swap_2_operands (unsigned int, unsigned int); |
48bcea9f | 164 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
165 | static void optimize_imm (void); |
166 | static void optimize_disp (void); | |
83b16ac6 | 167 | static const insn_template *match_template (char); |
e3bb37b5 L |
168 | static int check_string (void); |
169 | static int process_suffix (void); | |
170 | static int check_byte_reg (void); | |
171 | static int check_long_reg (void); | |
172 | static int check_qword_reg (void); | |
173 | static int check_word_reg (void); | |
174 | static int finalize_imm (void); | |
175 | static int process_operands (void); | |
5e042380 | 176 | static const reg_entry *build_modrm_byte (void); |
e3bb37b5 L |
177 | static void output_insn (void); |
178 | static void output_imm (fragS *, offsetT); | |
179 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 180 | #ifndef I386COFF |
e3bb37b5 | 181 | static void s_bss (int); |
252b5132 | 182 | #endif |
17d4e2a2 L |
183 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
184 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
185 | |
186 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
187 | static unsigned int x86_isa_1_used; | |
188 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
189 | static unsigned int x86_feature_2_used; | |
190 | /* Generate x86 used ISA and feature properties. */ | |
191 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 192 | #endif |
252b5132 | 193 | |
a847613f | 194 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 195 | |
8a6fb3f9 JB |
196 | /* parse_register() returns this when a register alias cannot be used. */ |
197 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
198 | { Dw2Inval, Dw2Inval } }; | |
199 | ||
34684862 | 200 | static const reg_entry *reg_eax; |
5e042380 JB |
201 | static const reg_entry *reg_ds; |
202 | static const reg_entry *reg_es; | |
203 | static const reg_entry *reg_ss; | |
6288d05f | 204 | static const reg_entry *reg_st0; |
6225c532 JB |
205 | static const reg_entry *reg_k0; |
206 | ||
c0f3af97 L |
207 | /* VEX prefix. */ |
208 | typedef struct | |
209 | { | |
43234a1e L |
210 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
211 | unsigned char bytes[4]; | |
c0f3af97 L |
212 | unsigned int length; |
213 | /* Destination or source register specifier. */ | |
214 | const reg_entry *register_specifier; | |
215 | } vex_prefix; | |
216 | ||
252b5132 | 217 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 218 | i386_insn. */ |
252b5132 | 219 | |
520dc8e8 AM |
220 | union i386_op |
221 | { | |
222 | expressionS *disps; | |
223 | expressionS *imms; | |
224 | const reg_entry *regs; | |
225 | }; | |
226 | ||
a65babc9 L |
227 | enum i386_error |
228 | { | |
b4d65f2d | 229 | no_error, /* Must be first. */ |
86e026a4 | 230 | operand_size_mismatch, |
a65babc9 L |
231 | operand_type_mismatch, |
232 | register_type_mismatch, | |
233 | number_of_operands_mismatch, | |
234 | invalid_instruction_suffix, | |
235 | bad_imm4, | |
a65babc9 L |
236 | unsupported_with_intel_mnemonic, |
237 | unsupported_syntax, | |
6c30d220 | 238 | unsupported, |
260cd341 | 239 | invalid_sib_address, |
6c30d220 | 240 | invalid_vsib_address, |
7bab8ab5 | 241 | invalid_vector_register_set, |
260cd341 | 242 | invalid_tmm_register_set, |
0cc78721 | 243 | invalid_dest_and_src_register_set, |
43234a1e L |
244 | unsupported_vector_index_register, |
245 | unsupported_broadcast, | |
43234a1e L |
246 | broadcast_needed, |
247 | unsupported_masking, | |
248 | mask_not_on_destination, | |
249 | no_default_mask, | |
250 | unsupported_rc_sae, | |
43234a1e | 251 | invalid_register_operand, |
a65babc9 L |
252 | }; |
253 | ||
252b5132 RH |
254 | struct _i386_insn |
255 | { | |
47926f60 | 256 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 257 | insn_template tm; |
252b5132 | 258 | |
7d5e4556 L |
259 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
260 | or qword, if given. */ | |
252b5132 RH |
261 | char suffix; |
262 | ||
9a182d04 JB |
263 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
264 | unsigned char opcode_length; | |
265 | ||
47926f60 | 266 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
267 | unsigned int operands; |
268 | ||
269 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
270 | of given register, displacement, memory operands and immediate | |
47926f60 | 271 | operands. */ |
252b5132 RH |
272 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
273 | ||
274 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 275 | use OP[i] for the corresponding operand. */ |
40fb9820 | 276 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 277 | |
520dc8e8 AM |
278 | /* Displacement expression, immediate expression, or register for each |
279 | operand. */ | |
280 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 281 | |
3e73aa7c JH |
282 | /* Flags for operands. */ |
283 | unsigned int flags[MAX_OPERANDS]; | |
284 | #define Operand_PCrel 1 | |
c48dadc9 | 285 | #define Operand_Mem 2 |
3e73aa7c | 286 | |
252b5132 | 287 | /* Relocation type for operand */ |
f86103b7 | 288 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 289 | |
252b5132 RH |
290 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
291 | the base index byte below. */ | |
292 | const reg_entry *base_reg; | |
293 | const reg_entry *index_reg; | |
294 | unsigned int log2_scale_factor; | |
295 | ||
296 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 297 | explicit segment overrides are given. */ |
5e042380 | 298 | const reg_entry *seg[2]; |
252b5132 | 299 | |
8325cc63 JB |
300 | /* Copied first memory operand string, for re-checking. */ |
301 | char *memop1_string; | |
302 | ||
252b5132 RH |
303 | /* PREFIX holds all the given prefix opcodes (usually null). |
304 | PREFIXES is the number of prefix opcodes. */ | |
305 | unsigned int prefixes; | |
306 | unsigned char prefix[MAX_PREFIXES]; | |
307 | ||
50128d0c | 308 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 309 | bool short_form; |
50128d0c | 310 | |
6f2f06be | 311 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 312 | bool jumpabsolute; |
6f2f06be | 313 | |
921eafea L |
314 | /* Extended states. */ |
315 | enum | |
316 | { | |
317 | /* Use MMX state. */ | |
318 | xstate_mmx = 1 << 0, | |
319 | /* Use XMM state. */ | |
320 | xstate_xmm = 1 << 1, | |
321 | /* Use YMM state. */ | |
322 | xstate_ymm = 1 << 2 | xstate_xmm, | |
323 | /* Use ZMM state. */ | |
324 | xstate_zmm = 1 << 3 | xstate_ymm, | |
325 | /* Use TMM state. */ | |
32930e4e L |
326 | xstate_tmm = 1 << 4, |
327 | /* Use MASK state. */ | |
328 | xstate_mask = 1 << 5 | |
921eafea | 329 | } xstate; |
260cd341 | 330 | |
e379e5f3 | 331 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 332 | bool has_gotpc_tls_reloc; |
e379e5f3 | 333 | |
252b5132 | 334 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 335 | addressing modes of this insn are encoded. */ |
252b5132 | 336 | modrm_byte rm; |
3e73aa7c | 337 | rex_byte rex; |
43234a1e | 338 | rex_byte vrex; |
252b5132 | 339 | sib_byte sib; |
c0f3af97 | 340 | vex_prefix vex; |
b6169b20 | 341 | |
6225c532 JB |
342 | /* Masking attributes. |
343 | ||
344 | The struct describes masking, applied to OPERAND in the instruction. | |
345 | REG is a pointer to the corresponding mask register. ZEROING tells | |
346 | whether merging or zeroing mask is used. */ | |
347 | struct Mask_Operation | |
348 | { | |
349 | const reg_entry *reg; | |
350 | unsigned int zeroing; | |
351 | /* The operand where this operation is associated. */ | |
352 | unsigned int operand; | |
353 | } mask; | |
43234a1e L |
354 | |
355 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
356 | struct RC_Operation |
357 | { | |
358 | enum rc_type | |
359 | { | |
360 | rc_none = -1, | |
361 | rne, | |
362 | rd, | |
363 | ru, | |
364 | rz, | |
365 | saeonly | |
366 | } type; | |
7063667e JB |
367 | /* In Intel syntax the operand modifier form is supposed to be used, but |
368 | we continue to accept the immediate forms as well. */ | |
369 | bool modifier; | |
ca5312a2 | 370 | } rounding; |
43234a1e | 371 | |
5273a3cd JB |
372 | /* Broadcasting attributes. |
373 | ||
374 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
375 | expresses the broadcast factor. */ | |
376 | struct Broadcast_Operation | |
377 | { | |
0cc78721 | 378 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */ |
5273a3cd JB |
379 | unsigned int type; |
380 | ||
381 | /* Index of broadcasted operand. */ | |
382 | unsigned int operand; | |
383 | ||
384 | /* Number of bytes to broadcast. */ | |
385 | unsigned int bytes; | |
386 | } broadcast; | |
43234a1e L |
387 | |
388 | /* Compressed disp8*N attribute. */ | |
389 | unsigned int memshift; | |
390 | ||
86fa6981 L |
391 | /* Prefer load or store in encoding. */ |
392 | enum | |
393 | { | |
394 | dir_encoding_default = 0, | |
395 | dir_encoding_load, | |
64c49ab3 JB |
396 | dir_encoding_store, |
397 | dir_encoding_swap | |
86fa6981 | 398 | } dir_encoding; |
891edac4 | 399 | |
41eb8e88 | 400 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
401 | enum |
402 | { | |
403 | disp_encoding_default = 0, | |
404 | disp_encoding_8bit, | |
41eb8e88 | 405 | disp_encoding_16bit, |
a501d77e L |
406 | disp_encoding_32bit |
407 | } disp_encoding; | |
f8a5c266 | 408 | |
6b6b6807 | 409 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 410 | bool rex_encoding; |
6b6b6807 | 411 | |
b6f8c7c4 | 412 | /* Disable instruction size optimization. */ |
5b7c81bd | 413 | bool no_optimize; |
b6f8c7c4 | 414 | |
86fa6981 L |
415 | /* How to encode vector instructions. */ |
416 | enum | |
417 | { | |
418 | vex_encoding_default = 0, | |
42e04b36 | 419 | vex_encoding_vex, |
86fa6981 | 420 | vex_encoding_vex3, |
da4977e0 JB |
421 | vex_encoding_evex, |
422 | vex_encoding_error | |
86fa6981 L |
423 | } vec_encoding; |
424 | ||
d5de92cf L |
425 | /* REP prefix. */ |
426 | const char *rep_prefix; | |
427 | ||
165de32a L |
428 | /* HLE prefix. */ |
429 | const char *hle_prefix; | |
42164a71 | 430 | |
7e8b059b L |
431 | /* Have BND prefix. */ |
432 | const char *bnd_prefix; | |
433 | ||
04ef582a L |
434 | /* Have NOTRACK prefix. */ |
435 | const char *notrack_prefix; | |
436 | ||
891edac4 | 437 | /* Error message. */ |
a65babc9 | 438 | enum i386_error error; |
252b5132 RH |
439 | }; |
440 | ||
441 | typedef struct _i386_insn i386_insn; | |
442 | ||
43234a1e L |
443 | /* Link RC type with corresponding string, that'll be looked for in |
444 | asm. */ | |
445 | struct RC_name | |
446 | { | |
447 | enum rc_type type; | |
448 | const char *name; | |
449 | unsigned int len; | |
450 | }; | |
451 | ||
452 | static const struct RC_name RC_NamesTable[] = | |
453 | { | |
454 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
455 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
456 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
457 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
458 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
459 | }; | |
460 | ||
252b5132 RH |
461 | /* List of chars besides those in app.c:symbol_chars that can start an |
462 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 463 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 464 | #ifdef LEX_AT |
32137342 NC |
465 | "@" |
466 | #endif | |
467 | #ifdef LEX_QM | |
468 | "?" | |
252b5132 | 469 | #endif |
32137342 | 470 | ; |
252b5132 | 471 | |
b3983e5f JB |
472 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
473 | && !defined (TE_GNU) \ | |
474 | && !defined (TE_LINUX) \ | |
d85e70a3 | 475 | && !defined (TE_Haiku) \ |
b3983e5f JB |
476 | && !defined (TE_FreeBSD) \ |
477 | && !defined (TE_DragonFly) \ | |
478 | && !defined (TE_NetBSD)) | |
252b5132 | 479 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
480 | pre-processor is disabled, these aren't very useful. The option |
481 | --divide will remove '/' from this list. */ | |
482 | const char *i386_comment_chars = "#/"; | |
483 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 484 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 485 | |
b3b91714 AM |
486 | #else |
487 | const char *i386_comment_chars = "#"; | |
488 | #define PREFIX_SEPARATOR '/' | |
489 | #endif | |
490 | ||
252b5132 RH |
491 | /* This array holds the chars that only start a comment at the beginning of |
492 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
493 | .line and .file directives will appear in the pre-processed output. |
494 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 495 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
496 | #NO_APP at the beginning of its output. |
497 | Also note that comments started like this one will always work if | |
252b5132 | 498 | '/' isn't otherwise defined. */ |
b3b91714 | 499 | const char line_comment_chars[] = "#/"; |
252b5132 | 500 | |
63a0b638 | 501 | const char line_separator_chars[] = ";"; |
252b5132 | 502 | |
ce8a8b2f AM |
503 | /* Chars that can be used to separate mant from exp in floating point |
504 | nums. */ | |
252b5132 RH |
505 | const char EXP_CHARS[] = "eE"; |
506 | ||
ce8a8b2f AM |
507 | /* Chars that mean this number is a floating point constant |
508 | As in 0f12.456 | |
509 | or 0d1.2345e12. */ | |
de133cf9 | 510 | const char FLT_CHARS[] = "fFdDxXhHbB"; |
252b5132 | 511 | |
ce8a8b2f | 512 | /* Tables for lexical analysis. */ |
252b5132 RH |
513 | static char mnemonic_chars[256]; |
514 | static char register_chars[256]; | |
515 | static char operand_chars[256]; | |
516 | static char identifier_chars[256]; | |
252b5132 | 517 | |
ce8a8b2f | 518 | /* Lexical macros. */ |
252b5132 RH |
519 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
520 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
521 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
522 | #define is_space_char(x) ((x) == ' ') | |
523 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
252b5132 | 524 | |
0234cb7c | 525 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
526 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
527 | ||
528 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
529 | effect this we maintain a stack of saved characters that we've smashed | |
530 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 531 | assembler instruction). */ |
252b5132 | 532 | static char save_stack[32]; |
ce8a8b2f | 533 | static char *save_stack_p; |
252b5132 RH |
534 | #define END_STRING_AND_SAVE(s) \ |
535 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
536 | #define RESTORE_END_STRING(s) \ | |
537 | do { *(s) = *--save_stack_p; } while (0) | |
538 | ||
47926f60 | 539 | /* The instruction we're assembling. */ |
252b5132 RH |
540 | static i386_insn i; |
541 | ||
542 | /* Possible templates for current insn. */ | |
543 | static const templates *current_templates; | |
544 | ||
31b2323c L |
545 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
546 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
547 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 548 | |
47926f60 | 549 | /* Current operand we are working on. */ |
ee86248c | 550 | static int this_operand = -1; |
252b5132 | 551 | |
3e73aa7c JH |
552 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
553 | these. */ | |
554 | ||
555 | enum flag_code { | |
556 | CODE_32BIT, | |
557 | CODE_16BIT, | |
558 | CODE_64BIT }; | |
559 | ||
560 | static enum flag_code flag_code; | |
4fa24527 | 561 | static unsigned int object_64bit; |
862be3fb | 562 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 563 | static int use_rela_relocations = 0; |
e379e5f3 L |
564 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
565 | static const char *tls_get_addr; | |
3e73aa7c | 566 | |
7af8ed2d NC |
567 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
568 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
569 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
570 | ||
351f65ca L |
571 | /* The ELF ABI to use. */ |
572 | enum x86_elf_abi | |
573 | { | |
574 | I386_ABI, | |
7f56bc95 L |
575 | X86_64_ABI, |
576 | X86_64_X32_ABI | |
351f65ca L |
577 | }; |
578 | ||
579 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 580 | #endif |
351f65ca | 581 | |
167ad85b TG |
582 | #if defined (TE_PE) || defined (TE_PEP) |
583 | /* Use big object file format. */ | |
584 | static int use_big_obj = 0; | |
585 | #endif | |
586 | ||
8dcea932 L |
587 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
588 | /* 1 if generating code for a shared library. */ | |
589 | static int shared = 0; | |
590 | #endif | |
591 | ||
47926f60 KH |
592 | /* 1 for intel syntax, |
593 | 0 if att syntax. */ | |
594 | static int intel_syntax = 0; | |
252b5132 | 595 | |
4b5aaf5f L |
596 | static enum x86_64_isa |
597 | { | |
598 | amd64 = 1, /* AMD64 ISA. */ | |
599 | intel64 /* Intel64 ISA. */ | |
600 | } isa64; | |
e89c5eaa | 601 | |
1efbbeb4 L |
602 | /* 1 for intel mnemonic, |
603 | 0 if att mnemonic. */ | |
604 | static int intel_mnemonic = !SYSV386_COMPAT; | |
605 | ||
a60de03c JB |
606 | /* 1 if pseudo registers are permitted. */ |
607 | static int allow_pseudo_reg = 0; | |
608 | ||
47926f60 KH |
609 | /* 1 if register prefix % not required. */ |
610 | static int allow_naked_reg = 0; | |
252b5132 | 611 | |
33eaf5de | 612 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
613 | instructions supporting it, even if this prefix wasn't specified |
614 | explicitly. */ | |
615 | static int add_bnd_prefix = 0; | |
616 | ||
ba104c83 | 617 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
618 | static int allow_index_reg = 0; |
619 | ||
d022bddd IT |
620 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
621 | specified explicitly. */ | |
622 | static int omit_lock_prefix = 0; | |
623 | ||
e4e00185 AS |
624 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
625 | "lock addl $0, (%{re}sp)". */ | |
626 | static int avoid_fence = 0; | |
627 | ||
ae531041 L |
628 | /* 1 if lfence should be inserted after every load. */ |
629 | static int lfence_after_load = 0; | |
630 | ||
631 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
632 | static enum lfence_before_indirect_branch_kind | |
633 | { | |
634 | lfence_branch_none = 0, | |
635 | lfence_branch_register, | |
636 | lfence_branch_memory, | |
637 | lfence_branch_all | |
638 | } | |
639 | lfence_before_indirect_branch; | |
640 | ||
641 | /* Non-zero if lfence should be inserted before ret. */ | |
642 | static enum lfence_before_ret_kind | |
643 | { | |
644 | lfence_before_ret_none = 0, | |
645 | lfence_before_ret_not, | |
a09f656b | 646 | lfence_before_ret_or, |
647 | lfence_before_ret_shl | |
ae531041 L |
648 | } |
649 | lfence_before_ret; | |
650 | ||
651 | /* Types of previous instruction is .byte or prefix. */ | |
e379e5f3 L |
652 | static struct |
653 | { | |
654 | segT seg; | |
655 | const char *file; | |
656 | const char *name; | |
657 | unsigned int line; | |
658 | enum last_insn_kind | |
659 | { | |
660 | last_insn_other = 0, | |
661 | last_insn_directive, | |
662 | last_insn_prefix | |
663 | } kind; | |
664 | } last_insn; | |
665 | ||
0cb4071e L |
666 | /* 1 if the assembler should generate relax relocations. */ |
667 | ||
668 | static int generate_relax_relocations | |
669 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
670 | ||
7bab8ab5 | 671 | static enum check_kind |
daf50ae7 | 672 | { |
7bab8ab5 JB |
673 | check_none = 0, |
674 | check_warning, | |
675 | check_error | |
daf50ae7 | 676 | } |
7bab8ab5 | 677 | sse_check, operand_check = check_warning; |
daf50ae7 | 678 | |
e379e5f3 L |
679 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
680 | static int align_branch_power = 0; | |
681 | ||
682 | /* Types of branches to align. */ | |
683 | enum align_branch_kind | |
684 | { | |
685 | align_branch_none = 0, | |
686 | align_branch_jcc = 1, | |
687 | align_branch_fused = 2, | |
688 | align_branch_jmp = 3, | |
689 | align_branch_call = 4, | |
690 | align_branch_indirect = 5, | |
691 | align_branch_ret = 6 | |
692 | }; | |
693 | ||
694 | /* Type bits of branches to align. */ | |
695 | enum align_branch_bit | |
696 | { | |
697 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
698 | align_branch_fused_bit = 1 << align_branch_fused, | |
699 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
700 | align_branch_call_bit = 1 << align_branch_call, | |
701 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
702 | align_branch_ret_bit = 1 << align_branch_ret | |
703 | }; | |
704 | ||
705 | static unsigned int align_branch = (align_branch_jcc_bit | |
706 | | align_branch_fused_bit | |
707 | | align_branch_jmp_bit); | |
708 | ||
79d72f45 HL |
709 | /* Types of condition jump used by macro-fusion. */ |
710 | enum mf_jcc_kind | |
711 | { | |
712 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
713 | mf_jcc_jc, /* base opcode 0x72 */ | |
714 | mf_jcc_je, /* base opcode 0x74 */ | |
715 | mf_jcc_jna, /* base opcode 0x76 */ | |
716 | mf_jcc_js, /* base opcode 0x78 */ | |
717 | mf_jcc_jp, /* base opcode 0x7a */ | |
718 | mf_jcc_jl, /* base opcode 0x7c */ | |
719 | mf_jcc_jle, /* base opcode 0x7e */ | |
720 | }; | |
721 | ||
722 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
723 | enum mf_cmp_kind | |
724 | { | |
725 | mf_cmp_test_and, /* test/cmp */ | |
726 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
727 | mf_cmp_incdec /* inc/dec */ | |
728 | }; | |
729 | ||
e379e5f3 L |
730 | /* The maximum padding size for fused jcc. CMP like instruction can |
731 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
732 | prefixes. */ | |
733 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
734 | ||
735 | /* The maximum number of prefixes added for an instruction. */ | |
736 | static unsigned int align_branch_prefix_size = 5; | |
737 | ||
b6f8c7c4 L |
738 | /* Optimization: |
739 | 1. Clear the REX_W bit with register operand if possible. | |
740 | 2. Above plus use 128bit vector instruction to clear the full vector | |
741 | register. | |
742 | */ | |
743 | static int optimize = 0; | |
744 | ||
745 | /* Optimization: | |
746 | 1. Clear the REX_W bit with register operand if possible. | |
747 | 2. Above plus use 128bit vector instruction to clear the full vector | |
748 | register. | |
749 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
750 | "testb $imm7,%r8". | |
751 | */ | |
752 | static int optimize_for_space = 0; | |
753 | ||
2ca3ace5 L |
754 | /* Register prefix used for error message. */ |
755 | static const char *register_prefix = "%"; | |
756 | ||
47926f60 KH |
757 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
758 | leave, push, and pop instructions so that gcc has the same stack | |
759 | frame as in 32 bit mode. */ | |
760 | static char stackop_size = '\0'; | |
eecb386c | 761 | |
12b55ccc L |
762 | /* Non-zero to optimize code alignment. */ |
763 | int optimize_align_code = 1; | |
764 | ||
47926f60 KH |
765 | /* Non-zero to quieten some warnings. */ |
766 | static int quiet_warnings = 0; | |
a38cf1db | 767 | |
d59a54c2 JB |
768 | /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */ |
769 | static bool pre_386_16bit_warned; | |
770 | ||
47926f60 KH |
771 | /* CPU name. */ |
772 | static const char *cpu_arch_name = NULL; | |
6305a203 | 773 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 774 | |
47926f60 | 775 | /* CPU feature flags. */ |
40fb9820 L |
776 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
777 | ||
ccc9c027 L |
778 | /* If we have selected a cpu we are generating instructions for. */ |
779 | static int cpu_arch_tune_set = 0; | |
780 | ||
9103f4f4 | 781 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 782 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
783 | |
784 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 785 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 786 | |
ccc9c027 | 787 | /* CPU instruction set architecture used. */ |
fbf3f584 | 788 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 789 | |
9103f4f4 | 790 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 791 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 792 | |
fddf5b5b AM |
793 | /* If set, conditional jumps are not automatically promoted to handle |
794 | larger than a byte offset. */ | |
f68697e8 | 795 | static bool no_cond_jump_promotion = false; |
fddf5b5b | 796 | |
c0f3af97 L |
797 | /* Encode SSE instructions with VEX prefix. */ |
798 | static unsigned int sse2avx; | |
799 | ||
c8480b58 L |
800 | /* Encode aligned vector move as unaligned vector move. */ |
801 | static unsigned int use_unaligned_vector_move; | |
802 | ||
539f890d L |
803 | /* Encode scalar AVX instructions with specific vector length. */ |
804 | static enum | |
805 | { | |
806 | vex128 = 0, | |
807 | vex256 | |
808 | } avxscalar; | |
809 | ||
03751133 L |
810 | /* Encode VEX WIG instructions with specific vex.w. */ |
811 | static enum | |
812 | { | |
813 | vexw0 = 0, | |
814 | vexw1 | |
815 | } vexwig; | |
816 | ||
43234a1e L |
817 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
818 | static enum | |
819 | { | |
820 | evexl128 = 0, | |
821 | evexl256, | |
822 | evexl512 | |
823 | } evexlig; | |
824 | ||
825 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
826 | static enum | |
827 | { | |
828 | evexw0 = 0, | |
829 | evexw1 | |
830 | } evexwig; | |
831 | ||
d3d3c6db IT |
832 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
833 | static enum rc_type evexrcig = rne; | |
834 | ||
29b0f896 | 835 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 836 | static symbolS *GOT_symbol; |
29b0f896 | 837 | |
a4447b93 RH |
838 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
839 | unsigned int x86_dwarf2_return_column; | |
840 | ||
841 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
842 | int x86_cie_data_alignment; | |
843 | ||
252b5132 | 844 | /* Interface to relax_segment. |
fddf5b5b AM |
845 | There are 3 major relax states for 386 jump insns because the |
846 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
847 | figuring out what sort of jump to choose to reach a given label. |
848 | ||
849 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
850 | branches which are handled by md_estimate_size_before_relax() and | |
851 | i386_generic_table_relax_frag(). */ | |
252b5132 | 852 | |
47926f60 | 853 | /* Types. */ |
93c2a809 AM |
854 | #define UNCOND_JUMP 0 |
855 | #define COND_JUMP 1 | |
856 | #define COND_JUMP86 2 | |
e379e5f3 L |
857 | #define BRANCH_PADDING 3 |
858 | #define BRANCH_PREFIX 4 | |
859 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 860 | |
47926f60 | 861 | /* Sizes. */ |
252b5132 RH |
862 | #define CODE16 1 |
863 | #define SMALL 0 | |
29b0f896 | 864 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 865 | #define BIG 2 |
29b0f896 | 866 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
867 | |
868 | #ifndef INLINE | |
869 | #ifdef __GNUC__ | |
870 | #define INLINE __inline__ | |
871 | #else | |
872 | #define INLINE | |
873 | #endif | |
874 | #endif | |
875 | ||
fddf5b5b AM |
876 | #define ENCODE_RELAX_STATE(type, size) \ |
877 | ((relax_substateT) (((type) << 2) | (size))) | |
878 | #define TYPE_FROM_RELAX_STATE(s) \ | |
879 | ((s) >> 2) | |
880 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
881 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
882 | |
883 | /* This table is used by relax_frag to promote short jumps to long | |
884 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
885 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
886 | don't allow a short jump in a 32 bit code segment to be promoted to | |
887 | a 16 bit offset jump because it's slower (requires data size | |
888 | prefix), and doesn't work, unless the destination is in the bottom | |
889 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
890 | ||
891 | const relax_typeS md_relax_table[] = | |
892 | { | |
24eab124 AM |
893 | /* The fields are: |
894 | 1) most positive reach of this state, | |
895 | 2) most negative reach of this state, | |
93c2a809 | 896 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 897 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 898 | |
fddf5b5b | 899 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
900 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
901 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
902 | /* dword jmp adds 4 bytes to frag: | |
903 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 904 | {0, 0, 4, 0}, |
93c2a809 AM |
905 | /* word jmp adds 2 byte2 to frag: |
906 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
907 | {0, 0, 2, 0}, |
908 | ||
93c2a809 AM |
909 | /* COND_JUMP states. */ |
910 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
911 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
912 | /* dword conditionals adds 5 bytes to frag: | |
913 | 1 extra opcode byte, 4 displacement bytes. */ | |
914 | {0, 0, 5, 0}, | |
fddf5b5b | 915 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
916 | 1 extra opcode byte, 2 displacement bytes. */ |
917 | {0, 0, 3, 0}, | |
918 | ||
919 | /* COND_JUMP86 states. */ | |
920 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
921 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
922 | /* dword conditionals adds 5 bytes to frag: | |
923 | 1 extra opcode byte, 4 displacement bytes. */ | |
924 | {0, 0, 5, 0}, | |
925 | /* word conditionals add 4 bytes to frag: | |
926 | 1 displacement byte and a 3 byte long branch insn. */ | |
927 | {0, 0, 4, 0} | |
252b5132 RH |
928 | }; |
929 | ||
6ceeed25 | 930 | #define ARCH(n, t, f, s) \ |
ae89daec JB |
931 | { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, CPU_ ## f ## _FLAGS, \ |
932 | CPU_NONE_FLAGS } | |
933 | #define SUBARCH(n, e, d, s) \ | |
934 | { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, CPU_ ## e ## _FLAGS, \ | |
935 | CPU_ ## d ## _FLAGS } | |
6ceeed25 | 936 | |
9103f4f4 L |
937 | static const arch_entry cpu_arch[] = |
938 | { | |
3ce2ebcf JB |
939 | /* Do not replace the first two entries - i386_target_format() and |
940 | set_cpu_arch() rely on them being there in this order. */ | |
6ceeed25 JB |
941 | ARCH (generic32, GENERIC32, GENERIC32, false), |
942 | ARCH (generic64, GENERIC64, GENERIC64, false), | |
943 | ARCH (i8086, UNKNOWN, NONE, false), | |
944 | ARCH (i186, UNKNOWN, I186, false), | |
945 | ARCH (i286, UNKNOWN, I286, false), | |
946 | ARCH (i386, I386, I386, false), | |
947 | ARCH (i486, I486, I486, false), | |
948 | ARCH (i586, PENTIUM, I586, false), | |
949 | ARCH (i686, PENTIUMPRO, I686, false), | |
950 | ARCH (pentium, PENTIUM, I586, false), | |
951 | ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false), | |
952 | ARCH (pentiumii, PENTIUMPRO, P2, false), | |
953 | ARCH (pentiumiii, PENTIUMPRO, P3, false), | |
954 | ARCH (pentium4, PENTIUM4, P4, false), | |
955 | ARCH (prescott, NOCONA, CORE, false), | |
956 | ARCH (nocona, NOCONA, NOCONA, false), | |
957 | ARCH (yonah, CORE, CORE, true), | |
958 | ARCH (core, CORE, CORE, false), | |
959 | ARCH (merom, CORE2, CORE2, true), | |
960 | ARCH (core2, CORE2, CORE2, false), | |
961 | ARCH (corei7, COREI7, COREI7, false), | |
962 | ARCH (iamcu, IAMCU, IAMCU, false), | |
963 | ARCH (k6, K6, K6, false), | |
964 | ARCH (k6_2, K6, K6_2, false), | |
965 | ARCH (athlon, ATHLON, ATHLON, false), | |
966 | ARCH (sledgehammer, K8, K8, true), | |
967 | ARCH (opteron, K8, K8, false), | |
968 | ARCH (k8, K8, K8, false), | |
969 | ARCH (amdfam10, AMDFAM10, AMDFAM10, false), | |
970 | ARCH (bdver1, BD, BDVER1, false), | |
971 | ARCH (bdver2, BD, BDVER2, false), | |
972 | ARCH (bdver3, BD, BDVER3, false), | |
973 | ARCH (bdver4, BD, BDVER4, false), | |
974 | ARCH (znver1, ZNVER, ZNVER1, false), | |
975 | ARCH (znver2, ZNVER, ZNVER2, false), | |
976 | ARCH (znver3, ZNVER, ZNVER3, false), | |
977 | ARCH (btver1, BT, BTVER1, false), | |
978 | ARCH (btver2, BT, BTVER2, false), | |
979 | ||
ae89daec JB |
980 | SUBARCH (8087, 8087, ANY_X87, false), |
981 | SUBARCH (87, NONE, ANY_X87, false), /* Disable only! */ | |
982 | SUBARCH (287, 287, ANY_287, false), | |
983 | SUBARCH (387, 387, ANY_387, false), | |
984 | SUBARCH (687, 687, ANY_687, false), | |
985 | SUBARCH (cmov, CMOV, ANY_CMOV, false), | |
986 | SUBARCH (fxsr, FXSR, ANY_FXSR, false), | |
987 | SUBARCH (mmx, MMX, ANY_MMX, false), | |
988 | SUBARCH (sse, SSE, ANY_SSE, false), | |
989 | SUBARCH (sse2, SSE2, ANY_SSE2, false), | |
990 | SUBARCH (sse3, SSE3, ANY_SSE3, false), | |
991 | SUBARCH (sse4a, SSE4A, ANY_SSE4A, false), | |
992 | SUBARCH (ssse3, SSSE3, ANY_SSSE3, false), | |
993 | SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false), | |
994 | SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false), | |
995 | SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false), | |
996 | SUBARCH (avx, AVX, ANY_AVX, false), | |
997 | SUBARCH (avx2, AVX2, ANY_AVX2, false), | |
998 | SUBARCH (avx512f, AVX512F, ANY_AVX512F, false), | |
999 | SUBARCH (avx512cd, AVX512CD, ANY_AVX512CD, false), | |
1000 | SUBARCH (avx512er, AVX512ER, ANY_AVX512ER, false), | |
1001 | SUBARCH (avx512pf, AVX512PF, ANY_AVX512PF, false), | |
1002 | SUBARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, false), | |
1003 | SUBARCH (avx512bw, AVX512BW, ANY_AVX512BW, false), | |
1004 | SUBARCH (avx512vl, AVX512VL, ANY_AVX512VL, false), | |
1005 | SUBARCH (vmx, VMX, VMX, false), | |
1006 | SUBARCH (vmfunc, VMFUNC, VMFUNC, false), | |
1007 | SUBARCH (smx, SMX, SMX, false), | |
1008 | SUBARCH (xsave, XSAVE, XSAVE, false), | |
1009 | SUBARCH (xsaveopt, XSAVEOPT, XSAVEOPT, false), | |
1010 | SUBARCH (xsavec, XSAVEC, XSAVEC, false), | |
1011 | SUBARCH (xsaves, XSAVES, XSAVES, false), | |
1012 | SUBARCH (aes, AES, AES, false), | |
1013 | SUBARCH (pclmul, PCLMUL, PCLMUL, false), | |
1014 | SUBARCH (clmul, PCLMUL, PCLMUL, true), | |
1015 | SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false), | |
1016 | SUBARCH (rdrnd, RDRND, RDRND, false), | |
1017 | SUBARCH (f16c, F16C, F16C, false), | |
1018 | SUBARCH (bmi2, BMI2, BMI2, false), | |
1019 | SUBARCH (fma, FMA, FMA, false), | |
1020 | SUBARCH (fma4, FMA4, FMA4, false), | |
1021 | SUBARCH (xop, XOP, XOP, false), | |
1022 | SUBARCH (lwp, LWP, LWP, false), | |
1023 | SUBARCH (movbe, MOVBE, MOVBE, false), | |
1024 | SUBARCH (cx16, CX16, CX16, false), | |
1025 | SUBARCH (ept, EPT, EPT, false), | |
1026 | SUBARCH (lzcnt, LZCNT, LZCNT, false), | |
1027 | SUBARCH (popcnt, POPCNT, POPCNT, false), | |
1028 | SUBARCH (hle, HLE, HLE, false), | |
1029 | SUBARCH (rtm, RTM, RTM, false), | |
1030 | SUBARCH (invpcid, INVPCID, INVPCID, false), | |
1031 | SUBARCH (clflush, CLFLUSH, CLFLUSH, false), | |
1032 | SUBARCH (nop, NOP, NOP, false), | |
1033 | SUBARCH (syscall, SYSCALL, SYSCALL, false), | |
1034 | SUBARCH (rdtscp, RDTSCP, RDTSCP, false), | |
1035 | SUBARCH (3dnow, 3DNOW, 3DNOW, false), | |
1036 | SUBARCH (3dnowa, 3DNOWA, 3DNOWA, false), | |
1037 | SUBARCH (padlock, PADLOCK, PADLOCK, false), | |
1038 | SUBARCH (pacifica, SVME, SVME, true), | |
1039 | SUBARCH (svme, SVME, SVME, false), | |
1040 | SUBARCH (sse4a, SSE4A, SSE4A, false), | |
1041 | SUBARCH (abm, ABM, ABM, false), | |
1042 | SUBARCH (bmi, BMI, BMI, false), | |
1043 | SUBARCH (tbm, TBM, TBM, false), | |
1044 | SUBARCH (adx, ADX, ADX, false), | |
1045 | SUBARCH (rdseed, RDSEED, RDSEED, false), | |
1046 | SUBARCH (prfchw, PRFCHW, PRFCHW, false), | |
1047 | SUBARCH (smap, SMAP, SMAP, false), | |
1048 | SUBARCH (mpx, MPX, MPX, false), | |
1049 | SUBARCH (sha, SHA, SHA, false), | |
1050 | SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false), | |
1051 | SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false), | |
1052 | SUBARCH (se1, SE1, SE1, false), | |
1053 | SUBARCH (clwb, CLWB, CLWB, false), | |
1054 | SUBARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, false), | |
1055 | SUBARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, false), | |
1056 | SUBARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, false), | |
1057 | SUBARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, false), | |
1058 | SUBARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, false), | |
1059 | SUBARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, false), | |
1060 | SUBARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, false), | |
1061 | SUBARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, false), | |
1062 | SUBARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, false), | |
1063 | SUBARCH (clzero, CLZERO, CLZERO, false), | |
1064 | SUBARCH (mwaitx, MWAITX, MWAITX, false), | |
1065 | SUBARCH (ospke, OSPKE, OSPKE, false), | |
1066 | SUBARCH (rdpid, RDPID, RDPID, false), | |
1067 | SUBARCH (ptwrite, PTWRITE, PTWRITE, false), | |
1068 | SUBARCH (ibt, IBT, ANY_IBT, false), | |
1069 | SUBARCH (shstk, SHSTK, ANY_SHSTK, false), | |
1070 | SUBARCH (gfni, GFNI, GFNI, false), | |
1071 | SUBARCH (vaes, VAES, VAES, false), | |
1072 | SUBARCH (vpclmulqdq, VPCLMULQDQ, VPCLMULQDQ, false), | |
1073 | SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false), | |
1074 | SUBARCH (pconfig, PCONFIG, PCONFIG, false), | |
1075 | SUBARCH (waitpkg, WAITPKG, WAITPKG, false), | |
1076 | SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false), | |
1077 | SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false), | |
1078 | SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false), | |
68830fba | 1079 | SUBARCH (amx_fp16, AMX_FP16, AMX_FP16, false), |
ae89daec JB |
1080 | SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false), |
1081 | SUBARCH (movdiri, MOVDIRI, ANY_MOVDIRI, false), | |
1082 | SUBARCH (movdir64b, MOVDIR64B, ANY_MOVDIR64B, false), | |
1083 | SUBARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, false), | |
1084 | SUBARCH (avx512_vp2intersect, AVX512_VP2INTERSECT, | |
1085 | ANY_AVX512_VP2INTERSECT, false), | |
1086 | SUBARCH (tdx, TDX, ANY_TDX, false), | |
1087 | SUBARCH (enqcmd, ENQCMD, ANY_ENQCMD, false), | |
1088 | SUBARCH (serialize, SERIALIZE, ANY_SERIALIZE, false), | |
1089 | SUBARCH (rdpru, RDPRU, RDPRU, false), | |
1090 | SUBARCH (mcommit, MCOMMIT, MCOMMIT, false), | |
1091 | SUBARCH (sev_es, SEV_ES, SEV_ES, false), | |
1092 | SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false), | |
1093 | SUBARCH (kl, KL, ANY_KL, false), | |
1094 | SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false), | |
1095 | SUBARCH (uintr, UINTR, ANY_UINTR, false), | |
1096 | SUBARCH (hreset, HRESET, ANY_HRESET, false), | |
1097 | SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false), | |
ef07be45 | 1098 | SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false), |
4321af3e | 1099 | SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), |
23ae61ad | 1100 | SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), |
a93e3234 | 1101 | SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), |
941f0833 | 1102 | SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), |
2188d6ea | 1103 | SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false), |
01d8ce74 | 1104 | SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), |
b06311ad | 1105 | SUBARCH (rao_int, RAO_INT, ANY_RAO_INT, false), |
293f5f65 L |
1106 | }; |
1107 | ||
6ceeed25 JB |
1108 | #undef SUBARCH |
1109 | #undef ARCH | |
1110 | ||
704209c0 | 1111 | #ifdef I386COFF |
a6c24e68 NC |
1112 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1113 | is allowed to be optional. */ | |
1114 | ||
1115 | static symbolS * | |
1116 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1117 | { | |
1118 | addressT align = 0; | |
1119 | ||
1120 | SKIP_WHITESPACE (); | |
1121 | ||
7ab9ffdd | 1122 | if (needs_align |
a6c24e68 NC |
1123 | && *input_line_pointer == ',') |
1124 | { | |
1125 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1126 | |
a6c24e68 NC |
1127 | if (align == (addressT) -1) |
1128 | return NULL; | |
1129 | } | |
1130 | else | |
1131 | { | |
1132 | if (size >= 8) | |
1133 | align = 3; | |
1134 | else if (size >= 4) | |
1135 | align = 2; | |
1136 | else if (size >= 2) | |
1137 | align = 1; | |
1138 | else | |
1139 | align = 0; | |
1140 | } | |
1141 | ||
1142 | bss_alloc (symbolP, size, align); | |
1143 | return symbolP; | |
1144 | } | |
1145 | ||
704209c0 | 1146 | static void |
a6c24e68 NC |
1147 | pe_lcomm (int needs_align) |
1148 | { | |
1149 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1150 | } | |
704209c0 | 1151 | #endif |
a6c24e68 | 1152 | |
29b0f896 AM |
1153 | const pseudo_typeS md_pseudo_table[] = |
1154 | { | |
1155 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1156 | {"align", s_align_bytes, 0}, | |
1157 | #else | |
1158 | {"align", s_align_ptwo, 0}, | |
1159 | #endif | |
1160 | {"arch", set_cpu_arch, 0}, | |
1161 | #ifndef I386COFF | |
1162 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1163 | #else |
1164 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1165 | #endif |
1166 | {"ffloat", float_cons, 'f'}, | |
1167 | {"dfloat", float_cons, 'd'}, | |
1168 | {"tfloat", float_cons, 'x'}, | |
7d19d096 | 1169 | {"hfloat", float_cons, 'h'}, |
de133cf9 | 1170 | {"bfloat16", float_cons, 'b'}, |
29b0f896 | 1171 | {"value", cons, 2}, |
d182319b | 1172 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1173 | {"noopt", s_ignore, 0}, |
1174 | {"optim", s_ignore, 0}, | |
1175 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1176 | {"code16", set_code_flag, CODE_16BIT}, | |
1177 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1178 | #ifdef BFD64 |
29b0f896 | 1179 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1180 | #endif |
29b0f896 AM |
1181 | {"intel_syntax", set_intel_syntax, 1}, |
1182 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1183 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1184 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1185 | {"allow_index_reg", set_allow_index_reg, 1}, |
1186 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1187 | {"sse_check", set_check, 0}, |
1188 | {"operand_check", set_check, 1}, | |
3b22753a L |
1189 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1190 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1191 | #else |
68d20676 | 1192 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1193 | {"loc", dwarf2_directive_loc, 0}, |
1194 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1195 | #endif |
6482c264 NC |
1196 | #ifdef TE_PE |
1197 | {"secrel32", pe_directive_secrel, 0}, | |
145667f8 | 1198 | {"secidx", pe_directive_secidx, 0}, |
6482c264 | 1199 | #endif |
29b0f896 AM |
1200 | {0, 0, 0} |
1201 | }; | |
1202 | ||
1203 | /* For interface with expression (). */ | |
1204 | extern char *input_line_pointer; | |
1205 | ||
1206 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1207 | static htab_t op_hash; |
29b0f896 AM |
1208 | |
1209 | /* Hash table for register lookup. */ | |
629310ab | 1210 | static htab_t reg_hash; |
29b0f896 | 1211 | \f |
ce8a8b2f AM |
1212 | /* Various efficient no-op patterns for aligning code labels. |
1213 | Note: Don't try to assemble the instructions in the comments. | |
1214 | 0L and 0w are not legal. */ | |
62a02d25 L |
1215 | static const unsigned char f32_1[] = |
1216 | {0x90}; /* nop */ | |
1217 | static const unsigned char f32_2[] = | |
1218 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1219 | static const unsigned char f32_3[] = | |
1220 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1221 | static const unsigned char f32_4[] = | |
1222 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1223 | static const unsigned char f32_6[] = |
1224 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1225 | static const unsigned char f32_7[] = | |
1226 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1227 | static const unsigned char f16_3[] = |
3ae729d5 | 1228 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1229 | static const unsigned char f16_4[] = |
3ae729d5 L |
1230 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1231 | static const unsigned char jump_disp8[] = | |
1232 | {0xeb}; /* jmp disp8 */ | |
1233 | static const unsigned char jump32_disp32[] = | |
1234 | {0xe9}; /* jmp disp32 */ | |
1235 | static const unsigned char jump16_disp32[] = | |
1236 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1237 | /* 32-bit NOPs patterns. */ |
1238 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1239 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1240 | }; |
1241 | /* 16-bit NOPs patterns. */ | |
1242 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1243 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1244 | }; |
1245 | /* nopl (%[re]ax) */ | |
1246 | static const unsigned char alt_3[] = | |
1247 | {0x0f,0x1f,0x00}; | |
1248 | /* nopl 0(%[re]ax) */ | |
1249 | static const unsigned char alt_4[] = | |
1250 | {0x0f,0x1f,0x40,0x00}; | |
1251 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1252 | static const unsigned char alt_5[] = | |
1253 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1254 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1255 | static const unsigned char alt_6[] = | |
1256 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1257 | /* nopl 0L(%[re]ax) */ | |
1258 | static const unsigned char alt_7[] = | |
1259 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1260 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1261 | static const unsigned char alt_8[] = | |
1262 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1263 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1264 | static const unsigned char alt_9[] = | |
1265 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1266 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1267 | static const unsigned char alt_10[] = | |
1268 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1269 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1270 | static const unsigned char alt_11[] = | |
1271 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1272 | /* 32-bit and 64-bit NOPs patterns. */ |
1273 | static const unsigned char *const alt_patt[] = { | |
1274 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1275 | alt_9, alt_10, alt_11 |
62a02d25 L |
1276 | }; |
1277 | ||
1278 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1279 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1280 | ||
1281 | static void | |
1282 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1283 | int count, int max_single_nop_size) | |
1284 | ||
1285 | { | |
3ae729d5 L |
1286 | /* Place the longer NOP first. */ |
1287 | int last; | |
1288 | int offset; | |
3076e594 NC |
1289 | const unsigned char *nops; |
1290 | ||
1291 | if (max_single_nop_size < 1) | |
1292 | { | |
1293 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1294 | max_single_nop_size); | |
1295 | return; | |
1296 | } | |
1297 | ||
1298 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1299 | |
1300 | /* Use the smaller one if the requsted one isn't available. */ | |
1301 | if (nops == NULL) | |
62a02d25 | 1302 | { |
3ae729d5 L |
1303 | max_single_nop_size--; |
1304 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1305 | } |
1306 | ||
3ae729d5 L |
1307 | last = count % max_single_nop_size; |
1308 | ||
1309 | count -= last; | |
1310 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1311 | memcpy (where + offset, nops, max_single_nop_size); | |
1312 | ||
1313 | if (last) | |
1314 | { | |
1315 | nops = patt[last - 1]; | |
1316 | if (nops == NULL) | |
1317 | { | |
1318 | /* Use the smaller one plus one-byte NOP if the needed one | |
1319 | isn't available. */ | |
1320 | last--; | |
1321 | nops = patt[last - 1]; | |
1322 | memcpy (where + offset, nops, last); | |
1323 | where[offset + last] = *patt[0]; | |
1324 | } | |
1325 | else | |
1326 | memcpy (where + offset, nops, last); | |
1327 | } | |
62a02d25 L |
1328 | } |
1329 | ||
3ae729d5 L |
1330 | static INLINE int |
1331 | fits_in_imm7 (offsetT num) | |
1332 | { | |
1333 | return (num & 0x7f) == num; | |
1334 | } | |
1335 | ||
1336 | static INLINE int | |
1337 | fits_in_imm31 (offsetT num) | |
1338 | { | |
1339 | return (num & 0x7fffffff) == num; | |
1340 | } | |
62a02d25 L |
1341 | |
1342 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1343 | single NOP instruction LIMIT. */ | |
1344 | ||
1345 | void | |
3ae729d5 | 1346 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1347 | { |
3ae729d5 | 1348 | const unsigned char *const *patt = NULL; |
62a02d25 | 1349 | int max_single_nop_size; |
3ae729d5 L |
1350 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1351 | int max_number_of_nops; | |
62a02d25 | 1352 | |
3ae729d5 | 1353 | switch (fragP->fr_type) |
62a02d25 | 1354 | { |
3ae729d5 L |
1355 | case rs_fill_nop: |
1356 | case rs_align_code: | |
1357 | break; | |
e379e5f3 L |
1358 | case rs_machine_dependent: |
1359 | /* Allow NOP padding for jumps and calls. */ | |
1360 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1361 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1362 | break; | |
1363 | /* Fall through. */ | |
3ae729d5 | 1364 | default: |
62a02d25 L |
1365 | return; |
1366 | } | |
1367 | ||
ccc9c027 L |
1368 | /* We need to decide which NOP sequence to use for 32bit and |
1369 | 64bit. When -mtune= is used: | |
4eed87de | 1370 | |
76bc74dc L |
1371 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1372 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1373 | 2. For the rest, alt_patt will be used. |
1374 | ||
1375 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1376 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1377 | be used. |
ccc9c027 L |
1378 | |
1379 | When -march= or .arch is used, we can't use anything beyond | |
1380 | cpu_arch_isa_flags. */ | |
1381 | ||
1382 | if (flag_code == CODE_16BIT) | |
1383 | { | |
3ae729d5 L |
1384 | patt = f16_patt; |
1385 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1386 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1387 | max_number_of_nops = 2; | |
252b5132 | 1388 | } |
33fef721 | 1389 | else |
ccc9c027 | 1390 | { |
fbf3f584 | 1391 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1392 | { |
1393 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1394 | switch (cpu_arch_tune) | |
1395 | { | |
1396 | case PROCESSOR_UNKNOWN: | |
1397 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1398 | optimize with nops. */ |
1399 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1400 | patt = alt_patt; |
ccc9c027 L |
1401 | else |
1402 | patt = f32_patt; | |
1403 | break; | |
ccc9c027 L |
1404 | case PROCESSOR_PENTIUM4: |
1405 | case PROCESSOR_NOCONA: | |
ef05d495 | 1406 | case PROCESSOR_CORE: |
76bc74dc | 1407 | case PROCESSOR_CORE2: |
bd5295b2 | 1408 | case PROCESSOR_COREI7: |
76bc74dc | 1409 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1410 | case PROCESSOR_K6: |
1411 | case PROCESSOR_ATHLON: | |
1412 | case PROCESSOR_K8: | |
4eed87de | 1413 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1414 | case PROCESSOR_BD: |
029f3522 | 1415 | case PROCESSOR_ZNVER: |
7b458c12 | 1416 | case PROCESSOR_BT: |
80b8656c | 1417 | patt = alt_patt; |
ccc9c027 | 1418 | break; |
76bc74dc | 1419 | case PROCESSOR_I386: |
ccc9c027 L |
1420 | case PROCESSOR_I486: |
1421 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1422 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1423 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1424 | case PROCESSOR_GENERIC32: |
1425 | patt = f32_patt; | |
1426 | break; | |
c368d2a8 JB |
1427 | case PROCESSOR_NONE: |
1428 | abort (); | |
4eed87de | 1429 | } |
ccc9c027 L |
1430 | } |
1431 | else | |
1432 | { | |
fbf3f584 | 1433 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1434 | { |
1435 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1436 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1437 | PROCESSOR_UNKNOWN. */ |
1438 | abort (); | |
1439 | break; | |
1440 | ||
76bc74dc | 1441 | case PROCESSOR_I386: |
ccc9c027 L |
1442 | case PROCESSOR_I486: |
1443 | case PROCESSOR_PENTIUM: | |
81486035 | 1444 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1445 | case PROCESSOR_K6: |
1446 | case PROCESSOR_ATHLON: | |
1447 | case PROCESSOR_K8: | |
4eed87de | 1448 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1449 | case PROCESSOR_BD: |
029f3522 | 1450 | case PROCESSOR_ZNVER: |
7b458c12 | 1451 | case PROCESSOR_BT: |
ccc9c027 L |
1452 | case PROCESSOR_GENERIC32: |
1453 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1454 | with nops. */ |
1455 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1456 | patt = alt_patt; |
ccc9c027 L |
1457 | else |
1458 | patt = f32_patt; | |
1459 | break; | |
76bc74dc L |
1460 | case PROCESSOR_PENTIUMPRO: |
1461 | case PROCESSOR_PENTIUM4: | |
1462 | case PROCESSOR_NOCONA: | |
1463 | case PROCESSOR_CORE: | |
ef05d495 | 1464 | case PROCESSOR_CORE2: |
bd5295b2 | 1465 | case PROCESSOR_COREI7: |
22109423 | 1466 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1467 | patt = alt_patt; |
ccc9c027 L |
1468 | else |
1469 | patt = f32_patt; | |
1470 | break; | |
1471 | case PROCESSOR_GENERIC64: | |
80b8656c | 1472 | patt = alt_patt; |
ccc9c027 | 1473 | break; |
c368d2a8 JB |
1474 | case PROCESSOR_NONE: |
1475 | abort (); | |
4eed87de | 1476 | } |
ccc9c027 L |
1477 | } |
1478 | ||
76bc74dc L |
1479 | if (patt == f32_patt) |
1480 | { | |
3ae729d5 L |
1481 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1482 | /* Limit number of NOPs to 2 for older processors. */ | |
1483 | max_number_of_nops = 2; | |
76bc74dc L |
1484 | } |
1485 | else | |
1486 | { | |
3ae729d5 L |
1487 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1488 | /* Limit number of NOPs to 7 for newer processors. */ | |
1489 | max_number_of_nops = 7; | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | if (limit == 0) | |
1494 | limit = max_single_nop_size; | |
1495 | ||
1496 | if (fragP->fr_type == rs_fill_nop) | |
1497 | { | |
1498 | /* Output NOPs for .nop directive. */ | |
1499 | if (limit > max_single_nop_size) | |
1500 | { | |
1501 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1502 | _("invalid single nop size: %d " | |
1503 | "(expect within [0, %d])"), | |
1504 | limit, max_single_nop_size); | |
1505 | return; | |
1506 | } | |
1507 | } | |
e379e5f3 | 1508 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1509 | fragP->fr_var = count; |
1510 | ||
1511 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1512 | { | |
1513 | /* Generate jump over NOPs. */ | |
1514 | offsetT disp = count - 2; | |
1515 | if (fits_in_imm7 (disp)) | |
1516 | { | |
1517 | /* Use "jmp disp8" if possible. */ | |
1518 | count = disp; | |
1519 | where[0] = jump_disp8[0]; | |
1520 | where[1] = count; | |
1521 | where += 2; | |
1522 | } | |
1523 | else | |
1524 | { | |
1525 | unsigned int size_of_jump; | |
1526 | ||
1527 | if (flag_code == CODE_16BIT) | |
1528 | { | |
1529 | where[0] = jump16_disp32[0]; | |
1530 | where[1] = jump16_disp32[1]; | |
1531 | size_of_jump = 2; | |
1532 | } | |
1533 | else | |
1534 | { | |
1535 | where[0] = jump32_disp32[0]; | |
1536 | size_of_jump = 1; | |
1537 | } | |
1538 | ||
1539 | count -= size_of_jump + 4; | |
1540 | if (!fits_in_imm31 (count)) | |
1541 | { | |
1542 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1543 | _("jump over nop padding out of range")); | |
1544 | return; | |
1545 | } | |
1546 | ||
1547 | md_number_to_chars (where + size_of_jump, count, 4); | |
1548 | where += size_of_jump + 4; | |
76bc74dc | 1549 | } |
ccc9c027 | 1550 | } |
3ae729d5 L |
1551 | |
1552 | /* Generate multiple NOPs. */ | |
1553 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1554 | } |
1555 | ||
c6fb90c8 | 1556 | static INLINE int |
0dfbf9d7 | 1557 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1558 | { |
0dfbf9d7 | 1559 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1560 | { |
1561 | case 3: | |
0dfbf9d7 | 1562 | if (x->array[2]) |
c6fb90c8 | 1563 | return 0; |
1a0670f3 | 1564 | /* Fall through. */ |
c6fb90c8 | 1565 | case 2: |
0dfbf9d7 | 1566 | if (x->array[1]) |
c6fb90c8 | 1567 | return 0; |
1a0670f3 | 1568 | /* Fall through. */ |
c6fb90c8 | 1569 | case 1: |
0dfbf9d7 | 1570 | return !x->array[0]; |
c6fb90c8 L |
1571 | default: |
1572 | abort (); | |
1573 | } | |
40fb9820 L |
1574 | } |
1575 | ||
c6fb90c8 | 1576 | static INLINE void |
0dfbf9d7 | 1577 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1578 | { |
0dfbf9d7 | 1579 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1580 | { |
1581 | case 3: | |
0dfbf9d7 | 1582 | x->array[2] = v; |
1a0670f3 | 1583 | /* Fall through. */ |
c6fb90c8 | 1584 | case 2: |
0dfbf9d7 | 1585 | x->array[1] = v; |
1a0670f3 | 1586 | /* Fall through. */ |
c6fb90c8 | 1587 | case 1: |
0dfbf9d7 | 1588 | x->array[0] = v; |
1a0670f3 | 1589 | /* Fall through. */ |
c6fb90c8 L |
1590 | break; |
1591 | default: | |
1592 | abort (); | |
1593 | } | |
bab6aec1 JB |
1594 | |
1595 | x->bitfield.class = ClassNone; | |
75e5731b | 1596 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1597 | } |
40fb9820 | 1598 | |
c6fb90c8 | 1599 | static INLINE int |
0dfbf9d7 L |
1600 | operand_type_equal (const union i386_operand_type *x, |
1601 | const union i386_operand_type *y) | |
c6fb90c8 | 1602 | { |
0dfbf9d7 | 1603 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1604 | { |
1605 | case 3: | |
0dfbf9d7 | 1606 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1607 | return 0; |
1a0670f3 | 1608 | /* Fall through. */ |
c6fb90c8 | 1609 | case 2: |
0dfbf9d7 | 1610 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1611 | return 0; |
1a0670f3 | 1612 | /* Fall through. */ |
c6fb90c8 | 1613 | case 1: |
0dfbf9d7 | 1614 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1615 | break; |
1616 | default: | |
1617 | abort (); | |
1618 | } | |
1619 | } | |
40fb9820 | 1620 | |
0dfbf9d7 L |
1621 | static INLINE int |
1622 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1623 | { | |
1624 | switch (ARRAY_SIZE(x->array)) | |
1625 | { | |
75f8266a KL |
1626 | case 5: |
1627 | if (x->array[4]) | |
1628 | return 0; | |
1629 | /* Fall through. */ | |
53467f57 IT |
1630 | case 4: |
1631 | if (x->array[3]) | |
1632 | return 0; | |
1633 | /* Fall through. */ | |
0dfbf9d7 L |
1634 | case 3: |
1635 | if (x->array[2]) | |
1636 | return 0; | |
1a0670f3 | 1637 | /* Fall through. */ |
0dfbf9d7 L |
1638 | case 2: |
1639 | if (x->array[1]) | |
1640 | return 0; | |
1a0670f3 | 1641 | /* Fall through. */ |
0dfbf9d7 L |
1642 | case 1: |
1643 | return !x->array[0]; | |
1644 | default: | |
1645 | abort (); | |
1646 | } | |
1647 | } | |
1648 | ||
0dfbf9d7 L |
1649 | static INLINE int |
1650 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1651 | const union i386_cpu_flags *y) | |
1652 | { | |
1653 | switch (ARRAY_SIZE(x->array)) | |
1654 | { | |
75f8266a KL |
1655 | case 5: |
1656 | if (x->array[4] != y->array[4]) | |
1657 | return 0; | |
1658 | /* Fall through. */ | |
53467f57 IT |
1659 | case 4: |
1660 | if (x->array[3] != y->array[3]) | |
1661 | return 0; | |
1662 | /* Fall through. */ | |
0dfbf9d7 L |
1663 | case 3: |
1664 | if (x->array[2] != y->array[2]) | |
1665 | return 0; | |
1a0670f3 | 1666 | /* Fall through. */ |
0dfbf9d7 L |
1667 | case 2: |
1668 | if (x->array[1] != y->array[1]) | |
1669 | return 0; | |
1a0670f3 | 1670 | /* Fall through. */ |
0dfbf9d7 L |
1671 | case 1: |
1672 | return x->array[0] == y->array[0]; | |
1673 | break; | |
1674 | default: | |
1675 | abort (); | |
1676 | } | |
1677 | } | |
c6fb90c8 L |
1678 | |
1679 | static INLINE int | |
1680 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1681 | { | |
1682 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1683 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1684 | } |
1685 | ||
c6fb90c8 L |
1686 | static INLINE i386_cpu_flags |
1687 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1688 | { |
c6fb90c8 L |
1689 | switch (ARRAY_SIZE (x.array)) |
1690 | { | |
75f8266a KL |
1691 | case 5: |
1692 | x.array [4] &= y.array [4]; | |
1693 | /* Fall through. */ | |
53467f57 IT |
1694 | case 4: |
1695 | x.array [3] &= y.array [3]; | |
1696 | /* Fall through. */ | |
c6fb90c8 L |
1697 | case 3: |
1698 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1699 | /* Fall through. */ |
c6fb90c8 L |
1700 | case 2: |
1701 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1702 | /* Fall through. */ |
c6fb90c8 L |
1703 | case 1: |
1704 | x.array [0] &= y.array [0]; | |
1705 | break; | |
1706 | default: | |
1707 | abort (); | |
1708 | } | |
1709 | return x; | |
1710 | } | |
40fb9820 | 1711 | |
c6fb90c8 L |
1712 | static INLINE i386_cpu_flags |
1713 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1714 | { |
c6fb90c8 | 1715 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1716 | { |
75f8266a KL |
1717 | case 5: |
1718 | x.array [4] |= y.array [4]; | |
1719 | /* Fall through. */ | |
53467f57 IT |
1720 | case 4: |
1721 | x.array [3] |= y.array [3]; | |
1722 | /* Fall through. */ | |
c6fb90c8 L |
1723 | case 3: |
1724 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1725 | /* Fall through. */ |
c6fb90c8 L |
1726 | case 2: |
1727 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1728 | /* Fall through. */ |
c6fb90c8 L |
1729 | case 1: |
1730 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1731 | break; |
1732 | default: | |
1733 | abort (); | |
1734 | } | |
40fb9820 L |
1735 | return x; |
1736 | } | |
1737 | ||
309d3373 JB |
1738 | static INLINE i386_cpu_flags |
1739 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1740 | { | |
1741 | switch (ARRAY_SIZE (x.array)) | |
1742 | { | |
75f8266a KL |
1743 | case 5: |
1744 | x.array [4] &= ~y.array [4]; | |
1745 | /* Fall through. */ | |
53467f57 IT |
1746 | case 4: |
1747 | x.array [3] &= ~y.array [3]; | |
1748 | /* Fall through. */ | |
309d3373 JB |
1749 | case 3: |
1750 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1751 | /* Fall through. */ |
309d3373 JB |
1752 | case 2: |
1753 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1754 | /* Fall through. */ |
309d3373 JB |
1755 | case 1: |
1756 | x.array [0] &= ~y.array [0]; | |
1757 | break; | |
1758 | default: | |
1759 | abort (); | |
1760 | } | |
1761 | return x; | |
1762 | } | |
1763 | ||
6c0946d0 JB |
1764 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1765 | ||
c0f3af97 L |
1766 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1767 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1768 | ||
c0f3af97 | 1769 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1770 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1771 | |
1772 | /* Return CPU flags match bits. */ | |
3629bb00 | 1773 | |
40fb9820 | 1774 | static int |
d3ce72d0 | 1775 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1776 | { |
c0f3af97 L |
1777 | i386_cpu_flags x = t->cpu_flags; |
1778 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1779 | |
1780 | x.bitfield.cpu64 = 0; | |
1781 | x.bitfield.cpuno64 = 0; | |
1782 | ||
0dfbf9d7 | 1783 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1784 | { |
1785 | /* This instruction is available on all archs. */ | |
db12e14e | 1786 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1787 | } |
3629bb00 L |
1788 | else |
1789 | { | |
c0f3af97 | 1790 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1791 | i386_cpu_flags cpu = cpu_arch_flags; |
1792 | ||
ab592e75 JB |
1793 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1794 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1795 | return match; | |
1796 | x.bitfield.cpuavx512vl = 0; | |
1797 | ||
22c36940 JB |
1798 | /* AVX and AVX2 present at the same time express an operand size |
1799 | dependency - strip AVX2 for the purposes here. The operand size | |
1800 | dependent check occurs in check_vecOperands(). */ | |
1801 | if (x.bitfield.cpuavx && x.bitfield.cpuavx2) | |
1802 | x.bitfield.cpuavx2 = 0; | |
1803 | ||
3629bb00 | 1804 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1805 | if (!cpu_flags_all_zero (&cpu)) |
1806 | { | |
57392598 | 1807 | if (x.bitfield.cpuavx) |
a5ff0eb2 | 1808 | { |
929f69fa | 1809 | /* We need to check a few extra flags with AVX. */ |
b9d49817 | 1810 | if (cpu.bitfield.cpuavx |
40d231b4 JB |
1811 | && (!t->opcode_modifier.sse2avx |
1812 | || (sse2avx && !i.prefix[DATA_PREFIX])) | |
b9d49817 | 1813 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
929f69fa | 1814 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1815 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1816 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1817 | } |
929f69fa JB |
1818 | else if (x.bitfield.cpuavx512f) |
1819 | { | |
1820 | /* We need to check a few extra flags with AVX512F. */ | |
1821 | if (cpu.bitfield.cpuavx512f | |
1822 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1823 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1824 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1825 | match |= CPU_FLAGS_ARCH_MATCH; | |
1826 | } | |
a5ff0eb2 | 1827 | else |
db12e14e | 1828 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1829 | } |
3629bb00 | 1830 | } |
c0f3af97 | 1831 | return match; |
40fb9820 L |
1832 | } |
1833 | ||
c6fb90c8 L |
1834 | static INLINE i386_operand_type |
1835 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1836 | { |
bab6aec1 JB |
1837 | if (x.bitfield.class != y.bitfield.class) |
1838 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1839 | if (x.bitfield.instance != y.bitfield.instance) |
1840 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1841 | |
c6fb90c8 L |
1842 | switch (ARRAY_SIZE (x.array)) |
1843 | { | |
1844 | case 3: | |
1845 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1846 | /* Fall through. */ |
c6fb90c8 L |
1847 | case 2: |
1848 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1849 | /* Fall through. */ |
c6fb90c8 L |
1850 | case 1: |
1851 | x.array [0] &= y.array [0]; | |
1852 | break; | |
1853 | default: | |
1854 | abort (); | |
1855 | } | |
1856 | return x; | |
40fb9820 L |
1857 | } |
1858 | ||
73053c1f JB |
1859 | static INLINE i386_operand_type |
1860 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1861 | { | |
bab6aec1 | 1862 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1863 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1864 | |
73053c1f JB |
1865 | switch (ARRAY_SIZE (x.array)) |
1866 | { | |
1867 | case 3: | |
1868 | x.array [2] &= ~y.array [2]; | |
1869 | /* Fall through. */ | |
1870 | case 2: | |
1871 | x.array [1] &= ~y.array [1]; | |
1872 | /* Fall through. */ | |
1873 | case 1: | |
1874 | x.array [0] &= ~y.array [0]; | |
1875 | break; | |
1876 | default: | |
1877 | abort (); | |
1878 | } | |
1879 | return x; | |
1880 | } | |
1881 | ||
c6fb90c8 L |
1882 | static INLINE i386_operand_type |
1883 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1884 | { |
bab6aec1 JB |
1885 | gas_assert (x.bitfield.class == ClassNone || |
1886 | y.bitfield.class == ClassNone || | |
1887 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1888 | gas_assert (x.bitfield.instance == InstanceNone || |
1889 | y.bitfield.instance == InstanceNone || | |
1890 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1891 | |
c6fb90c8 | 1892 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1893 | { |
c6fb90c8 L |
1894 | case 3: |
1895 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1896 | /* Fall through. */ |
c6fb90c8 L |
1897 | case 2: |
1898 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1899 | /* Fall through. */ |
c6fb90c8 L |
1900 | case 1: |
1901 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1902 | break; |
1903 | default: | |
1904 | abort (); | |
1905 | } | |
c6fb90c8 L |
1906 | return x; |
1907 | } | |
40fb9820 | 1908 | |
c6fb90c8 L |
1909 | static INLINE i386_operand_type |
1910 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1911 | { | |
bab6aec1 | 1912 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1913 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1914 | |
c6fb90c8 L |
1915 | switch (ARRAY_SIZE (x.array)) |
1916 | { | |
1917 | case 3: | |
1918 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1919 | /* Fall through. */ |
c6fb90c8 L |
1920 | case 2: |
1921 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1922 | /* Fall through. */ |
c6fb90c8 L |
1923 | case 1: |
1924 | x.array [0] ^= y.array [0]; | |
1925 | break; | |
1926 | default: | |
1927 | abort (); | |
1928 | } | |
40fb9820 L |
1929 | return x; |
1930 | } | |
1931 | ||
40fb9820 | 1932 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; |
bab6aec1 | 1933 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
40fb9820 | 1934 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
40fb9820 L |
1935 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; |
1936 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
1937 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
40fb9820 L |
1938 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; |
1939 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
1940 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
1941 | ||
1942 | enum operand_type | |
1943 | { | |
1944 | reg, | |
40fb9820 L |
1945 | imm, |
1946 | disp, | |
1947 | anymem | |
1948 | }; | |
1949 | ||
c6fb90c8 | 1950 | static INLINE int |
40fb9820 L |
1951 | operand_type_check (i386_operand_type t, enum operand_type c) |
1952 | { | |
1953 | switch (c) | |
1954 | { | |
1955 | case reg: | |
bab6aec1 | 1956 | return t.bitfield.class == Reg; |
40fb9820 | 1957 | |
40fb9820 L |
1958 | case imm: |
1959 | return (t.bitfield.imm8 | |
1960 | || t.bitfield.imm8s | |
1961 | || t.bitfield.imm16 | |
1962 | || t.bitfield.imm32 | |
1963 | || t.bitfield.imm32s | |
1964 | || t.bitfield.imm64); | |
1965 | ||
1966 | case disp: | |
1967 | return (t.bitfield.disp8 | |
1968 | || t.bitfield.disp16 | |
1969 | || t.bitfield.disp32 | |
40fb9820 L |
1970 | || t.bitfield.disp64); |
1971 | ||
1972 | case anymem: | |
1973 | return (t.bitfield.disp8 | |
1974 | || t.bitfield.disp16 | |
1975 | || t.bitfield.disp32 | |
40fb9820 L |
1976 | || t.bitfield.disp64 |
1977 | || t.bitfield.baseindex); | |
1978 | ||
1979 | default: | |
1980 | abort (); | |
1981 | } | |
2cfe26b6 AM |
1982 | |
1983 | return 0; | |
40fb9820 L |
1984 | } |
1985 | ||
7a54636a L |
1986 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
1987 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
1988 | |
1989 | static INLINE int | |
7a54636a L |
1990 | match_operand_size (const insn_template *t, unsigned int wanted, |
1991 | unsigned int given) | |
5c07affc | 1992 | { |
3ac21baa JB |
1993 | return !((i.types[given].bitfield.byte |
1994 | && !t->operand_types[wanted].bitfield.byte) | |
1995 | || (i.types[given].bitfield.word | |
1996 | && !t->operand_types[wanted].bitfield.word) | |
1997 | || (i.types[given].bitfield.dword | |
1998 | && !t->operand_types[wanted].bitfield.dword) | |
1999 | || (i.types[given].bitfield.qword | |
2000 | && !t->operand_types[wanted].bitfield.qword) | |
2001 | || (i.types[given].bitfield.tbyte | |
2002 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2003 | } |
2004 | ||
dd40ce22 L |
2005 | /* Return 1 if there is no conflict in SIMD register between operand |
2006 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2007 | |
2008 | static INLINE int | |
dd40ce22 L |
2009 | match_simd_size (const insn_template *t, unsigned int wanted, |
2010 | unsigned int given) | |
1b54b8d7 | 2011 | { |
3ac21baa JB |
2012 | return !((i.types[given].bitfield.xmmword |
2013 | && !t->operand_types[wanted].bitfield.xmmword) | |
2014 | || (i.types[given].bitfield.ymmword | |
2015 | && !t->operand_types[wanted].bitfield.ymmword) | |
2016 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2017 | && !t->operand_types[wanted].bitfield.zmmword) |
2018 | || (i.types[given].bitfield.tmmword | |
2019 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2020 | } |
2021 | ||
7a54636a L |
2022 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2023 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2024 | |
2025 | static INLINE int | |
dd40ce22 L |
2026 | match_mem_size (const insn_template *t, unsigned int wanted, |
2027 | unsigned int given) | |
5c07affc | 2028 | { |
7a54636a | 2029 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2030 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2031 | && !i.broadcast.type |
a5748e0d | 2032 | && !i.broadcast.bytes |
3ac21baa JB |
2033 | && !t->operand_types[wanted].bitfield.unspecified) |
2034 | || (i.types[given].bitfield.fword | |
2035 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2036 | /* For scalar opcode templates to allow register and memory |
2037 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2038 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2039 | down-conversion vpmov*. */ | |
3528c362 | 2040 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2041 | && t->operand_types[wanted].bitfield.byte |
2042 | + t->operand_types[wanted].bitfield.word | |
2043 | + t->operand_types[wanted].bitfield.dword | |
2044 | + t->operand_types[wanted].bitfield.qword | |
2045 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2046 | ? (i.types[given].bitfield.xmmword |
2047 | || i.types[given].bitfield.ymmword | |
2048 | || i.types[given].bitfield.zmmword) | |
2049 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2050 | } |
2051 | ||
3ac21baa JB |
2052 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2053 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2054 | is no size conflict on any operands for the template with operands reversed | |
2055 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2056 | |
3ac21baa JB |
2057 | #define MATCH_STRAIGHT 1 |
2058 | #define MATCH_REVERSE 2 | |
2059 | ||
2060 | static INLINE unsigned int | |
d3ce72d0 | 2061 | operand_size_match (const insn_template *t) |
5c07affc | 2062 | { |
3ac21baa | 2063 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2064 | |
0cfa3eb3 | 2065 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2066 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2067 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2068 | return match; |
2069 | ||
2070 | /* Check memory and accumulator operand size. */ | |
2071 | for (j = 0; j < i.operands; j++) | |
2072 | { | |
3528c362 JB |
2073 | if (i.types[j].bitfield.class != Reg |
2074 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2075 | && t->opcode_modifier.anysize) |
5c07affc L |
2076 | continue; |
2077 | ||
bab6aec1 | 2078 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2079 | && !match_operand_size (t, j, j)) |
5c07affc L |
2080 | { |
2081 | match = 0; | |
2082 | break; | |
2083 | } | |
2084 | ||
3528c362 | 2085 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2086 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2087 | { |
2088 | match = 0; | |
2089 | break; | |
2090 | } | |
2091 | ||
75e5731b | 2092 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2093 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2094 | { |
2095 | match = 0; | |
2096 | break; | |
2097 | } | |
2098 | ||
c48dadc9 | 2099 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2100 | { |
2101 | match = 0; | |
2102 | break; | |
2103 | } | |
2104 | } | |
2105 | ||
3ac21baa | 2106 | if (!t->opcode_modifier.d) |
7b94647a | 2107 | return match; |
5c07affc L |
2108 | |
2109 | /* Check reverse. */ | |
8bd915b7 JB |
2110 | gas_assert ((i.operands >= 2 && i.operands <= 3) |
2111 | || t->opcode_modifier.vexsources); | |
5c07affc | 2112 | |
f5eb1d70 | 2113 | for (j = 0; j < i.operands; j++) |
5c07affc | 2114 | { |
f5eb1d70 JB |
2115 | unsigned int given = i.operands - j - 1; |
2116 | ||
8bd915b7 JB |
2117 | /* For 4- and 5-operand insns VEX.W controls just the first two |
2118 | register operands. */ | |
2119 | if (t->opcode_modifier.vexsources) | |
2120 | given = j < 2 ? 1 - j : j; | |
2121 | ||
bab6aec1 | 2122 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2123 | && !match_operand_size (t, j, given)) |
7b94647a | 2124 | return match; |
5c07affc | 2125 | |
3528c362 | 2126 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2127 | && !match_simd_size (t, j, given)) |
7b94647a | 2128 | return match; |
dbbc8b7e | 2129 | |
75e5731b | 2130 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2131 | && (!match_operand_size (t, j, given) |
2132 | || !match_simd_size (t, j, given))) | |
7b94647a | 2133 | return match; |
dbbc8b7e | 2134 | |
f5eb1d70 | 2135 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
7b94647a | 2136 | return match; |
5c07affc L |
2137 | } |
2138 | ||
3ac21baa | 2139 | return match | MATCH_REVERSE; |
5c07affc L |
2140 | } |
2141 | ||
c6fb90c8 | 2142 | static INLINE int |
40fb9820 L |
2143 | operand_type_match (i386_operand_type overlap, |
2144 | i386_operand_type given) | |
2145 | { | |
2146 | i386_operand_type temp = overlap; | |
2147 | ||
7d5e4556 | 2148 | temp.bitfield.unspecified = 0; |
5c07affc L |
2149 | temp.bitfield.byte = 0; |
2150 | temp.bitfield.word = 0; | |
2151 | temp.bitfield.dword = 0; | |
2152 | temp.bitfield.fword = 0; | |
2153 | temp.bitfield.qword = 0; | |
2154 | temp.bitfield.tbyte = 0; | |
2155 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2156 | temp.bitfield.ymmword = 0; |
43234a1e | 2157 | temp.bitfield.zmmword = 0; |
260cd341 | 2158 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2159 | if (operand_type_all_zero (&temp)) |
891edac4 | 2160 | goto mismatch; |
40fb9820 | 2161 | |
6f2f06be | 2162 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2163 | return 1; |
2164 | ||
dc1e8a47 | 2165 | mismatch: |
a65babc9 | 2166 | i.error = operand_type_mismatch; |
891edac4 | 2167 | return 0; |
40fb9820 L |
2168 | } |
2169 | ||
7d5e4556 | 2170 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2171 | unless the expected operand type register overlap is null. |
5de4d9ef | 2172 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2173 | |
c6fb90c8 | 2174 | static INLINE int |
dc821c5f | 2175 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2176 | i386_operand_type t0, |
40fb9820 L |
2177 | i386_operand_type g1, |
2178 | i386_operand_type t1) | |
2179 | { | |
bab6aec1 | 2180 | if (g0.bitfield.class != Reg |
3528c362 | 2181 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2182 | && (!operand_type_check (g0, anymem) |
2183 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2184 | || (t0.bitfield.class != Reg |
2185 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2186 | return 1; |
2187 | ||
bab6aec1 | 2188 | if (g1.bitfield.class != Reg |
3528c362 | 2189 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2190 | && (!operand_type_check (g1, anymem) |
2191 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2192 | || (t1.bitfield.class != Reg |
2193 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2194 | return 1; |
2195 | ||
dc821c5f JB |
2196 | if (g0.bitfield.byte == g1.bitfield.byte |
2197 | && g0.bitfield.word == g1.bitfield.word | |
2198 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2199 | && g0.bitfield.qword == g1.bitfield.qword |
2200 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2201 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2202 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2203 | return 1; |
2204 | ||
c4d09633 JB |
2205 | /* If expectations overlap in no more than a single size, all is fine. */ |
2206 | g0 = operand_type_and (t0, t1); | |
2207 | if (g0.bitfield.byte | |
2208 | + g0.bitfield.word | |
2209 | + g0.bitfield.dword | |
2210 | + g0.bitfield.qword | |
2211 | + g0.bitfield.xmmword | |
2212 | + g0.bitfield.ymmword | |
2213 | + g0.bitfield.zmmword <= 1) | |
891edac4 L |
2214 | return 1; |
2215 | ||
a65babc9 | 2216 | i.error = register_type_mismatch; |
891edac4 L |
2217 | |
2218 | return 0; | |
40fb9820 L |
2219 | } |
2220 | ||
4c692bc7 JB |
2221 | static INLINE unsigned int |
2222 | register_number (const reg_entry *r) | |
2223 | { | |
2224 | unsigned int nr = r->reg_num; | |
2225 | ||
2226 | if (r->reg_flags & RegRex) | |
2227 | nr += 8; | |
2228 | ||
200cbe0f L |
2229 | if (r->reg_flags & RegVRex) |
2230 | nr += 16; | |
2231 | ||
4c692bc7 JB |
2232 | return nr; |
2233 | } | |
2234 | ||
252b5132 | 2235 | static INLINE unsigned int |
40fb9820 | 2236 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2237 | { |
b5014f7a | 2238 | if (t.bitfield.disp8) |
40fb9820 L |
2239 | return 1; |
2240 | else if (t.bitfield.disp16 | |
a775efc8 | 2241 | || t.bitfield.disp32) |
40fb9820 L |
2242 | return 2; |
2243 | else | |
2244 | return 0; | |
252b5132 RH |
2245 | } |
2246 | ||
2247 | static INLINE int | |
65879393 | 2248 | fits_in_signed_byte (addressT num) |
252b5132 | 2249 | { |
65879393 | 2250 | return num + 0x80 <= 0xff; |
47926f60 | 2251 | } |
252b5132 RH |
2252 | |
2253 | static INLINE int | |
65879393 | 2254 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2255 | { |
65879393 | 2256 | return num <= 0xff; |
47926f60 | 2257 | } |
252b5132 RH |
2258 | |
2259 | static INLINE int | |
65879393 | 2260 | fits_in_unsigned_word (addressT num) |
252b5132 | 2261 | { |
65879393 | 2262 | return num <= 0xffff; |
47926f60 | 2263 | } |
252b5132 RH |
2264 | |
2265 | static INLINE int | |
65879393 | 2266 | fits_in_signed_word (addressT num) |
252b5132 | 2267 | { |
65879393 | 2268 | return num + 0x8000 <= 0xffff; |
47926f60 | 2269 | } |
2a962e6d | 2270 | |
3e73aa7c | 2271 | static INLINE int |
65879393 | 2272 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2273 | { |
2274 | #ifndef BFD64 | |
2275 | return 1; | |
2276 | #else | |
65879393 | 2277 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2278 | #endif |
2279 | } /* fits_in_signed_long() */ | |
2a962e6d | 2280 | |
3e73aa7c | 2281 | static INLINE int |
65879393 | 2282 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2283 | { |
2284 | #ifndef BFD64 | |
2285 | return 1; | |
2286 | #else | |
65879393 | 2287 | return num <= 0xffffffff; |
3e73aa7c JH |
2288 | #endif |
2289 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2290 | |
a442cac5 JB |
2291 | static INLINE valueT extend_to_32bit_address (addressT num) |
2292 | { | |
2293 | #ifdef BFD64 | |
2294 | if (fits_in_unsigned_long(num)) | |
2295 | return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
2296 | ||
2297 | if (!fits_in_signed_long (num)) | |
2298 | return num & 0xffffffff; | |
2299 | #endif | |
2300 | ||
2301 | return num; | |
2302 | } | |
2303 | ||
43234a1e | 2304 | static INLINE int |
b5014f7a | 2305 | fits_in_disp8 (offsetT num) |
43234a1e L |
2306 | { |
2307 | int shift = i.memshift; | |
2308 | unsigned int mask; | |
2309 | ||
2310 | if (shift == -1) | |
2311 | abort (); | |
2312 | ||
2313 | mask = (1 << shift) - 1; | |
2314 | ||
2315 | /* Return 0 if NUM isn't properly aligned. */ | |
2316 | if ((num & mask)) | |
2317 | return 0; | |
2318 | ||
2319 | /* Check if NUM will fit in 8bit after shift. */ | |
2320 | return fits_in_signed_byte (num >> shift); | |
2321 | } | |
2322 | ||
a683cc34 SP |
2323 | static INLINE int |
2324 | fits_in_imm4 (offsetT num) | |
2325 | { | |
2326 | return (num & 0xf) == num; | |
2327 | } | |
2328 | ||
40fb9820 | 2329 | static i386_operand_type |
e3bb37b5 | 2330 | smallest_imm_type (offsetT num) |
252b5132 | 2331 | { |
40fb9820 | 2332 | i386_operand_type t; |
7ab9ffdd | 2333 | |
0dfbf9d7 | 2334 | operand_type_set (&t, 0); |
40fb9820 L |
2335 | t.bitfield.imm64 = 1; |
2336 | ||
2337 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2338 | { |
2339 | /* This code is disabled on the 486 because all the Imm1 forms | |
2340 | in the opcode table are slower on the i486. They're the | |
2341 | versions with the implicitly specified single-position | |
2342 | displacement, which has another syntax if you really want to | |
2343 | use that form. */ | |
40fb9820 L |
2344 | t.bitfield.imm1 = 1; |
2345 | t.bitfield.imm8 = 1; | |
2346 | t.bitfield.imm8s = 1; | |
2347 | t.bitfield.imm16 = 1; | |
2348 | t.bitfield.imm32 = 1; | |
2349 | t.bitfield.imm32s = 1; | |
2350 | } | |
2351 | else if (fits_in_signed_byte (num)) | |
2352 | { | |
2353 | t.bitfield.imm8 = 1; | |
2354 | t.bitfield.imm8s = 1; | |
2355 | t.bitfield.imm16 = 1; | |
2356 | t.bitfield.imm32 = 1; | |
2357 | t.bitfield.imm32s = 1; | |
2358 | } | |
2359 | else if (fits_in_unsigned_byte (num)) | |
2360 | { | |
2361 | t.bitfield.imm8 = 1; | |
2362 | t.bitfield.imm16 = 1; | |
2363 | t.bitfield.imm32 = 1; | |
2364 | t.bitfield.imm32s = 1; | |
2365 | } | |
2366 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2367 | { | |
2368 | t.bitfield.imm16 = 1; | |
2369 | t.bitfield.imm32 = 1; | |
2370 | t.bitfield.imm32s = 1; | |
2371 | } | |
2372 | else if (fits_in_signed_long (num)) | |
2373 | { | |
2374 | t.bitfield.imm32 = 1; | |
2375 | t.bitfield.imm32s = 1; | |
2376 | } | |
2377 | else if (fits_in_unsigned_long (num)) | |
2378 | t.bitfield.imm32 = 1; | |
2379 | ||
2380 | return t; | |
47926f60 | 2381 | } |
252b5132 | 2382 | |
847f7ad4 | 2383 | static offsetT |
e3bb37b5 | 2384 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2385 | { |
508866be | 2386 | addressT mask; |
ba2adb93 | 2387 | |
847f7ad4 AM |
2388 | switch (size) |
2389 | { | |
508866be L |
2390 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2391 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3e73aa7c | 2392 | #ifdef BFD64 |
64965897 | 2393 | case 4: mask = ((addressT) 1 << 32) - 1; break; |
3e73aa7c | 2394 | #endif |
64965897 | 2395 | case sizeof (val): return val; |
47926f60 | 2396 | default: abort (); |
847f7ad4 AM |
2397 | } |
2398 | ||
4fe51f7d | 2399 | if ((val & ~mask) != 0 && (-val & ~mask) != 0) |
f493c217 AM |
2400 | as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64), |
2401 | (uint64_t) val, (uint64_t) (val & mask)); | |
847f7ad4 | 2402 | |
847f7ad4 AM |
2403 | return val & mask; |
2404 | } | |
2405 | ||
c32fa91d L |
2406 | enum PREFIX_GROUP |
2407 | { | |
2408 | PREFIX_EXIST = 0, | |
2409 | PREFIX_LOCK, | |
2410 | PREFIX_REP, | |
04ef582a | 2411 | PREFIX_DS, |
c32fa91d L |
2412 | PREFIX_OTHER |
2413 | }; | |
2414 | ||
2415 | /* Returns | |
2416 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2417 | same class already exists. | |
2418 | b. PREFIX_LOCK if lock prefix is added. | |
2419 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2420 | d. PREFIX_DS if ds prefix is added. |
2421 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2422 | */ |
2423 | ||
2424 | static enum PREFIX_GROUP | |
e3bb37b5 | 2425 | add_prefix (unsigned int prefix) |
252b5132 | 2426 | { |
c32fa91d | 2427 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2428 | unsigned int q; |
252b5132 | 2429 | |
29b0f896 AM |
2430 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2431 | && flag_code == CODE_64BIT) | |
b1905489 | 2432 | { |
161a04f6 | 2433 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2434 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2435 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2436 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2437 | ret = PREFIX_EXIST; |
b1905489 JB |
2438 | q = REX_PREFIX; |
2439 | } | |
3e73aa7c | 2440 | else |
b1905489 JB |
2441 | { |
2442 | switch (prefix) | |
2443 | { | |
2444 | default: | |
2445 | abort (); | |
2446 | ||
b1905489 | 2447 | case DS_PREFIX_OPCODE: |
04ef582a L |
2448 | ret = PREFIX_DS; |
2449 | /* Fall through. */ | |
2450 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2451 | case ES_PREFIX_OPCODE: |
2452 | case FS_PREFIX_OPCODE: | |
2453 | case GS_PREFIX_OPCODE: | |
2454 | case SS_PREFIX_OPCODE: | |
2455 | q = SEG_PREFIX; | |
2456 | break; | |
2457 | ||
2458 | case REPNE_PREFIX_OPCODE: | |
2459 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2460 | q = REP_PREFIX; |
2461 | ret = PREFIX_REP; | |
2462 | break; | |
2463 | ||
b1905489 | 2464 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2465 | q = LOCK_PREFIX; |
2466 | ret = PREFIX_LOCK; | |
b1905489 JB |
2467 | break; |
2468 | ||
2469 | case FWAIT_OPCODE: | |
2470 | q = WAIT_PREFIX; | |
2471 | break; | |
2472 | ||
2473 | case ADDR_PREFIX_OPCODE: | |
2474 | q = ADDR_PREFIX; | |
2475 | break; | |
2476 | ||
2477 | case DATA_PREFIX_OPCODE: | |
2478 | q = DATA_PREFIX; | |
2479 | break; | |
2480 | } | |
2481 | if (i.prefix[q] != 0) | |
c32fa91d | 2482 | ret = PREFIX_EXIST; |
b1905489 | 2483 | } |
252b5132 | 2484 | |
b1905489 | 2485 | if (ret) |
252b5132 | 2486 | { |
b1905489 JB |
2487 | if (!i.prefix[q]) |
2488 | ++i.prefixes; | |
2489 | i.prefix[q] |= prefix; | |
252b5132 | 2490 | } |
b1905489 JB |
2491 | else |
2492 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2493 | |
252b5132 RH |
2494 | return ret; |
2495 | } | |
2496 | ||
2497 | static void | |
78f12dd3 | 2498 | update_code_flag (int value, int check) |
eecb386c | 2499 | { |
78f12dd3 L |
2500 | PRINTF_LIKE ((*as_error)); |
2501 | ||
1e9cc1c2 | 2502 | flag_code = (enum flag_code) value; |
40fb9820 L |
2503 | if (flag_code == CODE_64BIT) |
2504 | { | |
2505 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2506 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2507 | } |
2508 | else | |
2509 | { | |
2510 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2511 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2512 | } |
2513 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2514 | { |
78f12dd3 L |
2515 | if (check) |
2516 | as_error = as_fatal; | |
2517 | else | |
2518 | as_error = as_bad; | |
2519 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2520 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2521 | } |
40fb9820 | 2522 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2523 | { |
78f12dd3 L |
2524 | if (check) |
2525 | as_error = as_fatal; | |
2526 | else | |
2527 | as_error = as_bad; | |
2528 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2529 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2530 | } |
eecb386c AM |
2531 | stackop_size = '\0'; |
2532 | } | |
2533 | ||
78f12dd3 L |
2534 | static void |
2535 | set_code_flag (int value) | |
2536 | { | |
2537 | update_code_flag (value, 0); | |
2538 | } | |
2539 | ||
eecb386c | 2540 | static void |
e3bb37b5 | 2541 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2542 | { |
1e9cc1c2 | 2543 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2544 | if (flag_code != CODE_16BIT) |
2545 | abort (); | |
2546 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2547 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2548 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2549 | } |
2550 | ||
2551 | static void | |
e3bb37b5 | 2552 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2553 | { |
2554 | /* Find out if register prefixing is specified. */ | |
2555 | int ask_naked_reg = 0; | |
2556 | ||
2557 | SKIP_WHITESPACE (); | |
29b0f896 | 2558 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2559 | { |
d02603dc NC |
2560 | char *string; |
2561 | int e = get_symbol_name (&string); | |
252b5132 | 2562 | |
47926f60 | 2563 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2564 | ask_naked_reg = 1; |
47926f60 | 2565 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2566 | ask_naked_reg = -1; |
2567 | else | |
d0b47220 | 2568 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2569 | (void) restore_line_pointer (e); |
252b5132 RH |
2570 | } |
2571 | demand_empty_rest_of_line (); | |
c3332e24 | 2572 | |
252b5132 RH |
2573 | intel_syntax = syntax_flag; |
2574 | ||
2575 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2576 | allow_naked_reg = (intel_syntax |
2577 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2578 | else |
2579 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2580 | |
ee86248c | 2581 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2582 | |
e4a3b5a4 | 2583 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2584 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2585 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2586 | } |
2587 | ||
1efbbeb4 L |
2588 | static void |
2589 | set_intel_mnemonic (int mnemonic_flag) | |
2590 | { | |
e1d4d893 | 2591 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2592 | } |
2593 | ||
db51cc60 L |
2594 | static void |
2595 | set_allow_index_reg (int flag) | |
2596 | { | |
2597 | allow_index_reg = flag; | |
2598 | } | |
2599 | ||
cb19c032 | 2600 | static void |
7bab8ab5 | 2601 | set_check (int what) |
cb19c032 | 2602 | { |
7bab8ab5 JB |
2603 | enum check_kind *kind; |
2604 | const char *str; | |
2605 | ||
2606 | if (what) | |
2607 | { | |
2608 | kind = &operand_check; | |
2609 | str = "operand"; | |
2610 | } | |
2611 | else | |
2612 | { | |
2613 | kind = &sse_check; | |
2614 | str = "sse"; | |
2615 | } | |
2616 | ||
cb19c032 L |
2617 | SKIP_WHITESPACE (); |
2618 | ||
2619 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2620 | { | |
d02603dc NC |
2621 | char *string; |
2622 | int e = get_symbol_name (&string); | |
cb19c032 L |
2623 | |
2624 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2625 | *kind = check_none; |
cb19c032 | 2626 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2627 | *kind = check_warning; |
cb19c032 | 2628 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2629 | *kind = check_error; |
cb19c032 | 2630 | else |
7bab8ab5 | 2631 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2632 | (void) restore_line_pointer (e); |
cb19c032 L |
2633 | } |
2634 | else | |
7bab8ab5 | 2635 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2636 | |
2637 | demand_empty_rest_of_line (); | |
2638 | } | |
2639 | ||
8a9036a4 L |
2640 | static void |
2641 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2642 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2643 | { |
2644 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2645 | static const char *arch; | |
2646 | ||
c085ab00 | 2647 | /* Intel MCU is only supported on ELF. */ |
8a9036a4 L |
2648 | if (!IS_ELF) |
2649 | return; | |
2650 | ||
2651 | if (!arch) | |
2652 | { | |
2653 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2654 | use default_arch. */ | |
2655 | arch = cpu_arch_name; | |
2656 | if (!arch) | |
2657 | arch = default_arch; | |
2658 | } | |
2659 | ||
81486035 | 2660 | /* If we are targeting Intel MCU, we must enable it. */ |
648d04db JB |
2661 | if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU) |
2662 | == new_flag.bitfield.cpuiamcu) | |
81486035 L |
2663 | return; |
2664 | ||
8a9036a4 L |
2665 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2666 | #endif | |
2667 | } | |
2668 | ||
8180707f JB |
2669 | static void |
2670 | extend_cpu_sub_arch_name (const char *name) | |
2671 | { | |
2672 | if (cpu_sub_arch_name) | |
2673 | cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name, | |
ae89daec | 2674 | ".", name, (const char *) NULL); |
8180707f | 2675 | else |
ae89daec | 2676 | cpu_sub_arch_name = concat (".", name, (const char *) NULL); |
8180707f JB |
2677 | } |
2678 | ||
e413e4e9 | 2679 | static void |
e3bb37b5 | 2680 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2681 | { |
f68697e8 JB |
2682 | typedef struct arch_stack_entry |
2683 | { | |
2684 | const struct arch_stack_entry *prev; | |
2685 | const char *name; | |
2686 | char *sub_name; | |
2687 | i386_cpu_flags flags; | |
2688 | i386_cpu_flags isa_flags; | |
2689 | enum processor_type isa; | |
2690 | enum flag_code flag_code; | |
2691 | char stackop_size; | |
2692 | bool no_cond_jump_promotion; | |
2693 | } arch_stack_entry; | |
2694 | static const arch_stack_entry *arch_stack_top; | |
2695 | ||
47926f60 | 2696 | SKIP_WHITESPACE (); |
e413e4e9 | 2697 | |
29b0f896 | 2698 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2699 | { |
3ce2ebcf JB |
2700 | char *s; |
2701 | int e = get_symbol_name (&s); | |
2702 | const char *string = s; | |
2703 | unsigned int j = 0; | |
40fb9820 | 2704 | i386_cpu_flags flags; |
e413e4e9 | 2705 | |
3ce2ebcf JB |
2706 | if (strcmp (string, "default") == 0) |
2707 | { | |
2708 | if (strcmp (default_arch, "iamcu") == 0) | |
2709 | string = default_arch; | |
2710 | else | |
2711 | { | |
2712 | static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS; | |
2713 | ||
2714 | cpu_arch_name = NULL; | |
2715 | free (cpu_sub_arch_name); | |
2716 | cpu_sub_arch_name = NULL; | |
2717 | cpu_arch_flags = cpu_unknown_flags; | |
2718 | if (flag_code == CODE_64BIT) | |
2719 | { | |
2720 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2721 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2722 | } | |
2723 | else | |
2724 | { | |
2725 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2726 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2727 | } | |
2728 | cpu_arch_isa = PROCESSOR_UNKNOWN; | |
ae89daec | 2729 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
3ce2ebcf JB |
2730 | if (!cpu_arch_tune_set) |
2731 | { | |
2732 | cpu_arch_tune = cpu_arch_isa; | |
2733 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2734 | } | |
2735 | ||
2736 | j = ARRAY_SIZE (cpu_arch) + 1; | |
2737 | } | |
2738 | } | |
f68697e8 JB |
2739 | else if (strcmp (string, "push") == 0) |
2740 | { | |
2741 | arch_stack_entry *top = XNEW (arch_stack_entry); | |
2742 | ||
2743 | top->name = cpu_arch_name; | |
2744 | if (cpu_sub_arch_name) | |
2745 | top->sub_name = xstrdup (cpu_sub_arch_name); | |
2746 | else | |
2747 | top->sub_name = NULL; | |
2748 | top->flags = cpu_arch_flags; | |
2749 | top->isa = cpu_arch_isa; | |
2750 | top->isa_flags = cpu_arch_isa_flags; | |
2751 | top->flag_code = flag_code; | |
2752 | top->stackop_size = stackop_size; | |
2753 | top->no_cond_jump_promotion = no_cond_jump_promotion; | |
2754 | ||
2755 | top->prev = arch_stack_top; | |
2756 | arch_stack_top = top; | |
2757 | ||
2758 | (void) restore_line_pointer (e); | |
2759 | demand_empty_rest_of_line (); | |
2760 | return; | |
2761 | } | |
2762 | else if (strcmp (string, "pop") == 0) | |
2763 | { | |
2764 | const arch_stack_entry *top = arch_stack_top; | |
2765 | ||
2766 | if (!top) | |
2767 | as_bad (_(".arch stack is empty")); | |
2768 | else if (top->flag_code != flag_code | |
2769 | || top->stackop_size != stackop_size) | |
2770 | { | |
2771 | static const unsigned int bits[] = { | |
2772 | [CODE_16BIT] = 16, | |
2773 | [CODE_32BIT] = 32, | |
2774 | [CODE_64BIT] = 64, | |
2775 | }; | |
2776 | ||
2777 | as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"), | |
2778 | bits[top->flag_code], | |
2779 | top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : ""); | |
2780 | } | |
2781 | else | |
2782 | { | |
2783 | arch_stack_top = top->prev; | |
2784 | ||
2785 | cpu_arch_name = top->name; | |
2786 | free (cpu_sub_arch_name); | |
2787 | cpu_sub_arch_name = top->sub_name; | |
2788 | cpu_arch_flags = top->flags; | |
2789 | cpu_arch_isa = top->isa; | |
2790 | cpu_arch_isa_flags = top->isa_flags; | |
2791 | no_cond_jump_promotion = top->no_cond_jump_promotion; | |
2792 | ||
2793 | XDELETE (top); | |
2794 | } | |
2795 | ||
2796 | (void) restore_line_pointer (e); | |
2797 | demand_empty_rest_of_line (); | |
2798 | return; | |
2799 | } | |
3ce2ebcf JB |
2800 | |
2801 | for (; j < ARRAY_SIZE (cpu_arch); j++) | |
e413e4e9 | 2802 | { |
ae89daec JB |
2803 | if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0 |
2804 | && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE)) | |
e413e4e9 | 2805 | { |
5c6af06e JB |
2806 | if (*string != '.') |
2807 | { | |
ae89daec | 2808 | check_cpu_arch_compatible (string, cpu_arch[j].enable); |
648d04db | 2809 | |
91d6fa6a | 2810 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 2811 | free (cpu_sub_arch_name); |
5c6af06e | 2812 | cpu_sub_arch_name = NULL; |
ae89daec | 2813 | cpu_arch_flags = cpu_arch[j].enable; |
40fb9820 L |
2814 | if (flag_code == CODE_64BIT) |
2815 | { | |
2816 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2817 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2818 | } | |
2819 | else | |
2820 | { | |
2821 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2822 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2823 | } | |
91d6fa6a | 2824 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 2825 | cpu_arch_isa_flags = cpu_arch[j].enable; |
ccc9c027 L |
2826 | if (!cpu_arch_tune_set) |
2827 | { | |
2828 | cpu_arch_tune = cpu_arch_isa; | |
2829 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2830 | } | |
d59a54c2 | 2831 | pre_386_16bit_warned = false; |
5c6af06e JB |
2832 | break; |
2833 | } | |
40fb9820 | 2834 | |
ae89daec JB |
2835 | if (cpu_flags_all_zero (&cpu_arch[j].enable)) |
2836 | continue; | |
2837 | ||
293f5f65 | 2838 | flags = cpu_flags_or (cpu_arch_flags, |
ae89daec | 2839 | cpu_arch[j].enable); |
81486035 | 2840 | |
5b64d091 | 2841 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2842 | { |
ae89daec | 2843 | extend_cpu_sub_arch_name (string + 1); |
40fb9820 | 2844 | cpu_arch_flags = flags; |
a586129e | 2845 | cpu_arch_isa_flags = flags; |
5c6af06e | 2846 | } |
0089dace L |
2847 | else |
2848 | cpu_arch_isa_flags | |
2849 | = cpu_flags_or (cpu_arch_isa_flags, | |
ae89daec | 2850 | cpu_arch[j].enable); |
d02603dc | 2851 | (void) restore_line_pointer (e); |
5c6af06e JB |
2852 | demand_empty_rest_of_line (); |
2853 | return; | |
e413e4e9 AM |
2854 | } |
2855 | } | |
293f5f65 | 2856 | |
ae89daec | 2857 | if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch)) |
293f5f65 | 2858 | { |
33eaf5de | 2859 | /* Disable an ISA extension. */ |
ae89daec JB |
2860 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
2861 | if (cpu_arch[j].type == PROCESSOR_NONE | |
2862 | && strcmp (string + 3, cpu_arch[j].name) == 0) | |
293f5f65 L |
2863 | { |
2864 | flags = cpu_flags_and_not (cpu_arch_flags, | |
ae89daec | 2865 | cpu_arch[j].disable); |
293f5f65 L |
2866 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
2867 | { | |
ae89daec | 2868 | extend_cpu_sub_arch_name (string + 1); |
293f5f65 L |
2869 | cpu_arch_flags = flags; |
2870 | cpu_arch_isa_flags = flags; | |
2871 | } | |
2872 | (void) restore_line_pointer (e); | |
2873 | demand_empty_rest_of_line (); | |
2874 | return; | |
2875 | } | |
293f5f65 L |
2876 | } |
2877 | ||
3ce2ebcf | 2878 | if (j == ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2879 | as_bad (_("no such architecture: `%s'"), string); |
2880 | ||
2881 | *input_line_pointer = e; | |
2882 | } | |
2883 | else | |
2884 | as_bad (_("missing cpu architecture")); | |
2885 | ||
fddf5b5b AM |
2886 | no_cond_jump_promotion = 0; |
2887 | if (*input_line_pointer == ',' | |
29b0f896 | 2888 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2889 | { |
d02603dc NC |
2890 | char *string; |
2891 | char e; | |
2892 | ||
2893 | ++input_line_pointer; | |
2894 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2895 | |
2896 | if (strcmp (string, "nojumps") == 0) | |
2897 | no_cond_jump_promotion = 1; | |
2898 | else if (strcmp (string, "jumps") == 0) | |
2899 | ; | |
2900 | else | |
2901 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2902 | ||
d02603dc | 2903 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2904 | } |
2905 | ||
e413e4e9 AM |
2906 | demand_empty_rest_of_line (); |
2907 | } | |
2908 | ||
8a9036a4 L |
2909 | enum bfd_architecture |
2910 | i386_arch (void) | |
2911 | { | |
c085ab00 | 2912 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
2913 | { |
2914 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2915 | || flag_code == CODE_64BIT) | |
2916 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2917 | return bfd_arch_iamcu; | |
2918 | } | |
8a9036a4 L |
2919 | else |
2920 | return bfd_arch_i386; | |
2921 | } | |
2922 | ||
b9d79e03 | 2923 | unsigned long |
7016a5d5 | 2924 | i386_mach (void) |
b9d79e03 | 2925 | { |
d34049e8 | 2926 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 2927 | { |
c085ab00 | 2928 | if (default_arch[6] == '\0') |
8a9036a4 | 2929 | return bfd_mach_x86_64; |
351f65ca L |
2930 | else |
2931 | return bfd_mach_x64_32; | |
8a9036a4 | 2932 | } |
5197d474 L |
2933 | else if (!strcmp (default_arch, "i386") |
2934 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2935 | { |
2936 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2937 | { | |
2938 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2939 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2940 | return bfd_mach_i386_iamcu; | |
2941 | } | |
2942 | else | |
2943 | return bfd_mach_i386_i386; | |
2944 | } | |
b9d79e03 | 2945 | else |
2b5d6a91 | 2946 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2947 | } |
b9d79e03 | 2948 | \f |
252b5132 | 2949 | void |
7016a5d5 | 2950 | md_begin (void) |
252b5132 | 2951 | { |
86fa6981 L |
2952 | /* Support pseudo prefixes like {disp32}. */ |
2953 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2954 | ||
47926f60 | 2955 | /* Initialize op_hash hash table. */ |
629310ab | 2956 | op_hash = str_htab_create (); |
252b5132 RH |
2957 | |
2958 | { | |
d3ce72d0 | 2959 | const insn_template *optab; |
29b0f896 | 2960 | templates *core_optab; |
252b5132 | 2961 | |
47926f60 KH |
2962 | /* Setup for loop. */ |
2963 | optab = i386_optab; | |
654d6f31 | 2964 | core_optab = notes_alloc (sizeof (*core_optab)); |
252b5132 RH |
2965 | core_optab->start = optab; |
2966 | ||
2967 | while (1) | |
2968 | { | |
2969 | ++optab; | |
2970 | if (optab->name == NULL | |
2971 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
2972 | { | |
2973 | /* different name --> ship out current template list; | |
47926f60 | 2974 | add to hash table; & begin anew. */ |
252b5132 | 2975 | core_optab->end = optab; |
fe0e921f AM |
2976 | if (str_hash_insert (op_hash, (optab - 1)->name, core_optab, 0)) |
2977 | as_fatal (_("duplicate %s"), (optab - 1)->name); | |
2978 | ||
252b5132 RH |
2979 | if (optab->name == NULL) |
2980 | break; | |
654d6f31 | 2981 | core_optab = notes_alloc (sizeof (*core_optab)); |
252b5132 RH |
2982 | core_optab->start = optab; |
2983 | } | |
2984 | } | |
2985 | } | |
2986 | ||
47926f60 | 2987 | /* Initialize reg_hash hash table. */ |
629310ab | 2988 | reg_hash = str_htab_create (); |
252b5132 | 2989 | { |
29b0f896 | 2990 | const reg_entry *regtab; |
c3fe08fa | 2991 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 2992 | |
c3fe08fa | 2993 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 2994 | { |
6288d05f JB |
2995 | switch (regtab->reg_type.bitfield.class) |
2996 | { | |
2997 | case Reg: | |
34684862 JB |
2998 | if (regtab->reg_type.bitfield.dword) |
2999 | { | |
3000 | if (regtab->reg_type.bitfield.instance == Accum) | |
3001 | reg_eax = regtab; | |
3002 | } | |
3003 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3004 | { |
3005 | /* There's no point inserting st(<N>) in the hash table, as | |
3006 | parentheses aren't included in register_chars[] anyway. */ | |
3007 | if (regtab->reg_type.bitfield.instance != Accum) | |
3008 | continue; | |
3009 | reg_st0 = regtab; | |
3010 | } | |
3011 | break; | |
3012 | ||
5e042380 JB |
3013 | case SReg: |
3014 | switch (regtab->reg_num) | |
3015 | { | |
3016 | case 0: reg_es = regtab; break; | |
3017 | case 2: reg_ss = regtab; break; | |
3018 | case 3: reg_ds = regtab; break; | |
3019 | } | |
3020 | break; | |
3021 | ||
6288d05f JB |
3022 | case RegMask: |
3023 | if (!regtab->reg_num) | |
3024 | reg_k0 = regtab; | |
3025 | break; | |
3026 | } | |
3027 | ||
6225c532 JB |
3028 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3029 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3030 | } |
252b5132 RH |
3031 | } |
3032 | ||
47926f60 | 3033 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3034 | { |
29b0f896 AM |
3035 | int c; |
3036 | char *p; | |
252b5132 RH |
3037 | |
3038 | for (c = 0; c < 256; c++) | |
3039 | { | |
014fbcda | 3040 | if (ISDIGIT (c) || ISLOWER (c)) |
252b5132 RH |
3041 | { |
3042 | mnemonic_chars[c] = c; | |
3043 | register_chars[c] = c; | |
3044 | operand_chars[c] = c; | |
3045 | } | |
3882b010 | 3046 | else if (ISUPPER (c)) |
252b5132 | 3047 | { |
3882b010 | 3048 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3049 | register_chars[c] = mnemonic_chars[c]; |
3050 | operand_chars[c] = c; | |
3051 | } | |
43234a1e | 3052 | else if (c == '{' || c == '}') |
86fa6981 L |
3053 | { |
3054 | mnemonic_chars[c] = c; | |
3055 | operand_chars[c] = c; | |
3056 | } | |
b3983e5f JB |
3057 | #ifdef SVR4_COMMENT_CHARS |
3058 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3059 | operand_chars[c] = c; | |
3060 | #endif | |
252b5132 | 3061 | |
3882b010 | 3062 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3063 | identifier_chars[c] = c; |
3064 | else if (c >= 128) | |
3065 | { | |
3066 | identifier_chars[c] = c; | |
3067 | operand_chars[c] = c; | |
3068 | } | |
3069 | } | |
3070 | ||
3071 | #ifdef LEX_AT | |
3072 | identifier_chars['@'] = '@'; | |
32137342 NC |
3073 | #endif |
3074 | #ifdef LEX_QM | |
3075 | identifier_chars['?'] = '?'; | |
3076 | operand_chars['?'] = '?'; | |
252b5132 | 3077 | #endif |
c0f3af97 | 3078 | mnemonic_chars['_'] = '_'; |
791fe849 | 3079 | mnemonic_chars['-'] = '-'; |
0003779b | 3080 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3081 | identifier_chars['_'] = '_'; |
3082 | identifier_chars['.'] = '.'; | |
3083 | ||
3084 | for (p = operand_special_chars; *p != '\0'; p++) | |
3085 | operand_chars[(unsigned char) *p] = *p; | |
3086 | } | |
3087 | ||
a4447b93 RH |
3088 | if (flag_code == CODE_64BIT) |
3089 | { | |
ca19b261 KT |
3090 | #if defined (OBJ_COFF) && defined (TE_PE) |
3091 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3092 | ? 32 : 16); | |
3093 | #else | |
a4447b93 | 3094 | x86_dwarf2_return_column = 16; |
ca19b261 | 3095 | #endif |
61ff971f | 3096 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3097 | } |
3098 | else | |
3099 | { | |
3100 | x86_dwarf2_return_column = 8; | |
3101 | x86_cie_data_alignment = -4; | |
3102 | } | |
e379e5f3 L |
3103 | |
3104 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3105 | can be turned into BRANCH_PREFIX frag. */ | |
3106 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3107 | abort (); | |
252b5132 RH |
3108 | } |
3109 | ||
3110 | void | |
e3bb37b5 | 3111 | i386_print_statistics (FILE *file) |
252b5132 | 3112 | { |
629310ab ML |
3113 | htab_print_statistics (file, "i386 opcode", op_hash); |
3114 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 | 3115 | } |
654d6f31 AM |
3116 | |
3117 | void | |
3118 | i386_md_end (void) | |
3119 | { | |
3120 | htab_delete (op_hash); | |
3121 | htab_delete (reg_hash); | |
3122 | } | |
252b5132 | 3123 | \f |
252b5132 RH |
3124 | #ifdef DEBUG386 |
3125 | ||
ce8a8b2f | 3126 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3127 | static void pte (insn_template *); |
40fb9820 | 3128 | static void pt (i386_operand_type); |
e3bb37b5 L |
3129 | static void pe (expressionS *); |
3130 | static void ps (symbolS *); | |
252b5132 RH |
3131 | |
3132 | static void | |
2c703856 | 3133 | pi (const char *line, i386_insn *x) |
252b5132 | 3134 | { |
09137c09 | 3135 | unsigned int j; |
252b5132 RH |
3136 | |
3137 | fprintf (stdout, "%s: template ", line); | |
3138 | pte (&x->tm); | |
09f131f2 JH |
3139 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3140 | x->base_reg ? x->base_reg->reg_name : "none", | |
3141 | x->index_reg ? x->index_reg->reg_name : "none", | |
3142 | x->log2_scale_factor); | |
3143 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3144 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3145 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3146 | x->sib.base, x->sib.index, x->sib.scale); | |
3147 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3148 | (x->rex & REX_W) != 0, |
3149 | (x->rex & REX_R) != 0, | |
3150 | (x->rex & REX_X) != 0, | |
3151 | (x->rex & REX_B) != 0); | |
09137c09 | 3152 | for (j = 0; j < x->operands; j++) |
252b5132 | 3153 | { |
09137c09 SP |
3154 | fprintf (stdout, " #%d: ", j + 1); |
3155 | pt (x->types[j]); | |
252b5132 | 3156 | fprintf (stdout, "\n"); |
bab6aec1 | 3157 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3158 | || x->types[j].bitfield.class == RegMMX |
3159 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3160 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3161 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3162 | || x->types[j].bitfield.class == RegCR |
3163 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3164 | || x->types[j].bitfield.class == RegTR |
3165 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3166 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3167 | if (operand_type_check (x->types[j], imm)) | |
3168 | pe (x->op[j].imms); | |
3169 | if (operand_type_check (x->types[j], disp)) | |
3170 | pe (x->op[j].disps); | |
252b5132 RH |
3171 | } |
3172 | } | |
3173 | ||
3174 | static void | |
d3ce72d0 | 3175 | pte (insn_template *t) |
252b5132 | 3176 | { |
b933fa4b | 3177 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca | 3178 | static const char *const opc_spc[] = { |
0cc78721 | 3179 | NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL, |
441f6aca JB |
3180 | "XOP08", "XOP09", "XOP0A", |
3181 | }; | |
09137c09 | 3182 | unsigned int j; |
441f6aca | 3183 | |
252b5132 | 3184 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3185 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3186 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
3187 | if (opc_spc[t->opcode_modifier.opcodespace]) | |
3188 | fprintf (stdout, "space %s ", opc_spc[t->opcode_modifier.opcodespace]); | |
47926f60 | 3189 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3190 | if (t->extension_opcode != None) |
3191 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3192 | if (t->opcode_modifier.d) |
252b5132 | 3193 | fprintf (stdout, "D"); |
40fb9820 | 3194 | if (t->opcode_modifier.w) |
252b5132 RH |
3195 | fprintf (stdout, "W"); |
3196 | fprintf (stdout, "\n"); | |
09137c09 | 3197 | for (j = 0; j < t->operands; j++) |
252b5132 | 3198 | { |
09137c09 SP |
3199 | fprintf (stdout, " #%d type ", j + 1); |
3200 | pt (t->operand_types[j]); | |
252b5132 RH |
3201 | fprintf (stdout, "\n"); |
3202 | } | |
3203 | } | |
3204 | ||
3205 | static void | |
e3bb37b5 | 3206 | pe (expressionS *e) |
252b5132 | 3207 | { |
24eab124 | 3208 | fprintf (stdout, " operation %d\n", e->X_op); |
b8281767 AM |
3209 | fprintf (stdout, " add_number %" PRId64 " (%" PRIx64 ")\n", |
3210 | (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number); | |
252b5132 RH |
3211 | if (e->X_add_symbol) |
3212 | { | |
3213 | fprintf (stdout, " add_symbol "); | |
3214 | ps (e->X_add_symbol); | |
3215 | fprintf (stdout, "\n"); | |
3216 | } | |
3217 | if (e->X_op_symbol) | |
3218 | { | |
3219 | fprintf (stdout, " op_symbol "); | |
3220 | ps (e->X_op_symbol); | |
3221 | fprintf (stdout, "\n"); | |
3222 | } | |
3223 | } | |
3224 | ||
3225 | static void | |
e3bb37b5 | 3226 | ps (symbolS *s) |
252b5132 RH |
3227 | { |
3228 | fprintf (stdout, "%s type %s%s", | |
3229 | S_GET_NAME (s), | |
3230 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3231 | segment_name (S_GET_SEGMENT (s))); | |
3232 | } | |
3233 | ||
7b81dfbb | 3234 | static struct type_name |
252b5132 | 3235 | { |
40fb9820 L |
3236 | i386_operand_type mask; |
3237 | const char *name; | |
252b5132 | 3238 | } |
7b81dfbb | 3239 | const type_names[] = |
252b5132 | 3240 | { |
40fb9820 L |
3241 | { OPERAND_TYPE_REG8, "r8" }, |
3242 | { OPERAND_TYPE_REG16, "r16" }, | |
3243 | { OPERAND_TYPE_REG32, "r32" }, | |
3244 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3245 | { OPERAND_TYPE_ACC8, "acc8" }, |
3246 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3247 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3248 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3249 | { OPERAND_TYPE_IMM8, "i8" }, |
3250 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3251 | { OPERAND_TYPE_IMM16, "i16" }, | |
3252 | { OPERAND_TYPE_IMM32, "i32" }, | |
3253 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3254 | { OPERAND_TYPE_IMM64, "i64" }, | |
3255 | { OPERAND_TYPE_IMM1, "i1" }, | |
3256 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3257 | { OPERAND_TYPE_DISP8, "d8" }, | |
3258 | { OPERAND_TYPE_DISP16, "d16" }, | |
3259 | { OPERAND_TYPE_DISP32, "d32" }, | |
40fb9820 L |
3260 | { OPERAND_TYPE_DISP64, "d64" }, |
3261 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3262 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3263 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3264 | { OPERAND_TYPE_TEST, "test reg" }, | |
3265 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3266 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3267 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3268 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3269 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3270 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3271 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e | 3272 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
260cd341 | 3273 | { OPERAND_TYPE_REGTMM, "rTMM" }, |
43234a1e | 3274 | { OPERAND_TYPE_REGMASK, "Mask reg" }, |
252b5132 RH |
3275 | }; |
3276 | ||
3277 | static void | |
40fb9820 | 3278 | pt (i386_operand_type t) |
252b5132 | 3279 | { |
40fb9820 | 3280 | unsigned int j; |
c6fb90c8 | 3281 | i386_operand_type a; |
252b5132 | 3282 | |
40fb9820 | 3283 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3284 | { |
3285 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3286 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3287 | fprintf (stdout, "%s, ", type_names[j].name); |
3288 | } | |
252b5132 RH |
3289 | fflush (stdout); |
3290 | } | |
3291 | ||
3292 | #endif /* DEBUG386 */ | |
3293 | \f | |
252b5132 | 3294 | static bfd_reloc_code_real_type |
3956db08 | 3295 | reloc (unsigned int size, |
64e74474 AM |
3296 | int pcrel, |
3297 | int sign, | |
3298 | bfd_reloc_code_real_type other) | |
252b5132 | 3299 | { |
47926f60 | 3300 | if (other != NO_RELOC) |
3956db08 | 3301 | { |
91d6fa6a | 3302 | reloc_howto_type *rel; |
3956db08 JB |
3303 | |
3304 | if (size == 8) | |
3305 | switch (other) | |
3306 | { | |
64e74474 AM |
3307 | case BFD_RELOC_X86_64_GOT32: |
3308 | return BFD_RELOC_X86_64_GOT64; | |
3309 | break; | |
553d1284 L |
3310 | case BFD_RELOC_X86_64_GOTPLT64: |
3311 | return BFD_RELOC_X86_64_GOTPLT64; | |
3312 | break; | |
64e74474 AM |
3313 | case BFD_RELOC_X86_64_PLTOFF64: |
3314 | return BFD_RELOC_X86_64_PLTOFF64; | |
3315 | break; | |
3316 | case BFD_RELOC_X86_64_GOTPC32: | |
3317 | other = BFD_RELOC_X86_64_GOTPC64; | |
3318 | break; | |
3319 | case BFD_RELOC_X86_64_GOTPCREL: | |
3320 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3321 | break; | |
3322 | case BFD_RELOC_X86_64_TPOFF32: | |
3323 | other = BFD_RELOC_X86_64_TPOFF64; | |
3324 | break; | |
3325 | case BFD_RELOC_X86_64_DTPOFF32: | |
3326 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3327 | break; | |
3328 | default: | |
3329 | break; | |
3956db08 | 3330 | } |
e05278af | 3331 | |
8ce3d284 | 3332 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3333 | if (other == BFD_RELOC_SIZE32) |
3334 | { | |
3335 | if (size == 8) | |
1ab668bf | 3336 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3337 | if (pcrel) |
1ab668bf AM |
3338 | { |
3339 | as_bad (_("there are no pc-relative size relocations")); | |
3340 | return NO_RELOC; | |
3341 | } | |
8fd4256d | 3342 | } |
8ce3d284 | 3343 | #endif |
8fd4256d | 3344 | |
e05278af | 3345 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3346 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3347 | sign = -1; |
3348 | ||
91d6fa6a NC |
3349 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3350 | if (!rel) | |
3956db08 | 3351 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3352 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3353 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3354 | bfd_get_reloc_size (rel), |
3956db08 | 3355 | size); |
91d6fa6a | 3356 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3357 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3358 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3359 | && !sign) |
91d6fa6a | 3360 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3361 | && sign > 0)) |
3956db08 JB |
3362 | as_bad (_("relocated field and relocation type differ in signedness")); |
3363 | else | |
3364 | return other; | |
3365 | return NO_RELOC; | |
3366 | } | |
252b5132 RH |
3367 | |
3368 | if (pcrel) | |
3369 | { | |
3e73aa7c | 3370 | if (!sign) |
3956db08 | 3371 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3372 | switch (size) |
3373 | { | |
3374 | case 1: return BFD_RELOC_8_PCREL; | |
3375 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3376 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3377 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3378 | } |
3956db08 | 3379 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3380 | } |
3381 | else | |
3382 | { | |
3956db08 | 3383 | if (sign > 0) |
e5cb08ac | 3384 | switch (size) |
3e73aa7c JH |
3385 | { |
3386 | case 4: return BFD_RELOC_X86_64_32S; | |
3387 | } | |
3388 | else | |
3389 | switch (size) | |
3390 | { | |
3391 | case 1: return BFD_RELOC_8; | |
3392 | case 2: return BFD_RELOC_16; | |
3393 | case 4: return BFD_RELOC_32; | |
3394 | case 8: return BFD_RELOC_64; | |
3395 | } | |
3956db08 JB |
3396 | as_bad (_("cannot do %s %u byte relocation"), |
3397 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3398 | } |
3399 | ||
0cc9e1d3 | 3400 | return NO_RELOC; |
252b5132 RH |
3401 | } |
3402 | ||
47926f60 KH |
3403 | /* Here we decide which fixups can be adjusted to make them relative to |
3404 | the beginning of the section instead of the symbol. Basically we need | |
3405 | to make sure that the dynamic relocations are done correctly, so in | |
3406 | some cases we force the original symbol to be used. */ | |
3407 | ||
252b5132 | 3408 | int |
e3bb37b5 | 3409 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3410 | { |
6d249963 | 3411 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3412 | if (!IS_ELF) |
31312f95 AM |
3413 | return 1; |
3414 | ||
a161fe53 AM |
3415 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3416 | mode. */ | |
3417 | if (use_rela_relocations | |
3418 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3419 | && fixP->fx_pcrel) | |
252b5132 | 3420 | return 0; |
31312f95 | 3421 | |
8d01d9a9 AJ |
3422 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3423 | and changed later by validate_fix. */ | |
3424 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3425 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3426 | return 0; | |
3427 | ||
8fd4256d L |
3428 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3429 | for size relocations. */ | |
3430 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3431 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3432 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3433 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3434 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3435 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3436 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3437 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3438 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3439 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3440 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3441 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3442 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3443 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3444 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3445 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3446 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3447 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3448 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3449 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3450 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3451 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3452 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3453 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3454 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3455 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3456 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3457 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3458 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3459 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3460 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3461 | return 0; | |
31312f95 | 3462 | #endif |
252b5132 RH |
3463 | return 1; |
3464 | } | |
252b5132 | 3465 | |
a9aabc23 JB |
3466 | static INLINE bool |
3467 | want_disp32 (const insn_template *t) | |
3468 | { | |
3469 | return flag_code != CODE_64BIT | |
3470 | || i.prefix[ADDR_PREFIX] | |
3471 | || (t->base_opcode == 0x8d | |
3472 | && t->opcode_modifier.opcodespace == SPACE_BASE | |
fe134c65 JB |
3473 | && (!i.types[1].bitfield.qword |
3474 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3475 | } |
3476 | ||
b4cac588 | 3477 | static int |
e3bb37b5 | 3478 | intel_float_operand (const char *mnemonic) |
252b5132 | 3479 | { |
9306ca4a JB |
3480 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3481 | operands, hence the code here is free to improperly handle opcodes that | |
3482 | have no operands (for better performance and smaller code). */ | |
3483 | ||
3484 | if (mnemonic[0] != 'f') | |
3485 | return 0; /* non-math */ | |
3486 | ||
3487 | switch (mnemonic[1]) | |
3488 | { | |
3489 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3490 | the fs segment override prefix not currently handled because no | |
3491 | call path can make opcodes without operands get here */ | |
3492 | case 'i': | |
3493 | return 2 /* integer op */; | |
3494 | case 'l': | |
3495 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3496 | return 3; /* fldcw/fldenv */ | |
3497 | break; | |
3498 | case 'n': | |
3499 | if (mnemonic[2] != 'o' /* fnop */) | |
3500 | return 3; /* non-waiting control op */ | |
3501 | break; | |
3502 | case 'r': | |
3503 | if (mnemonic[2] == 's') | |
3504 | return 3; /* frstor/frstpm */ | |
3505 | break; | |
3506 | case 's': | |
3507 | if (mnemonic[2] == 'a') | |
3508 | return 3; /* fsave */ | |
3509 | if (mnemonic[2] == 't') | |
3510 | { | |
3511 | switch (mnemonic[3]) | |
3512 | { | |
3513 | case 'c': /* fstcw */ | |
3514 | case 'd': /* fstdw */ | |
3515 | case 'e': /* fstenv */ | |
3516 | case 's': /* fsts[gw] */ | |
3517 | return 3; | |
3518 | } | |
3519 | } | |
3520 | break; | |
3521 | case 'x': | |
3522 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3523 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3524 | break; | |
3525 | } | |
252b5132 | 3526 | |
9306ca4a | 3527 | return 1; |
252b5132 RH |
3528 | } |
3529 | ||
9a182d04 JB |
3530 | static INLINE void |
3531 | install_template (const insn_template *t) | |
3532 | { | |
3533 | unsigned int l; | |
3534 | ||
3535 | i.tm = *t; | |
3536 | ||
3537 | /* Note that for pseudo prefixes this produces a length of 1. But for them | |
3538 | the length isn't interesting at all. */ | |
3539 | for (l = 1; l < 4; ++l) | |
3540 | if (!(t->base_opcode >> (8 * l))) | |
3541 | break; | |
3542 | ||
3543 | i.opcode_length = l; | |
3544 | } | |
3545 | ||
c0f3af97 L |
3546 | /* Build the VEX prefix. */ |
3547 | ||
3548 | static void | |
d3ce72d0 | 3549 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3550 | { |
3551 | unsigned int register_specifier; | |
c0f3af97 | 3552 | unsigned int vector_length; |
03751133 | 3553 | unsigned int w; |
c0f3af97 L |
3554 | |
3555 | /* Check register specifier. */ | |
3556 | if (i.vex.register_specifier) | |
43234a1e L |
3557 | { |
3558 | register_specifier = | |
3559 | ~register_number (i.vex.register_specifier) & 0xf; | |
3560 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3561 | } | |
c0f3af97 L |
3562 | else |
3563 | register_specifier = 0xf; | |
3564 | ||
79f0fa25 L |
3565 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3566 | if there are more than 1 register operand. */ | |
3567 | if (i.reg_operands > 1 | |
3568 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3569 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3570 | && i.operands == i.reg_operands |
dbbc8b7e | 3571 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
441f6aca | 3572 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
dbbc8b7e | 3573 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3574 | && i.rex == REX_B) |
3575 | { | |
3576 | unsigned int xchg = i.operands - 1; | |
3577 | union i386_op temp_op; | |
3578 | i386_operand_type temp_type; | |
3579 | ||
3580 | temp_type = i.types[xchg]; | |
3581 | i.types[xchg] = i.types[0]; | |
3582 | i.types[0] = temp_type; | |
3583 | temp_op = i.op[xchg]; | |
3584 | i.op[xchg] = i.op[0]; | |
3585 | i.op[0] = temp_op; | |
3586 | ||
9c2799c2 | 3587 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3588 | |
3589 | i.rex = REX_R; | |
3590 | xchg = i.rm.regmem; | |
3591 | i.rm.regmem = i.rm.reg; | |
3592 | i.rm.reg = xchg; | |
3593 | ||
dbbc8b7e JB |
3594 | if (i.tm.opcode_modifier.d) |
3595 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
2c735193 | 3596 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
dbbc8b7e | 3597 | else /* Use the next insn. */ |
9a182d04 | 3598 | install_template (&t[1]); |
fa99fab2 L |
3599 | } |
3600 | ||
79dec6b7 JB |
3601 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3602 | are no memory operands and at least 3 register ones. */ | |
3603 | if (i.reg_operands >= 3 | |
3604 | && i.vec_encoding != vex_encoding_vex3 | |
3605 | && i.reg_operands == i.operands - i.imm_operands | |
3606 | && i.tm.opcode_modifier.vex | |
3607 | && i.tm.opcode_modifier.commutative | |
3608 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3609 | && i.rex == REX_B | |
3610 | && i.vex.register_specifier | |
3611 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3612 | { | |
3613 | unsigned int xchg = i.operands - i.reg_operands; | |
3614 | union i386_op temp_op; | |
3615 | i386_operand_type temp_type; | |
3616 | ||
441f6aca | 3617 | gas_assert (i.tm.opcode_modifier.opcodespace == SPACE_0F); |
79dec6b7 JB |
3618 | gas_assert (!i.tm.opcode_modifier.sae); |
3619 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3620 | &i.types[i.operands - 3])); | |
3621 | gas_assert (i.rm.mode == 3); | |
3622 | ||
3623 | temp_type = i.types[xchg]; | |
3624 | i.types[xchg] = i.types[xchg + 1]; | |
3625 | i.types[xchg + 1] = temp_type; | |
3626 | temp_op = i.op[xchg]; | |
3627 | i.op[xchg] = i.op[xchg + 1]; | |
3628 | i.op[xchg + 1] = temp_op; | |
3629 | ||
3630 | i.rex = 0; | |
3631 | xchg = i.rm.regmem | 8; | |
3632 | i.rm.regmem = ~register_specifier & 0xf; | |
3633 | gas_assert (!(i.rm.regmem & 8)); | |
3634 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3635 | register_specifier = ~xchg & 0xf; | |
3636 | } | |
3637 | ||
539f890d L |
3638 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3639 | vector_length = avxscalar; | |
10c17abd JB |
3640 | else if (i.tm.opcode_modifier.vex == VEX256) |
3641 | vector_length = 1; | |
539f890d | 3642 | else |
10c17abd | 3643 | { |
56522fc5 | 3644 | unsigned int op; |
10c17abd | 3645 | |
c7213af9 L |
3646 | /* Determine vector length from the last multi-length vector |
3647 | operand. */ | |
10c17abd | 3648 | vector_length = 0; |
56522fc5 | 3649 | for (op = t->operands; op--;) |
10c17abd JB |
3650 | if (t->operand_types[op].bitfield.xmmword |
3651 | && t->operand_types[op].bitfield.ymmword | |
3652 | && i.types[op].bitfield.ymmword) | |
3653 | { | |
3654 | vector_length = 1; | |
3655 | break; | |
3656 | } | |
3657 | } | |
c0f3af97 | 3658 | |
03751133 L |
3659 | /* Check the REX.W bit and VEXW. */ |
3660 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3661 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3662 | else if (i.tm.opcode_modifier.vexw) | |
3663 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3664 | else | |
931d03b7 | 3665 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3666 | |
c0f3af97 | 3667 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3668 | if (w == 0 |
3669 | && i.vec_encoding != vex_encoding_vex3 | |
441f6aca | 3670 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
c0f3af97 L |
3671 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3672 | { | |
3673 | /* 2-byte VEX prefix. */ | |
3674 | unsigned int r; | |
3675 | ||
3676 | i.vex.length = 2; | |
3677 | i.vex.bytes[0] = 0xc5; | |
3678 | ||
3679 | /* Check the REX.R bit. */ | |
3680 | r = (i.rex & REX_R) ? 0 : 1; | |
3681 | i.vex.bytes[1] = (r << 7 | |
3682 | | register_specifier << 3 | |
3683 | | vector_length << 2 | |
35648716 | 3684 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3685 | } |
3686 | else | |
3687 | { | |
3688 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3689 | i.vex.length = 3; |
f88c9eb0 | 3690 | |
441f6aca | 3691 | switch (i.tm.opcode_modifier.opcodespace) |
5dd85c99 | 3692 | { |
441f6aca JB |
3693 | case SPACE_0F: |
3694 | case SPACE_0F38: | |
3695 | case SPACE_0F3A: | |
80de6e00 | 3696 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3697 | break; |
441f6aca JB |
3698 | case SPACE_XOP08: |
3699 | case SPACE_XOP09: | |
3700 | case SPACE_XOP0A: | |
f88c9eb0 | 3701 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3702 | break; |
3703 | default: | |
3704 | abort (); | |
f88c9eb0 | 3705 | } |
c0f3af97 | 3706 | |
c0f3af97 L |
3707 | /* The high 3 bits of the second VEX byte are 1's compliment |
3708 | of RXB bits from REX. */ | |
441f6aca | 3709 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_modifier.opcodespace; |
c0f3af97 | 3710 | |
c0f3af97 L |
3711 | i.vex.bytes[2] = (w << 7 |
3712 | | register_specifier << 3 | |
3713 | | vector_length << 2 | |
35648716 | 3714 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3715 | } |
3716 | } | |
3717 | ||
5b7c81bd | 3718 | static INLINE bool |
e771e7c9 JB |
3719 | is_evex_encoding (const insn_template *t) |
3720 | { | |
7091c612 | 3721 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3722 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3723 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3724 | } |
3725 | ||
5b7c81bd | 3726 | static INLINE bool |
7a8655d2 JB |
3727 | is_any_vex_encoding (const insn_template *t) |
3728 | { | |
7b47a312 | 3729 | return t->opcode_modifier.vex || is_evex_encoding (t); |
7a8655d2 JB |
3730 | } |
3731 | ||
a5748e0d JB |
3732 | static unsigned int |
3733 | get_broadcast_bytes (const insn_template *t, bool diag) | |
3734 | { | |
3735 | unsigned int op, bytes; | |
3736 | const i386_operand_type *types; | |
3737 | ||
3738 | if (i.broadcast.type) | |
3739 | return i.broadcast.bytes = ((1 << (t->opcode_modifier.broadcast - 1)) | |
3740 | * i.broadcast.type); | |
3741 | ||
3742 | gas_assert (intel_syntax); | |
3743 | ||
3744 | for (op = 0; op < t->operands; ++op) | |
3745 | if (t->operand_types[op].bitfield.baseindex) | |
3746 | break; | |
3747 | ||
3748 | gas_assert (op < t->operands); | |
3749 | ||
3750 | if (t->opcode_modifier.evex | |
3751 | && t->opcode_modifier.evex != EVEXDYN) | |
3752 | switch (i.broadcast.bytes) | |
3753 | { | |
3754 | case 1: | |
3755 | if (t->operand_types[op].bitfield.word) | |
3756 | return 2; | |
3757 | /* Fall through. */ | |
3758 | case 2: | |
3759 | if (t->operand_types[op].bitfield.dword) | |
3760 | return 4; | |
3761 | /* Fall through. */ | |
3762 | case 4: | |
3763 | if (t->operand_types[op].bitfield.qword) | |
3764 | return 8; | |
3765 | /* Fall through. */ | |
3766 | case 8: | |
3767 | if (t->operand_types[op].bitfield.xmmword) | |
3768 | return 16; | |
3769 | if (t->operand_types[op].bitfield.ymmword) | |
3770 | return 32; | |
3771 | if (t->operand_types[op].bitfield.zmmword) | |
3772 | return 64; | |
3773 | /* Fall through. */ | |
3774 | default: | |
3775 | abort (); | |
3776 | } | |
3777 | ||
3778 | gas_assert (op + 1 < t->operands); | |
3779 | ||
3780 | if (t->operand_types[op + 1].bitfield.xmmword | |
3781 | + t->operand_types[op + 1].bitfield.ymmword | |
3782 | + t->operand_types[op + 1].bitfield.zmmword > 1) | |
3783 | { | |
3784 | types = &i.types[op + 1]; | |
3785 | diag = false; | |
3786 | } | |
3787 | else /* Ambiguous - guess with a preference to non-AVX512VL forms. */ | |
3788 | types = &t->operand_types[op]; | |
3789 | ||
3790 | if (types->bitfield.zmmword) | |
3791 | bytes = 64; | |
3792 | else if (types->bitfield.ymmword) | |
3793 | bytes = 32; | |
3794 | else | |
3795 | bytes = 16; | |
3796 | ||
3797 | if (diag) | |
3798 | as_warn (_("ambiguous broadcast for `%s', using %u-bit form"), | |
3799 | t->name, bytes * 8); | |
3800 | ||
3801 | return bytes; | |
3802 | } | |
3803 | ||
43234a1e L |
3804 | /* Build the EVEX prefix. */ |
3805 | ||
3806 | static void | |
3807 | build_evex_prefix (void) | |
3808 | { | |
35648716 | 3809 | unsigned int register_specifier, w; |
43234a1e L |
3810 | rex_byte vrex_used = 0; |
3811 | ||
3812 | /* Check register specifier. */ | |
3813 | if (i.vex.register_specifier) | |
3814 | { | |
3815 | gas_assert ((i.vrex & REX_X) == 0); | |
3816 | ||
3817 | register_specifier = i.vex.register_specifier->reg_num; | |
3818 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3819 | register_specifier += 8; | |
3820 | /* The upper 16 registers are encoded in the fourth byte of the | |
3821 | EVEX prefix. */ | |
3822 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3823 | i.vex.bytes[3] = 0x8; | |
3824 | register_specifier = ~register_specifier & 0xf; | |
3825 | } | |
3826 | else | |
3827 | { | |
3828 | register_specifier = 0xf; | |
3829 | ||
3830 | /* Encode upper 16 vector index register in the fourth byte of | |
3831 | the EVEX prefix. */ | |
3832 | if (!(i.vrex & REX_X)) | |
3833 | i.vex.bytes[3] = 0x8; | |
3834 | else | |
3835 | vrex_used |= REX_X; | |
3836 | } | |
3837 | ||
43234a1e L |
3838 | /* 4 byte EVEX prefix. */ |
3839 | i.vex.length = 4; | |
3840 | i.vex.bytes[0] = 0x62; | |
3841 | ||
43234a1e L |
3842 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
3843 | bits from REX. */ | |
441f6aca | 3844 | gas_assert (i.tm.opcode_modifier.opcodespace >= SPACE_0F); |
0cc78721 | 3845 | gas_assert (i.tm.opcode_modifier.opcodespace <= SPACE_EVEXMAP6); |
441f6aca | 3846 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_modifier.opcodespace; |
43234a1e L |
3847 | |
3848 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3849 | REX_R bit in VREX. */ | |
3850 | if (!(i.vrex & REX_R)) | |
3851 | i.vex.bytes[1] |= 0x10; | |
3852 | else | |
3853 | vrex_used |= REX_R; | |
3854 | ||
3855 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3856 | { | |
3857 | /* When all operands are registers, the REX_X bit in REX is not | |
3858 | used. We reuse it to encode the upper 16 registers, which is | |
3859 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3860 | as 1's compliment. */ | |
3861 | if ((i.vrex & REX_B)) | |
3862 | { | |
3863 | vrex_used |= REX_B; | |
3864 | i.vex.bytes[1] &= ~0x40; | |
3865 | } | |
3866 | } | |
3867 | ||
3868 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3869 | i.vrex &= ~vrex_used; | |
3870 | gas_assert (i.vrex == 0); | |
3871 | ||
6865c043 L |
3872 | /* Check the REX.W bit and VEXW. */ |
3873 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3874 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3875 | else if (i.tm.opcode_modifier.vexw) | |
3876 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3877 | else | |
931d03b7 | 3878 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 3879 | |
43234a1e | 3880 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
3881 | i.vex.bytes[2] = ((w << 7) |
3882 | | (register_specifier << 3) | |
3883 | | 4 /* Encode the U bit. */ | |
3884 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
3885 | |
3886 | /* The fourth byte of the EVEX prefix. */ | |
3887 | /* The zeroing-masking bit. */ | |
6225c532 | 3888 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
3889 | i.vex.bytes[3] |= 0x80; |
3890 | ||
3891 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 3892 | if (i.rounding.type == rc_none) |
43234a1e L |
3893 | { |
3894 | /* Encode the vector length. */ | |
3895 | unsigned int vec_length; | |
3896 | ||
e771e7c9 JB |
3897 | if (!i.tm.opcode_modifier.evex |
3898 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3899 | { | |
56522fc5 | 3900 | unsigned int op; |
e771e7c9 | 3901 | |
c7213af9 L |
3902 | /* Determine vector length from the last multi-length vector |
3903 | operand. */ | |
56522fc5 | 3904 | for (op = i.operands; op--;) |
e771e7c9 JB |
3905 | if (i.tm.operand_types[op].bitfield.xmmword |
3906 | + i.tm.operand_types[op].bitfield.ymmword | |
3907 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3908 | { | |
3909 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3910 | { |
3911 | i.tm.opcode_modifier.evex = EVEX512; | |
3912 | break; | |
3913 | } | |
e771e7c9 | 3914 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3915 | { |
3916 | i.tm.opcode_modifier.evex = EVEX256; | |
3917 | break; | |
3918 | } | |
e771e7c9 | 3919 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3920 | { |
3921 | i.tm.opcode_modifier.evex = EVEX128; | |
3922 | break; | |
3923 | } | |
a5748e0d | 3924 | else if (i.broadcast.bytes && op == i.broadcast.operand) |
625cbd7a | 3925 | { |
a5748e0d | 3926 | switch (get_broadcast_bytes (&i.tm, true)) |
625cbd7a JB |
3927 | { |
3928 | case 64: | |
3929 | i.tm.opcode_modifier.evex = EVEX512; | |
3930 | break; | |
3931 | case 32: | |
3932 | i.tm.opcode_modifier.evex = EVEX256; | |
3933 | break; | |
3934 | case 16: | |
3935 | i.tm.opcode_modifier.evex = EVEX128; | |
3936 | break; | |
3937 | default: | |
c7213af9 | 3938 | abort (); |
625cbd7a | 3939 | } |
c7213af9 | 3940 | break; |
625cbd7a | 3941 | } |
e771e7c9 | 3942 | } |
c7213af9 | 3943 | |
56522fc5 | 3944 | if (op >= MAX_OPERANDS) |
c7213af9 | 3945 | abort (); |
e771e7c9 JB |
3946 | } |
3947 | ||
43234a1e L |
3948 | switch (i.tm.opcode_modifier.evex) |
3949 | { | |
3950 | case EVEXLIG: /* LL' is ignored */ | |
3951 | vec_length = evexlig << 5; | |
3952 | break; | |
3953 | case EVEX128: | |
3954 | vec_length = 0 << 5; | |
3955 | break; | |
3956 | case EVEX256: | |
3957 | vec_length = 1 << 5; | |
3958 | break; | |
3959 | case EVEX512: | |
3960 | vec_length = 2 << 5; | |
3961 | break; | |
3962 | default: | |
3963 | abort (); | |
3964 | break; | |
3965 | } | |
3966 | i.vex.bytes[3] |= vec_length; | |
3967 | /* Encode the broadcast bit. */ | |
a5748e0d | 3968 | if (i.broadcast.bytes) |
43234a1e L |
3969 | i.vex.bytes[3] |= 0x10; |
3970 | } | |
ca5312a2 JB |
3971 | else if (i.rounding.type != saeonly) |
3972 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 3973 | else |
ca5312a2 | 3974 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 3975 | |
6225c532 JB |
3976 | if (i.mask.reg) |
3977 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
3978 | } |
3979 | ||
65da13b5 L |
3980 | static void |
3981 | process_immext (void) | |
3982 | { | |
3983 | expressionS *exp; | |
3984 | ||
c0f3af97 | 3985 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
3986 | which is coded in the same place as an 8-bit immediate field |
3987 | would be. Here we fake an 8-bit immediate operand from the | |
3988 | opcode suffix stored in tm.extension_opcode. | |
3989 | ||
c1e679ec | 3990 | AVX instructions also use this encoding, for some of |
c0f3af97 | 3991 | 3 argument instructions. */ |
65da13b5 | 3992 | |
43234a1e | 3993 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 3994 | && (i.operands <= 2 |
7a8655d2 | 3995 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 3996 | && i.operands <= 4))); |
65da13b5 L |
3997 | |
3998 | exp = &im_expressions[i.imm_operands++]; | |
3999 | i.op[i.operands].imms = exp; | |
be1643ff | 4000 | i.types[i.operands].bitfield.imm8 = 1; |
65da13b5 L |
4001 | i.operands++; |
4002 | exp->X_op = O_constant; | |
4003 | exp->X_add_number = i.tm.extension_opcode; | |
4004 | i.tm.extension_opcode = None; | |
4005 | } | |
4006 | ||
42164a71 L |
4007 | |
4008 | static int | |
4009 | check_hle (void) | |
4010 | { | |
742732c7 | 4011 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4012 | { |
4013 | default: | |
4014 | abort (); | |
742732c7 JB |
4015 | case PrefixLock: |
4016 | case PrefixNone: | |
4017 | case PrefixNoTrack: | |
4018 | case PrefixRep: | |
165de32a L |
4019 | as_bad (_("invalid instruction `%s' after `%s'"), |
4020 | i.tm.name, i.hle_prefix); | |
42164a71 | 4021 | return 0; |
742732c7 | 4022 | case PrefixHLELock: |
42164a71 L |
4023 | if (i.prefix[LOCK_PREFIX]) |
4024 | return 1; | |
165de32a | 4025 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4026 | return 0; |
742732c7 | 4027 | case PrefixHLEAny: |
42164a71 | 4028 | return 1; |
742732c7 | 4029 | case PrefixHLERelease: |
42164a71 L |
4030 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4031 | { | |
4032 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4033 | i.tm.name); | |
4034 | return 0; | |
4035 | } | |
8dc0818e | 4036 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4037 | { |
4038 | as_bad (_("memory destination needed for instruction `%s'" | |
4039 | " after `xrelease'"), i.tm.name); | |
4040 | return 0; | |
4041 | } | |
4042 | return 1; | |
4043 | } | |
4044 | } | |
4045 | ||
c8480b58 L |
4046 | /* Encode aligned vector move as unaligned vector move. */ |
4047 | ||
4048 | static void | |
4049 | encode_with_unaligned_vector_move (void) | |
4050 | { | |
4051 | switch (i.tm.base_opcode) | |
4052 | { | |
b3a9fe6f L |
4053 | case 0x28: /* Load instructions. */ |
4054 | case 0x29: /* Store instructions. */ | |
c8480b58 L |
4055 | /* movaps/movapd/vmovaps/vmovapd. */ |
4056 | if (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
4057 | && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66) | |
b3a9fe6f | 4058 | i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1); |
c8480b58 | 4059 | break; |
b3a9fe6f L |
4060 | case 0x6f: /* Load instructions. */ |
4061 | case 0x7f: /* Store instructions. */ | |
c8480b58 L |
4062 | /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */ |
4063 | if (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
4064 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66) | |
4065 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
4066 | break; | |
4067 | default: | |
4068 | break; | |
4069 | } | |
4070 | } | |
4071 | ||
b6f8c7c4 L |
4072 | /* Try the shortest encoding by shortening operand size. */ |
4073 | ||
4074 | static void | |
4075 | optimize_encoding (void) | |
4076 | { | |
a0a1771e | 4077 | unsigned int j; |
b6f8c7c4 | 4078 | |
fe134c65 JB |
4079 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
4080 | && i.tm.base_opcode == 0x8d) | |
4081 | { | |
4082 | /* Optimize: -O: | |
4083 | lea symbol, %rN -> mov $symbol, %rN | |
4084 | lea (%rM), %rN -> mov %rM, %rN | |
4085 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4086 | ||
4087 | and in 32-bit mode for 16-bit addressing | |
4088 | ||
4089 | lea (%rM), %rN -> movzx %rM, %rN | |
4090 | ||
4091 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4092 | 32-bit (or less) destination. | |
4093 | */ | |
4094 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4095 | { | |
4096 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4097 | i.tm.opcode_modifier.size = SIZE32; | |
4098 | i.prefix[ADDR_PREFIX] = 0; | |
4099 | } | |
4100 | ||
4101 | if (!i.index_reg && !i.base_reg) | |
4102 | { | |
4103 | /* Handle: | |
4104 | lea symbol, %rN -> mov $symbol, %rN | |
4105 | */ | |
4106 | if (flag_code == CODE_64BIT) | |
4107 | { | |
4108 | /* Don't transform a relocation to a 16-bit one. */ | |
4109 | if (i.op[0].disps | |
4110 | && i.op[0].disps->X_op != O_constant | |
4111 | && i.op[1].regs->reg_type.bitfield.word) | |
4112 | return; | |
4113 | ||
4114 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4115 | || i.tm.opcode_modifier.size == SIZE32) | |
4116 | { | |
4117 | i.tm.base_opcode = 0xb8; | |
4118 | i.tm.opcode_modifier.modrm = 0; | |
4119 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4120 | i.types[0].bitfield.imm32 = 1; | |
4121 | else | |
4122 | { | |
4123 | i.tm.opcode_modifier.size = SIZE16; | |
4124 | i.types[0].bitfield.imm16 = 1; | |
4125 | } | |
4126 | } | |
4127 | else | |
4128 | { | |
4129 | /* Subject to further optimization below. */ | |
4130 | i.tm.base_opcode = 0xc7; | |
4131 | i.tm.extension_opcode = 0; | |
4132 | i.types[0].bitfield.imm32s = 1; | |
4133 | i.types[0].bitfield.baseindex = 0; | |
4134 | } | |
4135 | } | |
4136 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4137 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4138 | even couldn't express the relocation correctly. */ | |
4139 | else if (i.op[0].disps | |
4140 | && i.op[0].disps->X_op != O_constant | |
4141 | && ((!i.prefix[ADDR_PREFIX]) | |
4142 | != (flag_code == CODE_32BIT | |
4143 | ? i.op[1].regs->reg_type.bitfield.dword | |
4144 | : i.op[1].regs->reg_type.bitfield.word))) | |
4145 | return; | |
7772f168 JB |
4146 | /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit |
4147 | destination is going to grow encoding size. */ | |
4148 | else if (flag_code == CODE_16BIT | |
4149 | && (optimize <= 1 || optimize_for_space) | |
4150 | && !i.prefix[ADDR_PREFIX] | |
4151 | && i.op[1].regs->reg_type.bitfield.dword) | |
4152 | return; | |
fe134c65 JB |
4153 | else |
4154 | { | |
4155 | i.tm.base_opcode = 0xb8; | |
4156 | i.tm.opcode_modifier.modrm = 0; | |
4157 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4158 | i.types[0].bitfield.imm32 = 1; | |
4159 | else | |
4160 | i.types[0].bitfield.imm16 = 1; | |
4161 | ||
4162 | if (i.op[0].disps | |
4163 | && i.op[0].disps->X_op == O_constant | |
4164 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4165 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4166 | GCC 5. */ | |
4167 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4168 | i.op[0].disps->X_add_number &= 0xffff; |
4169 | } | |
4170 | ||
4171 | i.tm.operand_types[0] = i.types[0]; | |
4172 | i.imm_operands = 1; | |
4173 | if (!i.op[0].imms) | |
4174 | { | |
4175 | i.op[0].imms = &im_expressions[0]; | |
4176 | i.op[0].imms->X_op = O_absent; | |
4177 | } | |
4178 | } | |
4179 | else if (i.op[0].disps | |
4180 | && (i.op[0].disps->X_op != O_constant | |
4181 | || i.op[0].disps->X_add_number)) | |
4182 | return; | |
4183 | else | |
4184 | { | |
4185 | /* Handle: | |
4186 | lea (%rM), %rN -> mov %rM, %rN | |
4187 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4188 | lea (%rM), %rN -> movzx %rM, %rN | |
4189 | */ | |
4190 | const reg_entry *addr_reg; | |
4191 | ||
4192 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4193 | addr_reg = i.base_reg; | |
4194 | else if (!i.base_reg | |
4195 | && i.index_reg->reg_num != RegIZ | |
4196 | && !i.log2_scale_factor) | |
4197 | addr_reg = i.index_reg; | |
4198 | else | |
4199 | return; | |
4200 | ||
4201 | if (addr_reg->reg_type.bitfield.word | |
4202 | && i.op[1].regs->reg_type.bitfield.dword) | |
4203 | { | |
4204 | if (flag_code != CODE_32BIT) | |
4205 | return; | |
4206 | i.tm.opcode_modifier.opcodespace = SPACE_0F; | |
4207 | i.tm.base_opcode = 0xb7; | |
4208 | } | |
4209 | else | |
4210 | i.tm.base_opcode = 0x8b; | |
4211 | ||
4212 | if (addr_reg->reg_type.bitfield.dword | |
4213 | && i.op[1].regs->reg_type.bitfield.qword) | |
4214 | i.tm.opcode_modifier.size = SIZE32; | |
4215 | ||
4216 | i.op[0].regs = addr_reg; | |
4217 | i.reg_operands = 2; | |
4218 | } | |
4219 | ||
4220 | i.mem_operands = 0; | |
4221 | i.disp_operands = 0; | |
4222 | i.prefix[ADDR_PREFIX] = 0; | |
4223 | i.prefix[SEG_PREFIX] = 0; | |
4224 | i.seg[0] = NULL; | |
4225 | } | |
4226 | ||
b6f8c7c4 | 4227 | if (optimize_for_space |
389d00a5 | 4228 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
b6f8c7c4 L |
4229 | && i.reg_operands == 1 |
4230 | && i.imm_operands == 1 | |
4231 | && !i.types[1].bitfield.byte | |
4232 | && i.op[0].imms->X_op == O_constant | |
4233 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4234 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4235 | || (i.tm.base_opcode == 0xf6 |
4236 | && i.tm.extension_opcode == 0x0))) | |
4237 | { | |
4238 | /* Optimize: -Os: | |
4239 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4240 | */ | |
4241 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4242 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4243 | { | |
4244 | i.types[1].bitfield.byte = 1; | |
4245 | /* Ignore the suffix. */ | |
4246 | i.suffix = 0; | |
7697afb6 JB |
4247 | /* Convert to byte registers. */ |
4248 | if (i.types[1].bitfield.word) | |
4249 | j = 16; | |
4250 | else if (i.types[1].bitfield.dword) | |
4251 | j = 32; | |
4252 | else | |
4253 | j = 48; | |
4254 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4255 | j += 8; | |
4256 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4257 | } |
4258 | } | |
4259 | else if (flag_code == CODE_64BIT | |
389d00a5 | 4260 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
d3d50934 L |
4261 | && ((i.types[1].bitfield.qword |
4262 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4263 | && i.imm_operands == 1 |
4264 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4265 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4266 | && i.tm.extension_opcode == None |
4267 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4268 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4269 | && ((i.tm.base_opcode == 0x24 |
4270 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4271 | || (i.tm.base_opcode == 0x80 |
4272 | && i.tm.extension_opcode == 0x4) | |
4273 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4274 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4275 | && i.tm.extension_opcode == 0x0))) |
4276 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4277 | && i.tm.base_opcode == 0x83 | |
4278 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4279 | || (i.types[0].bitfield.qword |
4280 | && ((i.reg_operands == 2 | |
4281 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4282 | && (i.tm.base_opcode == 0x30 |
4283 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4284 | || (i.reg_operands == 1 |
4285 | && i.operands == 1 | |
72aea328 | 4286 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4287 | { |
4288 | /* Optimize: -O: | |
4289 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4290 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4291 | testq $imm31, %r64 -> testl $imm31, %r32 |
4292 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4293 | subq %r64, %r64 -> subl %r32, %r32 | |
4294 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4295 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4296 | */ | |
4297 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4298 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4299 | { |
4300 | /* Handle | |
4301 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4302 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4303 | */ | |
4304 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4305 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4306 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4307 | i.types[0].bitfield.imm32 = 1; | |
4308 | i.types[0].bitfield.imm32s = 0; | |
4309 | i.types[0].bitfield.imm64 = 0; | |
4310 | i.types[1].bitfield.dword = 1; | |
4311 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4312 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4313 | { |
4314 | /* Handle | |
4315 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4316 | */ | |
507916b8 | 4317 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4318 | i.tm.extension_opcode = None; |
507916b8 | 4319 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4320 | i.tm.opcode_modifier.modrm = 0; |
4321 | } | |
4322 | } | |
4323 | } | |
5641ec01 JB |
4324 | else if (optimize > 1 |
4325 | && !optimize_for_space | |
389d00a5 | 4326 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
5641ec01 JB |
4327 | && i.reg_operands == 2 |
4328 | && i.op[0].regs == i.op[1].regs | |
4329 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4330 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4331 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4332 | { | |
4333 | /* Optimize: -O2: | |
4334 | andb %rN, %rN -> testb %rN, %rN | |
4335 | andw %rN, %rN -> testw %rN, %rN | |
4336 | andq %rN, %rN -> testq %rN, %rN | |
4337 | orb %rN, %rN -> testb %rN, %rN | |
4338 | orw %rN, %rN -> testw %rN, %rN | |
4339 | orq %rN, %rN -> testq %rN, %rN | |
4340 | ||
4341 | and outside of 64-bit mode | |
4342 | ||
4343 | andl %rN, %rN -> testl %rN, %rN | |
4344 | orl %rN, %rN -> testl %rN, %rN | |
4345 | */ | |
4346 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4347 | } | |
99112332 | 4348 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4349 | && i.op[0].regs == i.op[1].regs |
4350 | && !i.types[2].bitfield.xmmword | |
4351 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4352 | || ((!i.mask.reg || i.mask.zeroing) |
e771e7c9 | 4353 | && is_evex_encoding (&i.tm) |
80c34c38 | 4354 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4355 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4356 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4357 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4358 | && i.types[2].bitfield.ymmword)))) |
5844ccaa JB |
4359 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
4360 | && ((i.tm.base_opcode | 2) == 0x57 | |
4361 | || i.tm.base_opcode == 0xdf | |
4362 | || i.tm.base_opcode == 0xef | |
4363 | || (i.tm.base_opcode | 3) == 0xfb | |
4364 | || i.tm.base_opcode == 0x42 | |
4365 | || i.tm.base_opcode == 0x47)) | |
b6f8c7c4 | 4366 | { |
99112332 | 4367 | /* Optimize: -O1: |
8305403a L |
4368 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4369 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4370 | EVEX VOP %zmmM, %zmmM, %zmmN |
4371 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4372 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4373 | EVEX VOP %ymmM, %ymmM, %ymmN |
4374 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4375 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4376 | VEX VOP %ymmM, %ymmM, %ymmN |
4377 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4378 | VOP, one of vpandn and vpxor: | |
4379 | VEX VOP %ymmM, %ymmM, %ymmN | |
4380 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4381 | VOP, one of vpandnd and vpandnq: | |
4382 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4383 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4384 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4385 | EVEX VOP %ymmM, %ymmM, %ymmN |
4386 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4387 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4388 | VOP, one of vpxord and vpxorq: |
4389 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4390 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4391 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4392 | EVEX VOP %ymmM, %ymmM, %ymmN |
4393 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4394 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4395 | VOP, one of kxord and kxorq: |
4396 | VEX VOP %kM, %kM, %kN | |
4397 | -> VEX kxorw %kM, %kM, %kN | |
4398 | VOP, one of kandnd and kandnq: | |
4399 | VEX VOP %kM, %kM, %kN | |
4400 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4401 | */ |
e771e7c9 | 4402 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4403 | { |
7b1d7ca1 | 4404 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4405 | { |
4406 | i.tm.opcode_modifier.vex = VEX128; | |
4407 | i.tm.opcode_modifier.vexw = VEXW0; | |
4408 | i.tm.opcode_modifier.evex = 0; | |
4409 | } | |
7b1d7ca1 | 4410 | else if (optimize > 1) |
dd22218c L |
4411 | i.tm.opcode_modifier.evex = EVEX128; |
4412 | else | |
4413 | return; | |
b6f8c7c4 | 4414 | } |
f74a6307 | 4415 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4416 | { |
35648716 | 4417 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4418 | i.tm.opcode_modifier.vexw = VEXW0; |
4419 | } | |
b6f8c7c4 L |
4420 | else |
4421 | i.tm.opcode_modifier.vex = VEX128; | |
4422 | ||
4423 | if (i.tm.opcode_modifier.vex) | |
4424 | for (j = 0; j < 3; j++) | |
4425 | { | |
4426 | i.types[j].bitfield.xmmword = 1; | |
4427 | i.types[j].bitfield.ymmword = 0; | |
4428 | } | |
4429 | } | |
392a5972 | 4430 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4431 | && !i.types[0].bitfield.zmmword |
392a5972 | 4432 | && !i.types[1].bitfield.zmmword |
6225c532 | 4433 | && !i.mask.reg |
a5748e0d | 4434 | && !i.broadcast.bytes |
97ed31ae | 4435 | && is_evex_encoding (&i.tm) |
35648716 JB |
4436 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4437 | || (i.tm.base_opcode & ~4) == 0xdb | |
4438 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4439 | && i.tm.extension_opcode == None) |
4440 | { | |
4441 | /* Optimize: -O1: | |
4442 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4443 | vmovdqu32 and vmovdqu64: | |
4444 | EVEX VOP %xmmM, %xmmN | |
4445 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4446 | EVEX VOP %ymmM, %ymmN | |
4447 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4448 | EVEX VOP %xmmM, mem | |
4449 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4450 | EVEX VOP %ymmM, mem | |
4451 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4452 | EVEX VOP mem, %xmmN | |
4453 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4454 | EVEX VOP mem, %ymmN | |
4455 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4456 | VOP, one of vpand, vpandn, vpor, vpxor: |
4457 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4458 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4459 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4460 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4461 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4462 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4463 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4464 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4465 | */ |
a0a1771e | 4466 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4467 | if (operand_type_check (i.types[j], disp) |
4468 | && i.op[j].disps->X_op == O_constant) | |
4469 | { | |
4470 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4471 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4472 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4473 | int evex_disp8, vex_disp8; | |
4474 | unsigned int memshift = i.memshift; | |
4475 | offsetT n = i.op[j].disps->X_add_number; | |
4476 | ||
4477 | evex_disp8 = fits_in_disp8 (n); | |
4478 | i.memshift = 0; | |
4479 | vex_disp8 = fits_in_disp8 (n); | |
4480 | if (evex_disp8 != vex_disp8) | |
4481 | { | |
4482 | i.memshift = memshift; | |
4483 | return; | |
4484 | } | |
4485 | ||
4486 | i.types[j].bitfield.disp8 = vex_disp8; | |
4487 | break; | |
4488 | } | |
35648716 JB |
4489 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4490 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4491 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4492 | i.tm.opcode_modifier.vex |
4493 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4494 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4495 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4496 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4497 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4498 | i.tm.opcode_modifier.evex = 0; |
4499 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4500 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4501 | i.tm.opcode_modifier.disp8memshift = 0; |
4502 | i.memshift = 0; | |
a0a1771e JB |
4503 | if (j < i.operands) |
4504 | i.types[j].bitfield.disp8 | |
4505 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4506 | } |
b6f8c7c4 L |
4507 | } |
4508 | ||
ae531041 L |
4509 | /* Return non-zero for load instruction. */ |
4510 | ||
4511 | static int | |
4512 | load_insn_p (void) | |
4513 | { | |
4514 | unsigned int dest; | |
4515 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4516 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4517 | ||
4518 | if (!any_vex_p) | |
4519 | { | |
ef07be45 CL |
4520 | /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, |
4521 | bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ | |
a09f656b | 4522 | if (i.tm.opcode_modifier.anysize) |
ae531041 L |
4523 | return 0; |
4524 | ||
389d00a5 JB |
4525 | /* pop. */ |
4526 | if (strcmp (i.tm.name, "pop") == 0) | |
4527 | return 1; | |
4528 | } | |
4529 | ||
4530 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE) | |
4531 | { | |
4532 | /* popf, popa. */ | |
4533 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 4534 | || i.tm.base_opcode == 0x61) |
ae531041 L |
4535 | return 1; |
4536 | ||
4537 | /* movs, cmps, lods, scas. */ | |
4538 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4539 | return 1; | |
4540 | ||
a09f656b | 4541 | /* outs, xlatb. */ |
4542 | if (base_opcode == 0x6f | |
4543 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4544 | return 1; |
a09f656b | 4545 | /* NB: For AMD-specific insns with implicit memory operands, |
4546 | they're intentionally not covered. */ | |
ae531041 L |
4547 | } |
4548 | ||
4549 | /* No memory operand. */ | |
4550 | if (!i.mem_operands) | |
4551 | return 0; | |
4552 | ||
4553 | if (any_vex_p) | |
4554 | { | |
4555 | /* vldmxcsr. */ | |
4556 | if (i.tm.base_opcode == 0xae | |
4557 | && i.tm.opcode_modifier.vex | |
441f6aca | 4558 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
35648716 | 4559 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE |
ae531041 L |
4560 | && i.tm.extension_opcode == 2) |
4561 | return 1; | |
4562 | } | |
389d00a5 | 4563 | else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE) |
ae531041 L |
4564 | { |
4565 | /* test, not, neg, mul, imul, div, idiv. */ | |
4566 | if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7) | |
4567 | && i.tm.extension_opcode != 1) | |
4568 | return 1; | |
4569 | ||
4570 | /* inc, dec. */ | |
4571 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
4572 | return 1; | |
4573 | ||
4574 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
4575 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
4576 | return 1; | |
4577 | ||
ae531041 L |
4578 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
4579 | if ((base_opcode == 0xc1 | |
4580 | || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3)) | |
4581 | && i.tm.extension_opcode != 6) | |
4582 | return 1; | |
4583 | ||
ae531041 | 4584 | /* Check for x87 instructions. */ |
389d00a5 | 4585 | if (base_opcode >= 0xd8 && base_opcode <= 0xdf) |
ae531041 L |
4586 | { |
4587 | /* Skip fst, fstp, fstenv, fstcw. */ | |
4588 | if (i.tm.base_opcode == 0xd9 | |
4589 | && (i.tm.extension_opcode == 2 | |
4590 | || i.tm.extension_opcode == 3 | |
4591 | || i.tm.extension_opcode == 6 | |
4592 | || i.tm.extension_opcode == 7)) | |
4593 | return 0; | |
4594 | ||
4595 | /* Skip fisttp, fist, fistp, fstp. */ | |
4596 | if (i.tm.base_opcode == 0xdb | |
4597 | && (i.tm.extension_opcode == 1 | |
4598 | || i.tm.extension_opcode == 2 | |
4599 | || i.tm.extension_opcode == 3 | |
4600 | || i.tm.extension_opcode == 7)) | |
4601 | return 0; | |
4602 | ||
4603 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
4604 | if (i.tm.base_opcode == 0xdd | |
4605 | && (i.tm.extension_opcode == 1 | |
4606 | || i.tm.extension_opcode == 2 | |
4607 | || i.tm.extension_opcode == 3 | |
4608 | || i.tm.extension_opcode == 6 | |
4609 | || i.tm.extension_opcode == 7)) | |
4610 | return 0; | |
4611 | ||
4612 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
4613 | if (i.tm.base_opcode == 0xdf | |
4614 | && (i.tm.extension_opcode == 1 | |
4615 | || i.tm.extension_opcode == 2 | |
4616 | || i.tm.extension_opcode == 3 | |
4617 | || i.tm.extension_opcode == 6 | |
4618 | || i.tm.extension_opcode == 7)) | |
4619 | return 0; | |
4620 | ||
4621 | return 1; | |
4622 | } | |
4623 | } | |
389d00a5 JB |
4624 | else if (i.tm.opcode_modifier.opcodespace == SPACE_0F) |
4625 | { | |
4626 | /* bt, bts, btr, btc. */ | |
4627 | if (i.tm.base_opcode == 0xba | |
4628 | && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7)) | |
4629 | return 1; | |
4630 | ||
4631 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
4632 | if (i.tm.base_opcode == 0xc7 | |
4633 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
4634 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
4635 | || i.tm.extension_opcode == 6)) | |
4636 | return 1; | |
4637 | ||
4638 | /* fxrstor, ldmxcsr, xrstor. */ | |
4639 | if (i.tm.base_opcode == 0xae | |
4640 | && (i.tm.extension_opcode == 1 | |
4641 | || i.tm.extension_opcode == 2 | |
4642 | || i.tm.extension_opcode == 5)) | |
4643 | return 1; | |
4644 | ||
4645 | /* lgdt, lidt, lmsw. */ | |
4646 | if (i.tm.base_opcode == 0x01 | |
4647 | && (i.tm.extension_opcode == 2 | |
4648 | || i.tm.extension_opcode == 3 | |
4649 | || i.tm.extension_opcode == 6)) | |
4650 | return 1; | |
4651 | } | |
ae531041 L |
4652 | |
4653 | dest = i.operands - 1; | |
4654 | ||
4655 | /* Check fake imm8 operand and 3 source operands. */ | |
4656 | if ((i.tm.opcode_modifier.immext | |
4657 | || i.tm.opcode_modifier.vexsources == VEX3SOURCES) | |
4658 | && i.types[dest].bitfield.imm8) | |
4659 | dest--; | |
4660 | ||
389d00a5 JB |
4661 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
4662 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE | |
ae531041 L |
4663 | && (base_opcode == 0x1 |
4664 | || base_opcode == 0x9 | |
4665 | || base_opcode == 0x11 | |
4666 | || base_opcode == 0x19 | |
4667 | || base_opcode == 0x21 | |
4668 | || base_opcode == 0x29 | |
4669 | || base_opcode == 0x31 | |
4670 | || base_opcode == 0x39 | |
389d00a5 JB |
4671 | || (base_opcode | 2) == 0x87)) |
4672 | return 1; | |
4673 | ||
4674 | /* xadd. */ | |
4675 | if (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
4676 | && base_opcode == 0xc1) | |
ae531041 L |
4677 | return 1; |
4678 | ||
4679 | /* Check for load instruction. */ | |
4680 | return (i.types[dest].bitfield.class != ClassNone | |
4681 | || i.types[dest].bitfield.instance == Accum); | |
4682 | } | |
4683 | ||
4684 | /* Output lfence, 0xfaee8, after instruction. */ | |
4685 | ||
4686 | static void | |
4687 | insert_lfence_after (void) | |
4688 | { | |
4689 | if (lfence_after_load && load_insn_p ()) | |
4690 | { | |
a09f656b | 4691 | /* There are also two REP string instructions that require |
4692 | special treatment. Specifically, the compare string (CMPS) | |
4693 | and scan string (SCAS) instructions set EFLAGS in a manner | |
4694 | that depends on the data being compared/scanned. When used | |
4695 | with a REP prefix, the number of iterations may therefore | |
4696 | vary depending on this data. If the data is a program secret | |
4697 | chosen by the adversary using an LVI method, | |
4698 | then this data-dependent behavior may leak some aspect | |
4699 | of the secret. */ | |
4700 | if (((i.tm.base_opcode | 0x1) == 0xa7 | |
4701 | || (i.tm.base_opcode | 0x1) == 0xaf) | |
4702 | && i.prefix[REP_PREFIX]) | |
4703 | { | |
4704 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
4705 | i.tm.name); | |
4706 | } | |
ae531041 L |
4707 | char *p = frag_more (3); |
4708 | *p++ = 0xf; | |
4709 | *p++ = 0xae; | |
4710 | *p = 0xe8; | |
4711 | } | |
4712 | } | |
4713 | ||
4714 | /* Output lfence, 0xfaee8, before instruction. */ | |
4715 | ||
4716 | static void | |
4717 | insert_lfence_before (void) | |
4718 | { | |
4719 | char *p; | |
4720 | ||
389d00a5 | 4721 | if (i.tm.opcode_modifier.opcodespace != SPACE_BASE) |
ae531041 L |
4722 | return; |
4723 | ||
4724 | if (i.tm.base_opcode == 0xff | |
4725 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
4726 | { | |
4727 | /* Insert lfence before indirect branch if needed. */ | |
4728 | ||
4729 | if (lfence_before_indirect_branch == lfence_branch_none) | |
4730 | return; | |
4731 | ||
4732 | if (i.operands != 1) | |
4733 | abort (); | |
4734 | ||
4735 | if (i.reg_operands == 1) | |
4736 | { | |
4737 | /* Indirect branch via register. Don't insert lfence with | |
4738 | -mlfence-after-load=yes. */ | |
4739 | if (lfence_after_load | |
4740 | || lfence_before_indirect_branch == lfence_branch_memory) | |
4741 | return; | |
4742 | } | |
4743 | else if (i.mem_operands == 1 | |
4744 | && lfence_before_indirect_branch != lfence_branch_register) | |
4745 | { | |
4746 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
4747 | i.tm.name); | |
4748 | return; | |
4749 | } | |
4750 | else | |
4751 | return; | |
4752 | ||
4753 | if (last_insn.kind != last_insn_other | |
4754 | && last_insn.seg == now_seg) | |
4755 | { | |
4756 | as_warn_where (last_insn.file, last_insn.line, | |
4757 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), | |
4758 | last_insn.name, i.tm.name); | |
4759 | return; | |
4760 | } | |
4761 | ||
4762 | p = frag_more (3); | |
4763 | *p++ = 0xf; | |
4764 | *p++ = 0xae; | |
4765 | *p = 0xe8; | |
4766 | return; | |
4767 | } | |
4768 | ||
503648e4 | 4769 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 L |
4770 | if (lfence_before_ret != lfence_before_ret_none |
4771 | && (i.tm.base_opcode == 0xc2 | |
503648e4 | 4772 | || i.tm.base_opcode == 0xc3)) |
ae531041 L |
4773 | { |
4774 | if (last_insn.kind != last_insn_other | |
4775 | && last_insn.seg == now_seg) | |
4776 | { | |
4777 | as_warn_where (last_insn.file, last_insn.line, | |
4778 | _("`%s` skips -mlfence-before-ret on `%s`"), | |
4779 | last_insn.name, i.tm.name); | |
4780 | return; | |
4781 | } | |
a09f656b | 4782 | |
a09f656b | 4783 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 4784 | char prefix = flag_code == CODE_64BIT |
4785 | ? 0x48 | |
4786 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 4787 | |
4788 | if (lfence_before_ret == lfence_before_ret_not) | |
4789 | { | |
4790 | /* not: 0xf71424, may add prefix | |
4791 | for operand size override or 64-bit code. */ | |
4792 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
4793 | if (prefix) | |
4794 | *p++ = prefix; | |
ae531041 L |
4795 | *p++ = 0xf7; |
4796 | *p++ = 0x14; | |
4797 | *p++ = 0x24; | |
a09f656b | 4798 | if (prefix) |
4799 | *p++ = prefix; | |
ae531041 L |
4800 | *p++ = 0xf7; |
4801 | *p++ = 0x14; | |
4802 | *p++ = 0x24; | |
4803 | } | |
a09f656b | 4804 | else |
4805 | { | |
4806 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
4807 | if (prefix) | |
4808 | *p++ = prefix; | |
4809 | if (lfence_before_ret == lfence_before_ret_or) | |
4810 | { | |
4811 | /* or: 0x830c2400, may add prefix | |
4812 | for operand size override or 64-bit code. */ | |
4813 | *p++ = 0x83; | |
4814 | *p++ = 0x0c; | |
4815 | } | |
4816 | else | |
4817 | { | |
4818 | /* shl: 0xc1242400, may add prefix | |
4819 | for operand size override or 64-bit code. */ | |
4820 | *p++ = 0xc1; | |
4821 | *p++ = 0x24; | |
4822 | } | |
4823 | ||
4824 | *p++ = 0x24; | |
4825 | *p++ = 0x0; | |
4826 | } | |
4827 | ||
ae531041 L |
4828 | *p++ = 0xf; |
4829 | *p++ = 0xae; | |
4830 | *p = 0xe8; | |
4831 | } | |
4832 | } | |
4833 | ||
252b5132 RH |
4834 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4835 | machine dependent instruction. This function is supposed to emit | |
4836 | the frags/bytes it assembles to. */ | |
4837 | ||
4838 | void | |
65da13b5 | 4839 | md_assemble (char *line) |
252b5132 | 4840 | { |
40fb9820 | 4841 | unsigned int j; |
83b16ac6 | 4842 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4843 | const insn_template *t; |
252b5132 | 4844 | |
47926f60 | 4845 | /* Initialize globals. */ |
252b5132 | 4846 | memset (&i, '\0', sizeof (i)); |
ca5312a2 | 4847 | i.rounding.type = rc_none; |
252b5132 | 4848 | for (j = 0; j < MAX_OPERANDS; j++) |
1ae12ab7 | 4849 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4850 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4851 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4852 | save_stack_p = save_stack; |
252b5132 RH |
4853 | |
4854 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4855 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4856 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4857 | |
29b0f896 AM |
4858 | line = parse_insn (line, mnemonic); |
4859 | if (line == NULL) | |
4860 | return; | |
83b16ac6 | 4861 | mnem_suffix = i.suffix; |
252b5132 | 4862 | |
29b0f896 | 4863 | line = parse_operands (line, mnemonic); |
ee86248c | 4864 | this_operand = -1; |
8325cc63 JB |
4865 | xfree (i.memop1_string); |
4866 | i.memop1_string = NULL; | |
29b0f896 AM |
4867 | if (line == NULL) |
4868 | return; | |
252b5132 | 4869 | |
29b0f896 AM |
4870 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4871 | operands at hand. */ | |
4872 | ||
b630c145 | 4873 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 JB |
4874 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
4875 | "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp" | |
4876 | and "call" instructions with 2 immediate operands so that the immediate | |
4877 | segment precedes the offset consistently in Intel and AT&T modes. */ | |
4d456e3d L |
4878 | if (intel_syntax |
4879 | && i.operands > 1 | |
29b0f896 | 4880 | && (strcmp (mnemonic, "bound") != 0) |
c0e54661 | 4881 | && (strncmp (mnemonic, "invlpg", 6) != 0) |
d34049e8 ML |
4882 | && !startswith (mnemonic, "monitor") |
4883 | && !startswith (mnemonic, "mwait") | |
c0e54661 | 4884 | && (strcmp (mnemonic, "pvalidate") != 0) |
d34049e8 | 4885 | && !startswith (mnemonic, "rmp") |
b630c145 JB |
4886 | && (strcmp (mnemonic, "tpause") != 0) |
4887 | && (strcmp (mnemonic, "umwait") != 0) | |
40fb9820 L |
4888 | && !(operand_type_check (i.types[0], imm) |
4889 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4890 | swap_operands (); |
4891 | ||
ec56d5c0 JB |
4892 | /* The order of the immediates should be reversed |
4893 | for 2 immediates extrq and insertq instructions */ | |
4894 | if (i.imm_operands == 2 | |
4895 | && (strcmp (mnemonic, "extrq") == 0 | |
4896 | || strcmp (mnemonic, "insertq") == 0)) | |
4897 | swap_2_operands (0, 1); | |
4898 | ||
29b0f896 AM |
4899 | if (i.imm_operands) |
4900 | optimize_imm (); | |
4901 | ||
9386188e JB |
4902 | if (i.disp_operands && !want_disp32 (current_templates->start) |
4903 | && (!current_templates->start->opcode_modifier.jump | |
4904 | || i.jumpabsolute || i.types[0].bitfield.baseindex)) | |
cce08655 JB |
4905 | { |
4906 | for (j = 0; j < i.operands; ++j) | |
4907 | { | |
4908 | const expressionS *exp = i.op[j].disps; | |
4909 | ||
4910 | if (!operand_type_check (i.types[j], disp)) | |
4911 | continue; | |
4912 | ||
4913 | if (exp->X_op != O_constant) | |
4914 | continue; | |
4915 | ||
4916 | /* Since displacement is signed extended to 64bit, don't allow | |
a775efc8 | 4917 | disp32 if it is out of range. */ |
cce08655 JB |
4918 | if (fits_in_signed_long (exp->X_add_number)) |
4919 | continue; | |
4920 | ||
a775efc8 | 4921 | i.types[j].bitfield.disp32 = 0; |
cce08655 JB |
4922 | if (i.types[j].bitfield.baseindex) |
4923 | { | |
f493c217 AM |
4924 | as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"), |
4925 | (uint64_t) exp->X_add_number); | |
cce08655 JB |
4926 | return; |
4927 | } | |
4928 | } | |
4929 | } | |
4930 | ||
b300c311 L |
4931 | /* Don't optimize displacement for movabs since it only takes 64bit |
4932 | displacement. */ | |
4933 | if (i.disp_operands | |
1a42a9fe | 4934 | && i.disp_encoding <= disp_encoding_8bit |
862be3fb L |
4935 | && (flag_code != CODE_64BIT |
4936 | || strcmp (mnemonic, "movabs") != 0)) | |
4937 | optimize_disp (); | |
29b0f896 AM |
4938 | |
4939 | /* Next, we find a template that matches the given insn, | |
4940 | making sure the overlap of the given operands types is consistent | |
4941 | with the template operand types. */ | |
252b5132 | 4942 | |
83b16ac6 | 4943 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4944 | return; |
252b5132 | 4945 | |
7bab8ab5 | 4946 | if (sse_check != check_none |
ffb86450 JB |
4947 | /* The opcode space check isn't strictly needed; it's there only to |
4948 | bypass the logic below when easily possible. */ | |
4949 | && t->opcode_modifier.opcodespace >= SPACE_0F | |
4950 | && t->opcode_modifier.opcodespace <= SPACE_0F3A | |
4951 | && !i.tm.cpu_flags.bitfield.cpusse4a | |
4952 | && !is_any_vex_encoding (t)) | |
daf50ae7 | 4953 | { |
ffb86450 JB |
4954 | bool simd = false; |
4955 | ||
4956 | for (j = 0; j < t->operands; ++j) | |
4957 | { | |
4958 | if (t->operand_types[j].bitfield.class == RegMMX) | |
4959 | break; | |
4960 | if (t->operand_types[j].bitfield.class == RegSIMD) | |
4961 | simd = true; | |
4962 | } | |
4963 | ||
4964 | if (j >= t->operands && simd) | |
4965 | (sse_check == check_warning | |
4966 | ? as_warn | |
4967 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
daf50ae7 L |
4968 | } |
4969 | ||
40fb9820 | 4970 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4971 | if (!add_prefix (FWAIT_OPCODE)) |
4972 | return; | |
252b5132 | 4973 | |
d5de92cf | 4974 | /* Check if REP prefix is OK. */ |
742732c7 | 4975 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
4976 | { |
4977 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4978 | i.tm.name, i.rep_prefix); | |
4979 | return; | |
4980 | } | |
4981 | ||
c1ba0266 L |
4982 | /* Check for lock without a lockable instruction. Destination operand |
4983 | must be memory unless it is xchg (0x86). */ | |
c32fa91d | 4984 | if (i.prefix[LOCK_PREFIX] |
742732c7 | 4985 | && (i.tm.opcode_modifier.prefixok < PrefixLock |
c1ba0266 L |
4986 | || i.mem_operands == 0 |
4987 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4988 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4989 | { |
4990 | as_bad (_("expecting lockable instruction after `lock'")); | |
4991 | return; | |
4992 | } | |
4993 | ||
40d231b4 JB |
4994 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
4995 | if (i.prefix[DATA_PREFIX] | |
4996 | && (is_any_vex_encoding (&i.tm) | |
4997 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
4998 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)) | |
7a8655d2 JB |
4999 | { |
5000 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
5001 | return; | |
5002 | } | |
5003 | ||
42164a71 | 5004 | /* Check if HLE prefix is OK. */ |
165de32a | 5005 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
5006 | return; |
5007 | ||
7e8b059b L |
5008 | /* Check BND prefix. */ |
5009 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
5010 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
5011 | ||
04ef582a | 5012 | /* Check NOTRACK prefix. */ |
742732c7 | 5013 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 5014 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 5015 | |
327e8c42 JB |
5016 | if (i.tm.cpu_flags.bitfield.cpumpx) |
5017 | { | |
5018 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
5019 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
5020 | else if (flag_code != CODE_16BIT | |
5021 | ? i.prefix[ADDR_PREFIX] | |
5022 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
5023 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
5024 | } | |
7e8b059b L |
5025 | |
5026 | /* Insert BND prefix. */ | |
76d3a78a JB |
5027 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
5028 | { | |
5029 | if (!i.prefix[BND_PREFIX]) | |
5030 | add_prefix (BND_PREFIX_OPCODE); | |
5031 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
5032 | { | |
5033 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
5034 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
5035 | } | |
5036 | } | |
7e8b059b | 5037 | |
29b0f896 | 5038 | /* Check string instruction segment overrides. */ |
51c8edf6 | 5039 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 5040 | { |
51c8edf6 | 5041 | gas_assert (i.mem_operands); |
29b0f896 | 5042 | if (!check_string ()) |
5dd0794d | 5043 | return; |
fc0763e6 | 5044 | i.disp_operands = 0; |
29b0f896 | 5045 | } |
5dd0794d | 5046 | |
b6f8c7c4 L |
5047 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
5048 | optimize_encoding (); | |
5049 | ||
c8480b58 L |
5050 | if (use_unaligned_vector_move) |
5051 | encode_with_unaligned_vector_move (); | |
5052 | ||
29b0f896 AM |
5053 | if (!process_suffix ()) |
5054 | return; | |
e413e4e9 | 5055 | |
ef07be45 CL |
5056 | /* Check if IP-relative addressing requirements can be satisfied. */ |
5057 | if (i.tm.cpu_flags.bitfield.cpuprefetchi | |
5058 | && !(i.base_reg && i.base_reg->reg_num == RegIP)) | |
f2462532 | 5059 | as_warn (_("'%s' only supports RIP-relative address"), i.tm.name); |
ef07be45 | 5060 | |
921eafea | 5061 | /* Update operand types and check extended states. */ |
bc0844ae | 5062 | for (j = 0; j < i.operands; j++) |
921eafea L |
5063 | { |
5064 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 5065 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
5066 | { |
5067 | default: | |
5068 | break; | |
5069 | case RegMMX: | |
5070 | i.xstate |= xstate_mmx; | |
5071 | break; | |
5072 | case RegMask: | |
32930e4e | 5073 | i.xstate |= xstate_mask; |
921eafea L |
5074 | break; |
5075 | case RegSIMD: | |
3d70986f | 5076 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 5077 | i.xstate |= xstate_tmm; |
3d70986f | 5078 | else if (i.tm.operand_types[j].bitfield.zmmword) |
921eafea | 5079 | i.xstate |= xstate_zmm; |
3d70986f | 5080 | else if (i.tm.operand_types[j].bitfield.ymmword) |
921eafea | 5081 | i.xstate |= xstate_ymm; |
3d70986f | 5082 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
5083 | i.xstate |= xstate_xmm; |
5084 | break; | |
5085 | } | |
5086 | } | |
bc0844ae | 5087 | |
29b0f896 AM |
5088 | /* Make still unresolved immediate matches conform to size of immediate |
5089 | given in i.suffix. */ | |
5090 | if (!finalize_imm ()) | |
5091 | return; | |
252b5132 | 5092 | |
40fb9820 | 5093 | if (i.types[0].bitfield.imm1) |
29b0f896 | 5094 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 5095 | |
9afe6eb8 L |
5096 | /* We only need to check those implicit registers for instructions |
5097 | with 3 operands or less. */ | |
5098 | if (i.operands <= 3) | |
5099 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
5100 | if (i.types[j].bitfield.instance != InstanceNone |
5101 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 5102 | i.reg_operands--; |
40fb9820 | 5103 | |
29b0f896 AM |
5104 | /* For insns with operands there are more diddles to do to the opcode. */ |
5105 | if (i.operands) | |
5106 | { | |
5107 | if (!process_operands ()) | |
5108 | return; | |
5109 | } | |
8c190ce0 | 5110 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
5111 | { |
5112 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
5113 | as_warn (_("translating to `%sp'"), i.tm.name); | |
5114 | } | |
252b5132 | 5115 | |
7a8655d2 | 5116 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 5117 | { |
c1dc7af5 | 5118 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 5119 | { |
c1dc7af5 | 5120 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
5121 | i.tm.name); |
5122 | return; | |
5123 | } | |
c0f3af97 | 5124 | |
0b9404fd JB |
5125 | /* Check for explicit REX prefix. */ |
5126 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
5127 | { | |
5128 | as_bad (_("REX prefix invalid with `%s'"), i.tm.name); | |
5129 | return; | |
5130 | } | |
5131 | ||
9e5e5283 L |
5132 | if (i.tm.opcode_modifier.vex) |
5133 | build_vex_prefix (t); | |
5134 | else | |
5135 | build_evex_prefix (); | |
0b9404fd JB |
5136 | |
5137 | /* The individual REX.RXBW bits got consumed. */ | |
5138 | i.rex &= REX_OPCODE; | |
9e5e5283 | 5139 | } |
43234a1e | 5140 | |
5dd85c99 SP |
5141 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
5142 | instructions may define INT_OPCODE as well, so avoid this corner | |
5143 | case for those instructions that use MODRM. */ | |
389d00a5 JB |
5144 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
5145 | && i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
5146 | && !i.tm.opcode_modifier.modrm |
5147 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
5148 | { |
5149 | i.tm.base_opcode = INT3_OPCODE; | |
5150 | i.imm_operands = 0; | |
5151 | } | |
252b5132 | 5152 | |
0cfa3eb3 JB |
5153 | if ((i.tm.opcode_modifier.jump == JUMP |
5154 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
5155 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
5156 | && i.op[0].disps->X_op == O_constant) |
5157 | { | |
5158 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
5159 | the absolute address given by the constant. Since ix86 jumps and | |
5160 | calls are pc relative, we need to generate a reloc. */ | |
5161 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
5162 | i.op[0].disps->X_op = O_symbol; | |
5163 | } | |
252b5132 | 5164 | |
29b0f896 AM |
5165 | /* For 8 bit registers we need an empty rex prefix. Also if the |
5166 | instruction already has a prefix, we need to convert old | |
5167 | registers to new ones. */ | |
773f551c | 5168 | |
bab6aec1 | 5169 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 5170 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 5171 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 5172 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
5173 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
5174 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
5175 | && i.rex != 0)) |
5176 | { | |
5177 | int x; | |
726c5dcd | 5178 | |
29b0f896 AM |
5179 | i.rex |= REX_OPCODE; |
5180 | for (x = 0; x < 2; x++) | |
5181 | { | |
5182 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 5183 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 5184 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 5185 | { |
3f93af61 | 5186 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
5187 | /* In case it is "hi" register, give up. */ |
5188 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 5189 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 5190 | "instruction requiring REX prefix."), |
a540244d | 5191 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 5192 | |
29b0f896 AM |
5193 | /* Otherwise it is equivalent to the extended register. |
5194 | Since the encoding doesn't change this is merely | |
5195 | cosmetic cleanup for debug output. */ | |
5196 | ||
5197 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 5198 | } |
29b0f896 AM |
5199 | } |
5200 | } | |
773f551c | 5201 | |
6b6b6807 L |
5202 | if (i.rex == 0 && i.rex_encoding) |
5203 | { | |
5204 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 5205 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
5206 | the REX_OPCODE byte. */ |
5207 | int x; | |
5208 | for (x = 0; x < 2; x++) | |
bab6aec1 | 5209 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
5210 | && i.types[x].bitfield.byte |
5211 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
5212 | && i.op[x].regs->reg_num > 3) | |
5213 | { | |
3f93af61 | 5214 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
5b7c81bd | 5215 | i.rex_encoding = false; |
6b6b6807 L |
5216 | break; |
5217 | } | |
5218 | ||
5219 | if (i.rex_encoding) | |
5220 | i.rex = REX_OPCODE; | |
5221 | } | |
5222 | ||
7ab9ffdd | 5223 | if (i.rex != 0) |
29b0f896 AM |
5224 | add_prefix (REX_OPCODE | i.rex); |
5225 | ||
ae531041 L |
5226 | insert_lfence_before (); |
5227 | ||
29b0f896 AM |
5228 | /* We are ready to output the insn. */ |
5229 | output_insn (); | |
e379e5f3 | 5230 | |
ae531041 L |
5231 | insert_lfence_after (); |
5232 | ||
e379e5f3 L |
5233 | last_insn.seg = now_seg; |
5234 | ||
5235 | if (i.tm.opcode_modifier.isprefix) | |
5236 | { | |
5237 | last_insn.kind = last_insn_prefix; | |
5238 | last_insn.name = i.tm.name; | |
5239 | last_insn.file = as_where (&last_insn.line); | |
5240 | } | |
5241 | else | |
5242 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
5243 | } |
5244 | ||
5245 | static char * | |
e3bb37b5 | 5246 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
5247 | { |
5248 | char *l = line; | |
5249 | char *token_start = l; | |
5250 | char *mnem_p; | |
5c6af06e | 5251 | int supported; |
d3ce72d0 | 5252 | const insn_template *t; |
b6169b20 | 5253 | char *dot_p = NULL; |
29b0f896 | 5254 | |
29b0f896 AM |
5255 | while (1) |
5256 | { | |
5257 | mnem_p = mnemonic; | |
5258 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
5259 | { | |
b6169b20 L |
5260 | if (*mnem_p == '.') |
5261 | dot_p = mnem_p; | |
29b0f896 AM |
5262 | mnem_p++; |
5263 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5264 | { |
29b0f896 AM |
5265 | as_bad (_("no such instruction: `%s'"), token_start); |
5266 | return NULL; | |
5267 | } | |
5268 | l++; | |
5269 | } | |
5270 | if (!is_space_char (*l) | |
5271 | && *l != END_OF_INSN | |
e44823cf JB |
5272 | && (intel_syntax |
5273 | || (*l != PREFIX_SEPARATOR | |
5274 | && *l != ','))) | |
29b0f896 AM |
5275 | { |
5276 | as_bad (_("invalid character %s in mnemonic"), | |
5277 | output_invalid (*l)); | |
5278 | return NULL; | |
5279 | } | |
5280 | if (token_start == l) | |
5281 | { | |
e44823cf | 5282 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5283 | as_bad (_("expecting prefix; got nothing")); |
5284 | else | |
5285 | as_bad (_("expecting mnemonic; got nothing")); | |
5286 | return NULL; | |
5287 | } | |
45288df1 | 5288 | |
29b0f896 | 5289 | /* Look up instruction (or prefix) via hash table. */ |
629310ab | 5290 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
47926f60 | 5291 | |
29b0f896 AM |
5292 | if (*l != END_OF_INSN |
5293 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
5294 | && current_templates | |
40fb9820 | 5295 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 5296 | { |
c6fb90c8 | 5297 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
5298 | { |
5299 | as_bad ((flag_code != CODE_64BIT | |
5300 | ? _("`%s' is only supported in 64-bit mode") | |
5301 | : _("`%s' is not supported in 64-bit mode")), | |
5302 | current_templates->start->name); | |
5303 | return NULL; | |
5304 | } | |
29b0f896 AM |
5305 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5306 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
5307 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
5308 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5309 | && flag_code != CODE_64BIT |
673fe0f0 | 5310 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5311 | ^ (flag_code == CODE_16BIT))) |
5312 | { | |
5313 | as_bad (_("redundant %s prefix"), | |
5314 | current_templates->start->name); | |
5315 | return NULL; | |
45288df1 | 5316 | } |
31184569 JB |
5317 | |
5318 | if (current_templates->start->base_opcode == PSEUDO_PREFIX) | |
29b0f896 | 5319 | { |
86fa6981 | 5320 | /* Handle pseudo prefixes. */ |
31184569 | 5321 | switch (current_templates->start->extension_opcode) |
86fa6981 | 5322 | { |
41eb8e88 | 5323 | case Prefix_Disp8: |
86fa6981 L |
5324 | /* {disp8} */ |
5325 | i.disp_encoding = disp_encoding_8bit; | |
5326 | break; | |
41eb8e88 L |
5327 | case Prefix_Disp16: |
5328 | /* {disp16} */ | |
5329 | i.disp_encoding = disp_encoding_16bit; | |
5330 | break; | |
5331 | case Prefix_Disp32: | |
86fa6981 L |
5332 | /* {disp32} */ |
5333 | i.disp_encoding = disp_encoding_32bit; | |
5334 | break; | |
41eb8e88 | 5335 | case Prefix_Load: |
86fa6981 L |
5336 | /* {load} */ |
5337 | i.dir_encoding = dir_encoding_load; | |
5338 | break; | |
41eb8e88 | 5339 | case Prefix_Store: |
86fa6981 L |
5340 | /* {store} */ |
5341 | i.dir_encoding = dir_encoding_store; | |
5342 | break; | |
41eb8e88 | 5343 | case Prefix_VEX: |
42e04b36 L |
5344 | /* {vex} */ |
5345 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 | 5346 | break; |
41eb8e88 | 5347 | case Prefix_VEX3: |
86fa6981 L |
5348 | /* {vex3} */ |
5349 | i.vec_encoding = vex_encoding_vex3; | |
5350 | break; | |
41eb8e88 | 5351 | case Prefix_EVEX: |
86fa6981 L |
5352 | /* {evex} */ |
5353 | i.vec_encoding = vex_encoding_evex; | |
5354 | break; | |
41eb8e88 | 5355 | case Prefix_REX: |
6b6b6807 | 5356 | /* {rex} */ |
5b7c81bd | 5357 | i.rex_encoding = true; |
6b6b6807 | 5358 | break; |
41eb8e88 | 5359 | case Prefix_NoOptimize: |
b6f8c7c4 | 5360 | /* {nooptimize} */ |
5b7c81bd | 5361 | i.no_optimize = true; |
b6f8c7c4 | 5362 | break; |
86fa6981 L |
5363 | default: |
5364 | abort (); | |
5365 | } | |
5366 | } | |
5367 | else | |
5368 | { | |
5369 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 5370 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 5371 | { |
4e9ac44a L |
5372 | case PREFIX_EXIST: |
5373 | return NULL; | |
5374 | case PREFIX_DS: | |
d777820b | 5375 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
5376 | i.notrack_prefix = current_templates->start->name; |
5377 | break; | |
5378 | case PREFIX_REP: | |
5379 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
5380 | i.hle_prefix = current_templates->start->name; | |
5381 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
5382 | i.bnd_prefix = current_templates->start->name; | |
5383 | else | |
5384 | i.rep_prefix = current_templates->start->name; | |
5385 | break; | |
5386 | default: | |
5387 | break; | |
86fa6981 | 5388 | } |
29b0f896 AM |
5389 | } |
5390 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
5391 | token_start = ++l; | |
5392 | } | |
5393 | else | |
5394 | break; | |
5395 | } | |
45288df1 | 5396 | |
30a55f88 | 5397 | if (!current_templates) |
b6169b20 | 5398 | { |
07d5e953 JB |
5399 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
5400 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 5401 | encoding. */ |
30a55f88 | 5402 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 5403 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 5404 | else if (mnem_p - 3 == dot_p |
a501d77e L |
5405 | && dot_p[1] == 'd' |
5406 | && dot_p[2] == '8') | |
5407 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 5408 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
5409 | && dot_p[1] == 'd' |
5410 | && dot_p[2] == '3' | |
5411 | && dot_p[3] == '2') | |
a501d77e | 5412 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
5413 | else |
5414 | goto check_suffix; | |
5415 | mnem_p = dot_p; | |
5416 | *dot_p = '\0'; | |
629310ab | 5417 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
b6169b20 L |
5418 | } |
5419 | ||
29b0f896 AM |
5420 | if (!current_templates) |
5421 | { | |
dc1e8a47 | 5422 | check_suffix: |
1c529385 | 5423 | if (mnem_p > mnemonic) |
29b0f896 | 5424 | { |
1c529385 LH |
5425 | /* See if we can get a match by trimming off a suffix. */ |
5426 | switch (mnem_p[-1]) | |
29b0f896 | 5427 | { |
1c529385 LH |
5428 | case WORD_MNEM_SUFFIX: |
5429 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
5430 | i.suffix = SHORT_MNEM_SUFFIX; |
5431 | else | |
1c529385 LH |
5432 | /* Fall through. */ |
5433 | case BYTE_MNEM_SUFFIX: | |
5434 | case QWORD_MNEM_SUFFIX: | |
5435 | i.suffix = mnem_p[-1]; | |
29b0f896 | 5436 | mnem_p[-1] = '\0'; |
fe0e921f AM |
5437 | current_templates |
5438 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5439 | break; |
5440 | case SHORT_MNEM_SUFFIX: | |
5441 | case LONG_MNEM_SUFFIX: | |
5442 | if (!intel_syntax) | |
5443 | { | |
5444 | i.suffix = mnem_p[-1]; | |
5445 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5446 | current_templates |
5447 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5448 | } |
5449 | break; | |
5450 | ||
5451 | /* Intel Syntax. */ | |
5452 | case 'd': | |
5453 | if (intel_syntax) | |
5454 | { | |
5455 | if (intel_float_operand (mnemonic) == 1) | |
5456 | i.suffix = SHORT_MNEM_SUFFIX; | |
5457 | else | |
5458 | i.suffix = LONG_MNEM_SUFFIX; | |
5459 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5460 | current_templates |
5461 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5462 | } |
5463 | break; | |
29b0f896 | 5464 | } |
29b0f896 | 5465 | } |
1c529385 | 5466 | |
29b0f896 AM |
5467 | if (!current_templates) |
5468 | { | |
5469 | as_bad (_("no such instruction: `%s'"), token_start); | |
5470 | return NULL; | |
5471 | } | |
5472 | } | |
252b5132 | 5473 | |
0cfa3eb3 JB |
5474 | if (current_templates->start->opcode_modifier.jump == JUMP |
5475 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
5476 | { |
5477 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
5478 | predict taken and predict not taken respectively. | |
5479 | I'm not sure that branch hints actually do anything on loop | |
5480 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
5481 | may work in the future and it doesn't hurt to accept them | |
5482 | now. */ | |
5483 | if (l[0] == ',' && l[1] == 'p') | |
5484 | { | |
5485 | if (l[2] == 't') | |
5486 | { | |
5487 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
5488 | return NULL; | |
5489 | l += 3; | |
5490 | } | |
5491 | else if (l[2] == 'n') | |
5492 | { | |
5493 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
5494 | return NULL; | |
5495 | l += 3; | |
5496 | } | |
5497 | } | |
5498 | } | |
5499 | /* Any other comma loses. */ | |
5500 | if (*l == ',') | |
5501 | { | |
5502 | as_bad (_("invalid character %s in mnemonic"), | |
5503 | output_invalid (*l)); | |
5504 | return NULL; | |
5505 | } | |
252b5132 | 5506 | |
29b0f896 | 5507 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
5508 | supported = 0; |
5509 | for (t = current_templates->start; t < current_templates->end; ++t) | |
5510 | { | |
c0f3af97 L |
5511 | supported |= cpu_flags_match (t); |
5512 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
d59a54c2 | 5513 | return l; |
29b0f896 | 5514 | } |
3629bb00 | 5515 | |
548d0ee6 JB |
5516 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5517 | as_bad (flag_code == CODE_64BIT | |
5518 | ? _("`%s' is not supported in 64-bit mode") | |
5519 | : _("`%s' is only supported in 64-bit mode"), | |
5520 | current_templates->start->name); | |
5521 | else | |
5522 | as_bad (_("`%s' is not supported on `%s%s'"), | |
5523 | current_templates->start->name, | |
5524 | cpu_arch_name ? cpu_arch_name : default_arch, | |
5525 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 5526 | |
548d0ee6 | 5527 | return NULL; |
29b0f896 | 5528 | } |
252b5132 | 5529 | |
29b0f896 | 5530 | static char * |
e3bb37b5 | 5531 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
5532 | { |
5533 | char *token_start; | |
3138f287 | 5534 | |
29b0f896 AM |
5535 | /* 1 if operand is pending after ','. */ |
5536 | unsigned int expecting_operand = 0; | |
252b5132 | 5537 | |
29b0f896 AM |
5538 | while (*l != END_OF_INSN) |
5539 | { | |
e68c3d59 JB |
5540 | /* Non-zero if operand parens not balanced. */ |
5541 | unsigned int paren_not_balanced = 0; | |
5542 | /* True if inside double quotes. */ | |
5543 | bool in_quotes = false; | |
5544 | ||
29b0f896 AM |
5545 | /* Skip optional white space before operand. */ |
5546 | if (is_space_char (*l)) | |
5547 | ++l; | |
d02603dc | 5548 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
5549 | { |
5550 | as_bad (_("invalid character %s before operand %d"), | |
5551 | output_invalid (*l), | |
5552 | i.operands + 1); | |
5553 | return NULL; | |
5554 | } | |
d02603dc | 5555 | token_start = l; /* After white space. */ |
e68c3d59 | 5556 | while (in_quotes || paren_not_balanced || *l != ',') |
29b0f896 AM |
5557 | { |
5558 | if (*l == END_OF_INSN) | |
5559 | { | |
e68c3d59 JB |
5560 | if (in_quotes) |
5561 | { | |
5562 | as_bad (_("unbalanced double quotes in operand %d."), | |
5563 | i.operands + 1); | |
5564 | return NULL; | |
5565 | } | |
29b0f896 AM |
5566 | if (paren_not_balanced) |
5567 | { | |
98ff9f1c JB |
5568 | know (!intel_syntax); |
5569 | as_bad (_("unbalanced parenthesis in operand %d."), | |
5570 | i.operands + 1); | |
29b0f896 AM |
5571 | return NULL; |
5572 | } | |
5573 | else | |
5574 | break; /* we are done */ | |
5575 | } | |
e68c3d59 JB |
5576 | else if (*l == '\\' && l[1] == '"') |
5577 | ++l; | |
5578 | else if (*l == '"') | |
5579 | in_quotes = !in_quotes; | |
5580 | else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l)) | |
29b0f896 AM |
5581 | { |
5582 | as_bad (_("invalid character %s in operand %d"), | |
5583 | output_invalid (*l), | |
5584 | i.operands + 1); | |
5585 | return NULL; | |
5586 | } | |
e68c3d59 | 5587 | if (!intel_syntax && !in_quotes) |
29b0f896 AM |
5588 | { |
5589 | if (*l == '(') | |
5590 | ++paren_not_balanced; | |
5591 | if (*l == ')') | |
5592 | --paren_not_balanced; | |
5593 | } | |
29b0f896 AM |
5594 | l++; |
5595 | } | |
5596 | if (l != token_start) | |
5597 | { /* Yes, we've read in another operand. */ | |
5598 | unsigned int operand_ok; | |
5599 | this_operand = i.operands++; | |
5600 | if (i.operands > MAX_OPERANDS) | |
5601 | { | |
5602 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5603 | MAX_OPERANDS); | |
5604 | return NULL; | |
5605 | } | |
9d46ce34 | 5606 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5607 | /* Now parse operand adding info to 'i' as we go along. */ |
5608 | END_STRING_AND_SAVE (l); | |
5609 | ||
1286ab78 L |
5610 | if (i.mem_operands > 1) |
5611 | { | |
5612 | as_bad (_("too many memory references for `%s'"), | |
5613 | mnemonic); | |
5614 | return 0; | |
5615 | } | |
5616 | ||
29b0f896 AM |
5617 | if (intel_syntax) |
5618 | operand_ok = | |
5619 | i386_intel_operand (token_start, | |
5620 | intel_float_operand (mnemonic)); | |
5621 | else | |
a7619375 | 5622 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5623 | |
5624 | RESTORE_END_STRING (l); | |
5625 | if (!operand_ok) | |
5626 | return NULL; | |
5627 | } | |
5628 | else | |
5629 | { | |
5630 | if (expecting_operand) | |
5631 | { | |
5632 | expecting_operand_after_comma: | |
5633 | as_bad (_("expecting operand after ','; got nothing")); | |
5634 | return NULL; | |
5635 | } | |
5636 | if (*l == ',') | |
5637 | { | |
5638 | as_bad (_("expecting operand before ','; got nothing")); | |
5639 | return NULL; | |
5640 | } | |
5641 | } | |
7f3f1ea2 | 5642 | |
29b0f896 AM |
5643 | /* Now *l must be either ',' or END_OF_INSN. */ |
5644 | if (*l == ',') | |
5645 | { | |
5646 | if (*++l == END_OF_INSN) | |
5647 | { | |
5648 | /* Just skip it, if it's \n complain. */ | |
5649 | goto expecting_operand_after_comma; | |
5650 | } | |
5651 | expecting_operand = 1; | |
5652 | } | |
5653 | } | |
5654 | return l; | |
5655 | } | |
7f3f1ea2 | 5656 | |
050dfa73 | 5657 | static void |
783c187b | 5658 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
5659 | { |
5660 | union i386_op temp_op; | |
40fb9820 | 5661 | i386_operand_type temp_type; |
c48dadc9 | 5662 | unsigned int temp_flags; |
050dfa73 | 5663 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5664 | |
050dfa73 MM |
5665 | temp_type = i.types[xchg2]; |
5666 | i.types[xchg2] = i.types[xchg1]; | |
5667 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5668 | |
5669 | temp_flags = i.flags[xchg2]; | |
5670 | i.flags[xchg2] = i.flags[xchg1]; | |
5671 | i.flags[xchg1] = temp_flags; | |
5672 | ||
050dfa73 MM |
5673 | temp_op = i.op[xchg2]; |
5674 | i.op[xchg2] = i.op[xchg1]; | |
5675 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5676 | |
050dfa73 MM |
5677 | temp_reloc = i.reloc[xchg2]; |
5678 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5679 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 5680 | |
6225c532 | 5681 | if (i.mask.reg) |
43234a1e | 5682 | { |
6225c532 JB |
5683 | if (i.mask.operand == xchg1) |
5684 | i.mask.operand = xchg2; | |
5685 | else if (i.mask.operand == xchg2) | |
5686 | i.mask.operand = xchg1; | |
43234a1e | 5687 | } |
a5748e0d | 5688 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 5689 | { |
5273a3cd JB |
5690 | if (i.broadcast.operand == xchg1) |
5691 | i.broadcast.operand = xchg2; | |
5692 | else if (i.broadcast.operand == xchg2) | |
5693 | i.broadcast.operand = xchg1; | |
43234a1e | 5694 | } |
050dfa73 MM |
5695 | } |
5696 | ||
29b0f896 | 5697 | static void |
e3bb37b5 | 5698 | swap_operands (void) |
29b0f896 | 5699 | { |
b7c61d9a | 5700 | switch (i.operands) |
050dfa73 | 5701 | { |
c0f3af97 | 5702 | case 5: |
b7c61d9a | 5703 | case 4: |
4d456e3d | 5704 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5705 | /* Fall through. */ |
b7c61d9a L |
5706 | case 3: |
5707 | case 2: | |
4d456e3d | 5708 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5709 | break; |
5710 | default: | |
5711 | abort (); | |
29b0f896 | 5712 | } |
29b0f896 AM |
5713 | |
5714 | if (i.mem_operands == 2) | |
5715 | { | |
5e042380 | 5716 | const reg_entry *temp_seg; |
29b0f896 AM |
5717 | temp_seg = i.seg[0]; |
5718 | i.seg[0] = i.seg[1]; | |
5719 | i.seg[1] = temp_seg; | |
5720 | } | |
5721 | } | |
252b5132 | 5722 | |
29b0f896 AM |
5723 | /* Try to ensure constant immediates are represented in the smallest |
5724 | opcode possible. */ | |
5725 | static void | |
e3bb37b5 | 5726 | optimize_imm (void) |
29b0f896 AM |
5727 | { |
5728 | char guess_suffix = 0; | |
5729 | int op; | |
252b5132 | 5730 | |
29b0f896 AM |
5731 | if (i.suffix) |
5732 | guess_suffix = i.suffix; | |
5733 | else if (i.reg_operands) | |
5734 | { | |
5735 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5736 | We can't do this properly yet, i.e. excluding special register |
5737 | instances, but the following works for instructions with | |
5738 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5739 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5740 | if (i.types[op].bitfield.class != Reg) |
5741 | continue; | |
5742 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5743 | { |
40fb9820 L |
5744 | guess_suffix = BYTE_MNEM_SUFFIX; |
5745 | break; | |
5746 | } | |
bab6aec1 | 5747 | else if (i.types[op].bitfield.word) |
252b5132 | 5748 | { |
40fb9820 L |
5749 | guess_suffix = WORD_MNEM_SUFFIX; |
5750 | break; | |
5751 | } | |
bab6aec1 | 5752 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5753 | { |
5754 | guess_suffix = LONG_MNEM_SUFFIX; | |
5755 | break; | |
5756 | } | |
bab6aec1 | 5757 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5758 | { |
5759 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5760 | break; |
252b5132 | 5761 | } |
29b0f896 AM |
5762 | } |
5763 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5764 | guess_suffix = WORD_MNEM_SUFFIX; | |
5765 | ||
5766 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5767 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5768 | { |
5769 | switch (i.op[op].imms->X_op) | |
252b5132 | 5770 | { |
29b0f896 AM |
5771 | case O_constant: |
5772 | /* If a suffix is given, this operand may be shortened. */ | |
5773 | switch (guess_suffix) | |
252b5132 | 5774 | { |
29b0f896 | 5775 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5776 | i.types[op].bitfield.imm32 = 1; |
5777 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5778 | break; |
5779 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5780 | i.types[op].bitfield.imm16 = 1; |
5781 | i.types[op].bitfield.imm32 = 1; | |
5782 | i.types[op].bitfield.imm32s = 1; | |
5783 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5784 | break; |
5785 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5786 | i.types[op].bitfield.imm8 = 1; |
5787 | i.types[op].bitfield.imm8s = 1; | |
5788 | i.types[op].bitfield.imm16 = 1; | |
5789 | i.types[op].bitfield.imm32 = 1; | |
5790 | i.types[op].bitfield.imm32s = 1; | |
5791 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5792 | break; |
252b5132 | 5793 | } |
252b5132 | 5794 | |
29b0f896 AM |
5795 | /* If this operand is at most 16 bits, convert it |
5796 | to a signed 16 bit number before trying to see | |
5797 | whether it will fit in an even smaller size. | |
5798 | This allows a 16-bit operand such as $0xffe0 to | |
5799 | be recognised as within Imm8S range. */ | |
40fb9820 | 5800 | if ((i.types[op].bitfield.imm16) |
7e96fb68 | 5801 | && fits_in_unsigned_word (i.op[op].imms->X_add_number)) |
252b5132 | 5802 | { |
87ed972d JB |
5803 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
5804 | ^ 0x8000) - 0x8000); | |
29b0f896 | 5805 | } |
a28def75 L |
5806 | #ifdef BFD64 |
5807 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5808 | if ((i.types[op].bitfield.imm32) |
7e96fb68 | 5809 | && fits_in_unsigned_long (i.op[op].imms->X_add_number)) |
29b0f896 AM |
5810 | { |
5811 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5812 | ^ ((offsetT) 1 << 31)) | |
5813 | - ((offsetT) 1 << 31)); | |
5814 | } | |
a28def75 | 5815 | #endif |
40fb9820 | 5816 | i.types[op] |
c6fb90c8 L |
5817 | = operand_type_or (i.types[op], |
5818 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5819 | |
29b0f896 AM |
5820 | /* We must avoid matching of Imm32 templates when 64bit |
5821 | only immediate is available. */ | |
5822 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5823 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5824 | break; |
252b5132 | 5825 | |
29b0f896 AM |
5826 | case O_absent: |
5827 | case O_register: | |
5828 | abort (); | |
5829 | ||
5830 | /* Symbols and expressions. */ | |
5831 | default: | |
9cd96992 JB |
5832 | /* Convert symbolic operand to proper sizes for matching, but don't |
5833 | prevent matching a set of insns that only supports sizes other | |
5834 | than those matching the insn suffix. */ | |
5835 | { | |
40fb9820 | 5836 | i386_operand_type mask, allowed; |
87ed972d | 5837 | const insn_template *t = current_templates->start; |
9cd96992 | 5838 | |
0dfbf9d7 | 5839 | operand_type_set (&mask, 0); |
9cd96992 JB |
5840 | switch (guess_suffix) |
5841 | { | |
5842 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5843 | mask.bitfield.imm64 = 1; |
5844 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5845 | break; |
5846 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5847 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5848 | break; |
5849 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5850 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5851 | break; |
5852 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5853 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5854 | break; |
5855 | default: | |
9cd96992 JB |
5856 | break; |
5857 | } | |
8f0212ac JB |
5858 | |
5859 | allowed = operand_type_and (t->operand_types[op], mask); | |
5860 | while (++t < current_templates->end) | |
5861 | { | |
5862 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
5863 | allowed = operand_type_and (allowed, mask); | |
5864 | } | |
5865 | ||
0dfbf9d7 | 5866 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5867 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5868 | } |
29b0f896 | 5869 | break; |
252b5132 | 5870 | } |
29b0f896 AM |
5871 | } |
5872 | } | |
47926f60 | 5873 | |
29b0f896 AM |
5874 | /* Try to use the smallest displacement type too. */ |
5875 | static void | |
e3bb37b5 | 5876 | optimize_disp (void) |
29b0f896 AM |
5877 | { |
5878 | int op; | |
3e73aa7c | 5879 | |
29b0f896 | 5880 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5881 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5882 | { |
b300c311 | 5883 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5884 | { |
91d6fa6a | 5885 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5886 | |
91d6fa6a | 5887 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5888 | { |
2f2be86b JB |
5889 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
5890 | i.op[op].disps = NULL; | |
b300c311 | 5891 | i.disp_operands--; |
f185acdd JB |
5892 | continue; |
5893 | } | |
5894 | ||
5895 | if (i.types[op].bitfield.disp16 | |
cd613c1f | 5896 | && fits_in_unsigned_word (op_disp)) |
f185acdd JB |
5897 | { |
5898 | /* If this operand is at most 16 bits, convert | |
5899 | to a signed 16 bit number and don't use 64bit | |
5900 | displacement. */ | |
5901 | op_disp = ((op_disp ^ 0x8000) - 0x8000); | |
5902 | i.types[op].bitfield.disp64 = 0; | |
b300c311 | 5903 | } |
f185acdd | 5904 | |
28a167a4 | 5905 | #ifdef BFD64 |
a50187b2 | 5906 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
a775efc8 JB |
5907 | if ((flag_code != CODE_64BIT |
5908 | ? i.types[op].bitfield.disp32 | |
5909 | : want_disp32 (current_templates->start) | |
5910 | && (!current_templates->start->opcode_modifier.jump | |
5911 | || i.jumpabsolute || i.types[op].bitfield.baseindex)) | |
a50187b2 | 5912 | && fits_in_unsigned_long (op_disp)) |
b300c311 | 5913 | { |
a50187b2 JB |
5914 | /* If this operand is at most 32 bits, convert |
5915 | to a signed 32 bit number and don't use 64bit | |
5916 | displacement. */ | |
5917 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
5918 | i.types[op].bitfield.disp64 = 0; | |
5919 | i.types[op].bitfield.disp32 = 1; | |
5920 | } | |
28a167a4 | 5921 | |
a50187b2 JB |
5922 | if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp)) |
5923 | { | |
5924 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 5925 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 5926 | } |
28a167a4 | 5927 | #endif |
40fb9820 | 5928 | if ((i.types[op].bitfield.disp32 |
40fb9820 | 5929 | || i.types[op].bitfield.disp16) |
b5014f7a | 5930 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5931 | i.types[op].bitfield.disp8 = 1; |
77c59789 JB |
5932 | |
5933 | i.op[op].disps->X_add_number = op_disp; | |
252b5132 | 5934 | } |
67a4f2b7 AO |
5935 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5936 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5937 | { | |
5938 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5939 | i.op[op].disps, 0, i.reloc[op]); | |
2f2be86b | 5940 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
67a4f2b7 AO |
5941 | } |
5942 | else | |
b300c311 | 5943 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5944 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5945 | } |
29b0f896 AM |
5946 | } |
5947 | ||
4a1b91ea L |
5948 | /* Return 1 if there is a match in broadcast bytes between operand |
5949 | GIVEN and instruction template T. */ | |
5950 | ||
5951 | static INLINE int | |
5952 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5953 | { | |
5954 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5955 | && i.types[given].bitfield.byte) | |
5956 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5957 | && i.types[given].bitfield.word) | |
5958 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5959 | && i.types[given].bitfield.dword) | |
5960 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5961 | && i.types[given].bitfield.qword)); | |
5962 | } | |
5963 | ||
6c30d220 L |
5964 | /* Check if operands are valid for the instruction. */ |
5965 | ||
5966 | static int | |
5967 | check_VecOperands (const insn_template *t) | |
5968 | { | |
43234a1e | 5969 | unsigned int op; |
e2195274 | 5970 | i386_cpu_flags cpu; |
e2195274 JB |
5971 | |
5972 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5973 | any one operand are implicity requiring AVX512VL support if the actual | |
5974 | operand size is YMMword or XMMword. Since this function runs after | |
5975 | template matching, there's no need to check for YMMword/XMMword in | |
5976 | the template. */ | |
5977 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5978 | if (!cpu_flags_all_zero (&cpu) | |
5979 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5980 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5981 | { | |
5982 | for (op = 0; op < t->operands; ++op) | |
5983 | { | |
5984 | if (t->operand_types[op].bitfield.zmmword | |
5985 | && (i.types[op].bitfield.ymmword | |
5986 | || i.types[op].bitfield.xmmword)) | |
5987 | { | |
5988 | i.error = unsupported; | |
5989 | return 1; | |
5990 | } | |
5991 | } | |
5992 | } | |
43234a1e | 5993 | |
22c36940 JB |
5994 | /* Somewhat similarly, templates specifying both AVX and AVX2 are |
5995 | requiring AVX2 support if the actual operand size is YMMword. */ | |
5996 | if (t->cpu_flags.bitfield.cpuavx | |
5997 | && t->cpu_flags.bitfield.cpuavx2 | |
5998 | && !cpu_arch_flags.bitfield.cpuavx2) | |
5999 | { | |
6000 | for (op = 0; op < t->operands; ++op) | |
6001 | { | |
6002 | if (t->operand_types[op].bitfield.xmmword | |
6003 | && i.types[op].bitfield.ymmword) | |
6004 | { | |
6005 | i.error = unsupported; | |
6006 | return 1; | |
6007 | } | |
6008 | } | |
6009 | } | |
6010 | ||
6c30d220 | 6011 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 6012 | if (!t->opcode_modifier.sib |
6c30d220 | 6013 | && i.index_reg |
1b54b8d7 JB |
6014 | && (i.index_reg->reg_type.bitfield.xmmword |
6015 | || i.index_reg->reg_type.bitfield.ymmword | |
6016 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
6017 | { |
6018 | i.error = unsupported_vector_index_register; | |
6019 | return 1; | |
6020 | } | |
6021 | ||
ad8ecc81 MZ |
6022 | /* Check if default mask is allowed. */ |
6023 | if (t->opcode_modifier.nodefmask | |
6225c532 | 6024 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
6025 | { |
6026 | i.error = no_default_mask; | |
6027 | return 1; | |
6028 | } | |
6029 | ||
7bab8ab5 JB |
6030 | /* For VSIB byte, we need a vector register for index, and all vector |
6031 | registers must be distinct. */ | |
260cd341 | 6032 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
6033 | { |
6034 | if (!i.index_reg | |
63112cd6 | 6035 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 6036 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 6037 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 6038 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 6039 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 6040 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
6041 | { |
6042 | i.error = invalid_vsib_address; | |
6043 | return 1; | |
6044 | } | |
6045 | ||
6225c532 JB |
6046 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
6047 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 6048 | { |
3528c362 | 6049 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6050 | gas_assert (i.types[0].bitfield.xmmword |
6051 | || i.types[0].bitfield.ymmword); | |
3528c362 | 6052 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6053 | gas_assert (i.types[2].bitfield.xmmword |
6054 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
6055 | if (operand_check == check_none) |
6056 | return 0; | |
6057 | if (register_number (i.op[0].regs) | |
6058 | != register_number (i.index_reg) | |
6059 | && register_number (i.op[2].regs) | |
6060 | != register_number (i.index_reg) | |
6061 | && register_number (i.op[0].regs) | |
6062 | != register_number (i.op[2].regs)) | |
6063 | return 0; | |
6064 | if (operand_check == check_error) | |
6065 | { | |
6066 | i.error = invalid_vector_register_set; | |
6067 | return 1; | |
6068 | } | |
6069 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6070 | } | |
6225c532 | 6071 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 6072 | { |
3528c362 | 6073 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
6074 | && (i.types[1].bitfield.xmmword |
6075 | || i.types[1].bitfield.ymmword | |
6076 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
6077 | && (register_number (i.op[1].regs) |
6078 | == register_number (i.index_reg))) | |
6079 | { | |
6080 | if (operand_check == check_error) | |
6081 | { | |
6082 | i.error = invalid_vector_register_set; | |
6083 | return 1; | |
6084 | } | |
6085 | if (operand_check != check_none) | |
6086 | as_warn (_("index and destination registers should be distinct")); | |
6087 | } | |
6088 | } | |
43234a1e | 6089 | } |
7bab8ab5 | 6090 | |
fc141319 L |
6091 | /* For AMX instructions with 3 TMM register operands, all operands |
6092 | must be distinct. */ | |
6093 | if (i.reg_operands == 3 | |
6094 | && t->operand_types[0].bitfield.tmmword | |
6095 | && (i.op[0].regs == i.op[1].regs | |
6096 | || i.op[0].regs == i.op[2].regs | |
6097 | || i.op[1].regs == i.op[2].regs)) | |
6098 | { | |
6099 | i.error = invalid_tmm_register_set; | |
6100 | return 1; | |
260cd341 LC |
6101 | } |
6102 | ||
0cc78721 CL |
6103 | /* For some special instructions require that destination must be distinct |
6104 | from source registers. */ | |
6105 | if (t->opcode_modifier.distinctdest) | |
6106 | { | |
6107 | unsigned int dest_reg = i.operands - 1; | |
6108 | ||
6109 | know (i.operands >= 3); | |
6110 | ||
6111 | /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */ | |
6112 | if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs | |
6113 | || (i.reg_operands > 2 | |
6114 | && i.op[dest_reg - 2].regs == i.op[dest_reg].regs)) | |
6115 | { | |
6116 | i.error = invalid_dest_and_src_register_set; | |
6117 | return 1; | |
6118 | } | |
6119 | } | |
6120 | ||
43234a1e L |
6121 | /* Check if broadcast is supported by the instruction and is applied |
6122 | to the memory operand. */ | |
a5748e0d | 6123 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 6124 | { |
8e6e0792 | 6125 | i386_operand_type type, overlap; |
43234a1e L |
6126 | |
6127 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 6128 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 6129 | op = i.broadcast.operand; |
8e6e0792 | 6130 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 6131 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 6132 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 6133 | && !match_broadcast_size (t, op))) |
43234a1e L |
6134 | { |
6135 | bad_broadcast: | |
6136 | i.error = unsupported_broadcast; | |
6137 | return 1; | |
6138 | } | |
8e6e0792 | 6139 | |
a5748e0d JB |
6140 | if (i.broadcast.type) |
6141 | i.broadcast.bytes = ((1 << (t->opcode_modifier.broadcast - 1)) | |
6142 | * i.broadcast.type); | |
8e6e0792 | 6143 | operand_type_set (&type, 0); |
a5748e0d | 6144 | switch (get_broadcast_bytes (t, false)) |
8e6e0792 | 6145 | { |
4a1b91ea L |
6146 | case 2: |
6147 | type.bitfield.word = 1; | |
6148 | break; | |
6149 | case 4: | |
6150 | type.bitfield.dword = 1; | |
6151 | break; | |
8e6e0792 JB |
6152 | case 8: |
6153 | type.bitfield.qword = 1; | |
6154 | break; | |
6155 | case 16: | |
6156 | type.bitfield.xmmword = 1; | |
6157 | break; | |
6158 | case 32: | |
6159 | type.bitfield.ymmword = 1; | |
6160 | break; | |
6161 | case 64: | |
6162 | type.bitfield.zmmword = 1; | |
6163 | break; | |
6164 | default: | |
6165 | goto bad_broadcast; | |
6166 | } | |
6167 | ||
6168 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
6169 | if (t->operand_types[op].bitfield.class == RegSIMD |
6170 | && t->operand_types[op].bitfield.byte | |
6171 | + t->operand_types[op].bitfield.word | |
6172 | + t->operand_types[op].bitfield.dword | |
6173 | + t->operand_types[op].bitfield.qword > 1) | |
6174 | { | |
6175 | overlap.bitfield.xmmword = 0; | |
6176 | overlap.bitfield.ymmword = 0; | |
6177 | overlap.bitfield.zmmword = 0; | |
6178 | } | |
8e6e0792 JB |
6179 | if (operand_type_all_zero (&overlap)) |
6180 | goto bad_broadcast; | |
6181 | ||
6182 | if (t->opcode_modifier.checkregsize) | |
6183 | { | |
6184 | unsigned int j; | |
6185 | ||
e2195274 | 6186 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
6187 | for (j = 0; j < i.operands; ++j) |
6188 | { | |
6189 | if (j != op | |
6190 | && !operand_type_register_match(i.types[j], | |
6191 | t->operand_types[j], | |
6192 | type, | |
6193 | t->operand_types[op])) | |
6194 | goto bad_broadcast; | |
6195 | } | |
6196 | } | |
43234a1e L |
6197 | } |
6198 | /* If broadcast is supported in this instruction, we need to check if | |
6199 | operand of one-element size isn't specified without broadcast. */ | |
6200 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
6201 | { | |
6202 | /* Find memory operand. */ | |
6203 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6204 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
6205 | break; |
6206 | gas_assert (op < i.operands); | |
6207 | /* Check size of the memory operand. */ | |
4a1b91ea | 6208 | if (match_broadcast_size (t, op)) |
43234a1e L |
6209 | { |
6210 | i.error = broadcast_needed; | |
6211 | return 1; | |
6212 | } | |
6213 | } | |
c39e5b26 JB |
6214 | else |
6215 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
6216 | |
6217 | /* Check if requested masking is supported. */ | |
6225c532 | 6218 | if (i.mask.reg) |
43234a1e | 6219 | { |
ae2387fe JB |
6220 | switch (t->opcode_modifier.masking) |
6221 | { | |
6222 | case BOTH_MASKING: | |
6223 | break; | |
6224 | case MERGING_MASKING: | |
6225c532 | 6225 | if (i.mask.zeroing) |
ae2387fe JB |
6226 | { |
6227 | case 0: | |
6228 | i.error = unsupported_masking; | |
6229 | return 1; | |
6230 | } | |
6231 | break; | |
6232 | case DYNAMIC_MASKING: | |
6233 | /* Memory destinations allow only merging masking. */ | |
6225c532 | 6234 | if (i.mask.zeroing && i.mem_operands) |
ae2387fe JB |
6235 | { |
6236 | /* Find memory operand. */ | |
6237 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 6238 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
6239 | break; |
6240 | gas_assert (op < i.operands); | |
6241 | if (op == i.operands - 1) | |
6242 | { | |
6243 | i.error = unsupported_masking; | |
6244 | return 1; | |
6245 | } | |
6246 | } | |
6247 | break; | |
6248 | default: | |
6249 | abort (); | |
6250 | } | |
43234a1e L |
6251 | } |
6252 | ||
6253 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 6254 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
6255 | { |
6256 | i.error = mask_not_on_destination; | |
6257 | return 1; | |
6258 | } | |
6259 | ||
43234a1e | 6260 | /* Check RC/SAE. */ |
ca5312a2 | 6261 | if (i.rounding.type != rc_none) |
43234a1e | 6262 | { |
a80195f1 | 6263 | if (!t->opcode_modifier.sae |
cf665fee JB |
6264 | || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding) |
6265 | || i.mem_operands) | |
43234a1e L |
6266 | { |
6267 | i.error = unsupported_rc_sae; | |
6268 | return 1; | |
6269 | } | |
cf665fee JB |
6270 | |
6271 | /* Non-EVEX.LIG forms need to have a ZMM register as at least one | |
6272 | operand. */ | |
6273 | if (t->opcode_modifier.evex != EVEXLIG) | |
7bab8ab5 | 6274 | { |
cf665fee JB |
6275 | for (op = 0; op < t->operands; ++op) |
6276 | if (i.types[op].bitfield.zmmword) | |
6277 | break; | |
6278 | if (op >= t->operands) | |
6279 | { | |
6280 | i.error = operand_size_mismatch; | |
6281 | return 1; | |
6282 | } | |
7bab8ab5 | 6283 | } |
6c30d220 L |
6284 | } |
6285 | ||
da4977e0 JB |
6286 | /* Check the special Imm4 cases; must be the first operand. */ |
6287 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
6288 | { | |
6289 | if (i.op[0].imms->X_op != O_constant | |
6290 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
6291 | { | |
6292 | i.error = bad_imm4; | |
6293 | return 1; | |
6294 | } | |
6295 | ||
6296 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
6297 | operand_type_set (&i.types[0], 0); | |
6298 | } | |
6299 | ||
43234a1e | 6300 | /* Check vector Disp8 operand. */ |
b5014f7a | 6301 | if (t->opcode_modifier.disp8memshift |
1a42a9fe | 6302 | && i.disp_encoding <= disp_encoding_8bit) |
43234a1e | 6303 | { |
a5748e0d | 6304 | if (i.broadcast.bytes) |
4a1b91ea | 6305 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 6306 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 6307 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
6308 | else |
6309 | { | |
125ff819 | 6310 | const i386_operand_type *type = NULL, *fallback = NULL; |
7091c612 JB |
6311 | |
6312 | i.memshift = 0; | |
6313 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6314 | if (i.flags[op] & Operand_Mem) |
7091c612 | 6315 | { |
4174bfff JB |
6316 | if (t->opcode_modifier.evex == EVEXLIG) |
6317 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
6318 | else if (t->operand_types[op].bitfield.xmmword | |
6319 | + t->operand_types[op].bitfield.ymmword | |
6320 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
6321 | type = &t->operand_types[op]; |
6322 | else if (!i.types[op].bitfield.unspecified) | |
6323 | type = &i.types[op]; | |
125ff819 JB |
6324 | else /* Ambiguities get resolved elsewhere. */ |
6325 | fallback = &t->operand_types[op]; | |
7091c612 | 6326 | } |
3528c362 | 6327 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 6328 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
6329 | { |
6330 | if (i.types[op].bitfield.zmmword) | |
6331 | i.memshift = 6; | |
6332 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
6333 | i.memshift = 5; | |
6334 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
6335 | i.memshift = 4; | |
6336 | } | |
6337 | ||
125ff819 JB |
6338 | if (!type && !i.memshift) |
6339 | type = fallback; | |
7091c612 JB |
6340 | if (type) |
6341 | { | |
6342 | if (type->bitfield.zmmword) | |
6343 | i.memshift = 6; | |
6344 | else if (type->bitfield.ymmword) | |
6345 | i.memshift = 5; | |
6346 | else if (type->bitfield.xmmword) | |
6347 | i.memshift = 4; | |
6348 | } | |
6349 | ||
6350 | /* For the check in fits_in_disp8(). */ | |
6351 | if (i.memshift == 0) | |
6352 | i.memshift = -1; | |
6353 | } | |
43234a1e L |
6354 | |
6355 | for (op = 0; op < i.operands; op++) | |
6356 | if (operand_type_check (i.types[op], disp) | |
6357 | && i.op[op].disps->X_op == O_constant) | |
6358 | { | |
b5014f7a | 6359 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 6360 | { |
b5014f7a JB |
6361 | i.types[op].bitfield.disp8 = 1; |
6362 | return 0; | |
43234a1e | 6363 | } |
b5014f7a | 6364 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
6365 | } |
6366 | } | |
b5014f7a JB |
6367 | |
6368 | i.memshift = 0; | |
43234a1e | 6369 | |
6c30d220 L |
6370 | return 0; |
6371 | } | |
6372 | ||
da4977e0 | 6373 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
6374 | |
6375 | static int | |
da4977e0 | 6376 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 6377 | { |
da4977e0 JB |
6378 | if (i.vec_encoding == vex_encoding_error) |
6379 | { | |
6380 | i.error = unsupported; | |
6381 | return 1; | |
6382 | } | |
6383 | ||
86fa6981 | 6384 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 6385 | { |
86fa6981 | 6386 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 6387 | if (!is_evex_encoding (t)) |
86fa6981 L |
6388 | { |
6389 | i.error = unsupported; | |
6390 | return 1; | |
6391 | } | |
6392 | return 0; | |
43234a1e L |
6393 | } |
6394 | ||
a683cc34 | 6395 | if (!t->opcode_modifier.vex) |
86fa6981 L |
6396 | { |
6397 | /* This instruction template doesn't have VEX prefix. */ | |
6398 | if (i.vec_encoding != vex_encoding_default) | |
6399 | { | |
6400 | i.error = unsupported; | |
6401 | return 1; | |
6402 | } | |
6403 | return 0; | |
6404 | } | |
a683cc34 | 6405 | |
a683cc34 SP |
6406 | return 0; |
6407 | } | |
6408 | ||
7b94647a JB |
6409 | /* Helper function for the progress() macro in match_template(). */ |
6410 | static INLINE enum i386_error progress (enum i386_error new, | |
6411 | enum i386_error last, | |
6412 | unsigned int line, unsigned int *line_p) | |
6413 | { | |
6414 | if (line <= *line_p) | |
6415 | return last; | |
6416 | *line_p = line; | |
6417 | return new; | |
6418 | } | |
6419 | ||
d3ce72d0 | 6420 | static const insn_template * |
83b16ac6 | 6421 | match_template (char mnem_suffix) |
29b0f896 AM |
6422 | { |
6423 | /* Points to template once we've found it. */ | |
d3ce72d0 | 6424 | const insn_template *t; |
40fb9820 | 6425 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 6426 | i386_operand_type overlap4; |
29b0f896 | 6427 | unsigned int found_reverse_match; |
dc2be329 | 6428 | i386_opcode_modifier suffix_check; |
40fb9820 | 6429 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 6430 | int addr_prefix_disp; |
7b94647a JB |
6431 | unsigned int j, size_match, check_register, errline = __LINE__; |
6432 | enum i386_error specific_error = number_of_operands_mismatch; | |
6433 | #define progress(err) progress (err, specific_error, __LINE__, &errline) | |
29b0f896 | 6434 | |
c0f3af97 L |
6435 | #if MAX_OPERANDS != 5 |
6436 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
6437 | #endif |
6438 | ||
29b0f896 | 6439 | found_reverse_match = 0; |
539e75ad | 6440 | addr_prefix_disp = -1; |
40fb9820 | 6441 | |
dc2be329 | 6442 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 6443 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
6444 | switch (mnem_suffix) |
6445 | { | |
6446 | case BYTE_MNEM_SUFFIX: | |
6447 | suffix_check.no_bsuf = 1; | |
6448 | break; | |
6449 | case WORD_MNEM_SUFFIX: | |
6450 | suffix_check.no_wsuf = 1; | |
6451 | break; | |
6452 | case SHORT_MNEM_SUFFIX: | |
6453 | suffix_check.no_ssuf = 1; | |
6454 | break; | |
6455 | case LONG_MNEM_SUFFIX: | |
6456 | suffix_check.no_lsuf = 1; | |
6457 | break; | |
6458 | case QWORD_MNEM_SUFFIX: | |
6459 | suffix_check.no_qsuf = 1; | |
6460 | break; | |
6461 | default: | |
6462 | /* NB: In Intel syntax, normally we can check for memory operand | |
6463 | size when there is no mnemonic suffix. But jmp and call have | |
6464 | 2 different encodings with Dword memory operand size, one with | |
6465 | No_ldSuf and the other without. i.suffix is set to | |
6466 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
6467 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
6468 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
6469 | } |
6470 | ||
45aa61fe | 6471 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 6472 | { |
539e75ad | 6473 | addr_prefix_disp = -1; |
dbbc8b7e | 6474 | found_reverse_match = 0; |
539e75ad | 6475 | |
7b94647a | 6476 | /* Must have right number of operands. */ |
29b0f896 AM |
6477 | if (i.operands != t->operands) |
6478 | continue; | |
6479 | ||
50aecf8c | 6480 | /* Check processor support. */ |
7b94647a | 6481 | specific_error = progress (unsupported); |
45a4bb20 | 6482 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
6483 | continue; |
6484 | ||
e1d4d893 | 6485 | /* Check AT&T mnemonic. */ |
7b94647a | 6486 | specific_error = progress (unsupported_with_intel_mnemonic); |
e1d4d893 | 6487 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
6488 | continue; |
6489 | ||
4b5aaf5f | 6490 | /* Check AT&T/Intel syntax. */ |
7b94647a | 6491 | specific_error = progress (unsupported_syntax); |
5c07affc | 6492 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 6493 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
6494 | continue; |
6495 | ||
4b5aaf5f L |
6496 | /* Check Intel64/AMD64 ISA. */ |
6497 | switch (isa64) | |
6498 | { | |
6499 | default: | |
6500 | /* Default: Don't accept Intel64. */ | |
6501 | if (t->opcode_modifier.isa64 == INTEL64) | |
6502 | continue; | |
6503 | break; | |
6504 | case amd64: | |
6505 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
6506 | if (t->opcode_modifier.isa64 >= INTEL64) | |
6507 | continue; | |
6508 | break; | |
6509 | case intel64: | |
6510 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 6511 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
6512 | continue; |
6513 | break; | |
6514 | } | |
6515 | ||
dc2be329 | 6516 | /* Check the suffix. */ |
7b94647a | 6517 | specific_error = progress (invalid_instruction_suffix); |
dc2be329 L |
6518 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
6519 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
6520 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
6521 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
6522 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
6523 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 6524 | continue; |
29b0f896 | 6525 | |
7b94647a | 6526 | specific_error = progress (operand_size_mismatch); |
3ac21baa JB |
6527 | size_match = operand_size_match (t); |
6528 | if (!size_match) | |
7d5e4556 | 6529 | continue; |
539e75ad | 6530 | |
6f2f06be JB |
6531 | /* This is intentionally not |
6532 | ||
0cfa3eb3 | 6533 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
6534 | |
6535 | as the case of a missing * on the operand is accepted (perhaps with | |
6536 | a warning, issued further down). */ | |
7b94647a | 6537 | specific_error = progress (operand_type_mismatch); |
0cfa3eb3 | 6538 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
7b94647a | 6539 | continue; |
6f2f06be | 6540 | |
5c07affc L |
6541 | for (j = 0; j < MAX_OPERANDS; j++) |
6542 | operand_types[j] = t->operand_types[j]; | |
6543 | ||
e365e234 JB |
6544 | /* In general, don't allow |
6545 | - 64-bit operands outside of 64-bit mode, | |
6546 | - 32-bit operands on pre-386. */ | |
7b94647a JB |
6547 | specific_error = progress (mnem_suffix ? invalid_instruction_suffix |
6548 | : operand_size_mismatch); | |
4873e243 | 6549 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
e365e234 JB |
6550 | if (((i.suffix == QWORD_MNEM_SUFFIX |
6551 | && flag_code != CODE_64BIT | |
389d00a5 JB |
6552 | && !(t->opcode_modifier.opcodespace == SPACE_0F |
6553 | && t->base_opcode == 0xc7 | |
5e74b495 | 6554 | && t->opcode_modifier.opcodeprefix == PREFIX_NONE |
8b65b895 | 6555 | && t->extension_opcode == 1) /* cmpxchg8b */) |
e365e234 JB |
6556 | || (i.suffix == LONG_MNEM_SUFFIX |
6557 | && !cpu_arch_flags.bitfield.cpui386)) | |
45aa61fe | 6558 | && (intel_syntax |
3cd7f3e3 | 6559 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
45aa61fe AM |
6560 | && !intel_float_operand (t->name)) |
6561 | : intel_float_operand (t->name) != 2) | |
4873e243 JB |
6562 | && (t->operands == i.imm_operands |
6563 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
6564 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
6565 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
6566 | || (operand_types[j].bitfield.class != RegMMX | |
6567 | && operand_types[j].bitfield.class != RegSIMD | |
6568 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 6569 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
6570 | continue; |
6571 | ||
29b0f896 | 6572 | /* Do not verify operands when there are none. */ |
e365e234 | 6573 | if (!t->operands) |
da4977e0 JB |
6574 | { |
6575 | if (VEX_check_encoding (t)) | |
6576 | { | |
7b94647a | 6577 | specific_error = progress (i.error); |
da4977e0 JB |
6578 | continue; |
6579 | } | |
6580 | ||
6581 | /* We've found a match; break out of loop. */ | |
6582 | break; | |
6583 | } | |
252b5132 | 6584 | |
48bcea9f JB |
6585 | if (!t->opcode_modifier.jump |
6586 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
6587 | { | |
6588 | /* There should be only one Disp operand. */ | |
6589 | for (j = 0; j < MAX_OPERANDS; j++) | |
6590 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 6591 | break; |
48bcea9f JB |
6592 | if (j < MAX_OPERANDS) |
6593 | { | |
5b7c81bd | 6594 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
6595 | |
6596 | addr_prefix_disp = j; | |
6597 | ||
a775efc8 JB |
6598 | /* Address size prefix will turn Disp64 operand into Disp32 and |
6599 | Disp32/Disp16 one into Disp16/Disp32 respectively. */ | |
48bcea9f | 6600 | switch (flag_code) |
40fb9820 | 6601 | { |
48bcea9f JB |
6602 | case CODE_16BIT: |
6603 | override = !override; | |
6604 | /* Fall through. */ | |
6605 | case CODE_32BIT: | |
6606 | if (operand_types[j].bitfield.disp32 | |
6607 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 6608 | { |
48bcea9f JB |
6609 | operand_types[j].bitfield.disp16 = override; |
6610 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 6611 | } |
a775efc8 | 6612 | gas_assert (!operand_types[j].bitfield.disp64); |
48bcea9f JB |
6613 | break; |
6614 | ||
6615 | case CODE_64BIT: | |
a775efc8 | 6616 | if (operand_types[j].bitfield.disp64) |
40fb9820 | 6617 | { |
a775efc8 | 6618 | gas_assert (!operand_types[j].bitfield.disp32); |
48bcea9f | 6619 | operand_types[j].bitfield.disp32 = override; |
a775efc8 | 6620 | operand_types[j].bitfield.disp64 = !override; |
40fb9820 | 6621 | } |
48bcea9f JB |
6622 | operand_types[j].bitfield.disp16 = 0; |
6623 | break; | |
40fb9820 | 6624 | } |
539e75ad | 6625 | } |
48bcea9f | 6626 | } |
539e75ad | 6627 | |
d7e3e627 L |
6628 | switch (i.reloc[0]) |
6629 | { | |
6630 | case BFD_RELOC_386_GOT32: | |
6631 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ | |
6632 | if (t->base_opcode == 0xa0 | |
6633 | && t->opcode_modifier.opcodespace == SPACE_BASE) | |
6634 | continue; | |
6635 | break; | |
6636 | case BFD_RELOC_386_TLS_GOTIE: | |
6637 | case BFD_RELOC_386_TLS_LE_32: | |
6638 | case BFD_RELOC_X86_64_GOTTPOFF: | |
6639 | case BFD_RELOC_X86_64_TLSLD: | |
6640 | /* Don't allow KMOV in TLS code sequences. */ | |
6641 | if (t->opcode_modifier.vex) | |
6642 | continue; | |
6643 | break; | |
6644 | default: | |
6645 | break; | |
6646 | } | |
02a86693 | 6647 | |
56ffb741 | 6648 | /* We check register size if needed. */ |
e2195274 JB |
6649 | if (t->opcode_modifier.checkregsize) |
6650 | { | |
6651 | check_register = (1 << t->operands) - 1; | |
a5748e0d | 6652 | if (i.broadcast.type || i.broadcast.bytes) |
5273a3cd | 6653 | check_register &= ~(1 << i.broadcast.operand); |
e2195274 JB |
6654 | } |
6655 | else | |
6656 | check_register = 0; | |
6657 | ||
c6fb90c8 | 6658 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
6659 | switch (t->operands) |
6660 | { | |
6661 | case 1: | |
40fb9820 | 6662 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
6663 | continue; |
6664 | break; | |
6665 | case 2: | |
33eaf5de | 6666 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
6667 | only in 32bit mode and we can use opcode 0x90. In 64bit |
6668 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
6669 | zero-extend %eax to %rax. */ | |
6670 | if (flag_code == CODE_64BIT | |
6671 | && t->base_opcode == 0x90 | |
35648716 | 6672 | && t->opcode_modifier.opcodespace == SPACE_BASE |
75e5731b JB |
6673 | && i.types[0].bitfield.instance == Accum |
6674 | && i.types[0].bitfield.dword | |
6675 | && i.types[1].bitfield.instance == Accum | |
6676 | && i.types[1].bitfield.dword) | |
8b38ad71 | 6677 | continue; |
1212781b JB |
6678 | /* xrelease mov %eax, <disp> is another special case. It must not |
6679 | match the accumulator-only encoding of mov. */ | |
6680 | if (flag_code != CODE_64BIT | |
6681 | && i.hle_prefix | |
6682 | && t->base_opcode == 0xa0 | |
35648716 | 6683 | && t->opcode_modifier.opcodespace == SPACE_BASE |
75e5731b | 6684 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 6685 | && (i.flags[1] & Operand_Mem)) |
1212781b | 6686 | continue; |
f5eb1d70 JB |
6687 | /* Fall through. */ |
6688 | ||
6689 | case 3: | |
3ac21baa JB |
6690 | if (!(size_match & MATCH_STRAIGHT)) |
6691 | goto check_reverse; | |
64c49ab3 JB |
6692 | /* Reverse direction of operands if swapping is possible in the first |
6693 | place (operands need to be symmetric) and | |
6694 | - the load form is requested, and the template is a store form, | |
6695 | - the store form is requested, and the template is a load form, | |
6696 | - the non-default (swapped) form is requested. */ | |
6697 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6698 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6699 | && !operand_type_all_zero (&overlap1)) |
6700 | switch (i.dir_encoding) | |
6701 | { | |
6702 | case dir_encoding_load: | |
6703 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6704 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6705 | goto check_reverse; |
6706 | break; | |
6707 | ||
6708 | case dir_encoding_store: | |
6709 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6710 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6711 | goto check_reverse; |
6712 | break; | |
6713 | ||
6714 | case dir_encoding_swap: | |
6715 | goto check_reverse; | |
6716 | ||
6717 | case dir_encoding_default: | |
6718 | break; | |
6719 | } | |
86fa6981 | 6720 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6721 | if ((i.dir_encoding == dir_encoding_store |
6722 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6723 | && i.mem_operands == 0 |
6724 | && t->opcode_modifier.load) | |
fa99fab2 | 6725 | continue; |
1a0670f3 | 6726 | /* Fall through. */ |
f48ff2ae | 6727 | case 4: |
c0f3af97 | 6728 | case 5: |
c6fb90c8 | 6729 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6730 | if (!operand_type_match (overlap0, i.types[0]) |
6731 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6732 | || ((check_register & 3) == 3 |
dc821c5f | 6733 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6734 | operand_types[0], |
dc821c5f | 6735 | i.types[1], |
40fb9820 | 6736 | operand_types[1]))) |
29b0f896 | 6737 | { |
7b94647a JB |
6738 | specific_error = progress (i.error); |
6739 | ||
29b0f896 | 6740 | /* Check if other direction is valid ... */ |
38e314eb | 6741 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6742 | continue; |
6743 | ||
dc1e8a47 | 6744 | check_reverse: |
3ac21baa JB |
6745 | if (!(size_match & MATCH_REVERSE)) |
6746 | continue; | |
29b0f896 | 6747 | /* Try reversing direction of operands. */ |
8bd915b7 JB |
6748 | j = t->opcode_modifier.vexsources ? 1 : i.operands - 1; |
6749 | overlap0 = operand_type_and (i.types[0], operand_types[j]); | |
6750 | overlap1 = operand_type_and (i.types[j], operand_types[0]); | |
c975cec5 JB |
6751 | overlap2 = operand_type_and (i.types[1], operand_types[1]); |
6752 | gas_assert (t->operands != 3 || !check_register); | |
40fb9820 | 6753 | if (!operand_type_match (overlap0, i.types[0]) |
8bd915b7 | 6754 | || !operand_type_match (overlap1, i.types[j]) |
c975cec5 JB |
6755 | || (t->operands == 3 |
6756 | && !operand_type_match (overlap2, i.types[1])) | |
45664ddb | 6757 | || (check_register |
dc821c5f | 6758 | && !operand_type_register_match (i.types[0], |
8bd915b7 JB |
6759 | operand_types[j], |
6760 | i.types[j], | |
45664ddb | 6761 | operand_types[0]))) |
29b0f896 AM |
6762 | { |
6763 | /* Does not match either direction. */ | |
7b94647a | 6764 | specific_error = progress (i.error); |
29b0f896 AM |
6765 | continue; |
6766 | } | |
38e314eb | 6767 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6768 | we've found. */ |
38e314eb JB |
6769 | if (!t->opcode_modifier.d) |
6770 | found_reverse_match = 0; | |
6771 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6772 | found_reverse_match = Opcode_FloatD; |
8bd915b7 JB |
6773 | else if (t->opcode_modifier.vexsources) |
6774 | { | |
6775 | found_reverse_match = Opcode_VexW; | |
6776 | goto check_operands_345; | |
6777 | } | |
2c735193 JB |
6778 | else if (t->opcode_modifier.opcodespace != SPACE_BASE |
6779 | && (t->opcode_modifier.opcodespace != SPACE_0F | |
6780 | /* MOV to/from CR/DR/TR, as an exception, follow | |
6781 | the base opcode space encoding model. */ | |
6782 | || (t->base_opcode | 7) != 0x27)) | |
dbbc8b7e | 6783 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e |
2c735193 | 6784 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
8a2ed489 | 6785 | else |
38e314eb | 6786 | found_reverse_match = Opcode_D; |
40fb9820 | 6787 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6788 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6789 | } |
f48ff2ae | 6790 | else |
29b0f896 | 6791 | { |
f48ff2ae | 6792 | /* Found a forward 2 operand match here. */ |
8bd915b7 | 6793 | check_operands_345: |
d1cbb4db L |
6794 | switch (t->operands) |
6795 | { | |
c0f3af97 | 6796 | case 5: |
3d0738af | 6797 | overlap4 = operand_type_and (i.types[4], operand_types[4]); |
c0f3af97 | 6798 | if (!operand_type_match (overlap4, i.types[4]) |
dc821c5f | 6799 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6800 | operand_types[3], |
c0f3af97 L |
6801 | i.types[4], |
6802 | operand_types[4])) | |
7b94647a JB |
6803 | { |
6804 | specific_error = progress (i.error); | |
6805 | continue; | |
6806 | } | |
1a0670f3 | 6807 | /* Fall through. */ |
f48ff2ae | 6808 | case 4: |
3d0738af | 6809 | overlap3 = operand_type_and (i.types[3], operand_types[3]); |
40fb9820 | 6810 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6811 | || ((check_register & 0xa) == 0xa |
6812 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6813 | operand_types[1], |
6814 | i.types[3], | |
e2195274 JB |
6815 | operand_types[3])) |
6816 | || ((check_register & 0xc) == 0xc | |
6817 | && !operand_type_register_match (i.types[2], | |
6818 | operand_types[2], | |
6819 | i.types[3], | |
6820 | operand_types[3]))) | |
7b94647a JB |
6821 | { |
6822 | specific_error = progress (i.error); | |
6823 | continue; | |
6824 | } | |
1a0670f3 | 6825 | /* Fall through. */ |
f48ff2ae | 6826 | case 3: |
3d0738af | 6827 | overlap2 = operand_type_and (i.types[2], operand_types[2]); |
40fb9820 | 6828 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6829 | || ((check_register & 5) == 5 |
6830 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6831 | operand_types[0], |
6832 | i.types[2], | |
e2195274 JB |
6833 | operand_types[2])) |
6834 | || ((check_register & 6) == 6 | |
6835 | && !operand_type_register_match (i.types[1], | |
6836 | operand_types[1], | |
6837 | i.types[2], | |
6838 | operand_types[2]))) | |
7b94647a JB |
6839 | { |
6840 | specific_error = progress (i.error); | |
6841 | continue; | |
6842 | } | |
f48ff2ae L |
6843 | break; |
6844 | } | |
29b0f896 | 6845 | } |
f48ff2ae | 6846 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6847 | slip through to break. */ |
6848 | } | |
c0f3af97 | 6849 | |
9bb4d860 L |
6850 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ |
6851 | if (VEX_check_encoding (t)) | |
da4977e0 | 6852 | { |
7b94647a | 6853 | specific_error = progress (i.error); |
da4977e0 JB |
6854 | continue; |
6855 | } | |
6856 | ||
9bb4d860 L |
6857 | /* Check if vector operands are valid. */ |
6858 | if (check_VecOperands (t)) | |
5614d22c | 6859 | { |
7b94647a | 6860 | specific_error = progress (i.error); |
5614d22c JB |
6861 | continue; |
6862 | } | |
a683cc34 | 6863 | |
29b0f896 AM |
6864 | /* We've found a match; break out of loop. */ |
6865 | break; | |
6866 | } | |
6867 | ||
7b94647a JB |
6868 | #undef progress |
6869 | ||
29b0f896 AM |
6870 | if (t == current_templates->end) |
6871 | { | |
6872 | /* We found no match. */ | |
a65babc9 | 6873 | const char *err_msg; |
7b94647a | 6874 | switch (specific_error) |
a65babc9 L |
6875 | { |
6876 | default: | |
6877 | abort (); | |
86e026a4 | 6878 | case operand_size_mismatch: |
a65babc9 L |
6879 | err_msg = _("operand size mismatch"); |
6880 | break; | |
6881 | case operand_type_mismatch: | |
6882 | err_msg = _("operand type mismatch"); | |
6883 | break; | |
6884 | case register_type_mismatch: | |
6885 | err_msg = _("register type mismatch"); | |
6886 | break; | |
6887 | case number_of_operands_mismatch: | |
6888 | err_msg = _("number of operands mismatch"); | |
6889 | break; | |
6890 | case invalid_instruction_suffix: | |
6891 | err_msg = _("invalid instruction suffix"); | |
6892 | break; | |
6893 | case bad_imm4: | |
4a2608e3 | 6894 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6895 | break; |
a65babc9 L |
6896 | case unsupported_with_intel_mnemonic: |
6897 | err_msg = _("unsupported with Intel mnemonic"); | |
6898 | break; | |
6899 | case unsupported_syntax: | |
6900 | err_msg = _("unsupported syntax"); | |
6901 | break; | |
6902 | case unsupported: | |
35262a23 | 6903 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6904 | current_templates->start->name); |
6905 | return NULL; | |
260cd341 LC |
6906 | case invalid_sib_address: |
6907 | err_msg = _("invalid SIB address"); | |
6908 | break; | |
6c30d220 L |
6909 | case invalid_vsib_address: |
6910 | err_msg = _("invalid VSIB address"); | |
6911 | break; | |
7bab8ab5 JB |
6912 | case invalid_vector_register_set: |
6913 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6914 | break; | |
260cd341 LC |
6915 | case invalid_tmm_register_set: |
6916 | err_msg = _("all tmm registers must be distinct"); | |
6917 | break; | |
0cc78721 CL |
6918 | case invalid_dest_and_src_register_set: |
6919 | err_msg = _("destination and source registers must be distinct"); | |
6920 | break; | |
6c30d220 L |
6921 | case unsupported_vector_index_register: |
6922 | err_msg = _("unsupported vector index register"); | |
6923 | break; | |
43234a1e L |
6924 | case unsupported_broadcast: |
6925 | err_msg = _("unsupported broadcast"); | |
6926 | break; | |
43234a1e L |
6927 | case broadcast_needed: |
6928 | err_msg = _("broadcast is needed for operand of such type"); | |
6929 | break; | |
6930 | case unsupported_masking: | |
6931 | err_msg = _("unsupported masking"); | |
6932 | break; | |
6933 | case mask_not_on_destination: | |
6934 | err_msg = _("mask not on destination operand"); | |
6935 | break; | |
6936 | case no_default_mask: | |
6937 | err_msg = _("default mask isn't allowed"); | |
6938 | break; | |
6939 | case unsupported_rc_sae: | |
6940 | err_msg = _("unsupported static rounding/sae"); | |
6941 | break; | |
43234a1e L |
6942 | case invalid_register_operand: |
6943 | err_msg = _("invalid register operand"); | |
6944 | break; | |
a65babc9 L |
6945 | } |
6946 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6947 | current_templates->start->name); |
fa99fab2 | 6948 | return NULL; |
29b0f896 | 6949 | } |
252b5132 | 6950 | |
29b0f896 AM |
6951 | if (!quiet_warnings) |
6952 | { | |
6953 | if (!intel_syntax | |
0cfa3eb3 | 6954 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6955 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6956 | |
40fb9820 | 6957 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 6958 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
6959 | { |
6960 | /* Warn them that a data or address size prefix doesn't | |
6961 | affect assembly of the next line of code. */ | |
6962 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6963 | } | |
6964 | } | |
6965 | ||
6966 | /* Copy the template we found. */ | |
9a182d04 | 6967 | install_template (t); |
539e75ad L |
6968 | |
6969 | if (addr_prefix_disp != -1) | |
6970 | i.tm.operand_types[addr_prefix_disp] | |
6971 | = operand_types[addr_prefix_disp]; | |
6972 | ||
8bd915b7 | 6973 | switch (found_reverse_match) |
29b0f896 | 6974 | { |
8bd915b7 JB |
6975 | case 0: |
6976 | break; | |
6977 | ||
6978 | default: | |
dfd69174 JB |
6979 | /* If we found a reverse match we must alter the opcode direction |
6980 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6981 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6982 | |
6983 | i.tm.base_opcode ^= found_reverse_match; | |
6984 | ||
f5eb1d70 JB |
6985 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6986 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6987 | |
6988 | /* Certain SIMD insns have their load forms specified in the opcode | |
6989 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6990 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6991 | i.tm.opcode_modifier.regmem | |
6992 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6993 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6994 | && !i.tm.opcode_modifier.regmem; | |
8bd915b7 JB |
6995 | break; |
6996 | ||
6997 | case Opcode_VexW: | |
6998 | /* Only the first two register operands need reversing, alongside | |
6999 | flipping VEX.W. */ | |
7000 | i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1; | |
7001 | ||
7002 | j = i.tm.operand_types[0].bitfield.imm8; | |
7003 | i.tm.operand_types[j] = operand_types[j + 1]; | |
7004 | i.tm.operand_types[j + 1] = operand_types[j]; | |
7005 | break; | |
29b0f896 AM |
7006 | } |
7007 | ||
fa99fab2 | 7008 | return t; |
29b0f896 AM |
7009 | } |
7010 | ||
7011 | static int | |
e3bb37b5 | 7012 | check_string (void) |
29b0f896 | 7013 | { |
51c8edf6 JB |
7014 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
7015 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 7016 | |
5e042380 | 7017 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 7018 | { |
51c8edf6 JB |
7019 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
7020 | i.tm.name, | |
7021 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
7022 | register_prefix); | |
7023 | return 0; | |
29b0f896 | 7024 | } |
51c8edf6 JB |
7025 | |
7026 | /* There's only ever one segment override allowed per instruction. | |
7027 | This instruction possibly has a legal segment override on the | |
7028 | second operand, so copy the segment to where non-string | |
7029 | instructions store it, allowing common code. */ | |
7030 | i.seg[op] = i.seg[1]; | |
7031 | ||
29b0f896 AM |
7032 | return 1; |
7033 | } | |
7034 | ||
7035 | static int | |
543613e9 | 7036 | process_suffix (void) |
29b0f896 | 7037 | { |
5b7c81bd | 7038 | bool is_crc32 = false, is_movx = false; |
8b65b895 | 7039 | |
29b0f896 AM |
7040 | /* If matched instruction specifies an explicit instruction mnemonic |
7041 | suffix, use it. */ | |
673fe0f0 | 7042 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 7043 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 7044 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 7045 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 7046 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 7047 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 7048 | else if (i.reg_operands |
c8f8eebc JB |
7049 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
7050 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 7051 | { |
65fca059 | 7052 | unsigned int numop = i.operands; |
389d00a5 JB |
7053 | |
7054 | /* MOVSX/MOVZX */ | |
7055 | is_movx = (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
7056 | && (i.tm.base_opcode | 8) == 0xbe) | |
7057 | || (i.tm.opcode_modifier.opcodespace == SPACE_BASE | |
7058 | && i.tm.base_opcode == 0x63 | |
7059 | && i.tm.cpu_flags.bitfield.cpu64); | |
7060 | ||
8b65b895 | 7061 | /* CRC32 */ |
389d00a5 JB |
7062 | is_crc32 = (i.tm.base_opcode == 0xf0 |
7063 | && i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
8b65b895 | 7064 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2); |
65fca059 JB |
7065 | |
7066 | /* movsx/movzx want only their source operand considered here, for the | |
7067 | ambiguity checking below. The suffix will be replaced afterwards | |
7068 | to represent the destination (register). */ | |
389d00a5 | 7069 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
7070 | --i.operands; |
7071 | ||
643bb870 | 7072 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
8b65b895 | 7073 | if (is_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
7074 | i.rex |= REX_W; |
7075 | ||
29b0f896 | 7076 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 7077 | based on GPR operands. */ |
29b0f896 AM |
7078 | if (!i.suffix) |
7079 | { | |
7080 | /* We take i.suffix from the last register operand specified, | |
7081 | Destination register type is more significant than source | |
381d071f L |
7082 | register type. crc32 in SSE4.2 prefers source register |
7083 | type. */ | |
8b65b895 | 7084 | unsigned int op = is_crc32 ? 1 : i.operands; |
20592a94 | 7085 | |
1a035124 JB |
7086 | while (op--) |
7087 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
7088 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
7089 | { | |
7090 | if (i.types[op].bitfield.class != Reg) | |
7091 | continue; | |
7092 | if (i.types[op].bitfield.byte) | |
7093 | i.suffix = BYTE_MNEM_SUFFIX; | |
7094 | else if (i.types[op].bitfield.word) | |
7095 | i.suffix = WORD_MNEM_SUFFIX; | |
7096 | else if (i.types[op].bitfield.dword) | |
7097 | i.suffix = LONG_MNEM_SUFFIX; | |
7098 | else if (i.types[op].bitfield.qword) | |
7099 | i.suffix = QWORD_MNEM_SUFFIX; | |
7100 | else | |
7101 | continue; | |
7102 | break; | |
7103 | } | |
65fca059 JB |
7104 | |
7105 | /* As an exception, movsx/movzx silently default to a byte source | |
7106 | in AT&T mode. */ | |
389d00a5 | 7107 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 7108 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
7109 | } |
7110 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
7111 | { | |
1cb0ab18 | 7112 | if (!check_byte_reg ()) |
29b0f896 AM |
7113 | return 0; |
7114 | } | |
7115 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
7116 | { | |
1cb0ab18 | 7117 | if (!check_long_reg ()) |
29b0f896 AM |
7118 | return 0; |
7119 | } | |
7120 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7121 | { | |
1cb0ab18 | 7122 | if (!check_qword_reg ()) |
29b0f896 AM |
7123 | return 0; |
7124 | } | |
7125 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7126 | { | |
1cb0ab18 | 7127 | if (!check_word_reg ()) |
29b0f896 AM |
7128 | return 0; |
7129 | } | |
3cd7f3e3 L |
7130 | else if (intel_syntax |
7131 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
7132 | /* Do nothing if the instruction is going to ignore the prefix. */ |
7133 | ; | |
7134 | else | |
7135 | abort (); | |
65fca059 JB |
7136 | |
7137 | /* Undo the movsx/movzx change done above. */ | |
7138 | i.operands = numop; | |
29b0f896 | 7139 | } |
3cd7f3e3 L |
7140 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
7141 | && !i.suffix) | |
29b0f896 | 7142 | { |
13e600d0 JB |
7143 | i.suffix = stackop_size; |
7144 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
7145 | { |
7146 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
7147 | .code16gcc directive to support 16-bit mode with | |
7148 | 32-bit address. For IRET without a suffix, generate | |
7149 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
7150 | handler. */ | |
13e600d0 JB |
7151 | if (i.tm.base_opcode == 0xcf) |
7152 | { | |
7153 | i.suffix = WORD_MNEM_SUFFIX; | |
7154 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
7155 | } | |
7156 | /* Warn about changed behavior for segment register push/pop. */ | |
7157 | else if ((i.tm.base_opcode | 1) == 0x07) | |
7158 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
7159 | i.tm.name); | |
06f74c5c | 7160 | } |
29b0f896 | 7161 | } |
c006a730 | 7162 | else if (!i.suffix |
0cfa3eb3 JB |
7163 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
7164 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
7165 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
389d00a5 JB |
7166 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
7167 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ | |
64e74474 | 7168 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
7169 | { |
7170 | switch (flag_code) | |
7171 | { | |
7172 | case CODE_64BIT: | |
40fb9820 | 7173 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 7174 | { |
828c2a25 JB |
7175 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
7176 | || i.tm.opcode_modifier.no_lsuf) | |
7177 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
7178 | break; |
7179 | } | |
1a0670f3 | 7180 | /* Fall through. */ |
9306ca4a | 7181 | case CODE_32BIT: |
40fb9820 | 7182 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
7183 | i.suffix = LONG_MNEM_SUFFIX; |
7184 | break; | |
7185 | case CODE_16BIT: | |
40fb9820 | 7186 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
7187 | i.suffix = WORD_MNEM_SUFFIX; |
7188 | break; | |
7189 | } | |
7190 | } | |
252b5132 | 7191 | |
c006a730 | 7192 | if (!i.suffix |
3cd7f3e3 | 7193 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
7194 | /* Also cover lret/retf/iret in 64-bit mode. */ |
7195 | || (flag_code == CODE_64BIT | |
7196 | && !i.tm.opcode_modifier.no_lsuf | |
7197 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 7198 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
7199 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
7200 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
7201 | /* Accept FLDENV et al without suffix. */ |
7202 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 7203 | { |
6c0946d0 | 7204 | unsigned int suffixes, evex = 0; |
c006a730 JB |
7205 | |
7206 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
7207 | if (!i.tm.opcode_modifier.no_wsuf) | |
7208 | suffixes |= 1 << 1; | |
7209 | if (!i.tm.opcode_modifier.no_lsuf) | |
7210 | suffixes |= 1 << 2; | |
7211 | if (!i.tm.opcode_modifier.no_ldsuf) | |
7212 | suffixes |= 1 << 3; | |
7213 | if (!i.tm.opcode_modifier.no_ssuf) | |
7214 | suffixes |= 1 << 4; | |
7215 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
7216 | suffixes |= 1 << 5; | |
7217 | ||
6c0946d0 JB |
7218 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
7219 | also suitable for AT&T syntax mode, it was requested that this be | |
7220 | restricted to just Intel syntax. */ | |
a5748e0d JB |
7221 | if (intel_syntax && is_any_vex_encoding (&i.tm) |
7222 | && !i.broadcast.type && !i.broadcast.bytes) | |
6c0946d0 | 7223 | { |
b9915cbc | 7224 | unsigned int op; |
6c0946d0 | 7225 | |
b9915cbc | 7226 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 7227 | { |
b9915cbc JB |
7228 | if (is_evex_encoding (&i.tm) |
7229 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 7230 | { |
b9915cbc JB |
7231 | if (i.tm.operand_types[op].bitfield.ymmword) |
7232 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
7233 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7234 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
7235 | if (!i.tm.opcode_modifier.evex | |
7236 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
7237 | i.tm.opcode_modifier.evex = EVEX512; | |
7238 | } | |
6c0946d0 | 7239 | |
b9915cbc JB |
7240 | if (i.tm.operand_types[op].bitfield.xmmword |
7241 | + i.tm.operand_types[op].bitfield.ymmword | |
7242 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
7243 | continue; | |
6c0946d0 | 7244 | |
b9915cbc JB |
7245 | /* Any properly sized operand disambiguates the insn. */ |
7246 | if (i.types[op].bitfield.xmmword | |
7247 | || i.types[op].bitfield.ymmword | |
7248 | || i.types[op].bitfield.zmmword) | |
7249 | { | |
7250 | suffixes &= ~(7 << 6); | |
7251 | evex = 0; | |
7252 | break; | |
7253 | } | |
6c0946d0 | 7254 | |
b9915cbc JB |
7255 | if ((i.flags[op] & Operand_Mem) |
7256 | && i.tm.operand_types[op].bitfield.unspecified) | |
7257 | { | |
7258 | if (i.tm.operand_types[op].bitfield.xmmword) | |
7259 | suffixes |= 1 << 6; | |
7260 | if (i.tm.operand_types[op].bitfield.ymmword) | |
7261 | suffixes |= 1 << 7; | |
7262 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7263 | suffixes |= 1 << 8; | |
7264 | if (is_evex_encoding (&i.tm)) | |
7265 | evex = EVEX512; | |
6c0946d0 JB |
7266 | } |
7267 | } | |
7268 | } | |
7269 | ||
7270 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 7271 | if (suffixes & (suffixes - 1)) |
9306ca4a | 7272 | { |
873494c8 | 7273 | if (intel_syntax |
3cd7f3e3 | 7274 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 7275 | || operand_check == check_error)) |
9306ca4a | 7276 | { |
c006a730 | 7277 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
7278 | return 0; |
7279 | } | |
c006a730 | 7280 | if (operand_check == check_error) |
9306ca4a | 7281 | { |
c006a730 JB |
7282 | as_bad (_("no instruction mnemonic suffix given and " |
7283 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
7284 | return 0; |
7285 | } | |
c006a730 | 7286 | if (operand_check == check_warning) |
873494c8 JB |
7287 | as_warn (_("%s; using default for `%s'"), |
7288 | intel_syntax | |
7289 | ? _("ambiguous operand size") | |
7290 | : _("no instruction mnemonic suffix given and " | |
7291 | "no register operands"), | |
7292 | i.tm.name); | |
c006a730 JB |
7293 | |
7294 | if (i.tm.opcode_modifier.floatmf) | |
7295 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 7296 | else if (is_movx) |
65fca059 | 7297 | /* handled below */; |
6c0946d0 JB |
7298 | else if (evex) |
7299 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
7300 | else if (flag_code == CODE_16BIT) |
7301 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 7302 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 7303 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
7304 | else |
7305 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 7306 | } |
29b0f896 | 7307 | } |
252b5132 | 7308 | |
389d00a5 | 7309 | if (is_movx) |
65fca059 JB |
7310 | { |
7311 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
7312 | In AT&T syntax, if there is no suffix (warned about above), the default | |
7313 | will be byte extension. */ | |
7314 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
7315 | i.tm.base_opcode |= 1; | |
7316 | ||
7317 | /* For further processing, the suffix should represent the destination | |
7318 | (register). This is already the case when one was used with | |
7319 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
7320 | no suffix to begin with. */ | |
7321 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
7322 | { | |
7323 | if (i.types[1].bitfield.word) | |
7324 | i.suffix = WORD_MNEM_SUFFIX; | |
7325 | else if (i.types[1].bitfield.qword) | |
7326 | i.suffix = QWORD_MNEM_SUFFIX; | |
7327 | else | |
7328 | i.suffix = LONG_MNEM_SUFFIX; | |
7329 | ||
7330 | i.tm.opcode_modifier.w = 0; | |
7331 | } | |
7332 | } | |
7333 | ||
50128d0c JB |
7334 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
7335 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
7336 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
7337 | ||
d2224064 JB |
7338 | /* Change the opcode based on the operand size given by i.suffix. */ |
7339 | switch (i.suffix) | |
29b0f896 | 7340 | { |
d2224064 JB |
7341 | /* Size floating point instruction. */ |
7342 | case LONG_MNEM_SUFFIX: | |
7343 | if (i.tm.opcode_modifier.floatmf) | |
7344 | { | |
7345 | i.tm.base_opcode ^= 4; | |
7346 | break; | |
7347 | } | |
7348 | /* fall through */ | |
7349 | case WORD_MNEM_SUFFIX: | |
7350 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 7351 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 7352 | if (i.tm.opcode_modifier.w) |
29b0f896 | 7353 | { |
50128d0c | 7354 | if (i.short_form) |
29b0f896 AM |
7355 | i.tm.base_opcode |= 8; |
7356 | else | |
7357 | i.tm.base_opcode |= 1; | |
7358 | } | |
d2224064 JB |
7359 | /* fall through */ |
7360 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
7361 | /* Now select between word & dword operations via the operand |
7362 | size prefix, except for instructions that will ignore this | |
7363 | prefix anyway. */ | |
c8f8eebc | 7364 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 7365 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
7366 | && !i.tm.opcode_modifier.floatmf |
7367 | && !is_any_vex_encoding (&i.tm) | |
7368 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
7369 | || (flag_code == CODE_64BIT | |
7370 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
7371 | { |
7372 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 7373 | |
0cfa3eb3 | 7374 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 7375 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 7376 | |
29b0f896 AM |
7377 | if (!add_prefix (prefix)) |
7378 | return 0; | |
24eab124 | 7379 | } |
252b5132 | 7380 | |
29b0f896 AM |
7381 | /* Set mode64 for an operand. */ |
7382 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 7383 | && flag_code == CODE_64BIT |
d2224064 | 7384 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 7385 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 7386 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
7387 | need rex64. */ |
7388 | && ! (i.operands == 2 | |
7389 | && i.tm.base_opcode == 0x90 | |
7390 | && i.tm.extension_opcode == None | |
75e5731b JB |
7391 | && i.types[0].bitfield.instance == Accum |
7392 | && i.types[0].bitfield.qword | |
7393 | && i.types[1].bitfield.instance == Accum | |
7394 | && i.types[1].bitfield.qword)) | |
d2224064 | 7395 | i.rex |= REX_W; |
3e73aa7c | 7396 | |
d2224064 | 7397 | break; |
8bbb3ad8 JB |
7398 | |
7399 | case 0: | |
f9a6a8f0 | 7400 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
7401 | when there are no suitable register operands. */ |
7402 | if (i.tm.opcode_modifier.w | |
7403 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
7404 | && (!i.reg_operands | |
7405 | || (i.reg_operands == 1 | |
7406 | /* ShiftCount */ | |
7407 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
7408 | /* InOutPortReg */ | |
7409 | || i.tm.operand_types[0].bitfield.instance == RegD | |
7410 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7411 | /* CRC32 */ | |
8b65b895 | 7412 | || is_crc32)))) |
8bbb3ad8 JB |
7413 | i.tm.base_opcode |= 1; |
7414 | break; | |
29b0f896 | 7415 | } |
7ecd2f8b | 7416 | |
c8f8eebc | 7417 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 7418 | { |
c8f8eebc JB |
7419 | gas_assert (!i.suffix); |
7420 | gas_assert (i.reg_operands); | |
c0a30a9f | 7421 | |
c8f8eebc JB |
7422 | if (i.tm.operand_types[0].bitfield.instance == Accum |
7423 | || i.operands == 1) | |
7424 | { | |
7425 | /* The address size override prefix changes the size of the | |
7426 | first operand. */ | |
7427 | if (flag_code == CODE_64BIT | |
7428 | && i.op[0].regs->reg_type.bitfield.word) | |
7429 | { | |
7430 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
7431 | i.tm.name); | |
7432 | return 0; | |
7433 | } | |
7434 | ||
7435 | if ((flag_code == CODE_32BIT | |
7436 | ? i.op[0].regs->reg_type.bitfield.word | |
7437 | : i.op[0].regs->reg_type.bitfield.dword) | |
7438 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
7439 | return 0; | |
7440 | } | |
c0a30a9f L |
7441 | else |
7442 | { | |
c8f8eebc JB |
7443 | /* Check invalid register operand when the address size override |
7444 | prefix changes the size of register operands. */ | |
7445 | unsigned int op; | |
7446 | enum { need_word, need_dword, need_qword } need; | |
7447 | ||
27f13469 | 7448 | /* Check the register operand for the address size prefix if |
b3a3496f | 7449 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 7450 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
7451 | if (i.mem_operands == 1 |
7452 | && i.reg_operands == 1 | |
7453 | && i.operands == 2 | |
27f13469 | 7454 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
7455 | && (flag_code == CODE_32BIT |
7456 | ? i.op[1].regs->reg_type.bitfield.word | |
7457 | : i.op[1].regs->reg_type.bitfield.dword) | |
7458 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
7459 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
7460 | || (x86_elf_abi == X86_64_X32_ABI | |
7461 | && i.base_reg | |
b3a3496f L |
7462 | && i.base_reg->reg_num == RegIP |
7463 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
7464 | #else |
7465 | || 0) | |
7466 | #endif | |
27f13469 L |
7467 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
7468 | return 0; | |
7469 | ||
c8f8eebc JB |
7470 | if (flag_code == CODE_32BIT) |
7471 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
7472 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
7473 | need = need_dword; |
7474 | else | |
7475 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 7476 | |
c8f8eebc JB |
7477 | for (op = 0; op < i.operands; op++) |
7478 | { | |
7479 | if (i.types[op].bitfield.class != Reg) | |
7480 | continue; | |
7481 | ||
7482 | switch (need) | |
7483 | { | |
7484 | case need_word: | |
7485 | if (i.op[op].regs->reg_type.bitfield.word) | |
7486 | continue; | |
7487 | break; | |
7488 | case need_dword: | |
7489 | if (i.op[op].regs->reg_type.bitfield.dword) | |
7490 | continue; | |
7491 | break; | |
7492 | case need_qword: | |
7493 | if (i.op[op].regs->reg_type.bitfield.qword) | |
7494 | continue; | |
7495 | break; | |
7496 | } | |
7497 | ||
7498 | as_bad (_("invalid register operand size for `%s'"), | |
7499 | i.tm.name); | |
7500 | return 0; | |
7501 | } | |
7502 | } | |
c0a30a9f L |
7503 | } |
7504 | ||
29b0f896 AM |
7505 | return 1; |
7506 | } | |
3e73aa7c | 7507 | |
29b0f896 | 7508 | static int |
543613e9 | 7509 | check_byte_reg (void) |
29b0f896 AM |
7510 | { |
7511 | int op; | |
543613e9 | 7512 | |
29b0f896 AM |
7513 | for (op = i.operands; --op >= 0;) |
7514 | { | |
dc821c5f | 7515 | /* Skip non-register operands. */ |
bab6aec1 | 7516 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
7517 | continue; |
7518 | ||
29b0f896 AM |
7519 | /* If this is an eight bit register, it's OK. If it's the 16 or |
7520 | 32 bit version of an eight bit register, we will just use the | |
7521 | low portion, and that's OK too. */ | |
dc821c5f | 7522 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
7523 | continue; |
7524 | ||
5a819eb9 | 7525 | /* I/O port address operands are OK too. */ |
75e5731b JB |
7526 | if (i.tm.operand_types[op].bitfield.instance == RegD |
7527 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
7528 | continue; |
7529 | ||
9706160a | 7530 | /* crc32 only wants its source operand checked here. */ |
389d00a5 JB |
7531 | if (i.tm.base_opcode == 0xf0 |
7532 | && i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
8b65b895 L |
7533 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2 |
7534 | && op != 0) | |
9344ff29 L |
7535 | continue; |
7536 | ||
29b0f896 | 7537 | /* Any other register is bad. */ |
73c76375 JB |
7538 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7539 | register_prefix, i.op[op].regs->reg_name, | |
7540 | i.tm.name, i.suffix); | |
7541 | return 0; | |
29b0f896 AM |
7542 | } |
7543 | return 1; | |
7544 | } | |
7545 | ||
7546 | static int | |
e3bb37b5 | 7547 | check_long_reg (void) |
29b0f896 AM |
7548 | { |
7549 | int op; | |
7550 | ||
7551 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7552 | /* Skip non-register operands. */ |
bab6aec1 | 7553 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7554 | continue; |
29b0f896 AM |
7555 | /* Reject eight bit registers, except where the template requires |
7556 | them. (eg. movzb) */ | |
dc821c5f | 7557 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7558 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7559 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7560 | && (i.tm.operand_types[op].bitfield.word |
7561 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7562 | { |
a540244d L |
7563 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7564 | register_prefix, | |
29b0f896 AM |
7565 | i.op[op].regs->reg_name, |
7566 | i.tm.name, | |
7567 | i.suffix); | |
7568 | return 0; | |
7569 | } | |
be4c5e58 L |
7570 | /* Error if the e prefix on a general reg is missing. */ |
7571 | else if (i.types[op].bitfield.word | |
bab6aec1 | 7572 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7573 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7574 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 7575 | { |
be4c5e58 L |
7576 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7577 | register_prefix, i.op[op].regs->reg_name, | |
7578 | i.suffix); | |
7579 | return 0; | |
252b5132 | 7580 | } |
e4630f71 | 7581 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 7582 | else if (i.types[op].bitfield.qword |
bab6aec1 | 7583 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7584 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7585 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 7586 | { |
1cb0ab18 JB |
7587 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7588 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
7589 | return 0; | |
29b0f896 AM |
7590 | } |
7591 | return 1; | |
7592 | } | |
252b5132 | 7593 | |
29b0f896 | 7594 | static int |
e3bb37b5 | 7595 | check_qword_reg (void) |
29b0f896 AM |
7596 | { |
7597 | int op; | |
252b5132 | 7598 | |
29b0f896 | 7599 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 7600 | /* Skip non-register operands. */ |
bab6aec1 | 7601 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7602 | continue; |
29b0f896 AM |
7603 | /* Reject eight bit registers, except where the template requires |
7604 | them. (eg. movzb) */ | |
dc821c5f | 7605 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7606 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7607 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7608 | && (i.tm.operand_types[op].bitfield.word |
7609 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7610 | { |
a540244d L |
7611 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7612 | register_prefix, | |
29b0f896 AM |
7613 | i.op[op].regs->reg_name, |
7614 | i.tm.name, | |
7615 | i.suffix); | |
7616 | return 0; | |
7617 | } | |
e4630f71 | 7618 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
7619 | else if ((i.types[op].bitfield.word |
7620 | || i.types[op].bitfield.dword) | |
bab6aec1 | 7621 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7622 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7623 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
7624 | { |
7625 | /* Prohibit these changes in the 64bit mode, since the | |
7626 | lowering is more complicated. */ | |
1cb0ab18 JB |
7627 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7628 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
7629 | return 0; | |
252b5132 | 7630 | } |
29b0f896 AM |
7631 | return 1; |
7632 | } | |
252b5132 | 7633 | |
29b0f896 | 7634 | static int |
e3bb37b5 | 7635 | check_word_reg (void) |
29b0f896 AM |
7636 | { |
7637 | int op; | |
7638 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7639 | /* Skip non-register operands. */ |
bab6aec1 | 7640 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7641 | continue; |
29b0f896 AM |
7642 | /* Reject eight bit registers, except where the template requires |
7643 | them. (eg. movzb) */ | |
dc821c5f | 7644 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7645 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7646 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7647 | && (i.tm.operand_types[op].bitfield.word |
7648 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7649 | { |
a540244d L |
7650 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7651 | register_prefix, | |
29b0f896 AM |
7652 | i.op[op].regs->reg_name, |
7653 | i.tm.name, | |
7654 | i.suffix); | |
7655 | return 0; | |
7656 | } | |
9706160a JB |
7657 | /* Error if the e or r prefix on a general reg is present. */ |
7658 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 7659 | || i.types[op].bitfield.qword) |
bab6aec1 | 7660 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7661 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7662 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 7663 | { |
9706160a JB |
7664 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7665 | register_prefix, i.op[op].regs->reg_name, | |
7666 | i.suffix); | |
7667 | return 0; | |
29b0f896 AM |
7668 | } |
7669 | return 1; | |
7670 | } | |
252b5132 | 7671 | |
29b0f896 | 7672 | static int |
40fb9820 | 7673 | update_imm (unsigned int j) |
29b0f896 | 7674 | { |
bc0844ae | 7675 | i386_operand_type overlap = i.types[j]; |
be1643ff JB |
7676 | if (overlap.bitfield.imm8 |
7677 | + overlap.bitfield.imm8s | |
7678 | + overlap.bitfield.imm16 | |
7679 | + overlap.bitfield.imm32 | |
7680 | + overlap.bitfield.imm32s | |
7681 | + overlap.bitfield.imm64 > 1) | |
29b0f896 AM |
7682 | { |
7683 | if (i.suffix) | |
7684 | { | |
40fb9820 L |
7685 | i386_operand_type temp; |
7686 | ||
0dfbf9d7 | 7687 | operand_type_set (&temp, 0); |
7ab9ffdd | 7688 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
7689 | { |
7690 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
7691 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
7692 | } | |
7693 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7694 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
7695 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7696 | { | |
7697 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
7698 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
7699 | } | |
7700 | else | |
7701 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
7702 | overlap = temp; | |
29b0f896 | 7703 | } |
0dfbf9d7 L |
7704 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
7705 | || operand_type_equal (&overlap, &imm16_32) | |
7706 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 7707 | { |
40fb9820 | 7708 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 7709 | overlap = imm16; |
40fb9820 | 7710 | else |
65da13b5 | 7711 | overlap = imm32s; |
29b0f896 | 7712 | } |
8bbb3ad8 JB |
7713 | else if (i.prefix[REX_PREFIX] & REX_W) |
7714 | overlap = operand_type_and (overlap, imm32s); | |
7715 | else if (i.prefix[DATA_PREFIX]) | |
7716 | overlap = operand_type_and (overlap, | |
7717 | flag_code != CODE_16BIT ? imm16 : imm32); | |
be1643ff JB |
7718 | if (overlap.bitfield.imm8 |
7719 | + overlap.bitfield.imm8s | |
7720 | + overlap.bitfield.imm16 | |
7721 | + overlap.bitfield.imm32 | |
7722 | + overlap.bitfield.imm32s | |
7723 | + overlap.bitfield.imm64 != 1) | |
29b0f896 | 7724 | { |
4eed87de AM |
7725 | as_bad (_("no instruction mnemonic suffix given; " |
7726 | "can't determine immediate size")); | |
29b0f896 AM |
7727 | return 0; |
7728 | } | |
7729 | } | |
40fb9820 | 7730 | i.types[j] = overlap; |
29b0f896 | 7731 | |
40fb9820 L |
7732 | return 1; |
7733 | } | |
7734 | ||
7735 | static int | |
7736 | finalize_imm (void) | |
7737 | { | |
bc0844ae | 7738 | unsigned int j, n; |
29b0f896 | 7739 | |
bc0844ae L |
7740 | /* Update the first 2 immediate operands. */ |
7741 | n = i.operands > 2 ? 2 : i.operands; | |
7742 | if (n) | |
7743 | { | |
7744 | for (j = 0; j < n; j++) | |
7745 | if (update_imm (j) == 0) | |
7746 | return 0; | |
40fb9820 | 7747 | |
bc0844ae L |
7748 | /* The 3rd operand can't be immediate operand. */ |
7749 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7750 | } | |
29b0f896 AM |
7751 | |
7752 | return 1; | |
7753 | } | |
7754 | ||
7755 | static int | |
e3bb37b5 | 7756 | process_operands (void) |
29b0f896 AM |
7757 | { |
7758 | /* Default segment register this instruction will use for memory | |
7759 | accesses. 0 means unknown. This is only for optimizing out | |
7760 | unnecessary segment overrides. */ | |
5e042380 | 7761 | const reg_entry *default_seg = NULL; |
29b0f896 | 7762 | |
a5aeccd9 JB |
7763 | if (i.tm.opcode_modifier.sse2avx) |
7764 | { | |
7765 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
7766 | need converting. */ | |
7767 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
7768 | i.prefix[REX_PREFIX] = 0; | |
7769 | i.rex_encoding = 0; | |
7770 | } | |
c423d21a JB |
7771 | /* ImmExt should be processed after SSE2AVX. */ |
7772 | else if (i.tm.opcode_modifier.immext) | |
7773 | process_immext (); | |
a5aeccd9 | 7774 | |
2426c15f | 7775 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7776 | { |
91d6fa6a NC |
7777 | unsigned int dupl = i.operands; |
7778 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7779 | unsigned int j; |
7780 | ||
c0f3af97 | 7781 | /* The destination must be an xmm register. */ |
9c2799c2 | 7782 | gas_assert (i.reg_operands |
91d6fa6a | 7783 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7784 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7785 | |
75e5731b | 7786 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7787 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7788 | { |
8cd7925b | 7789 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7790 | { |
7791 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7792 | sources. */ | |
75e5731b | 7793 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7794 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7795 | goto duplicate; |
7796 | } | |
e2ec9d29 | 7797 | else |
c0f3af97 L |
7798 | { |
7799 | /* We remove the first xmm0 and keep the number of | |
7800 | operands unchanged, which in fact duplicates the | |
7801 | destination. */ | |
7802 | for (j = 1; j < i.operands; j++) | |
7803 | { | |
7804 | i.op[j - 1] = i.op[j]; | |
7805 | i.types[j - 1] = i.types[j]; | |
7806 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7807 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7808 | } |
7809 | } | |
7810 | } | |
7811 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7812 | { |
91d6fa6a | 7813 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7814 | && (i.tm.opcode_modifier.vexsources |
7815 | == VEX3SOURCES)); | |
c0f3af97 L |
7816 | |
7817 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7818 | and 3 sources. */ | |
7819 | for (j = i.operands; j > 0; j--) | |
7820 | { | |
7821 | i.op[j] = i.op[j - 1]; | |
7822 | i.types[j] = i.types[j - 1]; | |
7823 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7824 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7825 | } |
7826 | i.op[0].regs | |
629310ab | 7827 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 7828 | i.types[0] = regxmm; |
c0f3af97 L |
7829 | i.tm.operand_types[0] = regxmm; |
7830 | ||
7831 | i.operands += 2; | |
7832 | i.reg_operands += 2; | |
7833 | i.tm.operands += 2; | |
7834 | ||
91d6fa6a | 7835 | dupl++; |
c0f3af97 | 7836 | dest++; |
91d6fa6a NC |
7837 | i.op[dupl] = i.op[dest]; |
7838 | i.types[dupl] = i.types[dest]; | |
7839 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7840 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7841 | } |
c0f3af97 L |
7842 | else |
7843 | { | |
dc1e8a47 | 7844 | duplicate: |
c0f3af97 L |
7845 | i.operands++; |
7846 | i.reg_operands++; | |
7847 | i.tm.operands++; | |
7848 | ||
91d6fa6a NC |
7849 | i.op[dupl] = i.op[dest]; |
7850 | i.types[dupl] = i.types[dest]; | |
7851 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7852 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7853 | } |
7854 | ||
7855 | if (i.tm.opcode_modifier.immext) | |
7856 | process_immext (); | |
7857 | } | |
75e5731b | 7858 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7859 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7860 | { |
7861 | unsigned int j; | |
7862 | ||
9fcfb3d7 L |
7863 | for (j = 1; j < i.operands; j++) |
7864 | { | |
7865 | i.op[j - 1] = i.op[j]; | |
7866 | i.types[j - 1] = i.types[j]; | |
7867 | ||
7868 | /* We need to adjust fields in i.tm since they are used by | |
7869 | build_modrm_byte. */ | |
7870 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7871 | |
7872 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7873 | } |
7874 | ||
e2ec9d29 L |
7875 | i.operands--; |
7876 | i.reg_operands--; | |
e2ec9d29 L |
7877 | i.tm.operands--; |
7878 | } | |
920d2ddc IT |
7879 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7880 | { | |
a477a8c4 JB |
7881 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7882 | ||
920d2ddc | 7883 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7884 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7885 | regnum = register_number (i.op[1].regs); |
7886 | first_reg_in_group = regnum & ~3; | |
7887 | last_reg_in_group = first_reg_in_group + 3; | |
7888 | if (regnum != first_reg_in_group) | |
7889 | as_warn (_("source register `%s%s' implicitly denotes" | |
7890 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7891 | register_prefix, i.op[1].regs->reg_name, | |
7892 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7893 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7894 | i.tm.name); | |
7895 | } | |
e2ec9d29 L |
7896 | else if (i.tm.opcode_modifier.regkludge) |
7897 | { | |
7898 | /* The imul $imm, %reg instruction is converted into | |
7899 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7900 | is converted into xor %reg, %reg. */ | |
7901 | ||
7902 | unsigned int first_reg_op; | |
7903 | ||
7904 | if (operand_type_check (i.types[0], reg)) | |
7905 | first_reg_op = 0; | |
7906 | else | |
7907 | first_reg_op = 1; | |
7908 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7909 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7910 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7911 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7912 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7913 | i.operands++; | |
7914 | i.reg_operands++; | |
29b0f896 AM |
7915 | } |
7916 | ||
85b80b0f | 7917 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7918 | { |
7919 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7920 | must be put into the modrm byte). Now, we make the modrm and |
7921 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7922 | |
7923 | default_seg = build_modrm_byte (); | |
7924 | } | |
00cee14f | 7925 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7926 | { |
7927 | if (flag_code != CODE_64BIT | |
7928 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7929 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 7930 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
7931 | && i.op[0].regs->reg_num < 4) |
7932 | { | |
7933 | as_bad (_("you can't `%s %s%s'"), | |
7934 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7935 | return 0; | |
7936 | } | |
389d00a5 JB |
7937 | if (i.op[0].regs->reg_num > 3 |
7938 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE ) | |
85b80b0f | 7939 | { |
389d00a5 JB |
7940 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
7941 | i.tm.opcode_modifier.opcodespace = SPACE_0F; | |
85b80b0f JB |
7942 | } |
7943 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7944 | } | |
389d00a5 JB |
7945 | else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
7946 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) | |
29b0f896 | 7947 | { |
5e042380 | 7948 | default_seg = reg_ds; |
29b0f896 | 7949 | } |
40fb9820 | 7950 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7951 | { |
7952 | /* For the string instructions that allow a segment override | |
7953 | on one of their operands, the default segment is ds. */ | |
5e042380 | 7954 | default_seg = reg_ds; |
29b0f896 | 7955 | } |
50128d0c | 7956 | else if (i.short_form) |
85b80b0f JB |
7957 | { |
7958 | /* The register or float register operand is in operand | |
7959 | 0 or 1. */ | |
bab6aec1 | 7960 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7961 | |
7962 | /* Register goes in low 3 bits of opcode. */ | |
7963 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7964 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7965 | i.rex |= REX_B; | |
7966 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7967 | { | |
7968 | /* Warn about some common errors, but press on regardless. | |
7969 | The first case can be generated by gcc (<= 2.8.1). */ | |
7970 | if (i.operands == 2) | |
7971 | { | |
7972 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7973 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7974 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7975 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7976 | } | |
7977 | else | |
7978 | { | |
7979 | /* Extraneous `l' suffix on fp insn. */ | |
7980 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7981 | register_prefix, i.op[0].regs->reg_name); | |
7982 | } | |
7983 | } | |
7984 | } | |
29b0f896 | 7985 | |
514a8bb0 | 7986 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 | 7987 | && i.tm.base_opcode == 0x8d /* lea */ |
35648716 | 7988 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
514a8bb0 | 7989 | && !is_any_vex_encoding(&i.tm)) |
92334ad2 JB |
7990 | { |
7991 | if (!quiet_warnings) | |
7992 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7993 | if (optimize) | |
7994 | { | |
7995 | i.seg[0] = NULL; | |
7996 | i.prefix[SEG_PREFIX] = 0; | |
7997 | } | |
7998 | } | |
52271982 AM |
7999 | |
8000 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
8001 | is neither the default nor the one already recorded from a prefix, |
8002 | use an opcode prefix to select it. If we never figured out what | |
8003 | the default segment is, then default_seg will be zero at this | |
8004 | point, and the specified segment prefix will always be used. */ | |
8005 | if (i.seg[0] | |
8006 | && i.seg[0] != default_seg | |
5e042380 | 8007 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 8008 | { |
5e042380 | 8009 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
8010 | return 0; |
8011 | } | |
8012 | return 1; | |
8013 | } | |
8014 | ||
a5aeccd9 | 8015 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
5b7c81bd | 8016 | bool do_sse2avx) |
a5aeccd9 JB |
8017 | { |
8018 | if (r->reg_flags & RegRex) | |
8019 | { | |
8020 | if (i.rex & rex_bit) | |
8021 | as_bad (_("same type of prefix used twice")); | |
8022 | i.rex |= rex_bit; | |
8023 | } | |
8024 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
8025 | { | |
8026 | gas_assert (i.vex.register_specifier == r); | |
8027 | i.vex.register_specifier += 8; | |
8028 | } | |
8029 | ||
8030 | if (r->reg_flags & RegVRex) | |
8031 | i.vrex |= rex_bit; | |
8032 | } | |
8033 | ||
5e042380 | 8034 | static const reg_entry * |
e3bb37b5 | 8035 | build_modrm_byte (void) |
29b0f896 | 8036 | { |
5e042380 | 8037 | const reg_entry *default_seg = NULL; |
c0f3af97 | 8038 | unsigned int source, dest; |
8cd7925b | 8039 | int vex_3_sources; |
c0f3af97 | 8040 | |
8cd7925b | 8041 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
8042 | if (vex_3_sources) |
8043 | { | |
91d6fa6a | 8044 | unsigned int nds, reg_slot; |
4c2c6516 | 8045 | expressionS *exp; |
c0f3af97 | 8046 | |
6b8d3588 | 8047 | dest = i.operands - 1; |
c0f3af97 | 8048 | nds = dest - 1; |
922d8de8 | 8049 | |
a683cc34 | 8050 | /* There are 2 kinds of instructions: |
bed3d976 | 8051 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 8052 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 8053 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 8054 | ZMM register. |
bed3d976 | 8055 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 8056 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 8057 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
8058 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
8059 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 8060 | && i.tm.opcode_modifier.vexw |
3528c362 | 8061 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 8062 | |
48db9223 JB |
8063 | /* If VexW1 is set, the first non-immediate operand is the source and |
8064 | the second non-immediate one is encoded in the immediate operand. */ | |
8065 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
8066 | { | |
8067 | source = i.imm_operands; | |
8068 | reg_slot = i.imm_operands + 1; | |
8069 | } | |
8070 | else | |
8071 | { | |
8072 | source = i.imm_operands + 1; | |
8073 | reg_slot = i.imm_operands; | |
8074 | } | |
8075 | ||
a683cc34 | 8076 | if (i.imm_operands == 0) |
bed3d976 JB |
8077 | { |
8078 | /* When there is no immediate operand, generate an 8bit | |
8079 | immediate operand to encode the first operand. */ | |
8080 | exp = &im_expressions[i.imm_operands++]; | |
8081 | i.op[i.operands].imms = exp; | |
be1643ff | 8082 | i.types[i.operands].bitfield.imm8 = 1; |
bed3d976 JB |
8083 | i.operands++; |
8084 | ||
3528c362 | 8085 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
8086 | exp->X_op = O_constant; |
8087 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
8088 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
8089 | } | |
922d8de8 | 8090 | else |
bed3d976 | 8091 | { |
9d3bf266 JB |
8092 | gas_assert (i.imm_operands == 1); |
8093 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
8094 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 8095 | |
9d3bf266 JB |
8096 | /* Turn on Imm8 again so that output_imm will generate it. */ |
8097 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 8098 | |
3528c362 | 8099 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 8100 | i.op[0].imms->X_add_number |
bed3d976 | 8101 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 8102 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 8103 | } |
a683cc34 | 8104 | |
3528c362 | 8105 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 8106 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
8107 | } |
8108 | else | |
8109 | source = dest = 0; | |
29b0f896 AM |
8110 | |
8111 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
8112 | implicit registers do not count. If there are 3 register |
8113 | operands, it must be a instruction with VexNDS. For a | |
8114 | instruction with VexNDD, the destination register is encoded | |
8115 | in VEX prefix. If there are 4 register operands, it must be | |
8116 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
8117 | if (i.mem_operands == 0 |
8118 | && ((i.reg_operands == 2 | |
2426c15f | 8119 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 8120 | || (i.reg_operands == 3 |
2426c15f | 8121 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 8122 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 8123 | { |
cab737b9 L |
8124 | switch (i.operands) |
8125 | { | |
8126 | case 2: | |
8127 | source = 0; | |
8128 | break; | |
8129 | case 3: | |
c81128dc L |
8130 | /* When there are 3 operands, one of them may be immediate, |
8131 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
8132 | the first operand must be shift count register (cl) or it |
8133 | is an instruction with VexNDS. */ | |
9c2799c2 | 8134 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 8135 | || (i.imm_operands == 0 |
2426c15f | 8136 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
8137 | || (i.types[0].bitfield.instance == RegC |
8138 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 8139 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
8140 | || (i.types[0].bitfield.instance == RegC |
8141 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
8142 | source = 1; |
8143 | else | |
8144 | source = 0; | |
cab737b9 L |
8145 | break; |
8146 | case 4: | |
368d64cc L |
8147 | /* When there are 4 operands, the first two must be 8bit |
8148 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
8149 | one. |
8150 | ||
8151 | For instructions with VexNDS, if the first operand | |
8152 | an imm8, the source operand is the 2nd one. If the last | |
8153 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 8154 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
8155 | && i.types[0].bitfield.imm8 |
8156 | && i.types[1].bitfield.imm8) | |
2426c15f | 8157 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
8158 | && i.imm_operands == 1 |
8159 | && (i.types[0].bitfield.imm8 | |
cf665fee | 8160 | || i.types[i.operands - 1].bitfield.imm8))); |
9f2670f2 L |
8161 | if (i.imm_operands == 2) |
8162 | source = 2; | |
8163 | else | |
c0f3af97 L |
8164 | { |
8165 | if (i.types[0].bitfield.imm8) | |
8166 | source = 1; | |
8167 | else | |
8168 | source = 0; | |
8169 | } | |
c0f3af97 L |
8170 | break; |
8171 | case 5: | |
cf665fee JB |
8172 | gas_assert (!is_evex_encoding (&i.tm)); |
8173 | gas_assert (i.imm_operands == 1 && vex_3_sources); | |
cab737b9 L |
8174 | break; |
8175 | default: | |
8176 | abort (); | |
8177 | } | |
8178 | ||
c0f3af97 L |
8179 | if (!vex_3_sources) |
8180 | { | |
8181 | dest = source + 1; | |
8182 | ||
2426c15f | 8183 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 8184 | { |
43234a1e | 8185 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 8186 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 8187 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
8188 | |
8189 | i386_operand_type op; | |
8190 | unsigned int vvvv; | |
8191 | ||
c2ecccb3 L |
8192 | /* Swap two source operands if needed. */ |
8193 | if (i.tm.opcode_modifier.swapsources) | |
f12dc422 L |
8194 | { |
8195 | vvvv = source; | |
8196 | source = dest; | |
8197 | } | |
8198 | else | |
8199 | vvvv = dest; | |
8200 | ||
8201 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 8202 | if ((dest + 1) >= i.operands |
bab6aec1 | 8203 | || ((op.bitfield.class != Reg |
dc821c5f | 8204 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 8205 | && op.bitfield.class != RegSIMD |
c0f327b8 | 8206 | && op.bitfield.class != RegMask)) |
c0f3af97 | 8207 | abort (); |
f12dc422 | 8208 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
8209 | dest++; |
8210 | } | |
8211 | } | |
29b0f896 AM |
8212 | |
8213 | i.rm.mode = 3; | |
dfd69174 JB |
8214 | /* One of the register operands will be encoded in the i.rm.reg |
8215 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
8216 | fields. If no form of this instruction supports a memory |
8217 | destination operand, then we assume the source operand may | |
8218 | sometimes be a memory operand and so we need to store the | |
8219 | destination in the i.rm.reg field. */ | |
dfd69174 | 8220 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 8221 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
8222 | { |
8223 | i.rm.reg = i.op[dest].regs->reg_num; | |
8224 | i.rm.regmem = i.op[source].regs->reg_num; | |
a5aeccd9 | 8225 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8226 | set_rex_vrex (i.op[source].regs, REX_B, false); |
29b0f896 AM |
8227 | } |
8228 | else | |
8229 | { | |
8230 | i.rm.reg = i.op[source].regs->reg_num; | |
8231 | i.rm.regmem = i.op[dest].regs->reg_num; | |
a5aeccd9 | 8232 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8233 | set_rex_vrex (i.op[source].regs, REX_R, false); |
29b0f896 | 8234 | } |
e0c7f900 | 8235 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 8236 | { |
4a5c67ed | 8237 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 8238 | abort (); |
e0c7f900 | 8239 | i.rex &= ~REX_R; |
c4a530c5 JB |
8240 | add_prefix (LOCK_PREFIX_OPCODE); |
8241 | } | |
29b0f896 AM |
8242 | } |
8243 | else | |
8244 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
8245 | unsigned int mem; |
8246 | ||
29b0f896 AM |
8247 | if (i.mem_operands) |
8248 | { | |
8249 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 8250 | unsigned int op; |
4eed87de | 8251 | |
7ab9ffdd | 8252 | for (op = 0; op < i.operands; op++) |
8dc0818e | 8253 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 8254 | break; |
7ab9ffdd | 8255 | gas_assert (op < i.operands); |
29b0f896 | 8256 | |
63112cd6 | 8257 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 8258 | { |
260cd341 LC |
8259 | /* The index register of VSIB shouldn't be RegIZ. */ |
8260 | if (i.tm.opcode_modifier.sib != SIBMEM | |
8261 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
8262 | abort (); |
8263 | ||
8264 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8265 | if (!i.base_reg) | |
8266 | { | |
8267 | i.sib.base = NO_BASE_REGISTER; | |
8268 | i.sib.scale = i.log2_scale_factor; | |
2f2be86b | 8269 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 8270 | i.types[op].bitfield.disp32 = 1; |
6c30d220 | 8271 | } |
260cd341 LC |
8272 | |
8273 | /* Since the mandatory SIB always has index register, so | |
8274 | the code logic remains unchanged. The non-mandatory SIB | |
8275 | without index register is allowed and will be handled | |
8276 | later. */ | |
8277 | if (i.index_reg) | |
8278 | { | |
8279 | if (i.index_reg->reg_num == RegIZ) | |
8280 | i.sib.index = NO_INDEX_REGISTER; | |
8281 | else | |
8282 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 8283 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 8284 | } |
6c30d220 L |
8285 | } |
8286 | ||
5e042380 | 8287 | default_seg = reg_ds; |
29b0f896 AM |
8288 | |
8289 | if (i.base_reg == 0) | |
8290 | { | |
8291 | i.rm.mode = 0; | |
8292 | if (!i.disp_operands) | |
9bb129e8 | 8293 | fake_zero_displacement = 1; |
29b0f896 AM |
8294 | if (i.index_reg == 0) |
8295 | { | |
260cd341 LC |
8296 | /* Both check for VSIB and mandatory non-vector SIB. */ |
8297 | gas_assert (!i.tm.opcode_modifier.sib | |
8298 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 8299 | /* Operand is just <disp> */ |
2f2be86b | 8300 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
20f0a1fc | 8301 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
8302 | { |
8303 | /* 64bit mode overwrites the 32bit absolute | |
8304 | addressing by RIP relative addressing and | |
8305 | absolute addressing is encoded by one of the | |
8306 | redundant SIB forms. */ | |
8307 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8308 | i.sib.base = NO_BASE_REGISTER; | |
8309 | i.sib.index = NO_INDEX_REGISTER; | |
a775efc8 | 8310 | i.types[op].bitfield.disp32 = 1; |
20f0a1fc | 8311 | } |
fc225355 L |
8312 | else if ((flag_code == CODE_16BIT) |
8313 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
8314 | { |
8315 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2f2be86b | 8316 | i.types[op].bitfield.disp16 = 1; |
20f0a1fc NC |
8317 | } |
8318 | else | |
8319 | { | |
8320 | i.rm.regmem = NO_BASE_REGISTER; | |
2f2be86b | 8321 | i.types[op].bitfield.disp32 = 1; |
29b0f896 AM |
8322 | } |
8323 | } | |
63112cd6 | 8324 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8325 | { |
6c30d220 | 8326 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 8327 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8328 | i.sib.index = NO_INDEX_REGISTER; |
8329 | else | |
8330 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8331 | i.sib.base = NO_BASE_REGISTER; |
8332 | i.sib.scale = i.log2_scale_factor; | |
8333 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2f2be86b | 8334 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 8335 | i.types[op].bitfield.disp32 = 1; |
29b0f896 | 8336 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8337 | i.rex |= REX_X; |
29b0f896 AM |
8338 | } |
8339 | } | |
8340 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 8341 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 8342 | { |
63112cd6 | 8343 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 8344 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
8345 | i.types[op].bitfield.disp8 = 0; |
8346 | i.types[op].bitfield.disp16 = 0; | |
a775efc8 | 8347 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 8348 | i.types[op].bitfield.disp64 = 0; |
71903a11 | 8349 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
8350 | if (! i.disp_operands) |
8351 | fake_zero_displacement = 1; | |
29b0f896 | 8352 | } |
dc821c5f | 8353 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 8354 | { |
63112cd6 | 8355 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
8356 | switch (i.base_reg->reg_num) |
8357 | { | |
8358 | case 3: /* (%bx) */ | |
8359 | if (i.index_reg == 0) | |
8360 | i.rm.regmem = 7; | |
8361 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
8362 | i.rm.regmem = i.index_reg->reg_num - 6; | |
8363 | break; | |
8364 | case 5: /* (%bp) */ | |
5e042380 | 8365 | default_seg = reg_ss; |
29b0f896 AM |
8366 | if (i.index_reg == 0) |
8367 | { | |
8368 | i.rm.regmem = 6; | |
40fb9820 | 8369 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
8370 | { |
8371 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 8372 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
8373 | i.types[op].bitfield.disp16 = 1; |
8374 | else | |
8375 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 8376 | fake_zero_displacement = 1; |
29b0f896 AM |
8377 | } |
8378 | } | |
8379 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
8380 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
8381 | break; | |
8382 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
8383 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
8384 | } | |
41eb8e88 L |
8385 | if (!fake_zero_displacement |
8386 | && !i.disp_operands | |
8387 | && i.disp_encoding) | |
8388 | { | |
8389 | fake_zero_displacement = 1; | |
8390 | if (i.disp_encoding == disp_encoding_8bit) | |
8391 | i.types[op].bitfield.disp8 = 1; | |
8392 | else | |
8393 | i.types[op].bitfield.disp16 = 1; | |
8394 | } | |
29b0f896 AM |
8395 | i.rm.mode = mode_from_disp_size (i.types[op]); |
8396 | } | |
8397 | else /* i.base_reg and 32/64 bit mode */ | |
8398 | { | |
a9aabc23 | 8399 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 8400 | { |
73053c1f JB |
8401 | i.types[op].bitfield.disp16 = 0; |
8402 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 8403 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 8404 | } |
20f0a1fc | 8405 | |
63112cd6 | 8406 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 8407 | i.rm.regmem = i.base_reg->reg_num; |
29b0f896 | 8408 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8409 | i.rex |= REX_B; |
29b0f896 AM |
8410 | i.sib.base = i.base_reg->reg_num; |
8411 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
8412 | complications. */ | |
848930b2 JB |
8413 | if (!(i.base_reg->reg_flags & RegRex) |
8414 | && (i.base_reg->reg_num == EBP_REG_NUM | |
8415 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 8416 | default_seg = reg_ss; |
848930b2 | 8417 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 8418 | { |
848930b2 | 8419 | fake_zero_displacement = 1; |
1a02d6b0 L |
8420 | if (i.disp_encoding == disp_encoding_32bit) |
8421 | i.types[op].bitfield.disp32 = 1; | |
8422 | else | |
8423 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
8424 | } |
8425 | i.sib.scale = i.log2_scale_factor; | |
8426 | if (i.index_reg == 0) | |
8427 | { | |
260cd341 LC |
8428 | /* Only check for VSIB. */ |
8429 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
8430 | && i.tm.opcode_modifier.sib != VECSIB256 | |
8431 | && i.tm.opcode_modifier.sib != VECSIB512); | |
8432 | ||
29b0f896 AM |
8433 | /* <disp>(%esp) becomes two byte modrm with no index |
8434 | register. We've already stored the code for esp | |
8435 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
8436 | Any base register besides %esp will not use the | |
8437 | extra modrm byte. */ | |
8438 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 8439 | } |
63112cd6 | 8440 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8441 | { |
e968fc9b | 8442 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8443 | i.sib.index = NO_INDEX_REGISTER; |
8444 | else | |
8445 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8446 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
8447 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 8448 | i.rex |= REX_X; |
29b0f896 | 8449 | } |
67a4f2b7 AO |
8450 | |
8451 | if (i.disp_operands | |
8452 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
8453 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
8454 | i.rm.mode = 0; | |
8455 | else | |
a501d77e L |
8456 | { |
8457 | if (!fake_zero_displacement | |
8458 | && !i.disp_operands | |
8459 | && i.disp_encoding) | |
8460 | { | |
8461 | fake_zero_displacement = 1; | |
8462 | if (i.disp_encoding == disp_encoding_8bit) | |
8463 | i.types[op].bitfield.disp8 = 1; | |
8464 | else | |
8465 | i.types[op].bitfield.disp32 = 1; | |
8466 | } | |
8467 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8468 | } | |
29b0f896 | 8469 | } |
252b5132 | 8470 | |
29b0f896 AM |
8471 | if (fake_zero_displacement) |
8472 | { | |
8473 | /* Fakes a zero displacement assuming that i.types[op] | |
8474 | holds the correct displacement size. */ | |
8475 | expressionS *exp; | |
8476 | ||
9c2799c2 | 8477 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
8478 | exp = &disp_expressions[i.disp_operands++]; |
8479 | i.op[op].disps = exp; | |
8480 | exp->X_op = O_constant; | |
8481 | exp->X_add_number = 0; | |
8482 | exp->X_add_symbol = (symbolS *) 0; | |
8483 | exp->X_op_symbol = (symbolS *) 0; | |
8484 | } | |
c0f3af97 L |
8485 | |
8486 | mem = op; | |
29b0f896 | 8487 | } |
c0f3af97 L |
8488 | else |
8489 | mem = ~0; | |
252b5132 | 8490 | |
8c43a48b | 8491 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
8492 | { |
8493 | if (operand_type_check (i.types[0], imm)) | |
8494 | i.vex.register_specifier = NULL; | |
8495 | else | |
8496 | { | |
8497 | /* VEX.vvvv encodes one of the sources when the first | |
8498 | operand is not an immediate. */ | |
1ef99a7b | 8499 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8500 | i.vex.register_specifier = i.op[0].regs; |
8501 | else | |
8502 | i.vex.register_specifier = i.op[1].regs; | |
8503 | } | |
8504 | ||
8505 | /* Destination is a XMM register encoded in the ModRM.reg | |
8506 | and VEX.R bit. */ | |
8507 | i.rm.reg = i.op[2].regs->reg_num; | |
8508 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
8509 | i.rex |= REX_R; | |
8510 | ||
8511 | /* ModRM.rm and VEX.B encodes the other source. */ | |
8512 | if (!i.mem_operands) | |
8513 | { | |
8514 | i.rm.mode = 3; | |
8515 | ||
1ef99a7b | 8516 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8517 | i.rm.regmem = i.op[1].regs->reg_num; |
8518 | else | |
8519 | i.rm.regmem = i.op[0].regs->reg_num; | |
8520 | ||
8521 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8522 | i.rex |= REX_B; | |
8523 | } | |
8524 | } | |
2426c15f | 8525 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
8526 | { |
8527 | i.vex.register_specifier = i.op[2].regs; | |
8528 | if (!i.mem_operands) | |
8529 | { | |
8530 | i.rm.mode = 3; | |
8531 | i.rm.regmem = i.op[1].regs->reg_num; | |
8532 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8533 | i.rex |= REX_B; | |
8534 | } | |
8535 | } | |
29b0f896 AM |
8536 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
8537 | (if any) based on i.tm.extension_opcode. Again, we must be | |
8538 | careful to make sure that segment/control/debug/test/MMX | |
8539 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 8540 | else if (i.reg_operands) |
29b0f896 | 8541 | { |
99018f42 | 8542 | unsigned int op; |
7ab9ffdd L |
8543 | unsigned int vex_reg = ~0; |
8544 | ||
8545 | for (op = 0; op < i.operands; op++) | |
921eafea L |
8546 | if (i.types[op].bitfield.class == Reg |
8547 | || i.types[op].bitfield.class == RegBND | |
8548 | || i.types[op].bitfield.class == RegMask | |
8549 | || i.types[op].bitfield.class == SReg | |
8550 | || i.types[op].bitfield.class == RegCR | |
8551 | || i.types[op].bitfield.class == RegDR | |
8552 | || i.types[op].bitfield.class == RegTR | |
8553 | || i.types[op].bitfield.class == RegSIMD | |
8554 | || i.types[op].bitfield.class == RegMMX) | |
8555 | break; | |
c0209578 | 8556 | |
7ab9ffdd L |
8557 | if (vex_3_sources) |
8558 | op = dest; | |
2426c15f | 8559 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
8560 | { |
8561 | /* For instructions with VexNDS, the register-only | |
8562 | source operand is encoded in VEX prefix. */ | |
8563 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 8564 | |
a93e3234 | 8565 | if (op > mem || i.tm.cpu_flags.bitfield.cpucmpccxadd) |
c0f3af97 | 8566 | { |
7ab9ffdd L |
8567 | vex_reg = op++; |
8568 | gas_assert (op < i.operands); | |
c0f3af97 L |
8569 | } |
8570 | else | |
c0f3af97 | 8571 | { |
f12dc422 L |
8572 | /* Check register-only source operand when two source |
8573 | operands are swapped. */ | |
8574 | if (!i.tm.operand_types[op].bitfield.baseindex | |
8575 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
8576 | { | |
8577 | vex_reg = op; | |
8578 | op += 2; | |
8579 | gas_assert (mem == (vex_reg + 1) | |
8580 | && op < i.operands); | |
8581 | } | |
8582 | else | |
8583 | { | |
8584 | vex_reg = op + 1; | |
8585 | gas_assert (vex_reg < i.operands); | |
8586 | } | |
c0f3af97 | 8587 | } |
7ab9ffdd | 8588 | } |
2426c15f | 8589 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 8590 | { |
f12dc422 | 8591 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 8592 | is encoded in VEX prefix. */ |
f12dc422 L |
8593 | if (i.mem_operands == 0) |
8594 | { | |
8595 | /* There is no memory operand. */ | |
8596 | gas_assert ((op + 2) == i.operands); | |
8597 | vex_reg = op + 1; | |
8598 | } | |
8599 | else | |
8d63c93e | 8600 | { |
ed438a93 JB |
8601 | /* There are only 2 non-immediate operands. */ |
8602 | gas_assert (op < i.imm_operands + 2 | |
8603 | && i.operands == i.imm_operands + 2); | |
8604 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 8605 | } |
7ab9ffdd L |
8606 | } |
8607 | else | |
8608 | gas_assert (op < i.operands); | |
99018f42 | 8609 | |
7ab9ffdd L |
8610 | if (vex_reg != (unsigned int) ~0) |
8611 | { | |
f12dc422 | 8612 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 8613 | |
bab6aec1 | 8614 | if ((type->bitfield.class != Reg |
dc821c5f | 8615 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 8616 | && type->bitfield.class != RegSIMD |
c0f327b8 | 8617 | && type->bitfield.class != RegMask) |
7ab9ffdd | 8618 | abort (); |
f88c9eb0 | 8619 | |
7ab9ffdd L |
8620 | i.vex.register_specifier = i.op[vex_reg].regs; |
8621 | } | |
8622 | ||
1b9f0c97 L |
8623 | /* Don't set OP operand twice. */ |
8624 | if (vex_reg != op) | |
7ab9ffdd | 8625 | { |
1b9f0c97 L |
8626 | /* If there is an extension opcode to put here, the |
8627 | register number must be put into the regmem field. */ | |
8628 | if (i.tm.extension_opcode != None) | |
8629 | { | |
8630 | i.rm.regmem = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8631 | set_rex_vrex (i.op[op].regs, REX_B, |
8632 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 L |
8633 | } |
8634 | else | |
8635 | { | |
8636 | i.rm.reg = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8637 | set_rex_vrex (i.op[op].regs, REX_R, |
8638 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 | 8639 | } |
7ab9ffdd | 8640 | } |
252b5132 | 8641 | |
29b0f896 AM |
8642 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
8643 | must set it to 3 to indicate this is a register operand | |
8644 | in the regmem field. */ | |
8645 | if (!i.mem_operands) | |
8646 | i.rm.mode = 3; | |
8647 | } | |
252b5132 | 8648 | |
29b0f896 | 8649 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 8650 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
8651 | i.rm.reg = i.tm.extension_opcode; |
8652 | } | |
8653 | return default_seg; | |
8654 | } | |
252b5132 | 8655 | |
48ef937e JB |
8656 | static INLINE void |
8657 | frag_opcode_byte (unsigned char byte) | |
8658 | { | |
8659 | if (now_seg != absolute_section) | |
8660 | FRAG_APPEND_1_CHAR (byte); | |
8661 | else | |
8662 | ++abs_section_offset; | |
8663 | } | |
8664 | ||
376cd056 JB |
8665 | static unsigned int |
8666 | flip_code16 (unsigned int code16) | |
8667 | { | |
8668 | gas_assert (i.tm.operands == 1); | |
8669 | ||
8670 | return !(i.prefix[REX_PREFIX] & REX_W) | |
8671 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
376cd056 JB |
8672 | : i.tm.operand_types[0].bitfield.disp16) |
8673 | ? CODE16 : 0; | |
8674 | } | |
8675 | ||
29b0f896 | 8676 | static void |
e3bb37b5 | 8677 | output_branch (void) |
29b0f896 AM |
8678 | { |
8679 | char *p; | |
f8a5c266 | 8680 | int size; |
29b0f896 AM |
8681 | int code16; |
8682 | int prefix; | |
8683 | relax_substateT subtype; | |
8684 | symbolS *sym; | |
8685 | offsetT off; | |
8686 | ||
48ef937e JB |
8687 | if (now_seg == absolute_section) |
8688 | { | |
8689 | as_bad (_("relaxable branches not supported in absolute section")); | |
8690 | return; | |
8691 | } | |
8692 | ||
f8a5c266 | 8693 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
1a42a9fe | 8694 | size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL; |
29b0f896 AM |
8695 | |
8696 | prefix = 0; | |
8697 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8698 | { |
29b0f896 AM |
8699 | prefix = 1; |
8700 | i.prefixes -= 1; | |
376cd056 | 8701 | code16 ^= flip_code16(code16); |
252b5132 | 8702 | } |
29b0f896 AM |
8703 | /* Pentium4 branch hints. */ |
8704 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8705 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8706 | { |
29b0f896 AM |
8707 | prefix++; |
8708 | i.prefixes--; | |
8709 | } | |
8710 | if (i.prefix[REX_PREFIX] != 0) | |
8711 | { | |
8712 | prefix++; | |
8713 | i.prefixes--; | |
2f66722d AM |
8714 | } |
8715 | ||
7e8b059b L |
8716 | /* BND prefixed jump. */ |
8717 | if (i.prefix[BND_PREFIX] != 0) | |
8718 | { | |
6cb0a70e JB |
8719 | prefix++; |
8720 | i.prefixes--; | |
7e8b059b L |
8721 | } |
8722 | ||
f2810fe0 JB |
8723 | if (i.prefixes != 0) |
8724 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8725 | |
8726 | /* It's always a symbol; End frag & setup for relax. | |
8727 | Make sure there is enough room in this frag for the largest | |
8728 | instruction we may generate in md_convert_frag. This is 2 | |
8729 | bytes for the opcode and room for the prefix and largest | |
8730 | displacement. */ | |
8731 | frag_grow (prefix + 2 + 4); | |
8732 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8733 | p = frag_more (prefix + 1); | |
8734 | if (i.prefix[DATA_PREFIX] != 0) | |
8735 | *p++ = DATA_PREFIX_OPCODE; | |
8736 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8737 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8738 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8739 | if (i.prefix[BND_PREFIX] != 0) |
8740 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8741 | if (i.prefix[REX_PREFIX] != 0) |
8742 | *p++ = i.prefix[REX_PREFIX]; | |
8743 | *p = i.tm.base_opcode; | |
8744 | ||
8745 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8746 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8747 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8748 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8749 | else |
f8a5c266 | 8750 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8751 | subtype |= code16; |
3e73aa7c | 8752 | |
29b0f896 AM |
8753 | sym = i.op[0].disps->X_add_symbol; |
8754 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8755 | |
29b0f896 AM |
8756 | if (i.op[0].disps->X_op != O_constant |
8757 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8758 | { |
29b0f896 AM |
8759 | /* Handle complex expressions. */ |
8760 | sym = make_expr_symbol (i.op[0].disps); | |
8761 | off = 0; | |
8762 | } | |
3e73aa7c | 8763 | |
1ef3994a JB |
8764 | frag_now->tc_frag_data.code64 = flag_code == CODE_64BIT; |
8765 | ||
29b0f896 AM |
8766 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8767 | Pass reloc in fr_var. */ | |
d258b828 | 8768 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8769 | } |
3e73aa7c | 8770 | |
bd7ab16b L |
8771 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8772 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8773 | symbol S. */ | |
8774 | ||
5b7c81bd | 8775 | static bool |
bd7ab16b L |
8776 | need_plt32_p (symbolS *s) |
8777 | { | |
8778 | /* PLT32 relocation is ELF only. */ | |
8779 | if (!IS_ELF) | |
5b7c81bd | 8780 | return false; |
bd7ab16b | 8781 | |
a5def729 RO |
8782 | #ifdef TE_SOLARIS |
8783 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8784 | krtld support it. */ | |
5b7c81bd | 8785 | return false; |
a5def729 RO |
8786 | #endif |
8787 | ||
bd7ab16b L |
8788 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8789 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8790 | be used as a marker for 32-bit PC-relative branches. */ | |
8791 | if (!object_64bit) | |
5b7c81bd | 8792 | return false; |
bd7ab16b | 8793 | |
44365e88 | 8794 | if (s == NULL) |
5b7c81bd | 8795 | return false; |
44365e88 | 8796 | |
bd7ab16b L |
8797 | /* Weak or undefined symbol need PLT32 relocation. */ |
8798 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 8799 | return true; |
bd7ab16b L |
8800 | |
8801 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8802 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 8803 | return false; |
bd7ab16b L |
8804 | |
8805 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8806 | non-default visibilities are treated as normal global symbol | |
8807 | so that PLT32 relocation can be used as a marker for 32-bit | |
8808 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 8809 | return true; |
bd7ab16b L |
8810 | } |
8811 | #endif | |
8812 | ||
29b0f896 | 8813 | static void |
e3bb37b5 | 8814 | output_jump (void) |
29b0f896 AM |
8815 | { |
8816 | char *p; | |
8817 | int size; | |
3e02c1cc | 8818 | fixS *fixP; |
bd7ab16b | 8819 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8820 | |
0cfa3eb3 | 8821 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8822 | { |
8823 | /* This is a loop or jecxz type instruction. */ | |
8824 | size = 1; | |
8825 | if (i.prefix[ADDR_PREFIX] != 0) | |
8826 | { | |
48ef937e | 8827 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
8828 | i.prefixes -= 1; |
8829 | } | |
8830 | /* Pentium4 branch hints. */ | |
8831 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8832 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8833 | { | |
48ef937e | 8834 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 8835 | i.prefixes--; |
3e73aa7c JH |
8836 | } |
8837 | } | |
29b0f896 AM |
8838 | else |
8839 | { | |
8840 | int code16; | |
3e73aa7c | 8841 | |
29b0f896 AM |
8842 | code16 = 0; |
8843 | if (flag_code == CODE_16BIT) | |
8844 | code16 = CODE16; | |
3e73aa7c | 8845 | |
29b0f896 AM |
8846 | if (i.prefix[DATA_PREFIX] != 0) |
8847 | { | |
48ef937e | 8848 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 8849 | i.prefixes -= 1; |
376cd056 | 8850 | code16 ^= flip_code16(code16); |
29b0f896 | 8851 | } |
252b5132 | 8852 | |
29b0f896 AM |
8853 | size = 4; |
8854 | if (code16) | |
8855 | size = 2; | |
8856 | } | |
9fcc94b6 | 8857 | |
6cb0a70e JB |
8858 | /* BND prefixed jump. */ |
8859 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8860 | { |
48ef937e | 8861 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8862 | i.prefixes -= 1; |
8863 | } | |
252b5132 | 8864 | |
6cb0a70e | 8865 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8866 | { |
48ef937e | 8867 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
8868 | i.prefixes -= 1; |
8869 | } | |
8870 | ||
f2810fe0 JB |
8871 | if (i.prefixes != 0) |
8872 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8873 | |
48ef937e JB |
8874 | if (now_seg == absolute_section) |
8875 | { | |
9a182d04 | 8876 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
8877 | return; |
8878 | } | |
8879 | ||
9a182d04 JB |
8880 | p = frag_more (i.opcode_length + size); |
8881 | switch (i.opcode_length) | |
42164a71 L |
8882 | { |
8883 | case 2: | |
8884 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8885 | /* Fall through. */ |
42164a71 L |
8886 | case 1: |
8887 | *p++ = i.tm.base_opcode; | |
8888 | break; | |
8889 | default: | |
8890 | abort (); | |
8891 | } | |
e0890092 | 8892 | |
bd7ab16b | 8893 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
8894 | if (flag_code == CODE_64BIT && size == 4 |
8895 | && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0 | |
bd7ab16b L |
8896 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
8897 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8898 | #endif | |
8899 | ||
8900 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8901 | ||
3e02c1cc | 8902 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8903 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 8904 | |
eb19308f JB |
8905 | /* All jumps handled here are signed, but don't unconditionally use a |
8906 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
8907 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
8908 | respectively. */ | |
8909 | switch (size) | |
8910 | { | |
8911 | case 1: | |
8912 | fixP->fx_signed = 1; | |
8913 | break; | |
8914 | ||
8915 | case 2: | |
8916 | if (i.tm.base_opcode == 0xc7f8) | |
8917 | fixP->fx_signed = 1; | |
8918 | break; | |
8919 | ||
8920 | case 4: | |
8921 | if (flag_code == CODE_64BIT) | |
8922 | fixP->fx_signed = 1; | |
8923 | break; | |
8924 | } | |
29b0f896 | 8925 | } |
e0890092 | 8926 | |
29b0f896 | 8927 | static void |
e3bb37b5 | 8928 | output_interseg_jump (void) |
29b0f896 AM |
8929 | { |
8930 | char *p; | |
8931 | int size; | |
8932 | int prefix; | |
8933 | int code16; | |
252b5132 | 8934 | |
29b0f896 AM |
8935 | code16 = 0; |
8936 | if (flag_code == CODE_16BIT) | |
8937 | code16 = CODE16; | |
a217f122 | 8938 | |
29b0f896 AM |
8939 | prefix = 0; |
8940 | if (i.prefix[DATA_PREFIX] != 0) | |
8941 | { | |
8942 | prefix = 1; | |
8943 | i.prefixes -= 1; | |
8944 | code16 ^= CODE16; | |
8945 | } | |
6cb0a70e JB |
8946 | |
8947 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8948 | |
29b0f896 AM |
8949 | size = 4; |
8950 | if (code16) | |
8951 | size = 2; | |
252b5132 | 8952 | |
f2810fe0 JB |
8953 | if (i.prefixes != 0) |
8954 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8955 | |
48ef937e JB |
8956 | if (now_seg == absolute_section) |
8957 | { | |
8958 | abs_section_offset += prefix + 1 + 2 + size; | |
8959 | return; | |
8960 | } | |
8961 | ||
29b0f896 AM |
8962 | /* 1 opcode; 2 segment; offset */ |
8963 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8964 | |
29b0f896 AM |
8965 | if (i.prefix[DATA_PREFIX] != 0) |
8966 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 8967 | |
29b0f896 AM |
8968 | if (i.prefix[REX_PREFIX] != 0) |
8969 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 8970 | |
29b0f896 AM |
8971 | *p++ = i.tm.base_opcode; |
8972 | if (i.op[1].imms->X_op == O_constant) | |
8973 | { | |
8974 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 8975 | |
29b0f896 AM |
8976 | if (size == 2 |
8977 | && !fits_in_unsigned_word (n) | |
8978 | && !fits_in_signed_word (n)) | |
8979 | { | |
8980 | as_bad (_("16-bit jump out of range")); | |
8981 | return; | |
8982 | } | |
8983 | md_number_to_chars (p, n, size); | |
8984 | } | |
8985 | else | |
8986 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 8987 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
8988 | |
8989 | p += size; | |
8990 | if (i.op[0].imms->X_op == O_constant) | |
8991 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
8992 | else | |
8993 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
8994 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 8995 | } |
a217f122 | 8996 | |
b4a3a7b4 L |
8997 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8998 | void | |
8999 | x86_cleanup (void) | |
9000 | { | |
9001 | char *p; | |
9002 | asection *seg = now_seg; | |
9003 | subsegT subseg = now_subseg; | |
9004 | asection *sec; | |
9005 | unsigned int alignment, align_size_1; | |
9006 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
9007 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
9008 | unsigned int padding; | |
9009 | ||
1273b2f8 | 9010 | if (!IS_ELF || !x86_used_note) |
b4a3a7b4 L |
9011 | return; |
9012 | ||
b4a3a7b4 L |
9013 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
9014 | ||
9015 | /* The .note.gnu.property section layout: | |
9016 | ||
9017 | Field Length Contents | |
9018 | ---- ---- ---- | |
9019 | n_namsz 4 4 | |
9020 | n_descsz 4 The note descriptor size | |
9021 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
9022 | n_name 4 "GNU" | |
9023 | n_desc n_descsz The program property array | |
9024 | .... .... .... | |
9025 | */ | |
9026 | ||
9027 | /* Create the .note.gnu.property section. */ | |
9028 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 9029 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
9030 | (SEC_ALLOC |
9031 | | SEC_LOAD | |
9032 | | SEC_DATA | |
9033 | | SEC_HAS_CONTENTS | |
9034 | | SEC_READONLY)); | |
9035 | ||
9036 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
9037 | { | |
9038 | align_size_1 = 7; | |
9039 | alignment = 3; | |
9040 | } | |
9041 | else | |
9042 | { | |
9043 | align_size_1 = 3; | |
9044 | alignment = 2; | |
9045 | } | |
9046 | ||
fd361982 | 9047 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
9048 | elf_section_type (sec) = SHT_NOTE; |
9049 | ||
1273b2f8 L |
9050 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
9051 | + 4-byte data */ | |
9052 | isa_1_descsz_raw = 4 + 4 + 4; | |
9053 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
9054 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
b4a3a7b4 L |
9055 | |
9056 | feature_2_descsz_raw = isa_1_descsz; | |
9057 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
1273b2f8 | 9058 | + 4-byte data */ |
b4a3a7b4 L |
9059 | feature_2_descsz_raw += 4 + 4 + 4; |
9060 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
9061 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
9062 | & ~align_size_1); | |
9063 | ||
9064 | descsz = feature_2_descsz; | |
9065 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
9066 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
9067 | ||
9068 | /* Write n_namsz. */ | |
9069 | md_number_to_chars (p, (valueT) 4, 4); | |
9070 | ||
9071 | /* Write n_descsz. */ | |
9072 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
9073 | ||
9074 | /* Write n_type. */ | |
9075 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
9076 | ||
9077 | /* Write n_name. */ | |
9078 | memcpy (p + 4 * 3, "GNU", 4); | |
9079 | ||
1273b2f8 L |
9080 | /* Write 4-byte type. */ |
9081 | md_number_to_chars (p + 4 * 4, | |
9082 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 9083 | |
1273b2f8 L |
9084 | /* Write 4-byte data size. */ |
9085 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 9086 | |
1273b2f8 L |
9087 | /* Write 4-byte data. */ |
9088 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 9089 | |
1273b2f8 L |
9090 | /* Zero out paddings. */ |
9091 | padding = isa_1_descsz - isa_1_descsz_raw; | |
9092 | if (padding) | |
9093 | memset (p + 4 * 7, 0, padding); | |
b4a3a7b4 L |
9094 | |
9095 | /* Write 4-byte type. */ | |
9096 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
9097 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
9098 | ||
9099 | /* Write 4-byte data size. */ | |
9100 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
9101 | ||
9102 | /* Write 4-byte data. */ | |
9103 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
9104 | (valueT) x86_feature_2_used, 4); | |
9105 | ||
9106 | /* Zero out paddings. */ | |
9107 | padding = feature_2_descsz - feature_2_descsz_raw; | |
9108 | if (padding) | |
9109 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
9110 | ||
9111 | /* We probably can't restore the current segment, for there likely | |
9112 | isn't one yet... */ | |
9113 | if (seg && subseg) | |
9114 | subseg_set (seg, subseg); | |
9115 | } | |
9116 | #endif | |
9117 | ||
9c33702b JB |
9118 | static unsigned int |
9119 | encoding_length (const fragS *start_frag, offsetT start_off, | |
9120 | const char *frag_now_ptr) | |
9121 | { | |
9122 | unsigned int len = 0; | |
9123 | ||
9124 | if (start_frag != frag_now) | |
9125 | { | |
9126 | const fragS *fr = start_frag; | |
9127 | ||
9128 | do { | |
9129 | len += fr->fr_fix; | |
9130 | fr = fr->fr_next; | |
9131 | } while (fr && fr != frag_now); | |
9132 | } | |
9133 | ||
9134 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
9135 | } | |
9136 | ||
e379e5f3 | 9137 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
9138 | be macro-fused with conditional jumps. |
9139 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
9140 | or is one of the following format: | |
9141 | ||
9142 | cmp m, imm | |
9143 | add m, imm | |
9144 | sub m, imm | |
9145 | test m, imm | |
9146 | and m, imm | |
9147 | inc m | |
9148 | dec m | |
9149 | ||
9150 | it is unfusible. */ | |
e379e5f3 L |
9151 | |
9152 | static int | |
79d72f45 | 9153 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9154 | { |
9155 | /* No RIP address. */ | |
9156 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
9157 | return 0; | |
9158 | ||
389d00a5 JB |
9159 | /* No opcodes outside of base encoding space. */ |
9160 | if (i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
e379e5f3 L |
9161 | return 0; |
9162 | ||
79d72f45 HL |
9163 | /* add, sub without add/sub m, imm. */ |
9164 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
9165 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
9166 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 9167 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 9168 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
9169 | { |
9170 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9171 | return !(i.mem_operands && i.imm_operands); | |
9172 | } | |
e379e5f3 | 9173 | |
79d72f45 HL |
9174 | /* and without and m, imm. */ |
9175 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
9176 | || ((i.tm.base_opcode | 3) == 0x83 | |
9177 | && i.tm.extension_opcode == 0x4)) | |
9178 | { | |
9179 | *mf_cmp_p = mf_cmp_test_and; | |
9180 | return !(i.mem_operands && i.imm_operands); | |
9181 | } | |
9182 | ||
9183 | /* test without test m imm. */ | |
e379e5f3 L |
9184 | if ((i.tm.base_opcode | 1) == 0x85 |
9185 | || (i.tm.base_opcode | 1) == 0xa9 | |
9186 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
9187 | && i.tm.extension_opcode == 0)) |
9188 | { | |
9189 | *mf_cmp_p = mf_cmp_test_and; | |
9190 | return !(i.mem_operands && i.imm_operands); | |
9191 | } | |
9192 | ||
9193 | /* cmp without cmp m, imm. */ | |
9194 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
9195 | || ((i.tm.base_opcode | 3) == 0x83 |
9196 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
9197 | { |
9198 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9199 | return !(i.mem_operands && i.imm_operands); | |
9200 | } | |
e379e5f3 | 9201 | |
79d72f45 | 9202 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
9203 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
9204 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
9205 | || ((i.tm.base_opcode | 1) == 0xff | |
9206 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
9207 | { |
9208 | *mf_cmp_p = mf_cmp_incdec; | |
9209 | return !i.mem_operands; | |
9210 | } | |
e379e5f3 L |
9211 | |
9212 | return 0; | |
9213 | } | |
9214 | ||
9215 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
9216 | ||
9217 | static int | |
79d72f45 | 9218 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9219 | { |
9220 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9221 | if (!align_branch_power | |
9222 | || now_seg == absolute_section | |
9223 | || !cpu_arch_flags.bitfield.cpui386 | |
9224 | || !(align_branch & align_branch_fused_bit)) | |
9225 | return 0; | |
9226 | ||
79d72f45 | 9227 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
9228 | { |
9229 | if (last_insn.kind == last_insn_other | |
9230 | || last_insn.seg != now_seg) | |
9231 | return 1; | |
9232 | if (flag_debug) | |
9233 | as_warn_where (last_insn.file, last_insn.line, | |
9234 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9235 | last_insn.name, i.tm.name); | |
9236 | } | |
9237 | ||
9238 | return 0; | |
9239 | } | |
9240 | ||
9241 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
9242 | ||
9243 | static int | |
9244 | add_branch_prefix_frag_p (void) | |
9245 | { | |
9246 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
9247 | to PadLock instructions since they include prefixes in opcode. */ | |
9248 | if (!align_branch_power | |
9249 | || !align_branch_prefix_size | |
9250 | || now_seg == absolute_section | |
9251 | || i.tm.cpu_flags.bitfield.cpupadlock | |
9252 | || !cpu_arch_flags.bitfield.cpui386) | |
9253 | return 0; | |
9254 | ||
9255 | /* Don't add prefix if it is a prefix or there is no operand in case | |
9256 | that segment prefix is special. */ | |
9257 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
9258 | return 0; | |
9259 | ||
9260 | if (last_insn.kind == last_insn_other | |
9261 | || last_insn.seg != now_seg) | |
9262 | return 1; | |
9263 | ||
9264 | if (flag_debug) | |
9265 | as_warn_where (last_insn.file, last_insn.line, | |
9266 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9267 | last_insn.name, i.tm.name); | |
9268 | ||
9269 | return 0; | |
9270 | } | |
9271 | ||
9272 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
9273 | ||
9274 | static int | |
79d72f45 HL |
9275 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
9276 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
9277 | { |
9278 | int add_padding; | |
9279 | ||
9280 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9281 | if (!align_branch_power | |
9282 | || now_seg == absolute_section | |
389d00a5 JB |
9283 | || !cpu_arch_flags.bitfield.cpui386 |
9284 | || i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
e379e5f3 L |
9285 | return 0; |
9286 | ||
9287 | add_padding = 0; | |
9288 | ||
9289 | /* Check for jcc and direct jmp. */ | |
9290 | if (i.tm.opcode_modifier.jump == JUMP) | |
9291 | { | |
9292 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
9293 | { | |
9294 | *branch_p = align_branch_jmp; | |
9295 | add_padding = align_branch & align_branch_jmp_bit; | |
9296 | } | |
9297 | else | |
9298 | { | |
79d72f45 HL |
9299 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
9300 | igore the lowest bit. */ | |
9301 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
9302 | *branch_p = align_branch_jcc; |
9303 | if ((align_branch & align_branch_jcc_bit)) | |
9304 | add_padding = 1; | |
9305 | } | |
9306 | } | |
e379e5f3 L |
9307 | else if ((i.tm.base_opcode | 1) == 0xc3) |
9308 | { | |
9309 | /* Near ret. */ | |
9310 | *branch_p = align_branch_ret; | |
9311 | if ((align_branch & align_branch_ret_bit)) | |
9312 | add_padding = 1; | |
9313 | } | |
9314 | else | |
9315 | { | |
9316 | /* Check for indirect jmp, direct and indirect calls. */ | |
9317 | if (i.tm.base_opcode == 0xe8) | |
9318 | { | |
9319 | /* Direct call. */ | |
9320 | *branch_p = align_branch_call; | |
9321 | if ((align_branch & align_branch_call_bit)) | |
9322 | add_padding = 1; | |
9323 | } | |
9324 | else if (i.tm.base_opcode == 0xff | |
9325 | && (i.tm.extension_opcode == 2 | |
9326 | || i.tm.extension_opcode == 4)) | |
9327 | { | |
9328 | /* Indirect call and jmp. */ | |
9329 | *branch_p = align_branch_indirect; | |
9330 | if ((align_branch & align_branch_indirect_bit)) | |
9331 | add_padding = 1; | |
9332 | } | |
9333 | ||
9334 | if (add_padding | |
9335 | && i.disp_operands | |
9336 | && tls_get_addr | |
9337 | && (i.op[0].disps->X_op == O_symbol | |
9338 | || (i.op[0].disps->X_op == O_subtract | |
9339 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
9340 | { | |
9341 | symbolS *s = i.op[0].disps->X_add_symbol; | |
9342 | /* No padding to call to global or undefined tls_get_addr. */ | |
9343 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
9344 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
9345 | return 0; | |
9346 | } | |
9347 | } | |
9348 | ||
9349 | if (add_padding | |
9350 | && last_insn.kind != last_insn_other | |
9351 | && last_insn.seg == now_seg) | |
9352 | { | |
9353 | if (flag_debug) | |
9354 | as_warn_where (last_insn.file, last_insn.line, | |
9355 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9356 | last_insn.name, i.tm.name); | |
9357 | return 0; | |
9358 | } | |
9359 | ||
9360 | return add_padding; | |
9361 | } | |
9362 | ||
29b0f896 | 9363 | static void |
e3bb37b5 | 9364 | output_insn (void) |
29b0f896 | 9365 | { |
2bbd9c25 JJ |
9366 | fragS *insn_start_frag; |
9367 | offsetT insn_start_off; | |
e379e5f3 L |
9368 | fragS *fragP = NULL; |
9369 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
9370 | /* The initializer is arbitrary just to avoid uninitialized error. |
9371 | it's actually either assigned in add_branch_padding_frag_p | |
9372 | or never be used. */ | |
9373 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 9374 | |
b4a3a7b4 | 9375 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 9376 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 9377 | { |
32930e4e L |
9378 | if ((i.xstate & xstate_tmm) == xstate_tmm |
9379 | || i.tm.cpu_flags.bitfield.cpuamx_tile) | |
9380 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; | |
9381 | ||
b4a3a7b4 L |
9382 | if (i.tm.cpu_flags.bitfield.cpu8087 |
9383 | || i.tm.cpu_flags.bitfield.cpu287 | |
9384 | || i.tm.cpu_flags.bitfield.cpu387 | |
9385 | || i.tm.cpu_flags.bitfield.cpu687 | |
9386 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
9387 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
014d61ea | 9388 | |
921eafea | 9389 | if ((i.xstate & xstate_mmx) |
389d00a5 JB |
9390 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
9391 | && !is_any_vex_encoding (&i.tm) | |
9392 | && (i.tm.base_opcode == 0x77 /* emms */ | |
9393 | || i.tm.base_opcode == 0x0e /* femms */))) | |
b4a3a7b4 | 9394 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 9395 | |
32930e4e L |
9396 | if (i.index_reg) |
9397 | { | |
9398 | if (i.index_reg->reg_type.bitfield.zmmword) | |
9399 | i.xstate |= xstate_zmm; | |
9400 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
9401 | i.xstate |= xstate_ymm; | |
9402 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
9403 | i.xstate |= xstate_xmm; | |
9404 | } | |
014d61ea JB |
9405 | |
9406 | /* vzeroall / vzeroupper */ | |
9407 | if (i.tm.base_opcode == 0x77 && i.tm.cpu_flags.bitfield.cpuavx) | |
9408 | i.xstate |= xstate_ymm; | |
9409 | ||
c4694f17 | 9410 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
9411 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
9412 | || (i.tm.base_opcode == 0xae | |
9413 | && (i.tm.cpu_flags.bitfield.cpusse | |
9414 | || i.tm.cpu_flags.bitfield.cpuavx)) | |
c4694f17 TG |
9415 | || i.tm.cpu_flags.bitfield.cpuwidekl |
9416 | || i.tm.cpu_flags.bitfield.cpukl) | |
b4a3a7b4 | 9417 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 9418 | |
921eafea | 9419 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 9420 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 9421 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 9422 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 9423 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 9424 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
b4a3a7b4 L |
9425 | if (i.tm.cpu_flags.bitfield.cpufxsr) |
9426 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
9427 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
9428 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
9429 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
9430 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
9431 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
9432 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
b0ab0693 L |
9433 | |
9434 | if (x86_feature_2_used | |
9435 | || i.tm.cpu_flags.bitfield.cpucmov | |
9436 | || i.tm.cpu_flags.bitfield.cpusyscall | |
389d00a5 JB |
9437 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
9438 | && i.tm.base_opcode == 0xc7 | |
70e95837 | 9439 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE |
b0ab0693 L |
9440 | && i.tm.extension_opcode == 1) /* cmpxchg8b */) |
9441 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; | |
9442 | if (i.tm.cpu_flags.bitfield.cpusse3 | |
9443 | || i.tm.cpu_flags.bitfield.cpussse3 | |
9444 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
9445 | || i.tm.cpu_flags.bitfield.cpusse4_2 | |
9446 | || i.tm.cpu_flags.bitfield.cpucx16 | |
9447 | || i.tm.cpu_flags.bitfield.cpupopcnt | |
9448 | /* LAHF-SAHF insns in 64-bit mode. */ | |
9449 | || (flag_code == CODE_64BIT | |
35648716 JB |
9450 | && (i.tm.base_opcode | 1) == 0x9f |
9451 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE)) | |
b0ab0693 L |
9452 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
9453 | if (i.tm.cpu_flags.bitfield.cpuavx | |
9454 | || i.tm.cpu_flags.bitfield.cpuavx2 | |
a9860005 JB |
9455 | /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ, |
9456 | XOP, FMA4, LPW, TBM, and AMX. */ | |
b0ab0693 L |
9457 | || (i.tm.opcode_modifier.vex |
9458 | && !i.tm.cpu_flags.bitfield.cpuavx512f | |
9459 | && !i.tm.cpu_flags.bitfield.cpuavx512bw | |
9460 | && !i.tm.cpu_flags.bitfield.cpuavx512dq | |
a9860005 JB |
9461 | && !i.tm.cpu_flags.bitfield.cpuxop |
9462 | && !i.tm.cpu_flags.bitfield.cpufma4 | |
b0ab0693 L |
9463 | && !i.tm.cpu_flags.bitfield.cpulwp |
9464 | && !i.tm.cpu_flags.bitfield.cputbm | |
9465 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) | |
9466 | || i.tm.cpu_flags.bitfield.cpuf16c | |
9467 | || i.tm.cpu_flags.bitfield.cpufma | |
9468 | || i.tm.cpu_flags.bitfield.cpulzcnt | |
9469 | || i.tm.cpu_flags.bitfield.cpumovbe | |
9470 | || i.tm.cpu_flags.bitfield.cpuxsaves | |
9471 | || (x86_feature_2_used | |
9472 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
9473 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
9474 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
9475 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
9476 | if (i.tm.cpu_flags.bitfield.cpuavx512f | |
9477 | || i.tm.cpu_flags.bitfield.cpuavx512bw | |
9478 | || i.tm.cpu_flags.bitfield.cpuavx512dq | |
9479 | || i.tm.cpu_flags.bitfield.cpuavx512vl | |
a9860005 JB |
9480 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF, |
9481 | AVX512-4FMAPS, and AVX512-4VNNIW. */ | |
b0ab0693 L |
9482 | || (i.tm.opcode_modifier.evex |
9483 | && !i.tm.cpu_flags.bitfield.cpuavx512er | |
9484 | && !i.tm.cpu_flags.bitfield.cpuavx512pf | |
a9860005 | 9485 | && !i.tm.cpu_flags.bitfield.cpuavx512_4fmaps |
b0ab0693 L |
9486 | && !i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)) |
9487 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; | |
b4a3a7b4 L |
9488 | } |
9489 | #endif | |
9490 | ||
29b0f896 AM |
9491 | /* Tie dwarf2 debug info to the address at the start of the insn. |
9492 | We can't do this after the insn has been output as the current | |
9493 | frag may have been closed off. eg. by frag_var. */ | |
9494 | dwarf2_emit_insn (0); | |
9495 | ||
2bbd9c25 JJ |
9496 | insn_start_frag = frag_now; |
9497 | insn_start_off = frag_now_fix (); | |
9498 | ||
79d72f45 | 9499 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
9500 | { |
9501 | char *p; | |
9502 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
9503 | unsigned int max_branch_padding_size = 14; | |
9504 | ||
9505 | /* Align section to boundary. */ | |
9506 | record_alignment (now_seg, align_branch_power); | |
9507 | ||
9508 | /* Make room for padding. */ | |
9509 | frag_grow (max_branch_padding_size); | |
9510 | ||
9511 | /* Start of the padding. */ | |
9512 | p = frag_more (0); | |
9513 | ||
9514 | fragP = frag_now; | |
9515 | ||
9516 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
9517 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
9518 | NULL, 0, p); | |
9519 | ||
79d72f45 | 9520 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
9521 | fragP->tc_frag_data.branch_type = branch; |
9522 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
9523 | } | |
9524 | ||
d59a54c2 JB |
9525 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT) |
9526 | && !pre_386_16bit_warned) | |
9527 | { | |
9528 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
9529 | pre_386_16bit_warned = true; | |
9530 | } | |
9531 | ||
29b0f896 | 9532 | /* Output jumps. */ |
0cfa3eb3 | 9533 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 9534 | output_branch (); |
0cfa3eb3 JB |
9535 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9536 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 9537 | output_jump (); |
0cfa3eb3 | 9538 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
9539 | output_interseg_jump (); |
9540 | else | |
9541 | { | |
9542 | /* Output normal instructions here. */ | |
9543 | char *p; | |
9544 | unsigned char *q; | |
47465058 | 9545 | unsigned int j; |
79d72f45 | 9546 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 9547 | |
e4e00185 | 9548 | if (avoid_fence |
389d00a5 JB |
9549 | && (i.tm.base_opcode == 0xaee8 |
9550 | || i.tm.base_opcode == 0xaef0 | |
9551 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
9552 | { |
9553 | /* Encode lfence, mfence, and sfence as | |
9554 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
47f4115a JB |
9555 | if (flag_code == CODE_16BIT) |
9556 | as_bad (_("Cannot convert `%s' in 16-bit mode"), i.tm.name); | |
9557 | else if (omit_lock_prefix) | |
9558 | as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"), | |
9559 | i.tm.name); | |
9560 | else if (now_seg != absolute_section) | |
48ef937e JB |
9561 | { |
9562 | offsetT val = 0x240483f0ULL; | |
9563 | ||
9564 | p = frag_more (5); | |
9565 | md_number_to_chars (p, val, 5); | |
9566 | } | |
9567 | else | |
9568 | abs_section_offset += 5; | |
9569 | return; | |
9570 | } | |
e4e00185 | 9571 | |
d022bddd IT |
9572 | /* Some processors fail on LOCK prefix. This options makes |
9573 | assembler ignore LOCK prefix and serves as a workaround. */ | |
9574 | if (omit_lock_prefix) | |
9575 | { | |
35648716 JB |
9576 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
9577 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
9578 | return; |
9579 | i.prefix[LOCK_PREFIX] = 0; | |
9580 | } | |
9581 | ||
e379e5f3 L |
9582 | if (branch) |
9583 | /* Skip if this is a branch. */ | |
9584 | ; | |
79d72f45 | 9585 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
9586 | { |
9587 | /* Make room for padding. */ | |
9588 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
9589 | p = frag_more (0); | |
9590 | ||
9591 | fragP = frag_now; | |
9592 | ||
9593 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
9594 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
9595 | NULL, 0, p); | |
9596 | ||
79d72f45 | 9597 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
9598 | fragP->tc_frag_data.branch_type = align_branch_fused; |
9599 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
9600 | } | |
9601 | else if (add_branch_prefix_frag_p ()) | |
9602 | { | |
9603 | unsigned int max_prefix_size = align_branch_prefix_size; | |
9604 | ||
9605 | /* Make room for padding. */ | |
9606 | frag_grow (max_prefix_size); | |
9607 | p = frag_more (0); | |
9608 | ||
9609 | fragP = frag_now; | |
9610 | ||
9611 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
9612 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
9613 | NULL, 0, p); | |
9614 | ||
9615 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
9616 | } | |
9617 | ||
43234a1e L |
9618 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
9619 | don't need the explicit prefix. */ | |
cf665fee | 9620 | if (!is_any_vex_encoding (&i.tm)) |
bc4bd9ab | 9621 | { |
7b47a312 | 9622 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 9623 | { |
7b47a312 L |
9624 | case PREFIX_0X66: |
9625 | add_prefix (0x66); | |
9626 | break; | |
9627 | case PREFIX_0XF2: | |
9628 | add_prefix (0xf2); | |
9629 | break; | |
9630 | case PREFIX_0XF3: | |
8b65b895 L |
9631 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
9632 | || (i.prefix[REP_PREFIX] != 0xf3)) | |
9633 | add_prefix (0xf3); | |
c0f3af97 | 9634 | break; |
7b47a312 | 9635 | case PREFIX_NONE: |
9a182d04 | 9636 | switch (i.opcode_length) |
c0f3af97 | 9637 | { |
7b47a312 | 9638 | case 2: |
7b47a312 | 9639 | break; |
9a182d04 | 9640 | case 1: |
7b47a312 | 9641 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
9642 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
9643 | break; | |
7b47a312 L |
9644 | as_bad_where (insn_start_frag->fr_file, |
9645 | insn_start_frag->fr_line, | |
9646 | _("pseudo prefix without instruction")); | |
9647 | return; | |
9648 | default: | |
9649 | abort (); | |
4dffcebc | 9650 | } |
c0f3af97 | 9651 | break; |
c0f3af97 L |
9652 | default: |
9653 | abort (); | |
bc4bd9ab | 9654 | } |
c0f3af97 | 9655 | |
6d19a37a | 9656 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
9657 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
9658 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
9659 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
9660 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
9661 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
9662 | if (x86_elf_abi == X86_64_X32_ABI |
9663 | && i.operands == 2 | |
14470f07 L |
9664 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
9665 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
9666 | && i.prefix[REX_PREFIX] == 0) |
9667 | add_prefix (REX_OPCODE); | |
6d19a37a | 9668 | #endif |
cf61b747 | 9669 | |
c0f3af97 L |
9670 | /* The prefix bytes. */ |
9671 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
9672 | if (*q) | |
48ef937e | 9673 | frag_opcode_byte (*q); |
0f10071e | 9674 | } |
ae5c1c7b | 9675 | else |
c0f3af97 L |
9676 | { |
9677 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
9678 | if (*q) | |
9679 | switch (j) | |
9680 | { | |
c0f3af97 L |
9681 | case SEG_PREFIX: |
9682 | case ADDR_PREFIX: | |
48ef937e | 9683 | frag_opcode_byte (*q); |
c0f3af97 L |
9684 | break; |
9685 | default: | |
9686 | /* There should be no other prefixes for instructions | |
9687 | with VEX prefix. */ | |
9688 | abort (); | |
9689 | } | |
9690 | ||
43234a1e L |
9691 | /* For EVEX instructions i.vrex should become 0 after |
9692 | build_evex_prefix. For VEX instructions upper 16 registers | |
9693 | aren't available, so VREX should be 0. */ | |
9694 | if (i.vrex) | |
9695 | abort (); | |
c0f3af97 | 9696 | /* Now the VEX prefix. */ |
48ef937e JB |
9697 | if (now_seg != absolute_section) |
9698 | { | |
9699 | p = frag_more (i.vex.length); | |
9700 | for (j = 0; j < i.vex.length; j++) | |
9701 | p[j] = i.vex.bytes[j]; | |
9702 | } | |
9703 | else | |
9704 | abs_section_offset += i.vex.length; | |
c0f3af97 | 9705 | } |
252b5132 | 9706 | |
29b0f896 | 9707 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
9708 | j = i.opcode_length; |
9709 | if (!i.vex.length) | |
9710 | switch (i.tm.opcode_modifier.opcodespace) | |
9711 | { | |
9712 | case SPACE_BASE: | |
9713 | break; | |
9714 | case SPACE_0F: | |
9715 | ++j; | |
9716 | break; | |
9717 | case SPACE_0F38: | |
9718 | case SPACE_0F3A: | |
9719 | j += 2; | |
9720 | break; | |
9721 | default: | |
9722 | abort (); | |
9723 | } | |
9724 | ||
48ef937e | 9725 | if (now_seg == absolute_section) |
389d00a5 JB |
9726 | abs_section_offset += j; |
9727 | else if (j == 1) | |
29b0f896 AM |
9728 | { |
9729 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
9730 | } | |
9731 | else | |
9732 | { | |
389d00a5 JB |
9733 | p = frag_more (j); |
9734 | if (!i.vex.length | |
9735 | && i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
9736 | { | |
9737 | *p++ = 0x0f; | |
9738 | if (i.tm.opcode_modifier.opcodespace != SPACE_0F) | |
9739 | *p++ = i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
9740 | ? 0x38 : 0x3a; | |
9741 | } | |
9742 | ||
9a182d04 | 9743 | switch (i.opcode_length) |
331d2d0d | 9744 | { |
4dffcebc | 9745 | case 2: |
389d00a5 JB |
9746 | /* Put out high byte first: can't use md_number_to_chars! */ |
9747 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
9748 | /* Fall through. */ | |
9749 | case 1: | |
9750 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
9751 | break; |
9752 | default: | |
9753 | abort (); | |
9754 | break; | |
331d2d0d | 9755 | } |
0f10071e | 9756 | |
29b0f896 | 9757 | } |
3e73aa7c | 9758 | |
29b0f896 | 9759 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 9760 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 9761 | { |
48ef937e JB |
9762 | frag_opcode_byte ((i.rm.regmem << 0) |
9763 | | (i.rm.reg << 3) | |
9764 | | (i.rm.mode << 6)); | |
29b0f896 AM |
9765 | /* If i.rm.regmem == ESP (4) |
9766 | && i.rm.mode != (Register mode) | |
9767 | && not 16 bit | |
9768 | ==> need second modrm byte. */ | |
9769 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
9770 | && i.rm.mode != 3 | |
dc821c5f | 9771 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
9772 | frag_opcode_byte ((i.sib.base << 0) |
9773 | | (i.sib.index << 3) | |
9774 | | (i.sib.scale << 6)); | |
29b0f896 | 9775 | } |
3e73aa7c | 9776 | |
29b0f896 | 9777 | if (i.disp_operands) |
2bbd9c25 | 9778 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 9779 | |
29b0f896 | 9780 | if (i.imm_operands) |
2bbd9c25 | 9781 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
9782 | |
9783 | /* | |
9784 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
9785 | * absolute section, and abs_section_offset not getting updated as data | |
9786 | * gets added to the frag breaks the logic below. | |
9787 | */ | |
9788 | if (now_seg != absolute_section) | |
9789 | { | |
9790 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
9791 | if (j > 15) | |
9792 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
9793 | j); | |
e379e5f3 L |
9794 | else if (fragP) |
9795 | { | |
9796 | /* NB: Don't add prefix with GOTPC relocation since | |
9797 | output_disp() above depends on the fixed encoding | |
9798 | length. Can't add prefix with TLS relocation since | |
9799 | it breaks TLS linker optimization. */ | |
9800 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
9801 | /* Prefix count on the current instruction. */ | |
9802 | unsigned int count = i.vex.length; | |
9803 | unsigned int k; | |
9804 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
9805 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
9806 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
9807 | count++; | |
9808 | ||
9809 | /* Count prefixes for extended opcode maps. */ | |
9810 | if (!i.vex.length) | |
389d00a5 | 9811 | switch (i.tm.opcode_modifier.opcodespace) |
e379e5f3 | 9812 | { |
389d00a5 | 9813 | case SPACE_BASE: |
e379e5f3 | 9814 | break; |
389d00a5 JB |
9815 | case SPACE_0F: |
9816 | count++; | |
e379e5f3 | 9817 | break; |
389d00a5 JB |
9818 | case SPACE_0F38: |
9819 | case SPACE_0F3A: | |
9820 | count += 2; | |
e379e5f3 L |
9821 | break; |
9822 | default: | |
9823 | abort (); | |
9824 | } | |
9825 | ||
9826 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9827 | == BRANCH_PREFIX) | |
9828 | { | |
9829 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9830 | frag. */ | |
9831 | if (fragP->tc_frag_data.max_bytes > max) | |
9832 | fragP->tc_frag_data.max_bytes = max; | |
9833 | if (fragP->tc_frag_data.max_bytes > count) | |
9834 | fragP->tc_frag_data.max_bytes -= count; | |
9835 | else | |
9836 | fragP->tc_frag_data.max_bytes = 0; | |
9837 | } | |
9838 | else | |
9839 | { | |
9840 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9841 | frag. */ | |
9842 | unsigned int max_prefix_size; | |
9843 | if (align_branch_prefix_size > max) | |
9844 | max_prefix_size = max; | |
9845 | else | |
9846 | max_prefix_size = align_branch_prefix_size; | |
9847 | if (max_prefix_size > count) | |
9848 | fragP->tc_frag_data.max_prefix_length | |
9849 | = max_prefix_size - count; | |
9850 | } | |
9851 | ||
9852 | /* Use existing segment prefix if possible. Use CS | |
9853 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9854 | segment prefix with ESP/EBP base register and use DS | |
9855 | segment prefix without ESP/EBP base register. */ | |
9856 | if (i.prefix[SEG_PREFIX]) | |
9857 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9858 | else if (flag_code == CODE_64BIT) | |
9859 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9860 | else if (i.base_reg | |
9861 | && (i.base_reg->reg_num == 4 | |
9862 | || i.base_reg->reg_num == 5)) | |
9863 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9864 | else | |
9865 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9866 | } | |
9c33702b | 9867 | } |
29b0f896 | 9868 | } |
252b5132 | 9869 | |
e379e5f3 L |
9870 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9871 | if (align_branch_power | |
9872 | && now_seg != absolute_section | |
9873 | && cpu_arch_flags.bitfield.cpui386) | |
9874 | { | |
9875 | /* Terminate each frag so that we can add prefix and check for | |
9876 | fused jcc. */ | |
9877 | frag_wane (frag_now); | |
9878 | frag_new (0); | |
9879 | } | |
9880 | ||
29b0f896 AM |
9881 | #ifdef DEBUG386 |
9882 | if (flag_debug) | |
9883 | { | |
7b81dfbb | 9884 | pi ("" /*line*/, &i); |
29b0f896 AM |
9885 | } |
9886 | #endif /* DEBUG386 */ | |
9887 | } | |
252b5132 | 9888 | |
e205caa7 L |
9889 | /* Return the size of the displacement operand N. */ |
9890 | ||
9891 | static int | |
9892 | disp_size (unsigned int n) | |
9893 | { | |
9894 | int size = 4; | |
43234a1e | 9895 | |
b5014f7a | 9896 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9897 | size = 8; |
9898 | else if (i.types[n].bitfield.disp8) | |
9899 | size = 1; | |
9900 | else if (i.types[n].bitfield.disp16) | |
9901 | size = 2; | |
e205caa7 L |
9902 | return size; |
9903 | } | |
9904 | ||
9905 | /* Return the size of the immediate operand N. */ | |
9906 | ||
9907 | static int | |
9908 | imm_size (unsigned int n) | |
9909 | { | |
9910 | int size = 4; | |
40fb9820 L |
9911 | if (i.types[n].bitfield.imm64) |
9912 | size = 8; | |
9913 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9914 | size = 1; | |
9915 | else if (i.types[n].bitfield.imm16) | |
9916 | size = 2; | |
e205caa7 L |
9917 | return size; |
9918 | } | |
9919 | ||
29b0f896 | 9920 | static void |
64e74474 | 9921 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9922 | { |
9923 | char *p; | |
9924 | unsigned int n; | |
252b5132 | 9925 | |
29b0f896 AM |
9926 | for (n = 0; n < i.operands; n++) |
9927 | { | |
b5014f7a | 9928 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 9929 | { |
48ef937e JB |
9930 | int size = disp_size (n); |
9931 | ||
9932 | if (now_seg == absolute_section) | |
9933 | abs_section_offset += size; | |
9934 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 9935 | { |
43234a1e | 9936 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9937 | |
629cfaf1 JB |
9938 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9939 | size); | |
29b0f896 AM |
9940 | p = frag_more (size); |
9941 | md_number_to_chars (p, val, size); | |
9942 | } | |
9943 | else | |
9944 | { | |
f86103b7 | 9945 | enum bfd_reloc_code_real reloc_type; |
a775efc8 JB |
9946 | bool pcrel = (i.flags[n] & Operand_PCrel) != 0; |
9947 | bool sign = (flag_code == CODE_64BIT && size == 4 | |
9948 | && (!want_disp32 (&i.tm) | |
9949 | || (i.tm.opcode_modifier.jump && !i.jumpabsolute | |
9950 | && !i.types[n].bitfield.baseindex))) | |
9951 | || pcrel; | |
02a86693 | 9952 | fixS *fixP; |
29b0f896 | 9953 | |
e205caa7 | 9954 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9955 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9956 | |
29b0f896 AM |
9957 | /* The PC relative address is computed relative |
9958 | to the instruction boundary, so in case immediate | |
9959 | fields follows, we need to adjust the value. */ | |
9960 | if (pcrel && i.imm_operands) | |
9961 | { | |
29b0f896 | 9962 | unsigned int n1; |
e205caa7 | 9963 | int sz = 0; |
252b5132 | 9964 | |
29b0f896 | 9965 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9966 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9967 | { |
e205caa7 L |
9968 | /* Only one immediate is allowed for PC |
9969 | relative address. */ | |
9c2799c2 | 9970 | gas_assert (sz == 0); |
e205caa7 L |
9971 | sz = imm_size (n1); |
9972 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9973 | } |
29b0f896 | 9974 | /* We should find the immediate. */ |
9c2799c2 | 9975 | gas_assert (sz != 0); |
29b0f896 | 9976 | } |
520dc8e8 | 9977 | |
29b0f896 | 9978 | p = frag_more (size); |
d258b828 | 9979 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 9980 | if (GOT_symbol |
2bbd9c25 | 9981 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 9982 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
9983 | || reloc_type == BFD_RELOC_X86_64_32S |
9984 | || (reloc_type == BFD_RELOC_64 | |
9985 | && object_64bit)) | |
d6ab8113 JB |
9986 | && (i.op[n].disps->X_op == O_symbol |
9987 | || (i.op[n].disps->X_op == O_add | |
9988 | && ((symbol_get_value_expression | |
9989 | (i.op[n].disps->X_op_symbol)->X_op) | |
9990 | == O_subtract)))) | |
9991 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 9992 | { |
4fa24527 | 9993 | if (!object_64bit) |
7b81dfbb AJ |
9994 | { |
9995 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 9996 | i.has_gotpc_tls_reloc = true; |
98da05bf | 9997 | i.op[n].disps->X_add_number += |
d583596c | 9998 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
9999 | } |
10000 | else if (reloc_type == BFD_RELOC_64) | |
10001 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 10002 | else |
7b81dfbb AJ |
10003 | /* Don't do the adjustment for x86-64, as there |
10004 | the pcrel addressing is relative to the _next_ | |
10005 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 10006 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 10007 | } |
e379e5f3 L |
10008 | else if (align_branch_power) |
10009 | { | |
10010 | switch (reloc_type) | |
10011 | { | |
10012 | case BFD_RELOC_386_TLS_GD: | |
10013 | case BFD_RELOC_386_TLS_LDM: | |
10014 | case BFD_RELOC_386_TLS_IE: | |
10015 | case BFD_RELOC_386_TLS_IE_32: | |
10016 | case BFD_RELOC_386_TLS_GOTIE: | |
10017 | case BFD_RELOC_386_TLS_GOTDESC: | |
10018 | case BFD_RELOC_386_TLS_DESC_CALL: | |
10019 | case BFD_RELOC_X86_64_TLSGD: | |
10020 | case BFD_RELOC_X86_64_TLSLD: | |
10021 | case BFD_RELOC_X86_64_GOTTPOFF: | |
10022 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
10023 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
5b7c81bd | 10024 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
10025 | default: |
10026 | break; | |
10027 | } | |
10028 | } | |
02a86693 L |
10029 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
10030 | size, i.op[n].disps, pcrel, | |
10031 | reloc_type); | |
eb19308f JB |
10032 | |
10033 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
10034 | && !i.prefix[ADDR_PREFIX]) | |
10035 | fixP->fx_signed = 1; | |
10036 | ||
02a86693 L |
10037 | /* Check for "call/jmp *mem", "mov mem, %reg", |
10038 | "test %reg, mem" and "binop mem, %reg" where binop | |
10039 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
10040 | instructions without data prefix. Always generate |
10041 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
10042 | if (i.prefix[DATA_PREFIX] == 0 | |
10043 | && (generate_relax_relocations | |
10044 | || (!object_64bit | |
10045 | && i.rm.mode == 0 | |
10046 | && i.rm.regmem == 5)) | |
0cb4071e L |
10047 | && (i.rm.mode == 2 |
10048 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
389d00a5 | 10049 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
02a86693 L |
10050 | && ((i.operands == 1 |
10051 | && i.tm.base_opcode == 0xff | |
10052 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
10053 | || (i.operands == 2 | |
10054 | && (i.tm.base_opcode == 0x8b | |
10055 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 10056 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
10057 | { |
10058 | if (object_64bit) | |
10059 | { | |
10060 | fixP->fx_tcbit = i.rex != 0; | |
10061 | if (i.base_reg | |
e968fc9b | 10062 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
10063 | fixP->fx_tcbit2 = 1; |
10064 | } | |
10065 | else | |
10066 | fixP->fx_tcbit2 = 1; | |
10067 | } | |
29b0f896 AM |
10068 | } |
10069 | } | |
10070 | } | |
10071 | } | |
252b5132 | 10072 | |
29b0f896 | 10073 | static void |
64e74474 | 10074 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10075 | { |
10076 | char *p; | |
10077 | unsigned int n; | |
252b5132 | 10078 | |
29b0f896 AM |
10079 | for (n = 0; n < i.operands; n++) |
10080 | { | |
40fb9820 | 10081 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 10082 | { |
48ef937e JB |
10083 | int size = imm_size (n); |
10084 | ||
10085 | if (now_seg == absolute_section) | |
10086 | abs_section_offset += size; | |
10087 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 10088 | { |
29b0f896 | 10089 | offsetT val; |
b4cac588 | 10090 | |
29b0f896 AM |
10091 | val = offset_in_range (i.op[n].imms->X_add_number, |
10092 | size); | |
10093 | p = frag_more (size); | |
10094 | md_number_to_chars (p, val, size); | |
10095 | } | |
10096 | else | |
10097 | { | |
10098 | /* Not absolute_section. | |
10099 | Need a 32-bit fixup (don't support 8bit | |
10100 | non-absolute imms). Try to support other | |
10101 | sizes ... */ | |
f86103b7 | 10102 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 10103 | int sign; |
29b0f896 | 10104 | |
40fb9820 | 10105 | if (i.types[n].bitfield.imm32s |
a7d61044 | 10106 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 10107 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 10108 | sign = 1; |
e205caa7 L |
10109 | else |
10110 | sign = 0; | |
520dc8e8 | 10111 | |
29b0f896 | 10112 | p = frag_more (size); |
d258b828 | 10113 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 10114 | |
2bbd9c25 JJ |
10115 | /* This is tough to explain. We end up with this one if we |
10116 | * have operands that look like | |
10117 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
10118 | * obtain the absolute address of the GOT, and it is strongly | |
10119 | * preferable from a performance point of view to avoid using | |
10120 | * a runtime relocation for this. The actual sequence of | |
10121 | * instructions often look something like: | |
10122 | * | |
10123 | * call .L66 | |
10124 | * .L66: | |
10125 | * popl %ebx | |
10126 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
10127 | * | |
10128 | * The call and pop essentially return the absolute address | |
10129 | * of the label .L66 and store it in %ebx. The linker itself | |
10130 | * will ultimately change the first operand of the addl so | |
10131 | * that %ebx points to the GOT, but to keep things simple, the | |
10132 | * .o file must have this operand set so that it generates not | |
10133 | * the absolute address of .L66, but the absolute address of | |
10134 | * itself. This allows the linker itself simply treat a GOTPC | |
10135 | * relocation as asking for a pcrel offset to the GOT to be | |
10136 | * added in, and the addend of the relocation is stored in the | |
10137 | * operand field for the instruction itself. | |
10138 | * | |
10139 | * Our job here is to fix the operand so that it would add | |
10140 | * the correct offset so that %ebx would point to itself. The | |
10141 | * thing that is tricky is that .-.L66 will point to the | |
10142 | * beginning of the instruction, so we need to further modify | |
10143 | * the operand so that it will point to itself. There are | |
10144 | * other cases where you have something like: | |
10145 | * | |
10146 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
10147 | * | |
10148 | * and here no correction would be required. Internally in | |
10149 | * the assembler we treat operands of this form as not being | |
10150 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
10151 | * whether it would simplify matters to do it this way. Who | |
10152 | * knows. In earlier versions of the PIC patches, the | |
10153 | * pcrel_adjust field was used to store the correction, but | |
10154 | * since the expression is not pcrel, I felt it would be | |
10155 | * confusing to do it this way. */ | |
10156 | ||
d6ab8113 | 10157 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10158 | || reloc_type == BFD_RELOC_X86_64_32S |
10159 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
10160 | && GOT_symbol |
10161 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
10162 | && (i.op[n].imms->X_op == O_symbol | |
10163 | || (i.op[n].imms->X_op == O_add | |
10164 | && ((symbol_get_value_expression | |
10165 | (i.op[n].imms->X_op_symbol)->X_op) | |
10166 | == O_subtract)))) | |
10167 | { | |
4fa24527 | 10168 | if (!object_64bit) |
d6ab8113 | 10169 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 10170 | else if (size == 4) |
d6ab8113 | 10171 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
10172 | else if (size == 8) |
10173 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 10174 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
10175 | i.op[n].imms->X_add_number += |
10176 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 10177 | } |
29b0f896 AM |
10178 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
10179 | i.op[n].imms, 0, reloc_type); | |
10180 | } | |
10181 | } | |
10182 | } | |
252b5132 RH |
10183 | } |
10184 | \f | |
d182319b JB |
10185 | /* x86_cons_fix_new is called via the expression parsing code when a |
10186 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
10187 | static int cons_sign = -1; |
10188 | ||
10189 | void | |
e3bb37b5 | 10190 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 10191 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 10192 | { |
d258b828 | 10193 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
10194 | |
10195 | #ifdef TE_PE | |
10196 | if (exp->X_op == O_secrel) | |
10197 | { | |
10198 | exp->X_op = O_symbol; | |
10199 | r = BFD_RELOC_32_SECREL; | |
10200 | } | |
145667f8 MH |
10201 | else if (exp->X_op == O_secidx) |
10202 | r = BFD_RELOC_16_SECIDX; | |
d182319b JB |
10203 | #endif |
10204 | ||
10205 | fix_new_exp (frag, off, len, exp, 0, r); | |
10206 | } | |
10207 | ||
357d1bd8 L |
10208 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
10209 | purpose of the `.dc.a' internal pseudo-op. */ | |
10210 | ||
10211 | int | |
10212 | x86_address_bytes (void) | |
10213 | { | |
10214 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
10215 | return 4; | |
10216 | return stdoutput->arch_info->bits_per_address / 8; | |
10217 | } | |
10218 | ||
deea4973 JB |
10219 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
10220 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 10221 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 10222 | #else |
f3c180ae AM |
10223 | /* Parse operands of the form |
10224 | <symbol>@GOTOFF+<nnn> | |
10225 | and similar .plt or .got references. | |
10226 | ||
10227 | If we find one, set up the correct relocation in RELOC and copy the | |
10228 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
10229 | parsing by the calling routine. Return this buffer, and if ADJUST | |
10230 | is non-null set it to the length of the string we removed from the | |
10231 | input line. Otherwise return NULL. */ | |
10232 | static char * | |
91d6fa6a | 10233 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 10234 | int *adjust, |
d258b828 | 10235 | i386_operand_type *types) |
f3c180ae | 10236 | { |
7b81dfbb AJ |
10237 | /* Some of the relocations depend on the size of what field is to |
10238 | be relocated. But in our callers i386_immediate and i386_displacement | |
10239 | we don't yet know the operand size (this will be set by insn | |
10240 | matching). Hence we record the word32 relocation here, | |
10241 | and adjust the reloc according to the real size in reloc(). */ | |
145667f8 MH |
10242 | static const struct |
10243 | { | |
f3c180ae | 10244 | const char *str; |
cff8d58a | 10245 | int len; |
4fa24527 | 10246 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 10247 | const i386_operand_type types64; |
5b7c81bd | 10248 | bool need_GOT_symbol; |
145667f8 MH |
10249 | } |
10250 | gotrel[] = | |
10251 | { | |
deea4973 | 10252 | #ifndef TE_PE |
8ce3d284 | 10253 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10254 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
10255 | BFD_RELOC_SIZE32 }, | |
5b7c81bd | 10256 | OPERAND_TYPE_IMM32_64, false }, |
8ce3d284 | 10257 | #endif |
cff8d58a L |
10258 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
10259 | BFD_RELOC_X86_64_PLTOFF64 }, | |
5b7c81bd | 10260 | OPERAND_TYPE_IMM64, true }, |
cff8d58a L |
10261 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
10262 | BFD_RELOC_X86_64_PLT32 }, | |
a775efc8 | 10263 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
10264 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
10265 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 10266 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10267 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
10268 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 10269 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10270 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
10271 | BFD_RELOC_X86_64_GOTPCREL }, | |
a775efc8 | 10272 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10273 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
10274 | BFD_RELOC_X86_64_TLSGD }, | |
a775efc8 | 10275 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10276 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
10277 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10278 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10279 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
10280 | BFD_RELOC_X86_64_TLSLD }, | |
a775efc8 | 10281 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10282 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
10283 | BFD_RELOC_X86_64_GOTTPOFF }, | |
a775efc8 | 10284 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10285 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
10286 | BFD_RELOC_X86_64_TPOFF32 }, | |
a775efc8 | 10287 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10288 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
10289 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10290 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10291 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
10292 | BFD_RELOC_X86_64_DTPOFF32 }, | |
a775efc8 | 10293 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10294 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
10295 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10296 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10297 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
10298 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10299 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10300 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
10301 | BFD_RELOC_X86_64_GOT32 }, | |
a775efc8 | 10302 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
10303 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
10304 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
a775efc8 | 10305 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10306 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
10307 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
a775efc8 | 10308 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
10309 | #else /* TE_PE */ |
10310 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
10311 | BFD_RELOC_32_SECREL }, | |
a775efc8 | 10312 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, |
deea4973 | 10313 | #endif |
f3c180ae AM |
10314 | }; |
10315 | char *cp; | |
10316 | unsigned int j; | |
10317 | ||
deea4973 | 10318 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
10319 | if (!IS_ELF) |
10320 | return NULL; | |
d382c579 | 10321 | #endif |
718ddfc0 | 10322 | |
f3c180ae | 10323 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 10324 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
10325 | return NULL; |
10326 | ||
47465058 | 10327 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 10328 | { |
cff8d58a | 10329 | int len = gotrel[j].len; |
28f81592 | 10330 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 10331 | { |
4fa24527 | 10332 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 10333 | { |
28f81592 AM |
10334 | int first, second; |
10335 | char *tmpbuf, *past_reloc; | |
f3c180ae | 10336 | |
91d6fa6a | 10337 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 10338 | |
3956db08 JB |
10339 | if (types) |
10340 | { | |
10341 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
10342 | { |
10343 | types->bitfield.imm32 = 1; | |
10344 | types->bitfield.disp32 = 1; | |
10345 | } | |
3956db08 JB |
10346 | else |
10347 | *types = gotrel[j].types64; | |
10348 | } | |
10349 | ||
844bf810 | 10350 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
10351 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
10352 | ||
28f81592 | 10353 | /* The length of the first part of our input line. */ |
f3c180ae | 10354 | first = cp - input_line_pointer; |
28f81592 AM |
10355 | |
10356 | /* The second part goes from after the reloc token until | |
67c11a9b | 10357 | (and including) an end_of_line char or comma. */ |
28f81592 | 10358 | past_reloc = cp + 1 + len; |
67c11a9b AM |
10359 | cp = past_reloc; |
10360 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10361 | ++cp; | |
10362 | second = cp + 1 - past_reloc; | |
28f81592 AM |
10363 | |
10364 | /* Allocate and copy string. The trailing NUL shouldn't | |
10365 | be necessary, but be safe. */ | |
add39d23 | 10366 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 10367 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
10368 | if (second != 0 && *past_reloc != ' ') |
10369 | /* Replace the relocation token with ' ', so that | |
10370 | errors like foo@GOTOFF1 will be detected. */ | |
10371 | tmpbuf[first++] = ' '; | |
af89796a L |
10372 | else |
10373 | /* Increment length by 1 if the relocation token is | |
10374 | removed. */ | |
10375 | len++; | |
10376 | if (adjust) | |
10377 | *adjust = len; | |
0787a12d AM |
10378 | memcpy (tmpbuf + first, past_reloc, second); |
10379 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
10380 | return tmpbuf; |
10381 | } | |
10382 | ||
4fa24527 JB |
10383 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
10384 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
10385 | return NULL; |
10386 | } | |
10387 | } | |
10388 | ||
10389 | /* Might be a symbol version string. Don't as_bad here. */ | |
10390 | return NULL; | |
10391 | } | |
4e4f7c87 | 10392 | #endif |
f3c180ae | 10393 | |
62ebcb5c | 10394 | bfd_reloc_code_real_type |
e3bb37b5 | 10395 | x86_cons (expressionS *exp, int size) |
f3c180ae | 10396 | { |
62ebcb5c AM |
10397 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
10398 | ||
2748c1b1 L |
10399 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
10400 | && !defined (LEX_AT)) \ | |
10401 | || defined (TE_PE) | |
ee86248c JB |
10402 | intel_syntax = -intel_syntax; |
10403 | ||
3c7b9c2c | 10404 | exp->X_md = 0; |
4fa24527 | 10405 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
10406 | { |
10407 | /* Handle @GOTOFF and the like in an expression. */ | |
10408 | char *save; | |
10409 | char *gotfree_input_line; | |
4a57f2cf | 10410 | int adjust = 0; |
f3c180ae AM |
10411 | |
10412 | save = input_line_pointer; | |
d258b828 | 10413 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
10414 | if (gotfree_input_line) |
10415 | input_line_pointer = gotfree_input_line; | |
10416 | ||
10417 | expression (exp); | |
10418 | ||
10419 | if (gotfree_input_line) | |
10420 | { | |
10421 | /* expression () has merrily parsed up to the end of line, | |
10422 | or a comma - in the wrong buffer. Transfer how far | |
10423 | input_line_pointer has moved to the right buffer. */ | |
10424 | input_line_pointer = (save | |
10425 | + (input_line_pointer - gotfree_input_line) | |
10426 | + adjust); | |
10427 | free (gotfree_input_line); | |
3992d3b7 AM |
10428 | if (exp->X_op == O_constant |
10429 | || exp->X_op == O_absent | |
10430 | || exp->X_op == O_illegal | |
0398aac5 | 10431 | || exp->X_op == O_register |
3992d3b7 AM |
10432 | || exp->X_op == O_big) |
10433 | { | |
10434 | char c = *input_line_pointer; | |
10435 | *input_line_pointer = 0; | |
10436 | as_bad (_("missing or invalid expression `%s'"), save); | |
10437 | *input_line_pointer = c; | |
10438 | } | |
b9519cfe L |
10439 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
10440 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
10441 | && exp->X_op != O_symbol) | |
10442 | { | |
10443 | char c = *input_line_pointer; | |
10444 | *input_line_pointer = 0; | |
10445 | as_bad (_("invalid PLT expression `%s'"), save); | |
10446 | *input_line_pointer = c; | |
10447 | } | |
f3c180ae AM |
10448 | } |
10449 | } | |
10450 | else | |
10451 | expression (exp); | |
ee86248c JB |
10452 | |
10453 | intel_syntax = -intel_syntax; | |
10454 | ||
10455 | if (intel_syntax) | |
10456 | i386_intel_simplify (exp); | |
2748c1b1 L |
10457 | #else |
10458 | expression (exp); | |
10459 | #endif | |
62ebcb5c | 10460 | |
a442cac5 JB |
10461 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ |
10462 | if (size == 4 && exp->X_op == O_constant && !object_64bit) | |
10463 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
10464 | ||
62ebcb5c | 10465 | return got_reloc; |
f3c180ae | 10466 | } |
f3c180ae | 10467 | |
9f32dd5b L |
10468 | static void |
10469 | signed_cons (int size) | |
6482c264 | 10470 | { |
a442cac5 | 10471 | if (object_64bit) |
d182319b JB |
10472 | cons_sign = 1; |
10473 | cons (size); | |
10474 | cons_sign = -1; | |
6482c264 NC |
10475 | } |
10476 | ||
d182319b | 10477 | #ifdef TE_PE |
6482c264 | 10478 | static void |
7016a5d5 | 10479 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
10480 | { |
10481 | expressionS exp; | |
10482 | ||
10483 | do | |
10484 | { | |
10485 | expression (&exp); | |
10486 | if (exp.X_op == O_symbol) | |
10487 | exp.X_op = O_secrel; | |
10488 | ||
10489 | emit_expr (&exp, 4); | |
10490 | } | |
10491 | while (*input_line_pointer++ == ','); | |
10492 | ||
10493 | input_line_pointer--; | |
10494 | demand_empty_rest_of_line (); | |
10495 | } | |
145667f8 MH |
10496 | |
10497 | static void | |
10498 | pe_directive_secidx (int dummy ATTRIBUTE_UNUSED) | |
10499 | { | |
10500 | expressionS exp; | |
10501 | ||
10502 | do | |
10503 | { | |
10504 | expression (&exp); | |
10505 | if (exp.X_op == O_symbol) | |
10506 | exp.X_op = O_secidx; | |
10507 | ||
10508 | emit_expr (&exp, 2); | |
10509 | } | |
10510 | while (*input_line_pointer++ == ','); | |
10511 | ||
10512 | input_line_pointer--; | |
10513 | demand_empty_rest_of_line (); | |
10514 | } | |
6482c264 NC |
10515 | #endif |
10516 | ||
7063667e JB |
10517 | /* Handle Rounding Control / SAE specifiers. */ |
10518 | ||
10519 | static char * | |
10520 | RC_SAE_specifier (const char *pstr) | |
10521 | { | |
10522 | unsigned int j; | |
10523 | ||
10524 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10525 | { | |
10526 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10527 | { | |
10528 | if (i.rounding.type != rc_none) | |
10529 | { | |
10530 | as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name); | |
10531 | return NULL; | |
10532 | } | |
10533 | ||
10534 | i.rounding.type = RC_NamesTable[j].type; | |
10535 | ||
10536 | return (char *)(pstr + RC_NamesTable[j].len); | |
10537 | } | |
10538 | } | |
10539 | ||
10540 | return NULL; | |
10541 | } | |
10542 | ||
43234a1e L |
10543 | /* Handle Vector operations. */ |
10544 | ||
10545 | static char * | |
f70c6814 | 10546 | check_VecOperations (char *op_string) |
43234a1e L |
10547 | { |
10548 | const reg_entry *mask; | |
10549 | const char *saved; | |
10550 | char *end_op; | |
10551 | ||
f70c6814 | 10552 | while (*op_string) |
43234a1e L |
10553 | { |
10554 | saved = op_string; | |
10555 | if (*op_string == '{') | |
10556 | { | |
10557 | op_string++; | |
10558 | ||
10559 | /* Check broadcasts. */ | |
d34049e8 | 10560 | if (startswith (op_string, "1to")) |
43234a1e | 10561 | { |
5273a3cd | 10562 | unsigned int bcst_type; |
43234a1e | 10563 | |
5273a3cd | 10564 | if (i.broadcast.type) |
43234a1e L |
10565 | goto duplicated_vec_op; |
10566 | ||
10567 | op_string += 3; | |
10568 | if (*op_string == '8') | |
8e6e0792 | 10569 | bcst_type = 8; |
b28d1bda | 10570 | else if (*op_string == '4') |
8e6e0792 | 10571 | bcst_type = 4; |
b28d1bda | 10572 | else if (*op_string == '2') |
8e6e0792 | 10573 | bcst_type = 2; |
43234a1e L |
10574 | else if (*op_string == '1' |
10575 | && *(op_string+1) == '6') | |
10576 | { | |
8e6e0792 | 10577 | bcst_type = 16; |
43234a1e L |
10578 | op_string++; |
10579 | } | |
0cc78721 CL |
10580 | else if (*op_string == '3' |
10581 | && *(op_string+1) == '2') | |
10582 | { | |
10583 | bcst_type = 32; | |
10584 | op_string++; | |
10585 | } | |
43234a1e L |
10586 | else |
10587 | { | |
10588 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
10589 | return NULL; | |
10590 | } | |
10591 | op_string++; | |
10592 | ||
5273a3cd JB |
10593 | i.broadcast.type = bcst_type; |
10594 | i.broadcast.operand = this_operand; | |
43234a1e L |
10595 | } |
10596 | /* Check masking operation. */ | |
10597 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
10598 | { | |
8a6fb3f9 JB |
10599 | if (mask == &bad_reg) |
10600 | return NULL; | |
10601 | ||
43234a1e | 10602 | /* k0 can't be used for write mask. */ |
f74a6307 | 10603 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 10604 | { |
6d2cd6b2 JB |
10605 | as_bad (_("`%s%s' can't be used for write mask"), |
10606 | register_prefix, mask->reg_name); | |
43234a1e L |
10607 | return NULL; |
10608 | } | |
10609 | ||
6225c532 | 10610 | if (!i.mask.reg) |
43234a1e | 10611 | { |
6225c532 JB |
10612 | i.mask.reg = mask; |
10613 | i.mask.operand = this_operand; | |
43234a1e | 10614 | } |
6225c532 JB |
10615 | else if (i.mask.reg->reg_num) |
10616 | goto duplicated_vec_op; | |
43234a1e L |
10617 | else |
10618 | { | |
6225c532 | 10619 | i.mask.reg = mask; |
43234a1e L |
10620 | |
10621 | /* Only "{z}" is allowed here. No need to check | |
10622 | zeroing mask explicitly. */ | |
6225c532 | 10623 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10624 | { |
10625 | as_bad (_("invalid write mask `%s'"), saved); | |
10626 | return NULL; | |
10627 | } | |
10628 | } | |
10629 | ||
10630 | op_string = end_op; | |
10631 | } | |
10632 | /* Check zeroing-flag for masking operation. */ | |
10633 | else if (*op_string == 'z') | |
10634 | { | |
6225c532 | 10635 | if (!i.mask.reg) |
43234a1e | 10636 | { |
6225c532 JB |
10637 | i.mask.reg = reg_k0; |
10638 | i.mask.zeroing = 1; | |
10639 | i.mask.operand = this_operand; | |
43234a1e L |
10640 | } |
10641 | else | |
10642 | { | |
6225c532 | 10643 | if (i.mask.zeroing) |
43234a1e L |
10644 | { |
10645 | duplicated_vec_op: | |
10646 | as_bad (_("duplicated `%s'"), saved); | |
10647 | return NULL; | |
10648 | } | |
10649 | ||
6225c532 | 10650 | i.mask.zeroing = 1; |
43234a1e L |
10651 | |
10652 | /* Only "{%k}" is allowed here. No need to check mask | |
10653 | register explicitly. */ | |
6225c532 | 10654 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10655 | { |
10656 | as_bad (_("invalid zeroing-masking `%s'"), | |
10657 | saved); | |
10658 | return NULL; | |
10659 | } | |
10660 | } | |
10661 | ||
10662 | op_string++; | |
10663 | } | |
7063667e JB |
10664 | else if (intel_syntax |
10665 | && (op_string = RC_SAE_specifier (op_string)) != NULL) | |
10666 | i.rounding.modifier = true; | |
43234a1e L |
10667 | else |
10668 | goto unknown_vec_op; | |
10669 | ||
10670 | if (*op_string != '}') | |
10671 | { | |
10672 | as_bad (_("missing `}' in `%s'"), saved); | |
10673 | return NULL; | |
10674 | } | |
10675 | op_string++; | |
0ba3a731 L |
10676 | |
10677 | /* Strip whitespace since the addition of pseudo prefixes | |
10678 | changed how the scrubber treats '{'. */ | |
10679 | if (is_space_char (*op_string)) | |
10680 | ++op_string; | |
10681 | ||
43234a1e L |
10682 | continue; |
10683 | } | |
10684 | unknown_vec_op: | |
10685 | /* We don't know this one. */ | |
10686 | as_bad (_("unknown vector operation: `%s'"), saved); | |
10687 | return NULL; | |
10688 | } | |
10689 | ||
6225c532 | 10690 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
10691 | { |
10692 | as_bad (_("zeroing-masking only allowed with write mask")); | |
10693 | return NULL; | |
10694 | } | |
10695 | ||
43234a1e L |
10696 | return op_string; |
10697 | } | |
10698 | ||
252b5132 | 10699 | static int |
70e41ade | 10700 | i386_immediate (char *imm_start) |
252b5132 RH |
10701 | { |
10702 | char *save_input_line_pointer; | |
f3c180ae | 10703 | char *gotfree_input_line; |
252b5132 | 10704 | segT exp_seg = 0; |
47926f60 | 10705 | expressionS *exp; |
40fb9820 L |
10706 | i386_operand_type types; |
10707 | ||
0dfbf9d7 | 10708 | operand_type_set (&types, ~0); |
252b5132 RH |
10709 | |
10710 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
10711 | { | |
31b2323c L |
10712 | as_bad (_("at most %d immediate operands are allowed"), |
10713 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
10714 | return 0; |
10715 | } | |
10716 | ||
10717 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 10718 | i.op[this_operand].imms = exp; |
252b5132 RH |
10719 | |
10720 | if (is_space_char (*imm_start)) | |
10721 | ++imm_start; | |
10722 | ||
10723 | save_input_line_pointer = input_line_pointer; | |
10724 | input_line_pointer = imm_start; | |
10725 | ||
d258b828 | 10726 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10727 | if (gotfree_input_line) |
10728 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
10729 | |
10730 | exp_seg = expression (exp); | |
10731 | ||
83183c0c | 10732 | SKIP_WHITESPACE (); |
252b5132 | 10733 | if (*input_line_pointer) |
f3c180ae | 10734 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
10735 | |
10736 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 10737 | if (gotfree_input_line) |
ee86248c JB |
10738 | { |
10739 | free (gotfree_input_line); | |
10740 | ||
9aac24b1 | 10741 | if (exp->X_op == O_constant) |
ee86248c JB |
10742 | exp->X_op = O_illegal; |
10743 | } | |
10744 | ||
9aac24b1 JB |
10745 | if (exp_seg == reg_section) |
10746 | { | |
10747 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
10748 | return 0; | |
10749 | } | |
10750 | ||
ee86248c JB |
10751 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
10752 | } | |
252b5132 | 10753 | |
ee86248c JB |
10754 | static int |
10755 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10756 | i386_operand_type types, const char *imm_start) | |
10757 | { | |
10758 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 10759 | { |
313c53d1 L |
10760 | if (imm_start) |
10761 | as_bad (_("missing or invalid immediate expression `%s'"), | |
10762 | imm_start); | |
3992d3b7 | 10763 | return 0; |
252b5132 | 10764 | } |
3e73aa7c | 10765 | else if (exp->X_op == O_constant) |
252b5132 | 10766 | { |
47926f60 | 10767 | /* Size it properly later. */ |
40fb9820 | 10768 | i.types[this_operand].bitfield.imm64 = 1; |
a442cac5 JB |
10769 | |
10770 | /* If not 64bit, sign/zero extend val, to account for wraparound | |
10771 | when !BFD64. */ | |
10772 | if (flag_code != CODE_64BIT) | |
10773 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
252b5132 | 10774 | } |
4c63da97 | 10775 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 10776 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 10777 | && exp_seg != absolute_section |
47926f60 | 10778 | && exp_seg != text_section |
24eab124 AM |
10779 | && exp_seg != data_section |
10780 | && exp_seg != bss_section | |
10781 | && exp_seg != undefined_section | |
f86103b7 | 10782 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10783 | { |
d0b47220 | 10784 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10785 | return 0; |
10786 | } | |
10787 | #endif | |
10788 | else | |
10789 | { | |
10790 | /* This is an address. The size of the address will be | |
24eab124 | 10791 | determined later, depending on destination register, |
3e73aa7c | 10792 | suffix, or the default for the section. */ |
40fb9820 L |
10793 | i.types[this_operand].bitfield.imm8 = 1; |
10794 | i.types[this_operand].bitfield.imm16 = 1; | |
10795 | i.types[this_operand].bitfield.imm32 = 1; | |
10796 | i.types[this_operand].bitfield.imm32s = 1; | |
10797 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10798 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10799 | types); | |
252b5132 RH |
10800 | } |
10801 | ||
10802 | return 1; | |
10803 | } | |
10804 | ||
551c1ca1 | 10805 | static char * |
e3bb37b5 | 10806 | i386_scale (char *scale) |
252b5132 | 10807 | { |
551c1ca1 AM |
10808 | offsetT val; |
10809 | char *save = input_line_pointer; | |
252b5132 | 10810 | |
551c1ca1 AM |
10811 | input_line_pointer = scale; |
10812 | val = get_absolute_expression (); | |
10813 | ||
10814 | switch (val) | |
252b5132 | 10815 | { |
551c1ca1 | 10816 | case 1: |
252b5132 RH |
10817 | i.log2_scale_factor = 0; |
10818 | break; | |
551c1ca1 | 10819 | case 2: |
252b5132 RH |
10820 | i.log2_scale_factor = 1; |
10821 | break; | |
551c1ca1 | 10822 | case 4: |
252b5132 RH |
10823 | i.log2_scale_factor = 2; |
10824 | break; | |
551c1ca1 | 10825 | case 8: |
252b5132 RH |
10826 | i.log2_scale_factor = 3; |
10827 | break; | |
10828 | default: | |
a724f0f4 JB |
10829 | { |
10830 | char sep = *input_line_pointer; | |
10831 | ||
10832 | *input_line_pointer = '\0'; | |
10833 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10834 | scale); | |
10835 | *input_line_pointer = sep; | |
10836 | input_line_pointer = save; | |
10837 | return NULL; | |
10838 | } | |
252b5132 | 10839 | } |
29b0f896 | 10840 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10841 | { |
10842 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10843 | 1 << i.log2_scale_factor); |
252b5132 | 10844 | i.log2_scale_factor = 0; |
252b5132 | 10845 | } |
551c1ca1 AM |
10846 | scale = input_line_pointer; |
10847 | input_line_pointer = save; | |
10848 | return scale; | |
252b5132 RH |
10849 | } |
10850 | ||
252b5132 | 10851 | static int |
e3bb37b5 | 10852 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10853 | { |
29b0f896 | 10854 | expressionS *exp; |
252b5132 RH |
10855 | segT exp_seg = 0; |
10856 | char *save_input_line_pointer; | |
f3c180ae | 10857 | char *gotfree_input_line; |
40fb9820 L |
10858 | int override; |
10859 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10860 | int ret; |
252b5132 | 10861 | |
31b2323c L |
10862 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10863 | { | |
10864 | as_bad (_("at most %d displacement operands are allowed"), | |
10865 | MAX_MEMORY_OPERANDS); | |
10866 | return 0; | |
10867 | } | |
10868 | ||
0dfbf9d7 | 10869 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10870 | if (i.jumpabsolute |
48bcea9f | 10871 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10872 | || (current_templates->start->opcode_modifier.jump != JUMP |
10873 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10874 | { |
48bcea9f | 10875 | i386_addressing_mode (); |
e05278af | 10876 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10877 | if (flag_code == CODE_64BIT) |
10878 | { | |
a775efc8 | 10879 | bigdisp.bitfield.disp32 = 1; |
40fb9820 | 10880 | if (!override) |
a775efc8 | 10881 | bigdisp.bitfield.disp64 = 1; |
40fb9820 L |
10882 | } |
10883 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10884 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10885 | else |
10886 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10887 | } |
10888 | else | |
10889 | { | |
376cd056 JB |
10890 | /* For PC-relative branches, the width of the displacement may be |
10891 | dependent upon data size, but is never dependent upon address size. | |
10892 | Also make sure to not unintentionally match against a non-PC-relative | |
10893 | branch template. */ | |
10894 | static templates aux_templates; | |
10895 | const insn_template *t = current_templates->start; | |
5b7c81bd | 10896 | bool has_intel64 = false; |
376cd056 JB |
10897 | |
10898 | aux_templates.start = t; | |
10899 | while (++t < current_templates->end) | |
10900 | { | |
10901 | if (t->opcode_modifier.jump | |
10902 | != current_templates->start->opcode_modifier.jump) | |
10903 | break; | |
4b5aaf5f | 10904 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 10905 | has_intel64 = true; |
376cd056 JB |
10906 | } |
10907 | if (t < current_templates->end) | |
10908 | { | |
10909 | aux_templates.end = t; | |
10910 | current_templates = &aux_templates; | |
10911 | } | |
10912 | ||
e05278af | 10913 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10914 | if (flag_code == CODE_64BIT) |
10915 | { | |
376cd056 JB |
10916 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10917 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10918 | bigdisp.bitfield.disp16 = 1; |
10919 | else | |
a775efc8 | 10920 | bigdisp.bitfield.disp32 = 1; |
40fb9820 L |
10921 | } |
10922 | else | |
e05278af JB |
10923 | { |
10924 | if (!override) | |
10925 | override = (i.suffix == (flag_code != CODE_16BIT | |
10926 | ? WORD_MNEM_SUFFIX | |
10927 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10928 | bigdisp.bitfield.disp32 = 1; |
10929 | if ((flag_code == CODE_16BIT) ^ override) | |
10930 | { | |
10931 | bigdisp.bitfield.disp32 = 0; | |
10932 | bigdisp.bitfield.disp16 = 1; | |
10933 | } | |
e05278af | 10934 | } |
e05278af | 10935 | } |
c6fb90c8 L |
10936 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10937 | bigdisp); | |
252b5132 RH |
10938 | |
10939 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10940 | i.op[this_operand].disps = exp; |
252b5132 RH |
10941 | i.disp_operands++; |
10942 | save_input_line_pointer = input_line_pointer; | |
10943 | input_line_pointer = disp_start; | |
10944 | END_STRING_AND_SAVE (disp_end); | |
10945 | ||
10946 | #ifndef GCC_ASM_O_HACK | |
10947 | #define GCC_ASM_O_HACK 0 | |
10948 | #endif | |
10949 | #if GCC_ASM_O_HACK | |
10950 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10951 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10952 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10953 | { |
10954 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10955 | constraint within gcc asm statements. |
10956 | For instance: | |
10957 | ||
10958 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10959 | __asm__ __volatile__ ( \ | |
10960 | "movw %w2,%0\n\t" \ | |
10961 | "movw %w1,2+%0\n\t" \ | |
10962 | "rorl $16,%1\n\t" \ | |
10963 | "movb %b1,4+%0\n\t" \ | |
10964 | "movb %4,5+%0\n\t" \ | |
10965 | "movb $0,6+%0\n\t" \ | |
10966 | "movb %h1,7+%0\n\t" \ | |
10967 | "rorl $16,%1" \ | |
10968 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10969 | ||
10970 | This works great except that the output assembler ends | |
10971 | up looking a bit weird if it turns out that there is | |
10972 | no offset. You end up producing code that looks like: | |
10973 | ||
10974 | #APP | |
10975 | movw $235,(%eax) | |
10976 | movw %dx,2+(%eax) | |
10977 | rorl $16,%edx | |
10978 | movb %dl,4+(%eax) | |
10979 | movb $137,5+(%eax) | |
10980 | movb $0,6+(%eax) | |
10981 | movb %dh,7+(%eax) | |
10982 | rorl $16,%edx | |
10983 | #NO_APP | |
10984 | ||
47926f60 | 10985 | So here we provide the missing zero. */ |
24eab124 AM |
10986 | |
10987 | *displacement_string_end = '0'; | |
252b5132 RH |
10988 | } |
10989 | #endif | |
d258b828 | 10990 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10991 | if (gotfree_input_line) |
10992 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10993 | |
24eab124 | 10994 | exp_seg = expression (exp); |
252b5132 | 10995 | |
636c26b0 AM |
10996 | SKIP_WHITESPACE (); |
10997 | if (*input_line_pointer) | |
10998 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10999 | #if GCC_ASM_O_HACK | |
11000 | RESTORE_END_STRING (disp_end + 1); | |
11001 | #endif | |
636c26b0 | 11002 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 11003 | if (gotfree_input_line) |
ee86248c JB |
11004 | { |
11005 | free (gotfree_input_line); | |
11006 | ||
11007 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
11008 | exp->X_op = O_illegal; | |
11009 | } | |
11010 | ||
11011 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
11012 | ||
11013 | RESTORE_END_STRING (disp_end); | |
11014 | ||
11015 | return ret; | |
11016 | } | |
11017 | ||
11018 | static int | |
11019 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
11020 | i386_operand_type types, const char *disp_start) | |
11021 | { | |
ee86248c | 11022 | int ret = 1; |
636c26b0 | 11023 | |
24eab124 AM |
11024 | /* We do this to make sure that the section symbol is in |
11025 | the symbol table. We will ultimately change the relocation | |
47926f60 | 11026 | to be relative to the beginning of the section. */ |
1ae12ab7 | 11027 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
11028 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
11029 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 11030 | { |
636c26b0 | 11031 | if (exp->X_op != O_symbol) |
3992d3b7 | 11032 | goto inv_disp; |
636c26b0 | 11033 | |
e5cb08ac | 11034 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
11035 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
11036 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 11037 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
11038 | exp->X_op = O_subtract; |
11039 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 11040 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 11041 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
11042 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
11043 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 11044 | else |
29b0f896 | 11045 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 11046 | } |
252b5132 | 11047 | |
3992d3b7 AM |
11048 | else if (exp->X_op == O_absent |
11049 | || exp->X_op == O_illegal | |
ee86248c | 11050 | || exp->X_op == O_big) |
2daf4fd8 | 11051 | { |
3992d3b7 AM |
11052 | inv_disp: |
11053 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 11054 | disp_start); |
3992d3b7 | 11055 | ret = 0; |
2daf4fd8 AM |
11056 | } |
11057 | ||
a50187b2 JB |
11058 | else if (exp->X_op == O_constant) |
11059 | { | |
11060 | /* Sizing gets taken care of by optimize_disp(). | |
11061 | ||
11062 | If not 64bit, sign/zero extend val, to account for wraparound | |
11063 | when !BFD64. */ | |
11064 | if (flag_code != CODE_64BIT) | |
11065 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
11066 | } | |
11067 | ||
4c63da97 | 11068 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
a50187b2 | 11069 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
3992d3b7 AM |
11070 | && exp_seg != absolute_section |
11071 | && exp_seg != text_section | |
11072 | && exp_seg != data_section | |
11073 | && exp_seg != bss_section | |
11074 | && exp_seg != undefined_section | |
11075 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 11076 | { |
d0b47220 | 11077 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 11078 | ret = 0; |
24eab124 | 11079 | } |
252b5132 | 11080 | #endif |
3956db08 | 11081 | |
a50187b2 | 11082 | else if (current_templates->start->opcode_modifier.jump == JUMP_BYTE) |
48bcea9f JB |
11083 | i.types[this_operand].bitfield.disp8 = 1; |
11084 | ||
40fb9820 | 11085 | /* Check if this is a displacement only operand. */ |
02b83698 JB |
11086 | if (!i.types[this_operand].bitfield.baseindex) |
11087 | i.types[this_operand] = | |
11088 | operand_type_or (operand_type_and_not (i.types[this_operand], anydisp), | |
11089 | operand_type_and (i.types[this_operand], types)); | |
3956db08 | 11090 | |
3992d3b7 | 11091 | return ret; |
252b5132 RH |
11092 | } |
11093 | ||
2abc2bec JB |
11094 | /* Return the active addressing mode, taking address override and |
11095 | registers forming the address into consideration. Update the | |
11096 | address override prefix if necessary. */ | |
47926f60 | 11097 | |
2abc2bec JB |
11098 | static enum flag_code |
11099 | i386_addressing_mode (void) | |
252b5132 | 11100 | { |
be05d201 L |
11101 | enum flag_code addr_mode; |
11102 | ||
11103 | if (i.prefix[ADDR_PREFIX]) | |
11104 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 JB |
11105 | else if (flag_code == CODE_16BIT |
11106 | && current_templates->start->cpu_flags.bitfield.cpumpx | |
11107 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic | |
11108 | from md_assemble() by "is not a valid base/index expression" | |
11109 | when there is a base and/or index. */ | |
11110 | && !i.types[this_operand].bitfield.baseindex) | |
11111 | { | |
11112 | /* MPX insn memory operands with neither base nor index must be forced | |
11113 | to use 32-bit addressing in 16-bit mode. */ | |
11114 | addr_mode = CODE_32BIT; | |
11115 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11116 | ++i.prefixes; | |
11117 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
11118 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
11119 | } | |
be05d201 L |
11120 | else |
11121 | { | |
11122 | addr_mode = flag_code; | |
11123 | ||
24eab124 | 11124 | #if INFER_ADDR_PREFIX |
be05d201 L |
11125 | if (i.mem_operands == 0) |
11126 | { | |
11127 | /* Infer address prefix from the first memory operand. */ | |
11128 | const reg_entry *addr_reg = i.base_reg; | |
11129 | ||
11130 | if (addr_reg == NULL) | |
11131 | addr_reg = i.index_reg; | |
eecb386c | 11132 | |
be05d201 L |
11133 | if (addr_reg) |
11134 | { | |
e968fc9b | 11135 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
11136 | addr_mode = CODE_32BIT; |
11137 | else if (flag_code != CODE_64BIT | |
dc821c5f | 11138 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
11139 | addr_mode = CODE_16BIT; |
11140 | ||
11141 | if (addr_mode != flag_code) | |
11142 | { | |
11143 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11144 | i.prefixes += 1; | |
11145 | /* Change the size of any displacement too. At most one | |
11146 | of Disp16 or Disp32 is set. | |
11147 | FIXME. There doesn't seem to be any real need for | |
11148 | separate Disp16 and Disp32 flags. The same goes for | |
11149 | Imm16 and Imm32. Removing them would probably clean | |
11150 | up the code quite a lot. */ | |
11151 | if (flag_code != CODE_64BIT | |
11152 | && (i.types[this_operand].bitfield.disp16 | |
11153 | || i.types[this_operand].bitfield.disp32)) | |
11154 | i.types[this_operand] | |
11155 | = operand_type_xor (i.types[this_operand], disp16_32); | |
11156 | } | |
11157 | } | |
11158 | } | |
24eab124 | 11159 | #endif |
be05d201 L |
11160 | } |
11161 | ||
2abc2bec JB |
11162 | return addr_mode; |
11163 | } | |
11164 | ||
11165 | /* Make sure the memory operand we've been dealt is valid. | |
11166 | Return 1 on success, 0 on a failure. */ | |
11167 | ||
11168 | static int | |
11169 | i386_index_check (const char *operand_string) | |
11170 | { | |
11171 | const char *kind = "base/index"; | |
11172 | enum flag_code addr_mode = i386_addressing_mode (); | |
a152332d | 11173 | const insn_template *t = current_templates->start; |
2abc2bec | 11174 | |
a152332d JB |
11175 | if (t->opcode_modifier.isstring |
11176 | && !t->cpu_flags.bitfield.cpupadlock | |
fc0763e6 JB |
11177 | && (current_templates->end[-1].opcode_modifier.isstring |
11178 | || i.mem_operands)) | |
11179 | { | |
11180 | /* Memory operands of string insns are special in that they only allow | |
11181 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
11182 | const reg_entry *expected_reg; |
11183 | static const char *di_si[][2] = | |
11184 | { | |
11185 | { "esi", "edi" }, | |
11186 | { "si", "di" }, | |
11187 | { "rsi", "rdi" } | |
11188 | }; | |
11189 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
11190 | |
11191 | kind = "string address"; | |
11192 | ||
a152332d | 11193 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 11194 | { |
51c8edf6 JB |
11195 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
11196 | - IS_STRING_ES_OP0; | |
11197 | int op = 0; | |
fc0763e6 | 11198 | |
51c8edf6 | 11199 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
11200 | || ((!i.mem_operands != !intel_syntax) |
11201 | && current_templates->end[-1].operand_types[1] | |
11202 | .bitfield.baseindex)) | |
51c8edf6 | 11203 | op = 1; |
fe0e921f AM |
11204 | expected_reg |
11205 | = (const reg_entry *) str_hash_find (reg_hash, | |
11206 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
11207 | } |
11208 | else | |
fe0e921f AM |
11209 | expected_reg |
11210 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 11211 | |
be05d201 L |
11212 | if (i.base_reg != expected_reg |
11213 | || i.index_reg | |
fc0763e6 | 11214 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 11215 | { |
be05d201 L |
11216 | /* The second memory operand must have the same size as |
11217 | the first one. */ | |
11218 | if (i.mem_operands | |
11219 | && i.base_reg | |
11220 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 11221 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 11222 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
11223 | ? i.base_reg->reg_type.bitfield.dword |
11224 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
11225 | goto bad_address; |
11226 | ||
fc0763e6 JB |
11227 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
11228 | operand_string, | |
11229 | intel_syntax ? '[' : '(', | |
11230 | register_prefix, | |
be05d201 | 11231 | expected_reg->reg_name, |
fc0763e6 | 11232 | intel_syntax ? ']' : ')'); |
be05d201 | 11233 | return 1; |
fc0763e6 | 11234 | } |
be05d201 L |
11235 | else |
11236 | return 1; | |
11237 | ||
dc1e8a47 | 11238 | bad_address: |
be05d201 L |
11239 | as_bad (_("`%s' is not a valid %s expression"), |
11240 | operand_string, kind); | |
11241 | return 0; | |
3e73aa7c JH |
11242 | } |
11243 | else | |
11244 | { | |
be05d201 L |
11245 | if (addr_mode != CODE_16BIT) |
11246 | { | |
11247 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
11248 | if (i.disp_encoding == disp_encoding_16bit) |
11249 | { | |
11250 | bad_disp: | |
11251 | as_bad (_("invalid `%s' prefix"), | |
11252 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
11253 | return 0; | |
11254 | } | |
11255 | ||
be05d201 | 11256 | if ((i.base_reg |
e968fc9b JB |
11257 | && ((addr_mode == CODE_64BIT |
11258 | ? !i.base_reg->reg_type.bitfield.qword | |
11259 | : !i.base_reg->reg_type.bitfield.dword) | |
11260 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
11261 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 11262 | || (i.index_reg |
1b54b8d7 JB |
11263 | && !i.index_reg->reg_type.bitfield.xmmword |
11264 | && !i.index_reg->reg_type.bitfield.ymmword | |
11265 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 11266 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
11267 | ? !i.index_reg->reg_type.bitfield.qword |
11268 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
11269 | || !i.index_reg->reg_type.bitfield.baseindex))) |
11270 | goto bad_address; | |
8178be5b | 11271 | |
260cd341 | 11272 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
a152332d | 11273 | if ((t->opcode_modifier.opcodeprefix == PREFIX_0XF3 |
389d00a5 JB |
11274 | && t->opcode_modifier.opcodespace == SPACE_0F |
11275 | && t->base_opcode == 0x1b) | |
a152332d | 11276 | || (t->opcode_modifier.opcodeprefix == PREFIX_NONE |
389d00a5 JB |
11277 | && t->opcode_modifier.opcodespace == SPACE_0F |
11278 | && (t->base_opcode & ~1) == 0x1a) | |
a152332d | 11279 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
11280 | { |
11281 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 11282 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
11283 | { |
11284 | as_bad (_("`%s' cannot be used here"), operand_string); | |
11285 | return 0; | |
11286 | } | |
11287 | ||
11288 | /* bndldx and bndstx ignore their scale factor. */ | |
a152332d | 11289 | if (t->opcode_modifier.opcodeprefix == PREFIX_NONE |
389d00a5 JB |
11290 | && t->opcode_modifier.opcodespace == SPACE_0F |
11291 | && (t->base_opcode & ~1) == 0x1a | |
8178be5b JB |
11292 | && i.log2_scale_factor) |
11293 | as_warn (_("register scaling is being ignored here")); | |
11294 | } | |
be05d201 L |
11295 | } |
11296 | else | |
3e73aa7c | 11297 | { |
be05d201 | 11298 | /* 16-bit checks. */ |
41eb8e88 L |
11299 | if (i.disp_encoding == disp_encoding_32bit) |
11300 | goto bad_disp; | |
11301 | ||
3e73aa7c | 11302 | if ((i.base_reg |
dc821c5f | 11303 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 11304 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 11305 | || (i.index_reg |
dc821c5f | 11306 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 11307 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
11308 | || !(i.base_reg |
11309 | && i.base_reg->reg_num < 6 | |
11310 | && i.index_reg->reg_num >= 6 | |
11311 | && i.log2_scale_factor == 0)))) | |
be05d201 | 11312 | goto bad_address; |
3e73aa7c JH |
11313 | } |
11314 | } | |
be05d201 | 11315 | return 1; |
24eab124 | 11316 | } |
252b5132 | 11317 | |
43234a1e L |
11318 | /* Handle vector immediates. */ |
11319 | ||
11320 | static int | |
11321 | RC_SAE_immediate (const char *imm_start) | |
11322 | { | |
43234a1e | 11323 | const char *pstr = imm_start; |
43234a1e L |
11324 | |
11325 | if (*pstr != '{') | |
11326 | return 0; | |
11327 | ||
7063667e JB |
11328 | pstr = RC_SAE_specifier (pstr + 1); |
11329 | if (pstr == NULL) | |
43234a1e L |
11330 | return 0; |
11331 | ||
11332 | if (*pstr++ != '}') | |
11333 | { | |
11334 | as_bad (_("Missing '}': '%s'"), imm_start); | |
11335 | return 0; | |
11336 | } | |
11337 | /* RC/SAE immediate string should contain nothing more. */; | |
11338 | if (*pstr != 0) | |
11339 | { | |
11340 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
11341 | return 0; | |
11342 | } | |
11343 | ||
cf665fee JB |
11344 | /* Internally this doesn't count as an operand. */ |
11345 | --i.operands; | |
43234a1e | 11346 | |
43234a1e L |
11347 | return 1; |
11348 | } | |
11349 | ||
8325cc63 JB |
11350 | /* Only string instructions can have a second memory operand, so |
11351 | reduce current_templates to just those if it contains any. */ | |
11352 | static int | |
11353 | maybe_adjust_templates (void) | |
11354 | { | |
11355 | const insn_template *t; | |
11356 | ||
11357 | gas_assert (i.mem_operands == 1); | |
11358 | ||
11359 | for (t = current_templates->start; t < current_templates->end; ++t) | |
11360 | if (t->opcode_modifier.isstring) | |
11361 | break; | |
11362 | ||
11363 | if (t < current_templates->end) | |
11364 | { | |
11365 | static templates aux_templates; | |
5b7c81bd | 11366 | bool recheck; |
8325cc63 JB |
11367 | |
11368 | aux_templates.start = t; | |
11369 | for (; t < current_templates->end; ++t) | |
11370 | if (!t->opcode_modifier.isstring) | |
11371 | break; | |
11372 | aux_templates.end = t; | |
11373 | ||
11374 | /* Determine whether to re-check the first memory operand. */ | |
11375 | recheck = (aux_templates.start != current_templates->start | |
11376 | || t != current_templates->end); | |
11377 | ||
11378 | current_templates = &aux_templates; | |
11379 | ||
11380 | if (recheck) | |
11381 | { | |
11382 | i.mem_operands = 0; | |
11383 | if (i.memop1_string != NULL | |
11384 | && i386_index_check (i.memop1_string) == 0) | |
11385 | return 0; | |
11386 | i.mem_operands = 1; | |
11387 | } | |
11388 | } | |
11389 | ||
11390 | return 1; | |
11391 | } | |
11392 | ||
9d299bea JB |
11393 | static INLINE bool starts_memory_operand (char c) |
11394 | { | |
014fbcda | 11395 | return ISDIGIT (c) |
9d299bea | 11396 | || is_identifier_char (c) |
014fbcda | 11397 | || strchr ("([\"+-!~", c); |
9d299bea JB |
11398 | } |
11399 | ||
fc0763e6 | 11400 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 11401 | on error. */ |
252b5132 | 11402 | |
252b5132 | 11403 | static int |
a7619375 | 11404 | i386_att_operand (char *operand_string) |
252b5132 | 11405 | { |
af6bdddf AM |
11406 | const reg_entry *r; |
11407 | char *end_op; | |
24eab124 | 11408 | char *op_string = operand_string; |
252b5132 | 11409 | |
24eab124 | 11410 | if (is_space_char (*op_string)) |
252b5132 RH |
11411 | ++op_string; |
11412 | ||
24eab124 | 11413 | /* We check for an absolute prefix (differentiating, |
47926f60 | 11414 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
11415 | if (*op_string == ABSOLUTE_PREFIX) |
11416 | { | |
11417 | ++op_string; | |
11418 | if (is_space_char (*op_string)) | |
11419 | ++op_string; | |
5b7c81bd | 11420 | i.jumpabsolute = true; |
24eab124 | 11421 | } |
252b5132 | 11422 | |
47926f60 | 11423 | /* Check if operand is a register. */ |
4d1bb795 | 11424 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 11425 | { |
40fb9820 L |
11426 | i386_operand_type temp; |
11427 | ||
8a6fb3f9 JB |
11428 | if (r == &bad_reg) |
11429 | return 0; | |
11430 | ||
24eab124 AM |
11431 | /* Check for a segment override by searching for ':' after a |
11432 | segment register. */ | |
11433 | op_string = end_op; | |
11434 | if (is_space_char (*op_string)) | |
11435 | ++op_string; | |
00cee14f | 11436 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 11437 | { |
5e042380 | 11438 | i.seg[i.mem_operands] = r; |
252b5132 | 11439 | |
24eab124 | 11440 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
11441 | ++op_string; |
11442 | if (is_space_char (*op_string)) | |
24eab124 | 11443 | ++op_string; |
252b5132 | 11444 | |
47926f60 | 11445 | /* Handle case of %es:*foo. */ |
c8d541e2 | 11446 | if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX) |
24eab124 AM |
11447 | { |
11448 | ++op_string; | |
11449 | if (is_space_char (*op_string)) | |
11450 | ++op_string; | |
5b7c81bd | 11451 | i.jumpabsolute = true; |
24eab124 | 11452 | } |
c8d541e2 | 11453 | |
9d299bea | 11454 | if (!starts_memory_operand (*op_string)) |
c8d541e2 JB |
11455 | { |
11456 | as_bad (_("bad memory operand `%s'"), op_string); | |
11457 | return 0; | |
11458 | } | |
24eab124 AM |
11459 | goto do_memory_reference; |
11460 | } | |
43234a1e L |
11461 | |
11462 | /* Handle vector operations. */ | |
11463 | if (*op_string == '{') | |
11464 | { | |
f70c6814 | 11465 | op_string = check_VecOperations (op_string); |
43234a1e L |
11466 | if (op_string == NULL) |
11467 | return 0; | |
11468 | } | |
11469 | ||
24eab124 AM |
11470 | if (*op_string) |
11471 | { | |
d0b47220 | 11472 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
11473 | return 0; |
11474 | } | |
40fb9820 L |
11475 | temp = r->reg_type; |
11476 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
11477 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
11478 | temp); | |
7d5e4556 | 11479 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 11480 | i.op[this_operand].regs = r; |
24eab124 | 11481 | i.reg_operands++; |
cf665fee JB |
11482 | |
11483 | /* A GPR may follow an RC or SAE immediate only if a (vector) register | |
11484 | operand was also present earlier on. */ | |
11485 | if (i.rounding.type != rc_none && temp.bitfield.class == Reg | |
11486 | && i.reg_operands == 1) | |
11487 | { | |
11488 | unsigned int j; | |
11489 | ||
11490 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j) | |
11491 | if (i.rounding.type == RC_NamesTable[j].type) | |
11492 | break; | |
11493 | as_bad (_("`%s': misplaced `{%s}'"), | |
11494 | current_templates->start->name, RC_NamesTable[j].name); | |
11495 | return 0; | |
11496 | } | |
24eab124 | 11497 | } |
af6bdddf AM |
11498 | else if (*op_string == REGISTER_PREFIX) |
11499 | { | |
11500 | as_bad (_("bad register name `%s'"), op_string); | |
11501 | return 0; | |
11502 | } | |
24eab124 | 11503 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 11504 | { |
24eab124 | 11505 | ++op_string; |
6f2f06be | 11506 | if (i.jumpabsolute) |
24eab124 | 11507 | { |
d0b47220 | 11508 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
11509 | return 0; |
11510 | } | |
11511 | if (!i386_immediate (op_string)) | |
11512 | return 0; | |
cf665fee JB |
11513 | if (i.rounding.type != rc_none) |
11514 | { | |
11515 | as_bad (_("`%s': RC/SAE operand must follow immediate operands"), | |
11516 | current_templates->start->name); | |
11517 | return 0; | |
11518 | } | |
24eab124 | 11519 | } |
43234a1e L |
11520 | else if (RC_SAE_immediate (operand_string)) |
11521 | { | |
cf665fee JB |
11522 | /* If it is a RC or SAE immediate, do the necessary placement check: |
11523 | Only another immediate or a GPR may precede it. */ | |
11524 | if (i.mem_operands || i.reg_operands + i.imm_operands > 1 | |
11525 | || (i.reg_operands == 1 | |
11526 | && i.op[0].regs->reg_type.bitfield.class != Reg)) | |
11527 | { | |
11528 | as_bad (_("`%s': misplaced `%s'"), | |
11529 | current_templates->start->name, operand_string); | |
11530 | return 0; | |
11531 | } | |
43234a1e | 11532 | } |
9d299bea | 11533 | else if (starts_memory_operand (*op_string)) |
24eab124 | 11534 | { |
47926f60 | 11535 | /* This is a memory reference of some sort. */ |
af6bdddf | 11536 | char *base_string; |
252b5132 | 11537 | |
47926f60 | 11538 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
11539 | char *displacement_string_start; |
11540 | char *displacement_string_end; | |
252b5132 | 11541 | |
24eab124 | 11542 | do_memory_reference: |
8325cc63 JB |
11543 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
11544 | return 0; | |
24eab124 | 11545 | if ((i.mem_operands == 1 |
40fb9820 | 11546 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
11547 | || i.mem_operands == 2) |
11548 | { | |
11549 | as_bad (_("too many memory references for `%s'"), | |
11550 | current_templates->start->name); | |
11551 | return 0; | |
11552 | } | |
252b5132 | 11553 | |
24eab124 AM |
11554 | /* Check for base index form. We detect the base index form by |
11555 | looking for an ')' at the end of the operand, searching | |
11556 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
11557 | after the '('. */ | |
af6bdddf | 11558 | base_string = op_string + strlen (op_string); |
c3332e24 | 11559 | |
43234a1e | 11560 | /* Handle vector operations. */ |
6b5ba0d4 JB |
11561 | --base_string; |
11562 | if (is_space_char (*base_string)) | |
11563 | --base_string; | |
11564 | ||
11565 | if (*base_string == '}') | |
43234a1e | 11566 | { |
6b5ba0d4 JB |
11567 | char *vop_start = NULL; |
11568 | ||
11569 | while (base_string-- > op_string) | |
11570 | { | |
11571 | if (*base_string == '"') | |
11572 | break; | |
11573 | if (*base_string != '{') | |
11574 | continue; | |
11575 | ||
11576 | vop_start = base_string; | |
11577 | ||
11578 | --base_string; | |
11579 | if (is_space_char (*base_string)) | |
11580 | --base_string; | |
11581 | ||
11582 | if (*base_string != '}') | |
11583 | break; | |
11584 | ||
11585 | vop_start = NULL; | |
11586 | } | |
11587 | ||
11588 | if (!vop_start) | |
11589 | { | |
11590 | as_bad (_("unbalanced figure braces")); | |
11591 | return 0; | |
11592 | } | |
11593 | ||
f70c6814 | 11594 | if (check_VecOperations (vop_start) == NULL) |
43234a1e | 11595 | return 0; |
43234a1e L |
11596 | } |
11597 | ||
47926f60 | 11598 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
11599 | displacement_string_start = op_string; |
11600 | displacement_string_end = base_string + 1; | |
252b5132 | 11601 | |
24eab124 AM |
11602 | if (*base_string == ')') |
11603 | { | |
af6bdddf | 11604 | char *temp_string; |
e87fb6a6 JB |
11605 | unsigned int parens_not_balanced = 0; |
11606 | bool in_quotes = false; | |
e68c3d59 | 11607 | |
24eab124 | 11608 | /* We've already checked that the number of left & right ()'s are |
e87fb6a6 JB |
11609 | equal, and that there's a matching set of double quotes. */ |
11610 | end_op = base_string; | |
11611 | for (temp_string = op_string; temp_string < end_op; temp_string++) | |
24eab124 | 11612 | { |
e87fb6a6 JB |
11613 | if (*temp_string == '\\' && temp_string[1] == '"') |
11614 | ++temp_string; | |
11615 | else if (*temp_string == '"') | |
11616 | in_quotes = !in_quotes; | |
11617 | else if (!in_quotes) | |
11618 | { | |
11619 | if (*temp_string == '(' && !parens_not_balanced++) | |
11620 | base_string = temp_string; | |
11621 | if (*temp_string == ')') | |
11622 | --parens_not_balanced; | |
11623 | } | |
24eab124 | 11624 | } |
c3332e24 | 11625 | |
af6bdddf | 11626 | temp_string = base_string; |
c3332e24 | 11627 | |
24eab124 | 11628 | /* Skip past '(' and whitespace. */ |
e87fb6a6 JB |
11629 | gas_assert (*base_string == '('); |
11630 | ++base_string; | |
252b5132 | 11631 | if (is_space_char (*base_string)) |
24eab124 | 11632 | ++base_string; |
252b5132 | 11633 | |
af6bdddf | 11634 | if (*base_string == ',' |
4eed87de AM |
11635 | || ((i.base_reg = parse_register (base_string, &end_op)) |
11636 | != NULL)) | |
252b5132 | 11637 | { |
af6bdddf | 11638 | displacement_string_end = temp_string; |
252b5132 | 11639 | |
40fb9820 | 11640 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 11641 | |
af6bdddf | 11642 | if (i.base_reg) |
24eab124 | 11643 | { |
8a6fb3f9 JB |
11644 | if (i.base_reg == &bad_reg) |
11645 | return 0; | |
24eab124 AM |
11646 | base_string = end_op; |
11647 | if (is_space_char (*base_string)) | |
11648 | ++base_string; | |
af6bdddf AM |
11649 | } |
11650 | ||
11651 | /* There may be an index reg or scale factor here. */ | |
11652 | if (*base_string == ',') | |
11653 | { | |
11654 | ++base_string; | |
11655 | if (is_space_char (*base_string)) | |
11656 | ++base_string; | |
11657 | ||
4eed87de AM |
11658 | if ((i.index_reg = parse_register (base_string, &end_op)) |
11659 | != NULL) | |
24eab124 | 11660 | { |
8a6fb3f9 JB |
11661 | if (i.index_reg == &bad_reg) |
11662 | return 0; | |
af6bdddf | 11663 | base_string = end_op; |
24eab124 AM |
11664 | if (is_space_char (*base_string)) |
11665 | ++base_string; | |
af6bdddf AM |
11666 | if (*base_string == ',') |
11667 | { | |
11668 | ++base_string; | |
11669 | if (is_space_char (*base_string)) | |
11670 | ++base_string; | |
11671 | } | |
e5cb08ac | 11672 | else if (*base_string != ')') |
af6bdddf | 11673 | { |
4eed87de AM |
11674 | as_bad (_("expecting `,' or `)' " |
11675 | "after index register in `%s'"), | |
af6bdddf AM |
11676 | operand_string); |
11677 | return 0; | |
11678 | } | |
24eab124 | 11679 | } |
af6bdddf | 11680 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 11681 | { |
f76bf5e0 L |
11682 | end_op = strchr (base_string, ','); |
11683 | if (end_op) | |
11684 | *end_op = '\0'; | |
af6bdddf | 11685 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
11686 | return 0; |
11687 | } | |
252b5132 | 11688 | |
47926f60 | 11689 | /* Check for scale factor. */ |
551c1ca1 | 11690 | if (*base_string != ')') |
af6bdddf | 11691 | { |
551c1ca1 AM |
11692 | char *end_scale = i386_scale (base_string); |
11693 | ||
11694 | if (!end_scale) | |
af6bdddf | 11695 | return 0; |
24eab124 | 11696 | |
551c1ca1 | 11697 | base_string = end_scale; |
af6bdddf AM |
11698 | if (is_space_char (*base_string)) |
11699 | ++base_string; | |
11700 | if (*base_string != ')') | |
11701 | { | |
4eed87de AM |
11702 | as_bad (_("expecting `)' " |
11703 | "after scale factor in `%s'"), | |
af6bdddf AM |
11704 | operand_string); |
11705 | return 0; | |
11706 | } | |
11707 | } | |
11708 | else if (!i.index_reg) | |
24eab124 | 11709 | { |
4eed87de AM |
11710 | as_bad (_("expecting index register or scale factor " |
11711 | "after `,'; got '%c'"), | |
af6bdddf | 11712 | *base_string); |
24eab124 AM |
11713 | return 0; |
11714 | } | |
11715 | } | |
af6bdddf | 11716 | else if (*base_string != ')') |
24eab124 | 11717 | { |
4eed87de AM |
11718 | as_bad (_("expecting `,' or `)' " |
11719 | "after base register in `%s'"), | |
af6bdddf | 11720 | operand_string); |
24eab124 AM |
11721 | return 0; |
11722 | } | |
c3332e24 | 11723 | } |
af6bdddf | 11724 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 11725 | { |
f76bf5e0 L |
11726 | end_op = strchr (base_string, ','); |
11727 | if (end_op) | |
11728 | *end_op = '\0'; | |
af6bdddf | 11729 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 11730 | return 0; |
c3332e24 | 11731 | } |
24eab124 AM |
11732 | } |
11733 | ||
11734 | /* If there's an expression beginning the operand, parse it, | |
11735 | assuming displacement_string_start and | |
11736 | displacement_string_end are meaningful. */ | |
11737 | if (displacement_string_start != displacement_string_end) | |
11738 | { | |
11739 | if (!i386_displacement (displacement_string_start, | |
11740 | displacement_string_end)) | |
11741 | return 0; | |
11742 | } | |
11743 | ||
11744 | /* Special case for (%dx) while doing input/output op. */ | |
11745 | if (i.base_reg | |
75e5731b JB |
11746 | && i.base_reg->reg_type.bitfield.instance == RegD |
11747 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
11748 | && i.index_reg == 0 |
11749 | && i.log2_scale_factor == 0 | |
11750 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 11751 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 11752 | { |
2fb5be8d | 11753 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
11754 | return 1; |
11755 | } | |
11756 | ||
eecb386c AM |
11757 | if (i386_index_check (operand_string) == 0) |
11758 | return 0; | |
c48dadc9 | 11759 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
11760 | if (i.mem_operands == 0) |
11761 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
11762 | i.mem_operands++; |
11763 | } | |
11764 | else | |
ce8a8b2f AM |
11765 | { |
11766 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
11767 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
11768 | output_invalid (*op_string), | |
11769 | this_operand + 1, | |
11770 | op_string); | |
11771 | return 0; | |
11772 | } | |
47926f60 | 11773 | return 1; /* Normal return. */ |
252b5132 RH |
11774 | } |
11775 | \f | |
fa94de6b RM |
11776 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
11777 | that an rs_machine_dependent frag may reach. */ | |
11778 | ||
11779 | unsigned int | |
11780 | i386_frag_max_var (fragS *frag) | |
11781 | { | |
11782 | /* The only relaxable frags are for jumps. | |
11783 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
11784 | gas_assert (frag->fr_type == rs_machine_dependent); | |
11785 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
11786 | } | |
11787 | ||
b084df0b L |
11788 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11789 | static int | |
8dcea932 | 11790 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
11791 | { |
11792 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
11793 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
11794 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
11795 | return 0; | |
11796 | ||
11797 | if (!S_IS_EXTERNAL (fr_symbol)) | |
11798 | /* Symbol may be weak or local. */ | |
11799 | return !S_IS_WEAK (fr_symbol); | |
11800 | ||
8dcea932 L |
11801 | /* Global symbols with non-default visibility can't be preempted. */ |
11802 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
11803 | return 1; | |
11804 | ||
11805 | if (fr_var != NO_RELOC) | |
11806 | switch ((enum bfd_reloc_code_real) fr_var) | |
11807 | { | |
11808 | case BFD_RELOC_386_PLT32: | |
11809 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11810 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11811 | return 0; |
11812 | default: | |
11813 | abort (); | |
11814 | } | |
11815 | ||
b084df0b L |
11816 | /* Global symbols with default visibility in a shared library may be |
11817 | preempted by another definition. */ | |
8dcea932 | 11818 | return !shared; |
b084df0b L |
11819 | } |
11820 | #endif | |
11821 | ||
79d72f45 HL |
11822 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11823 | Note also work for Skylake and Cascadelake. | |
11824 | --------------------------------------------------------------------- | |
11825 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11826 | | ------ | ----------- | ------- | -------- | | |
11827 | | Jo | N | N | Y | | |
11828 | | Jno | N | N | Y | | |
11829 | | Jc/Jb | Y | N | Y | | |
11830 | | Jae/Jnb | Y | N | Y | | |
11831 | | Je/Jz | Y | Y | Y | | |
11832 | | Jne/Jnz | Y | Y | Y | | |
11833 | | Jna/Jbe | Y | N | Y | | |
11834 | | Ja/Jnbe | Y | N | Y | | |
11835 | | Js | N | N | Y | | |
11836 | | Jns | N | N | Y | | |
11837 | | Jp/Jpe | N | N | Y | | |
11838 | | Jnp/Jpo | N | N | Y | | |
11839 | | Jl/Jnge | Y | Y | Y | | |
11840 | | Jge/Jnl | Y | Y | Y | | |
11841 | | Jle/Jng | Y | Y | Y | | |
11842 | | Jg/Jnle | Y | Y | Y | | |
11843 | --------------------------------------------------------------------- */ | |
11844 | static int | |
11845 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11846 | { | |
11847 | if (mf_cmp == mf_cmp_alu_cmp) | |
11848 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11849 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11850 | if (mf_cmp == mf_cmp_incdec) | |
11851 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11852 | || mf_jcc == mf_jcc_jle); | |
11853 | if (mf_cmp == mf_cmp_test_and) | |
11854 | return 1; | |
11855 | return 0; | |
11856 | } | |
11857 | ||
e379e5f3 L |
11858 | /* Return the next non-empty frag. */ |
11859 | ||
11860 | static fragS * | |
11861 | i386_next_non_empty_frag (fragS *fragP) | |
11862 | { | |
11863 | /* There may be a frag with a ".fill 0" when there is no room in | |
11864 | the current frag for frag_grow in output_insn. */ | |
11865 | for (fragP = fragP->fr_next; | |
11866 | (fragP != NULL | |
11867 | && fragP->fr_type == rs_fill | |
11868 | && fragP->fr_fix == 0); | |
11869 | fragP = fragP->fr_next) | |
11870 | ; | |
11871 | return fragP; | |
11872 | } | |
11873 | ||
11874 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11875 | ||
11876 | static fragS * | |
79d72f45 | 11877 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11878 | { |
79d72f45 HL |
11879 | fragS *branch_fragP; |
11880 | if (!pad_fragP) | |
e379e5f3 L |
11881 | return NULL; |
11882 | ||
79d72f45 HL |
11883 | if (pad_fragP->fr_type == rs_machine_dependent |
11884 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11885 | == BRANCH_PADDING)) |
11886 | { | |
79d72f45 HL |
11887 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11888 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11889 | return NULL; |
79d72f45 HL |
11890 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11891 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11892 | pad_fragP->tc_frag_data.mf_type)) | |
11893 | return branch_fragP; | |
e379e5f3 L |
11894 | } |
11895 | ||
11896 | return NULL; | |
11897 | } | |
11898 | ||
11899 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11900 | ||
11901 | static void | |
11902 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11903 | { | |
11904 | fragS *cmp_fragP; | |
11905 | fragS *pad_fragP; | |
11906 | fragS *branch_fragP; | |
11907 | fragS *next_fragP; | |
11908 | unsigned int max_prefix_length; | |
11909 | ||
11910 | if (fragP->tc_frag_data.classified) | |
11911 | return; | |
11912 | ||
11913 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11914 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11915 | for (next_fragP = fragP; | |
11916 | next_fragP != NULL; | |
11917 | next_fragP = next_fragP->fr_next) | |
11918 | { | |
11919 | next_fragP->tc_frag_data.classified = 1; | |
11920 | if (next_fragP->fr_type == rs_machine_dependent) | |
11921 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11922 | { | |
11923 | case BRANCH_PADDING: | |
11924 | /* The BRANCH_PADDING frag must be followed by a branch | |
11925 | frag. */ | |
11926 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11927 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11928 | break; | |
11929 | case FUSED_JCC_PADDING: | |
11930 | /* Check if this is a fused jcc: | |
11931 | FUSED_JCC_PADDING | |
11932 | CMP like instruction | |
11933 | BRANCH_PADDING | |
11934 | COND_JUMP | |
11935 | */ | |
11936 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11937 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11938 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11939 | if (branch_fragP) |
11940 | { | |
11941 | /* The BRANCH_PADDING frag is merged with the | |
11942 | FUSED_JCC_PADDING frag. */ | |
11943 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11944 | /* CMP like instruction size. */ | |
11945 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11946 | frag_wane (pad_fragP); | |
11947 | /* Skip to branch_fragP. */ | |
11948 | next_fragP = branch_fragP; | |
11949 | } | |
11950 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11951 | { | |
11952 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11953 | a fused jcc. */ | |
11954 | next_fragP->fr_subtype | |
11955 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11956 | next_fragP->tc_frag_data.max_bytes | |
11957 | = next_fragP->tc_frag_data.max_prefix_length; | |
11958 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11959 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11960 | } | |
11961 | else | |
11962 | frag_wane (next_fragP); | |
11963 | break; | |
11964 | } | |
11965 | } | |
11966 | ||
11967 | /* Stop if there is no BRANCH_PREFIX. */ | |
11968 | if (!align_branch_prefix_size) | |
11969 | return; | |
11970 | ||
11971 | /* Scan for BRANCH_PREFIX. */ | |
11972 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11973 | { | |
11974 | if (fragP->fr_type != rs_machine_dependent | |
11975 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11976 | != BRANCH_PREFIX)) | |
11977 | continue; | |
11978 | ||
11979 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11980 | COND_JUMP_PREFIX. */ | |
11981 | max_prefix_length = 0; | |
11982 | for (next_fragP = fragP; | |
11983 | next_fragP != NULL; | |
11984 | next_fragP = next_fragP->fr_next) | |
11985 | { | |
11986 | if (next_fragP->fr_type == rs_fill) | |
11987 | /* Skip rs_fill frags. */ | |
11988 | continue; | |
11989 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11990 | /* Stop for all other frags. */ | |
11991 | break; | |
11992 | ||
11993 | /* rs_machine_dependent frags. */ | |
11994 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11995 | == BRANCH_PREFIX) | |
11996 | { | |
11997 | /* Count BRANCH_PREFIX frags. */ | |
11998 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11999 | { | |
12000 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
12001 | frag_wane (next_fragP); | |
12002 | } | |
12003 | else | |
12004 | max_prefix_length | |
12005 | += next_fragP->tc_frag_data.max_bytes; | |
12006 | } | |
12007 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12008 | == BRANCH_PADDING) | |
12009 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12010 | == FUSED_JCC_PADDING)) | |
12011 | { | |
12012 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
12013 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
12014 | break; | |
12015 | } | |
12016 | else | |
12017 | /* Stop for other rs_machine_dependent frags. */ | |
12018 | break; | |
12019 | } | |
12020 | ||
12021 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
12022 | ||
12023 | /* Skip to the next frag. */ | |
12024 | fragP = next_fragP; | |
12025 | } | |
12026 | } | |
12027 | ||
12028 | /* Compute padding size for | |
12029 | ||
12030 | FUSED_JCC_PADDING | |
12031 | CMP like instruction | |
12032 | BRANCH_PADDING | |
12033 | COND_JUMP/UNCOND_JUMP | |
12034 | ||
12035 | or | |
12036 | ||
12037 | BRANCH_PADDING | |
12038 | COND_JUMP/UNCOND_JUMP | |
12039 | */ | |
12040 | ||
12041 | static int | |
12042 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
12043 | { | |
12044 | unsigned int offset, size, padding_size; | |
12045 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
12046 | ||
12047 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
12048 | if (!address) | |
12049 | address = fragP->fr_address; | |
12050 | address += fragP->fr_fix; | |
12051 | ||
12052 | /* CMP like instrunction size. */ | |
12053 | size = fragP->tc_frag_data.cmp_size; | |
12054 | ||
12055 | /* The base size of the branch frag. */ | |
12056 | size += branch_fragP->fr_fix; | |
12057 | ||
12058 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
12059 | branch frag. */ | |
12060 | if (branch_fragP->fr_type == rs_machine_dependent) | |
12061 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
12062 | ||
12063 | /* Check if branch is within boundary and doesn't end at the last | |
12064 | byte. */ | |
12065 | offset = address & ((1U << align_branch_power) - 1); | |
12066 | if ((offset + size) >= (1U << align_branch_power)) | |
12067 | /* Padding needed to avoid crossing boundary. */ | |
12068 | padding_size = (1U << align_branch_power) - offset; | |
12069 | else | |
12070 | /* No padding needed. */ | |
12071 | padding_size = 0; | |
12072 | ||
12073 | /* The return value may be saved in tc_frag_data.length which is | |
12074 | unsigned byte. */ | |
12075 | if (!fits_in_unsigned_byte (padding_size)) | |
12076 | abort (); | |
12077 | ||
12078 | return padding_size; | |
12079 | } | |
12080 | ||
12081 | /* i386_generic_table_relax_frag() | |
12082 | ||
12083 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
12084 | grow/shrink padding to align branch frags. Hand others to | |
12085 | relax_frag(). */ | |
12086 | ||
12087 | long | |
12088 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
12089 | { | |
12090 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
12091 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12092 | { | |
12093 | long padding_size = i386_branch_padding_size (fragP, 0); | |
12094 | long grow = padding_size - fragP->tc_frag_data.length; | |
12095 | ||
12096 | /* When the BRANCH_PREFIX frag is used, the computed address | |
12097 | must match the actual address and there should be no padding. */ | |
12098 | if (fragP->tc_frag_data.padding_address | |
12099 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
12100 | || padding_size)) | |
12101 | abort (); | |
12102 | ||
12103 | /* Update the padding size. */ | |
12104 | if (grow) | |
12105 | fragP->tc_frag_data.length = padding_size; | |
12106 | ||
12107 | return grow; | |
12108 | } | |
12109 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12110 | { | |
12111 | fragS *padding_fragP, *next_fragP; | |
12112 | long padding_size, left_size, last_size; | |
12113 | ||
12114 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12115 | if (!padding_fragP) | |
12116 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
12117 | return (fragP->tc_frag_data.length | |
12118 | - fragP->tc_frag_data.last_length); | |
12119 | ||
12120 | /* Compute the relative address of the padding frag in the very | |
12121 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
12122 | if (!fragP->tc_frag_data.padding_address) | |
12123 | fragP->tc_frag_data.padding_address | |
12124 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
12125 | ||
12126 | /* First update the last length from the previous interation. */ | |
12127 | left_size = fragP->tc_frag_data.prefix_length; | |
12128 | for (next_fragP = fragP; | |
12129 | next_fragP != padding_fragP; | |
12130 | next_fragP = next_fragP->fr_next) | |
12131 | if (next_fragP->fr_type == rs_machine_dependent | |
12132 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12133 | == BRANCH_PREFIX)) | |
12134 | { | |
12135 | if (left_size) | |
12136 | { | |
12137 | int max = next_fragP->tc_frag_data.max_bytes; | |
12138 | if (max) | |
12139 | { | |
12140 | int size; | |
12141 | if (max > left_size) | |
12142 | size = left_size; | |
12143 | else | |
12144 | size = max; | |
12145 | left_size -= size; | |
12146 | next_fragP->tc_frag_data.last_length = size; | |
12147 | } | |
12148 | } | |
12149 | else | |
12150 | next_fragP->tc_frag_data.last_length = 0; | |
12151 | } | |
12152 | ||
12153 | /* Check the padding size for the padding frag. */ | |
12154 | padding_size = i386_branch_padding_size | |
12155 | (padding_fragP, (fragP->fr_address | |
12156 | + fragP->tc_frag_data.padding_address)); | |
12157 | ||
12158 | last_size = fragP->tc_frag_data.prefix_length; | |
12159 | /* Check if there is change from the last interation. */ | |
12160 | if (padding_size == last_size) | |
12161 | { | |
12162 | /* Update the expected address of the padding frag. */ | |
12163 | padding_fragP->tc_frag_data.padding_address | |
12164 | = (fragP->fr_address + padding_size | |
12165 | + fragP->tc_frag_data.padding_address); | |
12166 | return 0; | |
12167 | } | |
12168 | ||
12169 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
12170 | { | |
12171 | /* No padding if there is no sufficient room. Clear the | |
12172 | expected address of the padding frag. */ | |
12173 | padding_fragP->tc_frag_data.padding_address = 0; | |
12174 | padding_size = 0; | |
12175 | } | |
12176 | else | |
12177 | /* Store the expected address of the padding frag. */ | |
12178 | padding_fragP->tc_frag_data.padding_address | |
12179 | = (fragP->fr_address + padding_size | |
12180 | + fragP->tc_frag_data.padding_address); | |
12181 | ||
12182 | fragP->tc_frag_data.prefix_length = padding_size; | |
12183 | ||
12184 | /* Update the length for the current interation. */ | |
12185 | left_size = padding_size; | |
12186 | for (next_fragP = fragP; | |
12187 | next_fragP != padding_fragP; | |
12188 | next_fragP = next_fragP->fr_next) | |
12189 | if (next_fragP->fr_type == rs_machine_dependent | |
12190 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12191 | == BRANCH_PREFIX)) | |
12192 | { | |
12193 | if (left_size) | |
12194 | { | |
12195 | int max = next_fragP->tc_frag_data.max_bytes; | |
12196 | if (max) | |
12197 | { | |
12198 | int size; | |
12199 | if (max > left_size) | |
12200 | size = left_size; | |
12201 | else | |
12202 | size = max; | |
12203 | left_size -= size; | |
12204 | next_fragP->tc_frag_data.length = size; | |
12205 | } | |
12206 | } | |
12207 | else | |
12208 | next_fragP->tc_frag_data.length = 0; | |
12209 | } | |
12210 | ||
12211 | return (fragP->tc_frag_data.length | |
12212 | - fragP->tc_frag_data.last_length); | |
12213 | } | |
12214 | return relax_frag (segment, fragP, stretch); | |
12215 | } | |
12216 | ||
ee7fcc42 AM |
12217 | /* md_estimate_size_before_relax() |
12218 | ||
12219 | Called just before relax() for rs_machine_dependent frags. The x86 | |
12220 | assembler uses these frags to handle variable size jump | |
12221 | instructions. | |
12222 | ||
12223 | Any symbol that is now undefined will not become defined. | |
12224 | Return the correct fr_subtype in the frag. | |
12225 | Return the initial "guess for variable size of frag" to caller. | |
12226 | The guess is actually the growth beyond the fixed part. Whatever | |
12227 | we do to grow the fixed or variable part contributes to our | |
12228 | returned value. */ | |
12229 | ||
252b5132 | 12230 | int |
7016a5d5 | 12231 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 12232 | { |
e379e5f3 L |
12233 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12234 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
12235 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12236 | { | |
12237 | i386_classify_machine_dependent_frag (fragP); | |
12238 | return fragP->tc_frag_data.length; | |
12239 | } | |
12240 | ||
252b5132 | 12241 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
12242 | check for un-relaxable symbols. On an ELF system, we can't relax |
12243 | an externally visible symbol, because it may be overridden by a | |
12244 | shared library. */ | |
12245 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 12246 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12247 | || (IS_ELF |
8dcea932 L |
12248 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
12249 | fragP->fr_var)) | |
fbeb56a4 DK |
12250 | #endif |
12251 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 12252 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 12253 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
12254 | #endif |
12255 | ) | |
252b5132 | 12256 | { |
b98ef147 AM |
12257 | /* Symbol is undefined in this segment, or we need to keep a |
12258 | reloc so that weak symbols can be overridden. */ | |
12259 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 12260 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
12261 | unsigned char *opcode; |
12262 | int old_fr_fix; | |
eb19308f | 12263 | fixS *fixP = NULL; |
f6af82bd | 12264 | |
ee7fcc42 | 12265 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 12266 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 12267 | else if (size == 2) |
f6af82bd | 12268 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b | 12269 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
12270 | else if (fragP->tc_frag_data.code64 && fragP->fr_offset == 0 |
12271 | && need_plt32_p (fragP->fr_symbol)) | |
bd7ab16b L |
12272 | reloc_type = BFD_RELOC_X86_64_PLT32; |
12273 | #endif | |
f6af82bd AM |
12274 | else |
12275 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 12276 | |
ee7fcc42 AM |
12277 | old_fr_fix = fragP->fr_fix; |
12278 | opcode = (unsigned char *) fragP->fr_opcode; | |
12279 | ||
fddf5b5b | 12280 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 12281 | { |
fddf5b5b AM |
12282 | case UNCOND_JUMP: |
12283 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 12284 | opcode[0] = 0xe9; |
252b5132 | 12285 | fragP->fr_fix += size; |
eb19308f JB |
12286 | fixP = fix_new (fragP, old_fr_fix, size, |
12287 | fragP->fr_symbol, | |
12288 | fragP->fr_offset, 1, | |
12289 | reloc_type); | |
252b5132 RH |
12290 | break; |
12291 | ||
fddf5b5b | 12292 | case COND_JUMP86: |
412167cb AM |
12293 | if (size == 2 |
12294 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
12295 | { |
12296 | /* Negate the condition, and branch past an | |
12297 | unconditional jump. */ | |
12298 | opcode[0] ^= 1; | |
12299 | opcode[1] = 3; | |
12300 | /* Insert an unconditional jump. */ | |
12301 | opcode[2] = 0xe9; | |
12302 | /* We added two extra opcode bytes, and have a two byte | |
12303 | offset. */ | |
12304 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
12305 | fix_new (fragP, old_fr_fix + 2, 2, |
12306 | fragP->fr_symbol, | |
12307 | fragP->fr_offset, 1, | |
12308 | reloc_type); | |
fddf5b5b AM |
12309 | break; |
12310 | } | |
12311 | /* Fall through. */ | |
12312 | ||
12313 | case COND_JUMP: | |
412167cb AM |
12314 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
12315 | { | |
12316 | fragP->fr_fix += 1; | |
3e02c1cc AM |
12317 | fixP = fix_new (fragP, old_fr_fix, 1, |
12318 | fragP->fr_symbol, | |
12319 | fragP->fr_offset, 1, | |
12320 | BFD_RELOC_8_PCREL); | |
12321 | fixP->fx_signed = 1; | |
412167cb AM |
12322 | break; |
12323 | } | |
93c2a809 | 12324 | |
24eab124 | 12325 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 12326 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 12327 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 12328 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
12329 | /* We've added an opcode byte. */ |
12330 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
12331 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
12332 | fragP->fr_symbol, | |
12333 | fragP->fr_offset, 1, | |
12334 | reloc_type); | |
252b5132 | 12335 | break; |
fddf5b5b AM |
12336 | |
12337 | default: | |
12338 | BAD_CASE (fragP->fr_subtype); | |
12339 | break; | |
252b5132 | 12340 | } |
eb19308f JB |
12341 | |
12342 | /* All jumps handled here are signed, but don't unconditionally use a | |
12343 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
12344 | around at 4G (outside of 64-bit mode) and 64k. */ | |
12345 | if (size == 4 && flag_code == CODE_64BIT) | |
12346 | fixP->fx_signed = 1; | |
12347 | ||
252b5132 | 12348 | frag_wane (fragP); |
ee7fcc42 | 12349 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 12350 | } |
93c2a809 | 12351 | |
93c2a809 AM |
12352 | /* Guess size depending on current relax state. Initially the relax |
12353 | state will correspond to a short jump and we return 1, because | |
12354 | the variable part of the frag (the branch offset) is one byte | |
12355 | long. However, we can relax a section more than once and in that | |
12356 | case we must either set fr_subtype back to the unrelaxed state, | |
12357 | or return the value for the appropriate branch. */ | |
12358 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
12359 | } |
12360 | ||
47926f60 KH |
12361 | /* Called after relax() is finished. |
12362 | ||
12363 | In: Address of frag. | |
12364 | fr_type == rs_machine_dependent. | |
12365 | fr_subtype is what the address relaxed to. | |
12366 | ||
12367 | Out: Any fixSs and constants are set up. | |
12368 | Caller will turn frag into a ".space 0". */ | |
12369 | ||
252b5132 | 12370 | void |
7016a5d5 TG |
12371 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
12372 | fragS *fragP) | |
252b5132 | 12373 | { |
29b0f896 | 12374 | unsigned char *opcode; |
252b5132 | 12375 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
12376 | offsetT target_address; |
12377 | offsetT opcode_address; | |
252b5132 | 12378 | unsigned int extension = 0; |
847f7ad4 | 12379 | offsetT displacement_from_opcode_start; |
252b5132 | 12380 | |
e379e5f3 L |
12381 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12382 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
12383 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12384 | { | |
12385 | /* Generate nop padding. */ | |
12386 | unsigned int size = fragP->tc_frag_data.length; | |
12387 | if (size) | |
12388 | { | |
12389 | if (size > fragP->tc_frag_data.max_bytes) | |
12390 | abort (); | |
12391 | ||
12392 | if (flag_debug) | |
12393 | { | |
12394 | const char *msg; | |
12395 | const char *branch = "branch"; | |
12396 | const char *prefix = ""; | |
12397 | fragS *padding_fragP; | |
12398 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
12399 | == BRANCH_PREFIX) | |
12400 | { | |
12401 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12402 | switch (fragP->tc_frag_data.default_prefix) | |
12403 | { | |
12404 | default: | |
12405 | abort (); | |
12406 | break; | |
12407 | case CS_PREFIX_OPCODE: | |
12408 | prefix = " cs"; | |
12409 | break; | |
12410 | case DS_PREFIX_OPCODE: | |
12411 | prefix = " ds"; | |
12412 | break; | |
12413 | case ES_PREFIX_OPCODE: | |
12414 | prefix = " es"; | |
12415 | break; | |
12416 | case FS_PREFIX_OPCODE: | |
12417 | prefix = " fs"; | |
12418 | break; | |
12419 | case GS_PREFIX_OPCODE: | |
12420 | prefix = " gs"; | |
12421 | break; | |
12422 | case SS_PREFIX_OPCODE: | |
12423 | prefix = " ss"; | |
12424 | break; | |
12425 | } | |
12426 | if (padding_fragP) | |
12427 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
12428 | "%s within %d-byte boundary\n"); | |
12429 | else | |
12430 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
12431 | "align %s within %d-byte boundary\n"); | |
12432 | } | |
12433 | else | |
12434 | { | |
12435 | padding_fragP = fragP; | |
12436 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
12437 | "%s within %d-byte boundary\n"); | |
12438 | } | |
12439 | ||
12440 | if (padding_fragP) | |
12441 | switch (padding_fragP->tc_frag_data.branch_type) | |
12442 | { | |
12443 | case align_branch_jcc: | |
12444 | branch = "jcc"; | |
12445 | break; | |
12446 | case align_branch_fused: | |
12447 | branch = "fused jcc"; | |
12448 | break; | |
12449 | case align_branch_jmp: | |
12450 | branch = "jmp"; | |
12451 | break; | |
12452 | case align_branch_call: | |
12453 | branch = "call"; | |
12454 | break; | |
12455 | case align_branch_indirect: | |
12456 | branch = "indiret branch"; | |
12457 | break; | |
12458 | case align_branch_ret: | |
12459 | branch = "ret"; | |
12460 | break; | |
12461 | default: | |
12462 | break; | |
12463 | } | |
12464 | ||
12465 | fprintf (stdout, msg, | |
12466 | fragP->fr_file, fragP->fr_line, size, prefix, | |
12467 | (long long) fragP->fr_address, branch, | |
12468 | 1 << align_branch_power); | |
12469 | } | |
12470 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12471 | memset (fragP->fr_opcode, | |
12472 | fragP->tc_frag_data.default_prefix, size); | |
12473 | else | |
12474 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
12475 | size, 0); | |
12476 | fragP->fr_fix += size; | |
12477 | } | |
12478 | return; | |
12479 | } | |
12480 | ||
252b5132 RH |
12481 | opcode = (unsigned char *) fragP->fr_opcode; |
12482 | ||
47926f60 | 12483 | /* Address we want to reach in file space. */ |
252b5132 | 12484 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 12485 | |
47926f60 | 12486 | /* Address opcode resides at in file space. */ |
252b5132 RH |
12487 | opcode_address = fragP->fr_address + fragP->fr_fix; |
12488 | ||
47926f60 | 12489 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
12490 | displacement_from_opcode_start = target_address - opcode_address; |
12491 | ||
fddf5b5b | 12492 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 12493 | { |
47926f60 KH |
12494 | /* Don't have to change opcode. */ |
12495 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 12496 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
12497 | } |
12498 | else | |
12499 | { | |
12500 | if (no_cond_jump_promotion | |
12501 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
12502 | as_warn_where (fragP->fr_file, fragP->fr_line, |
12503 | _("long jump required")); | |
252b5132 | 12504 | |
fddf5b5b AM |
12505 | switch (fragP->fr_subtype) |
12506 | { | |
12507 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
12508 | extension = 4; /* 1 opcode + 4 displacement */ | |
12509 | opcode[0] = 0xe9; | |
12510 | where_to_put_displacement = &opcode[1]; | |
12511 | break; | |
252b5132 | 12512 | |
fddf5b5b AM |
12513 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
12514 | extension = 2; /* 1 opcode + 2 displacement */ | |
12515 | opcode[0] = 0xe9; | |
12516 | where_to_put_displacement = &opcode[1]; | |
12517 | break; | |
252b5132 | 12518 | |
fddf5b5b AM |
12519 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
12520 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
12521 | extension = 5; /* 2 opcode + 4 displacement */ | |
12522 | opcode[1] = opcode[0] + 0x10; | |
12523 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12524 | where_to_put_displacement = &opcode[2]; | |
12525 | break; | |
252b5132 | 12526 | |
fddf5b5b AM |
12527 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
12528 | extension = 3; /* 2 opcode + 2 displacement */ | |
12529 | opcode[1] = opcode[0] + 0x10; | |
12530 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12531 | where_to_put_displacement = &opcode[2]; | |
12532 | break; | |
252b5132 | 12533 | |
fddf5b5b AM |
12534 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
12535 | extension = 4; | |
12536 | opcode[0] ^= 1; | |
12537 | opcode[1] = 3; | |
12538 | opcode[2] = 0xe9; | |
12539 | where_to_put_displacement = &opcode[3]; | |
12540 | break; | |
12541 | ||
12542 | default: | |
12543 | BAD_CASE (fragP->fr_subtype); | |
12544 | break; | |
12545 | } | |
252b5132 | 12546 | } |
fddf5b5b | 12547 | |
7b81dfbb AJ |
12548 | /* If size if less then four we are sure that the operand fits, |
12549 | but if it's 4, then it could be that the displacement is larger | |
12550 | then -/+ 2GB. */ | |
12551 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
12552 | && object_64bit | |
12553 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
12554 | + ((addressT) 1 << 31)) |
12555 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
12556 | { |
12557 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
12558 | _("jump target out of range")); | |
12559 | /* Make us emit 0. */ | |
12560 | displacement_from_opcode_start = extension; | |
12561 | } | |
47926f60 | 12562 | /* Now put displacement after opcode. */ |
252b5132 RH |
12563 | md_number_to_chars ((char *) where_to_put_displacement, |
12564 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 12565 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
12566 | fragP->fr_fix += extension; |
12567 | } | |
12568 | \f | |
7016a5d5 | 12569 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
12570 | by our caller that we have all the info we need to fix it up. |
12571 | ||
7016a5d5 TG |
12572 | Parameter valP is the pointer to the value of the bits. |
12573 | ||
252b5132 RH |
12574 | On the 386, immediates, displacements, and data pointers are all in |
12575 | the same (little-endian) format, so we don't need to care about which | |
12576 | we are handling. */ | |
12577 | ||
94f592af | 12578 | void |
7016a5d5 | 12579 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12580 | { |
94f592af | 12581 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 12582 | valueT value = *valP; |
252b5132 | 12583 | |
f86103b7 | 12584 | #if !defined (TE_Mach) |
93382f6d AM |
12585 | if (fixP->fx_pcrel) |
12586 | { | |
12587 | switch (fixP->fx_r_type) | |
12588 | { | |
5865bb77 ILT |
12589 | default: |
12590 | break; | |
12591 | ||
d6ab8113 JB |
12592 | case BFD_RELOC_64: |
12593 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
12594 | break; | |
93382f6d | 12595 | case BFD_RELOC_32: |
ae8887b5 | 12596 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
12597 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
12598 | break; | |
12599 | case BFD_RELOC_16: | |
12600 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
12601 | break; | |
12602 | case BFD_RELOC_8: | |
12603 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
12604 | break; | |
12605 | } | |
12606 | } | |
252b5132 | 12607 | |
a161fe53 | 12608 | if (fixP->fx_addsy != NULL |
31312f95 | 12609 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 12610 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 12611 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 12612 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 12613 | && !use_rela_relocations) |
252b5132 | 12614 | { |
31312f95 AM |
12615 | /* This is a hack. There should be a better way to handle this. |
12616 | This covers for the fact that bfd_install_relocation will | |
12617 | subtract the current location (for partial_inplace, PC relative | |
12618 | relocations); see more below. */ | |
252b5132 | 12619 | #ifndef OBJ_AOUT |
718ddfc0 | 12620 | if (IS_ELF |
252b5132 RH |
12621 | #ifdef TE_PE |
12622 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
12623 | #endif | |
12624 | ) | |
12625 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12626 | #endif | |
12627 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 12628 | if (IS_ELF) |
252b5132 | 12629 | { |
6539b54b | 12630 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 12631 | |
6539b54b | 12632 | if ((sym_seg == seg |
2f66722d | 12633 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 12634 | && sym_seg != absolute_section)) |
af65af87 | 12635 | && !generic_force_reloc (fixP)) |
2f66722d AM |
12636 | { |
12637 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
12638 | bfd_install_relocation subtracts them out again. I think |
12639 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
12640 | it. FIXME. */ |
12641 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12642 | } | |
252b5132 RH |
12643 | } |
12644 | #endif | |
12645 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
12646 | /* For some reason, the PE format does not store a |
12647 | section address offset for a PC relative symbol. */ | |
12648 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 12649 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
12650 | value += md_pcrel_from (fixP); |
12651 | #endif | |
12652 | } | |
fbeb56a4 | 12653 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
12654 | if (fixP->fx_addsy != NULL |
12655 | && S_IS_WEAK (fixP->fx_addsy) | |
12656 | /* PR 16858: Do not modify weak function references. */ | |
12657 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 12658 | { |
296a8689 NC |
12659 | #if !defined (TE_PEP) |
12660 | /* For x86 PE weak function symbols are neither PC-relative | |
12661 | nor do they set S_IS_FUNCTION. So the only reliable way | |
12662 | to detect them is to check the flags of their containing | |
12663 | section. */ | |
12664 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
12665 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
12666 | ; | |
12667 | else | |
12668 | #endif | |
fbeb56a4 DK |
12669 | value -= S_GET_VALUE (fixP->fx_addsy); |
12670 | } | |
12671 | #endif | |
252b5132 RH |
12672 | |
12673 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 12674 | and we must not disappoint it. */ |
252b5132 | 12675 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12676 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
12677 | switch (fixP->fx_r_type) |
12678 | { | |
12679 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 12680 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
12681 | /* Make the jump instruction point to the address of the operand. |
12682 | At runtime we merely add the offset to the actual PLT entry. | |
12683 | NB: Subtract the offset size only for jump instructions. */ | |
12684 | if (fixP->fx_pcrel) | |
12685 | value = -4; | |
47926f60 | 12686 | break; |
31312f95 | 12687 | |
13ae64f3 JJ |
12688 | case BFD_RELOC_386_TLS_GD: |
12689 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 12690 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
12691 | case BFD_RELOC_386_TLS_IE: |
12692 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 12693 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
12694 | case BFD_RELOC_X86_64_TLSGD: |
12695 | case BFD_RELOC_X86_64_TLSLD: | |
12696 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 12697 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
12698 | value = 0; /* Fully resolved at runtime. No addend. */ |
12699 | /* Fallthrough */ | |
12700 | case BFD_RELOC_386_TLS_LE: | |
12701 | case BFD_RELOC_386_TLS_LDO_32: | |
12702 | case BFD_RELOC_386_TLS_LE_32: | |
12703 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12704 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 12705 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 12706 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
12707 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
12708 | break; | |
12709 | ||
67a4f2b7 AO |
12710 | case BFD_RELOC_386_TLS_DESC_CALL: |
12711 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
12712 | value = 0; /* Fully resolved at runtime. No addend. */ | |
12713 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12714 | fixP->fx_done = 0; | |
12715 | return; | |
12716 | ||
47926f60 KH |
12717 | case BFD_RELOC_VTABLE_INHERIT: |
12718 | case BFD_RELOC_VTABLE_ENTRY: | |
12719 | fixP->fx_done = 0; | |
94f592af | 12720 | return; |
47926f60 KH |
12721 | |
12722 | default: | |
12723 | break; | |
12724 | } | |
12725 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
a442cac5 JB |
12726 | |
12727 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ | |
12728 | if (!object_64bit) | |
12729 | value = extend_to_32bit_address (value); | |
12730 | ||
c6682705 | 12731 | *valP = value; |
f86103b7 | 12732 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 12733 | |
3e73aa7c | 12734 | /* Are we finished with this relocation now? */ |
c6682705 | 12735 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
12736 | { |
12737 | fixP->fx_done = 1; | |
12738 | switch (fixP->fx_r_type) | |
12739 | { | |
12740 | case BFD_RELOC_X86_64_32S: | |
12741 | fixP->fx_signed = 1; | |
12742 | break; | |
12743 | ||
12744 | default: | |
12745 | break; | |
12746 | } | |
12747 | } | |
fbeb56a4 DK |
12748 | #if defined (OBJ_COFF) && defined (TE_PE) |
12749 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
12750 | { | |
12751 | fixP->fx_done = 0; | |
12752 | /* Remember value for tc_gen_reloc. */ | |
12753 | fixP->fx_addnumber = value; | |
12754 | /* Clear out the frag for now. */ | |
12755 | value = 0; | |
12756 | } | |
12757 | #endif | |
3e73aa7c JH |
12758 | else if (use_rela_relocations) |
12759 | { | |
46fb6d5a JB |
12760 | if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC) |
12761 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
12762 | /* Remember value for tc_gen_reloc. */ |
12763 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
12764 | value = 0; |
12765 | } | |
f86103b7 | 12766 | |
94f592af | 12767 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 12768 | } |
252b5132 | 12769 | \f |
6d4af3c2 | 12770 | const char * |
499ac353 | 12771 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 12772 | { |
499ac353 NC |
12773 | /* This outputs the LITTLENUMs in REVERSE order; |
12774 | in accord with the bigendian 386. */ | |
5b7c81bd | 12775 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
12776 | } |
12777 | \f | |
2d545b82 | 12778 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 12779 | |
252b5132 | 12780 | static char * |
e3bb37b5 | 12781 | output_invalid (int c) |
252b5132 | 12782 | { |
3882b010 | 12783 | if (ISPRINT (c)) |
f9f21a03 L |
12784 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
12785 | "'%c'", c); | |
252b5132 | 12786 | else |
f9f21a03 | 12787 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 12788 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
12789 | return output_invalid_buf; |
12790 | } | |
12791 | ||
8a6fb3f9 JB |
12792 | /* Verify that @r can be used in the current context. */ |
12793 | ||
5b7c81bd | 12794 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
12795 | { |
12796 | if (allow_pseudo_reg) | |
5b7c81bd | 12797 | return true; |
8a6fb3f9 JB |
12798 | |
12799 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 12800 | return false; |
8a6fb3f9 JB |
12801 | |
12802 | if ((r->reg_type.bitfield.dword | |
12803 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
12804 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 12805 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 12806 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 12807 | return false; |
8a6fb3f9 | 12808 | |
22e00a3f JB |
12809 | if (r->reg_type.bitfield.class == RegTR |
12810 | && (flag_code == CODE_64BIT | |
12811 | || !cpu_arch_flags.bitfield.cpui386 | |
12812 | || cpu_arch_isa_flags.bitfield.cpui586 | |
12813 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 12814 | return false; |
22e00a3f | 12815 | |
8a6fb3f9 | 12816 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 12817 | return false; |
8a6fb3f9 JB |
12818 | |
12819 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
12820 | { | |
12821 | if (r->reg_type.bitfield.zmmword | |
12822 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 12823 | return false; |
8a6fb3f9 JB |
12824 | |
12825 | if (!cpu_arch_flags.bitfield.cpuavx) | |
12826 | { | |
12827 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 12828 | return false; |
8a6fb3f9 JB |
12829 | |
12830 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 12831 | return false; |
8a6fb3f9 JB |
12832 | } |
12833 | } | |
12834 | ||
260cd341 LC |
12835 | if (r->reg_type.bitfield.tmmword |
12836 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
12837 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 12838 | return false; |
260cd341 | 12839 | |
8a6fb3f9 | 12840 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 12841 | return false; |
8a6fb3f9 JB |
12842 | |
12843 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
12844 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 12845 | return false; |
8a6fb3f9 JB |
12846 | |
12847 | /* Upper 16 vector registers are only available with VREX in 64bit | |
12848 | mode, and require EVEX encoding. */ | |
12849 | if (r->reg_flags & RegVRex) | |
12850 | { | |
12851 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
12852 | || flag_code != CODE_64BIT) | |
5b7c81bd | 12853 | return false; |
8a6fb3f9 | 12854 | |
da4977e0 JB |
12855 | if (i.vec_encoding == vex_encoding_default) |
12856 | i.vec_encoding = vex_encoding_evex; | |
12857 | else if (i.vec_encoding != vex_encoding_evex) | |
12858 | i.vec_encoding = vex_encoding_error; | |
8a6fb3f9 JB |
12859 | } |
12860 | ||
12861 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) | |
12862 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) | |
12863 | && flag_code != CODE_64BIT) | |
5b7c81bd | 12864 | return false; |
8a6fb3f9 JB |
12865 | |
12866 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
12867 | && !intel_syntax) | |
5b7c81bd | 12868 | return false; |
8a6fb3f9 | 12869 | |
5b7c81bd | 12870 | return true; |
8a6fb3f9 JB |
12871 | } |
12872 | ||
af6bdddf | 12873 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
12874 | |
12875 | static const reg_entry * | |
4d1bb795 | 12876 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 12877 | { |
af6bdddf AM |
12878 | char *s = reg_string; |
12879 | char *p; | |
252b5132 RH |
12880 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
12881 | const reg_entry *r; | |
12882 | ||
12883 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
12884 | if (*s == REGISTER_PREFIX) | |
12885 | ++s; | |
12886 | ||
12887 | if (is_space_char (*s)) | |
12888 | ++s; | |
12889 | ||
12890 | p = reg_name_given; | |
af6bdddf | 12891 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
12892 | { |
12893 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
12894 | return (const reg_entry *) NULL; |
12895 | s++; | |
252b5132 RH |
12896 | } |
12897 | ||
6588847e DN |
12898 | /* For naked regs, make sure that we are not dealing with an identifier. |
12899 | This prevents confusing an identifier like `eax_var' with register | |
12900 | `eax'. */ | |
12901 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
12902 | return (const reg_entry *) NULL; | |
12903 | ||
af6bdddf | 12904 | *end_op = s; |
252b5132 | 12905 | |
629310ab | 12906 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 12907 | |
5f47d35b | 12908 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 12909 | if (r == reg_st0) |
5f47d35b | 12910 | { |
0e0eea78 JB |
12911 | if (!cpu_arch_flags.bitfield.cpu8087 |
12912 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
12913 | && !cpu_arch_flags.bitfield.cpu387 |
12914 | && !allow_pseudo_reg) | |
0e0eea78 JB |
12915 | return (const reg_entry *) NULL; |
12916 | ||
5f47d35b AM |
12917 | if (is_space_char (*s)) |
12918 | ++s; | |
12919 | if (*s == '(') | |
12920 | { | |
af6bdddf | 12921 | ++s; |
5f47d35b AM |
12922 | if (is_space_char (*s)) |
12923 | ++s; | |
12924 | if (*s >= '0' && *s <= '7') | |
12925 | { | |
db557034 | 12926 | int fpr = *s - '0'; |
af6bdddf | 12927 | ++s; |
5f47d35b AM |
12928 | if (is_space_char (*s)) |
12929 | ++s; | |
12930 | if (*s == ')') | |
12931 | { | |
12932 | *end_op = s + 1; | |
6288d05f | 12933 | know (r[fpr].reg_num == fpr); |
db557034 | 12934 | return r + fpr; |
5f47d35b | 12935 | } |
5f47d35b | 12936 | } |
47926f60 | 12937 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12938 | return (const reg_entry *) NULL; |
12939 | } | |
12940 | } | |
12941 | ||
8a6fb3f9 | 12942 | return r && check_register (r) ? r : NULL; |
252b5132 | 12943 | } |
4d1bb795 JB |
12944 | |
12945 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12946 | ||
12947 | static const reg_entry * | |
12948 | parse_register (char *reg_string, char **end_op) | |
12949 | { | |
12950 | const reg_entry *r; | |
12951 | ||
12952 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12953 | r = parse_real_register (reg_string, end_op); | |
12954 | else | |
12955 | r = NULL; | |
12956 | if (!r) | |
12957 | { | |
12958 | char *save = input_line_pointer; | |
12959 | char c; | |
12960 | symbolS *symbolP; | |
12961 | ||
12962 | input_line_pointer = reg_string; | |
d02603dc | 12963 | c = get_symbol_name (®_string); |
4d1bb795 | 12964 | symbolP = symbol_find (reg_string); |
64d23078 JB |
12965 | while (symbolP && S_GET_SEGMENT (symbolP) != reg_section) |
12966 | { | |
12967 | const expressionS *e = symbol_get_value_expression(symbolP); | |
12968 | ||
12969 | if (e->X_op != O_symbol || e->X_add_number) | |
12970 | break; | |
12971 | symbolP = e->X_add_symbol; | |
12972 | } | |
4d1bb795 JB |
12973 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
12974 | { | |
12975 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12976 | ||
3b55a1d0 JB |
12977 | know (e->X_op == O_register); |
12978 | know (e->X_add_number >= 0 | |
12979 | && (valueT) e->X_add_number < i386_regtab_size); | |
12980 | r = i386_regtab + e->X_add_number; | |
12981 | if (!check_register (r)) | |
8a6fb3f9 | 12982 | { |
3b55a1d0 JB |
12983 | as_bad (_("register '%s%s' cannot be used here"), |
12984 | register_prefix, r->reg_name); | |
12985 | r = &bad_reg; | |
8a6fb3f9 | 12986 | } |
3b55a1d0 | 12987 | *end_op = input_line_pointer; |
4d1bb795 JB |
12988 | } |
12989 | *input_line_pointer = c; | |
12990 | input_line_pointer = save; | |
12991 | } | |
12992 | return r; | |
12993 | } | |
12994 | ||
12995 | int | |
12996 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12997 | { | |
4faaa10f | 12998 | const reg_entry *r = NULL; |
4d1bb795 JB |
12999 | char *end = input_line_pointer; |
13000 | ||
13001 | *end = *nextcharP; | |
4faaa10f JB |
13002 | if (*name == REGISTER_PREFIX || allow_naked_reg) |
13003 | r = parse_real_register (name, &input_line_pointer); | |
4d1bb795 JB |
13004 | if (r && end <= input_line_pointer) |
13005 | { | |
13006 | *nextcharP = *input_line_pointer; | |
13007 | *input_line_pointer = 0; | |
8a6fb3f9 JB |
13008 | if (r != &bad_reg) |
13009 | { | |
13010 | e->X_op = O_register; | |
13011 | e->X_add_number = r - i386_regtab; | |
13012 | } | |
13013 | else | |
13014 | e->X_op = O_illegal; | |
4d1bb795 JB |
13015 | return 1; |
13016 | } | |
13017 | input_line_pointer = end; | |
13018 | *end = 0; | |
ee86248c | 13019 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
13020 | } |
13021 | ||
13022 | void | |
13023 | md_operand (expressionS *e) | |
13024 | { | |
ee86248c JB |
13025 | char *end; |
13026 | const reg_entry *r; | |
4d1bb795 | 13027 | |
ee86248c JB |
13028 | switch (*input_line_pointer) |
13029 | { | |
13030 | case REGISTER_PREFIX: | |
13031 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
13032 | if (r) |
13033 | { | |
13034 | e->X_op = O_register; | |
13035 | e->X_add_number = r - i386_regtab; | |
13036 | input_line_pointer = end; | |
13037 | } | |
ee86248c JB |
13038 | break; |
13039 | ||
13040 | case '[': | |
9c2799c2 | 13041 | gas_assert (intel_syntax); |
ee86248c JB |
13042 | end = input_line_pointer++; |
13043 | expression (e); | |
13044 | if (*input_line_pointer == ']') | |
13045 | { | |
13046 | ++input_line_pointer; | |
13047 | e->X_op_symbol = make_expr_symbol (e); | |
13048 | e->X_add_symbol = NULL; | |
13049 | e->X_add_number = 0; | |
13050 | e->X_op = O_index; | |
13051 | } | |
13052 | else | |
13053 | { | |
13054 | e->X_op = O_absent; | |
13055 | input_line_pointer = end; | |
13056 | } | |
13057 | break; | |
4d1bb795 JB |
13058 | } |
13059 | } | |
13060 | ||
252b5132 | 13061 | \f |
4cc782b5 | 13062 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 13063 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 13064 | #else |
b6f8c7c4 | 13065 | const char *md_shortopts = "qnO::"; |
252b5132 | 13066 | #endif |
6e0b89ee | 13067 | |
3e73aa7c | 13068 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
13069 | #define OPTION_64 (OPTION_MD_BASE + 1) |
13070 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
13071 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
13072 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
13073 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
13074 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
13075 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
13076 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 13077 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 13078 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 13079 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
13080 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
13081 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
13082 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 13083 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
13084 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
13085 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 13086 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 13087 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 13088 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 13089 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
13090 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
13091 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 13092 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 13093 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 13094 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
13095 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
13096 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
13097 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 13098 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
13099 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
13100 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
13101 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
c8480b58 | 13102 | #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34) |
b3b91714 | 13103 | |
99ad8390 NC |
13104 | struct option md_longopts[] = |
13105 | { | |
3e73aa7c | 13106 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 13107 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13108 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 13109 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
13110 | #endif |
13111 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 13112 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 13113 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 13114 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 13115 | #endif |
b3b91714 | 13116 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
13117 | {"march", required_argument, NULL, OPTION_MARCH}, |
13118 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
13119 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
13120 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
13121 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
13122 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 13123 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
c8480b58 | 13124 | {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE}, |
daf50ae7 | 13125 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 13126 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 13127 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 13128 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 13129 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
13130 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
13131 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
13132 | # if defined (TE_PE) || defined (TE_PEP) |
13133 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
13134 | #endif | |
d1982f93 | 13135 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 13136 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 13137 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 13138 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
13139 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
13140 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
13141 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 13142 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
13143 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
13144 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
13145 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
13146 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
13147 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
13148 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
13149 | {NULL, no_argument, NULL, 0} |
13150 | }; | |
13151 | size_t md_longopts_size = sizeof (md_longopts); | |
13152 | ||
13153 | int | |
17b9d67d | 13154 | md_parse_option (int c, const char *arg) |
252b5132 | 13155 | { |
91d6fa6a | 13156 | unsigned int j; |
e379e5f3 | 13157 | char *arch, *next, *saved, *type; |
9103f4f4 | 13158 | |
252b5132 RH |
13159 | switch (c) |
13160 | { | |
12b55ccc L |
13161 | case 'n': |
13162 | optimize_align_code = 0; | |
13163 | break; | |
13164 | ||
a38cf1db AM |
13165 | case 'q': |
13166 | quiet_warnings = 1; | |
252b5132 RH |
13167 | break; |
13168 | ||
13169 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
13170 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
13171 | should be emitted or not. FIXME: Not implemented. */ | |
13172 | case 'Q': | |
d4693039 JB |
13173 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
13174 | return 0; | |
252b5132 RH |
13175 | break; |
13176 | ||
13177 | /* -V: SVR4 argument to print version ID. */ | |
13178 | case 'V': | |
13179 | print_version_id (); | |
13180 | break; | |
13181 | ||
a38cf1db AM |
13182 | /* -k: Ignore for FreeBSD compatibility. */ |
13183 | case 'k': | |
252b5132 | 13184 | break; |
4cc782b5 ILT |
13185 | |
13186 | case 's': | |
13187 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 13188 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 13189 | break; |
8dcea932 L |
13190 | |
13191 | case OPTION_MSHARED: | |
13192 | shared = 1; | |
13193 | break; | |
b4a3a7b4 L |
13194 | |
13195 | case OPTION_X86_USED_NOTE: | |
13196 | if (strcasecmp (arg, "yes") == 0) | |
13197 | x86_used_note = 1; | |
13198 | else if (strcasecmp (arg, "no") == 0) | |
13199 | x86_used_note = 0; | |
13200 | else | |
13201 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
13202 | break; | |
13203 | ||
13204 | ||
99ad8390 | 13205 | #endif |
321098a5 | 13206 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13207 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
13208 | case OPTION_64: |
13209 | { | |
13210 | const char **list, **l; | |
13211 | ||
3e73aa7c JH |
13212 | list = bfd_target_list (); |
13213 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13214 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
13215 | || strcmp (*l, "coff-x86-64") == 0 |
13216 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
13217 | || strcmp (*l, "pei-x86-64") == 0 |
13218 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
13219 | { |
13220 | default_arch = "x86_64"; | |
13221 | break; | |
13222 | } | |
3e73aa7c | 13223 | if (*l == NULL) |
2b5d6a91 | 13224 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
13225 | free (list); |
13226 | } | |
13227 | break; | |
13228 | #endif | |
252b5132 | 13229 | |
351f65ca | 13230 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 13231 | case OPTION_X32: |
351f65ca L |
13232 | if (IS_ELF) |
13233 | { | |
13234 | const char **list, **l; | |
13235 | ||
13236 | list = bfd_target_list (); | |
13237 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13238 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
13239 | { |
13240 | default_arch = "x86_64:32"; | |
13241 | break; | |
13242 | } | |
13243 | if (*l == NULL) | |
2b5d6a91 | 13244 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
13245 | free (list); |
13246 | } | |
13247 | else | |
13248 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
13249 | break; | |
13250 | #endif | |
13251 | ||
6e0b89ee AM |
13252 | case OPTION_32: |
13253 | default_arch = "i386"; | |
13254 | break; | |
13255 | ||
b3b91714 AM |
13256 | case OPTION_DIVIDE: |
13257 | #ifdef SVR4_COMMENT_CHARS | |
13258 | { | |
13259 | char *n, *t; | |
13260 | const char *s; | |
13261 | ||
add39d23 | 13262 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
13263 | t = n; |
13264 | for (s = i386_comment_chars; *s != '\0'; s++) | |
13265 | if (*s != '/') | |
13266 | *t++ = *s; | |
13267 | *t = '\0'; | |
13268 | i386_comment_chars = n; | |
13269 | } | |
13270 | #endif | |
13271 | break; | |
13272 | ||
9103f4f4 | 13273 | case OPTION_MARCH: |
293f5f65 L |
13274 | saved = xstrdup (arg); |
13275 | arch = saved; | |
13276 | /* Allow -march=+nosse. */ | |
13277 | if (*arch == '+') | |
13278 | arch++; | |
6305a203 | 13279 | do |
9103f4f4 | 13280 | { |
6305a203 | 13281 | if (*arch == '.') |
2b5d6a91 | 13282 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13283 | next = strchr (arch, '+'); |
13284 | if (next) | |
13285 | *next++ = '\0'; | |
91d6fa6a | 13286 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13287 | { |
ae89daec JB |
13288 | if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE |
13289 | && strcmp (arch, cpu_arch[j].name) == 0) | |
ccc9c027 | 13290 | { |
6305a203 | 13291 | /* Processor. */ |
ae89daec | 13292 | if (! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
13293 | continue; |
13294 | ||
91d6fa6a | 13295 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 13296 | free (cpu_sub_arch_name); |
6305a203 | 13297 | cpu_sub_arch_name = NULL; |
ae89daec | 13298 | cpu_arch_flags = cpu_arch[j].enable; |
91d6fa6a | 13299 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 13300 | cpu_arch_isa_flags = cpu_arch[j].enable; |
6305a203 L |
13301 | if (!cpu_arch_tune_set) |
13302 | { | |
13303 | cpu_arch_tune = cpu_arch_isa; | |
13304 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13305 | } | |
13306 | break; | |
13307 | } | |
ae89daec JB |
13308 | else if (cpu_arch[j].type == PROCESSOR_NONE |
13309 | && strcmp (arch, cpu_arch[j].name) == 0 | |
13310 | && !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
6305a203 | 13311 | { |
33eaf5de | 13312 | /* ISA extension. */ |
6305a203 | 13313 | i386_cpu_flags flags; |
309d3373 | 13314 | |
293f5f65 | 13315 | flags = cpu_flags_or (cpu_arch_flags, |
ae89daec | 13316 | cpu_arch[j].enable); |
81486035 | 13317 | |
5b64d091 | 13318 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 | 13319 | { |
ae89daec | 13320 | extend_cpu_sub_arch_name (arch); |
6305a203 | 13321 | cpu_arch_flags = flags; |
a586129e | 13322 | cpu_arch_isa_flags = flags; |
6305a203 | 13323 | } |
0089dace L |
13324 | else |
13325 | cpu_arch_isa_flags | |
13326 | = cpu_flags_or (cpu_arch_isa_flags, | |
ae89daec | 13327 | cpu_arch[j].enable); |
6305a203 | 13328 | break; |
ccc9c027 | 13329 | } |
9103f4f4 | 13330 | } |
6305a203 | 13331 | |
ae89daec | 13332 | if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no")) |
293f5f65 | 13333 | { |
33eaf5de | 13334 | /* Disable an ISA extension. */ |
ae89daec JB |
13335 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
13336 | if (cpu_arch[j].type == PROCESSOR_NONE | |
13337 | && strcmp (arch + 2, cpu_arch[j].name) == 0) | |
293f5f65 L |
13338 | { |
13339 | i386_cpu_flags flags; | |
13340 | ||
13341 | flags = cpu_flags_and_not (cpu_arch_flags, | |
ae89daec | 13342 | cpu_arch[j].disable); |
293f5f65 L |
13343 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
13344 | { | |
8180707f | 13345 | extend_cpu_sub_arch_name (arch); |
293f5f65 L |
13346 | cpu_arch_flags = flags; |
13347 | cpu_arch_isa_flags = flags; | |
13348 | } | |
13349 | break; | |
13350 | } | |
293f5f65 L |
13351 | } |
13352 | ||
91d6fa6a | 13353 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13354 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13355 | |
13356 | arch = next; | |
9103f4f4 | 13357 | } |
293f5f65 L |
13358 | while (next != NULL); |
13359 | free (saved); | |
9103f4f4 L |
13360 | break; |
13361 | ||
13362 | case OPTION_MTUNE: | |
13363 | if (*arg == '.') | |
2b5d6a91 | 13364 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 13365 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13366 | { |
ae89daec JB |
13367 | if (cpu_arch[j].type != PROCESSOR_NONE |
13368 | && strcmp (arg, cpu_arch[j].name) == 0) | |
9103f4f4 | 13369 | { |
ccc9c027 | 13370 | cpu_arch_tune_set = 1; |
91d6fa6a | 13371 | cpu_arch_tune = cpu_arch [j].type; |
ae89daec | 13372 | cpu_arch_tune_flags = cpu_arch[j].enable; |
9103f4f4 L |
13373 | break; |
13374 | } | |
13375 | } | |
91d6fa6a | 13376 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13377 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
13378 | break; |
13379 | ||
1efbbeb4 L |
13380 | case OPTION_MMNEMONIC: |
13381 | if (strcasecmp (arg, "att") == 0) | |
13382 | intel_mnemonic = 0; | |
13383 | else if (strcasecmp (arg, "intel") == 0) | |
13384 | intel_mnemonic = 1; | |
13385 | else | |
2b5d6a91 | 13386 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
13387 | break; |
13388 | ||
13389 | case OPTION_MSYNTAX: | |
13390 | if (strcasecmp (arg, "att") == 0) | |
13391 | intel_syntax = 0; | |
13392 | else if (strcasecmp (arg, "intel") == 0) | |
13393 | intel_syntax = 1; | |
13394 | else | |
2b5d6a91 | 13395 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
13396 | break; |
13397 | ||
13398 | case OPTION_MINDEX_REG: | |
13399 | allow_index_reg = 1; | |
13400 | break; | |
13401 | ||
13402 | case OPTION_MNAKED_REG: | |
13403 | allow_naked_reg = 1; | |
13404 | break; | |
13405 | ||
c0f3af97 L |
13406 | case OPTION_MSSE2AVX: |
13407 | sse2avx = 1; | |
13408 | break; | |
13409 | ||
c8480b58 L |
13410 | case OPTION_MUSE_UNALIGNED_VECTOR_MOVE: |
13411 | use_unaligned_vector_move = 1; | |
13412 | break; | |
13413 | ||
daf50ae7 L |
13414 | case OPTION_MSSE_CHECK: |
13415 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 13416 | sse_check = check_error; |
daf50ae7 | 13417 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 13418 | sse_check = check_warning; |
daf50ae7 | 13419 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 13420 | sse_check = check_none; |
daf50ae7 | 13421 | else |
2b5d6a91 | 13422 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
13423 | break; |
13424 | ||
7bab8ab5 JB |
13425 | case OPTION_MOPERAND_CHECK: |
13426 | if (strcasecmp (arg, "error") == 0) | |
13427 | operand_check = check_error; | |
13428 | else if (strcasecmp (arg, "warning") == 0) | |
13429 | operand_check = check_warning; | |
13430 | else if (strcasecmp (arg, "none") == 0) | |
13431 | operand_check = check_none; | |
13432 | else | |
13433 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
13434 | break; | |
13435 | ||
539f890d L |
13436 | case OPTION_MAVXSCALAR: |
13437 | if (strcasecmp (arg, "128") == 0) | |
13438 | avxscalar = vex128; | |
13439 | else if (strcasecmp (arg, "256") == 0) | |
13440 | avxscalar = vex256; | |
13441 | else | |
2b5d6a91 | 13442 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
13443 | break; |
13444 | ||
03751133 L |
13445 | case OPTION_MVEXWIG: |
13446 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 13447 | vexwig = vexw0; |
03751133 | 13448 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 13449 | vexwig = vexw1; |
03751133 L |
13450 | else |
13451 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
13452 | break; | |
13453 | ||
7e8b059b L |
13454 | case OPTION_MADD_BND_PREFIX: |
13455 | add_bnd_prefix = 1; | |
13456 | break; | |
13457 | ||
43234a1e L |
13458 | case OPTION_MEVEXLIG: |
13459 | if (strcmp (arg, "128") == 0) | |
13460 | evexlig = evexl128; | |
13461 | else if (strcmp (arg, "256") == 0) | |
13462 | evexlig = evexl256; | |
13463 | else if (strcmp (arg, "512") == 0) | |
13464 | evexlig = evexl512; | |
13465 | else | |
13466 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
13467 | break; | |
13468 | ||
d3d3c6db IT |
13469 | case OPTION_MEVEXRCIG: |
13470 | if (strcmp (arg, "rne") == 0) | |
13471 | evexrcig = rne; | |
13472 | else if (strcmp (arg, "rd") == 0) | |
13473 | evexrcig = rd; | |
13474 | else if (strcmp (arg, "ru") == 0) | |
13475 | evexrcig = ru; | |
13476 | else if (strcmp (arg, "rz") == 0) | |
13477 | evexrcig = rz; | |
13478 | else | |
13479 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
13480 | break; | |
13481 | ||
43234a1e L |
13482 | case OPTION_MEVEXWIG: |
13483 | if (strcmp (arg, "0") == 0) | |
13484 | evexwig = evexw0; | |
13485 | else if (strcmp (arg, "1") == 0) | |
13486 | evexwig = evexw1; | |
13487 | else | |
13488 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
13489 | break; | |
13490 | ||
167ad85b TG |
13491 | # if defined (TE_PE) || defined (TE_PEP) |
13492 | case OPTION_MBIG_OBJ: | |
13493 | use_big_obj = 1; | |
13494 | break; | |
13495 | #endif | |
13496 | ||
d1982f93 | 13497 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
13498 | if (strcasecmp (arg, "yes") == 0) |
13499 | omit_lock_prefix = 1; | |
13500 | else if (strcasecmp (arg, "no") == 0) | |
13501 | omit_lock_prefix = 0; | |
13502 | else | |
13503 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
13504 | break; | |
13505 | ||
e4e00185 AS |
13506 | case OPTION_MFENCE_AS_LOCK_ADD: |
13507 | if (strcasecmp (arg, "yes") == 0) | |
13508 | avoid_fence = 1; | |
13509 | else if (strcasecmp (arg, "no") == 0) | |
13510 | avoid_fence = 0; | |
13511 | else | |
13512 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
13513 | break; | |
13514 | ||
ae531041 L |
13515 | case OPTION_MLFENCE_AFTER_LOAD: |
13516 | if (strcasecmp (arg, "yes") == 0) | |
13517 | lfence_after_load = 1; | |
13518 | else if (strcasecmp (arg, "no") == 0) | |
13519 | lfence_after_load = 0; | |
13520 | else | |
13521 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
13522 | break; | |
13523 | ||
13524 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
13525 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 13526 | { |
13527 | lfence_before_indirect_branch = lfence_branch_all; | |
13528 | if (lfence_before_ret == lfence_before_ret_none) | |
13529 | lfence_before_ret = lfence_before_ret_shl; | |
13530 | } | |
ae531041 L |
13531 | else if (strcasecmp (arg, "memory") == 0) |
13532 | lfence_before_indirect_branch = lfence_branch_memory; | |
13533 | else if (strcasecmp (arg, "register") == 0) | |
13534 | lfence_before_indirect_branch = lfence_branch_register; | |
13535 | else if (strcasecmp (arg, "none") == 0) | |
13536 | lfence_before_indirect_branch = lfence_branch_none; | |
13537 | else | |
13538 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
13539 | arg); | |
13540 | break; | |
13541 | ||
13542 | case OPTION_MLFENCE_BEFORE_RET: | |
13543 | if (strcasecmp (arg, "or") == 0) | |
13544 | lfence_before_ret = lfence_before_ret_or; | |
13545 | else if (strcasecmp (arg, "not") == 0) | |
13546 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 13547 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
13548 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
13549 | else if (strcasecmp (arg, "none") == 0) |
13550 | lfence_before_ret = lfence_before_ret_none; | |
13551 | else | |
13552 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
13553 | arg); | |
13554 | break; | |
13555 | ||
0cb4071e L |
13556 | case OPTION_MRELAX_RELOCATIONS: |
13557 | if (strcasecmp (arg, "yes") == 0) | |
13558 | generate_relax_relocations = 1; | |
13559 | else if (strcasecmp (arg, "no") == 0) | |
13560 | generate_relax_relocations = 0; | |
13561 | else | |
13562 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
13563 | break; | |
13564 | ||
e379e5f3 L |
13565 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
13566 | { | |
13567 | char *end; | |
13568 | long int align = strtoul (arg, &end, 0); | |
13569 | if (*end == '\0') | |
13570 | { | |
13571 | if (align == 0) | |
13572 | { | |
13573 | align_branch_power = 0; | |
13574 | break; | |
13575 | } | |
13576 | else if (align >= 16) | |
13577 | { | |
13578 | int align_power; | |
13579 | for (align_power = 0; | |
13580 | (align & 1) == 0; | |
13581 | align >>= 1, align_power++) | |
13582 | continue; | |
13583 | /* Limit alignment power to 31. */ | |
13584 | if (align == 1 && align_power < 32) | |
13585 | { | |
13586 | align_branch_power = align_power; | |
13587 | break; | |
13588 | } | |
13589 | } | |
13590 | } | |
13591 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
13592 | } | |
13593 | break; | |
13594 | ||
13595 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
13596 | { | |
13597 | char *end; | |
13598 | int align = strtoul (arg, &end, 0); | |
13599 | /* Some processors only support 5 prefixes. */ | |
13600 | if (*end == '\0' && align >= 0 && align < 6) | |
13601 | { | |
13602 | align_branch_prefix_size = align; | |
13603 | break; | |
13604 | } | |
13605 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
13606 | arg); | |
13607 | } | |
13608 | break; | |
13609 | ||
13610 | case OPTION_MALIGN_BRANCH: | |
13611 | align_branch = 0; | |
13612 | saved = xstrdup (arg); | |
13613 | type = saved; | |
13614 | do | |
13615 | { | |
13616 | next = strchr (type, '+'); | |
13617 | if (next) | |
13618 | *next++ = '\0'; | |
13619 | if (strcasecmp (type, "jcc") == 0) | |
13620 | align_branch |= align_branch_jcc_bit; | |
13621 | else if (strcasecmp (type, "fused") == 0) | |
13622 | align_branch |= align_branch_fused_bit; | |
13623 | else if (strcasecmp (type, "jmp") == 0) | |
13624 | align_branch |= align_branch_jmp_bit; | |
13625 | else if (strcasecmp (type, "call") == 0) | |
13626 | align_branch |= align_branch_call_bit; | |
13627 | else if (strcasecmp (type, "ret") == 0) | |
13628 | align_branch |= align_branch_ret_bit; | |
13629 | else if (strcasecmp (type, "indirect") == 0) | |
13630 | align_branch |= align_branch_indirect_bit; | |
13631 | else | |
13632 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
13633 | type = next; | |
13634 | } | |
13635 | while (next != NULL); | |
13636 | free (saved); | |
13637 | break; | |
13638 | ||
76cf450b L |
13639 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
13640 | align_branch_power = 5; | |
13641 | align_branch_prefix_size = 5; | |
13642 | align_branch = (align_branch_jcc_bit | |
13643 | | align_branch_fused_bit | |
13644 | | align_branch_jmp_bit); | |
13645 | break; | |
13646 | ||
5db04b09 | 13647 | case OPTION_MAMD64: |
4b5aaf5f | 13648 | isa64 = amd64; |
5db04b09 L |
13649 | break; |
13650 | ||
13651 | case OPTION_MINTEL64: | |
4b5aaf5f | 13652 | isa64 = intel64; |
5db04b09 L |
13653 | break; |
13654 | ||
b6f8c7c4 L |
13655 | case 'O': |
13656 | if (arg == NULL) | |
13657 | { | |
13658 | optimize = 1; | |
13659 | /* Turn off -Os. */ | |
13660 | optimize_for_space = 0; | |
13661 | } | |
13662 | else if (*arg == 's') | |
13663 | { | |
13664 | optimize_for_space = 1; | |
13665 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 13666 | optimize = INT_MAX; |
b6f8c7c4 L |
13667 | } |
13668 | else | |
13669 | { | |
13670 | optimize = atoi (arg); | |
13671 | /* Turn off -Os. */ | |
13672 | optimize_for_space = 0; | |
13673 | } | |
13674 | break; | |
13675 | ||
252b5132 RH |
13676 | default: |
13677 | return 0; | |
13678 | } | |
13679 | return 1; | |
13680 | } | |
13681 | ||
8a2c8fef L |
13682 | #define MESSAGE_TEMPLATE \ |
13683 | " " | |
13684 | ||
293f5f65 L |
13685 | static char * |
13686 | output_message (FILE *stream, char *p, char *message, char *start, | |
13687 | int *left_p, const char *name, int len) | |
13688 | { | |
13689 | int size = sizeof (MESSAGE_TEMPLATE); | |
13690 | int left = *left_p; | |
13691 | ||
13692 | /* Reserve 2 spaces for ", " or ",\0" */ | |
13693 | left -= len + 2; | |
13694 | ||
13695 | /* Check if there is any room. */ | |
13696 | if (left >= 0) | |
13697 | { | |
13698 | if (p != start) | |
13699 | { | |
13700 | *p++ = ','; | |
13701 | *p++ = ' '; | |
13702 | } | |
13703 | p = mempcpy (p, name, len); | |
13704 | } | |
13705 | else | |
13706 | { | |
13707 | /* Output the current message now and start a new one. */ | |
13708 | *p++ = ','; | |
13709 | *p = '\0'; | |
13710 | fprintf (stream, "%s\n", message); | |
13711 | p = start; | |
13712 | left = size - (start - message) - len - 2; | |
13713 | ||
13714 | gas_assert (left >= 0); | |
13715 | ||
13716 | p = mempcpy (p, name, len); | |
13717 | } | |
13718 | ||
13719 | *left_p = left; | |
13720 | return p; | |
13721 | } | |
13722 | ||
8a2c8fef | 13723 | static void |
1ded5609 | 13724 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
13725 | { |
13726 | static char message[] = MESSAGE_TEMPLATE; | |
13727 | char *start = message + 27; | |
13728 | char *p; | |
13729 | int size = sizeof (MESSAGE_TEMPLATE); | |
13730 | int left; | |
13731 | const char *name; | |
13732 | int len; | |
13733 | unsigned int j; | |
13734 | ||
13735 | p = start; | |
13736 | left = size - (start - message); | |
3ce2ebcf JB |
13737 | |
13738 | if (!ext && check) | |
13739 | { | |
13740 | p = output_message (stream, p, message, start, &left, | |
13741 | STRING_COMMA_LEN ("default")); | |
f68697e8 JB |
13742 | p = output_message (stream, p, message, start, &left, |
13743 | STRING_COMMA_LEN ("push")); | |
13744 | p = output_message (stream, p, message, start, &left, | |
13745 | STRING_COMMA_LEN ("pop")); | |
3ce2ebcf JB |
13746 | } |
13747 | ||
8a2c8fef L |
13748 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
13749 | { | |
13750 | /* Should it be skipped? */ | |
13751 | if (cpu_arch [j].skip) | |
13752 | continue; | |
13753 | ||
13754 | name = cpu_arch [j].name; | |
13755 | len = cpu_arch [j].len; | |
ae89daec | 13756 | if (cpu_arch[j].type == PROCESSOR_NONE) |
8a2c8fef L |
13757 | { |
13758 | /* It is an extension. Skip if we aren't asked to show it. */ | |
ae89daec | 13759 | if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable)) |
8a2c8fef L |
13760 | continue; |
13761 | } | |
13762 | else if (ext) | |
13763 | { | |
13764 | /* It is an processor. Skip if we show only extension. */ | |
13765 | continue; | |
13766 | } | |
ae89daec | 13767 | else if (check && ! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
13768 | { |
13769 | /* It is an impossible processor - skip. */ | |
13770 | continue; | |
13771 | } | |
8a2c8fef | 13772 | |
293f5f65 | 13773 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
13774 | } |
13775 | ||
293f5f65 L |
13776 | /* Display disabled extensions. */ |
13777 | if (ext) | |
ae89daec | 13778 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
293f5f65 | 13779 | { |
ae89daec JB |
13780 | char *str; |
13781 | ||
13782 | if (cpu_arch[j].type != PROCESSOR_NONE | |
13783 | || !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
13784 | continue; | |
13785 | str = xasprintf ("no%s", cpu_arch[j].name); | |
13786 | p = output_message (stream, p, message, start, &left, str, | |
13787 | strlen (str)); | |
13788 | free (str); | |
293f5f65 L |
13789 | } |
13790 | ||
8a2c8fef L |
13791 | *p = '\0'; |
13792 | fprintf (stream, "%s\n", message); | |
13793 | } | |
13794 | ||
252b5132 | 13795 | void |
8a2c8fef | 13796 | md_show_usage (FILE *stream) |
252b5132 | 13797 | { |
4cc782b5 ILT |
13798 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13799 | fprintf (stream, _("\ | |
d4693039 | 13800 | -Qy, -Qn ignored\n\ |
a38cf1db | 13801 | -V print assembler version number\n\ |
b3b91714 AM |
13802 | -k ignored\n")); |
13803 | #endif | |
13804 | fprintf (stream, _("\ | |
7ebd68d1 NC |
13805 | -n do not optimize code alignment\n\ |
13806 | -O{012s} attempt some code optimizations\n\ | |
b3b91714 AM |
13807 | -q quieten some warnings\n")); |
13808 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13809 | fprintf (stream, _("\ | |
a38cf1db | 13810 | -s ignored\n")); |
b3b91714 | 13811 | #endif |
b00af7c8 JB |
13812 | #ifdef BFD64 |
13813 | # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13814 | fprintf (stream, _("\ | |
13815 | --32/--64/--x32 generate 32bit/64bit/x32 object\n")); | |
13816 | # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O) | |
751d281c | 13817 | fprintf (stream, _("\ |
b00af7c8 JB |
13818 | --32/--64 generate 32bit/64bit object\n")); |
13819 | # endif | |
751d281c | 13820 | #endif |
b3b91714 AM |
13821 | #ifdef SVR4_COMMENT_CHARS |
13822 | fprintf (stream, _("\ | |
13823 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
13824 | #else |
13825 | fprintf (stream, _("\ | |
b3b91714 | 13826 | --divide ignored\n")); |
4cc782b5 | 13827 | #endif |
9103f4f4 | 13828 | fprintf (stream, _("\ |
6305a203 | 13829 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 13830 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 13831 | show_arch (stream, 0, 1); |
8a2c8fef | 13832 | fprintf (stream, _("\ |
ae89daec | 13833 | EXTENSION is combination of (possibly \"no\"-prefixed):\n")); |
1ded5609 | 13834 | show_arch (stream, 1, 0); |
6305a203 | 13835 | fprintf (stream, _("\ |
8a2c8fef | 13836 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 13837 | show_arch (stream, 0, 0); |
ba104c83 | 13838 | fprintf (stream, _("\ |
c0f3af97 L |
13839 | -msse2avx encode SSE instructions with VEX prefix\n")); |
13840 | fprintf (stream, _("\ | |
c8480b58 L |
13841 | -muse-unaligned-vector-move\n\ |
13842 | encode aligned vector move as unaligned vector move\n")); | |
13843 | fprintf (stream, _("\ | |
7c5c05ef | 13844 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
13845 | check SSE instructions\n")); |
13846 | fprintf (stream, _("\ | |
7c5c05ef | 13847 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
13848 | check operand combinations for validity\n")); |
13849 | fprintf (stream, _("\ | |
7c5c05ef L |
13850 | -mavxscalar=[128|256] (default: 128)\n\ |
13851 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
13852 | length\n")); |
13853 | fprintf (stream, _("\ | |
03751133 L |
13854 | -mvexwig=[0|1] (default: 0)\n\ |
13855 | encode VEX instructions with specific VEX.W value\n\ | |
13856 | for VEX.W bit ignored instructions\n")); | |
13857 | fprintf (stream, _("\ | |
7c5c05ef L |
13858 | -mevexlig=[128|256|512] (default: 128)\n\ |
13859 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
13860 | length\n")); |
13861 | fprintf (stream, _("\ | |
7c5c05ef L |
13862 | -mevexwig=[0|1] (default: 0)\n\ |
13863 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
13864 | for EVEX.W bit ignored instructions\n")); |
13865 | fprintf (stream, _("\ | |
7c5c05ef | 13866 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
13867 | encode EVEX instructions with specific EVEX.RC value\n\ |
13868 | for SAE-only ignored instructions\n")); | |
13869 | fprintf (stream, _("\ | |
7c5c05ef L |
13870 | -mmnemonic=[att|intel] ")); |
13871 | if (SYSV386_COMPAT) | |
13872 | fprintf (stream, _("(default: att)\n")); | |
13873 | else | |
13874 | fprintf (stream, _("(default: intel)\n")); | |
13875 | fprintf (stream, _("\ | |
13876 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 13877 | fprintf (stream, _("\ |
7c5c05ef L |
13878 | -msyntax=[att|intel] (default: att)\n\ |
13879 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
13880 | fprintf (stream, _("\ |
13881 | -mindex-reg support pseudo index registers\n")); | |
13882 | fprintf (stream, _("\ | |
13883 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
13884 | fprintf (stream, _("\ | |
7e8b059b | 13885 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 13886 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
13887 | fprintf (stream, _("\ |
13888 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
13889 | fprintf (stream, _("\ |
13890 | -mx86-used-note=[no|yes] ")); | |
13891 | if (DEFAULT_X86_USED_NOTE) | |
13892 | fprintf (stream, _("(default: yes)\n")); | |
13893 | else | |
13894 | fprintf (stream, _("(default: no)\n")); | |
13895 | fprintf (stream, _("\ | |
13896 | generate x86 used ISA and feature properties\n")); | |
13897 | #endif | |
13898 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
13899 | fprintf (stream, _("\ |
13900 | -mbig-obj generate big object files\n")); | |
13901 | #endif | |
d022bddd | 13902 | fprintf (stream, _("\ |
7c5c05ef | 13903 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 13904 | strip all lock prefixes\n")); |
5db04b09 | 13905 | fprintf (stream, _("\ |
7c5c05ef | 13906 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
13907 | encode lfence, mfence and sfence as\n\ |
13908 | lock addl $0x0, (%%{re}sp)\n")); | |
13909 | fprintf (stream, _("\ | |
7c5c05ef L |
13910 | -mrelax-relocations=[no|yes] ")); |
13911 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
13912 | fprintf (stream, _("(default: yes)\n")); | |
13913 | else | |
13914 | fprintf (stream, _("(default: no)\n")); | |
13915 | fprintf (stream, _("\ | |
0cb4071e L |
13916 | generate relax relocations\n")); |
13917 | fprintf (stream, _("\ | |
e379e5f3 L |
13918 | -malign-branch-boundary=NUM (default: 0)\n\ |
13919 | align branches within NUM byte boundary\n")); | |
13920 | fprintf (stream, _("\ | |
13921 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
13922 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
13923 | indirect\n\ | |
13924 | specify types of branches to align\n")); | |
13925 | fprintf (stream, _("\ | |
13926 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
13927 | align branches with NUM prefixes per instruction\n")); | |
13928 | fprintf (stream, _("\ | |
76cf450b L |
13929 | -mbranches-within-32B-boundaries\n\ |
13930 | align branches within 32 byte boundary\n")); | |
13931 | fprintf (stream, _("\ | |
ae531041 L |
13932 | -mlfence-after-load=[no|yes] (default: no)\n\ |
13933 | generate lfence after load\n")); | |
13934 | fprintf (stream, _("\ | |
13935 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
13936 | generate lfence before indirect near branch\n")); | |
13937 | fprintf (stream, _("\ | |
a09f656b | 13938 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
13939 | generate lfence before ret\n")); |
13940 | fprintf (stream, _("\ | |
7c5c05ef | 13941 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13942 | fprintf (stream, _("\ |
13943 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13944 | } |
13945 | ||
3e73aa7c | 13946 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13947 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13948 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13949 | |
13950 | /* Pick the target format to use. */ | |
13951 | ||
47926f60 | 13952 | const char * |
e3bb37b5 | 13953 | i386_target_format (void) |
252b5132 | 13954 | { |
d34049e8 | 13955 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
13956 | { |
13957 | update_code_flag (CODE_64BIT, 1); | |
13958 | if (default_arch[6] == '\0') | |
7f56bc95 | 13959 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13960 | else |
7f56bc95 | 13961 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13962 | } |
3e73aa7c | 13963 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13964 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13965 | else if (!strcmp (default_arch, "iamcu")) |
13966 | { | |
13967 | update_code_flag (CODE_32BIT, 1); | |
13968 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13969 | { | |
13970 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13971 | cpu_arch_name = "iamcu"; | |
d92c7521 | 13972 | free (cpu_sub_arch_name); |
5197d474 L |
13973 | cpu_sub_arch_name = NULL; |
13974 | cpu_arch_flags = iamcu_flags; | |
13975 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13976 | cpu_arch_isa_flags = iamcu_flags; | |
13977 | if (!cpu_arch_tune_set) | |
13978 | { | |
13979 | cpu_arch_tune = cpu_arch_isa; | |
13980 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13981 | } | |
13982 | } | |
8d471ec1 | 13983 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13984 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13985 | cpu_arch_name); | |
13986 | } | |
3e73aa7c | 13987 | else |
2b5d6a91 | 13988 | as_fatal (_("unknown architecture")); |
89507696 JB |
13989 | |
13990 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
ae89daec | 13991 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 13992 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
ae89daec | 13993 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 13994 | |
252b5132 RH |
13995 | switch (OUTPUT_FLAVOR) |
13996 | { | |
9384f2ff | 13997 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13998 | case bfd_target_aout_flavour: |
47926f60 | 13999 | return AOUT_TARGET_FORMAT; |
4c63da97 | 14000 | #endif |
9384f2ff AM |
14001 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
14002 | # if defined (TE_PE) || defined (TE_PEP) | |
14003 | case bfd_target_coff_flavour: | |
167ad85b | 14004 | if (flag_code == CODE_64BIT) |
eb19308f JB |
14005 | { |
14006 | object_64bit = 1; | |
14007 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
14008 | } | |
14009 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 14010 | # elif defined (TE_GO32) |
0561d57c JK |
14011 | case bfd_target_coff_flavour: |
14012 | return "coff-go32"; | |
9384f2ff | 14013 | # else |
252b5132 RH |
14014 | case bfd_target_coff_flavour: |
14015 | return "coff-i386"; | |
9384f2ff | 14016 | # endif |
4c63da97 | 14017 | #endif |
3e73aa7c | 14018 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 14019 | case bfd_target_elf_flavour: |
3e73aa7c | 14020 | { |
351f65ca L |
14021 | const char *format; |
14022 | ||
14023 | switch (x86_elf_abi) | |
4fa24527 | 14024 | { |
351f65ca L |
14025 | default: |
14026 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
14027 | #ifndef TE_SOLARIS |
14028 | tls_get_addr = "___tls_get_addr"; | |
14029 | #endif | |
351f65ca | 14030 | break; |
7f56bc95 | 14031 | case X86_64_ABI: |
351f65ca | 14032 | use_rela_relocations = 1; |
4fa24527 | 14033 | object_64bit = 1; |
e379e5f3 L |
14034 | #ifndef TE_SOLARIS |
14035 | tls_get_addr = "__tls_get_addr"; | |
14036 | #endif | |
351f65ca L |
14037 | format = ELF_TARGET_FORMAT64; |
14038 | break; | |
7f56bc95 | 14039 | case X86_64_X32_ABI: |
4fa24527 | 14040 | use_rela_relocations = 1; |
351f65ca | 14041 | object_64bit = 1; |
e379e5f3 L |
14042 | #ifndef TE_SOLARIS |
14043 | tls_get_addr = "__tls_get_addr"; | |
14044 | #endif | |
862be3fb | 14045 | disallow_64bit_reloc = 1; |
351f65ca L |
14046 | format = ELF_TARGET_FORMAT32; |
14047 | break; | |
4fa24527 | 14048 | } |
c085ab00 | 14049 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
14050 | { |
14051 | if (x86_elf_abi != I386_ABI) | |
14052 | as_fatal (_("Intel MCU is 32bit only")); | |
14053 | return ELF_TARGET_IAMCU_FORMAT; | |
14054 | } | |
8a9036a4 | 14055 | else |
351f65ca | 14056 | return format; |
3e73aa7c | 14057 | } |
e57f8c65 TG |
14058 | #endif |
14059 | #if defined (OBJ_MACH_O) | |
14060 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
14061 | if (flag_code == CODE_64BIT) |
14062 | { | |
14063 | use_rela_relocations = 1; | |
14064 | object_64bit = 1; | |
14065 | return "mach-o-x86-64"; | |
14066 | } | |
14067 | else | |
14068 | return "mach-o-i386"; | |
4c63da97 | 14069 | #endif |
252b5132 RH |
14070 | default: |
14071 | abort (); | |
14072 | return NULL; | |
14073 | } | |
14074 | } | |
14075 | ||
47926f60 | 14076 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 14077 | \f |
252b5132 | 14078 | symbolS * |
7016a5d5 | 14079 | md_undefined_symbol (char *name) |
252b5132 | 14080 | { |
18dc2407 ILT |
14081 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
14082 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
14083 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
14084 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
14085 | { |
14086 | if (!GOT_symbol) | |
14087 | { | |
14088 | if (symbol_find (name)) | |
14089 | as_bad (_("GOT already in symbol table")); | |
14090 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 14091 | &zero_address_frag, 0); |
24eab124 AM |
14092 | }; |
14093 | return GOT_symbol; | |
14094 | } | |
252b5132 RH |
14095 | return 0; |
14096 | } | |
14097 | ||
14098 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 14099 | |
252b5132 | 14100 | valueT |
7016a5d5 | 14101 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 14102 | { |
4c63da97 AM |
14103 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
14104 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
14105 | { | |
14106 | /* For a.out, force the section size to be aligned. If we don't do | |
14107 | this, BFD will align it for us, but it will not write out the | |
14108 | final bytes of the section. This may be a bug in BFD, but it is | |
14109 | easier to fix it here since that is how the other a.out targets | |
14110 | work. */ | |
14111 | int align; | |
14112 | ||
fd361982 | 14113 | align = bfd_section_alignment (segment); |
8d3842cd | 14114 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 14115 | } |
252b5132 RH |
14116 | #endif |
14117 | ||
14118 | return size; | |
14119 | } | |
14120 | ||
14121 | /* On the i386, PC-relative offsets are relative to the start of the | |
14122 | next instruction. That is, the address of the offset, plus its | |
14123 | size, since the offset is always the last part of the insn. */ | |
14124 | ||
14125 | long | |
e3bb37b5 | 14126 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
14127 | { |
14128 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
14129 | } | |
14130 | ||
14131 | #ifndef I386COFF | |
14132 | ||
14133 | static void | |
e3bb37b5 | 14134 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14135 | { |
29b0f896 | 14136 | int temp; |
252b5132 | 14137 | |
8a75718c JB |
14138 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14139 | if (IS_ELF) | |
14140 | obj_elf_section_change_hook (); | |
14141 | #endif | |
252b5132 RH |
14142 | temp = get_absolute_expression (); |
14143 | subseg_set (bss_section, (subsegT) temp); | |
14144 | demand_empty_rest_of_line (); | |
14145 | } | |
14146 | ||
14147 | #endif | |
14148 | ||
e379e5f3 L |
14149 | /* Remember constant directive. */ |
14150 | ||
14151 | void | |
14152 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
14153 | { | |
14154 | if (last_insn.kind != last_insn_directive | |
14155 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
14156 | { | |
14157 | last_insn.seg = now_seg; | |
14158 | last_insn.kind = last_insn_directive; | |
14159 | last_insn.name = "constant directive"; | |
14160 | last_insn.file = as_where (&last_insn.line); | |
ae531041 L |
14161 | if (lfence_before_ret != lfence_before_ret_none) |
14162 | { | |
14163 | if (lfence_before_indirect_branch != lfence_branch_none) | |
14164 | as_warn (_("constant directive skips -mlfence-before-ret " | |
14165 | "and -mlfence-before-indirect-branch")); | |
14166 | else | |
14167 | as_warn (_("constant directive skips -mlfence-before-ret")); | |
14168 | } | |
14169 | else if (lfence_before_indirect_branch != lfence_branch_none) | |
14170 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); | |
e379e5f3 L |
14171 | } |
14172 | } | |
14173 | ||
3abbafc2 | 14174 | int |
e3bb37b5 | 14175 | i386_validate_fix (fixS *fixp) |
252b5132 | 14176 | { |
e52a16f2 JB |
14177 | if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section) |
14178 | { | |
14179 | reloc_howto_type *howto; | |
14180 | ||
14181 | howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
14182 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14183 | _("invalid %s relocation against register"), | |
14184 | howto ? howto->name : "<unknown>"); | |
14185 | return 0; | |
14186 | } | |
14187 | ||
3abbafc2 JB |
14188 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14189 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
14190 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
14191 | return IS_ELF && fixp->fx_addsy | |
14192 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
14193 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
14194 | #endif | |
14195 | ||
02a86693 | 14196 | if (fixp->fx_subsy) |
252b5132 | 14197 | { |
02a86693 | 14198 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 14199 | { |
02a86693 L |
14200 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
14201 | { | |
14202 | if (!object_64bit) | |
14203 | abort (); | |
14204 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14205 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
14206 | fixp->fx_r_type = (fixp->fx_tcbit |
14207 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
14208 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
14209 | else |
14210 | #endif | |
14211 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
14212 | } | |
d6ab8113 | 14213 | else |
02a86693 L |
14214 | { |
14215 | if (!object_64bit) | |
14216 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
14217 | else | |
14218 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
14219 | } | |
14220 | fixp->fx_subsy = 0; | |
23df1078 | 14221 | } |
252b5132 | 14222 | } |
02a86693 | 14223 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 14224 | else |
02a86693 | 14225 | { |
2585b7a5 L |
14226 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
14227 | to section. Since PLT32 relocation must be against symbols, | |
14228 | turn such PLT32 relocation into PC32 relocation. */ | |
14229 | if (fixp->fx_addsy | |
14230 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
14231 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
14232 | && symbol_section_p (fixp->fx_addsy)) | |
14233 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
14234 | if (!object_64bit) | |
14235 | { | |
14236 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
14237 | && fixp->fx_tcbit2) | |
14238 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
14239 | } | |
02a86693 L |
14240 | } |
14241 | #endif | |
3abbafc2 JB |
14242 | |
14243 | return 1; | |
252b5132 RH |
14244 | } |
14245 | ||
252b5132 | 14246 | arelent * |
7016a5d5 | 14247 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14248 | { |
14249 | arelent *rel; | |
14250 | bfd_reloc_code_real_type code; | |
14251 | ||
14252 | switch (fixp->fx_r_type) | |
14253 | { | |
8ce3d284 | 14254 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
14255 | symbolS *sym; |
14256 | ||
8fd4256d L |
14257 | case BFD_RELOC_SIZE32: |
14258 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
14259 | if (fixp->fx_addsy |
14260 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
14261 | && (!fixp->fx_subsy | |
14262 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
14263 | sym = fixp->fx_addsy; | |
14264 | else if (fixp->fx_subsy | |
14265 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
14266 | && (!fixp->fx_addsy | |
14267 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
14268 | sym = fixp->fx_subsy; | |
14269 | else | |
14270 | sym = NULL; | |
14271 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
14272 | { |
14273 | /* Resolve size relocation against local symbol to size of | |
14274 | the symbol plus addend. */ | |
3abbafc2 | 14275 | valueT value = S_GET_SIZE (sym); |
44f87162 | 14276 | |
3abbafc2 JB |
14277 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
14278 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
14279 | if (sym == fixp->fx_subsy) | |
14280 | { | |
14281 | value = -value; | |
14282 | if (fixp->fx_addsy) | |
14283 | value += S_GET_VALUE (fixp->fx_addsy); | |
14284 | } | |
14285 | else if (fixp->fx_subsy) | |
14286 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 14287 | value += fixp->fx_offset; |
8fd4256d | 14288 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 14289 | && object_64bit |
8fd4256d L |
14290 | && !fits_in_unsigned_long (value)) |
14291 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14292 | _("symbol size computation overflow")); | |
14293 | fixp->fx_addsy = NULL; | |
14294 | fixp->fx_subsy = NULL; | |
14295 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
14296 | return NULL; | |
14297 | } | |
3abbafc2 JB |
14298 | if (!fixp->fx_addsy || fixp->fx_subsy) |
14299 | { | |
14300 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14301 | "unsupported expression involving @size"); | |
14302 | return NULL; | |
14303 | } | |
8ce3d284 | 14304 | #endif |
1a0670f3 | 14305 | /* Fall through. */ |
8fd4256d | 14306 | |
3e73aa7c JH |
14307 | case BFD_RELOC_X86_64_PLT32: |
14308 | case BFD_RELOC_X86_64_GOT32: | |
14309 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14310 | case BFD_RELOC_X86_64_GOTPCRELX: |
14311 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
14312 | case BFD_RELOC_386_PLT32: |
14313 | case BFD_RELOC_386_GOT32: | |
02a86693 | 14314 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
14315 | case BFD_RELOC_386_GOTOFF: |
14316 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
14317 | case BFD_RELOC_386_TLS_GD: |
14318 | case BFD_RELOC_386_TLS_LDM: | |
14319 | case BFD_RELOC_386_TLS_LDO_32: | |
14320 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
14321 | case BFD_RELOC_386_TLS_IE: |
14322 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
14323 | case BFD_RELOC_386_TLS_LE_32: |
14324 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
14325 | case BFD_RELOC_386_TLS_GOTDESC: |
14326 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
14327 | case BFD_RELOC_X86_64_TLSGD: |
14328 | case BFD_RELOC_X86_64_TLSLD: | |
14329 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 14330 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
14331 | case BFD_RELOC_X86_64_GOTTPOFF: |
14332 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
14333 | case BFD_RELOC_X86_64_TPOFF64: |
14334 | case BFD_RELOC_X86_64_GOTOFF64: | |
14335 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
14336 | case BFD_RELOC_X86_64_GOT64: |
14337 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14338 | case BFD_RELOC_X86_64_GOTPC64: | |
14339 | case BFD_RELOC_X86_64_GOTPLT64: | |
14340 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
14341 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14342 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
14343 | case BFD_RELOC_RVA: |
14344 | case BFD_RELOC_VTABLE_ENTRY: | |
14345 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
14346 | #ifdef TE_PE |
14347 | case BFD_RELOC_32_SECREL: | |
145667f8 | 14348 | case BFD_RELOC_16_SECIDX: |
6482c264 | 14349 | #endif |
252b5132 RH |
14350 | code = fixp->fx_r_type; |
14351 | break; | |
dbbaec26 L |
14352 | case BFD_RELOC_X86_64_32S: |
14353 | if (!fixp->fx_pcrel) | |
14354 | { | |
14355 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
14356 | code = fixp->fx_r_type; | |
14357 | break; | |
14358 | } | |
1a0670f3 | 14359 | /* Fall through. */ |
252b5132 | 14360 | default: |
93382f6d | 14361 | if (fixp->fx_pcrel) |
252b5132 | 14362 | { |
93382f6d AM |
14363 | switch (fixp->fx_size) |
14364 | { | |
14365 | default: | |
b091f402 AM |
14366 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14367 | _("can not do %d byte pc-relative relocation"), | |
14368 | fixp->fx_size); | |
93382f6d AM |
14369 | code = BFD_RELOC_32_PCREL; |
14370 | break; | |
14371 | case 1: code = BFD_RELOC_8_PCREL; break; | |
14372 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 14373 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
14374 | #ifdef BFD64 |
14375 | case 8: code = BFD_RELOC_64_PCREL; break; | |
14376 | #endif | |
93382f6d AM |
14377 | } |
14378 | } | |
14379 | else | |
14380 | { | |
14381 | switch (fixp->fx_size) | |
14382 | { | |
14383 | default: | |
b091f402 AM |
14384 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14385 | _("can not do %d byte relocation"), | |
14386 | fixp->fx_size); | |
93382f6d AM |
14387 | code = BFD_RELOC_32; |
14388 | break; | |
14389 | case 1: code = BFD_RELOC_8; break; | |
14390 | case 2: code = BFD_RELOC_16; break; | |
14391 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 14392 | #ifdef BFD64 |
3e73aa7c | 14393 | case 8: code = BFD_RELOC_64; break; |
937149dd | 14394 | #endif |
93382f6d | 14395 | } |
252b5132 RH |
14396 | } |
14397 | break; | |
14398 | } | |
252b5132 | 14399 | |
d182319b JB |
14400 | if ((code == BFD_RELOC_32 |
14401 | || code == BFD_RELOC_32_PCREL | |
14402 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
14403 | && GOT_symbol |
14404 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 14405 | { |
4fa24527 | 14406 | if (!object_64bit) |
d6ab8113 JB |
14407 | code = BFD_RELOC_386_GOTPC; |
14408 | else | |
14409 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 14410 | } |
7b81dfbb AJ |
14411 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
14412 | && GOT_symbol | |
14413 | && fixp->fx_addsy == GOT_symbol) | |
14414 | { | |
14415 | code = BFD_RELOC_X86_64_GOTPC64; | |
14416 | } | |
252b5132 | 14417 | |
add39d23 TS |
14418 | rel = XNEW (arelent); |
14419 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 14420 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
14421 | |
14422 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 14423 | |
3e73aa7c JH |
14424 | if (!use_rela_relocations) |
14425 | { | |
14426 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
14427 | vtable entry to be used in the relocation's section offset. */ | |
14428 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14429 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
14430 | #if defined (OBJ_COFF) && defined (TE_PE) |
14431 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
14432 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
14433 | else | |
14434 | #endif | |
c6682705 | 14435 | rel->addend = 0; |
3e73aa7c JH |
14436 | } |
14437 | /* Use the rela in 64bit mode. */ | |
252b5132 | 14438 | else |
3e73aa7c | 14439 | { |
862be3fb L |
14440 | if (disallow_64bit_reloc) |
14441 | switch (code) | |
14442 | { | |
862be3fb L |
14443 | case BFD_RELOC_X86_64_DTPOFF64: |
14444 | case BFD_RELOC_X86_64_TPOFF64: | |
14445 | case BFD_RELOC_64_PCREL: | |
14446 | case BFD_RELOC_X86_64_GOTOFF64: | |
14447 | case BFD_RELOC_X86_64_GOT64: | |
14448 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14449 | case BFD_RELOC_X86_64_GOTPC64: | |
14450 | case BFD_RELOC_X86_64_GOTPLT64: | |
14451 | case BFD_RELOC_X86_64_PLTOFF64: | |
14452 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14453 | _("cannot represent relocation type %s in x32 mode"), | |
14454 | bfd_get_reloc_code_name (code)); | |
14455 | break; | |
14456 | default: | |
14457 | break; | |
14458 | } | |
14459 | ||
062cd5e7 AS |
14460 | if (!fixp->fx_pcrel) |
14461 | rel->addend = fixp->fx_offset; | |
14462 | else | |
14463 | switch (code) | |
14464 | { | |
14465 | case BFD_RELOC_X86_64_PLT32: | |
14466 | case BFD_RELOC_X86_64_GOT32: | |
14467 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14468 | case BFD_RELOC_X86_64_GOTPCRELX: |
14469 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
14470 | case BFD_RELOC_X86_64_TLSGD: |
14471 | case BFD_RELOC_X86_64_TLSLD: | |
14472 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
14473 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14474 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
14475 | rel->addend = fixp->fx_offset - fixp->fx_size; |
14476 | break; | |
14477 | default: | |
14478 | rel->addend = (section->vma | |
14479 | - fixp->fx_size | |
14480 | + fixp->fx_addnumber | |
14481 | + md_pcrel_from (fixp)); | |
14482 | break; | |
14483 | } | |
3e73aa7c JH |
14484 | } |
14485 | ||
252b5132 RH |
14486 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
14487 | if (rel->howto == NULL) | |
14488 | { | |
14489 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 14490 | _("cannot represent relocation type %s"), |
252b5132 RH |
14491 | bfd_get_reloc_code_name (code)); |
14492 | /* Set howto to a garbage value so that we can keep going. */ | |
14493 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 14494 | gas_assert (rel->howto != NULL); |
252b5132 RH |
14495 | } |
14496 | ||
14497 | return rel; | |
14498 | } | |
14499 | ||
ee86248c | 14500 | #include "tc-i386-intel.c" |
54cfded0 | 14501 | |
a60de03c JB |
14502 | void |
14503 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 14504 | { |
a60de03c JB |
14505 | int saved_naked_reg; |
14506 | char saved_register_dot; | |
54cfded0 | 14507 | |
a60de03c JB |
14508 | saved_naked_reg = allow_naked_reg; |
14509 | allow_naked_reg = 1; | |
14510 | saved_register_dot = register_chars['.']; | |
14511 | register_chars['.'] = '.'; | |
14512 | allow_pseudo_reg = 1; | |
14513 | expression_and_evaluate (exp); | |
14514 | allow_pseudo_reg = 0; | |
14515 | register_chars['.'] = saved_register_dot; | |
14516 | allow_naked_reg = saved_naked_reg; | |
14517 | ||
e96d56a1 | 14518 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 14519 | { |
a60de03c JB |
14520 | if ((addressT) exp->X_add_number < i386_regtab_size) |
14521 | { | |
14522 | exp->X_op = O_constant; | |
14523 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
14524 | .dw2_regnum[flag_code >> 1]; | |
14525 | } | |
14526 | else | |
14527 | exp->X_op = O_illegal; | |
54cfded0 | 14528 | } |
54cfded0 AM |
14529 | } |
14530 | ||
14531 | void | |
14532 | tc_x86_frame_initial_instructions (void) | |
14533 | { | |
a60de03c JB |
14534 | static unsigned int sp_regno[2]; |
14535 | ||
14536 | if (!sp_regno[flag_code >> 1]) | |
14537 | { | |
14538 | char *saved_input = input_line_pointer; | |
14539 | char sp[][4] = {"esp", "rsp"}; | |
14540 | expressionS exp; | |
a4447b93 | 14541 | |
a60de03c JB |
14542 | input_line_pointer = sp[flag_code >> 1]; |
14543 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 14544 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
14545 | sp_regno[flag_code >> 1] = exp.X_add_number; |
14546 | input_line_pointer = saved_input; | |
14547 | } | |
a4447b93 | 14548 | |
61ff971f L |
14549 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
14550 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 14551 | } |
d2b2c203 | 14552 | |
d7921315 L |
14553 | int |
14554 | x86_dwarf2_addr_size (void) | |
14555 | { | |
14556 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
14557 | if (x86_elf_abi == X86_64_X32_ABI) | |
14558 | return 4; | |
14559 | #endif | |
14560 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
14561 | } | |
14562 | ||
d2b2c203 DJ |
14563 | int |
14564 | i386_elf_section_type (const char *str, size_t len) | |
14565 | { | |
14566 | if (flag_code == CODE_64BIT | |
14567 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 14568 | && startswith (str, "unwind")) |
d2b2c203 DJ |
14569 | return SHT_X86_64_UNWIND; |
14570 | ||
14571 | return -1; | |
14572 | } | |
bb41ade5 | 14573 | |
ad5fec3b EB |
14574 | #ifdef TE_SOLARIS |
14575 | void | |
14576 | i386_solaris_fix_up_eh_frame (segT sec) | |
14577 | { | |
14578 | if (flag_code == CODE_64BIT) | |
14579 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
14580 | } | |
14581 | #endif | |
14582 | ||
bb41ade5 AM |
14583 | #ifdef TE_PE |
14584 | void | |
14585 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
14586 | { | |
91d6fa6a | 14587 | expressionS exp; |
bb41ade5 | 14588 | |
91d6fa6a NC |
14589 | exp.X_op = O_secrel; |
14590 | exp.X_add_symbol = symbol; | |
14591 | exp.X_add_number = 0; | |
14592 | emit_expr (&exp, size); | |
bb41ade5 AM |
14593 | } |
14594 | #endif | |
3b22753a L |
14595 | |
14596 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14597 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
14598 | ||
01e1a5bc | 14599 | bfd_vma |
6d4af3c2 | 14600 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
14601 | { |
14602 | if (flag_code == CODE_64BIT) | |
14603 | { | |
14604 | if (letter == 'l') | |
14605 | return SHF_X86_64_LARGE; | |
14606 | ||
8f3bae45 | 14607 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 14608 | } |
3b22753a | 14609 | else |
8f3bae45 | 14610 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
14611 | return -1; |
14612 | } | |
14613 | ||
01e1a5bc | 14614 | bfd_vma |
3b22753a L |
14615 | x86_64_section_word (char *str, size_t len) |
14616 | { | |
08dedd66 | 14617 | if (len == 5 && flag_code == CODE_64BIT && startswith (str, "large")) |
3b22753a L |
14618 | return SHF_X86_64_LARGE; |
14619 | ||
14620 | return -1; | |
14621 | } | |
14622 | ||
14623 | static void | |
14624 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
14625 | { | |
14626 | if (flag_code != CODE_64BIT) | |
14627 | { | |
14628 | s_comm_internal (0, elf_common_parse); | |
14629 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
14630 | } | |
14631 | else | |
14632 | { | |
14633 | static segT lbss_section; | |
14634 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
14635 | asection *saved_bss_section = bss_section; | |
14636 | ||
14637 | if (lbss_section == NULL) | |
14638 | { | |
14639 | flagword applicable; | |
14640 | segT seg = now_seg; | |
14641 | subsegT subseg = now_subseg; | |
14642 | ||
14643 | /* The .lbss section is for local .largecomm symbols. */ | |
14644 | lbss_section = subseg_new (".lbss", 0); | |
14645 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 14646 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
14647 | seg_info (lbss_section)->bss = 1; |
14648 | ||
14649 | subseg_set (seg, subseg); | |
14650 | } | |
14651 | ||
14652 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
14653 | bss_section = lbss_section; | |
14654 | ||
14655 | s_comm_internal (0, elf_common_parse); | |
14656 | ||
14657 | elf_com_section_ptr = saved_com_section_ptr; | |
14658 | bss_section = saved_bss_section; | |
14659 | } | |
14660 | } | |
14661 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |