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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
d87bef3a | 2 | Copyright (C) 1989-2023 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
b52c4ee4 IB |
33 | #include "gen-sframe.h" |
34 | #include "sframe.h" | |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
5c139202 | 37 | #include "opcodes/i386-mnem.h" |
41fd2579 | 38 | #include <limits.h> |
41fd2579 | 39 | |
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
84 | |
85 | #define END_OF_INSN '\0' | |
86 | ||
05909f23 JB |
87 | #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } } |
88 | ||
79dec6b7 JB |
89 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
90 | #define commutative staticrounding | |
91 | ||
6305a203 L |
92 | /* |
93 | 'templates' is for grouping together 'template' structures for opcodes | |
94 | of the same name. This is only used for storing the insns in the grand | |
95 | ole hash table of insns. | |
96 | The templates themselves start at START and range up to (but not including) | |
97 | END. | |
98 | */ | |
99 | typedef struct | |
100 | { | |
d3ce72d0 NC |
101 | const insn_template *start; |
102 | const insn_template *end; | |
6305a203 L |
103 | } |
104 | templates; | |
105 | ||
106 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
107 | typedef struct | |
108 | { | |
109 | unsigned int regmem; /* codes register or memory operand */ | |
110 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
111 | unsigned int mode; /* how to interpret regmem & reg */ | |
112 | } | |
113 | modrm_byte; | |
114 | ||
115 | /* x86-64 extension prefix. */ | |
116 | typedef int rex_byte; | |
117 | ||
6305a203 L |
118 | /* 386 opcode byte to code indirect addressing. */ |
119 | typedef struct | |
120 | { | |
121 | unsigned base; | |
122 | unsigned index; | |
123 | unsigned scale; | |
124 | } | |
125 | sib_byte; | |
126 | ||
6305a203 L |
127 | /* x86 arch names, types and features */ |
128 | typedef struct | |
129 | { | |
130 | const char *name; /* arch name */ | |
6ceeed25 JB |
131 | unsigned int len:8; /* arch string length */ |
132 | bool skip:1; /* show_arch should skip this. */ | |
6305a203 | 133 | enum processor_type type; /* arch type */ |
ae89daec JB |
134 | i386_cpu_flags enable; /* cpu feature enable flags */ |
135 | i386_cpu_flags disable; /* cpu feature disable flags */ | |
6305a203 L |
136 | } |
137 | arch_entry; | |
138 | ||
78f12dd3 | 139 | static void update_code_flag (int, int); |
e3bb37b5 L |
140 | static void set_code_flag (int); |
141 | static void set_16bit_gcc_code_flag (int); | |
142 | static void set_intel_syntax (int); | |
1efbbeb4 | 143 | static void set_intel_mnemonic (int); |
db51cc60 | 144 | static void set_allow_index_reg (int); |
7bab8ab5 | 145 | static void set_check (int); |
e3bb37b5 | 146 | static void set_cpu_arch (int); |
6482c264 | 147 | #ifdef TE_PE |
e3bb37b5 | 148 | static void pe_directive_secrel (int); |
145667f8 | 149 | static void pe_directive_secidx (int); |
6482c264 | 150 | #endif |
e3bb37b5 L |
151 | static void signed_cons (int); |
152 | static char *output_invalid (int c); | |
ee86248c JB |
153 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
154 | const char *); | |
155 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
156 | const char *); | |
a7619375 | 157 | static int i386_att_operand (char *); |
e3bb37b5 | 158 | static int i386_intel_operand (char *, int); |
ee86248c JB |
159 | static int i386_intel_simplify (expressionS *); |
160 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 | 161 | static const reg_entry *parse_register (char *, char **); |
5317ad2c | 162 | static const char *parse_insn (const char *, char *); |
e3bb37b5 L |
163 | static char *parse_operands (char *, const char *); |
164 | static void swap_operands (void); | |
783c187b | 165 | static void swap_2_operands (unsigned int, unsigned int); |
48bcea9f | 166 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
167 | static void optimize_imm (void); |
168 | static void optimize_disp (void); | |
83b16ac6 | 169 | static const insn_template *match_template (char); |
e3bb37b5 L |
170 | static int check_string (void); |
171 | static int process_suffix (void); | |
172 | static int check_byte_reg (void); | |
173 | static int check_long_reg (void); | |
174 | static int check_qword_reg (void); | |
175 | static int check_word_reg (void); | |
176 | static int finalize_imm (void); | |
177 | static int process_operands (void); | |
5e042380 | 178 | static const reg_entry *build_modrm_byte (void); |
e3bb37b5 L |
179 | static void output_insn (void); |
180 | static void output_imm (fragS *, offsetT); | |
181 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 182 | #ifndef I386COFF |
e3bb37b5 | 183 | static void s_bss (int); |
252b5132 | 184 | #endif |
17d4e2a2 L |
185 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
186 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
187 | |
188 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
189 | static unsigned int x86_isa_1_used; | |
190 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
191 | static unsigned int x86_feature_2_used; | |
192 | /* Generate x86 used ISA and feature properties. */ | |
193 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 194 | #endif |
252b5132 | 195 | |
a847613f | 196 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 197 | |
8a6fb3f9 JB |
198 | /* parse_register() returns this when a register alias cannot be used. */ |
199 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
200 | { Dw2Inval, Dw2Inval } }; | |
201 | ||
34684862 | 202 | static const reg_entry *reg_eax; |
5e042380 JB |
203 | static const reg_entry *reg_ds; |
204 | static const reg_entry *reg_es; | |
205 | static const reg_entry *reg_ss; | |
6288d05f | 206 | static const reg_entry *reg_st0; |
6225c532 JB |
207 | static const reg_entry *reg_k0; |
208 | ||
c0f3af97 L |
209 | /* VEX prefix. */ |
210 | typedef struct | |
211 | { | |
43234a1e L |
212 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
213 | unsigned char bytes[4]; | |
c0f3af97 L |
214 | unsigned int length; |
215 | /* Destination or source register specifier. */ | |
216 | const reg_entry *register_specifier; | |
217 | } vex_prefix; | |
218 | ||
252b5132 | 219 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 220 | i386_insn. */ |
252b5132 | 221 | |
520dc8e8 AM |
222 | union i386_op |
223 | { | |
224 | expressionS *disps; | |
225 | expressionS *imms; | |
226 | const reg_entry *regs; | |
227 | }; | |
228 | ||
a65babc9 L |
229 | enum i386_error |
230 | { | |
b4d65f2d | 231 | no_error, /* Must be first. */ |
86e026a4 | 232 | operand_size_mismatch, |
a65babc9 L |
233 | operand_type_mismatch, |
234 | register_type_mismatch, | |
235 | number_of_operands_mismatch, | |
236 | invalid_instruction_suffix, | |
237 | bad_imm4, | |
a65babc9 L |
238 | unsupported_with_intel_mnemonic, |
239 | unsupported_syntax, | |
6c30d220 | 240 | unsupported, |
9db83a32 JB |
241 | unsupported_on_arch, |
242 | unsupported_64bit, | |
260cd341 | 243 | invalid_sib_address, |
6c30d220 | 244 | invalid_vsib_address, |
7bab8ab5 | 245 | invalid_vector_register_set, |
260cd341 | 246 | invalid_tmm_register_set, |
0cc78721 | 247 | invalid_dest_and_src_register_set, |
43234a1e L |
248 | unsupported_vector_index_register, |
249 | unsupported_broadcast, | |
43234a1e L |
250 | broadcast_needed, |
251 | unsupported_masking, | |
252 | mask_not_on_destination, | |
253 | no_default_mask, | |
254 | unsupported_rc_sae, | |
43234a1e | 255 | invalid_register_operand, |
a65babc9 L |
256 | }; |
257 | ||
252b5132 RH |
258 | struct _i386_insn |
259 | { | |
47926f60 | 260 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 261 | insn_template tm; |
252b5132 | 262 | |
7d5e4556 L |
263 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
264 | or qword, if given. */ | |
252b5132 RH |
265 | char suffix; |
266 | ||
9a182d04 JB |
267 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
268 | unsigned char opcode_length; | |
269 | ||
47926f60 | 270 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
271 | unsigned int operands; |
272 | ||
273 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
274 | of given register, displacement, memory operands and immediate | |
47926f60 | 275 | operands. */ |
252b5132 RH |
276 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
277 | ||
278 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 279 | use OP[i] for the corresponding operand. */ |
40fb9820 | 280 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 281 | |
520dc8e8 AM |
282 | /* Displacement expression, immediate expression, or register for each |
283 | operand. */ | |
284 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 285 | |
3e73aa7c JH |
286 | /* Flags for operands. */ |
287 | unsigned int flags[MAX_OPERANDS]; | |
288 | #define Operand_PCrel 1 | |
c48dadc9 | 289 | #define Operand_Mem 2 |
3e73aa7c | 290 | |
252b5132 | 291 | /* Relocation type for operand */ |
f86103b7 | 292 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 293 | |
252b5132 RH |
294 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
295 | the base index byte below. */ | |
296 | const reg_entry *base_reg; | |
297 | const reg_entry *index_reg; | |
298 | unsigned int log2_scale_factor; | |
299 | ||
300 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 301 | explicit segment overrides are given. */ |
5e042380 | 302 | const reg_entry *seg[2]; |
252b5132 RH |
303 | |
304 | /* PREFIX holds all the given prefix opcodes (usually null). | |
305 | PREFIXES is the number of prefix opcodes. */ | |
306 | unsigned int prefixes; | |
307 | unsigned char prefix[MAX_PREFIXES]; | |
308 | ||
50128d0c | 309 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 310 | bool short_form; |
50128d0c | 311 | |
6f2f06be | 312 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 313 | bool jumpabsolute; |
6f2f06be | 314 | |
a4d3acd2 JB |
315 | /* The operand to a branch insn indicates a far branch. */ |
316 | bool far_branch; | |
317 | ||
9373f275 L |
318 | /* There is a memory operand of (%dx) which should be only used |
319 | with input/output instructions. */ | |
320 | bool input_output_operand; | |
321 | ||
921eafea L |
322 | /* Extended states. */ |
323 | enum | |
324 | { | |
325 | /* Use MMX state. */ | |
326 | xstate_mmx = 1 << 0, | |
327 | /* Use XMM state. */ | |
328 | xstate_xmm = 1 << 1, | |
329 | /* Use YMM state. */ | |
330 | xstate_ymm = 1 << 2 | xstate_xmm, | |
331 | /* Use ZMM state. */ | |
332 | xstate_zmm = 1 << 3 | xstate_ymm, | |
333 | /* Use TMM state. */ | |
32930e4e L |
334 | xstate_tmm = 1 << 4, |
335 | /* Use MASK state. */ | |
336 | xstate_mask = 1 << 5 | |
921eafea | 337 | } xstate; |
260cd341 | 338 | |
e379e5f3 | 339 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 340 | bool has_gotpc_tls_reloc; |
e379e5f3 | 341 | |
252b5132 | 342 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 343 | addressing modes of this insn are encoded. */ |
252b5132 | 344 | modrm_byte rm; |
3e73aa7c | 345 | rex_byte rex; |
43234a1e | 346 | rex_byte vrex; |
252b5132 | 347 | sib_byte sib; |
c0f3af97 | 348 | vex_prefix vex; |
b6169b20 | 349 | |
6225c532 JB |
350 | /* Masking attributes. |
351 | ||
352 | The struct describes masking, applied to OPERAND in the instruction. | |
353 | REG is a pointer to the corresponding mask register. ZEROING tells | |
354 | whether merging or zeroing mask is used. */ | |
355 | struct Mask_Operation | |
356 | { | |
357 | const reg_entry *reg; | |
358 | unsigned int zeroing; | |
359 | /* The operand where this operation is associated. */ | |
360 | unsigned int operand; | |
361 | } mask; | |
43234a1e L |
362 | |
363 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
364 | struct RC_Operation |
365 | { | |
366 | enum rc_type | |
367 | { | |
368 | rc_none = -1, | |
369 | rne, | |
370 | rd, | |
371 | ru, | |
372 | rz, | |
373 | saeonly | |
374 | } type; | |
7063667e JB |
375 | /* In Intel syntax the operand modifier form is supposed to be used, but |
376 | we continue to accept the immediate forms as well. */ | |
377 | bool modifier; | |
ca5312a2 | 378 | } rounding; |
43234a1e | 379 | |
5273a3cd JB |
380 | /* Broadcasting attributes. |
381 | ||
382 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
383 | expresses the broadcast factor. */ | |
384 | struct Broadcast_Operation | |
385 | { | |
0cc78721 | 386 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */ |
5273a3cd JB |
387 | unsigned int type; |
388 | ||
389 | /* Index of broadcasted operand. */ | |
390 | unsigned int operand; | |
391 | ||
392 | /* Number of bytes to broadcast. */ | |
393 | unsigned int bytes; | |
394 | } broadcast; | |
43234a1e L |
395 | |
396 | /* Compressed disp8*N attribute. */ | |
397 | unsigned int memshift; | |
398 | ||
86fa6981 L |
399 | /* Prefer load or store in encoding. */ |
400 | enum | |
401 | { | |
402 | dir_encoding_default = 0, | |
403 | dir_encoding_load, | |
64c49ab3 JB |
404 | dir_encoding_store, |
405 | dir_encoding_swap | |
86fa6981 | 406 | } dir_encoding; |
891edac4 | 407 | |
41eb8e88 | 408 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
409 | enum |
410 | { | |
411 | disp_encoding_default = 0, | |
412 | disp_encoding_8bit, | |
41eb8e88 | 413 | disp_encoding_16bit, |
a501d77e L |
414 | disp_encoding_32bit |
415 | } disp_encoding; | |
f8a5c266 | 416 | |
6b6b6807 | 417 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 418 | bool rex_encoding; |
6b6b6807 | 419 | |
b6f8c7c4 | 420 | /* Disable instruction size optimization. */ |
5b7c81bd | 421 | bool no_optimize; |
b6f8c7c4 | 422 | |
86fa6981 L |
423 | /* How to encode vector instructions. */ |
424 | enum | |
425 | { | |
426 | vex_encoding_default = 0, | |
42e04b36 | 427 | vex_encoding_vex, |
86fa6981 | 428 | vex_encoding_vex3, |
da4977e0 JB |
429 | vex_encoding_evex, |
430 | vex_encoding_error | |
86fa6981 L |
431 | } vec_encoding; |
432 | ||
d5de92cf L |
433 | /* REP prefix. */ |
434 | const char *rep_prefix; | |
435 | ||
165de32a L |
436 | /* HLE prefix. */ |
437 | const char *hle_prefix; | |
42164a71 | 438 | |
7e8b059b L |
439 | /* Have BND prefix. */ |
440 | const char *bnd_prefix; | |
441 | ||
04ef582a L |
442 | /* Have NOTRACK prefix. */ |
443 | const char *notrack_prefix; | |
444 | ||
891edac4 | 445 | /* Error message. */ |
a65babc9 | 446 | enum i386_error error; |
252b5132 RH |
447 | }; |
448 | ||
449 | typedef struct _i386_insn i386_insn; | |
450 | ||
43234a1e L |
451 | /* Link RC type with corresponding string, that'll be looked for in |
452 | asm. */ | |
453 | struct RC_name | |
454 | { | |
455 | enum rc_type type; | |
456 | const char *name; | |
457 | unsigned int len; | |
458 | }; | |
459 | ||
460 | static const struct RC_name RC_NamesTable[] = | |
461 | { | |
462 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
463 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
464 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
465 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
466 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
467 | }; | |
468 | ||
3bfea8ba L |
469 | /* To be indexed by segment register number. */ |
470 | static const unsigned char i386_seg_prefixes[] = { | |
471 | ES_PREFIX_OPCODE, | |
472 | CS_PREFIX_OPCODE, | |
473 | SS_PREFIX_OPCODE, | |
474 | DS_PREFIX_OPCODE, | |
475 | FS_PREFIX_OPCODE, | |
476 | GS_PREFIX_OPCODE | |
477 | }; | |
478 | ||
252b5132 RH |
479 | /* List of chars besides those in app.c:symbol_chars that can start an |
480 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 481 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 482 | #ifdef LEX_AT |
32137342 NC |
483 | "@" |
484 | #endif | |
485 | #ifdef LEX_QM | |
486 | "?" | |
252b5132 | 487 | #endif |
32137342 | 488 | ; |
252b5132 | 489 | |
b3983e5f JB |
490 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
491 | && !defined (TE_GNU) \ | |
492 | && !defined (TE_LINUX) \ | |
d85e70a3 | 493 | && !defined (TE_Haiku) \ |
b3983e5f JB |
494 | && !defined (TE_FreeBSD) \ |
495 | && !defined (TE_DragonFly) \ | |
496 | && !defined (TE_NetBSD)) | |
252b5132 | 497 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
498 | pre-processor is disabled, these aren't very useful. The option |
499 | --divide will remove '/' from this list. */ | |
500 | const char *i386_comment_chars = "#/"; | |
501 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 502 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 503 | |
b3b91714 AM |
504 | #else |
505 | const char *i386_comment_chars = "#"; | |
506 | #define PREFIX_SEPARATOR '/' | |
507 | #endif | |
508 | ||
252b5132 RH |
509 | /* This array holds the chars that only start a comment at the beginning of |
510 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
511 | .line and .file directives will appear in the pre-processed output. |
512 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 513 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
514 | #NO_APP at the beginning of its output. |
515 | Also note that comments started like this one will always work if | |
252b5132 | 516 | '/' isn't otherwise defined. */ |
b3b91714 | 517 | const char line_comment_chars[] = "#/"; |
252b5132 | 518 | |
63a0b638 | 519 | const char line_separator_chars[] = ";"; |
252b5132 | 520 | |
ce8a8b2f AM |
521 | /* Chars that can be used to separate mant from exp in floating point |
522 | nums. */ | |
252b5132 RH |
523 | const char EXP_CHARS[] = "eE"; |
524 | ||
ce8a8b2f AM |
525 | /* Chars that mean this number is a floating point constant |
526 | As in 0f12.456 | |
527 | or 0d1.2345e12. */ | |
de133cf9 | 528 | const char FLT_CHARS[] = "fFdDxXhHbB"; |
252b5132 | 529 | |
ce8a8b2f | 530 | /* Tables for lexical analysis. */ |
252b5132 RH |
531 | static char mnemonic_chars[256]; |
532 | static char register_chars[256]; | |
533 | static char operand_chars[256]; | |
534 | static char identifier_chars[256]; | |
252b5132 | 535 | |
ce8a8b2f | 536 | /* Lexical macros. */ |
252b5132 RH |
537 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
538 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
539 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
540 | #define is_space_char(x) ((x) == ' ') | |
541 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
252b5132 | 542 | |
0234cb7c | 543 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
544 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
545 | ||
546 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
547 | effect this we maintain a stack of saved characters that we've smashed | |
548 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 549 | assembler instruction). */ |
252b5132 | 550 | static char save_stack[32]; |
ce8a8b2f | 551 | static char *save_stack_p; |
252b5132 RH |
552 | #define END_STRING_AND_SAVE(s) \ |
553 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
554 | #define RESTORE_END_STRING(s) \ | |
555 | do { *(s) = *--save_stack_p; } while (0) | |
556 | ||
47926f60 | 557 | /* The instruction we're assembling. */ |
252b5132 RH |
558 | static i386_insn i; |
559 | ||
560 | /* Possible templates for current insn. */ | |
561 | static const templates *current_templates; | |
562 | ||
31b2323c L |
563 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
564 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
565 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 566 | |
47926f60 | 567 | /* Current operand we are working on. */ |
ee86248c | 568 | static int this_operand = -1; |
252b5132 | 569 | |
3e73aa7c JH |
570 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
571 | these. */ | |
572 | ||
573 | enum flag_code { | |
574 | CODE_32BIT, | |
575 | CODE_16BIT, | |
576 | CODE_64BIT }; | |
577 | ||
578 | static enum flag_code flag_code; | |
4fa24527 | 579 | static unsigned int object_64bit; |
862be3fb | 580 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 581 | static int use_rela_relocations = 0; |
e379e5f3 L |
582 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
583 | static const char *tls_get_addr; | |
3e73aa7c | 584 | |
7af8ed2d NC |
585 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
586 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
587 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
588 | ||
351f65ca L |
589 | /* The ELF ABI to use. */ |
590 | enum x86_elf_abi | |
591 | { | |
592 | I386_ABI, | |
7f56bc95 L |
593 | X86_64_ABI, |
594 | X86_64_X32_ABI | |
351f65ca L |
595 | }; |
596 | ||
597 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 598 | #endif |
351f65ca | 599 | |
167ad85b TG |
600 | #if defined (TE_PE) || defined (TE_PEP) |
601 | /* Use big object file format. */ | |
602 | static int use_big_obj = 0; | |
603 | #endif | |
604 | ||
8dcea932 L |
605 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
606 | /* 1 if generating code for a shared library. */ | |
607 | static int shared = 0; | |
b52c4ee4 IB |
608 | |
609 | unsigned int x86_sframe_cfa_sp_reg; | |
3e3e792a | 610 | /* The other CFA base register for SFrame stack trace info. */ |
b52c4ee4 IB |
611 | unsigned int x86_sframe_cfa_fp_reg; |
612 | unsigned int x86_sframe_cfa_ra_reg; | |
613 | ||
8dcea932 L |
614 | #endif |
615 | ||
47926f60 KH |
616 | /* 1 for intel syntax, |
617 | 0 if att syntax. */ | |
618 | static int intel_syntax = 0; | |
252b5132 | 619 | |
4b5aaf5f L |
620 | static enum x86_64_isa |
621 | { | |
622 | amd64 = 1, /* AMD64 ISA. */ | |
623 | intel64 /* Intel64 ISA. */ | |
624 | } isa64; | |
e89c5eaa | 625 | |
1efbbeb4 L |
626 | /* 1 for intel mnemonic, |
627 | 0 if att mnemonic. */ | |
628 | static int intel_mnemonic = !SYSV386_COMPAT; | |
629 | ||
a60de03c JB |
630 | /* 1 if pseudo registers are permitted. */ |
631 | static int allow_pseudo_reg = 0; | |
632 | ||
47926f60 KH |
633 | /* 1 if register prefix % not required. */ |
634 | static int allow_naked_reg = 0; | |
252b5132 | 635 | |
33eaf5de | 636 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
637 | instructions supporting it, even if this prefix wasn't specified |
638 | explicitly. */ | |
639 | static int add_bnd_prefix = 0; | |
640 | ||
ba104c83 | 641 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
642 | static int allow_index_reg = 0; |
643 | ||
d022bddd IT |
644 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
645 | specified explicitly. */ | |
646 | static int omit_lock_prefix = 0; | |
647 | ||
e4e00185 AS |
648 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
649 | "lock addl $0, (%{re}sp)". */ | |
650 | static int avoid_fence = 0; | |
651 | ||
ae531041 L |
652 | /* 1 if lfence should be inserted after every load. */ |
653 | static int lfence_after_load = 0; | |
654 | ||
655 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
656 | static enum lfence_before_indirect_branch_kind | |
657 | { | |
658 | lfence_branch_none = 0, | |
659 | lfence_branch_register, | |
660 | lfence_branch_memory, | |
661 | lfence_branch_all | |
662 | } | |
663 | lfence_before_indirect_branch; | |
664 | ||
665 | /* Non-zero if lfence should be inserted before ret. */ | |
666 | static enum lfence_before_ret_kind | |
667 | { | |
668 | lfence_before_ret_none = 0, | |
669 | lfence_before_ret_not, | |
a09f656b | 670 | lfence_before_ret_or, |
671 | lfence_before_ret_shl | |
ae531041 L |
672 | } |
673 | lfence_before_ret; | |
674 | ||
675 | /* Types of previous instruction is .byte or prefix. */ | |
e379e5f3 L |
676 | static struct |
677 | { | |
678 | segT seg; | |
679 | const char *file; | |
680 | const char *name; | |
681 | unsigned int line; | |
682 | enum last_insn_kind | |
683 | { | |
684 | last_insn_other = 0, | |
685 | last_insn_directive, | |
686 | last_insn_prefix | |
687 | } kind; | |
688 | } last_insn; | |
689 | ||
0cb4071e L |
690 | /* 1 if the assembler should generate relax relocations. */ |
691 | ||
692 | static int generate_relax_relocations | |
693 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
694 | ||
7bab8ab5 | 695 | static enum check_kind |
daf50ae7 | 696 | { |
7bab8ab5 JB |
697 | check_none = 0, |
698 | check_warning, | |
699 | check_error | |
daf50ae7 | 700 | } |
7bab8ab5 | 701 | sse_check, operand_check = check_warning; |
daf50ae7 | 702 | |
e379e5f3 L |
703 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
704 | static int align_branch_power = 0; | |
705 | ||
706 | /* Types of branches to align. */ | |
707 | enum align_branch_kind | |
708 | { | |
709 | align_branch_none = 0, | |
710 | align_branch_jcc = 1, | |
711 | align_branch_fused = 2, | |
712 | align_branch_jmp = 3, | |
713 | align_branch_call = 4, | |
714 | align_branch_indirect = 5, | |
715 | align_branch_ret = 6 | |
716 | }; | |
717 | ||
718 | /* Type bits of branches to align. */ | |
719 | enum align_branch_bit | |
720 | { | |
721 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
722 | align_branch_fused_bit = 1 << align_branch_fused, | |
723 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
724 | align_branch_call_bit = 1 << align_branch_call, | |
725 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
726 | align_branch_ret_bit = 1 << align_branch_ret | |
727 | }; | |
728 | ||
729 | static unsigned int align_branch = (align_branch_jcc_bit | |
730 | | align_branch_fused_bit | |
731 | | align_branch_jmp_bit); | |
732 | ||
79d72f45 HL |
733 | /* Types of condition jump used by macro-fusion. */ |
734 | enum mf_jcc_kind | |
735 | { | |
736 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
737 | mf_jcc_jc, /* base opcode 0x72 */ | |
738 | mf_jcc_je, /* base opcode 0x74 */ | |
739 | mf_jcc_jna, /* base opcode 0x76 */ | |
740 | mf_jcc_js, /* base opcode 0x78 */ | |
741 | mf_jcc_jp, /* base opcode 0x7a */ | |
742 | mf_jcc_jl, /* base opcode 0x7c */ | |
743 | mf_jcc_jle, /* base opcode 0x7e */ | |
744 | }; | |
745 | ||
746 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
747 | enum mf_cmp_kind | |
748 | { | |
749 | mf_cmp_test_and, /* test/cmp */ | |
750 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
751 | mf_cmp_incdec /* inc/dec */ | |
752 | }; | |
753 | ||
e379e5f3 L |
754 | /* The maximum padding size for fused jcc. CMP like instruction can |
755 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
756 | prefixes. */ | |
757 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
758 | ||
759 | /* The maximum number of prefixes added for an instruction. */ | |
760 | static unsigned int align_branch_prefix_size = 5; | |
761 | ||
b6f8c7c4 L |
762 | /* Optimization: |
763 | 1. Clear the REX_W bit with register operand if possible. | |
764 | 2. Above plus use 128bit vector instruction to clear the full vector | |
765 | register. | |
766 | */ | |
767 | static int optimize = 0; | |
768 | ||
769 | /* Optimization: | |
770 | 1. Clear the REX_W bit with register operand if possible. | |
771 | 2. Above plus use 128bit vector instruction to clear the full vector | |
772 | register. | |
773 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
774 | "testb $imm7,%r8". | |
775 | */ | |
776 | static int optimize_for_space = 0; | |
777 | ||
2ca3ace5 L |
778 | /* Register prefix used for error message. */ |
779 | static const char *register_prefix = "%"; | |
780 | ||
47926f60 KH |
781 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
782 | leave, push, and pop instructions so that gcc has the same stack | |
783 | frame as in 32 bit mode. */ | |
784 | static char stackop_size = '\0'; | |
eecb386c | 785 | |
12b55ccc L |
786 | /* Non-zero to optimize code alignment. */ |
787 | int optimize_align_code = 1; | |
788 | ||
47926f60 KH |
789 | /* Non-zero to quieten some warnings. */ |
790 | static int quiet_warnings = 0; | |
a38cf1db | 791 | |
d59a54c2 JB |
792 | /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */ |
793 | static bool pre_386_16bit_warned; | |
794 | ||
47926f60 KH |
795 | /* CPU name. */ |
796 | static const char *cpu_arch_name = NULL; | |
6305a203 | 797 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 798 | |
47926f60 | 799 | /* CPU feature flags. */ |
40fb9820 L |
800 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
801 | ||
ccc9c027 L |
802 | /* If we have selected a cpu we are generating instructions for. */ |
803 | static int cpu_arch_tune_set = 0; | |
804 | ||
9103f4f4 | 805 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 806 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
807 | |
808 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 809 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 810 | |
ccc9c027 | 811 | /* CPU instruction set architecture used. */ |
fbf3f584 | 812 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 813 | |
9103f4f4 | 814 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 815 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 816 | |
fddf5b5b AM |
817 | /* If set, conditional jumps are not automatically promoted to handle |
818 | larger than a byte offset. */ | |
f68697e8 | 819 | static bool no_cond_jump_promotion = false; |
fddf5b5b | 820 | |
c0f3af97 L |
821 | /* Encode SSE instructions with VEX prefix. */ |
822 | static unsigned int sse2avx; | |
823 | ||
c8480b58 L |
824 | /* Encode aligned vector move as unaligned vector move. */ |
825 | static unsigned int use_unaligned_vector_move; | |
826 | ||
539f890d L |
827 | /* Encode scalar AVX instructions with specific vector length. */ |
828 | static enum | |
829 | { | |
830 | vex128 = 0, | |
831 | vex256 | |
832 | } avxscalar; | |
833 | ||
03751133 L |
834 | /* Encode VEX WIG instructions with specific vex.w. */ |
835 | static enum | |
836 | { | |
837 | vexw0 = 0, | |
838 | vexw1 | |
839 | } vexwig; | |
840 | ||
43234a1e L |
841 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
842 | static enum | |
843 | { | |
844 | evexl128 = 0, | |
845 | evexl256, | |
846 | evexl512 | |
847 | } evexlig; | |
848 | ||
849 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
850 | static enum | |
851 | { | |
852 | evexw0 = 0, | |
853 | evexw1 | |
854 | } evexwig; | |
855 | ||
d3d3c6db IT |
856 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
857 | static enum rc_type evexrcig = rne; | |
858 | ||
29b0f896 | 859 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 860 | static symbolS *GOT_symbol; |
29b0f896 | 861 | |
a4447b93 RH |
862 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
863 | unsigned int x86_dwarf2_return_column; | |
864 | ||
865 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
866 | int x86_cie_data_alignment; | |
867 | ||
252b5132 | 868 | /* Interface to relax_segment. |
fddf5b5b AM |
869 | There are 3 major relax states for 386 jump insns because the |
870 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
871 | figuring out what sort of jump to choose to reach a given label. |
872 | ||
873 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
874 | branches which are handled by md_estimate_size_before_relax() and | |
875 | i386_generic_table_relax_frag(). */ | |
252b5132 | 876 | |
47926f60 | 877 | /* Types. */ |
93c2a809 AM |
878 | #define UNCOND_JUMP 0 |
879 | #define COND_JUMP 1 | |
880 | #define COND_JUMP86 2 | |
e379e5f3 L |
881 | #define BRANCH_PADDING 3 |
882 | #define BRANCH_PREFIX 4 | |
883 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 884 | |
47926f60 | 885 | /* Sizes. */ |
252b5132 RH |
886 | #define CODE16 1 |
887 | #define SMALL 0 | |
29b0f896 | 888 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 889 | #define BIG 2 |
29b0f896 | 890 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
891 | |
892 | #ifndef INLINE | |
893 | #ifdef __GNUC__ | |
894 | #define INLINE __inline__ | |
895 | #else | |
896 | #define INLINE | |
897 | #endif | |
898 | #endif | |
899 | ||
fddf5b5b AM |
900 | #define ENCODE_RELAX_STATE(type, size) \ |
901 | ((relax_substateT) (((type) << 2) | (size))) | |
902 | #define TYPE_FROM_RELAX_STATE(s) \ | |
903 | ((s) >> 2) | |
904 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
905 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
906 | |
907 | /* This table is used by relax_frag to promote short jumps to long | |
908 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
909 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
910 | don't allow a short jump in a 32 bit code segment to be promoted to | |
911 | a 16 bit offset jump because it's slower (requires data size | |
912 | prefix), and doesn't work, unless the destination is in the bottom | |
913 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
914 | ||
915 | const relax_typeS md_relax_table[] = | |
916 | { | |
24eab124 AM |
917 | /* The fields are: |
918 | 1) most positive reach of this state, | |
919 | 2) most negative reach of this state, | |
93c2a809 | 920 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 921 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 922 | |
fddf5b5b | 923 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
924 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
925 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
926 | /* dword jmp adds 4 bytes to frag: | |
927 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 928 | {0, 0, 4, 0}, |
93c2a809 AM |
929 | /* word jmp adds 2 byte2 to frag: |
930 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
931 | {0, 0, 2, 0}, |
932 | ||
93c2a809 AM |
933 | /* COND_JUMP states. */ |
934 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
935 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
936 | /* dword conditionals adds 5 bytes to frag: | |
937 | 1 extra opcode byte, 4 displacement bytes. */ | |
938 | {0, 0, 5, 0}, | |
fddf5b5b | 939 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
940 | 1 extra opcode byte, 2 displacement bytes. */ |
941 | {0, 0, 3, 0}, | |
942 | ||
943 | /* COND_JUMP86 states. */ | |
944 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
945 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
946 | /* dword conditionals adds 5 bytes to frag: | |
947 | 1 extra opcode byte, 4 displacement bytes. */ | |
948 | {0, 0, 5, 0}, | |
949 | /* word conditionals add 4 bytes to frag: | |
950 | 1 displacement byte and a 3 byte long branch insn. */ | |
951 | {0, 0, 4, 0} | |
252b5132 RH |
952 | }; |
953 | ||
6ceeed25 | 954 | #define ARCH(n, t, f, s) \ |
ae89daec JB |
955 | { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, CPU_ ## f ## _FLAGS, \ |
956 | CPU_NONE_FLAGS } | |
957 | #define SUBARCH(n, e, d, s) \ | |
958 | { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, CPU_ ## e ## _FLAGS, \ | |
959 | CPU_ ## d ## _FLAGS } | |
6ceeed25 | 960 | |
9103f4f4 L |
961 | static const arch_entry cpu_arch[] = |
962 | { | |
3ce2ebcf JB |
963 | /* Do not replace the first two entries - i386_target_format() and |
964 | set_cpu_arch() rely on them being there in this order. */ | |
6ceeed25 JB |
965 | ARCH (generic32, GENERIC32, GENERIC32, false), |
966 | ARCH (generic64, GENERIC64, GENERIC64, false), | |
967 | ARCH (i8086, UNKNOWN, NONE, false), | |
4d97c5c8 JB |
968 | ARCH (i186, UNKNOWN, 186, false), |
969 | ARCH (i286, UNKNOWN, 286, false), | |
970 | ARCH (i386, I386, 386, false), | |
971 | ARCH (i486, I486, 486, false), | |
972 | ARCH (i586, PENTIUM, 586, false), | |
973 | ARCH (i686, PENTIUMPRO, 686, false), | |
974 | ARCH (pentium, PENTIUM, 586, false), | |
6ceeed25 JB |
975 | ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false), |
976 | ARCH (pentiumii, PENTIUMPRO, P2, false), | |
977 | ARCH (pentiumiii, PENTIUMPRO, P3, false), | |
978 | ARCH (pentium4, PENTIUM4, P4, false), | |
979 | ARCH (prescott, NOCONA, CORE, false), | |
980 | ARCH (nocona, NOCONA, NOCONA, false), | |
981 | ARCH (yonah, CORE, CORE, true), | |
982 | ARCH (core, CORE, CORE, false), | |
983 | ARCH (merom, CORE2, CORE2, true), | |
984 | ARCH (core2, CORE2, CORE2, false), | |
985 | ARCH (corei7, COREI7, COREI7, false), | |
986 | ARCH (iamcu, IAMCU, IAMCU, false), | |
987 | ARCH (k6, K6, K6, false), | |
988 | ARCH (k6_2, K6, K6_2, false), | |
989 | ARCH (athlon, ATHLON, ATHLON, false), | |
990 | ARCH (sledgehammer, K8, K8, true), | |
991 | ARCH (opteron, K8, K8, false), | |
992 | ARCH (k8, K8, K8, false), | |
993 | ARCH (amdfam10, AMDFAM10, AMDFAM10, false), | |
994 | ARCH (bdver1, BD, BDVER1, false), | |
995 | ARCH (bdver2, BD, BDVER2, false), | |
996 | ARCH (bdver3, BD, BDVER3, false), | |
997 | ARCH (bdver4, BD, BDVER4, false), | |
998 | ARCH (znver1, ZNVER, ZNVER1, false), | |
999 | ARCH (znver2, ZNVER, ZNVER2, false), | |
1000 | ARCH (znver3, ZNVER, ZNVER3, false), | |
b0e8fa7f | 1001 | ARCH (znver4, ZNVER, ZNVER4, false), |
6ceeed25 JB |
1002 | ARCH (btver1, BT, BTVER1, false), |
1003 | ARCH (btver2, BT, BTVER2, false), | |
1004 | ||
4d97c5c8 JB |
1005 | SUBARCH (8087, 8087, ANY_8087, false), |
1006 | SUBARCH (87, NONE, ANY_8087, false), /* Disable only! */ | |
ae89daec JB |
1007 | SUBARCH (287, 287, ANY_287, false), |
1008 | SUBARCH (387, 387, ANY_387, false), | |
1009 | SUBARCH (687, 687, ANY_687, false), | |
4d97c5c8 | 1010 | SUBARCH (cmov, CMOV, CMOV, false), |
88bd2203 | 1011 | SUBARCH (fxsr, FXSR, ANY_FXSR, false), |
ae89daec JB |
1012 | SUBARCH (mmx, MMX, ANY_MMX, false), |
1013 | SUBARCH (sse, SSE, ANY_SSE, false), | |
1014 | SUBARCH (sse2, SSE2, ANY_SSE2, false), | |
1015 | SUBARCH (sse3, SSE3, ANY_SSE3, false), | |
1016 | SUBARCH (sse4a, SSE4A, ANY_SSE4A, false), | |
1017 | SUBARCH (ssse3, SSSE3, ANY_SSSE3, false), | |
1018 | SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false), | |
1019 | SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false), | |
1020 | SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false), | |
1021 | SUBARCH (avx, AVX, ANY_AVX, false), | |
1022 | SUBARCH (avx2, AVX2, ANY_AVX2, false), | |
1023 | SUBARCH (avx512f, AVX512F, ANY_AVX512F, false), | |
1024 | SUBARCH (avx512cd, AVX512CD, ANY_AVX512CD, false), | |
1025 | SUBARCH (avx512er, AVX512ER, ANY_AVX512ER, false), | |
1026 | SUBARCH (avx512pf, AVX512PF, ANY_AVX512PF, false), | |
1027 | SUBARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, false), | |
1028 | SUBARCH (avx512bw, AVX512BW, ANY_AVX512BW, false), | |
1029 | SUBARCH (avx512vl, AVX512VL, ANY_AVX512VL, false), | |
cafa5ef7 | 1030 | SUBARCH (monitor, MONITOR, MONITOR, false), |
25626f79 JB |
1031 | SUBARCH (vmx, VMX, ANY_VMX, false), |
1032 | SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false), | |
ae89daec | 1033 | SUBARCH (smx, SMX, SMX, false), |
5091b9ee JB |
1034 | SUBARCH (xsave, XSAVE, ANY_XSAVE, false), |
1035 | SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false), | |
1036 | SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false), | |
1037 | SUBARCH (xsaves, XSAVES, ANY_XSAVES, false), | |
1038 | SUBARCH (aes, AES, ANY_AES, false), | |
1039 | SUBARCH (pclmul, PCLMUL, ANY_PCLMUL, false), | |
1040 | SUBARCH (clmul, PCLMUL, ANY_PCLMUL, true), | |
ae89daec JB |
1041 | SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false), |
1042 | SUBARCH (rdrnd, RDRND, RDRND, false), | |
5091b9ee | 1043 | SUBARCH (f16c, F16C, ANY_F16C, false), |
ae89daec | 1044 | SUBARCH (bmi2, BMI2, BMI2, false), |
5091b9ee JB |
1045 | SUBARCH (fma, FMA, ANY_FMA, false), |
1046 | SUBARCH (fma4, FMA4, ANY_FMA4, false), | |
1047 | SUBARCH (xop, XOP, ANY_XOP, false), | |
1048 | SUBARCH (lwp, LWP, ANY_LWP, false), | |
ae89daec JB |
1049 | SUBARCH (movbe, MOVBE, MOVBE, false), |
1050 | SUBARCH (cx16, CX16, CX16, false), | |
c3bb24f5 | 1051 | SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false), |
25626f79 | 1052 | SUBARCH (ept, EPT, ANY_EPT, false), |
ae89daec JB |
1053 | SUBARCH (lzcnt, LZCNT, LZCNT, false), |
1054 | SUBARCH (popcnt, POPCNT, POPCNT, false), | |
1055 | SUBARCH (hle, HLE, HLE, false), | |
760ab3d0 JB |
1056 | SUBARCH (rtm, RTM, ANY_RTM, false), |
1057 | SUBARCH (tsx, TSX, TSX, false), | |
ae89daec JB |
1058 | SUBARCH (invpcid, INVPCID, INVPCID, false), |
1059 | SUBARCH (clflush, CLFLUSH, CLFLUSH, false), | |
1060 | SUBARCH (nop, NOP, NOP, false), | |
1061 | SUBARCH (syscall, SYSCALL, SYSCALL, false), | |
1062 | SUBARCH (rdtscp, RDTSCP, RDTSCP, false), | |
5091b9ee JB |
1063 | SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false), |
1064 | SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false), | |
ae89daec | 1065 | SUBARCH (padlock, PADLOCK, PADLOCK, false), |
0919e770 JB |
1066 | SUBARCH (pacifica, SVME, ANY_SVME, true), |
1067 | SUBARCH (svme, SVME, ANY_SVME, false), | |
ae89daec JB |
1068 | SUBARCH (abm, ABM, ABM, false), |
1069 | SUBARCH (bmi, BMI, BMI, false), | |
1070 | SUBARCH (tbm, TBM, TBM, false), | |
1071 | SUBARCH (adx, ADX, ADX, false), | |
1072 | SUBARCH (rdseed, RDSEED, RDSEED, false), | |
1073 | SUBARCH (prfchw, PRFCHW, PRFCHW, false), | |
1074 | SUBARCH (smap, SMAP, SMAP, false), | |
5091b9ee JB |
1075 | SUBARCH (mpx, MPX, ANY_MPX, false), |
1076 | SUBARCH (sha, SHA, ANY_SHA, false), | |
ae89daec JB |
1077 | SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false), |
1078 | SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false), | |
1079 | SUBARCH (se1, SE1, SE1, false), | |
1080 | SUBARCH (clwb, CLWB, CLWB, false), | |
1081 | SUBARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, false), | |
1082 | SUBARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, false), | |
1083 | SUBARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, false), | |
1084 | SUBARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, false), | |
1085 | SUBARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, false), | |
1086 | SUBARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, false), | |
1087 | SUBARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, false), | |
1088 | SUBARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, false), | |
1089 | SUBARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, false), | |
1090 | SUBARCH (clzero, CLZERO, CLZERO, false), | |
1091 | SUBARCH (mwaitx, MWAITX, MWAITX, false), | |
5091b9ee | 1092 | SUBARCH (ospke, OSPKE, ANY_OSPKE, false), |
ae89daec JB |
1093 | SUBARCH (rdpid, RDPID, RDPID, false), |
1094 | SUBARCH (ptwrite, PTWRITE, PTWRITE, false), | |
4d97c5c8 JB |
1095 | SUBARCH (ibt, IBT, IBT, false), |
1096 | SUBARCH (shstk, SHSTK, SHSTK, false), | |
88bd2203 | 1097 | SUBARCH (gfni, GFNI, ANY_GFNI, false), |
b20f4261 JB |
1098 | SUBARCH (vaes, VAES, ANY_VAES, false), |
1099 | SUBARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, false), | |
ae89daec JB |
1100 | SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false), |
1101 | SUBARCH (pconfig, PCONFIG, PCONFIG, false), | |
1102 | SUBARCH (waitpkg, WAITPKG, WAITPKG, false), | |
1103 | SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false), | |
1104 | SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false), | |
1105 | SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false), | |
5091b9ee | 1106 | SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false), |
ae89daec | 1107 | SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false), |
4d97c5c8 JB |
1108 | SUBARCH (movdiri, MOVDIRI, MOVDIRI, false), |
1109 | SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false), | |
ae89daec JB |
1110 | SUBARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, false), |
1111 | SUBARCH (avx512_vp2intersect, AVX512_VP2INTERSECT, | |
1112 | ANY_AVX512_VP2INTERSECT, false), | |
4d97c5c8 JB |
1113 | SUBARCH (tdx, TDX, TDX, false), |
1114 | SUBARCH (enqcmd, ENQCMD, ENQCMD, false), | |
1115 | SUBARCH (serialize, SERIALIZE, SERIALIZE, false), | |
ae89daec JB |
1116 | SUBARCH (rdpru, RDPRU, RDPRU, false), |
1117 | SUBARCH (mcommit, MCOMMIT, MCOMMIT, false), | |
0919e770 | 1118 | SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false), |
760ab3d0 | 1119 | SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false), |
88bd2203 JB |
1120 | SUBARCH (kl, KL, ANY_KL, false), |
1121 | SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false), | |
4d97c5c8 JB |
1122 | SUBARCH (uintr, UINTR, UINTR, false), |
1123 | SUBARCH (hreset, HRESET, HRESET, false), | |
ae89daec | 1124 | SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false), |
ef07be45 | 1125 | SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false), |
4321af3e | 1126 | SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), |
23ae61ad | 1127 | SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), |
4d97c5c8 JB |
1128 | SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), |
1129 | SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), | |
1130 | SUBARCH (msrlist, MSRLIST, MSRLIST, false), | |
01d8ce74 | 1131 | SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), |
4d97c5c8 | 1132 | SUBARCH (rao_int, RAO_INT, RAO_INT, false), |
0919e770 | 1133 | SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), |
293f5f65 L |
1134 | }; |
1135 | ||
6ceeed25 JB |
1136 | #undef SUBARCH |
1137 | #undef ARCH | |
1138 | ||
704209c0 | 1139 | #ifdef I386COFF |
a6c24e68 NC |
1140 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1141 | is allowed to be optional. */ | |
1142 | ||
1143 | static symbolS * | |
1144 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1145 | { | |
1146 | addressT align = 0; | |
1147 | ||
1148 | SKIP_WHITESPACE (); | |
1149 | ||
7ab9ffdd | 1150 | if (needs_align |
a6c24e68 NC |
1151 | && *input_line_pointer == ',') |
1152 | { | |
1153 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1154 | |
a6c24e68 NC |
1155 | if (align == (addressT) -1) |
1156 | return NULL; | |
1157 | } | |
1158 | else | |
1159 | { | |
1160 | if (size >= 8) | |
1161 | align = 3; | |
1162 | else if (size >= 4) | |
1163 | align = 2; | |
1164 | else if (size >= 2) | |
1165 | align = 1; | |
1166 | else | |
1167 | align = 0; | |
1168 | } | |
1169 | ||
1170 | bss_alloc (symbolP, size, align); | |
1171 | return symbolP; | |
1172 | } | |
1173 | ||
704209c0 | 1174 | static void |
a6c24e68 NC |
1175 | pe_lcomm (int needs_align) |
1176 | { | |
1177 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1178 | } | |
704209c0 | 1179 | #endif |
a6c24e68 | 1180 | |
29b0f896 AM |
1181 | const pseudo_typeS md_pseudo_table[] = |
1182 | { | |
1183 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1184 | {"align", s_align_bytes, 0}, | |
1185 | #else | |
1186 | {"align", s_align_ptwo, 0}, | |
1187 | #endif | |
1188 | {"arch", set_cpu_arch, 0}, | |
1189 | #ifndef I386COFF | |
1190 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1191 | #else |
1192 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1193 | #endif |
1194 | {"ffloat", float_cons, 'f'}, | |
1195 | {"dfloat", float_cons, 'd'}, | |
1196 | {"tfloat", float_cons, 'x'}, | |
7d19d096 | 1197 | {"hfloat", float_cons, 'h'}, |
de133cf9 | 1198 | {"bfloat16", float_cons, 'b'}, |
29b0f896 | 1199 | {"value", cons, 2}, |
d182319b | 1200 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1201 | {"noopt", s_ignore, 0}, |
1202 | {"optim", s_ignore, 0}, | |
1203 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1204 | {"code16", set_code_flag, CODE_16BIT}, | |
1205 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1206 | #ifdef BFD64 |
29b0f896 | 1207 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1208 | #endif |
29b0f896 AM |
1209 | {"intel_syntax", set_intel_syntax, 1}, |
1210 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1211 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1212 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1213 | {"allow_index_reg", set_allow_index_reg, 1}, |
1214 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1215 | {"sse_check", set_check, 0}, |
1216 | {"operand_check", set_check, 1}, | |
3b22753a L |
1217 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1218 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1219 | #else |
68d20676 | 1220 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1221 | {"loc", dwarf2_directive_loc, 0}, |
1222 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1223 | #endif |
6482c264 NC |
1224 | #ifdef TE_PE |
1225 | {"secrel32", pe_directive_secrel, 0}, | |
145667f8 | 1226 | {"secidx", pe_directive_secidx, 0}, |
6482c264 | 1227 | #endif |
29b0f896 AM |
1228 | {0, 0, 0} |
1229 | }; | |
1230 | ||
1231 | /* For interface with expression (). */ | |
1232 | extern char *input_line_pointer; | |
1233 | ||
1234 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1235 | static htab_t op_hash; |
29b0f896 AM |
1236 | |
1237 | /* Hash table for register lookup. */ | |
629310ab | 1238 | static htab_t reg_hash; |
29b0f896 | 1239 | \f |
ce8a8b2f AM |
1240 | /* Various efficient no-op patterns for aligning code labels. |
1241 | Note: Don't try to assemble the instructions in the comments. | |
1242 | 0L and 0w are not legal. */ | |
62a02d25 L |
1243 | static const unsigned char f32_1[] = |
1244 | {0x90}; /* nop */ | |
1245 | static const unsigned char f32_2[] = | |
1246 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1247 | static const unsigned char f32_3[] = | |
1248 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1249 | static const unsigned char f32_4[] = | |
1250 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1251 | static const unsigned char f32_6[] = |
1252 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1253 | static const unsigned char f32_7[] = | |
1254 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1255 | static const unsigned char f16_3[] = |
3ae729d5 | 1256 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1257 | static const unsigned char f16_4[] = |
3ae729d5 L |
1258 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1259 | static const unsigned char jump_disp8[] = | |
1260 | {0xeb}; /* jmp disp8 */ | |
1261 | static const unsigned char jump32_disp32[] = | |
1262 | {0xe9}; /* jmp disp32 */ | |
1263 | static const unsigned char jump16_disp32[] = | |
1264 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1265 | /* 32-bit NOPs patterns. */ |
1266 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1267 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1268 | }; |
1269 | /* 16-bit NOPs patterns. */ | |
1270 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1271 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1272 | }; |
1273 | /* nopl (%[re]ax) */ | |
1274 | static const unsigned char alt_3[] = | |
1275 | {0x0f,0x1f,0x00}; | |
1276 | /* nopl 0(%[re]ax) */ | |
1277 | static const unsigned char alt_4[] = | |
1278 | {0x0f,0x1f,0x40,0x00}; | |
1279 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1280 | static const unsigned char alt_5[] = | |
1281 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1282 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1283 | static const unsigned char alt_6[] = | |
1284 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1285 | /* nopl 0L(%[re]ax) */ | |
1286 | static const unsigned char alt_7[] = | |
1287 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1288 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1289 | static const unsigned char alt_8[] = | |
1290 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1291 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1292 | static const unsigned char alt_9[] = | |
1293 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1294 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1295 | static const unsigned char alt_10[] = | |
1296 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1297 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1298 | static const unsigned char alt_11[] = | |
1299 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1300 | /* 32-bit and 64-bit NOPs patterns. */ |
1301 | static const unsigned char *const alt_patt[] = { | |
1302 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1303 | alt_9, alt_10, alt_11 |
62a02d25 L |
1304 | }; |
1305 | ||
1306 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1307 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1308 | ||
1309 | static void | |
1310 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1311 | int count, int max_single_nop_size) | |
1312 | ||
1313 | { | |
3ae729d5 L |
1314 | /* Place the longer NOP first. */ |
1315 | int last; | |
1316 | int offset; | |
3076e594 NC |
1317 | const unsigned char *nops; |
1318 | ||
1319 | if (max_single_nop_size < 1) | |
1320 | { | |
1321 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1322 | max_single_nop_size); | |
1323 | return; | |
1324 | } | |
1325 | ||
1326 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1327 | |
1328 | /* Use the smaller one if the requsted one isn't available. */ | |
1329 | if (nops == NULL) | |
62a02d25 | 1330 | { |
3ae729d5 L |
1331 | max_single_nop_size--; |
1332 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1333 | } |
1334 | ||
3ae729d5 L |
1335 | last = count % max_single_nop_size; |
1336 | ||
1337 | count -= last; | |
1338 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1339 | memcpy (where + offset, nops, max_single_nop_size); | |
1340 | ||
1341 | if (last) | |
1342 | { | |
1343 | nops = patt[last - 1]; | |
1344 | if (nops == NULL) | |
1345 | { | |
1346 | /* Use the smaller one plus one-byte NOP if the needed one | |
1347 | isn't available. */ | |
1348 | last--; | |
1349 | nops = patt[last - 1]; | |
1350 | memcpy (where + offset, nops, last); | |
1351 | where[offset + last] = *patt[0]; | |
1352 | } | |
1353 | else | |
1354 | memcpy (where + offset, nops, last); | |
1355 | } | |
62a02d25 L |
1356 | } |
1357 | ||
3ae729d5 L |
1358 | static INLINE int |
1359 | fits_in_imm7 (offsetT num) | |
1360 | { | |
1361 | return (num & 0x7f) == num; | |
1362 | } | |
1363 | ||
1364 | static INLINE int | |
1365 | fits_in_imm31 (offsetT num) | |
1366 | { | |
1367 | return (num & 0x7fffffff) == num; | |
1368 | } | |
62a02d25 L |
1369 | |
1370 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1371 | single NOP instruction LIMIT. */ | |
1372 | ||
1373 | void | |
3ae729d5 | 1374 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1375 | { |
3ae729d5 | 1376 | const unsigned char *const *patt = NULL; |
62a02d25 | 1377 | int max_single_nop_size; |
3ae729d5 L |
1378 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1379 | int max_number_of_nops; | |
62a02d25 | 1380 | |
3ae729d5 | 1381 | switch (fragP->fr_type) |
62a02d25 | 1382 | { |
3ae729d5 L |
1383 | case rs_fill_nop: |
1384 | case rs_align_code: | |
1385 | break; | |
e379e5f3 L |
1386 | case rs_machine_dependent: |
1387 | /* Allow NOP padding for jumps and calls. */ | |
1388 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1389 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1390 | break; | |
1391 | /* Fall through. */ | |
3ae729d5 | 1392 | default: |
62a02d25 L |
1393 | return; |
1394 | } | |
1395 | ||
ccc9c027 L |
1396 | /* We need to decide which NOP sequence to use for 32bit and |
1397 | 64bit. When -mtune= is used: | |
4eed87de | 1398 | |
76bc74dc L |
1399 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1400 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1401 | 2. For the rest, alt_patt will be used. |
1402 | ||
1403 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1404 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1405 | be used. |
ccc9c027 L |
1406 | |
1407 | When -march= or .arch is used, we can't use anything beyond | |
1408 | cpu_arch_isa_flags. */ | |
1409 | ||
1410 | if (flag_code == CODE_16BIT) | |
1411 | { | |
3ae729d5 L |
1412 | patt = f16_patt; |
1413 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1414 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1415 | max_number_of_nops = 2; | |
252b5132 | 1416 | } |
33fef721 | 1417 | else |
ccc9c027 | 1418 | { |
fbf3f584 | 1419 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1420 | { |
1421 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1422 | switch (cpu_arch_tune) | |
1423 | { | |
1424 | case PROCESSOR_UNKNOWN: | |
1425 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1426 | optimize with nops. */ |
1427 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1428 | patt = alt_patt; |
ccc9c027 L |
1429 | else |
1430 | patt = f32_patt; | |
1431 | break; | |
ccc9c027 L |
1432 | case PROCESSOR_PENTIUM4: |
1433 | case PROCESSOR_NOCONA: | |
ef05d495 | 1434 | case PROCESSOR_CORE: |
76bc74dc | 1435 | case PROCESSOR_CORE2: |
bd5295b2 | 1436 | case PROCESSOR_COREI7: |
76bc74dc | 1437 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1438 | case PROCESSOR_K6: |
1439 | case PROCESSOR_ATHLON: | |
1440 | case PROCESSOR_K8: | |
4eed87de | 1441 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1442 | case PROCESSOR_BD: |
029f3522 | 1443 | case PROCESSOR_ZNVER: |
7b458c12 | 1444 | case PROCESSOR_BT: |
80b8656c | 1445 | patt = alt_patt; |
ccc9c027 | 1446 | break; |
76bc74dc | 1447 | case PROCESSOR_I386: |
ccc9c027 L |
1448 | case PROCESSOR_I486: |
1449 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1450 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1451 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1452 | case PROCESSOR_GENERIC32: |
1453 | patt = f32_patt; | |
1454 | break; | |
c368d2a8 JB |
1455 | case PROCESSOR_NONE: |
1456 | abort (); | |
4eed87de | 1457 | } |
ccc9c027 L |
1458 | } |
1459 | else | |
1460 | { | |
fbf3f584 | 1461 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1462 | { |
1463 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1464 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1465 | PROCESSOR_UNKNOWN. */ |
1466 | abort (); | |
1467 | break; | |
1468 | ||
76bc74dc | 1469 | case PROCESSOR_I386: |
ccc9c027 L |
1470 | case PROCESSOR_I486: |
1471 | case PROCESSOR_PENTIUM: | |
81486035 | 1472 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1473 | case PROCESSOR_K6: |
1474 | case PROCESSOR_ATHLON: | |
1475 | case PROCESSOR_K8: | |
4eed87de | 1476 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1477 | case PROCESSOR_BD: |
029f3522 | 1478 | case PROCESSOR_ZNVER: |
7b458c12 | 1479 | case PROCESSOR_BT: |
ccc9c027 L |
1480 | case PROCESSOR_GENERIC32: |
1481 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1482 | with nops. */ |
1483 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1484 | patt = alt_patt; |
ccc9c027 L |
1485 | else |
1486 | patt = f32_patt; | |
1487 | break; | |
76bc74dc L |
1488 | case PROCESSOR_PENTIUMPRO: |
1489 | case PROCESSOR_PENTIUM4: | |
1490 | case PROCESSOR_NOCONA: | |
1491 | case PROCESSOR_CORE: | |
ef05d495 | 1492 | case PROCESSOR_CORE2: |
bd5295b2 | 1493 | case PROCESSOR_COREI7: |
22109423 | 1494 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1495 | patt = alt_patt; |
ccc9c027 L |
1496 | else |
1497 | patt = f32_patt; | |
1498 | break; | |
1499 | case PROCESSOR_GENERIC64: | |
80b8656c | 1500 | patt = alt_patt; |
ccc9c027 | 1501 | break; |
c368d2a8 JB |
1502 | case PROCESSOR_NONE: |
1503 | abort (); | |
4eed87de | 1504 | } |
ccc9c027 L |
1505 | } |
1506 | ||
76bc74dc L |
1507 | if (patt == f32_patt) |
1508 | { | |
3ae729d5 L |
1509 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1510 | /* Limit number of NOPs to 2 for older processors. */ | |
1511 | max_number_of_nops = 2; | |
76bc74dc L |
1512 | } |
1513 | else | |
1514 | { | |
3ae729d5 L |
1515 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1516 | /* Limit number of NOPs to 7 for newer processors. */ | |
1517 | max_number_of_nops = 7; | |
1518 | } | |
1519 | } | |
1520 | ||
1521 | if (limit == 0) | |
1522 | limit = max_single_nop_size; | |
1523 | ||
1524 | if (fragP->fr_type == rs_fill_nop) | |
1525 | { | |
1526 | /* Output NOPs for .nop directive. */ | |
1527 | if (limit > max_single_nop_size) | |
1528 | { | |
1529 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1530 | _("invalid single nop size: %d " | |
1531 | "(expect within [0, %d])"), | |
1532 | limit, max_single_nop_size); | |
1533 | return; | |
1534 | } | |
1535 | } | |
e379e5f3 | 1536 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1537 | fragP->fr_var = count; |
1538 | ||
1539 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1540 | { | |
1541 | /* Generate jump over NOPs. */ | |
1542 | offsetT disp = count - 2; | |
1543 | if (fits_in_imm7 (disp)) | |
1544 | { | |
1545 | /* Use "jmp disp8" if possible. */ | |
1546 | count = disp; | |
1547 | where[0] = jump_disp8[0]; | |
1548 | where[1] = count; | |
1549 | where += 2; | |
1550 | } | |
1551 | else | |
1552 | { | |
1553 | unsigned int size_of_jump; | |
1554 | ||
1555 | if (flag_code == CODE_16BIT) | |
1556 | { | |
1557 | where[0] = jump16_disp32[0]; | |
1558 | where[1] = jump16_disp32[1]; | |
1559 | size_of_jump = 2; | |
1560 | } | |
1561 | else | |
1562 | { | |
1563 | where[0] = jump32_disp32[0]; | |
1564 | size_of_jump = 1; | |
1565 | } | |
1566 | ||
1567 | count -= size_of_jump + 4; | |
1568 | if (!fits_in_imm31 (count)) | |
1569 | { | |
1570 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1571 | _("jump over nop padding out of range")); | |
1572 | return; | |
1573 | } | |
1574 | ||
1575 | md_number_to_chars (where + size_of_jump, count, 4); | |
1576 | where += size_of_jump + 4; | |
76bc74dc | 1577 | } |
ccc9c027 | 1578 | } |
3ae729d5 L |
1579 | |
1580 | /* Generate multiple NOPs. */ | |
1581 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1582 | } |
1583 | ||
c6fb90c8 | 1584 | static INLINE int |
0dfbf9d7 | 1585 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1586 | { |
0dfbf9d7 | 1587 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1588 | { |
1589 | case 3: | |
0dfbf9d7 | 1590 | if (x->array[2]) |
c6fb90c8 | 1591 | return 0; |
1a0670f3 | 1592 | /* Fall through. */ |
c6fb90c8 | 1593 | case 2: |
0dfbf9d7 | 1594 | if (x->array[1]) |
c6fb90c8 | 1595 | return 0; |
1a0670f3 | 1596 | /* Fall through. */ |
c6fb90c8 | 1597 | case 1: |
0dfbf9d7 | 1598 | return !x->array[0]; |
c6fb90c8 L |
1599 | default: |
1600 | abort (); | |
1601 | } | |
40fb9820 L |
1602 | } |
1603 | ||
c6fb90c8 | 1604 | static INLINE void |
0dfbf9d7 | 1605 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1606 | { |
0dfbf9d7 | 1607 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1608 | { |
1609 | case 3: | |
0dfbf9d7 | 1610 | x->array[2] = v; |
1a0670f3 | 1611 | /* Fall through. */ |
c6fb90c8 | 1612 | case 2: |
0dfbf9d7 | 1613 | x->array[1] = v; |
1a0670f3 | 1614 | /* Fall through. */ |
c6fb90c8 | 1615 | case 1: |
0dfbf9d7 | 1616 | x->array[0] = v; |
1a0670f3 | 1617 | /* Fall through. */ |
c6fb90c8 L |
1618 | break; |
1619 | default: | |
1620 | abort (); | |
1621 | } | |
bab6aec1 JB |
1622 | |
1623 | x->bitfield.class = ClassNone; | |
75e5731b | 1624 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1625 | } |
40fb9820 | 1626 | |
c6fb90c8 | 1627 | static INLINE int |
0dfbf9d7 L |
1628 | operand_type_equal (const union i386_operand_type *x, |
1629 | const union i386_operand_type *y) | |
c6fb90c8 | 1630 | { |
0dfbf9d7 | 1631 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1632 | { |
1633 | case 3: | |
0dfbf9d7 | 1634 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1635 | return 0; |
1a0670f3 | 1636 | /* Fall through. */ |
c6fb90c8 | 1637 | case 2: |
0dfbf9d7 | 1638 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1639 | return 0; |
1a0670f3 | 1640 | /* Fall through. */ |
c6fb90c8 | 1641 | case 1: |
0dfbf9d7 | 1642 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1643 | break; |
1644 | default: | |
1645 | abort (); | |
1646 | } | |
1647 | } | |
40fb9820 | 1648 | |
0dfbf9d7 L |
1649 | static INLINE int |
1650 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1651 | { | |
1652 | switch (ARRAY_SIZE(x->array)) | |
1653 | { | |
75f8266a KL |
1654 | case 5: |
1655 | if (x->array[4]) | |
1656 | return 0; | |
1657 | /* Fall through. */ | |
53467f57 IT |
1658 | case 4: |
1659 | if (x->array[3]) | |
1660 | return 0; | |
1661 | /* Fall through. */ | |
0dfbf9d7 L |
1662 | case 3: |
1663 | if (x->array[2]) | |
1664 | return 0; | |
1a0670f3 | 1665 | /* Fall through. */ |
0dfbf9d7 L |
1666 | case 2: |
1667 | if (x->array[1]) | |
1668 | return 0; | |
1a0670f3 | 1669 | /* Fall through. */ |
0dfbf9d7 L |
1670 | case 1: |
1671 | return !x->array[0]; | |
1672 | default: | |
1673 | abort (); | |
1674 | } | |
1675 | } | |
1676 | ||
0dfbf9d7 L |
1677 | static INLINE int |
1678 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1679 | const union i386_cpu_flags *y) | |
1680 | { | |
1681 | switch (ARRAY_SIZE(x->array)) | |
1682 | { | |
75f8266a KL |
1683 | case 5: |
1684 | if (x->array[4] != y->array[4]) | |
1685 | return 0; | |
1686 | /* Fall through. */ | |
53467f57 IT |
1687 | case 4: |
1688 | if (x->array[3] != y->array[3]) | |
1689 | return 0; | |
1690 | /* Fall through. */ | |
0dfbf9d7 L |
1691 | case 3: |
1692 | if (x->array[2] != y->array[2]) | |
1693 | return 0; | |
1a0670f3 | 1694 | /* Fall through. */ |
0dfbf9d7 L |
1695 | case 2: |
1696 | if (x->array[1] != y->array[1]) | |
1697 | return 0; | |
1a0670f3 | 1698 | /* Fall through. */ |
0dfbf9d7 L |
1699 | case 1: |
1700 | return x->array[0] == y->array[0]; | |
1701 | break; | |
1702 | default: | |
1703 | abort (); | |
1704 | } | |
1705 | } | |
c6fb90c8 L |
1706 | |
1707 | static INLINE int | |
1708 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1709 | { | |
1710 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1711 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1712 | } |
1713 | ||
c6fb90c8 L |
1714 | static INLINE i386_cpu_flags |
1715 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1716 | { |
c6fb90c8 L |
1717 | switch (ARRAY_SIZE (x.array)) |
1718 | { | |
75f8266a KL |
1719 | case 5: |
1720 | x.array [4] &= y.array [4]; | |
1721 | /* Fall through. */ | |
53467f57 IT |
1722 | case 4: |
1723 | x.array [3] &= y.array [3]; | |
1724 | /* Fall through. */ | |
c6fb90c8 L |
1725 | case 3: |
1726 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1727 | /* Fall through. */ |
c6fb90c8 L |
1728 | case 2: |
1729 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1730 | /* Fall through. */ |
c6fb90c8 L |
1731 | case 1: |
1732 | x.array [0] &= y.array [0]; | |
1733 | break; | |
1734 | default: | |
1735 | abort (); | |
1736 | } | |
1737 | return x; | |
1738 | } | |
40fb9820 | 1739 | |
c6fb90c8 L |
1740 | static INLINE i386_cpu_flags |
1741 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1742 | { |
c6fb90c8 | 1743 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1744 | { |
75f8266a KL |
1745 | case 5: |
1746 | x.array [4] |= y.array [4]; | |
1747 | /* Fall through. */ | |
53467f57 IT |
1748 | case 4: |
1749 | x.array [3] |= y.array [3]; | |
1750 | /* Fall through. */ | |
c6fb90c8 L |
1751 | case 3: |
1752 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1753 | /* Fall through. */ |
c6fb90c8 L |
1754 | case 2: |
1755 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1756 | /* Fall through. */ |
c6fb90c8 L |
1757 | case 1: |
1758 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1759 | break; |
1760 | default: | |
1761 | abort (); | |
1762 | } | |
40fb9820 L |
1763 | return x; |
1764 | } | |
1765 | ||
309d3373 JB |
1766 | static INLINE i386_cpu_flags |
1767 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1768 | { | |
1769 | switch (ARRAY_SIZE (x.array)) | |
1770 | { | |
75f8266a KL |
1771 | case 5: |
1772 | x.array [4] &= ~y.array [4]; | |
1773 | /* Fall through. */ | |
53467f57 IT |
1774 | case 4: |
1775 | x.array [3] &= ~y.array [3]; | |
1776 | /* Fall through. */ | |
309d3373 JB |
1777 | case 3: |
1778 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1779 | /* Fall through. */ |
309d3373 JB |
1780 | case 2: |
1781 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1782 | /* Fall through. */ |
309d3373 JB |
1783 | case 1: |
1784 | x.array [0] &= ~y.array [0]; | |
1785 | break; | |
1786 | default: | |
1787 | abort (); | |
1788 | } | |
1789 | return x; | |
1790 | } | |
1791 | ||
6c0946d0 JB |
1792 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1793 | ||
c0f3af97 L |
1794 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1795 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1796 | ||
c0f3af97 | 1797 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1798 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1799 | |
1800 | /* Return CPU flags match bits. */ | |
3629bb00 | 1801 | |
40fb9820 | 1802 | static int |
d3ce72d0 | 1803 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1804 | { |
c0f3af97 L |
1805 | i386_cpu_flags x = t->cpu_flags; |
1806 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1807 | |
1808 | x.bitfield.cpu64 = 0; | |
1809 | x.bitfield.cpuno64 = 0; | |
1810 | ||
0dfbf9d7 | 1811 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1812 | { |
1813 | /* This instruction is available on all archs. */ | |
db12e14e | 1814 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1815 | } |
3629bb00 L |
1816 | else |
1817 | { | |
c0f3af97 | 1818 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1819 | i386_cpu_flags cpu = cpu_arch_flags; |
1820 | ||
ab592e75 JB |
1821 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1822 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1823 | return match; | |
1824 | x.bitfield.cpuavx512vl = 0; | |
1825 | ||
22c36940 JB |
1826 | /* AVX and AVX2 present at the same time express an operand size |
1827 | dependency - strip AVX2 for the purposes here. The operand size | |
1828 | dependent check occurs in check_vecOperands(). */ | |
1829 | if (x.bitfield.cpuavx && x.bitfield.cpuavx2) | |
1830 | x.bitfield.cpuavx2 = 0; | |
1831 | ||
3629bb00 | 1832 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1833 | if (!cpu_flags_all_zero (&cpu)) |
1834 | { | |
57392598 | 1835 | if (x.bitfield.cpuavx) |
a5ff0eb2 | 1836 | { |
929f69fa | 1837 | /* We need to check a few extra flags with AVX. */ |
b9d49817 | 1838 | if (cpu.bitfield.cpuavx |
40d231b4 JB |
1839 | && (!t->opcode_modifier.sse2avx |
1840 | || (sse2avx && !i.prefix[DATA_PREFIX])) | |
b9d49817 | 1841 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
929f69fa | 1842 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1843 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1844 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1845 | } |
929f69fa JB |
1846 | else if (x.bitfield.cpuavx512f) |
1847 | { | |
1848 | /* We need to check a few extra flags with AVX512F. */ | |
1849 | if (cpu.bitfield.cpuavx512f | |
1850 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1851 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1852 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1853 | match |= CPU_FLAGS_ARCH_MATCH; | |
1854 | } | |
a5ff0eb2 | 1855 | else |
db12e14e | 1856 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1857 | } |
3629bb00 | 1858 | } |
c0f3af97 | 1859 | return match; |
40fb9820 L |
1860 | } |
1861 | ||
c6fb90c8 L |
1862 | static INLINE i386_operand_type |
1863 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1864 | { |
bab6aec1 JB |
1865 | if (x.bitfield.class != y.bitfield.class) |
1866 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1867 | if (x.bitfield.instance != y.bitfield.instance) |
1868 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1869 | |
c6fb90c8 L |
1870 | switch (ARRAY_SIZE (x.array)) |
1871 | { | |
1872 | case 3: | |
1873 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1874 | /* Fall through. */ |
c6fb90c8 L |
1875 | case 2: |
1876 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1877 | /* Fall through. */ |
c6fb90c8 L |
1878 | case 1: |
1879 | x.array [0] &= y.array [0]; | |
1880 | break; | |
1881 | default: | |
1882 | abort (); | |
1883 | } | |
1884 | return x; | |
40fb9820 L |
1885 | } |
1886 | ||
73053c1f JB |
1887 | static INLINE i386_operand_type |
1888 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1889 | { | |
bab6aec1 | 1890 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1891 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1892 | |
73053c1f JB |
1893 | switch (ARRAY_SIZE (x.array)) |
1894 | { | |
1895 | case 3: | |
1896 | x.array [2] &= ~y.array [2]; | |
1897 | /* Fall through. */ | |
1898 | case 2: | |
1899 | x.array [1] &= ~y.array [1]; | |
1900 | /* Fall through. */ | |
1901 | case 1: | |
1902 | x.array [0] &= ~y.array [0]; | |
1903 | break; | |
1904 | default: | |
1905 | abort (); | |
1906 | } | |
1907 | return x; | |
1908 | } | |
1909 | ||
c6fb90c8 L |
1910 | static INLINE i386_operand_type |
1911 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1912 | { |
bab6aec1 JB |
1913 | gas_assert (x.bitfield.class == ClassNone || |
1914 | y.bitfield.class == ClassNone || | |
1915 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1916 | gas_assert (x.bitfield.instance == InstanceNone || |
1917 | y.bitfield.instance == InstanceNone || | |
1918 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 1919 | |
c6fb90c8 | 1920 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1921 | { |
c6fb90c8 L |
1922 | case 3: |
1923 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1924 | /* Fall through. */ |
c6fb90c8 L |
1925 | case 2: |
1926 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1927 | /* Fall through. */ |
c6fb90c8 L |
1928 | case 1: |
1929 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1930 | break; |
1931 | default: | |
1932 | abort (); | |
1933 | } | |
c6fb90c8 L |
1934 | return x; |
1935 | } | |
40fb9820 | 1936 | |
c6fb90c8 L |
1937 | static INLINE i386_operand_type |
1938 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
1939 | { | |
bab6aec1 | 1940 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1941 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1942 | |
c6fb90c8 L |
1943 | switch (ARRAY_SIZE (x.array)) |
1944 | { | |
1945 | case 3: | |
1946 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 1947 | /* Fall through. */ |
c6fb90c8 L |
1948 | case 2: |
1949 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 1950 | /* Fall through. */ |
c6fb90c8 L |
1951 | case 1: |
1952 | x.array [0] ^= y.array [0]; | |
1953 | break; | |
1954 | default: | |
1955 | abort (); | |
1956 | } | |
40fb9820 L |
1957 | return x; |
1958 | } | |
1959 | ||
05909f23 JB |
1960 | static const i386_operand_type anydisp = { |
1961 | .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 } | |
1962 | }; | |
40fb9820 L |
1963 | |
1964 | enum operand_type | |
1965 | { | |
1966 | reg, | |
40fb9820 L |
1967 | imm, |
1968 | disp, | |
1969 | anymem | |
1970 | }; | |
1971 | ||
c6fb90c8 | 1972 | static INLINE int |
40fb9820 L |
1973 | operand_type_check (i386_operand_type t, enum operand_type c) |
1974 | { | |
1975 | switch (c) | |
1976 | { | |
1977 | case reg: | |
bab6aec1 | 1978 | return t.bitfield.class == Reg; |
40fb9820 | 1979 | |
40fb9820 L |
1980 | case imm: |
1981 | return (t.bitfield.imm8 | |
1982 | || t.bitfield.imm8s | |
1983 | || t.bitfield.imm16 | |
1984 | || t.bitfield.imm32 | |
1985 | || t.bitfield.imm32s | |
1986 | || t.bitfield.imm64); | |
1987 | ||
1988 | case disp: | |
1989 | return (t.bitfield.disp8 | |
1990 | || t.bitfield.disp16 | |
1991 | || t.bitfield.disp32 | |
40fb9820 L |
1992 | || t.bitfield.disp64); |
1993 | ||
1994 | case anymem: | |
1995 | return (t.bitfield.disp8 | |
1996 | || t.bitfield.disp16 | |
1997 | || t.bitfield.disp32 | |
40fb9820 L |
1998 | || t.bitfield.disp64 |
1999 | || t.bitfield.baseindex); | |
2000 | ||
2001 | default: | |
2002 | abort (); | |
2003 | } | |
2cfe26b6 AM |
2004 | |
2005 | return 0; | |
40fb9820 L |
2006 | } |
2007 | ||
7a54636a L |
2008 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2009 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2010 | |
2011 | static INLINE int | |
7a54636a L |
2012 | match_operand_size (const insn_template *t, unsigned int wanted, |
2013 | unsigned int given) | |
5c07affc | 2014 | { |
3ac21baa JB |
2015 | return !((i.types[given].bitfield.byte |
2016 | && !t->operand_types[wanted].bitfield.byte) | |
2017 | || (i.types[given].bitfield.word | |
2018 | && !t->operand_types[wanted].bitfield.word) | |
2019 | || (i.types[given].bitfield.dword | |
2020 | && !t->operand_types[wanted].bitfield.dword) | |
2021 | || (i.types[given].bitfield.qword | |
9db83a32 JB |
2022 | && (!t->operand_types[wanted].bitfield.qword |
2023 | /* Don't allow 64-bit (memory) operands outside of 64-bit | |
2024 | mode, when they're used where a 64-bit GPR could also | |
2025 | be used. Checking is needed for Intel Syntax only. */ | |
2026 | || (intel_syntax | |
2027 | && flag_code != CODE_64BIT | |
2028 | && (t->operand_types[wanted].bitfield.class == Reg | |
2029 | || t->operand_types[wanted].bitfield.class == Accum | |
2030 | || t->opcode_modifier.isstring)))) | |
3ac21baa JB |
2031 | || (i.types[given].bitfield.tbyte |
2032 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2033 | } |
2034 | ||
dd40ce22 L |
2035 | /* Return 1 if there is no conflict in SIMD register between operand |
2036 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2037 | |
2038 | static INLINE int | |
dd40ce22 L |
2039 | match_simd_size (const insn_template *t, unsigned int wanted, |
2040 | unsigned int given) | |
1b54b8d7 | 2041 | { |
3ac21baa JB |
2042 | return !((i.types[given].bitfield.xmmword |
2043 | && !t->operand_types[wanted].bitfield.xmmword) | |
2044 | || (i.types[given].bitfield.ymmword | |
2045 | && !t->operand_types[wanted].bitfield.ymmword) | |
2046 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2047 | && !t->operand_types[wanted].bitfield.zmmword) |
2048 | || (i.types[given].bitfield.tmmword | |
2049 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2050 | } |
2051 | ||
7a54636a L |
2052 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2053 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2054 | |
2055 | static INLINE int | |
dd40ce22 L |
2056 | match_mem_size (const insn_template *t, unsigned int wanted, |
2057 | unsigned int given) | |
5c07affc | 2058 | { |
7a54636a | 2059 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2060 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2061 | && !i.broadcast.type |
a5748e0d | 2062 | && !i.broadcast.bytes |
3ac21baa JB |
2063 | && !t->operand_types[wanted].bitfield.unspecified) |
2064 | || (i.types[given].bitfield.fword | |
2065 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2066 | /* For scalar opcode templates to allow register and memory |
2067 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2068 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2069 | down-conversion vpmov*. */ | |
3528c362 | 2070 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2071 | && t->operand_types[wanted].bitfield.byte |
2072 | + t->operand_types[wanted].bitfield.word | |
2073 | + t->operand_types[wanted].bitfield.dword | |
2074 | + t->operand_types[wanted].bitfield.qword | |
2075 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2076 | ? (i.types[given].bitfield.xmmword |
2077 | || i.types[given].bitfield.ymmword | |
2078 | || i.types[given].bitfield.zmmword) | |
2079 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2080 | } |
2081 | ||
3ac21baa JB |
2082 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2083 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2084 | is no size conflict on any operands for the template with operands reversed | |
2085 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2086 | |
3ac21baa JB |
2087 | #define MATCH_STRAIGHT 1 |
2088 | #define MATCH_REVERSE 2 | |
2089 | ||
2090 | static INLINE unsigned int | |
d3ce72d0 | 2091 | operand_size_match (const insn_template *t) |
5c07affc | 2092 | { |
3ac21baa | 2093 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2094 | |
0cfa3eb3 | 2095 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2096 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2097 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2098 | return match; |
2099 | ||
2100 | /* Check memory and accumulator operand size. */ | |
2101 | for (j = 0; j < i.operands; j++) | |
2102 | { | |
3528c362 JB |
2103 | if (i.types[j].bitfield.class != Reg |
2104 | && i.types[j].bitfield.class != RegSIMD | |
255571cd | 2105 | && t->opcode_modifier.operandconstraint == ANY_SIZE) |
5c07affc L |
2106 | continue; |
2107 | ||
bab6aec1 | 2108 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2109 | && !match_operand_size (t, j, j)) |
5c07affc L |
2110 | { |
2111 | match = 0; | |
2112 | break; | |
2113 | } | |
2114 | ||
3528c362 | 2115 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2116 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2117 | { |
2118 | match = 0; | |
2119 | break; | |
2120 | } | |
2121 | ||
75e5731b | 2122 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2123 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2124 | { |
2125 | match = 0; | |
2126 | break; | |
2127 | } | |
2128 | ||
c48dadc9 | 2129 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2130 | { |
2131 | match = 0; | |
2132 | break; | |
2133 | } | |
2134 | } | |
2135 | ||
3ac21baa | 2136 | if (!t->opcode_modifier.d) |
7b94647a | 2137 | return match; |
5c07affc L |
2138 | |
2139 | /* Check reverse. */ | |
aa180741 | 2140 | gas_assert (i.operands >= 2); |
5c07affc | 2141 | |
f5eb1d70 | 2142 | for (j = 0; j < i.operands; j++) |
5c07affc | 2143 | { |
f5eb1d70 JB |
2144 | unsigned int given = i.operands - j - 1; |
2145 | ||
aa180741 | 2146 | /* For FMA4 and XOP insns VEX.W controls just the first two |
8bd915b7 | 2147 | register operands. */ |
aa180741 | 2148 | if (t->cpu_flags.bitfield.cpufma4 || t->cpu_flags.bitfield.cpuxop) |
8bd915b7 JB |
2149 | given = j < 2 ? 1 - j : j; |
2150 | ||
bab6aec1 | 2151 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2152 | && !match_operand_size (t, j, given)) |
7b94647a | 2153 | return match; |
5c07affc | 2154 | |
3528c362 | 2155 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2156 | && !match_simd_size (t, j, given)) |
7b94647a | 2157 | return match; |
dbbc8b7e | 2158 | |
75e5731b | 2159 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2160 | && (!match_operand_size (t, j, given) |
2161 | || !match_simd_size (t, j, given))) | |
7b94647a | 2162 | return match; |
dbbc8b7e | 2163 | |
f5eb1d70 | 2164 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
7b94647a | 2165 | return match; |
5c07affc L |
2166 | } |
2167 | ||
3ac21baa | 2168 | return match | MATCH_REVERSE; |
5c07affc L |
2169 | } |
2170 | ||
c6fb90c8 | 2171 | static INLINE int |
40fb9820 L |
2172 | operand_type_match (i386_operand_type overlap, |
2173 | i386_operand_type given) | |
2174 | { | |
2175 | i386_operand_type temp = overlap; | |
2176 | ||
7d5e4556 | 2177 | temp.bitfield.unspecified = 0; |
5c07affc L |
2178 | temp.bitfield.byte = 0; |
2179 | temp.bitfield.word = 0; | |
2180 | temp.bitfield.dword = 0; | |
2181 | temp.bitfield.fword = 0; | |
2182 | temp.bitfield.qword = 0; | |
2183 | temp.bitfield.tbyte = 0; | |
2184 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2185 | temp.bitfield.ymmword = 0; |
43234a1e | 2186 | temp.bitfield.zmmword = 0; |
260cd341 | 2187 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2188 | if (operand_type_all_zero (&temp)) |
891edac4 | 2189 | goto mismatch; |
40fb9820 | 2190 | |
6f2f06be | 2191 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2192 | return 1; |
2193 | ||
dc1e8a47 | 2194 | mismatch: |
a65babc9 | 2195 | i.error = operand_type_mismatch; |
891edac4 | 2196 | return 0; |
40fb9820 L |
2197 | } |
2198 | ||
7d5e4556 | 2199 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2200 | unless the expected operand type register overlap is null. |
8ee52bcf | 2201 | Intel syntax sized memory operands are also checked here. */ |
40fb9820 | 2202 | |
c6fb90c8 | 2203 | static INLINE int |
dc821c5f | 2204 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2205 | i386_operand_type t0, |
40fb9820 L |
2206 | i386_operand_type g1, |
2207 | i386_operand_type t1) | |
2208 | { | |
bab6aec1 | 2209 | if (g0.bitfield.class != Reg |
3528c362 | 2210 | && g0.bitfield.class != RegSIMD |
8ee52bcf JB |
2211 | && (g0.bitfield.unspecified |
2212 | || !operand_type_check (g0, anymem))) | |
40fb9820 L |
2213 | return 1; |
2214 | ||
bab6aec1 | 2215 | if (g1.bitfield.class != Reg |
3528c362 | 2216 | && g1.bitfield.class != RegSIMD |
8ee52bcf JB |
2217 | && (g1.bitfield.unspecified |
2218 | || !operand_type_check (g1, anymem))) | |
40fb9820 L |
2219 | return 1; |
2220 | ||
dc821c5f JB |
2221 | if (g0.bitfield.byte == g1.bitfield.byte |
2222 | && g0.bitfield.word == g1.bitfield.word | |
2223 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2224 | && g0.bitfield.qword == g1.bitfield.qword |
2225 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2226 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2227 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2228 | return 1; |
2229 | ||
c4d09633 JB |
2230 | /* If expectations overlap in no more than a single size, all is fine. */ |
2231 | g0 = operand_type_and (t0, t1); | |
2232 | if (g0.bitfield.byte | |
2233 | + g0.bitfield.word | |
2234 | + g0.bitfield.dword | |
2235 | + g0.bitfield.qword | |
2236 | + g0.bitfield.xmmword | |
2237 | + g0.bitfield.ymmword | |
2238 | + g0.bitfield.zmmword <= 1) | |
891edac4 L |
2239 | return 1; |
2240 | ||
a65babc9 | 2241 | i.error = register_type_mismatch; |
891edac4 L |
2242 | |
2243 | return 0; | |
40fb9820 L |
2244 | } |
2245 | ||
4c692bc7 JB |
2246 | static INLINE unsigned int |
2247 | register_number (const reg_entry *r) | |
2248 | { | |
2249 | unsigned int nr = r->reg_num; | |
2250 | ||
2251 | if (r->reg_flags & RegRex) | |
2252 | nr += 8; | |
2253 | ||
200cbe0f L |
2254 | if (r->reg_flags & RegVRex) |
2255 | nr += 16; | |
2256 | ||
4c692bc7 JB |
2257 | return nr; |
2258 | } | |
2259 | ||
252b5132 | 2260 | static INLINE unsigned int |
40fb9820 | 2261 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2262 | { |
b5014f7a | 2263 | if (t.bitfield.disp8) |
40fb9820 L |
2264 | return 1; |
2265 | else if (t.bitfield.disp16 | |
a775efc8 | 2266 | || t.bitfield.disp32) |
40fb9820 L |
2267 | return 2; |
2268 | else | |
2269 | return 0; | |
252b5132 RH |
2270 | } |
2271 | ||
2272 | static INLINE int | |
65879393 | 2273 | fits_in_signed_byte (addressT num) |
252b5132 | 2274 | { |
65879393 | 2275 | return num + 0x80 <= 0xff; |
47926f60 | 2276 | } |
252b5132 RH |
2277 | |
2278 | static INLINE int | |
65879393 | 2279 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2280 | { |
65879393 | 2281 | return num <= 0xff; |
47926f60 | 2282 | } |
252b5132 RH |
2283 | |
2284 | static INLINE int | |
65879393 | 2285 | fits_in_unsigned_word (addressT num) |
252b5132 | 2286 | { |
65879393 | 2287 | return num <= 0xffff; |
47926f60 | 2288 | } |
252b5132 RH |
2289 | |
2290 | static INLINE int | |
65879393 | 2291 | fits_in_signed_word (addressT num) |
252b5132 | 2292 | { |
65879393 | 2293 | return num + 0x8000 <= 0xffff; |
47926f60 | 2294 | } |
2a962e6d | 2295 | |
3e73aa7c | 2296 | static INLINE int |
65879393 | 2297 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2298 | { |
2299 | #ifndef BFD64 | |
2300 | return 1; | |
2301 | #else | |
65879393 | 2302 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2303 | #endif |
2304 | } /* fits_in_signed_long() */ | |
2a962e6d | 2305 | |
3e73aa7c | 2306 | static INLINE int |
65879393 | 2307 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2308 | { |
2309 | #ifndef BFD64 | |
2310 | return 1; | |
2311 | #else | |
65879393 | 2312 | return num <= 0xffffffff; |
3e73aa7c JH |
2313 | #endif |
2314 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2315 | |
a442cac5 JB |
2316 | static INLINE valueT extend_to_32bit_address (addressT num) |
2317 | { | |
2318 | #ifdef BFD64 | |
2319 | if (fits_in_unsigned_long(num)) | |
2320 | return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
2321 | ||
2322 | if (!fits_in_signed_long (num)) | |
2323 | return num & 0xffffffff; | |
2324 | #endif | |
2325 | ||
2326 | return num; | |
2327 | } | |
2328 | ||
43234a1e | 2329 | static INLINE int |
b5014f7a | 2330 | fits_in_disp8 (offsetT num) |
43234a1e L |
2331 | { |
2332 | int shift = i.memshift; | |
2333 | unsigned int mask; | |
2334 | ||
2335 | if (shift == -1) | |
2336 | abort (); | |
2337 | ||
2338 | mask = (1 << shift) - 1; | |
2339 | ||
2340 | /* Return 0 if NUM isn't properly aligned. */ | |
2341 | if ((num & mask)) | |
2342 | return 0; | |
2343 | ||
2344 | /* Check if NUM will fit in 8bit after shift. */ | |
2345 | return fits_in_signed_byte (num >> shift); | |
2346 | } | |
2347 | ||
a683cc34 SP |
2348 | static INLINE int |
2349 | fits_in_imm4 (offsetT num) | |
2350 | { | |
2351 | return (num & 0xf) == num; | |
2352 | } | |
2353 | ||
40fb9820 | 2354 | static i386_operand_type |
e3bb37b5 | 2355 | smallest_imm_type (offsetT num) |
252b5132 | 2356 | { |
40fb9820 | 2357 | i386_operand_type t; |
7ab9ffdd | 2358 | |
0dfbf9d7 | 2359 | operand_type_set (&t, 0); |
40fb9820 L |
2360 | t.bitfield.imm64 = 1; |
2361 | ||
2362 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2363 | { |
2364 | /* This code is disabled on the 486 because all the Imm1 forms | |
2365 | in the opcode table are slower on the i486. They're the | |
2366 | versions with the implicitly specified single-position | |
2367 | displacement, which has another syntax if you really want to | |
2368 | use that form. */ | |
40fb9820 L |
2369 | t.bitfield.imm1 = 1; |
2370 | t.bitfield.imm8 = 1; | |
2371 | t.bitfield.imm8s = 1; | |
2372 | t.bitfield.imm16 = 1; | |
2373 | t.bitfield.imm32 = 1; | |
2374 | t.bitfield.imm32s = 1; | |
2375 | } | |
2376 | else if (fits_in_signed_byte (num)) | |
2377 | { | |
c34d1cc9 JB |
2378 | if (fits_in_unsigned_byte (num)) |
2379 | t.bitfield.imm8 = 1; | |
40fb9820 L |
2380 | t.bitfield.imm8s = 1; |
2381 | t.bitfield.imm16 = 1; | |
2382 | t.bitfield.imm32 = 1; | |
2383 | t.bitfield.imm32s = 1; | |
2384 | } | |
2385 | else if (fits_in_unsigned_byte (num)) | |
2386 | { | |
2387 | t.bitfield.imm8 = 1; | |
2388 | t.bitfield.imm16 = 1; | |
2389 | t.bitfield.imm32 = 1; | |
2390 | t.bitfield.imm32s = 1; | |
2391 | } | |
2392 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2393 | { | |
2394 | t.bitfield.imm16 = 1; | |
2395 | t.bitfield.imm32 = 1; | |
2396 | t.bitfield.imm32s = 1; | |
2397 | } | |
2398 | else if (fits_in_signed_long (num)) | |
2399 | { | |
2400 | t.bitfield.imm32 = 1; | |
2401 | t.bitfield.imm32s = 1; | |
2402 | } | |
2403 | else if (fits_in_unsigned_long (num)) | |
2404 | t.bitfield.imm32 = 1; | |
2405 | ||
2406 | return t; | |
47926f60 | 2407 | } |
252b5132 | 2408 | |
847f7ad4 | 2409 | static offsetT |
e3bb37b5 | 2410 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2411 | { |
508866be | 2412 | addressT mask; |
ba2adb93 | 2413 | |
847f7ad4 AM |
2414 | switch (size) |
2415 | { | |
508866be L |
2416 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2417 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3e73aa7c | 2418 | #ifdef BFD64 |
64965897 | 2419 | case 4: mask = ((addressT) 1 << 32) - 1; break; |
3e73aa7c | 2420 | #endif |
64965897 | 2421 | case sizeof (val): return val; |
47926f60 | 2422 | default: abort (); |
847f7ad4 AM |
2423 | } |
2424 | ||
4fe51f7d | 2425 | if ((val & ~mask) != 0 && (-val & ~mask) != 0) |
f493c217 AM |
2426 | as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64), |
2427 | (uint64_t) val, (uint64_t) (val & mask)); | |
847f7ad4 | 2428 | |
847f7ad4 AM |
2429 | return val & mask; |
2430 | } | |
2431 | ||
76d3f746 JB |
2432 | static INLINE const char *insn_name (const insn_template *t) |
2433 | { | |
5c139202 | 2434 | return &i386_mnemonics[t->mnem_off]; |
76d3f746 JB |
2435 | } |
2436 | ||
c32fa91d L |
2437 | enum PREFIX_GROUP |
2438 | { | |
2439 | PREFIX_EXIST = 0, | |
2440 | PREFIX_LOCK, | |
2441 | PREFIX_REP, | |
04ef582a | 2442 | PREFIX_DS, |
c32fa91d L |
2443 | PREFIX_OTHER |
2444 | }; | |
2445 | ||
2446 | /* Returns | |
2447 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2448 | same class already exists. | |
2449 | b. PREFIX_LOCK if lock prefix is added. | |
2450 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2451 | d. PREFIX_DS if ds prefix is added. |
2452 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2453 | */ |
2454 | ||
2455 | static enum PREFIX_GROUP | |
e3bb37b5 | 2456 | add_prefix (unsigned int prefix) |
252b5132 | 2457 | { |
c32fa91d | 2458 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2459 | unsigned int q; |
252b5132 | 2460 | |
29b0f896 AM |
2461 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2462 | && flag_code == CODE_64BIT) | |
b1905489 | 2463 | { |
161a04f6 | 2464 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2465 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2466 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2467 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2468 | ret = PREFIX_EXIST; |
b1905489 JB |
2469 | q = REX_PREFIX; |
2470 | } | |
3e73aa7c | 2471 | else |
b1905489 JB |
2472 | { |
2473 | switch (prefix) | |
2474 | { | |
2475 | default: | |
2476 | abort (); | |
2477 | ||
b1905489 | 2478 | case DS_PREFIX_OPCODE: |
04ef582a L |
2479 | ret = PREFIX_DS; |
2480 | /* Fall through. */ | |
2481 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2482 | case ES_PREFIX_OPCODE: |
2483 | case FS_PREFIX_OPCODE: | |
2484 | case GS_PREFIX_OPCODE: | |
2485 | case SS_PREFIX_OPCODE: | |
2486 | q = SEG_PREFIX; | |
2487 | break; | |
2488 | ||
2489 | case REPNE_PREFIX_OPCODE: | |
2490 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2491 | q = REP_PREFIX; |
2492 | ret = PREFIX_REP; | |
2493 | break; | |
2494 | ||
b1905489 | 2495 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2496 | q = LOCK_PREFIX; |
2497 | ret = PREFIX_LOCK; | |
b1905489 JB |
2498 | break; |
2499 | ||
2500 | case FWAIT_OPCODE: | |
2501 | q = WAIT_PREFIX; | |
2502 | break; | |
2503 | ||
2504 | case ADDR_PREFIX_OPCODE: | |
2505 | q = ADDR_PREFIX; | |
2506 | break; | |
2507 | ||
2508 | case DATA_PREFIX_OPCODE: | |
2509 | q = DATA_PREFIX; | |
2510 | break; | |
2511 | } | |
2512 | if (i.prefix[q] != 0) | |
c32fa91d | 2513 | ret = PREFIX_EXIST; |
b1905489 | 2514 | } |
252b5132 | 2515 | |
b1905489 | 2516 | if (ret) |
252b5132 | 2517 | { |
b1905489 JB |
2518 | if (!i.prefix[q]) |
2519 | ++i.prefixes; | |
2520 | i.prefix[q] |= prefix; | |
252b5132 | 2521 | } |
b1905489 JB |
2522 | else |
2523 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2524 | |
252b5132 RH |
2525 | return ret; |
2526 | } | |
2527 | ||
2528 | static void | |
78f12dd3 | 2529 | update_code_flag (int value, int check) |
eecb386c | 2530 | { |
78f12dd3 L |
2531 | PRINTF_LIKE ((*as_error)); |
2532 | ||
1e9cc1c2 | 2533 | flag_code = (enum flag_code) value; |
40fb9820 L |
2534 | if (flag_code == CODE_64BIT) |
2535 | { | |
2536 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2537 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2538 | } |
2539 | else | |
2540 | { | |
2541 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2542 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2543 | } |
2544 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2545 | { |
78f12dd3 L |
2546 | if (check) |
2547 | as_error = as_fatal; | |
2548 | else | |
2549 | as_error = as_bad; | |
2550 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2551 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2552 | } |
40fb9820 | 2553 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2554 | { |
78f12dd3 L |
2555 | if (check) |
2556 | as_error = as_fatal; | |
2557 | else | |
2558 | as_error = as_bad; | |
2559 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2560 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2561 | } |
eecb386c AM |
2562 | stackop_size = '\0'; |
2563 | } | |
2564 | ||
78f12dd3 L |
2565 | static void |
2566 | set_code_flag (int value) | |
2567 | { | |
2568 | update_code_flag (value, 0); | |
2569 | } | |
2570 | ||
eecb386c | 2571 | static void |
e3bb37b5 | 2572 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2573 | { |
1e9cc1c2 | 2574 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2575 | if (flag_code != CODE_16BIT) |
2576 | abort (); | |
2577 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2578 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2579 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2580 | } |
2581 | ||
2582 | static void | |
e3bb37b5 | 2583 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2584 | { |
2585 | /* Find out if register prefixing is specified. */ | |
2586 | int ask_naked_reg = 0; | |
2587 | ||
2588 | SKIP_WHITESPACE (); | |
29b0f896 | 2589 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2590 | { |
d02603dc NC |
2591 | char *string; |
2592 | int e = get_symbol_name (&string); | |
252b5132 | 2593 | |
47926f60 | 2594 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2595 | ask_naked_reg = 1; |
47926f60 | 2596 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2597 | ask_naked_reg = -1; |
2598 | else | |
d0b47220 | 2599 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2600 | (void) restore_line_pointer (e); |
252b5132 RH |
2601 | } |
2602 | demand_empty_rest_of_line (); | |
c3332e24 | 2603 | |
252b5132 RH |
2604 | intel_syntax = syntax_flag; |
2605 | ||
2606 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2607 | allow_naked_reg = (intel_syntax |
2608 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2609 | else |
2610 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2611 | |
ee86248c | 2612 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2613 | |
e4a3b5a4 | 2614 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2615 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2616 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2617 | } |
2618 | ||
1efbbeb4 L |
2619 | static void |
2620 | set_intel_mnemonic (int mnemonic_flag) | |
2621 | { | |
e1d4d893 | 2622 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2623 | } |
2624 | ||
db51cc60 L |
2625 | static void |
2626 | set_allow_index_reg (int flag) | |
2627 | { | |
2628 | allow_index_reg = flag; | |
2629 | } | |
2630 | ||
cb19c032 | 2631 | static void |
7bab8ab5 | 2632 | set_check (int what) |
cb19c032 | 2633 | { |
7bab8ab5 JB |
2634 | enum check_kind *kind; |
2635 | const char *str; | |
2636 | ||
2637 | if (what) | |
2638 | { | |
2639 | kind = &operand_check; | |
2640 | str = "operand"; | |
2641 | } | |
2642 | else | |
2643 | { | |
2644 | kind = &sse_check; | |
2645 | str = "sse"; | |
2646 | } | |
2647 | ||
cb19c032 L |
2648 | SKIP_WHITESPACE (); |
2649 | ||
2650 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2651 | { | |
d02603dc NC |
2652 | char *string; |
2653 | int e = get_symbol_name (&string); | |
cb19c032 L |
2654 | |
2655 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2656 | *kind = check_none; |
cb19c032 | 2657 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2658 | *kind = check_warning; |
cb19c032 | 2659 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2660 | *kind = check_error; |
cb19c032 | 2661 | else |
7bab8ab5 | 2662 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2663 | (void) restore_line_pointer (e); |
cb19c032 L |
2664 | } |
2665 | else | |
7bab8ab5 | 2666 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2667 | |
2668 | demand_empty_rest_of_line (); | |
2669 | } | |
2670 | ||
8a9036a4 L |
2671 | static void |
2672 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2673 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2674 | { |
2675 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2676 | static const char *arch; | |
2677 | ||
c085ab00 | 2678 | /* Intel MCU is only supported on ELF. */ |
8a9036a4 L |
2679 | if (!IS_ELF) |
2680 | return; | |
2681 | ||
2682 | if (!arch) | |
2683 | { | |
2684 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2685 | use default_arch. */ | |
2686 | arch = cpu_arch_name; | |
2687 | if (!arch) | |
2688 | arch = default_arch; | |
2689 | } | |
2690 | ||
81486035 | 2691 | /* If we are targeting Intel MCU, we must enable it. */ |
648d04db JB |
2692 | if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU) |
2693 | == new_flag.bitfield.cpuiamcu) | |
81486035 L |
2694 | return; |
2695 | ||
8a9036a4 L |
2696 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2697 | #endif | |
2698 | } | |
2699 | ||
8180707f JB |
2700 | static void |
2701 | extend_cpu_sub_arch_name (const char *name) | |
2702 | { | |
2703 | if (cpu_sub_arch_name) | |
2704 | cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name, | |
ae89daec | 2705 | ".", name, (const char *) NULL); |
8180707f | 2706 | else |
ae89daec | 2707 | cpu_sub_arch_name = concat (".", name, (const char *) NULL); |
8180707f JB |
2708 | } |
2709 | ||
e413e4e9 | 2710 | static void |
e3bb37b5 | 2711 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2712 | { |
f68697e8 JB |
2713 | typedef struct arch_stack_entry |
2714 | { | |
2715 | const struct arch_stack_entry *prev; | |
2716 | const char *name; | |
2717 | char *sub_name; | |
2718 | i386_cpu_flags flags; | |
2719 | i386_cpu_flags isa_flags; | |
2720 | enum processor_type isa; | |
2721 | enum flag_code flag_code; | |
2722 | char stackop_size; | |
2723 | bool no_cond_jump_promotion; | |
2724 | } arch_stack_entry; | |
2725 | static const arch_stack_entry *arch_stack_top; | |
2726 | ||
47926f60 | 2727 | SKIP_WHITESPACE (); |
e413e4e9 | 2728 | |
29b0f896 | 2729 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2730 | { |
3ce2ebcf JB |
2731 | char *s; |
2732 | int e = get_symbol_name (&s); | |
2733 | const char *string = s; | |
2734 | unsigned int j = 0; | |
40fb9820 | 2735 | i386_cpu_flags flags; |
e413e4e9 | 2736 | |
3ce2ebcf JB |
2737 | if (strcmp (string, "default") == 0) |
2738 | { | |
2739 | if (strcmp (default_arch, "iamcu") == 0) | |
2740 | string = default_arch; | |
2741 | else | |
2742 | { | |
2743 | static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS; | |
2744 | ||
2745 | cpu_arch_name = NULL; | |
2746 | free (cpu_sub_arch_name); | |
2747 | cpu_sub_arch_name = NULL; | |
2748 | cpu_arch_flags = cpu_unknown_flags; | |
2749 | if (flag_code == CODE_64BIT) | |
2750 | { | |
2751 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2752 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2753 | } | |
2754 | else | |
2755 | { | |
2756 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2757 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2758 | } | |
2759 | cpu_arch_isa = PROCESSOR_UNKNOWN; | |
ae89daec | 2760 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
3ce2ebcf JB |
2761 | if (!cpu_arch_tune_set) |
2762 | { | |
2763 | cpu_arch_tune = cpu_arch_isa; | |
2764 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2765 | } | |
2766 | ||
2767 | j = ARRAY_SIZE (cpu_arch) + 1; | |
2768 | } | |
2769 | } | |
f68697e8 JB |
2770 | else if (strcmp (string, "push") == 0) |
2771 | { | |
2772 | arch_stack_entry *top = XNEW (arch_stack_entry); | |
2773 | ||
2774 | top->name = cpu_arch_name; | |
2775 | if (cpu_sub_arch_name) | |
2776 | top->sub_name = xstrdup (cpu_sub_arch_name); | |
2777 | else | |
2778 | top->sub_name = NULL; | |
2779 | top->flags = cpu_arch_flags; | |
2780 | top->isa = cpu_arch_isa; | |
2781 | top->isa_flags = cpu_arch_isa_flags; | |
2782 | top->flag_code = flag_code; | |
2783 | top->stackop_size = stackop_size; | |
2784 | top->no_cond_jump_promotion = no_cond_jump_promotion; | |
2785 | ||
2786 | top->prev = arch_stack_top; | |
2787 | arch_stack_top = top; | |
2788 | ||
2789 | (void) restore_line_pointer (e); | |
2790 | demand_empty_rest_of_line (); | |
2791 | return; | |
2792 | } | |
2793 | else if (strcmp (string, "pop") == 0) | |
2794 | { | |
2795 | const arch_stack_entry *top = arch_stack_top; | |
2796 | ||
2797 | if (!top) | |
2798 | as_bad (_(".arch stack is empty")); | |
2799 | else if (top->flag_code != flag_code | |
2800 | || top->stackop_size != stackop_size) | |
2801 | { | |
2802 | static const unsigned int bits[] = { | |
2803 | [CODE_16BIT] = 16, | |
2804 | [CODE_32BIT] = 32, | |
2805 | [CODE_64BIT] = 64, | |
2806 | }; | |
2807 | ||
2808 | as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"), | |
2809 | bits[top->flag_code], | |
2810 | top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : ""); | |
2811 | } | |
2812 | else | |
2813 | { | |
2814 | arch_stack_top = top->prev; | |
2815 | ||
2816 | cpu_arch_name = top->name; | |
2817 | free (cpu_sub_arch_name); | |
2818 | cpu_sub_arch_name = top->sub_name; | |
2819 | cpu_arch_flags = top->flags; | |
2820 | cpu_arch_isa = top->isa; | |
2821 | cpu_arch_isa_flags = top->isa_flags; | |
2822 | no_cond_jump_promotion = top->no_cond_jump_promotion; | |
2823 | ||
2824 | XDELETE (top); | |
2825 | } | |
2826 | ||
2827 | (void) restore_line_pointer (e); | |
2828 | demand_empty_rest_of_line (); | |
2829 | return; | |
2830 | } | |
3ce2ebcf JB |
2831 | |
2832 | for (; j < ARRAY_SIZE (cpu_arch); j++) | |
e413e4e9 | 2833 | { |
ae89daec JB |
2834 | if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0 |
2835 | && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE)) | |
e413e4e9 | 2836 | { |
5c6af06e JB |
2837 | if (*string != '.') |
2838 | { | |
ae89daec | 2839 | check_cpu_arch_compatible (string, cpu_arch[j].enable); |
648d04db | 2840 | |
91d6fa6a | 2841 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 2842 | free (cpu_sub_arch_name); |
5c6af06e | 2843 | cpu_sub_arch_name = NULL; |
ae89daec | 2844 | cpu_arch_flags = cpu_arch[j].enable; |
40fb9820 L |
2845 | if (flag_code == CODE_64BIT) |
2846 | { | |
2847 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2848 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2849 | } | |
2850 | else | |
2851 | { | |
2852 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2853 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2854 | } | |
91d6fa6a | 2855 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 2856 | cpu_arch_isa_flags = cpu_arch[j].enable; |
ccc9c027 L |
2857 | if (!cpu_arch_tune_set) |
2858 | { | |
2859 | cpu_arch_tune = cpu_arch_isa; | |
2860 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2861 | } | |
d59a54c2 | 2862 | pre_386_16bit_warned = false; |
5c6af06e JB |
2863 | break; |
2864 | } | |
40fb9820 | 2865 | |
ae89daec JB |
2866 | if (cpu_flags_all_zero (&cpu_arch[j].enable)) |
2867 | continue; | |
2868 | ||
293f5f65 | 2869 | flags = cpu_flags_or (cpu_arch_flags, |
ae89daec | 2870 | cpu_arch[j].enable); |
81486035 | 2871 | |
5b64d091 | 2872 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2873 | { |
ae89daec | 2874 | extend_cpu_sub_arch_name (string + 1); |
40fb9820 | 2875 | cpu_arch_flags = flags; |
a586129e | 2876 | cpu_arch_isa_flags = flags; |
5c6af06e | 2877 | } |
0089dace L |
2878 | else |
2879 | cpu_arch_isa_flags | |
2880 | = cpu_flags_or (cpu_arch_isa_flags, | |
ae89daec | 2881 | cpu_arch[j].enable); |
d02603dc | 2882 | (void) restore_line_pointer (e); |
5c6af06e JB |
2883 | demand_empty_rest_of_line (); |
2884 | return; | |
e413e4e9 AM |
2885 | } |
2886 | } | |
293f5f65 | 2887 | |
ae89daec | 2888 | if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch)) |
293f5f65 | 2889 | { |
33eaf5de | 2890 | /* Disable an ISA extension. */ |
ae89daec JB |
2891 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
2892 | if (cpu_arch[j].type == PROCESSOR_NONE | |
2893 | && strcmp (string + 3, cpu_arch[j].name) == 0) | |
293f5f65 L |
2894 | { |
2895 | flags = cpu_flags_and_not (cpu_arch_flags, | |
ae89daec | 2896 | cpu_arch[j].disable); |
293f5f65 L |
2897 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
2898 | { | |
ae89daec | 2899 | extend_cpu_sub_arch_name (string + 1); |
293f5f65 L |
2900 | cpu_arch_flags = flags; |
2901 | cpu_arch_isa_flags = flags; | |
2902 | } | |
2903 | (void) restore_line_pointer (e); | |
2904 | demand_empty_rest_of_line (); | |
2905 | return; | |
2906 | } | |
293f5f65 L |
2907 | } |
2908 | ||
3ce2ebcf | 2909 | if (j == ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2910 | as_bad (_("no such architecture: `%s'"), string); |
2911 | ||
2912 | *input_line_pointer = e; | |
2913 | } | |
2914 | else | |
2915 | as_bad (_("missing cpu architecture")); | |
2916 | ||
fddf5b5b AM |
2917 | no_cond_jump_promotion = 0; |
2918 | if (*input_line_pointer == ',' | |
29b0f896 | 2919 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2920 | { |
d02603dc NC |
2921 | char *string; |
2922 | char e; | |
2923 | ||
2924 | ++input_line_pointer; | |
2925 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2926 | |
2927 | if (strcmp (string, "nojumps") == 0) | |
2928 | no_cond_jump_promotion = 1; | |
2929 | else if (strcmp (string, "jumps") == 0) | |
2930 | ; | |
2931 | else | |
2932 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2933 | ||
d02603dc | 2934 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2935 | } |
2936 | ||
e413e4e9 AM |
2937 | demand_empty_rest_of_line (); |
2938 | } | |
2939 | ||
8a9036a4 L |
2940 | enum bfd_architecture |
2941 | i386_arch (void) | |
2942 | { | |
c085ab00 | 2943 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
2944 | { |
2945 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2946 | || flag_code == CODE_64BIT) | |
2947 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2948 | return bfd_arch_iamcu; | |
2949 | } | |
8a9036a4 L |
2950 | else |
2951 | return bfd_arch_i386; | |
2952 | } | |
2953 | ||
b9d79e03 | 2954 | unsigned long |
7016a5d5 | 2955 | i386_mach (void) |
b9d79e03 | 2956 | { |
d34049e8 | 2957 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 2958 | { |
c085ab00 | 2959 | if (default_arch[6] == '\0') |
8a9036a4 | 2960 | return bfd_mach_x86_64; |
351f65ca L |
2961 | else |
2962 | return bfd_mach_x64_32; | |
8a9036a4 | 2963 | } |
5197d474 L |
2964 | else if (!strcmp (default_arch, "i386") |
2965 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
2966 | { |
2967 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
2968 | { | |
2969 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
2970 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
2971 | return bfd_mach_i386_iamcu; | |
2972 | } | |
2973 | else | |
2974 | return bfd_mach_i386_i386; | |
2975 | } | |
b9d79e03 | 2976 | else |
2b5d6a91 | 2977 | as_fatal (_("unknown architecture")); |
b9d79e03 | 2978 | } |
b9d79e03 | 2979 | \f |
99f0fb12 JB |
2980 | #include "opcodes/i386-tbl.h" |
2981 | ||
252b5132 | 2982 | void |
7016a5d5 | 2983 | md_begin (void) |
252b5132 | 2984 | { |
86fa6981 L |
2985 | /* Support pseudo prefixes like {disp32}. */ |
2986 | lex_type ['{'] = LEX_BEGIN_NAME; | |
2987 | ||
47926f60 | 2988 | /* Initialize op_hash hash table. */ |
629310ab | 2989 | op_hash = str_htab_create (); |
252b5132 RH |
2990 | |
2991 | { | |
65f440c8 JB |
2992 | const insn_template *const *sets = i386_op_sets; |
2993 | const insn_template *const *end = sets + ARRAY_SIZE (i386_op_sets) - 1; | |
2994 | ||
2995 | /* Type checks to compensate for the conversion through void * which | |
2996 | occurs during hash table insertion / lookup. */ | |
eb993861 JB |
2997 | (void) sizeof (sets == ¤t_templates->start); |
2998 | (void) sizeof (end == ¤t_templates->end); | |
65f440c8 | 2999 | for (; sets < end; ++sets) |
76d3f746 JB |
3000 | if (str_hash_insert (op_hash, insn_name (*sets), sets, 0)) |
3001 | as_fatal (_("duplicate %s"), insn_name (*sets)); | |
252b5132 RH |
3002 | } |
3003 | ||
47926f60 | 3004 | /* Initialize reg_hash hash table. */ |
629310ab | 3005 | reg_hash = str_htab_create (); |
252b5132 | 3006 | { |
29b0f896 | 3007 | const reg_entry *regtab; |
c3fe08fa | 3008 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3009 | |
c3fe08fa | 3010 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 3011 | { |
6288d05f JB |
3012 | switch (regtab->reg_type.bitfield.class) |
3013 | { | |
3014 | case Reg: | |
34684862 JB |
3015 | if (regtab->reg_type.bitfield.dword) |
3016 | { | |
3017 | if (regtab->reg_type.bitfield.instance == Accum) | |
3018 | reg_eax = regtab; | |
3019 | } | |
3020 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3021 | { |
3022 | /* There's no point inserting st(<N>) in the hash table, as | |
3023 | parentheses aren't included in register_chars[] anyway. */ | |
3024 | if (regtab->reg_type.bitfield.instance != Accum) | |
3025 | continue; | |
3026 | reg_st0 = regtab; | |
3027 | } | |
3028 | break; | |
3029 | ||
5e042380 JB |
3030 | case SReg: |
3031 | switch (regtab->reg_num) | |
3032 | { | |
3033 | case 0: reg_es = regtab; break; | |
3034 | case 2: reg_ss = regtab; break; | |
3035 | case 3: reg_ds = regtab; break; | |
3036 | } | |
3037 | break; | |
3038 | ||
6288d05f JB |
3039 | case RegMask: |
3040 | if (!regtab->reg_num) | |
3041 | reg_k0 = regtab; | |
3042 | break; | |
3043 | } | |
3044 | ||
6225c532 JB |
3045 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3046 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3047 | } |
252b5132 RH |
3048 | } |
3049 | ||
47926f60 | 3050 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3051 | { |
29b0f896 AM |
3052 | int c; |
3053 | char *p; | |
252b5132 RH |
3054 | |
3055 | for (c = 0; c < 256; c++) | |
3056 | { | |
014fbcda | 3057 | if (ISDIGIT (c) || ISLOWER (c)) |
252b5132 RH |
3058 | { |
3059 | mnemonic_chars[c] = c; | |
3060 | register_chars[c] = c; | |
3061 | operand_chars[c] = c; | |
3062 | } | |
3882b010 | 3063 | else if (ISUPPER (c)) |
252b5132 | 3064 | { |
3882b010 | 3065 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3066 | register_chars[c] = mnemonic_chars[c]; |
3067 | operand_chars[c] = c; | |
3068 | } | |
43234a1e | 3069 | else if (c == '{' || c == '}') |
86fa6981 L |
3070 | { |
3071 | mnemonic_chars[c] = c; | |
3072 | operand_chars[c] = c; | |
3073 | } | |
b3983e5f JB |
3074 | #ifdef SVR4_COMMENT_CHARS |
3075 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3076 | operand_chars[c] = c; | |
3077 | #endif | |
252b5132 | 3078 | |
3882b010 | 3079 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3080 | identifier_chars[c] = c; |
3081 | else if (c >= 128) | |
3082 | { | |
3083 | identifier_chars[c] = c; | |
3084 | operand_chars[c] = c; | |
3085 | } | |
3086 | } | |
3087 | ||
3088 | #ifdef LEX_AT | |
3089 | identifier_chars['@'] = '@'; | |
32137342 NC |
3090 | #endif |
3091 | #ifdef LEX_QM | |
3092 | identifier_chars['?'] = '?'; | |
3093 | operand_chars['?'] = '?'; | |
252b5132 | 3094 | #endif |
c0f3af97 | 3095 | mnemonic_chars['_'] = '_'; |
791fe849 | 3096 | mnemonic_chars['-'] = '-'; |
0003779b | 3097 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3098 | identifier_chars['_'] = '_'; |
3099 | identifier_chars['.'] = '.'; | |
3100 | ||
3101 | for (p = operand_special_chars; *p != '\0'; p++) | |
3102 | operand_chars[(unsigned char) *p] = *p; | |
3103 | } | |
3104 | ||
a4447b93 RH |
3105 | if (flag_code == CODE_64BIT) |
3106 | { | |
ca19b261 KT |
3107 | #if defined (OBJ_COFF) && defined (TE_PE) |
3108 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3109 | ? 32 : 16); | |
3110 | #else | |
a4447b93 | 3111 | x86_dwarf2_return_column = 16; |
ca19b261 | 3112 | #endif |
61ff971f | 3113 | x86_cie_data_alignment = -8; |
b52c4ee4 IB |
3114 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3115 | x86_sframe_cfa_sp_reg = 7; | |
3116 | x86_sframe_cfa_fp_reg = 6; | |
3117 | #endif | |
a4447b93 RH |
3118 | } |
3119 | else | |
3120 | { | |
3121 | x86_dwarf2_return_column = 8; | |
3122 | x86_cie_data_alignment = -4; | |
3123 | } | |
e379e5f3 L |
3124 | |
3125 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3126 | can be turned into BRANCH_PREFIX frag. */ | |
3127 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3128 | abort (); | |
252b5132 RH |
3129 | } |
3130 | ||
3131 | void | |
e3bb37b5 | 3132 | i386_print_statistics (FILE *file) |
252b5132 | 3133 | { |
629310ab ML |
3134 | htab_print_statistics (file, "i386 opcode", op_hash); |
3135 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 | 3136 | } |
654d6f31 AM |
3137 | |
3138 | void | |
3139 | i386_md_end (void) | |
3140 | { | |
3141 | htab_delete (op_hash); | |
3142 | htab_delete (reg_hash); | |
3143 | } | |
252b5132 | 3144 | \f |
252b5132 RH |
3145 | #ifdef DEBUG386 |
3146 | ||
ce8a8b2f | 3147 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3148 | static void pte (insn_template *); |
40fb9820 | 3149 | static void pt (i386_operand_type); |
e3bb37b5 L |
3150 | static void pe (expressionS *); |
3151 | static void ps (symbolS *); | |
252b5132 RH |
3152 | |
3153 | static void | |
2c703856 | 3154 | pi (const char *line, i386_insn *x) |
252b5132 | 3155 | { |
09137c09 | 3156 | unsigned int j; |
252b5132 RH |
3157 | |
3158 | fprintf (stdout, "%s: template ", line); | |
3159 | pte (&x->tm); | |
09f131f2 JH |
3160 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3161 | x->base_reg ? x->base_reg->reg_name : "none", | |
3162 | x->index_reg ? x->index_reg->reg_name : "none", | |
3163 | x->log2_scale_factor); | |
3164 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3165 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3166 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3167 | x->sib.base, x->sib.index, x->sib.scale); | |
3168 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3169 | (x->rex & REX_W) != 0, |
3170 | (x->rex & REX_R) != 0, | |
3171 | (x->rex & REX_X) != 0, | |
3172 | (x->rex & REX_B) != 0); | |
09137c09 | 3173 | for (j = 0; j < x->operands; j++) |
252b5132 | 3174 | { |
09137c09 SP |
3175 | fprintf (stdout, " #%d: ", j + 1); |
3176 | pt (x->types[j]); | |
252b5132 | 3177 | fprintf (stdout, "\n"); |
bab6aec1 | 3178 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3179 | || x->types[j].bitfield.class == RegMMX |
3180 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3181 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3182 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3183 | || x->types[j].bitfield.class == RegCR |
3184 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3185 | || x->types[j].bitfield.class == RegTR |
3186 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3187 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3188 | if (operand_type_check (x->types[j], imm)) | |
3189 | pe (x->op[j].imms); | |
3190 | if (operand_type_check (x->types[j], disp)) | |
3191 | pe (x->op[j].disps); | |
252b5132 RH |
3192 | } |
3193 | } | |
3194 | ||
3195 | static void | |
d3ce72d0 | 3196 | pte (insn_template *t) |
252b5132 | 3197 | { |
b933fa4b | 3198 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca | 3199 | static const char *const opc_spc[] = { |
0cc78721 | 3200 | NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL, |
441f6aca JB |
3201 | "XOP08", "XOP09", "XOP0A", |
3202 | }; | |
09137c09 | 3203 | unsigned int j; |
441f6aca | 3204 | |
252b5132 | 3205 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3206 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3207 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
ddb62495 JB |
3208 | if (opc_spc[t->opcode_space]) |
3209 | fprintf (stdout, "space %s ", opc_spc[t->opcode_space]); | |
47926f60 | 3210 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3211 | if (t->extension_opcode != None) |
3212 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3213 | if (t->opcode_modifier.d) |
252b5132 | 3214 | fprintf (stdout, "D"); |
40fb9820 | 3215 | if (t->opcode_modifier.w) |
252b5132 RH |
3216 | fprintf (stdout, "W"); |
3217 | fprintf (stdout, "\n"); | |
09137c09 | 3218 | for (j = 0; j < t->operands; j++) |
252b5132 | 3219 | { |
09137c09 SP |
3220 | fprintf (stdout, " #%d type ", j + 1); |
3221 | pt (t->operand_types[j]); | |
252b5132 RH |
3222 | fprintf (stdout, "\n"); |
3223 | } | |
3224 | } | |
3225 | ||
3226 | static void | |
e3bb37b5 | 3227 | pe (expressionS *e) |
252b5132 | 3228 | { |
24eab124 | 3229 | fprintf (stdout, " operation %d\n", e->X_op); |
b8281767 AM |
3230 | fprintf (stdout, " add_number %" PRId64 " (%" PRIx64 ")\n", |
3231 | (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number); | |
252b5132 RH |
3232 | if (e->X_add_symbol) |
3233 | { | |
3234 | fprintf (stdout, " add_symbol "); | |
3235 | ps (e->X_add_symbol); | |
3236 | fprintf (stdout, "\n"); | |
3237 | } | |
3238 | if (e->X_op_symbol) | |
3239 | { | |
3240 | fprintf (stdout, " op_symbol "); | |
3241 | ps (e->X_op_symbol); | |
3242 | fprintf (stdout, "\n"); | |
3243 | } | |
3244 | } | |
3245 | ||
3246 | static void | |
e3bb37b5 | 3247 | ps (symbolS *s) |
252b5132 RH |
3248 | { |
3249 | fprintf (stdout, "%s type %s%s", | |
3250 | S_GET_NAME (s), | |
3251 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3252 | segment_name (S_GET_SEGMENT (s))); | |
3253 | } | |
3254 | ||
7b81dfbb | 3255 | static struct type_name |
252b5132 | 3256 | { |
40fb9820 L |
3257 | i386_operand_type mask; |
3258 | const char *name; | |
252b5132 | 3259 | } |
7b81dfbb | 3260 | const type_names[] = |
252b5132 | 3261 | { |
05909f23 JB |
3262 | { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" }, |
3263 | { { .bitfield = { .class = Reg, .word = 1 } }, "r16" }, | |
3264 | { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" }, | |
3265 | { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" }, | |
3266 | { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" }, | |
3267 | { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" }, | |
3268 | { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" }, | |
3269 | { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" }, | |
3270 | { { .bitfield = { .imm8 = 1 } }, "i8" }, | |
3271 | { { .bitfield = { .imm8s = 1 } }, "i8s" }, | |
3272 | { { .bitfield = { .imm16 = 1 } }, "i16" }, | |
3273 | { { .bitfield = { .imm32 = 1 } }, "i32" }, | |
3274 | { { .bitfield = { .imm32s = 1 } }, "i32s" }, | |
3275 | { { .bitfield = { .imm64 = 1 } }, "i64" }, | |
3276 | { { .bitfield = { .imm1 = 1 } }, "i1" }, | |
3277 | { { .bitfield = { .baseindex = 1 } }, "BaseIndex" }, | |
3278 | { { .bitfield = { .disp8 = 1 } }, "d8" }, | |
3279 | { { .bitfield = { .disp16 = 1 } }, "d16" }, | |
3280 | { { .bitfield = { .disp32 = 1 } }, "d32" }, | |
3281 | { { .bitfield = { .disp64 = 1 } }, "d64" }, | |
3282 | { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" }, | |
3283 | { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" }, | |
3284 | { { .bitfield = { .class = RegCR } }, "control reg" }, | |
3285 | { { .bitfield = { .class = RegTR } }, "test reg" }, | |
3286 | { { .bitfield = { .class = RegDR } }, "debug reg" }, | |
3287 | { { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" }, | |
3288 | { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" }, | |
3289 | { { .bitfield = { .class = SReg } }, "SReg" }, | |
3290 | { { .bitfield = { .class = RegMMX } }, "rMMX" }, | |
3291 | { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" }, | |
3292 | { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" }, | |
3293 | { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" }, | |
3294 | { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" }, | |
3295 | { { .bitfield = { .class = RegMask } }, "Mask reg" }, | |
252b5132 RH |
3296 | }; |
3297 | ||
3298 | static void | |
40fb9820 | 3299 | pt (i386_operand_type t) |
252b5132 | 3300 | { |
40fb9820 | 3301 | unsigned int j; |
c6fb90c8 | 3302 | i386_operand_type a; |
252b5132 | 3303 | |
40fb9820 | 3304 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3305 | { |
3306 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3307 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3308 | fprintf (stdout, "%s, ", type_names[j].name); |
3309 | } | |
252b5132 RH |
3310 | fflush (stdout); |
3311 | } | |
3312 | ||
3313 | #endif /* DEBUG386 */ | |
3314 | \f | |
252b5132 | 3315 | static bfd_reloc_code_real_type |
3956db08 | 3316 | reloc (unsigned int size, |
64e74474 AM |
3317 | int pcrel, |
3318 | int sign, | |
3319 | bfd_reloc_code_real_type other) | |
252b5132 | 3320 | { |
47926f60 | 3321 | if (other != NO_RELOC) |
3956db08 | 3322 | { |
91d6fa6a | 3323 | reloc_howto_type *rel; |
3956db08 JB |
3324 | |
3325 | if (size == 8) | |
3326 | switch (other) | |
3327 | { | |
64e74474 AM |
3328 | case BFD_RELOC_X86_64_GOT32: |
3329 | return BFD_RELOC_X86_64_GOT64; | |
3330 | break; | |
553d1284 L |
3331 | case BFD_RELOC_X86_64_GOTPLT64: |
3332 | return BFD_RELOC_X86_64_GOTPLT64; | |
3333 | break; | |
64e74474 AM |
3334 | case BFD_RELOC_X86_64_PLTOFF64: |
3335 | return BFD_RELOC_X86_64_PLTOFF64; | |
3336 | break; | |
3337 | case BFD_RELOC_X86_64_GOTPC32: | |
3338 | other = BFD_RELOC_X86_64_GOTPC64; | |
3339 | break; | |
3340 | case BFD_RELOC_X86_64_GOTPCREL: | |
3341 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3342 | break; | |
3343 | case BFD_RELOC_X86_64_TPOFF32: | |
3344 | other = BFD_RELOC_X86_64_TPOFF64; | |
3345 | break; | |
3346 | case BFD_RELOC_X86_64_DTPOFF32: | |
3347 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3348 | break; | |
3349 | default: | |
3350 | break; | |
3956db08 | 3351 | } |
e05278af | 3352 | |
8ce3d284 | 3353 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3354 | if (other == BFD_RELOC_SIZE32) |
3355 | { | |
3356 | if (size == 8) | |
1ab668bf | 3357 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3358 | if (pcrel) |
1ab668bf AM |
3359 | { |
3360 | as_bad (_("there are no pc-relative size relocations")); | |
3361 | return NO_RELOC; | |
3362 | } | |
8fd4256d | 3363 | } |
8ce3d284 | 3364 | #endif |
8fd4256d | 3365 | |
e05278af | 3366 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3367 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3368 | sign = -1; |
3369 | ||
91d6fa6a NC |
3370 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3371 | if (!rel) | |
3956db08 | 3372 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3373 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3374 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3375 | bfd_get_reloc_size (rel), |
3956db08 | 3376 | size); |
91d6fa6a | 3377 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3378 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3379 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3380 | && !sign) |
91d6fa6a | 3381 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3382 | && sign > 0)) |
3956db08 JB |
3383 | as_bad (_("relocated field and relocation type differ in signedness")); |
3384 | else | |
3385 | return other; | |
3386 | return NO_RELOC; | |
3387 | } | |
252b5132 RH |
3388 | |
3389 | if (pcrel) | |
3390 | { | |
3e73aa7c | 3391 | if (!sign) |
3956db08 | 3392 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3393 | switch (size) |
3394 | { | |
3395 | case 1: return BFD_RELOC_8_PCREL; | |
3396 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3397 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3398 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3399 | } |
3956db08 | 3400 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3401 | } |
3402 | else | |
3403 | { | |
3956db08 | 3404 | if (sign > 0) |
e5cb08ac | 3405 | switch (size) |
3e73aa7c JH |
3406 | { |
3407 | case 4: return BFD_RELOC_X86_64_32S; | |
3408 | } | |
3409 | else | |
3410 | switch (size) | |
3411 | { | |
3412 | case 1: return BFD_RELOC_8; | |
3413 | case 2: return BFD_RELOC_16; | |
3414 | case 4: return BFD_RELOC_32; | |
3415 | case 8: return BFD_RELOC_64; | |
3416 | } | |
3956db08 JB |
3417 | as_bad (_("cannot do %s %u byte relocation"), |
3418 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3419 | } |
3420 | ||
0cc9e1d3 | 3421 | return NO_RELOC; |
252b5132 RH |
3422 | } |
3423 | ||
47926f60 KH |
3424 | /* Here we decide which fixups can be adjusted to make them relative to |
3425 | the beginning of the section instead of the symbol. Basically we need | |
3426 | to make sure that the dynamic relocations are done correctly, so in | |
3427 | some cases we force the original symbol to be used. */ | |
3428 | ||
252b5132 | 3429 | int |
e3bb37b5 | 3430 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3431 | { |
6d249963 | 3432 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3433 | if (!IS_ELF) |
31312f95 AM |
3434 | return 1; |
3435 | ||
a161fe53 AM |
3436 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3437 | mode. */ | |
3438 | if (use_rela_relocations | |
3439 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3440 | && fixP->fx_pcrel) | |
252b5132 | 3441 | return 0; |
31312f95 | 3442 | |
8d01d9a9 AJ |
3443 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3444 | and changed later by validate_fix. */ | |
3445 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3446 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3447 | return 0; | |
3448 | ||
8fd4256d L |
3449 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3450 | for size relocations. */ | |
3451 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3452 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3453 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3454 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3455 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3456 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3457 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3458 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3459 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3460 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3461 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3462 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3463 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3464 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3465 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3466 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3467 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3468 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3469 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3470 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3471 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3472 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3473 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3474 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3475 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3476 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3477 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3478 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3479 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3480 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3481 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3482 | return 0; | |
31312f95 | 3483 | #endif |
252b5132 RH |
3484 | return 1; |
3485 | } | |
252b5132 | 3486 | |
a9aabc23 JB |
3487 | static INLINE bool |
3488 | want_disp32 (const insn_template *t) | |
3489 | { | |
3490 | return flag_code != CODE_64BIT | |
3491 | || i.prefix[ADDR_PREFIX] | |
7fc69528 | 3492 | || (t->mnem_off == MN_lea |
fe134c65 JB |
3493 | && (!i.types[1].bitfield.qword |
3494 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3495 | } |
3496 | ||
b4cac588 | 3497 | static int |
e3bb37b5 | 3498 | intel_float_operand (const char *mnemonic) |
252b5132 | 3499 | { |
9306ca4a JB |
3500 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3501 | operands, hence the code here is free to improperly handle opcodes that | |
3502 | have no operands (for better performance and smaller code). */ | |
3503 | ||
3504 | if (mnemonic[0] != 'f') | |
3505 | return 0; /* non-math */ | |
3506 | ||
3507 | switch (mnemonic[1]) | |
3508 | { | |
3509 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3510 | the fs segment override prefix not currently handled because no | |
3511 | call path can make opcodes without operands get here */ | |
3512 | case 'i': | |
3513 | return 2 /* integer op */; | |
3514 | case 'l': | |
3515 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3516 | return 3; /* fldcw/fldenv */ | |
3517 | break; | |
3518 | case 'n': | |
3519 | if (mnemonic[2] != 'o' /* fnop */) | |
3520 | return 3; /* non-waiting control op */ | |
3521 | break; | |
3522 | case 'r': | |
3523 | if (mnemonic[2] == 's') | |
3524 | return 3; /* frstor/frstpm */ | |
3525 | break; | |
3526 | case 's': | |
3527 | if (mnemonic[2] == 'a') | |
3528 | return 3; /* fsave */ | |
3529 | if (mnemonic[2] == 't') | |
3530 | { | |
3531 | switch (mnemonic[3]) | |
3532 | { | |
3533 | case 'c': /* fstcw */ | |
3534 | case 'd': /* fstdw */ | |
3535 | case 'e': /* fstenv */ | |
3536 | case 's': /* fsts[gw] */ | |
3537 | return 3; | |
3538 | } | |
3539 | } | |
3540 | break; | |
3541 | case 'x': | |
3542 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3543 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3544 | break; | |
3545 | } | |
252b5132 | 3546 | |
9306ca4a | 3547 | return 1; |
252b5132 RH |
3548 | } |
3549 | ||
9a182d04 JB |
3550 | static INLINE void |
3551 | install_template (const insn_template *t) | |
3552 | { | |
3553 | unsigned int l; | |
3554 | ||
3555 | i.tm = *t; | |
3556 | ||
3557 | /* Note that for pseudo prefixes this produces a length of 1. But for them | |
3558 | the length isn't interesting at all. */ | |
3559 | for (l = 1; l < 4; ++l) | |
3560 | if (!(t->base_opcode >> (8 * l))) | |
3561 | break; | |
3562 | ||
3563 | i.opcode_length = l; | |
3564 | } | |
3565 | ||
c0f3af97 L |
3566 | /* Build the VEX prefix. */ |
3567 | ||
3568 | static void | |
d3ce72d0 | 3569 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3570 | { |
3571 | unsigned int register_specifier; | |
c0f3af97 | 3572 | unsigned int vector_length; |
03751133 | 3573 | unsigned int w; |
c0f3af97 L |
3574 | |
3575 | /* Check register specifier. */ | |
3576 | if (i.vex.register_specifier) | |
43234a1e L |
3577 | { |
3578 | register_specifier = | |
3579 | ~register_number (i.vex.register_specifier) & 0xf; | |
3580 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3581 | } | |
c0f3af97 L |
3582 | else |
3583 | register_specifier = 0xf; | |
3584 | ||
79f0fa25 L |
3585 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3586 | if there are more than 1 register operand. */ | |
3587 | if (i.reg_operands > 1 | |
3588 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3589 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3590 | && i.operands == i.reg_operands |
dbbc8b7e | 3591 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
ddb62495 | 3592 | && i.tm.opcode_space == SPACE_0F |
dbbc8b7e | 3593 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3594 | && i.rex == REX_B) |
3595 | { | |
3596 | unsigned int xchg = i.operands - 1; | |
3597 | union i386_op temp_op; | |
3598 | i386_operand_type temp_type; | |
3599 | ||
3600 | temp_type = i.types[xchg]; | |
3601 | i.types[xchg] = i.types[0]; | |
3602 | i.types[0] = temp_type; | |
3603 | temp_op = i.op[xchg]; | |
3604 | i.op[xchg] = i.op[0]; | |
3605 | i.op[0] = temp_op; | |
3606 | ||
9c2799c2 | 3607 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3608 | |
3609 | i.rex = REX_R; | |
3610 | xchg = i.rm.regmem; | |
3611 | i.rm.regmem = i.rm.reg; | |
3612 | i.rm.reg = xchg; | |
3613 | ||
dbbc8b7e JB |
3614 | if (i.tm.opcode_modifier.d) |
3615 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
2c735193 | 3616 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
dbbc8b7e | 3617 | else /* Use the next insn. */ |
9a182d04 | 3618 | install_template (&t[1]); |
fa99fab2 L |
3619 | } |
3620 | ||
79dec6b7 JB |
3621 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3622 | are no memory operands and at least 3 register ones. */ | |
3623 | if (i.reg_operands >= 3 | |
3624 | && i.vec_encoding != vex_encoding_vex3 | |
3625 | && i.reg_operands == i.operands - i.imm_operands | |
3626 | && i.tm.opcode_modifier.vex | |
3627 | && i.tm.opcode_modifier.commutative | |
33740f21 JB |
3628 | && (i.tm.opcode_modifier.sse2avx |
3629 | || (optimize > 1 && !i.no_optimize)) | |
79dec6b7 JB |
3630 | && i.rex == REX_B |
3631 | && i.vex.register_specifier | |
3632 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3633 | { | |
3634 | unsigned int xchg = i.operands - i.reg_operands; | |
3635 | union i386_op temp_op; | |
3636 | i386_operand_type temp_type; | |
3637 | ||
ddb62495 | 3638 | gas_assert (i.tm.opcode_space == SPACE_0F); |
79dec6b7 JB |
3639 | gas_assert (!i.tm.opcode_modifier.sae); |
3640 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3641 | &i.types[i.operands - 3])); | |
3642 | gas_assert (i.rm.mode == 3); | |
3643 | ||
3644 | temp_type = i.types[xchg]; | |
3645 | i.types[xchg] = i.types[xchg + 1]; | |
3646 | i.types[xchg + 1] = temp_type; | |
3647 | temp_op = i.op[xchg]; | |
3648 | i.op[xchg] = i.op[xchg + 1]; | |
3649 | i.op[xchg + 1] = temp_op; | |
3650 | ||
3651 | i.rex = 0; | |
3652 | xchg = i.rm.regmem | 8; | |
3653 | i.rm.regmem = ~register_specifier & 0xf; | |
3654 | gas_assert (!(i.rm.regmem & 8)); | |
3655 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3656 | register_specifier = ~xchg & 0xf; | |
3657 | } | |
3658 | ||
539f890d L |
3659 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3660 | vector_length = avxscalar; | |
10c17abd JB |
3661 | else if (i.tm.opcode_modifier.vex == VEX256) |
3662 | vector_length = 1; | |
539f890d | 3663 | else |
10c17abd | 3664 | { |
56522fc5 | 3665 | unsigned int op; |
10c17abd | 3666 | |
c7213af9 L |
3667 | /* Determine vector length from the last multi-length vector |
3668 | operand. */ | |
10c17abd | 3669 | vector_length = 0; |
56522fc5 | 3670 | for (op = t->operands; op--;) |
10c17abd JB |
3671 | if (t->operand_types[op].bitfield.xmmword |
3672 | && t->operand_types[op].bitfield.ymmword | |
3673 | && i.types[op].bitfield.ymmword) | |
3674 | { | |
3675 | vector_length = 1; | |
3676 | break; | |
3677 | } | |
3678 | } | |
c0f3af97 | 3679 | |
03751133 L |
3680 | /* Check the REX.W bit and VEXW. */ |
3681 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3682 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3683 | else if (i.tm.opcode_modifier.vexw) | |
3684 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3685 | else | |
931d03b7 | 3686 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3687 | |
c0f3af97 | 3688 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3689 | if (w == 0 |
3690 | && i.vec_encoding != vex_encoding_vex3 | |
ddb62495 | 3691 | && i.tm.opcode_space == SPACE_0F |
c0f3af97 L |
3692 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3693 | { | |
3694 | /* 2-byte VEX prefix. */ | |
3695 | unsigned int r; | |
3696 | ||
3697 | i.vex.length = 2; | |
3698 | i.vex.bytes[0] = 0xc5; | |
3699 | ||
3700 | /* Check the REX.R bit. */ | |
3701 | r = (i.rex & REX_R) ? 0 : 1; | |
3702 | i.vex.bytes[1] = (r << 7 | |
3703 | | register_specifier << 3 | |
3704 | | vector_length << 2 | |
35648716 | 3705 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3706 | } |
3707 | else | |
3708 | { | |
3709 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3710 | i.vex.length = 3; |
f88c9eb0 | 3711 | |
ddb62495 | 3712 | switch (i.tm.opcode_space) |
5dd85c99 | 3713 | { |
441f6aca JB |
3714 | case SPACE_0F: |
3715 | case SPACE_0F38: | |
3716 | case SPACE_0F3A: | |
80de6e00 | 3717 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3718 | break; |
441f6aca JB |
3719 | case SPACE_XOP08: |
3720 | case SPACE_XOP09: | |
3721 | case SPACE_XOP0A: | |
f88c9eb0 | 3722 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3723 | break; |
3724 | default: | |
3725 | abort (); | |
f88c9eb0 | 3726 | } |
c0f3af97 | 3727 | |
c0f3af97 L |
3728 | /* The high 3 bits of the second VEX byte are 1's compliment |
3729 | of RXB bits from REX. */ | |
ddb62495 | 3730 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_space; |
c0f3af97 | 3731 | |
c0f3af97 L |
3732 | i.vex.bytes[2] = (w << 7 |
3733 | | register_specifier << 3 | |
3734 | | vector_length << 2 | |
35648716 | 3735 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3736 | } |
3737 | } | |
3738 | ||
5b7c81bd | 3739 | static INLINE bool |
e771e7c9 JB |
3740 | is_evex_encoding (const insn_template *t) |
3741 | { | |
7091c612 | 3742 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3743 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3744 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3745 | } |
3746 | ||
5b7c81bd | 3747 | static INLINE bool |
7a8655d2 JB |
3748 | is_any_vex_encoding (const insn_template *t) |
3749 | { | |
7b47a312 | 3750 | return t->opcode_modifier.vex || is_evex_encoding (t); |
7a8655d2 JB |
3751 | } |
3752 | ||
a5748e0d JB |
3753 | static unsigned int |
3754 | get_broadcast_bytes (const insn_template *t, bool diag) | |
3755 | { | |
3756 | unsigned int op, bytes; | |
3757 | const i386_operand_type *types; | |
3758 | ||
3759 | if (i.broadcast.type) | |
3760 | return i.broadcast.bytes = ((1 << (t->opcode_modifier.broadcast - 1)) | |
3761 | * i.broadcast.type); | |
3762 | ||
3763 | gas_assert (intel_syntax); | |
3764 | ||
3765 | for (op = 0; op < t->operands; ++op) | |
3766 | if (t->operand_types[op].bitfield.baseindex) | |
3767 | break; | |
3768 | ||
3769 | gas_assert (op < t->operands); | |
3770 | ||
3771 | if (t->opcode_modifier.evex | |
3772 | && t->opcode_modifier.evex != EVEXDYN) | |
3773 | switch (i.broadcast.bytes) | |
3774 | { | |
3775 | case 1: | |
3776 | if (t->operand_types[op].bitfield.word) | |
3777 | return 2; | |
3778 | /* Fall through. */ | |
3779 | case 2: | |
3780 | if (t->operand_types[op].bitfield.dword) | |
3781 | return 4; | |
3782 | /* Fall through. */ | |
3783 | case 4: | |
3784 | if (t->operand_types[op].bitfield.qword) | |
3785 | return 8; | |
3786 | /* Fall through. */ | |
3787 | case 8: | |
3788 | if (t->operand_types[op].bitfield.xmmword) | |
3789 | return 16; | |
3790 | if (t->operand_types[op].bitfield.ymmword) | |
3791 | return 32; | |
3792 | if (t->operand_types[op].bitfield.zmmword) | |
3793 | return 64; | |
3794 | /* Fall through. */ | |
3795 | default: | |
3796 | abort (); | |
3797 | } | |
3798 | ||
3799 | gas_assert (op + 1 < t->operands); | |
3800 | ||
3801 | if (t->operand_types[op + 1].bitfield.xmmword | |
3802 | + t->operand_types[op + 1].bitfield.ymmword | |
3803 | + t->operand_types[op + 1].bitfield.zmmword > 1) | |
3804 | { | |
3805 | types = &i.types[op + 1]; | |
3806 | diag = false; | |
3807 | } | |
3808 | else /* Ambiguous - guess with a preference to non-AVX512VL forms. */ | |
3809 | types = &t->operand_types[op]; | |
3810 | ||
3811 | if (types->bitfield.zmmword) | |
3812 | bytes = 64; | |
3813 | else if (types->bitfield.ymmword) | |
3814 | bytes = 32; | |
3815 | else | |
3816 | bytes = 16; | |
3817 | ||
3818 | if (diag) | |
3819 | as_warn (_("ambiguous broadcast for `%s', using %u-bit form"), | |
76d3f746 | 3820 | insn_name (t), bytes * 8); |
a5748e0d JB |
3821 | |
3822 | return bytes; | |
3823 | } | |
3824 | ||
43234a1e L |
3825 | /* Build the EVEX prefix. */ |
3826 | ||
3827 | static void | |
3828 | build_evex_prefix (void) | |
3829 | { | |
35648716 | 3830 | unsigned int register_specifier, w; |
43234a1e L |
3831 | rex_byte vrex_used = 0; |
3832 | ||
3833 | /* Check register specifier. */ | |
3834 | if (i.vex.register_specifier) | |
3835 | { | |
3836 | gas_assert ((i.vrex & REX_X) == 0); | |
3837 | ||
3838 | register_specifier = i.vex.register_specifier->reg_num; | |
3839 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3840 | register_specifier += 8; | |
3841 | /* The upper 16 registers are encoded in the fourth byte of the | |
3842 | EVEX prefix. */ | |
3843 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3844 | i.vex.bytes[3] = 0x8; | |
3845 | register_specifier = ~register_specifier & 0xf; | |
3846 | } | |
3847 | else | |
3848 | { | |
3849 | register_specifier = 0xf; | |
3850 | ||
3851 | /* Encode upper 16 vector index register in the fourth byte of | |
3852 | the EVEX prefix. */ | |
3853 | if (!(i.vrex & REX_X)) | |
3854 | i.vex.bytes[3] = 0x8; | |
3855 | else | |
3856 | vrex_used |= REX_X; | |
3857 | } | |
3858 | ||
43234a1e L |
3859 | /* 4 byte EVEX prefix. */ |
3860 | i.vex.length = 4; | |
3861 | i.vex.bytes[0] = 0x62; | |
3862 | ||
43234a1e L |
3863 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
3864 | bits from REX. */ | |
ddb62495 JB |
3865 | gas_assert (i.tm.opcode_space >= SPACE_0F); |
3866 | gas_assert (i.tm.opcode_space <= SPACE_EVEXMAP6); | |
3867 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_space; | |
43234a1e L |
3868 | |
3869 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3870 | REX_R bit in VREX. */ | |
3871 | if (!(i.vrex & REX_R)) | |
3872 | i.vex.bytes[1] |= 0x10; | |
3873 | else | |
3874 | vrex_used |= REX_R; | |
3875 | ||
3876 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3877 | { | |
3878 | /* When all operands are registers, the REX_X bit in REX is not | |
3879 | used. We reuse it to encode the upper 16 registers, which is | |
3880 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3881 | as 1's compliment. */ | |
3882 | if ((i.vrex & REX_B)) | |
3883 | { | |
3884 | vrex_used |= REX_B; | |
3885 | i.vex.bytes[1] &= ~0x40; | |
3886 | } | |
3887 | } | |
3888 | ||
3889 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3890 | i.vrex &= ~vrex_used; | |
3891 | gas_assert (i.vrex == 0); | |
3892 | ||
6865c043 L |
3893 | /* Check the REX.W bit and VEXW. */ |
3894 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3895 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3896 | else if (i.tm.opcode_modifier.vexw) | |
3897 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3898 | else | |
931d03b7 | 3899 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 3900 | |
43234a1e | 3901 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
3902 | i.vex.bytes[2] = ((w << 7) |
3903 | | (register_specifier << 3) | |
3904 | | 4 /* Encode the U bit. */ | |
3905 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
3906 | |
3907 | /* The fourth byte of the EVEX prefix. */ | |
3908 | /* The zeroing-masking bit. */ | |
6225c532 | 3909 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
3910 | i.vex.bytes[3] |= 0x80; |
3911 | ||
3912 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 3913 | if (i.rounding.type == rc_none) |
43234a1e L |
3914 | { |
3915 | /* Encode the vector length. */ | |
3916 | unsigned int vec_length; | |
3917 | ||
e771e7c9 JB |
3918 | if (!i.tm.opcode_modifier.evex |
3919 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3920 | { | |
56522fc5 | 3921 | unsigned int op; |
e771e7c9 | 3922 | |
c7213af9 L |
3923 | /* Determine vector length from the last multi-length vector |
3924 | operand. */ | |
56522fc5 | 3925 | for (op = i.operands; op--;) |
e771e7c9 JB |
3926 | if (i.tm.operand_types[op].bitfield.xmmword |
3927 | + i.tm.operand_types[op].bitfield.ymmword | |
3928 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3929 | { | |
3930 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3931 | { |
3932 | i.tm.opcode_modifier.evex = EVEX512; | |
3933 | break; | |
3934 | } | |
e771e7c9 | 3935 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3936 | { |
3937 | i.tm.opcode_modifier.evex = EVEX256; | |
3938 | break; | |
3939 | } | |
e771e7c9 | 3940 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3941 | { |
3942 | i.tm.opcode_modifier.evex = EVEX128; | |
3943 | break; | |
3944 | } | |
a5748e0d | 3945 | else if (i.broadcast.bytes && op == i.broadcast.operand) |
625cbd7a | 3946 | { |
a5748e0d | 3947 | switch (get_broadcast_bytes (&i.tm, true)) |
625cbd7a JB |
3948 | { |
3949 | case 64: | |
3950 | i.tm.opcode_modifier.evex = EVEX512; | |
3951 | break; | |
3952 | case 32: | |
3953 | i.tm.opcode_modifier.evex = EVEX256; | |
3954 | break; | |
3955 | case 16: | |
3956 | i.tm.opcode_modifier.evex = EVEX128; | |
3957 | break; | |
3958 | default: | |
c7213af9 | 3959 | abort (); |
625cbd7a | 3960 | } |
c7213af9 | 3961 | break; |
625cbd7a | 3962 | } |
e771e7c9 | 3963 | } |
c7213af9 | 3964 | |
56522fc5 | 3965 | if (op >= MAX_OPERANDS) |
c7213af9 | 3966 | abort (); |
e771e7c9 JB |
3967 | } |
3968 | ||
43234a1e L |
3969 | switch (i.tm.opcode_modifier.evex) |
3970 | { | |
3971 | case EVEXLIG: /* LL' is ignored */ | |
3972 | vec_length = evexlig << 5; | |
3973 | break; | |
3974 | case EVEX128: | |
3975 | vec_length = 0 << 5; | |
3976 | break; | |
3977 | case EVEX256: | |
3978 | vec_length = 1 << 5; | |
3979 | break; | |
3980 | case EVEX512: | |
3981 | vec_length = 2 << 5; | |
3982 | break; | |
3983 | default: | |
3984 | abort (); | |
3985 | break; | |
3986 | } | |
3987 | i.vex.bytes[3] |= vec_length; | |
3988 | /* Encode the broadcast bit. */ | |
a5748e0d | 3989 | if (i.broadcast.bytes) |
43234a1e L |
3990 | i.vex.bytes[3] |= 0x10; |
3991 | } | |
ca5312a2 JB |
3992 | else if (i.rounding.type != saeonly) |
3993 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 3994 | else |
ca5312a2 | 3995 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 3996 | |
6225c532 JB |
3997 | if (i.mask.reg) |
3998 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
3999 | } |
4000 | ||
65da13b5 L |
4001 | static void |
4002 | process_immext (void) | |
4003 | { | |
4004 | expressionS *exp; | |
4005 | ||
c0f3af97 | 4006 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4007 | which is coded in the same place as an 8-bit immediate field |
4008 | would be. Here we fake an 8-bit immediate operand from the | |
4009 | opcode suffix stored in tm.extension_opcode. | |
4010 | ||
c1e679ec | 4011 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4012 | 3 argument instructions. */ |
65da13b5 | 4013 | |
43234a1e | 4014 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4015 | && (i.operands <= 2 |
7a8655d2 | 4016 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4017 | && i.operands <= 4))); |
65da13b5 L |
4018 | |
4019 | exp = &im_expressions[i.imm_operands++]; | |
4020 | i.op[i.operands].imms = exp; | |
be1643ff | 4021 | i.types[i.operands].bitfield.imm8 = 1; |
65da13b5 L |
4022 | i.operands++; |
4023 | exp->X_op = O_constant; | |
4024 | exp->X_add_number = i.tm.extension_opcode; | |
4025 | i.tm.extension_opcode = None; | |
4026 | } | |
4027 | ||
42164a71 L |
4028 | |
4029 | static int | |
4030 | check_hle (void) | |
4031 | { | |
742732c7 | 4032 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4033 | { |
4034 | default: | |
4035 | abort (); | |
742732c7 JB |
4036 | case PrefixLock: |
4037 | case PrefixNone: | |
4038 | case PrefixNoTrack: | |
4039 | case PrefixRep: | |
165de32a | 4040 | as_bad (_("invalid instruction `%s' after `%s'"), |
76d3f746 | 4041 | insn_name (&i.tm), i.hle_prefix); |
42164a71 | 4042 | return 0; |
742732c7 | 4043 | case PrefixHLELock: |
42164a71 L |
4044 | if (i.prefix[LOCK_PREFIX]) |
4045 | return 1; | |
165de32a | 4046 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4047 | return 0; |
742732c7 | 4048 | case PrefixHLEAny: |
42164a71 | 4049 | return 1; |
742732c7 | 4050 | case PrefixHLERelease: |
42164a71 L |
4051 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4052 | { | |
4053 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
76d3f746 | 4054 | insn_name (&i.tm)); |
42164a71 L |
4055 | return 0; |
4056 | } | |
8dc0818e | 4057 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4058 | { |
4059 | as_bad (_("memory destination needed for instruction `%s'" | |
76d3f746 | 4060 | " after `xrelease'"), insn_name (&i.tm)); |
42164a71 L |
4061 | return 0; |
4062 | } | |
4063 | return 1; | |
4064 | } | |
4065 | } | |
4066 | ||
c8480b58 L |
4067 | /* Encode aligned vector move as unaligned vector move. */ |
4068 | ||
4069 | static void | |
4070 | encode_with_unaligned_vector_move (void) | |
4071 | { | |
4072 | switch (i.tm.base_opcode) | |
4073 | { | |
b3a9fe6f L |
4074 | case 0x28: /* Load instructions. */ |
4075 | case 0x29: /* Store instructions. */ | |
c8480b58 | 4076 | /* movaps/movapd/vmovaps/vmovapd. */ |
ddb62495 | 4077 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 | 4078 | && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66) |
b3a9fe6f | 4079 | i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1); |
c8480b58 | 4080 | break; |
b3a9fe6f L |
4081 | case 0x6f: /* Load instructions. */ |
4082 | case 0x7f: /* Store instructions. */ | |
c8480b58 | 4083 | /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */ |
ddb62495 | 4084 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 L |
4085 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66) |
4086 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
4087 | break; | |
4088 | default: | |
4089 | break; | |
4090 | } | |
4091 | } | |
4092 | ||
b6f8c7c4 L |
4093 | /* Try the shortest encoding by shortening operand size. */ |
4094 | ||
4095 | static void | |
4096 | optimize_encoding (void) | |
4097 | { | |
a0a1771e | 4098 | unsigned int j; |
b6f8c7c4 | 4099 | |
7fc69528 | 4100 | if (i.tm.mnem_off == MN_lea) |
fe134c65 JB |
4101 | { |
4102 | /* Optimize: -O: | |
4103 | lea symbol, %rN -> mov $symbol, %rN | |
4104 | lea (%rM), %rN -> mov %rM, %rN | |
4105 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4106 | ||
4107 | and in 32-bit mode for 16-bit addressing | |
4108 | ||
4109 | lea (%rM), %rN -> movzx %rM, %rN | |
4110 | ||
4111 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4112 | 32-bit (or less) destination. | |
4113 | */ | |
4114 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4115 | { | |
4116 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4117 | i.tm.opcode_modifier.size = SIZE32; | |
4118 | i.prefix[ADDR_PREFIX] = 0; | |
4119 | } | |
4120 | ||
4121 | if (!i.index_reg && !i.base_reg) | |
4122 | { | |
4123 | /* Handle: | |
4124 | lea symbol, %rN -> mov $symbol, %rN | |
4125 | */ | |
4126 | if (flag_code == CODE_64BIT) | |
4127 | { | |
4128 | /* Don't transform a relocation to a 16-bit one. */ | |
4129 | if (i.op[0].disps | |
4130 | && i.op[0].disps->X_op != O_constant | |
4131 | && i.op[1].regs->reg_type.bitfield.word) | |
4132 | return; | |
4133 | ||
4134 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4135 | || i.tm.opcode_modifier.size == SIZE32) | |
4136 | { | |
4137 | i.tm.base_opcode = 0xb8; | |
4138 | i.tm.opcode_modifier.modrm = 0; | |
4139 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4140 | i.types[0].bitfield.imm32 = 1; | |
4141 | else | |
4142 | { | |
4143 | i.tm.opcode_modifier.size = SIZE16; | |
4144 | i.types[0].bitfield.imm16 = 1; | |
4145 | } | |
4146 | } | |
4147 | else | |
4148 | { | |
4149 | /* Subject to further optimization below. */ | |
4150 | i.tm.base_opcode = 0xc7; | |
4151 | i.tm.extension_opcode = 0; | |
4152 | i.types[0].bitfield.imm32s = 1; | |
4153 | i.types[0].bitfield.baseindex = 0; | |
4154 | } | |
4155 | } | |
4156 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4157 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4158 | even couldn't express the relocation correctly. */ | |
4159 | else if (i.op[0].disps | |
4160 | && i.op[0].disps->X_op != O_constant | |
4161 | && ((!i.prefix[ADDR_PREFIX]) | |
4162 | != (flag_code == CODE_32BIT | |
4163 | ? i.op[1].regs->reg_type.bitfield.dword | |
4164 | : i.op[1].regs->reg_type.bitfield.word))) | |
4165 | return; | |
7772f168 JB |
4166 | /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit |
4167 | destination is going to grow encoding size. */ | |
4168 | else if (flag_code == CODE_16BIT | |
4169 | && (optimize <= 1 || optimize_for_space) | |
4170 | && !i.prefix[ADDR_PREFIX] | |
4171 | && i.op[1].regs->reg_type.bitfield.dword) | |
4172 | return; | |
fe134c65 JB |
4173 | else |
4174 | { | |
4175 | i.tm.base_opcode = 0xb8; | |
4176 | i.tm.opcode_modifier.modrm = 0; | |
4177 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4178 | i.types[0].bitfield.imm32 = 1; | |
4179 | else | |
4180 | i.types[0].bitfield.imm16 = 1; | |
4181 | ||
4182 | if (i.op[0].disps | |
4183 | && i.op[0].disps->X_op == O_constant | |
4184 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4185 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4186 | GCC 5. */ | |
4187 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4188 | i.op[0].disps->X_add_number &= 0xffff; |
4189 | } | |
4190 | ||
4191 | i.tm.operand_types[0] = i.types[0]; | |
4192 | i.imm_operands = 1; | |
4193 | if (!i.op[0].imms) | |
4194 | { | |
4195 | i.op[0].imms = &im_expressions[0]; | |
4196 | i.op[0].imms->X_op = O_absent; | |
4197 | } | |
4198 | } | |
4199 | else if (i.op[0].disps | |
4200 | && (i.op[0].disps->X_op != O_constant | |
4201 | || i.op[0].disps->X_add_number)) | |
4202 | return; | |
4203 | else | |
4204 | { | |
4205 | /* Handle: | |
4206 | lea (%rM), %rN -> mov %rM, %rN | |
4207 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4208 | lea (%rM), %rN -> movzx %rM, %rN | |
4209 | */ | |
4210 | const reg_entry *addr_reg; | |
4211 | ||
4212 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4213 | addr_reg = i.base_reg; | |
4214 | else if (!i.base_reg | |
4215 | && i.index_reg->reg_num != RegIZ | |
4216 | && !i.log2_scale_factor) | |
4217 | addr_reg = i.index_reg; | |
4218 | else | |
4219 | return; | |
4220 | ||
4221 | if (addr_reg->reg_type.bitfield.word | |
4222 | && i.op[1].regs->reg_type.bitfield.dword) | |
4223 | { | |
4224 | if (flag_code != CODE_32BIT) | |
4225 | return; | |
ddb62495 | 4226 | i.tm.opcode_space = SPACE_0F; |
fe134c65 JB |
4227 | i.tm.base_opcode = 0xb7; |
4228 | } | |
4229 | else | |
4230 | i.tm.base_opcode = 0x8b; | |
4231 | ||
4232 | if (addr_reg->reg_type.bitfield.dword | |
4233 | && i.op[1].regs->reg_type.bitfield.qword) | |
4234 | i.tm.opcode_modifier.size = SIZE32; | |
4235 | ||
4236 | i.op[0].regs = addr_reg; | |
4237 | i.reg_operands = 2; | |
4238 | } | |
4239 | ||
4240 | i.mem_operands = 0; | |
4241 | i.disp_operands = 0; | |
4242 | i.prefix[ADDR_PREFIX] = 0; | |
4243 | i.prefix[SEG_PREFIX] = 0; | |
4244 | i.seg[0] = NULL; | |
4245 | } | |
4246 | ||
b6f8c7c4 | 4247 | if (optimize_for_space |
7fc69528 | 4248 | && i.tm.mnem_off == MN_test |
b6f8c7c4 L |
4249 | && i.reg_operands == 1 |
4250 | && i.imm_operands == 1 | |
4251 | && !i.types[1].bitfield.byte | |
4252 | && i.op[0].imms->X_op == O_constant | |
7fc69528 | 4253 | && fits_in_imm7 (i.op[0].imms->X_add_number)) |
b6f8c7c4 L |
4254 | { |
4255 | /* Optimize: -Os: | |
4256 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4257 | */ | |
4258 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4259 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4260 | { | |
4261 | i.types[1].bitfield.byte = 1; | |
4262 | /* Ignore the suffix. */ | |
4263 | i.suffix = 0; | |
7697afb6 JB |
4264 | /* Convert to byte registers. */ |
4265 | if (i.types[1].bitfield.word) | |
4266 | j = 16; | |
4267 | else if (i.types[1].bitfield.dword) | |
4268 | j = 32; | |
4269 | else | |
4270 | j = 48; | |
4271 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4272 | j += 8; | |
4273 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4274 | } |
4275 | } | |
4276 | else if (flag_code == CODE_64BIT | |
ddb62495 | 4277 | && i.tm.opcode_space == SPACE_BASE |
d3d50934 L |
4278 | && ((i.types[1].bitfield.qword |
4279 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4280 | && i.imm_operands == 1 |
4281 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4282 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4283 | && i.tm.extension_opcode == None |
4284 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4285 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
7fc69528 | 4286 | && (i.tm.base_opcode == 0x24 |
b6f8c7c4 L |
4287 | || (i.tm.base_opcode == 0x80 |
4288 | && i.tm.extension_opcode == 0x4) | |
7fc69528 JB |
4289 | || i.tm.mnem_off == MN_test |
4290 | || ((i.tm.base_opcode | 1) == 0xc7 | |
b8364fa7 JB |
4291 | && i.tm.extension_opcode == 0x0))) |
4292 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4293 | && i.tm.base_opcode == 0x83 | |
4294 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4295 | || (i.types[0].bitfield.qword |
4296 | && ((i.reg_operands == 2 | |
4297 | && i.op[0].regs == i.op[1].regs | |
7fc69528 JB |
4298 | && (i.tm.mnem_off == MN_xor |
4299 | || i.tm.mnem_off == MN_sub)) | |
4300 | || i.tm.mnem_off == MN_clr)))) | |
b6f8c7c4 L |
4301 | { |
4302 | /* Optimize: -O: | |
4303 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4304 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4305 | testq $imm31, %r64 -> testl $imm31, %r32 |
4306 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4307 | subq %r64, %r64 -> subl %r32, %r32 | |
4308 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4309 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4310 | */ | |
04784e33 JB |
4311 | i.tm.opcode_modifier.size = SIZE32; |
4312 | if (i.imm_operands) | |
4313 | { | |
4314 | i.types[0].bitfield.imm32 = 1; | |
4315 | i.types[0].bitfield.imm32s = 0; | |
4316 | i.types[0].bitfield.imm64 = 0; | |
4317 | } | |
4318 | else | |
4319 | { | |
4320 | i.types[0].bitfield.dword = 1; | |
4321 | i.types[0].bitfield.qword = 0; | |
4322 | } | |
4323 | i.types[1].bitfield.dword = 1; | |
4324 | i.types[1].bitfield.qword = 0; | |
7fc69528 | 4325 | if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea) |
b6f8c7c4 L |
4326 | { |
4327 | /* Handle | |
4328 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4329 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4330 | */ | |
4331 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4332 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4333 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
507916b8 | 4334 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4335 | { |
4336 | /* Handle | |
4337 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4338 | */ | |
507916b8 | 4339 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4340 | i.tm.extension_opcode = None; |
507916b8 | 4341 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4342 | i.tm.opcode_modifier.modrm = 0; |
4343 | } | |
4344 | } | |
4345 | } | |
5641ec01 JB |
4346 | else if (optimize > 1 |
4347 | && !optimize_for_space | |
4348 | && i.reg_operands == 2 | |
4349 | && i.op[0].regs == i.op[1].regs | |
7fc69528 | 4350 | && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or) |
5641ec01 JB |
4351 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) |
4352 | { | |
4353 | /* Optimize: -O2: | |
4354 | andb %rN, %rN -> testb %rN, %rN | |
4355 | andw %rN, %rN -> testw %rN, %rN | |
4356 | andq %rN, %rN -> testq %rN, %rN | |
4357 | orb %rN, %rN -> testb %rN, %rN | |
4358 | orw %rN, %rN -> testw %rN, %rN | |
4359 | orq %rN, %rN -> testq %rN, %rN | |
4360 | ||
4361 | and outside of 64-bit mode | |
4362 | ||
4363 | andl %rN, %rN -> testl %rN, %rN | |
4364 | orl %rN, %rN -> testl %rN, %rN | |
4365 | */ | |
4366 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4367 | } | |
ad2f4436 JB |
4368 | else if (i.tm.base_opcode == 0xba |
4369 | && i.tm.opcode_space == SPACE_0F | |
4370 | && i.reg_operands == 1 | |
4371 | && i.op[0].imms->X_op == O_constant | |
4372 | && i.op[0].imms->X_add_number >= 0) | |
4373 | { | |
4374 | /* Optimize: -O: | |
4375 | btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16) | |
4376 | btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8) | |
4377 | btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4378 | ||
4379 | With <BT> one of bts, btr, and bts also: | |
4380 | <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16) | |
4381 | <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4382 | */ | |
4383 | switch (flag_code) | |
4384 | { | |
4385 | case CODE_64BIT: | |
4386 | if (i.tm.extension_opcode != 4) | |
4387 | break; | |
4388 | if (i.types[1].bitfield.qword | |
4389 | && i.op[0].imms->X_add_number < 32 | |
4390 | && !(i.op[1].regs->reg_flags & RegRex)) | |
4391 | i.tm.opcode_modifier.size = SIZE32; | |
4392 | /* Fall through. */ | |
4393 | case CODE_32BIT: | |
4394 | if (i.types[1].bitfield.word | |
4395 | && i.op[0].imms->X_add_number < 16) | |
4396 | i.tm.opcode_modifier.size = SIZE32; | |
4397 | break; | |
4398 | case CODE_16BIT: | |
4399 | if (i.op[0].imms->X_add_number < 16) | |
4400 | i.tm.opcode_modifier.size = SIZE16; | |
4401 | break; | |
4402 | } | |
4403 | } | |
99112332 | 4404 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4405 | && i.op[0].regs == i.op[1].regs |
4406 | && !i.types[2].bitfield.xmmword | |
4407 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4408 | || ((!i.mask.reg || i.mask.zeroing) |
e771e7c9 | 4409 | && is_evex_encoding (&i.tm) |
80c34c38 | 4410 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4411 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4412 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4413 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4414 | && i.types[2].bitfield.ymmword)))) |
ddb62495 | 4415 | && i.tm.opcode_space == SPACE_0F |
5844ccaa JB |
4416 | && ((i.tm.base_opcode | 2) == 0x57 |
4417 | || i.tm.base_opcode == 0xdf | |
4418 | || i.tm.base_opcode == 0xef | |
4419 | || (i.tm.base_opcode | 3) == 0xfb | |
4420 | || i.tm.base_opcode == 0x42 | |
4421 | || i.tm.base_opcode == 0x47)) | |
b6f8c7c4 | 4422 | { |
99112332 | 4423 | /* Optimize: -O1: |
8305403a L |
4424 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4425 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4426 | EVEX VOP %zmmM, %zmmM, %zmmN |
4427 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4428 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4429 | EVEX VOP %ymmM, %ymmM, %ymmN |
4430 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4431 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4432 | VEX VOP %ymmM, %ymmM, %ymmN |
4433 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4434 | VOP, one of vpandn and vpxor: | |
4435 | VEX VOP %ymmM, %ymmM, %ymmN | |
4436 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4437 | VOP, one of vpandnd and vpandnq: | |
4438 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4439 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4440 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4441 | EVEX VOP %ymmM, %ymmM, %ymmN |
4442 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4443 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4444 | VOP, one of vpxord and vpxorq: |
4445 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4446 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4447 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4448 | EVEX VOP %ymmM, %ymmM, %ymmN |
4449 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4450 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4451 | VOP, one of kxord and kxorq: |
4452 | VEX VOP %kM, %kM, %kN | |
4453 | -> VEX kxorw %kM, %kM, %kN | |
4454 | VOP, one of kandnd and kandnq: | |
4455 | VEX VOP %kM, %kM, %kN | |
4456 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4457 | */ |
e771e7c9 | 4458 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4459 | { |
7b1d7ca1 | 4460 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4461 | { |
4462 | i.tm.opcode_modifier.vex = VEX128; | |
4463 | i.tm.opcode_modifier.vexw = VEXW0; | |
4464 | i.tm.opcode_modifier.evex = 0; | |
4465 | } | |
7b1d7ca1 | 4466 | else if (optimize > 1) |
dd22218c L |
4467 | i.tm.opcode_modifier.evex = EVEX128; |
4468 | else | |
4469 | return; | |
b6f8c7c4 | 4470 | } |
f74a6307 | 4471 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4472 | { |
35648716 | 4473 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4474 | i.tm.opcode_modifier.vexw = VEXW0; |
4475 | } | |
b6f8c7c4 L |
4476 | else |
4477 | i.tm.opcode_modifier.vex = VEX128; | |
4478 | ||
4479 | if (i.tm.opcode_modifier.vex) | |
4480 | for (j = 0; j < 3; j++) | |
4481 | { | |
4482 | i.types[j].bitfield.xmmword = 1; | |
4483 | i.types[j].bitfield.ymmword = 0; | |
4484 | } | |
4485 | } | |
392a5972 | 4486 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4487 | && !i.types[0].bitfield.zmmword |
392a5972 | 4488 | && !i.types[1].bitfield.zmmword |
6225c532 | 4489 | && !i.mask.reg |
a5748e0d | 4490 | && !i.broadcast.bytes |
97ed31ae | 4491 | && is_evex_encoding (&i.tm) |
35648716 JB |
4492 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4493 | || (i.tm.base_opcode & ~4) == 0xdb | |
4494 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4495 | && i.tm.extension_opcode == None) |
4496 | { | |
4497 | /* Optimize: -O1: | |
4498 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4499 | vmovdqu32 and vmovdqu64: | |
4500 | EVEX VOP %xmmM, %xmmN | |
4501 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4502 | EVEX VOP %ymmM, %ymmN | |
4503 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4504 | EVEX VOP %xmmM, mem | |
4505 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4506 | EVEX VOP %ymmM, mem | |
4507 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4508 | EVEX VOP mem, %xmmN | |
4509 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4510 | EVEX VOP mem, %ymmN | |
4511 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4512 | VOP, one of vpand, vpandn, vpor, vpxor: |
4513 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4514 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4515 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4516 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4517 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4518 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4519 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4520 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4521 | */ |
a0a1771e | 4522 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4523 | if (operand_type_check (i.types[j], disp) |
4524 | && i.op[j].disps->X_op == O_constant) | |
4525 | { | |
4526 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4527 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4528 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4529 | int evex_disp8, vex_disp8; | |
4530 | unsigned int memshift = i.memshift; | |
4531 | offsetT n = i.op[j].disps->X_add_number; | |
4532 | ||
4533 | evex_disp8 = fits_in_disp8 (n); | |
4534 | i.memshift = 0; | |
4535 | vex_disp8 = fits_in_disp8 (n); | |
4536 | if (evex_disp8 != vex_disp8) | |
4537 | { | |
4538 | i.memshift = memshift; | |
4539 | return; | |
4540 | } | |
4541 | ||
4542 | i.types[j].bitfield.disp8 = vex_disp8; | |
4543 | break; | |
4544 | } | |
35648716 JB |
4545 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4546 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4547 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4548 | i.tm.opcode_modifier.vex |
4549 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4550 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4551 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4552 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4553 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4554 | i.tm.opcode_modifier.evex = 0; |
4555 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4556 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4557 | i.tm.opcode_modifier.disp8memshift = 0; |
4558 | i.memshift = 0; | |
a0a1771e JB |
4559 | if (j < i.operands) |
4560 | i.types[j].bitfield.disp8 | |
4561 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4562 | } |
b6f8c7c4 L |
4563 | } |
4564 | ||
ae531041 L |
4565 | /* Return non-zero for load instruction. */ |
4566 | ||
4567 | static int | |
4568 | load_insn_p (void) | |
4569 | { | |
4570 | unsigned int dest; | |
4571 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4572 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4573 | ||
4574 | if (!any_vex_p) | |
4575 | { | |
ef07be45 CL |
4576 | /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, |
4577 | bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ | |
255571cd | 4578 | if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE) |
ae531041 L |
4579 | return 0; |
4580 | ||
389d00a5 | 4581 | /* pop. */ |
6d86a545 | 4582 | if (i.tm.mnem_off == MN_pop) |
389d00a5 JB |
4583 | return 1; |
4584 | } | |
4585 | ||
ddb62495 | 4586 | if (i.tm.opcode_space == SPACE_BASE) |
389d00a5 JB |
4587 | { |
4588 | /* popf, popa. */ | |
4589 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 4590 | || i.tm.base_opcode == 0x61) |
ae531041 L |
4591 | return 1; |
4592 | ||
4593 | /* movs, cmps, lods, scas. */ | |
4594 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4595 | return 1; | |
4596 | ||
a09f656b | 4597 | /* outs, xlatb. */ |
4598 | if (base_opcode == 0x6f | |
4599 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4600 | return 1; |
a09f656b | 4601 | /* NB: For AMD-specific insns with implicit memory operands, |
4602 | they're intentionally not covered. */ | |
ae531041 L |
4603 | } |
4604 | ||
4605 | /* No memory operand. */ | |
4606 | if (!i.mem_operands) | |
4607 | return 0; | |
4608 | ||
4609 | if (any_vex_p) | |
4610 | { | |
7fc69528 | 4611 | if (i.tm.mnem_off == MN_vldmxcsr) |
ae531041 L |
4612 | return 1; |
4613 | } | |
ddb62495 | 4614 | else if (i.tm.opcode_space == SPACE_BASE) |
ae531041 L |
4615 | { |
4616 | /* test, not, neg, mul, imul, div, idiv. */ | |
aa4c197d | 4617 | if (base_opcode == 0xf7 && i.tm.extension_opcode != 1) |
ae531041 L |
4618 | return 1; |
4619 | ||
4620 | /* inc, dec. */ | |
4621 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
4622 | return 1; | |
4623 | ||
4624 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
4625 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
4626 | return 1; | |
4627 | ||
ae531041 | 4628 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
aa4c197d | 4629 | if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3) |
ae531041 L |
4630 | && i.tm.extension_opcode != 6) |
4631 | return 1; | |
4632 | ||
ae531041 | 4633 | /* Check for x87 instructions. */ |
aa4c197d | 4634 | if ((base_opcode | 6) == 0xdf) |
ae531041 L |
4635 | { |
4636 | /* Skip fst, fstp, fstenv, fstcw. */ | |
4637 | if (i.tm.base_opcode == 0xd9 | |
4638 | && (i.tm.extension_opcode == 2 | |
4639 | || i.tm.extension_opcode == 3 | |
4640 | || i.tm.extension_opcode == 6 | |
4641 | || i.tm.extension_opcode == 7)) | |
4642 | return 0; | |
4643 | ||
4644 | /* Skip fisttp, fist, fistp, fstp. */ | |
4645 | if (i.tm.base_opcode == 0xdb | |
4646 | && (i.tm.extension_opcode == 1 | |
4647 | || i.tm.extension_opcode == 2 | |
4648 | || i.tm.extension_opcode == 3 | |
4649 | || i.tm.extension_opcode == 7)) | |
4650 | return 0; | |
4651 | ||
4652 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
4653 | if (i.tm.base_opcode == 0xdd | |
4654 | && (i.tm.extension_opcode == 1 | |
4655 | || i.tm.extension_opcode == 2 | |
4656 | || i.tm.extension_opcode == 3 | |
4657 | || i.tm.extension_opcode == 6 | |
4658 | || i.tm.extension_opcode == 7)) | |
4659 | return 0; | |
4660 | ||
4661 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
4662 | if (i.tm.base_opcode == 0xdf | |
4663 | && (i.tm.extension_opcode == 1 | |
4664 | || i.tm.extension_opcode == 2 | |
4665 | || i.tm.extension_opcode == 3 | |
4666 | || i.tm.extension_opcode == 6 | |
4667 | || i.tm.extension_opcode == 7)) | |
4668 | return 0; | |
4669 | ||
4670 | return 1; | |
4671 | } | |
4672 | } | |
ddb62495 | 4673 | else if (i.tm.opcode_space == SPACE_0F) |
389d00a5 JB |
4674 | { |
4675 | /* bt, bts, btr, btc. */ | |
4676 | if (i.tm.base_opcode == 0xba | |
aa4c197d | 4677 | && (i.tm.extension_opcode | 3) == 7) |
389d00a5 JB |
4678 | return 1; |
4679 | ||
4680 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
4681 | if (i.tm.base_opcode == 0xc7 | |
4682 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
4683 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
4684 | || i.tm.extension_opcode == 6)) | |
4685 | return 1; | |
4686 | ||
4687 | /* fxrstor, ldmxcsr, xrstor. */ | |
4688 | if (i.tm.base_opcode == 0xae | |
4689 | && (i.tm.extension_opcode == 1 | |
4690 | || i.tm.extension_opcode == 2 | |
4691 | || i.tm.extension_opcode == 5)) | |
4692 | return 1; | |
4693 | ||
4694 | /* lgdt, lidt, lmsw. */ | |
4695 | if (i.tm.base_opcode == 0x01 | |
4696 | && (i.tm.extension_opcode == 2 | |
4697 | || i.tm.extension_opcode == 3 | |
4698 | || i.tm.extension_opcode == 6)) | |
4699 | return 1; | |
4700 | } | |
ae531041 L |
4701 | |
4702 | dest = i.operands - 1; | |
4703 | ||
4704 | /* Check fake imm8 operand and 3 source operands. */ | |
4705 | if ((i.tm.opcode_modifier.immext | |
aa180741 | 4706 | || i.reg_operands + i.mem_operands == 4) |
ae531041 L |
4707 | && i.types[dest].bitfield.imm8) |
4708 | dest--; | |
4709 | ||
389d00a5 | 4710 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
ddb62495 | 4711 | if (i.tm.opcode_space == SPACE_BASE |
aa4c197d | 4712 | && ((base_opcode | 0x38) == 0x39 |
389d00a5 JB |
4713 | || (base_opcode | 2) == 0x87)) |
4714 | return 1; | |
4715 | ||
7fc69528 | 4716 | if (i.tm.mnem_off == MN_xadd) |
ae531041 L |
4717 | return 1; |
4718 | ||
4719 | /* Check for load instruction. */ | |
4720 | return (i.types[dest].bitfield.class != ClassNone | |
4721 | || i.types[dest].bitfield.instance == Accum); | |
4722 | } | |
4723 | ||
4724 | /* Output lfence, 0xfaee8, after instruction. */ | |
4725 | ||
4726 | static void | |
4727 | insert_lfence_after (void) | |
4728 | { | |
4729 | if (lfence_after_load && load_insn_p ()) | |
4730 | { | |
a09f656b | 4731 | /* There are also two REP string instructions that require |
4732 | special treatment. Specifically, the compare string (CMPS) | |
4733 | and scan string (SCAS) instructions set EFLAGS in a manner | |
4734 | that depends on the data being compared/scanned. When used | |
4735 | with a REP prefix, the number of iterations may therefore | |
4736 | vary depending on this data. If the data is a program secret | |
4737 | chosen by the adversary using an LVI method, | |
4738 | then this data-dependent behavior may leak some aspect | |
4739 | of the secret. */ | |
aa4c197d | 4740 | if (((i.tm.base_opcode | 0x9) == 0xaf) |
a09f656b | 4741 | && i.prefix[REP_PREFIX]) |
4742 | { | |
4743 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
76d3f746 | 4744 | insn_name (&i.tm)); |
a09f656b | 4745 | } |
ae531041 L |
4746 | char *p = frag_more (3); |
4747 | *p++ = 0xf; | |
4748 | *p++ = 0xae; | |
4749 | *p = 0xe8; | |
4750 | } | |
4751 | } | |
4752 | ||
4753 | /* Output lfence, 0xfaee8, before instruction. */ | |
4754 | ||
4755 | static void | |
4756 | insert_lfence_before (void) | |
4757 | { | |
4758 | char *p; | |
4759 | ||
ddb62495 | 4760 | if (i.tm.opcode_space != SPACE_BASE) |
ae531041 L |
4761 | return; |
4762 | ||
4763 | if (i.tm.base_opcode == 0xff | |
4764 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
4765 | { | |
4766 | /* Insert lfence before indirect branch if needed. */ | |
4767 | ||
4768 | if (lfence_before_indirect_branch == lfence_branch_none) | |
4769 | return; | |
4770 | ||
4771 | if (i.operands != 1) | |
4772 | abort (); | |
4773 | ||
4774 | if (i.reg_operands == 1) | |
4775 | { | |
4776 | /* Indirect branch via register. Don't insert lfence with | |
4777 | -mlfence-after-load=yes. */ | |
4778 | if (lfence_after_load | |
4779 | || lfence_before_indirect_branch == lfence_branch_memory) | |
4780 | return; | |
4781 | } | |
4782 | else if (i.mem_operands == 1 | |
4783 | && lfence_before_indirect_branch != lfence_branch_register) | |
4784 | { | |
4785 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
76d3f746 | 4786 | insn_name (&i.tm)); |
ae531041 L |
4787 | return; |
4788 | } | |
4789 | else | |
4790 | return; | |
4791 | ||
4792 | if (last_insn.kind != last_insn_other | |
4793 | && last_insn.seg == now_seg) | |
4794 | { | |
4795 | as_warn_where (last_insn.file, last_insn.line, | |
4796 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), | |
76d3f746 | 4797 | last_insn.name, insn_name (&i.tm)); |
ae531041 L |
4798 | return; |
4799 | } | |
4800 | ||
4801 | p = frag_more (3); | |
4802 | *p++ = 0xf; | |
4803 | *p++ = 0xae; | |
4804 | *p = 0xe8; | |
4805 | return; | |
4806 | } | |
4807 | ||
503648e4 | 4808 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 | 4809 | if (lfence_before_ret != lfence_before_ret_none |
aa4c197d | 4810 | && (i.tm.base_opcode | 1) == 0xc3) |
ae531041 L |
4811 | { |
4812 | if (last_insn.kind != last_insn_other | |
4813 | && last_insn.seg == now_seg) | |
4814 | { | |
4815 | as_warn_where (last_insn.file, last_insn.line, | |
4816 | _("`%s` skips -mlfence-before-ret on `%s`"), | |
76d3f746 | 4817 | last_insn.name, insn_name (&i.tm)); |
ae531041 L |
4818 | return; |
4819 | } | |
a09f656b | 4820 | |
a09f656b | 4821 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 4822 | char prefix = flag_code == CODE_64BIT |
4823 | ? 0x48 | |
4824 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 4825 | |
4826 | if (lfence_before_ret == lfence_before_ret_not) | |
4827 | { | |
4828 | /* not: 0xf71424, may add prefix | |
4829 | for operand size override or 64-bit code. */ | |
4830 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
4831 | if (prefix) | |
4832 | *p++ = prefix; | |
ae531041 L |
4833 | *p++ = 0xf7; |
4834 | *p++ = 0x14; | |
4835 | *p++ = 0x24; | |
a09f656b | 4836 | if (prefix) |
4837 | *p++ = prefix; | |
ae531041 L |
4838 | *p++ = 0xf7; |
4839 | *p++ = 0x14; | |
4840 | *p++ = 0x24; | |
4841 | } | |
a09f656b | 4842 | else |
4843 | { | |
4844 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
4845 | if (prefix) | |
4846 | *p++ = prefix; | |
4847 | if (lfence_before_ret == lfence_before_ret_or) | |
4848 | { | |
4849 | /* or: 0x830c2400, may add prefix | |
4850 | for operand size override or 64-bit code. */ | |
4851 | *p++ = 0x83; | |
4852 | *p++ = 0x0c; | |
4853 | } | |
4854 | else | |
4855 | { | |
4856 | /* shl: 0xc1242400, may add prefix | |
4857 | for operand size override or 64-bit code. */ | |
4858 | *p++ = 0xc1; | |
4859 | *p++ = 0x24; | |
4860 | } | |
4861 | ||
4862 | *p++ = 0x24; | |
4863 | *p++ = 0x0; | |
4864 | } | |
4865 | ||
ae531041 L |
4866 | *p++ = 0xf; |
4867 | *p++ = 0xae; | |
4868 | *p = 0xe8; | |
4869 | } | |
4870 | } | |
4871 | ||
04784e33 JB |
4872 | /* Helper for md_assemble() to decide whether to prepare for a possible 2nd |
4873 | parsing pass. Instead of introducing a rarely use new insn attribute this | |
4874 | utilizes a common pattern between affected templates. It is deemed | |
4875 | acceptable that this will lead to unnecessary pass 2 preparations in a | |
4876 | limited set of cases. */ | |
4877 | static INLINE bool may_need_pass2 (const insn_template *t) | |
4878 | { | |
4879 | return t->opcode_modifier.sse2avx | |
4880 | /* Note that all SSE2AVX templates have at least one operand. */ | |
a28fedbc | 4881 | ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD |
ddb62495 | 4882 | : (t->opcode_space == SPACE_0F |
a28fedbc | 4883 | && (t->base_opcode | 1) == 0xbf) |
ddb62495 | 4884 | || (t->opcode_space == SPACE_BASE |
a28fedbc | 4885 | && t->base_opcode == 0x63); |
04784e33 JB |
4886 | } |
4887 | ||
252b5132 RH |
4888 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4889 | machine dependent instruction. This function is supposed to emit | |
4890 | the frags/bytes it assembles to. */ | |
4891 | ||
4892 | void | |
65da13b5 | 4893 | md_assemble (char *line) |
252b5132 | 4894 | { |
40fb9820 | 4895 | unsigned int j; |
9db83a32 | 4896 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL; |
04784e33 JB |
4897 | const char *end, *pass1_mnem = NULL; |
4898 | enum i386_error pass1_err = 0; | |
d3ce72d0 | 4899 | const insn_template *t; |
252b5132 | 4900 | |
47926f60 | 4901 | /* Initialize globals. */ |
04784e33 JB |
4902 | current_templates = NULL; |
4903 | retry: | |
252b5132 | 4904 | memset (&i, '\0', sizeof (i)); |
ca5312a2 | 4905 | i.rounding.type = rc_none; |
252b5132 | 4906 | for (j = 0; j < MAX_OPERANDS; j++) |
1ae12ab7 | 4907 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4908 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4909 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4910 | save_stack_p = save_stack; |
252b5132 RH |
4911 | |
4912 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4913 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4914 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4915 | |
5317ad2c JB |
4916 | end = parse_insn (line, mnemonic); |
4917 | if (end == NULL) | |
04784e33 JB |
4918 | { |
4919 | if (pass1_mnem != NULL) | |
4920 | goto match_error; | |
9db83a32 JB |
4921 | if (i.error != no_error) |
4922 | { | |
4923 | gas_assert (current_templates != NULL); | |
4924 | if (may_need_pass2 (current_templates->start) && !i.suffix) | |
4925 | goto no_match; | |
4926 | /* No point in trying a 2nd pass - it'll only find the same suffix | |
4927 | again. */ | |
4928 | mnem_suffix = i.suffix; | |
4929 | goto match_error; | |
4930 | } | |
04784e33 JB |
4931 | return; |
4932 | } | |
6d86a545 JB |
4933 | t = current_templates->start; |
4934 | if (may_need_pass2 (t)) | |
04784e33 JB |
4935 | { |
4936 | /* Make a copy of the full line in case we need to retry. */ | |
4937 | copy = xstrdup (line); | |
4938 | } | |
5317ad2c | 4939 | line += end - line; |
83b16ac6 | 4940 | mnem_suffix = i.suffix; |
252b5132 | 4941 | |
29b0f896 | 4942 | line = parse_operands (line, mnemonic); |
ee86248c | 4943 | this_operand = -1; |
29b0f896 | 4944 | if (line == NULL) |
04784e33 JB |
4945 | { |
4946 | free (copy); | |
4947 | return; | |
4948 | } | |
252b5132 | 4949 | |
29b0f896 AM |
4950 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4951 | operands at hand. */ | |
4952 | ||
b630c145 | 4953 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 | 4954 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
b0e8fa7f TJ |
4955 | "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse |
4956 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
4957 | that the immediate segment precedes the offset consistently in Intel and | |
4958 | AT&T modes. */ | |
4d456e3d L |
4959 | if (intel_syntax |
4960 | && i.operands > 1 | |
6d86a545 JB |
4961 | && (t->mnem_off != MN_bound) |
4962 | && !startswith (mnemonic, "invlpg") | |
d34049e8 ML |
4963 | && !startswith (mnemonic, "monitor") |
4964 | && !startswith (mnemonic, "mwait") | |
6d86a545 | 4965 | && (t->mnem_off != MN_pvalidate) |
d34049e8 | 4966 | && !startswith (mnemonic, "rmp") |
6d86a545 JB |
4967 | && (t->mnem_off != MN_tpause) |
4968 | && (t->mnem_off != MN_umwait) | |
47c0279b JB |
4969 | && !(i.operands == 2 |
4970 | && operand_type_check (i.types[0], imm) | |
40fb9820 | 4971 | && operand_type_check (i.types[1], imm))) |
29b0f896 AM |
4972 | swap_operands (); |
4973 | ||
ec56d5c0 JB |
4974 | /* The order of the immediates should be reversed |
4975 | for 2 immediates extrq and insertq instructions */ | |
4976 | if (i.imm_operands == 2 | |
6d86a545 | 4977 | && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) |
ec56d5c0 JB |
4978 | swap_2_operands (0, 1); |
4979 | ||
29b0f896 AM |
4980 | if (i.imm_operands) |
4981 | optimize_imm (); | |
4982 | ||
6d86a545 JB |
4983 | if (i.disp_operands && !want_disp32 (t) |
4984 | && (!t->opcode_modifier.jump | |
9386188e | 4985 | || i.jumpabsolute || i.types[0].bitfield.baseindex)) |
cce08655 JB |
4986 | { |
4987 | for (j = 0; j < i.operands; ++j) | |
4988 | { | |
4989 | const expressionS *exp = i.op[j].disps; | |
4990 | ||
4991 | if (!operand_type_check (i.types[j], disp)) | |
4992 | continue; | |
4993 | ||
4994 | if (exp->X_op != O_constant) | |
4995 | continue; | |
4996 | ||
4997 | /* Since displacement is signed extended to 64bit, don't allow | |
a775efc8 | 4998 | disp32 if it is out of range. */ |
cce08655 JB |
4999 | if (fits_in_signed_long (exp->X_add_number)) |
5000 | continue; | |
5001 | ||
a775efc8 | 5002 | i.types[j].bitfield.disp32 = 0; |
cce08655 JB |
5003 | if (i.types[j].bitfield.baseindex) |
5004 | { | |
f493c217 AM |
5005 | as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"), |
5006 | (uint64_t) exp->X_add_number); | |
cce08655 JB |
5007 | return; |
5008 | } | |
5009 | } | |
5010 | } | |
5011 | ||
b300c311 L |
5012 | /* Don't optimize displacement for movabs since it only takes 64bit |
5013 | displacement. */ | |
5014 | if (i.disp_operands | |
1a42a9fe | 5015 | && i.disp_encoding <= disp_encoding_8bit |
862be3fb L |
5016 | && (flag_code != CODE_64BIT |
5017 | || strcmp (mnemonic, "movabs") != 0)) | |
5018 | optimize_disp (); | |
29b0f896 AM |
5019 | |
5020 | /* Next, we find a template that matches the given insn, | |
5021 | making sure the overlap of the given operands types is consistent | |
5022 | with the template operand types. */ | |
252b5132 | 5023 | |
83b16ac6 | 5024 | if (!(t = match_template (mnem_suffix))) |
04784e33 JB |
5025 | { |
5026 | const char *err_msg; | |
5027 | ||
5028 | if (copy && !mnem_suffix) | |
5029 | { | |
5030 | line = copy; | |
5031 | copy = NULL; | |
9db83a32 | 5032 | no_match: |
04784e33 | 5033 | pass1_err = i.error; |
76d3f746 | 5034 | pass1_mnem = insn_name (current_templates->start); |
04784e33 JB |
5035 | goto retry; |
5036 | } | |
9db83a32 JB |
5037 | |
5038 | /* If a non-/only-64bit template (group) was found in pass 1, and if | |
5039 | _some_ template (group) was found in pass 2, squash pass 1's | |
5040 | error. */ | |
5041 | if (pass1_err == unsupported_64bit) | |
5042 | pass1_mnem = NULL; | |
5043 | ||
04784e33 | 5044 | match_error: |
9db83a32 JB |
5045 | free (copy); |
5046 | ||
04784e33 JB |
5047 | switch (pass1_mnem ? pass1_err : i.error) |
5048 | { | |
5049 | default: | |
5050 | abort (); | |
5051 | case operand_size_mismatch: | |
5052 | err_msg = _("operand size mismatch"); | |
5053 | break; | |
5054 | case operand_type_mismatch: | |
5055 | err_msg = _("operand type mismatch"); | |
5056 | break; | |
5057 | case register_type_mismatch: | |
5058 | err_msg = _("register type mismatch"); | |
5059 | break; | |
5060 | case number_of_operands_mismatch: | |
5061 | err_msg = _("number of operands mismatch"); | |
5062 | break; | |
5063 | case invalid_instruction_suffix: | |
5064 | err_msg = _("invalid instruction suffix"); | |
5065 | break; | |
5066 | case bad_imm4: | |
5067 | err_msg = _("constant doesn't fit in 4 bits"); | |
5068 | break; | |
5069 | case unsupported_with_intel_mnemonic: | |
5070 | err_msg = _("unsupported with Intel mnemonic"); | |
5071 | break; | |
5072 | case unsupported_syntax: | |
5073 | err_msg = _("unsupported syntax"); | |
5074 | break; | |
5075 | case unsupported: | |
5076 | as_bad (_("unsupported instruction `%s'"), | |
76d3f746 | 5077 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
04784e33 | 5078 | return; |
9db83a32 JB |
5079 | case unsupported_on_arch: |
5080 | as_bad (_("`%s' is not supported on `%s%s'"), | |
76d3f746 | 5081 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start), |
9db83a32 JB |
5082 | cpu_arch_name ? cpu_arch_name : default_arch, |
5083 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
5084 | return; | |
5085 | case unsupported_64bit: | |
5086 | if (ISLOWER (mnem_suffix)) | |
e8b4b7b2 NC |
5087 | { |
5088 | if (flag_code == CODE_64BIT) | |
5089 | as_bad (_("`%s%c' is not supported in 64-bit mode"), | |
76d3f746 | 5090 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start), |
e8b4b7b2 NC |
5091 | mnem_suffix); |
5092 | else | |
5093 | as_bad (_("`%s%c' is only supported in 64-bit mode"), | |
76d3f746 | 5094 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start), |
e8b4b7b2 NC |
5095 | mnem_suffix); |
5096 | } | |
9db83a32 | 5097 | else |
e8b4b7b2 NC |
5098 | { |
5099 | if (flag_code == CODE_64BIT) | |
5100 | as_bad (_("`%s' is not supported in 64-bit mode"), | |
76d3f746 | 5101 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
e8b4b7b2 NC |
5102 | else |
5103 | as_bad (_("`%s' is only supported in 64-bit mode"), | |
76d3f746 | 5104 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
e8b4b7b2 | 5105 | } |
9db83a32 | 5106 | return; |
04784e33 JB |
5107 | case invalid_sib_address: |
5108 | err_msg = _("invalid SIB address"); | |
5109 | break; | |
5110 | case invalid_vsib_address: | |
5111 | err_msg = _("invalid VSIB address"); | |
5112 | break; | |
5113 | case invalid_vector_register_set: | |
5114 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5115 | break; | |
5116 | case invalid_tmm_register_set: | |
5117 | err_msg = _("all tmm registers must be distinct"); | |
5118 | break; | |
5119 | case invalid_dest_and_src_register_set: | |
5120 | err_msg = _("destination and source registers must be distinct"); | |
5121 | break; | |
5122 | case unsupported_vector_index_register: | |
5123 | err_msg = _("unsupported vector index register"); | |
5124 | break; | |
5125 | case unsupported_broadcast: | |
5126 | err_msg = _("unsupported broadcast"); | |
5127 | break; | |
5128 | case broadcast_needed: | |
5129 | err_msg = _("broadcast is needed for operand of such type"); | |
5130 | break; | |
5131 | case unsupported_masking: | |
5132 | err_msg = _("unsupported masking"); | |
5133 | break; | |
5134 | case mask_not_on_destination: | |
5135 | err_msg = _("mask not on destination operand"); | |
5136 | break; | |
5137 | case no_default_mask: | |
5138 | err_msg = _("default mask isn't allowed"); | |
5139 | break; | |
5140 | case unsupported_rc_sae: | |
5141 | err_msg = _("unsupported static rounding/sae"); | |
5142 | break; | |
5143 | case invalid_register_operand: | |
5144 | err_msg = _("invalid register operand"); | |
5145 | break; | |
5146 | } | |
5147 | as_bad (_("%s for `%s'"), err_msg, | |
76d3f746 | 5148 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
04784e33 JB |
5149 | return; |
5150 | } | |
5151 | ||
5152 | free (copy); | |
252b5132 | 5153 | |
7bab8ab5 | 5154 | if (sse_check != check_none |
ffb86450 JB |
5155 | /* The opcode space check isn't strictly needed; it's there only to |
5156 | bypass the logic below when easily possible. */ | |
ddb62495 JB |
5157 | && t->opcode_space >= SPACE_0F |
5158 | && t->opcode_space <= SPACE_0F3A | |
ffb86450 JB |
5159 | && !i.tm.cpu_flags.bitfield.cpusse4a |
5160 | && !is_any_vex_encoding (t)) | |
daf50ae7 | 5161 | { |
ffb86450 JB |
5162 | bool simd = false; |
5163 | ||
5164 | for (j = 0; j < t->operands; ++j) | |
5165 | { | |
5166 | if (t->operand_types[j].bitfield.class == RegMMX) | |
5167 | break; | |
5168 | if (t->operand_types[j].bitfield.class == RegSIMD) | |
5169 | simd = true; | |
5170 | } | |
5171 | ||
5172 | if (j >= t->operands && simd) | |
5173 | (sse_check == check_warning | |
5174 | ? as_warn | |
76d3f746 | 5175 | : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm)); |
daf50ae7 L |
5176 | } |
5177 | ||
40fb9820 | 5178 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
5179 | if (!add_prefix (FWAIT_OPCODE)) |
5180 | return; | |
252b5132 | 5181 | |
d5de92cf | 5182 | /* Check if REP prefix is OK. */ |
742732c7 | 5183 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
5184 | { |
5185 | as_bad (_("invalid instruction `%s' after `%s'"), | |
76d3f746 | 5186 | insn_name (&i.tm), i.rep_prefix); |
d5de92cf L |
5187 | return; |
5188 | } | |
5189 | ||
c1ba0266 L |
5190 | /* Check for lock without a lockable instruction. Destination operand |
5191 | must be memory unless it is xchg (0x86). */ | |
9a4a4499 JB |
5192 | if (i.prefix[LOCK_PREFIX]) |
5193 | { | |
5194 | if (i.tm.opcode_modifier.prefixok < PrefixLock | |
c1ba0266 L |
5195 | || i.mem_operands == 0 |
5196 | || (i.tm.base_opcode != 0x86 | |
9a4a4499 JB |
5197 | && !(i.flags[i.operands - 1] & Operand_Mem))) |
5198 | { | |
5199 | as_bad (_("expecting lockable instruction after `lock'")); | |
5200 | return; | |
5201 | } | |
5202 | ||
5203 | /* Zap the redundant prefix from XCHG when optimizing. */ | |
5204 | if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize) | |
5205 | i.prefix[LOCK_PREFIX] = 0; | |
c32fa91d L |
5206 | } |
5207 | ||
e3669c7f JB |
5208 | if (is_any_vex_encoding (&i.tm) |
5209 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
5210 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX) | |
7a8655d2 | 5211 | { |
e3669c7f JB |
5212 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
5213 | if (i.prefix[DATA_PREFIX]) | |
5214 | { | |
76d3f746 | 5215 | as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
5216 | return; |
5217 | } | |
5218 | ||
5219 | /* Don't allow e.g. KMOV in TLS code sequences. */ | |
5220 | for (j = i.imm_operands; j < i.operands; ++j) | |
5221 | switch (i.reloc[j]) | |
5222 | { | |
5223 | case BFD_RELOC_386_TLS_GOTIE: | |
5224 | case BFD_RELOC_386_TLS_LE_32: | |
5225 | case BFD_RELOC_X86_64_GOTTPOFF: | |
5226 | case BFD_RELOC_X86_64_TLSLD: | |
76d3f746 | 5227 | as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
5228 | return; |
5229 | default: | |
5230 | break; | |
5231 | } | |
7a8655d2 JB |
5232 | } |
5233 | ||
42164a71 | 5234 | /* Check if HLE prefix is OK. */ |
165de32a | 5235 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
5236 | return; |
5237 | ||
7e8b059b L |
5238 | /* Check BND prefix. */ |
5239 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
5240 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
5241 | ||
04ef582a | 5242 | /* Check NOTRACK prefix. */ |
742732c7 | 5243 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 5244 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 5245 | |
327e8c42 JB |
5246 | if (i.tm.cpu_flags.bitfield.cpumpx) |
5247 | { | |
5248 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
5249 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
5250 | else if (flag_code != CODE_16BIT | |
5251 | ? i.prefix[ADDR_PREFIX] | |
5252 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
5253 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
5254 | } | |
7e8b059b L |
5255 | |
5256 | /* Insert BND prefix. */ | |
76d3a78a JB |
5257 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
5258 | { | |
5259 | if (!i.prefix[BND_PREFIX]) | |
5260 | add_prefix (BND_PREFIX_OPCODE); | |
5261 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
5262 | { | |
5263 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
5264 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
5265 | } | |
5266 | } | |
7e8b059b | 5267 | |
29b0f896 | 5268 | /* Check string instruction segment overrides. */ |
51c8edf6 | 5269 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 5270 | { |
51c8edf6 | 5271 | gas_assert (i.mem_operands); |
29b0f896 | 5272 | if (!check_string ()) |
5dd0794d | 5273 | return; |
fc0763e6 | 5274 | i.disp_operands = 0; |
29b0f896 | 5275 | } |
5dd0794d | 5276 | |
9373f275 L |
5277 | /* The memory operand of (%dx) should be only used with input/output |
5278 | instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */ | |
5279 | if (i.input_output_operand | |
5280 | && ((i.tm.base_opcode | 0x82) != 0xee | |
ddb62495 | 5281 | || i.tm.opcode_space != SPACE_BASE)) |
9373f275 L |
5282 | { |
5283 | as_bad (_("input/output port address isn't allowed with `%s'"), | |
76d3f746 | 5284 | insn_name (&i.tm)); |
9373f275 L |
5285 | return; |
5286 | } | |
5287 | ||
b6f8c7c4 L |
5288 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
5289 | optimize_encoding (); | |
5290 | ||
c8480b58 L |
5291 | if (use_unaligned_vector_move) |
5292 | encode_with_unaligned_vector_move (); | |
5293 | ||
29b0f896 AM |
5294 | if (!process_suffix ()) |
5295 | return; | |
e413e4e9 | 5296 | |
ef07be45 CL |
5297 | /* Check if IP-relative addressing requirements can be satisfied. */ |
5298 | if (i.tm.cpu_flags.bitfield.cpuprefetchi | |
5299 | && !(i.base_reg && i.base_reg->reg_num == RegIP)) | |
76d3f746 | 5300 | as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm)); |
ef07be45 | 5301 | |
921eafea | 5302 | /* Update operand types and check extended states. */ |
bc0844ae | 5303 | for (j = 0; j < i.operands; j++) |
921eafea L |
5304 | { |
5305 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 5306 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
5307 | { |
5308 | default: | |
5309 | break; | |
5310 | case RegMMX: | |
5311 | i.xstate |= xstate_mmx; | |
5312 | break; | |
5313 | case RegMask: | |
32930e4e | 5314 | i.xstate |= xstate_mask; |
921eafea L |
5315 | break; |
5316 | case RegSIMD: | |
3d70986f | 5317 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 5318 | i.xstate |= xstate_tmm; |
3d70986f | 5319 | else if (i.tm.operand_types[j].bitfield.zmmword) |
921eafea | 5320 | i.xstate |= xstate_zmm; |
3d70986f | 5321 | else if (i.tm.operand_types[j].bitfield.ymmword) |
921eafea | 5322 | i.xstate |= xstate_ymm; |
3d70986f | 5323 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
5324 | i.xstate |= xstate_xmm; |
5325 | break; | |
5326 | } | |
5327 | } | |
bc0844ae | 5328 | |
29b0f896 AM |
5329 | /* Make still unresolved immediate matches conform to size of immediate |
5330 | given in i.suffix. */ | |
5331 | if (!finalize_imm ()) | |
5332 | return; | |
252b5132 | 5333 | |
40fb9820 | 5334 | if (i.types[0].bitfield.imm1) |
29b0f896 | 5335 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 5336 | |
29b0f896 AM |
5337 | /* For insns with operands there are more diddles to do to the opcode. */ |
5338 | if (i.operands) | |
5339 | { | |
5340 | if (!process_operands ()) | |
5341 | return; | |
5342 | } | |
255571cd | 5343 | else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) |
29b0f896 AM |
5344 | { |
5345 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
76d3f746 | 5346 | as_warn (_("translating to `%sp'"), insn_name (&i.tm)); |
29b0f896 | 5347 | } |
252b5132 | 5348 | |
7a8655d2 | 5349 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 5350 | { |
c1dc7af5 | 5351 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 5352 | { |
c1dc7af5 | 5353 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
76d3f746 | 5354 | insn_name (&i.tm)); |
9e5e5283 L |
5355 | return; |
5356 | } | |
c0f3af97 | 5357 | |
0b9404fd JB |
5358 | /* Check for explicit REX prefix. */ |
5359 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
5360 | { | |
76d3f746 | 5361 | as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm)); |
0b9404fd JB |
5362 | return; |
5363 | } | |
5364 | ||
9e5e5283 L |
5365 | if (i.tm.opcode_modifier.vex) |
5366 | build_vex_prefix (t); | |
5367 | else | |
5368 | build_evex_prefix (); | |
0b9404fd JB |
5369 | |
5370 | /* The individual REX.RXBW bits got consumed. */ | |
5371 | i.rex &= REX_OPCODE; | |
9e5e5283 | 5372 | } |
43234a1e | 5373 | |
7fc69528 JB |
5374 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
5375 | if (i.tm.mnem_off == MN_int | |
a6461c02 | 5376 | && i.op[0].imms->X_add_number == 3) |
29b0f896 AM |
5377 | { |
5378 | i.tm.base_opcode = INT3_OPCODE; | |
5379 | i.imm_operands = 0; | |
5380 | } | |
252b5132 | 5381 | |
0cfa3eb3 JB |
5382 | if ((i.tm.opcode_modifier.jump == JUMP |
5383 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
5384 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
5385 | && i.op[0].disps->X_op == O_constant) |
5386 | { | |
5387 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
5388 | the absolute address given by the constant. Since ix86 jumps and | |
5389 | calls are pc relative, we need to generate a reloc. */ | |
5390 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
5391 | i.op[0].disps->X_op = O_symbol; | |
5392 | } | |
252b5132 | 5393 | |
29b0f896 AM |
5394 | /* For 8 bit registers we need an empty rex prefix. Also if the |
5395 | instruction already has a prefix, we need to convert old | |
5396 | registers to new ones. */ | |
773f551c | 5397 | |
bab6aec1 | 5398 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 5399 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 5400 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 5401 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
5402 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
5403 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
5404 | && i.rex != 0)) |
5405 | { | |
5406 | int x; | |
726c5dcd | 5407 | |
29b0f896 AM |
5408 | i.rex |= REX_OPCODE; |
5409 | for (x = 0; x < 2; x++) | |
5410 | { | |
5411 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 5412 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 5413 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 5414 | { |
3f93af61 | 5415 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
5416 | /* In case it is "hi" register, give up. */ |
5417 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 5418 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 5419 | "instruction requiring REX prefix."), |
a540244d | 5420 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 5421 | |
29b0f896 AM |
5422 | /* Otherwise it is equivalent to the extended register. |
5423 | Since the encoding doesn't change this is merely | |
5424 | cosmetic cleanup for debug output. */ | |
5425 | ||
5426 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 5427 | } |
29b0f896 AM |
5428 | } |
5429 | } | |
773f551c | 5430 | |
6b6b6807 L |
5431 | if (i.rex == 0 && i.rex_encoding) |
5432 | { | |
5433 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 5434 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
5435 | the REX_OPCODE byte. */ |
5436 | int x; | |
5437 | for (x = 0; x < 2; x++) | |
bab6aec1 | 5438 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
5439 | && i.types[x].bitfield.byte |
5440 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
5441 | && i.op[x].regs->reg_num > 3) | |
5442 | { | |
3f93af61 | 5443 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
5b7c81bd | 5444 | i.rex_encoding = false; |
6b6b6807 L |
5445 | break; |
5446 | } | |
5447 | ||
5448 | if (i.rex_encoding) | |
5449 | i.rex = REX_OPCODE; | |
5450 | } | |
5451 | ||
7ab9ffdd | 5452 | if (i.rex != 0) |
29b0f896 AM |
5453 | add_prefix (REX_OPCODE | i.rex); |
5454 | ||
ae531041 L |
5455 | insert_lfence_before (); |
5456 | ||
29b0f896 AM |
5457 | /* We are ready to output the insn. */ |
5458 | output_insn (); | |
e379e5f3 | 5459 | |
ae531041 L |
5460 | insert_lfence_after (); |
5461 | ||
e379e5f3 L |
5462 | last_insn.seg = now_seg; |
5463 | ||
5464 | if (i.tm.opcode_modifier.isprefix) | |
5465 | { | |
5466 | last_insn.kind = last_insn_prefix; | |
76d3f746 | 5467 | last_insn.name = insn_name (&i.tm); |
e379e5f3 L |
5468 | last_insn.file = as_where (&last_insn.line); |
5469 | } | |
5470 | else | |
5471 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
5472 | } |
5473 | ||
9db83a32 JB |
5474 | /* The Q suffix is generally valid only in 64-bit mode, with very few |
5475 | exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild | |
5476 | and fisttp only one of their two templates is matched below: That's | |
5477 | sufficient since other relevant attributes are the same between both | |
5478 | respective templates. */ | |
5479 | static INLINE bool q_suffix_allowed(const insn_template *t) | |
5480 | { | |
5481 | return flag_code == CODE_64BIT | |
ddb62495 | 5482 | || (t->opcode_space == SPACE_BASE |
9db83a32 JB |
5483 | && t->base_opcode == 0xdf |
5484 | && (t->extension_opcode & 1)) /* fild / fistp / fisttp */ | |
7fc69528 | 5485 | || t->mnem_off == MN_cmpxchg8b; |
9db83a32 JB |
5486 | } |
5487 | ||
5317ad2c JB |
5488 | static const char * |
5489 | parse_insn (const char *line, char *mnemonic) | |
29b0f896 | 5490 | { |
5317ad2c | 5491 | const char *l = line, *token_start = l; |
29b0f896 | 5492 | char *mnem_p; |
04784e33 | 5493 | bool pass1 = !current_templates; |
5c6af06e | 5494 | int supported; |
d3ce72d0 | 5495 | const insn_template *t; |
b6169b20 | 5496 | char *dot_p = NULL; |
29b0f896 | 5497 | |
29b0f896 AM |
5498 | while (1) |
5499 | { | |
5500 | mnem_p = mnemonic; | |
5501 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
5502 | { | |
b6169b20 L |
5503 | if (*mnem_p == '.') |
5504 | dot_p = mnem_p; | |
29b0f896 AM |
5505 | mnem_p++; |
5506 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5507 | { |
29b0f896 AM |
5508 | as_bad (_("no such instruction: `%s'"), token_start); |
5509 | return NULL; | |
5510 | } | |
5511 | l++; | |
5512 | } | |
5513 | if (!is_space_char (*l) | |
5514 | && *l != END_OF_INSN | |
e44823cf JB |
5515 | && (intel_syntax |
5516 | || (*l != PREFIX_SEPARATOR | |
5517 | && *l != ','))) | |
29b0f896 AM |
5518 | { |
5519 | as_bad (_("invalid character %s in mnemonic"), | |
5520 | output_invalid (*l)); | |
5521 | return NULL; | |
5522 | } | |
5523 | if (token_start == l) | |
5524 | { | |
e44823cf | 5525 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5526 | as_bad (_("expecting prefix; got nothing")); |
5527 | else | |
5528 | as_bad (_("expecting mnemonic; got nothing")); | |
5529 | return NULL; | |
5530 | } | |
45288df1 | 5531 | |
29b0f896 | 5532 | /* Look up instruction (or prefix) via hash table. */ |
629310ab | 5533 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
47926f60 | 5534 | |
29b0f896 AM |
5535 | if (*l != END_OF_INSN |
5536 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
5537 | && current_templates | |
40fb9820 | 5538 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 5539 | { |
c6fb90c8 | 5540 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
5541 | { |
5542 | as_bad ((flag_code != CODE_64BIT | |
5543 | ? _("`%s' is only supported in 64-bit mode") | |
5544 | : _("`%s' is not supported in 64-bit mode")), | |
76d3f746 | 5545 | insn_name (current_templates->start)); |
2dd88dca JB |
5546 | return NULL; |
5547 | } | |
29b0f896 AM |
5548 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5549 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
5550 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
5551 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5552 | && flag_code != CODE_64BIT |
673fe0f0 | 5553 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5554 | ^ (flag_code == CODE_16BIT))) |
5555 | { | |
5556 | as_bad (_("redundant %s prefix"), | |
76d3f746 | 5557 | insn_name (current_templates->start)); |
29b0f896 | 5558 | return NULL; |
45288df1 | 5559 | } |
31184569 JB |
5560 | |
5561 | if (current_templates->start->base_opcode == PSEUDO_PREFIX) | |
29b0f896 | 5562 | { |
86fa6981 | 5563 | /* Handle pseudo prefixes. */ |
31184569 | 5564 | switch (current_templates->start->extension_opcode) |
86fa6981 | 5565 | { |
41eb8e88 | 5566 | case Prefix_Disp8: |
86fa6981 L |
5567 | /* {disp8} */ |
5568 | i.disp_encoding = disp_encoding_8bit; | |
5569 | break; | |
41eb8e88 L |
5570 | case Prefix_Disp16: |
5571 | /* {disp16} */ | |
5572 | i.disp_encoding = disp_encoding_16bit; | |
5573 | break; | |
5574 | case Prefix_Disp32: | |
86fa6981 L |
5575 | /* {disp32} */ |
5576 | i.disp_encoding = disp_encoding_32bit; | |
5577 | break; | |
41eb8e88 | 5578 | case Prefix_Load: |
86fa6981 L |
5579 | /* {load} */ |
5580 | i.dir_encoding = dir_encoding_load; | |
5581 | break; | |
41eb8e88 | 5582 | case Prefix_Store: |
86fa6981 L |
5583 | /* {store} */ |
5584 | i.dir_encoding = dir_encoding_store; | |
5585 | break; | |
41eb8e88 | 5586 | case Prefix_VEX: |
42e04b36 L |
5587 | /* {vex} */ |
5588 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 | 5589 | break; |
41eb8e88 | 5590 | case Prefix_VEX3: |
86fa6981 L |
5591 | /* {vex3} */ |
5592 | i.vec_encoding = vex_encoding_vex3; | |
5593 | break; | |
41eb8e88 | 5594 | case Prefix_EVEX: |
86fa6981 L |
5595 | /* {evex} */ |
5596 | i.vec_encoding = vex_encoding_evex; | |
5597 | break; | |
41eb8e88 | 5598 | case Prefix_REX: |
6b6b6807 | 5599 | /* {rex} */ |
5b7c81bd | 5600 | i.rex_encoding = true; |
6b6b6807 | 5601 | break; |
41eb8e88 | 5602 | case Prefix_NoOptimize: |
b6f8c7c4 | 5603 | /* {nooptimize} */ |
5b7c81bd | 5604 | i.no_optimize = true; |
b6f8c7c4 | 5605 | break; |
86fa6981 L |
5606 | default: |
5607 | abort (); | |
5608 | } | |
5609 | } | |
5610 | else | |
5611 | { | |
5612 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 5613 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 5614 | { |
4e9ac44a L |
5615 | case PREFIX_EXIST: |
5616 | return NULL; | |
5617 | case PREFIX_DS: | |
d777820b | 5618 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
76d3f746 | 5619 | i.notrack_prefix = insn_name (current_templates->start); |
4e9ac44a L |
5620 | break; |
5621 | case PREFIX_REP: | |
5622 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
76d3f746 | 5623 | i.hle_prefix = insn_name (current_templates->start); |
4e9ac44a | 5624 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) |
76d3f746 | 5625 | i.bnd_prefix = insn_name (current_templates->start); |
4e9ac44a | 5626 | else |
76d3f746 | 5627 | i.rep_prefix = insn_name (current_templates->start); |
4e9ac44a L |
5628 | break; |
5629 | default: | |
5630 | break; | |
86fa6981 | 5631 | } |
29b0f896 AM |
5632 | } |
5633 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
5634 | token_start = ++l; | |
5635 | } | |
5636 | else | |
5637 | break; | |
5638 | } | |
45288df1 | 5639 | |
30a55f88 | 5640 | if (!current_templates) |
b6169b20 | 5641 | { |
07d5e953 JB |
5642 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
5643 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 5644 | encoding. */ |
30a55f88 | 5645 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 5646 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 5647 | else if (mnem_p - 3 == dot_p |
a501d77e L |
5648 | && dot_p[1] == 'd' |
5649 | && dot_p[2] == '8') | |
5650 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 5651 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
5652 | && dot_p[1] == 'd' |
5653 | && dot_p[2] == '3' | |
5654 | && dot_p[3] == '2') | |
a501d77e | 5655 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
5656 | else |
5657 | goto check_suffix; | |
5658 | mnem_p = dot_p; | |
5659 | *dot_p = '\0'; | |
629310ab | 5660 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
b6169b20 L |
5661 | } |
5662 | ||
04784e33 | 5663 | if (!current_templates || !pass1) |
29b0f896 | 5664 | { |
04784e33 JB |
5665 | current_templates = NULL; |
5666 | ||
dc1e8a47 | 5667 | check_suffix: |
1c529385 | 5668 | if (mnem_p > mnemonic) |
29b0f896 | 5669 | { |
1c529385 LH |
5670 | /* See if we can get a match by trimming off a suffix. */ |
5671 | switch (mnem_p[-1]) | |
29b0f896 | 5672 | { |
1c529385 LH |
5673 | case WORD_MNEM_SUFFIX: |
5674 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
5675 | i.suffix = SHORT_MNEM_SUFFIX; |
5676 | else | |
1c529385 LH |
5677 | /* Fall through. */ |
5678 | case BYTE_MNEM_SUFFIX: | |
5679 | case QWORD_MNEM_SUFFIX: | |
5680 | i.suffix = mnem_p[-1]; | |
29b0f896 | 5681 | mnem_p[-1] = '\0'; |
fe0e921f AM |
5682 | current_templates |
5683 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5684 | break; |
5685 | case SHORT_MNEM_SUFFIX: | |
5686 | case LONG_MNEM_SUFFIX: | |
5687 | if (!intel_syntax) | |
5688 | { | |
5689 | i.suffix = mnem_p[-1]; | |
5690 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5691 | current_templates |
5692 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5693 | } |
5694 | break; | |
5695 | ||
5696 | /* Intel Syntax. */ | |
5697 | case 'd': | |
5698 | if (intel_syntax) | |
5699 | { | |
5700 | if (intel_float_operand (mnemonic) == 1) | |
5701 | i.suffix = SHORT_MNEM_SUFFIX; | |
5702 | else | |
5703 | i.suffix = LONG_MNEM_SUFFIX; | |
5704 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5705 | current_templates |
5706 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 | 5707 | } |
04784e33 JB |
5708 | /* For compatibility reasons accept MOVSD and CMPSD without |
5709 | operands even in AT&T mode. */ | |
5710 | else if (*l == END_OF_INSN | |
5711 | || (is_space_char (*l) && l[1] == END_OF_INSN)) | |
5712 | { | |
5713 | mnem_p[-1] = '\0'; | |
5714 | current_templates | |
5715 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
5716 | if (current_templates != NULL | |
5717 | /* MOVS or CMPS */ | |
5718 | && (current_templates->start->base_opcode | 2) == 0xa6 | |
ddb62495 | 5719 | && current_templates->start->opcode_space |
04784e33 JB |
5720 | == SPACE_BASE |
5721 | && mnem_p[-2] == 's') | |
5722 | { | |
5723 | as_warn (_("found `%sd'; assuming `%sl' was meant"), | |
5724 | mnemonic, mnemonic); | |
5725 | i.suffix = LONG_MNEM_SUFFIX; | |
5726 | } | |
5727 | else | |
5728 | { | |
5729 | current_templates = NULL; | |
5730 | mnem_p[-1] = 'd'; | |
5731 | } | |
5732 | } | |
1c529385 | 5733 | break; |
29b0f896 | 5734 | } |
29b0f896 | 5735 | } |
1c529385 | 5736 | |
29b0f896 AM |
5737 | if (!current_templates) |
5738 | { | |
04784e33 JB |
5739 | if (pass1) |
5740 | as_bad (_("no such instruction: `%s'"), token_start); | |
29b0f896 AM |
5741 | return NULL; |
5742 | } | |
5743 | } | |
252b5132 | 5744 | |
0cfa3eb3 JB |
5745 | if (current_templates->start->opcode_modifier.jump == JUMP |
5746 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
5747 | { |
5748 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
5749 | predict taken and predict not taken respectively. | |
5750 | I'm not sure that branch hints actually do anything on loop | |
5751 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
5752 | may work in the future and it doesn't hurt to accept them | |
5753 | now. */ | |
5754 | if (l[0] == ',' && l[1] == 'p') | |
5755 | { | |
5756 | if (l[2] == 't') | |
5757 | { | |
5758 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
5759 | return NULL; | |
5760 | l += 3; | |
5761 | } | |
5762 | else if (l[2] == 'n') | |
5763 | { | |
5764 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
5765 | return NULL; | |
5766 | l += 3; | |
5767 | } | |
5768 | } | |
5769 | } | |
5770 | /* Any other comma loses. */ | |
5771 | if (*l == ',') | |
5772 | { | |
5773 | as_bad (_("invalid character %s in mnemonic"), | |
5774 | output_invalid (*l)); | |
5775 | return NULL; | |
5776 | } | |
252b5132 | 5777 | |
29b0f896 | 5778 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
5779 | supported = 0; |
5780 | for (t = current_templates->start; t < current_templates->end; ++t) | |
5781 | { | |
c0f3af97 | 5782 | supported |= cpu_flags_match (t); |
9db83a32 JB |
5783 | |
5784 | if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t)) | |
5785 | supported &= ~CPU_FLAGS_64BIT_MATCH; | |
5786 | ||
c0f3af97 | 5787 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
d59a54c2 | 5788 | return l; |
29b0f896 | 5789 | } |
3629bb00 | 5790 | |
9db83a32 JB |
5791 | if (pass1) |
5792 | { | |
5793 | if (supported & CPU_FLAGS_64BIT_MATCH) | |
5794 | i.error = unsupported_on_arch; | |
5795 | else | |
5796 | i.error = unsupported_64bit; | |
5797 | } | |
252b5132 | 5798 | |
548d0ee6 | 5799 | return NULL; |
29b0f896 | 5800 | } |
252b5132 | 5801 | |
29b0f896 | 5802 | static char * |
e3bb37b5 | 5803 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
5804 | { |
5805 | char *token_start; | |
3138f287 | 5806 | |
29b0f896 AM |
5807 | /* 1 if operand is pending after ','. */ |
5808 | unsigned int expecting_operand = 0; | |
252b5132 | 5809 | |
29b0f896 AM |
5810 | while (*l != END_OF_INSN) |
5811 | { | |
e68c3d59 JB |
5812 | /* Non-zero if operand parens not balanced. */ |
5813 | unsigned int paren_not_balanced = 0; | |
5814 | /* True if inside double quotes. */ | |
5815 | bool in_quotes = false; | |
5816 | ||
29b0f896 AM |
5817 | /* Skip optional white space before operand. */ |
5818 | if (is_space_char (*l)) | |
5819 | ++l; | |
d02603dc | 5820 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
5821 | { |
5822 | as_bad (_("invalid character %s before operand %d"), | |
5823 | output_invalid (*l), | |
5824 | i.operands + 1); | |
5825 | return NULL; | |
5826 | } | |
d02603dc | 5827 | token_start = l; /* After white space. */ |
e68c3d59 | 5828 | while (in_quotes || paren_not_balanced || *l != ',') |
29b0f896 AM |
5829 | { |
5830 | if (*l == END_OF_INSN) | |
5831 | { | |
e68c3d59 JB |
5832 | if (in_quotes) |
5833 | { | |
5834 | as_bad (_("unbalanced double quotes in operand %d."), | |
5835 | i.operands + 1); | |
5836 | return NULL; | |
5837 | } | |
29b0f896 AM |
5838 | if (paren_not_balanced) |
5839 | { | |
98ff9f1c JB |
5840 | know (!intel_syntax); |
5841 | as_bad (_("unbalanced parenthesis in operand %d."), | |
5842 | i.operands + 1); | |
29b0f896 AM |
5843 | return NULL; |
5844 | } | |
5845 | else | |
5846 | break; /* we are done */ | |
5847 | } | |
e68c3d59 JB |
5848 | else if (*l == '\\' && l[1] == '"') |
5849 | ++l; | |
5850 | else if (*l == '"') | |
5851 | in_quotes = !in_quotes; | |
5852 | else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l)) | |
29b0f896 AM |
5853 | { |
5854 | as_bad (_("invalid character %s in operand %d"), | |
5855 | output_invalid (*l), | |
5856 | i.operands + 1); | |
5857 | return NULL; | |
5858 | } | |
e68c3d59 | 5859 | if (!intel_syntax && !in_quotes) |
29b0f896 AM |
5860 | { |
5861 | if (*l == '(') | |
5862 | ++paren_not_balanced; | |
5863 | if (*l == ')') | |
5864 | --paren_not_balanced; | |
5865 | } | |
29b0f896 AM |
5866 | l++; |
5867 | } | |
5868 | if (l != token_start) | |
5869 | { /* Yes, we've read in another operand. */ | |
5870 | unsigned int operand_ok; | |
5871 | this_operand = i.operands++; | |
5872 | if (i.operands > MAX_OPERANDS) | |
5873 | { | |
5874 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5875 | MAX_OPERANDS); | |
5876 | return NULL; | |
5877 | } | |
9d46ce34 | 5878 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5879 | /* Now parse operand adding info to 'i' as we go along. */ |
5880 | END_STRING_AND_SAVE (l); | |
5881 | ||
1286ab78 L |
5882 | if (i.mem_operands > 1) |
5883 | { | |
5884 | as_bad (_("too many memory references for `%s'"), | |
5885 | mnemonic); | |
5886 | return 0; | |
5887 | } | |
5888 | ||
29b0f896 AM |
5889 | if (intel_syntax) |
5890 | operand_ok = | |
5891 | i386_intel_operand (token_start, | |
5892 | intel_float_operand (mnemonic)); | |
5893 | else | |
a7619375 | 5894 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5895 | |
5896 | RESTORE_END_STRING (l); | |
5897 | if (!operand_ok) | |
5898 | return NULL; | |
5899 | } | |
5900 | else | |
5901 | { | |
5902 | if (expecting_operand) | |
5903 | { | |
5904 | expecting_operand_after_comma: | |
5905 | as_bad (_("expecting operand after ','; got nothing")); | |
5906 | return NULL; | |
5907 | } | |
5908 | if (*l == ',') | |
5909 | { | |
5910 | as_bad (_("expecting operand before ','; got nothing")); | |
5911 | return NULL; | |
5912 | } | |
5913 | } | |
7f3f1ea2 | 5914 | |
29b0f896 AM |
5915 | /* Now *l must be either ',' or END_OF_INSN. */ |
5916 | if (*l == ',') | |
5917 | { | |
5918 | if (*++l == END_OF_INSN) | |
5919 | { | |
5920 | /* Just skip it, if it's \n complain. */ | |
5921 | goto expecting_operand_after_comma; | |
5922 | } | |
5923 | expecting_operand = 1; | |
5924 | } | |
5925 | } | |
5926 | return l; | |
5927 | } | |
7f3f1ea2 | 5928 | |
050dfa73 | 5929 | static void |
783c187b | 5930 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
5931 | { |
5932 | union i386_op temp_op; | |
40fb9820 | 5933 | i386_operand_type temp_type; |
c48dadc9 | 5934 | unsigned int temp_flags; |
050dfa73 | 5935 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5936 | |
050dfa73 MM |
5937 | temp_type = i.types[xchg2]; |
5938 | i.types[xchg2] = i.types[xchg1]; | |
5939 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5940 | |
5941 | temp_flags = i.flags[xchg2]; | |
5942 | i.flags[xchg2] = i.flags[xchg1]; | |
5943 | i.flags[xchg1] = temp_flags; | |
5944 | ||
050dfa73 MM |
5945 | temp_op = i.op[xchg2]; |
5946 | i.op[xchg2] = i.op[xchg1]; | |
5947 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5948 | |
050dfa73 MM |
5949 | temp_reloc = i.reloc[xchg2]; |
5950 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5951 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 5952 | |
6225c532 | 5953 | if (i.mask.reg) |
43234a1e | 5954 | { |
6225c532 JB |
5955 | if (i.mask.operand == xchg1) |
5956 | i.mask.operand = xchg2; | |
5957 | else if (i.mask.operand == xchg2) | |
5958 | i.mask.operand = xchg1; | |
43234a1e | 5959 | } |
a5748e0d | 5960 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 5961 | { |
5273a3cd JB |
5962 | if (i.broadcast.operand == xchg1) |
5963 | i.broadcast.operand = xchg2; | |
5964 | else if (i.broadcast.operand == xchg2) | |
5965 | i.broadcast.operand = xchg1; | |
43234a1e | 5966 | } |
050dfa73 MM |
5967 | } |
5968 | ||
29b0f896 | 5969 | static void |
e3bb37b5 | 5970 | swap_operands (void) |
29b0f896 | 5971 | { |
b7c61d9a | 5972 | switch (i.operands) |
050dfa73 | 5973 | { |
c0f3af97 | 5974 | case 5: |
b7c61d9a | 5975 | case 4: |
4d456e3d | 5976 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5977 | /* Fall through. */ |
b7c61d9a L |
5978 | case 3: |
5979 | case 2: | |
4d456e3d | 5980 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5981 | break; |
5982 | default: | |
5983 | abort (); | |
29b0f896 | 5984 | } |
29b0f896 AM |
5985 | |
5986 | if (i.mem_operands == 2) | |
5987 | { | |
5e042380 | 5988 | const reg_entry *temp_seg; |
29b0f896 AM |
5989 | temp_seg = i.seg[0]; |
5990 | i.seg[0] = i.seg[1]; | |
5991 | i.seg[1] = temp_seg; | |
5992 | } | |
5993 | } | |
252b5132 | 5994 | |
29b0f896 AM |
5995 | /* Try to ensure constant immediates are represented in the smallest |
5996 | opcode possible. */ | |
5997 | static void | |
e3bb37b5 | 5998 | optimize_imm (void) |
29b0f896 AM |
5999 | { |
6000 | char guess_suffix = 0; | |
6001 | int op; | |
252b5132 | 6002 | |
29b0f896 AM |
6003 | if (i.suffix) |
6004 | guess_suffix = i.suffix; | |
6005 | else if (i.reg_operands) | |
6006 | { | |
6007 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
6008 | We can't do this properly yet, i.e. excluding special register |
6009 | instances, but the following works for instructions with | |
6010 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 6011 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
6012 | if (i.types[op].bitfield.class != Reg) |
6013 | continue; | |
6014 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 6015 | { |
40fb9820 L |
6016 | guess_suffix = BYTE_MNEM_SUFFIX; |
6017 | break; | |
6018 | } | |
bab6aec1 | 6019 | else if (i.types[op].bitfield.word) |
252b5132 | 6020 | { |
40fb9820 L |
6021 | guess_suffix = WORD_MNEM_SUFFIX; |
6022 | break; | |
6023 | } | |
bab6aec1 | 6024 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
6025 | { |
6026 | guess_suffix = LONG_MNEM_SUFFIX; | |
6027 | break; | |
6028 | } | |
bab6aec1 | 6029 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
6030 | { |
6031 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 6032 | break; |
252b5132 | 6033 | } |
29b0f896 AM |
6034 | } |
6035 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
6036 | guess_suffix = WORD_MNEM_SUFFIX; | |
6037 | ||
6038 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 6039 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
6040 | { |
6041 | switch (i.op[op].imms->X_op) | |
252b5132 | 6042 | { |
29b0f896 AM |
6043 | case O_constant: |
6044 | /* If a suffix is given, this operand may be shortened. */ | |
6045 | switch (guess_suffix) | |
252b5132 | 6046 | { |
29b0f896 | 6047 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
6048 | i.types[op].bitfield.imm32 = 1; |
6049 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
6050 | break; |
6051 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
6052 | i.types[op].bitfield.imm16 = 1; |
6053 | i.types[op].bitfield.imm32 = 1; | |
6054 | i.types[op].bitfield.imm32s = 1; | |
6055 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
6056 | break; |
6057 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
6058 | i.types[op].bitfield.imm8 = 1; |
6059 | i.types[op].bitfield.imm8s = 1; | |
6060 | i.types[op].bitfield.imm16 = 1; | |
6061 | i.types[op].bitfield.imm32 = 1; | |
6062 | i.types[op].bitfield.imm32s = 1; | |
6063 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 6064 | break; |
252b5132 | 6065 | } |
252b5132 | 6066 | |
29b0f896 AM |
6067 | /* If this operand is at most 16 bits, convert it |
6068 | to a signed 16 bit number before trying to see | |
6069 | whether it will fit in an even smaller size. | |
6070 | This allows a 16-bit operand such as $0xffe0 to | |
6071 | be recognised as within Imm8S range. */ | |
40fb9820 | 6072 | if ((i.types[op].bitfield.imm16) |
7e96fb68 | 6073 | && fits_in_unsigned_word (i.op[op].imms->X_add_number)) |
252b5132 | 6074 | { |
87ed972d JB |
6075 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
6076 | ^ 0x8000) - 0x8000); | |
29b0f896 | 6077 | } |
a28def75 L |
6078 | #ifdef BFD64 |
6079 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 6080 | if ((i.types[op].bitfield.imm32) |
7e96fb68 | 6081 | && fits_in_unsigned_long (i.op[op].imms->X_add_number)) |
29b0f896 AM |
6082 | { |
6083 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
6084 | ^ ((offsetT) 1 << 31)) | |
6085 | - ((offsetT) 1 << 31)); | |
6086 | } | |
a28def75 | 6087 | #endif |
40fb9820 | 6088 | i.types[op] |
c6fb90c8 L |
6089 | = operand_type_or (i.types[op], |
6090 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 6091 | |
29b0f896 AM |
6092 | /* We must avoid matching of Imm32 templates when 64bit |
6093 | only immediate is available. */ | |
6094 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 6095 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 6096 | break; |
252b5132 | 6097 | |
29b0f896 AM |
6098 | case O_absent: |
6099 | case O_register: | |
6100 | abort (); | |
6101 | ||
6102 | /* Symbols and expressions. */ | |
6103 | default: | |
9cd96992 JB |
6104 | /* Convert symbolic operand to proper sizes for matching, but don't |
6105 | prevent matching a set of insns that only supports sizes other | |
6106 | than those matching the insn suffix. */ | |
6107 | { | |
40fb9820 | 6108 | i386_operand_type mask, allowed; |
87ed972d | 6109 | const insn_template *t = current_templates->start; |
9cd96992 | 6110 | |
0dfbf9d7 | 6111 | operand_type_set (&mask, 0); |
9cd96992 JB |
6112 | switch (guess_suffix) |
6113 | { | |
6114 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
6115 | mask.bitfield.imm64 = 1; |
6116 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
6117 | break; |
6118 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 6119 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
6120 | break; |
6121 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 6122 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
6123 | break; |
6124 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 6125 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
6126 | break; |
6127 | default: | |
9cd96992 JB |
6128 | break; |
6129 | } | |
8f0212ac JB |
6130 | |
6131 | allowed = operand_type_and (t->operand_types[op], mask); | |
6132 | while (++t < current_templates->end) | |
6133 | { | |
6134 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
6135 | allowed = operand_type_and (allowed, mask); | |
6136 | } | |
6137 | ||
0dfbf9d7 | 6138 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 6139 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 6140 | } |
29b0f896 | 6141 | break; |
252b5132 | 6142 | } |
29b0f896 AM |
6143 | } |
6144 | } | |
47926f60 | 6145 | |
29b0f896 AM |
6146 | /* Try to use the smallest displacement type too. */ |
6147 | static void | |
e3bb37b5 | 6148 | optimize_disp (void) |
29b0f896 AM |
6149 | { |
6150 | int op; | |
3e73aa7c | 6151 | |
29b0f896 | 6152 | for (op = i.operands; --op >= 0;) |
40fb9820 | 6153 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 6154 | { |
b300c311 | 6155 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 6156 | { |
91d6fa6a | 6157 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 6158 | |
91d6fa6a | 6159 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 6160 | { |
2f2be86b JB |
6161 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
6162 | i.op[op].disps = NULL; | |
b300c311 | 6163 | i.disp_operands--; |
f185acdd JB |
6164 | continue; |
6165 | } | |
6166 | ||
6167 | if (i.types[op].bitfield.disp16 | |
cd613c1f | 6168 | && fits_in_unsigned_word (op_disp)) |
f185acdd JB |
6169 | { |
6170 | /* If this operand is at most 16 bits, convert | |
6171 | to a signed 16 bit number and don't use 64bit | |
6172 | displacement. */ | |
6173 | op_disp = ((op_disp ^ 0x8000) - 0x8000); | |
6174 | i.types[op].bitfield.disp64 = 0; | |
b300c311 | 6175 | } |
f185acdd | 6176 | |
28a167a4 | 6177 | #ifdef BFD64 |
a50187b2 | 6178 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
a775efc8 JB |
6179 | if ((flag_code != CODE_64BIT |
6180 | ? i.types[op].bitfield.disp32 | |
6181 | : want_disp32 (current_templates->start) | |
6182 | && (!current_templates->start->opcode_modifier.jump | |
6183 | || i.jumpabsolute || i.types[op].bitfield.baseindex)) | |
a50187b2 | 6184 | && fits_in_unsigned_long (op_disp)) |
b300c311 | 6185 | { |
a50187b2 JB |
6186 | /* If this operand is at most 32 bits, convert |
6187 | to a signed 32 bit number and don't use 64bit | |
6188 | displacement. */ | |
6189 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
6190 | i.types[op].bitfield.disp64 = 0; | |
6191 | i.types[op].bitfield.disp32 = 1; | |
6192 | } | |
28a167a4 | 6193 | |
a50187b2 JB |
6194 | if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp)) |
6195 | { | |
6196 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 6197 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 6198 | } |
28a167a4 | 6199 | #endif |
40fb9820 | 6200 | if ((i.types[op].bitfield.disp32 |
40fb9820 | 6201 | || i.types[op].bitfield.disp16) |
b5014f7a | 6202 | && fits_in_disp8 (op_disp)) |
40fb9820 | 6203 | i.types[op].bitfield.disp8 = 1; |
77c59789 JB |
6204 | |
6205 | i.op[op].disps->X_add_number = op_disp; | |
252b5132 | 6206 | } |
67a4f2b7 AO |
6207 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
6208 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
6209 | { | |
6210 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
6211 | i.op[op].disps, 0, i.reloc[op]); | |
2f2be86b | 6212 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
67a4f2b7 AO |
6213 | } |
6214 | else | |
b300c311 | 6215 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 6216 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 6217 | } |
29b0f896 AM |
6218 | } |
6219 | ||
4a1b91ea L |
6220 | /* Return 1 if there is a match in broadcast bytes between operand |
6221 | GIVEN and instruction template T. */ | |
6222 | ||
6223 | static INLINE int | |
6224 | match_broadcast_size (const insn_template *t, unsigned int given) | |
6225 | { | |
6226 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
6227 | && i.types[given].bitfield.byte) | |
6228 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
6229 | && i.types[given].bitfield.word) | |
6230 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
6231 | && i.types[given].bitfield.dword) | |
6232 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
6233 | && i.types[given].bitfield.qword)); | |
6234 | } | |
6235 | ||
6c30d220 L |
6236 | /* Check if operands are valid for the instruction. */ |
6237 | ||
6238 | static int | |
6239 | check_VecOperands (const insn_template *t) | |
6240 | { | |
43234a1e | 6241 | unsigned int op; |
e2195274 | 6242 | i386_cpu_flags cpu; |
e2195274 JB |
6243 | |
6244 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
6245 | any one operand are implicity requiring AVX512VL support if the actual | |
6246 | operand size is YMMword or XMMword. Since this function runs after | |
6247 | template matching, there's no need to check for YMMword/XMMword in | |
6248 | the template. */ | |
6249 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
6250 | if (!cpu_flags_all_zero (&cpu) | |
6251 | && !t->cpu_flags.bitfield.cpuavx512vl | |
6252 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6253 | { | |
6254 | for (op = 0; op < t->operands; ++op) | |
6255 | { | |
6256 | if (t->operand_types[op].bitfield.zmmword | |
6257 | && (i.types[op].bitfield.ymmword | |
6258 | || i.types[op].bitfield.xmmword)) | |
6259 | { | |
6260 | i.error = unsupported; | |
6261 | return 1; | |
6262 | } | |
6263 | } | |
6264 | } | |
43234a1e | 6265 | |
22c36940 JB |
6266 | /* Somewhat similarly, templates specifying both AVX and AVX2 are |
6267 | requiring AVX2 support if the actual operand size is YMMword. */ | |
6268 | if (t->cpu_flags.bitfield.cpuavx | |
6269 | && t->cpu_flags.bitfield.cpuavx2 | |
6270 | && !cpu_arch_flags.bitfield.cpuavx2) | |
6271 | { | |
6272 | for (op = 0; op < t->operands; ++op) | |
6273 | { | |
6274 | if (t->operand_types[op].bitfield.xmmword | |
6275 | && i.types[op].bitfield.ymmword) | |
6276 | { | |
6277 | i.error = unsupported; | |
6278 | return 1; | |
6279 | } | |
6280 | } | |
6281 | } | |
6282 | ||
6c30d220 | 6283 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 6284 | if (!t->opcode_modifier.sib |
6c30d220 | 6285 | && i.index_reg |
1b54b8d7 JB |
6286 | && (i.index_reg->reg_type.bitfield.xmmword |
6287 | || i.index_reg->reg_type.bitfield.ymmword | |
6288 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
6289 | { |
6290 | i.error = unsupported_vector_index_register; | |
6291 | return 1; | |
6292 | } | |
6293 | ||
ad8ecc81 | 6294 | /* Check if default mask is allowed. */ |
255571cd | 6295 | if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK |
6225c532 | 6296 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
6297 | { |
6298 | i.error = no_default_mask; | |
6299 | return 1; | |
6300 | } | |
6301 | ||
7bab8ab5 JB |
6302 | /* For VSIB byte, we need a vector register for index, and all vector |
6303 | registers must be distinct. */ | |
260cd341 | 6304 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
6305 | { |
6306 | if (!i.index_reg | |
63112cd6 | 6307 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 6308 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 6309 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 6310 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 6311 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 6312 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
6313 | { |
6314 | i.error = invalid_vsib_address; | |
6315 | return 1; | |
6316 | } | |
6317 | ||
6225c532 JB |
6318 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
6319 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 6320 | { |
3528c362 | 6321 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6322 | gas_assert (i.types[0].bitfield.xmmword |
6323 | || i.types[0].bitfield.ymmword); | |
3528c362 | 6324 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6325 | gas_assert (i.types[2].bitfield.xmmword |
6326 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
6327 | if (operand_check == check_none) |
6328 | return 0; | |
6329 | if (register_number (i.op[0].regs) | |
6330 | != register_number (i.index_reg) | |
6331 | && register_number (i.op[2].regs) | |
6332 | != register_number (i.index_reg) | |
6333 | && register_number (i.op[0].regs) | |
6334 | != register_number (i.op[2].regs)) | |
6335 | return 0; | |
6336 | if (operand_check == check_error) | |
6337 | { | |
6338 | i.error = invalid_vector_register_set; | |
6339 | return 1; | |
6340 | } | |
6341 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6342 | } | |
6225c532 | 6343 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 6344 | { |
3528c362 | 6345 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
6346 | && (i.types[1].bitfield.xmmword |
6347 | || i.types[1].bitfield.ymmword | |
6348 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
6349 | && (register_number (i.op[1].regs) |
6350 | == register_number (i.index_reg))) | |
6351 | { | |
6352 | if (operand_check == check_error) | |
6353 | { | |
6354 | i.error = invalid_vector_register_set; | |
6355 | return 1; | |
6356 | } | |
6357 | if (operand_check != check_none) | |
6358 | as_warn (_("index and destination registers should be distinct")); | |
6359 | } | |
6360 | } | |
43234a1e | 6361 | } |
7bab8ab5 | 6362 | |
fc141319 L |
6363 | /* For AMX instructions with 3 TMM register operands, all operands |
6364 | must be distinct. */ | |
6365 | if (i.reg_operands == 3 | |
6366 | && t->operand_types[0].bitfield.tmmword | |
6367 | && (i.op[0].regs == i.op[1].regs | |
6368 | || i.op[0].regs == i.op[2].regs | |
6369 | || i.op[1].regs == i.op[2].regs)) | |
6370 | { | |
6371 | i.error = invalid_tmm_register_set; | |
6372 | return 1; | |
260cd341 LC |
6373 | } |
6374 | ||
0cc78721 CL |
6375 | /* For some special instructions require that destination must be distinct |
6376 | from source registers. */ | |
255571cd | 6377 | if (t->opcode_modifier.operandconstraint == DISTINCT_DEST) |
0cc78721 CL |
6378 | { |
6379 | unsigned int dest_reg = i.operands - 1; | |
6380 | ||
6381 | know (i.operands >= 3); | |
6382 | ||
6383 | /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */ | |
6384 | if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs | |
6385 | || (i.reg_operands > 2 | |
6386 | && i.op[dest_reg - 2].regs == i.op[dest_reg].regs)) | |
6387 | { | |
6388 | i.error = invalid_dest_and_src_register_set; | |
6389 | return 1; | |
6390 | } | |
6391 | } | |
6392 | ||
43234a1e L |
6393 | /* Check if broadcast is supported by the instruction and is applied |
6394 | to the memory operand. */ | |
a5748e0d | 6395 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 6396 | { |
8e6e0792 | 6397 | i386_operand_type type, overlap; |
43234a1e L |
6398 | |
6399 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 6400 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 6401 | op = i.broadcast.operand; |
8e6e0792 | 6402 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 6403 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 6404 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 6405 | && !match_broadcast_size (t, op))) |
43234a1e L |
6406 | { |
6407 | bad_broadcast: | |
6408 | i.error = unsupported_broadcast; | |
6409 | return 1; | |
6410 | } | |
8e6e0792 JB |
6411 | |
6412 | operand_type_set (&type, 0); | |
a5748e0d | 6413 | switch (get_broadcast_bytes (t, false)) |
8e6e0792 | 6414 | { |
4a1b91ea L |
6415 | case 2: |
6416 | type.bitfield.word = 1; | |
6417 | break; | |
6418 | case 4: | |
6419 | type.bitfield.dword = 1; | |
6420 | break; | |
8e6e0792 JB |
6421 | case 8: |
6422 | type.bitfield.qword = 1; | |
6423 | break; | |
6424 | case 16: | |
6425 | type.bitfield.xmmword = 1; | |
6426 | break; | |
6427 | case 32: | |
6428 | type.bitfield.ymmword = 1; | |
6429 | break; | |
6430 | case 64: | |
6431 | type.bitfield.zmmword = 1; | |
6432 | break; | |
6433 | default: | |
6434 | goto bad_broadcast; | |
6435 | } | |
6436 | ||
6437 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
6438 | if (t->operand_types[op].bitfield.class == RegSIMD |
6439 | && t->operand_types[op].bitfield.byte | |
6440 | + t->operand_types[op].bitfield.word | |
6441 | + t->operand_types[op].bitfield.dword | |
6442 | + t->operand_types[op].bitfield.qword > 1) | |
6443 | { | |
6444 | overlap.bitfield.xmmword = 0; | |
6445 | overlap.bitfield.ymmword = 0; | |
6446 | overlap.bitfield.zmmword = 0; | |
6447 | } | |
8e6e0792 JB |
6448 | if (operand_type_all_zero (&overlap)) |
6449 | goto bad_broadcast; | |
6450 | ||
9c19e9ec | 6451 | if (t->opcode_modifier.checkoperandsize) |
8e6e0792 JB |
6452 | { |
6453 | unsigned int j; | |
6454 | ||
e2195274 | 6455 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
6456 | for (j = 0; j < i.operands; ++j) |
6457 | { | |
6458 | if (j != op | |
6459 | && !operand_type_register_match(i.types[j], | |
6460 | t->operand_types[j], | |
6461 | type, | |
6462 | t->operand_types[op])) | |
6463 | goto bad_broadcast; | |
6464 | } | |
6465 | } | |
43234a1e L |
6466 | } |
6467 | /* If broadcast is supported in this instruction, we need to check if | |
6468 | operand of one-element size isn't specified without broadcast. */ | |
6469 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
6470 | { | |
6471 | /* Find memory operand. */ | |
6472 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6473 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
6474 | break; |
6475 | gas_assert (op < i.operands); | |
6476 | /* Check size of the memory operand. */ | |
4a1b91ea | 6477 | if (match_broadcast_size (t, op)) |
43234a1e L |
6478 | { |
6479 | i.error = broadcast_needed; | |
6480 | return 1; | |
6481 | } | |
6482 | } | |
c39e5b26 JB |
6483 | else |
6484 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
6485 | |
6486 | /* Check if requested masking is supported. */ | |
6225c532 | 6487 | if (i.mask.reg) |
43234a1e | 6488 | { |
ae2387fe JB |
6489 | switch (t->opcode_modifier.masking) |
6490 | { | |
6491 | case BOTH_MASKING: | |
6492 | break; | |
6493 | case MERGING_MASKING: | |
6225c532 | 6494 | if (i.mask.zeroing) |
ae2387fe JB |
6495 | { |
6496 | case 0: | |
6497 | i.error = unsupported_masking; | |
6498 | return 1; | |
6499 | } | |
6500 | break; | |
6501 | case DYNAMIC_MASKING: | |
6502 | /* Memory destinations allow only merging masking. */ | |
6225c532 | 6503 | if (i.mask.zeroing && i.mem_operands) |
ae2387fe JB |
6504 | { |
6505 | /* Find memory operand. */ | |
6506 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 6507 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
6508 | break; |
6509 | gas_assert (op < i.operands); | |
6510 | if (op == i.operands - 1) | |
6511 | { | |
6512 | i.error = unsupported_masking; | |
6513 | return 1; | |
6514 | } | |
6515 | } | |
6516 | break; | |
6517 | default: | |
6518 | abort (); | |
6519 | } | |
43234a1e L |
6520 | } |
6521 | ||
6522 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 6523 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
6524 | { |
6525 | i.error = mask_not_on_destination; | |
6526 | return 1; | |
6527 | } | |
6528 | ||
43234a1e | 6529 | /* Check RC/SAE. */ |
ca5312a2 | 6530 | if (i.rounding.type != rc_none) |
43234a1e | 6531 | { |
a80195f1 | 6532 | if (!t->opcode_modifier.sae |
cf665fee JB |
6533 | || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding) |
6534 | || i.mem_operands) | |
43234a1e L |
6535 | { |
6536 | i.error = unsupported_rc_sae; | |
6537 | return 1; | |
6538 | } | |
cf665fee JB |
6539 | |
6540 | /* Non-EVEX.LIG forms need to have a ZMM register as at least one | |
6541 | operand. */ | |
6542 | if (t->opcode_modifier.evex != EVEXLIG) | |
7bab8ab5 | 6543 | { |
cf665fee JB |
6544 | for (op = 0; op < t->operands; ++op) |
6545 | if (i.types[op].bitfield.zmmword) | |
6546 | break; | |
6547 | if (op >= t->operands) | |
6548 | { | |
6549 | i.error = operand_size_mismatch; | |
6550 | return 1; | |
6551 | } | |
7bab8ab5 | 6552 | } |
6c30d220 L |
6553 | } |
6554 | ||
da4977e0 JB |
6555 | /* Check the special Imm4 cases; must be the first operand. */ |
6556 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
6557 | { | |
6558 | if (i.op[0].imms->X_op != O_constant | |
6559 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
6560 | { | |
6561 | i.error = bad_imm4; | |
6562 | return 1; | |
6563 | } | |
6564 | ||
6565 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
6566 | operand_type_set (&i.types[0], 0); | |
6567 | } | |
6568 | ||
43234a1e | 6569 | /* Check vector Disp8 operand. */ |
b5014f7a | 6570 | if (t->opcode_modifier.disp8memshift |
1a42a9fe | 6571 | && i.disp_encoding <= disp_encoding_8bit) |
43234a1e | 6572 | { |
a5748e0d | 6573 | if (i.broadcast.bytes) |
4a1b91ea | 6574 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 6575 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 6576 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
6577 | else |
6578 | { | |
125ff819 | 6579 | const i386_operand_type *type = NULL, *fallback = NULL; |
7091c612 JB |
6580 | |
6581 | i.memshift = 0; | |
6582 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6583 | if (i.flags[op] & Operand_Mem) |
7091c612 | 6584 | { |
4174bfff JB |
6585 | if (t->opcode_modifier.evex == EVEXLIG) |
6586 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
6587 | else if (t->operand_types[op].bitfield.xmmword | |
6588 | + t->operand_types[op].bitfield.ymmword | |
6589 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
6590 | type = &t->operand_types[op]; |
6591 | else if (!i.types[op].bitfield.unspecified) | |
6592 | type = &i.types[op]; | |
125ff819 JB |
6593 | else /* Ambiguities get resolved elsewhere. */ |
6594 | fallback = &t->operand_types[op]; | |
7091c612 | 6595 | } |
3528c362 | 6596 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 6597 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
6598 | { |
6599 | if (i.types[op].bitfield.zmmword) | |
6600 | i.memshift = 6; | |
6601 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
6602 | i.memshift = 5; | |
6603 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
6604 | i.memshift = 4; | |
6605 | } | |
6606 | ||
125ff819 JB |
6607 | if (!type && !i.memshift) |
6608 | type = fallback; | |
7091c612 JB |
6609 | if (type) |
6610 | { | |
6611 | if (type->bitfield.zmmword) | |
6612 | i.memshift = 6; | |
6613 | else if (type->bitfield.ymmword) | |
6614 | i.memshift = 5; | |
6615 | else if (type->bitfield.xmmword) | |
6616 | i.memshift = 4; | |
6617 | } | |
6618 | ||
6619 | /* For the check in fits_in_disp8(). */ | |
6620 | if (i.memshift == 0) | |
6621 | i.memshift = -1; | |
6622 | } | |
43234a1e L |
6623 | |
6624 | for (op = 0; op < i.operands; op++) | |
6625 | if (operand_type_check (i.types[op], disp) | |
6626 | && i.op[op].disps->X_op == O_constant) | |
6627 | { | |
b5014f7a | 6628 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 6629 | { |
b5014f7a JB |
6630 | i.types[op].bitfield.disp8 = 1; |
6631 | return 0; | |
43234a1e | 6632 | } |
b5014f7a | 6633 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
6634 | } |
6635 | } | |
b5014f7a JB |
6636 | |
6637 | i.memshift = 0; | |
43234a1e | 6638 | |
6c30d220 L |
6639 | return 0; |
6640 | } | |
6641 | ||
da4977e0 | 6642 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
6643 | |
6644 | static int | |
da4977e0 | 6645 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 6646 | { |
da4977e0 JB |
6647 | if (i.vec_encoding == vex_encoding_error) |
6648 | { | |
6649 | i.error = unsupported; | |
6650 | return 1; | |
6651 | } | |
6652 | ||
86fa6981 | 6653 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 6654 | { |
86fa6981 | 6655 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 6656 | if (!is_evex_encoding (t)) |
86fa6981 L |
6657 | { |
6658 | i.error = unsupported; | |
6659 | return 1; | |
6660 | } | |
6661 | return 0; | |
43234a1e L |
6662 | } |
6663 | ||
a683cc34 | 6664 | if (!t->opcode_modifier.vex) |
86fa6981 L |
6665 | { |
6666 | /* This instruction template doesn't have VEX prefix. */ | |
6667 | if (i.vec_encoding != vex_encoding_default) | |
6668 | { | |
6669 | i.error = unsupported; | |
6670 | return 1; | |
6671 | } | |
6672 | return 0; | |
6673 | } | |
a683cc34 | 6674 | |
a683cc34 SP |
6675 | return 0; |
6676 | } | |
6677 | ||
7b94647a JB |
6678 | /* Helper function for the progress() macro in match_template(). */ |
6679 | static INLINE enum i386_error progress (enum i386_error new, | |
6680 | enum i386_error last, | |
6681 | unsigned int line, unsigned int *line_p) | |
6682 | { | |
6683 | if (line <= *line_p) | |
6684 | return last; | |
6685 | *line_p = line; | |
6686 | return new; | |
6687 | } | |
6688 | ||
d3ce72d0 | 6689 | static const insn_template * |
83b16ac6 | 6690 | match_template (char mnem_suffix) |
29b0f896 AM |
6691 | { |
6692 | /* Points to template once we've found it. */ | |
d3ce72d0 | 6693 | const insn_template *t; |
40fb9820 | 6694 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 6695 | i386_operand_type overlap4; |
29b0f896 | 6696 | unsigned int found_reverse_match; |
40fb9820 | 6697 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 6698 | int addr_prefix_disp; |
7b94647a JB |
6699 | unsigned int j, size_match, check_register, errline = __LINE__; |
6700 | enum i386_error specific_error = number_of_operands_mismatch; | |
6701 | #define progress(err) progress (err, specific_error, __LINE__, &errline) | |
29b0f896 | 6702 | |
c0f3af97 L |
6703 | #if MAX_OPERANDS != 5 |
6704 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
6705 | #endif |
6706 | ||
29b0f896 | 6707 | found_reverse_match = 0; |
539e75ad | 6708 | addr_prefix_disp = -1; |
40fb9820 | 6709 | |
45aa61fe | 6710 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 6711 | { |
539e75ad | 6712 | addr_prefix_disp = -1; |
dbbc8b7e | 6713 | found_reverse_match = 0; |
539e75ad | 6714 | |
7b94647a | 6715 | /* Must have right number of operands. */ |
29b0f896 AM |
6716 | if (i.operands != t->operands) |
6717 | continue; | |
6718 | ||
50aecf8c | 6719 | /* Check processor support. */ |
7b94647a | 6720 | specific_error = progress (unsupported); |
45a4bb20 | 6721 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
6722 | continue; |
6723 | ||
e1d4d893 | 6724 | /* Check AT&T mnemonic. */ |
7b94647a | 6725 | specific_error = progress (unsupported_with_intel_mnemonic); |
e1d4d893 | 6726 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
6727 | continue; |
6728 | ||
4b5aaf5f | 6729 | /* Check AT&T/Intel syntax. */ |
7b94647a | 6730 | specific_error = progress (unsupported_syntax); |
5c07affc | 6731 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 6732 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
6733 | continue; |
6734 | ||
4b5aaf5f L |
6735 | /* Check Intel64/AMD64 ISA. */ |
6736 | switch (isa64) | |
6737 | { | |
6738 | default: | |
6739 | /* Default: Don't accept Intel64. */ | |
6740 | if (t->opcode_modifier.isa64 == INTEL64) | |
6741 | continue; | |
6742 | break; | |
6743 | case amd64: | |
6744 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
6745 | if (t->opcode_modifier.isa64 >= INTEL64) | |
6746 | continue; | |
6747 | break; | |
6748 | case intel64: | |
6749 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 6750 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
6751 | continue; |
6752 | break; | |
6753 | } | |
6754 | ||
dc2be329 | 6755 | /* Check the suffix. */ |
7b94647a | 6756 | specific_error = progress (invalid_instruction_suffix); |
7505bb03 JB |
6757 | if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX) |
6758 | || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX) | |
6759 | || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX) | |
6760 | || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX) | |
6761 | || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX)) | |
83b16ac6 | 6762 | continue; |
29b0f896 | 6763 | |
7b94647a | 6764 | specific_error = progress (operand_size_mismatch); |
3ac21baa JB |
6765 | size_match = operand_size_match (t); |
6766 | if (!size_match) | |
7d5e4556 | 6767 | continue; |
539e75ad | 6768 | |
6f2f06be JB |
6769 | /* This is intentionally not |
6770 | ||
0cfa3eb3 | 6771 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
6772 | |
6773 | as the case of a missing * on the operand is accepted (perhaps with | |
6774 | a warning, issued further down). */ | |
7b94647a | 6775 | specific_error = progress (operand_type_mismatch); |
0cfa3eb3 | 6776 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
7b94647a | 6777 | continue; |
6f2f06be | 6778 | |
a4d3acd2 JB |
6779 | /* In Intel syntax, normally we can check for memory operand size when |
6780 | there is no mnemonic suffix. But jmp and call have 2 different | |
6781 | encodings with Dword memory operand size. Skip the "near" one | |
6782 | (permitting a register operand) when "far" was requested. */ | |
6783 | if (i.far_branch | |
6784 | && t->opcode_modifier.jump == JUMP_ABSOLUTE | |
6785 | && t->operand_types[0].bitfield.class == Reg) | |
6786 | continue; | |
6787 | ||
5c07affc L |
6788 | for (j = 0; j < MAX_OPERANDS; j++) |
6789 | operand_types[j] = t->operand_types[j]; | |
6790 | ||
9db83a32 | 6791 | /* In general, don't allow 32-bit operands on pre-386. */ |
7b94647a JB |
6792 | specific_error = progress (mnem_suffix ? invalid_instruction_suffix |
6793 | : operand_size_mismatch); | |
4873e243 | 6794 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
9db83a32 JB |
6795 | if (i.suffix == LONG_MNEM_SUFFIX |
6796 | && !cpu_arch_flags.bitfield.cpui386 | |
45aa61fe | 6797 | && (intel_syntax |
3cd7f3e3 | 6798 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
76d3f746 JB |
6799 | && !intel_float_operand (insn_name (t))) |
6800 | : intel_float_operand (insn_name (t)) != 2) | |
4873e243 JB |
6801 | && (t->operands == i.imm_operands |
6802 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
6803 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
6804 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
6805 | || (operand_types[j].bitfield.class != RegMMX | |
6806 | && operand_types[j].bitfield.class != RegSIMD | |
6807 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 6808 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
6809 | continue; |
6810 | ||
29b0f896 | 6811 | /* Do not verify operands when there are none. */ |
e365e234 | 6812 | if (!t->operands) |
da4977e0 JB |
6813 | { |
6814 | if (VEX_check_encoding (t)) | |
6815 | { | |
7b94647a | 6816 | specific_error = progress (i.error); |
da4977e0 JB |
6817 | continue; |
6818 | } | |
6819 | ||
6820 | /* We've found a match; break out of loop. */ | |
6821 | break; | |
6822 | } | |
252b5132 | 6823 | |
48bcea9f JB |
6824 | if (!t->opcode_modifier.jump |
6825 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
6826 | { | |
6827 | /* There should be only one Disp operand. */ | |
6828 | for (j = 0; j < MAX_OPERANDS; j++) | |
6829 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 6830 | break; |
48bcea9f JB |
6831 | if (j < MAX_OPERANDS) |
6832 | { | |
5b7c81bd | 6833 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
6834 | |
6835 | addr_prefix_disp = j; | |
6836 | ||
a775efc8 JB |
6837 | /* Address size prefix will turn Disp64 operand into Disp32 and |
6838 | Disp32/Disp16 one into Disp16/Disp32 respectively. */ | |
48bcea9f | 6839 | switch (flag_code) |
40fb9820 | 6840 | { |
48bcea9f JB |
6841 | case CODE_16BIT: |
6842 | override = !override; | |
6843 | /* Fall through. */ | |
6844 | case CODE_32BIT: | |
6845 | if (operand_types[j].bitfield.disp32 | |
6846 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 6847 | { |
48bcea9f JB |
6848 | operand_types[j].bitfield.disp16 = override; |
6849 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 6850 | } |
a775efc8 | 6851 | gas_assert (!operand_types[j].bitfield.disp64); |
48bcea9f JB |
6852 | break; |
6853 | ||
6854 | case CODE_64BIT: | |
a775efc8 | 6855 | if (operand_types[j].bitfield.disp64) |
40fb9820 | 6856 | { |
a775efc8 | 6857 | gas_assert (!operand_types[j].bitfield.disp32); |
48bcea9f | 6858 | operand_types[j].bitfield.disp32 = override; |
a775efc8 | 6859 | operand_types[j].bitfield.disp64 = !override; |
40fb9820 | 6860 | } |
48bcea9f JB |
6861 | operand_types[j].bitfield.disp16 = 0; |
6862 | break; | |
40fb9820 | 6863 | } |
539e75ad | 6864 | } |
48bcea9f | 6865 | } |
539e75ad | 6866 | |
56ffb741 | 6867 | /* We check register size if needed. */ |
9c19e9ec | 6868 | if (t->opcode_modifier.checkoperandsize) |
e2195274 JB |
6869 | { |
6870 | check_register = (1 << t->operands) - 1; | |
a5748e0d | 6871 | if (i.broadcast.type || i.broadcast.bytes) |
5273a3cd | 6872 | check_register &= ~(1 << i.broadcast.operand); |
e2195274 JB |
6873 | } |
6874 | else | |
6875 | check_register = 0; | |
6876 | ||
c6fb90c8 | 6877 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
6878 | switch (t->operands) |
6879 | { | |
6880 | case 1: | |
40fb9820 | 6881 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 | 6882 | continue; |
ae9a0a51 JB |
6883 | |
6884 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
6885 | {store} pseudo prefix on an applicable insn. */ | |
6886 | if (!t->opcode_modifier.modrm | |
6887 | && i.reg_operands == 1 | |
6888 | && ((i.dir_encoding == dir_encoding_load | |
6889 | && t->mnem_off != MN_pop) | |
6890 | || (i.dir_encoding == dir_encoding_store | |
6891 | && t->mnem_off != MN_push)) | |
6892 | /* Avoid BSWAP. */ | |
6893 | && t->mnem_off != MN_bswap) | |
6894 | continue; | |
29b0f896 | 6895 | break; |
ae9a0a51 | 6896 | |
29b0f896 | 6897 | case 2: |
33eaf5de | 6898 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
6899 | only in 32bit mode and we can use opcode 0x90. In 64bit |
6900 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
6901 | zero-extend %eax to %rax. */ | |
ae9a0a51 JB |
6902 | if (t->base_opcode == 0x90 |
6903 | && t->opcode_space == SPACE_BASE) | |
6904 | { | |
6905 | if (flag_code == CODE_64BIT | |
6906 | && i.types[0].bitfield.instance == Accum | |
6907 | && i.types[0].bitfield.dword | |
6908 | && i.types[1].bitfield.instance == Accum) | |
6909 | continue; | |
6910 | ||
6911 | /* Allow the ModR/M encoding to be requested by using the | |
6912 | {load} or {store} pseudo prefix. */ | |
6913 | if (i.dir_encoding == dir_encoding_load | |
6914 | || i.dir_encoding == dir_encoding_store) | |
6915 | continue; | |
6916 | } | |
e3669c7f JB |
6917 | |
6918 | if (t->base_opcode == MOV_AX_DISP32 | |
ddb62495 | 6919 | && t->opcode_space == SPACE_BASE |
69196391 | 6920 | && t->mnem_off != MN_movabs) |
e3669c7f JB |
6921 | { |
6922 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ | |
6923 | if (i.reloc[0] == BFD_RELOC_386_GOT32) | |
6924 | continue; | |
6925 | ||
6926 | /* xrelease mov %eax, <disp> is another special case. It must not | |
6927 | match the accumulator-only encoding of mov. */ | |
6928 | if (i.hle_prefix) | |
6929 | continue; | |
ae9a0a51 JB |
6930 | |
6931 | /* Allow the ModR/M encoding to be requested by using a suitable | |
6932 | {load} or {store} pseudo prefix. */ | |
6933 | if (i.dir_encoding == (i.types[0].bitfield.instance == Accum | |
6934 | ? dir_encoding_store | |
6935 | : dir_encoding_load) | |
6936 | && !i.types[0].bitfield.disp64 | |
6937 | && !i.types[1].bitfield.disp64) | |
6938 | continue; | |
6939 | } | |
6940 | ||
6941 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
6942 | {store} pseudo prefix on an applicable insn. */ | |
6943 | if (!t->opcode_modifier.modrm | |
6944 | && i.reg_operands == 1 | |
6945 | && i.imm_operands == 1 | |
6946 | && (i.dir_encoding == dir_encoding_load | |
6947 | || i.dir_encoding == dir_encoding_store) | |
6948 | && t->opcode_space == SPACE_BASE) | |
6949 | { | |
6950 | if (t->base_opcode == 0xb0 /* mov $imm, %reg */ | |
6951 | && i.dir_encoding == dir_encoding_store) | |
6952 | continue; | |
6953 | ||
6954 | if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */ | |
6955 | && (t->base_opcode != 0x3c /* cmp $imm, %acc */ | |
6956 | || i.dir_encoding == dir_encoding_load)) | |
6957 | continue; | |
6958 | ||
6959 | if (t->base_opcode == 0xa8 /* test $imm, %acc */ | |
6960 | && i.dir_encoding == dir_encoding_load) | |
6961 | continue; | |
e3669c7f | 6962 | } |
f5eb1d70 JB |
6963 | /* Fall through. */ |
6964 | ||
6965 | case 3: | |
3ac21baa JB |
6966 | if (!(size_match & MATCH_STRAIGHT)) |
6967 | goto check_reverse; | |
64c49ab3 JB |
6968 | /* Reverse direction of operands if swapping is possible in the first |
6969 | place (operands need to be symmetric) and | |
6970 | - the load form is requested, and the template is a store form, | |
6971 | - the store form is requested, and the template is a load form, | |
6972 | - the non-default (swapped) form is requested. */ | |
6973 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6974 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6975 | && !operand_type_all_zero (&overlap1)) |
6976 | switch (i.dir_encoding) | |
6977 | { | |
6978 | case dir_encoding_load: | |
6979 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6980 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6981 | goto check_reverse; |
6982 | break; | |
6983 | ||
6984 | case dir_encoding_store: | |
6985 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6986 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6987 | goto check_reverse; |
6988 | break; | |
6989 | ||
6990 | case dir_encoding_swap: | |
6991 | goto check_reverse; | |
6992 | ||
6993 | case dir_encoding_default: | |
6994 | break; | |
6995 | } | |
86fa6981 | 6996 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6997 | if ((i.dir_encoding == dir_encoding_store |
6998 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6999 | && i.mem_operands == 0 |
7000 | && t->opcode_modifier.load) | |
fa99fab2 | 7001 | continue; |
1a0670f3 | 7002 | /* Fall through. */ |
f48ff2ae | 7003 | case 4: |
c0f3af97 | 7004 | case 5: |
c6fb90c8 | 7005 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
7006 | if (!operand_type_match (overlap0, i.types[0]) |
7007 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 7008 | || ((check_register & 3) == 3 |
dc821c5f | 7009 | && !operand_type_register_match (i.types[0], |
40fb9820 | 7010 | operand_types[0], |
dc821c5f | 7011 | i.types[1], |
40fb9820 | 7012 | operand_types[1]))) |
29b0f896 | 7013 | { |
7b94647a JB |
7014 | specific_error = progress (i.error); |
7015 | ||
29b0f896 | 7016 | /* Check if other direction is valid ... */ |
38e314eb | 7017 | if (!t->opcode_modifier.d) |
29b0f896 AM |
7018 | continue; |
7019 | ||
dc1e8a47 | 7020 | check_reverse: |
3ac21baa JB |
7021 | if (!(size_match & MATCH_REVERSE)) |
7022 | continue; | |
29b0f896 | 7023 | /* Try reversing direction of operands. */ |
aa180741 | 7024 | j = t->cpu_flags.bitfield.cpufma4 |
5dab1799 | 7025 | || t->cpu_flags.bitfield.cpuxop ? 1 : i.operands - 1; |
8bd915b7 JB |
7026 | overlap0 = operand_type_and (i.types[0], operand_types[j]); |
7027 | overlap1 = operand_type_and (i.types[j], operand_types[0]); | |
c975cec5 JB |
7028 | overlap2 = operand_type_and (i.types[1], operand_types[1]); |
7029 | gas_assert (t->operands != 3 || !check_register); | |
40fb9820 | 7030 | if (!operand_type_match (overlap0, i.types[0]) |
8bd915b7 | 7031 | || !operand_type_match (overlap1, i.types[j]) |
c975cec5 JB |
7032 | || (t->operands == 3 |
7033 | && !operand_type_match (overlap2, i.types[1])) | |
45664ddb | 7034 | || (check_register |
dc821c5f | 7035 | && !operand_type_register_match (i.types[0], |
8bd915b7 JB |
7036 | operand_types[j], |
7037 | i.types[j], | |
45664ddb | 7038 | operand_types[0]))) |
29b0f896 AM |
7039 | { |
7040 | /* Does not match either direction. */ | |
7b94647a | 7041 | specific_error = progress (i.error); |
29b0f896 AM |
7042 | continue; |
7043 | } | |
ac9226cf | 7044 | /* found_reverse_match holds which variant of D |
29b0f896 | 7045 | we've found. */ |
38e314eb JB |
7046 | if (!t->opcode_modifier.d) |
7047 | found_reverse_match = 0; | |
7048 | else if (operand_types[0].bitfield.tbyte) | |
ac9226cf | 7049 | { |
4943d587 JB |
7050 | if (t->opcode_modifier.operandconstraint != UGH) |
7051 | found_reverse_match = Opcode_FloatD; | |
bd782808 JB |
7052 | else |
7053 | found_reverse_match = ~0; | |
ac9226cf | 7054 | /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ |
bd782808 | 7055 | if ((t->extension_opcode & 4) |
ac9226cf JB |
7056 | && (intel_syntax || intel_mnemonic)) |
7057 | found_reverse_match |= Opcode_FloatR; | |
7058 | } | |
aa180741 | 7059 | else if (t->cpu_flags.bitfield.cpufma4 |
5dab1799 | 7060 | || t->cpu_flags.bitfield.cpuxop) |
8bd915b7 JB |
7061 | { |
7062 | found_reverse_match = Opcode_VexW; | |
7063 | goto check_operands_345; | |
7064 | } | |
ddb62495 JB |
7065 | else if (t->opcode_space != SPACE_BASE |
7066 | && (t->opcode_space != SPACE_0F | |
2c735193 JB |
7067 | /* MOV to/from CR/DR/TR, as an exception, follow |
7068 | the base opcode space encoding model. */ | |
7069 | || (t->base_opcode | 7) != 0x27)) | |
dbbc8b7e | 7070 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e |
2c735193 | 7071 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
a33ef3c2 | 7072 | else if (!t->opcode_modifier.commutative) |
38e314eb | 7073 | found_reverse_match = Opcode_D; |
a33ef3c2 JB |
7074 | else |
7075 | found_reverse_match = ~0; | |
29b0f896 | 7076 | } |
f48ff2ae | 7077 | else |
29b0f896 | 7078 | { |
f48ff2ae | 7079 | /* Found a forward 2 operand match here. */ |
8bd915b7 | 7080 | check_operands_345: |
d1cbb4db L |
7081 | switch (t->operands) |
7082 | { | |
c0f3af97 | 7083 | case 5: |
3d0738af | 7084 | overlap4 = operand_type_and (i.types[4], operand_types[4]); |
c0f3af97 | 7085 | if (!operand_type_match (overlap4, i.types[4]) |
dc821c5f | 7086 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 7087 | operand_types[3], |
c0f3af97 L |
7088 | i.types[4], |
7089 | operand_types[4])) | |
7b94647a JB |
7090 | { |
7091 | specific_error = progress (i.error); | |
7092 | continue; | |
7093 | } | |
1a0670f3 | 7094 | /* Fall through. */ |
f48ff2ae | 7095 | case 4: |
3d0738af | 7096 | overlap3 = operand_type_and (i.types[3], operand_types[3]); |
40fb9820 | 7097 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
7098 | || ((check_register & 0xa) == 0xa |
7099 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
7100 | operand_types[1], |
7101 | i.types[3], | |
e2195274 JB |
7102 | operand_types[3])) |
7103 | || ((check_register & 0xc) == 0xc | |
7104 | && !operand_type_register_match (i.types[2], | |
7105 | operand_types[2], | |
7106 | i.types[3], | |
7107 | operand_types[3]))) | |
7b94647a JB |
7108 | { |
7109 | specific_error = progress (i.error); | |
7110 | continue; | |
7111 | } | |
1a0670f3 | 7112 | /* Fall through. */ |
f48ff2ae | 7113 | case 3: |
3d0738af | 7114 | overlap2 = operand_type_and (i.types[2], operand_types[2]); |
40fb9820 | 7115 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
7116 | || ((check_register & 5) == 5 |
7117 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
7118 | operand_types[0], |
7119 | i.types[2], | |
e2195274 JB |
7120 | operand_types[2])) |
7121 | || ((check_register & 6) == 6 | |
7122 | && !operand_type_register_match (i.types[1], | |
7123 | operand_types[1], | |
7124 | i.types[2], | |
7125 | operand_types[2]))) | |
7b94647a JB |
7126 | { |
7127 | specific_error = progress (i.error); | |
7128 | continue; | |
7129 | } | |
f48ff2ae L |
7130 | break; |
7131 | } | |
29b0f896 | 7132 | } |
f48ff2ae | 7133 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
7134 | slip through to break. */ |
7135 | } | |
c0f3af97 | 7136 | |
9bb4d860 L |
7137 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ |
7138 | if (VEX_check_encoding (t)) | |
da4977e0 | 7139 | { |
7b94647a | 7140 | specific_error = progress (i.error); |
da4977e0 JB |
7141 | continue; |
7142 | } | |
7143 | ||
9bb4d860 L |
7144 | /* Check if vector operands are valid. */ |
7145 | if (check_VecOperands (t)) | |
5614d22c | 7146 | { |
7b94647a | 7147 | specific_error = progress (i.error); |
5614d22c JB |
7148 | continue; |
7149 | } | |
a683cc34 | 7150 | |
29b0f896 AM |
7151 | /* We've found a match; break out of loop. */ |
7152 | break; | |
7153 | } | |
7154 | ||
7b94647a JB |
7155 | #undef progress |
7156 | ||
29b0f896 AM |
7157 | if (t == current_templates->end) |
7158 | { | |
7159 | /* We found no match. */ | |
04784e33 | 7160 | i.error = specific_error; |
fa99fab2 | 7161 | return NULL; |
29b0f896 | 7162 | } |
252b5132 | 7163 | |
29b0f896 AM |
7164 | if (!quiet_warnings) |
7165 | { | |
7166 | if (!intel_syntax | |
0cfa3eb3 | 7167 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
76d3f746 | 7168 | as_warn (_("indirect %s without `*'"), insn_name (t)); |
29b0f896 | 7169 | |
40fb9820 | 7170 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 7171 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
7172 | { |
7173 | /* Warn them that a data or address size prefix doesn't | |
7174 | affect assembly of the next line of code. */ | |
76d3f746 | 7175 | as_warn (_("stand-alone `%s' prefix"), insn_name (t)); |
29b0f896 AM |
7176 | } |
7177 | } | |
7178 | ||
7179 | /* Copy the template we found. */ | |
9a182d04 | 7180 | install_template (t); |
539e75ad L |
7181 | |
7182 | if (addr_prefix_disp != -1) | |
7183 | i.tm.operand_types[addr_prefix_disp] | |
7184 | = operand_types[addr_prefix_disp]; | |
7185 | ||
8bd915b7 | 7186 | switch (found_reverse_match) |
29b0f896 | 7187 | { |
8bd915b7 JB |
7188 | case 0: |
7189 | break; | |
7190 | ||
bd782808 JB |
7191 | case Opcode_FloatR: |
7192 | case Opcode_FloatR | Opcode_FloatD: | |
7193 | i.tm.extension_opcode ^= Opcode_FloatR >> 3; | |
7194 | found_reverse_match &= Opcode_FloatD; | |
7195 | ||
7196 | /* Fall through. */ | |
8bd915b7 | 7197 | default: |
dfd69174 JB |
7198 | /* If we found a reverse match we must alter the opcode direction |
7199 | bit and clear/flip the regmem modifier one. found_reverse_match | |
7200 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
7201 | |
7202 | i.tm.base_opcode ^= found_reverse_match; | |
7203 | ||
dfd69174 JB |
7204 | /* Certain SIMD insns have their load forms specified in the opcode |
7205 | table, and hence we need to _set_ RegMem instead of clearing it. | |
7206 | We need to avoid setting the bit though on insns like KMOVW. */ | |
7207 | i.tm.opcode_modifier.regmem | |
7208 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
7209 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
7210 | && !i.tm.opcode_modifier.regmem; | |
a33ef3c2 JB |
7211 | |
7212 | /* Fall through. */ | |
7213 | case ~0: | |
7214 | i.tm.operand_types[0] = operand_types[i.operands - 1]; | |
7215 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
8bd915b7 JB |
7216 | break; |
7217 | ||
7218 | case Opcode_VexW: | |
7219 | /* Only the first two register operands need reversing, alongside | |
7220 | flipping VEX.W. */ | |
7221 | i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1; | |
7222 | ||
7223 | j = i.tm.operand_types[0].bitfield.imm8; | |
7224 | i.tm.operand_types[j] = operand_types[j + 1]; | |
7225 | i.tm.operand_types[j + 1] = operand_types[j]; | |
7226 | break; | |
29b0f896 AM |
7227 | } |
7228 | ||
fa99fab2 | 7229 | return t; |
29b0f896 AM |
7230 | } |
7231 | ||
7232 | static int | |
e3bb37b5 | 7233 | check_string (void) |
29b0f896 | 7234 | { |
51c8edf6 JB |
7235 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
7236 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 7237 | |
5e042380 | 7238 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 7239 | { |
51c8edf6 | 7240 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
76d3f746 | 7241 | insn_name (&i.tm), |
51c8edf6 JB |
7242 | intel_syntax ? i.tm.operands - es_op : es_op + 1, |
7243 | register_prefix); | |
7244 | return 0; | |
29b0f896 | 7245 | } |
51c8edf6 JB |
7246 | |
7247 | /* There's only ever one segment override allowed per instruction. | |
7248 | This instruction possibly has a legal segment override on the | |
7249 | second operand, so copy the segment to where non-string | |
7250 | instructions store it, allowing common code. */ | |
7251 | i.seg[op] = i.seg[1]; | |
7252 | ||
29b0f896 AM |
7253 | return 1; |
7254 | } | |
7255 | ||
7256 | static int | |
543613e9 | 7257 | process_suffix (void) |
29b0f896 | 7258 | { |
7fc69528 | 7259 | bool is_movx = false; |
8b65b895 | 7260 | |
29b0f896 AM |
7261 | /* If matched instruction specifies an explicit instruction mnemonic |
7262 | suffix, use it. */ | |
673fe0f0 | 7263 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 7264 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 7265 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 7266 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 7267 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 7268 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 7269 | else if (i.reg_operands |
c8f8eebc | 7270 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
255571cd | 7271 | && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG) |
29b0f896 | 7272 | { |
65fca059 | 7273 | unsigned int numop = i.operands; |
389d00a5 JB |
7274 | |
7275 | /* MOVSX/MOVZX */ | |
ddb62495 | 7276 | is_movx = (i.tm.opcode_space == SPACE_0F |
389d00a5 | 7277 | && (i.tm.base_opcode | 8) == 0xbe) |
ddb62495 | 7278 | || (i.tm.opcode_space == SPACE_BASE |
389d00a5 JB |
7279 | && i.tm.base_opcode == 0x63 |
7280 | && i.tm.cpu_flags.bitfield.cpu64); | |
7281 | ||
65fca059 JB |
7282 | /* movsx/movzx want only their source operand considered here, for the |
7283 | ambiguity checking below. The suffix will be replaced afterwards | |
7284 | to represent the destination (register). */ | |
389d00a5 | 7285 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
7286 | --i.operands; |
7287 | ||
643bb870 | 7288 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
7fc69528 | 7289 | if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
7290 | i.rex |= REX_W; |
7291 | ||
29b0f896 | 7292 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 7293 | based on GPR operands. */ |
29b0f896 AM |
7294 | if (!i.suffix) |
7295 | { | |
7296 | /* We take i.suffix from the last register operand specified, | |
7297 | Destination register type is more significant than source | |
381d071f L |
7298 | register type. crc32 in SSE4.2 prefers source register |
7299 | type. */ | |
7fc69528 | 7300 | unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands; |
20592a94 | 7301 | |
1a035124 JB |
7302 | while (op--) |
7303 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
7304 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
7305 | { | |
7306 | if (i.types[op].bitfield.class != Reg) | |
7307 | continue; | |
7308 | if (i.types[op].bitfield.byte) | |
7309 | i.suffix = BYTE_MNEM_SUFFIX; | |
7310 | else if (i.types[op].bitfield.word) | |
7311 | i.suffix = WORD_MNEM_SUFFIX; | |
7312 | else if (i.types[op].bitfield.dword) | |
7313 | i.suffix = LONG_MNEM_SUFFIX; | |
7314 | else if (i.types[op].bitfield.qword) | |
7315 | i.suffix = QWORD_MNEM_SUFFIX; | |
7316 | else | |
7317 | continue; | |
7318 | break; | |
7319 | } | |
65fca059 JB |
7320 | |
7321 | /* As an exception, movsx/movzx silently default to a byte source | |
7322 | in AT&T mode. */ | |
389d00a5 | 7323 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 7324 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
7325 | } |
7326 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
7327 | { | |
1cb0ab18 | 7328 | if (!check_byte_reg ()) |
29b0f896 AM |
7329 | return 0; |
7330 | } | |
7331 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
7332 | { | |
1cb0ab18 | 7333 | if (!check_long_reg ()) |
29b0f896 AM |
7334 | return 0; |
7335 | } | |
7336 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7337 | { | |
1cb0ab18 | 7338 | if (!check_qword_reg ()) |
29b0f896 AM |
7339 | return 0; |
7340 | } | |
7341 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7342 | { | |
1cb0ab18 | 7343 | if (!check_word_reg ()) |
29b0f896 AM |
7344 | return 0; |
7345 | } | |
3cd7f3e3 L |
7346 | else if (intel_syntax |
7347 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
7348 | /* Do nothing if the instruction is going to ignore the prefix. */ |
7349 | ; | |
7350 | else | |
7351 | abort (); | |
65fca059 JB |
7352 | |
7353 | /* Undo the movsx/movzx change done above. */ | |
7354 | i.operands = numop; | |
29b0f896 | 7355 | } |
3cd7f3e3 L |
7356 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
7357 | && !i.suffix) | |
29b0f896 | 7358 | { |
13e600d0 JB |
7359 | i.suffix = stackop_size; |
7360 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
7361 | { |
7362 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
7363 | .code16gcc directive to support 16-bit mode with | |
7364 | 32-bit address. For IRET without a suffix, generate | |
7365 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
7366 | handler. */ | |
13e600d0 JB |
7367 | if (i.tm.base_opcode == 0xcf) |
7368 | { | |
7369 | i.suffix = WORD_MNEM_SUFFIX; | |
7370 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
7371 | } | |
7372 | /* Warn about changed behavior for segment register push/pop. */ | |
7373 | else if ((i.tm.base_opcode | 1) == 0x07) | |
7374 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
76d3f746 | 7375 | insn_name (&i.tm)); |
06f74c5c | 7376 | } |
29b0f896 | 7377 | } |
c006a730 | 7378 | else if (!i.suffix |
0cfa3eb3 JB |
7379 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
7380 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
7381 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
ddb62495 | 7382 | || (i.tm.opcode_space == SPACE_0F |
389d00a5 | 7383 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ |
64e74474 | 7384 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
7385 | { |
7386 | switch (flag_code) | |
7387 | { | |
7388 | case CODE_64BIT: | |
40fb9820 | 7389 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 7390 | { |
828c2a25 JB |
7391 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
7392 | || i.tm.opcode_modifier.no_lsuf) | |
7393 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
7394 | break; |
7395 | } | |
1a0670f3 | 7396 | /* Fall through. */ |
9306ca4a | 7397 | case CODE_32BIT: |
40fb9820 | 7398 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
7399 | i.suffix = LONG_MNEM_SUFFIX; |
7400 | break; | |
7401 | case CODE_16BIT: | |
40fb9820 | 7402 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
7403 | i.suffix = WORD_MNEM_SUFFIX; |
7404 | break; | |
7405 | } | |
7406 | } | |
252b5132 | 7407 | |
c006a730 | 7408 | if (!i.suffix |
3cd7f3e3 | 7409 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
7410 | /* Also cover lret/retf/iret in 64-bit mode. */ |
7411 | || (flag_code == CODE_64BIT | |
7412 | && !i.tm.opcode_modifier.no_lsuf | |
7413 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 7414 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
7415 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
7416 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
7417 | /* Accept FLDENV et al without suffix. */ |
7418 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 7419 | { |
6c0946d0 | 7420 | unsigned int suffixes, evex = 0; |
c006a730 JB |
7421 | |
7422 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
7423 | if (!i.tm.opcode_modifier.no_wsuf) | |
7424 | suffixes |= 1 << 1; | |
7425 | if (!i.tm.opcode_modifier.no_lsuf) | |
7426 | suffixes |= 1 << 2; | |
c006a730 JB |
7427 | if (!i.tm.opcode_modifier.no_ssuf) |
7428 | suffixes |= 1 << 4; | |
7429 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
7430 | suffixes |= 1 << 5; | |
7431 | ||
6c0946d0 JB |
7432 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
7433 | also suitable for AT&T syntax mode, it was requested that this be | |
7434 | restricted to just Intel syntax. */ | |
a5748e0d JB |
7435 | if (intel_syntax && is_any_vex_encoding (&i.tm) |
7436 | && !i.broadcast.type && !i.broadcast.bytes) | |
6c0946d0 | 7437 | { |
b9915cbc | 7438 | unsigned int op; |
6c0946d0 | 7439 | |
b9915cbc | 7440 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 7441 | { |
b9915cbc JB |
7442 | if (is_evex_encoding (&i.tm) |
7443 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 7444 | { |
b9915cbc JB |
7445 | if (i.tm.operand_types[op].bitfield.ymmword) |
7446 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
7447 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7448 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
7449 | if (!i.tm.opcode_modifier.evex | |
7450 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
7451 | i.tm.opcode_modifier.evex = EVEX512; | |
7452 | } | |
6c0946d0 | 7453 | |
b9915cbc JB |
7454 | if (i.tm.operand_types[op].bitfield.xmmword |
7455 | + i.tm.operand_types[op].bitfield.ymmword | |
7456 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
7457 | continue; | |
6c0946d0 | 7458 | |
b9915cbc JB |
7459 | /* Any properly sized operand disambiguates the insn. */ |
7460 | if (i.types[op].bitfield.xmmword | |
7461 | || i.types[op].bitfield.ymmword | |
7462 | || i.types[op].bitfield.zmmword) | |
7463 | { | |
7464 | suffixes &= ~(7 << 6); | |
7465 | evex = 0; | |
7466 | break; | |
7467 | } | |
6c0946d0 | 7468 | |
b9915cbc JB |
7469 | if ((i.flags[op] & Operand_Mem) |
7470 | && i.tm.operand_types[op].bitfield.unspecified) | |
7471 | { | |
7472 | if (i.tm.operand_types[op].bitfield.xmmword) | |
7473 | suffixes |= 1 << 6; | |
7474 | if (i.tm.operand_types[op].bitfield.ymmword) | |
7475 | suffixes |= 1 << 7; | |
7476 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7477 | suffixes |= 1 << 8; | |
7478 | if (is_evex_encoding (&i.tm)) | |
7479 | evex = EVEX512; | |
6c0946d0 JB |
7480 | } |
7481 | } | |
7482 | } | |
7483 | ||
7484 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 7485 | if (suffixes & (suffixes - 1)) |
9306ca4a | 7486 | { |
873494c8 | 7487 | if (intel_syntax |
3cd7f3e3 | 7488 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 7489 | || operand_check == check_error)) |
9306ca4a | 7490 | { |
76d3f746 | 7491 | as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
7492 | return 0; |
7493 | } | |
c006a730 | 7494 | if (operand_check == check_error) |
9306ca4a | 7495 | { |
c006a730 | 7496 | as_bad (_("no instruction mnemonic suffix given and " |
76d3f746 | 7497 | "no register operands; can't size `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
7498 | return 0; |
7499 | } | |
c006a730 | 7500 | if (operand_check == check_warning) |
873494c8 JB |
7501 | as_warn (_("%s; using default for `%s'"), |
7502 | intel_syntax | |
7503 | ? _("ambiguous operand size") | |
7504 | : _("no instruction mnemonic suffix given and " | |
7505 | "no register operands"), | |
76d3f746 | 7506 | insn_name (&i.tm)); |
c006a730 JB |
7507 | |
7508 | if (i.tm.opcode_modifier.floatmf) | |
7509 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 7510 | else if (is_movx) |
65fca059 | 7511 | /* handled below */; |
6c0946d0 JB |
7512 | else if (evex) |
7513 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
7514 | else if (flag_code == CODE_16BIT) |
7515 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 7516 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 7517 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
7518 | else |
7519 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 7520 | } |
29b0f896 | 7521 | } |
252b5132 | 7522 | |
389d00a5 | 7523 | if (is_movx) |
65fca059 JB |
7524 | { |
7525 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
7526 | In AT&T syntax, if there is no suffix (warned about above), the default | |
7527 | will be byte extension. */ | |
7528 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
7529 | i.tm.base_opcode |= 1; | |
7530 | ||
7531 | /* For further processing, the suffix should represent the destination | |
7532 | (register). This is already the case when one was used with | |
7533 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
7534 | no suffix to begin with. */ | |
7535 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
7536 | { | |
7537 | if (i.types[1].bitfield.word) | |
7538 | i.suffix = WORD_MNEM_SUFFIX; | |
7539 | else if (i.types[1].bitfield.qword) | |
7540 | i.suffix = QWORD_MNEM_SUFFIX; | |
7541 | else | |
7542 | i.suffix = LONG_MNEM_SUFFIX; | |
7543 | ||
7544 | i.tm.opcode_modifier.w = 0; | |
7545 | } | |
7546 | } | |
7547 | ||
50128d0c JB |
7548 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
7549 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
7550 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
7551 | ||
d2224064 JB |
7552 | /* Change the opcode based on the operand size given by i.suffix. */ |
7553 | switch (i.suffix) | |
29b0f896 | 7554 | { |
d2224064 JB |
7555 | /* Size floating point instruction. */ |
7556 | case LONG_MNEM_SUFFIX: | |
7557 | if (i.tm.opcode_modifier.floatmf) | |
7558 | { | |
7559 | i.tm.base_opcode ^= 4; | |
7560 | break; | |
7561 | } | |
7562 | /* fall through */ | |
7563 | case WORD_MNEM_SUFFIX: | |
7564 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 7565 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 7566 | if (i.tm.opcode_modifier.w) |
29b0f896 | 7567 | { |
50128d0c | 7568 | if (i.short_form) |
29b0f896 AM |
7569 | i.tm.base_opcode |= 8; |
7570 | else | |
7571 | i.tm.base_opcode |= 1; | |
7572 | } | |
d2224064 JB |
7573 | /* fall through */ |
7574 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
7575 | /* Now select between word & dword operations via the operand |
7576 | size prefix, except for instructions that will ignore this | |
7577 | prefix anyway. */ | |
c8f8eebc | 7578 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 7579 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
7580 | && !i.tm.opcode_modifier.floatmf |
7581 | && !is_any_vex_encoding (&i.tm) | |
7582 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
7583 | || (flag_code == CODE_64BIT | |
7584 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
7585 | { |
7586 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 7587 | |
0cfa3eb3 | 7588 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 7589 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 7590 | |
29b0f896 AM |
7591 | if (!add_prefix (prefix)) |
7592 | return 0; | |
24eab124 | 7593 | } |
252b5132 | 7594 | |
29b0f896 AM |
7595 | /* Set mode64 for an operand. */ |
7596 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 7597 | && flag_code == CODE_64BIT |
d2224064 | 7598 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 7599 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 7600 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
7601 | need rex64. */ |
7602 | && ! (i.operands == 2 | |
7603 | && i.tm.base_opcode == 0x90 | |
ddb62495 | 7604 | && i.tm.opcode_space == SPACE_BASE |
75e5731b JB |
7605 | && i.types[0].bitfield.instance == Accum |
7606 | && i.types[0].bitfield.qword | |
44732014 | 7607 | && i.types[1].bitfield.instance == Accum)) |
d2224064 | 7608 | i.rex |= REX_W; |
3e73aa7c | 7609 | |
d2224064 | 7610 | break; |
8bbb3ad8 JB |
7611 | |
7612 | case 0: | |
f9a6a8f0 | 7613 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
7614 | when there are no suitable register operands. */ |
7615 | if (i.tm.opcode_modifier.w | |
7616 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
7617 | && (!i.reg_operands | |
7618 | || (i.reg_operands == 1 | |
7619 | /* ShiftCount */ | |
7620 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
7621 | /* InOutPortReg */ | |
7622 | || i.tm.operand_types[0].bitfield.instance == RegD | |
7623 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7fc69528 | 7624 | || i.tm.mnem_off == MN_crc32)))) |
8bbb3ad8 JB |
7625 | i.tm.base_opcode |= 1; |
7626 | break; | |
29b0f896 | 7627 | } |
7ecd2f8b | 7628 | |
255571cd | 7629 | if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG) |
c0a30a9f | 7630 | { |
c8f8eebc JB |
7631 | gas_assert (!i.suffix); |
7632 | gas_assert (i.reg_operands); | |
c0a30a9f | 7633 | |
c8f8eebc JB |
7634 | if (i.tm.operand_types[0].bitfield.instance == Accum |
7635 | || i.operands == 1) | |
7636 | { | |
7637 | /* The address size override prefix changes the size of the | |
7638 | first operand. */ | |
7639 | if (flag_code == CODE_64BIT | |
7640 | && i.op[0].regs->reg_type.bitfield.word) | |
7641 | { | |
7642 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
76d3f746 | 7643 | insn_name (&i.tm)); |
c8f8eebc JB |
7644 | return 0; |
7645 | } | |
7646 | ||
7647 | if ((flag_code == CODE_32BIT | |
7648 | ? i.op[0].regs->reg_type.bitfield.word | |
7649 | : i.op[0].regs->reg_type.bitfield.dword) | |
7650 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
7651 | return 0; | |
7652 | } | |
c0a30a9f L |
7653 | else |
7654 | { | |
c8f8eebc JB |
7655 | /* Check invalid register operand when the address size override |
7656 | prefix changes the size of register operands. */ | |
7657 | unsigned int op; | |
7658 | enum { need_word, need_dword, need_qword } need; | |
7659 | ||
27f13469 | 7660 | /* Check the register operand for the address size prefix if |
b3a3496f | 7661 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 7662 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
7663 | if (i.mem_operands == 1 |
7664 | && i.reg_operands == 1 | |
7665 | && i.operands == 2 | |
27f13469 | 7666 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
7667 | && (flag_code == CODE_32BIT |
7668 | ? i.op[1].regs->reg_type.bitfield.word | |
7669 | : i.op[1].regs->reg_type.bitfield.dword) | |
7670 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
7671 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
7672 | || (x86_elf_abi == X86_64_X32_ABI | |
7673 | && i.base_reg | |
b3a3496f L |
7674 | && i.base_reg->reg_num == RegIP |
7675 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
7676 | #else |
7677 | || 0) | |
7678 | #endif | |
27f13469 L |
7679 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
7680 | return 0; | |
7681 | ||
c8f8eebc JB |
7682 | if (flag_code == CODE_32BIT) |
7683 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
7684 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
7685 | need = need_dword; |
7686 | else | |
7687 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 7688 | |
c8f8eebc JB |
7689 | for (op = 0; op < i.operands; op++) |
7690 | { | |
7691 | if (i.types[op].bitfield.class != Reg) | |
7692 | continue; | |
7693 | ||
7694 | switch (need) | |
7695 | { | |
7696 | case need_word: | |
7697 | if (i.op[op].regs->reg_type.bitfield.word) | |
7698 | continue; | |
7699 | break; | |
7700 | case need_dword: | |
7701 | if (i.op[op].regs->reg_type.bitfield.dword) | |
7702 | continue; | |
7703 | break; | |
7704 | case need_qword: | |
7705 | if (i.op[op].regs->reg_type.bitfield.qword) | |
7706 | continue; | |
7707 | break; | |
7708 | } | |
7709 | ||
7710 | as_bad (_("invalid register operand size for `%s'"), | |
76d3f746 | 7711 | insn_name (&i.tm)); |
c8f8eebc JB |
7712 | return 0; |
7713 | } | |
7714 | } | |
c0a30a9f L |
7715 | } |
7716 | ||
29b0f896 AM |
7717 | return 1; |
7718 | } | |
3e73aa7c | 7719 | |
29b0f896 | 7720 | static int |
543613e9 | 7721 | check_byte_reg (void) |
29b0f896 AM |
7722 | { |
7723 | int op; | |
543613e9 | 7724 | |
29b0f896 AM |
7725 | for (op = i.operands; --op >= 0;) |
7726 | { | |
dc821c5f | 7727 | /* Skip non-register operands. */ |
bab6aec1 | 7728 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
7729 | continue; |
7730 | ||
29b0f896 AM |
7731 | /* If this is an eight bit register, it's OK. If it's the 16 or |
7732 | 32 bit version of an eight bit register, we will just use the | |
7733 | low portion, and that's OK too. */ | |
dc821c5f | 7734 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
7735 | continue; |
7736 | ||
5a819eb9 | 7737 | /* I/O port address operands are OK too. */ |
75e5731b JB |
7738 | if (i.tm.operand_types[op].bitfield.instance == RegD |
7739 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
7740 | continue; |
7741 | ||
9706160a | 7742 | /* crc32 only wants its source operand checked here. */ |
7fc69528 | 7743 | if (i.tm.mnem_off == MN_crc32 && op != 0) |
9344ff29 L |
7744 | continue; |
7745 | ||
29b0f896 | 7746 | /* Any other register is bad. */ |
73c76375 JB |
7747 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7748 | register_prefix, i.op[op].regs->reg_name, | |
76d3f746 | 7749 | insn_name (&i.tm), i.suffix); |
73c76375 | 7750 | return 0; |
29b0f896 AM |
7751 | } |
7752 | return 1; | |
7753 | } | |
7754 | ||
7755 | static int | |
e3bb37b5 | 7756 | check_long_reg (void) |
29b0f896 AM |
7757 | { |
7758 | int op; | |
7759 | ||
7760 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7761 | /* Skip non-register operands. */ |
bab6aec1 | 7762 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7763 | continue; |
29b0f896 AM |
7764 | /* Reject eight bit registers, except where the template requires |
7765 | them. (eg. movzb) */ | |
dc821c5f | 7766 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7767 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7768 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7769 | && (i.tm.operand_types[op].bitfield.word |
7770 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7771 | { |
a540244d L |
7772 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7773 | register_prefix, | |
29b0f896 | 7774 | i.op[op].regs->reg_name, |
76d3f746 | 7775 | insn_name (&i.tm), |
29b0f896 AM |
7776 | i.suffix); |
7777 | return 0; | |
7778 | } | |
be4c5e58 L |
7779 | /* Error if the e prefix on a general reg is missing. */ |
7780 | else if (i.types[op].bitfield.word | |
bab6aec1 | 7781 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7782 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7783 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 7784 | { |
be4c5e58 L |
7785 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7786 | register_prefix, i.op[op].regs->reg_name, | |
7787 | i.suffix); | |
7788 | return 0; | |
252b5132 | 7789 | } |
e4630f71 | 7790 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 7791 | else if (i.types[op].bitfield.qword |
bab6aec1 | 7792 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7793 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7794 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 7795 | { |
1cb0ab18 JB |
7796 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7797 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
7798 | return 0; | |
29b0f896 AM |
7799 | } |
7800 | return 1; | |
7801 | } | |
252b5132 | 7802 | |
29b0f896 | 7803 | static int |
e3bb37b5 | 7804 | check_qword_reg (void) |
29b0f896 AM |
7805 | { |
7806 | int op; | |
252b5132 | 7807 | |
29b0f896 | 7808 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 7809 | /* Skip non-register operands. */ |
bab6aec1 | 7810 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7811 | continue; |
29b0f896 AM |
7812 | /* Reject eight bit registers, except where the template requires |
7813 | them. (eg. movzb) */ | |
dc821c5f | 7814 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7815 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7816 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7817 | && (i.tm.operand_types[op].bitfield.word |
7818 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7819 | { |
a540244d L |
7820 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7821 | register_prefix, | |
29b0f896 | 7822 | i.op[op].regs->reg_name, |
76d3f746 | 7823 | insn_name (&i.tm), |
29b0f896 AM |
7824 | i.suffix); |
7825 | return 0; | |
7826 | } | |
e4630f71 | 7827 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
7828 | else if ((i.types[op].bitfield.word |
7829 | || i.types[op].bitfield.dword) | |
bab6aec1 | 7830 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7831 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7832 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
7833 | { |
7834 | /* Prohibit these changes in the 64bit mode, since the | |
7835 | lowering is more complicated. */ | |
1cb0ab18 JB |
7836 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7837 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
7838 | return 0; | |
252b5132 | 7839 | } |
29b0f896 AM |
7840 | return 1; |
7841 | } | |
252b5132 | 7842 | |
29b0f896 | 7843 | static int |
e3bb37b5 | 7844 | check_word_reg (void) |
29b0f896 AM |
7845 | { |
7846 | int op; | |
7847 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7848 | /* Skip non-register operands. */ |
bab6aec1 | 7849 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7850 | continue; |
29b0f896 AM |
7851 | /* Reject eight bit registers, except where the template requires |
7852 | them. (eg. movzb) */ | |
dc821c5f | 7853 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7854 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7855 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7856 | && (i.tm.operand_types[op].bitfield.word |
7857 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7858 | { |
a540244d L |
7859 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7860 | register_prefix, | |
29b0f896 | 7861 | i.op[op].regs->reg_name, |
76d3f746 | 7862 | insn_name (&i.tm), |
29b0f896 AM |
7863 | i.suffix); |
7864 | return 0; | |
7865 | } | |
9706160a JB |
7866 | /* Error if the e or r prefix on a general reg is present. */ |
7867 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 7868 | || i.types[op].bitfield.qword) |
bab6aec1 | 7869 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7870 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7871 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 7872 | { |
9706160a JB |
7873 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7874 | register_prefix, i.op[op].regs->reg_name, | |
7875 | i.suffix); | |
7876 | return 0; | |
29b0f896 AM |
7877 | } |
7878 | return 1; | |
7879 | } | |
252b5132 | 7880 | |
29b0f896 | 7881 | static int |
40fb9820 | 7882 | update_imm (unsigned int j) |
29b0f896 | 7883 | { |
bc0844ae | 7884 | i386_operand_type overlap = i.types[j]; |
c34d1cc9 JB |
7885 | |
7886 | if (i.tm.operand_types[j].bitfield.imm8 | |
7887 | && i.tm.operand_types[j].bitfield.imm8s | |
7888 | && overlap.bitfield.imm8 && overlap.bitfield.imm8s) | |
7889 | { | |
7890 | /* This combination is used on 8-bit immediates where e.g. $~0 is | |
7891 | desirable to permit. We're past operand type matching, so simply | |
7892 | put things back in the shape they were before introducing the | |
7893 | distinction between Imm8, Imm8S, and Imm8|Imm8S. */ | |
7894 | overlap.bitfield.imm8s = 0; | |
7895 | } | |
7896 | ||
be1643ff JB |
7897 | if (overlap.bitfield.imm8 |
7898 | + overlap.bitfield.imm8s | |
7899 | + overlap.bitfield.imm16 | |
7900 | + overlap.bitfield.imm32 | |
7901 | + overlap.bitfield.imm32s | |
7902 | + overlap.bitfield.imm64 > 1) | |
29b0f896 | 7903 | { |
05909f23 JB |
7904 | static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } }; |
7905 | static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } }; | |
7906 | static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } }; | |
7907 | static const i386_operand_type imm16_32 = { .bitfield = | |
7908 | { .imm16 = 1, .imm32 = 1 } | |
7909 | }; | |
7910 | static const i386_operand_type imm16_32s = { .bitfield = | |
7911 | { .imm16 = 1, .imm32s = 1 } | |
7912 | }; | |
7913 | static const i386_operand_type imm16_32_32s = { .bitfield = | |
7914 | { .imm16 = 1, .imm32 = 1, .imm32s = 1 } | |
7915 | }; | |
7916 | ||
29b0f896 AM |
7917 | if (i.suffix) |
7918 | { | |
40fb9820 L |
7919 | i386_operand_type temp; |
7920 | ||
0dfbf9d7 | 7921 | operand_type_set (&temp, 0); |
7ab9ffdd | 7922 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
7923 | { |
7924 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
7925 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
7926 | } | |
7927 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7928 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
7929 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7930 | { | |
7931 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
7932 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
7933 | } | |
7934 | else | |
7935 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
7936 | overlap = temp; | |
29b0f896 | 7937 | } |
0dfbf9d7 L |
7938 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
7939 | || operand_type_equal (&overlap, &imm16_32) | |
7940 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 7941 | { |
40fb9820 | 7942 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 7943 | overlap = imm16; |
40fb9820 | 7944 | else |
65da13b5 | 7945 | overlap = imm32s; |
29b0f896 | 7946 | } |
8bbb3ad8 JB |
7947 | else if (i.prefix[REX_PREFIX] & REX_W) |
7948 | overlap = operand_type_and (overlap, imm32s); | |
7949 | else if (i.prefix[DATA_PREFIX]) | |
7950 | overlap = operand_type_and (overlap, | |
7951 | flag_code != CODE_16BIT ? imm16 : imm32); | |
be1643ff JB |
7952 | if (overlap.bitfield.imm8 |
7953 | + overlap.bitfield.imm8s | |
7954 | + overlap.bitfield.imm16 | |
7955 | + overlap.bitfield.imm32 | |
7956 | + overlap.bitfield.imm32s | |
7957 | + overlap.bitfield.imm64 != 1) | |
29b0f896 | 7958 | { |
4eed87de AM |
7959 | as_bad (_("no instruction mnemonic suffix given; " |
7960 | "can't determine immediate size")); | |
29b0f896 AM |
7961 | return 0; |
7962 | } | |
7963 | } | |
40fb9820 | 7964 | i.types[j] = overlap; |
29b0f896 | 7965 | |
40fb9820 L |
7966 | return 1; |
7967 | } | |
7968 | ||
7969 | static int | |
7970 | finalize_imm (void) | |
7971 | { | |
bc0844ae | 7972 | unsigned int j, n; |
29b0f896 | 7973 | |
bc0844ae L |
7974 | /* Update the first 2 immediate operands. */ |
7975 | n = i.operands > 2 ? 2 : i.operands; | |
7976 | if (n) | |
7977 | { | |
7978 | for (j = 0; j < n; j++) | |
7979 | if (update_imm (j) == 0) | |
7980 | return 0; | |
40fb9820 | 7981 | |
bc0844ae L |
7982 | /* The 3rd operand can't be immediate operand. */ |
7983 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7984 | } | |
29b0f896 AM |
7985 | |
7986 | return 1; | |
7987 | } | |
7988 | ||
7989 | static int | |
e3bb37b5 | 7990 | process_operands (void) |
29b0f896 AM |
7991 | { |
7992 | /* Default segment register this instruction will use for memory | |
7993 | accesses. 0 means unknown. This is only for optimizing out | |
7994 | unnecessary segment overrides. */ | |
5e042380 | 7995 | const reg_entry *default_seg = NULL; |
29b0f896 | 7996 | |
31b4cda3 JB |
7997 | /* We only need to check those implicit registers for instructions |
7998 | with 3 operands or less. */ | |
7999 | if (i.operands <= 3) | |
8000 | for (unsigned int j = 0; j < i.operands; j++) | |
8001 | if (i.types[j].bitfield.instance != InstanceNone) | |
8002 | i.reg_operands--; | |
8003 | ||
a5aeccd9 JB |
8004 | if (i.tm.opcode_modifier.sse2avx) |
8005 | { | |
8006 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
8007 | need converting. */ | |
8008 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
8009 | i.prefix[REX_PREFIX] = 0; | |
8010 | i.rex_encoding = 0; | |
8011 | } | |
c423d21a JB |
8012 | /* ImmExt should be processed after SSE2AVX. */ |
8013 | else if (i.tm.opcode_modifier.immext) | |
8014 | process_immext (); | |
a5aeccd9 | 8015 | |
2426c15f | 8016 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 8017 | { |
05909f23 JB |
8018 | static const i386_operand_type regxmm = { |
8019 | .bitfield = { .class = RegSIMD, .xmmword = 1 } | |
8020 | }; | |
91d6fa6a NC |
8021 | unsigned int dupl = i.operands; |
8022 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
8023 | unsigned int j; |
8024 | ||
c0f3af97 | 8025 | /* The destination must be an xmm register. */ |
9c2799c2 | 8026 | gas_assert (i.reg_operands |
91d6fa6a | 8027 | && MAX_OPERANDS > dupl |
7ab9ffdd | 8028 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 8029 | |
75e5731b | 8030 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 8031 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 8032 | { |
95dfdd85 JB |
8033 | /* Keep xmm0 for instructions with VEX prefix and 3 |
8034 | sources. */ | |
8035 | i.tm.operand_types[0].bitfield.instance = InstanceNone; | |
8036 | i.tm.operand_types[0].bitfield.class = RegSIMD; | |
31b4cda3 | 8037 | i.reg_operands++; |
95dfdd85 | 8038 | goto duplicate; |
c0f3af97 | 8039 | } |
95dfdd85 JB |
8040 | |
8041 | if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) | |
7ab9ffdd | 8042 | { |
aa180741 | 8043 | gas_assert ((MAX_OPERANDS - 1) > dupl); |
c0f3af97 L |
8044 | |
8045 | /* Add the implicit xmm0 for instructions with VEX prefix | |
8046 | and 3 sources. */ | |
8047 | for (j = i.operands; j > 0; j--) | |
8048 | { | |
8049 | i.op[j] = i.op[j - 1]; | |
8050 | i.types[j] = i.types[j - 1]; | |
8051 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 8052 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
8053 | } |
8054 | i.op[0].regs | |
629310ab | 8055 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 8056 | i.types[0] = regxmm; |
c0f3af97 L |
8057 | i.tm.operand_types[0] = regxmm; |
8058 | ||
8059 | i.operands += 2; | |
8060 | i.reg_operands += 2; | |
8061 | i.tm.operands += 2; | |
8062 | ||
91d6fa6a | 8063 | dupl++; |
c0f3af97 | 8064 | dest++; |
91d6fa6a NC |
8065 | i.op[dupl] = i.op[dest]; |
8066 | i.types[dupl] = i.types[dest]; | |
8067 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 8068 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 8069 | } |
c0f3af97 L |
8070 | else |
8071 | { | |
dc1e8a47 | 8072 | duplicate: |
c0f3af97 L |
8073 | i.operands++; |
8074 | i.reg_operands++; | |
8075 | i.tm.operands++; | |
8076 | ||
91d6fa6a NC |
8077 | i.op[dupl] = i.op[dest]; |
8078 | i.types[dupl] = i.types[dest]; | |
8079 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 8080 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
8081 | } |
8082 | ||
8083 | if (i.tm.opcode_modifier.immext) | |
8084 | process_immext (); | |
8085 | } | |
75e5731b | 8086 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
bd782808 | 8087 | && i.tm.opcode_modifier.modrm) |
c0f3af97 L |
8088 | { |
8089 | unsigned int j; | |
8090 | ||
9fcfb3d7 L |
8091 | for (j = 1; j < i.operands; j++) |
8092 | { | |
8093 | i.op[j - 1] = i.op[j]; | |
8094 | i.types[j - 1] = i.types[j]; | |
8095 | ||
8096 | /* We need to adjust fields in i.tm since they are used by | |
8097 | build_modrm_byte. */ | |
8098 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
8099 | |
8100 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
8101 | } |
8102 | ||
31b4cda3 JB |
8103 | /* No adjustment to i.reg_operands: This was already done at the top |
8104 | of the function. */ | |
e2ec9d29 | 8105 | i.operands--; |
e2ec9d29 L |
8106 | i.tm.operands--; |
8107 | } | |
255571cd | 8108 | else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP) |
920d2ddc | 8109 | { |
a477a8c4 JB |
8110 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
8111 | ||
920d2ddc | 8112 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 8113 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
8114 | regnum = register_number (i.op[1].regs); |
8115 | first_reg_in_group = regnum & ~3; | |
8116 | last_reg_in_group = first_reg_in_group + 3; | |
8117 | if (regnum != first_reg_in_group) | |
8118 | as_warn (_("source register `%s%s' implicitly denotes" | |
8119 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
8120 | register_prefix, i.op[1].regs->reg_name, | |
8121 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
8122 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
76d3f746 | 8123 | insn_name (&i.tm)); |
a477a8c4 | 8124 | } |
255571cd | 8125 | else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE) |
e2ec9d29 L |
8126 | { |
8127 | /* The imul $imm, %reg instruction is converted into | |
8128 | imul $imm, %reg, %reg, and the clr %reg instruction | |
8129 | is converted into xor %reg, %reg. */ | |
8130 | ||
8131 | unsigned int first_reg_op; | |
8132 | ||
8133 | if (operand_type_check (i.types[0], reg)) | |
8134 | first_reg_op = 0; | |
8135 | else | |
8136 | first_reg_op = 1; | |
8137 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 8138 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 8139 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
8140 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
8141 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
8142 | i.operands++; | |
8143 | i.reg_operands++; | |
29b0f896 AM |
8144 | } |
8145 | ||
85b80b0f | 8146 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
8147 | { |
8148 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
8149 | must be put into the modrm byte). Now, we make the modrm and |
8150 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
8151 | |
8152 | default_seg = build_modrm_byte (); | |
bd782808 JB |
8153 | |
8154 | if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) | |
8155 | { | |
8156 | /* Warn about some common errors, but press on regardless. */ | |
8157 | if (i.operands == 2) | |
8158 | { | |
8159 | /* Reversed arguments on faddp or fmulp. */ | |
8160 | as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm), | |
8161 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
8162 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
8163 | } | |
8164 | else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
8165 | { | |
8166 | /* Extraneous `l' suffix on fp insn. */ | |
8167 | as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm), | |
8168 | register_prefix, i.op[0].regs->reg_name); | |
8169 | } | |
8170 | } | |
29b0f896 | 8171 | } |
00cee14f | 8172 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
8173 | { |
8174 | if (flag_code != CODE_64BIT | |
8175 | ? i.tm.base_opcode == POP_SEG_SHORT | |
8176 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 8177 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
8178 | && i.op[0].regs->reg_num < 4) |
8179 | { | |
8180 | as_bad (_("you can't `%s %s%s'"), | |
76d3f746 | 8181 | insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name); |
85b80b0f JB |
8182 | return 0; |
8183 | } | |
389d00a5 | 8184 | if (i.op[0].regs->reg_num > 3 |
ddb62495 | 8185 | && i.tm.opcode_space == SPACE_BASE ) |
85b80b0f | 8186 | { |
389d00a5 | 8187 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
ddb62495 | 8188 | i.tm.opcode_space = SPACE_0F; |
85b80b0f JB |
8189 | } |
8190 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
8191 | } | |
ddb62495 | 8192 | else if (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 8193 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) |
29b0f896 | 8194 | { |
5e042380 | 8195 | default_seg = reg_ds; |
29b0f896 | 8196 | } |
40fb9820 | 8197 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
8198 | { |
8199 | /* For the string instructions that allow a segment override | |
8200 | on one of their operands, the default segment is ds. */ | |
5e042380 | 8201 | default_seg = reg_ds; |
29b0f896 | 8202 | } |
50128d0c | 8203 | else if (i.short_form) |
85b80b0f | 8204 | { |
bd782808 | 8205 | /* The register operand is in operand 0 or 1. */ |
4943d587 | 8206 | const reg_entry *r = i.op[0].regs; |
85b80b0f | 8207 | |
4943d587 JB |
8208 | if (i.imm_operands |
8209 | || (r->reg_type.bitfield.instance == Accum && i.op[1].regs)) | |
8210 | r = i.op[1].regs; | |
85b80b0f | 8211 | /* Register goes in low 3 bits of opcode. */ |
4943d587 JB |
8212 | i.tm.base_opcode |= r->reg_num; |
8213 | if ((r->reg_flags & RegRex) != 0) | |
85b80b0f | 8214 | i.rex |= REX_B; |
85b80b0f | 8215 | } |
29b0f896 | 8216 | |
514a8bb0 | 8217 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
7fc69528 | 8218 | && i.tm.mnem_off == MN_lea) |
92334ad2 JB |
8219 | { |
8220 | if (!quiet_warnings) | |
76d3f746 | 8221 | as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm)); |
739d7649 | 8222 | if (optimize && !i.no_optimize) |
92334ad2 JB |
8223 | { |
8224 | i.seg[0] = NULL; | |
8225 | i.prefix[SEG_PREFIX] = 0; | |
8226 | } | |
8227 | } | |
52271982 AM |
8228 | |
8229 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
8230 | is neither the default nor the one already recorded from a prefix, |
8231 | use an opcode prefix to select it. If we never figured out what | |
8232 | the default segment is, then default_seg will be zero at this | |
8233 | point, and the specified segment prefix will always be used. */ | |
8234 | if (i.seg[0] | |
8235 | && i.seg[0] != default_seg | |
5e042380 | 8236 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 8237 | { |
5e042380 | 8238 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
8239 | return 0; |
8240 | } | |
8241 | return 1; | |
8242 | } | |
8243 | ||
a5aeccd9 | 8244 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
5b7c81bd | 8245 | bool do_sse2avx) |
a5aeccd9 JB |
8246 | { |
8247 | if (r->reg_flags & RegRex) | |
8248 | { | |
8249 | if (i.rex & rex_bit) | |
8250 | as_bad (_("same type of prefix used twice")); | |
8251 | i.rex |= rex_bit; | |
8252 | } | |
8253 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
8254 | { | |
8255 | gas_assert (i.vex.register_specifier == r); | |
8256 | i.vex.register_specifier += 8; | |
8257 | } | |
8258 | ||
8259 | if (r->reg_flags & RegVRex) | |
8260 | i.vrex |= rex_bit; | |
8261 | } | |
8262 | ||
5e042380 | 8263 | static const reg_entry * |
e3bb37b5 | 8264 | build_modrm_byte (void) |
29b0f896 | 8265 | { |
5e042380 | 8266 | const reg_entry *default_seg = NULL; |
c0f3af97 | 8267 | unsigned int source, dest; |
aa180741 | 8268 | bool vex_3_sources = (i.reg_operands + i.mem_operands == 4); |
c0f3af97 | 8269 | |
c0f3af97 L |
8270 | if (vex_3_sources) |
8271 | { | |
91d6fa6a | 8272 | unsigned int nds, reg_slot; |
4c2c6516 | 8273 | expressionS *exp; |
c0f3af97 | 8274 | |
6b8d3588 | 8275 | dest = i.operands - 1; |
c0f3af97 | 8276 | nds = dest - 1; |
922d8de8 | 8277 | |
a683cc34 | 8278 | /* There are 2 kinds of instructions: |
bed3d976 | 8279 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 8280 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 8281 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 8282 | ZMM register. |
bed3d976 | 8283 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 8284 | plus 1 memory operand, with VexXDS. */ |
aa180741 | 8285 | gas_assert (i.tm.opcode_modifier.vexvvvv == VEXXDS |
dcd7e323 | 8286 | && i.tm.opcode_modifier.vexw |
3528c362 | 8287 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 8288 | |
48db9223 JB |
8289 | /* If VexW1 is set, the first non-immediate operand is the source and |
8290 | the second non-immediate one is encoded in the immediate operand. */ | |
8291 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
8292 | { | |
8293 | source = i.imm_operands; | |
8294 | reg_slot = i.imm_operands + 1; | |
8295 | } | |
8296 | else | |
8297 | { | |
8298 | source = i.imm_operands + 1; | |
8299 | reg_slot = i.imm_operands; | |
8300 | } | |
8301 | ||
a683cc34 | 8302 | if (i.imm_operands == 0) |
bed3d976 JB |
8303 | { |
8304 | /* When there is no immediate operand, generate an 8bit | |
8305 | immediate operand to encode the first operand. */ | |
8306 | exp = &im_expressions[i.imm_operands++]; | |
8307 | i.op[i.operands].imms = exp; | |
be1643ff | 8308 | i.types[i.operands].bitfield.imm8 = 1; |
bed3d976 JB |
8309 | i.operands++; |
8310 | ||
3528c362 | 8311 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
8312 | exp->X_op = O_constant; |
8313 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
8314 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
8315 | } | |
922d8de8 | 8316 | else |
bed3d976 | 8317 | { |
9d3bf266 JB |
8318 | gas_assert (i.imm_operands == 1); |
8319 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
8320 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 8321 | |
9d3bf266 JB |
8322 | /* Turn on Imm8 again so that output_imm will generate it. */ |
8323 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 8324 | |
3528c362 | 8325 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 8326 | i.op[0].imms->X_add_number |
bed3d976 | 8327 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 8328 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 8329 | } |
a683cc34 | 8330 | |
3528c362 | 8331 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 8332 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
8333 | } |
8334 | else | |
8335 | source = dest = 0; | |
29b0f896 AM |
8336 | |
8337 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
8338 | implicit registers do not count. If there are 3 register |
8339 | operands, it must be a instruction with VexNDS. For a | |
8340 | instruction with VexNDD, the destination register is encoded | |
8341 | in VEX prefix. If there are 4 register operands, it must be | |
8342 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
8343 | if (i.mem_operands == 0 |
8344 | && ((i.reg_operands == 2 | |
2426c15f | 8345 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 8346 | || (i.reg_operands == 3 |
2426c15f | 8347 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 8348 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 8349 | { |
cab737b9 L |
8350 | switch (i.operands) |
8351 | { | |
8352 | case 2: | |
8353 | source = 0; | |
8354 | break; | |
8355 | case 3: | |
c81128dc L |
8356 | /* When there are 3 operands, one of them may be immediate, |
8357 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
8358 | the first operand must be shift count register (cl) or it |
8359 | is an instruction with VexNDS. */ | |
9c2799c2 | 8360 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 8361 | || (i.imm_operands == 0 |
2426c15f | 8362 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
8363 | || (i.types[0].bitfield.instance == RegC |
8364 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 8365 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
8366 | || (i.types[0].bitfield.instance == RegC |
8367 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
8368 | source = 1; |
8369 | else | |
8370 | source = 0; | |
cab737b9 L |
8371 | break; |
8372 | case 4: | |
368d64cc L |
8373 | /* When there are 4 operands, the first two must be 8bit |
8374 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
8375 | one. |
8376 | ||
8377 | For instructions with VexNDS, if the first operand | |
8378 | an imm8, the source operand is the 2nd one. If the last | |
8379 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 8380 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
8381 | && i.types[0].bitfield.imm8 |
8382 | && i.types[1].bitfield.imm8) | |
2426c15f | 8383 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
8384 | && i.imm_operands == 1 |
8385 | && (i.types[0].bitfield.imm8 | |
c34d1cc9 | 8386 | || i.types[0].bitfield.imm8s |
cf665fee | 8387 | || i.types[i.operands - 1].bitfield.imm8))); |
9f2670f2 L |
8388 | if (i.imm_operands == 2) |
8389 | source = 2; | |
8390 | else | |
c0f3af97 L |
8391 | { |
8392 | if (i.types[0].bitfield.imm8) | |
8393 | source = 1; | |
8394 | else | |
8395 | source = 0; | |
8396 | } | |
c0f3af97 L |
8397 | break; |
8398 | case 5: | |
cf665fee JB |
8399 | gas_assert (!is_evex_encoding (&i.tm)); |
8400 | gas_assert (i.imm_operands == 1 && vex_3_sources); | |
cab737b9 L |
8401 | break; |
8402 | default: | |
8403 | abort (); | |
8404 | } | |
8405 | ||
c0f3af97 L |
8406 | if (!vex_3_sources) |
8407 | { | |
8408 | dest = source + 1; | |
8409 | ||
2426c15f | 8410 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 8411 | { |
43234a1e | 8412 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 8413 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 8414 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
8415 | |
8416 | i386_operand_type op; | |
8417 | unsigned int vvvv; | |
8418 | ||
c2ecccb3 | 8419 | /* Swap two source operands if needed. */ |
255571cd | 8420 | if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES) |
f12dc422 L |
8421 | { |
8422 | vvvv = source; | |
8423 | source = dest; | |
8424 | } | |
8425 | else | |
8426 | vvvv = dest; | |
8427 | ||
8428 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 8429 | if ((dest + 1) >= i.operands |
bab6aec1 | 8430 | || ((op.bitfield.class != Reg |
dc821c5f | 8431 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 8432 | && op.bitfield.class != RegSIMD |
c0f327b8 | 8433 | && op.bitfield.class != RegMask)) |
c0f3af97 | 8434 | abort (); |
f12dc422 | 8435 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
8436 | dest++; |
8437 | } | |
8438 | } | |
29b0f896 AM |
8439 | |
8440 | i.rm.mode = 3; | |
dfd69174 JB |
8441 | /* One of the register operands will be encoded in the i.rm.reg |
8442 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
8443 | fields. If no form of this instruction supports a memory |
8444 | destination operand, then we assume the source operand may | |
8445 | sometimes be a memory operand and so we need to store the | |
8446 | destination in the i.rm.reg field. */ | |
dfd69174 | 8447 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 8448 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
8449 | { |
8450 | i.rm.reg = i.op[dest].regs->reg_num; | |
8451 | i.rm.regmem = i.op[source].regs->reg_num; | |
a5aeccd9 | 8452 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8453 | set_rex_vrex (i.op[source].regs, REX_B, false); |
29b0f896 AM |
8454 | } |
8455 | else | |
8456 | { | |
8457 | i.rm.reg = i.op[source].regs->reg_num; | |
8458 | i.rm.regmem = i.op[dest].regs->reg_num; | |
a5aeccd9 | 8459 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8460 | set_rex_vrex (i.op[source].regs, REX_R, false); |
29b0f896 | 8461 | } |
e0c7f900 | 8462 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 8463 | { |
4a5c67ed | 8464 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 8465 | abort (); |
e0c7f900 | 8466 | i.rex &= ~REX_R; |
c4a530c5 JB |
8467 | add_prefix (LOCK_PREFIX_OPCODE); |
8468 | } | |
29b0f896 AM |
8469 | } |
8470 | else | |
8471 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
8472 | unsigned int mem; |
8473 | ||
29b0f896 AM |
8474 | if (i.mem_operands) |
8475 | { | |
8476 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 8477 | unsigned int op; |
4eed87de | 8478 | |
7ab9ffdd | 8479 | for (op = 0; op < i.operands; op++) |
8dc0818e | 8480 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 8481 | break; |
7ab9ffdd | 8482 | gas_assert (op < i.operands); |
29b0f896 | 8483 | |
63112cd6 | 8484 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 8485 | { |
260cd341 LC |
8486 | /* The index register of VSIB shouldn't be RegIZ. */ |
8487 | if (i.tm.opcode_modifier.sib != SIBMEM | |
8488 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
8489 | abort (); |
8490 | ||
8491 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8492 | if (!i.base_reg) | |
8493 | { | |
8494 | i.sib.base = NO_BASE_REGISTER; | |
8495 | i.sib.scale = i.log2_scale_factor; | |
2f2be86b | 8496 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 8497 | i.types[op].bitfield.disp32 = 1; |
6c30d220 | 8498 | } |
260cd341 LC |
8499 | |
8500 | /* Since the mandatory SIB always has index register, so | |
8501 | the code logic remains unchanged. The non-mandatory SIB | |
8502 | without index register is allowed and will be handled | |
8503 | later. */ | |
8504 | if (i.index_reg) | |
8505 | { | |
8506 | if (i.index_reg->reg_num == RegIZ) | |
8507 | i.sib.index = NO_INDEX_REGISTER; | |
8508 | else | |
8509 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 8510 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 8511 | } |
6c30d220 L |
8512 | } |
8513 | ||
5e042380 | 8514 | default_seg = reg_ds; |
29b0f896 AM |
8515 | |
8516 | if (i.base_reg == 0) | |
8517 | { | |
8518 | i.rm.mode = 0; | |
8519 | if (!i.disp_operands) | |
9bb129e8 | 8520 | fake_zero_displacement = 1; |
29b0f896 AM |
8521 | if (i.index_reg == 0) |
8522 | { | |
260cd341 LC |
8523 | /* Both check for VSIB and mandatory non-vector SIB. */ |
8524 | gas_assert (!i.tm.opcode_modifier.sib | |
8525 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 8526 | /* Operand is just <disp> */ |
2f2be86b | 8527 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
20f0a1fc | 8528 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
8529 | { |
8530 | /* 64bit mode overwrites the 32bit absolute | |
8531 | addressing by RIP relative addressing and | |
8532 | absolute addressing is encoded by one of the | |
8533 | redundant SIB forms. */ | |
8534 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8535 | i.sib.base = NO_BASE_REGISTER; | |
8536 | i.sib.index = NO_INDEX_REGISTER; | |
a775efc8 | 8537 | i.types[op].bitfield.disp32 = 1; |
20f0a1fc | 8538 | } |
fc225355 L |
8539 | else if ((flag_code == CODE_16BIT) |
8540 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
8541 | { |
8542 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2f2be86b | 8543 | i.types[op].bitfield.disp16 = 1; |
20f0a1fc NC |
8544 | } |
8545 | else | |
8546 | { | |
8547 | i.rm.regmem = NO_BASE_REGISTER; | |
2f2be86b | 8548 | i.types[op].bitfield.disp32 = 1; |
29b0f896 AM |
8549 | } |
8550 | } | |
63112cd6 | 8551 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8552 | { |
6c30d220 | 8553 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 8554 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8555 | i.sib.index = NO_INDEX_REGISTER; |
8556 | else | |
8557 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8558 | i.sib.base = NO_BASE_REGISTER; |
8559 | i.sib.scale = i.log2_scale_factor; | |
8560 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2f2be86b | 8561 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 8562 | i.types[op].bitfield.disp32 = 1; |
29b0f896 | 8563 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8564 | i.rex |= REX_X; |
29b0f896 AM |
8565 | } |
8566 | } | |
8567 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 8568 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 8569 | { |
63112cd6 | 8570 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 8571 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
8572 | i.types[op].bitfield.disp8 = 0; |
8573 | i.types[op].bitfield.disp16 = 0; | |
a775efc8 | 8574 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 8575 | i.types[op].bitfield.disp64 = 0; |
71903a11 | 8576 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
8577 | if (! i.disp_operands) |
8578 | fake_zero_displacement = 1; | |
29b0f896 | 8579 | } |
dc821c5f | 8580 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 8581 | { |
63112cd6 | 8582 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
8583 | switch (i.base_reg->reg_num) |
8584 | { | |
8585 | case 3: /* (%bx) */ | |
8586 | if (i.index_reg == 0) | |
8587 | i.rm.regmem = 7; | |
8588 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
8589 | i.rm.regmem = i.index_reg->reg_num - 6; | |
8590 | break; | |
8591 | case 5: /* (%bp) */ | |
5e042380 | 8592 | default_seg = reg_ss; |
29b0f896 AM |
8593 | if (i.index_reg == 0) |
8594 | { | |
8595 | i.rm.regmem = 6; | |
40fb9820 | 8596 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
8597 | { |
8598 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 8599 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
8600 | i.types[op].bitfield.disp16 = 1; |
8601 | else | |
8602 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 8603 | fake_zero_displacement = 1; |
29b0f896 AM |
8604 | } |
8605 | } | |
8606 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
8607 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
8608 | break; | |
8609 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
8610 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
8611 | } | |
41eb8e88 L |
8612 | if (!fake_zero_displacement |
8613 | && !i.disp_operands | |
8614 | && i.disp_encoding) | |
8615 | { | |
8616 | fake_zero_displacement = 1; | |
8617 | if (i.disp_encoding == disp_encoding_8bit) | |
8618 | i.types[op].bitfield.disp8 = 1; | |
8619 | else | |
8620 | i.types[op].bitfield.disp16 = 1; | |
8621 | } | |
29b0f896 AM |
8622 | i.rm.mode = mode_from_disp_size (i.types[op]); |
8623 | } | |
8624 | else /* i.base_reg and 32/64 bit mode */ | |
8625 | { | |
a9aabc23 | 8626 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 8627 | { |
73053c1f JB |
8628 | i.types[op].bitfield.disp16 = 0; |
8629 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 8630 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 8631 | } |
20f0a1fc | 8632 | |
63112cd6 | 8633 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 8634 | i.rm.regmem = i.base_reg->reg_num; |
29b0f896 | 8635 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8636 | i.rex |= REX_B; |
29b0f896 AM |
8637 | i.sib.base = i.base_reg->reg_num; |
8638 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
8639 | complications. */ | |
848930b2 JB |
8640 | if (!(i.base_reg->reg_flags & RegRex) |
8641 | && (i.base_reg->reg_num == EBP_REG_NUM | |
8642 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 8643 | default_seg = reg_ss; |
848930b2 | 8644 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 8645 | { |
848930b2 | 8646 | fake_zero_displacement = 1; |
1a02d6b0 L |
8647 | if (i.disp_encoding == disp_encoding_32bit) |
8648 | i.types[op].bitfield.disp32 = 1; | |
8649 | else | |
8650 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
8651 | } |
8652 | i.sib.scale = i.log2_scale_factor; | |
8653 | if (i.index_reg == 0) | |
8654 | { | |
260cd341 LC |
8655 | /* Only check for VSIB. */ |
8656 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
8657 | && i.tm.opcode_modifier.sib != VECSIB256 | |
8658 | && i.tm.opcode_modifier.sib != VECSIB512); | |
8659 | ||
29b0f896 AM |
8660 | /* <disp>(%esp) becomes two byte modrm with no index |
8661 | register. We've already stored the code for esp | |
8662 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
8663 | Any base register besides %esp will not use the | |
8664 | extra modrm byte. */ | |
8665 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 8666 | } |
63112cd6 | 8667 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8668 | { |
e968fc9b | 8669 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8670 | i.sib.index = NO_INDEX_REGISTER; |
8671 | else | |
8672 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8673 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
8674 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 8675 | i.rex |= REX_X; |
29b0f896 | 8676 | } |
67a4f2b7 AO |
8677 | |
8678 | if (i.disp_operands | |
8679 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
8680 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
8681 | i.rm.mode = 0; | |
8682 | else | |
a501d77e L |
8683 | { |
8684 | if (!fake_zero_displacement | |
8685 | && !i.disp_operands | |
8686 | && i.disp_encoding) | |
8687 | { | |
8688 | fake_zero_displacement = 1; | |
8689 | if (i.disp_encoding == disp_encoding_8bit) | |
8690 | i.types[op].bitfield.disp8 = 1; | |
8691 | else | |
8692 | i.types[op].bitfield.disp32 = 1; | |
8693 | } | |
8694 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8695 | } | |
29b0f896 | 8696 | } |
252b5132 | 8697 | |
29b0f896 AM |
8698 | if (fake_zero_displacement) |
8699 | { | |
8700 | /* Fakes a zero displacement assuming that i.types[op] | |
8701 | holds the correct displacement size. */ | |
8702 | expressionS *exp; | |
8703 | ||
9c2799c2 | 8704 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
8705 | exp = &disp_expressions[i.disp_operands++]; |
8706 | i.op[op].disps = exp; | |
8707 | exp->X_op = O_constant; | |
8708 | exp->X_add_number = 0; | |
8709 | exp->X_add_symbol = (symbolS *) 0; | |
8710 | exp->X_op_symbol = (symbolS *) 0; | |
8711 | } | |
c0f3af97 L |
8712 | |
8713 | mem = op; | |
29b0f896 | 8714 | } |
c0f3af97 L |
8715 | else |
8716 | mem = ~0; | |
252b5132 | 8717 | |
5dab1799 | 8718 | if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
8719 | { |
8720 | i.vex.register_specifier = i.op[2].regs; | |
8721 | if (!i.mem_operands) | |
8722 | { | |
8723 | i.rm.mode = 3; | |
8724 | i.rm.regmem = i.op[1].regs->reg_num; | |
8725 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8726 | i.rex |= REX_B; | |
8727 | } | |
8728 | } | |
29b0f896 AM |
8729 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
8730 | (if any) based on i.tm.extension_opcode. Again, we must be | |
8731 | careful to make sure that segment/control/debug/test/MMX | |
8732 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 8733 | else if (i.reg_operands) |
29b0f896 | 8734 | { |
99018f42 | 8735 | unsigned int op; |
7ab9ffdd L |
8736 | unsigned int vex_reg = ~0; |
8737 | ||
8738 | for (op = 0; op < i.operands; op++) | |
921eafea L |
8739 | if (i.types[op].bitfield.class == Reg |
8740 | || i.types[op].bitfield.class == RegBND | |
8741 | || i.types[op].bitfield.class == RegMask | |
8742 | || i.types[op].bitfield.class == SReg | |
8743 | || i.types[op].bitfield.class == RegCR | |
8744 | || i.types[op].bitfield.class == RegDR | |
8745 | || i.types[op].bitfield.class == RegTR | |
8746 | || i.types[op].bitfield.class == RegSIMD | |
8747 | || i.types[op].bitfield.class == RegMMX) | |
8748 | break; | |
c0209578 | 8749 | |
7ab9ffdd L |
8750 | if (vex_3_sources) |
8751 | op = dest; | |
2426c15f | 8752 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
8753 | { |
8754 | /* For instructions with VexNDS, the register-only | |
8755 | source operand is encoded in VEX prefix. */ | |
8756 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 8757 | |
a93e3234 | 8758 | if (op > mem || i.tm.cpu_flags.bitfield.cpucmpccxadd) |
c0f3af97 | 8759 | { |
7ab9ffdd L |
8760 | vex_reg = op++; |
8761 | gas_assert (op < i.operands); | |
c0f3af97 L |
8762 | } |
8763 | else | |
c0f3af97 | 8764 | { |
f12dc422 L |
8765 | /* Check register-only source operand when two source |
8766 | operands are swapped. */ | |
8767 | if (!i.tm.operand_types[op].bitfield.baseindex | |
8768 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
8769 | { | |
8770 | vex_reg = op; | |
8771 | op += 2; | |
8772 | gas_assert (mem == (vex_reg + 1) | |
8773 | && op < i.operands); | |
8774 | } | |
8775 | else | |
8776 | { | |
8777 | vex_reg = op + 1; | |
8778 | gas_assert (vex_reg < i.operands); | |
8779 | } | |
c0f3af97 | 8780 | } |
7ab9ffdd | 8781 | } |
2426c15f | 8782 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 8783 | { |
f12dc422 | 8784 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 8785 | is encoded in VEX prefix. */ |
f12dc422 L |
8786 | if (i.mem_operands == 0) |
8787 | { | |
8788 | /* There is no memory operand. */ | |
8789 | gas_assert ((op + 2) == i.operands); | |
8790 | vex_reg = op + 1; | |
8791 | } | |
8792 | else | |
8d63c93e | 8793 | { |
ed438a93 JB |
8794 | /* There are only 2 non-immediate operands. */ |
8795 | gas_assert (op < i.imm_operands + 2 | |
8796 | && i.operands == i.imm_operands + 2); | |
8797 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 8798 | } |
7ab9ffdd L |
8799 | } |
8800 | else | |
8801 | gas_assert (op < i.operands); | |
99018f42 | 8802 | |
7ab9ffdd L |
8803 | if (vex_reg != (unsigned int) ~0) |
8804 | { | |
f12dc422 | 8805 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 8806 | |
bab6aec1 | 8807 | if ((type->bitfield.class != Reg |
dc821c5f | 8808 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 8809 | && type->bitfield.class != RegSIMD |
c0f327b8 | 8810 | && type->bitfield.class != RegMask) |
7ab9ffdd | 8811 | abort (); |
f88c9eb0 | 8812 | |
7ab9ffdd L |
8813 | i.vex.register_specifier = i.op[vex_reg].regs; |
8814 | } | |
8815 | ||
1b9f0c97 L |
8816 | /* Don't set OP operand twice. */ |
8817 | if (vex_reg != op) | |
7ab9ffdd | 8818 | { |
1b9f0c97 L |
8819 | /* If there is an extension opcode to put here, the |
8820 | register number must be put into the regmem field. */ | |
8821 | if (i.tm.extension_opcode != None) | |
8822 | { | |
8823 | i.rm.regmem = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8824 | set_rex_vrex (i.op[op].regs, REX_B, |
8825 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 L |
8826 | } |
8827 | else | |
8828 | { | |
8829 | i.rm.reg = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8830 | set_rex_vrex (i.op[op].regs, REX_R, |
8831 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 | 8832 | } |
7ab9ffdd | 8833 | } |
252b5132 | 8834 | |
29b0f896 AM |
8835 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
8836 | must set it to 3 to indicate this is a register operand | |
8837 | in the regmem field. */ | |
8838 | if (!i.mem_operands) | |
8839 | i.rm.mode = 3; | |
8840 | } | |
252b5132 | 8841 | |
29b0f896 | 8842 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 8843 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
8844 | i.rm.reg = i.tm.extension_opcode; |
8845 | } | |
8846 | return default_seg; | |
8847 | } | |
252b5132 | 8848 | |
48ef937e JB |
8849 | static INLINE void |
8850 | frag_opcode_byte (unsigned char byte) | |
8851 | { | |
8852 | if (now_seg != absolute_section) | |
8853 | FRAG_APPEND_1_CHAR (byte); | |
8854 | else | |
8855 | ++abs_section_offset; | |
8856 | } | |
8857 | ||
376cd056 JB |
8858 | static unsigned int |
8859 | flip_code16 (unsigned int code16) | |
8860 | { | |
8861 | gas_assert (i.tm.operands == 1); | |
8862 | ||
8863 | return !(i.prefix[REX_PREFIX] & REX_W) | |
8864 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
376cd056 JB |
8865 | : i.tm.operand_types[0].bitfield.disp16) |
8866 | ? CODE16 : 0; | |
8867 | } | |
8868 | ||
29b0f896 | 8869 | static void |
e3bb37b5 | 8870 | output_branch (void) |
29b0f896 AM |
8871 | { |
8872 | char *p; | |
f8a5c266 | 8873 | int size; |
29b0f896 AM |
8874 | int code16; |
8875 | int prefix; | |
8876 | relax_substateT subtype; | |
8877 | symbolS *sym; | |
8878 | offsetT off; | |
8879 | ||
48ef937e JB |
8880 | if (now_seg == absolute_section) |
8881 | { | |
8882 | as_bad (_("relaxable branches not supported in absolute section")); | |
8883 | return; | |
8884 | } | |
8885 | ||
f8a5c266 | 8886 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
1a42a9fe | 8887 | size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL; |
29b0f896 AM |
8888 | |
8889 | prefix = 0; | |
8890 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8891 | { |
29b0f896 AM |
8892 | prefix = 1; |
8893 | i.prefixes -= 1; | |
376cd056 | 8894 | code16 ^= flip_code16(code16); |
252b5132 | 8895 | } |
29b0f896 AM |
8896 | /* Pentium4 branch hints. */ |
8897 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8898 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8899 | { |
29b0f896 AM |
8900 | prefix++; |
8901 | i.prefixes--; | |
8902 | } | |
8903 | if (i.prefix[REX_PREFIX] != 0) | |
8904 | { | |
8905 | prefix++; | |
8906 | i.prefixes--; | |
2f66722d AM |
8907 | } |
8908 | ||
7e8b059b L |
8909 | /* BND prefixed jump. */ |
8910 | if (i.prefix[BND_PREFIX] != 0) | |
8911 | { | |
6cb0a70e JB |
8912 | prefix++; |
8913 | i.prefixes--; | |
7e8b059b L |
8914 | } |
8915 | ||
f2810fe0 | 8916 | if (i.prefixes != 0) |
76d3f746 | 8917 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
29b0f896 AM |
8918 | |
8919 | /* It's always a symbol; End frag & setup for relax. | |
8920 | Make sure there is enough room in this frag for the largest | |
8921 | instruction we may generate in md_convert_frag. This is 2 | |
8922 | bytes for the opcode and room for the prefix and largest | |
8923 | displacement. */ | |
8924 | frag_grow (prefix + 2 + 4); | |
8925 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8926 | p = frag_more (prefix + 1); | |
8927 | if (i.prefix[DATA_PREFIX] != 0) | |
8928 | *p++ = DATA_PREFIX_OPCODE; | |
8929 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8930 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8931 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8932 | if (i.prefix[BND_PREFIX] != 0) |
8933 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8934 | if (i.prefix[REX_PREFIX] != 0) |
8935 | *p++ = i.prefix[REX_PREFIX]; | |
8936 | *p = i.tm.base_opcode; | |
8937 | ||
8938 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8939 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8940 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8941 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8942 | else |
f8a5c266 | 8943 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8944 | subtype |= code16; |
3e73aa7c | 8945 | |
29b0f896 AM |
8946 | sym = i.op[0].disps->X_add_symbol; |
8947 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8948 | |
29b0f896 AM |
8949 | if (i.op[0].disps->X_op != O_constant |
8950 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8951 | { |
29b0f896 AM |
8952 | /* Handle complex expressions. */ |
8953 | sym = make_expr_symbol (i.op[0].disps); | |
8954 | off = 0; | |
8955 | } | |
3e73aa7c | 8956 | |
1ef3994a JB |
8957 | frag_now->tc_frag_data.code64 = flag_code == CODE_64BIT; |
8958 | ||
29b0f896 AM |
8959 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8960 | Pass reloc in fr_var. */ | |
d258b828 | 8961 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8962 | } |
3e73aa7c | 8963 | |
bd7ab16b L |
8964 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8965 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8966 | symbol S. */ | |
8967 | ||
5b7c81bd | 8968 | static bool |
bd7ab16b L |
8969 | need_plt32_p (symbolS *s) |
8970 | { | |
8971 | /* PLT32 relocation is ELF only. */ | |
8972 | if (!IS_ELF) | |
5b7c81bd | 8973 | return false; |
bd7ab16b | 8974 | |
a5def729 RO |
8975 | #ifdef TE_SOLARIS |
8976 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8977 | krtld support it. */ | |
5b7c81bd | 8978 | return false; |
a5def729 RO |
8979 | #endif |
8980 | ||
bd7ab16b L |
8981 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8982 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8983 | be used as a marker for 32-bit PC-relative branches. */ | |
8984 | if (!object_64bit) | |
5b7c81bd | 8985 | return false; |
bd7ab16b | 8986 | |
44365e88 | 8987 | if (s == NULL) |
5b7c81bd | 8988 | return false; |
44365e88 | 8989 | |
bd7ab16b L |
8990 | /* Weak or undefined symbol need PLT32 relocation. */ |
8991 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 8992 | return true; |
bd7ab16b L |
8993 | |
8994 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8995 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 8996 | return false; |
bd7ab16b L |
8997 | |
8998 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8999 | non-default visibilities are treated as normal global symbol | |
9000 | so that PLT32 relocation can be used as a marker for 32-bit | |
9001 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 9002 | return true; |
bd7ab16b L |
9003 | } |
9004 | #endif | |
9005 | ||
29b0f896 | 9006 | static void |
e3bb37b5 | 9007 | output_jump (void) |
29b0f896 AM |
9008 | { |
9009 | char *p; | |
9010 | int size; | |
3e02c1cc | 9011 | fixS *fixP; |
bd7ab16b | 9012 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 9013 | |
0cfa3eb3 | 9014 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
9015 | { |
9016 | /* This is a loop or jecxz type instruction. */ | |
9017 | size = 1; | |
9018 | if (i.prefix[ADDR_PREFIX] != 0) | |
9019 | { | |
48ef937e | 9020 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
9021 | i.prefixes -= 1; |
9022 | } | |
9023 | /* Pentium4 branch hints. */ | |
9024 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
9025 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
9026 | { | |
48ef937e | 9027 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 9028 | i.prefixes--; |
3e73aa7c JH |
9029 | } |
9030 | } | |
29b0f896 AM |
9031 | else |
9032 | { | |
9033 | int code16; | |
3e73aa7c | 9034 | |
29b0f896 AM |
9035 | code16 = 0; |
9036 | if (flag_code == CODE_16BIT) | |
9037 | code16 = CODE16; | |
3e73aa7c | 9038 | |
29b0f896 AM |
9039 | if (i.prefix[DATA_PREFIX] != 0) |
9040 | { | |
48ef937e | 9041 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 9042 | i.prefixes -= 1; |
376cd056 | 9043 | code16 ^= flip_code16(code16); |
29b0f896 | 9044 | } |
252b5132 | 9045 | |
29b0f896 AM |
9046 | size = 4; |
9047 | if (code16) | |
9048 | size = 2; | |
9049 | } | |
9fcc94b6 | 9050 | |
6cb0a70e JB |
9051 | /* BND prefixed jump. */ |
9052 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 9053 | { |
48ef937e | 9054 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
9055 | i.prefixes -= 1; |
9056 | } | |
252b5132 | 9057 | |
6cb0a70e | 9058 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 9059 | { |
48ef937e | 9060 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
9061 | i.prefixes -= 1; |
9062 | } | |
9063 | ||
f2810fe0 | 9064 | if (i.prefixes != 0) |
76d3f746 | 9065 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
e0890092 | 9066 | |
48ef937e JB |
9067 | if (now_seg == absolute_section) |
9068 | { | |
9a182d04 | 9069 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
9070 | return; |
9071 | } | |
9072 | ||
9a182d04 JB |
9073 | p = frag_more (i.opcode_length + size); |
9074 | switch (i.opcode_length) | |
42164a71 L |
9075 | { |
9076 | case 2: | |
9077 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 9078 | /* Fall through. */ |
42164a71 L |
9079 | case 1: |
9080 | *p++ = i.tm.base_opcode; | |
9081 | break; | |
9082 | default: | |
9083 | abort (); | |
9084 | } | |
e0890092 | 9085 | |
bd7ab16b | 9086 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
9087 | if (flag_code == CODE_64BIT && size == 4 |
9088 | && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0 | |
bd7ab16b L |
9089 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
9090 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
9091 | #endif | |
9092 | ||
9093 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
9094 | ||
3e02c1cc | 9095 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 9096 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 9097 | |
eb19308f JB |
9098 | /* All jumps handled here are signed, but don't unconditionally use a |
9099 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
9100 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
9101 | respectively. */ | |
9102 | switch (size) | |
9103 | { | |
9104 | case 1: | |
9105 | fixP->fx_signed = 1; | |
9106 | break; | |
9107 | ||
9108 | case 2: | |
7fc69528 | 9109 | if (i.tm.mnem_off == MN_xbegin) |
eb19308f JB |
9110 | fixP->fx_signed = 1; |
9111 | break; | |
9112 | ||
9113 | case 4: | |
9114 | if (flag_code == CODE_64BIT) | |
9115 | fixP->fx_signed = 1; | |
9116 | break; | |
9117 | } | |
29b0f896 | 9118 | } |
e0890092 | 9119 | |
29b0f896 | 9120 | static void |
e3bb37b5 | 9121 | output_interseg_jump (void) |
29b0f896 AM |
9122 | { |
9123 | char *p; | |
9124 | int size; | |
9125 | int prefix; | |
9126 | int code16; | |
252b5132 | 9127 | |
29b0f896 AM |
9128 | code16 = 0; |
9129 | if (flag_code == CODE_16BIT) | |
9130 | code16 = CODE16; | |
a217f122 | 9131 | |
29b0f896 AM |
9132 | prefix = 0; |
9133 | if (i.prefix[DATA_PREFIX] != 0) | |
9134 | { | |
9135 | prefix = 1; | |
9136 | i.prefixes -= 1; | |
9137 | code16 ^= CODE16; | |
9138 | } | |
6cb0a70e JB |
9139 | |
9140 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 9141 | |
29b0f896 AM |
9142 | size = 4; |
9143 | if (code16) | |
9144 | size = 2; | |
252b5132 | 9145 | |
f2810fe0 | 9146 | if (i.prefixes != 0) |
76d3f746 | 9147 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
252b5132 | 9148 | |
48ef937e JB |
9149 | if (now_seg == absolute_section) |
9150 | { | |
9151 | abs_section_offset += prefix + 1 + 2 + size; | |
9152 | return; | |
9153 | } | |
9154 | ||
29b0f896 AM |
9155 | /* 1 opcode; 2 segment; offset */ |
9156 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 9157 | |
29b0f896 AM |
9158 | if (i.prefix[DATA_PREFIX] != 0) |
9159 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 9160 | |
29b0f896 AM |
9161 | if (i.prefix[REX_PREFIX] != 0) |
9162 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 9163 | |
29b0f896 AM |
9164 | *p++ = i.tm.base_opcode; |
9165 | if (i.op[1].imms->X_op == O_constant) | |
9166 | { | |
9167 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 9168 | |
29b0f896 AM |
9169 | if (size == 2 |
9170 | && !fits_in_unsigned_word (n) | |
9171 | && !fits_in_signed_word (n)) | |
9172 | { | |
9173 | as_bad (_("16-bit jump out of range")); | |
9174 | return; | |
9175 | } | |
9176 | md_number_to_chars (p, n, size); | |
9177 | } | |
9178 | else | |
9179 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 9180 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
9181 | |
9182 | p += size; | |
9183 | if (i.op[0].imms->X_op == O_constant) | |
9184 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
9185 | else | |
9186 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
9187 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 9188 | } |
a217f122 | 9189 | |
b4a3a7b4 L |
9190 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9191 | void | |
9192 | x86_cleanup (void) | |
9193 | { | |
9194 | char *p; | |
9195 | asection *seg = now_seg; | |
9196 | subsegT subseg = now_subseg; | |
9197 | asection *sec; | |
9198 | unsigned int alignment, align_size_1; | |
9199 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
9200 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
9201 | unsigned int padding; | |
9202 | ||
1273b2f8 | 9203 | if (!IS_ELF || !x86_used_note) |
b4a3a7b4 L |
9204 | return; |
9205 | ||
b4a3a7b4 L |
9206 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
9207 | ||
9208 | /* The .note.gnu.property section layout: | |
9209 | ||
9210 | Field Length Contents | |
9211 | ---- ---- ---- | |
9212 | n_namsz 4 4 | |
9213 | n_descsz 4 The note descriptor size | |
9214 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
9215 | n_name 4 "GNU" | |
9216 | n_desc n_descsz The program property array | |
9217 | .... .... .... | |
9218 | */ | |
9219 | ||
9220 | /* Create the .note.gnu.property section. */ | |
9221 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 9222 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
9223 | (SEC_ALLOC |
9224 | | SEC_LOAD | |
9225 | | SEC_DATA | |
9226 | | SEC_HAS_CONTENTS | |
9227 | | SEC_READONLY)); | |
9228 | ||
9229 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
9230 | { | |
9231 | align_size_1 = 7; | |
9232 | alignment = 3; | |
9233 | } | |
9234 | else | |
9235 | { | |
9236 | align_size_1 = 3; | |
9237 | alignment = 2; | |
9238 | } | |
9239 | ||
fd361982 | 9240 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
9241 | elf_section_type (sec) = SHT_NOTE; |
9242 | ||
1273b2f8 L |
9243 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
9244 | + 4-byte data */ | |
9245 | isa_1_descsz_raw = 4 + 4 + 4; | |
9246 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
9247 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
b4a3a7b4 L |
9248 | |
9249 | feature_2_descsz_raw = isa_1_descsz; | |
9250 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
1273b2f8 | 9251 | + 4-byte data */ |
b4a3a7b4 L |
9252 | feature_2_descsz_raw += 4 + 4 + 4; |
9253 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
9254 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
9255 | & ~align_size_1); | |
9256 | ||
9257 | descsz = feature_2_descsz; | |
9258 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
9259 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
9260 | ||
9261 | /* Write n_namsz. */ | |
9262 | md_number_to_chars (p, (valueT) 4, 4); | |
9263 | ||
9264 | /* Write n_descsz. */ | |
9265 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
9266 | ||
9267 | /* Write n_type. */ | |
9268 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
9269 | ||
9270 | /* Write n_name. */ | |
9271 | memcpy (p + 4 * 3, "GNU", 4); | |
9272 | ||
1273b2f8 L |
9273 | /* Write 4-byte type. */ |
9274 | md_number_to_chars (p + 4 * 4, | |
9275 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 9276 | |
1273b2f8 L |
9277 | /* Write 4-byte data size. */ |
9278 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 9279 | |
1273b2f8 L |
9280 | /* Write 4-byte data. */ |
9281 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 9282 | |
1273b2f8 L |
9283 | /* Zero out paddings. */ |
9284 | padding = isa_1_descsz - isa_1_descsz_raw; | |
9285 | if (padding) | |
9286 | memset (p + 4 * 7, 0, padding); | |
b4a3a7b4 L |
9287 | |
9288 | /* Write 4-byte type. */ | |
9289 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
9290 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
9291 | ||
9292 | /* Write 4-byte data size. */ | |
9293 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
9294 | ||
9295 | /* Write 4-byte data. */ | |
9296 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
9297 | (valueT) x86_feature_2_used, 4); | |
9298 | ||
9299 | /* Zero out paddings. */ | |
9300 | padding = feature_2_descsz - feature_2_descsz_raw; | |
9301 | if (padding) | |
9302 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
9303 | ||
9304 | /* We probably can't restore the current segment, for there likely | |
9305 | isn't one yet... */ | |
9306 | if (seg && subseg) | |
9307 | subseg_set (seg, subseg); | |
9308 | } | |
b52c4ee4 IB |
9309 | |
9310 | bool | |
9311 | x86_support_sframe_p (void) | |
9312 | { | |
3e3e792a | 9313 | /* At this time, SFrame stack trace is supported for AMD64 ABI only. */ |
b52c4ee4 IB |
9314 | return (x86_elf_abi == X86_64_ABI); |
9315 | } | |
9316 | ||
9317 | bool | |
9318 | x86_sframe_ra_tracking_p (void) | |
9319 | { | |
9320 | /* In AMD64, return address is always stored on the stack at a fixed offset | |
9321 | from the CFA (provided via x86_sframe_cfa_ra_offset ()). | |
9322 | Do not track explicitly via an SFrame Frame Row Entry. */ | |
9323 | return false; | |
9324 | } | |
9325 | ||
9326 | offsetT | |
9327 | x86_sframe_cfa_ra_offset (void) | |
9328 | { | |
9329 | gas_assert (x86_elf_abi == X86_64_ABI); | |
9330 | return (offsetT) -8; | |
9331 | } | |
9332 | ||
9333 | unsigned char | |
9334 | x86_sframe_get_abi_arch (void) | |
9335 | { | |
9336 | unsigned char sframe_abi_arch = 0; | |
9337 | ||
9338 | if (x86_support_sframe_p ()) | |
9339 | { | |
9340 | gas_assert (!target_big_endian); | |
9341 | sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE; | |
9342 | } | |
9343 | ||
9344 | return sframe_abi_arch; | |
9345 | } | |
9346 | ||
b4a3a7b4 L |
9347 | #endif |
9348 | ||
9c33702b JB |
9349 | static unsigned int |
9350 | encoding_length (const fragS *start_frag, offsetT start_off, | |
9351 | const char *frag_now_ptr) | |
9352 | { | |
9353 | unsigned int len = 0; | |
9354 | ||
9355 | if (start_frag != frag_now) | |
9356 | { | |
9357 | const fragS *fr = start_frag; | |
9358 | ||
9359 | do { | |
9360 | len += fr->fr_fix; | |
9361 | fr = fr->fr_next; | |
9362 | } while (fr && fr != frag_now); | |
9363 | } | |
9364 | ||
9365 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
9366 | } | |
9367 | ||
e379e5f3 | 9368 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
9369 | be macro-fused with conditional jumps. |
9370 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
9371 | or is one of the following format: | |
9372 | ||
9373 | cmp m, imm | |
9374 | add m, imm | |
9375 | sub m, imm | |
9376 | test m, imm | |
9377 | and m, imm | |
9378 | inc m | |
9379 | dec m | |
9380 | ||
9381 | it is unfusible. */ | |
e379e5f3 L |
9382 | |
9383 | static int | |
79d72f45 | 9384 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9385 | { |
9386 | /* No RIP address. */ | |
9387 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
9388 | return 0; | |
9389 | ||
389d00a5 | 9390 | /* No opcodes outside of base encoding space. */ |
ddb62495 | 9391 | if (i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
9392 | return 0; |
9393 | ||
79d72f45 HL |
9394 | /* add, sub without add/sub m, imm. */ |
9395 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
9396 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
9397 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 9398 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 9399 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
9400 | { |
9401 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9402 | return !(i.mem_operands && i.imm_operands); | |
9403 | } | |
e379e5f3 | 9404 | |
79d72f45 HL |
9405 | /* and without and m, imm. */ |
9406 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
9407 | || ((i.tm.base_opcode | 3) == 0x83 | |
9408 | && i.tm.extension_opcode == 0x4)) | |
9409 | { | |
9410 | *mf_cmp_p = mf_cmp_test_and; | |
9411 | return !(i.mem_operands && i.imm_operands); | |
9412 | } | |
9413 | ||
9414 | /* test without test m imm. */ | |
e379e5f3 L |
9415 | if ((i.tm.base_opcode | 1) == 0x85 |
9416 | || (i.tm.base_opcode | 1) == 0xa9 | |
9417 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
9418 | && i.tm.extension_opcode == 0)) |
9419 | { | |
9420 | *mf_cmp_p = mf_cmp_test_and; | |
9421 | return !(i.mem_operands && i.imm_operands); | |
9422 | } | |
9423 | ||
9424 | /* cmp without cmp m, imm. */ | |
9425 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
9426 | || ((i.tm.base_opcode | 3) == 0x83 |
9427 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
9428 | { |
9429 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9430 | return !(i.mem_operands && i.imm_operands); | |
9431 | } | |
e379e5f3 | 9432 | |
79d72f45 | 9433 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
9434 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
9435 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
9436 | || ((i.tm.base_opcode | 1) == 0xff | |
9437 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
9438 | { |
9439 | *mf_cmp_p = mf_cmp_incdec; | |
9440 | return !i.mem_operands; | |
9441 | } | |
e379e5f3 L |
9442 | |
9443 | return 0; | |
9444 | } | |
9445 | ||
9446 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
9447 | ||
9448 | static int | |
79d72f45 | 9449 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9450 | { |
9451 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9452 | if (!align_branch_power | |
9453 | || now_seg == absolute_section | |
9454 | || !cpu_arch_flags.bitfield.cpui386 | |
9455 | || !(align_branch & align_branch_fused_bit)) | |
9456 | return 0; | |
9457 | ||
79d72f45 | 9458 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
9459 | { |
9460 | if (last_insn.kind == last_insn_other | |
9461 | || last_insn.seg != now_seg) | |
9462 | return 1; | |
9463 | if (flag_debug) | |
9464 | as_warn_where (last_insn.file, last_insn.line, | |
9465 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
76d3f746 | 9466 | last_insn.name, insn_name (&i.tm)); |
e379e5f3 L |
9467 | } |
9468 | ||
9469 | return 0; | |
9470 | } | |
9471 | ||
9472 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
9473 | ||
9474 | static int | |
9475 | add_branch_prefix_frag_p (void) | |
9476 | { | |
9477 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
9478 | to PadLock instructions since they include prefixes in opcode. */ | |
9479 | if (!align_branch_power | |
9480 | || !align_branch_prefix_size | |
9481 | || now_seg == absolute_section | |
9482 | || i.tm.cpu_flags.bitfield.cpupadlock | |
9483 | || !cpu_arch_flags.bitfield.cpui386) | |
9484 | return 0; | |
9485 | ||
9486 | /* Don't add prefix if it is a prefix or there is no operand in case | |
9487 | that segment prefix is special. */ | |
9488 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
9489 | return 0; | |
9490 | ||
9491 | if (last_insn.kind == last_insn_other | |
9492 | || last_insn.seg != now_seg) | |
9493 | return 1; | |
9494 | ||
9495 | if (flag_debug) | |
9496 | as_warn_where (last_insn.file, last_insn.line, | |
9497 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
76d3f746 | 9498 | last_insn.name, insn_name (&i.tm)); |
e379e5f3 L |
9499 | |
9500 | return 0; | |
9501 | } | |
9502 | ||
9503 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
9504 | ||
9505 | static int | |
79d72f45 HL |
9506 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
9507 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
9508 | { |
9509 | int add_padding; | |
9510 | ||
9511 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9512 | if (!align_branch_power | |
9513 | || now_seg == absolute_section | |
389d00a5 | 9514 | || !cpu_arch_flags.bitfield.cpui386 |
ddb62495 | 9515 | || i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
9516 | return 0; |
9517 | ||
9518 | add_padding = 0; | |
9519 | ||
9520 | /* Check for jcc and direct jmp. */ | |
9521 | if (i.tm.opcode_modifier.jump == JUMP) | |
9522 | { | |
9523 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
9524 | { | |
9525 | *branch_p = align_branch_jmp; | |
9526 | add_padding = align_branch & align_branch_jmp_bit; | |
9527 | } | |
9528 | else | |
9529 | { | |
79d72f45 HL |
9530 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
9531 | igore the lowest bit. */ | |
9532 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
9533 | *branch_p = align_branch_jcc; |
9534 | if ((align_branch & align_branch_jcc_bit)) | |
9535 | add_padding = 1; | |
9536 | } | |
9537 | } | |
e379e5f3 L |
9538 | else if ((i.tm.base_opcode | 1) == 0xc3) |
9539 | { | |
9540 | /* Near ret. */ | |
9541 | *branch_p = align_branch_ret; | |
9542 | if ((align_branch & align_branch_ret_bit)) | |
9543 | add_padding = 1; | |
9544 | } | |
9545 | else | |
9546 | { | |
9547 | /* Check for indirect jmp, direct and indirect calls. */ | |
9548 | if (i.tm.base_opcode == 0xe8) | |
9549 | { | |
9550 | /* Direct call. */ | |
9551 | *branch_p = align_branch_call; | |
9552 | if ((align_branch & align_branch_call_bit)) | |
9553 | add_padding = 1; | |
9554 | } | |
9555 | else if (i.tm.base_opcode == 0xff | |
9556 | && (i.tm.extension_opcode == 2 | |
9557 | || i.tm.extension_opcode == 4)) | |
9558 | { | |
9559 | /* Indirect call and jmp. */ | |
9560 | *branch_p = align_branch_indirect; | |
9561 | if ((align_branch & align_branch_indirect_bit)) | |
9562 | add_padding = 1; | |
9563 | } | |
9564 | ||
9565 | if (add_padding | |
9566 | && i.disp_operands | |
9567 | && tls_get_addr | |
9568 | && (i.op[0].disps->X_op == O_symbol | |
9569 | || (i.op[0].disps->X_op == O_subtract | |
9570 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
9571 | { | |
9572 | symbolS *s = i.op[0].disps->X_add_symbol; | |
9573 | /* No padding to call to global or undefined tls_get_addr. */ | |
9574 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
9575 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
9576 | return 0; | |
9577 | } | |
9578 | } | |
9579 | ||
9580 | if (add_padding | |
9581 | && last_insn.kind != last_insn_other | |
9582 | && last_insn.seg == now_seg) | |
9583 | { | |
9584 | if (flag_debug) | |
9585 | as_warn_where (last_insn.file, last_insn.line, | |
9586 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
76d3f746 | 9587 | last_insn.name, insn_name (&i.tm)); |
e379e5f3 L |
9588 | return 0; |
9589 | } | |
9590 | ||
9591 | return add_padding; | |
9592 | } | |
9593 | ||
29b0f896 | 9594 | static void |
e3bb37b5 | 9595 | output_insn (void) |
29b0f896 | 9596 | { |
2bbd9c25 JJ |
9597 | fragS *insn_start_frag; |
9598 | offsetT insn_start_off; | |
e379e5f3 L |
9599 | fragS *fragP = NULL; |
9600 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
9601 | /* The initializer is arbitrary just to avoid uninitialized error. |
9602 | it's actually either assigned in add_branch_padding_frag_p | |
9603 | or never be used. */ | |
9604 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 9605 | |
b4a3a7b4 | 9606 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 9607 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 9608 | { |
32930e4e L |
9609 | if ((i.xstate & xstate_tmm) == xstate_tmm |
9610 | || i.tm.cpu_flags.bitfield.cpuamx_tile) | |
9611 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; | |
9612 | ||
b4a3a7b4 L |
9613 | if (i.tm.cpu_flags.bitfield.cpu8087 |
9614 | || i.tm.cpu_flags.bitfield.cpu287 | |
9615 | || i.tm.cpu_flags.bitfield.cpu387 | |
9616 | || i.tm.cpu_flags.bitfield.cpu687 | |
9617 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
9618 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
014d61ea | 9619 | |
921eafea | 9620 | if ((i.xstate & xstate_mmx) |
7fc69528 JB |
9621 | || i.tm.mnem_off == MN_emms |
9622 | || i.tm.mnem_off == MN_femms) | |
b4a3a7b4 | 9623 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 9624 | |
32930e4e L |
9625 | if (i.index_reg) |
9626 | { | |
9627 | if (i.index_reg->reg_type.bitfield.zmmword) | |
9628 | i.xstate |= xstate_zmm; | |
9629 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
9630 | i.xstate |= xstate_ymm; | |
9631 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
9632 | i.xstate |= xstate_xmm; | |
9633 | } | |
014d61ea JB |
9634 | |
9635 | /* vzeroall / vzeroupper */ | |
9636 | if (i.tm.base_opcode == 0x77 && i.tm.cpu_flags.bitfield.cpuavx) | |
9637 | i.xstate |= xstate_ymm; | |
9638 | ||
c4694f17 | 9639 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
9640 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
9641 | || (i.tm.base_opcode == 0xae | |
9642 | && (i.tm.cpu_flags.bitfield.cpusse | |
9643 | || i.tm.cpu_flags.bitfield.cpuavx)) | |
c4694f17 TG |
9644 | || i.tm.cpu_flags.bitfield.cpuwidekl |
9645 | || i.tm.cpu_flags.bitfield.cpukl) | |
b4a3a7b4 | 9646 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 9647 | |
921eafea | 9648 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 9649 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 9650 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 9651 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 9652 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 9653 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
b4a3a7b4 L |
9654 | if (i.tm.cpu_flags.bitfield.cpufxsr) |
9655 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
9656 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
9657 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
9658 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
9659 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
9660 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
9661 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
b0ab0693 L |
9662 | |
9663 | if (x86_feature_2_used | |
9664 | || i.tm.cpu_flags.bitfield.cpucmov | |
9665 | || i.tm.cpu_flags.bitfield.cpusyscall | |
7fc69528 | 9666 | || i.tm.mnem_off == MN_cmpxchg8b) |
b0ab0693 L |
9667 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; |
9668 | if (i.tm.cpu_flags.bitfield.cpusse3 | |
9669 | || i.tm.cpu_flags.bitfield.cpussse3 | |
9670 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
9671 | || i.tm.cpu_flags.bitfield.cpusse4_2 | |
9672 | || i.tm.cpu_flags.bitfield.cpucx16 | |
9673 | || i.tm.cpu_flags.bitfield.cpupopcnt | |
9674 | /* LAHF-SAHF insns in 64-bit mode. */ | |
9675 | || (flag_code == CODE_64BIT | |
35648716 | 9676 | && (i.tm.base_opcode | 1) == 0x9f |
ddb62495 | 9677 | && i.tm.opcode_space == SPACE_BASE)) |
b0ab0693 L |
9678 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
9679 | if (i.tm.cpu_flags.bitfield.cpuavx | |
9680 | || i.tm.cpu_flags.bitfield.cpuavx2 | |
a9860005 JB |
9681 | /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ, |
9682 | XOP, FMA4, LPW, TBM, and AMX. */ | |
b0ab0693 L |
9683 | || (i.tm.opcode_modifier.vex |
9684 | && !i.tm.cpu_flags.bitfield.cpuavx512f | |
9685 | && !i.tm.cpu_flags.bitfield.cpuavx512bw | |
9686 | && !i.tm.cpu_flags.bitfield.cpuavx512dq | |
a9860005 JB |
9687 | && !i.tm.cpu_flags.bitfield.cpuxop |
9688 | && !i.tm.cpu_flags.bitfield.cpufma4 | |
b0ab0693 L |
9689 | && !i.tm.cpu_flags.bitfield.cpulwp |
9690 | && !i.tm.cpu_flags.bitfield.cputbm | |
9691 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) | |
9692 | || i.tm.cpu_flags.bitfield.cpuf16c | |
9693 | || i.tm.cpu_flags.bitfield.cpufma | |
9694 | || i.tm.cpu_flags.bitfield.cpulzcnt | |
9695 | || i.tm.cpu_flags.bitfield.cpumovbe | |
9696 | || i.tm.cpu_flags.bitfield.cpuxsaves | |
9697 | || (x86_feature_2_used | |
9698 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
9699 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
9700 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
9701 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
9702 | if (i.tm.cpu_flags.bitfield.cpuavx512f | |
9703 | || i.tm.cpu_flags.bitfield.cpuavx512bw | |
9704 | || i.tm.cpu_flags.bitfield.cpuavx512dq | |
9705 | || i.tm.cpu_flags.bitfield.cpuavx512vl | |
a9860005 JB |
9706 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF, |
9707 | AVX512-4FMAPS, and AVX512-4VNNIW. */ | |
b0ab0693 L |
9708 | || (i.tm.opcode_modifier.evex |
9709 | && !i.tm.cpu_flags.bitfield.cpuavx512er | |
9710 | && !i.tm.cpu_flags.bitfield.cpuavx512pf | |
a9860005 | 9711 | && !i.tm.cpu_flags.bitfield.cpuavx512_4fmaps |
b0ab0693 L |
9712 | && !i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)) |
9713 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; | |
b4a3a7b4 L |
9714 | } |
9715 | #endif | |
9716 | ||
29b0f896 AM |
9717 | /* Tie dwarf2 debug info to the address at the start of the insn. |
9718 | We can't do this after the insn has been output as the current | |
9719 | frag may have been closed off. eg. by frag_var. */ | |
9720 | dwarf2_emit_insn (0); | |
9721 | ||
2bbd9c25 JJ |
9722 | insn_start_frag = frag_now; |
9723 | insn_start_off = frag_now_fix (); | |
9724 | ||
79d72f45 | 9725 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
9726 | { |
9727 | char *p; | |
9728 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
9729 | unsigned int max_branch_padding_size = 14; | |
9730 | ||
9731 | /* Align section to boundary. */ | |
9732 | record_alignment (now_seg, align_branch_power); | |
9733 | ||
9734 | /* Make room for padding. */ | |
9735 | frag_grow (max_branch_padding_size); | |
9736 | ||
9737 | /* Start of the padding. */ | |
9738 | p = frag_more (0); | |
9739 | ||
9740 | fragP = frag_now; | |
9741 | ||
9742 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
9743 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
9744 | NULL, 0, p); | |
9745 | ||
79d72f45 | 9746 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
9747 | fragP->tc_frag_data.branch_type = branch; |
9748 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
9749 | } | |
9750 | ||
d59a54c2 JB |
9751 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT) |
9752 | && !pre_386_16bit_warned) | |
9753 | { | |
9754 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
9755 | pre_386_16bit_warned = true; | |
9756 | } | |
9757 | ||
29b0f896 | 9758 | /* Output jumps. */ |
0cfa3eb3 | 9759 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 9760 | output_branch (); |
0cfa3eb3 JB |
9761 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9762 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 9763 | output_jump (); |
0cfa3eb3 | 9764 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
9765 | output_interseg_jump (); |
9766 | else | |
9767 | { | |
9768 | /* Output normal instructions here. */ | |
9769 | char *p; | |
9770 | unsigned char *q; | |
47465058 | 9771 | unsigned int j; |
79d72f45 | 9772 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 9773 | |
e4e00185 | 9774 | if (avoid_fence |
389d00a5 JB |
9775 | && (i.tm.base_opcode == 0xaee8 |
9776 | || i.tm.base_opcode == 0xaef0 | |
9777 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
9778 | { |
9779 | /* Encode lfence, mfence, and sfence as | |
9780 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
47f4115a | 9781 | if (flag_code == CODE_16BIT) |
76d3f746 | 9782 | as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm)); |
47f4115a JB |
9783 | else if (omit_lock_prefix) |
9784 | as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"), | |
76d3f746 | 9785 | insn_name (&i.tm)); |
47f4115a | 9786 | else if (now_seg != absolute_section) |
48ef937e JB |
9787 | { |
9788 | offsetT val = 0x240483f0ULL; | |
9789 | ||
9790 | p = frag_more (5); | |
9791 | md_number_to_chars (p, val, 5); | |
9792 | } | |
9793 | else | |
9794 | abs_section_offset += 5; | |
9795 | return; | |
9796 | } | |
e4e00185 | 9797 | |
d022bddd IT |
9798 | /* Some processors fail on LOCK prefix. This options makes |
9799 | assembler ignore LOCK prefix and serves as a workaround. */ | |
9800 | if (omit_lock_prefix) | |
9801 | { | |
35648716 JB |
9802 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
9803 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
9804 | return; |
9805 | i.prefix[LOCK_PREFIX] = 0; | |
9806 | } | |
9807 | ||
e379e5f3 L |
9808 | if (branch) |
9809 | /* Skip if this is a branch. */ | |
9810 | ; | |
79d72f45 | 9811 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
9812 | { |
9813 | /* Make room for padding. */ | |
9814 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
9815 | p = frag_more (0); | |
9816 | ||
9817 | fragP = frag_now; | |
9818 | ||
9819 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
9820 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
9821 | NULL, 0, p); | |
9822 | ||
79d72f45 | 9823 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
9824 | fragP->tc_frag_data.branch_type = align_branch_fused; |
9825 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
9826 | } | |
9827 | else if (add_branch_prefix_frag_p ()) | |
9828 | { | |
9829 | unsigned int max_prefix_size = align_branch_prefix_size; | |
9830 | ||
9831 | /* Make room for padding. */ | |
9832 | frag_grow (max_prefix_size); | |
9833 | p = frag_more (0); | |
9834 | ||
9835 | fragP = frag_now; | |
9836 | ||
9837 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
9838 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
9839 | NULL, 0, p); | |
9840 | ||
9841 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
9842 | } | |
9843 | ||
43234a1e L |
9844 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
9845 | don't need the explicit prefix. */ | |
cf665fee | 9846 | if (!is_any_vex_encoding (&i.tm)) |
bc4bd9ab | 9847 | { |
7b47a312 | 9848 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 9849 | { |
7b47a312 L |
9850 | case PREFIX_0X66: |
9851 | add_prefix (0x66); | |
9852 | break; | |
9853 | case PREFIX_0XF2: | |
9854 | add_prefix (0xf2); | |
9855 | break; | |
9856 | case PREFIX_0XF3: | |
8b65b895 L |
9857 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
9858 | || (i.prefix[REP_PREFIX] != 0xf3)) | |
9859 | add_prefix (0xf3); | |
c0f3af97 | 9860 | break; |
7b47a312 | 9861 | case PREFIX_NONE: |
9a182d04 | 9862 | switch (i.opcode_length) |
c0f3af97 | 9863 | { |
7b47a312 | 9864 | case 2: |
7b47a312 | 9865 | break; |
9a182d04 | 9866 | case 1: |
7b47a312 | 9867 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
9868 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
9869 | break; | |
7b47a312 L |
9870 | as_bad_where (insn_start_frag->fr_file, |
9871 | insn_start_frag->fr_line, | |
9872 | _("pseudo prefix without instruction")); | |
9873 | return; | |
9874 | default: | |
9875 | abort (); | |
4dffcebc | 9876 | } |
c0f3af97 | 9877 | break; |
c0f3af97 L |
9878 | default: |
9879 | abort (); | |
bc4bd9ab | 9880 | } |
c0f3af97 | 9881 | |
6d19a37a | 9882 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
9883 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
9884 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
9885 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
9886 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
9887 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
9888 | if (x86_elf_abi == X86_64_X32_ABI |
9889 | && i.operands == 2 | |
14470f07 L |
9890 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
9891 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
9892 | && i.prefix[REX_PREFIX] == 0) |
9893 | add_prefix (REX_OPCODE); | |
6d19a37a | 9894 | #endif |
cf61b747 | 9895 | |
c0f3af97 L |
9896 | /* The prefix bytes. */ |
9897 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
9898 | if (*q) | |
48ef937e | 9899 | frag_opcode_byte (*q); |
0f10071e | 9900 | } |
ae5c1c7b | 9901 | else |
c0f3af97 L |
9902 | { |
9903 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
9904 | if (*q) | |
9905 | switch (j) | |
9906 | { | |
c0f3af97 L |
9907 | case SEG_PREFIX: |
9908 | case ADDR_PREFIX: | |
48ef937e | 9909 | frag_opcode_byte (*q); |
c0f3af97 L |
9910 | break; |
9911 | default: | |
9912 | /* There should be no other prefixes for instructions | |
9913 | with VEX prefix. */ | |
9914 | abort (); | |
9915 | } | |
9916 | ||
43234a1e L |
9917 | /* For EVEX instructions i.vrex should become 0 after |
9918 | build_evex_prefix. For VEX instructions upper 16 registers | |
9919 | aren't available, so VREX should be 0. */ | |
9920 | if (i.vrex) | |
9921 | abort (); | |
c0f3af97 | 9922 | /* Now the VEX prefix. */ |
48ef937e JB |
9923 | if (now_seg != absolute_section) |
9924 | { | |
9925 | p = frag_more (i.vex.length); | |
9926 | for (j = 0; j < i.vex.length; j++) | |
9927 | p[j] = i.vex.bytes[j]; | |
9928 | } | |
9929 | else | |
9930 | abs_section_offset += i.vex.length; | |
c0f3af97 | 9931 | } |
252b5132 | 9932 | |
29b0f896 | 9933 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
9934 | j = i.opcode_length; |
9935 | if (!i.vex.length) | |
ddb62495 | 9936 | switch (i.tm.opcode_space) |
389d00a5 JB |
9937 | { |
9938 | case SPACE_BASE: | |
9939 | break; | |
9940 | case SPACE_0F: | |
9941 | ++j; | |
9942 | break; | |
9943 | case SPACE_0F38: | |
9944 | case SPACE_0F3A: | |
9945 | j += 2; | |
9946 | break; | |
9947 | default: | |
9948 | abort (); | |
9949 | } | |
9950 | ||
48ef937e | 9951 | if (now_seg == absolute_section) |
389d00a5 JB |
9952 | abs_section_offset += j; |
9953 | else if (j == 1) | |
29b0f896 AM |
9954 | { |
9955 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
9956 | } | |
9957 | else | |
9958 | { | |
389d00a5 JB |
9959 | p = frag_more (j); |
9960 | if (!i.vex.length | |
ddb62495 | 9961 | && i.tm.opcode_space != SPACE_BASE) |
389d00a5 JB |
9962 | { |
9963 | *p++ = 0x0f; | |
ddb62495 JB |
9964 | if (i.tm.opcode_space != SPACE_0F) |
9965 | *p++ = i.tm.opcode_space == SPACE_0F38 | |
389d00a5 JB |
9966 | ? 0x38 : 0x3a; |
9967 | } | |
9968 | ||
9a182d04 | 9969 | switch (i.opcode_length) |
331d2d0d | 9970 | { |
4dffcebc | 9971 | case 2: |
389d00a5 JB |
9972 | /* Put out high byte first: can't use md_number_to_chars! */ |
9973 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
9974 | /* Fall through. */ | |
9975 | case 1: | |
9976 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
9977 | break; |
9978 | default: | |
9979 | abort (); | |
9980 | break; | |
331d2d0d | 9981 | } |
0f10071e | 9982 | |
29b0f896 | 9983 | } |
3e73aa7c | 9984 | |
29b0f896 | 9985 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 9986 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 9987 | { |
48ef937e JB |
9988 | frag_opcode_byte ((i.rm.regmem << 0) |
9989 | | (i.rm.reg << 3) | |
9990 | | (i.rm.mode << 6)); | |
29b0f896 AM |
9991 | /* If i.rm.regmem == ESP (4) |
9992 | && i.rm.mode != (Register mode) | |
9993 | && not 16 bit | |
9994 | ==> need second modrm byte. */ | |
9995 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
9996 | && i.rm.mode != 3 | |
dc821c5f | 9997 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
9998 | frag_opcode_byte ((i.sib.base << 0) |
9999 | | (i.sib.index << 3) | |
10000 | | (i.sib.scale << 6)); | |
29b0f896 | 10001 | } |
3e73aa7c | 10002 | |
29b0f896 | 10003 | if (i.disp_operands) |
2bbd9c25 | 10004 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 10005 | |
29b0f896 | 10006 | if (i.imm_operands) |
2bbd9c25 | 10007 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
10008 | |
10009 | /* | |
10010 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
10011 | * absolute section, and abs_section_offset not getting updated as data | |
10012 | * gets added to the frag breaks the logic below. | |
10013 | */ | |
10014 | if (now_seg != absolute_section) | |
10015 | { | |
10016 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
10017 | if (j > 15) | |
10018 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
10019 | j); | |
e379e5f3 L |
10020 | else if (fragP) |
10021 | { | |
10022 | /* NB: Don't add prefix with GOTPC relocation since | |
10023 | output_disp() above depends on the fixed encoding | |
10024 | length. Can't add prefix with TLS relocation since | |
10025 | it breaks TLS linker optimization. */ | |
10026 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
10027 | /* Prefix count on the current instruction. */ | |
10028 | unsigned int count = i.vex.length; | |
10029 | unsigned int k; | |
10030 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
10031 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
10032 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
10033 | count++; | |
10034 | ||
10035 | /* Count prefixes for extended opcode maps. */ | |
10036 | if (!i.vex.length) | |
ddb62495 | 10037 | switch (i.tm.opcode_space) |
e379e5f3 | 10038 | { |
389d00a5 | 10039 | case SPACE_BASE: |
e379e5f3 | 10040 | break; |
389d00a5 JB |
10041 | case SPACE_0F: |
10042 | count++; | |
e379e5f3 | 10043 | break; |
389d00a5 JB |
10044 | case SPACE_0F38: |
10045 | case SPACE_0F3A: | |
10046 | count += 2; | |
e379e5f3 L |
10047 | break; |
10048 | default: | |
10049 | abort (); | |
10050 | } | |
10051 | ||
10052 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
10053 | == BRANCH_PREFIX) | |
10054 | { | |
10055 | /* Set the maximum prefix size in BRANCH_PREFIX | |
10056 | frag. */ | |
10057 | if (fragP->tc_frag_data.max_bytes > max) | |
10058 | fragP->tc_frag_data.max_bytes = max; | |
10059 | if (fragP->tc_frag_data.max_bytes > count) | |
10060 | fragP->tc_frag_data.max_bytes -= count; | |
10061 | else | |
10062 | fragP->tc_frag_data.max_bytes = 0; | |
10063 | } | |
10064 | else | |
10065 | { | |
10066 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
10067 | frag. */ | |
10068 | unsigned int max_prefix_size; | |
10069 | if (align_branch_prefix_size > max) | |
10070 | max_prefix_size = max; | |
10071 | else | |
10072 | max_prefix_size = align_branch_prefix_size; | |
10073 | if (max_prefix_size > count) | |
10074 | fragP->tc_frag_data.max_prefix_length | |
10075 | = max_prefix_size - count; | |
10076 | } | |
10077 | ||
10078 | /* Use existing segment prefix if possible. Use CS | |
10079 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
10080 | segment prefix with ESP/EBP base register and use DS | |
10081 | segment prefix without ESP/EBP base register. */ | |
10082 | if (i.prefix[SEG_PREFIX]) | |
10083 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
10084 | else if (flag_code == CODE_64BIT) | |
10085 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
10086 | else if (i.base_reg | |
10087 | && (i.base_reg->reg_num == 4 | |
10088 | || i.base_reg->reg_num == 5)) | |
10089 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
10090 | else | |
10091 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
10092 | } | |
9c33702b | 10093 | } |
29b0f896 | 10094 | } |
252b5132 | 10095 | |
e379e5f3 L |
10096 | /* NB: Don't work with COND_JUMP86 without i386. */ |
10097 | if (align_branch_power | |
10098 | && now_seg != absolute_section | |
10099 | && cpu_arch_flags.bitfield.cpui386) | |
10100 | { | |
10101 | /* Terminate each frag so that we can add prefix and check for | |
10102 | fused jcc. */ | |
10103 | frag_wane (frag_now); | |
10104 | frag_new (0); | |
10105 | } | |
10106 | ||
29b0f896 AM |
10107 | #ifdef DEBUG386 |
10108 | if (flag_debug) | |
10109 | { | |
7b81dfbb | 10110 | pi ("" /*line*/, &i); |
29b0f896 AM |
10111 | } |
10112 | #endif /* DEBUG386 */ | |
10113 | } | |
252b5132 | 10114 | |
e205caa7 L |
10115 | /* Return the size of the displacement operand N. */ |
10116 | ||
10117 | static int | |
10118 | disp_size (unsigned int n) | |
10119 | { | |
10120 | int size = 4; | |
43234a1e | 10121 | |
b5014f7a | 10122 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
10123 | size = 8; |
10124 | else if (i.types[n].bitfield.disp8) | |
10125 | size = 1; | |
10126 | else if (i.types[n].bitfield.disp16) | |
10127 | size = 2; | |
e205caa7 L |
10128 | return size; |
10129 | } | |
10130 | ||
10131 | /* Return the size of the immediate operand N. */ | |
10132 | ||
10133 | static int | |
10134 | imm_size (unsigned int n) | |
10135 | { | |
10136 | int size = 4; | |
40fb9820 L |
10137 | if (i.types[n].bitfield.imm64) |
10138 | size = 8; | |
10139 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
10140 | size = 1; | |
10141 | else if (i.types[n].bitfield.imm16) | |
10142 | size = 2; | |
e205caa7 L |
10143 | return size; |
10144 | } | |
10145 | ||
29b0f896 | 10146 | static void |
64e74474 | 10147 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10148 | { |
10149 | char *p; | |
10150 | unsigned int n; | |
252b5132 | 10151 | |
29b0f896 AM |
10152 | for (n = 0; n < i.operands; n++) |
10153 | { | |
b5014f7a | 10154 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 10155 | { |
48ef937e JB |
10156 | int size = disp_size (n); |
10157 | ||
10158 | if (now_seg == absolute_section) | |
10159 | abs_section_offset += size; | |
10160 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 10161 | { |
43234a1e | 10162 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 10163 | |
629cfaf1 JB |
10164 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
10165 | size); | |
29b0f896 AM |
10166 | p = frag_more (size); |
10167 | md_number_to_chars (p, val, size); | |
10168 | } | |
10169 | else | |
10170 | { | |
f86103b7 | 10171 | enum bfd_reloc_code_real reloc_type; |
a775efc8 JB |
10172 | bool pcrel = (i.flags[n] & Operand_PCrel) != 0; |
10173 | bool sign = (flag_code == CODE_64BIT && size == 4 | |
10174 | && (!want_disp32 (&i.tm) | |
10175 | || (i.tm.opcode_modifier.jump && !i.jumpabsolute | |
10176 | && !i.types[n].bitfield.baseindex))) | |
10177 | || pcrel; | |
02a86693 | 10178 | fixS *fixP; |
29b0f896 | 10179 | |
e205caa7 | 10180 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 10181 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 10182 | |
29b0f896 AM |
10183 | /* The PC relative address is computed relative |
10184 | to the instruction boundary, so in case immediate | |
10185 | fields follows, we need to adjust the value. */ | |
10186 | if (pcrel && i.imm_operands) | |
10187 | { | |
29b0f896 | 10188 | unsigned int n1; |
e205caa7 | 10189 | int sz = 0; |
252b5132 | 10190 | |
29b0f896 | 10191 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 10192 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 10193 | { |
e205caa7 L |
10194 | /* Only one immediate is allowed for PC |
10195 | relative address. */ | |
9c2799c2 | 10196 | gas_assert (sz == 0); |
e205caa7 L |
10197 | sz = imm_size (n1); |
10198 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 10199 | } |
29b0f896 | 10200 | /* We should find the immediate. */ |
9c2799c2 | 10201 | gas_assert (sz != 0); |
29b0f896 | 10202 | } |
520dc8e8 | 10203 | |
29b0f896 | 10204 | p = frag_more (size); |
d258b828 | 10205 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 10206 | if (GOT_symbol |
2bbd9c25 | 10207 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 10208 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10209 | || reloc_type == BFD_RELOC_X86_64_32S |
10210 | || (reloc_type == BFD_RELOC_64 | |
10211 | && object_64bit)) | |
d6ab8113 JB |
10212 | && (i.op[n].disps->X_op == O_symbol |
10213 | || (i.op[n].disps->X_op == O_add | |
10214 | && ((symbol_get_value_expression | |
10215 | (i.op[n].disps->X_op_symbol)->X_op) | |
10216 | == O_subtract)))) | |
10217 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 10218 | { |
4fa24527 | 10219 | if (!object_64bit) |
7b81dfbb AJ |
10220 | { |
10221 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 10222 | i.has_gotpc_tls_reloc = true; |
98da05bf | 10223 | i.op[n].disps->X_add_number += |
d583596c | 10224 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
10225 | } |
10226 | else if (reloc_type == BFD_RELOC_64) | |
10227 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 10228 | else |
7b81dfbb AJ |
10229 | /* Don't do the adjustment for x86-64, as there |
10230 | the pcrel addressing is relative to the _next_ | |
10231 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 10232 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 10233 | } |
e379e5f3 L |
10234 | else if (align_branch_power) |
10235 | { | |
10236 | switch (reloc_type) | |
10237 | { | |
10238 | case BFD_RELOC_386_TLS_GD: | |
10239 | case BFD_RELOC_386_TLS_LDM: | |
10240 | case BFD_RELOC_386_TLS_IE: | |
10241 | case BFD_RELOC_386_TLS_IE_32: | |
10242 | case BFD_RELOC_386_TLS_GOTIE: | |
10243 | case BFD_RELOC_386_TLS_GOTDESC: | |
10244 | case BFD_RELOC_386_TLS_DESC_CALL: | |
10245 | case BFD_RELOC_X86_64_TLSGD: | |
10246 | case BFD_RELOC_X86_64_TLSLD: | |
10247 | case BFD_RELOC_X86_64_GOTTPOFF: | |
10248 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
10249 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
5b7c81bd | 10250 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
10251 | default: |
10252 | break; | |
10253 | } | |
10254 | } | |
02a86693 L |
10255 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
10256 | size, i.op[n].disps, pcrel, | |
10257 | reloc_type); | |
eb19308f JB |
10258 | |
10259 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
10260 | && !i.prefix[ADDR_PREFIX]) | |
10261 | fixP->fx_signed = 1; | |
10262 | ||
02a86693 L |
10263 | /* Check for "call/jmp *mem", "mov mem, %reg", |
10264 | "test %reg, mem" and "binop mem, %reg" where binop | |
10265 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
10266 | instructions without data prefix. Always generate |
10267 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
10268 | if (i.prefix[DATA_PREFIX] == 0 | |
10269 | && (generate_relax_relocations | |
10270 | || (!object_64bit | |
10271 | && i.rm.mode == 0 | |
10272 | && i.rm.regmem == 5)) | |
0cb4071e L |
10273 | && (i.rm.mode == 2 |
10274 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
ddb62495 | 10275 | && i.tm.opcode_space == SPACE_BASE |
02a86693 L |
10276 | && ((i.operands == 1 |
10277 | && i.tm.base_opcode == 0xff | |
10278 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
10279 | || (i.operands == 2 | |
10280 | && (i.tm.base_opcode == 0x8b | |
10281 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 10282 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
10283 | { |
10284 | if (object_64bit) | |
10285 | { | |
10286 | fixP->fx_tcbit = i.rex != 0; | |
10287 | if (i.base_reg | |
e968fc9b | 10288 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
10289 | fixP->fx_tcbit2 = 1; |
10290 | } | |
10291 | else | |
10292 | fixP->fx_tcbit2 = 1; | |
10293 | } | |
29b0f896 AM |
10294 | } |
10295 | } | |
10296 | } | |
10297 | } | |
252b5132 | 10298 | |
29b0f896 | 10299 | static void |
64e74474 | 10300 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10301 | { |
10302 | char *p; | |
10303 | unsigned int n; | |
252b5132 | 10304 | |
29b0f896 AM |
10305 | for (n = 0; n < i.operands; n++) |
10306 | { | |
40fb9820 | 10307 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 10308 | { |
48ef937e JB |
10309 | int size = imm_size (n); |
10310 | ||
10311 | if (now_seg == absolute_section) | |
10312 | abs_section_offset += size; | |
10313 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 10314 | { |
29b0f896 | 10315 | offsetT val; |
b4cac588 | 10316 | |
29b0f896 AM |
10317 | val = offset_in_range (i.op[n].imms->X_add_number, |
10318 | size); | |
10319 | p = frag_more (size); | |
10320 | md_number_to_chars (p, val, size); | |
10321 | } | |
10322 | else | |
10323 | { | |
10324 | /* Not absolute_section. | |
10325 | Need a 32-bit fixup (don't support 8bit | |
10326 | non-absolute imms). Try to support other | |
10327 | sizes ... */ | |
f86103b7 | 10328 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 10329 | int sign; |
29b0f896 | 10330 | |
40fb9820 | 10331 | if (i.types[n].bitfield.imm32s |
a7d61044 | 10332 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 10333 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 10334 | sign = 1; |
e205caa7 L |
10335 | else |
10336 | sign = 0; | |
520dc8e8 | 10337 | |
29b0f896 | 10338 | p = frag_more (size); |
d258b828 | 10339 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 10340 | |
2bbd9c25 JJ |
10341 | /* This is tough to explain. We end up with this one if we |
10342 | * have operands that look like | |
10343 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
10344 | * obtain the absolute address of the GOT, and it is strongly | |
10345 | * preferable from a performance point of view to avoid using | |
10346 | * a runtime relocation for this. The actual sequence of | |
10347 | * instructions often look something like: | |
10348 | * | |
10349 | * call .L66 | |
10350 | * .L66: | |
10351 | * popl %ebx | |
10352 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
10353 | * | |
10354 | * The call and pop essentially return the absolute address | |
10355 | * of the label .L66 and store it in %ebx. The linker itself | |
10356 | * will ultimately change the first operand of the addl so | |
10357 | * that %ebx points to the GOT, but to keep things simple, the | |
10358 | * .o file must have this operand set so that it generates not | |
10359 | * the absolute address of .L66, but the absolute address of | |
10360 | * itself. This allows the linker itself simply treat a GOTPC | |
10361 | * relocation as asking for a pcrel offset to the GOT to be | |
10362 | * added in, and the addend of the relocation is stored in the | |
10363 | * operand field for the instruction itself. | |
10364 | * | |
10365 | * Our job here is to fix the operand so that it would add | |
10366 | * the correct offset so that %ebx would point to itself. The | |
10367 | * thing that is tricky is that .-.L66 will point to the | |
10368 | * beginning of the instruction, so we need to further modify | |
10369 | * the operand so that it will point to itself. There are | |
10370 | * other cases where you have something like: | |
10371 | * | |
10372 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
10373 | * | |
10374 | * and here no correction would be required. Internally in | |
10375 | * the assembler we treat operands of this form as not being | |
10376 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
10377 | * whether it would simplify matters to do it this way. Who | |
10378 | * knows. In earlier versions of the PIC patches, the | |
10379 | * pcrel_adjust field was used to store the correction, but | |
10380 | * since the expression is not pcrel, I felt it would be | |
10381 | * confusing to do it this way. */ | |
10382 | ||
d6ab8113 | 10383 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10384 | || reloc_type == BFD_RELOC_X86_64_32S |
10385 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
10386 | && GOT_symbol |
10387 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
10388 | && (i.op[n].imms->X_op == O_symbol | |
10389 | || (i.op[n].imms->X_op == O_add | |
10390 | && ((symbol_get_value_expression | |
10391 | (i.op[n].imms->X_op_symbol)->X_op) | |
10392 | == O_subtract)))) | |
10393 | { | |
4fa24527 | 10394 | if (!object_64bit) |
d6ab8113 | 10395 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 10396 | else if (size == 4) |
d6ab8113 | 10397 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
10398 | else if (size == 8) |
10399 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 10400 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
10401 | i.op[n].imms->X_add_number += |
10402 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 10403 | } |
29b0f896 AM |
10404 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
10405 | i.op[n].imms, 0, reloc_type); | |
10406 | } | |
10407 | } | |
10408 | } | |
252b5132 RH |
10409 | } |
10410 | \f | |
d182319b JB |
10411 | /* x86_cons_fix_new is called via the expression parsing code when a |
10412 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
10413 | static int cons_sign = -1; |
10414 | ||
10415 | void | |
e3bb37b5 | 10416 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 10417 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 10418 | { |
d258b828 | 10419 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
10420 | |
10421 | #ifdef TE_PE | |
10422 | if (exp->X_op == O_secrel) | |
10423 | { | |
10424 | exp->X_op = O_symbol; | |
10425 | r = BFD_RELOC_32_SECREL; | |
10426 | } | |
145667f8 MH |
10427 | else if (exp->X_op == O_secidx) |
10428 | r = BFD_RELOC_16_SECIDX; | |
d182319b JB |
10429 | #endif |
10430 | ||
10431 | fix_new_exp (frag, off, len, exp, 0, r); | |
10432 | } | |
10433 | ||
357d1bd8 L |
10434 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
10435 | purpose of the `.dc.a' internal pseudo-op. */ | |
10436 | ||
10437 | int | |
10438 | x86_address_bytes (void) | |
10439 | { | |
10440 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
10441 | return 4; | |
10442 | return stdoutput->arch_info->bits_per_address / 8; | |
10443 | } | |
10444 | ||
deea4973 JB |
10445 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
10446 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 10447 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 10448 | #else |
f3c180ae AM |
10449 | /* Parse operands of the form |
10450 | <symbol>@GOTOFF+<nnn> | |
10451 | and similar .plt or .got references. | |
10452 | ||
10453 | If we find one, set up the correct relocation in RELOC and copy the | |
10454 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
10455 | parsing by the calling routine. Return this buffer, and if ADJUST | |
10456 | is non-null set it to the length of the string we removed from the | |
10457 | input line. Otherwise return NULL. */ | |
10458 | static char * | |
91d6fa6a | 10459 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 10460 | int *adjust, |
d258b828 | 10461 | i386_operand_type *types) |
f3c180ae | 10462 | { |
7b81dfbb AJ |
10463 | /* Some of the relocations depend on the size of what field is to |
10464 | be relocated. But in our callers i386_immediate and i386_displacement | |
10465 | we don't yet know the operand size (this will be set by insn | |
10466 | matching). Hence we record the word32 relocation here, | |
10467 | and adjust the reloc according to the real size in reloc(). */ | |
145667f8 MH |
10468 | static const struct |
10469 | { | |
f3c180ae | 10470 | const char *str; |
cff8d58a | 10471 | int len; |
4fa24527 | 10472 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 10473 | const i386_operand_type types64; |
5b7c81bd | 10474 | bool need_GOT_symbol; |
145667f8 MH |
10475 | } |
10476 | gotrel[] = | |
10477 | { | |
05909f23 JB |
10478 | |
10479 | #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \ | |
10480 | { .imm32 = 1, .imm32s = 1, .disp32 = 1 } } | |
10481 | #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \ | |
10482 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } } | |
10483 | #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \ | |
10484 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } } | |
10485 | #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \ | |
10486 | { .imm64 = 1, .disp64 = 1 } } | |
10487 | ||
deea4973 | 10488 | #ifndef TE_PE |
8ce3d284 | 10489 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10490 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
10491 | BFD_RELOC_SIZE32 }, | |
05909f23 | 10492 | { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false }, |
8ce3d284 | 10493 | #endif |
cff8d58a L |
10494 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
10495 | BFD_RELOC_X86_64_PLTOFF64 }, | |
05909f23 | 10496 | { .bitfield = { .imm64 = 1 } }, true }, |
cff8d58a L |
10497 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
10498 | BFD_RELOC_X86_64_PLT32 }, | |
a775efc8 | 10499 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
10500 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
10501 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 10502 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10503 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
10504 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 10505 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10506 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
10507 | BFD_RELOC_X86_64_GOTPCREL }, | |
a775efc8 | 10508 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10509 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
10510 | BFD_RELOC_X86_64_TLSGD }, | |
a775efc8 | 10511 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10512 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
10513 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10514 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10515 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
10516 | BFD_RELOC_X86_64_TLSLD }, | |
a775efc8 | 10517 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10518 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
10519 | BFD_RELOC_X86_64_GOTTPOFF }, | |
a775efc8 | 10520 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10521 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
10522 | BFD_RELOC_X86_64_TPOFF32 }, | |
a775efc8 | 10523 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10524 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
10525 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10526 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10527 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
10528 | BFD_RELOC_X86_64_DTPOFF32 }, | |
a775efc8 | 10529 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10530 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
10531 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10532 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10533 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
10534 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10535 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10536 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
10537 | BFD_RELOC_X86_64_GOT32 }, | |
a775efc8 | 10538 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
10539 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
10540 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
a775efc8 | 10541 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10542 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
10543 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
a775efc8 | 10544 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
10545 | #else /* TE_PE */ |
10546 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
10547 | BFD_RELOC_32_SECREL }, | |
a775efc8 | 10548 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, |
deea4973 | 10549 | #endif |
05909f23 JB |
10550 | |
10551 | #undef OPERAND_TYPE_IMM32_32S_DISP32 | |
10552 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32 | |
10553 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64 | |
10554 | #undef OPERAND_TYPE_IMM64_DISP64 | |
10555 | ||
f3c180ae AM |
10556 | }; |
10557 | char *cp; | |
10558 | unsigned int j; | |
10559 | ||
deea4973 | 10560 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
10561 | if (!IS_ELF) |
10562 | return NULL; | |
d382c579 | 10563 | #endif |
718ddfc0 | 10564 | |
f3c180ae | 10565 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 10566 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
10567 | return NULL; |
10568 | ||
47465058 | 10569 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 10570 | { |
cff8d58a | 10571 | int len = gotrel[j].len; |
28f81592 | 10572 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 10573 | { |
4fa24527 | 10574 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 10575 | { |
28f81592 AM |
10576 | int first, second; |
10577 | char *tmpbuf, *past_reloc; | |
f3c180ae | 10578 | |
91d6fa6a | 10579 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 10580 | |
3956db08 JB |
10581 | if (types) |
10582 | { | |
10583 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
10584 | { |
10585 | types->bitfield.imm32 = 1; | |
10586 | types->bitfield.disp32 = 1; | |
10587 | } | |
3956db08 JB |
10588 | else |
10589 | *types = gotrel[j].types64; | |
10590 | } | |
10591 | ||
844bf810 | 10592 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
10593 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
10594 | ||
28f81592 | 10595 | /* The length of the first part of our input line. */ |
f3c180ae | 10596 | first = cp - input_line_pointer; |
28f81592 AM |
10597 | |
10598 | /* The second part goes from after the reloc token until | |
67c11a9b | 10599 | (and including) an end_of_line char or comma. */ |
28f81592 | 10600 | past_reloc = cp + 1 + len; |
67c11a9b AM |
10601 | cp = past_reloc; |
10602 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10603 | ++cp; | |
10604 | second = cp + 1 - past_reloc; | |
28f81592 AM |
10605 | |
10606 | /* Allocate and copy string. The trailing NUL shouldn't | |
10607 | be necessary, but be safe. */ | |
add39d23 | 10608 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 10609 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
10610 | if (second != 0 && *past_reloc != ' ') |
10611 | /* Replace the relocation token with ' ', so that | |
10612 | errors like foo@GOTOFF1 will be detected. */ | |
10613 | tmpbuf[first++] = ' '; | |
af89796a L |
10614 | else |
10615 | /* Increment length by 1 if the relocation token is | |
10616 | removed. */ | |
10617 | len++; | |
10618 | if (adjust) | |
10619 | *adjust = len; | |
0787a12d AM |
10620 | memcpy (tmpbuf + first, past_reloc, second); |
10621 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
10622 | return tmpbuf; |
10623 | } | |
10624 | ||
4fa24527 JB |
10625 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
10626 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
10627 | return NULL; |
10628 | } | |
10629 | } | |
10630 | ||
10631 | /* Might be a symbol version string. Don't as_bad here. */ | |
10632 | return NULL; | |
10633 | } | |
4e4f7c87 | 10634 | #endif |
f3c180ae | 10635 | |
62ebcb5c | 10636 | bfd_reloc_code_real_type |
e3bb37b5 | 10637 | x86_cons (expressionS *exp, int size) |
f3c180ae | 10638 | { |
62ebcb5c AM |
10639 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
10640 | ||
2748c1b1 L |
10641 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
10642 | && !defined (LEX_AT)) \ | |
10643 | || defined (TE_PE) | |
ee86248c JB |
10644 | intel_syntax = -intel_syntax; |
10645 | ||
3c7b9c2c | 10646 | exp->X_md = 0; |
4fa24527 | 10647 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
10648 | { |
10649 | /* Handle @GOTOFF and the like in an expression. */ | |
10650 | char *save; | |
10651 | char *gotfree_input_line; | |
4a57f2cf | 10652 | int adjust = 0; |
f3c180ae AM |
10653 | |
10654 | save = input_line_pointer; | |
d258b828 | 10655 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
10656 | if (gotfree_input_line) |
10657 | input_line_pointer = gotfree_input_line; | |
10658 | ||
10659 | expression (exp); | |
10660 | ||
10661 | if (gotfree_input_line) | |
10662 | { | |
10663 | /* expression () has merrily parsed up to the end of line, | |
10664 | or a comma - in the wrong buffer. Transfer how far | |
10665 | input_line_pointer has moved to the right buffer. */ | |
10666 | input_line_pointer = (save | |
10667 | + (input_line_pointer - gotfree_input_line) | |
10668 | + adjust); | |
10669 | free (gotfree_input_line); | |
3992d3b7 AM |
10670 | if (exp->X_op == O_constant |
10671 | || exp->X_op == O_absent | |
10672 | || exp->X_op == O_illegal | |
0398aac5 | 10673 | || exp->X_op == O_register |
3992d3b7 AM |
10674 | || exp->X_op == O_big) |
10675 | { | |
10676 | char c = *input_line_pointer; | |
10677 | *input_line_pointer = 0; | |
10678 | as_bad (_("missing or invalid expression `%s'"), save); | |
10679 | *input_line_pointer = c; | |
10680 | } | |
b9519cfe L |
10681 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
10682 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
10683 | && exp->X_op != O_symbol) | |
10684 | { | |
10685 | char c = *input_line_pointer; | |
10686 | *input_line_pointer = 0; | |
10687 | as_bad (_("invalid PLT expression `%s'"), save); | |
10688 | *input_line_pointer = c; | |
10689 | } | |
f3c180ae AM |
10690 | } |
10691 | } | |
10692 | else | |
10693 | expression (exp); | |
ee86248c JB |
10694 | |
10695 | intel_syntax = -intel_syntax; | |
10696 | ||
10697 | if (intel_syntax) | |
10698 | i386_intel_simplify (exp); | |
2748c1b1 L |
10699 | #else |
10700 | expression (exp); | |
10701 | #endif | |
62ebcb5c | 10702 | |
a442cac5 JB |
10703 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ |
10704 | if (size == 4 && exp->X_op == O_constant && !object_64bit) | |
10705 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
10706 | ||
62ebcb5c | 10707 | return got_reloc; |
f3c180ae | 10708 | } |
f3c180ae | 10709 | |
9f32dd5b L |
10710 | static void |
10711 | signed_cons (int size) | |
6482c264 | 10712 | { |
a442cac5 | 10713 | if (object_64bit) |
d182319b JB |
10714 | cons_sign = 1; |
10715 | cons (size); | |
10716 | cons_sign = -1; | |
6482c264 NC |
10717 | } |
10718 | ||
d182319b | 10719 | #ifdef TE_PE |
6482c264 | 10720 | static void |
7016a5d5 | 10721 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
10722 | { |
10723 | expressionS exp; | |
10724 | ||
10725 | do | |
10726 | { | |
10727 | expression (&exp); | |
10728 | if (exp.X_op == O_symbol) | |
10729 | exp.X_op = O_secrel; | |
10730 | ||
10731 | emit_expr (&exp, 4); | |
10732 | } | |
10733 | while (*input_line_pointer++ == ','); | |
10734 | ||
10735 | input_line_pointer--; | |
10736 | demand_empty_rest_of_line (); | |
10737 | } | |
145667f8 MH |
10738 | |
10739 | static void | |
10740 | pe_directive_secidx (int dummy ATTRIBUTE_UNUSED) | |
10741 | { | |
10742 | expressionS exp; | |
10743 | ||
10744 | do | |
10745 | { | |
10746 | expression (&exp); | |
10747 | if (exp.X_op == O_symbol) | |
10748 | exp.X_op = O_secidx; | |
10749 | ||
10750 | emit_expr (&exp, 2); | |
10751 | } | |
10752 | while (*input_line_pointer++ == ','); | |
10753 | ||
10754 | input_line_pointer--; | |
10755 | demand_empty_rest_of_line (); | |
10756 | } | |
6482c264 NC |
10757 | #endif |
10758 | ||
7063667e JB |
10759 | /* Handle Rounding Control / SAE specifiers. */ |
10760 | ||
10761 | static char * | |
10762 | RC_SAE_specifier (const char *pstr) | |
10763 | { | |
10764 | unsigned int j; | |
10765 | ||
10766 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
10767 | { | |
10768 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
10769 | { | |
10770 | if (i.rounding.type != rc_none) | |
10771 | { | |
10772 | as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name); | |
10773 | return NULL; | |
10774 | } | |
10775 | ||
10776 | i.rounding.type = RC_NamesTable[j].type; | |
10777 | ||
10778 | return (char *)(pstr + RC_NamesTable[j].len); | |
10779 | } | |
10780 | } | |
10781 | ||
10782 | return NULL; | |
10783 | } | |
10784 | ||
43234a1e L |
10785 | /* Handle Vector operations. */ |
10786 | ||
10787 | static char * | |
f70c6814 | 10788 | check_VecOperations (char *op_string) |
43234a1e L |
10789 | { |
10790 | const reg_entry *mask; | |
10791 | const char *saved; | |
10792 | char *end_op; | |
10793 | ||
f70c6814 | 10794 | while (*op_string) |
43234a1e L |
10795 | { |
10796 | saved = op_string; | |
10797 | if (*op_string == '{') | |
10798 | { | |
10799 | op_string++; | |
10800 | ||
10801 | /* Check broadcasts. */ | |
d34049e8 | 10802 | if (startswith (op_string, "1to")) |
43234a1e | 10803 | { |
5273a3cd | 10804 | unsigned int bcst_type; |
43234a1e | 10805 | |
5273a3cd | 10806 | if (i.broadcast.type) |
43234a1e L |
10807 | goto duplicated_vec_op; |
10808 | ||
10809 | op_string += 3; | |
10810 | if (*op_string == '8') | |
8e6e0792 | 10811 | bcst_type = 8; |
b28d1bda | 10812 | else if (*op_string == '4') |
8e6e0792 | 10813 | bcst_type = 4; |
b28d1bda | 10814 | else if (*op_string == '2') |
8e6e0792 | 10815 | bcst_type = 2; |
43234a1e L |
10816 | else if (*op_string == '1' |
10817 | && *(op_string+1) == '6') | |
10818 | { | |
8e6e0792 | 10819 | bcst_type = 16; |
43234a1e L |
10820 | op_string++; |
10821 | } | |
0cc78721 CL |
10822 | else if (*op_string == '3' |
10823 | && *(op_string+1) == '2') | |
10824 | { | |
10825 | bcst_type = 32; | |
10826 | op_string++; | |
10827 | } | |
43234a1e L |
10828 | else |
10829 | { | |
10830 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
10831 | return NULL; | |
10832 | } | |
10833 | op_string++; | |
10834 | ||
5273a3cd JB |
10835 | i.broadcast.type = bcst_type; |
10836 | i.broadcast.operand = this_operand; | |
43234a1e L |
10837 | } |
10838 | /* Check masking operation. */ | |
10839 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
10840 | { | |
8a6fb3f9 JB |
10841 | if (mask == &bad_reg) |
10842 | return NULL; | |
10843 | ||
43234a1e | 10844 | /* k0 can't be used for write mask. */ |
f74a6307 | 10845 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 10846 | { |
6d2cd6b2 JB |
10847 | as_bad (_("`%s%s' can't be used for write mask"), |
10848 | register_prefix, mask->reg_name); | |
43234a1e L |
10849 | return NULL; |
10850 | } | |
10851 | ||
6225c532 | 10852 | if (!i.mask.reg) |
43234a1e | 10853 | { |
6225c532 JB |
10854 | i.mask.reg = mask; |
10855 | i.mask.operand = this_operand; | |
43234a1e | 10856 | } |
6225c532 JB |
10857 | else if (i.mask.reg->reg_num) |
10858 | goto duplicated_vec_op; | |
43234a1e L |
10859 | else |
10860 | { | |
6225c532 | 10861 | i.mask.reg = mask; |
43234a1e L |
10862 | |
10863 | /* Only "{z}" is allowed here. No need to check | |
10864 | zeroing mask explicitly. */ | |
6225c532 | 10865 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10866 | { |
10867 | as_bad (_("invalid write mask `%s'"), saved); | |
10868 | return NULL; | |
10869 | } | |
10870 | } | |
10871 | ||
10872 | op_string = end_op; | |
10873 | } | |
10874 | /* Check zeroing-flag for masking operation. */ | |
10875 | else if (*op_string == 'z') | |
10876 | { | |
6225c532 | 10877 | if (!i.mask.reg) |
43234a1e | 10878 | { |
6225c532 JB |
10879 | i.mask.reg = reg_k0; |
10880 | i.mask.zeroing = 1; | |
10881 | i.mask.operand = this_operand; | |
43234a1e L |
10882 | } |
10883 | else | |
10884 | { | |
6225c532 | 10885 | if (i.mask.zeroing) |
43234a1e L |
10886 | { |
10887 | duplicated_vec_op: | |
10888 | as_bad (_("duplicated `%s'"), saved); | |
10889 | return NULL; | |
10890 | } | |
10891 | ||
6225c532 | 10892 | i.mask.zeroing = 1; |
43234a1e L |
10893 | |
10894 | /* Only "{%k}" is allowed here. No need to check mask | |
10895 | register explicitly. */ | |
6225c532 | 10896 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10897 | { |
10898 | as_bad (_("invalid zeroing-masking `%s'"), | |
10899 | saved); | |
10900 | return NULL; | |
10901 | } | |
10902 | } | |
10903 | ||
10904 | op_string++; | |
10905 | } | |
7063667e JB |
10906 | else if (intel_syntax |
10907 | && (op_string = RC_SAE_specifier (op_string)) != NULL) | |
10908 | i.rounding.modifier = true; | |
43234a1e L |
10909 | else |
10910 | goto unknown_vec_op; | |
10911 | ||
10912 | if (*op_string != '}') | |
10913 | { | |
10914 | as_bad (_("missing `}' in `%s'"), saved); | |
10915 | return NULL; | |
10916 | } | |
10917 | op_string++; | |
0ba3a731 L |
10918 | |
10919 | /* Strip whitespace since the addition of pseudo prefixes | |
10920 | changed how the scrubber treats '{'. */ | |
10921 | if (is_space_char (*op_string)) | |
10922 | ++op_string; | |
10923 | ||
43234a1e L |
10924 | continue; |
10925 | } | |
10926 | unknown_vec_op: | |
10927 | /* We don't know this one. */ | |
10928 | as_bad (_("unknown vector operation: `%s'"), saved); | |
10929 | return NULL; | |
10930 | } | |
10931 | ||
6225c532 | 10932 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
10933 | { |
10934 | as_bad (_("zeroing-masking only allowed with write mask")); | |
10935 | return NULL; | |
10936 | } | |
10937 | ||
43234a1e L |
10938 | return op_string; |
10939 | } | |
10940 | ||
252b5132 | 10941 | static int |
70e41ade | 10942 | i386_immediate (char *imm_start) |
252b5132 RH |
10943 | { |
10944 | char *save_input_line_pointer; | |
f3c180ae | 10945 | char *gotfree_input_line; |
252b5132 | 10946 | segT exp_seg = 0; |
47926f60 | 10947 | expressionS *exp; |
40fb9820 L |
10948 | i386_operand_type types; |
10949 | ||
0dfbf9d7 | 10950 | operand_type_set (&types, ~0); |
252b5132 RH |
10951 | |
10952 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
10953 | { | |
31b2323c L |
10954 | as_bad (_("at most %d immediate operands are allowed"), |
10955 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
10956 | return 0; |
10957 | } | |
10958 | ||
10959 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 10960 | i.op[this_operand].imms = exp; |
252b5132 RH |
10961 | |
10962 | if (is_space_char (*imm_start)) | |
10963 | ++imm_start; | |
10964 | ||
10965 | save_input_line_pointer = input_line_pointer; | |
10966 | input_line_pointer = imm_start; | |
10967 | ||
d258b828 | 10968 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10969 | if (gotfree_input_line) |
10970 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
10971 | |
10972 | exp_seg = expression (exp); | |
10973 | ||
83183c0c | 10974 | SKIP_WHITESPACE (); |
252b5132 | 10975 | if (*input_line_pointer) |
f3c180ae | 10976 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
10977 | |
10978 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 10979 | if (gotfree_input_line) |
ee86248c JB |
10980 | { |
10981 | free (gotfree_input_line); | |
10982 | ||
9aac24b1 | 10983 | if (exp->X_op == O_constant) |
ee86248c JB |
10984 | exp->X_op = O_illegal; |
10985 | } | |
10986 | ||
9aac24b1 JB |
10987 | if (exp_seg == reg_section) |
10988 | { | |
10989 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
10990 | return 0; | |
10991 | } | |
10992 | ||
ee86248c JB |
10993 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
10994 | } | |
252b5132 | 10995 | |
ee86248c JB |
10996 | static int |
10997 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10998 | i386_operand_type types, const char *imm_start) | |
10999 | { | |
11000 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 11001 | { |
313c53d1 L |
11002 | if (imm_start) |
11003 | as_bad (_("missing or invalid immediate expression `%s'"), | |
11004 | imm_start); | |
3992d3b7 | 11005 | return 0; |
252b5132 | 11006 | } |
3e73aa7c | 11007 | else if (exp->X_op == O_constant) |
252b5132 | 11008 | { |
47926f60 | 11009 | /* Size it properly later. */ |
40fb9820 | 11010 | i.types[this_operand].bitfield.imm64 = 1; |
a442cac5 JB |
11011 | |
11012 | /* If not 64bit, sign/zero extend val, to account for wraparound | |
11013 | when !BFD64. */ | |
11014 | if (flag_code != CODE_64BIT) | |
11015 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
252b5132 | 11016 | } |
4c63da97 | 11017 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 11018 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 11019 | && exp_seg != absolute_section |
47926f60 | 11020 | && exp_seg != text_section |
24eab124 AM |
11021 | && exp_seg != data_section |
11022 | && exp_seg != bss_section | |
11023 | && exp_seg != undefined_section | |
f86103b7 | 11024 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 11025 | { |
d0b47220 | 11026 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
11027 | return 0; |
11028 | } | |
11029 | #endif | |
11030 | else | |
11031 | { | |
11032 | /* This is an address. The size of the address will be | |
24eab124 | 11033 | determined later, depending on destination register, |
3e73aa7c | 11034 | suffix, or the default for the section. */ |
40fb9820 L |
11035 | i.types[this_operand].bitfield.imm8 = 1; |
11036 | i.types[this_operand].bitfield.imm16 = 1; | |
11037 | i.types[this_operand].bitfield.imm32 = 1; | |
11038 | i.types[this_operand].bitfield.imm32s = 1; | |
11039 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
11040 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
11041 | types); | |
252b5132 RH |
11042 | } |
11043 | ||
11044 | return 1; | |
11045 | } | |
11046 | ||
551c1ca1 | 11047 | static char * |
e3bb37b5 | 11048 | i386_scale (char *scale) |
252b5132 | 11049 | { |
551c1ca1 AM |
11050 | offsetT val; |
11051 | char *save = input_line_pointer; | |
252b5132 | 11052 | |
551c1ca1 AM |
11053 | input_line_pointer = scale; |
11054 | val = get_absolute_expression (); | |
11055 | ||
11056 | switch (val) | |
252b5132 | 11057 | { |
551c1ca1 | 11058 | case 1: |
252b5132 RH |
11059 | i.log2_scale_factor = 0; |
11060 | break; | |
551c1ca1 | 11061 | case 2: |
252b5132 RH |
11062 | i.log2_scale_factor = 1; |
11063 | break; | |
551c1ca1 | 11064 | case 4: |
252b5132 RH |
11065 | i.log2_scale_factor = 2; |
11066 | break; | |
551c1ca1 | 11067 | case 8: |
252b5132 RH |
11068 | i.log2_scale_factor = 3; |
11069 | break; | |
11070 | default: | |
a724f0f4 JB |
11071 | { |
11072 | char sep = *input_line_pointer; | |
11073 | ||
11074 | *input_line_pointer = '\0'; | |
11075 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
11076 | scale); | |
11077 | *input_line_pointer = sep; | |
11078 | input_line_pointer = save; | |
11079 | return NULL; | |
11080 | } | |
252b5132 | 11081 | } |
29b0f896 | 11082 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
11083 | { |
11084 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 11085 | 1 << i.log2_scale_factor); |
252b5132 | 11086 | i.log2_scale_factor = 0; |
252b5132 | 11087 | } |
551c1ca1 AM |
11088 | scale = input_line_pointer; |
11089 | input_line_pointer = save; | |
11090 | return scale; | |
252b5132 RH |
11091 | } |
11092 | ||
252b5132 | 11093 | static int |
e3bb37b5 | 11094 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 11095 | { |
29b0f896 | 11096 | expressionS *exp; |
252b5132 RH |
11097 | segT exp_seg = 0; |
11098 | char *save_input_line_pointer; | |
f3c180ae | 11099 | char *gotfree_input_line; |
40fb9820 L |
11100 | int override; |
11101 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 11102 | int ret; |
252b5132 | 11103 | |
31b2323c L |
11104 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
11105 | { | |
11106 | as_bad (_("at most %d displacement operands are allowed"), | |
11107 | MAX_MEMORY_OPERANDS); | |
11108 | return 0; | |
11109 | } | |
11110 | ||
0dfbf9d7 | 11111 | operand_type_set (&bigdisp, 0); |
6f2f06be | 11112 | if (i.jumpabsolute |
48bcea9f | 11113 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
11114 | || (current_templates->start->opcode_modifier.jump != JUMP |
11115 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 11116 | { |
48bcea9f | 11117 | i386_addressing_mode (); |
e05278af | 11118 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
11119 | if (flag_code == CODE_64BIT) |
11120 | { | |
a775efc8 | 11121 | bigdisp.bitfield.disp32 = 1; |
40fb9820 | 11122 | if (!override) |
a775efc8 | 11123 | bigdisp.bitfield.disp64 = 1; |
40fb9820 L |
11124 | } |
11125 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 11126 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
11127 | else |
11128 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
11129 | } |
11130 | else | |
11131 | { | |
376cd056 JB |
11132 | /* For PC-relative branches, the width of the displacement may be |
11133 | dependent upon data size, but is never dependent upon address size. | |
11134 | Also make sure to not unintentionally match against a non-PC-relative | |
11135 | branch template. */ | |
11136 | static templates aux_templates; | |
11137 | const insn_template *t = current_templates->start; | |
5b7c81bd | 11138 | bool has_intel64 = false; |
376cd056 JB |
11139 | |
11140 | aux_templates.start = t; | |
11141 | while (++t < current_templates->end) | |
11142 | { | |
11143 | if (t->opcode_modifier.jump | |
11144 | != current_templates->start->opcode_modifier.jump) | |
11145 | break; | |
4b5aaf5f | 11146 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 11147 | has_intel64 = true; |
376cd056 JB |
11148 | } |
11149 | if (t < current_templates->end) | |
11150 | { | |
11151 | aux_templates.end = t; | |
11152 | current_templates = &aux_templates; | |
11153 | } | |
11154 | ||
e05278af | 11155 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
11156 | if (flag_code == CODE_64BIT) |
11157 | { | |
376cd056 JB |
11158 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
11159 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
11160 | bigdisp.bitfield.disp16 = 1; |
11161 | else | |
a775efc8 | 11162 | bigdisp.bitfield.disp32 = 1; |
40fb9820 L |
11163 | } |
11164 | else | |
e05278af JB |
11165 | { |
11166 | if (!override) | |
11167 | override = (i.suffix == (flag_code != CODE_16BIT | |
11168 | ? WORD_MNEM_SUFFIX | |
11169 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
11170 | bigdisp.bitfield.disp32 = 1; |
11171 | if ((flag_code == CODE_16BIT) ^ override) | |
11172 | { | |
11173 | bigdisp.bitfield.disp32 = 0; | |
11174 | bigdisp.bitfield.disp16 = 1; | |
11175 | } | |
e05278af | 11176 | } |
e05278af | 11177 | } |
c6fb90c8 L |
11178 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
11179 | bigdisp); | |
252b5132 RH |
11180 | |
11181 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 11182 | i.op[this_operand].disps = exp; |
252b5132 RH |
11183 | i.disp_operands++; |
11184 | save_input_line_pointer = input_line_pointer; | |
11185 | input_line_pointer = disp_start; | |
11186 | END_STRING_AND_SAVE (disp_end); | |
11187 | ||
11188 | #ifndef GCC_ASM_O_HACK | |
11189 | #define GCC_ASM_O_HACK 0 | |
11190 | #endif | |
11191 | #if GCC_ASM_O_HACK | |
11192 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 11193 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 11194 | && displacement_string_end[-1] == '+') |
252b5132 RH |
11195 | { |
11196 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
11197 | constraint within gcc asm statements. |
11198 | For instance: | |
11199 | ||
11200 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
11201 | __asm__ __volatile__ ( \ | |
11202 | "movw %w2,%0\n\t" \ | |
11203 | "movw %w1,2+%0\n\t" \ | |
11204 | "rorl $16,%1\n\t" \ | |
11205 | "movb %b1,4+%0\n\t" \ | |
11206 | "movb %4,5+%0\n\t" \ | |
11207 | "movb $0,6+%0\n\t" \ | |
11208 | "movb %h1,7+%0\n\t" \ | |
11209 | "rorl $16,%1" \ | |
11210 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
11211 | ||
11212 | This works great except that the output assembler ends | |
11213 | up looking a bit weird if it turns out that there is | |
11214 | no offset. You end up producing code that looks like: | |
11215 | ||
11216 | #APP | |
11217 | movw $235,(%eax) | |
11218 | movw %dx,2+(%eax) | |
11219 | rorl $16,%edx | |
11220 | movb %dl,4+(%eax) | |
11221 | movb $137,5+(%eax) | |
11222 | movb $0,6+(%eax) | |
11223 | movb %dh,7+(%eax) | |
11224 | rorl $16,%edx | |
11225 | #NO_APP | |
11226 | ||
47926f60 | 11227 | So here we provide the missing zero. */ |
24eab124 AM |
11228 | |
11229 | *displacement_string_end = '0'; | |
252b5132 RH |
11230 | } |
11231 | #endif | |
d258b828 | 11232 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
11233 | if (gotfree_input_line) |
11234 | input_line_pointer = gotfree_input_line; | |
252b5132 | 11235 | |
24eab124 | 11236 | exp_seg = expression (exp); |
252b5132 | 11237 | |
636c26b0 AM |
11238 | SKIP_WHITESPACE (); |
11239 | if (*input_line_pointer) | |
11240 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
11241 | #if GCC_ASM_O_HACK | |
11242 | RESTORE_END_STRING (disp_end + 1); | |
11243 | #endif | |
636c26b0 | 11244 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 11245 | if (gotfree_input_line) |
ee86248c JB |
11246 | { |
11247 | free (gotfree_input_line); | |
11248 | ||
11249 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
11250 | exp->X_op = O_illegal; | |
11251 | } | |
11252 | ||
11253 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
11254 | ||
11255 | RESTORE_END_STRING (disp_end); | |
11256 | ||
11257 | return ret; | |
11258 | } | |
11259 | ||
11260 | static int | |
11261 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
11262 | i386_operand_type types, const char *disp_start) | |
11263 | { | |
ee86248c | 11264 | int ret = 1; |
636c26b0 | 11265 | |
24eab124 AM |
11266 | /* We do this to make sure that the section symbol is in |
11267 | the symbol table. We will ultimately change the relocation | |
47926f60 | 11268 | to be relative to the beginning of the section. */ |
1ae12ab7 | 11269 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
11270 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
11271 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 11272 | { |
636c26b0 | 11273 | if (exp->X_op != O_symbol) |
3992d3b7 | 11274 | goto inv_disp; |
636c26b0 | 11275 | |
e5cb08ac | 11276 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
11277 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
11278 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 11279 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
11280 | exp->X_op = O_subtract; |
11281 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 11282 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 11283 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
11284 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
11285 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 11286 | else |
29b0f896 | 11287 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 11288 | } |
252b5132 | 11289 | |
3992d3b7 AM |
11290 | else if (exp->X_op == O_absent |
11291 | || exp->X_op == O_illegal | |
ee86248c | 11292 | || exp->X_op == O_big) |
2daf4fd8 | 11293 | { |
3992d3b7 AM |
11294 | inv_disp: |
11295 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 11296 | disp_start); |
3992d3b7 | 11297 | ret = 0; |
2daf4fd8 AM |
11298 | } |
11299 | ||
a50187b2 JB |
11300 | else if (exp->X_op == O_constant) |
11301 | { | |
11302 | /* Sizing gets taken care of by optimize_disp(). | |
11303 | ||
11304 | If not 64bit, sign/zero extend val, to account for wraparound | |
11305 | when !BFD64. */ | |
11306 | if (flag_code != CODE_64BIT) | |
11307 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); | |
11308 | } | |
11309 | ||
4c63da97 | 11310 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
a50187b2 | 11311 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
3992d3b7 AM |
11312 | && exp_seg != absolute_section |
11313 | && exp_seg != text_section | |
11314 | && exp_seg != data_section | |
11315 | && exp_seg != bss_section | |
11316 | && exp_seg != undefined_section | |
11317 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 11318 | { |
d0b47220 | 11319 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 11320 | ret = 0; |
24eab124 | 11321 | } |
252b5132 | 11322 | #endif |
3956db08 | 11323 | |
a50187b2 | 11324 | else if (current_templates->start->opcode_modifier.jump == JUMP_BYTE) |
48bcea9f JB |
11325 | i.types[this_operand].bitfield.disp8 = 1; |
11326 | ||
40fb9820 | 11327 | /* Check if this is a displacement only operand. */ |
02b83698 JB |
11328 | if (!i.types[this_operand].bitfield.baseindex) |
11329 | i.types[this_operand] = | |
11330 | operand_type_or (operand_type_and_not (i.types[this_operand], anydisp), | |
11331 | operand_type_and (i.types[this_operand], types)); | |
3956db08 | 11332 | |
3992d3b7 | 11333 | return ret; |
252b5132 RH |
11334 | } |
11335 | ||
2abc2bec JB |
11336 | /* Return the active addressing mode, taking address override and |
11337 | registers forming the address into consideration. Update the | |
11338 | address override prefix if necessary. */ | |
47926f60 | 11339 | |
2abc2bec JB |
11340 | static enum flag_code |
11341 | i386_addressing_mode (void) | |
252b5132 | 11342 | { |
be05d201 L |
11343 | enum flag_code addr_mode; |
11344 | ||
11345 | if (i.prefix[ADDR_PREFIX]) | |
11346 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 JB |
11347 | else if (flag_code == CODE_16BIT |
11348 | && current_templates->start->cpu_flags.bitfield.cpumpx | |
11349 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic | |
11350 | from md_assemble() by "is not a valid base/index expression" | |
11351 | when there is a base and/or index. */ | |
11352 | && !i.types[this_operand].bitfield.baseindex) | |
11353 | { | |
11354 | /* MPX insn memory operands with neither base nor index must be forced | |
11355 | to use 32-bit addressing in 16-bit mode. */ | |
11356 | addr_mode = CODE_32BIT; | |
11357 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11358 | ++i.prefixes; | |
11359 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
11360 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
11361 | } | |
be05d201 L |
11362 | else |
11363 | { | |
11364 | addr_mode = flag_code; | |
11365 | ||
24eab124 | 11366 | #if INFER_ADDR_PREFIX |
be05d201 L |
11367 | if (i.mem_operands == 0) |
11368 | { | |
11369 | /* Infer address prefix from the first memory operand. */ | |
11370 | const reg_entry *addr_reg = i.base_reg; | |
11371 | ||
11372 | if (addr_reg == NULL) | |
11373 | addr_reg = i.index_reg; | |
eecb386c | 11374 | |
be05d201 L |
11375 | if (addr_reg) |
11376 | { | |
e968fc9b | 11377 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
11378 | addr_mode = CODE_32BIT; |
11379 | else if (flag_code != CODE_64BIT | |
dc821c5f | 11380 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
11381 | addr_mode = CODE_16BIT; |
11382 | ||
11383 | if (addr_mode != flag_code) | |
11384 | { | |
11385 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11386 | i.prefixes += 1; | |
11387 | /* Change the size of any displacement too. At most one | |
11388 | of Disp16 or Disp32 is set. | |
11389 | FIXME. There doesn't seem to be any real need for | |
11390 | separate Disp16 and Disp32 flags. The same goes for | |
11391 | Imm16 and Imm32. Removing them would probably clean | |
11392 | up the code quite a lot. */ | |
11393 | if (flag_code != CODE_64BIT | |
11394 | && (i.types[this_operand].bitfield.disp16 | |
11395 | || i.types[this_operand].bitfield.disp32)) | |
05909f23 JB |
11396 | { |
11397 | static const i386_operand_type disp16_32 = { | |
11398 | .bitfield = { .disp16 = 1, .disp32 = 1 } | |
11399 | }; | |
11400 | ||
11401 | i.types[this_operand] | |
11402 | = operand_type_xor (i.types[this_operand], disp16_32); | |
11403 | } | |
be05d201 L |
11404 | } |
11405 | } | |
11406 | } | |
24eab124 | 11407 | #endif |
be05d201 L |
11408 | } |
11409 | ||
2abc2bec JB |
11410 | return addr_mode; |
11411 | } | |
11412 | ||
11413 | /* Make sure the memory operand we've been dealt is valid. | |
11414 | Return 1 on success, 0 on a failure. */ | |
11415 | ||
11416 | static int | |
11417 | i386_index_check (const char *operand_string) | |
11418 | { | |
11419 | const char *kind = "base/index"; | |
11420 | enum flag_code addr_mode = i386_addressing_mode (); | |
77a19f0e | 11421 | const insn_template *t = current_templates->end - 1; |
2abc2bec | 11422 | |
77a19f0e | 11423 | if (t->opcode_modifier.isstring) |
fc0763e6 JB |
11424 | { |
11425 | /* Memory operands of string insns are special in that they only allow | |
11426 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
11427 | const reg_entry *expected_reg; |
11428 | static const char *di_si[][2] = | |
11429 | { | |
11430 | { "esi", "edi" }, | |
11431 | { "si", "di" }, | |
11432 | { "rsi", "rdi" } | |
11433 | }; | |
11434 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
11435 | |
11436 | kind = "string address"; | |
11437 | ||
a152332d | 11438 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 11439 | { |
77a19f0e | 11440 | int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0; |
51c8edf6 | 11441 | int op = 0; |
fc0763e6 | 11442 | |
77a19f0e | 11443 | if (!t->operand_types[0].bitfield.baseindex |
fc0763e6 | 11444 | || ((!i.mem_operands != !intel_syntax) |
77a19f0e | 11445 | && t->operand_types[1].bitfield.baseindex)) |
51c8edf6 | 11446 | op = 1; |
fe0e921f AM |
11447 | expected_reg |
11448 | = (const reg_entry *) str_hash_find (reg_hash, | |
11449 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
11450 | } |
11451 | else | |
fe0e921f AM |
11452 | expected_reg |
11453 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 11454 | |
be05d201 L |
11455 | if (i.base_reg != expected_reg |
11456 | || i.index_reg | |
fc0763e6 | 11457 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 11458 | { |
be05d201 L |
11459 | /* The second memory operand must have the same size as |
11460 | the first one. */ | |
11461 | if (i.mem_operands | |
11462 | && i.base_reg | |
11463 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 11464 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 11465 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
11466 | ? i.base_reg->reg_type.bitfield.dword |
11467 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
11468 | goto bad_address; |
11469 | ||
fc0763e6 JB |
11470 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
11471 | operand_string, | |
11472 | intel_syntax ? '[' : '(', | |
11473 | register_prefix, | |
be05d201 | 11474 | expected_reg->reg_name, |
fc0763e6 | 11475 | intel_syntax ? ']' : ')'); |
be05d201 | 11476 | return 1; |
fc0763e6 | 11477 | } |
be05d201 L |
11478 | else |
11479 | return 1; | |
11480 | ||
dc1e8a47 | 11481 | bad_address: |
be05d201 L |
11482 | as_bad (_("`%s' is not a valid %s expression"), |
11483 | operand_string, kind); | |
11484 | return 0; | |
3e73aa7c JH |
11485 | } |
11486 | else | |
11487 | { | |
77a19f0e JB |
11488 | t = current_templates->start; |
11489 | ||
be05d201 L |
11490 | if (addr_mode != CODE_16BIT) |
11491 | { | |
11492 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
11493 | if (i.disp_encoding == disp_encoding_16bit) |
11494 | { | |
11495 | bad_disp: | |
11496 | as_bad (_("invalid `%s' prefix"), | |
11497 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
11498 | return 0; | |
11499 | } | |
11500 | ||
be05d201 | 11501 | if ((i.base_reg |
e968fc9b JB |
11502 | && ((addr_mode == CODE_64BIT |
11503 | ? !i.base_reg->reg_type.bitfield.qword | |
11504 | : !i.base_reg->reg_type.bitfield.dword) | |
11505 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
11506 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 11507 | || (i.index_reg |
1b54b8d7 JB |
11508 | && !i.index_reg->reg_type.bitfield.xmmword |
11509 | && !i.index_reg->reg_type.bitfield.ymmword | |
11510 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 11511 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
11512 | ? !i.index_reg->reg_type.bitfield.qword |
11513 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
11514 | || !i.index_reg->reg_type.bitfield.baseindex))) |
11515 | goto bad_address; | |
8178be5b | 11516 | |
260cd341 | 11517 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
7fc69528 JB |
11518 | if (t->mnem_off == MN_bndmk |
11519 | || t->mnem_off == MN_bndldx | |
11520 | || t->mnem_off == MN_bndstx | |
a152332d | 11521 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
11522 | { |
11523 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 11524 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
11525 | { |
11526 | as_bad (_("`%s' cannot be used here"), operand_string); | |
11527 | return 0; | |
11528 | } | |
11529 | ||
11530 | /* bndldx and bndstx ignore their scale factor. */ | |
7fc69528 | 11531 | if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx) |
8178be5b JB |
11532 | && i.log2_scale_factor) |
11533 | as_warn (_("register scaling is being ignored here")); | |
11534 | } | |
be05d201 L |
11535 | } |
11536 | else | |
3e73aa7c | 11537 | { |
be05d201 | 11538 | /* 16-bit checks. */ |
41eb8e88 L |
11539 | if (i.disp_encoding == disp_encoding_32bit) |
11540 | goto bad_disp; | |
11541 | ||
3e73aa7c | 11542 | if ((i.base_reg |
dc821c5f | 11543 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 11544 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 11545 | || (i.index_reg |
dc821c5f | 11546 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 11547 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
11548 | || !(i.base_reg |
11549 | && i.base_reg->reg_num < 6 | |
11550 | && i.index_reg->reg_num >= 6 | |
11551 | && i.log2_scale_factor == 0)))) | |
be05d201 | 11552 | goto bad_address; |
3e73aa7c JH |
11553 | } |
11554 | } | |
be05d201 | 11555 | return 1; |
24eab124 | 11556 | } |
252b5132 | 11557 | |
43234a1e L |
11558 | /* Handle vector immediates. */ |
11559 | ||
11560 | static int | |
11561 | RC_SAE_immediate (const char *imm_start) | |
11562 | { | |
43234a1e | 11563 | const char *pstr = imm_start; |
43234a1e L |
11564 | |
11565 | if (*pstr != '{') | |
11566 | return 0; | |
11567 | ||
7063667e JB |
11568 | pstr = RC_SAE_specifier (pstr + 1); |
11569 | if (pstr == NULL) | |
43234a1e L |
11570 | return 0; |
11571 | ||
11572 | if (*pstr++ != '}') | |
11573 | { | |
11574 | as_bad (_("Missing '}': '%s'"), imm_start); | |
11575 | return 0; | |
11576 | } | |
11577 | /* RC/SAE immediate string should contain nothing more. */; | |
11578 | if (*pstr != 0) | |
11579 | { | |
11580 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
11581 | return 0; | |
11582 | } | |
11583 | ||
cf665fee JB |
11584 | /* Internally this doesn't count as an operand. */ |
11585 | --i.operands; | |
43234a1e | 11586 | |
43234a1e L |
11587 | return 1; |
11588 | } | |
11589 | ||
9d299bea JB |
11590 | static INLINE bool starts_memory_operand (char c) |
11591 | { | |
014fbcda | 11592 | return ISDIGIT (c) |
9d299bea | 11593 | || is_identifier_char (c) |
014fbcda | 11594 | || strchr ("([\"+-!~", c); |
9d299bea JB |
11595 | } |
11596 | ||
fc0763e6 | 11597 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 11598 | on error. */ |
252b5132 | 11599 | |
252b5132 | 11600 | static int |
a7619375 | 11601 | i386_att_operand (char *operand_string) |
252b5132 | 11602 | { |
af6bdddf AM |
11603 | const reg_entry *r; |
11604 | char *end_op; | |
24eab124 | 11605 | char *op_string = operand_string; |
252b5132 | 11606 | |
24eab124 | 11607 | if (is_space_char (*op_string)) |
252b5132 RH |
11608 | ++op_string; |
11609 | ||
24eab124 | 11610 | /* We check for an absolute prefix (differentiating, |
47926f60 | 11611 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
11612 | if (*op_string == ABSOLUTE_PREFIX) |
11613 | { | |
11614 | ++op_string; | |
11615 | if (is_space_char (*op_string)) | |
11616 | ++op_string; | |
5b7c81bd | 11617 | i.jumpabsolute = true; |
24eab124 | 11618 | } |
252b5132 | 11619 | |
47926f60 | 11620 | /* Check if operand is a register. */ |
4d1bb795 | 11621 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 11622 | { |
40fb9820 L |
11623 | i386_operand_type temp; |
11624 | ||
8a6fb3f9 JB |
11625 | if (r == &bad_reg) |
11626 | return 0; | |
11627 | ||
24eab124 AM |
11628 | /* Check for a segment override by searching for ':' after a |
11629 | segment register. */ | |
11630 | op_string = end_op; | |
11631 | if (is_space_char (*op_string)) | |
11632 | ++op_string; | |
00cee14f | 11633 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 11634 | { |
5e042380 | 11635 | i.seg[i.mem_operands] = r; |
252b5132 | 11636 | |
24eab124 | 11637 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
11638 | ++op_string; |
11639 | if (is_space_char (*op_string)) | |
24eab124 | 11640 | ++op_string; |
252b5132 | 11641 | |
47926f60 | 11642 | /* Handle case of %es:*foo. */ |
c8d541e2 | 11643 | if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX) |
24eab124 AM |
11644 | { |
11645 | ++op_string; | |
11646 | if (is_space_char (*op_string)) | |
11647 | ++op_string; | |
5b7c81bd | 11648 | i.jumpabsolute = true; |
24eab124 | 11649 | } |
c8d541e2 | 11650 | |
9d299bea | 11651 | if (!starts_memory_operand (*op_string)) |
c8d541e2 JB |
11652 | { |
11653 | as_bad (_("bad memory operand `%s'"), op_string); | |
11654 | return 0; | |
11655 | } | |
24eab124 AM |
11656 | goto do_memory_reference; |
11657 | } | |
43234a1e L |
11658 | |
11659 | /* Handle vector operations. */ | |
11660 | if (*op_string == '{') | |
11661 | { | |
f70c6814 | 11662 | op_string = check_VecOperations (op_string); |
43234a1e L |
11663 | if (op_string == NULL) |
11664 | return 0; | |
11665 | } | |
11666 | ||
24eab124 AM |
11667 | if (*op_string) |
11668 | { | |
d0b47220 | 11669 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
11670 | return 0; |
11671 | } | |
40fb9820 L |
11672 | temp = r->reg_type; |
11673 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
11674 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
11675 | temp); | |
7d5e4556 | 11676 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 11677 | i.op[this_operand].regs = r; |
24eab124 | 11678 | i.reg_operands++; |
cf665fee JB |
11679 | |
11680 | /* A GPR may follow an RC or SAE immediate only if a (vector) register | |
11681 | operand was also present earlier on. */ | |
11682 | if (i.rounding.type != rc_none && temp.bitfield.class == Reg | |
11683 | && i.reg_operands == 1) | |
11684 | { | |
11685 | unsigned int j; | |
11686 | ||
11687 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j) | |
11688 | if (i.rounding.type == RC_NamesTable[j].type) | |
11689 | break; | |
11690 | as_bad (_("`%s': misplaced `{%s}'"), | |
76d3f746 | 11691 | insn_name (current_templates->start), RC_NamesTable[j].name); |
cf665fee JB |
11692 | return 0; |
11693 | } | |
24eab124 | 11694 | } |
af6bdddf AM |
11695 | else if (*op_string == REGISTER_PREFIX) |
11696 | { | |
11697 | as_bad (_("bad register name `%s'"), op_string); | |
11698 | return 0; | |
11699 | } | |
24eab124 | 11700 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 11701 | { |
24eab124 | 11702 | ++op_string; |
6f2f06be | 11703 | if (i.jumpabsolute) |
24eab124 | 11704 | { |
d0b47220 | 11705 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
11706 | return 0; |
11707 | } | |
11708 | if (!i386_immediate (op_string)) | |
11709 | return 0; | |
cf665fee JB |
11710 | if (i.rounding.type != rc_none) |
11711 | { | |
11712 | as_bad (_("`%s': RC/SAE operand must follow immediate operands"), | |
76d3f746 | 11713 | insn_name (current_templates->start)); |
cf665fee JB |
11714 | return 0; |
11715 | } | |
24eab124 | 11716 | } |
43234a1e L |
11717 | else if (RC_SAE_immediate (operand_string)) |
11718 | { | |
cf665fee JB |
11719 | /* If it is a RC or SAE immediate, do the necessary placement check: |
11720 | Only another immediate or a GPR may precede it. */ | |
11721 | if (i.mem_operands || i.reg_operands + i.imm_operands > 1 | |
11722 | || (i.reg_operands == 1 | |
11723 | && i.op[0].regs->reg_type.bitfield.class != Reg)) | |
11724 | { | |
11725 | as_bad (_("`%s': misplaced `%s'"), | |
76d3f746 | 11726 | insn_name (current_templates->start), operand_string); |
cf665fee JB |
11727 | return 0; |
11728 | } | |
43234a1e | 11729 | } |
9d299bea | 11730 | else if (starts_memory_operand (*op_string)) |
24eab124 | 11731 | { |
47926f60 | 11732 | /* This is a memory reference of some sort. */ |
af6bdddf | 11733 | char *base_string; |
252b5132 | 11734 | |
47926f60 | 11735 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
11736 | char *displacement_string_start; |
11737 | char *displacement_string_end; | |
252b5132 | 11738 | |
24eab124 | 11739 | do_memory_reference: |
24eab124 AM |
11740 | /* Check for base index form. We detect the base index form by |
11741 | looking for an ')' at the end of the operand, searching | |
11742 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
11743 | after the '('. */ | |
af6bdddf | 11744 | base_string = op_string + strlen (op_string); |
c3332e24 | 11745 | |
43234a1e | 11746 | /* Handle vector operations. */ |
6b5ba0d4 JB |
11747 | --base_string; |
11748 | if (is_space_char (*base_string)) | |
11749 | --base_string; | |
11750 | ||
11751 | if (*base_string == '}') | |
43234a1e | 11752 | { |
6b5ba0d4 JB |
11753 | char *vop_start = NULL; |
11754 | ||
11755 | while (base_string-- > op_string) | |
11756 | { | |
11757 | if (*base_string == '"') | |
11758 | break; | |
11759 | if (*base_string != '{') | |
11760 | continue; | |
11761 | ||
11762 | vop_start = base_string; | |
11763 | ||
11764 | --base_string; | |
11765 | if (is_space_char (*base_string)) | |
11766 | --base_string; | |
11767 | ||
11768 | if (*base_string != '}') | |
11769 | break; | |
11770 | ||
11771 | vop_start = NULL; | |
11772 | } | |
11773 | ||
11774 | if (!vop_start) | |
11775 | { | |
11776 | as_bad (_("unbalanced figure braces")); | |
11777 | return 0; | |
11778 | } | |
11779 | ||
f70c6814 | 11780 | if (check_VecOperations (vop_start) == NULL) |
43234a1e | 11781 | return 0; |
43234a1e L |
11782 | } |
11783 | ||
47926f60 | 11784 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
11785 | displacement_string_start = op_string; |
11786 | displacement_string_end = base_string + 1; | |
252b5132 | 11787 | |
24eab124 AM |
11788 | if (*base_string == ')') |
11789 | { | |
af6bdddf | 11790 | char *temp_string; |
e87fb6a6 JB |
11791 | unsigned int parens_not_balanced = 0; |
11792 | bool in_quotes = false; | |
e68c3d59 | 11793 | |
24eab124 | 11794 | /* We've already checked that the number of left & right ()'s are |
e87fb6a6 JB |
11795 | equal, and that there's a matching set of double quotes. */ |
11796 | end_op = base_string; | |
11797 | for (temp_string = op_string; temp_string < end_op; temp_string++) | |
24eab124 | 11798 | { |
e87fb6a6 JB |
11799 | if (*temp_string == '\\' && temp_string[1] == '"') |
11800 | ++temp_string; | |
11801 | else if (*temp_string == '"') | |
11802 | in_quotes = !in_quotes; | |
11803 | else if (!in_quotes) | |
11804 | { | |
11805 | if (*temp_string == '(' && !parens_not_balanced++) | |
11806 | base_string = temp_string; | |
11807 | if (*temp_string == ')') | |
11808 | --parens_not_balanced; | |
11809 | } | |
24eab124 | 11810 | } |
c3332e24 | 11811 | |
af6bdddf | 11812 | temp_string = base_string; |
c3332e24 | 11813 | |
24eab124 | 11814 | /* Skip past '(' and whitespace. */ |
e87fb6a6 JB |
11815 | gas_assert (*base_string == '('); |
11816 | ++base_string; | |
252b5132 | 11817 | if (is_space_char (*base_string)) |
24eab124 | 11818 | ++base_string; |
252b5132 | 11819 | |
af6bdddf | 11820 | if (*base_string == ',' |
4eed87de AM |
11821 | || ((i.base_reg = parse_register (base_string, &end_op)) |
11822 | != NULL)) | |
252b5132 | 11823 | { |
af6bdddf | 11824 | displacement_string_end = temp_string; |
252b5132 | 11825 | |
40fb9820 | 11826 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 11827 | |
af6bdddf | 11828 | if (i.base_reg) |
24eab124 | 11829 | { |
8a6fb3f9 JB |
11830 | if (i.base_reg == &bad_reg) |
11831 | return 0; | |
24eab124 AM |
11832 | base_string = end_op; |
11833 | if (is_space_char (*base_string)) | |
11834 | ++base_string; | |
af6bdddf AM |
11835 | } |
11836 | ||
11837 | /* There may be an index reg or scale factor here. */ | |
11838 | if (*base_string == ',') | |
11839 | { | |
11840 | ++base_string; | |
11841 | if (is_space_char (*base_string)) | |
11842 | ++base_string; | |
11843 | ||
4eed87de AM |
11844 | if ((i.index_reg = parse_register (base_string, &end_op)) |
11845 | != NULL) | |
24eab124 | 11846 | { |
8a6fb3f9 JB |
11847 | if (i.index_reg == &bad_reg) |
11848 | return 0; | |
af6bdddf | 11849 | base_string = end_op; |
24eab124 AM |
11850 | if (is_space_char (*base_string)) |
11851 | ++base_string; | |
af6bdddf AM |
11852 | if (*base_string == ',') |
11853 | { | |
11854 | ++base_string; | |
11855 | if (is_space_char (*base_string)) | |
11856 | ++base_string; | |
11857 | } | |
e5cb08ac | 11858 | else if (*base_string != ')') |
af6bdddf | 11859 | { |
4eed87de AM |
11860 | as_bad (_("expecting `,' or `)' " |
11861 | "after index register in `%s'"), | |
af6bdddf AM |
11862 | operand_string); |
11863 | return 0; | |
11864 | } | |
24eab124 | 11865 | } |
af6bdddf | 11866 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 11867 | { |
f76bf5e0 L |
11868 | end_op = strchr (base_string, ','); |
11869 | if (end_op) | |
11870 | *end_op = '\0'; | |
af6bdddf | 11871 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
11872 | return 0; |
11873 | } | |
252b5132 | 11874 | |
47926f60 | 11875 | /* Check for scale factor. */ |
551c1ca1 | 11876 | if (*base_string != ')') |
af6bdddf | 11877 | { |
551c1ca1 AM |
11878 | char *end_scale = i386_scale (base_string); |
11879 | ||
11880 | if (!end_scale) | |
af6bdddf | 11881 | return 0; |
24eab124 | 11882 | |
551c1ca1 | 11883 | base_string = end_scale; |
af6bdddf AM |
11884 | if (is_space_char (*base_string)) |
11885 | ++base_string; | |
11886 | if (*base_string != ')') | |
11887 | { | |
4eed87de AM |
11888 | as_bad (_("expecting `)' " |
11889 | "after scale factor in `%s'"), | |
af6bdddf AM |
11890 | operand_string); |
11891 | return 0; | |
11892 | } | |
11893 | } | |
11894 | else if (!i.index_reg) | |
24eab124 | 11895 | { |
4eed87de AM |
11896 | as_bad (_("expecting index register or scale factor " |
11897 | "after `,'; got '%c'"), | |
af6bdddf | 11898 | *base_string); |
24eab124 AM |
11899 | return 0; |
11900 | } | |
11901 | } | |
af6bdddf | 11902 | else if (*base_string != ')') |
24eab124 | 11903 | { |
4eed87de AM |
11904 | as_bad (_("expecting `,' or `)' " |
11905 | "after base register in `%s'"), | |
af6bdddf | 11906 | operand_string); |
24eab124 AM |
11907 | return 0; |
11908 | } | |
c3332e24 | 11909 | } |
af6bdddf | 11910 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 11911 | { |
f76bf5e0 L |
11912 | end_op = strchr (base_string, ','); |
11913 | if (end_op) | |
11914 | *end_op = '\0'; | |
af6bdddf | 11915 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 11916 | return 0; |
c3332e24 | 11917 | } |
24eab124 AM |
11918 | } |
11919 | ||
11920 | /* If there's an expression beginning the operand, parse it, | |
11921 | assuming displacement_string_start and | |
11922 | displacement_string_end are meaningful. */ | |
11923 | if (displacement_string_start != displacement_string_end) | |
11924 | { | |
11925 | if (!i386_displacement (displacement_string_start, | |
11926 | displacement_string_end)) | |
11927 | return 0; | |
11928 | } | |
11929 | ||
11930 | /* Special case for (%dx) while doing input/output op. */ | |
11931 | if (i.base_reg | |
75e5731b JB |
11932 | && i.base_reg->reg_type.bitfield.instance == RegD |
11933 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
11934 | && i.index_reg == 0 |
11935 | && i.log2_scale_factor == 0 | |
11936 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 11937 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 11938 | { |
2fb5be8d | 11939 | i.types[this_operand] = i.base_reg->reg_type; |
9373f275 | 11940 | i.input_output_operand = true; |
24eab124 AM |
11941 | return 1; |
11942 | } | |
11943 | ||
eecb386c AM |
11944 | if (i386_index_check (operand_string) == 0) |
11945 | return 0; | |
c48dadc9 | 11946 | i.flags[this_operand] |= Operand_Mem; |
24eab124 AM |
11947 | i.mem_operands++; |
11948 | } | |
11949 | else | |
ce8a8b2f AM |
11950 | { |
11951 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
11952 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
11953 | output_invalid (*op_string), | |
11954 | this_operand + 1, | |
11955 | op_string); | |
11956 | return 0; | |
11957 | } | |
47926f60 | 11958 | return 1; /* Normal return. */ |
252b5132 RH |
11959 | } |
11960 | \f | |
fa94de6b RM |
11961 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
11962 | that an rs_machine_dependent frag may reach. */ | |
11963 | ||
11964 | unsigned int | |
11965 | i386_frag_max_var (fragS *frag) | |
11966 | { | |
11967 | /* The only relaxable frags are for jumps. | |
11968 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
11969 | gas_assert (frag->fr_type == rs_machine_dependent); | |
11970 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
11971 | } | |
11972 | ||
b084df0b L |
11973 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11974 | static int | |
8dcea932 | 11975 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
11976 | { |
11977 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
11978 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
11979 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
11980 | return 0; | |
11981 | ||
11982 | if (!S_IS_EXTERNAL (fr_symbol)) | |
11983 | /* Symbol may be weak or local. */ | |
11984 | return !S_IS_WEAK (fr_symbol); | |
11985 | ||
8dcea932 L |
11986 | /* Global symbols with non-default visibility can't be preempted. */ |
11987 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
11988 | return 1; | |
11989 | ||
11990 | if (fr_var != NO_RELOC) | |
11991 | switch ((enum bfd_reloc_code_real) fr_var) | |
11992 | { | |
11993 | case BFD_RELOC_386_PLT32: | |
11994 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11995 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11996 | return 0; |
11997 | default: | |
11998 | abort (); | |
11999 | } | |
12000 | ||
b084df0b L |
12001 | /* Global symbols with default visibility in a shared library may be |
12002 | preempted by another definition. */ | |
8dcea932 | 12003 | return !shared; |
b084df0b L |
12004 | } |
12005 | #endif | |
12006 | ||
79d72f45 HL |
12007 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
12008 | Note also work for Skylake and Cascadelake. | |
12009 | --------------------------------------------------------------------- | |
12010 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
12011 | | ------ | ----------- | ------- | -------- | | |
12012 | | Jo | N | N | Y | | |
12013 | | Jno | N | N | Y | | |
12014 | | Jc/Jb | Y | N | Y | | |
12015 | | Jae/Jnb | Y | N | Y | | |
12016 | | Je/Jz | Y | Y | Y | | |
12017 | | Jne/Jnz | Y | Y | Y | | |
12018 | | Jna/Jbe | Y | N | Y | | |
12019 | | Ja/Jnbe | Y | N | Y | | |
12020 | | Js | N | N | Y | | |
12021 | | Jns | N | N | Y | | |
12022 | | Jp/Jpe | N | N | Y | | |
12023 | | Jnp/Jpo | N | N | Y | | |
12024 | | Jl/Jnge | Y | Y | Y | | |
12025 | | Jge/Jnl | Y | Y | Y | | |
12026 | | Jle/Jng | Y | Y | Y | | |
12027 | | Jg/Jnle | Y | Y | Y | | |
12028 | --------------------------------------------------------------------- */ | |
12029 | static int | |
12030 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
12031 | { | |
12032 | if (mf_cmp == mf_cmp_alu_cmp) | |
12033 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
12034 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
12035 | if (mf_cmp == mf_cmp_incdec) | |
12036 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
12037 | || mf_jcc == mf_jcc_jle); | |
12038 | if (mf_cmp == mf_cmp_test_and) | |
12039 | return 1; | |
12040 | return 0; | |
12041 | } | |
12042 | ||
e379e5f3 L |
12043 | /* Return the next non-empty frag. */ |
12044 | ||
12045 | static fragS * | |
12046 | i386_next_non_empty_frag (fragS *fragP) | |
12047 | { | |
12048 | /* There may be a frag with a ".fill 0" when there is no room in | |
12049 | the current frag for frag_grow in output_insn. */ | |
12050 | for (fragP = fragP->fr_next; | |
12051 | (fragP != NULL | |
12052 | && fragP->fr_type == rs_fill | |
12053 | && fragP->fr_fix == 0); | |
12054 | fragP = fragP->fr_next) | |
12055 | ; | |
12056 | return fragP; | |
12057 | } | |
12058 | ||
12059 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
12060 | ||
12061 | static fragS * | |
79d72f45 | 12062 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 12063 | { |
79d72f45 HL |
12064 | fragS *branch_fragP; |
12065 | if (!pad_fragP) | |
e379e5f3 L |
12066 | return NULL; |
12067 | ||
79d72f45 HL |
12068 | if (pad_fragP->fr_type == rs_machine_dependent |
12069 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
12070 | == BRANCH_PADDING)) |
12071 | { | |
79d72f45 HL |
12072 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
12073 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 12074 | return NULL; |
79d72f45 HL |
12075 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
12076 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
12077 | pad_fragP->tc_frag_data.mf_type)) | |
12078 | return branch_fragP; | |
e379e5f3 L |
12079 | } |
12080 | ||
12081 | return NULL; | |
12082 | } | |
12083 | ||
12084 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
12085 | ||
12086 | static void | |
12087 | i386_classify_machine_dependent_frag (fragS *fragP) | |
12088 | { | |
12089 | fragS *cmp_fragP; | |
12090 | fragS *pad_fragP; | |
12091 | fragS *branch_fragP; | |
12092 | fragS *next_fragP; | |
12093 | unsigned int max_prefix_length; | |
12094 | ||
12095 | if (fragP->tc_frag_data.classified) | |
12096 | return; | |
12097 | ||
12098 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
12099 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
12100 | for (next_fragP = fragP; | |
12101 | next_fragP != NULL; | |
12102 | next_fragP = next_fragP->fr_next) | |
12103 | { | |
12104 | next_fragP->tc_frag_data.classified = 1; | |
12105 | if (next_fragP->fr_type == rs_machine_dependent) | |
12106 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
12107 | { | |
12108 | case BRANCH_PADDING: | |
12109 | /* The BRANCH_PADDING frag must be followed by a branch | |
12110 | frag. */ | |
12111 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
12112 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
12113 | break; | |
12114 | case FUSED_JCC_PADDING: | |
12115 | /* Check if this is a fused jcc: | |
12116 | FUSED_JCC_PADDING | |
12117 | CMP like instruction | |
12118 | BRANCH_PADDING | |
12119 | COND_JUMP | |
12120 | */ | |
12121 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
12122 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 12123 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
12124 | if (branch_fragP) |
12125 | { | |
12126 | /* The BRANCH_PADDING frag is merged with the | |
12127 | FUSED_JCC_PADDING frag. */ | |
12128 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
12129 | /* CMP like instruction size. */ | |
12130 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
12131 | frag_wane (pad_fragP); | |
12132 | /* Skip to branch_fragP. */ | |
12133 | next_fragP = branch_fragP; | |
12134 | } | |
12135 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
12136 | { | |
12137 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
12138 | a fused jcc. */ | |
12139 | next_fragP->fr_subtype | |
12140 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
12141 | next_fragP->tc_frag_data.max_bytes | |
12142 | = next_fragP->tc_frag_data.max_prefix_length; | |
12143 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
12144 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
12145 | } | |
12146 | else | |
12147 | frag_wane (next_fragP); | |
12148 | break; | |
12149 | } | |
12150 | } | |
12151 | ||
12152 | /* Stop if there is no BRANCH_PREFIX. */ | |
12153 | if (!align_branch_prefix_size) | |
12154 | return; | |
12155 | ||
12156 | /* Scan for BRANCH_PREFIX. */ | |
12157 | for (; fragP != NULL; fragP = fragP->fr_next) | |
12158 | { | |
12159 | if (fragP->fr_type != rs_machine_dependent | |
12160 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
12161 | != BRANCH_PREFIX)) | |
12162 | continue; | |
12163 | ||
12164 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
12165 | COND_JUMP_PREFIX. */ | |
12166 | max_prefix_length = 0; | |
12167 | for (next_fragP = fragP; | |
12168 | next_fragP != NULL; | |
12169 | next_fragP = next_fragP->fr_next) | |
12170 | { | |
12171 | if (next_fragP->fr_type == rs_fill) | |
12172 | /* Skip rs_fill frags. */ | |
12173 | continue; | |
12174 | else if (next_fragP->fr_type != rs_machine_dependent) | |
12175 | /* Stop for all other frags. */ | |
12176 | break; | |
12177 | ||
12178 | /* rs_machine_dependent frags. */ | |
12179 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12180 | == BRANCH_PREFIX) | |
12181 | { | |
12182 | /* Count BRANCH_PREFIX frags. */ | |
12183 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
12184 | { | |
12185 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
12186 | frag_wane (next_fragP); | |
12187 | } | |
12188 | else | |
12189 | max_prefix_length | |
12190 | += next_fragP->tc_frag_data.max_bytes; | |
12191 | } | |
12192 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12193 | == BRANCH_PADDING) | |
12194 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12195 | == FUSED_JCC_PADDING)) | |
12196 | { | |
12197 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
12198 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
12199 | break; | |
12200 | } | |
12201 | else | |
12202 | /* Stop for other rs_machine_dependent frags. */ | |
12203 | break; | |
12204 | } | |
12205 | ||
12206 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
12207 | ||
12208 | /* Skip to the next frag. */ | |
12209 | fragP = next_fragP; | |
12210 | } | |
12211 | } | |
12212 | ||
12213 | /* Compute padding size for | |
12214 | ||
12215 | FUSED_JCC_PADDING | |
12216 | CMP like instruction | |
12217 | BRANCH_PADDING | |
12218 | COND_JUMP/UNCOND_JUMP | |
12219 | ||
12220 | or | |
12221 | ||
12222 | BRANCH_PADDING | |
12223 | COND_JUMP/UNCOND_JUMP | |
12224 | */ | |
12225 | ||
12226 | static int | |
12227 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
12228 | { | |
12229 | unsigned int offset, size, padding_size; | |
12230 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
12231 | ||
12232 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
12233 | if (!address) | |
12234 | address = fragP->fr_address; | |
12235 | address += fragP->fr_fix; | |
12236 | ||
12237 | /* CMP like instrunction size. */ | |
12238 | size = fragP->tc_frag_data.cmp_size; | |
12239 | ||
12240 | /* The base size of the branch frag. */ | |
12241 | size += branch_fragP->fr_fix; | |
12242 | ||
12243 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
12244 | branch frag. */ | |
12245 | if (branch_fragP->fr_type == rs_machine_dependent) | |
12246 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
12247 | ||
12248 | /* Check if branch is within boundary and doesn't end at the last | |
12249 | byte. */ | |
12250 | offset = address & ((1U << align_branch_power) - 1); | |
12251 | if ((offset + size) >= (1U << align_branch_power)) | |
12252 | /* Padding needed to avoid crossing boundary. */ | |
12253 | padding_size = (1U << align_branch_power) - offset; | |
12254 | else | |
12255 | /* No padding needed. */ | |
12256 | padding_size = 0; | |
12257 | ||
12258 | /* The return value may be saved in tc_frag_data.length which is | |
12259 | unsigned byte. */ | |
12260 | if (!fits_in_unsigned_byte (padding_size)) | |
12261 | abort (); | |
12262 | ||
12263 | return padding_size; | |
12264 | } | |
12265 | ||
12266 | /* i386_generic_table_relax_frag() | |
12267 | ||
12268 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
12269 | grow/shrink padding to align branch frags. Hand others to | |
12270 | relax_frag(). */ | |
12271 | ||
12272 | long | |
12273 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
12274 | { | |
12275 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
12276 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12277 | { | |
12278 | long padding_size = i386_branch_padding_size (fragP, 0); | |
12279 | long grow = padding_size - fragP->tc_frag_data.length; | |
12280 | ||
12281 | /* When the BRANCH_PREFIX frag is used, the computed address | |
12282 | must match the actual address and there should be no padding. */ | |
12283 | if (fragP->tc_frag_data.padding_address | |
12284 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
12285 | || padding_size)) | |
12286 | abort (); | |
12287 | ||
12288 | /* Update the padding size. */ | |
12289 | if (grow) | |
12290 | fragP->tc_frag_data.length = padding_size; | |
12291 | ||
12292 | return grow; | |
12293 | } | |
12294 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12295 | { | |
12296 | fragS *padding_fragP, *next_fragP; | |
12297 | long padding_size, left_size, last_size; | |
12298 | ||
12299 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12300 | if (!padding_fragP) | |
12301 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
12302 | return (fragP->tc_frag_data.length | |
12303 | - fragP->tc_frag_data.last_length); | |
12304 | ||
12305 | /* Compute the relative address of the padding frag in the very | |
12306 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
12307 | if (!fragP->tc_frag_data.padding_address) | |
12308 | fragP->tc_frag_data.padding_address | |
12309 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
12310 | ||
12311 | /* First update the last length from the previous interation. */ | |
12312 | left_size = fragP->tc_frag_data.prefix_length; | |
12313 | for (next_fragP = fragP; | |
12314 | next_fragP != padding_fragP; | |
12315 | next_fragP = next_fragP->fr_next) | |
12316 | if (next_fragP->fr_type == rs_machine_dependent | |
12317 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12318 | == BRANCH_PREFIX)) | |
12319 | { | |
12320 | if (left_size) | |
12321 | { | |
12322 | int max = next_fragP->tc_frag_data.max_bytes; | |
12323 | if (max) | |
12324 | { | |
12325 | int size; | |
12326 | if (max > left_size) | |
12327 | size = left_size; | |
12328 | else | |
12329 | size = max; | |
12330 | left_size -= size; | |
12331 | next_fragP->tc_frag_data.last_length = size; | |
12332 | } | |
12333 | } | |
12334 | else | |
12335 | next_fragP->tc_frag_data.last_length = 0; | |
12336 | } | |
12337 | ||
12338 | /* Check the padding size for the padding frag. */ | |
12339 | padding_size = i386_branch_padding_size | |
12340 | (padding_fragP, (fragP->fr_address | |
12341 | + fragP->tc_frag_data.padding_address)); | |
12342 | ||
12343 | last_size = fragP->tc_frag_data.prefix_length; | |
12344 | /* Check if there is change from the last interation. */ | |
12345 | if (padding_size == last_size) | |
12346 | { | |
12347 | /* Update the expected address of the padding frag. */ | |
12348 | padding_fragP->tc_frag_data.padding_address | |
12349 | = (fragP->fr_address + padding_size | |
12350 | + fragP->tc_frag_data.padding_address); | |
12351 | return 0; | |
12352 | } | |
12353 | ||
12354 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
12355 | { | |
12356 | /* No padding if there is no sufficient room. Clear the | |
12357 | expected address of the padding frag. */ | |
12358 | padding_fragP->tc_frag_data.padding_address = 0; | |
12359 | padding_size = 0; | |
12360 | } | |
12361 | else | |
12362 | /* Store the expected address of the padding frag. */ | |
12363 | padding_fragP->tc_frag_data.padding_address | |
12364 | = (fragP->fr_address + padding_size | |
12365 | + fragP->tc_frag_data.padding_address); | |
12366 | ||
12367 | fragP->tc_frag_data.prefix_length = padding_size; | |
12368 | ||
12369 | /* Update the length for the current interation. */ | |
12370 | left_size = padding_size; | |
12371 | for (next_fragP = fragP; | |
12372 | next_fragP != padding_fragP; | |
12373 | next_fragP = next_fragP->fr_next) | |
12374 | if (next_fragP->fr_type == rs_machine_dependent | |
12375 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12376 | == BRANCH_PREFIX)) | |
12377 | { | |
12378 | if (left_size) | |
12379 | { | |
12380 | int max = next_fragP->tc_frag_data.max_bytes; | |
12381 | if (max) | |
12382 | { | |
12383 | int size; | |
12384 | if (max > left_size) | |
12385 | size = left_size; | |
12386 | else | |
12387 | size = max; | |
12388 | left_size -= size; | |
12389 | next_fragP->tc_frag_data.length = size; | |
12390 | } | |
12391 | } | |
12392 | else | |
12393 | next_fragP->tc_frag_data.length = 0; | |
12394 | } | |
12395 | ||
12396 | return (fragP->tc_frag_data.length | |
12397 | - fragP->tc_frag_data.last_length); | |
12398 | } | |
12399 | return relax_frag (segment, fragP, stretch); | |
12400 | } | |
12401 | ||
ee7fcc42 AM |
12402 | /* md_estimate_size_before_relax() |
12403 | ||
12404 | Called just before relax() for rs_machine_dependent frags. The x86 | |
12405 | assembler uses these frags to handle variable size jump | |
12406 | instructions. | |
12407 | ||
12408 | Any symbol that is now undefined will not become defined. | |
12409 | Return the correct fr_subtype in the frag. | |
12410 | Return the initial "guess for variable size of frag" to caller. | |
12411 | The guess is actually the growth beyond the fixed part. Whatever | |
12412 | we do to grow the fixed or variable part contributes to our | |
12413 | returned value. */ | |
12414 | ||
252b5132 | 12415 | int |
7016a5d5 | 12416 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 12417 | { |
e379e5f3 L |
12418 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12419 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
12420 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12421 | { | |
12422 | i386_classify_machine_dependent_frag (fragP); | |
12423 | return fragP->tc_frag_data.length; | |
12424 | } | |
12425 | ||
252b5132 | 12426 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
12427 | check for un-relaxable symbols. On an ELF system, we can't relax |
12428 | an externally visible symbol, because it may be overridden by a | |
12429 | shared library. */ | |
12430 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 12431 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12432 | || (IS_ELF |
8dcea932 L |
12433 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
12434 | fragP->fr_var)) | |
fbeb56a4 DK |
12435 | #endif |
12436 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 12437 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 12438 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
12439 | #endif |
12440 | ) | |
252b5132 | 12441 | { |
b98ef147 AM |
12442 | /* Symbol is undefined in this segment, or we need to keep a |
12443 | reloc so that weak symbols can be overridden. */ | |
12444 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 12445 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
12446 | unsigned char *opcode; |
12447 | int old_fr_fix; | |
eb19308f | 12448 | fixS *fixP = NULL; |
f6af82bd | 12449 | |
ee7fcc42 | 12450 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 12451 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 12452 | else if (size == 2) |
f6af82bd | 12453 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b | 12454 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
12455 | else if (fragP->tc_frag_data.code64 && fragP->fr_offset == 0 |
12456 | && need_plt32_p (fragP->fr_symbol)) | |
bd7ab16b L |
12457 | reloc_type = BFD_RELOC_X86_64_PLT32; |
12458 | #endif | |
f6af82bd AM |
12459 | else |
12460 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 12461 | |
ee7fcc42 AM |
12462 | old_fr_fix = fragP->fr_fix; |
12463 | opcode = (unsigned char *) fragP->fr_opcode; | |
12464 | ||
fddf5b5b | 12465 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 12466 | { |
fddf5b5b AM |
12467 | case UNCOND_JUMP: |
12468 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 12469 | opcode[0] = 0xe9; |
252b5132 | 12470 | fragP->fr_fix += size; |
eb19308f JB |
12471 | fixP = fix_new (fragP, old_fr_fix, size, |
12472 | fragP->fr_symbol, | |
12473 | fragP->fr_offset, 1, | |
12474 | reloc_type); | |
252b5132 RH |
12475 | break; |
12476 | ||
fddf5b5b | 12477 | case COND_JUMP86: |
412167cb AM |
12478 | if (size == 2 |
12479 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
12480 | { |
12481 | /* Negate the condition, and branch past an | |
12482 | unconditional jump. */ | |
12483 | opcode[0] ^= 1; | |
12484 | opcode[1] = 3; | |
12485 | /* Insert an unconditional jump. */ | |
12486 | opcode[2] = 0xe9; | |
12487 | /* We added two extra opcode bytes, and have a two byte | |
12488 | offset. */ | |
12489 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
12490 | fix_new (fragP, old_fr_fix + 2, 2, |
12491 | fragP->fr_symbol, | |
12492 | fragP->fr_offset, 1, | |
12493 | reloc_type); | |
fddf5b5b AM |
12494 | break; |
12495 | } | |
12496 | /* Fall through. */ | |
12497 | ||
12498 | case COND_JUMP: | |
412167cb AM |
12499 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
12500 | { | |
12501 | fragP->fr_fix += 1; | |
3e02c1cc AM |
12502 | fixP = fix_new (fragP, old_fr_fix, 1, |
12503 | fragP->fr_symbol, | |
12504 | fragP->fr_offset, 1, | |
12505 | BFD_RELOC_8_PCREL); | |
12506 | fixP->fx_signed = 1; | |
412167cb AM |
12507 | break; |
12508 | } | |
93c2a809 | 12509 | |
24eab124 | 12510 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 12511 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 12512 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 12513 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
12514 | /* We've added an opcode byte. */ |
12515 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
12516 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
12517 | fragP->fr_symbol, | |
12518 | fragP->fr_offset, 1, | |
12519 | reloc_type); | |
252b5132 | 12520 | break; |
fddf5b5b AM |
12521 | |
12522 | default: | |
12523 | BAD_CASE (fragP->fr_subtype); | |
12524 | break; | |
252b5132 | 12525 | } |
eb19308f JB |
12526 | |
12527 | /* All jumps handled here are signed, but don't unconditionally use a | |
12528 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
12529 | around at 4G (outside of 64-bit mode) and 64k. */ | |
12530 | if (size == 4 && flag_code == CODE_64BIT) | |
12531 | fixP->fx_signed = 1; | |
12532 | ||
252b5132 | 12533 | frag_wane (fragP); |
ee7fcc42 | 12534 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 12535 | } |
93c2a809 | 12536 | |
93c2a809 AM |
12537 | /* Guess size depending on current relax state. Initially the relax |
12538 | state will correspond to a short jump and we return 1, because | |
12539 | the variable part of the frag (the branch offset) is one byte | |
12540 | long. However, we can relax a section more than once and in that | |
12541 | case we must either set fr_subtype back to the unrelaxed state, | |
12542 | or return the value for the appropriate branch. */ | |
12543 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
12544 | } |
12545 | ||
47926f60 KH |
12546 | /* Called after relax() is finished. |
12547 | ||
12548 | In: Address of frag. | |
12549 | fr_type == rs_machine_dependent. | |
12550 | fr_subtype is what the address relaxed to. | |
12551 | ||
12552 | Out: Any fixSs and constants are set up. | |
12553 | Caller will turn frag into a ".space 0". */ | |
12554 | ||
252b5132 | 12555 | void |
7016a5d5 TG |
12556 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
12557 | fragS *fragP) | |
252b5132 | 12558 | { |
29b0f896 | 12559 | unsigned char *opcode; |
252b5132 | 12560 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
12561 | offsetT target_address; |
12562 | offsetT opcode_address; | |
252b5132 | 12563 | unsigned int extension = 0; |
847f7ad4 | 12564 | offsetT displacement_from_opcode_start; |
252b5132 | 12565 | |
e379e5f3 L |
12566 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12567 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
12568 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12569 | { | |
12570 | /* Generate nop padding. */ | |
12571 | unsigned int size = fragP->tc_frag_data.length; | |
12572 | if (size) | |
12573 | { | |
12574 | if (size > fragP->tc_frag_data.max_bytes) | |
12575 | abort (); | |
12576 | ||
12577 | if (flag_debug) | |
12578 | { | |
12579 | const char *msg; | |
12580 | const char *branch = "branch"; | |
12581 | const char *prefix = ""; | |
12582 | fragS *padding_fragP; | |
12583 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
12584 | == BRANCH_PREFIX) | |
12585 | { | |
12586 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12587 | switch (fragP->tc_frag_data.default_prefix) | |
12588 | { | |
12589 | default: | |
12590 | abort (); | |
12591 | break; | |
12592 | case CS_PREFIX_OPCODE: | |
12593 | prefix = " cs"; | |
12594 | break; | |
12595 | case DS_PREFIX_OPCODE: | |
12596 | prefix = " ds"; | |
12597 | break; | |
12598 | case ES_PREFIX_OPCODE: | |
12599 | prefix = " es"; | |
12600 | break; | |
12601 | case FS_PREFIX_OPCODE: | |
12602 | prefix = " fs"; | |
12603 | break; | |
12604 | case GS_PREFIX_OPCODE: | |
12605 | prefix = " gs"; | |
12606 | break; | |
12607 | case SS_PREFIX_OPCODE: | |
12608 | prefix = " ss"; | |
12609 | break; | |
12610 | } | |
12611 | if (padding_fragP) | |
12612 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
12613 | "%s within %d-byte boundary\n"); | |
12614 | else | |
12615 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
12616 | "align %s within %d-byte boundary\n"); | |
12617 | } | |
12618 | else | |
12619 | { | |
12620 | padding_fragP = fragP; | |
12621 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
12622 | "%s within %d-byte boundary\n"); | |
12623 | } | |
12624 | ||
12625 | if (padding_fragP) | |
12626 | switch (padding_fragP->tc_frag_data.branch_type) | |
12627 | { | |
12628 | case align_branch_jcc: | |
12629 | branch = "jcc"; | |
12630 | break; | |
12631 | case align_branch_fused: | |
12632 | branch = "fused jcc"; | |
12633 | break; | |
12634 | case align_branch_jmp: | |
12635 | branch = "jmp"; | |
12636 | break; | |
12637 | case align_branch_call: | |
12638 | branch = "call"; | |
12639 | break; | |
12640 | case align_branch_indirect: | |
12641 | branch = "indiret branch"; | |
12642 | break; | |
12643 | case align_branch_ret: | |
12644 | branch = "ret"; | |
12645 | break; | |
12646 | default: | |
12647 | break; | |
12648 | } | |
12649 | ||
12650 | fprintf (stdout, msg, | |
12651 | fragP->fr_file, fragP->fr_line, size, prefix, | |
12652 | (long long) fragP->fr_address, branch, | |
12653 | 1 << align_branch_power); | |
12654 | } | |
12655 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12656 | memset (fragP->fr_opcode, | |
12657 | fragP->tc_frag_data.default_prefix, size); | |
12658 | else | |
12659 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
12660 | size, 0); | |
12661 | fragP->fr_fix += size; | |
12662 | } | |
12663 | return; | |
12664 | } | |
12665 | ||
252b5132 RH |
12666 | opcode = (unsigned char *) fragP->fr_opcode; |
12667 | ||
47926f60 | 12668 | /* Address we want to reach in file space. */ |
252b5132 | 12669 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 12670 | |
47926f60 | 12671 | /* Address opcode resides at in file space. */ |
252b5132 RH |
12672 | opcode_address = fragP->fr_address + fragP->fr_fix; |
12673 | ||
47926f60 | 12674 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
12675 | displacement_from_opcode_start = target_address - opcode_address; |
12676 | ||
fddf5b5b | 12677 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 12678 | { |
47926f60 KH |
12679 | /* Don't have to change opcode. */ |
12680 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 12681 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
12682 | } |
12683 | else | |
12684 | { | |
12685 | if (no_cond_jump_promotion | |
12686 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
12687 | as_warn_where (fragP->fr_file, fragP->fr_line, |
12688 | _("long jump required")); | |
252b5132 | 12689 | |
fddf5b5b AM |
12690 | switch (fragP->fr_subtype) |
12691 | { | |
12692 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
12693 | extension = 4; /* 1 opcode + 4 displacement */ | |
12694 | opcode[0] = 0xe9; | |
12695 | where_to_put_displacement = &opcode[1]; | |
12696 | break; | |
252b5132 | 12697 | |
fddf5b5b AM |
12698 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
12699 | extension = 2; /* 1 opcode + 2 displacement */ | |
12700 | opcode[0] = 0xe9; | |
12701 | where_to_put_displacement = &opcode[1]; | |
12702 | break; | |
252b5132 | 12703 | |
fddf5b5b AM |
12704 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
12705 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
12706 | extension = 5; /* 2 opcode + 4 displacement */ | |
12707 | opcode[1] = opcode[0] + 0x10; | |
12708 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12709 | where_to_put_displacement = &opcode[2]; | |
12710 | break; | |
252b5132 | 12711 | |
fddf5b5b AM |
12712 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
12713 | extension = 3; /* 2 opcode + 2 displacement */ | |
12714 | opcode[1] = opcode[0] + 0x10; | |
12715 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12716 | where_to_put_displacement = &opcode[2]; | |
12717 | break; | |
252b5132 | 12718 | |
fddf5b5b AM |
12719 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
12720 | extension = 4; | |
12721 | opcode[0] ^= 1; | |
12722 | opcode[1] = 3; | |
12723 | opcode[2] = 0xe9; | |
12724 | where_to_put_displacement = &opcode[3]; | |
12725 | break; | |
12726 | ||
12727 | default: | |
12728 | BAD_CASE (fragP->fr_subtype); | |
12729 | break; | |
12730 | } | |
252b5132 | 12731 | } |
fddf5b5b | 12732 | |
7b81dfbb AJ |
12733 | /* If size if less then four we are sure that the operand fits, |
12734 | but if it's 4, then it could be that the displacement is larger | |
12735 | then -/+ 2GB. */ | |
12736 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
12737 | && object_64bit | |
12738 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
12739 | + ((addressT) 1 << 31)) |
12740 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
12741 | { |
12742 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
12743 | _("jump target out of range")); | |
12744 | /* Make us emit 0. */ | |
12745 | displacement_from_opcode_start = extension; | |
12746 | } | |
47926f60 | 12747 | /* Now put displacement after opcode. */ |
252b5132 RH |
12748 | md_number_to_chars ((char *) where_to_put_displacement, |
12749 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 12750 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
12751 | fragP->fr_fix += extension; |
12752 | } | |
12753 | \f | |
7016a5d5 | 12754 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
12755 | by our caller that we have all the info we need to fix it up. |
12756 | ||
7016a5d5 TG |
12757 | Parameter valP is the pointer to the value of the bits. |
12758 | ||
252b5132 RH |
12759 | On the 386, immediates, displacements, and data pointers are all in |
12760 | the same (little-endian) format, so we don't need to care about which | |
12761 | we are handling. */ | |
12762 | ||
94f592af | 12763 | void |
7016a5d5 | 12764 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12765 | { |
94f592af | 12766 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 12767 | valueT value = *valP; |
252b5132 | 12768 | |
f86103b7 | 12769 | #if !defined (TE_Mach) |
93382f6d AM |
12770 | if (fixP->fx_pcrel) |
12771 | { | |
12772 | switch (fixP->fx_r_type) | |
12773 | { | |
5865bb77 ILT |
12774 | default: |
12775 | break; | |
12776 | ||
d6ab8113 JB |
12777 | case BFD_RELOC_64: |
12778 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
12779 | break; | |
93382f6d | 12780 | case BFD_RELOC_32: |
ae8887b5 | 12781 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
12782 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
12783 | break; | |
12784 | case BFD_RELOC_16: | |
12785 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
12786 | break; | |
12787 | case BFD_RELOC_8: | |
12788 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
12789 | break; | |
12790 | } | |
12791 | } | |
252b5132 | 12792 | |
a161fe53 | 12793 | if (fixP->fx_addsy != NULL |
31312f95 | 12794 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 12795 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 12796 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 12797 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 12798 | && !use_rela_relocations) |
252b5132 | 12799 | { |
31312f95 AM |
12800 | /* This is a hack. There should be a better way to handle this. |
12801 | This covers for the fact that bfd_install_relocation will | |
12802 | subtract the current location (for partial_inplace, PC relative | |
12803 | relocations); see more below. */ | |
252b5132 | 12804 | #ifndef OBJ_AOUT |
718ddfc0 | 12805 | if (IS_ELF |
252b5132 RH |
12806 | #ifdef TE_PE |
12807 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
12808 | #endif | |
12809 | ) | |
12810 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12811 | #endif | |
12812 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 12813 | if (IS_ELF) |
252b5132 | 12814 | { |
6539b54b | 12815 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 12816 | |
6539b54b | 12817 | if ((sym_seg == seg |
2f66722d | 12818 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 12819 | && sym_seg != absolute_section)) |
af65af87 | 12820 | && !generic_force_reloc (fixP)) |
2f66722d AM |
12821 | { |
12822 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
12823 | bfd_install_relocation subtracts them out again. I think |
12824 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
12825 | it. FIXME. */ |
12826 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12827 | } | |
252b5132 RH |
12828 | } |
12829 | #endif | |
12830 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
12831 | /* For some reason, the PE format does not store a |
12832 | section address offset for a PC relative symbol. */ | |
12833 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 12834 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
12835 | value += md_pcrel_from (fixP); |
12836 | #endif | |
12837 | } | |
fbeb56a4 | 12838 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
12839 | if (fixP->fx_addsy != NULL |
12840 | && S_IS_WEAK (fixP->fx_addsy) | |
12841 | /* PR 16858: Do not modify weak function references. */ | |
12842 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 12843 | { |
296a8689 NC |
12844 | #if !defined (TE_PEP) |
12845 | /* For x86 PE weak function symbols are neither PC-relative | |
12846 | nor do they set S_IS_FUNCTION. So the only reliable way | |
12847 | to detect them is to check the flags of their containing | |
12848 | section. */ | |
12849 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
12850 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
12851 | ; | |
12852 | else | |
12853 | #endif | |
fbeb56a4 DK |
12854 | value -= S_GET_VALUE (fixP->fx_addsy); |
12855 | } | |
12856 | #endif | |
252b5132 RH |
12857 | |
12858 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 12859 | and we must not disappoint it. */ |
252b5132 | 12860 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12861 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
12862 | switch (fixP->fx_r_type) |
12863 | { | |
12864 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 12865 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
12866 | /* Make the jump instruction point to the address of the operand. |
12867 | At runtime we merely add the offset to the actual PLT entry. | |
12868 | NB: Subtract the offset size only for jump instructions. */ | |
12869 | if (fixP->fx_pcrel) | |
12870 | value = -4; | |
47926f60 | 12871 | break; |
31312f95 | 12872 | |
13ae64f3 JJ |
12873 | case BFD_RELOC_386_TLS_GD: |
12874 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 12875 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
12876 | case BFD_RELOC_386_TLS_IE: |
12877 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 12878 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
12879 | case BFD_RELOC_X86_64_TLSGD: |
12880 | case BFD_RELOC_X86_64_TLSLD: | |
12881 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 12882 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
12883 | value = 0; /* Fully resolved at runtime. No addend. */ |
12884 | /* Fallthrough */ | |
12885 | case BFD_RELOC_386_TLS_LE: | |
12886 | case BFD_RELOC_386_TLS_LDO_32: | |
12887 | case BFD_RELOC_386_TLS_LE_32: | |
12888 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12889 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 12890 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 12891 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
12892 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
12893 | break; | |
12894 | ||
67a4f2b7 AO |
12895 | case BFD_RELOC_386_TLS_DESC_CALL: |
12896 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
12897 | value = 0; /* Fully resolved at runtime. No addend. */ | |
12898 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12899 | fixP->fx_done = 0; | |
12900 | return; | |
12901 | ||
47926f60 KH |
12902 | case BFD_RELOC_VTABLE_INHERIT: |
12903 | case BFD_RELOC_VTABLE_ENTRY: | |
12904 | fixP->fx_done = 0; | |
94f592af | 12905 | return; |
47926f60 KH |
12906 | |
12907 | default: | |
12908 | break; | |
12909 | } | |
12910 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
a442cac5 JB |
12911 | |
12912 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ | |
12913 | if (!object_64bit) | |
12914 | value = extend_to_32bit_address (value); | |
12915 | ||
c6682705 | 12916 | *valP = value; |
f86103b7 | 12917 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 12918 | |
3e73aa7c | 12919 | /* Are we finished with this relocation now? */ |
c6682705 | 12920 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
12921 | { |
12922 | fixP->fx_done = 1; | |
12923 | switch (fixP->fx_r_type) | |
12924 | { | |
12925 | case BFD_RELOC_X86_64_32S: | |
12926 | fixP->fx_signed = 1; | |
12927 | break; | |
12928 | ||
12929 | default: | |
12930 | break; | |
12931 | } | |
12932 | } | |
fbeb56a4 DK |
12933 | #if defined (OBJ_COFF) && defined (TE_PE) |
12934 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
12935 | { | |
12936 | fixP->fx_done = 0; | |
12937 | /* Remember value for tc_gen_reloc. */ | |
12938 | fixP->fx_addnumber = value; | |
12939 | /* Clear out the frag for now. */ | |
12940 | value = 0; | |
12941 | } | |
12942 | #endif | |
3e73aa7c JH |
12943 | else if (use_rela_relocations) |
12944 | { | |
46fb6d5a JB |
12945 | if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC) |
12946 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
12947 | /* Remember value for tc_gen_reloc. */ |
12948 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
12949 | value = 0; |
12950 | } | |
f86103b7 | 12951 | |
94f592af | 12952 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 12953 | } |
252b5132 | 12954 | \f |
6d4af3c2 | 12955 | const char * |
499ac353 | 12956 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 12957 | { |
499ac353 NC |
12958 | /* This outputs the LITTLENUMs in REVERSE order; |
12959 | in accord with the bigendian 386. */ | |
5b7c81bd | 12960 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
12961 | } |
12962 | \f | |
2d545b82 | 12963 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 12964 | |
252b5132 | 12965 | static char * |
e3bb37b5 | 12966 | output_invalid (int c) |
252b5132 | 12967 | { |
3882b010 | 12968 | if (ISPRINT (c)) |
f9f21a03 L |
12969 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
12970 | "'%c'", c); | |
252b5132 | 12971 | else |
f9f21a03 | 12972 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 12973 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
12974 | return output_invalid_buf; |
12975 | } | |
12976 | ||
8a6fb3f9 JB |
12977 | /* Verify that @r can be used in the current context. */ |
12978 | ||
5b7c81bd | 12979 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
12980 | { |
12981 | if (allow_pseudo_reg) | |
5b7c81bd | 12982 | return true; |
8a6fb3f9 JB |
12983 | |
12984 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 12985 | return false; |
8a6fb3f9 JB |
12986 | |
12987 | if ((r->reg_type.bitfield.dword | |
12988 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
12989 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 12990 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 12991 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 12992 | return false; |
8a6fb3f9 | 12993 | |
22e00a3f JB |
12994 | if (r->reg_type.bitfield.class == RegTR |
12995 | && (flag_code == CODE_64BIT | |
12996 | || !cpu_arch_flags.bitfield.cpui386 | |
12997 | || cpu_arch_isa_flags.bitfield.cpui586 | |
12998 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 12999 | return false; |
22e00a3f | 13000 | |
8a6fb3f9 | 13001 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 13002 | return false; |
8a6fb3f9 JB |
13003 | |
13004 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
13005 | { | |
13006 | if (r->reg_type.bitfield.zmmword | |
13007 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 13008 | return false; |
8a6fb3f9 JB |
13009 | |
13010 | if (!cpu_arch_flags.bitfield.cpuavx) | |
13011 | { | |
13012 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 13013 | return false; |
8a6fb3f9 JB |
13014 | |
13015 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 13016 | return false; |
8a6fb3f9 JB |
13017 | } |
13018 | } | |
13019 | ||
260cd341 LC |
13020 | if (r->reg_type.bitfield.tmmword |
13021 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
13022 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 13023 | return false; |
260cd341 | 13024 | |
8a6fb3f9 | 13025 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 13026 | return false; |
8a6fb3f9 JB |
13027 | |
13028 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
13029 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 13030 | return false; |
8a6fb3f9 JB |
13031 | |
13032 | /* Upper 16 vector registers are only available with VREX in 64bit | |
13033 | mode, and require EVEX encoding. */ | |
13034 | if (r->reg_flags & RegVRex) | |
13035 | { | |
13036 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
13037 | || flag_code != CODE_64BIT) | |
5b7c81bd | 13038 | return false; |
8a6fb3f9 | 13039 | |
da4977e0 JB |
13040 | if (i.vec_encoding == vex_encoding_default) |
13041 | i.vec_encoding = vex_encoding_evex; | |
13042 | else if (i.vec_encoding != vex_encoding_evex) | |
13043 | i.vec_encoding = vex_encoding_error; | |
8a6fb3f9 JB |
13044 | } |
13045 | ||
13046 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) | |
13047 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) | |
13048 | && flag_code != CODE_64BIT) | |
5b7c81bd | 13049 | return false; |
8a6fb3f9 JB |
13050 | |
13051 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
13052 | && !intel_syntax) | |
5b7c81bd | 13053 | return false; |
8a6fb3f9 | 13054 | |
5b7c81bd | 13055 | return true; |
8a6fb3f9 JB |
13056 | } |
13057 | ||
af6bdddf | 13058 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
13059 | |
13060 | static const reg_entry * | |
4d1bb795 | 13061 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 13062 | { |
af6bdddf AM |
13063 | char *s = reg_string; |
13064 | char *p; | |
252b5132 RH |
13065 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
13066 | const reg_entry *r; | |
13067 | ||
13068 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
13069 | if (*s == REGISTER_PREFIX) | |
13070 | ++s; | |
13071 | ||
13072 | if (is_space_char (*s)) | |
13073 | ++s; | |
13074 | ||
13075 | p = reg_name_given; | |
af6bdddf | 13076 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
13077 | { |
13078 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
13079 | return (const reg_entry *) NULL; |
13080 | s++; | |
252b5132 RH |
13081 | } |
13082 | ||
6588847e DN |
13083 | /* For naked regs, make sure that we are not dealing with an identifier. |
13084 | This prevents confusing an identifier like `eax_var' with register | |
13085 | `eax'. */ | |
13086 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
13087 | return (const reg_entry *) NULL; | |
13088 | ||
af6bdddf | 13089 | *end_op = s; |
252b5132 | 13090 | |
629310ab | 13091 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 13092 | |
5f47d35b | 13093 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 13094 | if (r == reg_st0) |
5f47d35b | 13095 | { |
0e0eea78 JB |
13096 | if (!cpu_arch_flags.bitfield.cpu8087 |
13097 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
13098 | && !cpu_arch_flags.bitfield.cpu387 |
13099 | && !allow_pseudo_reg) | |
0e0eea78 JB |
13100 | return (const reg_entry *) NULL; |
13101 | ||
5f47d35b AM |
13102 | if (is_space_char (*s)) |
13103 | ++s; | |
13104 | if (*s == '(') | |
13105 | { | |
af6bdddf | 13106 | ++s; |
5f47d35b AM |
13107 | if (is_space_char (*s)) |
13108 | ++s; | |
13109 | if (*s >= '0' && *s <= '7') | |
13110 | { | |
db557034 | 13111 | int fpr = *s - '0'; |
af6bdddf | 13112 | ++s; |
5f47d35b AM |
13113 | if (is_space_char (*s)) |
13114 | ++s; | |
13115 | if (*s == ')') | |
13116 | { | |
13117 | *end_op = s + 1; | |
6288d05f | 13118 | know (r[fpr].reg_num == fpr); |
db557034 | 13119 | return r + fpr; |
5f47d35b | 13120 | } |
5f47d35b | 13121 | } |
47926f60 | 13122 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
13123 | return (const reg_entry *) NULL; |
13124 | } | |
13125 | } | |
13126 | ||
8a6fb3f9 | 13127 | return r && check_register (r) ? r : NULL; |
252b5132 | 13128 | } |
4d1bb795 JB |
13129 | |
13130 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
13131 | ||
13132 | static const reg_entry * | |
13133 | parse_register (char *reg_string, char **end_op) | |
13134 | { | |
13135 | const reg_entry *r; | |
13136 | ||
13137 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
13138 | r = parse_real_register (reg_string, end_op); | |
13139 | else | |
13140 | r = NULL; | |
13141 | if (!r) | |
13142 | { | |
13143 | char *save = input_line_pointer; | |
13144 | char c; | |
13145 | symbolS *symbolP; | |
13146 | ||
13147 | input_line_pointer = reg_string; | |
d02603dc | 13148 | c = get_symbol_name (®_string); |
4d1bb795 | 13149 | symbolP = symbol_find (reg_string); |
64d23078 JB |
13150 | while (symbolP && S_GET_SEGMENT (symbolP) != reg_section) |
13151 | { | |
13152 | const expressionS *e = symbol_get_value_expression(symbolP); | |
13153 | ||
13154 | if (e->X_op != O_symbol || e->X_add_number) | |
13155 | break; | |
13156 | symbolP = e->X_add_symbol; | |
13157 | } | |
4d1bb795 JB |
13158 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
13159 | { | |
13160 | const expressionS *e = symbol_get_value_expression (symbolP); | |
13161 | ||
0ccade1a JB |
13162 | if (e->X_op == O_register) |
13163 | { | |
13164 | know (e->X_add_number >= 0 | |
13165 | && (valueT) e->X_add_number < i386_regtab_size); | |
13166 | r = i386_regtab + e->X_add_number; | |
13167 | *end_op = input_line_pointer; | |
13168 | } | |
13169 | if (r && !check_register (r)) | |
8a6fb3f9 | 13170 | { |
3b55a1d0 JB |
13171 | as_bad (_("register '%s%s' cannot be used here"), |
13172 | register_prefix, r->reg_name); | |
13173 | r = &bad_reg; | |
8a6fb3f9 | 13174 | } |
4d1bb795 JB |
13175 | } |
13176 | *input_line_pointer = c; | |
13177 | input_line_pointer = save; | |
13178 | } | |
13179 | return r; | |
13180 | } | |
13181 | ||
13182 | int | |
13183 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
13184 | { | |
4faaa10f | 13185 | const reg_entry *r = NULL; |
4d1bb795 JB |
13186 | char *end = input_line_pointer; |
13187 | ||
13188 | *end = *nextcharP; | |
4faaa10f JB |
13189 | if (*name == REGISTER_PREFIX || allow_naked_reg) |
13190 | r = parse_real_register (name, &input_line_pointer); | |
4d1bb795 JB |
13191 | if (r && end <= input_line_pointer) |
13192 | { | |
13193 | *nextcharP = *input_line_pointer; | |
13194 | *input_line_pointer = 0; | |
8a6fb3f9 JB |
13195 | if (r != &bad_reg) |
13196 | { | |
13197 | e->X_op = O_register; | |
13198 | e->X_add_number = r - i386_regtab; | |
13199 | } | |
13200 | else | |
13201 | e->X_op = O_illegal; | |
4d1bb795 JB |
13202 | return 1; |
13203 | } | |
13204 | input_line_pointer = end; | |
13205 | *end = 0; | |
ee86248c | 13206 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
13207 | } |
13208 | ||
13209 | void | |
13210 | md_operand (expressionS *e) | |
13211 | { | |
ee86248c JB |
13212 | char *end; |
13213 | const reg_entry *r; | |
4d1bb795 | 13214 | |
ee86248c JB |
13215 | switch (*input_line_pointer) |
13216 | { | |
13217 | case REGISTER_PREFIX: | |
13218 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
13219 | if (r) |
13220 | { | |
13221 | e->X_op = O_register; | |
13222 | e->X_add_number = r - i386_regtab; | |
13223 | input_line_pointer = end; | |
13224 | } | |
ee86248c JB |
13225 | break; |
13226 | ||
13227 | case '[': | |
9c2799c2 | 13228 | gas_assert (intel_syntax); |
ee86248c JB |
13229 | end = input_line_pointer++; |
13230 | expression (e); | |
13231 | if (*input_line_pointer == ']') | |
13232 | { | |
13233 | ++input_line_pointer; | |
13234 | e->X_op_symbol = make_expr_symbol (e); | |
13235 | e->X_add_symbol = NULL; | |
13236 | e->X_add_number = 0; | |
13237 | e->X_op = O_index; | |
13238 | } | |
13239 | else | |
13240 | { | |
13241 | e->X_op = O_absent; | |
13242 | input_line_pointer = end; | |
13243 | } | |
13244 | break; | |
4d1bb795 JB |
13245 | } |
13246 | } | |
13247 | ||
252b5132 | 13248 | \f |
4cc782b5 | 13249 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 13250 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 13251 | #else |
b6f8c7c4 | 13252 | const char *md_shortopts = "qnO::"; |
252b5132 | 13253 | #endif |
6e0b89ee | 13254 | |
3e73aa7c | 13255 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
13256 | #define OPTION_64 (OPTION_MD_BASE + 1) |
13257 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
13258 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
13259 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
13260 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
13261 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
13262 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
13263 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 13264 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 13265 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 13266 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
13267 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
13268 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
13269 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 13270 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
13271 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
13272 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 13273 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 13274 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 13275 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 13276 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
13277 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
13278 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 13279 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 13280 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 13281 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
13282 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
13283 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
13284 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 13285 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
13286 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
13287 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
13288 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
c8480b58 | 13289 | #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34) |
b3b91714 | 13290 | |
99ad8390 NC |
13291 | struct option md_longopts[] = |
13292 | { | |
3e73aa7c | 13293 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 13294 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13295 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 13296 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
13297 | #endif |
13298 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 13299 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 13300 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 13301 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 13302 | #endif |
b3b91714 | 13303 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
13304 | {"march", required_argument, NULL, OPTION_MARCH}, |
13305 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
13306 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
13307 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
13308 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
13309 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 13310 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
c8480b58 | 13311 | {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE}, |
daf50ae7 | 13312 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 13313 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 13314 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 13315 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 13316 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
13317 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
13318 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
13319 | # if defined (TE_PE) || defined (TE_PEP) |
13320 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
13321 | #endif | |
d1982f93 | 13322 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 13323 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 13324 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 13325 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
13326 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
13327 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
13328 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 13329 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
13330 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
13331 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
13332 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
13333 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
13334 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
13335 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
13336 | {NULL, no_argument, NULL, 0} |
13337 | }; | |
13338 | size_t md_longopts_size = sizeof (md_longopts); | |
13339 | ||
13340 | int | |
17b9d67d | 13341 | md_parse_option (int c, const char *arg) |
252b5132 | 13342 | { |
91d6fa6a | 13343 | unsigned int j; |
e379e5f3 | 13344 | char *arch, *next, *saved, *type; |
9103f4f4 | 13345 | |
252b5132 RH |
13346 | switch (c) |
13347 | { | |
12b55ccc L |
13348 | case 'n': |
13349 | optimize_align_code = 0; | |
13350 | break; | |
13351 | ||
a38cf1db AM |
13352 | case 'q': |
13353 | quiet_warnings = 1; | |
252b5132 RH |
13354 | break; |
13355 | ||
13356 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
13357 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
13358 | should be emitted or not. FIXME: Not implemented. */ | |
13359 | case 'Q': | |
d4693039 JB |
13360 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
13361 | return 0; | |
252b5132 RH |
13362 | break; |
13363 | ||
13364 | /* -V: SVR4 argument to print version ID. */ | |
13365 | case 'V': | |
13366 | print_version_id (); | |
13367 | break; | |
13368 | ||
a38cf1db AM |
13369 | /* -k: Ignore for FreeBSD compatibility. */ |
13370 | case 'k': | |
252b5132 | 13371 | break; |
4cc782b5 ILT |
13372 | |
13373 | case 's': | |
13374 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 13375 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 13376 | break; |
8dcea932 L |
13377 | |
13378 | case OPTION_MSHARED: | |
13379 | shared = 1; | |
13380 | break; | |
b4a3a7b4 L |
13381 | |
13382 | case OPTION_X86_USED_NOTE: | |
13383 | if (strcasecmp (arg, "yes") == 0) | |
13384 | x86_used_note = 1; | |
13385 | else if (strcasecmp (arg, "no") == 0) | |
13386 | x86_used_note = 0; | |
13387 | else | |
13388 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
13389 | break; | |
13390 | ||
13391 | ||
99ad8390 | 13392 | #endif |
321098a5 | 13393 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13394 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
13395 | case OPTION_64: |
13396 | { | |
13397 | const char **list, **l; | |
13398 | ||
3e73aa7c JH |
13399 | list = bfd_target_list (); |
13400 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13401 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
13402 | || strcmp (*l, "coff-x86-64") == 0 |
13403 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
13404 | || strcmp (*l, "pei-x86-64") == 0 |
13405 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
13406 | { |
13407 | default_arch = "x86_64"; | |
13408 | break; | |
13409 | } | |
3e73aa7c | 13410 | if (*l == NULL) |
2b5d6a91 | 13411 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
13412 | free (list); |
13413 | } | |
13414 | break; | |
13415 | #endif | |
252b5132 | 13416 | |
351f65ca | 13417 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 13418 | case OPTION_X32: |
351f65ca L |
13419 | if (IS_ELF) |
13420 | { | |
13421 | const char **list, **l; | |
13422 | ||
13423 | list = bfd_target_list (); | |
13424 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13425 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
13426 | { |
13427 | default_arch = "x86_64:32"; | |
13428 | break; | |
13429 | } | |
13430 | if (*l == NULL) | |
2b5d6a91 | 13431 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
13432 | free (list); |
13433 | } | |
13434 | else | |
13435 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
13436 | break; | |
13437 | #endif | |
13438 | ||
6e0b89ee AM |
13439 | case OPTION_32: |
13440 | default_arch = "i386"; | |
13441 | break; | |
13442 | ||
b3b91714 AM |
13443 | case OPTION_DIVIDE: |
13444 | #ifdef SVR4_COMMENT_CHARS | |
13445 | { | |
13446 | char *n, *t; | |
13447 | const char *s; | |
13448 | ||
add39d23 | 13449 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
13450 | t = n; |
13451 | for (s = i386_comment_chars; *s != '\0'; s++) | |
13452 | if (*s != '/') | |
13453 | *t++ = *s; | |
13454 | *t = '\0'; | |
13455 | i386_comment_chars = n; | |
13456 | } | |
13457 | #endif | |
13458 | break; | |
13459 | ||
9103f4f4 | 13460 | case OPTION_MARCH: |
293f5f65 L |
13461 | saved = xstrdup (arg); |
13462 | arch = saved; | |
13463 | /* Allow -march=+nosse. */ | |
13464 | if (*arch == '+') | |
13465 | arch++; | |
6305a203 | 13466 | do |
9103f4f4 | 13467 | { |
6305a203 | 13468 | if (*arch == '.') |
2b5d6a91 | 13469 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13470 | next = strchr (arch, '+'); |
13471 | if (next) | |
13472 | *next++ = '\0'; | |
91d6fa6a | 13473 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13474 | { |
ae89daec JB |
13475 | if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE |
13476 | && strcmp (arch, cpu_arch[j].name) == 0) | |
ccc9c027 | 13477 | { |
6305a203 | 13478 | /* Processor. */ |
ae89daec | 13479 | if (! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
13480 | continue; |
13481 | ||
91d6fa6a | 13482 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 13483 | free (cpu_sub_arch_name); |
6305a203 | 13484 | cpu_sub_arch_name = NULL; |
ae89daec | 13485 | cpu_arch_flags = cpu_arch[j].enable; |
91d6fa6a | 13486 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 13487 | cpu_arch_isa_flags = cpu_arch[j].enable; |
6305a203 L |
13488 | if (!cpu_arch_tune_set) |
13489 | { | |
13490 | cpu_arch_tune = cpu_arch_isa; | |
13491 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13492 | } | |
13493 | break; | |
13494 | } | |
ae89daec JB |
13495 | else if (cpu_arch[j].type == PROCESSOR_NONE |
13496 | && strcmp (arch, cpu_arch[j].name) == 0 | |
13497 | && !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
6305a203 | 13498 | { |
33eaf5de | 13499 | /* ISA extension. */ |
6305a203 | 13500 | i386_cpu_flags flags; |
309d3373 | 13501 | |
293f5f65 | 13502 | flags = cpu_flags_or (cpu_arch_flags, |
ae89daec | 13503 | cpu_arch[j].enable); |
81486035 | 13504 | |
5b64d091 | 13505 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 | 13506 | { |
ae89daec | 13507 | extend_cpu_sub_arch_name (arch); |
6305a203 | 13508 | cpu_arch_flags = flags; |
a586129e | 13509 | cpu_arch_isa_flags = flags; |
6305a203 | 13510 | } |
0089dace L |
13511 | else |
13512 | cpu_arch_isa_flags | |
13513 | = cpu_flags_or (cpu_arch_isa_flags, | |
ae89daec | 13514 | cpu_arch[j].enable); |
6305a203 | 13515 | break; |
ccc9c027 | 13516 | } |
9103f4f4 | 13517 | } |
6305a203 | 13518 | |
ae89daec | 13519 | if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no")) |
293f5f65 | 13520 | { |
33eaf5de | 13521 | /* Disable an ISA extension. */ |
ae89daec JB |
13522 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
13523 | if (cpu_arch[j].type == PROCESSOR_NONE | |
13524 | && strcmp (arch + 2, cpu_arch[j].name) == 0) | |
293f5f65 L |
13525 | { |
13526 | i386_cpu_flags flags; | |
13527 | ||
13528 | flags = cpu_flags_and_not (cpu_arch_flags, | |
ae89daec | 13529 | cpu_arch[j].disable); |
293f5f65 L |
13530 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
13531 | { | |
8180707f | 13532 | extend_cpu_sub_arch_name (arch); |
293f5f65 L |
13533 | cpu_arch_flags = flags; |
13534 | cpu_arch_isa_flags = flags; | |
13535 | } | |
13536 | break; | |
13537 | } | |
293f5f65 L |
13538 | } |
13539 | ||
91d6fa6a | 13540 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13541 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13542 | |
13543 | arch = next; | |
9103f4f4 | 13544 | } |
293f5f65 L |
13545 | while (next != NULL); |
13546 | free (saved); | |
9103f4f4 L |
13547 | break; |
13548 | ||
13549 | case OPTION_MTUNE: | |
13550 | if (*arg == '.') | |
2b5d6a91 | 13551 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 13552 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13553 | { |
ae89daec JB |
13554 | if (cpu_arch[j].type != PROCESSOR_NONE |
13555 | && strcmp (arg, cpu_arch[j].name) == 0) | |
9103f4f4 | 13556 | { |
ccc9c027 | 13557 | cpu_arch_tune_set = 1; |
91d6fa6a | 13558 | cpu_arch_tune = cpu_arch [j].type; |
ae89daec | 13559 | cpu_arch_tune_flags = cpu_arch[j].enable; |
9103f4f4 L |
13560 | break; |
13561 | } | |
13562 | } | |
91d6fa6a | 13563 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13564 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
13565 | break; |
13566 | ||
1efbbeb4 L |
13567 | case OPTION_MMNEMONIC: |
13568 | if (strcasecmp (arg, "att") == 0) | |
13569 | intel_mnemonic = 0; | |
13570 | else if (strcasecmp (arg, "intel") == 0) | |
13571 | intel_mnemonic = 1; | |
13572 | else | |
2b5d6a91 | 13573 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
13574 | break; |
13575 | ||
13576 | case OPTION_MSYNTAX: | |
13577 | if (strcasecmp (arg, "att") == 0) | |
13578 | intel_syntax = 0; | |
13579 | else if (strcasecmp (arg, "intel") == 0) | |
13580 | intel_syntax = 1; | |
13581 | else | |
2b5d6a91 | 13582 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
13583 | break; |
13584 | ||
13585 | case OPTION_MINDEX_REG: | |
13586 | allow_index_reg = 1; | |
13587 | break; | |
13588 | ||
13589 | case OPTION_MNAKED_REG: | |
13590 | allow_naked_reg = 1; | |
13591 | break; | |
13592 | ||
c0f3af97 L |
13593 | case OPTION_MSSE2AVX: |
13594 | sse2avx = 1; | |
13595 | break; | |
13596 | ||
c8480b58 L |
13597 | case OPTION_MUSE_UNALIGNED_VECTOR_MOVE: |
13598 | use_unaligned_vector_move = 1; | |
13599 | break; | |
13600 | ||
daf50ae7 L |
13601 | case OPTION_MSSE_CHECK: |
13602 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 13603 | sse_check = check_error; |
daf50ae7 | 13604 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 13605 | sse_check = check_warning; |
daf50ae7 | 13606 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 13607 | sse_check = check_none; |
daf50ae7 | 13608 | else |
2b5d6a91 | 13609 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
13610 | break; |
13611 | ||
7bab8ab5 JB |
13612 | case OPTION_MOPERAND_CHECK: |
13613 | if (strcasecmp (arg, "error") == 0) | |
13614 | operand_check = check_error; | |
13615 | else if (strcasecmp (arg, "warning") == 0) | |
13616 | operand_check = check_warning; | |
13617 | else if (strcasecmp (arg, "none") == 0) | |
13618 | operand_check = check_none; | |
13619 | else | |
13620 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
13621 | break; | |
13622 | ||
539f890d L |
13623 | case OPTION_MAVXSCALAR: |
13624 | if (strcasecmp (arg, "128") == 0) | |
13625 | avxscalar = vex128; | |
13626 | else if (strcasecmp (arg, "256") == 0) | |
13627 | avxscalar = vex256; | |
13628 | else | |
2b5d6a91 | 13629 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
13630 | break; |
13631 | ||
03751133 L |
13632 | case OPTION_MVEXWIG: |
13633 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 13634 | vexwig = vexw0; |
03751133 | 13635 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 13636 | vexwig = vexw1; |
03751133 L |
13637 | else |
13638 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
13639 | break; | |
13640 | ||
7e8b059b L |
13641 | case OPTION_MADD_BND_PREFIX: |
13642 | add_bnd_prefix = 1; | |
13643 | break; | |
13644 | ||
43234a1e L |
13645 | case OPTION_MEVEXLIG: |
13646 | if (strcmp (arg, "128") == 0) | |
13647 | evexlig = evexl128; | |
13648 | else if (strcmp (arg, "256") == 0) | |
13649 | evexlig = evexl256; | |
13650 | else if (strcmp (arg, "512") == 0) | |
13651 | evexlig = evexl512; | |
13652 | else | |
13653 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
13654 | break; | |
13655 | ||
d3d3c6db IT |
13656 | case OPTION_MEVEXRCIG: |
13657 | if (strcmp (arg, "rne") == 0) | |
13658 | evexrcig = rne; | |
13659 | else if (strcmp (arg, "rd") == 0) | |
13660 | evexrcig = rd; | |
13661 | else if (strcmp (arg, "ru") == 0) | |
13662 | evexrcig = ru; | |
13663 | else if (strcmp (arg, "rz") == 0) | |
13664 | evexrcig = rz; | |
13665 | else | |
13666 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
13667 | break; | |
13668 | ||
43234a1e L |
13669 | case OPTION_MEVEXWIG: |
13670 | if (strcmp (arg, "0") == 0) | |
13671 | evexwig = evexw0; | |
13672 | else if (strcmp (arg, "1") == 0) | |
13673 | evexwig = evexw1; | |
13674 | else | |
13675 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
13676 | break; | |
13677 | ||
167ad85b TG |
13678 | # if defined (TE_PE) || defined (TE_PEP) |
13679 | case OPTION_MBIG_OBJ: | |
13680 | use_big_obj = 1; | |
13681 | break; | |
13682 | #endif | |
13683 | ||
d1982f93 | 13684 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
13685 | if (strcasecmp (arg, "yes") == 0) |
13686 | omit_lock_prefix = 1; | |
13687 | else if (strcasecmp (arg, "no") == 0) | |
13688 | omit_lock_prefix = 0; | |
13689 | else | |
13690 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
13691 | break; | |
13692 | ||
e4e00185 AS |
13693 | case OPTION_MFENCE_AS_LOCK_ADD: |
13694 | if (strcasecmp (arg, "yes") == 0) | |
13695 | avoid_fence = 1; | |
13696 | else if (strcasecmp (arg, "no") == 0) | |
13697 | avoid_fence = 0; | |
13698 | else | |
13699 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
13700 | break; | |
13701 | ||
ae531041 L |
13702 | case OPTION_MLFENCE_AFTER_LOAD: |
13703 | if (strcasecmp (arg, "yes") == 0) | |
13704 | lfence_after_load = 1; | |
13705 | else if (strcasecmp (arg, "no") == 0) | |
13706 | lfence_after_load = 0; | |
13707 | else | |
13708 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
13709 | break; | |
13710 | ||
13711 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
13712 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 13713 | { |
13714 | lfence_before_indirect_branch = lfence_branch_all; | |
13715 | if (lfence_before_ret == lfence_before_ret_none) | |
13716 | lfence_before_ret = lfence_before_ret_shl; | |
13717 | } | |
ae531041 L |
13718 | else if (strcasecmp (arg, "memory") == 0) |
13719 | lfence_before_indirect_branch = lfence_branch_memory; | |
13720 | else if (strcasecmp (arg, "register") == 0) | |
13721 | lfence_before_indirect_branch = lfence_branch_register; | |
13722 | else if (strcasecmp (arg, "none") == 0) | |
13723 | lfence_before_indirect_branch = lfence_branch_none; | |
13724 | else | |
13725 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
13726 | arg); | |
13727 | break; | |
13728 | ||
13729 | case OPTION_MLFENCE_BEFORE_RET: | |
13730 | if (strcasecmp (arg, "or") == 0) | |
13731 | lfence_before_ret = lfence_before_ret_or; | |
13732 | else if (strcasecmp (arg, "not") == 0) | |
13733 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 13734 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
13735 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
13736 | else if (strcasecmp (arg, "none") == 0) |
13737 | lfence_before_ret = lfence_before_ret_none; | |
13738 | else | |
13739 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
13740 | arg); | |
13741 | break; | |
13742 | ||
0cb4071e L |
13743 | case OPTION_MRELAX_RELOCATIONS: |
13744 | if (strcasecmp (arg, "yes") == 0) | |
13745 | generate_relax_relocations = 1; | |
13746 | else if (strcasecmp (arg, "no") == 0) | |
13747 | generate_relax_relocations = 0; | |
13748 | else | |
13749 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
13750 | break; | |
13751 | ||
e379e5f3 L |
13752 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
13753 | { | |
13754 | char *end; | |
13755 | long int align = strtoul (arg, &end, 0); | |
13756 | if (*end == '\0') | |
13757 | { | |
13758 | if (align == 0) | |
13759 | { | |
13760 | align_branch_power = 0; | |
13761 | break; | |
13762 | } | |
13763 | else if (align >= 16) | |
13764 | { | |
13765 | int align_power; | |
13766 | for (align_power = 0; | |
13767 | (align & 1) == 0; | |
13768 | align >>= 1, align_power++) | |
13769 | continue; | |
13770 | /* Limit alignment power to 31. */ | |
13771 | if (align == 1 && align_power < 32) | |
13772 | { | |
13773 | align_branch_power = align_power; | |
13774 | break; | |
13775 | } | |
13776 | } | |
13777 | } | |
13778 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
13779 | } | |
13780 | break; | |
13781 | ||
13782 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
13783 | { | |
13784 | char *end; | |
13785 | int align = strtoul (arg, &end, 0); | |
13786 | /* Some processors only support 5 prefixes. */ | |
13787 | if (*end == '\0' && align >= 0 && align < 6) | |
13788 | { | |
13789 | align_branch_prefix_size = align; | |
13790 | break; | |
13791 | } | |
13792 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
13793 | arg); | |
13794 | } | |
13795 | break; | |
13796 | ||
13797 | case OPTION_MALIGN_BRANCH: | |
13798 | align_branch = 0; | |
13799 | saved = xstrdup (arg); | |
13800 | type = saved; | |
13801 | do | |
13802 | { | |
13803 | next = strchr (type, '+'); | |
13804 | if (next) | |
13805 | *next++ = '\0'; | |
13806 | if (strcasecmp (type, "jcc") == 0) | |
13807 | align_branch |= align_branch_jcc_bit; | |
13808 | else if (strcasecmp (type, "fused") == 0) | |
13809 | align_branch |= align_branch_fused_bit; | |
13810 | else if (strcasecmp (type, "jmp") == 0) | |
13811 | align_branch |= align_branch_jmp_bit; | |
13812 | else if (strcasecmp (type, "call") == 0) | |
13813 | align_branch |= align_branch_call_bit; | |
13814 | else if (strcasecmp (type, "ret") == 0) | |
13815 | align_branch |= align_branch_ret_bit; | |
13816 | else if (strcasecmp (type, "indirect") == 0) | |
13817 | align_branch |= align_branch_indirect_bit; | |
13818 | else | |
13819 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
13820 | type = next; | |
13821 | } | |
13822 | while (next != NULL); | |
13823 | free (saved); | |
13824 | break; | |
13825 | ||
76cf450b L |
13826 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
13827 | align_branch_power = 5; | |
13828 | align_branch_prefix_size = 5; | |
13829 | align_branch = (align_branch_jcc_bit | |
13830 | | align_branch_fused_bit | |
13831 | | align_branch_jmp_bit); | |
13832 | break; | |
13833 | ||
5db04b09 | 13834 | case OPTION_MAMD64: |
4b5aaf5f | 13835 | isa64 = amd64; |
5db04b09 L |
13836 | break; |
13837 | ||
13838 | case OPTION_MINTEL64: | |
4b5aaf5f | 13839 | isa64 = intel64; |
5db04b09 L |
13840 | break; |
13841 | ||
b6f8c7c4 L |
13842 | case 'O': |
13843 | if (arg == NULL) | |
13844 | { | |
13845 | optimize = 1; | |
13846 | /* Turn off -Os. */ | |
13847 | optimize_for_space = 0; | |
13848 | } | |
13849 | else if (*arg == 's') | |
13850 | { | |
13851 | optimize_for_space = 1; | |
13852 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 13853 | optimize = INT_MAX; |
b6f8c7c4 L |
13854 | } |
13855 | else | |
13856 | { | |
13857 | optimize = atoi (arg); | |
13858 | /* Turn off -Os. */ | |
13859 | optimize_for_space = 0; | |
13860 | } | |
13861 | break; | |
13862 | ||
252b5132 RH |
13863 | default: |
13864 | return 0; | |
13865 | } | |
13866 | return 1; | |
13867 | } | |
13868 | ||
8a2c8fef L |
13869 | #define MESSAGE_TEMPLATE \ |
13870 | " " | |
13871 | ||
293f5f65 L |
13872 | static char * |
13873 | output_message (FILE *stream, char *p, char *message, char *start, | |
13874 | int *left_p, const char *name, int len) | |
13875 | { | |
13876 | int size = sizeof (MESSAGE_TEMPLATE); | |
13877 | int left = *left_p; | |
13878 | ||
13879 | /* Reserve 2 spaces for ", " or ",\0" */ | |
13880 | left -= len + 2; | |
13881 | ||
13882 | /* Check if there is any room. */ | |
13883 | if (left >= 0) | |
13884 | { | |
13885 | if (p != start) | |
13886 | { | |
13887 | *p++ = ','; | |
13888 | *p++ = ' '; | |
13889 | } | |
13890 | p = mempcpy (p, name, len); | |
13891 | } | |
13892 | else | |
13893 | { | |
13894 | /* Output the current message now and start a new one. */ | |
13895 | *p++ = ','; | |
13896 | *p = '\0'; | |
13897 | fprintf (stream, "%s\n", message); | |
13898 | p = start; | |
13899 | left = size - (start - message) - len - 2; | |
13900 | ||
13901 | gas_assert (left >= 0); | |
13902 | ||
13903 | p = mempcpy (p, name, len); | |
13904 | } | |
13905 | ||
13906 | *left_p = left; | |
13907 | return p; | |
13908 | } | |
13909 | ||
8a2c8fef | 13910 | static void |
1ded5609 | 13911 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
13912 | { |
13913 | static char message[] = MESSAGE_TEMPLATE; | |
13914 | char *start = message + 27; | |
13915 | char *p; | |
13916 | int size = sizeof (MESSAGE_TEMPLATE); | |
13917 | int left; | |
13918 | const char *name; | |
13919 | int len; | |
13920 | unsigned int j; | |
13921 | ||
13922 | p = start; | |
13923 | left = size - (start - message); | |
3ce2ebcf JB |
13924 | |
13925 | if (!ext && check) | |
13926 | { | |
13927 | p = output_message (stream, p, message, start, &left, | |
13928 | STRING_COMMA_LEN ("default")); | |
f68697e8 JB |
13929 | p = output_message (stream, p, message, start, &left, |
13930 | STRING_COMMA_LEN ("push")); | |
13931 | p = output_message (stream, p, message, start, &left, | |
13932 | STRING_COMMA_LEN ("pop")); | |
3ce2ebcf JB |
13933 | } |
13934 | ||
8a2c8fef L |
13935 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
13936 | { | |
13937 | /* Should it be skipped? */ | |
13938 | if (cpu_arch [j].skip) | |
13939 | continue; | |
13940 | ||
13941 | name = cpu_arch [j].name; | |
13942 | len = cpu_arch [j].len; | |
ae89daec | 13943 | if (cpu_arch[j].type == PROCESSOR_NONE) |
8a2c8fef L |
13944 | { |
13945 | /* It is an extension. Skip if we aren't asked to show it. */ | |
ae89daec | 13946 | if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable)) |
8a2c8fef L |
13947 | continue; |
13948 | } | |
13949 | else if (ext) | |
13950 | { | |
13951 | /* It is an processor. Skip if we show only extension. */ | |
13952 | continue; | |
13953 | } | |
ae89daec | 13954 | else if (check && ! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
13955 | { |
13956 | /* It is an impossible processor - skip. */ | |
13957 | continue; | |
13958 | } | |
8a2c8fef | 13959 | |
293f5f65 | 13960 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
13961 | } |
13962 | ||
293f5f65 L |
13963 | /* Display disabled extensions. */ |
13964 | if (ext) | |
ae89daec | 13965 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
293f5f65 | 13966 | { |
ae89daec JB |
13967 | char *str; |
13968 | ||
13969 | if (cpu_arch[j].type != PROCESSOR_NONE | |
13970 | || !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
13971 | continue; | |
13972 | str = xasprintf ("no%s", cpu_arch[j].name); | |
13973 | p = output_message (stream, p, message, start, &left, str, | |
13974 | strlen (str)); | |
13975 | free (str); | |
293f5f65 L |
13976 | } |
13977 | ||
8a2c8fef L |
13978 | *p = '\0'; |
13979 | fprintf (stream, "%s\n", message); | |
13980 | } | |
13981 | ||
252b5132 | 13982 | void |
8a2c8fef | 13983 | md_show_usage (FILE *stream) |
252b5132 | 13984 | { |
4cc782b5 ILT |
13985 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13986 | fprintf (stream, _("\ | |
d4693039 | 13987 | -Qy, -Qn ignored\n\ |
a38cf1db | 13988 | -V print assembler version number\n\ |
b3b91714 AM |
13989 | -k ignored\n")); |
13990 | #endif | |
13991 | fprintf (stream, _("\ | |
7ebd68d1 NC |
13992 | -n do not optimize code alignment\n\ |
13993 | -O{012s} attempt some code optimizations\n\ | |
b3b91714 AM |
13994 | -q quieten some warnings\n")); |
13995 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13996 | fprintf (stream, _("\ | |
a38cf1db | 13997 | -s ignored\n")); |
b3b91714 | 13998 | #endif |
b00af7c8 JB |
13999 | #ifdef BFD64 |
14000 | # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14001 | fprintf (stream, _("\ | |
14002 | --32/--64/--x32 generate 32bit/64bit/x32 object\n")); | |
14003 | # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O) | |
751d281c | 14004 | fprintf (stream, _("\ |
b00af7c8 JB |
14005 | --32/--64 generate 32bit/64bit object\n")); |
14006 | # endif | |
751d281c | 14007 | #endif |
b3b91714 AM |
14008 | #ifdef SVR4_COMMENT_CHARS |
14009 | fprintf (stream, _("\ | |
14010 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
14011 | #else |
14012 | fprintf (stream, _("\ | |
b3b91714 | 14013 | --divide ignored\n")); |
4cc782b5 | 14014 | #endif |
9103f4f4 | 14015 | fprintf (stream, _("\ |
6305a203 | 14016 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 14017 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 14018 | show_arch (stream, 0, 1); |
8a2c8fef | 14019 | fprintf (stream, _("\ |
ae89daec | 14020 | EXTENSION is combination of (possibly \"no\"-prefixed):\n")); |
1ded5609 | 14021 | show_arch (stream, 1, 0); |
6305a203 | 14022 | fprintf (stream, _("\ |
8a2c8fef | 14023 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 14024 | show_arch (stream, 0, 0); |
ba104c83 | 14025 | fprintf (stream, _("\ |
c0f3af97 L |
14026 | -msse2avx encode SSE instructions with VEX prefix\n")); |
14027 | fprintf (stream, _("\ | |
c8480b58 L |
14028 | -muse-unaligned-vector-move\n\ |
14029 | encode aligned vector move as unaligned vector move\n")); | |
14030 | fprintf (stream, _("\ | |
7c5c05ef | 14031 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
14032 | check SSE instructions\n")); |
14033 | fprintf (stream, _("\ | |
7c5c05ef | 14034 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
14035 | check operand combinations for validity\n")); |
14036 | fprintf (stream, _("\ | |
7c5c05ef L |
14037 | -mavxscalar=[128|256] (default: 128)\n\ |
14038 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
14039 | length\n")); |
14040 | fprintf (stream, _("\ | |
03751133 L |
14041 | -mvexwig=[0|1] (default: 0)\n\ |
14042 | encode VEX instructions with specific VEX.W value\n\ | |
14043 | for VEX.W bit ignored instructions\n")); | |
14044 | fprintf (stream, _("\ | |
7c5c05ef L |
14045 | -mevexlig=[128|256|512] (default: 128)\n\ |
14046 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
14047 | length\n")); |
14048 | fprintf (stream, _("\ | |
7c5c05ef L |
14049 | -mevexwig=[0|1] (default: 0)\n\ |
14050 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
14051 | for EVEX.W bit ignored instructions\n")); |
14052 | fprintf (stream, _("\ | |
7c5c05ef | 14053 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
14054 | encode EVEX instructions with specific EVEX.RC value\n\ |
14055 | for SAE-only ignored instructions\n")); | |
14056 | fprintf (stream, _("\ | |
7c5c05ef L |
14057 | -mmnemonic=[att|intel] ")); |
14058 | if (SYSV386_COMPAT) | |
14059 | fprintf (stream, _("(default: att)\n")); | |
14060 | else | |
14061 | fprintf (stream, _("(default: intel)\n")); | |
14062 | fprintf (stream, _("\ | |
14063 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 14064 | fprintf (stream, _("\ |
7c5c05ef L |
14065 | -msyntax=[att|intel] (default: att)\n\ |
14066 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
14067 | fprintf (stream, _("\ |
14068 | -mindex-reg support pseudo index registers\n")); | |
14069 | fprintf (stream, _("\ | |
14070 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
14071 | fprintf (stream, _("\ | |
7e8b059b | 14072 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 14073 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
14074 | fprintf (stream, _("\ |
14075 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
14076 | fprintf (stream, _("\ |
14077 | -mx86-used-note=[no|yes] ")); | |
14078 | if (DEFAULT_X86_USED_NOTE) | |
14079 | fprintf (stream, _("(default: yes)\n")); | |
14080 | else | |
14081 | fprintf (stream, _("(default: no)\n")); | |
14082 | fprintf (stream, _("\ | |
14083 | generate x86 used ISA and feature properties\n")); | |
14084 | #endif | |
14085 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
14086 | fprintf (stream, _("\ |
14087 | -mbig-obj generate big object files\n")); | |
14088 | #endif | |
d022bddd | 14089 | fprintf (stream, _("\ |
7c5c05ef | 14090 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 14091 | strip all lock prefixes\n")); |
5db04b09 | 14092 | fprintf (stream, _("\ |
7c5c05ef | 14093 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
14094 | encode lfence, mfence and sfence as\n\ |
14095 | lock addl $0x0, (%%{re}sp)\n")); | |
14096 | fprintf (stream, _("\ | |
7c5c05ef L |
14097 | -mrelax-relocations=[no|yes] ")); |
14098 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
14099 | fprintf (stream, _("(default: yes)\n")); | |
14100 | else | |
14101 | fprintf (stream, _("(default: no)\n")); | |
14102 | fprintf (stream, _("\ | |
0cb4071e L |
14103 | generate relax relocations\n")); |
14104 | fprintf (stream, _("\ | |
e379e5f3 L |
14105 | -malign-branch-boundary=NUM (default: 0)\n\ |
14106 | align branches within NUM byte boundary\n")); | |
14107 | fprintf (stream, _("\ | |
14108 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
14109 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
14110 | indirect\n\ | |
14111 | specify types of branches to align\n")); | |
14112 | fprintf (stream, _("\ | |
14113 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
14114 | align branches with NUM prefixes per instruction\n")); | |
14115 | fprintf (stream, _("\ | |
76cf450b L |
14116 | -mbranches-within-32B-boundaries\n\ |
14117 | align branches within 32 byte boundary\n")); | |
14118 | fprintf (stream, _("\ | |
ae531041 L |
14119 | -mlfence-after-load=[no|yes] (default: no)\n\ |
14120 | generate lfence after load\n")); | |
14121 | fprintf (stream, _("\ | |
14122 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
14123 | generate lfence before indirect near branch\n")); | |
14124 | fprintf (stream, _("\ | |
a09f656b | 14125 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
14126 | generate lfence before ret\n")); |
14127 | fprintf (stream, _("\ | |
7c5c05ef | 14128 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
14129 | fprintf (stream, _("\ |
14130 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
14131 | } |
14132 | ||
3e73aa7c | 14133 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 14134 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 14135 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
14136 | |
14137 | /* Pick the target format to use. */ | |
14138 | ||
47926f60 | 14139 | const char * |
e3bb37b5 | 14140 | i386_target_format (void) |
252b5132 | 14141 | { |
d34049e8 | 14142 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
14143 | { |
14144 | update_code_flag (CODE_64BIT, 1); | |
14145 | if (default_arch[6] == '\0') | |
7f56bc95 | 14146 | x86_elf_abi = X86_64_ABI; |
351f65ca | 14147 | else |
7f56bc95 | 14148 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 14149 | } |
3e73aa7c | 14150 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 14151 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
14152 | else if (!strcmp (default_arch, "iamcu")) |
14153 | { | |
14154 | update_code_flag (CODE_32BIT, 1); | |
14155 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
14156 | { | |
14157 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
14158 | cpu_arch_name = "iamcu"; | |
d92c7521 | 14159 | free (cpu_sub_arch_name); |
5197d474 L |
14160 | cpu_sub_arch_name = NULL; |
14161 | cpu_arch_flags = iamcu_flags; | |
14162 | cpu_arch_isa = PROCESSOR_IAMCU; | |
14163 | cpu_arch_isa_flags = iamcu_flags; | |
14164 | if (!cpu_arch_tune_set) | |
14165 | { | |
14166 | cpu_arch_tune = cpu_arch_isa; | |
14167 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
14168 | } | |
14169 | } | |
8d471ec1 | 14170 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
14171 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
14172 | cpu_arch_name); | |
14173 | } | |
3e73aa7c | 14174 | else |
2b5d6a91 | 14175 | as_fatal (_("unknown architecture")); |
89507696 JB |
14176 | |
14177 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
ae89daec | 14178 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 14179 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
ae89daec | 14180 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 14181 | |
252b5132 RH |
14182 | switch (OUTPUT_FLAVOR) |
14183 | { | |
9384f2ff | 14184 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 14185 | case bfd_target_aout_flavour: |
47926f60 | 14186 | return AOUT_TARGET_FORMAT; |
4c63da97 | 14187 | #endif |
9384f2ff AM |
14188 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
14189 | # if defined (TE_PE) || defined (TE_PEP) | |
14190 | case bfd_target_coff_flavour: | |
167ad85b | 14191 | if (flag_code == CODE_64BIT) |
eb19308f JB |
14192 | { |
14193 | object_64bit = 1; | |
14194 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
14195 | } | |
14196 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 14197 | # elif defined (TE_GO32) |
0561d57c JK |
14198 | case bfd_target_coff_flavour: |
14199 | return "coff-go32"; | |
9384f2ff | 14200 | # else |
252b5132 RH |
14201 | case bfd_target_coff_flavour: |
14202 | return "coff-i386"; | |
9384f2ff | 14203 | # endif |
4c63da97 | 14204 | #endif |
3e73aa7c | 14205 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 14206 | case bfd_target_elf_flavour: |
3e73aa7c | 14207 | { |
351f65ca L |
14208 | const char *format; |
14209 | ||
14210 | switch (x86_elf_abi) | |
4fa24527 | 14211 | { |
351f65ca L |
14212 | default: |
14213 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
14214 | #ifndef TE_SOLARIS |
14215 | tls_get_addr = "___tls_get_addr"; | |
14216 | #endif | |
351f65ca | 14217 | break; |
7f56bc95 | 14218 | case X86_64_ABI: |
351f65ca | 14219 | use_rela_relocations = 1; |
4fa24527 | 14220 | object_64bit = 1; |
e379e5f3 L |
14221 | #ifndef TE_SOLARIS |
14222 | tls_get_addr = "__tls_get_addr"; | |
14223 | #endif | |
351f65ca L |
14224 | format = ELF_TARGET_FORMAT64; |
14225 | break; | |
7f56bc95 | 14226 | case X86_64_X32_ABI: |
4fa24527 | 14227 | use_rela_relocations = 1; |
351f65ca | 14228 | object_64bit = 1; |
e379e5f3 L |
14229 | #ifndef TE_SOLARIS |
14230 | tls_get_addr = "__tls_get_addr"; | |
14231 | #endif | |
862be3fb | 14232 | disallow_64bit_reloc = 1; |
351f65ca L |
14233 | format = ELF_TARGET_FORMAT32; |
14234 | break; | |
4fa24527 | 14235 | } |
c085ab00 | 14236 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
14237 | { |
14238 | if (x86_elf_abi != I386_ABI) | |
14239 | as_fatal (_("Intel MCU is 32bit only")); | |
14240 | return ELF_TARGET_IAMCU_FORMAT; | |
14241 | } | |
8a9036a4 | 14242 | else |
351f65ca | 14243 | return format; |
3e73aa7c | 14244 | } |
e57f8c65 TG |
14245 | #endif |
14246 | #if defined (OBJ_MACH_O) | |
14247 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
14248 | if (flag_code == CODE_64BIT) |
14249 | { | |
14250 | use_rela_relocations = 1; | |
14251 | object_64bit = 1; | |
14252 | return "mach-o-x86-64"; | |
14253 | } | |
14254 | else | |
14255 | return "mach-o-i386"; | |
4c63da97 | 14256 | #endif |
252b5132 RH |
14257 | default: |
14258 | abort (); | |
14259 | return NULL; | |
14260 | } | |
14261 | } | |
14262 | ||
47926f60 | 14263 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 14264 | \f |
252b5132 | 14265 | symbolS * |
7016a5d5 | 14266 | md_undefined_symbol (char *name) |
252b5132 | 14267 | { |
18dc2407 ILT |
14268 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
14269 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
14270 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
14271 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
14272 | { |
14273 | if (!GOT_symbol) | |
14274 | { | |
14275 | if (symbol_find (name)) | |
14276 | as_bad (_("GOT already in symbol table")); | |
14277 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 14278 | &zero_address_frag, 0); |
24eab124 AM |
14279 | }; |
14280 | return GOT_symbol; | |
14281 | } | |
252b5132 RH |
14282 | return 0; |
14283 | } | |
14284 | ||
14285 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 14286 | |
252b5132 | 14287 | valueT |
7016a5d5 | 14288 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 14289 | { |
4c63da97 AM |
14290 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
14291 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
14292 | { | |
14293 | /* For a.out, force the section size to be aligned. If we don't do | |
14294 | this, BFD will align it for us, but it will not write out the | |
14295 | final bytes of the section. This may be a bug in BFD, but it is | |
14296 | easier to fix it here since that is how the other a.out targets | |
14297 | work. */ | |
14298 | int align; | |
14299 | ||
fd361982 | 14300 | align = bfd_section_alignment (segment); |
8d3842cd | 14301 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 14302 | } |
252b5132 RH |
14303 | #endif |
14304 | ||
14305 | return size; | |
14306 | } | |
14307 | ||
14308 | /* On the i386, PC-relative offsets are relative to the start of the | |
14309 | next instruction. That is, the address of the offset, plus its | |
14310 | size, since the offset is always the last part of the insn. */ | |
14311 | ||
14312 | long | |
e3bb37b5 | 14313 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
14314 | { |
14315 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
14316 | } | |
14317 | ||
14318 | #ifndef I386COFF | |
14319 | ||
14320 | static void | |
e3bb37b5 | 14321 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14322 | { |
29b0f896 | 14323 | int temp; |
252b5132 | 14324 | |
8a75718c JB |
14325 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14326 | if (IS_ELF) | |
14327 | obj_elf_section_change_hook (); | |
14328 | #endif | |
252b5132 RH |
14329 | temp = get_absolute_expression (); |
14330 | subseg_set (bss_section, (subsegT) temp); | |
14331 | demand_empty_rest_of_line (); | |
14332 | } | |
14333 | ||
14334 | #endif | |
14335 | ||
e379e5f3 L |
14336 | /* Remember constant directive. */ |
14337 | ||
14338 | void | |
14339 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
14340 | { | |
14341 | if (last_insn.kind != last_insn_directive | |
14342 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
14343 | { | |
14344 | last_insn.seg = now_seg; | |
14345 | last_insn.kind = last_insn_directive; | |
14346 | last_insn.name = "constant directive"; | |
14347 | last_insn.file = as_where (&last_insn.line); | |
ae531041 L |
14348 | if (lfence_before_ret != lfence_before_ret_none) |
14349 | { | |
14350 | if (lfence_before_indirect_branch != lfence_branch_none) | |
14351 | as_warn (_("constant directive skips -mlfence-before-ret " | |
14352 | "and -mlfence-before-indirect-branch")); | |
14353 | else | |
14354 | as_warn (_("constant directive skips -mlfence-before-ret")); | |
14355 | } | |
14356 | else if (lfence_before_indirect_branch != lfence_branch_none) | |
14357 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); | |
e379e5f3 L |
14358 | } |
14359 | } | |
14360 | ||
3abbafc2 | 14361 | int |
e3bb37b5 | 14362 | i386_validate_fix (fixS *fixp) |
252b5132 | 14363 | { |
e52a16f2 JB |
14364 | if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section) |
14365 | { | |
14366 | reloc_howto_type *howto; | |
14367 | ||
14368 | howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
14369 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14370 | _("invalid %s relocation against register"), | |
14371 | howto ? howto->name : "<unknown>"); | |
14372 | return 0; | |
14373 | } | |
14374 | ||
3abbafc2 JB |
14375 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14376 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
14377 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
14378 | return IS_ELF && fixp->fx_addsy | |
14379 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
14380 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
14381 | #endif | |
14382 | ||
02a86693 | 14383 | if (fixp->fx_subsy) |
252b5132 | 14384 | { |
02a86693 | 14385 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 14386 | { |
02a86693 L |
14387 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
14388 | { | |
14389 | if (!object_64bit) | |
14390 | abort (); | |
14391 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14392 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
14393 | fixp->fx_r_type = (fixp->fx_tcbit |
14394 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
14395 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
14396 | else |
14397 | #endif | |
14398 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
14399 | } | |
d6ab8113 | 14400 | else |
02a86693 L |
14401 | { |
14402 | if (!object_64bit) | |
14403 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
14404 | else | |
14405 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
14406 | } | |
14407 | fixp->fx_subsy = 0; | |
23df1078 | 14408 | } |
252b5132 | 14409 | } |
02a86693 | 14410 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 14411 | else |
02a86693 | 14412 | { |
2585b7a5 L |
14413 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
14414 | to section. Since PLT32 relocation must be against symbols, | |
14415 | turn such PLT32 relocation into PC32 relocation. */ | |
14416 | if (fixp->fx_addsy | |
14417 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
14418 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
14419 | && symbol_section_p (fixp->fx_addsy)) | |
14420 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
14421 | if (!object_64bit) | |
14422 | { | |
14423 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
14424 | && fixp->fx_tcbit2) | |
14425 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
14426 | } | |
02a86693 L |
14427 | } |
14428 | #endif | |
3abbafc2 JB |
14429 | |
14430 | return 1; | |
252b5132 RH |
14431 | } |
14432 | ||
252b5132 | 14433 | arelent * |
7016a5d5 | 14434 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14435 | { |
14436 | arelent *rel; | |
14437 | bfd_reloc_code_real_type code; | |
14438 | ||
14439 | switch (fixp->fx_r_type) | |
14440 | { | |
8ce3d284 | 14441 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
14442 | symbolS *sym; |
14443 | ||
8fd4256d L |
14444 | case BFD_RELOC_SIZE32: |
14445 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
14446 | if (fixp->fx_addsy |
14447 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
14448 | && (!fixp->fx_subsy | |
14449 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
14450 | sym = fixp->fx_addsy; | |
14451 | else if (fixp->fx_subsy | |
14452 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
14453 | && (!fixp->fx_addsy | |
14454 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
14455 | sym = fixp->fx_subsy; | |
14456 | else | |
14457 | sym = NULL; | |
14458 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
14459 | { |
14460 | /* Resolve size relocation against local symbol to size of | |
14461 | the symbol plus addend. */ | |
3abbafc2 | 14462 | valueT value = S_GET_SIZE (sym); |
44f87162 | 14463 | |
3abbafc2 JB |
14464 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
14465 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
14466 | if (sym == fixp->fx_subsy) | |
14467 | { | |
14468 | value = -value; | |
14469 | if (fixp->fx_addsy) | |
14470 | value += S_GET_VALUE (fixp->fx_addsy); | |
14471 | } | |
14472 | else if (fixp->fx_subsy) | |
14473 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 14474 | value += fixp->fx_offset; |
8fd4256d | 14475 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 14476 | && object_64bit |
8fd4256d L |
14477 | && !fits_in_unsigned_long (value)) |
14478 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14479 | _("symbol size computation overflow")); | |
14480 | fixp->fx_addsy = NULL; | |
14481 | fixp->fx_subsy = NULL; | |
14482 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
14483 | return NULL; | |
14484 | } | |
3abbafc2 JB |
14485 | if (!fixp->fx_addsy || fixp->fx_subsy) |
14486 | { | |
14487 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14488 | "unsupported expression involving @size"); | |
14489 | return NULL; | |
14490 | } | |
8ce3d284 | 14491 | #endif |
1a0670f3 | 14492 | /* Fall through. */ |
8fd4256d | 14493 | |
3e73aa7c JH |
14494 | case BFD_RELOC_X86_64_PLT32: |
14495 | case BFD_RELOC_X86_64_GOT32: | |
14496 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14497 | case BFD_RELOC_X86_64_GOTPCRELX: |
14498 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
14499 | case BFD_RELOC_386_PLT32: |
14500 | case BFD_RELOC_386_GOT32: | |
02a86693 | 14501 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
14502 | case BFD_RELOC_386_GOTOFF: |
14503 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
14504 | case BFD_RELOC_386_TLS_GD: |
14505 | case BFD_RELOC_386_TLS_LDM: | |
14506 | case BFD_RELOC_386_TLS_LDO_32: | |
14507 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
14508 | case BFD_RELOC_386_TLS_IE: |
14509 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
14510 | case BFD_RELOC_386_TLS_LE_32: |
14511 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
14512 | case BFD_RELOC_386_TLS_GOTDESC: |
14513 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
14514 | case BFD_RELOC_X86_64_TLSGD: |
14515 | case BFD_RELOC_X86_64_TLSLD: | |
14516 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 14517 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
14518 | case BFD_RELOC_X86_64_GOTTPOFF: |
14519 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
14520 | case BFD_RELOC_X86_64_TPOFF64: |
14521 | case BFD_RELOC_X86_64_GOTOFF64: | |
14522 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
14523 | case BFD_RELOC_X86_64_GOT64: |
14524 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14525 | case BFD_RELOC_X86_64_GOTPC64: | |
14526 | case BFD_RELOC_X86_64_GOTPLT64: | |
14527 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
14528 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14529 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
14530 | case BFD_RELOC_RVA: |
14531 | case BFD_RELOC_VTABLE_ENTRY: | |
14532 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
14533 | #ifdef TE_PE |
14534 | case BFD_RELOC_32_SECREL: | |
145667f8 | 14535 | case BFD_RELOC_16_SECIDX: |
6482c264 | 14536 | #endif |
252b5132 RH |
14537 | code = fixp->fx_r_type; |
14538 | break; | |
dbbaec26 L |
14539 | case BFD_RELOC_X86_64_32S: |
14540 | if (!fixp->fx_pcrel) | |
14541 | { | |
14542 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
14543 | code = fixp->fx_r_type; | |
14544 | break; | |
14545 | } | |
1a0670f3 | 14546 | /* Fall through. */ |
252b5132 | 14547 | default: |
93382f6d | 14548 | if (fixp->fx_pcrel) |
252b5132 | 14549 | { |
93382f6d AM |
14550 | switch (fixp->fx_size) |
14551 | { | |
14552 | default: | |
b091f402 AM |
14553 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14554 | _("can not do %d byte pc-relative relocation"), | |
14555 | fixp->fx_size); | |
93382f6d AM |
14556 | code = BFD_RELOC_32_PCREL; |
14557 | break; | |
14558 | case 1: code = BFD_RELOC_8_PCREL; break; | |
14559 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 14560 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
14561 | #ifdef BFD64 |
14562 | case 8: code = BFD_RELOC_64_PCREL; break; | |
14563 | #endif | |
93382f6d AM |
14564 | } |
14565 | } | |
14566 | else | |
14567 | { | |
14568 | switch (fixp->fx_size) | |
14569 | { | |
14570 | default: | |
b091f402 AM |
14571 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14572 | _("can not do %d byte relocation"), | |
14573 | fixp->fx_size); | |
93382f6d AM |
14574 | code = BFD_RELOC_32; |
14575 | break; | |
14576 | case 1: code = BFD_RELOC_8; break; | |
14577 | case 2: code = BFD_RELOC_16; break; | |
14578 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 14579 | #ifdef BFD64 |
3e73aa7c | 14580 | case 8: code = BFD_RELOC_64; break; |
937149dd | 14581 | #endif |
93382f6d | 14582 | } |
252b5132 RH |
14583 | } |
14584 | break; | |
14585 | } | |
252b5132 | 14586 | |
d182319b JB |
14587 | if ((code == BFD_RELOC_32 |
14588 | || code == BFD_RELOC_32_PCREL | |
14589 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
14590 | && GOT_symbol |
14591 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 14592 | { |
4fa24527 | 14593 | if (!object_64bit) |
d6ab8113 JB |
14594 | code = BFD_RELOC_386_GOTPC; |
14595 | else | |
14596 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 14597 | } |
7b81dfbb AJ |
14598 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
14599 | && GOT_symbol | |
14600 | && fixp->fx_addsy == GOT_symbol) | |
14601 | { | |
14602 | code = BFD_RELOC_X86_64_GOTPC64; | |
14603 | } | |
252b5132 | 14604 | |
add39d23 TS |
14605 | rel = XNEW (arelent); |
14606 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 14607 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
14608 | |
14609 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 14610 | |
3e73aa7c JH |
14611 | if (!use_rela_relocations) |
14612 | { | |
14613 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
14614 | vtable entry to be used in the relocation's section offset. */ | |
14615 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14616 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
14617 | #if defined (OBJ_COFF) && defined (TE_PE) |
14618 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
14619 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
14620 | else | |
14621 | #endif | |
c6682705 | 14622 | rel->addend = 0; |
3e73aa7c JH |
14623 | } |
14624 | /* Use the rela in 64bit mode. */ | |
252b5132 | 14625 | else |
3e73aa7c | 14626 | { |
862be3fb L |
14627 | if (disallow_64bit_reloc) |
14628 | switch (code) | |
14629 | { | |
862be3fb L |
14630 | case BFD_RELOC_X86_64_DTPOFF64: |
14631 | case BFD_RELOC_X86_64_TPOFF64: | |
14632 | case BFD_RELOC_64_PCREL: | |
14633 | case BFD_RELOC_X86_64_GOTOFF64: | |
14634 | case BFD_RELOC_X86_64_GOT64: | |
14635 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14636 | case BFD_RELOC_X86_64_GOTPC64: | |
14637 | case BFD_RELOC_X86_64_GOTPLT64: | |
14638 | case BFD_RELOC_X86_64_PLTOFF64: | |
14639 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14640 | _("cannot represent relocation type %s in x32 mode"), | |
14641 | bfd_get_reloc_code_name (code)); | |
14642 | break; | |
14643 | default: | |
14644 | break; | |
14645 | } | |
14646 | ||
062cd5e7 AS |
14647 | if (!fixp->fx_pcrel) |
14648 | rel->addend = fixp->fx_offset; | |
14649 | else | |
14650 | switch (code) | |
14651 | { | |
14652 | case BFD_RELOC_X86_64_PLT32: | |
14653 | case BFD_RELOC_X86_64_GOT32: | |
14654 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14655 | case BFD_RELOC_X86_64_GOTPCRELX: |
14656 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
14657 | case BFD_RELOC_X86_64_TLSGD: |
14658 | case BFD_RELOC_X86_64_TLSLD: | |
14659 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
14660 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14661 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
14662 | rel->addend = fixp->fx_offset - fixp->fx_size; |
14663 | break; | |
14664 | default: | |
14665 | rel->addend = (section->vma | |
14666 | - fixp->fx_size | |
14667 | + fixp->fx_addnumber | |
14668 | + md_pcrel_from (fixp)); | |
14669 | break; | |
14670 | } | |
3e73aa7c JH |
14671 | } |
14672 | ||
252b5132 RH |
14673 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
14674 | if (rel->howto == NULL) | |
14675 | { | |
14676 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 14677 | _("cannot represent relocation type %s"), |
252b5132 RH |
14678 | bfd_get_reloc_code_name (code)); |
14679 | /* Set howto to a garbage value so that we can keep going. */ | |
14680 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 14681 | gas_assert (rel->howto != NULL); |
252b5132 RH |
14682 | } |
14683 | ||
14684 | return rel; | |
14685 | } | |
14686 | ||
ee86248c | 14687 | #include "tc-i386-intel.c" |
54cfded0 | 14688 | |
a60de03c JB |
14689 | void |
14690 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 14691 | { |
a60de03c JB |
14692 | int saved_naked_reg; |
14693 | char saved_register_dot; | |
54cfded0 | 14694 | |
a60de03c JB |
14695 | saved_naked_reg = allow_naked_reg; |
14696 | allow_naked_reg = 1; | |
14697 | saved_register_dot = register_chars['.']; | |
14698 | register_chars['.'] = '.'; | |
14699 | allow_pseudo_reg = 1; | |
14700 | expression_and_evaluate (exp); | |
14701 | allow_pseudo_reg = 0; | |
14702 | register_chars['.'] = saved_register_dot; | |
14703 | allow_naked_reg = saved_naked_reg; | |
14704 | ||
e96d56a1 | 14705 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 14706 | { |
a60de03c JB |
14707 | if ((addressT) exp->X_add_number < i386_regtab_size) |
14708 | { | |
14709 | exp->X_op = O_constant; | |
14710 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
14711 | .dw2_regnum[flag_code >> 1]; | |
14712 | } | |
14713 | else | |
14714 | exp->X_op = O_illegal; | |
54cfded0 | 14715 | } |
54cfded0 AM |
14716 | } |
14717 | ||
14718 | void | |
14719 | tc_x86_frame_initial_instructions (void) | |
14720 | { | |
a60de03c JB |
14721 | static unsigned int sp_regno[2]; |
14722 | ||
14723 | if (!sp_regno[flag_code >> 1]) | |
14724 | { | |
14725 | char *saved_input = input_line_pointer; | |
14726 | char sp[][4] = {"esp", "rsp"}; | |
14727 | expressionS exp; | |
a4447b93 | 14728 | |
a60de03c JB |
14729 | input_line_pointer = sp[flag_code >> 1]; |
14730 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 14731 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
14732 | sp_regno[flag_code >> 1] = exp.X_add_number; |
14733 | input_line_pointer = saved_input; | |
14734 | } | |
a4447b93 | 14735 | |
61ff971f L |
14736 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
14737 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 14738 | } |
d2b2c203 | 14739 | |
d7921315 L |
14740 | int |
14741 | x86_dwarf2_addr_size (void) | |
14742 | { | |
14743 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
14744 | if (x86_elf_abi == X86_64_X32_ABI) | |
14745 | return 4; | |
14746 | #endif | |
14747 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
14748 | } | |
14749 | ||
d2b2c203 DJ |
14750 | int |
14751 | i386_elf_section_type (const char *str, size_t len) | |
14752 | { | |
14753 | if (flag_code == CODE_64BIT | |
14754 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 14755 | && startswith (str, "unwind")) |
d2b2c203 DJ |
14756 | return SHT_X86_64_UNWIND; |
14757 | ||
14758 | return -1; | |
14759 | } | |
bb41ade5 | 14760 | |
ad5fec3b EB |
14761 | #ifdef TE_SOLARIS |
14762 | void | |
14763 | i386_solaris_fix_up_eh_frame (segT sec) | |
14764 | { | |
14765 | if (flag_code == CODE_64BIT) | |
14766 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
14767 | } | |
14768 | #endif | |
14769 | ||
bb41ade5 AM |
14770 | #ifdef TE_PE |
14771 | void | |
14772 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
14773 | { | |
91d6fa6a | 14774 | expressionS exp; |
bb41ade5 | 14775 | |
91d6fa6a NC |
14776 | exp.X_op = O_secrel; |
14777 | exp.X_add_symbol = symbol; | |
14778 | exp.X_add_number = 0; | |
14779 | emit_expr (&exp, size); | |
bb41ade5 AM |
14780 | } |
14781 | #endif | |
3b22753a L |
14782 | |
14783 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14784 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
14785 | ||
01e1a5bc | 14786 | bfd_vma |
6d4af3c2 | 14787 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
14788 | { |
14789 | if (flag_code == CODE_64BIT) | |
14790 | { | |
14791 | if (letter == 'l') | |
14792 | return SHF_X86_64_LARGE; | |
14793 | ||
8f3bae45 | 14794 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 14795 | } |
3b22753a | 14796 | else |
8f3bae45 | 14797 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
14798 | return -1; |
14799 | } | |
14800 | ||
01e1a5bc | 14801 | bfd_vma |
3b22753a L |
14802 | x86_64_section_word (char *str, size_t len) |
14803 | { | |
08dedd66 | 14804 | if (len == 5 && flag_code == CODE_64BIT && startswith (str, "large")) |
3b22753a L |
14805 | return SHF_X86_64_LARGE; |
14806 | ||
14807 | return -1; | |
14808 | } | |
14809 | ||
14810 | static void | |
14811 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
14812 | { | |
14813 | if (flag_code != CODE_64BIT) | |
14814 | { | |
14815 | s_comm_internal (0, elf_common_parse); | |
14816 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
14817 | } | |
14818 | else | |
14819 | { | |
14820 | static segT lbss_section; | |
14821 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
14822 | asection *saved_bss_section = bss_section; | |
14823 | ||
14824 | if (lbss_section == NULL) | |
14825 | { | |
14826 | flagword applicable; | |
14827 | segT seg = now_seg; | |
14828 | subsegT subseg = now_subseg; | |
14829 | ||
14830 | /* The .lbss section is for local .largecomm symbols. */ | |
14831 | lbss_section = subseg_new (".lbss", 0); | |
14832 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 14833 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
14834 | seg_info (lbss_section)->bss = 1; |
14835 | ||
14836 | subseg_set (seg, subseg); | |
14837 | } | |
14838 | ||
14839 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
14840 | bss_section = lbss_section; | |
14841 | ||
14842 | s_comm_internal (0, elf_common_parse); | |
14843 | ||
14844 | elf_com_section_ptr = saved_com_section_ptr; | |
14845 | bss_section = saved_bss_section; | |
14846 | } | |
14847 | } | |
14848 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |