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[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
153enum processor_type
154{
155 PROCESSOR_UNKNOWN,
156 PROCESSOR_I386,
157 PROCESSOR_I486,
158 PROCESSOR_PENTIUM,
159 PROCESSOR_PENTIUMPRO,
160 PROCESSOR_PENTIUM4,
161 PROCESSOR_NOCONA,
162 PROCESSOR_CORE,
163 PROCESSOR_CORE2,
164 PROCESSOR_K6,
165 PROCESSOR_ATHLON,
166 PROCESSOR_K8,
167 PROCESSOR_GENERIC32,
168 PROCESSOR_GENERIC64,
169 PROCESSOR_AMDFAM10
170};
171
172/* x86 arch names, types and features */
173typedef struct
174{
175 const char *name; /* arch name */
176 enum processor_type type; /* arch type */
177 i386_cpu_flags flags; /* cpu feature flags */
178}
179arch_entry;
180
e3bb37b5
L		 181static void set_code_flag (int);
182static void set_16bit_gcc_code_flag (int);
183static void set_intel_syntax (int);
1efbbeb4 184static void set_intel_mnemonic (int);
db51cc60 185static void set_allow_index_reg (int);
cb19c032 186static void set_sse_check (int);
e3bb37b5 187static void set_cpu_arch (int);
6482c264 188#ifdef TE_PE
e3bb37b5 189static void pe_directive_secrel (int);
6482c264 190#endif
e3bb37b5
L		 191static void signed_cons (int);
192static char *output_invalid (int c);
a7619375 193static int i386_att_operand (char *);
e3bb37b5
L		 194static int i386_intel_operand (char *, int);
195static const reg_entry *parse_register (char *, char **);
196static char *parse_insn (char *, char *);
197static char *parse_operands (char *, const char *);
198static void swap_operands (void);
4d456e3d 199static void swap_2_operands (int, int);
e3bb37b5
L		 200static void optimize_imm (void);
201static void optimize_disp (void);
202static int match_template (void);
203static int check_string (void);
204static int process_suffix (void);
205static int check_byte_reg (void);
206static int check_long_reg (void);
207static int check_qword_reg (void);
208static int check_word_reg (void);
209static int finalize_imm (void);
85f10a01 210static void process_drex (void);
e3bb37b5
L		 211static int process_operands (void);
212static const seg_entry *build_modrm_byte (void);
213static void output_insn (void);
214static void output_imm (fragS *, offsetT);
215static void output_disp (fragS *, offsetT);
29b0f896 216#ifndef I386COFF
e3bb37b5 217static void s_bss (int);
252b5132 218#endif
17d4e2a2
L		 219#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
220static void handle_large_common (int small ATTRIBUTE_UNUSED);
221#endif
252b5132 222
a847613f 223static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 224
c0f3af97
L		 225/* VEX prefix. */
226typedef struct
227{
228 /* VEX prefix is either 2 byte or 3 byte. */
229 unsigned char bytes[3];
230 unsigned int length;
231 /* Destination or source register specifier. */
232 const reg_entry *register_specifier;
233} vex_prefix;
234
252b5132 235/* 'md_assemble ()' gathers together information and puts it into a
47926f60 236 i386_insn. */
252b5132 237
520dc8e8
AM		 238union i386_op
239 {
240 expressionS *disps;
241 expressionS *imms;
242 const reg_entry *regs;
243 };
244
252b5132
RH		 245struct _i386_insn
246 {
47926f60 247 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 248 template tm;
249
7d5e4556
L		 250 /* SUFFIX holds the instruction size suffix for byte, word, dword
251 or qword, if given. */
252b5132
RH		 252 char suffix;
253
47926f60 254 /* OPERANDS gives the number of given operands. */
252b5132
RH		 255 unsigned int operands;
256
257 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
258 of given register, displacement, memory operands and immediate
47926f60 259 operands. */
252b5132
RH		 260 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
261
262 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 263 use OP[i] for the corresponding operand. */
40fb9820 264 i386_operand_type types[MAX_OPERANDS];
252b5132 265
520dc8e8
AM		 266 /* Displacement expression, immediate expression, or register for each
267 operand. */
268 union i386_op op[MAX_OPERANDS];
252b5132 269
3e73aa7c
JH		 270 /* Flags for operands. */
271 unsigned int flags[MAX_OPERANDS];
272#define Operand_PCrel 1
273
252b5132 274 /* Relocation type for operand */
f86103b7 275 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 276
252b5132
RH		 277 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
278 the base index byte below. */
279 const reg_entry *base_reg;
280 const reg_entry *index_reg;
281 unsigned int log2_scale_factor;
282
283 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 284 explicit segment overrides are given. */
ce8a8b2f 285 const seg_entry *seg[2];
252b5132
RH		 286
287 /* PREFIX holds all the given prefix opcodes (usually null).
288 PREFIXES is the number of prefix opcodes. */
289 unsigned int prefixes;
290 unsigned char prefix[MAX_PREFIXES];
291
292 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 293 addressing modes of this insn are encoded. DREX is the byte
294 added by the SSE5 instructions. */
252b5132
RH		 295
296 modrm_byte rm;
3e73aa7c 297 rex_byte rex;
252b5132 298 sib_byte sib;
85f10a01 299 drex_byte drex;
c0f3af97 300 vex_prefix vex;
252b5132
RH		 301 };
302
303typedef struct _i386_insn i386_insn;
304
305/* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
32137342 307const char extra_symbol_chars[] = "*%-(["
252b5132 308#ifdef LEX_AT
32137342
NC		 309 "@"
310#endif
311#ifdef LEX_QM
312 "?"
252b5132 313#endif
32137342 314 ;
252b5132 315
29b0f896
AM		 316#if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 318 && !defined (TE_GNU) \
29b0f896 319 && !defined (TE_LINUX) \
32137342 320 && !defined (TE_NETWARE) \
29b0f896
AM		 321 && !defined (TE_FreeBSD) \
322 && !defined (TE_NetBSD)))
252b5132 323/* This array holds the chars that always start a comment. If the
b3b91714
AM		 324 pre-processor is disabled, these aren't very useful. The option
325 --divide will remove '/' from this list. */
326const char *i386_comment_chars = "#/";
327#define SVR4_COMMENT_CHARS 1
252b5132 328#define PREFIX_SEPARATOR '\\'
252b5132 329
b3b91714
AM		 330#else
331const char *i386_comment_chars = "#";
332#define PREFIX_SEPARATOR '/'
333#endif
334
252b5132
RH		 335/* This array holds the chars that only start a comment at the beginning of
336 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 337 .line and .file directives will appear in the pre-processed output.
338 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 339 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 340 #NO_APP at the beginning of its output.
341 Also note that comments started like this one will always work if
252b5132 342 '/' isn't otherwise defined. */
b3b91714 343const char line_comment_chars[] = "#/";
252b5132 344
63a0b638 345const char line_separator_chars[] = ";";
252b5132 346
ce8a8b2f
AM		 347/* Chars that can be used to separate mant from exp in floating point
348 nums. */
252b5132
RH		 349const char EXP_CHARS[] = "eE";
350
ce8a8b2f
AM		 351/* Chars that mean this number is a floating point constant
352 As in 0f12.456
353 or 0d1.2345e12. */
252b5132
RH		 354const char FLT_CHARS[] = "fFdDxX";
355
ce8a8b2f 356/* Tables for lexical analysis. */
252b5132
RH		 357static char mnemonic_chars[256];
358static char register_chars[256];
359static char operand_chars[256];
360static char identifier_chars[256];
361static char digit_chars[256];
362
ce8a8b2f 363/* Lexical macros. */
252b5132
RH		 364#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
365#define is_operand_char(x) (operand_chars[(unsigned char) x])
366#define is_register_char(x) (register_chars[(unsigned char) x])
367#define is_space_char(x) ((x) == ' ')
368#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
369#define is_digit_char(x) (digit_chars[(unsigned char) x])
370
0234cb7c 371/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 372static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
373
374/* md_assemble() always leaves the strings it's passed unaltered. To
375 effect this we maintain a stack of saved characters that we've smashed
376 with '\0's (indicating end of strings for various sub-fields of the
47926f60 377 assembler instruction). */
252b5132 378static char save_stack[32];
ce8a8b2f 379static char *save_stack_p;
252b5132
RH		 380#define END_STRING_AND_SAVE(s) \
381 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
382#define RESTORE_END_STRING(s) \
383 do { *(s) = *--save_stack_p; } while (0)
384
47926f60 385/* The instruction we're assembling. */
252b5132
RH		 386static i386_insn i;
387
388/* Possible templates for current insn. */
389static const templates *current_templates;
390
31b2323c
L		 391/* Per instruction expressionS buffers: max displacements & immediates. */
392static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
393static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 394
47926f60
KH		 395/* Current operand we are working on. */
396static int this_operand;
252b5132 397
3e73aa7c
JH		 398/* We support four different modes. FLAG_CODE variable is used to distinguish
399 these. */
400
401enum flag_code {
402 CODE_32BIT,
403 CODE_16BIT,
404 CODE_64BIT };
405
406static enum flag_code flag_code;
4fa24527 407static unsigned int object_64bit;
3e73aa7c
JH		 408static int use_rela_relocations = 0;
409
410/* The names used to print error messages. */
b77a7acd 411static const char *flag_code_names[] =
3e73aa7c
JH		 412 {
413 "32",
414 "16",
415 "64"
416 };
252b5132 417
47926f60
KH		 418/* 1 for intel syntax,
419 0 if att syntax. */
420static int intel_syntax = 0;
252b5132 421
1efbbeb4
L		 422/* 1 for intel mnemonic,
423 0 if att mnemonic. */
424static int intel_mnemonic = !SYSV386_COMPAT;
425
5209009a 426/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 427static int old_gcc = OLDGCC_COMPAT;
428
a60de03c
JB		 429/* 1 if pseudo registers are permitted. */
430static int allow_pseudo_reg = 0;
431
47926f60
KH		 432/* 1 if register prefix % not required. */
433static int allow_naked_reg = 0;
252b5132 434
ba104c83 435/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 436static int allow_index_reg = 0;
437
daf50ae7
L		 438static enum
439 {
440 sse_check_none = 0,
441 sse_check_warning,
442 sse_check_error
443 }
444sse_check;
445
2ca3ace5
L		 446/* Register prefix used for error message. */
447static const char *register_prefix = "%";
448
47926f60
KH		 449/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
450 leave, push, and pop instructions so that gcc has the same stack
451 frame as in 32 bit mode. */
452static char stackop_size = '\0';
eecb386c 453
12b55ccc
L		 454/* Non-zero to optimize code alignment. */
455int optimize_align_code = 1;
456
47926f60
KH		 457/* Non-zero to quieten some warnings. */
458static int quiet_warnings = 0;
a38cf1db 459
47926f60
KH		 460/* CPU name. */
461static const char *cpu_arch_name = NULL;
6305a203 462static char *cpu_sub_arch_name = NULL;
a38cf1db 463
47926f60 464/* CPU feature flags. */
40fb9820
L		 465static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
466
ccc9c027
L		 467/* If we have selected a cpu we are generating instructions for. */
468static int cpu_arch_tune_set = 0;
469
9103f4f4
L		 470/* Cpu we are generating instructions for. */
471static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
472
473/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 474static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 475
ccc9c027
L		 476/* CPU instruction set architecture used. */
477static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
478
9103f4f4 479/* CPU feature flags of instruction set architecture used. */
40fb9820 480static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 481
fddf5b5b
AM		 482/* If set, conditional jumps are not automatically promoted to handle
483 larger than a byte offset. */
484static unsigned int no_cond_jump_promotion = 0;
485
c0f3af97
L		 486/* Encode SSE instructions with VEX prefix. */
487static unsigned int sse2avx;
488
29b0f896 489/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 490static symbolS *GOT_symbol;
29b0f896 491
a4447b93
RH		 492/* The dwarf2 return column, adjusted for 32 or 64 bit. */
493unsigned int x86_dwarf2_return_column;
494
495/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
496int x86_cie_data_alignment;
497
252b5132 498/* Interface to relax_segment.
fddf5b5b
AM		 499 There are 3 major relax states for 386 jump insns because the
500 different types of jumps add different sizes to frags when we're
501 figuring out what sort of jump to choose to reach a given label. */
252b5132 502
47926f60 503/* Types. */
93c2a809
AM		 504#define UNCOND_JUMP 0
505#define COND_JUMP 1
506#define COND_JUMP86 2
fddf5b5b 507
47926f60 508/* Sizes. */
252b5132
RH		 509#define CODE16 1
510#define SMALL 0
29b0f896 511#define SMALL16 (SMALL | CODE16)
252b5132 512#define BIG 2
29b0f896 513#define BIG16 (BIG | CODE16)
252b5132
RH		 514
515#ifndef INLINE
516#ifdef __GNUC__
517#define INLINE __inline__
518#else
519#define INLINE
520#endif
521#endif
522
fddf5b5b
AM		 523#define ENCODE_RELAX_STATE(type, size) \
524 ((relax_substateT) (((type) << 2) | (size)))
525#define TYPE_FROM_RELAX_STATE(s) \
526 ((s) >> 2)
527#define DISP_SIZE_FROM_RELAX_STATE(s) \
528 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 529
530/* This table is used by relax_frag to promote short jumps to long
531 ones where necessary. SMALL (short) jumps may be promoted to BIG
532 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
533 don't allow a short jump in a 32 bit code segment to be promoted to
534 a 16 bit offset jump because it's slower (requires data size
535 prefix), and doesn't work, unless the destination is in the bottom
536 64k of the code segment (The top 16 bits of eip are zeroed). */
537
538const relax_typeS md_relax_table[] =
539{
24eab124
AM		 540 /* The fields are:
541 1) most positive reach of this state,
542 2) most negative reach of this state,
93c2a809 543 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 544 4) which index into the table to try if we can't fit into this one. */
252b5132 545
fddf5b5b 546 /* UNCOND_JUMP states. */
93c2a809
AM		 547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
549 /* dword jmp adds 4 bytes to frag:
550 0 extra opcode bytes, 4 displacement bytes. */
252b5132 551 {0, 0, 4, 0},
93c2a809
AM		 552 /* word jmp adds 2 byte2 to frag:
553 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 554 {0, 0, 2, 0},
555
93c2a809
AM		 556 /* COND_JUMP states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
561 {0, 0, 5, 0},
fddf5b5b 562 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 563 1 extra opcode byte, 2 displacement bytes. */
564 {0, 0, 3, 0},
565
566 /* COND_JUMP86 states. */
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
569 /* dword conditionals adds 5 bytes to frag:
570 1 extra opcode byte, 4 displacement bytes. */
571 {0, 0, 5, 0},
572 /* word conditionals add 4 bytes to frag:
573 1 displacement byte and a 3 byte long branch insn. */
574 {0, 0, 4, 0}
252b5132
RH		 575};
576
9103f4f4
L		 577static const arch_entry cpu_arch[] =
578{
6305a203
L		 579 { "generic32", PROCESSOR_GENERIC32,
580 CPU_GENERIC32_FLAGS },
581 { "generic64", PROCESSOR_GENERIC64,
582 CPU_GENERIC64_FLAGS },
583 { "i8086", PROCESSOR_UNKNOWN,
584 CPU_NONE_FLAGS },
585 { "i186", PROCESSOR_UNKNOWN,
586 CPU_I186_FLAGS },
587 { "i286", PROCESSOR_UNKNOWN,
588 CPU_I286_FLAGS },
589 { "i386", PROCESSOR_I386,
590 CPU_I386_FLAGS },
591 { "i486", PROCESSOR_I486,
592 CPU_I486_FLAGS },
593 { "i586", PROCESSOR_PENTIUM,
594 CPU_I586_FLAGS },
595 { "i686", PROCESSOR_PENTIUMPRO,
596 CPU_I686_FLAGS },
597 { "pentium", PROCESSOR_PENTIUM,
598 CPU_I586_FLAGS },
599 { "pentiumpro", PROCESSOR_PENTIUMPRO,
600 CPU_I686_FLAGS },
601 { "pentiumii", PROCESSOR_PENTIUMPRO,
602 CPU_P2_FLAGS },
603 { "pentiumiii",PROCESSOR_PENTIUMPRO,
604 CPU_P3_FLAGS },
605 { "pentium4", PROCESSOR_PENTIUM4,
606 CPU_P4_FLAGS },
607 { "prescott", PROCESSOR_NOCONA,
608 CPU_CORE_FLAGS },
609 { "nocona", PROCESSOR_NOCONA,
610 CPU_NOCONA_FLAGS },
611 { "yonah", PROCESSOR_CORE,
612 CPU_CORE_FLAGS },
613 { "core", PROCESSOR_CORE,
614 CPU_CORE_FLAGS },
615 { "merom", PROCESSOR_CORE2,
616 CPU_CORE2_FLAGS },
617 { "core2", PROCESSOR_CORE2,
618 CPU_CORE2_FLAGS },
619 { "k6", PROCESSOR_K6,
620 CPU_K6_FLAGS },
621 { "k6_2", PROCESSOR_K6,
622 CPU_K6_2_FLAGS },
623 { "athlon", PROCESSOR_ATHLON,
624 CPU_ATHLON_FLAGS },
625 { "sledgehammer", PROCESSOR_K8,
626 CPU_K8_FLAGS },
627 { "opteron", PROCESSOR_K8,
628 CPU_K8_FLAGS },
629 { "k8", PROCESSOR_K8,
630 CPU_K8_FLAGS },
631 { "amdfam10", PROCESSOR_AMDFAM10,
632 CPU_AMDFAM10_FLAGS },
633 { ".mmx", PROCESSOR_UNKNOWN,
634 CPU_MMX_FLAGS },
635 { ".sse", PROCESSOR_UNKNOWN,
636 CPU_SSE_FLAGS },
637 { ".sse2", PROCESSOR_UNKNOWN,
638 CPU_SSE2_FLAGS },
639 { ".sse3", PROCESSOR_UNKNOWN,
640 CPU_SSE3_FLAGS },
641 { ".ssse3", PROCESSOR_UNKNOWN,
642 CPU_SSSE3_FLAGS },
643 { ".sse4.1", PROCESSOR_UNKNOWN,
644 CPU_SSE4_1_FLAGS },
645 { ".sse4.2", PROCESSOR_UNKNOWN,
646 CPU_SSE4_2_FLAGS },
647 { ".sse4", PROCESSOR_UNKNOWN,
648 CPU_SSE4_2_FLAGS },
c0f3af97
L		 649 { ".avx", PROCESSOR_UNKNOWN,
650 CPU_AVX_FLAGS },
6305a203
L		 651 { ".vmx", PROCESSOR_UNKNOWN,
652 CPU_VMX_FLAGS },
653 { ".smx", PROCESSOR_UNKNOWN,
654 CPU_SMX_FLAGS },
f03fe4c1
L		 655 { ".xsave", PROCESSOR_UNKNOWN,
656 CPU_XSAVE_FLAGS },
c0f3af97
L		 657 { ".aes", PROCESSOR_UNKNOWN,
658 CPU_AES_FLAGS },
594ab6a3
L		 659 { ".pclmul", PROCESSOR_UNKNOWN,
660 CPU_PCLMUL_FLAGS },
c0f3af97 661 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 662 CPU_PCLMUL_FLAGS },
c0f3af97
L		 663 { ".fma", PROCESSOR_UNKNOWN,
664 CPU_FMA_FLAGS },
f1f8f695
L		 665 { ".movbe", PROCESSOR_UNKNOWN,
666 CPU_MOVBE_FLAGS },
667 { ".ept", PROCESSOR_UNKNOWN,
668 CPU_EPT_FLAGS },
6305a203
L		 669 { ".3dnow", PROCESSOR_UNKNOWN,
670 CPU_3DNOW_FLAGS },
671 { ".3dnowa", PROCESSOR_UNKNOWN,
672 CPU_3DNOWA_FLAGS },
673 { ".padlock", PROCESSOR_UNKNOWN,
674 CPU_PADLOCK_FLAGS },
675 { ".pacifica", PROCESSOR_UNKNOWN,
676 CPU_SVME_FLAGS },
677 { ".svme", PROCESSOR_UNKNOWN,
678 CPU_SVME_FLAGS },
679 { ".sse4a", PROCESSOR_UNKNOWN,
680 CPU_SSE4A_FLAGS },
681 { ".abm", PROCESSOR_UNKNOWN,
682 CPU_ABM_FLAGS },
683 { ".sse5", PROCESSOR_UNKNOWN,
684 CPU_SSE5_FLAGS },
e413e4e9
AM		 685};
686
29b0f896
AM		 687const pseudo_typeS md_pseudo_table[] =
688{
689#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
690 {"align", s_align_bytes, 0},
691#else
692 {"align", s_align_ptwo, 0},
693#endif
694 {"arch", set_cpu_arch, 0},
695#ifndef I386COFF
696 {"bss", s_bss, 0},
697#endif
698 {"ffloat", float_cons, 'f'},
699 {"dfloat", float_cons, 'd'},
700 {"tfloat", float_cons, 'x'},
701 {"value", cons, 2},
d182319b 702 {"slong", signed_cons, 4},
29b0f896
AM		 703 {"noopt", s_ignore, 0},
704 {"optim", s_ignore, 0},
705 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
706 {"code16", set_code_flag, CODE_16BIT},
707 {"code32", set_code_flag, CODE_32BIT},
708 {"code64", set_code_flag, CODE_64BIT},
709 {"intel_syntax", set_intel_syntax, 1},
710 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 711 {"intel_mnemonic", set_intel_mnemonic, 1},
712 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 713 {"allow_index_reg", set_allow_index_reg, 1},
714 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 715 {"sse_check", set_sse_check, 0},
3b22753a
L		 716#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
717 {"largecomm", handle_large_common, 0},
07a53e5c 718#else
e3bb37b5 719 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 720 {"loc", dwarf2_directive_loc, 0},
721 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 722#endif
6482c264
NC		 723#ifdef TE_PE
724 {"secrel32", pe_directive_secrel, 0},
725#endif
29b0f896
AM		 726 {0, 0, 0}
727};
728
729/* For interface with expression (). */
730extern char *input_line_pointer;
731
732/* Hash table for instruction mnemonic lookup. */
733static struct hash_control *op_hash;
734
735/* Hash table for register lookup. */
736static struct hash_control *reg_hash;
737\f
252b5132 738void
e3bb37b5 739i386_align_code (fragS *fragP, int count)
252b5132 740{
ce8a8b2f
AM		 741 /* Various efficient no-op patterns for aligning code labels.
742 Note: Don't try to assemble the instructions in the comments.
743 0L and 0w are not legal. */
252b5132
RH		 744 static const char f32_1[] =
745 {0x90}; /* nop */
746 static const char f32_2[] =
ccc9c027 747 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 748 static const char f32_3[] =
749 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
750 static const char f32_4[] =
751 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
752 static const char f32_5[] =
753 {0x90, /* nop */
754 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
755 static const char f32_6[] =
756 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
757 static const char f32_7[] =
758 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
759 static const char f32_8[] =
760 {0x90, /* nop */
761 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
762 static const char f32_9[] =
763 {0x89,0xf6, /* movl %esi,%esi */
764 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
765 static const char f32_10[] =
766 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
767 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
768 static const char f32_11[] =
769 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
770 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
771 static const char f32_12[] =
772 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
773 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
774 static const char f32_13[] =
775 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_14[] =
778 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 780 static const char f16_3[] =
781 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 782 static const char f16_4[] =
783 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
784 static const char f16_5[] =
785 {0x90, /* nop */
786 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
787 static const char f16_6[] =
788 {0x89,0xf6, /* mov %si,%si */
789 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
790 static const char f16_7[] =
791 {0x8d,0x74,0x00, /* lea 0(%si),%si */
792 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
793 static const char f16_8[] =
794 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
795 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 796 static const char jump_31[] =
797 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
798 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
799 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
800 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 801 static const char *const f32_patt[] = {
802 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 803 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 804 };
805 static const char *const f16_patt[] = {
76bc74dc 806 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 807 };
ccc9c027
L		 808 /* nopl (%[re]ax) */
809 static const char alt_3[] =
810 {0x0f,0x1f,0x00};
811 /* nopl 0(%[re]ax) */
812 static const char alt_4[] =
813 {0x0f,0x1f,0x40,0x00};
814 /* nopl 0(%[re]ax,%[re]ax,1) */
815 static const char alt_5[] =
816 {0x0f,0x1f,0x44,0x00,0x00};
817 /* nopw 0(%[re]ax,%[re]ax,1) */
818 static const char alt_6[] =
819 {0x66,0x0f,0x1f,0x44,0x00,0x00};
820 /* nopl 0L(%[re]ax) */
821 static const char alt_7[] =
822 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
823 /* nopl 0L(%[re]ax,%[re]ax,1) */
824 static const char alt_8[] =
825 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
826 /* nopw 0L(%[re]ax,%[re]ax,1) */
827 static const char alt_9[] =
828 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
829 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
830 static const char alt_10[] =
831 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
832 /* data16
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_11[] =
835 {0x66,
836 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* data16
838 data16
839 nopw %cs:0L(%[re]ax,%[re]ax,1) */
840 static const char alt_long_12[] =
841 {0x66,
842 0x66,
843 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
844 /* data16
845 data16
846 data16
847 nopw %cs:0L(%[re]ax,%[re]ax,1) */
848 static const char alt_long_13[] =
849 {0x66,
850 0x66,
851 0x66,
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* data16
854 data16
855 data16
856 data16
857 nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_long_14[] =
859 {0x66,
860 0x66,
861 0x66,
862 0x66,
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 data16
866 data16
867 data16
868 data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_15[] =
871 {0x66,
872 0x66,
873 0x66,
874 0x66,
875 0x66,
876 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1)
878 nopw 0(%[re]ax,%[re]ax,1) */
879 static const char alt_short_11[] =
880 {0x0f,0x1f,0x44,0x00,0x00,
881 0x66,0x0f,0x1f,0x44,0x00,0x00};
882 /* nopw 0(%[re]ax,%[re]ax,1)
883 nopw 0(%[re]ax,%[re]ax,1) */
884 static const char alt_short_12[] =
885 {0x66,0x0f,0x1f,0x44,0x00,0x00,
886 0x66,0x0f,0x1f,0x44,0x00,0x00};
887 /* nopw 0(%[re]ax,%[re]ax,1)
888 nopl 0L(%[re]ax) */
889 static const char alt_short_13[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00,
891 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
892 /* nopl 0L(%[re]ax)
893 nopl 0L(%[re]ax) */
894 static const char alt_short_14[] =
895 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
896 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
897 /* nopl 0L(%[re]ax)
898 nopl 0L(%[re]ax,%[re]ax,1) */
899 static const char alt_short_15[] =
900 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
901 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 static const char *const alt_short_patt[] = {
903 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
904 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
905 alt_short_14, alt_short_15
906 };
907 static const char *const alt_long_patt[] = {
908 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
909 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
910 alt_long_14, alt_long_15
911 };
252b5132 912
76bc74dc
L		 913 /* Only align for at least a positive non-zero boundary. */
914 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 915 return;
3e73aa7c 916
ccc9c027
L		 917 /* We need to decide which NOP sequence to use for 32bit and
918 64bit. When -mtune= is used:
4eed87de 919
76bc74dc
L		 920 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
921 PROCESSOR_GENERIC32, f32_patt will be used.
922 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
923 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
924 alt_long_patt will be used.
925 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
926 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 927
76bc74dc
L		 928 When -mtune= isn't used, alt_long_patt will be used if
929 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
930 be used.
ccc9c027
L		 931
932 When -march= or .arch is used, we can't use anything beyond
933 cpu_arch_isa_flags. */
934
935 if (flag_code == CODE_16BIT)
936 {
ccc9c027 937 if (count > 8)
33fef721 938 {
76bc74dc
L		 939 memcpy (fragP->fr_literal + fragP->fr_fix,
940 jump_31, count);
941 /* Adjust jump offset. */
942 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 943 }
76bc74dc
L		 944 else
945 memcpy (fragP->fr_literal + fragP->fr_fix,
946 f16_patt[count - 1], count);
252b5132 947 }
33fef721 948 else
ccc9c027
L		 949 {
950 const char *const *patt = NULL;
951
952 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
953 {
954 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
955 switch (cpu_arch_tune)
956 {
957 case PROCESSOR_UNKNOWN:
958 /* We use cpu_arch_isa_flags to check if we SHOULD
959 optimize for Cpu686. */
40fb9820 960 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 961 patt = alt_long_patt;
ccc9c027
L		 962 else
963 patt = f32_patt;
964 break;
ccc9c027
L		 965 case PROCESSOR_PENTIUMPRO:
966 case PROCESSOR_PENTIUM4:
967 case PROCESSOR_NOCONA:
ef05d495 968 case PROCESSOR_CORE:
76bc74dc
L		 969 case PROCESSOR_CORE2:
970 case PROCESSOR_GENERIC64:
971 patt = alt_long_patt;
972 break;
ccc9c027
L		 973 case PROCESSOR_K6:
974 case PROCESSOR_ATHLON:
975 case PROCESSOR_K8:
4eed87de 976 case PROCESSOR_AMDFAM10:
ccc9c027
L		 977 patt = alt_short_patt;
978 break;
76bc74dc 979 case PROCESSOR_I386:
ccc9c027
L		 980 case PROCESSOR_I486:
981 case PROCESSOR_PENTIUM:
982 case PROCESSOR_GENERIC32:
983 patt = f32_patt;
984 break;
4eed87de 985 }
ccc9c027
L		 986 }
987 else
988 {
989 switch (cpu_arch_tune)
990 {
991 case PROCESSOR_UNKNOWN:
e6a14101 992 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 993 PROCESSOR_UNKNOWN. */
994 abort ();
995 break;
996
76bc74dc 997 case PROCESSOR_I386:
ccc9c027
L		 998 case PROCESSOR_I486:
999 case PROCESSOR_PENTIUM:
ccc9c027
L		 1000 case PROCESSOR_K6:
1001 case PROCESSOR_ATHLON:
1002 case PROCESSOR_K8:
4eed87de 1003 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1004 case PROCESSOR_GENERIC32:
1005 /* We use cpu_arch_isa_flags to check if we CAN optimize
1006 for Cpu686. */
40fb9820 1007 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 1008 patt = alt_short_patt;
1009 else
1010 patt = f32_patt;
1011 break;
76bc74dc
L		 1012 case PROCESSOR_PENTIUMPRO:
1013 case PROCESSOR_PENTIUM4:
1014 case PROCESSOR_NOCONA:
1015 case PROCESSOR_CORE:
ef05d495 1016 case PROCESSOR_CORE2:
40fb9820 1017 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 1018 patt = alt_long_patt;
1019 else
1020 patt = f32_patt;
1021 break;
1022 case PROCESSOR_GENERIC64:
76bc74dc 1023 patt = alt_long_patt;
ccc9c027 1024 break;
4eed87de 1025 }
ccc9c027
L		 1026 }
1027
76bc74dc
L		 1028 if (patt == f32_patt)
1029 {
1030 /* If the padding is less than 15 bytes, we use the normal
1031 ones. Otherwise, we use a jump instruction and adjust
1032 its offset. */
1033 if (count < 15)
1034 memcpy (fragP->fr_literal + fragP->fr_fix,
1035 patt[count - 1], count);
1036 else
1037 {
1038 memcpy (fragP->fr_literal + fragP->fr_fix,
1039 jump_31, count);
1040 /* Adjust jump offset. */
1041 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1042 }
1043 }
1044 else
1045 {
1046 /* Maximum length of an instruction is 15 byte. If the
1047 padding is greater than 15 bytes and we don't use jump,
1048 we have to break it into smaller pieces. */
1049 int padding = count;
1050 while (padding > 15)
1051 {
1052 padding -= 15;
1053 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1054 patt [14], 15);
1055 }
1056
1057 if (padding)
1058 memcpy (fragP->fr_literal + fragP->fr_fix,
1059 patt [padding - 1], padding);
1060 }
ccc9c027 1061 }
33fef721 1062 fragP->fr_var = count;
252b5132
RH		 1063}
1064
c6fb90c8 1065static INLINE int
0dfbf9d7 1066operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1067{
0dfbf9d7 1068 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1069 {
1070 case 3:
0dfbf9d7 1071 if (x->array[2])
c6fb90c8
L		 1072 return 0;
1073 case 2:
0dfbf9d7 1074 if (x->array[1])
c6fb90c8
L		 1075 return 0;
1076 case 1:
0dfbf9d7 1077 return !x->array[0];
c6fb90c8
L		 1078 default:
1079 abort ();
1080 }
40fb9820
L		 1081}
1082
c6fb90c8 1083static INLINE void
0dfbf9d7 1084operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1085{
0dfbf9d7 1086 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1087 {
1088 case 3:
0dfbf9d7 1089 x->array[2] = v;
c6fb90c8 1090 case 2:
0dfbf9d7 1091 x->array[1] = v;
c6fb90c8 1092 case 1:
0dfbf9d7 1093 x->array[0] = v;
c6fb90c8
L		 1094 break;
1095 default:
1096 abort ();
1097 }
1098}
40fb9820 1099
c6fb90c8 1100static INLINE int
0dfbf9d7
L		 1101operand_type_equal (const union i386_operand_type *x,
1102 const union i386_operand_type *y)
c6fb90c8 1103{
0dfbf9d7 1104 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1105 {
1106 case 3:
0dfbf9d7 1107 if (x->array[2] != y->array[2])
c6fb90c8
L		 1108 return 0;
1109 case 2:
0dfbf9d7 1110 if (x->array[1] != y->array[1])
c6fb90c8
L		 1111 return 0;
1112 case 1:
0dfbf9d7 1113 return x->array[0] == y->array[0];
c6fb90c8
L		 1114 break;
1115 default:
1116 abort ();
1117 }
1118}
40fb9820 1119
0dfbf9d7
L		 1120static INLINE int
1121cpu_flags_all_zero (const union i386_cpu_flags *x)
1122{
1123 switch (ARRAY_SIZE(x->array))
1124 {
1125 case 3:
1126 if (x->array[2])
1127 return 0;
1128 case 2:
1129 if (x->array[1])
1130 return 0;
1131 case 1:
1132 return !x->array[0];
1133 default:
1134 abort ();
1135 }
1136}
1137
1138static INLINE void
1139cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1140{
1141 switch (ARRAY_SIZE(x->array))
1142 {
1143 case 3:
1144 x->array[2] = v;
1145 case 2:
1146 x->array[1] = v;
1147 case 1:
1148 x->array[0] = v;
1149 break;
1150 default:
1151 abort ();
1152 }
1153}
1154
1155static INLINE int
1156cpu_flags_equal (const union i386_cpu_flags *x,
1157 const union i386_cpu_flags *y)
1158{
1159 switch (ARRAY_SIZE(x->array))
1160 {
1161 case 3:
1162 if (x->array[2] != y->array[2])
1163 return 0;
1164 case 2:
1165 if (x->array[1] != y->array[1])
1166 return 0;
1167 case 1:
1168 return x->array[0] == y->array[0];
1169 break;
1170 default:
1171 abort ();
1172 }
1173}
c6fb90c8
L		 1174
1175static INLINE int
1176cpu_flags_check_cpu64 (i386_cpu_flags f)
1177{
1178 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1179 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1180}
1181
c6fb90c8
L		 1182static INLINE i386_cpu_flags
1183cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1184{
c6fb90c8
L		 1185 switch (ARRAY_SIZE (x.array))
1186 {
1187 case 3:
1188 x.array [2] &= y.array [2];
1189 case 2:
1190 x.array [1] &= y.array [1];
1191 case 1:
1192 x.array [0] &= y.array [0];
1193 break;
1194 default:
1195 abort ();
1196 }
1197 return x;
1198}
40fb9820 1199
c6fb90c8
L		 1200static INLINE i386_cpu_flags
1201cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1202{
c6fb90c8 1203 switch (ARRAY_SIZE (x.array))
40fb9820 1204 {
c6fb90c8
L		 1205 case 3:
1206 x.array [2] |= y.array [2];
1207 case 2:
1208 x.array [1] |= y.array [1];
1209 case 1:
1210 x.array [0] |= y.array [0];
40fb9820
L		 1211 break;
1212 default:
1213 abort ();
1214 }
40fb9820
L		 1215 return x;
1216}
1217
c0f3af97
L		 1218#define CPU_FLAGS_ARCH_MATCH 0x1
1219#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2
L		 1220#define CPU_FLAGS_AES_MATCH 0x4
1221#define CPU_FLAGS_AVX_MATCH 0x8
c0f3af97 1222
a5ff0eb2
L		 1223#define CPU_FLAGS_32BIT_MATCH \
1224 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1225#define CPU_FLAGS_PERFECT_MATCH \
1226 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1227
1228/* Return CPU flags match bits. */
3629bb00 1229
40fb9820 1230static int
c0f3af97 1231cpu_flags_match (const template *t)
40fb9820 1232{
c0f3af97
L		 1233 i386_cpu_flags x = t->cpu_flags;
1234 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1235
1236 x.bitfield.cpu64 = 0;
1237 x.bitfield.cpuno64 = 0;
1238
0dfbf9d7 1239 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1240 {
1241 /* This instruction is available on all archs. */
1242 match |= CPU_FLAGS_32BIT_MATCH;
1243 }
3629bb00
L		 1244 else
1245 {
c0f3af97 1246 /* This instruction is available only on some archs. */
3629bb00
L		 1247 i386_cpu_flags cpu = cpu_arch_flags;
1248
1249 cpu.bitfield.cpu64 = 0;
1250 cpu.bitfield.cpuno64 = 0;
1251 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1252 if (!cpu_flags_all_zero (&cpu))
1253 {
a5ff0eb2
L		 1254 if (x.bitfield.cpuavx)
1255 {
1256 /* We only need to check AES/SSE2AVX with AVX. */
1257 if (cpu.bitfield.cpuavx)
1258 {
1259 /* Check SSE2AVX. */
1260 if (!t->opcode_modifier.sse2avx|| sse2avx)
1261 {
1262 match |= (CPU_FLAGS_ARCH_MATCH
1263 | CPU_FLAGS_AVX_MATCH);
1264 /* Check AES. */
1265 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1266 match |= CPU_FLAGS_AES_MATCH;
1267 }
1268 }
1269 else
1270 match |= CPU_FLAGS_ARCH_MATCH;
1271 }
1272 else
c0f3af97
L		 1273 match |= CPU_FLAGS_32BIT_MATCH;
1274 }
3629bb00 1275 }
c0f3af97 1276 return match;
40fb9820
L		 1277}
1278
c6fb90c8
L		 1279static INLINE i386_operand_type
1280operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1281{
c6fb90c8
L		 1282 switch (ARRAY_SIZE (x.array))
1283 {
1284 case 3:
1285 x.array [2] &= y.array [2];
1286 case 2:
1287 x.array [1] &= y.array [1];
1288 case 1:
1289 x.array [0] &= y.array [0];
1290 break;
1291 default:
1292 abort ();
1293 }
1294 return x;
40fb9820
L		 1295}
1296
c6fb90c8
L		 1297static INLINE i386_operand_type
1298operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1299{
c6fb90c8 1300 switch (ARRAY_SIZE (x.array))
40fb9820 1301 {
c6fb90c8
L		 1302 case 3:
1303 x.array [2] |= y.array [2];
1304 case 2:
1305 x.array [1] |= y.array [1];
1306 case 1:
1307 x.array [0] |= y.array [0];
40fb9820
L		 1308 break;
1309 default:
1310 abort ();
1311 }
c6fb90c8
L		 1312 return x;
1313}
40fb9820 1314
c6fb90c8
L		 1315static INLINE i386_operand_type
1316operand_type_xor (i386_operand_type x, i386_operand_type y)
1317{
1318 switch (ARRAY_SIZE (x.array))
1319 {
1320 case 3:
1321 x.array [2] ^= y.array [2];
1322 case 2:
1323 x.array [1] ^= y.array [1];
1324 case 1:
1325 x.array [0] ^= y.array [0];
1326 break;
1327 default:
1328 abort ();
1329 }
40fb9820
L		 1330 return x;
1331}
1332
1333static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1334static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1335static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1336static const i386_operand_type inoutportreg
1337 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1338static const i386_operand_type reg16_inoutportreg
1339 = OPERAND_TYPE_REG16_INOUTPORTREG;
1340static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1341static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1342static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1343static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1344static const i386_operand_type anydisp
1345 = OPERAND_TYPE_ANYDISP;
40fb9820 1346static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1347static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1348static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1349static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1350static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1351static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1352static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1353static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1354static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1355static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1356static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
c0f3af97 1357static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
40fb9820
L		 1358
1359enum operand_type
1360{
1361 reg,
40fb9820
L		 1362 imm,
1363 disp,
1364 anymem
1365};
1366
c6fb90c8 1367static INLINE int
40fb9820
L		 1368operand_type_check (i386_operand_type t, enum operand_type c)
1369{
1370 switch (c)
1371 {
1372 case reg:
1373 return (t.bitfield.reg8
1374 || t.bitfield.reg16
1375 || t.bitfield.reg32
1376 || t.bitfield.reg64);
1377
40fb9820
L		 1378 case imm:
1379 return (t.bitfield.imm8
1380 || t.bitfield.imm8s
1381 || t.bitfield.imm16
1382 || t.bitfield.imm32
1383 || t.bitfield.imm32s
1384 || t.bitfield.imm64);
1385
1386 case disp:
1387 return (t.bitfield.disp8
1388 || t.bitfield.disp16
1389 || t.bitfield.disp32
1390 || t.bitfield.disp32s
1391 || t.bitfield.disp64);
1392
1393 case anymem:
1394 return (t.bitfield.disp8
1395 || t.bitfield.disp16
1396 || t.bitfield.disp32
1397 || t.bitfield.disp32s
1398 || t.bitfield.disp64
1399 || t.bitfield.baseindex);
1400
1401 default:
1402 abort ();
1403 }
2cfe26b6
AM		 1404
1405 return 0;
40fb9820
L		 1406}
1407
5c07affc
L		 1408/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1409 operand J for instruction template T. */
1410
1411static INLINE int
1412match_reg_size (const template *t, unsigned int j)
1413{
1414 return !((i.types[j].bitfield.byte
1415 && !t->operand_types[j].bitfield.byte)
1416 || (i.types[j].bitfield.word
1417 && !t->operand_types[j].bitfield.word)
1418 || (i.types[j].bitfield.dword
1419 && !t->operand_types[j].bitfield.dword)
1420 || (i.types[j].bitfield.qword
1421 && !t->operand_types[j].bitfield.qword));
1422}
1423
1424/* Return 1 if there is no conflict in any size on operand J for
1425 instruction template T. */
1426
1427static INLINE int
1428match_mem_size (const template *t, unsigned int j)
1429{
1430 return (match_reg_size (t, j)
1431 && !((i.types[j].bitfield.unspecified
1432 && !t->operand_types[j].bitfield.unspecified)
1433 || (i.types[j].bitfield.fword
1434 && !t->operand_types[j].bitfield.fword)
1435 || (i.types[j].bitfield.tbyte
1436 && !t->operand_types[j].bitfield.tbyte)
1437 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1438 && !t->operand_types[j].bitfield.xmmword)
1439 || (i.types[j].bitfield.ymmword
1440 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1441}
1442
1443/* Return 1 if there is no size conflict on any operands for
1444 instruction template T. */
1445
1446static INLINE int
1447operand_size_match (const template *t)
1448{
1449 unsigned int j;
1450 int match = 1;
1451
1452 /* Don't check jump instructions. */
1453 if (t->opcode_modifier.jump
1454 || t->opcode_modifier.jumpbyte
1455 || t->opcode_modifier.jumpdword
1456 || t->opcode_modifier.jumpintersegment)
1457 return match;
1458
1459 /* Check memory and accumulator operand size. */
1460 for (j = 0; j < i.operands; j++)
1461 {
1462 if (t->operand_types[j].bitfield.anysize)
1463 continue;
1464
1465 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1466 {
1467 match = 0;
1468 break;
1469 }
1470
1471 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1472 {
1473 match = 0;
1474 break;
1475 }
1476 }
1477
1478 if (match
1479 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1480 return match;
1481
1482 /* Check reverse. */
1483 assert (i.operands == 2);
1484
1485 match = 1;
1486 for (j = 0; j < 2; j++)
1487 {
1488 if (t->operand_types[j].bitfield.acc
1489 && !match_reg_size (t, j ? 0 : 1))
1490 {
1491 match = 0;
1492 break;
1493 }
1494
1495 if (i.types[j].bitfield.mem
1496 && !match_mem_size (t, j ? 0 : 1))
1497 {
1498 match = 0;
1499 break;
1500 }
1501 }
1502
1503 return match;
1504}
1505
c6fb90c8 1506static INLINE int
40fb9820
L		 1507operand_type_match (i386_operand_type overlap,
1508 i386_operand_type given)
1509{
1510 i386_operand_type temp = overlap;
1511
1512 temp.bitfield.jumpabsolute = 0;
7d5e4556 1513 temp.bitfield.unspecified = 0;
5c07affc
L		 1514 temp.bitfield.byte = 0;
1515 temp.bitfield.word = 0;
1516 temp.bitfield.dword = 0;
1517 temp.bitfield.fword = 0;
1518 temp.bitfield.qword = 0;
1519 temp.bitfield.tbyte = 0;
1520 temp.bitfield.xmmword = 0;
c0f3af97 1521 temp.bitfield.ymmword = 0;
0dfbf9d7 1522 if (operand_type_all_zero (&temp))
40fb9820
L		 1523 return 0;
1524
1525 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1526 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1527}
1528
7d5e4556 1529/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1530 unless the expected operand type register overlap is null.
1531 Note that Acc in a template matches every size of reg. */
1532
c6fb90c8 1533static INLINE int
40fb9820
L		 1534operand_type_register_match (i386_operand_type m0,
1535 i386_operand_type g0,
1536 i386_operand_type t0,
1537 i386_operand_type m1,
1538 i386_operand_type g1,
1539 i386_operand_type t1)
1540{
1541 if (!operand_type_check (g0, reg))
1542 return 1;
1543
1544 if (!operand_type_check (g1, reg))
1545 return 1;
1546
1547 if (g0.bitfield.reg8 == g1.bitfield.reg8
1548 && g0.bitfield.reg16 == g1.bitfield.reg16
1549 && g0.bitfield.reg32 == g1.bitfield.reg32
1550 && g0.bitfield.reg64 == g1.bitfield.reg64)
1551 return 1;
1552
1553 if (m0.bitfield.acc)
1554 {
1555 t0.bitfield.reg8 = 1;
1556 t0.bitfield.reg16 = 1;
1557 t0.bitfield.reg32 = 1;
1558 t0.bitfield.reg64 = 1;
1559 }
1560
1561 if (m1.bitfield.acc)
1562 {
1563 t1.bitfield.reg8 = 1;
1564 t1.bitfield.reg16 = 1;
1565 t1.bitfield.reg32 = 1;
1566 t1.bitfield.reg64 = 1;
1567 }
1568
1569 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1570 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1571 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1572 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1573}
1574
252b5132 1575static INLINE unsigned int
40fb9820 1576mode_from_disp_size (i386_operand_type t)
252b5132 1577{
40fb9820
L		 1578 if (t.bitfield.disp8)
1579 return 1;
1580 else if (t.bitfield.disp16
1581 || t.bitfield.disp32
1582 || t.bitfield.disp32s)
1583 return 2;
1584 else
1585 return 0;
252b5132
RH		 1586}
1587
1588static INLINE int
e3bb37b5 1589fits_in_signed_byte (offsetT num)
252b5132
RH		 1590{
1591 return (num >= -128) && (num <= 127);
47926f60 1592}
252b5132
RH		 1593
1594static INLINE int
e3bb37b5 1595fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1596{
1597 return (num & 0xff) == num;
47926f60 1598}
252b5132
RH		 1599
1600static INLINE int
e3bb37b5 1601fits_in_unsigned_word (offsetT num)
252b5132
RH		 1602{
1603 return (num & 0xffff) == num;
47926f60 1604}
252b5132
RH		 1605
1606static INLINE int
e3bb37b5 1607fits_in_signed_word (offsetT num)
252b5132
RH		 1608{
1609 return (-32768 <= num) && (num <= 32767);
47926f60 1610}
2a962e6d 1611
3e73aa7c 1612static INLINE int
e3bb37b5 1613fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1614{
1615#ifndef BFD64
1616 return 1;
1617#else
1618 return (!(((offsetT) -1 << 31) & num)
1619 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1620#endif
1621} /* fits_in_signed_long() */
2a962e6d 1622
3e73aa7c 1623static INLINE int
e3bb37b5 1624fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1625{
1626#ifndef BFD64
1627 return 1;
1628#else
1629 return (num & (((offsetT) 2 << 31) - 1)) == num;
1630#endif
1631} /* fits_in_unsigned_long() */
252b5132 1632
c0f3af97
L		 1633static INLINE int
1634fits_in_imm4 (offsetT num)
1635{
1636 return (num & 0xf) == num;
1637}
1638
40fb9820 1639static i386_operand_type
e3bb37b5 1640smallest_imm_type (offsetT num)
252b5132 1641{
40fb9820
L		 1642 i386_operand_type t;
1643
0dfbf9d7 1644 operand_type_set (&t, 0);
40fb9820
L		 1645 t.bitfield.imm64 = 1;
1646
1647 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1648 {
1649 /* This code is disabled on the 486 because all the Imm1 forms
1650 in the opcode table are slower on the i486. They're the
1651 versions with the implicitly specified single-position
1652 displacement, which has another syntax if you really want to
1653 use that form. */
40fb9820
L		 1654 t.bitfield.imm1 = 1;
1655 t.bitfield.imm8 = 1;
1656 t.bitfield.imm8s = 1;
1657 t.bitfield.imm16 = 1;
1658 t.bitfield.imm32 = 1;
1659 t.bitfield.imm32s = 1;
1660 }
1661 else if (fits_in_signed_byte (num))
1662 {
1663 t.bitfield.imm8 = 1;
1664 t.bitfield.imm8s = 1;
1665 t.bitfield.imm16 = 1;
1666 t.bitfield.imm32 = 1;
1667 t.bitfield.imm32s = 1;
1668 }
1669 else if (fits_in_unsigned_byte (num))
1670 {
1671 t.bitfield.imm8 = 1;
1672 t.bitfield.imm16 = 1;
1673 t.bitfield.imm32 = 1;
1674 t.bitfield.imm32s = 1;
1675 }
1676 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1677 {
1678 t.bitfield.imm16 = 1;
1679 t.bitfield.imm32 = 1;
1680 t.bitfield.imm32s = 1;
1681 }
1682 else if (fits_in_signed_long (num))
1683 {
1684 t.bitfield.imm32 = 1;
1685 t.bitfield.imm32s = 1;
1686 }
1687 else if (fits_in_unsigned_long (num))
1688 t.bitfield.imm32 = 1;
1689
1690 return t;
47926f60 1691}
252b5132 1692
847f7ad4 1693static offsetT
e3bb37b5 1694offset_in_range (offsetT val, int size)
847f7ad4 1695{
508866be 1696 addressT mask;
ba2adb93 1697
847f7ad4
AM		 1698 switch (size)
1699 {
508866be
L		 1700 case 1: mask = ((addressT) 1 << 8) - 1; break;
1701 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1702 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1703#ifdef BFD64
1704 case 8: mask = ((addressT) 2 << 63) - 1; break;
1705#endif
47926f60 1706 default: abort ();
847f7ad4
AM		 1707 }
1708
ba2adb93 1709 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1710 if (!use_rela_relocations)
1711 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1712 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1713
47926f60 1714 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1715 {
1716 char buf1[40], buf2[40];
1717
1718 sprint_value (buf1, val);
1719 sprint_value (buf2, val & mask);
1720 as_warn (_("%s shortened to %s"), buf1, buf2);
1721 }
1722 return val & mask;
1723}
1724
252b5132
RH		 1725/* Returns 0 if attempting to add a prefix where one from the same
1726 class already exists, 1 if non rep/repne added, 2 if rep/repne
1727 added. */
1728static int
e3bb37b5 1729add_prefix (unsigned int prefix)
252b5132
RH		 1730{
1731 int ret = 1;
b1905489 1732 unsigned int q;
252b5132 1733
29b0f896
AM		 1734 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1735 && flag_code == CODE_64BIT)
b1905489 1736 {
161a04f6
L		 1737 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1738 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1739 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1740 ret = 0;
1741 q = REX_PREFIX;
1742 }
3e73aa7c 1743 else
b1905489
JB		 1744 {
1745 switch (prefix)
1746 {
1747 default:
1748 abort ();
1749
1750 case CS_PREFIX_OPCODE:
1751 case DS_PREFIX_OPCODE:
1752 case ES_PREFIX_OPCODE:
1753 case FS_PREFIX_OPCODE:
1754 case GS_PREFIX_OPCODE:
1755 case SS_PREFIX_OPCODE:
1756 q = SEG_PREFIX;
1757 break;
1758
1759 case REPNE_PREFIX_OPCODE:
1760 case REPE_PREFIX_OPCODE:
1761 ret = 2;
1762 /* fall thru */
1763 case LOCK_PREFIX_OPCODE:
1764 q = LOCKREP_PREFIX;
1765 break;
1766
1767 case FWAIT_OPCODE:
1768 q = WAIT_PREFIX;
1769 break;
1770
1771 case ADDR_PREFIX_OPCODE:
1772 q = ADDR_PREFIX;
1773 break;
1774
1775 case DATA_PREFIX_OPCODE:
1776 q = DATA_PREFIX;
1777 break;
1778 }
1779 if (i.prefix[q] != 0)
1780 ret = 0;
1781 }
252b5132 1782
b1905489 1783 if (ret)
252b5132 1784 {
b1905489
JB		 1785 if (!i.prefix[q])
1786 ++i.prefixes;
1787 i.prefix[q] |= prefix;
252b5132 1788 }
b1905489
JB		 1789 else
1790 as_bad (_("same type of prefix used twice"));
252b5132 1791
252b5132
RH		 1792 return ret;
1793}
1794
1795static void
e3bb37b5 1796set_code_flag (int value)
eecb386c 1797{
3e73aa7c 1798 flag_code = value;
40fb9820
L		 1799 if (flag_code == CODE_64BIT)
1800 {
1801 cpu_arch_flags.bitfield.cpu64 = 1;
1802 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1803 }
1804 else
1805 {
1806 cpu_arch_flags.bitfield.cpu64 = 0;
1807 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1808 }
1809 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1810 {
1811 as_bad (_("64bit mode not supported on this CPU."));
1812 }
40fb9820 1813 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1814 {
1815 as_bad (_("32bit mode not supported on this CPU."));
1816 }
eecb386c
AM		 1817 stackop_size = '\0';
1818}
1819
1820static void
e3bb37b5 1821set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1822{
3e73aa7c 1823 flag_code = new_code_flag;
40fb9820
L		 1824 if (flag_code != CODE_16BIT)
1825 abort ();
1826 cpu_arch_flags.bitfield.cpu64 = 0;
1827 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1828 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1829}
1830
1831static void
e3bb37b5 1832set_intel_syntax (int syntax_flag)
252b5132
RH		 1833{
1834 /* Find out if register prefixing is specified. */
1835 int ask_naked_reg = 0;
1836
1837 SKIP_WHITESPACE ();
29b0f896 1838 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1839 {
1840 char *string = input_line_pointer;
1841 int e = get_symbol_end ();
1842
47926f60 1843 if (strcmp (string, "prefix") == 0)
252b5132 1844 ask_naked_reg = 1;
47926f60 1845 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1846 ask_naked_reg = -1;
1847 else
d0b47220 1848 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1849 *input_line_pointer = e;
1850 }
1851 demand_empty_rest_of_line ();
c3332e24 1852
252b5132
RH		 1853 intel_syntax = syntax_flag;
1854
1855 if (ask_naked_reg == 0)
f86103b7
AM		 1856 allow_naked_reg = (intel_syntax
1857 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1858 else
1859 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1860
e4a3b5a4 1861 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1862 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1863 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1864}
1865
1efbbeb4
L		 1866static void
1867set_intel_mnemonic (int mnemonic_flag)
1868{
e1d4d893 1869 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1870}
1871
db51cc60
L		 1872static void
1873set_allow_index_reg (int flag)
1874{
1875 allow_index_reg = flag;
1876}
1877
cb19c032
L		 1878static void
1879set_sse_check (int dummy ATTRIBUTE_UNUSED)
1880{
1881 SKIP_WHITESPACE ();
1882
1883 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1884 {
1885 char *string = input_line_pointer;
1886 int e = get_symbol_end ();
1887
1888 if (strcmp (string, "none") == 0)
1889 sse_check = sse_check_none;
1890 else if (strcmp (string, "warning") == 0)
1891 sse_check = sse_check_warning;
1892 else if (strcmp (string, "error") == 0)
1893 sse_check = sse_check_error;
1894 else
1895 as_bad (_("bad argument to sse_check directive."));
1896 *input_line_pointer = e;
1897 }
1898 else
1899 as_bad (_("missing argument for sse_check directive"));
1900
1901 demand_empty_rest_of_line ();
1902}
1903
e413e4e9 1904static void
e3bb37b5 1905set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1906{
47926f60 1907 SKIP_WHITESPACE ();
e413e4e9 1908
29b0f896 1909 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1910 {
1911 char *string = input_line_pointer;
1912 int e = get_symbol_end ();
9103f4f4 1913 unsigned int i;
40fb9820 1914 i386_cpu_flags flags;
e413e4e9 1915
9103f4f4 1916 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1917 {
1918 if (strcmp (string, cpu_arch[i].name) == 0)
1919 {
5c6af06e
JB		 1920 if (*string != '.')
1921 {
1922 cpu_arch_name = cpu_arch[i].name;
1923 cpu_sub_arch_name = NULL;
40fb9820
L		 1924 cpu_arch_flags = cpu_arch[i].flags;
1925 if (flag_code == CODE_64BIT)
1926 {
1927 cpu_arch_flags.bitfield.cpu64 = 1;
1928 cpu_arch_flags.bitfield.cpuno64 = 0;
1929 }
1930 else
1931 {
1932 cpu_arch_flags.bitfield.cpu64 = 0;
1933 cpu_arch_flags.bitfield.cpuno64 = 1;
1934 }
ccc9c027 1935 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1936 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1937 if (!cpu_arch_tune_set)
1938 {
1939 cpu_arch_tune = cpu_arch_isa;
1940 cpu_arch_tune_flags = cpu_arch_isa_flags;
1941 }
5c6af06e
JB		 1942 break;
1943 }
40fb9820 1944
c6fb90c8
L		 1945 flags = cpu_flags_or (cpu_arch_flags,
1946 cpu_arch[i].flags);
0dfbf9d7 1947 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1948 {
6305a203
L		 1949 if (cpu_sub_arch_name)
1950 {
1951 char *name = cpu_sub_arch_name;
1952 cpu_sub_arch_name = concat (name,
1953 cpu_arch[i].name,
1bf57e9f 1954 (const char *) NULL);
6305a203
L		 1955 free (name);
1956 }
1957 else
1958 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1959 cpu_arch_flags = flags;
5c6af06e
JB		 1960 }
1961 *input_line_pointer = e;
1962 demand_empty_rest_of_line ();
1963 return;
e413e4e9
AM		 1964 }
1965 }
9103f4f4 1966 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1967 as_bad (_("no such architecture: `%s'"), string);
1968
1969 *input_line_pointer = e;
1970 }
1971 else
1972 as_bad (_("missing cpu architecture"));
1973
fddf5b5b
AM		 1974 no_cond_jump_promotion = 0;
1975 if (*input_line_pointer == ','
29b0f896 1976 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1977 {
1978 char *string = ++input_line_pointer;
1979 int e = get_symbol_end ();
1980
1981 if (strcmp (string, "nojumps") == 0)
1982 no_cond_jump_promotion = 1;
1983 else if (strcmp (string, "jumps") == 0)
1984 ;
1985 else
1986 as_bad (_("no such architecture modifier: `%s'"), string);
1987
1988 *input_line_pointer = e;
1989 }
1990
e413e4e9
AM		 1991 demand_empty_rest_of_line ();
1992}
1993
b9d79e03
JH		 1994unsigned long
1995i386_mach ()
1996{
1997 if (!strcmp (default_arch, "x86_64"))
1998 return bfd_mach_x86_64;
1999 else if (!strcmp (default_arch, "i386"))
2000 return bfd_mach_i386_i386;
2001 else
2002 as_fatal (_("Unknown architecture"));
2003}
b9d79e03 2004\f
252b5132
RH		 2005void
2006md_begin ()
2007{
2008 const char *hash_err;
2009
47926f60 2010 /* Initialize op_hash hash table. */
252b5132
RH		 2011 op_hash = hash_new ();
2012
2013 {
29b0f896
AM		 2014 const template *optab;
2015 templates *core_optab;
252b5132 2016
47926f60
KH		 2017 /* Setup for loop. */
2018 optab = i386_optab;
252b5132
RH		 2019 core_optab = (templates *) xmalloc (sizeof (templates));
2020 core_optab->start = optab;
2021
2022 while (1)
2023 {
2024 ++optab;
2025 if (optab->name == NULL
2026 || strcmp (optab->name, (optab - 1)->name) != 0)
2027 {
2028 /* different name --> ship out current template list;
47926f60 2029 add to hash table; & begin anew. */
252b5132
RH		 2030 core_optab->end = optab;
2031 hash_err = hash_insert (op_hash,
2032 (optab - 1)->name,
5a49b8ac 2033 (void *) core_optab);
252b5132
RH		 2034 if (hash_err)
2035 {
252b5132
RH		 2036 as_fatal (_("Internal Error: Can't hash %s: %s"),
2037 (optab - 1)->name,
2038 hash_err);
2039 }
2040 if (optab->name == NULL)
2041 break;
2042 core_optab = (templates *) xmalloc (sizeof (templates));
2043 core_optab->start = optab;
2044 }
2045 }
2046 }
2047
47926f60 2048 /* Initialize reg_hash hash table. */
252b5132
RH		 2049 reg_hash = hash_new ();
2050 {
29b0f896 2051 const reg_entry *regtab;
c3fe08fa 2052 unsigned int regtab_size = i386_regtab_size;
252b5132 2053
c3fe08fa 2054 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2055 {
5a49b8ac 2056 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2057 if (hash_err)
3e73aa7c
JH		 2058 as_fatal (_("Internal Error: Can't hash %s: %s"),
2059 regtab->reg_name,
2060 hash_err);
252b5132
RH		 2061 }
2062 }
2063
47926f60 2064 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2065 {
29b0f896
AM		 2066 int c;
2067 char *p;
252b5132
RH		 2068
2069 for (c = 0; c < 256; c++)
2070 {
3882b010 2071 if (ISDIGIT (c))
252b5132
RH		 2072 {
2073 digit_chars[c] = c;
2074 mnemonic_chars[c] = c;
2075 register_chars[c] = c;
2076 operand_chars[c] = c;
2077 }
3882b010 2078 else if (ISLOWER (c))
252b5132
RH		 2079 {
2080 mnemonic_chars[c] = c;
2081 register_chars[c] = c;
2082 operand_chars[c] = c;
2083 }
3882b010 2084 else if (ISUPPER (c))
252b5132 2085 {
3882b010 2086 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2087 register_chars[c] = mnemonic_chars[c];
2088 operand_chars[c] = c;
2089 }
2090
3882b010 2091 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2092 identifier_chars[c] = c;
2093 else if (c >= 128)
2094 {
2095 identifier_chars[c] = c;
2096 operand_chars[c] = c;
2097 }
2098 }
2099
2100#ifdef LEX_AT
2101 identifier_chars['@'] = '@';
32137342
NC		 2102#endif
2103#ifdef LEX_QM
2104 identifier_chars['?'] = '?';
2105 operand_chars['?'] = '?';
252b5132 2106#endif
252b5132 2107 digit_chars['-'] = '-';
c0f3af97 2108 mnemonic_chars['_'] = '_';
791fe849 2109 mnemonic_chars['-'] = '-';
0003779b 2110 mnemonic_chars['.'] = '.';
252b5132
RH		 2111 identifier_chars['_'] = '_';
2112 identifier_chars['.'] = '.';
2113
2114 for (p = operand_special_chars; *p != '\0'; p++)
2115 operand_chars[(unsigned char) *p] = *p;
2116 }
2117
2118#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2119 if (IS_ELF)
252b5132
RH		 2120 {
2121 record_alignment (text_section, 2);
2122 record_alignment (data_section, 2);
2123 record_alignment (bss_section, 2);
2124 }
2125#endif
a4447b93
RH		 2126
2127 if (flag_code == CODE_64BIT)
2128 {
2129 x86_dwarf2_return_column = 16;
2130 x86_cie_data_alignment = -8;
2131 }
2132 else
2133 {
2134 x86_dwarf2_return_column = 8;
2135 x86_cie_data_alignment = -4;
2136 }
252b5132
RH		 2137}
2138
2139void
e3bb37b5 2140i386_print_statistics (FILE *file)
252b5132
RH		 2141{
2142 hash_print_statistics (file, "i386 opcode", op_hash);
2143 hash_print_statistics (file, "i386 register", reg_hash);
2144}
2145\f
252b5132
RH		 2146#ifdef DEBUG386
2147
ce8a8b2f 2148/* Debugging routines for md_assemble. */
e3bb37b5 2149static void pte (template *);
40fb9820 2150static void pt (i386_operand_type);
e3bb37b5
L		 2151static void pe (expressionS *);
2152static void ps (symbolS *);
252b5132
RH		 2153
2154static void
e3bb37b5 2155pi (char *line, i386_insn *x)
252b5132 2156{
09f131f2 2157 unsigned int i;
252b5132
RH		 2158
2159 fprintf (stdout, "%s: template ", line);
2160 pte (&x->tm);
09f131f2
JH		 2161 fprintf (stdout, " address: base %s index %s scale %x\n",
2162 x->base_reg ? x->base_reg->reg_name : "none",
2163 x->index_reg ? x->index_reg->reg_name : "none",
2164 x->log2_scale_factor);
2165 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2166 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2167 fprintf (stdout, " sib: base %x index %x scale %x\n",
2168 x->sib.base, x->sib.index, x->sib.scale);
2169 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2170 (x->rex & REX_W) != 0,
2171 (x->rex & REX_R) != 0,
2172 (x->rex & REX_X) != 0,
2173 (x->rex & REX_B) != 0);
85f10a01
MM		 2174 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2175 x->drex.reg, x->drex.rex);
252b5132
RH		 2176 for (i = 0; i < x->operands; i++)
2177 {
2178 fprintf (stdout, " #%d: ", i + 1);
2179 pt (x->types[i]);
2180 fprintf (stdout, "\n");
40fb9820
L		 2181 if (x->types[i].bitfield.reg8
2182 || x->types[i].bitfield.reg16
2183 || x->types[i].bitfield.reg32
2184 || x->types[i].bitfield.reg64
2185 || x->types[i].bitfield.regmmx
2186 || x->types[i].bitfield.regxmm
c0f3af97 2187 || x->types[i].bitfield.regymm
40fb9820
L		 2188 || x->types[i].bitfield.sreg2
2189 || x->types[i].bitfield.sreg3
2190 || x->types[i].bitfield.control
2191 || x->types[i].bitfield.debug
2192 || x->types[i].bitfield.test)
520dc8e8 2193 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2194 if (operand_type_check (x->types[i], imm))
520dc8e8 2195 pe (x->op[i].imms);
40fb9820 2196 if (operand_type_check (x->types[i], disp))
520dc8e8 2197 pe (x->op[i].disps);
252b5132
RH		 2198 }
2199}
2200
2201static void
e3bb37b5 2202pte (template *t)
252b5132 2203{
09f131f2 2204 unsigned int i;
252b5132 2205 fprintf (stdout, " %d operands ", t->operands);
47926f60 2206 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2207 if (t->extension_opcode != None)
2208 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2209 if (t->opcode_modifier.d)
252b5132 2210 fprintf (stdout, "D");
40fb9820 2211 if (t->opcode_modifier.w)
252b5132
RH		 2212 fprintf (stdout, "W");
2213 fprintf (stdout, "\n");
2214 for (i = 0; i < t->operands; i++)
2215 {
2216 fprintf (stdout, " #%d type ", i + 1);
2217 pt (t->operand_types[i]);
2218 fprintf (stdout, "\n");
2219 }
2220}
2221
2222static void
e3bb37b5 2223pe (expressionS *e)
252b5132 2224{
24eab124 2225 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2226 fprintf (stdout, " add_number %ld (%lx)\n",
2227 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2228 if (e->X_add_symbol)
2229 {
2230 fprintf (stdout, " add_symbol ");
2231 ps (e->X_add_symbol);
2232 fprintf (stdout, "\n");
2233 }
2234 if (e->X_op_symbol)
2235 {
2236 fprintf (stdout, " op_symbol ");
2237 ps (e->X_op_symbol);
2238 fprintf (stdout, "\n");
2239 }
2240}
2241
2242static void
e3bb37b5 2243ps (symbolS *s)
252b5132
RH		 2244{
2245 fprintf (stdout, "%s type %s%s",
2246 S_GET_NAME (s),
2247 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2248 segment_name (S_GET_SEGMENT (s)));
2249}
2250
7b81dfbb 2251static struct type_name
252b5132 2252 {
40fb9820
L		 2253 i386_operand_type mask;
2254 const char *name;
252b5132 2255 }
7b81dfbb 2256const type_names[] =
252b5132 2257{
40fb9820
L		 2258 { OPERAND_TYPE_REG8, "r8" },
2259 { OPERAND_TYPE_REG16, "r16" },
2260 { OPERAND_TYPE_REG32, "r32" },
2261 { OPERAND_TYPE_REG64, "r64" },
2262 { OPERAND_TYPE_IMM8, "i8" },
2263 { OPERAND_TYPE_IMM8, "i8s" },
2264 { OPERAND_TYPE_IMM16, "i16" },
2265 { OPERAND_TYPE_IMM32, "i32" },
2266 { OPERAND_TYPE_IMM32S, "i32s" },
2267 { OPERAND_TYPE_IMM64, "i64" },
2268 { OPERAND_TYPE_IMM1, "i1" },
2269 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2270 { OPERAND_TYPE_DISP8, "d8" },
2271 { OPERAND_TYPE_DISP16, "d16" },
2272 { OPERAND_TYPE_DISP32, "d32" },
2273 { OPERAND_TYPE_DISP32S, "d32s" },
2274 { OPERAND_TYPE_DISP64, "d64" },
2275 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2276 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2277 { OPERAND_TYPE_CONTROL, "control reg" },
2278 { OPERAND_TYPE_TEST, "test reg" },
2279 { OPERAND_TYPE_DEBUG, "debug reg" },
2280 { OPERAND_TYPE_FLOATREG, "FReg" },
2281 { OPERAND_TYPE_FLOATACC, "FAcc" },
2282 { OPERAND_TYPE_SREG2, "SReg2" },
2283 { OPERAND_TYPE_SREG3, "SReg3" },
2284 { OPERAND_TYPE_ACC, "Acc" },
2285 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2286 { OPERAND_TYPE_REGMMX, "rMMX" },
2287 { OPERAND_TYPE_REGXMM, "rXMM" },
2288 { OPERAND_TYPE_ESSEG, "es" },
c0f3af97 2289 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
252b5132
RH		 2290};
2291
2292static void
40fb9820 2293pt (i386_operand_type t)
252b5132 2294{
40fb9820 2295 unsigned int j;
c6fb90c8 2296 i386_operand_type a;
252b5132 2297
40fb9820 2298 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2299 {
2300 a = operand_type_and (t, type_names[j].mask);
2301 if (!UINTS_ALL_ZERO (a))
2302 fprintf (stdout, "%s, ", type_names[j].name);
2303 }
252b5132
RH		 2304 fflush (stdout);
2305}
2306
2307#endif /* DEBUG386 */
2308\f
252b5132 2309static bfd_reloc_code_real_type
3956db08 2310reloc (unsigned int size,
64e74474
AM		 2311 int pcrel,
2312 int sign,
2313 bfd_reloc_code_real_type other)
252b5132 2314{
47926f60 2315 if (other != NO_RELOC)
3956db08
JB		 2316 {
2317 reloc_howto_type *reloc;
2318
2319 if (size == 8)
2320 switch (other)
2321 {
64e74474
AM		 2322 case BFD_RELOC_X86_64_GOT32:
2323 return BFD_RELOC_X86_64_GOT64;
2324 break;
2325 case BFD_RELOC_X86_64_PLTOFF64:
2326 return BFD_RELOC_X86_64_PLTOFF64;
2327 break;
2328 case BFD_RELOC_X86_64_GOTPC32:
2329 other = BFD_RELOC_X86_64_GOTPC64;
2330 break;
2331 case BFD_RELOC_X86_64_GOTPCREL:
2332 other = BFD_RELOC_X86_64_GOTPCREL64;
2333 break;
2334 case BFD_RELOC_X86_64_TPOFF32:
2335 other = BFD_RELOC_X86_64_TPOFF64;
2336 break;
2337 case BFD_RELOC_X86_64_DTPOFF32:
2338 other = BFD_RELOC_X86_64_DTPOFF64;
2339 break;
2340 default:
2341 break;
3956db08 2342 }
e05278af
JB		 2343
2344 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2345 if (size == 4 && flag_code != CODE_64BIT)
2346 sign = -1;
2347
3956db08
JB		 2348 reloc = bfd_reloc_type_lookup (stdoutput, other);
2349 if (!reloc)
2350 as_bad (_("unknown relocation (%u)"), other);
2351 else if (size != bfd_get_reloc_size (reloc))
2352 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2353 bfd_get_reloc_size (reloc),
2354 size);
2355 else if (pcrel && !reloc->pc_relative)
2356 as_bad (_("non-pc-relative relocation for pc-relative field"));
2357 else if ((reloc->complain_on_overflow == complain_overflow_signed
2358 && !sign)
2359 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2360 && sign > 0))
3956db08
JB		 2361 as_bad (_("relocated field and relocation type differ in signedness"));
2362 else
2363 return other;
2364 return NO_RELOC;
2365 }
252b5132
RH		 2366
2367 if (pcrel)
2368 {
3e73aa7c 2369 if (!sign)
3956db08 2370 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2371 switch (size)
2372 {
2373 case 1: return BFD_RELOC_8_PCREL;
2374 case 2: return BFD_RELOC_16_PCREL;
2375 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2376 case 8: return BFD_RELOC_64_PCREL;
252b5132 2377 }
3956db08 2378 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2379 }
2380 else
2381 {
3956db08 2382 if (sign > 0)
e5cb08ac 2383 switch (size)
3e73aa7c
JH		 2384 {
2385 case 4: return BFD_RELOC_X86_64_32S;
2386 }
2387 else
2388 switch (size)
2389 {
2390 case 1: return BFD_RELOC_8;
2391 case 2: return BFD_RELOC_16;
2392 case 4: return BFD_RELOC_32;
2393 case 8: return BFD_RELOC_64;
2394 }
3956db08
JB		 2395 as_bad (_("cannot do %s %u byte relocation"),
2396 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2397 }
2398
bfb32b52 2399 abort ();
252b5132
RH		 2400 return BFD_RELOC_NONE;
2401}
2402
47926f60
KH		 2403/* Here we decide which fixups can be adjusted to make them relative to
2404 the beginning of the section instead of the symbol. Basically we need
2405 to make sure that the dynamic relocations are done correctly, so in
2406 some cases we force the original symbol to be used. */
2407
252b5132 2408int
e3bb37b5 2409tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2410{
6d249963 2411#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2412 if (!IS_ELF)
31312f95
AM		 2413 return 1;
2414
a161fe53
AM		 2415 /* Don't adjust pc-relative references to merge sections in 64-bit
2416 mode. */
2417 if (use_rela_relocations
2418 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2419 && fixP->fx_pcrel)
252b5132 2420 return 0;
31312f95 2421
8d01d9a9
AJ		 2422 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2423 and changed later by validate_fix. */
2424 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2425 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2426 return 0;
2427
ce8a8b2f 2428 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2429 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2430 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2431 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2432 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2433 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2434 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2435 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2436 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2437 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2438 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2439 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2440 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2441 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2442 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2443 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2444 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2445 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2446 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2447 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2448 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2449 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2450 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2451 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2452 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2453 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2454 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2455 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2456 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2457 return 0;
31312f95 2458#endif
252b5132
RH		 2459 return 1;
2460}
252b5132 2461
b4cac588 2462static int
e3bb37b5 2463intel_float_operand (const char *mnemonic)
252b5132 2464{
9306ca4a
JB		 2465 /* Note that the value returned is meaningful only for opcodes with (memory)
2466 operands, hence the code here is free to improperly handle opcodes that
2467 have no operands (for better performance and smaller code). */
2468
2469 if (mnemonic[0] != 'f')
2470 return 0; /* non-math */
2471
2472 switch (mnemonic[1])
2473 {
2474 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2475 the fs segment override prefix not currently handled because no
2476 call path can make opcodes without operands get here */
2477 case 'i':
2478 return 2 /* integer op */;
2479 case 'l':
2480 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2481 return 3; /* fldcw/fldenv */
2482 break;
2483 case 'n':
2484 if (mnemonic[2] != 'o' /* fnop */)
2485 return 3; /* non-waiting control op */
2486 break;
2487 case 'r':
2488 if (mnemonic[2] == 's')
2489 return 3; /* frstor/frstpm */
2490 break;
2491 case 's':
2492 if (mnemonic[2] == 'a')
2493 return 3; /* fsave */
2494 if (mnemonic[2] == 't')
2495 {
2496 switch (mnemonic[3])
2497 {
2498 case 'c': /* fstcw */
2499 case 'd': /* fstdw */
2500 case 'e': /* fstenv */
2501 case 's': /* fsts[gw] */
2502 return 3;
2503 }
2504 }
2505 break;
2506 case 'x':
2507 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2508 return 0; /* fxsave/fxrstor are not really math ops */
2509 break;
2510 }
252b5132 2511
9306ca4a 2512 return 1;
252b5132
RH		 2513}
2514
c0f3af97
L		 2515/* Build the VEX prefix. */
2516
2517static void
2518build_vex_prefix (void)
2519{
2520 unsigned int register_specifier;
2521 unsigned int implied_prefix;
2522 unsigned int vector_length;
2523
2524 /* Check register specifier. */
2525 if (i.vex.register_specifier)
2526 {
2527 register_specifier = i.vex.register_specifier->reg_num;
2528 if ((i.vex.register_specifier->reg_flags & RegRex))
2529 register_specifier += 8;
2530 register_specifier = ~register_specifier & 0xf;
2531 }
2532 else
2533 register_specifier = 0xf;
2534
2535 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2536
2537 switch ((i.tm.base_opcode >> 8) & 0xff)
2538 {
2539 case 0:
2540 implied_prefix = 0;
2541 break;
2542 case DATA_PREFIX_OPCODE:
2543 implied_prefix = 1;
2544 break;
2545 case REPE_PREFIX_OPCODE:
2546 implied_prefix = 2;
2547 break;
2548 case REPNE_PREFIX_OPCODE:
2549 implied_prefix = 3;
2550 break;
2551 default:
2552 abort ();
2553 }
2554
2555 /* Use 2-byte VEX prefix if possible. */
2556 if (i.tm.opcode_modifier.vex0f
2557 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2558 {
2559 /* 2-byte VEX prefix. */
2560 unsigned int r;
2561
2562 i.vex.length = 2;
2563 i.vex.bytes[0] = 0xc5;
2564
2565 /* Check the REX.R bit. */
2566 r = (i.rex & REX_R) ? 0 : 1;
2567 i.vex.bytes[1] = (r << 7
2568 | register_specifier << 3
2569 | vector_length << 2
2570 | implied_prefix);
2571 }
2572 else
2573 {
2574 /* 3-byte VEX prefix. */
2575 unsigned int m, w;
2576
2577 if (i.tm.opcode_modifier.vex0f)
2578 m = 0x1;
2579 else if (i.tm.opcode_modifier.vex0f38)
2580 m = 0x2;
2581 else if (i.tm.opcode_modifier.vex0f3a)
2582 m = 0x3;
2583 else
2584 abort ();
2585
2586 i.vex.length = 3;
2587 i.vex.bytes[0] = 0xc4;
2588
2589 /* The high 3 bits of the second VEX byte are 1's compliment
2590 of RXB bits from REX. */
2591 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2592
2593 /* Check the REX.W bit. */
2594 w = (i.rex & REX_W) ? 1 : 0;
2595 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2596 {
2597 if (w)
2598 abort ();
2599
2600 if (i.tm.opcode_modifier.vexw1)
2601 w = 1;
2602 }
2603
2604 i.vex.bytes[2] = (w << 7
2605 | register_specifier << 3
2606 | vector_length << 2
2607 | implied_prefix);
2608 }
2609}
2610
65da13b5
L		 2611static void
2612process_immext (void)
2613{
2614 expressionS *exp;
2615
2616 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2617 {
1fed0ba1
L		 2618 /* SSE3 Instructions have the fixed operands with an opcode
2619 suffix which is coded in the same place as an 8-bit immediate
2620 field would be. Here we check those operands and remove them
2621 afterwards. */
65da13b5
L		 2622 unsigned int x;
2623
2624 for (x = 0; x < i.operands; x++)
2625 if (i.op[x].regs->reg_num != x)
2626 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2627 register_prefix, i.op[x].regs->reg_name, x + 1,
2628 i.tm.name);
2629
2630 i.operands = 0;
65da13b5
L		 2631 }
2632
c0f3af97 2633 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2634 which is coded in the same place as an 8-bit immediate field
2635 would be. Here we fake an 8-bit immediate operand from the
2636 opcode suffix stored in tm.extension_opcode.
2637
c0f3af97
L		 2638 SSE5 and AVX instructions also use this encoding, for some of
2639 3 argument instructions. */
65da13b5
L		 2640
2641 assert (i.imm_operands == 0
2642 && (i.operands <= 2
2643 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2644 && i.operands <= 3)
2645 || (i.tm.opcode_modifier.vex
2646 && i.operands <= 4)));
65da13b5
L		 2647
2648 exp = &im_expressions[i.imm_operands++];
2649 i.op[i.operands].imms = exp;
2650 i.types[i.operands] = imm8;
2651 i.operands++;
2652 exp->X_op = O_constant;
2653 exp->X_add_number = i.tm.extension_opcode;
2654 i.tm.extension_opcode = None;
2655}
2656
252b5132
RH		 2657/* This is the guts of the machine-dependent assembler. LINE points to a
2658 machine dependent instruction. This function is supposed to emit
2659 the frags/bytes it assembles to. */
2660
2661void
65da13b5 2662md_assemble (char *line)
252b5132 2663{
40fb9820 2664 unsigned int j;
252b5132
RH		 2665 char mnemonic[MAX_MNEM_SIZE];
2666
47926f60 2667 /* Initialize globals. */
252b5132
RH		 2668 memset (&i, '\0', sizeof (i));
2669 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2670 i.reloc[j] = NO_RELOC;
252b5132
RH		 2671 memset (disp_expressions, '\0', sizeof (disp_expressions));
2672 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2673 save_stack_p = save_stack;
252b5132
RH		 2674
2675 /* First parse an instruction mnemonic & call i386_operand for the operands.
2676 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2677 start of a (possibly prefixed) mnemonic. */
252b5132 2678
29b0f896
AM		 2679 line = parse_insn (line, mnemonic);
2680 if (line == NULL)
2681 return;
252b5132 2682
29b0f896
AM		 2683 line = parse_operands (line, mnemonic);
2684 if (line == NULL)
2685 return;
252b5132 2686
29b0f896
AM		 2687 /* Now we've parsed the mnemonic into a set of templates, and have the
2688 operands at hand. */
2689
2690 /* All intel opcodes have reversed operands except for "bound" and
2691 "enter". We also don't reverse intersegment "jmp" and "call"
2692 instructions with 2 immediate operands so that the immediate segment
050dfa73 2693 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2694 if (intel_syntax
2695 && i.operands > 1
29b0f896 2696 && (strcmp (mnemonic, "bound") != 0)
30123838 2697 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2698 && !(operand_type_check (i.types[0], imm)
2699 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2700 swap_operands ();
2701
ec56d5c0
JB		 2702 /* The order of the immediates should be reversed
2703 for 2 immediates extrq and insertq instructions */
2704 if (i.imm_operands == 2
2705 && (strcmp (mnemonic, "extrq") == 0
2706 || strcmp (mnemonic, "insertq") == 0))
2707 swap_2_operands (0, 1);
2708
29b0f896
AM		 2709 if (i.imm_operands)
2710 optimize_imm ();
2711
b300c311
L		 2712 /* Don't optimize displacement for movabs since it only takes 64bit
2713 displacement. */
2714 if (i.disp_operands
2715 && (flag_code != CODE_64BIT
2716 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2717 optimize_disp ();
2718
2719 /* Next, we find a template that matches the given insn,
2720 making sure the overlap of the given operands types is consistent
2721 with the template operand types. */
252b5132 2722
29b0f896
AM		 2723 if (!match_template ())
2724 return;
252b5132 2725
daf50ae7 2726 if (sse_check != sse_check_none
81f8a913 2727 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2728 && (i.tm.cpu_flags.bitfield.cpusse
2729 || i.tm.cpu_flags.bitfield.cpusse2
2730 || i.tm.cpu_flags.bitfield.cpusse3
2731 || i.tm.cpu_flags.bitfield.cpussse3
2732 || i.tm.cpu_flags.bitfield.cpusse4_1
2733 || i.tm.cpu_flags.bitfield.cpusse4_2))
2734 {
2735 (sse_check == sse_check_warning
2736 ? as_warn
2737 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2738 }
2739
321fd21e
L		 2740 /* Zap movzx and movsx suffix. The suffix has been set from
2741 "word ptr" or "byte ptr" on the source operand in Intel syntax
2742 or extracted from mnemonic in AT&T syntax. But we'll use
2743 the destination register to choose the suffix for encoding. */
2744 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2745 {
321fd21e
L		 2746 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2747 there is no suffix, the default will be byte extension. */
2748 if (i.reg_operands != 2
2749 && !i.suffix
2750 && intel_syntax)
2751 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2752
2753 i.suffix = 0;
cd61ebfe 2754 }
24eab124 2755
40fb9820 2756 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2757 if (!add_prefix (FWAIT_OPCODE))
2758 return;
252b5132 2759
29b0f896 2760 /* Check string instruction segment overrides. */
40fb9820 2761 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2762 {
2763 if (!check_string ())
5dd0794d 2764 return;
fc0763e6 2765 i.disp_operands = 0;
29b0f896 2766 }
5dd0794d 2767
29b0f896
AM		 2768 if (!process_suffix ())
2769 return;
e413e4e9 2770
29b0f896
AM		 2771 /* Make still unresolved immediate matches conform to size of immediate
2772 given in i.suffix. */
2773 if (!finalize_imm ())
2774 return;
252b5132 2775
40fb9820 2776 if (i.types[0].bitfield.imm1)
29b0f896 2777 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2778
40fb9820 2779 for (j = 0; j < 3; j++)
c6fb90c8
L		 2780 if (i.types[j].bitfield.inoutportreg
2781 || i.types[j].bitfield.shiftcount
2782 || i.types[j].bitfield.acc
2783 || i.types[j].bitfield.floatacc)
40fb9820
L		 2784 i.reg_operands--;
2785
c0f3af97
L		 2786 /* ImmExt should be processed after SSE2AVX. */
2787 if (!i.tm.opcode_modifier.sse2avx
2788 && i.tm.opcode_modifier.immext)
65da13b5 2789 process_immext ();
252b5132 2790
29b0f896
AM		 2791 /* For insns with operands there are more diddles to do to the opcode. */
2792 if (i.operands)
2793 {
2794 if (!process_operands ())
2795 return;
2796 }
40fb9820 2797 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2798 {
2799 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2800 as_warn (_("translating to `%sp'"), i.tm.name);
2801 }
252b5132 2802
c0f3af97
L		 2803 if (i.tm.opcode_modifier.vex)
2804 build_vex_prefix ();
2805
29b0f896
AM		 2806 /* Handle conversion of 'int $3' --> special int3 insn. */
2807 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2808 {
2809 i.tm.base_opcode = INT3_OPCODE;
2810 i.imm_operands = 0;
2811 }
252b5132 2812
40fb9820
L		 2813 if ((i.tm.opcode_modifier.jump
2814 || i.tm.opcode_modifier.jumpbyte
2815 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2816 && i.op[0].disps->X_op == O_constant)
2817 {
2818 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2819 the absolute address given by the constant. Since ix86 jumps and
2820 calls are pc relative, we need to generate a reloc. */
2821 i.op[0].disps->X_add_symbol = &abs_symbol;
2822 i.op[0].disps->X_op = O_symbol;
2823 }
252b5132 2824
40fb9820 2825 if (i.tm.opcode_modifier.rex64)
161a04f6 2826 i.rex |= REX_W;
252b5132 2827
29b0f896
AM		 2828 /* For 8 bit registers we need an empty rex prefix. Also if the
2829 instruction already has a prefix, we need to convert old
2830 registers to new ones. */
773f551c 2831
40fb9820 2832 if ((i.types[0].bitfield.reg8
29b0f896 2833 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2834 || (i.types[1].bitfield.reg8
29b0f896 2835 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2836 || ((i.types[0].bitfield.reg8
2837 || i.types[1].bitfield.reg8)
29b0f896
AM		 2838 && i.rex != 0))
2839 {
2840 int x;
726c5dcd 2841
29b0f896
AM		 2842 i.rex |= REX_OPCODE;
2843 for (x = 0; x < 2; x++)
2844 {
2845 /* Look for 8 bit operand that uses old registers. */
40fb9820 2846 if (i.types[x].bitfield.reg8
29b0f896 2847 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2848 {
29b0f896
AM		 2849 /* In case it is "hi" register, give up. */
2850 if (i.op[x].regs->reg_num > 3)
a540244d 2851 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2852 "instruction requiring REX prefix."),
a540244d 2853 register_prefix, i.op[x].regs->reg_name);
773f551c 2854
29b0f896
AM		 2855 /* Otherwise it is equivalent to the extended register.
2856 Since the encoding doesn't change this is merely
2857 cosmetic cleanup for debug output. */
2858
2859 i.op[x].regs = i.op[x].regs + 8;
773f551c 2860 }
29b0f896
AM		 2861 }
2862 }
773f551c 2863
85f10a01
MM		 2864 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2865 REX prefix. */
2866 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2867 {
2868 i.drex.rex = i.rex;
2869 i.rex = 0;
2870 }
2871 else if (i.rex != 0)
29b0f896
AM		 2872 add_prefix (REX_OPCODE | i.rex);
2873
2874 /* We are ready to output the insn. */
2875 output_insn ();
2876}
2877
2878static char *
e3bb37b5 2879parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2880{
2881 char *l = line;
2882 char *token_start = l;
2883 char *mnem_p;
5c6af06e
JB		 2884 int supported;
2885 const template *t;
29b0f896
AM		 2886
2887 /* Non-zero if we found a prefix only acceptable with string insns. */
2888 const char *expecting_string_instruction = NULL;
45288df1 2889
29b0f896
AM		 2890 while (1)
2891 {
2892 mnem_p = mnemonic;
2893 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2894 {
2895 mnem_p++;
2896 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2897 {
29b0f896
AM		 2898 as_bad (_("no such instruction: `%s'"), token_start);
2899 return NULL;
2900 }
2901 l++;
2902 }
2903 if (!is_space_char (*l)
2904 && *l != END_OF_INSN
e44823cf
JB		 2905 && (intel_syntax
2906 || (*l != PREFIX_SEPARATOR
2907 && *l != ',')))
29b0f896
AM		 2908 {
2909 as_bad (_("invalid character %s in mnemonic"),
2910 output_invalid (*l));
2911 return NULL;
2912 }
2913 if (token_start == l)
2914 {
e44823cf 2915 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2916 as_bad (_("expecting prefix; got nothing"));
2917 else
2918 as_bad (_("expecting mnemonic; got nothing"));
2919 return NULL;
2920 }
45288df1 2921
29b0f896
AM		 2922 /* Look up instruction (or prefix) via hash table. */
2923 current_templates = hash_find (op_hash, mnemonic);
47926f60 2924
29b0f896
AM		 2925 if (*l != END_OF_INSN
2926 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2927 && current_templates
40fb9820 2928 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2929 {
c6fb90c8 2930 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2931 {
2932 as_bad ((flag_code != CODE_64BIT
2933 ? _("`%s' is only supported in 64-bit mode")
2934 : _("`%s' is not supported in 64-bit mode")),
2935 current_templates->start->name);
2936 return NULL;
2937 }
29b0f896
AM		 2938 /* If we are in 16-bit mode, do not allow addr16 or data16.
2939 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2940 if ((current_templates->start->opcode_modifier.size16
2941 || current_templates->start->opcode_modifier.size32)
29b0f896 2942 && flag_code != CODE_64BIT
40fb9820 2943 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2944 ^ (flag_code == CODE_16BIT)))
2945 {
2946 as_bad (_("redundant %s prefix"),
2947 current_templates->start->name);
2948 return NULL;
45288df1 2949 }
29b0f896
AM		 2950 /* Add prefix, checking for repeated prefixes. */
2951 switch (add_prefix (current_templates->start->base_opcode))
2952 {
2953 case 0:
2954 return NULL;
2955 case 2:
2956 expecting_string_instruction = current_templates->start->name;
2957 break;
2958 }
2959 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2960 token_start = ++l;
2961 }
2962 else
2963 break;
2964 }
45288df1 2965
29b0f896
AM		 2966 if (!current_templates)
2967 {
2968 /* See if we can get a match by trimming off a suffix. */
2969 switch (mnem_p[-1])
2970 {
2971 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2972 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2973 i.suffix = SHORT_MNEM_SUFFIX;
2974 else
29b0f896
AM		 2975 case BYTE_MNEM_SUFFIX:
2976 case QWORD_MNEM_SUFFIX:
2977 i.suffix = mnem_p[-1];
2978 mnem_p[-1] = '\0';
2979 current_templates = hash_find (op_hash, mnemonic);
2980 break;
2981 case SHORT_MNEM_SUFFIX:
2982 case LONG_MNEM_SUFFIX:
2983 if (!intel_syntax)
2984 {
2985 i.suffix = mnem_p[-1];
2986 mnem_p[-1] = '\0';
2987 current_templates = hash_find (op_hash, mnemonic);
2988 }
2989 break;
252b5132 2990
29b0f896
AM		 2991 /* Intel Syntax. */
2992 case 'd':
2993 if (intel_syntax)
2994 {
9306ca4a 2995 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2996 i.suffix = SHORT_MNEM_SUFFIX;
2997 else
2998 i.suffix = LONG_MNEM_SUFFIX;
2999 mnem_p[-1] = '\0';
3000 current_templates = hash_find (op_hash, mnemonic);
3001 }
3002 break;
3003 }
3004 if (!current_templates)
3005 {
3006 as_bad (_("no such instruction: `%s'"), token_start);
3007 return NULL;
3008 }
3009 }
252b5132 3010
40fb9820
L		 3011 if (current_templates->start->opcode_modifier.jump
3012 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3013 {
3014 /* Check for a branch hint. We allow ",pt" and ",pn" for
3015 predict taken and predict not taken respectively.
3016 I'm not sure that branch hints actually do anything on loop
3017 and jcxz insns (JumpByte) for current Pentium4 chips. They
3018 may work in the future and it doesn't hurt to accept them
3019 now. */
3020 if (l[0] == ',' && l[1] == 'p')
3021 {
3022 if (l[2] == 't')
3023 {
3024 if (!add_prefix (DS_PREFIX_OPCODE))
3025 return NULL;
3026 l += 3;
3027 }
3028 else if (l[2] == 'n')
3029 {
3030 if (!add_prefix (CS_PREFIX_OPCODE))
3031 return NULL;
3032 l += 3;
3033 }
3034 }
3035 }
3036 /* Any other comma loses. */
3037 if (*l == ',')
3038 {
3039 as_bad (_("invalid character %s in mnemonic"),
3040 output_invalid (*l));
3041 return NULL;
3042 }
252b5132 3043
29b0f896 3044 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3045 supported = 0;
3046 for (t = current_templates->start; t < current_templates->end; ++t)
3047 {
c0f3af97
L		 3048 supported |= cpu_flags_match (t);
3049 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3050 goto skip;
5c6af06e 3051 }
3629bb00 3052
c0f3af97 3053 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3054 {
3055 as_bad (flag_code == CODE_64BIT
3056 ? _("`%s' is not supported in 64-bit mode")
3057 : _("`%s' is only supported in 64-bit mode"),
3058 current_templates->start->name);
3059 return NULL;
3060 }
c0f3af97 3061 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3062 {
3629bb00
L		 3063 as_bad (_("`%s' is not supported on `%s%s'"),
3064 current_templates->start->name, cpu_arch_name,
3065 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3066 return NULL;
29b0f896 3067 }
3629bb00
L		 3068
3069skip:
3070 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3071 && (flag_code != CODE_16BIT))
29b0f896
AM		 3072 {
3073 as_warn (_("use .code16 to ensure correct addressing mode"));
3074 }
252b5132 3075
29b0f896 3076 /* Check for rep/repne without a string instruction. */
f41bbced 3077 if (expecting_string_instruction)
29b0f896 3078 {
f41bbced
JB		 3079 static templates override;
3080
3081 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3082 if (t->opcode_modifier.isstring)
f41bbced
JB		 3083 break;
3084 if (t >= current_templates->end)
3085 {
3086 as_bad (_("expecting string instruction after `%s'"),
64e74474 3087 expecting_string_instruction);
f41bbced
JB		 3088 return NULL;
3089 }
3090 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3091 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3092 break;
3093 override.end = t;
3094 current_templates = &override;
29b0f896 3095 }
252b5132 3096
29b0f896
AM		 3097 return l;
3098}
252b5132 3099
29b0f896 3100static char *
e3bb37b5 3101parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3102{
3103 char *token_start;
3138f287 3104
29b0f896
AM		 3105 /* 1 if operand is pending after ','. */
3106 unsigned int expecting_operand = 0;
252b5132 3107
29b0f896
AM		 3108 /* Non-zero if operand parens not balanced. */
3109 unsigned int paren_not_balanced;
3110
3111 while (*l != END_OF_INSN)
3112 {
3113 /* Skip optional white space before operand. */
3114 if (is_space_char (*l))
3115 ++l;
3116 if (!is_operand_char (*l) && *l != END_OF_INSN)
3117 {
3118 as_bad (_("invalid character %s before operand %d"),
3119 output_invalid (*l),
3120 i.operands + 1);
3121 return NULL;
3122 }
3123 token_start = l; /* after white space */
3124 paren_not_balanced = 0;
3125 while (paren_not_balanced || *l != ',')
3126 {
3127 if (*l == END_OF_INSN)
3128 {
3129 if (paren_not_balanced)
3130 {
3131 if (!intel_syntax)
3132 as_bad (_("unbalanced parenthesis in operand %d."),
3133 i.operands + 1);
3134 else
3135 as_bad (_("unbalanced brackets in operand %d."),
3136 i.operands + 1);
3137 return NULL;
3138 }
3139 else
3140 break; /* we are done */
3141 }
3142 else if (!is_operand_char (*l) && !is_space_char (*l))
3143 {
3144 as_bad (_("invalid character %s in operand %d"),
3145 output_invalid (*l),
3146 i.operands + 1);
3147 return NULL;
3148 }
3149 if (!intel_syntax)
3150 {
3151 if (*l == '(')
3152 ++paren_not_balanced;
3153 if (*l == ')')
3154 --paren_not_balanced;
3155 }
3156 else
3157 {
3158 if (*l == '[')
3159 ++paren_not_balanced;
3160 if (*l == ']')
3161 --paren_not_balanced;
3162 }
3163 l++;
3164 }
3165 if (l != token_start)
3166 { /* Yes, we've read in another operand. */
3167 unsigned int operand_ok;
3168 this_operand = i.operands++;
7d5e4556 3169 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3170 if (i.operands > MAX_OPERANDS)
3171 {
3172 as_bad (_("spurious operands; (%d operands/instruction max)"),
3173 MAX_OPERANDS);
3174 return NULL;
3175 }
3176 /* Now parse operand adding info to 'i' as we go along. */
3177 END_STRING_AND_SAVE (l);
3178
3179 if (intel_syntax)
3180 operand_ok =
3181 i386_intel_operand (token_start,
3182 intel_float_operand (mnemonic));
3183 else
a7619375 3184 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3185
3186 RESTORE_END_STRING (l);
3187 if (!operand_ok)
3188 return NULL;
3189 }
3190 else
3191 {
3192 if (expecting_operand)
3193 {
3194 expecting_operand_after_comma:
3195 as_bad (_("expecting operand after ','; got nothing"));
3196 return NULL;
3197 }
3198 if (*l == ',')
3199 {
3200 as_bad (_("expecting operand before ','; got nothing"));
3201 return NULL;
3202 }
3203 }
7f3f1ea2 3204
29b0f896
AM		 3205 /* Now *l must be either ',' or END_OF_INSN. */
3206 if (*l == ',')
3207 {
3208 if (*++l == END_OF_INSN)
3209 {
3210 /* Just skip it, if it's \n complain. */
3211 goto expecting_operand_after_comma;
3212 }
3213 expecting_operand = 1;
3214 }
3215 }
3216 return l;
3217}
7f3f1ea2 3218
050dfa73 3219static void
4d456e3d 3220swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3221{
3222 union i386_op temp_op;
40fb9820 3223 i386_operand_type temp_type;
050dfa73 3224 enum bfd_reloc_code_real temp_reloc;
4eed87de 3225
050dfa73
MM		 3226 temp_type = i.types[xchg2];
3227 i.types[xchg2] = i.types[xchg1];
3228 i.types[xchg1] = temp_type;
3229 temp_op = i.op[xchg2];
3230 i.op[xchg2] = i.op[xchg1];
3231 i.op[xchg1] = temp_op;
3232 temp_reloc = i.reloc[xchg2];
3233 i.reloc[xchg2] = i.reloc[xchg1];
3234 i.reloc[xchg1] = temp_reloc;
3235}
3236
29b0f896 3237static void
e3bb37b5 3238swap_operands (void)
29b0f896 3239{
b7c61d9a 3240 switch (i.operands)
050dfa73 3241 {
c0f3af97 3242 case 5:
b7c61d9a 3243 case 4:
4d456e3d 3244 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3245 case 3:
3246 case 2:
4d456e3d 3247 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3248 break;
3249 default:
3250 abort ();
29b0f896 3251 }
29b0f896
AM		 3252
3253 if (i.mem_operands == 2)
3254 {
3255 const seg_entry *temp_seg;
3256 temp_seg = i.seg[0];
3257 i.seg[0] = i.seg[1];
3258 i.seg[1] = temp_seg;
3259 }
3260}
252b5132 3261
29b0f896
AM		 3262/* Try to ensure constant immediates are represented in the smallest
3263 opcode possible. */
3264static void
e3bb37b5 3265optimize_imm (void)
29b0f896
AM		 3266{
3267 char guess_suffix = 0;
3268 int op;
252b5132 3269
29b0f896
AM		 3270 if (i.suffix)
3271 guess_suffix = i.suffix;
3272 else if (i.reg_operands)
3273 {
3274 /* Figure out a suffix from the last register operand specified.
3275 We can't do this properly yet, ie. excluding InOutPortReg,
3276 but the following works for instructions with immediates.
3277 In any case, we can't set i.suffix yet. */
3278 for (op = i.operands; --op >= 0;)
40fb9820
L		 3279 if (i.types[op].bitfield.reg8)
3280 {
3281 guess_suffix = BYTE_MNEM_SUFFIX;
3282 break;
3283 }
3284 else if (i.types[op].bitfield.reg16)
252b5132 3285 {
40fb9820
L		 3286 guess_suffix = WORD_MNEM_SUFFIX;
3287 break;
3288 }
3289 else if (i.types[op].bitfield.reg32)
3290 {
3291 guess_suffix = LONG_MNEM_SUFFIX;
3292 break;
3293 }
3294 else if (i.types[op].bitfield.reg64)
3295 {
3296 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3297 break;
252b5132 3298 }
29b0f896
AM		 3299 }
3300 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3301 guess_suffix = WORD_MNEM_SUFFIX;
3302
3303 for (op = i.operands; --op >= 0;)
40fb9820 3304 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3305 {
3306 switch (i.op[op].imms->X_op)
252b5132 3307 {
29b0f896
AM		 3308 case O_constant:
3309 /* If a suffix is given, this operand may be shortened. */
3310 switch (guess_suffix)
252b5132 3311 {
29b0f896 3312 case LONG_MNEM_SUFFIX:
40fb9820
L		 3313 i.types[op].bitfield.imm32 = 1;
3314 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3315 break;
3316 case WORD_MNEM_SUFFIX:
40fb9820
L		 3317 i.types[op].bitfield.imm16 = 1;
3318 i.types[op].bitfield.imm32 = 1;
3319 i.types[op].bitfield.imm32s = 1;
3320 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3321 break;
3322 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3323 i.types[op].bitfield.imm8 = 1;
3324 i.types[op].bitfield.imm8s = 1;
3325 i.types[op].bitfield.imm16 = 1;
3326 i.types[op].bitfield.imm32 = 1;
3327 i.types[op].bitfield.imm32s = 1;
3328 i.types[op].bitfield.imm64 = 1;
29b0f896 3329 break;
252b5132 3330 }
252b5132 3331
29b0f896
AM		 3332 /* If this operand is at most 16 bits, convert it
3333 to a signed 16 bit number before trying to see
3334 whether it will fit in an even smaller size.
3335 This allows a 16-bit operand such as $0xffe0 to
3336 be recognised as within Imm8S range. */
40fb9820 3337 if ((i.types[op].bitfield.imm16)
29b0f896 3338 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3339 {
29b0f896
AM		 3340 i.op[op].imms->X_add_number =
3341 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3342 }
40fb9820 3343 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3344 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3345 == 0))
3346 {
3347 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3348 ^ ((offsetT) 1 << 31))
3349 - ((offsetT) 1 << 31));
3350 }
40fb9820 3351 i.types[op]
c6fb90c8
L		 3352 = operand_type_or (i.types[op],
3353 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3354
29b0f896
AM		 3355 /* We must avoid matching of Imm32 templates when 64bit
3356 only immediate is available. */
3357 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3358 i.types[op].bitfield.imm32 = 0;
29b0f896 3359 break;
252b5132 3360
29b0f896
AM		 3361 case O_absent:
3362 case O_register:
3363 abort ();
3364
3365 /* Symbols and expressions. */
3366 default:
9cd96992
JB		 3367 /* Convert symbolic operand to proper sizes for matching, but don't
3368 prevent matching a set of insns that only supports sizes other
3369 than those matching the insn suffix. */
3370 {
40fb9820 3371 i386_operand_type mask, allowed;
9cd96992
JB		 3372 const template *t;
3373
0dfbf9d7
L		 3374 operand_type_set (&mask, 0);
3375 operand_type_set (&allowed, 0);
40fb9820 3376
4eed87de
AM		 3377 for (t = current_templates->start;
3378 t < current_templates->end;
3379 ++t)
c6fb90c8
L		 3380 allowed = operand_type_or (allowed,
3381 t->operand_types[op]);
9cd96992
JB		 3382 switch (guess_suffix)
3383 {
3384 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3385 mask.bitfield.imm64 = 1;
3386 mask.bitfield.imm32s = 1;
9cd96992
JB		 3387 break;
3388 case LONG_MNEM_SUFFIX:
40fb9820 3389 mask.bitfield.imm32 = 1;
9cd96992
JB		 3390 break;
3391 case WORD_MNEM_SUFFIX:
40fb9820 3392 mask.bitfield.imm16 = 1;
9cd96992
JB		 3393 break;
3394 case BYTE_MNEM_SUFFIX:
40fb9820 3395 mask.bitfield.imm8 = 1;
9cd96992
JB		 3396 break;
3397 default:
9cd96992
JB		 3398 break;
3399 }
c6fb90c8 3400 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3401 if (!operand_type_all_zero (&allowed))
c6fb90c8 3402 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3403 }
29b0f896 3404 break;
252b5132 3405 }
29b0f896
AM		 3406 }
3407}
47926f60 3408
29b0f896
AM		 3409/* Try to use the smallest displacement type too. */
3410static void
e3bb37b5 3411optimize_disp (void)
29b0f896
AM		 3412{
3413 int op;
3e73aa7c 3414
29b0f896 3415 for (op = i.operands; --op >= 0;)
40fb9820 3416 if (operand_type_check (i.types[op], disp))
252b5132 3417 {
b300c311 3418 if (i.op[op].disps->X_op == O_constant)
252b5132 3419 {
b300c311 3420 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3421
40fb9820 3422 if (i.types[op].bitfield.disp16
b300c311
L		 3423 && (disp & ~(offsetT) 0xffff) == 0)
3424 {
3425 /* If this operand is at most 16 bits, convert
3426 to a signed 16 bit number and don't use 64bit
3427 displacement. */
3428 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3429 i.types[op].bitfield.disp64 = 0;
b300c311 3430 }
40fb9820 3431 if (i.types[op].bitfield.disp32
b300c311
L		 3432 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3433 {
3434 /* If this operand is at most 32 bits, convert
3435 to a signed 32 bit number and don't use 64bit
3436 displacement. */
3437 disp &= (((offsetT) 2 << 31) - 1);
3438 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3439 i.types[op].bitfield.disp64 = 0;
b300c311 3440 }
40fb9820 3441 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3442 {
40fb9820
L		 3443 i.types[op].bitfield.disp8 = 0;
3444 i.types[op].bitfield.disp16 = 0;
3445 i.types[op].bitfield.disp32 = 0;
3446 i.types[op].bitfield.disp32s = 0;
3447 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3448 i.op[op].disps = 0;
3449 i.disp_operands--;
3450 }
3451 else if (flag_code == CODE_64BIT)
3452 {
3453 if (fits_in_signed_long (disp))
28a9d8f5 3454 {
40fb9820
L		 3455 i.types[op].bitfield.disp64 = 0;
3456 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3457 }
b300c311 3458 if (fits_in_unsigned_long (disp))
40fb9820 3459 i.types[op].bitfield.disp32 = 1;
b300c311 3460 }
40fb9820
L		 3461 if ((i.types[op].bitfield.disp32
3462 || i.types[op].bitfield.disp32s
3463 || i.types[op].bitfield.disp16)
b300c311 3464 && fits_in_signed_byte (disp))
40fb9820 3465 i.types[op].bitfield.disp8 = 1;
252b5132 3466 }
67a4f2b7
AO		 3467 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3468 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3469 {
3470 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3471 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3472 i.types[op].bitfield.disp8 = 0;
3473 i.types[op].bitfield.disp16 = 0;
3474 i.types[op].bitfield.disp32 = 0;
3475 i.types[op].bitfield.disp32s = 0;
3476 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3477 }
3478 else
b300c311 3479 /* We only support 64bit displacement on constants. */
40fb9820 3480 i.types[op].bitfield.disp64 = 0;
252b5132 3481 }
29b0f896
AM		 3482}
3483
c0f3af97
L		 3484/* Check if operands are valid for the instrucrtion. Update VEX
3485 operand types. */
3486
3487static int
3488VEX_check_operands (const template *t)
3489{
3490 if (!t->opcode_modifier.vex)
3491 return 0;
3492
3493 /* Only check VEX_Imm4, which must be the first operand. */
3494 if (t->operand_types[0].bitfield.vex_imm4)
3495 {
3496 if (i.op[0].imms->X_op != O_constant
3497 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3498 return 1;
3499
3500 /* Turn off Imm8 so that update_imm won't complain. */
3501 i.types[0] = vex_imm4;
3502 }
3503
3504 return 0;
3505}
3506
29b0f896 3507static int
e3bb37b5 3508match_template (void)
29b0f896
AM		 3509{
3510 /* Points to template once we've found it. */
3511 const template *t;
40fb9820 3512 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3513 i386_operand_type overlap4;
29b0f896 3514 unsigned int found_reverse_match;
40fb9820
L		 3515 i386_opcode_modifier suffix_check;
3516 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3517 int addr_prefix_disp;
a5c311ca 3518 unsigned int j;
3629bb00 3519 unsigned int found_cpu_match;
45664ddb 3520 unsigned int check_register;
29b0f896 3521
c0f3af97
L		 3522#if MAX_OPERANDS != 5
3523# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3524#endif
3525
29b0f896 3526 found_reverse_match = 0;
539e75ad 3527 addr_prefix_disp = -1;
40fb9820
L		 3528
3529 memset (&suffix_check, 0, sizeof (suffix_check));
3530 if (i.suffix == BYTE_MNEM_SUFFIX)
3531 suffix_check.no_bsuf = 1;
3532 else if (i.suffix == WORD_MNEM_SUFFIX)
3533 suffix_check.no_wsuf = 1;
3534 else if (i.suffix == SHORT_MNEM_SUFFIX)
3535 suffix_check.no_ssuf = 1;
3536 else if (i.suffix == LONG_MNEM_SUFFIX)
3537 suffix_check.no_lsuf = 1;
3538 else if (i.suffix == QWORD_MNEM_SUFFIX)
3539 suffix_check.no_qsuf = 1;
3540 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3541 suffix_check.no_ldsuf = 1;
29b0f896 3542
45aa61fe 3543 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3544 {
539e75ad
L		 3545 addr_prefix_disp = -1;
3546
29b0f896
AM		 3547 /* Must have right number of operands. */
3548 if (i.operands != t->operands)
3549 continue;
3550
50aecf8c 3551 /* Check processor support. */
c0f3af97
L		 3552 found_cpu_match = (cpu_flags_match (t)
3553 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3554 if (!found_cpu_match)
3555 continue;
3556
e1d4d893
L		 3557 /* Check old gcc support. */
3558 if (!old_gcc && t->opcode_modifier.oldgcc)
3559 continue;
3560
3561 /* Check AT&T mnemonic. */
3562 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3563 continue;
3564
5c07affc
L		 3565 /* Check AT&T syntax Intel syntax. */
3566 if ((intel_syntax && t->opcode_modifier.attsyntax)
3567 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3568 continue;
3569
20592a94 3570 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3571 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3572 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3573 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3574 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3575 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3576 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3577 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3578 continue;
3579
5c07affc 3580 if (!operand_size_match (t))
7d5e4556 3581 continue;
539e75ad 3582
5c07affc
L		 3583 for (j = 0; j < MAX_OPERANDS; j++)
3584 operand_types[j] = t->operand_types[j];
3585
45aa61fe
AM		 3586 /* In general, don't allow 64-bit operands in 32-bit mode. */
3587 if (i.suffix == QWORD_MNEM_SUFFIX
3588 && flag_code != CODE_64BIT
3589 && (intel_syntax
40fb9820 3590 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3591 && !intel_float_operand (t->name))
3592 : intel_float_operand (t->name) != 2)
40fb9820 3593 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3594 && !operand_types[0].bitfield.regxmm
3595 && !operand_types[0].bitfield.regymm)
40fb9820 3596 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3597 && !!operand_types[t->operands > 1].bitfield.regxmm
3598 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3599 && (t->base_opcode != 0x0fc7
3600 || t->extension_opcode != 1 /* cmpxchg8b */))
3601 continue;
3602
192dc9c6
JB		 3603 /* In general, don't allow 32-bit operands on pre-386. */
3604 else if (i.suffix == LONG_MNEM_SUFFIX
3605 && !cpu_arch_flags.bitfield.cpui386
3606 && (intel_syntax
3607 ? (!t->opcode_modifier.ignoresize
3608 && !intel_float_operand (t->name))
3609 : intel_float_operand (t->name) != 2)
3610 && ((!operand_types[0].bitfield.regmmx
3611 && !operand_types[0].bitfield.regxmm)
3612 || (!operand_types[t->operands > 1].bitfield.regmmx
3613 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3614 continue;
3615
29b0f896 3616 /* Do not verify operands when there are none. */
50aecf8c 3617 else
29b0f896 3618 {
c6fb90c8 3619 if (!t->operands)
2dbab7d5
L		 3620 /* We've found a match; break out of loop. */
3621 break;
29b0f896 3622 }
252b5132 3623
539e75ad
L		 3624 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3625 into Disp32/Disp16/Disp32 operand. */
3626 if (i.prefix[ADDR_PREFIX] != 0)
3627 {
40fb9820 3628 /* There should be only one Disp operand. */
539e75ad
L		 3629 switch (flag_code)
3630 {
3631 case CODE_16BIT:
40fb9820
L		 3632 for (j = 0; j < MAX_OPERANDS; j++)
3633 {
3634 if (operand_types[j].bitfield.disp16)
3635 {
3636 addr_prefix_disp = j;
3637 operand_types[j].bitfield.disp32 = 1;
3638 operand_types[j].bitfield.disp16 = 0;
3639 break;
3640 }
3641 }
539e75ad
L		 3642 break;
3643 case CODE_32BIT:
40fb9820
L		 3644 for (j = 0; j < MAX_OPERANDS; j++)
3645 {
3646 if (operand_types[j].bitfield.disp32)
3647 {
3648 addr_prefix_disp = j;
3649 operand_types[j].bitfield.disp32 = 0;
3650 operand_types[j].bitfield.disp16 = 1;
3651 break;
3652 }
3653 }
539e75ad
L		 3654 break;
3655 case CODE_64BIT:
40fb9820
L		 3656 for (j = 0; j < MAX_OPERANDS; j++)
3657 {
3658 if (operand_types[j].bitfield.disp64)
3659 {
3660 addr_prefix_disp = j;
3661 operand_types[j].bitfield.disp64 = 0;
3662 operand_types[j].bitfield.disp32 = 1;
3663 break;
3664 }
3665 }
539e75ad
L		 3666 break;
3667 }
539e75ad
L		 3668 }
3669
45664ddb
L		 3670 /* We check register size only if size of operands can be
3671 encoded the canonical way. */
3672 check_register = t->opcode_modifier.w;
c6fb90c8 3673 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3674 switch (t->operands)
3675 {
3676 case 1:
40fb9820 3677 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3678 continue;
3679 break;
3680 case 2:
8b38ad71
L		 3681 /* xchg %eax, %eax is a special case. It is an aliase for nop
3682 only in 32bit mode and we can use opcode 0x90. In 64bit
3683 mode, we can't use 0x90 for xchg %eax, %eax since it should
3684 zero-extend %eax to %rax. */
3685 if (flag_code == CODE_64BIT
3686 && t->base_opcode == 0x90
0dfbf9d7
L		 3687 && operand_type_equal (&i.types [0], &acc32)
3688 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3689 continue;
29b0f896 3690 case 3:
f48ff2ae 3691 case 4:
c0f3af97 3692 case 5:
c6fb90c8 3693 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3694 if (!operand_type_match (overlap0, i.types[0])
3695 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3696 || (check_register
3697 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3698 operand_types[0],
3699 overlap1, i.types[1],
3700 operand_types[1])))
29b0f896
AM		 3701 {
3702 /* Check if other direction is valid ... */
40fb9820 3703 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3704 continue;
3705
3706 /* Try reversing direction of operands. */
c6fb90c8
L		 3707 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3708 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3709 if (!operand_type_match (overlap0, i.types[0])
3710 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3711 || (check_register
3712 && !operand_type_register_match (overlap0,
3713 i.types[0],
3714 operand_types[1],
3715 overlap1,
3716 i.types[1],
3717 operand_types[0])))
29b0f896
AM		 3718 {
3719 /* Does not match either direction. */
3720 continue;
3721 }
3722 /* found_reverse_match holds which of D or FloatDR
3723 we've found. */
40fb9820 3724 if (t->opcode_modifier.d)
8a2ed489 3725 found_reverse_match = Opcode_D;
40fb9820 3726 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3727 found_reverse_match = Opcode_FloatD;
3728 else
3729 found_reverse_match = 0;
40fb9820 3730 if (t->opcode_modifier.floatr)
8a2ed489 3731 found_reverse_match |= Opcode_FloatR;
29b0f896 3732 }
f48ff2ae 3733 else
29b0f896 3734 {
f48ff2ae 3735 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3736 switch (t->operands)
3737 {
c0f3af97
L		 3738 case 5:
3739 overlap4 = operand_type_and (i.types[4],
3740 operand_types[4]);
d1cbb4db 3741 case 4:
c6fb90c8
L		 3742 overlap3 = operand_type_and (i.types[3],
3743 operand_types[3]);
d1cbb4db 3744 case 3:
c6fb90c8
L		 3745 overlap2 = operand_type_and (i.types[2],
3746 operand_types[2]);
d1cbb4db
L		 3747 break;
3748 }
29b0f896 3749
f48ff2ae
L		 3750 switch (t->operands)
3751 {
c0f3af97
L		 3752 case 5:
3753 if (!operand_type_match (overlap4, i.types[4])
3754 || !operand_type_register_match (overlap3,
3755 i.types[3],
3756 operand_types[3],
3757 overlap4,
3758 i.types[4],
3759 operand_types[4]))
3760 continue;
f48ff2ae 3761 case 4:
40fb9820 3762 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3763 || (check_register
3764 && !operand_type_register_match (overlap2,
3765 i.types[2],
3766 operand_types[2],
3767 overlap3,
3768 i.types[3],
3769 operand_types[3])))
f48ff2ae
L		 3770 continue;
3771 case 3:
3772 /* Here we make use of the fact that there are no
3773 reverse match 3 operand instructions, and all 3
3774 operand instructions only need to be checked for
3775 register consistency between operands 2 and 3. */
40fb9820 3776 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3777 || (check_register
3778 && !operand_type_register_match (overlap1,
3779 i.types[1],
3780 operand_types[1],
3781 overlap2,
3782 i.types[2],
3783 operand_types[2])))
f48ff2ae
L		 3784 continue;
3785 break;
3786 }
29b0f896 3787 }
f48ff2ae 3788 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3789 slip through to break. */
3790 }
3629bb00 3791 if (!found_cpu_match)
29b0f896
AM		 3792 {
3793 found_reverse_match = 0;
3794 continue;
3795 }
c0f3af97
L		 3796
3797 /* Check if VEX operands are valid. */
3798 if (VEX_check_operands (t))
3799 continue;
3800
29b0f896
AM		 3801 /* We've found a match; break out of loop. */
3802 break;
3803 }
3804
3805 if (t == current_templates->end)
3806 {
3807 /* We found no match. */
95f283e8
L		 3808 if (intel_syntax)
3809 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3810 current_templates->start->name);
3811 else
3812 as_bad (_("suffix or operands invalid for `%s'"),
3813 current_templates->start->name);
29b0f896
AM		 3814 return 0;
3815 }
252b5132 3816
29b0f896
AM		 3817 if (!quiet_warnings)
3818 {
3819 if (!intel_syntax
40fb9820
L		 3820 && (i.types[0].bitfield.jumpabsolute
3821 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3822 {
3823 as_warn (_("indirect %s without `*'"), t->name);
3824 }
3825
40fb9820
L		 3826 if (t->opcode_modifier.isprefix
3827 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3828 {
3829 /* Warn them that a data or address size prefix doesn't
3830 affect assembly of the next line of code. */
3831 as_warn (_("stand-alone `%s' prefix"), t->name);
3832 }
3833 }
3834
3835 /* Copy the template we found. */
3836 i.tm = *t;
539e75ad
L		 3837
3838 if (addr_prefix_disp != -1)
3839 i.tm.operand_types[addr_prefix_disp]
3840 = operand_types[addr_prefix_disp];
3841
29b0f896
AM		 3842 if (found_reverse_match)
3843 {
3844 /* If we found a reverse match we must alter the opcode
3845 direction bit. found_reverse_match holds bits to change
3846 (different for int & float insns). */
3847
3848 i.tm.base_opcode ^= found_reverse_match;
3849
539e75ad
L		 3850 i.tm.operand_types[0] = operand_types[1];
3851 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3852 }
3853
3854 return 1;
3855}
3856
3857static int
e3bb37b5 3858check_string (void)
29b0f896 3859{
40fb9820
L		 3860 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3861 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3862 {
3863 if (i.seg[0] != NULL && i.seg[0] != &es)
3864 {
a87af027 3865 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3866 i.tm.name,
a87af027
JB		 3867 mem_op + 1,
3868 register_prefix);
29b0f896
AM		 3869 return 0;
3870 }
3871 /* There's only ever one segment override allowed per instruction.
3872 This instruction possibly has a legal segment override on the
3873 second operand, so copy the segment to where non-string
3874 instructions store it, allowing common code. */
3875 i.seg[0] = i.seg[1];
3876 }
40fb9820 3877 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3878 {
3879 if (i.seg[1] != NULL && i.seg[1] != &es)
3880 {
a87af027 3881 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3882 i.tm.name,
a87af027
JB		 3883 mem_op + 2,
3884 register_prefix);
29b0f896
AM		 3885 return 0;
3886 }
3887 }
3888 return 1;
3889}
3890
3891static int
543613e9 3892process_suffix (void)
29b0f896
AM		 3893{
3894 /* If matched instruction specifies an explicit instruction mnemonic
3895 suffix, use it. */
40fb9820
L		 3896 if (i.tm.opcode_modifier.size16)
3897 i.suffix = WORD_MNEM_SUFFIX;
3898 else if (i.tm.opcode_modifier.size32)
3899 i.suffix = LONG_MNEM_SUFFIX;
3900 else if (i.tm.opcode_modifier.size64)
3901 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3902 else if (i.reg_operands)
3903 {
3904 /* If there's no instruction mnemonic suffix we try to invent one
3905 based on register operands. */
3906 if (!i.suffix)
3907 {
3908 /* We take i.suffix from the last register operand specified,
3909 Destination register type is more significant than source
381d071f
L		 3910 register type. crc32 in SSE4.2 prefers source register
3911 type. */
3912 if (i.tm.base_opcode == 0xf20f38f1)
3913 {
40fb9820
L		 3914 if (i.types[0].bitfield.reg16)
3915 i.suffix = WORD_MNEM_SUFFIX;
3916 else if (i.types[0].bitfield.reg32)
3917 i.suffix = LONG_MNEM_SUFFIX;
3918 else if (i.types[0].bitfield.reg64)
3919 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3920 }
9344ff29 3921 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3922 {
40fb9820 3923 if (i.types[0].bitfield.reg8)
20592a94
L		 3924 i.suffix = BYTE_MNEM_SUFFIX;
3925 }
381d071f
L		 3926
3927 if (!i.suffix)
3928 {
3929 int op;
3930
20592a94
L		 3931 if (i.tm.base_opcode == 0xf20f38f1
3932 || i.tm.base_opcode == 0xf20f38f0)
3933 {
3934 /* We have to know the operand size for crc32. */
3935 as_bad (_("ambiguous memory operand size for `%s`"),
3936 i.tm.name);
3937 return 0;
3938 }
3939
381d071f 3940 for (op = i.operands; --op >= 0;)
40fb9820 3941 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3942 {
40fb9820
L		 3943 if (i.types[op].bitfield.reg8)
3944 {
3945 i.suffix = BYTE_MNEM_SUFFIX;
3946 break;
3947 }
3948 else if (i.types[op].bitfield.reg16)
3949 {
3950 i.suffix = WORD_MNEM_SUFFIX;
3951 break;
3952 }
3953 else if (i.types[op].bitfield.reg32)
3954 {
3955 i.suffix = LONG_MNEM_SUFFIX;
3956 break;
3957 }
3958 else if (i.types[op].bitfield.reg64)
3959 {
3960 i.suffix = QWORD_MNEM_SUFFIX;
3961 break;
3962 }
381d071f
L		 3963 }
3964 }
29b0f896
AM		 3965 }
3966 else if (i.suffix == BYTE_MNEM_SUFFIX)
3967 {
3968 if (!check_byte_reg ())
3969 return 0;
3970 }
3971 else if (i.suffix == LONG_MNEM_SUFFIX)
3972 {
3973 if (!check_long_reg ())
3974 return 0;
3975 }
3976 else if (i.suffix == QWORD_MNEM_SUFFIX)
3977 {
955e1e6a
L		 3978 if (intel_syntax
3979 && i.tm.opcode_modifier.ignoresize
3980 && i.tm.opcode_modifier.no_qsuf)
3981 i.suffix = 0;
3982 else if (!check_qword_reg ())
29b0f896
AM		 3983 return 0;
3984 }
3985 else if (i.suffix == WORD_MNEM_SUFFIX)
3986 {
3987 if (!check_word_reg ())
3988 return 0;
3989 }
c0f3af97
L		 3990 else if (i.suffix == XMMWORD_MNEM_SUFFIX
3991 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 3992 {
c0f3af97 3993 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 3994 should check if it is a valid suffix. */
3995 }
40fb9820 3996 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3997 /* Do nothing if the instruction is going to ignore the prefix. */
3998 ;
3999 else
4000 abort ();
4001 }
40fb9820 4002 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4003 && !i.suffix
4004 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4005 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4006 {
4007 i.suffix = stackop_size;
4008 }
9306ca4a
JB		 4009 else if (intel_syntax
4010 && !i.suffix
40fb9820
L		 4011 && (i.tm.operand_types[0].bitfield.jumpabsolute
4012 || i.tm.opcode_modifier.jumpbyte
4013 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4014 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4015 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4016 {
4017 switch (flag_code)
4018 {
4019 case CODE_64BIT:
40fb9820 4020 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4021 {
4022 i.suffix = QWORD_MNEM_SUFFIX;
4023 break;
4024 }
4025 case CODE_32BIT:
40fb9820 4026 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4027 i.suffix = LONG_MNEM_SUFFIX;
4028 break;
4029 case CODE_16BIT:
40fb9820 4030 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4031 i.suffix = WORD_MNEM_SUFFIX;
4032 break;
4033 }
4034 }
252b5132 4035
9306ca4a 4036 if (!i.suffix)
29b0f896 4037 {
9306ca4a
JB		 4038 if (!intel_syntax)
4039 {
40fb9820 4040 if (i.tm.opcode_modifier.w)
9306ca4a 4041 {
4eed87de
AM		 4042 as_bad (_("no instruction mnemonic suffix given and "
4043 "no register operands; can't size instruction"));
9306ca4a
JB		 4044 return 0;
4045 }
4046 }
4047 else
4048 {
40fb9820
L		 4049 unsigned int suffixes;
4050
4051 suffixes = !i.tm.opcode_modifier.no_bsuf;
4052 if (!i.tm.opcode_modifier.no_wsuf)
4053 suffixes |= 1 << 1;
4054 if (!i.tm.opcode_modifier.no_lsuf)
4055 suffixes |= 1 << 2;
fc4adea1 4056 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4057 suffixes |= 1 << 3;
4058 if (!i.tm.opcode_modifier.no_ssuf)
4059 suffixes |= 1 << 4;
4060 if (!i.tm.opcode_modifier.no_qsuf)
4061 suffixes |= 1 << 5;
4062
4063 /* There are more than suffix matches. */
4064 if (i.tm.opcode_modifier.w
9306ca4a 4065 || ((suffixes & (suffixes - 1))
40fb9820
L		 4066 && !i.tm.opcode_modifier.defaultsize
4067 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4068 {
4069 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4070 return 0;
4071 }
4072 }
29b0f896 4073 }
252b5132 4074
9306ca4a
JB		 4075 /* Change the opcode based on the operand size given by i.suffix;
4076 We don't need to change things for byte insns. */
4077
582d5edd
L		 4078 if (i.suffix
4079 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4080 && i.suffix != XMMWORD_MNEM_SUFFIX
4081 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4082 {
4083 /* It's not a byte, select word/dword operation. */
40fb9820 4084 if (i.tm.opcode_modifier.w)
29b0f896 4085 {
40fb9820 4086 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4087 i.tm.base_opcode |= 8;
4088 else
4089 i.tm.base_opcode |= 1;
4090 }
0f3f3d8b 4091
29b0f896
AM		 4092 /* Now select between word & dword operations via the operand
4093 size prefix, except for instructions that will ignore this
4094 prefix anyway. */
ca61edf2 4095 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4096 {
ca61edf2
L		 4097 /* The address size override prefix changes the size of the
4098 first operand. */
40fb9820
L		 4099 if ((flag_code == CODE_32BIT
4100 && i.op->regs[0].reg_type.bitfield.reg16)
4101 || (flag_code != CODE_32BIT
4102 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4103 if (!add_prefix (ADDR_PREFIX_OPCODE))
4104 return 0;
4105 }
4106 else if (i.suffix != QWORD_MNEM_SUFFIX
4107 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4108 && !i.tm.opcode_modifier.ignoresize
4109 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4110 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4111 || (flag_code == CODE_64BIT
40fb9820 4112 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4113 {
4114 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4115
40fb9820 4116 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4117 prefix = ADDR_PREFIX_OPCODE;
252b5132 4118
29b0f896
AM		 4119 if (!add_prefix (prefix))
4120 return 0;
24eab124 4121 }
252b5132 4122
29b0f896
AM		 4123 /* Set mode64 for an operand. */
4124 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4125 && flag_code == CODE_64BIT
40fb9820 4126 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4127 {
4128 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4129 need rex64. cmpxchg8b is also a special case. */
4130 if (! (i.operands == 2
4131 && i.tm.base_opcode == 0x90
4132 && i.tm.extension_opcode == None
0dfbf9d7
L		 4133 && operand_type_equal (&i.types [0], &acc64)
4134 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4135 && ! (i.operands == 1
4136 && i.tm.base_opcode == 0xfc7
4137 && i.tm.extension_opcode == 1
40fb9820
L		 4138 && !operand_type_check (i.types [0], reg)
4139 && operand_type_check (i.types [0], anymem)))
f6bee062 4140 i.rex |= REX_W;
46e883c5 4141 }
3e73aa7c 4142
29b0f896
AM		 4143 /* Size floating point instruction. */
4144 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4145 if (i.tm.opcode_modifier.floatmf)
543613e9 4146 i.tm.base_opcode ^= 4;
29b0f896 4147 }
7ecd2f8b 4148
29b0f896
AM		 4149 return 1;
4150}
3e73aa7c 4151
29b0f896 4152static int
543613e9 4153check_byte_reg (void)
29b0f896
AM		 4154{
4155 int op;
543613e9 4156
29b0f896
AM		 4157 for (op = i.operands; --op >= 0;)
4158 {
4159 /* If this is an eight bit register, it's OK. If it's the 16 or
4160 32 bit version of an eight bit register, we will just use the
4161 low portion, and that's OK too. */
40fb9820 4162 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4163 continue;
4164
ca61edf2
L		 4165 /* Don't generate this warning if not needed. */
4166 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4167 continue;
4168
9344ff29
L		 4169 /* crc32 doesn't generate this warning. */
4170 if (i.tm.base_opcode == 0xf20f38f0)
4171 continue;
4172
40fb9820
L		 4173 if ((i.types[op].bitfield.reg16
4174 || i.types[op].bitfield.reg32
4175 || i.types[op].bitfield.reg64)
4176 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4177 {
4178 /* Prohibit these changes in the 64bit mode, since the
4179 lowering is more complicated. */
4180 if (flag_code == CODE_64BIT
40fb9820 4181 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4182 {
2ca3ace5
L		 4183 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4184 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4185 i.suffix);
4186 return 0;
4187 }
4188#if REGISTER_WARNINGS
4189 if (!quiet_warnings
40fb9820 4190 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4191 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4192 register_prefix,
40fb9820 4193 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4194 ? REGNAM_AL - REGNAM_AX
4195 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4196 register_prefix,
29b0f896
AM		 4197 i.op[op].regs->reg_name,
4198 i.suffix);
4199#endif
4200 continue;
4201 }
4202 /* Any other register is bad. */
40fb9820
L		 4203 if (i.types[op].bitfield.reg16
4204 || i.types[op].bitfield.reg32
4205 || i.types[op].bitfield.reg64
4206 || i.types[op].bitfield.regmmx
4207 || i.types[op].bitfield.regxmm
c0f3af97 4208 || i.types[op].bitfield.regymm
40fb9820
L		 4209 || i.types[op].bitfield.sreg2
4210 || i.types[op].bitfield.sreg3
4211 || i.types[op].bitfield.control
4212 || i.types[op].bitfield.debug
4213 || i.types[op].bitfield.test
4214 || i.types[op].bitfield.floatreg
4215 || i.types[op].bitfield.floatacc)
29b0f896 4216 {
a540244d
L		 4217 as_bad (_("`%s%s' not allowed with `%s%c'"),
4218 register_prefix,
29b0f896
AM		 4219 i.op[op].regs->reg_name,
4220 i.tm.name,
4221 i.suffix);
4222 return 0;
4223 }
4224 }
4225 return 1;
4226}
4227
4228static int
e3bb37b5 4229check_long_reg (void)
29b0f896
AM		 4230{
4231 int op;
4232
4233 for (op = i.operands; --op >= 0;)
4234 /* Reject eight bit registers, except where the template requires
4235 them. (eg. movzb) */
40fb9820
L		 4236 if (i.types[op].bitfield.reg8
4237 && (i.tm.operand_types[op].bitfield.reg16
4238 || i.tm.operand_types[op].bitfield.reg32
4239 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4240 {
a540244d
L		 4241 as_bad (_("`%s%s' not allowed with `%s%c'"),
4242 register_prefix,
29b0f896
AM		 4243 i.op[op].regs->reg_name,
4244 i.tm.name,
4245 i.suffix);
4246 return 0;
4247 }
4248 /* Warn if the e prefix on a general reg is missing. */
4249 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4250 && i.types[op].bitfield.reg16
4251 && (i.tm.operand_types[op].bitfield.reg32
4252 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4253 {
4254 /* Prohibit these changes in the 64bit mode, since the
4255 lowering is more complicated. */
4256 if (flag_code == CODE_64BIT)
252b5132 4257 {
2ca3ace5
L		 4258 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4259 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4260 i.suffix);
4261 return 0;
252b5132 4262 }
29b0f896
AM		 4263#if REGISTER_WARNINGS
4264 else
a540244d
L		 4265 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4266 register_prefix,
29b0f896 4267 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4268 register_prefix,
29b0f896
AM		 4269 i.op[op].regs->reg_name,
4270 i.suffix);
4271#endif
252b5132 4272 }
29b0f896 4273 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4274 else if (i.types[op].bitfield.reg64
4275 && (i.tm.operand_types[op].bitfield.reg32
4276 || i.tm.operand_types[op].bitfield.acc))
252b5132 4277 {
34828aad 4278 if (intel_syntax
ca61edf2 4279 && i.tm.opcode_modifier.toqword
40fb9820 4280 && !i.types[0].bitfield.regxmm)
34828aad 4281 {
ca61edf2 4282 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4283 i.suffix = QWORD_MNEM_SUFFIX;
4284 }
4285 else
4286 {
4287 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4288 register_prefix, i.op[op].regs->reg_name,
4289 i.suffix);
4290 return 0;
4291 }
29b0f896
AM		 4292 }
4293 return 1;
4294}
252b5132 4295
29b0f896 4296static int
e3bb37b5 4297check_qword_reg (void)
29b0f896
AM		 4298{
4299 int op;
252b5132 4300
29b0f896
AM		 4301 for (op = i.operands; --op >= 0; )
4302 /* Reject eight bit registers, except where the template requires
4303 them. (eg. movzb) */
40fb9820
L		 4304 if (i.types[op].bitfield.reg8
4305 && (i.tm.operand_types[op].bitfield.reg16
4306 || i.tm.operand_types[op].bitfield.reg32
4307 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4308 {
a540244d
L		 4309 as_bad (_("`%s%s' not allowed with `%s%c'"),
4310 register_prefix,
29b0f896
AM		 4311 i.op[op].regs->reg_name,
4312 i.tm.name,
4313 i.suffix);
4314 return 0;
4315 }
4316 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4317 else if ((i.types[op].bitfield.reg16
4318 || i.types[op].bitfield.reg32)
4319 && (i.tm.operand_types[op].bitfield.reg32
4320 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4321 {
4322 /* Prohibit these changes in the 64bit mode, since the
4323 lowering is more complicated. */
34828aad 4324 if (intel_syntax
ca61edf2 4325 && i.tm.opcode_modifier.todword
40fb9820 4326 && !i.types[0].bitfield.regxmm)
34828aad 4327 {
ca61edf2 4328 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4329 i.suffix = LONG_MNEM_SUFFIX;
4330 }
4331 else
4332 {
4333 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4334 register_prefix, i.op[op].regs->reg_name,
4335 i.suffix);
4336 return 0;
4337 }
252b5132 4338 }
29b0f896
AM		 4339 return 1;
4340}
252b5132 4341
29b0f896 4342static int
e3bb37b5 4343check_word_reg (void)
29b0f896
AM		 4344{
4345 int op;
4346 for (op = i.operands; --op >= 0;)
4347 /* Reject eight bit registers, except where the template requires
4348 them. (eg. movzb) */
40fb9820
L		 4349 if (i.types[op].bitfield.reg8
4350 && (i.tm.operand_types[op].bitfield.reg16
4351 || i.tm.operand_types[op].bitfield.reg32
4352 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4353 {
a540244d
L		 4354 as_bad (_("`%s%s' not allowed with `%s%c'"),
4355 register_prefix,
29b0f896
AM		 4356 i.op[op].regs->reg_name,
4357 i.tm.name,
4358 i.suffix);
4359 return 0;
4360 }
4361 /* Warn if the e prefix on a general reg is present. */
4362 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4363 && i.types[op].bitfield.reg32
4364 && (i.tm.operand_types[op].bitfield.reg16
4365 || i.tm.operand_types[op].bitfield.acc))
252b5132 4366 {
29b0f896
AM		 4367 /* Prohibit these changes in the 64bit mode, since the
4368 lowering is more complicated. */
4369 if (flag_code == CODE_64BIT)
252b5132 4370 {
2ca3ace5
L		 4371 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4372 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4373 i.suffix);
4374 return 0;
252b5132 4375 }
29b0f896
AM		 4376 else
4377#if REGISTER_WARNINGS
a540244d
L		 4378 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4379 register_prefix,
29b0f896 4380 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4381 register_prefix,
29b0f896
AM		 4382 i.op[op].regs->reg_name,
4383 i.suffix);
4384#endif
4385 }
4386 return 1;
4387}
252b5132 4388
29b0f896 4389static int
40fb9820 4390update_imm (unsigned int j)
29b0f896 4391{
40fb9820
L		 4392 i386_operand_type overlap;
4393
c6fb90c8 4394 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4395 if ((overlap.bitfield.imm8
4396 || overlap.bitfield.imm8s
4397 || overlap.bitfield.imm16
4398 || overlap.bitfield.imm32
4399 || overlap.bitfield.imm32s
4400 || overlap.bitfield.imm64)
0dfbf9d7
L		 4401 && !operand_type_equal (&overlap, &imm8)
4402 && !operand_type_equal (&overlap, &imm8s)
4403 && !operand_type_equal (&overlap, &imm16)
4404 && !operand_type_equal (&overlap, &imm32)
4405 && !operand_type_equal (&overlap, &imm32s)
4406 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4407 {
4408 if (i.suffix)
4409 {
40fb9820
L		 4410 i386_operand_type temp;
4411
0dfbf9d7 4412 operand_type_set (&temp, 0);
40fb9820
L		 4413 if (i.suffix == BYTE_MNEM_SUFFIX)
4414 {
4415 temp.bitfield.imm8 = overlap.bitfield.imm8;
4416 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4417 }
4418 else if (i.suffix == WORD_MNEM_SUFFIX)
4419 temp.bitfield.imm16 = overlap.bitfield.imm16;
4420 else if (i.suffix == QWORD_MNEM_SUFFIX)
4421 {
4422 temp.bitfield.imm64 = overlap.bitfield.imm64;
4423 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4424 }
4425 else
4426 temp.bitfield.imm32 = overlap.bitfield.imm32;
4427 overlap = temp;
29b0f896 4428 }
0dfbf9d7
L		 4429 else if (operand_type_equal (&overlap, &imm16_32_32s)
4430 || operand_type_equal (&overlap, &imm16_32)
4431 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4432 {
40fb9820 4433 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4434 overlap = imm16;
40fb9820 4435 else
65da13b5 4436 overlap = imm32s;
29b0f896 4437 }
0dfbf9d7
L		 4438 if (!operand_type_equal (&overlap, &imm8)
4439 && !operand_type_equal (&overlap, &imm8s)
4440 && !operand_type_equal (&overlap, &imm16)
4441 && !operand_type_equal (&overlap, &imm32)
4442 && !operand_type_equal (&overlap, &imm32s)
4443 && !operand_type_equal (&overlap, &imm64))
29b0f896 4444 {
4eed87de
AM		 4445 as_bad (_("no instruction mnemonic suffix given; "
4446 "can't determine immediate size"));
29b0f896
AM		 4447 return 0;
4448 }
4449 }
40fb9820 4450 i.types[j] = overlap;
29b0f896 4451
40fb9820
L		 4452 return 1;
4453}
4454
4455static int
4456finalize_imm (void)
4457{
4458 unsigned int j;
29b0f896 4459
40fb9820
L		 4460 for (j = 0; j < 2; j++)
4461 if (update_imm (j) == 0)
4462 return 0;
4463
c6fb90c8 4464 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4465 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4466
4467 return 1;
4468}
4469
85f10a01
MM		 4470static void
4471process_drex (void)
4472{
5dd15031
JJ		 4473 i.drex.modrm_reg = 0;
4474 i.drex.modrm_regmem = 0;
85f10a01
MM		 4475
4476 /* SSE5 4 operand instructions must have the destination the same as
4477 one of the inputs. Figure out the destination register and cache
4478 it away in the drex field, and remember which fields to use for
4479 the modrm byte. */
4480 if (i.tm.opcode_modifier.drex
4481 && i.tm.opcode_modifier.drexv
4482 && i.operands == 4)
4483 {
4484 i.tm.extension_opcode = None;
4485
4486 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4487 if (i.types[0].bitfield.regxmm != 0
4488 && i.types[1].bitfield.regxmm != 0
4489 && i.types[2].bitfield.regxmm != 0
4490 && i.types[3].bitfield.regxmm != 0
4491 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4492 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4493 {
4494 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4495 operand_type_set (&i.types[0], 0);
4496 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4497 i.reg_operands -= 2;
4498
4499 /* There are two different ways to encode a 4 operand
4500 instruction with all registers that uses OC1 set to
4501 0 or 1. Favor setting OC1 to 0 since this mimics the
4502 actions of other SSE5 assemblers. Use modrm encoding 2
4503 for register/register. Include the high order bit that
4504 is normally stored in the REX byte in the register
4505 field. */
4506 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4507 i.drex.modrm_reg = 2;
4508 i.drex.modrm_regmem = 1;
4509 i.drex.reg = (i.op[3].regs->reg_num
4510 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4511 }
4512
4513 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4514 else if (i.types[0].bitfield.regxmm != 0
4515 && i.types[1].bitfield.regxmm != 0
4516 && (i.types[2].bitfield.regxmm
4517 || operand_type_check (i.types[2], anymem))
4518 && i.types[3].bitfield.regxmm != 0
4519 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4520 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4521 {
4522 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4523 operand_type_set (&i.types[0], 0);
4524 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4525 i.reg_operands -= 2;
4526
4527 /* Specify the modrm encoding for memory addressing. Include
4528 the high order bit that is normally stored in the REX byte
4529 in the register field. */
4530 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4531 i.drex.modrm_reg = 1;
4532 i.drex.modrm_regmem = 2;
4533 i.drex.reg = (i.op[3].regs->reg_num
4534 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4535 }
4536
4537 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4538 else if (i.types[0].bitfield.regxmm != 0
4539 && operand_type_check (i.types[1], anymem) != 0
4540 && i.types[2].bitfield.regxmm != 0
4541 && i.types[3].bitfield.regxmm != 0
4542 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4543 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4544 {
4545 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4546 operand_type_set (&i.types[0], 0);
4547 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4548 i.reg_operands -= 2;
4549
4550 /* Specify the modrm encoding for memory addressing. Include
4551 the high order bit that is normally stored in the REX byte
4552 in the register field. */
4553 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4554 i.drex.modrm_reg = 2;
4555 i.drex.modrm_regmem = 1;
4556 i.drex.reg = (i.op[3].regs->reg_num
4557 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4558 }
4559
4560 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4561 else if (i.types[0].bitfield.regxmm != 0
4562 && i.types[1].bitfield.regxmm != 0
4563 && i.types[2].bitfield.regxmm != 0
4564 && i.types[3].bitfield.regxmm != 0
4565 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4566 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4567 {
4568 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4569 operand_type_set (&i.types[2], 0);
4570 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4571 i.reg_operands -= 2;
4572
4573 /* There are two different ways to encode a 4 operand
4574 instruction with all registers that uses OC1 set to
4575 0 or 1. Favor setting OC1 to 0 since this mimics the
4576 actions of other SSE5 assemblers. Use modrm encoding
4577 2 for register/register. Include the high order bit that
4578 is normally stored in the REX byte in the register
4579 field. */
4580 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4581 i.drex.modrm_reg = 1;
4582 i.drex.modrm_regmem = 0;
4583
4584 /* Remember the register, including the upper bits */
4585 i.drex.reg = (i.op[3].regs->reg_num
4586 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4587 }
4588
4589 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4590 else if (i.types[0].bitfield.regxmm != 0
4591 && (i.types[1].bitfield.regxmm
4592 || operand_type_check (i.types[1], anymem))
4593 && i.types[2].bitfield.regxmm != 0
4594 && i.types[3].bitfield.regxmm != 0
4595 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4596 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4597 {
4598 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4599 operand_type_set (&i.types[2], 0);
4600 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4601 i.reg_operands -= 2;
4602
4603 /* Specify the modrm encoding and remember the register
4604 including the bits normally stored in the REX byte. */
4605 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4606 i.drex.modrm_reg = 0;
4607 i.drex.modrm_regmem = 1;
4608 i.drex.reg = (i.op[3].regs->reg_num
4609 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4610 }
4611
4612 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4613 else if (operand_type_check (i.types[0], anymem) != 0
4614 && i.types[1].bitfield.regxmm != 0
4615 && i.types[2].bitfield.regxmm != 0
4616 && i.types[3].bitfield.regxmm != 0
4617 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4618 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4619 {
4620 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4621 operand_type_set (&i.types[2], 0);
4622 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4623 i.reg_operands -= 2;
4624
4625 /* Specify the modrm encoding and remember the register
4626 including the bits normally stored in the REX byte. */
4627 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4628 i.drex.modrm_reg = 1;
4629 i.drex.modrm_regmem = 0;
4630 i.drex.reg = (i.op[3].regs->reg_num
4631 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4632 }
4633
4634 else
4635 as_bad (_("Incorrect operands for the '%s' instruction"),
4636 i.tm.name);
4637 }
4638
4639 /* SSE5 instructions with the DREX byte where the only memory operand
4640 is in the 2nd argument, and the first and last xmm register must
4641 match, and is encoded in the DREX byte. */
4642 else if (i.tm.opcode_modifier.drex
4643 && !i.tm.opcode_modifier.drexv
4644 && i.operands == 4)
4645 {
4646 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4647 if (i.types[0].bitfield.regxmm != 0
4648 && (i.types[1].bitfield.regxmm
4649 || operand_type_check(i.types[1], anymem))
4650 && i.types[2].bitfield.regxmm != 0
4651 && i.types[3].bitfield.regxmm != 0
4652 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4653 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4654 {
4655 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4656 operand_type_set (&i.types[0], 0);
4657 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4658 i.reg_operands -= 2;
4659
4660 /* Specify the modrm encoding and remember the register
4661 including the high bit normally stored in the REX
4662 byte. */
4663 i.drex.modrm_reg = 2;
4664 i.drex.modrm_regmem = 1;
4665 i.drex.reg = (i.op[3].regs->reg_num
4666 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4667 }
4668
4669 else
4670 as_bad (_("Incorrect operands for the '%s' instruction"),
4671 i.tm.name);
4672 }
4673
4674 /* SSE5 3 operand instructions that the result is a register, being
4675 either operand can be a memory operand, using OC0 to note which
4676 one is the memory. */
4677 else if (i.tm.opcode_modifier.drex
4678 && i.tm.opcode_modifier.drexv
4679 && i.operands == 3)
4680 {
4681 i.tm.extension_opcode = None;
4682
4683 /* Case 1: 3 operand insn, src1 = register. */
4684 if (i.types[0].bitfield.regxmm != 0
4685 && i.types[1].bitfield.regxmm != 0
4686 && i.types[2].bitfield.regxmm != 0)
4687 {
4688 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4689 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4690 i.reg_operands--;
4691
4692 /* Specify the modrm encoding and remember the register
4693 including the high bit normally stored in the REX byte. */
4694 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4695 i.drex.modrm_reg = 1;
4696 i.drex.modrm_regmem = 0;
4697 i.drex.reg = (i.op[2].regs->reg_num
4698 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4699 }
4700
4701 /* Case 2: 3 operand insn, src1 = memory. */
4702 else if (operand_type_check (i.types[0], anymem) != 0
4703 && i.types[1].bitfield.regxmm != 0
4704 && i.types[2].bitfield.regxmm != 0)
4705 {
4706 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4707 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4708 i.reg_operands--;
4709
4710 /* Specify the modrm encoding and remember the register
4711 including the high bit normally stored in the REX
4712 byte. */
4713 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4714 i.drex.modrm_reg = 1;
4715 i.drex.modrm_regmem = 0;
4716 i.drex.reg = (i.op[2].regs->reg_num
4717 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4718 }
4719
4720 /* Case 3: 3 operand insn, src2 = memory. */
4721 else if (i.types[0].bitfield.regxmm != 0
4722 && operand_type_check (i.types[1], anymem) != 0
4723 && i.types[2].bitfield.regxmm != 0)
4724 {
4725 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4726 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4727 i.reg_operands--;
4728
4729 /* Specify the modrm encoding and remember the register
4730 including the high bit normally stored in the REX byte. */
4731 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4732 i.drex.modrm_reg = 0;
4733 i.drex.modrm_regmem = 1;
4734 i.drex.reg = (i.op[2].regs->reg_num
4735 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4736 }
4737
4738 else
4739 as_bad (_("Incorrect operands for the '%s' instruction"),
4740 i.tm.name);
4741 }
4742
4743 /* SSE5 4 operand instructions that are the comparison instructions
4744 where the first operand is the immediate value of the comparison
4745 to be done. */
4746 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4747 {
4748 /* Case 1: 4 operand insn, src1 = reg/memory. */
4749 if (operand_type_check (i.types[0], imm) != 0
4750 && (i.types[1].bitfield.regxmm
4751 || operand_type_check (i.types[1], anymem))
4752 && i.types[2].bitfield.regxmm != 0
4753 && i.types[3].bitfield.regxmm != 0)
4754 {
4755 /* clear the arguments that are stored in drex */
0dfbf9d7 4756 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4757 i.reg_operands--;
4758
4759 /* Specify the modrm encoding and remember the register
4760 including the high bit normally stored in the REX byte. */
4761 i.drex.modrm_reg = 2;
4762 i.drex.modrm_regmem = 1;
4763 i.drex.reg = (i.op[3].regs->reg_num
4764 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4765 }
4766
4767 /* Case 2: 3 operand insn with ImmExt that places the
4768 opcode_extension as an immediate argument. This is used for
4769 all of the varients of comparison that supplies the appropriate
4770 value as part of the instruction. */
4771 else if ((i.types[0].bitfield.regxmm
4772 || operand_type_check (i.types[0], anymem))
4773 && i.types[1].bitfield.regxmm != 0
4774 && i.types[2].bitfield.regxmm != 0
4775 && operand_type_check (i.types[3], imm) != 0)
4776 {
4777 /* clear the arguments that are stored in drex */
0dfbf9d7 4778 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4779 i.reg_operands--;
4780
4781 /* Specify the modrm encoding and remember the register
4782 including the high bit normally stored in the REX byte. */
4783 i.drex.modrm_reg = 1;
4784 i.drex.modrm_regmem = 0;
4785 i.drex.reg = (i.op[2].regs->reg_num
4786 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4787 }
4788
4789 else
4790 as_bad (_("Incorrect operands for the '%s' instruction"),
4791 i.tm.name);
4792 }
4793
4794 else if (i.tm.opcode_modifier.drex
4795 || i.tm.opcode_modifier.drexv
4796 || i.tm.opcode_modifier.drexc)
4797 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4798}
4799
c0f3af97
L		 4800static int
4801bad_implicit_operand (int xmm)
4802{
4803 const char *reg = xmm ? "xmm0" : "ymm0";
4804 if (intel_syntax)
4805 as_bad (_("the last operand of `%s' must be `%s%s'"),
4806 i.tm.name, register_prefix, reg);
4807 else
4808 as_bad (_("the first operand of `%s' must be `%s%s'"),
4809 i.tm.name, register_prefix, reg);
4810 return 0;
4811}
4812
29b0f896 4813static int
e3bb37b5 4814process_operands (void)
29b0f896
AM		 4815{
4816 /* Default segment register this instruction will use for memory
4817 accesses. 0 means unknown. This is only for optimizing out
4818 unnecessary segment overrides. */
4819 const seg_entry *default_seg = 0;
4820
85f10a01
MM		 4821 /* Handle all of the DREX munging that SSE5 needs. */
4822 if (i.tm.opcode_modifier.drex
4823 || i.tm.opcode_modifier.drexv
4824 || i.tm.opcode_modifier.drexc)
4825 process_drex ();
4826
c0f3af97
L		 4827 if (i.tm.opcode_modifier.sse2avx
4828 && (i.tm.opcode_modifier.vexnds
4829 || i.tm.opcode_modifier.vexndd))
29b0f896 4830 {
c0f3af97
L		 4831 unsigned int dup = i.operands;
4832 unsigned int dest = dup - 1;
9fcfb3d7
L		 4833 unsigned int j;
4834
c0f3af97 4835 /* The destination must be an xmm register. */
0dfbf9d7 4836 assert (i.reg_operands
c0f3af97
L		 4837 && MAX_OPERANDS > dup
4838 && operand_type_equal (&i.types[dest], &regxmm));
4839
4840 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4841 {
c0f3af97
L		 4842 /* The first operand is implicit and must be xmm0. */
4843 assert (operand_type_equal (&i.types[0], &regxmm));
4844 if (i.op[0].regs->reg_num != 0)
4845 return bad_implicit_operand (1);
4846
4847 if (i.tm.opcode_modifier.vex3sources)
4848 {
4849 /* Keep xmm0 for instructions with VEX prefix and 3
4850 sources. */
4851 goto duplicate;
4852 }
e2ec9d29 4853 else
c0f3af97
L		 4854 {
4855 /* We remove the first xmm0 and keep the number of
4856 operands unchanged, which in fact duplicates the
4857 destination. */
4858 for (j = 1; j < i.operands; j++)
4859 {
4860 i.op[j - 1] = i.op[j];
4861 i.types[j - 1] = i.types[j];
4862 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4863 }
4864 }
4865 }
4866 else if (i.tm.opcode_modifier.implicit1stxmm0)
4867 {
4868 assert ((MAX_OPERANDS - 1) > dup
4869 && i.tm.opcode_modifier.vex3sources);
4870
4871 /* Add the implicit xmm0 for instructions with VEX prefix
4872 and 3 sources. */
4873 for (j = i.operands; j > 0; j--)
4874 {
4875 i.op[j] = i.op[j - 1];
4876 i.types[j] = i.types[j - 1];
4877 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4878 }
4879 i.op[0].regs
4880 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4881 i.types[0] = regxmm;
4882 i.tm.operand_types[0] = regxmm;
4883
4884 i.operands += 2;
4885 i.reg_operands += 2;
4886 i.tm.operands += 2;
4887
4888 dup++;
4889 dest++;
4890 i.op[dup] = i.op[dest];
4891 i.types[dup] = i.types[dest];
4892 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4893 }
c0f3af97
L		 4894 else
4895 {
4896duplicate:
4897 i.operands++;
4898 i.reg_operands++;
4899 i.tm.operands++;
4900
4901 i.op[dup] = i.op[dest];
4902 i.types[dup] = i.types[dest];
4903 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4904 }
4905
4906 if (i.tm.opcode_modifier.immext)
4907 process_immext ();
4908 }
4909 else if (i.tm.opcode_modifier.firstxmm0)
4910 {
4911 unsigned int j;
4912
4913 /* The first operand is implicit and must be xmm0/ymm0. */
4914 assert (i.reg_operands
4915 && (operand_type_equal (&i.types[0], &regxmm)
4916 || operand_type_equal (&i.types[0], &regymm)));
4917 if (i.op[0].regs->reg_num != 0)
4918 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4919
4920 for (j = 1; j < i.operands; j++)
4921 {
4922 i.op[j - 1] = i.op[j];
4923 i.types[j - 1] = i.types[j];
4924
4925 /* We need to adjust fields in i.tm since they are used by
4926 build_modrm_byte. */
4927 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4928 }
4929
e2ec9d29
L		 4930 i.operands--;
4931 i.reg_operands--;
e2ec9d29
L		 4932 i.tm.operands--;
4933 }
4934 else if (i.tm.opcode_modifier.regkludge)
4935 {
4936 /* The imul $imm, %reg instruction is converted into
4937 imul $imm, %reg, %reg, and the clr %reg instruction
4938 is converted into xor %reg, %reg. */
4939
4940 unsigned int first_reg_op;
4941
4942 if (operand_type_check (i.types[0], reg))
4943 first_reg_op = 0;
4944 else
4945 first_reg_op = 1;
4946 /* Pretend we saw the extra register operand. */
4947 assert (i.reg_operands == 1
4948 && i.op[first_reg_op + 1].regs == 0);
4949 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4950 i.types[first_reg_op + 1] = i.types[first_reg_op];
4951 i.operands++;
4952 i.reg_operands++;
29b0f896
AM		 4953 }
4954
40fb9820 4955 if (i.tm.opcode_modifier.shortform)
29b0f896 4956 {
40fb9820
L		 4957 if (i.types[0].bitfield.sreg2
4958 || i.types[0].bitfield.sreg3)
29b0f896 4959 {
4eed87de
AM		 4960 if (i.tm.base_opcode == POP_SEG_SHORT
4961 && i.op[0].regs->reg_num == 1)
29b0f896 4962 {
a87af027 4963 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 4964 return 0;
29b0f896 4965 }
4eed87de
AM		 4966 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4967 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4968 i.rex |= REX_B;
4eed87de
AM		 4969 }
4970 else
4971 {
85f10a01
MM		 4972 /* The register or float register operand is in operand
4973 0 or 1. */
40fb9820
L		 4974 unsigned int op;
4975
4976 if (i.types[0].bitfield.floatreg
4977 || operand_type_check (i.types[0], reg))
4978 op = 0;
4979 else
4980 op = 1;
4eed87de
AM		 4981 /* Register goes in low 3 bits of opcode. */
4982 i.tm.base_opcode |= i.op[op].regs->reg_num;
4983 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4984 i.rex |= REX_B;
40fb9820 4985 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4986 {
4eed87de
AM		 4987 /* Warn about some common errors, but press on regardless.
4988 The first case can be generated by gcc (<= 2.8.1). */
4989 if (i.operands == 2)
4990 {
4991 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4992 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4993 register_prefix, i.op[1].regs->reg_name,
4994 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4995 }
4996 else
4997 {
4998 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4999 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5000 register_prefix, i.op[0].regs->reg_name);
4eed87de 5001 }
29b0f896
AM		 5002 }
5003 }
5004 }
40fb9820 5005 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5006 {
5007 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5008 must be put into the modrm byte). Now, we make the modrm and
5009 index base bytes based on all the info we've collected. */
29b0f896
AM		 5010
5011 default_seg = build_modrm_byte ();
5012 }
8a2ed489 5013 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5014 {
5015 default_seg = &ds;
5016 }
40fb9820 5017 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5018 {
5019 /* For the string instructions that allow a segment override
5020 on one of their operands, the default segment is ds. */
5021 default_seg = &ds;
5022 }
5023
75178d9d
L		 5024 if (i.tm.base_opcode == 0x8d /* lea */
5025 && i.seg[0]
5026 && !quiet_warnings)
30123838 5027 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5028
5029 /* If a segment was explicitly specified, and the specified segment
5030 is not the default, use an opcode prefix to select it. If we
5031 never figured out what the default segment is, then default_seg
5032 will be zero at this point, and the specified segment prefix will
5033 always be used. */
29b0f896
AM		 5034 if ((i.seg[0]) && (i.seg[0] != default_seg))
5035 {
5036 if (!add_prefix (i.seg[0]->seg_prefix))
5037 return 0;
5038 }
5039 return 1;
5040}
5041
5042static const seg_entry *
e3bb37b5 5043build_modrm_byte (void)
29b0f896
AM		 5044{
5045 const seg_entry *default_seg = 0;
c0f3af97
L		 5046 unsigned int source, dest;
5047 int vex_3_sources;
5048
5049 /* The first operand of instructions with VEX prefix and 3 sources
5050 must be VEX_Imm4. */
5051 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5052 if (vex_3_sources)
5053 {
5054 unsigned int nds, reg;
5055
5056 if (i.tm.opcode_modifier.veximmext
5057 && i.tm.opcode_modifier.immext)
5058 {
5059 dest = i.operands - 2;
5060 assert (dest == 3);
5061 }
5062 else
5063 dest = i.operands - 1;
5064 nds = dest - 1;
5065
5066 /* There are 2 kinds of instructions:
dae39acc 5067 1. 5 operands: one immediate operand and 4 register
c0f3af97
L		 5068 operands or 3 register operands plus 1 memory operand.
5069 It must have VexNDS and VexW0 or VexW1. The destination
5070 must be either XMM or YMM register.
5071 2. 4 operands: 4 register operands or 3 register operands
5072 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5073 if (!((i.reg_operands == 4
5074 || (i.reg_operands == 3 && i.mem_operands == 1))
5075 && i.tm.opcode_modifier.vexnds
5076 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5077 || operand_type_equal (&i.tm.operand_types[dest], &regymm))
c0f3af97
L		 5078 && ((dest == 4
5079 && i.imm_operands == 1
5080 && i.types[0].bitfield.vex_imm4
5081 && (i.tm.opcode_modifier.vexw0
5082 || i.tm.opcode_modifier.vexw1))
5083 || (dest == 3
5084 && (i.imm_operands == 0
5085 || (i.imm_operands == 1
5086 && i.tm.opcode_modifier.immext))
5087 && i.tm.opcode_modifier.veximmext))))
5088 abort ();
5089
c0f3af97
L		 5090 if (i.imm_operands == 0)
5091 {
5092 /* When there is no immediate operand, generate an 8bit
5093 immediate operand to encode the first operand. */
5094 expressionS *exp = &im_expressions[i.imm_operands++];
5095 i.op[i.operands].imms = exp;
5096 i.types[i.operands] = imm8;
5097 i.operands++;
5098 /* If VexW1 is set, the first operand is the source and
5099 the second operand is encoded in the immediate operand. */
5100 if (i.tm.opcode_modifier.vexw1)
5101 {
5102 source = 0;
5103 reg = 1;
5104 }
5105 else
5106 {
5107 source = 1;
5108 reg = 0;
5109 }
dae39acc
L		 5110
5111 /* FMA swaps REG and NDS. */
5112 if (i.tm.cpu_flags.bitfield.cpufma)
5113 {
5114 unsigned int tmp;
5115 tmp = reg;
5116 reg = nds;
5117 nds = tmp;
5118 }
5119
c0f3af97
L		 5120 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5121 || operand_type_equal (&i.tm.operand_types[reg],
5122 &regymm));
5123 exp->X_op = O_constant;
5124 exp->X_add_number
5125 = ((i.op[reg].regs->reg_num
5126 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5127 }
5128 else
5129 {
5130 unsigned int imm;
5131
5132 if (i.tm.opcode_modifier.vexw0)
5133 {
5134 /* If VexW0 is set, the third operand is the source and
5135 the second operand is encoded in the immediate
5136 operand. */
5137 source = 2;
5138 reg = 1;
5139 }
5140 else
5141 {
5142 /* VexW1 is set, the second operand is the source and
5143 the third operand is encoded in the immediate
5144 operand. */
5145 source = 1;
5146 reg = 2;
5147 }
5148
5149 if (i.tm.opcode_modifier.immext)
5150 {
5151 /* When ImmExt is set, the immdiate byte is the last
5152 operand. */
5153 imm = i.operands - 1;
5154 source--;
5155 reg--;
5156 }
5157 else
5158 {
5159 imm = 0;
5160
5161 /* Turn on Imm8 so that output_imm will generate it. */
5162 i.types[imm].bitfield.imm8 = 1;
5163 }
5164
5165 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5166 || operand_type_equal (&i.tm.operand_types[reg],
5167 &regymm));
5168 i.op[imm].imms->X_add_number
5169 |= ((i.op[reg].regs->reg_num
5170 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5171 }
dae39acc
L		 5172
5173 assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5174 || operand_type_equal (&i.tm.operand_types[nds], &regymm));
5175 i.vex.register_specifier = i.op[nds].regs;
5176
c0f3af97
L		 5177 }
5178 else
5179 source = dest = 0;
29b0f896 5180
85f10a01
MM		 5181 /* SSE5 4 operand instructions are encoded in such a way that one of
5182 the inputs must match the destination register. Process_drex hides
5183 the 3rd argument in the drex field, so that by the time we get
5184 here, it looks to GAS as if this is a 2 operand instruction. */
5185 if ((i.tm.opcode_modifier.drex
5186 || i.tm.opcode_modifier.drexv
b5016f89 5187 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5188 && i.reg_operands == 2)
5189 {
5190 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5191 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5192
5193 i.rm.reg = reg->reg_num;
5194 i.rm.regmem = regmem->reg_num;
5195 i.rm.mode = 3;
5196 if ((reg->reg_flags & RegRex) != 0)
5197 i.rex |= REX_R;
5198 if ((regmem->reg_flags & RegRex) != 0)
5199 i.rex |= REX_B;
5200 }
5201
29b0f896 5202 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5203 implicit registers do not count. If there are 3 register
5204 operands, it must be a instruction with VexNDS. For a
5205 instruction with VexNDD, the destination register is encoded
5206 in VEX prefix. If there are 4 register operands, it must be
5207 a instruction with VEX prefix and 3 sources. */
5208 else if (i.mem_operands == 0
5209 && ((i.reg_operands == 2
5210 && !i.tm.opcode_modifier.vexndd)
5211 || (i.reg_operands == 3
5212 && i.tm.opcode_modifier.vexnds)
5213 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5214 {
cab737b9
L		 5215 switch (i.operands)
5216 {
5217 case 2:
5218 source = 0;
5219 break;
5220 case 3:
c81128dc
L		 5221 /* When there are 3 operands, one of them may be immediate,
5222 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5223 the first operand must be shift count register (cl) or it
5224 is an instruction with VexNDS. */
c81128dc
L		 5225 assert (i.imm_operands == 1
5226 || (i.imm_operands == 0
c0f3af97
L		 5227 && (i.tm.opcode_modifier.vexnds
5228 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5229 if (operand_type_check (i.types[0], imm)
5230 || i.types[0].bitfield.shiftcount)
5231 source = 1;
5232 else
5233 source = 0;
cab737b9
L		 5234 break;
5235 case 4:
368d64cc
L		 5236 /* When there are 4 operands, the first two must be 8bit
5237 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5238 one.
5239
5240 For instructions with VexNDS, if the first operand
5241 an imm8, the source operand is the 2nd one. If the last
5242 operand is imm8, the source operand is the first one. */
5243 assert ((i.imm_operands == 2
5244 && i.types[0].bitfield.imm8
5245 && i.types[1].bitfield.imm8)
5246 || (i.tm.opcode_modifier.vexnds
5247 && i.imm_operands == 1
5248 && (i.types[0].bitfield.imm8
5249 || i.types[i.operands - 1].bitfield.imm8)));
5250 if (i.tm.opcode_modifier.vexnds)
5251 {
5252 if (i.types[0].bitfield.imm8)
5253 source = 1;
5254 else
5255 source = 0;
5256 }
5257 else
5258 source = 2;
5259 break;
5260 case 5:
cab737b9
L		 5261 break;
5262 default:
5263 abort ();
5264 }
5265
c0f3af97
L		 5266 if (!vex_3_sources)
5267 {
5268 dest = source + 1;
5269
5270 if (i.tm.opcode_modifier.vexnds)
5271 {
5272 /* For instructions with VexNDS, the register-only
5273 source operand must be XMM or YMM register. It is
5274 encoded in VEX prefix. */
5275 if ((dest + 1) >= i.operands
5276 || (!operand_type_equal (&i.tm.operand_types[dest],
5277 &regxmm)
5278 && !operand_type_equal (&i.tm.operand_types[dest],
5279 &regymm)))
5280 abort ();
5281 i.vex.register_specifier = i.op[dest].regs;
5282 dest++;
5283 }
5284 }
29b0f896
AM		 5285
5286 i.rm.mode = 3;
5287 /* One of the register operands will be encoded in the i.tm.reg
5288 field, the other in the combined i.tm.mode and i.tm.regmem
5289 fields. If no form of this instruction supports a memory
5290 destination operand, then we assume the source operand may
5291 sometimes be a memory operand and so we need to store the
5292 destination in the i.rm.reg field. */
40fb9820
L		 5293 if (!i.tm.operand_types[dest].bitfield.regmem
5294 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5295 {
5296 i.rm.reg = i.op[dest].regs->reg_num;
5297 i.rm.regmem = i.op[source].regs->reg_num;
5298 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5299 i.rex |= REX_R;
29b0f896 5300 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5301 i.rex |= REX_B;
29b0f896
AM		 5302 }
5303 else
5304 {
5305 i.rm.reg = i.op[source].regs->reg_num;
5306 i.rm.regmem = i.op[dest].regs->reg_num;
5307 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5308 i.rex |= REX_B;
29b0f896 5309 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5310 i.rex |= REX_R;
29b0f896 5311 }
161a04f6 5312 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5313 {
40fb9820
L		 5314 if (!i.types[0].bitfield.control
5315 && !i.types[1].bitfield.control)
c4a530c5 5316 abort ();
161a04f6 5317 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5318 add_prefix (LOCK_PREFIX_OPCODE);
5319 }
29b0f896
AM		 5320 }
5321 else
5322 { /* If it's not 2 reg operands... */
c0f3af97
L		 5323 unsigned int mem;
5324
29b0f896
AM		 5325 if (i.mem_operands)
5326 {
5327 unsigned int fake_zero_displacement = 0;
99018f42 5328 unsigned int op;
4eed87de 5329
85f10a01
MM		 5330 /* This has been precalculated for SSE5 instructions
5331 that have a DREX field earlier in process_drex. */
b5016f89
L		 5332 if (i.tm.opcode_modifier.drex
5333 || i.tm.opcode_modifier.drexv
5334 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5335 op = i.drex.modrm_regmem;
5336 else
5337 {
c0209578
L		 5338 for (op = 0; op < i.operands; op++)
5339 if (operand_type_check (i.types[op], anymem))
5340 break;
5341 assert (op < i.operands);
85f10a01 5342 }
29b0f896
AM		 5343
5344 default_seg = &ds;
5345
5346 if (i.base_reg == 0)
5347 {
5348 i.rm.mode = 0;
5349 if (!i.disp_operands)
5350 fake_zero_displacement = 1;
5351 if (i.index_reg == 0)
5352 {
5353 /* Operand is just <disp> */
20f0a1fc 5354 if (flag_code == CODE_64BIT)
29b0f896
AM		 5355 {
5356 /* 64bit mode overwrites the 32bit absolute
5357 addressing by RIP relative addressing and
5358 absolute addressing is encoded by one of the
5359 redundant SIB forms. */
5360 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5361 i.sib.base = NO_BASE_REGISTER;
5362 i.sib.index = NO_INDEX_REGISTER;
fc225355 5363 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5364 ? disp32s : disp32);
20f0a1fc 5365 }
fc225355
L		 5366 else if ((flag_code == CODE_16BIT)
5367 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5368 {
5369 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5370 i.types[op] = disp16;
20f0a1fc
NC		 5371 }
5372 else
5373 {
5374 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5375 i.types[op] = disp32;
29b0f896
AM		 5376 }
5377 }
5378 else /* !i.base_reg && i.index_reg */
5379 {
db51cc60
L		 5380 if (i.index_reg->reg_num == RegEiz
5381 || i.index_reg->reg_num == RegRiz)
5382 i.sib.index = NO_INDEX_REGISTER;
5383 else
5384 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5385 i.sib.base = NO_BASE_REGISTER;
5386 i.sib.scale = i.log2_scale_factor;
5387 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5388 i.types[op].bitfield.disp8 = 0;
5389 i.types[op].bitfield.disp16 = 0;
5390 i.types[op].bitfield.disp64 = 0;
29b0f896 5391 if (flag_code != CODE_64BIT)
40fb9820
L		 5392 {
5393 /* Must be 32 bit */
5394 i.types[op].bitfield.disp32 = 1;
5395 i.types[op].bitfield.disp32s = 0;
5396 }
29b0f896 5397 else
40fb9820
L		 5398 {
5399 i.types[op].bitfield.disp32 = 0;
5400 i.types[op].bitfield.disp32s = 1;
5401 }
29b0f896 5402 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5403 i.rex |= REX_X;
29b0f896
AM		 5404 }
5405 }
5406 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5407 else if (i.base_reg->reg_num == RegRip ||
5408 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5409 {
5410 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5411 i.types[op].bitfield.disp8 = 0;
5412 i.types[op].bitfield.disp16 = 0;
5413 i.types[op].bitfield.disp32 = 0;
5414 i.types[op].bitfield.disp32s = 1;
5415 i.types[op].bitfield.disp64 = 0;
71903a11 5416 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5417 if (! i.disp_operands)
5418 fake_zero_displacement = 1;
29b0f896 5419 }
40fb9820 5420 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5421 {
5422 switch (i.base_reg->reg_num)
5423 {
5424 case 3: /* (%bx) */
5425 if (i.index_reg == 0)
5426 i.rm.regmem = 7;
5427 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5428 i.rm.regmem = i.index_reg->reg_num - 6;
5429 break;
5430 case 5: /* (%bp) */
5431 default_seg = &ss;
5432 if (i.index_reg == 0)
5433 {
5434 i.rm.regmem = 6;
40fb9820 5435 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5436 {
5437 /* fake (%bp) into 0(%bp) */
40fb9820 5438 i.types[op].bitfield.disp8 = 1;
252b5132 5439 fake_zero_displacement = 1;
29b0f896
AM		 5440 }
5441 }
5442 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5443 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5444 break;
5445 default: /* (%si) -> 4 or (%di) -> 5 */
5446 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5447 }
5448 i.rm.mode = mode_from_disp_size (i.types[op]);
5449 }
5450 else /* i.base_reg and 32/64 bit mode */
5451 {
5452 if (flag_code == CODE_64BIT
40fb9820
L		 5453 && operand_type_check (i.types[op], disp))
5454 {
5455 i386_operand_type temp;
0dfbf9d7 5456 operand_type_set (&temp, 0);
40fb9820
L		 5457 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5458 i.types[op] = temp;
5459 if (i.prefix[ADDR_PREFIX] == 0)
5460 i.types[op].bitfield.disp32s = 1;
5461 else
5462 i.types[op].bitfield.disp32 = 1;
5463 }
20f0a1fc 5464
29b0f896
AM		 5465 i.rm.regmem = i.base_reg->reg_num;
5466 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5467 i.rex |= REX_B;
29b0f896
AM		 5468 i.sib.base = i.base_reg->reg_num;
5469 /* x86-64 ignores REX prefix bit here to avoid decoder
5470 complications. */
5471 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5472 {
5473 default_seg = &ss;
5474 if (i.disp_operands == 0)
5475 {
5476 fake_zero_displacement = 1;
40fb9820 5477 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5478 }
5479 }
5480 else if (i.base_reg->reg_num == ESP_REG_NUM)
5481 {
5482 default_seg = &ss;
5483 }
5484 i.sib.scale = i.log2_scale_factor;
5485 if (i.index_reg == 0)
5486 {
5487 /* <disp>(%esp) becomes two byte modrm with no index
5488 register. We've already stored the code for esp
5489 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5490 Any base register besides %esp will not use the
5491 extra modrm byte. */
5492 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5493 }
5494 else
5495 {
db51cc60
L		 5496 if (i.index_reg->reg_num == RegEiz
5497 || i.index_reg->reg_num == RegRiz)
5498 i.sib.index = NO_INDEX_REGISTER;
5499 else
5500 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5501 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5502 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5503 i.rex |= REX_X;
29b0f896 5504 }
67a4f2b7
AO		 5505
5506 if (i.disp_operands
5507 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5508 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5509 i.rm.mode = 0;
5510 else
5511 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5512 }
252b5132 5513
29b0f896
AM		 5514 if (fake_zero_displacement)
5515 {
5516 /* Fakes a zero displacement assuming that i.types[op]
5517 holds the correct displacement size. */
5518 expressionS *exp;
5519
5520 assert (i.op[op].disps == 0);
5521 exp = &disp_expressions[i.disp_operands++];
5522 i.op[op].disps = exp;
5523 exp->X_op = O_constant;
5524 exp->X_add_number = 0;
5525 exp->X_add_symbol = (symbolS *) 0;
5526 exp->X_op_symbol = (symbolS *) 0;
5527 }
c0f3af97
L		 5528
5529 mem = op;
29b0f896 5530 }
c0f3af97
L		 5531 else
5532 mem = ~0;
252b5132 5533
29b0f896
AM		 5534 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5535 (if any) based on i.tm.extension_opcode. Again, we must be
5536 careful to make sure that segment/control/debug/test/MMX
5537 registers are coded into the i.rm.reg field. */
5538 if (i.reg_operands)
5539 {
99018f42
L		 5540 unsigned int op;
5541
85f10a01
MM		 5542 /* This has been precalculated for SSE5 instructions
5543 that have a DREX field earlier in process_drex. */
b5016f89
L		 5544 if (i.tm.opcode_modifier.drex
5545 || i.tm.opcode_modifier.drexv
5546 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5547 {
5548 op = i.drex.modrm_reg;
5549 i.rm.reg = i.op[op].regs->reg_num;
5550 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5551 i.rex |= REX_R;
5552 }
5553 else
5554 {
c0f3af97
L		 5555 unsigned int vex_reg = ~0;
5556
c0209578
L		 5557 for (op = 0; op < i.operands; op++)
5558 if (i.types[op].bitfield.reg8
5559 || i.types[op].bitfield.reg16
5560 || i.types[op].bitfield.reg32
5561 || i.types[op].bitfield.reg64
5562 || i.types[op].bitfield.regmmx
5563 || i.types[op].bitfield.regxmm
c0f3af97 5564 || i.types[op].bitfield.regymm
c0209578
L		 5565 || i.types[op].bitfield.sreg2
5566 || i.types[op].bitfield.sreg3
5567 || i.types[op].bitfield.control
5568 || i.types[op].bitfield.debug
5569 || i.types[op].bitfield.test)
5570 break;
5571
c0f3af97
L		 5572 if (vex_3_sources)
5573 op = dest;
5574 else if (i.tm.opcode_modifier.vexnds)
5575 {
5576 /* For instructions with VexNDS, the register-only
5577 source operand is encoded in VEX prefix. */
5578 assert (mem != (unsigned int) ~0);
5579
5580 if (op > mem)
5581 {
5582 vex_reg = op++;
5583 assert (op < i.operands);
5584 }
5585 else
5586 {
5587 vex_reg = op + 1;
5588 assert (vex_reg < i.operands);
5589 }
5590 }
5591 else if (i.tm.opcode_modifier.vexndd)
5592 {
5593 /* For instructions with VexNDD, there should be
5594 no memory operand and the register destination
5595 is encoded in VEX prefix. */
5596 assert (i.mem_operands == 0
5597 && (op + 2) == i.operands);
5598 vex_reg = op + 1;
5599 }
5600 else
5601 assert (op < i.operands);
5602
5603 if (vex_reg != (unsigned int) ~0)
5604 {
5605 assert (i.reg_operands == 2);
5606
5607 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5608 & regxmm)
5609 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5610 &regymm))
5611 abort ();
5612 i.vex.register_specifier = i.op[vex_reg].regs;
5613 }
99018f42 5614
85f10a01
MM		 5615 /* If there is an extension opcode to put here, the
5616 register number must be put into the regmem field. */
c0209578
L		 5617 if (i.tm.extension_opcode != None)
5618 {
5619 i.rm.regmem = i.op[op].regs->reg_num;
5620 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5621 i.rex |= REX_B;
5622 }
5623 else
5624 {
5625 i.rm.reg = i.op[op].regs->reg_num;
5626 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5627 i.rex |= REX_R;
5628 }
85f10a01 5629 }
252b5132 5630
29b0f896
AM		 5631 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5632 must set it to 3 to indicate this is a register operand
5633 in the regmem field. */
5634 if (!i.mem_operands)
5635 i.rm.mode = 3;
5636 }
252b5132 5637
29b0f896 5638 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5639 if (i.tm.extension_opcode != None
5640 && !(i.tm.opcode_modifier.drex
5641 || i.tm.opcode_modifier.drexv
5642 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5643 i.rm.reg = i.tm.extension_opcode;
5644 }
5645 return default_seg;
5646}
252b5132 5647
29b0f896 5648static void
e3bb37b5 5649output_branch (void)
29b0f896
AM		 5650{
5651 char *p;
5652 int code16;
5653 int prefix;
5654 relax_substateT subtype;
5655 symbolS *sym;
5656 offsetT off;
5657
5658 code16 = 0;
5659 if (flag_code == CODE_16BIT)
5660 code16 = CODE16;
5661
5662 prefix = 0;
5663 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5664 {
29b0f896
AM		 5665 prefix = 1;
5666 i.prefixes -= 1;
5667 code16 ^= CODE16;
252b5132 5668 }
29b0f896
AM		 5669 /* Pentium4 branch hints. */
5670 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5671 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5672 {
29b0f896
AM		 5673 prefix++;
5674 i.prefixes--;
5675 }
5676 if (i.prefix[REX_PREFIX] != 0)
5677 {
5678 prefix++;
5679 i.prefixes--;
2f66722d
AM		 5680 }
5681
29b0f896
AM		 5682 if (i.prefixes != 0 && !intel_syntax)
5683 as_warn (_("skipping prefixes on this instruction"));
5684
5685 /* It's always a symbol; End frag & setup for relax.
5686 Make sure there is enough room in this frag for the largest
5687 instruction we may generate in md_convert_frag. This is 2
5688 bytes for the opcode and room for the prefix and largest
5689 displacement. */
5690 frag_grow (prefix + 2 + 4);
5691 /* Prefix and 1 opcode byte go in fr_fix. */
5692 p = frag_more (prefix + 1);
5693 if (i.prefix[DATA_PREFIX] != 0)
5694 *p++ = DATA_PREFIX_OPCODE;
5695 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5696 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5697 *p++ = i.prefix[SEG_PREFIX];
5698 if (i.prefix[REX_PREFIX] != 0)
5699 *p++ = i.prefix[REX_PREFIX];
5700 *p = i.tm.base_opcode;
5701
5702 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5703 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5704 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5705 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5706 else
5707 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5708 subtype |= code16;
3e73aa7c 5709
29b0f896
AM		 5710 sym = i.op[0].disps->X_add_symbol;
5711 off = i.op[0].disps->X_add_number;
3e73aa7c 5712
29b0f896
AM		 5713 if (i.op[0].disps->X_op != O_constant
5714 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5715 {
29b0f896
AM		 5716 /* Handle complex expressions. */
5717 sym = make_expr_symbol (i.op[0].disps);
5718 off = 0;
5719 }
3e73aa7c 5720
29b0f896
AM		 5721 /* 1 possible extra opcode + 4 byte displacement go in var part.
5722 Pass reloc in fr_var. */
5723 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5724}
3e73aa7c 5725
29b0f896 5726static void
e3bb37b5 5727output_jump (void)
29b0f896
AM		 5728{
5729 char *p;
5730 int size;
3e02c1cc 5731 fixS *fixP;
29b0f896 5732
40fb9820 5733 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5734 {
5735 /* This is a loop or jecxz type instruction. */
5736 size = 1;
5737 if (i.prefix[ADDR_PREFIX] != 0)
5738 {
5739 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5740 i.prefixes -= 1;
5741 }
5742 /* Pentium4 branch hints. */
5743 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5744 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5745 {
5746 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5747 i.prefixes--;
3e73aa7c
JH		 5748 }
5749 }
29b0f896
AM		 5750 else
5751 {
5752 int code16;
3e73aa7c 5753
29b0f896
AM		 5754 code16 = 0;
5755 if (flag_code == CODE_16BIT)
5756 code16 = CODE16;
3e73aa7c 5757
29b0f896
AM		 5758 if (i.prefix[DATA_PREFIX] != 0)
5759 {
5760 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5761 i.prefixes -= 1;
5762 code16 ^= CODE16;
5763 }
252b5132 5764
29b0f896
AM		 5765 size = 4;
5766 if (code16)
5767 size = 2;
5768 }
9fcc94b6 5769
29b0f896
AM		 5770 if (i.prefix[REX_PREFIX] != 0)
5771 {
5772 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5773 i.prefixes -= 1;
5774 }
252b5132 5775
29b0f896
AM		 5776 if (i.prefixes != 0 && !intel_syntax)
5777 as_warn (_("skipping prefixes on this instruction"));
e0890092 5778
29b0f896
AM		 5779 p = frag_more (1 + size);
5780 *p++ = i.tm.base_opcode;
e0890092 5781
3e02c1cc
AM		 5782 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5783 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5784
5785 /* All jumps handled here are signed, but don't use a signed limit
5786 check for 32 and 16 bit jumps as we want to allow wrap around at
5787 4G and 64k respectively. */
5788 if (size == 1)
5789 fixP->fx_signed = 1;
29b0f896 5790}
e0890092 5791
29b0f896 5792static void
e3bb37b5 5793output_interseg_jump (void)
29b0f896
AM		 5794{
5795 char *p;
5796 int size;
5797 int prefix;
5798 int code16;
252b5132 5799
29b0f896
AM		 5800 code16 = 0;
5801 if (flag_code == CODE_16BIT)
5802 code16 = CODE16;
a217f122 5803
29b0f896
AM		 5804 prefix = 0;
5805 if (i.prefix[DATA_PREFIX] != 0)
5806 {
5807 prefix = 1;
5808 i.prefixes -= 1;
5809 code16 ^= CODE16;
5810 }
5811 if (i.prefix[REX_PREFIX] != 0)
5812 {
5813 prefix++;
5814 i.prefixes -= 1;
5815 }
252b5132 5816
29b0f896
AM		 5817 size = 4;
5818 if (code16)
5819 size = 2;
252b5132 5820
29b0f896
AM		 5821 if (i.prefixes != 0 && !intel_syntax)
5822 as_warn (_("skipping prefixes on this instruction"));
252b5132 5823
29b0f896
AM		 5824 /* 1 opcode; 2 segment; offset */
5825 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5826
29b0f896
AM		 5827 if (i.prefix[DATA_PREFIX] != 0)
5828 *p++ = DATA_PREFIX_OPCODE;
252b5132 5829
29b0f896
AM		 5830 if (i.prefix[REX_PREFIX] != 0)
5831 *p++ = i.prefix[REX_PREFIX];
252b5132 5832
29b0f896
AM		 5833 *p++ = i.tm.base_opcode;
5834 if (i.op[1].imms->X_op == O_constant)
5835 {
5836 offsetT n = i.op[1].imms->X_add_number;
252b5132 5837
29b0f896
AM		 5838 if (size == 2
5839 && !fits_in_unsigned_word (n)
5840 && !fits_in_signed_word (n))
5841 {
5842 as_bad (_("16-bit jump out of range"));
5843 return;
5844 }
5845 md_number_to_chars (p, n, size);
5846 }
5847 else
5848 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5849 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5850 if (i.op[0].imms->X_op != O_constant)
5851 as_bad (_("can't handle non absolute segment in `%s'"),
5852 i.tm.name);
5853 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5854}
a217f122 5855
29b0f896 5856static void
e3bb37b5 5857output_insn (void)
29b0f896 5858{
2bbd9c25
JJ		 5859 fragS *insn_start_frag;
5860 offsetT insn_start_off;
5861
29b0f896
AM		 5862 /* Tie dwarf2 debug info to the address at the start of the insn.
5863 We can't do this after the insn has been output as the current
5864 frag may have been closed off. eg. by frag_var. */
5865 dwarf2_emit_insn (0);
5866
2bbd9c25
JJ		 5867 insn_start_frag = frag_now;
5868 insn_start_off = frag_now_fix ();
5869
29b0f896 5870 /* Output jumps. */
40fb9820 5871 if (i.tm.opcode_modifier.jump)
29b0f896 5872 output_branch ();
40fb9820
L		 5873 else if (i.tm.opcode_modifier.jumpbyte
5874 || i.tm.opcode_modifier.jumpdword)
29b0f896 5875 output_jump ();
40fb9820 5876 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5877 output_interseg_jump ();
5878 else
5879 {
5880 /* Output normal instructions here. */
5881 char *p;
5882 unsigned char *q;
47465058 5883 unsigned int j;
331d2d0d 5884 unsigned int prefix;
4dffcebc 5885
c0f3af97
L		 5886 /* Since the VEX prefix contains the implicit prefix, we don't
5887 need the explicit prefix. */
5888 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5889 {
c0f3af97 5890 switch (i.tm.opcode_length)
bc4bd9ab 5891 {
c0f3af97
L		 5892 case 3:
5893 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5894 {
c0f3af97
L		 5895 prefix = (i.tm.base_opcode >> 24) & 0xff;
5896 goto check_prefix;
5897 }
5898 break;
5899 case 2:
5900 if ((i.tm.base_opcode & 0xff0000) != 0)
5901 {
5902 prefix = (i.tm.base_opcode >> 16) & 0xff;
5903 if (i.tm.cpu_flags.bitfield.cpupadlock)
5904 {
4dffcebc 5905check_prefix:
c0f3af97
L		 5906 if (prefix != REPE_PREFIX_OPCODE
5907 || (i.prefix[LOCKREP_PREFIX]
5908 != REPE_PREFIX_OPCODE))
5909 add_prefix (prefix);
5910 }
5911 else
4dffcebc
L		 5912 add_prefix (prefix);
5913 }
c0f3af97
L		 5914 break;
5915 case 1:
5916 break;
5917 default:
5918 abort ();
bc4bd9ab 5919 }
c0f3af97
L		 5920
5921 /* The prefix bytes. */
5922 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5923 if (*q)
5924 FRAG_APPEND_1_CHAR (*q);
0f10071e 5925 }
252b5132 5926
c0f3af97
L		 5927 if (i.tm.opcode_modifier.vex)
5928 {
5929 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5930 if (*q)
5931 switch (j)
5932 {
5933 case REX_PREFIX:
5934 /* REX byte is encoded in VEX prefix. */
5935 break;
5936 case SEG_PREFIX:
5937 case ADDR_PREFIX:
5938 FRAG_APPEND_1_CHAR (*q);
5939 break;
5940 default:
5941 /* There should be no other prefixes for instructions
5942 with VEX prefix. */
5943 abort ();
5944 }
5945
5946 /* Now the VEX prefix. */
5947 p = frag_more (i.vex.length);
5948 for (j = 0; j < i.vex.length; j++)
5949 p[j] = i.vex.bytes[j];
5950 }
252b5132 5951
29b0f896 5952 /* Now the opcode; be careful about word order here! */
4dffcebc 5953 if (i.tm.opcode_length == 1)
29b0f896
AM		 5954 {
5955 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5956 }
5957 else
5958 {
4dffcebc 5959 switch (i.tm.opcode_length)
331d2d0d 5960 {
4dffcebc 5961 case 3:
331d2d0d
L		 5962 p = frag_more (3);
5963 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5964 break;
5965 case 2:
5966 p = frag_more (2);
5967 break;
5968 default:
5969 abort ();
5970 break;
331d2d0d 5971 }
0f10071e 5972
29b0f896
AM		 5973 /* Put out high byte first: can't use md_number_to_chars! */
5974 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5975 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5976
5977 /* On SSE5, encode the OC1 bit in the DREX field if this
5978 encoding has multiple formats. */
5979 if (i.tm.opcode_modifier.drex
5980 && i.tm.opcode_modifier.drexv
5981 && DREX_OC1 (i.tm.extension_opcode))
5982 *p |= DREX_OC1_MASK;
29b0f896 5983 }
3e73aa7c 5984
29b0f896 5985 /* Now the modrm byte and sib byte (if present). */
40fb9820 5986 if (i.tm.opcode_modifier.modrm)
29b0f896 5987 {
4a3523fa
L		 5988 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5989 | i.rm.reg << 3
5990 | i.rm.mode << 6));
29b0f896
AM		 5991 /* If i.rm.regmem == ESP (4)
5992 && i.rm.mode != (Register mode)
5993 && not 16 bit
5994 ==> need second modrm byte. */
5995 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5996 && i.rm.mode != 3
40fb9820 5997 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5998 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5999 | i.sib.index << 3
6000 | i.sib.scale << 6));
29b0f896 6001 }
3e73aa7c 6002
85f10a01
MM		 6003 /* Write the DREX byte if needed. */
6004 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
6005 {
6006 p = frag_more (1);
6007 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
6008
6009 /* Encode the OC0 bit if this encoding has multiple
6010 formats. */
6011 if ((i.tm.opcode_modifier.drex
6012 || i.tm.opcode_modifier.drexv)
6013 && DREX_OC0 (i.tm.extension_opcode))
6014 *p |= DREX_OC0_MASK;
6015 }
6016
29b0f896 6017 if (i.disp_operands)
2bbd9c25 6018 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6019
29b0f896 6020 if (i.imm_operands)
2bbd9c25 6021 output_imm (insn_start_frag, insn_start_off);
29b0f896 6022 }
252b5132 6023
29b0f896
AM		 6024#ifdef DEBUG386
6025 if (flag_debug)
6026 {
7b81dfbb 6027 pi ("" /*line*/, &i);
29b0f896
AM		 6028 }
6029#endif /* DEBUG386 */
6030}
252b5132 6031
e205caa7
L		 6032/* Return the size of the displacement operand N. */
6033
6034static int
6035disp_size (unsigned int n)
6036{
6037 int size = 4;
40fb9820
L		 6038 if (i.types[n].bitfield.disp64)
6039 size = 8;
6040 else if (i.types[n].bitfield.disp8)
6041 size = 1;
6042 else if (i.types[n].bitfield.disp16)
6043 size = 2;
e205caa7
L		 6044 return size;
6045}
6046
6047/* Return the size of the immediate operand N. */
6048
6049static int
6050imm_size (unsigned int n)
6051{
6052 int size = 4;
40fb9820
L		 6053 if (i.types[n].bitfield.imm64)
6054 size = 8;
6055 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6056 size = 1;
6057 else if (i.types[n].bitfield.imm16)
6058 size = 2;
e205caa7
L		 6059 return size;
6060}
6061
29b0f896 6062static void
64e74474 6063output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6064{
6065 char *p;
6066 unsigned int n;
252b5132 6067
29b0f896
AM		 6068 for (n = 0; n < i.operands; n++)
6069 {
40fb9820 6070 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6071 {
6072 if (i.op[n].disps->X_op == O_constant)
6073 {
e205caa7 6074 int size = disp_size (n);
29b0f896 6075 offsetT val;
252b5132 6076
29b0f896
AM		 6077 val = offset_in_range (i.op[n].disps->X_add_number,
6078 size);
6079 p = frag_more (size);
6080 md_number_to_chars (p, val, size);
6081 }
6082 else
6083 {
f86103b7 6084 enum bfd_reloc_code_real reloc_type;
e205caa7 6085 int size = disp_size (n);
40fb9820 6086 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6087 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6088
e205caa7 6089 /* We can't have 8 bit displacement here. */
40fb9820 6090 assert (!i.types[n].bitfield.disp8);
e205caa7 6091
29b0f896
AM		 6092 /* The PC relative address is computed relative
6093 to the instruction boundary, so in case immediate
6094 fields follows, we need to adjust the value. */
6095 if (pcrel && i.imm_operands)
6096 {
29b0f896 6097 unsigned int n1;
e205caa7 6098 int sz = 0;
252b5132 6099
29b0f896 6100 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6101 if (operand_type_check (i.types[n1], imm))
252b5132 6102 {
e205caa7
L		 6103 /* Only one immediate is allowed for PC
6104 relative address. */
6105 assert (sz == 0);
6106 sz = imm_size (n1);
6107 i.op[n].disps->X_add_number -= sz;
252b5132 6108 }
29b0f896 6109 /* We should find the immediate. */
e205caa7 6110 assert (sz != 0);
29b0f896 6111 }
520dc8e8 6112
29b0f896 6113 p = frag_more (size);
2bbd9c25 6114 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6115 if (GOT_symbol
2bbd9c25 6116 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6117 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6118 || reloc_type == BFD_RELOC_X86_64_32S
6119 || (reloc_type == BFD_RELOC_64
6120 && object_64bit))
d6ab8113
JB		 6121 && (i.op[n].disps->X_op == O_symbol
6122 || (i.op[n].disps->X_op == O_add
6123 && ((symbol_get_value_expression
6124 (i.op[n].disps->X_op_symbol)->X_op)
6125 == O_subtract))))
6126 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6127 {
6128 offsetT add;
6129
6130 if (insn_start_frag == frag_now)
6131 add = (p - frag_now->fr_literal) - insn_start_off;
6132 else
6133 {
6134 fragS *fr;
6135
6136 add = insn_start_frag->fr_fix - insn_start_off;
6137 for (fr = insn_start_frag->fr_next;
6138 fr && fr != frag_now; fr = fr->fr_next)
6139 add += fr->fr_fix;
6140 add += p - frag_now->fr_literal;
6141 }
6142
4fa24527 6143 if (!object_64bit)
7b81dfbb
AJ		 6144 {
6145 reloc_type = BFD_RELOC_386_GOTPC;
6146 i.op[n].imms->X_add_number += add;
6147 }
6148 else if (reloc_type == BFD_RELOC_64)
6149 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6150 else
7b81dfbb
AJ		 6151 /* Don't do the adjustment for x86-64, as there
6152 the pcrel addressing is relative to the _next_
6153 insn, and that is taken care of in other code. */
d6ab8113 6154 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6155 }
062cd5e7 6156 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6157 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6158 }
6159 }
6160 }
6161}
252b5132 6162
29b0f896 6163static void
64e74474 6164output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6165{
6166 char *p;
6167 unsigned int n;
252b5132 6168
29b0f896
AM		 6169 for (n = 0; n < i.operands; n++)
6170 {
40fb9820 6171 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6172 {
6173 if (i.op[n].imms->X_op == O_constant)
6174 {
e205caa7 6175 int size = imm_size (n);
29b0f896 6176 offsetT val;
b4cac588 6177
29b0f896
AM		 6178 val = offset_in_range (i.op[n].imms->X_add_number,
6179 size);
6180 p = frag_more (size);
6181 md_number_to_chars (p, val, size);
6182 }
6183 else
6184 {
6185 /* Not absolute_section.
6186 Need a 32-bit fixup (don't support 8bit
6187 non-absolute imms). Try to support other
6188 sizes ... */
f86103b7 6189 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6190 int size = imm_size (n);
6191 int sign;
29b0f896 6192
40fb9820 6193 if (i.types[n].bitfield.imm32s
a7d61044 6194 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6195 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6196 sign = 1;
e205caa7
L		 6197 else
6198 sign = 0;
520dc8e8 6199
29b0f896
AM		 6200 p = frag_more (size);
6201 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6202
2bbd9c25
JJ		 6203 /* This is tough to explain. We end up with this one if we
6204 * have operands that look like
6205 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6206 * obtain the absolute address of the GOT, and it is strongly
6207 * preferable from a performance point of view to avoid using
6208 * a runtime relocation for this. The actual sequence of
6209 * instructions often look something like:
6210 *
6211 * call .L66
6212 * .L66:
6213 * popl %ebx
6214 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6215 *
6216 * The call and pop essentially return the absolute address
6217 * of the label .L66 and store it in %ebx. The linker itself
6218 * will ultimately change the first operand of the addl so
6219 * that %ebx points to the GOT, but to keep things simple, the
6220 * .o file must have this operand set so that it generates not
6221 * the absolute address of .L66, but the absolute address of
6222 * itself. This allows the linker itself simply treat a GOTPC
6223 * relocation as asking for a pcrel offset to the GOT to be
6224 * added in, and the addend of the relocation is stored in the
6225 * operand field for the instruction itself.
6226 *
6227 * Our job here is to fix the operand so that it would add
6228 * the correct offset so that %ebx would point to itself. The
6229 * thing that is tricky is that .-.L66 will point to the
6230 * beginning of the instruction, so we need to further modify
6231 * the operand so that it will point to itself. There are
6232 * other cases where you have something like:
6233 *
6234 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6235 *
6236 * and here no correction would be required. Internally in
6237 * the assembler we treat operands of this form as not being
6238 * pcrel since the '.' is explicitly mentioned, and I wonder
6239 * whether it would simplify matters to do it this way. Who
6240 * knows. In earlier versions of the PIC patches, the
6241 * pcrel_adjust field was used to store the correction, but
6242 * since the expression is not pcrel, I felt it would be
6243 * confusing to do it this way. */
6244
d6ab8113 6245 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6246 || reloc_type == BFD_RELOC_X86_64_32S
6247 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6248 && GOT_symbol
6249 && GOT_symbol == i.op[n].imms->X_add_symbol
6250 && (i.op[n].imms->X_op == O_symbol
6251 || (i.op[n].imms->X_op == O_add
6252 && ((symbol_get_value_expression
6253 (i.op[n].imms->X_op_symbol)->X_op)
6254 == O_subtract))))
6255 {
2bbd9c25
JJ		 6256 offsetT add;
6257
6258 if (insn_start_frag == frag_now)
6259 add = (p - frag_now->fr_literal) - insn_start_off;
6260 else
6261 {
6262 fragS *fr;
6263
6264 add = insn_start_frag->fr_fix - insn_start_off;
6265 for (fr = insn_start_frag->fr_next;
6266 fr && fr != frag_now; fr = fr->fr_next)
6267 add += fr->fr_fix;
6268 add += p - frag_now->fr_literal;
6269 }
6270
4fa24527 6271 if (!object_64bit)
d6ab8113 6272 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6273 else if (size == 4)
d6ab8113 6274 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6275 else if (size == 8)
6276 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6277 i.op[n].imms->X_add_number += add;
29b0f896 6278 }
29b0f896
AM		 6279 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6280 i.op[n].imms, 0, reloc_type);
6281 }
6282 }
6283 }
252b5132
RH		 6284}
6285\f
d182319b
JB		 6286/* x86_cons_fix_new is called via the expression parsing code when a
6287 reloc is needed. We use this hook to get the correct .got reloc. */
6288static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6289static int cons_sign = -1;
6290
6291void
e3bb37b5 6292x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6293 expressionS *exp)
d182319b
JB		 6294{
6295 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6296
6297 got_reloc = NO_RELOC;
6298
6299#ifdef TE_PE
6300 if (exp->X_op == O_secrel)
6301 {
6302 exp->X_op = O_symbol;
6303 r = BFD_RELOC_32_SECREL;
6304 }
6305#endif
6306
6307 fix_new_exp (frag, off, len, exp, 0, r);
6308}
6309
718ddfc0
JB		 6310#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6311# define lex_got(reloc, adjust, types) NULL
6312#else
f3c180ae
AM		 6313/* Parse operands of the form
6314 <symbol>@GOTOFF+<nnn>
6315 and similar .plt or .got references.
6316
6317 If we find one, set up the correct relocation in RELOC and copy the
6318 input string, minus the `@GOTOFF' into a malloc'd buffer for
6319 parsing by the calling routine. Return this buffer, and if ADJUST
6320 is non-null set it to the length of the string we removed from the
6321 input line. Otherwise return NULL. */
6322static char *
3956db08 6323lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6324 int *adjust,
40fb9820 6325 i386_operand_type *types)
f3c180ae 6326{
7b81dfbb
AJ		 6327 /* Some of the relocations depend on the size of what field is to
6328 be relocated. But in our callers i386_immediate and i386_displacement
6329 we don't yet know the operand size (this will be set by insn
6330 matching). Hence we record the word32 relocation here,
6331 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6332 static const struct {
6333 const char *str;
4fa24527 6334 const enum bfd_reloc_code_real rel[2];
40fb9820 6335 const i386_operand_type types64;
f3c180ae 6336 } gotrel[] = {
4eed87de
AM		 6337 { "PLTOFF", { 0,
6338 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6339 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6340 { "PLT", { BFD_RELOC_386_PLT32,
6341 BFD_RELOC_X86_64_PLT32 },
40fb9820 6342 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6343 { "GOTPLT", { 0,
6344 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6345 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6346 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6347 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6348 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6349 { "GOTPCREL", { 0,
6350 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6351 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6352 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6353 BFD_RELOC_X86_64_TLSGD },
40fb9820 6354 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6355 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6356 0 },
40fb9820 6357 OPERAND_TYPE_NONE },
4eed87de
AM		 6358 { "TLSLD", { 0,
6359 BFD_RELOC_X86_64_TLSLD },
40fb9820 6360 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6361 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6362 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6363 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6364 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6365 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6366 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6367 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6368 0 },
40fb9820 6369 OPERAND_TYPE_NONE },
4eed87de
AM		 6370 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6371 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6372
6373 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6374 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6375 0 },
40fb9820 6376 OPERAND_TYPE_NONE },
4eed87de
AM		 6377 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6378 0 },
40fb9820 6379 OPERAND_TYPE_NONE },
4eed87de
AM		 6380 { "GOT", { BFD_RELOC_386_GOT32,
6381 BFD_RELOC_X86_64_GOT32 },
40fb9820 6382 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6383 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6384 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6385 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6386 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6387 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6388 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6389 };
6390 char *cp;
6391 unsigned int j;
6392
718ddfc0
JB		 6393 if (!IS_ELF)
6394 return NULL;
6395
f3c180ae 6396 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6397 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6398 return NULL;
6399
47465058 6400 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6401 {
6402 int len;
6403
6404 len = strlen (gotrel[j].str);
28f81592 6405 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6406 {
4fa24527 6407 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6408 {
28f81592
AM		 6409 int first, second;
6410 char *tmpbuf, *past_reloc;
f3c180ae 6411
4fa24527 6412 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6413 if (adjust)
6414 *adjust = len;
f3c180ae 6415
3956db08
JB		 6416 if (types)
6417 {
6418 if (flag_code != CODE_64BIT)
40fb9820
L		 6419 {
6420 types->bitfield.imm32 = 1;
6421 types->bitfield.disp32 = 1;
6422 }
3956db08
JB		 6423 else
6424 *types = gotrel[j].types64;
6425 }
6426
f3c180ae
AM		 6427 if (GOT_symbol == NULL)
6428 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6429
28f81592 6430 /* The length of the first part of our input line. */
f3c180ae 6431 first = cp - input_line_pointer;
28f81592
AM		 6432
6433 /* The second part goes from after the reloc token until
67c11a9b 6434 (and including) an end_of_line char or comma. */
28f81592 6435 past_reloc = cp + 1 + len;
67c11a9b
AM		 6436 cp = past_reloc;
6437 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6438 ++cp;
6439 second = cp + 1 - past_reloc;
28f81592
AM		 6440
6441 /* Allocate and copy string. The trailing NUL shouldn't
6442 be necessary, but be safe. */
6443 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6444 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6445 if (second != 0 && *past_reloc != ' ')
6446 /* Replace the relocation token with ' ', so that
6447 errors like foo@GOTOFF1 will be detected. */
6448 tmpbuf[first++] = ' ';
6449 memcpy (tmpbuf + first, past_reloc, second);
6450 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6451 return tmpbuf;
6452 }
6453
4fa24527
JB		 6454 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6455 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6456 return NULL;
6457 }
6458 }
6459
6460 /* Might be a symbol version string. Don't as_bad here. */
6461 return NULL;
6462}
6463
f3c180ae 6464void
e3bb37b5 6465x86_cons (expressionS *exp, int size)
f3c180ae 6466{
4fa24527 6467 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6468 {
6469 /* Handle @GOTOFF and the like in an expression. */
6470 char *save;
6471 char *gotfree_input_line;
6472 int adjust;
6473
6474 save = input_line_pointer;
3956db08 6475 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6476 if (gotfree_input_line)
6477 input_line_pointer = gotfree_input_line;
6478
6479 expression (exp);
6480
6481 if (gotfree_input_line)
6482 {
6483 /* expression () has merrily parsed up to the end of line,
6484 or a comma - in the wrong buffer. Transfer how far
6485 input_line_pointer has moved to the right buffer. */
6486 input_line_pointer = (save
6487 + (input_line_pointer - gotfree_input_line)
6488 + adjust);
6489 free (gotfree_input_line);
3992d3b7
AM		 6490 if (exp->X_op == O_constant
6491 || exp->X_op == O_absent
6492 || exp->X_op == O_illegal
6493 || exp->X_op == O_register
6494 || exp->X_op == O_big)
6495 {
6496 char c = *input_line_pointer;
6497 *input_line_pointer = 0;
6498 as_bad (_("missing or invalid expression `%s'"), save);
6499 *input_line_pointer = c;
6500 }
f3c180ae
AM		 6501 }
6502 }
6503 else
6504 expression (exp);
6505}
6506#endif
6507
d182319b 6508static void signed_cons (int size)
6482c264 6509{
d182319b
JB		 6510 if (flag_code == CODE_64BIT)
6511 cons_sign = 1;
6512 cons (size);
6513 cons_sign = -1;
6482c264
NC		 6514}
6515
d182319b 6516#ifdef TE_PE
6482c264
NC		 6517static void
6518pe_directive_secrel (dummy)
6519 int dummy ATTRIBUTE_UNUSED;
6520{
6521 expressionS exp;
6522
6523 do
6524 {
6525 expression (&exp);
6526 if (exp.X_op == O_symbol)
6527 exp.X_op = O_secrel;
6528
6529 emit_expr (&exp, 4);
6530 }
6531 while (*input_line_pointer++ == ',');
6532
6533 input_line_pointer--;
6534 demand_empty_rest_of_line ();
6535}
6482c264
NC		 6536#endif
6537
252b5132 6538static int
70e41ade 6539i386_immediate (char *imm_start)
252b5132
RH		 6540{
6541 char *save_input_line_pointer;
f3c180ae 6542 char *gotfree_input_line;
252b5132 6543 segT exp_seg = 0;
47926f60 6544 expressionS *exp;
40fb9820
L		 6545 i386_operand_type types;
6546
0dfbf9d7 6547 operand_type_set (&types, ~0);
252b5132
RH		 6548
6549 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6550 {
31b2323c
L		 6551 as_bad (_("at most %d immediate operands are allowed"),
6552 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6553 return 0;
6554 }
6555
6556 exp = &im_expressions[i.imm_operands++];
520dc8e8 6557 i.op[this_operand].imms = exp;
252b5132
RH		 6558
6559 if (is_space_char (*imm_start))
6560 ++imm_start;
6561
6562 save_input_line_pointer = input_line_pointer;
6563 input_line_pointer = imm_start;
6564
3956db08 6565 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6566 if (gotfree_input_line)
6567 input_line_pointer = gotfree_input_line;
252b5132
RH		 6568
6569 exp_seg = expression (exp);
6570
83183c0c 6571 SKIP_WHITESPACE ();
252b5132 6572 if (*input_line_pointer)
f3c180ae 6573 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6574
6575 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6576 if (gotfree_input_line)
6577 free (gotfree_input_line);
252b5132 6578
3992d3b7
AM		 6579 if (exp->X_op == O_absent
6580 || exp->X_op == O_illegal
6581 || exp->X_op == O_big
6582 || (gotfree_input_line
6583 && (exp->X_op == O_constant
6584 || exp->X_op == O_register)))
252b5132 6585 {
3992d3b7 6586 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6587 imm_start);
3992d3b7 6588 return 0;
252b5132 6589 }
3e73aa7c 6590 else if (exp->X_op == O_constant)
252b5132 6591 {
47926f60 6592 /* Size it properly later. */
40fb9820 6593 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6594 /* If BFD64, sign extend val. */
4eed87de
AM		 6595 if (!use_rela_relocations
6596 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6597 exp->X_add_number
6598 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6599 }
4c63da97 6600#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6601 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6602 && exp_seg != absolute_section
47926f60 6603 && exp_seg != text_section
24eab124
AM		 6604 && exp_seg != data_section
6605 && exp_seg != bss_section
6606 && exp_seg != undefined_section
f86103b7 6607 && !bfd_is_com_section (exp_seg))
252b5132 6608 {
d0b47220 6609 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6610 return 0;
6611 }
6612#endif
bb8f5920
L		 6613 else if (!intel_syntax && exp->X_op == O_register)
6614 {
6615 as_bad (_("illegal immediate register operand %s"), imm_start);
6616 return 0;
6617 }
252b5132
RH		 6618 else
6619 {
6620 /* This is an address. The size of the address will be
24eab124 6621 determined later, depending on destination register,
3e73aa7c 6622 suffix, or the default for the section. */
40fb9820
L		 6623 i.types[this_operand].bitfield.imm8 = 1;
6624 i.types[this_operand].bitfield.imm16 = 1;
6625 i.types[this_operand].bitfield.imm32 = 1;
6626 i.types[this_operand].bitfield.imm32s = 1;
6627 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6628 i.types[this_operand] = operand_type_and (i.types[this_operand],
6629 types);
252b5132
RH		 6630 }
6631
6632 return 1;
6633}
6634
551c1ca1 6635static char *
e3bb37b5 6636i386_scale (char *scale)
252b5132 6637{
551c1ca1
AM		 6638 offsetT val;
6639 char *save = input_line_pointer;
252b5132 6640
551c1ca1
AM		 6641 input_line_pointer = scale;
6642 val = get_absolute_expression ();
6643
6644 switch (val)
252b5132 6645 {
551c1ca1 6646 case 1:
252b5132
RH		 6647 i.log2_scale_factor = 0;
6648 break;
551c1ca1 6649 case 2:
252b5132
RH		 6650 i.log2_scale_factor = 1;
6651 break;
551c1ca1 6652 case 4:
252b5132
RH		 6653 i.log2_scale_factor = 2;
6654 break;
551c1ca1 6655 case 8:
252b5132
RH		 6656 i.log2_scale_factor = 3;
6657 break;
6658 default:
a724f0f4
JB		 6659 {
6660 char sep = *input_line_pointer;
6661
6662 *input_line_pointer = '\0';
6663 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6664 scale);
6665 *input_line_pointer = sep;
6666 input_line_pointer = save;
6667 return NULL;
6668 }
252b5132 6669 }
29b0f896 6670 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6671 {
6672 as_warn (_("scale factor of %d without an index register"),
24eab124 6673 1 << i.log2_scale_factor);
252b5132 6674 i.log2_scale_factor = 0;
252b5132 6675 }
551c1ca1
AM		 6676 scale = input_line_pointer;
6677 input_line_pointer = save;
6678 return scale;
252b5132
RH		 6679}
6680
252b5132 6681static int
e3bb37b5 6682i386_displacement (char *disp_start, char *disp_end)
252b5132 6683{
29b0f896 6684 expressionS *exp;
252b5132
RH		 6685 segT exp_seg = 0;
6686 char *save_input_line_pointer;
f3c180ae 6687 char *gotfree_input_line;
40fb9820
L		 6688 int override;
6689 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6690 int ret;
252b5132 6691
31b2323c
L		 6692 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6693 {
6694 as_bad (_("at most %d displacement operands are allowed"),
6695 MAX_MEMORY_OPERANDS);
6696 return 0;
6697 }
6698
0dfbf9d7 6699 operand_type_set (&bigdisp, 0);
40fb9820
L		 6700 if ((i.types[this_operand].bitfield.jumpabsolute)
6701 || (!current_templates->start->opcode_modifier.jump
6702 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6703 {
40fb9820 6704 bigdisp.bitfield.disp32 = 1;
e05278af 6705 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6706 if (flag_code == CODE_64BIT)
6707 {
6708 if (!override)
6709 {
6710 bigdisp.bitfield.disp32s = 1;
6711 bigdisp.bitfield.disp64 = 1;
6712 }
6713 }
6714 else if ((flag_code == CODE_16BIT) ^ override)
6715 {
6716 bigdisp.bitfield.disp32 = 0;
6717 bigdisp.bitfield.disp16 = 1;
6718 }
e05278af
JB		 6719 }
6720 else
6721 {
6722 /* For PC-relative branches, the width of the displacement
6723 is dependent upon data size, not address size. */
e05278af 6724 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6725 if (flag_code == CODE_64BIT)
6726 {
6727 if (override || i.suffix == WORD_MNEM_SUFFIX)
6728 bigdisp.bitfield.disp16 = 1;
6729 else
6730 {
6731 bigdisp.bitfield.disp32 = 1;
6732 bigdisp.bitfield.disp32s = 1;
6733 }
6734 }
6735 else
e05278af
JB		 6736 {
6737 if (!override)
6738 override = (i.suffix == (flag_code != CODE_16BIT
6739 ? WORD_MNEM_SUFFIX
6740 : LONG_MNEM_SUFFIX));
40fb9820
L		 6741 bigdisp.bitfield.disp32 = 1;
6742 if ((flag_code == CODE_16BIT) ^ override)
6743 {
6744 bigdisp.bitfield.disp32 = 0;
6745 bigdisp.bitfield.disp16 = 1;
6746 }
e05278af 6747 }
e05278af 6748 }
c6fb90c8
L		 6749 i.types[this_operand] = operand_type_or (i.types[this_operand],
6750 bigdisp);
252b5132
RH		 6751
6752 exp = &disp_expressions[i.disp_operands];
520dc8e8 6753 i.op[this_operand].disps = exp;
252b5132
RH		 6754 i.disp_operands++;
6755 save_input_line_pointer = input_line_pointer;
6756 input_line_pointer = disp_start;
6757 END_STRING_AND_SAVE (disp_end);
6758
6759#ifndef GCC_ASM_O_HACK
6760#define GCC_ASM_O_HACK 0
6761#endif
6762#if GCC_ASM_O_HACK
6763 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6764 if (i.types[this_operand].bitfield.baseIndex
24eab124 6765 && displacement_string_end[-1] == '+')
252b5132
RH		 6766 {
6767 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6768 constraint within gcc asm statements.
6769 For instance:
6770
6771 #define _set_tssldt_desc(n,addr,limit,type) \
6772 __asm__ __volatile__ ( \
6773 "movw %w2,%0\n\t" \
6774 "movw %w1,2+%0\n\t" \
6775 "rorl $16,%1\n\t" \
6776 "movb %b1,4+%0\n\t" \
6777 "movb %4,5+%0\n\t" \
6778 "movb $0,6+%0\n\t" \
6779 "movb %h1,7+%0\n\t" \
6780 "rorl $16,%1" \
6781 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6782
6783 This works great except that the output assembler ends
6784 up looking a bit weird if it turns out that there is
6785 no offset. You end up producing code that looks like:
6786
6787 #APP
6788 movw $235,(%eax)
6789 movw %dx,2+(%eax)
6790 rorl $16,%edx
6791 movb %dl,4+(%eax)
6792 movb $137,5+(%eax)
6793 movb $0,6+(%eax)
6794 movb %dh,7+(%eax)
6795 rorl $16,%edx
6796 #NO_APP
6797
47926f60 6798 So here we provide the missing zero. */
24eab124
AM		 6799
6800 *displacement_string_end = '0';
252b5132
RH		 6801 }
6802#endif
3956db08 6803 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6804 if (gotfree_input_line)
6805 input_line_pointer = gotfree_input_line;
252b5132 6806
24eab124 6807 exp_seg = expression (exp);
252b5132 6808
636c26b0
AM		 6809 SKIP_WHITESPACE ();
6810 if (*input_line_pointer)
6811 as_bad (_("junk `%s' after expression"), input_line_pointer);
6812#if GCC_ASM_O_HACK
6813 RESTORE_END_STRING (disp_end + 1);
6814#endif
636c26b0 6815 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6816 if (gotfree_input_line)
6817 free (gotfree_input_line);
3992d3b7 6818 ret = 1;
636c26b0 6819
24eab124
AM		 6820 /* We do this to make sure that the section symbol is in
6821 the symbol table. We will ultimately change the relocation
47926f60 6822 to be relative to the beginning of the section. */
1ae12ab7 6823 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6824 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6825 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6826 {
636c26b0 6827 if (exp->X_op != O_symbol)
3992d3b7 6828 goto inv_disp;
636c26b0 6829
e5cb08ac 6830 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6831 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6832 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6833 exp->X_op = O_subtract;
6834 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6835 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6836 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6837 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6838 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6839 else
29b0f896 6840 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6841 }
252b5132 6842
3992d3b7
AM		 6843 else if (exp->X_op == O_absent
6844 || exp->X_op == O_illegal
6845 || exp->X_op == O_big
6846 || (gotfree_input_line
6847 && (exp->X_op == O_constant
6848 || exp->X_op == O_register)))
2daf4fd8 6849 {
3992d3b7
AM		 6850 inv_disp:
6851 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6852 disp_start);
3992d3b7 6853 ret = 0;
2daf4fd8
AM		 6854 }
6855
4c63da97 6856#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6857 else if (exp->X_op != O_constant
6858 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6859 && exp_seg != absolute_section
6860 && exp_seg != text_section
6861 && exp_seg != data_section
6862 && exp_seg != bss_section
6863 && exp_seg != undefined_section
6864 && !bfd_is_com_section (exp_seg))
24eab124 6865 {
d0b47220 6866 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6867 ret = 0;
24eab124 6868 }
252b5132 6869#endif
3956db08 6870
3992d3b7
AM		 6871 RESTORE_END_STRING (disp_end);
6872
40fb9820
L		 6873 /* Check if this is a displacement only operand. */
6874 bigdisp = i.types[this_operand];
6875 bigdisp.bitfield.disp8 = 0;
6876 bigdisp.bitfield.disp16 = 0;
6877 bigdisp.bitfield.disp32 = 0;
6878 bigdisp.bitfield.disp32s = 0;
6879 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6880 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6881 i.types[this_operand] = operand_type_and (i.types[this_operand],
6882 types);
3956db08 6883
3992d3b7 6884 return ret;
252b5132
RH		 6885}
6886
eecb386c 6887/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6888 Return 1 on success, 0 on a failure. */
6889
252b5132 6890static int
e3bb37b5 6891i386_index_check (const char *operand_string)
252b5132 6892{
3e73aa7c 6893 int ok;
fc0763e6 6894 const char *kind = "base/index";
24eab124 6895#if INFER_ADDR_PREFIX
eecb386c
AM		 6896 int fudged = 0;
6897
24eab124
AM		 6898 tryprefix:
6899#endif
3e73aa7c 6900 ok = 1;
fc0763e6
JB		 6901 if (current_templates->start->opcode_modifier.isstring
6902 && !current_templates->start->opcode_modifier.immext
6903 && (current_templates->end[-1].opcode_modifier.isstring
6904 || i.mem_operands))
6905 {
6906 /* Memory operands of string insns are special in that they only allow
6907 a single register (rDI, rSI, or rBX) as their memory address. */
6908 unsigned int expected;
6909
6910 kind = "string address";
6911
6912 if (current_templates->start->opcode_modifier.w)
6913 {
6914 i386_operand_type type = current_templates->end[-1].operand_types[0];
6915
6916 if (!type.bitfield.baseindex
6917 || ((!i.mem_operands != !intel_syntax)
6918 && current_templates->end[-1].operand_types[1]
6919 .bitfield.baseindex))
6920 type = current_templates->end[-1].operand_types[1];
6921 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6922 }
6923 else
6924 expected = 3 /* rBX */;
6925
6926 if (!i.base_reg || i.index_reg
6927 || operand_type_check (i.types[this_operand], disp))
6928 ok = -1;
6929 else if (!(flag_code == CODE_64BIT
6930 ? i.prefix[ADDR_PREFIX]
6931 ? i.base_reg->reg_type.bitfield.reg32
6932 : i.base_reg->reg_type.bitfield.reg64
6933 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6934 ? i.base_reg->reg_type.bitfield.reg32
6935 : i.base_reg->reg_type.bitfield.reg16))
6936 ok = 0;
6937 else if (i.base_reg->reg_num != expected)
6938 ok = -1;
6939
6940 if (ok < 0)
6941 {
6942 unsigned int j;
6943
6944 for (j = 0; j < i386_regtab_size; ++j)
6945 if ((flag_code == CODE_64BIT
6946 ? i.prefix[ADDR_PREFIX]
6947 ? i386_regtab[j].reg_type.bitfield.reg32
6948 : i386_regtab[j].reg_type.bitfield.reg64
6949 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6950 ? i386_regtab[j].reg_type.bitfield.reg32
6951 : i386_regtab[j].reg_type.bitfield.reg16)
6952 && i386_regtab[j].reg_num == expected)
6953 break;
6954 assert (j < i386_regtab_size);
6955 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6956 operand_string,
6957 intel_syntax ? '[' : '(',
6958 register_prefix,
6959 i386_regtab[j].reg_name,
6960 intel_syntax ? ']' : ')');
6961 ok = 1;
6962 }
6963 }
6964 else if (flag_code == CODE_64BIT)
64e74474 6965 {
64e74474 6966 if ((i.base_reg
40fb9820
L		 6967 && ((i.prefix[ADDR_PREFIX] == 0
6968 && !i.base_reg->reg_type.bitfield.reg64)
6969 || (i.prefix[ADDR_PREFIX]
6970 && !i.base_reg->reg_type.bitfield.reg32))
6971 && (i.index_reg
9a04903e
JB		 6972 || i.base_reg->reg_num !=
6973 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6974 || (i.index_reg
40fb9820
L		 6975 && (!i.index_reg->reg_type.bitfield.baseindex
6976 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6977 && i.index_reg->reg_num != RegRiz
6978 && !i.index_reg->reg_type.bitfield.reg64
6979 )
40fb9820 6980 || (i.prefix[ADDR_PREFIX]
db51cc60 6981 && i.index_reg->reg_num != RegEiz
40fb9820 6982 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6983 ok = 0;
3e73aa7c
JH		 6984 }
6985 else
6986 {
6987 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6988 {
6989 /* 16bit checks. */
6990 if ((i.base_reg
40fb9820
L		 6991 && (!i.base_reg->reg_type.bitfield.reg16
6992 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6993 || (i.index_reg
40fb9820
L		 6994 && (!i.index_reg->reg_type.bitfield.reg16
6995 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6996 || !(i.base_reg
6997 && i.base_reg->reg_num < 6
6998 && i.index_reg->reg_num >= 6
6999 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 7000 ok = 0;
7001 }
7002 else
e5cb08ac 7003 {
3e73aa7c
JH		 7004 /* 32bit checks. */
7005 if ((i.base_reg
40fb9820 7006 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 7007 || (i.index_reg
db51cc60
L		 7008 && ((!i.index_reg->reg_type.bitfield.reg32
7009 && i.index_reg->reg_num != RegEiz)
40fb9820 7010 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7011 ok = 0;
3e73aa7c
JH		 7012 }
7013 }
7014 if (!ok)
24eab124
AM		 7015 {
7016#if INFER_ADDR_PREFIX
fc0763e6 7017 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7018 {
7019 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7020 i.prefixes += 1;
b23bac36
AM		 7021 /* Change the size of any displacement too. At most one of
7022 Disp16 or Disp32 is set.
7023 FIXME. There doesn't seem to be any real need for separate
7024 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7025 Removing them would probably clean up the code quite a lot. */
4eed87de 7026 if (flag_code != CODE_64BIT
40fb9820
L		 7027 && (i.types[this_operand].bitfield.disp16
7028 || i.types[this_operand].bitfield.disp32))
7029 i.types[this_operand]
c6fb90c8 7030 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7031 fudged = 1;
24eab124
AM		 7032 goto tryprefix;
7033 }
eecb386c 7034 if (fudged)
fc0763e6
JB		 7035 as_bad (_("`%s' is not a valid %s expression"),
7036 operand_string,
7037 kind);
eecb386c 7038 else
c388dee8 7039#endif
fc0763e6 7040 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7041 operand_string,
fc0763e6
JB		 7042 flag_code_names[i.prefix[ADDR_PREFIX]
7043 ? flag_code == CODE_32BIT
7044 ? CODE_16BIT
7045 : CODE_32BIT
7046 : flag_code],
7047 kind);
24eab124 7048 }
20f0a1fc 7049 return ok;
24eab124 7050}
252b5132 7051
fc0763e6 7052/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7053 on error. */
252b5132 7054
252b5132 7055static int
a7619375 7056i386_att_operand (char *operand_string)
252b5132 7057{
af6bdddf
AM		 7058 const reg_entry *r;
7059 char *end_op;
24eab124 7060 char *op_string = operand_string;
252b5132 7061
24eab124 7062 if (is_space_char (*op_string))
252b5132
RH		 7063 ++op_string;
7064
24eab124 7065 /* We check for an absolute prefix (differentiating,
47926f60 7066 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7067 if (*op_string == ABSOLUTE_PREFIX)
7068 {
7069 ++op_string;
7070 if (is_space_char (*op_string))
7071 ++op_string;
40fb9820 7072 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7073 }
252b5132 7074
47926f60 7075 /* Check if operand is a register. */
4d1bb795 7076 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7077 {
40fb9820
L		 7078 i386_operand_type temp;
7079
24eab124
AM		 7080 /* Check for a segment override by searching for ':' after a
7081 segment register. */
7082 op_string = end_op;
7083 if (is_space_char (*op_string))
7084 ++op_string;
40fb9820
L		 7085 if (*op_string == ':'
7086 && (r->reg_type.bitfield.sreg2
7087 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7088 {
7089 switch (r->reg_num)
7090 {
7091 case 0:
7092 i.seg[i.mem_operands] = &es;
7093 break;
7094 case 1:
7095 i.seg[i.mem_operands] = &cs;
7096 break;
7097 case 2:
7098 i.seg[i.mem_operands] = &ss;
7099 break;
7100 case 3:
7101 i.seg[i.mem_operands] = &ds;
7102 break;
7103 case 4:
7104 i.seg[i.mem_operands] = &fs;
7105 break;
7106 case 5:
7107 i.seg[i.mem_operands] = &gs;
7108 break;
7109 }
252b5132 7110
24eab124 7111 /* Skip the ':' and whitespace. */
252b5132
RH		 7112 ++op_string;
7113 if (is_space_char (*op_string))
24eab124 7114 ++op_string;
252b5132 7115
24eab124
AM		 7116 if (!is_digit_char (*op_string)
7117 && !is_identifier_char (*op_string)
7118 && *op_string != '('
7119 && *op_string != ABSOLUTE_PREFIX)
7120 {
7121 as_bad (_("bad memory operand `%s'"), op_string);
7122 return 0;
7123 }
47926f60 7124 /* Handle case of %es:*foo. */
24eab124
AM		 7125 if (*op_string == ABSOLUTE_PREFIX)
7126 {
7127 ++op_string;
7128 if (is_space_char (*op_string))
7129 ++op_string;
40fb9820 7130 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7131 }
7132 goto do_memory_reference;
7133 }
7134 if (*op_string)
7135 {
d0b47220 7136 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7137 return 0;
7138 }
40fb9820
L		 7139 temp = r->reg_type;
7140 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7141 i.types[this_operand] = operand_type_or (i.types[this_operand],
7142 temp);
7d5e4556 7143 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7144 i.op[this_operand].regs = r;
24eab124
AM		 7145 i.reg_operands++;
7146 }
af6bdddf
AM		 7147 else if (*op_string == REGISTER_PREFIX)
7148 {
7149 as_bad (_("bad register name `%s'"), op_string);
7150 return 0;
7151 }
24eab124 7152 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7153 {
24eab124 7154 ++op_string;
40fb9820 7155 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7156 {
d0b47220 7157 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7158 return 0;
7159 }
7160 if (!i386_immediate (op_string))
7161 return 0;
7162 }
7163 else if (is_digit_char (*op_string)
7164 || is_identifier_char (*op_string)
e5cb08ac 7165 || *op_string == '(')
24eab124 7166 {
47926f60 7167 /* This is a memory reference of some sort. */
af6bdddf 7168 char *base_string;
252b5132 7169
47926f60 7170 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7171 char *displacement_string_start;
7172 char *displacement_string_end;
252b5132 7173
24eab124 7174 do_memory_reference:
24eab124 7175 if ((i.mem_operands == 1
40fb9820 7176 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7177 || i.mem_operands == 2)
7178 {
7179 as_bad (_("too many memory references for `%s'"),
7180 current_templates->start->name);
7181 return 0;
7182 }
252b5132 7183
24eab124
AM		 7184 /* Check for base index form. We detect the base index form by
7185 looking for an ')' at the end of the operand, searching
7186 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7187 after the '('. */
af6bdddf 7188 base_string = op_string + strlen (op_string);
c3332e24 7189
af6bdddf
AM		 7190 --base_string;
7191 if (is_space_char (*base_string))
7192 --base_string;
252b5132 7193
47926f60 7194 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7195 displacement_string_start = op_string;
7196 displacement_string_end = base_string + 1;
252b5132 7197
24eab124
AM		 7198 if (*base_string == ')')
7199 {
af6bdddf 7200 char *temp_string;
24eab124
AM		 7201 unsigned int parens_balanced = 1;
7202 /* We've already checked that the number of left & right ()'s are
47926f60 7203 equal, so this loop will not be infinite. */
24eab124
AM		 7204 do
7205 {
7206 base_string--;
7207 if (*base_string == ')')
7208 parens_balanced++;
7209 if (*base_string == '(')
7210 parens_balanced--;
7211 }
7212 while (parens_balanced);
c3332e24 7213
af6bdddf 7214 temp_string = base_string;
c3332e24 7215
24eab124 7216 /* Skip past '(' and whitespace. */
252b5132
RH		 7217 ++base_string;
7218 if (is_space_char (*base_string))
24eab124 7219 ++base_string;
252b5132 7220
af6bdddf 7221 if (*base_string == ','
4eed87de
AM		 7222 || ((i.base_reg = parse_register (base_string, &end_op))
7223 != NULL))
252b5132 7224 {
af6bdddf 7225 displacement_string_end = temp_string;
252b5132 7226
40fb9820 7227 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7228
af6bdddf 7229 if (i.base_reg)
24eab124 7230 {
24eab124
AM		 7231 base_string = end_op;
7232 if (is_space_char (*base_string))
7233 ++base_string;
af6bdddf
AM		 7234 }
7235
7236 /* There may be an index reg or scale factor here. */
7237 if (*base_string == ',')
7238 {
7239 ++base_string;
7240 if (is_space_char (*base_string))
7241 ++base_string;
7242
4eed87de
AM		 7243 if ((i.index_reg = parse_register (base_string, &end_op))
7244 != NULL)
24eab124 7245 {
af6bdddf 7246 base_string = end_op;
24eab124
AM		 7247 if (is_space_char (*base_string))
7248 ++base_string;
af6bdddf
AM		 7249 if (*base_string == ',')
7250 {
7251 ++base_string;
7252 if (is_space_char (*base_string))
7253 ++base_string;
7254 }
e5cb08ac 7255 else if (*base_string != ')')
af6bdddf 7256 {
4eed87de
AM		 7257 as_bad (_("expecting `,' or `)' "
7258 "after index register in `%s'"),
af6bdddf
AM		 7259 operand_string);
7260 return 0;
7261 }
24eab124 7262 }
af6bdddf 7263 else if (*base_string == REGISTER_PREFIX)
24eab124 7264 {
af6bdddf 7265 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7266 return 0;
7267 }
252b5132 7268
47926f60 7269 /* Check for scale factor. */
551c1ca1 7270 if (*base_string != ')')
af6bdddf 7271 {
551c1ca1
AM		 7272 char *end_scale = i386_scale (base_string);
7273
7274 if (!end_scale)
af6bdddf 7275 return 0;
24eab124 7276
551c1ca1 7277 base_string = end_scale;
af6bdddf
AM		 7278 if (is_space_char (*base_string))
7279 ++base_string;
7280 if (*base_string != ')')
7281 {
4eed87de
AM		 7282 as_bad (_("expecting `)' "
7283 "after scale factor in `%s'"),
af6bdddf
AM		 7284 operand_string);
7285 return 0;
7286 }
7287 }
7288 else if (!i.index_reg)
24eab124 7289 {
4eed87de
AM		 7290 as_bad (_("expecting index register or scale factor "
7291 "after `,'; got '%c'"),
af6bdddf 7292 *base_string);
24eab124
AM		 7293 return 0;
7294 }
7295 }
af6bdddf 7296 else if (*base_string != ')')
24eab124 7297 {
4eed87de
AM		 7298 as_bad (_("expecting `,' or `)' "
7299 "after base register in `%s'"),
af6bdddf 7300 operand_string);
24eab124
AM		 7301 return 0;
7302 }
c3332e24 7303 }
af6bdddf 7304 else if (*base_string == REGISTER_PREFIX)
c3332e24 7305 {
af6bdddf 7306 as_bad (_("bad register name `%s'"), base_string);
24eab124 7307 return 0;
c3332e24 7308 }
24eab124
AM		 7309 }
7310
7311 /* If there's an expression beginning the operand, parse it,
7312 assuming displacement_string_start and
7313 displacement_string_end are meaningful. */
7314 if (displacement_string_start != displacement_string_end)
7315 {
7316 if (!i386_displacement (displacement_string_start,
7317 displacement_string_end))
7318 return 0;
7319 }
7320
7321 /* Special case for (%dx) while doing input/output op. */
7322 if (i.base_reg
0dfbf9d7
L		 7323 && operand_type_equal (&i.base_reg->reg_type,
7324 &reg16_inoutportreg)
24eab124
AM		 7325 && i.index_reg == 0
7326 && i.log2_scale_factor == 0
7327 && i.seg[i.mem_operands] == 0
40fb9820 7328 && !operand_type_check (i.types[this_operand], disp))
24eab124 7329 {
65da13b5 7330 i.types[this_operand] = inoutportreg;
24eab124
AM		 7331 return 1;
7332 }
7333
eecb386c
AM		 7334 if (i386_index_check (operand_string) == 0)
7335 return 0;
5c07affc 7336 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7337 i.mem_operands++;
7338 }
7339 else
ce8a8b2f
AM		 7340 {
7341 /* It's not a memory operand; argh! */
24eab124
AM		 7342 as_bad (_("invalid char %s beginning operand %d `%s'"),
7343 output_invalid (*op_string),
7344 this_operand + 1,
7345 op_string);
7346 return 0;
7347 }
47926f60 7348 return 1; /* Normal return. */
252b5132
RH		 7349}
7350\f
ee7fcc42
AM		 7351/* md_estimate_size_before_relax()
7352
7353 Called just before relax() for rs_machine_dependent frags. The x86
7354 assembler uses these frags to handle variable size jump
7355 instructions.
7356
7357 Any symbol that is now undefined will not become defined.
7358 Return the correct fr_subtype in the frag.
7359 Return the initial "guess for variable size of frag" to caller.
7360 The guess is actually the growth beyond the fixed part. Whatever
7361 we do to grow the fixed or variable part contributes to our
7362 returned value. */
7363
252b5132
RH		 7364int
7365md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7366 fragS *fragP;
7367 segT segment;
252b5132 7368{
252b5132 7369 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7370 check for un-relaxable symbols. On an ELF system, we can't relax
7371 an externally visible symbol, because it may be overridden by a
7372 shared library. */
7373 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7374#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7375 || (IS_ELF
31312f95
AM		 7376 && (S_IS_EXTERNAL (fragP->fr_symbol)
7377 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7378#endif
7379 )
252b5132 7380 {
b98ef147
AM		 7381 /* Symbol is undefined in this segment, or we need to keep a
7382 reloc so that weak symbols can be overridden. */
7383 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7384 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7385 unsigned char *opcode;
7386 int old_fr_fix;
f6af82bd 7387
ee7fcc42
AM		 7388 if (fragP->fr_var != NO_RELOC)
7389 reloc_type = fragP->fr_var;
b98ef147 7390 else if (size == 2)
f6af82bd
AM		 7391 reloc_type = BFD_RELOC_16_PCREL;
7392 else
7393 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7394
ee7fcc42
AM		 7395 old_fr_fix = fragP->fr_fix;
7396 opcode = (unsigned char *) fragP->fr_opcode;
7397
fddf5b5b 7398 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7399 {
fddf5b5b
AM		 7400 case UNCOND_JUMP:
7401 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7402 opcode[0] = 0xe9;
252b5132 7403 fragP->fr_fix += size;
062cd5e7
AS		 7404 fix_new (fragP, old_fr_fix, size,
7405 fragP->fr_symbol,
7406 fragP->fr_offset, 1,
7407 reloc_type);
252b5132
RH		 7408 break;
7409
fddf5b5b 7410 case COND_JUMP86:
412167cb
AM		 7411 if (size == 2
7412 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7413 {
7414 /* Negate the condition, and branch past an
7415 unconditional jump. */
7416 opcode[0] ^= 1;
7417 opcode[1] = 3;
7418 /* Insert an unconditional jump. */
7419 opcode[2] = 0xe9;
7420 /* We added two extra opcode bytes, and have a two byte
7421 offset. */
7422 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7423 fix_new (fragP, old_fr_fix + 2, 2,
7424 fragP->fr_symbol,
7425 fragP->fr_offset, 1,
7426 reloc_type);
fddf5b5b
AM		 7427 break;
7428 }
7429 /* Fall through. */
7430
7431 case COND_JUMP:
412167cb
AM		 7432 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7433 {
3e02c1cc
AM		 7434 fixS *fixP;
7435
412167cb 7436 fragP->fr_fix += 1;
3e02c1cc
AM		 7437 fixP = fix_new (fragP, old_fr_fix, 1,
7438 fragP->fr_symbol,
7439 fragP->fr_offset, 1,
7440 BFD_RELOC_8_PCREL);
7441 fixP->fx_signed = 1;
412167cb
AM		 7442 break;
7443 }
93c2a809 7444
24eab124 7445 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7446 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7447 opcode[1] = opcode[0] + 0x10;
f6af82bd 7448 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7449 /* We've added an opcode byte. */
7450 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7451 fix_new (fragP, old_fr_fix + 1, size,
7452 fragP->fr_symbol,
7453 fragP->fr_offset, 1,
7454 reloc_type);
252b5132 7455 break;
fddf5b5b
AM		 7456
7457 default:
7458 BAD_CASE (fragP->fr_subtype);
7459 break;
252b5132
RH		 7460 }
7461 frag_wane (fragP);
ee7fcc42 7462 return fragP->fr_fix - old_fr_fix;
252b5132 7463 }
93c2a809 7464
93c2a809
AM		 7465 /* Guess size depending on current relax state. Initially the relax
7466 state will correspond to a short jump and we return 1, because
7467 the variable part of the frag (the branch offset) is one byte
7468 long. However, we can relax a section more than once and in that
7469 case we must either set fr_subtype back to the unrelaxed state,
7470 or return the value for the appropriate branch. */
7471 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7472}
7473
47926f60
KH		 7474/* Called after relax() is finished.
7475
7476 In: Address of frag.
7477 fr_type == rs_machine_dependent.
7478 fr_subtype is what the address relaxed to.
7479
7480 Out: Any fixSs and constants are set up.
7481 Caller will turn frag into a ".space 0". */
7482
252b5132
RH		 7483void
7484md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7485 bfd *abfd ATTRIBUTE_UNUSED;
7486 segT sec ATTRIBUTE_UNUSED;
29b0f896 7487 fragS *fragP;
252b5132 7488{
29b0f896 7489 unsigned char *opcode;
252b5132 7490 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7491 offsetT target_address;
7492 offsetT opcode_address;
252b5132 7493 unsigned int extension = 0;
847f7ad4 7494 offsetT displacement_from_opcode_start;
252b5132
RH		 7495
7496 opcode = (unsigned char *) fragP->fr_opcode;
7497
47926f60 7498 /* Address we want to reach in file space. */
252b5132 7499 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7500
47926f60 7501 /* Address opcode resides at in file space. */
252b5132
RH		 7502 opcode_address = fragP->fr_address + fragP->fr_fix;
7503
47926f60 7504 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7505 displacement_from_opcode_start = target_address - opcode_address;
7506
fddf5b5b 7507 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7508 {
47926f60
KH		 7509 /* Don't have to change opcode. */
7510 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7511 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7512 }
7513 else
7514 {
7515 if (no_cond_jump_promotion
7516 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7517 as_warn_where (fragP->fr_file, fragP->fr_line,
7518 _("long jump required"));
252b5132 7519
fddf5b5b
AM		 7520 switch (fragP->fr_subtype)
7521 {
7522 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7523 extension = 4; /* 1 opcode + 4 displacement */
7524 opcode[0] = 0xe9;
7525 where_to_put_displacement = &opcode[1];
7526 break;
252b5132 7527
fddf5b5b
AM		 7528 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7529 extension = 2; /* 1 opcode + 2 displacement */
7530 opcode[0] = 0xe9;
7531 where_to_put_displacement = &opcode[1];
7532 break;
252b5132 7533
fddf5b5b
AM		 7534 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7535 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7536 extension = 5; /* 2 opcode + 4 displacement */
7537 opcode[1] = opcode[0] + 0x10;
7538 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7539 where_to_put_displacement = &opcode[2];
7540 break;
252b5132 7541
fddf5b5b
AM		 7542 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7543 extension = 3; /* 2 opcode + 2 displacement */
7544 opcode[1] = opcode[0] + 0x10;
7545 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7546 where_to_put_displacement = &opcode[2];
7547 break;
252b5132 7548
fddf5b5b
AM		 7549 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7550 extension = 4;
7551 opcode[0] ^= 1;
7552 opcode[1] = 3;
7553 opcode[2] = 0xe9;
7554 where_to_put_displacement = &opcode[3];
7555 break;
7556
7557 default:
7558 BAD_CASE (fragP->fr_subtype);
7559 break;
7560 }
252b5132 7561 }
fddf5b5b 7562
7b81dfbb
AJ		 7563 /* If size if less then four we are sure that the operand fits,
7564 but if it's 4, then it could be that the displacement is larger
7565 then -/+ 2GB. */
7566 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7567 && object_64bit
7568 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7569 + ((addressT) 1 << 31))
7570 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7571 {
7572 as_bad_where (fragP->fr_file, fragP->fr_line,
7573 _("jump target out of range"));
7574 /* Make us emit 0. */
7575 displacement_from_opcode_start = extension;
7576 }
47926f60 7577 /* Now put displacement after opcode. */
252b5132
RH		 7578 md_number_to_chars ((char *) where_to_put_displacement,
7579 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7580 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7581 fragP->fr_fix += extension;
7582}
7583\f
252b5132
RH		 7584/* Apply a fixup (fixS) to segment data, once it has been determined
7585 by our caller that we have all the info we need to fix it up.
7586
7587 On the 386, immediates, displacements, and data pointers are all in
7588 the same (little-endian) format, so we don't need to care about which
7589 we are handling. */
7590
94f592af 7591void
55cf6793 7592md_apply_fix (fixP, valP, seg)
47926f60
KH		 7593 /* The fix we're to put in. */
7594 fixS *fixP;
47926f60 7595 /* Pointer to the value of the bits. */
c6682705 7596 valueT *valP;
47926f60
KH		 7597 /* Segment fix is from. */
7598 segT seg ATTRIBUTE_UNUSED;
252b5132 7599{
94f592af 7600 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7601 valueT value = *valP;
252b5132 7602
f86103b7 7603#if !defined (TE_Mach)
93382f6d
AM		 7604 if (fixP->fx_pcrel)
7605 {
7606 switch (fixP->fx_r_type)
7607 {
5865bb77
ILT		 7608 default:
7609 break;
7610
d6ab8113
JB		 7611 case BFD_RELOC_64:
7612 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7613 break;
93382f6d 7614 case BFD_RELOC_32:
ae8887b5 7615 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7616 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7617 break;
7618 case BFD_RELOC_16:
7619 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7620 break;
7621 case BFD_RELOC_8:
7622 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7623 break;
7624 }
7625 }
252b5132 7626
a161fe53 7627 if (fixP->fx_addsy != NULL
31312f95 7628 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7629 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7630 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7631 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7632 && !use_rela_relocations)
252b5132 7633 {
31312f95
AM		 7634 /* This is a hack. There should be a better way to handle this.
7635 This covers for the fact that bfd_install_relocation will
7636 subtract the current location (for partial_inplace, PC relative
7637 relocations); see more below. */
252b5132 7638#ifndef OBJ_AOUT
718ddfc0 7639 if (IS_ELF
252b5132
RH		 7640#ifdef TE_PE
7641 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7642#endif
7643 )
7644 value += fixP->fx_where + fixP->fx_frag->fr_address;
7645#endif
7646#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7647 if (IS_ELF)
252b5132 7648 {
6539b54b 7649 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7650
6539b54b 7651 if ((sym_seg == seg
2f66722d 7652 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7653 && sym_seg != absolute_section))
ae6063d4 7654 && !generic_force_reloc (fixP))
2f66722d
AM		 7655 {
7656 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7657 bfd_install_relocation subtracts them out again. I think
7658 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7659 it. FIXME. */
7660 value += fixP->fx_where + fixP->fx_frag->fr_address;
7661 }
252b5132
RH		 7662 }
7663#endif
7664#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7665 /* For some reason, the PE format does not store a
7666 section address offset for a PC relative symbol. */
7667 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7668 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7669 value += md_pcrel_from (fixP);
7670#endif
7671 }
7672
7673 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7674 and we must not disappoint it. */
252b5132 7675#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7676 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7677 switch (fixP->fx_r_type)
7678 {
7679 case BFD_RELOC_386_PLT32:
3e73aa7c 7680 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7681 /* Make the jump instruction point to the address of the operand. At
7682 runtime we merely add the offset to the actual PLT entry. */
7683 value = -4;
7684 break;
31312f95 7685
13ae64f3
JJ		 7686 case BFD_RELOC_386_TLS_GD:
7687 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7688 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7689 case BFD_RELOC_386_TLS_IE:
7690 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7691 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7692 case BFD_RELOC_X86_64_TLSGD:
7693 case BFD_RELOC_X86_64_TLSLD:
7694 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7695 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7696 value = 0; /* Fully resolved at runtime. No addend. */
7697 /* Fallthrough */
7698 case BFD_RELOC_386_TLS_LE:
7699 case BFD_RELOC_386_TLS_LDO_32:
7700 case BFD_RELOC_386_TLS_LE_32:
7701 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7702 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7703 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7704 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7705 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7706 break;
7707
67a4f2b7
AO		 7708 case BFD_RELOC_386_TLS_DESC_CALL:
7709 case BFD_RELOC_X86_64_TLSDESC_CALL:
7710 value = 0; /* Fully resolved at runtime. No addend. */
7711 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7712 fixP->fx_done = 0;
7713 return;
7714
00f7efb6
JJ		 7715 case BFD_RELOC_386_GOT32:
7716 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7717 value = 0; /* Fully resolved at runtime. No addend. */
7718 break;
47926f60
KH		 7719
7720 case BFD_RELOC_VTABLE_INHERIT:
7721 case BFD_RELOC_VTABLE_ENTRY:
7722 fixP->fx_done = 0;
94f592af 7723 return;
47926f60
KH		 7724
7725 default:
7726 break;
7727 }
7728#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7729 *valP = value;
f86103b7 7730#endif /* !defined (TE_Mach) */
3e73aa7c 7731
3e73aa7c 7732 /* Are we finished with this relocation now? */
c6682705 7733 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7734 fixP->fx_done = 1;
7735 else if (use_rela_relocations)
7736 {
7737 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7738 /* Remember value for tc_gen_reloc. */
7739 fixP->fx_addnumber = value;
3e73aa7c
JH		 7740 value = 0;
7741 }
f86103b7 7742
94f592af 7743 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7744}
252b5132 7745\f
252b5132 7746char *
499ac353 7747md_atof (int type, char *litP, int *sizeP)
252b5132 7748{
499ac353
NC		 7749 /* This outputs the LITTLENUMs in REVERSE order;
7750 in accord with the bigendian 386. */
7751 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7752}
7753\f
2d545b82 7754static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7755
252b5132 7756static char *
e3bb37b5 7757output_invalid (int c)
252b5132 7758{
3882b010 7759 if (ISPRINT (c))
f9f21a03
L		 7760 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7761 "'%c'", c);
252b5132 7762 else
f9f21a03 7763 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7764 "(0x%x)", (unsigned char) c);
252b5132
RH		 7765 return output_invalid_buf;
7766}
7767
af6bdddf 7768/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7769
7770static const reg_entry *
4d1bb795 7771parse_real_register (char *reg_string, char **end_op)
252b5132 7772{
af6bdddf
AM		 7773 char *s = reg_string;
7774 char *p;
252b5132
RH		 7775 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7776 const reg_entry *r;
7777
7778 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7779 if (*s == REGISTER_PREFIX)
7780 ++s;
7781
7782 if (is_space_char (*s))
7783 ++s;
7784
7785 p = reg_name_given;
af6bdddf 7786 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7787 {
7788 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7789 return (const reg_entry *) NULL;
7790 s++;
252b5132
RH		 7791 }
7792
6588847e
DN		 7793 /* For naked regs, make sure that we are not dealing with an identifier.
7794 This prevents confusing an identifier like `eax_var' with register
7795 `eax'. */
7796 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7797 return (const reg_entry *) NULL;
7798
af6bdddf 7799 *end_op = s;
252b5132
RH		 7800
7801 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7802
5f47d35b 7803 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7804 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7805 {
5f47d35b
AM		 7806 if (is_space_char (*s))
7807 ++s;
7808 if (*s == '(')
7809 {
af6bdddf 7810 ++s;
5f47d35b
AM		 7811 if (is_space_char (*s))
7812 ++s;
7813 if (*s >= '0' && *s <= '7')
7814 {
db557034 7815 int fpr = *s - '0';
af6bdddf 7816 ++s;
5f47d35b
AM		 7817 if (is_space_char (*s))
7818 ++s;
7819 if (*s == ')')
7820 {
7821 *end_op = s + 1;
db557034
AM		 7822 r = hash_find (reg_hash, "st(0)");
7823 know (r);
7824 return r + fpr;
5f47d35b 7825 }
5f47d35b 7826 }
47926f60 7827 /* We have "%st(" then garbage. */
5f47d35b
AM		 7828 return (const reg_entry *) NULL;
7829 }
7830 }
7831
a60de03c
JB		 7832 if (r == NULL || allow_pseudo_reg)
7833 return r;
7834
0dfbf9d7 7835 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7836 return (const reg_entry *) NULL;
7837
192dc9c6
JB		 7838 if ((r->reg_type.bitfield.reg32
7839 || r->reg_type.bitfield.sreg3
7840 || r->reg_type.bitfield.control
7841 || r->reg_type.bitfield.debug
7842 || r->reg_type.bitfield.test)
7843 && !cpu_arch_flags.bitfield.cpui386)
7844 return (const reg_entry *) NULL;
7845
7846 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7847 return (const reg_entry *) NULL;
7848
7849 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7850 return (const reg_entry *) NULL;
7851
40f12533
L		 7852 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7853 return (const reg_entry *) NULL;
7854
db51cc60 7855 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7856 if (!allow_index_reg
db51cc60
L		 7857 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7858 return (const reg_entry *) NULL;
7859
a60de03c
JB		 7860 if (((r->reg_flags & (RegRex64 | RegRex))
7861 || r->reg_type.bitfield.reg64)
40fb9820 7862 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7863 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7864 && flag_code != CODE_64BIT)
20f0a1fc 7865 return (const reg_entry *) NULL;
1ae00879 7866
b7240065
JB		 7867 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7868 return (const reg_entry *) NULL;
7869
252b5132
RH		 7870 return r;
7871}
4d1bb795
JB		 7872
7873/* REG_STRING starts *before* REGISTER_PREFIX. */
7874
7875static const reg_entry *
7876parse_register (char *reg_string, char **end_op)
7877{
7878 const reg_entry *r;
7879
7880 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7881 r = parse_real_register (reg_string, end_op);
7882 else
7883 r = NULL;
7884 if (!r)
7885 {
7886 char *save = input_line_pointer;
7887 char c;
7888 symbolS *symbolP;
7889
7890 input_line_pointer = reg_string;
7891 c = get_symbol_end ();
7892 symbolP = symbol_find (reg_string);
7893 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7894 {
7895 const expressionS *e = symbol_get_value_expression (symbolP);
7896
7897 know (e->X_op == O_register);
4eed87de 7898 know (e->X_add_number >= 0
c3fe08fa 7899 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7900 r = i386_regtab + e->X_add_number;
7901 *end_op = input_line_pointer;
7902 }
7903 *input_line_pointer = c;
7904 input_line_pointer = save;
7905 }
7906 return r;
7907}
7908
7909int
7910i386_parse_name (char *name, expressionS *e, char *nextcharP)
7911{
7912 const reg_entry *r;
7913 char *end = input_line_pointer;
7914
7915 *end = *nextcharP;
7916 r = parse_register (name, &input_line_pointer);
7917 if (r && end <= input_line_pointer)
7918 {
7919 *nextcharP = *input_line_pointer;
7920 *input_line_pointer = 0;
7921 e->X_op = O_register;
7922 e->X_add_number = r - i386_regtab;
7923 return 1;
7924 }
7925 input_line_pointer = end;
7926 *end = 0;
7927 return 0;
7928}
7929
7930void
7931md_operand (expressionS *e)
7932{
7933 if (*input_line_pointer == REGISTER_PREFIX)
7934 {
7935 char *end;
7936 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7937
7938 if (r)
7939 {
7940 e->X_op = O_register;
7941 e->X_add_number = r - i386_regtab;
7942 input_line_pointer = end;
7943 }
7944 }
7945}
7946
252b5132 7947\f
4cc782b5 7948#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7949const char *md_shortopts = "kVQ:sqn";
252b5132 7950#else
12b55ccc 7951const char *md_shortopts = "qn";
252b5132 7952#endif
6e0b89ee 7953
3e73aa7c 7954#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7955#define OPTION_64 (OPTION_MD_BASE + 1)
7956#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7957#define OPTION_MARCH (OPTION_MD_BASE + 3)
7958#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7959#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7960#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7961#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7962#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7963#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7964#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7965#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7966
99ad8390
NC		 7967struct option md_longopts[] =
7968{
3e73aa7c 7969 {"32", no_argument, NULL, OPTION_32},
99ad8390 7970#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7971 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7972#endif
b3b91714 7973 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7974 {"march", required_argument, NULL, OPTION_MARCH},
7975 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7976 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7977 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7978 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7979 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7980 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7981 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7982 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7983 {NULL, no_argument, NULL, 0}
7984};
7985size_t md_longopts_size = sizeof (md_longopts);
7986
7987int
9103f4f4 7988md_parse_option (int c, char *arg)
252b5132 7989{
9103f4f4 7990 unsigned int i;
6305a203 7991 char *arch, *next;
9103f4f4 7992
252b5132
RH		 7993 switch (c)
7994 {
12b55ccc
L		 7995 case 'n':
7996 optimize_align_code = 0;
7997 break;
7998
a38cf1db
AM		 7999 case 'q':
8000 quiet_warnings = 1;
252b5132
RH		 8001 break;
8002
8003#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 8004 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8005 should be emitted or not. FIXME: Not implemented. */
8006 case 'Q':
252b5132
RH		 8007 break;
8008
8009 /* -V: SVR4 argument to print version ID. */
8010 case 'V':
8011 print_version_id ();
8012 break;
8013
a38cf1db
AM		 8014 /* -k: Ignore for FreeBSD compatibility. */
8015 case 'k':
252b5132 8016 break;
4cc782b5
ILT		 8017
8018 case 's':
8019 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8020 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8021 break;
99ad8390
NC		 8022#endif
8023#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 8024 case OPTION_64:
8025 {
8026 const char **list, **l;
8027
3e73aa7c
JH		 8028 list = bfd_target_list ();
8029 for (l = list; *l != NULL; l++)
8620418b 8030 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8031 || strcmp (*l, "coff-x86-64") == 0
8032 || strcmp (*l, "pe-x86-64") == 0
8033 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8034 {
8035 default_arch = "x86_64";
8036 break;
8037 }
3e73aa7c 8038 if (*l == NULL)
6e0b89ee 8039 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8040 free (list);
8041 }
8042 break;
8043#endif
252b5132 8044
6e0b89ee
AM		 8045 case OPTION_32:
8046 default_arch = "i386";
8047 break;
8048
b3b91714
AM		 8049 case OPTION_DIVIDE:
8050#ifdef SVR4_COMMENT_CHARS
8051 {
8052 char *n, *t;
8053 const char *s;
8054
8055 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8056 t = n;
8057 for (s = i386_comment_chars; *s != '\0'; s++)
8058 if (*s != '/')
8059 *t++ = *s;
8060 *t = '\0';
8061 i386_comment_chars = n;
8062 }
8063#endif
8064 break;
8065
9103f4f4 8066 case OPTION_MARCH:
6305a203
L		 8067 arch = xstrdup (arg);
8068 do
9103f4f4 8069 {
6305a203
L		 8070 if (*arch == '.')
8071 as_fatal (_("Invalid -march= option: `%s'"), arg);
8072 next = strchr (arch, '+');
8073 if (next)
8074 *next++ = '\0';
8075 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8076 {
6305a203 8077 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8078 {
6305a203
L		 8079 /* Processor. */
8080 cpu_arch_name = cpu_arch[i].name;
8081 cpu_sub_arch_name = NULL;
8082 cpu_arch_flags = cpu_arch[i].flags;
8083 cpu_arch_isa = cpu_arch[i].type;
8084 cpu_arch_isa_flags = cpu_arch[i].flags;
8085 if (!cpu_arch_tune_set)
8086 {
8087 cpu_arch_tune = cpu_arch_isa;
8088 cpu_arch_tune_flags = cpu_arch_isa_flags;
8089 }
8090 break;
8091 }
8092 else if (*cpu_arch [i].name == '.'
8093 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8094 {
8095 /* ISA entension. */
8096 i386_cpu_flags flags;
8097 flags = cpu_flags_or (cpu_arch_flags,
8098 cpu_arch[i].flags);
0dfbf9d7 8099 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8100 {
8101 if (cpu_sub_arch_name)
8102 {
8103 char *name = cpu_sub_arch_name;
8104 cpu_sub_arch_name = concat (name,
8105 cpu_arch[i].name,
1bf57e9f 8106 (const char *) NULL);
6305a203
L		 8107 free (name);
8108 }
8109 else
8110 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8111 cpu_arch_flags = flags;
8112 }
8113 break;
ccc9c027 8114 }
9103f4f4 8115 }
6305a203
L		 8116
8117 if (i >= ARRAY_SIZE (cpu_arch))
8118 as_fatal (_("Invalid -march= option: `%s'"), arg);
8119
8120 arch = next;
9103f4f4 8121 }
6305a203 8122 while (next != NULL );
9103f4f4
L		 8123 break;
8124
8125 case OPTION_MTUNE:
8126 if (*arg == '.')
8127 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8128 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8129 {
8130 if (strcmp (arg, cpu_arch [i].name) == 0)
8131 {
ccc9c027 8132 cpu_arch_tune_set = 1;
9103f4f4
L		 8133 cpu_arch_tune = cpu_arch [i].type;
8134 cpu_arch_tune_flags = cpu_arch[i].flags;
8135 break;
8136 }
8137 }
8138 if (i >= ARRAY_SIZE (cpu_arch))
8139 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8140 break;
8141
1efbbeb4
L		 8142 case OPTION_MMNEMONIC:
8143 if (strcasecmp (arg, "att") == 0)
8144 intel_mnemonic = 0;
8145 else if (strcasecmp (arg, "intel") == 0)
8146 intel_mnemonic = 1;
8147 else
8148 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8149 break;
8150
8151 case OPTION_MSYNTAX:
8152 if (strcasecmp (arg, "att") == 0)
8153 intel_syntax = 0;
8154 else if (strcasecmp (arg, "intel") == 0)
8155 intel_syntax = 1;
8156 else
8157 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8158 break;
8159
8160 case OPTION_MINDEX_REG:
8161 allow_index_reg = 1;
8162 break;
8163
8164 case OPTION_MNAKED_REG:
8165 allow_naked_reg = 1;
8166 break;
8167
8168 case OPTION_MOLD_GCC:
8169 old_gcc = 1;
1efbbeb4
L		 8170 break;
8171
c0f3af97
L		 8172 case OPTION_MSSE2AVX:
8173 sse2avx = 1;
8174 break;
8175
daf50ae7
L		 8176 case OPTION_MSSE_CHECK:
8177 if (strcasecmp (arg, "error") == 0)
8178 sse_check = sse_check_error;
8179 else if (strcasecmp (arg, "warning") == 0)
8180 sse_check = sse_check_warning;
8181 else if (strcasecmp (arg, "none") == 0)
8182 sse_check = sse_check_none;
8183 else
8184 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8185 break;
8186
252b5132
RH		 8187 default:
8188 return 0;
8189 }
8190 return 1;
8191}
8192
8193void
8194md_show_usage (stream)
8195 FILE *stream;
8196{
4cc782b5
ILT		 8197#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8198 fprintf (stream, _("\
a38cf1db
AM		 8199 -Q ignored\n\
8200 -V print assembler version number\n\
b3b91714
AM		 8201 -k ignored\n"));
8202#endif
8203 fprintf (stream, _("\
12b55ccc 8204 -n Do not optimize code alignment\n\
b3b91714
AM		 8205 -q quieten some warnings\n"));
8206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8207 fprintf (stream, _("\
a38cf1db 8208 -s ignored\n"));
b3b91714 8209#endif
751d281c
L		 8210#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8211 fprintf (stream, _("\
8212 --32/--64 generate 32bit/64bit code\n"));
8213#endif
b3b91714
AM		 8214#ifdef SVR4_COMMENT_CHARS
8215 fprintf (stream, _("\
8216 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8217#else
8218 fprintf (stream, _("\
b3b91714 8219 --divide ignored\n"));
4cc782b5 8220#endif
9103f4f4 8221 fprintf (stream, _("\
6305a203
L		 8222 -march=CPU[,+EXTENSION...]\n\
8223 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8224 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8225 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8226 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8227 generic32, generic64\n\
599121aa
L		 8228 EXTENSION is combination of:\n\
8229 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695
L		 8230 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8231 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
6305a203 8232 fprintf (stream, _("\
2cb4f3d5
L		 8233 -mtune=CPU optimize for CPU, CPU is one of:\n\
8234 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8235 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8236 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8237 generic32, generic64\n"));
ba104c83 8238 fprintf (stream, _("\
c0f3af97
L		 8239 -msse2avx encode SSE instructions with VEX prefix\n"));
8240 fprintf (stream, _("\
daf50ae7
L		 8241 -msse-check=[none|error|warning]\n\
8242 check SSE instructions\n"));
8243 fprintf (stream, _("\
ba104c83
L		 8244 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8245 fprintf (stream, _("\
8246 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8247 fprintf (stream, _("\
8248 -mindex-reg support pseudo index registers\n"));
8249 fprintf (stream, _("\
8250 -mnaked-reg don't require `%%' prefix for registers\n"));
8251 fprintf (stream, _("\
8252 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8253}
8254
3e73aa7c 8255#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8256 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8257
8258/* Pick the target format to use. */
8259
47926f60 8260const char *
e3bb37b5 8261i386_target_format (void)
252b5132 8262{
3e73aa7c 8263 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8264 {
8265 set_code_flag (CODE_64BIT);
0dfbf9d7 8266 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8267 {
8268 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8269 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8270 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8271 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8272 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8273 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8274 cpu_arch_isa_flags.bitfield.cpup4 = 1;
8275 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8276 cpu_arch_isa_flags.bitfield.cpusse = 1;
8277 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8278 }
0dfbf9d7 8279 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8280 {
8281 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8282 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8283 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8284 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8285 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8286 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8287 cpu_arch_tune_flags.bitfield.cpup4 = 1;
8288 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8289 cpu_arch_tune_flags.bitfield.cpusse = 1;
8290 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8291 }
9103f4f4 8292 }
3e73aa7c 8293 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8294 {
8295 set_code_flag (CODE_32BIT);
0dfbf9d7 8296 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8297 {
8298 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8299 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8300 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8301 }
0dfbf9d7 8302 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8303 {
8304 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8305 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8306 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8307 }
9103f4f4 8308 }
3e73aa7c
JH		 8309 else
8310 as_fatal (_("Unknown architecture"));
252b5132
RH		 8311 switch (OUTPUT_FLAVOR)
8312 {
872ce6ff
L		 8313#ifdef TE_PEP
8314 case bfd_target_coff_flavour:
8315 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
8316 break;
8317#endif
4c63da97
AM		 8318#ifdef OBJ_MAYBE_AOUT
8319 case bfd_target_aout_flavour:
47926f60 8320 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8321#endif
8322#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8323 case bfd_target_coff_flavour:
8324 return "coff-i386";
4c63da97 8325#endif
3e73aa7c 8326#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8327 case bfd_target_elf_flavour:
3e73aa7c 8328 {
e5cb08ac 8329 if (flag_code == CODE_64BIT)
4fa24527
JB		 8330 {
8331 object_64bit = 1;
8332 use_rela_relocations = 1;
8333 }
9d7cbccd 8334 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8335 }
4c63da97 8336#endif
252b5132
RH		 8337 default:
8338 abort ();
8339 return NULL;
8340 }
8341}
8342
47926f60 8343#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8344
8345#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8346void
8347i386_elf_emit_arch_note (void)
a847613f 8348{
718ddfc0 8349 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8350 {
8351 char *p;
8352 asection *seg = now_seg;
8353 subsegT subseg = now_subseg;
8354 Elf_Internal_Note i_note;
8355 Elf_External_Note e_note;
8356 asection *note_secp;
8357 int len;
8358
8359 /* Create the .note section. */
8360 note_secp = subseg_new (".note", 0);
8361 bfd_set_section_flags (stdoutput,
8362 note_secp,
8363 SEC_HAS_CONTENTS | SEC_READONLY);
8364
8365 /* Process the arch string. */
8366 len = strlen (cpu_arch_name);
8367
8368 i_note.namesz = len + 1;
8369 i_note.descsz = 0;
8370 i_note.type = NT_ARCH;
8371 p = frag_more (sizeof (e_note.namesz));
8372 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8373 p = frag_more (sizeof (e_note.descsz));
8374 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8375 p = frag_more (sizeof (e_note.type));
8376 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8377 p = frag_more (len + 1);
8378 strcpy (p, cpu_arch_name);
8379
8380 frag_align (2, 0, 0);
8381
8382 subseg_set (seg, subseg);
8383 }
8384}
8385#endif
252b5132 8386\f
252b5132
RH		 8387symbolS *
8388md_undefined_symbol (name)
8389 char *name;
8390{
18dc2407
ILT		 8391 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8392 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8393 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8394 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8395 {
8396 if (!GOT_symbol)
8397 {
8398 if (symbol_find (name))
8399 as_bad (_("GOT already in symbol table"));
8400 GOT_symbol = symbol_new (name, undefined_section,
8401 (valueT) 0, &zero_address_frag);
8402 };
8403 return GOT_symbol;
8404 }
252b5132
RH		 8405 return 0;
8406}
8407
8408/* Round up a section size to the appropriate boundary. */
47926f60 8409
252b5132
RH		 8410valueT
8411md_section_align (segment, size)
ab9da554 8412 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8413 valueT size;
8414{
4c63da97
AM		 8415#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8416 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8417 {
8418 /* For a.out, force the section size to be aligned. If we don't do
8419 this, BFD will align it for us, but it will not write out the
8420 final bytes of the section. This may be a bug in BFD, but it is
8421 easier to fix it here since that is how the other a.out targets
8422 work. */
8423 int align;
8424
8425 align = bfd_get_section_alignment (stdoutput, segment);
8426 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8427 }
252b5132
RH		 8428#endif
8429
8430 return size;
8431}
8432
8433/* On the i386, PC-relative offsets are relative to the start of the
8434 next instruction. That is, the address of the offset, plus its
8435 size, since the offset is always the last part of the insn. */
8436
8437long
e3bb37b5 8438md_pcrel_from (fixS *fixP)
252b5132
RH		 8439{
8440 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8441}
8442
8443#ifndef I386COFF
8444
8445static void
e3bb37b5 8446s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8447{
29b0f896 8448 int temp;
252b5132 8449
8a75718c
JB		 8450#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8451 if (IS_ELF)
8452 obj_elf_section_change_hook ();
8453#endif
252b5132
RH		 8454 temp = get_absolute_expression ();
8455 subseg_set (bss_section, (subsegT) temp);
8456 demand_empty_rest_of_line ();
8457}
8458
8459#endif
8460
252b5132 8461void
e3bb37b5 8462i386_validate_fix (fixS *fixp)
252b5132
RH		 8463{
8464 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8465 {
23df1078
JH		 8466 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8467 {
4fa24527 8468 if (!object_64bit)
23df1078
JH		 8469 abort ();
8470 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8471 }
8472 else
8473 {
4fa24527 8474 if (!object_64bit)
d6ab8113
JB		 8475 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8476 else
8477 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8478 }
252b5132
RH		 8479 fixp->fx_subsy = 0;
8480 }
8481}
8482
252b5132
RH		 8483arelent *
8484tc_gen_reloc (section, fixp)
ab9da554 8485 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8486 fixS *fixp;
8487{
8488 arelent *rel;
8489 bfd_reloc_code_real_type code;
8490
8491 switch (fixp->fx_r_type)
8492 {
3e73aa7c
JH		 8493 case BFD_RELOC_X86_64_PLT32:
8494 case BFD_RELOC_X86_64_GOT32:
8495 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8496 case BFD_RELOC_386_PLT32:
8497 case BFD_RELOC_386_GOT32:
8498 case BFD_RELOC_386_GOTOFF:
8499 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8500 case BFD_RELOC_386_TLS_GD:
8501 case BFD_RELOC_386_TLS_LDM:
8502 case BFD_RELOC_386_TLS_LDO_32:
8503 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8504 case BFD_RELOC_386_TLS_IE:
8505 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8506 case BFD_RELOC_386_TLS_LE_32:
8507 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8508 case BFD_RELOC_386_TLS_GOTDESC:
8509 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8510 case BFD_RELOC_X86_64_TLSGD:
8511 case BFD_RELOC_X86_64_TLSLD:
8512 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8513 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8514 case BFD_RELOC_X86_64_GOTTPOFF:
8515 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8516 case BFD_RELOC_X86_64_TPOFF64:
8517 case BFD_RELOC_X86_64_GOTOFF64:
8518 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8519 case BFD_RELOC_X86_64_GOT64:
8520 case BFD_RELOC_X86_64_GOTPCREL64:
8521 case BFD_RELOC_X86_64_GOTPC64:
8522 case BFD_RELOC_X86_64_GOTPLT64:
8523 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8524 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8525 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8526 case BFD_RELOC_RVA:
8527 case BFD_RELOC_VTABLE_ENTRY:
8528 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8529#ifdef TE_PE
8530 case BFD_RELOC_32_SECREL:
8531#endif
252b5132
RH		 8532 code = fixp->fx_r_type;
8533 break;
dbbaec26
L		 8534 case BFD_RELOC_X86_64_32S:
8535 if (!fixp->fx_pcrel)
8536 {
8537 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8538 code = fixp->fx_r_type;
8539 break;
8540 }
252b5132 8541 default:
93382f6d 8542 if (fixp->fx_pcrel)
252b5132 8543 {
93382f6d
AM		 8544 switch (fixp->fx_size)
8545 {
8546 default:
b091f402
AM		 8547 as_bad_where (fixp->fx_file, fixp->fx_line,
8548 _("can not do %d byte pc-relative relocation"),
8549 fixp->fx_size);
93382f6d
AM		 8550 code = BFD_RELOC_32_PCREL;
8551 break;
8552 case 1: code = BFD_RELOC_8_PCREL; break;
8553 case 2: code = BFD_RELOC_16_PCREL; break;
8554 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8555#ifdef BFD64
8556 case 8: code = BFD_RELOC_64_PCREL; break;
8557#endif
93382f6d
AM		 8558 }
8559 }
8560 else
8561 {
8562 switch (fixp->fx_size)
8563 {
8564 default:
b091f402
AM		 8565 as_bad_where (fixp->fx_file, fixp->fx_line,
8566 _("can not do %d byte relocation"),
8567 fixp->fx_size);
93382f6d
AM		 8568 code = BFD_RELOC_32;
8569 break;
8570 case 1: code = BFD_RELOC_8; break;
8571 case 2: code = BFD_RELOC_16; break;
8572 case 4: code = BFD_RELOC_32; break;
937149dd 8573#ifdef BFD64
3e73aa7c 8574 case 8: code = BFD_RELOC_64; break;
937149dd 8575#endif
93382f6d 8576 }
252b5132
RH		 8577 }
8578 break;
8579 }
252b5132 8580
d182319b
JB		 8581 if ((code == BFD_RELOC_32
8582 || code == BFD_RELOC_32_PCREL
8583 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8584 && GOT_symbol
8585 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8586 {
4fa24527 8587 if (!object_64bit)
d6ab8113
JB		 8588 code = BFD_RELOC_386_GOTPC;
8589 else
8590 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8591 }
7b81dfbb
AJ		 8592 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8593 && GOT_symbol
8594 && fixp->fx_addsy == GOT_symbol)
8595 {
8596 code = BFD_RELOC_X86_64_GOTPC64;
8597 }
252b5132
RH		 8598
8599 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8600 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8601 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8602
8603 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8604
3e73aa7c
JH		 8605 if (!use_rela_relocations)
8606 {
8607 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8608 vtable entry to be used in the relocation's section offset. */
8609 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8610 rel->address = fixp->fx_offset;
252b5132 8611
c6682705 8612 rel->addend = 0;
3e73aa7c
JH		 8613 }
8614 /* Use the rela in 64bit mode. */
252b5132 8615 else
3e73aa7c 8616 {
062cd5e7
AS		 8617 if (!fixp->fx_pcrel)
8618 rel->addend = fixp->fx_offset;
8619 else
8620 switch (code)
8621 {
8622 case BFD_RELOC_X86_64_PLT32:
8623 case BFD_RELOC_X86_64_GOT32:
8624 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8625 case BFD_RELOC_X86_64_TLSGD:
8626 case BFD_RELOC_X86_64_TLSLD:
8627 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8628 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8629 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8630 rel->addend = fixp->fx_offset - fixp->fx_size;
8631 break;
8632 default:
8633 rel->addend = (section->vma
8634 - fixp->fx_size
8635 + fixp->fx_addnumber
8636 + md_pcrel_from (fixp));
8637 break;
8638 }
3e73aa7c
JH		 8639 }
8640
252b5132
RH		 8641 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8642 if (rel->howto == NULL)
8643 {
8644 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8645 _("cannot represent relocation type %s"),
252b5132
RH		 8646 bfd_get_reloc_code_name (code));
8647 /* Set howto to a garbage value so that we can keep going. */
8648 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8649 assert (rel->howto != NULL);
8650 }
8651
8652 return rel;
8653}
8654
64a0c779
DN		 8655\f
8656/* Parse operands using Intel syntax. This implements a recursive descent
8657 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8658 Programmer's Guide.
8659
8660 FIXME: We do not recognize the full operand grammar defined in the MASM
8661 documentation. In particular, all the structure/union and
8662 high-level macro operands are missing.
8663
8664 Uppercase words are terminals, lower case words are non-terminals.
8665 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8666 bars '|' denote choices. Most grammar productions are implemented in
8667 functions called 'intel_<production>'.
8668
8669 Initial production is 'expr'.
8670
9306ca4a 8671 addOp + | -
64a0c779
DN		 8672
8673 alpha [a-zA-Z]
8674
9306ca4a
JB		 8675 binOp & | AND | \| | OR | ^ | XOR
8676
64a0c779
DN		 8677 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8678
8679 constant digits [[ radixOverride ]]
8680
c0f3af97 8681 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8682
8683 digits decdigit
b77a7acd
AJ		 8684 | digits decdigit
8685 | digits hexdigit
64a0c779
DN		 8686
8687 decdigit [0-9]
8688
9306ca4a
JB		 8689 e04 e04 addOp e05
8690 | e05
8691
8692 e05 e05 binOp e06
b77a7acd 8693 | e06
64a0c779
DN		 8694
8695 e06 e06 mulOp e09
b77a7acd 8696 | e09
64a0c779
DN		 8697
8698 e09 OFFSET e10
a724f0f4
JB		 8699 | SHORT e10
8700 | + e10
8701 | - e10
9306ca4a
JB		 8702 | ~ e10
8703 | NOT e10
64a0c779
DN		 8704 | e09 PTR e10
8705 | e09 : e10
8706 | e10
8707
8708 e10 e10 [ expr ]
b77a7acd 8709 | e11
64a0c779
DN		 8710
8711 e11 ( expr )
b77a7acd 8712 | [ expr ]
64a0c779
DN		 8713 | constant
8714 | dataType
8715 | id
8716 | $
8717 | register
8718
a724f0f4 8719 => expr expr cmpOp e04
9306ca4a 8720 | e04
64a0c779
DN		 8721
8722 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8723 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8724
8725 hexdigit a | b | c | d | e | f
b77a7acd 8726 | A | B | C | D | E | F
64a0c779
DN		 8727
8728 id alpha
b77a7acd 8729 | id alpha
64a0c779
DN		 8730 | id decdigit
8731
9306ca4a 8732 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8733
8734 quote " | '
8735
8736 register specialRegister
b77a7acd 8737 | gpRegister
64a0c779
DN		 8738 | byteRegister
8739
8740 segmentRegister CS | DS | ES | FS | GS | SS
8741
9306ca4a 8742 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8743 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8744 | TR3 | TR4 | TR5 | TR6 | TR7
8745
64a0c779
DN		 8746 We simplify the grammar in obvious places (e.g., register parsing is
8747 done by calling parse_register) and eliminate immediate left recursion
8748 to implement a recursive-descent parser.
8749
a724f0f4
JB		 8750 expr e04 expr'
8751
8752 expr' cmpOp e04 expr'
8753 | Empty
9306ca4a
JB		 8754
8755 e04 e05 e04'
8756
8757 e04' addOp e05 e04'
8758 | Empty
64a0c779
DN		 8759
8760 e05 e06 e05'
8761
9306ca4a 8762 e05' binOp e06 e05'
b77a7acd 8763 | Empty
64a0c779
DN		 8764
8765 e06 e09 e06'
8766
8767 e06' mulOp e09 e06'
b77a7acd 8768 | Empty
64a0c779
DN		 8769
8770 e09 OFFSET e10 e09'
a724f0f4
JB		 8771 | SHORT e10'
8772 | + e10'
8773 | - e10'
8774 | ~ e10'
8775 | NOT e10'
b77a7acd 8776 | e10 e09'
64a0c779
DN		 8777
8778 e09' PTR e10 e09'
b77a7acd 8779 | : e10 e09'
64a0c779
DN		 8780 | Empty
8781
8782 e10 e11 e10'
8783
8784 e10' [ expr ] e10'
b77a7acd 8785 | Empty
64a0c779
DN		 8786
8787 e11 ( expr )
b77a7acd 8788 | [ expr ]
64a0c779
DN		 8789 | BYTE
8790 | WORD
8791 | DWORD
9306ca4a 8792 | FWORD
64a0c779 8793 | QWORD
9306ca4a
JB		 8794 | TBYTE
8795 | OWORD
8796 | XMMWORD
c0f3af97 8797 | YMMWORD
64a0c779
DN		 8798 | .
8799 | $
8800 | register
8801 | id
8802 | constant */
8803
8804/* Parsing structure for the intel syntax parser. Used to implement the
8805 semantic actions for the operand grammar. */
8806struct intel_parser_s
8807 {
8808 char *op_string; /* The string being parsed. */
8809 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8810 int op_modifier; /* Operand modifier. */
64a0c779 8811 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8812 int in_offset; /* >=1 if parsing operand of offset. */
8813 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8814 const reg_entry *reg; /* Last register reference found. */
8815 char *disp; /* Displacement string being built. */
a724f0f4 8816 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8817 };
8818
8819static struct intel_parser_s intel_parser;
8820
8821/* Token structure for parsing intel syntax. */
8822struct intel_token
8823 {
8824 int code; /* Token code. */
8825 const reg_entry *reg; /* Register entry for register tokens. */
8826 char *str; /* String representation. */
8827 };
8828
8829static struct intel_token cur_token, prev_token;
8830
50705ef4
AM		 8831/* Token codes for the intel parser. Since T_SHORT is already used
8832 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8833#define T_NIL -1
8834#define T_CONST 1
8835#define T_REG 2
8836#define T_BYTE 3
8837#define T_WORD 4
9306ca4a
JB		 8838#define T_DWORD 5
8839#define T_FWORD 6
8840#define T_QWORD 7
8841#define T_TBYTE 8
8842#define T_XMMWORD 9
50705ef4 8843#undef T_SHORT
9306ca4a
JB		 8844#define T_SHORT 10
8845#define T_OFFSET 11
8846#define T_PTR 12
8847#define T_ID 13
8848#define T_SHL 14
8849#define T_SHR 15
c0f3af97 8850#define T_YMMWORD 16
64a0c779
DN		 8851
8852/* Prototypes for intel parser functions. */
e3bb37b5
L		 8853static int intel_match_token (int);
8854static void intel_putback_token (void);
8855static void intel_get_token (void);
8856static int intel_expr (void);
8857static int intel_e04 (void);
8858static int intel_e05 (void);
8859static int intel_e06 (void);
8860static int intel_e09 (void);
8861static int intel_e10 (void);
8862static int intel_e11 (void);
64a0c779 8863
64a0c779 8864static int
e3bb37b5 8865i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8866{
8867 int ret;
8868 char *p;
fc0763e6
JB		 8869 const reg_entry *final_base = i.base_reg;
8870 const reg_entry *final_index = i.index_reg;
64a0c779 8871
a724f0f4
JB		 8872 p = intel_parser.op_string = xstrdup (operand_string);
8873 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8874
8875 for (;;)
64a0c779 8876 {
a724f0f4
JB		 8877 /* Initialize token holders. */
8878 cur_token.code = prev_token.code = T_NIL;
8879 cur_token.reg = prev_token.reg = NULL;
8880 cur_token.str = prev_token.str = NULL;
8881
8882 /* Initialize parser structure. */
8883 intel_parser.got_a_float = got_a_float;
8884 intel_parser.op_modifier = 0;
8885 intel_parser.is_mem = 0;
8886 intel_parser.in_offset = 0;
8887 intel_parser.in_bracket = 0;
8888 intel_parser.reg = NULL;
8889 intel_parser.disp[0] = '\0';
8890 intel_parser.next_operand = NULL;
8891
fc0763e6
JB		 8892 i.base_reg = NULL;
8893 i.index_reg = NULL;
8894
a724f0f4
JB		 8895 /* Read the first token and start the parser. */
8896 intel_get_token ();
8897 ret = intel_expr ();
8898
8899 if (!ret)
8900 break;
8901
9306ca4a
JB		 8902 if (cur_token.code != T_NIL)
8903 {
8904 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8905 current_templates->start->name, cur_token.str);
8906 ret = 0;
8907 }
64a0c779
DN		 8908 /* If we found a memory reference, hand it over to i386_displacement
8909 to fill in the rest of the operand fields. */
9306ca4a 8910 else if (intel_parser.is_mem)
64a0c779
DN		 8911 {
8912 if ((i.mem_operands == 1
40fb9820 8913 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8914 || i.mem_operands == 2)
8915 {
8916 as_bad (_("too many memory references for '%s'"),
8917 current_templates->start->name);
8918 ret = 0;
8919 }
8920 else
8921 {
8922 char *s = intel_parser.disp;
64a0c779 8923
a724f0f4
JB		 8924 if (!quiet_warnings && intel_parser.is_mem < 0)
8925 /* See the comments in intel_bracket_expr. */
8926 as_warn (_("Treating `%s' as memory reference"), operand_string);
8927
64a0c779
DN		 8928 /* Add the displacement expression. */
8929 if (*s != '\0')
a4622f40
AM		 8930 ret = i386_displacement (s, s + strlen (s));
8931 if (ret)
a724f0f4
JB		 8932 {
8933 /* Swap base and index in 16-bit memory operands like
8934 [si+bx]. Since i386_index_check is also used in AT&T
8935 mode we have to do that here. */
8936 if (i.base_reg
8937 && i.index_reg
40fb9820
L		 8938 && i.base_reg->reg_type.bitfield.reg16
8939 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8940 && i.base_reg->reg_num >= 6
8941 && i.index_reg->reg_num < 6)
8942 {
8943 const reg_entry *base = i.index_reg;
8944
8945 i.index_reg = i.base_reg;
8946 i.base_reg = base;
8947 }
8948 ret = i386_index_check (operand_string);
8949 }
fc0763e6
JB		 8950 if (ret)
8951 {
8952 i.types[this_operand].bitfield.mem = 1;
8953 i.mem_operands++;
8954 }
64a0c779
DN		 8955 }
8956 }
8957
8958 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8959 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8960 || intel_parser.reg == NULL)
b7240065
JB		 8961 {
8962 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8963 {
8964 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8965 as_warn (_("Segment override ignored"));
8966 i.seg[i.mem_operands] = NULL;
8967 }
8968 ret = i386_immediate (intel_parser.disp);
8969 }
a724f0f4 8970
fc0763e6
JB		 8971 if (!final_base && !final_index)
8972 {
8973 final_base = i.base_reg;
8974 final_index = i.index_reg;
8975 }
8976
a724f0f4 8977 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8978 ret = 0;
a724f0f4
JB		 8979 if (!ret || !intel_parser.next_operand)
8980 break;
8981 intel_parser.op_string = intel_parser.next_operand;
8982 this_operand = i.operands++;
7d5e4556 8983 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8984 }
8985
8986 free (p);
8987 free (intel_parser.disp);
8988
fc0763e6
JB		 8989 if (final_base || final_index)
8990 {
8991 i.base_reg = final_base;
8992 i.index_reg = final_index;
8993 }
8994
64a0c779
DN		 8995 return ret;
8996}
8997
a724f0f4
JB		 8998#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8999
9000/* expr e04 expr'
9001
9002 expr' cmpOp e04 expr'
9003 | Empty */
64a0c779 9004static int
e3bb37b5 9005intel_expr (void)
64a0c779 9006{
a724f0f4
JB		 9007 /* XXX Implement the comparison operators. */
9008 return intel_e04 ();
9306ca4a
JB		 9009}
9010
a724f0f4 9011/* e04 e05 e04'
9306ca4a 9012
a724f0f4 9013 e04' addOp e05 e04'
9306ca4a
JB		 9014 | Empty */
9015static int
e3bb37b5 9016intel_e04 (void)
9306ca4a 9017{
a724f0f4 9018 int nregs = -1;
9306ca4a 9019
a724f0f4 9020 for (;;)
9306ca4a 9021 {
a724f0f4
JB		 9022 if (!intel_e05())
9023 return 0;
9306ca4a 9024
a724f0f4
JB		 9025 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9026 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 9027
a724f0f4
JB		 9028 if (cur_token.code == '+')
9029 nregs = -1;
9030 else if (cur_token.code == '-')
9031 nregs = NUM_ADDRESS_REGS;
9032 else
9033 return 1;
64a0c779 9034
a724f0f4
JB		 9035 strcat (intel_parser.disp, cur_token.str);
9036 intel_match_token (cur_token.code);
9037 }
64a0c779
DN		 9038}
9039
64a0c779
DN		 9040/* e05 e06 e05'
9041
9306ca4a 9042 e05' binOp e06 e05'
64a0c779
DN		 9043 | Empty */
9044static int
e3bb37b5 9045intel_e05 (void)
64a0c779 9046{
a724f0f4 9047 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9048
a724f0f4 9049 for (;;)
64a0c779 9050 {
a724f0f4
JB		 9051 if (!intel_e06())
9052 return 0;
9053
4eed87de
AM		 9054 if (cur_token.code == '&'
9055 || cur_token.code == '|'
9056 || cur_token.code == '^')
a724f0f4
JB		 9057 {
9058 char str[2];
9059
9060 str[0] = cur_token.code;
9061 str[1] = 0;
9062 strcat (intel_parser.disp, str);
9063 }
9064 else
9065 break;
9306ca4a 9066
64a0c779
DN		 9067 intel_match_token (cur_token.code);
9068
a724f0f4
JB		 9069 if (nregs < 0)
9070 nregs = ~nregs;
64a0c779 9071 }
a724f0f4
JB		 9072 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9073 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
9074 return 1;
4a1805b1 9075}
64a0c779
DN		 9076
9077/* e06 e09 e06'
9078
9079 e06' mulOp e09 e06'
b77a7acd 9080 | Empty */
64a0c779 9081static int
e3bb37b5 9082intel_e06 (void)
64a0c779 9083{
a724f0f4 9084 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9085
a724f0f4 9086 for (;;)
64a0c779 9087 {
a724f0f4
JB		 9088 if (!intel_e09())
9089 return 0;
9306ca4a 9090
4eed87de
AM		 9091 if (cur_token.code == '*'
9092 || cur_token.code == '/'
9093 || cur_token.code == '%')
a724f0f4
JB		 9094 {
9095 char str[2];
9306ca4a 9096
a724f0f4
JB		 9097 str[0] = cur_token.code;
9098 str[1] = 0;
9099 strcat (intel_parser.disp, str);
9100 }
9101 else if (cur_token.code == T_SHL)
9102 strcat (intel_parser.disp, "<<");
9103 else if (cur_token.code == T_SHR)
9104 strcat (intel_parser.disp, ">>");
9105 else
9106 break;
9306ca4a 9107
64e74474 9108 intel_match_token (cur_token.code);
64a0c779 9109
a724f0f4
JB		 9110 if (nregs < 0)
9111 nregs = ~nregs;
64a0c779 9112 }
a724f0f4
JB		 9113 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9114 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9115 return 1;
64a0c779
DN		 9116}
9117
a724f0f4
JB		 9118/* e09 OFFSET e09
9119 | SHORT e09
9120 | + e09
9121 | - e09
9122 | ~ e09
9123 | NOT e09
9306ca4a
JB		 9124 | e10 e09'
9125
64a0c779 9126 e09' PTR e10 e09'
b77a7acd 9127 | : e10 e09'
64a0c779
DN		 9128 | Empty */
9129static int
e3bb37b5 9130intel_e09 (void)
64a0c779 9131{
a724f0f4
JB		 9132 int nregs = ~NUM_ADDRESS_REGS;
9133 int in_offset = 0;
9134
9135 for (;;)
64a0c779 9136 {
a724f0f4
JB		 9137 /* Don't consume constants here. */
9138 if (cur_token.code == '+' || cur_token.code == '-')
9139 {
9140 /* Need to look one token ahead - if the next token
9141 is a constant, the current token is its sign. */
9142 int next_code;
9143
9144 intel_match_token (cur_token.code);
9145 next_code = cur_token.code;
9146 intel_putback_token ();
9147 if (next_code == T_CONST)
9148 break;
9149 }
9150
9151 /* e09 OFFSET e09 */
9152 if (cur_token.code == T_OFFSET)
9153 {
9154 if (!in_offset++)
9155 ++intel_parser.in_offset;
9156 }
9157
9158 /* e09 SHORT e09 */
9159 else if (cur_token.code == T_SHORT)
9160 intel_parser.op_modifier |= 1 << T_SHORT;
9161
9162 /* e09 + e09 */
9163 else if (cur_token.code == '+')
9164 strcat (intel_parser.disp, "+");
9165
9166 /* e09 - e09
9167 | ~ e09
9168 | NOT e09 */
9169 else if (cur_token.code == '-' || cur_token.code == '~')
9170 {
9171 char str[2];
64a0c779 9172
a724f0f4
JB		 9173 if (nregs < 0)
9174 nregs = ~nregs;
9175 str[0] = cur_token.code;
9176 str[1] = 0;
9177 strcat (intel_parser.disp, str);
9178 }
9179
9180 /* e09 e10 e09' */
9181 else
9182 break;
9183
9184 intel_match_token (cur_token.code);
64a0c779
DN		 9185 }
9186
a724f0f4 9187 for (;;)
9306ca4a 9188 {
a724f0f4
JB		 9189 if (!intel_e10 ())
9190 return 0;
9306ca4a 9191
a724f0f4
JB		 9192 /* e09' PTR e10 e09' */
9193 if (cur_token.code == T_PTR)
9194 {
9195 char suffix;
9306ca4a 9196
a724f0f4 9197 if (prev_token.code == T_BYTE)
7d5e4556
L		 9198 {
9199 suffix = BYTE_MNEM_SUFFIX;
9200 i.types[this_operand].bitfield.byte = 1;
9201 }
9306ca4a 9202
a724f0f4
JB		 9203 else if (prev_token.code == T_WORD)
9204 {
34b772a6
JB		 9205 if ((current_templates->start->name[0] == 'l'
9206 && current_templates->start->name[2] == 's'
9207 && current_templates->start->name[3] == 0)
9208 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9209 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9210 else if (intel_parser.got_a_float == 2) /* "fi..." */
9211 suffix = SHORT_MNEM_SUFFIX;
9212 else
9213 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9214 i.types[this_operand].bitfield.word = 1;
a724f0f4 9215 }
64a0c779 9216
a724f0f4
JB		 9217 else if (prev_token.code == T_DWORD)
9218 {
34b772a6
JB		 9219 if ((current_templates->start->name[0] == 'l'
9220 && current_templates->start->name[2] == 's'
9221 && current_templates->start->name[3] == 0)
9222 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9223 suffix = WORD_MNEM_SUFFIX;
9224 else if (flag_code == CODE_16BIT
40fb9820
L		 9225 && (current_templates->start->opcode_modifier.jump
9226 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9227 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9228 else if (intel_parser.got_a_float == 1) /* "f..." */
9229 suffix = SHORT_MNEM_SUFFIX;
9230 else
9231 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9232 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9233 }
9306ca4a 9234
a724f0f4
JB		 9235 else if (prev_token.code == T_FWORD)
9236 {
9237 if (current_templates->start->name[0] == 'l'
9238 && current_templates->start->name[2] == 's'
9239 && current_templates->start->name[3] == 0)
9240 suffix = LONG_MNEM_SUFFIX;
9241 else if (!intel_parser.got_a_float)
9242 {
9243 if (flag_code == CODE_16BIT)
9244 add_prefix (DATA_PREFIX_OPCODE);
9245 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9246 }
9247 else
9248 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9249 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9250 }
64a0c779 9251
a724f0f4
JB		 9252 else if (prev_token.code == T_QWORD)
9253 {
34b772a6
JB		 9254 if (current_templates->start->base_opcode == 0x62 /* bound */
9255 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9256 suffix = LONG_MNEM_SUFFIX;
9257 else
34b772a6 9258 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9259 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9260 }
64a0c779 9261
a724f0f4
JB		 9262 else if (prev_token.code == T_TBYTE)
9263 {
9264 if (intel_parser.got_a_float == 1)
9265 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9266 else
9267 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9268 }
9306ca4a 9269
a724f0f4 9270 else if (prev_token.code == T_XMMWORD)
9306ca4a 9271 {
582d5edd 9272 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9273 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9274 }
64a0c779 9275
c0f3af97
L		 9276 else if (prev_token.code == T_YMMWORD)
9277 {
9278 suffix = YMMWORD_MNEM_SUFFIX;
9279 i.types[this_operand].bitfield.ymmword = 1;
9280 }
9281
f16b83df 9282 else
a724f0f4
JB		 9283 {
9284 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9285 return 0;
9286 }
9287
7d5e4556
L		 9288 i.types[this_operand].bitfield.unspecified = 0;
9289
435acd52
JB		 9290 /* Operands for jump/call using 'ptr' notation denote absolute
9291 addresses. */
40fb9820
L		 9292 if (current_templates->start->opcode_modifier.jump
9293 || current_templates->start->opcode_modifier.jumpdword)
9294 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9295
a724f0f4
JB		 9296 if (current_templates->start->base_opcode == 0x8d /* lea */)
9297 ;
9298 else if (!i.suffix)
9299 i.suffix = suffix;
9300 else if (i.suffix != suffix)
9301 {
9302 as_bad (_("Conflicting operand modifiers"));
9303 return 0;
9304 }
64a0c779 9305
9306ca4a
JB		 9306 }
9307
a724f0f4
JB		 9308 /* e09' : e10 e09' */
9309 else if (cur_token.code == ':')
9306ca4a 9310 {
a724f0f4
JB		 9311 if (prev_token.code != T_REG)
9312 {
9313 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9314 segment/group identifier (which we don't have), using comma
9315 as the operand separator there is even less consistent, since
9316 there all branches only have a single operand. */
9317 if (this_operand != 0
9318 || intel_parser.in_offset
9319 || intel_parser.in_bracket
40fb9820
L		 9320 || (!current_templates->start->opcode_modifier.jump
9321 && !current_templates->start->opcode_modifier.jumpdword
9322 && !current_templates->start->opcode_modifier.jumpintersegment
9323 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9324 return intel_match_token (T_NIL);
9325 /* Remember the start of the 2nd operand and terminate 1st
9326 operand here.
9327 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9328 another expression), but it gets at least the simplest case
9329 (a plain number or symbol on the left side) right. */
9330 intel_parser.next_operand = intel_parser.op_string;
9331 *--intel_parser.op_string = '\0';
9332 return intel_match_token (':');
9333 }
9306ca4a 9334 }
64a0c779 9335
a724f0f4 9336 /* e09' Empty */
64a0c779 9337 else
a724f0f4 9338 break;
64a0c779 9339
a724f0f4
JB		 9340 intel_match_token (cur_token.code);
9341
9342 }
9343
9344 if (in_offset)
9345 {
9346 --intel_parser.in_offset;
9347 if (nregs < 0)
9348 nregs = ~nregs;
9349 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9350 {
a724f0f4 9351 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9352 return 0;
9353 }
a724f0f4
JB		 9354 intel_parser.op_modifier |= 1 << T_OFFSET;
9355 }
9306ca4a 9356
a724f0f4
JB		 9357 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9358 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9359 return 1;
9360}
64a0c779 9361
a724f0f4 9362static int
e3bb37b5 9363intel_bracket_expr (void)
a724f0f4
JB		 9364{
9365 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9366 const char *start = intel_parser.op_string;
9367 int len;
9368
9369 if (i.op[this_operand].regs)
9370 return intel_match_token (T_NIL);
9371
9372 intel_match_token ('[');
9373
9374 /* Mark as a memory operand only if it's not already known to be an
9375 offset expression. If it's an offset expression, we need to keep
9376 the brace in. */
9377 if (!intel_parser.in_offset)
9378 {
9379 ++intel_parser.in_bracket;
435acd52
JB		 9380
9381 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9382 if (current_templates->start->opcode_modifier.jump
9383 || current_templates->start->opcode_modifier.jumpdword)
9384 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9385
a724f0f4
JB		 9386 /* Unfortunately gas always diverged from MASM in a respect that can't
9387 be easily fixed without risking to break code sequences likely to be
9388 encountered (the testsuite even check for this): MASM doesn't consider
9389 an expression inside brackets unconditionally as a memory reference.
9390 When that is e.g. a constant, an offset expression, or the sum of the
9391 two, this is still taken as a constant load. gas, however, always
9392 treated these as memory references. As a compromise, we'll try to make
9393 offset expressions inside brackets work the MASM way (since that's
9394 less likely to be found in real world code), but make constants alone
9395 continue to work the traditional gas way. In either case, issue a
9396 warning. */
9397 intel_parser.op_modifier &= ~was_offset;
64a0c779 9398 }
a724f0f4 9399 else
64e74474 9400 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9401
9402 /* Add a '+' to the displacement string if necessary. */
9403 if (*intel_parser.disp != '\0'
9404 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9405 strcat (intel_parser.disp, "+");
64a0c779 9406
a724f0f4
JB		 9407 if (intel_expr ()
9408 && (len = intel_parser.op_string - start - 1,
9409 intel_match_token (']')))
64a0c779 9410 {
a724f0f4
JB		 9411 /* Preserve brackets when the operand is an offset expression. */
9412 if (intel_parser.in_offset)
9413 strcat (intel_parser.disp, "]");
9414 else
9415 {
9416 --intel_parser.in_bracket;
9417 if (i.base_reg || i.index_reg)
9418 intel_parser.is_mem = 1;
9419 if (!intel_parser.is_mem)
9420 {
9421 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9422 /* Defer the warning until all of the operand was parsed. */
9423 intel_parser.is_mem = -1;
9424 else if (!quiet_warnings)
4eed87de
AM		 9425 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9426 len, start, len, start);
a724f0f4
JB		 9427 }
9428 }
9429 intel_parser.op_modifier |= was_offset;
64a0c779 9430
a724f0f4 9431 return 1;
64a0c779 9432 }
a724f0f4 9433 return 0;
64a0c779
DN		 9434}
9435
9436/* e10 e11 e10'
9437
9438 e10' [ expr ] e10'
b77a7acd 9439 | Empty */
64a0c779 9440static int
e3bb37b5 9441intel_e10 (void)
64a0c779 9442{
a724f0f4
JB		 9443 if (!intel_e11 ())
9444 return 0;
64a0c779 9445
a724f0f4 9446 while (cur_token.code == '[')
64a0c779 9447 {
a724f0f4 9448 if (!intel_bracket_expr ())
21d6c4af 9449 return 0;
64a0c779
DN		 9450 }
9451
a724f0f4 9452 return 1;
64a0c779
DN		 9453}
9454
64a0c779 9455/* e11 ( expr )
b77a7acd 9456 | [ expr ]
64a0c779
DN		 9457 | BYTE
9458 | WORD
9459 | DWORD
9306ca4a 9460 | FWORD
64a0c779 9461 | QWORD
9306ca4a
JB		 9462 | TBYTE
9463 | OWORD
9464 | XMMWORD
c0f3af97 9465 | YMMWORD
4a1805b1 9466 | $
64a0c779
DN		 9467 | .
9468 | register
9469 | id
9470 | constant */
9471static int
e3bb37b5 9472intel_e11 (void)
64a0c779 9473{
a724f0f4 9474 switch (cur_token.code)
64a0c779 9475 {
a724f0f4
JB		 9476 /* e11 ( expr ) */
9477 case '(':
64a0c779
DN		 9478 intel_match_token ('(');
9479 strcat (intel_parser.disp, "(");
9480
9481 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9482 {
9483 strcat (intel_parser.disp, ")");
9484 return 1;
9485 }
a724f0f4 9486 return 0;
4a1805b1 9487
a724f0f4
JB		 9488 /* e11 [ expr ] */
9489 case '[':
a724f0f4 9490 return intel_bracket_expr ();
64a0c779 9491
a724f0f4
JB		 9492 /* e11 $
9493 | . */
9494 case '.':
64a0c779
DN		 9495 strcat (intel_parser.disp, cur_token.str);
9496 intel_match_token (cur_token.code);
21d6c4af
DN		 9497
9498 /* Mark as a memory operand only if it's not already known to be an
9499 offset expression. */
a724f0f4 9500 if (!intel_parser.in_offset)
21d6c4af 9501 intel_parser.is_mem = 1;
64a0c779
DN		 9502
9503 return 1;
64a0c779 9504
a724f0f4
JB		 9505 /* e11 register */
9506 case T_REG:
9507 {
9508 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9509
a724f0f4 9510 intel_match_token (T_REG);
64a0c779 9511
a724f0f4
JB		 9512 /* Check for segment change. */
9513 if (cur_token.code == ':')
9514 {
40fb9820
L		 9515 if (!reg->reg_type.bitfield.sreg2
9516 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9517 {
4eed87de
AM		 9518 as_bad (_("`%s' is not a valid segment register"),
9519 reg->reg_name);
a724f0f4
JB		 9520 return 0;
9521 }
b7240065
JB		 9522 else if (i.mem_operands >= 2)
9523 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9524 else if (i.seg[i.mem_operands])
9525 as_warn (_("Extra segment override ignored"));
9526 else
9527 {
9528 if (!intel_parser.in_offset)
9529 intel_parser.is_mem = 1;
9530 switch (reg->reg_num)
9531 {
9532 case 0:
9533 i.seg[i.mem_operands] = &es;
9534 break;
9535 case 1:
9536 i.seg[i.mem_operands] = &cs;
9537 break;
9538 case 2:
9539 i.seg[i.mem_operands] = &ss;
9540 break;
9541 case 3:
9542 i.seg[i.mem_operands] = &ds;
9543 break;
9544 case 4:
9545 i.seg[i.mem_operands] = &fs;
9546 break;
9547 case 5:
9548 i.seg[i.mem_operands] = &gs;
9549 break;
9550 }
9551 }
9552 }
64a0c779 9553
b7240065
JB		 9554 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9555 {
9556 as_bad (_("cannot use `FLAT' here"));
9557 return 0;
9558 }
9559
a724f0f4
JB		 9560 /* Not a segment register. Check for register scaling. */
9561 else if (cur_token.code == '*')
9562 {
9563 if (!intel_parser.in_bracket)
9564 {
9565 as_bad (_("Register scaling only allowed in memory operands"));
9566 return 0;
9567 }
64a0c779 9568
40fb9820 9569 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9570 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9571 else if (i.index_reg)
9572 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9573
a724f0f4
JB		 9574 /* What follows must be a valid scale. */
9575 intel_match_token ('*');
9576 i.index_reg = reg;
40fb9820 9577 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9578
a724f0f4
JB		 9579 /* Set the scale after setting the register (otherwise,
9580 i386_scale will complain) */
9581 if (cur_token.code == '+' || cur_token.code == '-')
9582 {
9583 char *str, sign = cur_token.code;
9584 intel_match_token (cur_token.code);
9585 if (cur_token.code != T_CONST)
9586 {
9587 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9588 cur_token.str);
9589 return 0;
9590 }
9591 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9592 strcpy (str + 1, cur_token.str);
9593 *str = sign;
9594 if (!i386_scale (str))
9595 return 0;
9596 free (str);
9597 }
9598 else if (!i386_scale (cur_token.str))
64a0c779 9599 return 0;
a724f0f4
JB		 9600 intel_match_token (cur_token.code);
9601 }
64a0c779 9602
a724f0f4
JB		 9603 /* No scaling. If this is a memory operand, the register is either a
9604 base register (first occurrence) or an index register (second
9605 occurrence). */
7b0441f6 9606 else if (intel_parser.in_bracket)
a724f0f4 9607 {
64a0c779 9608
a724f0f4
JB		 9609 if (!i.base_reg)
9610 i.base_reg = reg;
9611 else if (!i.index_reg)
9612 i.index_reg = reg;
9613 else
9614 {
9615 as_bad (_("Too many register references in memory operand"));
9616 return 0;
9617 }
64a0c779 9618
40fb9820 9619 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9620 }
4a1805b1 9621
4d1bb795
JB		 9622 /* It's neither base nor index. */
9623 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9624 {
40fb9820
L		 9625 i386_operand_type temp = reg->reg_type;
9626 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9627 i.types[this_operand] = operand_type_or (i.types[this_operand],
9628 temp);
7d5e4556 9629 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9630 i.op[this_operand].regs = reg;
9631 i.reg_operands++;
9632 }
9633 else
9634 {
9635 as_bad (_("Invalid use of register"));
9636 return 0;
9637 }
64a0c779 9638
a724f0f4
JB		 9639 /* Since registers are not part of the displacement string (except
9640 when we're parsing offset operands), we may need to remove any
9641 preceding '+' from the displacement string. */
9642 if (*intel_parser.disp != '\0'
9643 && !intel_parser.in_offset)
9644 {
9645 char *s = intel_parser.disp;
9646 s += strlen (s) - 1;
9647 if (*s == '+')
9648 *s = '\0';
9649 }
4a1805b1 9650
a724f0f4
JB		 9651 return 1;
9652 }
9653
9654 /* e11 BYTE
9655 | WORD
9656 | DWORD
9657 | FWORD
9658 | QWORD
9659 | TBYTE
9660 | OWORD
c0f3af97
L		 9661 | XMMWORD
9662 | YMMWORD */
a724f0f4
JB		 9663 case T_BYTE:
9664 case T_WORD:
9665 case T_DWORD:
9666 case T_FWORD:
9667 case T_QWORD:
9668 case T_TBYTE:
9669 case T_XMMWORD:
c0f3af97 9670 case T_YMMWORD:
a724f0f4 9671 intel_match_token (cur_token.code);
64a0c779 9672
a724f0f4
JB		 9673 if (cur_token.code == T_PTR)
9674 return 1;
9675
9676 /* It must have been an identifier. */
9677 intel_putback_token ();
9678 cur_token.code = T_ID;
9679 /* FALLTHRU */
9680
9681 /* e11 id
9682 | constant */
9683 case T_ID:
9684 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9685 {
9686 symbolS *symbolP;
9687
a724f0f4
JB		 9688 /* The identifier represents a memory reference only if it's not
9689 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9690 symbolP = symbol_find(cur_token.str);
9691 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9692 intel_parser.is_mem = 1;
9693 }
a724f0f4 9694 /* FALLTHRU */
64a0c779 9695
a724f0f4
JB		 9696 case T_CONST:
9697 case '-':
9698 case '+':
9699 {
9700 char *save_str, sign = 0;
64a0c779 9701
a724f0f4
JB		 9702 /* Allow constants that start with `+' or `-'. */
9703 if (cur_token.code == '-' || cur_token.code == '+')
9704 {
9705 sign = cur_token.code;
9706 intel_match_token (cur_token.code);
9707 if (cur_token.code != T_CONST)
9708 {
9709 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9710 cur_token.str);
9711 return 0;
9712 }
9713 }
64a0c779 9714
a724f0f4
JB		 9715 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9716 strcpy (save_str + !!sign, cur_token.str);
9717 if (sign)
9718 *save_str = sign;
64a0c779 9719
a724f0f4
JB		 9720 /* Get the next token to check for register scaling. */
9721 intel_match_token (cur_token.code);
64a0c779 9722
4eed87de
AM		 9723 /* Check if this constant is a scaling factor for an
9724 index register. */
a724f0f4
JB		 9725 if (cur_token.code == '*')
9726 {
9727 if (intel_match_token ('*') && cur_token.code == T_REG)
9728 {
9729 const reg_entry *reg = cur_token.reg;
9730
9731 if (!intel_parser.in_bracket)
9732 {
4eed87de
AM		 9733 as_bad (_("Register scaling only allowed "
9734 "in memory operands"));
a724f0f4
JB		 9735 return 0;
9736 }
9737
4eed87de
AM		 9738 /* Disallow things like [1*si].
9739 sp and esp are invalid as index. */
40fb9820 9740 if (reg->reg_type.bitfield.reg16)
4eed87de 9741 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9742 else if (i.index_reg)
4eed87de 9743 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9744
9745 /* The constant is followed by `* reg', so it must be
9746 a valid scale. */
9747 i.index_reg = reg;
40fb9820 9748 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9749
9750 /* Set the scale after setting the register (otherwise,
9751 i386_scale will complain) */
9752 if (!i386_scale (save_str))
64a0c779 9753 return 0;
a724f0f4
JB		 9754 intel_match_token (T_REG);
9755
9756 /* Since registers are not part of the displacement
9757 string, we may need to remove any preceding '+' from
9758 the displacement string. */
9759 if (*intel_parser.disp != '\0')
9760 {
9761 char *s = intel_parser.disp;
9762 s += strlen (s) - 1;
9763 if (*s == '+')
9764 *s = '\0';
9765 }
9766
9767 free (save_str);
9768
9769 return 1;
9770 }
64a0c779 9771
a724f0f4
JB		 9772 /* The constant was not used for register scaling. Since we have
9773 already consumed the token following `*' we now need to put it
9774 back in the stream. */
64a0c779 9775 intel_putback_token ();
a724f0f4 9776 }
64a0c779 9777
a724f0f4
JB		 9778 /* Add the constant to the displacement string. */
9779 strcat (intel_parser.disp, save_str);
9780 free (save_str);
64a0c779 9781
a724f0f4
JB		 9782 return 1;
9783 }
64a0c779
DN		 9784 }
9785
64a0c779
DN		 9786 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9787 return 0;
9788}
9789
64a0c779
DN		 9790/* Match the given token against cur_token. If they match, read the next
9791 token from the operand string. */
9792static int
e3bb37b5 9793intel_match_token (int code)
64a0c779
DN		 9794{
9795 if (cur_token.code == code)
9796 {
9797 intel_get_token ();
9798 return 1;
9799 }
9800 else
9801 {
0477af35 9802 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9803 return 0;
9804 }
9805}
9806
64a0c779
DN		 9807/* Read a new token from intel_parser.op_string and store it in cur_token. */
9808static void
e3bb37b5 9809intel_get_token (void)
64a0c779
DN		 9810{
9811 char *end_op;
9812 const reg_entry *reg;
9813 struct intel_token new_token;
9814
9815 new_token.code = T_NIL;
9816 new_token.reg = NULL;
9817 new_token.str = NULL;
9818
4a1805b1 9819 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9820 cur_token to prev_token. */
9821 if (prev_token.str)
9822 free (prev_token.str);
9823
9824 prev_token = cur_token;
9825
9826 /* Skip whitespace. */
9827 while (is_space_char (*intel_parser.op_string))
9828 intel_parser.op_string++;
9829
9830 /* Return an empty token if we find nothing else on the line. */
9831 if (*intel_parser.op_string == '\0')
9832 {
9833 cur_token = new_token;
9834 return;
9835 }
9836
9837 /* The new token cannot be larger than the remainder of the operand
9838 string. */
a724f0f4 9839 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9840 new_token.str[0] = '\0';
9841
9842 if (strchr ("0123456789", *intel_parser.op_string))
9843 {
9844 char *p = new_token.str;
9845 char *q = intel_parser.op_string;
9846 new_token.code = T_CONST;
9847
9848 /* Allow any kind of identifier char to encompass floating point and
9849 hexadecimal numbers. */
9850 while (is_identifier_char (*q))
9851 *p++ = *q++;
9852 *p = '\0';
9853
9854 /* Recognize special symbol names [0-9][bf]. */
9855 if (strlen (intel_parser.op_string) == 2
4a1805b1 9856 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9857 || intel_parser.op_string[1] == 'f'))
9858 new_token.code = T_ID;
9859 }
9860
4d1bb795 9861 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9862 {
4d1bb795
JB		 9863 size_t len = end_op - intel_parser.op_string;
9864
64a0c779
DN		 9865 new_token.code = T_REG;
9866 new_token.reg = reg;
9867
4d1bb795
JB		 9868 memcpy (new_token.str, intel_parser.op_string, len);
9869 new_token.str[len] = '\0';
64a0c779
DN		 9870 }
9871
9872 else if (is_identifier_char (*intel_parser.op_string))
9873 {
9874 char *p = new_token.str;
9875 char *q = intel_parser.op_string;
9876
9877 /* A '.' or '$' followed by an identifier char is an identifier.
9878 Otherwise, it's operator '.' followed by an expression. */
9879 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9880 {
9306ca4a
JB		 9881 new_token.code = '.';
9882 new_token.str[0] = '.';
64a0c779
DN		 9883 new_token.str[1] = '\0';
9884 }
9885 else
9886 {
9887 while (is_identifier_char (*q) || *q == '@')
9888 *p++ = *q++;
9889 *p = '\0';
9890
9306ca4a
JB		 9891 if (strcasecmp (new_token.str, "NOT") == 0)
9892 new_token.code = '~';
9893
9894 else if (strcasecmp (new_token.str, "MOD") == 0)
9895 new_token.code = '%';
9896
9897 else if (strcasecmp (new_token.str, "AND") == 0)
9898 new_token.code = '&';
9899
9900 else if (strcasecmp (new_token.str, "OR") == 0)
9901 new_token.code = '|';
9902
9903 else if (strcasecmp (new_token.str, "XOR") == 0)
9904 new_token.code = '^';
9905
9906 else if (strcasecmp (new_token.str, "SHL") == 0)
9907 new_token.code = T_SHL;
9908
9909 else if (strcasecmp (new_token.str, "SHR") == 0)
9910 new_token.code = T_SHR;
9911
9912 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9913 new_token.code = T_BYTE;
9914
9915 else if (strcasecmp (new_token.str, "WORD") == 0)
9916 new_token.code = T_WORD;
9917
9918 else if (strcasecmp (new_token.str, "DWORD") == 0)
9919 new_token.code = T_DWORD;
9920
9306ca4a
JB		 9921 else if (strcasecmp (new_token.str, "FWORD") == 0)
9922 new_token.code = T_FWORD;
9923
64a0c779
DN		 9924 else if (strcasecmp (new_token.str, "QWORD") == 0)
9925 new_token.code = T_QWORD;
9926
9306ca4a
JB		 9927 else if (strcasecmp (new_token.str, "TBYTE") == 0
9928 /* XXX remove (gcc still uses it) */
9929 || strcasecmp (new_token.str, "XWORD") == 0)
9930 new_token.code = T_TBYTE;
9931
9932 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9933 || strcasecmp (new_token.str, "OWORD") == 0)
9934 new_token.code = T_XMMWORD;
64a0c779 9935
c0f3af97
L		 9936 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9937 new_token.code = T_YMMWORD;
9938
64a0c779
DN		 9939 else if (strcasecmp (new_token.str, "PTR") == 0)
9940 new_token.code = T_PTR;
9941
9942 else if (strcasecmp (new_token.str, "SHORT") == 0)
9943 new_token.code = T_SHORT;
9944
9945 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9946 {
9947 new_token.code = T_OFFSET;
9948
9949 /* ??? This is not mentioned in the MASM grammar but gcc
9950 makes use of it with -mintel-syntax. OFFSET may be
9951 followed by FLAT: */
9952 if (strncasecmp (q, " FLAT:", 6) == 0)
9953 strcat (new_token.str, " FLAT:");
9954 }
9955
64a0c779
DN		 9956 else
9957 new_token.code = T_ID;
9958 }
9959 }
9960
9306ca4a
JB		 9961 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9962 {
9963 new_token.code = *intel_parser.op_string;
9964 new_token.str[0] = *intel_parser.op_string;
9965 new_token.str[1] = '\0';
9966 }
9967
9968 else if (strchr ("<>", *intel_parser.op_string)
9969 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9970 {
9971 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9972 new_token.str[0] = *intel_parser.op_string;
9973 new_token.str[1] = *intel_parser.op_string;
9974 new_token.str[2] = '\0';
9975 }
9976
64a0c779 9977 else
0477af35 9978 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9979
9980 intel_parser.op_string += strlen (new_token.str);
9981 cur_token = new_token;
9982}
9983
64a0c779
DN		 9984/* Put cur_token back into the token stream and make cur_token point to
9985 prev_token. */
9986static void
e3bb37b5 9987intel_putback_token (void)
64a0c779 9988{
a724f0f4
JB		 9989 if (cur_token.code != T_NIL)
9990 {
9991 intel_parser.op_string -= strlen (cur_token.str);
9992 free (cur_token.str);
9993 }
64a0c779 9994 cur_token = prev_token;
4a1805b1 9995
64a0c779
DN		 9996 /* Forget prev_token. */
9997 prev_token.code = T_NIL;
9998 prev_token.reg = NULL;
9999 prev_token.str = NULL;
10000}
54cfded0 10001
a60de03c
JB		 10002void
10003tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 10004{
a60de03c
JB		 10005 int saved_naked_reg;
10006 char saved_register_dot;
54cfded0 10007
a60de03c
JB		 10008 saved_naked_reg = allow_naked_reg;
10009 allow_naked_reg = 1;
10010 saved_register_dot = register_chars['.'];
10011 register_chars['.'] = '.';
10012 allow_pseudo_reg = 1;
10013 expression_and_evaluate (exp);
10014 allow_pseudo_reg = 0;
10015 register_chars['.'] = saved_register_dot;
10016 allow_naked_reg = saved_naked_reg;
10017
10018 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10019 {
a60de03c
JB		 10020 if ((addressT) exp->X_add_number < i386_regtab_size)
10021 {
10022 exp->X_op = O_constant;
10023 exp->X_add_number = i386_regtab[exp->X_add_number]
10024 .dw2_regnum[flag_code >> 1];
10025 }
10026 else
10027 exp->X_op = O_illegal;
54cfded0 10028 }
54cfded0
AM		 10029}
10030
10031void
10032tc_x86_frame_initial_instructions (void)
10033{
a60de03c
JB		 10034 static unsigned int sp_regno[2];
10035
10036 if (!sp_regno[flag_code >> 1])
10037 {
10038 char *saved_input = input_line_pointer;
10039 char sp[][4] = {"esp", "rsp"};
10040 expressionS exp;
a4447b93 10041
a60de03c
JB		 10042 input_line_pointer = sp[flag_code >> 1];
10043 tc_x86_parse_to_dw2regnum (&exp);
10044 assert (exp.X_op == O_constant);
10045 sp_regno[flag_code >> 1] = exp.X_add_number;
10046 input_line_pointer = saved_input;
10047 }
a4447b93 10048
a60de03c 10049 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 10050 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10051}
d2b2c203
DJ		 10052
10053int
10054i386_elf_section_type (const char *str, size_t len)
10055{
10056 if (flag_code == CODE_64BIT
10057 && len == sizeof ("unwind") - 1
10058 && strncmp (str, "unwind", 6) == 0)
10059 return SHT_X86_64_UNWIND;
10060
10061 return -1;
10062}
bb41ade5
AM		 10063
10064#ifdef TE_PE
10065void
10066tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10067{
10068 expressionS expr;
10069
10070 expr.X_op = O_secrel;
10071 expr.X_add_symbol = symbol;
10072 expr.X_add_number = 0;
10073 emit_expr (&expr, size);
10074}
10075#endif
3b22753a
L		 10076
10077#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10079
10080int
10081x86_64_section_letter (int letter, char **ptr_msg)
10082{
10083 if (flag_code == CODE_64BIT)
10084 {
10085 if (letter == 'l')
10086 return SHF_X86_64_LARGE;
10087
10088 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10089 }
3b22753a 10090 else
64e74474 10091 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10092 return -1;
10093}
10094
10095int
10096x86_64_section_word (char *str, size_t len)
10097{
8620418b 10098 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10099 return SHF_X86_64_LARGE;
10100
10101 return -1;
10102}
10103
10104static void
10105handle_large_common (int small ATTRIBUTE_UNUSED)
10106{
10107 if (flag_code != CODE_64BIT)
10108 {
10109 s_comm_internal (0, elf_common_parse);
10110 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10111 }
10112 else
10113 {
10114 static segT lbss_section;
10115 asection *saved_com_section_ptr = elf_com_section_ptr;
10116 asection *saved_bss_section = bss_section;
10117
10118 if (lbss_section == NULL)
10119 {
10120 flagword applicable;
10121 segT seg = now_seg;
10122 subsegT subseg = now_subseg;
10123
10124 /* The .lbss section is for local .largecomm symbols. */
10125 lbss_section = subseg_new (".lbss", 0);
10126 applicable = bfd_applicable_section_flags (stdoutput);
10127 bfd_set_section_flags (stdoutput, lbss_section,
10128 applicable & SEC_ALLOC);
10129 seg_info (lbss_section)->bss = 1;
10130
10131 subseg_set (seg, subseg);
10132 }
10133
10134 elf_com_section_ptr = &_bfd_elf_large_com_section;
10135 bss_section = lbss_section;
10136
10137 s_comm_internal (0, elf_common_parse);
10138
10139 elf_com_section_ptr = saved_com_section_ptr;
10140 bss_section = saved_bss_section;
10141 }
10142}
10143#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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