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[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
153enum processor_type
154{
155 PROCESSOR_UNKNOWN,
156 PROCESSOR_I386,
157 PROCESSOR_I486,
158 PROCESSOR_PENTIUM,
159 PROCESSOR_PENTIUMPRO,
160 PROCESSOR_PENTIUM4,
161 PROCESSOR_NOCONA,
162 PROCESSOR_CORE,
163 PROCESSOR_CORE2,
164 PROCESSOR_K6,
165 PROCESSOR_ATHLON,
166 PROCESSOR_K8,
167 PROCESSOR_GENERIC32,
168 PROCESSOR_GENERIC64,
169 PROCESSOR_AMDFAM10
170};
171
172/* x86 arch names, types and features */
173typedef struct
174{
175 const char *name; /* arch name */
176 enum processor_type type; /* arch type */
177 i386_cpu_flags flags; /* cpu feature flags */
178}
179arch_entry;
180
e3bb37b5
L		 181static void set_code_flag (int);
182static void set_16bit_gcc_code_flag (int);
183static void set_intel_syntax (int);
1efbbeb4 184static void set_intel_mnemonic (int);
db51cc60 185static void set_allow_index_reg (int);
cb19c032 186static void set_sse_check (int);
e3bb37b5 187static void set_cpu_arch (int);
6482c264 188#ifdef TE_PE
e3bb37b5 189static void pe_directive_secrel (int);
6482c264 190#endif
e3bb37b5
L		 191static void signed_cons (int);
192static char *output_invalid (int c);
a7619375 193static int i386_att_operand (char *);
e3bb37b5
L		 194static int i386_intel_operand (char *, int);
195static const reg_entry *parse_register (char *, char **);
196static char *parse_insn (char *, char *);
197static char *parse_operands (char *, const char *);
198static void swap_operands (void);
4d456e3d 199static void swap_2_operands (int, int);
e3bb37b5
L		 200static void optimize_imm (void);
201static void optimize_disp (void);
202static int match_template (void);
203static int check_string (void);
204static int process_suffix (void);
205static int check_byte_reg (void);
206static int check_long_reg (void);
207static int check_qword_reg (void);
208static int check_word_reg (void);
209static int finalize_imm (void);
85f10a01 210static void process_drex (void);
e3bb37b5
L		 211static int process_operands (void);
212static const seg_entry *build_modrm_byte (void);
213static void output_insn (void);
214static void output_imm (fragS *, offsetT);
215static void output_disp (fragS *, offsetT);
29b0f896 216#ifndef I386COFF
e3bb37b5 217static void s_bss (int);
252b5132 218#endif
17d4e2a2
L		 219#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
220static void handle_large_common (int small ATTRIBUTE_UNUSED);
221#endif
252b5132 222
a847613f 223static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 224
c0f3af97
L		 225/* VEX prefix. */
226typedef struct
227{
228 /* VEX prefix is either 2 byte or 3 byte. */
229 unsigned char bytes[3];
230 unsigned int length;
231 /* Destination or source register specifier. */
232 const reg_entry *register_specifier;
233} vex_prefix;
234
252b5132 235/* 'md_assemble ()' gathers together information and puts it into a
47926f60 236 i386_insn. */
252b5132 237
520dc8e8
AM		 238union i386_op
239 {
240 expressionS *disps;
241 expressionS *imms;
242 const reg_entry *regs;
243 };
244
252b5132
RH		 245struct _i386_insn
246 {
47926f60 247 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 248 template tm;
249
7d5e4556
L		 250 /* SUFFIX holds the instruction size suffix for byte, word, dword
251 or qword, if given. */
252b5132
RH		 252 char suffix;
253
47926f60 254 /* OPERANDS gives the number of given operands. */
252b5132
RH		 255 unsigned int operands;
256
257 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
258 of given register, displacement, memory operands and immediate
47926f60 259 operands. */
252b5132
RH		 260 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
261
262 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 263 use OP[i] for the corresponding operand. */
40fb9820 264 i386_operand_type types[MAX_OPERANDS];
252b5132 265
520dc8e8
AM		 266 /* Displacement expression, immediate expression, or register for each
267 operand. */
268 union i386_op op[MAX_OPERANDS];
252b5132 269
3e73aa7c
JH		 270 /* Flags for operands. */
271 unsigned int flags[MAX_OPERANDS];
272#define Operand_PCrel 1
273
252b5132 274 /* Relocation type for operand */
f86103b7 275 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 276
252b5132
RH		 277 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
278 the base index byte below. */
279 const reg_entry *base_reg;
280 const reg_entry *index_reg;
281 unsigned int log2_scale_factor;
282
283 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 284 explicit segment overrides are given. */
ce8a8b2f 285 const seg_entry *seg[2];
252b5132
RH		 286
287 /* PREFIX holds all the given prefix opcodes (usually null).
288 PREFIXES is the number of prefix opcodes. */
289 unsigned int prefixes;
290 unsigned char prefix[MAX_PREFIXES];
291
292 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 293 addressing modes of this insn are encoded. DREX is the byte
294 added by the SSE5 instructions. */
252b5132
RH		 295
296 modrm_byte rm;
3e73aa7c 297 rex_byte rex;
252b5132 298 sib_byte sib;
85f10a01 299 drex_byte drex;
c0f3af97 300 vex_prefix vex;
252b5132
RH		 301 };
302
303typedef struct _i386_insn i386_insn;
304
305/* List of chars besides those in app.c:symbol_chars that can start an
306 operand. Used to prevent the scrubber eating vital white-space. */
32137342 307const char extra_symbol_chars[] = "*%-(["
252b5132 308#ifdef LEX_AT
32137342
NC		 309 "@"
310#endif
311#ifdef LEX_QM
312 "?"
252b5132 313#endif
32137342 314 ;
252b5132 315
29b0f896
AM		 316#if (defined (TE_I386AIX) \
317 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 318 && !defined (TE_GNU) \
29b0f896 319 && !defined (TE_LINUX) \
32137342 320 && !defined (TE_NETWARE) \
29b0f896
AM		 321 && !defined (TE_FreeBSD) \
322 && !defined (TE_NetBSD)))
252b5132 323/* This array holds the chars that always start a comment. If the
b3b91714
AM		 324 pre-processor is disabled, these aren't very useful. The option
325 --divide will remove '/' from this list. */
326const char *i386_comment_chars = "#/";
327#define SVR4_COMMENT_CHARS 1
252b5132 328#define PREFIX_SEPARATOR '\\'
252b5132 329
b3b91714
AM		 330#else
331const char *i386_comment_chars = "#";
332#define PREFIX_SEPARATOR '/'
333#endif
334
252b5132
RH		 335/* This array holds the chars that only start a comment at the beginning of
336 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 337 .line and .file directives will appear in the pre-processed output.
338 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 339 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 340 #NO_APP at the beginning of its output.
341 Also note that comments started like this one will always work if
252b5132 342 '/' isn't otherwise defined. */
b3b91714 343const char line_comment_chars[] = "#/";
252b5132 344
63a0b638 345const char line_separator_chars[] = ";";
252b5132 346
ce8a8b2f
AM		 347/* Chars that can be used to separate mant from exp in floating point
348 nums. */
252b5132
RH		 349const char EXP_CHARS[] = "eE";
350
ce8a8b2f
AM		 351/* Chars that mean this number is a floating point constant
352 As in 0f12.456
353 or 0d1.2345e12. */
252b5132
RH		 354const char FLT_CHARS[] = "fFdDxX";
355
ce8a8b2f 356/* Tables for lexical analysis. */
252b5132
RH		 357static char mnemonic_chars[256];
358static char register_chars[256];
359static char operand_chars[256];
360static char identifier_chars[256];
361static char digit_chars[256];
362
ce8a8b2f 363/* Lexical macros. */
252b5132
RH		 364#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
365#define is_operand_char(x) (operand_chars[(unsigned char) x])
366#define is_register_char(x) (register_chars[(unsigned char) x])
367#define is_space_char(x) ((x) == ' ')
368#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
369#define is_digit_char(x) (digit_chars[(unsigned char) x])
370
0234cb7c 371/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 372static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
373
374/* md_assemble() always leaves the strings it's passed unaltered. To
375 effect this we maintain a stack of saved characters that we've smashed
376 with '\0's (indicating end of strings for various sub-fields of the
47926f60 377 assembler instruction). */
252b5132 378static char save_stack[32];
ce8a8b2f 379static char *save_stack_p;
252b5132
RH		 380#define END_STRING_AND_SAVE(s) \
381 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
382#define RESTORE_END_STRING(s) \
383 do { *(s) = *--save_stack_p; } while (0)
384
47926f60 385/* The instruction we're assembling. */
252b5132
RH		 386static i386_insn i;
387
388/* Possible templates for current insn. */
389static const templates *current_templates;
390
31b2323c
L		 391/* Per instruction expressionS buffers: max displacements & immediates. */
392static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
393static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 394
47926f60
KH		 395/* Current operand we are working on. */
396static int this_operand;
252b5132 397
3e73aa7c
JH		 398/* We support four different modes. FLAG_CODE variable is used to distinguish
399 these. */
400
401enum flag_code {
402 CODE_32BIT,
403 CODE_16BIT,
404 CODE_64BIT };
405
406static enum flag_code flag_code;
4fa24527 407static unsigned int object_64bit;
3e73aa7c
JH		 408static int use_rela_relocations = 0;
409
410/* The names used to print error messages. */
b77a7acd 411static const char *flag_code_names[] =
3e73aa7c
JH		 412 {
413 "32",
414 "16",
415 "64"
416 };
252b5132 417
47926f60
KH		 418/* 1 for intel syntax,
419 0 if att syntax. */
420static int intel_syntax = 0;
252b5132 421
1efbbeb4
L		 422/* 1 for intel mnemonic,
423 0 if att mnemonic. */
424static int intel_mnemonic = !SYSV386_COMPAT;
425
5209009a 426/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 427static int old_gcc = OLDGCC_COMPAT;
428
a60de03c
JB		 429/* 1 if pseudo registers are permitted. */
430static int allow_pseudo_reg = 0;
431
47926f60
KH		 432/* 1 if register prefix % not required. */
433static int allow_naked_reg = 0;
252b5132 434
ba104c83 435/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 436static int allow_index_reg = 0;
437
daf50ae7
L		 438static enum
439 {
440 sse_check_none = 0,
441 sse_check_warning,
442 sse_check_error
443 }
444sse_check;
445
2ca3ace5
L		 446/* Register prefix used for error message. */
447static const char *register_prefix = "%";
448
47926f60
KH		 449/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
450 leave, push, and pop instructions so that gcc has the same stack
451 frame as in 32 bit mode. */
452static char stackop_size = '\0';
eecb386c 453
12b55ccc
L		 454/* Non-zero to optimize code alignment. */
455int optimize_align_code = 1;
456
47926f60
KH		 457/* Non-zero to quieten some warnings. */
458static int quiet_warnings = 0;
a38cf1db 459
47926f60
KH		 460/* CPU name. */
461static const char *cpu_arch_name = NULL;
6305a203 462static char *cpu_sub_arch_name = NULL;
a38cf1db 463
47926f60 464/* CPU feature flags. */
40fb9820
L		 465static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
466
ccc9c027
L		 467/* If we have selected a cpu we are generating instructions for. */
468static int cpu_arch_tune_set = 0;
469
9103f4f4
L		 470/* Cpu we are generating instructions for. */
471static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
472
473/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 474static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 475
ccc9c027
L		 476/* CPU instruction set architecture used. */
477static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
478
9103f4f4 479/* CPU feature flags of instruction set architecture used. */
40fb9820 480static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 481
fddf5b5b
AM		 482/* If set, conditional jumps are not automatically promoted to handle
483 larger than a byte offset. */
484static unsigned int no_cond_jump_promotion = 0;
485
c0f3af97
L		 486/* Encode SSE instructions with VEX prefix. */
487static unsigned int sse2avx;
488
29b0f896 489/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 490static symbolS *GOT_symbol;
29b0f896 491
a4447b93
RH		 492/* The dwarf2 return column, adjusted for 32 or 64 bit. */
493unsigned int x86_dwarf2_return_column;
494
495/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
496int x86_cie_data_alignment;
497
252b5132 498/* Interface to relax_segment.
fddf5b5b
AM		 499 There are 3 major relax states for 386 jump insns because the
500 different types of jumps add different sizes to frags when we're
501 figuring out what sort of jump to choose to reach a given label. */
252b5132 502
47926f60 503/* Types. */
93c2a809
AM		 504#define UNCOND_JUMP 0
505#define COND_JUMP 1
506#define COND_JUMP86 2
fddf5b5b 507
47926f60 508/* Sizes. */
252b5132
RH		 509#define CODE16 1
510#define SMALL 0
29b0f896 511#define SMALL16 (SMALL | CODE16)
252b5132 512#define BIG 2
29b0f896 513#define BIG16 (BIG | CODE16)
252b5132
RH		 514
515#ifndef INLINE
516#ifdef __GNUC__
517#define INLINE __inline__
518#else
519#define INLINE
520#endif
521#endif
522
fddf5b5b
AM		 523#define ENCODE_RELAX_STATE(type, size) \
524 ((relax_substateT) (((type) << 2) | (size)))
525#define TYPE_FROM_RELAX_STATE(s) \
526 ((s) >> 2)
527#define DISP_SIZE_FROM_RELAX_STATE(s) \
528 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 529
530/* This table is used by relax_frag to promote short jumps to long
531 ones where necessary. SMALL (short) jumps may be promoted to BIG
532 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
533 don't allow a short jump in a 32 bit code segment to be promoted to
534 a 16 bit offset jump because it's slower (requires data size
535 prefix), and doesn't work, unless the destination is in the bottom
536 64k of the code segment (The top 16 bits of eip are zeroed). */
537
538const relax_typeS md_relax_table[] =
539{
24eab124
AM		 540 /* The fields are:
541 1) most positive reach of this state,
542 2) most negative reach of this state,
93c2a809 543 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 544 4) which index into the table to try if we can't fit into this one. */
252b5132 545
fddf5b5b 546 /* UNCOND_JUMP states. */
93c2a809
AM		 547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
549 /* dword jmp adds 4 bytes to frag:
550 0 extra opcode bytes, 4 displacement bytes. */
252b5132 551 {0, 0, 4, 0},
93c2a809
AM		 552 /* word jmp adds 2 byte2 to frag:
553 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 554 {0, 0, 2, 0},
555
93c2a809
AM		 556 /* COND_JUMP states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
561 {0, 0, 5, 0},
fddf5b5b 562 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 563 1 extra opcode byte, 2 displacement bytes. */
564 {0, 0, 3, 0},
565
566 /* COND_JUMP86 states. */
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
569 /* dword conditionals adds 5 bytes to frag:
570 1 extra opcode byte, 4 displacement bytes. */
571 {0, 0, 5, 0},
572 /* word conditionals add 4 bytes to frag:
573 1 displacement byte and a 3 byte long branch insn. */
574 {0, 0, 4, 0}
252b5132
RH		 575};
576
9103f4f4
L		 577static const arch_entry cpu_arch[] =
578{
6305a203
L		 579 { "generic32", PROCESSOR_GENERIC32,
580 CPU_GENERIC32_FLAGS },
581 { "generic64", PROCESSOR_GENERIC64,
582 CPU_GENERIC64_FLAGS },
583 { "i8086", PROCESSOR_UNKNOWN,
584 CPU_NONE_FLAGS },
585 { "i186", PROCESSOR_UNKNOWN,
586 CPU_I186_FLAGS },
587 { "i286", PROCESSOR_UNKNOWN,
588 CPU_I286_FLAGS },
589 { "i386", PROCESSOR_I386,
590 CPU_I386_FLAGS },
591 { "i486", PROCESSOR_I486,
592 CPU_I486_FLAGS },
593 { "i586", PROCESSOR_PENTIUM,
594 CPU_I586_FLAGS },
595 { "i686", PROCESSOR_PENTIUMPRO,
596 CPU_I686_FLAGS },
597 { "pentium", PROCESSOR_PENTIUM,
598 CPU_I586_FLAGS },
599 { "pentiumpro", PROCESSOR_PENTIUMPRO,
600 CPU_I686_FLAGS },
601 { "pentiumii", PROCESSOR_PENTIUMPRO,
602 CPU_P2_FLAGS },
603 { "pentiumiii",PROCESSOR_PENTIUMPRO,
604 CPU_P3_FLAGS },
605 { "pentium4", PROCESSOR_PENTIUM4,
606 CPU_P4_FLAGS },
607 { "prescott", PROCESSOR_NOCONA,
608 CPU_CORE_FLAGS },
609 { "nocona", PROCESSOR_NOCONA,
610 CPU_NOCONA_FLAGS },
611 { "yonah", PROCESSOR_CORE,
612 CPU_CORE_FLAGS },
613 { "core", PROCESSOR_CORE,
614 CPU_CORE_FLAGS },
615 { "merom", PROCESSOR_CORE2,
616 CPU_CORE2_FLAGS },
617 { "core2", PROCESSOR_CORE2,
618 CPU_CORE2_FLAGS },
619 { "k6", PROCESSOR_K6,
620 CPU_K6_FLAGS },
621 { "k6_2", PROCESSOR_K6,
622 CPU_K6_2_FLAGS },
623 { "athlon", PROCESSOR_ATHLON,
624 CPU_ATHLON_FLAGS },
625 { "sledgehammer", PROCESSOR_K8,
626 CPU_K8_FLAGS },
627 { "opteron", PROCESSOR_K8,
628 CPU_K8_FLAGS },
629 { "k8", PROCESSOR_K8,
630 CPU_K8_FLAGS },
631 { "amdfam10", PROCESSOR_AMDFAM10,
632 CPU_AMDFAM10_FLAGS },
633 { ".mmx", PROCESSOR_UNKNOWN,
634 CPU_MMX_FLAGS },
635 { ".sse", PROCESSOR_UNKNOWN,
636 CPU_SSE_FLAGS },
637 { ".sse2", PROCESSOR_UNKNOWN,
638 CPU_SSE2_FLAGS },
639 { ".sse3", PROCESSOR_UNKNOWN,
640 CPU_SSE3_FLAGS },
641 { ".ssse3", PROCESSOR_UNKNOWN,
642 CPU_SSSE3_FLAGS },
643 { ".sse4.1", PROCESSOR_UNKNOWN,
644 CPU_SSE4_1_FLAGS },
645 { ".sse4.2", PROCESSOR_UNKNOWN,
646 CPU_SSE4_2_FLAGS },
647 { ".sse4", PROCESSOR_UNKNOWN,
648 CPU_SSE4_2_FLAGS },
c0f3af97
L		 649 { ".avx", PROCESSOR_UNKNOWN,
650 CPU_AVX_FLAGS },
6305a203
L		 651 { ".vmx", PROCESSOR_UNKNOWN,
652 CPU_VMX_FLAGS },
653 { ".smx", PROCESSOR_UNKNOWN,
654 CPU_SMX_FLAGS },
f03fe4c1
L		 655 { ".xsave", PROCESSOR_UNKNOWN,
656 CPU_XSAVE_FLAGS },
c0f3af97
L		 657 { ".aes", PROCESSOR_UNKNOWN,
658 CPU_AES_FLAGS },
594ab6a3
L		 659 { ".pclmul", PROCESSOR_UNKNOWN,
660 CPU_PCLMUL_FLAGS },
c0f3af97 661 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 662 CPU_PCLMUL_FLAGS },
c0f3af97
L		 663 { ".fma", PROCESSOR_UNKNOWN,
664 CPU_FMA_FLAGS },
f1f8f695
L		 665 { ".movbe", PROCESSOR_UNKNOWN,
666 CPU_MOVBE_FLAGS },
667 { ".ept", PROCESSOR_UNKNOWN,
668 CPU_EPT_FLAGS },
6305a203
L		 669 { ".3dnow", PROCESSOR_UNKNOWN,
670 CPU_3DNOW_FLAGS },
671 { ".3dnowa", PROCESSOR_UNKNOWN,
672 CPU_3DNOWA_FLAGS },
673 { ".padlock", PROCESSOR_UNKNOWN,
674 CPU_PADLOCK_FLAGS },
675 { ".pacifica", PROCESSOR_UNKNOWN,
676 CPU_SVME_FLAGS },
677 { ".svme", PROCESSOR_UNKNOWN,
678 CPU_SVME_FLAGS },
679 { ".sse4a", PROCESSOR_UNKNOWN,
680 CPU_SSE4A_FLAGS },
681 { ".abm", PROCESSOR_UNKNOWN,
682 CPU_ABM_FLAGS },
683 { ".sse5", PROCESSOR_UNKNOWN,
684 CPU_SSE5_FLAGS },
e413e4e9
AM		 685};
686
29b0f896
AM		 687const pseudo_typeS md_pseudo_table[] =
688{
689#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
690 {"align", s_align_bytes, 0},
691#else
692 {"align", s_align_ptwo, 0},
693#endif
694 {"arch", set_cpu_arch, 0},
695#ifndef I386COFF
696 {"bss", s_bss, 0},
697#endif
698 {"ffloat", float_cons, 'f'},
699 {"dfloat", float_cons, 'd'},
700 {"tfloat", float_cons, 'x'},
701 {"value", cons, 2},
d182319b 702 {"slong", signed_cons, 4},
29b0f896
AM		 703 {"noopt", s_ignore, 0},
704 {"optim", s_ignore, 0},
705 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
706 {"code16", set_code_flag, CODE_16BIT},
707 {"code32", set_code_flag, CODE_32BIT},
708 {"code64", set_code_flag, CODE_64BIT},
709 {"intel_syntax", set_intel_syntax, 1},
710 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 711 {"intel_mnemonic", set_intel_mnemonic, 1},
712 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 713 {"allow_index_reg", set_allow_index_reg, 1},
714 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 715 {"sse_check", set_sse_check, 0},
3b22753a
L		 716#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
717 {"largecomm", handle_large_common, 0},
07a53e5c 718#else
e3bb37b5 719 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 720 {"loc", dwarf2_directive_loc, 0},
721 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 722#endif
6482c264
NC		 723#ifdef TE_PE
724 {"secrel32", pe_directive_secrel, 0},
725#endif
29b0f896
AM		 726 {0, 0, 0}
727};
728
729/* For interface with expression (). */
730extern char *input_line_pointer;
731
732/* Hash table for instruction mnemonic lookup. */
733static struct hash_control *op_hash;
734
735/* Hash table for register lookup. */
736static struct hash_control *reg_hash;
737\f
252b5132 738void
e3bb37b5 739i386_align_code (fragS *fragP, int count)
252b5132 740{
ce8a8b2f
AM		 741 /* Various efficient no-op patterns for aligning code labels.
742 Note: Don't try to assemble the instructions in the comments.
743 0L and 0w are not legal. */
252b5132
RH		 744 static const char f32_1[] =
745 {0x90}; /* nop */
746 static const char f32_2[] =
ccc9c027 747 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 748 static const char f32_3[] =
749 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
750 static const char f32_4[] =
751 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
752 static const char f32_5[] =
753 {0x90, /* nop */
754 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
755 static const char f32_6[] =
756 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
757 static const char f32_7[] =
758 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
759 static const char f32_8[] =
760 {0x90, /* nop */
761 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
762 static const char f32_9[] =
763 {0x89,0xf6, /* movl %esi,%esi */
764 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
765 static const char f32_10[] =
766 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
767 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
768 static const char f32_11[] =
769 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
770 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
771 static const char f32_12[] =
772 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
773 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
774 static const char f32_13[] =
775 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_14[] =
778 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 780 static const char f16_3[] =
781 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 782 static const char f16_4[] =
783 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
784 static const char f16_5[] =
785 {0x90, /* nop */
786 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
787 static const char f16_6[] =
788 {0x89,0xf6, /* mov %si,%si */
789 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
790 static const char f16_7[] =
791 {0x8d,0x74,0x00, /* lea 0(%si),%si */
792 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
793 static const char f16_8[] =
794 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
795 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 796 static const char jump_31[] =
797 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
798 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
799 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
800 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 801 static const char *const f32_patt[] = {
802 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 803 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 804 };
805 static const char *const f16_patt[] = {
76bc74dc 806 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 807 };
ccc9c027
L		 808 /* nopl (%[re]ax) */
809 static const char alt_3[] =
810 {0x0f,0x1f,0x00};
811 /* nopl 0(%[re]ax) */
812 static const char alt_4[] =
813 {0x0f,0x1f,0x40,0x00};
814 /* nopl 0(%[re]ax,%[re]ax,1) */
815 static const char alt_5[] =
816 {0x0f,0x1f,0x44,0x00,0x00};
817 /* nopw 0(%[re]ax,%[re]ax,1) */
818 static const char alt_6[] =
819 {0x66,0x0f,0x1f,0x44,0x00,0x00};
820 /* nopl 0L(%[re]ax) */
821 static const char alt_7[] =
822 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
823 /* nopl 0L(%[re]ax,%[re]ax,1) */
824 static const char alt_8[] =
825 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
826 /* nopw 0L(%[re]ax,%[re]ax,1) */
827 static const char alt_9[] =
828 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
829 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
830 static const char alt_10[] =
831 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
832 /* data16
833 nopw %cs:0L(%[re]ax,%[re]ax,1) */
834 static const char alt_long_11[] =
835 {0x66,
836 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
837 /* data16
838 data16
839 nopw %cs:0L(%[re]ax,%[re]ax,1) */
840 static const char alt_long_12[] =
841 {0x66,
842 0x66,
843 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
844 /* data16
845 data16
846 data16
847 nopw %cs:0L(%[re]ax,%[re]ax,1) */
848 static const char alt_long_13[] =
849 {0x66,
850 0x66,
851 0x66,
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* data16
854 data16
855 data16
856 data16
857 nopw %cs:0L(%[re]ax,%[re]ax,1) */
858 static const char alt_long_14[] =
859 {0x66,
860 0x66,
861 0x66,
862 0x66,
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 /* data16
865 data16
866 data16
867 data16
868 data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_15[] =
871 {0x66,
872 0x66,
873 0x66,
874 0x66,
875 0x66,
876 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1)
878 nopw 0(%[re]ax,%[re]ax,1) */
879 static const char alt_short_11[] =
880 {0x0f,0x1f,0x44,0x00,0x00,
881 0x66,0x0f,0x1f,0x44,0x00,0x00};
882 /* nopw 0(%[re]ax,%[re]ax,1)
883 nopw 0(%[re]ax,%[re]ax,1) */
884 static const char alt_short_12[] =
885 {0x66,0x0f,0x1f,0x44,0x00,0x00,
886 0x66,0x0f,0x1f,0x44,0x00,0x00};
887 /* nopw 0(%[re]ax,%[re]ax,1)
888 nopl 0L(%[re]ax) */
889 static const char alt_short_13[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00,
891 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
892 /* nopl 0L(%[re]ax)
893 nopl 0L(%[re]ax) */
894 static const char alt_short_14[] =
895 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
896 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
897 /* nopl 0L(%[re]ax)
898 nopl 0L(%[re]ax,%[re]ax,1) */
899 static const char alt_short_15[] =
900 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
901 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 static const char *const alt_short_patt[] = {
903 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
904 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
905 alt_short_14, alt_short_15
906 };
907 static const char *const alt_long_patt[] = {
908 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
909 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
910 alt_long_14, alt_long_15
911 };
252b5132 912
76bc74dc
L		 913 /* Only align for at least a positive non-zero boundary. */
914 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 915 return;
3e73aa7c 916
ccc9c027
L		 917 /* We need to decide which NOP sequence to use for 32bit and
918 64bit. When -mtune= is used:
4eed87de 919
76bc74dc
L		 920 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
921 PROCESSOR_GENERIC32, f32_patt will be used.
922 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
923 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
924 alt_long_patt will be used.
925 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
926 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 927
76bc74dc
L		 928 When -mtune= isn't used, alt_long_patt will be used if
929 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
930 be used.
ccc9c027
L		 931
932 When -march= or .arch is used, we can't use anything beyond
933 cpu_arch_isa_flags. */
934
935 if (flag_code == CODE_16BIT)
936 {
ccc9c027 937 if (count > 8)
33fef721 938 {
76bc74dc
L		 939 memcpy (fragP->fr_literal + fragP->fr_fix,
940 jump_31, count);
941 /* Adjust jump offset. */
942 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 943 }
76bc74dc
L		 944 else
945 memcpy (fragP->fr_literal + fragP->fr_fix,
946 f16_patt[count - 1], count);
252b5132 947 }
33fef721 948 else
ccc9c027
L		 949 {
950 const char *const *patt = NULL;
951
952 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
953 {
954 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
955 switch (cpu_arch_tune)
956 {
957 case PROCESSOR_UNKNOWN:
958 /* We use cpu_arch_isa_flags to check if we SHOULD
959 optimize for Cpu686. */
40fb9820 960 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 961 patt = alt_long_patt;
ccc9c027
L		 962 else
963 patt = f32_patt;
964 break;
ccc9c027
L		 965 case PROCESSOR_PENTIUMPRO:
966 case PROCESSOR_PENTIUM4:
967 case PROCESSOR_NOCONA:
ef05d495 968 case PROCESSOR_CORE:
76bc74dc
L		 969 case PROCESSOR_CORE2:
970 case PROCESSOR_GENERIC64:
971 patt = alt_long_patt;
972 break;
ccc9c027
L		 973 case PROCESSOR_K6:
974 case PROCESSOR_ATHLON:
975 case PROCESSOR_K8:
4eed87de 976 case PROCESSOR_AMDFAM10:
ccc9c027
L		 977 patt = alt_short_patt;
978 break;
76bc74dc 979 case PROCESSOR_I386:
ccc9c027
L		 980 case PROCESSOR_I486:
981 case PROCESSOR_PENTIUM:
982 case PROCESSOR_GENERIC32:
983 patt = f32_patt;
984 break;
4eed87de 985 }
ccc9c027
L		 986 }
987 else
988 {
989 switch (cpu_arch_tune)
990 {
991 case PROCESSOR_UNKNOWN:
e6a14101 992 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 993 PROCESSOR_UNKNOWN. */
994 abort ();
995 break;
996
76bc74dc 997 case PROCESSOR_I386:
ccc9c027
L		 998 case PROCESSOR_I486:
999 case PROCESSOR_PENTIUM:
ccc9c027
L		 1000 case PROCESSOR_K6:
1001 case PROCESSOR_ATHLON:
1002 case PROCESSOR_K8:
4eed87de 1003 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1004 case PROCESSOR_GENERIC32:
1005 /* We use cpu_arch_isa_flags to check if we CAN optimize
1006 for Cpu686. */
40fb9820 1007 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 1008 patt = alt_short_patt;
1009 else
1010 patt = f32_patt;
1011 break;
76bc74dc
L		 1012 case PROCESSOR_PENTIUMPRO:
1013 case PROCESSOR_PENTIUM4:
1014 case PROCESSOR_NOCONA:
1015 case PROCESSOR_CORE:
ef05d495 1016 case PROCESSOR_CORE2:
40fb9820 1017 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 1018 patt = alt_long_patt;
1019 else
1020 patt = f32_patt;
1021 break;
1022 case PROCESSOR_GENERIC64:
76bc74dc 1023 patt = alt_long_patt;
ccc9c027 1024 break;
4eed87de 1025 }
ccc9c027
L		 1026 }
1027
76bc74dc
L		 1028 if (patt == f32_patt)
1029 {
1030 /* If the padding is less than 15 bytes, we use the normal
1031 ones. Otherwise, we use a jump instruction and adjust
1032 its offset. */
1033 if (count < 15)
1034 memcpy (fragP->fr_literal + fragP->fr_fix,
1035 patt[count - 1], count);
1036 else
1037 {
1038 memcpy (fragP->fr_literal + fragP->fr_fix,
1039 jump_31, count);
1040 /* Adjust jump offset. */
1041 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1042 }
1043 }
1044 else
1045 {
1046 /* Maximum length of an instruction is 15 byte. If the
1047 padding is greater than 15 bytes and we don't use jump,
1048 we have to break it into smaller pieces. */
1049 int padding = count;
1050 while (padding > 15)
1051 {
1052 padding -= 15;
1053 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1054 patt [14], 15);
1055 }
1056
1057 if (padding)
1058 memcpy (fragP->fr_literal + fragP->fr_fix,
1059 patt [padding - 1], padding);
1060 }
ccc9c027 1061 }
33fef721 1062 fragP->fr_var = count;
252b5132
RH		 1063}
1064
c6fb90c8 1065static INLINE int
0dfbf9d7 1066operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1067{
0dfbf9d7 1068 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1069 {
1070 case 3:
0dfbf9d7 1071 if (x->array[2])
c6fb90c8
L		 1072 return 0;
1073 case 2:
0dfbf9d7 1074 if (x->array[1])
c6fb90c8
L		 1075 return 0;
1076 case 1:
0dfbf9d7 1077 return !x->array[0];
c6fb90c8
L		 1078 default:
1079 abort ();
1080 }
40fb9820
L		 1081}
1082
c6fb90c8 1083static INLINE void
0dfbf9d7 1084operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1085{
0dfbf9d7 1086 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1087 {
1088 case 3:
0dfbf9d7 1089 x->array[2] = v;
c6fb90c8 1090 case 2:
0dfbf9d7 1091 x->array[1] = v;
c6fb90c8 1092 case 1:
0dfbf9d7 1093 x->array[0] = v;
c6fb90c8
L		 1094 break;
1095 default:
1096 abort ();
1097 }
1098}
40fb9820 1099
c6fb90c8 1100static INLINE int
0dfbf9d7
L		 1101operand_type_equal (const union i386_operand_type *x,
1102 const union i386_operand_type *y)
c6fb90c8 1103{
0dfbf9d7 1104 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1105 {
1106 case 3:
0dfbf9d7 1107 if (x->array[2] != y->array[2])
c6fb90c8
L		 1108 return 0;
1109 case 2:
0dfbf9d7 1110 if (x->array[1] != y->array[1])
c6fb90c8
L		 1111 return 0;
1112 case 1:
0dfbf9d7 1113 return x->array[0] == y->array[0];
c6fb90c8
L		 1114 break;
1115 default:
1116 abort ();
1117 }
1118}
40fb9820 1119
0dfbf9d7
L		 1120static INLINE int
1121cpu_flags_all_zero (const union i386_cpu_flags *x)
1122{
1123 switch (ARRAY_SIZE(x->array))
1124 {
1125 case 3:
1126 if (x->array[2])
1127 return 0;
1128 case 2:
1129 if (x->array[1])
1130 return 0;
1131 case 1:
1132 return !x->array[0];
1133 default:
1134 abort ();
1135 }
1136}
1137
1138static INLINE void
1139cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1140{
1141 switch (ARRAY_SIZE(x->array))
1142 {
1143 case 3:
1144 x->array[2] = v;
1145 case 2:
1146 x->array[1] = v;
1147 case 1:
1148 x->array[0] = v;
1149 break;
1150 default:
1151 abort ();
1152 }
1153}
1154
1155static INLINE int
1156cpu_flags_equal (const union i386_cpu_flags *x,
1157 const union i386_cpu_flags *y)
1158{
1159 switch (ARRAY_SIZE(x->array))
1160 {
1161 case 3:
1162 if (x->array[2] != y->array[2])
1163 return 0;
1164 case 2:
1165 if (x->array[1] != y->array[1])
1166 return 0;
1167 case 1:
1168 return x->array[0] == y->array[0];
1169 break;
1170 default:
1171 abort ();
1172 }
1173}
c6fb90c8
L		 1174
1175static INLINE int
1176cpu_flags_check_cpu64 (i386_cpu_flags f)
1177{
1178 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1179 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1180}
1181
c6fb90c8
L		 1182static INLINE i386_cpu_flags
1183cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1184{
c6fb90c8
L		 1185 switch (ARRAY_SIZE (x.array))
1186 {
1187 case 3:
1188 x.array [2] &= y.array [2];
1189 case 2:
1190 x.array [1] &= y.array [1];
1191 case 1:
1192 x.array [0] &= y.array [0];
1193 break;
1194 default:
1195 abort ();
1196 }
1197 return x;
1198}
40fb9820 1199
c6fb90c8
L		 1200static INLINE i386_cpu_flags
1201cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1202{
c6fb90c8 1203 switch (ARRAY_SIZE (x.array))
40fb9820 1204 {
c6fb90c8
L		 1205 case 3:
1206 x.array [2] |= y.array [2];
1207 case 2:
1208 x.array [1] |= y.array [1];
1209 case 1:
1210 x.array [0] |= y.array [0];
40fb9820
L		 1211 break;
1212 default:
1213 abort ();
1214 }
40fb9820
L		 1215 return x;
1216}
1217
c0f3af97
L		 1218#define CPU_FLAGS_ARCH_MATCH 0x1
1219#define CPU_FLAGS_64BIT_MATCH 0x2
1220
1221#define CPU_FLAGS_32BIT_MATCH CPU_FLAGS_ARCH_MATCH
1222#define CPU_FLAGS_PERFECT_MATCH \
1223 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1224
1225/* Return CPU flags match bits. */
3629bb00 1226
40fb9820 1227static int
c0f3af97 1228cpu_flags_match (const template *t)
40fb9820 1229{
c0f3af97
L		 1230 i386_cpu_flags x = t->cpu_flags;
1231 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1232
1233 x.bitfield.cpu64 = 0;
1234 x.bitfield.cpuno64 = 0;
1235
0dfbf9d7 1236 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1237 {
1238 /* This instruction is available on all archs. */
1239 match |= CPU_FLAGS_32BIT_MATCH;
1240 }
3629bb00
L		 1241 else
1242 {
c0f3af97 1243 /* This instruction is available only on some archs. */
3629bb00
L		 1244 i386_cpu_flags cpu = cpu_arch_flags;
1245
1246 cpu.bitfield.cpu64 = 0;
1247 cpu.bitfield.cpuno64 = 0;
1248 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1249 if (!cpu_flags_all_zero (&cpu))
1250 {
1251 /* Check SSE2AVX */
1252 if (!t->opcode_modifier.sse2avx || sse2avx)
1253 match |= CPU_FLAGS_32BIT_MATCH;
1254 }
3629bb00 1255 }
c0f3af97 1256 return match;
40fb9820
L		 1257}
1258
c6fb90c8
L		 1259static INLINE i386_operand_type
1260operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1261{
c6fb90c8
L		 1262 switch (ARRAY_SIZE (x.array))
1263 {
1264 case 3:
1265 x.array [2] &= y.array [2];
1266 case 2:
1267 x.array [1] &= y.array [1];
1268 case 1:
1269 x.array [0] &= y.array [0];
1270 break;
1271 default:
1272 abort ();
1273 }
1274 return x;
40fb9820
L		 1275}
1276
c6fb90c8
L		 1277static INLINE i386_operand_type
1278operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1279{
c6fb90c8 1280 switch (ARRAY_SIZE (x.array))
40fb9820 1281 {
c6fb90c8
L		 1282 case 3:
1283 x.array [2] |= y.array [2];
1284 case 2:
1285 x.array [1] |= y.array [1];
1286 case 1:
1287 x.array [0] |= y.array [0];
40fb9820
L		 1288 break;
1289 default:
1290 abort ();
1291 }
c6fb90c8
L		 1292 return x;
1293}
40fb9820 1294
c6fb90c8
L		 1295static INLINE i386_operand_type
1296operand_type_xor (i386_operand_type x, i386_operand_type y)
1297{
1298 switch (ARRAY_SIZE (x.array))
1299 {
1300 case 3:
1301 x.array [2] ^= y.array [2];
1302 case 2:
1303 x.array [1] ^= y.array [1];
1304 case 1:
1305 x.array [0] ^= y.array [0];
1306 break;
1307 default:
1308 abort ();
1309 }
40fb9820
L		 1310 return x;
1311}
1312
1313static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1314static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1315static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1316static const i386_operand_type inoutportreg
1317 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1318static const i386_operand_type reg16_inoutportreg
1319 = OPERAND_TYPE_REG16_INOUTPORTREG;
1320static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1321static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1322static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1323static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1324static const i386_operand_type anydisp
1325 = OPERAND_TYPE_ANYDISP;
40fb9820 1326static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1327static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1328static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1329static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1330static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1331static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1332static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1333static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1334static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1335static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1336static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
c0f3af97 1337static const i386_operand_type vex_imm4 = OPERAND_TYPE_VEX_IMM4;
40fb9820
L		 1338
1339enum operand_type
1340{
1341 reg,
40fb9820
L		 1342 imm,
1343 disp,
1344 anymem
1345};
1346
c6fb90c8 1347static INLINE int
40fb9820
L		 1348operand_type_check (i386_operand_type t, enum operand_type c)
1349{
1350 switch (c)
1351 {
1352 case reg:
1353 return (t.bitfield.reg8
1354 || t.bitfield.reg16
1355 || t.bitfield.reg32
1356 || t.bitfield.reg64);
1357
40fb9820
L		 1358 case imm:
1359 return (t.bitfield.imm8
1360 || t.bitfield.imm8s
1361 || t.bitfield.imm16
1362 || t.bitfield.imm32
1363 || t.bitfield.imm32s
1364 || t.bitfield.imm64);
1365
1366 case disp:
1367 return (t.bitfield.disp8
1368 || t.bitfield.disp16
1369 || t.bitfield.disp32
1370 || t.bitfield.disp32s
1371 || t.bitfield.disp64);
1372
1373 case anymem:
1374 return (t.bitfield.disp8
1375 || t.bitfield.disp16
1376 || t.bitfield.disp32
1377 || t.bitfield.disp32s
1378 || t.bitfield.disp64
1379 || t.bitfield.baseindex);
1380
1381 default:
1382 abort ();
1383 }
2cfe26b6
AM		 1384
1385 return 0;
40fb9820
L		 1386}
1387
5c07affc
L		 1388/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1389 operand J for instruction template T. */
1390
1391static INLINE int
1392match_reg_size (const template *t, unsigned int j)
1393{
1394 return !((i.types[j].bitfield.byte
1395 && !t->operand_types[j].bitfield.byte)
1396 || (i.types[j].bitfield.word
1397 && !t->operand_types[j].bitfield.word)
1398 || (i.types[j].bitfield.dword
1399 && !t->operand_types[j].bitfield.dword)
1400 || (i.types[j].bitfield.qword
1401 && !t->operand_types[j].bitfield.qword));
1402}
1403
1404/* Return 1 if there is no conflict in any size on operand J for
1405 instruction template T. */
1406
1407static INLINE int
1408match_mem_size (const template *t, unsigned int j)
1409{
1410 return (match_reg_size (t, j)
1411 && !((i.types[j].bitfield.unspecified
1412 && !t->operand_types[j].bitfield.unspecified)
1413 || (i.types[j].bitfield.fword
1414 && !t->operand_types[j].bitfield.fword)
1415 || (i.types[j].bitfield.tbyte
1416 && !t->operand_types[j].bitfield.tbyte)
1417 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1418 && !t->operand_types[j].bitfield.xmmword)
1419 || (i.types[j].bitfield.ymmword
1420 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1421}
1422
1423/* Return 1 if there is no size conflict on any operands for
1424 instruction template T. */
1425
1426static INLINE int
1427operand_size_match (const template *t)
1428{
1429 unsigned int j;
1430 int match = 1;
1431
1432 /* Don't check jump instructions. */
1433 if (t->opcode_modifier.jump
1434 || t->opcode_modifier.jumpbyte
1435 || t->opcode_modifier.jumpdword
1436 || t->opcode_modifier.jumpintersegment)
1437 return match;
1438
1439 /* Check memory and accumulator operand size. */
1440 for (j = 0; j < i.operands; j++)
1441 {
1442 if (t->operand_types[j].bitfield.anysize)
1443 continue;
1444
1445 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1446 {
1447 match = 0;
1448 break;
1449 }
1450
1451 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1452 {
1453 match = 0;
1454 break;
1455 }
1456 }
1457
1458 if (match
1459 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1460 return match;
1461
1462 /* Check reverse. */
1463 assert (i.operands == 2);
1464
1465 match = 1;
1466 for (j = 0; j < 2; j++)
1467 {
1468 if (t->operand_types[j].bitfield.acc
1469 && !match_reg_size (t, j ? 0 : 1))
1470 {
1471 match = 0;
1472 break;
1473 }
1474
1475 if (i.types[j].bitfield.mem
1476 && !match_mem_size (t, j ? 0 : 1))
1477 {
1478 match = 0;
1479 break;
1480 }
1481 }
1482
1483 return match;
1484}
1485
c6fb90c8 1486static INLINE int
40fb9820
L		 1487operand_type_match (i386_operand_type overlap,
1488 i386_operand_type given)
1489{
1490 i386_operand_type temp = overlap;
1491
1492 temp.bitfield.jumpabsolute = 0;
7d5e4556 1493 temp.bitfield.unspecified = 0;
5c07affc
L		 1494 temp.bitfield.byte = 0;
1495 temp.bitfield.word = 0;
1496 temp.bitfield.dword = 0;
1497 temp.bitfield.fword = 0;
1498 temp.bitfield.qword = 0;
1499 temp.bitfield.tbyte = 0;
1500 temp.bitfield.xmmword = 0;
c0f3af97 1501 temp.bitfield.ymmword = 0;
0dfbf9d7 1502 if (operand_type_all_zero (&temp))
40fb9820
L		 1503 return 0;
1504
1505 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1506 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1507}
1508
7d5e4556 1509/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1510 unless the expected operand type register overlap is null.
1511 Note that Acc in a template matches every size of reg. */
1512
c6fb90c8 1513static INLINE int
40fb9820
L		 1514operand_type_register_match (i386_operand_type m0,
1515 i386_operand_type g0,
1516 i386_operand_type t0,
1517 i386_operand_type m1,
1518 i386_operand_type g1,
1519 i386_operand_type t1)
1520{
1521 if (!operand_type_check (g0, reg))
1522 return 1;
1523
1524 if (!operand_type_check (g1, reg))
1525 return 1;
1526
1527 if (g0.bitfield.reg8 == g1.bitfield.reg8
1528 && g0.bitfield.reg16 == g1.bitfield.reg16
1529 && g0.bitfield.reg32 == g1.bitfield.reg32
1530 && g0.bitfield.reg64 == g1.bitfield.reg64)
1531 return 1;
1532
1533 if (m0.bitfield.acc)
1534 {
1535 t0.bitfield.reg8 = 1;
1536 t0.bitfield.reg16 = 1;
1537 t0.bitfield.reg32 = 1;
1538 t0.bitfield.reg64 = 1;
1539 }
1540
1541 if (m1.bitfield.acc)
1542 {
1543 t1.bitfield.reg8 = 1;
1544 t1.bitfield.reg16 = 1;
1545 t1.bitfield.reg32 = 1;
1546 t1.bitfield.reg64 = 1;
1547 }
1548
1549 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1550 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1551 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1552 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1553}
1554
252b5132 1555static INLINE unsigned int
40fb9820 1556mode_from_disp_size (i386_operand_type t)
252b5132 1557{
40fb9820
L		 1558 if (t.bitfield.disp8)
1559 return 1;
1560 else if (t.bitfield.disp16
1561 || t.bitfield.disp32
1562 || t.bitfield.disp32s)
1563 return 2;
1564 else
1565 return 0;
252b5132
RH		 1566}
1567
1568static INLINE int
e3bb37b5 1569fits_in_signed_byte (offsetT num)
252b5132
RH		 1570{
1571 return (num >= -128) && (num <= 127);
47926f60 1572}
252b5132
RH		 1573
1574static INLINE int
e3bb37b5 1575fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1576{
1577 return (num & 0xff) == num;
47926f60 1578}
252b5132
RH		 1579
1580static INLINE int
e3bb37b5 1581fits_in_unsigned_word (offsetT num)
252b5132
RH		 1582{
1583 return (num & 0xffff) == num;
47926f60 1584}
252b5132
RH		 1585
1586static INLINE int
e3bb37b5 1587fits_in_signed_word (offsetT num)
252b5132
RH		 1588{
1589 return (-32768 <= num) && (num <= 32767);
47926f60 1590}
2a962e6d 1591
3e73aa7c 1592static INLINE int
e3bb37b5 1593fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1594{
1595#ifndef BFD64
1596 return 1;
1597#else
1598 return (!(((offsetT) -1 << 31) & num)
1599 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1600#endif
1601} /* fits_in_signed_long() */
2a962e6d 1602
3e73aa7c 1603static INLINE int
e3bb37b5 1604fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1605{
1606#ifndef BFD64
1607 return 1;
1608#else
1609 return (num & (((offsetT) 2 << 31) - 1)) == num;
1610#endif
1611} /* fits_in_unsigned_long() */
252b5132 1612
c0f3af97
L		 1613static INLINE int
1614fits_in_imm4 (offsetT num)
1615{
1616 return (num & 0xf) == num;
1617}
1618
40fb9820 1619static i386_operand_type
e3bb37b5 1620smallest_imm_type (offsetT num)
252b5132 1621{
40fb9820
L		 1622 i386_operand_type t;
1623
0dfbf9d7 1624 operand_type_set (&t, 0);
40fb9820
L		 1625 t.bitfield.imm64 = 1;
1626
1627 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1628 {
1629 /* This code is disabled on the 486 because all the Imm1 forms
1630 in the opcode table are slower on the i486. They're the
1631 versions with the implicitly specified single-position
1632 displacement, which has another syntax if you really want to
1633 use that form. */
40fb9820
L		 1634 t.bitfield.imm1 = 1;
1635 t.bitfield.imm8 = 1;
1636 t.bitfield.imm8s = 1;
1637 t.bitfield.imm16 = 1;
1638 t.bitfield.imm32 = 1;
1639 t.bitfield.imm32s = 1;
1640 }
1641 else if (fits_in_signed_byte (num))
1642 {
1643 t.bitfield.imm8 = 1;
1644 t.bitfield.imm8s = 1;
1645 t.bitfield.imm16 = 1;
1646 t.bitfield.imm32 = 1;
1647 t.bitfield.imm32s = 1;
1648 }
1649 else if (fits_in_unsigned_byte (num))
1650 {
1651 t.bitfield.imm8 = 1;
1652 t.bitfield.imm16 = 1;
1653 t.bitfield.imm32 = 1;
1654 t.bitfield.imm32s = 1;
1655 }
1656 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1657 {
1658 t.bitfield.imm16 = 1;
1659 t.bitfield.imm32 = 1;
1660 t.bitfield.imm32s = 1;
1661 }
1662 else if (fits_in_signed_long (num))
1663 {
1664 t.bitfield.imm32 = 1;
1665 t.bitfield.imm32s = 1;
1666 }
1667 else if (fits_in_unsigned_long (num))
1668 t.bitfield.imm32 = 1;
1669
1670 return t;
47926f60 1671}
252b5132 1672
847f7ad4 1673static offsetT
e3bb37b5 1674offset_in_range (offsetT val, int size)
847f7ad4 1675{
508866be 1676 addressT mask;
ba2adb93 1677
847f7ad4
AM		 1678 switch (size)
1679 {
508866be
L		 1680 case 1: mask = ((addressT) 1 << 8) - 1; break;
1681 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1682 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1683#ifdef BFD64
1684 case 8: mask = ((addressT) 2 << 63) - 1; break;
1685#endif
47926f60 1686 default: abort ();
847f7ad4
AM		 1687 }
1688
ba2adb93 1689 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1690 if (!use_rela_relocations)
1691 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1692 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1693
47926f60 1694 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1695 {
1696 char buf1[40], buf2[40];
1697
1698 sprint_value (buf1, val);
1699 sprint_value (buf2, val & mask);
1700 as_warn (_("%s shortened to %s"), buf1, buf2);
1701 }
1702 return val & mask;
1703}
1704
252b5132
RH		 1705/* Returns 0 if attempting to add a prefix where one from the same
1706 class already exists, 1 if non rep/repne added, 2 if rep/repne
1707 added. */
1708static int
e3bb37b5 1709add_prefix (unsigned int prefix)
252b5132
RH		 1710{
1711 int ret = 1;
b1905489 1712 unsigned int q;
252b5132 1713
29b0f896
AM		 1714 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1715 && flag_code == CODE_64BIT)
b1905489 1716 {
161a04f6
L		 1717 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1718 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1719 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1720 ret = 0;
1721 q = REX_PREFIX;
1722 }
3e73aa7c 1723 else
b1905489
JB		 1724 {
1725 switch (prefix)
1726 {
1727 default:
1728 abort ();
1729
1730 case CS_PREFIX_OPCODE:
1731 case DS_PREFIX_OPCODE:
1732 case ES_PREFIX_OPCODE:
1733 case FS_PREFIX_OPCODE:
1734 case GS_PREFIX_OPCODE:
1735 case SS_PREFIX_OPCODE:
1736 q = SEG_PREFIX;
1737 break;
1738
1739 case REPNE_PREFIX_OPCODE:
1740 case REPE_PREFIX_OPCODE:
1741 ret = 2;
1742 /* fall thru */
1743 case LOCK_PREFIX_OPCODE:
1744 q = LOCKREP_PREFIX;
1745 break;
1746
1747 case FWAIT_OPCODE:
1748 q = WAIT_PREFIX;
1749 break;
1750
1751 case ADDR_PREFIX_OPCODE:
1752 q = ADDR_PREFIX;
1753 break;
1754
1755 case DATA_PREFIX_OPCODE:
1756 q = DATA_PREFIX;
1757 break;
1758 }
1759 if (i.prefix[q] != 0)
1760 ret = 0;
1761 }
252b5132 1762
b1905489 1763 if (ret)
252b5132 1764 {
b1905489
JB		 1765 if (!i.prefix[q])
1766 ++i.prefixes;
1767 i.prefix[q] |= prefix;
252b5132 1768 }
b1905489
JB		 1769 else
1770 as_bad (_("same type of prefix used twice"));
252b5132 1771
252b5132
RH		 1772 return ret;
1773}
1774
1775static void
e3bb37b5 1776set_code_flag (int value)
eecb386c 1777{
3e73aa7c 1778 flag_code = value;
40fb9820
L		 1779 if (flag_code == CODE_64BIT)
1780 {
1781 cpu_arch_flags.bitfield.cpu64 = 1;
1782 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1783 }
1784 else
1785 {
1786 cpu_arch_flags.bitfield.cpu64 = 0;
1787 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1788 }
1789 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1790 {
1791 as_bad (_("64bit mode not supported on this CPU."));
1792 }
40fb9820 1793 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1794 {
1795 as_bad (_("32bit mode not supported on this CPU."));
1796 }
eecb386c
AM		 1797 stackop_size = '\0';
1798}
1799
1800static void
e3bb37b5 1801set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1802{
3e73aa7c 1803 flag_code = new_code_flag;
40fb9820
L		 1804 if (flag_code != CODE_16BIT)
1805 abort ();
1806 cpu_arch_flags.bitfield.cpu64 = 0;
1807 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1808 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1809}
1810
1811static void
e3bb37b5 1812set_intel_syntax (int syntax_flag)
252b5132
RH		 1813{
1814 /* Find out if register prefixing is specified. */
1815 int ask_naked_reg = 0;
1816
1817 SKIP_WHITESPACE ();
29b0f896 1818 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1819 {
1820 char *string = input_line_pointer;
1821 int e = get_symbol_end ();
1822
47926f60 1823 if (strcmp (string, "prefix") == 0)
252b5132 1824 ask_naked_reg = 1;
47926f60 1825 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1826 ask_naked_reg = -1;
1827 else
d0b47220 1828 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1829 *input_line_pointer = e;
1830 }
1831 demand_empty_rest_of_line ();
c3332e24 1832
252b5132
RH		 1833 intel_syntax = syntax_flag;
1834
1835 if (ask_naked_reg == 0)
f86103b7
AM		 1836 allow_naked_reg = (intel_syntax
1837 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1838 else
1839 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1840
e4a3b5a4 1841 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1842 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1843 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1844}
1845
1efbbeb4
L		 1846static void
1847set_intel_mnemonic (int mnemonic_flag)
1848{
e1d4d893 1849 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1850}
1851
db51cc60
L		 1852static void
1853set_allow_index_reg (int flag)
1854{
1855 allow_index_reg = flag;
1856}
1857
cb19c032
L		 1858static void
1859set_sse_check (int dummy ATTRIBUTE_UNUSED)
1860{
1861 SKIP_WHITESPACE ();
1862
1863 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1864 {
1865 char *string = input_line_pointer;
1866 int e = get_symbol_end ();
1867
1868 if (strcmp (string, "none") == 0)
1869 sse_check = sse_check_none;
1870 else if (strcmp (string, "warning") == 0)
1871 sse_check = sse_check_warning;
1872 else if (strcmp (string, "error") == 0)
1873 sse_check = sse_check_error;
1874 else
1875 as_bad (_("bad argument to sse_check directive."));
1876 *input_line_pointer = e;
1877 }
1878 else
1879 as_bad (_("missing argument for sse_check directive"));
1880
1881 demand_empty_rest_of_line ();
1882}
1883
e413e4e9 1884static void
e3bb37b5 1885set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1886{
47926f60 1887 SKIP_WHITESPACE ();
e413e4e9 1888
29b0f896 1889 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1890 {
1891 char *string = input_line_pointer;
1892 int e = get_symbol_end ();
9103f4f4 1893 unsigned int i;
40fb9820 1894 i386_cpu_flags flags;
e413e4e9 1895
9103f4f4 1896 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1897 {
1898 if (strcmp (string, cpu_arch[i].name) == 0)
1899 {
5c6af06e
JB		 1900 if (*string != '.')
1901 {
1902 cpu_arch_name = cpu_arch[i].name;
1903 cpu_sub_arch_name = NULL;
40fb9820
L		 1904 cpu_arch_flags = cpu_arch[i].flags;
1905 if (flag_code == CODE_64BIT)
1906 {
1907 cpu_arch_flags.bitfield.cpu64 = 1;
1908 cpu_arch_flags.bitfield.cpuno64 = 0;
1909 }
1910 else
1911 {
1912 cpu_arch_flags.bitfield.cpu64 = 0;
1913 cpu_arch_flags.bitfield.cpuno64 = 1;
1914 }
ccc9c027 1915 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1916 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1917 if (!cpu_arch_tune_set)
1918 {
1919 cpu_arch_tune = cpu_arch_isa;
1920 cpu_arch_tune_flags = cpu_arch_isa_flags;
1921 }
5c6af06e
JB		 1922 break;
1923 }
40fb9820 1924
c6fb90c8
L		 1925 flags = cpu_flags_or (cpu_arch_flags,
1926 cpu_arch[i].flags);
0dfbf9d7 1927 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1928 {
6305a203
L		 1929 if (cpu_sub_arch_name)
1930 {
1931 char *name = cpu_sub_arch_name;
1932 cpu_sub_arch_name = concat (name,
1933 cpu_arch[i].name,
1bf57e9f 1934 (const char *) NULL);
6305a203
L		 1935 free (name);
1936 }
1937 else
1938 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1939 cpu_arch_flags = flags;
5c6af06e
JB		 1940 }
1941 *input_line_pointer = e;
1942 demand_empty_rest_of_line ();
1943 return;
e413e4e9
AM		 1944 }
1945 }
9103f4f4 1946 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1947 as_bad (_("no such architecture: `%s'"), string);
1948
1949 *input_line_pointer = e;
1950 }
1951 else
1952 as_bad (_("missing cpu architecture"));
1953
fddf5b5b
AM		 1954 no_cond_jump_promotion = 0;
1955 if (*input_line_pointer == ','
29b0f896 1956 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1957 {
1958 char *string = ++input_line_pointer;
1959 int e = get_symbol_end ();
1960
1961 if (strcmp (string, "nojumps") == 0)
1962 no_cond_jump_promotion = 1;
1963 else if (strcmp (string, "jumps") == 0)
1964 ;
1965 else
1966 as_bad (_("no such architecture modifier: `%s'"), string);
1967
1968 *input_line_pointer = e;
1969 }
1970
e413e4e9
AM		 1971 demand_empty_rest_of_line ();
1972}
1973
b9d79e03
JH		 1974unsigned long
1975i386_mach ()
1976{
1977 if (!strcmp (default_arch, "x86_64"))
1978 return bfd_mach_x86_64;
1979 else if (!strcmp (default_arch, "i386"))
1980 return bfd_mach_i386_i386;
1981 else
1982 as_fatal (_("Unknown architecture"));
1983}
b9d79e03 1984\f
252b5132
RH		 1985void
1986md_begin ()
1987{
1988 const char *hash_err;
1989
47926f60 1990 /* Initialize op_hash hash table. */
252b5132
RH		 1991 op_hash = hash_new ();
1992
1993 {
29b0f896
AM		 1994 const template *optab;
1995 templates *core_optab;
252b5132 1996
47926f60
KH		 1997 /* Setup for loop. */
1998 optab = i386_optab;
252b5132
RH		 1999 core_optab = (templates *) xmalloc (sizeof (templates));
2000 core_optab->start = optab;
2001
2002 while (1)
2003 {
2004 ++optab;
2005 if (optab->name == NULL
2006 || strcmp (optab->name, (optab - 1)->name) != 0)
2007 {
2008 /* different name --> ship out current template list;
47926f60 2009 add to hash table; & begin anew. */
252b5132
RH		 2010 core_optab->end = optab;
2011 hash_err = hash_insert (op_hash,
2012 (optab - 1)->name,
5a49b8ac 2013 (void *) core_optab);
252b5132
RH		 2014 if (hash_err)
2015 {
252b5132
RH		 2016 as_fatal (_("Internal Error: Can't hash %s: %s"),
2017 (optab - 1)->name,
2018 hash_err);
2019 }
2020 if (optab->name == NULL)
2021 break;
2022 core_optab = (templates *) xmalloc (sizeof (templates));
2023 core_optab->start = optab;
2024 }
2025 }
2026 }
2027
47926f60 2028 /* Initialize reg_hash hash table. */
252b5132
RH		 2029 reg_hash = hash_new ();
2030 {
29b0f896 2031 const reg_entry *regtab;
c3fe08fa 2032 unsigned int regtab_size = i386_regtab_size;
252b5132 2033
c3fe08fa 2034 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2035 {
5a49b8ac 2036 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2037 if (hash_err)
3e73aa7c
JH		 2038 as_fatal (_("Internal Error: Can't hash %s: %s"),
2039 regtab->reg_name,
2040 hash_err);
252b5132
RH		 2041 }
2042 }
2043
47926f60 2044 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2045 {
29b0f896
AM		 2046 int c;
2047 char *p;
252b5132
RH		 2048
2049 for (c = 0; c < 256; c++)
2050 {
3882b010 2051 if (ISDIGIT (c))
252b5132
RH		 2052 {
2053 digit_chars[c] = c;
2054 mnemonic_chars[c] = c;
2055 register_chars[c] = c;
2056 operand_chars[c] = c;
2057 }
3882b010 2058 else if (ISLOWER (c))
252b5132
RH		 2059 {
2060 mnemonic_chars[c] = c;
2061 register_chars[c] = c;
2062 operand_chars[c] = c;
2063 }
3882b010 2064 else if (ISUPPER (c))
252b5132 2065 {
3882b010 2066 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2067 register_chars[c] = mnemonic_chars[c];
2068 operand_chars[c] = c;
2069 }
2070
3882b010 2071 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2072 identifier_chars[c] = c;
2073 else if (c >= 128)
2074 {
2075 identifier_chars[c] = c;
2076 operand_chars[c] = c;
2077 }
2078 }
2079
2080#ifdef LEX_AT
2081 identifier_chars['@'] = '@';
32137342
NC		 2082#endif
2083#ifdef LEX_QM
2084 identifier_chars['?'] = '?';
2085 operand_chars['?'] = '?';
252b5132 2086#endif
252b5132 2087 digit_chars['-'] = '-';
c0f3af97 2088 mnemonic_chars['_'] = '_';
791fe849 2089 mnemonic_chars['-'] = '-';
0003779b 2090 mnemonic_chars['.'] = '.';
252b5132
RH		 2091 identifier_chars['_'] = '_';
2092 identifier_chars['.'] = '.';
2093
2094 for (p = operand_special_chars; *p != '\0'; p++)
2095 operand_chars[(unsigned char) *p] = *p;
2096 }
2097
2098#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2099 if (IS_ELF)
252b5132
RH		 2100 {
2101 record_alignment (text_section, 2);
2102 record_alignment (data_section, 2);
2103 record_alignment (bss_section, 2);
2104 }
2105#endif
a4447b93
RH		 2106
2107 if (flag_code == CODE_64BIT)
2108 {
2109 x86_dwarf2_return_column = 16;
2110 x86_cie_data_alignment = -8;
2111 }
2112 else
2113 {
2114 x86_dwarf2_return_column = 8;
2115 x86_cie_data_alignment = -4;
2116 }
252b5132
RH		 2117}
2118
2119void
e3bb37b5 2120i386_print_statistics (FILE *file)
252b5132
RH		 2121{
2122 hash_print_statistics (file, "i386 opcode", op_hash);
2123 hash_print_statistics (file, "i386 register", reg_hash);
2124}
2125\f
252b5132
RH		 2126#ifdef DEBUG386
2127
ce8a8b2f 2128/* Debugging routines for md_assemble. */
e3bb37b5 2129static void pte (template *);
40fb9820 2130static void pt (i386_operand_type);
e3bb37b5
L		 2131static void pe (expressionS *);
2132static void ps (symbolS *);
252b5132
RH		 2133
2134static void
e3bb37b5 2135pi (char *line, i386_insn *x)
252b5132 2136{
09f131f2 2137 unsigned int i;
252b5132
RH		 2138
2139 fprintf (stdout, "%s: template ", line);
2140 pte (&x->tm);
09f131f2
JH		 2141 fprintf (stdout, " address: base %s index %s scale %x\n",
2142 x->base_reg ? x->base_reg->reg_name : "none",
2143 x->index_reg ? x->index_reg->reg_name : "none",
2144 x->log2_scale_factor);
2145 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2146 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2147 fprintf (stdout, " sib: base %x index %x scale %x\n",
2148 x->sib.base, x->sib.index, x->sib.scale);
2149 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2150 (x->rex & REX_W) != 0,
2151 (x->rex & REX_R) != 0,
2152 (x->rex & REX_X) != 0,
2153 (x->rex & REX_B) != 0);
85f10a01
MM		 2154 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2155 x->drex.reg, x->drex.rex);
252b5132
RH		 2156 for (i = 0; i < x->operands; i++)
2157 {
2158 fprintf (stdout, " #%d: ", i + 1);
2159 pt (x->types[i]);
2160 fprintf (stdout, "\n");
40fb9820
L		 2161 if (x->types[i].bitfield.reg8
2162 || x->types[i].bitfield.reg16
2163 || x->types[i].bitfield.reg32
2164 || x->types[i].bitfield.reg64
2165 || x->types[i].bitfield.regmmx
2166 || x->types[i].bitfield.regxmm
c0f3af97 2167 || x->types[i].bitfield.regymm
40fb9820
L		 2168 || x->types[i].bitfield.sreg2
2169 || x->types[i].bitfield.sreg3
2170 || x->types[i].bitfield.control
2171 || x->types[i].bitfield.debug
2172 || x->types[i].bitfield.test)
520dc8e8 2173 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2174 if (operand_type_check (x->types[i], imm))
520dc8e8 2175 pe (x->op[i].imms);
40fb9820 2176 if (operand_type_check (x->types[i], disp))
520dc8e8 2177 pe (x->op[i].disps);
252b5132
RH		 2178 }
2179}
2180
2181static void
e3bb37b5 2182pte (template *t)
252b5132 2183{
09f131f2 2184 unsigned int i;
252b5132 2185 fprintf (stdout, " %d operands ", t->operands);
47926f60 2186 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2187 if (t->extension_opcode != None)
2188 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2189 if (t->opcode_modifier.d)
252b5132 2190 fprintf (stdout, "D");
40fb9820 2191 if (t->opcode_modifier.w)
252b5132
RH		 2192 fprintf (stdout, "W");
2193 fprintf (stdout, "\n");
2194 for (i = 0; i < t->operands; i++)
2195 {
2196 fprintf (stdout, " #%d type ", i + 1);
2197 pt (t->operand_types[i]);
2198 fprintf (stdout, "\n");
2199 }
2200}
2201
2202static void
e3bb37b5 2203pe (expressionS *e)
252b5132 2204{
24eab124 2205 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2206 fprintf (stdout, " add_number %ld (%lx)\n",
2207 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2208 if (e->X_add_symbol)
2209 {
2210 fprintf (stdout, " add_symbol ");
2211 ps (e->X_add_symbol);
2212 fprintf (stdout, "\n");
2213 }
2214 if (e->X_op_symbol)
2215 {
2216 fprintf (stdout, " op_symbol ");
2217 ps (e->X_op_symbol);
2218 fprintf (stdout, "\n");
2219 }
2220}
2221
2222static void
e3bb37b5 2223ps (symbolS *s)
252b5132
RH		 2224{
2225 fprintf (stdout, "%s type %s%s",
2226 S_GET_NAME (s),
2227 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2228 segment_name (S_GET_SEGMENT (s)));
2229}
2230
7b81dfbb 2231static struct type_name
252b5132 2232 {
40fb9820
L		 2233 i386_operand_type mask;
2234 const char *name;
252b5132 2235 }
7b81dfbb 2236const type_names[] =
252b5132 2237{
40fb9820
L		 2238 { OPERAND_TYPE_REG8, "r8" },
2239 { OPERAND_TYPE_REG16, "r16" },
2240 { OPERAND_TYPE_REG32, "r32" },
2241 { OPERAND_TYPE_REG64, "r64" },
2242 { OPERAND_TYPE_IMM8, "i8" },
2243 { OPERAND_TYPE_IMM8, "i8s" },
2244 { OPERAND_TYPE_IMM16, "i16" },
2245 { OPERAND_TYPE_IMM32, "i32" },
2246 { OPERAND_TYPE_IMM32S, "i32s" },
2247 { OPERAND_TYPE_IMM64, "i64" },
2248 { OPERAND_TYPE_IMM1, "i1" },
2249 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2250 { OPERAND_TYPE_DISP8, "d8" },
2251 { OPERAND_TYPE_DISP16, "d16" },
2252 { OPERAND_TYPE_DISP32, "d32" },
2253 { OPERAND_TYPE_DISP32S, "d32s" },
2254 { OPERAND_TYPE_DISP64, "d64" },
2255 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2256 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2257 { OPERAND_TYPE_CONTROL, "control reg" },
2258 { OPERAND_TYPE_TEST, "test reg" },
2259 { OPERAND_TYPE_DEBUG, "debug reg" },
2260 { OPERAND_TYPE_FLOATREG, "FReg" },
2261 { OPERAND_TYPE_FLOATACC, "FAcc" },
2262 { OPERAND_TYPE_SREG2, "SReg2" },
2263 { OPERAND_TYPE_SREG3, "SReg3" },
2264 { OPERAND_TYPE_ACC, "Acc" },
2265 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2266 { OPERAND_TYPE_REGMMX, "rMMX" },
2267 { OPERAND_TYPE_REGXMM, "rXMM" },
2268 { OPERAND_TYPE_ESSEG, "es" },
c0f3af97 2269 { OPERAND_TYPE_VEX_IMM4, "VEX i4" },
252b5132
RH		 2270};
2271
2272static void
40fb9820 2273pt (i386_operand_type t)
252b5132 2274{
40fb9820 2275 unsigned int j;
c6fb90c8 2276 i386_operand_type a;
252b5132 2277
40fb9820 2278 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2279 {
2280 a = operand_type_and (t, type_names[j].mask);
2281 if (!UINTS_ALL_ZERO (a))
2282 fprintf (stdout, "%s, ", type_names[j].name);
2283 }
252b5132
RH		 2284 fflush (stdout);
2285}
2286
2287#endif /* DEBUG386 */
2288\f
252b5132 2289static bfd_reloc_code_real_type
3956db08 2290reloc (unsigned int size,
64e74474
AM		 2291 int pcrel,
2292 int sign,
2293 bfd_reloc_code_real_type other)
252b5132 2294{
47926f60 2295 if (other != NO_RELOC)
3956db08
JB		 2296 {
2297 reloc_howto_type *reloc;
2298
2299 if (size == 8)
2300 switch (other)
2301 {
64e74474
AM		 2302 case BFD_RELOC_X86_64_GOT32:
2303 return BFD_RELOC_X86_64_GOT64;
2304 break;
2305 case BFD_RELOC_X86_64_PLTOFF64:
2306 return BFD_RELOC_X86_64_PLTOFF64;
2307 break;
2308 case BFD_RELOC_X86_64_GOTPC32:
2309 other = BFD_RELOC_X86_64_GOTPC64;
2310 break;
2311 case BFD_RELOC_X86_64_GOTPCREL:
2312 other = BFD_RELOC_X86_64_GOTPCREL64;
2313 break;
2314 case BFD_RELOC_X86_64_TPOFF32:
2315 other = BFD_RELOC_X86_64_TPOFF64;
2316 break;
2317 case BFD_RELOC_X86_64_DTPOFF32:
2318 other = BFD_RELOC_X86_64_DTPOFF64;
2319 break;
2320 default:
2321 break;
3956db08 2322 }
e05278af
JB		 2323
2324 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2325 if (size == 4 && flag_code != CODE_64BIT)
2326 sign = -1;
2327
3956db08
JB		 2328 reloc = bfd_reloc_type_lookup (stdoutput, other);
2329 if (!reloc)
2330 as_bad (_("unknown relocation (%u)"), other);
2331 else if (size != bfd_get_reloc_size (reloc))
2332 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2333 bfd_get_reloc_size (reloc),
2334 size);
2335 else if (pcrel && !reloc->pc_relative)
2336 as_bad (_("non-pc-relative relocation for pc-relative field"));
2337 else if ((reloc->complain_on_overflow == complain_overflow_signed
2338 && !sign)
2339 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2340 && sign > 0))
3956db08
JB		 2341 as_bad (_("relocated field and relocation type differ in signedness"));
2342 else
2343 return other;
2344 return NO_RELOC;
2345 }
252b5132
RH		 2346
2347 if (pcrel)
2348 {
3e73aa7c 2349 if (!sign)
3956db08 2350 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2351 switch (size)
2352 {
2353 case 1: return BFD_RELOC_8_PCREL;
2354 case 2: return BFD_RELOC_16_PCREL;
2355 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2356 case 8: return BFD_RELOC_64_PCREL;
252b5132 2357 }
3956db08 2358 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2359 }
2360 else
2361 {
3956db08 2362 if (sign > 0)
e5cb08ac 2363 switch (size)
3e73aa7c
JH		 2364 {
2365 case 4: return BFD_RELOC_X86_64_32S;
2366 }
2367 else
2368 switch (size)
2369 {
2370 case 1: return BFD_RELOC_8;
2371 case 2: return BFD_RELOC_16;
2372 case 4: return BFD_RELOC_32;
2373 case 8: return BFD_RELOC_64;
2374 }
3956db08
JB		 2375 as_bad (_("cannot do %s %u byte relocation"),
2376 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2377 }
2378
bfb32b52 2379 abort ();
252b5132
RH		 2380 return BFD_RELOC_NONE;
2381}
2382
47926f60
KH		 2383/* Here we decide which fixups can be adjusted to make them relative to
2384 the beginning of the section instead of the symbol. Basically we need
2385 to make sure that the dynamic relocations are done correctly, so in
2386 some cases we force the original symbol to be used. */
2387
252b5132 2388int
e3bb37b5 2389tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2390{
6d249963 2391#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2392 if (!IS_ELF)
31312f95
AM		 2393 return 1;
2394
a161fe53
AM		 2395 /* Don't adjust pc-relative references to merge sections in 64-bit
2396 mode. */
2397 if (use_rela_relocations
2398 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2399 && fixP->fx_pcrel)
252b5132 2400 return 0;
31312f95 2401
8d01d9a9
AJ		 2402 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2403 and changed later by validate_fix. */
2404 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2405 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2406 return 0;
2407
ce8a8b2f 2408 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2409 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2410 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2411 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2412 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2413 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2414 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2415 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2416 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2417 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2418 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2419 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2420 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2421 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2422 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2423 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2424 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2425 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2426 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2427 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2428 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2429 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2430 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2431 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2432 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2433 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2434 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2435 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2436 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2437 return 0;
31312f95 2438#endif
252b5132
RH		 2439 return 1;
2440}
252b5132 2441
b4cac588 2442static int
e3bb37b5 2443intel_float_operand (const char *mnemonic)
252b5132 2444{
9306ca4a
JB		 2445 /* Note that the value returned is meaningful only for opcodes with (memory)
2446 operands, hence the code here is free to improperly handle opcodes that
2447 have no operands (for better performance and smaller code). */
2448
2449 if (mnemonic[0] != 'f')
2450 return 0; /* non-math */
2451
2452 switch (mnemonic[1])
2453 {
2454 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2455 the fs segment override prefix not currently handled because no
2456 call path can make opcodes without operands get here */
2457 case 'i':
2458 return 2 /* integer op */;
2459 case 'l':
2460 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2461 return 3; /* fldcw/fldenv */
2462 break;
2463 case 'n':
2464 if (mnemonic[2] != 'o' /* fnop */)
2465 return 3; /* non-waiting control op */
2466 break;
2467 case 'r':
2468 if (mnemonic[2] == 's')
2469 return 3; /* frstor/frstpm */
2470 break;
2471 case 's':
2472 if (mnemonic[2] == 'a')
2473 return 3; /* fsave */
2474 if (mnemonic[2] == 't')
2475 {
2476 switch (mnemonic[3])
2477 {
2478 case 'c': /* fstcw */
2479 case 'd': /* fstdw */
2480 case 'e': /* fstenv */
2481 case 's': /* fsts[gw] */
2482 return 3;
2483 }
2484 }
2485 break;
2486 case 'x':
2487 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2488 return 0; /* fxsave/fxrstor are not really math ops */
2489 break;
2490 }
252b5132 2491
9306ca4a 2492 return 1;
252b5132
RH		 2493}
2494
c0f3af97
L		 2495/* Build the VEX prefix. */
2496
2497static void
2498build_vex_prefix (void)
2499{
2500 unsigned int register_specifier;
2501 unsigned int implied_prefix;
2502 unsigned int vector_length;
2503
2504 /* Check register specifier. */
2505 if (i.vex.register_specifier)
2506 {
2507 register_specifier = i.vex.register_specifier->reg_num;
2508 if ((i.vex.register_specifier->reg_flags & RegRex))
2509 register_specifier += 8;
2510 register_specifier = ~register_specifier & 0xf;
2511 }
2512 else
2513 register_specifier = 0xf;
2514
2515 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2516
2517 switch ((i.tm.base_opcode >> 8) & 0xff)
2518 {
2519 case 0:
2520 implied_prefix = 0;
2521 break;
2522 case DATA_PREFIX_OPCODE:
2523 implied_prefix = 1;
2524 break;
2525 case REPE_PREFIX_OPCODE:
2526 implied_prefix = 2;
2527 break;
2528 case REPNE_PREFIX_OPCODE:
2529 implied_prefix = 3;
2530 break;
2531 default:
2532 abort ();
2533 }
2534
2535 /* Use 2-byte VEX prefix if possible. */
2536 if (i.tm.opcode_modifier.vex0f
2537 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2538 {
2539 /* 2-byte VEX prefix. */
2540 unsigned int r;
2541
2542 i.vex.length = 2;
2543 i.vex.bytes[0] = 0xc5;
2544
2545 /* Check the REX.R bit. */
2546 r = (i.rex & REX_R) ? 0 : 1;
2547 i.vex.bytes[1] = (r << 7
2548 | register_specifier << 3
2549 | vector_length << 2
2550 | implied_prefix);
2551 }
2552 else
2553 {
2554 /* 3-byte VEX prefix. */
2555 unsigned int m, w;
2556
2557 if (i.tm.opcode_modifier.vex0f)
2558 m = 0x1;
2559 else if (i.tm.opcode_modifier.vex0f38)
2560 m = 0x2;
2561 else if (i.tm.opcode_modifier.vex0f3a)
2562 m = 0x3;
2563 else
2564 abort ();
2565
2566 i.vex.length = 3;
2567 i.vex.bytes[0] = 0xc4;
2568
2569 /* The high 3 bits of the second VEX byte are 1's compliment
2570 of RXB bits from REX. */
2571 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2572
2573 /* Check the REX.W bit. */
2574 w = (i.rex & REX_W) ? 1 : 0;
2575 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2576 {
2577 if (w)
2578 abort ();
2579
2580 if (i.tm.opcode_modifier.vexw1)
2581 w = 1;
2582 }
2583
2584 i.vex.bytes[2] = (w << 7
2585 | register_specifier << 3
2586 | vector_length << 2
2587 | implied_prefix);
2588 }
2589}
2590
65da13b5
L		 2591static void
2592process_immext (void)
2593{
2594 expressionS *exp;
2595
2596 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2597 {
1fed0ba1
L		 2598 /* SSE3 Instructions have the fixed operands with an opcode
2599 suffix which is coded in the same place as an 8-bit immediate
2600 field would be. Here we check those operands and remove them
2601 afterwards. */
65da13b5
L		 2602 unsigned int x;
2603
2604 for (x = 0; x < i.operands; x++)
2605 if (i.op[x].regs->reg_num != x)
2606 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2607 register_prefix, i.op[x].regs->reg_name, x + 1,
2608 i.tm.name);
2609
2610 i.operands = 0;
65da13b5
L		 2611 }
2612
c0f3af97 2613 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2614 which is coded in the same place as an 8-bit immediate field
2615 would be. Here we fake an 8-bit immediate operand from the
2616 opcode suffix stored in tm.extension_opcode.
2617
c0f3af97
L		 2618 SSE5 and AVX instructions also use this encoding, for some of
2619 3 argument instructions. */
65da13b5
L		 2620
2621 assert (i.imm_operands == 0
2622 && (i.operands <= 2
2623 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2624 && i.operands <= 3)
2625 || (i.tm.opcode_modifier.vex
2626 && i.operands <= 4)));
65da13b5
L		 2627
2628 exp = &im_expressions[i.imm_operands++];
2629 i.op[i.operands].imms = exp;
2630 i.types[i.operands] = imm8;
2631 i.operands++;
2632 exp->X_op = O_constant;
2633 exp->X_add_number = i.tm.extension_opcode;
2634 i.tm.extension_opcode = None;
2635}
2636
252b5132
RH		 2637/* This is the guts of the machine-dependent assembler. LINE points to a
2638 machine dependent instruction. This function is supposed to emit
2639 the frags/bytes it assembles to. */
2640
2641void
65da13b5 2642md_assemble (char *line)
252b5132 2643{
40fb9820 2644 unsigned int j;
252b5132
RH		 2645 char mnemonic[MAX_MNEM_SIZE];
2646
47926f60 2647 /* Initialize globals. */
252b5132
RH		 2648 memset (&i, '\0', sizeof (i));
2649 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2650 i.reloc[j] = NO_RELOC;
252b5132
RH		 2651 memset (disp_expressions, '\0', sizeof (disp_expressions));
2652 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2653 save_stack_p = save_stack;
252b5132
RH		 2654
2655 /* First parse an instruction mnemonic & call i386_operand for the operands.
2656 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2657 start of a (possibly prefixed) mnemonic. */
252b5132 2658
29b0f896
AM		 2659 line = parse_insn (line, mnemonic);
2660 if (line == NULL)
2661 return;
252b5132 2662
29b0f896
AM		 2663 line = parse_operands (line, mnemonic);
2664 if (line == NULL)
2665 return;
252b5132 2666
29b0f896
AM		 2667 /* Now we've parsed the mnemonic into a set of templates, and have the
2668 operands at hand. */
2669
2670 /* All intel opcodes have reversed operands except for "bound" and
2671 "enter". We also don't reverse intersegment "jmp" and "call"
2672 instructions with 2 immediate operands so that the immediate segment
050dfa73 2673 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2674 if (intel_syntax
2675 && i.operands > 1
29b0f896 2676 && (strcmp (mnemonic, "bound") != 0)
30123838 2677 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2678 && !(operand_type_check (i.types[0], imm)
2679 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2680 swap_operands ();
2681
ec56d5c0
JB		 2682 /* The order of the immediates should be reversed
2683 for 2 immediates extrq and insertq instructions */
2684 if (i.imm_operands == 2
2685 && (strcmp (mnemonic, "extrq") == 0
2686 || strcmp (mnemonic, "insertq") == 0))
2687 swap_2_operands (0, 1);
2688
29b0f896
AM		 2689 if (i.imm_operands)
2690 optimize_imm ();
2691
b300c311
L		 2692 /* Don't optimize displacement for movabs since it only takes 64bit
2693 displacement. */
2694 if (i.disp_operands
2695 && (flag_code != CODE_64BIT
2696 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2697 optimize_disp ();
2698
2699 /* Next, we find a template that matches the given insn,
2700 making sure the overlap of the given operands types is consistent
2701 with the template operand types. */
252b5132 2702
29b0f896
AM		 2703 if (!match_template ())
2704 return;
252b5132 2705
daf50ae7 2706 if (sse_check != sse_check_none
81f8a913 2707 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2708 && (i.tm.cpu_flags.bitfield.cpusse
2709 || i.tm.cpu_flags.bitfield.cpusse2
2710 || i.tm.cpu_flags.bitfield.cpusse3
2711 || i.tm.cpu_flags.bitfield.cpussse3
2712 || i.tm.cpu_flags.bitfield.cpusse4_1
2713 || i.tm.cpu_flags.bitfield.cpusse4_2))
2714 {
2715 (sse_check == sse_check_warning
2716 ? as_warn
2717 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2718 }
2719
321fd21e
L		 2720 /* Zap movzx and movsx suffix. The suffix has been set from
2721 "word ptr" or "byte ptr" on the source operand in Intel syntax
2722 or extracted from mnemonic in AT&T syntax. But we'll use
2723 the destination register to choose the suffix for encoding. */
2724 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2725 {
321fd21e
L		 2726 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2727 there is no suffix, the default will be byte extension. */
2728 if (i.reg_operands != 2
2729 && !i.suffix
2730 && intel_syntax)
2731 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2732
2733 i.suffix = 0;
cd61ebfe 2734 }
24eab124 2735
40fb9820 2736 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2737 if (!add_prefix (FWAIT_OPCODE))
2738 return;
252b5132 2739
29b0f896 2740 /* Check string instruction segment overrides. */
40fb9820 2741 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2742 {
2743 if (!check_string ())
5dd0794d 2744 return;
29b0f896 2745 }
5dd0794d 2746
29b0f896
AM		 2747 if (!process_suffix ())
2748 return;
e413e4e9 2749
29b0f896
AM		 2750 /* Make still unresolved immediate matches conform to size of immediate
2751 given in i.suffix. */
2752 if (!finalize_imm ())
2753 return;
252b5132 2754
40fb9820 2755 if (i.types[0].bitfield.imm1)
29b0f896 2756 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2757
40fb9820 2758 for (j = 0; j < 3; j++)
c6fb90c8
L		 2759 if (i.types[j].bitfield.inoutportreg
2760 || i.types[j].bitfield.shiftcount
2761 || i.types[j].bitfield.acc
2762 || i.types[j].bitfield.floatacc)
40fb9820
L		 2763 i.reg_operands--;
2764
c0f3af97
L		 2765 /* ImmExt should be processed after SSE2AVX. */
2766 if (!i.tm.opcode_modifier.sse2avx
2767 && i.tm.opcode_modifier.immext)
65da13b5 2768 process_immext ();
252b5132 2769
29b0f896
AM		 2770 /* For insns with operands there are more diddles to do to the opcode. */
2771 if (i.operands)
2772 {
2773 if (!process_operands ())
2774 return;
2775 }
40fb9820 2776 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2777 {
2778 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2779 as_warn (_("translating to `%sp'"), i.tm.name);
2780 }
252b5132 2781
c0f3af97
L		 2782 if (i.tm.opcode_modifier.vex)
2783 build_vex_prefix ();
2784
29b0f896
AM		 2785 /* Handle conversion of 'int $3' --> special int3 insn. */
2786 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2787 {
2788 i.tm.base_opcode = INT3_OPCODE;
2789 i.imm_operands = 0;
2790 }
252b5132 2791
40fb9820
L		 2792 if ((i.tm.opcode_modifier.jump
2793 || i.tm.opcode_modifier.jumpbyte
2794 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2795 && i.op[0].disps->X_op == O_constant)
2796 {
2797 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2798 the absolute address given by the constant. Since ix86 jumps and
2799 calls are pc relative, we need to generate a reloc. */
2800 i.op[0].disps->X_add_symbol = &abs_symbol;
2801 i.op[0].disps->X_op = O_symbol;
2802 }
252b5132 2803
40fb9820 2804 if (i.tm.opcode_modifier.rex64)
161a04f6 2805 i.rex |= REX_W;
252b5132 2806
29b0f896
AM		 2807 /* For 8 bit registers we need an empty rex prefix. Also if the
2808 instruction already has a prefix, we need to convert old
2809 registers to new ones. */
773f551c 2810
40fb9820 2811 if ((i.types[0].bitfield.reg8
29b0f896 2812 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2813 || (i.types[1].bitfield.reg8
29b0f896 2814 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2815 || ((i.types[0].bitfield.reg8
2816 || i.types[1].bitfield.reg8)
29b0f896
AM		 2817 && i.rex != 0))
2818 {
2819 int x;
726c5dcd 2820
29b0f896
AM		 2821 i.rex |= REX_OPCODE;
2822 for (x = 0; x < 2; x++)
2823 {
2824 /* Look for 8 bit operand that uses old registers. */
40fb9820 2825 if (i.types[x].bitfield.reg8
29b0f896 2826 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2827 {
29b0f896
AM		 2828 /* In case it is "hi" register, give up. */
2829 if (i.op[x].regs->reg_num > 3)
a540244d 2830 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2831 "instruction requiring REX prefix."),
a540244d 2832 register_prefix, i.op[x].regs->reg_name);
773f551c 2833
29b0f896
AM		 2834 /* Otherwise it is equivalent to the extended register.
2835 Since the encoding doesn't change this is merely
2836 cosmetic cleanup for debug output. */
2837
2838 i.op[x].regs = i.op[x].regs + 8;
773f551c 2839 }
29b0f896
AM		 2840 }
2841 }
773f551c 2842
85f10a01
MM		 2843 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2844 REX prefix. */
2845 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2846 {
2847 i.drex.rex = i.rex;
2848 i.rex = 0;
2849 }
2850 else if (i.rex != 0)
29b0f896
AM		 2851 add_prefix (REX_OPCODE | i.rex);
2852
2853 /* We are ready to output the insn. */
2854 output_insn ();
2855}
2856
2857static char *
e3bb37b5 2858parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2859{
2860 char *l = line;
2861 char *token_start = l;
2862 char *mnem_p;
5c6af06e
JB		 2863 int supported;
2864 const template *t;
29b0f896
AM		 2865
2866 /* Non-zero if we found a prefix only acceptable with string insns. */
2867 const char *expecting_string_instruction = NULL;
45288df1 2868
29b0f896
AM		 2869 while (1)
2870 {
2871 mnem_p = mnemonic;
2872 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2873 {
2874 mnem_p++;
2875 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2876 {
29b0f896
AM		 2877 as_bad (_("no such instruction: `%s'"), token_start);
2878 return NULL;
2879 }
2880 l++;
2881 }
2882 if (!is_space_char (*l)
2883 && *l != END_OF_INSN
e44823cf
JB		 2884 && (intel_syntax
2885 || (*l != PREFIX_SEPARATOR
2886 && *l != ',')))
29b0f896
AM		 2887 {
2888 as_bad (_("invalid character %s in mnemonic"),
2889 output_invalid (*l));
2890 return NULL;
2891 }
2892 if (token_start == l)
2893 {
e44823cf 2894 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2895 as_bad (_("expecting prefix; got nothing"));
2896 else
2897 as_bad (_("expecting mnemonic; got nothing"));
2898 return NULL;
2899 }
45288df1 2900
29b0f896
AM		 2901 /* Look up instruction (or prefix) via hash table. */
2902 current_templates = hash_find (op_hash, mnemonic);
47926f60 2903
29b0f896
AM		 2904 if (*l != END_OF_INSN
2905 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2906 && current_templates
40fb9820 2907 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2908 {
c6fb90c8 2909 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2910 {
2911 as_bad ((flag_code != CODE_64BIT
2912 ? _("`%s' is only supported in 64-bit mode")
2913 : _("`%s' is not supported in 64-bit mode")),
2914 current_templates->start->name);
2915 return NULL;
2916 }
29b0f896
AM		 2917 /* If we are in 16-bit mode, do not allow addr16 or data16.
2918 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2919 if ((current_templates->start->opcode_modifier.size16
2920 || current_templates->start->opcode_modifier.size32)
29b0f896 2921 && flag_code != CODE_64BIT
40fb9820 2922 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2923 ^ (flag_code == CODE_16BIT)))
2924 {
2925 as_bad (_("redundant %s prefix"),
2926 current_templates->start->name);
2927 return NULL;
45288df1 2928 }
29b0f896
AM		 2929 /* Add prefix, checking for repeated prefixes. */
2930 switch (add_prefix (current_templates->start->base_opcode))
2931 {
2932 case 0:
2933 return NULL;
2934 case 2:
2935 expecting_string_instruction = current_templates->start->name;
2936 break;
2937 }
2938 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2939 token_start = ++l;
2940 }
2941 else
2942 break;
2943 }
45288df1 2944
29b0f896
AM		 2945 if (!current_templates)
2946 {
2947 /* See if we can get a match by trimming off a suffix. */
2948 switch (mnem_p[-1])
2949 {
2950 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2951 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2952 i.suffix = SHORT_MNEM_SUFFIX;
2953 else
29b0f896
AM		 2954 case BYTE_MNEM_SUFFIX:
2955 case QWORD_MNEM_SUFFIX:
2956 i.suffix = mnem_p[-1];
2957 mnem_p[-1] = '\0';
2958 current_templates = hash_find (op_hash, mnemonic);
2959 break;
2960 case SHORT_MNEM_SUFFIX:
2961 case LONG_MNEM_SUFFIX:
2962 if (!intel_syntax)
2963 {
2964 i.suffix = mnem_p[-1];
2965 mnem_p[-1] = '\0';
2966 current_templates = hash_find (op_hash, mnemonic);
2967 }
2968 break;
252b5132 2969
29b0f896
AM		 2970 /* Intel Syntax. */
2971 case 'd':
2972 if (intel_syntax)
2973 {
9306ca4a 2974 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2975 i.suffix = SHORT_MNEM_SUFFIX;
2976 else
2977 i.suffix = LONG_MNEM_SUFFIX;
2978 mnem_p[-1] = '\0';
2979 current_templates = hash_find (op_hash, mnemonic);
2980 }
2981 break;
2982 }
2983 if (!current_templates)
2984 {
2985 as_bad (_("no such instruction: `%s'"), token_start);
2986 return NULL;
2987 }
2988 }
252b5132 2989
40fb9820
L		 2990 if (current_templates->start->opcode_modifier.jump
2991 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2992 {
2993 /* Check for a branch hint. We allow ",pt" and ",pn" for
2994 predict taken and predict not taken respectively.
2995 I'm not sure that branch hints actually do anything on loop
2996 and jcxz insns (JumpByte) for current Pentium4 chips. They
2997 may work in the future and it doesn't hurt to accept them
2998 now. */
2999 if (l[0] == ',' && l[1] == 'p')
3000 {
3001 if (l[2] == 't')
3002 {
3003 if (!add_prefix (DS_PREFIX_OPCODE))
3004 return NULL;
3005 l += 3;
3006 }
3007 else if (l[2] == 'n')
3008 {
3009 if (!add_prefix (CS_PREFIX_OPCODE))
3010 return NULL;
3011 l += 3;
3012 }
3013 }
3014 }
3015 /* Any other comma loses. */
3016 if (*l == ',')
3017 {
3018 as_bad (_("invalid character %s in mnemonic"),
3019 output_invalid (*l));
3020 return NULL;
3021 }
252b5132 3022
29b0f896 3023 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3024 supported = 0;
3025 for (t = current_templates->start; t < current_templates->end; ++t)
3026 {
c0f3af97
L		 3027 supported |= cpu_flags_match (t);
3028 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3029 goto skip;
5c6af06e 3030 }
3629bb00 3031
c0f3af97 3032 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3033 {
3034 as_bad (flag_code == CODE_64BIT
3035 ? _("`%s' is not supported in 64-bit mode")
3036 : _("`%s' is only supported in 64-bit mode"),
3037 current_templates->start->name);
3038 return NULL;
3039 }
c0f3af97 3040 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3041 {
3629bb00
L		 3042 as_bad (_("`%s' is not supported on `%s%s'"),
3043 current_templates->start->name, cpu_arch_name,
3044 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3045 return NULL;
29b0f896 3046 }
3629bb00
L		 3047
3048skip:
3049 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3050 && (flag_code != CODE_16BIT))
29b0f896
AM		 3051 {
3052 as_warn (_("use .code16 to ensure correct addressing mode"));
3053 }
252b5132 3054
29b0f896 3055 /* Check for rep/repne without a string instruction. */
f41bbced 3056 if (expecting_string_instruction)
29b0f896 3057 {
f41bbced
JB		 3058 static templates override;
3059
3060 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3061 if (t->opcode_modifier.isstring)
f41bbced
JB		 3062 break;
3063 if (t >= current_templates->end)
3064 {
3065 as_bad (_("expecting string instruction after `%s'"),
64e74474 3066 expecting_string_instruction);
f41bbced
JB		 3067 return NULL;
3068 }
3069 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3070 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3071 break;
3072 override.end = t;
3073 current_templates = &override;
29b0f896 3074 }
252b5132 3075
29b0f896
AM		 3076 return l;
3077}
252b5132 3078
29b0f896 3079static char *
e3bb37b5 3080parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3081{
3082 char *token_start;
3138f287 3083
29b0f896
AM		 3084 /* 1 if operand is pending after ','. */
3085 unsigned int expecting_operand = 0;
252b5132 3086
29b0f896
AM		 3087 /* Non-zero if operand parens not balanced. */
3088 unsigned int paren_not_balanced;
3089
3090 while (*l != END_OF_INSN)
3091 {
3092 /* Skip optional white space before operand. */
3093 if (is_space_char (*l))
3094 ++l;
3095 if (!is_operand_char (*l) && *l != END_OF_INSN)
3096 {
3097 as_bad (_("invalid character %s before operand %d"),
3098 output_invalid (*l),
3099 i.operands + 1);
3100 return NULL;
3101 }
3102 token_start = l; /* after white space */
3103 paren_not_balanced = 0;
3104 while (paren_not_balanced || *l != ',')
3105 {
3106 if (*l == END_OF_INSN)
3107 {
3108 if (paren_not_balanced)
3109 {
3110 if (!intel_syntax)
3111 as_bad (_("unbalanced parenthesis in operand %d."),
3112 i.operands + 1);
3113 else
3114 as_bad (_("unbalanced brackets in operand %d."),
3115 i.operands + 1);
3116 return NULL;
3117 }
3118 else
3119 break; /* we are done */
3120 }
3121 else if (!is_operand_char (*l) && !is_space_char (*l))
3122 {
3123 as_bad (_("invalid character %s in operand %d"),
3124 output_invalid (*l),
3125 i.operands + 1);
3126 return NULL;
3127 }
3128 if (!intel_syntax)
3129 {
3130 if (*l == '(')
3131 ++paren_not_balanced;
3132 if (*l == ')')
3133 --paren_not_balanced;
3134 }
3135 else
3136 {
3137 if (*l == '[')
3138 ++paren_not_balanced;
3139 if (*l == ']')
3140 --paren_not_balanced;
3141 }
3142 l++;
3143 }
3144 if (l != token_start)
3145 { /* Yes, we've read in another operand. */
3146 unsigned int operand_ok;
3147 this_operand = i.operands++;
7d5e4556 3148 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3149 if (i.operands > MAX_OPERANDS)
3150 {
3151 as_bad (_("spurious operands; (%d operands/instruction max)"),
3152 MAX_OPERANDS);
3153 return NULL;
3154 }
3155 /* Now parse operand adding info to 'i' as we go along. */
3156 END_STRING_AND_SAVE (l);
3157
3158 if (intel_syntax)
3159 operand_ok =
3160 i386_intel_operand (token_start,
3161 intel_float_operand (mnemonic));
3162 else
a7619375 3163 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3164
3165 RESTORE_END_STRING (l);
3166 if (!operand_ok)
3167 return NULL;
3168 }
3169 else
3170 {
3171 if (expecting_operand)
3172 {
3173 expecting_operand_after_comma:
3174 as_bad (_("expecting operand after ','; got nothing"));
3175 return NULL;
3176 }
3177 if (*l == ',')
3178 {
3179 as_bad (_("expecting operand before ','; got nothing"));
3180 return NULL;
3181 }
3182 }
7f3f1ea2 3183
29b0f896
AM		 3184 /* Now *l must be either ',' or END_OF_INSN. */
3185 if (*l == ',')
3186 {
3187 if (*++l == END_OF_INSN)
3188 {
3189 /* Just skip it, if it's \n complain. */
3190 goto expecting_operand_after_comma;
3191 }
3192 expecting_operand = 1;
3193 }
3194 }
3195 return l;
3196}
7f3f1ea2 3197
050dfa73 3198static void
4d456e3d 3199swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3200{
3201 union i386_op temp_op;
40fb9820 3202 i386_operand_type temp_type;
050dfa73 3203 enum bfd_reloc_code_real temp_reloc;
4eed87de 3204
050dfa73
MM		 3205 temp_type = i.types[xchg2];
3206 i.types[xchg2] = i.types[xchg1];
3207 i.types[xchg1] = temp_type;
3208 temp_op = i.op[xchg2];
3209 i.op[xchg2] = i.op[xchg1];
3210 i.op[xchg1] = temp_op;
3211 temp_reloc = i.reloc[xchg2];
3212 i.reloc[xchg2] = i.reloc[xchg1];
3213 i.reloc[xchg1] = temp_reloc;
3214}
3215
29b0f896 3216static void
e3bb37b5 3217swap_operands (void)
29b0f896 3218{
b7c61d9a 3219 switch (i.operands)
050dfa73 3220 {
c0f3af97 3221 case 5:
b7c61d9a 3222 case 4:
4d456e3d 3223 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3224 case 3:
3225 case 2:
4d456e3d 3226 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3227 break;
3228 default:
3229 abort ();
29b0f896 3230 }
29b0f896
AM		 3231
3232 if (i.mem_operands == 2)
3233 {
3234 const seg_entry *temp_seg;
3235 temp_seg = i.seg[0];
3236 i.seg[0] = i.seg[1];
3237 i.seg[1] = temp_seg;
3238 }
3239}
252b5132 3240
29b0f896
AM		 3241/* Try to ensure constant immediates are represented in the smallest
3242 opcode possible. */
3243static void
e3bb37b5 3244optimize_imm (void)
29b0f896
AM		 3245{
3246 char guess_suffix = 0;
3247 int op;
252b5132 3248
29b0f896
AM		 3249 if (i.suffix)
3250 guess_suffix = i.suffix;
3251 else if (i.reg_operands)
3252 {
3253 /* Figure out a suffix from the last register operand specified.
3254 We can't do this properly yet, ie. excluding InOutPortReg,
3255 but the following works for instructions with immediates.
3256 In any case, we can't set i.suffix yet. */
3257 for (op = i.operands; --op >= 0;)
40fb9820
L		 3258 if (i.types[op].bitfield.reg8)
3259 {
3260 guess_suffix = BYTE_MNEM_SUFFIX;
3261 break;
3262 }
3263 else if (i.types[op].bitfield.reg16)
252b5132 3264 {
40fb9820
L		 3265 guess_suffix = WORD_MNEM_SUFFIX;
3266 break;
3267 }
3268 else if (i.types[op].bitfield.reg32)
3269 {
3270 guess_suffix = LONG_MNEM_SUFFIX;
3271 break;
3272 }
3273 else if (i.types[op].bitfield.reg64)
3274 {
3275 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3276 break;
252b5132 3277 }
29b0f896
AM		 3278 }
3279 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3280 guess_suffix = WORD_MNEM_SUFFIX;
3281
3282 for (op = i.operands; --op >= 0;)
40fb9820 3283 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3284 {
3285 switch (i.op[op].imms->X_op)
252b5132 3286 {
29b0f896
AM		 3287 case O_constant:
3288 /* If a suffix is given, this operand may be shortened. */
3289 switch (guess_suffix)
252b5132 3290 {
29b0f896 3291 case LONG_MNEM_SUFFIX:
40fb9820
L		 3292 i.types[op].bitfield.imm32 = 1;
3293 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3294 break;
3295 case WORD_MNEM_SUFFIX:
40fb9820
L		 3296 i.types[op].bitfield.imm16 = 1;
3297 i.types[op].bitfield.imm32 = 1;
3298 i.types[op].bitfield.imm32s = 1;
3299 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3300 break;
3301 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3302 i.types[op].bitfield.imm8 = 1;
3303 i.types[op].bitfield.imm8s = 1;
3304 i.types[op].bitfield.imm16 = 1;
3305 i.types[op].bitfield.imm32 = 1;
3306 i.types[op].bitfield.imm32s = 1;
3307 i.types[op].bitfield.imm64 = 1;
29b0f896 3308 break;
252b5132 3309 }
252b5132 3310
29b0f896
AM		 3311 /* If this operand is at most 16 bits, convert it
3312 to a signed 16 bit number before trying to see
3313 whether it will fit in an even smaller size.
3314 This allows a 16-bit operand such as $0xffe0 to
3315 be recognised as within Imm8S range. */
40fb9820 3316 if ((i.types[op].bitfield.imm16)
29b0f896 3317 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3318 {
29b0f896
AM		 3319 i.op[op].imms->X_add_number =
3320 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3321 }
40fb9820 3322 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3323 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3324 == 0))
3325 {
3326 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3327 ^ ((offsetT) 1 << 31))
3328 - ((offsetT) 1 << 31));
3329 }
40fb9820 3330 i.types[op]
c6fb90c8
L		 3331 = operand_type_or (i.types[op],
3332 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3333
29b0f896
AM		 3334 /* We must avoid matching of Imm32 templates when 64bit
3335 only immediate is available. */
3336 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3337 i.types[op].bitfield.imm32 = 0;
29b0f896 3338 break;
252b5132 3339
29b0f896
AM		 3340 case O_absent:
3341 case O_register:
3342 abort ();
3343
3344 /* Symbols and expressions. */
3345 default:
9cd96992
JB		 3346 /* Convert symbolic operand to proper sizes for matching, but don't
3347 prevent matching a set of insns that only supports sizes other
3348 than those matching the insn suffix. */
3349 {
40fb9820 3350 i386_operand_type mask, allowed;
9cd96992
JB		 3351 const template *t;
3352
0dfbf9d7
L		 3353 operand_type_set (&mask, 0);
3354 operand_type_set (&allowed, 0);
40fb9820 3355
4eed87de
AM		 3356 for (t = current_templates->start;
3357 t < current_templates->end;
3358 ++t)
c6fb90c8
L		 3359 allowed = operand_type_or (allowed,
3360 t->operand_types[op]);
9cd96992
JB		 3361 switch (guess_suffix)
3362 {
3363 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3364 mask.bitfield.imm64 = 1;
3365 mask.bitfield.imm32s = 1;
9cd96992
JB		 3366 break;
3367 case LONG_MNEM_SUFFIX:
40fb9820 3368 mask.bitfield.imm32 = 1;
9cd96992
JB		 3369 break;
3370 case WORD_MNEM_SUFFIX:
40fb9820 3371 mask.bitfield.imm16 = 1;
9cd96992
JB		 3372 break;
3373 case BYTE_MNEM_SUFFIX:
40fb9820 3374 mask.bitfield.imm8 = 1;
9cd96992
JB		 3375 break;
3376 default:
9cd96992
JB		 3377 break;
3378 }
c6fb90c8 3379 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3380 if (!operand_type_all_zero (&allowed))
c6fb90c8 3381 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3382 }
29b0f896 3383 break;
252b5132 3384 }
29b0f896
AM		 3385 }
3386}
47926f60 3387
29b0f896
AM		 3388/* Try to use the smallest displacement type too. */
3389static void
e3bb37b5 3390optimize_disp (void)
29b0f896
AM		 3391{
3392 int op;
3e73aa7c 3393
29b0f896 3394 for (op = i.operands; --op >= 0;)
40fb9820 3395 if (operand_type_check (i.types[op], disp))
252b5132 3396 {
b300c311 3397 if (i.op[op].disps->X_op == O_constant)
252b5132 3398 {
b300c311 3399 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3400
40fb9820 3401 if (i.types[op].bitfield.disp16
b300c311
L		 3402 && (disp & ~(offsetT) 0xffff) == 0)
3403 {
3404 /* If this operand is at most 16 bits, convert
3405 to a signed 16 bit number and don't use 64bit
3406 displacement. */
3407 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3408 i.types[op].bitfield.disp64 = 0;
b300c311 3409 }
40fb9820 3410 if (i.types[op].bitfield.disp32
b300c311
L		 3411 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3412 {
3413 /* If this operand is at most 32 bits, convert
3414 to a signed 32 bit number and don't use 64bit
3415 displacement. */
3416 disp &= (((offsetT) 2 << 31) - 1);
3417 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3418 i.types[op].bitfield.disp64 = 0;
b300c311 3419 }
40fb9820 3420 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3421 {
40fb9820
L		 3422 i.types[op].bitfield.disp8 = 0;
3423 i.types[op].bitfield.disp16 = 0;
3424 i.types[op].bitfield.disp32 = 0;
3425 i.types[op].bitfield.disp32s = 0;
3426 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3427 i.op[op].disps = 0;
3428 i.disp_operands--;
3429 }
3430 else if (flag_code == CODE_64BIT)
3431 {
3432 if (fits_in_signed_long (disp))
28a9d8f5 3433 {
40fb9820
L		 3434 i.types[op].bitfield.disp64 = 0;
3435 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3436 }
b300c311 3437 if (fits_in_unsigned_long (disp))
40fb9820 3438 i.types[op].bitfield.disp32 = 1;
b300c311 3439 }
40fb9820
L		 3440 if ((i.types[op].bitfield.disp32
3441 || i.types[op].bitfield.disp32s
3442 || i.types[op].bitfield.disp16)
b300c311 3443 && fits_in_signed_byte (disp))
40fb9820 3444 i.types[op].bitfield.disp8 = 1;
252b5132 3445 }
67a4f2b7
AO		 3446 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3447 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3448 {
3449 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3450 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3451 i.types[op].bitfield.disp8 = 0;
3452 i.types[op].bitfield.disp16 = 0;
3453 i.types[op].bitfield.disp32 = 0;
3454 i.types[op].bitfield.disp32s = 0;
3455 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3456 }
3457 else
b300c311 3458 /* We only support 64bit displacement on constants. */
40fb9820 3459 i.types[op].bitfield.disp64 = 0;
252b5132 3460 }
29b0f896
AM		 3461}
3462
c0f3af97
L		 3463/* Check if operands are valid for the instrucrtion. Update VEX
3464 operand types. */
3465
3466static int
3467VEX_check_operands (const template *t)
3468{
3469 if (!t->opcode_modifier.vex)
3470 return 0;
3471
3472 /* Only check VEX_Imm4, which must be the first operand. */
3473 if (t->operand_types[0].bitfield.vex_imm4)
3474 {
3475 if (i.op[0].imms->X_op != O_constant
3476 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3477 return 1;
3478
3479 /* Turn off Imm8 so that update_imm won't complain. */
3480 i.types[0] = vex_imm4;
3481 }
3482
3483 return 0;
3484}
3485
29b0f896 3486static int
e3bb37b5 3487match_template (void)
29b0f896
AM		 3488{
3489 /* Points to template once we've found it. */
3490 const template *t;
40fb9820 3491 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3492 i386_operand_type overlap4;
29b0f896 3493 unsigned int found_reverse_match;
40fb9820
L		 3494 i386_opcode_modifier suffix_check;
3495 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3496 int addr_prefix_disp;
a5c311ca 3497 unsigned int j;
3629bb00 3498 unsigned int found_cpu_match;
45664ddb 3499 unsigned int check_register;
29b0f896 3500
c0f3af97
L		 3501#if MAX_OPERANDS != 5
3502# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3503#endif
3504
29b0f896 3505 found_reverse_match = 0;
539e75ad 3506 addr_prefix_disp = -1;
40fb9820
L		 3507
3508 memset (&suffix_check, 0, sizeof (suffix_check));
3509 if (i.suffix == BYTE_MNEM_SUFFIX)
3510 suffix_check.no_bsuf = 1;
3511 else if (i.suffix == WORD_MNEM_SUFFIX)
3512 suffix_check.no_wsuf = 1;
3513 else if (i.suffix == SHORT_MNEM_SUFFIX)
3514 suffix_check.no_ssuf = 1;
3515 else if (i.suffix == LONG_MNEM_SUFFIX)
3516 suffix_check.no_lsuf = 1;
3517 else if (i.suffix == QWORD_MNEM_SUFFIX)
3518 suffix_check.no_qsuf = 1;
3519 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3520 suffix_check.no_ldsuf = 1;
29b0f896 3521
45aa61fe 3522 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3523 {
539e75ad
L		 3524 addr_prefix_disp = -1;
3525
29b0f896
AM		 3526 /* Must have right number of operands. */
3527 if (i.operands != t->operands)
3528 continue;
3529
50aecf8c 3530 /* Check processor support. */
c0f3af97
L		 3531 found_cpu_match = (cpu_flags_match (t)
3532 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3533 if (!found_cpu_match)
3534 continue;
3535
e1d4d893
L		 3536 /* Check old gcc support. */
3537 if (!old_gcc && t->opcode_modifier.oldgcc)
3538 continue;
3539
3540 /* Check AT&T mnemonic. */
3541 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3542 continue;
3543
5c07affc
L		 3544 /* Check AT&T syntax Intel syntax. */
3545 if ((intel_syntax && t->opcode_modifier.attsyntax)
3546 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3547 continue;
3548
20592a94 3549 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3550 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3551 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3552 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3553 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3554 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3555 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3556 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3557 continue;
3558
5c07affc 3559 if (!operand_size_match (t))
7d5e4556 3560 continue;
539e75ad 3561
5c07affc
L		 3562 for (j = 0; j < MAX_OPERANDS; j++)
3563 operand_types[j] = t->operand_types[j];
3564
45aa61fe
AM		 3565 /* In general, don't allow 64-bit operands in 32-bit mode. */
3566 if (i.suffix == QWORD_MNEM_SUFFIX
3567 && flag_code != CODE_64BIT
3568 && (intel_syntax
40fb9820 3569 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3570 && !intel_float_operand (t->name))
3571 : intel_float_operand (t->name) != 2)
40fb9820 3572 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3573 && !operand_types[0].bitfield.regxmm
3574 && !operand_types[0].bitfield.regymm)
40fb9820 3575 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3576 && !!operand_types[t->operands > 1].bitfield.regxmm
3577 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3578 && (t->base_opcode != 0x0fc7
3579 || t->extension_opcode != 1 /* cmpxchg8b */))
3580 continue;
3581
192dc9c6
JB		 3582 /* In general, don't allow 32-bit operands on pre-386. */
3583 else if (i.suffix == LONG_MNEM_SUFFIX
3584 && !cpu_arch_flags.bitfield.cpui386
3585 && (intel_syntax
3586 ? (!t->opcode_modifier.ignoresize
3587 && !intel_float_operand (t->name))
3588 : intel_float_operand (t->name) != 2)
3589 && ((!operand_types[0].bitfield.regmmx
3590 && !operand_types[0].bitfield.regxmm)
3591 || (!operand_types[t->operands > 1].bitfield.regmmx
3592 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3593 continue;
3594
29b0f896 3595 /* Do not verify operands when there are none. */
50aecf8c 3596 else
29b0f896 3597 {
c6fb90c8 3598 if (!t->operands)
2dbab7d5
L		 3599 /* We've found a match; break out of loop. */
3600 break;
29b0f896 3601 }
252b5132 3602
539e75ad
L		 3603 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3604 into Disp32/Disp16/Disp32 operand. */
3605 if (i.prefix[ADDR_PREFIX] != 0)
3606 {
40fb9820 3607 /* There should be only one Disp operand. */
539e75ad
L		 3608 switch (flag_code)
3609 {
3610 case CODE_16BIT:
40fb9820
L		 3611 for (j = 0; j < MAX_OPERANDS; j++)
3612 {
3613 if (operand_types[j].bitfield.disp16)
3614 {
3615 addr_prefix_disp = j;
3616 operand_types[j].bitfield.disp32 = 1;
3617 operand_types[j].bitfield.disp16 = 0;
3618 break;
3619 }
3620 }
539e75ad
L		 3621 break;
3622 case CODE_32BIT:
40fb9820
L		 3623 for (j = 0; j < MAX_OPERANDS; j++)
3624 {
3625 if (operand_types[j].bitfield.disp32)
3626 {
3627 addr_prefix_disp = j;
3628 operand_types[j].bitfield.disp32 = 0;
3629 operand_types[j].bitfield.disp16 = 1;
3630 break;
3631 }
3632 }
539e75ad
L		 3633 break;
3634 case CODE_64BIT:
40fb9820
L		 3635 for (j = 0; j < MAX_OPERANDS; j++)
3636 {
3637 if (operand_types[j].bitfield.disp64)
3638 {
3639 addr_prefix_disp = j;
3640 operand_types[j].bitfield.disp64 = 0;
3641 operand_types[j].bitfield.disp32 = 1;
3642 break;
3643 }
3644 }
539e75ad
L		 3645 break;
3646 }
539e75ad
L		 3647 }
3648
45664ddb
L		 3649 /* We check register size only if size of operands can be
3650 encoded the canonical way. */
3651 check_register = t->opcode_modifier.w;
c6fb90c8 3652 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3653 switch (t->operands)
3654 {
3655 case 1:
40fb9820 3656 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3657 continue;
3658 break;
3659 case 2:
8b38ad71
L		 3660 /* xchg %eax, %eax is a special case. It is an aliase for nop
3661 only in 32bit mode and we can use opcode 0x90. In 64bit
3662 mode, we can't use 0x90 for xchg %eax, %eax since it should
3663 zero-extend %eax to %rax. */
3664 if (flag_code == CODE_64BIT
3665 && t->base_opcode == 0x90
0dfbf9d7
L		 3666 && operand_type_equal (&i.types [0], &acc32)
3667 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3668 continue;
29b0f896 3669 case 3:
f48ff2ae 3670 case 4:
c0f3af97 3671 case 5:
c6fb90c8 3672 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3673 if (!operand_type_match (overlap0, i.types[0])
3674 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3675 || (check_register
3676 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3677 operand_types[0],
3678 overlap1, i.types[1],
3679 operand_types[1])))
29b0f896
AM		 3680 {
3681 /* Check if other direction is valid ... */
40fb9820 3682 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3683 continue;
3684
3685 /* Try reversing direction of operands. */
c6fb90c8
L		 3686 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3687 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3688 if (!operand_type_match (overlap0, i.types[0])
3689 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3690 || (check_register
3691 && !operand_type_register_match (overlap0,
3692 i.types[0],
3693 operand_types[1],
3694 overlap1,
3695 i.types[1],
3696 operand_types[0])))
29b0f896
AM		 3697 {
3698 /* Does not match either direction. */
3699 continue;
3700 }
3701 /* found_reverse_match holds which of D or FloatDR
3702 we've found. */
40fb9820 3703 if (t->opcode_modifier.d)
8a2ed489 3704 found_reverse_match = Opcode_D;
40fb9820 3705 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3706 found_reverse_match = Opcode_FloatD;
3707 else
3708 found_reverse_match = 0;
40fb9820 3709 if (t->opcode_modifier.floatr)
8a2ed489 3710 found_reverse_match |= Opcode_FloatR;
29b0f896 3711 }
f48ff2ae 3712 else
29b0f896 3713 {
f48ff2ae 3714 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3715 switch (t->operands)
3716 {
c0f3af97
L		 3717 case 5:
3718 overlap4 = operand_type_and (i.types[4],
3719 operand_types[4]);
d1cbb4db 3720 case 4:
c6fb90c8
L		 3721 overlap3 = operand_type_and (i.types[3],
3722 operand_types[3]);
d1cbb4db 3723 case 3:
c6fb90c8
L		 3724 overlap2 = operand_type_and (i.types[2],
3725 operand_types[2]);
d1cbb4db
L		 3726 break;
3727 }
29b0f896 3728
f48ff2ae
L		 3729 switch (t->operands)
3730 {
c0f3af97
L		 3731 case 5:
3732 if (!operand_type_match (overlap4, i.types[4])
3733 || !operand_type_register_match (overlap3,
3734 i.types[3],
3735 operand_types[3],
3736 overlap4,
3737 i.types[4],
3738 operand_types[4]))
3739 continue;
f48ff2ae 3740 case 4:
40fb9820 3741 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3742 || (check_register
3743 && !operand_type_register_match (overlap2,
3744 i.types[2],
3745 operand_types[2],
3746 overlap3,
3747 i.types[3],
3748 operand_types[3])))
f48ff2ae
L		 3749 continue;
3750 case 3:
3751 /* Here we make use of the fact that there are no
3752 reverse match 3 operand instructions, and all 3
3753 operand instructions only need to be checked for
3754 register consistency between operands 2 and 3. */
40fb9820 3755 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3756 || (check_register
3757 && !operand_type_register_match (overlap1,
3758 i.types[1],
3759 operand_types[1],
3760 overlap2,
3761 i.types[2],
3762 operand_types[2])))
f48ff2ae
L		 3763 continue;
3764 break;
3765 }
29b0f896 3766 }
f48ff2ae 3767 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3768 slip through to break. */
3769 }
3629bb00 3770 if (!found_cpu_match)
29b0f896
AM		 3771 {
3772 found_reverse_match = 0;
3773 continue;
3774 }
c0f3af97
L		 3775
3776 /* Check if VEX operands are valid. */
3777 if (VEX_check_operands (t))
3778 continue;
3779
29b0f896
AM		 3780 /* We've found a match; break out of loop. */
3781 break;
3782 }
3783
3784 if (t == current_templates->end)
3785 {
3786 /* We found no match. */
95f283e8
L		 3787 if (intel_syntax)
3788 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3789 current_templates->start->name);
3790 else
3791 as_bad (_("suffix or operands invalid for `%s'"),
3792 current_templates->start->name);
29b0f896
AM		 3793 return 0;
3794 }
252b5132 3795
29b0f896
AM		 3796 if (!quiet_warnings)
3797 {
3798 if (!intel_syntax
40fb9820
L		 3799 && (i.types[0].bitfield.jumpabsolute
3800 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3801 {
3802 as_warn (_("indirect %s without `*'"), t->name);
3803 }
3804
40fb9820
L		 3805 if (t->opcode_modifier.isprefix
3806 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3807 {
3808 /* Warn them that a data or address size prefix doesn't
3809 affect assembly of the next line of code. */
3810 as_warn (_("stand-alone `%s' prefix"), t->name);
3811 }
3812 }
3813
3814 /* Copy the template we found. */
3815 i.tm = *t;
539e75ad
L		 3816
3817 if (addr_prefix_disp != -1)
3818 i.tm.operand_types[addr_prefix_disp]
3819 = operand_types[addr_prefix_disp];
3820
29b0f896
AM		 3821 if (found_reverse_match)
3822 {
3823 /* If we found a reverse match we must alter the opcode
3824 direction bit. found_reverse_match holds bits to change
3825 (different for int & float insns). */
3826
3827 i.tm.base_opcode ^= found_reverse_match;
3828
539e75ad
L		 3829 i.tm.operand_types[0] = operand_types[1];
3830 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3831 }
3832
3833 return 1;
3834}
3835
3836static int
e3bb37b5 3837check_string (void)
29b0f896 3838{
40fb9820
L		 3839 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3840 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3841 {
3842 if (i.seg[0] != NULL && i.seg[0] != &es)
3843 {
3844 as_bad (_("`%s' operand %d must use `%%es' segment"),
3845 i.tm.name,
3846 mem_op + 1);
3847 return 0;
3848 }
3849 /* There's only ever one segment override allowed per instruction.
3850 This instruction possibly has a legal segment override on the
3851 second operand, so copy the segment to where non-string
3852 instructions store it, allowing common code. */
3853 i.seg[0] = i.seg[1];
3854 }
40fb9820 3855 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3856 {
3857 if (i.seg[1] != NULL && i.seg[1] != &es)
3858 {
3859 as_bad (_("`%s' operand %d must use `%%es' segment"),
3860 i.tm.name,
3861 mem_op + 2);
3862 return 0;
3863 }
3864 }
3865 return 1;
3866}
3867
3868static int
543613e9 3869process_suffix (void)
29b0f896
AM		 3870{
3871 /* If matched instruction specifies an explicit instruction mnemonic
3872 suffix, use it. */
40fb9820
L		 3873 if (i.tm.opcode_modifier.size16)
3874 i.suffix = WORD_MNEM_SUFFIX;
3875 else if (i.tm.opcode_modifier.size32)
3876 i.suffix = LONG_MNEM_SUFFIX;
3877 else if (i.tm.opcode_modifier.size64)
3878 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3879 else if (i.reg_operands)
3880 {
3881 /* If there's no instruction mnemonic suffix we try to invent one
3882 based on register operands. */
3883 if (!i.suffix)
3884 {
3885 /* We take i.suffix from the last register operand specified,
3886 Destination register type is more significant than source
381d071f
L		 3887 register type. crc32 in SSE4.2 prefers source register
3888 type. */
3889 if (i.tm.base_opcode == 0xf20f38f1)
3890 {
40fb9820
L		 3891 if (i.types[0].bitfield.reg16)
3892 i.suffix = WORD_MNEM_SUFFIX;
3893 else if (i.types[0].bitfield.reg32)
3894 i.suffix = LONG_MNEM_SUFFIX;
3895 else if (i.types[0].bitfield.reg64)
3896 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3897 }
9344ff29 3898 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3899 {
40fb9820 3900 if (i.types[0].bitfield.reg8)
20592a94
L		 3901 i.suffix = BYTE_MNEM_SUFFIX;
3902 }
381d071f
L		 3903
3904 if (!i.suffix)
3905 {
3906 int op;
3907
20592a94
L		 3908 if (i.tm.base_opcode == 0xf20f38f1
3909 || i.tm.base_opcode == 0xf20f38f0)
3910 {
3911 /* We have to know the operand size for crc32. */
3912 as_bad (_("ambiguous memory operand size for `%s`"),
3913 i.tm.name);
3914 return 0;
3915 }
3916
381d071f 3917 for (op = i.operands; --op >= 0;)
40fb9820 3918 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3919 {
40fb9820
L		 3920 if (i.types[op].bitfield.reg8)
3921 {
3922 i.suffix = BYTE_MNEM_SUFFIX;
3923 break;
3924 }
3925 else if (i.types[op].bitfield.reg16)
3926 {
3927 i.suffix = WORD_MNEM_SUFFIX;
3928 break;
3929 }
3930 else if (i.types[op].bitfield.reg32)
3931 {
3932 i.suffix = LONG_MNEM_SUFFIX;
3933 break;
3934 }
3935 else if (i.types[op].bitfield.reg64)
3936 {
3937 i.suffix = QWORD_MNEM_SUFFIX;
3938 break;
3939 }
381d071f
L		 3940 }
3941 }
29b0f896
AM		 3942 }
3943 else if (i.suffix == BYTE_MNEM_SUFFIX)
3944 {
3945 if (!check_byte_reg ())
3946 return 0;
3947 }
3948 else if (i.suffix == LONG_MNEM_SUFFIX)
3949 {
3950 if (!check_long_reg ())
3951 return 0;
3952 }
3953 else if (i.suffix == QWORD_MNEM_SUFFIX)
3954 {
955e1e6a
L		 3955 if (intel_syntax
3956 && i.tm.opcode_modifier.ignoresize
3957 && i.tm.opcode_modifier.no_qsuf)
3958 i.suffix = 0;
3959 else if (!check_qword_reg ())
29b0f896
AM		 3960 return 0;
3961 }
3962 else if (i.suffix == WORD_MNEM_SUFFIX)
3963 {
3964 if (!check_word_reg ())
3965 return 0;
3966 }
c0f3af97
L		 3967 else if (i.suffix == XMMWORD_MNEM_SUFFIX
3968 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 3969 {
c0f3af97 3970 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 3971 should check if it is a valid suffix. */
3972 }
40fb9820 3973 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3974 /* Do nothing if the instruction is going to ignore the prefix. */
3975 ;
3976 else
3977 abort ();
3978 }
40fb9820 3979 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3980 && !i.suffix
3981 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3982 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3983 {
3984 i.suffix = stackop_size;
3985 }
9306ca4a
JB		 3986 else if (intel_syntax
3987 && !i.suffix
40fb9820
L		 3988 && (i.tm.operand_types[0].bitfield.jumpabsolute
3989 || i.tm.opcode_modifier.jumpbyte
3990 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3991 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3992 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3993 {
3994 switch (flag_code)
3995 {
3996 case CODE_64BIT:
40fb9820 3997 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3998 {
3999 i.suffix = QWORD_MNEM_SUFFIX;
4000 break;
4001 }
4002 case CODE_32BIT:
40fb9820 4003 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4004 i.suffix = LONG_MNEM_SUFFIX;
4005 break;
4006 case CODE_16BIT:
40fb9820 4007 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4008 i.suffix = WORD_MNEM_SUFFIX;
4009 break;
4010 }
4011 }
252b5132 4012
9306ca4a 4013 if (!i.suffix)
29b0f896 4014 {
9306ca4a
JB		 4015 if (!intel_syntax)
4016 {
40fb9820 4017 if (i.tm.opcode_modifier.w)
9306ca4a 4018 {
4eed87de
AM		 4019 as_bad (_("no instruction mnemonic suffix given and "
4020 "no register operands; can't size instruction"));
9306ca4a
JB		 4021 return 0;
4022 }
4023 }
4024 else
4025 {
40fb9820
L		 4026 unsigned int suffixes;
4027
4028 suffixes = !i.tm.opcode_modifier.no_bsuf;
4029 if (!i.tm.opcode_modifier.no_wsuf)
4030 suffixes |= 1 << 1;
4031 if (!i.tm.opcode_modifier.no_lsuf)
4032 suffixes |= 1 << 2;
fc4adea1 4033 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4034 suffixes |= 1 << 3;
4035 if (!i.tm.opcode_modifier.no_ssuf)
4036 suffixes |= 1 << 4;
4037 if (!i.tm.opcode_modifier.no_qsuf)
4038 suffixes |= 1 << 5;
4039
4040 /* There are more than suffix matches. */
4041 if (i.tm.opcode_modifier.w
9306ca4a 4042 || ((suffixes & (suffixes - 1))
40fb9820
L		 4043 && !i.tm.opcode_modifier.defaultsize
4044 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4045 {
4046 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4047 return 0;
4048 }
4049 }
29b0f896 4050 }
252b5132 4051
9306ca4a
JB		 4052 /* Change the opcode based on the operand size given by i.suffix;
4053 We don't need to change things for byte insns. */
4054
582d5edd
L		 4055 if (i.suffix
4056 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4057 && i.suffix != XMMWORD_MNEM_SUFFIX
4058 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4059 {
4060 /* It's not a byte, select word/dword operation. */
40fb9820 4061 if (i.tm.opcode_modifier.w)
29b0f896 4062 {
40fb9820 4063 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4064 i.tm.base_opcode |= 8;
4065 else
4066 i.tm.base_opcode |= 1;
4067 }
0f3f3d8b 4068
29b0f896
AM		 4069 /* Now select between word & dword operations via the operand
4070 size prefix, except for instructions that will ignore this
4071 prefix anyway. */
ca61edf2 4072 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4073 {
ca61edf2
L		 4074 /* The address size override prefix changes the size of the
4075 first operand. */
40fb9820
L		 4076 if ((flag_code == CODE_32BIT
4077 && i.op->regs[0].reg_type.bitfield.reg16)
4078 || (flag_code != CODE_32BIT
4079 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4080 if (!add_prefix (ADDR_PREFIX_OPCODE))
4081 return 0;
4082 }
4083 else if (i.suffix != QWORD_MNEM_SUFFIX
4084 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4085 && !i.tm.opcode_modifier.ignoresize
4086 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4087 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4088 || (flag_code == CODE_64BIT
40fb9820 4089 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4090 {
4091 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4092
40fb9820 4093 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4094 prefix = ADDR_PREFIX_OPCODE;
252b5132 4095
29b0f896
AM		 4096 if (!add_prefix (prefix))
4097 return 0;
24eab124 4098 }
252b5132 4099
29b0f896
AM		 4100 /* Set mode64 for an operand. */
4101 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4102 && flag_code == CODE_64BIT
40fb9820 4103 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4104 {
4105 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4106 need rex64. cmpxchg8b is also a special case. */
4107 if (! (i.operands == 2
4108 && i.tm.base_opcode == 0x90
4109 && i.tm.extension_opcode == None
0dfbf9d7
L		 4110 && operand_type_equal (&i.types [0], &acc64)
4111 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4112 && ! (i.operands == 1
4113 && i.tm.base_opcode == 0xfc7
4114 && i.tm.extension_opcode == 1
40fb9820
L		 4115 && !operand_type_check (i.types [0], reg)
4116 && operand_type_check (i.types [0], anymem)))
f6bee062 4117 i.rex |= REX_W;
46e883c5 4118 }
3e73aa7c 4119
29b0f896
AM		 4120 /* Size floating point instruction. */
4121 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4122 if (i.tm.opcode_modifier.floatmf)
543613e9 4123 i.tm.base_opcode ^= 4;
29b0f896 4124 }
7ecd2f8b 4125
29b0f896
AM		 4126 return 1;
4127}
3e73aa7c 4128
29b0f896 4129static int
543613e9 4130check_byte_reg (void)
29b0f896
AM		 4131{
4132 int op;
543613e9 4133
29b0f896
AM		 4134 for (op = i.operands; --op >= 0;)
4135 {
4136 /* If this is an eight bit register, it's OK. If it's the 16 or
4137 32 bit version of an eight bit register, we will just use the
4138 low portion, and that's OK too. */
40fb9820 4139 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4140 continue;
4141
ca61edf2
L		 4142 /* Don't generate this warning if not needed. */
4143 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4144 continue;
4145
9344ff29
L		 4146 /* crc32 doesn't generate this warning. */
4147 if (i.tm.base_opcode == 0xf20f38f0)
4148 continue;
4149
40fb9820
L		 4150 if ((i.types[op].bitfield.reg16
4151 || i.types[op].bitfield.reg32
4152 || i.types[op].bitfield.reg64)
4153 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4154 {
4155 /* Prohibit these changes in the 64bit mode, since the
4156 lowering is more complicated. */
4157 if (flag_code == CODE_64BIT
40fb9820 4158 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4159 {
2ca3ace5
L		 4160 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4161 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4162 i.suffix);
4163 return 0;
4164 }
4165#if REGISTER_WARNINGS
4166 if (!quiet_warnings
40fb9820 4167 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4168 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4169 register_prefix,
40fb9820 4170 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4171 ? REGNAM_AL - REGNAM_AX
4172 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4173 register_prefix,
29b0f896
AM		 4174 i.op[op].regs->reg_name,
4175 i.suffix);
4176#endif
4177 continue;
4178 }
4179 /* Any other register is bad. */
40fb9820
L		 4180 if (i.types[op].bitfield.reg16
4181 || i.types[op].bitfield.reg32
4182 || i.types[op].bitfield.reg64
4183 || i.types[op].bitfield.regmmx
4184 || i.types[op].bitfield.regxmm
c0f3af97 4185 || i.types[op].bitfield.regymm
40fb9820
L		 4186 || i.types[op].bitfield.sreg2
4187 || i.types[op].bitfield.sreg3
4188 || i.types[op].bitfield.control
4189 || i.types[op].bitfield.debug
4190 || i.types[op].bitfield.test
4191 || i.types[op].bitfield.floatreg
4192 || i.types[op].bitfield.floatacc)
29b0f896 4193 {
a540244d
L		 4194 as_bad (_("`%s%s' not allowed with `%s%c'"),
4195 register_prefix,
29b0f896
AM		 4196 i.op[op].regs->reg_name,
4197 i.tm.name,
4198 i.suffix);
4199 return 0;
4200 }
4201 }
4202 return 1;
4203}
4204
4205static int
e3bb37b5 4206check_long_reg (void)
29b0f896
AM		 4207{
4208 int op;
4209
4210 for (op = i.operands; --op >= 0;)
4211 /* Reject eight bit registers, except where the template requires
4212 them. (eg. movzb) */
40fb9820
L		 4213 if (i.types[op].bitfield.reg8
4214 && (i.tm.operand_types[op].bitfield.reg16
4215 || i.tm.operand_types[op].bitfield.reg32
4216 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4217 {
a540244d
L		 4218 as_bad (_("`%s%s' not allowed with `%s%c'"),
4219 register_prefix,
29b0f896
AM		 4220 i.op[op].regs->reg_name,
4221 i.tm.name,
4222 i.suffix);
4223 return 0;
4224 }
4225 /* Warn if the e prefix on a general reg is missing. */
4226 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4227 && i.types[op].bitfield.reg16
4228 && (i.tm.operand_types[op].bitfield.reg32
4229 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4230 {
4231 /* Prohibit these changes in the 64bit mode, since the
4232 lowering is more complicated. */
4233 if (flag_code == CODE_64BIT)
252b5132 4234 {
2ca3ace5
L		 4235 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4236 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4237 i.suffix);
4238 return 0;
252b5132 4239 }
29b0f896
AM		 4240#if REGISTER_WARNINGS
4241 else
a540244d
L		 4242 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4243 register_prefix,
29b0f896 4244 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4245 register_prefix,
29b0f896
AM		 4246 i.op[op].regs->reg_name,
4247 i.suffix);
4248#endif
252b5132 4249 }
29b0f896 4250 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4251 else if (i.types[op].bitfield.reg64
4252 && (i.tm.operand_types[op].bitfield.reg32
4253 || i.tm.operand_types[op].bitfield.acc))
252b5132 4254 {
34828aad 4255 if (intel_syntax
ca61edf2 4256 && i.tm.opcode_modifier.toqword
40fb9820 4257 && !i.types[0].bitfield.regxmm)
34828aad 4258 {
ca61edf2 4259 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4260 i.suffix = QWORD_MNEM_SUFFIX;
4261 }
4262 else
4263 {
4264 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4265 register_prefix, i.op[op].regs->reg_name,
4266 i.suffix);
4267 return 0;
4268 }
29b0f896
AM		 4269 }
4270 return 1;
4271}
252b5132 4272
29b0f896 4273static int
e3bb37b5 4274check_qword_reg (void)
29b0f896
AM		 4275{
4276 int op;
252b5132 4277
29b0f896
AM		 4278 for (op = i.operands; --op >= 0; )
4279 /* Reject eight bit registers, except where the template requires
4280 them. (eg. movzb) */
40fb9820
L		 4281 if (i.types[op].bitfield.reg8
4282 && (i.tm.operand_types[op].bitfield.reg16
4283 || i.tm.operand_types[op].bitfield.reg32
4284 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4285 {
a540244d
L		 4286 as_bad (_("`%s%s' not allowed with `%s%c'"),
4287 register_prefix,
29b0f896
AM		 4288 i.op[op].regs->reg_name,
4289 i.tm.name,
4290 i.suffix);
4291 return 0;
4292 }
4293 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4294 else if ((i.types[op].bitfield.reg16
4295 || i.types[op].bitfield.reg32)
4296 && (i.tm.operand_types[op].bitfield.reg32
4297 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4298 {
4299 /* Prohibit these changes in the 64bit mode, since the
4300 lowering is more complicated. */
34828aad 4301 if (intel_syntax
ca61edf2 4302 && i.tm.opcode_modifier.todword
40fb9820 4303 && !i.types[0].bitfield.regxmm)
34828aad 4304 {
ca61edf2 4305 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4306 i.suffix = LONG_MNEM_SUFFIX;
4307 }
4308 else
4309 {
4310 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4311 register_prefix, i.op[op].regs->reg_name,
4312 i.suffix);
4313 return 0;
4314 }
252b5132 4315 }
29b0f896
AM		 4316 return 1;
4317}
252b5132 4318
29b0f896 4319static int
e3bb37b5 4320check_word_reg (void)
29b0f896
AM		 4321{
4322 int op;
4323 for (op = i.operands; --op >= 0;)
4324 /* Reject eight bit registers, except where the template requires
4325 them. (eg. movzb) */
40fb9820
L		 4326 if (i.types[op].bitfield.reg8
4327 && (i.tm.operand_types[op].bitfield.reg16
4328 || i.tm.operand_types[op].bitfield.reg32
4329 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4330 {
a540244d
L		 4331 as_bad (_("`%s%s' not allowed with `%s%c'"),
4332 register_prefix,
29b0f896
AM		 4333 i.op[op].regs->reg_name,
4334 i.tm.name,
4335 i.suffix);
4336 return 0;
4337 }
4338 /* Warn if the e prefix on a general reg is present. */
4339 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4340 && i.types[op].bitfield.reg32
4341 && (i.tm.operand_types[op].bitfield.reg16
4342 || i.tm.operand_types[op].bitfield.acc))
252b5132 4343 {
29b0f896
AM		 4344 /* Prohibit these changes in the 64bit mode, since the
4345 lowering is more complicated. */
4346 if (flag_code == CODE_64BIT)
252b5132 4347 {
2ca3ace5
L		 4348 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4349 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4350 i.suffix);
4351 return 0;
252b5132 4352 }
29b0f896
AM		 4353 else
4354#if REGISTER_WARNINGS
a540244d
L		 4355 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4356 register_prefix,
29b0f896 4357 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4358 register_prefix,
29b0f896
AM		 4359 i.op[op].regs->reg_name,
4360 i.suffix);
4361#endif
4362 }
4363 return 1;
4364}
252b5132 4365
29b0f896 4366static int
40fb9820 4367update_imm (unsigned int j)
29b0f896 4368{
40fb9820
L		 4369 i386_operand_type overlap;
4370
c6fb90c8 4371 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4372 if ((overlap.bitfield.imm8
4373 || overlap.bitfield.imm8s
4374 || overlap.bitfield.imm16
4375 || overlap.bitfield.imm32
4376 || overlap.bitfield.imm32s
4377 || overlap.bitfield.imm64)
0dfbf9d7
L		 4378 && !operand_type_equal (&overlap, &imm8)
4379 && !operand_type_equal (&overlap, &imm8s)
4380 && !operand_type_equal (&overlap, &imm16)
4381 && !operand_type_equal (&overlap, &imm32)
4382 && !operand_type_equal (&overlap, &imm32s)
4383 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4384 {
4385 if (i.suffix)
4386 {
40fb9820
L		 4387 i386_operand_type temp;
4388
0dfbf9d7 4389 operand_type_set (&temp, 0);
40fb9820
L		 4390 if (i.suffix == BYTE_MNEM_SUFFIX)
4391 {
4392 temp.bitfield.imm8 = overlap.bitfield.imm8;
4393 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4394 }
4395 else if (i.suffix == WORD_MNEM_SUFFIX)
4396 temp.bitfield.imm16 = overlap.bitfield.imm16;
4397 else if (i.suffix == QWORD_MNEM_SUFFIX)
4398 {
4399 temp.bitfield.imm64 = overlap.bitfield.imm64;
4400 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4401 }
4402 else
4403 temp.bitfield.imm32 = overlap.bitfield.imm32;
4404 overlap = temp;
29b0f896 4405 }
0dfbf9d7
L		 4406 else if (operand_type_equal (&overlap, &imm16_32_32s)
4407 || operand_type_equal (&overlap, &imm16_32)
4408 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4409 {
40fb9820 4410 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4411 overlap = imm16;
40fb9820 4412 else
65da13b5 4413 overlap = imm32s;
29b0f896 4414 }
0dfbf9d7
L		 4415 if (!operand_type_equal (&overlap, &imm8)
4416 && !operand_type_equal (&overlap, &imm8s)
4417 && !operand_type_equal (&overlap, &imm16)
4418 && !operand_type_equal (&overlap, &imm32)
4419 && !operand_type_equal (&overlap, &imm32s)
4420 && !operand_type_equal (&overlap, &imm64))
29b0f896 4421 {
4eed87de
AM		 4422 as_bad (_("no instruction mnemonic suffix given; "
4423 "can't determine immediate size"));
29b0f896
AM		 4424 return 0;
4425 }
4426 }
40fb9820 4427 i.types[j] = overlap;
29b0f896 4428
40fb9820
L		 4429 return 1;
4430}
4431
4432static int
4433finalize_imm (void)
4434{
4435 unsigned int j;
29b0f896 4436
40fb9820
L		 4437 for (j = 0; j < 2; j++)
4438 if (update_imm (j) == 0)
4439 return 0;
4440
c6fb90c8 4441 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4442 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4443
4444 return 1;
4445}
4446
85f10a01
MM		 4447static void
4448process_drex (void)
4449{
5dd15031
JJ		 4450 i.drex.modrm_reg = 0;
4451 i.drex.modrm_regmem = 0;
85f10a01
MM		 4452
4453 /* SSE5 4 operand instructions must have the destination the same as
4454 one of the inputs. Figure out the destination register and cache
4455 it away in the drex field, and remember which fields to use for
4456 the modrm byte. */
4457 if (i.tm.opcode_modifier.drex
4458 && i.tm.opcode_modifier.drexv
4459 && i.operands == 4)
4460 {
4461 i.tm.extension_opcode = None;
4462
4463 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4464 if (i.types[0].bitfield.regxmm != 0
4465 && i.types[1].bitfield.regxmm != 0
4466 && i.types[2].bitfield.regxmm != 0
4467 && i.types[3].bitfield.regxmm != 0
4468 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4469 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4470 {
4471 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4472 operand_type_set (&i.types[0], 0);
4473 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4474 i.reg_operands -= 2;
4475
4476 /* There are two different ways to encode a 4 operand
4477 instruction with all registers that uses OC1 set to
4478 0 or 1. Favor setting OC1 to 0 since this mimics the
4479 actions of other SSE5 assemblers. Use modrm encoding 2
4480 for register/register. Include the high order bit that
4481 is normally stored in the REX byte in the register
4482 field. */
4483 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4484 i.drex.modrm_reg = 2;
4485 i.drex.modrm_regmem = 1;
4486 i.drex.reg = (i.op[3].regs->reg_num
4487 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4488 }
4489
4490 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4491 else if (i.types[0].bitfield.regxmm != 0
4492 && i.types[1].bitfield.regxmm != 0
4493 && (i.types[2].bitfield.regxmm
4494 || operand_type_check (i.types[2], anymem))
4495 && i.types[3].bitfield.regxmm != 0
4496 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4497 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4498 {
4499 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4500 operand_type_set (&i.types[0], 0);
4501 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4502 i.reg_operands -= 2;
4503
4504 /* Specify the modrm encoding for memory addressing. Include
4505 the high order bit that is normally stored in the REX byte
4506 in the register field. */
4507 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4508 i.drex.modrm_reg = 1;
4509 i.drex.modrm_regmem = 2;
4510 i.drex.reg = (i.op[3].regs->reg_num
4511 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4512 }
4513
4514 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4515 else if (i.types[0].bitfield.regxmm != 0
4516 && operand_type_check (i.types[1], anymem) != 0
4517 && i.types[2].bitfield.regxmm != 0
4518 && i.types[3].bitfield.regxmm != 0
4519 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4520 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4521 {
4522 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4523 operand_type_set (&i.types[0], 0);
4524 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4525 i.reg_operands -= 2;
4526
4527 /* Specify the modrm encoding for memory addressing. Include
4528 the high order bit that is normally stored in the REX byte
4529 in the register field. */
4530 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4531 i.drex.modrm_reg = 2;
4532 i.drex.modrm_regmem = 1;
4533 i.drex.reg = (i.op[3].regs->reg_num
4534 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4535 }
4536
4537 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4538 else if (i.types[0].bitfield.regxmm != 0
4539 && i.types[1].bitfield.regxmm != 0
4540 && i.types[2].bitfield.regxmm != 0
4541 && i.types[3].bitfield.regxmm != 0
4542 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4543 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4544 {
4545 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4546 operand_type_set (&i.types[2], 0);
4547 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4548 i.reg_operands -= 2;
4549
4550 /* There are two different ways to encode a 4 operand
4551 instruction with all registers that uses OC1 set to
4552 0 or 1. Favor setting OC1 to 0 since this mimics the
4553 actions of other SSE5 assemblers. Use modrm encoding
4554 2 for register/register. Include the high order bit that
4555 is normally stored in the REX byte in the register
4556 field. */
4557 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4558 i.drex.modrm_reg = 1;
4559 i.drex.modrm_regmem = 0;
4560
4561 /* Remember the register, including the upper bits */
4562 i.drex.reg = (i.op[3].regs->reg_num
4563 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4564 }
4565
4566 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4567 else if (i.types[0].bitfield.regxmm != 0
4568 && (i.types[1].bitfield.regxmm
4569 || operand_type_check (i.types[1], anymem))
4570 && i.types[2].bitfield.regxmm != 0
4571 && i.types[3].bitfield.regxmm != 0
4572 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4573 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4574 {
4575 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4576 operand_type_set (&i.types[2], 0);
4577 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4578 i.reg_operands -= 2;
4579
4580 /* Specify the modrm encoding and remember the register
4581 including the bits normally stored in the REX byte. */
4582 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4583 i.drex.modrm_reg = 0;
4584 i.drex.modrm_regmem = 1;
4585 i.drex.reg = (i.op[3].regs->reg_num
4586 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4587 }
4588
4589 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4590 else if (operand_type_check (i.types[0], anymem) != 0
4591 && i.types[1].bitfield.regxmm != 0
4592 && i.types[2].bitfield.regxmm != 0
4593 && i.types[3].bitfield.regxmm != 0
4594 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4595 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4596 {
4597 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4598 operand_type_set (&i.types[2], 0);
4599 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4600 i.reg_operands -= 2;
4601
4602 /* Specify the modrm encoding and remember the register
4603 including the bits normally stored in the REX byte. */
4604 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4605 i.drex.modrm_reg = 1;
4606 i.drex.modrm_regmem = 0;
4607 i.drex.reg = (i.op[3].regs->reg_num
4608 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4609 }
4610
4611 else
4612 as_bad (_("Incorrect operands for the '%s' instruction"),
4613 i.tm.name);
4614 }
4615
4616 /* SSE5 instructions with the DREX byte where the only memory operand
4617 is in the 2nd argument, and the first and last xmm register must
4618 match, and is encoded in the DREX byte. */
4619 else if (i.tm.opcode_modifier.drex
4620 && !i.tm.opcode_modifier.drexv
4621 && i.operands == 4)
4622 {
4623 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4624 if (i.types[0].bitfield.regxmm != 0
4625 && (i.types[1].bitfield.regxmm
4626 || operand_type_check(i.types[1], anymem))
4627 && i.types[2].bitfield.regxmm != 0
4628 && i.types[3].bitfield.regxmm != 0
4629 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4630 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4631 {
4632 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4633 operand_type_set (&i.types[0], 0);
4634 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4635 i.reg_operands -= 2;
4636
4637 /* Specify the modrm encoding and remember the register
4638 including the high bit normally stored in the REX
4639 byte. */
4640 i.drex.modrm_reg = 2;
4641 i.drex.modrm_regmem = 1;
4642 i.drex.reg = (i.op[3].regs->reg_num
4643 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4644 }
4645
4646 else
4647 as_bad (_("Incorrect operands for the '%s' instruction"),
4648 i.tm.name);
4649 }
4650
4651 /* SSE5 3 operand instructions that the result is a register, being
4652 either operand can be a memory operand, using OC0 to note which
4653 one is the memory. */
4654 else if (i.tm.opcode_modifier.drex
4655 && i.tm.opcode_modifier.drexv
4656 && i.operands == 3)
4657 {
4658 i.tm.extension_opcode = None;
4659
4660 /* Case 1: 3 operand insn, src1 = register. */
4661 if (i.types[0].bitfield.regxmm != 0
4662 && i.types[1].bitfield.regxmm != 0
4663 && i.types[2].bitfield.regxmm != 0)
4664 {
4665 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4666 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4667 i.reg_operands--;
4668
4669 /* Specify the modrm encoding and remember the register
4670 including the high bit normally stored in the REX byte. */
4671 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4672 i.drex.modrm_reg = 1;
4673 i.drex.modrm_regmem = 0;
4674 i.drex.reg = (i.op[2].regs->reg_num
4675 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4676 }
4677
4678 /* Case 2: 3 operand insn, src1 = memory. */
4679 else if (operand_type_check (i.types[0], anymem) != 0
4680 && i.types[1].bitfield.regxmm != 0
4681 && i.types[2].bitfield.regxmm != 0)
4682 {
4683 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4684 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4685 i.reg_operands--;
4686
4687 /* Specify the modrm encoding and remember the register
4688 including the high bit normally stored in the REX
4689 byte. */
4690 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4691 i.drex.modrm_reg = 1;
4692 i.drex.modrm_regmem = 0;
4693 i.drex.reg = (i.op[2].regs->reg_num
4694 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4695 }
4696
4697 /* Case 3: 3 operand insn, src2 = memory. */
4698 else if (i.types[0].bitfield.regxmm != 0
4699 && operand_type_check (i.types[1], anymem) != 0
4700 && i.types[2].bitfield.regxmm != 0)
4701 {
4702 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4703 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4704 i.reg_operands--;
4705
4706 /* Specify the modrm encoding and remember the register
4707 including the high bit normally stored in the REX byte. */
4708 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4709 i.drex.modrm_reg = 0;
4710 i.drex.modrm_regmem = 1;
4711 i.drex.reg = (i.op[2].regs->reg_num
4712 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4713 }
4714
4715 else
4716 as_bad (_("Incorrect operands for the '%s' instruction"),
4717 i.tm.name);
4718 }
4719
4720 /* SSE5 4 operand instructions that are the comparison instructions
4721 where the first operand is the immediate value of the comparison
4722 to be done. */
4723 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4724 {
4725 /* Case 1: 4 operand insn, src1 = reg/memory. */
4726 if (operand_type_check (i.types[0], imm) != 0
4727 && (i.types[1].bitfield.regxmm
4728 || operand_type_check (i.types[1], anymem))
4729 && i.types[2].bitfield.regxmm != 0
4730 && i.types[3].bitfield.regxmm != 0)
4731 {
4732 /* clear the arguments that are stored in drex */
0dfbf9d7 4733 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4734 i.reg_operands--;
4735
4736 /* Specify the modrm encoding and remember the register
4737 including the high bit normally stored in the REX byte. */
4738 i.drex.modrm_reg = 2;
4739 i.drex.modrm_regmem = 1;
4740 i.drex.reg = (i.op[3].regs->reg_num
4741 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4742 }
4743
4744 /* Case 2: 3 operand insn with ImmExt that places the
4745 opcode_extension as an immediate argument. This is used for
4746 all of the varients of comparison that supplies the appropriate
4747 value as part of the instruction. */
4748 else if ((i.types[0].bitfield.regxmm
4749 || operand_type_check (i.types[0], anymem))
4750 && i.types[1].bitfield.regxmm != 0
4751 && i.types[2].bitfield.regxmm != 0
4752 && operand_type_check (i.types[3], imm) != 0)
4753 {
4754 /* clear the arguments that are stored in drex */
0dfbf9d7 4755 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4756 i.reg_operands--;
4757
4758 /* Specify the modrm encoding and remember the register
4759 including the high bit normally stored in the REX byte. */
4760 i.drex.modrm_reg = 1;
4761 i.drex.modrm_regmem = 0;
4762 i.drex.reg = (i.op[2].regs->reg_num
4763 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4764 }
4765
4766 else
4767 as_bad (_("Incorrect operands for the '%s' instruction"),
4768 i.tm.name);
4769 }
4770
4771 else if (i.tm.opcode_modifier.drex
4772 || i.tm.opcode_modifier.drexv
4773 || i.tm.opcode_modifier.drexc)
4774 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4775}
4776
c0f3af97
L		 4777static int
4778bad_implicit_operand (int xmm)
4779{
4780 const char *reg = xmm ? "xmm0" : "ymm0";
4781 if (intel_syntax)
4782 as_bad (_("the last operand of `%s' must be `%s%s'"),
4783 i.tm.name, register_prefix, reg);
4784 else
4785 as_bad (_("the first operand of `%s' must be `%s%s'"),
4786 i.tm.name, register_prefix, reg);
4787 return 0;
4788}
4789
29b0f896 4790static int
e3bb37b5 4791process_operands (void)
29b0f896
AM		 4792{
4793 /* Default segment register this instruction will use for memory
4794 accesses. 0 means unknown. This is only for optimizing out
4795 unnecessary segment overrides. */
4796 const seg_entry *default_seg = 0;
4797
85f10a01
MM		 4798 /* Handle all of the DREX munging that SSE5 needs. */
4799 if (i.tm.opcode_modifier.drex
4800 || i.tm.opcode_modifier.drexv
4801 || i.tm.opcode_modifier.drexc)
4802 process_drex ();
4803
c0f3af97
L		 4804 if (i.tm.opcode_modifier.sse2avx
4805 && (i.tm.opcode_modifier.vexnds
4806 || i.tm.opcode_modifier.vexndd))
29b0f896 4807 {
c0f3af97
L		 4808 unsigned int dup = i.operands;
4809 unsigned int dest = dup - 1;
9fcfb3d7
L		 4810 unsigned int j;
4811
c0f3af97 4812 /* The destination must be an xmm register. */
0dfbf9d7 4813 assert (i.reg_operands
c0f3af97
L		 4814 && MAX_OPERANDS > dup
4815 && operand_type_equal (&i.types[dest], &regxmm));
4816
4817 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4818 {
c0f3af97
L		 4819 /* The first operand is implicit and must be xmm0. */
4820 assert (operand_type_equal (&i.types[0], &regxmm));
4821 if (i.op[0].regs->reg_num != 0)
4822 return bad_implicit_operand (1);
4823
4824 if (i.tm.opcode_modifier.vex3sources)
4825 {
4826 /* Keep xmm0 for instructions with VEX prefix and 3
4827 sources. */
4828 goto duplicate;
4829 }
e2ec9d29 4830 else
c0f3af97
L		 4831 {
4832 /* We remove the first xmm0 and keep the number of
4833 operands unchanged, which in fact duplicates the
4834 destination. */
4835 for (j = 1; j < i.operands; j++)
4836 {
4837 i.op[j - 1] = i.op[j];
4838 i.types[j - 1] = i.types[j];
4839 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4840 }
4841 }
4842 }
4843 else if (i.tm.opcode_modifier.implicit1stxmm0)
4844 {
4845 assert ((MAX_OPERANDS - 1) > dup
4846 && i.tm.opcode_modifier.vex3sources);
4847
4848 /* Add the implicit xmm0 for instructions with VEX prefix
4849 and 3 sources. */
4850 for (j = i.operands; j > 0; j--)
4851 {
4852 i.op[j] = i.op[j - 1];
4853 i.types[j] = i.types[j - 1];
4854 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4855 }
4856 i.op[0].regs
4857 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4858 i.types[0] = regxmm;
4859 i.tm.operand_types[0] = regxmm;
4860
4861 i.operands += 2;
4862 i.reg_operands += 2;
4863 i.tm.operands += 2;
4864
4865 dup++;
4866 dest++;
4867 i.op[dup] = i.op[dest];
4868 i.types[dup] = i.types[dest];
4869 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4870 }
c0f3af97
L		 4871 else
4872 {
4873duplicate:
4874 i.operands++;
4875 i.reg_operands++;
4876 i.tm.operands++;
4877
4878 i.op[dup] = i.op[dest];
4879 i.types[dup] = i.types[dest];
4880 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4881 }
4882
4883 if (i.tm.opcode_modifier.immext)
4884 process_immext ();
4885 }
4886 else if (i.tm.opcode_modifier.firstxmm0)
4887 {
4888 unsigned int j;
4889
4890 /* The first operand is implicit and must be xmm0/ymm0. */
4891 assert (i.reg_operands
4892 && (operand_type_equal (&i.types[0], &regxmm)
4893 || operand_type_equal (&i.types[0], &regymm)));
4894 if (i.op[0].regs->reg_num != 0)
4895 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4896
4897 for (j = 1; j < i.operands; j++)
4898 {
4899 i.op[j - 1] = i.op[j];
4900 i.types[j - 1] = i.types[j];
4901
4902 /* We need to adjust fields in i.tm since they are used by
4903 build_modrm_byte. */
4904 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4905 }
4906
e2ec9d29
L		 4907 i.operands--;
4908 i.reg_operands--;
e2ec9d29
L		 4909 i.tm.operands--;
4910 }
4911 else if (i.tm.opcode_modifier.regkludge)
4912 {
4913 /* The imul $imm, %reg instruction is converted into
4914 imul $imm, %reg, %reg, and the clr %reg instruction
4915 is converted into xor %reg, %reg. */
4916
4917 unsigned int first_reg_op;
4918
4919 if (operand_type_check (i.types[0], reg))
4920 first_reg_op = 0;
4921 else
4922 first_reg_op = 1;
4923 /* Pretend we saw the extra register operand. */
4924 assert (i.reg_operands == 1
4925 && i.op[first_reg_op + 1].regs == 0);
4926 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4927 i.types[first_reg_op + 1] = i.types[first_reg_op];
4928 i.operands++;
4929 i.reg_operands++;
29b0f896
AM		 4930 }
4931
40fb9820 4932 if (i.tm.opcode_modifier.shortform)
29b0f896 4933 {
40fb9820
L		 4934 if (i.types[0].bitfield.sreg2
4935 || i.types[0].bitfield.sreg3)
29b0f896 4936 {
4eed87de
AM		 4937 if (i.tm.base_opcode == POP_SEG_SHORT
4938 && i.op[0].regs->reg_num == 1)
29b0f896 4939 {
4eed87de
AM		 4940 as_bad (_("you can't `pop %%cs'"));
4941 return 0;
29b0f896 4942 }
4eed87de
AM		 4943 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4944 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4945 i.rex |= REX_B;
4eed87de
AM		 4946 }
4947 else
4948 {
85f10a01
MM		 4949 /* The register or float register operand is in operand
4950 0 or 1. */
40fb9820
L		 4951 unsigned int op;
4952
4953 if (i.types[0].bitfield.floatreg
4954 || operand_type_check (i.types[0], reg))
4955 op = 0;
4956 else
4957 op = 1;
4eed87de
AM		 4958 /* Register goes in low 3 bits of opcode. */
4959 i.tm.base_opcode |= i.op[op].regs->reg_num;
4960 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4961 i.rex |= REX_B;
40fb9820 4962 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4963 {
4eed87de
AM		 4964 /* Warn about some common errors, but press on regardless.
4965 The first case can be generated by gcc (<= 2.8.1). */
4966 if (i.operands == 2)
4967 {
4968 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4969 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4970 register_prefix, i.op[1].regs->reg_name,
4971 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4972 }
4973 else
4974 {
4975 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4976 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4977 register_prefix, i.op[0].regs->reg_name);
4eed87de 4978 }
29b0f896
AM		 4979 }
4980 }
4981 }
40fb9820 4982 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4983 {
4984 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4985 must be put into the modrm byte). Now, we make the modrm and
4986 index base bytes based on all the info we've collected. */
29b0f896
AM		 4987
4988 default_seg = build_modrm_byte ();
4989 }
8a2ed489 4990 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4991 {
4992 default_seg = &ds;
4993 }
40fb9820 4994 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4995 {
4996 /* For the string instructions that allow a segment override
4997 on one of their operands, the default segment is ds. */
4998 default_seg = &ds;
4999 }
5000
75178d9d
L		 5001 if (i.tm.base_opcode == 0x8d /* lea */
5002 && i.seg[0]
5003 && !quiet_warnings)
30123838 5004 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5005
5006 /* If a segment was explicitly specified, and the specified segment
5007 is not the default, use an opcode prefix to select it. If we
5008 never figured out what the default segment is, then default_seg
5009 will be zero at this point, and the specified segment prefix will
5010 always be used. */
29b0f896
AM		 5011 if ((i.seg[0]) && (i.seg[0] != default_seg))
5012 {
5013 if (!add_prefix (i.seg[0]->seg_prefix))
5014 return 0;
5015 }
5016 return 1;
5017}
5018
5019static const seg_entry *
e3bb37b5 5020build_modrm_byte (void)
29b0f896
AM		 5021{
5022 const seg_entry *default_seg = 0;
c0f3af97
L		 5023 unsigned int source, dest;
5024 int vex_3_sources;
5025
5026 /* The first operand of instructions with VEX prefix and 3 sources
5027 must be VEX_Imm4. */
5028 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5029 if (vex_3_sources)
5030 {
5031 unsigned int nds, reg;
5032
5033 if (i.tm.opcode_modifier.veximmext
5034 && i.tm.opcode_modifier.immext)
5035 {
5036 dest = i.operands - 2;
5037 assert (dest == 3);
5038 }
5039 else
5040 dest = i.operands - 1;
5041 nds = dest - 1;
5042
5043 /* There are 2 kinds of instructions:
dae39acc 5044 1. 5 operands: one immediate operand and 4 register
c0f3af97
L		 5045 operands or 3 register operands plus 1 memory operand.
5046 It must have VexNDS and VexW0 or VexW1. The destination
5047 must be either XMM or YMM register.
5048 2. 4 operands: 4 register operands or 3 register operands
5049 plus 1 memory operand. It must have VexNDS and VexImmExt. */
5050 if (!((i.reg_operands == 4
5051 || (i.reg_operands == 3 && i.mem_operands == 1))
5052 && i.tm.opcode_modifier.vexnds
5053 && (operand_type_equal (&i.tm.operand_types[dest], &regxmm)
5054 || operand_type_equal (&i.tm.operand_types[dest], &regymm))
c0f3af97
L		 5055 && ((dest == 4
5056 && i.imm_operands == 1
5057 && i.types[0].bitfield.vex_imm4
5058 && (i.tm.opcode_modifier.vexw0
5059 || i.tm.opcode_modifier.vexw1))
5060 || (dest == 3
5061 && (i.imm_operands == 0
5062 || (i.imm_operands == 1
5063 && i.tm.opcode_modifier.immext))
5064 && i.tm.opcode_modifier.veximmext))))
5065 abort ();
5066
c0f3af97
L		 5067 if (i.imm_operands == 0)
5068 {
5069 /* When there is no immediate operand, generate an 8bit
5070 immediate operand to encode the first operand. */
5071 expressionS *exp = &im_expressions[i.imm_operands++];
5072 i.op[i.operands].imms = exp;
5073 i.types[i.operands] = imm8;
5074 i.operands++;
5075 /* If VexW1 is set, the first operand is the source and
5076 the second operand is encoded in the immediate operand. */
5077 if (i.tm.opcode_modifier.vexw1)
5078 {
5079 source = 0;
5080 reg = 1;
5081 }
5082 else
5083 {
5084 source = 1;
5085 reg = 0;
5086 }
dae39acc
L		 5087
5088 /* FMA swaps REG and NDS. */
5089 if (i.tm.cpu_flags.bitfield.cpufma)
5090 {
5091 unsigned int tmp;
5092 tmp = reg;
5093 reg = nds;
5094 nds = tmp;
5095 }
5096
c0f3af97
L		 5097 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5098 || operand_type_equal (&i.tm.operand_types[reg],
5099 &regymm));
5100 exp->X_op = O_constant;
5101 exp->X_add_number
5102 = ((i.op[reg].regs->reg_num
5103 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5104 }
5105 else
5106 {
5107 unsigned int imm;
5108
5109 if (i.tm.opcode_modifier.vexw0)
5110 {
5111 /* If VexW0 is set, the third operand is the source and
5112 the second operand is encoded in the immediate
5113 operand. */
5114 source = 2;
5115 reg = 1;
5116 }
5117 else
5118 {
5119 /* VexW1 is set, the second operand is the source and
5120 the third operand is encoded in the immediate
5121 operand. */
5122 source = 1;
5123 reg = 2;
5124 }
5125
5126 if (i.tm.opcode_modifier.immext)
5127 {
5128 /* When ImmExt is set, the immdiate byte is the last
5129 operand. */
5130 imm = i.operands - 1;
5131 source--;
5132 reg--;
5133 }
5134 else
5135 {
5136 imm = 0;
5137
5138 /* Turn on Imm8 so that output_imm will generate it. */
5139 i.types[imm].bitfield.imm8 = 1;
5140 }
5141
5142 assert (operand_type_equal (&i.tm.operand_types[reg], &regxmm)
5143 || operand_type_equal (&i.tm.operand_types[reg],
5144 &regymm));
5145 i.op[imm].imms->X_add_number
5146 |= ((i.op[reg].regs->reg_num
5147 + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
5148 }
dae39acc
L		 5149
5150 assert (operand_type_equal (&i.tm.operand_types[nds], &regxmm)
5151 || operand_type_equal (&i.tm.operand_types[nds], &regymm));
5152 i.vex.register_specifier = i.op[nds].regs;
5153
c0f3af97
L		 5154 }
5155 else
5156 source = dest = 0;
29b0f896 5157
85f10a01
MM		 5158 /* SSE5 4 operand instructions are encoded in such a way that one of
5159 the inputs must match the destination register. Process_drex hides
5160 the 3rd argument in the drex field, so that by the time we get
5161 here, it looks to GAS as if this is a 2 operand instruction. */
5162 if ((i.tm.opcode_modifier.drex
5163 || i.tm.opcode_modifier.drexv
b5016f89 5164 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5165 && i.reg_operands == 2)
5166 {
5167 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5168 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5169
5170 i.rm.reg = reg->reg_num;
5171 i.rm.regmem = regmem->reg_num;
5172 i.rm.mode = 3;
5173 if ((reg->reg_flags & RegRex) != 0)
5174 i.rex |= REX_R;
5175 if ((regmem->reg_flags & RegRex) != 0)
5176 i.rex |= REX_B;
5177 }
5178
29b0f896 5179 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5180 implicit registers do not count. If there are 3 register
5181 operands, it must be a instruction with VexNDS. For a
5182 instruction with VexNDD, the destination register is encoded
5183 in VEX prefix. If there are 4 register operands, it must be
5184 a instruction with VEX prefix and 3 sources. */
5185 else if (i.mem_operands == 0
5186 && ((i.reg_operands == 2
5187 && !i.tm.opcode_modifier.vexndd)
5188 || (i.reg_operands == 3
5189 && i.tm.opcode_modifier.vexnds)
5190 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5191 {
cab737b9
L		 5192 switch (i.operands)
5193 {
5194 case 2:
5195 source = 0;
5196 break;
5197 case 3:
c81128dc
L		 5198 /* When there are 3 operands, one of them may be immediate,
5199 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5200 the first operand must be shift count register (cl) or it
5201 is an instruction with VexNDS. */
c81128dc
L		 5202 assert (i.imm_operands == 1
5203 || (i.imm_operands == 0
c0f3af97
L		 5204 && (i.tm.opcode_modifier.vexnds
5205 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5206 if (operand_type_check (i.types[0], imm)
5207 || i.types[0].bitfield.shiftcount)
5208 source = 1;
5209 else
5210 source = 0;
cab737b9
L		 5211 break;
5212 case 4:
368d64cc
L		 5213 /* When there are 4 operands, the first two must be 8bit
5214 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5215 one.
5216
5217 For instructions with VexNDS, if the first operand
5218 an imm8, the source operand is the 2nd one. If the last
5219 operand is imm8, the source operand is the first one. */
5220 assert ((i.imm_operands == 2
5221 && i.types[0].bitfield.imm8
5222 && i.types[1].bitfield.imm8)
5223 || (i.tm.opcode_modifier.vexnds
5224 && i.imm_operands == 1
5225 && (i.types[0].bitfield.imm8
5226 || i.types[i.operands - 1].bitfield.imm8)));
5227 if (i.tm.opcode_modifier.vexnds)
5228 {
5229 if (i.types[0].bitfield.imm8)
5230 source = 1;
5231 else
5232 source = 0;
5233 }
5234 else
5235 source = 2;
5236 break;
5237 case 5:
cab737b9
L		 5238 break;
5239 default:
5240 abort ();
5241 }
5242
c0f3af97
L		 5243 if (!vex_3_sources)
5244 {
5245 dest = source + 1;
5246
5247 if (i.tm.opcode_modifier.vexnds)
5248 {
5249 /* For instructions with VexNDS, the register-only
5250 source operand must be XMM or YMM register. It is
5251 encoded in VEX prefix. */
5252 if ((dest + 1) >= i.operands
5253 || (!operand_type_equal (&i.tm.operand_types[dest],
5254 &regxmm)
5255 && !operand_type_equal (&i.tm.operand_types[dest],
5256 &regymm)))
5257 abort ();
5258 i.vex.register_specifier = i.op[dest].regs;
5259 dest++;
5260 }
5261 }
29b0f896
AM		 5262
5263 i.rm.mode = 3;
5264 /* One of the register operands will be encoded in the i.tm.reg
5265 field, the other in the combined i.tm.mode and i.tm.regmem
5266 fields. If no form of this instruction supports a memory
5267 destination operand, then we assume the source operand may
5268 sometimes be a memory operand and so we need to store the
5269 destination in the i.rm.reg field. */
40fb9820
L		 5270 if (!i.tm.operand_types[dest].bitfield.regmem
5271 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5272 {
5273 i.rm.reg = i.op[dest].regs->reg_num;
5274 i.rm.regmem = i.op[source].regs->reg_num;
5275 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5276 i.rex |= REX_R;
29b0f896 5277 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5278 i.rex |= REX_B;
29b0f896
AM		 5279 }
5280 else
5281 {
5282 i.rm.reg = i.op[source].regs->reg_num;
5283 i.rm.regmem = i.op[dest].regs->reg_num;
5284 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5285 i.rex |= REX_B;
29b0f896 5286 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5287 i.rex |= REX_R;
29b0f896 5288 }
161a04f6 5289 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5290 {
40fb9820
L		 5291 if (!i.types[0].bitfield.control
5292 && !i.types[1].bitfield.control)
c4a530c5 5293 abort ();
161a04f6 5294 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5295 add_prefix (LOCK_PREFIX_OPCODE);
5296 }
29b0f896
AM		 5297 }
5298 else
5299 { /* If it's not 2 reg operands... */
c0f3af97
L		 5300 unsigned int mem;
5301
29b0f896
AM		 5302 if (i.mem_operands)
5303 {
5304 unsigned int fake_zero_displacement = 0;
99018f42 5305 unsigned int op;
4eed87de 5306
85f10a01
MM		 5307 /* This has been precalculated for SSE5 instructions
5308 that have a DREX field earlier in process_drex. */
b5016f89
L		 5309 if (i.tm.opcode_modifier.drex
5310 || i.tm.opcode_modifier.drexv
5311 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5312 op = i.drex.modrm_regmem;
5313 else
5314 {
c0209578
L		 5315 for (op = 0; op < i.operands; op++)
5316 if (operand_type_check (i.types[op], anymem))
5317 break;
5318 assert (op < i.operands);
85f10a01 5319 }
29b0f896
AM		 5320
5321 default_seg = &ds;
5322
5323 if (i.base_reg == 0)
5324 {
5325 i.rm.mode = 0;
5326 if (!i.disp_operands)
5327 fake_zero_displacement = 1;
5328 if (i.index_reg == 0)
5329 {
5330 /* Operand is just <disp> */
20f0a1fc 5331 if (flag_code == CODE_64BIT)
29b0f896
AM		 5332 {
5333 /* 64bit mode overwrites the 32bit absolute
5334 addressing by RIP relative addressing and
5335 absolute addressing is encoded by one of the
5336 redundant SIB forms. */
5337 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5338 i.sib.base = NO_BASE_REGISTER;
5339 i.sib.index = NO_INDEX_REGISTER;
fc225355 5340 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5341 ? disp32s : disp32);
20f0a1fc 5342 }
fc225355
L		 5343 else if ((flag_code == CODE_16BIT)
5344 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5345 {
5346 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5347 i.types[op] = disp16;
20f0a1fc
NC		 5348 }
5349 else
5350 {
5351 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5352 i.types[op] = disp32;
29b0f896
AM		 5353 }
5354 }
5355 else /* !i.base_reg && i.index_reg */
5356 {
db51cc60
L		 5357 if (i.index_reg->reg_num == RegEiz
5358 || i.index_reg->reg_num == RegRiz)
5359 i.sib.index = NO_INDEX_REGISTER;
5360 else
5361 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5362 i.sib.base = NO_BASE_REGISTER;
5363 i.sib.scale = i.log2_scale_factor;
5364 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5365 i.types[op].bitfield.disp8 = 0;
5366 i.types[op].bitfield.disp16 = 0;
5367 i.types[op].bitfield.disp64 = 0;
29b0f896 5368 if (flag_code != CODE_64BIT)
40fb9820
L		 5369 {
5370 /* Must be 32 bit */
5371 i.types[op].bitfield.disp32 = 1;
5372 i.types[op].bitfield.disp32s = 0;
5373 }
29b0f896 5374 else
40fb9820
L		 5375 {
5376 i.types[op].bitfield.disp32 = 0;
5377 i.types[op].bitfield.disp32s = 1;
5378 }
29b0f896 5379 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5380 i.rex |= REX_X;
29b0f896
AM		 5381 }
5382 }
5383 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5384 else if (i.base_reg->reg_num == RegRip ||
5385 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5386 {
5387 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5388 i.types[op].bitfield.disp8 = 0;
5389 i.types[op].bitfield.disp16 = 0;
5390 i.types[op].bitfield.disp32 = 0;
5391 i.types[op].bitfield.disp32s = 1;
5392 i.types[op].bitfield.disp64 = 0;
71903a11 5393 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5394 if (! i.disp_operands)
5395 fake_zero_displacement = 1;
29b0f896 5396 }
40fb9820 5397 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5398 {
5399 switch (i.base_reg->reg_num)
5400 {
5401 case 3: /* (%bx) */
5402 if (i.index_reg == 0)
5403 i.rm.regmem = 7;
5404 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5405 i.rm.regmem = i.index_reg->reg_num - 6;
5406 break;
5407 case 5: /* (%bp) */
5408 default_seg = &ss;
5409 if (i.index_reg == 0)
5410 {
5411 i.rm.regmem = 6;
40fb9820 5412 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5413 {
5414 /* fake (%bp) into 0(%bp) */
40fb9820 5415 i.types[op].bitfield.disp8 = 1;
252b5132 5416 fake_zero_displacement = 1;
29b0f896
AM		 5417 }
5418 }
5419 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5420 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5421 break;
5422 default: /* (%si) -> 4 or (%di) -> 5 */
5423 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5424 }
5425 i.rm.mode = mode_from_disp_size (i.types[op]);
5426 }
5427 else /* i.base_reg and 32/64 bit mode */
5428 {
5429 if (flag_code == CODE_64BIT
40fb9820
L		 5430 && operand_type_check (i.types[op], disp))
5431 {
5432 i386_operand_type temp;
0dfbf9d7 5433 operand_type_set (&temp, 0);
40fb9820
L		 5434 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5435 i.types[op] = temp;
5436 if (i.prefix[ADDR_PREFIX] == 0)
5437 i.types[op].bitfield.disp32s = 1;
5438 else
5439 i.types[op].bitfield.disp32 = 1;
5440 }
20f0a1fc 5441
29b0f896
AM		 5442 i.rm.regmem = i.base_reg->reg_num;
5443 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5444 i.rex |= REX_B;
29b0f896
AM		 5445 i.sib.base = i.base_reg->reg_num;
5446 /* x86-64 ignores REX prefix bit here to avoid decoder
5447 complications. */
5448 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5449 {
5450 default_seg = &ss;
5451 if (i.disp_operands == 0)
5452 {
5453 fake_zero_displacement = 1;
40fb9820 5454 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5455 }
5456 }
5457 else if (i.base_reg->reg_num == ESP_REG_NUM)
5458 {
5459 default_seg = &ss;
5460 }
5461 i.sib.scale = i.log2_scale_factor;
5462 if (i.index_reg == 0)
5463 {
5464 /* <disp>(%esp) becomes two byte modrm with no index
5465 register. We've already stored the code for esp
5466 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5467 Any base register besides %esp will not use the
5468 extra modrm byte. */
5469 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5470 }
5471 else
5472 {
db51cc60
L		 5473 if (i.index_reg->reg_num == RegEiz
5474 || i.index_reg->reg_num == RegRiz)
5475 i.sib.index = NO_INDEX_REGISTER;
5476 else
5477 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5478 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5479 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5480 i.rex |= REX_X;
29b0f896 5481 }
67a4f2b7
AO		 5482
5483 if (i.disp_operands
5484 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5485 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5486 i.rm.mode = 0;
5487 else
5488 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5489 }
252b5132 5490
29b0f896
AM		 5491 if (fake_zero_displacement)
5492 {
5493 /* Fakes a zero displacement assuming that i.types[op]
5494 holds the correct displacement size. */
5495 expressionS *exp;
5496
5497 assert (i.op[op].disps == 0);
5498 exp = &disp_expressions[i.disp_operands++];
5499 i.op[op].disps = exp;
5500 exp->X_op = O_constant;
5501 exp->X_add_number = 0;
5502 exp->X_add_symbol = (symbolS *) 0;
5503 exp->X_op_symbol = (symbolS *) 0;
5504 }
c0f3af97
L		 5505
5506 mem = op;
29b0f896 5507 }
c0f3af97
L		 5508 else
5509 mem = ~0;
252b5132 5510
29b0f896
AM		 5511 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5512 (if any) based on i.tm.extension_opcode. Again, we must be
5513 careful to make sure that segment/control/debug/test/MMX
5514 registers are coded into the i.rm.reg field. */
5515 if (i.reg_operands)
5516 {
99018f42
L		 5517 unsigned int op;
5518
85f10a01
MM		 5519 /* This has been precalculated for SSE5 instructions
5520 that have a DREX field earlier in process_drex. */
b5016f89
L		 5521 if (i.tm.opcode_modifier.drex
5522 || i.tm.opcode_modifier.drexv
5523 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5524 {
5525 op = i.drex.modrm_reg;
5526 i.rm.reg = i.op[op].regs->reg_num;
5527 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5528 i.rex |= REX_R;
5529 }
5530 else
5531 {
c0f3af97
L		 5532 unsigned int vex_reg = ~0;
5533
c0209578
L		 5534 for (op = 0; op < i.operands; op++)
5535 if (i.types[op].bitfield.reg8
5536 || i.types[op].bitfield.reg16
5537 || i.types[op].bitfield.reg32
5538 || i.types[op].bitfield.reg64
5539 || i.types[op].bitfield.regmmx
5540 || i.types[op].bitfield.regxmm
c0f3af97 5541 || i.types[op].bitfield.regymm
c0209578
L		 5542 || i.types[op].bitfield.sreg2
5543 || i.types[op].bitfield.sreg3
5544 || i.types[op].bitfield.control
5545 || i.types[op].bitfield.debug
5546 || i.types[op].bitfield.test)
5547 break;
5548
c0f3af97
L		 5549 if (vex_3_sources)
5550 op = dest;
5551 else if (i.tm.opcode_modifier.vexnds)
5552 {
5553 /* For instructions with VexNDS, the register-only
5554 source operand is encoded in VEX prefix. */
5555 assert (mem != (unsigned int) ~0);
5556
5557 if (op > mem)
5558 {
5559 vex_reg = op++;
5560 assert (op < i.operands);
5561 }
5562 else
5563 {
5564 vex_reg = op + 1;
5565 assert (vex_reg < i.operands);
5566 }
5567 }
5568 else if (i.tm.opcode_modifier.vexndd)
5569 {
5570 /* For instructions with VexNDD, there should be
5571 no memory operand and the register destination
5572 is encoded in VEX prefix. */
5573 assert (i.mem_operands == 0
5574 && (op + 2) == i.operands);
5575 vex_reg = op + 1;
5576 }
5577 else
5578 assert (op < i.operands);
5579
5580 if (vex_reg != (unsigned int) ~0)
5581 {
5582 assert (i.reg_operands == 2);
5583
5584 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5585 & regxmm)
5586 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5587 &regymm))
5588 abort ();
5589 i.vex.register_specifier = i.op[vex_reg].regs;
5590 }
99018f42 5591
85f10a01
MM		 5592 /* If there is an extension opcode to put here, the
5593 register number must be put into the regmem field. */
c0209578
L		 5594 if (i.tm.extension_opcode != None)
5595 {
5596 i.rm.regmem = i.op[op].regs->reg_num;
5597 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5598 i.rex |= REX_B;
5599 }
5600 else
5601 {
5602 i.rm.reg = i.op[op].regs->reg_num;
5603 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5604 i.rex |= REX_R;
5605 }
85f10a01 5606 }
252b5132 5607
29b0f896
AM		 5608 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5609 must set it to 3 to indicate this is a register operand
5610 in the regmem field. */
5611 if (!i.mem_operands)
5612 i.rm.mode = 3;
5613 }
252b5132 5614
29b0f896 5615 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5616 if (i.tm.extension_opcode != None
5617 && !(i.tm.opcode_modifier.drex
5618 || i.tm.opcode_modifier.drexv
5619 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5620 i.rm.reg = i.tm.extension_opcode;
5621 }
5622 return default_seg;
5623}
252b5132 5624
29b0f896 5625static void
e3bb37b5 5626output_branch (void)
29b0f896
AM		 5627{
5628 char *p;
5629 int code16;
5630 int prefix;
5631 relax_substateT subtype;
5632 symbolS *sym;
5633 offsetT off;
5634
5635 code16 = 0;
5636 if (flag_code == CODE_16BIT)
5637 code16 = CODE16;
5638
5639 prefix = 0;
5640 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5641 {
29b0f896
AM		 5642 prefix = 1;
5643 i.prefixes -= 1;
5644 code16 ^= CODE16;
252b5132 5645 }
29b0f896
AM		 5646 /* Pentium4 branch hints. */
5647 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5648 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5649 {
29b0f896
AM		 5650 prefix++;
5651 i.prefixes--;
5652 }
5653 if (i.prefix[REX_PREFIX] != 0)
5654 {
5655 prefix++;
5656 i.prefixes--;
2f66722d
AM		 5657 }
5658
29b0f896
AM		 5659 if (i.prefixes != 0 && !intel_syntax)
5660 as_warn (_("skipping prefixes on this instruction"));
5661
5662 /* It's always a symbol; End frag & setup for relax.
5663 Make sure there is enough room in this frag for the largest
5664 instruction we may generate in md_convert_frag. This is 2
5665 bytes for the opcode and room for the prefix and largest
5666 displacement. */
5667 frag_grow (prefix + 2 + 4);
5668 /* Prefix and 1 opcode byte go in fr_fix. */
5669 p = frag_more (prefix + 1);
5670 if (i.prefix[DATA_PREFIX] != 0)
5671 *p++ = DATA_PREFIX_OPCODE;
5672 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5673 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5674 *p++ = i.prefix[SEG_PREFIX];
5675 if (i.prefix[REX_PREFIX] != 0)
5676 *p++ = i.prefix[REX_PREFIX];
5677 *p = i.tm.base_opcode;
5678
5679 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5680 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5681 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5682 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5683 else
5684 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5685 subtype |= code16;
3e73aa7c 5686
29b0f896
AM		 5687 sym = i.op[0].disps->X_add_symbol;
5688 off = i.op[0].disps->X_add_number;
3e73aa7c 5689
29b0f896
AM		 5690 if (i.op[0].disps->X_op != O_constant
5691 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5692 {
29b0f896
AM		 5693 /* Handle complex expressions. */
5694 sym = make_expr_symbol (i.op[0].disps);
5695 off = 0;
5696 }
3e73aa7c 5697
29b0f896
AM		 5698 /* 1 possible extra opcode + 4 byte displacement go in var part.
5699 Pass reloc in fr_var. */
5700 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5701}
3e73aa7c 5702
29b0f896 5703static void
e3bb37b5 5704output_jump (void)
29b0f896
AM		 5705{
5706 char *p;
5707 int size;
3e02c1cc 5708 fixS *fixP;
29b0f896 5709
40fb9820 5710 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5711 {
5712 /* This is a loop or jecxz type instruction. */
5713 size = 1;
5714 if (i.prefix[ADDR_PREFIX] != 0)
5715 {
5716 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5717 i.prefixes -= 1;
5718 }
5719 /* Pentium4 branch hints. */
5720 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5721 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5722 {
5723 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5724 i.prefixes--;
3e73aa7c
JH		 5725 }
5726 }
29b0f896
AM		 5727 else
5728 {
5729 int code16;
3e73aa7c 5730
29b0f896
AM		 5731 code16 = 0;
5732 if (flag_code == CODE_16BIT)
5733 code16 = CODE16;
3e73aa7c 5734
29b0f896
AM		 5735 if (i.prefix[DATA_PREFIX] != 0)
5736 {
5737 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5738 i.prefixes -= 1;
5739 code16 ^= CODE16;
5740 }
252b5132 5741
29b0f896
AM		 5742 size = 4;
5743 if (code16)
5744 size = 2;
5745 }
9fcc94b6 5746
29b0f896
AM		 5747 if (i.prefix[REX_PREFIX] != 0)
5748 {
5749 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5750 i.prefixes -= 1;
5751 }
252b5132 5752
29b0f896
AM		 5753 if (i.prefixes != 0 && !intel_syntax)
5754 as_warn (_("skipping prefixes on this instruction"));
e0890092 5755
29b0f896
AM		 5756 p = frag_more (1 + size);
5757 *p++ = i.tm.base_opcode;
e0890092 5758
3e02c1cc
AM		 5759 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5760 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5761
5762 /* All jumps handled here are signed, but don't use a signed limit
5763 check for 32 and 16 bit jumps as we want to allow wrap around at
5764 4G and 64k respectively. */
5765 if (size == 1)
5766 fixP->fx_signed = 1;
29b0f896 5767}
e0890092 5768
29b0f896 5769static void
e3bb37b5 5770output_interseg_jump (void)
29b0f896
AM		 5771{
5772 char *p;
5773 int size;
5774 int prefix;
5775 int code16;
252b5132 5776
29b0f896
AM		 5777 code16 = 0;
5778 if (flag_code == CODE_16BIT)
5779 code16 = CODE16;
a217f122 5780
29b0f896
AM		 5781 prefix = 0;
5782 if (i.prefix[DATA_PREFIX] != 0)
5783 {
5784 prefix = 1;
5785 i.prefixes -= 1;
5786 code16 ^= CODE16;
5787 }
5788 if (i.prefix[REX_PREFIX] != 0)
5789 {
5790 prefix++;
5791 i.prefixes -= 1;
5792 }
252b5132 5793
29b0f896
AM		 5794 size = 4;
5795 if (code16)
5796 size = 2;
252b5132 5797
29b0f896
AM		 5798 if (i.prefixes != 0 && !intel_syntax)
5799 as_warn (_("skipping prefixes on this instruction"));
252b5132 5800
29b0f896
AM		 5801 /* 1 opcode; 2 segment; offset */
5802 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5803
29b0f896
AM		 5804 if (i.prefix[DATA_PREFIX] != 0)
5805 *p++ = DATA_PREFIX_OPCODE;
252b5132 5806
29b0f896
AM		 5807 if (i.prefix[REX_PREFIX] != 0)
5808 *p++ = i.prefix[REX_PREFIX];
252b5132 5809
29b0f896
AM		 5810 *p++ = i.tm.base_opcode;
5811 if (i.op[1].imms->X_op == O_constant)
5812 {
5813 offsetT n = i.op[1].imms->X_add_number;
252b5132 5814
29b0f896
AM		 5815 if (size == 2
5816 && !fits_in_unsigned_word (n)
5817 && !fits_in_signed_word (n))
5818 {
5819 as_bad (_("16-bit jump out of range"));
5820 return;
5821 }
5822 md_number_to_chars (p, n, size);
5823 }
5824 else
5825 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5826 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5827 if (i.op[0].imms->X_op != O_constant)
5828 as_bad (_("can't handle non absolute segment in `%s'"),
5829 i.tm.name);
5830 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5831}
a217f122 5832
29b0f896 5833static void
e3bb37b5 5834output_insn (void)
29b0f896 5835{
2bbd9c25
JJ		 5836 fragS *insn_start_frag;
5837 offsetT insn_start_off;
5838
29b0f896
AM		 5839 /* Tie dwarf2 debug info to the address at the start of the insn.
5840 We can't do this after the insn has been output as the current
5841 frag may have been closed off. eg. by frag_var. */
5842 dwarf2_emit_insn (0);
5843
2bbd9c25
JJ		 5844 insn_start_frag = frag_now;
5845 insn_start_off = frag_now_fix ();
5846
29b0f896 5847 /* Output jumps. */
40fb9820 5848 if (i.tm.opcode_modifier.jump)
29b0f896 5849 output_branch ();
40fb9820
L		 5850 else if (i.tm.opcode_modifier.jumpbyte
5851 || i.tm.opcode_modifier.jumpdword)
29b0f896 5852 output_jump ();
40fb9820 5853 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5854 output_interseg_jump ();
5855 else
5856 {
5857 /* Output normal instructions here. */
5858 char *p;
5859 unsigned char *q;
47465058 5860 unsigned int j;
331d2d0d 5861 unsigned int prefix;
4dffcebc 5862
c0f3af97
L		 5863 /* Since the VEX prefix contains the implicit prefix, we don't
5864 need the explicit prefix. */
5865 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5866 {
c0f3af97 5867 switch (i.tm.opcode_length)
bc4bd9ab 5868 {
c0f3af97
L		 5869 case 3:
5870 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5871 {
c0f3af97
L		 5872 prefix = (i.tm.base_opcode >> 24) & 0xff;
5873 goto check_prefix;
5874 }
5875 break;
5876 case 2:
5877 if ((i.tm.base_opcode & 0xff0000) != 0)
5878 {
5879 prefix = (i.tm.base_opcode >> 16) & 0xff;
5880 if (i.tm.cpu_flags.bitfield.cpupadlock)
5881 {
4dffcebc 5882check_prefix:
c0f3af97
L		 5883 if (prefix != REPE_PREFIX_OPCODE
5884 || (i.prefix[LOCKREP_PREFIX]
5885 != REPE_PREFIX_OPCODE))
5886 add_prefix (prefix);
5887 }
5888 else
4dffcebc
L		 5889 add_prefix (prefix);
5890 }
c0f3af97
L		 5891 break;
5892 case 1:
5893 break;
5894 default:
5895 abort ();
bc4bd9ab 5896 }
c0f3af97
L		 5897
5898 /* The prefix bytes. */
5899 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5900 if (*q)
5901 FRAG_APPEND_1_CHAR (*q);
0f10071e 5902 }
252b5132 5903
c0f3af97
L		 5904 if (i.tm.opcode_modifier.vex)
5905 {
5906 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5907 if (*q)
5908 switch (j)
5909 {
5910 case REX_PREFIX:
5911 /* REX byte is encoded in VEX prefix. */
5912 break;
5913 case SEG_PREFIX:
5914 case ADDR_PREFIX:
5915 FRAG_APPEND_1_CHAR (*q);
5916 break;
5917 default:
5918 /* There should be no other prefixes for instructions
5919 with VEX prefix. */
5920 abort ();
5921 }
5922
5923 /* Now the VEX prefix. */
5924 p = frag_more (i.vex.length);
5925 for (j = 0; j < i.vex.length; j++)
5926 p[j] = i.vex.bytes[j];
5927 }
252b5132 5928
29b0f896 5929 /* Now the opcode; be careful about word order here! */
4dffcebc 5930 if (i.tm.opcode_length == 1)
29b0f896
AM		 5931 {
5932 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5933 }
5934 else
5935 {
4dffcebc 5936 switch (i.tm.opcode_length)
331d2d0d 5937 {
4dffcebc 5938 case 3:
331d2d0d
L		 5939 p = frag_more (3);
5940 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5941 break;
5942 case 2:
5943 p = frag_more (2);
5944 break;
5945 default:
5946 abort ();
5947 break;
331d2d0d 5948 }
0f10071e 5949
29b0f896
AM		 5950 /* Put out high byte first: can't use md_number_to_chars! */
5951 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5952 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5953
5954 /* On SSE5, encode the OC1 bit in the DREX field if this
5955 encoding has multiple formats. */
5956 if (i.tm.opcode_modifier.drex
5957 && i.tm.opcode_modifier.drexv
5958 && DREX_OC1 (i.tm.extension_opcode))
5959 *p |= DREX_OC1_MASK;
29b0f896 5960 }
3e73aa7c 5961
29b0f896 5962 /* Now the modrm byte and sib byte (if present). */
40fb9820 5963 if (i.tm.opcode_modifier.modrm)
29b0f896 5964 {
4a3523fa
L		 5965 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5966 | i.rm.reg << 3
5967 | i.rm.mode << 6));
29b0f896
AM		 5968 /* If i.rm.regmem == ESP (4)
5969 && i.rm.mode != (Register mode)
5970 && not 16 bit
5971 ==> need second modrm byte. */
5972 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5973 && i.rm.mode != 3
40fb9820 5974 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5975 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5976 | i.sib.index << 3
5977 | i.sib.scale << 6));
29b0f896 5978 }
3e73aa7c 5979
85f10a01
MM		 5980 /* Write the DREX byte if needed. */
5981 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5982 {
5983 p = frag_more (1);
5984 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5985
5986 /* Encode the OC0 bit if this encoding has multiple
5987 formats. */
5988 if ((i.tm.opcode_modifier.drex
5989 || i.tm.opcode_modifier.drexv)
5990 && DREX_OC0 (i.tm.extension_opcode))
5991 *p |= DREX_OC0_MASK;
5992 }
5993
29b0f896 5994 if (i.disp_operands)
2bbd9c25 5995 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5996
29b0f896 5997 if (i.imm_operands)
2bbd9c25 5998 output_imm (insn_start_frag, insn_start_off);
29b0f896 5999 }
252b5132 6000
29b0f896
AM		 6001#ifdef DEBUG386
6002 if (flag_debug)
6003 {
7b81dfbb 6004 pi ("" /*line*/, &i);
29b0f896
AM		 6005 }
6006#endif /* DEBUG386 */
6007}
252b5132 6008
e205caa7
L		 6009/* Return the size of the displacement operand N. */
6010
6011static int
6012disp_size (unsigned int n)
6013{
6014 int size = 4;
40fb9820
L		 6015 if (i.types[n].bitfield.disp64)
6016 size = 8;
6017 else if (i.types[n].bitfield.disp8)
6018 size = 1;
6019 else if (i.types[n].bitfield.disp16)
6020 size = 2;
e205caa7
L		 6021 return size;
6022}
6023
6024/* Return the size of the immediate operand N. */
6025
6026static int
6027imm_size (unsigned int n)
6028{
6029 int size = 4;
40fb9820
L		 6030 if (i.types[n].bitfield.imm64)
6031 size = 8;
6032 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6033 size = 1;
6034 else if (i.types[n].bitfield.imm16)
6035 size = 2;
e205caa7
L		 6036 return size;
6037}
6038
29b0f896 6039static void
64e74474 6040output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6041{
6042 char *p;
6043 unsigned int n;
252b5132 6044
29b0f896
AM		 6045 for (n = 0; n < i.operands; n++)
6046 {
40fb9820 6047 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6048 {
6049 if (i.op[n].disps->X_op == O_constant)
6050 {
e205caa7 6051 int size = disp_size (n);
29b0f896 6052 offsetT val;
252b5132 6053
29b0f896
AM		 6054 val = offset_in_range (i.op[n].disps->X_add_number,
6055 size);
6056 p = frag_more (size);
6057 md_number_to_chars (p, val, size);
6058 }
6059 else
6060 {
f86103b7 6061 enum bfd_reloc_code_real reloc_type;
e205caa7 6062 int size = disp_size (n);
40fb9820 6063 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6064 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6065
e205caa7 6066 /* We can't have 8 bit displacement here. */
40fb9820 6067 assert (!i.types[n].bitfield.disp8);
e205caa7 6068
29b0f896
AM		 6069 /* The PC relative address is computed relative
6070 to the instruction boundary, so in case immediate
6071 fields follows, we need to adjust the value. */
6072 if (pcrel && i.imm_operands)
6073 {
29b0f896 6074 unsigned int n1;
e205caa7 6075 int sz = 0;
252b5132 6076
29b0f896 6077 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6078 if (operand_type_check (i.types[n1], imm))
252b5132 6079 {
e205caa7
L		 6080 /* Only one immediate is allowed for PC
6081 relative address. */
6082 assert (sz == 0);
6083 sz = imm_size (n1);
6084 i.op[n].disps->X_add_number -= sz;
252b5132 6085 }
29b0f896 6086 /* We should find the immediate. */
e205caa7 6087 assert (sz != 0);
29b0f896 6088 }
520dc8e8 6089
29b0f896 6090 p = frag_more (size);
2bbd9c25 6091 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6092 if (GOT_symbol
2bbd9c25 6093 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6094 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6095 || reloc_type == BFD_RELOC_X86_64_32S
6096 || (reloc_type == BFD_RELOC_64
6097 && object_64bit))
d6ab8113
JB		 6098 && (i.op[n].disps->X_op == O_symbol
6099 || (i.op[n].disps->X_op == O_add
6100 && ((symbol_get_value_expression
6101 (i.op[n].disps->X_op_symbol)->X_op)
6102 == O_subtract))))
6103 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6104 {
6105 offsetT add;
6106
6107 if (insn_start_frag == frag_now)
6108 add = (p - frag_now->fr_literal) - insn_start_off;
6109 else
6110 {
6111 fragS *fr;
6112
6113 add = insn_start_frag->fr_fix - insn_start_off;
6114 for (fr = insn_start_frag->fr_next;
6115 fr && fr != frag_now; fr = fr->fr_next)
6116 add += fr->fr_fix;
6117 add += p - frag_now->fr_literal;
6118 }
6119
4fa24527 6120 if (!object_64bit)
7b81dfbb
AJ		 6121 {
6122 reloc_type = BFD_RELOC_386_GOTPC;
6123 i.op[n].imms->X_add_number += add;
6124 }
6125 else if (reloc_type == BFD_RELOC_64)
6126 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6127 else
7b81dfbb
AJ		 6128 /* Don't do the adjustment for x86-64, as there
6129 the pcrel addressing is relative to the _next_
6130 insn, and that is taken care of in other code. */
d6ab8113 6131 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6132 }
062cd5e7 6133 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6134 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6135 }
6136 }
6137 }
6138}
252b5132 6139
29b0f896 6140static void
64e74474 6141output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6142{
6143 char *p;
6144 unsigned int n;
252b5132 6145
29b0f896
AM		 6146 for (n = 0; n < i.operands; n++)
6147 {
40fb9820 6148 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6149 {
6150 if (i.op[n].imms->X_op == O_constant)
6151 {
e205caa7 6152 int size = imm_size (n);
29b0f896 6153 offsetT val;
b4cac588 6154
29b0f896
AM		 6155 val = offset_in_range (i.op[n].imms->X_add_number,
6156 size);
6157 p = frag_more (size);
6158 md_number_to_chars (p, val, size);
6159 }
6160 else
6161 {
6162 /* Not absolute_section.
6163 Need a 32-bit fixup (don't support 8bit
6164 non-absolute imms). Try to support other
6165 sizes ... */
f86103b7 6166 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6167 int size = imm_size (n);
6168 int sign;
29b0f896 6169
40fb9820 6170 if (i.types[n].bitfield.imm32s
a7d61044 6171 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6172 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6173 sign = 1;
e205caa7
L		 6174 else
6175 sign = 0;
520dc8e8 6176
29b0f896
AM		 6177 p = frag_more (size);
6178 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6179
2bbd9c25
JJ		 6180 /* This is tough to explain. We end up with this one if we
6181 * have operands that look like
6182 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6183 * obtain the absolute address of the GOT, and it is strongly
6184 * preferable from a performance point of view to avoid using
6185 * a runtime relocation for this. The actual sequence of
6186 * instructions often look something like:
6187 *
6188 * call .L66
6189 * .L66:
6190 * popl %ebx
6191 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6192 *
6193 * The call and pop essentially return the absolute address
6194 * of the label .L66 and store it in %ebx. The linker itself
6195 * will ultimately change the first operand of the addl so
6196 * that %ebx points to the GOT, but to keep things simple, the
6197 * .o file must have this operand set so that it generates not
6198 * the absolute address of .L66, but the absolute address of
6199 * itself. This allows the linker itself simply treat a GOTPC
6200 * relocation as asking for a pcrel offset to the GOT to be
6201 * added in, and the addend of the relocation is stored in the
6202 * operand field for the instruction itself.
6203 *
6204 * Our job here is to fix the operand so that it would add
6205 * the correct offset so that %ebx would point to itself. The
6206 * thing that is tricky is that .-.L66 will point to the
6207 * beginning of the instruction, so we need to further modify
6208 * the operand so that it will point to itself. There are
6209 * other cases where you have something like:
6210 *
6211 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6212 *
6213 * and here no correction would be required. Internally in
6214 * the assembler we treat operands of this form as not being
6215 * pcrel since the '.' is explicitly mentioned, and I wonder
6216 * whether it would simplify matters to do it this way. Who
6217 * knows. In earlier versions of the PIC patches, the
6218 * pcrel_adjust field was used to store the correction, but
6219 * since the expression is not pcrel, I felt it would be
6220 * confusing to do it this way. */
6221
d6ab8113 6222 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6223 || reloc_type == BFD_RELOC_X86_64_32S
6224 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6225 && GOT_symbol
6226 && GOT_symbol == i.op[n].imms->X_add_symbol
6227 && (i.op[n].imms->X_op == O_symbol
6228 || (i.op[n].imms->X_op == O_add
6229 && ((symbol_get_value_expression
6230 (i.op[n].imms->X_op_symbol)->X_op)
6231 == O_subtract))))
6232 {
2bbd9c25
JJ		 6233 offsetT add;
6234
6235 if (insn_start_frag == frag_now)
6236 add = (p - frag_now->fr_literal) - insn_start_off;
6237 else
6238 {
6239 fragS *fr;
6240
6241 add = insn_start_frag->fr_fix - insn_start_off;
6242 for (fr = insn_start_frag->fr_next;
6243 fr && fr != frag_now; fr = fr->fr_next)
6244 add += fr->fr_fix;
6245 add += p - frag_now->fr_literal;
6246 }
6247
4fa24527 6248 if (!object_64bit)
d6ab8113 6249 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6250 else if (size == 4)
d6ab8113 6251 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6252 else if (size == 8)
6253 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6254 i.op[n].imms->X_add_number += add;
29b0f896 6255 }
29b0f896
AM		 6256 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6257 i.op[n].imms, 0, reloc_type);
6258 }
6259 }
6260 }
252b5132
RH		 6261}
6262\f
d182319b
JB		 6263/* x86_cons_fix_new is called via the expression parsing code when a
6264 reloc is needed. We use this hook to get the correct .got reloc. */
6265static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6266static int cons_sign = -1;
6267
6268void
e3bb37b5 6269x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6270 expressionS *exp)
d182319b
JB		 6271{
6272 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6273
6274 got_reloc = NO_RELOC;
6275
6276#ifdef TE_PE
6277 if (exp->X_op == O_secrel)
6278 {
6279 exp->X_op = O_symbol;
6280 r = BFD_RELOC_32_SECREL;
6281 }
6282#endif
6283
6284 fix_new_exp (frag, off, len, exp, 0, r);
6285}
6286
718ddfc0
JB		 6287#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6288# define lex_got(reloc, adjust, types) NULL
6289#else
f3c180ae
AM		 6290/* Parse operands of the form
6291 <symbol>@GOTOFF+<nnn>
6292 and similar .plt or .got references.
6293
6294 If we find one, set up the correct relocation in RELOC and copy the
6295 input string, minus the `@GOTOFF' into a malloc'd buffer for
6296 parsing by the calling routine. Return this buffer, and if ADJUST
6297 is non-null set it to the length of the string we removed from the
6298 input line. Otherwise return NULL. */
6299static char *
3956db08 6300lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6301 int *adjust,
40fb9820 6302 i386_operand_type *types)
f3c180ae 6303{
7b81dfbb
AJ		 6304 /* Some of the relocations depend on the size of what field is to
6305 be relocated. But in our callers i386_immediate and i386_displacement
6306 we don't yet know the operand size (this will be set by insn
6307 matching). Hence we record the word32 relocation here,
6308 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6309 static const struct {
6310 const char *str;
4fa24527 6311 const enum bfd_reloc_code_real rel[2];
40fb9820 6312 const i386_operand_type types64;
f3c180ae 6313 } gotrel[] = {
4eed87de
AM		 6314 { "PLTOFF", { 0,
6315 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6316 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6317 { "PLT", { BFD_RELOC_386_PLT32,
6318 BFD_RELOC_X86_64_PLT32 },
40fb9820 6319 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6320 { "GOTPLT", { 0,
6321 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6322 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6323 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6324 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6325 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6326 { "GOTPCREL", { 0,
6327 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6328 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6329 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6330 BFD_RELOC_X86_64_TLSGD },
40fb9820 6331 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6332 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6333 0 },
40fb9820 6334 OPERAND_TYPE_NONE },
4eed87de
AM		 6335 { "TLSLD", { 0,
6336 BFD_RELOC_X86_64_TLSLD },
40fb9820 6337 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6338 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6339 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6340 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6341 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6342 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6343 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6344 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6345 0 },
40fb9820 6346 OPERAND_TYPE_NONE },
4eed87de
AM		 6347 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6348 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6349
6350 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6351 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6352 0 },
40fb9820 6353 OPERAND_TYPE_NONE },
4eed87de
AM		 6354 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6355 0 },
40fb9820 6356 OPERAND_TYPE_NONE },
4eed87de
AM		 6357 { "GOT", { BFD_RELOC_386_GOT32,
6358 BFD_RELOC_X86_64_GOT32 },
40fb9820 6359 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6360 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6361 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6362 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6363 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6364 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6365 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6366 };
6367 char *cp;
6368 unsigned int j;
6369
718ddfc0
JB		 6370 if (!IS_ELF)
6371 return NULL;
6372
f3c180ae 6373 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6374 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6375 return NULL;
6376
47465058 6377 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6378 {
6379 int len;
6380
6381 len = strlen (gotrel[j].str);
28f81592 6382 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6383 {
4fa24527 6384 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6385 {
28f81592
AM		 6386 int first, second;
6387 char *tmpbuf, *past_reloc;
f3c180ae 6388
4fa24527 6389 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6390 if (adjust)
6391 *adjust = len;
f3c180ae 6392
3956db08
JB		 6393 if (types)
6394 {
6395 if (flag_code != CODE_64BIT)
40fb9820
L		 6396 {
6397 types->bitfield.imm32 = 1;
6398 types->bitfield.disp32 = 1;
6399 }
3956db08
JB		 6400 else
6401 *types = gotrel[j].types64;
6402 }
6403
f3c180ae
AM		 6404 if (GOT_symbol == NULL)
6405 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6406
28f81592 6407 /* The length of the first part of our input line. */
f3c180ae 6408 first = cp - input_line_pointer;
28f81592
AM		 6409
6410 /* The second part goes from after the reloc token until
67c11a9b 6411 (and including) an end_of_line char or comma. */
28f81592 6412 past_reloc = cp + 1 + len;
67c11a9b
AM		 6413 cp = past_reloc;
6414 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6415 ++cp;
6416 second = cp + 1 - past_reloc;
28f81592
AM		 6417
6418 /* Allocate and copy string. The trailing NUL shouldn't
6419 be necessary, but be safe. */
6420 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6421 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6422 if (second != 0 && *past_reloc != ' ')
6423 /* Replace the relocation token with ' ', so that
6424 errors like foo@GOTOFF1 will be detected. */
6425 tmpbuf[first++] = ' ';
6426 memcpy (tmpbuf + first, past_reloc, second);
6427 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6428 return tmpbuf;
6429 }
6430
4fa24527
JB		 6431 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6432 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6433 return NULL;
6434 }
6435 }
6436
6437 /* Might be a symbol version string. Don't as_bad here. */
6438 return NULL;
6439}
6440
f3c180ae 6441void
e3bb37b5 6442x86_cons (expressionS *exp, int size)
f3c180ae 6443{
4fa24527 6444 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6445 {
6446 /* Handle @GOTOFF and the like in an expression. */
6447 char *save;
6448 char *gotfree_input_line;
6449 int adjust;
6450
6451 save = input_line_pointer;
3956db08 6452 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6453 if (gotfree_input_line)
6454 input_line_pointer = gotfree_input_line;
6455
6456 expression (exp);
6457
6458 if (gotfree_input_line)
6459 {
6460 /* expression () has merrily parsed up to the end of line,
6461 or a comma - in the wrong buffer. Transfer how far
6462 input_line_pointer has moved to the right buffer. */
6463 input_line_pointer = (save
6464 + (input_line_pointer - gotfree_input_line)
6465 + adjust);
6466 free (gotfree_input_line);
3992d3b7
AM		 6467 if (exp->X_op == O_constant
6468 || exp->X_op == O_absent
6469 || exp->X_op == O_illegal
6470 || exp->X_op == O_register
6471 || exp->X_op == O_big)
6472 {
6473 char c = *input_line_pointer;
6474 *input_line_pointer = 0;
6475 as_bad (_("missing or invalid expression `%s'"), save);
6476 *input_line_pointer = c;
6477 }
f3c180ae
AM		 6478 }
6479 }
6480 else
6481 expression (exp);
6482}
6483#endif
6484
d182319b 6485static void signed_cons (int size)
6482c264 6486{
d182319b
JB		 6487 if (flag_code == CODE_64BIT)
6488 cons_sign = 1;
6489 cons (size);
6490 cons_sign = -1;
6482c264
NC		 6491}
6492
d182319b 6493#ifdef TE_PE
6482c264
NC		 6494static void
6495pe_directive_secrel (dummy)
6496 int dummy ATTRIBUTE_UNUSED;
6497{
6498 expressionS exp;
6499
6500 do
6501 {
6502 expression (&exp);
6503 if (exp.X_op == O_symbol)
6504 exp.X_op = O_secrel;
6505
6506 emit_expr (&exp, 4);
6507 }
6508 while (*input_line_pointer++ == ',');
6509
6510 input_line_pointer--;
6511 demand_empty_rest_of_line ();
6512}
6482c264
NC		 6513#endif
6514
252b5132 6515static int
70e41ade 6516i386_immediate (char *imm_start)
252b5132
RH		 6517{
6518 char *save_input_line_pointer;
f3c180ae 6519 char *gotfree_input_line;
252b5132 6520 segT exp_seg = 0;
47926f60 6521 expressionS *exp;
40fb9820
L		 6522 i386_operand_type types;
6523
0dfbf9d7 6524 operand_type_set (&types, ~0);
252b5132
RH		 6525
6526 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6527 {
31b2323c
L		 6528 as_bad (_("at most %d immediate operands are allowed"),
6529 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6530 return 0;
6531 }
6532
6533 exp = &im_expressions[i.imm_operands++];
520dc8e8 6534 i.op[this_operand].imms = exp;
252b5132
RH		 6535
6536 if (is_space_char (*imm_start))
6537 ++imm_start;
6538
6539 save_input_line_pointer = input_line_pointer;
6540 input_line_pointer = imm_start;
6541
3956db08 6542 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6543 if (gotfree_input_line)
6544 input_line_pointer = gotfree_input_line;
252b5132
RH		 6545
6546 exp_seg = expression (exp);
6547
83183c0c 6548 SKIP_WHITESPACE ();
252b5132 6549 if (*input_line_pointer)
f3c180ae 6550 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6551
6552 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6553 if (gotfree_input_line)
6554 free (gotfree_input_line);
252b5132 6555
3992d3b7
AM		 6556 if (exp->X_op == O_absent
6557 || exp->X_op == O_illegal
6558 || exp->X_op == O_big
6559 || (gotfree_input_line
6560 && (exp->X_op == O_constant
6561 || exp->X_op == O_register)))
252b5132 6562 {
3992d3b7 6563 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6564 imm_start);
3992d3b7 6565 return 0;
252b5132 6566 }
3e73aa7c 6567 else if (exp->X_op == O_constant)
252b5132 6568 {
47926f60 6569 /* Size it properly later. */
40fb9820 6570 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6571 /* If BFD64, sign extend val. */
4eed87de
AM		 6572 if (!use_rela_relocations
6573 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6574 exp->X_add_number
6575 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6576 }
4c63da97 6577#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6578 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6579 && exp_seg != absolute_section
47926f60 6580 && exp_seg != text_section
24eab124
AM		 6581 && exp_seg != data_section
6582 && exp_seg != bss_section
6583 && exp_seg != undefined_section
f86103b7 6584 && !bfd_is_com_section (exp_seg))
252b5132 6585 {
d0b47220 6586 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6587 return 0;
6588 }
6589#endif
bb8f5920
L		 6590 else if (!intel_syntax && exp->X_op == O_register)
6591 {
6592 as_bad (_("illegal immediate register operand %s"), imm_start);
6593 return 0;
6594 }
252b5132
RH		 6595 else
6596 {
6597 /* This is an address. The size of the address will be
24eab124 6598 determined later, depending on destination register,
3e73aa7c 6599 suffix, or the default for the section. */
40fb9820
L		 6600 i.types[this_operand].bitfield.imm8 = 1;
6601 i.types[this_operand].bitfield.imm16 = 1;
6602 i.types[this_operand].bitfield.imm32 = 1;
6603 i.types[this_operand].bitfield.imm32s = 1;
6604 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6605 i.types[this_operand] = operand_type_and (i.types[this_operand],
6606 types);
252b5132
RH		 6607 }
6608
6609 return 1;
6610}
6611
551c1ca1 6612static char *
e3bb37b5 6613i386_scale (char *scale)
252b5132 6614{
551c1ca1
AM		 6615 offsetT val;
6616 char *save = input_line_pointer;
252b5132 6617
551c1ca1
AM		 6618 input_line_pointer = scale;
6619 val = get_absolute_expression ();
6620
6621 switch (val)
252b5132 6622 {
551c1ca1 6623 case 1:
252b5132
RH		 6624 i.log2_scale_factor = 0;
6625 break;
551c1ca1 6626 case 2:
252b5132
RH		 6627 i.log2_scale_factor = 1;
6628 break;
551c1ca1 6629 case 4:
252b5132
RH		 6630 i.log2_scale_factor = 2;
6631 break;
551c1ca1 6632 case 8:
252b5132
RH		 6633 i.log2_scale_factor = 3;
6634 break;
6635 default:
a724f0f4
JB		 6636 {
6637 char sep = *input_line_pointer;
6638
6639 *input_line_pointer = '\0';
6640 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6641 scale);
6642 *input_line_pointer = sep;
6643 input_line_pointer = save;
6644 return NULL;
6645 }
252b5132 6646 }
29b0f896 6647 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6648 {
6649 as_warn (_("scale factor of %d without an index register"),
24eab124 6650 1 << i.log2_scale_factor);
252b5132 6651 i.log2_scale_factor = 0;
252b5132 6652 }
551c1ca1
AM		 6653 scale = input_line_pointer;
6654 input_line_pointer = save;
6655 return scale;
252b5132
RH		 6656}
6657
252b5132 6658static int
e3bb37b5 6659i386_displacement (char *disp_start, char *disp_end)
252b5132 6660{
29b0f896 6661 expressionS *exp;
252b5132
RH		 6662 segT exp_seg = 0;
6663 char *save_input_line_pointer;
f3c180ae 6664 char *gotfree_input_line;
40fb9820
L		 6665 int override;
6666 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6667 int ret;
252b5132 6668
31b2323c
L		 6669 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6670 {
6671 as_bad (_("at most %d displacement operands are allowed"),
6672 MAX_MEMORY_OPERANDS);
6673 return 0;
6674 }
6675
0dfbf9d7 6676 operand_type_set (&bigdisp, 0);
40fb9820
L		 6677 if ((i.types[this_operand].bitfield.jumpabsolute)
6678 || (!current_templates->start->opcode_modifier.jump
6679 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6680 {
40fb9820 6681 bigdisp.bitfield.disp32 = 1;
e05278af 6682 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6683 if (flag_code == CODE_64BIT)
6684 {
6685 if (!override)
6686 {
6687 bigdisp.bitfield.disp32s = 1;
6688 bigdisp.bitfield.disp64 = 1;
6689 }
6690 }
6691 else if ((flag_code == CODE_16BIT) ^ override)
6692 {
6693 bigdisp.bitfield.disp32 = 0;
6694 bigdisp.bitfield.disp16 = 1;
6695 }
e05278af
JB		 6696 }
6697 else
6698 {
6699 /* For PC-relative branches, the width of the displacement
6700 is dependent upon data size, not address size. */
e05278af 6701 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6702 if (flag_code == CODE_64BIT)
6703 {
6704 if (override || i.suffix == WORD_MNEM_SUFFIX)
6705 bigdisp.bitfield.disp16 = 1;
6706 else
6707 {
6708 bigdisp.bitfield.disp32 = 1;
6709 bigdisp.bitfield.disp32s = 1;
6710 }
6711 }
6712 else
e05278af
JB		 6713 {
6714 if (!override)
6715 override = (i.suffix == (flag_code != CODE_16BIT
6716 ? WORD_MNEM_SUFFIX
6717 : LONG_MNEM_SUFFIX));
40fb9820
L		 6718 bigdisp.bitfield.disp32 = 1;
6719 if ((flag_code == CODE_16BIT) ^ override)
6720 {
6721 bigdisp.bitfield.disp32 = 0;
6722 bigdisp.bitfield.disp16 = 1;
6723 }
e05278af 6724 }
e05278af 6725 }
c6fb90c8
L		 6726 i.types[this_operand] = operand_type_or (i.types[this_operand],
6727 bigdisp);
252b5132
RH		 6728
6729 exp = &disp_expressions[i.disp_operands];
520dc8e8 6730 i.op[this_operand].disps = exp;
252b5132
RH		 6731 i.disp_operands++;
6732 save_input_line_pointer = input_line_pointer;
6733 input_line_pointer = disp_start;
6734 END_STRING_AND_SAVE (disp_end);
6735
6736#ifndef GCC_ASM_O_HACK
6737#define GCC_ASM_O_HACK 0
6738#endif
6739#if GCC_ASM_O_HACK
6740 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6741 if (i.types[this_operand].bitfield.baseIndex
24eab124 6742 && displacement_string_end[-1] == '+')
252b5132
RH		 6743 {
6744 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6745 constraint within gcc asm statements.
6746 For instance:
6747
6748 #define _set_tssldt_desc(n,addr,limit,type) \
6749 __asm__ __volatile__ ( \
6750 "movw %w2,%0\n\t" \
6751 "movw %w1,2+%0\n\t" \
6752 "rorl $16,%1\n\t" \
6753 "movb %b1,4+%0\n\t" \
6754 "movb %4,5+%0\n\t" \
6755 "movb $0,6+%0\n\t" \
6756 "movb %h1,7+%0\n\t" \
6757 "rorl $16,%1" \
6758 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6759
6760 This works great except that the output assembler ends
6761 up looking a bit weird if it turns out that there is
6762 no offset. You end up producing code that looks like:
6763
6764 #APP
6765 movw $235,(%eax)
6766 movw %dx,2+(%eax)
6767 rorl $16,%edx
6768 movb %dl,4+(%eax)
6769 movb $137,5+(%eax)
6770 movb $0,6+(%eax)
6771 movb %dh,7+(%eax)
6772 rorl $16,%edx
6773 #NO_APP
6774
47926f60 6775 So here we provide the missing zero. */
24eab124
AM		 6776
6777 *displacement_string_end = '0';
252b5132
RH		 6778 }
6779#endif
3956db08 6780 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6781 if (gotfree_input_line)
6782 input_line_pointer = gotfree_input_line;
252b5132 6783
24eab124 6784 exp_seg = expression (exp);
252b5132 6785
636c26b0
AM		 6786 SKIP_WHITESPACE ();
6787 if (*input_line_pointer)
6788 as_bad (_("junk `%s' after expression"), input_line_pointer);
6789#if GCC_ASM_O_HACK
6790 RESTORE_END_STRING (disp_end + 1);
6791#endif
636c26b0 6792 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6793 if (gotfree_input_line)
6794 free (gotfree_input_line);
3992d3b7 6795 ret = 1;
636c26b0 6796
24eab124
AM		 6797 /* We do this to make sure that the section symbol is in
6798 the symbol table. We will ultimately change the relocation
47926f60 6799 to be relative to the beginning of the section. */
1ae12ab7 6800 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6801 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6802 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6803 {
636c26b0 6804 if (exp->X_op != O_symbol)
3992d3b7 6805 goto inv_disp;
636c26b0 6806
e5cb08ac 6807 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6808 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6809 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6810 exp->X_op = O_subtract;
6811 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6812 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6813 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6814 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6815 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6816 else
29b0f896 6817 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6818 }
252b5132 6819
3992d3b7
AM		 6820 else if (exp->X_op == O_absent
6821 || exp->X_op == O_illegal
6822 || exp->X_op == O_big
6823 || (gotfree_input_line
6824 && (exp->X_op == O_constant
6825 || exp->X_op == O_register)))
2daf4fd8 6826 {
3992d3b7
AM		 6827 inv_disp:
6828 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6829 disp_start);
3992d3b7 6830 ret = 0;
2daf4fd8
AM		 6831 }
6832
4c63da97 6833#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6834 else if (exp->X_op != O_constant
6835 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6836 && exp_seg != absolute_section
6837 && exp_seg != text_section
6838 && exp_seg != data_section
6839 && exp_seg != bss_section
6840 && exp_seg != undefined_section
6841 && !bfd_is_com_section (exp_seg))
24eab124 6842 {
d0b47220 6843 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6844 ret = 0;
24eab124 6845 }
252b5132 6846#endif
3956db08 6847
3992d3b7
AM		 6848 RESTORE_END_STRING (disp_end);
6849
40fb9820
L		 6850 /* Check if this is a displacement only operand. */
6851 bigdisp = i.types[this_operand];
6852 bigdisp.bitfield.disp8 = 0;
6853 bigdisp.bitfield.disp16 = 0;
6854 bigdisp.bitfield.disp32 = 0;
6855 bigdisp.bitfield.disp32s = 0;
6856 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6857 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6858 i.types[this_operand] = operand_type_and (i.types[this_operand],
6859 types);
3956db08 6860
3992d3b7 6861 return ret;
252b5132
RH		 6862}
6863
eecb386c 6864/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6865 Return 1 on success, 0 on a failure. */
6866
252b5132 6867static int
e3bb37b5 6868i386_index_check (const char *operand_string)
252b5132 6869{
3e73aa7c 6870 int ok;
24eab124 6871#if INFER_ADDR_PREFIX
eecb386c
AM		 6872 int fudged = 0;
6873
24eab124
AM		 6874 tryprefix:
6875#endif
3e73aa7c 6876 ok = 1;
75178d9d 6877 if (flag_code == CODE_64BIT)
64e74474 6878 {
64e74474 6879 if ((i.base_reg
40fb9820
L		 6880 && ((i.prefix[ADDR_PREFIX] == 0
6881 && !i.base_reg->reg_type.bitfield.reg64)
6882 || (i.prefix[ADDR_PREFIX]
6883 && !i.base_reg->reg_type.bitfield.reg32))
6884 && (i.index_reg
9a04903e
JB		 6885 || i.base_reg->reg_num !=
6886 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6887 || (i.index_reg
40fb9820
L		 6888 && (!i.index_reg->reg_type.bitfield.baseindex
6889 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6890 && i.index_reg->reg_num != RegRiz
6891 && !i.index_reg->reg_type.bitfield.reg64
6892 )
40fb9820 6893 || (i.prefix[ADDR_PREFIX]
db51cc60 6894 && i.index_reg->reg_num != RegEiz
40fb9820 6895 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6896 ok = 0;
3e73aa7c
JH		 6897 }
6898 else
6899 {
6900 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6901 {
6902 /* 16bit checks. */
6903 if ((i.base_reg
40fb9820
L		 6904 && (!i.base_reg->reg_type.bitfield.reg16
6905 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6906 || (i.index_reg
40fb9820
L		 6907 && (!i.index_reg->reg_type.bitfield.reg16
6908 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6909 || !(i.base_reg
6910 && i.base_reg->reg_num < 6
6911 && i.index_reg->reg_num >= 6
6912 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6913 ok = 0;
6914 }
6915 else
e5cb08ac 6916 {
3e73aa7c
JH		 6917 /* 32bit checks. */
6918 if ((i.base_reg
40fb9820 6919 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6920 || (i.index_reg
db51cc60
L		 6921 && ((!i.index_reg->reg_type.bitfield.reg32
6922 && i.index_reg->reg_num != RegEiz)
40fb9820 6923 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6924 ok = 0;
3e73aa7c
JH		 6925 }
6926 }
6927 if (!ok)
24eab124
AM		 6928 {
6929#if INFER_ADDR_PREFIX
20f0a1fc 6930 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6931 {
6932 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6933 i.prefixes += 1;
b23bac36
AM		 6934 /* Change the size of any displacement too. At most one of
6935 Disp16 or Disp32 is set.
6936 FIXME. There doesn't seem to be any real need for separate
6937 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6938 Removing them would probably clean up the code quite a lot. */
4eed87de 6939 if (flag_code != CODE_64BIT
40fb9820
L		 6940 && (i.types[this_operand].bitfield.disp16
6941 || i.types[this_operand].bitfield.disp32))
6942 i.types[this_operand]
c6fb90c8 6943 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6944 fudged = 1;
24eab124
AM		 6945 goto tryprefix;
6946 }
eecb386c
AM		 6947 if (fudged)
6948 as_bad (_("`%s' is not a valid base/index expression"),
6949 operand_string);
6950 else
c388dee8 6951#endif
eecb386c
AM		 6952 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6953 operand_string,
3e73aa7c 6954 flag_code_names[flag_code]);
24eab124 6955 }
20f0a1fc 6956 return ok;
24eab124 6957}
252b5132 6958
252b5132 6959/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6960 on error. */
252b5132 6961
252b5132 6962static int
a7619375 6963i386_att_operand (char *operand_string)
252b5132 6964{
af6bdddf
AM		 6965 const reg_entry *r;
6966 char *end_op;
24eab124 6967 char *op_string = operand_string;
252b5132 6968
24eab124 6969 if (is_space_char (*op_string))
252b5132
RH		 6970 ++op_string;
6971
24eab124 6972 /* We check for an absolute prefix (differentiating,
47926f60 6973 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6974 if (*op_string == ABSOLUTE_PREFIX)
6975 {
6976 ++op_string;
6977 if (is_space_char (*op_string))
6978 ++op_string;
40fb9820 6979 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6980 }
252b5132 6981
47926f60 6982 /* Check if operand is a register. */
4d1bb795 6983 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6984 {
40fb9820
L		 6985 i386_operand_type temp;
6986
24eab124
AM		 6987 /* Check for a segment override by searching for ':' after a
6988 segment register. */
6989 op_string = end_op;
6990 if (is_space_char (*op_string))
6991 ++op_string;
40fb9820
L		 6992 if (*op_string == ':'
6993 && (r->reg_type.bitfield.sreg2
6994 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6995 {
6996 switch (r->reg_num)
6997 {
6998 case 0:
6999 i.seg[i.mem_operands] = &es;
7000 break;
7001 case 1:
7002 i.seg[i.mem_operands] = &cs;
7003 break;
7004 case 2:
7005 i.seg[i.mem_operands] = &ss;
7006 break;
7007 case 3:
7008 i.seg[i.mem_operands] = &ds;
7009 break;
7010 case 4:
7011 i.seg[i.mem_operands] = &fs;
7012 break;
7013 case 5:
7014 i.seg[i.mem_operands] = &gs;
7015 break;
7016 }
252b5132 7017
24eab124 7018 /* Skip the ':' and whitespace. */
252b5132
RH		 7019 ++op_string;
7020 if (is_space_char (*op_string))
24eab124 7021 ++op_string;
252b5132 7022
24eab124
AM		 7023 if (!is_digit_char (*op_string)
7024 && !is_identifier_char (*op_string)
7025 && *op_string != '('
7026 && *op_string != ABSOLUTE_PREFIX)
7027 {
7028 as_bad (_("bad memory operand `%s'"), op_string);
7029 return 0;
7030 }
47926f60 7031 /* Handle case of %es:*foo. */
24eab124
AM		 7032 if (*op_string == ABSOLUTE_PREFIX)
7033 {
7034 ++op_string;
7035 if (is_space_char (*op_string))
7036 ++op_string;
40fb9820 7037 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7038 }
7039 goto do_memory_reference;
7040 }
7041 if (*op_string)
7042 {
d0b47220 7043 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7044 return 0;
7045 }
40fb9820
L		 7046 temp = r->reg_type;
7047 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7048 i.types[this_operand] = operand_type_or (i.types[this_operand],
7049 temp);
7d5e4556 7050 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7051 i.op[this_operand].regs = r;
24eab124
AM		 7052 i.reg_operands++;
7053 }
af6bdddf
AM		 7054 else if (*op_string == REGISTER_PREFIX)
7055 {
7056 as_bad (_("bad register name `%s'"), op_string);
7057 return 0;
7058 }
24eab124 7059 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7060 {
24eab124 7061 ++op_string;
40fb9820 7062 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7063 {
d0b47220 7064 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7065 return 0;
7066 }
7067 if (!i386_immediate (op_string))
7068 return 0;
7069 }
7070 else if (is_digit_char (*op_string)
7071 || is_identifier_char (*op_string)
e5cb08ac 7072 || *op_string == '(')
24eab124 7073 {
47926f60 7074 /* This is a memory reference of some sort. */
af6bdddf 7075 char *base_string;
252b5132 7076
47926f60 7077 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7078 char *displacement_string_start;
7079 char *displacement_string_end;
252b5132 7080
24eab124 7081 do_memory_reference:
24eab124 7082 if ((i.mem_operands == 1
40fb9820 7083 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7084 || i.mem_operands == 2)
7085 {
7086 as_bad (_("too many memory references for `%s'"),
7087 current_templates->start->name);
7088 return 0;
7089 }
252b5132 7090
24eab124
AM		 7091 /* Check for base index form. We detect the base index form by
7092 looking for an ')' at the end of the operand, searching
7093 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7094 after the '('. */
af6bdddf 7095 base_string = op_string + strlen (op_string);
c3332e24 7096
af6bdddf
AM		 7097 --base_string;
7098 if (is_space_char (*base_string))
7099 --base_string;
252b5132 7100
47926f60 7101 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7102 displacement_string_start = op_string;
7103 displacement_string_end = base_string + 1;
252b5132 7104
24eab124
AM		 7105 if (*base_string == ')')
7106 {
af6bdddf 7107 char *temp_string;
24eab124
AM		 7108 unsigned int parens_balanced = 1;
7109 /* We've already checked that the number of left & right ()'s are
47926f60 7110 equal, so this loop will not be infinite. */
24eab124
AM		 7111 do
7112 {
7113 base_string--;
7114 if (*base_string == ')')
7115 parens_balanced++;
7116 if (*base_string == '(')
7117 parens_balanced--;
7118 }
7119 while (parens_balanced);
c3332e24 7120
af6bdddf 7121 temp_string = base_string;
c3332e24 7122
24eab124 7123 /* Skip past '(' and whitespace. */
252b5132
RH		 7124 ++base_string;
7125 if (is_space_char (*base_string))
24eab124 7126 ++base_string;
252b5132 7127
af6bdddf 7128 if (*base_string == ','
4eed87de
AM		 7129 || ((i.base_reg = parse_register (base_string, &end_op))
7130 != NULL))
252b5132 7131 {
af6bdddf 7132 displacement_string_end = temp_string;
252b5132 7133
40fb9820 7134 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7135
af6bdddf 7136 if (i.base_reg)
24eab124 7137 {
24eab124
AM		 7138 base_string = end_op;
7139 if (is_space_char (*base_string))
7140 ++base_string;
af6bdddf
AM		 7141 }
7142
7143 /* There may be an index reg or scale factor here. */
7144 if (*base_string == ',')
7145 {
7146 ++base_string;
7147 if (is_space_char (*base_string))
7148 ++base_string;
7149
4eed87de
AM		 7150 if ((i.index_reg = parse_register (base_string, &end_op))
7151 != NULL)
24eab124 7152 {
af6bdddf 7153 base_string = end_op;
24eab124
AM		 7154 if (is_space_char (*base_string))
7155 ++base_string;
af6bdddf
AM		 7156 if (*base_string == ',')
7157 {
7158 ++base_string;
7159 if (is_space_char (*base_string))
7160 ++base_string;
7161 }
e5cb08ac 7162 else if (*base_string != ')')
af6bdddf 7163 {
4eed87de
AM		 7164 as_bad (_("expecting `,' or `)' "
7165 "after index register in `%s'"),
af6bdddf
AM		 7166 operand_string);
7167 return 0;
7168 }
24eab124 7169 }
af6bdddf 7170 else if (*base_string == REGISTER_PREFIX)
24eab124 7171 {
af6bdddf 7172 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7173 return 0;
7174 }
252b5132 7175
47926f60 7176 /* Check for scale factor. */
551c1ca1 7177 if (*base_string != ')')
af6bdddf 7178 {
551c1ca1
AM		 7179 char *end_scale = i386_scale (base_string);
7180
7181 if (!end_scale)
af6bdddf 7182 return 0;
24eab124 7183
551c1ca1 7184 base_string = end_scale;
af6bdddf
AM		 7185 if (is_space_char (*base_string))
7186 ++base_string;
7187 if (*base_string != ')')
7188 {
4eed87de
AM		 7189 as_bad (_("expecting `)' "
7190 "after scale factor in `%s'"),
af6bdddf
AM		 7191 operand_string);
7192 return 0;
7193 }
7194 }
7195 else if (!i.index_reg)
24eab124 7196 {
4eed87de
AM		 7197 as_bad (_("expecting index register or scale factor "
7198 "after `,'; got '%c'"),
af6bdddf 7199 *base_string);
24eab124
AM		 7200 return 0;
7201 }
7202 }
af6bdddf 7203 else if (*base_string != ')')
24eab124 7204 {
4eed87de
AM		 7205 as_bad (_("expecting `,' or `)' "
7206 "after base register in `%s'"),
af6bdddf 7207 operand_string);
24eab124
AM		 7208 return 0;
7209 }
c3332e24 7210 }
af6bdddf 7211 else if (*base_string == REGISTER_PREFIX)
c3332e24 7212 {
af6bdddf 7213 as_bad (_("bad register name `%s'"), base_string);
24eab124 7214 return 0;
c3332e24 7215 }
24eab124
AM		 7216 }
7217
7218 /* If there's an expression beginning the operand, parse it,
7219 assuming displacement_string_start and
7220 displacement_string_end are meaningful. */
7221 if (displacement_string_start != displacement_string_end)
7222 {
7223 if (!i386_displacement (displacement_string_start,
7224 displacement_string_end))
7225 return 0;
7226 }
7227
7228 /* Special case for (%dx) while doing input/output op. */
7229 if (i.base_reg
0dfbf9d7
L		 7230 && operand_type_equal (&i.base_reg->reg_type,
7231 &reg16_inoutportreg)
24eab124
AM		 7232 && i.index_reg == 0
7233 && i.log2_scale_factor == 0
7234 && i.seg[i.mem_operands] == 0
40fb9820 7235 && !operand_type_check (i.types[this_operand], disp))
24eab124 7236 {
65da13b5 7237 i.types[this_operand] = inoutportreg;
24eab124
AM		 7238 return 1;
7239 }
7240
eecb386c
AM		 7241 if (i386_index_check (operand_string) == 0)
7242 return 0;
5c07affc 7243 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7244 i.mem_operands++;
7245 }
7246 else
ce8a8b2f
AM		 7247 {
7248 /* It's not a memory operand; argh! */
24eab124
AM		 7249 as_bad (_("invalid char %s beginning operand %d `%s'"),
7250 output_invalid (*op_string),
7251 this_operand + 1,
7252 op_string);
7253 return 0;
7254 }
47926f60 7255 return 1; /* Normal return. */
252b5132
RH		 7256}
7257\f
ee7fcc42
AM		 7258/* md_estimate_size_before_relax()
7259
7260 Called just before relax() for rs_machine_dependent frags. The x86
7261 assembler uses these frags to handle variable size jump
7262 instructions.
7263
7264 Any symbol that is now undefined will not become defined.
7265 Return the correct fr_subtype in the frag.
7266 Return the initial "guess for variable size of frag" to caller.
7267 The guess is actually the growth beyond the fixed part. Whatever
7268 we do to grow the fixed or variable part contributes to our
7269 returned value. */
7270
252b5132
RH		 7271int
7272md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7273 fragS *fragP;
7274 segT segment;
252b5132 7275{
252b5132 7276 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7277 check for un-relaxable symbols. On an ELF system, we can't relax
7278 an externally visible symbol, because it may be overridden by a
7279 shared library. */
7280 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7281#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7282 || (IS_ELF
31312f95
AM		 7283 && (S_IS_EXTERNAL (fragP->fr_symbol)
7284 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7285#endif
7286 )
252b5132 7287 {
b98ef147
AM		 7288 /* Symbol is undefined in this segment, or we need to keep a
7289 reloc so that weak symbols can be overridden. */
7290 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7291 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7292 unsigned char *opcode;
7293 int old_fr_fix;
f6af82bd 7294
ee7fcc42
AM		 7295 if (fragP->fr_var != NO_RELOC)
7296 reloc_type = fragP->fr_var;
b98ef147 7297 else if (size == 2)
f6af82bd
AM		 7298 reloc_type = BFD_RELOC_16_PCREL;
7299 else
7300 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7301
ee7fcc42
AM		 7302 old_fr_fix = fragP->fr_fix;
7303 opcode = (unsigned char *) fragP->fr_opcode;
7304
fddf5b5b 7305 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7306 {
fddf5b5b
AM		 7307 case UNCOND_JUMP:
7308 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7309 opcode[0] = 0xe9;
252b5132 7310 fragP->fr_fix += size;
062cd5e7
AS		 7311 fix_new (fragP, old_fr_fix, size,
7312 fragP->fr_symbol,
7313 fragP->fr_offset, 1,
7314 reloc_type);
252b5132
RH		 7315 break;
7316
fddf5b5b 7317 case COND_JUMP86:
412167cb
AM		 7318 if (size == 2
7319 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7320 {
7321 /* Negate the condition, and branch past an
7322 unconditional jump. */
7323 opcode[0] ^= 1;
7324 opcode[1] = 3;
7325 /* Insert an unconditional jump. */
7326 opcode[2] = 0xe9;
7327 /* We added two extra opcode bytes, and have a two byte
7328 offset. */
7329 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7330 fix_new (fragP, old_fr_fix + 2, 2,
7331 fragP->fr_symbol,
7332 fragP->fr_offset, 1,
7333 reloc_type);
fddf5b5b
AM		 7334 break;
7335 }
7336 /* Fall through. */
7337
7338 case COND_JUMP:
412167cb
AM		 7339 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7340 {
3e02c1cc
AM		 7341 fixS *fixP;
7342
412167cb 7343 fragP->fr_fix += 1;
3e02c1cc
AM		 7344 fixP = fix_new (fragP, old_fr_fix, 1,
7345 fragP->fr_symbol,
7346 fragP->fr_offset, 1,
7347 BFD_RELOC_8_PCREL);
7348 fixP->fx_signed = 1;
412167cb
AM		 7349 break;
7350 }
93c2a809 7351
24eab124 7352 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7353 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7354 opcode[1] = opcode[0] + 0x10;
f6af82bd 7355 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7356 /* We've added an opcode byte. */
7357 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7358 fix_new (fragP, old_fr_fix + 1, size,
7359 fragP->fr_symbol,
7360 fragP->fr_offset, 1,
7361 reloc_type);
252b5132 7362 break;
fddf5b5b
AM		 7363
7364 default:
7365 BAD_CASE (fragP->fr_subtype);
7366 break;
252b5132
RH		 7367 }
7368 frag_wane (fragP);
ee7fcc42 7369 return fragP->fr_fix - old_fr_fix;
252b5132 7370 }
93c2a809 7371
93c2a809
AM		 7372 /* Guess size depending on current relax state. Initially the relax
7373 state will correspond to a short jump and we return 1, because
7374 the variable part of the frag (the branch offset) is one byte
7375 long. However, we can relax a section more than once and in that
7376 case we must either set fr_subtype back to the unrelaxed state,
7377 or return the value for the appropriate branch. */
7378 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7379}
7380
47926f60
KH		 7381/* Called after relax() is finished.
7382
7383 In: Address of frag.
7384 fr_type == rs_machine_dependent.
7385 fr_subtype is what the address relaxed to.
7386
7387 Out: Any fixSs and constants are set up.
7388 Caller will turn frag into a ".space 0". */
7389
252b5132
RH		 7390void
7391md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7392 bfd *abfd ATTRIBUTE_UNUSED;
7393 segT sec ATTRIBUTE_UNUSED;
29b0f896 7394 fragS *fragP;
252b5132 7395{
29b0f896 7396 unsigned char *opcode;
252b5132 7397 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7398 offsetT target_address;
7399 offsetT opcode_address;
252b5132 7400 unsigned int extension = 0;
847f7ad4 7401 offsetT displacement_from_opcode_start;
252b5132
RH		 7402
7403 opcode = (unsigned char *) fragP->fr_opcode;
7404
47926f60 7405 /* Address we want to reach in file space. */
252b5132 7406 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7407
47926f60 7408 /* Address opcode resides at in file space. */
252b5132
RH		 7409 opcode_address = fragP->fr_address + fragP->fr_fix;
7410
47926f60 7411 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7412 displacement_from_opcode_start = target_address - opcode_address;
7413
fddf5b5b 7414 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7415 {
47926f60
KH		 7416 /* Don't have to change opcode. */
7417 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7418 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7419 }
7420 else
7421 {
7422 if (no_cond_jump_promotion
7423 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7424 as_warn_where (fragP->fr_file, fragP->fr_line,
7425 _("long jump required"));
252b5132 7426
fddf5b5b
AM		 7427 switch (fragP->fr_subtype)
7428 {
7429 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7430 extension = 4; /* 1 opcode + 4 displacement */
7431 opcode[0] = 0xe9;
7432 where_to_put_displacement = &opcode[1];
7433 break;
252b5132 7434
fddf5b5b
AM		 7435 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7436 extension = 2; /* 1 opcode + 2 displacement */
7437 opcode[0] = 0xe9;
7438 where_to_put_displacement = &opcode[1];
7439 break;
252b5132 7440
fddf5b5b
AM		 7441 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7442 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7443 extension = 5; /* 2 opcode + 4 displacement */
7444 opcode[1] = opcode[0] + 0x10;
7445 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7446 where_to_put_displacement = &opcode[2];
7447 break;
252b5132 7448
fddf5b5b
AM		 7449 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7450 extension = 3; /* 2 opcode + 2 displacement */
7451 opcode[1] = opcode[0] + 0x10;
7452 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7453 where_to_put_displacement = &opcode[2];
7454 break;
252b5132 7455
fddf5b5b
AM		 7456 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7457 extension = 4;
7458 opcode[0] ^= 1;
7459 opcode[1] = 3;
7460 opcode[2] = 0xe9;
7461 where_to_put_displacement = &opcode[3];
7462 break;
7463
7464 default:
7465 BAD_CASE (fragP->fr_subtype);
7466 break;
7467 }
252b5132 7468 }
fddf5b5b 7469
7b81dfbb
AJ		 7470 /* If size if less then four we are sure that the operand fits,
7471 but if it's 4, then it could be that the displacement is larger
7472 then -/+ 2GB. */
7473 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7474 && object_64bit
7475 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7476 + ((addressT) 1 << 31))
7477 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7478 {
7479 as_bad_where (fragP->fr_file, fragP->fr_line,
7480 _("jump target out of range"));
7481 /* Make us emit 0. */
7482 displacement_from_opcode_start = extension;
7483 }
47926f60 7484 /* Now put displacement after opcode. */
252b5132
RH		 7485 md_number_to_chars ((char *) where_to_put_displacement,
7486 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7487 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7488 fragP->fr_fix += extension;
7489}
7490\f
252b5132
RH		 7491/* Apply a fixup (fixS) to segment data, once it has been determined
7492 by our caller that we have all the info we need to fix it up.
7493
7494 On the 386, immediates, displacements, and data pointers are all in
7495 the same (little-endian) format, so we don't need to care about which
7496 we are handling. */
7497
94f592af 7498void
55cf6793 7499md_apply_fix (fixP, valP, seg)
47926f60
KH		 7500 /* The fix we're to put in. */
7501 fixS *fixP;
47926f60 7502 /* Pointer to the value of the bits. */
c6682705 7503 valueT *valP;
47926f60
KH		 7504 /* Segment fix is from. */
7505 segT seg ATTRIBUTE_UNUSED;
252b5132 7506{
94f592af 7507 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7508 valueT value = *valP;
252b5132 7509
f86103b7 7510#if !defined (TE_Mach)
93382f6d
AM		 7511 if (fixP->fx_pcrel)
7512 {
7513 switch (fixP->fx_r_type)
7514 {
5865bb77
ILT		 7515 default:
7516 break;
7517
d6ab8113
JB		 7518 case BFD_RELOC_64:
7519 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7520 break;
93382f6d 7521 case BFD_RELOC_32:
ae8887b5 7522 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7523 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7524 break;
7525 case BFD_RELOC_16:
7526 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7527 break;
7528 case BFD_RELOC_8:
7529 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7530 break;
7531 }
7532 }
252b5132 7533
a161fe53 7534 if (fixP->fx_addsy != NULL
31312f95 7535 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7536 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7537 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7538 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7539 && !use_rela_relocations)
252b5132 7540 {
31312f95
AM		 7541 /* This is a hack. There should be a better way to handle this.
7542 This covers for the fact that bfd_install_relocation will
7543 subtract the current location (for partial_inplace, PC relative
7544 relocations); see more below. */
252b5132 7545#ifndef OBJ_AOUT
718ddfc0 7546 if (IS_ELF
252b5132
RH		 7547#ifdef TE_PE
7548 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7549#endif
7550 )
7551 value += fixP->fx_where + fixP->fx_frag->fr_address;
7552#endif
7553#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7554 if (IS_ELF)
252b5132 7555 {
6539b54b 7556 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7557
6539b54b 7558 if ((sym_seg == seg
2f66722d 7559 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7560 && sym_seg != absolute_section))
ae6063d4 7561 && !generic_force_reloc (fixP))
2f66722d
AM		 7562 {
7563 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7564 bfd_install_relocation subtracts them out again. I think
7565 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7566 it. FIXME. */
7567 value += fixP->fx_where + fixP->fx_frag->fr_address;
7568 }
252b5132
RH		 7569 }
7570#endif
7571#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7572 /* For some reason, the PE format does not store a
7573 section address offset for a PC relative symbol. */
7574 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7575 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7576 value += md_pcrel_from (fixP);
7577#endif
7578 }
7579
7580 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7581 and we must not disappoint it. */
252b5132 7582#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7583 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7584 switch (fixP->fx_r_type)
7585 {
7586 case BFD_RELOC_386_PLT32:
3e73aa7c 7587 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7588 /* Make the jump instruction point to the address of the operand. At
7589 runtime we merely add the offset to the actual PLT entry. */
7590 value = -4;
7591 break;
31312f95 7592
13ae64f3
JJ		 7593 case BFD_RELOC_386_TLS_GD:
7594 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7595 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7596 case BFD_RELOC_386_TLS_IE:
7597 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7598 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7599 case BFD_RELOC_X86_64_TLSGD:
7600 case BFD_RELOC_X86_64_TLSLD:
7601 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7602 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7603 value = 0; /* Fully resolved at runtime. No addend. */
7604 /* Fallthrough */
7605 case BFD_RELOC_386_TLS_LE:
7606 case BFD_RELOC_386_TLS_LDO_32:
7607 case BFD_RELOC_386_TLS_LE_32:
7608 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7609 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7610 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7611 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7612 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7613 break;
7614
67a4f2b7
AO		 7615 case BFD_RELOC_386_TLS_DESC_CALL:
7616 case BFD_RELOC_X86_64_TLSDESC_CALL:
7617 value = 0; /* Fully resolved at runtime. No addend. */
7618 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7619 fixP->fx_done = 0;
7620 return;
7621
00f7efb6
JJ		 7622 case BFD_RELOC_386_GOT32:
7623 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7624 value = 0; /* Fully resolved at runtime. No addend. */
7625 break;
47926f60
KH		 7626
7627 case BFD_RELOC_VTABLE_INHERIT:
7628 case BFD_RELOC_VTABLE_ENTRY:
7629 fixP->fx_done = 0;
94f592af 7630 return;
47926f60
KH		 7631
7632 default:
7633 break;
7634 }
7635#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7636 *valP = value;
f86103b7 7637#endif /* !defined (TE_Mach) */
3e73aa7c 7638
3e73aa7c 7639 /* Are we finished with this relocation now? */
c6682705 7640 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7641 fixP->fx_done = 1;
7642 else if (use_rela_relocations)
7643 {
7644 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7645 /* Remember value for tc_gen_reloc. */
7646 fixP->fx_addnumber = value;
3e73aa7c
JH		 7647 value = 0;
7648 }
f86103b7 7649
94f592af 7650 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7651}
252b5132 7652\f
252b5132 7653char *
499ac353 7654md_atof (int type, char *litP, int *sizeP)
252b5132 7655{
499ac353
NC		 7656 /* This outputs the LITTLENUMs in REVERSE order;
7657 in accord with the bigendian 386. */
7658 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7659}
7660\f
2d545b82 7661static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7662
252b5132 7663static char *
e3bb37b5 7664output_invalid (int c)
252b5132 7665{
3882b010 7666 if (ISPRINT (c))
f9f21a03
L		 7667 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7668 "'%c'", c);
252b5132 7669 else
f9f21a03 7670 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7671 "(0x%x)", (unsigned char) c);
252b5132
RH		 7672 return output_invalid_buf;
7673}
7674
af6bdddf 7675/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7676
7677static const reg_entry *
4d1bb795 7678parse_real_register (char *reg_string, char **end_op)
252b5132 7679{
af6bdddf
AM		 7680 char *s = reg_string;
7681 char *p;
252b5132
RH		 7682 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7683 const reg_entry *r;
7684
7685 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7686 if (*s == REGISTER_PREFIX)
7687 ++s;
7688
7689 if (is_space_char (*s))
7690 ++s;
7691
7692 p = reg_name_given;
af6bdddf 7693 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7694 {
7695 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7696 return (const reg_entry *) NULL;
7697 s++;
252b5132
RH		 7698 }
7699
6588847e
DN		 7700 /* For naked regs, make sure that we are not dealing with an identifier.
7701 This prevents confusing an identifier like `eax_var' with register
7702 `eax'. */
7703 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7704 return (const reg_entry *) NULL;
7705
af6bdddf 7706 *end_op = s;
252b5132
RH		 7707
7708 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7709
5f47d35b 7710 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7711 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7712 {
5f47d35b
AM		 7713 if (is_space_char (*s))
7714 ++s;
7715 if (*s == '(')
7716 {
af6bdddf 7717 ++s;
5f47d35b
AM		 7718 if (is_space_char (*s))
7719 ++s;
7720 if (*s >= '0' && *s <= '7')
7721 {
db557034 7722 int fpr = *s - '0';
af6bdddf 7723 ++s;
5f47d35b
AM		 7724 if (is_space_char (*s))
7725 ++s;
7726 if (*s == ')')
7727 {
7728 *end_op = s + 1;
db557034
AM		 7729 r = hash_find (reg_hash, "st(0)");
7730 know (r);
7731 return r + fpr;
5f47d35b 7732 }
5f47d35b 7733 }
47926f60 7734 /* We have "%st(" then garbage. */
5f47d35b
AM		 7735 return (const reg_entry *) NULL;
7736 }
7737 }
7738
a60de03c
JB		 7739 if (r == NULL || allow_pseudo_reg)
7740 return r;
7741
0dfbf9d7 7742 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7743 return (const reg_entry *) NULL;
7744
192dc9c6
JB		 7745 if ((r->reg_type.bitfield.reg32
7746 || r->reg_type.bitfield.sreg3
7747 || r->reg_type.bitfield.control
7748 || r->reg_type.bitfield.debug
7749 || r->reg_type.bitfield.test)
7750 && !cpu_arch_flags.bitfield.cpui386)
7751 return (const reg_entry *) NULL;
7752
7753 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7754 return (const reg_entry *) NULL;
7755
7756 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7757 return (const reg_entry *) NULL;
7758
40f12533
L		 7759 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7760 return (const reg_entry *) NULL;
7761
db51cc60 7762 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7763 if (!allow_index_reg
db51cc60
L		 7764 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7765 return (const reg_entry *) NULL;
7766
a60de03c
JB		 7767 if (((r->reg_flags & (RegRex64 | RegRex))
7768 || r->reg_type.bitfield.reg64)
40fb9820 7769 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7770 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7771 && flag_code != CODE_64BIT)
20f0a1fc 7772 return (const reg_entry *) NULL;
1ae00879 7773
b7240065
JB		 7774 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7775 return (const reg_entry *) NULL;
7776
252b5132
RH		 7777 return r;
7778}
4d1bb795
JB		 7779
7780/* REG_STRING starts *before* REGISTER_PREFIX. */
7781
7782static const reg_entry *
7783parse_register (char *reg_string, char **end_op)
7784{
7785 const reg_entry *r;
7786
7787 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7788 r = parse_real_register (reg_string, end_op);
7789 else
7790 r = NULL;
7791 if (!r)
7792 {
7793 char *save = input_line_pointer;
7794 char c;
7795 symbolS *symbolP;
7796
7797 input_line_pointer = reg_string;
7798 c = get_symbol_end ();
7799 symbolP = symbol_find (reg_string);
7800 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7801 {
7802 const expressionS *e = symbol_get_value_expression (symbolP);
7803
7804 know (e->X_op == O_register);
4eed87de 7805 know (e->X_add_number >= 0
c3fe08fa 7806 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7807 r = i386_regtab + e->X_add_number;
7808 *end_op = input_line_pointer;
7809 }
7810 *input_line_pointer = c;
7811 input_line_pointer = save;
7812 }
7813 return r;
7814}
7815
7816int
7817i386_parse_name (char *name, expressionS *e, char *nextcharP)
7818{
7819 const reg_entry *r;
7820 char *end = input_line_pointer;
7821
7822 *end = *nextcharP;
7823 r = parse_register (name, &input_line_pointer);
7824 if (r && end <= input_line_pointer)
7825 {
7826 *nextcharP = *input_line_pointer;
7827 *input_line_pointer = 0;
7828 e->X_op = O_register;
7829 e->X_add_number = r - i386_regtab;
7830 return 1;
7831 }
7832 input_line_pointer = end;
7833 *end = 0;
7834 return 0;
7835}
7836
7837void
7838md_operand (expressionS *e)
7839{
7840 if (*input_line_pointer == REGISTER_PREFIX)
7841 {
7842 char *end;
7843 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7844
7845 if (r)
7846 {
7847 e->X_op = O_register;
7848 e->X_add_number = r - i386_regtab;
7849 input_line_pointer = end;
7850 }
7851 }
7852}
7853
252b5132 7854\f
4cc782b5 7855#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7856const char *md_shortopts = "kVQ:sqn";
252b5132 7857#else
12b55ccc 7858const char *md_shortopts = "qn";
252b5132 7859#endif
6e0b89ee 7860
3e73aa7c 7861#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7862#define OPTION_64 (OPTION_MD_BASE + 1)
7863#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7864#define OPTION_MARCH (OPTION_MD_BASE + 3)
7865#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7866#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7867#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7868#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7869#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7870#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7871#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7872#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7873
99ad8390
NC		 7874struct option md_longopts[] =
7875{
3e73aa7c 7876 {"32", no_argument, NULL, OPTION_32},
99ad8390 7877#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7878 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7879#endif
b3b91714 7880 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7881 {"march", required_argument, NULL, OPTION_MARCH},
7882 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7883 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7884 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7885 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7886 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7887 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7888 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7889 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7890 {NULL, no_argument, NULL, 0}
7891};
7892size_t md_longopts_size = sizeof (md_longopts);
7893
7894int
9103f4f4 7895md_parse_option (int c, char *arg)
252b5132 7896{
9103f4f4 7897 unsigned int i;
6305a203 7898 char *arch, *next;
9103f4f4 7899
252b5132
RH		 7900 switch (c)
7901 {
12b55ccc
L		 7902 case 'n':
7903 optimize_align_code = 0;
7904 break;
7905
a38cf1db
AM		 7906 case 'q':
7907 quiet_warnings = 1;
252b5132
RH		 7908 break;
7909
7910#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7911 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7912 should be emitted or not. FIXME: Not implemented. */
7913 case 'Q':
252b5132
RH		 7914 break;
7915
7916 /* -V: SVR4 argument to print version ID. */
7917 case 'V':
7918 print_version_id ();
7919 break;
7920
a38cf1db
AM		 7921 /* -k: Ignore for FreeBSD compatibility. */
7922 case 'k':
252b5132 7923 break;
4cc782b5
ILT		 7924
7925 case 's':
7926 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7927 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7928 break;
99ad8390
NC		 7929#endif
7930#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7931 case OPTION_64:
7932 {
7933 const char **list, **l;
7934
3e73aa7c
JH		 7935 list = bfd_target_list ();
7936 for (l = list; *l != NULL; l++)
8620418b 7937 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7938 || strcmp (*l, "coff-x86-64") == 0
7939 || strcmp (*l, "pe-x86-64") == 0
7940 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7941 {
7942 default_arch = "x86_64";
7943 break;
7944 }
3e73aa7c 7945 if (*l == NULL)
6e0b89ee 7946 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7947 free (list);
7948 }
7949 break;
7950#endif
252b5132 7951
6e0b89ee
AM		 7952 case OPTION_32:
7953 default_arch = "i386";
7954 break;
7955
b3b91714
AM		 7956 case OPTION_DIVIDE:
7957#ifdef SVR4_COMMENT_CHARS
7958 {
7959 char *n, *t;
7960 const char *s;
7961
7962 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7963 t = n;
7964 for (s = i386_comment_chars; *s != '\0'; s++)
7965 if (*s != '/')
7966 *t++ = *s;
7967 *t = '\0';
7968 i386_comment_chars = n;
7969 }
7970#endif
7971 break;
7972
9103f4f4 7973 case OPTION_MARCH:
6305a203
L		 7974 arch = xstrdup (arg);
7975 do
9103f4f4 7976 {
6305a203
L		 7977 if (*arch == '.')
7978 as_fatal (_("Invalid -march= option: `%s'"), arg);
7979 next = strchr (arch, '+');
7980 if (next)
7981 *next++ = '\0';
7982 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 7983 {
6305a203 7984 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 7985 {
6305a203
L		 7986 /* Processor. */
7987 cpu_arch_name = cpu_arch[i].name;
7988 cpu_sub_arch_name = NULL;
7989 cpu_arch_flags = cpu_arch[i].flags;
7990 cpu_arch_isa = cpu_arch[i].type;
7991 cpu_arch_isa_flags = cpu_arch[i].flags;
7992 if (!cpu_arch_tune_set)
7993 {
7994 cpu_arch_tune = cpu_arch_isa;
7995 cpu_arch_tune_flags = cpu_arch_isa_flags;
7996 }
7997 break;
7998 }
7999 else if (*cpu_arch [i].name == '.'
8000 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8001 {
8002 /* ISA entension. */
8003 i386_cpu_flags flags;
8004 flags = cpu_flags_or (cpu_arch_flags,
8005 cpu_arch[i].flags);
0dfbf9d7 8006 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8007 {
8008 if (cpu_sub_arch_name)
8009 {
8010 char *name = cpu_sub_arch_name;
8011 cpu_sub_arch_name = concat (name,
8012 cpu_arch[i].name,
1bf57e9f 8013 (const char *) NULL);
6305a203
L		 8014 free (name);
8015 }
8016 else
8017 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8018 cpu_arch_flags = flags;
8019 }
8020 break;
ccc9c027 8021 }
9103f4f4 8022 }
6305a203
L		 8023
8024 if (i >= ARRAY_SIZE (cpu_arch))
8025 as_fatal (_("Invalid -march= option: `%s'"), arg);
8026
8027 arch = next;
9103f4f4 8028 }
6305a203 8029 while (next != NULL );
9103f4f4
L		 8030 break;
8031
8032 case OPTION_MTUNE:
8033 if (*arg == '.')
8034 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8035 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8036 {
8037 if (strcmp (arg, cpu_arch [i].name) == 0)
8038 {
ccc9c027 8039 cpu_arch_tune_set = 1;
9103f4f4
L		 8040 cpu_arch_tune = cpu_arch [i].type;
8041 cpu_arch_tune_flags = cpu_arch[i].flags;
8042 break;
8043 }
8044 }
8045 if (i >= ARRAY_SIZE (cpu_arch))
8046 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8047 break;
8048
1efbbeb4
L		 8049 case OPTION_MMNEMONIC:
8050 if (strcasecmp (arg, "att") == 0)
8051 intel_mnemonic = 0;
8052 else if (strcasecmp (arg, "intel") == 0)
8053 intel_mnemonic = 1;
8054 else
8055 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8056 break;
8057
8058 case OPTION_MSYNTAX:
8059 if (strcasecmp (arg, "att") == 0)
8060 intel_syntax = 0;
8061 else if (strcasecmp (arg, "intel") == 0)
8062 intel_syntax = 1;
8063 else
8064 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8065 break;
8066
8067 case OPTION_MINDEX_REG:
8068 allow_index_reg = 1;
8069 break;
8070
8071 case OPTION_MNAKED_REG:
8072 allow_naked_reg = 1;
8073 break;
8074
8075 case OPTION_MOLD_GCC:
8076 old_gcc = 1;
1efbbeb4
L		 8077 break;
8078
c0f3af97
L		 8079 case OPTION_MSSE2AVX:
8080 sse2avx = 1;
8081 break;
8082
daf50ae7
L		 8083 case OPTION_MSSE_CHECK:
8084 if (strcasecmp (arg, "error") == 0)
8085 sse_check = sse_check_error;
8086 else if (strcasecmp (arg, "warning") == 0)
8087 sse_check = sse_check_warning;
8088 else if (strcasecmp (arg, "none") == 0)
8089 sse_check = sse_check_none;
8090 else
8091 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8092 break;
8093
252b5132
RH		 8094 default:
8095 return 0;
8096 }
8097 return 1;
8098}
8099
8100void
8101md_show_usage (stream)
8102 FILE *stream;
8103{
4cc782b5
ILT		 8104#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8105 fprintf (stream, _("\
a38cf1db
AM		 8106 -Q ignored\n\
8107 -V print assembler version number\n\
b3b91714
AM		 8108 -k ignored\n"));
8109#endif
8110 fprintf (stream, _("\
12b55ccc 8111 -n Do not optimize code alignment\n\
b3b91714
AM		 8112 -q quieten some warnings\n"));
8113#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8114 fprintf (stream, _("\
a38cf1db 8115 -s ignored\n"));
b3b91714 8116#endif
751d281c
L		 8117#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8118 fprintf (stream, _("\
8119 --32/--64 generate 32bit/64bit code\n"));
8120#endif
b3b91714
AM		 8121#ifdef SVR4_COMMENT_CHARS
8122 fprintf (stream, _("\
8123 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8124#else
8125 fprintf (stream, _("\
b3b91714 8126 --divide ignored\n"));
4cc782b5 8127#endif
9103f4f4 8128 fprintf (stream, _("\
6305a203
L		 8129 -march=CPU[,+EXTENSION...]\n\
8130 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8131 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8132 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8133 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8134 generic32, generic64\n\
599121aa
L		 8135 EXTENSION is combination of:\n\
8136 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695
L		 8137 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8138 3dnow, 3dnowa, sse4a, sse5, svme, abm, padlock\n"));
6305a203 8139 fprintf (stream, _("\
2cb4f3d5
L		 8140 -mtune=CPU optimize for CPU, CPU is one of:\n\
8141 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8142 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8143 core, core2, k6, k6_2, athlon, k8, amdfam10,\n\
8144 generic32, generic64\n"));
ba104c83 8145 fprintf (stream, _("\
c0f3af97
L		 8146 -msse2avx encode SSE instructions with VEX prefix\n"));
8147 fprintf (stream, _("\
daf50ae7
L		 8148 -msse-check=[none|error|warning]\n\
8149 check SSE instructions\n"));
8150 fprintf (stream, _("\
ba104c83
L		 8151 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8152 fprintf (stream, _("\
8153 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8154 fprintf (stream, _("\
8155 -mindex-reg support pseudo index registers\n"));
8156 fprintf (stream, _("\
8157 -mnaked-reg don't require `%%' prefix for registers\n"));
8158 fprintf (stream, _("\
8159 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8160}
8161
3e73aa7c 8162#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8163 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8164
8165/* Pick the target format to use. */
8166
47926f60 8167const char *
e3bb37b5 8168i386_target_format (void)
252b5132 8169{
3e73aa7c 8170 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8171 {
8172 set_code_flag (CODE_64BIT);
0dfbf9d7 8173 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8174 {
8175 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8176 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8177 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8178 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8179 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8180 cpu_arch_isa_flags.bitfield.cpui686 = 1;
8181 cpu_arch_isa_flags.bitfield.cpup4 = 1;
8182 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8183 cpu_arch_isa_flags.bitfield.cpusse = 1;
8184 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8185 }
0dfbf9d7 8186 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8187 {
8188 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8189 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8190 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8191 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8192 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8193 cpu_arch_tune_flags.bitfield.cpui686 = 1;
8194 cpu_arch_tune_flags.bitfield.cpup4 = 1;
8195 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8196 cpu_arch_tune_flags.bitfield.cpusse = 1;
8197 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8198 }
9103f4f4 8199 }
3e73aa7c 8200 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8201 {
8202 set_code_flag (CODE_32BIT);
0dfbf9d7 8203 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8204 {
8205 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8206 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8207 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8208 }
0dfbf9d7 8209 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8210 {
8211 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8212 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8213 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8214 }
9103f4f4 8215 }
3e73aa7c
JH		 8216 else
8217 as_fatal (_("Unknown architecture"));
252b5132
RH		 8218 switch (OUTPUT_FLAVOR)
8219 {
872ce6ff
L		 8220#ifdef TE_PEP
8221 case bfd_target_coff_flavour:
8222 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
8223 break;
8224#endif
4c63da97
AM		 8225#ifdef OBJ_MAYBE_AOUT
8226 case bfd_target_aout_flavour:
47926f60 8227 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8228#endif
8229#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8230 case bfd_target_coff_flavour:
8231 return "coff-i386";
4c63da97 8232#endif
3e73aa7c 8233#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8234 case bfd_target_elf_flavour:
3e73aa7c 8235 {
e5cb08ac 8236 if (flag_code == CODE_64BIT)
4fa24527
JB		 8237 {
8238 object_64bit = 1;
8239 use_rela_relocations = 1;
8240 }
9d7cbccd 8241 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8242 }
4c63da97 8243#endif
252b5132
RH		 8244 default:
8245 abort ();
8246 return NULL;
8247 }
8248}
8249
47926f60 8250#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8251
8252#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8253void
8254i386_elf_emit_arch_note (void)
a847613f 8255{
718ddfc0 8256 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8257 {
8258 char *p;
8259 asection *seg = now_seg;
8260 subsegT subseg = now_subseg;
8261 Elf_Internal_Note i_note;
8262 Elf_External_Note e_note;
8263 asection *note_secp;
8264 int len;
8265
8266 /* Create the .note section. */
8267 note_secp = subseg_new (".note", 0);
8268 bfd_set_section_flags (stdoutput,
8269 note_secp,
8270 SEC_HAS_CONTENTS | SEC_READONLY);
8271
8272 /* Process the arch string. */
8273 len = strlen (cpu_arch_name);
8274
8275 i_note.namesz = len + 1;
8276 i_note.descsz = 0;
8277 i_note.type = NT_ARCH;
8278 p = frag_more (sizeof (e_note.namesz));
8279 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8280 p = frag_more (sizeof (e_note.descsz));
8281 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8282 p = frag_more (sizeof (e_note.type));
8283 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8284 p = frag_more (len + 1);
8285 strcpy (p, cpu_arch_name);
8286
8287 frag_align (2, 0, 0);
8288
8289 subseg_set (seg, subseg);
8290 }
8291}
8292#endif
252b5132 8293\f
252b5132
RH		 8294symbolS *
8295md_undefined_symbol (name)
8296 char *name;
8297{
18dc2407
ILT		 8298 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8299 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8300 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8301 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8302 {
8303 if (!GOT_symbol)
8304 {
8305 if (symbol_find (name))
8306 as_bad (_("GOT already in symbol table"));
8307 GOT_symbol = symbol_new (name, undefined_section,
8308 (valueT) 0, &zero_address_frag);
8309 };
8310 return GOT_symbol;
8311 }
252b5132
RH		 8312 return 0;
8313}
8314
8315/* Round up a section size to the appropriate boundary. */
47926f60 8316
252b5132
RH		 8317valueT
8318md_section_align (segment, size)
ab9da554 8319 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8320 valueT size;
8321{
4c63da97
AM		 8322#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8323 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8324 {
8325 /* For a.out, force the section size to be aligned. If we don't do
8326 this, BFD will align it for us, but it will not write out the
8327 final bytes of the section. This may be a bug in BFD, but it is
8328 easier to fix it here since that is how the other a.out targets
8329 work. */
8330 int align;
8331
8332 align = bfd_get_section_alignment (stdoutput, segment);
8333 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8334 }
252b5132
RH		 8335#endif
8336
8337 return size;
8338}
8339
8340/* On the i386, PC-relative offsets are relative to the start of the
8341 next instruction. That is, the address of the offset, plus its
8342 size, since the offset is always the last part of the insn. */
8343
8344long
e3bb37b5 8345md_pcrel_from (fixS *fixP)
252b5132
RH		 8346{
8347 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8348}
8349
8350#ifndef I386COFF
8351
8352static void
e3bb37b5 8353s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8354{
29b0f896 8355 int temp;
252b5132 8356
8a75718c
JB		 8357#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8358 if (IS_ELF)
8359 obj_elf_section_change_hook ();
8360#endif
252b5132
RH		 8361 temp = get_absolute_expression ();
8362 subseg_set (bss_section, (subsegT) temp);
8363 demand_empty_rest_of_line ();
8364}
8365
8366#endif
8367
252b5132 8368void
e3bb37b5 8369i386_validate_fix (fixS *fixp)
252b5132
RH		 8370{
8371 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8372 {
23df1078
JH		 8373 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8374 {
4fa24527 8375 if (!object_64bit)
23df1078
JH		 8376 abort ();
8377 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8378 }
8379 else
8380 {
4fa24527 8381 if (!object_64bit)
d6ab8113
JB		 8382 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8383 else
8384 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8385 }
252b5132
RH		 8386 fixp->fx_subsy = 0;
8387 }
8388}
8389
252b5132
RH		 8390arelent *
8391tc_gen_reloc (section, fixp)
ab9da554 8392 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8393 fixS *fixp;
8394{
8395 arelent *rel;
8396 bfd_reloc_code_real_type code;
8397
8398 switch (fixp->fx_r_type)
8399 {
3e73aa7c
JH		 8400 case BFD_RELOC_X86_64_PLT32:
8401 case BFD_RELOC_X86_64_GOT32:
8402 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8403 case BFD_RELOC_386_PLT32:
8404 case BFD_RELOC_386_GOT32:
8405 case BFD_RELOC_386_GOTOFF:
8406 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8407 case BFD_RELOC_386_TLS_GD:
8408 case BFD_RELOC_386_TLS_LDM:
8409 case BFD_RELOC_386_TLS_LDO_32:
8410 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8411 case BFD_RELOC_386_TLS_IE:
8412 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8413 case BFD_RELOC_386_TLS_LE_32:
8414 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8415 case BFD_RELOC_386_TLS_GOTDESC:
8416 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8417 case BFD_RELOC_X86_64_TLSGD:
8418 case BFD_RELOC_X86_64_TLSLD:
8419 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8420 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8421 case BFD_RELOC_X86_64_GOTTPOFF:
8422 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8423 case BFD_RELOC_X86_64_TPOFF64:
8424 case BFD_RELOC_X86_64_GOTOFF64:
8425 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8426 case BFD_RELOC_X86_64_GOT64:
8427 case BFD_RELOC_X86_64_GOTPCREL64:
8428 case BFD_RELOC_X86_64_GOTPC64:
8429 case BFD_RELOC_X86_64_GOTPLT64:
8430 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8431 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8432 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8433 case BFD_RELOC_RVA:
8434 case BFD_RELOC_VTABLE_ENTRY:
8435 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8436#ifdef TE_PE
8437 case BFD_RELOC_32_SECREL:
8438#endif
252b5132
RH		 8439 code = fixp->fx_r_type;
8440 break;
dbbaec26
L		 8441 case BFD_RELOC_X86_64_32S:
8442 if (!fixp->fx_pcrel)
8443 {
8444 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8445 code = fixp->fx_r_type;
8446 break;
8447 }
252b5132 8448 default:
93382f6d 8449 if (fixp->fx_pcrel)
252b5132 8450 {
93382f6d
AM		 8451 switch (fixp->fx_size)
8452 {
8453 default:
b091f402
AM		 8454 as_bad_where (fixp->fx_file, fixp->fx_line,
8455 _("can not do %d byte pc-relative relocation"),
8456 fixp->fx_size);
93382f6d
AM		 8457 code = BFD_RELOC_32_PCREL;
8458 break;
8459 case 1: code = BFD_RELOC_8_PCREL; break;
8460 case 2: code = BFD_RELOC_16_PCREL; break;
8461 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8462#ifdef BFD64
8463 case 8: code = BFD_RELOC_64_PCREL; break;
8464#endif
93382f6d
AM		 8465 }
8466 }
8467 else
8468 {
8469 switch (fixp->fx_size)
8470 {
8471 default:
b091f402
AM		 8472 as_bad_where (fixp->fx_file, fixp->fx_line,
8473 _("can not do %d byte relocation"),
8474 fixp->fx_size);
93382f6d
AM		 8475 code = BFD_RELOC_32;
8476 break;
8477 case 1: code = BFD_RELOC_8; break;
8478 case 2: code = BFD_RELOC_16; break;
8479 case 4: code = BFD_RELOC_32; break;
937149dd 8480#ifdef BFD64
3e73aa7c 8481 case 8: code = BFD_RELOC_64; break;
937149dd 8482#endif
93382f6d 8483 }
252b5132
RH		 8484 }
8485 break;
8486 }
252b5132 8487
d182319b
JB		 8488 if ((code == BFD_RELOC_32
8489 || code == BFD_RELOC_32_PCREL
8490 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8491 && GOT_symbol
8492 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8493 {
4fa24527 8494 if (!object_64bit)
d6ab8113
JB		 8495 code = BFD_RELOC_386_GOTPC;
8496 else
8497 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8498 }
7b81dfbb
AJ		 8499 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8500 && GOT_symbol
8501 && fixp->fx_addsy == GOT_symbol)
8502 {
8503 code = BFD_RELOC_X86_64_GOTPC64;
8504 }
252b5132
RH		 8505
8506 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8507 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8508 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8509
8510 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8511
3e73aa7c
JH		 8512 if (!use_rela_relocations)
8513 {
8514 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8515 vtable entry to be used in the relocation's section offset. */
8516 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8517 rel->address = fixp->fx_offset;
252b5132 8518
c6682705 8519 rel->addend = 0;
3e73aa7c
JH		 8520 }
8521 /* Use the rela in 64bit mode. */
252b5132 8522 else
3e73aa7c 8523 {
062cd5e7
AS		 8524 if (!fixp->fx_pcrel)
8525 rel->addend = fixp->fx_offset;
8526 else
8527 switch (code)
8528 {
8529 case BFD_RELOC_X86_64_PLT32:
8530 case BFD_RELOC_X86_64_GOT32:
8531 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8532 case BFD_RELOC_X86_64_TLSGD:
8533 case BFD_RELOC_X86_64_TLSLD:
8534 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8535 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8536 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8537 rel->addend = fixp->fx_offset - fixp->fx_size;
8538 break;
8539 default:
8540 rel->addend = (section->vma
8541 - fixp->fx_size
8542 + fixp->fx_addnumber
8543 + md_pcrel_from (fixp));
8544 break;
8545 }
3e73aa7c
JH		 8546 }
8547
252b5132
RH		 8548 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8549 if (rel->howto == NULL)
8550 {
8551 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8552 _("cannot represent relocation type %s"),
252b5132
RH		 8553 bfd_get_reloc_code_name (code));
8554 /* Set howto to a garbage value so that we can keep going. */
8555 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8556 assert (rel->howto != NULL);
8557 }
8558
8559 return rel;
8560}
8561
64a0c779
DN		 8562\f
8563/* Parse operands using Intel syntax. This implements a recursive descent
8564 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8565 Programmer's Guide.
8566
8567 FIXME: We do not recognize the full operand grammar defined in the MASM
8568 documentation. In particular, all the structure/union and
8569 high-level macro operands are missing.
8570
8571 Uppercase words are terminals, lower case words are non-terminals.
8572 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8573 bars '|' denote choices. Most grammar productions are implemented in
8574 functions called 'intel_<production>'.
8575
8576 Initial production is 'expr'.
8577
9306ca4a 8578 addOp + | -
64a0c779
DN		 8579
8580 alpha [a-zA-Z]
8581
9306ca4a
JB		 8582 binOp & | AND | \| | OR | ^ | XOR
8583
64a0c779
DN		 8584 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8585
8586 constant digits [[ radixOverride ]]
8587
c0f3af97 8588 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8589
8590 digits decdigit
b77a7acd
AJ		 8591 | digits decdigit
8592 | digits hexdigit
64a0c779
DN		 8593
8594 decdigit [0-9]
8595
9306ca4a
JB		 8596 e04 e04 addOp e05
8597 | e05
8598
8599 e05 e05 binOp e06
b77a7acd 8600 | e06
64a0c779
DN		 8601
8602 e06 e06 mulOp e09
b77a7acd 8603 | e09
64a0c779
DN		 8604
8605 e09 OFFSET e10
a724f0f4
JB		 8606 | SHORT e10
8607 | + e10
8608 | - e10
9306ca4a
JB		 8609 | ~ e10
8610 | NOT e10
64a0c779
DN		 8611 | e09 PTR e10
8612 | e09 : e10
8613 | e10
8614
8615 e10 e10 [ expr ]
b77a7acd 8616 | e11
64a0c779
DN		 8617
8618 e11 ( expr )
b77a7acd 8619 | [ expr ]
64a0c779
DN		 8620 | constant
8621 | dataType
8622 | id
8623 | $
8624 | register
8625
a724f0f4 8626 => expr expr cmpOp e04
9306ca4a 8627 | e04
64a0c779
DN		 8628
8629 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8630 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8631
8632 hexdigit a | b | c | d | e | f
b77a7acd 8633 | A | B | C | D | E | F
64a0c779
DN		 8634
8635 id alpha
b77a7acd 8636 | id alpha
64a0c779
DN		 8637 | id decdigit
8638
9306ca4a 8639 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8640
8641 quote " | '
8642
8643 register specialRegister
b77a7acd 8644 | gpRegister
64a0c779
DN		 8645 | byteRegister
8646
8647 segmentRegister CS | DS | ES | FS | GS | SS
8648
9306ca4a 8649 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8650 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8651 | TR3 | TR4 | TR5 | TR6 | TR7
8652
64a0c779
DN		 8653 We simplify the grammar in obvious places (e.g., register parsing is
8654 done by calling parse_register) and eliminate immediate left recursion
8655 to implement a recursive-descent parser.
8656
a724f0f4
JB		 8657 expr e04 expr'
8658
8659 expr' cmpOp e04 expr'
8660 | Empty
9306ca4a
JB		 8661
8662 e04 e05 e04'
8663
8664 e04' addOp e05 e04'
8665 | Empty
64a0c779
DN		 8666
8667 e05 e06 e05'
8668
9306ca4a 8669 e05' binOp e06 e05'
b77a7acd 8670 | Empty
64a0c779
DN		 8671
8672 e06 e09 e06'
8673
8674 e06' mulOp e09 e06'
b77a7acd 8675 | Empty
64a0c779
DN		 8676
8677 e09 OFFSET e10 e09'
a724f0f4
JB		 8678 | SHORT e10'
8679 | + e10'
8680 | - e10'
8681 | ~ e10'
8682 | NOT e10'
b77a7acd 8683 | e10 e09'
64a0c779
DN		 8684
8685 e09' PTR e10 e09'
b77a7acd 8686 | : e10 e09'
64a0c779
DN		 8687 | Empty
8688
8689 e10 e11 e10'
8690
8691 e10' [ expr ] e10'
b77a7acd 8692 | Empty
64a0c779
DN		 8693
8694 e11 ( expr )
b77a7acd 8695 | [ expr ]
64a0c779
DN		 8696 | BYTE
8697 | WORD
8698 | DWORD
9306ca4a 8699 | FWORD
64a0c779 8700 | QWORD
9306ca4a
JB		 8701 | TBYTE
8702 | OWORD
8703 | XMMWORD
c0f3af97 8704 | YMMWORD
64a0c779
DN		 8705 | .
8706 | $
8707 | register
8708 | id
8709 | constant */
8710
8711/* Parsing structure for the intel syntax parser. Used to implement the
8712 semantic actions for the operand grammar. */
8713struct intel_parser_s
8714 {
8715 char *op_string; /* The string being parsed. */
8716 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8717 int op_modifier; /* Operand modifier. */
64a0c779 8718 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8719 int in_offset; /* >=1 if parsing operand of offset. */
8720 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8721 const reg_entry *reg; /* Last register reference found. */
8722 char *disp; /* Displacement string being built. */
a724f0f4 8723 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8724 };
8725
8726static struct intel_parser_s intel_parser;
8727
8728/* Token structure for parsing intel syntax. */
8729struct intel_token
8730 {
8731 int code; /* Token code. */
8732 const reg_entry *reg; /* Register entry for register tokens. */
8733 char *str; /* String representation. */
8734 };
8735
8736static struct intel_token cur_token, prev_token;
8737
50705ef4
AM		 8738/* Token codes for the intel parser. Since T_SHORT is already used
8739 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8740#define T_NIL -1
8741#define T_CONST 1
8742#define T_REG 2
8743#define T_BYTE 3
8744#define T_WORD 4
9306ca4a
JB		 8745#define T_DWORD 5
8746#define T_FWORD 6
8747#define T_QWORD 7
8748#define T_TBYTE 8
8749#define T_XMMWORD 9
50705ef4 8750#undef T_SHORT
9306ca4a
JB		 8751#define T_SHORT 10
8752#define T_OFFSET 11
8753#define T_PTR 12
8754#define T_ID 13
8755#define T_SHL 14
8756#define T_SHR 15
c0f3af97 8757#define T_YMMWORD 16
64a0c779
DN		 8758
8759/* Prototypes for intel parser functions. */
e3bb37b5
L		 8760static int intel_match_token (int);
8761static void intel_putback_token (void);
8762static void intel_get_token (void);
8763static int intel_expr (void);
8764static int intel_e04 (void);
8765static int intel_e05 (void);
8766static int intel_e06 (void);
8767static int intel_e09 (void);
8768static int intel_e10 (void);
8769static int intel_e11 (void);
64a0c779 8770
64a0c779 8771static int
e3bb37b5 8772i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8773{
8774 int ret;
8775 char *p;
8776
a724f0f4
JB		 8777 p = intel_parser.op_string = xstrdup (operand_string);
8778 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8779
8780 for (;;)
64a0c779 8781 {
a724f0f4
JB		 8782 /* Initialize token holders. */
8783 cur_token.code = prev_token.code = T_NIL;
8784 cur_token.reg = prev_token.reg = NULL;
8785 cur_token.str = prev_token.str = NULL;
8786
8787 /* Initialize parser structure. */
8788 intel_parser.got_a_float = got_a_float;
8789 intel_parser.op_modifier = 0;
8790 intel_parser.is_mem = 0;
8791 intel_parser.in_offset = 0;
8792 intel_parser.in_bracket = 0;
8793 intel_parser.reg = NULL;
8794 intel_parser.disp[0] = '\0';
8795 intel_parser.next_operand = NULL;
8796
8797 /* Read the first token and start the parser. */
8798 intel_get_token ();
8799 ret = intel_expr ();
8800
8801 if (!ret)
8802 break;
8803
9306ca4a
JB		 8804 if (cur_token.code != T_NIL)
8805 {
8806 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8807 current_templates->start->name, cur_token.str);
8808 ret = 0;
8809 }
64a0c779
DN		 8810 /* If we found a memory reference, hand it over to i386_displacement
8811 to fill in the rest of the operand fields. */
9306ca4a 8812 else if (intel_parser.is_mem)
64a0c779
DN		 8813 {
8814 if ((i.mem_operands == 1
40fb9820 8815 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8816 || i.mem_operands == 2)
8817 {
8818 as_bad (_("too many memory references for '%s'"),
8819 current_templates->start->name);
8820 ret = 0;
8821 }
8822 else
8823 {
8824 char *s = intel_parser.disp;
5c07affc 8825 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 8826 i.mem_operands++;
8827
a724f0f4
JB		 8828 if (!quiet_warnings && intel_parser.is_mem < 0)
8829 /* See the comments in intel_bracket_expr. */
8830 as_warn (_("Treating `%s' as memory reference"), operand_string);
8831
64a0c779
DN		 8832 /* Add the displacement expression. */
8833 if (*s != '\0')
a4622f40
AM		 8834 ret = i386_displacement (s, s + strlen (s));
8835 if (ret)
a724f0f4
JB		 8836 {
8837 /* Swap base and index in 16-bit memory operands like
8838 [si+bx]. Since i386_index_check is also used in AT&T
8839 mode we have to do that here. */
8840 if (i.base_reg
8841 && i.index_reg
40fb9820
L		 8842 && i.base_reg->reg_type.bitfield.reg16
8843 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8844 && i.base_reg->reg_num >= 6
8845 && i.index_reg->reg_num < 6)
8846 {
8847 const reg_entry *base = i.index_reg;
8848
8849 i.index_reg = i.base_reg;
8850 i.base_reg = base;
8851 }
8852 ret = i386_index_check (operand_string);
8853 }
64a0c779
DN		 8854 }
8855 }
8856
8857 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8858 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8859 || intel_parser.reg == NULL)
b7240065
JB		 8860 {
8861 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8862 {
8863 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8864 as_warn (_("Segment override ignored"));
8865 i.seg[i.mem_operands] = NULL;
8866 }
8867 ret = i386_immediate (intel_parser.disp);
8868 }
a724f0f4
JB		 8869
8870 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8871 ret = 0;
a724f0f4
JB		 8872 if (!ret || !intel_parser.next_operand)
8873 break;
8874 intel_parser.op_string = intel_parser.next_operand;
8875 this_operand = i.operands++;
7d5e4556 8876 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8877 }
8878
8879 free (p);
8880 free (intel_parser.disp);
8881
8882 return ret;
8883}
8884
a724f0f4
JB		 8885#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8886
8887/* expr e04 expr'
8888
8889 expr' cmpOp e04 expr'
8890 | Empty */
64a0c779 8891static int
e3bb37b5 8892intel_expr (void)
64a0c779 8893{
a724f0f4
JB		 8894 /* XXX Implement the comparison operators. */
8895 return intel_e04 ();
9306ca4a
JB		 8896}
8897
a724f0f4 8898/* e04 e05 e04'
9306ca4a 8899
a724f0f4 8900 e04' addOp e05 e04'
9306ca4a
JB		 8901 | Empty */
8902static int
e3bb37b5 8903intel_e04 (void)
9306ca4a 8904{
a724f0f4 8905 int nregs = -1;
9306ca4a 8906
a724f0f4 8907 for (;;)
9306ca4a 8908 {
a724f0f4
JB		 8909 if (!intel_e05())
8910 return 0;
9306ca4a 8911
a724f0f4
JB		 8912 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8913 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 8914
a724f0f4
JB		 8915 if (cur_token.code == '+')
8916 nregs = -1;
8917 else if (cur_token.code == '-')
8918 nregs = NUM_ADDRESS_REGS;
8919 else
8920 return 1;
64a0c779 8921
a724f0f4
JB		 8922 strcat (intel_parser.disp, cur_token.str);
8923 intel_match_token (cur_token.code);
8924 }
64a0c779
DN		 8925}
8926
64a0c779
DN		 8927/* e05 e06 e05'
8928
9306ca4a 8929 e05' binOp e06 e05'
64a0c779
DN		 8930 | Empty */
8931static int
e3bb37b5 8932intel_e05 (void)
64a0c779 8933{
a724f0f4 8934 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8935
a724f0f4 8936 for (;;)
64a0c779 8937 {
a724f0f4
JB		 8938 if (!intel_e06())
8939 return 0;
8940
4eed87de
AM		 8941 if (cur_token.code == '&'
8942 || cur_token.code == '|'
8943 || cur_token.code == '^')
a724f0f4
JB		 8944 {
8945 char str[2];
8946
8947 str[0] = cur_token.code;
8948 str[1] = 0;
8949 strcat (intel_parser.disp, str);
8950 }
8951 else
8952 break;
9306ca4a 8953
64a0c779
DN		 8954 intel_match_token (cur_token.code);
8955
a724f0f4
JB		 8956 if (nregs < 0)
8957 nregs = ~nregs;
64a0c779 8958 }
a724f0f4
JB		 8959 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8960 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8961 return 1;
4a1805b1 8962}
64a0c779
DN		 8963
8964/* e06 e09 e06'
8965
8966 e06' mulOp e09 e06'
b77a7acd 8967 | Empty */
64a0c779 8968static int
e3bb37b5 8969intel_e06 (void)
64a0c779 8970{
a724f0f4 8971 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8972
a724f0f4 8973 for (;;)
64a0c779 8974 {
a724f0f4
JB		 8975 if (!intel_e09())
8976 return 0;
9306ca4a 8977
4eed87de
AM		 8978 if (cur_token.code == '*'
8979 || cur_token.code == '/'
8980 || cur_token.code == '%')
a724f0f4
JB		 8981 {
8982 char str[2];
9306ca4a 8983
a724f0f4
JB		 8984 str[0] = cur_token.code;
8985 str[1] = 0;
8986 strcat (intel_parser.disp, str);
8987 }
8988 else if (cur_token.code == T_SHL)
8989 strcat (intel_parser.disp, "<<");
8990 else if (cur_token.code == T_SHR)
8991 strcat (intel_parser.disp, ">>");
8992 else
8993 break;
9306ca4a 8994
64e74474 8995 intel_match_token (cur_token.code);
64a0c779 8996
a724f0f4
JB		 8997 if (nregs < 0)
8998 nregs = ~nregs;
64a0c779 8999 }
a724f0f4
JB		 9000 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9001 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9002 return 1;
64a0c779
DN		 9003}
9004
a724f0f4
JB		 9005/* e09 OFFSET e09
9006 | SHORT e09
9007 | + e09
9008 | - e09
9009 | ~ e09
9010 | NOT e09
9306ca4a
JB		 9011 | e10 e09'
9012
64a0c779 9013 e09' PTR e10 e09'
b77a7acd 9014 | : e10 e09'
64a0c779
DN		 9015 | Empty */
9016static int
e3bb37b5 9017intel_e09 (void)
64a0c779 9018{
a724f0f4
JB		 9019 int nregs = ~NUM_ADDRESS_REGS;
9020 int in_offset = 0;
9021
9022 for (;;)
64a0c779 9023 {
a724f0f4
JB		 9024 /* Don't consume constants here. */
9025 if (cur_token.code == '+' || cur_token.code == '-')
9026 {
9027 /* Need to look one token ahead - if the next token
9028 is a constant, the current token is its sign. */
9029 int next_code;
9030
9031 intel_match_token (cur_token.code);
9032 next_code = cur_token.code;
9033 intel_putback_token ();
9034 if (next_code == T_CONST)
9035 break;
9036 }
9037
9038 /* e09 OFFSET e09 */
9039 if (cur_token.code == T_OFFSET)
9040 {
9041 if (!in_offset++)
9042 ++intel_parser.in_offset;
9043 }
9044
9045 /* e09 SHORT e09 */
9046 else if (cur_token.code == T_SHORT)
9047 intel_parser.op_modifier |= 1 << T_SHORT;
9048
9049 /* e09 + e09 */
9050 else if (cur_token.code == '+')
9051 strcat (intel_parser.disp, "+");
9052
9053 /* e09 - e09
9054 | ~ e09
9055 | NOT e09 */
9056 else if (cur_token.code == '-' || cur_token.code == '~')
9057 {
9058 char str[2];
64a0c779 9059
a724f0f4
JB		 9060 if (nregs < 0)
9061 nregs = ~nregs;
9062 str[0] = cur_token.code;
9063 str[1] = 0;
9064 strcat (intel_parser.disp, str);
9065 }
9066
9067 /* e09 e10 e09' */
9068 else
9069 break;
9070
9071 intel_match_token (cur_token.code);
64a0c779
DN		 9072 }
9073
a724f0f4 9074 for (;;)
9306ca4a 9075 {
a724f0f4
JB		 9076 if (!intel_e10 ())
9077 return 0;
9306ca4a 9078
a724f0f4
JB		 9079 /* e09' PTR e10 e09' */
9080 if (cur_token.code == T_PTR)
9081 {
9082 char suffix;
9306ca4a 9083
a724f0f4 9084 if (prev_token.code == T_BYTE)
7d5e4556
L		 9085 {
9086 suffix = BYTE_MNEM_SUFFIX;
9087 i.types[this_operand].bitfield.byte = 1;
9088 }
9306ca4a 9089
a724f0f4
JB		 9090 else if (prev_token.code == T_WORD)
9091 {
34b772a6
JB		 9092 if ((current_templates->start->name[0] == 'l'
9093 && current_templates->start->name[2] == 's'
9094 && current_templates->start->name[3] == 0)
9095 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9096 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9097 else if (intel_parser.got_a_float == 2) /* "fi..." */
9098 suffix = SHORT_MNEM_SUFFIX;
9099 else
9100 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9101 i.types[this_operand].bitfield.word = 1;
a724f0f4 9102 }
64a0c779 9103
a724f0f4
JB		 9104 else if (prev_token.code == T_DWORD)
9105 {
34b772a6
JB		 9106 if ((current_templates->start->name[0] == 'l'
9107 && current_templates->start->name[2] == 's'
9108 && current_templates->start->name[3] == 0)
9109 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9110 suffix = WORD_MNEM_SUFFIX;
9111 else if (flag_code == CODE_16BIT
40fb9820
L		 9112 && (current_templates->start->opcode_modifier.jump
9113 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9114 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9115 else if (intel_parser.got_a_float == 1) /* "f..." */
9116 suffix = SHORT_MNEM_SUFFIX;
9117 else
9118 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9119 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9120 }
9306ca4a 9121
a724f0f4
JB		 9122 else if (prev_token.code == T_FWORD)
9123 {
9124 if (current_templates->start->name[0] == 'l'
9125 && current_templates->start->name[2] == 's'
9126 && current_templates->start->name[3] == 0)
9127 suffix = LONG_MNEM_SUFFIX;
9128 else if (!intel_parser.got_a_float)
9129 {
9130 if (flag_code == CODE_16BIT)
9131 add_prefix (DATA_PREFIX_OPCODE);
9132 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9133 }
9134 else
9135 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9136 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9137 }
64a0c779 9138
a724f0f4
JB		 9139 else if (prev_token.code == T_QWORD)
9140 {
34b772a6
JB		 9141 if (current_templates->start->base_opcode == 0x62 /* bound */
9142 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9143 suffix = LONG_MNEM_SUFFIX;
9144 else
34b772a6 9145 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9146 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9147 }
64a0c779 9148
a724f0f4
JB		 9149 else if (prev_token.code == T_TBYTE)
9150 {
9151 if (intel_parser.got_a_float == 1)
9152 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9153 else
9154 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9155 }
9306ca4a 9156
a724f0f4 9157 else if (prev_token.code == T_XMMWORD)
9306ca4a 9158 {
582d5edd 9159 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9160 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9161 }
64a0c779 9162
c0f3af97
L		 9163 else if (prev_token.code == T_YMMWORD)
9164 {
9165 suffix = YMMWORD_MNEM_SUFFIX;
9166 i.types[this_operand].bitfield.ymmword = 1;
9167 }
9168
f16b83df 9169 else
a724f0f4
JB		 9170 {
9171 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9172 return 0;
9173 }
9174
7d5e4556
L		 9175 i.types[this_operand].bitfield.unspecified = 0;
9176
435acd52
JB		 9177 /* Operands for jump/call using 'ptr' notation denote absolute
9178 addresses. */
40fb9820
L		 9179 if (current_templates->start->opcode_modifier.jump
9180 || current_templates->start->opcode_modifier.jumpdword)
9181 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9182
a724f0f4
JB		 9183 if (current_templates->start->base_opcode == 0x8d /* lea */)
9184 ;
9185 else if (!i.suffix)
9186 i.suffix = suffix;
9187 else if (i.suffix != suffix)
9188 {
9189 as_bad (_("Conflicting operand modifiers"));
9190 return 0;
9191 }
64a0c779 9192
9306ca4a
JB		 9193 }
9194
a724f0f4
JB		 9195 /* e09' : e10 e09' */
9196 else if (cur_token.code == ':')
9306ca4a 9197 {
a724f0f4
JB		 9198 if (prev_token.code != T_REG)
9199 {
9200 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9201 segment/group identifier (which we don't have), using comma
9202 as the operand separator there is even less consistent, since
9203 there all branches only have a single operand. */
9204 if (this_operand != 0
9205 || intel_parser.in_offset
9206 || intel_parser.in_bracket
40fb9820
L		 9207 || (!current_templates->start->opcode_modifier.jump
9208 && !current_templates->start->opcode_modifier.jumpdword
9209 && !current_templates->start->opcode_modifier.jumpintersegment
9210 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9211 return intel_match_token (T_NIL);
9212 /* Remember the start of the 2nd operand and terminate 1st
9213 operand here.
9214 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9215 another expression), but it gets at least the simplest case
9216 (a plain number or symbol on the left side) right. */
9217 intel_parser.next_operand = intel_parser.op_string;
9218 *--intel_parser.op_string = '\0';
9219 return intel_match_token (':');
9220 }
9306ca4a 9221 }
64a0c779 9222
a724f0f4 9223 /* e09' Empty */
64a0c779 9224 else
a724f0f4 9225 break;
64a0c779 9226
a724f0f4
JB		 9227 intel_match_token (cur_token.code);
9228
9229 }
9230
9231 if (in_offset)
9232 {
9233 --intel_parser.in_offset;
9234 if (nregs < 0)
9235 nregs = ~nregs;
9236 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9237 {
a724f0f4 9238 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9239 return 0;
9240 }
a724f0f4
JB		 9241 intel_parser.op_modifier |= 1 << T_OFFSET;
9242 }
9306ca4a 9243
a724f0f4
JB		 9244 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9245 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9246 return 1;
9247}
64a0c779 9248
a724f0f4 9249static int
e3bb37b5 9250intel_bracket_expr (void)
a724f0f4
JB		 9251{
9252 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9253 const char *start = intel_parser.op_string;
9254 int len;
9255
9256 if (i.op[this_operand].regs)
9257 return intel_match_token (T_NIL);
9258
9259 intel_match_token ('[');
9260
9261 /* Mark as a memory operand only if it's not already known to be an
9262 offset expression. If it's an offset expression, we need to keep
9263 the brace in. */
9264 if (!intel_parser.in_offset)
9265 {
9266 ++intel_parser.in_bracket;
435acd52
JB		 9267
9268 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9269 if (current_templates->start->opcode_modifier.jump
9270 || current_templates->start->opcode_modifier.jumpdword)
9271 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9272
a724f0f4
JB		 9273 /* Unfortunately gas always diverged from MASM in a respect that can't
9274 be easily fixed without risking to break code sequences likely to be
9275 encountered (the testsuite even check for this): MASM doesn't consider
9276 an expression inside brackets unconditionally as a memory reference.
9277 When that is e.g. a constant, an offset expression, or the sum of the
9278 two, this is still taken as a constant load. gas, however, always
9279 treated these as memory references. As a compromise, we'll try to make
9280 offset expressions inside brackets work the MASM way (since that's
9281 less likely to be found in real world code), but make constants alone
9282 continue to work the traditional gas way. In either case, issue a
9283 warning. */
9284 intel_parser.op_modifier &= ~was_offset;
64a0c779 9285 }
a724f0f4 9286 else
64e74474 9287 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9288
9289 /* Add a '+' to the displacement string if necessary. */
9290 if (*intel_parser.disp != '\0'
9291 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9292 strcat (intel_parser.disp, "+");
64a0c779 9293
a724f0f4
JB		 9294 if (intel_expr ()
9295 && (len = intel_parser.op_string - start - 1,
9296 intel_match_token (']')))
64a0c779 9297 {
a724f0f4
JB		 9298 /* Preserve brackets when the operand is an offset expression. */
9299 if (intel_parser.in_offset)
9300 strcat (intel_parser.disp, "]");
9301 else
9302 {
9303 --intel_parser.in_bracket;
9304 if (i.base_reg || i.index_reg)
9305 intel_parser.is_mem = 1;
9306 if (!intel_parser.is_mem)
9307 {
9308 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9309 /* Defer the warning until all of the operand was parsed. */
9310 intel_parser.is_mem = -1;
9311 else if (!quiet_warnings)
4eed87de
AM		 9312 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9313 len, start, len, start);
a724f0f4
JB		 9314 }
9315 }
9316 intel_parser.op_modifier |= was_offset;
64a0c779 9317
a724f0f4 9318 return 1;
64a0c779 9319 }
a724f0f4 9320 return 0;
64a0c779
DN		 9321}
9322
9323/* e10 e11 e10'
9324
9325 e10' [ expr ] e10'
b77a7acd 9326 | Empty */
64a0c779 9327static int
e3bb37b5 9328intel_e10 (void)
64a0c779 9329{
a724f0f4
JB		 9330 if (!intel_e11 ())
9331 return 0;
64a0c779 9332
a724f0f4 9333 while (cur_token.code == '[')
64a0c779 9334 {
a724f0f4 9335 if (!intel_bracket_expr ())
21d6c4af 9336 return 0;
64a0c779
DN		 9337 }
9338
a724f0f4 9339 return 1;
64a0c779
DN		 9340}
9341
64a0c779 9342/* e11 ( expr )
b77a7acd 9343 | [ expr ]
64a0c779
DN		 9344 | BYTE
9345 | WORD
9346 | DWORD
9306ca4a 9347 | FWORD
64a0c779 9348 | QWORD
9306ca4a
JB		 9349 | TBYTE
9350 | OWORD
9351 | XMMWORD
c0f3af97 9352 | YMMWORD
4a1805b1 9353 | $
64a0c779
DN		 9354 | .
9355 | register
9356 | id
9357 | constant */
9358static int
e3bb37b5 9359intel_e11 (void)
64a0c779 9360{
a724f0f4 9361 switch (cur_token.code)
64a0c779 9362 {
a724f0f4
JB		 9363 /* e11 ( expr ) */
9364 case '(':
64a0c779
DN		 9365 intel_match_token ('(');
9366 strcat (intel_parser.disp, "(");
9367
9368 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9369 {
9370 strcat (intel_parser.disp, ")");
9371 return 1;
9372 }
a724f0f4 9373 return 0;
4a1805b1 9374
a724f0f4
JB		 9375 /* e11 [ expr ] */
9376 case '[':
a724f0f4 9377 return intel_bracket_expr ();
64a0c779 9378
a724f0f4
JB		 9379 /* e11 $
9380 | . */
9381 case '.':
64a0c779
DN		 9382 strcat (intel_parser.disp, cur_token.str);
9383 intel_match_token (cur_token.code);
21d6c4af
DN		 9384
9385 /* Mark as a memory operand only if it's not already known to be an
9386 offset expression. */
a724f0f4 9387 if (!intel_parser.in_offset)
21d6c4af 9388 intel_parser.is_mem = 1;
64a0c779
DN		 9389
9390 return 1;
64a0c779 9391
a724f0f4
JB		 9392 /* e11 register */
9393 case T_REG:
9394 {
9395 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9396
a724f0f4 9397 intel_match_token (T_REG);
64a0c779 9398
a724f0f4
JB		 9399 /* Check for segment change. */
9400 if (cur_token.code == ':')
9401 {
40fb9820
L		 9402 if (!reg->reg_type.bitfield.sreg2
9403 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9404 {
4eed87de
AM		 9405 as_bad (_("`%s' is not a valid segment register"),
9406 reg->reg_name);
a724f0f4
JB		 9407 return 0;
9408 }
b7240065
JB		 9409 else if (i.mem_operands >= 2)
9410 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9411 else if (i.seg[i.mem_operands])
9412 as_warn (_("Extra segment override ignored"));
9413 else
9414 {
9415 if (!intel_parser.in_offset)
9416 intel_parser.is_mem = 1;
9417 switch (reg->reg_num)
9418 {
9419 case 0:
9420 i.seg[i.mem_operands] = &es;
9421 break;
9422 case 1:
9423 i.seg[i.mem_operands] = &cs;
9424 break;
9425 case 2:
9426 i.seg[i.mem_operands] = &ss;
9427 break;
9428 case 3:
9429 i.seg[i.mem_operands] = &ds;
9430 break;
9431 case 4:
9432 i.seg[i.mem_operands] = &fs;
9433 break;
9434 case 5:
9435 i.seg[i.mem_operands] = &gs;
9436 break;
9437 }
9438 }
9439 }
64a0c779 9440
b7240065
JB		 9441 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9442 {
9443 as_bad (_("cannot use `FLAT' here"));
9444 return 0;
9445 }
9446
a724f0f4
JB		 9447 /* Not a segment register. Check for register scaling. */
9448 else if (cur_token.code == '*')
9449 {
9450 if (!intel_parser.in_bracket)
9451 {
9452 as_bad (_("Register scaling only allowed in memory operands"));
9453 return 0;
9454 }
64a0c779 9455
40fb9820 9456 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9457 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9458 else if (i.index_reg)
9459 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9460
a724f0f4
JB		 9461 /* What follows must be a valid scale. */
9462 intel_match_token ('*');
9463 i.index_reg = reg;
40fb9820 9464 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9465
a724f0f4
JB		 9466 /* Set the scale after setting the register (otherwise,
9467 i386_scale will complain) */
9468 if (cur_token.code == '+' || cur_token.code == '-')
9469 {
9470 char *str, sign = cur_token.code;
9471 intel_match_token (cur_token.code);
9472 if (cur_token.code != T_CONST)
9473 {
9474 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9475 cur_token.str);
9476 return 0;
9477 }
9478 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9479 strcpy (str + 1, cur_token.str);
9480 *str = sign;
9481 if (!i386_scale (str))
9482 return 0;
9483 free (str);
9484 }
9485 else if (!i386_scale (cur_token.str))
64a0c779 9486 return 0;
a724f0f4
JB		 9487 intel_match_token (cur_token.code);
9488 }
64a0c779 9489
a724f0f4
JB		 9490 /* No scaling. If this is a memory operand, the register is either a
9491 base register (first occurrence) or an index register (second
9492 occurrence). */
7b0441f6 9493 else if (intel_parser.in_bracket)
a724f0f4 9494 {
64a0c779 9495
a724f0f4
JB		 9496 if (!i.base_reg)
9497 i.base_reg = reg;
9498 else if (!i.index_reg)
9499 i.index_reg = reg;
9500 else
9501 {
9502 as_bad (_("Too many register references in memory operand"));
9503 return 0;
9504 }
64a0c779 9505
40fb9820 9506 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9507 }
4a1805b1 9508
4d1bb795
JB		 9509 /* It's neither base nor index. */
9510 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9511 {
40fb9820
L		 9512 i386_operand_type temp = reg->reg_type;
9513 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9514 i.types[this_operand] = operand_type_or (i.types[this_operand],
9515 temp);
7d5e4556 9516 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9517 i.op[this_operand].regs = reg;
9518 i.reg_operands++;
9519 }
9520 else
9521 {
9522 as_bad (_("Invalid use of register"));
9523 return 0;
9524 }
64a0c779 9525
a724f0f4
JB		 9526 /* Since registers are not part of the displacement string (except
9527 when we're parsing offset operands), we may need to remove any
9528 preceding '+' from the displacement string. */
9529 if (*intel_parser.disp != '\0'
9530 && !intel_parser.in_offset)
9531 {
9532 char *s = intel_parser.disp;
9533 s += strlen (s) - 1;
9534 if (*s == '+')
9535 *s = '\0';
9536 }
4a1805b1 9537
a724f0f4
JB		 9538 return 1;
9539 }
9540
9541 /* e11 BYTE
9542 | WORD
9543 | DWORD
9544 | FWORD
9545 | QWORD
9546 | TBYTE
9547 | OWORD
c0f3af97
L		 9548 | XMMWORD
9549 | YMMWORD */
a724f0f4
JB		 9550 case T_BYTE:
9551 case T_WORD:
9552 case T_DWORD:
9553 case T_FWORD:
9554 case T_QWORD:
9555 case T_TBYTE:
9556 case T_XMMWORD:
c0f3af97 9557 case T_YMMWORD:
a724f0f4 9558 intel_match_token (cur_token.code);
64a0c779 9559
a724f0f4
JB		 9560 if (cur_token.code == T_PTR)
9561 return 1;
9562
9563 /* It must have been an identifier. */
9564 intel_putback_token ();
9565 cur_token.code = T_ID;
9566 /* FALLTHRU */
9567
9568 /* e11 id
9569 | constant */
9570 case T_ID:
9571 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9572 {
9573 symbolS *symbolP;
9574
a724f0f4
JB		 9575 /* The identifier represents a memory reference only if it's not
9576 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9577 symbolP = symbol_find(cur_token.str);
9578 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9579 intel_parser.is_mem = 1;
9580 }
a724f0f4 9581 /* FALLTHRU */
64a0c779 9582
a724f0f4
JB		 9583 case T_CONST:
9584 case '-':
9585 case '+':
9586 {
9587 char *save_str, sign = 0;
64a0c779 9588
a724f0f4
JB		 9589 /* Allow constants that start with `+' or `-'. */
9590 if (cur_token.code == '-' || cur_token.code == '+')
9591 {
9592 sign = cur_token.code;
9593 intel_match_token (cur_token.code);
9594 if (cur_token.code != T_CONST)
9595 {
9596 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9597 cur_token.str);
9598 return 0;
9599 }
9600 }
64a0c779 9601
a724f0f4
JB		 9602 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9603 strcpy (save_str + !!sign, cur_token.str);
9604 if (sign)
9605 *save_str = sign;
64a0c779 9606
a724f0f4
JB		 9607 /* Get the next token to check for register scaling. */
9608 intel_match_token (cur_token.code);
64a0c779 9609
4eed87de
AM		 9610 /* Check if this constant is a scaling factor for an
9611 index register. */
a724f0f4
JB		 9612 if (cur_token.code == '*')
9613 {
9614 if (intel_match_token ('*') && cur_token.code == T_REG)
9615 {
9616 const reg_entry *reg = cur_token.reg;
9617
9618 if (!intel_parser.in_bracket)
9619 {
4eed87de
AM		 9620 as_bad (_("Register scaling only allowed "
9621 "in memory operands"));
a724f0f4
JB		 9622 return 0;
9623 }
9624
4eed87de
AM		 9625 /* Disallow things like [1*si].
9626 sp and esp are invalid as index. */
40fb9820 9627 if (reg->reg_type.bitfield.reg16)
4eed87de 9628 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9629 else if (i.index_reg)
4eed87de 9630 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9631
9632 /* The constant is followed by `* reg', so it must be
9633 a valid scale. */
9634 i.index_reg = reg;
40fb9820 9635 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9636
9637 /* Set the scale after setting the register (otherwise,
9638 i386_scale will complain) */
9639 if (!i386_scale (save_str))
64a0c779 9640 return 0;
a724f0f4
JB		 9641 intel_match_token (T_REG);
9642
9643 /* Since registers are not part of the displacement
9644 string, we may need to remove any preceding '+' from
9645 the displacement string. */
9646 if (*intel_parser.disp != '\0')
9647 {
9648 char *s = intel_parser.disp;
9649 s += strlen (s) - 1;
9650 if (*s == '+')
9651 *s = '\0';
9652 }
9653
9654 free (save_str);
9655
9656 return 1;
9657 }
64a0c779 9658
a724f0f4
JB		 9659 /* The constant was not used for register scaling. Since we have
9660 already consumed the token following `*' we now need to put it
9661 back in the stream. */
64a0c779 9662 intel_putback_token ();
a724f0f4 9663 }
64a0c779 9664
a724f0f4
JB		 9665 /* Add the constant to the displacement string. */
9666 strcat (intel_parser.disp, save_str);
9667 free (save_str);
64a0c779 9668
a724f0f4
JB		 9669 return 1;
9670 }
64a0c779
DN		 9671 }
9672
64a0c779
DN		 9673 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9674 return 0;
9675}
9676
64a0c779
DN		 9677/* Match the given token against cur_token. If they match, read the next
9678 token from the operand string. */
9679static int
e3bb37b5 9680intel_match_token (int code)
64a0c779
DN		 9681{
9682 if (cur_token.code == code)
9683 {
9684 intel_get_token ();
9685 return 1;
9686 }
9687 else
9688 {
0477af35 9689 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9690 return 0;
9691 }
9692}
9693
64a0c779
DN		 9694/* Read a new token from intel_parser.op_string and store it in cur_token. */
9695static void
e3bb37b5 9696intel_get_token (void)
64a0c779
DN		 9697{
9698 char *end_op;
9699 const reg_entry *reg;
9700 struct intel_token new_token;
9701
9702 new_token.code = T_NIL;
9703 new_token.reg = NULL;
9704 new_token.str = NULL;
9705
4a1805b1 9706 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9707 cur_token to prev_token. */
9708 if (prev_token.str)
9709 free (prev_token.str);
9710
9711 prev_token = cur_token;
9712
9713 /* Skip whitespace. */
9714 while (is_space_char (*intel_parser.op_string))
9715 intel_parser.op_string++;
9716
9717 /* Return an empty token if we find nothing else on the line. */
9718 if (*intel_parser.op_string == '\0')
9719 {
9720 cur_token = new_token;
9721 return;
9722 }
9723
9724 /* The new token cannot be larger than the remainder of the operand
9725 string. */
a724f0f4 9726 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9727 new_token.str[0] = '\0';
9728
9729 if (strchr ("0123456789", *intel_parser.op_string))
9730 {
9731 char *p = new_token.str;
9732 char *q = intel_parser.op_string;
9733 new_token.code = T_CONST;
9734
9735 /* Allow any kind of identifier char to encompass floating point and
9736 hexadecimal numbers. */
9737 while (is_identifier_char (*q))
9738 *p++ = *q++;
9739 *p = '\0';
9740
9741 /* Recognize special symbol names [0-9][bf]. */
9742 if (strlen (intel_parser.op_string) == 2
4a1805b1 9743 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9744 || intel_parser.op_string[1] == 'f'))
9745 new_token.code = T_ID;
9746 }
9747
4d1bb795 9748 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9749 {
4d1bb795
JB		 9750 size_t len = end_op - intel_parser.op_string;
9751
64a0c779
DN		 9752 new_token.code = T_REG;
9753 new_token.reg = reg;
9754
4d1bb795
JB		 9755 memcpy (new_token.str, intel_parser.op_string, len);
9756 new_token.str[len] = '\0';
64a0c779
DN		 9757 }
9758
9759 else if (is_identifier_char (*intel_parser.op_string))
9760 {
9761 char *p = new_token.str;
9762 char *q = intel_parser.op_string;
9763
9764 /* A '.' or '$' followed by an identifier char is an identifier.
9765 Otherwise, it's operator '.' followed by an expression. */
9766 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9767 {
9306ca4a
JB		 9768 new_token.code = '.';
9769 new_token.str[0] = '.';
64a0c779
DN		 9770 new_token.str[1] = '\0';
9771 }
9772 else
9773 {
9774 while (is_identifier_char (*q) || *q == '@')
9775 *p++ = *q++;
9776 *p = '\0';
9777
9306ca4a
JB		 9778 if (strcasecmp (new_token.str, "NOT") == 0)
9779 new_token.code = '~';
9780
9781 else if (strcasecmp (new_token.str, "MOD") == 0)
9782 new_token.code = '%';
9783
9784 else if (strcasecmp (new_token.str, "AND") == 0)
9785 new_token.code = '&';
9786
9787 else if (strcasecmp (new_token.str, "OR") == 0)
9788 new_token.code = '|';
9789
9790 else if (strcasecmp (new_token.str, "XOR") == 0)
9791 new_token.code = '^';
9792
9793 else if (strcasecmp (new_token.str, "SHL") == 0)
9794 new_token.code = T_SHL;
9795
9796 else if (strcasecmp (new_token.str, "SHR") == 0)
9797 new_token.code = T_SHR;
9798
9799 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9800 new_token.code = T_BYTE;
9801
9802 else if (strcasecmp (new_token.str, "WORD") == 0)
9803 new_token.code = T_WORD;
9804
9805 else if (strcasecmp (new_token.str, "DWORD") == 0)
9806 new_token.code = T_DWORD;
9807
9306ca4a
JB		 9808 else if (strcasecmp (new_token.str, "FWORD") == 0)
9809 new_token.code = T_FWORD;
9810
64a0c779
DN		 9811 else if (strcasecmp (new_token.str, "QWORD") == 0)
9812 new_token.code = T_QWORD;
9813
9306ca4a
JB		 9814 else if (strcasecmp (new_token.str, "TBYTE") == 0
9815 /* XXX remove (gcc still uses it) */
9816 || strcasecmp (new_token.str, "XWORD") == 0)
9817 new_token.code = T_TBYTE;
9818
9819 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9820 || strcasecmp (new_token.str, "OWORD") == 0)
9821 new_token.code = T_XMMWORD;
64a0c779 9822
c0f3af97
L		 9823 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9824 new_token.code = T_YMMWORD;
9825
64a0c779
DN		 9826 else if (strcasecmp (new_token.str, "PTR") == 0)
9827 new_token.code = T_PTR;
9828
9829 else if (strcasecmp (new_token.str, "SHORT") == 0)
9830 new_token.code = T_SHORT;
9831
9832 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9833 {
9834 new_token.code = T_OFFSET;
9835
9836 /* ??? This is not mentioned in the MASM grammar but gcc
9837 makes use of it with -mintel-syntax. OFFSET may be
9838 followed by FLAT: */
9839 if (strncasecmp (q, " FLAT:", 6) == 0)
9840 strcat (new_token.str, " FLAT:");
9841 }
9842
64a0c779
DN		 9843 else
9844 new_token.code = T_ID;
9845 }
9846 }
9847
9306ca4a
JB		 9848 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9849 {
9850 new_token.code = *intel_parser.op_string;
9851 new_token.str[0] = *intel_parser.op_string;
9852 new_token.str[1] = '\0';
9853 }
9854
9855 else if (strchr ("<>", *intel_parser.op_string)
9856 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9857 {
9858 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9859 new_token.str[0] = *intel_parser.op_string;
9860 new_token.str[1] = *intel_parser.op_string;
9861 new_token.str[2] = '\0';
9862 }
9863
64a0c779 9864 else
0477af35 9865 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9866
9867 intel_parser.op_string += strlen (new_token.str);
9868 cur_token = new_token;
9869}
9870
64a0c779
DN		 9871/* Put cur_token back into the token stream and make cur_token point to
9872 prev_token. */
9873static void
e3bb37b5 9874intel_putback_token (void)
64a0c779 9875{
a724f0f4
JB		 9876 if (cur_token.code != T_NIL)
9877 {
9878 intel_parser.op_string -= strlen (cur_token.str);
9879 free (cur_token.str);
9880 }
64a0c779 9881 cur_token = prev_token;
4a1805b1 9882
64a0c779
DN		 9883 /* Forget prev_token. */
9884 prev_token.code = T_NIL;
9885 prev_token.reg = NULL;
9886 prev_token.str = NULL;
9887}
54cfded0 9888
a60de03c
JB		 9889void
9890tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9891{
a60de03c
JB		 9892 int saved_naked_reg;
9893 char saved_register_dot;
54cfded0 9894
a60de03c
JB		 9895 saved_naked_reg = allow_naked_reg;
9896 allow_naked_reg = 1;
9897 saved_register_dot = register_chars['.'];
9898 register_chars['.'] = '.';
9899 allow_pseudo_reg = 1;
9900 expression_and_evaluate (exp);
9901 allow_pseudo_reg = 0;
9902 register_chars['.'] = saved_register_dot;
9903 allow_naked_reg = saved_naked_reg;
9904
9905 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 9906 {
a60de03c
JB		 9907 if ((addressT) exp->X_add_number < i386_regtab_size)
9908 {
9909 exp->X_op = O_constant;
9910 exp->X_add_number = i386_regtab[exp->X_add_number]
9911 .dw2_regnum[flag_code >> 1];
9912 }
9913 else
9914 exp->X_op = O_illegal;
54cfded0 9915 }
54cfded0
AM		 9916}
9917
9918void
9919tc_x86_frame_initial_instructions (void)
9920{
a60de03c
JB		 9921 static unsigned int sp_regno[2];
9922
9923 if (!sp_regno[flag_code >> 1])
9924 {
9925 char *saved_input = input_line_pointer;
9926 char sp[][4] = {"esp", "rsp"};
9927 expressionS exp;
a4447b93 9928
a60de03c
JB		 9929 input_line_pointer = sp[flag_code >> 1];
9930 tc_x86_parse_to_dw2regnum (&exp);
9931 assert (exp.X_op == O_constant);
9932 sp_regno[flag_code >> 1] = exp.X_add_number;
9933 input_line_pointer = saved_input;
9934 }
a4447b93 9935
a60de03c 9936 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 9937 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9938}
d2b2c203
DJ		 9939
9940int
9941i386_elf_section_type (const char *str, size_t len)
9942{
9943 if (flag_code == CODE_64BIT
9944 && len == sizeof ("unwind") - 1
9945 && strncmp (str, "unwind", 6) == 0)
9946 return SHT_X86_64_UNWIND;
9947
9948 return -1;
9949}
bb41ade5
AM		 9950
9951#ifdef TE_PE
9952void
9953tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9954{
9955 expressionS expr;
9956
9957 expr.X_op = O_secrel;
9958 expr.X_add_symbol = symbol;
9959 expr.X_add_number = 0;
9960 emit_expr (&expr, size);
9961}
9962#endif
3b22753a
L		 9963
9964#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9965/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9966
9967int
9968x86_64_section_letter (int letter, char **ptr_msg)
9969{
9970 if (flag_code == CODE_64BIT)
9971 {
9972 if (letter == 'l')
9973 return SHF_X86_64_LARGE;
9974
9975 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9976 }
3b22753a 9977 else
64e74474 9978 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9979 return -1;
9980}
9981
9982int
9983x86_64_section_word (char *str, size_t len)
9984{
8620418b 9985 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9986 return SHF_X86_64_LARGE;
9987
9988 return -1;
9989}
9990
9991static void
9992handle_large_common (int small ATTRIBUTE_UNUSED)
9993{
9994 if (flag_code != CODE_64BIT)
9995 {
9996 s_comm_internal (0, elf_common_parse);
9997 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9998 }
9999 else
10000 {
10001 static segT lbss_section;
10002 asection *saved_com_section_ptr = elf_com_section_ptr;
10003 asection *saved_bss_section = bss_section;
10004
10005 if (lbss_section == NULL)
10006 {
10007 flagword applicable;
10008 segT seg = now_seg;
10009 subsegT subseg = now_subseg;
10010
10011 /* The .lbss section is for local .largecomm symbols. */
10012 lbss_section = subseg_new (".lbss", 0);
10013 applicable = bfd_applicable_section_flags (stdoutput);
10014 bfd_set_section_flags (stdoutput, lbss_section,
10015 applicable & SEC_ALLOC);
10016 seg_info (lbss_section)->bss = 1;
10017
10018 subseg_set (seg, subseg);
10019 }
10020
10021 elf_com_section_ptr = &_bfd_elf_large_com_section;
10022 bss_section = lbss_section;
10023
10024 s_comm_internal (0, elf_common_parse);
10025
10026 elf_com_section_ptr = saved_com_section_ptr;
10027 bss_section = saved_bss_section;
10028 }
10029}
10030#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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