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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
050dfa73 92static void swap_imm_operands PARAMS ((void));
29b0f896
AM		 93static void optimize_imm PARAMS ((void));
94static void optimize_disp PARAMS ((void));
95static int match_template PARAMS ((void));
96static int check_string PARAMS ((void));
97static int process_suffix PARAMS ((void));
98static int check_byte_reg PARAMS ((void));
99static int check_long_reg PARAMS ((void));
100static int check_qword_reg PARAMS ((void));
101static int check_word_reg PARAMS ((void));
102static int finalize_imm PARAMS ((void));
103static int process_operands PARAMS ((void));
104static const seg_entry *build_modrm_byte PARAMS ((void));
105static void output_insn PARAMS ((void));
106static void output_branch PARAMS ((void));
107static void output_jump PARAMS ((void));
108static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 109static void output_imm PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
111static void output_disp PARAMS ((fragS *insn_start_frag,
112 offsetT insn_start_off));
29b0f896
AM		 113#ifndef I386COFF
114static void s_bss PARAMS ((int));
252b5132 115#endif
17d4e2a2
L		 116#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
117static void handle_large_common (int small ATTRIBUTE_UNUSED);
118#endif
252b5132 119
a847613f 120static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 121
252b5132 122/* 'md_assemble ()' gathers together information and puts it into a
47926f60 123 i386_insn. */
252b5132 124
520dc8e8
AM		 125union i386_op
126 {
127 expressionS *disps;
128 expressionS *imms;
129 const reg_entry *regs;
130 };
131
252b5132
RH		 132struct _i386_insn
133 {
47926f60 134 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 135 template tm;
136
137 /* SUFFIX holds the instruction mnemonic suffix if given.
138 (e.g. 'l' for 'movl') */
139 char suffix;
140
47926f60 141 /* OPERANDS gives the number of given operands. */
252b5132
RH		 142 unsigned int operands;
143
144 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
145 of given register, displacement, memory operands and immediate
47926f60 146 operands. */
252b5132
RH		 147 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
148
149 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 150 use OP[i] for the corresponding operand. */
252b5132
RH		 151 unsigned int types[MAX_OPERANDS];
152
520dc8e8
AM		 153 /* Displacement expression, immediate expression, or register for each
154 operand. */
155 union i386_op op[MAX_OPERANDS];
252b5132 156
3e73aa7c
JH		 157 /* Flags for operands. */
158 unsigned int flags[MAX_OPERANDS];
159#define Operand_PCrel 1
160
252b5132 161 /* Relocation type for operand */
f86103b7 162 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 163
252b5132
RH		 164 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
165 the base index byte below. */
166 const reg_entry *base_reg;
167 const reg_entry *index_reg;
168 unsigned int log2_scale_factor;
169
170 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 171 explicit segment overrides are given. */
ce8a8b2f 172 const seg_entry *seg[2];
252b5132
RH		 173
174 /* PREFIX holds all the given prefix opcodes (usually null).
175 PREFIXES is the number of prefix opcodes. */
176 unsigned int prefixes;
177 unsigned char prefix[MAX_PREFIXES];
178
179 /* RM and SIB are the modrm byte and the sib byte where the
180 addressing modes of this insn are encoded. */
181
182 modrm_byte rm;
3e73aa7c 183 rex_byte rex;
252b5132
RH		 184 sib_byte sib;
185 };
186
187typedef struct _i386_insn i386_insn;
188
189/* List of chars besides those in app.c:symbol_chars that can start an
190 operand. Used to prevent the scrubber eating vital white-space. */
32137342 191const char extra_symbol_chars[] = "*%-(["
252b5132 192#ifdef LEX_AT
32137342
NC		 193 "@"
194#endif
195#ifdef LEX_QM
196 "?"
252b5132 197#endif
32137342 198 ;
252b5132 199
29b0f896
AM		 200#if (defined (TE_I386AIX) \
201 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 202 && !defined (TE_GNU) \
29b0f896 203 && !defined (TE_LINUX) \
32137342 204 && !defined (TE_NETWARE) \
29b0f896
AM		 205 && !defined (TE_FreeBSD) \
206 && !defined (TE_NetBSD)))
252b5132 207/* This array holds the chars that always start a comment. If the
b3b91714
AM		 208 pre-processor is disabled, these aren't very useful. The option
209 --divide will remove '/' from this list. */
210const char *i386_comment_chars = "#/";
211#define SVR4_COMMENT_CHARS 1
252b5132 212#define PREFIX_SEPARATOR '\\'
252b5132 213
b3b91714
AM		 214#else
215const char *i386_comment_chars = "#";
216#define PREFIX_SEPARATOR '/'
217#endif
218
252b5132
RH		 219/* This array holds the chars that only start a comment at the beginning of
220 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 221 .line and .file directives will appear in the pre-processed output.
222 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 223 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 224 #NO_APP at the beginning of its output.
225 Also note that comments started like this one will always work if
252b5132 226 '/' isn't otherwise defined. */
b3b91714 227const char line_comment_chars[] = "#/";
252b5132 228
63a0b638 229const char line_separator_chars[] = ";";
252b5132 230
ce8a8b2f
AM		 231/* Chars that can be used to separate mant from exp in floating point
232 nums. */
252b5132
RH		 233const char EXP_CHARS[] = "eE";
234
ce8a8b2f
AM		 235/* Chars that mean this number is a floating point constant
236 As in 0f12.456
237 or 0d1.2345e12. */
252b5132
RH		 238const char FLT_CHARS[] = "fFdDxX";
239
ce8a8b2f 240/* Tables for lexical analysis. */
252b5132
RH		 241static char mnemonic_chars[256];
242static char register_chars[256];
243static char operand_chars[256];
244static char identifier_chars[256];
245static char digit_chars[256];
246
ce8a8b2f 247/* Lexical macros. */
252b5132
RH		 248#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
249#define is_operand_char(x) (operand_chars[(unsigned char) x])
250#define is_register_char(x) (register_chars[(unsigned char) x])
251#define is_space_char(x) ((x) == ' ')
252#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
253#define is_digit_char(x) (digit_chars[(unsigned char) x])
254
0234cb7c 255/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 256static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
257
258/* md_assemble() always leaves the strings it's passed unaltered. To
259 effect this we maintain a stack of saved characters that we've smashed
260 with '\0's (indicating end of strings for various sub-fields of the
47926f60 261 assembler instruction). */
252b5132 262static char save_stack[32];
ce8a8b2f 263static char *save_stack_p;
252b5132
RH		 264#define END_STRING_AND_SAVE(s) \
265 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
266#define RESTORE_END_STRING(s) \
267 do { *(s) = *--save_stack_p; } while (0)
268
47926f60 269/* The instruction we're assembling. */
252b5132
RH		 270static i386_insn i;
271
272/* Possible templates for current insn. */
273static const templates *current_templates;
274
47926f60 275/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 276static expressionS disp_expressions[2], im_expressions[2];
277
47926f60
KH		 278/* Current operand we are working on. */
279static int this_operand;
252b5132 280
3e73aa7c
JH		 281/* We support four different modes. FLAG_CODE variable is used to distinguish
282 these. */
283
284enum flag_code {
285 CODE_32BIT,
286 CODE_16BIT,
287 CODE_64BIT };
f3c180ae 288#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 289
290static enum flag_code flag_code;
4fa24527 291static unsigned int object_64bit;
3e73aa7c
JH		 292static int use_rela_relocations = 0;
293
294/* The names used to print error messages. */
b77a7acd 295static const char *flag_code_names[] =
3e73aa7c
JH		 296 {
297 "32",
298 "16",
299 "64"
300 };
252b5132 301
47926f60
KH		 302/* 1 for intel syntax,
303 0 if att syntax. */
304static int intel_syntax = 0;
252b5132 305
47926f60
KH		 306/* 1 if register prefix % not required. */
307static int allow_naked_reg = 0;
252b5132 308
47926f60
KH		 309/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
310 leave, push, and pop instructions so that gcc has the same stack
311 frame as in 32 bit mode. */
312static char stackop_size = '\0';
eecb386c 313
12b55ccc
L		 314/* Non-zero to optimize code alignment. */
315int optimize_align_code = 1;
316
47926f60
KH		 317/* Non-zero to quieten some warnings. */
318static int quiet_warnings = 0;
a38cf1db 319
47926f60
KH		 320/* CPU name. */
321static const char *cpu_arch_name = NULL;
5c6af06e 322static const char *cpu_sub_arch_name = NULL;
a38cf1db 323
47926f60 324/* CPU feature flags. */
29b0f896 325static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 326
ccc9c027
L		 327/* If we have selected a cpu we are generating instructions for. */
328static int cpu_arch_tune_set = 0;
329
9103f4f4
L		 330/* Cpu we are generating instructions for. */
331static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
332
333/* CPU feature flags of cpu we are generating instructions for. */
334static unsigned int cpu_arch_tune_flags = 0;
335
ccc9c027
L		 336/* CPU instruction set architecture used. */
337static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
338
9103f4f4
L		 339/* CPU feature flags of instruction set architecture used. */
340static unsigned int cpu_arch_isa_flags = 0;
341
fddf5b5b
AM		 342/* If set, conditional jumps are not automatically promoted to handle
343 larger than a byte offset. */
344static unsigned int no_cond_jump_promotion = 0;
345
29b0f896 346/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 347static symbolS *GOT_symbol;
29b0f896 348
a4447b93
RH		 349/* The dwarf2 return column, adjusted for 32 or 64 bit. */
350unsigned int x86_dwarf2_return_column;
351
352/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
353int x86_cie_data_alignment;
354
252b5132 355/* Interface to relax_segment.
fddf5b5b
AM		 356 There are 3 major relax states for 386 jump insns because the
357 different types of jumps add different sizes to frags when we're
358 figuring out what sort of jump to choose to reach a given label. */
252b5132 359
47926f60 360/* Types. */
93c2a809
AM		 361#define UNCOND_JUMP 0
362#define COND_JUMP 1
363#define COND_JUMP86 2
fddf5b5b 364
47926f60 365/* Sizes. */
252b5132
RH		 366#define CODE16 1
367#define SMALL 0
29b0f896 368#define SMALL16 (SMALL | CODE16)
252b5132 369#define BIG 2
29b0f896 370#define BIG16 (BIG | CODE16)
252b5132
RH		 371
372#ifndef INLINE
373#ifdef __GNUC__
374#define INLINE __inline__
375#else
376#define INLINE
377#endif
378#endif
379
fddf5b5b
AM		 380#define ENCODE_RELAX_STATE(type, size) \
381 ((relax_substateT) (((type) << 2) | (size)))
382#define TYPE_FROM_RELAX_STATE(s) \
383 ((s) >> 2)
384#define DISP_SIZE_FROM_RELAX_STATE(s) \
385 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 386
387/* This table is used by relax_frag to promote short jumps to long
388 ones where necessary. SMALL (short) jumps may be promoted to BIG
389 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
390 don't allow a short jump in a 32 bit code segment to be promoted to
391 a 16 bit offset jump because it's slower (requires data size
392 prefix), and doesn't work, unless the destination is in the bottom
393 64k of the code segment (The top 16 bits of eip are zeroed). */
394
395const relax_typeS md_relax_table[] =
396{
24eab124
AM		 397 /* The fields are:
398 1) most positive reach of this state,
399 2) most negative reach of this state,
93c2a809 400 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 401 4) which index into the table to try if we can't fit into this one. */
252b5132 402
fddf5b5b 403 /* UNCOND_JUMP states. */
93c2a809
AM		 404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
406 /* dword jmp adds 4 bytes to frag:
407 0 extra opcode bytes, 4 displacement bytes. */
252b5132 408 {0, 0, 4, 0},
93c2a809
AM		 409 /* word jmp adds 2 byte2 to frag:
410 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 411 {0, 0, 2, 0},
412
93c2a809
AM		 413 /* COND_JUMP states. */
414 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
415 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
416 /* dword conditionals adds 5 bytes to frag:
417 1 extra opcode byte, 4 displacement bytes. */
418 {0, 0, 5, 0},
fddf5b5b 419 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 420 1 extra opcode byte, 2 displacement bytes. */
421 {0, 0, 3, 0},
422
423 /* COND_JUMP86 states. */
424 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
425 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
426 /* dword conditionals adds 5 bytes to frag:
427 1 extra opcode byte, 4 displacement bytes. */
428 {0, 0, 5, 0},
429 /* word conditionals add 4 bytes to frag:
430 1 displacement byte and a 3 byte long branch insn. */
431 {0, 0, 4, 0}
252b5132
RH		 432};
433
9103f4f4
L		 434static const arch_entry cpu_arch[] =
435{
436 {"generic32", PROCESSOR_GENERIC32,
437 Cpu086|Cpu186|Cpu286|Cpu386},
438 {"generic64", PROCESSOR_GENERIC64,
439 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
440 |CpuMMX2|CpuSSE|CpuSSE2},
441 {"i8086", PROCESSOR_UNKNOWN,
442 Cpu086},
443 {"i186", PROCESSOR_UNKNOWN,
444 Cpu086|Cpu186},
445 {"i286", PROCESSOR_UNKNOWN,
446 Cpu086|Cpu186|Cpu286},
447 {"i386", PROCESSOR_GENERIC32,
448 Cpu086|Cpu186|Cpu286|Cpu386},
449 {"i486", PROCESSOR_I486,
450 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486},
451 {"i586", PROCESSOR_PENTIUM,
452 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
453 {"i686", PROCESSOR_PENTIUMPRO,
454 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
455 {"pentium", PROCESSOR_PENTIUM,
456 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
457 {"pentiumpro",PROCESSOR_PENTIUMPRO,
458 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
459 {"pentiumii", PROCESSOR_PENTIUMPRO,
460 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
461 {"pentiumiii",PROCESSOR_PENTIUMPRO,
462 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2
463 |CpuSSE},
464 {"pentium4", PROCESSOR_PENTIUM4,
465 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
466 |CpuMMX2|CpuSSE|CpuSSE2},
467 {"prescott", PROCESSOR_NOCONA,
468 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
469 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
470 {"nocona", PROCESSOR_NOCONA,
471 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
472 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
473 {"yonah", PROCESSOR_YONAH,
474 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
475 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
476 {"merom", PROCESSOR_MEROM,
477 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
478 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
479 {"k6", PROCESSOR_K6,
480 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
481 {"k6_2", PROCESSOR_K6,
482 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
483 {"athlon", PROCESSOR_ATHLON,
484 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
485 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
486 {"sledgehammer", PROCESSOR_K8,
487 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
488 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
489 {"opteron", PROCESSOR_K8,
490 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
491 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
492 {"k8", PROCESSOR_K8,
493 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
494 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
050dfa73
MM		 495 {"amdfam10", PROCESSOR_AMDFAM10,
496 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
497 |CpuSledgehammer|CpuAmdFam10|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a|CpuABM},
9103f4f4
L		 498 {".mmx", PROCESSOR_UNKNOWN,
499 CpuMMX},
500 {".sse", PROCESSOR_UNKNOWN,
501 CpuMMX|CpuMMX2|CpuSSE},
502 {".sse2", PROCESSOR_UNKNOWN,
503 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
504 {".sse3", PROCESSOR_UNKNOWN,
505 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
506 {".3dnow", PROCESSOR_UNKNOWN,
507 CpuMMX|Cpu3dnow},
508 {".3dnowa", PROCESSOR_UNKNOWN,
509 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
510 {".padlock", PROCESSOR_UNKNOWN,
511 CpuPadLock},
512 {".pacifica", PROCESSOR_UNKNOWN,
513 CpuSVME},
514 {".svme", PROCESSOR_UNKNOWN,
050dfa73
MM		 515 CpuSVME},
516 {".sse4a", PROCESSOR_UNKNOWN,
517 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuSSE4a},
518 {".abm", PROCESSOR_UNKNOWN,
519 CpuABM}
e413e4e9
AM		 520};
521
29b0f896
AM		 522const pseudo_typeS md_pseudo_table[] =
523{
524#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
525 {"align", s_align_bytes, 0},
526#else
527 {"align", s_align_ptwo, 0},
528#endif
529 {"arch", set_cpu_arch, 0},
530#ifndef I386COFF
531 {"bss", s_bss, 0},
532#endif
533 {"ffloat", float_cons, 'f'},
534 {"dfloat", float_cons, 'd'},
535 {"tfloat", float_cons, 'x'},
536 {"value", cons, 2},
d182319b 537 {"slong", signed_cons, 4},
29b0f896
AM		 538 {"noopt", s_ignore, 0},
539 {"optim", s_ignore, 0},
540 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
541 {"code16", set_code_flag, CODE_16BIT},
542 {"code32", set_code_flag, CODE_32BIT},
543 {"code64", set_code_flag, CODE_64BIT},
544 {"intel_syntax", set_intel_syntax, 1},
545 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 548#else
549 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 552#endif
6482c264
NC		 553#ifdef TE_PE
554 {"secrel32", pe_directive_secrel, 0},
555#endif
29b0f896
AM		 556 {0, 0, 0}
557};
558
559/* For interface with expression (). */
560extern char *input_line_pointer;
561
562/* Hash table for instruction mnemonic lookup. */
563static struct hash_control *op_hash;
564
565/* Hash table for register lookup. */
566static struct hash_control *reg_hash;
567\f
252b5132
RH		 568void
569i386_align_code (fragP, count)
570 fragS *fragP;
571 int count;
572{
ce8a8b2f
AM		 573 /* Various efficient no-op patterns for aligning code labels.
574 Note: Don't try to assemble the instructions in the comments.
575 0L and 0w are not legal. */
252b5132
RH		 576 static const char f32_1[] =
577 {0x90}; /* nop */
578 static const char f32_2[] =
ccc9c027 579 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 580 static const char f32_3[] =
581 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
582 static const char f32_4[] =
583 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
584 static const char f32_5[] =
585 {0x90, /* nop */
586 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
587 static const char f32_6[] =
588 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
589 static const char f32_7[] =
590 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
591 static const char f32_8[] =
592 {0x90, /* nop */
593 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
594 static const char f32_9[] =
595 {0x89,0xf6, /* movl %esi,%esi */
596 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
597 static const char f32_10[] =
598 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
599 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
600 static const char f32_11[] =
601 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
602 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
603 static const char f32_12[] =
604 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
605 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
606 static const char f32_13[] =
607 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
608 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
609 static const char f32_14[] =
610 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
611 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
612 static const char f32_15[] =
613 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
614 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 615 static const char f16_3[] =
616 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 617 static const char f16_4[] =
618 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
619 static const char f16_5[] =
620 {0x90, /* nop */
621 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
622 static const char f16_6[] =
623 {0x89,0xf6, /* mov %si,%si */
624 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
625 static const char f16_7[] =
626 {0x8d,0x74,0x00, /* lea 0(%si),%si */
627 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
628 static const char f16_8[] =
629 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
630 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
634 };
635 static const char *const f16_patt[] = {
c3332e24 636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 637 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
638 };
ccc9c027
L		 639 /* nopl (%[re]ax) */
640 static const char alt_3[] =
641 {0x0f,0x1f,0x00};
642 /* nopl 0(%[re]ax) */
643 static const char alt_4[] =
644 {0x0f,0x1f,0x40,0x00};
645 /* nopl 0(%[re]ax,%[re]ax,1) */
646 static const char alt_5[] =
647 {0x0f,0x1f,0x44,0x00,0x00};
648 /* nopw 0(%[re]ax,%[re]ax,1) */
649 static const char alt_6[] =
650 {0x66,0x0f,0x1f,0x44,0x00,0x00};
651 /* nopl 0L(%[re]ax) */
652 static const char alt_7[] =
653 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
654 /* nopl 0L(%[re]ax,%[re]ax,1) */
655 static const char alt_8[] =
656 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
657 /* nopw 0L(%[re]ax,%[re]ax,1) */
658 static const char alt_9[] =
659 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
660 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
661 static const char alt_10[] =
662 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
663 /* data16
664 nopw %cs:0L(%[re]ax,%[re]ax,1) */
665 static const char alt_long_11[] =
666 {0x66,
667 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
668 /* data16
669 data16
670 nopw %cs:0L(%[re]ax,%[re]ax,1) */
671 static const char alt_long_12[] =
672 {0x66,
673 0x66,
674 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
675 /* data16
676 data16
677 data16
678 nopw %cs:0L(%[re]ax,%[re]ax,1) */
679 static const char alt_long_13[] =
680 {0x66,
681 0x66,
682 0x66,
683 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
684 /* data16
685 data16
686 data16
687 data16
688 nopw %cs:0L(%[re]ax,%[re]ax,1) */
689 static const char alt_long_14[] =
690 {0x66,
691 0x66,
692 0x66,
693 0x66,
694 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
695 /* data16
696 data16
697 data16
698 data16
699 data16
700 nopw %cs:0L(%[re]ax,%[re]ax,1) */
701 static const char alt_long_15[] =
702 {0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,
707 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
708 /* nopl 0(%[re]ax,%[re]ax,1)
709 nopw 0(%[re]ax,%[re]ax,1) */
710 static const char alt_short_11[] =
711 {0x0f,0x1f,0x44,0x00,0x00,
712 0x66,0x0f,0x1f,0x44,0x00,0x00};
713 /* nopw 0(%[re]ax,%[re]ax,1)
714 nopw 0(%[re]ax,%[re]ax,1) */
715 static const char alt_short_12[] =
716 {0x66,0x0f,0x1f,0x44,0x00,0x00,
717 0x66,0x0f,0x1f,0x44,0x00,0x00};
718 /* nopw 0(%[re]ax,%[re]ax,1)
719 nopl 0L(%[re]ax) */
720 static const char alt_short_13[] =
721 {0x66,0x0f,0x1f,0x44,0x00,0x00,
722 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
723 /* nopl 0L(%[re]ax)
724 nopl 0L(%[re]ax) */
725 static const char alt_short_14[] =
726 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
727 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
728 /* nopl 0L(%[re]ax)
729 nopl 0L(%[re]ax,%[re]ax,1) */
730 static const char alt_short_15[] =
731 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
732 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
733 static const char *const alt_short_patt[] = {
734 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
735 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
736 alt_short_14, alt_short_15
737 };
738 static const char *const alt_long_patt[] = {
739 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
740 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
741 alt_long_14, alt_long_15
742 };
252b5132 743
33fef721
JH		 744 if (count <= 0 || count > 15)
745 return;
3e73aa7c 746
ccc9c027
L		 747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
749
750 1. For PROCESSOR_I486, PROCESSOR_PENTIUM and PROCESSOR_GENERIC32,
751 f32_patt will be used.
050dfa73 752 2. For PROCESSOR_K8 and PROCESSOR_AMDFAM10 in 64bit, NOPs with 0x66 prefix will be used.
ccc9c027
L		 753 3. For PROCESSOR_MEROM, alt_long_patt will be used.
754 4. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
755 PROCESSOR_YONAH, PROCESSOR_MEROM, PROCESSOR_K6, PROCESSOR_ATHLON
756 and PROCESSOR_GENERIC64, alt_short_patt will be used.
757
758 When -mtune= isn't used, alt_short_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will be used.
760
761 When -march= or .arch is used, we can't use anything beyond
762 cpu_arch_isa_flags. */
763
764 if (flag_code == CODE_16BIT)
765 {
766 memcpy (fragP->fr_literal + fragP->fr_fix,
767 f16_patt[count - 1], count);
768 if (count > 8)
769 /* Adjust jump offset. */
770 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
771 }
772 else if (flag_code == CODE_64BIT && cpu_arch_tune == PROCESSOR_K8)
252b5132 773 {
33fef721
JH		 774 int i;
775 int nnops = (count + 3) / 4;
776 int len = count / nnops;
777 int remains = count - nnops * len;
778 int pos = 0;
779
ccc9c027
L		 780 /* The recommended way to pad 64bit code is to use NOPs preceded
781 by maximally four 0x66 prefixes. Balance the size of nops. */
33fef721 782 for (i = 0; i < remains; i++)
252b5132 783 {
33fef721
JH		 784 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
785 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
786 pos += len + 1;
787 }
788 for (; i < nnops; i++)
789 {
790 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
791 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
792 pos += len;
252b5132 793 }
252b5132 794 }
33fef721 795 else
ccc9c027
L		 796 {
797 const char *const *patt = NULL;
798
799 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
800 {
801 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
802 switch (cpu_arch_tune)
803 {
804 case PROCESSOR_UNKNOWN:
805 /* We use cpu_arch_isa_flags to check if we SHOULD
806 optimize for Cpu686. */
807 if ((cpu_arch_isa_flags & Cpu686) != 0)
808 patt = alt_short_patt;
809 else
810 patt = f32_patt;
811 break;
812 case PROCESSOR_MEROM:
813 patt = alt_long_patt;
814 break;
815 case PROCESSOR_PENTIUMPRO:
816 case PROCESSOR_PENTIUM4:
817 case PROCESSOR_NOCONA:
818 case PROCESSOR_YONAH:
819 case PROCESSOR_K6:
820 case PROCESSOR_ATHLON:
821 case PROCESSOR_K8:
822 case PROCESSOR_GENERIC64:
050dfa73 823 case PROCESSOR_AMDFAM10:
ccc9c027
L		 824 patt = alt_short_patt;
825 break;
826 case PROCESSOR_I486:
827 case PROCESSOR_PENTIUM:
828 case PROCESSOR_GENERIC32:
829 patt = f32_patt;
830 break;
831 }
832 }
833 else
834 {
835 switch (cpu_arch_tune)
836 {
837 case PROCESSOR_UNKNOWN:
838 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
839 PROCESSOR_UNKNOWN. */
840 abort ();
841 break;
842
843 case PROCESSOR_I486:
844 case PROCESSOR_PENTIUM:
845 case PROCESSOR_PENTIUMPRO:
846 case PROCESSOR_PENTIUM4:
847 case PROCESSOR_NOCONA:
848 case PROCESSOR_YONAH:
849 case PROCESSOR_K6:
850 case PROCESSOR_ATHLON:
851 case PROCESSOR_K8:
050dfa73 852 case PROCESSOR_AMDFAM10:
ccc9c027
L		 853 case PROCESSOR_GENERIC32:
854 /* We use cpu_arch_isa_flags to check if we CAN optimize
855 for Cpu686. */
856 if ((cpu_arch_isa_flags & Cpu686) != 0)
857 patt = alt_short_patt;
858 else
859 patt = f32_patt;
860 break;
861 case PROCESSOR_MEROM:
862 if ((cpu_arch_isa_flags & Cpu686) != 0)
863 patt = alt_long_patt;
864 else
865 patt = f32_patt;
866 break;
867 case PROCESSOR_GENERIC64:
868 patt = alt_short_patt;
869 break;
870 }
871 }
872
33fef721 873 memcpy (fragP->fr_literal + fragP->fr_fix,
ccc9c027
L		 874 patt[count - 1], count);
875 }
33fef721 876 fragP->fr_var = count;
252b5132
RH		 877}
878
252b5132
RH		 879static INLINE unsigned int
880mode_from_disp_size (t)
881 unsigned int t;
882{
3e73aa7c 883 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 884}
885
886static INLINE int
887fits_in_signed_byte (num)
847f7ad4 888 offsetT num;
252b5132
RH		 889{
890 return (num >= -128) && (num <= 127);
47926f60 891}
252b5132
RH		 892
893static INLINE int
894fits_in_unsigned_byte (num)
847f7ad4 895 offsetT num;
252b5132
RH		 896{
897 return (num & 0xff) == num;
47926f60 898}
252b5132
RH		 899
900static INLINE int
901fits_in_unsigned_word (num)
847f7ad4 902 offsetT num;
252b5132
RH		 903{
904 return (num & 0xffff) == num;
47926f60 905}
252b5132
RH		 906
907static INLINE int
908fits_in_signed_word (num)
847f7ad4 909 offsetT num;
252b5132
RH		 910{
911 return (-32768 <= num) && (num <= 32767);
47926f60 912}
3e73aa7c
JH		 913static INLINE int
914fits_in_signed_long (num)
915 offsetT num ATTRIBUTE_UNUSED;
916{
917#ifndef BFD64
918 return 1;
919#else
920 return (!(((offsetT) -1 << 31) & num)
921 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
922#endif
923} /* fits_in_signed_long() */
924static INLINE int
925fits_in_unsigned_long (num)
926 offsetT num ATTRIBUTE_UNUSED;
927{
928#ifndef BFD64
929 return 1;
930#else
931 return (num & (((offsetT) 2 << 31) - 1)) == num;
932#endif
933} /* fits_in_unsigned_long() */
252b5132
RH		 934
935static int
936smallest_imm_type (num)
847f7ad4 937 offsetT num;
252b5132 938{
a847613f 939 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 940 {
941 /* This code is disabled on the 486 because all the Imm1 forms
942 in the opcode table are slower on the i486. They're the
943 versions with the implicitly specified single-position
944 displacement, which has another syntax if you really want to
945 use that form. */
946 if (num == 1)
3e73aa7c 947 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 948 }
252b5132 949 return (fits_in_signed_byte (num)
3e73aa7c 950 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 951 : fits_in_unsigned_byte (num)
3e73aa7c 952 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 953 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 954 ? (Imm16 | Imm32 | Imm32S | Imm64)
955 : fits_in_signed_long (num)
956 ? (Imm32 | Imm32S | Imm64)
957 : fits_in_unsigned_long (num)
958 ? (Imm32 | Imm64)
959 : Imm64);
47926f60 960}
252b5132 961
847f7ad4
AM		 962static offsetT
963offset_in_range (val, size)
964 offsetT val;
965 int size;
966{
508866be 967 addressT mask;
ba2adb93 968
847f7ad4
AM		 969 switch (size)
970 {
508866be
L		 971 case 1: mask = ((addressT) 1 << 8) - 1; break;
972 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 973 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 974#ifdef BFD64
975 case 8: mask = ((addressT) 2 << 63) - 1; break;
976#endif
47926f60 977 default: abort ();
847f7ad4
AM		 978 }
979
ba2adb93 980 /* If BFD64, sign extend val. */
3e73aa7c
JH		 981 if (!use_rela_relocations)
982 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
983 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 984
47926f60 985 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 986 {
987 char buf1[40], buf2[40];
988
989 sprint_value (buf1, val);
990 sprint_value (buf2, val & mask);
991 as_warn (_("%s shortened to %s"), buf1, buf2);
992 }
993 return val & mask;
994}
995
252b5132
RH		 996/* Returns 0 if attempting to add a prefix where one from the same
997 class already exists, 1 if non rep/repne added, 2 if rep/repne
998 added. */
999static int
1000add_prefix (prefix)
1001 unsigned int prefix;
1002{
1003 int ret = 1;
b1905489 1004 unsigned int q;
252b5132 1005
29b0f896
AM		 1006 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1007 && flag_code == CODE_64BIT)
b1905489
JB		 1008 {
1009 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
1010 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
1011 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
1012 ret = 0;
1013 q = REX_PREFIX;
1014 }
3e73aa7c 1015 else
b1905489
JB		 1016 {
1017 switch (prefix)
1018 {
1019 default:
1020 abort ();
1021
1022 case CS_PREFIX_OPCODE:
1023 case DS_PREFIX_OPCODE:
1024 case ES_PREFIX_OPCODE:
1025 case FS_PREFIX_OPCODE:
1026 case GS_PREFIX_OPCODE:
1027 case SS_PREFIX_OPCODE:
1028 q = SEG_PREFIX;
1029 break;
1030
1031 case REPNE_PREFIX_OPCODE:
1032 case REPE_PREFIX_OPCODE:
1033 ret = 2;
1034 /* fall thru */
1035 case LOCK_PREFIX_OPCODE:
1036 q = LOCKREP_PREFIX;
1037 break;
1038
1039 case FWAIT_OPCODE:
1040 q = WAIT_PREFIX;
1041 break;
1042
1043 case ADDR_PREFIX_OPCODE:
1044 q = ADDR_PREFIX;
1045 break;
1046
1047 case DATA_PREFIX_OPCODE:
1048 q = DATA_PREFIX;
1049 break;
1050 }
1051 if (i.prefix[q] != 0)
1052 ret = 0;
1053 }
252b5132 1054
b1905489 1055 if (ret)
252b5132 1056 {
b1905489
JB		 1057 if (!i.prefix[q])
1058 ++i.prefixes;
1059 i.prefix[q] |= prefix;
252b5132 1060 }
b1905489
JB		 1061 else
1062 as_bad (_("same type of prefix used twice"));
252b5132 1063
252b5132
RH		 1064 return ret;
1065}
1066
1067static void
3e73aa7c 1068set_code_flag (value)
e5cb08ac 1069 int value;
eecb386c 1070{
3e73aa7c
JH		 1071 flag_code = value;
1072 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1073 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
1074 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
1075 {
1076 as_bad (_("64bit mode not supported on this CPU."));
1077 }
1078 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
1079 {
1080 as_bad (_("32bit mode not supported on this CPU."));
1081 }
eecb386c
AM		 1082 stackop_size = '\0';
1083}
1084
1085static void
3e73aa7c
JH		 1086set_16bit_gcc_code_flag (new_code_flag)
1087 int new_code_flag;
252b5132 1088{
3e73aa7c
JH		 1089 flag_code = new_code_flag;
1090 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
1091 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 1092 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1093}
1094
1095static void
1096set_intel_syntax (syntax_flag)
eecb386c 1097 int syntax_flag;
252b5132
RH		 1098{
1099 /* Find out if register prefixing is specified. */
1100 int ask_naked_reg = 0;
1101
1102 SKIP_WHITESPACE ();
29b0f896 1103 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1104 {
1105 char *string = input_line_pointer;
1106 int e = get_symbol_end ();
1107
47926f60 1108 if (strcmp (string, "prefix") == 0)
252b5132 1109 ask_naked_reg = 1;
47926f60 1110 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1111 ask_naked_reg = -1;
1112 else
d0b47220 1113 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1114 *input_line_pointer = e;
1115 }
1116 demand_empty_rest_of_line ();
c3332e24 1117
252b5132
RH		 1118 intel_syntax = syntax_flag;
1119
1120 if (ask_naked_reg == 0)
f86103b7
AM		 1121 allow_naked_reg = (intel_syntax
1122 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1123 else
1124 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 1125
1126 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
1127 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 1128}
1129
e413e4e9
AM		 1130static void
1131set_cpu_arch (dummy)
47926f60 1132 int dummy ATTRIBUTE_UNUSED;
e413e4e9 1133{
47926f60 1134 SKIP_WHITESPACE ();
e413e4e9 1135
29b0f896 1136 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1137 {
1138 char *string = input_line_pointer;
1139 int e = get_symbol_end ();
9103f4f4 1140 unsigned int i;
e413e4e9 1141
9103f4f4 1142 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1143 {
1144 if (strcmp (string, cpu_arch[i].name) == 0)
1145 {
5c6af06e
JB		 1146 if (*string != '.')
1147 {
1148 cpu_arch_name = cpu_arch[i].name;
1149 cpu_sub_arch_name = NULL;
1150 cpu_arch_flags = (cpu_arch[i].flags
1151 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
ccc9c027 1152 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1153 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1154 if (!cpu_arch_tune_set)
1155 {
1156 cpu_arch_tune = cpu_arch_isa;
1157 cpu_arch_tune_flags = cpu_arch_isa_flags;
1158 }
5c6af06e
JB		 1159 break;
1160 }
1161 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
1162 {
1163 cpu_sub_arch_name = cpu_arch[i].name;
1164 cpu_arch_flags |= cpu_arch[i].flags;
1165 }
1166 *input_line_pointer = e;
1167 demand_empty_rest_of_line ();
1168 return;
e413e4e9
AM		 1169 }
1170 }
9103f4f4 1171 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1172 as_bad (_("no such architecture: `%s'"), string);
1173
1174 *input_line_pointer = e;
1175 }
1176 else
1177 as_bad (_("missing cpu architecture"));
1178
fddf5b5b
AM		 1179 no_cond_jump_promotion = 0;
1180 if (*input_line_pointer == ','
29b0f896 1181 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1182 {
1183 char *string = ++input_line_pointer;
1184 int e = get_symbol_end ();
1185
1186 if (strcmp (string, "nojumps") == 0)
1187 no_cond_jump_promotion = 1;
1188 else if (strcmp (string, "jumps") == 0)
1189 ;
1190 else
1191 as_bad (_("no such architecture modifier: `%s'"), string);
1192
1193 *input_line_pointer = e;
1194 }
1195
e413e4e9
AM		 1196 demand_empty_rest_of_line ();
1197}
1198
b9d79e03
JH		 1199unsigned long
1200i386_mach ()
1201{
1202 if (!strcmp (default_arch, "x86_64"))
1203 return bfd_mach_x86_64;
1204 else if (!strcmp (default_arch, "i386"))
1205 return bfd_mach_i386_i386;
1206 else
1207 as_fatal (_("Unknown architecture"));
1208}
b9d79e03 1209\f
252b5132
RH		 1210void
1211md_begin ()
1212{
1213 const char *hash_err;
1214
47926f60 1215 /* Initialize op_hash hash table. */
252b5132
RH		 1216 op_hash = hash_new ();
1217
1218 {
29b0f896
AM		 1219 const template *optab;
1220 templates *core_optab;
252b5132 1221
47926f60
KH		 1222 /* Setup for loop. */
1223 optab = i386_optab;
252b5132
RH		 1224 core_optab = (templates *) xmalloc (sizeof (templates));
1225 core_optab->start = optab;
1226
1227 while (1)
1228 {
1229 ++optab;
1230 if (optab->name == NULL
1231 || strcmp (optab->name, (optab - 1)->name) != 0)
1232 {
1233 /* different name --> ship out current template list;
47926f60 1234 add to hash table; & begin anew. */
252b5132
RH		 1235 core_optab->end = optab;
1236 hash_err = hash_insert (op_hash,
1237 (optab - 1)->name,
1238 (PTR) core_optab);
1239 if (hash_err)
1240 {
252b5132
RH		 1241 as_fatal (_("Internal Error: Can't hash %s: %s"),
1242 (optab - 1)->name,
1243 hash_err);
1244 }
1245 if (optab->name == NULL)
1246 break;
1247 core_optab = (templates *) xmalloc (sizeof (templates));
1248 core_optab->start = optab;
1249 }
1250 }
1251 }
1252
47926f60 1253 /* Initialize reg_hash hash table. */
252b5132
RH		 1254 reg_hash = hash_new ();
1255 {
29b0f896 1256 const reg_entry *regtab;
252b5132
RH		 1257
1258 for (regtab = i386_regtab;
1259 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1260 regtab++)
1261 {
1262 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1263 if (hash_err)
3e73aa7c
JH		 1264 as_fatal (_("Internal Error: Can't hash %s: %s"),
1265 regtab->reg_name,
1266 hash_err);
252b5132
RH		 1267 }
1268 }
1269
47926f60 1270 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1271 {
29b0f896
AM		 1272 int c;
1273 char *p;
252b5132
RH		 1274
1275 for (c = 0; c < 256; c++)
1276 {
3882b010 1277 if (ISDIGIT (c))
252b5132
RH		 1278 {
1279 digit_chars[c] = c;
1280 mnemonic_chars[c] = c;
1281 register_chars[c] = c;
1282 operand_chars[c] = c;
1283 }
3882b010 1284 else if (ISLOWER (c))
252b5132
RH		 1285 {
1286 mnemonic_chars[c] = c;
1287 register_chars[c] = c;
1288 operand_chars[c] = c;
1289 }
3882b010 1290 else if (ISUPPER (c))
252b5132 1291 {
3882b010 1292 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1293 register_chars[c] = mnemonic_chars[c];
1294 operand_chars[c] = c;
1295 }
1296
3882b010 1297 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1298 identifier_chars[c] = c;
1299 else if (c >= 128)
1300 {
1301 identifier_chars[c] = c;
1302 operand_chars[c] = c;
1303 }
1304 }
1305
1306#ifdef LEX_AT
1307 identifier_chars['@'] = '@';
32137342
NC		 1308#endif
1309#ifdef LEX_QM
1310 identifier_chars['?'] = '?';
1311 operand_chars['?'] = '?';
252b5132 1312#endif
252b5132 1313 digit_chars['-'] = '-';
791fe849 1314 mnemonic_chars['-'] = '-';
252b5132
RH		 1315 identifier_chars['_'] = '_';
1316 identifier_chars['.'] = '.';
1317
1318 for (p = operand_special_chars; *p != '\0'; p++)
1319 operand_chars[(unsigned char) *p] = *p;
1320 }
1321
1322#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1323 if (IS_ELF)
252b5132
RH		 1324 {
1325 record_alignment (text_section, 2);
1326 record_alignment (data_section, 2);
1327 record_alignment (bss_section, 2);
1328 }
1329#endif
a4447b93
RH		 1330
1331 if (flag_code == CODE_64BIT)
1332 {
1333 x86_dwarf2_return_column = 16;
1334 x86_cie_data_alignment = -8;
1335 }
1336 else
1337 {
1338 x86_dwarf2_return_column = 8;
1339 x86_cie_data_alignment = -4;
1340 }
252b5132
RH		 1341}
1342
1343void
1344i386_print_statistics (file)
1345 FILE *file;
1346{
1347 hash_print_statistics (file, "i386 opcode", op_hash);
1348 hash_print_statistics (file, "i386 register", reg_hash);
1349}
1350\f
252b5132
RH		 1351#ifdef DEBUG386
1352
ce8a8b2f 1353/* Debugging routines for md_assemble. */
252b5132
RH		 1354static void pi PARAMS ((char *, i386_insn *));
1355static void pte PARAMS ((template *));
1356static void pt PARAMS ((unsigned int));
1357static void pe PARAMS ((expressionS *));
1358static void ps PARAMS ((symbolS *));
1359
1360static void
1361pi (line, x)
1362 char *line;
1363 i386_insn *x;
1364{
09f131f2 1365 unsigned int i;
252b5132
RH		 1366
1367 fprintf (stdout, "%s: template ", line);
1368 pte (&x->tm);
09f131f2
JH		 1369 fprintf (stdout, " address: base %s index %s scale %x\n",
1370 x->base_reg ? x->base_reg->reg_name : "none",
1371 x->index_reg ? x->index_reg->reg_name : "none",
1372 x->log2_scale_factor);
1373 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1374 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1375 fprintf (stdout, " sib: base %x index %x scale %x\n",
1376 x->sib.base, x->sib.index, x->sib.scale);
1377 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1378 (x->rex & REX_MODE64) != 0,
1379 (x->rex & REX_EXTX) != 0,
1380 (x->rex & REX_EXTY) != 0,
1381 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1382 for (i = 0; i < x->operands; i++)
1383 {
1384 fprintf (stdout, " #%d: ", i + 1);
1385 pt (x->types[i]);
1386 fprintf (stdout, "\n");
1387 if (x->types[i]
3f4438ab 1388 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1389 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1390 if (x->types[i] & Imm)
520dc8e8 1391 pe (x->op[i].imms);
252b5132 1392 if (x->types[i] & Disp)
520dc8e8 1393 pe (x->op[i].disps);
252b5132
RH		 1394 }
1395}
1396
1397static void
1398pte (t)
1399 template *t;
1400{
09f131f2 1401 unsigned int i;
252b5132 1402 fprintf (stdout, " %d operands ", t->operands);
47926f60 1403 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1404 if (t->extension_opcode != None)
1405 fprintf (stdout, "ext %x ", t->extension_opcode);
1406 if (t->opcode_modifier & D)
1407 fprintf (stdout, "D");
1408 if (t->opcode_modifier & W)
1409 fprintf (stdout, "W");
1410 fprintf (stdout, "\n");
1411 for (i = 0; i < t->operands; i++)
1412 {
1413 fprintf (stdout, " #%d type ", i + 1);
1414 pt (t->operand_types[i]);
1415 fprintf (stdout, "\n");
1416 }
1417}
1418
1419static void
1420pe (e)
1421 expressionS *e;
1422{
24eab124 1423 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1424 fprintf (stdout, " add_number %ld (%lx)\n",
1425 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1426 if (e->X_add_symbol)
1427 {
1428 fprintf (stdout, " add_symbol ");
1429 ps (e->X_add_symbol);
1430 fprintf (stdout, "\n");
1431 }
1432 if (e->X_op_symbol)
1433 {
1434 fprintf (stdout, " op_symbol ");
1435 ps (e->X_op_symbol);
1436 fprintf (stdout, "\n");
1437 }
1438}
1439
1440static void
1441ps (s)
1442 symbolS *s;
1443{
1444 fprintf (stdout, "%s type %s%s",
1445 S_GET_NAME (s),
1446 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1447 segment_name (S_GET_SEGMENT (s)));
1448}
1449
7b81dfbb 1450static struct type_name
252b5132
RH		 1451 {
1452 unsigned int mask;
1453 char *tname;
1454 }
7b81dfbb 1455const type_names[] =
252b5132
RH		 1456{
1457 { Reg8, "r8" },
1458 { Reg16, "r16" },
1459 { Reg32, "r32" },
09f131f2 1460 { Reg64, "r64" },
252b5132
RH		 1461 { Imm8, "i8" },
1462 { Imm8S, "i8s" },
1463 { Imm16, "i16" },
1464 { Imm32, "i32" },
09f131f2
JH		 1465 { Imm32S, "i32s" },
1466 { Imm64, "i64" },
252b5132
RH		 1467 { Imm1, "i1" },
1468 { BaseIndex, "BaseIndex" },
1469 { Disp8, "d8" },
1470 { Disp16, "d16" },
1471 { Disp32, "d32" },
09f131f2
JH		 1472 { Disp32S, "d32s" },
1473 { Disp64, "d64" },
252b5132
RH		 1474 { InOutPortReg, "InOutPortReg" },
1475 { ShiftCount, "ShiftCount" },
1476 { Control, "control reg" },
1477 { Test, "test reg" },
1478 { Debug, "debug reg" },
1479 { FloatReg, "FReg" },
1480 { FloatAcc, "FAcc" },
1481 { SReg2, "SReg2" },
1482 { SReg3, "SReg3" },
1483 { Acc, "Acc" },
1484 { JumpAbsolute, "Jump Absolute" },
1485 { RegMMX, "rMMX" },
3f4438ab 1486 { RegXMM, "rXMM" },
252b5132
RH		 1487 { EsSeg, "es" },
1488 { 0, "" }
1489};
1490
1491static void
1492pt (t)
1493 unsigned int t;
1494{
29b0f896 1495 const struct type_name *ty;
252b5132 1496
09f131f2
JH		 1497 for (ty = type_names; ty->mask; ty++)
1498 if (t & ty->mask)
1499 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1500 fflush (stdout);
1501}
1502
1503#endif /* DEBUG386 */
1504\f
252b5132 1505static bfd_reloc_code_real_type
3956db08 1506reloc (unsigned int size,
64e74474
AM		 1507 int pcrel,
1508 int sign,
1509 bfd_reloc_code_real_type other)
252b5132 1510{
47926f60 1511 if (other != NO_RELOC)
3956db08
JB		 1512 {
1513 reloc_howto_type *reloc;
1514
1515 if (size == 8)
1516 switch (other)
1517 {
64e74474
AM		 1518 case BFD_RELOC_X86_64_GOT32:
1519 return BFD_RELOC_X86_64_GOT64;
1520 break;
1521 case BFD_RELOC_X86_64_PLTOFF64:
1522 return BFD_RELOC_X86_64_PLTOFF64;
1523 break;
1524 case BFD_RELOC_X86_64_GOTPC32:
1525 other = BFD_RELOC_X86_64_GOTPC64;
1526 break;
1527 case BFD_RELOC_X86_64_GOTPCREL:
1528 other = BFD_RELOC_X86_64_GOTPCREL64;
1529 break;
1530 case BFD_RELOC_X86_64_TPOFF32:
1531 other = BFD_RELOC_X86_64_TPOFF64;
1532 break;
1533 case BFD_RELOC_X86_64_DTPOFF32:
1534 other = BFD_RELOC_X86_64_DTPOFF64;
1535 break;
1536 default:
1537 break;
3956db08 1538 }
e05278af
JB		 1539
1540 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1541 if (size == 4 && flag_code != CODE_64BIT)
1542 sign = -1;
1543
3956db08
JB		 1544 reloc = bfd_reloc_type_lookup (stdoutput, other);
1545 if (!reloc)
1546 as_bad (_("unknown relocation (%u)"), other);
1547 else if (size != bfd_get_reloc_size (reloc))
1548 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1549 bfd_get_reloc_size (reloc),
1550 size);
1551 else if (pcrel && !reloc->pc_relative)
1552 as_bad (_("non-pc-relative relocation for pc-relative field"));
1553 else if ((reloc->complain_on_overflow == complain_overflow_signed
1554 && !sign)
1555 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1556 && sign > 0))
3956db08
JB		 1557 as_bad (_("relocated field and relocation type differ in signedness"));
1558 else
1559 return other;
1560 return NO_RELOC;
1561 }
252b5132
RH		 1562
1563 if (pcrel)
1564 {
3e73aa7c 1565 if (!sign)
3956db08 1566 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1567 switch (size)
1568 {
1569 case 1: return BFD_RELOC_8_PCREL;
1570 case 2: return BFD_RELOC_16_PCREL;
1571 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1572 case 8: return BFD_RELOC_64_PCREL;
252b5132 1573 }
3956db08 1574 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1575 }
1576 else
1577 {
3956db08 1578 if (sign > 0)
e5cb08ac 1579 switch (size)
3e73aa7c
JH		 1580 {
1581 case 4: return BFD_RELOC_X86_64_32S;
1582 }
1583 else
1584 switch (size)
1585 {
1586 case 1: return BFD_RELOC_8;
1587 case 2: return BFD_RELOC_16;
1588 case 4: return BFD_RELOC_32;
1589 case 8: return BFD_RELOC_64;
1590 }
3956db08
JB		 1591 as_bad (_("cannot do %s %u byte relocation"),
1592 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1593 }
1594
bfb32b52 1595 abort ();
252b5132
RH		 1596 return BFD_RELOC_NONE;
1597}
1598
47926f60
KH		 1599/* Here we decide which fixups can be adjusted to make them relative to
1600 the beginning of the section instead of the symbol. Basically we need
1601 to make sure that the dynamic relocations are done correctly, so in
1602 some cases we force the original symbol to be used. */
1603
252b5132 1604int
c0c949c7 1605tc_i386_fix_adjustable (fixP)
31312f95 1606 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1607{
6d249963 1608#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1609 if (!IS_ELF)
31312f95
AM		 1610 return 1;
1611
a161fe53
AM		 1612 /* Don't adjust pc-relative references to merge sections in 64-bit
1613 mode. */
1614 if (use_rela_relocations
1615 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1616 && fixP->fx_pcrel)
252b5132 1617 return 0;
31312f95 1618
8d01d9a9
AJ		 1619 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1620 and changed later by validate_fix. */
1621 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1622 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1623 return 0;
1624
ce8a8b2f 1625 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1626 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1627 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1628 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1629 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1630 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1631 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1632 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1633 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1634 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1635 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1636 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1637 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1638 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1639 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1640 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1641 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1642 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1643 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1644 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1645 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1646 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1647 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1648 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1649 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1650 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1651 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1652 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1653 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1654 return 0;
31312f95 1655#endif
252b5132
RH		 1656 return 1;
1657}
252b5132 1658
29b0f896 1659static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1660
1661static int
252b5132 1662intel_float_operand (mnemonic)
29b0f896 1663 const char *mnemonic;
252b5132 1664{
9306ca4a
JB		 1665 /* Note that the value returned is meaningful only for opcodes with (memory)
1666 operands, hence the code here is free to improperly handle opcodes that
1667 have no operands (for better performance and smaller code). */
1668
1669 if (mnemonic[0] != 'f')
1670 return 0; /* non-math */
1671
1672 switch (mnemonic[1])
1673 {
1674 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1675 the fs segment override prefix not currently handled because no
1676 call path can make opcodes without operands get here */
1677 case 'i':
1678 return 2 /* integer op */;
1679 case 'l':
1680 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1681 return 3; /* fldcw/fldenv */
1682 break;
1683 case 'n':
1684 if (mnemonic[2] != 'o' /* fnop */)
1685 return 3; /* non-waiting control op */
1686 break;
1687 case 'r':
1688 if (mnemonic[2] == 's')
1689 return 3; /* frstor/frstpm */
1690 break;
1691 case 's':
1692 if (mnemonic[2] == 'a')
1693 return 3; /* fsave */
1694 if (mnemonic[2] == 't')
1695 {
1696 switch (mnemonic[3])
1697 {
1698 case 'c': /* fstcw */
1699 case 'd': /* fstdw */
1700 case 'e': /* fstenv */
1701 case 's': /* fsts[gw] */
1702 return 3;
1703 }
1704 }
1705 break;
1706 case 'x':
1707 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1708 return 0; /* fxsave/fxrstor are not really math ops */
1709 break;
1710 }
252b5132 1711
9306ca4a 1712 return 1;
252b5132
RH		 1713}
1714
1715/* This is the guts of the machine-dependent assembler. LINE points to a
1716 machine dependent instruction. This function is supposed to emit
1717 the frags/bytes it assembles to. */
1718
1719void
1720md_assemble (line)
1721 char *line;
1722{
252b5132 1723 int j;
252b5132
RH		 1724 char mnemonic[MAX_MNEM_SIZE];
1725
47926f60 1726 /* Initialize globals. */
252b5132
RH		 1727 memset (&i, '\0', sizeof (i));
1728 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1729 i.reloc[j] = NO_RELOC;
252b5132
RH		 1730 memset (disp_expressions, '\0', sizeof (disp_expressions));
1731 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1732 save_stack_p = save_stack;
252b5132
RH		 1733
1734 /* First parse an instruction mnemonic & call i386_operand for the operands.
1735 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1736 start of a (possibly prefixed) mnemonic. */
252b5132 1737
29b0f896
AM		 1738 line = parse_insn (line, mnemonic);
1739 if (line == NULL)
1740 return;
252b5132 1741
29b0f896
AM		 1742 line = parse_operands (line, mnemonic);
1743 if (line == NULL)
1744 return;
252b5132 1745
050dfa73
MM		 1746 /* The order of the immediates should be reversed
1747 for 2 immediates extrq and insertq instructions */
1748 if ((i.imm_operands == 2) &&
1749 ((strcmp (mnemonic, "extrq") == 0)
1750 || (strcmp (mnemonic, "insertq") == 0)))
1751 {
1752 swap_imm_operands ();
1753 /* "extrq" and insertq" are the only two instructions whose operands
1754 have to be reversed even though they have two immediate operands.
1755 */
1756 if (intel_syntax)
1757 swap_operands ();
1758 }
1759
29b0f896
AM		 1760 /* Now we've parsed the mnemonic into a set of templates, and have the
1761 operands at hand. */
1762
1763 /* All intel opcodes have reversed operands except for "bound" and
1764 "enter". We also don't reverse intersegment "jmp" and "call"
1765 instructions with 2 immediate operands so that the immediate segment
050dfa73 1766 precedes the offset, as it does when in AT&T mode. */
29b0f896
AM		 1767 if (intel_syntax && i.operands > 1
1768 && (strcmp (mnemonic, "bound") != 0)
30123838 1769 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1770 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1771 swap_operands ();
1772
1773 if (i.imm_operands)
1774 optimize_imm ();
1775
b300c311
L		 1776 /* Don't optimize displacement for movabs since it only takes 64bit
1777 displacement. */
1778 if (i.disp_operands
1779 && (flag_code != CODE_64BIT
1780 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1781 optimize_disp ();
1782
1783 /* Next, we find a template that matches the given insn,
1784 making sure the overlap of the given operands types is consistent
1785 with the template operand types. */
252b5132 1786
29b0f896
AM		 1787 if (!match_template ())
1788 return;
252b5132 1789
cd61ebfe
AM		 1790 if (intel_syntax)
1791 {
1792 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1793 if (SYSV386_COMPAT
1794 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1795 i.tm.base_opcode ^= FloatR;
1796
1797 /* Zap movzx and movsx suffix. The suffix may have been set from
1798 "word ptr" or "byte ptr" on the source operand, but we'll use
1799 the suffix later to choose the destination register. */
1800 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1801 {
1802 if (i.reg_operands < 2
1803 && !i.suffix
1804 && (~i.tm.opcode_modifier
1805 & (No_bSuf
1806 | No_wSuf
1807 | No_lSuf
1808 | No_sSuf
1809 | No_xSuf
1810 | No_qSuf)))
1811 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1812
1813 i.suffix = 0;
1814 }
cd61ebfe 1815 }
24eab124 1816
29b0f896
AM		 1817 if (i.tm.opcode_modifier & FWait)
1818 if (!add_prefix (FWAIT_OPCODE))
1819 return;
252b5132 1820
29b0f896
AM		 1821 /* Check string instruction segment overrides. */
1822 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1823 {
1824 if (!check_string ())
5dd0794d 1825 return;
29b0f896 1826 }
5dd0794d 1827
29b0f896
AM		 1828 if (!process_suffix ())
1829 return;
e413e4e9 1830
29b0f896
AM		 1831 /* Make still unresolved immediate matches conform to size of immediate
1832 given in i.suffix. */
1833 if (!finalize_imm ())
1834 return;
252b5132 1835
29b0f896
AM		 1836 if (i.types[0] & Imm1)
1837 i.imm_operands = 0; /* kludge for shift insns. */
1838 if (i.types[0] & ImplicitRegister)
1839 i.reg_operands--;
1840 if (i.types[1] & ImplicitRegister)
1841 i.reg_operands--;
1842 if (i.types[2] & ImplicitRegister)
1843 i.reg_operands--;
252b5132 1844
29b0f896
AM		 1845 if (i.tm.opcode_modifier & ImmExt)
1846 {
02fc3089
L		 1847 expressionS *exp;
1848
ca164297
L		 1849 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1850 {
67c1ffbe 1851 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1852 operands with an opcode suffix which is coded in the same
1853 place as an 8-bit immediate field would be. Here we check
1854 those operands and remove them afterwards. */
1855 unsigned int x;
1856
a4622f40 1857 for (x = 0; x < i.operands; x++)
ca164297
L		 1858 if (i.op[x].regs->reg_num != x)
1859 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1860 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1861 i.operands = 0;
1862 }
1863
29b0f896
AM		 1864 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1865 opcode suffix which is coded in the same place as an 8-bit
1866 immediate field would be. Here we fake an 8-bit immediate
1867 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1868
29b0f896 1869 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1870
29b0f896
AM		 1871 exp = &im_expressions[i.imm_operands++];
1872 i.op[i.operands].imms = exp;
1873 i.types[i.operands++] = Imm8;
1874 exp->X_op = O_constant;
1875 exp->X_add_number = i.tm.extension_opcode;
1876 i.tm.extension_opcode = None;
1877 }
252b5132 1878
29b0f896
AM		 1879 /* For insns with operands there are more diddles to do to the opcode. */
1880 if (i.operands)
1881 {
1882 if (!process_operands ())
1883 return;
1884 }
1885 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1886 {
1887 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1888 as_warn (_("translating to `%sp'"), i.tm.name);
1889 }
252b5132 1890
29b0f896
AM		 1891 /* Handle conversion of 'int $3' --> special int3 insn. */
1892 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1893 {
1894 i.tm.base_opcode = INT3_OPCODE;
1895 i.imm_operands = 0;
1896 }
252b5132 1897
29b0f896
AM		 1898 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1899 && i.op[0].disps->X_op == O_constant)
1900 {
1901 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1902 the absolute address given by the constant. Since ix86 jumps and
1903 calls are pc relative, we need to generate a reloc. */
1904 i.op[0].disps->X_add_symbol = &abs_symbol;
1905 i.op[0].disps->X_op = O_symbol;
1906 }
252b5132 1907
29b0f896
AM		 1908 if ((i.tm.opcode_modifier & Rex64) != 0)
1909 i.rex |= REX_MODE64;
252b5132 1910
29b0f896
AM		 1911 /* For 8 bit registers we need an empty rex prefix. Also if the
1912 instruction already has a prefix, we need to convert old
1913 registers to new ones. */
773f551c 1914
29b0f896
AM		 1915 if (((i.types[0] & Reg8) != 0
1916 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1917 || ((i.types[1] & Reg8) != 0
1918 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1919 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1920 && i.rex != 0))
1921 {
1922 int x;
726c5dcd 1923
29b0f896
AM		 1924 i.rex |= REX_OPCODE;
1925 for (x = 0; x < 2; x++)
1926 {
1927 /* Look for 8 bit operand that uses old registers. */
1928 if ((i.types[x] & Reg8) != 0
1929 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1930 {
29b0f896
AM		 1931 /* In case it is "hi" register, give up. */
1932 if (i.op[x].regs->reg_num > 3)
0477af35 1933 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1934 i.op[x].regs->reg_name);
773f551c 1935
29b0f896
AM		 1936 /* Otherwise it is equivalent to the extended register.
1937 Since the encoding doesn't change this is merely
1938 cosmetic cleanup for debug output. */
1939
1940 i.op[x].regs = i.op[x].regs + 8;
773f551c 1941 }
29b0f896
AM		 1942 }
1943 }
773f551c 1944
29b0f896
AM		 1945 if (i.rex != 0)
1946 add_prefix (REX_OPCODE | i.rex);
1947
9103f4f4
L		 1948 /* Record what ISA we have generated so far. */
1949 cpu_arch_isa_flags |= i.tm.cpu_flags;
1950
29b0f896
AM		 1951 /* We are ready to output the insn. */
1952 output_insn ();
1953}
1954
1955static char *
1956parse_insn (line, mnemonic)
1957 char *line;
1958 char *mnemonic;
1959{
1960 char *l = line;
1961 char *token_start = l;
1962 char *mnem_p;
5c6af06e
JB		 1963 int supported;
1964 const template *t;
29b0f896
AM		 1965
1966 /* Non-zero if we found a prefix only acceptable with string insns. */
1967 const char *expecting_string_instruction = NULL;
45288df1 1968
29b0f896
AM		 1969 while (1)
1970 {
1971 mnem_p = mnemonic;
1972 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1973 {
1974 mnem_p++;
1975 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1976 {
29b0f896
AM		 1977 as_bad (_("no such instruction: `%s'"), token_start);
1978 return NULL;
1979 }
1980 l++;
1981 }
1982 if (!is_space_char (*l)
1983 && *l != END_OF_INSN
e44823cf
JB		 1984 && (intel_syntax
1985 || (*l != PREFIX_SEPARATOR
1986 && *l != ',')))
29b0f896
AM		 1987 {
1988 as_bad (_("invalid character %s in mnemonic"),
1989 output_invalid (*l));
1990 return NULL;
1991 }
1992 if (token_start == l)
1993 {
e44823cf 1994 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1995 as_bad (_("expecting prefix; got nothing"));
1996 else
1997 as_bad (_("expecting mnemonic; got nothing"));
1998 return NULL;
1999 }
45288df1 2000
29b0f896
AM		 2001 /* Look up instruction (or prefix) via hash table. */
2002 current_templates = hash_find (op_hash, mnemonic);
47926f60 2003
29b0f896
AM		 2004 if (*l != END_OF_INSN
2005 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2006 && current_templates
2007 && (current_templates->start->opcode_modifier & IsPrefix))
2008 {
2dd88dca
JB		 2009 if (current_templates->start->cpu_flags
2010 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
2011 {
2012 as_bad ((flag_code != CODE_64BIT
2013 ? _("`%s' is only supported in 64-bit mode")
2014 : _("`%s' is not supported in 64-bit mode")),
2015 current_templates->start->name);
2016 return NULL;
2017 }
29b0f896
AM		 2018 /* If we are in 16-bit mode, do not allow addr16 or data16.
2019 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2020 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
2021 && flag_code != CODE_64BIT
2022 && (((current_templates->start->opcode_modifier & Size32) != 0)
2023 ^ (flag_code == CODE_16BIT)))
2024 {
2025 as_bad (_("redundant %s prefix"),
2026 current_templates->start->name);
2027 return NULL;
45288df1 2028 }
29b0f896
AM		 2029 /* Add prefix, checking for repeated prefixes. */
2030 switch (add_prefix (current_templates->start->base_opcode))
2031 {
2032 case 0:
2033 return NULL;
2034 case 2:
2035 expecting_string_instruction = current_templates->start->name;
2036 break;
2037 }
2038 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2039 token_start = ++l;
2040 }
2041 else
2042 break;
2043 }
45288df1 2044
29b0f896
AM		 2045 if (!current_templates)
2046 {
2047 /* See if we can get a match by trimming off a suffix. */
2048 switch (mnem_p[-1])
2049 {
2050 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2051 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2052 i.suffix = SHORT_MNEM_SUFFIX;
2053 else
29b0f896
AM		 2054 case BYTE_MNEM_SUFFIX:
2055 case QWORD_MNEM_SUFFIX:
2056 i.suffix = mnem_p[-1];
2057 mnem_p[-1] = '\0';
2058 current_templates = hash_find (op_hash, mnemonic);
2059 break;
2060 case SHORT_MNEM_SUFFIX:
2061 case LONG_MNEM_SUFFIX:
2062 if (!intel_syntax)
2063 {
2064 i.suffix = mnem_p[-1];
2065 mnem_p[-1] = '\0';
2066 current_templates = hash_find (op_hash, mnemonic);
2067 }
2068 break;
252b5132 2069
29b0f896
AM		 2070 /* Intel Syntax. */
2071 case 'd':
2072 if (intel_syntax)
2073 {
9306ca4a 2074 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2075 i.suffix = SHORT_MNEM_SUFFIX;
2076 else
2077 i.suffix = LONG_MNEM_SUFFIX;
2078 mnem_p[-1] = '\0';
2079 current_templates = hash_find (op_hash, mnemonic);
2080 }
2081 break;
2082 }
2083 if (!current_templates)
2084 {
2085 as_bad (_("no such instruction: `%s'"), token_start);
2086 return NULL;
2087 }
2088 }
252b5132 2089
29b0f896
AM		 2090 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
2091 {
2092 /* Check for a branch hint. We allow ",pt" and ",pn" for
2093 predict taken and predict not taken respectively.
2094 I'm not sure that branch hints actually do anything on loop
2095 and jcxz insns (JumpByte) for current Pentium4 chips. They
2096 may work in the future and it doesn't hurt to accept them
2097 now. */
2098 if (l[0] == ',' && l[1] == 'p')
2099 {
2100 if (l[2] == 't')
2101 {
2102 if (!add_prefix (DS_PREFIX_OPCODE))
2103 return NULL;
2104 l += 3;
2105 }
2106 else if (l[2] == 'n')
2107 {
2108 if (!add_prefix (CS_PREFIX_OPCODE))
2109 return NULL;
2110 l += 3;
2111 }
2112 }
2113 }
2114 /* Any other comma loses. */
2115 if (*l == ',')
2116 {
2117 as_bad (_("invalid character %s in mnemonic"),
2118 output_invalid (*l));
2119 return NULL;
2120 }
252b5132 2121
29b0f896 2122 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2123 supported = 0;
2124 for (t = current_templates->start; t < current_templates->end; ++t)
2125 {
2126 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
2127 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 2128 supported |= 1;
5c6af06e 2129 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 2130 supported |= 2;
5c6af06e
JB		 2131 }
2132 if (!(supported & 2))
2133 {
2134 as_bad (flag_code == CODE_64BIT
2135 ? _("`%s' is not supported in 64-bit mode")
2136 : _("`%s' is only supported in 64-bit mode"),
2137 current_templates->start->name);
2138 return NULL;
2139 }
2140 if (!(supported & 1))
29b0f896 2141 {
5c6af06e
JB		 2142 as_warn (_("`%s' is not supported on `%s%s'"),
2143 current_templates->start->name,
2144 cpu_arch_name,
2145 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 2146 }
2147 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
2148 {
2149 as_warn (_("use .code16 to ensure correct addressing mode"));
2150 }
252b5132 2151
29b0f896 2152 /* Check for rep/repne without a string instruction. */
f41bbced 2153 if (expecting_string_instruction)
29b0f896 2154 {
f41bbced
JB		 2155 static templates override;
2156
2157 for (t = current_templates->start; t < current_templates->end; ++t)
2158 if (t->opcode_modifier & IsString)
2159 break;
2160 if (t >= current_templates->end)
2161 {
2162 as_bad (_("expecting string instruction after `%s'"),
64e74474 2163 expecting_string_instruction);
f41bbced
JB		 2164 return NULL;
2165 }
2166 for (override.start = t; t < current_templates->end; ++t)
2167 if (!(t->opcode_modifier & IsString))
2168 break;
2169 override.end = t;
2170 current_templates = &override;
29b0f896 2171 }
252b5132 2172
29b0f896
AM		 2173 return l;
2174}
252b5132 2175
29b0f896
AM		 2176static char *
2177parse_operands (l, mnemonic)
2178 char *l;
2179 const char *mnemonic;
2180{
2181 char *token_start;
3138f287 2182
29b0f896
AM		 2183 /* 1 if operand is pending after ','. */
2184 unsigned int expecting_operand = 0;
252b5132 2185
29b0f896
AM		 2186 /* Non-zero if operand parens not balanced. */
2187 unsigned int paren_not_balanced;
2188
2189 while (*l != END_OF_INSN)
2190 {
2191 /* Skip optional white space before operand. */
2192 if (is_space_char (*l))
2193 ++l;
2194 if (!is_operand_char (*l) && *l != END_OF_INSN)
2195 {
2196 as_bad (_("invalid character %s before operand %d"),
2197 output_invalid (*l),
2198 i.operands + 1);
2199 return NULL;
2200 }
2201 token_start = l; /* after white space */
2202 paren_not_balanced = 0;
2203 while (paren_not_balanced || *l != ',')
2204 {
2205 if (*l == END_OF_INSN)
2206 {
2207 if (paren_not_balanced)
2208 {
2209 if (!intel_syntax)
2210 as_bad (_("unbalanced parenthesis in operand %d."),
2211 i.operands + 1);
2212 else
2213 as_bad (_("unbalanced brackets in operand %d."),
2214 i.operands + 1);
2215 return NULL;
2216 }
2217 else
2218 break; /* we are done */
2219 }
2220 else if (!is_operand_char (*l) && !is_space_char (*l))
2221 {
2222 as_bad (_("invalid character %s in operand %d"),
2223 output_invalid (*l),
2224 i.operands + 1);
2225 return NULL;
2226 }
2227 if (!intel_syntax)
2228 {
2229 if (*l == '(')
2230 ++paren_not_balanced;
2231 if (*l == ')')
2232 --paren_not_balanced;
2233 }
2234 else
2235 {
2236 if (*l == '[')
2237 ++paren_not_balanced;
2238 if (*l == ']')
2239 --paren_not_balanced;
2240 }
2241 l++;
2242 }
2243 if (l != token_start)
2244 { /* Yes, we've read in another operand. */
2245 unsigned int operand_ok;
2246 this_operand = i.operands++;
2247 if (i.operands > MAX_OPERANDS)
2248 {
2249 as_bad (_("spurious operands; (%d operands/instruction max)"),
2250 MAX_OPERANDS);
2251 return NULL;
2252 }
2253 /* Now parse operand adding info to 'i' as we go along. */
2254 END_STRING_AND_SAVE (l);
2255
2256 if (intel_syntax)
2257 operand_ok =
2258 i386_intel_operand (token_start,
2259 intel_float_operand (mnemonic));
2260 else
2261 operand_ok = i386_operand (token_start);
2262
2263 RESTORE_END_STRING (l);
2264 if (!operand_ok)
2265 return NULL;
2266 }
2267 else
2268 {
2269 if (expecting_operand)
2270 {
2271 expecting_operand_after_comma:
2272 as_bad (_("expecting operand after ','; got nothing"));
2273 return NULL;
2274 }
2275 if (*l == ',')
2276 {
2277 as_bad (_("expecting operand before ','; got nothing"));
2278 return NULL;
2279 }
2280 }
7f3f1ea2 2281
29b0f896
AM		 2282 /* Now *l must be either ',' or END_OF_INSN. */
2283 if (*l == ',')
2284 {
2285 if (*++l == END_OF_INSN)
2286 {
2287 /* Just skip it, if it's \n complain. */
2288 goto expecting_operand_after_comma;
2289 }
2290 expecting_operand = 1;
2291 }
2292 }
2293 return l;
2294}
7f3f1ea2 2295
050dfa73
MM		 2296static void
2297swap_imm_operands ()
2298{
2299 union i386_op temp_op;
2300 unsigned int temp_type;
2301 enum bfd_reloc_code_real temp_reloc;
2302 int xchg1 = 0;
2303 int xchg2 = 1;
2304
2305 temp_type = i.types[xchg2];
2306 i.types[xchg2] = i.types[xchg1];
2307 i.types[xchg1] = temp_type;
2308 temp_op = i.op[xchg2];
2309 i.op[xchg2] = i.op[xchg1];
2310 i.op[xchg1] = temp_op;
2311 temp_reloc = i.reloc[xchg2];
2312 i.reloc[xchg2] = i.reloc[xchg1];
2313 i.reloc[xchg1] = temp_reloc;
2314}
2315
2316
29b0f896
AM		 2317static void
2318swap_operands ()
2319{
2320 union i386_op temp_op;
2321 unsigned int temp_type;
f86103b7 2322 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2323 int xchg1 = 0;
2324 int xchg2 = 0;
252b5132 2325
050dfa73
MM		 2326 if (i.operands == 4)
2327 /* There will be two exchanges in a 4 operand instruction.
2328 First exchange is the done inside this block.(1st and 4rth operand)
2329 The next exchange is done outside this block.(2nd and 3rd operand) */
2330 {
2331 xchg1 = 0;
2332 xchg2 = 3;
2333 temp_type = i.types[xchg2];
2334 i.types[xchg2] = i.types[xchg1];
2335 i.types[xchg1] = temp_type;
2336 temp_op = i.op[xchg2];
2337 i.op[xchg2] = i.op[xchg1];
2338 i.op[xchg1] = temp_op;
2339 temp_reloc = i.reloc[xchg2];
2340 i.reloc[xchg2] = i.reloc[xchg1];
2341 i.reloc[xchg1] = temp_reloc;
2342 xchg1 = 1;
2343 xchg2 = 2;
2344 }
2345
29b0f896
AM		 2346 if (i.operands == 2)
2347 {
2348 xchg1 = 0;
2349 xchg2 = 1;
2350 }
2351 else if (i.operands == 3)
2352 {
2353 xchg1 = 0;
2354 xchg2 = 2;
2355 }
2356 temp_type = i.types[xchg2];
2357 i.types[xchg2] = i.types[xchg1];
2358 i.types[xchg1] = temp_type;
2359 temp_op = i.op[xchg2];
2360 i.op[xchg2] = i.op[xchg1];
2361 i.op[xchg1] = temp_op;
2362 temp_reloc = i.reloc[xchg2];
2363 i.reloc[xchg2] = i.reloc[xchg1];
2364 i.reloc[xchg1] = temp_reloc;
2365
2366 if (i.mem_operands == 2)
2367 {
2368 const seg_entry *temp_seg;
2369 temp_seg = i.seg[0];
2370 i.seg[0] = i.seg[1];
2371 i.seg[1] = temp_seg;
2372 }
2373}
252b5132 2374
29b0f896
AM		 2375/* Try to ensure constant immediates are represented in the smallest
2376 opcode possible. */
2377static void
2378optimize_imm ()
2379{
2380 char guess_suffix = 0;
2381 int op;
252b5132 2382
29b0f896
AM		 2383 if (i.suffix)
2384 guess_suffix = i.suffix;
2385 else if (i.reg_operands)
2386 {
2387 /* Figure out a suffix from the last register operand specified.
2388 We can't do this properly yet, ie. excluding InOutPortReg,
2389 but the following works for instructions with immediates.
2390 In any case, we can't set i.suffix yet. */
2391 for (op = i.operands; --op >= 0;)
2392 if (i.types[op] & Reg)
252b5132 2393 {
29b0f896
AM		 2394 if (i.types[op] & Reg8)
2395 guess_suffix = BYTE_MNEM_SUFFIX;
2396 else if (i.types[op] & Reg16)
2397 guess_suffix = WORD_MNEM_SUFFIX;
2398 else if (i.types[op] & Reg32)
2399 guess_suffix = LONG_MNEM_SUFFIX;
2400 else if (i.types[op] & Reg64)
2401 guess_suffix = QWORD_MNEM_SUFFIX;
2402 break;
252b5132 2403 }
29b0f896
AM		 2404 }
2405 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2406 guess_suffix = WORD_MNEM_SUFFIX;
2407
2408 for (op = i.operands; --op >= 0;)
2409 if (i.types[op] & Imm)
2410 {
2411 switch (i.op[op].imms->X_op)
252b5132 2412 {
29b0f896
AM		 2413 case O_constant:
2414 /* If a suffix is given, this operand may be shortened. */
2415 switch (guess_suffix)
252b5132 2416 {
29b0f896
AM		 2417 case LONG_MNEM_SUFFIX:
2418 i.types[op] |= Imm32 | Imm64;
2419 break;
2420 case WORD_MNEM_SUFFIX:
2421 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2422 break;
2423 case BYTE_MNEM_SUFFIX:
2424 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2425 break;
252b5132 2426 }
252b5132 2427
29b0f896
AM		 2428 /* If this operand is at most 16 bits, convert it
2429 to a signed 16 bit number before trying to see
2430 whether it will fit in an even smaller size.
2431 This allows a 16-bit operand such as $0xffe0 to
2432 be recognised as within Imm8S range. */
2433 if ((i.types[op] & Imm16)
2434 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2435 {
29b0f896
AM		 2436 i.op[op].imms->X_add_number =
2437 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2438 }
2439 if ((i.types[op] & Imm32)
2440 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2441 == 0))
2442 {
2443 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2444 ^ ((offsetT) 1 << 31))
2445 - ((offsetT) 1 << 31));
2446 }
2447 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2448
29b0f896
AM		 2449 /* We must avoid matching of Imm32 templates when 64bit
2450 only immediate is available. */
2451 if (guess_suffix == QWORD_MNEM_SUFFIX)
2452 i.types[op] &= ~Imm32;
2453 break;
252b5132 2454
29b0f896
AM		 2455 case O_absent:
2456 case O_register:
2457 abort ();
2458
2459 /* Symbols and expressions. */
2460 default:
9cd96992
JB		 2461 /* Convert symbolic operand to proper sizes for matching, but don't
2462 prevent matching a set of insns that only supports sizes other
2463 than those matching the insn suffix. */
2464 {
2465 unsigned int mask, allowed = 0;
2466 const template *t;
2467
2468 for (t = current_templates->start; t < current_templates->end; ++t)
2469 allowed |= t->operand_types[op];
2470 switch (guess_suffix)
2471 {
2472 case QWORD_MNEM_SUFFIX:
2473 mask = Imm64 | Imm32S;
2474 break;
2475 case LONG_MNEM_SUFFIX:
2476 mask = Imm32;
2477 break;
2478 case WORD_MNEM_SUFFIX:
2479 mask = Imm16;
2480 break;
2481 case BYTE_MNEM_SUFFIX:
2482 mask = Imm8;
2483 break;
2484 default:
2485 mask = 0;
2486 break;
2487 }
64e74474
AM		 2488 if (mask & allowed)
2489 i.types[op] &= mask;
9cd96992 2490 }
29b0f896 2491 break;
252b5132 2492 }
29b0f896
AM		 2493 }
2494}
47926f60 2495
29b0f896
AM		 2496/* Try to use the smallest displacement type too. */
2497static void
2498optimize_disp ()
2499{
2500 int op;
3e73aa7c 2501
29b0f896 2502 for (op = i.operands; --op >= 0;)
b300c311 2503 if (i.types[op] & Disp)
252b5132 2504 {
b300c311 2505 if (i.op[op].disps->X_op == O_constant)
252b5132 2506 {
b300c311 2507 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2508
b300c311
L		 2509 if ((i.types[op] & Disp16)
2510 && (disp & ~(offsetT) 0xffff) == 0)
2511 {
2512 /* If this operand is at most 16 bits, convert
2513 to a signed 16 bit number and don't use 64bit
2514 displacement. */
2515 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2516 i.types[op] &= ~Disp64;
2517 }
2518 if ((i.types[op] & Disp32)
2519 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2520 {
2521 /* If this operand is at most 32 bits, convert
2522 to a signed 32 bit number and don't use 64bit
2523 displacement. */
2524 disp &= (((offsetT) 2 << 31) - 1);
2525 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2526 i.types[op] &= ~Disp64;
2527 }
2528 if (!disp && (i.types[op] & BaseIndex))
2529 {
2530 i.types[op] &= ~Disp;
2531 i.op[op].disps = 0;
2532 i.disp_operands--;
2533 }
2534 else if (flag_code == CODE_64BIT)
2535 {
2536 if (fits_in_signed_long (disp))
28a9d8f5
L		 2537 {
2538 i.types[op] &= ~Disp64;
2539 i.types[op] |= Disp32S;
2540 }
b300c311
L		 2541 if (fits_in_unsigned_long (disp))
2542 i.types[op] |= Disp32;
2543 }
2544 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2545 && fits_in_signed_byte (disp))
2546 i.types[op] |= Disp8;
252b5132 2547 }
67a4f2b7
AO		 2548 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2549 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2550 {
2551 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2552 i.op[op].disps, 0, i.reloc[op]);
2553 i.types[op] &= ~Disp;
2554 }
2555 else
b300c311
L		 2556 /* We only support 64bit displacement on constants. */
2557 i.types[op] &= ~Disp64;
252b5132 2558 }
29b0f896
AM		 2559}
2560
2561static int
2562match_template ()
2563{
2564 /* Points to template once we've found it. */
2565 const template *t;
2566 unsigned int overlap0, overlap1, overlap2;
2567 unsigned int found_reverse_match;
2568 int suffix_check;
2569
2570#define MATCH(overlap, given, template) \
2571 ((overlap & ~JumpAbsolute) \
2572 && (((given) & (BaseIndex | JumpAbsolute)) \
2573 == ((overlap) & (BaseIndex | JumpAbsolute))))
2574
2575 /* If given types r0 and r1 are registers they must be of the same type
2576 unless the expected operand type register overlap is null.
2577 Note that Acc in a template matches every size of reg. */
2578#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2579 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2580 || ((g0) & Reg) == ((g1) & Reg) \
2581 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2582
2583 overlap0 = 0;
2584 overlap1 = 0;
2585 overlap2 = 0;
2586 found_reverse_match = 0;
2587 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2588 ? No_bSuf
2589 : (i.suffix == WORD_MNEM_SUFFIX
2590 ? No_wSuf
2591 : (i.suffix == SHORT_MNEM_SUFFIX
2592 ? No_sSuf
2593 : (i.suffix == LONG_MNEM_SUFFIX
2594 ? No_lSuf
2595 : (i.suffix == QWORD_MNEM_SUFFIX
2596 ? No_qSuf
2597 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2598 ? No_xSuf : 0))))));
2599
45aa61fe 2600 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896
AM		 2601 {
2602 /* Must have right number of operands. */
2603 if (i.operands != t->operands)
2604 continue;
2605
2606 /* Check the suffix, except for some instructions in intel mode. */
2607 if ((t->opcode_modifier & suffix_check)
2608 && !(intel_syntax
9306ca4a 2609 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2610 continue;
2611
45aa61fe
AM		 2612 /* In general, don't allow 64-bit operands in 32-bit mode. */
2613 if (i.suffix == QWORD_MNEM_SUFFIX
2614 && flag_code != CODE_64BIT
2615 && (intel_syntax
2616 ? (!(t->opcode_modifier & IgnoreSize)
2617 && !intel_float_operand (t->name))
2618 : intel_float_operand (t->name) != 2)
2619 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2620 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2621 && (t->base_opcode != 0x0fc7
2622 || t->extension_opcode != 1 /* cmpxchg8b */))
2623 continue;
2624
29b0f896
AM		 2625 /* Do not verify operands when there are none. */
2626 else if (!t->operands)
2627 {
2628 if (t->cpu_flags & ~cpu_arch_flags)
2629 continue;
2630 /* We've found a match; break out of loop. */
2631 break;
2632 }
252b5132 2633
29b0f896
AM		 2634 overlap0 = i.types[0] & t->operand_types[0];
2635 switch (t->operands)
2636 {
2637 case 1:
2638 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2639 continue;
2640 break;
2641 case 2:
2642 case 3:
2643 overlap1 = i.types[1] & t->operand_types[1];
2644 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2645 || !MATCH (overlap1, i.types[1], t->operand_types[1])
cb712a9e 2646 /* monitor in SSE3 is a very special case. The first
708587a4 2647 register and the second register may have different
cb712a9e
L		 2648 sizes. */
2649 || !((t->base_opcode == 0x0f01
2650 && t->extension_opcode == 0xc8)
2651 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2652 t->operand_types[0],
2653 overlap1, i.types[1],
2654 t->operand_types[1])))
29b0f896
AM		 2655 {
2656 /* Check if other direction is valid ... */
2657 if ((t->opcode_modifier & (D | FloatD)) == 0)
2658 continue;
2659
2660 /* Try reversing direction of operands. */
2661 overlap0 = i.types[0] & t->operand_types[1];
2662 overlap1 = i.types[1] & t->operand_types[0];
2663 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2664 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2665 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2666 t->operand_types[1],
2667 overlap1, i.types[1],
2668 t->operand_types[0]))
2669 {
2670 /* Does not match either direction. */
2671 continue;
2672 }
2673 /* found_reverse_match holds which of D or FloatDR
2674 we've found. */
2675 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2676 }
2677 /* Found a forward 2 operand match here. */
2678 else if (t->operands == 3)
2679 {
2680 /* Here we make use of the fact that there are no
2681 reverse match 3 operand instructions, and all 3
2682 operand instructions only need to be checked for
2683 register consistency between operands 2 and 3. */
2684 overlap2 = i.types[2] & t->operand_types[2];
2685 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2686 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2687 t->operand_types[1],
2688 overlap2, i.types[2],
2689 t->operand_types[2]))
2690
2691 continue;
2692 }
2693 /* Found either forward/reverse 2 or 3 operand match here:
2694 slip through to break. */
2695 }
2696 if (t->cpu_flags & ~cpu_arch_flags)
2697 {
2698 found_reverse_match = 0;
2699 continue;
2700 }
2701 /* We've found a match; break out of loop. */
2702 break;
2703 }
2704
2705 if (t == current_templates->end)
2706 {
2707 /* We found no match. */
2708 as_bad (_("suffix or operands invalid for `%s'"),
2709 current_templates->start->name);
2710 return 0;
2711 }
252b5132 2712
29b0f896
AM		 2713 if (!quiet_warnings)
2714 {
2715 if (!intel_syntax
2716 && ((i.types[0] & JumpAbsolute)
2717 != (t->operand_types[0] & JumpAbsolute)))
2718 {
2719 as_warn (_("indirect %s without `*'"), t->name);
2720 }
2721
2722 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2723 == (IsPrefix | IgnoreSize))
2724 {
2725 /* Warn them that a data or address size prefix doesn't
2726 affect assembly of the next line of code. */
2727 as_warn (_("stand-alone `%s' prefix"), t->name);
2728 }
2729 }
2730
2731 /* Copy the template we found. */
2732 i.tm = *t;
2733 if (found_reverse_match)
2734 {
2735 /* If we found a reverse match we must alter the opcode
2736 direction bit. found_reverse_match holds bits to change
2737 (different for int & float insns). */
2738
2739 i.tm.base_opcode ^= found_reverse_match;
2740
2741 i.tm.operand_types[0] = t->operand_types[1];
2742 i.tm.operand_types[1] = t->operand_types[0];
2743 }
2744
2745 return 1;
2746}
2747
2748static int
2749check_string ()
2750{
2751 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2752 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2753 {
2754 if (i.seg[0] != NULL && i.seg[0] != &es)
2755 {
2756 as_bad (_("`%s' operand %d must use `%%es' segment"),
2757 i.tm.name,
2758 mem_op + 1);
2759 return 0;
2760 }
2761 /* There's only ever one segment override allowed per instruction.
2762 This instruction possibly has a legal segment override on the
2763 second operand, so copy the segment to where non-string
2764 instructions store it, allowing common code. */
2765 i.seg[0] = i.seg[1];
2766 }
2767 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2768 {
2769 if (i.seg[1] != NULL && i.seg[1] != &es)
2770 {
2771 as_bad (_("`%s' operand %d must use `%%es' segment"),
2772 i.tm.name,
2773 mem_op + 2);
2774 return 0;
2775 }
2776 }
2777 return 1;
2778}
2779
2780static int
543613e9 2781process_suffix (void)
29b0f896
AM		 2782{
2783 /* If matched instruction specifies an explicit instruction mnemonic
2784 suffix, use it. */
2785 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2786 {
2787 if (i.tm.opcode_modifier & Size16)
2788 i.suffix = WORD_MNEM_SUFFIX;
2789 else if (i.tm.opcode_modifier & Size64)
2790 i.suffix = QWORD_MNEM_SUFFIX;
2791 else
2792 i.suffix = LONG_MNEM_SUFFIX;
2793 }
2794 else if (i.reg_operands)
2795 {
2796 /* If there's no instruction mnemonic suffix we try to invent one
2797 based on register operands. */
2798 if (!i.suffix)
2799 {
2800 /* We take i.suffix from the last register operand specified,
2801 Destination register type is more significant than source
2802 register type. */
2803 int op;
543613e9 2804
29b0f896
AM		 2805 for (op = i.operands; --op >= 0;)
2806 if ((i.types[op] & Reg)
2807 && !(i.tm.operand_types[op] & InOutPortReg))
2808 {
2809 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2810 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2811 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2812 LONG_MNEM_SUFFIX);
2813 break;
2814 }
2815 }
2816 else if (i.suffix == BYTE_MNEM_SUFFIX)
2817 {
2818 if (!check_byte_reg ())
2819 return 0;
2820 }
2821 else if (i.suffix == LONG_MNEM_SUFFIX)
2822 {
2823 if (!check_long_reg ())
2824 return 0;
2825 }
2826 else if (i.suffix == QWORD_MNEM_SUFFIX)
2827 {
2828 if (!check_qword_reg ())
2829 return 0;
2830 }
2831 else if (i.suffix == WORD_MNEM_SUFFIX)
2832 {
2833 if (!check_word_reg ())
2834 return 0;
2835 }
2836 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2837 /* Do nothing if the instruction is going to ignore the prefix. */
2838 ;
2839 else
2840 abort ();
2841 }
9306ca4a
JB		 2842 else if ((i.tm.opcode_modifier & DefaultSize)
2843 && !i.suffix
2844 /* exclude fldenv/frstor/fsave/fstenv */
2845 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2846 {
2847 i.suffix = stackop_size;
2848 }
9306ca4a
JB		 2849 else if (intel_syntax
2850 && !i.suffix
2851 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2852 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2853 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2854 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2855 {
2856 switch (flag_code)
2857 {
2858 case CODE_64BIT:
2859 if (!(i.tm.opcode_modifier & No_qSuf))
2860 {
2861 i.suffix = QWORD_MNEM_SUFFIX;
2862 break;
2863 }
2864 case CODE_32BIT:
2865 if (!(i.tm.opcode_modifier & No_lSuf))
2866 i.suffix = LONG_MNEM_SUFFIX;
2867 break;
2868 case CODE_16BIT:
2869 if (!(i.tm.opcode_modifier & No_wSuf))
2870 i.suffix = WORD_MNEM_SUFFIX;
2871 break;
2872 }
2873 }
252b5132 2874
9306ca4a 2875 if (!i.suffix)
29b0f896 2876 {
9306ca4a
JB		 2877 if (!intel_syntax)
2878 {
2879 if (i.tm.opcode_modifier & W)
2880 {
2881 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2882 return 0;
2883 }
2884 }
2885 else
2886 {
64e74474
AM		 2887 unsigned int suffixes = (~i.tm.opcode_modifier
2888 & (No_bSuf
2889 | No_wSuf
2890 | No_lSuf
2891 | No_sSuf
2892 | No_xSuf
2893 | No_qSuf));
9306ca4a
JB		 2894
2895 if ((i.tm.opcode_modifier & W)
2896 || ((suffixes & (suffixes - 1))
2897 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2898 {
2899 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2900 return 0;
2901 }
2902 }
29b0f896 2903 }
252b5132 2904
9306ca4a
JB		 2905 /* Change the opcode based on the operand size given by i.suffix;
2906 We don't need to change things for byte insns. */
2907
29b0f896
AM		 2908 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2909 {
2910 /* It's not a byte, select word/dword operation. */
2911 if (i.tm.opcode_modifier & W)
2912 {
2913 if (i.tm.opcode_modifier & ShortForm)
2914 i.tm.base_opcode |= 8;
2915 else
2916 i.tm.base_opcode |= 1;
2917 }
0f3f3d8b 2918
29b0f896
AM		 2919 /* Now select between word & dword operations via the operand
2920 size prefix, except for instructions that will ignore this
2921 prefix anyway. */
cb712a9e
L		 2922 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2923 {
2924 /* monitor in SSE3 is a very special case. The default size
2925 of AX is the size of mode. The address size override
2926 prefix will change the size of AX. */
2927 if (i.op->regs[0].reg_type &
2928 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2929 if (!add_prefix (ADDR_PREFIX_OPCODE))
2930 return 0;
2931 }
2932 else if (i.suffix != QWORD_MNEM_SUFFIX
2933 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2934 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2935 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2936 || (flag_code == CODE_64BIT
2937 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2938 {
2939 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2940
29b0f896
AM		 2941 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2942 prefix = ADDR_PREFIX_OPCODE;
252b5132 2943
29b0f896
AM		 2944 if (!add_prefix (prefix))
2945 return 0;
24eab124 2946 }
252b5132 2947
29b0f896
AM		 2948 /* Set mode64 for an operand. */
2949 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2950 && flag_code == CODE_64BIT
29b0f896 2951 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2952 {
2953 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2954 need rex64. */
2955 if (i.operands != 2
2956 || i.types [0] != (Acc | Reg64)
2957 || i.types [1] != (Acc | Reg64)
2958 || strcmp (i.tm.name, "xchg") != 0)
2959 i.rex |= REX_MODE64;
2960 }
3e73aa7c 2961
29b0f896
AM		 2962 /* Size floating point instruction. */
2963 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2964 if (i.tm.opcode_modifier & FloatMF)
2965 i.tm.base_opcode ^= 4;
29b0f896 2966 }
7ecd2f8b 2967
29b0f896
AM		 2968 return 1;
2969}
3e73aa7c 2970
29b0f896 2971static int
543613e9 2972check_byte_reg (void)
29b0f896
AM		 2973{
2974 int op;
543613e9 2975
29b0f896
AM		 2976 for (op = i.operands; --op >= 0;)
2977 {
2978 /* If this is an eight bit register, it's OK. If it's the 16 or
2979 32 bit version of an eight bit register, we will just use the
2980 low portion, and that's OK too. */
2981 if (i.types[op] & Reg8)
2982 continue;
2983
2984 /* movzx and movsx should not generate this warning. */
2985 if (intel_syntax
2986 && (i.tm.base_opcode == 0xfb7
2987 || i.tm.base_opcode == 0xfb6
2988 || i.tm.base_opcode == 0x63
2989 || i.tm.base_opcode == 0xfbe
2990 || i.tm.base_opcode == 0xfbf))
2991 continue;
2992
65ec77d2 2993 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2994 {
2995 /* Prohibit these changes in the 64bit mode, since the
2996 lowering is more complicated. */
2997 if (flag_code == CODE_64BIT
2998 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2999 {
0f3f3d8b 3000 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3001 i.op[op].regs->reg_name,
3002 i.suffix);
3003 return 0;
3004 }
3005#if REGISTER_WARNINGS
3006 if (!quiet_warnings
3007 && (i.tm.operand_types[op] & InOutPortReg) == 0)
3008 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3009 (i.op[op].regs + (i.types[op] & Reg16
3010 ? REGNAM_AL - REGNAM_AX
3011 : REGNAM_AL - REGNAM_EAX))->reg_name,
3012 i.op[op].regs->reg_name,
3013 i.suffix);
3014#endif
3015 continue;
3016 }
3017 /* Any other register is bad. */
3018 if (i.types[op] & (Reg | RegMMX | RegXMM
3019 | SReg2 | SReg3
3020 | Control | Debug | Test
3021 | FloatReg | FloatAcc))
3022 {
3023 as_bad (_("`%%%s' not allowed with `%s%c'"),
3024 i.op[op].regs->reg_name,
3025 i.tm.name,
3026 i.suffix);
3027 return 0;
3028 }
3029 }
3030 return 1;
3031}
3032
3033static int
3034check_long_reg ()
3035{
3036 int op;
3037
3038 for (op = i.operands; --op >= 0;)
3039 /* Reject eight bit registers, except where the template requires
3040 them. (eg. movzb) */
3041 if ((i.types[op] & Reg8) != 0
3042 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3043 {
3044 as_bad (_("`%%%s' not allowed with `%s%c'"),
3045 i.op[op].regs->reg_name,
3046 i.tm.name,
3047 i.suffix);
3048 return 0;
3049 }
3050 /* Warn if the e prefix on a general reg is missing. */
3051 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3052 && (i.types[op] & Reg16) != 0
3053 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3054 {
3055 /* Prohibit these changes in the 64bit mode, since the
3056 lowering is more complicated. */
3057 if (flag_code == CODE_64BIT)
252b5132 3058 {
0f3f3d8b 3059 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3060 i.op[op].regs->reg_name,
3061 i.suffix);
3062 return 0;
252b5132 3063 }
29b0f896
AM		 3064#if REGISTER_WARNINGS
3065 else
3066 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3067 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
3068 i.op[op].regs->reg_name,
3069 i.suffix);
3070#endif
252b5132 3071 }
29b0f896
AM		 3072 /* Warn if the r prefix on a general reg is missing. */
3073 else if ((i.types[op] & Reg64) != 0
3074 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 3075 {
0f3f3d8b 3076 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3077 i.op[op].regs->reg_name,
3078 i.suffix);
3079 return 0;
3080 }
3081 return 1;
3082}
252b5132 3083
29b0f896
AM		 3084static int
3085check_qword_reg ()
3086{
3087 int op;
252b5132 3088
29b0f896
AM		 3089 for (op = i.operands; --op >= 0; )
3090 /* Reject eight bit registers, except where the template requires
3091 them. (eg. movzb) */
3092 if ((i.types[op] & Reg8) != 0
3093 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3094 {
3095 as_bad (_("`%%%s' not allowed with `%s%c'"),
3096 i.op[op].regs->reg_name,
3097 i.tm.name,
3098 i.suffix);
3099 return 0;
3100 }
3101 /* Warn if the e prefix on a general reg is missing. */
3102 else if (((i.types[op] & Reg16) != 0
3103 || (i.types[op] & Reg32) != 0)
3104 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
3105 {
3106 /* Prohibit these changes in the 64bit mode, since the
3107 lowering is more complicated. */
0f3f3d8b 3108 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3109 i.op[op].regs->reg_name,
3110 i.suffix);
3111 return 0;
252b5132 3112 }
29b0f896
AM		 3113 return 1;
3114}
252b5132 3115
29b0f896
AM		 3116static int
3117check_word_reg ()
3118{
3119 int op;
3120 for (op = i.operands; --op >= 0;)
3121 /* Reject eight bit registers, except where the template requires
3122 them. (eg. movzb) */
3123 if ((i.types[op] & Reg8) != 0
3124 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
3125 {
3126 as_bad (_("`%%%s' not allowed with `%s%c'"),
3127 i.op[op].regs->reg_name,
3128 i.tm.name,
3129 i.suffix);
3130 return 0;
3131 }
3132 /* Warn if the e prefix on a general reg is present. */
3133 else if ((!quiet_warnings || flag_code == CODE_64BIT)
3134 && (i.types[op] & Reg32) != 0
3135 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 3136 {
29b0f896
AM		 3137 /* Prohibit these changes in the 64bit mode, since the
3138 lowering is more complicated. */
3139 if (flag_code == CODE_64BIT)
252b5132 3140 {
0f3f3d8b 3141 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 3142 i.op[op].regs->reg_name,
3143 i.suffix);
3144 return 0;
252b5132 3145 }
29b0f896
AM		 3146 else
3147#if REGISTER_WARNINGS
3148 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
3149 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
3150 i.op[op].regs->reg_name,
3151 i.suffix);
3152#endif
3153 }
3154 return 1;
3155}
252b5132 3156
29b0f896
AM		 3157static int
3158finalize_imm ()
3159{
3160 unsigned int overlap0, overlap1, overlap2;
3161
3162 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 3163 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 3164 && overlap0 != Imm8 && overlap0 != Imm8S
3165 && overlap0 != Imm16 && overlap0 != Imm32S
3166 && overlap0 != Imm32 && overlap0 != Imm64)
3167 {
3168 if (i.suffix)
3169 {
3170 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
3171 ? Imm8 | Imm8S
3172 : (i.suffix == WORD_MNEM_SUFFIX
3173 ? Imm16
3174 : (i.suffix == QWORD_MNEM_SUFFIX
3175 ? Imm64 | Imm32S
3176 : Imm32)));
3177 }
3178 else if (overlap0 == (Imm16 | Imm32S | Imm32)
3179 || overlap0 == (Imm16 | Imm32)
3180 || overlap0 == (Imm16 | Imm32S))
3181 {
3182 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3183 ? Imm16 : Imm32S);
3184 }
3185 if (overlap0 != Imm8 && overlap0 != Imm8S
3186 && overlap0 != Imm16 && overlap0 != Imm32S
3187 && overlap0 != Imm32 && overlap0 != Imm64)
3188 {
3189 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
3190 return 0;
3191 }
3192 }
3193 i.types[0] = overlap0;
3194
3195 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 3196 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 3197 && overlap1 != Imm8 && overlap1 != Imm8S
3198 && overlap1 != Imm16 && overlap1 != Imm32S
3199 && overlap1 != Imm32 && overlap1 != Imm64)
3200 {
3201 if (i.suffix)
3202 {
3203 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
3204 ? Imm8 | Imm8S
3205 : (i.suffix == WORD_MNEM_SUFFIX
3206 ? Imm16
3207 : (i.suffix == QWORD_MNEM_SUFFIX
3208 ? Imm64 | Imm32S
3209 : Imm32)));
3210 }
3211 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
3212 || overlap1 == (Imm16 | Imm32)
3213 || overlap1 == (Imm16 | Imm32S))
3214 {
3215 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
3216 ? Imm16 : Imm32S);
3217 }
3218 if (overlap1 != Imm8 && overlap1 != Imm8S
3219 && overlap1 != Imm16 && overlap1 != Imm32S
3220 && overlap1 != Imm32 && overlap1 != Imm64)
3221 {
3222 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
3223 return 0;
3224 }
3225 }
3226 i.types[1] = overlap1;
3227
3228 overlap2 = i.types[2] & i.tm.operand_types[2];
3229 assert ((overlap2 & Imm) == 0);
3230 i.types[2] = overlap2;
3231
3232 return 1;
3233}
3234
3235static int
3236process_operands ()
3237{
3238 /* Default segment register this instruction will use for memory
3239 accesses. 0 means unknown. This is only for optimizing out
3240 unnecessary segment overrides. */
3241 const seg_entry *default_seg = 0;
3242
3243 /* The imul $imm, %reg instruction is converted into
3244 imul $imm, %reg, %reg, and the clr %reg instruction
3245 is converted into xor %reg, %reg. */
3246 if (i.tm.opcode_modifier & regKludge)
3247 {
3248 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
3249 /* Pretend we saw the extra register operand. */
3250 assert (i.op[first_reg_op + 1].regs == 0);
3251 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
3252 i.types[first_reg_op + 1] = i.types[first_reg_op];
3253 i.reg_operands = 2;
3254 }
3255
3256 if (i.tm.opcode_modifier & ShortForm)
3257 {
3258 /* The register or float register operand is in operand 0 or 1. */
3259 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
3260 /* Register goes in low 3 bits of opcode. */
3261 i.tm.base_opcode |= i.op[op].regs->reg_num;
3262 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3263 i.rex |= REX_EXTZ;
3264 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
3265 {
3266 /* Warn about some common errors, but press on regardless.
3267 The first case can be generated by gcc (<= 2.8.1). */
3268 if (i.operands == 2)
3269 {
3270 /* Reversed arguments on faddp, fsubp, etc. */
3271 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3272 i.op[1].regs->reg_name,
3273 i.op[0].regs->reg_name);
3274 }
3275 else
3276 {
3277 /* Extraneous `l' suffix on fp insn. */
3278 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3279 i.op[0].regs->reg_name);
3280 }
3281 }
3282 }
3283 else if (i.tm.opcode_modifier & Modrm)
3284 {
3285 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3286 must be put into the modrm byte). Now, we make the modrm and
3287 index base bytes based on all the info we've collected. */
29b0f896
AM		 3288
3289 default_seg = build_modrm_byte ();
3290 }
3291 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3292 {
3293 if (i.tm.base_opcode == POP_SEG_SHORT
3294 && i.op[0].regs->reg_num == 1)
3295 {
3296 as_bad (_("you can't `pop %%cs'"));
3297 return 0;
3298 }
3299 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3300 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3301 i.rex |= REX_EXTZ;
3302 }
3303 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3304 {
3305 default_seg = &ds;
3306 }
3307 else if ((i.tm.opcode_modifier & IsString) != 0)
3308 {
3309 /* For the string instructions that allow a segment override
3310 on one of their operands, the default segment is ds. */
3311 default_seg = &ds;
3312 }
3313
30123838
JB		 3314 if ((i.tm.base_opcode == 0x8d /* lea */
3315 || (i.tm.cpu_flags & CpuSVME))
3316 && i.seg[0] && !quiet_warnings)
3317 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3318
3319 /* If a segment was explicitly specified, and the specified segment
3320 is not the default, use an opcode prefix to select it. If we
3321 never figured out what the default segment is, then default_seg
3322 will be zero at this point, and the specified segment prefix will
3323 always be used. */
29b0f896
AM		 3324 if ((i.seg[0]) && (i.seg[0] != default_seg))
3325 {
3326 if (!add_prefix (i.seg[0]->seg_prefix))
3327 return 0;
3328 }
3329 return 1;
3330}
3331
3332static const seg_entry *
3333build_modrm_byte ()
3334{
3335 const seg_entry *default_seg = 0;
3336
3337 /* i.reg_operands MUST be the number of real register operands;
3338 implicit registers do not count. */
3339 if (i.reg_operands == 2)
3340 {
3341 unsigned int source, dest;
3342 source = ((i.types[0]
3343 & (Reg | RegMMX | RegXMM
3344 | SReg2 | SReg3
3345 | Control | Debug | Test))
3346 ? 0 : 1);
050dfa73
MM		 3347
3348 /* In 4 operands instructions with 2 immediate operands, the first two are immediate
3349 bytes and hence source operand will be in the next byte after the immediates */
3350 if ((i.operands == 4)&&(i.imm_operands=2)) source++;
29b0f896
AM		 3351 dest = source + 1;
3352
3353 i.rm.mode = 3;
3354 /* One of the register operands will be encoded in the i.tm.reg
3355 field, the other in the combined i.tm.mode and i.tm.regmem
3356 fields. If no form of this instruction supports a memory
3357 destination operand, then we assume the source operand may
3358 sometimes be a memory operand and so we need to store the
3359 destination in the i.rm.reg field. */
3360 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3361 {
3362 i.rm.reg = i.op[dest].regs->reg_num;
3363 i.rm.regmem = i.op[source].regs->reg_num;
3364 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3365 i.rex |= REX_EXTX;
3366 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3367 i.rex |= REX_EXTZ;
3368 }
3369 else
3370 {
3371 i.rm.reg = i.op[source].regs->reg_num;
3372 i.rm.regmem = i.op[dest].regs->reg_num;
3373 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3374 i.rex |= REX_EXTZ;
3375 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3376 i.rex |= REX_EXTX;
3377 }
c4a530c5
JB		 3378 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3379 {
3380 if (!((i.types[0] | i.types[1]) & Control))
3381 abort ();
3382 i.rex &= ~(REX_EXTX | REX_EXTZ);
3383 add_prefix (LOCK_PREFIX_OPCODE);
3384 }
29b0f896
AM		 3385 }
3386 else
3387 { /* If it's not 2 reg operands... */
3388 if (i.mem_operands)
3389 {
3390 unsigned int fake_zero_displacement = 0;
3391 unsigned int op = ((i.types[0] & AnyMem)
3392 ? 0
3393 : (i.types[1] & AnyMem) ? 1 : 2);
3394
3395 default_seg = &ds;
3396
3397 if (i.base_reg == 0)
3398 {
3399 i.rm.mode = 0;
3400 if (!i.disp_operands)
3401 fake_zero_displacement = 1;
3402 if (i.index_reg == 0)
3403 {
3404 /* Operand is just <disp> */
20f0a1fc 3405 if (flag_code == CODE_64BIT)
29b0f896
AM		 3406 {
3407 /* 64bit mode overwrites the 32bit absolute
3408 addressing by RIP relative addressing and
3409 absolute addressing is encoded by one of the
3410 redundant SIB forms. */
3411 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3412 i.sib.base = NO_BASE_REGISTER;
3413 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3414 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3415 }
3416 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3417 {
3418 i.rm.regmem = NO_BASE_REGISTER_16;
3419 i.types[op] = Disp16;
3420 }
3421 else
3422 {
3423 i.rm.regmem = NO_BASE_REGISTER;
3424 i.types[op] = Disp32;
29b0f896
AM		 3425 }
3426 }
3427 else /* !i.base_reg && i.index_reg */
3428 {
3429 i.sib.index = i.index_reg->reg_num;
3430 i.sib.base = NO_BASE_REGISTER;
3431 i.sib.scale = i.log2_scale_factor;
3432 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3433 i.types[op] &= ~Disp;
3434 if (flag_code != CODE_64BIT)
3435 i.types[op] |= Disp32; /* Must be 32 bit */
3436 else
3437 i.types[op] |= Disp32S;
3438 if ((i.index_reg->reg_flags & RegRex) != 0)
3439 i.rex |= REX_EXTY;
3440 }
3441 }
3442 /* RIP addressing for 64bit mode. */
3443 else if (i.base_reg->reg_type == BaseIndex)
3444 {
3445 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3446 i.types[op] &= ~ Disp;
29b0f896
AM		 3447 i.types[op] |= Disp32S;
3448 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3449 if (! i.disp_operands)
3450 fake_zero_displacement = 1;
29b0f896
AM		 3451 }
3452 else if (i.base_reg->reg_type & Reg16)
3453 {
3454 switch (i.base_reg->reg_num)
3455 {
3456 case 3: /* (%bx) */
3457 if (i.index_reg == 0)
3458 i.rm.regmem = 7;
3459 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3460 i.rm.regmem = i.index_reg->reg_num - 6;
3461 break;
3462 case 5: /* (%bp) */
3463 default_seg = &ss;
3464 if (i.index_reg == 0)
3465 {
3466 i.rm.regmem = 6;
3467 if ((i.types[op] & Disp) == 0)
3468 {
3469 /* fake (%bp) into 0(%bp) */
3470 i.types[op] |= Disp8;
252b5132 3471 fake_zero_displacement = 1;
29b0f896
AM		 3472 }
3473 }
3474 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3475 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3476 break;
3477 default: /* (%si) -> 4 or (%di) -> 5 */
3478 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3479 }
3480 i.rm.mode = mode_from_disp_size (i.types[op]);
3481 }
3482 else /* i.base_reg and 32/64 bit mode */
3483 {
3484 if (flag_code == CODE_64BIT
3485 && (i.types[op] & Disp))
20f0a1fc
NC		 3486 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3487
29b0f896
AM		 3488 i.rm.regmem = i.base_reg->reg_num;
3489 if ((i.base_reg->reg_flags & RegRex) != 0)
3490 i.rex |= REX_EXTZ;
3491 i.sib.base = i.base_reg->reg_num;
3492 /* x86-64 ignores REX prefix bit here to avoid decoder
3493 complications. */
3494 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3495 {
3496 default_seg = &ss;
3497 if (i.disp_operands == 0)
3498 {
3499 fake_zero_displacement = 1;
3500 i.types[op] |= Disp8;
3501 }
3502 }
3503 else if (i.base_reg->reg_num == ESP_REG_NUM)
3504 {
3505 default_seg = &ss;
3506 }
3507 i.sib.scale = i.log2_scale_factor;
3508 if (i.index_reg == 0)
3509 {
3510 /* <disp>(%esp) becomes two byte modrm with no index
3511 register. We've already stored the code for esp
3512 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3513 Any base register besides %esp will not use the
3514 extra modrm byte. */
3515 i.sib.index = NO_INDEX_REGISTER;
3516#if !SCALE1_WHEN_NO_INDEX
3517 /* Another case where we force the second modrm byte. */
3518 if (i.log2_scale_factor)
3519 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3520#endif
29b0f896
AM		 3521 }
3522 else
3523 {
3524 i.sib.index = i.index_reg->reg_num;
3525 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3526 if ((i.index_reg->reg_flags & RegRex) != 0)
3527 i.rex |= REX_EXTY;
3528 }
67a4f2b7
AO		 3529
3530 if (i.disp_operands
3531 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3532 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3533 i.rm.mode = 0;
3534 else
3535 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3536 }
252b5132 3537
29b0f896
AM		 3538 if (fake_zero_displacement)
3539 {
3540 /* Fakes a zero displacement assuming that i.types[op]
3541 holds the correct displacement size. */
3542 expressionS *exp;
3543
3544 assert (i.op[op].disps == 0);
3545 exp = &disp_expressions[i.disp_operands++];
3546 i.op[op].disps = exp;
3547 exp->X_op = O_constant;
3548 exp->X_add_number = 0;
3549 exp->X_add_symbol = (symbolS *) 0;
3550 exp->X_op_symbol = (symbolS *) 0;
3551 }
3552 }
252b5132 3553
29b0f896
AM		 3554 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3555 (if any) based on i.tm.extension_opcode. Again, we must be
3556 careful to make sure that segment/control/debug/test/MMX
3557 registers are coded into the i.rm.reg field. */
3558 if (i.reg_operands)
3559 {
3560 unsigned int op =
3561 ((i.types[0]
3562 & (Reg | RegMMX | RegXMM
3563 | SReg2 | SReg3
3564 | Control | Debug | Test))
3565 ? 0
3566 : ((i.types[1]
3567 & (Reg | RegMMX | RegXMM
3568 | SReg2 | SReg3
3569 | Control | Debug | Test))
3570 ? 1
3571 : 2));
3572 /* If there is an extension opcode to put here, the register
3573 number must be put into the regmem field. */
3574 if (i.tm.extension_opcode != None)
3575 {
3576 i.rm.regmem = i.op[op].regs->reg_num;
3577 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3578 i.rex |= REX_EXTZ;
3579 }
3580 else
3581 {
3582 i.rm.reg = i.op[op].regs->reg_num;
3583 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3584 i.rex |= REX_EXTX;
3585 }
252b5132 3586
29b0f896
AM		 3587 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3588 must set it to 3 to indicate this is a register operand
3589 in the regmem field. */
3590 if (!i.mem_operands)
3591 i.rm.mode = 3;
3592 }
252b5132 3593
29b0f896
AM		 3594 /* Fill in i.rm.reg field with extension opcode (if any). */
3595 if (i.tm.extension_opcode != None)
3596 i.rm.reg = i.tm.extension_opcode;
3597 }
3598 return default_seg;
3599}
252b5132 3600
29b0f896
AM		 3601static void
3602output_branch ()
3603{
3604 char *p;
3605 int code16;
3606 int prefix;
3607 relax_substateT subtype;
3608 symbolS *sym;
3609 offsetT off;
3610
3611 code16 = 0;
3612 if (flag_code == CODE_16BIT)
3613 code16 = CODE16;
3614
3615 prefix = 0;
3616 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3617 {
29b0f896
AM		 3618 prefix = 1;
3619 i.prefixes -= 1;
3620 code16 ^= CODE16;
252b5132 3621 }
29b0f896
AM		 3622 /* Pentium4 branch hints. */
3623 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3624 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3625 {
29b0f896
AM		 3626 prefix++;
3627 i.prefixes--;
3628 }
3629 if (i.prefix[REX_PREFIX] != 0)
3630 {
3631 prefix++;
3632 i.prefixes--;
2f66722d
AM		 3633 }
3634
29b0f896
AM		 3635 if (i.prefixes != 0 && !intel_syntax)
3636 as_warn (_("skipping prefixes on this instruction"));
3637
3638 /* It's always a symbol; End frag & setup for relax.
3639 Make sure there is enough room in this frag for the largest
3640 instruction we may generate in md_convert_frag. This is 2
3641 bytes for the opcode and room for the prefix and largest
3642 displacement. */
3643 frag_grow (prefix + 2 + 4);
3644 /* Prefix and 1 opcode byte go in fr_fix. */
3645 p = frag_more (prefix + 1);
3646 if (i.prefix[DATA_PREFIX] != 0)
3647 *p++ = DATA_PREFIX_OPCODE;
3648 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3649 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3650 *p++ = i.prefix[SEG_PREFIX];
3651 if (i.prefix[REX_PREFIX] != 0)
3652 *p++ = i.prefix[REX_PREFIX];
3653 *p = i.tm.base_opcode;
3654
3655 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3656 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3657 else if ((cpu_arch_flags & Cpu386) != 0)
3658 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3659 else
3660 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3661 subtype |= code16;
3e73aa7c 3662
29b0f896
AM		 3663 sym = i.op[0].disps->X_add_symbol;
3664 off = i.op[0].disps->X_add_number;
3e73aa7c 3665
29b0f896
AM		 3666 if (i.op[0].disps->X_op != O_constant
3667 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3668 {
29b0f896
AM		 3669 /* Handle complex expressions. */
3670 sym = make_expr_symbol (i.op[0].disps);
3671 off = 0;
3672 }
3e73aa7c 3673
29b0f896
AM		 3674 /* 1 possible extra opcode + 4 byte displacement go in var part.
3675 Pass reloc in fr_var. */
3676 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3677}
3e73aa7c 3678
29b0f896
AM		 3679static void
3680output_jump ()
3681{
3682 char *p;
3683 int size;
3e02c1cc 3684 fixS *fixP;
29b0f896
AM		 3685
3686 if (i.tm.opcode_modifier & JumpByte)
3687 {
3688 /* This is a loop or jecxz type instruction. */
3689 size = 1;
3690 if (i.prefix[ADDR_PREFIX] != 0)
3691 {
3692 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3693 i.prefixes -= 1;
3694 }
3695 /* Pentium4 branch hints. */
3696 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3697 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3698 {
3699 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3700 i.prefixes--;
3e73aa7c
JH		 3701 }
3702 }
29b0f896
AM		 3703 else
3704 {
3705 int code16;
3e73aa7c 3706
29b0f896
AM		 3707 code16 = 0;
3708 if (flag_code == CODE_16BIT)
3709 code16 = CODE16;
3e73aa7c 3710
29b0f896
AM		 3711 if (i.prefix[DATA_PREFIX] != 0)
3712 {
3713 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3714 i.prefixes -= 1;
3715 code16 ^= CODE16;
3716 }
252b5132 3717
29b0f896
AM		 3718 size = 4;
3719 if (code16)
3720 size = 2;
3721 }
9fcc94b6 3722
29b0f896
AM		 3723 if (i.prefix[REX_PREFIX] != 0)
3724 {
3725 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3726 i.prefixes -= 1;
3727 }
252b5132 3728
29b0f896
AM		 3729 if (i.prefixes != 0 && !intel_syntax)
3730 as_warn (_("skipping prefixes on this instruction"));
e0890092 3731
29b0f896
AM		 3732 p = frag_more (1 + size);
3733 *p++ = i.tm.base_opcode;
e0890092 3734
3e02c1cc
AM		 3735 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3736 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3737
3738 /* All jumps handled here are signed, but don't use a signed limit
3739 check for 32 and 16 bit jumps as we want to allow wrap around at
3740 4G and 64k respectively. */
3741 if (size == 1)
3742 fixP->fx_signed = 1;
29b0f896 3743}
e0890092 3744
29b0f896
AM		 3745static void
3746output_interseg_jump ()
3747{
3748 char *p;
3749 int size;
3750 int prefix;
3751 int code16;
252b5132 3752
29b0f896
AM		 3753 code16 = 0;
3754 if (flag_code == CODE_16BIT)
3755 code16 = CODE16;
a217f122 3756
29b0f896
AM		 3757 prefix = 0;
3758 if (i.prefix[DATA_PREFIX] != 0)
3759 {
3760 prefix = 1;
3761 i.prefixes -= 1;
3762 code16 ^= CODE16;
3763 }
3764 if (i.prefix[REX_PREFIX] != 0)
3765 {
3766 prefix++;
3767 i.prefixes -= 1;
3768 }
252b5132 3769
29b0f896
AM		 3770 size = 4;
3771 if (code16)
3772 size = 2;
252b5132 3773
29b0f896
AM		 3774 if (i.prefixes != 0 && !intel_syntax)
3775 as_warn (_("skipping prefixes on this instruction"));
252b5132 3776
29b0f896
AM		 3777 /* 1 opcode; 2 segment; offset */
3778 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3779
29b0f896
AM		 3780 if (i.prefix[DATA_PREFIX] != 0)
3781 *p++ = DATA_PREFIX_OPCODE;
252b5132 3782
29b0f896
AM		 3783 if (i.prefix[REX_PREFIX] != 0)
3784 *p++ = i.prefix[REX_PREFIX];
252b5132 3785
29b0f896
AM		 3786 *p++ = i.tm.base_opcode;
3787 if (i.op[1].imms->X_op == O_constant)
3788 {
3789 offsetT n = i.op[1].imms->X_add_number;
252b5132 3790
29b0f896
AM		 3791 if (size == 2
3792 && !fits_in_unsigned_word (n)
3793 && !fits_in_signed_word (n))
3794 {
3795 as_bad (_("16-bit jump out of range"));
3796 return;
3797 }
3798 md_number_to_chars (p, n, size);
3799 }
3800 else
3801 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3802 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3803 if (i.op[0].imms->X_op != O_constant)
3804 as_bad (_("can't handle non absolute segment in `%s'"),
3805 i.tm.name);
3806 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3807}
a217f122 3808
29b0f896
AM		 3809static void
3810output_insn ()
3811{
2bbd9c25
JJ		 3812 fragS *insn_start_frag;
3813 offsetT insn_start_off;
3814
29b0f896
AM		 3815 /* Tie dwarf2 debug info to the address at the start of the insn.
3816 We can't do this after the insn has been output as the current
3817 frag may have been closed off. eg. by frag_var. */
3818 dwarf2_emit_insn (0);
3819
2bbd9c25
JJ		 3820 insn_start_frag = frag_now;
3821 insn_start_off = frag_now_fix ();
3822
29b0f896
AM		 3823 /* Output jumps. */
3824 if (i.tm.opcode_modifier & Jump)
3825 output_branch ();
3826 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3827 output_jump ();
3828 else if (i.tm.opcode_modifier & JumpInterSegment)
3829 output_interseg_jump ();
3830 else
3831 {
3832 /* Output normal instructions here. */
3833 char *p;
3834 unsigned char *q;
331d2d0d 3835 unsigned int prefix;
252b5132 3836
331d2d0d
L		 3837 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3838 Instructions have 3 bytes. We may use one more higher byte
3839 to specify a prefix the instruction requires. */
3840 if ((i.tm.cpu_flags & CpuMNI) != 0)
bc4bd9ab 3841 {
331d2d0d
L		 3842 if (i.tm.base_opcode & 0xff000000)
3843 {
3844 prefix = (i.tm.base_opcode >> 24) & 0xff;
3845 goto check_prefix;
3846 }
3847 }
3848 else if ((i.tm.base_opcode & 0xff0000) != 0)
3849 {
3850 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3851 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3852 {
64e74474 3853 check_prefix:
bc4bd9ab
MK		 3854 if (prefix != REPE_PREFIX_OPCODE
3855 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3856 add_prefix (prefix);
3857 }
3858 else
331d2d0d 3859 add_prefix (prefix);
0f10071e 3860 }
252b5132 3861
29b0f896
AM		 3862 /* The prefix bytes. */
3863 for (q = i.prefix;
3864 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3865 q++)
3866 {
3867 if (*q)
3868 {
3869 p = frag_more (1);
3870 md_number_to_chars (p, (valueT) *q, 1);
3871 }
3872 }
252b5132 3873
29b0f896
AM		 3874 /* Now the opcode; be careful about word order here! */
3875 if (fits_in_unsigned_byte (i.tm.base_opcode))
3876 {
3877 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3878 }
3879 else
3880 {
331d2d0d
L		 3881 if ((i.tm.cpu_flags & CpuMNI) != 0)
3882 {
3883 p = frag_more (3);
3884 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3885 }
3886 else
3887 p = frag_more (2);
0f10071e 3888
29b0f896
AM		 3889 /* Put out high byte first: can't use md_number_to_chars! */
3890 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3891 *p = i.tm.base_opcode & 0xff;
3892 }
3e73aa7c 3893
29b0f896
AM		 3894 /* Now the modrm byte and sib byte (if present). */
3895 if (i.tm.opcode_modifier & Modrm)
3896 {
3897 p = frag_more (1);
3898 md_number_to_chars (p,
3899 (valueT) (i.rm.regmem << 0
3900 | i.rm.reg << 3
3901 | i.rm.mode << 6),
3902 1);
3903 /* If i.rm.regmem == ESP (4)
3904 && i.rm.mode != (Register mode)
3905 && not 16 bit
3906 ==> need second modrm byte. */
3907 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3908 && i.rm.mode != 3
3909 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3910 {
3911 p = frag_more (1);
3912 md_number_to_chars (p,
3913 (valueT) (i.sib.base << 0
3914 | i.sib.index << 3
3915 | i.sib.scale << 6),
3916 1);
3917 }
3918 }
3e73aa7c 3919
29b0f896 3920 if (i.disp_operands)
2bbd9c25 3921 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3922
29b0f896 3923 if (i.imm_operands)
2bbd9c25 3924 output_imm (insn_start_frag, insn_start_off);
29b0f896 3925 }
252b5132 3926
29b0f896
AM		 3927#ifdef DEBUG386
3928 if (flag_debug)
3929 {
7b81dfbb 3930 pi ("" /*line*/, &i);
29b0f896
AM		 3931 }
3932#endif /* DEBUG386 */
3933}
252b5132 3934
29b0f896 3935static void
64e74474 3936output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3937{
3938 char *p;
3939 unsigned int n;
252b5132 3940
29b0f896
AM		 3941 for (n = 0; n < i.operands; n++)
3942 {
3943 if (i.types[n] & Disp)
3944 {
3945 if (i.op[n].disps->X_op == O_constant)
3946 {
3947 int size;
3948 offsetT val;
252b5132 3949
29b0f896
AM		 3950 size = 4;
3951 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3952 {
3953 size = 2;
3954 if (i.types[n] & Disp8)
3955 size = 1;
3956 if (i.types[n] & Disp64)
3957 size = 8;
3958 }
3959 val = offset_in_range (i.op[n].disps->X_add_number,
3960 size);
3961 p = frag_more (size);
3962 md_number_to_chars (p, val, size);
3963 }
3964 else
3965 {
f86103b7 3966 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3967 int size = 4;
3968 int sign = 0;
3969 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3970
3971 /* The PC relative address is computed relative
3972 to the instruction boundary, so in case immediate
3973 fields follows, we need to adjust the value. */
3974 if (pcrel && i.imm_operands)
3975 {
3976 int imm_size = 4;
3977 unsigned int n1;
252b5132 3978
29b0f896
AM		 3979 for (n1 = 0; n1 < i.operands; n1++)
3980 if (i.types[n1] & Imm)
252b5132 3981 {
29b0f896 3982 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3983 {
29b0f896
AM		 3984 imm_size = 2;
3985 if (i.types[n1] & (Imm8 | Imm8S))
3986 imm_size = 1;
3987 if (i.types[n1] & Imm64)
3988 imm_size = 8;
252b5132 3989 }
29b0f896 3990 break;
252b5132 3991 }
29b0f896
AM		 3992 /* We should find the immediate. */
3993 if (n1 == i.operands)
3994 abort ();
3995 i.op[n].disps->X_add_number -= imm_size;
3996 }
520dc8e8 3997
29b0f896
AM		 3998 if (i.types[n] & Disp32S)
3999 sign = 1;
3e73aa7c 4000
29b0f896
AM		 4001 if (i.types[n] & (Disp16 | Disp64))
4002 {
4003 size = 2;
4004 if (i.types[n] & Disp64)
4005 size = 8;
4006 }
520dc8e8 4007
29b0f896 4008 p = frag_more (size);
2bbd9c25 4009 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 4010 if (GOT_symbol
2bbd9c25 4011 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 4012 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4013 || reloc_type == BFD_RELOC_X86_64_32S
4014 || (reloc_type == BFD_RELOC_64
4015 && object_64bit))
d6ab8113
JB		 4016 && (i.op[n].disps->X_op == O_symbol
4017 || (i.op[n].disps->X_op == O_add
4018 && ((symbol_get_value_expression
4019 (i.op[n].disps->X_op_symbol)->X_op)
4020 == O_subtract))))
4021 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 4022 {
4023 offsetT add;
4024
4025 if (insn_start_frag == frag_now)
4026 add = (p - frag_now->fr_literal) - insn_start_off;
4027 else
4028 {
4029 fragS *fr;
4030
4031 add = insn_start_frag->fr_fix - insn_start_off;
4032 for (fr = insn_start_frag->fr_next;
4033 fr && fr != frag_now; fr = fr->fr_next)
4034 add += fr->fr_fix;
4035 add += p - frag_now->fr_literal;
4036 }
4037
4fa24527 4038 if (!object_64bit)
7b81dfbb
AJ		 4039 {
4040 reloc_type = BFD_RELOC_386_GOTPC;
4041 i.op[n].imms->X_add_number += add;
4042 }
4043 else if (reloc_type == BFD_RELOC_64)
4044 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 4045 else
7b81dfbb
AJ		 4046 /* Don't do the adjustment for x86-64, as there
4047 the pcrel addressing is relative to the _next_
4048 insn, and that is taken care of in other code. */
d6ab8113 4049 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 4050 }
062cd5e7 4051 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 4052 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 4053 }
4054 }
4055 }
4056}
252b5132 4057
29b0f896 4058static void
64e74474 4059output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 4060{
4061 char *p;
4062 unsigned int n;
252b5132 4063
29b0f896
AM		 4064 for (n = 0; n < i.operands; n++)
4065 {
4066 if (i.types[n] & Imm)
4067 {
4068 if (i.op[n].imms->X_op == O_constant)
4069 {
4070 int size;
4071 offsetT val;
b4cac588 4072
29b0f896
AM		 4073 size = 4;
4074 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4075 {
4076 size = 2;
4077 if (i.types[n] & (Imm8 | Imm8S))
4078 size = 1;
4079 else if (i.types[n] & Imm64)
4080 size = 8;
4081 }
4082 val = offset_in_range (i.op[n].imms->X_add_number,
4083 size);
4084 p = frag_more (size);
4085 md_number_to_chars (p, val, size);
4086 }
4087 else
4088 {
4089 /* Not absolute_section.
4090 Need a 32-bit fixup (don't support 8bit
4091 non-absolute imms). Try to support other
4092 sizes ... */
f86103b7 4093 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 4094 int size = 4;
4095 int sign = 0;
4096
4097 if ((i.types[n] & (Imm32S))
a7d61044
JB		 4098 && (i.suffix == QWORD_MNEM_SUFFIX
4099 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 4100 sign = 1;
4101 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
4102 {
4103 size = 2;
4104 if (i.types[n] & (Imm8 | Imm8S))
4105 size = 1;
4106 if (i.types[n] & Imm64)
4107 size = 8;
4108 }
520dc8e8 4109
29b0f896
AM		 4110 p = frag_more (size);
4111 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 4112
2bbd9c25
JJ		 4113 /* This is tough to explain. We end up with this one if we
4114 * have operands that look like
4115 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
4116 * obtain the absolute address of the GOT, and it is strongly
4117 * preferable from a performance point of view to avoid using
4118 * a runtime relocation for this. The actual sequence of
4119 * instructions often look something like:
4120 *
4121 * call .L66
4122 * .L66:
4123 * popl %ebx
4124 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
4125 *
4126 * The call and pop essentially return the absolute address
4127 * of the label .L66 and store it in %ebx. The linker itself
4128 * will ultimately change the first operand of the addl so
4129 * that %ebx points to the GOT, but to keep things simple, the
4130 * .o file must have this operand set so that it generates not
4131 * the absolute address of .L66, but the absolute address of
4132 * itself. This allows the linker itself simply treat a GOTPC
4133 * relocation as asking for a pcrel offset to the GOT to be
4134 * added in, and the addend of the relocation is stored in the
4135 * operand field for the instruction itself.
4136 *
4137 * Our job here is to fix the operand so that it would add
4138 * the correct offset so that %ebx would point to itself. The
4139 * thing that is tricky is that .-.L66 will point to the
4140 * beginning of the instruction, so we need to further modify
4141 * the operand so that it will point to itself. There are
4142 * other cases where you have something like:
4143 *
4144 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
4145 *
4146 * and here no correction would be required. Internally in
4147 * the assembler we treat operands of this form as not being
4148 * pcrel since the '.' is explicitly mentioned, and I wonder
4149 * whether it would simplify matters to do it this way. Who
4150 * knows. In earlier versions of the PIC patches, the
4151 * pcrel_adjust field was used to store the correction, but
4152 * since the expression is not pcrel, I felt it would be
4153 * confusing to do it this way. */
4154
d6ab8113 4155 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 4156 || reloc_type == BFD_RELOC_X86_64_32S
4157 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 4158 && GOT_symbol
4159 && GOT_symbol == i.op[n].imms->X_add_symbol
4160 && (i.op[n].imms->X_op == O_symbol
4161 || (i.op[n].imms->X_op == O_add
4162 && ((symbol_get_value_expression
4163 (i.op[n].imms->X_op_symbol)->X_op)
4164 == O_subtract))))
4165 {
2bbd9c25
JJ		 4166 offsetT add;
4167
4168 if (insn_start_frag == frag_now)
4169 add = (p - frag_now->fr_literal) - insn_start_off;
4170 else
4171 {
4172 fragS *fr;
4173
4174 add = insn_start_frag->fr_fix - insn_start_off;
4175 for (fr = insn_start_frag->fr_next;
4176 fr && fr != frag_now; fr = fr->fr_next)
4177 add += fr->fr_fix;
4178 add += p - frag_now->fr_literal;
4179 }
4180
4fa24527 4181 if (!object_64bit)
d6ab8113 4182 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 4183 else if (size == 4)
d6ab8113 4184 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 4185 else if (size == 8)
4186 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 4187 i.op[n].imms->X_add_number += add;
29b0f896 4188 }
29b0f896
AM		 4189 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4190 i.op[n].imms, 0, reloc_type);
4191 }
4192 }
4193 }
252b5132
RH		 4194}
4195\f
d182319b
JB		 4196/* x86_cons_fix_new is called via the expression parsing code when a
4197 reloc is needed. We use this hook to get the correct .got reloc. */
4198static enum bfd_reloc_code_real got_reloc = NO_RELOC;
4199static int cons_sign = -1;
4200
4201void
4202x86_cons_fix_new (fragS *frag,
64e74474
AM		 4203 unsigned int off,
4204 unsigned int len,
4205 expressionS *exp)
d182319b
JB		 4206{
4207 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
4208
4209 got_reloc = NO_RELOC;
4210
4211#ifdef TE_PE
4212 if (exp->X_op == O_secrel)
4213 {
4214 exp->X_op = O_symbol;
4215 r = BFD_RELOC_32_SECREL;
4216 }
4217#endif
4218
4219 fix_new_exp (frag, off, len, exp, 0, r);
4220}
4221
718ddfc0
JB		 4222#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
4223# define lex_got(reloc, adjust, types) NULL
4224#else
f3c180ae
AM		 4225/* Parse operands of the form
4226 <symbol>@GOTOFF+<nnn>
4227 and similar .plt or .got references.
4228
4229 If we find one, set up the correct relocation in RELOC and copy the
4230 input string, minus the `@GOTOFF' into a malloc'd buffer for
4231 parsing by the calling routine. Return this buffer, and if ADJUST
4232 is non-null set it to the length of the string we removed from the
4233 input line. Otherwise return NULL. */
4234static char *
3956db08 4235lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 4236 int *adjust,
4237 unsigned int *types)
f3c180ae 4238{
7b81dfbb
AJ		 4239 /* Some of the relocations depend on the size of what field is to
4240 be relocated. But in our callers i386_immediate and i386_displacement
4241 we don't yet know the operand size (this will be set by insn
4242 matching). Hence we record the word32 relocation here,
4243 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 4244 static const struct {
4245 const char *str;
4fa24527 4246 const enum bfd_reloc_code_real rel[2];
3956db08 4247 const unsigned int types64;
f3c180ae 4248 } gotrel[] = {
7b81dfbb 4249 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 4250 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 4251 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 4252 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
4253 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
4254 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
4255 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
4256 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
4257 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
4258 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4259 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
4260 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
4261 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
4262 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 4263 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 4264 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
4265 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 4266 };
4267 char *cp;
4268 unsigned int j;
4269
718ddfc0
JB		 4270 if (!IS_ELF)
4271 return NULL;
4272
f3c180ae
AM		 4273 for (cp = input_line_pointer; *cp != '@'; cp++)
4274 if (is_end_of_line[(unsigned char) *cp])
4275 return NULL;
4276
4277 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4278 {
4279 int len;
4280
4281 len = strlen (gotrel[j].str);
28f81592 4282 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4283 {
4fa24527 4284 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4285 {
28f81592
AM		 4286 int first, second;
4287 char *tmpbuf, *past_reloc;
f3c180ae 4288
4fa24527 4289 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4290 if (adjust)
4291 *adjust = len;
f3c180ae 4292
3956db08
JB		 4293 if (types)
4294 {
4295 if (flag_code != CODE_64BIT)
4296 *types = Imm32|Disp32;
4297 else
4298 *types = gotrel[j].types64;
4299 }
4300
f3c180ae
AM		 4301 if (GOT_symbol == NULL)
4302 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4303
4304 /* Replace the relocation token with ' ', so that
4305 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4306
4307 /* The length of the first part of our input line. */
f3c180ae 4308 first = cp - input_line_pointer;
28f81592
AM		 4309
4310 /* The second part goes from after the reloc token until
4311 (and including) an end_of_line char. Don't use strlen
4312 here as the end_of_line char may not be a NUL. */
4313 past_reloc = cp + 1 + len;
4314 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4315 ;
4316 second = cp - past_reloc;
4317
4318 /* Allocate and copy string. The trailing NUL shouldn't
4319 be necessary, but be safe. */
4320 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4321 memcpy (tmpbuf, input_line_pointer, first);
4322 tmpbuf[first] = ' ';
28f81592
AM		 4323 memcpy (tmpbuf + first + 1, past_reloc, second);
4324 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4325 return tmpbuf;
4326 }
4327
4fa24527
JB		 4328 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4329 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4330 return NULL;
4331 }
4332 }
4333
4334 /* Might be a symbol version string. Don't as_bad here. */
4335 return NULL;
4336}
4337
f3c180ae
AM		 4338void
4339x86_cons (exp, size)
4340 expressionS *exp;
4341 int size;
4342{
4fa24527 4343 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4344 {
4345 /* Handle @GOTOFF and the like in an expression. */
4346 char *save;
4347 char *gotfree_input_line;
4348 int adjust;
4349
4350 save = input_line_pointer;
3956db08 4351 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4352 if (gotfree_input_line)
4353 input_line_pointer = gotfree_input_line;
4354
4355 expression (exp);
4356
4357 if (gotfree_input_line)
4358 {
4359 /* expression () has merrily parsed up to the end of line,
4360 or a comma - in the wrong buffer. Transfer how far
4361 input_line_pointer has moved to the right buffer. */
4362 input_line_pointer = (save
4363 + (input_line_pointer - gotfree_input_line)
4364 + adjust);
4365 free (gotfree_input_line);
4366 }
4367 }
4368 else
4369 expression (exp);
4370}
4371#endif
4372
d182319b 4373static void signed_cons (int size)
6482c264 4374{
d182319b
JB		 4375 if (flag_code == CODE_64BIT)
4376 cons_sign = 1;
4377 cons (size);
4378 cons_sign = -1;
6482c264
NC		 4379}
4380
d182319b 4381#ifdef TE_PE
6482c264
NC		 4382static void
4383pe_directive_secrel (dummy)
4384 int dummy ATTRIBUTE_UNUSED;
4385{
4386 expressionS exp;
4387
4388 do
4389 {
4390 expression (&exp);
4391 if (exp.X_op == O_symbol)
4392 exp.X_op = O_secrel;
4393
4394 emit_expr (&exp, 4);
4395 }
4396 while (*input_line_pointer++ == ',');
4397
4398 input_line_pointer--;
4399 demand_empty_rest_of_line ();
4400}
6482c264
NC		 4401#endif
4402
252b5132
RH		 4403static int i386_immediate PARAMS ((char *));
4404
4405static int
4406i386_immediate (imm_start)
4407 char *imm_start;
4408{
4409 char *save_input_line_pointer;
f3c180ae 4410 char *gotfree_input_line;
252b5132 4411 segT exp_seg = 0;
47926f60 4412 expressionS *exp;
3956db08 4413 unsigned int types = ~0U;
252b5132
RH		 4414
4415 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4416 {
d0b47220 4417 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4418 return 0;
4419 }
4420
4421 exp = &im_expressions[i.imm_operands++];
520dc8e8 4422 i.op[this_operand].imms = exp;
252b5132
RH		 4423
4424 if (is_space_char (*imm_start))
4425 ++imm_start;
4426
4427 save_input_line_pointer = input_line_pointer;
4428 input_line_pointer = imm_start;
4429
3956db08 4430 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4431 if (gotfree_input_line)
4432 input_line_pointer = gotfree_input_line;
252b5132
RH		 4433
4434 exp_seg = expression (exp);
4435
83183c0c 4436 SKIP_WHITESPACE ();
252b5132 4437 if (*input_line_pointer)
f3c180ae 4438 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4439
4440 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4441 if (gotfree_input_line)
4442 free (gotfree_input_line);
252b5132 4443
2daf4fd8 4444 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4445 {
47926f60 4446 /* Missing or bad expr becomes absolute 0. */
d0b47220 4447 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4448 imm_start);
252b5132
RH		 4449 exp->X_op = O_constant;
4450 exp->X_add_number = 0;
4451 exp->X_add_symbol = (symbolS *) 0;
4452 exp->X_op_symbol = (symbolS *) 0;
252b5132 4453 }
3e73aa7c 4454 else if (exp->X_op == O_constant)
252b5132 4455 {
47926f60 4456 /* Size it properly later. */
3e73aa7c
JH		 4457 i.types[this_operand] |= Imm64;
4458 /* If BFD64, sign extend val. */
4459 if (!use_rela_relocations)
4460 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4461 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4462 }
4c63da97 4463#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4464 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4465 && exp_seg != absolute_section
47926f60 4466 && exp_seg != text_section
24eab124
AM		 4467 && exp_seg != data_section
4468 && exp_seg != bss_section
4469 && exp_seg != undefined_section
f86103b7 4470 && !bfd_is_com_section (exp_seg))
252b5132 4471 {
d0b47220 4472 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4473 return 0;
4474 }
4475#endif
bb8f5920
L		 4476 else if (!intel_syntax && exp->X_op == O_register)
4477 {
4478 as_bad (_("illegal immediate register operand %s"), imm_start);
4479 return 0;
4480 }
252b5132
RH		 4481 else
4482 {
4483 /* This is an address. The size of the address will be
24eab124 4484 determined later, depending on destination register,
3e73aa7c
JH		 4485 suffix, or the default for the section. */
4486 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4487 i.types[this_operand] &= types;
252b5132
RH		 4488 }
4489
4490 return 1;
4491}
4492
551c1ca1 4493static char *i386_scale PARAMS ((char *));
252b5132 4494
551c1ca1 4495static char *
252b5132
RH		 4496i386_scale (scale)
4497 char *scale;
4498{
551c1ca1
AM		 4499 offsetT val;
4500 char *save = input_line_pointer;
252b5132 4501
551c1ca1
AM		 4502 input_line_pointer = scale;
4503 val = get_absolute_expression ();
4504
4505 switch (val)
252b5132 4506 {
551c1ca1 4507 case 1:
252b5132
RH		 4508 i.log2_scale_factor = 0;
4509 break;
551c1ca1 4510 case 2:
252b5132
RH		 4511 i.log2_scale_factor = 1;
4512 break;
551c1ca1 4513 case 4:
252b5132
RH		 4514 i.log2_scale_factor = 2;
4515 break;
551c1ca1 4516 case 8:
252b5132
RH		 4517 i.log2_scale_factor = 3;
4518 break;
4519 default:
a724f0f4
JB		 4520 {
4521 char sep = *input_line_pointer;
4522
4523 *input_line_pointer = '\0';
4524 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4525 scale);
4526 *input_line_pointer = sep;
4527 input_line_pointer = save;
4528 return NULL;
4529 }
252b5132 4530 }
29b0f896 4531 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4532 {
4533 as_warn (_("scale factor of %d without an index register"),
24eab124 4534 1 << i.log2_scale_factor);
252b5132
RH		 4535#if SCALE1_WHEN_NO_INDEX
4536 i.log2_scale_factor = 0;
4537#endif
4538 }
551c1ca1
AM		 4539 scale = input_line_pointer;
4540 input_line_pointer = save;
4541 return scale;
252b5132
RH		 4542}
4543
4544static int i386_displacement PARAMS ((char *, char *));
4545
4546static int
4547i386_displacement (disp_start, disp_end)
4548 char *disp_start;
4549 char *disp_end;
4550{
29b0f896 4551 expressionS *exp;
252b5132
RH		 4552 segT exp_seg = 0;
4553 char *save_input_line_pointer;
f3c180ae 4554 char *gotfree_input_line;
e05278af 4555 int bigdisp, override;
3956db08 4556 unsigned int types = Disp;
252b5132 4557
e05278af
JB		 4558 if ((i.types[this_operand] & JumpAbsolute)
4559 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4560 {
4561 bigdisp = Disp32;
4562 override = (i.prefix[ADDR_PREFIX] != 0);
4563 }
4564 else
4565 {
4566 /* For PC-relative branches, the width of the displacement
4567 is dependent upon data size, not address size. */
4568 bigdisp = 0;
4569 override = (i.prefix[DATA_PREFIX] != 0);
4570 }
3e73aa7c 4571 if (flag_code == CODE_64BIT)
7ecd2f8b 4572 {
e05278af 4573 if (!bigdisp)
64e74474
AM		 4574 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4575 ? Disp16
4576 : Disp32S | Disp32);
e05278af 4577 else if (!override)
3956db08 4578 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4579 }
e05278af
JB		 4580 else
4581 {
4582 if (!bigdisp)
4583 {
4584 if (!override)
4585 override = (i.suffix == (flag_code != CODE_16BIT
4586 ? WORD_MNEM_SUFFIX
4587 : LONG_MNEM_SUFFIX));
4588 bigdisp = Disp32;
4589 }
4590 if ((flag_code == CODE_16BIT) ^ override)
4591 bigdisp = Disp16;
4592 }
252b5132
RH		 4593 i.types[this_operand] |= bigdisp;
4594
4595 exp = &disp_expressions[i.disp_operands];
520dc8e8 4596 i.op[this_operand].disps = exp;
252b5132
RH		 4597 i.disp_operands++;
4598 save_input_line_pointer = input_line_pointer;
4599 input_line_pointer = disp_start;
4600 END_STRING_AND_SAVE (disp_end);
4601
4602#ifndef GCC_ASM_O_HACK
4603#define GCC_ASM_O_HACK 0
4604#endif
4605#if GCC_ASM_O_HACK
4606 END_STRING_AND_SAVE (disp_end + 1);
4607 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4608 && displacement_string_end[-1] == '+')
252b5132
RH		 4609 {
4610 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4611 constraint within gcc asm statements.
4612 For instance:
4613
4614 #define _set_tssldt_desc(n,addr,limit,type) \
4615 __asm__ __volatile__ ( \
4616 "movw %w2,%0\n\t" \
4617 "movw %w1,2+%0\n\t" \
4618 "rorl $16,%1\n\t" \
4619 "movb %b1,4+%0\n\t" \
4620 "movb %4,5+%0\n\t" \
4621 "movb $0,6+%0\n\t" \
4622 "movb %h1,7+%0\n\t" \
4623 "rorl $16,%1" \
4624 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4625
4626 This works great except that the output assembler ends
4627 up looking a bit weird if it turns out that there is
4628 no offset. You end up producing code that looks like:
4629
4630 #APP
4631 movw $235,(%eax)
4632 movw %dx,2+(%eax)
4633 rorl $16,%edx
4634 movb %dl,4+(%eax)
4635 movb $137,5+(%eax)
4636 movb $0,6+(%eax)
4637 movb %dh,7+(%eax)
4638 rorl $16,%edx
4639 #NO_APP
4640
47926f60 4641 So here we provide the missing zero. */
24eab124
AM		 4642
4643 *displacement_string_end = '0';
252b5132
RH		 4644 }
4645#endif
3956db08 4646 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4647 if (gotfree_input_line)
4648 input_line_pointer = gotfree_input_line;
252b5132 4649
24eab124 4650 exp_seg = expression (exp);
252b5132 4651
636c26b0
AM		 4652 SKIP_WHITESPACE ();
4653 if (*input_line_pointer)
4654 as_bad (_("junk `%s' after expression"), input_line_pointer);
4655#if GCC_ASM_O_HACK
4656 RESTORE_END_STRING (disp_end + 1);
4657#endif
4658 RESTORE_END_STRING (disp_end);
4659 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4660 if (gotfree_input_line)
4661 free (gotfree_input_line);
636c26b0 4662
24eab124
AM		 4663 /* We do this to make sure that the section symbol is in
4664 the symbol table. We will ultimately change the relocation
47926f60 4665 to be relative to the beginning of the section. */
1ae12ab7 4666 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4667 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4668 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4669 {
636c26b0
AM		 4670 if (exp->X_op != O_symbol)
4671 {
4672 as_bad (_("bad expression used with @%s"),
4673 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4674 ? "GOTPCREL"
4675 : "GOTOFF"));
4676 return 0;
4677 }
4678
e5cb08ac 4679 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4680 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4681 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4682 exp->X_op = O_subtract;
4683 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4684 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4685 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4686 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4687 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4688 else
29b0f896 4689 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4690 }
252b5132 4691
2daf4fd8
AM		 4692 if (exp->X_op == O_absent || exp->X_op == O_big)
4693 {
47926f60 4694 /* Missing or bad expr becomes absolute 0. */
d0b47220 4695 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4696 disp_start);
4697 exp->X_op = O_constant;
4698 exp->X_add_number = 0;
4699 exp->X_add_symbol = (symbolS *) 0;
4700 exp->X_op_symbol = (symbolS *) 0;
4701 }
4702
4c63da97 4703#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4704 if (exp->X_op != O_constant
45288df1 4705 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4706 && exp_seg != absolute_section
45288df1
AM		 4707 && exp_seg != text_section
4708 && exp_seg != data_section
4709 && exp_seg != bss_section
31312f95 4710 && exp_seg != undefined_section
f86103b7 4711 && !bfd_is_com_section (exp_seg))
24eab124 4712 {
d0b47220 4713 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4714 return 0;
4715 }
252b5132 4716#endif
3956db08
JB		 4717
4718 if (!(i.types[this_operand] & ~Disp))
4719 i.types[this_operand] &= types;
4720
252b5132
RH		 4721 return 1;
4722}
4723
e5cb08ac 4724static int i386_index_check PARAMS ((const char *));
252b5132 4725
eecb386c 4726/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4727 Return 1 on success, 0 on a failure. */
4728
252b5132 4729static int
eecb386c
AM		 4730i386_index_check (operand_string)
4731 const char *operand_string;
252b5132 4732{
3e73aa7c 4733 int ok;
24eab124 4734#if INFER_ADDR_PREFIX
eecb386c
AM		 4735 int fudged = 0;
4736
24eab124
AM		 4737 tryprefix:
4738#endif
3e73aa7c 4739 ok = 1;
30123838
JB		 4740 if ((current_templates->start->cpu_flags & CpuSVME)
4741 && current_templates->end[-1].operand_types[0] == AnyMem)
4742 {
4743 /* Memory operands of SVME insns are special in that they only allow
4744 rAX as their memory address and ignore any segment override. */
4745 unsigned RegXX;
4746
4747 /* SKINIT is even more restrictive: it always requires EAX. */
4748 if (strcmp (current_templates->start->name, "skinit") == 0)
4749 RegXX = Reg32;
4750 else if (flag_code == CODE_64BIT)
4751 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4752 else
64e74474
AM		 4753 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4754 ? Reg16
4755 : Reg32);
30123838
JB		 4756 if (!i.base_reg
4757 || !(i.base_reg->reg_type & Acc)
4758 || !(i.base_reg->reg_type & RegXX)
4759 || i.index_reg
4760 || (i.types[0] & Disp))
4761 ok = 0;
4762 }
4763 else if (flag_code == CODE_64BIT)
64e74474
AM		 4764 {
4765 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4766
4767 if ((i.base_reg
4768 && ((i.base_reg->reg_type & RegXX) == 0)
4769 && (i.base_reg->reg_type != BaseIndex
4770 || i.index_reg))
4771 || (i.index_reg
4772 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4773 != (RegXX | BaseIndex))))
4774 ok = 0;
3e73aa7c
JH		 4775 }
4776 else
4777 {
4778 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4779 {
4780 /* 16bit checks. */
4781 if ((i.base_reg
29b0f896
AM		 4782 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4783 != (Reg16 | BaseIndex)))
3e73aa7c 4784 || (i.index_reg
29b0f896
AM		 4785 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4786 != (Reg16 | BaseIndex))
4787 || !(i.base_reg
4788 && i.base_reg->reg_num < 6
4789 && i.index_reg->reg_num >= 6
4790 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4791 ok = 0;
4792 }
4793 else
e5cb08ac 4794 {
3e73aa7c
JH		 4795 /* 32bit checks. */
4796 if ((i.base_reg
4797 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4798 || (i.index_reg
29b0f896
AM		 4799 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4800 != (Reg32 | BaseIndex))))
e5cb08ac 4801 ok = 0;
3e73aa7c
JH		 4802 }
4803 }
4804 if (!ok)
24eab124
AM		 4805 {
4806#if INFER_ADDR_PREFIX
20f0a1fc 4807 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4808 {
4809 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4810 i.prefixes += 1;
b23bac36
AM		 4811 /* Change the size of any displacement too. At most one of
4812 Disp16 or Disp32 is set.
4813 FIXME. There doesn't seem to be any real need for separate
4814 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4815 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4816 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4817 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4818 fudged = 1;
24eab124
AM		 4819 goto tryprefix;
4820 }
eecb386c
AM		 4821 if (fudged)
4822 as_bad (_("`%s' is not a valid base/index expression"),
4823 operand_string);
4824 else
c388dee8 4825#endif
eecb386c
AM		 4826 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4827 operand_string,
3e73aa7c 4828 flag_code_names[flag_code]);
24eab124 4829 }
20f0a1fc 4830 return ok;
24eab124 4831}
252b5132 4832
252b5132 4833/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4834 on error. */
252b5132 4835
252b5132
RH		 4836static int
4837i386_operand (operand_string)
4838 char *operand_string;
4839{
af6bdddf
AM		 4840 const reg_entry *r;
4841 char *end_op;
24eab124 4842 char *op_string = operand_string;
252b5132 4843
24eab124 4844 if (is_space_char (*op_string))
252b5132
RH		 4845 ++op_string;
4846
24eab124 4847 /* We check for an absolute prefix (differentiating,
47926f60 4848 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4849 if (*op_string == ABSOLUTE_PREFIX)
4850 {
4851 ++op_string;
4852 if (is_space_char (*op_string))
4853 ++op_string;
4854 i.types[this_operand] |= JumpAbsolute;
4855 }
252b5132 4856
47926f60 4857 /* Check if operand is a register. */
4d1bb795 4858 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4859 {
24eab124
AM		 4860 /* Check for a segment override by searching for ':' after a
4861 segment register. */
4862 op_string = end_op;
4863 if (is_space_char (*op_string))
4864 ++op_string;
4865 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4866 {
4867 switch (r->reg_num)
4868 {
4869 case 0:
4870 i.seg[i.mem_operands] = &es;
4871 break;
4872 case 1:
4873 i.seg[i.mem_operands] = &cs;
4874 break;
4875 case 2:
4876 i.seg[i.mem_operands] = &ss;
4877 break;
4878 case 3:
4879 i.seg[i.mem_operands] = &ds;
4880 break;
4881 case 4:
4882 i.seg[i.mem_operands] = &fs;
4883 break;
4884 case 5:
4885 i.seg[i.mem_operands] = &gs;
4886 break;
4887 }
252b5132 4888
24eab124 4889 /* Skip the ':' and whitespace. */
252b5132
RH		 4890 ++op_string;
4891 if (is_space_char (*op_string))
24eab124 4892 ++op_string;
252b5132 4893
24eab124
AM		 4894 if (!is_digit_char (*op_string)
4895 && !is_identifier_char (*op_string)
4896 && *op_string != '('
4897 && *op_string != ABSOLUTE_PREFIX)
4898 {
4899 as_bad (_("bad memory operand `%s'"), op_string);
4900 return 0;
4901 }
47926f60 4902 /* Handle case of %es:*foo. */
24eab124
AM		 4903 if (*op_string == ABSOLUTE_PREFIX)
4904 {
4905 ++op_string;
4906 if (is_space_char (*op_string))
4907 ++op_string;
4908 i.types[this_operand] |= JumpAbsolute;
4909 }
4910 goto do_memory_reference;
4911 }
4912 if (*op_string)
4913 {
d0b47220 4914 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4915 return 0;
4916 }
4917 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4918 i.op[this_operand].regs = r;
24eab124
AM		 4919 i.reg_operands++;
4920 }
af6bdddf
AM		 4921 else if (*op_string == REGISTER_PREFIX)
4922 {
4923 as_bad (_("bad register name `%s'"), op_string);
4924 return 0;
4925 }
24eab124 4926 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4927 {
24eab124
AM		 4928 ++op_string;
4929 if (i.types[this_operand] & JumpAbsolute)
4930 {
d0b47220 4931 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4932 return 0;
4933 }
4934 if (!i386_immediate (op_string))
4935 return 0;
4936 }
4937 else if (is_digit_char (*op_string)
4938 || is_identifier_char (*op_string)
e5cb08ac 4939 || *op_string == '(')
24eab124 4940 {
47926f60 4941 /* This is a memory reference of some sort. */
af6bdddf 4942 char *base_string;
252b5132 4943
47926f60 4944 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4945 char *displacement_string_start;
4946 char *displacement_string_end;
252b5132 4947
24eab124 4948 do_memory_reference:
24eab124
AM		 4949 if ((i.mem_operands == 1
4950 && (current_templates->start->opcode_modifier & IsString) == 0)
4951 || i.mem_operands == 2)
4952 {
4953 as_bad (_("too many memory references for `%s'"),
4954 current_templates->start->name);
4955 return 0;
4956 }
252b5132 4957
24eab124
AM		 4958 /* Check for base index form. We detect the base index form by
4959 looking for an ')' at the end of the operand, searching
4960 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4961 after the '('. */
af6bdddf 4962 base_string = op_string + strlen (op_string);
c3332e24 4963
af6bdddf
AM		 4964 --base_string;
4965 if (is_space_char (*base_string))
4966 --base_string;
252b5132 4967
47926f60 4968 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4969 displacement_string_start = op_string;
4970 displacement_string_end = base_string + 1;
252b5132 4971
24eab124
AM		 4972 if (*base_string == ')')
4973 {
af6bdddf 4974 char *temp_string;
24eab124
AM		 4975 unsigned int parens_balanced = 1;
4976 /* We've already checked that the number of left & right ()'s are
47926f60 4977 equal, so this loop will not be infinite. */
24eab124
AM		 4978 do
4979 {
4980 base_string--;
4981 if (*base_string == ')')
4982 parens_balanced++;
4983 if (*base_string == '(')
4984 parens_balanced--;
4985 }
4986 while (parens_balanced);
c3332e24 4987
af6bdddf 4988 temp_string = base_string;
c3332e24 4989
24eab124 4990 /* Skip past '(' and whitespace. */
252b5132
RH		 4991 ++base_string;
4992 if (is_space_char (*base_string))
24eab124 4993 ++base_string;
252b5132 4994
af6bdddf 4995 if (*base_string == ','
4d1bb795 4996 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4997 {
af6bdddf 4998 displacement_string_end = temp_string;
252b5132 4999
af6bdddf 5000 i.types[this_operand] |= BaseIndex;
252b5132 5001
af6bdddf 5002 if (i.base_reg)
24eab124 5003 {
24eab124
AM		 5004 base_string = end_op;
5005 if (is_space_char (*base_string))
5006 ++base_string;
af6bdddf
AM		 5007 }
5008
5009 /* There may be an index reg or scale factor here. */
5010 if (*base_string == ',')
5011 {
5012 ++base_string;
5013 if (is_space_char (*base_string))
5014 ++base_string;
5015
4d1bb795 5016 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 5017 {
af6bdddf 5018 base_string = end_op;
24eab124
AM		 5019 if (is_space_char (*base_string))
5020 ++base_string;
af6bdddf
AM		 5021 if (*base_string == ',')
5022 {
5023 ++base_string;
5024 if (is_space_char (*base_string))
5025 ++base_string;
5026 }
e5cb08ac 5027 else if (*base_string != ')')
af6bdddf
AM		 5028 {
5029 as_bad (_("expecting `,' or `)' after index register in `%s'"),
5030 operand_string);
5031 return 0;
5032 }
24eab124 5033 }
af6bdddf 5034 else if (*base_string == REGISTER_PREFIX)
24eab124 5035 {
af6bdddf 5036 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 5037 return 0;
5038 }
252b5132 5039
47926f60 5040 /* Check for scale factor. */
551c1ca1 5041 if (*base_string != ')')
af6bdddf 5042 {
551c1ca1
AM		 5043 char *end_scale = i386_scale (base_string);
5044
5045 if (!end_scale)
af6bdddf 5046 return 0;
24eab124 5047
551c1ca1 5048 base_string = end_scale;
af6bdddf
AM		 5049 if (is_space_char (*base_string))
5050 ++base_string;
5051 if (*base_string != ')')
5052 {
5053 as_bad (_("expecting `)' after scale factor in `%s'"),
5054 operand_string);
5055 return 0;
5056 }
5057 }
5058 else if (!i.index_reg)
24eab124 5059 {
af6bdddf
AM		 5060 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
5061 *base_string);
24eab124
AM		 5062 return 0;
5063 }
5064 }
af6bdddf 5065 else if (*base_string != ')')
24eab124 5066 {
af6bdddf
AM		 5067 as_bad (_("expecting `,' or `)' after base register in `%s'"),
5068 operand_string);
24eab124
AM		 5069 return 0;
5070 }
c3332e24 5071 }
af6bdddf 5072 else if (*base_string == REGISTER_PREFIX)
c3332e24 5073 {
af6bdddf 5074 as_bad (_("bad register name `%s'"), base_string);
24eab124 5075 return 0;
c3332e24 5076 }
24eab124
AM		 5077 }
5078
5079 /* If there's an expression beginning the operand, parse it,
5080 assuming displacement_string_start and
5081 displacement_string_end are meaningful. */
5082 if (displacement_string_start != displacement_string_end)
5083 {
5084 if (!i386_displacement (displacement_string_start,
5085 displacement_string_end))
5086 return 0;
5087 }
5088
5089 /* Special case for (%dx) while doing input/output op. */
5090 if (i.base_reg
5091 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
5092 && i.index_reg == 0
5093 && i.log2_scale_factor == 0
5094 && i.seg[i.mem_operands] == 0
5095 && (i.types[this_operand] & Disp) == 0)
5096 {
5097 i.types[this_operand] = InOutPortReg;
5098 return 1;
5099 }
5100
eecb386c
AM		 5101 if (i386_index_check (operand_string) == 0)
5102 return 0;
24eab124
AM		 5103 i.mem_operands++;
5104 }
5105 else
ce8a8b2f
AM		 5106 {
5107 /* It's not a memory operand; argh! */
24eab124
AM		 5108 as_bad (_("invalid char %s beginning operand %d `%s'"),
5109 output_invalid (*op_string),
5110 this_operand + 1,
5111 op_string);
5112 return 0;
5113 }
47926f60 5114 return 1; /* Normal return. */
252b5132
RH		 5115}
5116\f
ee7fcc42
AM		 5117/* md_estimate_size_before_relax()
5118
5119 Called just before relax() for rs_machine_dependent frags. The x86
5120 assembler uses these frags to handle variable size jump
5121 instructions.
5122
5123 Any symbol that is now undefined will not become defined.
5124 Return the correct fr_subtype in the frag.
5125 Return the initial "guess for variable size of frag" to caller.
5126 The guess is actually the growth beyond the fixed part. Whatever
5127 we do to grow the fixed or variable part contributes to our
5128 returned value. */
5129
252b5132
RH		 5130int
5131md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 5132 fragS *fragP;
5133 segT segment;
252b5132 5134{
252b5132 5135 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 5136 check for un-relaxable symbols. On an ELF system, we can't relax
5137 an externally visible symbol, because it may be overridden by a
5138 shared library. */
5139 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 5140#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5141 || (IS_ELF
31312f95
AM		 5142 && (S_IS_EXTERNAL (fragP->fr_symbol)
5143 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 5144#endif
5145 )
252b5132 5146 {
b98ef147
AM		 5147 /* Symbol is undefined in this segment, or we need to keep a
5148 reloc so that weak symbols can be overridden. */
5149 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 5150 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 5151 unsigned char *opcode;
5152 int old_fr_fix;
f6af82bd 5153
ee7fcc42
AM		 5154 if (fragP->fr_var != NO_RELOC)
5155 reloc_type = fragP->fr_var;
b98ef147 5156 else if (size == 2)
f6af82bd
AM		 5157 reloc_type = BFD_RELOC_16_PCREL;
5158 else
5159 reloc_type = BFD_RELOC_32_PCREL;
252b5132 5160
ee7fcc42
AM		 5161 old_fr_fix = fragP->fr_fix;
5162 opcode = (unsigned char *) fragP->fr_opcode;
5163
fddf5b5b 5164 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 5165 {
fddf5b5b
AM		 5166 case UNCOND_JUMP:
5167 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 5168 opcode[0] = 0xe9;
252b5132 5169 fragP->fr_fix += size;
062cd5e7
AS		 5170 fix_new (fragP, old_fr_fix, size,
5171 fragP->fr_symbol,
5172 fragP->fr_offset, 1,
5173 reloc_type);
252b5132
RH		 5174 break;
5175
fddf5b5b 5176 case COND_JUMP86:
412167cb
AM		 5177 if (size == 2
5178 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 5179 {
5180 /* Negate the condition, and branch past an
5181 unconditional jump. */
5182 opcode[0] ^= 1;
5183 opcode[1] = 3;
5184 /* Insert an unconditional jump. */
5185 opcode[2] = 0xe9;
5186 /* We added two extra opcode bytes, and have a two byte
5187 offset. */
5188 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 5189 fix_new (fragP, old_fr_fix + 2, 2,
5190 fragP->fr_symbol,
5191 fragP->fr_offset, 1,
5192 reloc_type);
fddf5b5b
AM		 5193 break;
5194 }
5195 /* Fall through. */
5196
5197 case COND_JUMP:
412167cb
AM		 5198 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
5199 {
3e02c1cc
AM		 5200 fixS *fixP;
5201
412167cb 5202 fragP->fr_fix += 1;
3e02c1cc
AM		 5203 fixP = fix_new (fragP, old_fr_fix, 1,
5204 fragP->fr_symbol,
5205 fragP->fr_offset, 1,
5206 BFD_RELOC_8_PCREL);
5207 fixP->fx_signed = 1;
412167cb
AM		 5208 break;
5209 }
93c2a809 5210
24eab124 5211 /* This changes the byte-displacement jump 0x7N
fddf5b5b 5212 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 5213 opcode[1] = opcode[0] + 0x10;
f6af82bd 5214 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 5215 /* We've added an opcode byte. */
5216 fragP->fr_fix += 1 + size;
062cd5e7
AS		 5217 fix_new (fragP, old_fr_fix + 1, size,
5218 fragP->fr_symbol,
5219 fragP->fr_offset, 1,
5220 reloc_type);
252b5132 5221 break;
fddf5b5b
AM		 5222
5223 default:
5224 BAD_CASE (fragP->fr_subtype);
5225 break;
252b5132
RH		 5226 }
5227 frag_wane (fragP);
ee7fcc42 5228 return fragP->fr_fix - old_fr_fix;
252b5132 5229 }
93c2a809 5230
93c2a809
AM		 5231 /* Guess size depending on current relax state. Initially the relax
5232 state will correspond to a short jump and we return 1, because
5233 the variable part of the frag (the branch offset) is one byte
5234 long. However, we can relax a section more than once and in that
5235 case we must either set fr_subtype back to the unrelaxed state,
5236 or return the value for the appropriate branch. */
5237 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 5238}
5239
47926f60
KH		 5240/* Called after relax() is finished.
5241
5242 In: Address of frag.
5243 fr_type == rs_machine_dependent.
5244 fr_subtype is what the address relaxed to.
5245
5246 Out: Any fixSs and constants are set up.
5247 Caller will turn frag into a ".space 0". */
5248
252b5132
RH		 5249void
5250md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 5251 bfd *abfd ATTRIBUTE_UNUSED;
5252 segT sec ATTRIBUTE_UNUSED;
29b0f896 5253 fragS *fragP;
252b5132 5254{
29b0f896 5255 unsigned char *opcode;
252b5132 5256 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 5257 offsetT target_address;
5258 offsetT opcode_address;
252b5132 5259 unsigned int extension = 0;
847f7ad4 5260 offsetT displacement_from_opcode_start;
252b5132
RH		 5261
5262 opcode = (unsigned char *) fragP->fr_opcode;
5263
47926f60 5264 /* Address we want to reach in file space. */
252b5132 5265 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 5266
47926f60 5267 /* Address opcode resides at in file space. */
252b5132
RH		 5268 opcode_address = fragP->fr_address + fragP->fr_fix;
5269
47926f60 5270 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 5271 displacement_from_opcode_start = target_address - opcode_address;
5272
fddf5b5b 5273 if ((fragP->fr_subtype & BIG) == 0)
252b5132 5274 {
47926f60
KH		 5275 /* Don't have to change opcode. */
5276 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5277 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5278 }
5279 else
5280 {
5281 if (no_cond_jump_promotion
5282 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5283 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5284
fddf5b5b
AM		 5285 switch (fragP->fr_subtype)
5286 {
5287 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5288 extension = 4; /* 1 opcode + 4 displacement */
5289 opcode[0] = 0xe9;
5290 where_to_put_displacement = &opcode[1];
5291 break;
252b5132 5292
fddf5b5b
AM		 5293 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5294 extension = 2; /* 1 opcode + 2 displacement */
5295 opcode[0] = 0xe9;
5296 where_to_put_displacement = &opcode[1];
5297 break;
252b5132 5298
fddf5b5b
AM		 5299 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5300 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5301 extension = 5; /* 2 opcode + 4 displacement */
5302 opcode[1] = opcode[0] + 0x10;
5303 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5304 where_to_put_displacement = &opcode[2];
5305 break;
252b5132 5306
fddf5b5b
AM		 5307 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5308 extension = 3; /* 2 opcode + 2 displacement */
5309 opcode[1] = opcode[0] + 0x10;
5310 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5311 where_to_put_displacement = &opcode[2];
5312 break;
252b5132 5313
fddf5b5b
AM		 5314 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5315 extension = 4;
5316 opcode[0] ^= 1;
5317 opcode[1] = 3;
5318 opcode[2] = 0xe9;
5319 where_to_put_displacement = &opcode[3];
5320 break;
5321
5322 default:
5323 BAD_CASE (fragP->fr_subtype);
5324 break;
5325 }
252b5132 5326 }
fddf5b5b 5327
7b81dfbb
AJ		 5328 /* If size if less then four we are sure that the operand fits,
5329 but if it's 4, then it could be that the displacement is larger
5330 then -/+ 2GB. */
5331 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5332 && object_64bit
5333 && ((addressT) (displacement_from_opcode_start - extension
5334 + ((addressT) 1 << 31))
5335 > (((addressT) 2 << 31) - 1)))
5336 {
5337 as_bad_where (fragP->fr_file, fragP->fr_line,
5338 _("jump target out of range"));
5339 /* Make us emit 0. */
5340 displacement_from_opcode_start = extension;
5341 }
47926f60 5342 /* Now put displacement after opcode. */
252b5132
RH		 5343 md_number_to_chars ((char *) where_to_put_displacement,
5344 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5345 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5346 fragP->fr_fix += extension;
5347}
5348\f
47926f60
KH		 5349/* Size of byte displacement jmp. */
5350int md_short_jump_size = 2;
5351
5352/* Size of dword displacement jmp. */
5353int md_long_jump_size = 5;
252b5132 5354
252b5132
RH		 5355void
5356md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5357 char *ptr;
5358 addressT from_addr, to_addr;
ab9da554
ILT		 5359 fragS *frag ATTRIBUTE_UNUSED;
5360 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5361{
847f7ad4 5362 offsetT offset;
252b5132
RH		 5363
5364 offset = to_addr - (from_addr + 2);
47926f60
KH		 5365 /* Opcode for byte-disp jump. */
5366 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5367 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5368}
5369
5370void
5371md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5372 char *ptr;
5373 addressT from_addr, to_addr;
a38cf1db
AM		 5374 fragS *frag ATTRIBUTE_UNUSED;
5375 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5376{
847f7ad4 5377 offsetT offset;
252b5132 5378
a38cf1db
AM		 5379 offset = to_addr - (from_addr + 5);
5380 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5381 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5382}
5383\f
5384/* Apply a fixup (fixS) to segment data, once it has been determined
5385 by our caller that we have all the info we need to fix it up.
5386
5387 On the 386, immediates, displacements, and data pointers are all in
5388 the same (little-endian) format, so we don't need to care about which
5389 we are handling. */
5390
94f592af 5391void
55cf6793 5392md_apply_fix (fixP, valP, seg)
47926f60
KH		 5393 /* The fix we're to put in. */
5394 fixS *fixP;
47926f60 5395 /* Pointer to the value of the bits. */
c6682705 5396 valueT *valP;
47926f60
KH		 5397 /* Segment fix is from. */
5398 segT seg ATTRIBUTE_UNUSED;
252b5132 5399{
94f592af 5400 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5401 valueT value = *valP;
252b5132 5402
f86103b7 5403#if !defined (TE_Mach)
93382f6d
AM		 5404 if (fixP->fx_pcrel)
5405 {
5406 switch (fixP->fx_r_type)
5407 {
5865bb77
ILT		 5408 default:
5409 break;
5410
d6ab8113
JB		 5411 case BFD_RELOC_64:
5412 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5413 break;
93382f6d 5414 case BFD_RELOC_32:
ae8887b5 5415 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5416 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5417 break;
5418 case BFD_RELOC_16:
5419 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5420 break;
5421 case BFD_RELOC_8:
5422 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5423 break;
5424 }
5425 }
252b5132 5426
a161fe53 5427 if (fixP->fx_addsy != NULL
31312f95 5428 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5429 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5430 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5431 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5432 && !use_rela_relocations)
252b5132 5433 {
31312f95
AM		 5434 /* This is a hack. There should be a better way to handle this.
5435 This covers for the fact that bfd_install_relocation will
5436 subtract the current location (for partial_inplace, PC relative
5437 relocations); see more below. */
252b5132 5438#ifndef OBJ_AOUT
718ddfc0 5439 if (IS_ELF
252b5132
RH		 5440#ifdef TE_PE
5441 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5442#endif
5443 )
5444 value += fixP->fx_where + fixP->fx_frag->fr_address;
5445#endif
5446#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5447 if (IS_ELF)
252b5132 5448 {
6539b54b 5449 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5450
6539b54b 5451 if ((sym_seg == seg
2f66722d 5452 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5453 && sym_seg != absolute_section))
ae6063d4 5454 && !generic_force_reloc (fixP))
2f66722d
AM		 5455 {
5456 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5457 bfd_install_relocation subtracts them out again. I think
5458 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5459 it. FIXME. */
5460 value += fixP->fx_where + fixP->fx_frag->fr_address;
5461 }
252b5132
RH		 5462 }
5463#endif
5464#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5465 /* For some reason, the PE format does not store a
5466 section address offset for a PC relative symbol. */
5467 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5468 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5469 value += md_pcrel_from (fixP);
5470#endif
5471 }
5472
5473 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5474 and we must not disappoint it. */
252b5132 5475#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5476 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5477 switch (fixP->fx_r_type)
5478 {
5479 case BFD_RELOC_386_PLT32:
3e73aa7c 5480 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5481 /* Make the jump instruction point to the address of the operand. At
5482 runtime we merely add the offset to the actual PLT entry. */
5483 value = -4;
5484 break;
31312f95 5485
13ae64f3
JJ		 5486 case BFD_RELOC_386_TLS_GD:
5487 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5488 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5489 case BFD_RELOC_386_TLS_IE:
5490 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5491 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5492 case BFD_RELOC_X86_64_TLSGD:
5493 case BFD_RELOC_X86_64_TLSLD:
5494 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5495 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5496 value = 0; /* Fully resolved at runtime. No addend. */
5497 /* Fallthrough */
5498 case BFD_RELOC_386_TLS_LE:
5499 case BFD_RELOC_386_TLS_LDO_32:
5500 case BFD_RELOC_386_TLS_LE_32:
5501 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5502 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5503 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5504 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5505 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5506 break;
5507
67a4f2b7
AO		 5508 case BFD_RELOC_386_TLS_DESC_CALL:
5509 case BFD_RELOC_X86_64_TLSDESC_CALL:
5510 value = 0; /* Fully resolved at runtime. No addend. */
5511 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5512 fixP->fx_done = 0;
5513 return;
5514
00f7efb6
JJ		 5515 case BFD_RELOC_386_GOT32:
5516 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5517 value = 0; /* Fully resolved at runtime. No addend. */
5518 break;
47926f60
KH		 5519
5520 case BFD_RELOC_VTABLE_INHERIT:
5521 case BFD_RELOC_VTABLE_ENTRY:
5522 fixP->fx_done = 0;
94f592af 5523 return;
47926f60
KH		 5524
5525 default:
5526 break;
5527 }
5528#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5529 *valP = value;
f86103b7 5530#endif /* !defined (TE_Mach) */
3e73aa7c 5531
3e73aa7c 5532 /* Are we finished with this relocation now? */
c6682705 5533 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5534 fixP->fx_done = 1;
5535 else if (use_rela_relocations)
5536 {
5537 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5538 /* Remember value for tc_gen_reloc. */
5539 fixP->fx_addnumber = value;
3e73aa7c
JH		 5540 value = 0;
5541 }
f86103b7 5542
94f592af 5543 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5544}
252b5132 5545\f
252b5132
RH		 5546#define MAX_LITTLENUMS 6
5547
47926f60
KH		 5548/* Turn the string pointed to by litP into a floating point constant
5549 of type TYPE, and emit the appropriate bytes. The number of
5550 LITTLENUMS emitted is stored in *SIZEP. An error message is
5551 returned, or NULL on OK. */
5552
252b5132
RH		 5553char *
5554md_atof (type, litP, sizeP)
2ab9b79e 5555 int type;
252b5132
RH		 5556 char *litP;
5557 int *sizeP;
5558{
5559 int prec;
5560 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5561 LITTLENUM_TYPE *wordP;
5562 char *t;
5563
5564 switch (type)
5565 {
5566 case 'f':
5567 case 'F':
5568 prec = 2;
5569 break;
5570
5571 case 'd':
5572 case 'D':
5573 prec = 4;
5574 break;
5575
5576 case 'x':
5577 case 'X':
5578 prec = 5;
5579 break;
5580
5581 default:
5582 *sizeP = 0;
5583 return _("Bad call to md_atof ()");
5584 }
5585 t = atof_ieee (input_line_pointer, type, words);
5586 if (t)
5587 input_line_pointer = t;
5588
5589 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5590 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5591 the bigendian 386. */
5592 for (wordP = words + prec - 1; prec--;)
5593 {
5594 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5595 litP += sizeof (LITTLENUM_TYPE);
5596 }
5597 return 0;
5598}
5599\f
2d545b82 5600static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5601
252b5132
RH		 5602static char *
5603output_invalid (c)
5604 int c;
5605{
3882b010 5606 if (ISPRINT (c))
f9f21a03
L		 5607 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5608 "'%c'", c);
252b5132 5609 else
f9f21a03 5610 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5611 "(0x%x)", (unsigned char) c);
252b5132
RH		 5612 return output_invalid_buf;
5613}
5614
af6bdddf 5615/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5616
5617static const reg_entry *
4d1bb795 5618parse_real_register (char *reg_string, char **end_op)
252b5132 5619{
af6bdddf
AM		 5620 char *s = reg_string;
5621 char *p;
252b5132
RH		 5622 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5623 const reg_entry *r;
5624
5625 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5626 if (*s == REGISTER_PREFIX)
5627 ++s;
5628
5629 if (is_space_char (*s))
5630 ++s;
5631
5632 p = reg_name_given;
af6bdddf 5633 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5634 {
5635 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5636 return (const reg_entry *) NULL;
5637 s++;
252b5132
RH		 5638 }
5639
6588847e
DN		 5640 /* For naked regs, make sure that we are not dealing with an identifier.
5641 This prevents confusing an identifier like `eax_var' with register
5642 `eax'. */
5643 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5644 return (const reg_entry *) NULL;
5645
af6bdddf 5646 *end_op = s;
252b5132
RH		 5647
5648 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5649
5f47d35b 5650 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5651 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5652 {
5f47d35b
AM		 5653 if (is_space_char (*s))
5654 ++s;
5655 if (*s == '(')
5656 {
af6bdddf 5657 ++s;
5f47d35b
AM		 5658 if (is_space_char (*s))
5659 ++s;
5660 if (*s >= '0' && *s <= '7')
5661 {
5662 r = &i386_float_regtab[*s - '0'];
af6bdddf 5663 ++s;
5f47d35b
AM		 5664 if (is_space_char (*s))
5665 ++s;
5666 if (*s == ')')
5667 {
5668 *end_op = s + 1;
5669 return r;
5670 }
5f47d35b 5671 }
47926f60 5672 /* We have "%st(" then garbage. */
5f47d35b
AM		 5673 return (const reg_entry *) NULL;
5674 }
5675 }
5676
1ae00879 5677 if (r != NULL
20f0a1fc 5678 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5679 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5680 && flag_code != CODE_64BIT)
20f0a1fc 5681 return (const reg_entry *) NULL;
1ae00879 5682
252b5132
RH		 5683 return r;
5684}
4d1bb795
JB		 5685
5686/* REG_STRING starts *before* REGISTER_PREFIX. */
5687
5688static const reg_entry *
5689parse_register (char *reg_string, char **end_op)
5690{
5691 const reg_entry *r;
5692
5693 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5694 r = parse_real_register (reg_string, end_op);
5695 else
5696 r = NULL;
5697 if (!r)
5698 {
5699 char *save = input_line_pointer;
5700 char c;
5701 symbolS *symbolP;
5702
5703 input_line_pointer = reg_string;
5704 c = get_symbol_end ();
5705 symbolP = symbol_find (reg_string);
5706 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5707 {
5708 const expressionS *e = symbol_get_value_expression (symbolP);
5709
5710 know (e->X_op == O_register);
5711 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5712 r = i386_regtab + e->X_add_number;
5713 *end_op = input_line_pointer;
5714 }
5715 *input_line_pointer = c;
5716 input_line_pointer = save;
5717 }
5718 return r;
5719}
5720
5721int
5722i386_parse_name (char *name, expressionS *e, char *nextcharP)
5723{
5724 const reg_entry *r;
5725 char *end = input_line_pointer;
5726
5727 *end = *nextcharP;
5728 r = parse_register (name, &input_line_pointer);
5729 if (r && end <= input_line_pointer)
5730 {
5731 *nextcharP = *input_line_pointer;
5732 *input_line_pointer = 0;
5733 e->X_op = O_register;
5734 e->X_add_number = r - i386_regtab;
5735 return 1;
5736 }
5737 input_line_pointer = end;
5738 *end = 0;
5739 return 0;
5740}
5741
5742void
5743md_operand (expressionS *e)
5744{
5745 if (*input_line_pointer == REGISTER_PREFIX)
5746 {
5747 char *end;
5748 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5749
5750 if (r)
5751 {
5752 e->X_op = O_register;
5753 e->X_add_number = r - i386_regtab;
5754 input_line_pointer = end;
5755 }
5756 }
5757}
5758
252b5132 5759\f
4cc782b5 5760#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5761const char *md_shortopts = "kVQ:sqn";
252b5132 5762#else
12b55ccc 5763const char *md_shortopts = "qn";
252b5132 5764#endif
6e0b89ee 5765
3e73aa7c 5766#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5767#define OPTION_64 (OPTION_MD_BASE + 1)
5768#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5769#define OPTION_MARCH (OPTION_MD_BASE + 3)
5770#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714
AM		 5771
5772struct option md_longopts[] = {
3e73aa7c 5773 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5774#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c 5775 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5776#endif
b3b91714 5777 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5778 {"march", required_argument, NULL, OPTION_MARCH},
5779 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5780 {NULL, no_argument, NULL, 0}
5781};
5782size_t md_longopts_size = sizeof (md_longopts);
5783
5784int
9103f4f4 5785md_parse_option (int c, char *arg)
252b5132 5786{
9103f4f4
L		 5787 unsigned int i;
5788
252b5132
RH		 5789 switch (c)
5790 {
12b55ccc
L		 5791 case 'n':
5792 optimize_align_code = 0;
5793 break;
5794
a38cf1db
AM		 5795 case 'q':
5796 quiet_warnings = 1;
252b5132
RH		 5797 break;
5798
5799#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5800 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5801 should be emitted or not. FIXME: Not implemented. */
5802 case 'Q':
252b5132
RH		 5803 break;
5804
5805 /* -V: SVR4 argument to print version ID. */
5806 case 'V':
5807 print_version_id ();
5808 break;
5809
a38cf1db
AM		 5810 /* -k: Ignore for FreeBSD compatibility. */
5811 case 'k':
252b5132 5812 break;
4cc782b5
ILT		 5813
5814 case 's':
5815 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5816 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5817 break;
6e0b89ee 5818
3e73aa7c
JH		 5819 case OPTION_64:
5820 {
5821 const char **list, **l;
5822
3e73aa7c
JH		 5823 list = bfd_target_list ();
5824 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5825 if (strcmp (*l, "elf64-x86-64") == 0)
5826 {
5827 default_arch = "x86_64";
5828 break;
5829 }
3e73aa7c 5830 if (*l == NULL)
6e0b89ee 5831 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5832 free (list);
5833 }
5834 break;
5835#endif
252b5132 5836
6e0b89ee
AM		 5837 case OPTION_32:
5838 default_arch = "i386";
5839 break;
5840
b3b91714
AM		 5841 case OPTION_DIVIDE:
5842#ifdef SVR4_COMMENT_CHARS
5843 {
5844 char *n, *t;
5845 const char *s;
5846
5847 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5848 t = n;
5849 for (s = i386_comment_chars; *s != '\0'; s++)
5850 if (*s != '/')
5851 *t++ = *s;
5852 *t = '\0';
5853 i386_comment_chars = n;
5854 }
5855#endif
5856 break;
5857
9103f4f4
L		 5858 case OPTION_MARCH:
5859 if (*arg == '.')
5860 as_fatal (_("Invalid -march= option: `%s'"), arg);
5861 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5862 {
5863 if (strcmp (arg, cpu_arch [i].name) == 0)
5864 {
ccc9c027 5865 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 5866 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 5867 if (!cpu_arch_tune_set)
5868 {
5869 cpu_arch_tune = cpu_arch_isa;
5870 cpu_arch_tune_flags = cpu_arch_isa_flags;
5871 }
9103f4f4
L		 5872 break;
5873 }
5874 }
5875 if (i >= ARRAY_SIZE (cpu_arch))
5876 as_fatal (_("Invalid -march= option: `%s'"), arg);
5877 break;
5878
5879 case OPTION_MTUNE:
5880 if (*arg == '.')
5881 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5882 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5883 {
5884 if (strcmp (arg, cpu_arch [i].name) == 0)
5885 {
ccc9c027 5886 cpu_arch_tune_set = 1;
9103f4f4
L		 5887 cpu_arch_tune = cpu_arch [i].type;
5888 cpu_arch_tune_flags = cpu_arch[i].flags;
5889 break;
5890 }
5891 }
5892 if (i >= ARRAY_SIZE (cpu_arch))
5893 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5894 break;
5895
252b5132
RH		 5896 default:
5897 return 0;
5898 }
5899 return 1;
5900}
5901
5902void
5903md_show_usage (stream)
5904 FILE *stream;
5905{
4cc782b5
ILT		 5906#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5907 fprintf (stream, _("\
a38cf1db
AM		 5908 -Q ignored\n\
5909 -V print assembler version number\n\
b3b91714
AM		 5910 -k ignored\n"));
5911#endif
5912 fprintf (stream, _("\
12b55ccc 5913 -n Do not optimize code alignment\n\
b3b91714
AM		 5914 -q quieten some warnings\n"));
5915#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5916 fprintf (stream, _("\
a38cf1db 5917 -s ignored\n"));
b3b91714
AM		 5918#endif
5919#ifdef SVR4_COMMENT_CHARS
5920 fprintf (stream, _("\
5921 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5922#else
5923 fprintf (stream, _("\
b3b91714 5924 --divide ignored\n"));
4cc782b5 5925#endif
9103f4f4
L		 5926 fprintf (stream, _("\
5927 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5928 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5929 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5930
252b5132
RH		 5931}
5932
3e73aa7c
JH		 5933#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5934 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5935
5936/* Pick the target format to use. */
5937
47926f60 5938const char *
252b5132
RH		 5939i386_target_format ()
5940{
3e73aa7c 5941 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 5942 {
5943 set_code_flag (CODE_64BIT);
5944 if (cpu_arch_isa_flags == 0)
5945 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5946 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5947 |CpuSSE|CpuSSE2;
ccc9c027
L		 5948 if (cpu_arch_tune_flags == 0)
5949 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5950 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5951 |CpuSSE|CpuSSE2;
9103f4f4 5952 }
3e73aa7c 5953 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 5954 {
5955 set_code_flag (CODE_32BIT);
5956 if (cpu_arch_isa_flags == 0)
5957 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386;
ccc9c027
L		 5958 if (cpu_arch_tune_flags == 0)
5959 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386;
9103f4f4 5960 }
3e73aa7c
JH		 5961 else
5962 as_fatal (_("Unknown architecture"));
252b5132
RH		 5963 switch (OUTPUT_FLAVOR)
5964 {
4c63da97
AM		 5965#ifdef OBJ_MAYBE_AOUT
5966 case bfd_target_aout_flavour:
47926f60 5967 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5968#endif
5969#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5970 case bfd_target_coff_flavour:
5971 return "coff-i386";
4c63da97 5972#endif
3e73aa7c 5973#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5974 case bfd_target_elf_flavour:
3e73aa7c 5975 {
e5cb08ac 5976 if (flag_code == CODE_64BIT)
4fa24527
JB		 5977 {
5978 object_64bit = 1;
5979 use_rela_relocations = 1;
5980 }
4ada7262 5981 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5982 }
4c63da97 5983#endif
252b5132
RH		 5984 default:
5985 abort ();
5986 return NULL;
5987 }
5988}
5989
47926f60 5990#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5991
5992#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5993void i386_elf_emit_arch_note ()
5994{
718ddfc0 5995 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5996 {
5997 char *p;
5998 asection *seg = now_seg;
5999 subsegT subseg = now_subseg;
6000 Elf_Internal_Note i_note;
6001 Elf_External_Note e_note;
6002 asection *note_secp;
6003 int len;
6004
6005 /* Create the .note section. */
6006 note_secp = subseg_new (".note", 0);
6007 bfd_set_section_flags (stdoutput,
6008 note_secp,
6009 SEC_HAS_CONTENTS | SEC_READONLY);
6010
6011 /* Process the arch string. */
6012 len = strlen (cpu_arch_name);
6013
6014 i_note.namesz = len + 1;
6015 i_note.descsz = 0;
6016 i_note.type = NT_ARCH;
6017 p = frag_more (sizeof (e_note.namesz));
6018 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
6019 p = frag_more (sizeof (e_note.descsz));
6020 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
6021 p = frag_more (sizeof (e_note.type));
6022 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
6023 p = frag_more (len + 1);
6024 strcpy (p, cpu_arch_name);
6025
6026 frag_align (2, 0, 0);
6027
6028 subseg_set (seg, subseg);
6029 }
6030}
6031#endif
252b5132 6032\f
252b5132
RH		 6033symbolS *
6034md_undefined_symbol (name)
6035 char *name;
6036{
18dc2407
ILT		 6037 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
6038 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
6039 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
6040 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 6041 {
6042 if (!GOT_symbol)
6043 {
6044 if (symbol_find (name))
6045 as_bad (_("GOT already in symbol table"));
6046 GOT_symbol = symbol_new (name, undefined_section,
6047 (valueT) 0, &zero_address_frag);
6048 };
6049 return GOT_symbol;
6050 }
252b5132
RH		 6051 return 0;
6052}
6053
6054/* Round up a section size to the appropriate boundary. */
47926f60 6055
252b5132
RH		 6056valueT
6057md_section_align (segment, size)
ab9da554 6058 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 6059 valueT size;
6060{
4c63da97
AM		 6061#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6062 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
6063 {
6064 /* For a.out, force the section size to be aligned. If we don't do
6065 this, BFD will align it for us, but it will not write out the
6066 final bytes of the section. This may be a bug in BFD, but it is
6067 easier to fix it here since that is how the other a.out targets
6068 work. */
6069 int align;
6070
6071 align = bfd_get_section_alignment (stdoutput, segment);
6072 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
6073 }
252b5132
RH		 6074#endif
6075
6076 return size;
6077}
6078
6079/* On the i386, PC-relative offsets are relative to the start of the
6080 next instruction. That is, the address of the offset, plus its
6081 size, since the offset is always the last part of the insn. */
6082
6083long
6084md_pcrel_from (fixP)
6085 fixS *fixP;
6086{
6087 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
6088}
6089
6090#ifndef I386COFF
6091
6092static void
6093s_bss (ignore)
ab9da554 6094 int ignore ATTRIBUTE_UNUSED;
252b5132 6095{
29b0f896 6096 int temp;
252b5132 6097
8a75718c
JB		 6098#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6099 if (IS_ELF)
6100 obj_elf_section_change_hook ();
6101#endif
252b5132
RH		 6102 temp = get_absolute_expression ();
6103 subseg_set (bss_section, (subsegT) temp);
6104 demand_empty_rest_of_line ();
6105}
6106
6107#endif
6108
252b5132
RH		 6109void
6110i386_validate_fix (fixp)
6111 fixS *fixp;
6112{
6113 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
6114 {
23df1078
JH		 6115 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
6116 {
4fa24527 6117 if (!object_64bit)
23df1078
JH		 6118 abort ();
6119 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
6120 }
6121 else
6122 {
4fa24527 6123 if (!object_64bit)
d6ab8113
JB		 6124 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
6125 else
6126 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 6127 }
252b5132
RH		 6128 fixp->fx_subsy = 0;
6129 }
6130}
6131
252b5132
RH		 6132arelent *
6133tc_gen_reloc (section, fixp)
ab9da554 6134 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 6135 fixS *fixp;
6136{
6137 arelent *rel;
6138 bfd_reloc_code_real_type code;
6139
6140 switch (fixp->fx_r_type)
6141 {
3e73aa7c
JH		 6142 case BFD_RELOC_X86_64_PLT32:
6143 case BFD_RELOC_X86_64_GOT32:
6144 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 6145 case BFD_RELOC_386_PLT32:
6146 case BFD_RELOC_386_GOT32:
6147 case BFD_RELOC_386_GOTOFF:
6148 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 6149 case BFD_RELOC_386_TLS_GD:
6150 case BFD_RELOC_386_TLS_LDM:
6151 case BFD_RELOC_386_TLS_LDO_32:
6152 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6153 case BFD_RELOC_386_TLS_IE:
6154 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 6155 case BFD_RELOC_386_TLS_LE_32:
6156 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 6157 case BFD_RELOC_386_TLS_GOTDESC:
6158 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 6159 case BFD_RELOC_X86_64_TLSGD:
6160 case BFD_RELOC_X86_64_TLSLD:
6161 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6162 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 6163 case BFD_RELOC_X86_64_GOTTPOFF:
6164 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 6165 case BFD_RELOC_X86_64_TPOFF64:
6166 case BFD_RELOC_X86_64_GOTOFF64:
6167 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 6168 case BFD_RELOC_X86_64_GOT64:
6169 case BFD_RELOC_X86_64_GOTPCREL64:
6170 case BFD_RELOC_X86_64_GOTPC64:
6171 case BFD_RELOC_X86_64_GOTPLT64:
6172 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 6173 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6174 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 6175 case BFD_RELOC_RVA:
6176 case BFD_RELOC_VTABLE_ENTRY:
6177 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 6178#ifdef TE_PE
6179 case BFD_RELOC_32_SECREL:
6180#endif
252b5132
RH		 6181 code = fixp->fx_r_type;
6182 break;
dbbaec26
L		 6183 case BFD_RELOC_X86_64_32S:
6184 if (!fixp->fx_pcrel)
6185 {
6186 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
6187 code = fixp->fx_r_type;
6188 break;
6189 }
252b5132 6190 default:
93382f6d 6191 if (fixp->fx_pcrel)
252b5132 6192 {
93382f6d
AM		 6193 switch (fixp->fx_size)
6194 {
6195 default:
b091f402
AM		 6196 as_bad_where (fixp->fx_file, fixp->fx_line,
6197 _("can not do %d byte pc-relative relocation"),
6198 fixp->fx_size);
93382f6d
AM		 6199 code = BFD_RELOC_32_PCREL;
6200 break;
6201 case 1: code = BFD_RELOC_8_PCREL; break;
6202 case 2: code = BFD_RELOC_16_PCREL; break;
6203 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 6204#ifdef BFD64
6205 case 8: code = BFD_RELOC_64_PCREL; break;
6206#endif
93382f6d
AM		 6207 }
6208 }
6209 else
6210 {
6211 switch (fixp->fx_size)
6212 {
6213 default:
b091f402
AM		 6214 as_bad_where (fixp->fx_file, fixp->fx_line,
6215 _("can not do %d byte relocation"),
6216 fixp->fx_size);
93382f6d
AM		 6217 code = BFD_RELOC_32;
6218 break;
6219 case 1: code = BFD_RELOC_8; break;
6220 case 2: code = BFD_RELOC_16; break;
6221 case 4: code = BFD_RELOC_32; break;
937149dd 6222#ifdef BFD64
3e73aa7c 6223 case 8: code = BFD_RELOC_64; break;
937149dd 6224#endif
93382f6d 6225 }
252b5132
RH		 6226 }
6227 break;
6228 }
252b5132 6229
d182319b
JB		 6230 if ((code == BFD_RELOC_32
6231 || code == BFD_RELOC_32_PCREL
6232 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 6233 && GOT_symbol
6234 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 6235 {
4fa24527 6236 if (!object_64bit)
d6ab8113
JB		 6237 code = BFD_RELOC_386_GOTPC;
6238 else
6239 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 6240 }
7b81dfbb
AJ		 6241 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
6242 && GOT_symbol
6243 && fixp->fx_addsy == GOT_symbol)
6244 {
6245 code = BFD_RELOC_X86_64_GOTPC64;
6246 }
252b5132
RH		 6247
6248 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 6249 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
6250 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 6251
6252 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 6253
3e73aa7c
JH		 6254 if (!use_rela_relocations)
6255 {
6256 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
6257 vtable entry to be used in the relocation's section offset. */
6258 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
6259 rel->address = fixp->fx_offset;
252b5132 6260
c6682705 6261 rel->addend = 0;
3e73aa7c
JH		 6262 }
6263 /* Use the rela in 64bit mode. */
252b5132 6264 else
3e73aa7c 6265 {
062cd5e7
AS		 6266 if (!fixp->fx_pcrel)
6267 rel->addend = fixp->fx_offset;
6268 else
6269 switch (code)
6270 {
6271 case BFD_RELOC_X86_64_PLT32:
6272 case BFD_RELOC_X86_64_GOT32:
6273 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 6274 case BFD_RELOC_X86_64_TLSGD:
6275 case BFD_RELOC_X86_64_TLSLD:
6276 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6277 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6278 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6279 rel->addend = fixp->fx_offset - fixp->fx_size;
6280 break;
6281 default:
6282 rel->addend = (section->vma
6283 - fixp->fx_size
6284 + fixp->fx_addnumber
6285 + md_pcrel_from (fixp));
6286 break;
6287 }
3e73aa7c
JH		 6288 }
6289
252b5132
RH		 6290 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6291 if (rel->howto == NULL)
6292 {
6293 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6294 _("cannot represent relocation type %s"),
252b5132
RH		 6295 bfd_get_reloc_code_name (code));
6296 /* Set howto to a garbage value so that we can keep going. */
6297 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6298 assert (rel->howto != NULL);
6299 }
6300
6301 return rel;
6302}
6303
64a0c779
DN		 6304\f
6305/* Parse operands using Intel syntax. This implements a recursive descent
6306 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6307 Programmer's Guide.
6308
6309 FIXME: We do not recognize the full operand grammar defined in the MASM
6310 documentation. In particular, all the structure/union and
6311 high-level macro operands are missing.
6312
6313 Uppercase words are terminals, lower case words are non-terminals.
6314 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6315 bars '|' denote choices. Most grammar productions are implemented in
6316 functions called 'intel_<production>'.
6317
6318 Initial production is 'expr'.
6319
9306ca4a 6320 addOp + | -
64a0c779
DN		 6321
6322 alpha [a-zA-Z]
6323
9306ca4a
JB		 6324 binOp & | AND | \| | OR | ^ | XOR
6325
64a0c779
DN		 6326 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6327
6328 constant digits [[ radixOverride ]]
6329
9306ca4a 6330 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6331
6332 digits decdigit
b77a7acd
AJ		 6333 | digits decdigit
6334 | digits hexdigit
64a0c779
DN		 6335
6336 decdigit [0-9]
6337
9306ca4a
JB		 6338 e04 e04 addOp e05
6339 | e05
6340
6341 e05 e05 binOp e06
b77a7acd 6342 | e06
64a0c779
DN		 6343
6344 e06 e06 mulOp e09
b77a7acd 6345 | e09
64a0c779
DN		 6346
6347 e09 OFFSET e10
a724f0f4
JB		 6348 | SHORT e10
6349 | + e10
6350 | - e10
9306ca4a
JB		 6351 | ~ e10
6352 | NOT e10
64a0c779
DN		 6353 | e09 PTR e10
6354 | e09 : e10
6355 | e10
6356
6357 e10 e10 [ expr ]
b77a7acd 6358 | e11
64a0c779
DN		 6359
6360 e11 ( expr )
b77a7acd 6361 | [ expr ]
64a0c779
DN		 6362 | constant
6363 | dataType
6364 | id
6365 | $
6366 | register
6367
a724f0f4 6368 => expr expr cmpOp e04
9306ca4a 6369 | e04
64a0c779
DN		 6370
6371 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6372 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6373
6374 hexdigit a | b | c | d | e | f
b77a7acd 6375 | A | B | C | D | E | F
64a0c779
DN		 6376
6377 id alpha
b77a7acd 6378 | id alpha
64a0c779
DN		 6379 | id decdigit
6380
9306ca4a 6381 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6382
6383 quote " | '
6384
6385 register specialRegister
b77a7acd 6386 | gpRegister
64a0c779
DN		 6387 | byteRegister
6388
6389 segmentRegister CS | DS | ES | FS | GS | SS
6390
9306ca4a 6391 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6392 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6393 | TR3 | TR4 | TR5 | TR6 | TR7
6394
64a0c779
DN		 6395 We simplify the grammar in obvious places (e.g., register parsing is
6396 done by calling parse_register) and eliminate immediate left recursion
6397 to implement a recursive-descent parser.
6398
a724f0f4
JB		 6399 expr e04 expr'
6400
6401 expr' cmpOp e04 expr'
6402 | Empty
9306ca4a
JB		 6403
6404 e04 e05 e04'
6405
6406 e04' addOp e05 e04'
6407 | Empty
64a0c779
DN		 6408
6409 e05 e06 e05'
6410
9306ca4a 6411 e05' binOp e06 e05'
b77a7acd 6412 | Empty
64a0c779
DN		 6413
6414 e06 e09 e06'
6415
6416 e06' mulOp e09 e06'
b77a7acd 6417 | Empty
64a0c779
DN		 6418
6419 e09 OFFSET e10 e09'
a724f0f4
JB		 6420 | SHORT e10'
6421 | + e10'
6422 | - e10'
6423 | ~ e10'
6424 | NOT e10'
b77a7acd 6425 | e10 e09'
64a0c779
DN		 6426
6427 e09' PTR e10 e09'
b77a7acd 6428 | : e10 e09'
64a0c779
DN		 6429 | Empty
6430
6431 e10 e11 e10'
6432
6433 e10' [ expr ] e10'
b77a7acd 6434 | Empty
64a0c779
DN		 6435
6436 e11 ( expr )
b77a7acd 6437 | [ expr ]
64a0c779
DN		 6438 | BYTE
6439 | WORD
6440 | DWORD
9306ca4a 6441 | FWORD
64a0c779 6442 | QWORD
9306ca4a
JB		 6443 | TBYTE
6444 | OWORD
6445 | XMMWORD
64a0c779
DN		 6446 | .
6447 | $
6448 | register
6449 | id
6450 | constant */
6451
6452/* Parsing structure for the intel syntax parser. Used to implement the
6453 semantic actions for the operand grammar. */
6454struct intel_parser_s
6455 {
6456 char *op_string; /* The string being parsed. */
6457 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6458 int op_modifier; /* Operand modifier. */
64a0c779 6459 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6460 int in_offset; /* >=1 if parsing operand of offset. */
6461 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6462 const reg_entry *reg; /* Last register reference found. */
6463 char *disp; /* Displacement string being built. */
a724f0f4 6464 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6465 };
6466
6467static struct intel_parser_s intel_parser;
6468
6469/* Token structure for parsing intel syntax. */
6470struct intel_token
6471 {
6472 int code; /* Token code. */
6473 const reg_entry *reg; /* Register entry for register tokens. */
6474 char *str; /* String representation. */
6475 };
6476
6477static struct intel_token cur_token, prev_token;
6478
50705ef4
AM		 6479/* Token codes for the intel parser. Since T_SHORT is already used
6480 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6481#define T_NIL -1
6482#define T_CONST 1
6483#define T_REG 2
6484#define T_BYTE 3
6485#define T_WORD 4
9306ca4a
JB		 6486#define T_DWORD 5
6487#define T_FWORD 6
6488#define T_QWORD 7
6489#define T_TBYTE 8
6490#define T_XMMWORD 9
50705ef4 6491#undef T_SHORT
9306ca4a
JB		 6492#define T_SHORT 10
6493#define T_OFFSET 11
6494#define T_PTR 12
6495#define T_ID 13
6496#define T_SHL 14
6497#define T_SHR 15
64a0c779
DN		 6498
6499/* Prototypes for intel parser functions. */
6500static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6501static void intel_get_token PARAMS ((void));
6502static void intel_putback_token PARAMS ((void));
6503static int intel_expr PARAMS ((void));
9306ca4a 6504static int intel_e04 PARAMS ((void));
cce0cbdc 6505static int intel_e05 PARAMS ((void));
cce0cbdc 6506static int intel_e06 PARAMS ((void));
cce0cbdc 6507static int intel_e09 PARAMS ((void));
a724f0f4 6508static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6509static int intel_e10 PARAMS ((void));
cce0cbdc 6510static int intel_e11 PARAMS ((void));
64a0c779 6511
64a0c779
DN		 6512static int
6513i386_intel_operand (operand_string, got_a_float)
6514 char *operand_string;
6515 int got_a_float;
6516{
6517 int ret;
6518 char *p;
6519
a724f0f4
JB		 6520 p = intel_parser.op_string = xstrdup (operand_string);
6521 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6522
6523 for (;;)
64a0c779 6524 {
a724f0f4
JB		 6525 /* Initialize token holders. */
6526 cur_token.code = prev_token.code = T_NIL;
6527 cur_token.reg = prev_token.reg = NULL;
6528 cur_token.str = prev_token.str = NULL;
6529
6530 /* Initialize parser structure. */
6531 intel_parser.got_a_float = got_a_float;
6532 intel_parser.op_modifier = 0;
6533 intel_parser.is_mem = 0;
6534 intel_parser.in_offset = 0;
6535 intel_parser.in_bracket = 0;
6536 intel_parser.reg = NULL;
6537 intel_parser.disp[0] = '\0';
6538 intel_parser.next_operand = NULL;
6539
6540 /* Read the first token and start the parser. */
6541 intel_get_token ();
6542 ret = intel_expr ();
6543
6544 if (!ret)
6545 break;
6546
9306ca4a
JB		 6547 if (cur_token.code != T_NIL)
6548 {
6549 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6550 current_templates->start->name, cur_token.str);
6551 ret = 0;
6552 }
64a0c779
DN		 6553 /* If we found a memory reference, hand it over to i386_displacement
6554 to fill in the rest of the operand fields. */
9306ca4a 6555 else if (intel_parser.is_mem)
64a0c779
DN		 6556 {
6557 if ((i.mem_operands == 1
6558 && (current_templates->start->opcode_modifier & IsString) == 0)
6559 || i.mem_operands == 2)
6560 {
6561 as_bad (_("too many memory references for '%s'"),
6562 current_templates->start->name);
6563 ret = 0;
6564 }
6565 else
6566 {
6567 char *s = intel_parser.disp;
6568 i.mem_operands++;
6569
a724f0f4
JB		 6570 if (!quiet_warnings && intel_parser.is_mem < 0)
6571 /* See the comments in intel_bracket_expr. */
6572 as_warn (_("Treating `%s' as memory reference"), operand_string);
6573
64a0c779
DN		 6574 /* Add the displacement expression. */
6575 if (*s != '\0')
a4622f40
AM		 6576 ret = i386_displacement (s, s + strlen (s));
6577 if (ret)
a724f0f4
JB		 6578 {
6579 /* Swap base and index in 16-bit memory operands like
6580 [si+bx]. Since i386_index_check is also used in AT&T
6581 mode we have to do that here. */
6582 if (i.base_reg
6583 && i.index_reg
6584 && (i.base_reg->reg_type & Reg16)
6585 && (i.index_reg->reg_type & Reg16)
6586 && i.base_reg->reg_num >= 6
6587 && i.index_reg->reg_num < 6)
6588 {
6589 const reg_entry *base = i.index_reg;
6590
6591 i.index_reg = i.base_reg;
6592 i.base_reg = base;
6593 }
6594 ret = i386_index_check (operand_string);
6595 }
64a0c779
DN		 6596 }
6597 }
6598
6599 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6600 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6601 || intel_parser.reg == NULL)
6602 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6603
6604 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6605 ret = 0;
6606 if (!ret || !intel_parser.next_operand)
6607 break;
6608 intel_parser.op_string = intel_parser.next_operand;
6609 this_operand = i.operands++;
64a0c779
DN		 6610 }
6611
6612 free (p);
6613 free (intel_parser.disp);
6614
6615 return ret;
6616}
6617
a724f0f4
JB		 6618#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6619
6620/* expr e04 expr'
6621
6622 expr' cmpOp e04 expr'
6623 | Empty */
64a0c779
DN		 6624static int
6625intel_expr ()
6626{
a724f0f4
JB		 6627 /* XXX Implement the comparison operators. */
6628 return intel_e04 ();
9306ca4a
JB		 6629}
6630
a724f0f4 6631/* e04 e05 e04'
9306ca4a 6632
a724f0f4 6633 e04' addOp e05 e04'
9306ca4a
JB		 6634 | Empty */
6635static int
6636intel_e04 ()
6637{
a724f0f4 6638 int nregs = -1;
9306ca4a 6639
a724f0f4 6640 for (;;)
9306ca4a 6641 {
a724f0f4
JB		 6642 if (!intel_e05())
6643 return 0;
9306ca4a 6644
a724f0f4
JB		 6645 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6646 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6647
a724f0f4
JB		 6648 if (cur_token.code == '+')
6649 nregs = -1;
6650 else if (cur_token.code == '-')
6651 nregs = NUM_ADDRESS_REGS;
6652 else
6653 return 1;
64a0c779 6654
a724f0f4
JB		 6655 strcat (intel_parser.disp, cur_token.str);
6656 intel_match_token (cur_token.code);
6657 }
64a0c779
DN		 6658}
6659
64a0c779
DN		 6660/* e05 e06 e05'
6661
9306ca4a 6662 e05' binOp e06 e05'
64a0c779
DN		 6663 | Empty */
6664static int
6665intel_e05 ()
6666{
a724f0f4 6667 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6668
a724f0f4 6669 for (;;)
64a0c779 6670 {
a724f0f4
JB		 6671 if (!intel_e06())
6672 return 0;
6673
6674 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6675 {
6676 char str[2];
6677
6678 str[0] = cur_token.code;
6679 str[1] = 0;
6680 strcat (intel_parser.disp, str);
6681 }
6682 else
6683 break;
9306ca4a 6684
64a0c779
DN		 6685 intel_match_token (cur_token.code);
6686
a724f0f4
JB		 6687 if (nregs < 0)
6688 nregs = ~nregs;
64a0c779 6689 }
a724f0f4
JB		 6690 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6691 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6692 return 1;
4a1805b1 6693}
64a0c779
DN		 6694
6695/* e06 e09 e06'
6696
6697 e06' mulOp e09 e06'
b77a7acd 6698 | Empty */
64a0c779
DN		 6699static int
6700intel_e06 ()
6701{
a724f0f4 6702 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6703
a724f0f4 6704 for (;;)
64a0c779 6705 {
a724f0f4
JB		 6706 if (!intel_e09())
6707 return 0;
9306ca4a 6708
a724f0f4
JB		 6709 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6710 {
6711 char str[2];
9306ca4a 6712
a724f0f4
JB		 6713 str[0] = cur_token.code;
6714 str[1] = 0;
6715 strcat (intel_parser.disp, str);
6716 }
6717 else if (cur_token.code == T_SHL)
6718 strcat (intel_parser.disp, "<<");
6719 else if (cur_token.code == T_SHR)
6720 strcat (intel_parser.disp, ">>");
6721 else
6722 break;
9306ca4a 6723
64e74474 6724 intel_match_token (cur_token.code);
64a0c779 6725
a724f0f4
JB		 6726 if (nregs < 0)
6727 nregs = ~nregs;
64a0c779 6728 }
a724f0f4
JB		 6729 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6730 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6731 return 1;
64a0c779
DN		 6732}
6733
a724f0f4
JB		 6734/* e09 OFFSET e09
6735 | SHORT e09
6736 | + e09
6737 | - e09
6738 | ~ e09
6739 | NOT e09
9306ca4a
JB		 6740 | e10 e09'
6741
64a0c779 6742 e09' PTR e10 e09'
b77a7acd 6743 | : e10 e09'
64a0c779
DN		 6744 | Empty */
6745static int
6746intel_e09 ()
6747{
a724f0f4
JB		 6748 int nregs = ~NUM_ADDRESS_REGS;
6749 int in_offset = 0;
6750
6751 for (;;)
64a0c779 6752 {
a724f0f4
JB		 6753 /* Don't consume constants here. */
6754 if (cur_token.code == '+' || cur_token.code == '-')
6755 {
6756 /* Need to look one token ahead - if the next token
6757 is a constant, the current token is its sign. */
6758 int next_code;
6759
6760 intel_match_token (cur_token.code);
6761 next_code = cur_token.code;
6762 intel_putback_token ();
6763 if (next_code == T_CONST)
6764 break;
6765 }
6766
6767 /* e09 OFFSET e09 */
6768 if (cur_token.code == T_OFFSET)
6769 {
6770 if (!in_offset++)
6771 ++intel_parser.in_offset;
6772 }
6773
6774 /* e09 SHORT e09 */
6775 else if (cur_token.code == T_SHORT)
6776 intel_parser.op_modifier |= 1 << T_SHORT;
6777
6778 /* e09 + e09 */
6779 else if (cur_token.code == '+')
6780 strcat (intel_parser.disp, "+");
6781
6782 /* e09 - e09
6783 | ~ e09
6784 | NOT e09 */
6785 else if (cur_token.code == '-' || cur_token.code == '~')
6786 {
6787 char str[2];
64a0c779 6788
a724f0f4
JB		 6789 if (nregs < 0)
6790 nregs = ~nregs;
6791 str[0] = cur_token.code;
6792 str[1] = 0;
6793 strcat (intel_parser.disp, str);
6794 }
6795
6796 /* e09 e10 e09' */
6797 else
6798 break;
6799
6800 intel_match_token (cur_token.code);
64a0c779
DN		 6801 }
6802
a724f0f4 6803 for (;;)
9306ca4a 6804 {
a724f0f4
JB		 6805 if (!intel_e10 ())
6806 return 0;
9306ca4a 6807
a724f0f4
JB		 6808 /* e09' PTR e10 e09' */
6809 if (cur_token.code == T_PTR)
6810 {
6811 char suffix;
9306ca4a 6812
a724f0f4
JB		 6813 if (prev_token.code == T_BYTE)
6814 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6815
a724f0f4
JB		 6816 else if (prev_token.code == T_WORD)
6817 {
6818 if (current_templates->start->name[0] == 'l'
6819 && current_templates->start->name[2] == 's'
6820 && current_templates->start->name[3] == 0)
6821 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6822 else if (intel_parser.got_a_float == 2) /* "fi..." */
6823 suffix = SHORT_MNEM_SUFFIX;
6824 else
6825 suffix = WORD_MNEM_SUFFIX;
6826 }
64a0c779 6827
a724f0f4
JB		 6828 else if (prev_token.code == T_DWORD)
6829 {
6830 if (current_templates->start->name[0] == 'l'
6831 && current_templates->start->name[2] == 's'
6832 && current_templates->start->name[3] == 0)
6833 suffix = WORD_MNEM_SUFFIX;
6834 else if (flag_code == CODE_16BIT
6835 && (current_templates->start->opcode_modifier
435acd52 6836 & (Jump | JumpDword)))
a724f0f4
JB		 6837 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6838 else if (intel_parser.got_a_float == 1) /* "f..." */
6839 suffix = SHORT_MNEM_SUFFIX;
6840 else
6841 suffix = LONG_MNEM_SUFFIX;
6842 }
9306ca4a 6843
a724f0f4
JB		 6844 else if (prev_token.code == T_FWORD)
6845 {
6846 if (current_templates->start->name[0] == 'l'
6847 && current_templates->start->name[2] == 's'
6848 && current_templates->start->name[3] == 0)
6849 suffix = LONG_MNEM_SUFFIX;
6850 else if (!intel_parser.got_a_float)
6851 {
6852 if (flag_code == CODE_16BIT)
6853 add_prefix (DATA_PREFIX_OPCODE);
6854 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6855 }
6856 else
6857 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6858 }
64a0c779 6859
a724f0f4
JB		 6860 else if (prev_token.code == T_QWORD)
6861 {
6862 if (intel_parser.got_a_float == 1) /* "f..." */
6863 suffix = LONG_MNEM_SUFFIX;
6864 else
6865 suffix = QWORD_MNEM_SUFFIX;
6866 }
64a0c779 6867
a724f0f4
JB		 6868 else if (prev_token.code == T_TBYTE)
6869 {
6870 if (intel_parser.got_a_float == 1)
6871 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6872 else
6873 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6874 }
9306ca4a 6875
a724f0f4 6876 else if (prev_token.code == T_XMMWORD)
9306ca4a 6877 {
a724f0f4
JB		 6878 /* XXX ignored for now, but accepted since gcc uses it */
6879 suffix = 0;
9306ca4a 6880 }
64a0c779 6881
f16b83df 6882 else
a724f0f4
JB		 6883 {
6884 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6885 return 0;
6886 }
6887
435acd52
JB		 6888 /* Operands for jump/call using 'ptr' notation denote absolute
6889 addresses. */
6890 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6891 i.types[this_operand] |= JumpAbsolute;
6892
a724f0f4
JB		 6893 if (current_templates->start->base_opcode == 0x8d /* lea */)
6894 ;
6895 else if (!i.suffix)
6896 i.suffix = suffix;
6897 else if (i.suffix != suffix)
6898 {
6899 as_bad (_("Conflicting operand modifiers"));
6900 return 0;
6901 }
64a0c779 6902
9306ca4a
JB		 6903 }
6904
a724f0f4
JB		 6905 /* e09' : e10 e09' */
6906 else if (cur_token.code == ':')
9306ca4a 6907 {
a724f0f4
JB		 6908 if (prev_token.code != T_REG)
6909 {
6910 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6911 segment/group identifier (which we don't have), using comma
6912 as the operand separator there is even less consistent, since
6913 there all branches only have a single operand. */
6914 if (this_operand != 0
6915 || intel_parser.in_offset
6916 || intel_parser.in_bracket
6917 || (!(current_templates->start->opcode_modifier
6918 & (Jump|JumpDword|JumpInterSegment))
6919 && !(current_templates->start->operand_types[0]
6920 & JumpAbsolute)))
6921 return intel_match_token (T_NIL);
6922 /* Remember the start of the 2nd operand and terminate 1st
6923 operand here.
6924 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6925 another expression), but it gets at least the simplest case
6926 (a plain number or symbol on the left side) right. */
6927 intel_parser.next_operand = intel_parser.op_string;
6928 *--intel_parser.op_string = '\0';
6929 return intel_match_token (':');
6930 }
9306ca4a 6931 }
64a0c779 6932
a724f0f4 6933 /* e09' Empty */
64a0c779 6934 else
a724f0f4 6935 break;
64a0c779 6936
a724f0f4
JB		 6937 intel_match_token (cur_token.code);
6938
6939 }
6940
6941 if (in_offset)
6942 {
6943 --intel_parser.in_offset;
6944 if (nregs < 0)
6945 nregs = ~nregs;
6946 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6947 {
a724f0f4 6948 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6949 return 0;
6950 }
a724f0f4
JB		 6951 intel_parser.op_modifier |= 1 << T_OFFSET;
6952 }
9306ca4a 6953
a724f0f4
JB		 6954 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6955 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6956 return 1;
6957}
64a0c779 6958
a724f0f4
JB		 6959static int
6960intel_bracket_expr ()
6961{
6962 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6963 const char *start = intel_parser.op_string;
6964 int len;
6965
6966 if (i.op[this_operand].regs)
6967 return intel_match_token (T_NIL);
6968
6969 intel_match_token ('[');
6970
6971 /* Mark as a memory operand only if it's not already known to be an
6972 offset expression. If it's an offset expression, we need to keep
6973 the brace in. */
6974 if (!intel_parser.in_offset)
6975 {
6976 ++intel_parser.in_bracket;
435acd52
JB		 6977
6978 /* Operands for jump/call inside brackets denote absolute addresses. */
6979 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6980 i.types[this_operand] |= JumpAbsolute;
6981
a724f0f4
JB		 6982 /* Unfortunately gas always diverged from MASM in a respect that can't
6983 be easily fixed without risking to break code sequences likely to be
6984 encountered (the testsuite even check for this): MASM doesn't consider
6985 an expression inside brackets unconditionally as a memory reference.
6986 When that is e.g. a constant, an offset expression, or the sum of the
6987 two, this is still taken as a constant load. gas, however, always
6988 treated these as memory references. As a compromise, we'll try to make
6989 offset expressions inside brackets work the MASM way (since that's
6990 less likely to be found in real world code), but make constants alone
6991 continue to work the traditional gas way. In either case, issue a
6992 warning. */
6993 intel_parser.op_modifier &= ~was_offset;
64a0c779 6994 }
a724f0f4 6995 else
64e74474 6996 strcat (intel_parser.disp, "[");
a724f0f4
JB		 6997
6998 /* Add a '+' to the displacement string if necessary. */
6999 if (*intel_parser.disp != '\0'
7000 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
7001 strcat (intel_parser.disp, "+");
64a0c779 7002
a724f0f4
JB		 7003 if (intel_expr ()
7004 && (len = intel_parser.op_string - start - 1,
7005 intel_match_token (']')))
64a0c779 7006 {
a724f0f4
JB		 7007 /* Preserve brackets when the operand is an offset expression. */
7008 if (intel_parser.in_offset)
7009 strcat (intel_parser.disp, "]");
7010 else
7011 {
7012 --intel_parser.in_bracket;
7013 if (i.base_reg || i.index_reg)
7014 intel_parser.is_mem = 1;
7015 if (!intel_parser.is_mem)
7016 {
7017 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
7018 /* Defer the warning until all of the operand was parsed. */
7019 intel_parser.is_mem = -1;
7020 else if (!quiet_warnings)
7021 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
7022 }
7023 }
7024 intel_parser.op_modifier |= was_offset;
64a0c779 7025
a724f0f4 7026 return 1;
64a0c779 7027 }
a724f0f4 7028 return 0;
64a0c779
DN		 7029}
7030
7031/* e10 e11 e10'
7032
7033 e10' [ expr ] e10'
b77a7acd 7034 | Empty */
64a0c779
DN		 7035static int
7036intel_e10 ()
7037{
a724f0f4
JB		 7038 if (!intel_e11 ())
7039 return 0;
64a0c779 7040
a724f0f4 7041 while (cur_token.code == '[')
64a0c779 7042 {
a724f0f4 7043 if (!intel_bracket_expr ())
21d6c4af 7044 return 0;
64a0c779
DN		 7045 }
7046
a724f0f4 7047 return 1;
64a0c779
DN		 7048}
7049
64a0c779 7050/* e11 ( expr )
b77a7acd 7051 | [ expr ]
64a0c779
DN		 7052 | BYTE
7053 | WORD
7054 | DWORD
9306ca4a 7055 | FWORD
64a0c779 7056 | QWORD
9306ca4a
JB		 7057 | TBYTE
7058 | OWORD
7059 | XMMWORD
4a1805b1 7060 | $
64a0c779
DN		 7061 | .
7062 | register
7063 | id
7064 | constant */
7065static int
7066intel_e11 ()
7067{
a724f0f4 7068 switch (cur_token.code)
64a0c779 7069 {
a724f0f4
JB		 7070 /* e11 ( expr ) */
7071 case '(':
64a0c779
DN		 7072 intel_match_token ('(');
7073 strcat (intel_parser.disp, "(");
7074
7075 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 7076 {
7077 strcat (intel_parser.disp, ")");
7078 return 1;
7079 }
a724f0f4 7080 return 0;
4a1805b1 7081
a724f0f4
JB		 7082 /* e11 [ expr ] */
7083 case '[':
a724f0f4 7084 return intel_bracket_expr ();
64a0c779 7085
a724f0f4
JB		 7086 /* e11 $
7087 | . */
7088 case '.':
64a0c779
DN		 7089 strcat (intel_parser.disp, cur_token.str);
7090 intel_match_token (cur_token.code);
21d6c4af
DN		 7091
7092 /* Mark as a memory operand only if it's not already known to be an
7093 offset expression. */
a724f0f4 7094 if (!intel_parser.in_offset)
21d6c4af 7095 intel_parser.is_mem = 1;
64a0c779
DN		 7096
7097 return 1;
64a0c779 7098
a724f0f4
JB		 7099 /* e11 register */
7100 case T_REG:
7101 {
7102 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 7103
a724f0f4 7104 intel_match_token (T_REG);
64a0c779 7105
a724f0f4
JB		 7106 /* Check for segment change. */
7107 if (cur_token.code == ':')
7108 {
7109 if (!(reg->reg_type & (SReg2 | SReg3)))
7110 {
7111 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
7112 return 0;
7113 }
7114 else if (i.seg[i.mem_operands])
7115 as_warn (_("Extra segment override ignored"));
7116 else
7117 {
7118 if (!intel_parser.in_offset)
7119 intel_parser.is_mem = 1;
7120 switch (reg->reg_num)
7121 {
7122 case 0:
7123 i.seg[i.mem_operands] = &es;
7124 break;
7125 case 1:
7126 i.seg[i.mem_operands] = &cs;
7127 break;
7128 case 2:
7129 i.seg[i.mem_operands] = &ss;
7130 break;
7131 case 3:
7132 i.seg[i.mem_operands] = &ds;
7133 break;
7134 case 4:
7135 i.seg[i.mem_operands] = &fs;
7136 break;
7137 case 5:
7138 i.seg[i.mem_operands] = &gs;
7139 break;
7140 }
7141 }
7142 }
64a0c779 7143
a724f0f4
JB		 7144 /* Not a segment register. Check for register scaling. */
7145 else if (cur_token.code == '*')
7146 {
7147 if (!intel_parser.in_bracket)
7148 {
7149 as_bad (_("Register scaling only allowed in memory operands"));
7150 return 0;
7151 }
64a0c779 7152
a724f0f4
JB		 7153 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
7154 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7155 else if (i.index_reg)
7156 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 7157
a724f0f4
JB		 7158 /* What follows must be a valid scale. */
7159 intel_match_token ('*');
7160 i.index_reg = reg;
7161 i.types[this_operand] |= BaseIndex;
64a0c779 7162
a724f0f4
JB		 7163 /* Set the scale after setting the register (otherwise,
7164 i386_scale will complain) */
7165 if (cur_token.code == '+' || cur_token.code == '-')
7166 {
7167 char *str, sign = cur_token.code;
7168 intel_match_token (cur_token.code);
7169 if (cur_token.code != T_CONST)
7170 {
7171 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7172 cur_token.str);
7173 return 0;
7174 }
7175 str = (char *) xmalloc (strlen (cur_token.str) + 2);
7176 strcpy (str + 1, cur_token.str);
7177 *str = sign;
7178 if (!i386_scale (str))
7179 return 0;
7180 free (str);
7181 }
7182 else if (!i386_scale (cur_token.str))
64a0c779 7183 return 0;
a724f0f4
JB		 7184 intel_match_token (cur_token.code);
7185 }
64a0c779 7186
a724f0f4
JB		 7187 /* No scaling. If this is a memory operand, the register is either a
7188 base register (first occurrence) or an index register (second
7189 occurrence). */
7b0441f6 7190 else if (intel_parser.in_bracket)
a724f0f4 7191 {
64a0c779 7192
a724f0f4
JB		 7193 if (!i.base_reg)
7194 i.base_reg = reg;
7195 else if (!i.index_reg)
7196 i.index_reg = reg;
7197 else
7198 {
7199 as_bad (_("Too many register references in memory operand"));
7200 return 0;
7201 }
64a0c779 7202
a724f0f4
JB		 7203 i.types[this_operand] |= BaseIndex;
7204 }
4a1805b1 7205
4d1bb795
JB		 7206 /* It's neither base nor index. */
7207 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 7208 {
7209 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
7210 i.op[this_operand].regs = reg;
7211 i.reg_operands++;
7212 }
7213 else
7214 {
7215 as_bad (_("Invalid use of register"));
7216 return 0;
7217 }
64a0c779 7218
a724f0f4
JB		 7219 /* Since registers are not part of the displacement string (except
7220 when we're parsing offset operands), we may need to remove any
7221 preceding '+' from the displacement string. */
7222 if (*intel_parser.disp != '\0'
7223 && !intel_parser.in_offset)
7224 {
7225 char *s = intel_parser.disp;
7226 s += strlen (s) - 1;
7227 if (*s == '+')
7228 *s = '\0';
7229 }
4a1805b1 7230
a724f0f4
JB		 7231 return 1;
7232 }
7233
7234 /* e11 BYTE
7235 | WORD
7236 | DWORD
7237 | FWORD
7238 | QWORD
7239 | TBYTE
7240 | OWORD
7241 | XMMWORD */
7242 case T_BYTE:
7243 case T_WORD:
7244 case T_DWORD:
7245 case T_FWORD:
7246 case T_QWORD:
7247 case T_TBYTE:
7248 case T_XMMWORD:
7249 intel_match_token (cur_token.code);
64a0c779 7250
a724f0f4
JB		 7251 if (cur_token.code == T_PTR)
7252 return 1;
7253
7254 /* It must have been an identifier. */
7255 intel_putback_token ();
7256 cur_token.code = T_ID;
7257 /* FALLTHRU */
7258
7259 /* e11 id
7260 | constant */
7261 case T_ID:
7262 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 7263 {
7264 symbolS *symbolP;
7265
a724f0f4
JB		 7266 /* The identifier represents a memory reference only if it's not
7267 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 7268 symbolP = symbol_find(cur_token.str);
7269 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
7270 intel_parser.is_mem = 1;
7271 }
a724f0f4 7272 /* FALLTHRU */
64a0c779 7273
a724f0f4
JB		 7274 case T_CONST:
7275 case '-':
7276 case '+':
7277 {
7278 char *save_str, sign = 0;
64a0c779 7279
a724f0f4
JB		 7280 /* Allow constants that start with `+' or `-'. */
7281 if (cur_token.code == '-' || cur_token.code == '+')
7282 {
7283 sign = cur_token.code;
7284 intel_match_token (cur_token.code);
7285 if (cur_token.code != T_CONST)
7286 {
7287 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7288 cur_token.str);
7289 return 0;
7290 }
7291 }
64a0c779 7292
a724f0f4
JB		 7293 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7294 strcpy (save_str + !!sign, cur_token.str);
7295 if (sign)
7296 *save_str = sign;
64a0c779 7297
a724f0f4
JB		 7298 /* Get the next token to check for register scaling. */
7299 intel_match_token (cur_token.code);
64a0c779 7300
a724f0f4
JB		 7301 /* Check if this constant is a scaling factor for an index register. */
7302 if (cur_token.code == '*')
7303 {
7304 if (intel_match_token ('*') && cur_token.code == T_REG)
7305 {
7306 const reg_entry *reg = cur_token.reg;
7307
7308 if (!intel_parser.in_bracket)
7309 {
7310 as_bad (_("Register scaling only allowed in memory operands"));
7311 return 0;
7312 }
7313
7314 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7315 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7316 else if (i.index_reg)
7317 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7318
7319 /* The constant is followed by `* reg', so it must be
7320 a valid scale. */
7321 i.index_reg = reg;
7322 i.types[this_operand] |= BaseIndex;
7323
7324 /* Set the scale after setting the register (otherwise,
7325 i386_scale will complain) */
7326 if (!i386_scale (save_str))
64a0c779 7327 return 0;
a724f0f4
JB		 7328 intel_match_token (T_REG);
7329
7330 /* Since registers are not part of the displacement
7331 string, we may need to remove any preceding '+' from
7332 the displacement string. */
7333 if (*intel_parser.disp != '\0')
7334 {
7335 char *s = intel_parser.disp;
7336 s += strlen (s) - 1;
7337 if (*s == '+')
7338 *s = '\0';
7339 }
7340
7341 free (save_str);
7342
7343 return 1;
7344 }
64a0c779 7345
a724f0f4
JB		 7346 /* The constant was not used for register scaling. Since we have
7347 already consumed the token following `*' we now need to put it
7348 back in the stream. */
64a0c779 7349 intel_putback_token ();
a724f0f4 7350 }
64a0c779 7351
a724f0f4
JB		 7352 /* Add the constant to the displacement string. */
7353 strcat (intel_parser.disp, save_str);
7354 free (save_str);
64a0c779 7355
a724f0f4
JB		 7356 return 1;
7357 }
64a0c779
DN		 7358 }
7359
64a0c779
DN		 7360 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7361 return 0;
7362}
7363
64a0c779
DN		 7364/* Match the given token against cur_token. If they match, read the next
7365 token from the operand string. */
7366static int
7367intel_match_token (code)
e5cb08ac 7368 int code;
64a0c779
DN		 7369{
7370 if (cur_token.code == code)
7371 {
7372 intel_get_token ();
7373 return 1;
7374 }
7375 else
7376 {
0477af35 7377 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7378 return 0;
7379 }
7380}
7381
64a0c779
DN		 7382/* Read a new token from intel_parser.op_string and store it in cur_token. */
7383static void
7384intel_get_token ()
7385{
7386 char *end_op;
7387 const reg_entry *reg;
7388 struct intel_token new_token;
7389
7390 new_token.code = T_NIL;
7391 new_token.reg = NULL;
7392 new_token.str = NULL;
7393
4a1805b1 7394 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7395 cur_token to prev_token. */
7396 if (prev_token.str)
7397 free (prev_token.str);
7398
7399 prev_token = cur_token;
7400
7401 /* Skip whitespace. */
7402 while (is_space_char (*intel_parser.op_string))
7403 intel_parser.op_string++;
7404
7405 /* Return an empty token if we find nothing else on the line. */
7406 if (*intel_parser.op_string == '\0')
7407 {
7408 cur_token = new_token;
7409 return;
7410 }
7411
7412 /* The new token cannot be larger than the remainder of the operand
7413 string. */
a724f0f4 7414 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7415 new_token.str[0] = '\0';
7416
7417 if (strchr ("0123456789", *intel_parser.op_string))
7418 {
7419 char *p = new_token.str;
7420 char *q = intel_parser.op_string;
7421 new_token.code = T_CONST;
7422
7423 /* Allow any kind of identifier char to encompass floating point and
7424 hexadecimal numbers. */
7425 while (is_identifier_char (*q))
7426 *p++ = *q++;
7427 *p = '\0';
7428
7429 /* Recognize special symbol names [0-9][bf]. */
7430 if (strlen (intel_parser.op_string) == 2
4a1805b1 7431 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7432 || intel_parser.op_string[1] == 'f'))
7433 new_token.code = T_ID;
7434 }
7435
4d1bb795 7436 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7437 {
4d1bb795
JB		 7438 size_t len = end_op - intel_parser.op_string;
7439
64a0c779
DN		 7440 new_token.code = T_REG;
7441 new_token.reg = reg;
7442
4d1bb795
JB		 7443 memcpy (new_token.str, intel_parser.op_string, len);
7444 new_token.str[len] = '\0';
64a0c779
DN		 7445 }
7446
7447 else if (is_identifier_char (*intel_parser.op_string))
7448 {
7449 char *p = new_token.str;
7450 char *q = intel_parser.op_string;
7451
7452 /* A '.' or '$' followed by an identifier char is an identifier.
7453 Otherwise, it's operator '.' followed by an expression. */
7454 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7455 {
9306ca4a
JB		 7456 new_token.code = '.';
7457 new_token.str[0] = '.';
64a0c779
DN		 7458 new_token.str[1] = '\0';
7459 }
7460 else
7461 {
7462 while (is_identifier_char (*q) || *q == '@')
7463 *p++ = *q++;
7464 *p = '\0';
7465
9306ca4a
JB		 7466 if (strcasecmp (new_token.str, "NOT") == 0)
7467 new_token.code = '~';
7468
7469 else if (strcasecmp (new_token.str, "MOD") == 0)
7470 new_token.code = '%';
7471
7472 else if (strcasecmp (new_token.str, "AND") == 0)
7473 new_token.code = '&';
7474
7475 else if (strcasecmp (new_token.str, "OR") == 0)
7476 new_token.code = '|';
7477
7478 else if (strcasecmp (new_token.str, "XOR") == 0)
7479 new_token.code = '^';
7480
7481 else if (strcasecmp (new_token.str, "SHL") == 0)
7482 new_token.code = T_SHL;
7483
7484 else if (strcasecmp (new_token.str, "SHR") == 0)
7485 new_token.code = T_SHR;
7486
7487 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7488 new_token.code = T_BYTE;
7489
7490 else if (strcasecmp (new_token.str, "WORD") == 0)
7491 new_token.code = T_WORD;
7492
7493 else if (strcasecmp (new_token.str, "DWORD") == 0)
7494 new_token.code = T_DWORD;
7495
9306ca4a
JB		 7496 else if (strcasecmp (new_token.str, "FWORD") == 0)
7497 new_token.code = T_FWORD;
7498
64a0c779
DN		 7499 else if (strcasecmp (new_token.str, "QWORD") == 0)
7500 new_token.code = T_QWORD;
7501
9306ca4a
JB		 7502 else if (strcasecmp (new_token.str, "TBYTE") == 0
7503 /* XXX remove (gcc still uses it) */
7504 || strcasecmp (new_token.str, "XWORD") == 0)
7505 new_token.code = T_TBYTE;
7506
7507 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7508 || strcasecmp (new_token.str, "OWORD") == 0)
7509 new_token.code = T_XMMWORD;
64a0c779
DN		 7510
7511 else if (strcasecmp (new_token.str, "PTR") == 0)
7512 new_token.code = T_PTR;
7513
7514 else if (strcasecmp (new_token.str, "SHORT") == 0)
7515 new_token.code = T_SHORT;
7516
7517 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7518 {
7519 new_token.code = T_OFFSET;
7520
7521 /* ??? This is not mentioned in the MASM grammar but gcc
7522 makes use of it with -mintel-syntax. OFFSET may be
7523 followed by FLAT: */
7524 if (strncasecmp (q, " FLAT:", 6) == 0)
7525 strcat (new_token.str, " FLAT:");
7526 }
7527
7528 /* ??? This is not mentioned in the MASM grammar. */
7529 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7530 {
7531 new_token.code = T_OFFSET;
7532 if (*q == ':')
7533 strcat (new_token.str, ":");
7534 else
7535 as_bad (_("`:' expected"));
7536 }
64a0c779
DN		 7537
7538 else
7539 new_token.code = T_ID;
7540 }
7541 }
7542
9306ca4a
JB		 7543 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7544 {
7545 new_token.code = *intel_parser.op_string;
7546 new_token.str[0] = *intel_parser.op_string;
7547 new_token.str[1] = '\0';
7548 }
7549
7550 else if (strchr ("<>", *intel_parser.op_string)
7551 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7552 {
7553 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7554 new_token.str[0] = *intel_parser.op_string;
7555 new_token.str[1] = *intel_parser.op_string;
7556 new_token.str[2] = '\0';
7557 }
7558
64a0c779 7559 else
0477af35 7560 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7561
7562 intel_parser.op_string += strlen (new_token.str);
7563 cur_token = new_token;
7564}
7565
64a0c779
DN		 7566/* Put cur_token back into the token stream and make cur_token point to
7567 prev_token. */
7568static void
7569intel_putback_token ()
7570{
a724f0f4
JB		 7571 if (cur_token.code != T_NIL)
7572 {
7573 intel_parser.op_string -= strlen (cur_token.str);
7574 free (cur_token.str);
7575 }
64a0c779 7576 cur_token = prev_token;
4a1805b1 7577
64a0c779
DN		 7578 /* Forget prev_token. */
7579 prev_token.code = T_NIL;
7580 prev_token.reg = NULL;
7581 prev_token.str = NULL;
7582}
54cfded0 7583
a4447b93 7584int
1df69f4f 7585tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7586{
7587 unsigned int regnum;
7588 unsigned int regnames_count;
089dfecd 7589 static const char *const regnames_32[] =
54cfded0 7590 {
a4447b93
RH		 7591 "eax", "ecx", "edx", "ebx",
7592 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7593 "eip", "eflags", NULL,
7594 "st0", "st1", "st2", "st3",
7595 "st4", "st5", "st6", "st7",
7596 NULL, NULL,
7597 "xmm0", "xmm1", "xmm2", "xmm3",
7598 "xmm4", "xmm5", "xmm6", "xmm7",
7599 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7600 "mm4", "mm5", "mm6", "mm7",
7601 "fcw", "fsw", "mxcsr",
7602 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7603 "tr", "ldtr"
54cfded0 7604 };
089dfecd 7605 static const char *const regnames_64[] =
54cfded0 7606 {
089dfecd
JB		 7607 "rax", "rdx", "rcx", "rbx",
7608 "rsi", "rdi", "rbp", "rsp",
7609 "r8", "r9", "r10", "r11",
54cfded0 7610 "r12", "r13", "r14", "r15",
089dfecd
JB		 7611 "rip",
7612 "xmm0", "xmm1", "xmm2", "xmm3",
7613 "xmm4", "xmm5", "xmm6", "xmm7",
7614 "xmm8", "xmm9", "xmm10", "xmm11",
7615 "xmm12", "xmm13", "xmm14", "xmm15",
7616 "st0", "st1", "st2", "st3",
7617 "st4", "st5", "st6", "st7",
7618 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7619 "mm4", "mm5", "mm6", "mm7",
7620 "rflags",
7621 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7622 "fs.base", "gs.base", NULL, NULL,
7623 "tr", "ldtr",
7624 "mxcsr", "fcw", "fsw"
54cfded0 7625 };
089dfecd 7626 const char *const *regnames;
54cfded0
AM		 7627
7628 if (flag_code == CODE_64BIT)
7629 {
7630 regnames = regnames_64;
0cea6190 7631 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7632 }
7633 else
7634 {
7635 regnames = regnames_32;
0cea6190 7636 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7637 }
7638
7639 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7640 if (regnames[regnum] != NULL
7641 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7642 return regnum;
7643
54cfded0
AM		 7644 return -1;
7645}
7646
7647void
7648tc_x86_frame_initial_instructions (void)
7649{
a4447b93
RH		 7650 static unsigned int sp_regno;
7651
7652 if (!sp_regno)
7653 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7654 ? "rsp" : "esp");
7655
7656 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7657 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7658}
d2b2c203
DJ		 7659
7660int
7661i386_elf_section_type (const char *str, size_t len)
7662{
7663 if (flag_code == CODE_64BIT
7664 && len == sizeof ("unwind") - 1
7665 && strncmp (str, "unwind", 6) == 0)
7666 return SHT_X86_64_UNWIND;
7667
7668 return -1;
7669}
bb41ade5
AM		 7670
7671#ifdef TE_PE
7672void
7673tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7674{
7675 expressionS expr;
7676
7677 expr.X_op = O_secrel;
7678 expr.X_add_symbol = symbol;
7679 expr.X_add_number = 0;
7680 emit_expr (&expr, size);
7681}
7682#endif
3b22753a
L		 7683
7684#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7685/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7686
7687int
7688x86_64_section_letter (int letter, char **ptr_msg)
7689{
7690 if (flag_code == CODE_64BIT)
7691 {
7692 if (letter == 'l')
7693 return SHF_X86_64_LARGE;
7694
7695 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7696 }
3b22753a 7697 else
64e74474 7698 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7699 return -1;
7700}
7701
7702int
7703x86_64_section_word (char *str, size_t len)
7704{
7705 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7706 return SHF_X86_64_LARGE;
7707
7708 return -1;
7709}
7710
7711static void
7712handle_large_common (int small ATTRIBUTE_UNUSED)
7713{
7714 if (flag_code != CODE_64BIT)
7715 {
7716 s_comm_internal (0, elf_common_parse);
7717 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7718 }
7719 else
7720 {
7721 static segT lbss_section;
7722 asection *saved_com_section_ptr = elf_com_section_ptr;
7723 asection *saved_bss_section = bss_section;
7724
7725 if (lbss_section == NULL)
7726 {
7727 flagword applicable;
7728 segT seg = now_seg;
7729 subsegT subseg = now_subseg;
7730
7731 /* The .lbss section is for local .largecomm symbols. */
7732 lbss_section = subseg_new (".lbss", 0);
7733 applicable = bfd_applicable_section_flags (stdoutput);
7734 bfd_set_section_flags (stdoutput, lbss_section,
7735 applicable & SEC_ALLOC);
7736 seg_info (lbss_section)->bss = 1;
7737
7738 subseg_set (seg, subseg);
7739 }
7740
7741 elf_com_section_ptr = &_bfd_elf_large_com_section;
7742 bss_section = lbss_section;
7743
7744 s_comm_internal (0, elf_common_parse);
7745
7746 elf_com_section_ptr = saved_com_section_ptr;
7747 bss_section = saved_bss_section;
7748 }
7749}
7750#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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