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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
250d07de | 2 | Copyright (C) 1989-2021 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
d2b2c203 | 33 | #include "elf/x86-64.h" |
40fb9820 | 34 | #include "opcodes/i386-init.h" |
41fd2579 | 35 | #include <limits.h> |
41fd2579 | 36 | |
c3332e24 | 37 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 38 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
39 | #endif |
40 | ||
29b0f896 AM |
41 | #ifndef DEFAULT_ARCH |
42 | #define DEFAULT_ARCH "i386" | |
246fcdee | 43 | #endif |
252b5132 | 44 | |
edde18a5 AM |
45 | #ifndef INLINE |
46 | #if __GNUC__ >= 2 | |
47 | #define INLINE __inline__ | |
48 | #else | |
49 | #define INLINE | |
50 | #endif | |
51 | #endif | |
52 | ||
6305a203 L |
53 | /* Prefixes will be emitted in the order defined below. |
54 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
55 | instruction, and so must come before any prefixes. | |
56 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 57 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
58 | #define WAIT_PREFIX 0 |
59 | #define SEG_PREFIX 1 | |
60 | #define ADDR_PREFIX 2 | |
61 | #define DATA_PREFIX 3 | |
c32fa91d | 62 | #define REP_PREFIX 4 |
42164a71 | 63 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 64 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 65 | #define LOCK_PREFIX 5 |
4e9ac44a L |
66 | #define REX_PREFIX 6 /* must come last. */ |
67 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
68 | |
69 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
70 | #define REGISTER_PREFIX '%' | |
71 | #define IMMEDIATE_PREFIX '$' | |
72 | #define ABSOLUTE_PREFIX '*' | |
73 | ||
74 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
75 | memory operand size in Intel syntax. */ | |
76 | #define WORD_MNEM_SUFFIX 'w' | |
77 | #define BYTE_MNEM_SUFFIX 'b' | |
78 | #define SHORT_MNEM_SUFFIX 's' | |
79 | #define LONG_MNEM_SUFFIX 'l' | |
80 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
81 | /* Intel Syntax. Use a non-ascii letter since since it never appears |
82 | in instructions. */ | |
83 | #define LONG_DOUBLE_MNEM_SUFFIX '\1' | |
84 | ||
85 | #define END_OF_INSN '\0' | |
86 | ||
79dec6b7 JB |
87 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
88 | #define commutative staticrounding | |
89 | ||
6305a203 L |
90 | /* |
91 | 'templates' is for grouping together 'template' structures for opcodes | |
92 | of the same name. This is only used for storing the insns in the grand | |
93 | ole hash table of insns. | |
94 | The templates themselves start at START and range up to (but not including) | |
95 | END. | |
96 | */ | |
97 | typedef struct | |
98 | { | |
d3ce72d0 NC |
99 | const insn_template *start; |
100 | const insn_template *end; | |
6305a203 L |
101 | } |
102 | templates; | |
103 | ||
104 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
105 | typedef struct | |
106 | { | |
107 | unsigned int regmem; /* codes register or memory operand */ | |
108 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
109 | unsigned int mode; /* how to interpret regmem & reg */ | |
110 | } | |
111 | modrm_byte; | |
112 | ||
113 | /* x86-64 extension prefix. */ | |
114 | typedef int rex_byte; | |
115 | ||
6305a203 L |
116 | /* 386 opcode byte to code indirect addressing. */ |
117 | typedef struct | |
118 | { | |
119 | unsigned base; | |
120 | unsigned index; | |
121 | unsigned scale; | |
122 | } | |
123 | sib_byte; | |
124 | ||
6305a203 L |
125 | /* x86 arch names, types and features */ |
126 | typedef struct | |
127 | { | |
128 | const char *name; /* arch name */ | |
8a2c8fef | 129 | unsigned int len; /* arch string length */ |
6305a203 L |
130 | enum processor_type type; /* arch type */ |
131 | i386_cpu_flags flags; /* cpu feature flags */ | |
8a2c8fef | 132 | unsigned int skip; /* show_arch should skip this. */ |
6305a203 L |
133 | } |
134 | arch_entry; | |
135 | ||
293f5f65 L |
136 | /* Used to turn off indicated flags. */ |
137 | typedef struct | |
138 | { | |
139 | const char *name; /* arch name */ | |
140 | unsigned int len; /* arch string length */ | |
141 | i386_cpu_flags flags; /* cpu feature flags */ | |
142 | } | |
143 | noarch_entry; | |
144 | ||
78f12dd3 | 145 | static void update_code_flag (int, int); |
e3bb37b5 L |
146 | static void set_code_flag (int); |
147 | static void set_16bit_gcc_code_flag (int); | |
148 | static void set_intel_syntax (int); | |
1efbbeb4 | 149 | static void set_intel_mnemonic (int); |
db51cc60 | 150 | static void set_allow_index_reg (int); |
7bab8ab5 | 151 | static void set_check (int); |
e3bb37b5 | 152 | static void set_cpu_arch (int); |
6482c264 | 153 | #ifdef TE_PE |
e3bb37b5 | 154 | static void pe_directive_secrel (int); |
6482c264 | 155 | #endif |
e3bb37b5 L |
156 | static void signed_cons (int); |
157 | static char *output_invalid (int c); | |
ee86248c JB |
158 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
159 | const char *); | |
160 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
161 | const char *); | |
a7619375 | 162 | static int i386_att_operand (char *); |
e3bb37b5 | 163 | static int i386_intel_operand (char *, int); |
ee86248c JB |
164 | static int i386_intel_simplify (expressionS *); |
165 | static int i386_intel_parse_name (const char *, expressionS *); | |
e3bb37b5 L |
166 | static const reg_entry *parse_register (char *, char **); |
167 | static char *parse_insn (char *, char *); | |
168 | static char *parse_operands (char *, const char *); | |
169 | static void swap_operands (void); | |
783c187b | 170 | static void swap_2_operands (unsigned int, unsigned int); |
48bcea9f | 171 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 L |
172 | static void optimize_imm (void); |
173 | static void optimize_disp (void); | |
83b16ac6 | 174 | static const insn_template *match_template (char); |
e3bb37b5 L |
175 | static int check_string (void); |
176 | static int process_suffix (void); | |
177 | static int check_byte_reg (void); | |
178 | static int check_long_reg (void); | |
179 | static int check_qword_reg (void); | |
180 | static int check_word_reg (void); | |
181 | static int finalize_imm (void); | |
182 | static int process_operands (void); | |
5e042380 | 183 | static const reg_entry *build_modrm_byte (void); |
e3bb37b5 L |
184 | static void output_insn (void); |
185 | static void output_imm (fragS *, offsetT); | |
186 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 187 | #ifndef I386COFF |
e3bb37b5 | 188 | static void s_bss (int); |
252b5132 | 189 | #endif |
17d4e2a2 L |
190 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
191 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
192 | |
193 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
194 | static unsigned int x86_isa_1_used; | |
195 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
196 | static unsigned int x86_feature_2_used; | |
197 | /* Generate x86 used ISA and feature properties. */ | |
198 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 199 | #endif |
252b5132 | 200 | |
a847613f | 201 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 202 | |
8a6fb3f9 JB |
203 | /* parse_register() returns this when a register alias cannot be used. */ |
204 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
205 | { Dw2Inval, Dw2Inval } }; | |
206 | ||
34684862 | 207 | static const reg_entry *reg_eax; |
5e042380 JB |
208 | static const reg_entry *reg_ds; |
209 | static const reg_entry *reg_es; | |
210 | static const reg_entry *reg_ss; | |
6288d05f | 211 | static const reg_entry *reg_st0; |
6225c532 JB |
212 | static const reg_entry *reg_k0; |
213 | ||
c0f3af97 L |
214 | /* VEX prefix. */ |
215 | typedef struct | |
216 | { | |
43234a1e L |
217 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
218 | unsigned char bytes[4]; | |
c0f3af97 L |
219 | unsigned int length; |
220 | /* Destination or source register specifier. */ | |
221 | const reg_entry *register_specifier; | |
222 | } vex_prefix; | |
223 | ||
252b5132 | 224 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 225 | i386_insn. */ |
252b5132 | 226 | |
520dc8e8 AM |
227 | union i386_op |
228 | { | |
229 | expressionS *disps; | |
230 | expressionS *imms; | |
231 | const reg_entry *regs; | |
232 | }; | |
233 | ||
a65babc9 L |
234 | enum i386_error |
235 | { | |
86e026a4 | 236 | operand_size_mismatch, |
a65babc9 L |
237 | operand_type_mismatch, |
238 | register_type_mismatch, | |
239 | number_of_operands_mismatch, | |
240 | invalid_instruction_suffix, | |
241 | bad_imm4, | |
a65babc9 L |
242 | unsupported_with_intel_mnemonic, |
243 | unsupported_syntax, | |
6c30d220 | 244 | unsupported, |
260cd341 | 245 | invalid_sib_address, |
6c30d220 | 246 | invalid_vsib_address, |
7bab8ab5 | 247 | invalid_vector_register_set, |
260cd341 | 248 | invalid_tmm_register_set, |
43234a1e L |
249 | unsupported_vector_index_register, |
250 | unsupported_broadcast, | |
43234a1e L |
251 | broadcast_needed, |
252 | unsupported_masking, | |
253 | mask_not_on_destination, | |
254 | no_default_mask, | |
255 | unsupported_rc_sae, | |
256 | rc_sae_operand_not_last_imm, | |
257 | invalid_register_operand, | |
a65babc9 L |
258 | }; |
259 | ||
252b5132 RH |
260 | struct _i386_insn |
261 | { | |
47926f60 | 262 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 263 | insn_template tm; |
252b5132 | 264 | |
7d5e4556 L |
265 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
266 | or qword, if given. */ | |
252b5132 RH |
267 | char suffix; |
268 | ||
9a182d04 JB |
269 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
270 | unsigned char opcode_length; | |
271 | ||
47926f60 | 272 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
273 | unsigned int operands; |
274 | ||
275 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
276 | of given register, displacement, memory operands and immediate | |
47926f60 | 277 | operands. */ |
252b5132 RH |
278 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
279 | ||
280 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 281 | use OP[i] for the corresponding operand. */ |
40fb9820 | 282 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 283 | |
520dc8e8 AM |
284 | /* Displacement expression, immediate expression, or register for each |
285 | operand. */ | |
286 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 287 | |
3e73aa7c JH |
288 | /* Flags for operands. */ |
289 | unsigned int flags[MAX_OPERANDS]; | |
290 | #define Operand_PCrel 1 | |
c48dadc9 | 291 | #define Operand_Mem 2 |
3e73aa7c | 292 | |
252b5132 | 293 | /* Relocation type for operand */ |
f86103b7 | 294 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 295 | |
252b5132 RH |
296 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
297 | the base index byte below. */ | |
298 | const reg_entry *base_reg; | |
299 | const reg_entry *index_reg; | |
300 | unsigned int log2_scale_factor; | |
301 | ||
302 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 303 | explicit segment overrides are given. */ |
5e042380 | 304 | const reg_entry *seg[2]; |
252b5132 | 305 | |
8325cc63 JB |
306 | /* Copied first memory operand string, for re-checking. */ |
307 | char *memop1_string; | |
308 | ||
252b5132 RH |
309 | /* PREFIX holds all the given prefix opcodes (usually null). |
310 | PREFIXES is the number of prefix opcodes. */ | |
311 | unsigned int prefixes; | |
312 | unsigned char prefix[MAX_PREFIXES]; | |
313 | ||
50128d0c | 314 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 315 | bool short_form; |
50128d0c | 316 | |
6f2f06be | 317 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 318 | bool jumpabsolute; |
6f2f06be | 319 | |
921eafea L |
320 | /* Extended states. */ |
321 | enum | |
322 | { | |
323 | /* Use MMX state. */ | |
324 | xstate_mmx = 1 << 0, | |
325 | /* Use XMM state. */ | |
326 | xstate_xmm = 1 << 1, | |
327 | /* Use YMM state. */ | |
328 | xstate_ymm = 1 << 2 | xstate_xmm, | |
329 | /* Use ZMM state. */ | |
330 | xstate_zmm = 1 << 3 | xstate_ymm, | |
331 | /* Use TMM state. */ | |
32930e4e L |
332 | xstate_tmm = 1 << 4, |
333 | /* Use MASK state. */ | |
334 | xstate_mask = 1 << 5 | |
921eafea | 335 | } xstate; |
260cd341 | 336 | |
e379e5f3 | 337 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 338 | bool has_gotpc_tls_reloc; |
e379e5f3 | 339 | |
252b5132 | 340 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 341 | addressing modes of this insn are encoded. */ |
252b5132 | 342 | modrm_byte rm; |
3e73aa7c | 343 | rex_byte rex; |
43234a1e | 344 | rex_byte vrex; |
252b5132 | 345 | sib_byte sib; |
c0f3af97 | 346 | vex_prefix vex; |
b6169b20 | 347 | |
6225c532 JB |
348 | /* Masking attributes. |
349 | ||
350 | The struct describes masking, applied to OPERAND in the instruction. | |
351 | REG is a pointer to the corresponding mask register. ZEROING tells | |
352 | whether merging or zeroing mask is used. */ | |
353 | struct Mask_Operation | |
354 | { | |
355 | const reg_entry *reg; | |
356 | unsigned int zeroing; | |
357 | /* The operand where this operation is associated. */ | |
358 | unsigned int operand; | |
359 | } mask; | |
43234a1e L |
360 | |
361 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
362 | struct RC_Operation |
363 | { | |
364 | enum rc_type | |
365 | { | |
366 | rc_none = -1, | |
367 | rne, | |
368 | rd, | |
369 | ru, | |
370 | rz, | |
371 | saeonly | |
372 | } type; | |
373 | ||
374 | unsigned int operand; | |
375 | } rounding; | |
43234a1e | 376 | |
5273a3cd JB |
377 | /* Broadcasting attributes. |
378 | ||
379 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
380 | expresses the broadcast factor. */ | |
381 | struct Broadcast_Operation | |
382 | { | |
383 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, or {1to16}. */ | |
384 | unsigned int type; | |
385 | ||
386 | /* Index of broadcasted operand. */ | |
387 | unsigned int operand; | |
388 | ||
389 | /* Number of bytes to broadcast. */ | |
390 | unsigned int bytes; | |
391 | } broadcast; | |
43234a1e L |
392 | |
393 | /* Compressed disp8*N attribute. */ | |
394 | unsigned int memshift; | |
395 | ||
86fa6981 L |
396 | /* Prefer load or store in encoding. */ |
397 | enum | |
398 | { | |
399 | dir_encoding_default = 0, | |
400 | dir_encoding_load, | |
64c49ab3 JB |
401 | dir_encoding_store, |
402 | dir_encoding_swap | |
86fa6981 | 403 | } dir_encoding; |
891edac4 | 404 | |
41eb8e88 | 405 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
406 | enum |
407 | { | |
408 | disp_encoding_default = 0, | |
409 | disp_encoding_8bit, | |
41eb8e88 | 410 | disp_encoding_16bit, |
a501d77e L |
411 | disp_encoding_32bit |
412 | } disp_encoding; | |
f8a5c266 | 413 | |
6b6b6807 | 414 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 415 | bool rex_encoding; |
6b6b6807 | 416 | |
b6f8c7c4 | 417 | /* Disable instruction size optimization. */ |
5b7c81bd | 418 | bool no_optimize; |
b6f8c7c4 | 419 | |
86fa6981 L |
420 | /* How to encode vector instructions. */ |
421 | enum | |
422 | { | |
423 | vex_encoding_default = 0, | |
42e04b36 | 424 | vex_encoding_vex, |
86fa6981 | 425 | vex_encoding_vex3, |
da4977e0 JB |
426 | vex_encoding_evex, |
427 | vex_encoding_error | |
86fa6981 L |
428 | } vec_encoding; |
429 | ||
d5de92cf L |
430 | /* REP prefix. */ |
431 | const char *rep_prefix; | |
432 | ||
165de32a L |
433 | /* HLE prefix. */ |
434 | const char *hle_prefix; | |
42164a71 | 435 | |
7e8b059b L |
436 | /* Have BND prefix. */ |
437 | const char *bnd_prefix; | |
438 | ||
04ef582a L |
439 | /* Have NOTRACK prefix. */ |
440 | const char *notrack_prefix; | |
441 | ||
891edac4 | 442 | /* Error message. */ |
a65babc9 | 443 | enum i386_error error; |
252b5132 RH |
444 | }; |
445 | ||
446 | typedef struct _i386_insn i386_insn; | |
447 | ||
43234a1e L |
448 | /* Link RC type with corresponding string, that'll be looked for in |
449 | asm. */ | |
450 | struct RC_name | |
451 | { | |
452 | enum rc_type type; | |
453 | const char *name; | |
454 | unsigned int len; | |
455 | }; | |
456 | ||
457 | static const struct RC_name RC_NamesTable[] = | |
458 | { | |
459 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
460 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
461 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
462 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
463 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
464 | }; | |
465 | ||
252b5132 RH |
466 | /* List of chars besides those in app.c:symbol_chars that can start an |
467 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 468 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 469 | #ifdef LEX_AT |
32137342 NC |
470 | "@" |
471 | #endif | |
472 | #ifdef LEX_QM | |
473 | "?" | |
252b5132 | 474 | #endif |
32137342 | 475 | ; |
252b5132 | 476 | |
b3983e5f JB |
477 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
478 | && !defined (TE_GNU) \ | |
479 | && !defined (TE_LINUX) \ | |
480 | && !defined (TE_FreeBSD) \ | |
481 | && !defined (TE_DragonFly) \ | |
482 | && !defined (TE_NetBSD)) | |
252b5132 | 483 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
484 | pre-processor is disabled, these aren't very useful. The option |
485 | --divide will remove '/' from this list. */ | |
486 | const char *i386_comment_chars = "#/"; | |
487 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 488 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 489 | |
b3b91714 AM |
490 | #else |
491 | const char *i386_comment_chars = "#"; | |
492 | #define PREFIX_SEPARATOR '/' | |
493 | #endif | |
494 | ||
252b5132 RH |
495 | /* This array holds the chars that only start a comment at the beginning of |
496 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
497 | .line and .file directives will appear in the pre-processed output. |
498 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 499 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
500 | #NO_APP at the beginning of its output. |
501 | Also note that comments started like this one will always work if | |
252b5132 | 502 | '/' isn't otherwise defined. */ |
b3b91714 | 503 | const char line_comment_chars[] = "#/"; |
252b5132 | 504 | |
63a0b638 | 505 | const char line_separator_chars[] = ";"; |
252b5132 | 506 | |
ce8a8b2f AM |
507 | /* Chars that can be used to separate mant from exp in floating point |
508 | nums. */ | |
252b5132 RH |
509 | const char EXP_CHARS[] = "eE"; |
510 | ||
ce8a8b2f AM |
511 | /* Chars that mean this number is a floating point constant |
512 | As in 0f12.456 | |
513 | or 0d1.2345e12. */ | |
252b5132 RH |
514 | const char FLT_CHARS[] = "fFdDxX"; |
515 | ||
ce8a8b2f | 516 | /* Tables for lexical analysis. */ |
252b5132 RH |
517 | static char mnemonic_chars[256]; |
518 | static char register_chars[256]; | |
519 | static char operand_chars[256]; | |
520 | static char identifier_chars[256]; | |
521 | static char digit_chars[256]; | |
522 | ||
ce8a8b2f | 523 | /* Lexical macros. */ |
252b5132 RH |
524 | #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x]) |
525 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) | |
526 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
527 | #define is_space_char(x) ((x) == ' ') | |
528 | #define is_identifier_char(x) (identifier_chars[(unsigned char) x]) | |
529 | #define is_digit_char(x) (digit_chars[(unsigned char) x]) | |
530 | ||
0234cb7c | 531 | /* All non-digit non-letter characters that may occur in an operand. */ |
252b5132 RH |
532 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
533 | ||
534 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
535 | effect this we maintain a stack of saved characters that we've smashed | |
536 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 537 | assembler instruction). */ |
252b5132 | 538 | static char save_stack[32]; |
ce8a8b2f | 539 | static char *save_stack_p; |
252b5132 RH |
540 | #define END_STRING_AND_SAVE(s) \ |
541 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
542 | #define RESTORE_END_STRING(s) \ | |
543 | do { *(s) = *--save_stack_p; } while (0) | |
544 | ||
47926f60 | 545 | /* The instruction we're assembling. */ |
252b5132 RH |
546 | static i386_insn i; |
547 | ||
548 | /* Possible templates for current insn. */ | |
549 | static const templates *current_templates; | |
550 | ||
31b2323c L |
551 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
552 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
553 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 554 | |
47926f60 | 555 | /* Current operand we are working on. */ |
ee86248c | 556 | static int this_operand = -1; |
252b5132 | 557 | |
3e73aa7c JH |
558 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
559 | these. */ | |
560 | ||
561 | enum flag_code { | |
562 | CODE_32BIT, | |
563 | CODE_16BIT, | |
564 | CODE_64BIT }; | |
565 | ||
566 | static enum flag_code flag_code; | |
4fa24527 | 567 | static unsigned int object_64bit; |
862be3fb | 568 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 569 | static int use_rela_relocations = 0; |
e379e5f3 L |
570 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
571 | static const char *tls_get_addr; | |
3e73aa7c | 572 | |
7af8ed2d NC |
573 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
574 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
575 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
576 | ||
351f65ca L |
577 | /* The ELF ABI to use. */ |
578 | enum x86_elf_abi | |
579 | { | |
580 | I386_ABI, | |
7f56bc95 L |
581 | X86_64_ABI, |
582 | X86_64_X32_ABI | |
351f65ca L |
583 | }; |
584 | ||
585 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 586 | #endif |
351f65ca | 587 | |
167ad85b TG |
588 | #if defined (TE_PE) || defined (TE_PEP) |
589 | /* Use big object file format. */ | |
590 | static int use_big_obj = 0; | |
591 | #endif | |
592 | ||
8dcea932 L |
593 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
594 | /* 1 if generating code for a shared library. */ | |
595 | static int shared = 0; | |
596 | #endif | |
597 | ||
47926f60 KH |
598 | /* 1 for intel syntax, |
599 | 0 if att syntax. */ | |
600 | static int intel_syntax = 0; | |
252b5132 | 601 | |
4b5aaf5f L |
602 | static enum x86_64_isa |
603 | { | |
604 | amd64 = 1, /* AMD64 ISA. */ | |
605 | intel64 /* Intel64 ISA. */ | |
606 | } isa64; | |
e89c5eaa | 607 | |
1efbbeb4 L |
608 | /* 1 for intel mnemonic, |
609 | 0 if att mnemonic. */ | |
610 | static int intel_mnemonic = !SYSV386_COMPAT; | |
611 | ||
a60de03c JB |
612 | /* 1 if pseudo registers are permitted. */ |
613 | static int allow_pseudo_reg = 0; | |
614 | ||
47926f60 KH |
615 | /* 1 if register prefix % not required. */ |
616 | static int allow_naked_reg = 0; | |
252b5132 | 617 | |
33eaf5de | 618 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
619 | instructions supporting it, even if this prefix wasn't specified |
620 | explicitly. */ | |
621 | static int add_bnd_prefix = 0; | |
622 | ||
ba104c83 | 623 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
624 | static int allow_index_reg = 0; |
625 | ||
d022bddd IT |
626 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
627 | specified explicitly. */ | |
628 | static int omit_lock_prefix = 0; | |
629 | ||
e4e00185 AS |
630 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
631 | "lock addl $0, (%{re}sp)". */ | |
632 | static int avoid_fence = 0; | |
633 | ||
ae531041 L |
634 | /* 1 if lfence should be inserted after every load. */ |
635 | static int lfence_after_load = 0; | |
636 | ||
637 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
638 | static enum lfence_before_indirect_branch_kind | |
639 | { | |
640 | lfence_branch_none = 0, | |
641 | lfence_branch_register, | |
642 | lfence_branch_memory, | |
643 | lfence_branch_all | |
644 | } | |
645 | lfence_before_indirect_branch; | |
646 | ||
647 | /* Non-zero if lfence should be inserted before ret. */ | |
648 | static enum lfence_before_ret_kind | |
649 | { | |
650 | lfence_before_ret_none = 0, | |
651 | lfence_before_ret_not, | |
a09f656b | 652 | lfence_before_ret_or, |
653 | lfence_before_ret_shl | |
ae531041 L |
654 | } |
655 | lfence_before_ret; | |
656 | ||
657 | /* Types of previous instruction is .byte or prefix. */ | |
e379e5f3 L |
658 | static struct |
659 | { | |
660 | segT seg; | |
661 | const char *file; | |
662 | const char *name; | |
663 | unsigned int line; | |
664 | enum last_insn_kind | |
665 | { | |
666 | last_insn_other = 0, | |
667 | last_insn_directive, | |
668 | last_insn_prefix | |
669 | } kind; | |
670 | } last_insn; | |
671 | ||
0cb4071e L |
672 | /* 1 if the assembler should generate relax relocations. */ |
673 | ||
674 | static int generate_relax_relocations | |
675 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
676 | ||
7bab8ab5 | 677 | static enum check_kind |
daf50ae7 | 678 | { |
7bab8ab5 JB |
679 | check_none = 0, |
680 | check_warning, | |
681 | check_error | |
daf50ae7 | 682 | } |
7bab8ab5 | 683 | sse_check, operand_check = check_warning; |
daf50ae7 | 684 | |
e379e5f3 L |
685 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
686 | static int align_branch_power = 0; | |
687 | ||
688 | /* Types of branches to align. */ | |
689 | enum align_branch_kind | |
690 | { | |
691 | align_branch_none = 0, | |
692 | align_branch_jcc = 1, | |
693 | align_branch_fused = 2, | |
694 | align_branch_jmp = 3, | |
695 | align_branch_call = 4, | |
696 | align_branch_indirect = 5, | |
697 | align_branch_ret = 6 | |
698 | }; | |
699 | ||
700 | /* Type bits of branches to align. */ | |
701 | enum align_branch_bit | |
702 | { | |
703 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
704 | align_branch_fused_bit = 1 << align_branch_fused, | |
705 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
706 | align_branch_call_bit = 1 << align_branch_call, | |
707 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
708 | align_branch_ret_bit = 1 << align_branch_ret | |
709 | }; | |
710 | ||
711 | static unsigned int align_branch = (align_branch_jcc_bit | |
712 | | align_branch_fused_bit | |
713 | | align_branch_jmp_bit); | |
714 | ||
79d72f45 HL |
715 | /* Types of condition jump used by macro-fusion. */ |
716 | enum mf_jcc_kind | |
717 | { | |
718 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
719 | mf_jcc_jc, /* base opcode 0x72 */ | |
720 | mf_jcc_je, /* base opcode 0x74 */ | |
721 | mf_jcc_jna, /* base opcode 0x76 */ | |
722 | mf_jcc_js, /* base opcode 0x78 */ | |
723 | mf_jcc_jp, /* base opcode 0x7a */ | |
724 | mf_jcc_jl, /* base opcode 0x7c */ | |
725 | mf_jcc_jle, /* base opcode 0x7e */ | |
726 | }; | |
727 | ||
728 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
729 | enum mf_cmp_kind | |
730 | { | |
731 | mf_cmp_test_and, /* test/cmp */ | |
732 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
733 | mf_cmp_incdec /* inc/dec */ | |
734 | }; | |
735 | ||
e379e5f3 L |
736 | /* The maximum padding size for fused jcc. CMP like instruction can |
737 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
738 | prefixes. */ | |
739 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
740 | ||
741 | /* The maximum number of prefixes added for an instruction. */ | |
742 | static unsigned int align_branch_prefix_size = 5; | |
743 | ||
b6f8c7c4 L |
744 | /* Optimization: |
745 | 1. Clear the REX_W bit with register operand if possible. | |
746 | 2. Above plus use 128bit vector instruction to clear the full vector | |
747 | register. | |
748 | */ | |
749 | static int optimize = 0; | |
750 | ||
751 | /* Optimization: | |
752 | 1. Clear the REX_W bit with register operand if possible. | |
753 | 2. Above plus use 128bit vector instruction to clear the full vector | |
754 | register. | |
755 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
756 | "testb $imm7,%r8". | |
757 | */ | |
758 | static int optimize_for_space = 0; | |
759 | ||
2ca3ace5 L |
760 | /* Register prefix used for error message. */ |
761 | static const char *register_prefix = "%"; | |
762 | ||
47926f60 KH |
763 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
764 | leave, push, and pop instructions so that gcc has the same stack | |
765 | frame as in 32 bit mode. */ | |
766 | static char stackop_size = '\0'; | |
eecb386c | 767 | |
12b55ccc L |
768 | /* Non-zero to optimize code alignment. */ |
769 | int optimize_align_code = 1; | |
770 | ||
47926f60 KH |
771 | /* Non-zero to quieten some warnings. */ |
772 | static int quiet_warnings = 0; | |
a38cf1db | 773 | |
47926f60 KH |
774 | /* CPU name. */ |
775 | static const char *cpu_arch_name = NULL; | |
6305a203 | 776 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 777 | |
47926f60 | 778 | /* CPU feature flags. */ |
40fb9820 L |
779 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
780 | ||
ccc9c027 L |
781 | /* If we have selected a cpu we are generating instructions for. */ |
782 | static int cpu_arch_tune_set = 0; | |
783 | ||
9103f4f4 | 784 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 785 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
786 | |
787 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 788 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 789 | |
ccc9c027 | 790 | /* CPU instruction set architecture used. */ |
fbf3f584 | 791 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 792 | |
9103f4f4 | 793 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 794 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 795 | |
fddf5b5b AM |
796 | /* If set, conditional jumps are not automatically promoted to handle |
797 | larger than a byte offset. */ | |
798 | static unsigned int no_cond_jump_promotion = 0; | |
799 | ||
c0f3af97 L |
800 | /* Encode SSE instructions with VEX prefix. */ |
801 | static unsigned int sse2avx; | |
802 | ||
539f890d L |
803 | /* Encode scalar AVX instructions with specific vector length. */ |
804 | static enum | |
805 | { | |
806 | vex128 = 0, | |
807 | vex256 | |
808 | } avxscalar; | |
809 | ||
03751133 L |
810 | /* Encode VEX WIG instructions with specific vex.w. */ |
811 | static enum | |
812 | { | |
813 | vexw0 = 0, | |
814 | vexw1 | |
815 | } vexwig; | |
816 | ||
43234a1e L |
817 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
818 | static enum | |
819 | { | |
820 | evexl128 = 0, | |
821 | evexl256, | |
822 | evexl512 | |
823 | } evexlig; | |
824 | ||
825 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
826 | static enum | |
827 | { | |
828 | evexw0 = 0, | |
829 | evexw1 | |
830 | } evexwig; | |
831 | ||
d3d3c6db IT |
832 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
833 | static enum rc_type evexrcig = rne; | |
834 | ||
29b0f896 | 835 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 836 | static symbolS *GOT_symbol; |
29b0f896 | 837 | |
a4447b93 RH |
838 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
839 | unsigned int x86_dwarf2_return_column; | |
840 | ||
841 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
842 | int x86_cie_data_alignment; | |
843 | ||
252b5132 | 844 | /* Interface to relax_segment. |
fddf5b5b AM |
845 | There are 3 major relax states for 386 jump insns because the |
846 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
847 | figuring out what sort of jump to choose to reach a given label. |
848 | ||
849 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
850 | branches which are handled by md_estimate_size_before_relax() and | |
851 | i386_generic_table_relax_frag(). */ | |
252b5132 | 852 | |
47926f60 | 853 | /* Types. */ |
93c2a809 AM |
854 | #define UNCOND_JUMP 0 |
855 | #define COND_JUMP 1 | |
856 | #define COND_JUMP86 2 | |
e379e5f3 L |
857 | #define BRANCH_PADDING 3 |
858 | #define BRANCH_PREFIX 4 | |
859 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 860 | |
47926f60 | 861 | /* Sizes. */ |
252b5132 RH |
862 | #define CODE16 1 |
863 | #define SMALL 0 | |
29b0f896 | 864 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 865 | #define BIG 2 |
29b0f896 | 866 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
867 | |
868 | #ifndef INLINE | |
869 | #ifdef __GNUC__ | |
870 | #define INLINE __inline__ | |
871 | #else | |
872 | #define INLINE | |
873 | #endif | |
874 | #endif | |
875 | ||
fddf5b5b AM |
876 | #define ENCODE_RELAX_STATE(type, size) \ |
877 | ((relax_substateT) (((type) << 2) | (size))) | |
878 | #define TYPE_FROM_RELAX_STATE(s) \ | |
879 | ((s) >> 2) | |
880 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
881 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
882 | |
883 | /* This table is used by relax_frag to promote short jumps to long | |
884 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
885 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
886 | don't allow a short jump in a 32 bit code segment to be promoted to | |
887 | a 16 bit offset jump because it's slower (requires data size | |
888 | prefix), and doesn't work, unless the destination is in the bottom | |
889 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
890 | ||
891 | const relax_typeS md_relax_table[] = | |
892 | { | |
24eab124 AM |
893 | /* The fields are: |
894 | 1) most positive reach of this state, | |
895 | 2) most negative reach of this state, | |
93c2a809 | 896 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 897 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 898 | |
fddf5b5b | 899 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
900 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
901 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
902 | /* dword jmp adds 4 bytes to frag: | |
903 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 904 | {0, 0, 4, 0}, |
93c2a809 AM |
905 | /* word jmp adds 2 byte2 to frag: |
906 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
907 | {0, 0, 2, 0}, |
908 | ||
93c2a809 AM |
909 | /* COND_JUMP states. */ |
910 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
911 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
912 | /* dword conditionals adds 5 bytes to frag: | |
913 | 1 extra opcode byte, 4 displacement bytes. */ | |
914 | {0, 0, 5, 0}, | |
fddf5b5b | 915 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
916 | 1 extra opcode byte, 2 displacement bytes. */ |
917 | {0, 0, 3, 0}, | |
918 | ||
919 | /* COND_JUMP86 states. */ | |
920 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
921 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
922 | /* dword conditionals adds 5 bytes to frag: | |
923 | 1 extra opcode byte, 4 displacement bytes. */ | |
924 | {0, 0, 5, 0}, | |
925 | /* word conditionals add 4 bytes to frag: | |
926 | 1 displacement byte and a 3 byte long branch insn. */ | |
927 | {0, 0, 4, 0} | |
252b5132 RH |
928 | }; |
929 | ||
9103f4f4 L |
930 | static const arch_entry cpu_arch[] = |
931 | { | |
89507696 JB |
932 | /* Do not replace the first two entries - i386_target_format() |
933 | relies on them being there in this order. */ | |
8a2c8fef | 934 | { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32, |
293f5f65 | 935 | CPU_GENERIC32_FLAGS, 0 }, |
8a2c8fef | 936 | { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64, |
293f5f65 | 937 | CPU_GENERIC64_FLAGS, 0 }, |
8a2c8fef | 938 | { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN, |
293f5f65 | 939 | CPU_NONE_FLAGS, 0 }, |
8a2c8fef | 940 | { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN, |
293f5f65 | 941 | CPU_I186_FLAGS, 0 }, |
8a2c8fef | 942 | { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN, |
293f5f65 | 943 | CPU_I286_FLAGS, 0 }, |
8a2c8fef | 944 | { STRING_COMMA_LEN ("i386"), PROCESSOR_I386, |
293f5f65 | 945 | CPU_I386_FLAGS, 0 }, |
8a2c8fef | 946 | { STRING_COMMA_LEN ("i486"), PROCESSOR_I486, |
293f5f65 | 947 | CPU_I486_FLAGS, 0 }, |
8a2c8fef | 948 | { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM, |
293f5f65 | 949 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 950 | { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 951 | CPU_I686_FLAGS, 0 }, |
8a2c8fef | 952 | { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM, |
293f5f65 | 953 | CPU_I586_FLAGS, 0 }, |
8a2c8fef | 954 | { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 955 | CPU_PENTIUMPRO_FLAGS, 0 }, |
8a2c8fef | 956 | { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO, |
293f5f65 | 957 | CPU_P2_FLAGS, 0 }, |
8a2c8fef | 958 | { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO, |
293f5f65 | 959 | CPU_P3_FLAGS, 0 }, |
8a2c8fef | 960 | { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4, |
293f5f65 | 961 | CPU_P4_FLAGS, 0 }, |
8a2c8fef | 962 | { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA, |
293f5f65 | 963 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 964 | { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA, |
293f5f65 | 965 | CPU_NOCONA_FLAGS, 0 }, |
8a2c8fef | 966 | { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE, |
293f5f65 | 967 | CPU_CORE_FLAGS, 1 }, |
8a2c8fef | 968 | { STRING_COMMA_LEN ("core"), PROCESSOR_CORE, |
293f5f65 | 969 | CPU_CORE_FLAGS, 0 }, |
8a2c8fef | 970 | { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2, |
293f5f65 | 971 | CPU_CORE2_FLAGS, 1 }, |
8a2c8fef | 972 | { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2, |
293f5f65 | 973 | CPU_CORE2_FLAGS, 0 }, |
8a2c8fef | 974 | { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7, |
293f5f65 | 975 | CPU_COREI7_FLAGS, 0 }, |
8a2c8fef | 976 | { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM, |
293f5f65 | 977 | CPU_L1OM_FLAGS, 0 }, |
7a9068fe | 978 | { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM, |
293f5f65 | 979 | CPU_K1OM_FLAGS, 0 }, |
81486035 | 980 | { STRING_COMMA_LEN ("iamcu"), PROCESSOR_IAMCU, |
293f5f65 | 981 | CPU_IAMCU_FLAGS, 0 }, |
8a2c8fef | 982 | { STRING_COMMA_LEN ("k6"), PROCESSOR_K6, |
293f5f65 | 983 | CPU_K6_FLAGS, 0 }, |
8a2c8fef | 984 | { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6, |
293f5f65 | 985 | CPU_K6_2_FLAGS, 0 }, |
8a2c8fef | 986 | { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON, |
293f5f65 | 987 | CPU_ATHLON_FLAGS, 0 }, |
8a2c8fef | 988 | { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8, |
293f5f65 | 989 | CPU_K8_FLAGS, 1 }, |
8a2c8fef | 990 | { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8, |
293f5f65 | 991 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 992 | { STRING_COMMA_LEN ("k8"), PROCESSOR_K8, |
293f5f65 | 993 | CPU_K8_FLAGS, 0 }, |
8a2c8fef | 994 | { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10, |
293f5f65 | 995 | CPU_AMDFAM10_FLAGS, 0 }, |
8aedb9fe | 996 | { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD, |
293f5f65 | 997 | CPU_BDVER1_FLAGS, 0 }, |
8aedb9fe | 998 | { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD, |
293f5f65 | 999 | CPU_BDVER2_FLAGS, 0 }, |
5e5c50d3 | 1000 | { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD, |
293f5f65 | 1001 | CPU_BDVER3_FLAGS, 0 }, |
c7b0bd56 | 1002 | { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD, |
293f5f65 | 1003 | CPU_BDVER4_FLAGS, 0 }, |
029f3522 | 1004 | { STRING_COMMA_LEN ("znver1"), PROCESSOR_ZNVER, |
293f5f65 | 1005 | CPU_ZNVER1_FLAGS, 0 }, |
a9660a6f AP |
1006 | { STRING_COMMA_LEN ("znver2"), PROCESSOR_ZNVER, |
1007 | CPU_ZNVER2_FLAGS, 0 }, | |
646cc3e0 GG |
1008 | { STRING_COMMA_LEN ("znver3"), PROCESSOR_ZNVER, |
1009 | CPU_ZNVER3_FLAGS, 0 }, | |
7b458c12 | 1010 | { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT, |
293f5f65 | 1011 | CPU_BTVER1_FLAGS, 0 }, |
7b458c12 | 1012 | { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT, |
293f5f65 | 1013 | CPU_BTVER2_FLAGS, 0 }, |
8a2c8fef | 1014 | { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN, |
293f5f65 | 1015 | CPU_8087_FLAGS, 0 }, |
8a2c8fef | 1016 | { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN, |
293f5f65 | 1017 | CPU_287_FLAGS, 0 }, |
8a2c8fef | 1018 | { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN, |
293f5f65 | 1019 | CPU_387_FLAGS, 0 }, |
1848e567 L |
1020 | { STRING_COMMA_LEN (".687"), PROCESSOR_UNKNOWN, |
1021 | CPU_687_FLAGS, 0 }, | |
d871f3f4 L |
1022 | { STRING_COMMA_LEN (".cmov"), PROCESSOR_UNKNOWN, |
1023 | CPU_CMOV_FLAGS, 0 }, | |
1024 | { STRING_COMMA_LEN (".fxsr"), PROCESSOR_UNKNOWN, | |
1025 | CPU_FXSR_FLAGS, 0 }, | |
8a2c8fef | 1026 | { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1027 | CPU_MMX_FLAGS, 0 }, |
8a2c8fef | 1028 | { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN, |
293f5f65 | 1029 | CPU_SSE_FLAGS, 0 }, |
8a2c8fef | 1030 | { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1031 | CPU_SSE2_FLAGS, 0 }, |
8a2c8fef | 1032 | { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1033 | CPU_SSE3_FLAGS, 0 }, |
af5c13b0 L |
1034 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
1035 | CPU_SSE4A_FLAGS, 0 }, | |
8a2c8fef | 1036 | { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN, |
293f5f65 | 1037 | CPU_SSSE3_FLAGS, 0 }, |
8a2c8fef | 1038 | { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1039 | CPU_SSE4_1_FLAGS, 0 }, |
8a2c8fef | 1040 | { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1041 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1042 | { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1043 | CPU_SSE4_2_FLAGS, 0 }, |
8a2c8fef | 1044 | { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1045 | CPU_AVX_FLAGS, 0 }, |
6c30d220 | 1046 | { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1047 | CPU_AVX2_FLAGS, 0 }, |
43234a1e | 1048 | { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN, |
293f5f65 | 1049 | CPU_AVX512F_FLAGS, 0 }, |
43234a1e | 1050 | { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1051 | CPU_AVX512CD_FLAGS, 0 }, |
43234a1e | 1052 | { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN, |
293f5f65 | 1053 | CPU_AVX512ER_FLAGS, 0 }, |
43234a1e | 1054 | { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN, |
293f5f65 | 1055 | CPU_AVX512PF_FLAGS, 0 }, |
1dfc6506 | 1056 | { STRING_COMMA_LEN (".avx512dq"), PROCESSOR_UNKNOWN, |
293f5f65 | 1057 | CPU_AVX512DQ_FLAGS, 0 }, |
1dfc6506 | 1058 | { STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1059 | CPU_AVX512BW_FLAGS, 0 }, |
1dfc6506 | 1060 | { STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN, |
293f5f65 | 1061 | CPU_AVX512VL_FLAGS, 0 }, |
8a2c8fef | 1062 | { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1063 | CPU_VMX_FLAGS, 0 }, |
8729a6f6 | 1064 | { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN, |
293f5f65 | 1065 | CPU_VMFUNC_FLAGS, 0 }, |
8a2c8fef | 1066 | { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1067 | CPU_SMX_FLAGS, 0 }, |
8a2c8fef | 1068 | { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN, |
293f5f65 | 1069 | CPU_XSAVE_FLAGS, 0 }, |
c7b8aa3a | 1070 | { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1071 | CPU_XSAVEOPT_FLAGS, 0 }, |
1dfc6506 | 1072 | { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, |
293f5f65 | 1073 | CPU_XSAVEC_FLAGS, 0 }, |
1dfc6506 | 1074 | { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, |
293f5f65 | 1075 | CPU_XSAVES_FLAGS, 0 }, |
8a2c8fef | 1076 | { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN, |
293f5f65 | 1077 | CPU_AES_FLAGS, 0 }, |
8a2c8fef | 1078 | { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1079 | CPU_PCLMUL_FLAGS, 0 }, |
8a2c8fef | 1080 | { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN, |
293f5f65 | 1081 | CPU_PCLMUL_FLAGS, 1 }, |
c7b8aa3a | 1082 | { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN, |
293f5f65 | 1083 | CPU_FSGSBASE_FLAGS, 0 }, |
c7b8aa3a | 1084 | { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN, |
293f5f65 | 1085 | CPU_RDRND_FLAGS, 0 }, |
c7b8aa3a | 1086 | { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN, |
293f5f65 | 1087 | CPU_F16C_FLAGS, 0 }, |
6c30d220 | 1088 | { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN, |
293f5f65 | 1089 | CPU_BMI2_FLAGS, 0 }, |
8a2c8fef | 1090 | { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1091 | CPU_FMA_FLAGS, 0 }, |
8a2c8fef | 1092 | { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN, |
293f5f65 | 1093 | CPU_FMA4_FLAGS, 0 }, |
8a2c8fef | 1094 | { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1095 | CPU_XOP_FLAGS, 0 }, |
8a2c8fef | 1096 | { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1097 | CPU_LWP_FLAGS, 0 }, |
8a2c8fef | 1098 | { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN, |
293f5f65 | 1099 | CPU_MOVBE_FLAGS, 0 }, |
60aa667e | 1100 | { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN, |
293f5f65 | 1101 | CPU_CX16_FLAGS, 0 }, |
8a2c8fef | 1102 | { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN, |
293f5f65 | 1103 | CPU_EPT_FLAGS, 0 }, |
6c30d220 | 1104 | { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1105 | CPU_LZCNT_FLAGS, 0 }, |
272a84b1 L |
1106 | { STRING_COMMA_LEN (".popcnt"), PROCESSOR_UNKNOWN, |
1107 | CPU_POPCNT_FLAGS, 0 }, | |
42164a71 | 1108 | { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN, |
293f5f65 | 1109 | CPU_HLE_FLAGS, 0 }, |
42164a71 | 1110 | { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1111 | CPU_RTM_FLAGS, 0 }, |
6c30d220 | 1112 | { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1113 | CPU_INVPCID_FLAGS, 0 }, |
8a2c8fef | 1114 | { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN, |
293f5f65 | 1115 | CPU_CLFLUSH_FLAGS, 0 }, |
22109423 | 1116 | { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN, |
293f5f65 | 1117 | CPU_NOP_FLAGS, 0 }, |
8a2c8fef | 1118 | { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN, |
293f5f65 | 1119 | CPU_SYSCALL_FLAGS, 0 }, |
8a2c8fef | 1120 | { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN, |
293f5f65 | 1121 | CPU_RDTSCP_FLAGS, 0 }, |
8a2c8fef | 1122 | { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN, |
293f5f65 | 1123 | CPU_3DNOW_FLAGS, 0 }, |
8a2c8fef | 1124 | { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN, |
293f5f65 | 1125 | CPU_3DNOWA_FLAGS, 0 }, |
8a2c8fef | 1126 | { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN, |
293f5f65 | 1127 | CPU_PADLOCK_FLAGS, 0 }, |
8a2c8fef | 1128 | { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN, |
293f5f65 | 1129 | CPU_SVME_FLAGS, 1 }, |
8a2c8fef | 1130 | { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN, |
293f5f65 | 1131 | CPU_SVME_FLAGS, 0 }, |
8a2c8fef | 1132 | { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN, |
293f5f65 | 1133 | CPU_SSE4A_FLAGS, 0 }, |
8a2c8fef | 1134 | { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1135 | CPU_ABM_FLAGS, 0 }, |
87973e9f | 1136 | { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1137 | CPU_BMI_FLAGS, 0 }, |
2a2a0f38 | 1138 | { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN, |
293f5f65 | 1139 | CPU_TBM_FLAGS, 0 }, |
e2e1fcde | 1140 | { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1141 | CPU_ADX_FLAGS, 0 }, |
e2e1fcde | 1142 | { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN, |
293f5f65 | 1143 | CPU_RDSEED_FLAGS, 0 }, |
e2e1fcde | 1144 | { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN, |
293f5f65 | 1145 | CPU_PRFCHW_FLAGS, 0 }, |
5c111e37 | 1146 | { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN, |
293f5f65 | 1147 | CPU_SMAP_FLAGS, 0 }, |
7e8b059b | 1148 | { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1149 | CPU_MPX_FLAGS, 0 }, |
a0046408 | 1150 | { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, |
293f5f65 | 1151 | CPU_SHA_FLAGS, 0 }, |
963f3586 | 1152 | { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, |
293f5f65 | 1153 | CPU_CLFLUSHOPT_FLAGS, 0 }, |
dcf893b5 | 1154 | { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1155 | CPU_PREFETCHWT1_FLAGS, 0 }, |
2cf200a4 | 1156 | { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, |
293f5f65 | 1157 | CPU_SE1_FLAGS, 0 }, |
c5e7287a | 1158 | { STRING_COMMA_LEN (".clwb"), PROCESSOR_UNKNOWN, |
293f5f65 | 1159 | CPU_CLWB_FLAGS, 0 }, |
2cc1b5aa | 1160 | { STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN, |
293f5f65 | 1161 | CPU_AVX512IFMA_FLAGS, 0 }, |
14f195c9 | 1162 | { STRING_COMMA_LEN (".avx512vbmi"), PROCESSOR_UNKNOWN, |
293f5f65 | 1163 | CPU_AVX512VBMI_FLAGS, 0 }, |
920d2ddc IT |
1164 | { STRING_COMMA_LEN (".avx512_4fmaps"), PROCESSOR_UNKNOWN, |
1165 | CPU_AVX512_4FMAPS_FLAGS, 0 }, | |
47acf0bd IT |
1166 | { STRING_COMMA_LEN (".avx512_4vnniw"), PROCESSOR_UNKNOWN, |
1167 | CPU_AVX512_4VNNIW_FLAGS, 0 }, | |
620214f7 IT |
1168 | { STRING_COMMA_LEN (".avx512_vpopcntdq"), PROCESSOR_UNKNOWN, |
1169 | CPU_AVX512_VPOPCNTDQ_FLAGS, 0 }, | |
53467f57 IT |
1170 | { STRING_COMMA_LEN (".avx512_vbmi2"), PROCESSOR_UNKNOWN, |
1171 | CPU_AVX512_VBMI2_FLAGS, 0 }, | |
8cfcb765 IT |
1172 | { STRING_COMMA_LEN (".avx512_vnni"), PROCESSOR_UNKNOWN, |
1173 | CPU_AVX512_VNNI_FLAGS, 0 }, | |
ee6872be IT |
1174 | { STRING_COMMA_LEN (".avx512_bitalg"), PROCESSOR_UNKNOWN, |
1175 | CPU_AVX512_BITALG_FLAGS, 0 }, | |
58bf9b6a L |
1176 | { STRING_COMMA_LEN (".avx_vnni"), PROCESSOR_UNKNOWN, |
1177 | CPU_AVX_VNNI_FLAGS, 0 }, | |
029f3522 | 1178 | { STRING_COMMA_LEN (".clzero"), PROCESSOR_UNKNOWN, |
293f5f65 | 1179 | CPU_CLZERO_FLAGS, 0 }, |
9916071f | 1180 | { STRING_COMMA_LEN (".mwaitx"), PROCESSOR_UNKNOWN, |
293f5f65 | 1181 | CPU_MWAITX_FLAGS, 0 }, |
8eab4136 | 1182 | { STRING_COMMA_LEN (".ospke"), PROCESSOR_UNKNOWN, |
293f5f65 | 1183 | CPU_OSPKE_FLAGS, 0 }, |
8bc52696 | 1184 | { STRING_COMMA_LEN (".rdpid"), PROCESSOR_UNKNOWN, |
293f5f65 | 1185 | CPU_RDPID_FLAGS, 0 }, |
6b40c462 L |
1186 | { STRING_COMMA_LEN (".ptwrite"), PROCESSOR_UNKNOWN, |
1187 | CPU_PTWRITE_FLAGS, 0 }, | |
d777820b IT |
1188 | { STRING_COMMA_LEN (".ibt"), PROCESSOR_UNKNOWN, |
1189 | CPU_IBT_FLAGS, 0 }, | |
1190 | { STRING_COMMA_LEN (".shstk"), PROCESSOR_UNKNOWN, | |
1191 | CPU_SHSTK_FLAGS, 0 }, | |
48521003 IT |
1192 | { STRING_COMMA_LEN (".gfni"), PROCESSOR_UNKNOWN, |
1193 | CPU_GFNI_FLAGS, 0 }, | |
8dcf1fad IT |
1194 | { STRING_COMMA_LEN (".vaes"), PROCESSOR_UNKNOWN, |
1195 | CPU_VAES_FLAGS, 0 }, | |
ff1982d5 IT |
1196 | { STRING_COMMA_LEN (".vpclmulqdq"), PROCESSOR_UNKNOWN, |
1197 | CPU_VPCLMULQDQ_FLAGS, 0 }, | |
3233d7d0 IT |
1198 | { STRING_COMMA_LEN (".wbnoinvd"), PROCESSOR_UNKNOWN, |
1199 | CPU_WBNOINVD_FLAGS, 0 }, | |
be3a8dca IT |
1200 | { STRING_COMMA_LEN (".pconfig"), PROCESSOR_UNKNOWN, |
1201 | CPU_PCONFIG_FLAGS, 0 }, | |
de89d0a3 IT |
1202 | { STRING_COMMA_LEN (".waitpkg"), PROCESSOR_UNKNOWN, |
1203 | CPU_WAITPKG_FLAGS, 0 }, | |
c48935d7 IT |
1204 | { STRING_COMMA_LEN (".cldemote"), PROCESSOR_UNKNOWN, |
1205 | CPU_CLDEMOTE_FLAGS, 0 }, | |
260cd341 LC |
1206 | { STRING_COMMA_LEN (".amx_int8"), PROCESSOR_UNKNOWN, |
1207 | CPU_AMX_INT8_FLAGS, 0 }, | |
1208 | { STRING_COMMA_LEN (".amx_bf16"), PROCESSOR_UNKNOWN, | |
1209 | CPU_AMX_BF16_FLAGS, 0 }, | |
1210 | { STRING_COMMA_LEN (".amx_tile"), PROCESSOR_UNKNOWN, | |
1211 | CPU_AMX_TILE_FLAGS, 0 }, | |
c0a30a9f L |
1212 | { STRING_COMMA_LEN (".movdiri"), PROCESSOR_UNKNOWN, |
1213 | CPU_MOVDIRI_FLAGS, 0 }, | |
1214 | { STRING_COMMA_LEN (".movdir64b"), PROCESSOR_UNKNOWN, | |
1215 | CPU_MOVDIR64B_FLAGS, 0 }, | |
d6aab7a1 XG |
1216 | { STRING_COMMA_LEN (".avx512_bf16"), PROCESSOR_UNKNOWN, |
1217 | CPU_AVX512_BF16_FLAGS, 0 }, | |
9186c494 L |
1218 | { STRING_COMMA_LEN (".avx512_vp2intersect"), PROCESSOR_UNKNOWN, |
1219 | CPU_AVX512_VP2INTERSECT_FLAGS, 0 }, | |
81d54bb7 CL |
1220 | { STRING_COMMA_LEN (".tdx"), PROCESSOR_UNKNOWN, |
1221 | CPU_TDX_FLAGS, 0 }, | |
dd455cf5 L |
1222 | { STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN, |
1223 | CPU_ENQCMD_FLAGS, 0 }, | |
4b27d27c L |
1224 | { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN, |
1225 | CPU_SERIALIZE_FLAGS, 0 }, | |
142861df JB |
1226 | { STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN, |
1227 | CPU_RDPRU_FLAGS, 0 }, | |
1228 | { STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN, | |
1229 | CPU_MCOMMIT_FLAGS, 0 }, | |
a847e322 JB |
1230 | { STRING_COMMA_LEN (".sev_es"), PROCESSOR_UNKNOWN, |
1231 | CPU_SEV_ES_FLAGS, 0 }, | |
bb651e8b CL |
1232 | { STRING_COMMA_LEN (".tsxldtrk"), PROCESSOR_UNKNOWN, |
1233 | CPU_TSXLDTRK_FLAGS, 0 }, | |
c4694f17 TG |
1234 | { STRING_COMMA_LEN (".kl"), PROCESSOR_UNKNOWN, |
1235 | CPU_KL_FLAGS, 0 }, | |
1236 | { STRING_COMMA_LEN (".widekl"), PROCESSOR_UNKNOWN, | |
1237 | CPU_WIDEKL_FLAGS, 0 }, | |
f64c42a9 LC |
1238 | { STRING_COMMA_LEN (".uintr"), PROCESSOR_UNKNOWN, |
1239 | CPU_UINTR_FLAGS, 0 }, | |
c1fa250a LC |
1240 | { STRING_COMMA_LEN (".hreset"), PROCESSOR_UNKNOWN, |
1241 | CPU_HRESET_FLAGS, 0 }, | |
293f5f65 L |
1242 | }; |
1243 | ||
1244 | static const noarch_entry cpu_noarch[] = | |
1245 | { | |
1246 | { STRING_COMMA_LEN ("no87"), CPU_ANY_X87_FLAGS }, | |
1848e567 L |
1247 | { STRING_COMMA_LEN ("no287"), CPU_ANY_287_FLAGS }, |
1248 | { STRING_COMMA_LEN ("no387"), CPU_ANY_387_FLAGS }, | |
1249 | { STRING_COMMA_LEN ("no687"), CPU_ANY_687_FLAGS }, | |
d871f3f4 L |
1250 | { STRING_COMMA_LEN ("nocmov"), CPU_ANY_CMOV_FLAGS }, |
1251 | { STRING_COMMA_LEN ("nofxsr"), CPU_ANY_FXSR_FLAGS }, | |
293f5f65 L |
1252 | { STRING_COMMA_LEN ("nommx"), CPU_ANY_MMX_FLAGS }, |
1253 | { STRING_COMMA_LEN ("nosse"), CPU_ANY_SSE_FLAGS }, | |
1848e567 L |
1254 | { STRING_COMMA_LEN ("nosse2"), CPU_ANY_SSE2_FLAGS }, |
1255 | { STRING_COMMA_LEN ("nosse3"), CPU_ANY_SSE3_FLAGS }, | |
af5c13b0 | 1256 | { STRING_COMMA_LEN ("nosse4a"), CPU_ANY_SSE4A_FLAGS }, |
1848e567 L |
1257 | { STRING_COMMA_LEN ("nossse3"), CPU_ANY_SSSE3_FLAGS }, |
1258 | { STRING_COMMA_LEN ("nosse4.1"), CPU_ANY_SSE4_1_FLAGS }, | |
1259 | { STRING_COMMA_LEN ("nosse4.2"), CPU_ANY_SSE4_2_FLAGS }, | |
af5c13b0 | 1260 | { STRING_COMMA_LEN ("nosse4"), CPU_ANY_SSE4_1_FLAGS }, |
293f5f65 | 1261 | { STRING_COMMA_LEN ("noavx"), CPU_ANY_AVX_FLAGS }, |
1848e567 | 1262 | { STRING_COMMA_LEN ("noavx2"), CPU_ANY_AVX2_FLAGS }, |
144b71e2 L |
1263 | { STRING_COMMA_LEN ("noavx512f"), CPU_ANY_AVX512F_FLAGS }, |
1264 | { STRING_COMMA_LEN ("noavx512cd"), CPU_ANY_AVX512CD_FLAGS }, | |
1265 | { STRING_COMMA_LEN ("noavx512er"), CPU_ANY_AVX512ER_FLAGS }, | |
1266 | { STRING_COMMA_LEN ("noavx512pf"), CPU_ANY_AVX512PF_FLAGS }, | |
1267 | { STRING_COMMA_LEN ("noavx512dq"), CPU_ANY_AVX512DQ_FLAGS }, | |
1268 | { STRING_COMMA_LEN ("noavx512bw"), CPU_ANY_AVX512BW_FLAGS }, | |
1269 | { STRING_COMMA_LEN ("noavx512vl"), CPU_ANY_AVX512VL_FLAGS }, | |
1270 | { STRING_COMMA_LEN ("noavx512ifma"), CPU_ANY_AVX512IFMA_FLAGS }, | |
1271 | { STRING_COMMA_LEN ("noavx512vbmi"), CPU_ANY_AVX512VBMI_FLAGS }, | |
920d2ddc | 1272 | { STRING_COMMA_LEN ("noavx512_4fmaps"), CPU_ANY_AVX512_4FMAPS_FLAGS }, |
47acf0bd | 1273 | { STRING_COMMA_LEN ("noavx512_4vnniw"), CPU_ANY_AVX512_4VNNIW_FLAGS }, |
620214f7 | 1274 | { STRING_COMMA_LEN ("noavx512_vpopcntdq"), CPU_ANY_AVX512_VPOPCNTDQ_FLAGS }, |
53467f57 | 1275 | { STRING_COMMA_LEN ("noavx512_vbmi2"), CPU_ANY_AVX512_VBMI2_FLAGS }, |
8cfcb765 | 1276 | { STRING_COMMA_LEN ("noavx512_vnni"), CPU_ANY_AVX512_VNNI_FLAGS }, |
ee6872be | 1277 | { STRING_COMMA_LEN ("noavx512_bitalg"), CPU_ANY_AVX512_BITALG_FLAGS }, |
58bf9b6a | 1278 | { STRING_COMMA_LEN ("noavx_vnni"), CPU_ANY_AVX_VNNI_FLAGS }, |
d777820b IT |
1279 | { STRING_COMMA_LEN ("noibt"), CPU_ANY_IBT_FLAGS }, |
1280 | { STRING_COMMA_LEN ("noshstk"), CPU_ANY_SHSTK_FLAGS }, | |
260cd341 LC |
1281 | { STRING_COMMA_LEN ("noamx_int8"), CPU_ANY_AMX_INT8_FLAGS }, |
1282 | { STRING_COMMA_LEN ("noamx_bf16"), CPU_ANY_AMX_BF16_FLAGS }, | |
1283 | { STRING_COMMA_LEN ("noamx_tile"), CPU_ANY_AMX_TILE_FLAGS }, | |
c0a30a9f L |
1284 | { STRING_COMMA_LEN ("nomovdiri"), CPU_ANY_MOVDIRI_FLAGS }, |
1285 | { STRING_COMMA_LEN ("nomovdir64b"), CPU_ANY_MOVDIR64B_FLAGS }, | |
d6aab7a1 | 1286 | { STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS }, |
708a2fff CL |
1287 | { STRING_COMMA_LEN ("noavx512_vp2intersect"), |
1288 | CPU_ANY_AVX512_VP2INTERSECT_FLAGS }, | |
81d54bb7 | 1289 | { STRING_COMMA_LEN ("notdx"), CPU_ANY_TDX_FLAGS }, |
dd455cf5 | 1290 | { STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS }, |
4b27d27c | 1291 | { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS }, |
bb651e8b | 1292 | { STRING_COMMA_LEN ("notsxldtrk"), CPU_ANY_TSXLDTRK_FLAGS }, |
c4694f17 TG |
1293 | { STRING_COMMA_LEN ("nokl"), CPU_ANY_KL_FLAGS }, |
1294 | { STRING_COMMA_LEN ("nowidekl"), CPU_ANY_WIDEKL_FLAGS }, | |
f64c42a9 | 1295 | { STRING_COMMA_LEN ("nouintr"), CPU_ANY_UINTR_FLAGS }, |
c1fa250a | 1296 | { STRING_COMMA_LEN ("nohreset"), CPU_ANY_HRESET_FLAGS }, |
e413e4e9 AM |
1297 | }; |
1298 | ||
704209c0 | 1299 | #ifdef I386COFF |
a6c24e68 NC |
1300 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1301 | is allowed to be optional. */ | |
1302 | ||
1303 | static symbolS * | |
1304 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1305 | { | |
1306 | addressT align = 0; | |
1307 | ||
1308 | SKIP_WHITESPACE (); | |
1309 | ||
7ab9ffdd | 1310 | if (needs_align |
a6c24e68 NC |
1311 | && *input_line_pointer == ',') |
1312 | { | |
1313 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1314 | |
a6c24e68 NC |
1315 | if (align == (addressT) -1) |
1316 | return NULL; | |
1317 | } | |
1318 | else | |
1319 | { | |
1320 | if (size >= 8) | |
1321 | align = 3; | |
1322 | else if (size >= 4) | |
1323 | align = 2; | |
1324 | else if (size >= 2) | |
1325 | align = 1; | |
1326 | else | |
1327 | align = 0; | |
1328 | } | |
1329 | ||
1330 | bss_alloc (symbolP, size, align); | |
1331 | return symbolP; | |
1332 | } | |
1333 | ||
704209c0 | 1334 | static void |
a6c24e68 NC |
1335 | pe_lcomm (int needs_align) |
1336 | { | |
1337 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1338 | } | |
704209c0 | 1339 | #endif |
a6c24e68 | 1340 | |
29b0f896 AM |
1341 | const pseudo_typeS md_pseudo_table[] = |
1342 | { | |
1343 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1344 | {"align", s_align_bytes, 0}, | |
1345 | #else | |
1346 | {"align", s_align_ptwo, 0}, | |
1347 | #endif | |
1348 | {"arch", set_cpu_arch, 0}, | |
1349 | #ifndef I386COFF | |
1350 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1351 | #else |
1352 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1353 | #endif |
1354 | {"ffloat", float_cons, 'f'}, | |
1355 | {"dfloat", float_cons, 'd'}, | |
1356 | {"tfloat", float_cons, 'x'}, | |
1357 | {"value", cons, 2}, | |
d182319b | 1358 | {"slong", signed_cons, 4}, |
29b0f896 AM |
1359 | {"noopt", s_ignore, 0}, |
1360 | {"optim", s_ignore, 0}, | |
1361 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1362 | {"code16", set_code_flag, CODE_16BIT}, | |
1363 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1364 | #ifdef BFD64 |
29b0f896 | 1365 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1366 | #endif |
29b0f896 AM |
1367 | {"intel_syntax", set_intel_syntax, 1}, |
1368 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1369 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1370 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1371 | {"allow_index_reg", set_allow_index_reg, 1}, |
1372 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1373 | {"sse_check", set_check, 0}, |
1374 | {"operand_check", set_check, 1}, | |
3b22753a L |
1375 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1376 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1377 | #else |
68d20676 | 1378 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1379 | {"loc", dwarf2_directive_loc, 0}, |
1380 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1381 | #endif |
6482c264 NC |
1382 | #ifdef TE_PE |
1383 | {"secrel32", pe_directive_secrel, 0}, | |
1384 | #endif | |
29b0f896 AM |
1385 | {0, 0, 0} |
1386 | }; | |
1387 | ||
1388 | /* For interface with expression (). */ | |
1389 | extern char *input_line_pointer; | |
1390 | ||
1391 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1392 | static htab_t op_hash; |
29b0f896 AM |
1393 | |
1394 | /* Hash table for register lookup. */ | |
629310ab | 1395 | static htab_t reg_hash; |
29b0f896 | 1396 | \f |
ce8a8b2f AM |
1397 | /* Various efficient no-op patterns for aligning code labels. |
1398 | Note: Don't try to assemble the instructions in the comments. | |
1399 | 0L and 0w are not legal. */ | |
62a02d25 L |
1400 | static const unsigned char f32_1[] = |
1401 | {0x90}; /* nop */ | |
1402 | static const unsigned char f32_2[] = | |
1403 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1404 | static const unsigned char f32_3[] = | |
1405 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1406 | static const unsigned char f32_4[] = | |
1407 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1408 | static const unsigned char f32_6[] = |
1409 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1410 | static const unsigned char f32_7[] = | |
1411 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1412 | static const unsigned char f16_3[] = |
3ae729d5 | 1413 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1414 | static const unsigned char f16_4[] = |
3ae729d5 L |
1415 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1416 | static const unsigned char jump_disp8[] = | |
1417 | {0xeb}; /* jmp disp8 */ | |
1418 | static const unsigned char jump32_disp32[] = | |
1419 | {0xe9}; /* jmp disp32 */ | |
1420 | static const unsigned char jump16_disp32[] = | |
1421 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1422 | /* 32-bit NOPs patterns. */ |
1423 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1424 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1425 | }; |
1426 | /* 16-bit NOPs patterns. */ | |
1427 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1428 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1429 | }; |
1430 | /* nopl (%[re]ax) */ | |
1431 | static const unsigned char alt_3[] = | |
1432 | {0x0f,0x1f,0x00}; | |
1433 | /* nopl 0(%[re]ax) */ | |
1434 | static const unsigned char alt_4[] = | |
1435 | {0x0f,0x1f,0x40,0x00}; | |
1436 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1437 | static const unsigned char alt_5[] = | |
1438 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1439 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1440 | static const unsigned char alt_6[] = | |
1441 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1442 | /* nopl 0L(%[re]ax) */ | |
1443 | static const unsigned char alt_7[] = | |
1444 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1445 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1446 | static const unsigned char alt_8[] = | |
1447 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1448 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1449 | static const unsigned char alt_9[] = | |
1450 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1451 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1452 | static const unsigned char alt_10[] = | |
1453 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1454 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1455 | static const unsigned char alt_11[] = | |
1456 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1457 | /* 32-bit and 64-bit NOPs patterns. */ |
1458 | static const unsigned char *const alt_patt[] = { | |
1459 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1460 | alt_9, alt_10, alt_11 |
62a02d25 L |
1461 | }; |
1462 | ||
1463 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1464 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1465 | ||
1466 | static void | |
1467 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1468 | int count, int max_single_nop_size) | |
1469 | ||
1470 | { | |
3ae729d5 L |
1471 | /* Place the longer NOP first. */ |
1472 | int last; | |
1473 | int offset; | |
3076e594 NC |
1474 | const unsigned char *nops; |
1475 | ||
1476 | if (max_single_nop_size < 1) | |
1477 | { | |
1478 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1479 | max_single_nop_size); | |
1480 | return; | |
1481 | } | |
1482 | ||
1483 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1484 | |
1485 | /* Use the smaller one if the requsted one isn't available. */ | |
1486 | if (nops == NULL) | |
62a02d25 | 1487 | { |
3ae729d5 L |
1488 | max_single_nop_size--; |
1489 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1490 | } |
1491 | ||
3ae729d5 L |
1492 | last = count % max_single_nop_size; |
1493 | ||
1494 | count -= last; | |
1495 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1496 | memcpy (where + offset, nops, max_single_nop_size); | |
1497 | ||
1498 | if (last) | |
1499 | { | |
1500 | nops = patt[last - 1]; | |
1501 | if (nops == NULL) | |
1502 | { | |
1503 | /* Use the smaller one plus one-byte NOP if the needed one | |
1504 | isn't available. */ | |
1505 | last--; | |
1506 | nops = patt[last - 1]; | |
1507 | memcpy (where + offset, nops, last); | |
1508 | where[offset + last] = *patt[0]; | |
1509 | } | |
1510 | else | |
1511 | memcpy (where + offset, nops, last); | |
1512 | } | |
62a02d25 L |
1513 | } |
1514 | ||
3ae729d5 L |
1515 | static INLINE int |
1516 | fits_in_imm7 (offsetT num) | |
1517 | { | |
1518 | return (num & 0x7f) == num; | |
1519 | } | |
1520 | ||
1521 | static INLINE int | |
1522 | fits_in_imm31 (offsetT num) | |
1523 | { | |
1524 | return (num & 0x7fffffff) == num; | |
1525 | } | |
62a02d25 L |
1526 | |
1527 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1528 | single NOP instruction LIMIT. */ | |
1529 | ||
1530 | void | |
3ae729d5 | 1531 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1532 | { |
3ae729d5 | 1533 | const unsigned char *const *patt = NULL; |
62a02d25 | 1534 | int max_single_nop_size; |
3ae729d5 L |
1535 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1536 | int max_number_of_nops; | |
62a02d25 | 1537 | |
3ae729d5 | 1538 | switch (fragP->fr_type) |
62a02d25 | 1539 | { |
3ae729d5 L |
1540 | case rs_fill_nop: |
1541 | case rs_align_code: | |
1542 | break; | |
e379e5f3 L |
1543 | case rs_machine_dependent: |
1544 | /* Allow NOP padding for jumps and calls. */ | |
1545 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1546 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1547 | break; | |
1548 | /* Fall through. */ | |
3ae729d5 | 1549 | default: |
62a02d25 L |
1550 | return; |
1551 | } | |
1552 | ||
ccc9c027 L |
1553 | /* We need to decide which NOP sequence to use for 32bit and |
1554 | 64bit. When -mtune= is used: | |
4eed87de | 1555 | |
76bc74dc L |
1556 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1557 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1558 | 2. For the rest, alt_patt will be used. |
1559 | ||
1560 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1561 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1562 | be used. |
ccc9c027 L |
1563 | |
1564 | When -march= or .arch is used, we can't use anything beyond | |
1565 | cpu_arch_isa_flags. */ | |
1566 | ||
1567 | if (flag_code == CODE_16BIT) | |
1568 | { | |
3ae729d5 L |
1569 | patt = f16_patt; |
1570 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1571 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1572 | max_number_of_nops = 2; | |
252b5132 | 1573 | } |
33fef721 | 1574 | else |
ccc9c027 | 1575 | { |
fbf3f584 | 1576 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1577 | { |
1578 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1579 | switch (cpu_arch_tune) | |
1580 | { | |
1581 | case PROCESSOR_UNKNOWN: | |
1582 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1583 | optimize with nops. */ |
1584 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1585 | patt = alt_patt; |
ccc9c027 L |
1586 | else |
1587 | patt = f32_patt; | |
1588 | break; | |
ccc9c027 L |
1589 | case PROCESSOR_PENTIUM4: |
1590 | case PROCESSOR_NOCONA: | |
ef05d495 | 1591 | case PROCESSOR_CORE: |
76bc74dc | 1592 | case PROCESSOR_CORE2: |
bd5295b2 | 1593 | case PROCESSOR_COREI7: |
3632d14b | 1594 | case PROCESSOR_L1OM: |
7a9068fe | 1595 | case PROCESSOR_K1OM: |
76bc74dc | 1596 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1597 | case PROCESSOR_K6: |
1598 | case PROCESSOR_ATHLON: | |
1599 | case PROCESSOR_K8: | |
4eed87de | 1600 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1601 | case PROCESSOR_BD: |
029f3522 | 1602 | case PROCESSOR_ZNVER: |
7b458c12 | 1603 | case PROCESSOR_BT: |
80b8656c | 1604 | patt = alt_patt; |
ccc9c027 | 1605 | break; |
76bc74dc | 1606 | case PROCESSOR_I386: |
ccc9c027 L |
1607 | case PROCESSOR_I486: |
1608 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1609 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1610 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1611 | case PROCESSOR_GENERIC32: |
1612 | patt = f32_patt; | |
1613 | break; | |
4eed87de | 1614 | } |
ccc9c027 L |
1615 | } |
1616 | else | |
1617 | { | |
fbf3f584 | 1618 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1619 | { |
1620 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1621 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1622 | PROCESSOR_UNKNOWN. */ |
1623 | abort (); | |
1624 | break; | |
1625 | ||
76bc74dc | 1626 | case PROCESSOR_I386: |
ccc9c027 L |
1627 | case PROCESSOR_I486: |
1628 | case PROCESSOR_PENTIUM: | |
81486035 | 1629 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1630 | case PROCESSOR_K6: |
1631 | case PROCESSOR_ATHLON: | |
1632 | case PROCESSOR_K8: | |
4eed87de | 1633 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1634 | case PROCESSOR_BD: |
029f3522 | 1635 | case PROCESSOR_ZNVER: |
7b458c12 | 1636 | case PROCESSOR_BT: |
ccc9c027 L |
1637 | case PROCESSOR_GENERIC32: |
1638 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1639 | with nops. */ |
1640 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1641 | patt = alt_patt; |
ccc9c027 L |
1642 | else |
1643 | patt = f32_patt; | |
1644 | break; | |
76bc74dc L |
1645 | case PROCESSOR_PENTIUMPRO: |
1646 | case PROCESSOR_PENTIUM4: | |
1647 | case PROCESSOR_NOCONA: | |
1648 | case PROCESSOR_CORE: | |
ef05d495 | 1649 | case PROCESSOR_CORE2: |
bd5295b2 | 1650 | case PROCESSOR_COREI7: |
3632d14b | 1651 | case PROCESSOR_L1OM: |
7a9068fe | 1652 | case PROCESSOR_K1OM: |
22109423 | 1653 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1654 | patt = alt_patt; |
ccc9c027 L |
1655 | else |
1656 | patt = f32_patt; | |
1657 | break; | |
1658 | case PROCESSOR_GENERIC64: | |
80b8656c | 1659 | patt = alt_patt; |
ccc9c027 | 1660 | break; |
4eed87de | 1661 | } |
ccc9c027 L |
1662 | } |
1663 | ||
76bc74dc L |
1664 | if (patt == f32_patt) |
1665 | { | |
3ae729d5 L |
1666 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1667 | /* Limit number of NOPs to 2 for older processors. */ | |
1668 | max_number_of_nops = 2; | |
76bc74dc L |
1669 | } |
1670 | else | |
1671 | { | |
3ae729d5 L |
1672 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1673 | /* Limit number of NOPs to 7 for newer processors. */ | |
1674 | max_number_of_nops = 7; | |
1675 | } | |
1676 | } | |
1677 | ||
1678 | if (limit == 0) | |
1679 | limit = max_single_nop_size; | |
1680 | ||
1681 | if (fragP->fr_type == rs_fill_nop) | |
1682 | { | |
1683 | /* Output NOPs for .nop directive. */ | |
1684 | if (limit > max_single_nop_size) | |
1685 | { | |
1686 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1687 | _("invalid single nop size: %d " | |
1688 | "(expect within [0, %d])"), | |
1689 | limit, max_single_nop_size); | |
1690 | return; | |
1691 | } | |
1692 | } | |
e379e5f3 | 1693 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1694 | fragP->fr_var = count; |
1695 | ||
1696 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1697 | { | |
1698 | /* Generate jump over NOPs. */ | |
1699 | offsetT disp = count - 2; | |
1700 | if (fits_in_imm7 (disp)) | |
1701 | { | |
1702 | /* Use "jmp disp8" if possible. */ | |
1703 | count = disp; | |
1704 | where[0] = jump_disp8[0]; | |
1705 | where[1] = count; | |
1706 | where += 2; | |
1707 | } | |
1708 | else | |
1709 | { | |
1710 | unsigned int size_of_jump; | |
1711 | ||
1712 | if (flag_code == CODE_16BIT) | |
1713 | { | |
1714 | where[0] = jump16_disp32[0]; | |
1715 | where[1] = jump16_disp32[1]; | |
1716 | size_of_jump = 2; | |
1717 | } | |
1718 | else | |
1719 | { | |
1720 | where[0] = jump32_disp32[0]; | |
1721 | size_of_jump = 1; | |
1722 | } | |
1723 | ||
1724 | count -= size_of_jump + 4; | |
1725 | if (!fits_in_imm31 (count)) | |
1726 | { | |
1727 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1728 | _("jump over nop padding out of range")); | |
1729 | return; | |
1730 | } | |
1731 | ||
1732 | md_number_to_chars (where + size_of_jump, count, 4); | |
1733 | where += size_of_jump + 4; | |
76bc74dc | 1734 | } |
ccc9c027 | 1735 | } |
3ae729d5 L |
1736 | |
1737 | /* Generate multiple NOPs. */ | |
1738 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1739 | } |
1740 | ||
c6fb90c8 | 1741 | static INLINE int |
0dfbf9d7 | 1742 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1743 | { |
0dfbf9d7 | 1744 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1745 | { |
1746 | case 3: | |
0dfbf9d7 | 1747 | if (x->array[2]) |
c6fb90c8 | 1748 | return 0; |
1a0670f3 | 1749 | /* Fall through. */ |
c6fb90c8 | 1750 | case 2: |
0dfbf9d7 | 1751 | if (x->array[1]) |
c6fb90c8 | 1752 | return 0; |
1a0670f3 | 1753 | /* Fall through. */ |
c6fb90c8 | 1754 | case 1: |
0dfbf9d7 | 1755 | return !x->array[0]; |
c6fb90c8 L |
1756 | default: |
1757 | abort (); | |
1758 | } | |
40fb9820 L |
1759 | } |
1760 | ||
c6fb90c8 | 1761 | static INLINE void |
0dfbf9d7 | 1762 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1763 | { |
0dfbf9d7 | 1764 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1765 | { |
1766 | case 3: | |
0dfbf9d7 | 1767 | x->array[2] = v; |
1a0670f3 | 1768 | /* Fall through. */ |
c6fb90c8 | 1769 | case 2: |
0dfbf9d7 | 1770 | x->array[1] = v; |
1a0670f3 | 1771 | /* Fall through. */ |
c6fb90c8 | 1772 | case 1: |
0dfbf9d7 | 1773 | x->array[0] = v; |
1a0670f3 | 1774 | /* Fall through. */ |
c6fb90c8 L |
1775 | break; |
1776 | default: | |
1777 | abort (); | |
1778 | } | |
bab6aec1 JB |
1779 | |
1780 | x->bitfield.class = ClassNone; | |
75e5731b | 1781 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1782 | } |
40fb9820 | 1783 | |
c6fb90c8 | 1784 | static INLINE int |
0dfbf9d7 L |
1785 | operand_type_equal (const union i386_operand_type *x, |
1786 | const union i386_operand_type *y) | |
c6fb90c8 | 1787 | { |
0dfbf9d7 | 1788 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1789 | { |
1790 | case 3: | |
0dfbf9d7 | 1791 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1792 | return 0; |
1a0670f3 | 1793 | /* Fall through. */ |
c6fb90c8 | 1794 | case 2: |
0dfbf9d7 | 1795 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1796 | return 0; |
1a0670f3 | 1797 | /* Fall through. */ |
c6fb90c8 | 1798 | case 1: |
0dfbf9d7 | 1799 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1800 | break; |
1801 | default: | |
1802 | abort (); | |
1803 | } | |
1804 | } | |
40fb9820 | 1805 | |
0dfbf9d7 L |
1806 | static INLINE int |
1807 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1808 | { | |
1809 | switch (ARRAY_SIZE(x->array)) | |
1810 | { | |
53467f57 IT |
1811 | case 4: |
1812 | if (x->array[3]) | |
1813 | return 0; | |
1814 | /* Fall through. */ | |
0dfbf9d7 L |
1815 | case 3: |
1816 | if (x->array[2]) | |
1817 | return 0; | |
1a0670f3 | 1818 | /* Fall through. */ |
0dfbf9d7 L |
1819 | case 2: |
1820 | if (x->array[1]) | |
1821 | return 0; | |
1a0670f3 | 1822 | /* Fall through. */ |
0dfbf9d7 L |
1823 | case 1: |
1824 | return !x->array[0]; | |
1825 | default: | |
1826 | abort (); | |
1827 | } | |
1828 | } | |
1829 | ||
0dfbf9d7 L |
1830 | static INLINE int |
1831 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1832 | const union i386_cpu_flags *y) | |
1833 | { | |
1834 | switch (ARRAY_SIZE(x->array)) | |
1835 | { | |
53467f57 IT |
1836 | case 4: |
1837 | if (x->array[3] != y->array[3]) | |
1838 | return 0; | |
1839 | /* Fall through. */ | |
0dfbf9d7 L |
1840 | case 3: |
1841 | if (x->array[2] != y->array[2]) | |
1842 | return 0; | |
1a0670f3 | 1843 | /* Fall through. */ |
0dfbf9d7 L |
1844 | case 2: |
1845 | if (x->array[1] != y->array[1]) | |
1846 | return 0; | |
1a0670f3 | 1847 | /* Fall through. */ |
0dfbf9d7 L |
1848 | case 1: |
1849 | return x->array[0] == y->array[0]; | |
1850 | break; | |
1851 | default: | |
1852 | abort (); | |
1853 | } | |
1854 | } | |
c6fb90c8 L |
1855 | |
1856 | static INLINE int | |
1857 | cpu_flags_check_cpu64 (i386_cpu_flags f) | |
1858 | { | |
1859 | return !((flag_code == CODE_64BIT && f.bitfield.cpuno64) | |
1860 | || (flag_code != CODE_64BIT && f.bitfield.cpu64)); | |
40fb9820 L |
1861 | } |
1862 | ||
c6fb90c8 L |
1863 | static INLINE i386_cpu_flags |
1864 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1865 | { |
c6fb90c8 L |
1866 | switch (ARRAY_SIZE (x.array)) |
1867 | { | |
53467f57 IT |
1868 | case 4: |
1869 | x.array [3] &= y.array [3]; | |
1870 | /* Fall through. */ | |
c6fb90c8 L |
1871 | case 3: |
1872 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1873 | /* Fall through. */ |
c6fb90c8 L |
1874 | case 2: |
1875 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1876 | /* Fall through. */ |
c6fb90c8 L |
1877 | case 1: |
1878 | x.array [0] &= y.array [0]; | |
1879 | break; | |
1880 | default: | |
1881 | abort (); | |
1882 | } | |
1883 | return x; | |
1884 | } | |
40fb9820 | 1885 | |
c6fb90c8 L |
1886 | static INLINE i386_cpu_flags |
1887 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1888 | { |
c6fb90c8 | 1889 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1890 | { |
53467f57 IT |
1891 | case 4: |
1892 | x.array [3] |= y.array [3]; | |
1893 | /* Fall through. */ | |
c6fb90c8 L |
1894 | case 3: |
1895 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1896 | /* Fall through. */ |
c6fb90c8 L |
1897 | case 2: |
1898 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1899 | /* Fall through. */ |
c6fb90c8 L |
1900 | case 1: |
1901 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1902 | break; |
1903 | default: | |
1904 | abort (); | |
1905 | } | |
40fb9820 L |
1906 | return x; |
1907 | } | |
1908 | ||
309d3373 JB |
1909 | static INLINE i386_cpu_flags |
1910 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1911 | { | |
1912 | switch (ARRAY_SIZE (x.array)) | |
1913 | { | |
53467f57 IT |
1914 | case 4: |
1915 | x.array [3] &= ~y.array [3]; | |
1916 | /* Fall through. */ | |
309d3373 JB |
1917 | case 3: |
1918 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1919 | /* Fall through. */ |
309d3373 JB |
1920 | case 2: |
1921 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1922 | /* Fall through. */ |
309d3373 JB |
1923 | case 1: |
1924 | x.array [0] &= ~y.array [0]; | |
1925 | break; | |
1926 | default: | |
1927 | abort (); | |
1928 | } | |
1929 | return x; | |
1930 | } | |
1931 | ||
6c0946d0 JB |
1932 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1933 | ||
c0f3af97 L |
1934 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1935 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1936 | ||
c0f3af97 | 1937 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1938 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1939 | |
1940 | /* Return CPU flags match bits. */ | |
3629bb00 | 1941 | |
40fb9820 | 1942 | static int |
d3ce72d0 | 1943 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1944 | { |
c0f3af97 L |
1945 | i386_cpu_flags x = t->cpu_flags; |
1946 | int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0; | |
40fb9820 L |
1947 | |
1948 | x.bitfield.cpu64 = 0; | |
1949 | x.bitfield.cpuno64 = 0; | |
1950 | ||
0dfbf9d7 | 1951 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1952 | { |
1953 | /* This instruction is available on all archs. */ | |
db12e14e | 1954 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1955 | } |
3629bb00 L |
1956 | else |
1957 | { | |
c0f3af97 | 1958 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1959 | i386_cpu_flags cpu = cpu_arch_flags; |
1960 | ||
ab592e75 JB |
1961 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1962 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1963 | return match; | |
1964 | x.bitfield.cpuavx512vl = 0; | |
1965 | ||
3629bb00 | 1966 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1967 | if (!cpu_flags_all_zero (&cpu)) |
1968 | { | |
57392598 | 1969 | if (x.bitfield.cpuavx) |
a5ff0eb2 | 1970 | { |
929f69fa | 1971 | /* We need to check a few extra flags with AVX. */ |
b9d49817 | 1972 | if (cpu.bitfield.cpuavx |
40d231b4 JB |
1973 | && (!t->opcode_modifier.sse2avx |
1974 | || (sse2avx && !i.prefix[DATA_PREFIX])) | |
b9d49817 | 1975 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
929f69fa | 1976 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
b9d49817 JB |
1977 | && (!x.bitfield.cpupclmul || cpu.bitfield.cpupclmul)) |
1978 | match |= CPU_FLAGS_ARCH_MATCH; | |
a5ff0eb2 | 1979 | } |
929f69fa JB |
1980 | else if (x.bitfield.cpuavx512f) |
1981 | { | |
1982 | /* We need to check a few extra flags with AVX512F. */ | |
1983 | if (cpu.bitfield.cpuavx512f | |
1984 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1985 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1986 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1987 | match |= CPU_FLAGS_ARCH_MATCH; | |
1988 | } | |
a5ff0eb2 | 1989 | else |
db12e14e | 1990 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1991 | } |
3629bb00 | 1992 | } |
c0f3af97 | 1993 | return match; |
40fb9820 L |
1994 | } |
1995 | ||
c6fb90c8 L |
1996 | static INLINE i386_operand_type |
1997 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1998 | { |
bab6aec1 JB |
1999 | if (x.bitfield.class != y.bitfield.class) |
2000 | x.bitfield.class = ClassNone; | |
75e5731b JB |
2001 | if (x.bitfield.instance != y.bitfield.instance) |
2002 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 2003 | |
c6fb90c8 L |
2004 | switch (ARRAY_SIZE (x.array)) |
2005 | { | |
2006 | case 3: | |
2007 | x.array [2] &= y.array [2]; | |
1a0670f3 | 2008 | /* Fall through. */ |
c6fb90c8 L |
2009 | case 2: |
2010 | x.array [1] &= y.array [1]; | |
1a0670f3 | 2011 | /* Fall through. */ |
c6fb90c8 L |
2012 | case 1: |
2013 | x.array [0] &= y.array [0]; | |
2014 | break; | |
2015 | default: | |
2016 | abort (); | |
2017 | } | |
2018 | return x; | |
40fb9820 L |
2019 | } |
2020 | ||
73053c1f JB |
2021 | static INLINE i386_operand_type |
2022 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
2023 | { | |
bab6aec1 | 2024 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2025 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2026 | |
73053c1f JB |
2027 | switch (ARRAY_SIZE (x.array)) |
2028 | { | |
2029 | case 3: | |
2030 | x.array [2] &= ~y.array [2]; | |
2031 | /* Fall through. */ | |
2032 | case 2: | |
2033 | x.array [1] &= ~y.array [1]; | |
2034 | /* Fall through. */ | |
2035 | case 1: | |
2036 | x.array [0] &= ~y.array [0]; | |
2037 | break; | |
2038 | default: | |
2039 | abort (); | |
2040 | } | |
2041 | return x; | |
2042 | } | |
2043 | ||
c6fb90c8 L |
2044 | static INLINE i386_operand_type |
2045 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 2046 | { |
bab6aec1 JB |
2047 | gas_assert (x.bitfield.class == ClassNone || |
2048 | y.bitfield.class == ClassNone || | |
2049 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
2050 | gas_assert (x.bitfield.instance == InstanceNone || |
2051 | y.bitfield.instance == InstanceNone || | |
2052 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2053 | |
c6fb90c8 | 2054 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2055 | { |
c6fb90c8 L |
2056 | case 3: |
2057 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2058 | /* Fall through. */ |
c6fb90c8 L |
2059 | case 2: |
2060 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2061 | /* Fall through. */ |
c6fb90c8 L |
2062 | case 1: |
2063 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2064 | break; |
2065 | default: | |
2066 | abort (); | |
2067 | } | |
c6fb90c8 L |
2068 | return x; |
2069 | } | |
40fb9820 | 2070 | |
c6fb90c8 L |
2071 | static INLINE i386_operand_type |
2072 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2073 | { | |
bab6aec1 | 2074 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2075 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2076 | |
c6fb90c8 L |
2077 | switch (ARRAY_SIZE (x.array)) |
2078 | { | |
2079 | case 3: | |
2080 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2081 | /* Fall through. */ |
c6fb90c8 L |
2082 | case 2: |
2083 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2084 | /* Fall through. */ |
c6fb90c8 L |
2085 | case 1: |
2086 | x.array [0] ^= y.array [0]; | |
2087 | break; | |
2088 | default: | |
2089 | abort (); | |
2090 | } | |
40fb9820 L |
2091 | return x; |
2092 | } | |
2093 | ||
40fb9820 L |
2094 | static const i386_operand_type disp16 = OPERAND_TYPE_DISP16; |
2095 | static const i386_operand_type disp32 = OPERAND_TYPE_DISP32; | |
2096 | static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S; | |
2097 | static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32; | |
bab6aec1 JB |
2098 | static const i386_operand_type anydisp = OPERAND_TYPE_ANYDISP; |
2099 | static const i386_operand_type anyimm = OPERAND_TYPE_ANYIMM; | |
40fb9820 | 2100 | static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM; |
43234a1e | 2101 | static const i386_operand_type regmask = OPERAND_TYPE_REGMASK; |
40fb9820 L |
2102 | static const i386_operand_type imm8 = OPERAND_TYPE_IMM8; |
2103 | static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S; | |
2104 | static const i386_operand_type imm16 = OPERAND_TYPE_IMM16; | |
2105 | static const i386_operand_type imm32 = OPERAND_TYPE_IMM32; | |
2106 | static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S; | |
2107 | static const i386_operand_type imm64 = OPERAND_TYPE_IMM64; | |
2108 | static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32; | |
2109 | static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; | |
2110 | static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; | |
2111 | ||
2112 | enum operand_type | |
2113 | { | |
2114 | reg, | |
40fb9820 L |
2115 | imm, |
2116 | disp, | |
2117 | anymem | |
2118 | }; | |
2119 | ||
c6fb90c8 | 2120 | static INLINE int |
40fb9820 L |
2121 | operand_type_check (i386_operand_type t, enum operand_type c) |
2122 | { | |
2123 | switch (c) | |
2124 | { | |
2125 | case reg: | |
bab6aec1 | 2126 | return t.bitfield.class == Reg; |
40fb9820 | 2127 | |
40fb9820 L |
2128 | case imm: |
2129 | return (t.bitfield.imm8 | |
2130 | || t.bitfield.imm8s | |
2131 | || t.bitfield.imm16 | |
2132 | || t.bitfield.imm32 | |
2133 | || t.bitfield.imm32s | |
2134 | || t.bitfield.imm64); | |
2135 | ||
2136 | case disp: | |
2137 | return (t.bitfield.disp8 | |
2138 | || t.bitfield.disp16 | |
2139 | || t.bitfield.disp32 | |
2140 | || t.bitfield.disp32s | |
2141 | || t.bitfield.disp64); | |
2142 | ||
2143 | case anymem: | |
2144 | return (t.bitfield.disp8 | |
2145 | || t.bitfield.disp16 | |
2146 | || t.bitfield.disp32 | |
2147 | || t.bitfield.disp32s | |
2148 | || t.bitfield.disp64 | |
2149 | || t.bitfield.baseindex); | |
2150 | ||
2151 | default: | |
2152 | abort (); | |
2153 | } | |
2cfe26b6 AM |
2154 | |
2155 | return 0; | |
40fb9820 L |
2156 | } |
2157 | ||
7a54636a L |
2158 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2159 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2160 | |
2161 | static INLINE int | |
7a54636a L |
2162 | match_operand_size (const insn_template *t, unsigned int wanted, |
2163 | unsigned int given) | |
5c07affc | 2164 | { |
3ac21baa JB |
2165 | return !((i.types[given].bitfield.byte |
2166 | && !t->operand_types[wanted].bitfield.byte) | |
2167 | || (i.types[given].bitfield.word | |
2168 | && !t->operand_types[wanted].bitfield.word) | |
2169 | || (i.types[given].bitfield.dword | |
2170 | && !t->operand_types[wanted].bitfield.dword) | |
2171 | || (i.types[given].bitfield.qword | |
2172 | && !t->operand_types[wanted].bitfield.qword) | |
2173 | || (i.types[given].bitfield.tbyte | |
2174 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2175 | } |
2176 | ||
dd40ce22 L |
2177 | /* Return 1 if there is no conflict in SIMD register between operand |
2178 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2179 | |
2180 | static INLINE int | |
dd40ce22 L |
2181 | match_simd_size (const insn_template *t, unsigned int wanted, |
2182 | unsigned int given) | |
1b54b8d7 | 2183 | { |
3ac21baa JB |
2184 | return !((i.types[given].bitfield.xmmword |
2185 | && !t->operand_types[wanted].bitfield.xmmword) | |
2186 | || (i.types[given].bitfield.ymmword | |
2187 | && !t->operand_types[wanted].bitfield.ymmword) | |
2188 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2189 | && !t->operand_types[wanted].bitfield.zmmword) |
2190 | || (i.types[given].bitfield.tmmword | |
2191 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2192 | } |
2193 | ||
7a54636a L |
2194 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2195 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2196 | |
2197 | static INLINE int | |
dd40ce22 L |
2198 | match_mem_size (const insn_template *t, unsigned int wanted, |
2199 | unsigned int given) | |
5c07affc | 2200 | { |
7a54636a | 2201 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2202 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2203 | && !i.broadcast.type |
3ac21baa JB |
2204 | && !t->operand_types[wanted].bitfield.unspecified) |
2205 | || (i.types[given].bitfield.fword | |
2206 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2207 | /* For scalar opcode templates to allow register and memory |
2208 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2209 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2210 | down-conversion vpmov*. */ | |
3528c362 | 2211 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2212 | && t->operand_types[wanted].bitfield.byte |
2213 | + t->operand_types[wanted].bitfield.word | |
2214 | + t->operand_types[wanted].bitfield.dword | |
2215 | + t->operand_types[wanted].bitfield.qword | |
2216 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2217 | ? (i.types[given].bitfield.xmmword |
2218 | || i.types[given].bitfield.ymmword | |
2219 | || i.types[given].bitfield.zmmword) | |
2220 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2221 | } |
2222 | ||
3ac21baa JB |
2223 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2224 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2225 | is no size conflict on any operands for the template with operands reversed | |
2226 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2227 | |
3ac21baa JB |
2228 | #define MATCH_STRAIGHT 1 |
2229 | #define MATCH_REVERSE 2 | |
2230 | ||
2231 | static INLINE unsigned int | |
d3ce72d0 | 2232 | operand_size_match (const insn_template *t) |
5c07affc | 2233 | { |
3ac21baa | 2234 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2235 | |
0cfa3eb3 | 2236 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2237 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2238 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2239 | return match; |
2240 | ||
2241 | /* Check memory and accumulator operand size. */ | |
2242 | for (j = 0; j < i.operands; j++) | |
2243 | { | |
3528c362 JB |
2244 | if (i.types[j].bitfield.class != Reg |
2245 | && i.types[j].bitfield.class != RegSIMD | |
601e8564 | 2246 | && t->opcode_modifier.anysize) |
5c07affc L |
2247 | continue; |
2248 | ||
bab6aec1 | 2249 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2250 | && !match_operand_size (t, j, j)) |
5c07affc L |
2251 | { |
2252 | match = 0; | |
2253 | break; | |
2254 | } | |
2255 | ||
3528c362 | 2256 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2257 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2258 | { |
2259 | match = 0; | |
2260 | break; | |
2261 | } | |
2262 | ||
75e5731b | 2263 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2264 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2265 | { |
2266 | match = 0; | |
2267 | break; | |
2268 | } | |
2269 | ||
c48dadc9 | 2270 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2271 | { |
2272 | match = 0; | |
2273 | break; | |
2274 | } | |
2275 | } | |
2276 | ||
3ac21baa | 2277 | if (!t->opcode_modifier.d) |
891edac4 | 2278 | { |
dc1e8a47 | 2279 | mismatch: |
3ac21baa JB |
2280 | if (!match) |
2281 | i.error = operand_size_mismatch; | |
2282 | return match; | |
891edac4 | 2283 | } |
5c07affc L |
2284 | |
2285 | /* Check reverse. */ | |
f5eb1d70 | 2286 | gas_assert (i.operands >= 2 && i.operands <= 3); |
5c07affc | 2287 | |
f5eb1d70 | 2288 | for (j = 0; j < i.operands; j++) |
5c07affc | 2289 | { |
f5eb1d70 JB |
2290 | unsigned int given = i.operands - j - 1; |
2291 | ||
bab6aec1 | 2292 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2293 | && !match_operand_size (t, j, given)) |
891edac4 | 2294 | goto mismatch; |
5c07affc | 2295 | |
3528c362 | 2296 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2297 | && !match_simd_size (t, j, given)) |
dbbc8b7e JB |
2298 | goto mismatch; |
2299 | ||
75e5731b | 2300 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2301 | && (!match_operand_size (t, j, given) |
2302 | || !match_simd_size (t, j, given))) | |
dbbc8b7e JB |
2303 | goto mismatch; |
2304 | ||
f5eb1d70 | 2305 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
891edac4 | 2306 | goto mismatch; |
5c07affc L |
2307 | } |
2308 | ||
3ac21baa | 2309 | return match | MATCH_REVERSE; |
5c07affc L |
2310 | } |
2311 | ||
c6fb90c8 | 2312 | static INLINE int |
40fb9820 L |
2313 | operand_type_match (i386_operand_type overlap, |
2314 | i386_operand_type given) | |
2315 | { | |
2316 | i386_operand_type temp = overlap; | |
2317 | ||
7d5e4556 | 2318 | temp.bitfield.unspecified = 0; |
5c07affc L |
2319 | temp.bitfield.byte = 0; |
2320 | temp.bitfield.word = 0; | |
2321 | temp.bitfield.dword = 0; | |
2322 | temp.bitfield.fword = 0; | |
2323 | temp.bitfield.qword = 0; | |
2324 | temp.bitfield.tbyte = 0; | |
2325 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2326 | temp.bitfield.ymmword = 0; |
43234a1e | 2327 | temp.bitfield.zmmword = 0; |
260cd341 | 2328 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2329 | if (operand_type_all_zero (&temp)) |
891edac4 | 2330 | goto mismatch; |
40fb9820 | 2331 | |
6f2f06be | 2332 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2333 | return 1; |
2334 | ||
dc1e8a47 | 2335 | mismatch: |
a65babc9 | 2336 | i.error = operand_type_mismatch; |
891edac4 | 2337 | return 0; |
40fb9820 L |
2338 | } |
2339 | ||
7d5e4556 | 2340 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2341 | unless the expected operand type register overlap is null. |
5de4d9ef | 2342 | Some Intel syntax memory operand size checking also happens here. */ |
40fb9820 | 2343 | |
c6fb90c8 | 2344 | static INLINE int |
dc821c5f | 2345 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2346 | i386_operand_type t0, |
40fb9820 L |
2347 | i386_operand_type g1, |
2348 | i386_operand_type t1) | |
2349 | { | |
bab6aec1 | 2350 | if (g0.bitfield.class != Reg |
3528c362 | 2351 | && g0.bitfield.class != RegSIMD |
10c17abd JB |
2352 | && (!operand_type_check (g0, anymem) |
2353 | || g0.bitfield.unspecified | |
5de4d9ef JB |
2354 | || (t0.bitfield.class != Reg |
2355 | && t0.bitfield.class != RegSIMD))) | |
40fb9820 L |
2356 | return 1; |
2357 | ||
bab6aec1 | 2358 | if (g1.bitfield.class != Reg |
3528c362 | 2359 | && g1.bitfield.class != RegSIMD |
10c17abd JB |
2360 | && (!operand_type_check (g1, anymem) |
2361 | || g1.bitfield.unspecified | |
5de4d9ef JB |
2362 | || (t1.bitfield.class != Reg |
2363 | && t1.bitfield.class != RegSIMD))) | |
40fb9820 L |
2364 | return 1; |
2365 | ||
dc821c5f JB |
2366 | if (g0.bitfield.byte == g1.bitfield.byte |
2367 | && g0.bitfield.word == g1.bitfield.word | |
2368 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2369 | && g0.bitfield.qword == g1.bitfield.qword |
2370 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2371 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2372 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2373 | return 1; |
2374 | ||
dc821c5f JB |
2375 | if (!(t0.bitfield.byte & t1.bitfield.byte) |
2376 | && !(t0.bitfield.word & t1.bitfield.word) | |
2377 | && !(t0.bitfield.dword & t1.bitfield.dword) | |
10c17abd JB |
2378 | && !(t0.bitfield.qword & t1.bitfield.qword) |
2379 | && !(t0.bitfield.xmmword & t1.bitfield.xmmword) | |
2380 | && !(t0.bitfield.ymmword & t1.bitfield.ymmword) | |
2381 | && !(t0.bitfield.zmmword & t1.bitfield.zmmword)) | |
891edac4 L |
2382 | return 1; |
2383 | ||
a65babc9 | 2384 | i.error = register_type_mismatch; |
891edac4 L |
2385 | |
2386 | return 0; | |
40fb9820 L |
2387 | } |
2388 | ||
4c692bc7 JB |
2389 | static INLINE unsigned int |
2390 | register_number (const reg_entry *r) | |
2391 | { | |
2392 | unsigned int nr = r->reg_num; | |
2393 | ||
2394 | if (r->reg_flags & RegRex) | |
2395 | nr += 8; | |
2396 | ||
200cbe0f L |
2397 | if (r->reg_flags & RegVRex) |
2398 | nr += 16; | |
2399 | ||
4c692bc7 JB |
2400 | return nr; |
2401 | } | |
2402 | ||
252b5132 | 2403 | static INLINE unsigned int |
40fb9820 | 2404 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2405 | { |
b5014f7a | 2406 | if (t.bitfield.disp8) |
40fb9820 L |
2407 | return 1; |
2408 | else if (t.bitfield.disp16 | |
2409 | || t.bitfield.disp32 | |
2410 | || t.bitfield.disp32s) | |
2411 | return 2; | |
2412 | else | |
2413 | return 0; | |
252b5132 RH |
2414 | } |
2415 | ||
2416 | static INLINE int | |
65879393 | 2417 | fits_in_signed_byte (addressT num) |
252b5132 | 2418 | { |
65879393 | 2419 | return num + 0x80 <= 0xff; |
47926f60 | 2420 | } |
252b5132 RH |
2421 | |
2422 | static INLINE int | |
65879393 | 2423 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2424 | { |
65879393 | 2425 | return num <= 0xff; |
47926f60 | 2426 | } |
252b5132 RH |
2427 | |
2428 | static INLINE int | |
65879393 | 2429 | fits_in_unsigned_word (addressT num) |
252b5132 | 2430 | { |
65879393 | 2431 | return num <= 0xffff; |
47926f60 | 2432 | } |
252b5132 RH |
2433 | |
2434 | static INLINE int | |
65879393 | 2435 | fits_in_signed_word (addressT num) |
252b5132 | 2436 | { |
65879393 | 2437 | return num + 0x8000 <= 0xffff; |
47926f60 | 2438 | } |
2a962e6d | 2439 | |
3e73aa7c | 2440 | static INLINE int |
65879393 | 2441 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2442 | { |
2443 | #ifndef BFD64 | |
2444 | return 1; | |
2445 | #else | |
65879393 | 2446 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2447 | #endif |
2448 | } /* fits_in_signed_long() */ | |
2a962e6d | 2449 | |
3e73aa7c | 2450 | static INLINE int |
65879393 | 2451 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2452 | { |
2453 | #ifndef BFD64 | |
2454 | return 1; | |
2455 | #else | |
65879393 | 2456 | return num <= 0xffffffff; |
3e73aa7c JH |
2457 | #endif |
2458 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2459 | |
43234a1e | 2460 | static INLINE int |
b5014f7a | 2461 | fits_in_disp8 (offsetT num) |
43234a1e L |
2462 | { |
2463 | int shift = i.memshift; | |
2464 | unsigned int mask; | |
2465 | ||
2466 | if (shift == -1) | |
2467 | abort (); | |
2468 | ||
2469 | mask = (1 << shift) - 1; | |
2470 | ||
2471 | /* Return 0 if NUM isn't properly aligned. */ | |
2472 | if ((num & mask)) | |
2473 | return 0; | |
2474 | ||
2475 | /* Check if NUM will fit in 8bit after shift. */ | |
2476 | return fits_in_signed_byte (num >> shift); | |
2477 | } | |
2478 | ||
a683cc34 SP |
2479 | static INLINE int |
2480 | fits_in_imm4 (offsetT num) | |
2481 | { | |
2482 | return (num & 0xf) == num; | |
2483 | } | |
2484 | ||
40fb9820 | 2485 | static i386_operand_type |
e3bb37b5 | 2486 | smallest_imm_type (offsetT num) |
252b5132 | 2487 | { |
40fb9820 | 2488 | i386_operand_type t; |
7ab9ffdd | 2489 | |
0dfbf9d7 | 2490 | operand_type_set (&t, 0); |
40fb9820 L |
2491 | t.bitfield.imm64 = 1; |
2492 | ||
2493 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2494 | { |
2495 | /* This code is disabled on the 486 because all the Imm1 forms | |
2496 | in the opcode table are slower on the i486. They're the | |
2497 | versions with the implicitly specified single-position | |
2498 | displacement, which has another syntax if you really want to | |
2499 | use that form. */ | |
40fb9820 L |
2500 | t.bitfield.imm1 = 1; |
2501 | t.bitfield.imm8 = 1; | |
2502 | t.bitfield.imm8s = 1; | |
2503 | t.bitfield.imm16 = 1; | |
2504 | t.bitfield.imm32 = 1; | |
2505 | t.bitfield.imm32s = 1; | |
2506 | } | |
2507 | else if (fits_in_signed_byte (num)) | |
2508 | { | |
2509 | t.bitfield.imm8 = 1; | |
2510 | t.bitfield.imm8s = 1; | |
2511 | t.bitfield.imm16 = 1; | |
2512 | t.bitfield.imm32 = 1; | |
2513 | t.bitfield.imm32s = 1; | |
2514 | } | |
2515 | else if (fits_in_unsigned_byte (num)) | |
2516 | { | |
2517 | t.bitfield.imm8 = 1; | |
2518 | t.bitfield.imm16 = 1; | |
2519 | t.bitfield.imm32 = 1; | |
2520 | t.bitfield.imm32s = 1; | |
2521 | } | |
2522 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2523 | { | |
2524 | t.bitfield.imm16 = 1; | |
2525 | t.bitfield.imm32 = 1; | |
2526 | t.bitfield.imm32s = 1; | |
2527 | } | |
2528 | else if (fits_in_signed_long (num)) | |
2529 | { | |
2530 | t.bitfield.imm32 = 1; | |
2531 | t.bitfield.imm32s = 1; | |
2532 | } | |
2533 | else if (fits_in_unsigned_long (num)) | |
2534 | t.bitfield.imm32 = 1; | |
2535 | ||
2536 | return t; | |
47926f60 | 2537 | } |
252b5132 | 2538 | |
847f7ad4 | 2539 | static offsetT |
e3bb37b5 | 2540 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2541 | { |
508866be | 2542 | addressT mask; |
ba2adb93 | 2543 | |
847f7ad4 AM |
2544 | switch (size) |
2545 | { | |
508866be L |
2546 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2547 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3b0ec529 | 2548 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
3e73aa7c JH |
2549 | #ifdef BFD64 |
2550 | case 8: mask = ((addressT) 2 << 63) - 1; break; | |
2551 | #endif | |
47926f60 | 2552 | default: abort (); |
847f7ad4 AM |
2553 | } |
2554 | ||
47926f60 | 2555 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
847f7ad4 AM |
2556 | { |
2557 | char buf1[40], buf2[40]; | |
2558 | ||
9a8041fd JB |
2559 | bfd_sprintf_vma (stdoutput, buf1, val); |
2560 | bfd_sprintf_vma (stdoutput, buf2, val & mask); | |
847f7ad4 AM |
2561 | as_warn (_("%s shortened to %s"), buf1, buf2); |
2562 | } | |
2563 | return val & mask; | |
2564 | } | |
2565 | ||
c32fa91d L |
2566 | enum PREFIX_GROUP |
2567 | { | |
2568 | PREFIX_EXIST = 0, | |
2569 | PREFIX_LOCK, | |
2570 | PREFIX_REP, | |
04ef582a | 2571 | PREFIX_DS, |
c32fa91d L |
2572 | PREFIX_OTHER |
2573 | }; | |
2574 | ||
2575 | /* Returns | |
2576 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2577 | same class already exists. | |
2578 | b. PREFIX_LOCK if lock prefix is added. | |
2579 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2580 | d. PREFIX_DS if ds prefix is added. |
2581 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2582 | */ |
2583 | ||
2584 | static enum PREFIX_GROUP | |
e3bb37b5 | 2585 | add_prefix (unsigned int prefix) |
252b5132 | 2586 | { |
c32fa91d | 2587 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2588 | unsigned int q; |
252b5132 | 2589 | |
29b0f896 AM |
2590 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2591 | && flag_code == CODE_64BIT) | |
b1905489 | 2592 | { |
161a04f6 | 2593 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2594 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2595 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2596 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2597 | ret = PREFIX_EXIST; |
b1905489 JB |
2598 | q = REX_PREFIX; |
2599 | } | |
3e73aa7c | 2600 | else |
b1905489 JB |
2601 | { |
2602 | switch (prefix) | |
2603 | { | |
2604 | default: | |
2605 | abort (); | |
2606 | ||
b1905489 | 2607 | case DS_PREFIX_OPCODE: |
04ef582a L |
2608 | ret = PREFIX_DS; |
2609 | /* Fall through. */ | |
2610 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2611 | case ES_PREFIX_OPCODE: |
2612 | case FS_PREFIX_OPCODE: | |
2613 | case GS_PREFIX_OPCODE: | |
2614 | case SS_PREFIX_OPCODE: | |
2615 | q = SEG_PREFIX; | |
2616 | break; | |
2617 | ||
2618 | case REPNE_PREFIX_OPCODE: | |
2619 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2620 | q = REP_PREFIX; |
2621 | ret = PREFIX_REP; | |
2622 | break; | |
2623 | ||
b1905489 | 2624 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2625 | q = LOCK_PREFIX; |
2626 | ret = PREFIX_LOCK; | |
b1905489 JB |
2627 | break; |
2628 | ||
2629 | case FWAIT_OPCODE: | |
2630 | q = WAIT_PREFIX; | |
2631 | break; | |
2632 | ||
2633 | case ADDR_PREFIX_OPCODE: | |
2634 | q = ADDR_PREFIX; | |
2635 | break; | |
2636 | ||
2637 | case DATA_PREFIX_OPCODE: | |
2638 | q = DATA_PREFIX; | |
2639 | break; | |
2640 | } | |
2641 | if (i.prefix[q] != 0) | |
c32fa91d | 2642 | ret = PREFIX_EXIST; |
b1905489 | 2643 | } |
252b5132 | 2644 | |
b1905489 | 2645 | if (ret) |
252b5132 | 2646 | { |
b1905489 JB |
2647 | if (!i.prefix[q]) |
2648 | ++i.prefixes; | |
2649 | i.prefix[q] |= prefix; | |
252b5132 | 2650 | } |
b1905489 JB |
2651 | else |
2652 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2653 | |
252b5132 RH |
2654 | return ret; |
2655 | } | |
2656 | ||
2657 | static void | |
78f12dd3 | 2658 | update_code_flag (int value, int check) |
eecb386c | 2659 | { |
78f12dd3 L |
2660 | PRINTF_LIKE ((*as_error)); |
2661 | ||
1e9cc1c2 | 2662 | flag_code = (enum flag_code) value; |
40fb9820 L |
2663 | if (flag_code == CODE_64BIT) |
2664 | { | |
2665 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2666 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
40fb9820 L |
2667 | } |
2668 | else | |
2669 | { | |
2670 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2671 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
40fb9820 L |
2672 | } |
2673 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm ) | |
3e73aa7c | 2674 | { |
78f12dd3 L |
2675 | if (check) |
2676 | as_error = as_fatal; | |
2677 | else | |
2678 | as_error = as_bad; | |
2679 | (*as_error) (_("64bit mode not supported on `%s'."), | |
2680 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2681 | } |
40fb9820 | 2682 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) |
3e73aa7c | 2683 | { |
78f12dd3 L |
2684 | if (check) |
2685 | as_error = as_fatal; | |
2686 | else | |
2687 | as_error = as_bad; | |
2688 | (*as_error) (_("32bit mode not supported on `%s'."), | |
2689 | cpu_arch_name ? cpu_arch_name : default_arch); | |
3e73aa7c | 2690 | } |
eecb386c AM |
2691 | stackop_size = '\0'; |
2692 | } | |
2693 | ||
78f12dd3 L |
2694 | static void |
2695 | set_code_flag (int value) | |
2696 | { | |
2697 | update_code_flag (value, 0); | |
50c95a73 L |
2698 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2699 | if (value == CODE_16BIT) | |
2700 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_CODE16; | |
2701 | #endif | |
78f12dd3 L |
2702 | } |
2703 | ||
eecb386c | 2704 | static void |
e3bb37b5 | 2705 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2706 | { |
1e9cc1c2 | 2707 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2708 | if (flag_code != CODE_16BIT) |
2709 | abort (); | |
2710 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2711 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
9306ca4a | 2712 | stackop_size = LONG_MNEM_SUFFIX; |
50c95a73 L |
2713 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2714 | if (new_code_flag == CODE_16BIT) | |
2715 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_CODE16; | |
2716 | #endif | |
252b5132 RH |
2717 | } |
2718 | ||
2719 | static void | |
e3bb37b5 | 2720 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2721 | { |
2722 | /* Find out if register prefixing is specified. */ | |
2723 | int ask_naked_reg = 0; | |
2724 | ||
2725 | SKIP_WHITESPACE (); | |
29b0f896 | 2726 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2727 | { |
d02603dc NC |
2728 | char *string; |
2729 | int e = get_symbol_name (&string); | |
252b5132 | 2730 | |
47926f60 | 2731 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2732 | ask_naked_reg = 1; |
47926f60 | 2733 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2734 | ask_naked_reg = -1; |
2735 | else | |
d0b47220 | 2736 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2737 | (void) restore_line_pointer (e); |
252b5132 RH |
2738 | } |
2739 | demand_empty_rest_of_line (); | |
c3332e24 | 2740 | |
252b5132 RH |
2741 | intel_syntax = syntax_flag; |
2742 | ||
2743 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2744 | allow_naked_reg = (intel_syntax |
2745 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2746 | else |
2747 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2748 | |
ee86248c | 2749 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2750 | |
e4a3b5a4 | 2751 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
9306ca4a | 2752 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
e4a3b5a4 | 2753 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2754 | } |
2755 | ||
1efbbeb4 L |
2756 | static void |
2757 | set_intel_mnemonic (int mnemonic_flag) | |
2758 | { | |
e1d4d893 | 2759 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2760 | } |
2761 | ||
db51cc60 L |
2762 | static void |
2763 | set_allow_index_reg (int flag) | |
2764 | { | |
2765 | allow_index_reg = flag; | |
2766 | } | |
2767 | ||
cb19c032 | 2768 | static void |
7bab8ab5 | 2769 | set_check (int what) |
cb19c032 | 2770 | { |
7bab8ab5 JB |
2771 | enum check_kind *kind; |
2772 | const char *str; | |
2773 | ||
2774 | if (what) | |
2775 | { | |
2776 | kind = &operand_check; | |
2777 | str = "operand"; | |
2778 | } | |
2779 | else | |
2780 | { | |
2781 | kind = &sse_check; | |
2782 | str = "sse"; | |
2783 | } | |
2784 | ||
cb19c032 L |
2785 | SKIP_WHITESPACE (); |
2786 | ||
2787 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2788 | { | |
d02603dc NC |
2789 | char *string; |
2790 | int e = get_symbol_name (&string); | |
cb19c032 L |
2791 | |
2792 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2793 | *kind = check_none; |
cb19c032 | 2794 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2795 | *kind = check_warning; |
cb19c032 | 2796 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2797 | *kind = check_error; |
cb19c032 | 2798 | else |
7bab8ab5 | 2799 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2800 | (void) restore_line_pointer (e); |
cb19c032 L |
2801 | } |
2802 | else | |
7bab8ab5 | 2803 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2804 | |
2805 | demand_empty_rest_of_line (); | |
2806 | } | |
2807 | ||
8a9036a4 L |
2808 | static void |
2809 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2810 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2811 | { |
2812 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2813 | static const char *arch; | |
2814 | ||
2815 | /* Intel LIOM is only supported on ELF. */ | |
2816 | if (!IS_ELF) | |
2817 | return; | |
2818 | ||
2819 | if (!arch) | |
2820 | { | |
2821 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2822 | use default_arch. */ | |
2823 | arch = cpu_arch_name; | |
2824 | if (!arch) | |
2825 | arch = default_arch; | |
2826 | } | |
2827 | ||
81486035 L |
2828 | /* If we are targeting Intel MCU, we must enable it. */ |
2829 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_IAMCU | |
2830 | || new_flag.bitfield.cpuiamcu) | |
2831 | return; | |
2832 | ||
3632d14b | 2833 | /* If we are targeting Intel L1OM, we must enable it. */ |
8a9036a4 | 2834 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM |
1e9cc1c2 | 2835 | || new_flag.bitfield.cpul1om) |
8a9036a4 | 2836 | return; |
76ba9986 | 2837 | |
7a9068fe L |
2838 | /* If we are targeting Intel K1OM, we must enable it. */ |
2839 | if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM | |
2840 | || new_flag.bitfield.cpuk1om) | |
2841 | return; | |
2842 | ||
8a9036a4 L |
2843 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2844 | #endif | |
2845 | } | |
2846 | ||
e413e4e9 | 2847 | static void |
e3bb37b5 | 2848 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2849 | { |
47926f60 | 2850 | SKIP_WHITESPACE (); |
e413e4e9 | 2851 | |
29b0f896 | 2852 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
e413e4e9 | 2853 | { |
d02603dc NC |
2854 | char *string; |
2855 | int e = get_symbol_name (&string); | |
91d6fa6a | 2856 | unsigned int j; |
40fb9820 | 2857 | i386_cpu_flags flags; |
e413e4e9 | 2858 | |
91d6fa6a | 2859 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
e413e4e9 | 2860 | { |
91d6fa6a | 2861 | if (strcmp (string, cpu_arch[j].name) == 0) |
e413e4e9 | 2862 | { |
91d6fa6a | 2863 | check_cpu_arch_compatible (string, cpu_arch[j].flags); |
8a9036a4 | 2864 | |
5c6af06e JB |
2865 | if (*string != '.') |
2866 | { | |
91d6fa6a | 2867 | cpu_arch_name = cpu_arch[j].name; |
5c6af06e | 2868 | cpu_sub_arch_name = NULL; |
91d6fa6a | 2869 | cpu_arch_flags = cpu_arch[j].flags; |
40fb9820 L |
2870 | if (flag_code == CODE_64BIT) |
2871 | { | |
2872 | cpu_arch_flags.bitfield.cpu64 = 1; | |
2873 | cpu_arch_flags.bitfield.cpuno64 = 0; | |
2874 | } | |
2875 | else | |
2876 | { | |
2877 | cpu_arch_flags.bitfield.cpu64 = 0; | |
2878 | cpu_arch_flags.bitfield.cpuno64 = 1; | |
2879 | } | |
91d6fa6a NC |
2880 | cpu_arch_isa = cpu_arch[j].type; |
2881 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
ccc9c027 L |
2882 | if (!cpu_arch_tune_set) |
2883 | { | |
2884 | cpu_arch_tune = cpu_arch_isa; | |
2885 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2886 | } | |
5c6af06e JB |
2887 | break; |
2888 | } | |
40fb9820 | 2889 | |
293f5f65 L |
2890 | flags = cpu_flags_or (cpu_arch_flags, |
2891 | cpu_arch[j].flags); | |
81486035 | 2892 | |
5b64d091 | 2893 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
5c6af06e | 2894 | { |
6305a203 L |
2895 | if (cpu_sub_arch_name) |
2896 | { | |
2897 | char *name = cpu_sub_arch_name; | |
2898 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 2899 | cpu_arch[j].name, |
1bf57e9f | 2900 | (const char *) NULL); |
6305a203 L |
2901 | free (name); |
2902 | } | |
2903 | else | |
91d6fa6a | 2904 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
40fb9820 | 2905 | cpu_arch_flags = flags; |
a586129e | 2906 | cpu_arch_isa_flags = flags; |
5c6af06e | 2907 | } |
0089dace L |
2908 | else |
2909 | cpu_arch_isa_flags | |
2910 | = cpu_flags_or (cpu_arch_isa_flags, | |
2911 | cpu_arch[j].flags); | |
d02603dc | 2912 | (void) restore_line_pointer (e); |
5c6af06e JB |
2913 | demand_empty_rest_of_line (); |
2914 | return; | |
e413e4e9 AM |
2915 | } |
2916 | } | |
293f5f65 L |
2917 | |
2918 | if (*string == '.' && j >= ARRAY_SIZE (cpu_arch)) | |
2919 | { | |
33eaf5de | 2920 | /* Disable an ISA extension. */ |
293f5f65 L |
2921 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
2922 | if (strcmp (string + 1, cpu_noarch [j].name) == 0) | |
2923 | { | |
2924 | flags = cpu_flags_and_not (cpu_arch_flags, | |
2925 | cpu_noarch[j].flags); | |
2926 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
2927 | { | |
2928 | if (cpu_sub_arch_name) | |
2929 | { | |
2930 | char *name = cpu_sub_arch_name; | |
2931 | cpu_sub_arch_name = concat (name, string, | |
2932 | (const char *) NULL); | |
2933 | free (name); | |
2934 | } | |
2935 | else | |
2936 | cpu_sub_arch_name = xstrdup (string); | |
2937 | cpu_arch_flags = flags; | |
2938 | cpu_arch_isa_flags = flags; | |
2939 | } | |
2940 | (void) restore_line_pointer (e); | |
2941 | demand_empty_rest_of_line (); | |
2942 | return; | |
2943 | } | |
2944 | ||
2945 | j = ARRAY_SIZE (cpu_arch); | |
2946 | } | |
2947 | ||
91d6fa6a | 2948 | if (j >= ARRAY_SIZE (cpu_arch)) |
e413e4e9 AM |
2949 | as_bad (_("no such architecture: `%s'"), string); |
2950 | ||
2951 | *input_line_pointer = e; | |
2952 | } | |
2953 | else | |
2954 | as_bad (_("missing cpu architecture")); | |
2955 | ||
fddf5b5b AM |
2956 | no_cond_jump_promotion = 0; |
2957 | if (*input_line_pointer == ',' | |
29b0f896 | 2958 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 2959 | { |
d02603dc NC |
2960 | char *string; |
2961 | char e; | |
2962 | ||
2963 | ++input_line_pointer; | |
2964 | e = get_symbol_name (&string); | |
fddf5b5b AM |
2965 | |
2966 | if (strcmp (string, "nojumps") == 0) | |
2967 | no_cond_jump_promotion = 1; | |
2968 | else if (strcmp (string, "jumps") == 0) | |
2969 | ; | |
2970 | else | |
2971 | as_bad (_("no such architecture modifier: `%s'"), string); | |
2972 | ||
d02603dc | 2973 | (void) restore_line_pointer (e); |
fddf5b5b AM |
2974 | } |
2975 | ||
e413e4e9 AM |
2976 | demand_empty_rest_of_line (); |
2977 | } | |
2978 | ||
8a9036a4 L |
2979 | enum bfd_architecture |
2980 | i386_arch (void) | |
2981 | { | |
3632d14b | 2982 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 L |
2983 | { |
2984 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2985 | || flag_code != CODE_64BIT) | |
2986 | as_fatal (_("Intel L1OM is 64bit ELF only")); | |
2987 | return bfd_arch_l1om; | |
2988 | } | |
7a9068fe L |
2989 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
2990 | { | |
2991 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2992 | || flag_code != CODE_64BIT) | |
2993 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
2994 | return bfd_arch_k1om; | |
2995 | } | |
81486035 L |
2996 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
2997 | { | |
2998 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
2999 | || flag_code == CODE_64BIT) | |
3000 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3001 | return bfd_arch_iamcu; | |
3002 | } | |
8a9036a4 L |
3003 | else |
3004 | return bfd_arch_i386; | |
3005 | } | |
3006 | ||
b9d79e03 | 3007 | unsigned long |
7016a5d5 | 3008 | i386_mach (void) |
b9d79e03 | 3009 | { |
d34049e8 | 3010 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 3011 | { |
3632d14b | 3012 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 3013 | { |
351f65ca L |
3014 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour |
3015 | || default_arch[6] != '\0') | |
8a9036a4 L |
3016 | as_fatal (_("Intel L1OM is 64bit ELF only")); |
3017 | return bfd_mach_l1om; | |
3018 | } | |
7a9068fe L |
3019 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
3020 | { | |
3021 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3022 | || default_arch[6] != '\0') | |
3023 | as_fatal (_("Intel K1OM is 64bit ELF only")); | |
3024 | return bfd_mach_k1om; | |
3025 | } | |
351f65ca | 3026 | else if (default_arch[6] == '\0') |
8a9036a4 | 3027 | return bfd_mach_x86_64; |
351f65ca L |
3028 | else |
3029 | return bfd_mach_x64_32; | |
8a9036a4 | 3030 | } |
5197d474 L |
3031 | else if (!strcmp (default_arch, "i386") |
3032 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
3033 | { |
3034 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
3035 | { | |
3036 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
3037 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3038 | return bfd_mach_i386_iamcu; | |
3039 | } | |
3040 | else | |
3041 | return bfd_mach_i386_i386; | |
3042 | } | |
b9d79e03 | 3043 | else |
2b5d6a91 | 3044 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3045 | } |
b9d79e03 | 3046 | \f |
252b5132 | 3047 | void |
7016a5d5 | 3048 | md_begin (void) |
252b5132 | 3049 | { |
86fa6981 L |
3050 | /* Support pseudo prefixes like {disp32}. */ |
3051 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3052 | ||
47926f60 | 3053 | /* Initialize op_hash hash table. */ |
629310ab | 3054 | op_hash = str_htab_create (); |
252b5132 RH |
3055 | |
3056 | { | |
d3ce72d0 | 3057 | const insn_template *optab; |
29b0f896 | 3058 | templates *core_optab; |
252b5132 | 3059 | |
47926f60 KH |
3060 | /* Setup for loop. */ |
3061 | optab = i386_optab; | |
add39d23 | 3062 | core_optab = XNEW (templates); |
252b5132 RH |
3063 | core_optab->start = optab; |
3064 | ||
3065 | while (1) | |
3066 | { | |
3067 | ++optab; | |
3068 | if (optab->name == NULL | |
3069 | || strcmp (optab->name, (optab - 1)->name) != 0) | |
3070 | { | |
3071 | /* different name --> ship out current template list; | |
47926f60 | 3072 | add to hash table; & begin anew. */ |
252b5132 | 3073 | core_optab->end = optab; |
fe0e921f AM |
3074 | if (str_hash_insert (op_hash, (optab - 1)->name, core_optab, 0)) |
3075 | as_fatal (_("duplicate %s"), (optab - 1)->name); | |
3076 | ||
252b5132 RH |
3077 | if (optab->name == NULL) |
3078 | break; | |
add39d23 | 3079 | core_optab = XNEW (templates); |
252b5132 RH |
3080 | core_optab->start = optab; |
3081 | } | |
3082 | } | |
3083 | } | |
3084 | ||
47926f60 | 3085 | /* Initialize reg_hash hash table. */ |
629310ab | 3086 | reg_hash = str_htab_create (); |
252b5132 | 3087 | { |
29b0f896 | 3088 | const reg_entry *regtab; |
c3fe08fa | 3089 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3090 | |
c3fe08fa | 3091 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 3092 | { |
6288d05f JB |
3093 | switch (regtab->reg_type.bitfield.class) |
3094 | { | |
3095 | case Reg: | |
34684862 JB |
3096 | if (regtab->reg_type.bitfield.dword) |
3097 | { | |
3098 | if (regtab->reg_type.bitfield.instance == Accum) | |
3099 | reg_eax = regtab; | |
3100 | } | |
3101 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3102 | { |
3103 | /* There's no point inserting st(<N>) in the hash table, as | |
3104 | parentheses aren't included in register_chars[] anyway. */ | |
3105 | if (regtab->reg_type.bitfield.instance != Accum) | |
3106 | continue; | |
3107 | reg_st0 = regtab; | |
3108 | } | |
3109 | break; | |
3110 | ||
5e042380 JB |
3111 | case SReg: |
3112 | switch (regtab->reg_num) | |
3113 | { | |
3114 | case 0: reg_es = regtab; break; | |
3115 | case 2: reg_ss = regtab; break; | |
3116 | case 3: reg_ds = regtab; break; | |
3117 | } | |
3118 | break; | |
3119 | ||
6288d05f JB |
3120 | case RegMask: |
3121 | if (!regtab->reg_num) | |
3122 | reg_k0 = regtab; | |
3123 | break; | |
3124 | } | |
3125 | ||
6225c532 JB |
3126 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3127 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3128 | } |
252b5132 RH |
3129 | } |
3130 | ||
47926f60 | 3131 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3132 | { |
29b0f896 AM |
3133 | int c; |
3134 | char *p; | |
252b5132 RH |
3135 | |
3136 | for (c = 0; c < 256; c++) | |
3137 | { | |
3882b010 | 3138 | if (ISDIGIT (c)) |
252b5132 RH |
3139 | { |
3140 | digit_chars[c] = c; | |
3141 | mnemonic_chars[c] = c; | |
3142 | register_chars[c] = c; | |
3143 | operand_chars[c] = c; | |
3144 | } | |
3882b010 | 3145 | else if (ISLOWER (c)) |
252b5132 RH |
3146 | { |
3147 | mnemonic_chars[c] = c; | |
3148 | register_chars[c] = c; | |
3149 | operand_chars[c] = c; | |
3150 | } | |
3882b010 | 3151 | else if (ISUPPER (c)) |
252b5132 | 3152 | { |
3882b010 | 3153 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3154 | register_chars[c] = mnemonic_chars[c]; |
3155 | operand_chars[c] = c; | |
3156 | } | |
43234a1e | 3157 | else if (c == '{' || c == '}') |
86fa6981 L |
3158 | { |
3159 | mnemonic_chars[c] = c; | |
3160 | operand_chars[c] = c; | |
3161 | } | |
b3983e5f JB |
3162 | #ifdef SVR4_COMMENT_CHARS |
3163 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3164 | operand_chars[c] = c; | |
3165 | #endif | |
252b5132 | 3166 | |
3882b010 | 3167 | if (ISALPHA (c) || ISDIGIT (c)) |
252b5132 RH |
3168 | identifier_chars[c] = c; |
3169 | else if (c >= 128) | |
3170 | { | |
3171 | identifier_chars[c] = c; | |
3172 | operand_chars[c] = c; | |
3173 | } | |
3174 | } | |
3175 | ||
3176 | #ifdef LEX_AT | |
3177 | identifier_chars['@'] = '@'; | |
32137342 NC |
3178 | #endif |
3179 | #ifdef LEX_QM | |
3180 | identifier_chars['?'] = '?'; | |
3181 | operand_chars['?'] = '?'; | |
252b5132 | 3182 | #endif |
252b5132 | 3183 | digit_chars['-'] = '-'; |
c0f3af97 | 3184 | mnemonic_chars['_'] = '_'; |
791fe849 | 3185 | mnemonic_chars['-'] = '-'; |
0003779b | 3186 | mnemonic_chars['.'] = '.'; |
252b5132 RH |
3187 | identifier_chars['_'] = '_'; |
3188 | identifier_chars['.'] = '.'; | |
3189 | ||
3190 | for (p = operand_special_chars; *p != '\0'; p++) | |
3191 | operand_chars[(unsigned char) *p] = *p; | |
3192 | } | |
3193 | ||
a4447b93 RH |
3194 | if (flag_code == CODE_64BIT) |
3195 | { | |
ca19b261 KT |
3196 | #if defined (OBJ_COFF) && defined (TE_PE) |
3197 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3198 | ? 32 : 16); | |
3199 | #else | |
a4447b93 | 3200 | x86_dwarf2_return_column = 16; |
ca19b261 | 3201 | #endif |
61ff971f | 3202 | x86_cie_data_alignment = -8; |
a4447b93 RH |
3203 | } |
3204 | else | |
3205 | { | |
3206 | x86_dwarf2_return_column = 8; | |
3207 | x86_cie_data_alignment = -4; | |
3208 | } | |
e379e5f3 L |
3209 | |
3210 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3211 | can be turned into BRANCH_PREFIX frag. */ | |
3212 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3213 | abort (); | |
252b5132 RH |
3214 | } |
3215 | ||
3216 | void | |
e3bb37b5 | 3217 | i386_print_statistics (FILE *file) |
252b5132 | 3218 | { |
629310ab ML |
3219 | htab_print_statistics (file, "i386 opcode", op_hash); |
3220 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 RH |
3221 | } |
3222 | \f | |
252b5132 RH |
3223 | #ifdef DEBUG386 |
3224 | ||
ce8a8b2f | 3225 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3226 | static void pte (insn_template *); |
40fb9820 | 3227 | static void pt (i386_operand_type); |
e3bb37b5 L |
3228 | static void pe (expressionS *); |
3229 | static void ps (symbolS *); | |
252b5132 RH |
3230 | |
3231 | static void | |
2c703856 | 3232 | pi (const char *line, i386_insn *x) |
252b5132 | 3233 | { |
09137c09 | 3234 | unsigned int j; |
252b5132 RH |
3235 | |
3236 | fprintf (stdout, "%s: template ", line); | |
3237 | pte (&x->tm); | |
09f131f2 JH |
3238 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3239 | x->base_reg ? x->base_reg->reg_name : "none", | |
3240 | x->index_reg ? x->index_reg->reg_name : "none", | |
3241 | x->log2_scale_factor); | |
3242 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3243 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3244 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3245 | x->sib.base, x->sib.index, x->sib.scale); | |
3246 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3247 | (x->rex & REX_W) != 0, |
3248 | (x->rex & REX_R) != 0, | |
3249 | (x->rex & REX_X) != 0, | |
3250 | (x->rex & REX_B) != 0); | |
09137c09 | 3251 | for (j = 0; j < x->operands; j++) |
252b5132 | 3252 | { |
09137c09 SP |
3253 | fprintf (stdout, " #%d: ", j + 1); |
3254 | pt (x->types[j]); | |
252b5132 | 3255 | fprintf (stdout, "\n"); |
bab6aec1 | 3256 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3257 | || x->types[j].bitfield.class == RegMMX |
3258 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3259 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3260 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3261 | || x->types[j].bitfield.class == RegCR |
3262 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3263 | || x->types[j].bitfield.class == RegTR |
3264 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3265 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3266 | if (operand_type_check (x->types[j], imm)) | |
3267 | pe (x->op[j].imms); | |
3268 | if (operand_type_check (x->types[j], disp)) | |
3269 | pe (x->op[j].disps); | |
252b5132 RH |
3270 | } |
3271 | } | |
3272 | ||
3273 | static void | |
d3ce72d0 | 3274 | pte (insn_template *t) |
252b5132 | 3275 | { |
b933fa4b | 3276 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca JB |
3277 | static const char *const opc_spc[] = { |
3278 | NULL, "0f", "0f38", "0f3a", NULL, NULL, NULL, NULL, | |
3279 | "XOP08", "XOP09", "XOP0A", | |
3280 | }; | |
09137c09 | 3281 | unsigned int j; |
441f6aca | 3282 | |
252b5132 | 3283 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3284 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3285 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
3286 | if (opc_spc[t->opcode_modifier.opcodespace]) | |
3287 | fprintf (stdout, "space %s ", opc_spc[t->opcode_modifier.opcodespace]); | |
47926f60 | 3288 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3289 | if (t->extension_opcode != None) |
3290 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3291 | if (t->opcode_modifier.d) |
252b5132 | 3292 | fprintf (stdout, "D"); |
40fb9820 | 3293 | if (t->opcode_modifier.w) |
252b5132 RH |
3294 | fprintf (stdout, "W"); |
3295 | fprintf (stdout, "\n"); | |
09137c09 | 3296 | for (j = 0; j < t->operands; j++) |
252b5132 | 3297 | { |
09137c09 SP |
3298 | fprintf (stdout, " #%d type ", j + 1); |
3299 | pt (t->operand_types[j]); | |
252b5132 RH |
3300 | fprintf (stdout, "\n"); |
3301 | } | |
3302 | } | |
3303 | ||
3304 | static void | |
e3bb37b5 | 3305 | pe (expressionS *e) |
252b5132 | 3306 | { |
24eab124 | 3307 | fprintf (stdout, " operation %d\n", e->X_op); |
7b025ee8 JB |
3308 | fprintf (stdout, " add_number %" BFD_VMA_FMT "d (%" BFD_VMA_FMT "x)\n", |
3309 | e->X_add_number, e->X_add_number); | |
252b5132 RH |
3310 | if (e->X_add_symbol) |
3311 | { | |
3312 | fprintf (stdout, " add_symbol "); | |
3313 | ps (e->X_add_symbol); | |
3314 | fprintf (stdout, "\n"); | |
3315 | } | |
3316 | if (e->X_op_symbol) | |
3317 | { | |
3318 | fprintf (stdout, " op_symbol "); | |
3319 | ps (e->X_op_symbol); | |
3320 | fprintf (stdout, "\n"); | |
3321 | } | |
3322 | } | |
3323 | ||
3324 | static void | |
e3bb37b5 | 3325 | ps (symbolS *s) |
252b5132 RH |
3326 | { |
3327 | fprintf (stdout, "%s type %s%s", | |
3328 | S_GET_NAME (s), | |
3329 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3330 | segment_name (S_GET_SEGMENT (s))); | |
3331 | } | |
3332 | ||
7b81dfbb | 3333 | static struct type_name |
252b5132 | 3334 | { |
40fb9820 L |
3335 | i386_operand_type mask; |
3336 | const char *name; | |
252b5132 | 3337 | } |
7b81dfbb | 3338 | const type_names[] = |
252b5132 | 3339 | { |
40fb9820 L |
3340 | { OPERAND_TYPE_REG8, "r8" }, |
3341 | { OPERAND_TYPE_REG16, "r16" }, | |
3342 | { OPERAND_TYPE_REG32, "r32" }, | |
3343 | { OPERAND_TYPE_REG64, "r64" }, | |
2c703856 JB |
3344 | { OPERAND_TYPE_ACC8, "acc8" }, |
3345 | { OPERAND_TYPE_ACC16, "acc16" }, | |
3346 | { OPERAND_TYPE_ACC32, "acc32" }, | |
3347 | { OPERAND_TYPE_ACC64, "acc64" }, | |
40fb9820 L |
3348 | { OPERAND_TYPE_IMM8, "i8" }, |
3349 | { OPERAND_TYPE_IMM8, "i8s" }, | |
3350 | { OPERAND_TYPE_IMM16, "i16" }, | |
3351 | { OPERAND_TYPE_IMM32, "i32" }, | |
3352 | { OPERAND_TYPE_IMM32S, "i32s" }, | |
3353 | { OPERAND_TYPE_IMM64, "i64" }, | |
3354 | { OPERAND_TYPE_IMM1, "i1" }, | |
3355 | { OPERAND_TYPE_BASEINDEX, "BaseIndex" }, | |
3356 | { OPERAND_TYPE_DISP8, "d8" }, | |
3357 | { OPERAND_TYPE_DISP16, "d16" }, | |
3358 | { OPERAND_TYPE_DISP32, "d32" }, | |
3359 | { OPERAND_TYPE_DISP32S, "d32s" }, | |
3360 | { OPERAND_TYPE_DISP64, "d64" }, | |
3361 | { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" }, | |
3362 | { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" }, | |
3363 | { OPERAND_TYPE_CONTROL, "control reg" }, | |
3364 | { OPERAND_TYPE_TEST, "test reg" }, | |
3365 | { OPERAND_TYPE_DEBUG, "debug reg" }, | |
3366 | { OPERAND_TYPE_FLOATREG, "FReg" }, | |
3367 | { OPERAND_TYPE_FLOATACC, "FAcc" }, | |
21df382b | 3368 | { OPERAND_TYPE_SREG, "SReg" }, |
40fb9820 L |
3369 | { OPERAND_TYPE_REGMMX, "rMMX" }, |
3370 | { OPERAND_TYPE_REGXMM, "rXMM" }, | |
0349dc08 | 3371 | { OPERAND_TYPE_REGYMM, "rYMM" }, |
43234a1e | 3372 | { OPERAND_TYPE_REGZMM, "rZMM" }, |
260cd341 | 3373 | { OPERAND_TYPE_REGTMM, "rTMM" }, |
43234a1e | 3374 | { OPERAND_TYPE_REGMASK, "Mask reg" }, |
252b5132 RH |
3375 | }; |
3376 | ||
3377 | static void | |
40fb9820 | 3378 | pt (i386_operand_type t) |
252b5132 | 3379 | { |
40fb9820 | 3380 | unsigned int j; |
c6fb90c8 | 3381 | i386_operand_type a; |
252b5132 | 3382 | |
40fb9820 | 3383 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3384 | { |
3385 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3386 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3387 | fprintf (stdout, "%s, ", type_names[j].name); |
3388 | } | |
252b5132 RH |
3389 | fflush (stdout); |
3390 | } | |
3391 | ||
3392 | #endif /* DEBUG386 */ | |
3393 | \f | |
252b5132 | 3394 | static bfd_reloc_code_real_type |
3956db08 | 3395 | reloc (unsigned int size, |
64e74474 AM |
3396 | int pcrel, |
3397 | int sign, | |
3398 | bfd_reloc_code_real_type other) | |
252b5132 | 3399 | { |
47926f60 | 3400 | if (other != NO_RELOC) |
3956db08 | 3401 | { |
91d6fa6a | 3402 | reloc_howto_type *rel; |
3956db08 JB |
3403 | |
3404 | if (size == 8) | |
3405 | switch (other) | |
3406 | { | |
64e74474 AM |
3407 | case BFD_RELOC_X86_64_GOT32: |
3408 | return BFD_RELOC_X86_64_GOT64; | |
3409 | break; | |
553d1284 L |
3410 | case BFD_RELOC_X86_64_GOTPLT64: |
3411 | return BFD_RELOC_X86_64_GOTPLT64; | |
3412 | break; | |
64e74474 AM |
3413 | case BFD_RELOC_X86_64_PLTOFF64: |
3414 | return BFD_RELOC_X86_64_PLTOFF64; | |
3415 | break; | |
3416 | case BFD_RELOC_X86_64_GOTPC32: | |
3417 | other = BFD_RELOC_X86_64_GOTPC64; | |
3418 | break; | |
3419 | case BFD_RELOC_X86_64_GOTPCREL: | |
3420 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3421 | break; | |
3422 | case BFD_RELOC_X86_64_TPOFF32: | |
3423 | other = BFD_RELOC_X86_64_TPOFF64; | |
3424 | break; | |
3425 | case BFD_RELOC_X86_64_DTPOFF32: | |
3426 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3427 | break; | |
3428 | default: | |
3429 | break; | |
3956db08 | 3430 | } |
e05278af | 3431 | |
8ce3d284 | 3432 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3433 | if (other == BFD_RELOC_SIZE32) |
3434 | { | |
3435 | if (size == 8) | |
1ab668bf | 3436 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3437 | if (pcrel) |
1ab668bf AM |
3438 | { |
3439 | as_bad (_("there are no pc-relative size relocations")); | |
3440 | return NO_RELOC; | |
3441 | } | |
8fd4256d | 3442 | } |
8ce3d284 | 3443 | #endif |
8fd4256d | 3444 | |
e05278af | 3445 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3446 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3447 | sign = -1; |
3448 | ||
91d6fa6a NC |
3449 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3450 | if (!rel) | |
3956db08 | 3451 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3452 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3453 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3454 | bfd_get_reloc_size (rel), |
3956db08 | 3455 | size); |
91d6fa6a | 3456 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3457 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3458 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3459 | && !sign) |
91d6fa6a | 3460 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3461 | && sign > 0)) |
3956db08 JB |
3462 | as_bad (_("relocated field and relocation type differ in signedness")); |
3463 | else | |
3464 | return other; | |
3465 | return NO_RELOC; | |
3466 | } | |
252b5132 RH |
3467 | |
3468 | if (pcrel) | |
3469 | { | |
3e73aa7c | 3470 | if (!sign) |
3956db08 | 3471 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3472 | switch (size) |
3473 | { | |
3474 | case 1: return BFD_RELOC_8_PCREL; | |
3475 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3476 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3477 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3478 | } |
3956db08 | 3479 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3480 | } |
3481 | else | |
3482 | { | |
3956db08 | 3483 | if (sign > 0) |
e5cb08ac | 3484 | switch (size) |
3e73aa7c JH |
3485 | { |
3486 | case 4: return BFD_RELOC_X86_64_32S; | |
3487 | } | |
3488 | else | |
3489 | switch (size) | |
3490 | { | |
3491 | case 1: return BFD_RELOC_8; | |
3492 | case 2: return BFD_RELOC_16; | |
3493 | case 4: return BFD_RELOC_32; | |
3494 | case 8: return BFD_RELOC_64; | |
3495 | } | |
3956db08 JB |
3496 | as_bad (_("cannot do %s %u byte relocation"), |
3497 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3498 | } |
3499 | ||
0cc9e1d3 | 3500 | return NO_RELOC; |
252b5132 RH |
3501 | } |
3502 | ||
47926f60 KH |
3503 | /* Here we decide which fixups can be adjusted to make them relative to |
3504 | the beginning of the section instead of the symbol. Basically we need | |
3505 | to make sure that the dynamic relocations are done correctly, so in | |
3506 | some cases we force the original symbol to be used. */ | |
3507 | ||
252b5132 | 3508 | int |
e3bb37b5 | 3509 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3510 | { |
6d249963 | 3511 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3512 | if (!IS_ELF) |
31312f95 AM |
3513 | return 1; |
3514 | ||
a161fe53 AM |
3515 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3516 | mode. */ | |
3517 | if (use_rela_relocations | |
3518 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3519 | && fixP->fx_pcrel) | |
252b5132 | 3520 | return 0; |
31312f95 | 3521 | |
8d01d9a9 AJ |
3522 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3523 | and changed later by validate_fix. */ | |
3524 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3525 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3526 | return 0; | |
3527 | ||
8fd4256d L |
3528 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3529 | for size relocations. */ | |
3530 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3531 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3532 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3533 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3534 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3535 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3536 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3537 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3538 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3539 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3540 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3541 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3542 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3543 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3544 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3545 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3546 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3547 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3548 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3549 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3550 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3551 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3552 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3553 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3554 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3555 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3556 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3557 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3558 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3559 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3560 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3561 | return 0; | |
31312f95 | 3562 | #endif |
252b5132 RH |
3563 | return 1; |
3564 | } | |
252b5132 | 3565 | |
a9aabc23 JB |
3566 | static INLINE bool |
3567 | want_disp32 (const insn_template *t) | |
3568 | { | |
3569 | return flag_code != CODE_64BIT | |
3570 | || i.prefix[ADDR_PREFIX] | |
3571 | || (t->base_opcode == 0x8d | |
3572 | && t->opcode_modifier.opcodespace == SPACE_BASE | |
fe134c65 JB |
3573 | && (!i.types[1].bitfield.qword |
3574 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3575 | } |
3576 | ||
b4cac588 | 3577 | static int |
e3bb37b5 | 3578 | intel_float_operand (const char *mnemonic) |
252b5132 | 3579 | { |
9306ca4a JB |
3580 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3581 | operands, hence the code here is free to improperly handle opcodes that | |
3582 | have no operands (for better performance and smaller code). */ | |
3583 | ||
3584 | if (mnemonic[0] != 'f') | |
3585 | return 0; /* non-math */ | |
3586 | ||
3587 | switch (mnemonic[1]) | |
3588 | { | |
3589 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3590 | the fs segment override prefix not currently handled because no | |
3591 | call path can make opcodes without operands get here */ | |
3592 | case 'i': | |
3593 | return 2 /* integer op */; | |
3594 | case 'l': | |
3595 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3596 | return 3; /* fldcw/fldenv */ | |
3597 | break; | |
3598 | case 'n': | |
3599 | if (mnemonic[2] != 'o' /* fnop */) | |
3600 | return 3; /* non-waiting control op */ | |
3601 | break; | |
3602 | case 'r': | |
3603 | if (mnemonic[2] == 's') | |
3604 | return 3; /* frstor/frstpm */ | |
3605 | break; | |
3606 | case 's': | |
3607 | if (mnemonic[2] == 'a') | |
3608 | return 3; /* fsave */ | |
3609 | if (mnemonic[2] == 't') | |
3610 | { | |
3611 | switch (mnemonic[3]) | |
3612 | { | |
3613 | case 'c': /* fstcw */ | |
3614 | case 'd': /* fstdw */ | |
3615 | case 'e': /* fstenv */ | |
3616 | case 's': /* fsts[gw] */ | |
3617 | return 3; | |
3618 | } | |
3619 | } | |
3620 | break; | |
3621 | case 'x': | |
3622 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3623 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3624 | break; | |
3625 | } | |
252b5132 | 3626 | |
9306ca4a | 3627 | return 1; |
252b5132 RH |
3628 | } |
3629 | ||
9a182d04 JB |
3630 | static INLINE void |
3631 | install_template (const insn_template *t) | |
3632 | { | |
3633 | unsigned int l; | |
3634 | ||
3635 | i.tm = *t; | |
3636 | ||
3637 | /* Note that for pseudo prefixes this produces a length of 1. But for them | |
3638 | the length isn't interesting at all. */ | |
3639 | for (l = 1; l < 4; ++l) | |
3640 | if (!(t->base_opcode >> (8 * l))) | |
3641 | break; | |
3642 | ||
3643 | i.opcode_length = l; | |
3644 | } | |
3645 | ||
c0f3af97 L |
3646 | /* Build the VEX prefix. */ |
3647 | ||
3648 | static void | |
d3ce72d0 | 3649 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3650 | { |
3651 | unsigned int register_specifier; | |
c0f3af97 | 3652 | unsigned int vector_length; |
03751133 | 3653 | unsigned int w; |
c0f3af97 L |
3654 | |
3655 | /* Check register specifier. */ | |
3656 | if (i.vex.register_specifier) | |
43234a1e L |
3657 | { |
3658 | register_specifier = | |
3659 | ~register_number (i.vex.register_specifier) & 0xf; | |
3660 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3661 | } | |
c0f3af97 L |
3662 | else |
3663 | register_specifier = 0xf; | |
3664 | ||
79f0fa25 L |
3665 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3666 | if there are more than 1 register operand. */ | |
3667 | if (i.reg_operands > 1 | |
3668 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3669 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3670 | && i.operands == i.reg_operands |
dbbc8b7e | 3671 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
441f6aca | 3672 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
dbbc8b7e | 3673 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3674 | && i.rex == REX_B) |
3675 | { | |
3676 | unsigned int xchg = i.operands - 1; | |
3677 | union i386_op temp_op; | |
3678 | i386_operand_type temp_type; | |
3679 | ||
3680 | temp_type = i.types[xchg]; | |
3681 | i.types[xchg] = i.types[0]; | |
3682 | i.types[0] = temp_type; | |
3683 | temp_op = i.op[xchg]; | |
3684 | i.op[xchg] = i.op[0]; | |
3685 | i.op[0] = temp_op; | |
3686 | ||
9c2799c2 | 3687 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3688 | |
3689 | i.rex = REX_R; | |
3690 | xchg = i.rm.regmem; | |
3691 | i.rm.regmem = i.rm.reg; | |
3692 | i.rm.reg = xchg; | |
3693 | ||
dbbc8b7e JB |
3694 | if (i.tm.opcode_modifier.d) |
3695 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
3696 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
3697 | else /* Use the next insn. */ | |
9a182d04 | 3698 | install_template (&t[1]); |
fa99fab2 L |
3699 | } |
3700 | ||
79dec6b7 JB |
3701 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3702 | are no memory operands and at least 3 register ones. */ | |
3703 | if (i.reg_operands >= 3 | |
3704 | && i.vec_encoding != vex_encoding_vex3 | |
3705 | && i.reg_operands == i.operands - i.imm_operands | |
3706 | && i.tm.opcode_modifier.vex | |
3707 | && i.tm.opcode_modifier.commutative | |
3708 | && (i.tm.opcode_modifier.sse2avx || optimize > 1) | |
3709 | && i.rex == REX_B | |
3710 | && i.vex.register_specifier | |
3711 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3712 | { | |
3713 | unsigned int xchg = i.operands - i.reg_operands; | |
3714 | union i386_op temp_op; | |
3715 | i386_operand_type temp_type; | |
3716 | ||
441f6aca | 3717 | gas_assert (i.tm.opcode_modifier.opcodespace == SPACE_0F); |
79dec6b7 JB |
3718 | gas_assert (!i.tm.opcode_modifier.sae); |
3719 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3720 | &i.types[i.operands - 3])); | |
3721 | gas_assert (i.rm.mode == 3); | |
3722 | ||
3723 | temp_type = i.types[xchg]; | |
3724 | i.types[xchg] = i.types[xchg + 1]; | |
3725 | i.types[xchg + 1] = temp_type; | |
3726 | temp_op = i.op[xchg]; | |
3727 | i.op[xchg] = i.op[xchg + 1]; | |
3728 | i.op[xchg + 1] = temp_op; | |
3729 | ||
3730 | i.rex = 0; | |
3731 | xchg = i.rm.regmem | 8; | |
3732 | i.rm.regmem = ~register_specifier & 0xf; | |
3733 | gas_assert (!(i.rm.regmem & 8)); | |
3734 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3735 | register_specifier = ~xchg & 0xf; | |
3736 | } | |
3737 | ||
539f890d L |
3738 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3739 | vector_length = avxscalar; | |
10c17abd JB |
3740 | else if (i.tm.opcode_modifier.vex == VEX256) |
3741 | vector_length = 1; | |
539f890d | 3742 | else |
10c17abd | 3743 | { |
56522fc5 | 3744 | unsigned int op; |
10c17abd | 3745 | |
c7213af9 L |
3746 | /* Determine vector length from the last multi-length vector |
3747 | operand. */ | |
10c17abd | 3748 | vector_length = 0; |
56522fc5 | 3749 | for (op = t->operands; op--;) |
10c17abd JB |
3750 | if (t->operand_types[op].bitfield.xmmword |
3751 | && t->operand_types[op].bitfield.ymmword | |
3752 | && i.types[op].bitfield.ymmword) | |
3753 | { | |
3754 | vector_length = 1; | |
3755 | break; | |
3756 | } | |
3757 | } | |
c0f3af97 | 3758 | |
03751133 L |
3759 | /* Check the REX.W bit and VEXW. */ |
3760 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3761 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3762 | else if (i.tm.opcode_modifier.vexw) | |
3763 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3764 | else | |
931d03b7 | 3765 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3766 | |
c0f3af97 | 3767 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3768 | if (w == 0 |
3769 | && i.vec_encoding != vex_encoding_vex3 | |
441f6aca | 3770 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
c0f3af97 L |
3771 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3772 | { | |
3773 | /* 2-byte VEX prefix. */ | |
3774 | unsigned int r; | |
3775 | ||
3776 | i.vex.length = 2; | |
3777 | i.vex.bytes[0] = 0xc5; | |
3778 | ||
3779 | /* Check the REX.R bit. */ | |
3780 | r = (i.rex & REX_R) ? 0 : 1; | |
3781 | i.vex.bytes[1] = (r << 7 | |
3782 | | register_specifier << 3 | |
3783 | | vector_length << 2 | |
35648716 | 3784 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3785 | } |
3786 | else | |
3787 | { | |
3788 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3789 | i.vex.length = 3; |
f88c9eb0 | 3790 | |
441f6aca | 3791 | switch (i.tm.opcode_modifier.opcodespace) |
5dd85c99 | 3792 | { |
441f6aca JB |
3793 | case SPACE_0F: |
3794 | case SPACE_0F38: | |
3795 | case SPACE_0F3A: | |
80de6e00 | 3796 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3797 | break; |
441f6aca JB |
3798 | case SPACE_XOP08: |
3799 | case SPACE_XOP09: | |
3800 | case SPACE_XOP0A: | |
f88c9eb0 | 3801 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3802 | break; |
3803 | default: | |
3804 | abort (); | |
f88c9eb0 | 3805 | } |
c0f3af97 | 3806 | |
c0f3af97 L |
3807 | /* The high 3 bits of the second VEX byte are 1's compliment |
3808 | of RXB bits from REX. */ | |
441f6aca | 3809 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_modifier.opcodespace; |
c0f3af97 | 3810 | |
c0f3af97 L |
3811 | i.vex.bytes[2] = (w << 7 |
3812 | | register_specifier << 3 | |
3813 | | vector_length << 2 | |
35648716 | 3814 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3815 | } |
3816 | } | |
3817 | ||
5b7c81bd | 3818 | static INLINE bool |
e771e7c9 JB |
3819 | is_evex_encoding (const insn_template *t) |
3820 | { | |
7091c612 | 3821 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3822 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3823 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3824 | } |
3825 | ||
5b7c81bd | 3826 | static INLINE bool |
7a8655d2 JB |
3827 | is_any_vex_encoding (const insn_template *t) |
3828 | { | |
7b47a312 | 3829 | return t->opcode_modifier.vex || is_evex_encoding (t); |
7a8655d2 JB |
3830 | } |
3831 | ||
43234a1e L |
3832 | /* Build the EVEX prefix. */ |
3833 | ||
3834 | static void | |
3835 | build_evex_prefix (void) | |
3836 | { | |
35648716 | 3837 | unsigned int register_specifier, w; |
43234a1e L |
3838 | rex_byte vrex_used = 0; |
3839 | ||
3840 | /* Check register specifier. */ | |
3841 | if (i.vex.register_specifier) | |
3842 | { | |
3843 | gas_assert ((i.vrex & REX_X) == 0); | |
3844 | ||
3845 | register_specifier = i.vex.register_specifier->reg_num; | |
3846 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3847 | register_specifier += 8; | |
3848 | /* The upper 16 registers are encoded in the fourth byte of the | |
3849 | EVEX prefix. */ | |
3850 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3851 | i.vex.bytes[3] = 0x8; | |
3852 | register_specifier = ~register_specifier & 0xf; | |
3853 | } | |
3854 | else | |
3855 | { | |
3856 | register_specifier = 0xf; | |
3857 | ||
3858 | /* Encode upper 16 vector index register in the fourth byte of | |
3859 | the EVEX prefix. */ | |
3860 | if (!(i.vrex & REX_X)) | |
3861 | i.vex.bytes[3] = 0x8; | |
3862 | else | |
3863 | vrex_used |= REX_X; | |
3864 | } | |
3865 | ||
43234a1e L |
3866 | /* 4 byte EVEX prefix. */ |
3867 | i.vex.length = 4; | |
3868 | i.vex.bytes[0] = 0x62; | |
3869 | ||
43234a1e L |
3870 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
3871 | bits from REX. */ | |
441f6aca JB |
3872 | gas_assert (i.tm.opcode_modifier.opcodespace >= SPACE_0F); |
3873 | gas_assert (i.tm.opcode_modifier.opcodespace <= SPACE_0F3A); | |
3874 | i.vex.bytes[1] = (~i.rex & 0x7) << 5 | i.tm.opcode_modifier.opcodespace; | |
43234a1e L |
3875 | |
3876 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3877 | REX_R bit in VREX. */ | |
3878 | if (!(i.vrex & REX_R)) | |
3879 | i.vex.bytes[1] |= 0x10; | |
3880 | else | |
3881 | vrex_used |= REX_R; | |
3882 | ||
3883 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3884 | { | |
3885 | /* When all operands are registers, the REX_X bit in REX is not | |
3886 | used. We reuse it to encode the upper 16 registers, which is | |
3887 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3888 | as 1's compliment. */ | |
3889 | if ((i.vrex & REX_B)) | |
3890 | { | |
3891 | vrex_used |= REX_B; | |
3892 | i.vex.bytes[1] &= ~0x40; | |
3893 | } | |
3894 | } | |
3895 | ||
3896 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3897 | i.vrex &= ~vrex_used; | |
3898 | gas_assert (i.vrex == 0); | |
3899 | ||
6865c043 L |
3900 | /* Check the REX.W bit and VEXW. */ |
3901 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3902 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3903 | else if (i.tm.opcode_modifier.vexw) | |
3904 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3905 | else | |
931d03b7 | 3906 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 3907 | |
43234a1e | 3908 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
3909 | i.vex.bytes[2] = ((w << 7) |
3910 | | (register_specifier << 3) | |
3911 | | 4 /* Encode the U bit. */ | |
3912 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
3913 | |
3914 | /* The fourth byte of the EVEX prefix. */ | |
3915 | /* The zeroing-masking bit. */ | |
6225c532 | 3916 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
3917 | i.vex.bytes[3] |= 0x80; |
3918 | ||
3919 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 3920 | if (i.rounding.type == rc_none) |
43234a1e L |
3921 | { |
3922 | /* Encode the vector length. */ | |
3923 | unsigned int vec_length; | |
3924 | ||
e771e7c9 JB |
3925 | if (!i.tm.opcode_modifier.evex |
3926 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
3927 | { | |
56522fc5 | 3928 | unsigned int op; |
e771e7c9 | 3929 | |
c7213af9 L |
3930 | /* Determine vector length from the last multi-length vector |
3931 | operand. */ | |
56522fc5 | 3932 | for (op = i.operands; op--;) |
e771e7c9 JB |
3933 | if (i.tm.operand_types[op].bitfield.xmmword |
3934 | + i.tm.operand_types[op].bitfield.ymmword | |
3935 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
3936 | { | |
3937 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
3938 | { |
3939 | i.tm.opcode_modifier.evex = EVEX512; | |
3940 | break; | |
3941 | } | |
e771e7c9 | 3942 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
3943 | { |
3944 | i.tm.opcode_modifier.evex = EVEX256; | |
3945 | break; | |
3946 | } | |
e771e7c9 | 3947 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
3948 | { |
3949 | i.tm.opcode_modifier.evex = EVEX128; | |
3950 | break; | |
3951 | } | |
5273a3cd | 3952 | else if (i.broadcast.type && op == i.broadcast.operand) |
625cbd7a | 3953 | { |
5273a3cd | 3954 | switch (i.broadcast.bytes) |
625cbd7a JB |
3955 | { |
3956 | case 64: | |
3957 | i.tm.opcode_modifier.evex = EVEX512; | |
3958 | break; | |
3959 | case 32: | |
3960 | i.tm.opcode_modifier.evex = EVEX256; | |
3961 | break; | |
3962 | case 16: | |
3963 | i.tm.opcode_modifier.evex = EVEX128; | |
3964 | break; | |
3965 | default: | |
c7213af9 | 3966 | abort (); |
625cbd7a | 3967 | } |
c7213af9 | 3968 | break; |
625cbd7a | 3969 | } |
e771e7c9 | 3970 | } |
c7213af9 | 3971 | |
56522fc5 | 3972 | if (op >= MAX_OPERANDS) |
c7213af9 | 3973 | abort (); |
e771e7c9 JB |
3974 | } |
3975 | ||
43234a1e L |
3976 | switch (i.tm.opcode_modifier.evex) |
3977 | { | |
3978 | case EVEXLIG: /* LL' is ignored */ | |
3979 | vec_length = evexlig << 5; | |
3980 | break; | |
3981 | case EVEX128: | |
3982 | vec_length = 0 << 5; | |
3983 | break; | |
3984 | case EVEX256: | |
3985 | vec_length = 1 << 5; | |
3986 | break; | |
3987 | case EVEX512: | |
3988 | vec_length = 2 << 5; | |
3989 | break; | |
3990 | default: | |
3991 | abort (); | |
3992 | break; | |
3993 | } | |
3994 | i.vex.bytes[3] |= vec_length; | |
3995 | /* Encode the broadcast bit. */ | |
5273a3cd | 3996 | if (i.broadcast.type) |
43234a1e L |
3997 | i.vex.bytes[3] |= 0x10; |
3998 | } | |
ca5312a2 JB |
3999 | else if (i.rounding.type != saeonly) |
4000 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 4001 | else |
ca5312a2 | 4002 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 4003 | |
6225c532 JB |
4004 | if (i.mask.reg) |
4005 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
4006 | } |
4007 | ||
65da13b5 L |
4008 | static void |
4009 | process_immext (void) | |
4010 | { | |
4011 | expressionS *exp; | |
4012 | ||
c0f3af97 | 4013 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4014 | which is coded in the same place as an 8-bit immediate field |
4015 | would be. Here we fake an 8-bit immediate operand from the | |
4016 | opcode suffix stored in tm.extension_opcode. | |
4017 | ||
c1e679ec | 4018 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4019 | 3 argument instructions. */ |
65da13b5 | 4020 | |
43234a1e | 4021 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4022 | && (i.operands <= 2 |
7a8655d2 | 4023 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4024 | && i.operands <= 4))); |
65da13b5 L |
4025 | |
4026 | exp = &im_expressions[i.imm_operands++]; | |
4027 | i.op[i.operands].imms = exp; | |
4028 | i.types[i.operands] = imm8; | |
4029 | i.operands++; | |
4030 | exp->X_op = O_constant; | |
4031 | exp->X_add_number = i.tm.extension_opcode; | |
4032 | i.tm.extension_opcode = None; | |
4033 | } | |
4034 | ||
42164a71 L |
4035 | |
4036 | static int | |
4037 | check_hle (void) | |
4038 | { | |
742732c7 | 4039 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4040 | { |
4041 | default: | |
4042 | abort (); | |
742732c7 JB |
4043 | case PrefixLock: |
4044 | case PrefixNone: | |
4045 | case PrefixNoTrack: | |
4046 | case PrefixRep: | |
165de32a L |
4047 | as_bad (_("invalid instruction `%s' after `%s'"), |
4048 | i.tm.name, i.hle_prefix); | |
42164a71 | 4049 | return 0; |
742732c7 | 4050 | case PrefixHLELock: |
42164a71 L |
4051 | if (i.prefix[LOCK_PREFIX]) |
4052 | return 1; | |
165de32a | 4053 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4054 | return 0; |
742732c7 | 4055 | case PrefixHLEAny: |
42164a71 | 4056 | return 1; |
742732c7 | 4057 | case PrefixHLERelease: |
42164a71 L |
4058 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4059 | { | |
4060 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
4061 | i.tm.name); | |
4062 | return 0; | |
4063 | } | |
8dc0818e | 4064 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4065 | { |
4066 | as_bad (_("memory destination needed for instruction `%s'" | |
4067 | " after `xrelease'"), i.tm.name); | |
4068 | return 0; | |
4069 | } | |
4070 | return 1; | |
4071 | } | |
4072 | } | |
4073 | ||
b6f8c7c4 L |
4074 | /* Try the shortest encoding by shortening operand size. */ |
4075 | ||
4076 | static void | |
4077 | optimize_encoding (void) | |
4078 | { | |
a0a1771e | 4079 | unsigned int j; |
b6f8c7c4 | 4080 | |
fe134c65 JB |
4081 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
4082 | && i.tm.base_opcode == 0x8d) | |
4083 | { | |
4084 | /* Optimize: -O: | |
4085 | lea symbol, %rN -> mov $symbol, %rN | |
4086 | lea (%rM), %rN -> mov %rM, %rN | |
4087 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4088 | ||
4089 | and in 32-bit mode for 16-bit addressing | |
4090 | ||
4091 | lea (%rM), %rN -> movzx %rM, %rN | |
4092 | ||
4093 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4094 | 32-bit (or less) destination. | |
4095 | */ | |
4096 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4097 | { | |
4098 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4099 | i.tm.opcode_modifier.size = SIZE32; | |
4100 | i.prefix[ADDR_PREFIX] = 0; | |
4101 | } | |
4102 | ||
4103 | if (!i.index_reg && !i.base_reg) | |
4104 | { | |
4105 | /* Handle: | |
4106 | lea symbol, %rN -> mov $symbol, %rN | |
4107 | */ | |
4108 | if (flag_code == CODE_64BIT) | |
4109 | { | |
4110 | /* Don't transform a relocation to a 16-bit one. */ | |
4111 | if (i.op[0].disps | |
4112 | && i.op[0].disps->X_op != O_constant | |
4113 | && i.op[1].regs->reg_type.bitfield.word) | |
4114 | return; | |
4115 | ||
4116 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4117 | || i.tm.opcode_modifier.size == SIZE32) | |
4118 | { | |
4119 | i.tm.base_opcode = 0xb8; | |
4120 | i.tm.opcode_modifier.modrm = 0; | |
4121 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4122 | i.types[0].bitfield.imm32 = 1; | |
4123 | else | |
4124 | { | |
4125 | i.tm.opcode_modifier.size = SIZE16; | |
4126 | i.types[0].bitfield.imm16 = 1; | |
4127 | } | |
4128 | } | |
4129 | else | |
4130 | { | |
4131 | /* Subject to further optimization below. */ | |
4132 | i.tm.base_opcode = 0xc7; | |
4133 | i.tm.extension_opcode = 0; | |
4134 | i.types[0].bitfield.imm32s = 1; | |
4135 | i.types[0].bitfield.baseindex = 0; | |
4136 | } | |
4137 | } | |
4138 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4139 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4140 | even couldn't express the relocation correctly. */ | |
4141 | else if (i.op[0].disps | |
4142 | && i.op[0].disps->X_op != O_constant | |
4143 | && ((!i.prefix[ADDR_PREFIX]) | |
4144 | != (flag_code == CODE_32BIT | |
4145 | ? i.op[1].regs->reg_type.bitfield.dword | |
4146 | : i.op[1].regs->reg_type.bitfield.word))) | |
4147 | return; | |
4148 | else | |
4149 | { | |
4150 | i.tm.base_opcode = 0xb8; | |
4151 | i.tm.opcode_modifier.modrm = 0; | |
4152 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4153 | i.types[0].bitfield.imm32 = 1; | |
4154 | else | |
4155 | i.types[0].bitfield.imm16 = 1; | |
4156 | ||
4157 | if (i.op[0].disps | |
4158 | && i.op[0].disps->X_op == O_constant | |
4159 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4160 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4161 | GCC 5. */ | |
4162 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4163 | i.op[0].disps->X_add_number &= 0xffff; |
4164 | } | |
4165 | ||
4166 | i.tm.operand_types[0] = i.types[0]; | |
4167 | i.imm_operands = 1; | |
4168 | if (!i.op[0].imms) | |
4169 | { | |
4170 | i.op[0].imms = &im_expressions[0]; | |
4171 | i.op[0].imms->X_op = O_absent; | |
4172 | } | |
4173 | } | |
4174 | else if (i.op[0].disps | |
4175 | && (i.op[0].disps->X_op != O_constant | |
4176 | || i.op[0].disps->X_add_number)) | |
4177 | return; | |
4178 | else | |
4179 | { | |
4180 | /* Handle: | |
4181 | lea (%rM), %rN -> mov %rM, %rN | |
4182 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4183 | lea (%rM), %rN -> movzx %rM, %rN | |
4184 | */ | |
4185 | const reg_entry *addr_reg; | |
4186 | ||
4187 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4188 | addr_reg = i.base_reg; | |
4189 | else if (!i.base_reg | |
4190 | && i.index_reg->reg_num != RegIZ | |
4191 | && !i.log2_scale_factor) | |
4192 | addr_reg = i.index_reg; | |
4193 | else | |
4194 | return; | |
4195 | ||
4196 | if (addr_reg->reg_type.bitfield.word | |
4197 | && i.op[1].regs->reg_type.bitfield.dword) | |
4198 | { | |
4199 | if (flag_code != CODE_32BIT) | |
4200 | return; | |
4201 | i.tm.opcode_modifier.opcodespace = SPACE_0F; | |
4202 | i.tm.base_opcode = 0xb7; | |
4203 | } | |
4204 | else | |
4205 | i.tm.base_opcode = 0x8b; | |
4206 | ||
4207 | if (addr_reg->reg_type.bitfield.dword | |
4208 | && i.op[1].regs->reg_type.bitfield.qword) | |
4209 | i.tm.opcode_modifier.size = SIZE32; | |
4210 | ||
4211 | i.op[0].regs = addr_reg; | |
4212 | i.reg_operands = 2; | |
4213 | } | |
4214 | ||
4215 | i.mem_operands = 0; | |
4216 | i.disp_operands = 0; | |
4217 | i.prefix[ADDR_PREFIX] = 0; | |
4218 | i.prefix[SEG_PREFIX] = 0; | |
4219 | i.seg[0] = NULL; | |
4220 | } | |
4221 | ||
b6f8c7c4 | 4222 | if (optimize_for_space |
389d00a5 | 4223 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
b6f8c7c4 L |
4224 | && i.reg_operands == 1 |
4225 | && i.imm_operands == 1 | |
4226 | && !i.types[1].bitfield.byte | |
4227 | && i.op[0].imms->X_op == O_constant | |
4228 | && fits_in_imm7 (i.op[0].imms->X_add_number) | |
72aea328 | 4229 | && (i.tm.base_opcode == 0xa8 |
b6f8c7c4 L |
4230 | || (i.tm.base_opcode == 0xf6 |
4231 | && i.tm.extension_opcode == 0x0))) | |
4232 | { | |
4233 | /* Optimize: -Os: | |
4234 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4235 | */ | |
4236 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4237 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4238 | { | |
4239 | i.types[1].bitfield.byte = 1; | |
4240 | /* Ignore the suffix. */ | |
4241 | i.suffix = 0; | |
7697afb6 JB |
4242 | /* Convert to byte registers. */ |
4243 | if (i.types[1].bitfield.word) | |
4244 | j = 16; | |
4245 | else if (i.types[1].bitfield.dword) | |
4246 | j = 32; | |
4247 | else | |
4248 | j = 48; | |
4249 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4250 | j += 8; | |
4251 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4252 | } |
4253 | } | |
4254 | else if (flag_code == CODE_64BIT | |
389d00a5 | 4255 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
d3d50934 L |
4256 | && ((i.types[1].bitfield.qword |
4257 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4258 | && i.imm_operands == 1 |
4259 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4260 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4261 | && i.tm.extension_opcode == None |
4262 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4263 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
72aea328 JB |
4264 | && ((i.tm.base_opcode == 0x24 |
4265 | || i.tm.base_opcode == 0xa8) | |
b6f8c7c4 L |
4266 | || (i.tm.base_opcode == 0x80 |
4267 | && i.tm.extension_opcode == 0x4) | |
4268 | || ((i.tm.base_opcode == 0xf6 | |
507916b8 | 4269 | || (i.tm.base_opcode | 1) == 0xc7) |
b8364fa7 JB |
4270 | && i.tm.extension_opcode == 0x0))) |
4271 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4272 | && i.tm.base_opcode == 0x83 | |
4273 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4274 | || (i.types[0].bitfield.qword |
4275 | && ((i.reg_operands == 2 | |
4276 | && i.op[0].regs == i.op[1].regs | |
72aea328 JB |
4277 | && (i.tm.base_opcode == 0x30 |
4278 | || i.tm.base_opcode == 0x28)) | |
d3d50934 L |
4279 | || (i.reg_operands == 1 |
4280 | && i.operands == 1 | |
72aea328 | 4281 | && i.tm.base_opcode == 0x30))))) |
b6f8c7c4 L |
4282 | { |
4283 | /* Optimize: -O: | |
4284 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4285 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4286 | testq $imm31, %r64 -> testl $imm31, %r32 |
4287 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4288 | subq %r64, %r64 -> subl %r32, %r32 | |
4289 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4290 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4291 | */ | |
4292 | i.tm.opcode_modifier.norex64 = 1; | |
507916b8 | 4293 | if (i.tm.base_opcode == 0xb8 || (i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4294 | { |
4295 | /* Handle | |
4296 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4297 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4298 | */ | |
4299 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4300 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4301 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
4302 | i.types[0].bitfield.imm32 = 1; | |
4303 | i.types[0].bitfield.imm32s = 0; | |
4304 | i.types[0].bitfield.imm64 = 0; | |
4305 | i.types[1].bitfield.dword = 1; | |
4306 | i.types[1].bitfield.qword = 0; | |
507916b8 | 4307 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4308 | { |
4309 | /* Handle | |
4310 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4311 | */ | |
507916b8 | 4312 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4313 | i.tm.extension_opcode = None; |
507916b8 | 4314 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4315 | i.tm.opcode_modifier.modrm = 0; |
4316 | } | |
4317 | } | |
4318 | } | |
5641ec01 JB |
4319 | else if (optimize > 1 |
4320 | && !optimize_for_space | |
389d00a5 | 4321 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
5641ec01 JB |
4322 | && i.reg_operands == 2 |
4323 | && i.op[0].regs == i.op[1].regs | |
4324 | && ((i.tm.base_opcode & ~(Opcode_D | 1)) == 0x8 | |
4325 | || (i.tm.base_opcode & ~(Opcode_D | 1)) == 0x20) | |
4326 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) | |
4327 | { | |
4328 | /* Optimize: -O2: | |
4329 | andb %rN, %rN -> testb %rN, %rN | |
4330 | andw %rN, %rN -> testw %rN, %rN | |
4331 | andq %rN, %rN -> testq %rN, %rN | |
4332 | orb %rN, %rN -> testb %rN, %rN | |
4333 | orw %rN, %rN -> testw %rN, %rN | |
4334 | orq %rN, %rN -> testq %rN, %rN | |
4335 | ||
4336 | and outside of 64-bit mode | |
4337 | ||
4338 | andl %rN, %rN -> testl %rN, %rN | |
4339 | orl %rN, %rN -> testl %rN, %rN | |
4340 | */ | |
4341 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4342 | } | |
99112332 | 4343 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4344 | && i.op[0].regs == i.op[1].regs |
4345 | && !i.types[2].bitfield.xmmword | |
4346 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4347 | || ((!i.mask.reg || i.mask.zeroing) |
ca5312a2 | 4348 | && i.rounding.type == rc_none |
e771e7c9 | 4349 | && is_evex_encoding (&i.tm) |
80c34c38 | 4350 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4351 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
80c34c38 | 4352 | || i.tm.cpu_flags.bitfield.cpuavx512vl |
7091c612 | 4353 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4354 | && i.types[2].bitfield.ymmword)))) |
b6f8c7c4 | 4355 | && ((i.tm.base_opcode == 0x55 |
b6f8c7c4 | 4356 | || i.tm.base_opcode == 0x57 |
35648716 JB |
4357 | || i.tm.base_opcode == 0xdf |
4358 | || i.tm.base_opcode == 0xef | |
4359 | || i.tm.base_opcode == 0xf8 | |
4360 | || i.tm.base_opcode == 0xf9 | |
4361 | || i.tm.base_opcode == 0xfa | |
4362 | || i.tm.base_opcode == 0xfb | |
1424ad86 | 4363 | || i.tm.base_opcode == 0x42 |
35648716 | 4364 | || i.tm.base_opcode == 0x47) |
b6f8c7c4 L |
4365 | && i.tm.extension_opcode == None)) |
4366 | { | |
99112332 | 4367 | /* Optimize: -O1: |
8305403a L |
4368 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4369 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4370 | EVEX VOP %zmmM, %zmmM, %zmmN |
4371 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4372 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4373 | EVEX VOP %ymmM, %ymmM, %ymmN |
4374 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4375 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4376 | VEX VOP %ymmM, %ymmM, %ymmN |
4377 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4378 | VOP, one of vpandn and vpxor: | |
4379 | VEX VOP %ymmM, %ymmM, %ymmN | |
4380 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4381 | VOP, one of vpandnd and vpandnq: | |
4382 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4383 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4384 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4385 | EVEX VOP %ymmM, %ymmM, %ymmN |
4386 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4387 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4388 | VOP, one of vpxord and vpxorq: |
4389 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4390 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4391 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4392 | EVEX VOP %ymmM, %ymmM, %ymmN |
4393 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4394 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4395 | VOP, one of kxord and kxorq: |
4396 | VEX VOP %kM, %kM, %kN | |
4397 | -> VEX kxorw %kM, %kM, %kN | |
4398 | VOP, one of kandnd and kandnq: | |
4399 | VEX VOP %kM, %kM, %kN | |
4400 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4401 | */ |
e771e7c9 | 4402 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4403 | { |
7b1d7ca1 | 4404 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4405 | { |
4406 | i.tm.opcode_modifier.vex = VEX128; | |
4407 | i.tm.opcode_modifier.vexw = VEXW0; | |
4408 | i.tm.opcode_modifier.evex = 0; | |
4409 | } | |
7b1d7ca1 | 4410 | else if (optimize > 1) |
dd22218c L |
4411 | i.tm.opcode_modifier.evex = EVEX128; |
4412 | else | |
4413 | return; | |
b6f8c7c4 | 4414 | } |
f74a6307 | 4415 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4416 | { |
35648716 | 4417 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4418 | i.tm.opcode_modifier.vexw = VEXW0; |
4419 | } | |
b6f8c7c4 L |
4420 | else |
4421 | i.tm.opcode_modifier.vex = VEX128; | |
4422 | ||
4423 | if (i.tm.opcode_modifier.vex) | |
4424 | for (j = 0; j < 3; j++) | |
4425 | { | |
4426 | i.types[j].bitfield.xmmword = 1; | |
4427 | i.types[j].bitfield.ymmword = 0; | |
4428 | } | |
4429 | } | |
392a5972 | 4430 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4431 | && !i.types[0].bitfield.zmmword |
392a5972 | 4432 | && !i.types[1].bitfield.zmmword |
6225c532 | 4433 | && !i.mask.reg |
5273a3cd | 4434 | && !i.broadcast.type |
97ed31ae | 4435 | && is_evex_encoding (&i.tm) |
35648716 JB |
4436 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4437 | || (i.tm.base_opcode & ~4) == 0xdb | |
4438 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4439 | && i.tm.extension_opcode == None) |
4440 | { | |
4441 | /* Optimize: -O1: | |
4442 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4443 | vmovdqu32 and vmovdqu64: | |
4444 | EVEX VOP %xmmM, %xmmN | |
4445 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4446 | EVEX VOP %ymmM, %ymmN | |
4447 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4448 | EVEX VOP %xmmM, mem | |
4449 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4450 | EVEX VOP %ymmM, mem | |
4451 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4452 | EVEX VOP mem, %xmmN | |
4453 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4454 | EVEX VOP mem, %ymmN | |
4455 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4456 | VOP, one of vpand, vpandn, vpor, vpxor: |
4457 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4458 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4459 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4460 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4461 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4462 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4463 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4464 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4465 | */ |
a0a1771e | 4466 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4467 | if (operand_type_check (i.types[j], disp) |
4468 | && i.op[j].disps->X_op == O_constant) | |
4469 | { | |
4470 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4471 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4472 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4473 | int evex_disp8, vex_disp8; | |
4474 | unsigned int memshift = i.memshift; | |
4475 | offsetT n = i.op[j].disps->X_add_number; | |
4476 | ||
4477 | evex_disp8 = fits_in_disp8 (n); | |
4478 | i.memshift = 0; | |
4479 | vex_disp8 = fits_in_disp8 (n); | |
4480 | if (evex_disp8 != vex_disp8) | |
4481 | { | |
4482 | i.memshift = memshift; | |
4483 | return; | |
4484 | } | |
4485 | ||
4486 | i.types[j].bitfield.disp8 = vex_disp8; | |
4487 | break; | |
4488 | } | |
35648716 JB |
4489 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4490 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4491 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4492 | i.tm.opcode_modifier.vex |
4493 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4494 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4495 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4496 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4497 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4498 | i.tm.opcode_modifier.evex = 0; |
4499 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4500 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4501 | i.tm.opcode_modifier.disp8memshift = 0; |
4502 | i.memshift = 0; | |
a0a1771e JB |
4503 | if (j < i.operands) |
4504 | i.types[j].bitfield.disp8 | |
4505 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4506 | } |
b6f8c7c4 L |
4507 | } |
4508 | ||
ae531041 L |
4509 | /* Return non-zero for load instruction. */ |
4510 | ||
4511 | static int | |
4512 | load_insn_p (void) | |
4513 | { | |
4514 | unsigned int dest; | |
4515 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4516 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4517 | ||
4518 | if (!any_vex_p) | |
4519 | { | |
a09f656b | 4520 | /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0, |
4521 | prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn, | |
4522 | bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */ | |
4523 | if (i.tm.opcode_modifier.anysize) | |
ae531041 L |
4524 | return 0; |
4525 | ||
389d00a5 JB |
4526 | /* pop. */ |
4527 | if (strcmp (i.tm.name, "pop") == 0) | |
4528 | return 1; | |
4529 | } | |
4530 | ||
4531 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE) | |
4532 | { | |
4533 | /* popf, popa. */ | |
4534 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 4535 | || i.tm.base_opcode == 0x61) |
ae531041 L |
4536 | return 1; |
4537 | ||
4538 | /* movs, cmps, lods, scas. */ | |
4539 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4540 | return 1; | |
4541 | ||
a09f656b | 4542 | /* outs, xlatb. */ |
4543 | if (base_opcode == 0x6f | |
4544 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4545 | return 1; |
a09f656b | 4546 | /* NB: For AMD-specific insns with implicit memory operands, |
4547 | they're intentionally not covered. */ | |
ae531041 L |
4548 | } |
4549 | ||
4550 | /* No memory operand. */ | |
4551 | if (!i.mem_operands) | |
4552 | return 0; | |
4553 | ||
4554 | if (any_vex_p) | |
4555 | { | |
4556 | /* vldmxcsr. */ | |
4557 | if (i.tm.base_opcode == 0xae | |
4558 | && i.tm.opcode_modifier.vex | |
441f6aca | 4559 | && i.tm.opcode_modifier.opcodespace == SPACE_0F |
35648716 | 4560 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE |
ae531041 L |
4561 | && i.tm.extension_opcode == 2) |
4562 | return 1; | |
4563 | } | |
389d00a5 | 4564 | else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE) |
ae531041 L |
4565 | { |
4566 | /* test, not, neg, mul, imul, div, idiv. */ | |
4567 | if ((i.tm.base_opcode == 0xf6 || i.tm.base_opcode == 0xf7) | |
4568 | && i.tm.extension_opcode != 1) | |
4569 | return 1; | |
4570 | ||
4571 | /* inc, dec. */ | |
4572 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
4573 | return 1; | |
4574 | ||
4575 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
4576 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
4577 | return 1; | |
4578 | ||
ae531041 L |
4579 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
4580 | if ((base_opcode == 0xc1 | |
4581 | || (i.tm.base_opcode >= 0xd0 && i.tm.base_opcode <= 0xd3)) | |
4582 | && i.tm.extension_opcode != 6) | |
4583 | return 1; | |
4584 | ||
ae531041 | 4585 | /* Check for x87 instructions. */ |
389d00a5 | 4586 | if (base_opcode >= 0xd8 && base_opcode <= 0xdf) |
ae531041 L |
4587 | { |
4588 | /* Skip fst, fstp, fstenv, fstcw. */ | |
4589 | if (i.tm.base_opcode == 0xd9 | |
4590 | && (i.tm.extension_opcode == 2 | |
4591 | || i.tm.extension_opcode == 3 | |
4592 | || i.tm.extension_opcode == 6 | |
4593 | || i.tm.extension_opcode == 7)) | |
4594 | return 0; | |
4595 | ||
4596 | /* Skip fisttp, fist, fistp, fstp. */ | |
4597 | if (i.tm.base_opcode == 0xdb | |
4598 | && (i.tm.extension_opcode == 1 | |
4599 | || i.tm.extension_opcode == 2 | |
4600 | || i.tm.extension_opcode == 3 | |
4601 | || i.tm.extension_opcode == 7)) | |
4602 | return 0; | |
4603 | ||
4604 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
4605 | if (i.tm.base_opcode == 0xdd | |
4606 | && (i.tm.extension_opcode == 1 | |
4607 | || i.tm.extension_opcode == 2 | |
4608 | || i.tm.extension_opcode == 3 | |
4609 | || i.tm.extension_opcode == 6 | |
4610 | || i.tm.extension_opcode == 7)) | |
4611 | return 0; | |
4612 | ||
4613 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
4614 | if (i.tm.base_opcode == 0xdf | |
4615 | && (i.tm.extension_opcode == 1 | |
4616 | || i.tm.extension_opcode == 2 | |
4617 | || i.tm.extension_opcode == 3 | |
4618 | || i.tm.extension_opcode == 6 | |
4619 | || i.tm.extension_opcode == 7)) | |
4620 | return 0; | |
4621 | ||
4622 | return 1; | |
4623 | } | |
4624 | } | |
389d00a5 JB |
4625 | else if (i.tm.opcode_modifier.opcodespace == SPACE_0F) |
4626 | { | |
4627 | /* bt, bts, btr, btc. */ | |
4628 | if (i.tm.base_opcode == 0xba | |
4629 | && (i.tm.extension_opcode >= 4 && i.tm.extension_opcode <= 7)) | |
4630 | return 1; | |
4631 | ||
4632 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
4633 | if (i.tm.base_opcode == 0xc7 | |
4634 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
4635 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
4636 | || i.tm.extension_opcode == 6)) | |
4637 | return 1; | |
4638 | ||
4639 | /* fxrstor, ldmxcsr, xrstor. */ | |
4640 | if (i.tm.base_opcode == 0xae | |
4641 | && (i.tm.extension_opcode == 1 | |
4642 | || i.tm.extension_opcode == 2 | |
4643 | || i.tm.extension_opcode == 5)) | |
4644 | return 1; | |
4645 | ||
4646 | /* lgdt, lidt, lmsw. */ | |
4647 | if (i.tm.base_opcode == 0x01 | |
4648 | && (i.tm.extension_opcode == 2 | |
4649 | || i.tm.extension_opcode == 3 | |
4650 | || i.tm.extension_opcode == 6)) | |
4651 | return 1; | |
4652 | } | |
ae531041 L |
4653 | |
4654 | dest = i.operands - 1; | |
4655 | ||
4656 | /* Check fake imm8 operand and 3 source operands. */ | |
4657 | if ((i.tm.opcode_modifier.immext | |
4658 | || i.tm.opcode_modifier.vexsources == VEX3SOURCES) | |
4659 | && i.types[dest].bitfield.imm8) | |
4660 | dest--; | |
4661 | ||
389d00a5 JB |
4662 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
4663 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE | |
ae531041 L |
4664 | && (base_opcode == 0x1 |
4665 | || base_opcode == 0x9 | |
4666 | || base_opcode == 0x11 | |
4667 | || base_opcode == 0x19 | |
4668 | || base_opcode == 0x21 | |
4669 | || base_opcode == 0x29 | |
4670 | || base_opcode == 0x31 | |
4671 | || base_opcode == 0x39 | |
389d00a5 JB |
4672 | || (base_opcode | 2) == 0x87)) |
4673 | return 1; | |
4674 | ||
4675 | /* xadd. */ | |
4676 | if (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
4677 | && base_opcode == 0xc1) | |
ae531041 L |
4678 | return 1; |
4679 | ||
4680 | /* Check for load instruction. */ | |
4681 | return (i.types[dest].bitfield.class != ClassNone | |
4682 | || i.types[dest].bitfield.instance == Accum); | |
4683 | } | |
4684 | ||
4685 | /* Output lfence, 0xfaee8, after instruction. */ | |
4686 | ||
4687 | static void | |
4688 | insert_lfence_after (void) | |
4689 | { | |
4690 | if (lfence_after_load && load_insn_p ()) | |
4691 | { | |
a09f656b | 4692 | /* There are also two REP string instructions that require |
4693 | special treatment. Specifically, the compare string (CMPS) | |
4694 | and scan string (SCAS) instructions set EFLAGS in a manner | |
4695 | that depends on the data being compared/scanned. When used | |
4696 | with a REP prefix, the number of iterations may therefore | |
4697 | vary depending on this data. If the data is a program secret | |
4698 | chosen by the adversary using an LVI method, | |
4699 | then this data-dependent behavior may leak some aspect | |
4700 | of the secret. */ | |
4701 | if (((i.tm.base_opcode | 0x1) == 0xa7 | |
4702 | || (i.tm.base_opcode | 0x1) == 0xaf) | |
4703 | && i.prefix[REP_PREFIX]) | |
4704 | { | |
4705 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
4706 | i.tm.name); | |
4707 | } | |
ae531041 L |
4708 | char *p = frag_more (3); |
4709 | *p++ = 0xf; | |
4710 | *p++ = 0xae; | |
4711 | *p = 0xe8; | |
4712 | } | |
4713 | } | |
4714 | ||
4715 | /* Output lfence, 0xfaee8, before instruction. */ | |
4716 | ||
4717 | static void | |
4718 | insert_lfence_before (void) | |
4719 | { | |
4720 | char *p; | |
4721 | ||
389d00a5 | 4722 | if (i.tm.opcode_modifier.opcodespace != SPACE_BASE) |
ae531041 L |
4723 | return; |
4724 | ||
4725 | if (i.tm.base_opcode == 0xff | |
4726 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
4727 | { | |
4728 | /* Insert lfence before indirect branch if needed. */ | |
4729 | ||
4730 | if (lfence_before_indirect_branch == lfence_branch_none) | |
4731 | return; | |
4732 | ||
4733 | if (i.operands != 1) | |
4734 | abort (); | |
4735 | ||
4736 | if (i.reg_operands == 1) | |
4737 | { | |
4738 | /* Indirect branch via register. Don't insert lfence with | |
4739 | -mlfence-after-load=yes. */ | |
4740 | if (lfence_after_load | |
4741 | || lfence_before_indirect_branch == lfence_branch_memory) | |
4742 | return; | |
4743 | } | |
4744 | else if (i.mem_operands == 1 | |
4745 | && lfence_before_indirect_branch != lfence_branch_register) | |
4746 | { | |
4747 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
4748 | i.tm.name); | |
4749 | return; | |
4750 | } | |
4751 | else | |
4752 | return; | |
4753 | ||
4754 | if (last_insn.kind != last_insn_other | |
4755 | && last_insn.seg == now_seg) | |
4756 | { | |
4757 | as_warn_where (last_insn.file, last_insn.line, | |
4758 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), | |
4759 | last_insn.name, i.tm.name); | |
4760 | return; | |
4761 | } | |
4762 | ||
4763 | p = frag_more (3); | |
4764 | *p++ = 0xf; | |
4765 | *p++ = 0xae; | |
4766 | *p = 0xe8; | |
4767 | return; | |
4768 | } | |
4769 | ||
503648e4 | 4770 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 L |
4771 | if (lfence_before_ret != lfence_before_ret_none |
4772 | && (i.tm.base_opcode == 0xc2 | |
503648e4 | 4773 | || i.tm.base_opcode == 0xc3)) |
ae531041 L |
4774 | { |
4775 | if (last_insn.kind != last_insn_other | |
4776 | && last_insn.seg == now_seg) | |
4777 | { | |
4778 | as_warn_where (last_insn.file, last_insn.line, | |
4779 | _("`%s` skips -mlfence-before-ret on `%s`"), | |
4780 | last_insn.name, i.tm.name); | |
4781 | return; | |
4782 | } | |
a09f656b | 4783 | |
a09f656b | 4784 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 4785 | char prefix = flag_code == CODE_64BIT |
4786 | ? 0x48 | |
4787 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 4788 | |
4789 | if (lfence_before_ret == lfence_before_ret_not) | |
4790 | { | |
4791 | /* not: 0xf71424, may add prefix | |
4792 | for operand size override or 64-bit code. */ | |
4793 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
4794 | if (prefix) | |
4795 | *p++ = prefix; | |
ae531041 L |
4796 | *p++ = 0xf7; |
4797 | *p++ = 0x14; | |
4798 | *p++ = 0x24; | |
a09f656b | 4799 | if (prefix) |
4800 | *p++ = prefix; | |
ae531041 L |
4801 | *p++ = 0xf7; |
4802 | *p++ = 0x14; | |
4803 | *p++ = 0x24; | |
4804 | } | |
a09f656b | 4805 | else |
4806 | { | |
4807 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
4808 | if (prefix) | |
4809 | *p++ = prefix; | |
4810 | if (lfence_before_ret == lfence_before_ret_or) | |
4811 | { | |
4812 | /* or: 0x830c2400, may add prefix | |
4813 | for operand size override or 64-bit code. */ | |
4814 | *p++ = 0x83; | |
4815 | *p++ = 0x0c; | |
4816 | } | |
4817 | else | |
4818 | { | |
4819 | /* shl: 0xc1242400, may add prefix | |
4820 | for operand size override or 64-bit code. */ | |
4821 | *p++ = 0xc1; | |
4822 | *p++ = 0x24; | |
4823 | } | |
4824 | ||
4825 | *p++ = 0x24; | |
4826 | *p++ = 0x0; | |
4827 | } | |
4828 | ||
ae531041 L |
4829 | *p++ = 0xf; |
4830 | *p++ = 0xae; | |
4831 | *p = 0xe8; | |
4832 | } | |
4833 | } | |
4834 | ||
252b5132 RH |
4835 | /* This is the guts of the machine-dependent assembler. LINE points to a |
4836 | machine dependent instruction. This function is supposed to emit | |
4837 | the frags/bytes it assembles to. */ | |
4838 | ||
4839 | void | |
65da13b5 | 4840 | md_assemble (char *line) |
252b5132 | 4841 | { |
40fb9820 | 4842 | unsigned int j; |
83b16ac6 | 4843 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix; |
d3ce72d0 | 4844 | const insn_template *t; |
252b5132 | 4845 | |
47926f60 | 4846 | /* Initialize globals. */ |
252b5132 | 4847 | memset (&i, '\0', sizeof (i)); |
ca5312a2 | 4848 | i.rounding.type = rc_none; |
252b5132 | 4849 | for (j = 0; j < MAX_OPERANDS; j++) |
1ae12ab7 | 4850 | i.reloc[j] = NO_RELOC; |
252b5132 RH |
4851 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
4852 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
ce8a8b2f | 4853 | save_stack_p = save_stack; |
252b5132 RH |
4854 | |
4855 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
4856 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 4857 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 4858 | |
29b0f896 AM |
4859 | line = parse_insn (line, mnemonic); |
4860 | if (line == NULL) | |
4861 | return; | |
83b16ac6 | 4862 | mnem_suffix = i.suffix; |
252b5132 | 4863 | |
29b0f896 | 4864 | line = parse_operands (line, mnemonic); |
ee86248c | 4865 | this_operand = -1; |
8325cc63 JB |
4866 | xfree (i.memop1_string); |
4867 | i.memop1_string = NULL; | |
29b0f896 AM |
4868 | if (line == NULL) |
4869 | return; | |
252b5132 | 4870 | |
29b0f896 AM |
4871 | /* Now we've parsed the mnemonic into a set of templates, and have the |
4872 | operands at hand. */ | |
4873 | ||
b630c145 | 4874 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 JB |
4875 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
4876 | "rmpadjust", and "rmpupdate". We also don't reverse intersegment "jmp" | |
4877 | and "call" instructions with 2 immediate operands so that the immediate | |
4878 | segment precedes the offset consistently in Intel and AT&T modes. */ | |
4d456e3d L |
4879 | if (intel_syntax |
4880 | && i.operands > 1 | |
29b0f896 | 4881 | && (strcmp (mnemonic, "bound") != 0) |
c0e54661 | 4882 | && (strncmp (mnemonic, "invlpg", 6) != 0) |
d34049e8 ML |
4883 | && !startswith (mnemonic, "monitor") |
4884 | && !startswith (mnemonic, "mwait") | |
c0e54661 | 4885 | && (strcmp (mnemonic, "pvalidate") != 0) |
d34049e8 | 4886 | && !startswith (mnemonic, "rmp") |
b630c145 JB |
4887 | && (strcmp (mnemonic, "tpause") != 0) |
4888 | && (strcmp (mnemonic, "umwait") != 0) | |
40fb9820 L |
4889 | && !(operand_type_check (i.types[0], imm) |
4890 | && operand_type_check (i.types[1], imm))) | |
29b0f896 AM |
4891 | swap_operands (); |
4892 | ||
ec56d5c0 JB |
4893 | /* The order of the immediates should be reversed |
4894 | for 2 immediates extrq and insertq instructions */ | |
4895 | if (i.imm_operands == 2 | |
4896 | && (strcmp (mnemonic, "extrq") == 0 | |
4897 | || strcmp (mnemonic, "insertq") == 0)) | |
4898 | swap_2_operands (0, 1); | |
4899 | ||
29b0f896 AM |
4900 | if (i.imm_operands) |
4901 | optimize_imm (); | |
4902 | ||
a9aabc23 | 4903 | if (i.disp_operands && !want_disp32 (current_templates->start)) |
cce08655 JB |
4904 | { |
4905 | for (j = 0; j < i.operands; ++j) | |
4906 | { | |
4907 | const expressionS *exp = i.op[j].disps; | |
4908 | ||
4909 | if (!operand_type_check (i.types[j], disp)) | |
4910 | continue; | |
4911 | ||
4912 | if (exp->X_op != O_constant) | |
4913 | continue; | |
4914 | ||
4915 | /* Since displacement is signed extended to 64bit, don't allow | |
4916 | disp32 and turn off disp32s if they are out of range. */ | |
4917 | i.types[j].bitfield.disp32 = 0; | |
4918 | if (fits_in_signed_long (exp->X_add_number)) | |
4919 | continue; | |
4920 | ||
4921 | i.types[j].bitfield.disp32s = 0; | |
4922 | if (i.types[j].bitfield.baseindex) | |
4923 | { | |
4924 | as_bad (_("0x%" BFD_VMA_FMT "x out of range of signed 32bit displacement"), | |
4925 | exp->X_add_number); | |
4926 | return; | |
4927 | } | |
4928 | } | |
4929 | } | |
4930 | ||
b300c311 L |
4931 | /* Don't optimize displacement for movabs since it only takes 64bit |
4932 | displacement. */ | |
4933 | if (i.disp_operands | |
a501d77e | 4934 | && i.disp_encoding != disp_encoding_32bit |
862be3fb L |
4935 | && (flag_code != CODE_64BIT |
4936 | || strcmp (mnemonic, "movabs") != 0)) | |
4937 | optimize_disp (); | |
29b0f896 AM |
4938 | |
4939 | /* Next, we find a template that matches the given insn, | |
4940 | making sure the overlap of the given operands types is consistent | |
4941 | with the template operand types. */ | |
252b5132 | 4942 | |
83b16ac6 | 4943 | if (!(t = match_template (mnem_suffix))) |
29b0f896 | 4944 | return; |
252b5132 | 4945 | |
7bab8ab5 | 4946 | if (sse_check != check_none |
81f8a913 | 4947 | && !i.tm.opcode_modifier.noavx |
6e3e5c9e | 4948 | && !i.tm.cpu_flags.bitfield.cpuavx |
569d50f1 | 4949 | && !i.tm.cpu_flags.bitfield.cpuavx512f |
daf50ae7 L |
4950 | && (i.tm.cpu_flags.bitfield.cpusse |
4951 | || i.tm.cpu_flags.bitfield.cpusse2 | |
4952 | || i.tm.cpu_flags.bitfield.cpusse3 | |
4953 | || i.tm.cpu_flags.bitfield.cpussse3 | |
4954 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
6e3e5c9e JB |
4955 | || i.tm.cpu_flags.bitfield.cpusse4_2 |
4956 | || i.tm.cpu_flags.bitfield.cpupclmul | |
4957 | || i.tm.cpu_flags.bitfield.cpuaes | |
569d50f1 | 4958 | || i.tm.cpu_flags.bitfield.cpusha |
6e3e5c9e | 4959 | || i.tm.cpu_flags.bitfield.cpugfni)) |
daf50ae7 | 4960 | { |
7bab8ab5 | 4961 | (sse_check == check_warning |
daf50ae7 L |
4962 | ? as_warn |
4963 | : as_bad) (_("SSE instruction `%s' is used"), i.tm.name); | |
4964 | } | |
4965 | ||
40fb9820 | 4966 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
4967 | if (!add_prefix (FWAIT_OPCODE)) |
4968 | return; | |
252b5132 | 4969 | |
d5de92cf | 4970 | /* Check if REP prefix is OK. */ |
742732c7 | 4971 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
4972 | { |
4973 | as_bad (_("invalid instruction `%s' after `%s'"), | |
4974 | i.tm.name, i.rep_prefix); | |
4975 | return; | |
4976 | } | |
4977 | ||
c1ba0266 L |
4978 | /* Check for lock without a lockable instruction. Destination operand |
4979 | must be memory unless it is xchg (0x86). */ | |
c32fa91d | 4980 | if (i.prefix[LOCK_PREFIX] |
742732c7 | 4981 | && (i.tm.opcode_modifier.prefixok < PrefixLock |
c1ba0266 L |
4982 | || i.mem_operands == 0 |
4983 | || (i.tm.base_opcode != 0x86 | |
8dc0818e | 4984 | && !(i.flags[i.operands - 1] & Operand_Mem)))) |
c32fa91d L |
4985 | { |
4986 | as_bad (_("expecting lockable instruction after `lock'")); | |
4987 | return; | |
4988 | } | |
4989 | ||
40d231b4 JB |
4990 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
4991 | if (i.prefix[DATA_PREFIX] | |
4992 | && (is_any_vex_encoding (&i.tm) | |
4993 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
4994 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX)) | |
7a8655d2 JB |
4995 | { |
4996 | as_bad (_("data size prefix invalid with `%s'"), i.tm.name); | |
4997 | return; | |
4998 | } | |
4999 | ||
42164a71 | 5000 | /* Check if HLE prefix is OK. */ |
165de32a | 5001 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
5002 | return; |
5003 | ||
7e8b059b L |
5004 | /* Check BND prefix. */ |
5005 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
5006 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
5007 | ||
04ef582a | 5008 | /* Check NOTRACK prefix. */ |
742732c7 | 5009 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 5010 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 5011 | |
327e8c42 JB |
5012 | if (i.tm.cpu_flags.bitfield.cpumpx) |
5013 | { | |
5014 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
5015 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
5016 | else if (flag_code != CODE_16BIT | |
5017 | ? i.prefix[ADDR_PREFIX] | |
5018 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
5019 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
5020 | } | |
7e8b059b L |
5021 | |
5022 | /* Insert BND prefix. */ | |
76d3a78a JB |
5023 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
5024 | { | |
5025 | if (!i.prefix[BND_PREFIX]) | |
5026 | add_prefix (BND_PREFIX_OPCODE); | |
5027 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
5028 | { | |
5029 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
5030 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
5031 | } | |
5032 | } | |
7e8b059b | 5033 | |
29b0f896 | 5034 | /* Check string instruction segment overrides. */ |
51c8edf6 | 5035 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 5036 | { |
51c8edf6 | 5037 | gas_assert (i.mem_operands); |
29b0f896 | 5038 | if (!check_string ()) |
5dd0794d | 5039 | return; |
fc0763e6 | 5040 | i.disp_operands = 0; |
29b0f896 | 5041 | } |
5dd0794d | 5042 | |
b6f8c7c4 L |
5043 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
5044 | optimize_encoding (); | |
5045 | ||
29b0f896 AM |
5046 | if (!process_suffix ()) |
5047 | return; | |
e413e4e9 | 5048 | |
921eafea | 5049 | /* Update operand types and check extended states. */ |
bc0844ae | 5050 | for (j = 0; j < i.operands; j++) |
921eafea L |
5051 | { |
5052 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 5053 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
5054 | { |
5055 | default: | |
5056 | break; | |
5057 | case RegMMX: | |
5058 | i.xstate |= xstate_mmx; | |
5059 | break; | |
5060 | case RegMask: | |
32930e4e | 5061 | i.xstate |= xstate_mask; |
921eafea L |
5062 | break; |
5063 | case RegSIMD: | |
3d70986f | 5064 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 5065 | i.xstate |= xstate_tmm; |
3d70986f | 5066 | else if (i.tm.operand_types[j].bitfield.zmmword) |
921eafea | 5067 | i.xstate |= xstate_zmm; |
3d70986f | 5068 | else if (i.tm.operand_types[j].bitfield.ymmword) |
921eafea | 5069 | i.xstate |= xstate_ymm; |
3d70986f | 5070 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
5071 | i.xstate |= xstate_xmm; |
5072 | break; | |
5073 | } | |
5074 | } | |
bc0844ae | 5075 | |
29b0f896 AM |
5076 | /* Make still unresolved immediate matches conform to size of immediate |
5077 | given in i.suffix. */ | |
5078 | if (!finalize_imm ()) | |
5079 | return; | |
252b5132 | 5080 | |
40fb9820 | 5081 | if (i.types[0].bitfield.imm1) |
29b0f896 | 5082 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 5083 | |
9afe6eb8 L |
5084 | /* We only need to check those implicit registers for instructions |
5085 | with 3 operands or less. */ | |
5086 | if (i.operands <= 3) | |
5087 | for (j = 0; j < i.operands; j++) | |
75e5731b JB |
5088 | if (i.types[j].bitfield.instance != InstanceNone |
5089 | && !i.types[j].bitfield.xmmword) | |
9afe6eb8 | 5090 | i.reg_operands--; |
40fb9820 | 5091 | |
29b0f896 AM |
5092 | /* For insns with operands there are more diddles to do to the opcode. */ |
5093 | if (i.operands) | |
5094 | { | |
5095 | if (!process_operands ()) | |
5096 | return; | |
5097 | } | |
8c190ce0 | 5098 | else if (!quiet_warnings && i.tm.opcode_modifier.ugh) |
29b0f896 AM |
5099 | { |
5100 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
5101 | as_warn (_("translating to `%sp'"), i.tm.name); | |
5102 | } | |
252b5132 | 5103 | |
7a8655d2 | 5104 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 5105 | { |
c1dc7af5 | 5106 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 5107 | { |
c1dc7af5 | 5108 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
9e5e5283 L |
5109 | i.tm.name); |
5110 | return; | |
5111 | } | |
c0f3af97 | 5112 | |
0b9404fd JB |
5113 | /* Check for explicit REX prefix. */ |
5114 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
5115 | { | |
5116 | as_bad (_("REX prefix invalid with `%s'"), i.tm.name); | |
5117 | return; | |
5118 | } | |
5119 | ||
9e5e5283 L |
5120 | if (i.tm.opcode_modifier.vex) |
5121 | build_vex_prefix (t); | |
5122 | else | |
5123 | build_evex_prefix (); | |
0b9404fd JB |
5124 | |
5125 | /* The individual REX.RXBW bits got consumed. */ | |
5126 | i.rex &= REX_OPCODE; | |
9e5e5283 | 5127 | } |
43234a1e | 5128 | |
5dd85c99 SP |
5129 | /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4 |
5130 | instructions may define INT_OPCODE as well, so avoid this corner | |
5131 | case for those instructions that use MODRM. */ | |
389d00a5 JB |
5132 | if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
5133 | && i.tm.base_opcode == INT_OPCODE | |
a6461c02 SP |
5134 | && !i.tm.opcode_modifier.modrm |
5135 | && i.op[0].imms->X_add_number == 3) | |
29b0f896 AM |
5136 | { |
5137 | i.tm.base_opcode = INT3_OPCODE; | |
5138 | i.imm_operands = 0; | |
5139 | } | |
252b5132 | 5140 | |
0cfa3eb3 JB |
5141 | if ((i.tm.opcode_modifier.jump == JUMP |
5142 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
5143 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
5144 | && i.op[0].disps->X_op == O_constant) |
5145 | { | |
5146 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
5147 | the absolute address given by the constant. Since ix86 jumps and | |
5148 | calls are pc relative, we need to generate a reloc. */ | |
5149 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
5150 | i.op[0].disps->X_op = O_symbol; | |
5151 | } | |
252b5132 | 5152 | |
29b0f896 AM |
5153 | /* For 8 bit registers we need an empty rex prefix. Also if the |
5154 | instruction already has a prefix, we need to convert old | |
5155 | registers to new ones. */ | |
773f551c | 5156 | |
bab6aec1 | 5157 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 5158 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 5159 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 5160 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
5161 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
5162 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
5163 | && i.rex != 0)) |
5164 | { | |
5165 | int x; | |
726c5dcd | 5166 | |
29b0f896 AM |
5167 | i.rex |= REX_OPCODE; |
5168 | for (x = 0; x < 2; x++) | |
5169 | { | |
5170 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 5171 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 5172 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 5173 | { |
3f93af61 | 5174 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
5175 | /* In case it is "hi" register, give up. */ |
5176 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 5177 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 5178 | "instruction requiring REX prefix."), |
a540244d | 5179 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 5180 | |
29b0f896 AM |
5181 | /* Otherwise it is equivalent to the extended register. |
5182 | Since the encoding doesn't change this is merely | |
5183 | cosmetic cleanup for debug output. */ | |
5184 | ||
5185 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 5186 | } |
29b0f896 AM |
5187 | } |
5188 | } | |
773f551c | 5189 | |
6b6b6807 L |
5190 | if (i.rex == 0 && i.rex_encoding) |
5191 | { | |
5192 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 5193 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
5194 | the REX_OPCODE byte. */ |
5195 | int x; | |
5196 | for (x = 0; x < 2; x++) | |
bab6aec1 | 5197 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
5198 | && i.types[x].bitfield.byte |
5199 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
5200 | && i.op[x].regs->reg_num > 3) | |
5201 | { | |
3f93af61 | 5202 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
5b7c81bd | 5203 | i.rex_encoding = false; |
6b6b6807 L |
5204 | break; |
5205 | } | |
5206 | ||
5207 | if (i.rex_encoding) | |
5208 | i.rex = REX_OPCODE; | |
5209 | } | |
5210 | ||
7ab9ffdd | 5211 | if (i.rex != 0) |
29b0f896 AM |
5212 | add_prefix (REX_OPCODE | i.rex); |
5213 | ||
ae531041 L |
5214 | insert_lfence_before (); |
5215 | ||
29b0f896 AM |
5216 | /* We are ready to output the insn. */ |
5217 | output_insn (); | |
e379e5f3 | 5218 | |
ae531041 L |
5219 | insert_lfence_after (); |
5220 | ||
e379e5f3 L |
5221 | last_insn.seg = now_seg; |
5222 | ||
5223 | if (i.tm.opcode_modifier.isprefix) | |
5224 | { | |
5225 | last_insn.kind = last_insn_prefix; | |
5226 | last_insn.name = i.tm.name; | |
5227 | last_insn.file = as_where (&last_insn.line); | |
5228 | } | |
5229 | else | |
5230 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
5231 | } |
5232 | ||
5233 | static char * | |
e3bb37b5 | 5234 | parse_insn (char *line, char *mnemonic) |
29b0f896 AM |
5235 | { |
5236 | char *l = line; | |
5237 | char *token_start = l; | |
5238 | char *mnem_p; | |
5c6af06e | 5239 | int supported; |
d3ce72d0 | 5240 | const insn_template *t; |
b6169b20 | 5241 | char *dot_p = NULL; |
29b0f896 | 5242 | |
29b0f896 AM |
5243 | while (1) |
5244 | { | |
5245 | mnem_p = mnemonic; | |
5246 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) | |
5247 | { | |
b6169b20 L |
5248 | if (*mnem_p == '.') |
5249 | dot_p = mnem_p; | |
29b0f896 AM |
5250 | mnem_p++; |
5251 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5252 | { |
29b0f896 AM |
5253 | as_bad (_("no such instruction: `%s'"), token_start); |
5254 | return NULL; | |
5255 | } | |
5256 | l++; | |
5257 | } | |
5258 | if (!is_space_char (*l) | |
5259 | && *l != END_OF_INSN | |
e44823cf JB |
5260 | && (intel_syntax |
5261 | || (*l != PREFIX_SEPARATOR | |
5262 | && *l != ','))) | |
29b0f896 AM |
5263 | { |
5264 | as_bad (_("invalid character %s in mnemonic"), | |
5265 | output_invalid (*l)); | |
5266 | return NULL; | |
5267 | } | |
5268 | if (token_start == l) | |
5269 | { | |
e44823cf | 5270 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5271 | as_bad (_("expecting prefix; got nothing")); |
5272 | else | |
5273 | as_bad (_("expecting mnemonic; got nothing")); | |
5274 | return NULL; | |
5275 | } | |
45288df1 | 5276 | |
29b0f896 | 5277 | /* Look up instruction (or prefix) via hash table. */ |
629310ab | 5278 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
47926f60 | 5279 | |
29b0f896 AM |
5280 | if (*l != END_OF_INSN |
5281 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
5282 | && current_templates | |
40fb9820 | 5283 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 5284 | { |
c6fb90c8 | 5285 | if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags)) |
2dd88dca JB |
5286 | { |
5287 | as_bad ((flag_code != CODE_64BIT | |
5288 | ? _("`%s' is only supported in 64-bit mode") | |
5289 | : _("`%s' is not supported in 64-bit mode")), | |
5290 | current_templates->start->name); | |
5291 | return NULL; | |
5292 | } | |
29b0f896 AM |
5293 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5294 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
5295 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
5296 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5297 | && flag_code != CODE_64BIT |
673fe0f0 | 5298 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5299 | ^ (flag_code == CODE_16BIT))) |
5300 | { | |
5301 | as_bad (_("redundant %s prefix"), | |
5302 | current_templates->start->name); | |
5303 | return NULL; | |
45288df1 | 5304 | } |
31184569 JB |
5305 | |
5306 | if (current_templates->start->base_opcode == PSEUDO_PREFIX) | |
29b0f896 | 5307 | { |
86fa6981 | 5308 | /* Handle pseudo prefixes. */ |
31184569 | 5309 | switch (current_templates->start->extension_opcode) |
86fa6981 | 5310 | { |
41eb8e88 | 5311 | case Prefix_Disp8: |
86fa6981 L |
5312 | /* {disp8} */ |
5313 | i.disp_encoding = disp_encoding_8bit; | |
5314 | break; | |
41eb8e88 L |
5315 | case Prefix_Disp16: |
5316 | /* {disp16} */ | |
5317 | i.disp_encoding = disp_encoding_16bit; | |
5318 | break; | |
5319 | case Prefix_Disp32: | |
86fa6981 L |
5320 | /* {disp32} */ |
5321 | i.disp_encoding = disp_encoding_32bit; | |
5322 | break; | |
41eb8e88 | 5323 | case Prefix_Load: |
86fa6981 L |
5324 | /* {load} */ |
5325 | i.dir_encoding = dir_encoding_load; | |
5326 | break; | |
41eb8e88 | 5327 | case Prefix_Store: |
86fa6981 L |
5328 | /* {store} */ |
5329 | i.dir_encoding = dir_encoding_store; | |
5330 | break; | |
41eb8e88 | 5331 | case Prefix_VEX: |
42e04b36 L |
5332 | /* {vex} */ |
5333 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 | 5334 | break; |
41eb8e88 | 5335 | case Prefix_VEX3: |
86fa6981 L |
5336 | /* {vex3} */ |
5337 | i.vec_encoding = vex_encoding_vex3; | |
5338 | break; | |
41eb8e88 | 5339 | case Prefix_EVEX: |
86fa6981 L |
5340 | /* {evex} */ |
5341 | i.vec_encoding = vex_encoding_evex; | |
5342 | break; | |
41eb8e88 | 5343 | case Prefix_REX: |
6b6b6807 | 5344 | /* {rex} */ |
5b7c81bd | 5345 | i.rex_encoding = true; |
6b6b6807 | 5346 | break; |
41eb8e88 | 5347 | case Prefix_NoOptimize: |
b6f8c7c4 | 5348 | /* {nooptimize} */ |
5b7c81bd | 5349 | i.no_optimize = true; |
b6f8c7c4 | 5350 | break; |
86fa6981 L |
5351 | default: |
5352 | abort (); | |
5353 | } | |
5354 | } | |
5355 | else | |
5356 | { | |
5357 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 5358 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 5359 | { |
4e9ac44a L |
5360 | case PREFIX_EXIST: |
5361 | return NULL; | |
5362 | case PREFIX_DS: | |
d777820b | 5363 | if (current_templates->start->cpu_flags.bitfield.cpuibt) |
4e9ac44a L |
5364 | i.notrack_prefix = current_templates->start->name; |
5365 | break; | |
5366 | case PREFIX_REP: | |
5367 | if (current_templates->start->cpu_flags.bitfield.cpuhle) | |
5368 | i.hle_prefix = current_templates->start->name; | |
5369 | else if (current_templates->start->cpu_flags.bitfield.cpumpx) | |
5370 | i.bnd_prefix = current_templates->start->name; | |
5371 | else | |
5372 | i.rep_prefix = current_templates->start->name; | |
5373 | break; | |
5374 | default: | |
5375 | break; | |
86fa6981 | 5376 | } |
29b0f896 AM |
5377 | } |
5378 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
5379 | token_start = ++l; | |
5380 | } | |
5381 | else | |
5382 | break; | |
5383 | } | |
45288df1 | 5384 | |
30a55f88 | 5385 | if (!current_templates) |
b6169b20 | 5386 | { |
07d5e953 JB |
5387 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
5388 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 5389 | encoding. */ |
30a55f88 | 5390 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 5391 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 5392 | else if (mnem_p - 3 == dot_p |
a501d77e L |
5393 | && dot_p[1] == 'd' |
5394 | && dot_p[2] == '8') | |
5395 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 5396 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
5397 | && dot_p[1] == 'd' |
5398 | && dot_p[2] == '3' | |
5399 | && dot_p[3] == '2') | |
a501d77e | 5400 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
5401 | else |
5402 | goto check_suffix; | |
5403 | mnem_p = dot_p; | |
5404 | *dot_p = '\0'; | |
629310ab | 5405 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
b6169b20 L |
5406 | } |
5407 | ||
29b0f896 AM |
5408 | if (!current_templates) |
5409 | { | |
dc1e8a47 | 5410 | check_suffix: |
1c529385 | 5411 | if (mnem_p > mnemonic) |
29b0f896 | 5412 | { |
1c529385 LH |
5413 | /* See if we can get a match by trimming off a suffix. */ |
5414 | switch (mnem_p[-1]) | |
29b0f896 | 5415 | { |
1c529385 LH |
5416 | case WORD_MNEM_SUFFIX: |
5417 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
5418 | i.suffix = SHORT_MNEM_SUFFIX; |
5419 | else | |
1c529385 LH |
5420 | /* Fall through. */ |
5421 | case BYTE_MNEM_SUFFIX: | |
5422 | case QWORD_MNEM_SUFFIX: | |
5423 | i.suffix = mnem_p[-1]; | |
29b0f896 | 5424 | mnem_p[-1] = '\0'; |
fe0e921f AM |
5425 | current_templates |
5426 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5427 | break; |
5428 | case SHORT_MNEM_SUFFIX: | |
5429 | case LONG_MNEM_SUFFIX: | |
5430 | if (!intel_syntax) | |
5431 | { | |
5432 | i.suffix = mnem_p[-1]; | |
5433 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5434 | current_templates |
5435 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5436 | } |
5437 | break; | |
5438 | ||
5439 | /* Intel Syntax. */ | |
5440 | case 'd': | |
5441 | if (intel_syntax) | |
5442 | { | |
5443 | if (intel_float_operand (mnemonic) == 1) | |
5444 | i.suffix = SHORT_MNEM_SUFFIX; | |
5445 | else | |
5446 | i.suffix = LONG_MNEM_SUFFIX; | |
5447 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5448 | current_templates |
5449 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5450 | } |
5451 | break; | |
29b0f896 | 5452 | } |
29b0f896 | 5453 | } |
1c529385 | 5454 | |
29b0f896 AM |
5455 | if (!current_templates) |
5456 | { | |
5457 | as_bad (_("no such instruction: `%s'"), token_start); | |
5458 | return NULL; | |
5459 | } | |
5460 | } | |
252b5132 | 5461 | |
0cfa3eb3 JB |
5462 | if (current_templates->start->opcode_modifier.jump == JUMP |
5463 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
5464 | { |
5465 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
5466 | predict taken and predict not taken respectively. | |
5467 | I'm not sure that branch hints actually do anything on loop | |
5468 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
5469 | may work in the future and it doesn't hurt to accept them | |
5470 | now. */ | |
5471 | if (l[0] == ',' && l[1] == 'p') | |
5472 | { | |
5473 | if (l[2] == 't') | |
5474 | { | |
5475 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
5476 | return NULL; | |
5477 | l += 3; | |
5478 | } | |
5479 | else if (l[2] == 'n') | |
5480 | { | |
5481 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
5482 | return NULL; | |
5483 | l += 3; | |
5484 | } | |
5485 | } | |
5486 | } | |
5487 | /* Any other comma loses. */ | |
5488 | if (*l == ',') | |
5489 | { | |
5490 | as_bad (_("invalid character %s in mnemonic"), | |
5491 | output_invalid (*l)); | |
5492 | return NULL; | |
5493 | } | |
252b5132 | 5494 | |
29b0f896 | 5495 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
5496 | supported = 0; |
5497 | for (t = current_templates->start; t < current_templates->end; ++t) | |
5498 | { | |
c0f3af97 L |
5499 | supported |= cpu_flags_match (t); |
5500 | if (supported == CPU_FLAGS_PERFECT_MATCH) | |
548d0ee6 JB |
5501 | { |
5502 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT)) | |
5503 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
3629bb00 | 5504 | |
548d0ee6 JB |
5505 | return l; |
5506 | } | |
29b0f896 | 5507 | } |
3629bb00 | 5508 | |
548d0ee6 JB |
5509 | if (!(supported & CPU_FLAGS_64BIT_MATCH)) |
5510 | as_bad (flag_code == CODE_64BIT | |
5511 | ? _("`%s' is not supported in 64-bit mode") | |
5512 | : _("`%s' is only supported in 64-bit mode"), | |
5513 | current_templates->start->name); | |
5514 | else | |
5515 | as_bad (_("`%s' is not supported on `%s%s'"), | |
5516 | current_templates->start->name, | |
5517 | cpu_arch_name ? cpu_arch_name : default_arch, | |
5518 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
252b5132 | 5519 | |
548d0ee6 | 5520 | return NULL; |
29b0f896 | 5521 | } |
252b5132 | 5522 | |
29b0f896 | 5523 | static char * |
e3bb37b5 | 5524 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
5525 | { |
5526 | char *token_start; | |
3138f287 | 5527 | |
29b0f896 AM |
5528 | /* 1 if operand is pending after ','. */ |
5529 | unsigned int expecting_operand = 0; | |
252b5132 | 5530 | |
29b0f896 AM |
5531 | /* Non-zero if operand parens not balanced. */ |
5532 | unsigned int paren_not_balanced; | |
5533 | ||
5534 | while (*l != END_OF_INSN) | |
5535 | { | |
5536 | /* Skip optional white space before operand. */ | |
5537 | if (is_space_char (*l)) | |
5538 | ++l; | |
d02603dc | 5539 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
5540 | { |
5541 | as_bad (_("invalid character %s before operand %d"), | |
5542 | output_invalid (*l), | |
5543 | i.operands + 1); | |
5544 | return NULL; | |
5545 | } | |
d02603dc | 5546 | token_start = l; /* After white space. */ |
29b0f896 AM |
5547 | paren_not_balanced = 0; |
5548 | while (paren_not_balanced || *l != ',') | |
5549 | { | |
5550 | if (*l == END_OF_INSN) | |
5551 | { | |
5552 | if (paren_not_balanced) | |
5553 | { | |
5554 | if (!intel_syntax) | |
5555 | as_bad (_("unbalanced parenthesis in operand %d."), | |
5556 | i.operands + 1); | |
5557 | else | |
5558 | as_bad (_("unbalanced brackets in operand %d."), | |
5559 | i.operands + 1); | |
5560 | return NULL; | |
5561 | } | |
5562 | else | |
5563 | break; /* we are done */ | |
5564 | } | |
d02603dc | 5565 | else if (!is_operand_char (*l) && !is_space_char (*l) && *l != '"') |
29b0f896 AM |
5566 | { |
5567 | as_bad (_("invalid character %s in operand %d"), | |
5568 | output_invalid (*l), | |
5569 | i.operands + 1); | |
5570 | return NULL; | |
5571 | } | |
5572 | if (!intel_syntax) | |
5573 | { | |
5574 | if (*l == '(') | |
5575 | ++paren_not_balanced; | |
5576 | if (*l == ')') | |
5577 | --paren_not_balanced; | |
5578 | } | |
5579 | else | |
5580 | { | |
5581 | if (*l == '[') | |
5582 | ++paren_not_balanced; | |
5583 | if (*l == ']') | |
5584 | --paren_not_balanced; | |
5585 | } | |
5586 | l++; | |
5587 | } | |
5588 | if (l != token_start) | |
5589 | { /* Yes, we've read in another operand. */ | |
5590 | unsigned int operand_ok; | |
5591 | this_operand = i.operands++; | |
5592 | if (i.operands > MAX_OPERANDS) | |
5593 | { | |
5594 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
5595 | MAX_OPERANDS); | |
5596 | return NULL; | |
5597 | } | |
9d46ce34 | 5598 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
5599 | /* Now parse operand adding info to 'i' as we go along. */ |
5600 | END_STRING_AND_SAVE (l); | |
5601 | ||
1286ab78 L |
5602 | if (i.mem_operands > 1) |
5603 | { | |
5604 | as_bad (_("too many memory references for `%s'"), | |
5605 | mnemonic); | |
5606 | return 0; | |
5607 | } | |
5608 | ||
29b0f896 AM |
5609 | if (intel_syntax) |
5610 | operand_ok = | |
5611 | i386_intel_operand (token_start, | |
5612 | intel_float_operand (mnemonic)); | |
5613 | else | |
a7619375 | 5614 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
5615 | |
5616 | RESTORE_END_STRING (l); | |
5617 | if (!operand_ok) | |
5618 | return NULL; | |
5619 | } | |
5620 | else | |
5621 | { | |
5622 | if (expecting_operand) | |
5623 | { | |
5624 | expecting_operand_after_comma: | |
5625 | as_bad (_("expecting operand after ','; got nothing")); | |
5626 | return NULL; | |
5627 | } | |
5628 | if (*l == ',') | |
5629 | { | |
5630 | as_bad (_("expecting operand before ','; got nothing")); | |
5631 | return NULL; | |
5632 | } | |
5633 | } | |
7f3f1ea2 | 5634 | |
29b0f896 AM |
5635 | /* Now *l must be either ',' or END_OF_INSN. */ |
5636 | if (*l == ',') | |
5637 | { | |
5638 | if (*++l == END_OF_INSN) | |
5639 | { | |
5640 | /* Just skip it, if it's \n complain. */ | |
5641 | goto expecting_operand_after_comma; | |
5642 | } | |
5643 | expecting_operand = 1; | |
5644 | } | |
5645 | } | |
5646 | return l; | |
5647 | } | |
7f3f1ea2 | 5648 | |
050dfa73 | 5649 | static void |
783c187b | 5650 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
5651 | { |
5652 | union i386_op temp_op; | |
40fb9820 | 5653 | i386_operand_type temp_type; |
c48dadc9 | 5654 | unsigned int temp_flags; |
050dfa73 | 5655 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 5656 | |
050dfa73 MM |
5657 | temp_type = i.types[xchg2]; |
5658 | i.types[xchg2] = i.types[xchg1]; | |
5659 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
5660 | |
5661 | temp_flags = i.flags[xchg2]; | |
5662 | i.flags[xchg2] = i.flags[xchg1]; | |
5663 | i.flags[xchg1] = temp_flags; | |
5664 | ||
050dfa73 MM |
5665 | temp_op = i.op[xchg2]; |
5666 | i.op[xchg2] = i.op[xchg1]; | |
5667 | i.op[xchg1] = temp_op; | |
c48dadc9 | 5668 | |
050dfa73 MM |
5669 | temp_reloc = i.reloc[xchg2]; |
5670 | i.reloc[xchg2] = i.reloc[xchg1]; | |
5671 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 5672 | |
6225c532 | 5673 | if (i.mask.reg) |
43234a1e | 5674 | { |
6225c532 JB |
5675 | if (i.mask.operand == xchg1) |
5676 | i.mask.operand = xchg2; | |
5677 | else if (i.mask.operand == xchg2) | |
5678 | i.mask.operand = xchg1; | |
43234a1e | 5679 | } |
5273a3cd | 5680 | if (i.broadcast.type) |
43234a1e | 5681 | { |
5273a3cd JB |
5682 | if (i.broadcast.operand == xchg1) |
5683 | i.broadcast.operand = xchg2; | |
5684 | else if (i.broadcast.operand == xchg2) | |
5685 | i.broadcast.operand = xchg1; | |
43234a1e | 5686 | } |
ca5312a2 | 5687 | if (i.rounding.type != rc_none) |
43234a1e | 5688 | { |
ca5312a2 JB |
5689 | if (i.rounding.operand == xchg1) |
5690 | i.rounding.operand = xchg2; | |
5691 | else if (i.rounding.operand == xchg2) | |
5692 | i.rounding.operand = xchg1; | |
43234a1e | 5693 | } |
050dfa73 MM |
5694 | } |
5695 | ||
29b0f896 | 5696 | static void |
e3bb37b5 | 5697 | swap_operands (void) |
29b0f896 | 5698 | { |
b7c61d9a | 5699 | switch (i.operands) |
050dfa73 | 5700 | { |
c0f3af97 | 5701 | case 5: |
b7c61d9a | 5702 | case 4: |
4d456e3d | 5703 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 5704 | /* Fall through. */ |
b7c61d9a L |
5705 | case 3: |
5706 | case 2: | |
4d456e3d | 5707 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
5708 | break; |
5709 | default: | |
5710 | abort (); | |
29b0f896 | 5711 | } |
29b0f896 AM |
5712 | |
5713 | if (i.mem_operands == 2) | |
5714 | { | |
5e042380 | 5715 | const reg_entry *temp_seg; |
29b0f896 AM |
5716 | temp_seg = i.seg[0]; |
5717 | i.seg[0] = i.seg[1]; | |
5718 | i.seg[1] = temp_seg; | |
5719 | } | |
5720 | } | |
252b5132 | 5721 | |
29b0f896 AM |
5722 | /* Try to ensure constant immediates are represented in the smallest |
5723 | opcode possible. */ | |
5724 | static void | |
e3bb37b5 | 5725 | optimize_imm (void) |
29b0f896 AM |
5726 | { |
5727 | char guess_suffix = 0; | |
5728 | int op; | |
252b5132 | 5729 | |
29b0f896 AM |
5730 | if (i.suffix) |
5731 | guess_suffix = i.suffix; | |
5732 | else if (i.reg_operands) | |
5733 | { | |
5734 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
5735 | We can't do this properly yet, i.e. excluding special register |
5736 | instances, but the following works for instructions with | |
5737 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 5738 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
5739 | if (i.types[op].bitfield.class != Reg) |
5740 | continue; | |
5741 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 5742 | { |
40fb9820 L |
5743 | guess_suffix = BYTE_MNEM_SUFFIX; |
5744 | break; | |
5745 | } | |
bab6aec1 | 5746 | else if (i.types[op].bitfield.word) |
252b5132 | 5747 | { |
40fb9820 L |
5748 | guess_suffix = WORD_MNEM_SUFFIX; |
5749 | break; | |
5750 | } | |
bab6aec1 | 5751 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
5752 | { |
5753 | guess_suffix = LONG_MNEM_SUFFIX; | |
5754 | break; | |
5755 | } | |
bab6aec1 | 5756 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
5757 | { |
5758 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 5759 | break; |
252b5132 | 5760 | } |
29b0f896 AM |
5761 | } |
5762 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
5763 | guess_suffix = WORD_MNEM_SUFFIX; | |
5764 | ||
5765 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 5766 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
5767 | { |
5768 | switch (i.op[op].imms->X_op) | |
252b5132 | 5769 | { |
29b0f896 AM |
5770 | case O_constant: |
5771 | /* If a suffix is given, this operand may be shortened. */ | |
5772 | switch (guess_suffix) | |
252b5132 | 5773 | { |
29b0f896 | 5774 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
5775 | i.types[op].bitfield.imm32 = 1; |
5776 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5777 | break; |
5778 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
5779 | i.types[op].bitfield.imm16 = 1; |
5780 | i.types[op].bitfield.imm32 = 1; | |
5781 | i.types[op].bitfield.imm32s = 1; | |
5782 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
5783 | break; |
5784 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
5785 | i.types[op].bitfield.imm8 = 1; |
5786 | i.types[op].bitfield.imm8s = 1; | |
5787 | i.types[op].bitfield.imm16 = 1; | |
5788 | i.types[op].bitfield.imm32 = 1; | |
5789 | i.types[op].bitfield.imm32s = 1; | |
5790 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 5791 | break; |
252b5132 | 5792 | } |
252b5132 | 5793 | |
29b0f896 AM |
5794 | /* If this operand is at most 16 bits, convert it |
5795 | to a signed 16 bit number before trying to see | |
5796 | whether it will fit in an even smaller size. | |
5797 | This allows a 16-bit operand such as $0xffe0 to | |
5798 | be recognised as within Imm8S range. */ | |
40fb9820 | 5799 | if ((i.types[op].bitfield.imm16) |
29b0f896 | 5800 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
252b5132 | 5801 | { |
87ed972d JB |
5802 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
5803 | ^ 0x8000) - 0x8000); | |
29b0f896 | 5804 | } |
a28def75 L |
5805 | #ifdef BFD64 |
5806 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 5807 | if ((i.types[op].bitfield.imm32) |
29b0f896 AM |
5808 | && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) |
5809 | == 0)) | |
5810 | { | |
5811 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
5812 | ^ ((offsetT) 1 << 31)) | |
5813 | - ((offsetT) 1 << 31)); | |
5814 | } | |
a28def75 | 5815 | #endif |
40fb9820 | 5816 | i.types[op] |
c6fb90c8 L |
5817 | = operand_type_or (i.types[op], |
5818 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 5819 | |
29b0f896 AM |
5820 | /* We must avoid matching of Imm32 templates when 64bit |
5821 | only immediate is available. */ | |
5822 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 5823 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 5824 | break; |
252b5132 | 5825 | |
29b0f896 AM |
5826 | case O_absent: |
5827 | case O_register: | |
5828 | abort (); | |
5829 | ||
5830 | /* Symbols and expressions. */ | |
5831 | default: | |
9cd96992 JB |
5832 | /* Convert symbolic operand to proper sizes for matching, but don't |
5833 | prevent matching a set of insns that only supports sizes other | |
5834 | than those matching the insn suffix. */ | |
5835 | { | |
40fb9820 | 5836 | i386_operand_type mask, allowed; |
87ed972d | 5837 | const insn_template *t = current_templates->start; |
9cd96992 | 5838 | |
0dfbf9d7 | 5839 | operand_type_set (&mask, 0); |
87ed972d | 5840 | allowed = t->operand_types[op]; |
40fb9820 | 5841 | |
87ed972d | 5842 | while (++t < current_templates->end) |
bab6aec1 | 5843 | { |
bab6aec1 | 5844 | allowed = operand_type_and (allowed, anyimm); |
87ed972d | 5845 | allowed = operand_type_or (allowed, t->operand_types[op]); |
bab6aec1 | 5846 | } |
9cd96992 JB |
5847 | switch (guess_suffix) |
5848 | { | |
5849 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
5850 | mask.bitfield.imm64 = 1; |
5851 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
5852 | break; |
5853 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 5854 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
5855 | break; |
5856 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 5857 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
5858 | break; |
5859 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 5860 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
5861 | break; |
5862 | default: | |
9cd96992 JB |
5863 | break; |
5864 | } | |
c6fb90c8 | 5865 | allowed = operand_type_and (mask, allowed); |
0dfbf9d7 | 5866 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 5867 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 5868 | } |
29b0f896 | 5869 | break; |
252b5132 | 5870 | } |
29b0f896 AM |
5871 | } |
5872 | } | |
47926f60 | 5873 | |
29b0f896 AM |
5874 | /* Try to use the smallest displacement type too. */ |
5875 | static void | |
e3bb37b5 | 5876 | optimize_disp (void) |
29b0f896 AM |
5877 | { |
5878 | int op; | |
3e73aa7c | 5879 | |
29b0f896 | 5880 | for (op = i.operands; --op >= 0;) |
40fb9820 | 5881 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 5882 | { |
b300c311 | 5883 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 5884 | { |
91d6fa6a | 5885 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 5886 | |
40fb9820 | 5887 | if (i.types[op].bitfield.disp16 |
91d6fa6a | 5888 | && (op_disp & ~(offsetT) 0xffff) == 0) |
b300c311 L |
5889 | { |
5890 | /* If this operand is at most 16 bits, convert | |
5891 | to a signed 16 bit number and don't use 64bit | |
5892 | displacement. */ | |
91d6fa6a | 5893 | op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000); |
40fb9820 | 5894 | i.types[op].bitfield.disp64 = 0; |
b300c311 | 5895 | } |
91d6fa6a | 5896 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 5897 | { |
40fb9820 L |
5898 | i.types[op].bitfield.disp8 = 0; |
5899 | i.types[op].bitfield.disp16 = 0; | |
5900 | i.types[op].bitfield.disp32 = 0; | |
5901 | i.types[op].bitfield.disp32s = 0; | |
5902 | i.types[op].bitfield.disp64 = 0; | |
b300c311 L |
5903 | i.op[op].disps = 0; |
5904 | i.disp_operands--; | |
5905 | } | |
28a167a4 | 5906 | #ifdef BFD64 |
b300c311 L |
5907 | else if (flag_code == CODE_64BIT) |
5908 | { | |
a9aabc23 | 5909 | if (want_disp32 (current_templates->start) |
28a167a4 JB |
5910 | && fits_in_unsigned_long (op_disp)) |
5911 | i.types[op].bitfield.disp32 = 1; | |
5912 | ||
5913 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ | |
5914 | if (i.types[op].bitfield.disp32 | |
5915 | && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0) | |
5916 | { | |
5917 | /* If this operand is at most 32 bits, convert | |
5918 | to a signed 32 bit number and don't use 64bit | |
5919 | displacement. */ | |
5920 | op_disp &= (((offsetT) 2 << 31) - 1); | |
5921 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
5922 | i.types[op].bitfield.disp64 = 0; | |
5923 | } | |
5924 | ||
91d6fa6a | 5925 | if (fits_in_signed_long (op_disp)) |
28a9d8f5 | 5926 | { |
40fb9820 L |
5927 | i.types[op].bitfield.disp64 = 0; |
5928 | i.types[op].bitfield.disp32s = 1; | |
28a9d8f5 | 5929 | } |
b300c311 | 5930 | } |
28a167a4 | 5931 | #endif |
40fb9820 L |
5932 | if ((i.types[op].bitfield.disp32 |
5933 | || i.types[op].bitfield.disp32s | |
5934 | || i.types[op].bitfield.disp16) | |
b5014f7a | 5935 | && fits_in_disp8 (op_disp)) |
40fb9820 | 5936 | i.types[op].bitfield.disp8 = 1; |
252b5132 | 5937 | } |
67a4f2b7 AO |
5938 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
5939 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
5940 | { | |
5941 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
5942 | i.op[op].disps, 0, i.reloc[op]); | |
40fb9820 L |
5943 | i.types[op].bitfield.disp8 = 0; |
5944 | i.types[op].bitfield.disp16 = 0; | |
5945 | i.types[op].bitfield.disp32 = 0; | |
5946 | i.types[op].bitfield.disp32s = 0; | |
5947 | i.types[op].bitfield.disp64 = 0; | |
67a4f2b7 AO |
5948 | } |
5949 | else | |
b300c311 | 5950 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 5951 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 5952 | } |
29b0f896 AM |
5953 | } |
5954 | ||
4a1b91ea L |
5955 | /* Return 1 if there is a match in broadcast bytes between operand |
5956 | GIVEN and instruction template T. */ | |
5957 | ||
5958 | static INLINE int | |
5959 | match_broadcast_size (const insn_template *t, unsigned int given) | |
5960 | { | |
5961 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
5962 | && i.types[given].bitfield.byte) | |
5963 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
5964 | && i.types[given].bitfield.word) | |
5965 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
5966 | && i.types[given].bitfield.dword) | |
5967 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
5968 | && i.types[given].bitfield.qword)); | |
5969 | } | |
5970 | ||
6c30d220 L |
5971 | /* Check if operands are valid for the instruction. */ |
5972 | ||
5973 | static int | |
5974 | check_VecOperands (const insn_template *t) | |
5975 | { | |
43234a1e | 5976 | unsigned int op; |
e2195274 | 5977 | i386_cpu_flags cpu; |
e2195274 JB |
5978 | |
5979 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
5980 | any one operand are implicity requiring AVX512VL support if the actual | |
5981 | operand size is YMMword or XMMword. Since this function runs after | |
5982 | template matching, there's no need to check for YMMword/XMMword in | |
5983 | the template. */ | |
5984 | cpu = cpu_flags_and (t->cpu_flags, avx512); | |
5985 | if (!cpu_flags_all_zero (&cpu) | |
5986 | && !t->cpu_flags.bitfield.cpuavx512vl | |
5987 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
5988 | { | |
5989 | for (op = 0; op < t->operands; ++op) | |
5990 | { | |
5991 | if (t->operand_types[op].bitfield.zmmword | |
5992 | && (i.types[op].bitfield.ymmword | |
5993 | || i.types[op].bitfield.xmmword)) | |
5994 | { | |
5995 | i.error = unsupported; | |
5996 | return 1; | |
5997 | } | |
5998 | } | |
5999 | } | |
43234a1e | 6000 | |
6c30d220 | 6001 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 6002 | if (!t->opcode_modifier.sib |
6c30d220 | 6003 | && i.index_reg |
1b54b8d7 JB |
6004 | && (i.index_reg->reg_type.bitfield.xmmword |
6005 | || i.index_reg->reg_type.bitfield.ymmword | |
6006 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
6007 | { |
6008 | i.error = unsupported_vector_index_register; | |
6009 | return 1; | |
6010 | } | |
6011 | ||
ad8ecc81 MZ |
6012 | /* Check if default mask is allowed. */ |
6013 | if (t->opcode_modifier.nodefmask | |
6225c532 | 6014 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
6015 | { |
6016 | i.error = no_default_mask; | |
6017 | return 1; | |
6018 | } | |
6019 | ||
7bab8ab5 JB |
6020 | /* For VSIB byte, we need a vector register for index, and all vector |
6021 | registers must be distinct. */ | |
260cd341 | 6022 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
6023 | { |
6024 | if (!i.index_reg | |
63112cd6 | 6025 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 6026 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 6027 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 6028 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 6029 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 6030 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
6031 | { |
6032 | i.error = invalid_vsib_address; | |
6033 | return 1; | |
6034 | } | |
6035 | ||
6225c532 JB |
6036 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
6037 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 6038 | { |
3528c362 | 6039 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6040 | gas_assert (i.types[0].bitfield.xmmword |
6041 | || i.types[0].bitfield.ymmword); | |
3528c362 | 6042 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6043 | gas_assert (i.types[2].bitfield.xmmword |
6044 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
6045 | if (operand_check == check_none) |
6046 | return 0; | |
6047 | if (register_number (i.op[0].regs) | |
6048 | != register_number (i.index_reg) | |
6049 | && register_number (i.op[2].regs) | |
6050 | != register_number (i.index_reg) | |
6051 | && register_number (i.op[0].regs) | |
6052 | != register_number (i.op[2].regs)) | |
6053 | return 0; | |
6054 | if (operand_check == check_error) | |
6055 | { | |
6056 | i.error = invalid_vector_register_set; | |
6057 | return 1; | |
6058 | } | |
6059 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6060 | } | |
6225c532 | 6061 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 6062 | { |
3528c362 | 6063 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
6064 | && (i.types[1].bitfield.xmmword |
6065 | || i.types[1].bitfield.ymmword | |
6066 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
6067 | && (register_number (i.op[1].regs) |
6068 | == register_number (i.index_reg))) | |
6069 | { | |
6070 | if (operand_check == check_error) | |
6071 | { | |
6072 | i.error = invalid_vector_register_set; | |
6073 | return 1; | |
6074 | } | |
6075 | if (operand_check != check_none) | |
6076 | as_warn (_("index and destination registers should be distinct")); | |
6077 | } | |
6078 | } | |
43234a1e | 6079 | } |
7bab8ab5 | 6080 | |
260cd341 LC |
6081 | /* For AMX instructions with three tmmword operands, all tmmword operand must be |
6082 | distinct */ | |
6083 | if (t->operand_types[0].bitfield.tmmword | |
6084 | && i.reg_operands == 3) | |
6085 | { | |
6086 | if (register_number (i.op[0].regs) | |
6087 | == register_number (i.op[1].regs) | |
6088 | || register_number (i.op[0].regs) | |
6089 | == register_number (i.op[2].regs) | |
6090 | || register_number (i.op[1].regs) | |
6091 | == register_number (i.op[2].regs)) | |
6092 | { | |
6093 | i.error = invalid_tmm_register_set; | |
6094 | return 1; | |
6095 | } | |
6096 | } | |
6097 | ||
43234a1e L |
6098 | /* Check if broadcast is supported by the instruction and is applied |
6099 | to the memory operand. */ | |
5273a3cd | 6100 | if (i.broadcast.type) |
43234a1e | 6101 | { |
8e6e0792 | 6102 | i386_operand_type type, overlap; |
43234a1e L |
6103 | |
6104 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 6105 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 6106 | op = i.broadcast.operand; |
8e6e0792 | 6107 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 6108 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 6109 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 6110 | && !match_broadcast_size (t, op))) |
43234a1e L |
6111 | { |
6112 | bad_broadcast: | |
6113 | i.error = unsupported_broadcast; | |
6114 | return 1; | |
6115 | } | |
8e6e0792 | 6116 | |
5273a3cd JB |
6117 | i.broadcast.bytes = ((1 << (t->opcode_modifier.broadcast - 1)) |
6118 | * i.broadcast.type); | |
8e6e0792 | 6119 | operand_type_set (&type, 0); |
5273a3cd | 6120 | switch (i.broadcast.bytes) |
8e6e0792 | 6121 | { |
4a1b91ea L |
6122 | case 2: |
6123 | type.bitfield.word = 1; | |
6124 | break; | |
6125 | case 4: | |
6126 | type.bitfield.dword = 1; | |
6127 | break; | |
8e6e0792 JB |
6128 | case 8: |
6129 | type.bitfield.qword = 1; | |
6130 | break; | |
6131 | case 16: | |
6132 | type.bitfield.xmmword = 1; | |
6133 | break; | |
6134 | case 32: | |
6135 | type.bitfield.ymmword = 1; | |
6136 | break; | |
6137 | case 64: | |
6138 | type.bitfield.zmmword = 1; | |
6139 | break; | |
6140 | default: | |
6141 | goto bad_broadcast; | |
6142 | } | |
6143 | ||
6144 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
6145 | if (t->operand_types[op].bitfield.class == RegSIMD |
6146 | && t->operand_types[op].bitfield.byte | |
6147 | + t->operand_types[op].bitfield.word | |
6148 | + t->operand_types[op].bitfield.dword | |
6149 | + t->operand_types[op].bitfield.qword > 1) | |
6150 | { | |
6151 | overlap.bitfield.xmmword = 0; | |
6152 | overlap.bitfield.ymmword = 0; | |
6153 | overlap.bitfield.zmmword = 0; | |
6154 | } | |
8e6e0792 JB |
6155 | if (operand_type_all_zero (&overlap)) |
6156 | goto bad_broadcast; | |
6157 | ||
6158 | if (t->opcode_modifier.checkregsize) | |
6159 | { | |
6160 | unsigned int j; | |
6161 | ||
e2195274 | 6162 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
6163 | for (j = 0; j < i.operands; ++j) |
6164 | { | |
6165 | if (j != op | |
6166 | && !operand_type_register_match(i.types[j], | |
6167 | t->operand_types[j], | |
6168 | type, | |
6169 | t->operand_types[op])) | |
6170 | goto bad_broadcast; | |
6171 | } | |
6172 | } | |
43234a1e L |
6173 | } |
6174 | /* If broadcast is supported in this instruction, we need to check if | |
6175 | operand of one-element size isn't specified without broadcast. */ | |
6176 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
6177 | { | |
6178 | /* Find memory operand. */ | |
6179 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6180 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
6181 | break; |
6182 | gas_assert (op < i.operands); | |
6183 | /* Check size of the memory operand. */ | |
4a1b91ea | 6184 | if (match_broadcast_size (t, op)) |
43234a1e L |
6185 | { |
6186 | i.error = broadcast_needed; | |
6187 | return 1; | |
6188 | } | |
6189 | } | |
c39e5b26 JB |
6190 | else |
6191 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
6192 | |
6193 | /* Check if requested masking is supported. */ | |
6225c532 | 6194 | if (i.mask.reg) |
43234a1e | 6195 | { |
ae2387fe JB |
6196 | switch (t->opcode_modifier.masking) |
6197 | { | |
6198 | case BOTH_MASKING: | |
6199 | break; | |
6200 | case MERGING_MASKING: | |
6225c532 | 6201 | if (i.mask.zeroing) |
ae2387fe JB |
6202 | { |
6203 | case 0: | |
6204 | i.error = unsupported_masking; | |
6205 | return 1; | |
6206 | } | |
6207 | break; | |
6208 | case DYNAMIC_MASKING: | |
6209 | /* Memory destinations allow only merging masking. */ | |
6225c532 | 6210 | if (i.mask.zeroing && i.mem_operands) |
ae2387fe JB |
6211 | { |
6212 | /* Find memory operand. */ | |
6213 | for (op = 0; op < i.operands; op++) | |
c48dadc9 | 6214 | if (i.flags[op] & Operand_Mem) |
ae2387fe JB |
6215 | break; |
6216 | gas_assert (op < i.operands); | |
6217 | if (op == i.operands - 1) | |
6218 | { | |
6219 | i.error = unsupported_masking; | |
6220 | return 1; | |
6221 | } | |
6222 | } | |
6223 | break; | |
6224 | default: | |
6225 | abort (); | |
6226 | } | |
43234a1e L |
6227 | } |
6228 | ||
6229 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 6230 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
6231 | { |
6232 | i.error = mask_not_on_destination; | |
6233 | return 1; | |
6234 | } | |
6235 | ||
43234a1e | 6236 | /* Check RC/SAE. */ |
ca5312a2 | 6237 | if (i.rounding.type != rc_none) |
43234a1e | 6238 | { |
a80195f1 | 6239 | if (!t->opcode_modifier.sae |
ca5312a2 | 6240 | || (i.rounding.type != saeonly && !t->opcode_modifier.staticrounding)) |
43234a1e L |
6241 | { |
6242 | i.error = unsupported_rc_sae; | |
6243 | return 1; | |
6244 | } | |
6245 | /* If the instruction has several immediate operands and one of | |
6246 | them is rounding, the rounding operand should be the last | |
6247 | immediate operand. */ | |
6248 | if (i.imm_operands > 1 | |
ca5312a2 | 6249 | && i.rounding.operand != i.imm_operands - 1) |
7bab8ab5 | 6250 | { |
43234a1e | 6251 | i.error = rc_sae_operand_not_last_imm; |
7bab8ab5 JB |
6252 | return 1; |
6253 | } | |
6c30d220 L |
6254 | } |
6255 | ||
da4977e0 JB |
6256 | /* Check the special Imm4 cases; must be the first operand. */ |
6257 | if (t->cpu_flags.bitfield.cpuxop && t->operands == 5) | |
6258 | { | |
6259 | if (i.op[0].imms->X_op != O_constant | |
6260 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
6261 | { | |
6262 | i.error = bad_imm4; | |
6263 | return 1; | |
6264 | } | |
6265 | ||
6266 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
6267 | operand_type_set (&i.types[0], 0); | |
6268 | } | |
6269 | ||
43234a1e | 6270 | /* Check vector Disp8 operand. */ |
b5014f7a JB |
6271 | if (t->opcode_modifier.disp8memshift |
6272 | && i.disp_encoding != disp_encoding_32bit) | |
43234a1e | 6273 | { |
5273a3cd | 6274 | if (i.broadcast.type) |
4a1b91ea | 6275 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 6276 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 6277 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
6278 | else |
6279 | { | |
6280 | const i386_operand_type *type = NULL; | |
6281 | ||
6282 | i.memshift = 0; | |
6283 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6284 | if (i.flags[op] & Operand_Mem) |
7091c612 | 6285 | { |
4174bfff JB |
6286 | if (t->opcode_modifier.evex == EVEXLIG) |
6287 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
6288 | else if (t->operand_types[op].bitfield.xmmword | |
6289 | + t->operand_types[op].bitfield.ymmword | |
6290 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
6291 | type = &t->operand_types[op]; |
6292 | else if (!i.types[op].bitfield.unspecified) | |
6293 | type = &i.types[op]; | |
6294 | } | |
3528c362 | 6295 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 6296 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
6297 | { |
6298 | if (i.types[op].bitfield.zmmword) | |
6299 | i.memshift = 6; | |
6300 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
6301 | i.memshift = 5; | |
6302 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
6303 | i.memshift = 4; | |
6304 | } | |
6305 | ||
6306 | if (type) | |
6307 | { | |
6308 | if (type->bitfield.zmmword) | |
6309 | i.memshift = 6; | |
6310 | else if (type->bitfield.ymmword) | |
6311 | i.memshift = 5; | |
6312 | else if (type->bitfield.xmmword) | |
6313 | i.memshift = 4; | |
6314 | } | |
6315 | ||
6316 | /* For the check in fits_in_disp8(). */ | |
6317 | if (i.memshift == 0) | |
6318 | i.memshift = -1; | |
6319 | } | |
43234a1e L |
6320 | |
6321 | for (op = 0; op < i.operands; op++) | |
6322 | if (operand_type_check (i.types[op], disp) | |
6323 | && i.op[op].disps->X_op == O_constant) | |
6324 | { | |
b5014f7a | 6325 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 6326 | { |
b5014f7a JB |
6327 | i.types[op].bitfield.disp8 = 1; |
6328 | return 0; | |
43234a1e | 6329 | } |
b5014f7a | 6330 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
6331 | } |
6332 | } | |
b5014f7a JB |
6333 | |
6334 | i.memshift = 0; | |
43234a1e | 6335 | |
6c30d220 L |
6336 | return 0; |
6337 | } | |
6338 | ||
da4977e0 | 6339 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
6340 | |
6341 | static int | |
da4977e0 | 6342 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 6343 | { |
da4977e0 JB |
6344 | if (i.vec_encoding == vex_encoding_error) |
6345 | { | |
6346 | i.error = unsupported; | |
6347 | return 1; | |
6348 | } | |
6349 | ||
86fa6981 | 6350 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 6351 | { |
86fa6981 | 6352 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 6353 | if (!is_evex_encoding (t)) |
86fa6981 L |
6354 | { |
6355 | i.error = unsupported; | |
6356 | return 1; | |
6357 | } | |
6358 | return 0; | |
43234a1e L |
6359 | } |
6360 | ||
a683cc34 | 6361 | if (!t->opcode_modifier.vex) |
86fa6981 L |
6362 | { |
6363 | /* This instruction template doesn't have VEX prefix. */ | |
6364 | if (i.vec_encoding != vex_encoding_default) | |
6365 | { | |
6366 | i.error = unsupported; | |
6367 | return 1; | |
6368 | } | |
6369 | return 0; | |
6370 | } | |
a683cc34 | 6371 | |
a683cc34 SP |
6372 | return 0; |
6373 | } | |
6374 | ||
d3ce72d0 | 6375 | static const insn_template * |
83b16ac6 | 6376 | match_template (char mnem_suffix) |
29b0f896 AM |
6377 | { |
6378 | /* Points to template once we've found it. */ | |
d3ce72d0 | 6379 | const insn_template *t; |
40fb9820 | 6380 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 6381 | i386_operand_type overlap4; |
29b0f896 | 6382 | unsigned int found_reverse_match; |
dc2be329 | 6383 | i386_opcode_modifier suffix_check; |
40fb9820 | 6384 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 6385 | int addr_prefix_disp; |
45a4bb20 | 6386 | unsigned int j, size_match, check_register; |
5614d22c | 6387 | enum i386_error specific_error = 0; |
29b0f896 | 6388 | |
c0f3af97 L |
6389 | #if MAX_OPERANDS != 5 |
6390 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
6391 | #endif |
6392 | ||
29b0f896 | 6393 | found_reverse_match = 0; |
539e75ad | 6394 | addr_prefix_disp = -1; |
40fb9820 | 6395 | |
dc2be329 | 6396 | /* Prepare for mnemonic suffix check. */ |
40fb9820 | 6397 | memset (&suffix_check, 0, sizeof (suffix_check)); |
dc2be329 L |
6398 | switch (mnem_suffix) |
6399 | { | |
6400 | case BYTE_MNEM_SUFFIX: | |
6401 | suffix_check.no_bsuf = 1; | |
6402 | break; | |
6403 | case WORD_MNEM_SUFFIX: | |
6404 | suffix_check.no_wsuf = 1; | |
6405 | break; | |
6406 | case SHORT_MNEM_SUFFIX: | |
6407 | suffix_check.no_ssuf = 1; | |
6408 | break; | |
6409 | case LONG_MNEM_SUFFIX: | |
6410 | suffix_check.no_lsuf = 1; | |
6411 | break; | |
6412 | case QWORD_MNEM_SUFFIX: | |
6413 | suffix_check.no_qsuf = 1; | |
6414 | break; | |
6415 | default: | |
6416 | /* NB: In Intel syntax, normally we can check for memory operand | |
6417 | size when there is no mnemonic suffix. But jmp and call have | |
6418 | 2 different encodings with Dword memory operand size, one with | |
6419 | No_ldSuf and the other without. i.suffix is set to | |
6420 | LONG_DOUBLE_MNEM_SUFFIX to skip the one with No_ldSuf. */ | |
6421 | if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX) | |
6422 | suffix_check.no_ldsuf = 1; | |
83b16ac6 JB |
6423 | } |
6424 | ||
01559ecc L |
6425 | /* Must have right number of operands. */ |
6426 | i.error = number_of_operands_mismatch; | |
6427 | ||
45aa61fe | 6428 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 6429 | { |
539e75ad | 6430 | addr_prefix_disp = -1; |
dbbc8b7e | 6431 | found_reverse_match = 0; |
539e75ad | 6432 | |
29b0f896 AM |
6433 | if (i.operands != t->operands) |
6434 | continue; | |
6435 | ||
50aecf8c | 6436 | /* Check processor support. */ |
a65babc9 | 6437 | i.error = unsupported; |
45a4bb20 | 6438 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
6439 | continue; |
6440 | ||
57392598 CL |
6441 | /* Check Pseudo Prefix. */ |
6442 | i.error = unsupported; | |
6443 | if (t->opcode_modifier.pseudovexprefix | |
6444 | && !(i.vec_encoding == vex_encoding_vex | |
6445 | || i.vec_encoding == vex_encoding_vex3)) | |
6446 | continue; | |
6447 | ||
e1d4d893 | 6448 | /* Check AT&T mnemonic. */ |
a65babc9 | 6449 | i.error = unsupported_with_intel_mnemonic; |
e1d4d893 | 6450 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
6451 | continue; |
6452 | ||
4b5aaf5f | 6453 | /* Check AT&T/Intel syntax. */ |
a65babc9 | 6454 | i.error = unsupported_syntax; |
5c07affc | 6455 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 6456 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
6457 | continue; |
6458 | ||
4b5aaf5f L |
6459 | /* Check Intel64/AMD64 ISA. */ |
6460 | switch (isa64) | |
6461 | { | |
6462 | default: | |
6463 | /* Default: Don't accept Intel64. */ | |
6464 | if (t->opcode_modifier.isa64 == INTEL64) | |
6465 | continue; | |
6466 | break; | |
6467 | case amd64: | |
6468 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
6469 | if (t->opcode_modifier.isa64 >= INTEL64) | |
6470 | continue; | |
6471 | break; | |
6472 | case intel64: | |
6473 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 6474 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
6475 | continue; |
6476 | break; | |
6477 | } | |
6478 | ||
dc2be329 | 6479 | /* Check the suffix. */ |
a65babc9 | 6480 | i.error = invalid_instruction_suffix; |
dc2be329 L |
6481 | if ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf) |
6482 | || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf) | |
6483 | || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf) | |
6484 | || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf) | |
6485 | || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf) | |
6486 | || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)) | |
83b16ac6 | 6487 | continue; |
29b0f896 | 6488 | |
3ac21baa JB |
6489 | size_match = operand_size_match (t); |
6490 | if (!size_match) | |
7d5e4556 | 6491 | continue; |
539e75ad | 6492 | |
6f2f06be JB |
6493 | /* This is intentionally not |
6494 | ||
0cfa3eb3 | 6495 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
6496 | |
6497 | as the case of a missing * on the operand is accepted (perhaps with | |
6498 | a warning, issued further down). */ | |
0cfa3eb3 | 6499 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
6f2f06be JB |
6500 | { |
6501 | i.error = operand_type_mismatch; | |
6502 | continue; | |
6503 | } | |
6504 | ||
5c07affc L |
6505 | for (j = 0; j < MAX_OPERANDS; j++) |
6506 | operand_types[j] = t->operand_types[j]; | |
6507 | ||
e365e234 JB |
6508 | /* In general, don't allow |
6509 | - 64-bit operands outside of 64-bit mode, | |
6510 | - 32-bit operands on pre-386. */ | |
4873e243 | 6511 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
e365e234 JB |
6512 | if (((i.suffix == QWORD_MNEM_SUFFIX |
6513 | && flag_code != CODE_64BIT | |
389d00a5 JB |
6514 | && !(t->opcode_modifier.opcodespace == SPACE_0F |
6515 | && t->base_opcode == 0xc7 | |
5e74b495 | 6516 | && t->opcode_modifier.opcodeprefix == PREFIX_NONE |
8b65b895 | 6517 | && t->extension_opcode == 1) /* cmpxchg8b */) |
e365e234 JB |
6518 | || (i.suffix == LONG_MNEM_SUFFIX |
6519 | && !cpu_arch_flags.bitfield.cpui386)) | |
45aa61fe | 6520 | && (intel_syntax |
3cd7f3e3 | 6521 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
45aa61fe AM |
6522 | && !intel_float_operand (t->name)) |
6523 | : intel_float_operand (t->name) != 2) | |
4873e243 JB |
6524 | && (t->operands == i.imm_operands |
6525 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
6526 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
6527 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
6528 | || (operand_types[j].bitfield.class != RegMMX | |
6529 | && operand_types[j].bitfield.class != RegSIMD | |
6530 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 6531 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
6532 | continue; |
6533 | ||
29b0f896 | 6534 | /* Do not verify operands when there are none. */ |
e365e234 | 6535 | if (!t->operands) |
da4977e0 JB |
6536 | { |
6537 | if (VEX_check_encoding (t)) | |
6538 | { | |
6539 | specific_error = i.error; | |
6540 | continue; | |
6541 | } | |
6542 | ||
6543 | /* We've found a match; break out of loop. */ | |
6544 | break; | |
6545 | } | |
252b5132 | 6546 | |
48bcea9f JB |
6547 | if (!t->opcode_modifier.jump |
6548 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
6549 | { | |
6550 | /* There should be only one Disp operand. */ | |
6551 | for (j = 0; j < MAX_OPERANDS; j++) | |
6552 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 6553 | break; |
48bcea9f JB |
6554 | if (j < MAX_OPERANDS) |
6555 | { | |
5b7c81bd | 6556 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
6557 | |
6558 | addr_prefix_disp = j; | |
6559 | ||
6560 | /* Address size prefix will turn Disp64/Disp32S/Disp32/Disp16 | |
6561 | operand into Disp32/Disp32/Disp16/Disp32 operand. */ | |
6562 | switch (flag_code) | |
40fb9820 | 6563 | { |
48bcea9f JB |
6564 | case CODE_16BIT: |
6565 | override = !override; | |
6566 | /* Fall through. */ | |
6567 | case CODE_32BIT: | |
6568 | if (operand_types[j].bitfield.disp32 | |
6569 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 6570 | { |
48bcea9f JB |
6571 | operand_types[j].bitfield.disp16 = override; |
6572 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 6573 | } |
48bcea9f JB |
6574 | operand_types[j].bitfield.disp32s = 0; |
6575 | operand_types[j].bitfield.disp64 = 0; | |
6576 | break; | |
6577 | ||
6578 | case CODE_64BIT: | |
6579 | if (operand_types[j].bitfield.disp32s | |
6580 | || operand_types[j].bitfield.disp64) | |
40fb9820 | 6581 | { |
48bcea9f JB |
6582 | operand_types[j].bitfield.disp64 &= !override; |
6583 | operand_types[j].bitfield.disp32s &= !override; | |
6584 | operand_types[j].bitfield.disp32 = override; | |
40fb9820 | 6585 | } |
48bcea9f JB |
6586 | operand_types[j].bitfield.disp16 = 0; |
6587 | break; | |
40fb9820 | 6588 | } |
539e75ad | 6589 | } |
48bcea9f | 6590 | } |
539e75ad | 6591 | |
02a86693 | 6592 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ |
35648716 JB |
6593 | if (i.reloc[0] == BFD_RELOC_386_GOT32 |
6594 | && t->base_opcode == 0xa0 | |
6595 | && t->opcode_modifier.opcodespace == SPACE_BASE) | |
02a86693 L |
6596 | continue; |
6597 | ||
56ffb741 | 6598 | /* We check register size if needed. */ |
e2195274 JB |
6599 | if (t->opcode_modifier.checkregsize) |
6600 | { | |
6601 | check_register = (1 << t->operands) - 1; | |
5273a3cd JB |
6602 | if (i.broadcast.type) |
6603 | check_register &= ~(1 << i.broadcast.operand); | |
e2195274 JB |
6604 | } |
6605 | else | |
6606 | check_register = 0; | |
6607 | ||
c6fb90c8 | 6608 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
6609 | switch (t->operands) |
6610 | { | |
6611 | case 1: | |
40fb9820 | 6612 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 AM |
6613 | continue; |
6614 | break; | |
6615 | case 2: | |
33eaf5de | 6616 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
6617 | only in 32bit mode and we can use opcode 0x90. In 64bit |
6618 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
6619 | zero-extend %eax to %rax. */ | |
6620 | if (flag_code == CODE_64BIT | |
6621 | && t->base_opcode == 0x90 | |
35648716 | 6622 | && t->opcode_modifier.opcodespace == SPACE_BASE |
75e5731b JB |
6623 | && i.types[0].bitfield.instance == Accum |
6624 | && i.types[0].bitfield.dword | |
6625 | && i.types[1].bitfield.instance == Accum | |
6626 | && i.types[1].bitfield.dword) | |
8b38ad71 | 6627 | continue; |
1212781b JB |
6628 | /* xrelease mov %eax, <disp> is another special case. It must not |
6629 | match the accumulator-only encoding of mov. */ | |
6630 | if (flag_code != CODE_64BIT | |
6631 | && i.hle_prefix | |
6632 | && t->base_opcode == 0xa0 | |
35648716 | 6633 | && t->opcode_modifier.opcodespace == SPACE_BASE |
75e5731b | 6634 | && i.types[0].bitfield.instance == Accum |
8dc0818e | 6635 | && (i.flags[1] & Operand_Mem)) |
1212781b | 6636 | continue; |
f5eb1d70 JB |
6637 | /* Fall through. */ |
6638 | ||
6639 | case 3: | |
3ac21baa JB |
6640 | if (!(size_match & MATCH_STRAIGHT)) |
6641 | goto check_reverse; | |
64c49ab3 JB |
6642 | /* Reverse direction of operands if swapping is possible in the first |
6643 | place (operands need to be symmetric) and | |
6644 | - the load form is requested, and the template is a store form, | |
6645 | - the store form is requested, and the template is a load form, | |
6646 | - the non-default (swapped) form is requested. */ | |
6647 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 6648 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
6649 | && !operand_type_all_zero (&overlap1)) |
6650 | switch (i.dir_encoding) | |
6651 | { | |
6652 | case dir_encoding_load: | |
6653 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6654 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
6655 | goto check_reverse; |
6656 | break; | |
6657 | ||
6658 | case dir_encoding_store: | |
6659 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 6660 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
6661 | goto check_reverse; |
6662 | break; | |
6663 | ||
6664 | case dir_encoding_swap: | |
6665 | goto check_reverse; | |
6666 | ||
6667 | case dir_encoding_default: | |
6668 | break; | |
6669 | } | |
86fa6981 | 6670 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
6671 | if ((i.dir_encoding == dir_encoding_store |
6672 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
6673 | && i.mem_operands == 0 |
6674 | && t->opcode_modifier.load) | |
fa99fab2 | 6675 | continue; |
1a0670f3 | 6676 | /* Fall through. */ |
f48ff2ae | 6677 | case 4: |
c0f3af97 | 6678 | case 5: |
c6fb90c8 | 6679 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
6680 | if (!operand_type_match (overlap0, i.types[0]) |
6681 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 6682 | || ((check_register & 3) == 3 |
dc821c5f | 6683 | && !operand_type_register_match (i.types[0], |
40fb9820 | 6684 | operand_types[0], |
dc821c5f | 6685 | i.types[1], |
40fb9820 | 6686 | operand_types[1]))) |
29b0f896 AM |
6687 | { |
6688 | /* Check if other direction is valid ... */ | |
38e314eb | 6689 | if (!t->opcode_modifier.d) |
29b0f896 AM |
6690 | continue; |
6691 | ||
dc1e8a47 | 6692 | check_reverse: |
3ac21baa JB |
6693 | if (!(size_match & MATCH_REVERSE)) |
6694 | continue; | |
29b0f896 | 6695 | /* Try reversing direction of operands. */ |
f5eb1d70 JB |
6696 | overlap0 = operand_type_and (i.types[0], operand_types[i.operands - 1]); |
6697 | overlap1 = operand_type_and (i.types[i.operands - 1], operand_types[0]); | |
40fb9820 | 6698 | if (!operand_type_match (overlap0, i.types[0]) |
f5eb1d70 | 6699 | || !operand_type_match (overlap1, i.types[i.operands - 1]) |
45664ddb | 6700 | || (check_register |
dc821c5f | 6701 | && !operand_type_register_match (i.types[0], |
f5eb1d70 JB |
6702 | operand_types[i.operands - 1], |
6703 | i.types[i.operands - 1], | |
45664ddb | 6704 | operand_types[0]))) |
29b0f896 AM |
6705 | { |
6706 | /* Does not match either direction. */ | |
6707 | continue; | |
6708 | } | |
38e314eb | 6709 | /* found_reverse_match holds which of D or FloatR |
29b0f896 | 6710 | we've found. */ |
38e314eb JB |
6711 | if (!t->opcode_modifier.d) |
6712 | found_reverse_match = 0; | |
6713 | else if (operand_types[0].bitfield.tbyte) | |
8a2ed489 | 6714 | found_reverse_match = Opcode_FloatD; |
dbbc8b7e | 6715 | else if (operand_types[0].bitfield.xmmword |
f5eb1d70 | 6716 | || operand_types[i.operands - 1].bitfield.xmmword |
3528c362 JB |
6717 | || operand_types[0].bitfield.class == RegMMX |
6718 | || operand_types[i.operands - 1].bitfield.class == RegMMX | |
dbbc8b7e JB |
6719 | || is_any_vex_encoding(t)) |
6720 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e | |
6721 | ? Opcode_SIMD_FloatD : Opcode_SIMD_IntD; | |
8a2ed489 | 6722 | else |
38e314eb | 6723 | found_reverse_match = Opcode_D; |
40fb9820 | 6724 | if (t->opcode_modifier.floatr) |
8a2ed489 | 6725 | found_reverse_match |= Opcode_FloatR; |
29b0f896 | 6726 | } |
f48ff2ae | 6727 | else |
29b0f896 | 6728 | { |
f48ff2ae | 6729 | /* Found a forward 2 operand match here. */ |
d1cbb4db L |
6730 | switch (t->operands) |
6731 | { | |
c0f3af97 L |
6732 | case 5: |
6733 | overlap4 = operand_type_and (i.types[4], | |
6734 | operand_types[4]); | |
1a0670f3 | 6735 | /* Fall through. */ |
d1cbb4db | 6736 | case 4: |
c6fb90c8 L |
6737 | overlap3 = operand_type_and (i.types[3], |
6738 | operand_types[3]); | |
1a0670f3 | 6739 | /* Fall through. */ |
d1cbb4db | 6740 | case 3: |
c6fb90c8 L |
6741 | overlap2 = operand_type_and (i.types[2], |
6742 | operand_types[2]); | |
d1cbb4db L |
6743 | break; |
6744 | } | |
29b0f896 | 6745 | |
f48ff2ae L |
6746 | switch (t->operands) |
6747 | { | |
c0f3af97 L |
6748 | case 5: |
6749 | if (!operand_type_match (overlap4, i.types[4]) | |
dc821c5f | 6750 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 6751 | operand_types[3], |
c0f3af97 L |
6752 | i.types[4], |
6753 | operand_types[4])) | |
6754 | continue; | |
1a0670f3 | 6755 | /* Fall through. */ |
f48ff2ae | 6756 | case 4: |
40fb9820 | 6757 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
6758 | || ((check_register & 0xa) == 0xa |
6759 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
6760 | operand_types[1], |
6761 | i.types[3], | |
e2195274 JB |
6762 | operand_types[3])) |
6763 | || ((check_register & 0xc) == 0xc | |
6764 | && !operand_type_register_match (i.types[2], | |
6765 | operand_types[2], | |
6766 | i.types[3], | |
6767 | operand_types[3]))) | |
f48ff2ae | 6768 | continue; |
1a0670f3 | 6769 | /* Fall through. */ |
f48ff2ae L |
6770 | case 3: |
6771 | /* Here we make use of the fact that there are no | |
23e42951 | 6772 | reverse match 3 operand instructions. */ |
40fb9820 | 6773 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
6774 | || ((check_register & 5) == 5 |
6775 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
6776 | operand_types[0], |
6777 | i.types[2], | |
e2195274 JB |
6778 | operand_types[2])) |
6779 | || ((check_register & 6) == 6 | |
6780 | && !operand_type_register_match (i.types[1], | |
6781 | operand_types[1], | |
6782 | i.types[2], | |
6783 | operand_types[2]))) | |
f48ff2ae L |
6784 | continue; |
6785 | break; | |
6786 | } | |
29b0f896 | 6787 | } |
f48ff2ae | 6788 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
6789 | slip through to break. */ |
6790 | } | |
c0f3af97 | 6791 | |
da4977e0 JB |
6792 | /* Check if vector operands are valid. */ |
6793 | if (check_VecOperands (t)) | |
6794 | { | |
6795 | specific_error = i.error; | |
6796 | continue; | |
6797 | } | |
6798 | ||
6799 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ | |
6800 | if (VEX_check_encoding (t)) | |
5614d22c JB |
6801 | { |
6802 | specific_error = i.error; | |
6803 | continue; | |
6804 | } | |
a683cc34 | 6805 | |
29b0f896 AM |
6806 | /* We've found a match; break out of loop. */ |
6807 | break; | |
6808 | } | |
6809 | ||
6810 | if (t == current_templates->end) | |
6811 | { | |
6812 | /* We found no match. */ | |
a65babc9 | 6813 | const char *err_msg; |
5614d22c | 6814 | switch (specific_error ? specific_error : i.error) |
a65babc9 L |
6815 | { |
6816 | default: | |
6817 | abort (); | |
86e026a4 | 6818 | case operand_size_mismatch: |
a65babc9 L |
6819 | err_msg = _("operand size mismatch"); |
6820 | break; | |
6821 | case operand_type_mismatch: | |
6822 | err_msg = _("operand type mismatch"); | |
6823 | break; | |
6824 | case register_type_mismatch: | |
6825 | err_msg = _("register type mismatch"); | |
6826 | break; | |
6827 | case number_of_operands_mismatch: | |
6828 | err_msg = _("number of operands mismatch"); | |
6829 | break; | |
6830 | case invalid_instruction_suffix: | |
6831 | err_msg = _("invalid instruction suffix"); | |
6832 | break; | |
6833 | case bad_imm4: | |
4a2608e3 | 6834 | err_msg = _("constant doesn't fit in 4 bits"); |
a65babc9 | 6835 | break; |
a65babc9 L |
6836 | case unsupported_with_intel_mnemonic: |
6837 | err_msg = _("unsupported with Intel mnemonic"); | |
6838 | break; | |
6839 | case unsupported_syntax: | |
6840 | err_msg = _("unsupported syntax"); | |
6841 | break; | |
6842 | case unsupported: | |
35262a23 | 6843 | as_bad (_("unsupported instruction `%s'"), |
10efe3f6 L |
6844 | current_templates->start->name); |
6845 | return NULL; | |
260cd341 LC |
6846 | case invalid_sib_address: |
6847 | err_msg = _("invalid SIB address"); | |
6848 | break; | |
6c30d220 L |
6849 | case invalid_vsib_address: |
6850 | err_msg = _("invalid VSIB address"); | |
6851 | break; | |
7bab8ab5 JB |
6852 | case invalid_vector_register_set: |
6853 | err_msg = _("mask, index, and destination registers must be distinct"); | |
6854 | break; | |
260cd341 LC |
6855 | case invalid_tmm_register_set: |
6856 | err_msg = _("all tmm registers must be distinct"); | |
6857 | break; | |
6c30d220 L |
6858 | case unsupported_vector_index_register: |
6859 | err_msg = _("unsupported vector index register"); | |
6860 | break; | |
43234a1e L |
6861 | case unsupported_broadcast: |
6862 | err_msg = _("unsupported broadcast"); | |
6863 | break; | |
43234a1e L |
6864 | case broadcast_needed: |
6865 | err_msg = _("broadcast is needed for operand of such type"); | |
6866 | break; | |
6867 | case unsupported_masking: | |
6868 | err_msg = _("unsupported masking"); | |
6869 | break; | |
6870 | case mask_not_on_destination: | |
6871 | err_msg = _("mask not on destination operand"); | |
6872 | break; | |
6873 | case no_default_mask: | |
6874 | err_msg = _("default mask isn't allowed"); | |
6875 | break; | |
6876 | case unsupported_rc_sae: | |
6877 | err_msg = _("unsupported static rounding/sae"); | |
6878 | break; | |
6879 | case rc_sae_operand_not_last_imm: | |
6880 | if (intel_syntax) | |
6881 | err_msg = _("RC/SAE operand must precede immediate operands"); | |
6882 | else | |
6883 | err_msg = _("RC/SAE operand must follow immediate operands"); | |
6884 | break; | |
6885 | case invalid_register_operand: | |
6886 | err_msg = _("invalid register operand"); | |
6887 | break; | |
a65babc9 L |
6888 | } |
6889 | as_bad (_("%s for `%s'"), err_msg, | |
891edac4 | 6890 | current_templates->start->name); |
fa99fab2 | 6891 | return NULL; |
29b0f896 | 6892 | } |
252b5132 | 6893 | |
29b0f896 AM |
6894 | if (!quiet_warnings) |
6895 | { | |
6896 | if (!intel_syntax | |
0cfa3eb3 | 6897 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
6f2f06be | 6898 | as_warn (_("indirect %s without `*'"), t->name); |
29b0f896 | 6899 | |
40fb9820 | 6900 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 6901 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
6902 | { |
6903 | /* Warn them that a data or address size prefix doesn't | |
6904 | affect assembly of the next line of code. */ | |
6905 | as_warn (_("stand-alone `%s' prefix"), t->name); | |
6906 | } | |
6907 | } | |
6908 | ||
6909 | /* Copy the template we found. */ | |
9a182d04 | 6910 | install_template (t); |
539e75ad L |
6911 | |
6912 | if (addr_prefix_disp != -1) | |
6913 | i.tm.operand_types[addr_prefix_disp] | |
6914 | = operand_types[addr_prefix_disp]; | |
6915 | ||
29b0f896 AM |
6916 | if (found_reverse_match) |
6917 | { | |
dfd69174 JB |
6918 | /* If we found a reverse match we must alter the opcode direction |
6919 | bit and clear/flip the regmem modifier one. found_reverse_match | |
6920 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
6921 | |
6922 | i.tm.base_opcode ^= found_reverse_match; | |
6923 | ||
f5eb1d70 JB |
6924 | i.tm.operand_types[0] = operand_types[i.operands - 1]; |
6925 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
dfd69174 JB |
6926 | |
6927 | /* Certain SIMD insns have their load forms specified in the opcode | |
6928 | table, and hence we need to _set_ RegMem instead of clearing it. | |
6929 | We need to avoid setting the bit though on insns like KMOVW. */ | |
6930 | i.tm.opcode_modifier.regmem | |
6931 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
6932 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
6933 | && !i.tm.opcode_modifier.regmem; | |
29b0f896 AM |
6934 | } |
6935 | ||
fa99fab2 | 6936 | return t; |
29b0f896 AM |
6937 | } |
6938 | ||
6939 | static int | |
e3bb37b5 | 6940 | check_string (void) |
29b0f896 | 6941 | { |
51c8edf6 JB |
6942 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
6943 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 6944 | |
5e042380 | 6945 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 6946 | { |
51c8edf6 JB |
6947 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
6948 | i.tm.name, | |
6949 | intel_syntax ? i.tm.operands - es_op : es_op + 1, | |
6950 | register_prefix); | |
6951 | return 0; | |
29b0f896 | 6952 | } |
51c8edf6 JB |
6953 | |
6954 | /* There's only ever one segment override allowed per instruction. | |
6955 | This instruction possibly has a legal segment override on the | |
6956 | second operand, so copy the segment to where non-string | |
6957 | instructions store it, allowing common code. */ | |
6958 | i.seg[op] = i.seg[1]; | |
6959 | ||
29b0f896 AM |
6960 | return 1; |
6961 | } | |
6962 | ||
6963 | static int | |
543613e9 | 6964 | process_suffix (void) |
29b0f896 | 6965 | { |
5b7c81bd | 6966 | bool is_crc32 = false, is_movx = false; |
8b65b895 | 6967 | |
29b0f896 AM |
6968 | /* If matched instruction specifies an explicit instruction mnemonic |
6969 | suffix, use it. */ | |
673fe0f0 | 6970 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 6971 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 6972 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 6973 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 6974 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 6975 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 6976 | else if (i.reg_operands |
c8f8eebc JB |
6977 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
6978 | && !i.tm.opcode_modifier.addrprefixopreg) | |
29b0f896 | 6979 | { |
65fca059 | 6980 | unsigned int numop = i.operands; |
389d00a5 JB |
6981 | |
6982 | /* MOVSX/MOVZX */ | |
6983 | is_movx = (i.tm.opcode_modifier.opcodespace == SPACE_0F | |
6984 | && (i.tm.base_opcode | 8) == 0xbe) | |
6985 | || (i.tm.opcode_modifier.opcodespace == SPACE_BASE | |
6986 | && i.tm.base_opcode == 0x63 | |
6987 | && i.tm.cpu_flags.bitfield.cpu64); | |
6988 | ||
8b65b895 | 6989 | /* CRC32 */ |
389d00a5 JB |
6990 | is_crc32 = (i.tm.base_opcode == 0xf0 |
6991 | && i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
8b65b895 | 6992 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2); |
65fca059 JB |
6993 | |
6994 | /* movsx/movzx want only their source operand considered here, for the | |
6995 | ambiguity checking below. The suffix will be replaced afterwards | |
6996 | to represent the destination (register). */ | |
389d00a5 | 6997 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
6998 | --i.operands; |
6999 | ||
643bb870 | 7000 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
8b65b895 | 7001 | if (is_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
7002 | i.rex |= REX_W; |
7003 | ||
29b0f896 | 7004 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 7005 | based on GPR operands. */ |
29b0f896 AM |
7006 | if (!i.suffix) |
7007 | { | |
7008 | /* We take i.suffix from the last register operand specified, | |
7009 | Destination register type is more significant than source | |
381d071f L |
7010 | register type. crc32 in SSE4.2 prefers source register |
7011 | type. */ | |
8b65b895 | 7012 | unsigned int op = is_crc32 ? 1 : i.operands; |
20592a94 | 7013 | |
1a035124 JB |
7014 | while (op--) |
7015 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
7016 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
7017 | { | |
7018 | if (i.types[op].bitfield.class != Reg) | |
7019 | continue; | |
7020 | if (i.types[op].bitfield.byte) | |
7021 | i.suffix = BYTE_MNEM_SUFFIX; | |
7022 | else if (i.types[op].bitfield.word) | |
7023 | i.suffix = WORD_MNEM_SUFFIX; | |
7024 | else if (i.types[op].bitfield.dword) | |
7025 | i.suffix = LONG_MNEM_SUFFIX; | |
7026 | else if (i.types[op].bitfield.qword) | |
7027 | i.suffix = QWORD_MNEM_SUFFIX; | |
7028 | else | |
7029 | continue; | |
7030 | break; | |
7031 | } | |
65fca059 JB |
7032 | |
7033 | /* As an exception, movsx/movzx silently default to a byte source | |
7034 | in AT&T mode. */ | |
389d00a5 | 7035 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 7036 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
7037 | } |
7038 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
7039 | { | |
2eb952a4 | 7040 | if (intel_syntax |
3cd7f3e3 | 7041 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
7042 | && i.tm.opcode_modifier.no_bsuf) |
7043 | i.suffix = 0; | |
7044 | else if (!check_byte_reg ()) | |
29b0f896 AM |
7045 | return 0; |
7046 | } | |
7047 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
7048 | { | |
2eb952a4 | 7049 | if (intel_syntax |
3cd7f3e3 | 7050 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
7051 | && i.tm.opcode_modifier.no_lsuf |
7052 | && !i.tm.opcode_modifier.todword | |
7053 | && !i.tm.opcode_modifier.toqword) | |
2eb952a4 L |
7054 | i.suffix = 0; |
7055 | else if (!check_long_reg ()) | |
29b0f896 AM |
7056 | return 0; |
7057 | } | |
7058 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7059 | { | |
955e1e6a | 7060 | if (intel_syntax |
3cd7f3e3 | 7061 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
9f123b91 JB |
7062 | && i.tm.opcode_modifier.no_qsuf |
7063 | && !i.tm.opcode_modifier.todword | |
7064 | && !i.tm.opcode_modifier.toqword) | |
955e1e6a L |
7065 | i.suffix = 0; |
7066 | else if (!check_qword_reg ()) | |
29b0f896 AM |
7067 | return 0; |
7068 | } | |
7069 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7070 | { | |
2eb952a4 | 7071 | if (intel_syntax |
3cd7f3e3 | 7072 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE |
2eb952a4 L |
7073 | && i.tm.opcode_modifier.no_wsuf) |
7074 | i.suffix = 0; | |
7075 | else if (!check_word_reg ()) | |
29b0f896 AM |
7076 | return 0; |
7077 | } | |
3cd7f3e3 L |
7078 | else if (intel_syntax |
7079 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
7080 | /* Do nothing if the instruction is going to ignore the prefix. */ |
7081 | ; | |
7082 | else | |
7083 | abort (); | |
65fca059 JB |
7084 | |
7085 | /* Undo the movsx/movzx change done above. */ | |
7086 | i.operands = numop; | |
29b0f896 | 7087 | } |
3cd7f3e3 L |
7088 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
7089 | && !i.suffix) | |
29b0f896 | 7090 | { |
13e600d0 JB |
7091 | i.suffix = stackop_size; |
7092 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
7093 | { |
7094 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
7095 | .code16gcc directive to support 16-bit mode with | |
7096 | 32-bit address. For IRET without a suffix, generate | |
7097 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
7098 | handler. */ | |
13e600d0 JB |
7099 | if (i.tm.base_opcode == 0xcf) |
7100 | { | |
7101 | i.suffix = WORD_MNEM_SUFFIX; | |
7102 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
7103 | } | |
7104 | /* Warn about changed behavior for segment register push/pop. */ | |
7105 | else if ((i.tm.base_opcode | 1) == 0x07) | |
7106 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
7107 | i.tm.name); | |
06f74c5c | 7108 | } |
29b0f896 | 7109 | } |
c006a730 | 7110 | else if (!i.suffix |
0cfa3eb3 JB |
7111 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
7112 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
7113 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
389d00a5 JB |
7114 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
7115 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ | |
64e74474 | 7116 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
7117 | { |
7118 | switch (flag_code) | |
7119 | { | |
7120 | case CODE_64BIT: | |
40fb9820 | 7121 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 7122 | { |
828c2a25 JB |
7123 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
7124 | || i.tm.opcode_modifier.no_lsuf) | |
7125 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
7126 | break; |
7127 | } | |
1a0670f3 | 7128 | /* Fall through. */ |
9306ca4a | 7129 | case CODE_32BIT: |
40fb9820 | 7130 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
7131 | i.suffix = LONG_MNEM_SUFFIX; |
7132 | break; | |
7133 | case CODE_16BIT: | |
40fb9820 | 7134 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
7135 | i.suffix = WORD_MNEM_SUFFIX; |
7136 | break; | |
7137 | } | |
7138 | } | |
252b5132 | 7139 | |
c006a730 | 7140 | if (!i.suffix |
3cd7f3e3 | 7141 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
7142 | /* Also cover lret/retf/iret in 64-bit mode. */ |
7143 | || (flag_code == CODE_64BIT | |
7144 | && !i.tm.opcode_modifier.no_lsuf | |
7145 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 7146 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
7147 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
7148 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
7149 | /* Accept FLDENV et al without suffix. */ |
7150 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 7151 | { |
6c0946d0 | 7152 | unsigned int suffixes, evex = 0; |
c006a730 JB |
7153 | |
7154 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
7155 | if (!i.tm.opcode_modifier.no_wsuf) | |
7156 | suffixes |= 1 << 1; | |
7157 | if (!i.tm.opcode_modifier.no_lsuf) | |
7158 | suffixes |= 1 << 2; | |
7159 | if (!i.tm.opcode_modifier.no_ldsuf) | |
7160 | suffixes |= 1 << 3; | |
7161 | if (!i.tm.opcode_modifier.no_ssuf) | |
7162 | suffixes |= 1 << 4; | |
7163 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
7164 | suffixes |= 1 << 5; | |
7165 | ||
6c0946d0 JB |
7166 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
7167 | also suitable for AT&T syntax mode, it was requested that this be | |
7168 | restricted to just Intel syntax. */ | |
5273a3cd | 7169 | if (intel_syntax && is_any_vex_encoding (&i.tm) && !i.broadcast.type) |
6c0946d0 | 7170 | { |
b9915cbc | 7171 | unsigned int op; |
6c0946d0 | 7172 | |
b9915cbc | 7173 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 7174 | { |
b9915cbc JB |
7175 | if (is_evex_encoding (&i.tm) |
7176 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 7177 | { |
b9915cbc JB |
7178 | if (i.tm.operand_types[op].bitfield.ymmword) |
7179 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
7180 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7181 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
7182 | if (!i.tm.opcode_modifier.evex | |
7183 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
7184 | i.tm.opcode_modifier.evex = EVEX512; | |
7185 | } | |
6c0946d0 | 7186 | |
b9915cbc JB |
7187 | if (i.tm.operand_types[op].bitfield.xmmword |
7188 | + i.tm.operand_types[op].bitfield.ymmword | |
7189 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
7190 | continue; | |
6c0946d0 | 7191 | |
b9915cbc JB |
7192 | /* Any properly sized operand disambiguates the insn. */ |
7193 | if (i.types[op].bitfield.xmmword | |
7194 | || i.types[op].bitfield.ymmword | |
7195 | || i.types[op].bitfield.zmmword) | |
7196 | { | |
7197 | suffixes &= ~(7 << 6); | |
7198 | evex = 0; | |
7199 | break; | |
7200 | } | |
6c0946d0 | 7201 | |
b9915cbc JB |
7202 | if ((i.flags[op] & Operand_Mem) |
7203 | && i.tm.operand_types[op].bitfield.unspecified) | |
7204 | { | |
7205 | if (i.tm.operand_types[op].bitfield.xmmword) | |
7206 | suffixes |= 1 << 6; | |
7207 | if (i.tm.operand_types[op].bitfield.ymmword) | |
7208 | suffixes |= 1 << 7; | |
7209 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7210 | suffixes |= 1 << 8; | |
7211 | if (is_evex_encoding (&i.tm)) | |
7212 | evex = EVEX512; | |
6c0946d0 JB |
7213 | } |
7214 | } | |
7215 | } | |
7216 | ||
7217 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 7218 | if (suffixes & (suffixes - 1)) |
9306ca4a | 7219 | { |
873494c8 | 7220 | if (intel_syntax |
3cd7f3e3 | 7221 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 7222 | || operand_check == check_error)) |
9306ca4a | 7223 | { |
c006a730 | 7224 | as_bad (_("ambiguous operand size for `%s'"), i.tm.name); |
9306ca4a JB |
7225 | return 0; |
7226 | } | |
c006a730 | 7227 | if (operand_check == check_error) |
9306ca4a | 7228 | { |
c006a730 JB |
7229 | as_bad (_("no instruction mnemonic suffix given and " |
7230 | "no register operands; can't size `%s'"), i.tm.name); | |
9306ca4a JB |
7231 | return 0; |
7232 | } | |
c006a730 | 7233 | if (operand_check == check_warning) |
873494c8 JB |
7234 | as_warn (_("%s; using default for `%s'"), |
7235 | intel_syntax | |
7236 | ? _("ambiguous operand size") | |
7237 | : _("no instruction mnemonic suffix given and " | |
7238 | "no register operands"), | |
7239 | i.tm.name); | |
c006a730 JB |
7240 | |
7241 | if (i.tm.opcode_modifier.floatmf) | |
7242 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 7243 | else if (is_movx) |
65fca059 | 7244 | /* handled below */; |
6c0946d0 JB |
7245 | else if (evex) |
7246 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
7247 | else if (flag_code == CODE_16BIT) |
7248 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 7249 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 7250 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
7251 | else |
7252 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 7253 | } |
29b0f896 | 7254 | } |
252b5132 | 7255 | |
389d00a5 | 7256 | if (is_movx) |
65fca059 JB |
7257 | { |
7258 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
7259 | In AT&T syntax, if there is no suffix (warned about above), the default | |
7260 | will be byte extension. */ | |
7261 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
7262 | i.tm.base_opcode |= 1; | |
7263 | ||
7264 | /* For further processing, the suffix should represent the destination | |
7265 | (register). This is already the case when one was used with | |
7266 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
7267 | no suffix to begin with. */ | |
7268 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
7269 | { | |
7270 | if (i.types[1].bitfield.word) | |
7271 | i.suffix = WORD_MNEM_SUFFIX; | |
7272 | else if (i.types[1].bitfield.qword) | |
7273 | i.suffix = QWORD_MNEM_SUFFIX; | |
7274 | else | |
7275 | i.suffix = LONG_MNEM_SUFFIX; | |
7276 | ||
7277 | i.tm.opcode_modifier.w = 0; | |
7278 | } | |
7279 | } | |
7280 | ||
50128d0c JB |
7281 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
7282 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
7283 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
7284 | ||
d2224064 JB |
7285 | /* Change the opcode based on the operand size given by i.suffix. */ |
7286 | switch (i.suffix) | |
29b0f896 | 7287 | { |
d2224064 JB |
7288 | /* Size floating point instruction. */ |
7289 | case LONG_MNEM_SUFFIX: | |
7290 | if (i.tm.opcode_modifier.floatmf) | |
7291 | { | |
7292 | i.tm.base_opcode ^= 4; | |
7293 | break; | |
7294 | } | |
7295 | /* fall through */ | |
7296 | case WORD_MNEM_SUFFIX: | |
7297 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 7298 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 7299 | if (i.tm.opcode_modifier.w) |
29b0f896 | 7300 | { |
50128d0c | 7301 | if (i.short_form) |
29b0f896 AM |
7302 | i.tm.base_opcode |= 8; |
7303 | else | |
7304 | i.tm.base_opcode |= 1; | |
7305 | } | |
d2224064 JB |
7306 | /* fall through */ |
7307 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
7308 | /* Now select between word & dword operations via the operand |
7309 | size prefix, except for instructions that will ignore this | |
7310 | prefix anyway. */ | |
c8f8eebc | 7311 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 7312 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
7313 | && !i.tm.opcode_modifier.floatmf |
7314 | && !is_any_vex_encoding (&i.tm) | |
7315 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
7316 | || (flag_code == CODE_64BIT | |
7317 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
7318 | { |
7319 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 7320 | |
0cfa3eb3 | 7321 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 7322 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 7323 | |
29b0f896 AM |
7324 | if (!add_prefix (prefix)) |
7325 | return 0; | |
24eab124 | 7326 | } |
252b5132 | 7327 | |
29b0f896 AM |
7328 | /* Set mode64 for an operand. */ |
7329 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 7330 | && flag_code == CODE_64BIT |
d2224064 | 7331 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 7332 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 7333 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
7334 | need rex64. */ |
7335 | && ! (i.operands == 2 | |
7336 | && i.tm.base_opcode == 0x90 | |
7337 | && i.tm.extension_opcode == None | |
75e5731b JB |
7338 | && i.types[0].bitfield.instance == Accum |
7339 | && i.types[0].bitfield.qword | |
7340 | && i.types[1].bitfield.instance == Accum | |
7341 | && i.types[1].bitfield.qword)) | |
d2224064 | 7342 | i.rex |= REX_W; |
3e73aa7c | 7343 | |
d2224064 | 7344 | break; |
8bbb3ad8 JB |
7345 | |
7346 | case 0: | |
f9a6a8f0 | 7347 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
7348 | when there are no suitable register operands. */ |
7349 | if (i.tm.opcode_modifier.w | |
7350 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
7351 | && (!i.reg_operands | |
7352 | || (i.reg_operands == 1 | |
7353 | /* ShiftCount */ | |
7354 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
7355 | /* InOutPortReg */ | |
7356 | || i.tm.operand_types[0].bitfield.instance == RegD | |
7357 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7358 | /* CRC32 */ | |
8b65b895 | 7359 | || is_crc32)))) |
8bbb3ad8 JB |
7360 | i.tm.base_opcode |= 1; |
7361 | break; | |
29b0f896 | 7362 | } |
7ecd2f8b | 7363 | |
c8f8eebc | 7364 | if (i.tm.opcode_modifier.addrprefixopreg) |
c0a30a9f | 7365 | { |
c8f8eebc JB |
7366 | gas_assert (!i.suffix); |
7367 | gas_assert (i.reg_operands); | |
c0a30a9f | 7368 | |
c8f8eebc JB |
7369 | if (i.tm.operand_types[0].bitfield.instance == Accum |
7370 | || i.operands == 1) | |
7371 | { | |
7372 | /* The address size override prefix changes the size of the | |
7373 | first operand. */ | |
7374 | if (flag_code == CODE_64BIT | |
7375 | && i.op[0].regs->reg_type.bitfield.word) | |
7376 | { | |
7377 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
7378 | i.tm.name); | |
7379 | return 0; | |
7380 | } | |
7381 | ||
7382 | if ((flag_code == CODE_32BIT | |
7383 | ? i.op[0].regs->reg_type.bitfield.word | |
7384 | : i.op[0].regs->reg_type.bitfield.dword) | |
7385 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
7386 | return 0; | |
7387 | } | |
c0a30a9f L |
7388 | else |
7389 | { | |
c8f8eebc JB |
7390 | /* Check invalid register operand when the address size override |
7391 | prefix changes the size of register operands. */ | |
7392 | unsigned int op; | |
7393 | enum { need_word, need_dword, need_qword } need; | |
7394 | ||
27f13469 | 7395 | /* Check the register operand for the address size prefix if |
b3a3496f | 7396 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 7397 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
7398 | if (i.mem_operands == 1 |
7399 | && i.reg_operands == 1 | |
7400 | && i.operands == 2 | |
27f13469 | 7401 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
7402 | && (flag_code == CODE_32BIT |
7403 | ? i.op[1].regs->reg_type.bitfield.word | |
7404 | : i.op[1].regs->reg_type.bitfield.dword) | |
7405 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
7406 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
7407 | || (x86_elf_abi == X86_64_X32_ABI | |
7408 | && i.base_reg | |
b3a3496f L |
7409 | && i.base_reg->reg_num == RegIP |
7410 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
7411 | #else |
7412 | || 0) | |
7413 | #endif | |
27f13469 L |
7414 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
7415 | return 0; | |
7416 | ||
c8f8eebc JB |
7417 | if (flag_code == CODE_32BIT) |
7418 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
7419 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
7420 | need = need_dword; |
7421 | else | |
7422 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 7423 | |
c8f8eebc JB |
7424 | for (op = 0; op < i.operands; op++) |
7425 | { | |
7426 | if (i.types[op].bitfield.class != Reg) | |
7427 | continue; | |
7428 | ||
7429 | switch (need) | |
7430 | { | |
7431 | case need_word: | |
7432 | if (i.op[op].regs->reg_type.bitfield.word) | |
7433 | continue; | |
7434 | break; | |
7435 | case need_dword: | |
7436 | if (i.op[op].regs->reg_type.bitfield.dword) | |
7437 | continue; | |
7438 | break; | |
7439 | case need_qword: | |
7440 | if (i.op[op].regs->reg_type.bitfield.qword) | |
7441 | continue; | |
7442 | break; | |
7443 | } | |
7444 | ||
7445 | as_bad (_("invalid register operand size for `%s'"), | |
7446 | i.tm.name); | |
7447 | return 0; | |
7448 | } | |
7449 | } | |
c0a30a9f L |
7450 | } |
7451 | ||
29b0f896 AM |
7452 | return 1; |
7453 | } | |
3e73aa7c | 7454 | |
29b0f896 | 7455 | static int |
543613e9 | 7456 | check_byte_reg (void) |
29b0f896 AM |
7457 | { |
7458 | int op; | |
543613e9 | 7459 | |
29b0f896 AM |
7460 | for (op = i.operands; --op >= 0;) |
7461 | { | |
dc821c5f | 7462 | /* Skip non-register operands. */ |
bab6aec1 | 7463 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
7464 | continue; |
7465 | ||
29b0f896 AM |
7466 | /* If this is an eight bit register, it's OK. If it's the 16 or |
7467 | 32 bit version of an eight bit register, we will just use the | |
7468 | low portion, and that's OK too. */ | |
dc821c5f | 7469 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
7470 | continue; |
7471 | ||
5a819eb9 | 7472 | /* I/O port address operands are OK too. */ |
75e5731b JB |
7473 | if (i.tm.operand_types[op].bitfield.instance == RegD |
7474 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
7475 | continue; |
7476 | ||
9706160a | 7477 | /* crc32 only wants its source operand checked here. */ |
389d00a5 JB |
7478 | if (i.tm.base_opcode == 0xf0 |
7479 | && i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
8b65b895 L |
7480 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2 |
7481 | && op != 0) | |
9344ff29 L |
7482 | continue; |
7483 | ||
29b0f896 | 7484 | /* Any other register is bad. */ |
73c76375 JB |
7485 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7486 | register_prefix, i.op[op].regs->reg_name, | |
7487 | i.tm.name, i.suffix); | |
7488 | return 0; | |
29b0f896 AM |
7489 | } |
7490 | return 1; | |
7491 | } | |
7492 | ||
7493 | static int | |
e3bb37b5 | 7494 | check_long_reg (void) |
29b0f896 AM |
7495 | { |
7496 | int op; | |
7497 | ||
7498 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7499 | /* Skip non-register operands. */ |
bab6aec1 | 7500 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7501 | continue; |
29b0f896 AM |
7502 | /* Reject eight bit registers, except where the template requires |
7503 | them. (eg. movzb) */ | |
dc821c5f | 7504 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7505 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7506 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7507 | && (i.tm.operand_types[op].bitfield.word |
7508 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7509 | { |
a540244d L |
7510 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7511 | register_prefix, | |
29b0f896 AM |
7512 | i.op[op].regs->reg_name, |
7513 | i.tm.name, | |
7514 | i.suffix); | |
7515 | return 0; | |
7516 | } | |
be4c5e58 L |
7517 | /* Error if the e prefix on a general reg is missing. */ |
7518 | else if (i.types[op].bitfield.word | |
bab6aec1 | 7519 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7520 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7521 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 7522 | { |
be4c5e58 L |
7523 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7524 | register_prefix, i.op[op].regs->reg_name, | |
7525 | i.suffix); | |
7526 | return 0; | |
252b5132 | 7527 | } |
e4630f71 | 7528 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 7529 | else if (i.types[op].bitfield.qword |
bab6aec1 | 7530 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7531 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7532 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 7533 | { |
34828aad | 7534 | if (intel_syntax |
65fca059 | 7535 | && i.tm.opcode_modifier.toqword |
3528c362 | 7536 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7537 | { |
ca61edf2 | 7538 | /* Convert to QWORD. We want REX byte. */ |
34828aad L |
7539 | i.suffix = QWORD_MNEM_SUFFIX; |
7540 | } | |
7541 | else | |
7542 | { | |
2b5d6a91 | 7543 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7544 | register_prefix, i.op[op].regs->reg_name, |
7545 | i.suffix); | |
7546 | return 0; | |
7547 | } | |
29b0f896 AM |
7548 | } |
7549 | return 1; | |
7550 | } | |
252b5132 | 7551 | |
29b0f896 | 7552 | static int |
e3bb37b5 | 7553 | check_qword_reg (void) |
29b0f896 AM |
7554 | { |
7555 | int op; | |
252b5132 | 7556 | |
29b0f896 | 7557 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 7558 | /* Skip non-register operands. */ |
bab6aec1 | 7559 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7560 | continue; |
29b0f896 AM |
7561 | /* Reject eight bit registers, except where the template requires |
7562 | them. (eg. movzb) */ | |
dc821c5f | 7563 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7564 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7565 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7566 | && (i.tm.operand_types[op].bitfield.word |
7567 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7568 | { |
a540244d L |
7569 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7570 | register_prefix, | |
29b0f896 AM |
7571 | i.op[op].regs->reg_name, |
7572 | i.tm.name, | |
7573 | i.suffix); | |
7574 | return 0; | |
7575 | } | |
e4630f71 | 7576 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
7577 | else if ((i.types[op].bitfield.word |
7578 | || i.types[op].bitfield.dword) | |
bab6aec1 | 7579 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7580 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7581 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
7582 | { |
7583 | /* Prohibit these changes in the 64bit mode, since the | |
7584 | lowering is more complicated. */ | |
34828aad | 7585 | if (intel_syntax |
ca61edf2 | 7586 | && i.tm.opcode_modifier.todword |
3528c362 | 7587 | && i.types[0].bitfield.class != RegSIMD) |
34828aad | 7588 | { |
ca61edf2 | 7589 | /* Convert to DWORD. We don't want REX byte. */ |
34828aad L |
7590 | i.suffix = LONG_MNEM_SUFFIX; |
7591 | } | |
7592 | else | |
7593 | { | |
2b5d6a91 | 7594 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
34828aad L |
7595 | register_prefix, i.op[op].regs->reg_name, |
7596 | i.suffix); | |
7597 | return 0; | |
7598 | } | |
252b5132 | 7599 | } |
29b0f896 AM |
7600 | return 1; |
7601 | } | |
252b5132 | 7602 | |
29b0f896 | 7603 | static int |
e3bb37b5 | 7604 | check_word_reg (void) |
29b0f896 AM |
7605 | { |
7606 | int op; | |
7607 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 7608 | /* Skip non-register operands. */ |
bab6aec1 | 7609 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 7610 | continue; |
29b0f896 AM |
7611 | /* Reject eight bit registers, except where the template requires |
7612 | them. (eg. movzb) */ | |
dc821c5f | 7613 | else if (i.types[op].bitfield.byte |
bab6aec1 | 7614 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7615 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
7616 | && (i.tm.operand_types[op].bitfield.word |
7617 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 7618 | { |
a540244d L |
7619 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7620 | register_prefix, | |
29b0f896 AM |
7621 | i.op[op].regs->reg_name, |
7622 | i.tm.name, | |
7623 | i.suffix); | |
7624 | return 0; | |
7625 | } | |
9706160a JB |
7626 | /* Error if the e or r prefix on a general reg is present. */ |
7627 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 7628 | || i.types[op].bitfield.qword) |
bab6aec1 | 7629 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 7630 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 7631 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 7632 | { |
9706160a JB |
7633 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
7634 | register_prefix, i.op[op].regs->reg_name, | |
7635 | i.suffix); | |
7636 | return 0; | |
29b0f896 AM |
7637 | } |
7638 | return 1; | |
7639 | } | |
252b5132 | 7640 | |
29b0f896 | 7641 | static int |
40fb9820 | 7642 | update_imm (unsigned int j) |
29b0f896 | 7643 | { |
bc0844ae | 7644 | i386_operand_type overlap = i.types[j]; |
40fb9820 L |
7645 | if ((overlap.bitfield.imm8 |
7646 | || overlap.bitfield.imm8s | |
7647 | || overlap.bitfield.imm16 | |
7648 | || overlap.bitfield.imm32 | |
7649 | || overlap.bitfield.imm32s | |
7650 | || overlap.bitfield.imm64) | |
0dfbf9d7 L |
7651 | && !operand_type_equal (&overlap, &imm8) |
7652 | && !operand_type_equal (&overlap, &imm8s) | |
7653 | && !operand_type_equal (&overlap, &imm16) | |
7654 | && !operand_type_equal (&overlap, &imm32) | |
7655 | && !operand_type_equal (&overlap, &imm32s) | |
7656 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 AM |
7657 | { |
7658 | if (i.suffix) | |
7659 | { | |
40fb9820 L |
7660 | i386_operand_type temp; |
7661 | ||
0dfbf9d7 | 7662 | operand_type_set (&temp, 0); |
7ab9ffdd | 7663 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
7664 | { |
7665 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
7666 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
7667 | } | |
7668 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7669 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
7670 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7671 | { | |
7672 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
7673 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
7674 | } | |
7675 | else | |
7676 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
7677 | overlap = temp; | |
29b0f896 | 7678 | } |
0dfbf9d7 L |
7679 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
7680 | || operand_type_equal (&overlap, &imm16_32) | |
7681 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 7682 | { |
40fb9820 | 7683 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 7684 | overlap = imm16; |
40fb9820 | 7685 | else |
65da13b5 | 7686 | overlap = imm32s; |
29b0f896 | 7687 | } |
8bbb3ad8 JB |
7688 | else if (i.prefix[REX_PREFIX] & REX_W) |
7689 | overlap = operand_type_and (overlap, imm32s); | |
7690 | else if (i.prefix[DATA_PREFIX]) | |
7691 | overlap = operand_type_and (overlap, | |
7692 | flag_code != CODE_16BIT ? imm16 : imm32); | |
0dfbf9d7 L |
7693 | if (!operand_type_equal (&overlap, &imm8) |
7694 | && !operand_type_equal (&overlap, &imm8s) | |
7695 | && !operand_type_equal (&overlap, &imm16) | |
7696 | && !operand_type_equal (&overlap, &imm32) | |
7697 | && !operand_type_equal (&overlap, &imm32s) | |
7698 | && !operand_type_equal (&overlap, &imm64)) | |
29b0f896 | 7699 | { |
4eed87de AM |
7700 | as_bad (_("no instruction mnemonic suffix given; " |
7701 | "can't determine immediate size")); | |
29b0f896 AM |
7702 | return 0; |
7703 | } | |
7704 | } | |
40fb9820 | 7705 | i.types[j] = overlap; |
29b0f896 | 7706 | |
40fb9820 L |
7707 | return 1; |
7708 | } | |
7709 | ||
7710 | static int | |
7711 | finalize_imm (void) | |
7712 | { | |
bc0844ae | 7713 | unsigned int j, n; |
29b0f896 | 7714 | |
bc0844ae L |
7715 | /* Update the first 2 immediate operands. */ |
7716 | n = i.operands > 2 ? 2 : i.operands; | |
7717 | if (n) | |
7718 | { | |
7719 | for (j = 0; j < n; j++) | |
7720 | if (update_imm (j) == 0) | |
7721 | return 0; | |
40fb9820 | 7722 | |
bc0844ae L |
7723 | /* The 3rd operand can't be immediate operand. */ |
7724 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
7725 | } | |
29b0f896 AM |
7726 | |
7727 | return 1; | |
7728 | } | |
7729 | ||
7730 | static int | |
e3bb37b5 | 7731 | process_operands (void) |
29b0f896 AM |
7732 | { |
7733 | /* Default segment register this instruction will use for memory | |
7734 | accesses. 0 means unknown. This is only for optimizing out | |
7735 | unnecessary segment overrides. */ | |
5e042380 | 7736 | const reg_entry *default_seg = NULL; |
29b0f896 | 7737 | |
a5aeccd9 JB |
7738 | if (i.tm.opcode_modifier.sse2avx) |
7739 | { | |
7740 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
7741 | need converting. */ | |
7742 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
7743 | i.prefix[REX_PREFIX] = 0; | |
7744 | i.rex_encoding = 0; | |
7745 | } | |
c423d21a JB |
7746 | /* ImmExt should be processed after SSE2AVX. */ |
7747 | else if (i.tm.opcode_modifier.immext) | |
7748 | process_immext (); | |
a5aeccd9 | 7749 | |
2426c15f | 7750 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 7751 | { |
91d6fa6a NC |
7752 | unsigned int dupl = i.operands; |
7753 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
7754 | unsigned int j; |
7755 | ||
c0f3af97 | 7756 | /* The destination must be an xmm register. */ |
9c2799c2 | 7757 | gas_assert (i.reg_operands |
91d6fa6a | 7758 | && MAX_OPERANDS > dupl |
7ab9ffdd | 7759 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 7760 | |
75e5731b | 7761 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7762 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 7763 | { |
8cd7925b | 7764 | if (i.tm.opcode_modifier.vexsources == VEX3SOURCES) |
c0f3af97 L |
7765 | { |
7766 | /* Keep xmm0 for instructions with VEX prefix and 3 | |
7767 | sources. */ | |
75e5731b | 7768 | i.tm.operand_types[0].bitfield.instance = InstanceNone; |
3528c362 | 7769 | i.tm.operand_types[0].bitfield.class = RegSIMD; |
c0f3af97 L |
7770 | goto duplicate; |
7771 | } | |
e2ec9d29 | 7772 | else |
c0f3af97 L |
7773 | { |
7774 | /* We remove the first xmm0 and keep the number of | |
7775 | operands unchanged, which in fact duplicates the | |
7776 | destination. */ | |
7777 | for (j = 1; j < i.operands; j++) | |
7778 | { | |
7779 | i.op[j - 1] = i.op[j]; | |
7780 | i.types[j - 1] = i.types[j]; | |
7781 | i.tm.operand_types[j - 1] = i.tm.operand_types[j]; | |
8dc0818e | 7782 | i.flags[j - 1] = i.flags[j]; |
c0f3af97 L |
7783 | } |
7784 | } | |
7785 | } | |
7786 | else if (i.tm.opcode_modifier.implicit1stxmm0) | |
7ab9ffdd | 7787 | { |
91d6fa6a | 7788 | gas_assert ((MAX_OPERANDS - 1) > dupl |
8cd7925b L |
7789 | && (i.tm.opcode_modifier.vexsources |
7790 | == VEX3SOURCES)); | |
c0f3af97 L |
7791 | |
7792 | /* Add the implicit xmm0 for instructions with VEX prefix | |
7793 | and 3 sources. */ | |
7794 | for (j = i.operands; j > 0; j--) | |
7795 | { | |
7796 | i.op[j] = i.op[j - 1]; | |
7797 | i.types[j] = i.types[j - 1]; | |
7798 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 7799 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
7800 | } |
7801 | i.op[0].regs | |
629310ab | 7802 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 7803 | i.types[0] = regxmm; |
c0f3af97 L |
7804 | i.tm.operand_types[0] = regxmm; |
7805 | ||
7806 | i.operands += 2; | |
7807 | i.reg_operands += 2; | |
7808 | i.tm.operands += 2; | |
7809 | ||
91d6fa6a | 7810 | dupl++; |
c0f3af97 | 7811 | dest++; |
91d6fa6a NC |
7812 | i.op[dupl] = i.op[dest]; |
7813 | i.types[dupl] = i.types[dest]; | |
7814 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7815 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 7816 | } |
c0f3af97 L |
7817 | else |
7818 | { | |
dc1e8a47 | 7819 | duplicate: |
c0f3af97 L |
7820 | i.operands++; |
7821 | i.reg_operands++; | |
7822 | i.tm.operands++; | |
7823 | ||
91d6fa6a NC |
7824 | i.op[dupl] = i.op[dest]; |
7825 | i.types[dupl] = i.types[dest]; | |
7826 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 7827 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
7828 | } |
7829 | ||
7830 | if (i.tm.opcode_modifier.immext) | |
7831 | process_immext (); | |
7832 | } | |
75e5731b | 7833 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 7834 | && i.tm.operand_types[0].bitfield.xmmword) |
c0f3af97 L |
7835 | { |
7836 | unsigned int j; | |
7837 | ||
9fcfb3d7 L |
7838 | for (j = 1; j < i.operands; j++) |
7839 | { | |
7840 | i.op[j - 1] = i.op[j]; | |
7841 | i.types[j - 1] = i.types[j]; | |
7842 | ||
7843 | /* We need to adjust fields in i.tm since they are used by | |
7844 | build_modrm_byte. */ | |
7845 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
7846 | |
7847 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
7848 | } |
7849 | ||
e2ec9d29 L |
7850 | i.operands--; |
7851 | i.reg_operands--; | |
e2ec9d29 L |
7852 | i.tm.operands--; |
7853 | } | |
920d2ddc IT |
7854 | else if (i.tm.opcode_modifier.implicitquadgroup) |
7855 | { | |
a477a8c4 JB |
7856 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
7857 | ||
920d2ddc | 7858 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 7859 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
7860 | regnum = register_number (i.op[1].regs); |
7861 | first_reg_in_group = regnum & ~3; | |
7862 | last_reg_in_group = first_reg_in_group + 3; | |
7863 | if (regnum != first_reg_in_group) | |
7864 | as_warn (_("source register `%s%s' implicitly denotes" | |
7865 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
7866 | register_prefix, i.op[1].regs->reg_name, | |
7867 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
7868 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
7869 | i.tm.name); | |
7870 | } | |
e2ec9d29 L |
7871 | else if (i.tm.opcode_modifier.regkludge) |
7872 | { | |
7873 | /* The imul $imm, %reg instruction is converted into | |
7874 | imul $imm, %reg, %reg, and the clr %reg instruction | |
7875 | is converted into xor %reg, %reg. */ | |
7876 | ||
7877 | unsigned int first_reg_op; | |
7878 | ||
7879 | if (operand_type_check (i.types[0], reg)) | |
7880 | first_reg_op = 0; | |
7881 | else | |
7882 | first_reg_op = 1; | |
7883 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 7884 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 7885 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
7886 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
7887 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
7888 | i.operands++; | |
7889 | i.reg_operands++; | |
29b0f896 AM |
7890 | } |
7891 | ||
85b80b0f | 7892 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
7893 | { |
7894 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
7895 | must be put into the modrm byte). Now, we make the modrm and |
7896 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
7897 | |
7898 | default_seg = build_modrm_byte (); | |
7899 | } | |
00cee14f | 7900 | else if (i.types[0].bitfield.class == SReg) |
85b80b0f JB |
7901 | { |
7902 | if (flag_code != CODE_64BIT | |
7903 | ? i.tm.base_opcode == POP_SEG_SHORT | |
7904 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 7905 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
7906 | && i.op[0].regs->reg_num < 4) |
7907 | { | |
7908 | as_bad (_("you can't `%s %s%s'"), | |
7909 | i.tm.name, register_prefix, i.op[0].regs->reg_name); | |
7910 | return 0; | |
7911 | } | |
389d00a5 JB |
7912 | if (i.op[0].regs->reg_num > 3 |
7913 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE ) | |
85b80b0f | 7914 | { |
389d00a5 JB |
7915 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
7916 | i.tm.opcode_modifier.opcodespace = SPACE_0F; | |
85b80b0f JB |
7917 | } |
7918 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
7919 | } | |
389d00a5 JB |
7920 | else if (i.tm.opcode_modifier.opcodespace == SPACE_BASE |
7921 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) | |
29b0f896 | 7922 | { |
5e042380 | 7923 | default_seg = reg_ds; |
29b0f896 | 7924 | } |
40fb9820 | 7925 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
7926 | { |
7927 | /* For the string instructions that allow a segment override | |
7928 | on one of their operands, the default segment is ds. */ | |
5e042380 | 7929 | default_seg = reg_ds; |
29b0f896 | 7930 | } |
50128d0c | 7931 | else if (i.short_form) |
85b80b0f JB |
7932 | { |
7933 | /* The register or float register operand is in operand | |
7934 | 0 or 1. */ | |
bab6aec1 | 7935 | unsigned int op = i.tm.operand_types[0].bitfield.class != Reg; |
85b80b0f JB |
7936 | |
7937 | /* Register goes in low 3 bits of opcode. */ | |
7938 | i.tm.base_opcode |= i.op[op].regs->reg_num; | |
7939 | if ((i.op[op].regs->reg_flags & RegRex) != 0) | |
7940 | i.rex |= REX_B; | |
7941 | if (!quiet_warnings && i.tm.opcode_modifier.ugh) | |
7942 | { | |
7943 | /* Warn about some common errors, but press on regardless. | |
7944 | The first case can be generated by gcc (<= 2.8.1). */ | |
7945 | if (i.operands == 2) | |
7946 | { | |
7947 | /* Reversed arguments on faddp, fsubp, etc. */ | |
7948 | as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name, | |
7949 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
7950 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
7951 | } | |
7952 | else | |
7953 | { | |
7954 | /* Extraneous `l' suffix on fp insn. */ | |
7955 | as_warn (_("translating to `%s %s%s'"), i.tm.name, | |
7956 | register_prefix, i.op[0].regs->reg_name); | |
7957 | } | |
7958 | } | |
7959 | } | |
29b0f896 | 7960 | |
514a8bb0 | 7961 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
514a8bb0 | 7962 | && i.tm.base_opcode == 0x8d /* lea */ |
35648716 | 7963 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
514a8bb0 | 7964 | && !is_any_vex_encoding(&i.tm)) |
92334ad2 JB |
7965 | { |
7966 | if (!quiet_warnings) | |
7967 | as_warn (_("segment override on `%s' is ineffectual"), i.tm.name); | |
7968 | if (optimize) | |
7969 | { | |
7970 | i.seg[0] = NULL; | |
7971 | i.prefix[SEG_PREFIX] = 0; | |
7972 | } | |
7973 | } | |
52271982 AM |
7974 | |
7975 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
7976 | is neither the default nor the one already recorded from a prefix, |
7977 | use an opcode prefix to select it. If we never figured out what | |
7978 | the default segment is, then default_seg will be zero at this | |
7979 | point, and the specified segment prefix will always be used. */ | |
7980 | if (i.seg[0] | |
7981 | && i.seg[0] != default_seg | |
5e042380 | 7982 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 7983 | { |
5e042380 | 7984 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
7985 | return 0; |
7986 | } | |
7987 | return 1; | |
7988 | } | |
7989 | ||
a5aeccd9 | 7990 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
5b7c81bd | 7991 | bool do_sse2avx) |
a5aeccd9 JB |
7992 | { |
7993 | if (r->reg_flags & RegRex) | |
7994 | { | |
7995 | if (i.rex & rex_bit) | |
7996 | as_bad (_("same type of prefix used twice")); | |
7997 | i.rex |= rex_bit; | |
7998 | } | |
7999 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
8000 | { | |
8001 | gas_assert (i.vex.register_specifier == r); | |
8002 | i.vex.register_specifier += 8; | |
8003 | } | |
8004 | ||
8005 | if (r->reg_flags & RegVRex) | |
8006 | i.vrex |= rex_bit; | |
8007 | } | |
8008 | ||
5e042380 | 8009 | static const reg_entry * |
e3bb37b5 | 8010 | build_modrm_byte (void) |
29b0f896 | 8011 | { |
5e042380 | 8012 | const reg_entry *default_seg = NULL; |
c0f3af97 | 8013 | unsigned int source, dest; |
8cd7925b | 8014 | int vex_3_sources; |
c0f3af97 | 8015 | |
8cd7925b | 8016 | vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES; |
c0f3af97 L |
8017 | if (vex_3_sources) |
8018 | { | |
91d6fa6a | 8019 | unsigned int nds, reg_slot; |
4c2c6516 | 8020 | expressionS *exp; |
c0f3af97 | 8021 | |
6b8d3588 | 8022 | dest = i.operands - 1; |
c0f3af97 | 8023 | nds = dest - 1; |
922d8de8 | 8024 | |
a683cc34 | 8025 | /* There are 2 kinds of instructions: |
bed3d976 | 8026 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 8027 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 8028 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 8029 | ZMM register. |
bed3d976 | 8030 | 2. 4 operands: 4 register operands or 3 register operands |
2f1bada2 | 8031 | plus 1 memory operand, with VexXDS. */ |
922d8de8 | 8032 | gas_assert ((i.reg_operands == 4 |
bed3d976 JB |
8033 | || (i.reg_operands == 3 && i.mem_operands == 1)) |
8034 | && i.tm.opcode_modifier.vexvvvv == VEXXDS | |
dcd7e323 | 8035 | && i.tm.opcode_modifier.vexw |
3528c362 | 8036 | && i.tm.operand_types[dest].bitfield.class == RegSIMD); |
a683cc34 | 8037 | |
48db9223 JB |
8038 | /* If VexW1 is set, the first non-immediate operand is the source and |
8039 | the second non-immediate one is encoded in the immediate operand. */ | |
8040 | if (i.tm.opcode_modifier.vexw == VEXW1) | |
8041 | { | |
8042 | source = i.imm_operands; | |
8043 | reg_slot = i.imm_operands + 1; | |
8044 | } | |
8045 | else | |
8046 | { | |
8047 | source = i.imm_operands + 1; | |
8048 | reg_slot = i.imm_operands; | |
8049 | } | |
8050 | ||
a683cc34 | 8051 | if (i.imm_operands == 0) |
bed3d976 JB |
8052 | { |
8053 | /* When there is no immediate operand, generate an 8bit | |
8054 | immediate operand to encode the first operand. */ | |
8055 | exp = &im_expressions[i.imm_operands++]; | |
8056 | i.op[i.operands].imms = exp; | |
8057 | i.types[i.operands] = imm8; | |
8058 | i.operands++; | |
8059 | ||
3528c362 | 8060 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
bed3d976 JB |
8061 | exp->X_op = O_constant; |
8062 | exp->X_add_number = register_number (i.op[reg_slot].regs) << 4; | |
43234a1e L |
8063 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
8064 | } | |
922d8de8 | 8065 | else |
bed3d976 | 8066 | { |
9d3bf266 JB |
8067 | gas_assert (i.imm_operands == 1); |
8068 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
8069 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 8070 | |
9d3bf266 JB |
8071 | /* Turn on Imm8 again so that output_imm will generate it. */ |
8072 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 8073 | |
3528c362 | 8074 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); |
9d3bf266 | 8075 | i.op[0].imms->X_add_number |
bed3d976 | 8076 | |= register_number (i.op[reg_slot].regs) << 4; |
43234a1e | 8077 | gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0); |
bed3d976 | 8078 | } |
a683cc34 | 8079 | |
3528c362 | 8080 | gas_assert (i.tm.operand_types[nds].bitfield.class == RegSIMD); |
dae39acc | 8081 | i.vex.register_specifier = i.op[nds].regs; |
c0f3af97 L |
8082 | } |
8083 | else | |
8084 | source = dest = 0; | |
29b0f896 AM |
8085 | |
8086 | /* i.reg_operands MUST be the number of real register operands; | |
c0f3af97 L |
8087 | implicit registers do not count. If there are 3 register |
8088 | operands, it must be a instruction with VexNDS. For a | |
8089 | instruction with VexNDD, the destination register is encoded | |
8090 | in VEX prefix. If there are 4 register operands, it must be | |
8091 | a instruction with VEX prefix and 3 sources. */ | |
7ab9ffdd L |
8092 | if (i.mem_operands == 0 |
8093 | && ((i.reg_operands == 2 | |
2426c15f | 8094 | && i.tm.opcode_modifier.vexvvvv <= VEXXDS) |
7ab9ffdd | 8095 | || (i.reg_operands == 3 |
2426c15f | 8096 | && i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd | 8097 | || (i.reg_operands == 4 && vex_3_sources))) |
29b0f896 | 8098 | { |
cab737b9 L |
8099 | switch (i.operands) |
8100 | { | |
8101 | case 2: | |
8102 | source = 0; | |
8103 | break; | |
8104 | case 3: | |
c81128dc L |
8105 | /* When there are 3 operands, one of them may be immediate, |
8106 | which may be the first or the last operand. Otherwise, | |
c0f3af97 L |
8107 | the first operand must be shift count register (cl) or it |
8108 | is an instruction with VexNDS. */ | |
9c2799c2 | 8109 | gas_assert (i.imm_operands == 1 |
7ab9ffdd | 8110 | || (i.imm_operands == 0 |
2426c15f | 8111 | && (i.tm.opcode_modifier.vexvvvv == VEXXDS |
75e5731b JB |
8112 | || (i.types[0].bitfield.instance == RegC |
8113 | && i.types[0].bitfield.byte)))); | |
40fb9820 | 8114 | if (operand_type_check (i.types[0], imm) |
75e5731b JB |
8115 | || (i.types[0].bitfield.instance == RegC |
8116 | && i.types[0].bitfield.byte)) | |
40fb9820 L |
8117 | source = 1; |
8118 | else | |
8119 | source = 0; | |
cab737b9 L |
8120 | break; |
8121 | case 4: | |
368d64cc L |
8122 | /* When there are 4 operands, the first two must be 8bit |
8123 | immediate operands. The source operand will be the 3rd | |
c0f3af97 L |
8124 | one. |
8125 | ||
8126 | For instructions with VexNDS, if the first operand | |
8127 | an imm8, the source operand is the 2nd one. If the last | |
8128 | operand is imm8, the source operand is the first one. */ | |
9c2799c2 | 8129 | gas_assert ((i.imm_operands == 2 |
7ab9ffdd L |
8130 | && i.types[0].bitfield.imm8 |
8131 | && i.types[1].bitfield.imm8) | |
2426c15f | 8132 | || (i.tm.opcode_modifier.vexvvvv == VEXXDS |
7ab9ffdd L |
8133 | && i.imm_operands == 1 |
8134 | && (i.types[0].bitfield.imm8 | |
43234a1e | 8135 | || i.types[i.operands - 1].bitfield.imm8 |
ca5312a2 | 8136 | || i.rounding.type != rc_none))); |
9f2670f2 L |
8137 | if (i.imm_operands == 2) |
8138 | source = 2; | |
8139 | else | |
c0f3af97 L |
8140 | { |
8141 | if (i.types[0].bitfield.imm8) | |
8142 | source = 1; | |
8143 | else | |
8144 | source = 0; | |
8145 | } | |
c0f3af97 L |
8146 | break; |
8147 | case 5: | |
e771e7c9 | 8148 | if (is_evex_encoding (&i.tm)) |
43234a1e L |
8149 | { |
8150 | /* For EVEX instructions, when there are 5 operands, the | |
8151 | first one must be immediate operand. If the second one | |
8152 | is immediate operand, the source operand is the 3th | |
8153 | one. If the last one is immediate operand, the source | |
8154 | operand is the 2nd one. */ | |
8155 | gas_assert (i.imm_operands == 2 | |
8156 | && i.tm.opcode_modifier.sae | |
8157 | && operand_type_check (i.types[0], imm)); | |
8158 | if (operand_type_check (i.types[1], imm)) | |
8159 | source = 2; | |
8160 | else if (operand_type_check (i.types[4], imm)) | |
8161 | source = 1; | |
8162 | else | |
8163 | abort (); | |
8164 | } | |
cab737b9 L |
8165 | break; |
8166 | default: | |
8167 | abort (); | |
8168 | } | |
8169 | ||
c0f3af97 L |
8170 | if (!vex_3_sources) |
8171 | { | |
8172 | dest = source + 1; | |
8173 | ||
43234a1e L |
8174 | /* RC/SAE operand could be between DEST and SRC. That happens |
8175 | when one operand is GPR and the other one is XMM/YMM/ZMM | |
8176 | register. */ | |
ca5312a2 | 8177 | if (i.rounding.type != rc_none && i.rounding.operand == dest) |
43234a1e L |
8178 | dest++; |
8179 | ||
2426c15f | 8180 | if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
c0f3af97 | 8181 | { |
43234a1e | 8182 | /* For instructions with VexNDS, the register-only source |
c5d0745b | 8183 | operand must be a 32/64bit integer, XMM, YMM, ZMM, or mask |
dfd69174 | 8184 | register. It is encoded in VEX prefix. */ |
f12dc422 L |
8185 | |
8186 | i386_operand_type op; | |
8187 | unsigned int vvvv; | |
8188 | ||
c2ecccb3 L |
8189 | /* Swap two source operands if needed. */ |
8190 | if (i.tm.opcode_modifier.swapsources) | |
f12dc422 L |
8191 | { |
8192 | vvvv = source; | |
8193 | source = dest; | |
8194 | } | |
8195 | else | |
8196 | vvvv = dest; | |
8197 | ||
8198 | op = i.tm.operand_types[vvvv]; | |
c0f3af97 | 8199 | if ((dest + 1) >= i.operands |
bab6aec1 | 8200 | || ((op.bitfield.class != Reg |
dc821c5f | 8201 | || (!op.bitfield.dword && !op.bitfield.qword)) |
3528c362 | 8202 | && op.bitfield.class != RegSIMD |
43234a1e | 8203 | && !operand_type_equal (&op, ®mask))) |
c0f3af97 | 8204 | abort (); |
f12dc422 | 8205 | i.vex.register_specifier = i.op[vvvv].regs; |
c0f3af97 L |
8206 | dest++; |
8207 | } | |
8208 | } | |
29b0f896 AM |
8209 | |
8210 | i.rm.mode = 3; | |
dfd69174 JB |
8211 | /* One of the register operands will be encoded in the i.rm.reg |
8212 | field, the other in the combined i.rm.mode and i.rm.regmem | |
29b0f896 AM |
8213 | fields. If no form of this instruction supports a memory |
8214 | destination operand, then we assume the source operand may | |
8215 | sometimes be a memory operand and so we need to store the | |
8216 | destination in the i.rm.reg field. */ | |
dfd69174 | 8217 | if (!i.tm.opcode_modifier.regmem |
40fb9820 | 8218 | && operand_type_check (i.tm.operand_types[dest], anymem) == 0) |
29b0f896 AM |
8219 | { |
8220 | i.rm.reg = i.op[dest].regs->reg_num; | |
8221 | i.rm.regmem = i.op[source].regs->reg_num; | |
a5aeccd9 | 8222 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8223 | set_rex_vrex (i.op[source].regs, REX_B, false); |
29b0f896 AM |
8224 | } |
8225 | else | |
8226 | { | |
8227 | i.rm.reg = i.op[source].regs->reg_num; | |
8228 | i.rm.regmem = i.op[dest].regs->reg_num; | |
a5aeccd9 | 8229 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); |
5b7c81bd | 8230 | set_rex_vrex (i.op[source].regs, REX_R, false); |
29b0f896 | 8231 | } |
e0c7f900 | 8232 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) |
c4a530c5 | 8233 | { |
4a5c67ed | 8234 | if (i.types[!i.tm.opcode_modifier.regmem].bitfield.class != RegCR) |
c4a530c5 | 8235 | abort (); |
e0c7f900 | 8236 | i.rex &= ~REX_R; |
c4a530c5 JB |
8237 | add_prefix (LOCK_PREFIX_OPCODE); |
8238 | } | |
29b0f896 AM |
8239 | } |
8240 | else | |
8241 | { /* If it's not 2 reg operands... */ | |
c0f3af97 L |
8242 | unsigned int mem; |
8243 | ||
29b0f896 AM |
8244 | if (i.mem_operands) |
8245 | { | |
8246 | unsigned int fake_zero_displacement = 0; | |
99018f42 | 8247 | unsigned int op; |
4eed87de | 8248 | |
7ab9ffdd | 8249 | for (op = 0; op < i.operands; op++) |
8dc0818e | 8250 | if (i.flags[op] & Operand_Mem) |
7ab9ffdd | 8251 | break; |
7ab9ffdd | 8252 | gas_assert (op < i.operands); |
29b0f896 | 8253 | |
63112cd6 | 8254 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 8255 | { |
260cd341 LC |
8256 | /* The index register of VSIB shouldn't be RegIZ. */ |
8257 | if (i.tm.opcode_modifier.sib != SIBMEM | |
8258 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
8259 | abort (); |
8260 | ||
8261 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8262 | if (!i.base_reg) | |
8263 | { | |
8264 | i.sib.base = NO_BASE_REGISTER; | |
8265 | i.sib.scale = i.log2_scale_factor; | |
8266 | i.types[op].bitfield.disp8 = 0; | |
8267 | i.types[op].bitfield.disp16 = 0; | |
8268 | i.types[op].bitfield.disp64 = 0; | |
a9aabc23 | 8269 | if (want_disp32 (&i.tm)) |
6c30d220 L |
8270 | { |
8271 | /* Must be 32 bit */ | |
8272 | i.types[op].bitfield.disp32 = 1; | |
8273 | i.types[op].bitfield.disp32s = 0; | |
8274 | } | |
8275 | else | |
8276 | { | |
8277 | i.types[op].bitfield.disp32 = 0; | |
8278 | i.types[op].bitfield.disp32s = 1; | |
8279 | } | |
8280 | } | |
260cd341 LC |
8281 | |
8282 | /* Since the mandatory SIB always has index register, so | |
8283 | the code logic remains unchanged. The non-mandatory SIB | |
8284 | without index register is allowed and will be handled | |
8285 | later. */ | |
8286 | if (i.index_reg) | |
8287 | { | |
8288 | if (i.index_reg->reg_num == RegIZ) | |
8289 | i.sib.index = NO_INDEX_REGISTER; | |
8290 | else | |
8291 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 8292 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 8293 | } |
6c30d220 L |
8294 | } |
8295 | ||
5e042380 | 8296 | default_seg = reg_ds; |
29b0f896 AM |
8297 | |
8298 | if (i.base_reg == 0) | |
8299 | { | |
8300 | i.rm.mode = 0; | |
8301 | if (!i.disp_operands) | |
9bb129e8 | 8302 | fake_zero_displacement = 1; |
29b0f896 AM |
8303 | if (i.index_reg == 0) |
8304 | { | |
73053c1f JB |
8305 | i386_operand_type newdisp; |
8306 | ||
260cd341 LC |
8307 | /* Both check for VSIB and mandatory non-vector SIB. */ |
8308 | gas_assert (!i.tm.opcode_modifier.sib | |
8309 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 8310 | /* Operand is just <disp> */ |
20f0a1fc | 8311 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
8312 | { |
8313 | /* 64bit mode overwrites the 32bit absolute | |
8314 | addressing by RIP relative addressing and | |
8315 | absolute addressing is encoded by one of the | |
8316 | redundant SIB forms. */ | |
8317 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8318 | i.sib.base = NO_BASE_REGISTER; | |
8319 | i.sib.index = NO_INDEX_REGISTER; | |
a9aabc23 | 8320 | newdisp = (want_disp32(&i.tm) ? disp32 : disp32s); |
20f0a1fc | 8321 | } |
fc225355 L |
8322 | else if ((flag_code == CODE_16BIT) |
8323 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
8324 | { |
8325 | i.rm.regmem = NO_BASE_REGISTER_16; | |
73053c1f | 8326 | newdisp = disp16; |
20f0a1fc NC |
8327 | } |
8328 | else | |
8329 | { | |
8330 | i.rm.regmem = NO_BASE_REGISTER; | |
73053c1f | 8331 | newdisp = disp32; |
29b0f896 | 8332 | } |
73053c1f JB |
8333 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
8334 | i.types[op] = operand_type_or (i.types[op], newdisp); | |
29b0f896 | 8335 | } |
63112cd6 | 8336 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8337 | { |
6c30d220 | 8338 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 8339 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8340 | i.sib.index = NO_INDEX_REGISTER; |
8341 | else | |
8342 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8343 | i.sib.base = NO_BASE_REGISTER; |
8344 | i.sib.scale = i.log2_scale_factor; | |
8345 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
40fb9820 L |
8346 | i.types[op].bitfield.disp8 = 0; |
8347 | i.types[op].bitfield.disp16 = 0; | |
8348 | i.types[op].bitfield.disp64 = 0; | |
a9aabc23 | 8349 | if (want_disp32 (&i.tm)) |
40fb9820 L |
8350 | { |
8351 | /* Must be 32 bit */ | |
8352 | i.types[op].bitfield.disp32 = 1; | |
8353 | i.types[op].bitfield.disp32s = 0; | |
8354 | } | |
29b0f896 | 8355 | else |
40fb9820 L |
8356 | { |
8357 | i.types[op].bitfield.disp32 = 0; | |
8358 | i.types[op].bitfield.disp32s = 1; | |
8359 | } | |
29b0f896 | 8360 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8361 | i.rex |= REX_X; |
29b0f896 AM |
8362 | } |
8363 | } | |
8364 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 8365 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 8366 | { |
63112cd6 | 8367 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 8368 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
8369 | i.types[op].bitfield.disp8 = 0; |
8370 | i.types[op].bitfield.disp16 = 0; | |
8371 | i.types[op].bitfield.disp32 = 0; | |
8372 | i.types[op].bitfield.disp32s = 1; | |
8373 | i.types[op].bitfield.disp64 = 0; | |
71903a11 | 8374 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
8375 | if (! i.disp_operands) |
8376 | fake_zero_displacement = 1; | |
29b0f896 | 8377 | } |
dc821c5f | 8378 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 8379 | { |
63112cd6 | 8380 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
8381 | switch (i.base_reg->reg_num) |
8382 | { | |
8383 | case 3: /* (%bx) */ | |
8384 | if (i.index_reg == 0) | |
8385 | i.rm.regmem = 7; | |
8386 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
8387 | i.rm.regmem = i.index_reg->reg_num - 6; | |
8388 | break; | |
8389 | case 5: /* (%bp) */ | |
5e042380 | 8390 | default_seg = reg_ss; |
29b0f896 AM |
8391 | if (i.index_reg == 0) |
8392 | { | |
8393 | i.rm.regmem = 6; | |
40fb9820 | 8394 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
8395 | { |
8396 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 8397 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
8398 | i.types[op].bitfield.disp16 = 1; |
8399 | else | |
8400 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 8401 | fake_zero_displacement = 1; |
29b0f896 AM |
8402 | } |
8403 | } | |
8404 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
8405 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
8406 | break; | |
8407 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
8408 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
8409 | } | |
41eb8e88 L |
8410 | if (!fake_zero_displacement |
8411 | && !i.disp_operands | |
8412 | && i.disp_encoding) | |
8413 | { | |
8414 | fake_zero_displacement = 1; | |
8415 | if (i.disp_encoding == disp_encoding_8bit) | |
8416 | i.types[op].bitfield.disp8 = 1; | |
8417 | else | |
8418 | i.types[op].bitfield.disp16 = 1; | |
8419 | } | |
29b0f896 AM |
8420 | i.rm.mode = mode_from_disp_size (i.types[op]); |
8421 | } | |
8422 | else /* i.base_reg and 32/64 bit mode */ | |
8423 | { | |
a9aabc23 | 8424 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 8425 | { |
73053c1f JB |
8426 | i.types[op].bitfield.disp16 = 0; |
8427 | i.types[op].bitfield.disp64 = 0; | |
a9aabc23 | 8428 | if (!want_disp32 (&i.tm)) |
73053c1f JB |
8429 | { |
8430 | i.types[op].bitfield.disp32 = 0; | |
8431 | i.types[op].bitfield.disp32s = 1; | |
8432 | } | |
40fb9820 | 8433 | else |
73053c1f JB |
8434 | { |
8435 | i.types[op].bitfield.disp32 = 1; | |
8436 | i.types[op].bitfield.disp32s = 0; | |
8437 | } | |
40fb9820 | 8438 | } |
20f0a1fc | 8439 | |
63112cd6 | 8440 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 8441 | i.rm.regmem = i.base_reg->reg_num; |
29b0f896 | 8442 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8443 | i.rex |= REX_B; |
29b0f896 AM |
8444 | i.sib.base = i.base_reg->reg_num; |
8445 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
8446 | complications. */ | |
848930b2 JB |
8447 | if (!(i.base_reg->reg_flags & RegRex) |
8448 | && (i.base_reg->reg_num == EBP_REG_NUM | |
8449 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 8450 | default_seg = reg_ss; |
848930b2 | 8451 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 8452 | { |
848930b2 | 8453 | fake_zero_displacement = 1; |
1a02d6b0 L |
8454 | if (i.disp_encoding == disp_encoding_32bit) |
8455 | i.types[op].bitfield.disp32 = 1; | |
8456 | else | |
8457 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
8458 | } |
8459 | i.sib.scale = i.log2_scale_factor; | |
8460 | if (i.index_reg == 0) | |
8461 | { | |
260cd341 LC |
8462 | /* Only check for VSIB. */ |
8463 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
8464 | && i.tm.opcode_modifier.sib != VECSIB256 | |
8465 | && i.tm.opcode_modifier.sib != VECSIB512); | |
8466 | ||
29b0f896 AM |
8467 | /* <disp>(%esp) becomes two byte modrm with no index |
8468 | register. We've already stored the code for esp | |
8469 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
8470 | Any base register besides %esp will not use the | |
8471 | extra modrm byte. */ | |
8472 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 8473 | } |
63112cd6 | 8474 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8475 | { |
e968fc9b | 8476 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8477 | i.sib.index = NO_INDEX_REGISTER; |
8478 | else | |
8479 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8480 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
8481 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 8482 | i.rex |= REX_X; |
29b0f896 | 8483 | } |
67a4f2b7 AO |
8484 | |
8485 | if (i.disp_operands | |
8486 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
8487 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
8488 | i.rm.mode = 0; | |
8489 | else | |
a501d77e L |
8490 | { |
8491 | if (!fake_zero_displacement | |
8492 | && !i.disp_operands | |
8493 | && i.disp_encoding) | |
8494 | { | |
8495 | fake_zero_displacement = 1; | |
8496 | if (i.disp_encoding == disp_encoding_8bit) | |
8497 | i.types[op].bitfield.disp8 = 1; | |
8498 | else | |
8499 | i.types[op].bitfield.disp32 = 1; | |
8500 | } | |
8501 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8502 | } | |
29b0f896 | 8503 | } |
252b5132 | 8504 | |
29b0f896 AM |
8505 | if (fake_zero_displacement) |
8506 | { | |
8507 | /* Fakes a zero displacement assuming that i.types[op] | |
8508 | holds the correct displacement size. */ | |
8509 | expressionS *exp; | |
8510 | ||
9c2799c2 | 8511 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
8512 | exp = &disp_expressions[i.disp_operands++]; |
8513 | i.op[op].disps = exp; | |
8514 | exp->X_op = O_constant; | |
8515 | exp->X_add_number = 0; | |
8516 | exp->X_add_symbol = (symbolS *) 0; | |
8517 | exp->X_op_symbol = (symbolS *) 0; | |
8518 | } | |
c0f3af97 L |
8519 | |
8520 | mem = op; | |
29b0f896 | 8521 | } |
c0f3af97 L |
8522 | else |
8523 | mem = ~0; | |
252b5132 | 8524 | |
8c43a48b | 8525 | if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) |
5dd85c99 SP |
8526 | { |
8527 | if (operand_type_check (i.types[0], imm)) | |
8528 | i.vex.register_specifier = NULL; | |
8529 | else | |
8530 | { | |
8531 | /* VEX.vvvv encodes one of the sources when the first | |
8532 | operand is not an immediate. */ | |
1ef99a7b | 8533 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8534 | i.vex.register_specifier = i.op[0].regs; |
8535 | else | |
8536 | i.vex.register_specifier = i.op[1].regs; | |
8537 | } | |
8538 | ||
8539 | /* Destination is a XMM register encoded in the ModRM.reg | |
8540 | and VEX.R bit. */ | |
8541 | i.rm.reg = i.op[2].regs->reg_num; | |
8542 | if ((i.op[2].regs->reg_flags & RegRex) != 0) | |
8543 | i.rex |= REX_R; | |
8544 | ||
8545 | /* ModRM.rm and VEX.B encodes the other source. */ | |
8546 | if (!i.mem_operands) | |
8547 | { | |
8548 | i.rm.mode = 3; | |
8549 | ||
1ef99a7b | 8550 | if (i.tm.opcode_modifier.vexw == VEXW0) |
5dd85c99 SP |
8551 | i.rm.regmem = i.op[1].regs->reg_num; |
8552 | else | |
8553 | i.rm.regmem = i.op[0].regs->reg_num; | |
8554 | ||
8555 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8556 | i.rex |= REX_B; | |
8557 | } | |
8558 | } | |
2426c15f | 8559 | else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) |
f88c9eb0 SP |
8560 | { |
8561 | i.vex.register_specifier = i.op[2].regs; | |
8562 | if (!i.mem_operands) | |
8563 | { | |
8564 | i.rm.mode = 3; | |
8565 | i.rm.regmem = i.op[1].regs->reg_num; | |
8566 | if ((i.op[1].regs->reg_flags & RegRex) != 0) | |
8567 | i.rex |= REX_B; | |
8568 | } | |
8569 | } | |
29b0f896 AM |
8570 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
8571 | (if any) based on i.tm.extension_opcode. Again, we must be | |
8572 | careful to make sure that segment/control/debug/test/MMX | |
8573 | registers are coded into the i.rm.reg field. */ | |
f88c9eb0 | 8574 | else if (i.reg_operands) |
29b0f896 | 8575 | { |
99018f42 | 8576 | unsigned int op; |
7ab9ffdd L |
8577 | unsigned int vex_reg = ~0; |
8578 | ||
8579 | for (op = 0; op < i.operands; op++) | |
921eafea L |
8580 | if (i.types[op].bitfield.class == Reg |
8581 | || i.types[op].bitfield.class == RegBND | |
8582 | || i.types[op].bitfield.class == RegMask | |
8583 | || i.types[op].bitfield.class == SReg | |
8584 | || i.types[op].bitfield.class == RegCR | |
8585 | || i.types[op].bitfield.class == RegDR | |
8586 | || i.types[op].bitfield.class == RegTR | |
8587 | || i.types[op].bitfield.class == RegSIMD | |
8588 | || i.types[op].bitfield.class == RegMMX) | |
8589 | break; | |
c0209578 | 8590 | |
7ab9ffdd L |
8591 | if (vex_3_sources) |
8592 | op = dest; | |
2426c15f | 8593 | else if (i.tm.opcode_modifier.vexvvvv == VEXXDS) |
7ab9ffdd L |
8594 | { |
8595 | /* For instructions with VexNDS, the register-only | |
8596 | source operand is encoded in VEX prefix. */ | |
8597 | gas_assert (mem != (unsigned int) ~0); | |
c0f3af97 | 8598 | |
7ab9ffdd | 8599 | if (op > mem) |
c0f3af97 | 8600 | { |
7ab9ffdd L |
8601 | vex_reg = op++; |
8602 | gas_assert (op < i.operands); | |
c0f3af97 L |
8603 | } |
8604 | else | |
c0f3af97 | 8605 | { |
f12dc422 L |
8606 | /* Check register-only source operand when two source |
8607 | operands are swapped. */ | |
8608 | if (!i.tm.operand_types[op].bitfield.baseindex | |
8609 | && i.tm.operand_types[op + 1].bitfield.baseindex) | |
8610 | { | |
8611 | vex_reg = op; | |
8612 | op += 2; | |
8613 | gas_assert (mem == (vex_reg + 1) | |
8614 | && op < i.operands); | |
8615 | } | |
8616 | else | |
8617 | { | |
8618 | vex_reg = op + 1; | |
8619 | gas_assert (vex_reg < i.operands); | |
8620 | } | |
c0f3af97 | 8621 | } |
7ab9ffdd | 8622 | } |
2426c15f | 8623 | else if (i.tm.opcode_modifier.vexvvvv == VEXNDD) |
7ab9ffdd | 8624 | { |
f12dc422 | 8625 | /* For instructions with VexNDD, the register destination |
7ab9ffdd | 8626 | is encoded in VEX prefix. */ |
f12dc422 L |
8627 | if (i.mem_operands == 0) |
8628 | { | |
8629 | /* There is no memory operand. */ | |
8630 | gas_assert ((op + 2) == i.operands); | |
8631 | vex_reg = op + 1; | |
8632 | } | |
8633 | else | |
8d63c93e | 8634 | { |
ed438a93 JB |
8635 | /* There are only 2 non-immediate operands. */ |
8636 | gas_assert (op < i.imm_operands + 2 | |
8637 | && i.operands == i.imm_operands + 2); | |
8638 | vex_reg = i.imm_operands + 1; | |
f12dc422 | 8639 | } |
7ab9ffdd L |
8640 | } |
8641 | else | |
8642 | gas_assert (op < i.operands); | |
99018f42 | 8643 | |
7ab9ffdd L |
8644 | if (vex_reg != (unsigned int) ~0) |
8645 | { | |
f12dc422 | 8646 | i386_operand_type *type = &i.tm.operand_types[vex_reg]; |
7ab9ffdd | 8647 | |
bab6aec1 | 8648 | if ((type->bitfield.class != Reg |
dc821c5f | 8649 | || (!type->bitfield.dword && !type->bitfield.qword)) |
3528c362 | 8650 | && type->bitfield.class != RegSIMD |
43234a1e | 8651 | && !operand_type_equal (type, ®mask)) |
7ab9ffdd | 8652 | abort (); |
f88c9eb0 | 8653 | |
7ab9ffdd L |
8654 | i.vex.register_specifier = i.op[vex_reg].regs; |
8655 | } | |
8656 | ||
1b9f0c97 L |
8657 | /* Don't set OP operand twice. */ |
8658 | if (vex_reg != op) | |
7ab9ffdd | 8659 | { |
1b9f0c97 L |
8660 | /* If there is an extension opcode to put here, the |
8661 | register number must be put into the regmem field. */ | |
8662 | if (i.tm.extension_opcode != None) | |
8663 | { | |
8664 | i.rm.regmem = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8665 | set_rex_vrex (i.op[op].regs, REX_B, |
8666 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 L |
8667 | } |
8668 | else | |
8669 | { | |
8670 | i.rm.reg = i.op[op].regs->reg_num; | |
a5aeccd9 JB |
8671 | set_rex_vrex (i.op[op].regs, REX_R, |
8672 | i.tm.opcode_modifier.sse2avx); | |
1b9f0c97 | 8673 | } |
7ab9ffdd | 8674 | } |
252b5132 | 8675 | |
29b0f896 AM |
8676 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
8677 | must set it to 3 to indicate this is a register operand | |
8678 | in the regmem field. */ | |
8679 | if (!i.mem_operands) | |
8680 | i.rm.mode = 3; | |
8681 | } | |
252b5132 | 8682 | |
29b0f896 | 8683 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
c1e679ec | 8684 | if (i.tm.extension_opcode != None) |
29b0f896 AM |
8685 | i.rm.reg = i.tm.extension_opcode; |
8686 | } | |
8687 | return default_seg; | |
8688 | } | |
252b5132 | 8689 | |
48ef937e JB |
8690 | static INLINE void |
8691 | frag_opcode_byte (unsigned char byte) | |
8692 | { | |
8693 | if (now_seg != absolute_section) | |
8694 | FRAG_APPEND_1_CHAR (byte); | |
8695 | else | |
8696 | ++abs_section_offset; | |
8697 | } | |
8698 | ||
376cd056 JB |
8699 | static unsigned int |
8700 | flip_code16 (unsigned int code16) | |
8701 | { | |
8702 | gas_assert (i.tm.operands == 1); | |
8703 | ||
8704 | return !(i.prefix[REX_PREFIX] & REX_W) | |
8705 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
8706 | || i.tm.operand_types[0].bitfield.disp32s | |
8707 | : i.tm.operand_types[0].bitfield.disp16) | |
8708 | ? CODE16 : 0; | |
8709 | } | |
8710 | ||
29b0f896 | 8711 | static void |
e3bb37b5 | 8712 | output_branch (void) |
29b0f896 AM |
8713 | { |
8714 | char *p; | |
f8a5c266 | 8715 | int size; |
29b0f896 AM |
8716 | int code16; |
8717 | int prefix; | |
8718 | relax_substateT subtype; | |
8719 | symbolS *sym; | |
8720 | offsetT off; | |
8721 | ||
48ef937e JB |
8722 | if (now_seg == absolute_section) |
8723 | { | |
8724 | as_bad (_("relaxable branches not supported in absolute section")); | |
8725 | return; | |
8726 | } | |
8727 | ||
f8a5c266 | 8728 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
a501d77e | 8729 | size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL; |
29b0f896 AM |
8730 | |
8731 | prefix = 0; | |
8732 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8733 | { |
29b0f896 AM |
8734 | prefix = 1; |
8735 | i.prefixes -= 1; | |
376cd056 | 8736 | code16 ^= flip_code16(code16); |
252b5132 | 8737 | } |
29b0f896 AM |
8738 | /* Pentium4 branch hints. */ |
8739 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8740 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8741 | { |
29b0f896 AM |
8742 | prefix++; |
8743 | i.prefixes--; | |
8744 | } | |
8745 | if (i.prefix[REX_PREFIX] != 0) | |
8746 | { | |
8747 | prefix++; | |
8748 | i.prefixes--; | |
2f66722d AM |
8749 | } |
8750 | ||
7e8b059b L |
8751 | /* BND prefixed jump. */ |
8752 | if (i.prefix[BND_PREFIX] != 0) | |
8753 | { | |
6cb0a70e JB |
8754 | prefix++; |
8755 | i.prefixes--; | |
7e8b059b L |
8756 | } |
8757 | ||
f2810fe0 JB |
8758 | if (i.prefixes != 0) |
8759 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
29b0f896 AM |
8760 | |
8761 | /* It's always a symbol; End frag & setup for relax. | |
8762 | Make sure there is enough room in this frag for the largest | |
8763 | instruction we may generate in md_convert_frag. This is 2 | |
8764 | bytes for the opcode and room for the prefix and largest | |
8765 | displacement. */ | |
8766 | frag_grow (prefix + 2 + 4); | |
8767 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
8768 | p = frag_more (prefix + 1); | |
8769 | if (i.prefix[DATA_PREFIX] != 0) | |
8770 | *p++ = DATA_PREFIX_OPCODE; | |
8771 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
8772 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
8773 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
8774 | if (i.prefix[BND_PREFIX] != 0) |
8775 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
8776 | if (i.prefix[REX_PREFIX] != 0) |
8777 | *p++ = i.prefix[REX_PREFIX]; | |
8778 | *p = i.tm.base_opcode; | |
8779 | ||
8780 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 8781 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 8782 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 8783 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 8784 | else |
f8a5c266 | 8785 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 8786 | subtype |= code16; |
3e73aa7c | 8787 | |
29b0f896 AM |
8788 | sym = i.op[0].disps->X_add_symbol; |
8789 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 8790 | |
29b0f896 AM |
8791 | if (i.op[0].disps->X_op != O_constant |
8792 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 8793 | { |
29b0f896 AM |
8794 | /* Handle complex expressions. */ |
8795 | sym = make_expr_symbol (i.op[0].disps); | |
8796 | off = 0; | |
8797 | } | |
3e73aa7c | 8798 | |
29b0f896 AM |
8799 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
8800 | Pass reloc in fr_var. */ | |
d258b828 | 8801 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 8802 | } |
3e73aa7c | 8803 | |
bd7ab16b L |
8804 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8805 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
8806 | symbol S. */ | |
8807 | ||
5b7c81bd | 8808 | static bool |
bd7ab16b L |
8809 | need_plt32_p (symbolS *s) |
8810 | { | |
8811 | /* PLT32 relocation is ELF only. */ | |
8812 | if (!IS_ELF) | |
5b7c81bd | 8813 | return false; |
bd7ab16b | 8814 | |
a5def729 RO |
8815 | #ifdef TE_SOLARIS |
8816 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
8817 | krtld support it. */ | |
5b7c81bd | 8818 | return false; |
a5def729 RO |
8819 | #endif |
8820 | ||
bd7ab16b L |
8821 | /* Since there is no need to prepare for PLT branch on x86-64, we |
8822 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
8823 | be used as a marker for 32-bit PC-relative branches. */ | |
8824 | if (!object_64bit) | |
5b7c81bd | 8825 | return false; |
bd7ab16b | 8826 | |
44365e88 | 8827 | if (s == NULL) |
5b7c81bd | 8828 | return false; |
44365e88 | 8829 | |
bd7ab16b L |
8830 | /* Weak or undefined symbol need PLT32 relocation. */ |
8831 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 8832 | return true; |
bd7ab16b L |
8833 | |
8834 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
8835 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 8836 | return false; |
bd7ab16b L |
8837 | |
8838 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
8839 | non-default visibilities are treated as normal global symbol | |
8840 | so that PLT32 relocation can be used as a marker for 32-bit | |
8841 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 8842 | return true; |
bd7ab16b L |
8843 | } |
8844 | #endif | |
8845 | ||
29b0f896 | 8846 | static void |
e3bb37b5 | 8847 | output_jump (void) |
29b0f896 AM |
8848 | { |
8849 | char *p; | |
8850 | int size; | |
3e02c1cc | 8851 | fixS *fixP; |
bd7ab16b | 8852 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 8853 | |
0cfa3eb3 | 8854 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
8855 | { |
8856 | /* This is a loop or jecxz type instruction. */ | |
8857 | size = 1; | |
8858 | if (i.prefix[ADDR_PREFIX] != 0) | |
8859 | { | |
48ef937e | 8860 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
8861 | i.prefixes -= 1; |
8862 | } | |
8863 | /* Pentium4 branch hints. */ | |
8864 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8865 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
8866 | { | |
48ef937e | 8867 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 8868 | i.prefixes--; |
3e73aa7c JH |
8869 | } |
8870 | } | |
29b0f896 AM |
8871 | else |
8872 | { | |
8873 | int code16; | |
3e73aa7c | 8874 | |
29b0f896 AM |
8875 | code16 = 0; |
8876 | if (flag_code == CODE_16BIT) | |
8877 | code16 = CODE16; | |
3e73aa7c | 8878 | |
29b0f896 AM |
8879 | if (i.prefix[DATA_PREFIX] != 0) |
8880 | { | |
48ef937e | 8881 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 8882 | i.prefixes -= 1; |
376cd056 | 8883 | code16 ^= flip_code16(code16); |
29b0f896 | 8884 | } |
252b5132 | 8885 | |
29b0f896 AM |
8886 | size = 4; |
8887 | if (code16) | |
8888 | size = 2; | |
8889 | } | |
9fcc94b6 | 8890 | |
6cb0a70e JB |
8891 | /* BND prefixed jump. */ |
8892 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 8893 | { |
48ef937e | 8894 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
8895 | i.prefixes -= 1; |
8896 | } | |
252b5132 | 8897 | |
6cb0a70e | 8898 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 8899 | { |
48ef937e | 8900 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
8901 | i.prefixes -= 1; |
8902 | } | |
8903 | ||
f2810fe0 JB |
8904 | if (i.prefixes != 0) |
8905 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
e0890092 | 8906 | |
48ef937e JB |
8907 | if (now_seg == absolute_section) |
8908 | { | |
9a182d04 | 8909 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
8910 | return; |
8911 | } | |
8912 | ||
9a182d04 JB |
8913 | p = frag_more (i.opcode_length + size); |
8914 | switch (i.opcode_length) | |
42164a71 L |
8915 | { |
8916 | case 2: | |
8917 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 8918 | /* Fall through. */ |
42164a71 L |
8919 | case 1: |
8920 | *p++ = i.tm.base_opcode; | |
8921 | break; | |
8922 | default: | |
8923 | abort (); | |
8924 | } | |
e0890092 | 8925 | |
bd7ab16b L |
8926 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8927 | if (size == 4 | |
8928 | && jump_reloc == NO_RELOC | |
8929 | && need_plt32_p (i.op[0].disps->X_add_symbol)) | |
8930 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
8931 | #endif | |
8932 | ||
8933 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
8934 | ||
3e02c1cc | 8935 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 8936 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 8937 | |
eb19308f JB |
8938 | /* All jumps handled here are signed, but don't unconditionally use a |
8939 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
8940 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
8941 | respectively. */ | |
8942 | switch (size) | |
8943 | { | |
8944 | case 1: | |
8945 | fixP->fx_signed = 1; | |
8946 | break; | |
8947 | ||
8948 | case 2: | |
8949 | if (i.tm.base_opcode == 0xc7f8) | |
8950 | fixP->fx_signed = 1; | |
8951 | break; | |
8952 | ||
8953 | case 4: | |
8954 | if (flag_code == CODE_64BIT) | |
8955 | fixP->fx_signed = 1; | |
8956 | break; | |
8957 | } | |
29b0f896 | 8958 | } |
e0890092 | 8959 | |
29b0f896 | 8960 | static void |
e3bb37b5 | 8961 | output_interseg_jump (void) |
29b0f896 AM |
8962 | { |
8963 | char *p; | |
8964 | int size; | |
8965 | int prefix; | |
8966 | int code16; | |
252b5132 | 8967 | |
29b0f896 AM |
8968 | code16 = 0; |
8969 | if (flag_code == CODE_16BIT) | |
8970 | code16 = CODE16; | |
a217f122 | 8971 | |
29b0f896 AM |
8972 | prefix = 0; |
8973 | if (i.prefix[DATA_PREFIX] != 0) | |
8974 | { | |
8975 | prefix = 1; | |
8976 | i.prefixes -= 1; | |
8977 | code16 ^= CODE16; | |
8978 | } | |
6cb0a70e JB |
8979 | |
8980 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 8981 | |
29b0f896 AM |
8982 | size = 4; |
8983 | if (code16) | |
8984 | size = 2; | |
252b5132 | 8985 | |
f2810fe0 JB |
8986 | if (i.prefixes != 0) |
8987 | as_warn (_("skipping prefixes on `%s'"), i.tm.name); | |
252b5132 | 8988 | |
48ef937e JB |
8989 | if (now_seg == absolute_section) |
8990 | { | |
8991 | abs_section_offset += prefix + 1 + 2 + size; | |
8992 | return; | |
8993 | } | |
8994 | ||
29b0f896 AM |
8995 | /* 1 opcode; 2 segment; offset */ |
8996 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 8997 | |
29b0f896 AM |
8998 | if (i.prefix[DATA_PREFIX] != 0) |
8999 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 9000 | |
29b0f896 AM |
9001 | if (i.prefix[REX_PREFIX] != 0) |
9002 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 9003 | |
29b0f896 AM |
9004 | *p++ = i.tm.base_opcode; |
9005 | if (i.op[1].imms->X_op == O_constant) | |
9006 | { | |
9007 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 9008 | |
29b0f896 AM |
9009 | if (size == 2 |
9010 | && !fits_in_unsigned_word (n) | |
9011 | && !fits_in_signed_word (n)) | |
9012 | { | |
9013 | as_bad (_("16-bit jump out of range")); | |
9014 | return; | |
9015 | } | |
9016 | md_number_to_chars (p, n, size); | |
9017 | } | |
9018 | else | |
9019 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 9020 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
9021 | |
9022 | p += size; | |
9023 | if (i.op[0].imms->X_op == O_constant) | |
9024 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
9025 | else | |
9026 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
9027 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 9028 | } |
a217f122 | 9029 | |
b4a3a7b4 L |
9030 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9031 | void | |
9032 | x86_cleanup (void) | |
9033 | { | |
9034 | char *p; | |
9035 | asection *seg = now_seg; | |
9036 | subsegT subseg = now_subseg; | |
9037 | asection *sec; | |
9038 | unsigned int alignment, align_size_1; | |
9039 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
9040 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
9041 | unsigned int padding; | |
9042 | ||
50c95a73 | 9043 | if (!IS_ELF || (!x86_used_note && !x86_feature_2_used)) |
b4a3a7b4 L |
9044 | return; |
9045 | ||
b4a3a7b4 L |
9046 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
9047 | ||
9048 | /* The .note.gnu.property section layout: | |
9049 | ||
9050 | Field Length Contents | |
9051 | ---- ---- ---- | |
9052 | n_namsz 4 4 | |
9053 | n_descsz 4 The note descriptor size | |
9054 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
9055 | n_name 4 "GNU" | |
9056 | n_desc n_descsz The program property array | |
9057 | .... .... .... | |
9058 | */ | |
9059 | ||
9060 | /* Create the .note.gnu.property section. */ | |
9061 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 9062 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
9063 | (SEC_ALLOC |
9064 | | SEC_LOAD | |
9065 | | SEC_DATA | |
9066 | | SEC_HAS_CONTENTS | |
9067 | | SEC_READONLY)); | |
9068 | ||
9069 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
9070 | { | |
9071 | align_size_1 = 7; | |
9072 | alignment = 3; | |
9073 | } | |
9074 | else | |
9075 | { | |
9076 | align_size_1 = 3; | |
9077 | alignment = 2; | |
9078 | } | |
9079 | ||
fd361982 | 9080 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
9081 | elf_section_type (sec) = SHT_NOTE; |
9082 | ||
50c95a73 L |
9083 | if (x86_used_note) |
9084 | { | |
9085 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size | |
9086 | + 4-byte data */ | |
9087 | isa_1_descsz_raw = 4 + 4 + 4; | |
9088 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
9089 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
9090 | } | |
9091 | else | |
9092 | { | |
9093 | isa_1_descsz_raw = 0; | |
9094 | isa_1_descsz = 0; | |
9095 | } | |
b4a3a7b4 L |
9096 | |
9097 | feature_2_descsz_raw = isa_1_descsz; | |
9098 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
50c95a73 | 9099 | + 4-byte data */ |
b4a3a7b4 L |
9100 | feature_2_descsz_raw += 4 + 4 + 4; |
9101 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
9102 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
9103 | & ~align_size_1); | |
9104 | ||
9105 | descsz = feature_2_descsz; | |
9106 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
9107 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
9108 | ||
9109 | /* Write n_namsz. */ | |
9110 | md_number_to_chars (p, (valueT) 4, 4); | |
9111 | ||
9112 | /* Write n_descsz. */ | |
9113 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
9114 | ||
9115 | /* Write n_type. */ | |
9116 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
9117 | ||
9118 | /* Write n_name. */ | |
9119 | memcpy (p + 4 * 3, "GNU", 4); | |
9120 | ||
50c95a73 L |
9121 | if (isa_1_descsz != 0) |
9122 | { | |
9123 | /* Write 4-byte type. */ | |
9124 | md_number_to_chars (p + 4 * 4, | |
9125 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 9126 | |
50c95a73 L |
9127 | /* Write 4-byte data size. */ |
9128 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 9129 | |
50c95a73 L |
9130 | /* Write 4-byte data. */ |
9131 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 9132 | |
50c95a73 L |
9133 | /* Zero out paddings. */ |
9134 | padding = isa_1_descsz - isa_1_descsz_raw; | |
9135 | if (padding) | |
9136 | memset (p + 4 * 7, 0, padding); | |
9137 | } | |
b4a3a7b4 L |
9138 | |
9139 | /* Write 4-byte type. */ | |
9140 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
9141 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
9142 | ||
9143 | /* Write 4-byte data size. */ | |
9144 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
9145 | ||
9146 | /* Write 4-byte data. */ | |
9147 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
9148 | (valueT) x86_feature_2_used, 4); | |
9149 | ||
9150 | /* Zero out paddings. */ | |
9151 | padding = feature_2_descsz - feature_2_descsz_raw; | |
9152 | if (padding) | |
9153 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
9154 | ||
9155 | /* We probably can't restore the current segment, for there likely | |
9156 | isn't one yet... */ | |
9157 | if (seg && subseg) | |
9158 | subseg_set (seg, subseg); | |
9159 | } | |
9160 | #endif | |
9161 | ||
9c33702b JB |
9162 | static unsigned int |
9163 | encoding_length (const fragS *start_frag, offsetT start_off, | |
9164 | const char *frag_now_ptr) | |
9165 | { | |
9166 | unsigned int len = 0; | |
9167 | ||
9168 | if (start_frag != frag_now) | |
9169 | { | |
9170 | const fragS *fr = start_frag; | |
9171 | ||
9172 | do { | |
9173 | len += fr->fr_fix; | |
9174 | fr = fr->fr_next; | |
9175 | } while (fr && fr != frag_now); | |
9176 | } | |
9177 | ||
9178 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
9179 | } | |
9180 | ||
e379e5f3 | 9181 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
9182 | be macro-fused with conditional jumps. |
9183 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
9184 | or is one of the following format: | |
9185 | ||
9186 | cmp m, imm | |
9187 | add m, imm | |
9188 | sub m, imm | |
9189 | test m, imm | |
9190 | and m, imm | |
9191 | inc m | |
9192 | dec m | |
9193 | ||
9194 | it is unfusible. */ | |
e379e5f3 L |
9195 | |
9196 | static int | |
79d72f45 | 9197 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9198 | { |
9199 | /* No RIP address. */ | |
9200 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
9201 | return 0; | |
9202 | ||
389d00a5 JB |
9203 | /* No opcodes outside of base encoding space. */ |
9204 | if (i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
e379e5f3 L |
9205 | return 0; |
9206 | ||
79d72f45 HL |
9207 | /* add, sub without add/sub m, imm. */ |
9208 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
9209 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
9210 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 9211 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 9212 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
9213 | { |
9214 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9215 | return !(i.mem_operands && i.imm_operands); | |
9216 | } | |
e379e5f3 | 9217 | |
79d72f45 HL |
9218 | /* and without and m, imm. */ |
9219 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
9220 | || ((i.tm.base_opcode | 3) == 0x83 | |
9221 | && i.tm.extension_opcode == 0x4)) | |
9222 | { | |
9223 | *mf_cmp_p = mf_cmp_test_and; | |
9224 | return !(i.mem_operands && i.imm_operands); | |
9225 | } | |
9226 | ||
9227 | /* test without test m imm. */ | |
e379e5f3 L |
9228 | if ((i.tm.base_opcode | 1) == 0x85 |
9229 | || (i.tm.base_opcode | 1) == 0xa9 | |
9230 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
9231 | && i.tm.extension_opcode == 0)) |
9232 | { | |
9233 | *mf_cmp_p = mf_cmp_test_and; | |
9234 | return !(i.mem_operands && i.imm_operands); | |
9235 | } | |
9236 | ||
9237 | /* cmp without cmp m, imm. */ | |
9238 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
9239 | || ((i.tm.base_opcode | 3) == 0x83 |
9240 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
9241 | { |
9242 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9243 | return !(i.mem_operands && i.imm_operands); | |
9244 | } | |
e379e5f3 | 9245 | |
79d72f45 | 9246 | /* inc, dec without inc/dec m. */ |
e379e5f3 L |
9247 | if ((i.tm.cpu_flags.bitfield.cpuno64 |
9248 | && (i.tm.base_opcode | 0xf) == 0x4f) | |
9249 | || ((i.tm.base_opcode | 1) == 0xff | |
9250 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
9251 | { |
9252 | *mf_cmp_p = mf_cmp_incdec; | |
9253 | return !i.mem_operands; | |
9254 | } | |
e379e5f3 L |
9255 | |
9256 | return 0; | |
9257 | } | |
9258 | ||
9259 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
9260 | ||
9261 | static int | |
79d72f45 | 9262 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9263 | { |
9264 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9265 | if (!align_branch_power | |
9266 | || now_seg == absolute_section | |
9267 | || !cpu_arch_flags.bitfield.cpui386 | |
9268 | || !(align_branch & align_branch_fused_bit)) | |
9269 | return 0; | |
9270 | ||
79d72f45 | 9271 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
9272 | { |
9273 | if (last_insn.kind == last_insn_other | |
9274 | || last_insn.seg != now_seg) | |
9275 | return 1; | |
9276 | if (flag_debug) | |
9277 | as_warn_where (last_insn.file, last_insn.line, | |
9278 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9279 | last_insn.name, i.tm.name); | |
9280 | } | |
9281 | ||
9282 | return 0; | |
9283 | } | |
9284 | ||
9285 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
9286 | ||
9287 | static int | |
9288 | add_branch_prefix_frag_p (void) | |
9289 | { | |
9290 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
9291 | to PadLock instructions since they include prefixes in opcode. */ | |
9292 | if (!align_branch_power | |
9293 | || !align_branch_prefix_size | |
9294 | || now_seg == absolute_section | |
9295 | || i.tm.cpu_flags.bitfield.cpupadlock | |
9296 | || !cpu_arch_flags.bitfield.cpui386) | |
9297 | return 0; | |
9298 | ||
9299 | /* Don't add prefix if it is a prefix or there is no operand in case | |
9300 | that segment prefix is special. */ | |
9301 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
9302 | return 0; | |
9303 | ||
9304 | if (last_insn.kind == last_insn_other | |
9305 | || last_insn.seg != now_seg) | |
9306 | return 1; | |
9307 | ||
9308 | if (flag_debug) | |
9309 | as_warn_where (last_insn.file, last_insn.line, | |
9310 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9311 | last_insn.name, i.tm.name); | |
9312 | ||
9313 | return 0; | |
9314 | } | |
9315 | ||
9316 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
9317 | ||
9318 | static int | |
79d72f45 HL |
9319 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
9320 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
9321 | { |
9322 | int add_padding; | |
9323 | ||
9324 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9325 | if (!align_branch_power | |
9326 | || now_seg == absolute_section | |
389d00a5 JB |
9327 | || !cpu_arch_flags.bitfield.cpui386 |
9328 | || i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
e379e5f3 L |
9329 | return 0; |
9330 | ||
9331 | add_padding = 0; | |
9332 | ||
9333 | /* Check for jcc and direct jmp. */ | |
9334 | if (i.tm.opcode_modifier.jump == JUMP) | |
9335 | { | |
9336 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
9337 | { | |
9338 | *branch_p = align_branch_jmp; | |
9339 | add_padding = align_branch & align_branch_jmp_bit; | |
9340 | } | |
9341 | else | |
9342 | { | |
79d72f45 HL |
9343 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
9344 | igore the lowest bit. */ | |
9345 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
9346 | *branch_p = align_branch_jcc; |
9347 | if ((align_branch & align_branch_jcc_bit)) | |
9348 | add_padding = 1; | |
9349 | } | |
9350 | } | |
e379e5f3 L |
9351 | else if ((i.tm.base_opcode | 1) == 0xc3) |
9352 | { | |
9353 | /* Near ret. */ | |
9354 | *branch_p = align_branch_ret; | |
9355 | if ((align_branch & align_branch_ret_bit)) | |
9356 | add_padding = 1; | |
9357 | } | |
9358 | else | |
9359 | { | |
9360 | /* Check for indirect jmp, direct and indirect calls. */ | |
9361 | if (i.tm.base_opcode == 0xe8) | |
9362 | { | |
9363 | /* Direct call. */ | |
9364 | *branch_p = align_branch_call; | |
9365 | if ((align_branch & align_branch_call_bit)) | |
9366 | add_padding = 1; | |
9367 | } | |
9368 | else if (i.tm.base_opcode == 0xff | |
9369 | && (i.tm.extension_opcode == 2 | |
9370 | || i.tm.extension_opcode == 4)) | |
9371 | { | |
9372 | /* Indirect call and jmp. */ | |
9373 | *branch_p = align_branch_indirect; | |
9374 | if ((align_branch & align_branch_indirect_bit)) | |
9375 | add_padding = 1; | |
9376 | } | |
9377 | ||
9378 | if (add_padding | |
9379 | && i.disp_operands | |
9380 | && tls_get_addr | |
9381 | && (i.op[0].disps->X_op == O_symbol | |
9382 | || (i.op[0].disps->X_op == O_subtract | |
9383 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
9384 | { | |
9385 | symbolS *s = i.op[0].disps->X_add_symbol; | |
9386 | /* No padding to call to global or undefined tls_get_addr. */ | |
9387 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
9388 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
9389 | return 0; | |
9390 | } | |
9391 | } | |
9392 | ||
9393 | if (add_padding | |
9394 | && last_insn.kind != last_insn_other | |
9395 | && last_insn.seg == now_seg) | |
9396 | { | |
9397 | if (flag_debug) | |
9398 | as_warn_where (last_insn.file, last_insn.line, | |
9399 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
9400 | last_insn.name, i.tm.name); | |
9401 | return 0; | |
9402 | } | |
9403 | ||
9404 | return add_padding; | |
9405 | } | |
9406 | ||
29b0f896 | 9407 | static void |
e3bb37b5 | 9408 | output_insn (void) |
29b0f896 | 9409 | { |
2bbd9c25 JJ |
9410 | fragS *insn_start_frag; |
9411 | offsetT insn_start_off; | |
e379e5f3 L |
9412 | fragS *fragP = NULL; |
9413 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
9414 | /* The initializer is arbitrary just to avoid uninitialized error. |
9415 | it's actually either assigned in add_branch_padding_frag_p | |
9416 | or never be used. */ | |
9417 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 9418 | |
b4a3a7b4 | 9419 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 9420 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 9421 | { |
32930e4e L |
9422 | if ((i.xstate & xstate_tmm) == xstate_tmm |
9423 | || i.tm.cpu_flags.bitfield.cpuamx_tile) | |
9424 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; | |
9425 | ||
b4a3a7b4 L |
9426 | if (i.tm.cpu_flags.bitfield.cpu8087 |
9427 | || i.tm.cpu_flags.bitfield.cpu287 | |
9428 | || i.tm.cpu_flags.bitfield.cpu387 | |
9429 | || i.tm.cpu_flags.bitfield.cpu687 | |
9430 | || i.tm.cpu_flags.bitfield.cpufisttp) | |
9431 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; | |
014d61ea | 9432 | |
921eafea | 9433 | if ((i.xstate & xstate_mmx) |
389d00a5 JB |
9434 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
9435 | && !is_any_vex_encoding (&i.tm) | |
9436 | && (i.tm.base_opcode == 0x77 /* emms */ | |
9437 | || i.tm.base_opcode == 0x0e /* femms */))) | |
b4a3a7b4 | 9438 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 9439 | |
32930e4e L |
9440 | if (i.index_reg) |
9441 | { | |
9442 | if (i.index_reg->reg_type.bitfield.zmmword) | |
9443 | i.xstate |= xstate_zmm; | |
9444 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
9445 | i.xstate |= xstate_ymm; | |
9446 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
9447 | i.xstate |= xstate_xmm; | |
9448 | } | |
014d61ea JB |
9449 | |
9450 | /* vzeroall / vzeroupper */ | |
9451 | if (i.tm.base_opcode == 0x77 && i.tm.cpu_flags.bitfield.cpuavx) | |
9452 | i.xstate |= xstate_ymm; | |
9453 | ||
c4694f17 | 9454 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
9455 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
9456 | || (i.tm.base_opcode == 0xae | |
9457 | && (i.tm.cpu_flags.bitfield.cpusse | |
9458 | || i.tm.cpu_flags.bitfield.cpuavx)) | |
c4694f17 TG |
9459 | || i.tm.cpu_flags.bitfield.cpuwidekl |
9460 | || i.tm.cpu_flags.bitfield.cpukl) | |
b4a3a7b4 | 9461 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 9462 | |
921eafea | 9463 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 9464 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 9465 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 9466 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 9467 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 9468 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
b4a3a7b4 L |
9469 | if (i.tm.cpu_flags.bitfield.cpufxsr) |
9470 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; | |
9471 | if (i.tm.cpu_flags.bitfield.cpuxsave) | |
9472 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; | |
9473 | if (i.tm.cpu_flags.bitfield.cpuxsaveopt) | |
9474 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; | |
9475 | if (i.tm.cpu_flags.bitfield.cpuxsavec) | |
9476 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; | |
b0ab0693 L |
9477 | |
9478 | if (x86_feature_2_used | |
9479 | || i.tm.cpu_flags.bitfield.cpucmov | |
9480 | || i.tm.cpu_flags.bitfield.cpusyscall | |
389d00a5 JB |
9481 | || (i.tm.opcode_modifier.opcodespace == SPACE_0F |
9482 | && i.tm.base_opcode == 0xc7 | |
70e95837 | 9483 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE |
b0ab0693 L |
9484 | && i.tm.extension_opcode == 1) /* cmpxchg8b */) |
9485 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; | |
9486 | if (i.tm.cpu_flags.bitfield.cpusse3 | |
9487 | || i.tm.cpu_flags.bitfield.cpussse3 | |
9488 | || i.tm.cpu_flags.bitfield.cpusse4_1 | |
9489 | || i.tm.cpu_flags.bitfield.cpusse4_2 | |
9490 | || i.tm.cpu_flags.bitfield.cpucx16 | |
9491 | || i.tm.cpu_flags.bitfield.cpupopcnt | |
9492 | /* LAHF-SAHF insns in 64-bit mode. */ | |
9493 | || (flag_code == CODE_64BIT | |
35648716 JB |
9494 | && (i.tm.base_opcode | 1) == 0x9f |
9495 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE)) | |
b0ab0693 L |
9496 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
9497 | if (i.tm.cpu_flags.bitfield.cpuavx | |
9498 | || i.tm.cpu_flags.bitfield.cpuavx2 | |
9499 | /* Any VEX encoded insns execpt for CpuAVX512F, CpuAVX512BW, | |
9500 | CpuAVX512DQ, LPW, TBM and AMX. */ | |
9501 | || (i.tm.opcode_modifier.vex | |
9502 | && !i.tm.cpu_flags.bitfield.cpuavx512f | |
9503 | && !i.tm.cpu_flags.bitfield.cpuavx512bw | |
9504 | && !i.tm.cpu_flags.bitfield.cpuavx512dq | |
9505 | && !i.tm.cpu_flags.bitfield.cpulwp | |
9506 | && !i.tm.cpu_flags.bitfield.cputbm | |
9507 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) | |
9508 | || i.tm.cpu_flags.bitfield.cpuf16c | |
9509 | || i.tm.cpu_flags.bitfield.cpufma | |
9510 | || i.tm.cpu_flags.bitfield.cpulzcnt | |
9511 | || i.tm.cpu_flags.bitfield.cpumovbe | |
9512 | || i.tm.cpu_flags.bitfield.cpuxsaves | |
9513 | || (x86_feature_2_used | |
9514 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
9515 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
9516 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
9517 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
9518 | if (i.tm.cpu_flags.bitfield.cpuavx512f | |
9519 | || i.tm.cpu_flags.bitfield.cpuavx512bw | |
9520 | || i.tm.cpu_flags.bitfield.cpuavx512dq | |
9521 | || i.tm.cpu_flags.bitfield.cpuavx512vl | |
9522 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF and | |
9523 | VNNIW. */ | |
9524 | || (i.tm.opcode_modifier.evex | |
9525 | && !i.tm.cpu_flags.bitfield.cpuavx512er | |
9526 | && !i.tm.cpu_flags.bitfield.cpuavx512pf | |
9527 | && !i.tm.cpu_flags.bitfield.cpuavx512_4vnniw)) | |
9528 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; | |
b4a3a7b4 L |
9529 | } |
9530 | #endif | |
9531 | ||
29b0f896 AM |
9532 | /* Tie dwarf2 debug info to the address at the start of the insn. |
9533 | We can't do this after the insn has been output as the current | |
9534 | frag may have been closed off. eg. by frag_var. */ | |
9535 | dwarf2_emit_insn (0); | |
9536 | ||
2bbd9c25 JJ |
9537 | insn_start_frag = frag_now; |
9538 | insn_start_off = frag_now_fix (); | |
9539 | ||
79d72f45 | 9540 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
9541 | { |
9542 | char *p; | |
9543 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
9544 | unsigned int max_branch_padding_size = 14; | |
9545 | ||
9546 | /* Align section to boundary. */ | |
9547 | record_alignment (now_seg, align_branch_power); | |
9548 | ||
9549 | /* Make room for padding. */ | |
9550 | frag_grow (max_branch_padding_size); | |
9551 | ||
9552 | /* Start of the padding. */ | |
9553 | p = frag_more (0); | |
9554 | ||
9555 | fragP = frag_now; | |
9556 | ||
9557 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
9558 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
9559 | NULL, 0, p); | |
9560 | ||
79d72f45 | 9561 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
9562 | fragP->tc_frag_data.branch_type = branch; |
9563 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
9564 | } | |
9565 | ||
29b0f896 | 9566 | /* Output jumps. */ |
0cfa3eb3 | 9567 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 9568 | output_branch (); |
0cfa3eb3 JB |
9569 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9570 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 9571 | output_jump (); |
0cfa3eb3 | 9572 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
9573 | output_interseg_jump (); |
9574 | else | |
9575 | { | |
9576 | /* Output normal instructions here. */ | |
9577 | char *p; | |
9578 | unsigned char *q; | |
47465058 | 9579 | unsigned int j; |
79d72f45 | 9580 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 9581 | |
e4e00185 | 9582 | if (avoid_fence |
389d00a5 JB |
9583 | && (i.tm.base_opcode == 0xaee8 |
9584 | || i.tm.base_opcode == 0xaef0 | |
9585 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
9586 | { |
9587 | /* Encode lfence, mfence, and sfence as | |
9588 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
9589 | if (now_seg != absolute_section) | |
9590 | { | |
9591 | offsetT val = 0x240483f0ULL; | |
9592 | ||
9593 | p = frag_more (5); | |
9594 | md_number_to_chars (p, val, 5); | |
9595 | } | |
9596 | else | |
9597 | abs_section_offset += 5; | |
9598 | return; | |
9599 | } | |
e4e00185 | 9600 | |
d022bddd IT |
9601 | /* Some processors fail on LOCK prefix. This options makes |
9602 | assembler ignore LOCK prefix and serves as a workaround. */ | |
9603 | if (omit_lock_prefix) | |
9604 | { | |
35648716 JB |
9605 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
9606 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
9607 | return; |
9608 | i.prefix[LOCK_PREFIX] = 0; | |
9609 | } | |
9610 | ||
e379e5f3 L |
9611 | if (branch) |
9612 | /* Skip if this is a branch. */ | |
9613 | ; | |
79d72f45 | 9614 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
9615 | { |
9616 | /* Make room for padding. */ | |
9617 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
9618 | p = frag_more (0); | |
9619 | ||
9620 | fragP = frag_now; | |
9621 | ||
9622 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
9623 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
9624 | NULL, 0, p); | |
9625 | ||
79d72f45 | 9626 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
9627 | fragP->tc_frag_data.branch_type = align_branch_fused; |
9628 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
9629 | } | |
9630 | else if (add_branch_prefix_frag_p ()) | |
9631 | { | |
9632 | unsigned int max_prefix_size = align_branch_prefix_size; | |
9633 | ||
9634 | /* Make room for padding. */ | |
9635 | frag_grow (max_prefix_size); | |
9636 | p = frag_more (0); | |
9637 | ||
9638 | fragP = frag_now; | |
9639 | ||
9640 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
9641 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
9642 | NULL, 0, p); | |
9643 | ||
9644 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
9645 | } | |
9646 | ||
43234a1e L |
9647 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
9648 | don't need the explicit prefix. */ | |
9649 | if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex) | |
bc4bd9ab | 9650 | { |
7b47a312 | 9651 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 9652 | { |
7b47a312 L |
9653 | case PREFIX_0X66: |
9654 | add_prefix (0x66); | |
9655 | break; | |
9656 | case PREFIX_0XF2: | |
9657 | add_prefix (0xf2); | |
9658 | break; | |
9659 | case PREFIX_0XF3: | |
8b65b895 L |
9660 | if (!i.tm.cpu_flags.bitfield.cpupadlock |
9661 | || (i.prefix[REP_PREFIX] != 0xf3)) | |
9662 | add_prefix (0xf3); | |
c0f3af97 | 9663 | break; |
7b47a312 | 9664 | case PREFIX_NONE: |
9a182d04 | 9665 | switch (i.opcode_length) |
c0f3af97 | 9666 | { |
7b47a312 | 9667 | case 2: |
7b47a312 | 9668 | break; |
9a182d04 | 9669 | case 1: |
7b47a312 | 9670 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
9671 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
9672 | break; | |
7b47a312 L |
9673 | as_bad_where (insn_start_frag->fr_file, |
9674 | insn_start_frag->fr_line, | |
9675 | _("pseudo prefix without instruction")); | |
9676 | return; | |
9677 | default: | |
9678 | abort (); | |
4dffcebc | 9679 | } |
c0f3af97 | 9680 | break; |
c0f3af97 L |
9681 | default: |
9682 | abort (); | |
bc4bd9ab | 9683 | } |
c0f3af97 | 9684 | |
6d19a37a | 9685 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
9686 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
9687 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
9688 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
9689 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
9690 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
9691 | if (x86_elf_abi == X86_64_X32_ABI |
9692 | && i.operands == 2 | |
14470f07 L |
9693 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
9694 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
9695 | && i.prefix[REX_PREFIX] == 0) |
9696 | add_prefix (REX_OPCODE); | |
6d19a37a | 9697 | #endif |
cf61b747 | 9698 | |
c0f3af97 L |
9699 | /* The prefix bytes. */ |
9700 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
9701 | if (*q) | |
48ef937e | 9702 | frag_opcode_byte (*q); |
0f10071e | 9703 | } |
ae5c1c7b | 9704 | else |
c0f3af97 L |
9705 | { |
9706 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
9707 | if (*q) | |
9708 | switch (j) | |
9709 | { | |
c0f3af97 L |
9710 | case SEG_PREFIX: |
9711 | case ADDR_PREFIX: | |
48ef937e | 9712 | frag_opcode_byte (*q); |
c0f3af97 L |
9713 | break; |
9714 | default: | |
9715 | /* There should be no other prefixes for instructions | |
9716 | with VEX prefix. */ | |
9717 | abort (); | |
9718 | } | |
9719 | ||
43234a1e L |
9720 | /* For EVEX instructions i.vrex should become 0 after |
9721 | build_evex_prefix. For VEX instructions upper 16 registers | |
9722 | aren't available, so VREX should be 0. */ | |
9723 | if (i.vrex) | |
9724 | abort (); | |
c0f3af97 | 9725 | /* Now the VEX prefix. */ |
48ef937e JB |
9726 | if (now_seg != absolute_section) |
9727 | { | |
9728 | p = frag_more (i.vex.length); | |
9729 | for (j = 0; j < i.vex.length; j++) | |
9730 | p[j] = i.vex.bytes[j]; | |
9731 | } | |
9732 | else | |
9733 | abs_section_offset += i.vex.length; | |
c0f3af97 | 9734 | } |
252b5132 | 9735 | |
29b0f896 | 9736 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
9737 | j = i.opcode_length; |
9738 | if (!i.vex.length) | |
9739 | switch (i.tm.opcode_modifier.opcodespace) | |
9740 | { | |
9741 | case SPACE_BASE: | |
9742 | break; | |
9743 | case SPACE_0F: | |
9744 | ++j; | |
9745 | break; | |
9746 | case SPACE_0F38: | |
9747 | case SPACE_0F3A: | |
9748 | j += 2; | |
9749 | break; | |
9750 | default: | |
9751 | abort (); | |
9752 | } | |
9753 | ||
48ef937e | 9754 | if (now_seg == absolute_section) |
389d00a5 JB |
9755 | abs_section_offset += j; |
9756 | else if (j == 1) | |
29b0f896 AM |
9757 | { |
9758 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
9759 | } | |
9760 | else | |
9761 | { | |
389d00a5 JB |
9762 | p = frag_more (j); |
9763 | if (!i.vex.length | |
9764 | && i.tm.opcode_modifier.opcodespace != SPACE_BASE) | |
9765 | { | |
9766 | *p++ = 0x0f; | |
9767 | if (i.tm.opcode_modifier.opcodespace != SPACE_0F) | |
9768 | *p++ = i.tm.opcode_modifier.opcodespace == SPACE_0F38 | |
9769 | ? 0x38 : 0x3a; | |
9770 | } | |
9771 | ||
9a182d04 | 9772 | switch (i.opcode_length) |
331d2d0d | 9773 | { |
4dffcebc | 9774 | case 2: |
389d00a5 JB |
9775 | /* Put out high byte first: can't use md_number_to_chars! */ |
9776 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
9777 | /* Fall through. */ | |
9778 | case 1: | |
9779 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
9780 | break; |
9781 | default: | |
9782 | abort (); | |
9783 | break; | |
331d2d0d | 9784 | } |
0f10071e | 9785 | |
29b0f896 | 9786 | } |
3e73aa7c | 9787 | |
29b0f896 | 9788 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 9789 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 9790 | { |
48ef937e JB |
9791 | frag_opcode_byte ((i.rm.regmem << 0) |
9792 | | (i.rm.reg << 3) | |
9793 | | (i.rm.mode << 6)); | |
29b0f896 AM |
9794 | /* If i.rm.regmem == ESP (4) |
9795 | && i.rm.mode != (Register mode) | |
9796 | && not 16 bit | |
9797 | ==> need second modrm byte. */ | |
9798 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
9799 | && i.rm.mode != 3 | |
dc821c5f | 9800 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
9801 | frag_opcode_byte ((i.sib.base << 0) |
9802 | | (i.sib.index << 3) | |
9803 | | (i.sib.scale << 6)); | |
29b0f896 | 9804 | } |
3e73aa7c | 9805 | |
29b0f896 | 9806 | if (i.disp_operands) |
2bbd9c25 | 9807 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 9808 | |
29b0f896 | 9809 | if (i.imm_operands) |
2bbd9c25 | 9810 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
9811 | |
9812 | /* | |
9813 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
9814 | * absolute section, and abs_section_offset not getting updated as data | |
9815 | * gets added to the frag breaks the logic below. | |
9816 | */ | |
9817 | if (now_seg != absolute_section) | |
9818 | { | |
9819 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
9820 | if (j > 15) | |
9821 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
9822 | j); | |
e379e5f3 L |
9823 | else if (fragP) |
9824 | { | |
9825 | /* NB: Don't add prefix with GOTPC relocation since | |
9826 | output_disp() above depends on the fixed encoding | |
9827 | length. Can't add prefix with TLS relocation since | |
9828 | it breaks TLS linker optimization. */ | |
9829 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
9830 | /* Prefix count on the current instruction. */ | |
9831 | unsigned int count = i.vex.length; | |
9832 | unsigned int k; | |
9833 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
9834 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
9835 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
9836 | count++; | |
9837 | ||
9838 | /* Count prefixes for extended opcode maps. */ | |
9839 | if (!i.vex.length) | |
389d00a5 | 9840 | switch (i.tm.opcode_modifier.opcodespace) |
e379e5f3 | 9841 | { |
389d00a5 | 9842 | case SPACE_BASE: |
e379e5f3 | 9843 | break; |
389d00a5 JB |
9844 | case SPACE_0F: |
9845 | count++; | |
e379e5f3 | 9846 | break; |
389d00a5 JB |
9847 | case SPACE_0F38: |
9848 | case SPACE_0F3A: | |
9849 | count += 2; | |
e379e5f3 L |
9850 | break; |
9851 | default: | |
9852 | abort (); | |
9853 | } | |
9854 | ||
9855 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
9856 | == BRANCH_PREFIX) | |
9857 | { | |
9858 | /* Set the maximum prefix size in BRANCH_PREFIX | |
9859 | frag. */ | |
9860 | if (fragP->tc_frag_data.max_bytes > max) | |
9861 | fragP->tc_frag_data.max_bytes = max; | |
9862 | if (fragP->tc_frag_data.max_bytes > count) | |
9863 | fragP->tc_frag_data.max_bytes -= count; | |
9864 | else | |
9865 | fragP->tc_frag_data.max_bytes = 0; | |
9866 | } | |
9867 | else | |
9868 | { | |
9869 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
9870 | frag. */ | |
9871 | unsigned int max_prefix_size; | |
9872 | if (align_branch_prefix_size > max) | |
9873 | max_prefix_size = max; | |
9874 | else | |
9875 | max_prefix_size = align_branch_prefix_size; | |
9876 | if (max_prefix_size > count) | |
9877 | fragP->tc_frag_data.max_prefix_length | |
9878 | = max_prefix_size - count; | |
9879 | } | |
9880 | ||
9881 | /* Use existing segment prefix if possible. Use CS | |
9882 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
9883 | segment prefix with ESP/EBP base register and use DS | |
9884 | segment prefix without ESP/EBP base register. */ | |
9885 | if (i.prefix[SEG_PREFIX]) | |
9886 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
9887 | else if (flag_code == CODE_64BIT) | |
9888 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
9889 | else if (i.base_reg | |
9890 | && (i.base_reg->reg_num == 4 | |
9891 | || i.base_reg->reg_num == 5)) | |
9892 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
9893 | else | |
9894 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
9895 | } | |
9c33702b | 9896 | } |
29b0f896 | 9897 | } |
252b5132 | 9898 | |
e379e5f3 L |
9899 | /* NB: Don't work with COND_JUMP86 without i386. */ |
9900 | if (align_branch_power | |
9901 | && now_seg != absolute_section | |
9902 | && cpu_arch_flags.bitfield.cpui386) | |
9903 | { | |
9904 | /* Terminate each frag so that we can add prefix and check for | |
9905 | fused jcc. */ | |
9906 | frag_wane (frag_now); | |
9907 | frag_new (0); | |
9908 | } | |
9909 | ||
29b0f896 AM |
9910 | #ifdef DEBUG386 |
9911 | if (flag_debug) | |
9912 | { | |
7b81dfbb | 9913 | pi ("" /*line*/, &i); |
29b0f896 AM |
9914 | } |
9915 | #endif /* DEBUG386 */ | |
9916 | } | |
252b5132 | 9917 | |
e205caa7 L |
9918 | /* Return the size of the displacement operand N. */ |
9919 | ||
9920 | static int | |
9921 | disp_size (unsigned int n) | |
9922 | { | |
9923 | int size = 4; | |
43234a1e | 9924 | |
b5014f7a | 9925 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
9926 | size = 8; |
9927 | else if (i.types[n].bitfield.disp8) | |
9928 | size = 1; | |
9929 | else if (i.types[n].bitfield.disp16) | |
9930 | size = 2; | |
e205caa7 L |
9931 | return size; |
9932 | } | |
9933 | ||
9934 | /* Return the size of the immediate operand N. */ | |
9935 | ||
9936 | static int | |
9937 | imm_size (unsigned int n) | |
9938 | { | |
9939 | int size = 4; | |
40fb9820 L |
9940 | if (i.types[n].bitfield.imm64) |
9941 | size = 8; | |
9942 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
9943 | size = 1; | |
9944 | else if (i.types[n].bitfield.imm16) | |
9945 | size = 2; | |
e205caa7 L |
9946 | return size; |
9947 | } | |
9948 | ||
29b0f896 | 9949 | static void |
64e74474 | 9950 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
9951 | { |
9952 | char *p; | |
9953 | unsigned int n; | |
252b5132 | 9954 | |
29b0f896 AM |
9955 | for (n = 0; n < i.operands; n++) |
9956 | { | |
b5014f7a | 9957 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 9958 | { |
48ef937e JB |
9959 | int size = disp_size (n); |
9960 | ||
9961 | if (now_seg == absolute_section) | |
9962 | abs_section_offset += size; | |
9963 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 9964 | { |
43234a1e | 9965 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 9966 | |
629cfaf1 JB |
9967 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
9968 | size); | |
29b0f896 AM |
9969 | p = frag_more (size); |
9970 | md_number_to_chars (p, val, size); | |
9971 | } | |
9972 | else | |
9973 | { | |
f86103b7 | 9974 | enum bfd_reloc_code_real reloc_type; |
40fb9820 | 9975 | int sign = i.types[n].bitfield.disp32s; |
29b0f896 | 9976 | int pcrel = (i.flags[n] & Operand_PCrel) != 0; |
02a86693 | 9977 | fixS *fixP; |
29b0f896 | 9978 | |
e205caa7 | 9979 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 9980 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 9981 | |
29b0f896 AM |
9982 | /* The PC relative address is computed relative |
9983 | to the instruction boundary, so in case immediate | |
9984 | fields follows, we need to adjust the value. */ | |
9985 | if (pcrel && i.imm_operands) | |
9986 | { | |
29b0f896 | 9987 | unsigned int n1; |
e205caa7 | 9988 | int sz = 0; |
252b5132 | 9989 | |
29b0f896 | 9990 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 9991 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 9992 | { |
e205caa7 L |
9993 | /* Only one immediate is allowed for PC |
9994 | relative address. */ | |
9c2799c2 | 9995 | gas_assert (sz == 0); |
e205caa7 L |
9996 | sz = imm_size (n1); |
9997 | i.op[n].disps->X_add_number -= sz; | |
252b5132 | 9998 | } |
29b0f896 | 9999 | /* We should find the immediate. */ |
9c2799c2 | 10000 | gas_assert (sz != 0); |
29b0f896 | 10001 | } |
520dc8e8 | 10002 | |
29b0f896 | 10003 | p = frag_more (size); |
d258b828 | 10004 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 10005 | if (GOT_symbol |
2bbd9c25 | 10006 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 10007 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10008 | || reloc_type == BFD_RELOC_X86_64_32S |
10009 | || (reloc_type == BFD_RELOC_64 | |
10010 | && object_64bit)) | |
d6ab8113 JB |
10011 | && (i.op[n].disps->X_op == O_symbol |
10012 | || (i.op[n].disps->X_op == O_add | |
10013 | && ((symbol_get_value_expression | |
10014 | (i.op[n].disps->X_op_symbol)->X_op) | |
10015 | == O_subtract)))) | |
10016 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 10017 | { |
4fa24527 | 10018 | if (!object_64bit) |
7b81dfbb AJ |
10019 | { |
10020 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 10021 | i.has_gotpc_tls_reloc = true; |
98da05bf | 10022 | i.op[n].disps->X_add_number += |
d583596c | 10023 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
10024 | } |
10025 | else if (reloc_type == BFD_RELOC_64) | |
10026 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 10027 | else |
7b81dfbb AJ |
10028 | /* Don't do the adjustment for x86-64, as there |
10029 | the pcrel addressing is relative to the _next_ | |
10030 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 10031 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 10032 | } |
e379e5f3 L |
10033 | else if (align_branch_power) |
10034 | { | |
10035 | switch (reloc_type) | |
10036 | { | |
10037 | case BFD_RELOC_386_TLS_GD: | |
10038 | case BFD_RELOC_386_TLS_LDM: | |
10039 | case BFD_RELOC_386_TLS_IE: | |
10040 | case BFD_RELOC_386_TLS_IE_32: | |
10041 | case BFD_RELOC_386_TLS_GOTIE: | |
10042 | case BFD_RELOC_386_TLS_GOTDESC: | |
10043 | case BFD_RELOC_386_TLS_DESC_CALL: | |
10044 | case BFD_RELOC_X86_64_TLSGD: | |
10045 | case BFD_RELOC_X86_64_TLSLD: | |
10046 | case BFD_RELOC_X86_64_GOTTPOFF: | |
10047 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
10048 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
5b7c81bd | 10049 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
10050 | default: |
10051 | break; | |
10052 | } | |
10053 | } | |
02a86693 L |
10054 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
10055 | size, i.op[n].disps, pcrel, | |
10056 | reloc_type); | |
eb19308f JB |
10057 | |
10058 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
10059 | && !i.prefix[ADDR_PREFIX]) | |
10060 | fixP->fx_signed = 1; | |
10061 | ||
02a86693 L |
10062 | /* Check for "call/jmp *mem", "mov mem, %reg", |
10063 | "test %reg, mem" and "binop mem, %reg" where binop | |
10064 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
10065 | instructions without data prefix. Always generate |
10066 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
10067 | if (i.prefix[DATA_PREFIX] == 0 | |
10068 | && (generate_relax_relocations | |
10069 | || (!object_64bit | |
10070 | && i.rm.mode == 0 | |
10071 | && i.rm.regmem == 5)) | |
0cb4071e L |
10072 | && (i.rm.mode == 2 |
10073 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
389d00a5 | 10074 | && i.tm.opcode_modifier.opcodespace == SPACE_BASE |
02a86693 L |
10075 | && ((i.operands == 1 |
10076 | && i.tm.base_opcode == 0xff | |
10077 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
10078 | || (i.operands == 2 | |
10079 | && (i.tm.base_opcode == 0x8b | |
10080 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 10081 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
10082 | { |
10083 | if (object_64bit) | |
10084 | { | |
10085 | fixP->fx_tcbit = i.rex != 0; | |
10086 | if (i.base_reg | |
e968fc9b | 10087 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
10088 | fixP->fx_tcbit2 = 1; |
10089 | } | |
10090 | else | |
10091 | fixP->fx_tcbit2 = 1; | |
10092 | } | |
29b0f896 AM |
10093 | } |
10094 | } | |
10095 | } | |
10096 | } | |
252b5132 | 10097 | |
29b0f896 | 10098 | static void |
64e74474 | 10099 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10100 | { |
10101 | char *p; | |
10102 | unsigned int n; | |
252b5132 | 10103 | |
29b0f896 AM |
10104 | for (n = 0; n < i.operands; n++) |
10105 | { | |
43234a1e | 10106 | /* Skip SAE/RC Imm operand in EVEX. They are already handled. */ |
ca5312a2 | 10107 | if (i.rounding.type != rc_none && n == i.rounding.operand) |
43234a1e L |
10108 | continue; |
10109 | ||
40fb9820 | 10110 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 10111 | { |
48ef937e JB |
10112 | int size = imm_size (n); |
10113 | ||
10114 | if (now_seg == absolute_section) | |
10115 | abs_section_offset += size; | |
10116 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 10117 | { |
29b0f896 | 10118 | offsetT val; |
b4cac588 | 10119 | |
29b0f896 AM |
10120 | val = offset_in_range (i.op[n].imms->X_add_number, |
10121 | size); | |
10122 | p = frag_more (size); | |
10123 | md_number_to_chars (p, val, size); | |
10124 | } | |
10125 | else | |
10126 | { | |
10127 | /* Not absolute_section. | |
10128 | Need a 32-bit fixup (don't support 8bit | |
10129 | non-absolute imms). Try to support other | |
10130 | sizes ... */ | |
f86103b7 | 10131 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 10132 | int sign; |
29b0f896 | 10133 | |
40fb9820 | 10134 | if (i.types[n].bitfield.imm32s |
a7d61044 | 10135 | && (i.suffix == QWORD_MNEM_SUFFIX |
40fb9820 | 10136 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf))) |
29b0f896 | 10137 | sign = 1; |
e205caa7 L |
10138 | else |
10139 | sign = 0; | |
520dc8e8 | 10140 | |
29b0f896 | 10141 | p = frag_more (size); |
d258b828 | 10142 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 10143 | |
2bbd9c25 JJ |
10144 | /* This is tough to explain. We end up with this one if we |
10145 | * have operands that look like | |
10146 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
10147 | * obtain the absolute address of the GOT, and it is strongly | |
10148 | * preferable from a performance point of view to avoid using | |
10149 | * a runtime relocation for this. The actual sequence of | |
10150 | * instructions often look something like: | |
10151 | * | |
10152 | * call .L66 | |
10153 | * .L66: | |
10154 | * popl %ebx | |
10155 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
10156 | * | |
10157 | * The call and pop essentially return the absolute address | |
10158 | * of the label .L66 and store it in %ebx. The linker itself | |
10159 | * will ultimately change the first operand of the addl so | |
10160 | * that %ebx points to the GOT, but to keep things simple, the | |
10161 | * .o file must have this operand set so that it generates not | |
10162 | * the absolute address of .L66, but the absolute address of | |
10163 | * itself. This allows the linker itself simply treat a GOTPC | |
10164 | * relocation as asking for a pcrel offset to the GOT to be | |
10165 | * added in, and the addend of the relocation is stored in the | |
10166 | * operand field for the instruction itself. | |
10167 | * | |
10168 | * Our job here is to fix the operand so that it would add | |
10169 | * the correct offset so that %ebx would point to itself. The | |
10170 | * thing that is tricky is that .-.L66 will point to the | |
10171 | * beginning of the instruction, so we need to further modify | |
10172 | * the operand so that it will point to itself. There are | |
10173 | * other cases where you have something like: | |
10174 | * | |
10175 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
10176 | * | |
10177 | * and here no correction would be required. Internally in | |
10178 | * the assembler we treat operands of this form as not being | |
10179 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
10180 | * whether it would simplify matters to do it this way. Who | |
10181 | * knows. In earlier versions of the PIC patches, the | |
10182 | * pcrel_adjust field was used to store the correction, but | |
10183 | * since the expression is not pcrel, I felt it would be | |
10184 | * confusing to do it this way. */ | |
10185 | ||
d6ab8113 | 10186 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10187 | || reloc_type == BFD_RELOC_X86_64_32S |
10188 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
10189 | && GOT_symbol |
10190 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
10191 | && (i.op[n].imms->X_op == O_symbol | |
10192 | || (i.op[n].imms->X_op == O_add | |
10193 | && ((symbol_get_value_expression | |
10194 | (i.op[n].imms->X_op_symbol)->X_op) | |
10195 | == O_subtract)))) | |
10196 | { | |
4fa24527 | 10197 | if (!object_64bit) |
d6ab8113 | 10198 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 10199 | else if (size == 4) |
d6ab8113 | 10200 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
10201 | else if (size == 8) |
10202 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 10203 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
10204 | i.op[n].imms->X_add_number += |
10205 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 10206 | } |
29b0f896 AM |
10207 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
10208 | i.op[n].imms, 0, reloc_type); | |
10209 | } | |
10210 | } | |
10211 | } | |
252b5132 RH |
10212 | } |
10213 | \f | |
d182319b JB |
10214 | /* x86_cons_fix_new is called via the expression parsing code when a |
10215 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
10216 | static int cons_sign = -1; |
10217 | ||
10218 | void | |
e3bb37b5 | 10219 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 10220 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 10221 | { |
d258b828 | 10222 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
10223 | |
10224 | #ifdef TE_PE | |
10225 | if (exp->X_op == O_secrel) | |
10226 | { | |
10227 | exp->X_op = O_symbol; | |
10228 | r = BFD_RELOC_32_SECREL; | |
10229 | } | |
10230 | #endif | |
10231 | ||
10232 | fix_new_exp (frag, off, len, exp, 0, r); | |
10233 | } | |
10234 | ||
357d1bd8 L |
10235 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
10236 | purpose of the `.dc.a' internal pseudo-op. */ | |
10237 | ||
10238 | int | |
10239 | x86_address_bytes (void) | |
10240 | { | |
10241 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
10242 | return 4; | |
10243 | return stdoutput->arch_info->bits_per_address / 8; | |
10244 | } | |
10245 | ||
deea4973 JB |
10246 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
10247 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 10248 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 10249 | #else |
f3c180ae AM |
10250 | /* Parse operands of the form |
10251 | <symbol>@GOTOFF+<nnn> | |
10252 | and similar .plt or .got references. | |
10253 | ||
10254 | If we find one, set up the correct relocation in RELOC and copy the | |
10255 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
10256 | parsing by the calling routine. Return this buffer, and if ADJUST | |
10257 | is non-null set it to the length of the string we removed from the | |
10258 | input line. Otherwise return NULL. */ | |
10259 | static char * | |
91d6fa6a | 10260 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 10261 | int *adjust, |
d258b828 | 10262 | i386_operand_type *types) |
f3c180ae | 10263 | { |
7b81dfbb AJ |
10264 | /* Some of the relocations depend on the size of what field is to |
10265 | be relocated. But in our callers i386_immediate and i386_displacement | |
10266 | we don't yet know the operand size (this will be set by insn | |
10267 | matching). Hence we record the word32 relocation here, | |
10268 | and adjust the reloc according to the real size in reloc(). */ | |
f3c180ae AM |
10269 | static const struct { |
10270 | const char *str; | |
cff8d58a | 10271 | int len; |
4fa24527 | 10272 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 10273 | const i386_operand_type types64; |
5b7c81bd | 10274 | bool need_GOT_symbol; |
f3c180ae | 10275 | } gotrel[] = { |
deea4973 | 10276 | #ifndef TE_PE |
8ce3d284 | 10277 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10278 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
10279 | BFD_RELOC_SIZE32 }, | |
5b7c81bd | 10280 | OPERAND_TYPE_IMM32_64, false }, |
8ce3d284 | 10281 | #endif |
cff8d58a L |
10282 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
10283 | BFD_RELOC_X86_64_PLTOFF64 }, | |
5b7c81bd | 10284 | OPERAND_TYPE_IMM64, true }, |
cff8d58a L |
10285 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
10286 | BFD_RELOC_X86_64_PLT32 }, | |
5b7c81bd | 10287 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
10288 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
10289 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 10290 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10291 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
10292 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 10293 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10294 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
10295 | BFD_RELOC_X86_64_GOTPCREL }, | |
5b7c81bd | 10296 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10297 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
10298 | BFD_RELOC_X86_64_TLSGD }, | |
5b7c81bd | 10299 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10300 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
10301 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10302 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10303 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
10304 | BFD_RELOC_X86_64_TLSLD }, | |
5b7c81bd | 10305 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10306 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
10307 | BFD_RELOC_X86_64_GOTTPOFF }, | |
5b7c81bd | 10308 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10309 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
10310 | BFD_RELOC_X86_64_TPOFF32 }, | |
5b7c81bd | 10311 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10312 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
10313 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10314 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10315 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
10316 | BFD_RELOC_X86_64_DTPOFF32 }, | |
5b7c81bd | 10317 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10318 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
10319 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10320 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10321 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
10322 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10323 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10324 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
10325 | BFD_RELOC_X86_64_GOT32 }, | |
5b7c81bd | 10326 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
10327 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
10328 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
5b7c81bd | 10329 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10330 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
10331 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
5b7c81bd | 10332 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
10333 | #else /* TE_PE */ |
10334 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
10335 | BFD_RELOC_32_SECREL }, | |
10336 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, | |
10337 | #endif | |
f3c180ae AM |
10338 | }; |
10339 | char *cp; | |
10340 | unsigned int j; | |
10341 | ||
deea4973 | 10342 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
10343 | if (!IS_ELF) |
10344 | return NULL; | |
d382c579 | 10345 | #endif |
718ddfc0 | 10346 | |
f3c180ae | 10347 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 10348 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
10349 | return NULL; |
10350 | ||
47465058 | 10351 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 10352 | { |
cff8d58a | 10353 | int len = gotrel[j].len; |
28f81592 | 10354 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 10355 | { |
4fa24527 | 10356 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 10357 | { |
28f81592 AM |
10358 | int first, second; |
10359 | char *tmpbuf, *past_reloc; | |
f3c180ae | 10360 | |
91d6fa6a | 10361 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 10362 | |
3956db08 JB |
10363 | if (types) |
10364 | { | |
10365 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
10366 | { |
10367 | types->bitfield.imm32 = 1; | |
10368 | types->bitfield.disp32 = 1; | |
10369 | } | |
3956db08 JB |
10370 | else |
10371 | *types = gotrel[j].types64; | |
10372 | } | |
10373 | ||
844bf810 | 10374 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
10375 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
10376 | ||
28f81592 | 10377 | /* The length of the first part of our input line. */ |
f3c180ae | 10378 | first = cp - input_line_pointer; |
28f81592 AM |
10379 | |
10380 | /* The second part goes from after the reloc token until | |
67c11a9b | 10381 | (and including) an end_of_line char or comma. */ |
28f81592 | 10382 | past_reloc = cp + 1 + len; |
67c11a9b AM |
10383 | cp = past_reloc; |
10384 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10385 | ++cp; | |
10386 | second = cp + 1 - past_reloc; | |
28f81592 AM |
10387 | |
10388 | /* Allocate and copy string. The trailing NUL shouldn't | |
10389 | be necessary, but be safe. */ | |
add39d23 | 10390 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 10391 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
10392 | if (second != 0 && *past_reloc != ' ') |
10393 | /* Replace the relocation token with ' ', so that | |
10394 | errors like foo@GOTOFF1 will be detected. */ | |
10395 | tmpbuf[first++] = ' '; | |
af89796a L |
10396 | else |
10397 | /* Increment length by 1 if the relocation token is | |
10398 | removed. */ | |
10399 | len++; | |
10400 | if (adjust) | |
10401 | *adjust = len; | |
0787a12d AM |
10402 | memcpy (tmpbuf + first, past_reloc, second); |
10403 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
10404 | return tmpbuf; |
10405 | } | |
10406 | ||
4fa24527 JB |
10407 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
10408 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
10409 | return NULL; |
10410 | } | |
10411 | } | |
10412 | ||
10413 | /* Might be a symbol version string. Don't as_bad here. */ | |
10414 | return NULL; | |
10415 | } | |
4e4f7c87 | 10416 | #endif |
f3c180ae | 10417 | |
62ebcb5c | 10418 | bfd_reloc_code_real_type |
e3bb37b5 | 10419 | x86_cons (expressionS *exp, int size) |
f3c180ae | 10420 | { |
62ebcb5c AM |
10421 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
10422 | ||
ee86248c JB |
10423 | intel_syntax = -intel_syntax; |
10424 | ||
3c7b9c2c | 10425 | exp->X_md = 0; |
4fa24527 | 10426 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
10427 | { |
10428 | /* Handle @GOTOFF and the like in an expression. */ | |
10429 | char *save; | |
10430 | char *gotfree_input_line; | |
4a57f2cf | 10431 | int adjust = 0; |
f3c180ae AM |
10432 | |
10433 | save = input_line_pointer; | |
d258b828 | 10434 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
10435 | if (gotfree_input_line) |
10436 | input_line_pointer = gotfree_input_line; | |
10437 | ||
10438 | expression (exp); | |
10439 | ||
10440 | if (gotfree_input_line) | |
10441 | { | |
10442 | /* expression () has merrily parsed up to the end of line, | |
10443 | or a comma - in the wrong buffer. Transfer how far | |
10444 | input_line_pointer has moved to the right buffer. */ | |
10445 | input_line_pointer = (save | |
10446 | + (input_line_pointer - gotfree_input_line) | |
10447 | + adjust); | |
10448 | free (gotfree_input_line); | |
3992d3b7 AM |
10449 | if (exp->X_op == O_constant |
10450 | || exp->X_op == O_absent | |
10451 | || exp->X_op == O_illegal | |
0398aac5 | 10452 | || exp->X_op == O_register |
3992d3b7 AM |
10453 | || exp->X_op == O_big) |
10454 | { | |
10455 | char c = *input_line_pointer; | |
10456 | *input_line_pointer = 0; | |
10457 | as_bad (_("missing or invalid expression `%s'"), save); | |
10458 | *input_line_pointer = c; | |
10459 | } | |
b9519cfe L |
10460 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
10461 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
10462 | && exp->X_op != O_symbol) | |
10463 | { | |
10464 | char c = *input_line_pointer; | |
10465 | *input_line_pointer = 0; | |
10466 | as_bad (_("invalid PLT expression `%s'"), save); | |
10467 | *input_line_pointer = c; | |
10468 | } | |
f3c180ae AM |
10469 | } |
10470 | } | |
10471 | else | |
10472 | expression (exp); | |
ee86248c JB |
10473 | |
10474 | intel_syntax = -intel_syntax; | |
10475 | ||
10476 | if (intel_syntax) | |
10477 | i386_intel_simplify (exp); | |
62ebcb5c AM |
10478 | |
10479 | return got_reloc; | |
f3c180ae | 10480 | } |
f3c180ae | 10481 | |
9f32dd5b L |
10482 | static void |
10483 | signed_cons (int size) | |
6482c264 | 10484 | { |
d182319b JB |
10485 | if (flag_code == CODE_64BIT) |
10486 | cons_sign = 1; | |
10487 | cons (size); | |
10488 | cons_sign = -1; | |
6482c264 NC |
10489 | } |
10490 | ||
d182319b | 10491 | #ifdef TE_PE |
6482c264 | 10492 | static void |
7016a5d5 | 10493 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
10494 | { |
10495 | expressionS exp; | |
10496 | ||
10497 | do | |
10498 | { | |
10499 | expression (&exp); | |
10500 | if (exp.X_op == O_symbol) | |
10501 | exp.X_op = O_secrel; | |
10502 | ||
10503 | emit_expr (&exp, 4); | |
10504 | } | |
10505 | while (*input_line_pointer++ == ','); | |
10506 | ||
10507 | input_line_pointer--; | |
10508 | demand_empty_rest_of_line (); | |
10509 | } | |
6482c264 NC |
10510 | #endif |
10511 | ||
43234a1e L |
10512 | /* Handle Vector operations. */ |
10513 | ||
10514 | static char * | |
10515 | check_VecOperations (char *op_string, char *op_end) | |
10516 | { | |
10517 | const reg_entry *mask; | |
10518 | const char *saved; | |
10519 | char *end_op; | |
10520 | ||
10521 | while (*op_string | |
10522 | && (op_end == NULL || op_string < op_end)) | |
10523 | { | |
10524 | saved = op_string; | |
10525 | if (*op_string == '{') | |
10526 | { | |
10527 | op_string++; | |
10528 | ||
10529 | /* Check broadcasts. */ | |
d34049e8 | 10530 | if (startswith (op_string, "1to")) |
43234a1e | 10531 | { |
5273a3cd | 10532 | unsigned int bcst_type; |
43234a1e | 10533 | |
5273a3cd | 10534 | if (i.broadcast.type) |
43234a1e L |
10535 | goto duplicated_vec_op; |
10536 | ||
10537 | op_string += 3; | |
10538 | if (*op_string == '8') | |
8e6e0792 | 10539 | bcst_type = 8; |
b28d1bda | 10540 | else if (*op_string == '4') |
8e6e0792 | 10541 | bcst_type = 4; |
b28d1bda | 10542 | else if (*op_string == '2') |
8e6e0792 | 10543 | bcst_type = 2; |
43234a1e L |
10544 | else if (*op_string == '1' |
10545 | && *(op_string+1) == '6') | |
10546 | { | |
8e6e0792 | 10547 | bcst_type = 16; |
43234a1e L |
10548 | op_string++; |
10549 | } | |
10550 | else | |
10551 | { | |
10552 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
10553 | return NULL; | |
10554 | } | |
10555 | op_string++; | |
10556 | ||
5273a3cd JB |
10557 | i.broadcast.type = bcst_type; |
10558 | i.broadcast.operand = this_operand; | |
43234a1e L |
10559 | } |
10560 | /* Check masking operation. */ | |
10561 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
10562 | { | |
8a6fb3f9 JB |
10563 | if (mask == &bad_reg) |
10564 | return NULL; | |
10565 | ||
43234a1e | 10566 | /* k0 can't be used for write mask. */ |
f74a6307 | 10567 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 10568 | { |
6d2cd6b2 JB |
10569 | as_bad (_("`%s%s' can't be used for write mask"), |
10570 | register_prefix, mask->reg_name); | |
43234a1e L |
10571 | return NULL; |
10572 | } | |
10573 | ||
6225c532 | 10574 | if (!i.mask.reg) |
43234a1e | 10575 | { |
6225c532 JB |
10576 | i.mask.reg = mask; |
10577 | i.mask.operand = this_operand; | |
43234a1e | 10578 | } |
6225c532 JB |
10579 | else if (i.mask.reg->reg_num) |
10580 | goto duplicated_vec_op; | |
43234a1e L |
10581 | else |
10582 | { | |
6225c532 | 10583 | i.mask.reg = mask; |
43234a1e L |
10584 | |
10585 | /* Only "{z}" is allowed here. No need to check | |
10586 | zeroing mask explicitly. */ | |
6225c532 | 10587 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10588 | { |
10589 | as_bad (_("invalid write mask `%s'"), saved); | |
10590 | return NULL; | |
10591 | } | |
10592 | } | |
10593 | ||
10594 | op_string = end_op; | |
10595 | } | |
10596 | /* Check zeroing-flag for masking operation. */ | |
10597 | else if (*op_string == 'z') | |
10598 | { | |
6225c532 | 10599 | if (!i.mask.reg) |
43234a1e | 10600 | { |
6225c532 JB |
10601 | i.mask.reg = reg_k0; |
10602 | i.mask.zeroing = 1; | |
10603 | i.mask.operand = this_operand; | |
43234a1e L |
10604 | } |
10605 | else | |
10606 | { | |
6225c532 | 10607 | if (i.mask.zeroing) |
43234a1e L |
10608 | { |
10609 | duplicated_vec_op: | |
10610 | as_bad (_("duplicated `%s'"), saved); | |
10611 | return NULL; | |
10612 | } | |
10613 | ||
6225c532 | 10614 | i.mask.zeroing = 1; |
43234a1e L |
10615 | |
10616 | /* Only "{%k}" is allowed here. No need to check mask | |
10617 | register explicitly. */ | |
6225c532 | 10618 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
10619 | { |
10620 | as_bad (_("invalid zeroing-masking `%s'"), | |
10621 | saved); | |
10622 | return NULL; | |
10623 | } | |
10624 | } | |
10625 | ||
10626 | op_string++; | |
10627 | } | |
10628 | else | |
10629 | goto unknown_vec_op; | |
10630 | ||
10631 | if (*op_string != '}') | |
10632 | { | |
10633 | as_bad (_("missing `}' in `%s'"), saved); | |
10634 | return NULL; | |
10635 | } | |
10636 | op_string++; | |
0ba3a731 L |
10637 | |
10638 | /* Strip whitespace since the addition of pseudo prefixes | |
10639 | changed how the scrubber treats '{'. */ | |
10640 | if (is_space_char (*op_string)) | |
10641 | ++op_string; | |
10642 | ||
43234a1e L |
10643 | continue; |
10644 | } | |
10645 | unknown_vec_op: | |
10646 | /* We don't know this one. */ | |
10647 | as_bad (_("unknown vector operation: `%s'"), saved); | |
10648 | return NULL; | |
10649 | } | |
10650 | ||
6225c532 | 10651 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
10652 | { |
10653 | as_bad (_("zeroing-masking only allowed with write mask")); | |
10654 | return NULL; | |
10655 | } | |
10656 | ||
43234a1e L |
10657 | return op_string; |
10658 | } | |
10659 | ||
252b5132 | 10660 | static int |
70e41ade | 10661 | i386_immediate (char *imm_start) |
252b5132 RH |
10662 | { |
10663 | char *save_input_line_pointer; | |
f3c180ae | 10664 | char *gotfree_input_line; |
252b5132 | 10665 | segT exp_seg = 0; |
47926f60 | 10666 | expressionS *exp; |
40fb9820 L |
10667 | i386_operand_type types; |
10668 | ||
0dfbf9d7 | 10669 | operand_type_set (&types, ~0); |
252b5132 RH |
10670 | |
10671 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
10672 | { | |
31b2323c L |
10673 | as_bad (_("at most %d immediate operands are allowed"), |
10674 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
10675 | return 0; |
10676 | } | |
10677 | ||
10678 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 10679 | i.op[this_operand].imms = exp; |
252b5132 RH |
10680 | |
10681 | if (is_space_char (*imm_start)) | |
10682 | ++imm_start; | |
10683 | ||
10684 | save_input_line_pointer = input_line_pointer; | |
10685 | input_line_pointer = imm_start; | |
10686 | ||
d258b828 | 10687 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10688 | if (gotfree_input_line) |
10689 | input_line_pointer = gotfree_input_line; | |
252b5132 RH |
10690 | |
10691 | exp_seg = expression (exp); | |
10692 | ||
83183c0c | 10693 | SKIP_WHITESPACE (); |
43234a1e L |
10694 | |
10695 | /* Handle vector operations. */ | |
10696 | if (*input_line_pointer == '{') | |
10697 | { | |
10698 | input_line_pointer = check_VecOperations (input_line_pointer, | |
10699 | NULL); | |
10700 | if (input_line_pointer == NULL) | |
10701 | return 0; | |
10702 | } | |
10703 | ||
252b5132 | 10704 | if (*input_line_pointer) |
f3c180ae | 10705 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
10706 | |
10707 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 10708 | if (gotfree_input_line) |
ee86248c JB |
10709 | { |
10710 | free (gotfree_input_line); | |
10711 | ||
9aac24b1 | 10712 | if (exp->X_op == O_constant) |
ee86248c JB |
10713 | exp->X_op = O_illegal; |
10714 | } | |
10715 | ||
9aac24b1 JB |
10716 | if (exp_seg == reg_section) |
10717 | { | |
10718 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
10719 | return 0; | |
10720 | } | |
10721 | ||
ee86248c JB |
10722 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
10723 | } | |
252b5132 | 10724 | |
ee86248c JB |
10725 | static int |
10726 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10727 | i386_operand_type types, const char *imm_start) | |
10728 | { | |
10729 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 10730 | { |
313c53d1 L |
10731 | if (imm_start) |
10732 | as_bad (_("missing or invalid immediate expression `%s'"), | |
10733 | imm_start); | |
3992d3b7 | 10734 | return 0; |
252b5132 | 10735 | } |
3e73aa7c | 10736 | else if (exp->X_op == O_constant) |
252b5132 | 10737 | { |
47926f60 | 10738 | /* Size it properly later. */ |
40fb9820 | 10739 | i.types[this_operand].bitfield.imm64 = 1; |
13f864ae L |
10740 | /* If not 64bit, sign extend val. */ |
10741 | if (flag_code != CODE_64BIT | |
4eed87de AM |
10742 | && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
10743 | exp->X_add_number | |
10744 | = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
252b5132 | 10745 | } |
4c63da97 | 10746 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 10747 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 10748 | && exp_seg != absolute_section |
47926f60 | 10749 | && exp_seg != text_section |
24eab124 AM |
10750 | && exp_seg != data_section |
10751 | && exp_seg != bss_section | |
10752 | && exp_seg != undefined_section | |
f86103b7 | 10753 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 10754 | { |
d0b47220 | 10755 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
10756 | return 0; |
10757 | } | |
10758 | #endif | |
10759 | else | |
10760 | { | |
10761 | /* This is an address. The size of the address will be | |
24eab124 | 10762 | determined later, depending on destination register, |
3e73aa7c | 10763 | suffix, or the default for the section. */ |
40fb9820 L |
10764 | i.types[this_operand].bitfield.imm8 = 1; |
10765 | i.types[this_operand].bitfield.imm16 = 1; | |
10766 | i.types[this_operand].bitfield.imm32 = 1; | |
10767 | i.types[this_operand].bitfield.imm32s = 1; | |
10768 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
10769 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
10770 | types); | |
252b5132 RH |
10771 | } |
10772 | ||
10773 | return 1; | |
10774 | } | |
10775 | ||
551c1ca1 | 10776 | static char * |
e3bb37b5 | 10777 | i386_scale (char *scale) |
252b5132 | 10778 | { |
551c1ca1 AM |
10779 | offsetT val; |
10780 | char *save = input_line_pointer; | |
252b5132 | 10781 | |
551c1ca1 AM |
10782 | input_line_pointer = scale; |
10783 | val = get_absolute_expression (); | |
10784 | ||
10785 | switch (val) | |
252b5132 | 10786 | { |
551c1ca1 | 10787 | case 1: |
252b5132 RH |
10788 | i.log2_scale_factor = 0; |
10789 | break; | |
551c1ca1 | 10790 | case 2: |
252b5132 RH |
10791 | i.log2_scale_factor = 1; |
10792 | break; | |
551c1ca1 | 10793 | case 4: |
252b5132 RH |
10794 | i.log2_scale_factor = 2; |
10795 | break; | |
551c1ca1 | 10796 | case 8: |
252b5132 RH |
10797 | i.log2_scale_factor = 3; |
10798 | break; | |
10799 | default: | |
a724f0f4 JB |
10800 | { |
10801 | char sep = *input_line_pointer; | |
10802 | ||
10803 | *input_line_pointer = '\0'; | |
10804 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
10805 | scale); | |
10806 | *input_line_pointer = sep; | |
10807 | input_line_pointer = save; | |
10808 | return NULL; | |
10809 | } | |
252b5132 | 10810 | } |
29b0f896 | 10811 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
10812 | { |
10813 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 10814 | 1 << i.log2_scale_factor); |
252b5132 | 10815 | i.log2_scale_factor = 0; |
252b5132 | 10816 | } |
551c1ca1 AM |
10817 | scale = input_line_pointer; |
10818 | input_line_pointer = save; | |
10819 | return scale; | |
252b5132 RH |
10820 | } |
10821 | ||
252b5132 | 10822 | static int |
e3bb37b5 | 10823 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 10824 | { |
29b0f896 | 10825 | expressionS *exp; |
252b5132 RH |
10826 | segT exp_seg = 0; |
10827 | char *save_input_line_pointer; | |
f3c180ae | 10828 | char *gotfree_input_line; |
40fb9820 L |
10829 | int override; |
10830 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 10831 | int ret; |
252b5132 | 10832 | |
31b2323c L |
10833 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
10834 | { | |
10835 | as_bad (_("at most %d displacement operands are allowed"), | |
10836 | MAX_MEMORY_OPERANDS); | |
10837 | return 0; | |
10838 | } | |
10839 | ||
0dfbf9d7 | 10840 | operand_type_set (&bigdisp, 0); |
6f2f06be | 10841 | if (i.jumpabsolute |
48bcea9f | 10842 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
10843 | || (current_templates->start->opcode_modifier.jump != JUMP |
10844 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 10845 | { |
48bcea9f | 10846 | i386_addressing_mode (); |
e05278af | 10847 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
10848 | if (flag_code == CODE_64BIT) |
10849 | { | |
10850 | if (!override) | |
10851 | { | |
10852 | bigdisp.bitfield.disp32s = 1; | |
10853 | bigdisp.bitfield.disp64 = 1; | |
10854 | } | |
48bcea9f JB |
10855 | else |
10856 | bigdisp.bitfield.disp32 = 1; | |
40fb9820 L |
10857 | } |
10858 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 10859 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
10860 | else |
10861 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
10862 | } |
10863 | else | |
10864 | { | |
376cd056 JB |
10865 | /* For PC-relative branches, the width of the displacement may be |
10866 | dependent upon data size, but is never dependent upon address size. | |
10867 | Also make sure to not unintentionally match against a non-PC-relative | |
10868 | branch template. */ | |
10869 | static templates aux_templates; | |
10870 | const insn_template *t = current_templates->start; | |
5b7c81bd | 10871 | bool has_intel64 = false; |
376cd056 JB |
10872 | |
10873 | aux_templates.start = t; | |
10874 | while (++t < current_templates->end) | |
10875 | { | |
10876 | if (t->opcode_modifier.jump | |
10877 | != current_templates->start->opcode_modifier.jump) | |
10878 | break; | |
4b5aaf5f | 10879 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 10880 | has_intel64 = true; |
376cd056 JB |
10881 | } |
10882 | if (t < current_templates->end) | |
10883 | { | |
10884 | aux_templates.end = t; | |
10885 | current_templates = &aux_templates; | |
10886 | } | |
10887 | ||
e05278af | 10888 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
10889 | if (flag_code == CODE_64BIT) |
10890 | { | |
376cd056 JB |
10891 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
10892 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
10893 | bigdisp.bitfield.disp16 = 1; |
10894 | else | |
48bcea9f | 10895 | bigdisp.bitfield.disp32s = 1; |
40fb9820 L |
10896 | } |
10897 | else | |
e05278af JB |
10898 | { |
10899 | if (!override) | |
10900 | override = (i.suffix == (flag_code != CODE_16BIT | |
10901 | ? WORD_MNEM_SUFFIX | |
10902 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
10903 | bigdisp.bitfield.disp32 = 1; |
10904 | if ((flag_code == CODE_16BIT) ^ override) | |
10905 | { | |
10906 | bigdisp.bitfield.disp32 = 0; | |
10907 | bigdisp.bitfield.disp16 = 1; | |
10908 | } | |
e05278af | 10909 | } |
e05278af | 10910 | } |
c6fb90c8 L |
10911 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
10912 | bigdisp); | |
252b5132 RH |
10913 | |
10914 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 10915 | i.op[this_operand].disps = exp; |
252b5132 RH |
10916 | i.disp_operands++; |
10917 | save_input_line_pointer = input_line_pointer; | |
10918 | input_line_pointer = disp_start; | |
10919 | END_STRING_AND_SAVE (disp_end); | |
10920 | ||
10921 | #ifndef GCC_ASM_O_HACK | |
10922 | #define GCC_ASM_O_HACK 0 | |
10923 | #endif | |
10924 | #if GCC_ASM_O_HACK | |
10925 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 10926 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 10927 | && displacement_string_end[-1] == '+') |
252b5132 RH |
10928 | { |
10929 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
10930 | constraint within gcc asm statements. |
10931 | For instance: | |
10932 | ||
10933 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
10934 | __asm__ __volatile__ ( \ | |
10935 | "movw %w2,%0\n\t" \ | |
10936 | "movw %w1,2+%0\n\t" \ | |
10937 | "rorl $16,%1\n\t" \ | |
10938 | "movb %b1,4+%0\n\t" \ | |
10939 | "movb %4,5+%0\n\t" \ | |
10940 | "movb $0,6+%0\n\t" \ | |
10941 | "movb %h1,7+%0\n\t" \ | |
10942 | "rorl $16,%1" \ | |
10943 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
10944 | ||
10945 | This works great except that the output assembler ends | |
10946 | up looking a bit weird if it turns out that there is | |
10947 | no offset. You end up producing code that looks like: | |
10948 | ||
10949 | #APP | |
10950 | movw $235,(%eax) | |
10951 | movw %dx,2+(%eax) | |
10952 | rorl $16,%edx | |
10953 | movb %dl,4+(%eax) | |
10954 | movb $137,5+(%eax) | |
10955 | movb $0,6+(%eax) | |
10956 | movb %dh,7+(%eax) | |
10957 | rorl $16,%edx | |
10958 | #NO_APP | |
10959 | ||
47926f60 | 10960 | So here we provide the missing zero. */ |
24eab124 AM |
10961 | |
10962 | *displacement_string_end = '0'; | |
252b5132 RH |
10963 | } |
10964 | #endif | |
d258b828 | 10965 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
10966 | if (gotfree_input_line) |
10967 | input_line_pointer = gotfree_input_line; | |
252b5132 | 10968 | |
24eab124 | 10969 | exp_seg = expression (exp); |
252b5132 | 10970 | |
636c26b0 AM |
10971 | SKIP_WHITESPACE (); |
10972 | if (*input_line_pointer) | |
10973 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
10974 | #if GCC_ASM_O_HACK | |
10975 | RESTORE_END_STRING (disp_end + 1); | |
10976 | #endif | |
636c26b0 | 10977 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 10978 | if (gotfree_input_line) |
ee86248c JB |
10979 | { |
10980 | free (gotfree_input_line); | |
10981 | ||
10982 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
10983 | exp->X_op = O_illegal; | |
10984 | } | |
10985 | ||
10986 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
10987 | ||
10988 | RESTORE_END_STRING (disp_end); | |
10989 | ||
10990 | return ret; | |
10991 | } | |
10992 | ||
10993 | static int | |
10994 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
10995 | i386_operand_type types, const char *disp_start) | |
10996 | { | |
10997 | i386_operand_type bigdisp; | |
10998 | int ret = 1; | |
636c26b0 | 10999 | |
24eab124 AM |
11000 | /* We do this to make sure that the section symbol is in |
11001 | the symbol table. We will ultimately change the relocation | |
47926f60 | 11002 | to be relative to the beginning of the section. */ |
1ae12ab7 | 11003 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
11004 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
11005 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 11006 | { |
636c26b0 | 11007 | if (exp->X_op != O_symbol) |
3992d3b7 | 11008 | goto inv_disp; |
636c26b0 | 11009 | |
e5cb08ac | 11010 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
11011 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
11012 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 11013 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
11014 | exp->X_op = O_subtract; |
11015 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 11016 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 11017 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
11018 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
11019 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 11020 | else |
29b0f896 | 11021 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 11022 | } |
252b5132 | 11023 | |
3992d3b7 AM |
11024 | else if (exp->X_op == O_absent |
11025 | || exp->X_op == O_illegal | |
ee86248c | 11026 | || exp->X_op == O_big) |
2daf4fd8 | 11027 | { |
3992d3b7 AM |
11028 | inv_disp: |
11029 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 11030 | disp_start); |
3992d3b7 | 11031 | ret = 0; |
2daf4fd8 AM |
11032 | } |
11033 | ||
4c63da97 | 11034 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
3992d3b7 AM |
11035 | else if (exp->X_op != O_constant |
11036 | && OUTPUT_FLAVOR == bfd_target_aout_flavour | |
11037 | && exp_seg != absolute_section | |
11038 | && exp_seg != text_section | |
11039 | && exp_seg != data_section | |
11040 | && exp_seg != bss_section | |
11041 | && exp_seg != undefined_section | |
11042 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 11043 | { |
d0b47220 | 11044 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 11045 | ret = 0; |
24eab124 | 11046 | } |
252b5132 | 11047 | #endif |
3956db08 | 11048 | |
48bcea9f JB |
11049 | if (current_templates->start->opcode_modifier.jump == JUMP_BYTE |
11050 | /* Constants get taken care of by optimize_disp(). */ | |
11051 | && exp->X_op != O_constant) | |
11052 | i.types[this_operand].bitfield.disp8 = 1; | |
11053 | ||
40fb9820 L |
11054 | /* Check if this is a displacement only operand. */ |
11055 | bigdisp = i.types[this_operand]; | |
11056 | bigdisp.bitfield.disp8 = 0; | |
11057 | bigdisp.bitfield.disp16 = 0; | |
11058 | bigdisp.bitfield.disp32 = 0; | |
11059 | bigdisp.bitfield.disp32s = 0; | |
11060 | bigdisp.bitfield.disp64 = 0; | |
0dfbf9d7 | 11061 | if (operand_type_all_zero (&bigdisp)) |
c6fb90c8 L |
11062 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
11063 | types); | |
3956db08 | 11064 | |
3992d3b7 | 11065 | return ret; |
252b5132 RH |
11066 | } |
11067 | ||
2abc2bec JB |
11068 | /* Return the active addressing mode, taking address override and |
11069 | registers forming the address into consideration. Update the | |
11070 | address override prefix if necessary. */ | |
47926f60 | 11071 | |
2abc2bec JB |
11072 | static enum flag_code |
11073 | i386_addressing_mode (void) | |
252b5132 | 11074 | { |
be05d201 L |
11075 | enum flag_code addr_mode; |
11076 | ||
11077 | if (i.prefix[ADDR_PREFIX]) | |
11078 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 JB |
11079 | else if (flag_code == CODE_16BIT |
11080 | && current_templates->start->cpu_flags.bitfield.cpumpx | |
11081 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic | |
11082 | from md_assemble() by "is not a valid base/index expression" | |
11083 | when there is a base and/or index. */ | |
11084 | && !i.types[this_operand].bitfield.baseindex) | |
11085 | { | |
11086 | /* MPX insn memory operands with neither base nor index must be forced | |
11087 | to use 32-bit addressing in 16-bit mode. */ | |
11088 | addr_mode = CODE_32BIT; | |
11089 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11090 | ++i.prefixes; | |
11091 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
11092 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
11093 | } | |
be05d201 L |
11094 | else |
11095 | { | |
11096 | addr_mode = flag_code; | |
11097 | ||
24eab124 | 11098 | #if INFER_ADDR_PREFIX |
be05d201 L |
11099 | if (i.mem_operands == 0) |
11100 | { | |
11101 | /* Infer address prefix from the first memory operand. */ | |
11102 | const reg_entry *addr_reg = i.base_reg; | |
11103 | ||
11104 | if (addr_reg == NULL) | |
11105 | addr_reg = i.index_reg; | |
eecb386c | 11106 | |
be05d201 L |
11107 | if (addr_reg) |
11108 | { | |
e968fc9b | 11109 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
11110 | addr_mode = CODE_32BIT; |
11111 | else if (flag_code != CODE_64BIT | |
dc821c5f | 11112 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
11113 | addr_mode = CODE_16BIT; |
11114 | ||
11115 | if (addr_mode != flag_code) | |
11116 | { | |
11117 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
11118 | i.prefixes += 1; | |
11119 | /* Change the size of any displacement too. At most one | |
11120 | of Disp16 or Disp32 is set. | |
11121 | FIXME. There doesn't seem to be any real need for | |
11122 | separate Disp16 and Disp32 flags. The same goes for | |
11123 | Imm16 and Imm32. Removing them would probably clean | |
11124 | up the code quite a lot. */ | |
11125 | if (flag_code != CODE_64BIT | |
11126 | && (i.types[this_operand].bitfield.disp16 | |
11127 | || i.types[this_operand].bitfield.disp32)) | |
11128 | i.types[this_operand] | |
11129 | = operand_type_xor (i.types[this_operand], disp16_32); | |
11130 | } | |
11131 | } | |
11132 | } | |
24eab124 | 11133 | #endif |
be05d201 L |
11134 | } |
11135 | ||
2abc2bec JB |
11136 | return addr_mode; |
11137 | } | |
11138 | ||
11139 | /* Make sure the memory operand we've been dealt is valid. | |
11140 | Return 1 on success, 0 on a failure. */ | |
11141 | ||
11142 | static int | |
11143 | i386_index_check (const char *operand_string) | |
11144 | { | |
11145 | const char *kind = "base/index"; | |
11146 | enum flag_code addr_mode = i386_addressing_mode (); | |
a152332d | 11147 | const insn_template *t = current_templates->start; |
2abc2bec | 11148 | |
a152332d JB |
11149 | if (t->opcode_modifier.isstring |
11150 | && !t->cpu_flags.bitfield.cpupadlock | |
fc0763e6 JB |
11151 | && (current_templates->end[-1].opcode_modifier.isstring |
11152 | || i.mem_operands)) | |
11153 | { | |
11154 | /* Memory operands of string insns are special in that they only allow | |
11155 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 L |
11156 | const reg_entry *expected_reg; |
11157 | static const char *di_si[][2] = | |
11158 | { | |
11159 | { "esi", "edi" }, | |
11160 | { "si", "di" }, | |
11161 | { "rsi", "rdi" } | |
11162 | }; | |
11163 | static const char *bx[] = { "ebx", "bx", "rbx" }; | |
fc0763e6 JB |
11164 | |
11165 | kind = "string address"; | |
11166 | ||
a152332d | 11167 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 11168 | { |
51c8edf6 JB |
11169 | int es_op = current_templates->end[-1].opcode_modifier.isstring |
11170 | - IS_STRING_ES_OP0; | |
11171 | int op = 0; | |
fc0763e6 | 11172 | |
51c8edf6 | 11173 | if (!current_templates->end[-1].operand_types[0].bitfield.baseindex |
fc0763e6 JB |
11174 | || ((!i.mem_operands != !intel_syntax) |
11175 | && current_templates->end[-1].operand_types[1] | |
11176 | .bitfield.baseindex)) | |
51c8edf6 | 11177 | op = 1; |
fe0e921f AM |
11178 | expected_reg |
11179 | = (const reg_entry *) str_hash_find (reg_hash, | |
11180 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
11181 | } |
11182 | else | |
fe0e921f AM |
11183 | expected_reg |
11184 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 11185 | |
be05d201 L |
11186 | if (i.base_reg != expected_reg |
11187 | || i.index_reg | |
fc0763e6 | 11188 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 11189 | { |
be05d201 L |
11190 | /* The second memory operand must have the same size as |
11191 | the first one. */ | |
11192 | if (i.mem_operands | |
11193 | && i.base_reg | |
11194 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 11195 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 11196 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
11197 | ? i.base_reg->reg_type.bitfield.dword |
11198 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
11199 | goto bad_address; |
11200 | ||
fc0763e6 JB |
11201 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
11202 | operand_string, | |
11203 | intel_syntax ? '[' : '(', | |
11204 | register_prefix, | |
be05d201 | 11205 | expected_reg->reg_name, |
fc0763e6 | 11206 | intel_syntax ? ']' : ')'); |
be05d201 | 11207 | return 1; |
fc0763e6 | 11208 | } |
be05d201 L |
11209 | else |
11210 | return 1; | |
11211 | ||
dc1e8a47 | 11212 | bad_address: |
be05d201 L |
11213 | as_bad (_("`%s' is not a valid %s expression"), |
11214 | operand_string, kind); | |
11215 | return 0; | |
3e73aa7c JH |
11216 | } |
11217 | else | |
11218 | { | |
be05d201 L |
11219 | if (addr_mode != CODE_16BIT) |
11220 | { | |
11221 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
11222 | if (i.disp_encoding == disp_encoding_16bit) |
11223 | { | |
11224 | bad_disp: | |
11225 | as_bad (_("invalid `%s' prefix"), | |
11226 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
11227 | return 0; | |
11228 | } | |
11229 | ||
be05d201 | 11230 | if ((i.base_reg |
e968fc9b JB |
11231 | && ((addr_mode == CODE_64BIT |
11232 | ? !i.base_reg->reg_type.bitfield.qword | |
11233 | : !i.base_reg->reg_type.bitfield.dword) | |
11234 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
11235 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 11236 | || (i.index_reg |
1b54b8d7 JB |
11237 | && !i.index_reg->reg_type.bitfield.xmmword |
11238 | && !i.index_reg->reg_type.bitfield.ymmword | |
11239 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 11240 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
11241 | ? !i.index_reg->reg_type.bitfield.qword |
11242 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
11243 | || !i.index_reg->reg_type.bitfield.baseindex))) |
11244 | goto bad_address; | |
8178be5b | 11245 | |
260cd341 | 11246 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
a152332d | 11247 | if ((t->opcode_modifier.opcodeprefix == PREFIX_0XF3 |
389d00a5 JB |
11248 | && t->opcode_modifier.opcodespace == SPACE_0F |
11249 | && t->base_opcode == 0x1b) | |
a152332d | 11250 | || (t->opcode_modifier.opcodeprefix == PREFIX_NONE |
389d00a5 JB |
11251 | && t->opcode_modifier.opcodespace == SPACE_0F |
11252 | && (t->base_opcode & ~1) == 0x1a) | |
a152332d | 11253 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
11254 | { |
11255 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 11256 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
11257 | { |
11258 | as_bad (_("`%s' cannot be used here"), operand_string); | |
11259 | return 0; | |
11260 | } | |
11261 | ||
11262 | /* bndldx and bndstx ignore their scale factor. */ | |
a152332d | 11263 | if (t->opcode_modifier.opcodeprefix == PREFIX_NONE |
389d00a5 JB |
11264 | && t->opcode_modifier.opcodespace == SPACE_0F |
11265 | && (t->base_opcode & ~1) == 0x1a | |
8178be5b JB |
11266 | && i.log2_scale_factor) |
11267 | as_warn (_("register scaling is being ignored here")); | |
11268 | } | |
be05d201 L |
11269 | } |
11270 | else | |
3e73aa7c | 11271 | { |
be05d201 | 11272 | /* 16-bit checks. */ |
41eb8e88 L |
11273 | if (i.disp_encoding == disp_encoding_32bit) |
11274 | goto bad_disp; | |
11275 | ||
3e73aa7c | 11276 | if ((i.base_reg |
dc821c5f | 11277 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 11278 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 11279 | || (i.index_reg |
dc821c5f | 11280 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 11281 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
11282 | || !(i.base_reg |
11283 | && i.base_reg->reg_num < 6 | |
11284 | && i.index_reg->reg_num >= 6 | |
11285 | && i.log2_scale_factor == 0)))) | |
be05d201 | 11286 | goto bad_address; |
3e73aa7c JH |
11287 | } |
11288 | } | |
be05d201 | 11289 | return 1; |
24eab124 | 11290 | } |
252b5132 | 11291 | |
43234a1e L |
11292 | /* Handle vector immediates. */ |
11293 | ||
11294 | static int | |
11295 | RC_SAE_immediate (const char *imm_start) | |
11296 | { | |
11297 | unsigned int match_found, j; | |
11298 | const char *pstr = imm_start; | |
11299 | expressionS *exp; | |
11300 | ||
11301 | if (*pstr != '{') | |
11302 | return 0; | |
11303 | ||
11304 | pstr++; | |
11305 | match_found = 0; | |
11306 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
11307 | { | |
11308 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
11309 | { | |
ca5312a2 | 11310 | if (i.rounding.type != rc_none) |
43234a1e L |
11311 | { |
11312 | as_bad (_("duplicated `%s'"), imm_start); | |
11313 | return 0; | |
11314 | } | |
ca5312a2 JB |
11315 | |
11316 | i.rounding.type = RC_NamesTable[j].type; | |
11317 | i.rounding.operand = this_operand; | |
11318 | ||
43234a1e L |
11319 | pstr += RC_NamesTable[j].len; |
11320 | match_found = 1; | |
11321 | break; | |
11322 | } | |
11323 | } | |
11324 | if (!match_found) | |
11325 | return 0; | |
11326 | ||
11327 | if (*pstr++ != '}') | |
11328 | { | |
11329 | as_bad (_("Missing '}': '%s'"), imm_start); | |
11330 | return 0; | |
11331 | } | |
11332 | /* RC/SAE immediate string should contain nothing more. */; | |
11333 | if (*pstr != 0) | |
11334 | { | |
11335 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
11336 | return 0; | |
11337 | } | |
11338 | ||
11339 | exp = &im_expressions[i.imm_operands++]; | |
11340 | i.op[this_operand].imms = exp; | |
11341 | ||
11342 | exp->X_op = O_constant; | |
11343 | exp->X_add_number = 0; | |
11344 | exp->X_add_symbol = (symbolS *) 0; | |
11345 | exp->X_op_symbol = (symbolS *) 0; | |
11346 | ||
11347 | i.types[this_operand].bitfield.imm8 = 1; | |
11348 | return 1; | |
11349 | } | |
11350 | ||
8325cc63 JB |
11351 | /* Only string instructions can have a second memory operand, so |
11352 | reduce current_templates to just those if it contains any. */ | |
11353 | static int | |
11354 | maybe_adjust_templates (void) | |
11355 | { | |
11356 | const insn_template *t; | |
11357 | ||
11358 | gas_assert (i.mem_operands == 1); | |
11359 | ||
11360 | for (t = current_templates->start; t < current_templates->end; ++t) | |
11361 | if (t->opcode_modifier.isstring) | |
11362 | break; | |
11363 | ||
11364 | if (t < current_templates->end) | |
11365 | { | |
11366 | static templates aux_templates; | |
5b7c81bd | 11367 | bool recheck; |
8325cc63 JB |
11368 | |
11369 | aux_templates.start = t; | |
11370 | for (; t < current_templates->end; ++t) | |
11371 | if (!t->opcode_modifier.isstring) | |
11372 | break; | |
11373 | aux_templates.end = t; | |
11374 | ||
11375 | /* Determine whether to re-check the first memory operand. */ | |
11376 | recheck = (aux_templates.start != current_templates->start | |
11377 | || t != current_templates->end); | |
11378 | ||
11379 | current_templates = &aux_templates; | |
11380 | ||
11381 | if (recheck) | |
11382 | { | |
11383 | i.mem_operands = 0; | |
11384 | if (i.memop1_string != NULL | |
11385 | && i386_index_check (i.memop1_string) == 0) | |
11386 | return 0; | |
11387 | i.mem_operands = 1; | |
11388 | } | |
11389 | } | |
11390 | ||
11391 | return 1; | |
11392 | } | |
11393 | ||
fc0763e6 | 11394 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 11395 | on error. */ |
252b5132 | 11396 | |
252b5132 | 11397 | static int |
a7619375 | 11398 | i386_att_operand (char *operand_string) |
252b5132 | 11399 | { |
af6bdddf AM |
11400 | const reg_entry *r; |
11401 | char *end_op; | |
24eab124 | 11402 | char *op_string = operand_string; |
252b5132 | 11403 | |
24eab124 | 11404 | if (is_space_char (*op_string)) |
252b5132 RH |
11405 | ++op_string; |
11406 | ||
24eab124 | 11407 | /* We check for an absolute prefix (differentiating, |
47926f60 | 11408 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
24eab124 AM |
11409 | if (*op_string == ABSOLUTE_PREFIX) |
11410 | { | |
11411 | ++op_string; | |
11412 | if (is_space_char (*op_string)) | |
11413 | ++op_string; | |
5b7c81bd | 11414 | i.jumpabsolute = true; |
24eab124 | 11415 | } |
252b5132 | 11416 | |
47926f60 | 11417 | /* Check if operand is a register. */ |
4d1bb795 | 11418 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 11419 | { |
40fb9820 L |
11420 | i386_operand_type temp; |
11421 | ||
8a6fb3f9 JB |
11422 | if (r == &bad_reg) |
11423 | return 0; | |
11424 | ||
24eab124 AM |
11425 | /* Check for a segment override by searching for ':' after a |
11426 | segment register. */ | |
11427 | op_string = end_op; | |
11428 | if (is_space_char (*op_string)) | |
11429 | ++op_string; | |
00cee14f | 11430 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 11431 | { |
5e042380 | 11432 | i.seg[i.mem_operands] = r; |
252b5132 | 11433 | |
24eab124 | 11434 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
11435 | ++op_string; |
11436 | if (is_space_char (*op_string)) | |
24eab124 | 11437 | ++op_string; |
252b5132 | 11438 | |
24eab124 AM |
11439 | if (!is_digit_char (*op_string) |
11440 | && !is_identifier_char (*op_string) | |
11441 | && *op_string != '(' | |
11442 | && *op_string != ABSOLUTE_PREFIX) | |
11443 | { | |
11444 | as_bad (_("bad memory operand `%s'"), op_string); | |
11445 | return 0; | |
11446 | } | |
47926f60 | 11447 | /* Handle case of %es:*foo. */ |
24eab124 AM |
11448 | if (*op_string == ABSOLUTE_PREFIX) |
11449 | { | |
11450 | ++op_string; | |
11451 | if (is_space_char (*op_string)) | |
11452 | ++op_string; | |
5b7c81bd | 11453 | i.jumpabsolute = true; |
24eab124 AM |
11454 | } |
11455 | goto do_memory_reference; | |
11456 | } | |
43234a1e L |
11457 | |
11458 | /* Handle vector operations. */ | |
11459 | if (*op_string == '{') | |
11460 | { | |
11461 | op_string = check_VecOperations (op_string, NULL); | |
11462 | if (op_string == NULL) | |
11463 | return 0; | |
11464 | } | |
11465 | ||
24eab124 AM |
11466 | if (*op_string) |
11467 | { | |
d0b47220 | 11468 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
11469 | return 0; |
11470 | } | |
40fb9820 L |
11471 | temp = r->reg_type; |
11472 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
11473 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
11474 | temp); | |
7d5e4556 | 11475 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 11476 | i.op[this_operand].regs = r; |
24eab124 AM |
11477 | i.reg_operands++; |
11478 | } | |
af6bdddf AM |
11479 | else if (*op_string == REGISTER_PREFIX) |
11480 | { | |
11481 | as_bad (_("bad register name `%s'"), op_string); | |
11482 | return 0; | |
11483 | } | |
24eab124 | 11484 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 11485 | { |
24eab124 | 11486 | ++op_string; |
6f2f06be | 11487 | if (i.jumpabsolute) |
24eab124 | 11488 | { |
d0b47220 | 11489 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
11490 | return 0; |
11491 | } | |
11492 | if (!i386_immediate (op_string)) | |
11493 | return 0; | |
11494 | } | |
43234a1e L |
11495 | else if (RC_SAE_immediate (operand_string)) |
11496 | { | |
11497 | /* If it is a RC or SAE immediate, do nothing. */ | |
11498 | ; | |
11499 | } | |
24eab124 AM |
11500 | else if (is_digit_char (*op_string) |
11501 | || is_identifier_char (*op_string) | |
d02603dc | 11502 | || *op_string == '"' |
e5cb08ac | 11503 | || *op_string == '(') |
24eab124 | 11504 | { |
47926f60 | 11505 | /* This is a memory reference of some sort. */ |
af6bdddf | 11506 | char *base_string; |
252b5132 | 11507 | |
47926f60 | 11508 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
11509 | char *displacement_string_start; |
11510 | char *displacement_string_end; | |
43234a1e | 11511 | char *vop_start; |
252b5132 | 11512 | |
24eab124 | 11513 | do_memory_reference: |
8325cc63 JB |
11514 | if (i.mem_operands == 1 && !maybe_adjust_templates ()) |
11515 | return 0; | |
24eab124 | 11516 | if ((i.mem_operands == 1 |
40fb9820 | 11517 | && !current_templates->start->opcode_modifier.isstring) |
24eab124 AM |
11518 | || i.mem_operands == 2) |
11519 | { | |
11520 | as_bad (_("too many memory references for `%s'"), | |
11521 | current_templates->start->name); | |
11522 | return 0; | |
11523 | } | |
252b5132 | 11524 | |
24eab124 AM |
11525 | /* Check for base index form. We detect the base index form by |
11526 | looking for an ')' at the end of the operand, searching | |
11527 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
11528 | after the '('. */ | |
af6bdddf | 11529 | base_string = op_string + strlen (op_string); |
c3332e24 | 11530 | |
43234a1e L |
11531 | /* Handle vector operations. */ |
11532 | vop_start = strchr (op_string, '{'); | |
11533 | if (vop_start && vop_start < base_string) | |
11534 | { | |
11535 | if (check_VecOperations (vop_start, base_string) == NULL) | |
11536 | return 0; | |
11537 | base_string = vop_start; | |
11538 | } | |
11539 | ||
af6bdddf AM |
11540 | --base_string; |
11541 | if (is_space_char (*base_string)) | |
11542 | --base_string; | |
252b5132 | 11543 | |
47926f60 | 11544 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
11545 | displacement_string_start = op_string; |
11546 | displacement_string_end = base_string + 1; | |
252b5132 | 11547 | |
24eab124 AM |
11548 | if (*base_string == ')') |
11549 | { | |
af6bdddf | 11550 | char *temp_string; |
24eab124 AM |
11551 | unsigned int parens_balanced = 1; |
11552 | /* We've already checked that the number of left & right ()'s are | |
47926f60 | 11553 | equal, so this loop will not be infinite. */ |
24eab124 AM |
11554 | do |
11555 | { | |
11556 | base_string--; | |
11557 | if (*base_string == ')') | |
11558 | parens_balanced++; | |
11559 | if (*base_string == '(') | |
11560 | parens_balanced--; | |
11561 | } | |
11562 | while (parens_balanced); | |
c3332e24 | 11563 | |
af6bdddf | 11564 | temp_string = base_string; |
c3332e24 | 11565 | |
24eab124 | 11566 | /* Skip past '(' and whitespace. */ |
252b5132 RH |
11567 | ++base_string; |
11568 | if (is_space_char (*base_string)) | |
24eab124 | 11569 | ++base_string; |
252b5132 | 11570 | |
af6bdddf | 11571 | if (*base_string == ',' |
4eed87de AM |
11572 | || ((i.base_reg = parse_register (base_string, &end_op)) |
11573 | != NULL)) | |
252b5132 | 11574 | { |
af6bdddf | 11575 | displacement_string_end = temp_string; |
252b5132 | 11576 | |
40fb9820 | 11577 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 11578 | |
af6bdddf | 11579 | if (i.base_reg) |
24eab124 | 11580 | { |
8a6fb3f9 JB |
11581 | if (i.base_reg == &bad_reg) |
11582 | return 0; | |
24eab124 AM |
11583 | base_string = end_op; |
11584 | if (is_space_char (*base_string)) | |
11585 | ++base_string; | |
af6bdddf AM |
11586 | } |
11587 | ||
11588 | /* There may be an index reg or scale factor here. */ | |
11589 | if (*base_string == ',') | |
11590 | { | |
11591 | ++base_string; | |
11592 | if (is_space_char (*base_string)) | |
11593 | ++base_string; | |
11594 | ||
4eed87de AM |
11595 | if ((i.index_reg = parse_register (base_string, &end_op)) |
11596 | != NULL) | |
24eab124 | 11597 | { |
8a6fb3f9 JB |
11598 | if (i.index_reg == &bad_reg) |
11599 | return 0; | |
af6bdddf | 11600 | base_string = end_op; |
24eab124 AM |
11601 | if (is_space_char (*base_string)) |
11602 | ++base_string; | |
af6bdddf AM |
11603 | if (*base_string == ',') |
11604 | { | |
11605 | ++base_string; | |
11606 | if (is_space_char (*base_string)) | |
11607 | ++base_string; | |
11608 | } | |
e5cb08ac | 11609 | else if (*base_string != ')') |
af6bdddf | 11610 | { |
4eed87de AM |
11611 | as_bad (_("expecting `,' or `)' " |
11612 | "after index register in `%s'"), | |
af6bdddf AM |
11613 | operand_string); |
11614 | return 0; | |
11615 | } | |
24eab124 | 11616 | } |
af6bdddf | 11617 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 11618 | { |
f76bf5e0 L |
11619 | end_op = strchr (base_string, ','); |
11620 | if (end_op) | |
11621 | *end_op = '\0'; | |
af6bdddf | 11622 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
11623 | return 0; |
11624 | } | |
252b5132 | 11625 | |
47926f60 | 11626 | /* Check for scale factor. */ |
551c1ca1 | 11627 | if (*base_string != ')') |
af6bdddf | 11628 | { |
551c1ca1 AM |
11629 | char *end_scale = i386_scale (base_string); |
11630 | ||
11631 | if (!end_scale) | |
af6bdddf | 11632 | return 0; |
24eab124 | 11633 | |
551c1ca1 | 11634 | base_string = end_scale; |
af6bdddf AM |
11635 | if (is_space_char (*base_string)) |
11636 | ++base_string; | |
11637 | if (*base_string != ')') | |
11638 | { | |
4eed87de AM |
11639 | as_bad (_("expecting `)' " |
11640 | "after scale factor in `%s'"), | |
af6bdddf AM |
11641 | operand_string); |
11642 | return 0; | |
11643 | } | |
11644 | } | |
11645 | else if (!i.index_reg) | |
24eab124 | 11646 | { |
4eed87de AM |
11647 | as_bad (_("expecting index register or scale factor " |
11648 | "after `,'; got '%c'"), | |
af6bdddf | 11649 | *base_string); |
24eab124 AM |
11650 | return 0; |
11651 | } | |
11652 | } | |
af6bdddf | 11653 | else if (*base_string != ')') |
24eab124 | 11654 | { |
4eed87de AM |
11655 | as_bad (_("expecting `,' or `)' " |
11656 | "after base register in `%s'"), | |
af6bdddf | 11657 | operand_string); |
24eab124 AM |
11658 | return 0; |
11659 | } | |
c3332e24 | 11660 | } |
af6bdddf | 11661 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 11662 | { |
f76bf5e0 L |
11663 | end_op = strchr (base_string, ','); |
11664 | if (end_op) | |
11665 | *end_op = '\0'; | |
af6bdddf | 11666 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 11667 | return 0; |
c3332e24 | 11668 | } |
24eab124 AM |
11669 | } |
11670 | ||
11671 | /* If there's an expression beginning the operand, parse it, | |
11672 | assuming displacement_string_start and | |
11673 | displacement_string_end are meaningful. */ | |
11674 | if (displacement_string_start != displacement_string_end) | |
11675 | { | |
11676 | if (!i386_displacement (displacement_string_start, | |
11677 | displacement_string_end)) | |
11678 | return 0; | |
11679 | } | |
11680 | ||
11681 | /* Special case for (%dx) while doing input/output op. */ | |
11682 | if (i.base_reg | |
75e5731b JB |
11683 | && i.base_reg->reg_type.bitfield.instance == RegD |
11684 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
11685 | && i.index_reg == 0 |
11686 | && i.log2_scale_factor == 0 | |
11687 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 11688 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 11689 | { |
2fb5be8d | 11690 | i.types[this_operand] = i.base_reg->reg_type; |
24eab124 AM |
11691 | return 1; |
11692 | } | |
11693 | ||
eecb386c AM |
11694 | if (i386_index_check (operand_string) == 0) |
11695 | return 0; | |
c48dadc9 | 11696 | i.flags[this_operand] |= Operand_Mem; |
8325cc63 JB |
11697 | if (i.mem_operands == 0) |
11698 | i.memop1_string = xstrdup (operand_string); | |
24eab124 AM |
11699 | i.mem_operands++; |
11700 | } | |
11701 | else | |
ce8a8b2f AM |
11702 | { |
11703 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
11704 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
11705 | output_invalid (*op_string), | |
11706 | this_operand + 1, | |
11707 | op_string); | |
11708 | return 0; | |
11709 | } | |
47926f60 | 11710 | return 1; /* Normal return. */ |
252b5132 RH |
11711 | } |
11712 | \f | |
fa94de6b RM |
11713 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
11714 | that an rs_machine_dependent frag may reach. */ | |
11715 | ||
11716 | unsigned int | |
11717 | i386_frag_max_var (fragS *frag) | |
11718 | { | |
11719 | /* The only relaxable frags are for jumps. | |
11720 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
11721 | gas_assert (frag->fr_type == rs_machine_dependent); | |
11722 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
11723 | } | |
11724 | ||
b084df0b L |
11725 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
11726 | static int | |
8dcea932 | 11727 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
11728 | { |
11729 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
11730 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
11731 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
11732 | return 0; | |
11733 | ||
11734 | if (!S_IS_EXTERNAL (fr_symbol)) | |
11735 | /* Symbol may be weak or local. */ | |
11736 | return !S_IS_WEAK (fr_symbol); | |
11737 | ||
8dcea932 L |
11738 | /* Global symbols with non-default visibility can't be preempted. */ |
11739 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
11740 | return 1; | |
11741 | ||
11742 | if (fr_var != NO_RELOC) | |
11743 | switch ((enum bfd_reloc_code_real) fr_var) | |
11744 | { | |
11745 | case BFD_RELOC_386_PLT32: | |
11746 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 11747 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
11748 | return 0; |
11749 | default: | |
11750 | abort (); | |
11751 | } | |
11752 | ||
b084df0b L |
11753 | /* Global symbols with default visibility in a shared library may be |
11754 | preempted by another definition. */ | |
8dcea932 | 11755 | return !shared; |
b084df0b L |
11756 | } |
11757 | #endif | |
11758 | ||
79d72f45 HL |
11759 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
11760 | Note also work for Skylake and Cascadelake. | |
11761 | --------------------------------------------------------------------- | |
11762 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
11763 | | ------ | ----------- | ------- | -------- | | |
11764 | | Jo | N | N | Y | | |
11765 | | Jno | N | N | Y | | |
11766 | | Jc/Jb | Y | N | Y | | |
11767 | | Jae/Jnb | Y | N | Y | | |
11768 | | Je/Jz | Y | Y | Y | | |
11769 | | Jne/Jnz | Y | Y | Y | | |
11770 | | Jna/Jbe | Y | N | Y | | |
11771 | | Ja/Jnbe | Y | N | Y | | |
11772 | | Js | N | N | Y | | |
11773 | | Jns | N | N | Y | | |
11774 | | Jp/Jpe | N | N | Y | | |
11775 | | Jnp/Jpo | N | N | Y | | |
11776 | | Jl/Jnge | Y | Y | Y | | |
11777 | | Jge/Jnl | Y | Y | Y | | |
11778 | | Jle/Jng | Y | Y | Y | | |
11779 | | Jg/Jnle | Y | Y | Y | | |
11780 | --------------------------------------------------------------------- */ | |
11781 | static int | |
11782 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
11783 | { | |
11784 | if (mf_cmp == mf_cmp_alu_cmp) | |
11785 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
11786 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
11787 | if (mf_cmp == mf_cmp_incdec) | |
11788 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
11789 | || mf_jcc == mf_jcc_jle); | |
11790 | if (mf_cmp == mf_cmp_test_and) | |
11791 | return 1; | |
11792 | return 0; | |
11793 | } | |
11794 | ||
e379e5f3 L |
11795 | /* Return the next non-empty frag. */ |
11796 | ||
11797 | static fragS * | |
11798 | i386_next_non_empty_frag (fragS *fragP) | |
11799 | { | |
11800 | /* There may be a frag with a ".fill 0" when there is no room in | |
11801 | the current frag for frag_grow in output_insn. */ | |
11802 | for (fragP = fragP->fr_next; | |
11803 | (fragP != NULL | |
11804 | && fragP->fr_type == rs_fill | |
11805 | && fragP->fr_fix == 0); | |
11806 | fragP = fragP->fr_next) | |
11807 | ; | |
11808 | return fragP; | |
11809 | } | |
11810 | ||
11811 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
11812 | ||
11813 | static fragS * | |
79d72f45 | 11814 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 11815 | { |
79d72f45 HL |
11816 | fragS *branch_fragP; |
11817 | if (!pad_fragP) | |
e379e5f3 L |
11818 | return NULL; |
11819 | ||
79d72f45 HL |
11820 | if (pad_fragP->fr_type == rs_machine_dependent |
11821 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
11822 | == BRANCH_PADDING)) |
11823 | { | |
79d72f45 HL |
11824 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
11825 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 11826 | return NULL; |
79d72f45 HL |
11827 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
11828 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
11829 | pad_fragP->tc_frag_data.mf_type)) | |
11830 | return branch_fragP; | |
e379e5f3 L |
11831 | } |
11832 | ||
11833 | return NULL; | |
11834 | } | |
11835 | ||
11836 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
11837 | ||
11838 | static void | |
11839 | i386_classify_machine_dependent_frag (fragS *fragP) | |
11840 | { | |
11841 | fragS *cmp_fragP; | |
11842 | fragS *pad_fragP; | |
11843 | fragS *branch_fragP; | |
11844 | fragS *next_fragP; | |
11845 | unsigned int max_prefix_length; | |
11846 | ||
11847 | if (fragP->tc_frag_data.classified) | |
11848 | return; | |
11849 | ||
11850 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
11851 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
11852 | for (next_fragP = fragP; | |
11853 | next_fragP != NULL; | |
11854 | next_fragP = next_fragP->fr_next) | |
11855 | { | |
11856 | next_fragP->tc_frag_data.classified = 1; | |
11857 | if (next_fragP->fr_type == rs_machine_dependent) | |
11858 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
11859 | { | |
11860 | case BRANCH_PADDING: | |
11861 | /* The BRANCH_PADDING frag must be followed by a branch | |
11862 | frag. */ | |
11863 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
11864 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11865 | break; | |
11866 | case FUSED_JCC_PADDING: | |
11867 | /* Check if this is a fused jcc: | |
11868 | FUSED_JCC_PADDING | |
11869 | CMP like instruction | |
11870 | BRANCH_PADDING | |
11871 | COND_JUMP | |
11872 | */ | |
11873 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
11874 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 11875 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
11876 | if (branch_fragP) |
11877 | { | |
11878 | /* The BRANCH_PADDING frag is merged with the | |
11879 | FUSED_JCC_PADDING frag. */ | |
11880 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
11881 | /* CMP like instruction size. */ | |
11882 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
11883 | frag_wane (pad_fragP); | |
11884 | /* Skip to branch_fragP. */ | |
11885 | next_fragP = branch_fragP; | |
11886 | } | |
11887 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
11888 | { | |
11889 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
11890 | a fused jcc. */ | |
11891 | next_fragP->fr_subtype | |
11892 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
11893 | next_fragP->tc_frag_data.max_bytes | |
11894 | = next_fragP->tc_frag_data.max_prefix_length; | |
11895 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
11896 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
11897 | } | |
11898 | else | |
11899 | frag_wane (next_fragP); | |
11900 | break; | |
11901 | } | |
11902 | } | |
11903 | ||
11904 | /* Stop if there is no BRANCH_PREFIX. */ | |
11905 | if (!align_branch_prefix_size) | |
11906 | return; | |
11907 | ||
11908 | /* Scan for BRANCH_PREFIX. */ | |
11909 | for (; fragP != NULL; fragP = fragP->fr_next) | |
11910 | { | |
11911 | if (fragP->fr_type != rs_machine_dependent | |
11912 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
11913 | != BRANCH_PREFIX)) | |
11914 | continue; | |
11915 | ||
11916 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
11917 | COND_JUMP_PREFIX. */ | |
11918 | max_prefix_length = 0; | |
11919 | for (next_fragP = fragP; | |
11920 | next_fragP != NULL; | |
11921 | next_fragP = next_fragP->fr_next) | |
11922 | { | |
11923 | if (next_fragP->fr_type == rs_fill) | |
11924 | /* Skip rs_fill frags. */ | |
11925 | continue; | |
11926 | else if (next_fragP->fr_type != rs_machine_dependent) | |
11927 | /* Stop for all other frags. */ | |
11928 | break; | |
11929 | ||
11930 | /* rs_machine_dependent frags. */ | |
11931 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11932 | == BRANCH_PREFIX) | |
11933 | { | |
11934 | /* Count BRANCH_PREFIX frags. */ | |
11935 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
11936 | { | |
11937 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
11938 | frag_wane (next_fragP); | |
11939 | } | |
11940 | else | |
11941 | max_prefix_length | |
11942 | += next_fragP->tc_frag_data.max_bytes; | |
11943 | } | |
11944 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11945 | == BRANCH_PADDING) | |
11946 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
11947 | == FUSED_JCC_PADDING)) | |
11948 | { | |
11949 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
11950 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
11951 | break; | |
11952 | } | |
11953 | else | |
11954 | /* Stop for other rs_machine_dependent frags. */ | |
11955 | break; | |
11956 | } | |
11957 | ||
11958 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
11959 | ||
11960 | /* Skip to the next frag. */ | |
11961 | fragP = next_fragP; | |
11962 | } | |
11963 | } | |
11964 | ||
11965 | /* Compute padding size for | |
11966 | ||
11967 | FUSED_JCC_PADDING | |
11968 | CMP like instruction | |
11969 | BRANCH_PADDING | |
11970 | COND_JUMP/UNCOND_JUMP | |
11971 | ||
11972 | or | |
11973 | ||
11974 | BRANCH_PADDING | |
11975 | COND_JUMP/UNCOND_JUMP | |
11976 | */ | |
11977 | ||
11978 | static int | |
11979 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
11980 | { | |
11981 | unsigned int offset, size, padding_size; | |
11982 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
11983 | ||
11984 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
11985 | if (!address) | |
11986 | address = fragP->fr_address; | |
11987 | address += fragP->fr_fix; | |
11988 | ||
11989 | /* CMP like instrunction size. */ | |
11990 | size = fragP->tc_frag_data.cmp_size; | |
11991 | ||
11992 | /* The base size of the branch frag. */ | |
11993 | size += branch_fragP->fr_fix; | |
11994 | ||
11995 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
11996 | branch frag. */ | |
11997 | if (branch_fragP->fr_type == rs_machine_dependent) | |
11998 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
11999 | ||
12000 | /* Check if branch is within boundary and doesn't end at the last | |
12001 | byte. */ | |
12002 | offset = address & ((1U << align_branch_power) - 1); | |
12003 | if ((offset + size) >= (1U << align_branch_power)) | |
12004 | /* Padding needed to avoid crossing boundary. */ | |
12005 | padding_size = (1U << align_branch_power) - offset; | |
12006 | else | |
12007 | /* No padding needed. */ | |
12008 | padding_size = 0; | |
12009 | ||
12010 | /* The return value may be saved in tc_frag_data.length which is | |
12011 | unsigned byte. */ | |
12012 | if (!fits_in_unsigned_byte (padding_size)) | |
12013 | abort (); | |
12014 | ||
12015 | return padding_size; | |
12016 | } | |
12017 | ||
12018 | /* i386_generic_table_relax_frag() | |
12019 | ||
12020 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
12021 | grow/shrink padding to align branch frags. Hand others to | |
12022 | relax_frag(). */ | |
12023 | ||
12024 | long | |
12025 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
12026 | { | |
12027 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
12028 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12029 | { | |
12030 | long padding_size = i386_branch_padding_size (fragP, 0); | |
12031 | long grow = padding_size - fragP->tc_frag_data.length; | |
12032 | ||
12033 | /* When the BRANCH_PREFIX frag is used, the computed address | |
12034 | must match the actual address and there should be no padding. */ | |
12035 | if (fragP->tc_frag_data.padding_address | |
12036 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
12037 | || padding_size)) | |
12038 | abort (); | |
12039 | ||
12040 | /* Update the padding size. */ | |
12041 | if (grow) | |
12042 | fragP->tc_frag_data.length = padding_size; | |
12043 | ||
12044 | return grow; | |
12045 | } | |
12046 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12047 | { | |
12048 | fragS *padding_fragP, *next_fragP; | |
12049 | long padding_size, left_size, last_size; | |
12050 | ||
12051 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12052 | if (!padding_fragP) | |
12053 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
12054 | return (fragP->tc_frag_data.length | |
12055 | - fragP->tc_frag_data.last_length); | |
12056 | ||
12057 | /* Compute the relative address of the padding frag in the very | |
12058 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
12059 | if (!fragP->tc_frag_data.padding_address) | |
12060 | fragP->tc_frag_data.padding_address | |
12061 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
12062 | ||
12063 | /* First update the last length from the previous interation. */ | |
12064 | left_size = fragP->tc_frag_data.prefix_length; | |
12065 | for (next_fragP = fragP; | |
12066 | next_fragP != padding_fragP; | |
12067 | next_fragP = next_fragP->fr_next) | |
12068 | if (next_fragP->fr_type == rs_machine_dependent | |
12069 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12070 | == BRANCH_PREFIX)) | |
12071 | { | |
12072 | if (left_size) | |
12073 | { | |
12074 | int max = next_fragP->tc_frag_data.max_bytes; | |
12075 | if (max) | |
12076 | { | |
12077 | int size; | |
12078 | if (max > left_size) | |
12079 | size = left_size; | |
12080 | else | |
12081 | size = max; | |
12082 | left_size -= size; | |
12083 | next_fragP->tc_frag_data.last_length = size; | |
12084 | } | |
12085 | } | |
12086 | else | |
12087 | next_fragP->tc_frag_data.last_length = 0; | |
12088 | } | |
12089 | ||
12090 | /* Check the padding size for the padding frag. */ | |
12091 | padding_size = i386_branch_padding_size | |
12092 | (padding_fragP, (fragP->fr_address | |
12093 | + fragP->tc_frag_data.padding_address)); | |
12094 | ||
12095 | last_size = fragP->tc_frag_data.prefix_length; | |
12096 | /* Check if there is change from the last interation. */ | |
12097 | if (padding_size == last_size) | |
12098 | { | |
12099 | /* Update the expected address of the padding frag. */ | |
12100 | padding_fragP->tc_frag_data.padding_address | |
12101 | = (fragP->fr_address + padding_size | |
12102 | + fragP->tc_frag_data.padding_address); | |
12103 | return 0; | |
12104 | } | |
12105 | ||
12106 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
12107 | { | |
12108 | /* No padding if there is no sufficient room. Clear the | |
12109 | expected address of the padding frag. */ | |
12110 | padding_fragP->tc_frag_data.padding_address = 0; | |
12111 | padding_size = 0; | |
12112 | } | |
12113 | else | |
12114 | /* Store the expected address of the padding frag. */ | |
12115 | padding_fragP->tc_frag_data.padding_address | |
12116 | = (fragP->fr_address + padding_size | |
12117 | + fragP->tc_frag_data.padding_address); | |
12118 | ||
12119 | fragP->tc_frag_data.prefix_length = padding_size; | |
12120 | ||
12121 | /* Update the length for the current interation. */ | |
12122 | left_size = padding_size; | |
12123 | for (next_fragP = fragP; | |
12124 | next_fragP != padding_fragP; | |
12125 | next_fragP = next_fragP->fr_next) | |
12126 | if (next_fragP->fr_type == rs_machine_dependent | |
12127 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
12128 | == BRANCH_PREFIX)) | |
12129 | { | |
12130 | if (left_size) | |
12131 | { | |
12132 | int max = next_fragP->tc_frag_data.max_bytes; | |
12133 | if (max) | |
12134 | { | |
12135 | int size; | |
12136 | if (max > left_size) | |
12137 | size = left_size; | |
12138 | else | |
12139 | size = max; | |
12140 | left_size -= size; | |
12141 | next_fragP->tc_frag_data.length = size; | |
12142 | } | |
12143 | } | |
12144 | else | |
12145 | next_fragP->tc_frag_data.length = 0; | |
12146 | } | |
12147 | ||
12148 | return (fragP->tc_frag_data.length | |
12149 | - fragP->tc_frag_data.last_length); | |
12150 | } | |
12151 | return relax_frag (segment, fragP, stretch); | |
12152 | } | |
12153 | ||
ee7fcc42 AM |
12154 | /* md_estimate_size_before_relax() |
12155 | ||
12156 | Called just before relax() for rs_machine_dependent frags. The x86 | |
12157 | assembler uses these frags to handle variable size jump | |
12158 | instructions. | |
12159 | ||
12160 | Any symbol that is now undefined will not become defined. | |
12161 | Return the correct fr_subtype in the frag. | |
12162 | Return the initial "guess for variable size of frag" to caller. | |
12163 | The guess is actually the growth beyond the fixed part. Whatever | |
12164 | we do to grow the fixed or variable part contributes to our | |
12165 | returned value. */ | |
12166 | ||
252b5132 | 12167 | int |
7016a5d5 | 12168 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 12169 | { |
e379e5f3 L |
12170 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12171 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
12172 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
12173 | { | |
12174 | i386_classify_machine_dependent_frag (fragP); | |
12175 | return fragP->tc_frag_data.length; | |
12176 | } | |
12177 | ||
252b5132 | 12178 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
12179 | check for un-relaxable symbols. On an ELF system, we can't relax |
12180 | an externally visible symbol, because it may be overridden by a | |
12181 | shared library. */ | |
12182 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 12183 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12184 | || (IS_ELF |
8dcea932 L |
12185 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
12186 | fragP->fr_var)) | |
fbeb56a4 DK |
12187 | #endif |
12188 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 12189 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 12190 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
12191 | #endif |
12192 | ) | |
252b5132 | 12193 | { |
b98ef147 AM |
12194 | /* Symbol is undefined in this segment, or we need to keep a |
12195 | reloc so that weak symbols can be overridden. */ | |
12196 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 12197 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
12198 | unsigned char *opcode; |
12199 | int old_fr_fix; | |
eb19308f | 12200 | fixS *fixP = NULL; |
f6af82bd | 12201 | |
ee7fcc42 | 12202 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 12203 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 12204 | else if (size == 2) |
f6af82bd | 12205 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b L |
12206 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12207 | else if (need_plt32_p (fragP->fr_symbol)) | |
12208 | reloc_type = BFD_RELOC_X86_64_PLT32; | |
12209 | #endif | |
f6af82bd AM |
12210 | else |
12211 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 12212 | |
ee7fcc42 AM |
12213 | old_fr_fix = fragP->fr_fix; |
12214 | opcode = (unsigned char *) fragP->fr_opcode; | |
12215 | ||
fddf5b5b | 12216 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 12217 | { |
fddf5b5b AM |
12218 | case UNCOND_JUMP: |
12219 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 12220 | opcode[0] = 0xe9; |
252b5132 | 12221 | fragP->fr_fix += size; |
eb19308f JB |
12222 | fixP = fix_new (fragP, old_fr_fix, size, |
12223 | fragP->fr_symbol, | |
12224 | fragP->fr_offset, 1, | |
12225 | reloc_type); | |
252b5132 RH |
12226 | break; |
12227 | ||
fddf5b5b | 12228 | case COND_JUMP86: |
412167cb AM |
12229 | if (size == 2 |
12230 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
12231 | { |
12232 | /* Negate the condition, and branch past an | |
12233 | unconditional jump. */ | |
12234 | opcode[0] ^= 1; | |
12235 | opcode[1] = 3; | |
12236 | /* Insert an unconditional jump. */ | |
12237 | opcode[2] = 0xe9; | |
12238 | /* We added two extra opcode bytes, and have a two byte | |
12239 | offset. */ | |
12240 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
12241 | fix_new (fragP, old_fr_fix + 2, 2, |
12242 | fragP->fr_symbol, | |
12243 | fragP->fr_offset, 1, | |
12244 | reloc_type); | |
fddf5b5b AM |
12245 | break; |
12246 | } | |
12247 | /* Fall through. */ | |
12248 | ||
12249 | case COND_JUMP: | |
412167cb AM |
12250 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
12251 | { | |
12252 | fragP->fr_fix += 1; | |
3e02c1cc AM |
12253 | fixP = fix_new (fragP, old_fr_fix, 1, |
12254 | fragP->fr_symbol, | |
12255 | fragP->fr_offset, 1, | |
12256 | BFD_RELOC_8_PCREL); | |
12257 | fixP->fx_signed = 1; | |
412167cb AM |
12258 | break; |
12259 | } | |
93c2a809 | 12260 | |
24eab124 | 12261 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 12262 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 12263 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 12264 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
12265 | /* We've added an opcode byte. */ |
12266 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
12267 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
12268 | fragP->fr_symbol, | |
12269 | fragP->fr_offset, 1, | |
12270 | reloc_type); | |
252b5132 | 12271 | break; |
fddf5b5b AM |
12272 | |
12273 | default: | |
12274 | BAD_CASE (fragP->fr_subtype); | |
12275 | break; | |
252b5132 | 12276 | } |
eb19308f JB |
12277 | |
12278 | /* All jumps handled here are signed, but don't unconditionally use a | |
12279 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
12280 | around at 4G (outside of 64-bit mode) and 64k. */ | |
12281 | if (size == 4 && flag_code == CODE_64BIT) | |
12282 | fixP->fx_signed = 1; | |
12283 | ||
252b5132 | 12284 | frag_wane (fragP); |
ee7fcc42 | 12285 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 12286 | } |
93c2a809 | 12287 | |
93c2a809 AM |
12288 | /* Guess size depending on current relax state. Initially the relax |
12289 | state will correspond to a short jump and we return 1, because | |
12290 | the variable part of the frag (the branch offset) is one byte | |
12291 | long. However, we can relax a section more than once and in that | |
12292 | case we must either set fr_subtype back to the unrelaxed state, | |
12293 | or return the value for the appropriate branch. */ | |
12294 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
12295 | } |
12296 | ||
47926f60 KH |
12297 | /* Called after relax() is finished. |
12298 | ||
12299 | In: Address of frag. | |
12300 | fr_type == rs_machine_dependent. | |
12301 | fr_subtype is what the address relaxed to. | |
12302 | ||
12303 | Out: Any fixSs and constants are set up. | |
12304 | Caller will turn frag into a ".space 0". */ | |
12305 | ||
252b5132 | 12306 | void |
7016a5d5 TG |
12307 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
12308 | fragS *fragP) | |
252b5132 | 12309 | { |
29b0f896 | 12310 | unsigned char *opcode; |
252b5132 | 12311 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
12312 | offsetT target_address; |
12313 | offsetT opcode_address; | |
252b5132 | 12314 | unsigned int extension = 0; |
847f7ad4 | 12315 | offsetT displacement_from_opcode_start; |
252b5132 | 12316 | |
e379e5f3 L |
12317 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
12318 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
12319 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12320 | { | |
12321 | /* Generate nop padding. */ | |
12322 | unsigned int size = fragP->tc_frag_data.length; | |
12323 | if (size) | |
12324 | { | |
12325 | if (size > fragP->tc_frag_data.max_bytes) | |
12326 | abort (); | |
12327 | ||
12328 | if (flag_debug) | |
12329 | { | |
12330 | const char *msg; | |
12331 | const char *branch = "branch"; | |
12332 | const char *prefix = ""; | |
12333 | fragS *padding_fragP; | |
12334 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
12335 | == BRANCH_PREFIX) | |
12336 | { | |
12337 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
12338 | switch (fragP->tc_frag_data.default_prefix) | |
12339 | { | |
12340 | default: | |
12341 | abort (); | |
12342 | break; | |
12343 | case CS_PREFIX_OPCODE: | |
12344 | prefix = " cs"; | |
12345 | break; | |
12346 | case DS_PREFIX_OPCODE: | |
12347 | prefix = " ds"; | |
12348 | break; | |
12349 | case ES_PREFIX_OPCODE: | |
12350 | prefix = " es"; | |
12351 | break; | |
12352 | case FS_PREFIX_OPCODE: | |
12353 | prefix = " fs"; | |
12354 | break; | |
12355 | case GS_PREFIX_OPCODE: | |
12356 | prefix = " gs"; | |
12357 | break; | |
12358 | case SS_PREFIX_OPCODE: | |
12359 | prefix = " ss"; | |
12360 | break; | |
12361 | } | |
12362 | if (padding_fragP) | |
12363 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
12364 | "%s within %d-byte boundary\n"); | |
12365 | else | |
12366 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
12367 | "align %s within %d-byte boundary\n"); | |
12368 | } | |
12369 | else | |
12370 | { | |
12371 | padding_fragP = fragP; | |
12372 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
12373 | "%s within %d-byte boundary\n"); | |
12374 | } | |
12375 | ||
12376 | if (padding_fragP) | |
12377 | switch (padding_fragP->tc_frag_data.branch_type) | |
12378 | { | |
12379 | case align_branch_jcc: | |
12380 | branch = "jcc"; | |
12381 | break; | |
12382 | case align_branch_fused: | |
12383 | branch = "fused jcc"; | |
12384 | break; | |
12385 | case align_branch_jmp: | |
12386 | branch = "jmp"; | |
12387 | break; | |
12388 | case align_branch_call: | |
12389 | branch = "call"; | |
12390 | break; | |
12391 | case align_branch_indirect: | |
12392 | branch = "indiret branch"; | |
12393 | break; | |
12394 | case align_branch_ret: | |
12395 | branch = "ret"; | |
12396 | break; | |
12397 | default: | |
12398 | break; | |
12399 | } | |
12400 | ||
12401 | fprintf (stdout, msg, | |
12402 | fragP->fr_file, fragP->fr_line, size, prefix, | |
12403 | (long long) fragP->fr_address, branch, | |
12404 | 1 << align_branch_power); | |
12405 | } | |
12406 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
12407 | memset (fragP->fr_opcode, | |
12408 | fragP->tc_frag_data.default_prefix, size); | |
12409 | else | |
12410 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
12411 | size, 0); | |
12412 | fragP->fr_fix += size; | |
12413 | } | |
12414 | return; | |
12415 | } | |
12416 | ||
252b5132 RH |
12417 | opcode = (unsigned char *) fragP->fr_opcode; |
12418 | ||
47926f60 | 12419 | /* Address we want to reach in file space. */ |
252b5132 | 12420 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 12421 | |
47926f60 | 12422 | /* Address opcode resides at in file space. */ |
252b5132 RH |
12423 | opcode_address = fragP->fr_address + fragP->fr_fix; |
12424 | ||
47926f60 | 12425 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
12426 | displacement_from_opcode_start = target_address - opcode_address; |
12427 | ||
fddf5b5b | 12428 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 12429 | { |
47926f60 KH |
12430 | /* Don't have to change opcode. */ |
12431 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 12432 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
12433 | } |
12434 | else | |
12435 | { | |
12436 | if (no_cond_jump_promotion | |
12437 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
12438 | as_warn_where (fragP->fr_file, fragP->fr_line, |
12439 | _("long jump required")); | |
252b5132 | 12440 | |
fddf5b5b AM |
12441 | switch (fragP->fr_subtype) |
12442 | { | |
12443 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
12444 | extension = 4; /* 1 opcode + 4 displacement */ | |
12445 | opcode[0] = 0xe9; | |
12446 | where_to_put_displacement = &opcode[1]; | |
12447 | break; | |
252b5132 | 12448 | |
fddf5b5b AM |
12449 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
12450 | extension = 2; /* 1 opcode + 2 displacement */ | |
12451 | opcode[0] = 0xe9; | |
12452 | where_to_put_displacement = &opcode[1]; | |
12453 | break; | |
252b5132 | 12454 | |
fddf5b5b AM |
12455 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
12456 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
12457 | extension = 5; /* 2 opcode + 4 displacement */ | |
12458 | opcode[1] = opcode[0] + 0x10; | |
12459 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12460 | where_to_put_displacement = &opcode[2]; | |
12461 | break; | |
252b5132 | 12462 | |
fddf5b5b AM |
12463 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
12464 | extension = 3; /* 2 opcode + 2 displacement */ | |
12465 | opcode[1] = opcode[0] + 0x10; | |
12466 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
12467 | where_to_put_displacement = &opcode[2]; | |
12468 | break; | |
252b5132 | 12469 | |
fddf5b5b AM |
12470 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
12471 | extension = 4; | |
12472 | opcode[0] ^= 1; | |
12473 | opcode[1] = 3; | |
12474 | opcode[2] = 0xe9; | |
12475 | where_to_put_displacement = &opcode[3]; | |
12476 | break; | |
12477 | ||
12478 | default: | |
12479 | BAD_CASE (fragP->fr_subtype); | |
12480 | break; | |
12481 | } | |
252b5132 | 12482 | } |
fddf5b5b | 12483 | |
7b81dfbb AJ |
12484 | /* If size if less then four we are sure that the operand fits, |
12485 | but if it's 4, then it could be that the displacement is larger | |
12486 | then -/+ 2GB. */ | |
12487 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
12488 | && object_64bit | |
12489 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
12490 | + ((addressT) 1 << 31)) |
12491 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
12492 | { |
12493 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
12494 | _("jump target out of range")); | |
12495 | /* Make us emit 0. */ | |
12496 | displacement_from_opcode_start = extension; | |
12497 | } | |
47926f60 | 12498 | /* Now put displacement after opcode. */ |
252b5132 RH |
12499 | md_number_to_chars ((char *) where_to_put_displacement, |
12500 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 12501 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
12502 | fragP->fr_fix += extension; |
12503 | } | |
12504 | \f | |
7016a5d5 | 12505 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
12506 | by our caller that we have all the info we need to fix it up. |
12507 | ||
7016a5d5 TG |
12508 | Parameter valP is the pointer to the value of the bits. |
12509 | ||
252b5132 RH |
12510 | On the 386, immediates, displacements, and data pointers are all in |
12511 | the same (little-endian) format, so we don't need to care about which | |
12512 | we are handling. */ | |
12513 | ||
94f592af | 12514 | void |
7016a5d5 | 12515 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 12516 | { |
94f592af | 12517 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 12518 | valueT value = *valP; |
252b5132 | 12519 | |
f86103b7 | 12520 | #if !defined (TE_Mach) |
93382f6d AM |
12521 | if (fixP->fx_pcrel) |
12522 | { | |
12523 | switch (fixP->fx_r_type) | |
12524 | { | |
5865bb77 ILT |
12525 | default: |
12526 | break; | |
12527 | ||
d6ab8113 JB |
12528 | case BFD_RELOC_64: |
12529 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
12530 | break; | |
93382f6d | 12531 | case BFD_RELOC_32: |
ae8887b5 | 12532 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
12533 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
12534 | break; | |
12535 | case BFD_RELOC_16: | |
12536 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
12537 | break; | |
12538 | case BFD_RELOC_8: | |
12539 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
12540 | break; | |
12541 | } | |
12542 | } | |
252b5132 | 12543 | |
a161fe53 | 12544 | if (fixP->fx_addsy != NULL |
31312f95 | 12545 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 12546 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 12547 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 12548 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 12549 | && !use_rela_relocations) |
252b5132 | 12550 | { |
31312f95 AM |
12551 | /* This is a hack. There should be a better way to handle this. |
12552 | This covers for the fact that bfd_install_relocation will | |
12553 | subtract the current location (for partial_inplace, PC relative | |
12554 | relocations); see more below. */ | |
252b5132 | 12555 | #ifndef OBJ_AOUT |
718ddfc0 | 12556 | if (IS_ELF |
252b5132 RH |
12557 | #ifdef TE_PE |
12558 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
12559 | #endif | |
12560 | ) | |
12561 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12562 | #endif | |
12563 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 12564 | if (IS_ELF) |
252b5132 | 12565 | { |
6539b54b | 12566 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 12567 | |
6539b54b | 12568 | if ((sym_seg == seg |
2f66722d | 12569 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 12570 | && sym_seg != absolute_section)) |
af65af87 | 12571 | && !generic_force_reloc (fixP)) |
2f66722d AM |
12572 | { |
12573 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
12574 | bfd_install_relocation subtracts them out again. I think |
12575 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
12576 | it. FIXME. */ |
12577 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
12578 | } | |
252b5132 RH |
12579 | } |
12580 | #endif | |
12581 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
12582 | /* For some reason, the PE format does not store a |
12583 | section address offset for a PC relative symbol. */ | |
12584 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 12585 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
12586 | value += md_pcrel_from (fixP); |
12587 | #endif | |
12588 | } | |
fbeb56a4 | 12589 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
12590 | if (fixP->fx_addsy != NULL |
12591 | && S_IS_WEAK (fixP->fx_addsy) | |
12592 | /* PR 16858: Do not modify weak function references. */ | |
12593 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 12594 | { |
296a8689 NC |
12595 | #if !defined (TE_PEP) |
12596 | /* For x86 PE weak function symbols are neither PC-relative | |
12597 | nor do they set S_IS_FUNCTION. So the only reliable way | |
12598 | to detect them is to check the flags of their containing | |
12599 | section. */ | |
12600 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
12601 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
12602 | ; | |
12603 | else | |
12604 | #endif | |
fbeb56a4 DK |
12605 | value -= S_GET_VALUE (fixP->fx_addsy); |
12606 | } | |
12607 | #endif | |
252b5132 RH |
12608 | |
12609 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 12610 | and we must not disappoint it. */ |
252b5132 | 12611 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 12612 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
12613 | switch (fixP->fx_r_type) |
12614 | { | |
12615 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 12616 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
12617 | /* Make the jump instruction point to the address of the operand. |
12618 | At runtime we merely add the offset to the actual PLT entry. | |
12619 | NB: Subtract the offset size only for jump instructions. */ | |
12620 | if (fixP->fx_pcrel) | |
12621 | value = -4; | |
47926f60 | 12622 | break; |
31312f95 | 12623 | |
13ae64f3 JJ |
12624 | case BFD_RELOC_386_TLS_GD: |
12625 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 12626 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
12627 | case BFD_RELOC_386_TLS_IE: |
12628 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 12629 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
12630 | case BFD_RELOC_X86_64_TLSGD: |
12631 | case BFD_RELOC_X86_64_TLSLD: | |
12632 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 12633 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
12634 | value = 0; /* Fully resolved at runtime. No addend. */ |
12635 | /* Fallthrough */ | |
12636 | case BFD_RELOC_386_TLS_LE: | |
12637 | case BFD_RELOC_386_TLS_LDO_32: | |
12638 | case BFD_RELOC_386_TLS_LE_32: | |
12639 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 12640 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 12641 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 12642 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
12643 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
12644 | break; | |
12645 | ||
67a4f2b7 AO |
12646 | case BFD_RELOC_386_TLS_DESC_CALL: |
12647 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
12648 | value = 0; /* Fully resolved at runtime. No addend. */ | |
12649 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
12650 | fixP->fx_done = 0; | |
12651 | return; | |
12652 | ||
47926f60 KH |
12653 | case BFD_RELOC_VTABLE_INHERIT: |
12654 | case BFD_RELOC_VTABLE_ENTRY: | |
12655 | fixP->fx_done = 0; | |
94f592af | 12656 | return; |
47926f60 KH |
12657 | |
12658 | default: | |
12659 | break; | |
12660 | } | |
12661 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
c6682705 | 12662 | *valP = value; |
f86103b7 | 12663 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 12664 | |
3e73aa7c | 12665 | /* Are we finished with this relocation now? */ |
c6682705 | 12666 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
12667 | { |
12668 | fixP->fx_done = 1; | |
12669 | switch (fixP->fx_r_type) | |
12670 | { | |
12671 | case BFD_RELOC_X86_64_32S: | |
12672 | fixP->fx_signed = 1; | |
12673 | break; | |
12674 | ||
12675 | default: | |
12676 | break; | |
12677 | } | |
12678 | } | |
fbeb56a4 DK |
12679 | #if defined (OBJ_COFF) && defined (TE_PE) |
12680 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
12681 | { | |
12682 | fixP->fx_done = 0; | |
12683 | /* Remember value for tc_gen_reloc. */ | |
12684 | fixP->fx_addnumber = value; | |
12685 | /* Clear out the frag for now. */ | |
12686 | value = 0; | |
12687 | } | |
12688 | #endif | |
3e73aa7c JH |
12689 | else if (use_rela_relocations) |
12690 | { | |
12691 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
12692 | /* Remember value for tc_gen_reloc. */ |
12693 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
12694 | value = 0; |
12695 | } | |
f86103b7 | 12696 | |
94f592af | 12697 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 12698 | } |
252b5132 | 12699 | \f |
6d4af3c2 | 12700 | const char * |
499ac353 | 12701 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 12702 | { |
499ac353 NC |
12703 | /* This outputs the LITTLENUMs in REVERSE order; |
12704 | in accord with the bigendian 386. */ | |
5b7c81bd | 12705 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
12706 | } |
12707 | \f | |
2d545b82 | 12708 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 12709 | |
252b5132 | 12710 | static char * |
e3bb37b5 | 12711 | output_invalid (int c) |
252b5132 | 12712 | { |
3882b010 | 12713 | if (ISPRINT (c)) |
f9f21a03 L |
12714 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
12715 | "'%c'", c); | |
252b5132 | 12716 | else |
f9f21a03 | 12717 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 12718 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
12719 | return output_invalid_buf; |
12720 | } | |
12721 | ||
8a6fb3f9 JB |
12722 | /* Verify that @r can be used in the current context. */ |
12723 | ||
5b7c81bd | 12724 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
12725 | { |
12726 | if (allow_pseudo_reg) | |
5b7c81bd | 12727 | return true; |
8a6fb3f9 JB |
12728 | |
12729 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 12730 | return false; |
8a6fb3f9 JB |
12731 | |
12732 | if ((r->reg_type.bitfield.dword | |
12733 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
12734 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 12735 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 12736 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 12737 | return false; |
8a6fb3f9 | 12738 | |
22e00a3f JB |
12739 | if (r->reg_type.bitfield.class == RegTR |
12740 | && (flag_code == CODE_64BIT | |
12741 | || !cpu_arch_flags.bitfield.cpui386 | |
12742 | || cpu_arch_isa_flags.bitfield.cpui586 | |
12743 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 12744 | return false; |
22e00a3f | 12745 | |
8a6fb3f9 | 12746 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 12747 | return false; |
8a6fb3f9 JB |
12748 | |
12749 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
12750 | { | |
12751 | if (r->reg_type.bitfield.zmmword | |
12752 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 12753 | return false; |
8a6fb3f9 JB |
12754 | |
12755 | if (!cpu_arch_flags.bitfield.cpuavx) | |
12756 | { | |
12757 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 12758 | return false; |
8a6fb3f9 JB |
12759 | |
12760 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 12761 | return false; |
8a6fb3f9 JB |
12762 | } |
12763 | } | |
12764 | ||
260cd341 LC |
12765 | if (r->reg_type.bitfield.tmmword |
12766 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
12767 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 12768 | return false; |
260cd341 | 12769 | |
8a6fb3f9 | 12770 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 12771 | return false; |
8a6fb3f9 JB |
12772 | |
12773 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
12774 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 12775 | return false; |
8a6fb3f9 JB |
12776 | |
12777 | /* Upper 16 vector registers are only available with VREX in 64bit | |
12778 | mode, and require EVEX encoding. */ | |
12779 | if (r->reg_flags & RegVRex) | |
12780 | { | |
12781 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
12782 | || flag_code != CODE_64BIT) | |
5b7c81bd | 12783 | return false; |
8a6fb3f9 | 12784 | |
da4977e0 JB |
12785 | if (i.vec_encoding == vex_encoding_default) |
12786 | i.vec_encoding = vex_encoding_evex; | |
12787 | else if (i.vec_encoding != vex_encoding_evex) | |
12788 | i.vec_encoding = vex_encoding_error; | |
8a6fb3f9 JB |
12789 | } |
12790 | ||
12791 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) | |
12792 | && (!cpu_arch_flags.bitfield.cpulm || r->reg_type.bitfield.class != RegCR) | |
12793 | && flag_code != CODE_64BIT) | |
5b7c81bd | 12794 | return false; |
8a6fb3f9 JB |
12795 | |
12796 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
12797 | && !intel_syntax) | |
5b7c81bd | 12798 | return false; |
8a6fb3f9 | 12799 | |
5b7c81bd | 12800 | return true; |
8a6fb3f9 JB |
12801 | } |
12802 | ||
af6bdddf | 12803 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
12804 | |
12805 | static const reg_entry * | |
4d1bb795 | 12806 | parse_real_register (char *reg_string, char **end_op) |
252b5132 | 12807 | { |
af6bdddf AM |
12808 | char *s = reg_string; |
12809 | char *p; | |
252b5132 RH |
12810 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
12811 | const reg_entry *r; | |
12812 | ||
12813 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
12814 | if (*s == REGISTER_PREFIX) | |
12815 | ++s; | |
12816 | ||
12817 | if (is_space_char (*s)) | |
12818 | ++s; | |
12819 | ||
12820 | p = reg_name_given; | |
af6bdddf | 12821 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
12822 | { |
12823 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
12824 | return (const reg_entry *) NULL; |
12825 | s++; | |
252b5132 RH |
12826 | } |
12827 | ||
6588847e DN |
12828 | /* For naked regs, make sure that we are not dealing with an identifier. |
12829 | This prevents confusing an identifier like `eax_var' with register | |
12830 | `eax'. */ | |
12831 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) | |
12832 | return (const reg_entry *) NULL; | |
12833 | ||
af6bdddf | 12834 | *end_op = s; |
252b5132 | 12835 | |
629310ab | 12836 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 12837 | |
5f47d35b | 12838 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 12839 | if (r == reg_st0) |
5f47d35b | 12840 | { |
0e0eea78 JB |
12841 | if (!cpu_arch_flags.bitfield.cpu8087 |
12842 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
12843 | && !cpu_arch_flags.bitfield.cpu387 |
12844 | && !allow_pseudo_reg) | |
0e0eea78 JB |
12845 | return (const reg_entry *) NULL; |
12846 | ||
5f47d35b AM |
12847 | if (is_space_char (*s)) |
12848 | ++s; | |
12849 | if (*s == '(') | |
12850 | { | |
af6bdddf | 12851 | ++s; |
5f47d35b AM |
12852 | if (is_space_char (*s)) |
12853 | ++s; | |
12854 | if (*s >= '0' && *s <= '7') | |
12855 | { | |
db557034 | 12856 | int fpr = *s - '0'; |
af6bdddf | 12857 | ++s; |
5f47d35b AM |
12858 | if (is_space_char (*s)) |
12859 | ++s; | |
12860 | if (*s == ')') | |
12861 | { | |
12862 | *end_op = s + 1; | |
6288d05f | 12863 | know (r[fpr].reg_num == fpr); |
db557034 | 12864 | return r + fpr; |
5f47d35b | 12865 | } |
5f47d35b | 12866 | } |
47926f60 | 12867 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
12868 | return (const reg_entry *) NULL; |
12869 | } | |
12870 | } | |
12871 | ||
8a6fb3f9 | 12872 | return r && check_register (r) ? r : NULL; |
252b5132 | 12873 | } |
4d1bb795 JB |
12874 | |
12875 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
12876 | ||
12877 | static const reg_entry * | |
12878 | parse_register (char *reg_string, char **end_op) | |
12879 | { | |
12880 | const reg_entry *r; | |
12881 | ||
12882 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
12883 | r = parse_real_register (reg_string, end_op); | |
12884 | else | |
12885 | r = NULL; | |
12886 | if (!r) | |
12887 | { | |
12888 | char *save = input_line_pointer; | |
12889 | char c; | |
12890 | symbolS *symbolP; | |
12891 | ||
12892 | input_line_pointer = reg_string; | |
d02603dc | 12893 | c = get_symbol_name (®_string); |
4d1bb795 JB |
12894 | symbolP = symbol_find (reg_string); |
12895 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) | |
12896 | { | |
12897 | const expressionS *e = symbol_get_value_expression (symbolP); | |
12898 | ||
0398aac5 | 12899 | know (e->X_op == O_register); |
4eed87de | 12900 | know (e->X_add_number >= 0 |
c3fe08fa | 12901 | && (valueT) e->X_add_number < i386_regtab_size); |
4d1bb795 | 12902 | r = i386_regtab + e->X_add_number; |
8a6fb3f9 JB |
12903 | if (!check_register (r)) |
12904 | { | |
12905 | as_bad (_("register '%s%s' cannot be used here"), | |
12906 | register_prefix, r->reg_name); | |
12907 | r = &bad_reg; | |
12908 | } | |
4d1bb795 JB |
12909 | *end_op = input_line_pointer; |
12910 | } | |
12911 | *input_line_pointer = c; | |
12912 | input_line_pointer = save; | |
12913 | } | |
12914 | return r; | |
12915 | } | |
12916 | ||
12917 | int | |
12918 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
12919 | { | |
12920 | const reg_entry *r; | |
12921 | char *end = input_line_pointer; | |
12922 | ||
12923 | *end = *nextcharP; | |
12924 | r = parse_register (name, &input_line_pointer); | |
12925 | if (r && end <= input_line_pointer) | |
12926 | { | |
12927 | *nextcharP = *input_line_pointer; | |
12928 | *input_line_pointer = 0; | |
8a6fb3f9 JB |
12929 | if (r != &bad_reg) |
12930 | { | |
12931 | e->X_op = O_register; | |
12932 | e->X_add_number = r - i386_regtab; | |
12933 | } | |
12934 | else | |
12935 | e->X_op = O_illegal; | |
4d1bb795 JB |
12936 | return 1; |
12937 | } | |
12938 | input_line_pointer = end; | |
12939 | *end = 0; | |
ee86248c | 12940 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
12941 | } |
12942 | ||
12943 | void | |
12944 | md_operand (expressionS *e) | |
12945 | { | |
ee86248c JB |
12946 | char *end; |
12947 | const reg_entry *r; | |
4d1bb795 | 12948 | |
ee86248c JB |
12949 | switch (*input_line_pointer) |
12950 | { | |
12951 | case REGISTER_PREFIX: | |
12952 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
12953 | if (r) |
12954 | { | |
12955 | e->X_op = O_register; | |
12956 | e->X_add_number = r - i386_regtab; | |
12957 | input_line_pointer = end; | |
12958 | } | |
ee86248c JB |
12959 | break; |
12960 | ||
12961 | case '[': | |
9c2799c2 | 12962 | gas_assert (intel_syntax); |
ee86248c JB |
12963 | end = input_line_pointer++; |
12964 | expression (e); | |
12965 | if (*input_line_pointer == ']') | |
12966 | { | |
12967 | ++input_line_pointer; | |
12968 | e->X_op_symbol = make_expr_symbol (e); | |
12969 | e->X_add_symbol = NULL; | |
12970 | e->X_add_number = 0; | |
12971 | e->X_op = O_index; | |
12972 | } | |
12973 | else | |
12974 | { | |
12975 | e->X_op = O_absent; | |
12976 | input_line_pointer = end; | |
12977 | } | |
12978 | break; | |
4d1bb795 JB |
12979 | } |
12980 | } | |
12981 | ||
252b5132 | 12982 | \f |
4cc782b5 | 12983 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 12984 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 12985 | #else |
b6f8c7c4 | 12986 | const char *md_shortopts = "qnO::"; |
252b5132 | 12987 | #endif |
6e0b89ee | 12988 | |
3e73aa7c | 12989 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
12990 | #define OPTION_64 (OPTION_MD_BASE + 1) |
12991 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
12992 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
12993 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
12994 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
12995 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
12996 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
12997 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 12998 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 12999 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 13000 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
13001 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
13002 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
13003 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 13004 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
13005 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
13006 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 13007 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 13008 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 13009 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 13010 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
13011 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
13012 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 13013 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 13014 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 13015 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
13016 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
13017 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
13018 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 13019 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
13020 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
13021 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
13022 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
b3b91714 | 13023 | |
99ad8390 NC |
13024 | struct option md_longopts[] = |
13025 | { | |
3e73aa7c | 13026 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 13027 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13028 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 13029 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
13030 | #endif |
13031 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 13032 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 13033 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 13034 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 13035 | #endif |
b3b91714 | 13036 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
13037 | {"march", required_argument, NULL, OPTION_MARCH}, |
13038 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
13039 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
13040 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
13041 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
13042 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 13043 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
daf50ae7 | 13044 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 13045 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 13046 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 13047 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 13048 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
13049 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
13050 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
13051 | # if defined (TE_PE) || defined (TE_PEP) |
13052 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
13053 | #endif | |
d1982f93 | 13054 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 13055 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 13056 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 13057 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
13058 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
13059 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
13060 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 13061 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
13062 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
13063 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
13064 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
13065 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
13066 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
13067 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
13068 | {NULL, no_argument, NULL, 0} |
13069 | }; | |
13070 | size_t md_longopts_size = sizeof (md_longopts); | |
13071 | ||
13072 | int | |
17b9d67d | 13073 | md_parse_option (int c, const char *arg) |
252b5132 | 13074 | { |
91d6fa6a | 13075 | unsigned int j; |
e379e5f3 | 13076 | char *arch, *next, *saved, *type; |
9103f4f4 | 13077 | |
252b5132 RH |
13078 | switch (c) |
13079 | { | |
12b55ccc L |
13080 | case 'n': |
13081 | optimize_align_code = 0; | |
13082 | break; | |
13083 | ||
a38cf1db AM |
13084 | case 'q': |
13085 | quiet_warnings = 1; | |
252b5132 RH |
13086 | break; |
13087 | ||
13088 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
13089 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
13090 | should be emitted or not. FIXME: Not implemented. */ | |
13091 | case 'Q': | |
d4693039 JB |
13092 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
13093 | return 0; | |
252b5132 RH |
13094 | break; |
13095 | ||
13096 | /* -V: SVR4 argument to print version ID. */ | |
13097 | case 'V': | |
13098 | print_version_id (); | |
13099 | break; | |
13100 | ||
a38cf1db AM |
13101 | /* -k: Ignore for FreeBSD compatibility. */ |
13102 | case 'k': | |
252b5132 | 13103 | break; |
4cc782b5 ILT |
13104 | |
13105 | case 's': | |
13106 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 13107 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 13108 | break; |
8dcea932 L |
13109 | |
13110 | case OPTION_MSHARED: | |
13111 | shared = 1; | |
13112 | break; | |
b4a3a7b4 L |
13113 | |
13114 | case OPTION_X86_USED_NOTE: | |
13115 | if (strcasecmp (arg, "yes") == 0) | |
13116 | x86_used_note = 1; | |
13117 | else if (strcasecmp (arg, "no") == 0) | |
13118 | x86_used_note = 0; | |
13119 | else | |
13120 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
13121 | break; | |
13122 | ||
13123 | ||
99ad8390 | 13124 | #endif |
321098a5 | 13125 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 13126 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
13127 | case OPTION_64: |
13128 | { | |
13129 | const char **list, **l; | |
13130 | ||
3e73aa7c JH |
13131 | list = bfd_target_list (); |
13132 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13133 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
13134 | || strcmp (*l, "coff-x86-64") == 0 |
13135 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
13136 | || strcmp (*l, "pei-x86-64") == 0 |
13137 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
13138 | { |
13139 | default_arch = "x86_64"; | |
13140 | break; | |
13141 | } | |
3e73aa7c | 13142 | if (*l == NULL) |
2b5d6a91 | 13143 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
13144 | free (list); |
13145 | } | |
13146 | break; | |
13147 | #endif | |
252b5132 | 13148 | |
351f65ca | 13149 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 13150 | case OPTION_X32: |
351f65ca L |
13151 | if (IS_ELF) |
13152 | { | |
13153 | const char **list, **l; | |
13154 | ||
13155 | list = bfd_target_list (); | |
13156 | for (l = list; *l != NULL; l++) | |
08dedd66 | 13157 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
13158 | { |
13159 | default_arch = "x86_64:32"; | |
13160 | break; | |
13161 | } | |
13162 | if (*l == NULL) | |
2b5d6a91 | 13163 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
13164 | free (list); |
13165 | } | |
13166 | else | |
13167 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
13168 | break; | |
13169 | #endif | |
13170 | ||
6e0b89ee AM |
13171 | case OPTION_32: |
13172 | default_arch = "i386"; | |
13173 | break; | |
13174 | ||
b3b91714 AM |
13175 | case OPTION_DIVIDE: |
13176 | #ifdef SVR4_COMMENT_CHARS | |
13177 | { | |
13178 | char *n, *t; | |
13179 | const char *s; | |
13180 | ||
add39d23 | 13181 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
13182 | t = n; |
13183 | for (s = i386_comment_chars; *s != '\0'; s++) | |
13184 | if (*s != '/') | |
13185 | *t++ = *s; | |
13186 | *t = '\0'; | |
13187 | i386_comment_chars = n; | |
13188 | } | |
13189 | #endif | |
13190 | break; | |
13191 | ||
9103f4f4 | 13192 | case OPTION_MARCH: |
293f5f65 L |
13193 | saved = xstrdup (arg); |
13194 | arch = saved; | |
13195 | /* Allow -march=+nosse. */ | |
13196 | if (*arch == '+') | |
13197 | arch++; | |
6305a203 | 13198 | do |
9103f4f4 | 13199 | { |
6305a203 | 13200 | if (*arch == '.') |
2b5d6a91 | 13201 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13202 | next = strchr (arch, '+'); |
13203 | if (next) | |
13204 | *next++ = '\0'; | |
91d6fa6a | 13205 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13206 | { |
91d6fa6a | 13207 | if (strcmp (arch, cpu_arch [j].name) == 0) |
ccc9c027 | 13208 | { |
6305a203 | 13209 | /* Processor. */ |
1ded5609 JB |
13210 | if (! cpu_arch[j].flags.bitfield.cpui386) |
13211 | continue; | |
13212 | ||
91d6fa6a | 13213 | cpu_arch_name = cpu_arch[j].name; |
6305a203 | 13214 | cpu_sub_arch_name = NULL; |
91d6fa6a NC |
13215 | cpu_arch_flags = cpu_arch[j].flags; |
13216 | cpu_arch_isa = cpu_arch[j].type; | |
13217 | cpu_arch_isa_flags = cpu_arch[j].flags; | |
6305a203 L |
13218 | if (!cpu_arch_tune_set) |
13219 | { | |
13220 | cpu_arch_tune = cpu_arch_isa; | |
13221 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13222 | } | |
13223 | break; | |
13224 | } | |
91d6fa6a NC |
13225 | else if (*cpu_arch [j].name == '.' |
13226 | && strcmp (arch, cpu_arch [j].name + 1) == 0) | |
6305a203 | 13227 | { |
33eaf5de | 13228 | /* ISA extension. */ |
6305a203 | 13229 | i386_cpu_flags flags; |
309d3373 | 13230 | |
293f5f65 L |
13231 | flags = cpu_flags_or (cpu_arch_flags, |
13232 | cpu_arch[j].flags); | |
81486035 | 13233 | |
5b64d091 | 13234 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 L |
13235 | { |
13236 | if (cpu_sub_arch_name) | |
13237 | { | |
13238 | char *name = cpu_sub_arch_name; | |
13239 | cpu_sub_arch_name = concat (name, | |
91d6fa6a | 13240 | cpu_arch[j].name, |
1bf57e9f | 13241 | (const char *) NULL); |
6305a203 L |
13242 | free (name); |
13243 | } | |
13244 | else | |
91d6fa6a | 13245 | cpu_sub_arch_name = xstrdup (cpu_arch[j].name); |
6305a203 | 13246 | cpu_arch_flags = flags; |
a586129e | 13247 | cpu_arch_isa_flags = flags; |
6305a203 | 13248 | } |
0089dace L |
13249 | else |
13250 | cpu_arch_isa_flags | |
13251 | = cpu_flags_or (cpu_arch_isa_flags, | |
13252 | cpu_arch[j].flags); | |
6305a203 | 13253 | break; |
ccc9c027 | 13254 | } |
9103f4f4 | 13255 | } |
6305a203 | 13256 | |
293f5f65 L |
13257 | if (j >= ARRAY_SIZE (cpu_arch)) |
13258 | { | |
33eaf5de | 13259 | /* Disable an ISA extension. */ |
293f5f65 L |
13260 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) |
13261 | if (strcmp (arch, cpu_noarch [j].name) == 0) | |
13262 | { | |
13263 | i386_cpu_flags flags; | |
13264 | ||
13265 | flags = cpu_flags_and_not (cpu_arch_flags, | |
13266 | cpu_noarch[j].flags); | |
13267 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
13268 | { | |
13269 | if (cpu_sub_arch_name) | |
13270 | { | |
13271 | char *name = cpu_sub_arch_name; | |
13272 | cpu_sub_arch_name = concat (arch, | |
13273 | (const char *) NULL); | |
13274 | free (name); | |
13275 | } | |
13276 | else | |
13277 | cpu_sub_arch_name = xstrdup (arch); | |
13278 | cpu_arch_flags = flags; | |
13279 | cpu_arch_isa_flags = flags; | |
13280 | } | |
13281 | break; | |
13282 | } | |
13283 | ||
13284 | if (j >= ARRAY_SIZE (cpu_noarch)) | |
13285 | j = ARRAY_SIZE (cpu_arch); | |
13286 | } | |
13287 | ||
91d6fa6a | 13288 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13289 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
13290 | |
13291 | arch = next; | |
9103f4f4 | 13292 | } |
293f5f65 L |
13293 | while (next != NULL); |
13294 | free (saved); | |
9103f4f4 L |
13295 | break; |
13296 | ||
13297 | case OPTION_MTUNE: | |
13298 | if (*arg == '.') | |
2b5d6a91 | 13299 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 13300 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 13301 | { |
91d6fa6a | 13302 | if (strcmp (arg, cpu_arch [j].name) == 0) |
9103f4f4 | 13303 | { |
ccc9c027 | 13304 | cpu_arch_tune_set = 1; |
91d6fa6a NC |
13305 | cpu_arch_tune = cpu_arch [j].type; |
13306 | cpu_arch_tune_flags = cpu_arch[j].flags; | |
9103f4f4 L |
13307 | break; |
13308 | } | |
13309 | } | |
91d6fa6a | 13310 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 13311 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
13312 | break; |
13313 | ||
1efbbeb4 L |
13314 | case OPTION_MMNEMONIC: |
13315 | if (strcasecmp (arg, "att") == 0) | |
13316 | intel_mnemonic = 0; | |
13317 | else if (strcasecmp (arg, "intel") == 0) | |
13318 | intel_mnemonic = 1; | |
13319 | else | |
2b5d6a91 | 13320 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
13321 | break; |
13322 | ||
13323 | case OPTION_MSYNTAX: | |
13324 | if (strcasecmp (arg, "att") == 0) | |
13325 | intel_syntax = 0; | |
13326 | else if (strcasecmp (arg, "intel") == 0) | |
13327 | intel_syntax = 1; | |
13328 | else | |
2b5d6a91 | 13329 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
13330 | break; |
13331 | ||
13332 | case OPTION_MINDEX_REG: | |
13333 | allow_index_reg = 1; | |
13334 | break; | |
13335 | ||
13336 | case OPTION_MNAKED_REG: | |
13337 | allow_naked_reg = 1; | |
13338 | break; | |
13339 | ||
c0f3af97 L |
13340 | case OPTION_MSSE2AVX: |
13341 | sse2avx = 1; | |
13342 | break; | |
13343 | ||
daf50ae7 L |
13344 | case OPTION_MSSE_CHECK: |
13345 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 13346 | sse_check = check_error; |
daf50ae7 | 13347 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 13348 | sse_check = check_warning; |
daf50ae7 | 13349 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 13350 | sse_check = check_none; |
daf50ae7 | 13351 | else |
2b5d6a91 | 13352 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
13353 | break; |
13354 | ||
7bab8ab5 JB |
13355 | case OPTION_MOPERAND_CHECK: |
13356 | if (strcasecmp (arg, "error") == 0) | |
13357 | operand_check = check_error; | |
13358 | else if (strcasecmp (arg, "warning") == 0) | |
13359 | operand_check = check_warning; | |
13360 | else if (strcasecmp (arg, "none") == 0) | |
13361 | operand_check = check_none; | |
13362 | else | |
13363 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
13364 | break; | |
13365 | ||
539f890d L |
13366 | case OPTION_MAVXSCALAR: |
13367 | if (strcasecmp (arg, "128") == 0) | |
13368 | avxscalar = vex128; | |
13369 | else if (strcasecmp (arg, "256") == 0) | |
13370 | avxscalar = vex256; | |
13371 | else | |
2b5d6a91 | 13372 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
13373 | break; |
13374 | ||
03751133 L |
13375 | case OPTION_MVEXWIG: |
13376 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 13377 | vexwig = vexw0; |
03751133 | 13378 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 13379 | vexwig = vexw1; |
03751133 L |
13380 | else |
13381 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
13382 | break; | |
13383 | ||
7e8b059b L |
13384 | case OPTION_MADD_BND_PREFIX: |
13385 | add_bnd_prefix = 1; | |
13386 | break; | |
13387 | ||
43234a1e L |
13388 | case OPTION_MEVEXLIG: |
13389 | if (strcmp (arg, "128") == 0) | |
13390 | evexlig = evexl128; | |
13391 | else if (strcmp (arg, "256") == 0) | |
13392 | evexlig = evexl256; | |
13393 | else if (strcmp (arg, "512") == 0) | |
13394 | evexlig = evexl512; | |
13395 | else | |
13396 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
13397 | break; | |
13398 | ||
d3d3c6db IT |
13399 | case OPTION_MEVEXRCIG: |
13400 | if (strcmp (arg, "rne") == 0) | |
13401 | evexrcig = rne; | |
13402 | else if (strcmp (arg, "rd") == 0) | |
13403 | evexrcig = rd; | |
13404 | else if (strcmp (arg, "ru") == 0) | |
13405 | evexrcig = ru; | |
13406 | else if (strcmp (arg, "rz") == 0) | |
13407 | evexrcig = rz; | |
13408 | else | |
13409 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
13410 | break; | |
13411 | ||
43234a1e L |
13412 | case OPTION_MEVEXWIG: |
13413 | if (strcmp (arg, "0") == 0) | |
13414 | evexwig = evexw0; | |
13415 | else if (strcmp (arg, "1") == 0) | |
13416 | evexwig = evexw1; | |
13417 | else | |
13418 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
13419 | break; | |
13420 | ||
167ad85b TG |
13421 | # if defined (TE_PE) || defined (TE_PEP) |
13422 | case OPTION_MBIG_OBJ: | |
13423 | use_big_obj = 1; | |
13424 | break; | |
13425 | #endif | |
13426 | ||
d1982f93 | 13427 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
13428 | if (strcasecmp (arg, "yes") == 0) |
13429 | omit_lock_prefix = 1; | |
13430 | else if (strcasecmp (arg, "no") == 0) | |
13431 | omit_lock_prefix = 0; | |
13432 | else | |
13433 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
13434 | break; | |
13435 | ||
e4e00185 AS |
13436 | case OPTION_MFENCE_AS_LOCK_ADD: |
13437 | if (strcasecmp (arg, "yes") == 0) | |
13438 | avoid_fence = 1; | |
13439 | else if (strcasecmp (arg, "no") == 0) | |
13440 | avoid_fence = 0; | |
13441 | else | |
13442 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
13443 | break; | |
13444 | ||
ae531041 L |
13445 | case OPTION_MLFENCE_AFTER_LOAD: |
13446 | if (strcasecmp (arg, "yes") == 0) | |
13447 | lfence_after_load = 1; | |
13448 | else if (strcasecmp (arg, "no") == 0) | |
13449 | lfence_after_load = 0; | |
13450 | else | |
13451 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
13452 | break; | |
13453 | ||
13454 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
13455 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 13456 | { |
13457 | lfence_before_indirect_branch = lfence_branch_all; | |
13458 | if (lfence_before_ret == lfence_before_ret_none) | |
13459 | lfence_before_ret = lfence_before_ret_shl; | |
13460 | } | |
ae531041 L |
13461 | else if (strcasecmp (arg, "memory") == 0) |
13462 | lfence_before_indirect_branch = lfence_branch_memory; | |
13463 | else if (strcasecmp (arg, "register") == 0) | |
13464 | lfence_before_indirect_branch = lfence_branch_register; | |
13465 | else if (strcasecmp (arg, "none") == 0) | |
13466 | lfence_before_indirect_branch = lfence_branch_none; | |
13467 | else | |
13468 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
13469 | arg); | |
13470 | break; | |
13471 | ||
13472 | case OPTION_MLFENCE_BEFORE_RET: | |
13473 | if (strcasecmp (arg, "or") == 0) | |
13474 | lfence_before_ret = lfence_before_ret_or; | |
13475 | else if (strcasecmp (arg, "not") == 0) | |
13476 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 13477 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
13478 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
13479 | else if (strcasecmp (arg, "none") == 0) |
13480 | lfence_before_ret = lfence_before_ret_none; | |
13481 | else | |
13482 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
13483 | arg); | |
13484 | break; | |
13485 | ||
0cb4071e L |
13486 | case OPTION_MRELAX_RELOCATIONS: |
13487 | if (strcasecmp (arg, "yes") == 0) | |
13488 | generate_relax_relocations = 1; | |
13489 | else if (strcasecmp (arg, "no") == 0) | |
13490 | generate_relax_relocations = 0; | |
13491 | else | |
13492 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
13493 | break; | |
13494 | ||
e379e5f3 L |
13495 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
13496 | { | |
13497 | char *end; | |
13498 | long int align = strtoul (arg, &end, 0); | |
13499 | if (*end == '\0') | |
13500 | { | |
13501 | if (align == 0) | |
13502 | { | |
13503 | align_branch_power = 0; | |
13504 | break; | |
13505 | } | |
13506 | else if (align >= 16) | |
13507 | { | |
13508 | int align_power; | |
13509 | for (align_power = 0; | |
13510 | (align & 1) == 0; | |
13511 | align >>= 1, align_power++) | |
13512 | continue; | |
13513 | /* Limit alignment power to 31. */ | |
13514 | if (align == 1 && align_power < 32) | |
13515 | { | |
13516 | align_branch_power = align_power; | |
13517 | break; | |
13518 | } | |
13519 | } | |
13520 | } | |
13521 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
13522 | } | |
13523 | break; | |
13524 | ||
13525 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
13526 | { | |
13527 | char *end; | |
13528 | int align = strtoul (arg, &end, 0); | |
13529 | /* Some processors only support 5 prefixes. */ | |
13530 | if (*end == '\0' && align >= 0 && align < 6) | |
13531 | { | |
13532 | align_branch_prefix_size = align; | |
13533 | break; | |
13534 | } | |
13535 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
13536 | arg); | |
13537 | } | |
13538 | break; | |
13539 | ||
13540 | case OPTION_MALIGN_BRANCH: | |
13541 | align_branch = 0; | |
13542 | saved = xstrdup (arg); | |
13543 | type = saved; | |
13544 | do | |
13545 | { | |
13546 | next = strchr (type, '+'); | |
13547 | if (next) | |
13548 | *next++ = '\0'; | |
13549 | if (strcasecmp (type, "jcc") == 0) | |
13550 | align_branch |= align_branch_jcc_bit; | |
13551 | else if (strcasecmp (type, "fused") == 0) | |
13552 | align_branch |= align_branch_fused_bit; | |
13553 | else if (strcasecmp (type, "jmp") == 0) | |
13554 | align_branch |= align_branch_jmp_bit; | |
13555 | else if (strcasecmp (type, "call") == 0) | |
13556 | align_branch |= align_branch_call_bit; | |
13557 | else if (strcasecmp (type, "ret") == 0) | |
13558 | align_branch |= align_branch_ret_bit; | |
13559 | else if (strcasecmp (type, "indirect") == 0) | |
13560 | align_branch |= align_branch_indirect_bit; | |
13561 | else | |
13562 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
13563 | type = next; | |
13564 | } | |
13565 | while (next != NULL); | |
13566 | free (saved); | |
13567 | break; | |
13568 | ||
76cf450b L |
13569 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
13570 | align_branch_power = 5; | |
13571 | align_branch_prefix_size = 5; | |
13572 | align_branch = (align_branch_jcc_bit | |
13573 | | align_branch_fused_bit | |
13574 | | align_branch_jmp_bit); | |
13575 | break; | |
13576 | ||
5db04b09 | 13577 | case OPTION_MAMD64: |
4b5aaf5f | 13578 | isa64 = amd64; |
5db04b09 L |
13579 | break; |
13580 | ||
13581 | case OPTION_MINTEL64: | |
4b5aaf5f | 13582 | isa64 = intel64; |
5db04b09 L |
13583 | break; |
13584 | ||
b6f8c7c4 L |
13585 | case 'O': |
13586 | if (arg == NULL) | |
13587 | { | |
13588 | optimize = 1; | |
13589 | /* Turn off -Os. */ | |
13590 | optimize_for_space = 0; | |
13591 | } | |
13592 | else if (*arg == 's') | |
13593 | { | |
13594 | optimize_for_space = 1; | |
13595 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 13596 | optimize = INT_MAX; |
b6f8c7c4 L |
13597 | } |
13598 | else | |
13599 | { | |
13600 | optimize = atoi (arg); | |
13601 | /* Turn off -Os. */ | |
13602 | optimize_for_space = 0; | |
13603 | } | |
13604 | break; | |
13605 | ||
252b5132 RH |
13606 | default: |
13607 | return 0; | |
13608 | } | |
13609 | return 1; | |
13610 | } | |
13611 | ||
8a2c8fef L |
13612 | #define MESSAGE_TEMPLATE \ |
13613 | " " | |
13614 | ||
293f5f65 L |
13615 | static char * |
13616 | output_message (FILE *stream, char *p, char *message, char *start, | |
13617 | int *left_p, const char *name, int len) | |
13618 | { | |
13619 | int size = sizeof (MESSAGE_TEMPLATE); | |
13620 | int left = *left_p; | |
13621 | ||
13622 | /* Reserve 2 spaces for ", " or ",\0" */ | |
13623 | left -= len + 2; | |
13624 | ||
13625 | /* Check if there is any room. */ | |
13626 | if (left >= 0) | |
13627 | { | |
13628 | if (p != start) | |
13629 | { | |
13630 | *p++ = ','; | |
13631 | *p++ = ' '; | |
13632 | } | |
13633 | p = mempcpy (p, name, len); | |
13634 | } | |
13635 | else | |
13636 | { | |
13637 | /* Output the current message now and start a new one. */ | |
13638 | *p++ = ','; | |
13639 | *p = '\0'; | |
13640 | fprintf (stream, "%s\n", message); | |
13641 | p = start; | |
13642 | left = size - (start - message) - len - 2; | |
13643 | ||
13644 | gas_assert (left >= 0); | |
13645 | ||
13646 | p = mempcpy (p, name, len); | |
13647 | } | |
13648 | ||
13649 | *left_p = left; | |
13650 | return p; | |
13651 | } | |
13652 | ||
8a2c8fef | 13653 | static void |
1ded5609 | 13654 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
13655 | { |
13656 | static char message[] = MESSAGE_TEMPLATE; | |
13657 | char *start = message + 27; | |
13658 | char *p; | |
13659 | int size = sizeof (MESSAGE_TEMPLATE); | |
13660 | int left; | |
13661 | const char *name; | |
13662 | int len; | |
13663 | unsigned int j; | |
13664 | ||
13665 | p = start; | |
13666 | left = size - (start - message); | |
13667 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
13668 | { | |
13669 | /* Should it be skipped? */ | |
13670 | if (cpu_arch [j].skip) | |
13671 | continue; | |
13672 | ||
13673 | name = cpu_arch [j].name; | |
13674 | len = cpu_arch [j].len; | |
13675 | if (*name == '.') | |
13676 | { | |
13677 | /* It is an extension. Skip if we aren't asked to show it. */ | |
13678 | if (ext) | |
13679 | { | |
13680 | name++; | |
13681 | len--; | |
13682 | } | |
13683 | else | |
13684 | continue; | |
13685 | } | |
13686 | else if (ext) | |
13687 | { | |
13688 | /* It is an processor. Skip if we show only extension. */ | |
13689 | continue; | |
13690 | } | |
1ded5609 JB |
13691 | else if (check && ! cpu_arch[j].flags.bitfield.cpui386) |
13692 | { | |
13693 | /* It is an impossible processor - skip. */ | |
13694 | continue; | |
13695 | } | |
8a2c8fef | 13696 | |
293f5f65 | 13697 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
13698 | } |
13699 | ||
293f5f65 L |
13700 | /* Display disabled extensions. */ |
13701 | if (ext) | |
13702 | for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++) | |
13703 | { | |
13704 | name = cpu_noarch [j].name; | |
13705 | len = cpu_noarch [j].len; | |
13706 | p = output_message (stream, p, message, start, &left, name, | |
13707 | len); | |
13708 | } | |
13709 | ||
8a2c8fef L |
13710 | *p = '\0'; |
13711 | fprintf (stream, "%s\n", message); | |
13712 | } | |
13713 | ||
252b5132 | 13714 | void |
8a2c8fef | 13715 | md_show_usage (FILE *stream) |
252b5132 | 13716 | { |
4cc782b5 ILT |
13717 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
13718 | fprintf (stream, _("\ | |
d4693039 | 13719 | -Qy, -Qn ignored\n\ |
a38cf1db | 13720 | -V print assembler version number\n\ |
b3b91714 AM |
13721 | -k ignored\n")); |
13722 | #endif | |
13723 | fprintf (stream, _("\ | |
12b55ccc | 13724 | -n Do not optimize code alignment\n\ |
b3b91714 AM |
13725 | -q quieten some warnings\n")); |
13726 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
13727 | fprintf (stream, _("\ | |
a38cf1db | 13728 | -s ignored\n")); |
b3b91714 | 13729 | #endif |
d7f449c0 L |
13730 | #if defined BFD64 && (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
13731 | || defined (TE_PE) || defined (TE_PEP)) | |
751d281c | 13732 | fprintf (stream, _("\ |
570561f7 | 13733 | --32/--64/--x32 generate 32bit/64bit/x32 code\n")); |
751d281c | 13734 | #endif |
b3b91714 AM |
13735 | #ifdef SVR4_COMMENT_CHARS |
13736 | fprintf (stream, _("\ | |
13737 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
13738 | #else |
13739 | fprintf (stream, _("\ | |
b3b91714 | 13740 | --divide ignored\n")); |
4cc782b5 | 13741 | #endif |
9103f4f4 | 13742 | fprintf (stream, _("\ |
6305a203 | 13743 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 13744 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 13745 | show_arch (stream, 0, 1); |
8a2c8fef L |
13746 | fprintf (stream, _("\ |
13747 | EXTENSION is combination of:\n")); | |
1ded5609 | 13748 | show_arch (stream, 1, 0); |
6305a203 | 13749 | fprintf (stream, _("\ |
8a2c8fef | 13750 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 13751 | show_arch (stream, 0, 0); |
ba104c83 | 13752 | fprintf (stream, _("\ |
c0f3af97 L |
13753 | -msse2avx encode SSE instructions with VEX prefix\n")); |
13754 | fprintf (stream, _("\ | |
7c5c05ef | 13755 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
13756 | check SSE instructions\n")); |
13757 | fprintf (stream, _("\ | |
7c5c05ef | 13758 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
13759 | check operand combinations for validity\n")); |
13760 | fprintf (stream, _("\ | |
7c5c05ef L |
13761 | -mavxscalar=[128|256] (default: 128)\n\ |
13762 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
13763 | length\n")); |
13764 | fprintf (stream, _("\ | |
03751133 L |
13765 | -mvexwig=[0|1] (default: 0)\n\ |
13766 | encode VEX instructions with specific VEX.W value\n\ | |
13767 | for VEX.W bit ignored instructions\n")); | |
13768 | fprintf (stream, _("\ | |
7c5c05ef L |
13769 | -mevexlig=[128|256|512] (default: 128)\n\ |
13770 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
13771 | length\n")); |
13772 | fprintf (stream, _("\ | |
7c5c05ef L |
13773 | -mevexwig=[0|1] (default: 0)\n\ |
13774 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
13775 | for EVEX.W bit ignored instructions\n")); |
13776 | fprintf (stream, _("\ | |
7c5c05ef | 13777 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
13778 | encode EVEX instructions with specific EVEX.RC value\n\ |
13779 | for SAE-only ignored instructions\n")); | |
13780 | fprintf (stream, _("\ | |
7c5c05ef L |
13781 | -mmnemonic=[att|intel] ")); |
13782 | if (SYSV386_COMPAT) | |
13783 | fprintf (stream, _("(default: att)\n")); | |
13784 | else | |
13785 | fprintf (stream, _("(default: intel)\n")); | |
13786 | fprintf (stream, _("\ | |
13787 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 13788 | fprintf (stream, _("\ |
7c5c05ef L |
13789 | -msyntax=[att|intel] (default: att)\n\ |
13790 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
13791 | fprintf (stream, _("\ |
13792 | -mindex-reg support pseudo index registers\n")); | |
13793 | fprintf (stream, _("\ | |
13794 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
13795 | fprintf (stream, _("\ | |
7e8b059b | 13796 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 13797 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
13798 | fprintf (stream, _("\ |
13799 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
13800 | fprintf (stream, _("\ |
13801 | -mx86-used-note=[no|yes] ")); | |
13802 | if (DEFAULT_X86_USED_NOTE) | |
13803 | fprintf (stream, _("(default: yes)\n")); | |
13804 | else | |
13805 | fprintf (stream, _("(default: no)\n")); | |
13806 | fprintf (stream, _("\ | |
13807 | generate x86 used ISA and feature properties\n")); | |
13808 | #endif | |
13809 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
13810 | fprintf (stream, _("\ |
13811 | -mbig-obj generate big object files\n")); | |
13812 | #endif | |
d022bddd | 13813 | fprintf (stream, _("\ |
7c5c05ef | 13814 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 13815 | strip all lock prefixes\n")); |
5db04b09 | 13816 | fprintf (stream, _("\ |
7c5c05ef | 13817 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
13818 | encode lfence, mfence and sfence as\n\ |
13819 | lock addl $0x0, (%%{re}sp)\n")); | |
13820 | fprintf (stream, _("\ | |
7c5c05ef L |
13821 | -mrelax-relocations=[no|yes] ")); |
13822 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
13823 | fprintf (stream, _("(default: yes)\n")); | |
13824 | else | |
13825 | fprintf (stream, _("(default: no)\n")); | |
13826 | fprintf (stream, _("\ | |
0cb4071e L |
13827 | generate relax relocations\n")); |
13828 | fprintf (stream, _("\ | |
e379e5f3 L |
13829 | -malign-branch-boundary=NUM (default: 0)\n\ |
13830 | align branches within NUM byte boundary\n")); | |
13831 | fprintf (stream, _("\ | |
13832 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
13833 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
13834 | indirect\n\ | |
13835 | specify types of branches to align\n")); | |
13836 | fprintf (stream, _("\ | |
13837 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
13838 | align branches with NUM prefixes per instruction\n")); | |
13839 | fprintf (stream, _("\ | |
76cf450b L |
13840 | -mbranches-within-32B-boundaries\n\ |
13841 | align branches within 32 byte boundary\n")); | |
13842 | fprintf (stream, _("\ | |
ae531041 L |
13843 | -mlfence-after-load=[no|yes] (default: no)\n\ |
13844 | generate lfence after load\n")); | |
13845 | fprintf (stream, _("\ | |
13846 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
13847 | generate lfence before indirect near branch\n")); | |
13848 | fprintf (stream, _("\ | |
a09f656b | 13849 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
13850 | generate lfence before ret\n")); |
13851 | fprintf (stream, _("\ | |
7c5c05ef | 13852 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
13853 | fprintf (stream, _("\ |
13854 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
13855 | } |
13856 | ||
3e73aa7c | 13857 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 13858 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 13859 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
13860 | |
13861 | /* Pick the target format to use. */ | |
13862 | ||
47926f60 | 13863 | const char * |
e3bb37b5 | 13864 | i386_target_format (void) |
252b5132 | 13865 | { |
d34049e8 | 13866 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
13867 | { |
13868 | update_code_flag (CODE_64BIT, 1); | |
13869 | if (default_arch[6] == '\0') | |
7f56bc95 | 13870 | x86_elf_abi = X86_64_ABI; |
351f65ca | 13871 | else |
7f56bc95 | 13872 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 13873 | } |
3e73aa7c | 13874 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 13875 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
13876 | else if (!strcmp (default_arch, "iamcu")) |
13877 | { | |
13878 | update_code_flag (CODE_32BIT, 1); | |
13879 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
13880 | { | |
13881 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
13882 | cpu_arch_name = "iamcu"; | |
13883 | cpu_sub_arch_name = NULL; | |
13884 | cpu_arch_flags = iamcu_flags; | |
13885 | cpu_arch_isa = PROCESSOR_IAMCU; | |
13886 | cpu_arch_isa_flags = iamcu_flags; | |
13887 | if (!cpu_arch_tune_set) | |
13888 | { | |
13889 | cpu_arch_tune = cpu_arch_isa; | |
13890 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
13891 | } | |
13892 | } | |
8d471ec1 | 13893 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
13894 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
13895 | cpu_arch_name); | |
13896 | } | |
3e73aa7c | 13897 | else |
2b5d6a91 | 13898 | as_fatal (_("unknown architecture")); |
89507696 JB |
13899 | |
13900 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
13901 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13902 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) | |
13903 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags; | |
13904 | ||
252b5132 RH |
13905 | switch (OUTPUT_FLAVOR) |
13906 | { | |
9384f2ff | 13907 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 13908 | case bfd_target_aout_flavour: |
47926f60 | 13909 | return AOUT_TARGET_FORMAT; |
4c63da97 | 13910 | #endif |
9384f2ff AM |
13911 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
13912 | # if defined (TE_PE) || defined (TE_PEP) | |
13913 | case bfd_target_coff_flavour: | |
167ad85b | 13914 | if (flag_code == CODE_64BIT) |
eb19308f JB |
13915 | { |
13916 | object_64bit = 1; | |
13917 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
13918 | } | |
13919 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 13920 | # elif defined (TE_GO32) |
0561d57c JK |
13921 | case bfd_target_coff_flavour: |
13922 | return "coff-go32"; | |
9384f2ff | 13923 | # else |
252b5132 RH |
13924 | case bfd_target_coff_flavour: |
13925 | return "coff-i386"; | |
9384f2ff | 13926 | # endif |
4c63da97 | 13927 | #endif |
3e73aa7c | 13928 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 13929 | case bfd_target_elf_flavour: |
3e73aa7c | 13930 | { |
351f65ca L |
13931 | const char *format; |
13932 | ||
13933 | switch (x86_elf_abi) | |
4fa24527 | 13934 | { |
351f65ca L |
13935 | default: |
13936 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
13937 | #ifndef TE_SOLARIS |
13938 | tls_get_addr = "___tls_get_addr"; | |
13939 | #endif | |
351f65ca | 13940 | break; |
7f56bc95 | 13941 | case X86_64_ABI: |
351f65ca | 13942 | use_rela_relocations = 1; |
4fa24527 | 13943 | object_64bit = 1; |
e379e5f3 L |
13944 | #ifndef TE_SOLARIS |
13945 | tls_get_addr = "__tls_get_addr"; | |
13946 | #endif | |
351f65ca L |
13947 | format = ELF_TARGET_FORMAT64; |
13948 | break; | |
7f56bc95 | 13949 | case X86_64_X32_ABI: |
4fa24527 | 13950 | use_rela_relocations = 1; |
351f65ca | 13951 | object_64bit = 1; |
e379e5f3 L |
13952 | #ifndef TE_SOLARIS |
13953 | tls_get_addr = "__tls_get_addr"; | |
13954 | #endif | |
862be3fb | 13955 | disallow_64bit_reloc = 1; |
351f65ca L |
13956 | format = ELF_TARGET_FORMAT32; |
13957 | break; | |
4fa24527 | 13958 | } |
3632d14b | 13959 | if (cpu_arch_isa == PROCESSOR_L1OM) |
8a9036a4 | 13960 | { |
7f56bc95 | 13961 | if (x86_elf_abi != X86_64_ABI) |
8a9036a4 L |
13962 | as_fatal (_("Intel L1OM is 64bit only")); |
13963 | return ELF_TARGET_L1OM_FORMAT; | |
13964 | } | |
b49f93f6 | 13965 | else if (cpu_arch_isa == PROCESSOR_K1OM) |
7a9068fe L |
13966 | { |
13967 | if (x86_elf_abi != X86_64_ABI) | |
13968 | as_fatal (_("Intel K1OM is 64bit only")); | |
13969 | return ELF_TARGET_K1OM_FORMAT; | |
13970 | } | |
81486035 L |
13971 | else if (cpu_arch_isa == PROCESSOR_IAMCU) |
13972 | { | |
13973 | if (x86_elf_abi != I386_ABI) | |
13974 | as_fatal (_("Intel MCU is 32bit only")); | |
13975 | return ELF_TARGET_IAMCU_FORMAT; | |
13976 | } | |
8a9036a4 | 13977 | else |
351f65ca | 13978 | return format; |
3e73aa7c | 13979 | } |
e57f8c65 TG |
13980 | #endif |
13981 | #if defined (OBJ_MACH_O) | |
13982 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
13983 | if (flag_code == CODE_64BIT) |
13984 | { | |
13985 | use_rela_relocations = 1; | |
13986 | object_64bit = 1; | |
13987 | return "mach-o-x86-64"; | |
13988 | } | |
13989 | else | |
13990 | return "mach-o-i386"; | |
4c63da97 | 13991 | #endif |
252b5132 RH |
13992 | default: |
13993 | abort (); | |
13994 | return NULL; | |
13995 | } | |
13996 | } | |
13997 | ||
47926f60 | 13998 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 13999 | \f |
252b5132 | 14000 | symbolS * |
7016a5d5 | 14001 | md_undefined_symbol (char *name) |
252b5132 | 14002 | { |
18dc2407 ILT |
14003 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
14004 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
14005 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
14006 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
14007 | { |
14008 | if (!GOT_symbol) | |
14009 | { | |
14010 | if (symbol_find (name)) | |
14011 | as_bad (_("GOT already in symbol table")); | |
14012 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 14013 | &zero_address_frag, 0); |
24eab124 AM |
14014 | }; |
14015 | return GOT_symbol; | |
14016 | } | |
252b5132 RH |
14017 | return 0; |
14018 | } | |
14019 | ||
14020 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 14021 | |
252b5132 | 14022 | valueT |
7016a5d5 | 14023 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 14024 | { |
4c63da97 AM |
14025 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
14026 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
14027 | { | |
14028 | /* For a.out, force the section size to be aligned. If we don't do | |
14029 | this, BFD will align it for us, but it will not write out the | |
14030 | final bytes of the section. This may be a bug in BFD, but it is | |
14031 | easier to fix it here since that is how the other a.out targets | |
14032 | work. */ | |
14033 | int align; | |
14034 | ||
fd361982 | 14035 | align = bfd_section_alignment (segment); |
8d3842cd | 14036 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 14037 | } |
252b5132 RH |
14038 | #endif |
14039 | ||
14040 | return size; | |
14041 | } | |
14042 | ||
14043 | /* On the i386, PC-relative offsets are relative to the start of the | |
14044 | next instruction. That is, the address of the offset, plus its | |
14045 | size, since the offset is always the last part of the insn. */ | |
14046 | ||
14047 | long | |
e3bb37b5 | 14048 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
14049 | { |
14050 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
14051 | } | |
14052 | ||
14053 | #ifndef I386COFF | |
14054 | ||
14055 | static void | |
e3bb37b5 | 14056 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 14057 | { |
29b0f896 | 14058 | int temp; |
252b5132 | 14059 | |
8a75718c JB |
14060 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14061 | if (IS_ELF) | |
14062 | obj_elf_section_change_hook (); | |
14063 | #endif | |
252b5132 RH |
14064 | temp = get_absolute_expression (); |
14065 | subseg_set (bss_section, (subsegT) temp); | |
14066 | demand_empty_rest_of_line (); | |
14067 | } | |
14068 | ||
14069 | #endif | |
14070 | ||
e379e5f3 L |
14071 | /* Remember constant directive. */ |
14072 | ||
14073 | void | |
14074 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
14075 | { | |
14076 | if (last_insn.kind != last_insn_directive | |
14077 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
14078 | { | |
14079 | last_insn.seg = now_seg; | |
14080 | last_insn.kind = last_insn_directive; | |
14081 | last_insn.name = "constant directive"; | |
14082 | last_insn.file = as_where (&last_insn.line); | |
ae531041 L |
14083 | if (lfence_before_ret != lfence_before_ret_none) |
14084 | { | |
14085 | if (lfence_before_indirect_branch != lfence_branch_none) | |
14086 | as_warn (_("constant directive skips -mlfence-before-ret " | |
14087 | "and -mlfence-before-indirect-branch")); | |
14088 | else | |
14089 | as_warn (_("constant directive skips -mlfence-before-ret")); | |
14090 | } | |
14091 | else if (lfence_before_indirect_branch != lfence_branch_none) | |
14092 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); | |
e379e5f3 L |
14093 | } |
14094 | } | |
14095 | ||
3abbafc2 | 14096 | int |
e3bb37b5 | 14097 | i386_validate_fix (fixS *fixp) |
252b5132 | 14098 | { |
3abbafc2 JB |
14099 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
14100 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
14101 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
14102 | return IS_ELF && fixp->fx_addsy | |
14103 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
14104 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
14105 | #endif | |
14106 | ||
02a86693 | 14107 | if (fixp->fx_subsy) |
252b5132 | 14108 | { |
02a86693 | 14109 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 14110 | { |
02a86693 L |
14111 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
14112 | { | |
14113 | if (!object_64bit) | |
14114 | abort (); | |
14115 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14116 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
14117 | fixp->fx_r_type = (fixp->fx_tcbit |
14118 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
14119 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
14120 | else |
14121 | #endif | |
14122 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
14123 | } | |
d6ab8113 | 14124 | else |
02a86693 L |
14125 | { |
14126 | if (!object_64bit) | |
14127 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
14128 | else | |
14129 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
14130 | } | |
14131 | fixp->fx_subsy = 0; | |
23df1078 | 14132 | } |
252b5132 | 14133 | } |
02a86693 | 14134 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 14135 | else |
02a86693 | 14136 | { |
2585b7a5 L |
14137 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
14138 | to section. Since PLT32 relocation must be against symbols, | |
14139 | turn such PLT32 relocation into PC32 relocation. */ | |
14140 | if (fixp->fx_addsy | |
14141 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
14142 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
14143 | && symbol_section_p (fixp->fx_addsy)) | |
14144 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
14145 | if (!object_64bit) | |
14146 | { | |
14147 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
14148 | && fixp->fx_tcbit2) | |
14149 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
14150 | } | |
02a86693 L |
14151 | } |
14152 | #endif | |
3abbafc2 JB |
14153 | |
14154 | return 1; | |
252b5132 RH |
14155 | } |
14156 | ||
252b5132 | 14157 | arelent * |
7016a5d5 | 14158 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
14159 | { |
14160 | arelent *rel; | |
14161 | bfd_reloc_code_real_type code; | |
14162 | ||
14163 | switch (fixp->fx_r_type) | |
14164 | { | |
8ce3d284 | 14165 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
14166 | symbolS *sym; |
14167 | ||
8fd4256d L |
14168 | case BFD_RELOC_SIZE32: |
14169 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
14170 | if (fixp->fx_addsy |
14171 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
14172 | && (!fixp->fx_subsy | |
14173 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
14174 | sym = fixp->fx_addsy; | |
14175 | else if (fixp->fx_subsy | |
14176 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
14177 | && (!fixp->fx_addsy | |
14178 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
14179 | sym = fixp->fx_subsy; | |
14180 | else | |
14181 | sym = NULL; | |
14182 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
14183 | { |
14184 | /* Resolve size relocation against local symbol to size of | |
14185 | the symbol plus addend. */ | |
3abbafc2 | 14186 | valueT value = S_GET_SIZE (sym); |
44f87162 | 14187 | |
3abbafc2 JB |
14188 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
14189 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
14190 | if (sym == fixp->fx_subsy) | |
14191 | { | |
14192 | value = -value; | |
14193 | if (fixp->fx_addsy) | |
14194 | value += S_GET_VALUE (fixp->fx_addsy); | |
14195 | } | |
14196 | else if (fixp->fx_subsy) | |
14197 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 14198 | value += fixp->fx_offset; |
8fd4256d | 14199 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 14200 | && object_64bit |
8fd4256d L |
14201 | && !fits_in_unsigned_long (value)) |
14202 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14203 | _("symbol size computation overflow")); | |
14204 | fixp->fx_addsy = NULL; | |
14205 | fixp->fx_subsy = NULL; | |
14206 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
14207 | return NULL; | |
14208 | } | |
3abbafc2 JB |
14209 | if (!fixp->fx_addsy || fixp->fx_subsy) |
14210 | { | |
14211 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14212 | "unsupported expression involving @size"); | |
14213 | return NULL; | |
14214 | } | |
8ce3d284 | 14215 | #endif |
1a0670f3 | 14216 | /* Fall through. */ |
8fd4256d | 14217 | |
3e73aa7c JH |
14218 | case BFD_RELOC_X86_64_PLT32: |
14219 | case BFD_RELOC_X86_64_GOT32: | |
14220 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14221 | case BFD_RELOC_X86_64_GOTPCRELX: |
14222 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
14223 | case BFD_RELOC_386_PLT32: |
14224 | case BFD_RELOC_386_GOT32: | |
02a86693 | 14225 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
14226 | case BFD_RELOC_386_GOTOFF: |
14227 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
14228 | case BFD_RELOC_386_TLS_GD: |
14229 | case BFD_RELOC_386_TLS_LDM: | |
14230 | case BFD_RELOC_386_TLS_LDO_32: | |
14231 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
14232 | case BFD_RELOC_386_TLS_IE: |
14233 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
14234 | case BFD_RELOC_386_TLS_LE_32: |
14235 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
14236 | case BFD_RELOC_386_TLS_GOTDESC: |
14237 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
14238 | case BFD_RELOC_X86_64_TLSGD: |
14239 | case BFD_RELOC_X86_64_TLSLD: | |
14240 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 14241 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
14242 | case BFD_RELOC_X86_64_GOTTPOFF: |
14243 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
14244 | case BFD_RELOC_X86_64_TPOFF64: |
14245 | case BFD_RELOC_X86_64_GOTOFF64: | |
14246 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
14247 | case BFD_RELOC_X86_64_GOT64: |
14248 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14249 | case BFD_RELOC_X86_64_GOTPC64: | |
14250 | case BFD_RELOC_X86_64_GOTPLT64: | |
14251 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
14252 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14253 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
14254 | case BFD_RELOC_RVA: |
14255 | case BFD_RELOC_VTABLE_ENTRY: | |
14256 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
14257 | #ifdef TE_PE |
14258 | case BFD_RELOC_32_SECREL: | |
14259 | #endif | |
252b5132 RH |
14260 | code = fixp->fx_r_type; |
14261 | break; | |
dbbaec26 L |
14262 | case BFD_RELOC_X86_64_32S: |
14263 | if (!fixp->fx_pcrel) | |
14264 | { | |
14265 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
14266 | code = fixp->fx_r_type; | |
14267 | break; | |
14268 | } | |
1a0670f3 | 14269 | /* Fall through. */ |
252b5132 | 14270 | default: |
93382f6d | 14271 | if (fixp->fx_pcrel) |
252b5132 | 14272 | { |
93382f6d AM |
14273 | switch (fixp->fx_size) |
14274 | { | |
14275 | default: | |
b091f402 AM |
14276 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14277 | _("can not do %d byte pc-relative relocation"), | |
14278 | fixp->fx_size); | |
93382f6d AM |
14279 | code = BFD_RELOC_32_PCREL; |
14280 | break; | |
14281 | case 1: code = BFD_RELOC_8_PCREL; break; | |
14282 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 14283 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
14284 | #ifdef BFD64 |
14285 | case 8: code = BFD_RELOC_64_PCREL; break; | |
14286 | #endif | |
93382f6d AM |
14287 | } |
14288 | } | |
14289 | else | |
14290 | { | |
14291 | switch (fixp->fx_size) | |
14292 | { | |
14293 | default: | |
b091f402 AM |
14294 | as_bad_where (fixp->fx_file, fixp->fx_line, |
14295 | _("can not do %d byte relocation"), | |
14296 | fixp->fx_size); | |
93382f6d AM |
14297 | code = BFD_RELOC_32; |
14298 | break; | |
14299 | case 1: code = BFD_RELOC_8; break; | |
14300 | case 2: code = BFD_RELOC_16; break; | |
14301 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 14302 | #ifdef BFD64 |
3e73aa7c | 14303 | case 8: code = BFD_RELOC_64; break; |
937149dd | 14304 | #endif |
93382f6d | 14305 | } |
252b5132 RH |
14306 | } |
14307 | break; | |
14308 | } | |
252b5132 | 14309 | |
d182319b JB |
14310 | if ((code == BFD_RELOC_32 |
14311 | || code == BFD_RELOC_32_PCREL | |
14312 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
14313 | && GOT_symbol |
14314 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 14315 | { |
4fa24527 | 14316 | if (!object_64bit) |
d6ab8113 JB |
14317 | code = BFD_RELOC_386_GOTPC; |
14318 | else | |
14319 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 14320 | } |
7b81dfbb AJ |
14321 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
14322 | && GOT_symbol | |
14323 | && fixp->fx_addsy == GOT_symbol) | |
14324 | { | |
14325 | code = BFD_RELOC_X86_64_GOTPC64; | |
14326 | } | |
252b5132 | 14327 | |
add39d23 TS |
14328 | rel = XNEW (arelent); |
14329 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 14330 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
14331 | |
14332 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 14333 | |
3e73aa7c JH |
14334 | if (!use_rela_relocations) |
14335 | { | |
14336 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
14337 | vtable entry to be used in the relocation's section offset. */ | |
14338 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
14339 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
14340 | #if defined (OBJ_COFF) && defined (TE_PE) |
14341 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
14342 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
14343 | else | |
14344 | #endif | |
c6682705 | 14345 | rel->addend = 0; |
3e73aa7c JH |
14346 | } |
14347 | /* Use the rela in 64bit mode. */ | |
252b5132 | 14348 | else |
3e73aa7c | 14349 | { |
862be3fb L |
14350 | if (disallow_64bit_reloc) |
14351 | switch (code) | |
14352 | { | |
862be3fb L |
14353 | case BFD_RELOC_X86_64_DTPOFF64: |
14354 | case BFD_RELOC_X86_64_TPOFF64: | |
14355 | case BFD_RELOC_64_PCREL: | |
14356 | case BFD_RELOC_X86_64_GOTOFF64: | |
14357 | case BFD_RELOC_X86_64_GOT64: | |
14358 | case BFD_RELOC_X86_64_GOTPCREL64: | |
14359 | case BFD_RELOC_X86_64_GOTPC64: | |
14360 | case BFD_RELOC_X86_64_GOTPLT64: | |
14361 | case BFD_RELOC_X86_64_PLTOFF64: | |
14362 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
14363 | _("cannot represent relocation type %s in x32 mode"), | |
14364 | bfd_get_reloc_code_name (code)); | |
14365 | break; | |
14366 | default: | |
14367 | break; | |
14368 | } | |
14369 | ||
062cd5e7 AS |
14370 | if (!fixp->fx_pcrel) |
14371 | rel->addend = fixp->fx_offset; | |
14372 | else | |
14373 | switch (code) | |
14374 | { | |
14375 | case BFD_RELOC_X86_64_PLT32: | |
14376 | case BFD_RELOC_X86_64_GOT32: | |
14377 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
14378 | case BFD_RELOC_X86_64_GOTPCRELX: |
14379 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
14380 | case BFD_RELOC_X86_64_TLSGD: |
14381 | case BFD_RELOC_X86_64_TLSLD: | |
14382 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
14383 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
14384 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
14385 | rel->addend = fixp->fx_offset - fixp->fx_size; |
14386 | break; | |
14387 | default: | |
14388 | rel->addend = (section->vma | |
14389 | - fixp->fx_size | |
14390 | + fixp->fx_addnumber | |
14391 | + md_pcrel_from (fixp)); | |
14392 | break; | |
14393 | } | |
3e73aa7c JH |
14394 | } |
14395 | ||
252b5132 RH |
14396 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
14397 | if (rel->howto == NULL) | |
14398 | { | |
14399 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 14400 | _("cannot represent relocation type %s"), |
252b5132 RH |
14401 | bfd_get_reloc_code_name (code)); |
14402 | /* Set howto to a garbage value so that we can keep going. */ | |
14403 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 14404 | gas_assert (rel->howto != NULL); |
252b5132 RH |
14405 | } |
14406 | ||
14407 | return rel; | |
14408 | } | |
14409 | ||
ee86248c | 14410 | #include "tc-i386-intel.c" |
54cfded0 | 14411 | |
a60de03c JB |
14412 | void |
14413 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 14414 | { |
a60de03c JB |
14415 | int saved_naked_reg; |
14416 | char saved_register_dot; | |
54cfded0 | 14417 | |
a60de03c JB |
14418 | saved_naked_reg = allow_naked_reg; |
14419 | allow_naked_reg = 1; | |
14420 | saved_register_dot = register_chars['.']; | |
14421 | register_chars['.'] = '.'; | |
14422 | allow_pseudo_reg = 1; | |
14423 | expression_and_evaluate (exp); | |
14424 | allow_pseudo_reg = 0; | |
14425 | register_chars['.'] = saved_register_dot; | |
14426 | allow_naked_reg = saved_naked_reg; | |
14427 | ||
e96d56a1 | 14428 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 14429 | { |
a60de03c JB |
14430 | if ((addressT) exp->X_add_number < i386_regtab_size) |
14431 | { | |
14432 | exp->X_op = O_constant; | |
14433 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
14434 | .dw2_regnum[flag_code >> 1]; | |
14435 | } | |
14436 | else | |
14437 | exp->X_op = O_illegal; | |
54cfded0 | 14438 | } |
54cfded0 AM |
14439 | } |
14440 | ||
14441 | void | |
14442 | tc_x86_frame_initial_instructions (void) | |
14443 | { | |
a60de03c JB |
14444 | static unsigned int sp_regno[2]; |
14445 | ||
14446 | if (!sp_regno[flag_code >> 1]) | |
14447 | { | |
14448 | char *saved_input = input_line_pointer; | |
14449 | char sp[][4] = {"esp", "rsp"}; | |
14450 | expressionS exp; | |
a4447b93 | 14451 | |
a60de03c JB |
14452 | input_line_pointer = sp[flag_code >> 1]; |
14453 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 14454 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
14455 | sp_regno[flag_code >> 1] = exp.X_add_number; |
14456 | input_line_pointer = saved_input; | |
14457 | } | |
a4447b93 | 14458 | |
61ff971f L |
14459 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
14460 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 14461 | } |
d2b2c203 | 14462 | |
d7921315 L |
14463 | int |
14464 | x86_dwarf2_addr_size (void) | |
14465 | { | |
14466 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
14467 | if (x86_elf_abi == X86_64_X32_ABI) | |
14468 | return 4; | |
14469 | #endif | |
14470 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
14471 | } | |
14472 | ||
d2b2c203 DJ |
14473 | int |
14474 | i386_elf_section_type (const char *str, size_t len) | |
14475 | { | |
14476 | if (flag_code == CODE_64BIT | |
14477 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 14478 | && startswith (str, "unwind")) |
d2b2c203 DJ |
14479 | return SHT_X86_64_UNWIND; |
14480 | ||
14481 | return -1; | |
14482 | } | |
bb41ade5 | 14483 | |
ad5fec3b EB |
14484 | #ifdef TE_SOLARIS |
14485 | void | |
14486 | i386_solaris_fix_up_eh_frame (segT sec) | |
14487 | { | |
14488 | if (flag_code == CODE_64BIT) | |
14489 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
14490 | } | |
14491 | #endif | |
14492 | ||
bb41ade5 AM |
14493 | #ifdef TE_PE |
14494 | void | |
14495 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
14496 | { | |
91d6fa6a | 14497 | expressionS exp; |
bb41ade5 | 14498 | |
91d6fa6a NC |
14499 | exp.X_op = O_secrel; |
14500 | exp.X_add_symbol = symbol; | |
14501 | exp.X_add_number = 0; | |
14502 | emit_expr (&exp, size); | |
bb41ade5 AM |
14503 | } |
14504 | #endif | |
3b22753a L |
14505 | |
14506 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
14507 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
14508 | ||
01e1a5bc | 14509 | bfd_vma |
6d4af3c2 | 14510 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
14511 | { |
14512 | if (flag_code == CODE_64BIT) | |
14513 | { | |
14514 | if (letter == 'l') | |
14515 | return SHF_X86_64_LARGE; | |
14516 | ||
8f3bae45 | 14517 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 14518 | } |
3b22753a | 14519 | else |
8f3bae45 | 14520 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
14521 | return -1; |
14522 | } | |
14523 | ||
01e1a5bc | 14524 | bfd_vma |
3b22753a L |
14525 | x86_64_section_word (char *str, size_t len) |
14526 | { | |
08dedd66 | 14527 | if (len == 5 && flag_code == CODE_64BIT && startswith (str, "large")) |
3b22753a L |
14528 | return SHF_X86_64_LARGE; |
14529 | ||
14530 | return -1; | |
14531 | } | |
14532 | ||
14533 | static void | |
14534 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
14535 | { | |
14536 | if (flag_code != CODE_64BIT) | |
14537 | { | |
14538 | s_comm_internal (0, elf_common_parse); | |
14539 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
14540 | } | |
14541 | else | |
14542 | { | |
14543 | static segT lbss_section; | |
14544 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
14545 | asection *saved_bss_section = bss_section; | |
14546 | ||
14547 | if (lbss_section == NULL) | |
14548 | { | |
14549 | flagword applicable; | |
14550 | segT seg = now_seg; | |
14551 | subsegT subseg = now_subseg; | |
14552 | ||
14553 | /* The .lbss section is for local .largecomm symbols. */ | |
14554 | lbss_section = subseg_new (".lbss", 0); | |
14555 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 14556 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
14557 | seg_info (lbss_section)->bss = 1; |
14558 | ||
14559 | subseg_set (seg, subseg); | |
14560 | } | |
14561 | ||
14562 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
14563 | bss_section = lbss_section; | |
14564 | ||
14565 | s_comm_internal (0, elf_common_parse); | |
14566 | ||
14567 | elf_com_section_ptr = saved_com_section_ptr; | |
14568 | bss_section = saved_bss_section; | |
14569 | } | |
14570 | } | |
14571 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |