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* ld-scripts/dynamic-sections*: New test.
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5db1645b 3 2000, 2001, 2002
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21 02111-1307, USA. */
22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
47926f60
KH		 26 Bugs & suggestions are completely welcome. This is free software.
27 Please help us make it better. */
252b5132 28
252b5132 29#include "as.h"
3882b010 30#include "safe-ctype.h"
252b5132 31#include "subsegs.h"
316e2c05 32#include "dwarf2dbg.h"
252b5132
RH		 33#include "opcode/i386.h"
34
252b5132
RH		 35#ifndef REGISTER_WARNINGS
36#define REGISTER_WARNINGS 1
37#endif
38
c3332e24 39#ifndef INFER_ADDR_PREFIX
eecb386c 40#define INFER_ADDR_PREFIX 1
c3332e24
AM		 41#endif
42
252b5132
RH		 43#ifndef SCALE1_WHEN_NO_INDEX
44/* Specifying a scale factor besides 1 when there is no index is
45 futile. eg. `mov (%ebx,2),%al' does exactly the same as
46 `mov (%ebx),%al'. To slavishly follow what the programmer
47 specified, set SCALE1_WHEN_NO_INDEX to 0. */
48#define SCALE1_WHEN_NO_INDEX 1
49#endif
50
29b0f896
AM		 51#ifdef BFD_ASSEMBLER
52#define RELOC_ENUM enum bfd_reloc_code_real
53#else
54#define RELOC_ENUM int
246fcdee 55#endif
29b0f896
AM		 56
57#ifndef DEFAULT_ARCH
58#define DEFAULT_ARCH "i386"
246fcdee 59#endif
252b5132 60
edde18a5
AM		 61#ifndef INLINE
62#if __GNUC__ >= 2
63#define INLINE __inline__
64#else
65#define INLINE
66#endif
67#endif
68
29b0f896
AM		 69static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
70static INLINE int fits_in_signed_byte PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
72static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
73static INLINE int fits_in_signed_word PARAMS ((offsetT));
74static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
75static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 76static int smallest_imm_type PARAMS ((offsetT));
77static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 78static int add_prefix PARAMS ((unsigned int));
3e73aa7c 79static void set_code_flag PARAMS ((int));
47926f60 80static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 81static void set_intel_syntax PARAMS ((int));
e413e4e9 82static void set_cpu_arch PARAMS ((int));
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
107static void output_imm PARAMS ((void));
108static void output_disp PARAMS ((void));
109#ifndef I386COFF
110static void s_bss PARAMS ((int));
252b5132
RH		 111#endif
112
a847613f 113static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 114
252b5132 115/* 'md_assemble ()' gathers together information and puts it into a
47926f60 116 i386_insn. */
252b5132 117
520dc8e8
AM		 118union i386_op
119 {
120 expressionS *disps;
121 expressionS *imms;
122 const reg_entry *regs;
123 };
124
252b5132
RH		 125struct _i386_insn
126 {
47926f60 127 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 128 template tm;
129
130 /* SUFFIX holds the instruction mnemonic suffix if given.
131 (e.g. 'l' for 'movl') */
132 char suffix;
133
47926f60 134 /* OPERANDS gives the number of given operands. */
252b5132
RH		 135 unsigned int operands;
136
137 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
138 of given register, displacement, memory operands and immediate
47926f60 139 operands. */
252b5132
RH		 140 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
141
142 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 143 use OP[i] for the corresponding operand. */
252b5132
RH		 144 unsigned int types[MAX_OPERANDS];
145
520dc8e8
AM		 146 /* Displacement expression, immediate expression, or register for each
147 operand. */
148 union i386_op op[MAX_OPERANDS];
252b5132 149
3e73aa7c
JH		 150 /* Flags for operands. */
151 unsigned int flags[MAX_OPERANDS];
152#define Operand_PCrel 1
153
252b5132 154 /* Relocation type for operand */
f3c180ae 155 RELOC_ENUM reloc[MAX_OPERANDS];
252b5132 156
252b5132
RH		 157 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
158 the base index byte below. */
159 const reg_entry *base_reg;
160 const reg_entry *index_reg;
161 unsigned int log2_scale_factor;
162
163 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 164 explicit segment overrides are given. */
ce8a8b2f 165 const seg_entry *seg[2];
252b5132
RH		 166
167 /* PREFIX holds all the given prefix opcodes (usually null).
168 PREFIXES is the number of prefix opcodes. */
169 unsigned int prefixes;
170 unsigned char prefix[MAX_PREFIXES];
171
172 /* RM and SIB are the modrm byte and the sib byte where the
173 addressing modes of this insn are encoded. */
174
175 modrm_byte rm;
3e73aa7c 176 rex_byte rex;
252b5132
RH		 177 sib_byte sib;
178 };
179
180typedef struct _i386_insn i386_insn;
181
182/* List of chars besides those in app.c:symbol_chars that can start an
183 operand. Used to prevent the scrubber eating vital white-space. */
184#ifdef LEX_AT
200dbde8 185const char extra_symbol_chars[] = "*%-(@[";
252b5132 186#else
200dbde8 187const char extra_symbol_chars[] = "*%-([";
252b5132
RH		 188#endif
189
29b0f896
AM		 190#if (defined (TE_I386AIX) \
191 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
192 && !defined (TE_LINUX) \
193 && !defined (TE_FreeBSD) \
194 && !defined (TE_NetBSD)))
252b5132 195/* This array holds the chars that always start a comment. If the
ce8a8b2f 196 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 197const char comment_chars[] = "#/";
198#define PREFIX_SEPARATOR '\\'
252b5132
RH		 199
200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
252b5132 208const char line_comment_chars[] = "";
29b0f896 209
252b5132 210#else
29b0f896
AM		 211/* Putting '/' here makes it impossible to use the divide operator.
212 However, we need it for compatibility with SVR4 systems. */
213const char comment_chars[] = "#";
214#define PREFIX_SEPARATOR '/'
215
252b5132
RH		 216const char line_comment_chars[] = "/";
217#endif
218
63a0b638 219const char line_separator_chars[] = ";";
252b5132 220
ce8a8b2f
AM		 221/* Chars that can be used to separate mant from exp in floating point
222 nums. */
252b5132
RH		 223const char EXP_CHARS[] = "eE";
224
ce8a8b2f
AM		 225/* Chars that mean this number is a floating point constant
226 As in 0f12.456
227 or 0d1.2345e12. */
252b5132
RH		 228const char FLT_CHARS[] = "fFdDxX";
229
ce8a8b2f 230/* Tables for lexical analysis. */
252b5132
RH		 231static char mnemonic_chars[256];
232static char register_chars[256];
233static char operand_chars[256];
234static char identifier_chars[256];
235static char digit_chars[256];
236
ce8a8b2f 237/* Lexical macros. */
252b5132
RH		 238#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
239#define is_operand_char(x) (operand_chars[(unsigned char) x])
240#define is_register_char(x) (register_chars[(unsigned char) x])
241#define is_space_char(x) ((x) == ' ')
242#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
243#define is_digit_char(x) (digit_chars[(unsigned char) x])
244
ce8a8b2f 245/* All non-digit non-letter charcters that may occur in an operand. */
252b5132
RH		 246static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
247
248/* md_assemble() always leaves the strings it's passed unaltered. To
249 effect this we maintain a stack of saved characters that we've smashed
250 with '\0's (indicating end of strings for various sub-fields of the
47926f60 251 assembler instruction). */
252b5132 252static char save_stack[32];
ce8a8b2f 253static char *save_stack_p;
252b5132
RH		 254#define END_STRING_AND_SAVE(s) \
255 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
256#define RESTORE_END_STRING(s) \
257 do { *(s) = *--save_stack_p; } while (0)
258
47926f60 259/* The instruction we're assembling. */
252b5132
RH		 260static i386_insn i;
261
262/* Possible templates for current insn. */
263static const templates *current_templates;
264
47926f60 265/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 266static expressionS disp_expressions[2], im_expressions[2];
267
47926f60
KH		 268/* Current operand we are working on. */
269static int this_operand;
252b5132 270
3e73aa7c
JH		 271/* We support four different modes. FLAG_CODE variable is used to distinguish
272 these. */
273
274enum flag_code {
275 CODE_32BIT,
276 CODE_16BIT,
277 CODE_64BIT };
f3c180ae 278#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 279
280static enum flag_code flag_code;
281static int use_rela_relocations = 0;
282
283/* The names used to print error messages. */
b77a7acd 284static const char *flag_code_names[] =
3e73aa7c
JH		 285 {
286 "32",
287 "16",
288 "64"
289 };
252b5132 290
47926f60
KH		 291/* 1 for intel syntax,
292 0 if att syntax. */
293static int intel_syntax = 0;
252b5132 294
47926f60
KH		 295/* 1 if register prefix % not required. */
296static int allow_naked_reg = 0;
252b5132 297
47926f60
KH		 298/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
299 leave, push, and pop instructions so that gcc has the same stack
300 frame as in 32 bit mode. */
301static char stackop_size = '\0';
eecb386c 302
47926f60
KH		 303/* Non-zero to quieten some warnings. */
304static int quiet_warnings = 0;
a38cf1db 305
47926f60
KH		 306/* CPU name. */
307static const char *cpu_arch_name = NULL;
a38cf1db 308
47926f60 309/* CPU feature flags. */
29b0f896 310static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 311
fddf5b5b
AM		 312/* If set, conditional jumps are not automatically promoted to handle
313 larger than a byte offset. */
314static unsigned int no_cond_jump_promotion = 0;
315
29b0f896
AM		 316/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
317symbolS *GOT_symbol;
318
252b5132 319/* Interface to relax_segment.
fddf5b5b
AM		 320 There are 3 major relax states for 386 jump insns because the
321 different types of jumps add different sizes to frags when we're
322 figuring out what sort of jump to choose to reach a given label. */
252b5132 323
47926f60 324/* Types. */
93c2a809
AM		 325#define UNCOND_JUMP 0
326#define COND_JUMP 1
327#define COND_JUMP86 2
fddf5b5b 328
47926f60 329/* Sizes. */
252b5132
RH		 330#define CODE16 1
331#define SMALL 0
29b0f896 332#define SMALL16 (SMALL | CODE16)
252b5132 333#define BIG 2
29b0f896 334#define BIG16 (BIG | CODE16)
252b5132
RH		 335
336#ifndef INLINE
337#ifdef __GNUC__
338#define INLINE __inline__
339#else
340#define INLINE
341#endif
342#endif
343
fddf5b5b
AM		 344#define ENCODE_RELAX_STATE(type, size) \
345 ((relax_substateT) (((type) << 2) | (size)))
346#define TYPE_FROM_RELAX_STATE(s) \
347 ((s) >> 2)
348#define DISP_SIZE_FROM_RELAX_STATE(s) \
349 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 350
351/* This table is used by relax_frag to promote short jumps to long
352 ones where necessary. SMALL (short) jumps may be promoted to BIG
353 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
354 don't allow a short jump in a 32 bit code segment to be promoted to
355 a 16 bit offset jump because it's slower (requires data size
356 prefix), and doesn't work, unless the destination is in the bottom
357 64k of the code segment (The top 16 bits of eip are zeroed). */
358
359const relax_typeS md_relax_table[] =
360{
24eab124
AM		 361 /* The fields are:
362 1) most positive reach of this state,
363 2) most negative reach of this state,
93c2a809 364 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 365 4) which index into the table to try if we can't fit into this one. */
252b5132 366
fddf5b5b 367 /* UNCOND_JUMP states. */
93c2a809
AM		 368 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
369 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
370 /* dword jmp adds 4 bytes to frag:
371 0 extra opcode bytes, 4 displacement bytes. */
252b5132 372 {0, 0, 4, 0},
93c2a809
AM		 373 /* word jmp adds 2 byte2 to frag:
374 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 375 {0, 0, 2, 0},
376
93c2a809
AM		 377 /* COND_JUMP states. */
378 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
379 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
380 /* dword conditionals adds 5 bytes to frag:
381 1 extra opcode byte, 4 displacement bytes. */
382 {0, 0, 5, 0},
fddf5b5b 383 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 384 1 extra opcode byte, 2 displacement bytes. */
385 {0, 0, 3, 0},
386
387 /* COND_JUMP86 states. */
388 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
389 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
390 /* dword conditionals adds 5 bytes to frag:
391 1 extra opcode byte, 4 displacement bytes. */
392 {0, 0, 5, 0},
393 /* word conditionals add 4 bytes to frag:
394 1 displacement byte and a 3 byte long branch insn. */
395 {0, 0, 4, 0}
252b5132
RH		 396};
397
e413e4e9
AM		 398static const arch_entry cpu_arch[] = {
399 {"i8086", Cpu086 },
400 {"i186", Cpu086|Cpu186 },
401 {"i286", Cpu086|Cpu186|Cpu286 },
402 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
403 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
404 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
405 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
406 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
407 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
a167610d 408 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
3e73aa7c
JH		 409 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
410 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
a167610d 411 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
e413e4e9
AM		 412 {NULL, 0 }
413};
414
29b0f896
AM		 415const pseudo_typeS md_pseudo_table[] =
416{
417#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
418 {"align", s_align_bytes, 0},
419#else
420 {"align", s_align_ptwo, 0},
421#endif
422 {"arch", set_cpu_arch, 0},
423#ifndef I386COFF
424 {"bss", s_bss, 0},
425#endif
426 {"ffloat", float_cons, 'f'},
427 {"dfloat", float_cons, 'd'},
428 {"tfloat", float_cons, 'x'},
429 {"value", cons, 2},
430 {"noopt", s_ignore, 0},
431 {"optim", s_ignore, 0},
432 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
433 {"code16", set_code_flag, CODE_16BIT},
434 {"code32", set_code_flag, CODE_32BIT},
435 {"code64", set_code_flag, CODE_64BIT},
436 {"intel_syntax", set_intel_syntax, 1},
437 {"att_syntax", set_intel_syntax, 0},
438 {"file", dwarf2_directive_file, 0},
439 {"loc", dwarf2_directive_loc, 0},
440 {0, 0, 0}
441};
442
443/* For interface with expression (). */
444extern char *input_line_pointer;
445
446/* Hash table for instruction mnemonic lookup. */
447static struct hash_control *op_hash;
448
449/* Hash table for register lookup. */
450static struct hash_control *reg_hash;
451\f
252b5132
RH		 452void
453i386_align_code (fragP, count)
454 fragS *fragP;
455 int count;
456{
ce8a8b2f
AM		 457 /* Various efficient no-op patterns for aligning code labels.
458 Note: Don't try to assemble the instructions in the comments.
459 0L and 0w are not legal. */
252b5132
RH		 460 static const char f32_1[] =
461 {0x90}; /* nop */
462 static const char f32_2[] =
463 {0x89,0xf6}; /* movl %esi,%esi */
464 static const char f32_3[] =
465 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
466 static const char f32_4[] =
467 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
468 static const char f32_5[] =
469 {0x90, /* nop */
470 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
471 static const char f32_6[] =
472 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
473 static const char f32_7[] =
474 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
475 static const char f32_8[] =
476 {0x90, /* nop */
477 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
478 static const char f32_9[] =
479 {0x89,0xf6, /* movl %esi,%esi */
480 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
481 static const char f32_10[] =
482 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
483 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
484 static const char f32_11[] =
485 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
486 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
487 static const char f32_12[] =
488 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
489 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
490 static const char f32_13[] =
491 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
492 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
493 static const char f32_14[] =
494 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
495 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
496 static const char f32_15[] =
497 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
498 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 499 static const char f16_3[] =
500 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 501 static const char f16_4[] =
502 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
503 static const char f16_5[] =
504 {0x90, /* nop */
505 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
506 static const char f16_6[] =
507 {0x89,0xf6, /* mov %si,%si */
508 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
509 static const char f16_7[] =
510 {0x8d,0x74,0x00, /* lea 0(%si),%si */
511 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
512 static const char f16_8[] =
513 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
514 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
515 static const char *const f32_patt[] = {
516 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
517 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
518 };
519 static const char *const f16_patt[] = {
c3332e24 520 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 521 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
522 };
523
3e73aa7c
JH		 524 /* ??? We can't use these fillers for x86_64, since they often kills the
525 upper halves. Solve later. */
526 if (flag_code == CODE_64BIT)
527 count = 1;
528
252b5132
RH		 529 if (count > 0 && count <= 15)
530 {
3e73aa7c 531 if (flag_code == CODE_16BIT)
252b5132 532 {
47926f60
KH		 533 memcpy (fragP->fr_literal + fragP->fr_fix,
534 f16_patt[count - 1], count);
535 if (count > 8)
536 /* Adjust jump offset. */
252b5132
RH		 537 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
538 }
539 else
47926f60
KH		 540 memcpy (fragP->fr_literal + fragP->fr_fix,
541 f32_patt[count - 1], count);
252b5132
RH		 542 fragP->fr_var = count;
543 }
544}
545
252b5132
RH		 546static INLINE unsigned int
547mode_from_disp_size (t)
548 unsigned int t;
549{
3e73aa7c 550 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 551}
552
553static INLINE int
554fits_in_signed_byte (num)
847f7ad4 555 offsetT num;
252b5132
RH		 556{
557 return (num >= -128) && (num <= 127);
47926f60 558}
252b5132
RH		 559
560static INLINE int
561fits_in_unsigned_byte (num)
847f7ad4 562 offsetT num;
252b5132
RH		 563{
564 return (num & 0xff) == num;
47926f60 565}
252b5132
RH		 566
567static INLINE int
568fits_in_unsigned_word (num)
847f7ad4 569 offsetT num;
252b5132
RH		 570{
571 return (num & 0xffff) == num;
47926f60 572}
252b5132
RH		 573
574static INLINE int
575fits_in_signed_word (num)
847f7ad4 576 offsetT num;
252b5132
RH		 577{
578 return (-32768 <= num) && (num <= 32767);
47926f60 579}
3e73aa7c
JH		 580static INLINE int
581fits_in_signed_long (num)
582 offsetT num ATTRIBUTE_UNUSED;
583{
584#ifndef BFD64
585 return 1;
586#else
587 return (!(((offsetT) -1 << 31) & num)
588 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
589#endif
590} /* fits_in_signed_long() */
591static INLINE int
592fits_in_unsigned_long (num)
593 offsetT num ATTRIBUTE_UNUSED;
594{
595#ifndef BFD64
596 return 1;
597#else
598 return (num & (((offsetT) 2 << 31) - 1)) == num;
599#endif
600} /* fits_in_unsigned_long() */
252b5132
RH		 601
602static int
603smallest_imm_type (num)
847f7ad4 604 offsetT num;
252b5132 605{
a847613f 606 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 607 {
608 /* This code is disabled on the 486 because all the Imm1 forms
609 in the opcode table are slower on the i486. They're the
610 versions with the implicitly specified single-position
611 displacement, which has another syntax if you really want to
612 use that form. */
613 if (num == 1)
3e73aa7c 614 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 615 }
252b5132 616 return (fits_in_signed_byte (num)
3e73aa7c 617 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 618 : fits_in_unsigned_byte (num)
3e73aa7c 619 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 620 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 621 ? (Imm16 | Imm32 | Imm32S | Imm64)
622 : fits_in_signed_long (num)
623 ? (Imm32 | Imm32S | Imm64)
624 : fits_in_unsigned_long (num)
625 ? (Imm32 | Imm64)
626 : Imm64);
47926f60 627}
252b5132 628
847f7ad4
AM		 629static offsetT
630offset_in_range (val, size)
631 offsetT val;
632 int size;
633{
508866be 634 addressT mask;
ba2adb93 635
847f7ad4
AM		 636 switch (size)
637 {
508866be
L		 638 case 1: mask = ((addressT) 1 << 8) - 1; break;
639 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 640 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 641#ifdef BFD64
642 case 8: mask = ((addressT) 2 << 63) - 1; break;
643#endif
47926f60 644 default: abort ();
847f7ad4
AM		 645 }
646
ba2adb93 647 /* If BFD64, sign extend val. */
3e73aa7c
JH		 648 if (!use_rela_relocations)
649 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
650 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 651
47926f60 652 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 653 {
654 char buf1[40], buf2[40];
655
656 sprint_value (buf1, val);
657 sprint_value (buf2, val & mask);
658 as_warn (_("%s shortened to %s"), buf1, buf2);
659 }
660 return val & mask;
661}
662
252b5132
RH		 663/* Returns 0 if attempting to add a prefix where one from the same
664 class already exists, 1 if non rep/repne added, 2 if rep/repne
665 added. */
666static int
667add_prefix (prefix)
668 unsigned int prefix;
669{
670 int ret = 1;
671 int q;
672
29b0f896
AM		 673 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
674 && flag_code == CODE_64BIT)
3e73aa7c
JH		 675 q = REX_PREFIX;
676 else
677 switch (prefix)
678 {
679 default:
680 abort ();
681
682 case CS_PREFIX_OPCODE:
683 case DS_PREFIX_OPCODE:
684 case ES_PREFIX_OPCODE:
685 case FS_PREFIX_OPCODE:
686 case GS_PREFIX_OPCODE:
687 case SS_PREFIX_OPCODE:
688 q = SEG_PREFIX;
689 break;
252b5132 690
3e73aa7c
JH		 691 case REPNE_PREFIX_OPCODE:
692 case REPE_PREFIX_OPCODE:
693 ret = 2;
694 /* fall thru */
695 case LOCK_PREFIX_OPCODE:
696 q = LOCKREP_PREFIX;
697 break;
252b5132 698
3e73aa7c
JH		 699 case FWAIT_OPCODE:
700 q = WAIT_PREFIX;
701 break;
252b5132 702
3e73aa7c
JH		 703 case ADDR_PREFIX_OPCODE:
704 q = ADDR_PREFIX;
705 break;
252b5132 706
3e73aa7c
JH		 707 case DATA_PREFIX_OPCODE:
708 q = DATA_PREFIX;
709 break;
710 }
252b5132 711
29b0f896 712 if (i.prefix[q] != 0)
252b5132
RH		 713 {
714 as_bad (_("same type of prefix used twice"));
715 return 0;
716 }
717
718 i.prefixes += 1;
719 i.prefix[q] = prefix;
720 return ret;
721}
722
723static void
3e73aa7c 724set_code_flag (value)
e5cb08ac 725 int value;
eecb386c 726{
3e73aa7c
JH		 727 flag_code = value;
728 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
729 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
730 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
731 {
732 as_bad (_("64bit mode not supported on this CPU."));
733 }
734 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
735 {
736 as_bad (_("32bit mode not supported on this CPU."));
737 }
eecb386c
AM		 738 stackop_size = '\0';
739}
740
741static void
3e73aa7c
JH		 742set_16bit_gcc_code_flag (new_code_flag)
743 int new_code_flag;
252b5132 744{
3e73aa7c
JH		 745 flag_code = new_code_flag;
746 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
747 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
748 stackop_size = 'l';
252b5132
RH		 749}
750
751static void
752set_intel_syntax (syntax_flag)
eecb386c 753 int syntax_flag;
252b5132
RH		 754{
755 /* Find out if register prefixing is specified. */
756 int ask_naked_reg = 0;
757
758 SKIP_WHITESPACE ();
29b0f896 759 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 760 {
761 char *string = input_line_pointer;
762 int e = get_symbol_end ();
763
47926f60 764 if (strcmp (string, "prefix") == 0)
252b5132 765 ask_naked_reg = 1;
47926f60 766 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 767 ask_naked_reg = -1;
768 else
d0b47220 769 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 770 *input_line_pointer = e;
771 }
772 demand_empty_rest_of_line ();
c3332e24 773
252b5132
RH		 774 intel_syntax = syntax_flag;
775
776 if (ask_naked_reg == 0)
777 {
778#ifdef BFD_ASSEMBLER
779 allow_naked_reg = (intel_syntax
24eab124 780 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132 781#else
47926f60
KH		 782 /* Conservative default. */
783 allow_naked_reg = 0;
252b5132
RH		 784#endif
785 }
786 else
787 allow_naked_reg = (ask_naked_reg < 0);
788}
789
e413e4e9
AM		 790static void
791set_cpu_arch (dummy)
47926f60 792 int dummy ATTRIBUTE_UNUSED;
e413e4e9 793{
47926f60 794 SKIP_WHITESPACE ();
e413e4e9 795
29b0f896 796 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 797 {
798 char *string = input_line_pointer;
799 int e = get_symbol_end ();
800 int i;
801
802 for (i = 0; cpu_arch[i].name; i++)
803 {
804 if (strcmp (string, cpu_arch[i].name) == 0)
805 {
806 cpu_arch_name = cpu_arch[i].name;
fddf5b5b
AM		 807 cpu_arch_flags = (cpu_arch[i].flags
808 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
e413e4e9
AM		 809 break;
810 }
811 }
812 if (!cpu_arch[i].name)
813 as_bad (_("no such architecture: `%s'"), string);
814
815 *input_line_pointer = e;
816 }
817 else
818 as_bad (_("missing cpu architecture"));
819
fddf5b5b
AM		 820 no_cond_jump_promotion = 0;
821 if (*input_line_pointer == ','
29b0f896 822 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 823 {
824 char *string = ++input_line_pointer;
825 int e = get_symbol_end ();
826
827 if (strcmp (string, "nojumps") == 0)
828 no_cond_jump_promotion = 1;
829 else if (strcmp (string, "jumps") == 0)
830 ;
831 else
832 as_bad (_("no such architecture modifier: `%s'"), string);
833
834 *input_line_pointer = e;
835 }
836
e413e4e9
AM		 837 demand_empty_rest_of_line ();
838}
839
b9d79e03
JH		 840#ifdef BFD_ASSEMBLER
841unsigned long
842i386_mach ()
843{
844 if (!strcmp (default_arch, "x86_64"))
845 return bfd_mach_x86_64;
846 else if (!strcmp (default_arch, "i386"))
847 return bfd_mach_i386_i386;
848 else
849 as_fatal (_("Unknown architecture"));
850}
851#endif
852\f
252b5132
RH		 853void
854md_begin ()
855{
856 const char *hash_err;
857
47926f60 858 /* Initialize op_hash hash table. */
252b5132
RH		 859 op_hash = hash_new ();
860
861 {
29b0f896
AM		 862 const template *optab;
863 templates *core_optab;
252b5132 864
47926f60
KH		 865 /* Setup for loop. */
866 optab = i386_optab;
252b5132
RH		 867 core_optab = (templates *) xmalloc (sizeof (templates));
868 core_optab->start = optab;
869
870 while (1)
871 {
872 ++optab;
873 if (optab->name == NULL
874 || strcmp (optab->name, (optab - 1)->name) != 0)
875 {
876 /* different name --> ship out current template list;
47926f60 877 add to hash table; & begin anew. */
252b5132
RH		 878 core_optab->end = optab;
879 hash_err = hash_insert (op_hash,
880 (optab - 1)->name,
881 (PTR) core_optab);
882 if (hash_err)
883 {
252b5132
RH		 884 as_fatal (_("Internal Error: Can't hash %s: %s"),
885 (optab - 1)->name,
886 hash_err);
887 }
888 if (optab->name == NULL)
889 break;
890 core_optab = (templates *) xmalloc (sizeof (templates));
891 core_optab->start = optab;
892 }
893 }
894 }
895
47926f60 896 /* Initialize reg_hash hash table. */
252b5132
RH		 897 reg_hash = hash_new ();
898 {
29b0f896 899 const reg_entry *regtab;
252b5132
RH		 900
901 for (regtab = i386_regtab;
902 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
903 regtab++)
904 {
905 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
906 if (hash_err)
3e73aa7c
JH		 907 as_fatal (_("Internal Error: Can't hash %s: %s"),
908 regtab->reg_name,
909 hash_err);
252b5132
RH		 910 }
911 }
912
47926f60 913 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 914 {
29b0f896
AM		 915 int c;
916 char *p;
252b5132
RH		 917
918 for (c = 0; c < 256; c++)
919 {
3882b010 920 if (ISDIGIT (c))
252b5132
RH		 921 {
922 digit_chars[c] = c;
923 mnemonic_chars[c] = c;
924 register_chars[c] = c;
925 operand_chars[c] = c;
926 }
3882b010 927 else if (ISLOWER (c))
252b5132
RH		 928 {
929 mnemonic_chars[c] = c;
930 register_chars[c] = c;
931 operand_chars[c] = c;
932 }
3882b010 933 else if (ISUPPER (c))
252b5132 934 {
3882b010 935 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 936 register_chars[c] = mnemonic_chars[c];
937 operand_chars[c] = c;
938 }
939
3882b010 940 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 941 identifier_chars[c] = c;
942 else if (c >= 128)
943 {
944 identifier_chars[c] = c;
945 operand_chars[c] = c;
946 }
947 }
948
949#ifdef LEX_AT
950 identifier_chars['@'] = '@';
951#endif
252b5132
RH		 952 digit_chars['-'] = '-';
953 identifier_chars['_'] = '_';
954 identifier_chars['.'] = '.';
955
956 for (p = operand_special_chars; *p != '\0'; p++)
957 operand_chars[(unsigned char) *p] = *p;
958 }
959
960#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
961 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
962 {
963 record_alignment (text_section, 2);
964 record_alignment (data_section, 2);
965 record_alignment (bss_section, 2);
966 }
967#endif
968}
969
970void
971i386_print_statistics (file)
972 FILE *file;
973{
974 hash_print_statistics (file, "i386 opcode", op_hash);
975 hash_print_statistics (file, "i386 register", reg_hash);
976}
977\f
252b5132
RH		 978#ifdef DEBUG386
979
ce8a8b2f 980/* Debugging routines for md_assemble. */
252b5132
RH		 981static void pi PARAMS ((char *, i386_insn *));
982static void pte PARAMS ((template *));
983static void pt PARAMS ((unsigned int));
984static void pe PARAMS ((expressionS *));
985static void ps PARAMS ((symbolS *));
986
987static void
988pi (line, x)
989 char *line;
990 i386_insn *x;
991{
09f131f2 992 unsigned int i;
252b5132
RH		 993
994 fprintf (stdout, "%s: template ", line);
995 pte (&x->tm);
09f131f2
JH		 996 fprintf (stdout, " address: base %s index %s scale %x\n",
997 x->base_reg ? x->base_reg->reg_name : "none",
998 x->index_reg ? x->index_reg->reg_name : "none",
999 x->log2_scale_factor);
1000 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1001 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1002 fprintf (stdout, " sib: base %x index %x scale %x\n",
1003 x->sib.base, x->sib.index, x->sib.scale);
1004 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1005 (x->rex & REX_MODE64) != 0,
1006 (x->rex & REX_EXTX) != 0,
1007 (x->rex & REX_EXTY) != 0,
1008 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1009 for (i = 0; i < x->operands; i++)
1010 {
1011 fprintf (stdout, " #%d: ", i + 1);
1012 pt (x->types[i]);
1013 fprintf (stdout, "\n");
1014 if (x->types[i]
3f4438ab 1015 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1016 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1017 if (x->types[i] & Imm)
520dc8e8 1018 pe (x->op[i].imms);
252b5132 1019 if (x->types[i] & Disp)
520dc8e8 1020 pe (x->op[i].disps);
252b5132
RH		 1021 }
1022}
1023
1024static void
1025pte (t)
1026 template *t;
1027{
09f131f2 1028 unsigned int i;
252b5132 1029 fprintf (stdout, " %d operands ", t->operands);
47926f60 1030 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1031 if (t->extension_opcode != None)
1032 fprintf (stdout, "ext %x ", t->extension_opcode);
1033 if (t->opcode_modifier & D)
1034 fprintf (stdout, "D");
1035 if (t->opcode_modifier & W)
1036 fprintf (stdout, "W");
1037 fprintf (stdout, "\n");
1038 for (i = 0; i < t->operands; i++)
1039 {
1040 fprintf (stdout, " #%d type ", i + 1);
1041 pt (t->operand_types[i]);
1042 fprintf (stdout, "\n");
1043 }
1044}
1045
1046static void
1047pe (e)
1048 expressionS *e;
1049{
24eab124 1050 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1051 fprintf (stdout, " add_number %ld (%lx)\n",
1052 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1053 if (e->X_add_symbol)
1054 {
1055 fprintf (stdout, " add_symbol ");
1056 ps (e->X_add_symbol);
1057 fprintf (stdout, "\n");
1058 }
1059 if (e->X_op_symbol)
1060 {
1061 fprintf (stdout, " op_symbol ");
1062 ps (e->X_op_symbol);
1063 fprintf (stdout, "\n");
1064 }
1065}
1066
1067static void
1068ps (s)
1069 symbolS *s;
1070{
1071 fprintf (stdout, "%s type %s%s",
1072 S_GET_NAME (s),
1073 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1074 segment_name (S_GET_SEGMENT (s)));
1075}
1076
1077struct type_name
1078 {
1079 unsigned int mask;
1080 char *tname;
1081 }
1082
29b0f896 1083static const type_names[] =
252b5132
RH		 1084{
1085 { Reg8, "r8" },
1086 { Reg16, "r16" },
1087 { Reg32, "r32" },
09f131f2 1088 { Reg64, "r64" },
252b5132
RH		 1089 { Imm8, "i8" },
1090 { Imm8S, "i8s" },
1091 { Imm16, "i16" },
1092 { Imm32, "i32" },
09f131f2
JH		 1093 { Imm32S, "i32s" },
1094 { Imm64, "i64" },
252b5132
RH		 1095 { Imm1, "i1" },
1096 { BaseIndex, "BaseIndex" },
1097 { Disp8, "d8" },
1098 { Disp16, "d16" },
1099 { Disp32, "d32" },
09f131f2
JH		 1100 { Disp32S, "d32s" },
1101 { Disp64, "d64" },
252b5132
RH		 1102 { InOutPortReg, "InOutPortReg" },
1103 { ShiftCount, "ShiftCount" },
1104 { Control, "control reg" },
1105 { Test, "test reg" },
1106 { Debug, "debug reg" },
1107 { FloatReg, "FReg" },
1108 { FloatAcc, "FAcc" },
1109 { SReg2, "SReg2" },
1110 { SReg3, "SReg3" },
1111 { Acc, "Acc" },
1112 { JumpAbsolute, "Jump Absolute" },
1113 { RegMMX, "rMMX" },
3f4438ab 1114 { RegXMM, "rXMM" },
252b5132
RH		 1115 { EsSeg, "es" },
1116 { 0, "" }
1117};
1118
1119static void
1120pt (t)
1121 unsigned int t;
1122{
29b0f896 1123 const struct type_name *ty;
252b5132 1124
09f131f2
JH		 1125 for (ty = type_names; ty->mask; ty++)
1126 if (t & ty->mask)
1127 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1128 fflush (stdout);
1129}
1130
1131#endif /* DEBUG386 */
1132\f
1133int
1134tc_i386_force_relocation (fixp)
1135 struct fix *fixp;
1136{
1137#ifdef BFD_ASSEMBLER
1138 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1139 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1140 return 1;
1141 return 0;
1142#else
ce8a8b2f 1143 /* For COFF. */
f6af82bd 1144 return fixp->fx_r_type == 7;
252b5132
RH		 1145#endif
1146}
1147
1148#ifdef BFD_ASSEMBLER
29b0f896
AM		 1149static bfd_reloc_code_real_type reloc
1150 PARAMS ((int, int, int, bfd_reloc_code_real_type));
252b5132
RH		 1151
1152static bfd_reloc_code_real_type
3e73aa7c 1153reloc (size, pcrel, sign, other)
252b5132
RH		 1154 int size;
1155 int pcrel;
3e73aa7c 1156 int sign;
252b5132
RH		 1157 bfd_reloc_code_real_type other;
1158{
47926f60
KH		 1159 if (other != NO_RELOC)
1160 return other;
252b5132
RH		 1161
1162 if (pcrel)
1163 {
3e73aa7c 1164 if (!sign)
e5cb08ac 1165 as_bad (_("There are no unsigned pc-relative relocations"));
252b5132
RH		 1166 switch (size)
1167 {
1168 case 1: return BFD_RELOC_8_PCREL;
1169 case 2: return BFD_RELOC_16_PCREL;
1170 case 4: return BFD_RELOC_32_PCREL;
1171 }
d0b47220 1172 as_bad (_("can not do %d byte pc-relative relocation"), size);
252b5132
RH		 1173 }
1174 else
1175 {
3e73aa7c 1176 if (sign)
e5cb08ac 1177 switch (size)
3e73aa7c
JH		 1178 {
1179 case 4: return BFD_RELOC_X86_64_32S;
1180 }
1181 else
1182 switch (size)
1183 {
1184 case 1: return BFD_RELOC_8;
1185 case 2: return BFD_RELOC_16;
1186 case 4: return BFD_RELOC_32;
1187 case 8: return BFD_RELOC_64;
1188 }
1189 as_bad (_("can not do %s %d byte relocation"),
1190 sign ? "signed" : "unsigned", size);
252b5132
RH		 1191 }
1192
bfb32b52 1193 abort ();
252b5132
RH		 1194 return BFD_RELOC_NONE;
1195}
1196
47926f60
KH		 1197/* Here we decide which fixups can be adjusted to make them relative to
1198 the beginning of the section instead of the symbol. Basically we need
1199 to make sure that the dynamic relocations are done correctly, so in
1200 some cases we force the original symbol to be used. */
1201
252b5132 1202int
c0c949c7 1203tc_i386_fix_adjustable (fixP)
47926f60 1204 fixS *fixP;
252b5132 1205{
6d249963 1206#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
79d292aa
ILT		 1207 /* Prevent all adjustments to global symbols, or else dynamic
1208 linking will not work correctly. */
b98ef147 1209 if (S_IS_EXTERNAL (fixP->fx_addsy)
3bf057fa
AS		 1210 || S_IS_WEAK (fixP->fx_addsy)
1211 /* Don't adjust pc-relative references to merge sections in 64-bit
1212 mode. */
1213 || (use_rela_relocations
1214 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1215 && fixP->fx_pcrel))
252b5132
RH		 1216 return 0;
1217#endif
ce8a8b2f 1218 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1219 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1220 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1221 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1222 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1223 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1224 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1225 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1226 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1227 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1228 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1229 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1230 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
252b5132
RH		 1231 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1232 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1233 return 0;
1234 return 1;
1235}
1236#else
ec56dfb4
L		 1237#define reloc(SIZE,PCREL,SIGN,OTHER) 0
1238#define BFD_RELOC_16 0
1239#define BFD_RELOC_32 0
1240#define BFD_RELOC_16_PCREL 0
1241#define BFD_RELOC_32_PCREL 0
1242#define BFD_RELOC_386_PLT32 0
1243#define BFD_RELOC_386_GOT32 0
1244#define BFD_RELOC_386_GOTOFF 0
13ae64f3
JJ		 1245#define BFD_RELOC_386_TLS_GD 0
1246#define BFD_RELOC_386_TLS_LDM 0
1247#define BFD_RELOC_386_TLS_LDO_32 0
1248#define BFD_RELOC_386_TLS_IE_32 0
1249#define BFD_RELOC_386_TLS_LE_32 0
1250#define BFD_RELOC_386_TLS_LE 0
ec56dfb4
L		 1251#define BFD_RELOC_X86_64_PLT32 0
1252#define BFD_RELOC_X86_64_GOT32 0
1253#define BFD_RELOC_X86_64_GOTPCREL 0
252b5132
RH		 1254#endif
1255
29b0f896 1256static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1257
1258static int
252b5132 1259intel_float_operand (mnemonic)
29b0f896 1260 const char *mnemonic;
252b5132 1261{
47926f60 1262 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
cc5ca5ce 1263 return 2;
252b5132
RH		 1264
1265 if (mnemonic[0] == 'f')
1266 return 1;
1267
1268 return 0;
1269}
1270
1271/* This is the guts of the machine-dependent assembler. LINE points to a
1272 machine dependent instruction. This function is supposed to emit
1273 the frags/bytes it assembles to. */
1274
1275void
1276md_assemble (line)
1277 char *line;
1278{
252b5132 1279 int j;
252b5132
RH		 1280 char mnemonic[MAX_MNEM_SIZE];
1281
47926f60 1282 /* Initialize globals. */
252b5132
RH		 1283 memset (&i, '\0', sizeof (i));
1284 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1285 i.reloc[j] = NO_RELOC;
252b5132
RH		 1286 memset (disp_expressions, '\0', sizeof (disp_expressions));
1287 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1288 save_stack_p = save_stack;
252b5132
RH		 1289
1290 /* First parse an instruction mnemonic & call i386_operand for the operands.
1291 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1292 start of a (possibly prefixed) mnemonic. */
252b5132 1293
29b0f896
AM		 1294 line = parse_insn (line, mnemonic);
1295 if (line == NULL)
1296 return;
252b5132 1297
29b0f896
AM		 1298 line = parse_operands (line, mnemonic);
1299 if (line == NULL)
1300 return;
252b5132 1301
29b0f896
AM		 1302 /* Now we've parsed the mnemonic into a set of templates, and have the
1303 operands at hand. */
1304
1305 /* All intel opcodes have reversed operands except for "bound" and
1306 "enter". We also don't reverse intersegment "jmp" and "call"
1307 instructions with 2 immediate operands so that the immediate segment
1308 precedes the offset, as it does when in AT&T mode. "enter" and the
1309 intersegment "jmp" and "call" instructions are the only ones that
1310 have two immediate operands. */
1311 if (intel_syntax && i.operands > 1
1312 && (strcmp (mnemonic, "bound") != 0)
1313 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1314 swap_operands ();
1315
1316 if (i.imm_operands)
1317 optimize_imm ();
1318
1319 if (i.disp_operands)
1320 optimize_disp ();
1321
1322 /* Next, we find a template that matches the given insn,
1323 making sure the overlap of the given operands types is consistent
1324 with the template operand types. */
252b5132 1325
29b0f896
AM		 1326 if (!match_template ())
1327 return;
252b5132 1328
cd61ebfe
AM		 1329 if (intel_syntax)
1330 {
1331 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1332 if (SYSV386_COMPAT
1333 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1334 i.tm.base_opcode ^= FloatR;
1335
1336 /* Zap movzx and movsx suffix. The suffix may have been set from
1337 "word ptr" or "byte ptr" on the source operand, but we'll use
1338 the suffix later to choose the destination register. */
1339 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1340 i.suffix = 0;
1341 }
24eab124 1342
29b0f896
AM		 1343 if (i.tm.opcode_modifier & FWait)
1344 if (!add_prefix (FWAIT_OPCODE))
1345 return;
252b5132 1346
29b0f896
AM		 1347 /* Check string instruction segment overrides. */
1348 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1349 {
1350 if (!check_string ())
5dd0794d 1351 return;
29b0f896 1352 }
5dd0794d 1353
29b0f896
AM		 1354 if (!process_suffix ())
1355 return;
e413e4e9 1356
29b0f896
AM		 1357 /* Make still unresolved immediate matches conform to size of immediate
1358 given in i.suffix. */
1359 if (!finalize_imm ())
1360 return;
252b5132 1361
29b0f896
AM		 1362 if (i.types[0] & Imm1)
1363 i.imm_operands = 0; /* kludge for shift insns. */
1364 if (i.types[0] & ImplicitRegister)
1365 i.reg_operands--;
1366 if (i.types[1] & ImplicitRegister)
1367 i.reg_operands--;
1368 if (i.types[2] & ImplicitRegister)
1369 i.reg_operands--;
252b5132 1370
29b0f896
AM		 1371 if (i.tm.opcode_modifier & ImmExt)
1372 {
1373 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1374 opcode suffix which is coded in the same place as an 8-bit
1375 immediate field would be. Here we fake an 8-bit immediate
1376 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1377
29b0f896 1378 expressionS *exp;
252b5132 1379
29b0f896 1380 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1381
29b0f896
AM		 1382 exp = &im_expressions[i.imm_operands++];
1383 i.op[i.operands].imms = exp;
1384 i.types[i.operands++] = Imm8;
1385 exp->X_op = O_constant;
1386 exp->X_add_number = i.tm.extension_opcode;
1387 i.tm.extension_opcode = None;
1388 }
252b5132 1389
29b0f896
AM		 1390 /* For insns with operands there are more diddles to do to the opcode. */
1391 if (i.operands)
1392 {
1393 if (!process_operands ())
1394 return;
1395 }
1396 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1397 {
1398 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1399 as_warn (_("translating to `%sp'"), i.tm.name);
1400 }
252b5132 1401
29b0f896
AM		 1402 /* Handle conversion of 'int $3' --> special int3 insn. */
1403 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1404 {
1405 i.tm.base_opcode = INT3_OPCODE;
1406 i.imm_operands = 0;
1407 }
252b5132 1408
29b0f896
AM		 1409 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1410 && i.op[0].disps->X_op == O_constant)
1411 {
1412 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1413 the absolute address given by the constant. Since ix86 jumps and
1414 calls are pc relative, we need to generate a reloc. */
1415 i.op[0].disps->X_add_symbol = &abs_symbol;
1416 i.op[0].disps->X_op = O_symbol;
1417 }
252b5132 1418
29b0f896
AM		 1419 if ((i.tm.opcode_modifier & Rex64) != 0)
1420 i.rex |= REX_MODE64;
252b5132 1421
29b0f896
AM		 1422 /* For 8 bit registers we need an empty rex prefix. Also if the
1423 instruction already has a prefix, we need to convert old
1424 registers to new ones. */
773f551c 1425
29b0f896
AM		 1426 if (((i.types[0] & Reg8) != 0
1427 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1428 || ((i.types[1] & Reg8) != 0
1429 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1430 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1431 && i.rex != 0))
1432 {
1433 int x;
726c5dcd 1434
29b0f896
AM		 1435 i.rex |= REX_OPCODE;
1436 for (x = 0; x < 2; x++)
1437 {
1438 /* Look for 8 bit operand that uses old registers. */
1439 if ((i.types[x] & Reg8) != 0
1440 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1441 {
29b0f896
AM		 1442 /* In case it is "hi" register, give up. */
1443 if (i.op[x].regs->reg_num > 3)
1444 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1445 i.op[x].regs->reg_name);
773f551c 1446
29b0f896
AM		 1447 /* Otherwise it is equivalent to the extended register.
1448 Since the encoding doesn't change this is merely
1449 cosmetic cleanup for debug output. */
1450
1451 i.op[x].regs = i.op[x].regs + 8;
773f551c 1452 }
29b0f896
AM		 1453 }
1454 }
773f551c 1455
29b0f896
AM		 1456 if (i.rex != 0)
1457 add_prefix (REX_OPCODE | i.rex);
1458
1459 /* We are ready to output the insn. */
1460 output_insn ();
1461}
1462
1463static char *
1464parse_insn (line, mnemonic)
1465 char *line;
1466 char *mnemonic;
1467{
1468 char *l = line;
1469 char *token_start = l;
1470 char *mnem_p;
1471
1472 /* Non-zero if we found a prefix only acceptable with string insns. */
1473 const char *expecting_string_instruction = NULL;
45288df1 1474
29b0f896
AM		 1475 while (1)
1476 {
1477 mnem_p = mnemonic;
1478 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1479 {
1480 mnem_p++;
1481 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1482 {
29b0f896
AM		 1483 as_bad (_("no such instruction: `%s'"), token_start);
1484 return NULL;
1485 }
1486 l++;
1487 }
1488 if (!is_space_char (*l)
1489 && *l != END_OF_INSN
1490 && *l != PREFIX_SEPARATOR
1491 && *l != ',')
1492 {
1493 as_bad (_("invalid character %s in mnemonic"),
1494 output_invalid (*l));
1495 return NULL;
1496 }
1497 if (token_start == l)
1498 {
1499 if (*l == PREFIX_SEPARATOR)
1500 as_bad (_("expecting prefix; got nothing"));
1501 else
1502 as_bad (_("expecting mnemonic; got nothing"));
1503 return NULL;
1504 }
45288df1 1505
29b0f896
AM		 1506 /* Look up instruction (or prefix) via hash table. */
1507 current_templates = hash_find (op_hash, mnemonic);
47926f60 1508
29b0f896
AM		 1509 if (*l != END_OF_INSN
1510 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1511 && current_templates
1512 && (current_templates->start->opcode_modifier & IsPrefix))
1513 {
1514 /* If we are in 16-bit mode, do not allow addr16 or data16.
1515 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1516 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1517 && flag_code != CODE_64BIT
1518 && (((current_templates->start->opcode_modifier & Size32) != 0)
1519 ^ (flag_code == CODE_16BIT)))
1520 {
1521 as_bad (_("redundant %s prefix"),
1522 current_templates->start->name);
1523 return NULL;
45288df1 1524 }
29b0f896
AM		 1525 /* Add prefix, checking for repeated prefixes. */
1526 switch (add_prefix (current_templates->start->base_opcode))
1527 {
1528 case 0:
1529 return NULL;
1530 case 2:
1531 expecting_string_instruction = current_templates->start->name;
1532 break;
1533 }
1534 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1535 token_start = ++l;
1536 }
1537 else
1538 break;
1539 }
45288df1 1540
29b0f896
AM		 1541 if (!current_templates)
1542 {
1543 /* See if we can get a match by trimming off a suffix. */
1544 switch (mnem_p[-1])
1545 {
1546 case WORD_MNEM_SUFFIX:
1547 case BYTE_MNEM_SUFFIX:
1548 case QWORD_MNEM_SUFFIX:
1549 i.suffix = mnem_p[-1];
1550 mnem_p[-1] = '\0';
1551 current_templates = hash_find (op_hash, mnemonic);
1552 break;
1553 case SHORT_MNEM_SUFFIX:
1554 case LONG_MNEM_SUFFIX:
1555 if (!intel_syntax)
1556 {
1557 i.suffix = mnem_p[-1];
1558 mnem_p[-1] = '\0';
1559 current_templates = hash_find (op_hash, mnemonic);
1560 }
1561 break;
252b5132 1562
29b0f896
AM		 1563 /* Intel Syntax. */
1564 case 'd':
1565 if (intel_syntax)
1566 {
1567 if (intel_float_operand (mnemonic))
1568 i.suffix = SHORT_MNEM_SUFFIX;
1569 else
1570 i.suffix = LONG_MNEM_SUFFIX;
1571 mnem_p[-1] = '\0';
1572 current_templates = hash_find (op_hash, mnemonic);
1573 }
1574 break;
1575 }
1576 if (!current_templates)
1577 {
1578 as_bad (_("no such instruction: `%s'"), token_start);
1579 return NULL;
1580 }
1581 }
252b5132 1582
29b0f896
AM		 1583 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1584 {
1585 /* Check for a branch hint. We allow ",pt" and ",pn" for
1586 predict taken and predict not taken respectively.
1587 I'm not sure that branch hints actually do anything on loop
1588 and jcxz insns (JumpByte) for current Pentium4 chips. They
1589 may work in the future and it doesn't hurt to accept them
1590 now. */
1591 if (l[0] == ',' && l[1] == 'p')
1592 {
1593 if (l[2] == 't')
1594 {
1595 if (!add_prefix (DS_PREFIX_OPCODE))
1596 return NULL;
1597 l += 3;
1598 }
1599 else if (l[2] == 'n')
1600 {
1601 if (!add_prefix (CS_PREFIX_OPCODE))
1602 return NULL;
1603 l += 3;
1604 }
1605 }
1606 }
1607 /* Any other comma loses. */
1608 if (*l == ',')
1609 {
1610 as_bad (_("invalid character %s in mnemonic"),
1611 output_invalid (*l));
1612 return NULL;
1613 }
252b5132 1614
29b0f896
AM		 1615 /* Check if instruction is supported on specified architecture. */
1616 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1617 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1618 {
1619 as_warn (_("`%s' is not supported on `%s'"),
1620 current_templates->start->name, cpu_arch_name);
1621 }
1622 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1623 {
1624 as_warn (_("use .code16 to ensure correct addressing mode"));
1625 }
252b5132 1626
29b0f896
AM		 1627 /* Check for rep/repne without a string instruction. */
1628 if (expecting_string_instruction
1629 && !(current_templates->start->opcode_modifier & IsString))
1630 {
1631 as_bad (_("expecting string instruction after `%s'"),
1632 expecting_string_instruction);
1633 return NULL;
1634 }
252b5132 1635
29b0f896
AM		 1636 return l;
1637}
252b5132 1638
29b0f896
AM		 1639static char *
1640parse_operands (l, mnemonic)
1641 char *l;
1642 const char *mnemonic;
1643{
1644 char *token_start;
3138f287 1645
29b0f896
AM		 1646 /* 1 if operand is pending after ','. */
1647 unsigned int expecting_operand = 0;
252b5132 1648
29b0f896
AM		 1649 /* Non-zero if operand parens not balanced. */
1650 unsigned int paren_not_balanced;
1651
1652 while (*l != END_OF_INSN)
1653 {
1654 /* Skip optional white space before operand. */
1655 if (is_space_char (*l))
1656 ++l;
1657 if (!is_operand_char (*l) && *l != END_OF_INSN)
1658 {
1659 as_bad (_("invalid character %s before operand %d"),
1660 output_invalid (*l),
1661 i.operands + 1);
1662 return NULL;
1663 }
1664 token_start = l; /* after white space */
1665 paren_not_balanced = 0;
1666 while (paren_not_balanced || *l != ',')
1667 {
1668 if (*l == END_OF_INSN)
1669 {
1670 if (paren_not_balanced)
1671 {
1672 if (!intel_syntax)
1673 as_bad (_("unbalanced parenthesis in operand %d."),
1674 i.operands + 1);
1675 else
1676 as_bad (_("unbalanced brackets in operand %d."),
1677 i.operands + 1);
1678 return NULL;
1679 }
1680 else
1681 break; /* we are done */
1682 }
1683 else if (!is_operand_char (*l) && !is_space_char (*l))
1684 {
1685 as_bad (_("invalid character %s in operand %d"),
1686 output_invalid (*l),
1687 i.operands + 1);
1688 return NULL;
1689 }
1690 if (!intel_syntax)
1691 {
1692 if (*l == '(')
1693 ++paren_not_balanced;
1694 if (*l == ')')
1695 --paren_not_balanced;
1696 }
1697 else
1698 {
1699 if (*l == '[')
1700 ++paren_not_balanced;
1701 if (*l == ']')
1702 --paren_not_balanced;
1703 }
1704 l++;
1705 }
1706 if (l != token_start)
1707 { /* Yes, we've read in another operand. */
1708 unsigned int operand_ok;
1709 this_operand = i.operands++;
1710 if (i.operands > MAX_OPERANDS)
1711 {
1712 as_bad (_("spurious operands; (%d operands/instruction max)"),
1713 MAX_OPERANDS);
1714 return NULL;
1715 }
1716 /* Now parse operand adding info to 'i' as we go along. */
1717 END_STRING_AND_SAVE (l);
1718
1719 if (intel_syntax)
1720 operand_ok =
1721 i386_intel_operand (token_start,
1722 intel_float_operand (mnemonic));
1723 else
1724 operand_ok = i386_operand (token_start);
1725
1726 RESTORE_END_STRING (l);
1727 if (!operand_ok)
1728 return NULL;
1729 }
1730 else
1731 {
1732 if (expecting_operand)
1733 {
1734 expecting_operand_after_comma:
1735 as_bad (_("expecting operand after ','; got nothing"));
1736 return NULL;
1737 }
1738 if (*l == ',')
1739 {
1740 as_bad (_("expecting operand before ','; got nothing"));
1741 return NULL;
1742 }
1743 }
7f3f1ea2 1744
29b0f896
AM		 1745 /* Now *l must be either ',' or END_OF_INSN. */
1746 if (*l == ',')
1747 {
1748 if (*++l == END_OF_INSN)
1749 {
1750 /* Just skip it, if it's \n complain. */
1751 goto expecting_operand_after_comma;
1752 }
1753 expecting_operand = 1;
1754 }
1755 }
1756 return l;
1757}
7f3f1ea2 1758
29b0f896
AM		 1759static void
1760swap_operands ()
1761{
1762 union i386_op temp_op;
1763 unsigned int temp_type;
1764 RELOC_ENUM temp_reloc;
1765 int xchg1 = 0;
1766 int xchg2 = 0;
252b5132 1767
29b0f896
AM		 1768 if (i.operands == 2)
1769 {
1770 xchg1 = 0;
1771 xchg2 = 1;
1772 }
1773 else if (i.operands == 3)
1774 {
1775 xchg1 = 0;
1776 xchg2 = 2;
1777 }
1778 temp_type = i.types[xchg2];
1779 i.types[xchg2] = i.types[xchg1];
1780 i.types[xchg1] = temp_type;
1781 temp_op = i.op[xchg2];
1782 i.op[xchg2] = i.op[xchg1];
1783 i.op[xchg1] = temp_op;
1784 temp_reloc = i.reloc[xchg2];
1785 i.reloc[xchg2] = i.reloc[xchg1];
1786 i.reloc[xchg1] = temp_reloc;
1787
1788 if (i.mem_operands == 2)
1789 {
1790 const seg_entry *temp_seg;
1791 temp_seg = i.seg[0];
1792 i.seg[0] = i.seg[1];
1793 i.seg[1] = temp_seg;
1794 }
1795}
252b5132 1796
29b0f896
AM		 1797/* Try to ensure constant immediates are represented in the smallest
1798 opcode possible. */
1799static void
1800optimize_imm ()
1801{
1802 char guess_suffix = 0;
1803 int op;
252b5132 1804
29b0f896
AM		 1805 if (i.suffix)
1806 guess_suffix = i.suffix;
1807 else if (i.reg_operands)
1808 {
1809 /* Figure out a suffix from the last register operand specified.
1810 We can't do this properly yet, ie. excluding InOutPortReg,
1811 but the following works for instructions with immediates.
1812 In any case, we can't set i.suffix yet. */
1813 for (op = i.operands; --op >= 0;)
1814 if (i.types[op] & Reg)
252b5132 1815 {
29b0f896
AM		 1816 if (i.types[op] & Reg8)
1817 guess_suffix = BYTE_MNEM_SUFFIX;
1818 else if (i.types[op] & Reg16)
1819 guess_suffix = WORD_MNEM_SUFFIX;
1820 else if (i.types[op] & Reg32)
1821 guess_suffix = LONG_MNEM_SUFFIX;
1822 else if (i.types[op] & Reg64)
1823 guess_suffix = QWORD_MNEM_SUFFIX;
1824 break;
252b5132 1825 }
29b0f896
AM		 1826 }
1827 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1828 guess_suffix = WORD_MNEM_SUFFIX;
1829
1830 for (op = i.operands; --op >= 0;)
1831 if (i.types[op] & Imm)
1832 {
1833 switch (i.op[op].imms->X_op)
252b5132 1834 {
29b0f896
AM		 1835 case O_constant:
1836 /* If a suffix is given, this operand may be shortened. */
1837 switch (guess_suffix)
252b5132 1838 {
29b0f896
AM		 1839 case LONG_MNEM_SUFFIX:
1840 i.types[op] |= Imm32 | Imm64;
1841 break;
1842 case WORD_MNEM_SUFFIX:
1843 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1844 break;
1845 case BYTE_MNEM_SUFFIX:
1846 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1847 break;
252b5132 1848 }
252b5132 1849
29b0f896
AM		 1850 /* If this operand is at most 16 bits, convert it
1851 to a signed 16 bit number before trying to see
1852 whether it will fit in an even smaller size.
1853 This allows a 16-bit operand such as $0xffe0 to
1854 be recognised as within Imm8S range. */
1855 if ((i.types[op] & Imm16)
1856 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 1857 {
29b0f896
AM		 1858 i.op[op].imms->X_add_number =
1859 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1860 }
1861 if ((i.types[op] & Imm32)
1862 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1863 == 0))
1864 {
1865 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1866 ^ ((offsetT) 1 << 31))
1867 - ((offsetT) 1 << 31));
1868 }
1869 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 1870
29b0f896
AM		 1871 /* We must avoid matching of Imm32 templates when 64bit
1872 only immediate is available. */
1873 if (guess_suffix == QWORD_MNEM_SUFFIX)
1874 i.types[op] &= ~Imm32;
1875 break;
252b5132 1876
29b0f896
AM		 1877 case O_absent:
1878 case O_register:
1879 abort ();
1880
1881 /* Symbols and expressions. */
1882 default:
1883 /* Convert symbolic operand to proper sizes for matching. */
1884 switch (guess_suffix)
1885 {
1886 case QWORD_MNEM_SUFFIX:
1887 i.types[op] = Imm64 | Imm32S;
1888 break;
1889 case LONG_MNEM_SUFFIX:
1890 i.types[op] = Imm32 | Imm64;
1891 break;
1892 case WORD_MNEM_SUFFIX:
1893 i.types[op] = Imm16 | Imm32 | Imm64;
1894 break;
1895 break;
1896 case BYTE_MNEM_SUFFIX:
1897 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1898 break;
1899 break;
252b5132 1900 }
29b0f896 1901 break;
252b5132 1902 }
29b0f896
AM		 1903 }
1904}
47926f60 1905
29b0f896
AM		 1906/* Try to use the smallest displacement type too. */
1907static void
1908optimize_disp ()
1909{
1910 int op;
3e73aa7c 1911
29b0f896
AM		 1912 for (op = i.operands; --op >= 0;)
1913 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
252b5132 1914 {
29b0f896
AM		 1915 offsetT disp = i.op[op].disps->X_add_number;
1916
1917 if (i.types[op] & Disp16)
252b5132 1918 {
29b0f896
AM		 1919 /* We know this operand is at most 16 bits, so
1920 convert to a signed 16 bit number before trying
1921 to see whether it will fit in an even smaller
1922 size. */
1923
1924 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
252b5132 1925 }
29b0f896 1926 else if (i.types[op] & Disp32)
252b5132 1927 {
29b0f896
AM		 1928 /* We know this operand is at most 32 bits, so convert to a
1929 signed 32 bit number before trying to see whether it will
1930 fit in an even smaller size. */
1931 disp &= (((offsetT) 2 << 31) - 1);
1932 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 1933 }
29b0f896 1934 if (flag_code == CODE_64BIT)
252b5132 1935 {
29b0f896
AM		 1936 if (fits_in_signed_long (disp))
1937 i.types[op] |= Disp32S;
1938 if (fits_in_unsigned_long (disp))
1939 i.types[op] |= Disp32;
252b5132 1940 }
29b0f896
AM		 1941 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1942 && fits_in_signed_byte (disp))
1943 i.types[op] |= Disp8;
252b5132 1944 }
29b0f896
AM		 1945}
1946
1947static int
1948match_template ()
1949{
1950 /* Points to template once we've found it. */
1951 const template *t;
1952 unsigned int overlap0, overlap1, overlap2;
1953 unsigned int found_reverse_match;
1954 int suffix_check;
1955
1956#define MATCH(overlap, given, template) \
1957 ((overlap & ~JumpAbsolute) \
1958 && (((given) & (BaseIndex | JumpAbsolute)) \
1959 == ((overlap) & (BaseIndex | JumpAbsolute))))
1960
1961 /* If given types r0 and r1 are registers they must be of the same type
1962 unless the expected operand type register overlap is null.
1963 Note that Acc in a template matches every size of reg. */
1964#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1965 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1966 || ((g0) & Reg) == ((g1) & Reg) \
1967 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1968
1969 overlap0 = 0;
1970 overlap1 = 0;
1971 overlap2 = 0;
1972 found_reverse_match = 0;
1973 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1974 ? No_bSuf
1975 : (i.suffix == WORD_MNEM_SUFFIX
1976 ? No_wSuf
1977 : (i.suffix == SHORT_MNEM_SUFFIX
1978 ? No_sSuf
1979 : (i.suffix == LONG_MNEM_SUFFIX
1980 ? No_lSuf
1981 : (i.suffix == QWORD_MNEM_SUFFIX
1982 ? No_qSuf
1983 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
1984 ? No_xSuf : 0))))));
1985
1986 for (t = current_templates->start;
1987 t < current_templates->end;
1988 t++)
1989 {
1990 /* Must have right number of operands. */
1991 if (i.operands != t->operands)
1992 continue;
1993
1994 /* Check the suffix, except for some instructions in intel mode. */
1995 if ((t->opcode_modifier & suffix_check)
1996 && !(intel_syntax
1997 && (t->opcode_modifier & IgnoreSize))
1998 && !(intel_syntax
1999 && t->base_opcode == 0xd9
2000 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2001 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2002 continue;
2003
2004 /* Do not verify operands when there are none. */
2005 else if (!t->operands)
2006 {
2007 if (t->cpu_flags & ~cpu_arch_flags)
2008 continue;
2009 /* We've found a match; break out of loop. */
2010 break;
2011 }
252b5132 2012
29b0f896
AM		 2013 overlap0 = i.types[0] & t->operand_types[0];
2014 switch (t->operands)
2015 {
2016 case 1:
2017 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2018 continue;
2019 break;
2020 case 2:
2021 case 3:
2022 overlap1 = i.types[1] & t->operand_types[1];
2023 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2024 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2025 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2026 t->operand_types[0],
2027 overlap1, i.types[1],
2028 t->operand_types[1]))
2029 {
2030 /* Check if other direction is valid ... */
2031 if ((t->opcode_modifier & (D | FloatD)) == 0)
2032 continue;
2033
2034 /* Try reversing direction of operands. */
2035 overlap0 = i.types[0] & t->operand_types[1];
2036 overlap1 = i.types[1] & t->operand_types[0];
2037 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2038 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2039 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2040 t->operand_types[1],
2041 overlap1, i.types[1],
2042 t->operand_types[0]))
2043 {
2044 /* Does not match either direction. */
2045 continue;
2046 }
2047 /* found_reverse_match holds which of D or FloatDR
2048 we've found. */
2049 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2050 }
2051 /* Found a forward 2 operand match here. */
2052 else if (t->operands == 3)
2053 {
2054 /* Here we make use of the fact that there are no
2055 reverse match 3 operand instructions, and all 3
2056 operand instructions only need to be checked for
2057 register consistency between operands 2 and 3. */
2058 overlap2 = i.types[2] & t->operand_types[2];
2059 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2060 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2061 t->operand_types[1],
2062 overlap2, i.types[2],
2063 t->operand_types[2]))
2064
2065 continue;
2066 }
2067 /* Found either forward/reverse 2 or 3 operand match here:
2068 slip through to break. */
2069 }
2070 if (t->cpu_flags & ~cpu_arch_flags)
2071 {
2072 found_reverse_match = 0;
2073 continue;
2074 }
2075 /* We've found a match; break out of loop. */
2076 break;
2077 }
2078
2079 if (t == current_templates->end)
2080 {
2081 /* We found no match. */
2082 as_bad (_("suffix or operands invalid for `%s'"),
2083 current_templates->start->name);
2084 return 0;
2085 }
252b5132 2086
29b0f896
AM		 2087 if (!quiet_warnings)
2088 {
2089 if (!intel_syntax
2090 && ((i.types[0] & JumpAbsolute)
2091 != (t->operand_types[0] & JumpAbsolute)))
2092 {
2093 as_warn (_("indirect %s without `*'"), t->name);
2094 }
2095
2096 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2097 == (IsPrefix | IgnoreSize))
2098 {
2099 /* Warn them that a data or address size prefix doesn't
2100 affect assembly of the next line of code. */
2101 as_warn (_("stand-alone `%s' prefix"), t->name);
2102 }
2103 }
2104
2105 /* Copy the template we found. */
2106 i.tm = *t;
2107 if (found_reverse_match)
2108 {
2109 /* If we found a reverse match we must alter the opcode
2110 direction bit. found_reverse_match holds bits to change
2111 (different for int & float insns). */
2112
2113 i.tm.base_opcode ^= found_reverse_match;
2114
2115 i.tm.operand_types[0] = t->operand_types[1];
2116 i.tm.operand_types[1] = t->operand_types[0];
2117 }
2118
2119 return 1;
2120}
2121
2122static int
2123check_string ()
2124{
2125 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2126 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2127 {
2128 if (i.seg[0] != NULL && i.seg[0] != &es)
2129 {
2130 as_bad (_("`%s' operand %d must use `%%es' segment"),
2131 i.tm.name,
2132 mem_op + 1);
2133 return 0;
2134 }
2135 /* There's only ever one segment override allowed per instruction.
2136 This instruction possibly has a legal segment override on the
2137 second operand, so copy the segment to where non-string
2138 instructions store it, allowing common code. */
2139 i.seg[0] = i.seg[1];
2140 }
2141 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2142 {
2143 if (i.seg[1] != NULL && i.seg[1] != &es)
2144 {
2145 as_bad (_("`%s' operand %d must use `%%es' segment"),
2146 i.tm.name,
2147 mem_op + 2);
2148 return 0;
2149 }
2150 }
2151 return 1;
2152}
2153
2154static int
2155process_suffix ()
2156{
2157 /* If matched instruction specifies an explicit instruction mnemonic
2158 suffix, use it. */
2159 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2160 {
2161 if (i.tm.opcode_modifier & Size16)
2162 i.suffix = WORD_MNEM_SUFFIX;
2163 else if (i.tm.opcode_modifier & Size64)
2164 i.suffix = QWORD_MNEM_SUFFIX;
2165 else
2166 i.suffix = LONG_MNEM_SUFFIX;
2167 }
2168 else if (i.reg_operands)
2169 {
2170 /* If there's no instruction mnemonic suffix we try to invent one
2171 based on register operands. */
2172 if (!i.suffix)
2173 {
2174 /* We take i.suffix from the last register operand specified,
2175 Destination register type is more significant than source
2176 register type. */
2177 int op;
2178 for (op = i.operands; --op >= 0;)
2179 if ((i.types[op] & Reg)
2180 && !(i.tm.operand_types[op] & InOutPortReg))
2181 {
2182 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2183 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2184 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2185 LONG_MNEM_SUFFIX);
2186 break;
2187 }
2188 }
2189 else if (i.suffix == BYTE_MNEM_SUFFIX)
2190 {
2191 if (!check_byte_reg ())
2192 return 0;
2193 }
2194 else if (i.suffix == LONG_MNEM_SUFFIX)
2195 {
2196 if (!check_long_reg ())
2197 return 0;
2198 }
2199 else if (i.suffix == QWORD_MNEM_SUFFIX)
2200 {
2201 if (!check_qword_reg ())
2202 return 0;
2203 }
2204 else if (i.suffix == WORD_MNEM_SUFFIX)
2205 {
2206 if (!check_word_reg ())
2207 return 0;
2208 }
2209 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2210 /* Do nothing if the instruction is going to ignore the prefix. */
2211 ;
2212 else
2213 abort ();
2214 }
2215 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2216 {
2217 i.suffix = stackop_size;
2218 }
252b5132 2219
29b0f896
AM		 2220 /* Change the opcode based on the operand size given by i.suffix;
2221 We need not change things for byte insns. */
252b5132 2222
29b0f896
AM		 2223 if (!i.suffix && (i.tm.opcode_modifier & W))
2224 {
2225 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2226 return 0;
2227 }
252b5132 2228
29b0f896
AM		 2229 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2230 {
2231 /* It's not a byte, select word/dword operation. */
2232 if (i.tm.opcode_modifier & W)
2233 {
2234 if (i.tm.opcode_modifier & ShortForm)
2235 i.tm.base_opcode |= 8;
2236 else
2237 i.tm.base_opcode |= 1;
2238 }
0f3f3d8b 2239
29b0f896
AM		 2240 /* Now select between word & dword operations via the operand
2241 size prefix, except for instructions that will ignore this
2242 prefix anyway. */
2243 if (i.suffix != QWORD_MNEM_SUFFIX
2244 && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2245 && !(i.tm.opcode_modifier & IgnoreSize))
24eab124
AM		 2246 {
2247 unsigned int prefix = DATA_PREFIX_OPCODE;
29b0f896
AM		 2248 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2249 prefix = ADDR_PREFIX_OPCODE;
252b5132 2250
29b0f896
AM		 2251 if (!add_prefix (prefix))
2252 return 0;
24eab124 2253 }
252b5132 2254
29b0f896
AM		 2255 if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT)
2256 && !(i.tm.opcode_modifier & IgnoreSize)
2257 && (i.tm.opcode_modifier & JumpByte))
2258 {
2259 if (!add_prefix (ADDR_PREFIX_OPCODE))
2260 return 0;
2261 }
252b5132 2262
29b0f896
AM		 2263 /* Set mode64 for an operand. */
2264 if (i.suffix == QWORD_MNEM_SUFFIX
2265 && (i.tm.opcode_modifier & NoRex64) == 0)
2266 {
2267 i.rex |= REX_MODE64;
2268 if (flag_code < CODE_64BIT)
2269 {
2270 as_bad (_("64bit operations available only in 64bit modes."));
2271 return 0;
2272 }
2273 }
3e73aa7c 2274
29b0f896
AM		 2275 /* Size floating point instruction. */
2276 if (i.suffix == LONG_MNEM_SUFFIX)
2277 {
2278 if (i.tm.opcode_modifier & FloatMF)
2279 i.tm.base_opcode ^= 4;
2280 }
2281 }
7ecd2f8b 2282
29b0f896
AM		 2283 return 1;
2284}
3e73aa7c 2285
29b0f896
AM		 2286static int
2287check_byte_reg ()
2288{
2289 int op;
2290 for (op = i.operands; --op >= 0;)
2291 {
2292 /* If this is an eight bit register, it's OK. If it's the 16 or
2293 32 bit version of an eight bit register, we will just use the
2294 low portion, and that's OK too. */
2295 if (i.types[op] & Reg8)
2296 continue;
2297
2298 /* movzx and movsx should not generate this warning. */
2299 if (intel_syntax
2300 && (i.tm.base_opcode == 0xfb7
2301 || i.tm.base_opcode == 0xfb6
2302 || i.tm.base_opcode == 0x63
2303 || i.tm.base_opcode == 0xfbe
2304 || i.tm.base_opcode == 0xfbf))
2305 continue;
2306
2307 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2308#if 0
2309 /* Check that the template allows eight bit regs. This
2310 kills insns such as `orb $1,%edx', which maybe should be
2311 allowed. */
2312 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2313#endif
2314 )
2315 {
2316 /* Prohibit these changes in the 64bit mode, since the
2317 lowering is more complicated. */
2318 if (flag_code == CODE_64BIT
2319 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2320 {
0f3f3d8b 2321 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2322 i.op[op].regs->reg_name,
2323 i.suffix);
2324 return 0;
2325 }
2326#if REGISTER_WARNINGS
2327 if (!quiet_warnings
2328 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2329 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2330 (i.op[op].regs + (i.types[op] & Reg16
2331 ? REGNAM_AL - REGNAM_AX
2332 : REGNAM_AL - REGNAM_EAX))->reg_name,
2333 i.op[op].regs->reg_name,
2334 i.suffix);
2335#endif
2336 continue;
2337 }
2338 /* Any other register is bad. */
2339 if (i.types[op] & (Reg | RegMMX | RegXMM
2340 | SReg2 | SReg3
2341 | Control | Debug | Test
2342 | FloatReg | FloatAcc))
2343 {
2344 as_bad (_("`%%%s' not allowed with `%s%c'"),
2345 i.op[op].regs->reg_name,
2346 i.tm.name,
2347 i.suffix);
2348 return 0;
2349 }
2350 }
2351 return 1;
2352}
2353
2354static int
2355check_long_reg ()
2356{
2357 int op;
2358
2359 for (op = i.operands; --op >= 0;)
2360 /* Reject eight bit registers, except where the template requires
2361 them. (eg. movzb) */
2362 if ((i.types[op] & Reg8) != 0
2363 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2364 {
2365 as_bad (_("`%%%s' not allowed with `%s%c'"),
2366 i.op[op].regs->reg_name,
2367 i.tm.name,
2368 i.suffix);
2369 return 0;
2370 }
2371 /* Warn if the e prefix on a general reg is missing. */
2372 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2373 && (i.types[op] & Reg16) != 0
2374 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2375 {
2376 /* Prohibit these changes in the 64bit mode, since the
2377 lowering is more complicated. */
2378 if (flag_code == CODE_64BIT)
252b5132 2379 {
0f3f3d8b 2380 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2381 i.op[op].regs->reg_name,
2382 i.suffix);
2383 return 0;
252b5132 2384 }
29b0f896
AM		 2385#if REGISTER_WARNINGS
2386 else
2387 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2388 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2389 i.op[op].regs->reg_name,
2390 i.suffix);
2391#endif
252b5132 2392 }
29b0f896
AM		 2393 /* Warn if the r prefix on a general reg is missing. */
2394 else if ((i.types[op] & Reg64) != 0
2395 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2396 {
0f3f3d8b 2397 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2398 i.op[op].regs->reg_name,
2399 i.suffix);
2400 return 0;
2401 }
2402 return 1;
2403}
252b5132 2404
29b0f896
AM		 2405static int
2406check_qword_reg ()
2407{
2408 int op;
252b5132 2409
29b0f896
AM		 2410 for (op = i.operands; --op >= 0; )
2411 /* Reject eight bit registers, except where the template requires
2412 them. (eg. movzb) */
2413 if ((i.types[op] & Reg8) != 0
2414 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2415 {
2416 as_bad (_("`%%%s' not allowed with `%s%c'"),
2417 i.op[op].regs->reg_name,
2418 i.tm.name,
2419 i.suffix);
2420 return 0;
2421 }
2422 /* Warn if the e prefix on a general reg is missing. */
2423 else if (((i.types[op] & Reg16) != 0
2424 || (i.types[op] & Reg32) != 0)
2425 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2426 {
2427 /* Prohibit these changes in the 64bit mode, since the
2428 lowering is more complicated. */
0f3f3d8b 2429 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2430 i.op[op].regs->reg_name,
2431 i.suffix);
2432 return 0;
252b5132 2433 }
29b0f896
AM		 2434 return 1;
2435}
252b5132 2436
29b0f896
AM		 2437static int
2438check_word_reg ()
2439{
2440 int op;
2441 for (op = i.operands; --op >= 0;)
2442 /* Reject eight bit registers, except where the template requires
2443 them. (eg. movzb) */
2444 if ((i.types[op] & Reg8) != 0
2445 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2446 {
2447 as_bad (_("`%%%s' not allowed with `%s%c'"),
2448 i.op[op].regs->reg_name,
2449 i.tm.name,
2450 i.suffix);
2451 return 0;
2452 }
2453 /* Warn if the e prefix on a general reg is present. */
2454 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2455 && (i.types[op] & Reg32) != 0
2456 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2457 {
29b0f896
AM		 2458 /* Prohibit these changes in the 64bit mode, since the
2459 lowering is more complicated. */
2460 if (flag_code == CODE_64BIT)
252b5132 2461 {
0f3f3d8b 2462 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2463 i.op[op].regs->reg_name,
2464 i.suffix);
2465 return 0;
252b5132 2466 }
29b0f896
AM		 2467 else
2468#if REGISTER_WARNINGS
2469 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2470 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2471 i.op[op].regs->reg_name,
2472 i.suffix);
2473#endif
2474 }
2475 return 1;
2476}
252b5132 2477
29b0f896
AM		 2478static int
2479finalize_imm ()
2480{
2481 unsigned int overlap0, overlap1, overlap2;
2482
2483 overlap0 = i.types[0] & i.tm.operand_types[0];
2484 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2485 && overlap0 != Imm8 && overlap0 != Imm8S
2486 && overlap0 != Imm16 && overlap0 != Imm32S
2487 && overlap0 != Imm32 && overlap0 != Imm64)
2488 {
2489 if (i.suffix)
2490 {
2491 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2492 ? Imm8 | Imm8S
2493 : (i.suffix == WORD_MNEM_SUFFIX
2494 ? Imm16
2495 : (i.suffix == QWORD_MNEM_SUFFIX
2496 ? Imm64 | Imm32S
2497 : Imm32)));
2498 }
2499 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2500 || overlap0 == (Imm16 | Imm32)
2501 || overlap0 == (Imm16 | Imm32S))
2502 {
2503 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2504 ? Imm16 : Imm32S);
2505 }
2506 if (overlap0 != Imm8 && overlap0 != Imm8S
2507 && overlap0 != Imm16 && overlap0 != Imm32S
2508 && overlap0 != Imm32 && overlap0 != Imm64)
2509 {
2510 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2511 return 0;
2512 }
2513 }
2514 i.types[0] = overlap0;
2515
2516 overlap1 = i.types[1] & i.tm.operand_types[1];
2517 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2518 && overlap1 != Imm8 && overlap1 != Imm8S
2519 && overlap1 != Imm16 && overlap1 != Imm32S
2520 && overlap1 != Imm32 && overlap1 != Imm64)
2521 {
2522 if (i.suffix)
2523 {
2524 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2525 ? Imm8 | Imm8S
2526 : (i.suffix == WORD_MNEM_SUFFIX
2527 ? Imm16
2528 : (i.suffix == QWORD_MNEM_SUFFIX
2529 ? Imm64 | Imm32S
2530 : Imm32)));
2531 }
2532 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2533 || overlap1 == (Imm16 | Imm32)
2534 || overlap1 == (Imm16 | Imm32S))
2535 {
2536 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2537 ? Imm16 : Imm32S);
2538 }
2539 if (overlap1 != Imm8 && overlap1 != Imm8S
2540 && overlap1 != Imm16 && overlap1 != Imm32S
2541 && overlap1 != Imm32 && overlap1 != Imm64)
2542 {
2543 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2544 return 0;
2545 }
2546 }
2547 i.types[1] = overlap1;
2548
2549 overlap2 = i.types[2] & i.tm.operand_types[2];
2550 assert ((overlap2 & Imm) == 0);
2551 i.types[2] = overlap2;
2552
2553 return 1;
2554}
2555
2556static int
2557process_operands ()
2558{
2559 /* Default segment register this instruction will use for memory
2560 accesses. 0 means unknown. This is only for optimizing out
2561 unnecessary segment overrides. */
2562 const seg_entry *default_seg = 0;
2563
2564 /* The imul $imm, %reg instruction is converted into
2565 imul $imm, %reg, %reg, and the clr %reg instruction
2566 is converted into xor %reg, %reg. */
2567 if (i.tm.opcode_modifier & regKludge)
2568 {
2569 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2570 /* Pretend we saw the extra register operand. */
2571 assert (i.op[first_reg_op + 1].regs == 0);
2572 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2573 i.types[first_reg_op + 1] = i.types[first_reg_op];
2574 i.reg_operands = 2;
2575 }
2576
2577 if (i.tm.opcode_modifier & ShortForm)
2578 {
2579 /* The register or float register operand is in operand 0 or 1. */
2580 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2581 /* Register goes in low 3 bits of opcode. */
2582 i.tm.base_opcode |= i.op[op].regs->reg_num;
2583 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2584 i.rex |= REX_EXTZ;
2585 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2586 {
2587 /* Warn about some common errors, but press on regardless.
2588 The first case can be generated by gcc (<= 2.8.1). */
2589 if (i.operands == 2)
2590 {
2591 /* Reversed arguments on faddp, fsubp, etc. */
2592 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2593 i.op[1].regs->reg_name,
2594 i.op[0].regs->reg_name);
2595 }
2596 else
2597 {
2598 /* Extraneous `l' suffix on fp insn. */
2599 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2600 i.op[0].regs->reg_name);
2601 }
2602 }
2603 }
2604 else if (i.tm.opcode_modifier & Modrm)
2605 {
2606 /* The opcode is completed (modulo i.tm.extension_opcode which
2607 must be put into the modrm byte).
2608 Now, we make the modrm & index base bytes based on all the
2609 info we've collected. */
2610
2611 default_seg = build_modrm_byte ();
2612 }
2613 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2614 {
2615 if (i.tm.base_opcode == POP_SEG_SHORT
2616 && i.op[0].regs->reg_num == 1)
2617 {
2618 as_bad (_("you can't `pop %%cs'"));
2619 return 0;
2620 }
2621 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2622 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2623 i.rex |= REX_EXTZ;
2624 }
2625 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2626 {
2627 default_seg = &ds;
2628 }
2629 else if ((i.tm.opcode_modifier & IsString) != 0)
2630 {
2631 /* For the string instructions that allow a segment override
2632 on one of their operands, the default segment is ds. */
2633 default_seg = &ds;
2634 }
2635
2636 /* If a segment was explicitly specified,
2637 and the specified segment is not the default,
2638 use an opcode prefix to select it.
2639 If we never figured out what the default segment is,
2640 then default_seg will be zero at this point,
2641 and the specified segment prefix will always be used. */
2642 if ((i.seg[0]) && (i.seg[0] != default_seg))
2643 {
2644 if (!add_prefix (i.seg[0]->seg_prefix))
2645 return 0;
2646 }
2647 return 1;
2648}
2649
2650static const seg_entry *
2651build_modrm_byte ()
2652{
2653 const seg_entry *default_seg = 0;
2654
2655 /* i.reg_operands MUST be the number of real register operands;
2656 implicit registers do not count. */
2657 if (i.reg_operands == 2)
2658 {
2659 unsigned int source, dest;
2660 source = ((i.types[0]
2661 & (Reg | RegMMX | RegXMM
2662 | SReg2 | SReg3
2663 | Control | Debug | Test))
2664 ? 0 : 1);
2665 dest = source + 1;
2666
2667 i.rm.mode = 3;
2668 /* One of the register operands will be encoded in the i.tm.reg
2669 field, the other in the combined i.tm.mode and i.tm.regmem
2670 fields. If no form of this instruction supports a memory
2671 destination operand, then we assume the source operand may
2672 sometimes be a memory operand and so we need to store the
2673 destination in the i.rm.reg field. */
2674 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2675 {
2676 i.rm.reg = i.op[dest].regs->reg_num;
2677 i.rm.regmem = i.op[source].regs->reg_num;
2678 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2679 i.rex |= REX_EXTX;
2680 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2681 i.rex |= REX_EXTZ;
2682 }
2683 else
2684 {
2685 i.rm.reg = i.op[source].regs->reg_num;
2686 i.rm.regmem = i.op[dest].regs->reg_num;
2687 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2688 i.rex |= REX_EXTZ;
2689 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2690 i.rex |= REX_EXTX;
2691 }
2692 }
2693 else
2694 { /* If it's not 2 reg operands... */
2695 if (i.mem_operands)
2696 {
2697 unsigned int fake_zero_displacement = 0;
2698 unsigned int op = ((i.types[0] & AnyMem)
2699 ? 0
2700 : (i.types[1] & AnyMem) ? 1 : 2);
2701
2702 default_seg = &ds;
2703
2704 if (i.base_reg == 0)
2705 {
2706 i.rm.mode = 0;
2707 if (!i.disp_operands)
2708 fake_zero_displacement = 1;
2709 if (i.index_reg == 0)
2710 {
2711 /* Operand is just <disp> */
2712 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2713 && (flag_code != CODE_64BIT))
2714 {
2715 i.rm.regmem = NO_BASE_REGISTER_16;
2716 i.types[op] &= ~Disp;
2717 i.types[op] |= Disp16;
2718 }
2719 else if (flag_code != CODE_64BIT
2720 || (i.prefix[ADDR_PREFIX] != 0))
2721 {
2722 i.rm.regmem = NO_BASE_REGISTER;
2723 i.types[op] &= ~Disp;
2724 i.types[op] |= Disp32;
2725 }
2726 else
2727 {
2728 /* 64bit mode overwrites the 32bit absolute
2729 addressing by RIP relative addressing and
2730 absolute addressing is encoded by one of the
2731 redundant SIB forms. */
2732 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2733 i.sib.base = NO_BASE_REGISTER;
2734 i.sib.index = NO_INDEX_REGISTER;
2735 i.types[op] &= ~Disp;
2736 i.types[op] |= Disp32S;
2737 }
2738 }
2739 else /* !i.base_reg && i.index_reg */
2740 {
2741 i.sib.index = i.index_reg->reg_num;
2742 i.sib.base = NO_BASE_REGISTER;
2743 i.sib.scale = i.log2_scale_factor;
2744 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2745 i.types[op] &= ~Disp;
2746 if (flag_code != CODE_64BIT)
2747 i.types[op] |= Disp32; /* Must be 32 bit */
2748 else
2749 i.types[op] |= Disp32S;
2750 if ((i.index_reg->reg_flags & RegRex) != 0)
2751 i.rex |= REX_EXTY;
2752 }
2753 }
2754 /* RIP addressing for 64bit mode. */
2755 else if (i.base_reg->reg_type == BaseIndex)
2756 {
2757 i.rm.regmem = NO_BASE_REGISTER;
2758 i.types[op] &= ~Disp;
2759 i.types[op] |= Disp32S;
2760 i.flags[op] = Operand_PCrel;
2761 }
2762 else if (i.base_reg->reg_type & Reg16)
2763 {
2764 switch (i.base_reg->reg_num)
2765 {
2766 case 3: /* (%bx) */
2767 if (i.index_reg == 0)
2768 i.rm.regmem = 7;
2769 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2770 i.rm.regmem = i.index_reg->reg_num - 6;
2771 break;
2772 case 5: /* (%bp) */
2773 default_seg = &ss;
2774 if (i.index_reg == 0)
2775 {
2776 i.rm.regmem = 6;
2777 if ((i.types[op] & Disp) == 0)
2778 {
2779 /* fake (%bp) into 0(%bp) */
2780 i.types[op] |= Disp8;
252b5132 2781 fake_zero_displacement = 1;
29b0f896
AM		 2782 }
2783 }
2784 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2785 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2786 break;
2787 default: /* (%si) -> 4 or (%di) -> 5 */
2788 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2789 }
2790 i.rm.mode = mode_from_disp_size (i.types[op]);
2791 }
2792 else /* i.base_reg and 32/64 bit mode */
2793 {
2794 if (flag_code == CODE_64BIT
2795 && (i.types[op] & Disp))
2796 {
2797 if (i.types[op] & Disp8)
2798 i.types[op] = Disp8 | Disp32S;
2799 else
2800 i.types[op] = Disp32S;
2801 }
2802 i.rm.regmem = i.base_reg->reg_num;
2803 if ((i.base_reg->reg_flags & RegRex) != 0)
2804 i.rex |= REX_EXTZ;
2805 i.sib.base = i.base_reg->reg_num;
2806 /* x86-64 ignores REX prefix bit here to avoid decoder
2807 complications. */
2808 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2809 {
2810 default_seg = &ss;
2811 if (i.disp_operands == 0)
2812 {
2813 fake_zero_displacement = 1;
2814 i.types[op] |= Disp8;
2815 }
2816 }
2817 else if (i.base_reg->reg_num == ESP_REG_NUM)
2818 {
2819 default_seg = &ss;
2820 }
2821 i.sib.scale = i.log2_scale_factor;
2822 if (i.index_reg == 0)
2823 {
2824 /* <disp>(%esp) becomes two byte modrm with no index
2825 register. We've already stored the code for esp
2826 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2827 Any base register besides %esp will not use the
2828 extra modrm byte. */
2829 i.sib.index = NO_INDEX_REGISTER;
2830#if !SCALE1_WHEN_NO_INDEX
2831 /* Another case where we force the second modrm byte. */
2832 if (i.log2_scale_factor)
2833 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 2834#endif
29b0f896
AM		 2835 }
2836 else
2837 {
2838 i.sib.index = i.index_reg->reg_num;
2839 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2840 if ((i.index_reg->reg_flags & RegRex) != 0)
2841 i.rex |= REX_EXTY;
2842 }
2843 i.rm.mode = mode_from_disp_size (i.types[op]);
2844 }
252b5132 2845
29b0f896
AM		 2846 if (fake_zero_displacement)
2847 {
2848 /* Fakes a zero displacement assuming that i.types[op]
2849 holds the correct displacement size. */
2850 expressionS *exp;
2851
2852 assert (i.op[op].disps == 0);
2853 exp = &disp_expressions[i.disp_operands++];
2854 i.op[op].disps = exp;
2855 exp->X_op = O_constant;
2856 exp->X_add_number = 0;
2857 exp->X_add_symbol = (symbolS *) 0;
2858 exp->X_op_symbol = (symbolS *) 0;
2859 }
2860 }
252b5132 2861
29b0f896
AM		 2862 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2863 (if any) based on i.tm.extension_opcode. Again, we must be
2864 careful to make sure that segment/control/debug/test/MMX
2865 registers are coded into the i.rm.reg field. */
2866 if (i.reg_operands)
2867 {
2868 unsigned int op =
2869 ((i.types[0]
2870 & (Reg | RegMMX | RegXMM
2871 | SReg2 | SReg3
2872 | Control | Debug | Test))
2873 ? 0
2874 : ((i.types[1]
2875 & (Reg | RegMMX | RegXMM
2876 | SReg2 | SReg3
2877 | Control | Debug | Test))
2878 ? 1
2879 : 2));
2880 /* If there is an extension opcode to put here, the register
2881 number must be put into the regmem field. */
2882 if (i.tm.extension_opcode != None)
2883 {
2884 i.rm.regmem = i.op[op].regs->reg_num;
2885 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2886 i.rex |= REX_EXTZ;
2887 }
2888 else
2889 {
2890 i.rm.reg = i.op[op].regs->reg_num;
2891 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2892 i.rex |= REX_EXTX;
2893 }
252b5132 2894
29b0f896
AM		 2895 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2896 must set it to 3 to indicate this is a register operand
2897 in the regmem field. */
2898 if (!i.mem_operands)
2899 i.rm.mode = 3;
2900 }
252b5132 2901
29b0f896
AM		 2902 /* Fill in i.rm.reg field with extension opcode (if any). */
2903 if (i.tm.extension_opcode != None)
2904 i.rm.reg = i.tm.extension_opcode;
2905 }
2906 return default_seg;
2907}
252b5132 2908
29b0f896
AM		 2909static void
2910output_branch ()
2911{
2912 char *p;
2913 int code16;
2914 int prefix;
2915 relax_substateT subtype;
2916 symbolS *sym;
2917 offsetT off;
2918
2919 code16 = 0;
2920 if (flag_code == CODE_16BIT)
2921 code16 = CODE16;
2922
2923 prefix = 0;
2924 if (i.prefix[DATA_PREFIX] != 0)
252b5132 2925 {
29b0f896
AM		 2926 prefix = 1;
2927 i.prefixes -= 1;
2928 code16 ^= CODE16;
252b5132 2929 }
29b0f896
AM		 2930 /* Pentium4 branch hints. */
2931 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2932 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 2933 {
29b0f896
AM		 2934 prefix++;
2935 i.prefixes--;
2936 }
2937 if (i.prefix[REX_PREFIX] != 0)
2938 {
2939 prefix++;
2940 i.prefixes--;
2f66722d
AM		 2941 }
2942
29b0f896
AM		 2943 if (i.prefixes != 0 && !intel_syntax)
2944 as_warn (_("skipping prefixes on this instruction"));
2945
2946 /* It's always a symbol; End frag & setup for relax.
2947 Make sure there is enough room in this frag for the largest
2948 instruction we may generate in md_convert_frag. This is 2
2949 bytes for the opcode and room for the prefix and largest
2950 displacement. */
2951 frag_grow (prefix + 2 + 4);
2952 /* Prefix and 1 opcode byte go in fr_fix. */
2953 p = frag_more (prefix + 1);
2954 if (i.prefix[DATA_PREFIX] != 0)
2955 *p++ = DATA_PREFIX_OPCODE;
2956 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2957 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2958 *p++ = i.prefix[SEG_PREFIX];
2959 if (i.prefix[REX_PREFIX] != 0)
2960 *p++ = i.prefix[REX_PREFIX];
2961 *p = i.tm.base_opcode;
2962
2963 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2964 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2965 else if ((cpu_arch_flags & Cpu386) != 0)
2966 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2967 else
2968 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2969 subtype |= code16;
3e73aa7c 2970
29b0f896
AM		 2971 sym = i.op[0].disps->X_add_symbol;
2972 off = i.op[0].disps->X_add_number;
3e73aa7c 2973
29b0f896
AM		 2974 if (i.op[0].disps->X_op != O_constant
2975 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 2976 {
29b0f896
AM		 2977 /* Handle complex expressions. */
2978 sym = make_expr_symbol (i.op[0].disps);
2979 off = 0;
2980 }
3e73aa7c 2981
29b0f896
AM		 2982 /* 1 possible extra opcode + 4 byte displacement go in var part.
2983 Pass reloc in fr_var. */
2984 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
2985}
3e73aa7c 2986
29b0f896
AM		 2987static void
2988output_jump ()
2989{
2990 char *p;
2991 int size;
2992
2993 if (i.tm.opcode_modifier & JumpByte)
2994 {
2995 /* This is a loop or jecxz type instruction. */
2996 size = 1;
2997 if (i.prefix[ADDR_PREFIX] != 0)
2998 {
2999 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3000 i.prefixes -= 1;
3001 }
3002 /* Pentium4 branch hints. */
3003 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3004 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3005 {
3006 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3007 i.prefixes--;
3e73aa7c
JH		 3008 }
3009 }
29b0f896
AM		 3010 else
3011 {
3012 int code16;
3e73aa7c 3013
29b0f896
AM		 3014 code16 = 0;
3015 if (flag_code == CODE_16BIT)
3016 code16 = CODE16;
3e73aa7c 3017
29b0f896
AM		 3018 if (i.prefix[DATA_PREFIX] != 0)
3019 {
3020 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3021 i.prefixes -= 1;
3022 code16 ^= CODE16;
3023 }
252b5132 3024
29b0f896
AM		 3025 size = 4;
3026 if (code16)
3027 size = 2;
3028 }
9fcc94b6 3029
29b0f896
AM		 3030 if (i.prefix[REX_PREFIX] != 0)
3031 {
3032 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3033 i.prefixes -= 1;
3034 }
252b5132 3035
29b0f896
AM		 3036 if (i.prefixes != 0 && !intel_syntax)
3037 as_warn (_("skipping prefixes on this instruction"));
e0890092 3038
29b0f896
AM		 3039 p = frag_more (1 + size);
3040 *p++ = i.tm.base_opcode;
e0890092 3041
062cd5e7
AS		 3042 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3043 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
29b0f896 3044}
e0890092 3045
29b0f896
AM		 3046static void
3047output_interseg_jump ()
3048{
3049 char *p;
3050 int size;
3051 int prefix;
3052 int code16;
252b5132 3053
29b0f896
AM		 3054 code16 = 0;
3055 if (flag_code == CODE_16BIT)
3056 code16 = CODE16;
a217f122 3057
29b0f896
AM		 3058 prefix = 0;
3059 if (i.prefix[DATA_PREFIX] != 0)
3060 {
3061 prefix = 1;
3062 i.prefixes -= 1;
3063 code16 ^= CODE16;
3064 }
3065 if (i.prefix[REX_PREFIX] != 0)
3066 {
3067 prefix++;
3068 i.prefixes -= 1;
3069 }
252b5132 3070
29b0f896
AM		 3071 size = 4;
3072 if (code16)
3073 size = 2;
252b5132 3074
29b0f896
AM		 3075 if (i.prefixes != 0 && !intel_syntax)
3076 as_warn (_("skipping prefixes on this instruction"));
252b5132 3077
29b0f896
AM		 3078 /* 1 opcode; 2 segment; offset */
3079 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3080
29b0f896
AM		 3081 if (i.prefix[DATA_PREFIX] != 0)
3082 *p++ = DATA_PREFIX_OPCODE;
252b5132 3083
29b0f896
AM		 3084 if (i.prefix[REX_PREFIX] != 0)
3085 *p++ = i.prefix[REX_PREFIX];
252b5132 3086
29b0f896
AM		 3087 *p++ = i.tm.base_opcode;
3088 if (i.op[1].imms->X_op == O_constant)
3089 {
3090 offsetT n = i.op[1].imms->X_add_number;
252b5132 3091
29b0f896
AM		 3092 if (size == 2
3093 && !fits_in_unsigned_word (n)
3094 && !fits_in_signed_word (n))
3095 {
3096 as_bad (_("16-bit jump out of range"));
3097 return;
3098 }
3099 md_number_to_chars (p, n, size);
3100 }
3101 else
3102 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3103 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3104 if (i.op[0].imms->X_op != O_constant)
3105 as_bad (_("can't handle non absolute segment in `%s'"),
3106 i.tm.name);
3107 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3108}
a217f122 3109
29b0f896
AM		 3110static void
3111output_insn ()
3112{
3113 /* Tie dwarf2 debug info to the address at the start of the insn.
3114 We can't do this after the insn has been output as the current
3115 frag may have been closed off. eg. by frag_var. */
3116 dwarf2_emit_insn (0);
3117
3118 /* Output jumps. */
3119 if (i.tm.opcode_modifier & Jump)
3120 output_branch ();
3121 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3122 output_jump ();
3123 else if (i.tm.opcode_modifier & JumpInterSegment)
3124 output_interseg_jump ();
3125 else
3126 {
3127 /* Output normal instructions here. */
3128 char *p;
3129 unsigned char *q;
252b5132 3130
29b0f896
AM		 3131 /* All opcodes on i386 have either 1 or 2 bytes. We may use third
3132 byte for the SSE instructions to specify a prefix they require. */
3133 if (i.tm.base_opcode & 0xff0000)
3134 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
252b5132 3135
29b0f896
AM		 3136 /* The prefix bytes. */
3137 for (q = i.prefix;
3138 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3139 q++)
3140 {
3141 if (*q)
3142 {
3143 p = frag_more (1);
3144 md_number_to_chars (p, (valueT) *q, 1);
3145 }
3146 }
252b5132 3147
29b0f896
AM		 3148 /* Now the opcode; be careful about word order here! */
3149 if (fits_in_unsigned_byte (i.tm.base_opcode))
3150 {
3151 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3152 }
3153 else
3154 {
3155 p = frag_more (2);
3156 /* Put out high byte first: can't use md_number_to_chars! */
3157 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3158 *p = i.tm.base_opcode & 0xff;
3159 }
3e73aa7c 3160
29b0f896
AM		 3161 /* Now the modrm byte and sib byte (if present). */
3162 if (i.tm.opcode_modifier & Modrm)
3163 {
3164 p = frag_more (1);
3165 md_number_to_chars (p,
3166 (valueT) (i.rm.regmem << 0
3167 | i.rm.reg << 3
3168 | i.rm.mode << 6),
3169 1);
3170 /* If i.rm.regmem == ESP (4)
3171 && i.rm.mode != (Register mode)
3172 && not 16 bit
3173 ==> need second modrm byte. */
3174 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3175 && i.rm.mode != 3
3176 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3177 {
3178 p = frag_more (1);
3179 md_number_to_chars (p,
3180 (valueT) (i.sib.base << 0
3181 | i.sib.index << 3
3182 | i.sib.scale << 6),
3183 1);
3184 }
3185 }
3e73aa7c 3186
29b0f896
AM		 3187 if (i.disp_operands)
3188 output_disp ();
3e73aa7c 3189
29b0f896
AM		 3190 if (i.imm_operands)
3191 output_imm ();
3192 }
252b5132 3193
29b0f896
AM		 3194#ifdef DEBUG386
3195 if (flag_debug)
3196 {
3197 pi (line, &i);
3198 }
3199#endif /* DEBUG386 */
3200}
252b5132 3201
29b0f896
AM		 3202static void
3203output_disp ()
3204{
3205 char *p;
3206 unsigned int n;
252b5132 3207
29b0f896
AM		 3208 for (n = 0; n < i.operands; n++)
3209 {
3210 if (i.types[n] & Disp)
3211 {
3212 if (i.op[n].disps->X_op == O_constant)
3213 {
3214 int size;
3215 offsetT val;
252b5132 3216
29b0f896
AM		 3217 size = 4;
3218 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3219 {
3220 size = 2;
3221 if (i.types[n] & Disp8)
3222 size = 1;
3223 if (i.types[n] & Disp64)
3224 size = 8;
3225 }
3226 val = offset_in_range (i.op[n].disps->X_add_number,
3227 size);
3228 p = frag_more (size);
3229 md_number_to_chars (p, val, size);
3230 }
3231 else
3232 {
3233 int size = 4;
3234 int sign = 0;
3235 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3236
3237 /* The PC relative address is computed relative
3238 to the instruction boundary, so in case immediate
3239 fields follows, we need to adjust the value. */
3240 if (pcrel && i.imm_operands)
3241 {
3242 int imm_size = 4;
3243 unsigned int n1;
252b5132 3244
29b0f896
AM		 3245 for (n1 = 0; n1 < i.operands; n1++)
3246 if (i.types[n1] & Imm)
252b5132 3247 {
29b0f896 3248 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3249 {
29b0f896
AM		 3250 imm_size = 2;
3251 if (i.types[n1] & (Imm8 | Imm8S))
3252 imm_size = 1;
3253 if (i.types[n1] & Imm64)
3254 imm_size = 8;
252b5132 3255 }
29b0f896 3256 break;
252b5132 3257 }
29b0f896
AM		 3258 /* We should find the immediate. */
3259 if (n1 == i.operands)
3260 abort ();
3261 i.op[n].disps->X_add_number -= imm_size;
3262 }
520dc8e8 3263
29b0f896
AM		 3264 if (i.types[n] & Disp32S)
3265 sign = 1;
3e73aa7c 3266
29b0f896
AM		 3267 if (i.types[n] & (Disp16 | Disp64))
3268 {
3269 size = 2;
3270 if (i.types[n] & Disp64)
3271 size = 8;
3272 }
520dc8e8 3273
29b0f896 3274 p = frag_more (size);
062cd5e7
AS		 3275 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3276 i.op[n].disps, pcrel,
3277 reloc (size, pcrel, sign, i.reloc[n]));
29b0f896
AM		 3278 }
3279 }
3280 }
3281}
252b5132 3282
29b0f896
AM		 3283static void
3284output_imm ()
3285{
3286 char *p;
3287 unsigned int n;
252b5132 3288
29b0f896
AM		 3289 for (n = 0; n < i.operands; n++)
3290 {
3291 if (i.types[n] & Imm)
3292 {
3293 if (i.op[n].imms->X_op == O_constant)
3294 {
3295 int size;
3296 offsetT val;
b4cac588 3297
29b0f896
AM		 3298 size = 4;
3299 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3300 {
3301 size = 2;
3302 if (i.types[n] & (Imm8 | Imm8S))
3303 size = 1;
3304 else if (i.types[n] & Imm64)
3305 size = 8;
3306 }
3307 val = offset_in_range (i.op[n].imms->X_add_number,
3308 size);
3309 p = frag_more (size);
3310 md_number_to_chars (p, val, size);
3311 }
3312 else
3313 {
3314 /* Not absolute_section.
3315 Need a 32-bit fixup (don't support 8bit
3316 non-absolute imms). Try to support other
3317 sizes ... */
3318 RELOC_ENUM reloc_type;
3319 int size = 4;
3320 int sign = 0;
3321
3322 if ((i.types[n] & (Imm32S))
3323 && i.suffix == QWORD_MNEM_SUFFIX)
3324 sign = 1;
3325 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3326 {
3327 size = 2;
3328 if (i.types[n] & (Imm8 | Imm8S))
3329 size = 1;
3330 if (i.types[n] & Imm64)
3331 size = 8;
3332 }
520dc8e8 3333
29b0f896
AM		 3334 p = frag_more (size);
3335 reloc_type = reloc (size, 0, sign, i.reloc[n]);
252b5132 3336#ifdef BFD_ASSEMBLER
29b0f896
AM		 3337 if (reloc_type == BFD_RELOC_32
3338 && GOT_symbol
3339 && GOT_symbol == i.op[n].imms->X_add_symbol
3340 && (i.op[n].imms->X_op == O_symbol
3341 || (i.op[n].imms->X_op == O_add
3342 && ((symbol_get_value_expression
3343 (i.op[n].imms->X_op_symbol)->X_op)
3344 == O_subtract))))
3345 {
3346 /* We don't support dynamic linking on x86-64 yet. */
3347 if (flag_code == CODE_64BIT)
3348 abort ();
3349 reloc_type = BFD_RELOC_386_GOTPC;
3350 i.op[n].imms->X_add_number += 3;
3351 }
252b5132 3352#endif
29b0f896
AM		 3353 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3354 i.op[n].imms, 0, reloc_type);
3355 }
3356 }
3357 }
252b5132
RH		 3358}
3359\f
f3c180ae
AM		 3360#ifndef LEX_AT
3361static char *lex_got PARAMS ((RELOC_ENUM *, int *));
3362
3363/* Parse operands of the form
3364 <symbol>@GOTOFF+<nnn>
3365 and similar .plt or .got references.
3366
3367 If we find one, set up the correct relocation in RELOC and copy the
3368 input string, minus the `@GOTOFF' into a malloc'd buffer for
3369 parsing by the calling routine. Return this buffer, and if ADJUST
3370 is non-null set it to the length of the string we removed from the
3371 input line. Otherwise return NULL. */
3372static char *
3373lex_got (reloc, adjust)
3374 RELOC_ENUM *reloc;
3375 int *adjust;
3376{
3377 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3378 static const struct {
3379 const char *str;
3380 const RELOC_ENUM rel[NUM_FLAG_CODE];
3381 } gotrel[] = {
13ae64f3
JJ		 3382 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3383 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3384 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3385 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } },
3386 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3387 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } },
3388 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } },
3389 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3390 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } },
3391 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
f3c180ae
AM		 3392 };
3393 char *cp;
3394 unsigned int j;
3395
3396 for (cp = input_line_pointer; *cp != '@'; cp++)
3397 if (is_end_of_line[(unsigned char) *cp])
3398 return NULL;
3399
3400 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3401 {
3402 int len;
3403
3404 len = strlen (gotrel[j].str);
28f81592 3405 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3406 {
3407 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3408 {
28f81592
AM		 3409 int first, second;
3410 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3411
3412 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3413 if (adjust)
3414 *adjust = len;
f3c180ae
AM		 3415
3416 if (GOT_symbol == NULL)
3417 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3418
3419 /* Replace the relocation token with ' ', so that
3420 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3421
3422 /* The length of the first part of our input line. */
f3c180ae 3423 first = cp - input_line_pointer;
28f81592
AM		 3424
3425 /* The second part goes from after the reloc token until
3426 (and including) an end_of_line char. Don't use strlen
3427 here as the end_of_line char may not be a NUL. */
3428 past_reloc = cp + 1 + len;
3429 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3430 ;
3431 second = cp - past_reloc;
3432
3433 /* Allocate and copy string. The trailing NUL shouldn't
3434 be necessary, but be safe. */
3435 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3436 memcpy (tmpbuf, input_line_pointer, first);
3437 tmpbuf[first] = ' ';
28f81592
AM		 3438 memcpy (tmpbuf + first + 1, past_reloc, second);
3439 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3440 return tmpbuf;
3441 }
3442
3443 as_bad (_("@%s reloc is not supported in %s bit mode"),
3444 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3445 return NULL;
3446 }
3447 }
3448
3449 /* Might be a symbol version string. Don't as_bad here. */
3450 return NULL;
3451}
3452
3453/* x86_cons_fix_new is called via the expression parsing code when a
3454 reloc is needed. We use this hook to get the correct .got reloc. */
3455static RELOC_ENUM got_reloc = NO_RELOC;
3456
3457void
3458x86_cons_fix_new (frag, off, len, exp)
3459 fragS *frag;
3460 unsigned int off;
3461 unsigned int len;
3462 expressionS *exp;
3463{
3464 RELOC_ENUM r = reloc (len, 0, 0, got_reloc);
3465 got_reloc = NO_RELOC;
3466 fix_new_exp (frag, off, len, exp, 0, r);
3467}
3468
3469void
3470x86_cons (exp, size)
3471 expressionS *exp;
3472 int size;
3473{
3474 if (size == 4)
3475 {
3476 /* Handle @GOTOFF and the like in an expression. */
3477 char *save;
3478 char *gotfree_input_line;
3479 int adjust;
3480
3481 save = input_line_pointer;
3482 gotfree_input_line = lex_got (&got_reloc, &adjust);
3483 if (gotfree_input_line)
3484 input_line_pointer = gotfree_input_line;
3485
3486 expression (exp);
3487
3488 if (gotfree_input_line)
3489 {
3490 /* expression () has merrily parsed up to the end of line,
3491 or a comma - in the wrong buffer. Transfer how far
3492 input_line_pointer has moved to the right buffer. */
3493 input_line_pointer = (save
3494 + (input_line_pointer - gotfree_input_line)
3495 + adjust);
3496 free (gotfree_input_line);
3497 }
3498 }
3499 else
3500 expression (exp);
3501}
3502#endif
3503
252b5132
RH		 3504static int i386_immediate PARAMS ((char *));
3505
3506static int
3507i386_immediate (imm_start)
3508 char *imm_start;
3509{
3510 char *save_input_line_pointer;
f3c180ae
AM		 3511#ifndef LEX_AT
3512 char *gotfree_input_line;
3513#endif
252b5132 3514 segT exp_seg = 0;
47926f60 3515 expressionS *exp;
252b5132
RH		 3516
3517 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3518 {
d0b47220 3519 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3520 return 0;
3521 }
3522
3523 exp = &im_expressions[i.imm_operands++];
520dc8e8 3524 i.op[this_operand].imms = exp;
252b5132
RH		 3525
3526 if (is_space_char (*imm_start))
3527 ++imm_start;
3528
3529 save_input_line_pointer = input_line_pointer;
3530 input_line_pointer = imm_start;
3531
3532#ifndef LEX_AT
f3c180ae
AM		 3533 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3534 if (gotfree_input_line)
3535 input_line_pointer = gotfree_input_line;
252b5132
RH		 3536#endif
3537
3538 exp_seg = expression (exp);
3539
83183c0c 3540 SKIP_WHITESPACE ();
252b5132 3541 if (*input_line_pointer)
f3c180ae 3542 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3543
3544 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3545#ifndef LEX_AT
3546 if (gotfree_input_line)
3547 free (gotfree_input_line);
3548#endif
252b5132 3549
2daf4fd8 3550 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3551 {
47926f60 3552 /* Missing or bad expr becomes absolute 0. */
d0b47220 3553 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3554 imm_start);
252b5132
RH		 3555 exp->X_op = O_constant;
3556 exp->X_add_number = 0;
3557 exp->X_add_symbol = (symbolS *) 0;
3558 exp->X_op_symbol = (symbolS *) 0;
252b5132 3559 }
3e73aa7c 3560 else if (exp->X_op == O_constant)
252b5132 3561 {
47926f60 3562 /* Size it properly later. */
3e73aa7c
JH		 3563 i.types[this_operand] |= Imm64;
3564 /* If BFD64, sign extend val. */
3565 if (!use_rela_relocations)
3566 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3567 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 3568 }
4c63da97 3569#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
47926f60 3570 else if (1
4c63da97 3571#ifdef BFD_ASSEMBLER
47926f60 3572 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3573#endif
47926f60 3574 && exp_seg != text_section
24eab124
AM		 3575 && exp_seg != data_section
3576 && exp_seg != bss_section
3577 && exp_seg != undefined_section
252b5132 3578#ifdef BFD_ASSEMBLER
24eab124 3579 && !bfd_is_com_section (exp_seg)
252b5132 3580#endif
24eab124 3581 )
252b5132 3582 {
4c63da97 3583#ifdef BFD_ASSEMBLER
d0b47220 3584 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3585#else
d0b47220 3586 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3587#endif
252b5132
RH		 3588 return 0;
3589 }
3590#endif
3591 else
3592 {
3593 /* This is an address. The size of the address will be
24eab124 3594 determined later, depending on destination register,
3e73aa7c
JH		 3595 suffix, or the default for the section. */
3596 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
252b5132
RH		 3597 }
3598
3599 return 1;
3600}
3601
551c1ca1 3602static char *i386_scale PARAMS ((char *));
252b5132 3603
551c1ca1 3604static char *
252b5132
RH		 3605i386_scale (scale)
3606 char *scale;
3607{
551c1ca1
AM		 3608 offsetT val;
3609 char *save = input_line_pointer;
252b5132 3610
551c1ca1
AM		 3611 input_line_pointer = scale;
3612 val = get_absolute_expression ();
3613
3614 switch (val)
252b5132 3615 {
551c1ca1
AM		 3616 case 0:
3617 case 1:
252b5132
RH		 3618 i.log2_scale_factor = 0;
3619 break;
551c1ca1 3620 case 2:
252b5132
RH		 3621 i.log2_scale_factor = 1;
3622 break;
551c1ca1 3623 case 4:
252b5132
RH		 3624 i.log2_scale_factor = 2;
3625 break;
551c1ca1 3626 case 8:
252b5132
RH		 3627 i.log2_scale_factor = 3;
3628 break;
3629 default:
252b5132 3630 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
24eab124 3631 scale);
551c1ca1
AM		 3632 input_line_pointer = save;
3633 return NULL;
252b5132 3634 }
29b0f896 3635 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 3636 {
3637 as_warn (_("scale factor of %d without an index register"),
24eab124 3638 1 << i.log2_scale_factor);
252b5132
RH		 3639#if SCALE1_WHEN_NO_INDEX
3640 i.log2_scale_factor = 0;
3641#endif
3642 }
551c1ca1
AM		 3643 scale = input_line_pointer;
3644 input_line_pointer = save;
3645 return scale;
252b5132
RH		 3646}
3647
3648static int i386_displacement PARAMS ((char *, char *));
3649
3650static int
3651i386_displacement (disp_start, disp_end)
3652 char *disp_start;
3653 char *disp_end;
3654{
29b0f896 3655 expressionS *exp;
252b5132
RH		 3656 segT exp_seg = 0;
3657 char *save_input_line_pointer;
f3c180ae
AM		 3658#ifndef LEX_AT
3659 char *gotfree_input_line;
3660#endif
252b5132
RH		 3661 int bigdisp = Disp32;
3662
3e73aa7c 3663 if (flag_code == CODE_64BIT)
7ecd2f8b 3664 {
29b0f896
AM		 3665 if (i.prefix[ADDR_PREFIX] == 0)
3666 bigdisp = Disp64;
7ecd2f8b
JH		 3667 }
3668 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3669 bigdisp = Disp16;
252b5132
RH		 3670 i.types[this_operand] |= bigdisp;
3671
3672 exp = &disp_expressions[i.disp_operands];
520dc8e8 3673 i.op[this_operand].disps = exp;
252b5132
RH		 3674 i.disp_operands++;
3675 save_input_line_pointer = input_line_pointer;
3676 input_line_pointer = disp_start;
3677 END_STRING_AND_SAVE (disp_end);
3678
3679#ifndef GCC_ASM_O_HACK
3680#define GCC_ASM_O_HACK 0
3681#endif
3682#if GCC_ASM_O_HACK
3683 END_STRING_AND_SAVE (disp_end + 1);
3684 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 3685 && displacement_string_end[-1] == '+')
252b5132
RH		 3686 {
3687 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 3688 constraint within gcc asm statements.
3689 For instance:
3690
3691 #define _set_tssldt_desc(n,addr,limit,type) \
3692 __asm__ __volatile__ ( \
3693 "movw %w2,%0\n\t" \
3694 "movw %w1,2+%0\n\t" \
3695 "rorl $16,%1\n\t" \
3696 "movb %b1,4+%0\n\t" \
3697 "movb %4,5+%0\n\t" \
3698 "movb $0,6+%0\n\t" \
3699 "movb %h1,7+%0\n\t" \
3700 "rorl $16,%1" \
3701 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3702
3703 This works great except that the output assembler ends
3704 up looking a bit weird if it turns out that there is
3705 no offset. You end up producing code that looks like:
3706
3707 #APP
3708 movw $235,(%eax)
3709 movw %dx,2+(%eax)
3710 rorl $16,%edx
3711 movb %dl,4+(%eax)
3712 movb $137,5+(%eax)
3713 movb $0,6+(%eax)
3714 movb %dh,7+(%eax)
3715 rorl $16,%edx
3716 #NO_APP
3717
47926f60 3718 So here we provide the missing zero. */
24eab124
AM		 3719
3720 *displacement_string_end = '0';
252b5132
RH		 3721 }
3722#endif
3723#ifndef LEX_AT
f3c180ae
AM		 3724 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3725 if (gotfree_input_line)
3726 input_line_pointer = gotfree_input_line;
252b5132
RH		 3727#endif
3728
24eab124 3729 exp_seg = expression (exp);
252b5132 3730
636c26b0
AM		 3731 SKIP_WHITESPACE ();
3732 if (*input_line_pointer)
3733 as_bad (_("junk `%s' after expression"), input_line_pointer);
3734#if GCC_ASM_O_HACK
3735 RESTORE_END_STRING (disp_end + 1);
3736#endif
3737 RESTORE_END_STRING (disp_end);
3738 input_line_pointer = save_input_line_pointer;
3739#ifndef LEX_AT
3740 if (gotfree_input_line)
3741 free (gotfree_input_line);
3742#endif
3743
252b5132 3744#ifdef BFD_ASSEMBLER
24eab124
AM		 3745 /* We do this to make sure that the section symbol is in
3746 the symbol table. We will ultimately change the relocation
47926f60 3747 to be relative to the beginning of the section. */
1ae12ab7
AM		 3748 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3749 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
24eab124 3750 {
636c26b0
AM		 3751 if (exp->X_op != O_symbol)
3752 {
3753 as_bad (_("bad expression used with @%s"),
3754 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3755 ? "GOTPCREL"
3756 : "GOTOFF"));
3757 return 0;
3758 }
3759
e5cb08ac 3760 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 3761 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3762 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 3763 exp->X_op = O_subtract;
3764 exp->X_op_symbol = GOT_symbol;
1ae12ab7 3765 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 3766 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
23df1078 3767 else
29b0f896 3768 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 3769 }
252b5132
RH		 3770#endif
3771
2daf4fd8
AM		 3772 if (exp->X_op == O_absent || exp->X_op == O_big)
3773 {
47926f60 3774 /* Missing or bad expr becomes absolute 0. */
d0b47220 3775 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 3776 disp_start);
3777 exp->X_op = O_constant;
3778 exp->X_add_number = 0;
3779 exp->X_add_symbol = (symbolS *) 0;
3780 exp->X_op_symbol = (symbolS *) 0;
3781 }
3782
4c63da97 3783#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 3784 if (exp->X_op != O_constant
4c63da97 3785#ifdef BFD_ASSEMBLER
45288df1 3786 && OUTPUT_FLAVOR == bfd_target_aout_flavour
4c63da97 3787#endif
45288df1
AM		 3788 && exp_seg != text_section
3789 && exp_seg != data_section
3790 && exp_seg != bss_section
3791 && exp_seg != undefined_section)
24eab124 3792 {
4c63da97 3793#ifdef BFD_ASSEMBLER
d0b47220 3794 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
4c63da97 3795#else
d0b47220 3796 as_bad (_("unimplemented segment type %d in operand"), exp_seg);
4c63da97 3797#endif
24eab124
AM		 3798 return 0;
3799 }
252b5132 3800#endif
3e73aa7c
JH		 3801 else if (flag_code == CODE_64BIT)
3802 i.types[this_operand] |= Disp32S | Disp32;
252b5132
RH		 3803 return 1;
3804}
3805
e5cb08ac 3806static int i386_index_check PARAMS ((const char *));
252b5132 3807
eecb386c 3808/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 3809 Return 1 on success, 0 on a failure. */
3810
252b5132 3811static int
eecb386c
AM		 3812i386_index_check (operand_string)
3813 const char *operand_string;
252b5132 3814{
3e73aa7c 3815 int ok;
24eab124 3816#if INFER_ADDR_PREFIX
eecb386c
AM		 3817 int fudged = 0;
3818
24eab124
AM		 3819 tryprefix:
3820#endif
3e73aa7c
JH		 3821 ok = 1;
3822 if (flag_code == CODE_64BIT)
3823 {
7ecd2f8b
JH		 3824 if (i.prefix[ADDR_PREFIX] == 0)
3825 {
3826 /* 64bit checks. */
3827 if ((i.base_reg
3828 && ((i.base_reg->reg_type & Reg64) == 0)
3829 && (i.base_reg->reg_type != BaseIndex
3830 || i.index_reg))
3831 || (i.index_reg
29b0f896
AM		 3832 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3833 != (Reg64 | BaseIndex))))
7ecd2f8b
JH		 3834 ok = 0;
3835 }
3836 else
3837 {
3838 /* 32bit checks. */
3839 if ((i.base_reg
3840 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3841 || (i.index_reg
29b0f896
AM		 3842 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3843 != (Reg32 | BaseIndex))))
7ecd2f8b
JH		 3844 ok = 0;
3845 }
3e73aa7c
JH		 3846 }
3847 else
3848 {
3849 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3850 {
3851 /* 16bit checks. */
3852 if ((i.base_reg
29b0f896
AM		 3853 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3854 != (Reg16 | BaseIndex)))
3e73aa7c 3855 || (i.index_reg
29b0f896
AM		 3856 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3857 != (Reg16 | BaseIndex))
3858 || !(i.base_reg
3859 && i.base_reg->reg_num < 6
3860 && i.index_reg->reg_num >= 6
3861 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 3862 ok = 0;
3863 }
3864 else
e5cb08ac 3865 {
3e73aa7c
JH		 3866 /* 32bit checks. */
3867 if ((i.base_reg
3868 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3869 || (i.index_reg
29b0f896
AM		 3870 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3871 != (Reg32 | BaseIndex))))
e5cb08ac 3872 ok = 0;
3e73aa7c
JH		 3873 }
3874 }
3875 if (!ok)
24eab124
AM		 3876 {
3877#if INFER_ADDR_PREFIX
3e73aa7c
JH		 3878 if (flag_code != CODE_64BIT
3879 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
24eab124
AM		 3880 {
3881 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
3882 i.prefixes += 1;
b23bac36
AM		 3883 /* Change the size of any displacement too. At most one of
3884 Disp16 or Disp32 is set.
3885 FIXME. There doesn't seem to be any real need for separate
3886 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 3887 Removing them would probably clean up the code quite a lot. */
29b0f896
AM		 3888 if (i.types[this_operand] & (Disp16 | Disp32))
3889 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 3890 fudged = 1;
24eab124
AM		 3891 goto tryprefix;
3892 }
eecb386c
AM		 3893 if (fudged)
3894 as_bad (_("`%s' is not a valid base/index expression"),
3895 operand_string);
3896 else
c388dee8 3897#endif
eecb386c
AM		 3898 as_bad (_("`%s' is not a valid %s bit base/index expression"),
3899 operand_string,
3e73aa7c 3900 flag_code_names[flag_code]);
eecb386c 3901 return 0;
24eab124
AM		 3902 }
3903 return 1;
3904}
252b5132 3905
252b5132 3906/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 3907 on error. */
252b5132 3908
252b5132
RH		 3909static int
3910i386_operand (operand_string)
3911 char *operand_string;
3912{
af6bdddf
AM		 3913 const reg_entry *r;
3914 char *end_op;
24eab124 3915 char *op_string = operand_string;
252b5132 3916
24eab124 3917 if (is_space_char (*op_string))
252b5132
RH		 3918 ++op_string;
3919
24eab124 3920 /* We check for an absolute prefix (differentiating,
47926f60 3921 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 3922 if (*op_string == ABSOLUTE_PREFIX)
3923 {
3924 ++op_string;
3925 if (is_space_char (*op_string))
3926 ++op_string;
3927 i.types[this_operand] |= JumpAbsolute;
3928 }
252b5132 3929
47926f60 3930 /* Check if operand is a register. */
af6bdddf
AM		 3931 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
3932 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 3933 {
24eab124
AM		 3934 /* Check for a segment override by searching for ':' after a
3935 segment register. */
3936 op_string = end_op;
3937 if (is_space_char (*op_string))
3938 ++op_string;
3939 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
3940 {
3941 switch (r->reg_num)
3942 {
3943 case 0:
3944 i.seg[i.mem_operands] = &es;
3945 break;
3946 case 1:
3947 i.seg[i.mem_operands] = &cs;
3948 break;
3949 case 2:
3950 i.seg[i.mem_operands] = &ss;
3951 break;
3952 case 3:
3953 i.seg[i.mem_operands] = &ds;
3954 break;
3955 case 4:
3956 i.seg[i.mem_operands] = &fs;
3957 break;
3958 case 5:
3959 i.seg[i.mem_operands] = &gs;
3960 break;
3961 }
252b5132 3962
24eab124 3963 /* Skip the ':' and whitespace. */
252b5132
RH		 3964 ++op_string;
3965 if (is_space_char (*op_string))
24eab124 3966 ++op_string;
252b5132 3967
24eab124
AM		 3968 if (!is_digit_char (*op_string)
3969 && !is_identifier_char (*op_string)
3970 && *op_string != '('
3971 && *op_string != ABSOLUTE_PREFIX)
3972 {
3973 as_bad (_("bad memory operand `%s'"), op_string);
3974 return 0;
3975 }
47926f60 3976 /* Handle case of %es:*foo. */
24eab124
AM		 3977 if (*op_string == ABSOLUTE_PREFIX)
3978 {
3979 ++op_string;
3980 if (is_space_char (*op_string))
3981 ++op_string;
3982 i.types[this_operand] |= JumpAbsolute;
3983 }
3984 goto do_memory_reference;
3985 }
3986 if (*op_string)
3987 {
d0b47220 3988 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 3989 return 0;
3990 }
3991 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 3992 i.op[this_operand].regs = r;
24eab124
AM		 3993 i.reg_operands++;
3994 }
af6bdddf
AM		 3995 else if (*op_string == REGISTER_PREFIX)
3996 {
3997 as_bad (_("bad register name `%s'"), op_string);
3998 return 0;
3999 }
24eab124 4000 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4001 {
24eab124
AM		 4002 ++op_string;
4003 if (i.types[this_operand] & JumpAbsolute)
4004 {
d0b47220 4005 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4006 return 0;
4007 }
4008 if (!i386_immediate (op_string))
4009 return 0;
4010 }
4011 else if (is_digit_char (*op_string)
4012 || is_identifier_char (*op_string)
e5cb08ac 4013 || *op_string == '(')
24eab124 4014 {
47926f60 4015 /* This is a memory reference of some sort. */
af6bdddf 4016 char *base_string;
252b5132 4017
47926f60 4018 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4019 char *displacement_string_start;
4020 char *displacement_string_end;
252b5132 4021
24eab124 4022 do_memory_reference:
24eab124
AM		 4023 if ((i.mem_operands == 1
4024 && (current_templates->start->opcode_modifier & IsString) == 0)
4025 || i.mem_operands == 2)
4026 {
4027 as_bad (_("too many memory references for `%s'"),
4028 current_templates->start->name);
4029 return 0;
4030 }
252b5132 4031
24eab124
AM		 4032 /* Check for base index form. We detect the base index form by
4033 looking for an ')' at the end of the operand, searching
4034 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4035 after the '('. */
af6bdddf 4036 base_string = op_string + strlen (op_string);
c3332e24 4037
af6bdddf
AM		 4038 --base_string;
4039 if (is_space_char (*base_string))
4040 --base_string;
252b5132 4041
47926f60 4042 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4043 displacement_string_start = op_string;
4044 displacement_string_end = base_string + 1;
252b5132 4045
24eab124
AM		 4046 if (*base_string == ')')
4047 {
af6bdddf 4048 char *temp_string;
24eab124
AM		 4049 unsigned int parens_balanced = 1;
4050 /* We've already checked that the number of left & right ()'s are
47926f60 4051 equal, so this loop will not be infinite. */
24eab124
AM		 4052 do
4053 {
4054 base_string--;
4055 if (*base_string == ')')
4056 parens_balanced++;
4057 if (*base_string == '(')
4058 parens_balanced--;
4059 }
4060 while (parens_balanced);
c3332e24 4061
af6bdddf 4062 temp_string = base_string;
c3332e24 4063
24eab124 4064 /* Skip past '(' and whitespace. */
252b5132
RH		 4065 ++base_string;
4066 if (is_space_char (*base_string))
24eab124 4067 ++base_string;
252b5132 4068
af6bdddf
AM		 4069 if (*base_string == ','
4070 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4071 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4072 {
af6bdddf 4073 displacement_string_end = temp_string;
252b5132 4074
af6bdddf 4075 i.types[this_operand] |= BaseIndex;
252b5132 4076
af6bdddf 4077 if (i.base_reg)
24eab124 4078 {
24eab124
AM		 4079 base_string = end_op;
4080 if (is_space_char (*base_string))
4081 ++base_string;
af6bdddf
AM		 4082 }
4083
4084 /* There may be an index reg or scale factor here. */
4085 if (*base_string == ',')
4086 {
4087 ++base_string;
4088 if (is_space_char (*base_string))
4089 ++base_string;
4090
4091 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4092 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4093 {
af6bdddf 4094 base_string = end_op;
24eab124
AM		 4095 if (is_space_char (*base_string))
4096 ++base_string;
af6bdddf
AM		 4097 if (*base_string == ',')
4098 {
4099 ++base_string;
4100 if (is_space_char (*base_string))
4101 ++base_string;
4102 }
e5cb08ac 4103 else if (*base_string != ')')
af6bdddf
AM		 4104 {
4105 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4106 operand_string);
4107 return 0;
4108 }
24eab124 4109 }
af6bdddf 4110 else if (*base_string == REGISTER_PREFIX)
24eab124 4111 {
af6bdddf 4112 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4113 return 0;
4114 }
252b5132 4115
47926f60 4116 /* Check for scale factor. */
551c1ca1 4117 if (*base_string != ')')
af6bdddf 4118 {
551c1ca1
AM		 4119 char *end_scale = i386_scale (base_string);
4120
4121 if (!end_scale)
af6bdddf 4122 return 0;
24eab124 4123
551c1ca1 4124 base_string = end_scale;
af6bdddf
AM		 4125 if (is_space_char (*base_string))
4126 ++base_string;
4127 if (*base_string != ')')
4128 {
4129 as_bad (_("expecting `)' after scale factor in `%s'"),
4130 operand_string);
4131 return 0;
4132 }
4133 }
4134 else if (!i.index_reg)
24eab124 4135 {
af6bdddf
AM		 4136 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4137 *base_string);
24eab124
AM		 4138 return 0;
4139 }
4140 }
af6bdddf 4141 else if (*base_string != ')')
24eab124 4142 {
af6bdddf
AM		 4143 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4144 operand_string);
24eab124
AM		 4145 return 0;
4146 }
c3332e24 4147 }
af6bdddf 4148 else if (*base_string == REGISTER_PREFIX)
c3332e24 4149 {
af6bdddf 4150 as_bad (_("bad register name `%s'"), base_string);
24eab124 4151 return 0;
c3332e24 4152 }
24eab124
AM		 4153 }
4154
4155 /* If there's an expression beginning the operand, parse it,
4156 assuming displacement_string_start and
4157 displacement_string_end are meaningful. */
4158 if (displacement_string_start != displacement_string_end)
4159 {
4160 if (!i386_displacement (displacement_string_start,
4161 displacement_string_end))
4162 return 0;
4163 }
4164
4165 /* Special case for (%dx) while doing input/output op. */
4166 if (i.base_reg
4167 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4168 && i.index_reg == 0
4169 && i.log2_scale_factor == 0
4170 && i.seg[i.mem_operands] == 0
4171 && (i.types[this_operand] & Disp) == 0)
4172 {
4173 i.types[this_operand] = InOutPortReg;
4174 return 1;
4175 }
4176
eecb386c
AM		 4177 if (i386_index_check (operand_string) == 0)
4178 return 0;
24eab124
AM		 4179 i.mem_operands++;
4180 }
4181 else
ce8a8b2f
AM		 4182 {
4183 /* It's not a memory operand; argh! */
24eab124
AM		 4184 as_bad (_("invalid char %s beginning operand %d `%s'"),
4185 output_invalid (*op_string),
4186 this_operand + 1,
4187 op_string);
4188 return 0;
4189 }
47926f60 4190 return 1; /* Normal return. */
252b5132
RH		 4191}
4192\f
ee7fcc42
AM		 4193/* md_estimate_size_before_relax()
4194
4195 Called just before relax() for rs_machine_dependent frags. The x86
4196 assembler uses these frags to handle variable size jump
4197 instructions.
4198
4199 Any symbol that is now undefined will not become defined.
4200 Return the correct fr_subtype in the frag.
4201 Return the initial "guess for variable size of frag" to caller.
4202 The guess is actually the growth beyond the fixed part. Whatever
4203 we do to grow the fixed or variable part contributes to our
4204 returned value. */
4205
252b5132
RH		 4206int
4207md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4208 fragS *fragP;
4209 segT segment;
252b5132 4210{
252b5132 4211 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4212 check for un-relaxable symbols. On an ELF system, we can't relax
4213 an externally visible symbol, because it may be overridden by a
4214 shared library. */
4215 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4216#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
b98ef147
AM		 4217 || S_IS_EXTERNAL (fragP->fr_symbol)
4218 || S_IS_WEAK (fragP->fr_symbol)
4219#endif
4220 )
252b5132 4221 {
b98ef147
AM		 4222 /* Symbol is undefined in this segment, or we need to keep a
4223 reloc so that weak symbols can be overridden. */
4224 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f3c180ae 4225 RELOC_ENUM reloc_type;
ee7fcc42
AM		 4226 unsigned char *opcode;
4227 int old_fr_fix;
f6af82bd 4228
ee7fcc42
AM		 4229 if (fragP->fr_var != NO_RELOC)
4230 reloc_type = fragP->fr_var;
b98ef147 4231 else if (size == 2)
f6af82bd
AM		 4232 reloc_type = BFD_RELOC_16_PCREL;
4233 else
4234 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4235
ee7fcc42
AM		 4236 old_fr_fix = fragP->fr_fix;
4237 opcode = (unsigned char *) fragP->fr_opcode;
4238
fddf5b5b 4239 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4240 {
fddf5b5b
AM		 4241 case UNCOND_JUMP:
4242 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4243 opcode[0] = 0xe9;
252b5132 4244 fragP->fr_fix += size;
062cd5e7
AS		 4245 fix_new (fragP, old_fr_fix, size,
4246 fragP->fr_symbol,
4247 fragP->fr_offset, 1,
4248 reloc_type);
252b5132
RH		 4249 break;
4250
fddf5b5b 4251 case COND_JUMP86:
412167cb
AM		 4252 if (size == 2
4253 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4254 {
4255 /* Negate the condition, and branch past an
4256 unconditional jump. */
4257 opcode[0] ^= 1;
4258 opcode[1] = 3;
4259 /* Insert an unconditional jump. */
4260 opcode[2] = 0xe9;
4261 /* We added two extra opcode bytes, and have a two byte
4262 offset. */
4263 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4264 fix_new (fragP, old_fr_fix + 2, 2,
4265 fragP->fr_symbol,
4266 fragP->fr_offset, 1,
4267 reloc_type);
fddf5b5b
AM		 4268 break;
4269 }
4270 /* Fall through. */
4271
4272 case COND_JUMP:
412167cb
AM		 4273 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4274 {
4275 fragP->fr_fix += 1;
4276 fix_new (fragP, old_fr_fix, 1,
4277 fragP->fr_symbol,
4278 fragP->fr_offset, 1,
4279 BFD_RELOC_8_PCREL);
4280 break;
4281 }
93c2a809 4282
24eab124 4283 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4284 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4285 opcode[1] = opcode[0] + 0x10;
f6af82bd 4286 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4287 /* We've added an opcode byte. */
4288 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4289 fix_new (fragP, old_fr_fix + 1, size,
4290 fragP->fr_symbol,
4291 fragP->fr_offset, 1,
4292 reloc_type);
252b5132 4293 break;
fddf5b5b
AM		 4294
4295 default:
4296 BAD_CASE (fragP->fr_subtype);
4297 break;
252b5132
RH		 4298 }
4299 frag_wane (fragP);
ee7fcc42 4300 return fragP->fr_fix - old_fr_fix;
252b5132 4301 }
93c2a809 4302
93c2a809
AM		 4303 /* Guess size depending on current relax state. Initially the relax
4304 state will correspond to a short jump and we return 1, because
4305 the variable part of the frag (the branch offset) is one byte
4306 long. However, we can relax a section more than once and in that
4307 case we must either set fr_subtype back to the unrelaxed state,
4308 or return the value for the appropriate branch. */
4309 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4310}
4311
47926f60
KH		 4312/* Called after relax() is finished.
4313
4314 In: Address of frag.
4315 fr_type == rs_machine_dependent.
4316 fr_subtype is what the address relaxed to.
4317
4318 Out: Any fixSs and constants are set up.
4319 Caller will turn frag into a ".space 0". */
4320
252b5132
RH		 4321#ifndef BFD_ASSEMBLER
4322void
4323md_convert_frag (headers, sec, fragP)
a04b544b
ILT		 4324 object_headers *headers ATTRIBUTE_UNUSED;
4325 segT sec ATTRIBUTE_UNUSED;
29b0f896 4326 fragS *fragP;
252b5132
RH		 4327#else
4328void
4329md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4330 bfd *abfd ATTRIBUTE_UNUSED;
4331 segT sec ATTRIBUTE_UNUSED;
29b0f896 4332 fragS *fragP;
252b5132
RH		 4333#endif
4334{
29b0f896 4335 unsigned char *opcode;
252b5132 4336 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4337 offsetT target_address;
4338 offsetT opcode_address;
252b5132 4339 unsigned int extension = 0;
847f7ad4 4340 offsetT displacement_from_opcode_start;
252b5132
RH		 4341
4342 opcode = (unsigned char *) fragP->fr_opcode;
4343
47926f60 4344 /* Address we want to reach in file space. */
252b5132 4345 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4346
47926f60 4347 /* Address opcode resides at in file space. */
252b5132
RH		 4348 opcode_address = fragP->fr_address + fragP->fr_fix;
4349
47926f60 4350 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4351 displacement_from_opcode_start = target_address - opcode_address;
4352
fddf5b5b 4353 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4354 {
47926f60
KH		 4355 /* Don't have to change opcode. */
4356 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4357 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4358 }
4359 else
4360 {
4361 if (no_cond_jump_promotion
4362 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4363 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4364
fddf5b5b
AM		 4365 switch (fragP->fr_subtype)
4366 {
4367 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4368 extension = 4; /* 1 opcode + 4 displacement */
4369 opcode[0] = 0xe9;
4370 where_to_put_displacement = &opcode[1];
4371 break;
252b5132 4372
fddf5b5b
AM		 4373 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4374 extension = 2; /* 1 opcode + 2 displacement */
4375 opcode[0] = 0xe9;
4376 where_to_put_displacement = &opcode[1];
4377 break;
252b5132 4378
fddf5b5b
AM		 4379 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4380 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4381 extension = 5; /* 2 opcode + 4 displacement */
4382 opcode[1] = opcode[0] + 0x10;
4383 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4384 where_to_put_displacement = &opcode[2];
4385 break;
252b5132 4386
fddf5b5b
AM		 4387 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4388 extension = 3; /* 2 opcode + 2 displacement */
4389 opcode[1] = opcode[0] + 0x10;
4390 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4391 where_to_put_displacement = &opcode[2];
4392 break;
252b5132 4393
fddf5b5b
AM		 4394 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4395 extension = 4;
4396 opcode[0] ^= 1;
4397 opcode[1] = 3;
4398 opcode[2] = 0xe9;
4399 where_to_put_displacement = &opcode[3];
4400 break;
4401
4402 default:
4403 BAD_CASE (fragP->fr_subtype);
4404 break;
4405 }
252b5132 4406 }
fddf5b5b 4407
47926f60 4408 /* Now put displacement after opcode. */
252b5132
RH		 4409 md_number_to_chars ((char *) where_to_put_displacement,
4410 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4411 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4412 fragP->fr_fix += extension;
4413}
4414\f
47926f60
KH		 4415/* Size of byte displacement jmp. */
4416int md_short_jump_size = 2;
4417
4418/* Size of dword displacement jmp. */
4419int md_long_jump_size = 5;
252b5132 4420
47926f60
KH		 4421/* Size of relocation record. */
4422const int md_reloc_size = 8;
252b5132
RH		 4423
4424void
4425md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4426 char *ptr;
4427 addressT from_addr, to_addr;
ab9da554
ILT		 4428 fragS *frag ATTRIBUTE_UNUSED;
4429 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4430{
847f7ad4 4431 offsetT offset;
252b5132
RH		 4432
4433 offset = to_addr - (from_addr + 2);
47926f60
KH		 4434 /* Opcode for byte-disp jump. */
4435 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4436 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4437}
4438
4439void
4440md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4441 char *ptr;
4442 addressT from_addr, to_addr;
a38cf1db
AM		 4443 fragS *frag ATTRIBUTE_UNUSED;
4444 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4445{
847f7ad4 4446 offsetT offset;
252b5132 4447
a38cf1db
AM		 4448 offset = to_addr - (from_addr + 5);
4449 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4450 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4451}
4452\f
4453/* Apply a fixup (fixS) to segment data, once it has been determined
4454 by our caller that we have all the info we need to fix it up.
4455
4456 On the 386, immediates, displacements, and data pointers are all in
4457 the same (little-endian) format, so we don't need to care about which
4458 we are handling. */
4459
94f592af
NC		 4460void
4461md_apply_fix3 (fixP, valP, seg)
47926f60
KH		 4462 /* The fix we're to put in. */
4463 fixS *fixP;
47926f60 4464 /* Pointer to the value of the bits. */
94f592af 4465 valueT * valP;
47926f60
KH		 4466 /* Segment fix is from. */
4467 segT seg ATTRIBUTE_UNUSED;
252b5132 4468{
94f592af
NC		 4469 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4470 valueT value = * valP;
252b5132 4471
e1b283bb 4472#if defined (BFD_ASSEMBLER) && !defined (TE_Mach)
93382f6d
AM		 4473 if (fixP->fx_pcrel)
4474 {
4475 switch (fixP->fx_r_type)
4476 {
5865bb77
ILT		 4477 default:
4478 break;
4479
93382f6d
AM		 4480 case BFD_RELOC_32:
4481 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4482 break;
4483 case BFD_RELOC_16:
4484 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4485 break;
4486 case BFD_RELOC_8:
4487 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4488 break;
4489 }
4490 }
252b5132 4491
0723899b
ILT		 4492 /* This is a hack. There should be a better way to handle this.
4493 This covers for the fact that bfd_install_relocation will
4494 subtract the current location (for partial_inplace, PC relative
4495 relocations); see more below. */
93382f6d
AM		 4496 if ((fixP->fx_r_type == BFD_RELOC_32_PCREL
4497 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4498 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7c44d1d3 4499 && fixP->fx_addsy && !use_rela_relocations)
252b5132
RH		 4500 {
4501#ifndef OBJ_AOUT
4502 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4503#ifdef TE_PE
4504 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4505#endif
4506 )
4507 value += fixP->fx_where + fixP->fx_frag->fr_address;
4508#endif
4509#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4510 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4511 {
2f66722d
AM		 4512 segT fseg = S_GET_SEGMENT (fixP->fx_addsy);
4513
4514 if ((fseg == seg
4515 || (symbol_section_p (fixP->fx_addsy)
4516 && fseg != absolute_section))
29b0f896
AM		 4517 && !S_IS_EXTERNAL (fixP->fx_addsy)
4518 && !S_IS_WEAK (fixP->fx_addsy)
2f66722d 4519 && S_IS_DEFINED (fixP->fx_addsy)
29b0f896 4520 && !S_IS_COMMON (fixP->fx_addsy))
2f66722d
AM		 4521 {
4522 /* Yes, we add the values in twice. This is because
4523 bfd_perform_relocation subtracts them out again. I think
4524 bfd_perform_relocation is broken, but I don't dare change
4525 it. FIXME. */
4526 value += fixP->fx_where + fixP->fx_frag->fr_address;
4527 }
252b5132
RH		 4528 }
4529#endif
4530#if defined (OBJ_COFF) && defined (TE_PE)
4531 /* For some reason, the PE format does not store a section
24eab124 4532 address offset for a PC relative symbol. */
252b5132
RH		 4533 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4534 value += md_pcrel_from (fixP);
4535#endif
4536 }
4537
4538 /* Fix a few things - the dynamic linker expects certain values here,
47926f60 4539 and we must not dissappoint it. */
252b5132
RH		 4540#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4541 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4542 && fixP->fx_addsy)
47926f60
KH		 4543 switch (fixP->fx_r_type)
4544 {
4545 case BFD_RELOC_386_PLT32:
3e73aa7c 4546 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4547 /* Make the jump instruction point to the address of the operand. At
4548 runtime we merely add the offset to the actual PLT entry. */
4549 value = -4;
4550 break;
4551 case BFD_RELOC_386_GOTPC:
4552
4553/* This is tough to explain. We end up with this one if we have
252b5132
RH		 4554 * operands that look like "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal
4555 * here is to obtain the absolute address of the GOT, and it is strongly
4556 * preferable from a performance point of view to avoid using a runtime
c3332e24 4557 * relocation for this. The actual sequence of instructions often look
252b5132 4558 * something like:
c3332e24 4559 *
24eab124 4560 * call .L66
252b5132 4561 * .L66:
24eab124
AM		 4562 * popl %ebx
4563 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
c3332e24 4564 *
24eab124 4565 * The call and pop essentially return the absolute address of
252b5132
RH		 4566 * the label .L66 and store it in %ebx. The linker itself will
4567 * ultimately change the first operand of the addl so that %ebx points to
4568 * the GOT, but to keep things simple, the .o file must have this operand
4569 * set so that it generates not the absolute address of .L66, but the
4570 * absolute address of itself. This allows the linker itself simply
4571 * treat a GOTPC relocation as asking for a pcrel offset to the GOT to be
4572 * added in, and the addend of the relocation is stored in the operand
4573 * field for the instruction itself.
c3332e24 4574 *
24eab124 4575 * Our job here is to fix the operand so that it would add the correct
252b5132
RH		 4576 * offset so that %ebx would point to itself. The thing that is tricky is
4577 * that .-.L66 will point to the beginning of the instruction, so we need
4578 * to further modify the operand so that it will point to itself.
4579 * There are other cases where you have something like:
c3332e24 4580 *
24eab124 4581 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
c3332e24 4582 *
252b5132 4583 * and here no correction would be required. Internally in the assembler
c3332e24 4584 * we treat operands of this form as not being pcrel since the '.' is
252b5132
RH		 4585 * explicitly mentioned, and I wonder whether it would simplify matters
4586 * to do it this way. Who knows. In earlier versions of the PIC patches,
4587 * the pcrel_adjust field was used to store the correction, but since the
47926f60
KH		 4588 * expression is not pcrel, I felt it would be confusing to do it this
4589 * way. */
4590
4591 value -= 1;
4592 break;
4593 case BFD_RELOC_386_GOT32:
13ae64f3
JJ		 4594 case BFD_RELOC_386_TLS_GD:
4595 case BFD_RELOC_386_TLS_LDM:
4596 case BFD_RELOC_386_TLS_LDO_32:
4597 case BFD_RELOC_386_TLS_IE_32:
4598 case BFD_RELOC_386_TLS_LE_32:
4599 case BFD_RELOC_386_TLS_LE:
3e73aa7c 4600 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 4601 value = 0; /* Fully resolved at runtime. No addend. */
4602 break;
4603 case BFD_RELOC_386_GOTOFF:
3e73aa7c 4604 case BFD_RELOC_X86_64_GOTPCREL:
47926f60
KH		 4605 break;
4606
4607 case BFD_RELOC_VTABLE_INHERIT:
4608 case BFD_RELOC_VTABLE_ENTRY:
4609 fixP->fx_done = 0;
94f592af 4610 return;
47926f60
KH		 4611
4612 default:
4613 break;
4614 }
4615#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
94f592af 4616 * valP = value;
47926f60 4617#endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */
3e73aa7c 4618
3e73aa7c 4619 /* Are we finished with this relocation now? */
94f592af 4620 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
3e73aa7c 4621 fixP->fx_done = 1;
94f592af 4622#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4623 else if (use_rela_relocations)
4624 {
4625 fixP->fx_no_overflow = 1;
062cd5e7
AS		 4626 /* Remember value for tc_gen_reloc. */
4627 fixP->fx_addnumber = value;
3e73aa7c
JH		 4628 value = 0;
4629 }
3e73aa7c 4630#endif
94f592af 4631 md_number_to_chars (p, value, fixP->fx_size);
252b5132 4632}
252b5132 4633\f
252b5132
RH		 4634#define MAX_LITTLENUMS 6
4635
47926f60
KH		 4636/* Turn the string pointed to by litP into a floating point constant
4637 of type TYPE, and emit the appropriate bytes. The number of
4638 LITTLENUMS emitted is stored in *SIZEP. An error message is
4639 returned, or NULL on OK. */
4640
252b5132
RH		 4641char *
4642md_atof (type, litP, sizeP)
2ab9b79e 4643 int type;
252b5132
RH		 4644 char *litP;
4645 int *sizeP;
4646{
4647 int prec;
4648 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4649 LITTLENUM_TYPE *wordP;
4650 char *t;
4651
4652 switch (type)
4653 {
4654 case 'f':
4655 case 'F':
4656 prec = 2;
4657 break;
4658
4659 case 'd':
4660 case 'D':
4661 prec = 4;
4662 break;
4663
4664 case 'x':
4665 case 'X':
4666 prec = 5;
4667 break;
4668
4669 default:
4670 *sizeP = 0;
4671 return _("Bad call to md_atof ()");
4672 }
4673 t = atof_ieee (input_line_pointer, type, words);
4674 if (t)
4675 input_line_pointer = t;
4676
4677 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4678 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4679 the bigendian 386. */
4680 for (wordP = words + prec - 1; prec--;)
4681 {
4682 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4683 litP += sizeof (LITTLENUM_TYPE);
4684 }
4685 return 0;
4686}
4687\f
4688char output_invalid_buf[8];
4689
252b5132
RH		 4690static char *
4691output_invalid (c)
4692 int c;
4693{
3882b010 4694 if (ISPRINT (c))
252b5132
RH		 4695 sprintf (output_invalid_buf, "'%c'", c);
4696 else
4697 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4698 return output_invalid_buf;
4699}
4700
af6bdddf 4701/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 4702
4703static const reg_entry *
4704parse_register (reg_string, end_op)
4705 char *reg_string;
4706 char **end_op;
4707{
af6bdddf
AM		 4708 char *s = reg_string;
4709 char *p;
252b5132
RH		 4710 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4711 const reg_entry *r;
4712
4713 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4714 if (*s == REGISTER_PREFIX)
4715 ++s;
4716
4717 if (is_space_char (*s))
4718 ++s;
4719
4720 p = reg_name_given;
af6bdddf 4721 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 4722 {
4723 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 4724 return (const reg_entry *) NULL;
4725 s++;
252b5132
RH		 4726 }
4727
6588847e
DN		 4728 /* For naked regs, make sure that we are not dealing with an identifier.
4729 This prevents confusing an identifier like `eax_var' with register
4730 `eax'. */
4731 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4732 return (const reg_entry *) NULL;
4733
af6bdddf 4734 *end_op = s;
252b5132
RH		 4735
4736 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4737
5f47d35b 4738 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 4739 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 4740 {
5f47d35b
AM		 4741 if (is_space_char (*s))
4742 ++s;
4743 if (*s == '(')
4744 {
af6bdddf 4745 ++s;
5f47d35b
AM		 4746 if (is_space_char (*s))
4747 ++s;
4748 if (*s >= '0' && *s <= '7')
4749 {
4750 r = &i386_float_regtab[*s - '0'];
af6bdddf 4751 ++s;
5f47d35b
AM		 4752 if (is_space_char (*s))
4753 ++s;
4754 if (*s == ')')
4755 {
4756 *end_op = s + 1;
4757 return r;
4758 }
5f47d35b 4759 }
47926f60 4760 /* We have "%st(" then garbage. */
5f47d35b
AM		 4761 return (const reg_entry *) NULL;
4762 }
4763 }
4764
1ae00879 4765 if (r != NULL
29b0f896 4766 && (r->reg_flags & (RegRex64 | RegRex)) != 0
1ae00879
AM		 4767 && flag_code != CODE_64BIT)
4768 {
4769 return (const reg_entry *) NULL;
4770 }
4771
252b5132
RH		 4772 return r;
4773}
4774\f
4cc782b5 4775#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
65172ab8 4776const char *md_shortopts = "kVQ:sq";
252b5132 4777#else
65172ab8 4778const char *md_shortopts = "q";
252b5132 4779#endif
6e0b89ee 4780
252b5132 4781struct option md_longopts[] = {
3e73aa7c
JH		 4782#define OPTION_32 (OPTION_MD_BASE + 0)
4783 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 4784#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 4785#define OPTION_64 (OPTION_MD_BASE + 1)
4786 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 4787#endif
252b5132
RH		 4788 {NULL, no_argument, NULL, 0}
4789};
4790size_t md_longopts_size = sizeof (md_longopts);
4791
4792int
4793md_parse_option (c, arg)
4794 int c;
ab9da554 4795 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 4796{
4797 switch (c)
4798 {
a38cf1db
AM		 4799 case 'q':
4800 quiet_warnings = 1;
252b5132
RH		 4801 break;
4802
4803#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 4804 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4805 should be emitted or not. FIXME: Not implemented. */
4806 case 'Q':
252b5132
RH		 4807 break;
4808
4809 /* -V: SVR4 argument to print version ID. */
4810 case 'V':
4811 print_version_id ();
4812 break;
4813
a38cf1db
AM		 4814 /* -k: Ignore for FreeBSD compatibility. */
4815 case 'k':
252b5132 4816 break;
4cc782b5
ILT		 4817
4818 case 's':
4819 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 4820 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 4821 break;
6e0b89ee 4822
3e73aa7c
JH		 4823 case OPTION_64:
4824 {
4825 const char **list, **l;
4826
3e73aa7c
JH		 4827 list = bfd_target_list ();
4828 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 4829 if (strcmp (*l, "elf64-x86-64") == 0)
4830 {
4831 default_arch = "x86_64";
4832 break;
4833 }
3e73aa7c 4834 if (*l == NULL)
6e0b89ee 4835 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 4836 free (list);
4837 }
4838 break;
4839#endif
252b5132 4840
6e0b89ee
AM		 4841 case OPTION_32:
4842 default_arch = "i386";
4843 break;
4844
252b5132
RH		 4845 default:
4846 return 0;
4847 }
4848 return 1;
4849}
4850
4851void
4852md_show_usage (stream)
4853 FILE *stream;
4854{
4cc782b5
ILT		 4855#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4856 fprintf (stream, _("\
a38cf1db
AM		 4857 -Q ignored\n\
4858 -V print assembler version number\n\
4859 -k ignored\n\
4860 -q quieten some warnings\n\
4861 -s ignored\n"));
4862#else
4863 fprintf (stream, _("\
4864 -q quieten some warnings\n"));
4cc782b5 4865#endif
252b5132
RH		 4866}
4867
4868#ifdef BFD_ASSEMBLER
3e73aa7c
JH		 4869#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4870 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 4871
4872/* Pick the target format to use. */
4873
47926f60 4874const char *
252b5132
RH		 4875i386_target_format ()
4876{
3e73aa7c
JH		 4877 if (!strcmp (default_arch, "x86_64"))
4878 set_code_flag (CODE_64BIT);
4879 else if (!strcmp (default_arch, "i386"))
4880 set_code_flag (CODE_32BIT);
4881 else
4882 as_fatal (_("Unknown architecture"));
252b5132
RH		 4883 switch (OUTPUT_FLAVOR)
4884 {
4c63da97
AM		 4885#ifdef OBJ_MAYBE_AOUT
4886 case bfd_target_aout_flavour:
47926f60 4887 return AOUT_TARGET_FORMAT;
4c63da97
AM		 4888#endif
4889#ifdef OBJ_MAYBE_COFF
252b5132
RH		 4890 case bfd_target_coff_flavour:
4891 return "coff-i386";
4c63da97 4892#endif
3e73aa7c 4893#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 4894 case bfd_target_elf_flavour:
3e73aa7c 4895 {
e5cb08ac
KH		 4896 if (flag_code == CODE_64BIT)
4897 use_rela_relocations = 1;
4898 return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386";
3e73aa7c 4899 }
4c63da97 4900#endif
252b5132
RH		 4901 default:
4902 abort ();
4903 return NULL;
4904 }
4905}
4906
47926f60 4907#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 4908
4909#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4910void i386_elf_emit_arch_note ()
4911{
4912 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4913 && cpu_arch_name != NULL)
4914 {
4915 char *p;
4916 asection *seg = now_seg;
4917 subsegT subseg = now_subseg;
4918 Elf_Internal_Note i_note;
4919 Elf_External_Note e_note;
4920 asection *note_secp;
4921 int len;
4922
4923 /* Create the .note section. */
4924 note_secp = subseg_new (".note", 0);
4925 bfd_set_section_flags (stdoutput,
4926 note_secp,
4927 SEC_HAS_CONTENTS | SEC_READONLY);
4928
4929 /* Process the arch string. */
4930 len = strlen (cpu_arch_name);
4931
4932 i_note.namesz = len + 1;
4933 i_note.descsz = 0;
4934 i_note.type = NT_ARCH;
4935 p = frag_more (sizeof (e_note.namesz));
4936 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
4937 p = frag_more (sizeof (e_note.descsz));
4938 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
4939 p = frag_more (sizeof (e_note.type));
4940 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
4941 p = frag_more (len + 1);
4942 strcpy (p, cpu_arch_name);
4943
4944 frag_align (2, 0, 0);
4945
4946 subseg_set (seg, subseg);
4947 }
4948}
4949#endif
47926f60 4950#endif /* BFD_ASSEMBLER */
252b5132 4951\f
252b5132
RH		 4952symbolS *
4953md_undefined_symbol (name)
4954 char *name;
4955{
18dc2407
ILT		 4956 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
4957 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
4958 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
4959 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 4960 {
4961 if (!GOT_symbol)
4962 {
4963 if (symbol_find (name))
4964 as_bad (_("GOT already in symbol table"));
4965 GOT_symbol = symbol_new (name, undefined_section,
4966 (valueT) 0, &zero_address_frag);
4967 };
4968 return GOT_symbol;
4969 }
252b5132
RH		 4970 return 0;
4971}
4972
4973/* Round up a section size to the appropriate boundary. */
47926f60 4974
252b5132
RH		 4975valueT
4976md_section_align (segment, size)
ab9da554 4977 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 4978 valueT size;
4979{
252b5132 4980#ifdef BFD_ASSEMBLER
4c63da97
AM		 4981#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
4982 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
4983 {
4984 /* For a.out, force the section size to be aligned. If we don't do
4985 this, BFD will align it for us, but it will not write out the
4986 final bytes of the section. This may be a bug in BFD, but it is
4987 easier to fix it here since that is how the other a.out targets
4988 work. */
4989 int align;
4990
4991 align = bfd_get_section_alignment (stdoutput, segment);
4992 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
4993 }
252b5132
RH		 4994#endif
4995#endif
4996
4997 return size;
4998}
4999
5000/* On the i386, PC-relative offsets are relative to the start of the
5001 next instruction. That is, the address of the offset, plus its
5002 size, since the offset is always the last part of the insn. */
5003
5004long
5005md_pcrel_from (fixP)
5006 fixS *fixP;
5007{
5008 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5009}
5010
5011#ifndef I386COFF
5012
5013static void
5014s_bss (ignore)
ab9da554 5015 int ignore ATTRIBUTE_UNUSED;
252b5132 5016{
29b0f896 5017 int temp;
252b5132
RH		 5018
5019 temp = get_absolute_expression ();
5020 subseg_set (bss_section, (subsegT) temp);
5021 demand_empty_rest_of_line ();
5022}
5023
5024#endif
5025
252b5132
RH		 5026#ifdef BFD_ASSEMBLER
5027
5028void
5029i386_validate_fix (fixp)
5030 fixS *fixp;
5031{
5032 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5033 {
3e73aa7c 5034 /* GOTOFF relocation are nonsense in 64bit mode. */
23df1078
JH		 5035 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5036 {
5037 if (flag_code != CODE_64BIT)
5038 abort ();
5039 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5040 }
5041 else
5042 {
5043 if (flag_code == CODE_64BIT)
5044 abort ();
5045 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5046 }
252b5132
RH		 5047 fixp->fx_subsy = 0;
5048 }
5049}
5050
252b5132
RH		 5051arelent *
5052tc_gen_reloc (section, fixp)
ab9da554 5053 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5054 fixS *fixp;
5055{
5056 arelent *rel;
5057 bfd_reloc_code_real_type code;
5058
5059 switch (fixp->fx_r_type)
5060 {
3e73aa7c
JH		 5061 case BFD_RELOC_X86_64_PLT32:
5062 case BFD_RELOC_X86_64_GOT32:
5063 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5064 case BFD_RELOC_386_PLT32:
5065 case BFD_RELOC_386_GOT32:
5066 case BFD_RELOC_386_GOTOFF:
5067 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5068 case BFD_RELOC_386_TLS_GD:
5069 case BFD_RELOC_386_TLS_LDM:
5070 case BFD_RELOC_386_TLS_LDO_32:
5071 case BFD_RELOC_386_TLS_IE_32:
5072 case BFD_RELOC_386_TLS_LE_32:
5073 case BFD_RELOC_386_TLS_LE:
3e73aa7c 5074 case BFD_RELOC_X86_64_32S:
252b5132
RH		 5075 case BFD_RELOC_RVA:
5076 case BFD_RELOC_VTABLE_ENTRY:
5077 case BFD_RELOC_VTABLE_INHERIT:
5078 code = fixp->fx_r_type;
5079 break;
5080 default:
93382f6d 5081 if (fixp->fx_pcrel)
252b5132 5082 {
93382f6d
AM		 5083 switch (fixp->fx_size)
5084 {
5085 default:
b091f402
AM		 5086 as_bad_where (fixp->fx_file, fixp->fx_line,
5087 _("can not do %d byte pc-relative relocation"),
5088 fixp->fx_size);
93382f6d
AM		 5089 code = BFD_RELOC_32_PCREL;
5090 break;
5091 case 1: code = BFD_RELOC_8_PCREL; break;
5092 case 2: code = BFD_RELOC_16_PCREL; break;
5093 case 4: code = BFD_RELOC_32_PCREL; break;
5094 }
5095 }
5096 else
5097 {
5098 switch (fixp->fx_size)
5099 {
5100 default:
b091f402
AM		 5101 as_bad_where (fixp->fx_file, fixp->fx_line,
5102 _("can not do %d byte relocation"),
5103 fixp->fx_size);
93382f6d
AM		 5104 code = BFD_RELOC_32;
5105 break;
5106 case 1: code = BFD_RELOC_8; break;
5107 case 2: code = BFD_RELOC_16; break;
5108 case 4: code = BFD_RELOC_32; break;
937149dd 5109#ifdef BFD64
3e73aa7c 5110 case 8: code = BFD_RELOC_64; break;
937149dd 5111#endif
93382f6d 5112 }
252b5132
RH		 5113 }
5114 break;
5115 }
252b5132
RH		 5116
5117 if (code == BFD_RELOC_32
5118 && GOT_symbol
5119 && fixp->fx_addsy == GOT_symbol)
3e73aa7c
JH		 5120 {
5121 /* We don't support GOTPC on 64bit targets. */
5122 if (flag_code == CODE_64BIT)
bfb32b52 5123 abort ();
3e73aa7c
JH		 5124 code = BFD_RELOC_386_GOTPC;
5125 }
252b5132
RH		 5126
5127 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5128 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5129 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5130
5131 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
3e73aa7c
JH		 5132 if (!use_rela_relocations)
5133 {
5134 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5135 vtable entry to be used in the relocation's section offset. */
5136 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5137 rel->address = fixp->fx_offset;
252b5132 5138
3e73aa7c
JH		 5139 if (fixp->fx_pcrel)
5140 rel->addend = fixp->fx_addnumber;
5141 else
5142 rel->addend = 0;
5143 }
5144 /* Use the rela in 64bit mode. */
252b5132 5145 else
3e73aa7c 5146 {
062cd5e7
AS		 5147 if (!fixp->fx_pcrel)
5148 rel->addend = fixp->fx_offset;
5149 else
5150 switch (code)
5151 {
5152 case BFD_RELOC_X86_64_PLT32:
5153 case BFD_RELOC_X86_64_GOT32:
5154 case BFD_RELOC_X86_64_GOTPCREL:
5155 rel->addend = fixp->fx_offset - fixp->fx_size;
5156 break;
5157 default:
5158 rel->addend = (section->vma
5159 - fixp->fx_size
5160 + fixp->fx_addnumber
5161 + md_pcrel_from (fixp));
5162 break;
5163 }
3e73aa7c
JH		 5164 }
5165
252b5132
RH		 5166 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5167 if (rel->howto == NULL)
5168 {
5169 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5170 _("cannot represent relocation type %s"),
252b5132
RH		 5171 bfd_get_reloc_code_name (code));
5172 /* Set howto to a garbage value so that we can keep going. */
5173 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5174 assert (rel->howto != NULL);
5175 }
5176
5177 return rel;
5178}
5179
29b0f896 5180#else /* !BFD_ASSEMBLER */
252b5132
RH		 5181
5182#if (defined(OBJ_AOUT) | defined(OBJ_BOUT))
5183void
5184tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
5185 char *where;
5186 fixS *fixP;
5187 relax_addressT segment_address_in_file;
5188{
47926f60
KH		 5189 /* In: length of relocation (or of address) in chars: 1, 2 or 4.
5190 Out: GNU LD relocation length code: 0, 1, or 2. */
252b5132 5191
47926f60 5192 static const unsigned char nbytes_r_length[] = { 42, 0, 1, 42, 2 };
252b5132
RH		 5193 long r_symbolnum;
5194
5195 know (fixP->fx_addsy != NULL);
5196
5197 md_number_to_chars (where,
5198 (valueT) (fixP->fx_frag->fr_address
5199 + fixP->fx_where - segment_address_in_file),
5200 4);
5201
5202 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
5203 ? S_GET_TYPE (fixP->fx_addsy)
5204 : fixP->fx_addsy->sy_number);
5205
5206 where[6] = (r_symbolnum >> 16) & 0x0ff;
5207 where[5] = (r_symbolnum >> 8) & 0x0ff;
5208 where[4] = r_symbolnum & 0x0ff;
5209 where[7] = ((((!S_IS_DEFINED (fixP->fx_addsy)) << 3) & 0x08)
5210 | ((nbytes_r_length[fixP->fx_size] << 1) & 0x06)
5211 | (((fixP->fx_pcrel << 0) & 0x01) & 0x0f));
5212}
5213
47926f60 5214#endif /* OBJ_AOUT or OBJ_BOUT. */
252b5132
RH		 5215
5216#if defined (I386COFF)
5217
5218short
5219tc_coff_fix2rtype (fixP)
5220 fixS *fixP;
5221{
5222 if (fixP->fx_r_type == R_IMAGEBASE)
5223 return R_IMAGEBASE;
5224
5225 return (fixP->fx_pcrel ?
5226 (fixP->fx_size == 1 ? R_PCRBYTE :
5227 fixP->fx_size == 2 ? R_PCRWORD :
5228 R_PCRLONG) :
5229 (fixP->fx_size == 1 ? R_RELBYTE :
5230 fixP->fx_size == 2 ? R_RELWORD :
5231 R_DIR32));
5232}
5233
5234int
5235tc_coff_sizemachdep (frag)
5236 fragS *frag;
5237{
5238 if (frag->fr_next)
5239 return (frag->fr_next->fr_address - frag->fr_address);
5240 else
5241 return 0;
5242}
5243
47926f60 5244#endif /* I386COFF */
252b5132 5245
29b0f896 5246#endif /* !BFD_ASSEMBLER */
64a0c779
DN		 5247\f
5248/* Parse operands using Intel syntax. This implements a recursive descent
5249 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5250 Programmer's Guide.
5251
5252 FIXME: We do not recognize the full operand grammar defined in the MASM
5253 documentation. In particular, all the structure/union and
5254 high-level macro operands are missing.
5255
5256 Uppercase words are terminals, lower case words are non-terminals.
5257 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5258 bars '|' denote choices. Most grammar productions are implemented in
5259 functions called 'intel_<production>'.
5260
5261 Initial production is 'expr'.
5262
64a0c779
DN		 5263 addOp + | -
5264
5265 alpha [a-zA-Z]
5266
5267 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5268
5269 constant digits [[ radixOverride ]]
5270
5271 dataType BYTE | WORD | DWORD | QWORD | XWORD
5272
5273 digits decdigit
b77a7acd
AJ		 5274 | digits decdigit
5275 | digits hexdigit
64a0c779
DN		 5276
5277 decdigit [0-9]
5278
5279 e05 e05 addOp e06
b77a7acd 5280 | e06
64a0c779
DN		 5281
5282 e06 e06 mulOp e09
b77a7acd 5283 | e09
64a0c779
DN		 5284
5285 e09 OFFSET e10
5286 | e09 PTR e10
5287 | e09 : e10
5288 | e10
5289
5290 e10 e10 [ expr ]
b77a7acd 5291 | e11
64a0c779
DN		 5292
5293 e11 ( expr )
b77a7acd 5294 | [ expr ]
64a0c779
DN		 5295 | constant
5296 | dataType
5297 | id
5298 | $
5299 | register
5300
5301 => expr SHORT e05
b77a7acd 5302 | e05
64a0c779
DN		 5303
5304 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5305 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5306
5307 hexdigit a | b | c | d | e | f
b77a7acd 5308 | A | B | C | D | E | F
64a0c779
DN		 5309
5310 id alpha
b77a7acd 5311 | id alpha
64a0c779
DN		 5312 | id decdigit
5313
5314 mulOp * | / | MOD
5315
5316 quote " | '
5317
5318 register specialRegister
b77a7acd 5319 | gpRegister
64a0c779
DN		 5320 | byteRegister
5321
5322 segmentRegister CS | DS | ES | FS | GS | SS
5323
5324 specialRegister CR0 | CR2 | CR3
b77a7acd 5325 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5326 | TR3 | TR4 | TR5 | TR6 | TR7
5327
64a0c779
DN		 5328 We simplify the grammar in obvious places (e.g., register parsing is
5329 done by calling parse_register) and eliminate immediate left recursion
5330 to implement a recursive-descent parser.
5331
5332 expr SHORT e05
b77a7acd 5333 | e05
64a0c779
DN		 5334
5335 e05 e06 e05'
5336
5337 e05' addOp e06 e05'
b77a7acd 5338 | Empty
64a0c779
DN		 5339
5340 e06 e09 e06'
5341
5342 e06' mulOp e09 e06'
b77a7acd 5343 | Empty
64a0c779
DN		 5344
5345 e09 OFFSET e10 e09'
b77a7acd 5346 | e10 e09'
64a0c779
DN		 5347
5348 e09' PTR e10 e09'
b77a7acd 5349 | : e10 e09'
64a0c779
DN		 5350 | Empty
5351
5352 e10 e11 e10'
5353
5354 e10' [ expr ] e10'
b77a7acd 5355 | Empty
64a0c779
DN		 5356
5357 e11 ( expr )
b77a7acd 5358 | [ expr ]
64a0c779
DN		 5359 | BYTE
5360 | WORD
5361 | DWORD
5362 | QWORD
5363 | XWORD
5364 | .
5365 | $
5366 | register
5367 | id
5368 | constant */
5369
5370/* Parsing structure for the intel syntax parser. Used to implement the
5371 semantic actions for the operand grammar. */
5372struct intel_parser_s
5373 {
5374 char *op_string; /* The string being parsed. */
5375 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5376 int op_modifier; /* Operand modifier. */
64a0c779
DN		 5377 int is_mem; /* 1 if operand is memory reference. */
5378 const reg_entry *reg; /* Last register reference found. */
5379 char *disp; /* Displacement string being built. */
5380 };
5381
5382static struct intel_parser_s intel_parser;
5383
5384/* Token structure for parsing intel syntax. */
5385struct intel_token
5386 {
5387 int code; /* Token code. */
5388 const reg_entry *reg; /* Register entry for register tokens. */
5389 char *str; /* String representation. */
5390 };
5391
5392static struct intel_token cur_token, prev_token;
5393
50705ef4
AM		 5394/* Token codes for the intel parser. Since T_SHORT is already used
5395 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5396#define T_NIL -1
5397#define T_CONST 1
5398#define T_REG 2
5399#define T_BYTE 3
5400#define T_WORD 4
5401#define T_DWORD 5
5402#define T_QWORD 6
5403#define T_XWORD 7
50705ef4 5404#undef T_SHORT
64a0c779
DN		 5405#define T_SHORT 8
5406#define T_OFFSET 9
5407#define T_PTR 10
5408#define T_ID 11
5409
5410/* Prototypes for intel parser functions. */
5411static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5412static void intel_get_token PARAMS ((void));
5413static void intel_putback_token PARAMS ((void));
5414static int intel_expr PARAMS ((void));
5415static int intel_e05 PARAMS ((void));
5416static int intel_e05_1 PARAMS ((void));
5417static int intel_e06 PARAMS ((void));
5418static int intel_e06_1 PARAMS ((void));
5419static int intel_e09 PARAMS ((void));
5420static int intel_e09_1 PARAMS ((void));
5421static int intel_e10 PARAMS ((void));
5422static int intel_e10_1 PARAMS ((void));
5423static int intel_e11 PARAMS ((void));
64a0c779 5424
64a0c779
DN		 5425static int
5426i386_intel_operand (operand_string, got_a_float)
5427 char *operand_string;
5428 int got_a_float;
5429{
5430 int ret;
5431 char *p;
5432
5433 /* Initialize token holders. */
5434 cur_token.code = prev_token.code = T_NIL;
5435 cur_token.reg = prev_token.reg = NULL;
5436 cur_token.str = prev_token.str = NULL;
5437
5438 /* Initialize parser structure. */
e5cb08ac 5439 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5440 if (p == NULL)
5441 abort ();
5442 strcpy (intel_parser.op_string, operand_string);
5443 intel_parser.got_a_float = got_a_float;
5444 intel_parser.op_modifier = -1;
5445 intel_parser.is_mem = 0;
5446 intel_parser.reg = NULL;
e5cb08ac 5447 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
64a0c779
DN		 5448 if (intel_parser.disp == NULL)
5449 abort ();
5450 intel_parser.disp[0] = '\0';
5451
5452 /* Read the first token and start the parser. */
5453 intel_get_token ();
5454 ret = intel_expr ();
5455
5456 if (ret)
5457 {
5458 /* If we found a memory reference, hand it over to i386_displacement
5459 to fill in the rest of the operand fields. */
5460 if (intel_parser.is_mem)
5461 {
5462 if ((i.mem_operands == 1
5463 && (current_templates->start->opcode_modifier & IsString) == 0)
5464 || i.mem_operands == 2)
5465 {
5466 as_bad (_("too many memory references for '%s'"),
5467 current_templates->start->name);
5468 ret = 0;
5469 }
5470 else
5471 {
5472 char *s = intel_parser.disp;
5473 i.mem_operands++;
5474
5475 /* Add the displacement expression. */
5476 if (*s != '\0')
5477 ret = i386_displacement (s, s + strlen (s))
5478 && i386_index_check (s);
5479 }
5480 }
5481
5482 /* Constant and OFFSET expressions are handled by i386_immediate. */
5483 else if (intel_parser.op_modifier == OFFSET_FLAT
5484 || intel_parser.reg == NULL)
5485 ret = i386_immediate (intel_parser.disp);
5486 }
5487
5488 free (p);
5489 free (intel_parser.disp);
5490
5491 return ret;
5492}
5493
64a0c779 5494/* expr SHORT e05
b77a7acd 5495 | e05 */
64a0c779
DN		 5496static int
5497intel_expr ()
5498{
5499 /* expr SHORT e05 */
5500 if (cur_token.code == T_SHORT)
5501 {
5502 intel_parser.op_modifier = SHORT;
5503 intel_match_token (T_SHORT);
5504
5505 return (intel_e05 ());
5506 }
5507
5508 /* expr e05 */
5509 else
5510 return intel_e05 ();
5511}
5512
64a0c779
DN		 5513/* e05 e06 e05'
5514
4a1805b1 5515 e05' addOp e06 e05'
64a0c779
DN		 5516 | Empty */
5517static int
5518intel_e05 ()
5519{
5520 return (intel_e06 () && intel_e05_1 ());
5521}
5522
5523static int
5524intel_e05_1 ()
5525{
5526 /* e05' addOp e06 e05' */
5527 if (cur_token.code == '+' || cur_token.code == '-')
5528 {
5529 strcat (intel_parser.disp, cur_token.str);
5530 intel_match_token (cur_token.code);
5531
5532 return (intel_e06 () && intel_e05_1 ());
5533 }
5534
5535 /* e05' Empty */
5536 else
5537 return 1;
4a1805b1 5538}
64a0c779
DN		 5539
5540/* e06 e09 e06'
5541
5542 e06' mulOp e09 e06'
b77a7acd 5543 | Empty */
64a0c779
DN		 5544static int
5545intel_e06 ()
5546{
5547 return (intel_e09 () && intel_e06_1 ());
5548}
5549
5550static int
5551intel_e06_1 ()
5552{
5553 /* e06' mulOp e09 e06' */
5554 if (cur_token.code == '*' || cur_token.code == '/')
5555 {
5556 strcat (intel_parser.disp, cur_token.str);
5557 intel_match_token (cur_token.code);
5558
5559 return (intel_e09 () && intel_e06_1 ());
5560 }
4a1805b1 5561
64a0c779 5562 /* e06' Empty */
4a1805b1 5563 else
64a0c779
DN		 5564 return 1;
5565}
5566
64a0c779 5567/* e09 OFFSET e10 e09'
b77a7acd 5568 | e10 e09'
64a0c779
DN		 5569
5570 e09' PTR e10 e09'
b77a7acd 5571 | : e10 e09'
64a0c779
DN		 5572 | Empty */
5573static int
5574intel_e09 ()
5575{
5576 /* e09 OFFSET e10 e09' */
5577 if (cur_token.code == T_OFFSET)
5578 {
5579 intel_parser.is_mem = 0;
5580 intel_parser.op_modifier = OFFSET_FLAT;
5581 intel_match_token (T_OFFSET);
5582
5583 return (intel_e10 () && intel_e09_1 ());
5584 }
5585
5586 /* e09 e10 e09' */
5587 else
5588 return (intel_e10 () && intel_e09_1 ());
5589}
5590
5591static int
5592intel_e09_1 ()
5593{
5594 /* e09' PTR e10 e09' */
5595 if (cur_token.code == T_PTR)
5596 {
5597 if (prev_token.code == T_BYTE)
5598 i.suffix = BYTE_MNEM_SUFFIX;
5599
5600 else if (prev_token.code == T_WORD)
5601 {
5602 if (intel_parser.got_a_float == 2) /* "fi..." */
5603 i.suffix = SHORT_MNEM_SUFFIX;
5604 else
5605 i.suffix = WORD_MNEM_SUFFIX;
5606 }
5607
5608 else if (prev_token.code == T_DWORD)
5609 {
5610 if (intel_parser.got_a_float == 1) /* "f..." */
5611 i.suffix = SHORT_MNEM_SUFFIX;
5612 else
5613 i.suffix = LONG_MNEM_SUFFIX;
5614 }
5615
5616 else if (prev_token.code == T_QWORD)
f16b83df
JH		 5617 {
5618 if (intel_parser.got_a_float == 1) /* "f..." */
5619 i.suffix = LONG_MNEM_SUFFIX;
5620 else
3e73aa7c 5621 i.suffix = QWORD_MNEM_SUFFIX;
f16b83df 5622 }
64a0c779
DN		 5623
5624 else if (prev_token.code == T_XWORD)
5625 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5626
5627 else
5628 {
5629 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5630 return 0;
5631 }
5632
5633 intel_match_token (T_PTR);
5634
5635 return (intel_e10 () && intel_e09_1 ());
5636 }
5637
5638 /* e09 : e10 e09' */
5639 else if (cur_token.code == ':')
5640 {
21d6c4af
DN		 5641 /* Mark as a memory operand only if it's not already known to be an
5642 offset expression. */
5643 if (intel_parser.op_modifier != OFFSET_FLAT)
5644 intel_parser.is_mem = 1;
64a0c779
DN		 5645
5646 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5647 }
5648
5649 /* e09' Empty */
5650 else
5651 return 1;
5652}
5653
5654/* e10 e11 e10'
5655
5656 e10' [ expr ] e10'
b77a7acd 5657 | Empty */
64a0c779
DN		 5658static int
5659intel_e10 ()
5660{
5661 return (intel_e11 () && intel_e10_1 ());
5662}
5663
5664static int
5665intel_e10_1 ()
5666{
5667 /* e10' [ expr ] e10' */
5668 if (cur_token.code == '[')
5669 {
5670 intel_match_token ('[');
21d6c4af
DN		 5671
5672 /* Mark as a memory operand only if it's not already known to be an
5673 offset expression. If it's an offset expression, we need to keep
5674 the brace in. */
5675 if (intel_parser.op_modifier != OFFSET_FLAT)
5676 intel_parser.is_mem = 1;
5677 else
5678 strcat (intel_parser.disp, "[");
4a1805b1 5679
64a0c779 5680 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5681 if (*intel_parser.disp != '\0'
5682 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5683 strcat (intel_parser.disp, "+");
5684
21d6c4af
DN		 5685 if (intel_expr () && intel_match_token (']'))
5686 {
5687 /* Preserve brackets when the operand is an offset expression. */
5688 if (intel_parser.op_modifier == OFFSET_FLAT)
5689 strcat (intel_parser.disp, "]");
5690
5691 return intel_e10_1 ();
5692 }
5693 else
5694 return 0;
64a0c779
DN		 5695 }
5696
5697 /* e10' Empty */
5698 else
5699 return 1;
5700}
5701
64a0c779 5702/* e11 ( expr )
b77a7acd 5703 | [ expr ]
64a0c779
DN		 5704 | BYTE
5705 | WORD
5706 | DWORD
5707 | QWORD
5708 | XWORD
4a1805b1 5709 | $
64a0c779
DN		 5710 | .
5711 | register
5712 | id
5713 | constant */
5714static int
5715intel_e11 ()
5716{
5717 /* e11 ( expr ) */
5718 if (cur_token.code == '(')
5719 {
5720 intel_match_token ('(');
5721 strcat (intel_parser.disp, "(");
5722
5723 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 5724 {
5725 strcat (intel_parser.disp, ")");
5726 return 1;
5727 }
64a0c779
DN		 5728 else
5729 return 0;
5730 }
5731
5732 /* e11 [ expr ] */
5733 else if (cur_token.code == '[')
5734 {
5735 intel_match_token ('[');
21d6c4af
DN		 5736
5737 /* Mark as a memory operand only if it's not already known to be an
5738 offset expression. If it's an offset expression, we need to keep
5739 the brace in. */
5740 if (intel_parser.op_modifier != OFFSET_FLAT)
5741 intel_parser.is_mem = 1;
5742 else
5743 strcat (intel_parser.disp, "[");
4a1805b1 5744
64a0c779
DN		 5745 /* Operands for jump/call inside brackets denote absolute addresses. */
5746 if (current_templates->start->opcode_modifier & Jump
5747 || current_templates->start->opcode_modifier & JumpDword
5748 || current_templates->start->opcode_modifier & JumpByte
5749 || current_templates->start->opcode_modifier & JumpInterSegment)
5750 i.types[this_operand] |= JumpAbsolute;
5751
5752 /* Add a '+' to the displacement string if necessary. */
21d6c4af
DN		 5753 if (*intel_parser.disp != '\0'
5754 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
64a0c779
DN		 5755 strcat (intel_parser.disp, "+");
5756
21d6c4af
DN		 5757 if (intel_expr () && intel_match_token (']'))
5758 {
5759 /* Preserve brackets when the operand is an offset expression. */
5760 if (intel_parser.op_modifier == OFFSET_FLAT)
5761 strcat (intel_parser.disp, "]");
5762
5763 return 1;
5764 }
5765 else
5766 return 0;
64a0c779
DN		 5767 }
5768
4a1805b1 5769 /* e11 BYTE
64a0c779
DN		 5770 | WORD
5771 | DWORD
5772 | QWORD
5773 | XWORD */
5774 else if (cur_token.code == T_BYTE
5775 || cur_token.code == T_WORD
5776 || cur_token.code == T_DWORD
5777 || cur_token.code == T_QWORD
5778 || cur_token.code == T_XWORD)
5779 {
5780 intel_match_token (cur_token.code);
5781
5782 return 1;
5783 }
5784
5785 /* e11 $
5786 | . */
5787 else if (cur_token.code == '$' || cur_token.code == '.')
5788 {
5789 strcat (intel_parser.disp, cur_token.str);
5790 intel_match_token (cur_token.code);
21d6c4af
DN		 5791
5792 /* Mark as a memory operand only if it's not already known to be an
5793 offset expression. */
5794 if (intel_parser.op_modifier != OFFSET_FLAT)
5795 intel_parser.is_mem = 1;
64a0c779
DN		 5796
5797 return 1;
5798 }
5799
5800 /* e11 register */
5801 else if (cur_token.code == T_REG)
5802 {
5803 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5804
5805 intel_match_token (T_REG);
5806
5807 /* Check for segment change. */
5808 if (cur_token.code == ':')
5809 {
5810 if (reg->reg_type & (SReg2 | SReg3))
5811 {
5812 switch (reg->reg_num)
5813 {
5814 case 0:
5815 i.seg[i.mem_operands] = &es;
5816 break;
5817 case 1:
5818 i.seg[i.mem_operands] = &cs;
5819 break;
5820 case 2:
5821 i.seg[i.mem_operands] = &ss;
5822 break;
5823 case 3:
5824 i.seg[i.mem_operands] = &ds;
5825 break;
5826 case 4:
5827 i.seg[i.mem_operands] = &fs;
5828 break;
5829 case 5:
5830 i.seg[i.mem_operands] = &gs;
5831 break;
5832 }
5833 }
5834 else
5835 {
5836 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5837 return 0;
5838 }
5839 }
5840
5841 /* Not a segment register. Check for register scaling. */
5842 else if (cur_token.code == '*')
5843 {
5844 if (!intel_parser.is_mem)
5845 {
5846 as_bad (_("Register scaling only allowed in memory operands."));
5847 return 0;
5848 }
5849
4a1805b1 5850 /* What follows must be a valid scale. */
64a0c779
DN		 5851 if (intel_match_token ('*')
5852 && strchr ("01248", *cur_token.str))
5853 {
5854 i.index_reg = reg;
5855 i.types[this_operand] |= BaseIndex;
5856
5857 /* Set the scale after setting the register (otherwise,
5858 i386_scale will complain) */
5859 i386_scale (cur_token.str);
5860 intel_match_token (T_CONST);
5861 }
5862 else
5863 {
5864 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5865 cur_token.str);
5866 return 0;
5867 }
5868 }
5869
5870 /* No scaling. If this is a memory operand, the register is either a
5871 base register (first occurrence) or an index register (second
5872 occurrence). */
5873 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5874 {
5875 if (i.base_reg && i.index_reg)
5876 {
5877 as_bad (_("Too many register references in memory operand.\n"));
5878 return 0;
5879 }
5880
5881 if (i.base_reg == NULL)
5882 i.base_reg = reg;
5883 else
5884 i.index_reg = reg;
5885
5886 i.types[this_operand] |= BaseIndex;
5887 }
5888
5889 /* Offset modifier. Add the register to the displacement string to be
5890 parsed as an immediate expression after we're done. */
5891 else if (intel_parser.op_modifier == OFFSET_FLAT)
5892 strcat (intel_parser.disp, reg->reg_name);
4a1805b1 5893
64a0c779
DN		 5894 /* It's neither base nor index nor offset. */
5895 else
5896 {
5897 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5898 i.op[this_operand].regs = reg;
5899 i.reg_operands++;
5900 }
5901
5902 /* Since registers are not part of the displacement string (except
5903 when we're parsing offset operands), we may need to remove any
5904 preceding '+' from the displacement string. */
5905 if (*intel_parser.disp != '\0'
5906 && intel_parser.op_modifier != OFFSET_FLAT)
5907 {
5908 char *s = intel_parser.disp;
5909 s += strlen (s) - 1;
5910 if (*s == '+')
5911 *s = '\0';
5912 }
5913
5914 return 1;
5915 }
4a1805b1 5916
64a0c779
DN		 5917 /* e11 id */
5918 else if (cur_token.code == T_ID)
5919 {
5920 /* Add the identifier to the displacement string. */
5921 strcat (intel_parser.disp, cur_token.str);
5922 intel_match_token (T_ID);
5923
5924 /* The identifier represents a memory reference only if it's not
5925 preceded by an offset modifier. */
21d6c4af 5926 if (intel_parser.op_modifier != OFFSET_FLAT)
64a0c779
DN		 5927 intel_parser.is_mem = 1;
5928
5929 return 1;
5930 }
5931
5932 /* e11 constant */
5933 else if (cur_token.code == T_CONST
e5cb08ac 5934 || cur_token.code == '-'
64a0c779
DN		 5935 || cur_token.code == '+')
5936 {
5937 char *save_str;
5938
5939 /* Allow constants that start with `+' or `-'. */
5940 if (cur_token.code == '-' || cur_token.code == '+')
5941 {
5942 strcat (intel_parser.disp, cur_token.str);
5943 intel_match_token (cur_token.code);
5944 if (cur_token.code != T_CONST)
5945 {
5946 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5947 cur_token.str);
5948 return 0;
5949 }
5950 }
5951
e5cb08ac 5952 save_str = (char *) malloc (strlen (cur_token.str) + 1);
64a0c779 5953 if (save_str == NULL)
bc805888 5954 abort ();
64a0c779
DN		 5955 strcpy (save_str, cur_token.str);
5956
5957 /* Get the next token to check for register scaling. */
5958 intel_match_token (cur_token.code);
5959
5960 /* Check if this constant is a scaling factor for an index register. */
5961 if (cur_token.code == '*')
5962 {
5963 if (intel_match_token ('*') && cur_token.code == T_REG)
5964 {
5965 if (!intel_parser.is_mem)
5966 {
5967 as_bad (_("Register scaling only allowed in memory operands."));
5968 return 0;
5969 }
5970
4a1805b1 5971 /* The constant is followed by `* reg', so it must be
64a0c779
DN		 5972 a valid scale. */
5973 if (strchr ("01248", *save_str))
5974 {
5975 i.index_reg = cur_token.reg;
5976 i.types[this_operand] |= BaseIndex;
5977
5978 /* Set the scale after setting the register (otherwise,
5979 i386_scale will complain) */
5980 i386_scale (save_str);
5981 intel_match_token (T_REG);
5982
5983 /* Since registers are not part of the displacement
5984 string, we may need to remove any preceding '+' from
5985 the displacement string. */
5986 if (*intel_parser.disp != '\0')
5987 {
5988 char *s = intel_parser.disp;
5989 s += strlen (s) - 1;
5990 if (*s == '+')
5991 *s = '\0';
5992 }
5993
5994 free (save_str);
5995
5996 return 1;
5997 }
5998 else
5999 return 0;
6000 }
6001
6002 /* The constant was not used for register scaling. Since we have
6003 already consumed the token following `*' we now need to put it
6004 back in the stream. */
6005 else
6006 intel_putback_token ();
6007 }
6008
6009 /* Add the constant to the displacement string. */
6010 strcat (intel_parser.disp, save_str);
6011 free (save_str);
6012
6013 return 1;
6014 }
6015
64a0c779
DN		 6016 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6017 return 0;
6018}
6019
64a0c779
DN		 6020/* Match the given token against cur_token. If they match, read the next
6021 token from the operand string. */
6022static int
6023intel_match_token (code)
e5cb08ac 6024 int code;
64a0c779
DN		 6025{
6026 if (cur_token.code == code)
6027 {
6028 intel_get_token ();
6029 return 1;
6030 }
6031 else
6032 {
6033 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6034 return 0;
6035 }
6036}
6037
64a0c779
DN		 6038/* Read a new token from intel_parser.op_string and store it in cur_token. */
6039static void
6040intel_get_token ()
6041{
6042 char *end_op;
6043 const reg_entry *reg;
6044 struct intel_token new_token;
6045
6046 new_token.code = T_NIL;
6047 new_token.reg = NULL;
6048 new_token.str = NULL;
6049
4a1805b1 6050 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6051 cur_token to prev_token. */
6052 if (prev_token.str)
6053 free (prev_token.str);
6054
6055 prev_token = cur_token;
6056
6057 /* Skip whitespace. */
6058 while (is_space_char (*intel_parser.op_string))
6059 intel_parser.op_string++;
6060
6061 /* Return an empty token if we find nothing else on the line. */
6062 if (*intel_parser.op_string == '\0')
6063 {
6064 cur_token = new_token;
6065 return;
6066 }
6067
6068 /* The new token cannot be larger than the remainder of the operand
6069 string. */
e5cb08ac 6070 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
64a0c779 6071 if (new_token.str == NULL)
bc805888 6072 abort ();
64a0c779
DN		 6073 new_token.str[0] = '\0';
6074
6075 if (strchr ("0123456789", *intel_parser.op_string))
6076 {
6077 char *p = new_token.str;
6078 char *q = intel_parser.op_string;
6079 new_token.code = T_CONST;
6080
6081 /* Allow any kind of identifier char to encompass floating point and
6082 hexadecimal numbers. */
6083 while (is_identifier_char (*q))
6084 *p++ = *q++;
6085 *p = '\0';
6086
6087 /* Recognize special symbol names [0-9][bf]. */
6088 if (strlen (intel_parser.op_string) == 2
4a1805b1 6089 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6090 || intel_parser.op_string[1] == 'f'))
6091 new_token.code = T_ID;
6092 }
6093
6094 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6095 {
6096 new_token.code = *intel_parser.op_string;
6097 new_token.str[0] = *intel_parser.op_string;
6098 new_token.str[1] = '\0';
6099 }
6100
6101 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6102 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6103 {
6104 new_token.code = T_REG;
6105 new_token.reg = reg;
6106
6107 if (*intel_parser.op_string == REGISTER_PREFIX)
6108 {
6109 new_token.str[0] = REGISTER_PREFIX;
6110 new_token.str[1] = '\0';
6111 }
6112
6113 strcat (new_token.str, reg->reg_name);
6114 }
6115
6116 else if (is_identifier_char (*intel_parser.op_string))
6117 {
6118 char *p = new_token.str;
6119 char *q = intel_parser.op_string;
6120
6121 /* A '.' or '$' followed by an identifier char is an identifier.
6122 Otherwise, it's operator '.' followed by an expression. */
6123 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6124 {
6125 new_token.code = *q;
6126 new_token.str[0] = *q;
6127 new_token.str[1] = '\0';
6128 }
6129 else
6130 {
6131 while (is_identifier_char (*q) || *q == '@')
6132 *p++ = *q++;
6133 *p = '\0';
6134
6135 if (strcasecmp (new_token.str, "BYTE") == 0)
6136 new_token.code = T_BYTE;
6137
6138 else if (strcasecmp (new_token.str, "WORD") == 0)
6139 new_token.code = T_WORD;
6140
6141 else if (strcasecmp (new_token.str, "DWORD") == 0)
6142 new_token.code = T_DWORD;
6143
6144 else if (strcasecmp (new_token.str, "QWORD") == 0)
6145 new_token.code = T_QWORD;
6146
6147 else if (strcasecmp (new_token.str, "XWORD") == 0)
6148 new_token.code = T_XWORD;
6149
6150 else if (strcasecmp (new_token.str, "PTR") == 0)
6151 new_token.code = T_PTR;
6152
6153 else if (strcasecmp (new_token.str, "SHORT") == 0)
6154 new_token.code = T_SHORT;
6155
6156 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6157 {
6158 new_token.code = T_OFFSET;
6159
6160 /* ??? This is not mentioned in the MASM grammar but gcc
6161 makes use of it with -mintel-syntax. OFFSET may be
6162 followed by FLAT: */
6163 if (strncasecmp (q, " FLAT:", 6) == 0)
6164 strcat (new_token.str, " FLAT:");
6165 }
6166
6167 /* ??? This is not mentioned in the MASM grammar. */
6168 else if (strcasecmp (new_token.str, "FLAT") == 0)
6169 new_token.code = T_OFFSET;
6170
6171 else
6172 new_token.code = T_ID;
6173 }
6174 }
6175
6176 else
6177 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6178
6179 intel_parser.op_string += strlen (new_token.str);
6180 cur_token = new_token;
6181}
6182
64a0c779
DN		 6183/* Put cur_token back into the token stream and make cur_token point to
6184 prev_token. */
6185static void
6186intel_putback_token ()
6187{
6188 intel_parser.op_string -= strlen (cur_token.str);
6189 free (cur_token.str);
6190 cur_token = prev_token;
4a1805b1 6191
64a0c779
DN		 6192 /* Forget prev_token. */
6193 prev_token.code = T_NIL;
6194 prev_token.reg = NULL;
6195 prev_token.str = NULL;
6196}
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