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[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
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252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
aef6203b 3 2000, 2001, 2002, 2003, 2004, 2005
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
29b0f896
AM		 83static char *output_invalid PARAMS ((int c));
84static int i386_operand PARAMS ((char *operand_string));
85static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
86static const reg_entry *parse_register PARAMS ((char *reg_string,
87 char **end_op));
88static char *parse_insn PARAMS ((char *, char *));
89static char *parse_operands PARAMS ((char *, const char *));
90static void swap_operands PARAMS ((void));
91static void optimize_imm PARAMS ((void));
92static void optimize_disp PARAMS ((void));
93static int match_template PARAMS ((void));
94static int check_string PARAMS ((void));
95static int process_suffix PARAMS ((void));
96static int check_byte_reg PARAMS ((void));
97static int check_long_reg PARAMS ((void));
98static int check_qword_reg PARAMS ((void));
99static int check_word_reg PARAMS ((void));
100static int finalize_imm PARAMS ((void));
101static int process_operands PARAMS ((void));
102static const seg_entry *build_modrm_byte PARAMS ((void));
103static void output_insn PARAMS ((void));
104static void output_branch PARAMS ((void));
105static void output_jump PARAMS ((void));
106static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 107static void output_imm PARAMS ((fragS *insn_start_frag,
108 offsetT insn_start_off));
109static void output_disp PARAMS ((fragS *insn_start_frag,
110 offsetT insn_start_off));
29b0f896
AM		 111#ifndef I386COFF
112static void s_bss PARAMS ((int));
252b5132
RH		 113#endif
114
a847613f 115static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 116
252b5132 117/* 'md_assemble ()' gathers together information and puts it into a
47926f60 118 i386_insn. */
252b5132 119
520dc8e8
AM		 120union i386_op
121 {
122 expressionS *disps;
123 expressionS *imms;
124 const reg_entry *regs;
125 };
126
252b5132
RH		 127struct _i386_insn
128 {
47926f60 129 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 130 template tm;
131
132 /* SUFFIX holds the instruction mnemonic suffix if given.
133 (e.g. 'l' for 'movl') */
134 char suffix;
135
47926f60 136 /* OPERANDS gives the number of given operands. */
252b5132
RH		 137 unsigned int operands;
138
139 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
140 of given register, displacement, memory operands and immediate
47926f60 141 operands. */
252b5132
RH		 142 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
143
144 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 145 use OP[i] for the corresponding operand. */
252b5132
RH		 146 unsigned int types[MAX_OPERANDS];
147
520dc8e8
AM		 148 /* Displacement expression, immediate expression, or register for each
149 operand. */
150 union i386_op op[MAX_OPERANDS];
252b5132 151
3e73aa7c
JH		 152 /* Flags for operands. */
153 unsigned int flags[MAX_OPERANDS];
154#define Operand_PCrel 1
155
252b5132 156 /* Relocation type for operand */
f86103b7 157 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 158
252b5132
RH		 159 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
160 the base index byte below. */
161 const reg_entry *base_reg;
162 const reg_entry *index_reg;
163 unsigned int log2_scale_factor;
164
165 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 166 explicit segment overrides are given. */
ce8a8b2f 167 const seg_entry *seg[2];
252b5132
RH		 168
169 /* PREFIX holds all the given prefix opcodes (usually null).
170 PREFIXES is the number of prefix opcodes. */
171 unsigned int prefixes;
172 unsigned char prefix[MAX_PREFIXES];
173
174 /* RM and SIB are the modrm byte and the sib byte where the
175 addressing modes of this insn are encoded. */
176
177 modrm_byte rm;
3e73aa7c 178 rex_byte rex;
252b5132
RH		 179 sib_byte sib;
180 };
181
182typedef struct _i386_insn i386_insn;
183
184/* List of chars besides those in app.c:symbol_chars that can start an
185 operand. Used to prevent the scrubber eating vital white-space. */
32137342 186const char extra_symbol_chars[] = "*%-(["
252b5132 187#ifdef LEX_AT
32137342
NC		 188 "@"
189#endif
190#ifdef LEX_QM
191 "?"
252b5132 192#endif
32137342 193 ;
252b5132 194
29b0f896
AM		 195#if (defined (TE_I386AIX) \
196 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
197 && !defined (TE_LINUX) \
32137342 198 && !defined (TE_NETWARE) \
29b0f896
AM		 199 && !defined (TE_FreeBSD) \
200 && !defined (TE_NetBSD)))
252b5132 201/* This array holds the chars that always start a comment. If the
ce8a8b2f 202 pre-processor is disabled, these aren't very useful. */
252b5132
RH		 203const char comment_chars[] = "#/";
204#define PREFIX_SEPARATOR '\\'
252b5132
RH		 205
206/* This array holds the chars that only start a comment at the beginning of
207 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 208 .line and .file directives will appear in the pre-processed output.
209 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 210 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 211 #NO_APP at the beginning of its output.
212 Also note that comments started like this one will always work if
252b5132 213 '/' isn't otherwise defined. */
0d9f6d04 214const char line_comment_chars[] = "#";
29b0f896 215
252b5132 216#else
29b0f896
AM		 217/* Putting '/' here makes it impossible to use the divide operator.
218 However, we need it for compatibility with SVR4 systems. */
219const char comment_chars[] = "#";
220#define PREFIX_SEPARATOR '/'
221
0d9f6d04 222const char line_comment_chars[] = "/#";
252b5132
RH		 223#endif
224
63a0b638 225const char line_separator_chars[] = ";";
252b5132 226
ce8a8b2f
AM		 227/* Chars that can be used to separate mant from exp in floating point
228 nums. */
252b5132
RH		 229const char EXP_CHARS[] = "eE";
230
ce8a8b2f
AM		 231/* Chars that mean this number is a floating point constant
232 As in 0f12.456
233 or 0d1.2345e12. */
252b5132
RH		 234const char FLT_CHARS[] = "fFdDxX";
235
ce8a8b2f 236/* Tables for lexical analysis. */
252b5132
RH		 237static char mnemonic_chars[256];
238static char register_chars[256];
239static char operand_chars[256];
240static char identifier_chars[256];
241static char digit_chars[256];
242
ce8a8b2f 243/* Lexical macros. */
252b5132
RH		 244#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
245#define is_operand_char(x) (operand_chars[(unsigned char) x])
246#define is_register_char(x) (register_chars[(unsigned char) x])
247#define is_space_char(x) ((x) == ' ')
248#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
249#define is_digit_char(x) (digit_chars[(unsigned char) x])
250
0234cb7c 251/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 252static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
253
254/* md_assemble() always leaves the strings it's passed unaltered. To
255 effect this we maintain a stack of saved characters that we've smashed
256 with '\0's (indicating end of strings for various sub-fields of the
47926f60 257 assembler instruction). */
252b5132 258static char save_stack[32];
ce8a8b2f 259static char *save_stack_p;
252b5132
RH		 260#define END_STRING_AND_SAVE(s) \
261 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
262#define RESTORE_END_STRING(s) \
263 do { *(s) = *--save_stack_p; } while (0)
264
47926f60 265/* The instruction we're assembling. */
252b5132
RH		 266static i386_insn i;
267
268/* Possible templates for current insn. */
269static const templates *current_templates;
270
47926f60 271/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 272static expressionS disp_expressions[2], im_expressions[2];
273
47926f60
KH		 274/* Current operand we are working on. */
275static int this_operand;
252b5132 276
3e73aa7c
JH		 277/* We support four different modes. FLAG_CODE variable is used to distinguish
278 these. */
279
280enum flag_code {
281 CODE_32BIT,
282 CODE_16BIT,
283 CODE_64BIT };
f3c180ae 284#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 285
286static enum flag_code flag_code;
287static int use_rela_relocations = 0;
288
289/* The names used to print error messages. */
b77a7acd 290static const char *flag_code_names[] =
3e73aa7c
JH		 291 {
292 "32",
293 "16",
294 "64"
295 };
252b5132 296
47926f60
KH		 297/* 1 for intel syntax,
298 0 if att syntax. */
299static int intel_syntax = 0;
252b5132 300
47926f60
KH		 301/* 1 if register prefix % not required. */
302static int allow_naked_reg = 0;
252b5132 303
47926f60
KH		 304/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
305 leave, push, and pop instructions so that gcc has the same stack
306 frame as in 32 bit mode. */
307static char stackop_size = '\0';
eecb386c 308
12b55ccc
L		 309/* Non-zero to optimize code alignment. */
310int optimize_align_code = 1;
311
47926f60
KH		 312/* Non-zero to quieten some warnings. */
313static int quiet_warnings = 0;
a38cf1db 314
47926f60
KH		 315/* CPU name. */
316static const char *cpu_arch_name = NULL;
5c6af06e 317static const char *cpu_sub_arch_name = NULL;
a38cf1db 318
47926f60 319/* CPU feature flags. */
29b0f896 320static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 321
fddf5b5b
AM		 322/* If set, conditional jumps are not automatically promoted to handle
323 larger than a byte offset. */
324static unsigned int no_cond_jump_promotion = 0;
325
29b0f896 326/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 327static symbolS *GOT_symbol;
29b0f896 328
a4447b93
RH		 329/* The dwarf2 return column, adjusted for 32 or 64 bit. */
330unsigned int x86_dwarf2_return_column;
331
332/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
333int x86_cie_data_alignment;
334
252b5132 335/* Interface to relax_segment.
fddf5b5b
AM		 336 There are 3 major relax states for 386 jump insns because the
337 different types of jumps add different sizes to frags when we're
338 figuring out what sort of jump to choose to reach a given label. */
252b5132 339
47926f60 340/* Types. */
93c2a809
AM		 341#define UNCOND_JUMP 0
342#define COND_JUMP 1
343#define COND_JUMP86 2
fddf5b5b 344
47926f60 345/* Sizes. */
252b5132
RH		 346#define CODE16 1
347#define SMALL 0
29b0f896 348#define SMALL16 (SMALL | CODE16)
252b5132 349#define BIG 2
29b0f896 350#define BIG16 (BIG | CODE16)
252b5132
RH		 351
352#ifndef INLINE
353#ifdef __GNUC__
354#define INLINE __inline__
355#else
356#define INLINE
357#endif
358#endif
359
fddf5b5b
AM		 360#define ENCODE_RELAX_STATE(type, size) \
361 ((relax_substateT) (((type) << 2) | (size)))
362#define TYPE_FROM_RELAX_STATE(s) \
363 ((s) >> 2)
364#define DISP_SIZE_FROM_RELAX_STATE(s) \
365 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 366
367/* This table is used by relax_frag to promote short jumps to long
368 ones where necessary. SMALL (short) jumps may be promoted to BIG
369 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
370 don't allow a short jump in a 32 bit code segment to be promoted to
371 a 16 bit offset jump because it's slower (requires data size
372 prefix), and doesn't work, unless the destination is in the bottom
373 64k of the code segment (The top 16 bits of eip are zeroed). */
374
375const relax_typeS md_relax_table[] =
376{
24eab124
AM		 377 /* The fields are:
378 1) most positive reach of this state,
379 2) most negative reach of this state,
93c2a809 380 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 381 4) which index into the table to try if we can't fit into this one. */
252b5132 382
fddf5b5b 383 /* UNCOND_JUMP states. */
93c2a809
AM		 384 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
386 /* dword jmp adds 4 bytes to frag:
387 0 extra opcode bytes, 4 displacement bytes. */
252b5132 388 {0, 0, 4, 0},
93c2a809
AM		 389 /* word jmp adds 2 byte2 to frag:
390 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 391 {0, 0, 2, 0},
392
93c2a809
AM		 393 /* COND_JUMP states. */
394 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
396 /* dword conditionals adds 5 bytes to frag:
397 1 extra opcode byte, 4 displacement bytes. */
398 {0, 0, 5, 0},
fddf5b5b 399 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 400 1 extra opcode byte, 2 displacement bytes. */
401 {0, 0, 3, 0},
402
403 /* COND_JUMP86 states. */
404 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
405 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
406 /* dword conditionals adds 5 bytes to frag:
407 1 extra opcode byte, 4 displacement bytes. */
408 {0, 0, 5, 0},
409 /* word conditionals add 4 bytes to frag:
410 1 displacement byte and a 3 byte long branch insn. */
411 {0, 0, 4, 0}
252b5132
RH		 412};
413
e413e4e9
AM		 414static const arch_entry cpu_arch[] = {
415 {"i8086", Cpu086 },
416 {"i186", Cpu086|Cpu186 },
417 {"i286", Cpu086|Cpu186|Cpu286 },
418 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
419 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
5c6af06e
JB		 420 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
421 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
422 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586 },
423 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 },
424 {"pentiumii", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX },
425 {"pentiumiii",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2|CpuSSE },
426 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
427 {"prescott", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuPNI },
428 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX },
429 {"k6_2", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
430 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
431 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
30123838 432 {"opteron", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2 },
5c6af06e
JB		 433 {".mmx", CpuMMX },
434 {".sse", CpuMMX|CpuMMX2|CpuSSE },
435 {".sse2", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2 },
bf50992e 436 {".sse3", CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3 },
5c6af06e
JB		 437 {".3dnow", CpuMMX|Cpu3dnow },
438 {".3dnowa", CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA },
439 {".padlock", CpuPadLock },
30123838
JB		 440 {".pacifica", CpuSVME },
441 {".svme", CpuSVME },
e413e4e9
AM		 442 {NULL, 0 }
443};
444
29b0f896
AM		 445const pseudo_typeS md_pseudo_table[] =
446{
447#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
448 {"align", s_align_bytes, 0},
449#else
450 {"align", s_align_ptwo, 0},
451#endif
452 {"arch", set_cpu_arch, 0},
453#ifndef I386COFF
454 {"bss", s_bss, 0},
455#endif
456 {"ffloat", float_cons, 'f'},
457 {"dfloat", float_cons, 'd'},
458 {"tfloat", float_cons, 'x'},
459 {"value", cons, 2},
460 {"noopt", s_ignore, 0},
461 {"optim", s_ignore, 0},
462 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
463 {"code16", set_code_flag, CODE_16BIT},
464 {"code32", set_code_flag, CODE_32BIT},
465 {"code64", set_code_flag, CODE_64BIT},
466 {"intel_syntax", set_intel_syntax, 1},
467 {"att_syntax", set_intel_syntax, 0},
c6682705 468 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
29b0f896 469 {"loc", dwarf2_directive_loc, 0},
6482c264
NC		 470#ifdef TE_PE
471 {"secrel32", pe_directive_secrel, 0},
472#endif
29b0f896
AM		 473 {0, 0, 0}
474};
475
476/* For interface with expression (). */
477extern char *input_line_pointer;
478
479/* Hash table for instruction mnemonic lookup. */
480static struct hash_control *op_hash;
481
482/* Hash table for register lookup. */
483static struct hash_control *reg_hash;
484\f
252b5132
RH		 485void
486i386_align_code (fragP, count)
487 fragS *fragP;
488 int count;
489{
ce8a8b2f
AM		 490 /* Various efficient no-op patterns for aligning code labels.
491 Note: Don't try to assemble the instructions in the comments.
492 0L and 0w are not legal. */
252b5132
RH		 493 static const char f32_1[] =
494 {0x90}; /* nop */
495 static const char f32_2[] =
496 {0x89,0xf6}; /* movl %esi,%esi */
497 static const char f32_3[] =
498 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
499 static const char f32_4[] =
500 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
501 static const char f32_5[] =
502 {0x90, /* nop */
503 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
504 static const char f32_6[] =
505 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
506 static const char f32_7[] =
507 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
508 static const char f32_8[] =
509 {0x90, /* nop */
510 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
511 static const char f32_9[] =
512 {0x89,0xf6, /* movl %esi,%esi */
513 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
514 static const char f32_10[] =
515 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
516 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
517 static const char f32_11[] =
518 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
519 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
520 static const char f32_12[] =
521 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
522 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
523 static const char f32_13[] =
524 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
525 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
526 static const char f32_14[] =
527 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
528 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
529 static const char f32_15[] =
530 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
531 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 532 static const char f16_3[] =
533 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 534 static const char f16_4[] =
535 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
536 static const char f16_5[] =
537 {0x90, /* nop */
538 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
539 static const char f16_6[] =
540 {0x89,0xf6, /* mov %si,%si */
541 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
542 static const char f16_7[] =
543 {0x8d,0x74,0x00, /* lea 0(%si),%si */
544 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
545 static const char f16_8[] =
546 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
547 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
548 static const char *const f32_patt[] = {
549 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
550 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
551 };
552 static const char *const f16_patt[] = {
c3332e24 553 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 554 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
555 };
556
33fef721
JH		 557 if (count <= 0 || count > 15)
558 return;
3e73aa7c 559
33fef721
JH		 560 /* The recommended way to pad 64bit code is to use NOPs preceded by
561 maximally four 0x66 prefixes. Balance the size of nops. */
562 if (flag_code == CODE_64BIT)
252b5132 563 {
33fef721
JH		 564 int i;
565 int nnops = (count + 3) / 4;
566 int len = count / nnops;
567 int remains = count - nnops * len;
568 int pos = 0;
569
570 for (i = 0; i < remains; i++)
252b5132 571 {
33fef721
JH		 572 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
573 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
574 pos += len + 1;
575 }
576 for (; i < nnops; i++)
577 {
578 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
579 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
580 pos += len;
252b5132 581 }
252b5132 582 }
33fef721
JH		 583 else
584 if (flag_code == CODE_16BIT)
585 {
586 memcpy (fragP->fr_literal + fragP->fr_fix,
587 f16_patt[count - 1], count);
588 if (count > 8)
589 /* Adjust jump offset. */
590 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
591 }
592 else
593 memcpy (fragP->fr_literal + fragP->fr_fix,
594 f32_patt[count - 1], count);
595 fragP->fr_var = count;
252b5132
RH		 596}
597
252b5132
RH		 598static INLINE unsigned int
599mode_from_disp_size (t)
600 unsigned int t;
601{
3e73aa7c 602 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 603}
604
605static INLINE int
606fits_in_signed_byte (num)
847f7ad4 607 offsetT num;
252b5132
RH		 608{
609 return (num >= -128) && (num <= 127);
47926f60 610}
252b5132
RH		 611
612static INLINE int
613fits_in_unsigned_byte (num)
847f7ad4 614 offsetT num;
252b5132
RH		 615{
616 return (num & 0xff) == num;
47926f60 617}
252b5132
RH		 618
619static INLINE int
620fits_in_unsigned_word (num)
847f7ad4 621 offsetT num;
252b5132
RH		 622{
623 return (num & 0xffff) == num;
47926f60 624}
252b5132
RH		 625
626static INLINE int
627fits_in_signed_word (num)
847f7ad4 628 offsetT num;
252b5132
RH		 629{
630 return (-32768 <= num) && (num <= 32767);
47926f60 631}
3e73aa7c
JH		 632static INLINE int
633fits_in_signed_long (num)
634 offsetT num ATTRIBUTE_UNUSED;
635{
636#ifndef BFD64
637 return 1;
638#else
639 return (!(((offsetT) -1 << 31) & num)
640 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
641#endif
642} /* fits_in_signed_long() */
643static INLINE int
644fits_in_unsigned_long (num)
645 offsetT num ATTRIBUTE_UNUSED;
646{
647#ifndef BFD64
648 return 1;
649#else
650 return (num & (((offsetT) 2 << 31) - 1)) == num;
651#endif
652} /* fits_in_unsigned_long() */
252b5132
RH		 653
654static int
655smallest_imm_type (num)
847f7ad4 656 offsetT num;
252b5132 657{
a847613f 658 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 659 {
660 /* This code is disabled on the 486 because all the Imm1 forms
661 in the opcode table are slower on the i486. They're the
662 versions with the implicitly specified single-position
663 displacement, which has another syntax if you really want to
664 use that form. */
665 if (num == 1)
3e73aa7c 666 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 667 }
252b5132 668 return (fits_in_signed_byte (num)
3e73aa7c 669 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 670 : fits_in_unsigned_byte (num)
3e73aa7c 671 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 672 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 673 ? (Imm16 | Imm32 | Imm32S | Imm64)
674 : fits_in_signed_long (num)
675 ? (Imm32 | Imm32S | Imm64)
676 : fits_in_unsigned_long (num)
677 ? (Imm32 | Imm64)
678 : Imm64);
47926f60 679}
252b5132 680
847f7ad4
AM		 681static offsetT
682offset_in_range (val, size)
683 offsetT val;
684 int size;
685{
508866be 686 addressT mask;
ba2adb93 687
847f7ad4
AM		 688 switch (size)
689 {
508866be
L		 690 case 1: mask = ((addressT) 1 << 8) - 1; break;
691 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 692 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 693#ifdef BFD64
694 case 8: mask = ((addressT) 2 << 63) - 1; break;
695#endif
47926f60 696 default: abort ();
847f7ad4
AM		 697 }
698
ba2adb93 699 /* If BFD64, sign extend val. */
3e73aa7c
JH		 700 if (!use_rela_relocations)
701 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
702 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 703
47926f60 704 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 705 {
706 char buf1[40], buf2[40];
707
708 sprint_value (buf1, val);
709 sprint_value (buf2, val & mask);
710 as_warn (_("%s shortened to %s"), buf1, buf2);
711 }
712 return val & mask;
713}
714
252b5132
RH		 715/* Returns 0 if attempting to add a prefix where one from the same
716 class already exists, 1 if non rep/repne added, 2 if rep/repne
717 added. */
718static int
719add_prefix (prefix)
720 unsigned int prefix;
721{
722 int ret = 1;
723 int q;
724
29b0f896
AM		 725 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
726 && flag_code == CODE_64BIT)
3e73aa7c
JH		 727 q = REX_PREFIX;
728 else
729 switch (prefix)
730 {
731 default:
732 abort ();
733
734 case CS_PREFIX_OPCODE:
735 case DS_PREFIX_OPCODE:
736 case ES_PREFIX_OPCODE:
737 case FS_PREFIX_OPCODE:
738 case GS_PREFIX_OPCODE:
739 case SS_PREFIX_OPCODE:
740 q = SEG_PREFIX;
741 break;
252b5132 742
3e73aa7c
JH		 743 case REPNE_PREFIX_OPCODE:
744 case REPE_PREFIX_OPCODE:
745 ret = 2;
746 /* fall thru */
747 case LOCK_PREFIX_OPCODE:
748 q = LOCKREP_PREFIX;
749 break;
252b5132 750
3e73aa7c
JH		 751 case FWAIT_OPCODE:
752 q = WAIT_PREFIX;
753 break;
252b5132 754
3e73aa7c
JH		 755 case ADDR_PREFIX_OPCODE:
756 q = ADDR_PREFIX;
757 break;
252b5132 758
3e73aa7c
JH		 759 case DATA_PREFIX_OPCODE:
760 q = DATA_PREFIX;
761 break;
762 }
252b5132 763
29b0f896 764 if (i.prefix[q] != 0)
252b5132
RH		 765 {
766 as_bad (_("same type of prefix used twice"));
767 return 0;
768 }
769
770 i.prefixes += 1;
771 i.prefix[q] = prefix;
772 return ret;
773}
774
775static void
3e73aa7c 776set_code_flag (value)
e5cb08ac 777 int value;
eecb386c 778{
3e73aa7c
JH		 779 flag_code = value;
780 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
781 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
782 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
783 {
784 as_bad (_("64bit mode not supported on this CPU."));
785 }
786 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
787 {
788 as_bad (_("32bit mode not supported on this CPU."));
789 }
eecb386c
AM		 790 stackop_size = '\0';
791}
792
793static void
3e73aa7c
JH		 794set_16bit_gcc_code_flag (new_code_flag)
795 int new_code_flag;
252b5132 796{
3e73aa7c
JH		 797 flag_code = new_code_flag;
798 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
799 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 800 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 801}
802
803static void
804set_intel_syntax (syntax_flag)
eecb386c 805 int syntax_flag;
252b5132
RH		 806{
807 /* Find out if register prefixing is specified. */
808 int ask_naked_reg = 0;
809
810 SKIP_WHITESPACE ();
29b0f896 811 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 812 {
813 char *string = input_line_pointer;
814 int e = get_symbol_end ();
815
47926f60 816 if (strcmp (string, "prefix") == 0)
252b5132 817 ask_naked_reg = 1;
47926f60 818 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 819 ask_naked_reg = -1;
820 else
d0b47220 821 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 822 *input_line_pointer = e;
823 }
824 demand_empty_rest_of_line ();
c3332e24 825
252b5132
RH		 826 intel_syntax = syntax_flag;
827
828 if (ask_naked_reg == 0)
f86103b7
AM		 829 allow_naked_reg = (intel_syntax
830 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 831 else
832 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 833
834 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
835 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 836}
837
e413e4e9
AM		 838static void
839set_cpu_arch (dummy)
47926f60 840 int dummy ATTRIBUTE_UNUSED;
e413e4e9 841{
47926f60 842 SKIP_WHITESPACE ();
e413e4e9 843
29b0f896 844 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 845 {
846 char *string = input_line_pointer;
847 int e = get_symbol_end ();
848 int i;
849
850 for (i = 0; cpu_arch[i].name; i++)
851 {
852 if (strcmp (string, cpu_arch[i].name) == 0)
853 {
5c6af06e
JB		 854 if (*string != '.')
855 {
856 cpu_arch_name = cpu_arch[i].name;
857 cpu_sub_arch_name = NULL;
858 cpu_arch_flags = (cpu_arch[i].flags
859 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
860 break;
861 }
862 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
863 {
864 cpu_sub_arch_name = cpu_arch[i].name;
865 cpu_arch_flags |= cpu_arch[i].flags;
866 }
867 *input_line_pointer = e;
868 demand_empty_rest_of_line ();
869 return;
e413e4e9
AM		 870 }
871 }
872 if (!cpu_arch[i].name)
873 as_bad (_("no such architecture: `%s'"), string);
874
875 *input_line_pointer = e;
876 }
877 else
878 as_bad (_("missing cpu architecture"));
879
fddf5b5b
AM		 880 no_cond_jump_promotion = 0;
881 if (*input_line_pointer == ','
29b0f896 882 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 883 {
884 char *string = ++input_line_pointer;
885 int e = get_symbol_end ();
886
887 if (strcmp (string, "nojumps") == 0)
888 no_cond_jump_promotion = 1;
889 else if (strcmp (string, "jumps") == 0)
890 ;
891 else
892 as_bad (_("no such architecture modifier: `%s'"), string);
893
894 *input_line_pointer = e;
895 }
896
e413e4e9
AM		 897 demand_empty_rest_of_line ();
898}
899
b9d79e03
JH		 900unsigned long
901i386_mach ()
902{
903 if (!strcmp (default_arch, "x86_64"))
904 return bfd_mach_x86_64;
905 else if (!strcmp (default_arch, "i386"))
906 return bfd_mach_i386_i386;
907 else
908 as_fatal (_("Unknown architecture"));
909}
b9d79e03 910\f
252b5132
RH		 911void
912md_begin ()
913{
914 const char *hash_err;
915
47926f60 916 /* Initialize op_hash hash table. */
252b5132
RH		 917 op_hash = hash_new ();
918
919 {
29b0f896
AM		 920 const template *optab;
921 templates *core_optab;
252b5132 922
47926f60
KH		 923 /* Setup for loop. */
924 optab = i386_optab;
252b5132
RH		 925 core_optab = (templates *) xmalloc (sizeof (templates));
926 core_optab->start = optab;
927
928 while (1)
929 {
930 ++optab;
931 if (optab->name == NULL
932 || strcmp (optab->name, (optab - 1)->name) != 0)
933 {
934 /* different name --> ship out current template list;
47926f60 935 add to hash table; & begin anew. */
252b5132
RH		 936 core_optab->end = optab;
937 hash_err = hash_insert (op_hash,
938 (optab - 1)->name,
939 (PTR) core_optab);
940 if (hash_err)
941 {
252b5132
RH		 942 as_fatal (_("Internal Error: Can't hash %s: %s"),
943 (optab - 1)->name,
944 hash_err);
945 }
946 if (optab->name == NULL)
947 break;
948 core_optab = (templates *) xmalloc (sizeof (templates));
949 core_optab->start = optab;
950 }
951 }
952 }
953
47926f60 954 /* Initialize reg_hash hash table. */
252b5132
RH		 955 reg_hash = hash_new ();
956 {
29b0f896 957 const reg_entry *regtab;
252b5132
RH		 958
959 for (regtab = i386_regtab;
960 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
961 regtab++)
962 {
963 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
964 if (hash_err)
3e73aa7c
JH		 965 as_fatal (_("Internal Error: Can't hash %s: %s"),
966 regtab->reg_name,
967 hash_err);
252b5132
RH		 968 }
969 }
970
47926f60 971 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 972 {
29b0f896
AM		 973 int c;
974 char *p;
252b5132
RH		 975
976 for (c = 0; c < 256; c++)
977 {
3882b010 978 if (ISDIGIT (c))
252b5132
RH		 979 {
980 digit_chars[c] = c;
981 mnemonic_chars[c] = c;
982 register_chars[c] = c;
983 operand_chars[c] = c;
984 }
3882b010 985 else if (ISLOWER (c))
252b5132
RH		 986 {
987 mnemonic_chars[c] = c;
988 register_chars[c] = c;
989 operand_chars[c] = c;
990 }
3882b010 991 else if (ISUPPER (c))
252b5132 992 {
3882b010 993 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 994 register_chars[c] = mnemonic_chars[c];
995 operand_chars[c] = c;
996 }
997
3882b010 998 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 999 identifier_chars[c] = c;
1000 else if (c >= 128)
1001 {
1002 identifier_chars[c] = c;
1003 operand_chars[c] = c;
1004 }
1005 }
1006
1007#ifdef LEX_AT
1008 identifier_chars['@'] = '@';
32137342
NC		 1009#endif
1010#ifdef LEX_QM
1011 identifier_chars['?'] = '?';
1012 operand_chars['?'] = '?';
252b5132 1013#endif
252b5132 1014 digit_chars['-'] = '-';
791fe849 1015 mnemonic_chars['-'] = '-';
252b5132
RH		 1016 identifier_chars['_'] = '_';
1017 identifier_chars['.'] = '.';
1018
1019 for (p = operand_special_chars; *p != '\0'; p++)
1020 operand_chars[(unsigned char) *p] = *p;
1021 }
1022
1023#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1024 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1025 {
1026 record_alignment (text_section, 2);
1027 record_alignment (data_section, 2);
1028 record_alignment (bss_section, 2);
1029 }
1030#endif
a4447b93
RH		 1031
1032 if (flag_code == CODE_64BIT)
1033 {
1034 x86_dwarf2_return_column = 16;
1035 x86_cie_data_alignment = -8;
1036 }
1037 else
1038 {
1039 x86_dwarf2_return_column = 8;
1040 x86_cie_data_alignment = -4;
1041 }
252b5132
RH		 1042}
1043
1044void
1045i386_print_statistics (file)
1046 FILE *file;
1047{
1048 hash_print_statistics (file, "i386 opcode", op_hash);
1049 hash_print_statistics (file, "i386 register", reg_hash);
1050}
1051\f
252b5132
RH		 1052#ifdef DEBUG386
1053
ce8a8b2f 1054/* Debugging routines for md_assemble. */
252b5132
RH		 1055static void pi PARAMS ((char *, i386_insn *));
1056static void pte PARAMS ((template *));
1057static void pt PARAMS ((unsigned int));
1058static void pe PARAMS ((expressionS *));
1059static void ps PARAMS ((symbolS *));
1060
1061static void
1062pi (line, x)
1063 char *line;
1064 i386_insn *x;
1065{
09f131f2 1066 unsigned int i;
252b5132
RH		 1067
1068 fprintf (stdout, "%s: template ", line);
1069 pte (&x->tm);
09f131f2
JH		 1070 fprintf (stdout, " address: base %s index %s scale %x\n",
1071 x->base_reg ? x->base_reg->reg_name : "none",
1072 x->index_reg ? x->index_reg->reg_name : "none",
1073 x->log2_scale_factor);
1074 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1075 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1076 fprintf (stdout, " sib: base %x index %x scale %x\n",
1077 x->sib.base, x->sib.index, x->sib.scale);
1078 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1079 (x->rex & REX_MODE64) != 0,
1080 (x->rex & REX_EXTX) != 0,
1081 (x->rex & REX_EXTY) != 0,
1082 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1083 for (i = 0; i < x->operands; i++)
1084 {
1085 fprintf (stdout, " #%d: ", i + 1);
1086 pt (x->types[i]);
1087 fprintf (stdout, "\n");
1088 if (x->types[i]
3f4438ab 1089 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1090 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1091 if (x->types[i] & Imm)
520dc8e8 1092 pe (x->op[i].imms);
252b5132 1093 if (x->types[i] & Disp)
520dc8e8 1094 pe (x->op[i].disps);
252b5132
RH		 1095 }
1096}
1097
1098static void
1099pte (t)
1100 template *t;
1101{
09f131f2 1102 unsigned int i;
252b5132 1103 fprintf (stdout, " %d operands ", t->operands);
47926f60 1104 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1105 if (t->extension_opcode != None)
1106 fprintf (stdout, "ext %x ", t->extension_opcode);
1107 if (t->opcode_modifier & D)
1108 fprintf (stdout, "D");
1109 if (t->opcode_modifier & W)
1110 fprintf (stdout, "W");
1111 fprintf (stdout, "\n");
1112 for (i = 0; i < t->operands; i++)
1113 {
1114 fprintf (stdout, " #%d type ", i + 1);
1115 pt (t->operand_types[i]);
1116 fprintf (stdout, "\n");
1117 }
1118}
1119
1120static void
1121pe (e)
1122 expressionS *e;
1123{
24eab124 1124 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1125 fprintf (stdout, " add_number %ld (%lx)\n",
1126 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1127 if (e->X_add_symbol)
1128 {
1129 fprintf (stdout, " add_symbol ");
1130 ps (e->X_add_symbol);
1131 fprintf (stdout, "\n");
1132 }
1133 if (e->X_op_symbol)
1134 {
1135 fprintf (stdout, " op_symbol ");
1136 ps (e->X_op_symbol);
1137 fprintf (stdout, "\n");
1138 }
1139}
1140
1141static void
1142ps (s)
1143 symbolS *s;
1144{
1145 fprintf (stdout, "%s type %s%s",
1146 S_GET_NAME (s),
1147 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1148 segment_name (S_GET_SEGMENT (s)));
1149}
1150
1151struct type_name
1152 {
1153 unsigned int mask;
1154 char *tname;
1155 }
1156
29b0f896 1157static const type_names[] =
252b5132
RH		 1158{
1159 { Reg8, "r8" },
1160 { Reg16, "r16" },
1161 { Reg32, "r32" },
09f131f2 1162 { Reg64, "r64" },
252b5132
RH		 1163 { Imm8, "i8" },
1164 { Imm8S, "i8s" },
1165 { Imm16, "i16" },
1166 { Imm32, "i32" },
09f131f2
JH		 1167 { Imm32S, "i32s" },
1168 { Imm64, "i64" },
252b5132
RH		 1169 { Imm1, "i1" },
1170 { BaseIndex, "BaseIndex" },
1171 { Disp8, "d8" },
1172 { Disp16, "d16" },
1173 { Disp32, "d32" },
09f131f2
JH		 1174 { Disp32S, "d32s" },
1175 { Disp64, "d64" },
252b5132
RH		 1176 { InOutPortReg, "InOutPortReg" },
1177 { ShiftCount, "ShiftCount" },
1178 { Control, "control reg" },
1179 { Test, "test reg" },
1180 { Debug, "debug reg" },
1181 { FloatReg, "FReg" },
1182 { FloatAcc, "FAcc" },
1183 { SReg2, "SReg2" },
1184 { SReg3, "SReg3" },
1185 { Acc, "Acc" },
1186 { JumpAbsolute, "Jump Absolute" },
1187 { RegMMX, "rMMX" },
3f4438ab 1188 { RegXMM, "rXMM" },
252b5132
RH		 1189 { EsSeg, "es" },
1190 { 0, "" }
1191};
1192
1193static void
1194pt (t)
1195 unsigned int t;
1196{
29b0f896 1197 const struct type_name *ty;
252b5132 1198
09f131f2
JH		 1199 for (ty = type_names; ty->mask; ty++)
1200 if (t & ty->mask)
1201 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1202 fflush (stdout);
1203}
1204
1205#endif /* DEBUG386 */
1206\f
252b5132 1207static bfd_reloc_code_real_type
3956db08
JB		 1208reloc (unsigned int size,
1209 int pcrel,
1210 int sign,
1211 bfd_reloc_code_real_type other)
252b5132 1212{
47926f60 1213 if (other != NO_RELOC)
3956db08
JB		 1214 {
1215 reloc_howto_type *reloc;
1216
1217 if (size == 8)
1218 switch (other)
1219 {
1220 case BFD_RELOC_X86_64_TPOFF32:
1221 other = BFD_RELOC_X86_64_TPOFF64;
1222 break;
1223 case BFD_RELOC_X86_64_DTPOFF32:
1224 other = BFD_RELOC_X86_64_DTPOFF64;
1225 break;
1226 default:
1227 break;
1228 }
1229 reloc = bfd_reloc_type_lookup (stdoutput, other);
1230 if (!reloc)
1231 as_bad (_("unknown relocation (%u)"), other);
1232 else if (size != bfd_get_reloc_size (reloc))
1233 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1234 bfd_get_reloc_size (reloc),
1235 size);
1236 else if (pcrel && !reloc->pc_relative)
1237 as_bad (_("non-pc-relative relocation for pc-relative field"));
1238 else if ((reloc->complain_on_overflow == complain_overflow_signed
1239 && !sign)
1240 || (reloc->complain_on_overflow == complain_overflow_unsigned
1241 && sign > 0))
1242 as_bad (_("relocated field and relocation type differ in signedness"));
1243 else
1244 return other;
1245 return NO_RELOC;
1246 }
252b5132
RH		 1247
1248 if (pcrel)
1249 {
3e73aa7c 1250 if (!sign)
3956db08 1251 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1252 switch (size)
1253 {
1254 case 1: return BFD_RELOC_8_PCREL;
1255 case 2: return BFD_RELOC_16_PCREL;
1256 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1257 case 8: return BFD_RELOC_64_PCREL;
252b5132 1258 }
3956db08 1259 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1260 }
1261 else
1262 {
3956db08 1263 if (sign > 0)
e5cb08ac 1264 switch (size)
3e73aa7c
JH		 1265 {
1266 case 4: return BFD_RELOC_X86_64_32S;
1267 }
1268 else
1269 switch (size)
1270 {
1271 case 1: return BFD_RELOC_8;
1272 case 2: return BFD_RELOC_16;
1273 case 4: return BFD_RELOC_32;
1274 case 8: return BFD_RELOC_64;
1275 }
3956db08
JB		 1276 as_bad (_("cannot do %s %u byte relocation"),
1277 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1278 }
1279
bfb32b52 1280 abort ();
252b5132
RH		 1281 return BFD_RELOC_NONE;
1282}
1283
47926f60
KH		 1284/* Here we decide which fixups can be adjusted to make them relative to
1285 the beginning of the section instead of the symbol. Basically we need
1286 to make sure that the dynamic relocations are done correctly, so in
1287 some cases we force the original symbol to be used. */
1288
252b5132 1289int
c0c949c7 1290tc_i386_fix_adjustable (fixP)
31312f95 1291 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1292{
6d249963 1293#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 1294 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1295 return 1;
1296
a161fe53
AM		 1297 /* Don't adjust pc-relative references to merge sections in 64-bit
1298 mode. */
1299 if (use_rela_relocations
1300 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1301 && fixP->fx_pcrel)
252b5132 1302 return 0;
31312f95 1303
8d01d9a9
AJ		 1304 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1305 and changed later by validate_fix. */
1306 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1307 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1308 return 0;
1309
ce8a8b2f 1310 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1311 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1312 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1313 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1314 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1315 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1316 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1317 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1318 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1319 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1320 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1321 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
3e73aa7c
JH		 1322 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1323 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1324 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1325 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1326 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1327 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1328 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1329 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1330 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1331 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1332 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
252b5132
RH		 1333 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1334 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1335 return 0;
31312f95 1336#endif
252b5132
RH		 1337 return 1;
1338}
252b5132 1339
29b0f896 1340static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1341
1342static int
252b5132 1343intel_float_operand (mnemonic)
29b0f896 1344 const char *mnemonic;
252b5132 1345{
9306ca4a
JB		 1346 /* Note that the value returned is meaningful only for opcodes with (memory)
1347 operands, hence the code here is free to improperly handle opcodes that
1348 have no operands (for better performance and smaller code). */
1349
1350 if (mnemonic[0] != 'f')
1351 return 0; /* non-math */
1352
1353 switch (mnemonic[1])
1354 {
1355 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1356 the fs segment override prefix not currently handled because no
1357 call path can make opcodes without operands get here */
1358 case 'i':
1359 return 2 /* integer op */;
1360 case 'l':
1361 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1362 return 3; /* fldcw/fldenv */
1363 break;
1364 case 'n':
1365 if (mnemonic[2] != 'o' /* fnop */)
1366 return 3; /* non-waiting control op */
1367 break;
1368 case 'r':
1369 if (mnemonic[2] == 's')
1370 return 3; /* frstor/frstpm */
1371 break;
1372 case 's':
1373 if (mnemonic[2] == 'a')
1374 return 3; /* fsave */
1375 if (mnemonic[2] == 't')
1376 {
1377 switch (mnemonic[3])
1378 {
1379 case 'c': /* fstcw */
1380 case 'd': /* fstdw */
1381 case 'e': /* fstenv */
1382 case 's': /* fsts[gw] */
1383 return 3;
1384 }
1385 }
1386 break;
1387 case 'x':
1388 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1389 return 0; /* fxsave/fxrstor are not really math ops */
1390 break;
1391 }
252b5132 1392
9306ca4a 1393 return 1;
252b5132
RH		 1394}
1395
1396/* This is the guts of the machine-dependent assembler. LINE points to a
1397 machine dependent instruction. This function is supposed to emit
1398 the frags/bytes it assembles to. */
1399
1400void
1401md_assemble (line)
1402 char *line;
1403{
252b5132 1404 int j;
252b5132
RH		 1405 char mnemonic[MAX_MNEM_SIZE];
1406
47926f60 1407 /* Initialize globals. */
252b5132
RH		 1408 memset (&i, '\0', sizeof (i));
1409 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1410 i.reloc[j] = NO_RELOC;
252b5132
RH		 1411 memset (disp_expressions, '\0', sizeof (disp_expressions));
1412 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1413 save_stack_p = save_stack;
252b5132
RH		 1414
1415 /* First parse an instruction mnemonic & call i386_operand for the operands.
1416 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1417 start of a (possibly prefixed) mnemonic. */
252b5132 1418
29b0f896
AM		 1419 line = parse_insn (line, mnemonic);
1420 if (line == NULL)
1421 return;
252b5132 1422
29b0f896
AM		 1423 line = parse_operands (line, mnemonic);
1424 if (line == NULL)
1425 return;
252b5132 1426
29b0f896
AM		 1427 /* Now we've parsed the mnemonic into a set of templates, and have the
1428 operands at hand. */
1429
1430 /* All intel opcodes have reversed operands except for "bound" and
1431 "enter". We also don't reverse intersegment "jmp" and "call"
1432 instructions with 2 immediate operands so that the immediate segment
1433 precedes the offset, as it does when in AT&T mode. "enter" and the
1434 intersegment "jmp" and "call" instructions are the only ones that
1435 have two immediate operands. */
1436 if (intel_syntax && i.operands > 1
1437 && (strcmp (mnemonic, "bound") != 0)
30123838 1438 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1439 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1440 swap_operands ();
1441
1442 if (i.imm_operands)
1443 optimize_imm ();
1444
b300c311
L		 1445 /* Don't optimize displacement for movabs since it only takes 64bit
1446 displacement. */
1447 if (i.disp_operands
1448 && (flag_code != CODE_64BIT
1449 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1450 optimize_disp ();
1451
1452 /* Next, we find a template that matches the given insn,
1453 making sure the overlap of the given operands types is consistent
1454 with the template operand types. */
252b5132 1455
29b0f896
AM		 1456 if (!match_template ())
1457 return;
252b5132 1458
cd61ebfe
AM		 1459 if (intel_syntax)
1460 {
1461 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1462 if (SYSV386_COMPAT
1463 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1464 i.tm.base_opcode ^= FloatR;
1465
1466 /* Zap movzx and movsx suffix. The suffix may have been set from
1467 "word ptr" or "byte ptr" on the source operand, but we'll use
1468 the suffix later to choose the destination register. */
1469 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1470 {
1471 if (i.reg_operands < 2
1472 && !i.suffix
1473 && (~i.tm.opcode_modifier
1474 & (No_bSuf
1475 | No_wSuf
1476 | No_lSuf
1477 | No_sSuf
1478 | No_xSuf
1479 | No_qSuf)))
1480 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1481
1482 i.suffix = 0;
1483 }
cd61ebfe 1484 }
24eab124 1485
29b0f896
AM		 1486 if (i.tm.opcode_modifier & FWait)
1487 if (!add_prefix (FWAIT_OPCODE))
1488 return;
252b5132 1489
29b0f896
AM		 1490 /* Check string instruction segment overrides. */
1491 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1492 {
1493 if (!check_string ())
5dd0794d 1494 return;
29b0f896 1495 }
5dd0794d 1496
29b0f896
AM		 1497 if (!process_suffix ())
1498 return;
e413e4e9 1499
29b0f896
AM		 1500 /* Make still unresolved immediate matches conform to size of immediate
1501 given in i.suffix. */
1502 if (!finalize_imm ())
1503 return;
252b5132 1504
29b0f896
AM		 1505 if (i.types[0] & Imm1)
1506 i.imm_operands = 0; /* kludge for shift insns. */
1507 if (i.types[0] & ImplicitRegister)
1508 i.reg_operands--;
1509 if (i.types[1] & ImplicitRegister)
1510 i.reg_operands--;
1511 if (i.types[2] & ImplicitRegister)
1512 i.reg_operands--;
252b5132 1513
29b0f896
AM		 1514 if (i.tm.opcode_modifier & ImmExt)
1515 {
02fc3089
L		 1516 expressionS *exp;
1517
ca164297
L		 1518 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1519 {
67c1ffbe 1520 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1521 operands with an opcode suffix which is coded in the same
1522 place as an 8-bit immediate field would be. Here we check
1523 those operands and remove them afterwards. */
1524 unsigned int x;
1525
a4622f40 1526 for (x = 0; x < i.operands; x++)
ca164297
L		 1527 if (i.op[x].regs->reg_num != x)
1528 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1529 i.op[x].regs->reg_name, x + 1, i.tm.name);
1530 i.operands = 0;
1531 }
1532
29b0f896
AM		 1533 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1534 opcode suffix which is coded in the same place as an 8-bit
1535 immediate field would be. Here we fake an 8-bit immediate
1536 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1537
29b0f896 1538 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1539
29b0f896
AM		 1540 exp = &im_expressions[i.imm_operands++];
1541 i.op[i.operands].imms = exp;
1542 i.types[i.operands++] = Imm8;
1543 exp->X_op = O_constant;
1544 exp->X_add_number = i.tm.extension_opcode;
1545 i.tm.extension_opcode = None;
1546 }
252b5132 1547
29b0f896
AM		 1548 /* For insns with operands there are more diddles to do to the opcode. */
1549 if (i.operands)
1550 {
1551 if (!process_operands ())
1552 return;
1553 }
1554 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1555 {
1556 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1557 as_warn (_("translating to `%sp'"), i.tm.name);
1558 }
252b5132 1559
29b0f896
AM		 1560 /* Handle conversion of 'int $3' --> special int3 insn. */
1561 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1562 {
1563 i.tm.base_opcode = INT3_OPCODE;
1564 i.imm_operands = 0;
1565 }
252b5132 1566
29b0f896
AM		 1567 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1568 && i.op[0].disps->X_op == O_constant)
1569 {
1570 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1571 the absolute address given by the constant. Since ix86 jumps and
1572 calls are pc relative, we need to generate a reloc. */
1573 i.op[0].disps->X_add_symbol = &abs_symbol;
1574 i.op[0].disps->X_op = O_symbol;
1575 }
252b5132 1576
29b0f896
AM		 1577 if ((i.tm.opcode_modifier & Rex64) != 0)
1578 i.rex |= REX_MODE64;
252b5132 1579
29b0f896
AM		 1580 /* For 8 bit registers we need an empty rex prefix. Also if the
1581 instruction already has a prefix, we need to convert old
1582 registers to new ones. */
773f551c 1583
29b0f896
AM		 1584 if (((i.types[0] & Reg8) != 0
1585 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1586 || ((i.types[1] & Reg8) != 0
1587 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1588 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1589 && i.rex != 0))
1590 {
1591 int x;
726c5dcd 1592
29b0f896
AM		 1593 i.rex |= REX_OPCODE;
1594 for (x = 0; x < 2; x++)
1595 {
1596 /* Look for 8 bit operand that uses old registers. */
1597 if ((i.types[x] & Reg8) != 0
1598 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1599 {
29b0f896
AM		 1600 /* In case it is "hi" register, give up. */
1601 if (i.op[x].regs->reg_num > 3)
0477af35 1602 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1603 i.op[x].regs->reg_name);
773f551c 1604
29b0f896
AM		 1605 /* Otherwise it is equivalent to the extended register.
1606 Since the encoding doesn't change this is merely
1607 cosmetic cleanup for debug output. */
1608
1609 i.op[x].regs = i.op[x].regs + 8;
773f551c 1610 }
29b0f896
AM		 1611 }
1612 }
773f551c 1613
29b0f896
AM		 1614 if (i.rex != 0)
1615 add_prefix (REX_OPCODE | i.rex);
1616
1617 /* We are ready to output the insn. */
1618 output_insn ();
1619}
1620
1621static char *
1622parse_insn (line, mnemonic)
1623 char *line;
1624 char *mnemonic;
1625{
1626 char *l = line;
1627 char *token_start = l;
1628 char *mnem_p;
5c6af06e
JB		 1629 int supported;
1630 const template *t;
29b0f896
AM		 1631
1632 /* Non-zero if we found a prefix only acceptable with string insns. */
1633 const char *expecting_string_instruction = NULL;
45288df1 1634
29b0f896
AM		 1635 while (1)
1636 {
1637 mnem_p = mnemonic;
1638 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1639 {
1640 mnem_p++;
1641 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1642 {
29b0f896
AM		 1643 as_bad (_("no such instruction: `%s'"), token_start);
1644 return NULL;
1645 }
1646 l++;
1647 }
1648 if (!is_space_char (*l)
1649 && *l != END_OF_INSN
e44823cf
JB		 1650 && (intel_syntax
1651 || (*l != PREFIX_SEPARATOR
1652 && *l != ',')))
29b0f896
AM		 1653 {
1654 as_bad (_("invalid character %s in mnemonic"),
1655 output_invalid (*l));
1656 return NULL;
1657 }
1658 if (token_start == l)
1659 {
e44823cf 1660 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1661 as_bad (_("expecting prefix; got nothing"));
1662 else
1663 as_bad (_("expecting mnemonic; got nothing"));
1664 return NULL;
1665 }
45288df1 1666
29b0f896
AM		 1667 /* Look up instruction (or prefix) via hash table. */
1668 current_templates = hash_find (op_hash, mnemonic);
47926f60 1669
29b0f896
AM		 1670 if (*l != END_OF_INSN
1671 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1672 && current_templates
1673 && (current_templates->start->opcode_modifier & IsPrefix))
1674 {
2dd88dca
JB		 1675 if (current_templates->start->cpu_flags
1676 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1677 {
1678 as_bad ((flag_code != CODE_64BIT
1679 ? _("`%s' is only supported in 64-bit mode")
1680 : _("`%s' is not supported in 64-bit mode")),
1681 current_templates->start->name);
1682 return NULL;
1683 }
29b0f896
AM		 1684 /* If we are in 16-bit mode, do not allow addr16 or data16.
1685 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1686 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1687 && flag_code != CODE_64BIT
1688 && (((current_templates->start->opcode_modifier & Size32) != 0)
1689 ^ (flag_code == CODE_16BIT)))
1690 {
1691 as_bad (_("redundant %s prefix"),
1692 current_templates->start->name);
1693 return NULL;
45288df1 1694 }
29b0f896
AM		 1695 /* Add prefix, checking for repeated prefixes. */
1696 switch (add_prefix (current_templates->start->base_opcode))
1697 {
1698 case 0:
1699 return NULL;
1700 case 2:
1701 expecting_string_instruction = current_templates->start->name;
1702 break;
1703 }
1704 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1705 token_start = ++l;
1706 }
1707 else
1708 break;
1709 }
45288df1 1710
29b0f896
AM		 1711 if (!current_templates)
1712 {
1713 /* See if we can get a match by trimming off a suffix. */
1714 switch (mnem_p[-1])
1715 {
1716 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1717 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1718 i.suffix = SHORT_MNEM_SUFFIX;
1719 else
29b0f896
AM		 1720 case BYTE_MNEM_SUFFIX:
1721 case QWORD_MNEM_SUFFIX:
1722 i.suffix = mnem_p[-1];
1723 mnem_p[-1] = '\0';
1724 current_templates = hash_find (op_hash, mnemonic);
1725 break;
1726 case SHORT_MNEM_SUFFIX:
1727 case LONG_MNEM_SUFFIX:
1728 if (!intel_syntax)
1729 {
1730 i.suffix = mnem_p[-1];
1731 mnem_p[-1] = '\0';
1732 current_templates = hash_find (op_hash, mnemonic);
1733 }
1734 break;
252b5132 1735
29b0f896
AM		 1736 /* Intel Syntax. */
1737 case 'd':
1738 if (intel_syntax)
1739 {
9306ca4a 1740 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1741 i.suffix = SHORT_MNEM_SUFFIX;
1742 else
1743 i.suffix = LONG_MNEM_SUFFIX;
1744 mnem_p[-1] = '\0';
1745 current_templates = hash_find (op_hash, mnemonic);
1746 }
1747 break;
1748 }
1749 if (!current_templates)
1750 {
1751 as_bad (_("no such instruction: `%s'"), token_start);
1752 return NULL;
1753 }
1754 }
252b5132 1755
29b0f896
AM		 1756 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1757 {
1758 /* Check for a branch hint. We allow ",pt" and ",pn" for
1759 predict taken and predict not taken respectively.
1760 I'm not sure that branch hints actually do anything on loop
1761 and jcxz insns (JumpByte) for current Pentium4 chips. They
1762 may work in the future and it doesn't hurt to accept them
1763 now. */
1764 if (l[0] == ',' && l[1] == 'p')
1765 {
1766 if (l[2] == 't')
1767 {
1768 if (!add_prefix (DS_PREFIX_OPCODE))
1769 return NULL;
1770 l += 3;
1771 }
1772 else if (l[2] == 'n')
1773 {
1774 if (!add_prefix (CS_PREFIX_OPCODE))
1775 return NULL;
1776 l += 3;
1777 }
1778 }
1779 }
1780 /* Any other comma loses. */
1781 if (*l == ',')
1782 {
1783 as_bad (_("invalid character %s in mnemonic"),
1784 output_invalid (*l));
1785 return NULL;
1786 }
252b5132 1787
29b0f896 1788 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1789 supported = 0;
1790 for (t = current_templates->start; t < current_templates->end; ++t)
1791 {
1792 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1793 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
1794 supported |= 1;
1795 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
1796 supported |= 2;
1797 }
1798 if (!(supported & 2))
1799 {
1800 as_bad (flag_code == CODE_64BIT
1801 ? _("`%s' is not supported in 64-bit mode")
1802 : _("`%s' is only supported in 64-bit mode"),
1803 current_templates->start->name);
1804 return NULL;
1805 }
1806 if (!(supported & 1))
29b0f896 1807 {
5c6af06e
JB		 1808 as_warn (_("`%s' is not supported on `%s%s'"),
1809 current_templates->start->name,
1810 cpu_arch_name,
1811 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1812 }
1813 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1814 {
1815 as_warn (_("use .code16 to ensure correct addressing mode"));
1816 }
252b5132 1817
29b0f896 1818 /* Check for rep/repne without a string instruction. */
f41bbced 1819 if (expecting_string_instruction)
29b0f896 1820 {
f41bbced
JB		 1821 static templates override;
1822
1823 for (t = current_templates->start; t < current_templates->end; ++t)
1824 if (t->opcode_modifier & IsString)
1825 break;
1826 if (t >= current_templates->end)
1827 {
1828 as_bad (_("expecting string instruction after `%s'"),
1829 expecting_string_instruction);
1830 return NULL;
1831 }
1832 for (override.start = t; t < current_templates->end; ++t)
1833 if (!(t->opcode_modifier & IsString))
1834 break;
1835 override.end = t;
1836 current_templates = &override;
29b0f896 1837 }
252b5132 1838
29b0f896
AM		 1839 return l;
1840}
252b5132 1841
29b0f896
AM		 1842static char *
1843parse_operands (l, mnemonic)
1844 char *l;
1845 const char *mnemonic;
1846{
1847 char *token_start;
3138f287 1848
29b0f896
AM		 1849 /* 1 if operand is pending after ','. */
1850 unsigned int expecting_operand = 0;
252b5132 1851
29b0f896
AM		 1852 /* Non-zero if operand parens not balanced. */
1853 unsigned int paren_not_balanced;
1854
1855 while (*l != END_OF_INSN)
1856 {
1857 /* Skip optional white space before operand. */
1858 if (is_space_char (*l))
1859 ++l;
1860 if (!is_operand_char (*l) && *l != END_OF_INSN)
1861 {
1862 as_bad (_("invalid character %s before operand %d"),
1863 output_invalid (*l),
1864 i.operands + 1);
1865 return NULL;
1866 }
1867 token_start = l; /* after white space */
1868 paren_not_balanced = 0;
1869 while (paren_not_balanced || *l != ',')
1870 {
1871 if (*l == END_OF_INSN)
1872 {
1873 if (paren_not_balanced)
1874 {
1875 if (!intel_syntax)
1876 as_bad (_("unbalanced parenthesis in operand %d."),
1877 i.operands + 1);
1878 else
1879 as_bad (_("unbalanced brackets in operand %d."),
1880 i.operands + 1);
1881 return NULL;
1882 }
1883 else
1884 break; /* we are done */
1885 }
1886 else if (!is_operand_char (*l) && !is_space_char (*l))
1887 {
1888 as_bad (_("invalid character %s in operand %d"),
1889 output_invalid (*l),
1890 i.operands + 1);
1891 return NULL;
1892 }
1893 if (!intel_syntax)
1894 {
1895 if (*l == '(')
1896 ++paren_not_balanced;
1897 if (*l == ')')
1898 --paren_not_balanced;
1899 }
1900 else
1901 {
1902 if (*l == '[')
1903 ++paren_not_balanced;
1904 if (*l == ']')
1905 --paren_not_balanced;
1906 }
1907 l++;
1908 }
1909 if (l != token_start)
1910 { /* Yes, we've read in another operand. */
1911 unsigned int operand_ok;
1912 this_operand = i.operands++;
1913 if (i.operands > MAX_OPERANDS)
1914 {
1915 as_bad (_("spurious operands; (%d operands/instruction max)"),
1916 MAX_OPERANDS);
1917 return NULL;
1918 }
1919 /* Now parse operand adding info to 'i' as we go along. */
1920 END_STRING_AND_SAVE (l);
1921
1922 if (intel_syntax)
1923 operand_ok =
1924 i386_intel_operand (token_start,
1925 intel_float_operand (mnemonic));
1926 else
1927 operand_ok = i386_operand (token_start);
1928
1929 RESTORE_END_STRING (l);
1930 if (!operand_ok)
1931 return NULL;
1932 }
1933 else
1934 {
1935 if (expecting_operand)
1936 {
1937 expecting_operand_after_comma:
1938 as_bad (_("expecting operand after ','; got nothing"));
1939 return NULL;
1940 }
1941 if (*l == ',')
1942 {
1943 as_bad (_("expecting operand before ','; got nothing"));
1944 return NULL;
1945 }
1946 }
7f3f1ea2 1947
29b0f896
AM		 1948 /* Now *l must be either ',' or END_OF_INSN. */
1949 if (*l == ',')
1950 {
1951 if (*++l == END_OF_INSN)
1952 {
1953 /* Just skip it, if it's \n complain. */
1954 goto expecting_operand_after_comma;
1955 }
1956 expecting_operand = 1;
1957 }
1958 }
1959 return l;
1960}
7f3f1ea2 1961
29b0f896
AM		 1962static void
1963swap_operands ()
1964{
1965 union i386_op temp_op;
1966 unsigned int temp_type;
f86103b7 1967 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 1968 int xchg1 = 0;
1969 int xchg2 = 0;
252b5132 1970
29b0f896
AM		 1971 if (i.operands == 2)
1972 {
1973 xchg1 = 0;
1974 xchg2 = 1;
1975 }
1976 else if (i.operands == 3)
1977 {
1978 xchg1 = 0;
1979 xchg2 = 2;
1980 }
1981 temp_type = i.types[xchg2];
1982 i.types[xchg2] = i.types[xchg1];
1983 i.types[xchg1] = temp_type;
1984 temp_op = i.op[xchg2];
1985 i.op[xchg2] = i.op[xchg1];
1986 i.op[xchg1] = temp_op;
1987 temp_reloc = i.reloc[xchg2];
1988 i.reloc[xchg2] = i.reloc[xchg1];
1989 i.reloc[xchg1] = temp_reloc;
1990
1991 if (i.mem_operands == 2)
1992 {
1993 const seg_entry *temp_seg;
1994 temp_seg = i.seg[0];
1995 i.seg[0] = i.seg[1];
1996 i.seg[1] = temp_seg;
1997 }
1998}
252b5132 1999
29b0f896
AM		 2000/* Try to ensure constant immediates are represented in the smallest
2001 opcode possible. */
2002static void
2003optimize_imm ()
2004{
2005 char guess_suffix = 0;
2006 int op;
252b5132 2007
29b0f896
AM		 2008 if (i.suffix)
2009 guess_suffix = i.suffix;
2010 else if (i.reg_operands)
2011 {
2012 /* Figure out a suffix from the last register operand specified.
2013 We can't do this properly yet, ie. excluding InOutPortReg,
2014 but the following works for instructions with immediates.
2015 In any case, we can't set i.suffix yet. */
2016 for (op = i.operands; --op >= 0;)
2017 if (i.types[op] & Reg)
252b5132 2018 {
29b0f896
AM		 2019 if (i.types[op] & Reg8)
2020 guess_suffix = BYTE_MNEM_SUFFIX;
2021 else if (i.types[op] & Reg16)
2022 guess_suffix = WORD_MNEM_SUFFIX;
2023 else if (i.types[op] & Reg32)
2024 guess_suffix = LONG_MNEM_SUFFIX;
2025 else if (i.types[op] & Reg64)
2026 guess_suffix = QWORD_MNEM_SUFFIX;
2027 break;
252b5132 2028 }
29b0f896
AM		 2029 }
2030 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2031 guess_suffix = WORD_MNEM_SUFFIX;
2032
2033 for (op = i.operands; --op >= 0;)
2034 if (i.types[op] & Imm)
2035 {
2036 switch (i.op[op].imms->X_op)
252b5132 2037 {
29b0f896
AM		 2038 case O_constant:
2039 /* If a suffix is given, this operand may be shortened. */
2040 switch (guess_suffix)
252b5132 2041 {
29b0f896
AM		 2042 case LONG_MNEM_SUFFIX:
2043 i.types[op] |= Imm32 | Imm64;
2044 break;
2045 case WORD_MNEM_SUFFIX:
2046 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2047 break;
2048 case BYTE_MNEM_SUFFIX:
2049 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2050 break;
252b5132 2051 }
252b5132 2052
29b0f896
AM		 2053 /* If this operand is at most 16 bits, convert it
2054 to a signed 16 bit number before trying to see
2055 whether it will fit in an even smaller size.
2056 This allows a 16-bit operand such as $0xffe0 to
2057 be recognised as within Imm8S range. */
2058 if ((i.types[op] & Imm16)
2059 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2060 {
29b0f896
AM		 2061 i.op[op].imms->X_add_number =
2062 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2063 }
2064 if ((i.types[op] & Imm32)
2065 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2066 == 0))
2067 {
2068 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2069 ^ ((offsetT) 1 << 31))
2070 - ((offsetT) 1 << 31));
2071 }
2072 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2073
29b0f896
AM		 2074 /* We must avoid matching of Imm32 templates when 64bit
2075 only immediate is available. */
2076 if (guess_suffix == QWORD_MNEM_SUFFIX)
2077 i.types[op] &= ~Imm32;
2078 break;
252b5132 2079
29b0f896
AM		 2080 case O_absent:
2081 case O_register:
2082 abort ();
2083
2084 /* Symbols and expressions. */
2085 default:
2086 /* Convert symbolic operand to proper sizes for matching. */
2087 switch (guess_suffix)
2088 {
2089 case QWORD_MNEM_SUFFIX:
3956db08 2090 i.types[op] &= Imm64 | Imm32S;
29b0f896
AM		 2091 break;
2092 case LONG_MNEM_SUFFIX:
3956db08 2093 i.types[op] &= Imm32;
29b0f896
AM		 2094 break;
2095 case WORD_MNEM_SUFFIX:
3956db08 2096 i.types[op] &= Imm16;
29b0f896
AM		 2097 break;
2098 case BYTE_MNEM_SUFFIX:
3956db08 2099 i.types[op] &= Imm8 | Imm8S;
29b0f896 2100 break;
252b5132 2101 }
29b0f896 2102 break;
252b5132 2103 }
29b0f896
AM		 2104 }
2105}
47926f60 2106
29b0f896
AM		 2107/* Try to use the smallest displacement type too. */
2108static void
2109optimize_disp ()
2110{
2111 int op;
3e73aa7c 2112
29b0f896 2113 for (op = i.operands; --op >= 0;)
b300c311 2114 if (i.types[op] & Disp)
252b5132 2115 {
b300c311 2116 if (i.op[op].disps->X_op == O_constant)
252b5132 2117 {
b300c311 2118 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2119
b300c311
L		 2120 if ((i.types[op] & Disp16)
2121 && (disp & ~(offsetT) 0xffff) == 0)
2122 {
2123 /* If this operand is at most 16 bits, convert
2124 to a signed 16 bit number and don't use 64bit
2125 displacement. */
2126 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2127 i.types[op] &= ~Disp64;
2128 }
2129 if ((i.types[op] & Disp32)
2130 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2131 {
2132 /* If this operand is at most 32 bits, convert
2133 to a signed 32 bit number and don't use 64bit
2134 displacement. */
2135 disp &= (((offsetT) 2 << 31) - 1);
2136 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2137 i.types[op] &= ~Disp64;
2138 }
2139 if (!disp && (i.types[op] & BaseIndex))
2140 {
2141 i.types[op] &= ~Disp;
2142 i.op[op].disps = 0;
2143 i.disp_operands--;
2144 }
2145 else if (flag_code == CODE_64BIT)
2146 {
2147 if (fits_in_signed_long (disp))
28a9d8f5
L		 2148 {
2149 i.types[op] &= ~Disp64;
2150 i.types[op] |= Disp32S;
2151 }
b300c311
L		 2152 if (fits_in_unsigned_long (disp))
2153 i.types[op] |= Disp32;
2154 }
2155 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2156 && fits_in_signed_byte (disp))
2157 i.types[op] |= Disp8;
252b5132 2158 }
b300c311
L		 2159 else
2160 /* We only support 64bit displacement on constants. */
2161 i.types[op] &= ~Disp64;
252b5132 2162 }
29b0f896
AM		 2163}
2164
2165static int
2166match_template ()
2167{
2168 /* Points to template once we've found it. */
2169 const template *t;
2170 unsigned int overlap0, overlap1, overlap2;
2171 unsigned int found_reverse_match;
2172 int suffix_check;
2173
2174#define MATCH(overlap, given, template) \
2175 ((overlap & ~JumpAbsolute) \
2176 && (((given) & (BaseIndex | JumpAbsolute)) \
2177 == ((overlap) & (BaseIndex | JumpAbsolute))))
2178
2179 /* If given types r0 and r1 are registers they must be of the same type
2180 unless the expected operand type register overlap is null.
2181 Note that Acc in a template matches every size of reg. */
2182#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2183 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2184 || ((g0) & Reg) == ((g1) & Reg) \
2185 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2186
2187 overlap0 = 0;
2188 overlap1 = 0;
2189 overlap2 = 0;
2190 found_reverse_match = 0;
2191 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2192 ? No_bSuf
2193 : (i.suffix == WORD_MNEM_SUFFIX
2194 ? No_wSuf
2195 : (i.suffix == SHORT_MNEM_SUFFIX
2196 ? No_sSuf
2197 : (i.suffix == LONG_MNEM_SUFFIX
2198 ? No_lSuf
2199 : (i.suffix == QWORD_MNEM_SUFFIX
2200 ? No_qSuf
2201 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2202 ? No_xSuf : 0))))));
2203
20f0a1fc
NC		 2204 t = current_templates->start;
2205 if (i.suffix == QWORD_MNEM_SUFFIX
2206 && flag_code != CODE_64BIT
9306ca4a
JB		 2207 && (intel_syntax
2208 ? !(t->opcode_modifier & IgnoreSize)
2209 && !intel_float_operand (t->name)
2210 : intel_float_operand (t->name) != 2)
20f0a1fc
NC		 2211 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2212 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2213 && (t->base_opcode != 0x0fc7
2214 || t->extension_opcode != 1 /* cmpxchg8b */))
2215 t = current_templates->end;
2216 for (; t < current_templates->end; t++)
29b0f896
AM		 2217 {
2218 /* Must have right number of operands. */
2219 if (i.operands != t->operands)
2220 continue;
2221
2222 /* Check the suffix, except for some instructions in intel mode. */
2223 if ((t->opcode_modifier & suffix_check)
2224 && !(intel_syntax
9306ca4a 2225 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2226 continue;
2227
2228 /* Do not verify operands when there are none. */
2229 else if (!t->operands)
2230 {
2231 if (t->cpu_flags & ~cpu_arch_flags)
2232 continue;
2233 /* We've found a match; break out of loop. */
2234 break;
2235 }
252b5132 2236
29b0f896
AM		 2237 overlap0 = i.types[0] & t->operand_types[0];
2238 switch (t->operands)
2239 {
2240 case 1:
2241 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2242 continue;
2243 break;
2244 case 2:
2245 case 3:
2246 overlap1 = i.types[1] & t->operand_types[1];
2247 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2248 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2249 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2250 t->operand_types[0],
2251 overlap1, i.types[1],
2252 t->operand_types[1]))
2253 {
2254 /* Check if other direction is valid ... */
2255 if ((t->opcode_modifier & (D | FloatD)) == 0)
2256 continue;
2257
2258 /* Try reversing direction of operands. */
2259 overlap0 = i.types[0] & t->operand_types[1];
2260 overlap1 = i.types[1] & t->operand_types[0];
2261 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2262 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2263 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2264 t->operand_types[1],
2265 overlap1, i.types[1],
2266 t->operand_types[0]))
2267 {
2268 /* Does not match either direction. */
2269 continue;
2270 }
2271 /* found_reverse_match holds which of D or FloatDR
2272 we've found. */
2273 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2274 }
2275 /* Found a forward 2 operand match here. */
2276 else if (t->operands == 3)
2277 {
2278 /* Here we make use of the fact that there are no
2279 reverse match 3 operand instructions, and all 3
2280 operand instructions only need to be checked for
2281 register consistency between operands 2 and 3. */
2282 overlap2 = i.types[2] & t->operand_types[2];
2283 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2284 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2285 t->operand_types[1],
2286 overlap2, i.types[2],
2287 t->operand_types[2]))
2288
2289 continue;
2290 }
2291 /* Found either forward/reverse 2 or 3 operand match here:
2292 slip through to break. */
2293 }
2294 if (t->cpu_flags & ~cpu_arch_flags)
2295 {
2296 found_reverse_match = 0;
2297 continue;
2298 }
2299 /* We've found a match; break out of loop. */
2300 break;
2301 }
2302
2303 if (t == current_templates->end)
2304 {
2305 /* We found no match. */
2306 as_bad (_("suffix or operands invalid for `%s'"),
2307 current_templates->start->name);
2308 return 0;
2309 }
252b5132 2310
29b0f896
AM		 2311 if (!quiet_warnings)
2312 {
2313 if (!intel_syntax
2314 && ((i.types[0] & JumpAbsolute)
2315 != (t->operand_types[0] & JumpAbsolute)))
2316 {
2317 as_warn (_("indirect %s without `*'"), t->name);
2318 }
2319
2320 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2321 == (IsPrefix | IgnoreSize))
2322 {
2323 /* Warn them that a data or address size prefix doesn't
2324 affect assembly of the next line of code. */
2325 as_warn (_("stand-alone `%s' prefix"), t->name);
2326 }
2327 }
2328
2329 /* Copy the template we found. */
2330 i.tm = *t;
2331 if (found_reverse_match)
2332 {
2333 /* If we found a reverse match we must alter the opcode
2334 direction bit. found_reverse_match holds bits to change
2335 (different for int & float insns). */
2336
2337 i.tm.base_opcode ^= found_reverse_match;
2338
2339 i.tm.operand_types[0] = t->operand_types[1];
2340 i.tm.operand_types[1] = t->operand_types[0];
2341 }
2342
2343 return 1;
2344}
2345
2346static int
2347check_string ()
2348{
2349 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2350 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2351 {
2352 if (i.seg[0] != NULL && i.seg[0] != &es)
2353 {
2354 as_bad (_("`%s' operand %d must use `%%es' segment"),
2355 i.tm.name,
2356 mem_op + 1);
2357 return 0;
2358 }
2359 /* There's only ever one segment override allowed per instruction.
2360 This instruction possibly has a legal segment override on the
2361 second operand, so copy the segment to where non-string
2362 instructions store it, allowing common code. */
2363 i.seg[0] = i.seg[1];
2364 }
2365 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2366 {
2367 if (i.seg[1] != NULL && i.seg[1] != &es)
2368 {
2369 as_bad (_("`%s' operand %d must use `%%es' segment"),
2370 i.tm.name,
2371 mem_op + 2);
2372 return 0;
2373 }
2374 }
2375 return 1;
2376}
2377
2378static int
543613e9 2379process_suffix (void)
29b0f896
AM		 2380{
2381 /* If matched instruction specifies an explicit instruction mnemonic
2382 suffix, use it. */
2383 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2384 {
2385 if (i.tm.opcode_modifier & Size16)
2386 i.suffix = WORD_MNEM_SUFFIX;
2387 else if (i.tm.opcode_modifier & Size64)
2388 i.suffix = QWORD_MNEM_SUFFIX;
2389 else
2390 i.suffix = LONG_MNEM_SUFFIX;
2391 }
2392 else if (i.reg_operands)
2393 {
2394 /* If there's no instruction mnemonic suffix we try to invent one
2395 based on register operands. */
2396 if (!i.suffix)
2397 {
2398 /* We take i.suffix from the last register operand specified,
2399 Destination register type is more significant than source
2400 register type. */
2401 int op;
543613e9 2402
29b0f896
AM		 2403 for (op = i.operands; --op >= 0;)
2404 if ((i.types[op] & Reg)
2405 && !(i.tm.operand_types[op] & InOutPortReg))
2406 {
2407 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2408 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2409 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2410 LONG_MNEM_SUFFIX);
2411 break;
2412 }
2413 }
2414 else if (i.suffix == BYTE_MNEM_SUFFIX)
2415 {
2416 if (!check_byte_reg ())
2417 return 0;
2418 }
2419 else if (i.suffix == LONG_MNEM_SUFFIX)
2420 {
2421 if (!check_long_reg ())
2422 return 0;
2423 }
2424 else if (i.suffix == QWORD_MNEM_SUFFIX)
2425 {
2426 if (!check_qword_reg ())
2427 return 0;
2428 }
2429 else if (i.suffix == WORD_MNEM_SUFFIX)
2430 {
2431 if (!check_word_reg ())
2432 return 0;
2433 }
2434 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2435 /* Do nothing if the instruction is going to ignore the prefix. */
2436 ;
2437 else
2438 abort ();
2439 }
9306ca4a
JB		 2440 else if ((i.tm.opcode_modifier & DefaultSize)
2441 && !i.suffix
2442 /* exclude fldenv/frstor/fsave/fstenv */
2443 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2444 {
2445 i.suffix = stackop_size;
2446 }
9306ca4a
JB		 2447 else if (intel_syntax
2448 && !i.suffix
2449 && ((i.tm.operand_types[0] & JumpAbsolute)
2450 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2451 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2452 && i.tm.extension_opcode <= 3)))
2453 {
2454 switch (flag_code)
2455 {
2456 case CODE_64BIT:
2457 if (!(i.tm.opcode_modifier & No_qSuf))
2458 {
2459 i.suffix = QWORD_MNEM_SUFFIX;
2460 break;
2461 }
2462 case CODE_32BIT:
2463 if (!(i.tm.opcode_modifier & No_lSuf))
2464 i.suffix = LONG_MNEM_SUFFIX;
2465 break;
2466 case CODE_16BIT:
2467 if (!(i.tm.opcode_modifier & No_wSuf))
2468 i.suffix = WORD_MNEM_SUFFIX;
2469 break;
2470 }
2471 }
252b5132 2472
9306ca4a 2473 if (!i.suffix)
29b0f896 2474 {
9306ca4a
JB		 2475 if (!intel_syntax)
2476 {
2477 if (i.tm.opcode_modifier & W)
2478 {
2479 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2480 return 0;
2481 }
2482 }
2483 else
2484 {
2485 unsigned int suffixes = ~i.tm.opcode_modifier
2486 & (No_bSuf
2487 | No_wSuf
2488 | No_lSuf
2489 | No_sSuf
2490 | No_xSuf
2491 | No_qSuf);
2492
2493 if ((i.tm.opcode_modifier & W)
2494 || ((suffixes & (suffixes - 1))
2495 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2496 {
2497 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2498 return 0;
2499 }
2500 }
29b0f896 2501 }
252b5132 2502
9306ca4a
JB		 2503 /* Change the opcode based on the operand size given by i.suffix;
2504 We don't need to change things for byte insns. */
2505
29b0f896
AM		 2506 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2507 {
2508 /* It's not a byte, select word/dword operation. */
2509 if (i.tm.opcode_modifier & W)
2510 {
2511 if (i.tm.opcode_modifier & ShortForm)
2512 i.tm.base_opcode |= 8;
2513 else
2514 i.tm.base_opcode |= 1;
2515 }
0f3f3d8b 2516
29b0f896
AM		 2517 /* Now select between word & dword operations via the operand
2518 size prefix, except for instructions that will ignore this
2519 prefix anyway. */
2520 if (i.suffix != QWORD_MNEM_SUFFIX
9306ca4a
JB		 2521 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2522 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
9146926a
AM		 2523 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2524 || (flag_code == CODE_64BIT
2525 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2526 {
2527 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2528
29b0f896
AM		 2529 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2530 prefix = ADDR_PREFIX_OPCODE;
252b5132 2531
29b0f896
AM		 2532 if (!add_prefix (prefix))
2533 return 0;
24eab124 2534 }
252b5132 2535
29b0f896
AM		 2536 /* Set mode64 for an operand. */
2537 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2538 && flag_code == CODE_64BIT
29b0f896 2539 && (i.tm.opcode_modifier & NoRex64) == 0)
9146926a 2540 i.rex |= REX_MODE64;
3e73aa7c 2541
29b0f896
AM		 2542 /* Size floating point instruction. */
2543 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2544 if (i.tm.opcode_modifier & FloatMF)
2545 i.tm.base_opcode ^= 4;
29b0f896 2546 }
7ecd2f8b 2547
29b0f896
AM		 2548 return 1;
2549}
3e73aa7c 2550
29b0f896 2551static int
543613e9 2552check_byte_reg (void)
29b0f896
AM		 2553{
2554 int op;
543613e9 2555
29b0f896
AM		 2556 for (op = i.operands; --op >= 0;)
2557 {
2558 /* If this is an eight bit register, it's OK. If it's the 16 or
2559 32 bit version of an eight bit register, we will just use the
2560 low portion, and that's OK too. */
2561 if (i.types[op] & Reg8)
2562 continue;
2563
2564 /* movzx and movsx should not generate this warning. */
2565 if (intel_syntax
2566 && (i.tm.base_opcode == 0xfb7
2567 || i.tm.base_opcode == 0xfb6
2568 || i.tm.base_opcode == 0x63
2569 || i.tm.base_opcode == 0xfbe
2570 || i.tm.base_opcode == 0xfbf))
2571 continue;
2572
65ec77d2 2573 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2574 {
2575 /* Prohibit these changes in the 64bit mode, since the
2576 lowering is more complicated. */
2577 if (flag_code == CODE_64BIT
2578 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2579 {
0f3f3d8b 2580 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2581 i.op[op].regs->reg_name,
2582 i.suffix);
2583 return 0;
2584 }
2585#if REGISTER_WARNINGS
2586 if (!quiet_warnings
2587 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2588 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2589 (i.op[op].regs + (i.types[op] & Reg16
2590 ? REGNAM_AL - REGNAM_AX
2591 : REGNAM_AL - REGNAM_EAX))->reg_name,
2592 i.op[op].regs->reg_name,
2593 i.suffix);
2594#endif
2595 continue;
2596 }
2597 /* Any other register is bad. */
2598 if (i.types[op] & (Reg | RegMMX | RegXMM
2599 | SReg2 | SReg3
2600 | Control | Debug | Test
2601 | FloatReg | FloatAcc))
2602 {
2603 as_bad (_("`%%%s' not allowed with `%s%c'"),
2604 i.op[op].regs->reg_name,
2605 i.tm.name,
2606 i.suffix);
2607 return 0;
2608 }
2609 }
2610 return 1;
2611}
2612
2613static int
2614check_long_reg ()
2615{
2616 int op;
2617
2618 for (op = i.operands; --op >= 0;)
2619 /* Reject eight bit registers, except where the template requires
2620 them. (eg. movzb) */
2621 if ((i.types[op] & Reg8) != 0
2622 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2623 {
2624 as_bad (_("`%%%s' not allowed with `%s%c'"),
2625 i.op[op].regs->reg_name,
2626 i.tm.name,
2627 i.suffix);
2628 return 0;
2629 }
2630 /* Warn if the e prefix on a general reg is missing. */
2631 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2632 && (i.types[op] & Reg16) != 0
2633 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2634 {
2635 /* Prohibit these changes in the 64bit mode, since the
2636 lowering is more complicated. */
2637 if (flag_code == CODE_64BIT)
252b5132 2638 {
0f3f3d8b 2639 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2640 i.op[op].regs->reg_name,
2641 i.suffix);
2642 return 0;
252b5132 2643 }
29b0f896
AM		 2644#if REGISTER_WARNINGS
2645 else
2646 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2647 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2648 i.op[op].regs->reg_name,
2649 i.suffix);
2650#endif
252b5132 2651 }
29b0f896
AM		 2652 /* Warn if the r prefix on a general reg is missing. */
2653 else if ((i.types[op] & Reg64) != 0
2654 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2655 {
0f3f3d8b 2656 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2657 i.op[op].regs->reg_name,
2658 i.suffix);
2659 return 0;
2660 }
2661 return 1;
2662}
252b5132 2663
29b0f896
AM		 2664static int
2665check_qword_reg ()
2666{
2667 int op;
252b5132 2668
29b0f896
AM		 2669 for (op = i.operands; --op >= 0; )
2670 /* Reject eight bit registers, except where the template requires
2671 them. (eg. movzb) */
2672 if ((i.types[op] & Reg8) != 0
2673 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2674 {
2675 as_bad (_("`%%%s' not allowed with `%s%c'"),
2676 i.op[op].regs->reg_name,
2677 i.tm.name,
2678 i.suffix);
2679 return 0;
2680 }
2681 /* Warn if the e prefix on a general reg is missing. */
2682 else if (((i.types[op] & Reg16) != 0
2683 || (i.types[op] & Reg32) != 0)
2684 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2685 {
2686 /* Prohibit these changes in the 64bit mode, since the
2687 lowering is more complicated. */
0f3f3d8b 2688 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2689 i.op[op].regs->reg_name,
2690 i.suffix);
2691 return 0;
252b5132 2692 }
29b0f896
AM		 2693 return 1;
2694}
252b5132 2695
29b0f896
AM		 2696static int
2697check_word_reg ()
2698{
2699 int op;
2700 for (op = i.operands; --op >= 0;)
2701 /* Reject eight bit registers, except where the template requires
2702 them. (eg. movzb) */
2703 if ((i.types[op] & Reg8) != 0
2704 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2705 {
2706 as_bad (_("`%%%s' not allowed with `%s%c'"),
2707 i.op[op].regs->reg_name,
2708 i.tm.name,
2709 i.suffix);
2710 return 0;
2711 }
2712 /* Warn if the e prefix on a general reg is present. */
2713 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2714 && (i.types[op] & Reg32) != 0
2715 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2716 {
29b0f896
AM		 2717 /* Prohibit these changes in the 64bit mode, since the
2718 lowering is more complicated. */
2719 if (flag_code == CODE_64BIT)
252b5132 2720 {
0f3f3d8b 2721 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2722 i.op[op].regs->reg_name,
2723 i.suffix);
2724 return 0;
252b5132 2725 }
29b0f896
AM		 2726 else
2727#if REGISTER_WARNINGS
2728 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2729 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2730 i.op[op].regs->reg_name,
2731 i.suffix);
2732#endif
2733 }
2734 return 1;
2735}
252b5132 2736
29b0f896
AM		 2737static int
2738finalize_imm ()
2739{
2740 unsigned int overlap0, overlap1, overlap2;
2741
2742 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2743 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2744 && overlap0 != Imm8 && overlap0 != Imm8S
2745 && overlap0 != Imm16 && overlap0 != Imm32S
2746 && overlap0 != Imm32 && overlap0 != Imm64)
2747 {
2748 if (i.suffix)
2749 {
2750 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2751 ? Imm8 | Imm8S
2752 : (i.suffix == WORD_MNEM_SUFFIX
2753 ? Imm16
2754 : (i.suffix == QWORD_MNEM_SUFFIX
2755 ? Imm64 | Imm32S
2756 : Imm32)));
2757 }
2758 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2759 || overlap0 == (Imm16 | Imm32)
2760 || overlap0 == (Imm16 | Imm32S))
2761 {
2762 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2763 ? Imm16 : Imm32S);
2764 }
2765 if (overlap0 != Imm8 && overlap0 != Imm8S
2766 && overlap0 != Imm16 && overlap0 != Imm32S
2767 && overlap0 != Imm32 && overlap0 != Imm64)
2768 {
2769 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2770 return 0;
2771 }
2772 }
2773 i.types[0] = overlap0;
2774
2775 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2776 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2777 && overlap1 != Imm8 && overlap1 != Imm8S
2778 && overlap1 != Imm16 && overlap1 != Imm32S
2779 && overlap1 != Imm32 && overlap1 != Imm64)
2780 {
2781 if (i.suffix)
2782 {
2783 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2784 ? Imm8 | Imm8S
2785 : (i.suffix == WORD_MNEM_SUFFIX
2786 ? Imm16
2787 : (i.suffix == QWORD_MNEM_SUFFIX
2788 ? Imm64 | Imm32S
2789 : Imm32)));
2790 }
2791 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2792 || overlap1 == (Imm16 | Imm32)
2793 || overlap1 == (Imm16 | Imm32S))
2794 {
2795 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2796 ? Imm16 : Imm32S);
2797 }
2798 if (overlap1 != Imm8 && overlap1 != Imm8S
2799 && overlap1 != Imm16 && overlap1 != Imm32S
2800 && overlap1 != Imm32 && overlap1 != Imm64)
2801 {
2802 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2803 return 0;
2804 }
2805 }
2806 i.types[1] = overlap1;
2807
2808 overlap2 = i.types[2] & i.tm.operand_types[2];
2809 assert ((overlap2 & Imm) == 0);
2810 i.types[2] = overlap2;
2811
2812 return 1;
2813}
2814
2815static int
2816process_operands ()
2817{
2818 /* Default segment register this instruction will use for memory
2819 accesses. 0 means unknown. This is only for optimizing out
2820 unnecessary segment overrides. */
2821 const seg_entry *default_seg = 0;
2822
2823 /* The imul $imm, %reg instruction is converted into
2824 imul $imm, %reg, %reg, and the clr %reg instruction
2825 is converted into xor %reg, %reg. */
2826 if (i.tm.opcode_modifier & regKludge)
2827 {
2828 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2829 /* Pretend we saw the extra register operand. */
2830 assert (i.op[first_reg_op + 1].regs == 0);
2831 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2832 i.types[first_reg_op + 1] = i.types[first_reg_op];
2833 i.reg_operands = 2;
2834 }
2835
2836 if (i.tm.opcode_modifier & ShortForm)
2837 {
2838 /* The register or float register operand is in operand 0 or 1. */
2839 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2840 /* Register goes in low 3 bits of opcode. */
2841 i.tm.base_opcode |= i.op[op].regs->reg_num;
2842 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2843 i.rex |= REX_EXTZ;
2844 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2845 {
2846 /* Warn about some common errors, but press on regardless.
2847 The first case can be generated by gcc (<= 2.8.1). */
2848 if (i.operands == 2)
2849 {
2850 /* Reversed arguments on faddp, fsubp, etc. */
2851 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2852 i.op[1].regs->reg_name,
2853 i.op[0].regs->reg_name);
2854 }
2855 else
2856 {
2857 /* Extraneous `l' suffix on fp insn. */
2858 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2859 i.op[0].regs->reg_name);
2860 }
2861 }
2862 }
2863 else if (i.tm.opcode_modifier & Modrm)
2864 {
2865 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 2866 must be put into the modrm byte). Now, we make the modrm and
2867 index base bytes based on all the info we've collected. */
29b0f896
AM		 2868
2869 default_seg = build_modrm_byte ();
2870 }
2871 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2872 {
2873 if (i.tm.base_opcode == POP_SEG_SHORT
2874 && i.op[0].regs->reg_num == 1)
2875 {
2876 as_bad (_("you can't `pop %%cs'"));
2877 return 0;
2878 }
2879 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2880 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2881 i.rex |= REX_EXTZ;
2882 }
2883 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2884 {
2885 default_seg = &ds;
2886 }
2887 else if ((i.tm.opcode_modifier & IsString) != 0)
2888 {
2889 /* For the string instructions that allow a segment override
2890 on one of their operands, the default segment is ds. */
2891 default_seg = &ds;
2892 }
2893
30123838
JB		 2894 if ((i.tm.base_opcode == 0x8d /* lea */
2895 || (i.tm.cpu_flags & CpuSVME))
2896 && i.seg[0] && !quiet_warnings)
2897 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 2898
2899 /* If a segment was explicitly specified, and the specified segment
2900 is not the default, use an opcode prefix to select it. If we
2901 never figured out what the default segment is, then default_seg
2902 will be zero at this point, and the specified segment prefix will
2903 always be used. */
29b0f896
AM		 2904 if ((i.seg[0]) && (i.seg[0] != default_seg))
2905 {
2906 if (!add_prefix (i.seg[0]->seg_prefix))
2907 return 0;
2908 }
2909 return 1;
2910}
2911
2912static const seg_entry *
2913build_modrm_byte ()
2914{
2915 const seg_entry *default_seg = 0;
2916
2917 /* i.reg_operands MUST be the number of real register operands;
2918 implicit registers do not count. */
2919 if (i.reg_operands == 2)
2920 {
2921 unsigned int source, dest;
2922 source = ((i.types[0]
2923 & (Reg | RegMMX | RegXMM
2924 | SReg2 | SReg3
2925 | Control | Debug | Test))
2926 ? 0 : 1);
2927 dest = source + 1;
2928
2929 i.rm.mode = 3;
2930 /* One of the register operands will be encoded in the i.tm.reg
2931 field, the other in the combined i.tm.mode and i.tm.regmem
2932 fields. If no form of this instruction supports a memory
2933 destination operand, then we assume the source operand may
2934 sometimes be a memory operand and so we need to store the
2935 destination in the i.rm.reg field. */
2936 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2937 {
2938 i.rm.reg = i.op[dest].regs->reg_num;
2939 i.rm.regmem = i.op[source].regs->reg_num;
2940 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2941 i.rex |= REX_EXTX;
2942 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2943 i.rex |= REX_EXTZ;
2944 }
2945 else
2946 {
2947 i.rm.reg = i.op[source].regs->reg_num;
2948 i.rm.regmem = i.op[dest].regs->reg_num;
2949 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2950 i.rex |= REX_EXTZ;
2951 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2952 i.rex |= REX_EXTX;
2953 }
c4a530c5
JB		 2954 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
2955 {
2956 if (!((i.types[0] | i.types[1]) & Control))
2957 abort ();
2958 i.rex &= ~(REX_EXTX | REX_EXTZ);
2959 add_prefix (LOCK_PREFIX_OPCODE);
2960 }
29b0f896
AM		 2961 }
2962 else
2963 { /* If it's not 2 reg operands... */
2964 if (i.mem_operands)
2965 {
2966 unsigned int fake_zero_displacement = 0;
2967 unsigned int op = ((i.types[0] & AnyMem)
2968 ? 0
2969 : (i.types[1] & AnyMem) ? 1 : 2);
2970
2971 default_seg = &ds;
2972
2973 if (i.base_reg == 0)
2974 {
2975 i.rm.mode = 0;
2976 if (!i.disp_operands)
2977 fake_zero_displacement = 1;
2978 if (i.index_reg == 0)
2979 {
2980 /* Operand is just <disp> */
20f0a1fc 2981 if (flag_code == CODE_64BIT)
29b0f896
AM		 2982 {
2983 /* 64bit mode overwrites the 32bit absolute
2984 addressing by RIP relative addressing and
2985 absolute addressing is encoded by one of the
2986 redundant SIB forms. */
2987 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2988 i.sib.base = NO_BASE_REGISTER;
2989 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 2990 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
2991 }
2992 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
2993 {
2994 i.rm.regmem = NO_BASE_REGISTER_16;
2995 i.types[op] = Disp16;
2996 }
2997 else
2998 {
2999 i.rm.regmem = NO_BASE_REGISTER;
3000 i.types[op] = Disp32;
29b0f896
AM		 3001 }
3002 }
3003 else /* !i.base_reg && i.index_reg */
3004 {
3005 i.sib.index = i.index_reg->reg_num;
3006 i.sib.base = NO_BASE_REGISTER;
3007 i.sib.scale = i.log2_scale_factor;
3008 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3009 i.types[op] &= ~Disp;
3010 if (flag_code != CODE_64BIT)
3011 i.types[op] |= Disp32; /* Must be 32 bit */
3012 else
3013 i.types[op] |= Disp32S;
3014 if ((i.index_reg->reg_flags & RegRex) != 0)
3015 i.rex |= REX_EXTY;
3016 }
3017 }
3018 /* RIP addressing for 64bit mode. */
3019 else if (i.base_reg->reg_type == BaseIndex)
3020 {
3021 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3022 i.types[op] &= ~ Disp;
29b0f896
AM		 3023 i.types[op] |= Disp32S;
3024 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3025 if (! i.disp_operands)
3026 fake_zero_displacement = 1;
29b0f896
AM		 3027 }
3028 else if (i.base_reg->reg_type & Reg16)
3029 {
3030 switch (i.base_reg->reg_num)
3031 {
3032 case 3: /* (%bx) */
3033 if (i.index_reg == 0)
3034 i.rm.regmem = 7;
3035 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3036 i.rm.regmem = i.index_reg->reg_num - 6;
3037 break;
3038 case 5: /* (%bp) */
3039 default_seg = &ss;
3040 if (i.index_reg == 0)
3041 {
3042 i.rm.regmem = 6;
3043 if ((i.types[op] & Disp) == 0)
3044 {
3045 /* fake (%bp) into 0(%bp) */
3046 i.types[op] |= Disp8;
252b5132 3047 fake_zero_displacement = 1;
29b0f896
AM		 3048 }
3049 }
3050 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3051 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3052 break;
3053 default: /* (%si) -> 4 or (%di) -> 5 */
3054 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3055 }
3056 i.rm.mode = mode_from_disp_size (i.types[op]);
3057 }
3058 else /* i.base_reg and 32/64 bit mode */
3059 {
3060 if (flag_code == CODE_64BIT
3061 && (i.types[op] & Disp))
20f0a1fc
NC		 3062 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3063
29b0f896
AM		 3064 i.rm.regmem = i.base_reg->reg_num;
3065 if ((i.base_reg->reg_flags & RegRex) != 0)
3066 i.rex |= REX_EXTZ;
3067 i.sib.base = i.base_reg->reg_num;
3068 /* x86-64 ignores REX prefix bit here to avoid decoder
3069 complications. */
3070 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3071 {
3072 default_seg = &ss;
3073 if (i.disp_operands == 0)
3074 {
3075 fake_zero_displacement = 1;
3076 i.types[op] |= Disp8;
3077 }
3078 }
3079 else if (i.base_reg->reg_num == ESP_REG_NUM)
3080 {
3081 default_seg = &ss;
3082 }
3083 i.sib.scale = i.log2_scale_factor;
3084 if (i.index_reg == 0)
3085 {
3086 /* <disp>(%esp) becomes two byte modrm with no index
3087 register. We've already stored the code for esp
3088 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3089 Any base register besides %esp will not use the
3090 extra modrm byte. */
3091 i.sib.index = NO_INDEX_REGISTER;
3092#if !SCALE1_WHEN_NO_INDEX
3093 /* Another case where we force the second modrm byte. */
3094 if (i.log2_scale_factor)
3095 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3096#endif
29b0f896
AM		 3097 }
3098 else
3099 {
3100 i.sib.index = i.index_reg->reg_num;
3101 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3102 if ((i.index_reg->reg_flags & RegRex) != 0)
3103 i.rex |= REX_EXTY;
3104 }
3105 i.rm.mode = mode_from_disp_size (i.types[op]);
3106 }
252b5132 3107
29b0f896
AM		 3108 if (fake_zero_displacement)
3109 {
3110 /* Fakes a zero displacement assuming that i.types[op]
3111 holds the correct displacement size. */
3112 expressionS *exp;
3113
3114 assert (i.op[op].disps == 0);
3115 exp = &disp_expressions[i.disp_operands++];
3116 i.op[op].disps = exp;
3117 exp->X_op = O_constant;
3118 exp->X_add_number = 0;
3119 exp->X_add_symbol = (symbolS *) 0;
3120 exp->X_op_symbol = (symbolS *) 0;
3121 }
3122 }
252b5132 3123
29b0f896
AM		 3124 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3125 (if any) based on i.tm.extension_opcode. Again, we must be
3126 careful to make sure that segment/control/debug/test/MMX
3127 registers are coded into the i.rm.reg field. */
3128 if (i.reg_operands)
3129 {
3130 unsigned int op =
3131 ((i.types[0]
3132 & (Reg | RegMMX | RegXMM
3133 | SReg2 | SReg3
3134 | Control | Debug | Test))
3135 ? 0
3136 : ((i.types[1]
3137 & (Reg | RegMMX | RegXMM
3138 | SReg2 | SReg3
3139 | Control | Debug | Test))
3140 ? 1
3141 : 2));
3142 /* If there is an extension opcode to put here, the register
3143 number must be put into the regmem field. */
3144 if (i.tm.extension_opcode != None)
3145 {
3146 i.rm.regmem = i.op[op].regs->reg_num;
3147 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3148 i.rex |= REX_EXTZ;
3149 }
3150 else
3151 {
3152 i.rm.reg = i.op[op].regs->reg_num;
3153 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3154 i.rex |= REX_EXTX;
3155 }
252b5132 3156
29b0f896
AM		 3157 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3158 must set it to 3 to indicate this is a register operand
3159 in the regmem field. */
3160 if (!i.mem_operands)
3161 i.rm.mode = 3;
3162 }
252b5132 3163
29b0f896
AM		 3164 /* Fill in i.rm.reg field with extension opcode (if any). */
3165 if (i.tm.extension_opcode != None)
3166 i.rm.reg = i.tm.extension_opcode;
3167 }
3168 return default_seg;
3169}
252b5132 3170
29b0f896
AM		 3171static void
3172output_branch ()
3173{
3174 char *p;
3175 int code16;
3176 int prefix;
3177 relax_substateT subtype;
3178 symbolS *sym;
3179 offsetT off;
3180
3181 code16 = 0;
3182 if (flag_code == CODE_16BIT)
3183 code16 = CODE16;
3184
3185 prefix = 0;
3186 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3187 {
29b0f896
AM		 3188 prefix = 1;
3189 i.prefixes -= 1;
3190 code16 ^= CODE16;
252b5132 3191 }
29b0f896
AM		 3192 /* Pentium4 branch hints. */
3193 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3194 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3195 {
29b0f896
AM		 3196 prefix++;
3197 i.prefixes--;
3198 }
3199 if (i.prefix[REX_PREFIX] != 0)
3200 {
3201 prefix++;
3202 i.prefixes--;
2f66722d
AM		 3203 }
3204
29b0f896
AM		 3205 if (i.prefixes != 0 && !intel_syntax)
3206 as_warn (_("skipping prefixes on this instruction"));
3207
3208 /* It's always a symbol; End frag & setup for relax.
3209 Make sure there is enough room in this frag for the largest
3210 instruction we may generate in md_convert_frag. This is 2
3211 bytes for the opcode and room for the prefix and largest
3212 displacement. */
3213 frag_grow (prefix + 2 + 4);
3214 /* Prefix and 1 opcode byte go in fr_fix. */
3215 p = frag_more (prefix + 1);
3216 if (i.prefix[DATA_PREFIX] != 0)
3217 *p++ = DATA_PREFIX_OPCODE;
3218 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3219 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3220 *p++ = i.prefix[SEG_PREFIX];
3221 if (i.prefix[REX_PREFIX] != 0)
3222 *p++ = i.prefix[REX_PREFIX];
3223 *p = i.tm.base_opcode;
3224
3225 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3226 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3227 else if ((cpu_arch_flags & Cpu386) != 0)
3228 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3229 else
3230 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3231 subtype |= code16;
3e73aa7c 3232
29b0f896
AM		 3233 sym = i.op[0].disps->X_add_symbol;
3234 off = i.op[0].disps->X_add_number;
3e73aa7c 3235
29b0f896
AM		 3236 if (i.op[0].disps->X_op != O_constant
3237 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3238 {
29b0f896
AM		 3239 /* Handle complex expressions. */
3240 sym = make_expr_symbol (i.op[0].disps);
3241 off = 0;
3242 }
3e73aa7c 3243
29b0f896
AM		 3244 /* 1 possible extra opcode + 4 byte displacement go in var part.
3245 Pass reloc in fr_var. */
3246 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3247}
3e73aa7c 3248
29b0f896
AM		 3249static void
3250output_jump ()
3251{
3252 char *p;
3253 int size;
3e02c1cc 3254 fixS *fixP;
29b0f896
AM		 3255
3256 if (i.tm.opcode_modifier & JumpByte)
3257 {
3258 /* This is a loop or jecxz type instruction. */
3259 size = 1;
3260 if (i.prefix[ADDR_PREFIX] != 0)
3261 {
3262 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3263 i.prefixes -= 1;
3264 }
3265 /* Pentium4 branch hints. */
3266 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3267 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3268 {
3269 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3270 i.prefixes--;
3e73aa7c
JH		 3271 }
3272 }
29b0f896
AM		 3273 else
3274 {
3275 int code16;
3e73aa7c 3276
29b0f896
AM		 3277 code16 = 0;
3278 if (flag_code == CODE_16BIT)
3279 code16 = CODE16;
3e73aa7c 3280
29b0f896
AM		 3281 if (i.prefix[DATA_PREFIX] != 0)
3282 {
3283 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3284 i.prefixes -= 1;
3285 code16 ^= CODE16;
3286 }
252b5132 3287
29b0f896
AM		 3288 size = 4;
3289 if (code16)
3290 size = 2;
3291 }
9fcc94b6 3292
29b0f896
AM		 3293 if (i.prefix[REX_PREFIX] != 0)
3294 {
3295 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3296 i.prefixes -= 1;
3297 }
252b5132 3298
29b0f896
AM		 3299 if (i.prefixes != 0 && !intel_syntax)
3300 as_warn (_("skipping prefixes on this instruction"));
e0890092 3301
29b0f896
AM		 3302 p = frag_more (1 + size);
3303 *p++ = i.tm.base_opcode;
e0890092 3304
3e02c1cc
AM		 3305 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3306 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3307
3308 /* All jumps handled here are signed, but don't use a signed limit
3309 check for 32 and 16 bit jumps as we want to allow wrap around at
3310 4G and 64k respectively. */
3311 if (size == 1)
3312 fixP->fx_signed = 1;
29b0f896 3313}
e0890092 3314
29b0f896
AM		 3315static void
3316output_interseg_jump ()
3317{
3318 char *p;
3319 int size;
3320 int prefix;
3321 int code16;
252b5132 3322
29b0f896
AM		 3323 code16 = 0;
3324 if (flag_code == CODE_16BIT)
3325 code16 = CODE16;
a217f122 3326
29b0f896
AM		 3327 prefix = 0;
3328 if (i.prefix[DATA_PREFIX] != 0)
3329 {
3330 prefix = 1;
3331 i.prefixes -= 1;
3332 code16 ^= CODE16;
3333 }
3334 if (i.prefix[REX_PREFIX] != 0)
3335 {
3336 prefix++;
3337 i.prefixes -= 1;
3338 }
252b5132 3339
29b0f896
AM		 3340 size = 4;
3341 if (code16)
3342 size = 2;
252b5132 3343
29b0f896
AM		 3344 if (i.prefixes != 0 && !intel_syntax)
3345 as_warn (_("skipping prefixes on this instruction"));
252b5132 3346
29b0f896
AM		 3347 /* 1 opcode; 2 segment; offset */
3348 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3349
29b0f896
AM		 3350 if (i.prefix[DATA_PREFIX] != 0)
3351 *p++ = DATA_PREFIX_OPCODE;
252b5132 3352
29b0f896
AM		 3353 if (i.prefix[REX_PREFIX] != 0)
3354 *p++ = i.prefix[REX_PREFIX];
252b5132 3355
29b0f896
AM		 3356 *p++ = i.tm.base_opcode;
3357 if (i.op[1].imms->X_op == O_constant)
3358 {
3359 offsetT n = i.op[1].imms->X_add_number;
252b5132 3360
29b0f896
AM		 3361 if (size == 2
3362 && !fits_in_unsigned_word (n)
3363 && !fits_in_signed_word (n))
3364 {
3365 as_bad (_("16-bit jump out of range"));
3366 return;
3367 }
3368 md_number_to_chars (p, n, size);
3369 }
3370 else
3371 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3372 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3373 if (i.op[0].imms->X_op != O_constant)
3374 as_bad (_("can't handle non absolute segment in `%s'"),
3375 i.tm.name);
3376 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3377}
a217f122 3378
29b0f896
AM		 3379static void
3380output_insn ()
3381{
2bbd9c25
JJ		 3382 fragS *insn_start_frag;
3383 offsetT insn_start_off;
3384
29b0f896
AM		 3385 /* Tie dwarf2 debug info to the address at the start of the insn.
3386 We can't do this after the insn has been output as the current
3387 frag may have been closed off. eg. by frag_var. */
3388 dwarf2_emit_insn (0);
3389
2bbd9c25
JJ		 3390 insn_start_frag = frag_now;
3391 insn_start_off = frag_now_fix ();
3392
29b0f896
AM		 3393 /* Output jumps. */
3394 if (i.tm.opcode_modifier & Jump)
3395 output_branch ();
3396 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3397 output_jump ();
3398 else if (i.tm.opcode_modifier & JumpInterSegment)
3399 output_interseg_jump ();
3400 else
3401 {
3402 /* Output normal instructions here. */
3403 char *p;
3404 unsigned char *q;
252b5132 3405
bc4bd9ab
MK		 3406 /* All opcodes on i386 have either 1 or 2 bytes. We may use one
3407 more higher byte to specify a prefix the instruction
3408 requires. */
3409 if ((i.tm.base_opcode & 0xff0000) != 0)
3410 {
3411 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3412 {
3413 unsigned int prefix;
3414 prefix = (i.tm.base_opcode >> 16) & 0xff;
3415
3416 if (prefix != REPE_PREFIX_OPCODE
3417 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3418 add_prefix (prefix);
3419 }
3420 else
3421 add_prefix ((i.tm.base_opcode >> 16) & 0xff);
0f10071e 3422 }
252b5132 3423
29b0f896
AM		 3424 /* The prefix bytes. */
3425 for (q = i.prefix;
3426 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3427 q++)
3428 {
3429 if (*q)
3430 {
3431 p = frag_more (1);
3432 md_number_to_chars (p, (valueT) *q, 1);
3433 }
3434 }
252b5132 3435
29b0f896
AM		 3436 /* Now the opcode; be careful about word order here! */
3437 if (fits_in_unsigned_byte (i.tm.base_opcode))
3438 {
3439 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3440 }
3441 else
3442 {
bc4bd9ab 3443 p = frag_more (2);
0f10071e 3444
29b0f896
AM		 3445 /* Put out high byte first: can't use md_number_to_chars! */
3446 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3447 *p = i.tm.base_opcode & 0xff;
3448 }
3e73aa7c 3449
29b0f896
AM		 3450 /* Now the modrm byte and sib byte (if present). */
3451 if (i.tm.opcode_modifier & Modrm)
3452 {
3453 p = frag_more (1);
3454 md_number_to_chars (p,
3455 (valueT) (i.rm.regmem << 0
3456 | i.rm.reg << 3
3457 | i.rm.mode << 6),
3458 1);
3459 /* If i.rm.regmem == ESP (4)
3460 && i.rm.mode != (Register mode)
3461 && not 16 bit
3462 ==> need second modrm byte. */
3463 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3464 && i.rm.mode != 3
3465 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3466 {
3467 p = frag_more (1);
3468 md_number_to_chars (p,
3469 (valueT) (i.sib.base << 0
3470 | i.sib.index << 3
3471 | i.sib.scale << 6),
3472 1);
3473 }
3474 }
3e73aa7c 3475
29b0f896 3476 if (i.disp_operands)
2bbd9c25 3477 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3478
29b0f896 3479 if (i.imm_operands)
2bbd9c25 3480 output_imm (insn_start_frag, insn_start_off);
29b0f896 3481 }
252b5132 3482
29b0f896
AM		 3483#ifdef DEBUG386
3484 if (flag_debug)
3485 {
3486 pi (line, &i);
3487 }
3488#endif /* DEBUG386 */
3489}
252b5132 3490
29b0f896 3491static void
2bbd9c25
JJ		 3492output_disp (insn_start_frag, insn_start_off)
3493 fragS *insn_start_frag;
3494 offsetT insn_start_off;
29b0f896
AM		 3495{
3496 char *p;
3497 unsigned int n;
252b5132 3498
29b0f896
AM		 3499 for (n = 0; n < i.operands; n++)
3500 {
3501 if (i.types[n] & Disp)
3502 {
3503 if (i.op[n].disps->X_op == O_constant)
3504 {
3505 int size;
3506 offsetT val;
252b5132 3507
29b0f896
AM		 3508 size = 4;
3509 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3510 {
3511 size = 2;
3512 if (i.types[n] & Disp8)
3513 size = 1;
3514 if (i.types[n] & Disp64)
3515 size = 8;
3516 }
3517 val = offset_in_range (i.op[n].disps->X_add_number,
3518 size);
3519 p = frag_more (size);
3520 md_number_to_chars (p, val, size);
3521 }
3522 else
3523 {
f86103b7 3524 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3525 int size = 4;
3526 int sign = 0;
3527 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3528
3529 /* The PC relative address is computed relative
3530 to the instruction boundary, so in case immediate
3531 fields follows, we need to adjust the value. */
3532 if (pcrel && i.imm_operands)
3533 {
3534 int imm_size = 4;
3535 unsigned int n1;
252b5132 3536
29b0f896
AM		 3537 for (n1 = 0; n1 < i.operands; n1++)
3538 if (i.types[n1] & Imm)
252b5132 3539 {
29b0f896 3540 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3541 {
29b0f896
AM		 3542 imm_size = 2;
3543 if (i.types[n1] & (Imm8 | Imm8S))
3544 imm_size = 1;
3545 if (i.types[n1] & Imm64)
3546 imm_size = 8;
252b5132 3547 }
29b0f896 3548 break;
252b5132 3549 }
29b0f896
AM		 3550 /* We should find the immediate. */
3551 if (n1 == i.operands)
3552 abort ();
3553 i.op[n].disps->X_add_number -= imm_size;
3554 }
520dc8e8 3555
29b0f896
AM		 3556 if (i.types[n] & Disp32S)
3557 sign = 1;
3e73aa7c 3558
29b0f896
AM		 3559 if (i.types[n] & (Disp16 | Disp64))
3560 {
3561 size = 2;
3562 if (i.types[n] & Disp64)
3563 size = 8;
3564 }
520dc8e8 3565
29b0f896 3566 p = frag_more (size);
2bbd9c25 3567 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3568 if (GOT_symbol
2bbd9c25 3569 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113
JB		 3570 && (((reloc_type == BFD_RELOC_32
3571 || reloc_type == BFD_RELOC_X86_64_32S)
3572 && (i.op[n].disps->X_op == O_symbol
3573 || (i.op[n].disps->X_op == O_add
3574 && ((symbol_get_value_expression
3575 (i.op[n].disps->X_op_symbol)->X_op)
3576 == O_subtract))))
3577 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3578 {
3579 offsetT add;
3580
3581 if (insn_start_frag == frag_now)
3582 add = (p - frag_now->fr_literal) - insn_start_off;
3583 else
3584 {
3585 fragS *fr;
3586
3587 add = insn_start_frag->fr_fix - insn_start_off;
3588 for (fr = insn_start_frag->fr_next;
3589 fr && fr != frag_now; fr = fr->fr_next)
3590 add += fr->fr_fix;
3591 add += p - frag_now->fr_literal;
3592 }
3593
d6ab8113
JB		 3594 if (flag_code != CODE_64BIT)
3595 reloc_type = BFD_RELOC_386_GOTPC;
3596 else
3597 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25
JJ		 3598 i.op[n].disps->X_add_number += add;
3599 }
062cd5e7 3600 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3601 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3602 }
3603 }
3604 }
3605}
252b5132 3606
29b0f896 3607static void
2bbd9c25
JJ		 3608output_imm (insn_start_frag, insn_start_off)
3609 fragS *insn_start_frag;
3610 offsetT insn_start_off;
29b0f896
AM		 3611{
3612 char *p;
3613 unsigned int n;
252b5132 3614
29b0f896
AM		 3615 for (n = 0; n < i.operands; n++)
3616 {
3617 if (i.types[n] & Imm)
3618 {
3619 if (i.op[n].imms->X_op == O_constant)
3620 {
3621 int size;
3622 offsetT val;
b4cac588 3623
29b0f896
AM		 3624 size = 4;
3625 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3626 {
3627 size = 2;
3628 if (i.types[n] & (Imm8 | Imm8S))
3629 size = 1;
3630 else if (i.types[n] & Imm64)
3631 size = 8;
3632 }
3633 val = offset_in_range (i.op[n].imms->X_add_number,
3634 size);
3635 p = frag_more (size);
3636 md_number_to_chars (p, val, size);
3637 }
3638 else
3639 {
3640 /* Not absolute_section.
3641 Need a 32-bit fixup (don't support 8bit
3642 non-absolute imms). Try to support other
3643 sizes ... */
f86103b7 3644 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3645 int size = 4;
3646 int sign = 0;
3647
3648 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3649 && (i.suffix == QWORD_MNEM_SUFFIX
3650 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3651 sign = 1;
3652 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3653 {
3654 size = 2;
3655 if (i.types[n] & (Imm8 | Imm8S))
3656 size = 1;
3657 if (i.types[n] & Imm64)
3658 size = 8;
3659 }
520dc8e8 3660
29b0f896
AM		 3661 p = frag_more (size);
3662 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3663
2bbd9c25
JJ		 3664 /* This is tough to explain. We end up with this one if we
3665 * have operands that look like
3666 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3667 * obtain the absolute address of the GOT, and it is strongly
3668 * preferable from a performance point of view to avoid using
3669 * a runtime relocation for this. The actual sequence of
3670 * instructions often look something like:
3671 *
3672 * call .L66
3673 * .L66:
3674 * popl %ebx
3675 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3676 *
3677 * The call and pop essentially return the absolute address
3678 * of the label .L66 and store it in %ebx. The linker itself
3679 * will ultimately change the first operand of the addl so
3680 * that %ebx points to the GOT, but to keep things simple, the
3681 * .o file must have this operand set so that it generates not
3682 * the absolute address of .L66, but the absolute address of
3683 * itself. This allows the linker itself simply treat a GOTPC
3684 * relocation as asking for a pcrel offset to the GOT to be
3685 * added in, and the addend of the relocation is stored in the
3686 * operand field for the instruction itself.
3687 *
3688 * Our job here is to fix the operand so that it would add
3689 * the correct offset so that %ebx would point to itself. The
3690 * thing that is tricky is that .-.L66 will point to the
3691 * beginning of the instruction, so we need to further modify
3692 * the operand so that it will point to itself. There are
3693 * other cases where you have something like:
3694 *
3695 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3696 *
3697 * and here no correction would be required. Internally in
3698 * the assembler we treat operands of this form as not being
3699 * pcrel since the '.' is explicitly mentioned, and I wonder
3700 * whether it would simplify matters to do it this way. Who
3701 * knows. In earlier versions of the PIC patches, the
3702 * pcrel_adjust field was used to store the correction, but
3703 * since the expression is not pcrel, I felt it would be
3704 * confusing to do it this way. */
3705
d6ab8113
JB		 3706 if ((reloc_type == BFD_RELOC_32
3707 || reloc_type == BFD_RELOC_X86_64_32S)
29b0f896
AM		 3708 && GOT_symbol
3709 && GOT_symbol == i.op[n].imms->X_add_symbol
3710 && (i.op[n].imms->X_op == O_symbol
3711 || (i.op[n].imms->X_op == O_add
3712 && ((symbol_get_value_expression
3713 (i.op[n].imms->X_op_symbol)->X_op)
3714 == O_subtract))))
3715 {
2bbd9c25
JJ		 3716 offsetT add;
3717
3718 if (insn_start_frag == frag_now)
3719 add = (p - frag_now->fr_literal) - insn_start_off;
3720 else
3721 {
3722 fragS *fr;
3723
3724 add = insn_start_frag->fr_fix - insn_start_off;
3725 for (fr = insn_start_frag->fr_next;
3726 fr && fr != frag_now; fr = fr->fr_next)
3727 add += fr->fr_fix;
3728 add += p - frag_now->fr_literal;
3729 }
3730
d6ab8113
JB		 3731 if (flag_code != CODE_64BIT)
3732 reloc_type = BFD_RELOC_386_GOTPC;
3733 else
3734 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3735 i.op[n].imms->X_add_number += add;
29b0f896 3736 }
29b0f896
AM		 3737 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3738 i.op[n].imms, 0, reloc_type);
3739 }
3740 }
3741 }
252b5132
RH		 3742}
3743\f
f3c180ae 3744#ifndef LEX_AT
f3c180ae
AM		 3745/* Parse operands of the form
3746 <symbol>@GOTOFF+<nnn>
3747 and similar .plt or .got references.
3748
3749 If we find one, set up the correct relocation in RELOC and copy the
3750 input string, minus the `@GOTOFF' into a malloc'd buffer for
3751 parsing by the calling routine. Return this buffer, and if ADJUST
3752 is non-null set it to the length of the string we removed from the
3753 input line. Otherwise return NULL. */
3754static char *
3956db08
JB		 3755lex_got (enum bfd_reloc_code_real *reloc,
3756 int *adjust,
3757 unsigned int *types)
f3c180ae
AM		 3758{
3759 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3760 static const struct {
3761 const char *str;
f86103b7 3762 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3956db08 3763 const unsigned int types64;
f3c180ae 3764 } gotrel[] = {
3956db08
JB		 3765 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
3766 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3767 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3768 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3769 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 }, 0 },
3770 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3771 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3772 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3773 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 }, 0 },
3774 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3775 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 }, 0 },
3776 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 }, 0 },
3777 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3778 };
3779 char *cp;
3780 unsigned int j;
3781
3782 for (cp = input_line_pointer; *cp != '@'; cp++)
3783 if (is_end_of_line[(unsigned char) *cp])
3784 return NULL;
3785
3786 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3787 {
3788 int len;
3789
3790 len = strlen (gotrel[j].str);
28f81592 3791 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae
AM		 3792 {
3793 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3794 {
28f81592
AM		 3795 int first, second;
3796 char *tmpbuf, *past_reloc;
f3c180ae
AM		 3797
3798 *reloc = gotrel[j].rel[(unsigned int) flag_code];
28f81592
AM		 3799 if (adjust)
3800 *adjust = len;
f3c180ae 3801
3956db08
JB		 3802 if (types)
3803 {
3804 if (flag_code != CODE_64BIT)
3805 *types = Imm32|Disp32;
3806 else
3807 *types = gotrel[j].types64;
3808 }
3809
f3c180ae
AM		 3810 if (GOT_symbol == NULL)
3811 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3812
3813 /* Replace the relocation token with ' ', so that
3814 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 3815
3816 /* The length of the first part of our input line. */
f3c180ae 3817 first = cp - input_line_pointer;
28f81592
AM		 3818
3819 /* The second part goes from after the reloc token until
3820 (and including) an end_of_line char. Don't use strlen
3821 here as the end_of_line char may not be a NUL. */
3822 past_reloc = cp + 1 + len;
3823 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3824 ;
3825 second = cp - past_reloc;
3826
3827 /* Allocate and copy string. The trailing NUL shouldn't
3828 be necessary, but be safe. */
3829 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 3830 memcpy (tmpbuf, input_line_pointer, first);
3831 tmpbuf[first] = ' ';
28f81592
AM		 3832 memcpy (tmpbuf + first + 1, past_reloc, second);
3833 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 3834 return tmpbuf;
3835 }
3836
3837 as_bad (_("@%s reloc is not supported in %s bit mode"),
3838 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3839 return NULL;
3840 }
3841 }
3842
3843 /* Might be a symbol version string. Don't as_bad here. */
3844 return NULL;
3845}
3846
3847/* x86_cons_fix_new is called via the expression parsing code when a
3848 reloc is needed. We use this hook to get the correct .got reloc. */
f86103b7 3849static enum bfd_reloc_code_real got_reloc = NO_RELOC;
f3c180ae
AM		 3850
3851void
3852x86_cons_fix_new (frag, off, len, exp)
3853 fragS *frag;
3854 unsigned int off;
3855 unsigned int len;
3856 expressionS *exp;
3857{
3956db08 3858 enum bfd_reloc_code_real r = reloc (len, 0, -1, got_reloc);
f3c180ae
AM		 3859 got_reloc = NO_RELOC;
3860 fix_new_exp (frag, off, len, exp, 0, r);
3861}
3862
3863void
3864x86_cons (exp, size)
3865 expressionS *exp;
3866 int size;
3867{
d6ab8113 3868 if (size == 4 || (flag_code == CODE_64BIT && size == 8))
f3c180ae
AM		 3869 {
3870 /* Handle @GOTOFF and the like in an expression. */
3871 char *save;
3872 char *gotfree_input_line;
3873 int adjust;
3874
3875 save = input_line_pointer;
3956db08 3876 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 3877 if (gotfree_input_line)
3878 input_line_pointer = gotfree_input_line;
3879
3880 expression (exp);
3881
3882 if (gotfree_input_line)
3883 {
3884 /* expression () has merrily parsed up to the end of line,
3885 or a comma - in the wrong buffer. Transfer how far
3886 input_line_pointer has moved to the right buffer. */
3887 input_line_pointer = (save
3888 + (input_line_pointer - gotfree_input_line)
3889 + adjust);
3890 free (gotfree_input_line);
3891 }
3892 }
3893 else
3894 expression (exp);
3895}
3896#endif
3897
6482c264
NC		 3898#ifdef TE_PE
3899
6482c264
NC		 3900void
3901x86_pe_cons_fix_new (frag, off, len, exp)
3902 fragS *frag;
3903 unsigned int off;
3904 unsigned int len;
3905 expressionS *exp;
3906{
3956db08 3907 enum bfd_reloc_code_real r = reloc (len, 0, -1, NO_RELOC);
6482c264
NC		 3908
3909 if (exp->X_op == O_secrel)
3910 {
3911 exp->X_op = O_symbol;
3912 r = BFD_RELOC_32_SECREL;
3913 }
3914
3915 fix_new_exp (frag, off, len, exp, 0, r);
3916}
3917
3918static void
3919pe_directive_secrel (dummy)
3920 int dummy ATTRIBUTE_UNUSED;
3921{
3922 expressionS exp;
3923
3924 do
3925 {
3926 expression (&exp);
3927 if (exp.X_op == O_symbol)
3928 exp.X_op = O_secrel;
3929
3930 emit_expr (&exp, 4);
3931 }
3932 while (*input_line_pointer++ == ',');
3933
3934 input_line_pointer--;
3935 demand_empty_rest_of_line ();
3936}
3937
3938#endif
3939
252b5132
RH		 3940static int i386_immediate PARAMS ((char *));
3941
3942static int
3943i386_immediate (imm_start)
3944 char *imm_start;
3945{
3946 char *save_input_line_pointer;
f3c180ae
AM		 3947#ifndef LEX_AT
3948 char *gotfree_input_line;
3949#endif
252b5132 3950 segT exp_seg = 0;
47926f60 3951 expressionS *exp;
3956db08 3952 unsigned int types = ~0U;
252b5132
RH		 3953
3954 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3955 {
d0b47220 3956 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 3957 return 0;
3958 }
3959
3960 exp = &im_expressions[i.imm_operands++];
520dc8e8 3961 i.op[this_operand].imms = exp;
252b5132
RH		 3962
3963 if (is_space_char (*imm_start))
3964 ++imm_start;
3965
3966 save_input_line_pointer = input_line_pointer;
3967 input_line_pointer = imm_start;
3968
3969#ifndef LEX_AT
3956db08 3970 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 3971 if (gotfree_input_line)
3972 input_line_pointer = gotfree_input_line;
252b5132
RH		 3973#endif
3974
3975 exp_seg = expression (exp);
3976
83183c0c 3977 SKIP_WHITESPACE ();
252b5132 3978 if (*input_line_pointer)
f3c180ae 3979 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 3980
3981 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 3982#ifndef LEX_AT
3983 if (gotfree_input_line)
3984 free (gotfree_input_line);
3985#endif
252b5132 3986
2daf4fd8 3987 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 3988 {
47926f60 3989 /* Missing or bad expr becomes absolute 0. */
d0b47220 3990 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 3991 imm_start);
252b5132
RH		 3992 exp->X_op = O_constant;
3993 exp->X_add_number = 0;
3994 exp->X_add_symbol = (symbolS *) 0;
3995 exp->X_op_symbol = (symbolS *) 0;
252b5132 3996 }
3e73aa7c 3997 else if (exp->X_op == O_constant)
252b5132 3998 {
47926f60 3999 /* Size it properly later. */
3e73aa7c
JH		 4000 i.types[this_operand] |= Imm64;
4001 /* If BFD64, sign extend val. */
4002 if (!use_rela_relocations)
4003 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4004 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4005 }
4c63da97 4006#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4007 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4008 && exp_seg != absolute_section
47926f60 4009 && exp_seg != text_section
24eab124
AM		 4010 && exp_seg != data_section
4011 && exp_seg != bss_section
4012 && exp_seg != undefined_section
f86103b7 4013 && !bfd_is_com_section (exp_seg))
252b5132 4014 {
d0b47220 4015 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4016 return 0;
4017 }
4018#endif
4019 else
4020 {
4021 /* This is an address. The size of the address will be
24eab124 4022 determined later, depending on destination register,
3e73aa7c
JH		 4023 suffix, or the default for the section. */
4024 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4025 i.types[this_operand] &= types;
252b5132
RH		 4026 }
4027
4028 return 1;
4029}
4030
551c1ca1 4031static char *i386_scale PARAMS ((char *));
252b5132 4032
551c1ca1 4033static char *
252b5132
RH		 4034i386_scale (scale)
4035 char *scale;
4036{
551c1ca1
AM		 4037 offsetT val;
4038 char *save = input_line_pointer;
252b5132 4039
551c1ca1
AM		 4040 input_line_pointer = scale;
4041 val = get_absolute_expression ();
4042
4043 switch (val)
252b5132 4044 {
551c1ca1 4045 case 1:
252b5132
RH		 4046 i.log2_scale_factor = 0;
4047 break;
551c1ca1 4048 case 2:
252b5132
RH		 4049 i.log2_scale_factor = 1;
4050 break;
551c1ca1 4051 case 4:
252b5132
RH		 4052 i.log2_scale_factor = 2;
4053 break;
551c1ca1 4054 case 8:
252b5132
RH		 4055 i.log2_scale_factor = 3;
4056 break;
4057 default:
a724f0f4
JB		 4058 {
4059 char sep = *input_line_pointer;
4060
4061 *input_line_pointer = '\0';
4062 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4063 scale);
4064 *input_line_pointer = sep;
4065 input_line_pointer = save;
4066 return NULL;
4067 }
252b5132 4068 }
29b0f896 4069 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4070 {
4071 as_warn (_("scale factor of %d without an index register"),
24eab124 4072 1 << i.log2_scale_factor);
252b5132
RH		 4073#if SCALE1_WHEN_NO_INDEX
4074 i.log2_scale_factor = 0;
4075#endif
4076 }
551c1ca1
AM		 4077 scale = input_line_pointer;
4078 input_line_pointer = save;
4079 return scale;
252b5132
RH		 4080}
4081
4082static int i386_displacement PARAMS ((char *, char *));
4083
4084static int
4085i386_displacement (disp_start, disp_end)
4086 char *disp_start;
4087 char *disp_end;
4088{
29b0f896 4089 expressionS *exp;
252b5132
RH		 4090 segT exp_seg = 0;
4091 char *save_input_line_pointer;
f3c180ae
AM		 4092#ifndef LEX_AT
4093 char *gotfree_input_line;
4094#endif
252b5132 4095 int bigdisp = Disp32;
3956db08 4096 unsigned int types = Disp;
252b5132 4097
3e73aa7c 4098 if (flag_code == CODE_64BIT)
7ecd2f8b 4099 {
29b0f896 4100 if (i.prefix[ADDR_PREFIX] == 0)
3956db08 4101 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b
JH		 4102 }
4103 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4104 bigdisp = Disp16;
252b5132
RH		 4105 i.types[this_operand] |= bigdisp;
4106
4107 exp = &disp_expressions[i.disp_operands];
520dc8e8 4108 i.op[this_operand].disps = exp;
252b5132
RH		 4109 i.disp_operands++;
4110 save_input_line_pointer = input_line_pointer;
4111 input_line_pointer = disp_start;
4112 END_STRING_AND_SAVE (disp_end);
4113
4114#ifndef GCC_ASM_O_HACK
4115#define GCC_ASM_O_HACK 0
4116#endif
4117#if GCC_ASM_O_HACK
4118 END_STRING_AND_SAVE (disp_end + 1);
4119 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4120 && displacement_string_end[-1] == '+')
252b5132
RH		 4121 {
4122 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4123 constraint within gcc asm statements.
4124 For instance:
4125
4126 #define _set_tssldt_desc(n,addr,limit,type) \
4127 __asm__ __volatile__ ( \
4128 "movw %w2,%0\n\t" \
4129 "movw %w1,2+%0\n\t" \
4130 "rorl $16,%1\n\t" \
4131 "movb %b1,4+%0\n\t" \
4132 "movb %4,5+%0\n\t" \
4133 "movb $0,6+%0\n\t" \
4134 "movb %h1,7+%0\n\t" \
4135 "rorl $16,%1" \
4136 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4137
4138 This works great except that the output assembler ends
4139 up looking a bit weird if it turns out that there is
4140 no offset. You end up producing code that looks like:
4141
4142 #APP
4143 movw $235,(%eax)
4144 movw %dx,2+(%eax)
4145 rorl $16,%edx
4146 movb %dl,4+(%eax)
4147 movb $137,5+(%eax)
4148 movb $0,6+(%eax)
4149 movb %dh,7+(%eax)
4150 rorl $16,%edx
4151 #NO_APP
4152
47926f60 4153 So here we provide the missing zero. */
24eab124
AM		 4154
4155 *displacement_string_end = '0';
252b5132
RH		 4156 }
4157#endif
4158#ifndef LEX_AT
3956db08 4159 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4160 if (gotfree_input_line)
4161 input_line_pointer = gotfree_input_line;
252b5132
RH		 4162#endif
4163
24eab124 4164 exp_seg = expression (exp);
252b5132 4165
636c26b0
AM		 4166 SKIP_WHITESPACE ();
4167 if (*input_line_pointer)
4168 as_bad (_("junk `%s' after expression"), input_line_pointer);
4169#if GCC_ASM_O_HACK
4170 RESTORE_END_STRING (disp_end + 1);
4171#endif
4172 RESTORE_END_STRING (disp_end);
4173 input_line_pointer = save_input_line_pointer;
4174#ifndef LEX_AT
4175 if (gotfree_input_line)
4176 free (gotfree_input_line);
4177#endif
4178
24eab124
AM		 4179 /* We do this to make sure that the section symbol is in
4180 the symbol table. We will ultimately change the relocation
47926f60 4181 to be relative to the beginning of the section. */
1ae12ab7 4182 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4183 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4184 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4185 {
636c26b0
AM		 4186 if (exp->X_op != O_symbol)
4187 {
4188 as_bad (_("bad expression used with @%s"),
4189 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4190 ? "GOTPCREL"
4191 : "GOTOFF"));
4192 return 0;
4193 }
4194
e5cb08ac 4195 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4196 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4197 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4198 exp->X_op = O_subtract;
4199 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4200 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4201 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4202 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4203 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4204 else
29b0f896 4205 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4206 }
252b5132 4207
2daf4fd8
AM		 4208 if (exp->X_op == O_absent || exp->X_op == O_big)
4209 {
47926f60 4210 /* Missing or bad expr becomes absolute 0. */
d0b47220 4211 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4212 disp_start);
4213 exp->X_op = O_constant;
4214 exp->X_add_number = 0;
4215 exp->X_add_symbol = (symbolS *) 0;
4216 exp->X_op_symbol = (symbolS *) 0;
4217 }
4218
4c63da97 4219#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4220 if (exp->X_op != O_constant
45288df1 4221 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4222 && exp_seg != absolute_section
45288df1
AM		 4223 && exp_seg != text_section
4224 && exp_seg != data_section
4225 && exp_seg != bss_section
31312f95 4226 && exp_seg != undefined_section
f86103b7 4227 && !bfd_is_com_section (exp_seg))
24eab124 4228 {
d0b47220 4229 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4230 return 0;
4231 }
252b5132 4232#endif
3956db08
JB		 4233
4234 if (!(i.types[this_operand] & ~Disp))
4235 i.types[this_operand] &= types;
4236
252b5132
RH		 4237 return 1;
4238}
4239
e5cb08ac 4240static int i386_index_check PARAMS ((const char *));
252b5132 4241
eecb386c 4242/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4243 Return 1 on success, 0 on a failure. */
4244
252b5132 4245static int
eecb386c
AM		 4246i386_index_check (operand_string)
4247 const char *operand_string;
252b5132 4248{
3e73aa7c 4249 int ok;
24eab124 4250#if INFER_ADDR_PREFIX
eecb386c
AM		 4251 int fudged = 0;
4252
24eab124
AM		 4253 tryprefix:
4254#endif
3e73aa7c 4255 ok = 1;
30123838
JB		 4256 if ((current_templates->start->cpu_flags & CpuSVME)
4257 && current_templates->end[-1].operand_types[0] == AnyMem)
4258 {
4259 /* Memory operands of SVME insns are special in that they only allow
4260 rAX as their memory address and ignore any segment override. */
4261 unsigned RegXX;
4262
4263 /* SKINIT is even more restrictive: it always requires EAX. */
4264 if (strcmp (current_templates->start->name, "skinit") == 0)
4265 RegXX = Reg32;
4266 else if (flag_code == CODE_64BIT)
4267 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4268 else
4269 RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4270 ? Reg16
4271 : Reg32;
4272 if (!i.base_reg
4273 || !(i.base_reg->reg_type & Acc)
4274 || !(i.base_reg->reg_type & RegXX)
4275 || i.index_reg
4276 || (i.types[0] & Disp))
4277 ok = 0;
4278 }
4279 else if (flag_code == CODE_64BIT)
20f0a1fc
NC		 4280 {
4281 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4282
4283 if ((i.base_reg
4284 && ((i.base_reg->reg_type & RegXX) == 0)
4285 && (i.base_reg->reg_type != BaseIndex
4286 || i.index_reg))
4287 || (i.index_reg
4288 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4289 != (RegXX | BaseIndex))))
4290 ok = 0;
3e73aa7c
JH		 4291 }
4292 else
4293 {
4294 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4295 {
4296 /* 16bit checks. */
4297 if ((i.base_reg
29b0f896
AM		 4298 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4299 != (Reg16 | BaseIndex)))
3e73aa7c 4300 || (i.index_reg
29b0f896
AM		 4301 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4302 != (Reg16 | BaseIndex))
4303 || !(i.base_reg
4304 && i.base_reg->reg_num < 6
4305 && i.index_reg->reg_num >= 6
4306 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4307 ok = 0;
4308 }
4309 else
e5cb08ac 4310 {
3e73aa7c
JH		 4311 /* 32bit checks. */
4312 if ((i.base_reg
4313 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4314 || (i.index_reg
29b0f896
AM		 4315 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4316 != (Reg32 | BaseIndex))))
e5cb08ac 4317 ok = 0;
3e73aa7c
JH		 4318 }
4319 }
4320 if (!ok)
24eab124
AM		 4321 {
4322#if INFER_ADDR_PREFIX
20f0a1fc 4323 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4324 {
4325 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4326 i.prefixes += 1;
b23bac36
AM		 4327 /* Change the size of any displacement too. At most one of
4328 Disp16 or Disp32 is set.
4329 FIXME. There doesn't seem to be any real need for separate
4330 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4331 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4332 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
29b0f896 4333 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4334 fudged = 1;
24eab124
AM		 4335 goto tryprefix;
4336 }
eecb386c
AM		 4337 if (fudged)
4338 as_bad (_("`%s' is not a valid base/index expression"),
4339 operand_string);
4340 else
c388dee8 4341#endif
eecb386c
AM		 4342 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4343 operand_string,
3e73aa7c 4344 flag_code_names[flag_code]);
24eab124 4345 }
20f0a1fc 4346 return ok;
24eab124 4347}
252b5132 4348
252b5132 4349/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4350 on error. */
252b5132 4351
252b5132
RH		 4352static int
4353i386_operand (operand_string)
4354 char *operand_string;
4355{
af6bdddf
AM		 4356 const reg_entry *r;
4357 char *end_op;
24eab124 4358 char *op_string = operand_string;
252b5132 4359
24eab124 4360 if (is_space_char (*op_string))
252b5132
RH		 4361 ++op_string;
4362
24eab124 4363 /* We check for an absolute prefix (differentiating,
47926f60 4364 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4365 if (*op_string == ABSOLUTE_PREFIX)
4366 {
4367 ++op_string;
4368 if (is_space_char (*op_string))
4369 ++op_string;
4370 i.types[this_operand] |= JumpAbsolute;
4371 }
252b5132 4372
47926f60 4373 /* Check if operand is a register. */
af6bdddf
AM		 4374 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4375 && (r = parse_register (op_string, &end_op)) != NULL)
24eab124 4376 {
24eab124
AM		 4377 /* Check for a segment override by searching for ':' after a
4378 segment register. */
4379 op_string = end_op;
4380 if (is_space_char (*op_string))
4381 ++op_string;
4382 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4383 {
4384 switch (r->reg_num)
4385 {
4386 case 0:
4387 i.seg[i.mem_operands] = &es;
4388 break;
4389 case 1:
4390 i.seg[i.mem_operands] = &cs;
4391 break;
4392 case 2:
4393 i.seg[i.mem_operands] = &ss;
4394 break;
4395 case 3:
4396 i.seg[i.mem_operands] = &ds;
4397 break;
4398 case 4:
4399 i.seg[i.mem_operands] = &fs;
4400 break;
4401 case 5:
4402 i.seg[i.mem_operands] = &gs;
4403 break;
4404 }
252b5132 4405
24eab124 4406 /* Skip the ':' and whitespace. */
252b5132
RH		 4407 ++op_string;
4408 if (is_space_char (*op_string))
24eab124 4409 ++op_string;
252b5132 4410
24eab124
AM		 4411 if (!is_digit_char (*op_string)
4412 && !is_identifier_char (*op_string)
4413 && *op_string != '('
4414 && *op_string != ABSOLUTE_PREFIX)
4415 {
4416 as_bad (_("bad memory operand `%s'"), op_string);
4417 return 0;
4418 }
47926f60 4419 /* Handle case of %es:*foo. */
24eab124
AM		 4420 if (*op_string == ABSOLUTE_PREFIX)
4421 {
4422 ++op_string;
4423 if (is_space_char (*op_string))
4424 ++op_string;
4425 i.types[this_operand] |= JumpAbsolute;
4426 }
4427 goto do_memory_reference;
4428 }
4429 if (*op_string)
4430 {
d0b47220 4431 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4432 return 0;
4433 }
4434 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4435 i.op[this_operand].regs = r;
24eab124
AM		 4436 i.reg_operands++;
4437 }
af6bdddf
AM		 4438 else if (*op_string == REGISTER_PREFIX)
4439 {
4440 as_bad (_("bad register name `%s'"), op_string);
4441 return 0;
4442 }
24eab124 4443 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4444 {
24eab124
AM		 4445 ++op_string;
4446 if (i.types[this_operand] & JumpAbsolute)
4447 {
d0b47220 4448 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4449 return 0;
4450 }
4451 if (!i386_immediate (op_string))
4452 return 0;
4453 }
4454 else if (is_digit_char (*op_string)
4455 || is_identifier_char (*op_string)
e5cb08ac 4456 || *op_string == '(')
24eab124 4457 {
47926f60 4458 /* This is a memory reference of some sort. */
af6bdddf 4459 char *base_string;
252b5132 4460
47926f60 4461 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4462 char *displacement_string_start;
4463 char *displacement_string_end;
252b5132 4464
24eab124 4465 do_memory_reference:
24eab124
AM		 4466 if ((i.mem_operands == 1
4467 && (current_templates->start->opcode_modifier & IsString) == 0)
4468 || i.mem_operands == 2)
4469 {
4470 as_bad (_("too many memory references for `%s'"),
4471 current_templates->start->name);
4472 return 0;
4473 }
252b5132 4474
24eab124
AM		 4475 /* Check for base index form. We detect the base index form by
4476 looking for an ')' at the end of the operand, searching
4477 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4478 after the '('. */
af6bdddf 4479 base_string = op_string + strlen (op_string);
c3332e24 4480
af6bdddf
AM		 4481 --base_string;
4482 if (is_space_char (*base_string))
4483 --base_string;
252b5132 4484
47926f60 4485 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4486 displacement_string_start = op_string;
4487 displacement_string_end = base_string + 1;
252b5132 4488
24eab124
AM		 4489 if (*base_string == ')')
4490 {
af6bdddf 4491 char *temp_string;
24eab124
AM		 4492 unsigned int parens_balanced = 1;
4493 /* We've already checked that the number of left & right ()'s are
47926f60 4494 equal, so this loop will not be infinite. */
24eab124
AM		 4495 do
4496 {
4497 base_string--;
4498 if (*base_string == ')')
4499 parens_balanced++;
4500 if (*base_string == '(')
4501 parens_balanced--;
4502 }
4503 while (parens_balanced);
c3332e24 4504
af6bdddf 4505 temp_string = base_string;
c3332e24 4506
24eab124 4507 /* Skip past '(' and whitespace. */
252b5132
RH		 4508 ++base_string;
4509 if (is_space_char (*base_string))
24eab124 4510 ++base_string;
252b5132 4511
af6bdddf
AM		 4512 if (*base_string == ','
4513 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4514 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4515 {
af6bdddf 4516 displacement_string_end = temp_string;
252b5132 4517
af6bdddf 4518 i.types[this_operand] |= BaseIndex;
252b5132 4519
af6bdddf 4520 if (i.base_reg)
24eab124 4521 {
24eab124
AM		 4522 base_string = end_op;
4523 if (is_space_char (*base_string))
4524 ++base_string;
af6bdddf
AM		 4525 }
4526
4527 /* There may be an index reg or scale factor here. */
4528 if (*base_string == ',')
4529 {
4530 ++base_string;
4531 if (is_space_char (*base_string))
4532 ++base_string;
4533
4534 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4535 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4536 {
af6bdddf 4537 base_string = end_op;
24eab124
AM		 4538 if (is_space_char (*base_string))
4539 ++base_string;
af6bdddf
AM		 4540 if (*base_string == ',')
4541 {
4542 ++base_string;
4543 if (is_space_char (*base_string))
4544 ++base_string;
4545 }
e5cb08ac 4546 else if (*base_string != ')')
af6bdddf
AM		 4547 {
4548 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4549 operand_string);
4550 return 0;
4551 }
24eab124 4552 }
af6bdddf 4553 else if (*base_string == REGISTER_PREFIX)
24eab124 4554 {
af6bdddf 4555 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4556 return 0;
4557 }
252b5132 4558
47926f60 4559 /* Check for scale factor. */
551c1ca1 4560 if (*base_string != ')')
af6bdddf 4561 {
551c1ca1
AM		 4562 char *end_scale = i386_scale (base_string);
4563
4564 if (!end_scale)
af6bdddf 4565 return 0;
24eab124 4566
551c1ca1 4567 base_string = end_scale;
af6bdddf
AM		 4568 if (is_space_char (*base_string))
4569 ++base_string;
4570 if (*base_string != ')')
4571 {
4572 as_bad (_("expecting `)' after scale factor in `%s'"),
4573 operand_string);
4574 return 0;
4575 }
4576 }
4577 else if (!i.index_reg)
24eab124 4578 {
af6bdddf
AM		 4579 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4580 *base_string);
24eab124
AM		 4581 return 0;
4582 }
4583 }
af6bdddf 4584 else if (*base_string != ')')
24eab124 4585 {
af6bdddf
AM		 4586 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4587 operand_string);
24eab124
AM		 4588 return 0;
4589 }
c3332e24 4590 }
af6bdddf 4591 else if (*base_string == REGISTER_PREFIX)
c3332e24 4592 {
af6bdddf 4593 as_bad (_("bad register name `%s'"), base_string);
24eab124 4594 return 0;
c3332e24 4595 }
24eab124
AM		 4596 }
4597
4598 /* If there's an expression beginning the operand, parse it,
4599 assuming displacement_string_start and
4600 displacement_string_end are meaningful. */
4601 if (displacement_string_start != displacement_string_end)
4602 {
4603 if (!i386_displacement (displacement_string_start,
4604 displacement_string_end))
4605 return 0;
4606 }
4607
4608 /* Special case for (%dx) while doing input/output op. */
4609 if (i.base_reg
4610 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4611 && i.index_reg == 0
4612 && i.log2_scale_factor == 0
4613 && i.seg[i.mem_operands] == 0
4614 && (i.types[this_operand] & Disp) == 0)
4615 {
4616 i.types[this_operand] = InOutPortReg;
4617 return 1;
4618 }
4619
eecb386c
AM		 4620 if (i386_index_check (operand_string) == 0)
4621 return 0;
24eab124
AM		 4622 i.mem_operands++;
4623 }
4624 else
ce8a8b2f
AM		 4625 {
4626 /* It's not a memory operand; argh! */
24eab124
AM		 4627 as_bad (_("invalid char %s beginning operand %d `%s'"),
4628 output_invalid (*op_string),
4629 this_operand + 1,
4630 op_string);
4631 return 0;
4632 }
47926f60 4633 return 1; /* Normal return. */
252b5132
RH		 4634}
4635\f
ee7fcc42
AM		 4636/* md_estimate_size_before_relax()
4637
4638 Called just before relax() for rs_machine_dependent frags. The x86
4639 assembler uses these frags to handle variable size jump
4640 instructions.
4641
4642 Any symbol that is now undefined will not become defined.
4643 Return the correct fr_subtype in the frag.
4644 Return the initial "guess for variable size of frag" to caller.
4645 The guess is actually the growth beyond the fixed part. Whatever
4646 we do to grow the fixed or variable part contributes to our
4647 returned value. */
4648
252b5132
RH		 4649int
4650md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4651 fragS *fragP;
4652 segT segment;
252b5132 4653{
252b5132 4654 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4655 check for un-relaxable symbols. On an ELF system, we can't relax
4656 an externally visible symbol, because it may be overridden by a
4657 shared library. */
4658 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4659#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
31312f95
AM		 4660 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4661 && (S_IS_EXTERNAL (fragP->fr_symbol)
4662 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4663#endif
4664 )
252b5132 4665 {
b98ef147
AM		 4666 /* Symbol is undefined in this segment, or we need to keep a
4667 reloc so that weak symbols can be overridden. */
4668 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4669 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4670 unsigned char *opcode;
4671 int old_fr_fix;
f6af82bd 4672
ee7fcc42
AM		 4673 if (fragP->fr_var != NO_RELOC)
4674 reloc_type = fragP->fr_var;
b98ef147 4675 else if (size == 2)
f6af82bd
AM		 4676 reloc_type = BFD_RELOC_16_PCREL;
4677 else
4678 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4679
ee7fcc42
AM		 4680 old_fr_fix = fragP->fr_fix;
4681 opcode = (unsigned char *) fragP->fr_opcode;
4682
fddf5b5b 4683 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4684 {
fddf5b5b
AM		 4685 case UNCOND_JUMP:
4686 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4687 opcode[0] = 0xe9;
252b5132 4688 fragP->fr_fix += size;
062cd5e7
AS		 4689 fix_new (fragP, old_fr_fix, size,
4690 fragP->fr_symbol,
4691 fragP->fr_offset, 1,
4692 reloc_type);
252b5132
RH		 4693 break;
4694
fddf5b5b 4695 case COND_JUMP86:
412167cb
AM		 4696 if (size == 2
4697 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4698 {
4699 /* Negate the condition, and branch past an
4700 unconditional jump. */
4701 opcode[0] ^= 1;
4702 opcode[1] = 3;
4703 /* Insert an unconditional jump. */
4704 opcode[2] = 0xe9;
4705 /* We added two extra opcode bytes, and have a two byte
4706 offset. */
4707 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4708 fix_new (fragP, old_fr_fix + 2, 2,
4709 fragP->fr_symbol,
4710 fragP->fr_offset, 1,
4711 reloc_type);
fddf5b5b
AM		 4712 break;
4713 }
4714 /* Fall through. */
4715
4716 case COND_JUMP:
412167cb
AM		 4717 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4718 {
3e02c1cc
AM		 4719 fixS *fixP;
4720
412167cb 4721 fragP->fr_fix += 1;
3e02c1cc
AM		 4722 fixP = fix_new (fragP, old_fr_fix, 1,
4723 fragP->fr_symbol,
4724 fragP->fr_offset, 1,
4725 BFD_RELOC_8_PCREL);
4726 fixP->fx_signed = 1;
412167cb
AM		 4727 break;
4728 }
93c2a809 4729
24eab124 4730 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4731 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4732 opcode[1] = opcode[0] + 0x10;
f6af82bd 4733 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4734 /* We've added an opcode byte. */
4735 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4736 fix_new (fragP, old_fr_fix + 1, size,
4737 fragP->fr_symbol,
4738 fragP->fr_offset, 1,
4739 reloc_type);
252b5132 4740 break;
fddf5b5b
AM		 4741
4742 default:
4743 BAD_CASE (fragP->fr_subtype);
4744 break;
252b5132
RH		 4745 }
4746 frag_wane (fragP);
ee7fcc42 4747 return fragP->fr_fix - old_fr_fix;
252b5132 4748 }
93c2a809 4749
93c2a809
AM		 4750 /* Guess size depending on current relax state. Initially the relax
4751 state will correspond to a short jump and we return 1, because
4752 the variable part of the frag (the branch offset) is one byte
4753 long. However, we can relax a section more than once and in that
4754 case we must either set fr_subtype back to the unrelaxed state,
4755 or return the value for the appropriate branch. */
4756 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4757}
4758
47926f60
KH		 4759/* Called after relax() is finished.
4760
4761 In: Address of frag.
4762 fr_type == rs_machine_dependent.
4763 fr_subtype is what the address relaxed to.
4764
4765 Out: Any fixSs and constants are set up.
4766 Caller will turn frag into a ".space 0". */
4767
252b5132
RH		 4768void
4769md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4770 bfd *abfd ATTRIBUTE_UNUSED;
4771 segT sec ATTRIBUTE_UNUSED;
29b0f896 4772 fragS *fragP;
252b5132 4773{
29b0f896 4774 unsigned char *opcode;
252b5132 4775 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4776 offsetT target_address;
4777 offsetT opcode_address;
252b5132 4778 unsigned int extension = 0;
847f7ad4 4779 offsetT displacement_from_opcode_start;
252b5132
RH		 4780
4781 opcode = (unsigned char *) fragP->fr_opcode;
4782
47926f60 4783 /* Address we want to reach in file space. */
252b5132 4784 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4785
47926f60 4786 /* Address opcode resides at in file space. */
252b5132
RH		 4787 opcode_address = fragP->fr_address + fragP->fr_fix;
4788
47926f60 4789 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4790 displacement_from_opcode_start = target_address - opcode_address;
4791
fddf5b5b 4792 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4793 {
47926f60
KH		 4794 /* Don't have to change opcode. */
4795 extension = 1; /* 1 opcode + 1 displacement */
252b5132 4796 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 4797 }
4798 else
4799 {
4800 if (no_cond_jump_promotion
4801 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4802 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 4803
fddf5b5b
AM		 4804 switch (fragP->fr_subtype)
4805 {
4806 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4807 extension = 4; /* 1 opcode + 4 displacement */
4808 opcode[0] = 0xe9;
4809 where_to_put_displacement = &opcode[1];
4810 break;
252b5132 4811
fddf5b5b
AM		 4812 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4813 extension = 2; /* 1 opcode + 2 displacement */
4814 opcode[0] = 0xe9;
4815 where_to_put_displacement = &opcode[1];
4816 break;
252b5132 4817
fddf5b5b
AM		 4818 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4819 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4820 extension = 5; /* 2 opcode + 4 displacement */
4821 opcode[1] = opcode[0] + 0x10;
4822 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4823 where_to_put_displacement = &opcode[2];
4824 break;
252b5132 4825
fddf5b5b
AM		 4826 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4827 extension = 3; /* 2 opcode + 2 displacement */
4828 opcode[1] = opcode[0] + 0x10;
4829 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4830 where_to_put_displacement = &opcode[2];
4831 break;
252b5132 4832
fddf5b5b
AM		 4833 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4834 extension = 4;
4835 opcode[0] ^= 1;
4836 opcode[1] = 3;
4837 opcode[2] = 0xe9;
4838 where_to_put_displacement = &opcode[3];
4839 break;
4840
4841 default:
4842 BAD_CASE (fragP->fr_subtype);
4843 break;
4844 }
252b5132 4845 }
fddf5b5b 4846
47926f60 4847 /* Now put displacement after opcode. */
252b5132
RH		 4848 md_number_to_chars ((char *) where_to_put_displacement,
4849 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 4850 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 4851 fragP->fr_fix += extension;
4852}
4853\f
47926f60
KH		 4854/* Size of byte displacement jmp. */
4855int md_short_jump_size = 2;
4856
4857/* Size of dword displacement jmp. */
4858int md_long_jump_size = 5;
252b5132 4859
47926f60
KH		 4860/* Size of relocation record. */
4861const int md_reloc_size = 8;
252b5132
RH		 4862
4863void
4864md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4865 char *ptr;
4866 addressT from_addr, to_addr;
ab9da554
ILT		 4867 fragS *frag ATTRIBUTE_UNUSED;
4868 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4869{
847f7ad4 4870 offsetT offset;
252b5132
RH		 4871
4872 offset = to_addr - (from_addr + 2);
47926f60
KH		 4873 /* Opcode for byte-disp jump. */
4874 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 4875 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4876}
4877
4878void
4879md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4880 char *ptr;
4881 addressT from_addr, to_addr;
a38cf1db
AM		 4882 fragS *frag ATTRIBUTE_UNUSED;
4883 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 4884{
847f7ad4 4885 offsetT offset;
252b5132 4886
a38cf1db
AM		 4887 offset = to_addr - (from_addr + 5);
4888 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4889 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 4890}
4891\f
4892/* Apply a fixup (fixS) to segment data, once it has been determined
4893 by our caller that we have all the info we need to fix it up.
4894
4895 On the 386, immediates, displacements, and data pointers are all in
4896 the same (little-endian) format, so we don't need to care about which
4897 we are handling. */
4898
94f592af 4899void
55cf6793 4900md_apply_fix (fixP, valP, seg)
47926f60
KH		 4901 /* The fix we're to put in. */
4902 fixS *fixP;
47926f60 4903 /* Pointer to the value of the bits. */
c6682705 4904 valueT *valP;
47926f60
KH		 4905 /* Segment fix is from. */
4906 segT seg ATTRIBUTE_UNUSED;
252b5132 4907{
94f592af 4908 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 4909 valueT value = *valP;
252b5132 4910
f86103b7 4911#if !defined (TE_Mach)
93382f6d
AM		 4912 if (fixP->fx_pcrel)
4913 {
4914 switch (fixP->fx_r_type)
4915 {
5865bb77
ILT		 4916 default:
4917 break;
4918
d6ab8113
JB		 4919 case BFD_RELOC_64:
4920 fixP->fx_r_type = BFD_RELOC_64_PCREL;
4921 break;
93382f6d 4922 case BFD_RELOC_32:
ae8887b5 4923 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 4924 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4925 break;
4926 case BFD_RELOC_16:
4927 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4928 break;
4929 case BFD_RELOC_8:
4930 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4931 break;
4932 }
4933 }
252b5132 4934
a161fe53 4935 if (fixP->fx_addsy != NULL
31312f95 4936 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 4937 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 4938 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4939 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4940 && !use_rela_relocations)
252b5132 4941 {
31312f95
AM		 4942 /* This is a hack. There should be a better way to handle this.
4943 This covers for the fact that bfd_install_relocation will
4944 subtract the current location (for partial_inplace, PC relative
4945 relocations); see more below. */
252b5132
RH		 4946#ifndef OBJ_AOUT
4947 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4948#ifdef TE_PE
4949 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4950#endif
4951 )
4952 value += fixP->fx_where + fixP->fx_frag->fr_address;
4953#endif
4954#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2f66722d 4955 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
252b5132 4956 {
6539b54b 4957 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 4958
6539b54b 4959 if ((sym_seg == seg
2f66722d 4960 || (symbol_section_p (fixP->fx_addsy)
6539b54b 4961 && sym_seg != absolute_section))
ae6063d4 4962 && !generic_force_reloc (fixP))
2f66722d
AM		 4963 {
4964 /* Yes, we add the values in twice. This is because
6539b54b
AM		 4965 bfd_install_relocation subtracts them out again. I think
4966 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 4967 it. FIXME. */
4968 value += fixP->fx_where + fixP->fx_frag->fr_address;
4969 }
252b5132
RH		 4970 }
4971#endif
4972#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 4973 /* For some reason, the PE format does not store a
4974 section address offset for a PC relative symbol. */
4975 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
4976#if defined(BFD_ASSEMBLER) || defined(S_IS_WEAK)
4977 || S_IS_WEAK (fixP->fx_addsy)
4978#endif
4979 )
252b5132
RH		 4980 value += md_pcrel_from (fixP);
4981#endif
4982 }
4983
4984 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 4985 and we must not disappoint it. */
252b5132
RH		 4986#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4987 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4988 && fixP->fx_addsy)
47926f60
KH		 4989 switch (fixP->fx_r_type)
4990 {
4991 case BFD_RELOC_386_PLT32:
3e73aa7c 4992 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 4993 /* Make the jump instruction point to the address of the operand. At
4994 runtime we merely add the offset to the actual PLT entry. */
4995 value = -4;
4996 break;
31312f95 4997
13ae64f3
JJ		 4998 case BFD_RELOC_386_TLS_GD:
4999 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5000 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5001 case BFD_RELOC_386_TLS_IE:
5002 case BFD_RELOC_386_TLS_GOTIE:
bffbf940
JJ		 5003 case BFD_RELOC_X86_64_TLSGD:
5004 case BFD_RELOC_X86_64_TLSLD:
5005 case BFD_RELOC_X86_64_GOTTPOFF:
00f7efb6
JJ		 5006 value = 0; /* Fully resolved at runtime. No addend. */
5007 /* Fallthrough */
5008 case BFD_RELOC_386_TLS_LE:
5009 case BFD_RELOC_386_TLS_LDO_32:
5010 case BFD_RELOC_386_TLS_LE_32:
5011 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5012 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5013 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5014 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5015 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5016 break;
5017
5018 case BFD_RELOC_386_GOT32:
5019 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5020 value = 0; /* Fully resolved at runtime. No addend. */
5021 break;
47926f60
KH		 5022
5023 case BFD_RELOC_VTABLE_INHERIT:
5024 case BFD_RELOC_VTABLE_ENTRY:
5025 fixP->fx_done = 0;
94f592af 5026 return;
47926f60
KH		 5027
5028 default:
5029 break;
5030 }
5031#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5032 *valP = value;
f86103b7 5033#endif /* !defined (TE_Mach) */
3e73aa7c 5034
3e73aa7c 5035 /* Are we finished with this relocation now? */
c6682705 5036 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5037 fixP->fx_done = 1;
5038 else if (use_rela_relocations)
5039 {
5040 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5041 /* Remember value for tc_gen_reloc. */
5042 fixP->fx_addnumber = value;
3e73aa7c
JH		 5043 value = 0;
5044 }
f86103b7 5045
94f592af 5046 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5047}
252b5132 5048\f
252b5132
RH		 5049#define MAX_LITTLENUMS 6
5050
47926f60
KH		 5051/* Turn the string pointed to by litP into a floating point constant
5052 of type TYPE, and emit the appropriate bytes. The number of
5053 LITTLENUMS emitted is stored in *SIZEP. An error message is
5054 returned, or NULL on OK. */
5055
252b5132
RH		 5056char *
5057md_atof (type, litP, sizeP)
2ab9b79e 5058 int type;
252b5132
RH		 5059 char *litP;
5060 int *sizeP;
5061{
5062 int prec;
5063 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5064 LITTLENUM_TYPE *wordP;
5065 char *t;
5066
5067 switch (type)
5068 {
5069 case 'f':
5070 case 'F':
5071 prec = 2;
5072 break;
5073
5074 case 'd':
5075 case 'D':
5076 prec = 4;
5077 break;
5078
5079 case 'x':
5080 case 'X':
5081 prec = 5;
5082 break;
5083
5084 default:
5085 *sizeP = 0;
5086 return _("Bad call to md_atof ()");
5087 }
5088 t = atof_ieee (input_line_pointer, type, words);
5089 if (t)
5090 input_line_pointer = t;
5091
5092 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5093 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5094 the bigendian 386. */
5095 for (wordP = words + prec - 1; prec--;)
5096 {
5097 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5098 litP += sizeof (LITTLENUM_TYPE);
5099 }
5100 return 0;
5101}
5102\f
87c245cc 5103static char output_invalid_buf[8];
252b5132 5104
252b5132
RH		 5105static char *
5106output_invalid (c)
5107 int c;
5108{
3882b010 5109 if (ISPRINT (c))
252b5132
RH		 5110 sprintf (output_invalid_buf, "'%c'", c);
5111 else
5112 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
5113 return output_invalid_buf;
5114}
5115
af6bdddf 5116/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5117
5118static const reg_entry *
5119parse_register (reg_string, end_op)
5120 char *reg_string;
5121 char **end_op;
5122{
af6bdddf
AM		 5123 char *s = reg_string;
5124 char *p;
252b5132
RH		 5125 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5126 const reg_entry *r;
5127
5128 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5129 if (*s == REGISTER_PREFIX)
5130 ++s;
5131
5132 if (is_space_char (*s))
5133 ++s;
5134
5135 p = reg_name_given;
af6bdddf 5136 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5137 {
5138 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5139 return (const reg_entry *) NULL;
5140 s++;
252b5132
RH		 5141 }
5142
6588847e
DN		 5143 /* For naked regs, make sure that we are not dealing with an identifier.
5144 This prevents confusing an identifier like `eax_var' with register
5145 `eax'. */
5146 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5147 return (const reg_entry *) NULL;
5148
af6bdddf 5149 *end_op = s;
252b5132
RH		 5150
5151 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5152
5f47d35b 5153 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5154 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5155 {
5f47d35b
AM		 5156 if (is_space_char (*s))
5157 ++s;
5158 if (*s == '(')
5159 {
af6bdddf 5160 ++s;
5f47d35b
AM		 5161 if (is_space_char (*s))
5162 ++s;
5163 if (*s >= '0' && *s <= '7')
5164 {
5165 r = &i386_float_regtab[*s - '0'];
af6bdddf 5166 ++s;
5f47d35b
AM		 5167 if (is_space_char (*s))
5168 ++s;
5169 if (*s == ')')
5170 {
5171 *end_op = s + 1;
5172 return r;
5173 }
5f47d35b 5174 }
47926f60 5175 /* We have "%st(" then garbage. */
5f47d35b
AM		 5176 return (const reg_entry *) NULL;
5177 }
5178 }
5179
1ae00879 5180 if (r != NULL
20f0a1fc 5181 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5182 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5183 && flag_code != CODE_64BIT)
20f0a1fc 5184 return (const reg_entry *) NULL;
1ae00879 5185
252b5132
RH		 5186 return r;
5187}
5188\f
4cc782b5 5189#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5190const char *md_shortopts = "kVQ:sqn";
252b5132 5191#else
12b55ccc 5192const char *md_shortopts = "qn";
252b5132 5193#endif
6e0b89ee 5194
252b5132 5195struct option md_longopts[] = {
3e73aa7c
JH		 5196#define OPTION_32 (OPTION_MD_BASE + 0)
5197 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5198#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c
JH		 5199#define OPTION_64 (OPTION_MD_BASE + 1)
5200 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5201#endif
252b5132
RH		 5202 {NULL, no_argument, NULL, 0}
5203};
5204size_t md_longopts_size = sizeof (md_longopts);
5205
5206int
5207md_parse_option (c, arg)
5208 int c;
ab9da554 5209 char *arg ATTRIBUTE_UNUSED;
252b5132
RH		 5210{
5211 switch (c)
5212 {
12b55ccc
L		 5213 case 'n':
5214 optimize_align_code = 0;
5215 break;
5216
a38cf1db
AM		 5217 case 'q':
5218 quiet_warnings = 1;
252b5132
RH		 5219 break;
5220
5221#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5222 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5223 should be emitted or not. FIXME: Not implemented. */
5224 case 'Q':
252b5132
RH		 5225 break;
5226
5227 /* -V: SVR4 argument to print version ID. */
5228 case 'V':
5229 print_version_id ();
5230 break;
5231
a38cf1db
AM		 5232 /* -k: Ignore for FreeBSD compatibility. */
5233 case 'k':
252b5132 5234 break;
4cc782b5
ILT		 5235
5236 case 's':
5237 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5238 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5239 break;
6e0b89ee 5240
3e73aa7c
JH		 5241 case OPTION_64:
5242 {
5243 const char **list, **l;
5244
3e73aa7c
JH		 5245 list = bfd_target_list ();
5246 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5247 if (strcmp (*l, "elf64-x86-64") == 0)
5248 {
5249 default_arch = "x86_64";
5250 break;
5251 }
3e73aa7c 5252 if (*l == NULL)
6e0b89ee 5253 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5254 free (list);
5255 }
5256 break;
5257#endif
252b5132 5258
6e0b89ee
AM		 5259 case OPTION_32:
5260 default_arch = "i386";
5261 break;
5262
252b5132
RH		 5263 default:
5264 return 0;
5265 }
5266 return 1;
5267}
5268
5269void
5270md_show_usage (stream)
5271 FILE *stream;
5272{
4cc782b5
ILT		 5273#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5274 fprintf (stream, _("\
a38cf1db
AM		 5275 -Q ignored\n\
5276 -V print assembler version number\n\
5277 -k ignored\n\
12b55ccc 5278 -n Do not optimize code alignment\n\
a38cf1db
AM		 5279 -q quieten some warnings\n\
5280 -s ignored\n"));
5281#else
5282 fprintf (stream, _("\
12b55ccc 5283 -n Do not optimize code alignment\n\
a38cf1db 5284 -q quieten some warnings\n"));
4cc782b5 5285#endif
252b5132
RH		 5286}
5287
3e73aa7c
JH		 5288#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5289 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5290
5291/* Pick the target format to use. */
5292
47926f60 5293const char *
252b5132
RH		 5294i386_target_format ()
5295{
3e73aa7c
JH		 5296 if (!strcmp (default_arch, "x86_64"))
5297 set_code_flag (CODE_64BIT);
5298 else if (!strcmp (default_arch, "i386"))
5299 set_code_flag (CODE_32BIT);
5300 else
5301 as_fatal (_("Unknown architecture"));
252b5132
RH		 5302 switch (OUTPUT_FLAVOR)
5303 {
4c63da97
AM		 5304#ifdef OBJ_MAYBE_AOUT
5305 case bfd_target_aout_flavour:
47926f60 5306 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5307#endif
5308#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5309 case bfd_target_coff_flavour:
5310 return "coff-i386";
4c63da97 5311#endif
3e73aa7c 5312#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5313 case bfd_target_elf_flavour:
3e73aa7c 5314 {
e5cb08ac
KH		 5315 if (flag_code == CODE_64BIT)
5316 use_rela_relocations = 1;
4ada7262 5317 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5318 }
4c63da97 5319#endif
252b5132
RH		 5320 default:
5321 abort ();
5322 return NULL;
5323 }
5324}
5325
47926f60 5326#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5327
5328#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5329void i386_elf_emit_arch_note ()
5330{
5331 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5332 && cpu_arch_name != NULL)
5333 {
5334 char *p;
5335 asection *seg = now_seg;
5336 subsegT subseg = now_subseg;
5337 Elf_Internal_Note i_note;
5338 Elf_External_Note e_note;
5339 asection *note_secp;
5340 int len;
5341
5342 /* Create the .note section. */
5343 note_secp = subseg_new (".note", 0);
5344 bfd_set_section_flags (stdoutput,
5345 note_secp,
5346 SEC_HAS_CONTENTS | SEC_READONLY);
5347
5348 /* Process the arch string. */
5349 len = strlen (cpu_arch_name);
5350
5351 i_note.namesz = len + 1;
5352 i_note.descsz = 0;
5353 i_note.type = NT_ARCH;
5354 p = frag_more (sizeof (e_note.namesz));
5355 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5356 p = frag_more (sizeof (e_note.descsz));
5357 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5358 p = frag_more (sizeof (e_note.type));
5359 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5360 p = frag_more (len + 1);
5361 strcpy (p, cpu_arch_name);
5362
5363 frag_align (2, 0, 0);
5364
5365 subseg_set (seg, subseg);
5366 }
5367}
5368#endif
252b5132 5369\f
252b5132
RH		 5370symbolS *
5371md_undefined_symbol (name)
5372 char *name;
5373{
18dc2407
ILT		 5374 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5375 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5376 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5377 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5378 {
5379 if (!GOT_symbol)
5380 {
5381 if (symbol_find (name))
5382 as_bad (_("GOT already in symbol table"));
5383 GOT_symbol = symbol_new (name, undefined_section,
5384 (valueT) 0, &zero_address_frag);
5385 };
5386 return GOT_symbol;
5387 }
252b5132
RH		 5388 return 0;
5389}
5390
5391/* Round up a section size to the appropriate boundary. */
47926f60 5392
252b5132
RH		 5393valueT
5394md_section_align (segment, size)
ab9da554 5395 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5396 valueT size;
5397{
4c63da97
AM		 5398#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5399 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5400 {
5401 /* For a.out, force the section size to be aligned. If we don't do
5402 this, BFD will align it for us, but it will not write out the
5403 final bytes of the section. This may be a bug in BFD, but it is
5404 easier to fix it here since that is how the other a.out targets
5405 work. */
5406 int align;
5407
5408 align = bfd_get_section_alignment (stdoutput, segment);
5409 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5410 }
252b5132
RH		 5411#endif
5412
5413 return size;
5414}
5415
5416/* On the i386, PC-relative offsets are relative to the start of the
5417 next instruction. That is, the address of the offset, plus its
5418 size, since the offset is always the last part of the insn. */
5419
5420long
5421md_pcrel_from (fixP)
5422 fixS *fixP;
5423{
5424 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5425}
5426
5427#ifndef I386COFF
5428
5429static void
5430s_bss (ignore)
ab9da554 5431 int ignore ATTRIBUTE_UNUSED;
252b5132 5432{
29b0f896 5433 int temp;
252b5132 5434
8a75718c
JB		 5435#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5436 if (IS_ELF)
5437 obj_elf_section_change_hook ();
5438#endif
252b5132
RH		 5439 temp = get_absolute_expression ();
5440 subseg_set (bss_section, (subsegT) temp);
5441 demand_empty_rest_of_line ();
5442}
5443
5444#endif
5445
252b5132
RH		 5446void
5447i386_validate_fix (fixp)
5448 fixS *fixp;
5449{
5450 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5451 {
23df1078
JH		 5452 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5453 {
5454 if (flag_code != CODE_64BIT)
5455 abort ();
5456 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5457 }
5458 else
5459 {
d6ab8113
JB		 5460 if (flag_code != CODE_64BIT)
5461 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5462 else
5463 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5464 }
252b5132
RH		 5465 fixp->fx_subsy = 0;
5466 }
5467}
5468
252b5132
RH		 5469arelent *
5470tc_gen_reloc (section, fixp)
ab9da554 5471 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5472 fixS *fixp;
5473{
5474 arelent *rel;
5475 bfd_reloc_code_real_type code;
5476
5477 switch (fixp->fx_r_type)
5478 {
3e73aa7c
JH		 5479 case BFD_RELOC_X86_64_PLT32:
5480 case BFD_RELOC_X86_64_GOT32:
5481 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5482 case BFD_RELOC_386_PLT32:
5483 case BFD_RELOC_386_GOT32:
5484 case BFD_RELOC_386_GOTOFF:
5485 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5486 case BFD_RELOC_386_TLS_GD:
5487 case BFD_RELOC_386_TLS_LDM:
5488 case BFD_RELOC_386_TLS_LDO_32:
5489 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5490 case BFD_RELOC_386_TLS_IE:
5491 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5492 case BFD_RELOC_386_TLS_LE_32:
5493 case BFD_RELOC_386_TLS_LE:
bffbf940
JJ		 5494 case BFD_RELOC_X86_64_TLSGD:
5495 case BFD_RELOC_X86_64_TLSLD:
5496 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5497 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5498 case BFD_RELOC_X86_64_GOTTPOFF:
5499 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5500 case BFD_RELOC_X86_64_TPOFF64:
5501 case BFD_RELOC_X86_64_GOTOFF64:
5502 case BFD_RELOC_X86_64_GOTPC32:
252b5132
RH		 5503 case BFD_RELOC_RVA:
5504 case BFD_RELOC_VTABLE_ENTRY:
5505 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5506#ifdef TE_PE
5507 case BFD_RELOC_32_SECREL:
5508#endif
252b5132
RH		 5509 code = fixp->fx_r_type;
5510 break;
dbbaec26
L		 5511 case BFD_RELOC_X86_64_32S:
5512 if (!fixp->fx_pcrel)
5513 {
5514 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5515 code = fixp->fx_r_type;
5516 break;
5517 }
252b5132 5518 default:
93382f6d 5519 if (fixp->fx_pcrel)
252b5132 5520 {
93382f6d
AM		 5521 switch (fixp->fx_size)
5522 {
5523 default:
b091f402
AM		 5524 as_bad_where (fixp->fx_file, fixp->fx_line,
5525 _("can not do %d byte pc-relative relocation"),
5526 fixp->fx_size);
93382f6d
AM		 5527 code = BFD_RELOC_32_PCREL;
5528 break;
5529 case 1: code = BFD_RELOC_8_PCREL; break;
5530 case 2: code = BFD_RELOC_16_PCREL; break;
5531 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5532#ifdef BFD64
5533 case 8: code = BFD_RELOC_64_PCREL; break;
5534#endif
93382f6d
AM		 5535 }
5536 }
5537 else
5538 {
5539 switch (fixp->fx_size)
5540 {
5541 default:
b091f402
AM		 5542 as_bad_where (fixp->fx_file, fixp->fx_line,
5543 _("can not do %d byte relocation"),
5544 fixp->fx_size);
93382f6d
AM		 5545 code = BFD_RELOC_32;
5546 break;
5547 case 1: code = BFD_RELOC_8; break;
5548 case 2: code = BFD_RELOC_16; break;
5549 case 4: code = BFD_RELOC_32; break;
937149dd 5550#ifdef BFD64
3e73aa7c 5551 case 8: code = BFD_RELOC_64; break;
937149dd 5552#endif
93382f6d 5553 }
252b5132
RH		 5554 }
5555 break;
5556 }
252b5132 5557
d6ab8113 5558 if ((code == BFD_RELOC_32 || code == BFD_RELOC_32_PCREL)
252b5132
RH		 5559 && GOT_symbol
5560 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5561 {
d6ab8113
JB		 5562 if (flag_code != CODE_64BIT)
5563 code = BFD_RELOC_386_GOTPC;
5564 else
5565 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5566 }
252b5132
RH		 5567
5568 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5569 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5570 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5571
5572 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5573
3e73aa7c
JH		 5574 if (!use_rela_relocations)
5575 {
5576 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5577 vtable entry to be used in the relocation's section offset. */
5578 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5579 rel->address = fixp->fx_offset;
252b5132 5580
c6682705 5581 rel->addend = 0;
3e73aa7c
JH		 5582 }
5583 /* Use the rela in 64bit mode. */
252b5132 5584 else
3e73aa7c 5585 {
062cd5e7
AS		 5586 if (!fixp->fx_pcrel)
5587 rel->addend = fixp->fx_offset;
5588 else
5589 switch (code)
5590 {
5591 case BFD_RELOC_X86_64_PLT32:
5592 case BFD_RELOC_X86_64_GOT32:
5593 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5594 case BFD_RELOC_X86_64_TLSGD:
5595 case BFD_RELOC_X86_64_TLSLD:
5596 case BFD_RELOC_X86_64_GOTTPOFF:
062cd5e7
AS		 5597 rel->addend = fixp->fx_offset - fixp->fx_size;
5598 break;
5599 default:
5600 rel->addend = (section->vma
5601 - fixp->fx_size
5602 + fixp->fx_addnumber
5603 + md_pcrel_from (fixp));
5604 break;
5605 }
3e73aa7c
JH		 5606 }
5607
252b5132
RH		 5608 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5609 if (rel->howto == NULL)
5610 {
5611 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 5612 _("cannot represent relocation type %s"),
252b5132
RH		 5613 bfd_get_reloc_code_name (code));
5614 /* Set howto to a garbage value so that we can keep going. */
5615 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5616 assert (rel->howto != NULL);
5617 }
5618
5619 return rel;
5620}
5621
64a0c779
DN		 5622\f
5623/* Parse operands using Intel syntax. This implements a recursive descent
5624 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5625 Programmer's Guide.
5626
5627 FIXME: We do not recognize the full operand grammar defined in the MASM
5628 documentation. In particular, all the structure/union and
5629 high-level macro operands are missing.
5630
5631 Uppercase words are terminals, lower case words are non-terminals.
5632 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5633 bars '|' denote choices. Most grammar productions are implemented in
5634 functions called 'intel_<production>'.
5635
5636 Initial production is 'expr'.
5637
9306ca4a 5638 addOp + | -
64a0c779
DN		 5639
5640 alpha [a-zA-Z]
5641
9306ca4a
JB		 5642 binOp & | AND | \| | OR | ^ | XOR
5643
64a0c779
DN		 5644 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5645
5646 constant digits [[ radixOverride ]]
5647
9306ca4a 5648 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 5649
5650 digits decdigit
b77a7acd
AJ		 5651 | digits decdigit
5652 | digits hexdigit
64a0c779
DN		 5653
5654 decdigit [0-9]
5655
9306ca4a
JB		 5656 e04 e04 addOp e05
5657 | e05
5658
5659 e05 e05 binOp e06
b77a7acd 5660 | e06
64a0c779
DN		 5661
5662 e06 e06 mulOp e09
b77a7acd 5663 | e09
64a0c779
DN		 5664
5665 e09 OFFSET e10
a724f0f4
JB		 5666 | SHORT e10
5667 | + e10
5668 | - e10
9306ca4a
JB		 5669 | ~ e10
5670 | NOT e10
64a0c779
DN		 5671 | e09 PTR e10
5672 | e09 : e10
5673 | e10
5674
5675 e10 e10 [ expr ]
b77a7acd 5676 | e11
64a0c779
DN		 5677
5678 e11 ( expr )
b77a7acd 5679 | [ expr ]
64a0c779
DN		 5680 | constant
5681 | dataType
5682 | id
5683 | $
5684 | register
5685
a724f0f4 5686 => expr expr cmpOp e04
9306ca4a 5687 | e04
64a0c779
DN		 5688
5689 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 5690 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 5691
5692 hexdigit a | b | c | d | e | f
b77a7acd 5693 | A | B | C | D | E | F
64a0c779
DN		 5694
5695 id alpha
b77a7acd 5696 | id alpha
64a0c779
DN		 5697 | id decdigit
5698
9306ca4a 5699 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 5700
5701 quote " | '
5702
5703 register specialRegister
b77a7acd 5704 | gpRegister
64a0c779
DN		 5705 | byteRegister
5706
5707 segmentRegister CS | DS | ES | FS | GS | SS
5708
9306ca4a 5709 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 5710 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 5711 | TR3 | TR4 | TR5 | TR6 | TR7
5712
64a0c779
DN		 5713 We simplify the grammar in obvious places (e.g., register parsing is
5714 done by calling parse_register) and eliminate immediate left recursion
5715 to implement a recursive-descent parser.
5716
a724f0f4
JB		 5717 expr e04 expr'
5718
5719 expr' cmpOp e04 expr'
5720 | Empty
9306ca4a
JB		 5721
5722 e04 e05 e04'
5723
5724 e04' addOp e05 e04'
5725 | Empty
64a0c779
DN		 5726
5727 e05 e06 e05'
5728
9306ca4a 5729 e05' binOp e06 e05'
b77a7acd 5730 | Empty
64a0c779
DN		 5731
5732 e06 e09 e06'
5733
5734 e06' mulOp e09 e06'
b77a7acd 5735 | Empty
64a0c779
DN		 5736
5737 e09 OFFSET e10 e09'
a724f0f4
JB		 5738 | SHORT e10'
5739 | + e10'
5740 | - e10'
5741 | ~ e10'
5742 | NOT e10'
b77a7acd 5743 | e10 e09'
64a0c779
DN		 5744
5745 e09' PTR e10 e09'
b77a7acd 5746 | : e10 e09'
64a0c779
DN		 5747 | Empty
5748
5749 e10 e11 e10'
5750
5751 e10' [ expr ] e10'
b77a7acd 5752 | Empty
64a0c779
DN		 5753
5754 e11 ( expr )
b77a7acd 5755 | [ expr ]
64a0c779
DN		 5756 | BYTE
5757 | WORD
5758 | DWORD
9306ca4a 5759 | FWORD
64a0c779 5760 | QWORD
9306ca4a
JB		 5761 | TBYTE
5762 | OWORD
5763 | XMMWORD
64a0c779
DN		 5764 | .
5765 | $
5766 | register
5767 | id
5768 | constant */
5769
5770/* Parsing structure for the intel syntax parser. Used to implement the
5771 semantic actions for the operand grammar. */
5772struct intel_parser_s
5773 {
5774 char *op_string; /* The string being parsed. */
5775 int got_a_float; /* Whether the operand is a float. */
4a1805b1 5776 int op_modifier; /* Operand modifier. */
64a0c779 5777 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 5778 int in_offset; /* >=1 if parsing operand of offset. */
5779 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 5780 const reg_entry *reg; /* Last register reference found. */
5781 char *disp; /* Displacement string being built. */
a724f0f4 5782 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 5783 };
5784
5785static struct intel_parser_s intel_parser;
5786
5787/* Token structure for parsing intel syntax. */
5788struct intel_token
5789 {
5790 int code; /* Token code. */
5791 const reg_entry *reg; /* Register entry for register tokens. */
5792 char *str; /* String representation. */
5793 };
5794
5795static struct intel_token cur_token, prev_token;
5796
50705ef4
AM		 5797/* Token codes for the intel parser. Since T_SHORT is already used
5798 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 5799#define T_NIL -1
5800#define T_CONST 1
5801#define T_REG 2
5802#define T_BYTE 3
5803#define T_WORD 4
9306ca4a
JB		 5804#define T_DWORD 5
5805#define T_FWORD 6
5806#define T_QWORD 7
5807#define T_TBYTE 8
5808#define T_XMMWORD 9
50705ef4 5809#undef T_SHORT
9306ca4a
JB		 5810#define T_SHORT 10
5811#define T_OFFSET 11
5812#define T_PTR 12
5813#define T_ID 13
5814#define T_SHL 14
5815#define T_SHR 15
64a0c779
DN		 5816
5817/* Prototypes for intel parser functions. */
5818static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 5819static void intel_get_token PARAMS ((void));
5820static void intel_putback_token PARAMS ((void));
5821static int intel_expr PARAMS ((void));
9306ca4a 5822static int intel_e04 PARAMS ((void));
cce0cbdc 5823static int intel_e05 PARAMS ((void));
cce0cbdc 5824static int intel_e06 PARAMS ((void));
cce0cbdc 5825static int intel_e09 PARAMS ((void));
a724f0f4 5826static int intel_bracket_expr PARAMS ((void));
cce0cbdc 5827static int intel_e10 PARAMS ((void));
cce0cbdc 5828static int intel_e11 PARAMS ((void));
64a0c779 5829
64a0c779
DN		 5830static int
5831i386_intel_operand (operand_string, got_a_float)
5832 char *operand_string;
5833 int got_a_float;
5834{
5835 int ret;
5836 char *p;
5837
a724f0f4
JB		 5838 p = intel_parser.op_string = xstrdup (operand_string);
5839 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
5840
5841 for (;;)
64a0c779 5842 {
a724f0f4
JB		 5843 /* Initialize token holders. */
5844 cur_token.code = prev_token.code = T_NIL;
5845 cur_token.reg = prev_token.reg = NULL;
5846 cur_token.str = prev_token.str = NULL;
5847
5848 /* Initialize parser structure. */
5849 intel_parser.got_a_float = got_a_float;
5850 intel_parser.op_modifier = 0;
5851 intel_parser.is_mem = 0;
5852 intel_parser.in_offset = 0;
5853 intel_parser.in_bracket = 0;
5854 intel_parser.reg = NULL;
5855 intel_parser.disp[0] = '\0';
5856 intel_parser.next_operand = NULL;
5857
5858 /* Read the first token and start the parser. */
5859 intel_get_token ();
5860 ret = intel_expr ();
5861
5862 if (!ret)
5863 break;
5864
9306ca4a
JB		 5865 if (cur_token.code != T_NIL)
5866 {
5867 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
5868 current_templates->start->name, cur_token.str);
5869 ret = 0;
5870 }
64a0c779
DN		 5871 /* If we found a memory reference, hand it over to i386_displacement
5872 to fill in the rest of the operand fields. */
9306ca4a 5873 else if (intel_parser.is_mem)
64a0c779
DN		 5874 {
5875 if ((i.mem_operands == 1
5876 && (current_templates->start->opcode_modifier & IsString) == 0)
5877 || i.mem_operands == 2)
5878 {
5879 as_bad (_("too many memory references for '%s'"),
5880 current_templates->start->name);
5881 ret = 0;
5882 }
5883 else
5884 {
5885 char *s = intel_parser.disp;
5886 i.mem_operands++;
5887
a724f0f4
JB		 5888 if (!quiet_warnings && intel_parser.is_mem < 0)
5889 /* See the comments in intel_bracket_expr. */
5890 as_warn (_("Treating `%s' as memory reference"), operand_string);
5891
64a0c779
DN		 5892 /* Add the displacement expression. */
5893 if (*s != '\0')
a4622f40
AM		 5894 ret = i386_displacement (s, s + strlen (s));
5895 if (ret)
a724f0f4
JB		 5896 {
5897 /* Swap base and index in 16-bit memory operands like
5898 [si+bx]. Since i386_index_check is also used in AT&T
5899 mode we have to do that here. */
5900 if (i.base_reg
5901 && i.index_reg
5902 && (i.base_reg->reg_type & Reg16)
5903 && (i.index_reg->reg_type & Reg16)
5904 && i.base_reg->reg_num >= 6
5905 && i.index_reg->reg_num < 6)
5906 {
5907 const reg_entry *base = i.index_reg;
5908
5909 i.index_reg = i.base_reg;
5910 i.base_reg = base;
5911 }
5912 ret = i386_index_check (operand_string);
5913 }
64a0c779
DN		 5914 }
5915 }
5916
5917 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 5918 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 5919 || intel_parser.reg == NULL)
5920 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 5921
5922 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
5923 ret = 0;
5924 if (!ret || !intel_parser.next_operand)
5925 break;
5926 intel_parser.op_string = intel_parser.next_operand;
5927 this_operand = i.operands++;
64a0c779
DN		 5928 }
5929
5930 free (p);
5931 free (intel_parser.disp);
5932
5933 return ret;
5934}
5935
a724f0f4
JB		 5936#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
5937
5938/* expr e04 expr'
5939
5940 expr' cmpOp e04 expr'
5941 | Empty */
64a0c779
DN		 5942static int
5943intel_expr ()
5944{
a724f0f4
JB		 5945 /* XXX Implement the comparison operators. */
5946 return intel_e04 ();
9306ca4a
JB		 5947}
5948
a724f0f4 5949/* e04 e05 e04'
9306ca4a 5950
a724f0f4 5951 e04' addOp e05 e04'
9306ca4a
JB		 5952 | Empty */
5953static int
5954intel_e04 ()
5955{
a724f0f4 5956 int nregs = -1;
9306ca4a 5957
a724f0f4 5958 for (;;)
9306ca4a 5959 {
a724f0f4
JB		 5960 if (!intel_e05())
5961 return 0;
9306ca4a 5962
a724f0f4
JB		 5963 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
5964 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 5965
a724f0f4
JB		 5966 if (cur_token.code == '+')
5967 nregs = -1;
5968 else if (cur_token.code == '-')
5969 nregs = NUM_ADDRESS_REGS;
5970 else
5971 return 1;
64a0c779 5972
a724f0f4
JB		 5973 strcat (intel_parser.disp, cur_token.str);
5974 intel_match_token (cur_token.code);
5975 }
64a0c779
DN		 5976}
5977
64a0c779
DN		 5978/* e05 e06 e05'
5979
9306ca4a 5980 e05' binOp e06 e05'
64a0c779
DN		 5981 | Empty */
5982static int
5983intel_e05 ()
5984{
a724f0f4 5985 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 5986
a724f0f4 5987 for (;;)
64a0c779 5988 {
a724f0f4
JB		 5989 if (!intel_e06())
5990 return 0;
5991
5992 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
5993 {
5994 char str[2];
5995
5996 str[0] = cur_token.code;
5997 str[1] = 0;
5998 strcat (intel_parser.disp, str);
5999 }
6000 else
6001 break;
9306ca4a 6002
64a0c779
DN		 6003 intel_match_token (cur_token.code);
6004
a724f0f4
JB		 6005 if (nregs < 0)
6006 nregs = ~nregs;
64a0c779 6007 }
a724f0f4
JB		 6008 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6009 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6010 return 1;
4a1805b1 6011}
64a0c779
DN		 6012
6013/* e06 e09 e06'
6014
6015 e06' mulOp e09 e06'
b77a7acd 6016 | Empty */
64a0c779
DN		 6017static int
6018intel_e06 ()
6019{
a724f0f4 6020 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6021
a724f0f4 6022 for (;;)
64a0c779 6023 {
a724f0f4
JB		 6024 if (!intel_e09())
6025 return 0;
9306ca4a 6026
a724f0f4
JB		 6027 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6028 {
6029 char str[2];
9306ca4a 6030
a724f0f4
JB		 6031 str[0] = cur_token.code;
6032 str[1] = 0;
6033 strcat (intel_parser.disp, str);
6034 }
6035 else if (cur_token.code == T_SHL)
6036 strcat (intel_parser.disp, "<<");
6037 else if (cur_token.code == T_SHR)
6038 strcat (intel_parser.disp, ">>");
6039 else
6040 break;
9306ca4a 6041
a724f0f4 6042 intel_match_token (cur_token.code);
64a0c779 6043
a724f0f4
JB		 6044 if (nregs < 0)
6045 nregs = ~nregs;
64a0c779 6046 }
a724f0f4
JB		 6047 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6048 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6049 return 1;
64a0c779
DN		 6050}
6051
a724f0f4
JB		 6052/* e09 OFFSET e09
6053 | SHORT e09
6054 | + e09
6055 | - e09
6056 | ~ e09
6057 | NOT e09
9306ca4a
JB		 6058 | e10 e09'
6059
64a0c779 6060 e09' PTR e10 e09'
b77a7acd 6061 | : e10 e09'
64a0c779
DN		 6062 | Empty */
6063static int
6064intel_e09 ()
6065{
a724f0f4
JB		 6066 int nregs = ~NUM_ADDRESS_REGS;
6067 int in_offset = 0;
6068
6069 for (;;)
64a0c779 6070 {
a724f0f4
JB		 6071 /* Don't consume constants here. */
6072 if (cur_token.code == '+' || cur_token.code == '-')
6073 {
6074 /* Need to look one token ahead - if the next token
6075 is a constant, the current token is its sign. */
6076 int next_code;
6077
6078 intel_match_token (cur_token.code);
6079 next_code = cur_token.code;
6080 intel_putback_token ();
6081 if (next_code == T_CONST)
6082 break;
6083 }
6084
6085 /* e09 OFFSET e09 */
6086 if (cur_token.code == T_OFFSET)
6087 {
6088 if (!in_offset++)
6089 ++intel_parser.in_offset;
6090 }
6091
6092 /* e09 SHORT e09 */
6093 else if (cur_token.code == T_SHORT)
6094 intel_parser.op_modifier |= 1 << T_SHORT;
6095
6096 /* e09 + e09 */
6097 else if (cur_token.code == '+')
6098 strcat (intel_parser.disp, "+");
6099
6100 /* e09 - e09
6101 | ~ e09
6102 | NOT e09 */
6103 else if (cur_token.code == '-' || cur_token.code == '~')
6104 {
6105 char str[2];
64a0c779 6106
a724f0f4
JB		 6107 if (nregs < 0)
6108 nregs = ~nregs;
6109 str[0] = cur_token.code;
6110 str[1] = 0;
6111 strcat (intel_parser.disp, str);
6112 }
6113
6114 /* e09 e10 e09' */
6115 else
6116 break;
6117
6118 intel_match_token (cur_token.code);
64a0c779
DN		 6119 }
6120
a724f0f4 6121 for (;;)
9306ca4a 6122 {
a724f0f4
JB		 6123 if (!intel_e10 ())
6124 return 0;
9306ca4a 6125
a724f0f4
JB		 6126 /* e09' PTR e10 e09' */
6127 if (cur_token.code == T_PTR)
6128 {
6129 char suffix;
9306ca4a 6130
a724f0f4
JB		 6131 if (prev_token.code == T_BYTE)
6132 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6133
a724f0f4
JB		 6134 else if (prev_token.code == T_WORD)
6135 {
6136 if (current_templates->start->name[0] == 'l'
6137 && current_templates->start->name[2] == 's'
6138 && current_templates->start->name[3] == 0)
6139 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6140 else if (intel_parser.got_a_float == 2) /* "fi..." */
6141 suffix = SHORT_MNEM_SUFFIX;
6142 else
6143 suffix = WORD_MNEM_SUFFIX;
6144 }
64a0c779 6145
a724f0f4
JB		 6146 else if (prev_token.code == T_DWORD)
6147 {
6148 if (current_templates->start->name[0] == 'l'
6149 && current_templates->start->name[2] == 's'
6150 && current_templates->start->name[3] == 0)
6151 suffix = WORD_MNEM_SUFFIX;
6152 else if (flag_code == CODE_16BIT
6153 && (current_templates->start->opcode_modifier
6154 & (Jump|JumpDword|JumpInterSegment)))
6155 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6156 else if (intel_parser.got_a_float == 1) /* "f..." */
6157 suffix = SHORT_MNEM_SUFFIX;
6158 else
6159 suffix = LONG_MNEM_SUFFIX;
6160 }
9306ca4a 6161
a724f0f4
JB		 6162 else if (prev_token.code == T_FWORD)
6163 {
6164 if (current_templates->start->name[0] == 'l'
6165 && current_templates->start->name[2] == 's'
6166 && current_templates->start->name[3] == 0)
6167 suffix = LONG_MNEM_SUFFIX;
6168 else if (!intel_parser.got_a_float)
6169 {
6170 if (flag_code == CODE_16BIT)
6171 add_prefix (DATA_PREFIX_OPCODE);
6172 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6173 }
6174 else
6175 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6176 }
64a0c779 6177
a724f0f4
JB		 6178 else if (prev_token.code == T_QWORD)
6179 {
6180 if (intel_parser.got_a_float == 1) /* "f..." */
6181 suffix = LONG_MNEM_SUFFIX;
6182 else
6183 suffix = QWORD_MNEM_SUFFIX;
6184 }
64a0c779 6185
a724f0f4
JB		 6186 else if (prev_token.code == T_TBYTE)
6187 {
6188 if (intel_parser.got_a_float == 1)
6189 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6190 else
6191 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6192 }
9306ca4a 6193
a724f0f4 6194 else if (prev_token.code == T_XMMWORD)
9306ca4a 6195 {
a724f0f4
JB		 6196 /* XXX ignored for now, but accepted since gcc uses it */
6197 suffix = 0;
9306ca4a 6198 }
64a0c779 6199
f16b83df 6200 else
a724f0f4
JB		 6201 {
6202 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6203 return 0;
6204 }
6205
6206 if (current_templates->start->base_opcode == 0x8d /* lea */)
6207 ;
6208 else if (!i.suffix)
6209 i.suffix = suffix;
6210 else if (i.suffix != suffix)
6211 {
6212 as_bad (_("Conflicting operand modifiers"));
6213 return 0;
6214 }
64a0c779 6215
9306ca4a
JB		 6216 }
6217
a724f0f4
JB		 6218 /* e09' : e10 e09' */
6219 else if (cur_token.code == ':')
9306ca4a 6220 {
a724f0f4
JB		 6221 if (prev_token.code != T_REG)
6222 {
6223 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6224 segment/group identifier (which we don't have), using comma
6225 as the operand separator there is even less consistent, since
6226 there all branches only have a single operand. */
6227 if (this_operand != 0
6228 || intel_parser.in_offset
6229 || intel_parser.in_bracket
6230 || (!(current_templates->start->opcode_modifier
6231 & (Jump|JumpDword|JumpInterSegment))
6232 && !(current_templates->start->operand_types[0]
6233 & JumpAbsolute)))
6234 return intel_match_token (T_NIL);
6235 /* Remember the start of the 2nd operand and terminate 1st
6236 operand here.
6237 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6238 another expression), but it gets at least the simplest case
6239 (a plain number or symbol on the left side) right. */
6240 intel_parser.next_operand = intel_parser.op_string;
6241 *--intel_parser.op_string = '\0';
6242 return intel_match_token (':');
6243 }
9306ca4a 6244 }
64a0c779 6245
a724f0f4 6246 /* e09' Empty */
64a0c779 6247 else
a724f0f4 6248 break;
64a0c779 6249
a724f0f4
JB		 6250 intel_match_token (cur_token.code);
6251
6252 }
6253
6254 if (in_offset)
6255 {
6256 --intel_parser.in_offset;
6257 if (nregs < 0)
6258 nregs = ~nregs;
6259 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6260 {
a724f0f4 6261 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6262 return 0;
6263 }
a724f0f4
JB		 6264 intel_parser.op_modifier |= 1 << T_OFFSET;
6265 }
9306ca4a 6266
a724f0f4
JB		 6267 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6268 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6269 return 1;
6270}
64a0c779 6271
a724f0f4
JB		 6272static int
6273intel_bracket_expr ()
6274{
6275 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6276 const char *start = intel_parser.op_string;
6277 int len;
6278
6279 if (i.op[this_operand].regs)
6280 return intel_match_token (T_NIL);
6281
6282 intel_match_token ('[');
6283
6284 /* Mark as a memory operand only if it's not already known to be an
6285 offset expression. If it's an offset expression, we need to keep
6286 the brace in. */
6287 if (!intel_parser.in_offset)
6288 {
6289 ++intel_parser.in_bracket;
6290 /* Unfortunately gas always diverged from MASM in a respect that can't
6291 be easily fixed without risking to break code sequences likely to be
6292 encountered (the testsuite even check for this): MASM doesn't consider
6293 an expression inside brackets unconditionally as a memory reference.
6294 When that is e.g. a constant, an offset expression, or the sum of the
6295 two, this is still taken as a constant load. gas, however, always
6296 treated these as memory references. As a compromise, we'll try to make
6297 offset expressions inside brackets work the MASM way (since that's
6298 less likely to be found in real world code), but make constants alone
6299 continue to work the traditional gas way. In either case, issue a
6300 warning. */
6301 intel_parser.op_modifier &= ~was_offset;
64a0c779 6302 }
a724f0f4
JB		 6303 else
6304 strcat (intel_parser.disp, "[");
6305
6306 /* Add a '+' to the displacement string if necessary. */
6307 if (*intel_parser.disp != '\0'
6308 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6309 strcat (intel_parser.disp, "+");
64a0c779 6310
a724f0f4
JB		 6311 if (intel_expr ()
6312 && (len = intel_parser.op_string - start - 1,
6313 intel_match_token (']')))
64a0c779 6314 {
a724f0f4
JB		 6315 /* Preserve brackets when the operand is an offset expression. */
6316 if (intel_parser.in_offset)
6317 strcat (intel_parser.disp, "]");
6318 else
6319 {
6320 --intel_parser.in_bracket;
6321 if (i.base_reg || i.index_reg)
6322 intel_parser.is_mem = 1;
6323 if (!intel_parser.is_mem)
6324 {
6325 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6326 /* Defer the warning until all of the operand was parsed. */
6327 intel_parser.is_mem = -1;
6328 else if (!quiet_warnings)
6329 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6330 }
6331 }
6332 intel_parser.op_modifier |= was_offset;
64a0c779 6333
a724f0f4 6334 return 1;
64a0c779 6335 }
a724f0f4 6336 return 0;
64a0c779
DN		 6337}
6338
6339/* e10 e11 e10'
6340
6341 e10' [ expr ] e10'
b77a7acd 6342 | Empty */
64a0c779
DN		 6343static int
6344intel_e10 ()
6345{
a724f0f4
JB		 6346 if (!intel_e11 ())
6347 return 0;
64a0c779 6348
a724f0f4 6349 while (cur_token.code == '[')
64a0c779 6350 {
a724f0f4 6351 if (!intel_bracket_expr ())
21d6c4af 6352 return 0;
64a0c779
DN		 6353 }
6354
a724f0f4 6355 return 1;
64a0c779
DN		 6356}
6357
64a0c779 6358/* e11 ( expr )
b77a7acd 6359 | [ expr ]
64a0c779
DN		 6360 | BYTE
6361 | WORD
6362 | DWORD
9306ca4a 6363 | FWORD
64a0c779 6364 | QWORD
9306ca4a
JB		 6365 | TBYTE
6366 | OWORD
6367 | XMMWORD
4a1805b1 6368 | $
64a0c779
DN		 6369 | .
6370 | register
6371 | id
6372 | constant */
6373static int
6374intel_e11 ()
6375{
a724f0f4 6376 switch (cur_token.code)
64a0c779 6377 {
a724f0f4
JB		 6378 /* e11 ( expr ) */
6379 case '(':
64a0c779
DN		 6380 intel_match_token ('(');
6381 strcat (intel_parser.disp, "(");
6382
6383 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6384 {
6385 strcat (intel_parser.disp, ")");
6386 return 1;
6387 }
a724f0f4 6388 return 0;
4a1805b1 6389
a724f0f4
JB		 6390 /* e11 [ expr ] */
6391 case '[':
6392 /* Operands for jump/call inside brackets denote absolute addresses.
6393 XXX This shouldn't be needed anymore (or if it should rather live
6394 in intel_bracket_expr). */
9306ca4a
JB		 6395 if (current_templates->start->opcode_modifier
6396 & (Jump|JumpDword|JumpByte|JumpInterSegment))
64a0c779
DN		 6397 i.types[this_operand] |= JumpAbsolute;
6398
a724f0f4 6399 return intel_bracket_expr ();
64a0c779 6400
a724f0f4
JB		 6401 /* e11 $
6402 | . */
6403 case '.':
64a0c779
DN		 6404 strcat (intel_parser.disp, cur_token.str);
6405 intel_match_token (cur_token.code);
21d6c4af
DN		 6406
6407 /* Mark as a memory operand only if it's not already known to be an
6408 offset expression. */
a724f0f4 6409 if (!intel_parser.in_offset)
21d6c4af 6410 intel_parser.is_mem = 1;
64a0c779
DN		 6411
6412 return 1;
64a0c779 6413
a724f0f4
JB		 6414 /* e11 register */
6415 case T_REG:
6416 {
6417 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6418
a724f0f4 6419 intel_match_token (T_REG);
64a0c779 6420
a724f0f4
JB		 6421 /* Check for segment change. */
6422 if (cur_token.code == ':')
6423 {
6424 if (!(reg->reg_type & (SReg2 | SReg3)))
6425 {
6426 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6427 return 0;
6428 }
6429 else if (i.seg[i.mem_operands])
6430 as_warn (_("Extra segment override ignored"));
6431 else
6432 {
6433 if (!intel_parser.in_offset)
6434 intel_parser.is_mem = 1;
6435 switch (reg->reg_num)
6436 {
6437 case 0:
6438 i.seg[i.mem_operands] = &es;
6439 break;
6440 case 1:
6441 i.seg[i.mem_operands] = &cs;
6442 break;
6443 case 2:
6444 i.seg[i.mem_operands] = &ss;
6445 break;
6446 case 3:
6447 i.seg[i.mem_operands] = &ds;
6448 break;
6449 case 4:
6450 i.seg[i.mem_operands] = &fs;
6451 break;
6452 case 5:
6453 i.seg[i.mem_operands] = &gs;
6454 break;
6455 }
6456 }
6457 }
64a0c779 6458
a724f0f4
JB		 6459 /* Not a segment register. Check for register scaling. */
6460 else if (cur_token.code == '*')
6461 {
6462 if (!intel_parser.in_bracket)
6463 {
6464 as_bad (_("Register scaling only allowed in memory operands"));
6465 return 0;
6466 }
64a0c779 6467
a724f0f4
JB		 6468 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6469 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6470 else if (i.index_reg)
6471 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6472
a724f0f4
JB		 6473 /* What follows must be a valid scale. */
6474 intel_match_token ('*');
6475 i.index_reg = reg;
6476 i.types[this_operand] |= BaseIndex;
64a0c779 6477
a724f0f4
JB		 6478 /* Set the scale after setting the register (otherwise,
6479 i386_scale will complain) */
6480 if (cur_token.code == '+' || cur_token.code == '-')
6481 {
6482 char *str, sign = cur_token.code;
6483 intel_match_token (cur_token.code);
6484 if (cur_token.code != T_CONST)
6485 {
6486 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6487 cur_token.str);
6488 return 0;
6489 }
6490 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6491 strcpy (str + 1, cur_token.str);
6492 *str = sign;
6493 if (!i386_scale (str))
6494 return 0;
6495 free (str);
6496 }
6497 else if (!i386_scale (cur_token.str))
64a0c779 6498 return 0;
a724f0f4
JB		 6499 intel_match_token (cur_token.code);
6500 }
64a0c779 6501
a724f0f4
JB		 6502 /* No scaling. If this is a memory operand, the register is either a
6503 base register (first occurrence) or an index register (second
6504 occurrence). */
6505 else if (intel_parser.in_bracket && !(reg->reg_type & (SReg2 | SReg3)))
6506 {
64a0c779 6507
a724f0f4
JB		 6508 if (!i.base_reg)
6509 i.base_reg = reg;
6510 else if (!i.index_reg)
6511 i.index_reg = reg;
6512 else
6513 {
6514 as_bad (_("Too many register references in memory operand"));
6515 return 0;
6516 }
64a0c779 6517
a724f0f4
JB		 6518 i.types[this_operand] |= BaseIndex;
6519 }
4a1805b1 6520
a724f0f4
JB		 6521 /* Offset modifier. Add the register to the displacement string to be
6522 parsed as an immediate expression after we're done. */
6523 else if (intel_parser.in_offset)
6524 {
6525 as_warn (_("Using register names in OFFSET expressions is deprecated"));
6526 strcat (intel_parser.disp, reg->reg_name);
6527 }
64a0c779 6528
a724f0f4
JB		 6529 /* It's neither base nor index nor offset. */
6530 else if (!intel_parser.is_mem)
6531 {
6532 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6533 i.op[this_operand].regs = reg;
6534 i.reg_operands++;
6535 }
6536 else
6537 {
6538 as_bad (_("Invalid use of register"));
6539 return 0;
6540 }
64a0c779 6541
a724f0f4
JB		 6542 /* Since registers are not part of the displacement string (except
6543 when we're parsing offset operands), we may need to remove any
6544 preceding '+' from the displacement string. */
6545 if (*intel_parser.disp != '\0'
6546 && !intel_parser.in_offset)
6547 {
6548 char *s = intel_parser.disp;
6549 s += strlen (s) - 1;
6550 if (*s == '+')
6551 *s = '\0';
6552 }
4a1805b1 6553
a724f0f4
JB		 6554 return 1;
6555 }
6556
6557 /* e11 BYTE
6558 | WORD
6559 | DWORD
6560 | FWORD
6561 | QWORD
6562 | TBYTE
6563 | OWORD
6564 | XMMWORD */
6565 case T_BYTE:
6566 case T_WORD:
6567 case T_DWORD:
6568 case T_FWORD:
6569 case T_QWORD:
6570 case T_TBYTE:
6571 case T_XMMWORD:
6572 intel_match_token (cur_token.code);
64a0c779 6573
a724f0f4
JB		 6574 if (cur_token.code == T_PTR)
6575 return 1;
6576
6577 /* It must have been an identifier. */
6578 intel_putback_token ();
6579 cur_token.code = T_ID;
6580 /* FALLTHRU */
6581
6582 /* e11 id
6583 | constant */
6584 case T_ID:
6585 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6586 {
6587 symbolS *symbolP;
6588
a724f0f4
JB		 6589 /* The identifier represents a memory reference only if it's not
6590 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6591 symbolP = symbol_find(cur_token.str);
6592 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6593 intel_parser.is_mem = 1;
6594 }
a724f0f4 6595 /* FALLTHRU */
64a0c779 6596
a724f0f4
JB		 6597 case T_CONST:
6598 case '-':
6599 case '+':
6600 {
6601 char *save_str, sign = 0;
64a0c779 6602
a724f0f4
JB		 6603 /* Allow constants that start with `+' or `-'. */
6604 if (cur_token.code == '-' || cur_token.code == '+')
6605 {
6606 sign = cur_token.code;
6607 intel_match_token (cur_token.code);
6608 if (cur_token.code != T_CONST)
6609 {
6610 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6611 cur_token.str);
6612 return 0;
6613 }
6614 }
64a0c779 6615
a724f0f4
JB		 6616 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
6617 strcpy (save_str + !!sign, cur_token.str);
6618 if (sign)
6619 *save_str = sign;
64a0c779 6620
a724f0f4
JB		 6621 /* Get the next token to check for register scaling. */
6622 intel_match_token (cur_token.code);
64a0c779 6623
a724f0f4
JB		 6624 /* Check if this constant is a scaling factor for an index register. */
6625 if (cur_token.code == '*')
6626 {
6627 if (intel_match_token ('*') && cur_token.code == T_REG)
6628 {
6629 const reg_entry *reg = cur_token.reg;
6630
6631 if (!intel_parser.in_bracket)
6632 {
6633 as_bad (_("Register scaling only allowed in memory operands"));
6634 return 0;
6635 }
6636
6637 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
6638 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6639 else if (i.index_reg)
6640 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
6641
6642 /* The constant is followed by `* reg', so it must be
6643 a valid scale. */
6644 i.index_reg = reg;
6645 i.types[this_operand] |= BaseIndex;
6646
6647 /* Set the scale after setting the register (otherwise,
6648 i386_scale will complain) */
6649 if (!i386_scale (save_str))
64a0c779 6650 return 0;
a724f0f4
JB		 6651 intel_match_token (T_REG);
6652
6653 /* Since registers are not part of the displacement
6654 string, we may need to remove any preceding '+' from
6655 the displacement string. */
6656 if (*intel_parser.disp != '\0')
6657 {
6658 char *s = intel_parser.disp;
6659 s += strlen (s) - 1;
6660 if (*s == '+')
6661 *s = '\0';
6662 }
6663
6664 free (save_str);
6665
6666 return 1;
6667 }
64a0c779 6668
a724f0f4
JB		 6669 /* The constant was not used for register scaling. Since we have
6670 already consumed the token following `*' we now need to put it
6671 back in the stream. */
64a0c779 6672 intel_putback_token ();
a724f0f4 6673 }
64a0c779 6674
a724f0f4
JB		 6675 /* Add the constant to the displacement string. */
6676 strcat (intel_parser.disp, save_str);
6677 free (save_str);
64a0c779 6678
a724f0f4
JB		 6679 return 1;
6680 }
64a0c779
DN		 6681 }
6682
64a0c779
DN		 6683 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6684 return 0;
6685}
6686
64a0c779
DN		 6687/* Match the given token against cur_token. If they match, read the next
6688 token from the operand string. */
6689static int
6690intel_match_token (code)
e5cb08ac 6691 int code;
64a0c779
DN		 6692{
6693 if (cur_token.code == code)
6694 {
6695 intel_get_token ();
6696 return 1;
6697 }
6698 else
6699 {
0477af35 6700 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 6701 return 0;
6702 }
6703}
6704
64a0c779
DN		 6705/* Read a new token from intel_parser.op_string and store it in cur_token. */
6706static void
6707intel_get_token ()
6708{
6709 char *end_op;
6710 const reg_entry *reg;
6711 struct intel_token new_token;
6712
6713 new_token.code = T_NIL;
6714 new_token.reg = NULL;
6715 new_token.str = NULL;
6716
4a1805b1 6717 /* Free the memory allocated to the previous token and move
64a0c779
DN		 6718 cur_token to prev_token. */
6719 if (prev_token.str)
6720 free (prev_token.str);
6721
6722 prev_token = cur_token;
6723
6724 /* Skip whitespace. */
6725 while (is_space_char (*intel_parser.op_string))
6726 intel_parser.op_string++;
6727
6728 /* Return an empty token if we find nothing else on the line. */
6729 if (*intel_parser.op_string == '\0')
6730 {
6731 cur_token = new_token;
6732 return;
6733 }
6734
6735 /* The new token cannot be larger than the remainder of the operand
6736 string. */
a724f0f4 6737 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 6738 new_token.str[0] = '\0';
6739
6740 if (strchr ("0123456789", *intel_parser.op_string))
6741 {
6742 char *p = new_token.str;
6743 char *q = intel_parser.op_string;
6744 new_token.code = T_CONST;
6745
6746 /* Allow any kind of identifier char to encompass floating point and
6747 hexadecimal numbers. */
6748 while (is_identifier_char (*q))
6749 *p++ = *q++;
6750 *p = '\0';
6751
6752 /* Recognize special symbol names [0-9][bf]. */
6753 if (strlen (intel_parser.op_string) == 2
4a1805b1 6754 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 6755 || intel_parser.op_string[1] == 'f'))
6756 new_token.code = T_ID;
6757 }
6758
64a0c779
DN		 6759 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6760 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6761 {
6762 new_token.code = T_REG;
6763 new_token.reg = reg;
6764
6765 if (*intel_parser.op_string == REGISTER_PREFIX)
6766 {
6767 new_token.str[0] = REGISTER_PREFIX;
6768 new_token.str[1] = '\0';
6769 }
6770
6771 strcat (new_token.str, reg->reg_name);
6772 }
6773
6774 else if (is_identifier_char (*intel_parser.op_string))
6775 {
6776 char *p = new_token.str;
6777 char *q = intel_parser.op_string;
6778
6779 /* A '.' or '$' followed by an identifier char is an identifier.
6780 Otherwise, it's operator '.' followed by an expression. */
6781 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6782 {
9306ca4a
JB		 6783 new_token.code = '.';
6784 new_token.str[0] = '.';
64a0c779
DN		 6785 new_token.str[1] = '\0';
6786 }
6787 else
6788 {
6789 while (is_identifier_char (*q) || *q == '@')
6790 *p++ = *q++;
6791 *p = '\0';
6792
9306ca4a
JB		 6793 if (strcasecmp (new_token.str, "NOT") == 0)
6794 new_token.code = '~';
6795
6796 else if (strcasecmp (new_token.str, "MOD") == 0)
6797 new_token.code = '%';
6798
6799 else if (strcasecmp (new_token.str, "AND") == 0)
6800 new_token.code = '&';
6801
6802 else if (strcasecmp (new_token.str, "OR") == 0)
6803 new_token.code = '|';
6804
6805 else if (strcasecmp (new_token.str, "XOR") == 0)
6806 new_token.code = '^';
6807
6808 else if (strcasecmp (new_token.str, "SHL") == 0)
6809 new_token.code = T_SHL;
6810
6811 else if (strcasecmp (new_token.str, "SHR") == 0)
6812 new_token.code = T_SHR;
6813
6814 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 6815 new_token.code = T_BYTE;
6816
6817 else if (strcasecmp (new_token.str, "WORD") == 0)
6818 new_token.code = T_WORD;
6819
6820 else if (strcasecmp (new_token.str, "DWORD") == 0)
6821 new_token.code = T_DWORD;
6822
9306ca4a
JB		 6823 else if (strcasecmp (new_token.str, "FWORD") == 0)
6824 new_token.code = T_FWORD;
6825
64a0c779
DN		 6826 else if (strcasecmp (new_token.str, "QWORD") == 0)
6827 new_token.code = T_QWORD;
6828
9306ca4a
JB		 6829 else if (strcasecmp (new_token.str, "TBYTE") == 0
6830 /* XXX remove (gcc still uses it) */
6831 || strcasecmp (new_token.str, "XWORD") == 0)
6832 new_token.code = T_TBYTE;
6833
6834 else if (strcasecmp (new_token.str, "XMMWORD") == 0
6835 || strcasecmp (new_token.str, "OWORD") == 0)
6836 new_token.code = T_XMMWORD;
64a0c779
DN		 6837
6838 else if (strcasecmp (new_token.str, "PTR") == 0)
6839 new_token.code = T_PTR;
6840
6841 else if (strcasecmp (new_token.str, "SHORT") == 0)
6842 new_token.code = T_SHORT;
6843
6844 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6845 {
6846 new_token.code = T_OFFSET;
6847
6848 /* ??? This is not mentioned in the MASM grammar but gcc
6849 makes use of it with -mintel-syntax. OFFSET may be
6850 followed by FLAT: */
6851 if (strncasecmp (q, " FLAT:", 6) == 0)
6852 strcat (new_token.str, " FLAT:");
6853 }
6854
6855 /* ??? This is not mentioned in the MASM grammar. */
6856 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 6857 {
6858 new_token.code = T_OFFSET;
6859 if (*q == ':')
6860 strcat (new_token.str, ":");
6861 else
6862 as_bad (_("`:' expected"));
6863 }
64a0c779
DN		 6864
6865 else
6866 new_token.code = T_ID;
6867 }
6868 }
6869
9306ca4a
JB		 6870 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
6871 {
6872 new_token.code = *intel_parser.op_string;
6873 new_token.str[0] = *intel_parser.op_string;
6874 new_token.str[1] = '\0';
6875 }
6876
6877 else if (strchr ("<>", *intel_parser.op_string)
6878 && *intel_parser.op_string == *(intel_parser.op_string + 1))
6879 {
6880 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
6881 new_token.str[0] = *intel_parser.op_string;
6882 new_token.str[1] = *intel_parser.op_string;
6883 new_token.str[2] = '\0';
6884 }
6885
64a0c779 6886 else
0477af35 6887 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 6888
6889 intel_parser.op_string += strlen (new_token.str);
6890 cur_token = new_token;
6891}
6892
64a0c779
DN		 6893/* Put cur_token back into the token stream and make cur_token point to
6894 prev_token. */
6895static void
6896intel_putback_token ()
6897{
a724f0f4
JB		 6898 if (cur_token.code != T_NIL)
6899 {
6900 intel_parser.op_string -= strlen (cur_token.str);
6901 free (cur_token.str);
6902 }
64a0c779 6903 cur_token = prev_token;
4a1805b1 6904
64a0c779
DN		 6905 /* Forget prev_token. */
6906 prev_token.code = T_NIL;
6907 prev_token.reg = NULL;
6908 prev_token.str = NULL;
6909}
54cfded0 6910
a4447b93 6911int
54cfded0
AM		 6912tc_x86_regname_to_dw2regnum (const char *regname)
6913{
6914 unsigned int regnum;
6915 unsigned int regnames_count;
089dfecd 6916 static const char *const regnames_32[] =
54cfded0 6917 {
a4447b93
RH		 6918 "eax", "ecx", "edx", "ebx",
6919 "esp", "ebp", "esi", "edi",
089dfecd
JB		 6920 "eip", "eflags", NULL,
6921 "st0", "st1", "st2", "st3",
6922 "st4", "st5", "st6", "st7",
6923 NULL, NULL,
6924 "xmm0", "xmm1", "xmm2", "xmm3",
6925 "xmm4", "xmm5", "xmm6", "xmm7",
6926 "mm0", "mm1", "mm2", "mm3",
6927 "mm4", "mm5", "mm6", "mm7"
54cfded0 6928 };
089dfecd 6929 static const char *const regnames_64[] =
54cfded0 6930 {
089dfecd
JB		 6931 "rax", "rdx", "rcx", "rbx",
6932 "rsi", "rdi", "rbp", "rsp",
6933 "r8", "r9", "r10", "r11",
54cfded0 6934 "r12", "r13", "r14", "r15",
089dfecd
JB		 6935 "rip",
6936 "xmm0", "xmm1", "xmm2", "xmm3",
6937 "xmm4", "xmm5", "xmm6", "xmm7",
6938 "xmm8", "xmm9", "xmm10", "xmm11",
6939 "xmm12", "xmm13", "xmm14", "xmm15",
6940 "st0", "st1", "st2", "st3",
6941 "st4", "st5", "st6", "st7",
6942 "mm0", "mm1", "mm2", "mm3",
6943 "mm4", "mm5", "mm6", "mm7"
54cfded0 6944 };
089dfecd 6945 const char *const *regnames;
54cfded0
AM		 6946
6947 if (flag_code == CODE_64BIT)
6948 {
6949 regnames = regnames_64;
0cea6190 6950 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 6951 }
6952 else
6953 {
6954 regnames = regnames_32;
0cea6190 6955 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 6956 }
6957
6958 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 6959 if (regnames[regnum] != NULL
6960 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 6961 return regnum;
6962
54cfded0
AM		 6963 return -1;
6964}
6965
6966void
6967tc_x86_frame_initial_instructions (void)
6968{
a4447b93
RH		 6969 static unsigned int sp_regno;
6970
6971 if (!sp_regno)
6972 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6973 ? "rsp" : "esp");
6974
6975 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6976 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 6977}
d2b2c203
DJ		 6978
6979int
6980i386_elf_section_type (const char *str, size_t len)
6981{
6982 if (flag_code == CODE_64BIT
6983 && len == sizeof ("unwind") - 1
6984 && strncmp (str, "unwind", 6) == 0)
6985 return SHT_X86_64_UNWIND;
6986
6987 return -1;
6988}
bb41ade5
AM		 6989
6990#ifdef TE_PE
6991void
6992tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
6993{
6994 expressionS expr;
6995
6996 expr.X_op = O_secrel;
6997 expr.X_add_symbol = symbol;
6998 expr.X_add_number = 0;
6999 emit_expr (&expr, size);
7000}
7001#endif
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