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* config/tc-mips.c (nopic_need_relax): Handle -fdata-sections
[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
252b5132 1/* i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
67a4f2b7 3 2000, 2001, 2002, 2003, 2004, 2005, 2006
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
252b5132 35#include "opcode/i386.h"
d2b2c203 36#include "elf/x86-64.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
252b5132
RH		 46#ifndef SCALE1_WHEN_NO_INDEX
47/* Specifying a scale factor besides 1 when there is no index is
48 futile. eg. `mov (%ebx,2),%al' does exactly the same as
49 `mov (%ebx),%al'. To slavishly follow what the programmer
50 specified, set SCALE1_WHEN_NO_INDEX to 0. */
51#define SCALE1_WHEN_NO_INDEX 1
52#endif
53
29b0f896
AM		 54#ifndef DEFAULT_ARCH
55#define DEFAULT_ARCH "i386"
246fcdee 56#endif
252b5132 57
edde18a5
AM		 58#ifndef INLINE
59#if __GNUC__ >= 2
60#define INLINE __inline__
61#else
62#define INLINE
63#endif
64#endif
65
29b0f896
AM		 66static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
67static INLINE int fits_in_signed_byte PARAMS ((offsetT));
68static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
69static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
70static INLINE int fits_in_signed_word PARAMS ((offsetT));
71static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
72static INLINE int fits_in_signed_long PARAMS ((offsetT));
847f7ad4
AM		 73static int smallest_imm_type PARAMS ((offsetT));
74static offsetT offset_in_range PARAMS ((offsetT, int));
252b5132 75static int add_prefix PARAMS ((unsigned int));
3e73aa7c 76static void set_code_flag PARAMS ((int));
47926f60 77static void set_16bit_gcc_code_flag PARAMS ((int));
252b5132 78static void set_intel_syntax PARAMS ((int));
e413e4e9 79static void set_cpu_arch PARAMS ((int));
6482c264
NC		 80#ifdef TE_PE
81static void pe_directive_secrel PARAMS ((int));
82#endif
d182319b 83static void signed_cons PARAMS ((int));
29b0f896
AM		 84static char *output_invalid PARAMS ((int c));
85static int i386_operand PARAMS ((char *operand_string));
86static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
87static const reg_entry *parse_register PARAMS ((char *reg_string,
88 char **end_op));
89static char *parse_insn PARAMS ((char *, char *));
90static char *parse_operands PARAMS ((char *, const char *));
91static void swap_operands PARAMS ((void));
92static void optimize_imm PARAMS ((void));
93static void optimize_disp PARAMS ((void));
94static int match_template PARAMS ((void));
95static int check_string PARAMS ((void));
96static int process_suffix PARAMS ((void));
97static int check_byte_reg PARAMS ((void));
98static int check_long_reg PARAMS ((void));
99static int check_qword_reg PARAMS ((void));
100static int check_word_reg PARAMS ((void));
101static int finalize_imm PARAMS ((void));
102static int process_operands PARAMS ((void));
103static const seg_entry *build_modrm_byte PARAMS ((void));
104static void output_insn PARAMS ((void));
105static void output_branch PARAMS ((void));
106static void output_jump PARAMS ((void));
107static void output_interseg_jump PARAMS ((void));
2bbd9c25
JJ		 108static void output_imm PARAMS ((fragS *insn_start_frag,
109 offsetT insn_start_off));
110static void output_disp PARAMS ((fragS *insn_start_frag,
111 offsetT insn_start_off));
29b0f896
AM		 112#ifndef I386COFF
113static void s_bss PARAMS ((int));
252b5132 114#endif
17d4e2a2
L		 115#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
116static void handle_large_common (int small ATTRIBUTE_UNUSED);
117#endif
252b5132 118
a847613f 119static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 120
252b5132 121/* 'md_assemble ()' gathers together information and puts it into a
47926f60 122 i386_insn. */
252b5132 123
520dc8e8
AM		 124union i386_op
125 {
126 expressionS *disps;
127 expressionS *imms;
128 const reg_entry *regs;
129 };
130
252b5132
RH		 131struct _i386_insn
132 {
47926f60 133 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 134 template tm;
135
136 /* SUFFIX holds the instruction mnemonic suffix if given.
137 (e.g. 'l' for 'movl') */
138 char suffix;
139
47926f60 140 /* OPERANDS gives the number of given operands. */
252b5132
RH		 141 unsigned int operands;
142
143 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
144 of given register, displacement, memory operands and immediate
47926f60 145 operands. */
252b5132
RH		 146 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
147
148 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 149 use OP[i] for the corresponding operand. */
252b5132
RH		 150 unsigned int types[MAX_OPERANDS];
151
520dc8e8
AM		 152 /* Displacement expression, immediate expression, or register for each
153 operand. */
154 union i386_op op[MAX_OPERANDS];
252b5132 155
3e73aa7c
JH		 156 /* Flags for operands. */
157 unsigned int flags[MAX_OPERANDS];
158#define Operand_PCrel 1
159
252b5132 160 /* Relocation type for operand */
f86103b7 161 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 162
252b5132
RH		 163 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
164 the base index byte below. */
165 const reg_entry *base_reg;
166 const reg_entry *index_reg;
167 unsigned int log2_scale_factor;
168
169 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 170 explicit segment overrides are given. */
ce8a8b2f 171 const seg_entry *seg[2];
252b5132
RH		 172
173 /* PREFIX holds all the given prefix opcodes (usually null).
174 PREFIXES is the number of prefix opcodes. */
175 unsigned int prefixes;
176 unsigned char prefix[MAX_PREFIXES];
177
178 /* RM and SIB are the modrm byte and the sib byte where the
179 addressing modes of this insn are encoded. */
180
181 modrm_byte rm;
3e73aa7c 182 rex_byte rex;
252b5132
RH		 183 sib_byte sib;
184 };
185
186typedef struct _i386_insn i386_insn;
187
188/* List of chars besides those in app.c:symbol_chars that can start an
189 operand. Used to prevent the scrubber eating vital white-space. */
32137342 190const char extra_symbol_chars[] = "*%-(["
252b5132 191#ifdef LEX_AT
32137342
NC		 192 "@"
193#endif
194#ifdef LEX_QM
195 "?"
252b5132 196#endif
32137342 197 ;
252b5132 198
29b0f896
AM		 199#if (defined (TE_I386AIX) \
200 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 201 && !defined (TE_GNU) \
29b0f896 202 && !defined (TE_LINUX) \
32137342 203 && !defined (TE_NETWARE) \
29b0f896
AM		 204 && !defined (TE_FreeBSD) \
205 && !defined (TE_NetBSD)))
252b5132 206/* This array holds the chars that always start a comment. If the
b3b91714
AM		 207 pre-processor is disabled, these aren't very useful. The option
208 --divide will remove '/' from this list. */
209const char *i386_comment_chars = "#/";
210#define SVR4_COMMENT_CHARS 1
252b5132 211#define PREFIX_SEPARATOR '\\'
252b5132 212
b3b91714
AM		 213#else
214const char *i386_comment_chars = "#";
215#define PREFIX_SEPARATOR '/'
216#endif
217
252b5132
RH		 218/* This array holds the chars that only start a comment at the beginning of
219 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 220 .line and .file directives will appear in the pre-processed output.
221 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 222 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 223 #NO_APP at the beginning of its output.
224 Also note that comments started like this one will always work if
252b5132 225 '/' isn't otherwise defined. */
b3b91714 226const char line_comment_chars[] = "#/";
252b5132 227
63a0b638 228const char line_separator_chars[] = ";";
252b5132 229
ce8a8b2f
AM		 230/* Chars that can be used to separate mant from exp in floating point
231 nums. */
252b5132
RH		 232const char EXP_CHARS[] = "eE";
233
ce8a8b2f
AM		 234/* Chars that mean this number is a floating point constant
235 As in 0f12.456
236 or 0d1.2345e12. */
252b5132
RH		 237const char FLT_CHARS[] = "fFdDxX";
238
ce8a8b2f 239/* Tables for lexical analysis. */
252b5132
RH		 240static char mnemonic_chars[256];
241static char register_chars[256];
242static char operand_chars[256];
243static char identifier_chars[256];
244static char digit_chars[256];
245
ce8a8b2f 246/* Lexical macros. */
252b5132
RH		 247#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
248#define is_operand_char(x) (operand_chars[(unsigned char) x])
249#define is_register_char(x) (register_chars[(unsigned char) x])
250#define is_space_char(x) ((x) == ' ')
251#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
252#define is_digit_char(x) (digit_chars[(unsigned char) x])
253
0234cb7c 254/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 255static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
256
257/* md_assemble() always leaves the strings it's passed unaltered. To
258 effect this we maintain a stack of saved characters that we've smashed
259 with '\0's (indicating end of strings for various sub-fields of the
47926f60 260 assembler instruction). */
252b5132 261static char save_stack[32];
ce8a8b2f 262static char *save_stack_p;
252b5132
RH		 263#define END_STRING_AND_SAVE(s) \
264 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
265#define RESTORE_END_STRING(s) \
266 do { *(s) = *--save_stack_p; } while (0)
267
47926f60 268/* The instruction we're assembling. */
252b5132
RH		 269static i386_insn i;
270
271/* Possible templates for current insn. */
272static const templates *current_templates;
273
47926f60 274/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
252b5132
RH		 275static expressionS disp_expressions[2], im_expressions[2];
276
47926f60
KH		 277/* Current operand we are working on. */
278static int this_operand;
252b5132 279
3e73aa7c
JH		 280/* We support four different modes. FLAG_CODE variable is used to distinguish
281 these. */
282
283enum flag_code {
284 CODE_32BIT,
285 CODE_16BIT,
286 CODE_64BIT };
f3c180ae 287#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
3e73aa7c
JH		 288
289static enum flag_code flag_code;
4fa24527 290static unsigned int object_64bit;
3e73aa7c
JH		 291static int use_rela_relocations = 0;
292
293/* The names used to print error messages. */
b77a7acd 294static const char *flag_code_names[] =
3e73aa7c
JH		 295 {
296 "32",
297 "16",
298 "64"
299 };
252b5132 300
47926f60
KH		 301/* 1 for intel syntax,
302 0 if att syntax. */
303static int intel_syntax = 0;
252b5132 304
47926f60
KH		 305/* 1 if register prefix % not required. */
306static int allow_naked_reg = 0;
252b5132 307
47926f60
KH		 308/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
309 leave, push, and pop instructions so that gcc has the same stack
310 frame as in 32 bit mode. */
311static char stackop_size = '\0';
eecb386c 312
12b55ccc
L		 313/* Non-zero to optimize code alignment. */
314int optimize_align_code = 1;
315
47926f60
KH		 316/* Non-zero to quieten some warnings. */
317static int quiet_warnings = 0;
a38cf1db 318
47926f60
KH		 319/* CPU name. */
320static const char *cpu_arch_name = NULL;
5c6af06e 321static const char *cpu_sub_arch_name = NULL;
a38cf1db 322
47926f60 323/* CPU feature flags. */
29b0f896 324static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
a38cf1db 325
9103f4f4
L		 326/* Cpu we are generating instructions for. */
327static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
328
329/* CPU feature flags of cpu we are generating instructions for. */
330static unsigned int cpu_arch_tune_flags = 0;
331
332/* CPU feature flags of instruction set architecture used. */
333static unsigned int cpu_arch_isa_flags = 0;
334
fddf5b5b
AM		 335/* If set, conditional jumps are not automatically promoted to handle
336 larger than a byte offset. */
337static unsigned int no_cond_jump_promotion = 0;
338
29b0f896 339/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 340static symbolS *GOT_symbol;
29b0f896 341
a4447b93
RH		 342/* The dwarf2 return column, adjusted for 32 or 64 bit. */
343unsigned int x86_dwarf2_return_column;
344
345/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
346int x86_cie_data_alignment;
347
252b5132 348/* Interface to relax_segment.
fddf5b5b
AM		 349 There are 3 major relax states for 386 jump insns because the
350 different types of jumps add different sizes to frags when we're
351 figuring out what sort of jump to choose to reach a given label. */
252b5132 352
47926f60 353/* Types. */
93c2a809
AM		 354#define UNCOND_JUMP 0
355#define COND_JUMP 1
356#define COND_JUMP86 2
fddf5b5b 357
47926f60 358/* Sizes. */
252b5132
RH		 359#define CODE16 1
360#define SMALL 0
29b0f896 361#define SMALL16 (SMALL | CODE16)
252b5132 362#define BIG 2
29b0f896 363#define BIG16 (BIG | CODE16)
252b5132
RH		 364
365#ifndef INLINE
366#ifdef __GNUC__
367#define INLINE __inline__
368#else
369#define INLINE
370#endif
371#endif
372
fddf5b5b
AM		 373#define ENCODE_RELAX_STATE(type, size) \
374 ((relax_substateT) (((type) << 2) | (size)))
375#define TYPE_FROM_RELAX_STATE(s) \
376 ((s) >> 2)
377#define DISP_SIZE_FROM_RELAX_STATE(s) \
378 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 379
380/* This table is used by relax_frag to promote short jumps to long
381 ones where necessary. SMALL (short) jumps may be promoted to BIG
382 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
383 don't allow a short jump in a 32 bit code segment to be promoted to
384 a 16 bit offset jump because it's slower (requires data size
385 prefix), and doesn't work, unless the destination is in the bottom
386 64k of the code segment (The top 16 bits of eip are zeroed). */
387
388const relax_typeS md_relax_table[] =
389{
24eab124
AM		 390 /* The fields are:
391 1) most positive reach of this state,
392 2) most negative reach of this state,
93c2a809 393 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 394 4) which index into the table to try if we can't fit into this one. */
252b5132 395
fddf5b5b 396 /* UNCOND_JUMP states. */
93c2a809
AM		 397 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
399 /* dword jmp adds 4 bytes to frag:
400 0 extra opcode bytes, 4 displacement bytes. */
252b5132 401 {0, 0, 4, 0},
93c2a809
AM		 402 /* word jmp adds 2 byte2 to frag:
403 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 404 {0, 0, 2, 0},
405
93c2a809
AM		 406 /* COND_JUMP states. */
407 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
409 /* dword conditionals adds 5 bytes to frag:
410 1 extra opcode byte, 4 displacement bytes. */
411 {0, 0, 5, 0},
fddf5b5b 412 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 413 1 extra opcode byte, 2 displacement bytes. */
414 {0, 0, 3, 0},
415
416 /* COND_JUMP86 states. */
417 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
419 /* dword conditionals adds 5 bytes to frag:
420 1 extra opcode byte, 4 displacement bytes. */
421 {0, 0, 5, 0},
422 /* word conditionals add 4 bytes to frag:
423 1 displacement byte and a 3 byte long branch insn. */
424 {0, 0, 4, 0}
252b5132
RH		 425};
426
9103f4f4
L		 427static const arch_entry cpu_arch[] =
428{
429 {"generic32", PROCESSOR_GENERIC32,
430 Cpu086|Cpu186|Cpu286|Cpu386},
431 {"generic64", PROCESSOR_GENERIC64,
432 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
433 |CpuMMX2|CpuSSE|CpuSSE2},
434 {"i8086", PROCESSOR_UNKNOWN,
435 Cpu086},
436 {"i186", PROCESSOR_UNKNOWN,
437 Cpu086|Cpu186},
438 {"i286", PROCESSOR_UNKNOWN,
439 Cpu086|Cpu186|Cpu286},
440 {"i386", PROCESSOR_GENERIC32,
441 Cpu086|Cpu186|Cpu286|Cpu386},
442 {"i486", PROCESSOR_I486,
443 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486},
444 {"i586", PROCESSOR_PENTIUM,
445 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
446 {"i686", PROCESSOR_PENTIUMPRO,
447 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
448 {"pentium", PROCESSOR_PENTIUM,
449 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586},
450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
451 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686},
452 {"pentiumii", PROCESSOR_PENTIUMPRO,
453 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX},
454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
455 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuMMX2
456 |CpuSSE},
457 {"pentium4", PROCESSOR_PENTIUM4,
458 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
459 |CpuMMX2|CpuSSE|CpuSSE2},
460 {"prescott", PROCESSOR_NOCONA,
461 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
462 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
463 {"nocona", PROCESSOR_NOCONA,
464 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
465 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
466 {"yonah", PROCESSOR_YONAH,
467 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
468 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
469 {"merom", PROCESSOR_MEROM,
470 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX
471 |CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuMNI},
472 {"k6", PROCESSOR_K6,
473 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX},
474 {"k6_2", PROCESSOR_K6,
475 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow},
476 {"athlon", PROCESSOR_ATHLON,
477 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
478 |CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
479 {"sledgehammer", PROCESSOR_K8,
480 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
481 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
482 {"opteron", PROCESSOR_K8,
483 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
484 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
485 {"k8", PROCESSOR_K8,
486 Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon
487 |CpuSledgehammer|CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA|CpuSSE|CpuSSE2},
488 {".mmx", PROCESSOR_UNKNOWN,
489 CpuMMX},
490 {".sse", PROCESSOR_UNKNOWN,
491 CpuMMX|CpuMMX2|CpuSSE},
492 {".sse2", PROCESSOR_UNKNOWN,
493 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2},
494 {".sse3", PROCESSOR_UNKNOWN,
495 CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3},
496 {".3dnow", PROCESSOR_UNKNOWN,
497 CpuMMX|Cpu3dnow},
498 {".3dnowa", PROCESSOR_UNKNOWN,
499 CpuMMX|CpuMMX2|Cpu3dnow|Cpu3dnowA},
500 {".padlock", PROCESSOR_UNKNOWN,
501 CpuPadLock},
502 {".pacifica", PROCESSOR_UNKNOWN,
503 CpuSVME},
504 {".svme", PROCESSOR_UNKNOWN,
505 CpuSVME}
e413e4e9
AM		 506};
507
29b0f896
AM		 508const pseudo_typeS md_pseudo_table[] =
509{
510#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
511 {"align", s_align_bytes, 0},
512#else
513 {"align", s_align_ptwo, 0},
514#endif
515 {"arch", set_cpu_arch, 0},
516#ifndef I386COFF
517 {"bss", s_bss, 0},
518#endif
519 {"ffloat", float_cons, 'f'},
520 {"dfloat", float_cons, 'd'},
521 {"tfloat", float_cons, 'x'},
522 {"value", cons, 2},
d182319b 523 {"slong", signed_cons, 4},
29b0f896
AM		 524 {"noopt", s_ignore, 0},
525 {"optim", s_ignore, 0},
526 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
527 {"code16", set_code_flag, CODE_16BIT},
528 {"code32", set_code_flag, CODE_32BIT},
529 {"code64", set_code_flag, CODE_64BIT},
530 {"intel_syntax", set_intel_syntax, 1},
531 {"att_syntax", set_intel_syntax, 0},
3b22753a
L		 532#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
533 {"largecomm", handle_large_common, 0},
07a53e5c
RH		 534#else
535 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
536 {"loc", dwarf2_directive_loc, 0},
537 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 538#endif
6482c264
NC		 539#ifdef TE_PE
540 {"secrel32", pe_directive_secrel, 0},
541#endif
29b0f896
AM		 542 {0, 0, 0}
543};
544
545/* For interface with expression (). */
546extern char *input_line_pointer;
547
548/* Hash table for instruction mnemonic lookup. */
549static struct hash_control *op_hash;
550
551/* Hash table for register lookup. */
552static struct hash_control *reg_hash;
553\f
252b5132
RH		 554void
555i386_align_code (fragP, count)
556 fragS *fragP;
557 int count;
558{
ce8a8b2f
AM		 559 /* Various efficient no-op patterns for aligning code labels.
560 Note: Don't try to assemble the instructions in the comments.
561 0L and 0w are not legal. */
252b5132
RH		 562 static const char f32_1[] =
563 {0x90}; /* nop */
564 static const char f32_2[] =
565 {0x89,0xf6}; /* movl %esi,%esi */
566 static const char f32_3[] =
567 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
568 static const char f32_4[] =
569 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
570 static const char f32_5[] =
571 {0x90, /* nop */
572 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
573 static const char f32_6[] =
574 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
575 static const char f32_7[] =
576 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
577 static const char f32_8[] =
578 {0x90, /* nop */
579 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
580 static const char f32_9[] =
581 {0x89,0xf6, /* movl %esi,%esi */
582 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
583 static const char f32_10[] =
584 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
585 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
586 static const char f32_11[] =
587 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
588 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
589 static const char f32_12[] =
590 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
591 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
592 static const char f32_13[] =
593 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_14[] =
596 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_15[] =
599 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
600 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
c3332e24
AM		 601 static const char f16_3[] =
602 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 603 static const char f16_4[] =
604 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
605 static const char f16_5[] =
606 {0x90, /* nop */
607 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
608 static const char f16_6[] =
609 {0x89,0xf6, /* mov %si,%si */
610 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
611 static const char f16_7[] =
612 {0x8d,0x74,0x00, /* lea 0(%si),%si */
613 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
614 static const char f16_8[] =
615 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
616 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
617 static const char *const f32_patt[] = {
618 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
619 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
620 };
621 static const char *const f16_patt[] = {
c3332e24 622 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
252b5132
RH		 623 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
624 };
625
33fef721
JH		 626 if (count <= 0 || count > 15)
627 return;
3e73aa7c 628
33fef721
JH		 629 /* The recommended way to pad 64bit code is to use NOPs preceded by
630 maximally four 0x66 prefixes. Balance the size of nops. */
631 if (flag_code == CODE_64BIT)
252b5132 632 {
33fef721
JH		 633 int i;
634 int nnops = (count + 3) / 4;
635 int len = count / nnops;
636 int remains = count - nnops * len;
637 int pos = 0;
638
639 for (i = 0; i < remains; i++)
252b5132 640 {
33fef721
JH		 641 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
642 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
643 pos += len + 1;
644 }
645 for (; i < nnops; i++)
646 {
647 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
648 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
649 pos += len;
252b5132 650 }
252b5132 651 }
33fef721
JH		 652 else
653 if (flag_code == CODE_16BIT)
654 {
655 memcpy (fragP->fr_literal + fragP->fr_fix,
656 f16_patt[count - 1], count);
657 if (count > 8)
658 /* Adjust jump offset. */
659 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
660 }
661 else
662 memcpy (fragP->fr_literal + fragP->fr_fix,
663 f32_patt[count - 1], count);
664 fragP->fr_var = count;
252b5132
RH		 665}
666
252b5132
RH		 667static INLINE unsigned int
668mode_from_disp_size (t)
669 unsigned int t;
670{
3e73aa7c 671 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
252b5132
RH		 672}
673
674static INLINE int
675fits_in_signed_byte (num)
847f7ad4 676 offsetT num;
252b5132
RH		 677{
678 return (num >= -128) && (num <= 127);
47926f60 679}
252b5132
RH		 680
681static INLINE int
682fits_in_unsigned_byte (num)
847f7ad4 683 offsetT num;
252b5132
RH		 684{
685 return (num & 0xff) == num;
47926f60 686}
252b5132
RH		 687
688static INLINE int
689fits_in_unsigned_word (num)
847f7ad4 690 offsetT num;
252b5132
RH		 691{
692 return (num & 0xffff) == num;
47926f60 693}
252b5132
RH		 694
695static INLINE int
696fits_in_signed_word (num)
847f7ad4 697 offsetT num;
252b5132
RH		 698{
699 return (-32768 <= num) && (num <= 32767);
47926f60 700}
3e73aa7c
JH		 701static INLINE int
702fits_in_signed_long (num)
703 offsetT num ATTRIBUTE_UNUSED;
704{
705#ifndef BFD64
706 return 1;
707#else
708 return (!(((offsetT) -1 << 31) & num)
709 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
710#endif
711} /* fits_in_signed_long() */
712static INLINE int
713fits_in_unsigned_long (num)
714 offsetT num ATTRIBUTE_UNUSED;
715{
716#ifndef BFD64
717 return 1;
718#else
719 return (num & (((offsetT) 2 << 31) - 1)) == num;
720#endif
721} /* fits_in_unsigned_long() */
252b5132
RH		 722
723static int
724smallest_imm_type (num)
847f7ad4 725 offsetT num;
252b5132 726{
a847613f 727 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
e413e4e9
AM		 728 {
729 /* This code is disabled on the 486 because all the Imm1 forms
730 in the opcode table are slower on the i486. They're the
731 versions with the implicitly specified single-position
732 displacement, which has another syntax if you really want to
733 use that form. */
734 if (num == 1)
3e73aa7c 735 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
e413e4e9 736 }
252b5132 737 return (fits_in_signed_byte (num)
3e73aa7c 738 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 739 : fits_in_unsigned_byte (num)
3e73aa7c 740 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
252b5132 741 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
3e73aa7c
JH		 742 ? (Imm16 | Imm32 | Imm32S | Imm64)
743 : fits_in_signed_long (num)
744 ? (Imm32 | Imm32S | Imm64)
745 : fits_in_unsigned_long (num)
746 ? (Imm32 | Imm64)
747 : Imm64);
47926f60 748}
252b5132 749
847f7ad4
AM		 750static offsetT
751offset_in_range (val, size)
752 offsetT val;
753 int size;
754{
508866be 755 addressT mask;
ba2adb93 756
847f7ad4
AM		 757 switch (size)
758 {
508866be
L		 759 case 1: mask = ((addressT) 1 << 8) - 1; break;
760 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 761 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 762#ifdef BFD64
763 case 8: mask = ((addressT) 2 << 63) - 1; break;
764#endif
47926f60 765 default: abort ();
847f7ad4
AM		 766 }
767
ba2adb93 768 /* If BFD64, sign extend val. */
3e73aa7c
JH		 769 if (!use_rela_relocations)
770 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
771 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 772
47926f60 773 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 774 {
775 char buf1[40], buf2[40];
776
777 sprint_value (buf1, val);
778 sprint_value (buf2, val & mask);
779 as_warn (_("%s shortened to %s"), buf1, buf2);
780 }
781 return val & mask;
782}
783
252b5132
RH		 784/* Returns 0 if attempting to add a prefix where one from the same
785 class already exists, 1 if non rep/repne added, 2 if rep/repne
786 added. */
787static int
788add_prefix (prefix)
789 unsigned int prefix;
790{
791 int ret = 1;
b1905489 792 unsigned int q;
252b5132 793
29b0f896
AM		 794 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
795 && flag_code == CODE_64BIT)
b1905489
JB		 796 {
797 if ((i.prefix[REX_PREFIX] & prefix & REX_MODE64)
798 || ((i.prefix[REX_PREFIX] & (REX_EXTX | REX_EXTY | REX_EXTZ))
799 && (prefix & (REX_EXTX | REX_EXTY | REX_EXTZ))))
800 ret = 0;
801 q = REX_PREFIX;
802 }
3e73aa7c 803 else
b1905489
JB		 804 {
805 switch (prefix)
806 {
807 default:
808 abort ();
809
810 case CS_PREFIX_OPCODE:
811 case DS_PREFIX_OPCODE:
812 case ES_PREFIX_OPCODE:
813 case FS_PREFIX_OPCODE:
814 case GS_PREFIX_OPCODE:
815 case SS_PREFIX_OPCODE:
816 q = SEG_PREFIX;
817 break;
818
819 case REPNE_PREFIX_OPCODE:
820 case REPE_PREFIX_OPCODE:
821 ret = 2;
822 /* fall thru */
823 case LOCK_PREFIX_OPCODE:
824 q = LOCKREP_PREFIX;
825 break;
826
827 case FWAIT_OPCODE:
828 q = WAIT_PREFIX;
829 break;
830
831 case ADDR_PREFIX_OPCODE:
832 q = ADDR_PREFIX;
833 break;
834
835 case DATA_PREFIX_OPCODE:
836 q = DATA_PREFIX;
837 break;
838 }
839 if (i.prefix[q] != 0)
840 ret = 0;
841 }
252b5132 842
b1905489 843 if (ret)
252b5132 844 {
b1905489
JB		 845 if (!i.prefix[q])
846 ++i.prefixes;
847 i.prefix[q] |= prefix;
252b5132 848 }
b1905489
JB		 849 else
850 as_bad (_("same type of prefix used twice"));
252b5132 851
252b5132
RH		 852 return ret;
853}
854
855static void
3e73aa7c 856set_code_flag (value)
e5cb08ac 857 int value;
eecb386c 858{
3e73aa7c
JH		 859 flag_code = value;
860 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
861 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
862 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
863 {
864 as_bad (_("64bit mode not supported on this CPU."));
865 }
866 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
867 {
868 as_bad (_("32bit mode not supported on this CPU."));
869 }
eecb386c
AM		 870 stackop_size = '\0';
871}
872
873static void
3e73aa7c
JH		 874set_16bit_gcc_code_flag (new_code_flag)
875 int new_code_flag;
252b5132 876{
3e73aa7c
JH		 877 flag_code = new_code_flag;
878 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
879 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
9306ca4a 880 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 881}
882
883static void
884set_intel_syntax (syntax_flag)
eecb386c 885 int syntax_flag;
252b5132
RH		 886{
887 /* Find out if register prefixing is specified. */
888 int ask_naked_reg = 0;
889
890 SKIP_WHITESPACE ();
29b0f896 891 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 892 {
893 char *string = input_line_pointer;
894 int e = get_symbol_end ();
895
47926f60 896 if (strcmp (string, "prefix") == 0)
252b5132 897 ask_naked_reg = 1;
47926f60 898 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 899 ask_naked_reg = -1;
900 else
d0b47220 901 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 902 *input_line_pointer = e;
903 }
904 demand_empty_rest_of_line ();
c3332e24 905
252b5132
RH		 906 intel_syntax = syntax_flag;
907
908 if (ask_naked_reg == 0)
f86103b7
AM		 909 allow_naked_reg = (intel_syntax
910 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 911 else
912 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a
JB		 913
914 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
915 identifier_chars['$'] = intel_syntax ? '$' : 0;
252b5132
RH		 916}
917
e413e4e9
AM		 918static void
919set_cpu_arch (dummy)
47926f60 920 int dummy ATTRIBUTE_UNUSED;
e413e4e9 921{
47926f60 922 SKIP_WHITESPACE ();
e413e4e9 923
29b0f896 924 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 925 {
926 char *string = input_line_pointer;
927 int e = get_symbol_end ();
9103f4f4 928 unsigned int i;
e413e4e9 929
9103f4f4 930 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 931 {
932 if (strcmp (string, cpu_arch[i].name) == 0)
933 {
5c6af06e
JB		 934 if (*string != '.')
935 {
936 cpu_arch_name = cpu_arch[i].name;
937 cpu_sub_arch_name = NULL;
938 cpu_arch_flags = (cpu_arch[i].flags
939 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
9103f4f4 940 cpu_arch_isa_flags = cpu_arch[i].flags;
5c6af06e
JB		 941 break;
942 }
943 if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags)
944 {
945 cpu_sub_arch_name = cpu_arch[i].name;
946 cpu_arch_flags |= cpu_arch[i].flags;
947 }
948 *input_line_pointer = e;
949 demand_empty_rest_of_line ();
950 return;
e413e4e9
AM		 951 }
952 }
9103f4f4 953 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 954 as_bad (_("no such architecture: `%s'"), string);
955
956 *input_line_pointer = e;
957 }
958 else
959 as_bad (_("missing cpu architecture"));
960
fddf5b5b
AM		 961 no_cond_jump_promotion = 0;
962 if (*input_line_pointer == ','
29b0f896 963 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 964 {
965 char *string = ++input_line_pointer;
966 int e = get_symbol_end ();
967
968 if (strcmp (string, "nojumps") == 0)
969 no_cond_jump_promotion = 1;
970 else if (strcmp (string, "jumps") == 0)
971 ;
972 else
973 as_bad (_("no such architecture modifier: `%s'"), string);
974
975 *input_line_pointer = e;
976 }
977
e413e4e9
AM		 978 demand_empty_rest_of_line ();
979}
980
b9d79e03
JH		 981unsigned long
982i386_mach ()
983{
984 if (!strcmp (default_arch, "x86_64"))
985 return bfd_mach_x86_64;
986 else if (!strcmp (default_arch, "i386"))
987 return bfd_mach_i386_i386;
988 else
989 as_fatal (_("Unknown architecture"));
990}
b9d79e03 991\f
252b5132
RH		 992void
993md_begin ()
994{
995 const char *hash_err;
996
47926f60 997 /* Initialize op_hash hash table. */
252b5132
RH		 998 op_hash = hash_new ();
999
1000 {
29b0f896
AM		 1001 const template *optab;
1002 templates *core_optab;
252b5132 1003
47926f60
KH		 1004 /* Setup for loop. */
1005 optab = i386_optab;
252b5132
RH		 1006 core_optab = (templates *) xmalloc (sizeof (templates));
1007 core_optab->start = optab;
1008
1009 while (1)
1010 {
1011 ++optab;
1012 if (optab->name == NULL
1013 || strcmp (optab->name, (optab - 1)->name) != 0)
1014 {
1015 /* different name --> ship out current template list;
47926f60 1016 add to hash table; & begin anew. */
252b5132
RH		 1017 core_optab->end = optab;
1018 hash_err = hash_insert (op_hash,
1019 (optab - 1)->name,
1020 (PTR) core_optab);
1021 if (hash_err)
1022 {
252b5132
RH		 1023 as_fatal (_("Internal Error: Can't hash %s: %s"),
1024 (optab - 1)->name,
1025 hash_err);
1026 }
1027 if (optab->name == NULL)
1028 break;
1029 core_optab = (templates *) xmalloc (sizeof (templates));
1030 core_optab->start = optab;
1031 }
1032 }
1033 }
1034
47926f60 1035 /* Initialize reg_hash hash table. */
252b5132
RH		 1036 reg_hash = hash_new ();
1037 {
29b0f896 1038 const reg_entry *regtab;
252b5132
RH		 1039
1040 for (regtab = i386_regtab;
1041 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
1042 regtab++)
1043 {
1044 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1045 if (hash_err)
3e73aa7c
JH		 1046 as_fatal (_("Internal Error: Can't hash %s: %s"),
1047 regtab->reg_name,
1048 hash_err);
252b5132
RH		 1049 }
1050 }
1051
47926f60 1052 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1053 {
29b0f896
AM		 1054 int c;
1055 char *p;
252b5132
RH		 1056
1057 for (c = 0; c < 256; c++)
1058 {
3882b010 1059 if (ISDIGIT (c))
252b5132
RH		 1060 {
1061 digit_chars[c] = c;
1062 mnemonic_chars[c] = c;
1063 register_chars[c] = c;
1064 operand_chars[c] = c;
1065 }
3882b010 1066 else if (ISLOWER (c))
252b5132
RH		 1067 {
1068 mnemonic_chars[c] = c;
1069 register_chars[c] = c;
1070 operand_chars[c] = c;
1071 }
3882b010 1072 else if (ISUPPER (c))
252b5132 1073 {
3882b010 1074 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1075 register_chars[c] = mnemonic_chars[c];
1076 operand_chars[c] = c;
1077 }
1078
3882b010 1079 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1080 identifier_chars[c] = c;
1081 else if (c >= 128)
1082 {
1083 identifier_chars[c] = c;
1084 operand_chars[c] = c;
1085 }
1086 }
1087
1088#ifdef LEX_AT
1089 identifier_chars['@'] = '@';
32137342
NC		 1090#endif
1091#ifdef LEX_QM
1092 identifier_chars['?'] = '?';
1093 operand_chars['?'] = '?';
252b5132 1094#endif
252b5132 1095 digit_chars['-'] = '-';
791fe849 1096 mnemonic_chars['-'] = '-';
252b5132
RH		 1097 identifier_chars['_'] = '_';
1098 identifier_chars['.'] = '.';
1099
1100 for (p = operand_special_chars; *p != '\0'; p++)
1101 operand_chars[(unsigned char) *p] = *p;
1102 }
1103
1104#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1105 if (IS_ELF)
252b5132
RH		 1106 {
1107 record_alignment (text_section, 2);
1108 record_alignment (data_section, 2);
1109 record_alignment (bss_section, 2);
1110 }
1111#endif
a4447b93
RH		 1112
1113 if (flag_code == CODE_64BIT)
1114 {
1115 x86_dwarf2_return_column = 16;
1116 x86_cie_data_alignment = -8;
1117 }
1118 else
1119 {
1120 x86_dwarf2_return_column = 8;
1121 x86_cie_data_alignment = -4;
1122 }
252b5132
RH		 1123}
1124
1125void
1126i386_print_statistics (file)
1127 FILE *file;
1128{
1129 hash_print_statistics (file, "i386 opcode", op_hash);
1130 hash_print_statistics (file, "i386 register", reg_hash);
1131}
1132\f
252b5132
RH		 1133#ifdef DEBUG386
1134
ce8a8b2f 1135/* Debugging routines for md_assemble. */
252b5132
RH		 1136static void pi PARAMS ((char *, i386_insn *));
1137static void pte PARAMS ((template *));
1138static void pt PARAMS ((unsigned int));
1139static void pe PARAMS ((expressionS *));
1140static void ps PARAMS ((symbolS *));
1141
1142static void
1143pi (line, x)
1144 char *line;
1145 i386_insn *x;
1146{
09f131f2 1147 unsigned int i;
252b5132
RH		 1148
1149 fprintf (stdout, "%s: template ", line);
1150 pte (&x->tm);
09f131f2
JH		 1151 fprintf (stdout, " address: base %s index %s scale %x\n",
1152 x->base_reg ? x->base_reg->reg_name : "none",
1153 x->index_reg ? x->index_reg->reg_name : "none",
1154 x->log2_scale_factor);
1155 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1156 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1157 fprintf (stdout, " sib: base %x index %x scale %x\n",
1158 x->sib.base, x->sib.index, x->sib.scale);
1159 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
29b0f896
AM		 1160 (x->rex & REX_MODE64) != 0,
1161 (x->rex & REX_EXTX) != 0,
1162 (x->rex & REX_EXTY) != 0,
1163 (x->rex & REX_EXTZ) != 0);
252b5132
RH		 1164 for (i = 0; i < x->operands; i++)
1165 {
1166 fprintf (stdout, " #%d: ", i + 1);
1167 pt (x->types[i]);
1168 fprintf (stdout, "\n");
1169 if (x->types[i]
3f4438ab 1170 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
520dc8e8 1171 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
252b5132 1172 if (x->types[i] & Imm)
520dc8e8 1173 pe (x->op[i].imms);
252b5132 1174 if (x->types[i] & Disp)
520dc8e8 1175 pe (x->op[i].disps);
252b5132
RH		 1176 }
1177}
1178
1179static void
1180pte (t)
1181 template *t;
1182{
09f131f2 1183 unsigned int i;
252b5132 1184 fprintf (stdout, " %d operands ", t->operands);
47926f60 1185 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1186 if (t->extension_opcode != None)
1187 fprintf (stdout, "ext %x ", t->extension_opcode);
1188 if (t->opcode_modifier & D)
1189 fprintf (stdout, "D");
1190 if (t->opcode_modifier & W)
1191 fprintf (stdout, "W");
1192 fprintf (stdout, "\n");
1193 for (i = 0; i < t->operands; i++)
1194 {
1195 fprintf (stdout, " #%d type ", i + 1);
1196 pt (t->operand_types[i]);
1197 fprintf (stdout, "\n");
1198 }
1199}
1200
1201static void
1202pe (e)
1203 expressionS *e;
1204{
24eab124 1205 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1206 fprintf (stdout, " add_number %ld (%lx)\n",
1207 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1208 if (e->X_add_symbol)
1209 {
1210 fprintf (stdout, " add_symbol ");
1211 ps (e->X_add_symbol);
1212 fprintf (stdout, "\n");
1213 }
1214 if (e->X_op_symbol)
1215 {
1216 fprintf (stdout, " op_symbol ");
1217 ps (e->X_op_symbol);
1218 fprintf (stdout, "\n");
1219 }
1220}
1221
1222static void
1223ps (s)
1224 symbolS *s;
1225{
1226 fprintf (stdout, "%s type %s%s",
1227 S_GET_NAME (s),
1228 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1229 segment_name (S_GET_SEGMENT (s)));
1230}
1231
7b81dfbb 1232static struct type_name
252b5132
RH		 1233 {
1234 unsigned int mask;
1235 char *tname;
1236 }
7b81dfbb 1237const type_names[] =
252b5132
RH		 1238{
1239 { Reg8, "r8" },
1240 { Reg16, "r16" },
1241 { Reg32, "r32" },
09f131f2 1242 { Reg64, "r64" },
252b5132
RH		 1243 { Imm8, "i8" },
1244 { Imm8S, "i8s" },
1245 { Imm16, "i16" },
1246 { Imm32, "i32" },
09f131f2
JH		 1247 { Imm32S, "i32s" },
1248 { Imm64, "i64" },
252b5132
RH		 1249 { Imm1, "i1" },
1250 { BaseIndex, "BaseIndex" },
1251 { Disp8, "d8" },
1252 { Disp16, "d16" },
1253 { Disp32, "d32" },
09f131f2
JH		 1254 { Disp32S, "d32s" },
1255 { Disp64, "d64" },
252b5132
RH		 1256 { InOutPortReg, "InOutPortReg" },
1257 { ShiftCount, "ShiftCount" },
1258 { Control, "control reg" },
1259 { Test, "test reg" },
1260 { Debug, "debug reg" },
1261 { FloatReg, "FReg" },
1262 { FloatAcc, "FAcc" },
1263 { SReg2, "SReg2" },
1264 { SReg3, "SReg3" },
1265 { Acc, "Acc" },
1266 { JumpAbsolute, "Jump Absolute" },
1267 { RegMMX, "rMMX" },
3f4438ab 1268 { RegXMM, "rXMM" },
252b5132
RH		 1269 { EsSeg, "es" },
1270 { 0, "" }
1271};
1272
1273static void
1274pt (t)
1275 unsigned int t;
1276{
29b0f896 1277 const struct type_name *ty;
252b5132 1278
09f131f2
JH		 1279 for (ty = type_names; ty->mask; ty++)
1280 if (t & ty->mask)
1281 fprintf (stdout, "%s, ", ty->tname);
252b5132
RH		 1282 fflush (stdout);
1283}
1284
1285#endif /* DEBUG386 */
1286\f
252b5132 1287static bfd_reloc_code_real_type
3956db08 1288reloc (unsigned int size,
64e74474
AM		 1289 int pcrel,
1290 int sign,
1291 bfd_reloc_code_real_type other)
252b5132 1292{
47926f60 1293 if (other != NO_RELOC)
3956db08
JB		 1294 {
1295 reloc_howto_type *reloc;
1296
1297 if (size == 8)
1298 switch (other)
1299 {
64e74474
AM		 1300 case BFD_RELOC_X86_64_GOT32:
1301 return BFD_RELOC_X86_64_GOT64;
1302 break;
1303 case BFD_RELOC_X86_64_PLTOFF64:
1304 return BFD_RELOC_X86_64_PLTOFF64;
1305 break;
1306 case BFD_RELOC_X86_64_GOTPC32:
1307 other = BFD_RELOC_X86_64_GOTPC64;
1308 break;
1309 case BFD_RELOC_X86_64_GOTPCREL:
1310 other = BFD_RELOC_X86_64_GOTPCREL64;
1311 break;
1312 case BFD_RELOC_X86_64_TPOFF32:
1313 other = BFD_RELOC_X86_64_TPOFF64;
1314 break;
1315 case BFD_RELOC_X86_64_DTPOFF32:
1316 other = BFD_RELOC_X86_64_DTPOFF64;
1317 break;
1318 default:
1319 break;
3956db08 1320 }
e05278af
JB		 1321
1322 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
1323 if (size == 4 && flag_code != CODE_64BIT)
1324 sign = -1;
1325
3956db08
JB		 1326 reloc = bfd_reloc_type_lookup (stdoutput, other);
1327 if (!reloc)
1328 as_bad (_("unknown relocation (%u)"), other);
1329 else if (size != bfd_get_reloc_size (reloc))
1330 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
1331 bfd_get_reloc_size (reloc),
1332 size);
1333 else if (pcrel && !reloc->pc_relative)
1334 as_bad (_("non-pc-relative relocation for pc-relative field"));
1335 else if ((reloc->complain_on_overflow == complain_overflow_signed
1336 && !sign)
1337 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 1338 && sign > 0))
3956db08
JB		 1339 as_bad (_("relocated field and relocation type differ in signedness"));
1340 else
1341 return other;
1342 return NO_RELOC;
1343 }
252b5132
RH		 1344
1345 if (pcrel)
1346 {
3e73aa7c 1347 if (!sign)
3956db08 1348 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 1349 switch (size)
1350 {
1351 case 1: return BFD_RELOC_8_PCREL;
1352 case 2: return BFD_RELOC_16_PCREL;
1353 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 1354 case 8: return BFD_RELOC_64_PCREL;
252b5132 1355 }
3956db08 1356 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 1357 }
1358 else
1359 {
3956db08 1360 if (sign > 0)
e5cb08ac 1361 switch (size)
3e73aa7c
JH		 1362 {
1363 case 4: return BFD_RELOC_X86_64_32S;
1364 }
1365 else
1366 switch (size)
1367 {
1368 case 1: return BFD_RELOC_8;
1369 case 2: return BFD_RELOC_16;
1370 case 4: return BFD_RELOC_32;
1371 case 8: return BFD_RELOC_64;
1372 }
3956db08
JB		 1373 as_bad (_("cannot do %s %u byte relocation"),
1374 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 1375 }
1376
bfb32b52 1377 abort ();
252b5132
RH		 1378 return BFD_RELOC_NONE;
1379}
1380
47926f60
KH		 1381/* Here we decide which fixups can be adjusted to make them relative to
1382 the beginning of the section instead of the symbol. Basically we need
1383 to make sure that the dynamic relocations are done correctly, so in
1384 some cases we force the original symbol to be used. */
1385
252b5132 1386int
c0c949c7 1387tc_i386_fix_adjustable (fixP)
31312f95 1388 fixS *fixP ATTRIBUTE_UNUSED;
252b5132 1389{
6d249963 1390#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1391 if (!IS_ELF)
31312f95
AM		 1392 return 1;
1393
a161fe53
AM		 1394 /* Don't adjust pc-relative references to merge sections in 64-bit
1395 mode. */
1396 if (use_rela_relocations
1397 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1398 && fixP->fx_pcrel)
252b5132 1399 return 0;
31312f95 1400
8d01d9a9
AJ		 1401 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1402 and changed later by validate_fix. */
1403 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1404 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1405 return 0;
1406
ce8a8b2f 1407 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1408 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1409 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1410 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 1411 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1412 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1413 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1414 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 1415 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1416 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 1417 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1418 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 1419 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
1420 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 1421 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1422 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 1423 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 1424 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1425 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1426 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 1427 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 1428 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1429 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 1430 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
1431 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 1432 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
1433 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 1434 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1435 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1436 return 0;
31312f95 1437#endif
252b5132
RH		 1438 return 1;
1439}
252b5132 1440
29b0f896 1441static int intel_float_operand PARAMS ((const char *mnemonic));
b4cac588
AM		 1442
1443static int
252b5132 1444intel_float_operand (mnemonic)
29b0f896 1445 const char *mnemonic;
252b5132 1446{
9306ca4a
JB		 1447 /* Note that the value returned is meaningful only for opcodes with (memory)
1448 operands, hence the code here is free to improperly handle opcodes that
1449 have no operands (for better performance and smaller code). */
1450
1451 if (mnemonic[0] != 'f')
1452 return 0; /* non-math */
1453
1454 switch (mnemonic[1])
1455 {
1456 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
1457 the fs segment override prefix not currently handled because no
1458 call path can make opcodes without operands get here */
1459 case 'i':
1460 return 2 /* integer op */;
1461 case 'l':
1462 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
1463 return 3; /* fldcw/fldenv */
1464 break;
1465 case 'n':
1466 if (mnemonic[2] != 'o' /* fnop */)
1467 return 3; /* non-waiting control op */
1468 break;
1469 case 'r':
1470 if (mnemonic[2] == 's')
1471 return 3; /* frstor/frstpm */
1472 break;
1473 case 's':
1474 if (mnemonic[2] == 'a')
1475 return 3; /* fsave */
1476 if (mnemonic[2] == 't')
1477 {
1478 switch (mnemonic[3])
1479 {
1480 case 'c': /* fstcw */
1481 case 'd': /* fstdw */
1482 case 'e': /* fstenv */
1483 case 's': /* fsts[gw] */
1484 return 3;
1485 }
1486 }
1487 break;
1488 case 'x':
1489 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
1490 return 0; /* fxsave/fxrstor are not really math ops */
1491 break;
1492 }
252b5132 1493
9306ca4a 1494 return 1;
252b5132
RH		 1495}
1496
1497/* This is the guts of the machine-dependent assembler. LINE points to a
1498 machine dependent instruction. This function is supposed to emit
1499 the frags/bytes it assembles to. */
1500
1501void
1502md_assemble (line)
1503 char *line;
1504{
252b5132 1505 int j;
252b5132
RH		 1506 char mnemonic[MAX_MNEM_SIZE];
1507
47926f60 1508 /* Initialize globals. */
252b5132
RH		 1509 memset (&i, '\0', sizeof (i));
1510 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 1511 i.reloc[j] = NO_RELOC;
252b5132
RH		 1512 memset (disp_expressions, '\0', sizeof (disp_expressions));
1513 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 1514 save_stack_p = save_stack;
252b5132
RH		 1515
1516 /* First parse an instruction mnemonic & call i386_operand for the operands.
1517 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 1518 start of a (possibly prefixed) mnemonic. */
252b5132 1519
29b0f896
AM		 1520 line = parse_insn (line, mnemonic);
1521 if (line == NULL)
1522 return;
252b5132 1523
29b0f896
AM		 1524 line = parse_operands (line, mnemonic);
1525 if (line == NULL)
1526 return;
252b5132 1527
29b0f896
AM		 1528 /* Now we've parsed the mnemonic into a set of templates, and have the
1529 operands at hand. */
1530
1531 /* All intel opcodes have reversed operands except for "bound" and
1532 "enter". We also don't reverse intersegment "jmp" and "call"
1533 instructions with 2 immediate operands so that the immediate segment
1534 precedes the offset, as it does when in AT&T mode. "enter" and the
1535 intersegment "jmp" and "call" instructions are the only ones that
1536 have two immediate operands. */
1537 if (intel_syntax && i.operands > 1
1538 && (strcmp (mnemonic, "bound") != 0)
30123838 1539 && (strcmp (mnemonic, "invlpga") != 0)
29b0f896
AM		 1540 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1541 swap_operands ();
1542
1543 if (i.imm_operands)
1544 optimize_imm ();
1545
b300c311
L		 1546 /* Don't optimize displacement for movabs since it only takes 64bit
1547 displacement. */
1548 if (i.disp_operands
1549 && (flag_code != CODE_64BIT
1550 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 1551 optimize_disp ();
1552
1553 /* Next, we find a template that matches the given insn,
1554 making sure the overlap of the given operands types is consistent
1555 with the template operand types. */
252b5132 1556
29b0f896
AM		 1557 if (!match_template ())
1558 return;
252b5132 1559
cd61ebfe
AM		 1560 if (intel_syntax)
1561 {
1562 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1563 if (SYSV386_COMPAT
1564 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1565 i.tm.base_opcode ^= FloatR;
1566
1567 /* Zap movzx and movsx suffix. The suffix may have been set from
1568 "word ptr" or "byte ptr" on the source operand, but we'll use
1569 the suffix later to choose the destination register. */
1570 if ((i.tm.base_opcode & ~9) == 0x0fb6)
9306ca4a
JB		 1571 {
1572 if (i.reg_operands < 2
1573 && !i.suffix
1574 && (~i.tm.opcode_modifier
1575 & (No_bSuf
1576 | No_wSuf
1577 | No_lSuf
1578 | No_sSuf
1579 | No_xSuf
1580 | No_qSuf)))
1581 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
1582
1583 i.suffix = 0;
1584 }
cd61ebfe 1585 }
24eab124 1586
29b0f896
AM		 1587 if (i.tm.opcode_modifier & FWait)
1588 if (!add_prefix (FWAIT_OPCODE))
1589 return;
252b5132 1590
29b0f896
AM		 1591 /* Check string instruction segment overrides. */
1592 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1593 {
1594 if (!check_string ())
5dd0794d 1595 return;
29b0f896 1596 }
5dd0794d 1597
29b0f896
AM		 1598 if (!process_suffix ())
1599 return;
e413e4e9 1600
29b0f896
AM		 1601 /* Make still unresolved immediate matches conform to size of immediate
1602 given in i.suffix. */
1603 if (!finalize_imm ())
1604 return;
252b5132 1605
29b0f896
AM		 1606 if (i.types[0] & Imm1)
1607 i.imm_operands = 0; /* kludge for shift insns. */
1608 if (i.types[0] & ImplicitRegister)
1609 i.reg_operands--;
1610 if (i.types[1] & ImplicitRegister)
1611 i.reg_operands--;
1612 if (i.types[2] & ImplicitRegister)
1613 i.reg_operands--;
252b5132 1614
29b0f896
AM		 1615 if (i.tm.opcode_modifier & ImmExt)
1616 {
02fc3089
L		 1617 expressionS *exp;
1618
ca164297
L		 1619 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1620 {
67c1ffbe 1621 /* These Intel Prescott New Instructions have the fixed
ca164297
L		 1622 operands with an opcode suffix which is coded in the same
1623 place as an 8-bit immediate field would be. Here we check
1624 those operands and remove them afterwards. */
1625 unsigned int x;
1626
a4622f40 1627 for (x = 0; x < i.operands; x++)
ca164297
L		 1628 if (i.op[x].regs->reg_num != x)
1629 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
64e74474 1630 i.op[x].regs->reg_name, x + 1, i.tm.name);
ca164297
L		 1631 i.operands = 0;
1632 }
1633
29b0f896
AM		 1634 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1635 opcode suffix which is coded in the same place as an 8-bit
1636 immediate field would be. Here we fake an 8-bit immediate
1637 operand from the opcode suffix stored in tm.extension_opcode. */
252b5132 1638
29b0f896 1639 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
252b5132 1640
29b0f896
AM		 1641 exp = &im_expressions[i.imm_operands++];
1642 i.op[i.operands].imms = exp;
1643 i.types[i.operands++] = Imm8;
1644 exp->X_op = O_constant;
1645 exp->X_add_number = i.tm.extension_opcode;
1646 i.tm.extension_opcode = None;
1647 }
252b5132 1648
29b0f896
AM		 1649 /* For insns with operands there are more diddles to do to the opcode. */
1650 if (i.operands)
1651 {
1652 if (!process_operands ())
1653 return;
1654 }
1655 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1656 {
1657 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1658 as_warn (_("translating to `%sp'"), i.tm.name);
1659 }
252b5132 1660
29b0f896
AM		 1661 /* Handle conversion of 'int $3' --> special int3 insn. */
1662 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1663 {
1664 i.tm.base_opcode = INT3_OPCODE;
1665 i.imm_operands = 0;
1666 }
252b5132 1667
29b0f896
AM		 1668 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1669 && i.op[0].disps->X_op == O_constant)
1670 {
1671 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1672 the absolute address given by the constant. Since ix86 jumps and
1673 calls are pc relative, we need to generate a reloc. */
1674 i.op[0].disps->X_add_symbol = &abs_symbol;
1675 i.op[0].disps->X_op = O_symbol;
1676 }
252b5132 1677
29b0f896
AM		 1678 if ((i.tm.opcode_modifier & Rex64) != 0)
1679 i.rex |= REX_MODE64;
252b5132 1680
29b0f896
AM		 1681 /* For 8 bit registers we need an empty rex prefix. Also if the
1682 instruction already has a prefix, we need to convert old
1683 registers to new ones. */
773f551c 1684
29b0f896
AM		 1685 if (((i.types[0] & Reg8) != 0
1686 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1687 || ((i.types[1] & Reg8) != 0
1688 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1689 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1690 && i.rex != 0))
1691 {
1692 int x;
726c5dcd 1693
29b0f896
AM		 1694 i.rex |= REX_OPCODE;
1695 for (x = 0; x < 2; x++)
1696 {
1697 /* Look for 8 bit operand that uses old registers. */
1698 if ((i.types[x] & Reg8) != 0
1699 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 1700 {
29b0f896
AM		 1701 /* In case it is "hi" register, give up. */
1702 if (i.op[x].regs->reg_num > 3)
0477af35 1703 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix."),
29b0f896 1704 i.op[x].regs->reg_name);
773f551c 1705
29b0f896
AM		 1706 /* Otherwise it is equivalent to the extended register.
1707 Since the encoding doesn't change this is merely
1708 cosmetic cleanup for debug output. */
1709
1710 i.op[x].regs = i.op[x].regs + 8;
773f551c 1711 }
29b0f896
AM		 1712 }
1713 }
773f551c 1714
29b0f896
AM		 1715 if (i.rex != 0)
1716 add_prefix (REX_OPCODE | i.rex);
1717
9103f4f4
L		 1718 /* Record what ISA we have generated so far. */
1719 cpu_arch_isa_flags |= i.tm.cpu_flags;
1720
29b0f896
AM		 1721 /* We are ready to output the insn. */
1722 output_insn ();
1723}
1724
1725static char *
1726parse_insn (line, mnemonic)
1727 char *line;
1728 char *mnemonic;
1729{
1730 char *l = line;
1731 char *token_start = l;
1732 char *mnem_p;
5c6af06e
JB		 1733 int supported;
1734 const template *t;
29b0f896
AM		 1735
1736 /* Non-zero if we found a prefix only acceptable with string insns. */
1737 const char *expecting_string_instruction = NULL;
45288df1 1738
29b0f896
AM		 1739 while (1)
1740 {
1741 mnem_p = mnemonic;
1742 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1743 {
1744 mnem_p++;
1745 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 1746 {
29b0f896
AM		 1747 as_bad (_("no such instruction: `%s'"), token_start);
1748 return NULL;
1749 }
1750 l++;
1751 }
1752 if (!is_space_char (*l)
1753 && *l != END_OF_INSN
e44823cf
JB		 1754 && (intel_syntax
1755 || (*l != PREFIX_SEPARATOR
1756 && *l != ',')))
29b0f896
AM		 1757 {
1758 as_bad (_("invalid character %s in mnemonic"),
1759 output_invalid (*l));
1760 return NULL;
1761 }
1762 if (token_start == l)
1763 {
e44823cf 1764 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 1765 as_bad (_("expecting prefix; got nothing"));
1766 else
1767 as_bad (_("expecting mnemonic; got nothing"));
1768 return NULL;
1769 }
45288df1 1770
29b0f896
AM		 1771 /* Look up instruction (or prefix) via hash table. */
1772 current_templates = hash_find (op_hash, mnemonic);
47926f60 1773
29b0f896
AM		 1774 if (*l != END_OF_INSN
1775 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1776 && current_templates
1777 && (current_templates->start->opcode_modifier & IsPrefix))
1778 {
2dd88dca
JB		 1779 if (current_templates->start->cpu_flags
1780 & (flag_code != CODE_64BIT ? Cpu64 : CpuNo64))
1781 {
1782 as_bad ((flag_code != CODE_64BIT
1783 ? _("`%s' is only supported in 64-bit mode")
1784 : _("`%s' is not supported in 64-bit mode")),
1785 current_templates->start->name);
1786 return NULL;
1787 }
29b0f896
AM		 1788 /* If we are in 16-bit mode, do not allow addr16 or data16.
1789 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1790 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1791 && flag_code != CODE_64BIT
1792 && (((current_templates->start->opcode_modifier & Size32) != 0)
1793 ^ (flag_code == CODE_16BIT)))
1794 {
1795 as_bad (_("redundant %s prefix"),
1796 current_templates->start->name);
1797 return NULL;
45288df1 1798 }
29b0f896
AM		 1799 /* Add prefix, checking for repeated prefixes. */
1800 switch (add_prefix (current_templates->start->base_opcode))
1801 {
1802 case 0:
1803 return NULL;
1804 case 2:
1805 expecting_string_instruction = current_templates->start->name;
1806 break;
1807 }
1808 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1809 token_start = ++l;
1810 }
1811 else
1812 break;
1813 }
45288df1 1814
29b0f896
AM		 1815 if (!current_templates)
1816 {
1817 /* See if we can get a match by trimming off a suffix. */
1818 switch (mnem_p[-1])
1819 {
1820 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 1821 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
1822 i.suffix = SHORT_MNEM_SUFFIX;
1823 else
29b0f896
AM		 1824 case BYTE_MNEM_SUFFIX:
1825 case QWORD_MNEM_SUFFIX:
1826 i.suffix = mnem_p[-1];
1827 mnem_p[-1] = '\0';
1828 current_templates = hash_find (op_hash, mnemonic);
1829 break;
1830 case SHORT_MNEM_SUFFIX:
1831 case LONG_MNEM_SUFFIX:
1832 if (!intel_syntax)
1833 {
1834 i.suffix = mnem_p[-1];
1835 mnem_p[-1] = '\0';
1836 current_templates = hash_find (op_hash, mnemonic);
1837 }
1838 break;
252b5132 1839
29b0f896
AM		 1840 /* Intel Syntax. */
1841 case 'd':
1842 if (intel_syntax)
1843 {
9306ca4a 1844 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 1845 i.suffix = SHORT_MNEM_SUFFIX;
1846 else
1847 i.suffix = LONG_MNEM_SUFFIX;
1848 mnem_p[-1] = '\0';
1849 current_templates = hash_find (op_hash, mnemonic);
1850 }
1851 break;
1852 }
1853 if (!current_templates)
1854 {
1855 as_bad (_("no such instruction: `%s'"), token_start);
1856 return NULL;
1857 }
1858 }
252b5132 1859
29b0f896
AM		 1860 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1861 {
1862 /* Check for a branch hint. We allow ",pt" and ",pn" for
1863 predict taken and predict not taken respectively.
1864 I'm not sure that branch hints actually do anything on loop
1865 and jcxz insns (JumpByte) for current Pentium4 chips. They
1866 may work in the future and it doesn't hurt to accept them
1867 now. */
1868 if (l[0] == ',' && l[1] == 'p')
1869 {
1870 if (l[2] == 't')
1871 {
1872 if (!add_prefix (DS_PREFIX_OPCODE))
1873 return NULL;
1874 l += 3;
1875 }
1876 else if (l[2] == 'n')
1877 {
1878 if (!add_prefix (CS_PREFIX_OPCODE))
1879 return NULL;
1880 l += 3;
1881 }
1882 }
1883 }
1884 /* Any other comma loses. */
1885 if (*l == ',')
1886 {
1887 as_bad (_("invalid character %s in mnemonic"),
1888 output_invalid (*l));
1889 return NULL;
1890 }
252b5132 1891
29b0f896 1892 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 1893 supported = 0;
1894 for (t = current_templates->start; t < current_templates->end; ++t)
1895 {
1896 if (!((t->cpu_flags & ~(Cpu64 | CpuNo64))
1897 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))))
64e74474 1898 supported |= 1;
5c6af06e 1899 if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo64 : Cpu64)))
64e74474 1900 supported |= 2;
5c6af06e
JB		 1901 }
1902 if (!(supported & 2))
1903 {
1904 as_bad (flag_code == CODE_64BIT
1905 ? _("`%s' is not supported in 64-bit mode")
1906 : _("`%s' is only supported in 64-bit mode"),
1907 current_templates->start->name);
1908 return NULL;
1909 }
1910 if (!(supported & 1))
29b0f896 1911 {
5c6af06e
JB		 1912 as_warn (_("`%s' is not supported on `%s%s'"),
1913 current_templates->start->name,
1914 cpu_arch_name,
1915 cpu_sub_arch_name ? cpu_sub_arch_name : "");
29b0f896
AM		 1916 }
1917 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1918 {
1919 as_warn (_("use .code16 to ensure correct addressing mode"));
1920 }
252b5132 1921
29b0f896 1922 /* Check for rep/repne without a string instruction. */
f41bbced 1923 if (expecting_string_instruction)
29b0f896 1924 {
f41bbced
JB		 1925 static templates override;
1926
1927 for (t = current_templates->start; t < current_templates->end; ++t)
1928 if (t->opcode_modifier & IsString)
1929 break;
1930 if (t >= current_templates->end)
1931 {
1932 as_bad (_("expecting string instruction after `%s'"),
64e74474 1933 expecting_string_instruction);
f41bbced
JB		 1934 return NULL;
1935 }
1936 for (override.start = t; t < current_templates->end; ++t)
1937 if (!(t->opcode_modifier & IsString))
1938 break;
1939 override.end = t;
1940 current_templates = &override;
29b0f896 1941 }
252b5132 1942
29b0f896
AM		 1943 return l;
1944}
252b5132 1945
29b0f896
AM		 1946static char *
1947parse_operands (l, mnemonic)
1948 char *l;
1949 const char *mnemonic;
1950{
1951 char *token_start;
3138f287 1952
29b0f896
AM		 1953 /* 1 if operand is pending after ','. */
1954 unsigned int expecting_operand = 0;
252b5132 1955
29b0f896
AM		 1956 /* Non-zero if operand parens not balanced. */
1957 unsigned int paren_not_balanced;
1958
1959 while (*l != END_OF_INSN)
1960 {
1961 /* Skip optional white space before operand. */
1962 if (is_space_char (*l))
1963 ++l;
1964 if (!is_operand_char (*l) && *l != END_OF_INSN)
1965 {
1966 as_bad (_("invalid character %s before operand %d"),
1967 output_invalid (*l),
1968 i.operands + 1);
1969 return NULL;
1970 }
1971 token_start = l; /* after white space */
1972 paren_not_balanced = 0;
1973 while (paren_not_balanced || *l != ',')
1974 {
1975 if (*l == END_OF_INSN)
1976 {
1977 if (paren_not_balanced)
1978 {
1979 if (!intel_syntax)
1980 as_bad (_("unbalanced parenthesis in operand %d."),
1981 i.operands + 1);
1982 else
1983 as_bad (_("unbalanced brackets in operand %d."),
1984 i.operands + 1);
1985 return NULL;
1986 }
1987 else
1988 break; /* we are done */
1989 }
1990 else if (!is_operand_char (*l) && !is_space_char (*l))
1991 {
1992 as_bad (_("invalid character %s in operand %d"),
1993 output_invalid (*l),
1994 i.operands + 1);
1995 return NULL;
1996 }
1997 if (!intel_syntax)
1998 {
1999 if (*l == '(')
2000 ++paren_not_balanced;
2001 if (*l == ')')
2002 --paren_not_balanced;
2003 }
2004 else
2005 {
2006 if (*l == '[')
2007 ++paren_not_balanced;
2008 if (*l == ']')
2009 --paren_not_balanced;
2010 }
2011 l++;
2012 }
2013 if (l != token_start)
2014 { /* Yes, we've read in another operand. */
2015 unsigned int operand_ok;
2016 this_operand = i.operands++;
2017 if (i.operands > MAX_OPERANDS)
2018 {
2019 as_bad (_("spurious operands; (%d operands/instruction max)"),
2020 MAX_OPERANDS);
2021 return NULL;
2022 }
2023 /* Now parse operand adding info to 'i' as we go along. */
2024 END_STRING_AND_SAVE (l);
2025
2026 if (intel_syntax)
2027 operand_ok =
2028 i386_intel_operand (token_start,
2029 intel_float_operand (mnemonic));
2030 else
2031 operand_ok = i386_operand (token_start);
2032
2033 RESTORE_END_STRING (l);
2034 if (!operand_ok)
2035 return NULL;
2036 }
2037 else
2038 {
2039 if (expecting_operand)
2040 {
2041 expecting_operand_after_comma:
2042 as_bad (_("expecting operand after ','; got nothing"));
2043 return NULL;
2044 }
2045 if (*l == ',')
2046 {
2047 as_bad (_("expecting operand before ','; got nothing"));
2048 return NULL;
2049 }
2050 }
7f3f1ea2 2051
29b0f896
AM		 2052 /* Now *l must be either ',' or END_OF_INSN. */
2053 if (*l == ',')
2054 {
2055 if (*++l == END_OF_INSN)
2056 {
2057 /* Just skip it, if it's \n complain. */
2058 goto expecting_operand_after_comma;
2059 }
2060 expecting_operand = 1;
2061 }
2062 }
2063 return l;
2064}
7f3f1ea2 2065
29b0f896
AM		 2066static void
2067swap_operands ()
2068{
2069 union i386_op temp_op;
2070 unsigned int temp_type;
f86103b7 2071 enum bfd_reloc_code_real temp_reloc;
29b0f896
AM		 2072 int xchg1 = 0;
2073 int xchg2 = 0;
252b5132 2074
29b0f896
AM		 2075 if (i.operands == 2)
2076 {
2077 xchg1 = 0;
2078 xchg2 = 1;
2079 }
2080 else if (i.operands == 3)
2081 {
2082 xchg1 = 0;
2083 xchg2 = 2;
2084 }
2085 temp_type = i.types[xchg2];
2086 i.types[xchg2] = i.types[xchg1];
2087 i.types[xchg1] = temp_type;
2088 temp_op = i.op[xchg2];
2089 i.op[xchg2] = i.op[xchg1];
2090 i.op[xchg1] = temp_op;
2091 temp_reloc = i.reloc[xchg2];
2092 i.reloc[xchg2] = i.reloc[xchg1];
2093 i.reloc[xchg1] = temp_reloc;
2094
2095 if (i.mem_operands == 2)
2096 {
2097 const seg_entry *temp_seg;
2098 temp_seg = i.seg[0];
2099 i.seg[0] = i.seg[1];
2100 i.seg[1] = temp_seg;
2101 }
2102}
252b5132 2103
29b0f896
AM		 2104/* Try to ensure constant immediates are represented in the smallest
2105 opcode possible. */
2106static void
2107optimize_imm ()
2108{
2109 char guess_suffix = 0;
2110 int op;
252b5132 2111
29b0f896
AM		 2112 if (i.suffix)
2113 guess_suffix = i.suffix;
2114 else if (i.reg_operands)
2115 {
2116 /* Figure out a suffix from the last register operand specified.
2117 We can't do this properly yet, ie. excluding InOutPortReg,
2118 but the following works for instructions with immediates.
2119 In any case, we can't set i.suffix yet. */
2120 for (op = i.operands; --op >= 0;)
2121 if (i.types[op] & Reg)
252b5132 2122 {
29b0f896
AM		 2123 if (i.types[op] & Reg8)
2124 guess_suffix = BYTE_MNEM_SUFFIX;
2125 else if (i.types[op] & Reg16)
2126 guess_suffix = WORD_MNEM_SUFFIX;
2127 else if (i.types[op] & Reg32)
2128 guess_suffix = LONG_MNEM_SUFFIX;
2129 else if (i.types[op] & Reg64)
2130 guess_suffix = QWORD_MNEM_SUFFIX;
2131 break;
252b5132 2132 }
29b0f896
AM		 2133 }
2134 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2135 guess_suffix = WORD_MNEM_SUFFIX;
2136
2137 for (op = i.operands; --op >= 0;)
2138 if (i.types[op] & Imm)
2139 {
2140 switch (i.op[op].imms->X_op)
252b5132 2141 {
29b0f896
AM		 2142 case O_constant:
2143 /* If a suffix is given, this operand may be shortened. */
2144 switch (guess_suffix)
252b5132 2145 {
29b0f896
AM		 2146 case LONG_MNEM_SUFFIX:
2147 i.types[op] |= Imm32 | Imm64;
2148 break;
2149 case WORD_MNEM_SUFFIX:
2150 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
2151 break;
2152 case BYTE_MNEM_SUFFIX:
2153 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
2154 break;
252b5132 2155 }
252b5132 2156
29b0f896
AM		 2157 /* If this operand is at most 16 bits, convert it
2158 to a signed 16 bit number before trying to see
2159 whether it will fit in an even smaller size.
2160 This allows a 16-bit operand such as $0xffe0 to
2161 be recognised as within Imm8S range. */
2162 if ((i.types[op] & Imm16)
2163 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2164 {
29b0f896
AM		 2165 i.op[op].imms->X_add_number =
2166 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2167 }
2168 if ((i.types[op] & Imm32)
2169 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2170 == 0))
2171 {
2172 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2173 ^ ((offsetT) 1 << 31))
2174 - ((offsetT) 1 << 31));
2175 }
2176 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
252b5132 2177
29b0f896
AM		 2178 /* We must avoid matching of Imm32 templates when 64bit
2179 only immediate is available. */
2180 if (guess_suffix == QWORD_MNEM_SUFFIX)
2181 i.types[op] &= ~Imm32;
2182 break;
252b5132 2183
29b0f896
AM		 2184 case O_absent:
2185 case O_register:
2186 abort ();
2187
2188 /* Symbols and expressions. */
2189 default:
9cd96992
JB		 2190 /* Convert symbolic operand to proper sizes for matching, but don't
2191 prevent matching a set of insns that only supports sizes other
2192 than those matching the insn suffix. */
2193 {
2194 unsigned int mask, allowed = 0;
2195 const template *t;
2196
2197 for (t = current_templates->start; t < current_templates->end; ++t)
2198 allowed |= t->operand_types[op];
2199 switch (guess_suffix)
2200 {
2201 case QWORD_MNEM_SUFFIX:
2202 mask = Imm64 | Imm32S;
2203 break;
2204 case LONG_MNEM_SUFFIX:
2205 mask = Imm32;
2206 break;
2207 case WORD_MNEM_SUFFIX:
2208 mask = Imm16;
2209 break;
2210 case BYTE_MNEM_SUFFIX:
2211 mask = Imm8;
2212 break;
2213 default:
2214 mask = 0;
2215 break;
2216 }
64e74474
AM		 2217 if (mask & allowed)
2218 i.types[op] &= mask;
9cd96992 2219 }
29b0f896 2220 break;
252b5132 2221 }
29b0f896
AM		 2222 }
2223}
47926f60 2224
29b0f896
AM		 2225/* Try to use the smallest displacement type too. */
2226static void
2227optimize_disp ()
2228{
2229 int op;
3e73aa7c 2230
29b0f896 2231 for (op = i.operands; --op >= 0;)
b300c311 2232 if (i.types[op] & Disp)
252b5132 2233 {
b300c311 2234 if (i.op[op].disps->X_op == O_constant)
252b5132 2235 {
b300c311 2236 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2237
b300c311
L		 2238 if ((i.types[op] & Disp16)
2239 && (disp & ~(offsetT) 0xffff) == 0)
2240 {
2241 /* If this operand is at most 16 bits, convert
2242 to a signed 16 bit number and don't use 64bit
2243 displacement. */
2244 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
2245 i.types[op] &= ~Disp64;
2246 }
2247 if ((i.types[op] & Disp32)
2248 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
2249 {
2250 /* If this operand is at most 32 bits, convert
2251 to a signed 32 bit number and don't use 64bit
2252 displacement. */
2253 disp &= (((offsetT) 2 << 31) - 1);
2254 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
2255 i.types[op] &= ~Disp64;
2256 }
2257 if (!disp && (i.types[op] & BaseIndex))
2258 {
2259 i.types[op] &= ~Disp;
2260 i.op[op].disps = 0;
2261 i.disp_operands--;
2262 }
2263 else if (flag_code == CODE_64BIT)
2264 {
2265 if (fits_in_signed_long (disp))
28a9d8f5
L		 2266 {
2267 i.types[op] &= ~Disp64;
2268 i.types[op] |= Disp32S;
2269 }
b300c311
L		 2270 if (fits_in_unsigned_long (disp))
2271 i.types[op] |= Disp32;
2272 }
2273 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
2274 && fits_in_signed_byte (disp))
2275 i.types[op] |= Disp8;
252b5132 2276 }
67a4f2b7
AO		 2277 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
2278 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
2279 {
2280 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
2281 i.op[op].disps, 0, i.reloc[op]);
2282 i.types[op] &= ~Disp;
2283 }
2284 else
b300c311
L		 2285 /* We only support 64bit displacement on constants. */
2286 i.types[op] &= ~Disp64;
252b5132 2287 }
29b0f896
AM		 2288}
2289
2290static int
2291match_template ()
2292{
2293 /* Points to template once we've found it. */
2294 const template *t;
2295 unsigned int overlap0, overlap1, overlap2;
2296 unsigned int found_reverse_match;
2297 int suffix_check;
2298
2299#define MATCH(overlap, given, template) \
2300 ((overlap & ~JumpAbsolute) \
2301 && (((given) & (BaseIndex | JumpAbsolute)) \
2302 == ((overlap) & (BaseIndex | JumpAbsolute))))
2303
2304 /* If given types r0 and r1 are registers they must be of the same type
2305 unless the expected operand type register overlap is null.
2306 Note that Acc in a template matches every size of reg. */
2307#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
2308 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
2309 || ((g0) & Reg) == ((g1) & Reg) \
2310 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
2311
2312 overlap0 = 0;
2313 overlap1 = 0;
2314 overlap2 = 0;
2315 found_reverse_match = 0;
2316 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
2317 ? No_bSuf
2318 : (i.suffix == WORD_MNEM_SUFFIX
2319 ? No_wSuf
2320 : (i.suffix == SHORT_MNEM_SUFFIX
2321 ? No_sSuf
2322 : (i.suffix == LONG_MNEM_SUFFIX
2323 ? No_lSuf
2324 : (i.suffix == QWORD_MNEM_SUFFIX
2325 ? No_qSuf
2326 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2327 ? No_xSuf : 0))))));
2328
45aa61fe 2329 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896
AM		 2330 {
2331 /* Must have right number of operands. */
2332 if (i.operands != t->operands)
2333 continue;
2334
2335 /* Check the suffix, except for some instructions in intel mode. */
2336 if ((t->opcode_modifier & suffix_check)
2337 && !(intel_syntax
9306ca4a 2338 && (t->opcode_modifier & IgnoreSize)))
29b0f896
AM		 2339 continue;
2340
45aa61fe
AM		 2341 /* In general, don't allow 64-bit operands in 32-bit mode. */
2342 if (i.suffix == QWORD_MNEM_SUFFIX
2343 && flag_code != CODE_64BIT
2344 && (intel_syntax
2345 ? (!(t->opcode_modifier & IgnoreSize)
2346 && !intel_float_operand (t->name))
2347 : intel_float_operand (t->name) != 2)
2348 && (!(t->operand_types[0] & (RegMMX | RegXMM))
2349 || !(t->operand_types[t->operands > 1] & (RegMMX | RegXMM)))
2350 && (t->base_opcode != 0x0fc7
2351 || t->extension_opcode != 1 /* cmpxchg8b */))
2352 continue;
2353
29b0f896
AM		 2354 /* Do not verify operands when there are none. */
2355 else if (!t->operands)
2356 {
2357 if (t->cpu_flags & ~cpu_arch_flags)
2358 continue;
2359 /* We've found a match; break out of loop. */
2360 break;
2361 }
252b5132 2362
29b0f896
AM		 2363 overlap0 = i.types[0] & t->operand_types[0];
2364 switch (t->operands)
2365 {
2366 case 1:
2367 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2368 continue;
2369 break;
2370 case 2:
2371 case 3:
2372 overlap1 = i.types[1] & t->operand_types[1];
2373 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2374 || !MATCH (overlap1, i.types[1], t->operand_types[1])
cb712a9e 2375 /* monitor in SSE3 is a very special case. The first
708587a4 2376 register and the second register may have different
cb712a9e
L		 2377 sizes. */
2378 || !((t->base_opcode == 0x0f01
2379 && t->extension_opcode == 0xc8)
2380 || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2381 t->operand_types[0],
2382 overlap1, i.types[1],
2383 t->operand_types[1])))
29b0f896
AM		 2384 {
2385 /* Check if other direction is valid ... */
2386 if ((t->opcode_modifier & (D | FloatD)) == 0)
2387 continue;
2388
2389 /* Try reversing direction of operands. */
2390 overlap0 = i.types[0] & t->operand_types[1];
2391 overlap1 = i.types[1] & t->operand_types[0];
2392 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2393 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2394 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2395 t->operand_types[1],
2396 overlap1, i.types[1],
2397 t->operand_types[0]))
2398 {
2399 /* Does not match either direction. */
2400 continue;
2401 }
2402 /* found_reverse_match holds which of D or FloatDR
2403 we've found. */
2404 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2405 }
2406 /* Found a forward 2 operand match here. */
2407 else if (t->operands == 3)
2408 {
2409 /* Here we make use of the fact that there are no
2410 reverse match 3 operand instructions, and all 3
2411 operand instructions only need to be checked for
2412 register consistency between operands 2 and 3. */
2413 overlap2 = i.types[2] & t->operand_types[2];
2414 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2415 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2416 t->operand_types[1],
2417 overlap2, i.types[2],
2418 t->operand_types[2]))
2419
2420 continue;
2421 }
2422 /* Found either forward/reverse 2 or 3 operand match here:
2423 slip through to break. */
2424 }
2425 if (t->cpu_flags & ~cpu_arch_flags)
2426 {
2427 found_reverse_match = 0;
2428 continue;
2429 }
2430 /* We've found a match; break out of loop. */
2431 break;
2432 }
2433
2434 if (t == current_templates->end)
2435 {
2436 /* We found no match. */
2437 as_bad (_("suffix or operands invalid for `%s'"),
2438 current_templates->start->name);
2439 return 0;
2440 }
252b5132 2441
29b0f896
AM		 2442 if (!quiet_warnings)
2443 {
2444 if (!intel_syntax
2445 && ((i.types[0] & JumpAbsolute)
2446 != (t->operand_types[0] & JumpAbsolute)))
2447 {
2448 as_warn (_("indirect %s without `*'"), t->name);
2449 }
2450
2451 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2452 == (IsPrefix | IgnoreSize))
2453 {
2454 /* Warn them that a data or address size prefix doesn't
2455 affect assembly of the next line of code. */
2456 as_warn (_("stand-alone `%s' prefix"), t->name);
2457 }
2458 }
2459
2460 /* Copy the template we found. */
2461 i.tm = *t;
2462 if (found_reverse_match)
2463 {
2464 /* If we found a reverse match we must alter the opcode
2465 direction bit. found_reverse_match holds bits to change
2466 (different for int & float insns). */
2467
2468 i.tm.base_opcode ^= found_reverse_match;
2469
2470 i.tm.operand_types[0] = t->operand_types[1];
2471 i.tm.operand_types[1] = t->operand_types[0];
2472 }
2473
2474 return 1;
2475}
2476
2477static int
2478check_string ()
2479{
2480 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2481 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2482 {
2483 if (i.seg[0] != NULL && i.seg[0] != &es)
2484 {
2485 as_bad (_("`%s' operand %d must use `%%es' segment"),
2486 i.tm.name,
2487 mem_op + 1);
2488 return 0;
2489 }
2490 /* There's only ever one segment override allowed per instruction.
2491 This instruction possibly has a legal segment override on the
2492 second operand, so copy the segment to where non-string
2493 instructions store it, allowing common code. */
2494 i.seg[0] = i.seg[1];
2495 }
2496 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2497 {
2498 if (i.seg[1] != NULL && i.seg[1] != &es)
2499 {
2500 as_bad (_("`%s' operand %d must use `%%es' segment"),
2501 i.tm.name,
2502 mem_op + 2);
2503 return 0;
2504 }
2505 }
2506 return 1;
2507}
2508
2509static int
543613e9 2510process_suffix (void)
29b0f896
AM		 2511{
2512 /* If matched instruction specifies an explicit instruction mnemonic
2513 suffix, use it. */
2514 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2515 {
2516 if (i.tm.opcode_modifier & Size16)
2517 i.suffix = WORD_MNEM_SUFFIX;
2518 else if (i.tm.opcode_modifier & Size64)
2519 i.suffix = QWORD_MNEM_SUFFIX;
2520 else
2521 i.suffix = LONG_MNEM_SUFFIX;
2522 }
2523 else if (i.reg_operands)
2524 {
2525 /* If there's no instruction mnemonic suffix we try to invent one
2526 based on register operands. */
2527 if (!i.suffix)
2528 {
2529 /* We take i.suffix from the last register operand specified,
2530 Destination register type is more significant than source
2531 register type. */
2532 int op;
543613e9 2533
29b0f896
AM		 2534 for (op = i.operands; --op >= 0;)
2535 if ((i.types[op] & Reg)
2536 && !(i.tm.operand_types[op] & InOutPortReg))
2537 {
2538 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2539 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2540 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2541 LONG_MNEM_SUFFIX);
2542 break;
2543 }
2544 }
2545 else if (i.suffix == BYTE_MNEM_SUFFIX)
2546 {
2547 if (!check_byte_reg ())
2548 return 0;
2549 }
2550 else if (i.suffix == LONG_MNEM_SUFFIX)
2551 {
2552 if (!check_long_reg ())
2553 return 0;
2554 }
2555 else if (i.suffix == QWORD_MNEM_SUFFIX)
2556 {
2557 if (!check_qword_reg ())
2558 return 0;
2559 }
2560 else if (i.suffix == WORD_MNEM_SUFFIX)
2561 {
2562 if (!check_word_reg ())
2563 return 0;
2564 }
2565 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2566 /* Do nothing if the instruction is going to ignore the prefix. */
2567 ;
2568 else
2569 abort ();
2570 }
9306ca4a
JB		 2571 else if ((i.tm.opcode_modifier & DefaultSize)
2572 && !i.suffix
2573 /* exclude fldenv/frstor/fsave/fstenv */
2574 && (i.tm.opcode_modifier & No_sSuf))
29b0f896
AM		 2575 {
2576 i.suffix = stackop_size;
2577 }
9306ca4a
JB		 2578 else if (intel_syntax
2579 && !i.suffix
2580 && ((i.tm.operand_types[0] & JumpAbsolute)
64e74474
AM		 2581 || (i.tm.opcode_modifier & (JumpByte|JumpInterSegment))
2582 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
2583 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 2584 {
2585 switch (flag_code)
2586 {
2587 case CODE_64BIT:
2588 if (!(i.tm.opcode_modifier & No_qSuf))
2589 {
2590 i.suffix = QWORD_MNEM_SUFFIX;
2591 break;
2592 }
2593 case CODE_32BIT:
2594 if (!(i.tm.opcode_modifier & No_lSuf))
2595 i.suffix = LONG_MNEM_SUFFIX;
2596 break;
2597 case CODE_16BIT:
2598 if (!(i.tm.opcode_modifier & No_wSuf))
2599 i.suffix = WORD_MNEM_SUFFIX;
2600 break;
2601 }
2602 }
252b5132 2603
9306ca4a 2604 if (!i.suffix)
29b0f896 2605 {
9306ca4a
JB		 2606 if (!intel_syntax)
2607 {
2608 if (i.tm.opcode_modifier & W)
2609 {
2610 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2611 return 0;
2612 }
2613 }
2614 else
2615 {
64e74474
AM		 2616 unsigned int suffixes = (~i.tm.opcode_modifier
2617 & (No_bSuf
2618 | No_wSuf
2619 | No_lSuf
2620 | No_sSuf
2621 | No_xSuf
2622 | No_qSuf));
9306ca4a
JB		 2623
2624 if ((i.tm.opcode_modifier & W)
2625 || ((suffixes & (suffixes - 1))
2626 && !(i.tm.opcode_modifier & (DefaultSize | IgnoreSize))))
2627 {
2628 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2629 return 0;
2630 }
2631 }
29b0f896 2632 }
252b5132 2633
9306ca4a
JB		 2634 /* Change the opcode based on the operand size given by i.suffix;
2635 We don't need to change things for byte insns. */
2636
29b0f896
AM		 2637 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2638 {
2639 /* It's not a byte, select word/dword operation. */
2640 if (i.tm.opcode_modifier & W)
2641 {
2642 if (i.tm.opcode_modifier & ShortForm)
2643 i.tm.base_opcode |= 8;
2644 else
2645 i.tm.base_opcode |= 1;
2646 }
0f3f3d8b 2647
29b0f896
AM		 2648 /* Now select between word & dword operations via the operand
2649 size prefix, except for instructions that will ignore this
2650 prefix anyway. */
cb712a9e
L		 2651 if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8)
2652 {
2653 /* monitor in SSE3 is a very special case. The default size
2654 of AX is the size of mode. The address size override
2655 prefix will change the size of AX. */
2656 if (i.op->regs[0].reg_type &
2657 (flag_code == CODE_32BIT ? Reg16 : Reg32))
2658 if (!add_prefix (ADDR_PREFIX_OPCODE))
2659 return 0;
2660 }
2661 else if (i.suffix != QWORD_MNEM_SUFFIX
2662 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
2663 && !(i.tm.opcode_modifier & (IgnoreSize | FloatMF))
2664 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2665 || (flag_code == CODE_64BIT
2666 && (i.tm.opcode_modifier & JumpByte))))
24eab124
AM		 2667 {
2668 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 2669
29b0f896
AM		 2670 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2671 prefix = ADDR_PREFIX_OPCODE;
252b5132 2672
29b0f896
AM		 2673 if (!add_prefix (prefix))
2674 return 0;
24eab124 2675 }
252b5132 2676
29b0f896
AM		 2677 /* Set mode64 for an operand. */
2678 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 2679 && flag_code == CODE_64BIT
29b0f896 2680 && (i.tm.opcode_modifier & NoRex64) == 0)
46e883c5
L		 2681 {
2682 /* Special case for xchg %rax,%rax. It is NOP and doesn't
2683 need rex64. */
2684 if (i.operands != 2
2685 || i.types [0] != (Acc | Reg64)
2686 || i.types [1] != (Acc | Reg64)
2687 || strcmp (i.tm.name, "xchg") != 0)
2688 i.rex |= REX_MODE64;
2689 }
3e73aa7c 2690
29b0f896
AM		 2691 /* Size floating point instruction. */
2692 if (i.suffix == LONG_MNEM_SUFFIX)
543613e9
NC		 2693 if (i.tm.opcode_modifier & FloatMF)
2694 i.tm.base_opcode ^= 4;
29b0f896 2695 }
7ecd2f8b 2696
29b0f896
AM		 2697 return 1;
2698}
3e73aa7c 2699
29b0f896 2700static int
543613e9 2701check_byte_reg (void)
29b0f896
AM		 2702{
2703 int op;
543613e9 2704
29b0f896
AM		 2705 for (op = i.operands; --op >= 0;)
2706 {
2707 /* If this is an eight bit register, it's OK. If it's the 16 or
2708 32 bit version of an eight bit register, we will just use the
2709 low portion, and that's OK too. */
2710 if (i.types[op] & Reg8)
2711 continue;
2712
2713 /* movzx and movsx should not generate this warning. */
2714 if (intel_syntax
2715 && (i.tm.base_opcode == 0xfb7
2716 || i.tm.base_opcode == 0xfb6
2717 || i.tm.base_opcode == 0x63
2718 || i.tm.base_opcode == 0xfbe
2719 || i.tm.base_opcode == 0xfbf))
2720 continue;
2721
65ec77d2 2722 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4)
29b0f896
AM		 2723 {
2724 /* Prohibit these changes in the 64bit mode, since the
2725 lowering is more complicated. */
2726 if (flag_code == CODE_64BIT
2727 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2728 {
0f3f3d8b 2729 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2730 i.op[op].regs->reg_name,
2731 i.suffix);
2732 return 0;
2733 }
2734#if REGISTER_WARNINGS
2735 if (!quiet_warnings
2736 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2737 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2738 (i.op[op].regs + (i.types[op] & Reg16
2739 ? REGNAM_AL - REGNAM_AX
2740 : REGNAM_AL - REGNAM_EAX))->reg_name,
2741 i.op[op].regs->reg_name,
2742 i.suffix);
2743#endif
2744 continue;
2745 }
2746 /* Any other register is bad. */
2747 if (i.types[op] & (Reg | RegMMX | RegXMM
2748 | SReg2 | SReg3
2749 | Control | Debug | Test
2750 | FloatReg | FloatAcc))
2751 {
2752 as_bad (_("`%%%s' not allowed with `%s%c'"),
2753 i.op[op].regs->reg_name,
2754 i.tm.name,
2755 i.suffix);
2756 return 0;
2757 }
2758 }
2759 return 1;
2760}
2761
2762static int
2763check_long_reg ()
2764{
2765 int op;
2766
2767 for (op = i.operands; --op >= 0;)
2768 /* Reject eight bit registers, except where the template requires
2769 them. (eg. movzb) */
2770 if ((i.types[op] & Reg8) != 0
2771 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2772 {
2773 as_bad (_("`%%%s' not allowed with `%s%c'"),
2774 i.op[op].regs->reg_name,
2775 i.tm.name,
2776 i.suffix);
2777 return 0;
2778 }
2779 /* Warn if the e prefix on a general reg is missing. */
2780 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2781 && (i.types[op] & Reg16) != 0
2782 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2783 {
2784 /* Prohibit these changes in the 64bit mode, since the
2785 lowering is more complicated. */
2786 if (flag_code == CODE_64BIT)
252b5132 2787 {
0f3f3d8b 2788 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2789 i.op[op].regs->reg_name,
2790 i.suffix);
2791 return 0;
252b5132 2792 }
29b0f896
AM		 2793#if REGISTER_WARNINGS
2794 else
2795 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2796 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2797 i.op[op].regs->reg_name,
2798 i.suffix);
2799#endif
252b5132 2800 }
29b0f896
AM		 2801 /* Warn if the r prefix on a general reg is missing. */
2802 else if ((i.types[op] & Reg64) != 0
2803 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
252b5132 2804 {
0f3f3d8b 2805 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2806 i.op[op].regs->reg_name,
2807 i.suffix);
2808 return 0;
2809 }
2810 return 1;
2811}
252b5132 2812
29b0f896
AM		 2813static int
2814check_qword_reg ()
2815{
2816 int op;
252b5132 2817
29b0f896
AM		 2818 for (op = i.operands; --op >= 0; )
2819 /* Reject eight bit registers, except where the template requires
2820 them. (eg. movzb) */
2821 if ((i.types[op] & Reg8) != 0
2822 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2823 {
2824 as_bad (_("`%%%s' not allowed with `%s%c'"),
2825 i.op[op].regs->reg_name,
2826 i.tm.name,
2827 i.suffix);
2828 return 0;
2829 }
2830 /* Warn if the e prefix on a general reg is missing. */
2831 else if (((i.types[op] & Reg16) != 0
2832 || (i.types[op] & Reg32) != 0)
2833 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2834 {
2835 /* Prohibit these changes in the 64bit mode, since the
2836 lowering is more complicated. */
0f3f3d8b 2837 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2838 i.op[op].regs->reg_name,
2839 i.suffix);
2840 return 0;
252b5132 2841 }
29b0f896
AM		 2842 return 1;
2843}
252b5132 2844
29b0f896
AM		 2845static int
2846check_word_reg ()
2847{
2848 int op;
2849 for (op = i.operands; --op >= 0;)
2850 /* Reject eight bit registers, except where the template requires
2851 them. (eg. movzb) */
2852 if ((i.types[op] & Reg8) != 0
2853 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2854 {
2855 as_bad (_("`%%%s' not allowed with `%s%c'"),
2856 i.op[op].regs->reg_name,
2857 i.tm.name,
2858 i.suffix);
2859 return 0;
2860 }
2861 /* Warn if the e prefix on a general reg is present. */
2862 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2863 && (i.types[op] & Reg32) != 0
2864 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
252b5132 2865 {
29b0f896
AM		 2866 /* Prohibit these changes in the 64bit mode, since the
2867 lowering is more complicated. */
2868 if (flag_code == CODE_64BIT)
252b5132 2869 {
0f3f3d8b 2870 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
29b0f896
AM		 2871 i.op[op].regs->reg_name,
2872 i.suffix);
2873 return 0;
252b5132 2874 }
29b0f896
AM		 2875 else
2876#if REGISTER_WARNINGS
2877 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2878 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2879 i.op[op].regs->reg_name,
2880 i.suffix);
2881#endif
2882 }
2883 return 1;
2884}
252b5132 2885
29b0f896
AM		 2886static int
2887finalize_imm ()
2888{
2889 unsigned int overlap0, overlap1, overlap2;
2890
2891 overlap0 = i.types[0] & i.tm.operand_types[0];
20f0a1fc 2892 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64))
29b0f896
AM		 2893 && overlap0 != Imm8 && overlap0 != Imm8S
2894 && overlap0 != Imm16 && overlap0 != Imm32S
2895 && overlap0 != Imm32 && overlap0 != Imm64)
2896 {
2897 if (i.suffix)
2898 {
2899 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2900 ? Imm8 | Imm8S
2901 : (i.suffix == WORD_MNEM_SUFFIX
2902 ? Imm16
2903 : (i.suffix == QWORD_MNEM_SUFFIX
2904 ? Imm64 | Imm32S
2905 : Imm32)));
2906 }
2907 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2908 || overlap0 == (Imm16 | Imm32)
2909 || overlap0 == (Imm16 | Imm32S))
2910 {
2911 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2912 ? Imm16 : Imm32S);
2913 }
2914 if (overlap0 != Imm8 && overlap0 != Imm8S
2915 && overlap0 != Imm16 && overlap0 != Imm32S
2916 && overlap0 != Imm32 && overlap0 != Imm64)
2917 {
2918 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2919 return 0;
2920 }
2921 }
2922 i.types[0] = overlap0;
2923
2924 overlap1 = i.types[1] & i.tm.operand_types[1];
37edbb65 2925 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64))
29b0f896
AM		 2926 && overlap1 != Imm8 && overlap1 != Imm8S
2927 && overlap1 != Imm16 && overlap1 != Imm32S
2928 && overlap1 != Imm32 && overlap1 != Imm64)
2929 {
2930 if (i.suffix)
2931 {
2932 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2933 ? Imm8 | Imm8S
2934 : (i.suffix == WORD_MNEM_SUFFIX
2935 ? Imm16
2936 : (i.suffix == QWORD_MNEM_SUFFIX
2937 ? Imm64 | Imm32S
2938 : Imm32)));
2939 }
2940 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2941 || overlap1 == (Imm16 | Imm32)
2942 || overlap1 == (Imm16 | Imm32S))
2943 {
2944 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2945 ? Imm16 : Imm32S);
2946 }
2947 if (overlap1 != Imm8 && overlap1 != Imm8S
2948 && overlap1 != Imm16 && overlap1 != Imm32S
2949 && overlap1 != Imm32 && overlap1 != Imm64)
2950 {
2951 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2952 return 0;
2953 }
2954 }
2955 i.types[1] = overlap1;
2956
2957 overlap2 = i.types[2] & i.tm.operand_types[2];
2958 assert ((overlap2 & Imm) == 0);
2959 i.types[2] = overlap2;
2960
2961 return 1;
2962}
2963
2964static int
2965process_operands ()
2966{
2967 /* Default segment register this instruction will use for memory
2968 accesses. 0 means unknown. This is only for optimizing out
2969 unnecessary segment overrides. */
2970 const seg_entry *default_seg = 0;
2971
2972 /* The imul $imm, %reg instruction is converted into
2973 imul $imm, %reg, %reg, and the clr %reg instruction
2974 is converted into xor %reg, %reg. */
2975 if (i.tm.opcode_modifier & regKludge)
2976 {
2977 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2978 /* Pretend we saw the extra register operand. */
2979 assert (i.op[first_reg_op + 1].regs == 0);
2980 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2981 i.types[first_reg_op + 1] = i.types[first_reg_op];
2982 i.reg_operands = 2;
2983 }
2984
2985 if (i.tm.opcode_modifier & ShortForm)
2986 {
2987 /* The register or float register operand is in operand 0 or 1. */
2988 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2989 /* Register goes in low 3 bits of opcode. */
2990 i.tm.base_opcode |= i.op[op].regs->reg_num;
2991 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2992 i.rex |= REX_EXTZ;
2993 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2994 {
2995 /* Warn about some common errors, but press on regardless.
2996 The first case can be generated by gcc (<= 2.8.1). */
2997 if (i.operands == 2)
2998 {
2999 /* Reversed arguments on faddp, fsubp, etc. */
3000 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
3001 i.op[1].regs->reg_name,
3002 i.op[0].regs->reg_name);
3003 }
3004 else
3005 {
3006 /* Extraneous `l' suffix on fp insn. */
3007 as_warn (_("translating to `%s %%%s'"), i.tm.name,
3008 i.op[0].regs->reg_name);
3009 }
3010 }
3011 }
3012 else if (i.tm.opcode_modifier & Modrm)
3013 {
3014 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 3015 must be put into the modrm byte). Now, we make the modrm and
3016 index base bytes based on all the info we've collected. */
29b0f896
AM		 3017
3018 default_seg = build_modrm_byte ();
3019 }
3020 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
3021 {
3022 if (i.tm.base_opcode == POP_SEG_SHORT
3023 && i.op[0].regs->reg_num == 1)
3024 {
3025 as_bad (_("you can't `pop %%cs'"));
3026 return 0;
3027 }
3028 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
3029 if ((i.op[0].regs->reg_flags & RegRex) != 0)
3030 i.rex |= REX_EXTZ;
3031 }
3032 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
3033 {
3034 default_seg = &ds;
3035 }
3036 else if ((i.tm.opcode_modifier & IsString) != 0)
3037 {
3038 /* For the string instructions that allow a segment override
3039 on one of their operands, the default segment is ds. */
3040 default_seg = &ds;
3041 }
3042
30123838
JB		 3043 if ((i.tm.base_opcode == 0x8d /* lea */
3044 || (i.tm.cpu_flags & CpuSVME))
3045 && i.seg[0] && !quiet_warnings)
3046 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 3047
3048 /* If a segment was explicitly specified, and the specified segment
3049 is not the default, use an opcode prefix to select it. If we
3050 never figured out what the default segment is, then default_seg
3051 will be zero at this point, and the specified segment prefix will
3052 always be used. */
29b0f896
AM		 3053 if ((i.seg[0]) && (i.seg[0] != default_seg))
3054 {
3055 if (!add_prefix (i.seg[0]->seg_prefix))
3056 return 0;
3057 }
3058 return 1;
3059}
3060
3061static const seg_entry *
3062build_modrm_byte ()
3063{
3064 const seg_entry *default_seg = 0;
3065
3066 /* i.reg_operands MUST be the number of real register operands;
3067 implicit registers do not count. */
3068 if (i.reg_operands == 2)
3069 {
3070 unsigned int source, dest;
3071 source = ((i.types[0]
3072 & (Reg | RegMMX | RegXMM
3073 | SReg2 | SReg3
3074 | Control | Debug | Test))
3075 ? 0 : 1);
3076 dest = source + 1;
3077
3078 i.rm.mode = 3;
3079 /* One of the register operands will be encoded in the i.tm.reg
3080 field, the other in the combined i.tm.mode and i.tm.regmem
3081 fields. If no form of this instruction supports a memory
3082 destination operand, then we assume the source operand may
3083 sometimes be a memory operand and so we need to store the
3084 destination in the i.rm.reg field. */
3085 if ((i.tm.operand_types[dest] & AnyMem) == 0)
3086 {
3087 i.rm.reg = i.op[dest].regs->reg_num;
3088 i.rm.regmem = i.op[source].regs->reg_num;
3089 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3090 i.rex |= REX_EXTX;
3091 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3092 i.rex |= REX_EXTZ;
3093 }
3094 else
3095 {
3096 i.rm.reg = i.op[source].regs->reg_num;
3097 i.rm.regmem = i.op[dest].regs->reg_num;
3098 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
3099 i.rex |= REX_EXTZ;
3100 if ((i.op[source].regs->reg_flags & RegRex) != 0)
3101 i.rex |= REX_EXTX;
3102 }
c4a530c5
JB		 3103 if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX | REX_EXTZ)))
3104 {
3105 if (!((i.types[0] | i.types[1]) & Control))
3106 abort ();
3107 i.rex &= ~(REX_EXTX | REX_EXTZ);
3108 add_prefix (LOCK_PREFIX_OPCODE);
3109 }
29b0f896
AM		 3110 }
3111 else
3112 { /* If it's not 2 reg operands... */
3113 if (i.mem_operands)
3114 {
3115 unsigned int fake_zero_displacement = 0;
3116 unsigned int op = ((i.types[0] & AnyMem)
3117 ? 0
3118 : (i.types[1] & AnyMem) ? 1 : 2);
3119
3120 default_seg = &ds;
3121
3122 if (i.base_reg == 0)
3123 {
3124 i.rm.mode = 0;
3125 if (!i.disp_operands)
3126 fake_zero_displacement = 1;
3127 if (i.index_reg == 0)
3128 {
3129 /* Operand is just <disp> */
20f0a1fc 3130 if (flag_code == CODE_64BIT)
29b0f896
AM		 3131 {
3132 /* 64bit mode overwrites the 32bit absolute
3133 addressing by RIP relative addressing and
3134 absolute addressing is encoded by one of the
3135 redundant SIB forms. */
3136 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3137 i.sib.base = NO_BASE_REGISTER;
3138 i.sib.index = NO_INDEX_REGISTER;
20f0a1fc
NC		 3139 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0) ? Disp32S : Disp32);
3140 }
3141 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3142 {
3143 i.rm.regmem = NO_BASE_REGISTER_16;
3144 i.types[op] = Disp16;
3145 }
3146 else
3147 {
3148 i.rm.regmem = NO_BASE_REGISTER;
3149 i.types[op] = Disp32;
29b0f896
AM		 3150 }
3151 }
3152 else /* !i.base_reg && i.index_reg */
3153 {
3154 i.sib.index = i.index_reg->reg_num;
3155 i.sib.base = NO_BASE_REGISTER;
3156 i.sib.scale = i.log2_scale_factor;
3157 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3158 i.types[op] &= ~Disp;
3159 if (flag_code != CODE_64BIT)
3160 i.types[op] |= Disp32; /* Must be 32 bit */
3161 else
3162 i.types[op] |= Disp32S;
3163 if ((i.index_reg->reg_flags & RegRex) != 0)
3164 i.rex |= REX_EXTY;
3165 }
3166 }
3167 /* RIP addressing for 64bit mode. */
3168 else if (i.base_reg->reg_type == BaseIndex)
3169 {
3170 i.rm.regmem = NO_BASE_REGISTER;
20f0a1fc 3171 i.types[op] &= ~ Disp;
29b0f896
AM		 3172 i.types[op] |= Disp32S;
3173 i.flags[op] = Operand_PCrel;
20f0a1fc
NC		 3174 if (! i.disp_operands)
3175 fake_zero_displacement = 1;
29b0f896
AM		 3176 }
3177 else if (i.base_reg->reg_type & Reg16)
3178 {
3179 switch (i.base_reg->reg_num)
3180 {
3181 case 3: /* (%bx) */
3182 if (i.index_reg == 0)
3183 i.rm.regmem = 7;
3184 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
3185 i.rm.regmem = i.index_reg->reg_num - 6;
3186 break;
3187 case 5: /* (%bp) */
3188 default_seg = &ss;
3189 if (i.index_reg == 0)
3190 {
3191 i.rm.regmem = 6;
3192 if ((i.types[op] & Disp) == 0)
3193 {
3194 /* fake (%bp) into 0(%bp) */
3195 i.types[op] |= Disp8;
252b5132 3196 fake_zero_displacement = 1;
29b0f896
AM		 3197 }
3198 }
3199 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
3200 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
3201 break;
3202 default: /* (%si) -> 4 or (%di) -> 5 */
3203 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
3204 }
3205 i.rm.mode = mode_from_disp_size (i.types[op]);
3206 }
3207 else /* i.base_reg and 32/64 bit mode */
3208 {
3209 if (flag_code == CODE_64BIT
3210 && (i.types[op] & Disp))
20f0a1fc
NC		 3211 i.types[op] = (i.types[op] & Disp8) | (i.prefix[ADDR_PREFIX] == 0 ? Disp32S : Disp32);
3212
29b0f896
AM		 3213 i.rm.regmem = i.base_reg->reg_num;
3214 if ((i.base_reg->reg_flags & RegRex) != 0)
3215 i.rex |= REX_EXTZ;
3216 i.sib.base = i.base_reg->reg_num;
3217 /* x86-64 ignores REX prefix bit here to avoid decoder
3218 complications. */
3219 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
3220 {
3221 default_seg = &ss;
3222 if (i.disp_operands == 0)
3223 {
3224 fake_zero_displacement = 1;
3225 i.types[op] |= Disp8;
3226 }
3227 }
3228 else if (i.base_reg->reg_num == ESP_REG_NUM)
3229 {
3230 default_seg = &ss;
3231 }
3232 i.sib.scale = i.log2_scale_factor;
3233 if (i.index_reg == 0)
3234 {
3235 /* <disp>(%esp) becomes two byte modrm with no index
3236 register. We've already stored the code for esp
3237 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
3238 Any base register besides %esp will not use the
3239 extra modrm byte. */
3240 i.sib.index = NO_INDEX_REGISTER;
3241#if !SCALE1_WHEN_NO_INDEX
3242 /* Another case where we force the second modrm byte. */
3243 if (i.log2_scale_factor)
3244 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
252b5132 3245#endif
29b0f896
AM		 3246 }
3247 else
3248 {
3249 i.sib.index = i.index_reg->reg_num;
3250 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
3251 if ((i.index_reg->reg_flags & RegRex) != 0)
3252 i.rex |= REX_EXTY;
3253 }
67a4f2b7
AO		 3254
3255 if (i.disp_operands
3256 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3257 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
3258 i.rm.mode = 0;
3259 else
3260 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 3261 }
252b5132 3262
29b0f896
AM		 3263 if (fake_zero_displacement)
3264 {
3265 /* Fakes a zero displacement assuming that i.types[op]
3266 holds the correct displacement size. */
3267 expressionS *exp;
3268
3269 assert (i.op[op].disps == 0);
3270 exp = &disp_expressions[i.disp_operands++];
3271 i.op[op].disps = exp;
3272 exp->X_op = O_constant;
3273 exp->X_add_number = 0;
3274 exp->X_add_symbol = (symbolS *) 0;
3275 exp->X_op_symbol = (symbolS *) 0;
3276 }
3277 }
252b5132 3278
29b0f896
AM		 3279 /* Fill in i.rm.reg or i.rm.regmem field with register operand
3280 (if any) based on i.tm.extension_opcode. Again, we must be
3281 careful to make sure that segment/control/debug/test/MMX
3282 registers are coded into the i.rm.reg field. */
3283 if (i.reg_operands)
3284 {
3285 unsigned int op =
3286 ((i.types[0]
3287 & (Reg | RegMMX | RegXMM
3288 | SReg2 | SReg3
3289 | Control | Debug | Test))
3290 ? 0
3291 : ((i.types[1]
3292 & (Reg | RegMMX | RegXMM
3293 | SReg2 | SReg3
3294 | Control | Debug | Test))
3295 ? 1
3296 : 2));
3297 /* If there is an extension opcode to put here, the register
3298 number must be put into the regmem field. */
3299 if (i.tm.extension_opcode != None)
3300 {
3301 i.rm.regmem = i.op[op].regs->reg_num;
3302 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3303 i.rex |= REX_EXTZ;
3304 }
3305 else
3306 {
3307 i.rm.reg = i.op[op].regs->reg_num;
3308 if ((i.op[op].regs->reg_flags & RegRex) != 0)
3309 i.rex |= REX_EXTX;
3310 }
252b5132 3311
29b0f896
AM		 3312 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
3313 must set it to 3 to indicate this is a register operand
3314 in the regmem field. */
3315 if (!i.mem_operands)
3316 i.rm.mode = 3;
3317 }
252b5132 3318
29b0f896
AM		 3319 /* Fill in i.rm.reg field with extension opcode (if any). */
3320 if (i.tm.extension_opcode != None)
3321 i.rm.reg = i.tm.extension_opcode;
3322 }
3323 return default_seg;
3324}
252b5132 3325
29b0f896
AM		 3326static void
3327output_branch ()
3328{
3329 char *p;
3330 int code16;
3331 int prefix;
3332 relax_substateT subtype;
3333 symbolS *sym;
3334 offsetT off;
3335
3336 code16 = 0;
3337 if (flag_code == CODE_16BIT)
3338 code16 = CODE16;
3339
3340 prefix = 0;
3341 if (i.prefix[DATA_PREFIX] != 0)
252b5132 3342 {
29b0f896
AM		 3343 prefix = 1;
3344 i.prefixes -= 1;
3345 code16 ^= CODE16;
252b5132 3346 }
29b0f896
AM		 3347 /* Pentium4 branch hints. */
3348 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3349 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 3350 {
29b0f896
AM		 3351 prefix++;
3352 i.prefixes--;
3353 }
3354 if (i.prefix[REX_PREFIX] != 0)
3355 {
3356 prefix++;
3357 i.prefixes--;
2f66722d
AM		 3358 }
3359
29b0f896
AM		 3360 if (i.prefixes != 0 && !intel_syntax)
3361 as_warn (_("skipping prefixes on this instruction"));
3362
3363 /* It's always a symbol; End frag & setup for relax.
3364 Make sure there is enough room in this frag for the largest
3365 instruction we may generate in md_convert_frag. This is 2
3366 bytes for the opcode and room for the prefix and largest
3367 displacement. */
3368 frag_grow (prefix + 2 + 4);
3369 /* Prefix and 1 opcode byte go in fr_fix. */
3370 p = frag_more (prefix + 1);
3371 if (i.prefix[DATA_PREFIX] != 0)
3372 *p++ = DATA_PREFIX_OPCODE;
3373 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
3374 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
3375 *p++ = i.prefix[SEG_PREFIX];
3376 if (i.prefix[REX_PREFIX] != 0)
3377 *p++ = i.prefix[REX_PREFIX];
3378 *p = i.tm.base_opcode;
3379
3380 if ((unsigned char) *p == JUMP_PC_RELATIVE)
3381 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
3382 else if ((cpu_arch_flags & Cpu386) != 0)
3383 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
3384 else
3385 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
3386 subtype |= code16;
3e73aa7c 3387
29b0f896
AM		 3388 sym = i.op[0].disps->X_add_symbol;
3389 off = i.op[0].disps->X_add_number;
3e73aa7c 3390
29b0f896
AM		 3391 if (i.op[0].disps->X_op != O_constant
3392 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 3393 {
29b0f896
AM		 3394 /* Handle complex expressions. */
3395 sym = make_expr_symbol (i.op[0].disps);
3396 off = 0;
3397 }
3e73aa7c 3398
29b0f896
AM		 3399 /* 1 possible extra opcode + 4 byte displacement go in var part.
3400 Pass reloc in fr_var. */
3401 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3402}
3e73aa7c 3403
29b0f896
AM		 3404static void
3405output_jump ()
3406{
3407 char *p;
3408 int size;
3e02c1cc 3409 fixS *fixP;
29b0f896
AM		 3410
3411 if (i.tm.opcode_modifier & JumpByte)
3412 {
3413 /* This is a loop or jecxz type instruction. */
3414 size = 1;
3415 if (i.prefix[ADDR_PREFIX] != 0)
3416 {
3417 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3418 i.prefixes -= 1;
3419 }
3420 /* Pentium4 branch hints. */
3421 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3422 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3423 {
3424 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3425 i.prefixes--;
3e73aa7c
JH		 3426 }
3427 }
29b0f896
AM		 3428 else
3429 {
3430 int code16;
3e73aa7c 3431
29b0f896
AM		 3432 code16 = 0;
3433 if (flag_code == CODE_16BIT)
3434 code16 = CODE16;
3e73aa7c 3435
29b0f896
AM		 3436 if (i.prefix[DATA_PREFIX] != 0)
3437 {
3438 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3439 i.prefixes -= 1;
3440 code16 ^= CODE16;
3441 }
252b5132 3442
29b0f896
AM		 3443 size = 4;
3444 if (code16)
3445 size = 2;
3446 }
9fcc94b6 3447
29b0f896
AM		 3448 if (i.prefix[REX_PREFIX] != 0)
3449 {
3450 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3451 i.prefixes -= 1;
3452 }
252b5132 3453
29b0f896
AM		 3454 if (i.prefixes != 0 && !intel_syntax)
3455 as_warn (_("skipping prefixes on this instruction"));
e0890092 3456
29b0f896
AM		 3457 p = frag_more (1 + size);
3458 *p++ = i.tm.base_opcode;
e0890092 3459
3e02c1cc
AM		 3460 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3461 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3462
3463 /* All jumps handled here are signed, but don't use a signed limit
3464 check for 32 and 16 bit jumps as we want to allow wrap around at
3465 4G and 64k respectively. */
3466 if (size == 1)
3467 fixP->fx_signed = 1;
29b0f896 3468}
e0890092 3469
29b0f896
AM		 3470static void
3471output_interseg_jump ()
3472{
3473 char *p;
3474 int size;
3475 int prefix;
3476 int code16;
252b5132 3477
29b0f896
AM		 3478 code16 = 0;
3479 if (flag_code == CODE_16BIT)
3480 code16 = CODE16;
a217f122 3481
29b0f896
AM		 3482 prefix = 0;
3483 if (i.prefix[DATA_PREFIX] != 0)
3484 {
3485 prefix = 1;
3486 i.prefixes -= 1;
3487 code16 ^= CODE16;
3488 }
3489 if (i.prefix[REX_PREFIX] != 0)
3490 {
3491 prefix++;
3492 i.prefixes -= 1;
3493 }
252b5132 3494
29b0f896
AM		 3495 size = 4;
3496 if (code16)
3497 size = 2;
252b5132 3498
29b0f896
AM		 3499 if (i.prefixes != 0 && !intel_syntax)
3500 as_warn (_("skipping prefixes on this instruction"));
252b5132 3501
29b0f896
AM		 3502 /* 1 opcode; 2 segment; offset */
3503 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 3504
29b0f896
AM		 3505 if (i.prefix[DATA_PREFIX] != 0)
3506 *p++ = DATA_PREFIX_OPCODE;
252b5132 3507
29b0f896
AM		 3508 if (i.prefix[REX_PREFIX] != 0)
3509 *p++ = i.prefix[REX_PREFIX];
252b5132 3510
29b0f896
AM		 3511 *p++ = i.tm.base_opcode;
3512 if (i.op[1].imms->X_op == O_constant)
3513 {
3514 offsetT n = i.op[1].imms->X_add_number;
252b5132 3515
29b0f896
AM		 3516 if (size == 2
3517 && !fits_in_unsigned_word (n)
3518 && !fits_in_signed_word (n))
3519 {
3520 as_bad (_("16-bit jump out of range"));
3521 return;
3522 }
3523 md_number_to_chars (p, n, size);
3524 }
3525 else
3526 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3527 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3528 if (i.op[0].imms->X_op != O_constant)
3529 as_bad (_("can't handle non absolute segment in `%s'"),
3530 i.tm.name);
3531 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3532}
a217f122 3533
29b0f896
AM		 3534static void
3535output_insn ()
3536{
2bbd9c25
JJ		 3537 fragS *insn_start_frag;
3538 offsetT insn_start_off;
3539
29b0f896
AM		 3540 /* Tie dwarf2 debug info to the address at the start of the insn.
3541 We can't do this after the insn has been output as the current
3542 frag may have been closed off. eg. by frag_var. */
3543 dwarf2_emit_insn (0);
3544
2bbd9c25
JJ		 3545 insn_start_frag = frag_now;
3546 insn_start_off = frag_now_fix ();
3547
29b0f896
AM		 3548 /* Output jumps. */
3549 if (i.tm.opcode_modifier & Jump)
3550 output_branch ();
3551 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3552 output_jump ();
3553 else if (i.tm.opcode_modifier & JumpInterSegment)
3554 output_interseg_jump ();
3555 else
3556 {
3557 /* Output normal instructions here. */
3558 char *p;
3559 unsigned char *q;
331d2d0d 3560 unsigned int prefix;
252b5132 3561
331d2d0d
L		 3562 /* All opcodes on i386 have either 1 or 2 bytes. Merom New
3563 Instructions have 3 bytes. We may use one more higher byte
3564 to specify a prefix the instruction requires. */
3565 if ((i.tm.cpu_flags & CpuMNI) != 0)
bc4bd9ab 3566 {
331d2d0d
L		 3567 if (i.tm.base_opcode & 0xff000000)
3568 {
3569 prefix = (i.tm.base_opcode >> 24) & 0xff;
3570 goto check_prefix;
3571 }
3572 }
3573 else if ((i.tm.base_opcode & 0xff0000) != 0)
3574 {
3575 prefix = (i.tm.base_opcode >> 16) & 0xff;
bc4bd9ab
MK		 3576 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3577 {
64e74474 3578 check_prefix:
bc4bd9ab
MK		 3579 if (prefix != REPE_PREFIX_OPCODE
3580 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3581 add_prefix (prefix);
3582 }
3583 else
331d2d0d 3584 add_prefix (prefix);
0f10071e 3585 }
252b5132 3586
29b0f896
AM		 3587 /* The prefix bytes. */
3588 for (q = i.prefix;
3589 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3590 q++)
3591 {
3592 if (*q)
3593 {
3594 p = frag_more (1);
3595 md_number_to_chars (p, (valueT) *q, 1);
3596 }
3597 }
252b5132 3598
29b0f896
AM		 3599 /* Now the opcode; be careful about word order here! */
3600 if (fits_in_unsigned_byte (i.tm.base_opcode))
3601 {
3602 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3603 }
3604 else
3605 {
331d2d0d
L		 3606 if ((i.tm.cpu_flags & CpuMNI) != 0)
3607 {
3608 p = frag_more (3);
3609 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3610 }
3611 else
3612 p = frag_more (2);
0f10071e 3613
29b0f896
AM		 3614 /* Put out high byte first: can't use md_number_to_chars! */
3615 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3616 *p = i.tm.base_opcode & 0xff;
3617 }
3e73aa7c 3618
29b0f896
AM		 3619 /* Now the modrm byte and sib byte (if present). */
3620 if (i.tm.opcode_modifier & Modrm)
3621 {
3622 p = frag_more (1);
3623 md_number_to_chars (p,
3624 (valueT) (i.rm.regmem << 0
3625 | i.rm.reg << 3
3626 | i.rm.mode << 6),
3627 1);
3628 /* If i.rm.regmem == ESP (4)
3629 && i.rm.mode != (Register mode)
3630 && not 16 bit
3631 ==> need second modrm byte. */
3632 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3633 && i.rm.mode != 3
3634 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3635 {
3636 p = frag_more (1);
3637 md_number_to_chars (p,
3638 (valueT) (i.sib.base << 0
3639 | i.sib.index << 3
3640 | i.sib.scale << 6),
3641 1);
3642 }
3643 }
3e73aa7c 3644
29b0f896 3645 if (i.disp_operands)
2bbd9c25 3646 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 3647
29b0f896 3648 if (i.imm_operands)
2bbd9c25 3649 output_imm (insn_start_frag, insn_start_off);
29b0f896 3650 }
252b5132 3651
29b0f896
AM		 3652#ifdef DEBUG386
3653 if (flag_debug)
3654 {
7b81dfbb 3655 pi ("" /*line*/, &i);
29b0f896
AM		 3656 }
3657#endif /* DEBUG386 */
3658}
252b5132 3659
29b0f896 3660static void
64e74474 3661output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3662{
3663 char *p;
3664 unsigned int n;
252b5132 3665
29b0f896
AM		 3666 for (n = 0; n < i.operands; n++)
3667 {
3668 if (i.types[n] & Disp)
3669 {
3670 if (i.op[n].disps->X_op == O_constant)
3671 {
3672 int size;
3673 offsetT val;
252b5132 3674
29b0f896
AM		 3675 size = 4;
3676 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3677 {
3678 size = 2;
3679 if (i.types[n] & Disp8)
3680 size = 1;
3681 if (i.types[n] & Disp64)
3682 size = 8;
3683 }
3684 val = offset_in_range (i.op[n].disps->X_add_number,
3685 size);
3686 p = frag_more (size);
3687 md_number_to_chars (p, val, size);
3688 }
3689 else
3690 {
f86103b7 3691 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3692 int size = 4;
3693 int sign = 0;
3694 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3695
3696 /* The PC relative address is computed relative
3697 to the instruction boundary, so in case immediate
3698 fields follows, we need to adjust the value. */
3699 if (pcrel && i.imm_operands)
3700 {
3701 int imm_size = 4;
3702 unsigned int n1;
252b5132 3703
29b0f896
AM		 3704 for (n1 = 0; n1 < i.operands; n1++)
3705 if (i.types[n1] & Imm)
252b5132 3706 {
29b0f896 3707 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
252b5132 3708 {
29b0f896
AM		 3709 imm_size = 2;
3710 if (i.types[n1] & (Imm8 | Imm8S))
3711 imm_size = 1;
3712 if (i.types[n1] & Imm64)
3713 imm_size = 8;
252b5132 3714 }
29b0f896 3715 break;
252b5132 3716 }
29b0f896
AM		 3717 /* We should find the immediate. */
3718 if (n1 == i.operands)
3719 abort ();
3720 i.op[n].disps->X_add_number -= imm_size;
3721 }
520dc8e8 3722
29b0f896
AM		 3723 if (i.types[n] & Disp32S)
3724 sign = 1;
3e73aa7c 3725
29b0f896
AM		 3726 if (i.types[n] & (Disp16 | Disp64))
3727 {
3728 size = 2;
3729 if (i.types[n] & Disp64)
3730 size = 8;
3731 }
520dc8e8 3732
29b0f896 3733 p = frag_more (size);
2bbd9c25 3734 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 3735 if (GOT_symbol
2bbd9c25 3736 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 3737 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 3738 || reloc_type == BFD_RELOC_X86_64_32S
3739 || (reloc_type == BFD_RELOC_64
3740 && object_64bit))
d6ab8113
JB		 3741 && (i.op[n].disps->X_op == O_symbol
3742 || (i.op[n].disps->X_op == O_add
3743 && ((symbol_get_value_expression
3744 (i.op[n].disps->X_op_symbol)->X_op)
3745 == O_subtract))))
3746 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 3747 {
3748 offsetT add;
3749
3750 if (insn_start_frag == frag_now)
3751 add = (p - frag_now->fr_literal) - insn_start_off;
3752 else
3753 {
3754 fragS *fr;
3755
3756 add = insn_start_frag->fr_fix - insn_start_off;
3757 for (fr = insn_start_frag->fr_next;
3758 fr && fr != frag_now; fr = fr->fr_next)
3759 add += fr->fr_fix;
3760 add += p - frag_now->fr_literal;
3761 }
3762
4fa24527 3763 if (!object_64bit)
7b81dfbb
AJ		 3764 {
3765 reloc_type = BFD_RELOC_386_GOTPC;
3766 i.op[n].imms->X_add_number += add;
3767 }
3768 else if (reloc_type == BFD_RELOC_64)
3769 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 3770 else
7b81dfbb
AJ		 3771 /* Don't do the adjustment for x86-64, as there
3772 the pcrel addressing is relative to the _next_
3773 insn, and that is taken care of in other code. */
d6ab8113 3774 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 3775 }
062cd5e7 3776 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 3777 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 3778 }
3779 }
3780 }
3781}
252b5132 3782
29b0f896 3783static void
64e74474 3784output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 3785{
3786 char *p;
3787 unsigned int n;
252b5132 3788
29b0f896
AM		 3789 for (n = 0; n < i.operands; n++)
3790 {
3791 if (i.types[n] & Imm)
3792 {
3793 if (i.op[n].imms->X_op == O_constant)
3794 {
3795 int size;
3796 offsetT val;
b4cac588 3797
29b0f896
AM		 3798 size = 4;
3799 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3800 {
3801 size = 2;
3802 if (i.types[n] & (Imm8 | Imm8S))
3803 size = 1;
3804 else if (i.types[n] & Imm64)
3805 size = 8;
3806 }
3807 val = offset_in_range (i.op[n].imms->X_add_number,
3808 size);
3809 p = frag_more (size);
3810 md_number_to_chars (p, val, size);
3811 }
3812 else
3813 {
3814 /* Not absolute_section.
3815 Need a 32-bit fixup (don't support 8bit
3816 non-absolute imms). Try to support other
3817 sizes ... */
f86103b7 3818 enum bfd_reloc_code_real reloc_type;
29b0f896
AM		 3819 int size = 4;
3820 int sign = 0;
3821
3822 if ((i.types[n] & (Imm32S))
a7d61044
JB		 3823 && (i.suffix == QWORD_MNEM_SUFFIX
3824 || (!i.suffix && (i.tm.opcode_modifier & No_lSuf))))
29b0f896
AM		 3825 sign = 1;
3826 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3827 {
3828 size = 2;
3829 if (i.types[n] & (Imm8 | Imm8S))
3830 size = 1;
3831 if (i.types[n] & Imm64)
3832 size = 8;
3833 }
520dc8e8 3834
29b0f896
AM		 3835 p = frag_more (size);
3836 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 3837
2bbd9c25
JJ		 3838 /* This is tough to explain. We end up with this one if we
3839 * have operands that look like
3840 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3841 * obtain the absolute address of the GOT, and it is strongly
3842 * preferable from a performance point of view to avoid using
3843 * a runtime relocation for this. The actual sequence of
3844 * instructions often look something like:
3845 *
3846 * call .L66
3847 * .L66:
3848 * popl %ebx
3849 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3850 *
3851 * The call and pop essentially return the absolute address
3852 * of the label .L66 and store it in %ebx. The linker itself
3853 * will ultimately change the first operand of the addl so
3854 * that %ebx points to the GOT, but to keep things simple, the
3855 * .o file must have this operand set so that it generates not
3856 * the absolute address of .L66, but the absolute address of
3857 * itself. This allows the linker itself simply treat a GOTPC
3858 * relocation as asking for a pcrel offset to the GOT to be
3859 * added in, and the addend of the relocation is stored in the
3860 * operand field for the instruction itself.
3861 *
3862 * Our job here is to fix the operand so that it would add
3863 * the correct offset so that %ebx would point to itself. The
3864 * thing that is tricky is that .-.L66 will point to the
3865 * beginning of the instruction, so we need to further modify
3866 * the operand so that it will point to itself. There are
3867 * other cases where you have something like:
3868 *
3869 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3870 *
3871 * and here no correction would be required. Internally in
3872 * the assembler we treat operands of this form as not being
3873 * pcrel since the '.' is explicitly mentioned, and I wonder
3874 * whether it would simplify matters to do it this way. Who
3875 * knows. In earlier versions of the PIC patches, the
3876 * pcrel_adjust field was used to store the correction, but
3877 * since the expression is not pcrel, I felt it would be
3878 * confusing to do it this way. */
3879
d6ab8113 3880 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 3881 || reloc_type == BFD_RELOC_X86_64_32S
3882 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 3883 && GOT_symbol
3884 && GOT_symbol == i.op[n].imms->X_add_symbol
3885 && (i.op[n].imms->X_op == O_symbol
3886 || (i.op[n].imms->X_op == O_add
3887 && ((symbol_get_value_expression
3888 (i.op[n].imms->X_op_symbol)->X_op)
3889 == O_subtract))))
3890 {
2bbd9c25
JJ		 3891 offsetT add;
3892
3893 if (insn_start_frag == frag_now)
3894 add = (p - frag_now->fr_literal) - insn_start_off;
3895 else
3896 {
3897 fragS *fr;
3898
3899 add = insn_start_frag->fr_fix - insn_start_off;
3900 for (fr = insn_start_frag->fr_next;
3901 fr && fr != frag_now; fr = fr->fr_next)
3902 add += fr->fr_fix;
3903 add += p - frag_now->fr_literal;
3904 }
3905
4fa24527 3906 if (!object_64bit)
d6ab8113 3907 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 3908 else if (size == 4)
d6ab8113 3909 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 3910 else if (size == 8)
3911 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 3912 i.op[n].imms->X_add_number += add;
29b0f896 3913 }
29b0f896
AM		 3914 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3915 i.op[n].imms, 0, reloc_type);
3916 }
3917 }
3918 }
252b5132
RH		 3919}
3920\f
d182319b
JB		 3921/* x86_cons_fix_new is called via the expression parsing code when a
3922 reloc is needed. We use this hook to get the correct .got reloc. */
3923static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3924static int cons_sign = -1;
3925
3926void
3927x86_cons_fix_new (fragS *frag,
64e74474
AM		 3928 unsigned int off,
3929 unsigned int len,
3930 expressionS *exp)
d182319b
JB		 3931{
3932 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
3933
3934 got_reloc = NO_RELOC;
3935
3936#ifdef TE_PE
3937 if (exp->X_op == O_secrel)
3938 {
3939 exp->X_op = O_symbol;
3940 r = BFD_RELOC_32_SECREL;
3941 }
3942#endif
3943
3944 fix_new_exp (frag, off, len, exp, 0, r);
3945}
3946
718ddfc0
JB		 3947#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
3948# define lex_got(reloc, adjust, types) NULL
3949#else
f3c180ae
AM		 3950/* Parse operands of the form
3951 <symbol>@GOTOFF+<nnn>
3952 and similar .plt or .got references.
3953
3954 If we find one, set up the correct relocation in RELOC and copy the
3955 input string, minus the `@GOTOFF' into a malloc'd buffer for
3956 parsing by the calling routine. Return this buffer, and if ADJUST
3957 is non-null set it to the length of the string we removed from the
3958 input line. Otherwise return NULL. */
3959static char *
3956db08 3960lex_got (enum bfd_reloc_code_real *reloc,
64e74474
AM		 3961 int *adjust,
3962 unsigned int *types)
f3c180ae 3963{
7b81dfbb
AJ		 3964 /* Some of the relocations depend on the size of what field is to
3965 be relocated. But in our callers i386_immediate and i386_displacement
3966 we don't yet know the operand size (this will be set by insn
3967 matching). Hence we record the word32 relocation here,
3968 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 3969 static const struct {
3970 const char *str;
4fa24527 3971 const enum bfd_reloc_code_real rel[2];
3956db08 3972 const unsigned int types64;
f3c180ae 3973 } gotrel[] = {
7b81dfbb 3974 { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm64 },
4fa24527 3975 { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm32|Imm32S|Disp32 },
7b81dfbb 3976 { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm64|Disp64 },
4fa24527
JB		 3977 { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm64|Disp64 },
3978 { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm32|Imm32S|Disp32 },
3979 { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm32|Imm32S|Disp32 },
3980 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 },
3981 { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm32|Imm32S|Disp32 },
3982 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm32|Imm32S|Disp32 },
3983 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3984 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 },
3985 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm32|Imm32S|Imm64|Disp32|Disp64 },
3986 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 },
3987 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 },
7b81dfbb 3988 { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm32|Imm32S|Disp32|Imm64 },
67a4f2b7
AO		 3989 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm32|Imm32S|Disp32 },
3990 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm32|Imm32S|Disp32 }
f3c180ae
AM		 3991 };
3992 char *cp;
3993 unsigned int j;
3994
718ddfc0
JB		 3995 if (!IS_ELF)
3996 return NULL;
3997
f3c180ae
AM		 3998 for (cp = input_line_pointer; *cp != '@'; cp++)
3999 if (is_end_of_line[(unsigned char) *cp])
4000 return NULL;
4001
4002 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
4003 {
4004 int len;
4005
4006 len = strlen (gotrel[j].str);
28f81592 4007 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 4008 {
4fa24527 4009 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 4010 {
28f81592
AM		 4011 int first, second;
4012 char *tmpbuf, *past_reloc;
f3c180ae 4013
4fa24527 4014 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 4015 if (adjust)
4016 *adjust = len;
f3c180ae 4017
3956db08
JB		 4018 if (types)
4019 {
4020 if (flag_code != CODE_64BIT)
4021 *types = Imm32|Disp32;
4022 else
4023 *types = gotrel[j].types64;
4024 }
4025
f3c180ae
AM		 4026 if (GOT_symbol == NULL)
4027 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
4028
4029 /* Replace the relocation token with ' ', so that
4030 errors like foo@GOTOFF1 will be detected. */
28f81592
AM		 4031
4032 /* The length of the first part of our input line. */
f3c180ae 4033 first = cp - input_line_pointer;
28f81592
AM		 4034
4035 /* The second part goes from after the reloc token until
4036 (and including) an end_of_line char. Don't use strlen
4037 here as the end_of_line char may not be a NUL. */
4038 past_reloc = cp + 1 + len;
4039 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
4040 ;
4041 second = cp - past_reloc;
4042
4043 /* Allocate and copy string. The trailing NUL shouldn't
4044 be necessary, but be safe. */
4045 tmpbuf = xmalloc (first + second + 2);
f3c180ae
AM		 4046 memcpy (tmpbuf, input_line_pointer, first);
4047 tmpbuf[first] = ' ';
28f81592
AM		 4048 memcpy (tmpbuf + first + 1, past_reloc, second);
4049 tmpbuf[first + second + 1] = '\0';
f3c180ae
AM		 4050 return tmpbuf;
4051 }
4052
4fa24527
JB		 4053 as_bad (_("@%s reloc is not supported with %d-bit output format"),
4054 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 4055 return NULL;
4056 }
4057 }
4058
4059 /* Might be a symbol version string. Don't as_bad here. */
4060 return NULL;
4061}
4062
f3c180ae
AM		 4063void
4064x86_cons (exp, size)
4065 expressionS *exp;
4066 int size;
4067{
4fa24527 4068 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 4069 {
4070 /* Handle @GOTOFF and the like in an expression. */
4071 char *save;
4072 char *gotfree_input_line;
4073 int adjust;
4074
4075 save = input_line_pointer;
3956db08 4076 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 4077 if (gotfree_input_line)
4078 input_line_pointer = gotfree_input_line;
4079
4080 expression (exp);
4081
4082 if (gotfree_input_line)
4083 {
4084 /* expression () has merrily parsed up to the end of line,
4085 or a comma - in the wrong buffer. Transfer how far
4086 input_line_pointer has moved to the right buffer. */
4087 input_line_pointer = (save
4088 + (input_line_pointer - gotfree_input_line)
4089 + adjust);
4090 free (gotfree_input_line);
4091 }
4092 }
4093 else
4094 expression (exp);
4095}
4096#endif
4097
d182319b 4098static void signed_cons (int size)
6482c264 4099{
d182319b
JB		 4100 if (flag_code == CODE_64BIT)
4101 cons_sign = 1;
4102 cons (size);
4103 cons_sign = -1;
6482c264
NC		 4104}
4105
d182319b 4106#ifdef TE_PE
6482c264
NC		 4107static void
4108pe_directive_secrel (dummy)
4109 int dummy ATTRIBUTE_UNUSED;
4110{
4111 expressionS exp;
4112
4113 do
4114 {
4115 expression (&exp);
4116 if (exp.X_op == O_symbol)
4117 exp.X_op = O_secrel;
4118
4119 emit_expr (&exp, 4);
4120 }
4121 while (*input_line_pointer++ == ',');
4122
4123 input_line_pointer--;
4124 demand_empty_rest_of_line ();
4125}
6482c264
NC		 4126#endif
4127
252b5132
RH		 4128static int i386_immediate PARAMS ((char *));
4129
4130static int
4131i386_immediate (imm_start)
4132 char *imm_start;
4133{
4134 char *save_input_line_pointer;
f3c180ae 4135 char *gotfree_input_line;
252b5132 4136 segT exp_seg = 0;
47926f60 4137 expressionS *exp;
3956db08 4138 unsigned int types = ~0U;
252b5132
RH		 4139
4140 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
4141 {
d0b47220 4142 as_bad (_("only 1 or 2 immediate operands are allowed"));
252b5132
RH		 4143 return 0;
4144 }
4145
4146 exp = &im_expressions[i.imm_operands++];
520dc8e8 4147 i.op[this_operand].imms = exp;
252b5132
RH		 4148
4149 if (is_space_char (*imm_start))
4150 ++imm_start;
4151
4152 save_input_line_pointer = input_line_pointer;
4153 input_line_pointer = imm_start;
4154
3956db08 4155 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4156 if (gotfree_input_line)
4157 input_line_pointer = gotfree_input_line;
252b5132
RH		 4158
4159 exp_seg = expression (exp);
4160
83183c0c 4161 SKIP_WHITESPACE ();
252b5132 4162 if (*input_line_pointer)
f3c180ae 4163 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 4164
4165 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 4166 if (gotfree_input_line)
4167 free (gotfree_input_line);
252b5132 4168
2daf4fd8 4169 if (exp->X_op == O_absent || exp->X_op == O_big)
252b5132 4170 {
47926f60 4171 /* Missing or bad expr becomes absolute 0. */
d0b47220 4172 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
24eab124 4173 imm_start);
252b5132
RH		 4174 exp->X_op = O_constant;
4175 exp->X_add_number = 0;
4176 exp->X_add_symbol = (symbolS *) 0;
4177 exp->X_op_symbol = (symbolS *) 0;
252b5132 4178 }
3e73aa7c 4179 else if (exp->X_op == O_constant)
252b5132 4180 {
47926f60 4181 /* Size it properly later. */
3e73aa7c
JH		 4182 i.types[this_operand] |= Imm64;
4183 /* If BFD64, sign extend val. */
4184 if (!use_rela_relocations)
4185 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
4186 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 4187 }
4c63da97 4188#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 4189 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4190 && exp_seg != absolute_section
47926f60 4191 && exp_seg != text_section
24eab124
AM		 4192 && exp_seg != data_section
4193 && exp_seg != bss_section
4194 && exp_seg != undefined_section
f86103b7 4195 && !bfd_is_com_section (exp_seg))
252b5132 4196 {
d0b47220 4197 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 4198 return 0;
4199 }
4200#endif
bb8f5920
L		 4201 else if (!intel_syntax && exp->X_op == O_register)
4202 {
4203 as_bad (_("illegal immediate register operand %s"), imm_start);
4204 return 0;
4205 }
252b5132
RH		 4206 else
4207 {
4208 /* This is an address. The size of the address will be
24eab124 4209 determined later, depending on destination register,
3e73aa7c
JH		 4210 suffix, or the default for the section. */
4211 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3956db08 4212 i.types[this_operand] &= types;
252b5132
RH		 4213 }
4214
4215 return 1;
4216}
4217
551c1ca1 4218static char *i386_scale PARAMS ((char *));
252b5132 4219
551c1ca1 4220static char *
252b5132
RH		 4221i386_scale (scale)
4222 char *scale;
4223{
551c1ca1
AM		 4224 offsetT val;
4225 char *save = input_line_pointer;
252b5132 4226
551c1ca1
AM		 4227 input_line_pointer = scale;
4228 val = get_absolute_expression ();
4229
4230 switch (val)
252b5132 4231 {
551c1ca1 4232 case 1:
252b5132
RH		 4233 i.log2_scale_factor = 0;
4234 break;
551c1ca1 4235 case 2:
252b5132
RH		 4236 i.log2_scale_factor = 1;
4237 break;
551c1ca1 4238 case 4:
252b5132
RH		 4239 i.log2_scale_factor = 2;
4240 break;
551c1ca1 4241 case 8:
252b5132
RH		 4242 i.log2_scale_factor = 3;
4243 break;
4244 default:
a724f0f4
JB		 4245 {
4246 char sep = *input_line_pointer;
4247
4248 *input_line_pointer = '\0';
4249 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
4250 scale);
4251 *input_line_pointer = sep;
4252 input_line_pointer = save;
4253 return NULL;
4254 }
252b5132 4255 }
29b0f896 4256 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 4257 {
4258 as_warn (_("scale factor of %d without an index register"),
24eab124 4259 1 << i.log2_scale_factor);
252b5132
RH		 4260#if SCALE1_WHEN_NO_INDEX
4261 i.log2_scale_factor = 0;
4262#endif
4263 }
551c1ca1
AM		 4264 scale = input_line_pointer;
4265 input_line_pointer = save;
4266 return scale;
252b5132
RH		 4267}
4268
4269static int i386_displacement PARAMS ((char *, char *));
4270
4271static int
4272i386_displacement (disp_start, disp_end)
4273 char *disp_start;
4274 char *disp_end;
4275{
29b0f896 4276 expressionS *exp;
252b5132
RH		 4277 segT exp_seg = 0;
4278 char *save_input_line_pointer;
f3c180ae 4279 char *gotfree_input_line;
e05278af 4280 int bigdisp, override;
3956db08 4281 unsigned int types = Disp;
252b5132 4282
e05278af
JB		 4283 if ((i.types[this_operand] & JumpAbsolute)
4284 || !(current_templates->start->opcode_modifier & (Jump | JumpDword)))
4285 {
4286 bigdisp = Disp32;
4287 override = (i.prefix[ADDR_PREFIX] != 0);
4288 }
4289 else
4290 {
4291 /* For PC-relative branches, the width of the displacement
4292 is dependent upon data size, not address size. */
4293 bigdisp = 0;
4294 override = (i.prefix[DATA_PREFIX] != 0);
4295 }
3e73aa7c 4296 if (flag_code == CODE_64BIT)
7ecd2f8b 4297 {
e05278af 4298 if (!bigdisp)
64e74474
AM		 4299 bigdisp = ((override || i.suffix == WORD_MNEM_SUFFIX)
4300 ? Disp16
4301 : Disp32S | Disp32);
e05278af 4302 else if (!override)
3956db08 4303 bigdisp = Disp64 | Disp32S | Disp32;
7ecd2f8b 4304 }
e05278af
JB		 4305 else
4306 {
4307 if (!bigdisp)
4308 {
4309 if (!override)
4310 override = (i.suffix == (flag_code != CODE_16BIT
4311 ? WORD_MNEM_SUFFIX
4312 : LONG_MNEM_SUFFIX));
4313 bigdisp = Disp32;
4314 }
4315 if ((flag_code == CODE_16BIT) ^ override)
4316 bigdisp = Disp16;
4317 }
252b5132
RH		 4318 i.types[this_operand] |= bigdisp;
4319
4320 exp = &disp_expressions[i.disp_operands];
520dc8e8 4321 i.op[this_operand].disps = exp;
252b5132
RH		 4322 i.disp_operands++;
4323 save_input_line_pointer = input_line_pointer;
4324 input_line_pointer = disp_start;
4325 END_STRING_AND_SAVE (disp_end);
4326
4327#ifndef GCC_ASM_O_HACK
4328#define GCC_ASM_O_HACK 0
4329#endif
4330#if GCC_ASM_O_HACK
4331 END_STRING_AND_SAVE (disp_end + 1);
4332 if ((i.types[this_operand] & BaseIndex) != 0
24eab124 4333 && displacement_string_end[-1] == '+')
252b5132
RH		 4334 {
4335 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 4336 constraint within gcc asm statements.
4337 For instance:
4338
4339 #define _set_tssldt_desc(n,addr,limit,type) \
4340 __asm__ __volatile__ ( \
4341 "movw %w2,%0\n\t" \
4342 "movw %w1,2+%0\n\t" \
4343 "rorl $16,%1\n\t" \
4344 "movb %b1,4+%0\n\t" \
4345 "movb %4,5+%0\n\t" \
4346 "movb $0,6+%0\n\t" \
4347 "movb %h1,7+%0\n\t" \
4348 "rorl $16,%1" \
4349 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
4350
4351 This works great except that the output assembler ends
4352 up looking a bit weird if it turns out that there is
4353 no offset. You end up producing code that looks like:
4354
4355 #APP
4356 movw $235,(%eax)
4357 movw %dx,2+(%eax)
4358 rorl $16,%edx
4359 movb %dl,4+(%eax)
4360 movb $137,5+(%eax)
4361 movb $0,6+(%eax)
4362 movb %dh,7+(%eax)
4363 rorl $16,%edx
4364 #NO_APP
4365
47926f60 4366 So here we provide the missing zero. */
24eab124
AM		 4367
4368 *displacement_string_end = '0';
252b5132
RH		 4369 }
4370#endif
3956db08 4371 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 4372 if (gotfree_input_line)
4373 input_line_pointer = gotfree_input_line;
252b5132 4374
24eab124 4375 exp_seg = expression (exp);
252b5132 4376
636c26b0
AM		 4377 SKIP_WHITESPACE ();
4378 if (*input_line_pointer)
4379 as_bad (_("junk `%s' after expression"), input_line_pointer);
4380#if GCC_ASM_O_HACK
4381 RESTORE_END_STRING (disp_end + 1);
4382#endif
4383 RESTORE_END_STRING (disp_end);
4384 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 4385 if (gotfree_input_line)
4386 free (gotfree_input_line);
636c26b0 4387
24eab124
AM		 4388 /* We do this to make sure that the section symbol is in
4389 the symbol table. We will ultimately change the relocation
47926f60 4390 to be relative to the beginning of the section. */
1ae12ab7 4391 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 4392 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4393 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 4394 {
636c26b0
AM		 4395 if (exp->X_op != O_symbol)
4396 {
4397 as_bad (_("bad expression used with @%s"),
4398 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
4399 ? "GOTPCREL"
4400 : "GOTOFF"));
4401 return 0;
4402 }
4403
e5cb08ac 4404 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 4405 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
4406 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 4407 exp->X_op = O_subtract;
4408 exp->X_op_symbol = GOT_symbol;
1ae12ab7 4409 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 4410 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 4411 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
4412 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 4413 else
29b0f896 4414 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 4415 }
252b5132 4416
2daf4fd8
AM		 4417 if (exp->X_op == O_absent || exp->X_op == O_big)
4418 {
47926f60 4419 /* Missing or bad expr becomes absolute 0. */
d0b47220 4420 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
2daf4fd8
AM		 4421 disp_start);
4422 exp->X_op = O_constant;
4423 exp->X_add_number = 0;
4424 exp->X_add_symbol = (symbolS *) 0;
4425 exp->X_op_symbol = (symbolS *) 0;
4426 }
4427
4c63da97 4428#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
45288df1 4429 if (exp->X_op != O_constant
45288df1 4430 && OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 4431 && exp_seg != absolute_section
45288df1
AM		 4432 && exp_seg != text_section
4433 && exp_seg != data_section
4434 && exp_seg != bss_section
31312f95 4435 && exp_seg != undefined_section
f86103b7 4436 && !bfd_is_com_section (exp_seg))
24eab124 4437 {
d0b47220 4438 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
24eab124
AM		 4439 return 0;
4440 }
252b5132 4441#endif
3956db08
JB		 4442
4443 if (!(i.types[this_operand] & ~Disp))
4444 i.types[this_operand] &= types;
4445
252b5132
RH		 4446 return 1;
4447}
4448
e5cb08ac 4449static int i386_index_check PARAMS ((const char *));
252b5132 4450
eecb386c 4451/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 4452 Return 1 on success, 0 on a failure. */
4453
252b5132 4454static int
eecb386c
AM		 4455i386_index_check (operand_string)
4456 const char *operand_string;
252b5132 4457{
3e73aa7c 4458 int ok;
24eab124 4459#if INFER_ADDR_PREFIX
eecb386c
AM		 4460 int fudged = 0;
4461
24eab124
AM		 4462 tryprefix:
4463#endif
3e73aa7c 4464 ok = 1;
30123838
JB		 4465 if ((current_templates->start->cpu_flags & CpuSVME)
4466 && current_templates->end[-1].operand_types[0] == AnyMem)
4467 {
4468 /* Memory operands of SVME insns are special in that they only allow
4469 rAX as their memory address and ignore any segment override. */
4470 unsigned RegXX;
4471
4472 /* SKINIT is even more restrictive: it always requires EAX. */
4473 if (strcmp (current_templates->start->name, "skinit") == 0)
4474 RegXX = Reg32;
4475 else if (flag_code == CODE_64BIT)
4476 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4477 else
64e74474
AM		 4478 RegXX = ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
4479 ? Reg16
4480 : Reg32);
30123838
JB		 4481 if (!i.base_reg
4482 || !(i.base_reg->reg_type & Acc)
4483 || !(i.base_reg->reg_type & RegXX)
4484 || i.index_reg
4485 || (i.types[0] & Disp))
4486 ok = 0;
4487 }
4488 else if (flag_code == CODE_64BIT)
64e74474
AM		 4489 {
4490 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4491
4492 if ((i.base_reg
4493 && ((i.base_reg->reg_type & RegXX) == 0)
4494 && (i.base_reg->reg_type != BaseIndex
4495 || i.index_reg))
4496 || (i.index_reg
4497 && ((i.index_reg->reg_type & (RegXX | BaseIndex))
4498 != (RegXX | BaseIndex))))
4499 ok = 0;
3e73aa7c
JH		 4500 }
4501 else
4502 {
4503 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
4504 {
4505 /* 16bit checks. */
4506 if ((i.base_reg
29b0f896
AM		 4507 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
4508 != (Reg16 | BaseIndex)))
3e73aa7c 4509 || (i.index_reg
29b0f896
AM		 4510 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
4511 != (Reg16 | BaseIndex))
4512 || !(i.base_reg
4513 && i.base_reg->reg_num < 6
4514 && i.index_reg->reg_num >= 6
4515 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 4516 ok = 0;
4517 }
4518 else
e5cb08ac 4519 {
3e73aa7c
JH		 4520 /* 32bit checks. */
4521 if ((i.base_reg
4522 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4523 || (i.index_reg
29b0f896
AM		 4524 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4525 != (Reg32 | BaseIndex))))
e5cb08ac 4526 ok = 0;
3e73aa7c
JH		 4527 }
4528 }
4529 if (!ok)
24eab124
AM		 4530 {
4531#if INFER_ADDR_PREFIX
20f0a1fc 4532 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 4533 {
4534 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4535 i.prefixes += 1;
b23bac36
AM		 4536 /* Change the size of any displacement too. At most one of
4537 Disp16 or Disp32 is set.
4538 FIXME. There doesn't seem to be any real need for separate
4539 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 4540 Removing them would probably clean up the code quite a lot. */
20f0a1fc 4541 if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp16 | Disp32)))
64e74474 4542 i.types[this_operand] ^= (Disp16 | Disp32);
eecb386c 4543 fudged = 1;
24eab124
AM		 4544 goto tryprefix;
4545 }
eecb386c
AM		 4546 if (fudged)
4547 as_bad (_("`%s' is not a valid base/index expression"),
4548 operand_string);
4549 else
c388dee8 4550#endif
eecb386c
AM		 4551 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4552 operand_string,
3e73aa7c 4553 flag_code_names[flag_code]);
24eab124 4554 }
20f0a1fc 4555 return ok;
24eab124 4556}
252b5132 4557
252b5132 4558/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 4559 on error. */
252b5132 4560
252b5132
RH		 4561static int
4562i386_operand (operand_string)
4563 char *operand_string;
4564{
af6bdddf
AM		 4565 const reg_entry *r;
4566 char *end_op;
24eab124 4567 char *op_string = operand_string;
252b5132 4568
24eab124 4569 if (is_space_char (*op_string))
252b5132
RH		 4570 ++op_string;
4571
24eab124 4572 /* We check for an absolute prefix (differentiating,
47926f60 4573 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 4574 if (*op_string == ABSOLUTE_PREFIX)
4575 {
4576 ++op_string;
4577 if (is_space_char (*op_string))
4578 ++op_string;
4579 i.types[this_operand] |= JumpAbsolute;
4580 }
252b5132 4581
47926f60 4582 /* Check if operand is a register. */
4d1bb795 4583 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 4584 {
24eab124
AM		 4585 /* Check for a segment override by searching for ':' after a
4586 segment register. */
4587 op_string = end_op;
4588 if (is_space_char (*op_string))
4589 ++op_string;
4590 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4591 {
4592 switch (r->reg_num)
4593 {
4594 case 0:
4595 i.seg[i.mem_operands] = &es;
4596 break;
4597 case 1:
4598 i.seg[i.mem_operands] = &cs;
4599 break;
4600 case 2:
4601 i.seg[i.mem_operands] = &ss;
4602 break;
4603 case 3:
4604 i.seg[i.mem_operands] = &ds;
4605 break;
4606 case 4:
4607 i.seg[i.mem_operands] = &fs;
4608 break;
4609 case 5:
4610 i.seg[i.mem_operands] = &gs;
4611 break;
4612 }
252b5132 4613
24eab124 4614 /* Skip the ':' and whitespace. */
252b5132
RH		 4615 ++op_string;
4616 if (is_space_char (*op_string))
24eab124 4617 ++op_string;
252b5132 4618
24eab124
AM		 4619 if (!is_digit_char (*op_string)
4620 && !is_identifier_char (*op_string)
4621 && *op_string != '('
4622 && *op_string != ABSOLUTE_PREFIX)
4623 {
4624 as_bad (_("bad memory operand `%s'"), op_string);
4625 return 0;
4626 }
47926f60 4627 /* Handle case of %es:*foo. */
24eab124
AM		 4628 if (*op_string == ABSOLUTE_PREFIX)
4629 {
4630 ++op_string;
4631 if (is_space_char (*op_string))
4632 ++op_string;
4633 i.types[this_operand] |= JumpAbsolute;
4634 }
4635 goto do_memory_reference;
4636 }
4637 if (*op_string)
4638 {
d0b47220 4639 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 4640 return 0;
4641 }
4642 i.types[this_operand] |= r->reg_type & ~BaseIndex;
520dc8e8 4643 i.op[this_operand].regs = r;
24eab124
AM		 4644 i.reg_operands++;
4645 }
af6bdddf
AM		 4646 else if (*op_string == REGISTER_PREFIX)
4647 {
4648 as_bad (_("bad register name `%s'"), op_string);
4649 return 0;
4650 }
24eab124 4651 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 4652 {
24eab124
AM		 4653 ++op_string;
4654 if (i.types[this_operand] & JumpAbsolute)
4655 {
d0b47220 4656 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 4657 return 0;
4658 }
4659 if (!i386_immediate (op_string))
4660 return 0;
4661 }
4662 else if (is_digit_char (*op_string)
4663 || is_identifier_char (*op_string)
e5cb08ac 4664 || *op_string == '(')
24eab124 4665 {
47926f60 4666 /* This is a memory reference of some sort. */
af6bdddf 4667 char *base_string;
252b5132 4668
47926f60 4669 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 4670 char *displacement_string_start;
4671 char *displacement_string_end;
252b5132 4672
24eab124 4673 do_memory_reference:
24eab124
AM		 4674 if ((i.mem_operands == 1
4675 && (current_templates->start->opcode_modifier & IsString) == 0)
4676 || i.mem_operands == 2)
4677 {
4678 as_bad (_("too many memory references for `%s'"),
4679 current_templates->start->name);
4680 return 0;
4681 }
252b5132 4682
24eab124
AM		 4683 /* Check for base index form. We detect the base index form by
4684 looking for an ')' at the end of the operand, searching
4685 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4686 after the '('. */
af6bdddf 4687 base_string = op_string + strlen (op_string);
c3332e24 4688
af6bdddf
AM		 4689 --base_string;
4690 if (is_space_char (*base_string))
4691 --base_string;
252b5132 4692
47926f60 4693 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 4694 displacement_string_start = op_string;
4695 displacement_string_end = base_string + 1;
252b5132 4696
24eab124
AM		 4697 if (*base_string == ')')
4698 {
af6bdddf 4699 char *temp_string;
24eab124
AM		 4700 unsigned int parens_balanced = 1;
4701 /* We've already checked that the number of left & right ()'s are
47926f60 4702 equal, so this loop will not be infinite. */
24eab124
AM		 4703 do
4704 {
4705 base_string--;
4706 if (*base_string == ')')
4707 parens_balanced++;
4708 if (*base_string == '(')
4709 parens_balanced--;
4710 }
4711 while (parens_balanced);
c3332e24 4712
af6bdddf 4713 temp_string = base_string;
c3332e24 4714
24eab124 4715 /* Skip past '(' and whitespace. */
252b5132
RH		 4716 ++base_string;
4717 if (is_space_char (*base_string))
24eab124 4718 ++base_string;
252b5132 4719
af6bdddf 4720 if (*base_string == ','
4d1bb795 4721 || ((i.base_reg = parse_register (base_string, &end_op)) != NULL))
252b5132 4722 {
af6bdddf 4723 displacement_string_end = temp_string;
252b5132 4724
af6bdddf 4725 i.types[this_operand] |= BaseIndex;
252b5132 4726
af6bdddf 4727 if (i.base_reg)
24eab124 4728 {
24eab124
AM		 4729 base_string = end_op;
4730 if (is_space_char (*base_string))
4731 ++base_string;
af6bdddf
AM		 4732 }
4733
4734 /* There may be an index reg or scale factor here. */
4735 if (*base_string == ',')
4736 {
4737 ++base_string;
4738 if (is_space_char (*base_string))
4739 ++base_string;
4740
4d1bb795 4741 if ((i.index_reg = parse_register (base_string, &end_op)) != NULL)
24eab124 4742 {
af6bdddf 4743 base_string = end_op;
24eab124
AM		 4744 if (is_space_char (*base_string))
4745 ++base_string;
af6bdddf
AM		 4746 if (*base_string == ',')
4747 {
4748 ++base_string;
4749 if (is_space_char (*base_string))
4750 ++base_string;
4751 }
e5cb08ac 4752 else if (*base_string != ')')
af6bdddf
AM		 4753 {
4754 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4755 operand_string);
4756 return 0;
4757 }
24eab124 4758 }
af6bdddf 4759 else if (*base_string == REGISTER_PREFIX)
24eab124 4760 {
af6bdddf 4761 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 4762 return 0;
4763 }
252b5132 4764
47926f60 4765 /* Check for scale factor. */
551c1ca1 4766 if (*base_string != ')')
af6bdddf 4767 {
551c1ca1
AM		 4768 char *end_scale = i386_scale (base_string);
4769
4770 if (!end_scale)
af6bdddf 4771 return 0;
24eab124 4772
551c1ca1 4773 base_string = end_scale;
af6bdddf
AM		 4774 if (is_space_char (*base_string))
4775 ++base_string;
4776 if (*base_string != ')')
4777 {
4778 as_bad (_("expecting `)' after scale factor in `%s'"),
4779 operand_string);
4780 return 0;
4781 }
4782 }
4783 else if (!i.index_reg)
24eab124 4784 {
af6bdddf
AM		 4785 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4786 *base_string);
24eab124
AM		 4787 return 0;
4788 }
4789 }
af6bdddf 4790 else if (*base_string != ')')
24eab124 4791 {
af6bdddf
AM		 4792 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4793 operand_string);
24eab124
AM		 4794 return 0;
4795 }
c3332e24 4796 }
af6bdddf 4797 else if (*base_string == REGISTER_PREFIX)
c3332e24 4798 {
af6bdddf 4799 as_bad (_("bad register name `%s'"), base_string);
24eab124 4800 return 0;
c3332e24 4801 }
24eab124
AM		 4802 }
4803
4804 /* If there's an expression beginning the operand, parse it,
4805 assuming displacement_string_start and
4806 displacement_string_end are meaningful. */
4807 if (displacement_string_start != displacement_string_end)
4808 {
4809 if (!i386_displacement (displacement_string_start,
4810 displacement_string_end))
4811 return 0;
4812 }
4813
4814 /* Special case for (%dx) while doing input/output op. */
4815 if (i.base_reg
4816 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4817 && i.index_reg == 0
4818 && i.log2_scale_factor == 0
4819 && i.seg[i.mem_operands] == 0
4820 && (i.types[this_operand] & Disp) == 0)
4821 {
4822 i.types[this_operand] = InOutPortReg;
4823 return 1;
4824 }
4825
eecb386c
AM		 4826 if (i386_index_check (operand_string) == 0)
4827 return 0;
24eab124
AM		 4828 i.mem_operands++;
4829 }
4830 else
ce8a8b2f
AM		 4831 {
4832 /* It's not a memory operand; argh! */
24eab124
AM		 4833 as_bad (_("invalid char %s beginning operand %d `%s'"),
4834 output_invalid (*op_string),
4835 this_operand + 1,
4836 op_string);
4837 return 0;
4838 }
47926f60 4839 return 1; /* Normal return. */
252b5132
RH		 4840}
4841\f
ee7fcc42
AM		 4842/* md_estimate_size_before_relax()
4843
4844 Called just before relax() for rs_machine_dependent frags. The x86
4845 assembler uses these frags to handle variable size jump
4846 instructions.
4847
4848 Any symbol that is now undefined will not become defined.
4849 Return the correct fr_subtype in the frag.
4850 Return the initial "guess for variable size of frag" to caller.
4851 The guess is actually the growth beyond the fixed part. Whatever
4852 we do to grow the fixed or variable part contributes to our
4853 returned value. */
4854
252b5132
RH		 4855int
4856md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 4857 fragS *fragP;
4858 segT segment;
252b5132 4859{
252b5132 4860 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 4861 check for un-relaxable symbols. On an ELF system, we can't relax
4862 an externally visible symbol, because it may be overridden by a
4863 shared library. */
4864 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 4865#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 4866 || (IS_ELF
31312f95
AM		 4867 && (S_IS_EXTERNAL (fragP->fr_symbol)
4868 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 4869#endif
4870 )
252b5132 4871 {
b98ef147
AM		 4872 /* Symbol is undefined in this segment, or we need to keep a
4873 reloc so that weak symbols can be overridden. */
4874 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 4875 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 4876 unsigned char *opcode;
4877 int old_fr_fix;
f6af82bd 4878
ee7fcc42
AM		 4879 if (fragP->fr_var != NO_RELOC)
4880 reloc_type = fragP->fr_var;
b98ef147 4881 else if (size == 2)
f6af82bd
AM		 4882 reloc_type = BFD_RELOC_16_PCREL;
4883 else
4884 reloc_type = BFD_RELOC_32_PCREL;
252b5132 4885
ee7fcc42
AM		 4886 old_fr_fix = fragP->fr_fix;
4887 opcode = (unsigned char *) fragP->fr_opcode;
4888
fddf5b5b 4889 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 4890 {
fddf5b5b
AM		 4891 case UNCOND_JUMP:
4892 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 4893 opcode[0] = 0xe9;
252b5132 4894 fragP->fr_fix += size;
062cd5e7
AS		 4895 fix_new (fragP, old_fr_fix, size,
4896 fragP->fr_symbol,
4897 fragP->fr_offset, 1,
4898 reloc_type);
252b5132
RH		 4899 break;
4900
fddf5b5b 4901 case COND_JUMP86:
412167cb
AM		 4902 if (size == 2
4903 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 4904 {
4905 /* Negate the condition, and branch past an
4906 unconditional jump. */
4907 opcode[0] ^= 1;
4908 opcode[1] = 3;
4909 /* Insert an unconditional jump. */
4910 opcode[2] = 0xe9;
4911 /* We added two extra opcode bytes, and have a two byte
4912 offset. */
4913 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 4914 fix_new (fragP, old_fr_fix + 2, 2,
4915 fragP->fr_symbol,
4916 fragP->fr_offset, 1,
4917 reloc_type);
fddf5b5b
AM		 4918 break;
4919 }
4920 /* Fall through. */
4921
4922 case COND_JUMP:
412167cb
AM		 4923 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4924 {
3e02c1cc
AM		 4925 fixS *fixP;
4926
412167cb 4927 fragP->fr_fix += 1;
3e02c1cc
AM		 4928 fixP = fix_new (fragP, old_fr_fix, 1,
4929 fragP->fr_symbol,
4930 fragP->fr_offset, 1,
4931 BFD_RELOC_8_PCREL);
4932 fixP->fx_signed = 1;
412167cb
AM		 4933 break;
4934 }
93c2a809 4935
24eab124 4936 /* This changes the byte-displacement jump 0x7N
fddf5b5b 4937 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 4938 opcode[1] = opcode[0] + 0x10;
f6af82bd 4939 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 4940 /* We've added an opcode byte. */
4941 fragP->fr_fix += 1 + size;
062cd5e7
AS		 4942 fix_new (fragP, old_fr_fix + 1, size,
4943 fragP->fr_symbol,
4944 fragP->fr_offset, 1,
4945 reloc_type);
252b5132 4946 break;
fddf5b5b
AM		 4947
4948 default:
4949 BAD_CASE (fragP->fr_subtype);
4950 break;
252b5132
RH		 4951 }
4952 frag_wane (fragP);
ee7fcc42 4953 return fragP->fr_fix - old_fr_fix;
252b5132 4954 }
93c2a809 4955
93c2a809
AM		 4956 /* Guess size depending on current relax state. Initially the relax
4957 state will correspond to a short jump and we return 1, because
4958 the variable part of the frag (the branch offset) is one byte
4959 long. However, we can relax a section more than once and in that
4960 case we must either set fr_subtype back to the unrelaxed state,
4961 or return the value for the appropriate branch. */
4962 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 4963}
4964
47926f60
KH		 4965/* Called after relax() is finished.
4966
4967 In: Address of frag.
4968 fr_type == rs_machine_dependent.
4969 fr_subtype is what the address relaxed to.
4970
4971 Out: Any fixSs and constants are set up.
4972 Caller will turn frag into a ".space 0". */
4973
252b5132
RH		 4974void
4975md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 4976 bfd *abfd ATTRIBUTE_UNUSED;
4977 segT sec ATTRIBUTE_UNUSED;
29b0f896 4978 fragS *fragP;
252b5132 4979{
29b0f896 4980 unsigned char *opcode;
252b5132 4981 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 4982 offsetT target_address;
4983 offsetT opcode_address;
252b5132 4984 unsigned int extension = 0;
847f7ad4 4985 offsetT displacement_from_opcode_start;
252b5132
RH		 4986
4987 opcode = (unsigned char *) fragP->fr_opcode;
4988
47926f60 4989 /* Address we want to reach in file space. */
252b5132 4990 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 4991
47926f60 4992 /* Address opcode resides at in file space. */
252b5132
RH		 4993 opcode_address = fragP->fr_address + fragP->fr_fix;
4994
47926f60 4995 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 4996 displacement_from_opcode_start = target_address - opcode_address;
4997
fddf5b5b 4998 if ((fragP->fr_subtype & BIG) == 0)
252b5132 4999 {
47926f60
KH		 5000 /* Don't have to change opcode. */
5001 extension = 1; /* 1 opcode + 1 displacement */
252b5132 5002 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 5003 }
5004 else
5005 {
5006 if (no_cond_jump_promotion
5007 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
5008 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
252b5132 5009
fddf5b5b
AM		 5010 switch (fragP->fr_subtype)
5011 {
5012 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
5013 extension = 4; /* 1 opcode + 4 displacement */
5014 opcode[0] = 0xe9;
5015 where_to_put_displacement = &opcode[1];
5016 break;
252b5132 5017
fddf5b5b
AM		 5018 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
5019 extension = 2; /* 1 opcode + 2 displacement */
5020 opcode[0] = 0xe9;
5021 where_to_put_displacement = &opcode[1];
5022 break;
252b5132 5023
fddf5b5b
AM		 5024 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
5025 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
5026 extension = 5; /* 2 opcode + 4 displacement */
5027 opcode[1] = opcode[0] + 0x10;
5028 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5029 where_to_put_displacement = &opcode[2];
5030 break;
252b5132 5031
fddf5b5b
AM		 5032 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
5033 extension = 3; /* 2 opcode + 2 displacement */
5034 opcode[1] = opcode[0] + 0x10;
5035 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
5036 where_to_put_displacement = &opcode[2];
5037 break;
252b5132 5038
fddf5b5b
AM		 5039 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
5040 extension = 4;
5041 opcode[0] ^= 1;
5042 opcode[1] = 3;
5043 opcode[2] = 0xe9;
5044 where_to_put_displacement = &opcode[3];
5045 break;
5046
5047 default:
5048 BAD_CASE (fragP->fr_subtype);
5049 break;
5050 }
252b5132 5051 }
fddf5b5b 5052
7b81dfbb
AJ		 5053 /* If size if less then four we are sure that the operand fits,
5054 but if it's 4, then it could be that the displacement is larger
5055 then -/+ 2GB. */
5056 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
5057 && object_64bit
5058 && ((addressT) (displacement_from_opcode_start - extension
5059 + ((addressT) 1 << 31))
5060 > (((addressT) 2 << 31) - 1)))
5061 {
5062 as_bad_where (fragP->fr_file, fragP->fr_line,
5063 _("jump target out of range"));
5064 /* Make us emit 0. */
5065 displacement_from_opcode_start = extension;
5066 }
47926f60 5067 /* Now put displacement after opcode. */
252b5132
RH		 5068 md_number_to_chars ((char *) where_to_put_displacement,
5069 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 5070 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 5071 fragP->fr_fix += extension;
5072}
5073\f
47926f60
KH		 5074/* Size of byte displacement jmp. */
5075int md_short_jump_size = 2;
5076
5077/* Size of dword displacement jmp. */
5078int md_long_jump_size = 5;
252b5132 5079
252b5132
RH		 5080void
5081md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
5082 char *ptr;
5083 addressT from_addr, to_addr;
ab9da554
ILT		 5084 fragS *frag ATTRIBUTE_UNUSED;
5085 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5086{
847f7ad4 5087 offsetT offset;
252b5132
RH		 5088
5089 offset = to_addr - (from_addr + 2);
47926f60
KH		 5090 /* Opcode for byte-disp jump. */
5091 md_number_to_chars (ptr, (valueT) 0xeb, 1);
252b5132
RH		 5092 md_number_to_chars (ptr + 1, (valueT) offset, 1);
5093}
5094
5095void
5096md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
5097 char *ptr;
5098 addressT from_addr, to_addr;
a38cf1db
AM		 5099 fragS *frag ATTRIBUTE_UNUSED;
5100 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132 5101{
847f7ad4 5102 offsetT offset;
252b5132 5103
a38cf1db
AM		 5104 offset = to_addr - (from_addr + 5);
5105 md_number_to_chars (ptr, (valueT) 0xe9, 1);
5106 md_number_to_chars (ptr + 1, (valueT) offset, 4);
252b5132
RH		 5107}
5108\f
5109/* Apply a fixup (fixS) to segment data, once it has been determined
5110 by our caller that we have all the info we need to fix it up.
5111
5112 On the 386, immediates, displacements, and data pointers are all in
5113 the same (little-endian) format, so we don't need to care about which
5114 we are handling. */
5115
94f592af 5116void
55cf6793 5117md_apply_fix (fixP, valP, seg)
47926f60
KH		 5118 /* The fix we're to put in. */
5119 fixS *fixP;
47926f60 5120 /* Pointer to the value of the bits. */
c6682705 5121 valueT *valP;
47926f60
KH		 5122 /* Segment fix is from. */
5123 segT seg ATTRIBUTE_UNUSED;
252b5132 5124{
94f592af 5125 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 5126 valueT value = *valP;
252b5132 5127
f86103b7 5128#if !defined (TE_Mach)
93382f6d
AM		 5129 if (fixP->fx_pcrel)
5130 {
5131 switch (fixP->fx_r_type)
5132 {
5865bb77
ILT		 5133 default:
5134 break;
5135
d6ab8113
JB		 5136 case BFD_RELOC_64:
5137 fixP->fx_r_type = BFD_RELOC_64_PCREL;
5138 break;
93382f6d 5139 case BFD_RELOC_32:
ae8887b5 5140 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 5141 fixP->fx_r_type = BFD_RELOC_32_PCREL;
5142 break;
5143 case BFD_RELOC_16:
5144 fixP->fx_r_type = BFD_RELOC_16_PCREL;
5145 break;
5146 case BFD_RELOC_8:
5147 fixP->fx_r_type = BFD_RELOC_8_PCREL;
5148 break;
5149 }
5150 }
252b5132 5151
a161fe53 5152 if (fixP->fx_addsy != NULL
31312f95 5153 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 5154 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 5155 || fixP->fx_r_type == BFD_RELOC_16_PCREL
5156 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
5157 && !use_rela_relocations)
252b5132 5158 {
31312f95
AM		 5159 /* This is a hack. There should be a better way to handle this.
5160 This covers for the fact that bfd_install_relocation will
5161 subtract the current location (for partial_inplace, PC relative
5162 relocations); see more below. */
252b5132 5163#ifndef OBJ_AOUT
718ddfc0 5164 if (IS_ELF
252b5132
RH		 5165#ifdef TE_PE
5166 || OUTPUT_FLAVOR == bfd_target_coff_flavour
5167#endif
5168 )
5169 value += fixP->fx_where + fixP->fx_frag->fr_address;
5170#endif
5171#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5172 if (IS_ELF)
252b5132 5173 {
6539b54b 5174 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 5175
6539b54b 5176 if ((sym_seg == seg
2f66722d 5177 || (symbol_section_p (fixP->fx_addsy)
6539b54b 5178 && sym_seg != absolute_section))
ae6063d4 5179 && !generic_force_reloc (fixP))
2f66722d
AM		 5180 {
5181 /* Yes, we add the values in twice. This is because
6539b54b
AM		 5182 bfd_install_relocation subtracts them out again. I think
5183 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 5184 it. FIXME. */
5185 value += fixP->fx_where + fixP->fx_frag->fr_address;
5186 }
252b5132
RH		 5187 }
5188#endif
5189#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 5190 /* For some reason, the PE format does not store a
5191 section address offset for a PC relative symbol. */
5192 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 5193 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 5194 value += md_pcrel_from (fixP);
5195#endif
5196 }
5197
5198 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 5199 and we must not disappoint it. */
252b5132 5200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 5201 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 5202 switch (fixP->fx_r_type)
5203 {
5204 case BFD_RELOC_386_PLT32:
3e73aa7c 5205 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 5206 /* Make the jump instruction point to the address of the operand. At
5207 runtime we merely add the offset to the actual PLT entry. */
5208 value = -4;
5209 break;
31312f95 5210
13ae64f3
JJ		 5211 case BFD_RELOC_386_TLS_GD:
5212 case BFD_RELOC_386_TLS_LDM:
13ae64f3 5213 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5214 case BFD_RELOC_386_TLS_IE:
5215 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 5216 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 5217 case BFD_RELOC_X86_64_TLSGD:
5218 case BFD_RELOC_X86_64_TLSLD:
5219 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 5220 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 5221 value = 0; /* Fully resolved at runtime. No addend. */
5222 /* Fallthrough */
5223 case BFD_RELOC_386_TLS_LE:
5224 case BFD_RELOC_386_TLS_LDO_32:
5225 case BFD_RELOC_386_TLS_LE_32:
5226 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5227 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 5228 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 5229 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 5230 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5231 break;
5232
67a4f2b7
AO		 5233 case BFD_RELOC_386_TLS_DESC_CALL:
5234 case BFD_RELOC_X86_64_TLSDESC_CALL:
5235 value = 0; /* Fully resolved at runtime. No addend. */
5236 S_SET_THREAD_LOCAL (fixP->fx_addsy);
5237 fixP->fx_done = 0;
5238 return;
5239
00f7efb6
JJ		 5240 case BFD_RELOC_386_GOT32:
5241 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 5242 value = 0; /* Fully resolved at runtime. No addend. */
5243 break;
47926f60
KH		 5244
5245 case BFD_RELOC_VTABLE_INHERIT:
5246 case BFD_RELOC_VTABLE_ENTRY:
5247 fixP->fx_done = 0;
94f592af 5248 return;
47926f60
KH		 5249
5250 default:
5251 break;
5252 }
5253#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 5254 *valP = value;
f86103b7 5255#endif /* !defined (TE_Mach) */
3e73aa7c 5256
3e73aa7c 5257 /* Are we finished with this relocation now? */
c6682705 5258 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 5259 fixP->fx_done = 1;
5260 else if (use_rela_relocations)
5261 {
5262 fixP->fx_no_overflow = 1;
062cd5e7
AS		 5263 /* Remember value for tc_gen_reloc. */
5264 fixP->fx_addnumber = value;
3e73aa7c
JH		 5265 value = 0;
5266 }
f86103b7 5267
94f592af 5268 md_number_to_chars (p, value, fixP->fx_size);
252b5132 5269}
252b5132 5270\f
252b5132
RH		 5271#define MAX_LITTLENUMS 6
5272
47926f60
KH		 5273/* Turn the string pointed to by litP into a floating point constant
5274 of type TYPE, and emit the appropriate bytes. The number of
5275 LITTLENUMS emitted is stored in *SIZEP. An error message is
5276 returned, or NULL on OK. */
5277
252b5132
RH		 5278char *
5279md_atof (type, litP, sizeP)
2ab9b79e 5280 int type;
252b5132
RH		 5281 char *litP;
5282 int *sizeP;
5283{
5284 int prec;
5285 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5286 LITTLENUM_TYPE *wordP;
5287 char *t;
5288
5289 switch (type)
5290 {
5291 case 'f':
5292 case 'F':
5293 prec = 2;
5294 break;
5295
5296 case 'd':
5297 case 'D':
5298 prec = 4;
5299 break;
5300
5301 case 'x':
5302 case 'X':
5303 prec = 5;
5304 break;
5305
5306 default:
5307 *sizeP = 0;
5308 return _("Bad call to md_atof ()");
5309 }
5310 t = atof_ieee (input_line_pointer, type, words);
5311 if (t)
5312 input_line_pointer = t;
5313
5314 *sizeP = prec * sizeof (LITTLENUM_TYPE);
5315 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
5316 the bigendian 386. */
5317 for (wordP = words + prec - 1; prec--;)
5318 {
5319 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
5320 litP += sizeof (LITTLENUM_TYPE);
5321 }
5322 return 0;
5323}
5324\f
2d545b82 5325static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 5326
252b5132
RH		 5327static char *
5328output_invalid (c)
5329 int c;
5330{
3882b010 5331 if (ISPRINT (c))
f9f21a03
L		 5332 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
5333 "'%c'", c);
252b5132 5334 else
f9f21a03 5335 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 5336 "(0x%x)", (unsigned char) c);
252b5132
RH		 5337 return output_invalid_buf;
5338}
5339
af6bdddf 5340/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 5341
5342static const reg_entry *
4d1bb795 5343parse_real_register (char *reg_string, char **end_op)
252b5132 5344{
af6bdddf
AM		 5345 char *s = reg_string;
5346 char *p;
252b5132
RH		 5347 char reg_name_given[MAX_REG_NAME_SIZE + 1];
5348 const reg_entry *r;
5349
5350 /* Skip possible REGISTER_PREFIX and possible whitespace. */
5351 if (*s == REGISTER_PREFIX)
5352 ++s;
5353
5354 if (is_space_char (*s))
5355 ++s;
5356
5357 p = reg_name_given;
af6bdddf 5358 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 5359 {
5360 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 5361 return (const reg_entry *) NULL;
5362 s++;
252b5132
RH		 5363 }
5364
6588847e
DN		 5365 /* For naked regs, make sure that we are not dealing with an identifier.
5366 This prevents confusing an identifier like `eax_var' with register
5367 `eax'. */
5368 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
5369 return (const reg_entry *) NULL;
5370
af6bdddf 5371 *end_op = s;
252b5132
RH		 5372
5373 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
5374
5f47d35b 5375 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 5376 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 5377 {
5f47d35b
AM		 5378 if (is_space_char (*s))
5379 ++s;
5380 if (*s == '(')
5381 {
af6bdddf 5382 ++s;
5f47d35b
AM		 5383 if (is_space_char (*s))
5384 ++s;
5385 if (*s >= '0' && *s <= '7')
5386 {
5387 r = &i386_float_regtab[*s - '0'];
af6bdddf 5388 ++s;
5f47d35b
AM		 5389 if (is_space_char (*s))
5390 ++s;
5391 if (*s == ')')
5392 {
5393 *end_op = s + 1;
5394 return r;
5395 }
5f47d35b 5396 }
47926f60 5397 /* We have "%st(" then garbage. */
5f47d35b
AM		 5398 return (const reg_entry *) NULL;
5399 }
5400 }
5401
1ae00879 5402 if (r != NULL
20f0a1fc 5403 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
c4a530c5 5404 && (r->reg_type != Control || !(cpu_arch_flags & CpuSledgehammer))
1ae00879 5405 && flag_code != CODE_64BIT)
20f0a1fc 5406 return (const reg_entry *) NULL;
1ae00879 5407
252b5132
RH		 5408 return r;
5409}
4d1bb795
JB		 5410
5411/* REG_STRING starts *before* REGISTER_PREFIX. */
5412
5413static const reg_entry *
5414parse_register (char *reg_string, char **end_op)
5415{
5416 const reg_entry *r;
5417
5418 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
5419 r = parse_real_register (reg_string, end_op);
5420 else
5421 r = NULL;
5422 if (!r)
5423 {
5424 char *save = input_line_pointer;
5425 char c;
5426 symbolS *symbolP;
5427
5428 input_line_pointer = reg_string;
5429 c = get_symbol_end ();
5430 symbolP = symbol_find (reg_string);
5431 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
5432 {
5433 const expressionS *e = symbol_get_value_expression (symbolP);
5434
5435 know (e->X_op == O_register);
5436 know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab));
5437 r = i386_regtab + e->X_add_number;
5438 *end_op = input_line_pointer;
5439 }
5440 *input_line_pointer = c;
5441 input_line_pointer = save;
5442 }
5443 return r;
5444}
5445
5446int
5447i386_parse_name (char *name, expressionS *e, char *nextcharP)
5448{
5449 const reg_entry *r;
5450 char *end = input_line_pointer;
5451
5452 *end = *nextcharP;
5453 r = parse_register (name, &input_line_pointer);
5454 if (r && end <= input_line_pointer)
5455 {
5456 *nextcharP = *input_line_pointer;
5457 *input_line_pointer = 0;
5458 e->X_op = O_register;
5459 e->X_add_number = r - i386_regtab;
5460 return 1;
5461 }
5462 input_line_pointer = end;
5463 *end = 0;
5464 return 0;
5465}
5466
5467void
5468md_operand (expressionS *e)
5469{
5470 if (*input_line_pointer == REGISTER_PREFIX)
5471 {
5472 char *end;
5473 const reg_entry *r = parse_real_register (input_line_pointer, &end);
5474
5475 if (r)
5476 {
5477 e->X_op = O_register;
5478 e->X_add_number = r - i386_regtab;
5479 input_line_pointer = end;
5480 }
5481 }
5482}
5483
252b5132 5484\f
4cc782b5 5485#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 5486const char *md_shortopts = "kVQ:sqn";
252b5132 5487#else
12b55ccc 5488const char *md_shortopts = "qn";
252b5132 5489#endif
6e0b89ee 5490
3e73aa7c 5491#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 5492#define OPTION_64 (OPTION_MD_BASE + 1)
5493#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 5494#define OPTION_MARCH (OPTION_MD_BASE + 3)
5495#define OPTION_MTUNE (OPTION_MD_BASE + 4)
b3b91714
AM		 5496
5497struct option md_longopts[] = {
3e73aa7c 5498 {"32", no_argument, NULL, OPTION_32},
6e0b89ee 5499#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
3e73aa7c 5500 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 5501#endif
b3b91714 5502 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 5503 {"march", required_argument, NULL, OPTION_MARCH},
5504 {"mtune", required_argument, NULL, OPTION_MTUNE},
252b5132
RH		 5505 {NULL, no_argument, NULL, 0}
5506};
5507size_t md_longopts_size = sizeof (md_longopts);
5508
5509int
9103f4f4 5510md_parse_option (int c, char *arg)
252b5132 5511{
9103f4f4
L		 5512 unsigned int i;
5513
252b5132
RH		 5514 switch (c)
5515 {
12b55ccc
L		 5516 case 'n':
5517 optimize_align_code = 0;
5518 break;
5519
a38cf1db
AM		 5520 case 'q':
5521 quiet_warnings = 1;
252b5132
RH		 5522 break;
5523
5524#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 5525 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
5526 should be emitted or not. FIXME: Not implemented. */
5527 case 'Q':
252b5132
RH		 5528 break;
5529
5530 /* -V: SVR4 argument to print version ID. */
5531 case 'V':
5532 print_version_id ();
5533 break;
5534
a38cf1db
AM		 5535 /* -k: Ignore for FreeBSD compatibility. */
5536 case 'k':
252b5132 5537 break;
4cc782b5
ILT		 5538
5539 case 's':
5540 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 5541 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 5542 break;
6e0b89ee 5543
3e73aa7c
JH		 5544 case OPTION_64:
5545 {
5546 const char **list, **l;
5547
3e73aa7c
JH		 5548 list = bfd_target_list ();
5549 for (l = list; *l != NULL; l++)
6e0b89ee
AM		 5550 if (strcmp (*l, "elf64-x86-64") == 0)
5551 {
5552 default_arch = "x86_64";
5553 break;
5554 }
3e73aa7c 5555 if (*l == NULL)
6e0b89ee 5556 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 5557 free (list);
5558 }
5559 break;
5560#endif
252b5132 5561
6e0b89ee
AM		 5562 case OPTION_32:
5563 default_arch = "i386";
5564 break;
5565
b3b91714
AM		 5566 case OPTION_DIVIDE:
5567#ifdef SVR4_COMMENT_CHARS
5568 {
5569 char *n, *t;
5570 const char *s;
5571
5572 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
5573 t = n;
5574 for (s = i386_comment_chars; *s != '\0'; s++)
5575 if (*s != '/')
5576 *t++ = *s;
5577 *t = '\0';
5578 i386_comment_chars = n;
5579 }
5580#endif
5581 break;
5582
9103f4f4
L		 5583 case OPTION_MARCH:
5584 if (*arg == '.')
5585 as_fatal (_("Invalid -march= option: `%s'"), arg);
5586 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5587 {
5588 if (strcmp (arg, cpu_arch [i].name) == 0)
5589 {
5590 cpu_arch_isa_flags = cpu_arch[i].flags;
5591 break;
5592 }
5593 }
5594 if (i >= ARRAY_SIZE (cpu_arch))
5595 as_fatal (_("Invalid -march= option: `%s'"), arg);
5596 break;
5597
5598 case OPTION_MTUNE:
5599 if (*arg == '.')
5600 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5601 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
5602 {
5603 if (strcmp (arg, cpu_arch [i].name) == 0)
5604 {
5605 cpu_arch_tune = cpu_arch [i].type;
5606 cpu_arch_tune_flags = cpu_arch[i].flags;
5607 break;
5608 }
5609 }
5610 if (i >= ARRAY_SIZE (cpu_arch))
5611 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
5612 break;
5613
252b5132
RH		 5614 default:
5615 return 0;
5616 }
5617 return 1;
5618}
5619
5620void
5621md_show_usage (stream)
5622 FILE *stream;
5623{
4cc782b5
ILT		 5624#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5625 fprintf (stream, _("\
a38cf1db
AM		 5626 -Q ignored\n\
5627 -V print assembler version number\n\
b3b91714
AM		 5628 -k ignored\n"));
5629#endif
5630 fprintf (stream, _("\
12b55ccc 5631 -n Do not optimize code alignment\n\
b3b91714
AM		 5632 -q quieten some warnings\n"));
5633#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5634 fprintf (stream, _("\
a38cf1db 5635 -s ignored\n"));
b3b91714
AM		 5636#endif
5637#ifdef SVR4_COMMENT_CHARS
5638 fprintf (stream, _("\
5639 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 5640#else
5641 fprintf (stream, _("\
b3b91714 5642 --divide ignored\n"));
4cc782b5 5643#endif
9103f4f4
L		 5644 fprintf (stream, _("\
5645 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
5646 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
5647 yonah, merom, k6, athlon, k8, generic32, generic64\n"));
5648
252b5132
RH		 5649}
5650
3e73aa7c
JH		 5651#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
5652 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
252b5132
RH		 5653
5654/* Pick the target format to use. */
5655
47926f60 5656const char *
252b5132
RH		 5657i386_target_format ()
5658{
3e73aa7c 5659 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 5660 {
5661 set_code_flag (CODE_64BIT);
5662 if (cpu_arch_isa_flags == 0)
5663 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5664 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5665 |CpuSSE|CpuSSE2;
5666 if (cpu_arch_tune == PROCESSOR_UNKNOWN)
5667 {
5668 cpu_arch_tune = PROCESSOR_GENERIC64;
5669 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386|Cpu486
5670 |Cpu586|Cpu686|CpuP4|CpuMMX|CpuMMX2
5671 |CpuSSE|CpuSSE2;
5672 }
5673 }
3e73aa7c 5674 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 5675 {
5676 set_code_flag (CODE_32BIT);
5677 if (cpu_arch_isa_flags == 0)
5678 cpu_arch_isa_flags = Cpu086|Cpu186|Cpu286|Cpu386;
5679 if (cpu_arch_tune == PROCESSOR_UNKNOWN)
5680 {
5681 cpu_arch_tune = PROCESSOR_GENERIC32;
5682 cpu_arch_tune_flags = Cpu086|Cpu186|Cpu286|Cpu386;
5683 }
5684 }
3e73aa7c
JH		 5685 else
5686 as_fatal (_("Unknown architecture"));
252b5132
RH		 5687 switch (OUTPUT_FLAVOR)
5688 {
4c63da97
AM		 5689#ifdef OBJ_MAYBE_AOUT
5690 case bfd_target_aout_flavour:
47926f60 5691 return AOUT_TARGET_FORMAT;
4c63da97
AM		 5692#endif
5693#ifdef OBJ_MAYBE_COFF
252b5132
RH		 5694 case bfd_target_coff_flavour:
5695 return "coff-i386";
4c63da97 5696#endif
3e73aa7c 5697#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 5698 case bfd_target_elf_flavour:
3e73aa7c 5699 {
e5cb08ac 5700 if (flag_code == CODE_64BIT)
4fa24527
JB		 5701 {
5702 object_64bit = 1;
5703 use_rela_relocations = 1;
5704 }
4ada7262 5705 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
3e73aa7c 5706 }
4c63da97 5707#endif
252b5132
RH		 5708 default:
5709 abort ();
5710 return NULL;
5711 }
5712}
5713
47926f60 5714#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 5715
5716#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5717void i386_elf_emit_arch_note ()
5718{
718ddfc0 5719 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 5720 {
5721 char *p;
5722 asection *seg = now_seg;
5723 subsegT subseg = now_subseg;
5724 Elf_Internal_Note i_note;
5725 Elf_External_Note e_note;
5726 asection *note_secp;
5727 int len;
5728
5729 /* Create the .note section. */
5730 note_secp = subseg_new (".note", 0);
5731 bfd_set_section_flags (stdoutput,
5732 note_secp,
5733 SEC_HAS_CONTENTS | SEC_READONLY);
5734
5735 /* Process the arch string. */
5736 len = strlen (cpu_arch_name);
5737
5738 i_note.namesz = len + 1;
5739 i_note.descsz = 0;
5740 i_note.type = NT_ARCH;
5741 p = frag_more (sizeof (e_note.namesz));
5742 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5743 p = frag_more (sizeof (e_note.descsz));
5744 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5745 p = frag_more (sizeof (e_note.type));
5746 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5747 p = frag_more (len + 1);
5748 strcpy (p, cpu_arch_name);
5749
5750 frag_align (2, 0, 0);
5751
5752 subseg_set (seg, subseg);
5753 }
5754}
5755#endif
252b5132 5756\f
252b5132
RH		 5757symbolS *
5758md_undefined_symbol (name)
5759 char *name;
5760{
18dc2407
ILT		 5761 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5762 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5763 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5764 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 5765 {
5766 if (!GOT_symbol)
5767 {
5768 if (symbol_find (name))
5769 as_bad (_("GOT already in symbol table"));
5770 GOT_symbol = symbol_new (name, undefined_section,
5771 (valueT) 0, &zero_address_frag);
5772 };
5773 return GOT_symbol;
5774 }
252b5132
RH		 5775 return 0;
5776}
5777
5778/* Round up a section size to the appropriate boundary. */
47926f60 5779
252b5132
RH		 5780valueT
5781md_section_align (segment, size)
ab9da554 5782 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 5783 valueT size;
5784{
4c63da97
AM		 5785#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5786 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5787 {
5788 /* For a.out, force the section size to be aligned. If we don't do
5789 this, BFD will align it for us, but it will not write out the
5790 final bytes of the section. This may be a bug in BFD, but it is
5791 easier to fix it here since that is how the other a.out targets
5792 work. */
5793 int align;
5794
5795 align = bfd_get_section_alignment (stdoutput, segment);
5796 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5797 }
252b5132
RH		 5798#endif
5799
5800 return size;
5801}
5802
5803/* On the i386, PC-relative offsets are relative to the start of the
5804 next instruction. That is, the address of the offset, plus its
5805 size, since the offset is always the last part of the insn. */
5806
5807long
5808md_pcrel_from (fixP)
5809 fixS *fixP;
5810{
5811 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5812}
5813
5814#ifndef I386COFF
5815
5816static void
5817s_bss (ignore)
ab9da554 5818 int ignore ATTRIBUTE_UNUSED;
252b5132 5819{
29b0f896 5820 int temp;
252b5132 5821
8a75718c
JB		 5822#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
5823 if (IS_ELF)
5824 obj_elf_section_change_hook ();
5825#endif
252b5132
RH		 5826 temp = get_absolute_expression ();
5827 subseg_set (bss_section, (subsegT) temp);
5828 demand_empty_rest_of_line ();
5829}
5830
5831#endif
5832
252b5132
RH		 5833void
5834i386_validate_fix (fixp)
5835 fixS *fixp;
5836{
5837 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5838 {
23df1078
JH		 5839 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5840 {
4fa24527 5841 if (!object_64bit)
23df1078
JH		 5842 abort ();
5843 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5844 }
5845 else
5846 {
4fa24527 5847 if (!object_64bit)
d6ab8113
JB		 5848 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5849 else
5850 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 5851 }
252b5132
RH		 5852 fixp->fx_subsy = 0;
5853 }
5854}
5855
252b5132
RH		 5856arelent *
5857tc_gen_reloc (section, fixp)
ab9da554 5858 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 5859 fixS *fixp;
5860{
5861 arelent *rel;
5862 bfd_reloc_code_real_type code;
5863
5864 switch (fixp->fx_r_type)
5865 {
3e73aa7c
JH		 5866 case BFD_RELOC_X86_64_PLT32:
5867 case BFD_RELOC_X86_64_GOT32:
5868 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 5869 case BFD_RELOC_386_PLT32:
5870 case BFD_RELOC_386_GOT32:
5871 case BFD_RELOC_386_GOTOFF:
5872 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 5873 case BFD_RELOC_386_TLS_GD:
5874 case BFD_RELOC_386_TLS_LDM:
5875 case BFD_RELOC_386_TLS_LDO_32:
5876 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 5877 case BFD_RELOC_386_TLS_IE:
5878 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 5879 case BFD_RELOC_386_TLS_LE_32:
5880 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 5881 case BFD_RELOC_386_TLS_GOTDESC:
5882 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 5883 case BFD_RELOC_X86_64_TLSGD:
5884 case BFD_RELOC_X86_64_TLSLD:
5885 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 5886 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 5887 case BFD_RELOC_X86_64_GOTTPOFF:
5888 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 5889 case BFD_RELOC_X86_64_TPOFF64:
5890 case BFD_RELOC_X86_64_GOTOFF64:
5891 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 5892 case BFD_RELOC_X86_64_GOT64:
5893 case BFD_RELOC_X86_64_GOTPCREL64:
5894 case BFD_RELOC_X86_64_GOTPC64:
5895 case BFD_RELOC_X86_64_GOTPLT64:
5896 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 5897 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
5898 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 5899 case BFD_RELOC_RVA:
5900 case BFD_RELOC_VTABLE_ENTRY:
5901 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 5902#ifdef TE_PE
5903 case BFD_RELOC_32_SECREL:
5904#endif
252b5132
RH		 5905 code = fixp->fx_r_type;
5906 break;
dbbaec26
L		 5907 case BFD_RELOC_X86_64_32S:
5908 if (!fixp->fx_pcrel)
5909 {
5910 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
5911 code = fixp->fx_r_type;
5912 break;
5913 }
252b5132 5914 default:
93382f6d 5915 if (fixp->fx_pcrel)
252b5132 5916 {
93382f6d
AM		 5917 switch (fixp->fx_size)
5918 {
5919 default:
b091f402
AM		 5920 as_bad_where (fixp->fx_file, fixp->fx_line,
5921 _("can not do %d byte pc-relative relocation"),
5922 fixp->fx_size);
93382f6d
AM		 5923 code = BFD_RELOC_32_PCREL;
5924 break;
5925 case 1: code = BFD_RELOC_8_PCREL; break;
5926 case 2: code = BFD_RELOC_16_PCREL; break;
5927 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 5928#ifdef BFD64
5929 case 8: code = BFD_RELOC_64_PCREL; break;
5930#endif
93382f6d
AM		 5931 }
5932 }
5933 else
5934 {
5935 switch (fixp->fx_size)
5936 {
5937 default:
b091f402
AM		 5938 as_bad_where (fixp->fx_file, fixp->fx_line,
5939 _("can not do %d byte relocation"),
5940 fixp->fx_size);
93382f6d
AM		 5941 code = BFD_RELOC_32;
5942 break;
5943 case 1: code = BFD_RELOC_8; break;
5944 case 2: code = BFD_RELOC_16; break;
5945 case 4: code = BFD_RELOC_32; break;
937149dd 5946#ifdef BFD64
3e73aa7c 5947 case 8: code = BFD_RELOC_64; break;
937149dd 5948#endif
93382f6d 5949 }
252b5132
RH		 5950 }
5951 break;
5952 }
252b5132 5953
d182319b
JB		 5954 if ((code == BFD_RELOC_32
5955 || code == BFD_RELOC_32_PCREL
5956 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 5957 && GOT_symbol
5958 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 5959 {
4fa24527 5960 if (!object_64bit)
d6ab8113
JB		 5961 code = BFD_RELOC_386_GOTPC;
5962 else
5963 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 5964 }
7b81dfbb
AJ		 5965 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
5966 && GOT_symbol
5967 && fixp->fx_addsy == GOT_symbol)
5968 {
5969 code = BFD_RELOC_X86_64_GOTPC64;
5970 }
252b5132
RH		 5971
5972 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 5973 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5974 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 5975
5976 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 5977
3e73aa7c
JH		 5978 if (!use_rela_relocations)
5979 {
5980 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5981 vtable entry to be used in the relocation's section offset. */
5982 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5983 rel->address = fixp->fx_offset;
252b5132 5984
c6682705 5985 rel->addend = 0;
3e73aa7c
JH		 5986 }
5987 /* Use the rela in 64bit mode. */
252b5132 5988 else
3e73aa7c 5989 {
062cd5e7
AS		 5990 if (!fixp->fx_pcrel)
5991 rel->addend = fixp->fx_offset;
5992 else
5993 switch (code)
5994 {
5995 case BFD_RELOC_X86_64_PLT32:
5996 case BFD_RELOC_X86_64_GOT32:
5997 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 5998 case BFD_RELOC_X86_64_TLSGD:
5999 case BFD_RELOC_X86_64_TLSLD:
6000 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 6001 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
6002 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 6003 rel->addend = fixp->fx_offset - fixp->fx_size;
6004 break;
6005 default:
6006 rel->addend = (section->vma
6007 - fixp->fx_size
6008 + fixp->fx_addnumber
6009 + md_pcrel_from (fixp));
6010 break;
6011 }
3e73aa7c
JH		 6012 }
6013
252b5132
RH		 6014 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
6015 if (rel->howto == NULL)
6016 {
6017 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 6018 _("cannot represent relocation type %s"),
252b5132
RH		 6019 bfd_get_reloc_code_name (code));
6020 /* Set howto to a garbage value so that we can keep going. */
6021 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
6022 assert (rel->howto != NULL);
6023 }
6024
6025 return rel;
6026}
6027
64a0c779
DN		 6028\f
6029/* Parse operands using Intel syntax. This implements a recursive descent
6030 parser based on the BNF grammar published in Appendix B of the MASM 6.1
6031 Programmer's Guide.
6032
6033 FIXME: We do not recognize the full operand grammar defined in the MASM
6034 documentation. In particular, all the structure/union and
6035 high-level macro operands are missing.
6036
6037 Uppercase words are terminals, lower case words are non-terminals.
6038 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
6039 bars '|' denote choices. Most grammar productions are implemented in
6040 functions called 'intel_<production>'.
6041
6042 Initial production is 'expr'.
6043
9306ca4a 6044 addOp + | -
64a0c779
DN		 6045
6046 alpha [a-zA-Z]
6047
9306ca4a
JB		 6048 binOp & | AND | \| | OR | ^ | XOR
6049
64a0c779
DN		 6050 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
6051
6052 constant digits [[ radixOverride ]]
6053
9306ca4a 6054 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 6055
6056 digits decdigit
b77a7acd
AJ		 6057 | digits decdigit
6058 | digits hexdigit
64a0c779
DN		 6059
6060 decdigit [0-9]
6061
9306ca4a
JB		 6062 e04 e04 addOp e05
6063 | e05
6064
6065 e05 e05 binOp e06
b77a7acd 6066 | e06
64a0c779
DN		 6067
6068 e06 e06 mulOp e09
b77a7acd 6069 | e09
64a0c779
DN		 6070
6071 e09 OFFSET e10
a724f0f4
JB		 6072 | SHORT e10
6073 | + e10
6074 | - e10
9306ca4a
JB		 6075 | ~ e10
6076 | NOT e10
64a0c779
DN		 6077 | e09 PTR e10
6078 | e09 : e10
6079 | e10
6080
6081 e10 e10 [ expr ]
b77a7acd 6082 | e11
64a0c779
DN		 6083
6084 e11 ( expr )
b77a7acd 6085 | [ expr ]
64a0c779
DN		 6086 | constant
6087 | dataType
6088 | id
6089 | $
6090 | register
6091
a724f0f4 6092 => expr expr cmpOp e04
9306ca4a 6093 | e04
64a0c779
DN		 6094
6095 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 6096 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 6097
6098 hexdigit a | b | c | d | e | f
b77a7acd 6099 | A | B | C | D | E | F
64a0c779
DN		 6100
6101 id alpha
b77a7acd 6102 | id alpha
64a0c779
DN		 6103 | id decdigit
6104
9306ca4a 6105 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 6106
6107 quote " | '
6108
6109 register specialRegister
b77a7acd 6110 | gpRegister
64a0c779
DN		 6111 | byteRegister
6112
6113 segmentRegister CS | DS | ES | FS | GS | SS
6114
9306ca4a 6115 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 6116 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 6117 | TR3 | TR4 | TR5 | TR6 | TR7
6118
64a0c779
DN		 6119 We simplify the grammar in obvious places (e.g., register parsing is
6120 done by calling parse_register) and eliminate immediate left recursion
6121 to implement a recursive-descent parser.
6122
a724f0f4
JB		 6123 expr e04 expr'
6124
6125 expr' cmpOp e04 expr'
6126 | Empty
9306ca4a
JB		 6127
6128 e04 e05 e04'
6129
6130 e04' addOp e05 e04'
6131 | Empty
64a0c779
DN		 6132
6133 e05 e06 e05'
6134
9306ca4a 6135 e05' binOp e06 e05'
b77a7acd 6136 | Empty
64a0c779
DN		 6137
6138 e06 e09 e06'
6139
6140 e06' mulOp e09 e06'
b77a7acd 6141 | Empty
64a0c779
DN		 6142
6143 e09 OFFSET e10 e09'
a724f0f4
JB		 6144 | SHORT e10'
6145 | + e10'
6146 | - e10'
6147 | ~ e10'
6148 | NOT e10'
b77a7acd 6149 | e10 e09'
64a0c779
DN		 6150
6151 e09' PTR e10 e09'
b77a7acd 6152 | : e10 e09'
64a0c779
DN		 6153 | Empty
6154
6155 e10 e11 e10'
6156
6157 e10' [ expr ] e10'
b77a7acd 6158 | Empty
64a0c779
DN		 6159
6160 e11 ( expr )
b77a7acd 6161 | [ expr ]
64a0c779
DN		 6162 | BYTE
6163 | WORD
6164 | DWORD
9306ca4a 6165 | FWORD
64a0c779 6166 | QWORD
9306ca4a
JB		 6167 | TBYTE
6168 | OWORD
6169 | XMMWORD
64a0c779
DN		 6170 | .
6171 | $
6172 | register
6173 | id
6174 | constant */
6175
6176/* Parsing structure for the intel syntax parser. Used to implement the
6177 semantic actions for the operand grammar. */
6178struct intel_parser_s
6179 {
6180 char *op_string; /* The string being parsed. */
6181 int got_a_float; /* Whether the operand is a float. */
4a1805b1 6182 int op_modifier; /* Operand modifier. */
64a0c779 6183 int is_mem; /* 1 if operand is memory reference. */
a724f0f4
JB		 6184 int in_offset; /* >=1 if parsing operand of offset. */
6185 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 6186 const reg_entry *reg; /* Last register reference found. */
6187 char *disp; /* Displacement string being built. */
a724f0f4 6188 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 6189 };
6190
6191static struct intel_parser_s intel_parser;
6192
6193/* Token structure for parsing intel syntax. */
6194struct intel_token
6195 {
6196 int code; /* Token code. */
6197 const reg_entry *reg; /* Register entry for register tokens. */
6198 char *str; /* String representation. */
6199 };
6200
6201static struct intel_token cur_token, prev_token;
6202
50705ef4
AM		 6203/* Token codes for the intel parser. Since T_SHORT is already used
6204 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 6205#define T_NIL -1
6206#define T_CONST 1
6207#define T_REG 2
6208#define T_BYTE 3
6209#define T_WORD 4
9306ca4a
JB		 6210#define T_DWORD 5
6211#define T_FWORD 6
6212#define T_QWORD 7
6213#define T_TBYTE 8
6214#define T_XMMWORD 9
50705ef4 6215#undef T_SHORT
9306ca4a
JB		 6216#define T_SHORT 10
6217#define T_OFFSET 11
6218#define T_PTR 12
6219#define T_ID 13
6220#define T_SHL 14
6221#define T_SHR 15
64a0c779
DN		 6222
6223/* Prototypes for intel parser functions. */
6224static int intel_match_token PARAMS ((int code));
cce0cbdc
DN		 6225static void intel_get_token PARAMS ((void));
6226static void intel_putback_token PARAMS ((void));
6227static int intel_expr PARAMS ((void));
9306ca4a 6228static int intel_e04 PARAMS ((void));
cce0cbdc 6229static int intel_e05 PARAMS ((void));
cce0cbdc 6230static int intel_e06 PARAMS ((void));
cce0cbdc 6231static int intel_e09 PARAMS ((void));
a724f0f4 6232static int intel_bracket_expr PARAMS ((void));
cce0cbdc 6233static int intel_e10 PARAMS ((void));
cce0cbdc 6234static int intel_e11 PARAMS ((void));
64a0c779 6235
64a0c779
DN		 6236static int
6237i386_intel_operand (operand_string, got_a_float)
6238 char *operand_string;
6239 int got_a_float;
6240{
6241 int ret;
6242 char *p;
6243
a724f0f4
JB		 6244 p = intel_parser.op_string = xstrdup (operand_string);
6245 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
6246
6247 for (;;)
64a0c779 6248 {
a724f0f4
JB		 6249 /* Initialize token holders. */
6250 cur_token.code = prev_token.code = T_NIL;
6251 cur_token.reg = prev_token.reg = NULL;
6252 cur_token.str = prev_token.str = NULL;
6253
6254 /* Initialize parser structure. */
6255 intel_parser.got_a_float = got_a_float;
6256 intel_parser.op_modifier = 0;
6257 intel_parser.is_mem = 0;
6258 intel_parser.in_offset = 0;
6259 intel_parser.in_bracket = 0;
6260 intel_parser.reg = NULL;
6261 intel_parser.disp[0] = '\0';
6262 intel_parser.next_operand = NULL;
6263
6264 /* Read the first token and start the parser. */
6265 intel_get_token ();
6266 ret = intel_expr ();
6267
6268 if (!ret)
6269 break;
6270
9306ca4a
JB		 6271 if (cur_token.code != T_NIL)
6272 {
6273 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
6274 current_templates->start->name, cur_token.str);
6275 ret = 0;
6276 }
64a0c779
DN		 6277 /* If we found a memory reference, hand it over to i386_displacement
6278 to fill in the rest of the operand fields. */
9306ca4a 6279 else if (intel_parser.is_mem)
64a0c779
DN		 6280 {
6281 if ((i.mem_operands == 1
6282 && (current_templates->start->opcode_modifier & IsString) == 0)
6283 || i.mem_operands == 2)
6284 {
6285 as_bad (_("too many memory references for '%s'"),
6286 current_templates->start->name);
6287 ret = 0;
6288 }
6289 else
6290 {
6291 char *s = intel_parser.disp;
6292 i.mem_operands++;
6293
a724f0f4
JB		 6294 if (!quiet_warnings && intel_parser.is_mem < 0)
6295 /* See the comments in intel_bracket_expr. */
6296 as_warn (_("Treating `%s' as memory reference"), operand_string);
6297
64a0c779
DN		 6298 /* Add the displacement expression. */
6299 if (*s != '\0')
a4622f40
AM		 6300 ret = i386_displacement (s, s + strlen (s));
6301 if (ret)
a724f0f4
JB		 6302 {
6303 /* Swap base and index in 16-bit memory operands like
6304 [si+bx]. Since i386_index_check is also used in AT&T
6305 mode we have to do that here. */
6306 if (i.base_reg
6307 && i.index_reg
6308 && (i.base_reg->reg_type & Reg16)
6309 && (i.index_reg->reg_type & Reg16)
6310 && i.base_reg->reg_num >= 6
6311 && i.index_reg->reg_num < 6)
6312 {
6313 const reg_entry *base = i.index_reg;
6314
6315 i.index_reg = i.base_reg;
6316 i.base_reg = base;
6317 }
6318 ret = i386_index_check (operand_string);
6319 }
64a0c779
DN		 6320 }
6321 }
6322
6323 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 6324 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 6325 || intel_parser.reg == NULL)
6326 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 6327
6328 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
6329 ret = 0;
6330 if (!ret || !intel_parser.next_operand)
6331 break;
6332 intel_parser.op_string = intel_parser.next_operand;
6333 this_operand = i.operands++;
64a0c779
DN		 6334 }
6335
6336 free (p);
6337 free (intel_parser.disp);
6338
6339 return ret;
6340}
6341
a724f0f4
JB		 6342#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
6343
6344/* expr e04 expr'
6345
6346 expr' cmpOp e04 expr'
6347 | Empty */
64a0c779
DN		 6348static int
6349intel_expr ()
6350{
a724f0f4
JB		 6351 /* XXX Implement the comparison operators. */
6352 return intel_e04 ();
9306ca4a
JB		 6353}
6354
a724f0f4 6355/* e04 e05 e04'
9306ca4a 6356
a724f0f4 6357 e04' addOp e05 e04'
9306ca4a
JB		 6358 | Empty */
6359static int
6360intel_e04 ()
6361{
a724f0f4 6362 int nregs = -1;
9306ca4a 6363
a724f0f4 6364 for (;;)
9306ca4a 6365 {
a724f0f4
JB		 6366 if (!intel_e05())
6367 return 0;
9306ca4a 6368
a724f0f4
JB		 6369 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6370 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 6371
a724f0f4
JB		 6372 if (cur_token.code == '+')
6373 nregs = -1;
6374 else if (cur_token.code == '-')
6375 nregs = NUM_ADDRESS_REGS;
6376 else
6377 return 1;
64a0c779 6378
a724f0f4
JB		 6379 strcat (intel_parser.disp, cur_token.str);
6380 intel_match_token (cur_token.code);
6381 }
64a0c779
DN		 6382}
6383
64a0c779
DN		 6384/* e05 e06 e05'
6385
9306ca4a 6386 e05' binOp e06 e05'
64a0c779
DN		 6387 | Empty */
6388static int
6389intel_e05 ()
6390{
a724f0f4 6391 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6392
a724f0f4 6393 for (;;)
64a0c779 6394 {
a724f0f4
JB		 6395 if (!intel_e06())
6396 return 0;
6397
6398 if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^')
6399 {
6400 char str[2];
6401
6402 str[0] = cur_token.code;
6403 str[1] = 0;
6404 strcat (intel_parser.disp, str);
6405 }
6406 else
6407 break;
9306ca4a 6408
64a0c779
DN		 6409 intel_match_token (cur_token.code);
6410
a724f0f4
JB		 6411 if (nregs < 0)
6412 nregs = ~nregs;
64a0c779 6413 }
a724f0f4
JB		 6414 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6415 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
6416 return 1;
4a1805b1 6417}
64a0c779
DN		 6418
6419/* e06 e09 e06'
6420
6421 e06' mulOp e09 e06'
b77a7acd 6422 | Empty */
64a0c779
DN		 6423static int
6424intel_e06 ()
6425{
a724f0f4 6426 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 6427
a724f0f4 6428 for (;;)
64a0c779 6429 {
a724f0f4
JB		 6430 if (!intel_e09())
6431 return 0;
9306ca4a 6432
a724f0f4
JB		 6433 if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%')
6434 {
6435 char str[2];
9306ca4a 6436
a724f0f4
JB		 6437 str[0] = cur_token.code;
6438 str[1] = 0;
6439 strcat (intel_parser.disp, str);
6440 }
6441 else if (cur_token.code == T_SHL)
6442 strcat (intel_parser.disp, "<<");
6443 else if (cur_token.code == T_SHR)
6444 strcat (intel_parser.disp, ">>");
6445 else
6446 break;
9306ca4a 6447
64e74474 6448 intel_match_token (cur_token.code);
64a0c779 6449
a724f0f4
JB		 6450 if (nregs < 0)
6451 nregs = ~nregs;
64a0c779 6452 }
a724f0f4
JB		 6453 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6454 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
6455 return 1;
64a0c779
DN		 6456}
6457
a724f0f4
JB		 6458/* e09 OFFSET e09
6459 | SHORT e09
6460 | + e09
6461 | - e09
6462 | ~ e09
6463 | NOT e09
9306ca4a
JB		 6464 | e10 e09'
6465
64a0c779 6466 e09' PTR e10 e09'
b77a7acd 6467 | : e10 e09'
64a0c779
DN		 6468 | Empty */
6469static int
6470intel_e09 ()
6471{
a724f0f4
JB		 6472 int nregs = ~NUM_ADDRESS_REGS;
6473 int in_offset = 0;
6474
6475 for (;;)
64a0c779 6476 {
a724f0f4
JB		 6477 /* Don't consume constants here. */
6478 if (cur_token.code == '+' || cur_token.code == '-')
6479 {
6480 /* Need to look one token ahead - if the next token
6481 is a constant, the current token is its sign. */
6482 int next_code;
6483
6484 intel_match_token (cur_token.code);
6485 next_code = cur_token.code;
6486 intel_putback_token ();
6487 if (next_code == T_CONST)
6488 break;
6489 }
6490
6491 /* e09 OFFSET e09 */
6492 if (cur_token.code == T_OFFSET)
6493 {
6494 if (!in_offset++)
6495 ++intel_parser.in_offset;
6496 }
6497
6498 /* e09 SHORT e09 */
6499 else if (cur_token.code == T_SHORT)
6500 intel_parser.op_modifier |= 1 << T_SHORT;
6501
6502 /* e09 + e09 */
6503 else if (cur_token.code == '+')
6504 strcat (intel_parser.disp, "+");
6505
6506 /* e09 - e09
6507 | ~ e09
6508 | NOT e09 */
6509 else if (cur_token.code == '-' || cur_token.code == '~')
6510 {
6511 char str[2];
64a0c779 6512
a724f0f4
JB		 6513 if (nregs < 0)
6514 nregs = ~nregs;
6515 str[0] = cur_token.code;
6516 str[1] = 0;
6517 strcat (intel_parser.disp, str);
6518 }
6519
6520 /* e09 e10 e09' */
6521 else
6522 break;
6523
6524 intel_match_token (cur_token.code);
64a0c779
DN		 6525 }
6526
a724f0f4 6527 for (;;)
9306ca4a 6528 {
a724f0f4
JB		 6529 if (!intel_e10 ())
6530 return 0;
9306ca4a 6531
a724f0f4
JB		 6532 /* e09' PTR e10 e09' */
6533 if (cur_token.code == T_PTR)
6534 {
6535 char suffix;
9306ca4a 6536
a724f0f4
JB		 6537 if (prev_token.code == T_BYTE)
6538 suffix = BYTE_MNEM_SUFFIX;
9306ca4a 6539
a724f0f4
JB		 6540 else if (prev_token.code == T_WORD)
6541 {
6542 if (current_templates->start->name[0] == 'l'
6543 && current_templates->start->name[2] == 's'
6544 && current_templates->start->name[3] == 0)
6545 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6546 else if (intel_parser.got_a_float == 2) /* "fi..." */
6547 suffix = SHORT_MNEM_SUFFIX;
6548 else
6549 suffix = WORD_MNEM_SUFFIX;
6550 }
64a0c779 6551
a724f0f4
JB		 6552 else if (prev_token.code == T_DWORD)
6553 {
6554 if (current_templates->start->name[0] == 'l'
6555 && current_templates->start->name[2] == 's'
6556 && current_templates->start->name[3] == 0)
6557 suffix = WORD_MNEM_SUFFIX;
6558 else if (flag_code == CODE_16BIT
6559 && (current_templates->start->opcode_modifier
435acd52 6560 & (Jump | JumpDword)))
a724f0f4
JB		 6561 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6562 else if (intel_parser.got_a_float == 1) /* "f..." */
6563 suffix = SHORT_MNEM_SUFFIX;
6564 else
6565 suffix = LONG_MNEM_SUFFIX;
6566 }
9306ca4a 6567
a724f0f4
JB		 6568 else if (prev_token.code == T_FWORD)
6569 {
6570 if (current_templates->start->name[0] == 'l'
6571 && current_templates->start->name[2] == 's'
6572 && current_templates->start->name[3] == 0)
6573 suffix = LONG_MNEM_SUFFIX;
6574 else if (!intel_parser.got_a_float)
6575 {
6576 if (flag_code == CODE_16BIT)
6577 add_prefix (DATA_PREFIX_OPCODE);
6578 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6579 }
6580 else
6581 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6582 }
64a0c779 6583
a724f0f4
JB		 6584 else if (prev_token.code == T_QWORD)
6585 {
6586 if (intel_parser.got_a_float == 1) /* "f..." */
6587 suffix = LONG_MNEM_SUFFIX;
6588 else
6589 suffix = QWORD_MNEM_SUFFIX;
6590 }
64a0c779 6591
a724f0f4
JB		 6592 else if (prev_token.code == T_TBYTE)
6593 {
6594 if (intel_parser.got_a_float == 1)
6595 suffix = LONG_DOUBLE_MNEM_SUFFIX;
6596 else
6597 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
6598 }
9306ca4a 6599
a724f0f4 6600 else if (prev_token.code == T_XMMWORD)
9306ca4a 6601 {
a724f0f4
JB		 6602 /* XXX ignored for now, but accepted since gcc uses it */
6603 suffix = 0;
9306ca4a 6604 }
64a0c779 6605
f16b83df 6606 else
a724f0f4
JB		 6607 {
6608 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
6609 return 0;
6610 }
6611
435acd52
JB		 6612 /* Operands for jump/call using 'ptr' notation denote absolute
6613 addresses. */
6614 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6615 i.types[this_operand] |= JumpAbsolute;
6616
a724f0f4
JB		 6617 if (current_templates->start->base_opcode == 0x8d /* lea */)
6618 ;
6619 else if (!i.suffix)
6620 i.suffix = suffix;
6621 else if (i.suffix != suffix)
6622 {
6623 as_bad (_("Conflicting operand modifiers"));
6624 return 0;
6625 }
64a0c779 6626
9306ca4a
JB		 6627 }
6628
a724f0f4
JB		 6629 /* e09' : e10 e09' */
6630 else if (cur_token.code == ':')
9306ca4a 6631 {
a724f0f4
JB		 6632 if (prev_token.code != T_REG)
6633 {
6634 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
6635 segment/group identifier (which we don't have), using comma
6636 as the operand separator there is even less consistent, since
6637 there all branches only have a single operand. */
6638 if (this_operand != 0
6639 || intel_parser.in_offset
6640 || intel_parser.in_bracket
6641 || (!(current_templates->start->opcode_modifier
6642 & (Jump|JumpDword|JumpInterSegment))
6643 && !(current_templates->start->operand_types[0]
6644 & JumpAbsolute)))
6645 return intel_match_token (T_NIL);
6646 /* Remember the start of the 2nd operand and terminate 1st
6647 operand here.
6648 XXX This isn't right, yet (when SSSS:OOOO is right operand of
6649 another expression), but it gets at least the simplest case
6650 (a plain number or symbol on the left side) right. */
6651 intel_parser.next_operand = intel_parser.op_string;
6652 *--intel_parser.op_string = '\0';
6653 return intel_match_token (':');
6654 }
9306ca4a 6655 }
64a0c779 6656
a724f0f4 6657 /* e09' Empty */
64a0c779 6658 else
a724f0f4 6659 break;
64a0c779 6660
a724f0f4
JB		 6661 intel_match_token (cur_token.code);
6662
6663 }
6664
6665 if (in_offset)
6666 {
6667 --intel_parser.in_offset;
6668 if (nregs < 0)
6669 nregs = ~nregs;
6670 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 6671 {
a724f0f4 6672 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 6673 return 0;
6674 }
a724f0f4
JB		 6675 intel_parser.op_modifier |= 1 << T_OFFSET;
6676 }
9306ca4a 6677
a724f0f4
JB		 6678 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
6679 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
6680 return 1;
6681}
64a0c779 6682
a724f0f4
JB		 6683static int
6684intel_bracket_expr ()
6685{
6686 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
6687 const char *start = intel_parser.op_string;
6688 int len;
6689
6690 if (i.op[this_operand].regs)
6691 return intel_match_token (T_NIL);
6692
6693 intel_match_token ('[');
6694
6695 /* Mark as a memory operand only if it's not already known to be an
6696 offset expression. If it's an offset expression, we need to keep
6697 the brace in. */
6698 if (!intel_parser.in_offset)
6699 {
6700 ++intel_parser.in_bracket;
435acd52
JB		 6701
6702 /* Operands for jump/call inside brackets denote absolute addresses. */
6703 if (current_templates->start->opcode_modifier & (Jump | JumpDword))
6704 i.types[this_operand] |= JumpAbsolute;
6705
a724f0f4
JB		 6706 /* Unfortunately gas always diverged from MASM in a respect that can't
6707 be easily fixed without risking to break code sequences likely to be
6708 encountered (the testsuite even check for this): MASM doesn't consider
6709 an expression inside brackets unconditionally as a memory reference.
6710 When that is e.g. a constant, an offset expression, or the sum of the
6711 two, this is still taken as a constant load. gas, however, always
6712 treated these as memory references. As a compromise, we'll try to make
6713 offset expressions inside brackets work the MASM way (since that's
6714 less likely to be found in real world code), but make constants alone
6715 continue to work the traditional gas way. In either case, issue a
6716 warning. */
6717 intel_parser.op_modifier &= ~was_offset;
64a0c779 6718 }
a724f0f4 6719 else
64e74474 6720 strcat (intel_parser.disp, "[");
a724f0f4
JB		 6721
6722 /* Add a '+' to the displacement string if necessary. */
6723 if (*intel_parser.disp != '\0'
6724 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
6725 strcat (intel_parser.disp, "+");
64a0c779 6726
a724f0f4
JB		 6727 if (intel_expr ()
6728 && (len = intel_parser.op_string - start - 1,
6729 intel_match_token (']')))
64a0c779 6730 {
a724f0f4
JB		 6731 /* Preserve brackets when the operand is an offset expression. */
6732 if (intel_parser.in_offset)
6733 strcat (intel_parser.disp, "]");
6734 else
6735 {
6736 --intel_parser.in_bracket;
6737 if (i.base_reg || i.index_reg)
6738 intel_parser.is_mem = 1;
6739 if (!intel_parser.is_mem)
6740 {
6741 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
6742 /* Defer the warning until all of the operand was parsed. */
6743 intel_parser.is_mem = -1;
6744 else if (!quiet_warnings)
6745 as_warn (_("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start);
6746 }
6747 }
6748 intel_parser.op_modifier |= was_offset;
64a0c779 6749
a724f0f4 6750 return 1;
64a0c779 6751 }
a724f0f4 6752 return 0;
64a0c779
DN		 6753}
6754
6755/* e10 e11 e10'
6756
6757 e10' [ expr ] e10'
b77a7acd 6758 | Empty */
64a0c779
DN		 6759static int
6760intel_e10 ()
6761{
a724f0f4
JB		 6762 if (!intel_e11 ())
6763 return 0;
64a0c779 6764
a724f0f4 6765 while (cur_token.code == '[')
64a0c779 6766 {
a724f0f4 6767 if (!intel_bracket_expr ())
21d6c4af 6768 return 0;
64a0c779
DN		 6769 }
6770
a724f0f4 6771 return 1;
64a0c779
DN		 6772}
6773
64a0c779 6774/* e11 ( expr )
b77a7acd 6775 | [ expr ]
64a0c779
DN		 6776 | BYTE
6777 | WORD
6778 | DWORD
9306ca4a 6779 | FWORD
64a0c779 6780 | QWORD
9306ca4a
JB		 6781 | TBYTE
6782 | OWORD
6783 | XMMWORD
4a1805b1 6784 | $
64a0c779
DN		 6785 | .
6786 | register
6787 | id
6788 | constant */
6789static int
6790intel_e11 ()
6791{
a724f0f4 6792 switch (cur_token.code)
64a0c779 6793 {
a724f0f4
JB		 6794 /* e11 ( expr ) */
6795 case '(':
64a0c779
DN		 6796 intel_match_token ('(');
6797 strcat (intel_parser.disp, "(");
6798
6799 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 6800 {
6801 strcat (intel_parser.disp, ")");
6802 return 1;
6803 }
a724f0f4 6804 return 0;
4a1805b1 6805
a724f0f4
JB		 6806 /* e11 [ expr ] */
6807 case '[':
a724f0f4 6808 return intel_bracket_expr ();
64a0c779 6809
a724f0f4
JB		 6810 /* e11 $
6811 | . */
6812 case '.':
64a0c779
DN		 6813 strcat (intel_parser.disp, cur_token.str);
6814 intel_match_token (cur_token.code);
21d6c4af
DN		 6815
6816 /* Mark as a memory operand only if it's not already known to be an
6817 offset expression. */
a724f0f4 6818 if (!intel_parser.in_offset)
21d6c4af 6819 intel_parser.is_mem = 1;
64a0c779
DN		 6820
6821 return 1;
64a0c779 6822
a724f0f4
JB		 6823 /* e11 register */
6824 case T_REG:
6825 {
6826 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 6827
a724f0f4 6828 intel_match_token (T_REG);
64a0c779 6829
a724f0f4
JB		 6830 /* Check for segment change. */
6831 if (cur_token.code == ':')
6832 {
6833 if (!(reg->reg_type & (SReg2 | SReg3)))
6834 {
6835 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
6836 return 0;
6837 }
6838 else if (i.seg[i.mem_operands])
6839 as_warn (_("Extra segment override ignored"));
6840 else
6841 {
6842 if (!intel_parser.in_offset)
6843 intel_parser.is_mem = 1;
6844 switch (reg->reg_num)
6845 {
6846 case 0:
6847 i.seg[i.mem_operands] = &es;
6848 break;
6849 case 1:
6850 i.seg[i.mem_operands] = &cs;
6851 break;
6852 case 2:
6853 i.seg[i.mem_operands] = &ss;
6854 break;
6855 case 3:
6856 i.seg[i.mem_operands] = &ds;
6857 break;
6858 case 4:
6859 i.seg[i.mem_operands] = &fs;
6860 break;
6861 case 5:
6862 i.seg[i.mem_operands] = &gs;
6863 break;
6864 }
6865 }
6866 }
64a0c779 6867
a724f0f4
JB		 6868 /* Not a segment register. Check for register scaling. */
6869 else if (cur_token.code == '*')
6870 {
6871 if (!intel_parser.in_bracket)
6872 {
6873 as_bad (_("Register scaling only allowed in memory operands"));
6874 return 0;
6875 }
64a0c779 6876
a724f0f4
JB		 6877 if (reg->reg_type & Reg16) /* Disallow things like [si*1]. */
6878 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
6879 else if (i.index_reg)
6880 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 6881
a724f0f4
JB		 6882 /* What follows must be a valid scale. */
6883 intel_match_token ('*');
6884 i.index_reg = reg;
6885 i.types[this_operand] |= BaseIndex;
64a0c779 6886
a724f0f4
JB		 6887 /* Set the scale after setting the register (otherwise,
6888 i386_scale will complain) */
6889 if (cur_token.code == '+' || cur_token.code == '-')
6890 {
6891 char *str, sign = cur_token.code;
6892 intel_match_token (cur_token.code);
6893 if (cur_token.code != T_CONST)
6894 {
6895 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
6896 cur_token.str);
6897 return 0;
6898 }
6899 str = (char *) xmalloc (strlen (cur_token.str) + 2);
6900 strcpy (str + 1, cur_token.str);
6901 *str = sign;
6902 if (!i386_scale (str))
6903 return 0;
6904 free (str);
6905 }
6906 else if (!i386_scale (cur_token.str))
64a0c779 6907 return 0;
a724f0f4
JB		 6908 intel_match_token (cur_token.code);
6909 }
64a0c779 6910
a724f0f4
JB		 6911 /* No scaling. If this is a memory operand, the register is either a
6912 base register (first occurrence) or an index register (second
6913 occurrence). */
7b0441f6 6914 else if (intel_parser.in_bracket)
a724f0f4 6915 {
64a0c779 6916
a724f0f4
JB		 6917 if (!i.base_reg)
6918 i.base_reg = reg;
6919 else if (!i.index_reg)
6920 i.index_reg = reg;
6921 else
6922 {
6923 as_bad (_("Too many register references in memory operand"));
6924 return 0;
6925 }
64a0c779 6926
a724f0f4
JB		 6927 i.types[this_operand] |= BaseIndex;
6928 }
4a1805b1 6929
4d1bb795
JB		 6930 /* It's neither base nor index. */
6931 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4
JB		 6932 {
6933 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
6934 i.op[this_operand].regs = reg;
6935 i.reg_operands++;
6936 }
6937 else
6938 {
6939 as_bad (_("Invalid use of register"));
6940 return 0;
6941 }
64a0c779 6942
a724f0f4
JB		 6943 /* Since registers are not part of the displacement string (except
6944 when we're parsing offset operands), we may need to remove any
6945 preceding '+' from the displacement string. */
6946 if (*intel_parser.disp != '\0'
6947 && !intel_parser.in_offset)
6948 {
6949 char *s = intel_parser.disp;
6950 s += strlen (s) - 1;
6951 if (*s == '+')
6952 *s = '\0';
6953 }
4a1805b1 6954
a724f0f4
JB		 6955 return 1;
6956 }
6957
6958 /* e11 BYTE
6959 | WORD
6960 | DWORD
6961 | FWORD
6962 | QWORD
6963 | TBYTE
6964 | OWORD
6965 | XMMWORD */
6966 case T_BYTE:
6967 case T_WORD:
6968 case T_DWORD:
6969 case T_FWORD:
6970 case T_QWORD:
6971 case T_TBYTE:
6972 case T_XMMWORD:
6973 intel_match_token (cur_token.code);
64a0c779 6974
a724f0f4
JB		 6975 if (cur_token.code == T_PTR)
6976 return 1;
6977
6978 /* It must have been an identifier. */
6979 intel_putback_token ();
6980 cur_token.code = T_ID;
6981 /* FALLTHRU */
6982
6983 /* e11 id
6984 | constant */
6985 case T_ID:
6986 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 6987 {
6988 symbolS *symbolP;
6989
a724f0f4
JB		 6990 /* The identifier represents a memory reference only if it's not
6991 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 6992 symbolP = symbol_find(cur_token.str);
6993 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
6994 intel_parser.is_mem = 1;
6995 }
a724f0f4 6996 /* FALLTHRU */
64a0c779 6997
a724f0f4
JB		 6998 case T_CONST:
6999 case '-':
7000 case '+':
7001 {
7002 char *save_str, sign = 0;
64a0c779 7003
a724f0f4
JB		 7004 /* Allow constants that start with `+' or `-'. */
7005 if (cur_token.code == '-' || cur_token.code == '+')
7006 {
7007 sign = cur_token.code;
7008 intel_match_token (cur_token.code);
7009 if (cur_token.code != T_CONST)
7010 {
7011 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
7012 cur_token.str);
7013 return 0;
7014 }
7015 }
64a0c779 7016
a724f0f4
JB		 7017 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
7018 strcpy (save_str + !!sign, cur_token.str);
7019 if (sign)
7020 *save_str = sign;
64a0c779 7021
a724f0f4
JB		 7022 /* Get the next token to check for register scaling. */
7023 intel_match_token (cur_token.code);
64a0c779 7024
a724f0f4
JB		 7025 /* Check if this constant is a scaling factor for an index register. */
7026 if (cur_token.code == '*')
7027 {
7028 if (intel_match_token ('*') && cur_token.code == T_REG)
7029 {
7030 const reg_entry *reg = cur_token.reg;
7031
7032 if (!intel_parser.in_bracket)
7033 {
7034 as_bad (_("Register scaling only allowed in memory operands"));
7035 return 0;
7036 }
7037
7038 if (reg->reg_type & Reg16) /* Disallow things like [1*si]. */
7039 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
7040 else if (i.index_reg)
7041 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
7042
7043 /* The constant is followed by `* reg', so it must be
7044 a valid scale. */
7045 i.index_reg = reg;
7046 i.types[this_operand] |= BaseIndex;
7047
7048 /* Set the scale after setting the register (otherwise,
7049 i386_scale will complain) */
7050 if (!i386_scale (save_str))
64a0c779 7051 return 0;
a724f0f4
JB		 7052 intel_match_token (T_REG);
7053
7054 /* Since registers are not part of the displacement
7055 string, we may need to remove any preceding '+' from
7056 the displacement string. */
7057 if (*intel_parser.disp != '\0')
7058 {
7059 char *s = intel_parser.disp;
7060 s += strlen (s) - 1;
7061 if (*s == '+')
7062 *s = '\0';
7063 }
7064
7065 free (save_str);
7066
7067 return 1;
7068 }
64a0c779 7069
a724f0f4
JB		 7070 /* The constant was not used for register scaling. Since we have
7071 already consumed the token following `*' we now need to put it
7072 back in the stream. */
64a0c779 7073 intel_putback_token ();
a724f0f4 7074 }
64a0c779 7075
a724f0f4
JB		 7076 /* Add the constant to the displacement string. */
7077 strcat (intel_parser.disp, save_str);
7078 free (save_str);
64a0c779 7079
a724f0f4
JB		 7080 return 1;
7081 }
64a0c779
DN		 7082 }
7083
64a0c779
DN		 7084 as_bad (_("Unrecognized token '%s'"), cur_token.str);
7085 return 0;
7086}
7087
64a0c779
DN		 7088/* Match the given token against cur_token. If they match, read the next
7089 token from the operand string. */
7090static int
7091intel_match_token (code)
e5cb08ac 7092 int code;
64a0c779
DN		 7093{
7094 if (cur_token.code == code)
7095 {
7096 intel_get_token ();
7097 return 1;
7098 }
7099 else
7100 {
0477af35 7101 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 7102 return 0;
7103 }
7104}
7105
64a0c779
DN		 7106/* Read a new token from intel_parser.op_string and store it in cur_token. */
7107static void
7108intel_get_token ()
7109{
7110 char *end_op;
7111 const reg_entry *reg;
7112 struct intel_token new_token;
7113
7114 new_token.code = T_NIL;
7115 new_token.reg = NULL;
7116 new_token.str = NULL;
7117
4a1805b1 7118 /* Free the memory allocated to the previous token and move
64a0c779
DN		 7119 cur_token to prev_token. */
7120 if (prev_token.str)
7121 free (prev_token.str);
7122
7123 prev_token = cur_token;
7124
7125 /* Skip whitespace. */
7126 while (is_space_char (*intel_parser.op_string))
7127 intel_parser.op_string++;
7128
7129 /* Return an empty token if we find nothing else on the line. */
7130 if (*intel_parser.op_string == '\0')
7131 {
7132 cur_token = new_token;
7133 return;
7134 }
7135
7136 /* The new token cannot be larger than the remainder of the operand
7137 string. */
a724f0f4 7138 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 7139 new_token.str[0] = '\0';
7140
7141 if (strchr ("0123456789", *intel_parser.op_string))
7142 {
7143 char *p = new_token.str;
7144 char *q = intel_parser.op_string;
7145 new_token.code = T_CONST;
7146
7147 /* Allow any kind of identifier char to encompass floating point and
7148 hexadecimal numbers. */
7149 while (is_identifier_char (*q))
7150 *p++ = *q++;
7151 *p = '\0';
7152
7153 /* Recognize special symbol names [0-9][bf]. */
7154 if (strlen (intel_parser.op_string) == 2
4a1805b1 7155 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 7156 || intel_parser.op_string[1] == 'f'))
7157 new_token.code = T_ID;
7158 }
7159
4d1bb795 7160 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 7161 {
4d1bb795
JB		 7162 size_t len = end_op - intel_parser.op_string;
7163
64a0c779
DN		 7164 new_token.code = T_REG;
7165 new_token.reg = reg;
7166
4d1bb795
JB		 7167 memcpy (new_token.str, intel_parser.op_string, len);
7168 new_token.str[len] = '\0';
64a0c779
DN		 7169 }
7170
7171 else if (is_identifier_char (*intel_parser.op_string))
7172 {
7173 char *p = new_token.str;
7174 char *q = intel_parser.op_string;
7175
7176 /* A '.' or '$' followed by an identifier char is an identifier.
7177 Otherwise, it's operator '.' followed by an expression. */
7178 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
7179 {
9306ca4a
JB		 7180 new_token.code = '.';
7181 new_token.str[0] = '.';
64a0c779
DN		 7182 new_token.str[1] = '\0';
7183 }
7184 else
7185 {
7186 while (is_identifier_char (*q) || *q == '@')
7187 *p++ = *q++;
7188 *p = '\0';
7189
9306ca4a
JB		 7190 if (strcasecmp (new_token.str, "NOT") == 0)
7191 new_token.code = '~';
7192
7193 else if (strcasecmp (new_token.str, "MOD") == 0)
7194 new_token.code = '%';
7195
7196 else if (strcasecmp (new_token.str, "AND") == 0)
7197 new_token.code = '&';
7198
7199 else if (strcasecmp (new_token.str, "OR") == 0)
7200 new_token.code = '|';
7201
7202 else if (strcasecmp (new_token.str, "XOR") == 0)
7203 new_token.code = '^';
7204
7205 else if (strcasecmp (new_token.str, "SHL") == 0)
7206 new_token.code = T_SHL;
7207
7208 else if (strcasecmp (new_token.str, "SHR") == 0)
7209 new_token.code = T_SHR;
7210
7211 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 7212 new_token.code = T_BYTE;
7213
7214 else if (strcasecmp (new_token.str, "WORD") == 0)
7215 new_token.code = T_WORD;
7216
7217 else if (strcasecmp (new_token.str, "DWORD") == 0)
7218 new_token.code = T_DWORD;
7219
9306ca4a
JB		 7220 else if (strcasecmp (new_token.str, "FWORD") == 0)
7221 new_token.code = T_FWORD;
7222
64a0c779
DN		 7223 else if (strcasecmp (new_token.str, "QWORD") == 0)
7224 new_token.code = T_QWORD;
7225
9306ca4a
JB		 7226 else if (strcasecmp (new_token.str, "TBYTE") == 0
7227 /* XXX remove (gcc still uses it) */
7228 || strcasecmp (new_token.str, "XWORD") == 0)
7229 new_token.code = T_TBYTE;
7230
7231 else if (strcasecmp (new_token.str, "XMMWORD") == 0
7232 || strcasecmp (new_token.str, "OWORD") == 0)
7233 new_token.code = T_XMMWORD;
64a0c779
DN		 7234
7235 else if (strcasecmp (new_token.str, "PTR") == 0)
7236 new_token.code = T_PTR;
7237
7238 else if (strcasecmp (new_token.str, "SHORT") == 0)
7239 new_token.code = T_SHORT;
7240
7241 else if (strcasecmp (new_token.str, "OFFSET") == 0)
7242 {
7243 new_token.code = T_OFFSET;
7244
7245 /* ??? This is not mentioned in the MASM grammar but gcc
7246 makes use of it with -mintel-syntax. OFFSET may be
7247 followed by FLAT: */
7248 if (strncasecmp (q, " FLAT:", 6) == 0)
7249 strcat (new_token.str, " FLAT:");
7250 }
7251
7252 /* ??? This is not mentioned in the MASM grammar. */
7253 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 7254 {
7255 new_token.code = T_OFFSET;
7256 if (*q == ':')
7257 strcat (new_token.str, ":");
7258 else
7259 as_bad (_("`:' expected"));
7260 }
64a0c779
DN		 7261
7262 else
7263 new_token.code = T_ID;
7264 }
7265 }
7266
9306ca4a
JB		 7267 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
7268 {
7269 new_token.code = *intel_parser.op_string;
7270 new_token.str[0] = *intel_parser.op_string;
7271 new_token.str[1] = '\0';
7272 }
7273
7274 else if (strchr ("<>", *intel_parser.op_string)
7275 && *intel_parser.op_string == *(intel_parser.op_string + 1))
7276 {
7277 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
7278 new_token.str[0] = *intel_parser.op_string;
7279 new_token.str[1] = *intel_parser.op_string;
7280 new_token.str[2] = '\0';
7281 }
7282
64a0c779 7283 else
0477af35 7284 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 7285
7286 intel_parser.op_string += strlen (new_token.str);
7287 cur_token = new_token;
7288}
7289
64a0c779
DN		 7290/* Put cur_token back into the token stream and make cur_token point to
7291 prev_token. */
7292static void
7293intel_putback_token ()
7294{
a724f0f4
JB		 7295 if (cur_token.code != T_NIL)
7296 {
7297 intel_parser.op_string -= strlen (cur_token.str);
7298 free (cur_token.str);
7299 }
64a0c779 7300 cur_token = prev_token;
4a1805b1 7301
64a0c779
DN		 7302 /* Forget prev_token. */
7303 prev_token.code = T_NIL;
7304 prev_token.reg = NULL;
7305 prev_token.str = NULL;
7306}
54cfded0 7307
a4447b93 7308int
1df69f4f 7309tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 7310{
7311 unsigned int regnum;
7312 unsigned int regnames_count;
089dfecd 7313 static const char *const regnames_32[] =
54cfded0 7314 {
a4447b93
RH		 7315 "eax", "ecx", "edx", "ebx",
7316 "esp", "ebp", "esi", "edi",
089dfecd
JB		 7317 "eip", "eflags", NULL,
7318 "st0", "st1", "st2", "st3",
7319 "st4", "st5", "st6", "st7",
7320 NULL, NULL,
7321 "xmm0", "xmm1", "xmm2", "xmm3",
7322 "xmm4", "xmm5", "xmm6", "xmm7",
7323 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7324 "mm4", "mm5", "mm6", "mm7",
7325 "fcw", "fsw", "mxcsr",
7326 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7327 "tr", "ldtr"
54cfded0 7328 };
089dfecd 7329 static const char *const regnames_64[] =
54cfded0 7330 {
089dfecd
JB		 7331 "rax", "rdx", "rcx", "rbx",
7332 "rsi", "rdi", "rbp", "rsp",
7333 "r8", "r9", "r10", "r11",
54cfded0 7334 "r12", "r13", "r14", "r15",
089dfecd
JB		 7335 "rip",
7336 "xmm0", "xmm1", "xmm2", "xmm3",
7337 "xmm4", "xmm5", "xmm6", "xmm7",
7338 "xmm8", "xmm9", "xmm10", "xmm11",
7339 "xmm12", "xmm13", "xmm14", "xmm15",
7340 "st0", "st1", "st2", "st3",
7341 "st4", "st5", "st6", "st7",
7342 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 7343 "mm4", "mm5", "mm6", "mm7",
7344 "rflags",
7345 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
7346 "fs.base", "gs.base", NULL, NULL,
7347 "tr", "ldtr",
7348 "mxcsr", "fcw", "fsw"
54cfded0 7349 };
089dfecd 7350 const char *const *regnames;
54cfded0
AM		 7351
7352 if (flag_code == CODE_64BIT)
7353 {
7354 regnames = regnames_64;
0cea6190 7355 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 7356 }
7357 else
7358 {
7359 regnames = regnames_32;
0cea6190 7360 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 7361 }
7362
7363 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 7364 if (regnames[regnum] != NULL
7365 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 7366 return regnum;
7367
54cfded0
AM		 7368 return -1;
7369}
7370
7371void
7372tc_x86_frame_initial_instructions (void)
7373{
a4447b93
RH		 7374 static unsigned int sp_regno;
7375
7376 if (!sp_regno)
7377 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
7378 ? "rsp" : "esp");
7379
7380 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
7381 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 7382}
d2b2c203
DJ		 7383
7384int
7385i386_elf_section_type (const char *str, size_t len)
7386{
7387 if (flag_code == CODE_64BIT
7388 && len == sizeof ("unwind") - 1
7389 && strncmp (str, "unwind", 6) == 0)
7390 return SHT_X86_64_UNWIND;
7391
7392 return -1;
7393}
bb41ade5
AM		 7394
7395#ifdef TE_PE
7396void
7397tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
7398{
7399 expressionS expr;
7400
7401 expr.X_op = O_secrel;
7402 expr.X_add_symbol = symbol;
7403 expr.X_add_number = 0;
7404 emit_expr (&expr, size);
7405}
7406#endif
3b22753a
L		 7407
7408#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7409/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
7410
7411int
7412x86_64_section_letter (int letter, char **ptr_msg)
7413{
7414 if (flag_code == CODE_64BIT)
7415 {
7416 if (letter == 'l')
7417 return SHF_X86_64_LARGE;
7418
7419 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 7420 }
3b22753a 7421 else
64e74474 7422 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 7423 return -1;
7424}
7425
7426int
7427x86_64_section_word (char *str, size_t len)
7428{
7429 if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0)
7430 return SHF_X86_64_LARGE;
7431
7432 return -1;
7433}
7434
7435static void
7436handle_large_common (int small ATTRIBUTE_UNUSED)
7437{
7438 if (flag_code != CODE_64BIT)
7439 {
7440 s_comm_internal (0, elf_common_parse);
7441 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
7442 }
7443 else
7444 {
7445 static segT lbss_section;
7446 asection *saved_com_section_ptr = elf_com_section_ptr;
7447 asection *saved_bss_section = bss_section;
7448
7449 if (lbss_section == NULL)
7450 {
7451 flagword applicable;
7452 segT seg = now_seg;
7453 subsegT subseg = now_subseg;
7454
7455 /* The .lbss section is for local .largecomm symbols. */
7456 lbss_section = subseg_new (".lbss", 0);
7457 applicable = bfd_applicable_section_flags (stdoutput);
7458 bfd_set_section_flags (stdoutput, lbss_section,
7459 applicable & SEC_ALLOC);
7460 seg_info (lbss_section)->bss = 1;
7461
7462 subseg_set (seg, subseg);
7463 }
7464
7465 elf_com_section_ptr = &_bfd_elf_large_com_section;
7466 bss_section = lbss_section;
7467
7468 s_comm_internal (0, elf_common_parse);
7469
7470 elf_com_section_ptr = saved_com_section_ptr;
7471 bss_section = saved_bss_section;
7472 }
7473}
7474#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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