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b534c6d3 | 1 | /* tc-i386.c -- Assemble code for the Intel 80386 |
d87bef3a | 2 | Copyright (C) 1989-2023 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
19 | 02110-1301, USA. */ | |
252b5132 | 20 | |
47926f60 KH |
21 | /* Intel 80386 machine specific gas. |
22 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). | |
3e73aa7c | 23 | x86_64 support by Jan Hubicka (jh@suse.cz) |
0f10071e | 24 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
47926f60 KH |
25 | Bugs & suggestions are completely welcome. This is free software. |
26 | Please help us make it better. */ | |
252b5132 | 27 | |
252b5132 | 28 | #include "as.h" |
3882b010 | 29 | #include "safe-ctype.h" |
252b5132 | 30 | #include "subsegs.h" |
316e2c05 | 31 | #include "dwarf2dbg.h" |
54cfded0 | 32 | #include "dw2gencfi.h" |
b52c4ee4 IB |
33 | #include "gen-sframe.h" |
34 | #include "sframe.h" | |
d2b2c203 | 35 | #include "elf/x86-64.h" |
40fb9820 | 36 | #include "opcodes/i386-init.h" |
5c139202 | 37 | #include "opcodes/i386-mnem.h" |
41fd2579 | 38 | #include <limits.h> |
41fd2579 | 39 | |
c3332e24 | 40 | #ifndef INFER_ADDR_PREFIX |
eecb386c | 41 | #define INFER_ADDR_PREFIX 1 |
c3332e24 AM |
42 | #endif |
43 | ||
29b0f896 AM |
44 | #ifndef DEFAULT_ARCH |
45 | #define DEFAULT_ARCH "i386" | |
246fcdee | 46 | #endif |
252b5132 | 47 | |
edde18a5 AM |
48 | #ifndef INLINE |
49 | #if __GNUC__ >= 2 | |
50 | #define INLINE __inline__ | |
51 | #else | |
52 | #define INLINE | |
53 | #endif | |
54 | #endif | |
55 | ||
6305a203 L |
56 | /* Prefixes will be emitted in the order defined below. |
57 | WAIT_PREFIX must be the first prefix since FWAIT is really is an | |
58 | instruction, and so must come before any prefixes. | |
59 | The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX, | |
42164a71 | 60 | REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */ |
6305a203 L |
61 | #define WAIT_PREFIX 0 |
62 | #define SEG_PREFIX 1 | |
63 | #define ADDR_PREFIX 2 | |
64 | #define DATA_PREFIX 3 | |
c32fa91d | 65 | #define REP_PREFIX 4 |
42164a71 | 66 | #define HLE_PREFIX REP_PREFIX |
7e8b059b | 67 | #define BND_PREFIX REP_PREFIX |
c32fa91d | 68 | #define LOCK_PREFIX 5 |
4e9ac44a L |
69 | #define REX_PREFIX 6 /* must come last. */ |
70 | #define MAX_PREFIXES 7 /* max prefixes per opcode */ | |
6305a203 L |
71 | |
72 | /* we define the syntax here (modulo base,index,scale syntax) */ | |
73 | #define REGISTER_PREFIX '%' | |
74 | #define IMMEDIATE_PREFIX '$' | |
75 | #define ABSOLUTE_PREFIX '*' | |
76 | ||
77 | /* these are the instruction mnemonic suffixes in AT&T syntax or | |
78 | memory operand size in Intel syntax. */ | |
79 | #define WORD_MNEM_SUFFIX 'w' | |
80 | #define BYTE_MNEM_SUFFIX 'b' | |
81 | #define SHORT_MNEM_SUFFIX 's' | |
82 | #define LONG_MNEM_SUFFIX 'l' | |
83 | #define QWORD_MNEM_SUFFIX 'q' | |
6305a203 L |
84 | |
85 | #define END_OF_INSN '\0' | |
86 | ||
05909f23 JB |
87 | #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } } |
88 | ||
79dec6b7 JB |
89 | /* This matches the C -> StaticRounding alias in the opcode table. */ |
90 | #define commutative staticrounding | |
91 | ||
6305a203 L |
92 | /* |
93 | 'templates' is for grouping together 'template' structures for opcodes | |
94 | of the same name. This is only used for storing the insns in the grand | |
95 | ole hash table of insns. | |
96 | The templates themselves start at START and range up to (but not including) | |
97 | END. | |
98 | */ | |
99 | typedef struct | |
100 | { | |
d3ce72d0 NC |
101 | const insn_template *start; |
102 | const insn_template *end; | |
6305a203 L |
103 | } |
104 | templates; | |
105 | ||
106 | /* 386 operand encoding bytes: see 386 book for details of this. */ | |
107 | typedef struct | |
108 | { | |
109 | unsigned int regmem; /* codes register or memory operand */ | |
110 | unsigned int reg; /* codes register operand (or extended opcode) */ | |
111 | unsigned int mode; /* how to interpret regmem & reg */ | |
112 | } | |
113 | modrm_byte; | |
114 | ||
115 | /* x86-64 extension prefix. */ | |
116 | typedef int rex_byte; | |
117 | ||
6305a203 L |
118 | /* 386 opcode byte to code indirect addressing. */ |
119 | typedef struct | |
120 | { | |
121 | unsigned base; | |
122 | unsigned index; | |
123 | unsigned scale; | |
124 | } | |
125 | sib_byte; | |
126 | ||
6305a203 L |
127 | /* x86 arch names, types and features */ |
128 | typedef struct | |
129 | { | |
130 | const char *name; /* arch name */ | |
6ceeed25 JB |
131 | unsigned int len:8; /* arch string length */ |
132 | bool skip:1; /* show_arch should skip this. */ | |
6305a203 | 133 | enum processor_type type; /* arch type */ |
4fc85f37 | 134 | enum { vsz_none, vsz_set, vsz_reset } vsz; /* vector size control */ |
ae89daec JB |
135 | i386_cpu_flags enable; /* cpu feature enable flags */ |
136 | i386_cpu_flags disable; /* cpu feature disable flags */ | |
6305a203 L |
137 | } |
138 | arch_entry; | |
139 | ||
78f12dd3 | 140 | static void update_code_flag (int, int); |
edd67638 | 141 | static void s_insn (int); |
e3bb37b5 L |
142 | static void set_code_flag (int); |
143 | static void set_16bit_gcc_code_flag (int); | |
144 | static void set_intel_syntax (int); | |
1efbbeb4 | 145 | static void set_intel_mnemonic (int); |
db51cc60 | 146 | static void set_allow_index_reg (int); |
7bab8ab5 | 147 | static void set_check (int); |
e3bb37b5 | 148 | static void set_cpu_arch (int); |
6482c264 | 149 | #ifdef TE_PE |
e3bb37b5 | 150 | static void pe_directive_secrel (int); |
145667f8 | 151 | static void pe_directive_secidx (int); |
6482c264 | 152 | #endif |
e3bb37b5 L |
153 | static void signed_cons (int); |
154 | static char *output_invalid (int c); | |
ee86248c JB |
155 | static int i386_finalize_immediate (segT, expressionS *, i386_operand_type, |
156 | const char *); | |
157 | static int i386_finalize_displacement (segT, expressionS *, i386_operand_type, | |
158 | const char *); | |
a7619375 | 159 | static int i386_att_operand (char *); |
e3bb37b5 | 160 | static int i386_intel_operand (char *, int); |
ee86248c JB |
161 | static int i386_intel_simplify (expressionS *); |
162 | static int i386_intel_parse_name (const char *, expressionS *); | |
4f081312 | 163 | static const reg_entry *parse_register (const char *, char **); |
edd67638 | 164 | static const char *parse_insn (const char *, char *, bool); |
e3bb37b5 L |
165 | static char *parse_operands (char *, const char *); |
166 | static void swap_operands (void); | |
783c187b | 167 | static void swap_2_operands (unsigned int, unsigned int); |
48bcea9f | 168 | static enum flag_code i386_addressing_mode (void); |
e3bb37b5 | 169 | static void optimize_imm (void); |
0de704b9 | 170 | static bool optimize_disp (const insn_template *t); |
83b16ac6 | 171 | static const insn_template *match_template (char); |
e3bb37b5 L |
172 | static int check_string (void); |
173 | static int process_suffix (void); | |
174 | static int check_byte_reg (void); | |
175 | static int check_long_reg (void); | |
176 | static int check_qword_reg (void); | |
177 | static int check_word_reg (void); | |
178 | static int finalize_imm (void); | |
179 | static int process_operands (void); | |
5e042380 | 180 | static const reg_entry *build_modrm_byte (void); |
e3bb37b5 L |
181 | static void output_insn (void); |
182 | static void output_imm (fragS *, offsetT); | |
183 | static void output_disp (fragS *, offsetT); | |
29b0f896 | 184 | #ifndef I386COFF |
e3bb37b5 | 185 | static void s_bss (int); |
252b5132 | 186 | #endif |
17d4e2a2 L |
187 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
188 | static void handle_large_common (int small ATTRIBUTE_UNUSED); | |
b4a3a7b4 L |
189 | |
190 | /* GNU_PROPERTY_X86_ISA_1_USED. */ | |
191 | static unsigned int x86_isa_1_used; | |
192 | /* GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
193 | static unsigned int x86_feature_2_used; | |
194 | /* Generate x86 used ISA and feature properties. */ | |
195 | static unsigned int x86_used_note = DEFAULT_X86_USED_NOTE; | |
17d4e2a2 | 196 | #endif |
252b5132 | 197 | |
a847613f | 198 | static const char *default_arch = DEFAULT_ARCH; |
3e73aa7c | 199 | |
8a6fb3f9 JB |
200 | /* parse_register() returns this when a register alias cannot be used. */ |
201 | static const reg_entry bad_reg = { "<bad>", OPERAND_TYPE_NONE, 0, 0, | |
202 | { Dw2Inval, Dw2Inval } }; | |
203 | ||
34684862 | 204 | static const reg_entry *reg_eax; |
5e042380 JB |
205 | static const reg_entry *reg_ds; |
206 | static const reg_entry *reg_es; | |
207 | static const reg_entry *reg_ss; | |
6288d05f | 208 | static const reg_entry *reg_st0; |
6225c532 JB |
209 | static const reg_entry *reg_k0; |
210 | ||
c0f3af97 L |
211 | /* VEX prefix. */ |
212 | typedef struct | |
213 | { | |
43234a1e L |
214 | /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */ |
215 | unsigned char bytes[4]; | |
c0f3af97 L |
216 | unsigned int length; |
217 | /* Destination or source register specifier. */ | |
218 | const reg_entry *register_specifier; | |
219 | } vex_prefix; | |
220 | ||
252b5132 | 221 | /* 'md_assemble ()' gathers together information and puts it into a |
47926f60 | 222 | i386_insn. */ |
252b5132 | 223 | |
520dc8e8 AM |
224 | union i386_op |
225 | { | |
226 | expressionS *disps; | |
227 | expressionS *imms; | |
228 | const reg_entry *regs; | |
229 | }; | |
230 | ||
a65babc9 L |
231 | enum i386_error |
232 | { | |
b4d65f2d | 233 | no_error, /* Must be first. */ |
86e026a4 | 234 | operand_size_mismatch, |
a65babc9 L |
235 | operand_type_mismatch, |
236 | register_type_mismatch, | |
237 | number_of_operands_mismatch, | |
238 | invalid_instruction_suffix, | |
239 | bad_imm4, | |
a65babc9 L |
240 | unsupported_with_intel_mnemonic, |
241 | unsupported_syntax, | |
6c30d220 | 242 | unsupported, |
9db83a32 JB |
243 | unsupported_on_arch, |
244 | unsupported_64bit, | |
260cd341 | 245 | invalid_sib_address, |
6c30d220 | 246 | invalid_vsib_address, |
7bab8ab5 | 247 | invalid_vector_register_set, |
260cd341 | 248 | invalid_tmm_register_set, |
0cc78721 | 249 | invalid_dest_and_src_register_set, |
43234a1e L |
250 | unsupported_vector_index_register, |
251 | unsupported_broadcast, | |
43234a1e L |
252 | broadcast_needed, |
253 | unsupported_masking, | |
254 | mask_not_on_destination, | |
255 | no_default_mask, | |
256 | unsupported_rc_sae, | |
43234a1e | 257 | invalid_register_operand, |
a65babc9 L |
258 | }; |
259 | ||
252b5132 RH |
260 | struct _i386_insn |
261 | { | |
47926f60 | 262 | /* TM holds the template for the insn were currently assembling. */ |
d3ce72d0 | 263 | insn_template tm; |
252b5132 | 264 | |
7d5e4556 L |
265 | /* SUFFIX holds the instruction size suffix for byte, word, dword |
266 | or qword, if given. */ | |
252b5132 RH |
267 | char suffix; |
268 | ||
9a182d04 JB |
269 | /* OPCODE_LENGTH holds the number of base opcode bytes. */ |
270 | unsigned char opcode_length; | |
271 | ||
47926f60 | 272 | /* OPERANDS gives the number of given operands. */ |
252b5132 RH |
273 | unsigned int operands; |
274 | ||
275 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number | |
276 | of given register, displacement, memory operands and immediate | |
47926f60 | 277 | operands. */ |
252b5132 RH |
278 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
279 | ||
280 | /* TYPES [i] is the type (see above #defines) which tells us how to | |
520dc8e8 | 281 | use OP[i] for the corresponding operand. */ |
40fb9820 | 282 | i386_operand_type types[MAX_OPERANDS]; |
252b5132 | 283 | |
520dc8e8 AM |
284 | /* Displacement expression, immediate expression, or register for each |
285 | operand. */ | |
286 | union i386_op op[MAX_OPERANDS]; | |
252b5132 | 287 | |
3e73aa7c JH |
288 | /* Flags for operands. */ |
289 | unsigned int flags[MAX_OPERANDS]; | |
290 | #define Operand_PCrel 1 | |
c48dadc9 | 291 | #define Operand_Mem 2 |
c032bc4f | 292 | #define Operand_Signed 4 /* .insn only */ |
3e73aa7c | 293 | |
252b5132 | 294 | /* Relocation type for operand */ |
f86103b7 | 295 | enum bfd_reloc_code_real reloc[MAX_OPERANDS]; |
252b5132 | 296 | |
252b5132 RH |
297 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
298 | the base index byte below. */ | |
299 | const reg_entry *base_reg; | |
300 | const reg_entry *index_reg; | |
301 | unsigned int log2_scale_factor; | |
302 | ||
303 | /* SEG gives the seg_entries of this insn. They are zero unless | |
47926f60 | 304 | explicit segment overrides are given. */ |
5e042380 | 305 | const reg_entry *seg[2]; |
252b5132 RH |
306 | |
307 | /* PREFIX holds all the given prefix opcodes (usually null). | |
308 | PREFIXES is the number of prefix opcodes. */ | |
309 | unsigned int prefixes; | |
310 | unsigned char prefix[MAX_PREFIXES]; | |
311 | ||
d0c2e3ec JB |
312 | /* .insn allows for reserved opcode spaces. */ |
313 | unsigned char insn_opcode_space; | |
314 | ||
c032bc4f JB |
315 | /* .insn also allows (requires) specifying immediate size. */ |
316 | unsigned char imm_bits[MAX_OPERANDS]; | |
317 | ||
50128d0c | 318 | /* Register is in low 3 bits of opcode. */ |
5b7c81bd | 319 | bool short_form; |
50128d0c | 320 | |
6f2f06be | 321 | /* The operand to a branch insn indicates an absolute branch. */ |
5b7c81bd | 322 | bool jumpabsolute; |
6f2f06be | 323 | |
a4d3acd2 JB |
324 | /* The operand to a branch insn indicates a far branch. */ |
325 | bool far_branch; | |
326 | ||
9373f275 L |
327 | /* There is a memory operand of (%dx) which should be only used |
328 | with input/output instructions. */ | |
329 | bool input_output_operand; | |
330 | ||
921eafea L |
331 | /* Extended states. */ |
332 | enum | |
333 | { | |
334 | /* Use MMX state. */ | |
335 | xstate_mmx = 1 << 0, | |
336 | /* Use XMM state. */ | |
337 | xstate_xmm = 1 << 1, | |
338 | /* Use YMM state. */ | |
339 | xstate_ymm = 1 << 2 | xstate_xmm, | |
340 | /* Use ZMM state. */ | |
341 | xstate_zmm = 1 << 3 | xstate_ymm, | |
342 | /* Use TMM state. */ | |
32930e4e L |
343 | xstate_tmm = 1 << 4, |
344 | /* Use MASK state. */ | |
345 | xstate_mask = 1 << 5 | |
921eafea | 346 | } xstate; |
260cd341 | 347 | |
e379e5f3 | 348 | /* Has GOTPC or TLS relocation. */ |
5b7c81bd | 349 | bool has_gotpc_tls_reloc; |
e379e5f3 | 350 | |
252b5132 | 351 | /* RM and SIB are the modrm byte and the sib byte where the |
c1e679ec | 352 | addressing modes of this insn are encoded. */ |
252b5132 | 353 | modrm_byte rm; |
3e73aa7c | 354 | rex_byte rex; |
43234a1e | 355 | rex_byte vrex; |
252b5132 | 356 | sib_byte sib; |
c0f3af97 | 357 | vex_prefix vex; |
b6169b20 | 358 | |
6225c532 JB |
359 | /* Masking attributes. |
360 | ||
361 | The struct describes masking, applied to OPERAND in the instruction. | |
362 | REG is a pointer to the corresponding mask register. ZEROING tells | |
363 | whether merging or zeroing mask is used. */ | |
364 | struct Mask_Operation | |
365 | { | |
366 | const reg_entry *reg; | |
367 | unsigned int zeroing; | |
368 | /* The operand where this operation is associated. */ | |
369 | unsigned int operand; | |
370 | } mask; | |
43234a1e L |
371 | |
372 | /* Rounding control and SAE attributes. */ | |
ca5312a2 JB |
373 | struct RC_Operation |
374 | { | |
375 | enum rc_type | |
376 | { | |
377 | rc_none = -1, | |
378 | rne, | |
379 | rd, | |
380 | ru, | |
381 | rz, | |
382 | saeonly | |
383 | } type; | |
7063667e JB |
384 | /* In Intel syntax the operand modifier form is supposed to be used, but |
385 | we continue to accept the immediate forms as well. */ | |
386 | bool modifier; | |
ca5312a2 | 387 | } rounding; |
43234a1e | 388 | |
5273a3cd JB |
389 | /* Broadcasting attributes. |
390 | ||
391 | The struct describes broadcasting, applied to OPERAND. TYPE is | |
392 | expresses the broadcast factor. */ | |
393 | struct Broadcast_Operation | |
394 | { | |
0cc78721 | 395 | /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */ |
5273a3cd JB |
396 | unsigned int type; |
397 | ||
398 | /* Index of broadcasted operand. */ | |
399 | unsigned int operand; | |
400 | ||
401 | /* Number of bytes to broadcast. */ | |
402 | unsigned int bytes; | |
403 | } broadcast; | |
43234a1e L |
404 | |
405 | /* Compressed disp8*N attribute. */ | |
406 | unsigned int memshift; | |
407 | ||
86fa6981 L |
408 | /* Prefer load or store in encoding. */ |
409 | enum | |
410 | { | |
411 | dir_encoding_default = 0, | |
412 | dir_encoding_load, | |
64c49ab3 JB |
413 | dir_encoding_store, |
414 | dir_encoding_swap | |
86fa6981 | 415 | } dir_encoding; |
891edac4 | 416 | |
41eb8e88 | 417 | /* Prefer 8bit, 16bit, 32bit displacement in encoding. */ |
a501d77e L |
418 | enum |
419 | { | |
420 | disp_encoding_default = 0, | |
421 | disp_encoding_8bit, | |
41eb8e88 | 422 | disp_encoding_16bit, |
a501d77e L |
423 | disp_encoding_32bit |
424 | } disp_encoding; | |
f8a5c266 | 425 | |
6b6b6807 | 426 | /* Prefer the REX byte in encoding. */ |
5b7c81bd | 427 | bool rex_encoding; |
6b6b6807 | 428 | |
b6f8c7c4 | 429 | /* Disable instruction size optimization. */ |
5b7c81bd | 430 | bool no_optimize; |
b6f8c7c4 | 431 | |
86fa6981 L |
432 | /* How to encode vector instructions. */ |
433 | enum | |
434 | { | |
435 | vex_encoding_default = 0, | |
42e04b36 | 436 | vex_encoding_vex, |
86fa6981 | 437 | vex_encoding_vex3, |
da4977e0 JB |
438 | vex_encoding_evex, |
439 | vex_encoding_error | |
86fa6981 L |
440 | } vec_encoding; |
441 | ||
d5de92cf L |
442 | /* REP prefix. */ |
443 | const char *rep_prefix; | |
444 | ||
165de32a L |
445 | /* HLE prefix. */ |
446 | const char *hle_prefix; | |
42164a71 | 447 | |
7e8b059b L |
448 | /* Have BND prefix. */ |
449 | const char *bnd_prefix; | |
450 | ||
04ef582a L |
451 | /* Have NOTRACK prefix. */ |
452 | const char *notrack_prefix; | |
453 | ||
891edac4 | 454 | /* Error message. */ |
a65babc9 | 455 | enum i386_error error; |
252b5132 RH |
456 | }; |
457 | ||
458 | typedef struct _i386_insn i386_insn; | |
459 | ||
43234a1e L |
460 | /* Link RC type with corresponding string, that'll be looked for in |
461 | asm. */ | |
462 | struct RC_name | |
463 | { | |
464 | enum rc_type type; | |
465 | const char *name; | |
466 | unsigned int len; | |
467 | }; | |
468 | ||
469 | static const struct RC_name RC_NamesTable[] = | |
470 | { | |
471 | { rne, STRING_COMMA_LEN ("rn-sae") }, | |
472 | { rd, STRING_COMMA_LEN ("rd-sae") }, | |
473 | { ru, STRING_COMMA_LEN ("ru-sae") }, | |
474 | { rz, STRING_COMMA_LEN ("rz-sae") }, | |
475 | { saeonly, STRING_COMMA_LEN ("sae") }, | |
476 | }; | |
477 | ||
3bfea8ba L |
478 | /* To be indexed by segment register number. */ |
479 | static const unsigned char i386_seg_prefixes[] = { | |
480 | ES_PREFIX_OPCODE, | |
481 | CS_PREFIX_OPCODE, | |
482 | SS_PREFIX_OPCODE, | |
483 | DS_PREFIX_OPCODE, | |
484 | FS_PREFIX_OPCODE, | |
485 | GS_PREFIX_OPCODE | |
486 | }; | |
487 | ||
252b5132 RH |
488 | /* List of chars besides those in app.c:symbol_chars that can start an |
489 | operand. Used to prevent the scrubber eating vital white-space. */ | |
86fa6981 | 490 | const char extra_symbol_chars[] = "*%-([{}" |
252b5132 | 491 | #ifdef LEX_AT |
32137342 NC |
492 | "@" |
493 | #endif | |
494 | #ifdef LEX_QM | |
495 | "?" | |
252b5132 | 496 | #endif |
32137342 | 497 | ; |
252b5132 | 498 | |
b3983e5f JB |
499 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
500 | && !defined (TE_GNU) \ | |
501 | && !defined (TE_LINUX) \ | |
d85e70a3 | 502 | && !defined (TE_Haiku) \ |
b3983e5f JB |
503 | && !defined (TE_FreeBSD) \ |
504 | && !defined (TE_DragonFly) \ | |
505 | && !defined (TE_NetBSD)) | |
252b5132 | 506 | /* This array holds the chars that always start a comment. If the |
b3b91714 AM |
507 | pre-processor is disabled, these aren't very useful. The option |
508 | --divide will remove '/' from this list. */ | |
509 | const char *i386_comment_chars = "#/"; | |
510 | #define SVR4_COMMENT_CHARS 1 | |
252b5132 | 511 | #define PREFIX_SEPARATOR '\\' |
252b5132 | 512 | |
b3b91714 AM |
513 | #else |
514 | const char *i386_comment_chars = "#"; | |
515 | #define PREFIX_SEPARATOR '/' | |
516 | #endif | |
517 | ||
252b5132 RH |
518 | /* This array holds the chars that only start a comment at the beginning of |
519 | a line. If the line seems to have the form '# 123 filename' | |
ce8a8b2f AM |
520 | .line and .file directives will appear in the pre-processed output. |
521 | Note that input_file.c hand checks for '#' at the beginning of the | |
252b5132 | 522 | first line of the input file. This is because the compiler outputs |
ce8a8b2f AM |
523 | #NO_APP at the beginning of its output. |
524 | Also note that comments started like this one will always work if | |
252b5132 | 525 | '/' isn't otherwise defined. */ |
b3b91714 | 526 | const char line_comment_chars[] = "#/"; |
252b5132 | 527 | |
63a0b638 | 528 | const char line_separator_chars[] = ";"; |
252b5132 | 529 | |
ce8a8b2f AM |
530 | /* Chars that can be used to separate mant from exp in floating point |
531 | nums. */ | |
252b5132 RH |
532 | const char EXP_CHARS[] = "eE"; |
533 | ||
ce8a8b2f AM |
534 | /* Chars that mean this number is a floating point constant |
535 | As in 0f12.456 | |
536 | or 0d1.2345e12. */ | |
de133cf9 | 537 | const char FLT_CHARS[] = "fFdDxXhHbB"; |
252b5132 | 538 | |
ce8a8b2f | 539 | /* Tables for lexical analysis. */ |
252b5132 RH |
540 | static char mnemonic_chars[256]; |
541 | static char register_chars[256]; | |
542 | static char operand_chars[256]; | |
252b5132 | 543 | |
ce8a8b2f | 544 | /* Lexical macros. */ |
252b5132 RH |
545 | #define is_operand_char(x) (operand_chars[(unsigned char) x]) |
546 | #define is_register_char(x) (register_chars[(unsigned char) x]) | |
547 | #define is_space_char(x) ((x) == ' ') | |
252b5132 | 548 | |
d2b1a14d JB |
549 | /* All non-digit non-letter characters that may occur in an operand and |
550 | which aren't already in extra_symbol_chars[]. */ | |
551 | static const char operand_special_chars[] = "$+,)._~/<>|&^!=:@]"; | |
252b5132 RH |
552 | |
553 | /* md_assemble() always leaves the strings it's passed unaltered. To | |
554 | effect this we maintain a stack of saved characters that we've smashed | |
555 | with '\0's (indicating end of strings for various sub-fields of the | |
47926f60 | 556 | assembler instruction). */ |
252b5132 | 557 | static char save_stack[32]; |
ce8a8b2f | 558 | static char *save_stack_p; |
252b5132 RH |
559 | #define END_STRING_AND_SAVE(s) \ |
560 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) | |
561 | #define RESTORE_END_STRING(s) \ | |
562 | do { *(s) = *--save_stack_p; } while (0) | |
563 | ||
47926f60 | 564 | /* The instruction we're assembling. */ |
252b5132 RH |
565 | static i386_insn i; |
566 | ||
567 | /* Possible templates for current insn. */ | |
568 | static const templates *current_templates; | |
569 | ||
31b2323c L |
570 | /* Per instruction expressionS buffers: max displacements & immediates. */ |
571 | static expressionS disp_expressions[MAX_MEMORY_OPERANDS]; | |
572 | static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS]; | |
252b5132 | 573 | |
47926f60 | 574 | /* Current operand we are working on. */ |
ee86248c | 575 | static int this_operand = -1; |
252b5132 | 576 | |
d0c2e3ec JB |
577 | /* Are we processing a .insn directive? */ |
578 | #define dot_insn() (i.tm.mnem_off == MN__insn) | |
579 | ||
3e73aa7c JH |
580 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
581 | these. */ | |
582 | ||
583 | enum flag_code { | |
584 | CODE_32BIT, | |
585 | CODE_16BIT, | |
586 | CODE_64BIT }; | |
587 | ||
588 | static enum flag_code flag_code; | |
4fa24527 | 589 | static unsigned int object_64bit; |
862be3fb | 590 | static unsigned int disallow_64bit_reloc; |
3e73aa7c | 591 | static int use_rela_relocations = 0; |
e379e5f3 L |
592 | /* __tls_get_addr/___tls_get_addr symbol for TLS. */ |
593 | static const char *tls_get_addr; | |
3e73aa7c | 594 | |
7af8ed2d NC |
595 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
596 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ | |
597 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) | |
598 | ||
351f65ca L |
599 | /* The ELF ABI to use. */ |
600 | enum x86_elf_abi | |
601 | { | |
602 | I386_ABI, | |
7f56bc95 L |
603 | X86_64_ABI, |
604 | X86_64_X32_ABI | |
351f65ca L |
605 | }; |
606 | ||
607 | static enum x86_elf_abi x86_elf_abi = I386_ABI; | |
7af8ed2d | 608 | #endif |
351f65ca | 609 | |
167ad85b TG |
610 | #if defined (TE_PE) || defined (TE_PEP) |
611 | /* Use big object file format. */ | |
612 | static int use_big_obj = 0; | |
613 | #endif | |
614 | ||
8dcea932 L |
615 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
616 | /* 1 if generating code for a shared library. */ | |
617 | static int shared = 0; | |
b52c4ee4 IB |
618 | |
619 | unsigned int x86_sframe_cfa_sp_reg; | |
3e3e792a | 620 | /* The other CFA base register for SFrame stack trace info. */ |
b52c4ee4 IB |
621 | unsigned int x86_sframe_cfa_fp_reg; |
622 | unsigned int x86_sframe_cfa_ra_reg; | |
623 | ||
8dcea932 L |
624 | #endif |
625 | ||
47926f60 KH |
626 | /* 1 for intel syntax, |
627 | 0 if att syntax. */ | |
628 | static int intel_syntax = 0; | |
252b5132 | 629 | |
4b5aaf5f L |
630 | static enum x86_64_isa |
631 | { | |
632 | amd64 = 1, /* AMD64 ISA. */ | |
633 | intel64 /* Intel64 ISA. */ | |
634 | } isa64; | |
e89c5eaa | 635 | |
1efbbeb4 L |
636 | /* 1 for intel mnemonic, |
637 | 0 if att mnemonic. */ | |
638 | static int intel_mnemonic = !SYSV386_COMPAT; | |
639 | ||
a60de03c JB |
640 | /* 1 if pseudo registers are permitted. */ |
641 | static int allow_pseudo_reg = 0; | |
642 | ||
47926f60 KH |
643 | /* 1 if register prefix % not required. */ |
644 | static int allow_naked_reg = 0; | |
252b5132 | 645 | |
33eaf5de | 646 | /* 1 if the assembler should add BND prefix for all control-transferring |
7e8b059b L |
647 | instructions supporting it, even if this prefix wasn't specified |
648 | explicitly. */ | |
649 | static int add_bnd_prefix = 0; | |
650 | ||
ba104c83 | 651 | /* 1 if pseudo index register, eiz/riz, is allowed . */ |
db51cc60 L |
652 | static int allow_index_reg = 0; |
653 | ||
d022bddd IT |
654 | /* 1 if the assembler should ignore LOCK prefix, even if it was |
655 | specified explicitly. */ | |
656 | static int omit_lock_prefix = 0; | |
657 | ||
e4e00185 AS |
658 | /* 1 if the assembler should encode lfence, mfence, and sfence as |
659 | "lock addl $0, (%{re}sp)". */ | |
660 | static int avoid_fence = 0; | |
661 | ||
ae531041 L |
662 | /* 1 if lfence should be inserted after every load. */ |
663 | static int lfence_after_load = 0; | |
664 | ||
665 | /* Non-zero if lfence should be inserted before indirect branch. */ | |
666 | static enum lfence_before_indirect_branch_kind | |
667 | { | |
668 | lfence_branch_none = 0, | |
669 | lfence_branch_register, | |
670 | lfence_branch_memory, | |
671 | lfence_branch_all | |
672 | } | |
673 | lfence_before_indirect_branch; | |
674 | ||
675 | /* Non-zero if lfence should be inserted before ret. */ | |
676 | static enum lfence_before_ret_kind | |
677 | { | |
678 | lfence_before_ret_none = 0, | |
679 | lfence_before_ret_not, | |
a09f656b | 680 | lfence_before_ret_or, |
681 | lfence_before_ret_shl | |
ae531041 L |
682 | } |
683 | lfence_before_ret; | |
684 | ||
685 | /* Types of previous instruction is .byte or prefix. */ | |
e379e5f3 L |
686 | static struct |
687 | { | |
688 | segT seg; | |
689 | const char *file; | |
690 | const char *name; | |
691 | unsigned int line; | |
692 | enum last_insn_kind | |
693 | { | |
694 | last_insn_other = 0, | |
695 | last_insn_directive, | |
696 | last_insn_prefix | |
697 | } kind; | |
698 | } last_insn; | |
699 | ||
0cb4071e L |
700 | /* 1 if the assembler should generate relax relocations. */ |
701 | ||
702 | static int generate_relax_relocations | |
703 | = DEFAULT_GENERATE_X86_RELAX_RELOCATIONS; | |
704 | ||
7bab8ab5 | 705 | static enum check_kind |
daf50ae7 | 706 | { |
7bab8ab5 JB |
707 | check_none = 0, |
708 | check_warning, | |
709 | check_error | |
daf50ae7 | 710 | } |
7bab8ab5 | 711 | sse_check, operand_check = check_warning; |
daf50ae7 | 712 | |
e379e5f3 L |
713 | /* Non-zero if branches should be aligned within power of 2 boundary. */ |
714 | static int align_branch_power = 0; | |
715 | ||
716 | /* Types of branches to align. */ | |
717 | enum align_branch_kind | |
718 | { | |
719 | align_branch_none = 0, | |
720 | align_branch_jcc = 1, | |
721 | align_branch_fused = 2, | |
722 | align_branch_jmp = 3, | |
723 | align_branch_call = 4, | |
724 | align_branch_indirect = 5, | |
725 | align_branch_ret = 6 | |
726 | }; | |
727 | ||
728 | /* Type bits of branches to align. */ | |
729 | enum align_branch_bit | |
730 | { | |
731 | align_branch_jcc_bit = 1 << align_branch_jcc, | |
732 | align_branch_fused_bit = 1 << align_branch_fused, | |
733 | align_branch_jmp_bit = 1 << align_branch_jmp, | |
734 | align_branch_call_bit = 1 << align_branch_call, | |
735 | align_branch_indirect_bit = 1 << align_branch_indirect, | |
736 | align_branch_ret_bit = 1 << align_branch_ret | |
737 | }; | |
738 | ||
739 | static unsigned int align_branch = (align_branch_jcc_bit | |
740 | | align_branch_fused_bit | |
741 | | align_branch_jmp_bit); | |
742 | ||
79d72f45 HL |
743 | /* Types of condition jump used by macro-fusion. */ |
744 | enum mf_jcc_kind | |
745 | { | |
746 | mf_jcc_jo = 0, /* base opcode 0x70 */ | |
747 | mf_jcc_jc, /* base opcode 0x72 */ | |
748 | mf_jcc_je, /* base opcode 0x74 */ | |
749 | mf_jcc_jna, /* base opcode 0x76 */ | |
750 | mf_jcc_js, /* base opcode 0x78 */ | |
751 | mf_jcc_jp, /* base opcode 0x7a */ | |
752 | mf_jcc_jl, /* base opcode 0x7c */ | |
753 | mf_jcc_jle, /* base opcode 0x7e */ | |
754 | }; | |
755 | ||
756 | /* Types of compare flag-modifying insntructions used by macro-fusion. */ | |
757 | enum mf_cmp_kind | |
758 | { | |
759 | mf_cmp_test_and, /* test/cmp */ | |
760 | mf_cmp_alu_cmp, /* add/sub/cmp */ | |
761 | mf_cmp_incdec /* inc/dec */ | |
762 | }; | |
763 | ||
e379e5f3 L |
764 | /* The maximum padding size for fused jcc. CMP like instruction can |
765 | be 9 bytes and jcc can be 6 bytes. Leave room just in case for | |
766 | prefixes. */ | |
767 | #define MAX_FUSED_JCC_PADDING_SIZE 20 | |
768 | ||
769 | /* The maximum number of prefixes added for an instruction. */ | |
770 | static unsigned int align_branch_prefix_size = 5; | |
771 | ||
b6f8c7c4 L |
772 | /* Optimization: |
773 | 1. Clear the REX_W bit with register operand if possible. | |
774 | 2. Above plus use 128bit vector instruction to clear the full vector | |
775 | register. | |
776 | */ | |
777 | static int optimize = 0; | |
778 | ||
779 | /* Optimization: | |
780 | 1. Clear the REX_W bit with register operand if possible. | |
781 | 2. Above plus use 128bit vector instruction to clear the full vector | |
782 | register. | |
783 | 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to | |
784 | "testb $imm7,%r8". | |
785 | */ | |
786 | static int optimize_for_space = 0; | |
787 | ||
2ca3ace5 L |
788 | /* Register prefix used for error message. */ |
789 | static const char *register_prefix = "%"; | |
790 | ||
47926f60 KH |
791 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
792 | leave, push, and pop instructions so that gcc has the same stack | |
793 | frame as in 32 bit mode. */ | |
794 | static char stackop_size = '\0'; | |
eecb386c | 795 | |
12b55ccc L |
796 | /* Non-zero to optimize code alignment. */ |
797 | int optimize_align_code = 1; | |
798 | ||
47926f60 KH |
799 | /* Non-zero to quieten some warnings. */ |
800 | static int quiet_warnings = 0; | |
a38cf1db | 801 | |
d59a54c2 JB |
802 | /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */ |
803 | static bool pre_386_16bit_warned; | |
804 | ||
47926f60 KH |
805 | /* CPU name. */ |
806 | static const char *cpu_arch_name = NULL; | |
6305a203 | 807 | static char *cpu_sub_arch_name = NULL; |
a38cf1db | 808 | |
47926f60 | 809 | /* CPU feature flags. */ |
40fb9820 L |
810 | static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS; |
811 | ||
ccc9c027 L |
812 | /* If we have selected a cpu we are generating instructions for. */ |
813 | static int cpu_arch_tune_set = 0; | |
814 | ||
9103f4f4 | 815 | /* Cpu we are generating instructions for. */ |
fbf3f584 | 816 | enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN; |
9103f4f4 L |
817 | |
818 | /* CPU feature flags of cpu we are generating instructions for. */ | |
40fb9820 | 819 | static i386_cpu_flags cpu_arch_tune_flags; |
9103f4f4 | 820 | |
ccc9c027 | 821 | /* CPU instruction set architecture used. */ |
fbf3f584 | 822 | enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN; |
ccc9c027 | 823 | |
9103f4f4 | 824 | /* CPU feature flags of instruction set architecture used. */ |
fbf3f584 | 825 | i386_cpu_flags cpu_arch_isa_flags; |
9103f4f4 | 826 | |
fddf5b5b AM |
827 | /* If set, conditional jumps are not automatically promoted to handle |
828 | larger than a byte offset. */ | |
f68697e8 | 829 | static bool no_cond_jump_promotion = false; |
fddf5b5b | 830 | |
5cc00775 JB |
831 | /* This will be set from an expression parser hook if there's any |
832 | applicable operator involved in an expression. */ | |
833 | static enum { | |
834 | expr_operator_none, | |
835 | expr_operator_present, | |
836 | expr_large_value, | |
837 | } expr_mode; | |
838 | ||
c0f3af97 L |
839 | /* Encode SSE instructions with VEX prefix. */ |
840 | static unsigned int sse2avx; | |
841 | ||
c8480b58 L |
842 | /* Encode aligned vector move as unaligned vector move. */ |
843 | static unsigned int use_unaligned_vector_move; | |
844 | ||
4fc85f37 JB |
845 | /* Maximum permitted vector size. */ |
846 | #define VSZ_DEFAULT VSZ512 | |
847 | static unsigned int vector_size = VSZ_DEFAULT; | |
848 | ||
539f890d L |
849 | /* Encode scalar AVX instructions with specific vector length. */ |
850 | static enum | |
851 | { | |
852 | vex128 = 0, | |
853 | vex256 | |
854 | } avxscalar; | |
855 | ||
03751133 L |
856 | /* Encode VEX WIG instructions with specific vex.w. */ |
857 | static enum | |
858 | { | |
859 | vexw0 = 0, | |
860 | vexw1 | |
861 | } vexwig; | |
862 | ||
43234a1e L |
863 | /* Encode scalar EVEX LIG instructions with specific vector length. */ |
864 | static enum | |
865 | { | |
866 | evexl128 = 0, | |
867 | evexl256, | |
868 | evexl512 | |
869 | } evexlig; | |
870 | ||
871 | /* Encode EVEX WIG instructions with specific evex.w. */ | |
872 | static enum | |
873 | { | |
874 | evexw0 = 0, | |
875 | evexw1 | |
876 | } evexwig; | |
877 | ||
d3d3c6db IT |
878 | /* Value to encode in EVEX RC bits, for SAE-only instructions. */ |
879 | static enum rc_type evexrcig = rne; | |
880 | ||
29b0f896 | 881 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
87c245cc | 882 | static symbolS *GOT_symbol; |
29b0f896 | 883 | |
a4447b93 RH |
884 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
885 | unsigned int x86_dwarf2_return_column; | |
886 | ||
887 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
888 | int x86_cie_data_alignment; | |
889 | ||
252b5132 | 890 | /* Interface to relax_segment. |
fddf5b5b AM |
891 | There are 3 major relax states for 386 jump insns because the |
892 | different types of jumps add different sizes to frags when we're | |
e379e5f3 L |
893 | figuring out what sort of jump to choose to reach a given label. |
894 | ||
895 | BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align | |
896 | branches which are handled by md_estimate_size_before_relax() and | |
897 | i386_generic_table_relax_frag(). */ | |
252b5132 | 898 | |
47926f60 | 899 | /* Types. */ |
93c2a809 AM |
900 | #define UNCOND_JUMP 0 |
901 | #define COND_JUMP 1 | |
902 | #define COND_JUMP86 2 | |
e379e5f3 L |
903 | #define BRANCH_PADDING 3 |
904 | #define BRANCH_PREFIX 4 | |
905 | #define FUSED_JCC_PADDING 5 | |
fddf5b5b | 906 | |
47926f60 | 907 | /* Sizes. */ |
252b5132 RH |
908 | #define CODE16 1 |
909 | #define SMALL 0 | |
29b0f896 | 910 | #define SMALL16 (SMALL | CODE16) |
252b5132 | 911 | #define BIG 2 |
29b0f896 | 912 | #define BIG16 (BIG | CODE16) |
252b5132 RH |
913 | |
914 | #ifndef INLINE | |
915 | #ifdef __GNUC__ | |
916 | #define INLINE __inline__ | |
917 | #else | |
918 | #define INLINE | |
919 | #endif | |
920 | #endif | |
921 | ||
fddf5b5b AM |
922 | #define ENCODE_RELAX_STATE(type, size) \ |
923 | ((relax_substateT) (((type) << 2) | (size))) | |
924 | #define TYPE_FROM_RELAX_STATE(s) \ | |
925 | ((s) >> 2) | |
926 | #define DISP_SIZE_FROM_RELAX_STATE(s) \ | |
927 | ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) | |
252b5132 RH |
928 | |
929 | /* This table is used by relax_frag to promote short jumps to long | |
930 | ones where necessary. SMALL (short) jumps may be promoted to BIG | |
931 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We | |
932 | don't allow a short jump in a 32 bit code segment to be promoted to | |
933 | a 16 bit offset jump because it's slower (requires data size | |
934 | prefix), and doesn't work, unless the destination is in the bottom | |
935 | 64k of the code segment (The top 16 bits of eip are zeroed). */ | |
936 | ||
937 | const relax_typeS md_relax_table[] = | |
938 | { | |
24eab124 AM |
939 | /* The fields are: |
940 | 1) most positive reach of this state, | |
941 | 2) most negative reach of this state, | |
93c2a809 | 942 | 3) how many bytes this mode will have in the variable part of the frag |
ce8a8b2f | 943 | 4) which index into the table to try if we can't fit into this one. */ |
252b5132 | 944 | |
fddf5b5b | 945 | /* UNCOND_JUMP states. */ |
93c2a809 AM |
946 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, |
947 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, | |
948 | /* dword jmp adds 4 bytes to frag: | |
949 | 0 extra opcode bytes, 4 displacement bytes. */ | |
252b5132 | 950 | {0, 0, 4, 0}, |
93c2a809 AM |
951 | /* word jmp adds 2 byte2 to frag: |
952 | 0 extra opcode bytes, 2 displacement bytes. */ | |
252b5132 RH |
953 | {0, 0, 2, 0}, |
954 | ||
93c2a809 AM |
955 | /* COND_JUMP states. */ |
956 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, | |
957 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, | |
958 | /* dword conditionals adds 5 bytes to frag: | |
959 | 1 extra opcode byte, 4 displacement bytes. */ | |
960 | {0, 0, 5, 0}, | |
fddf5b5b | 961 | /* word conditionals add 3 bytes to frag: |
93c2a809 AM |
962 | 1 extra opcode byte, 2 displacement bytes. */ |
963 | {0, 0, 3, 0}, | |
964 | ||
965 | /* COND_JUMP86 states. */ | |
966 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, | |
967 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, | |
968 | /* dword conditionals adds 5 bytes to frag: | |
969 | 1 extra opcode byte, 4 displacement bytes. */ | |
970 | {0, 0, 5, 0}, | |
971 | /* word conditionals add 4 bytes to frag: | |
972 | 1 displacement byte and a 3 byte long branch insn. */ | |
973 | {0, 0, 4, 0} | |
252b5132 RH |
974 | }; |
975 | ||
6ceeed25 | 976 | #define ARCH(n, t, f, s) \ |
4fc85f37 | 977 | { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \ |
ae89daec JB |
978 | CPU_NONE_FLAGS } |
979 | #define SUBARCH(n, e, d, s) \ | |
4fc85f37 | 980 | { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \ |
ae89daec | 981 | CPU_ ## d ## _FLAGS } |
4fc85f37 JB |
982 | #define VECARCH(n, e, d, v) \ |
983 | { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \ | |
984 | CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS } | |
6ceeed25 | 985 | |
9103f4f4 L |
986 | static const arch_entry cpu_arch[] = |
987 | { | |
3ce2ebcf JB |
988 | /* Do not replace the first two entries - i386_target_format() and |
989 | set_cpu_arch() rely on them being there in this order. */ | |
6ceeed25 JB |
990 | ARCH (generic32, GENERIC32, GENERIC32, false), |
991 | ARCH (generic64, GENERIC64, GENERIC64, false), | |
992 | ARCH (i8086, UNKNOWN, NONE, false), | |
4d97c5c8 JB |
993 | ARCH (i186, UNKNOWN, 186, false), |
994 | ARCH (i286, UNKNOWN, 286, false), | |
995 | ARCH (i386, I386, 386, false), | |
996 | ARCH (i486, I486, 486, false), | |
997 | ARCH (i586, PENTIUM, 586, false), | |
998 | ARCH (i686, PENTIUMPRO, 686, false), | |
999 | ARCH (pentium, PENTIUM, 586, false), | |
6ceeed25 JB |
1000 | ARCH (pentiumpro, PENTIUMPRO, PENTIUMPRO, false), |
1001 | ARCH (pentiumii, PENTIUMPRO, P2, false), | |
1002 | ARCH (pentiumiii, PENTIUMPRO, P3, false), | |
1003 | ARCH (pentium4, PENTIUM4, P4, false), | |
1004 | ARCH (prescott, NOCONA, CORE, false), | |
1005 | ARCH (nocona, NOCONA, NOCONA, false), | |
1006 | ARCH (yonah, CORE, CORE, true), | |
1007 | ARCH (core, CORE, CORE, false), | |
1008 | ARCH (merom, CORE2, CORE2, true), | |
1009 | ARCH (core2, CORE2, CORE2, false), | |
1010 | ARCH (corei7, COREI7, COREI7, false), | |
1011 | ARCH (iamcu, IAMCU, IAMCU, false), | |
1012 | ARCH (k6, K6, K6, false), | |
1013 | ARCH (k6_2, K6, K6_2, false), | |
1014 | ARCH (athlon, ATHLON, ATHLON, false), | |
1015 | ARCH (sledgehammer, K8, K8, true), | |
1016 | ARCH (opteron, K8, K8, false), | |
1017 | ARCH (k8, K8, K8, false), | |
1018 | ARCH (amdfam10, AMDFAM10, AMDFAM10, false), | |
1019 | ARCH (bdver1, BD, BDVER1, false), | |
1020 | ARCH (bdver2, BD, BDVER2, false), | |
1021 | ARCH (bdver3, BD, BDVER3, false), | |
1022 | ARCH (bdver4, BD, BDVER4, false), | |
1023 | ARCH (znver1, ZNVER, ZNVER1, false), | |
1024 | ARCH (znver2, ZNVER, ZNVER2, false), | |
1025 | ARCH (znver3, ZNVER, ZNVER3, false), | |
b0e8fa7f | 1026 | ARCH (znver4, ZNVER, ZNVER4, false), |
6ceeed25 JB |
1027 | ARCH (btver1, BT, BTVER1, false), |
1028 | ARCH (btver2, BT, BTVER2, false), | |
1029 | ||
4d97c5c8 JB |
1030 | SUBARCH (8087, 8087, ANY_8087, false), |
1031 | SUBARCH (87, NONE, ANY_8087, false), /* Disable only! */ | |
ae89daec JB |
1032 | SUBARCH (287, 287, ANY_287, false), |
1033 | SUBARCH (387, 387, ANY_387, false), | |
1034 | SUBARCH (687, 687, ANY_687, false), | |
4d97c5c8 | 1035 | SUBARCH (cmov, CMOV, CMOV, false), |
88bd2203 | 1036 | SUBARCH (fxsr, FXSR, ANY_FXSR, false), |
ae89daec JB |
1037 | SUBARCH (mmx, MMX, ANY_MMX, false), |
1038 | SUBARCH (sse, SSE, ANY_SSE, false), | |
1039 | SUBARCH (sse2, SSE2, ANY_SSE2, false), | |
1040 | SUBARCH (sse3, SSE3, ANY_SSE3, false), | |
1041 | SUBARCH (sse4a, SSE4A, ANY_SSE4A, false), | |
1042 | SUBARCH (ssse3, SSSE3, ANY_SSSE3, false), | |
1043 | SUBARCH (sse4.1, SSE4_1, ANY_SSE4_1, false), | |
1044 | SUBARCH (sse4.2, SSE4_2, ANY_SSE4_2, false), | |
1045 | SUBARCH (sse4, SSE4_2, ANY_SSE4_1, false), | |
4fc85f37 JB |
1046 | VECARCH (avx, AVX, ANY_AVX, reset), |
1047 | VECARCH (avx2, AVX2, ANY_AVX2, reset), | |
1048 | VECARCH (avx512f, AVX512F, ANY_AVX512F, reset), | |
1049 | VECARCH (avx512cd, AVX512CD, ANY_AVX512CD, reset), | |
1050 | VECARCH (avx512er, AVX512ER, ANY_AVX512ER, reset), | |
1051 | VECARCH (avx512pf, AVX512PF, ANY_AVX512PF, reset), | |
1052 | VECARCH (avx512dq, AVX512DQ, ANY_AVX512DQ, reset), | |
1053 | VECARCH (avx512bw, AVX512BW, ANY_AVX512BW, reset), | |
1054 | VECARCH (avx512vl, AVX512VL, ANY_AVX512VL, reset), | |
cafa5ef7 | 1055 | SUBARCH (monitor, MONITOR, MONITOR, false), |
25626f79 JB |
1056 | SUBARCH (vmx, VMX, ANY_VMX, false), |
1057 | SUBARCH (vmfunc, VMFUNC, ANY_VMFUNC, false), | |
ae89daec | 1058 | SUBARCH (smx, SMX, SMX, false), |
5091b9ee JB |
1059 | SUBARCH (xsave, XSAVE, ANY_XSAVE, false), |
1060 | SUBARCH (xsaveopt, XSAVEOPT, ANY_XSAVEOPT, false), | |
1061 | SUBARCH (xsavec, XSAVEC, ANY_XSAVEC, false), | |
1062 | SUBARCH (xsaves, XSAVES, ANY_XSAVES, false), | |
1063 | SUBARCH (aes, AES, ANY_AES, false), | |
d54678eb JB |
1064 | SUBARCH (pclmul, PCLMULQDQ, ANY_PCLMULQDQ, false), |
1065 | SUBARCH (clmul, PCLMULQDQ, ANY_PCLMULQDQ, true), | |
ae89daec JB |
1066 | SUBARCH (fsgsbase, FSGSBASE, FSGSBASE, false), |
1067 | SUBARCH (rdrnd, RDRND, RDRND, false), | |
5091b9ee | 1068 | SUBARCH (f16c, F16C, ANY_F16C, false), |
ae89daec | 1069 | SUBARCH (bmi2, BMI2, BMI2, false), |
5091b9ee JB |
1070 | SUBARCH (fma, FMA, ANY_FMA, false), |
1071 | SUBARCH (fma4, FMA4, ANY_FMA4, false), | |
1072 | SUBARCH (xop, XOP, ANY_XOP, false), | |
1073 | SUBARCH (lwp, LWP, ANY_LWP, false), | |
ae89daec JB |
1074 | SUBARCH (movbe, MOVBE, MOVBE, false), |
1075 | SUBARCH (cx16, CX16, CX16, false), | |
c3bb24f5 | 1076 | SUBARCH (lahf_sahf, LAHF_SAHF, LAHF_SAHF, false), |
25626f79 | 1077 | SUBARCH (ept, EPT, ANY_EPT, false), |
ae89daec JB |
1078 | SUBARCH (lzcnt, LZCNT, LZCNT, false), |
1079 | SUBARCH (popcnt, POPCNT, POPCNT, false), | |
1080 | SUBARCH (hle, HLE, HLE, false), | |
760ab3d0 JB |
1081 | SUBARCH (rtm, RTM, ANY_RTM, false), |
1082 | SUBARCH (tsx, TSX, TSX, false), | |
ae89daec JB |
1083 | SUBARCH (invpcid, INVPCID, INVPCID, false), |
1084 | SUBARCH (clflush, CLFLUSH, CLFLUSH, false), | |
1085 | SUBARCH (nop, NOP, NOP, false), | |
1086 | SUBARCH (syscall, SYSCALL, SYSCALL, false), | |
1087 | SUBARCH (rdtscp, RDTSCP, RDTSCP, false), | |
5091b9ee JB |
1088 | SUBARCH (3dnow, 3DNOW, ANY_3DNOW, false), |
1089 | SUBARCH (3dnowa, 3DNOWA, ANY_3DNOWA, false), | |
ae89daec | 1090 | SUBARCH (padlock, PADLOCK, PADLOCK, false), |
0919e770 JB |
1091 | SUBARCH (pacifica, SVME, ANY_SVME, true), |
1092 | SUBARCH (svme, SVME, ANY_SVME, false), | |
ae89daec JB |
1093 | SUBARCH (abm, ABM, ABM, false), |
1094 | SUBARCH (bmi, BMI, BMI, false), | |
1095 | SUBARCH (tbm, TBM, TBM, false), | |
1096 | SUBARCH (adx, ADX, ADX, false), | |
1097 | SUBARCH (rdseed, RDSEED, RDSEED, false), | |
1098 | SUBARCH (prfchw, PRFCHW, PRFCHW, false), | |
1099 | SUBARCH (smap, SMAP, SMAP, false), | |
5091b9ee JB |
1100 | SUBARCH (mpx, MPX, ANY_MPX, false), |
1101 | SUBARCH (sha, SHA, ANY_SHA, false), | |
ae89daec JB |
1102 | SUBARCH (clflushopt, CLFLUSHOPT, CLFLUSHOPT, false), |
1103 | SUBARCH (prefetchwt1, PREFETCHWT1, PREFETCHWT1, false), | |
1104 | SUBARCH (se1, SE1, SE1, false), | |
1105 | SUBARCH (clwb, CLWB, CLWB, false), | |
4fc85f37 JB |
1106 | VECARCH (avx512ifma, AVX512IFMA, ANY_AVX512IFMA, reset), |
1107 | VECARCH (avx512vbmi, AVX512VBMI, ANY_AVX512VBMI, reset), | |
1108 | VECARCH (avx512_4fmaps, AVX512_4FMAPS, ANY_AVX512_4FMAPS, reset), | |
1109 | VECARCH (avx512_4vnniw, AVX512_4VNNIW, ANY_AVX512_4VNNIW, reset), | |
1110 | VECARCH (avx512_vpopcntdq, AVX512_VPOPCNTDQ, ANY_AVX512_VPOPCNTDQ, reset), | |
1111 | VECARCH (avx512_vbmi2, AVX512_VBMI2, ANY_AVX512_VBMI2, reset), | |
1112 | VECARCH (avx512_vnni, AVX512_VNNI, ANY_AVX512_VNNI, reset), | |
1113 | VECARCH (avx512_bitalg, AVX512_BITALG, ANY_AVX512_BITALG, reset), | |
1114 | VECARCH (avx_vnni, AVX_VNNI, ANY_AVX_VNNI, reset), | |
ae89daec JB |
1115 | SUBARCH (clzero, CLZERO, CLZERO, false), |
1116 | SUBARCH (mwaitx, MWAITX, MWAITX, false), | |
5091b9ee | 1117 | SUBARCH (ospke, OSPKE, ANY_OSPKE, false), |
ae89daec JB |
1118 | SUBARCH (rdpid, RDPID, RDPID, false), |
1119 | SUBARCH (ptwrite, PTWRITE, PTWRITE, false), | |
4d97c5c8 JB |
1120 | SUBARCH (ibt, IBT, IBT, false), |
1121 | SUBARCH (shstk, SHSTK, SHSTK, false), | |
88bd2203 | 1122 | SUBARCH (gfni, GFNI, ANY_GFNI, false), |
4fc85f37 JB |
1123 | VECARCH (vaes, VAES, ANY_VAES, reset), |
1124 | VECARCH (vpclmulqdq, VPCLMULQDQ, ANY_VPCLMULQDQ, reset), | |
ae89daec JB |
1125 | SUBARCH (wbnoinvd, WBNOINVD, WBNOINVD, false), |
1126 | SUBARCH (pconfig, PCONFIG, PCONFIG, false), | |
1127 | SUBARCH (waitpkg, WAITPKG, WAITPKG, false), | |
1128 | SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false), | |
1129 | SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false), | |
1130 | SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false), | |
5091b9ee | 1131 | SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false), |
d100d8c1 | 1132 | SUBARCH (amx_complex, AMX_COMPLEX, ANY_AMX_COMPLEX, false), |
ae89daec | 1133 | SUBARCH (amx_tile, AMX_TILE, ANY_AMX_TILE, false), |
4d97c5c8 JB |
1134 | SUBARCH (movdiri, MOVDIRI, MOVDIRI, false), |
1135 | SUBARCH (movdir64b, MOVDIR64B, MOVDIR64B, false), | |
4fc85f37 JB |
1136 | VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset), |
1137 | VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT, | |
1138 | ANY_AVX512_VP2INTERSECT, reset), | |
4d97c5c8 JB |
1139 | SUBARCH (tdx, TDX, TDX, false), |
1140 | SUBARCH (enqcmd, ENQCMD, ENQCMD, false), | |
1141 | SUBARCH (serialize, SERIALIZE, SERIALIZE, false), | |
ae89daec JB |
1142 | SUBARCH (rdpru, RDPRU, RDPRU, false), |
1143 | SUBARCH (mcommit, MCOMMIT, MCOMMIT, false), | |
0919e770 | 1144 | SUBARCH (sev_es, SEV_ES, ANY_SEV_ES, false), |
760ab3d0 | 1145 | SUBARCH (tsxldtrk, TSXLDTRK, ANY_TSXLDTRK, false), |
88bd2203 JB |
1146 | SUBARCH (kl, KL, ANY_KL, false), |
1147 | SUBARCH (widekl, WIDEKL, ANY_WIDEKL, false), | |
4d97c5c8 JB |
1148 | SUBARCH (uintr, UINTR, UINTR, false), |
1149 | SUBARCH (hreset, HRESET, HRESET, false), | |
4fc85f37 | 1150 | VECARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, reset), |
ef07be45 | 1151 | SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false), |
4fc85f37 JB |
1152 | VECARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, reset), |
1153 | VECARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, reset), | |
4d97c5c8 JB |
1154 | SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), |
1155 | SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), | |
1156 | SUBARCH (msrlist, MSRLIST, MSRLIST, false), | |
4fc85f37 | 1157 | VECARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, reset), |
4d97c5c8 | 1158 | SUBARCH (rao_int, RAO_INT, RAO_INT, false), |
0919e770 | 1159 | SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false), |
c88ed92f ZJ |
1160 | SUBARCH (fred, FRED, ANY_FRED, false), |
1161 | SUBARCH (lkgs, LKGS, ANY_LKGS, false), | |
4fc85f37 JB |
1162 | VECARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, reset), |
1163 | VECARCH (sha512, SHA512, ANY_SHA512, reset), | |
1164 | VECARCH (sm3, SM3, ANY_SM3, reset), | |
1165 | VECARCH (sm4, SM4, ANY_SM4, reset), | |
b5c37946 | 1166 | SUBARCH (pbndkb, PBNDKB, PBNDKB, false), |
4fc85f37 | 1167 | VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set), |
293f5f65 L |
1168 | }; |
1169 | ||
6ceeed25 JB |
1170 | #undef SUBARCH |
1171 | #undef ARCH | |
1172 | ||
704209c0 | 1173 | #ifdef I386COFF |
a6c24e68 NC |
1174 | /* Like s_lcomm_internal in gas/read.c but the alignment string |
1175 | is allowed to be optional. */ | |
1176 | ||
1177 | static symbolS * | |
1178 | pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size) | |
1179 | { | |
1180 | addressT align = 0; | |
1181 | ||
1182 | SKIP_WHITESPACE (); | |
1183 | ||
7ab9ffdd | 1184 | if (needs_align |
a6c24e68 NC |
1185 | && *input_line_pointer == ',') |
1186 | { | |
1187 | align = parse_align (needs_align - 1); | |
7ab9ffdd | 1188 | |
a6c24e68 NC |
1189 | if (align == (addressT) -1) |
1190 | return NULL; | |
1191 | } | |
1192 | else | |
1193 | { | |
1194 | if (size >= 8) | |
1195 | align = 3; | |
1196 | else if (size >= 4) | |
1197 | align = 2; | |
1198 | else if (size >= 2) | |
1199 | align = 1; | |
1200 | else | |
1201 | align = 0; | |
1202 | } | |
1203 | ||
1204 | bss_alloc (symbolP, size, align); | |
1205 | return symbolP; | |
1206 | } | |
1207 | ||
704209c0 | 1208 | static void |
a6c24e68 NC |
1209 | pe_lcomm (int needs_align) |
1210 | { | |
1211 | s_comm_internal (needs_align * 2, pe_lcomm_internal); | |
1212 | } | |
704209c0 | 1213 | #endif |
a6c24e68 | 1214 | |
29b0f896 AM |
1215 | const pseudo_typeS md_pseudo_table[] = |
1216 | { | |
1217 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) | |
1218 | {"align", s_align_bytes, 0}, | |
1219 | #else | |
1220 | {"align", s_align_ptwo, 0}, | |
1221 | #endif | |
1222 | {"arch", set_cpu_arch, 0}, | |
1223 | #ifndef I386COFF | |
1224 | {"bss", s_bss, 0}, | |
a6c24e68 NC |
1225 | #else |
1226 | {"lcomm", pe_lcomm, 1}, | |
29b0f896 AM |
1227 | #endif |
1228 | {"ffloat", float_cons, 'f'}, | |
1229 | {"dfloat", float_cons, 'd'}, | |
1230 | {"tfloat", float_cons, 'x'}, | |
7d19d096 | 1231 | {"hfloat", float_cons, 'h'}, |
de133cf9 | 1232 | {"bfloat16", float_cons, 'b'}, |
29b0f896 | 1233 | {"value", cons, 2}, |
d182319b | 1234 | {"slong", signed_cons, 4}, |
edd67638 | 1235 | {"insn", s_insn, 0}, |
29b0f896 AM |
1236 | {"noopt", s_ignore, 0}, |
1237 | {"optim", s_ignore, 0}, | |
1238 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, | |
1239 | {"code16", set_code_flag, CODE_16BIT}, | |
1240 | {"code32", set_code_flag, CODE_32BIT}, | |
da5f19a2 | 1241 | #ifdef BFD64 |
29b0f896 | 1242 | {"code64", set_code_flag, CODE_64BIT}, |
da5f19a2 | 1243 | #endif |
29b0f896 AM |
1244 | {"intel_syntax", set_intel_syntax, 1}, |
1245 | {"att_syntax", set_intel_syntax, 0}, | |
1efbbeb4 L |
1246 | {"intel_mnemonic", set_intel_mnemonic, 1}, |
1247 | {"att_mnemonic", set_intel_mnemonic, 0}, | |
db51cc60 L |
1248 | {"allow_index_reg", set_allow_index_reg, 1}, |
1249 | {"disallow_index_reg", set_allow_index_reg, 0}, | |
7bab8ab5 JB |
1250 | {"sse_check", set_check, 0}, |
1251 | {"operand_check", set_check, 1}, | |
3b22753a L |
1252 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1253 | {"largecomm", handle_large_common, 0}, | |
07a53e5c | 1254 | #else |
68d20676 | 1255 | {"file", dwarf2_directive_file, 0}, |
07a53e5c RH |
1256 | {"loc", dwarf2_directive_loc, 0}, |
1257 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, | |
3b22753a | 1258 | #endif |
6482c264 NC |
1259 | #ifdef TE_PE |
1260 | {"secrel32", pe_directive_secrel, 0}, | |
145667f8 | 1261 | {"secidx", pe_directive_secidx, 0}, |
6482c264 | 1262 | #endif |
29b0f896 AM |
1263 | {0, 0, 0} |
1264 | }; | |
1265 | ||
1266 | /* For interface with expression (). */ | |
1267 | extern char *input_line_pointer; | |
1268 | ||
1269 | /* Hash table for instruction mnemonic lookup. */ | |
629310ab | 1270 | static htab_t op_hash; |
29b0f896 AM |
1271 | |
1272 | /* Hash table for register lookup. */ | |
629310ab | 1273 | static htab_t reg_hash; |
29b0f896 | 1274 | \f |
ce8a8b2f AM |
1275 | /* Various efficient no-op patterns for aligning code labels. |
1276 | Note: Don't try to assemble the instructions in the comments. | |
1277 | 0L and 0w are not legal. */ | |
62a02d25 L |
1278 | static const unsigned char f32_1[] = |
1279 | {0x90}; /* nop */ | |
1280 | static const unsigned char f32_2[] = | |
1281 | {0x66,0x90}; /* xchg %ax,%ax */ | |
1282 | static const unsigned char f32_3[] = | |
1283 | {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */ | |
1284 | static const unsigned char f32_4[] = | |
1285 | {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */ | |
62a02d25 L |
1286 | static const unsigned char f32_6[] = |
1287 | {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */ | |
1288 | static const unsigned char f32_7[] = | |
1289 | {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */ | |
62a02d25 | 1290 | static const unsigned char f16_3[] = |
3ae729d5 | 1291 | {0x8d,0x74,0x00}; /* lea 0(%si),%si */ |
62a02d25 | 1292 | static const unsigned char f16_4[] = |
3ae729d5 L |
1293 | {0x8d,0xb4,0x00,0x00}; /* lea 0W(%si),%si */ |
1294 | static const unsigned char jump_disp8[] = | |
1295 | {0xeb}; /* jmp disp8 */ | |
1296 | static const unsigned char jump32_disp32[] = | |
1297 | {0xe9}; /* jmp disp32 */ | |
1298 | static const unsigned char jump16_disp32[] = | |
1299 | {0x66,0xe9}; /* jmp disp32 */ | |
62a02d25 L |
1300 | /* 32-bit NOPs patterns. */ |
1301 | static const unsigned char *const f32_patt[] = { | |
3ae729d5 | 1302 | f32_1, f32_2, f32_3, f32_4, NULL, f32_6, f32_7 |
62a02d25 L |
1303 | }; |
1304 | /* 16-bit NOPs patterns. */ | |
1305 | static const unsigned char *const f16_patt[] = { | |
3ae729d5 | 1306 | f32_1, f32_2, f16_3, f16_4 |
62a02d25 L |
1307 | }; |
1308 | /* nopl (%[re]ax) */ | |
1309 | static const unsigned char alt_3[] = | |
1310 | {0x0f,0x1f,0x00}; | |
1311 | /* nopl 0(%[re]ax) */ | |
1312 | static const unsigned char alt_4[] = | |
1313 | {0x0f,0x1f,0x40,0x00}; | |
1314 | /* nopl 0(%[re]ax,%[re]ax,1) */ | |
1315 | static const unsigned char alt_5[] = | |
1316 | {0x0f,0x1f,0x44,0x00,0x00}; | |
1317 | /* nopw 0(%[re]ax,%[re]ax,1) */ | |
1318 | static const unsigned char alt_6[] = | |
1319 | {0x66,0x0f,0x1f,0x44,0x00,0x00}; | |
1320 | /* nopl 0L(%[re]ax) */ | |
1321 | static const unsigned char alt_7[] = | |
1322 | {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00}; | |
1323 | /* nopl 0L(%[re]ax,%[re]ax,1) */ | |
1324 | static const unsigned char alt_8[] = | |
1325 | {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1326 | /* nopw 0L(%[re]ax,%[re]ax,1) */ | |
1327 | static const unsigned char alt_9[] = | |
1328 | {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
1329 | /* nopw %cs:0L(%[re]ax,%[re]ax,1) */ | |
1330 | static const unsigned char alt_10[] = | |
1331 | {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
3ae729d5 L |
1332 | /* data16 nopw %cs:0L(%eax,%eax,1) */ |
1333 | static const unsigned char alt_11[] = | |
1334 | {0x66,0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00}; | |
62a02d25 L |
1335 | /* 32-bit and 64-bit NOPs patterns. */ |
1336 | static const unsigned char *const alt_patt[] = { | |
1337 | f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8, | |
3ae729d5 | 1338 | alt_9, alt_10, alt_11 |
62a02d25 L |
1339 | }; |
1340 | ||
1341 | /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum | |
1342 | size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */ | |
1343 | ||
1344 | static void | |
1345 | i386_output_nops (char *where, const unsigned char *const *patt, | |
1346 | int count, int max_single_nop_size) | |
1347 | ||
1348 | { | |
3ae729d5 L |
1349 | /* Place the longer NOP first. */ |
1350 | int last; | |
1351 | int offset; | |
3076e594 NC |
1352 | const unsigned char *nops; |
1353 | ||
1354 | if (max_single_nop_size < 1) | |
1355 | { | |
1356 | as_fatal (_("i386_output_nops called to generate nops of at most %d bytes!"), | |
1357 | max_single_nop_size); | |
1358 | return; | |
1359 | } | |
1360 | ||
1361 | nops = patt[max_single_nop_size - 1]; | |
3ae729d5 L |
1362 | |
1363 | /* Use the smaller one if the requsted one isn't available. */ | |
1364 | if (nops == NULL) | |
62a02d25 | 1365 | { |
3ae729d5 L |
1366 | max_single_nop_size--; |
1367 | nops = patt[max_single_nop_size - 1]; | |
62a02d25 L |
1368 | } |
1369 | ||
3ae729d5 L |
1370 | last = count % max_single_nop_size; |
1371 | ||
1372 | count -= last; | |
1373 | for (offset = 0; offset < count; offset += max_single_nop_size) | |
1374 | memcpy (where + offset, nops, max_single_nop_size); | |
1375 | ||
1376 | if (last) | |
1377 | { | |
1378 | nops = patt[last - 1]; | |
1379 | if (nops == NULL) | |
1380 | { | |
1381 | /* Use the smaller one plus one-byte NOP if the needed one | |
1382 | isn't available. */ | |
1383 | last--; | |
1384 | nops = patt[last - 1]; | |
1385 | memcpy (where + offset, nops, last); | |
1386 | where[offset + last] = *patt[0]; | |
1387 | } | |
1388 | else | |
1389 | memcpy (where + offset, nops, last); | |
1390 | } | |
62a02d25 L |
1391 | } |
1392 | ||
3ae729d5 L |
1393 | static INLINE int |
1394 | fits_in_imm7 (offsetT num) | |
1395 | { | |
1396 | return (num & 0x7f) == num; | |
1397 | } | |
1398 | ||
1399 | static INLINE int | |
1400 | fits_in_imm31 (offsetT num) | |
1401 | { | |
1402 | return (num & 0x7fffffff) == num; | |
1403 | } | |
62a02d25 L |
1404 | |
1405 | /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a | |
1406 | single NOP instruction LIMIT. */ | |
1407 | ||
1408 | void | |
3ae729d5 | 1409 | i386_generate_nops (fragS *fragP, char *where, offsetT count, int limit) |
62a02d25 | 1410 | { |
3ae729d5 | 1411 | const unsigned char *const *patt = NULL; |
62a02d25 | 1412 | int max_single_nop_size; |
3ae729d5 L |
1413 | /* Maximum number of NOPs before switching to jump over NOPs. */ |
1414 | int max_number_of_nops; | |
62a02d25 | 1415 | |
3ae729d5 | 1416 | switch (fragP->fr_type) |
62a02d25 | 1417 | { |
3ae729d5 L |
1418 | case rs_fill_nop: |
1419 | case rs_align_code: | |
1420 | break; | |
e379e5f3 L |
1421 | case rs_machine_dependent: |
1422 | /* Allow NOP padding for jumps and calls. */ | |
1423 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
1424 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
1425 | break; | |
1426 | /* Fall through. */ | |
3ae729d5 | 1427 | default: |
62a02d25 L |
1428 | return; |
1429 | } | |
1430 | ||
ccc9c027 L |
1431 | /* We need to decide which NOP sequence to use for 32bit and |
1432 | 64bit. When -mtune= is used: | |
4eed87de | 1433 | |
76bc74dc L |
1434 | 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and |
1435 | PROCESSOR_GENERIC32, f32_patt will be used. | |
80b8656c L |
1436 | 2. For the rest, alt_patt will be used. |
1437 | ||
1438 | When -mtune= isn't used, alt_patt will be used if | |
22109423 | 1439 | cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will |
76bc74dc | 1440 | be used. |
ccc9c027 L |
1441 | |
1442 | When -march= or .arch is used, we can't use anything beyond | |
1443 | cpu_arch_isa_flags. */ | |
1444 | ||
1445 | if (flag_code == CODE_16BIT) | |
1446 | { | |
3ae729d5 L |
1447 | patt = f16_patt; |
1448 | max_single_nop_size = sizeof (f16_patt) / sizeof (f16_patt[0]); | |
1449 | /* Limit number of NOPs to 2 in 16-bit mode. */ | |
1450 | max_number_of_nops = 2; | |
252b5132 | 1451 | } |
33fef721 | 1452 | else |
ccc9c027 | 1453 | { |
fbf3f584 | 1454 | if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN) |
ccc9c027 L |
1455 | { |
1456 | /* PROCESSOR_UNKNOWN means that all ISAs may be used. */ | |
1457 | switch (cpu_arch_tune) | |
1458 | { | |
1459 | case PROCESSOR_UNKNOWN: | |
1460 | /* We use cpu_arch_isa_flags to check if we SHOULD | |
22109423 L |
1461 | optimize with nops. */ |
1462 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1463 | patt = alt_patt; |
ccc9c027 L |
1464 | else |
1465 | patt = f32_patt; | |
1466 | break; | |
ccc9c027 L |
1467 | case PROCESSOR_PENTIUM4: |
1468 | case PROCESSOR_NOCONA: | |
ef05d495 | 1469 | case PROCESSOR_CORE: |
76bc74dc | 1470 | case PROCESSOR_CORE2: |
bd5295b2 | 1471 | case PROCESSOR_COREI7: |
76bc74dc | 1472 | case PROCESSOR_GENERIC64: |
ccc9c027 L |
1473 | case PROCESSOR_K6: |
1474 | case PROCESSOR_ATHLON: | |
1475 | case PROCESSOR_K8: | |
4eed87de | 1476 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1477 | case PROCESSOR_BD: |
029f3522 | 1478 | case PROCESSOR_ZNVER: |
7b458c12 | 1479 | case PROCESSOR_BT: |
80b8656c | 1480 | patt = alt_patt; |
ccc9c027 | 1481 | break; |
76bc74dc | 1482 | case PROCESSOR_I386: |
ccc9c027 L |
1483 | case PROCESSOR_I486: |
1484 | case PROCESSOR_PENTIUM: | |
2dde1948 | 1485 | case PROCESSOR_PENTIUMPRO: |
81486035 | 1486 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1487 | case PROCESSOR_GENERIC32: |
1488 | patt = f32_patt; | |
1489 | break; | |
c368d2a8 JB |
1490 | case PROCESSOR_NONE: |
1491 | abort (); | |
4eed87de | 1492 | } |
ccc9c027 L |
1493 | } |
1494 | else | |
1495 | { | |
fbf3f584 | 1496 | switch (fragP->tc_frag_data.tune) |
ccc9c027 L |
1497 | { |
1498 | case PROCESSOR_UNKNOWN: | |
e6a14101 | 1499 | /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be |
ccc9c027 L |
1500 | PROCESSOR_UNKNOWN. */ |
1501 | abort (); | |
1502 | break; | |
1503 | ||
76bc74dc | 1504 | case PROCESSOR_I386: |
ccc9c027 L |
1505 | case PROCESSOR_I486: |
1506 | case PROCESSOR_PENTIUM: | |
81486035 | 1507 | case PROCESSOR_IAMCU: |
ccc9c027 L |
1508 | case PROCESSOR_K6: |
1509 | case PROCESSOR_ATHLON: | |
1510 | case PROCESSOR_K8: | |
4eed87de | 1511 | case PROCESSOR_AMDFAM10: |
8aedb9fe | 1512 | case PROCESSOR_BD: |
029f3522 | 1513 | case PROCESSOR_ZNVER: |
7b458c12 | 1514 | case PROCESSOR_BT: |
ccc9c027 L |
1515 | case PROCESSOR_GENERIC32: |
1516 | /* We use cpu_arch_isa_flags to check if we CAN optimize | |
22109423 L |
1517 | with nops. */ |
1518 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) | |
80b8656c | 1519 | patt = alt_patt; |
ccc9c027 L |
1520 | else |
1521 | patt = f32_patt; | |
1522 | break; | |
76bc74dc L |
1523 | case PROCESSOR_PENTIUMPRO: |
1524 | case PROCESSOR_PENTIUM4: | |
1525 | case PROCESSOR_NOCONA: | |
1526 | case PROCESSOR_CORE: | |
ef05d495 | 1527 | case PROCESSOR_CORE2: |
bd5295b2 | 1528 | case PROCESSOR_COREI7: |
22109423 | 1529 | if (fragP->tc_frag_data.isa_flags.bitfield.cpunop) |
80b8656c | 1530 | patt = alt_patt; |
ccc9c027 L |
1531 | else |
1532 | patt = f32_patt; | |
1533 | break; | |
1534 | case PROCESSOR_GENERIC64: | |
80b8656c | 1535 | patt = alt_patt; |
ccc9c027 | 1536 | break; |
c368d2a8 JB |
1537 | case PROCESSOR_NONE: |
1538 | abort (); | |
4eed87de | 1539 | } |
ccc9c027 L |
1540 | } |
1541 | ||
76bc74dc L |
1542 | if (patt == f32_patt) |
1543 | { | |
3ae729d5 L |
1544 | max_single_nop_size = sizeof (f32_patt) / sizeof (f32_patt[0]); |
1545 | /* Limit number of NOPs to 2 for older processors. */ | |
1546 | max_number_of_nops = 2; | |
76bc74dc L |
1547 | } |
1548 | else | |
1549 | { | |
3ae729d5 L |
1550 | max_single_nop_size = sizeof (alt_patt) / sizeof (alt_patt[0]); |
1551 | /* Limit number of NOPs to 7 for newer processors. */ | |
1552 | max_number_of_nops = 7; | |
1553 | } | |
1554 | } | |
1555 | ||
1556 | if (limit == 0) | |
1557 | limit = max_single_nop_size; | |
1558 | ||
1559 | if (fragP->fr_type == rs_fill_nop) | |
1560 | { | |
1561 | /* Output NOPs for .nop directive. */ | |
1562 | if (limit > max_single_nop_size) | |
1563 | { | |
1564 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1565 | _("invalid single nop size: %d " | |
1566 | "(expect within [0, %d])"), | |
1567 | limit, max_single_nop_size); | |
1568 | return; | |
1569 | } | |
1570 | } | |
e379e5f3 | 1571 | else if (fragP->fr_type != rs_machine_dependent) |
3ae729d5 L |
1572 | fragP->fr_var = count; |
1573 | ||
1574 | if ((count / max_single_nop_size) > max_number_of_nops) | |
1575 | { | |
1576 | /* Generate jump over NOPs. */ | |
1577 | offsetT disp = count - 2; | |
1578 | if (fits_in_imm7 (disp)) | |
1579 | { | |
1580 | /* Use "jmp disp8" if possible. */ | |
1581 | count = disp; | |
1582 | where[0] = jump_disp8[0]; | |
1583 | where[1] = count; | |
1584 | where += 2; | |
1585 | } | |
1586 | else | |
1587 | { | |
1588 | unsigned int size_of_jump; | |
1589 | ||
1590 | if (flag_code == CODE_16BIT) | |
1591 | { | |
1592 | where[0] = jump16_disp32[0]; | |
1593 | where[1] = jump16_disp32[1]; | |
1594 | size_of_jump = 2; | |
1595 | } | |
1596 | else | |
1597 | { | |
1598 | where[0] = jump32_disp32[0]; | |
1599 | size_of_jump = 1; | |
1600 | } | |
1601 | ||
1602 | count -= size_of_jump + 4; | |
1603 | if (!fits_in_imm31 (count)) | |
1604 | { | |
1605 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
1606 | _("jump over nop padding out of range")); | |
1607 | return; | |
1608 | } | |
1609 | ||
1610 | md_number_to_chars (where + size_of_jump, count, 4); | |
1611 | where += size_of_jump + 4; | |
76bc74dc | 1612 | } |
ccc9c027 | 1613 | } |
3ae729d5 L |
1614 | |
1615 | /* Generate multiple NOPs. */ | |
1616 | i386_output_nops (where, patt, count, limit); | |
252b5132 RH |
1617 | } |
1618 | ||
c6fb90c8 | 1619 | static INLINE int |
0dfbf9d7 | 1620 | operand_type_all_zero (const union i386_operand_type *x) |
40fb9820 | 1621 | { |
0dfbf9d7 | 1622 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1623 | { |
1624 | case 3: | |
0dfbf9d7 | 1625 | if (x->array[2]) |
c6fb90c8 | 1626 | return 0; |
1a0670f3 | 1627 | /* Fall through. */ |
c6fb90c8 | 1628 | case 2: |
0dfbf9d7 | 1629 | if (x->array[1]) |
c6fb90c8 | 1630 | return 0; |
1a0670f3 | 1631 | /* Fall through. */ |
c6fb90c8 | 1632 | case 1: |
0dfbf9d7 | 1633 | return !x->array[0]; |
c6fb90c8 L |
1634 | default: |
1635 | abort (); | |
1636 | } | |
40fb9820 L |
1637 | } |
1638 | ||
c6fb90c8 | 1639 | static INLINE void |
0dfbf9d7 | 1640 | operand_type_set (union i386_operand_type *x, unsigned int v) |
40fb9820 | 1641 | { |
0dfbf9d7 | 1642 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1643 | { |
1644 | case 3: | |
0dfbf9d7 | 1645 | x->array[2] = v; |
1a0670f3 | 1646 | /* Fall through. */ |
c6fb90c8 | 1647 | case 2: |
0dfbf9d7 | 1648 | x->array[1] = v; |
1a0670f3 | 1649 | /* Fall through. */ |
c6fb90c8 | 1650 | case 1: |
0dfbf9d7 | 1651 | x->array[0] = v; |
1a0670f3 | 1652 | /* Fall through. */ |
c6fb90c8 L |
1653 | break; |
1654 | default: | |
1655 | abort (); | |
1656 | } | |
bab6aec1 JB |
1657 | |
1658 | x->bitfield.class = ClassNone; | |
75e5731b | 1659 | x->bitfield.instance = InstanceNone; |
c6fb90c8 | 1660 | } |
40fb9820 | 1661 | |
c6fb90c8 | 1662 | static INLINE int |
0dfbf9d7 L |
1663 | operand_type_equal (const union i386_operand_type *x, |
1664 | const union i386_operand_type *y) | |
c6fb90c8 | 1665 | { |
0dfbf9d7 | 1666 | switch (ARRAY_SIZE(x->array)) |
c6fb90c8 L |
1667 | { |
1668 | case 3: | |
0dfbf9d7 | 1669 | if (x->array[2] != y->array[2]) |
c6fb90c8 | 1670 | return 0; |
1a0670f3 | 1671 | /* Fall through. */ |
c6fb90c8 | 1672 | case 2: |
0dfbf9d7 | 1673 | if (x->array[1] != y->array[1]) |
c6fb90c8 | 1674 | return 0; |
1a0670f3 | 1675 | /* Fall through. */ |
c6fb90c8 | 1676 | case 1: |
0dfbf9d7 | 1677 | return x->array[0] == y->array[0]; |
c6fb90c8 L |
1678 | break; |
1679 | default: | |
1680 | abort (); | |
1681 | } | |
1682 | } | |
40fb9820 | 1683 | |
734dfd1c JB |
1684 | static INLINE bool |
1685 | is_cpu (const insn_template *t, enum i386_cpu cpu) | |
1686 | { | |
1687 | switch (cpu) | |
1688 | { | |
1689 | case Cpu287: return t->cpu.bitfield.cpu287; | |
1690 | case Cpu387: return t->cpu.bitfield.cpu387; | |
1691 | case Cpu3dnow: return t->cpu.bitfield.cpu3dnow; | |
1692 | case Cpu3dnowA: return t->cpu.bitfield.cpu3dnowa; | |
1693 | case CpuAVX: return t->cpu.bitfield.cpuavx; | |
1694 | case CpuHLE: return t->cpu.bitfield.cpuhle; | |
1695 | case CpuAVX512F: return t->cpu.bitfield.cpuavx512f; | |
1696 | case CpuAVX512VL: return t->cpu.bitfield.cpuavx512vl; | |
1697 | case Cpu64: return t->cpu.bitfield.cpu64; | |
1698 | case CpuNo64: return t->cpu.bitfield.cpuno64; | |
1699 | default: | |
1700 | gas_assert (cpu < CpuAttrEnums); | |
1701 | } | |
1702 | return t->cpu.bitfield.isa == cpu + 1u; | |
1703 | } | |
1704 | ||
1705 | static i386_cpu_flags cpu_flags_from_attr (i386_cpu_attr a) | |
1706 | { | |
1707 | const unsigned int bps = sizeof (a.array[0]) * CHAR_BIT; | |
1708 | i386_cpu_flags f = { .array[0] = 0 }; | |
1709 | ||
1710 | switch (ARRAY_SIZE(a.array)) | |
1711 | { | |
1712 | case 1: | |
1713 | f.array[CpuAttrEnums / bps] | |
1714 | |= (a.array[0] >> CpuIsaBits) << (CpuAttrEnums % bps); | |
1715 | if (CpuAttrEnums % bps > CpuIsaBits) | |
1716 | f.array[CpuAttrEnums / bps + 1] | |
1717 | = (a.array[0] >> CpuIsaBits) >> (bps - CpuAttrEnums % bps); | |
1718 | break; | |
1719 | default: | |
1720 | abort (); | |
1721 | } | |
1722 | ||
1723 | if (a.bitfield.isa) | |
1724 | f.array[(a.bitfield.isa - 1) / bps] |= 1u << ((a.bitfield.isa - 1) % bps); | |
1725 | ||
1726 | return f; | |
1727 | } | |
1728 | ||
0dfbf9d7 L |
1729 | static INLINE int |
1730 | cpu_flags_all_zero (const union i386_cpu_flags *x) | |
1731 | { | |
1732 | switch (ARRAY_SIZE(x->array)) | |
1733 | { | |
75f8266a KL |
1734 | case 5: |
1735 | if (x->array[4]) | |
1736 | return 0; | |
1737 | /* Fall through. */ | |
53467f57 IT |
1738 | case 4: |
1739 | if (x->array[3]) | |
1740 | return 0; | |
1741 | /* Fall through. */ | |
0dfbf9d7 L |
1742 | case 3: |
1743 | if (x->array[2]) | |
1744 | return 0; | |
1a0670f3 | 1745 | /* Fall through. */ |
0dfbf9d7 L |
1746 | case 2: |
1747 | if (x->array[1]) | |
1748 | return 0; | |
1a0670f3 | 1749 | /* Fall through. */ |
0dfbf9d7 L |
1750 | case 1: |
1751 | return !x->array[0]; | |
1752 | default: | |
1753 | abort (); | |
1754 | } | |
1755 | } | |
1756 | ||
0dfbf9d7 L |
1757 | static INLINE int |
1758 | cpu_flags_equal (const union i386_cpu_flags *x, | |
1759 | const union i386_cpu_flags *y) | |
1760 | { | |
1761 | switch (ARRAY_SIZE(x->array)) | |
1762 | { | |
75f8266a KL |
1763 | case 5: |
1764 | if (x->array[4] != y->array[4]) | |
1765 | return 0; | |
1766 | /* Fall through. */ | |
53467f57 IT |
1767 | case 4: |
1768 | if (x->array[3] != y->array[3]) | |
1769 | return 0; | |
1770 | /* Fall through. */ | |
0dfbf9d7 L |
1771 | case 3: |
1772 | if (x->array[2] != y->array[2]) | |
1773 | return 0; | |
1a0670f3 | 1774 | /* Fall through. */ |
0dfbf9d7 L |
1775 | case 2: |
1776 | if (x->array[1] != y->array[1]) | |
1777 | return 0; | |
1a0670f3 | 1778 | /* Fall through. */ |
0dfbf9d7 L |
1779 | case 1: |
1780 | return x->array[0] == y->array[0]; | |
1781 | break; | |
1782 | default: | |
1783 | abort (); | |
1784 | } | |
1785 | } | |
c6fb90c8 L |
1786 | |
1787 | static INLINE int | |
c0260ac6 | 1788 | cpu_flags_check_cpu64 (const insn_template *t) |
c6fb90c8 | 1789 | { |
c0260ac6 JB |
1790 | return flag_code == CODE_64BIT |
1791 | ? !t->cpu.bitfield.cpuno64 | |
1792 | : !t->cpu.bitfield.cpu64; | |
40fb9820 L |
1793 | } |
1794 | ||
c6fb90c8 L |
1795 | static INLINE i386_cpu_flags |
1796 | cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1797 | { |
c6fb90c8 L |
1798 | switch (ARRAY_SIZE (x.array)) |
1799 | { | |
75f8266a KL |
1800 | case 5: |
1801 | x.array [4] &= y.array [4]; | |
1802 | /* Fall through. */ | |
53467f57 IT |
1803 | case 4: |
1804 | x.array [3] &= y.array [3]; | |
1805 | /* Fall through. */ | |
c6fb90c8 L |
1806 | case 3: |
1807 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1808 | /* Fall through. */ |
c6fb90c8 L |
1809 | case 2: |
1810 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1811 | /* Fall through. */ |
c6fb90c8 L |
1812 | case 1: |
1813 | x.array [0] &= y.array [0]; | |
1814 | break; | |
1815 | default: | |
1816 | abort (); | |
1817 | } | |
1818 | return x; | |
1819 | } | |
40fb9820 | 1820 | |
c6fb90c8 L |
1821 | static INLINE i386_cpu_flags |
1822 | cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y) | |
40fb9820 | 1823 | { |
c6fb90c8 | 1824 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 1825 | { |
75f8266a KL |
1826 | case 5: |
1827 | x.array [4] |= y.array [4]; | |
1828 | /* Fall through. */ | |
53467f57 IT |
1829 | case 4: |
1830 | x.array [3] |= y.array [3]; | |
1831 | /* Fall through. */ | |
c6fb90c8 L |
1832 | case 3: |
1833 | x.array [2] |= y.array [2]; | |
1a0670f3 | 1834 | /* Fall through. */ |
c6fb90c8 L |
1835 | case 2: |
1836 | x.array [1] |= y.array [1]; | |
1a0670f3 | 1837 | /* Fall through. */ |
c6fb90c8 L |
1838 | case 1: |
1839 | x.array [0] |= y.array [0]; | |
40fb9820 L |
1840 | break; |
1841 | default: | |
1842 | abort (); | |
1843 | } | |
40fb9820 L |
1844 | return x; |
1845 | } | |
1846 | ||
309d3373 JB |
1847 | static INLINE i386_cpu_flags |
1848 | cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y) | |
1849 | { | |
1850 | switch (ARRAY_SIZE (x.array)) | |
1851 | { | |
75f8266a KL |
1852 | case 5: |
1853 | x.array [4] &= ~y.array [4]; | |
1854 | /* Fall through. */ | |
53467f57 IT |
1855 | case 4: |
1856 | x.array [3] &= ~y.array [3]; | |
1857 | /* Fall through. */ | |
309d3373 JB |
1858 | case 3: |
1859 | x.array [2] &= ~y.array [2]; | |
1a0670f3 | 1860 | /* Fall through. */ |
309d3373 JB |
1861 | case 2: |
1862 | x.array [1] &= ~y.array [1]; | |
1a0670f3 | 1863 | /* Fall through. */ |
309d3373 JB |
1864 | case 1: |
1865 | x.array [0] &= ~y.array [0]; | |
1866 | break; | |
1867 | default: | |
1868 | abort (); | |
1869 | } | |
1870 | return x; | |
1871 | } | |
1872 | ||
6c0946d0 JB |
1873 | static const i386_cpu_flags avx512 = CPU_ANY_AVX512F_FLAGS; |
1874 | ||
c0f3af97 L |
1875 | #define CPU_FLAGS_ARCH_MATCH 0x1 |
1876 | #define CPU_FLAGS_64BIT_MATCH 0x2 | |
1877 | ||
c0f3af97 | 1878 | #define CPU_FLAGS_PERFECT_MATCH \ |
db12e14e | 1879 | (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH) |
c0f3af97 L |
1880 | |
1881 | /* Return CPU flags match bits. */ | |
3629bb00 | 1882 | |
40fb9820 | 1883 | static int |
d3ce72d0 | 1884 | cpu_flags_match (const insn_template *t) |
40fb9820 | 1885 | { |
734dfd1c | 1886 | i386_cpu_flags x = cpu_flags_from_attr (t->cpu); |
c0260ac6 | 1887 | int match = cpu_flags_check_cpu64 (t) ? CPU_FLAGS_64BIT_MATCH : 0; |
40fb9820 L |
1888 | |
1889 | x.bitfield.cpu64 = 0; | |
1890 | x.bitfield.cpuno64 = 0; | |
1891 | ||
0dfbf9d7 | 1892 | if (cpu_flags_all_zero (&x)) |
c0f3af97 L |
1893 | { |
1894 | /* This instruction is available on all archs. */ | |
db12e14e | 1895 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1896 | } |
3629bb00 L |
1897 | else |
1898 | { | |
c0f3af97 | 1899 | /* This instruction is available only on some archs. */ |
3629bb00 L |
1900 | i386_cpu_flags cpu = cpu_arch_flags; |
1901 | ||
ab592e75 JB |
1902 | /* AVX512VL is no standalone feature - match it and then strip it. */ |
1903 | if (x.bitfield.cpuavx512vl && !cpu.bitfield.cpuavx512vl) | |
1904 | return match; | |
1905 | x.bitfield.cpuavx512vl = 0; | |
1906 | ||
22c36940 JB |
1907 | /* AVX and AVX2 present at the same time express an operand size |
1908 | dependency - strip AVX2 for the purposes here. The operand size | |
1909 | dependent check occurs in check_vecOperands(). */ | |
1910 | if (x.bitfield.cpuavx && x.bitfield.cpuavx2) | |
1911 | x.bitfield.cpuavx2 = 0; | |
1912 | ||
3629bb00 | 1913 | cpu = cpu_flags_and (x, cpu); |
c0f3af97 L |
1914 | if (!cpu_flags_all_zero (&cpu)) |
1915 | { | |
57392598 | 1916 | if (x.bitfield.cpuavx) |
a5ff0eb2 | 1917 | { |
929f69fa | 1918 | /* We need to check a few extra flags with AVX. */ |
b9d49817 | 1919 | if (cpu.bitfield.cpuavx |
40d231b4 JB |
1920 | && (!t->opcode_modifier.sse2avx |
1921 | || (sse2avx && !i.prefix[DATA_PREFIX])) | |
b9d49817 | 1922 | && (!x.bitfield.cpuaes || cpu.bitfield.cpuaes) |
929f69fa | 1923 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) |
d54678eb | 1924 | && (!x.bitfield.cpupclmulqdq || cpu.bitfield.cpupclmulqdq)) |
b9d49817 | 1925 | match |= CPU_FLAGS_ARCH_MATCH; |
a5ff0eb2 | 1926 | } |
929f69fa JB |
1927 | else if (x.bitfield.cpuavx512f) |
1928 | { | |
1929 | /* We need to check a few extra flags with AVX512F. */ | |
1930 | if (cpu.bitfield.cpuavx512f | |
1931 | && (!x.bitfield.cpugfni || cpu.bitfield.cpugfni) | |
1932 | && (!x.bitfield.cpuvaes || cpu.bitfield.cpuvaes) | |
1933 | && (!x.bitfield.cpuvpclmulqdq || cpu.bitfield.cpuvpclmulqdq)) | |
1934 | match |= CPU_FLAGS_ARCH_MATCH; | |
1935 | } | |
a5ff0eb2 | 1936 | else |
db12e14e | 1937 | match |= CPU_FLAGS_ARCH_MATCH; |
c0f3af97 | 1938 | } |
3629bb00 | 1939 | } |
c0f3af97 | 1940 | return match; |
40fb9820 L |
1941 | } |
1942 | ||
c6fb90c8 L |
1943 | static INLINE i386_operand_type |
1944 | operand_type_and (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1945 | { |
bab6aec1 JB |
1946 | if (x.bitfield.class != y.bitfield.class) |
1947 | x.bitfield.class = ClassNone; | |
75e5731b JB |
1948 | if (x.bitfield.instance != y.bitfield.instance) |
1949 | x.bitfield.instance = InstanceNone; | |
bab6aec1 | 1950 | |
c6fb90c8 L |
1951 | switch (ARRAY_SIZE (x.array)) |
1952 | { | |
1953 | case 3: | |
1954 | x.array [2] &= y.array [2]; | |
1a0670f3 | 1955 | /* Fall through. */ |
c6fb90c8 L |
1956 | case 2: |
1957 | x.array [1] &= y.array [1]; | |
1a0670f3 | 1958 | /* Fall through. */ |
c6fb90c8 L |
1959 | case 1: |
1960 | x.array [0] &= y.array [0]; | |
1961 | break; | |
1962 | default: | |
1963 | abort (); | |
1964 | } | |
1965 | return x; | |
40fb9820 L |
1966 | } |
1967 | ||
73053c1f JB |
1968 | static INLINE i386_operand_type |
1969 | operand_type_and_not (i386_operand_type x, i386_operand_type y) | |
1970 | { | |
bab6aec1 | 1971 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 1972 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 1973 | |
73053c1f JB |
1974 | switch (ARRAY_SIZE (x.array)) |
1975 | { | |
1976 | case 3: | |
1977 | x.array [2] &= ~y.array [2]; | |
1978 | /* Fall through. */ | |
1979 | case 2: | |
1980 | x.array [1] &= ~y.array [1]; | |
1981 | /* Fall through. */ | |
1982 | case 1: | |
1983 | x.array [0] &= ~y.array [0]; | |
1984 | break; | |
1985 | default: | |
1986 | abort (); | |
1987 | } | |
1988 | return x; | |
1989 | } | |
1990 | ||
c6fb90c8 L |
1991 | static INLINE i386_operand_type |
1992 | operand_type_or (i386_operand_type x, i386_operand_type y) | |
40fb9820 | 1993 | { |
bab6aec1 JB |
1994 | gas_assert (x.bitfield.class == ClassNone || |
1995 | y.bitfield.class == ClassNone || | |
1996 | x.bitfield.class == y.bitfield.class); | |
75e5731b JB |
1997 | gas_assert (x.bitfield.instance == InstanceNone || |
1998 | y.bitfield.instance == InstanceNone || | |
1999 | x.bitfield.instance == y.bitfield.instance); | |
bab6aec1 | 2000 | |
c6fb90c8 | 2001 | switch (ARRAY_SIZE (x.array)) |
40fb9820 | 2002 | { |
c6fb90c8 L |
2003 | case 3: |
2004 | x.array [2] |= y.array [2]; | |
1a0670f3 | 2005 | /* Fall through. */ |
c6fb90c8 L |
2006 | case 2: |
2007 | x.array [1] |= y.array [1]; | |
1a0670f3 | 2008 | /* Fall through. */ |
c6fb90c8 L |
2009 | case 1: |
2010 | x.array [0] |= y.array [0]; | |
40fb9820 L |
2011 | break; |
2012 | default: | |
2013 | abort (); | |
2014 | } | |
c6fb90c8 L |
2015 | return x; |
2016 | } | |
40fb9820 | 2017 | |
c6fb90c8 L |
2018 | static INLINE i386_operand_type |
2019 | operand_type_xor (i386_operand_type x, i386_operand_type y) | |
2020 | { | |
bab6aec1 | 2021 | gas_assert (y.bitfield.class == ClassNone); |
75e5731b | 2022 | gas_assert (y.bitfield.instance == InstanceNone); |
bab6aec1 | 2023 | |
c6fb90c8 L |
2024 | switch (ARRAY_SIZE (x.array)) |
2025 | { | |
2026 | case 3: | |
2027 | x.array [2] ^= y.array [2]; | |
1a0670f3 | 2028 | /* Fall through. */ |
c6fb90c8 L |
2029 | case 2: |
2030 | x.array [1] ^= y.array [1]; | |
1a0670f3 | 2031 | /* Fall through. */ |
c6fb90c8 L |
2032 | case 1: |
2033 | x.array [0] ^= y.array [0]; | |
2034 | break; | |
2035 | default: | |
2036 | abort (); | |
2037 | } | |
40fb9820 L |
2038 | return x; |
2039 | } | |
2040 | ||
05909f23 JB |
2041 | static const i386_operand_type anydisp = { |
2042 | .bitfield = { .disp8 = 1, .disp16 = 1, .disp32 = 1, .disp64 = 1 } | |
2043 | }; | |
40fb9820 L |
2044 | |
2045 | enum operand_type | |
2046 | { | |
2047 | reg, | |
40fb9820 L |
2048 | imm, |
2049 | disp, | |
2050 | anymem | |
2051 | }; | |
2052 | ||
c6fb90c8 | 2053 | static INLINE int |
40fb9820 L |
2054 | operand_type_check (i386_operand_type t, enum operand_type c) |
2055 | { | |
2056 | switch (c) | |
2057 | { | |
2058 | case reg: | |
bab6aec1 | 2059 | return t.bitfield.class == Reg; |
40fb9820 | 2060 | |
40fb9820 L |
2061 | case imm: |
2062 | return (t.bitfield.imm8 | |
2063 | || t.bitfield.imm8s | |
2064 | || t.bitfield.imm16 | |
2065 | || t.bitfield.imm32 | |
2066 | || t.bitfield.imm32s | |
2067 | || t.bitfield.imm64); | |
2068 | ||
2069 | case disp: | |
2070 | return (t.bitfield.disp8 | |
2071 | || t.bitfield.disp16 | |
2072 | || t.bitfield.disp32 | |
40fb9820 L |
2073 | || t.bitfield.disp64); |
2074 | ||
2075 | case anymem: | |
2076 | return (t.bitfield.disp8 | |
2077 | || t.bitfield.disp16 | |
2078 | || t.bitfield.disp32 | |
40fb9820 L |
2079 | || t.bitfield.disp64 |
2080 | || t.bitfield.baseindex); | |
2081 | ||
2082 | default: | |
2083 | abort (); | |
2084 | } | |
2cfe26b6 AM |
2085 | |
2086 | return 0; | |
40fb9820 L |
2087 | } |
2088 | ||
7a54636a L |
2089 | /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size |
2090 | between operand GIVEN and opeand WANTED for instruction template T. */ | |
5c07affc L |
2091 | |
2092 | static INLINE int | |
7a54636a L |
2093 | match_operand_size (const insn_template *t, unsigned int wanted, |
2094 | unsigned int given) | |
5c07affc | 2095 | { |
3ac21baa JB |
2096 | return !((i.types[given].bitfield.byte |
2097 | && !t->operand_types[wanted].bitfield.byte) | |
2098 | || (i.types[given].bitfield.word | |
2099 | && !t->operand_types[wanted].bitfield.word) | |
2100 | || (i.types[given].bitfield.dword | |
2101 | && !t->operand_types[wanted].bitfield.dword) | |
2102 | || (i.types[given].bitfield.qword | |
9db83a32 JB |
2103 | && (!t->operand_types[wanted].bitfield.qword |
2104 | /* Don't allow 64-bit (memory) operands outside of 64-bit | |
2105 | mode, when they're used where a 64-bit GPR could also | |
2106 | be used. Checking is needed for Intel Syntax only. */ | |
2107 | || (intel_syntax | |
2108 | && flag_code != CODE_64BIT | |
2109 | && (t->operand_types[wanted].bitfield.class == Reg | |
2110 | || t->operand_types[wanted].bitfield.class == Accum | |
2111 | || t->opcode_modifier.isstring)))) | |
3ac21baa JB |
2112 | || (i.types[given].bitfield.tbyte |
2113 | && !t->operand_types[wanted].bitfield.tbyte)); | |
5c07affc L |
2114 | } |
2115 | ||
dd40ce22 L |
2116 | /* Return 1 if there is no conflict in SIMD register between operand |
2117 | GIVEN and opeand WANTED for instruction template T. */ | |
1b54b8d7 JB |
2118 | |
2119 | static INLINE int | |
dd40ce22 L |
2120 | match_simd_size (const insn_template *t, unsigned int wanted, |
2121 | unsigned int given) | |
1b54b8d7 | 2122 | { |
3ac21baa JB |
2123 | return !((i.types[given].bitfield.xmmword |
2124 | && !t->operand_types[wanted].bitfield.xmmword) | |
2125 | || (i.types[given].bitfield.ymmword | |
2126 | && !t->operand_types[wanted].bitfield.ymmword) | |
2127 | || (i.types[given].bitfield.zmmword | |
260cd341 LC |
2128 | && !t->operand_types[wanted].bitfield.zmmword) |
2129 | || (i.types[given].bitfield.tmmword | |
2130 | && !t->operand_types[wanted].bitfield.tmmword)); | |
1b54b8d7 JB |
2131 | } |
2132 | ||
7a54636a L |
2133 | /* Return 1 if there is no conflict in any size between operand GIVEN |
2134 | and opeand WANTED for instruction template T. */ | |
5c07affc L |
2135 | |
2136 | static INLINE int | |
dd40ce22 L |
2137 | match_mem_size (const insn_template *t, unsigned int wanted, |
2138 | unsigned int given) | |
5c07affc | 2139 | { |
7a54636a | 2140 | return (match_operand_size (t, wanted, given) |
3ac21baa | 2141 | && !((i.types[given].bitfield.unspecified |
5273a3cd | 2142 | && !i.broadcast.type |
a5748e0d | 2143 | && !i.broadcast.bytes |
3ac21baa JB |
2144 | && !t->operand_types[wanted].bitfield.unspecified) |
2145 | || (i.types[given].bitfield.fword | |
2146 | && !t->operand_types[wanted].bitfield.fword) | |
1b54b8d7 JB |
2147 | /* For scalar opcode templates to allow register and memory |
2148 | operands at the same time, some special casing is needed | |
d6793fa1 JB |
2149 | here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and |
2150 | down-conversion vpmov*. */ | |
3528c362 | 2151 | || ((t->operand_types[wanted].bitfield.class == RegSIMD |
bc49bfd8 JB |
2152 | && t->operand_types[wanted].bitfield.byte |
2153 | + t->operand_types[wanted].bitfield.word | |
2154 | + t->operand_types[wanted].bitfield.dword | |
2155 | + t->operand_types[wanted].bitfield.qword | |
2156 | > !!t->opcode_modifier.broadcast) | |
3ac21baa JB |
2157 | ? (i.types[given].bitfield.xmmword |
2158 | || i.types[given].bitfield.ymmword | |
2159 | || i.types[given].bitfield.zmmword) | |
2160 | : !match_simd_size(t, wanted, given)))); | |
5c07affc L |
2161 | } |
2162 | ||
3ac21baa JB |
2163 | /* Return value has MATCH_STRAIGHT set if there is no size conflict on any |
2164 | operands for instruction template T, and it has MATCH_REVERSE set if there | |
2165 | is no size conflict on any operands for the template with operands reversed | |
2166 | (and the template allows for reversing in the first place). */ | |
5c07affc | 2167 | |
3ac21baa JB |
2168 | #define MATCH_STRAIGHT 1 |
2169 | #define MATCH_REVERSE 2 | |
2170 | ||
2171 | static INLINE unsigned int | |
d3ce72d0 | 2172 | operand_size_match (const insn_template *t) |
5c07affc | 2173 | { |
3ac21baa | 2174 | unsigned int j, match = MATCH_STRAIGHT; |
5c07affc | 2175 | |
0cfa3eb3 | 2176 | /* Don't check non-absolute jump instructions. */ |
5c07affc | 2177 | if (t->opcode_modifier.jump |
0cfa3eb3 | 2178 | && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
5c07affc L |
2179 | return match; |
2180 | ||
2181 | /* Check memory and accumulator operand size. */ | |
2182 | for (j = 0; j < i.operands; j++) | |
2183 | { | |
3528c362 JB |
2184 | if (i.types[j].bitfield.class != Reg |
2185 | && i.types[j].bitfield.class != RegSIMD | |
255571cd | 2186 | && t->opcode_modifier.operandconstraint == ANY_SIZE) |
5c07affc L |
2187 | continue; |
2188 | ||
bab6aec1 | 2189 | if (t->operand_types[j].bitfield.class == Reg |
7a54636a | 2190 | && !match_operand_size (t, j, j)) |
5c07affc L |
2191 | { |
2192 | match = 0; | |
2193 | break; | |
2194 | } | |
2195 | ||
3528c362 | 2196 | if (t->operand_types[j].bitfield.class == RegSIMD |
3ac21baa | 2197 | && !match_simd_size (t, j, j)) |
1b54b8d7 JB |
2198 | { |
2199 | match = 0; | |
2200 | break; | |
2201 | } | |
2202 | ||
75e5731b | 2203 | if (t->operand_types[j].bitfield.instance == Accum |
7a54636a | 2204 | && (!match_operand_size (t, j, j) || !match_simd_size (t, j, j))) |
1b54b8d7 JB |
2205 | { |
2206 | match = 0; | |
2207 | break; | |
2208 | } | |
2209 | ||
c48dadc9 | 2210 | if ((i.flags[j] & Operand_Mem) && !match_mem_size (t, j, j)) |
5c07affc L |
2211 | { |
2212 | match = 0; | |
2213 | break; | |
2214 | } | |
2215 | } | |
2216 | ||
3ac21baa | 2217 | if (!t->opcode_modifier.d) |
7b94647a | 2218 | return match; |
5c07affc L |
2219 | |
2220 | /* Check reverse. */ | |
aa180741 | 2221 | gas_assert (i.operands >= 2); |
5c07affc | 2222 | |
f5eb1d70 | 2223 | for (j = 0; j < i.operands; j++) |
5c07affc | 2224 | { |
f5eb1d70 JB |
2225 | unsigned int given = i.operands - j - 1; |
2226 | ||
aa180741 | 2227 | /* For FMA4 and XOP insns VEX.W controls just the first two |
8bd915b7 | 2228 | register operands. */ |
734dfd1c | 2229 | if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)) |
8bd915b7 JB |
2230 | given = j < 2 ? 1 - j : j; |
2231 | ||
bab6aec1 | 2232 | if (t->operand_types[j].bitfield.class == Reg |
f5eb1d70 | 2233 | && !match_operand_size (t, j, given)) |
7b94647a | 2234 | return match; |
5c07affc | 2235 | |
3528c362 | 2236 | if (t->operand_types[j].bitfield.class == RegSIMD |
f5eb1d70 | 2237 | && !match_simd_size (t, j, given)) |
7b94647a | 2238 | return match; |
dbbc8b7e | 2239 | |
75e5731b | 2240 | if (t->operand_types[j].bitfield.instance == Accum |
f5eb1d70 JB |
2241 | && (!match_operand_size (t, j, given) |
2242 | || !match_simd_size (t, j, given))) | |
7b94647a | 2243 | return match; |
dbbc8b7e | 2244 | |
f5eb1d70 | 2245 | if ((i.flags[given] & Operand_Mem) && !match_mem_size (t, j, given)) |
7b94647a | 2246 | return match; |
5c07affc L |
2247 | } |
2248 | ||
3ac21baa | 2249 | return match | MATCH_REVERSE; |
5c07affc L |
2250 | } |
2251 | ||
c6fb90c8 | 2252 | static INLINE int |
40fb9820 L |
2253 | operand_type_match (i386_operand_type overlap, |
2254 | i386_operand_type given) | |
2255 | { | |
2256 | i386_operand_type temp = overlap; | |
2257 | ||
7d5e4556 | 2258 | temp.bitfield.unspecified = 0; |
5c07affc L |
2259 | temp.bitfield.byte = 0; |
2260 | temp.bitfield.word = 0; | |
2261 | temp.bitfield.dword = 0; | |
2262 | temp.bitfield.fword = 0; | |
2263 | temp.bitfield.qword = 0; | |
2264 | temp.bitfield.tbyte = 0; | |
2265 | temp.bitfield.xmmword = 0; | |
c0f3af97 | 2266 | temp.bitfield.ymmword = 0; |
43234a1e | 2267 | temp.bitfield.zmmword = 0; |
260cd341 | 2268 | temp.bitfield.tmmword = 0; |
0dfbf9d7 | 2269 | if (operand_type_all_zero (&temp)) |
891edac4 | 2270 | goto mismatch; |
40fb9820 | 2271 | |
6f2f06be | 2272 | if (given.bitfield.baseindex == overlap.bitfield.baseindex) |
891edac4 L |
2273 | return 1; |
2274 | ||
dc1e8a47 | 2275 | mismatch: |
a65babc9 | 2276 | i.error = operand_type_mismatch; |
891edac4 | 2277 | return 0; |
40fb9820 L |
2278 | } |
2279 | ||
7d5e4556 | 2280 | /* If given types g0 and g1 are registers they must be of the same type |
10c17abd | 2281 | unless the expected operand type register overlap is null. |
8ee52bcf | 2282 | Intel syntax sized memory operands are also checked here. */ |
40fb9820 | 2283 | |
c6fb90c8 | 2284 | static INLINE int |
dc821c5f | 2285 | operand_type_register_match (i386_operand_type g0, |
40fb9820 | 2286 | i386_operand_type t0, |
40fb9820 L |
2287 | i386_operand_type g1, |
2288 | i386_operand_type t1) | |
2289 | { | |
bab6aec1 | 2290 | if (g0.bitfield.class != Reg |
3528c362 | 2291 | && g0.bitfield.class != RegSIMD |
8ee52bcf JB |
2292 | && (g0.bitfield.unspecified |
2293 | || !operand_type_check (g0, anymem))) | |
40fb9820 L |
2294 | return 1; |
2295 | ||
bab6aec1 | 2296 | if (g1.bitfield.class != Reg |
3528c362 | 2297 | && g1.bitfield.class != RegSIMD |
8ee52bcf JB |
2298 | && (g1.bitfield.unspecified |
2299 | || !operand_type_check (g1, anymem))) | |
40fb9820 L |
2300 | return 1; |
2301 | ||
dc821c5f JB |
2302 | if (g0.bitfield.byte == g1.bitfield.byte |
2303 | && g0.bitfield.word == g1.bitfield.word | |
2304 | && g0.bitfield.dword == g1.bitfield.dword | |
10c17abd JB |
2305 | && g0.bitfield.qword == g1.bitfield.qword |
2306 | && g0.bitfield.xmmword == g1.bitfield.xmmword | |
2307 | && g0.bitfield.ymmword == g1.bitfield.ymmword | |
2308 | && g0.bitfield.zmmword == g1.bitfield.zmmword) | |
40fb9820 L |
2309 | return 1; |
2310 | ||
c4d09633 JB |
2311 | /* If expectations overlap in no more than a single size, all is fine. */ |
2312 | g0 = operand_type_and (t0, t1); | |
2313 | if (g0.bitfield.byte | |
2314 | + g0.bitfield.word | |
2315 | + g0.bitfield.dword | |
2316 | + g0.bitfield.qword | |
2317 | + g0.bitfield.xmmword | |
2318 | + g0.bitfield.ymmword | |
2319 | + g0.bitfield.zmmword <= 1) | |
891edac4 L |
2320 | return 1; |
2321 | ||
a65babc9 | 2322 | i.error = register_type_mismatch; |
891edac4 L |
2323 | |
2324 | return 0; | |
40fb9820 L |
2325 | } |
2326 | ||
4c692bc7 JB |
2327 | static INLINE unsigned int |
2328 | register_number (const reg_entry *r) | |
2329 | { | |
2330 | unsigned int nr = r->reg_num; | |
2331 | ||
2332 | if (r->reg_flags & RegRex) | |
2333 | nr += 8; | |
2334 | ||
200cbe0f L |
2335 | if (r->reg_flags & RegVRex) |
2336 | nr += 16; | |
2337 | ||
4c692bc7 JB |
2338 | return nr; |
2339 | } | |
2340 | ||
252b5132 | 2341 | static INLINE unsigned int |
40fb9820 | 2342 | mode_from_disp_size (i386_operand_type t) |
252b5132 | 2343 | { |
b5014f7a | 2344 | if (t.bitfield.disp8) |
40fb9820 L |
2345 | return 1; |
2346 | else if (t.bitfield.disp16 | |
a775efc8 | 2347 | || t.bitfield.disp32) |
40fb9820 L |
2348 | return 2; |
2349 | else | |
2350 | return 0; | |
252b5132 RH |
2351 | } |
2352 | ||
2353 | static INLINE int | |
65879393 | 2354 | fits_in_signed_byte (addressT num) |
252b5132 | 2355 | { |
65879393 | 2356 | return num + 0x80 <= 0xff; |
47926f60 | 2357 | } |
252b5132 RH |
2358 | |
2359 | static INLINE int | |
65879393 | 2360 | fits_in_unsigned_byte (addressT num) |
252b5132 | 2361 | { |
65879393 | 2362 | return num <= 0xff; |
47926f60 | 2363 | } |
252b5132 RH |
2364 | |
2365 | static INLINE int | |
65879393 | 2366 | fits_in_unsigned_word (addressT num) |
252b5132 | 2367 | { |
65879393 | 2368 | return num <= 0xffff; |
47926f60 | 2369 | } |
252b5132 RH |
2370 | |
2371 | static INLINE int | |
65879393 | 2372 | fits_in_signed_word (addressT num) |
252b5132 | 2373 | { |
65879393 | 2374 | return num + 0x8000 <= 0xffff; |
47926f60 | 2375 | } |
2a962e6d | 2376 | |
3e73aa7c | 2377 | static INLINE int |
65879393 | 2378 | fits_in_signed_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2379 | { |
2380 | #ifndef BFD64 | |
2381 | return 1; | |
2382 | #else | |
65879393 | 2383 | return num + 0x80000000 <= 0xffffffff; |
3e73aa7c JH |
2384 | #endif |
2385 | } /* fits_in_signed_long() */ | |
2a962e6d | 2386 | |
3e73aa7c | 2387 | static INLINE int |
65879393 | 2388 | fits_in_unsigned_long (addressT num ATTRIBUTE_UNUSED) |
3e73aa7c JH |
2389 | { |
2390 | #ifndef BFD64 | |
2391 | return 1; | |
2392 | #else | |
65879393 | 2393 | return num <= 0xffffffff; |
3e73aa7c JH |
2394 | #endif |
2395 | } /* fits_in_unsigned_long() */ | |
252b5132 | 2396 | |
a442cac5 JB |
2397 | static INLINE valueT extend_to_32bit_address (addressT num) |
2398 | { | |
2399 | #ifdef BFD64 | |
2400 | if (fits_in_unsigned_long(num)) | |
2401 | return (num ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); | |
2402 | ||
2403 | if (!fits_in_signed_long (num)) | |
2404 | return num & 0xffffffff; | |
2405 | #endif | |
2406 | ||
2407 | return num; | |
2408 | } | |
2409 | ||
43234a1e | 2410 | static INLINE int |
b5014f7a | 2411 | fits_in_disp8 (offsetT num) |
43234a1e L |
2412 | { |
2413 | int shift = i.memshift; | |
2414 | unsigned int mask; | |
2415 | ||
2416 | if (shift == -1) | |
2417 | abort (); | |
2418 | ||
2419 | mask = (1 << shift) - 1; | |
2420 | ||
2421 | /* Return 0 if NUM isn't properly aligned. */ | |
2422 | if ((num & mask)) | |
2423 | return 0; | |
2424 | ||
2425 | /* Check if NUM will fit in 8bit after shift. */ | |
2426 | return fits_in_signed_byte (num >> shift); | |
2427 | } | |
2428 | ||
a683cc34 SP |
2429 | static INLINE int |
2430 | fits_in_imm4 (offsetT num) | |
2431 | { | |
0ff3b7d0 JB |
2432 | /* Despite the name, check for imm3 if we're dealing with EVEX. */ |
2433 | return (num & (i.vec_encoding != vex_encoding_evex ? 0xf : 7)) == num; | |
a683cc34 SP |
2434 | } |
2435 | ||
40fb9820 | 2436 | static i386_operand_type |
e3bb37b5 | 2437 | smallest_imm_type (offsetT num) |
252b5132 | 2438 | { |
40fb9820 | 2439 | i386_operand_type t; |
7ab9ffdd | 2440 | |
0dfbf9d7 | 2441 | operand_type_set (&t, 0); |
40fb9820 L |
2442 | t.bitfield.imm64 = 1; |
2443 | ||
2444 | if (cpu_arch_tune != PROCESSOR_I486 && num == 1) | |
e413e4e9 AM |
2445 | { |
2446 | /* This code is disabled on the 486 because all the Imm1 forms | |
2447 | in the opcode table are slower on the i486. They're the | |
2448 | versions with the implicitly specified single-position | |
2449 | displacement, which has another syntax if you really want to | |
2450 | use that form. */ | |
40fb9820 L |
2451 | t.bitfield.imm1 = 1; |
2452 | t.bitfield.imm8 = 1; | |
2453 | t.bitfield.imm8s = 1; | |
2454 | t.bitfield.imm16 = 1; | |
2455 | t.bitfield.imm32 = 1; | |
2456 | t.bitfield.imm32s = 1; | |
2457 | } | |
2458 | else if (fits_in_signed_byte (num)) | |
2459 | { | |
c34d1cc9 JB |
2460 | if (fits_in_unsigned_byte (num)) |
2461 | t.bitfield.imm8 = 1; | |
40fb9820 L |
2462 | t.bitfield.imm8s = 1; |
2463 | t.bitfield.imm16 = 1; | |
2464 | t.bitfield.imm32 = 1; | |
2465 | t.bitfield.imm32s = 1; | |
2466 | } | |
2467 | else if (fits_in_unsigned_byte (num)) | |
2468 | { | |
2469 | t.bitfield.imm8 = 1; | |
2470 | t.bitfield.imm16 = 1; | |
2471 | t.bitfield.imm32 = 1; | |
2472 | t.bitfield.imm32s = 1; | |
2473 | } | |
2474 | else if (fits_in_signed_word (num) || fits_in_unsigned_word (num)) | |
2475 | { | |
2476 | t.bitfield.imm16 = 1; | |
2477 | t.bitfield.imm32 = 1; | |
2478 | t.bitfield.imm32s = 1; | |
2479 | } | |
2480 | else if (fits_in_signed_long (num)) | |
2481 | { | |
2482 | t.bitfield.imm32 = 1; | |
2483 | t.bitfield.imm32s = 1; | |
2484 | } | |
2485 | else if (fits_in_unsigned_long (num)) | |
2486 | t.bitfield.imm32 = 1; | |
2487 | ||
2488 | return t; | |
47926f60 | 2489 | } |
252b5132 | 2490 | |
847f7ad4 | 2491 | static offsetT |
e3bb37b5 | 2492 | offset_in_range (offsetT val, int size) |
847f7ad4 | 2493 | { |
508866be | 2494 | addressT mask; |
ba2adb93 | 2495 | |
847f7ad4 AM |
2496 | switch (size) |
2497 | { | |
508866be L |
2498 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
2499 | case 2: mask = ((addressT) 1 << 16) - 1; break; | |
3e73aa7c | 2500 | #ifdef BFD64 |
64965897 | 2501 | case 4: mask = ((addressT) 1 << 32) - 1; break; |
3e73aa7c | 2502 | #endif |
64965897 | 2503 | case sizeof (val): return val; |
47926f60 | 2504 | default: abort (); |
847f7ad4 AM |
2505 | } |
2506 | ||
4fe51f7d | 2507 | if ((val & ~mask) != 0 && (-val & ~mask) != 0) |
f493c217 AM |
2508 | as_warn (_("0x%" PRIx64 " shortened to 0x%" PRIx64), |
2509 | (uint64_t) val, (uint64_t) (val & mask)); | |
847f7ad4 | 2510 | |
847f7ad4 AM |
2511 | return val & mask; |
2512 | } | |
2513 | ||
76d3f746 JB |
2514 | static INLINE const char *insn_name (const insn_template *t) |
2515 | { | |
5c139202 | 2516 | return &i386_mnemonics[t->mnem_off]; |
76d3f746 JB |
2517 | } |
2518 | ||
c32fa91d L |
2519 | enum PREFIX_GROUP |
2520 | { | |
2521 | PREFIX_EXIST = 0, | |
2522 | PREFIX_LOCK, | |
2523 | PREFIX_REP, | |
04ef582a | 2524 | PREFIX_DS, |
c32fa91d L |
2525 | PREFIX_OTHER |
2526 | }; | |
2527 | ||
2528 | /* Returns | |
2529 | a. PREFIX_EXIST if attempting to add a prefix where one from the | |
2530 | same class already exists. | |
2531 | b. PREFIX_LOCK if lock prefix is added. | |
2532 | c. PREFIX_REP if rep/repne prefix is added. | |
04ef582a L |
2533 | d. PREFIX_DS if ds prefix is added. |
2534 | e. PREFIX_OTHER if other prefix is added. | |
c32fa91d L |
2535 | */ |
2536 | ||
2537 | static enum PREFIX_GROUP | |
e3bb37b5 | 2538 | add_prefix (unsigned int prefix) |
252b5132 | 2539 | { |
c32fa91d | 2540 | enum PREFIX_GROUP ret = PREFIX_OTHER; |
b1905489 | 2541 | unsigned int q; |
252b5132 | 2542 | |
29b0f896 AM |
2543 | if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 |
2544 | && flag_code == CODE_64BIT) | |
b1905489 | 2545 | { |
161a04f6 | 2546 | if ((i.prefix[REX_PREFIX] & prefix & REX_W) |
44846f29 JB |
2547 | || (i.prefix[REX_PREFIX] & prefix & REX_R) |
2548 | || (i.prefix[REX_PREFIX] & prefix & REX_X) | |
2549 | || (i.prefix[REX_PREFIX] & prefix & REX_B)) | |
c32fa91d | 2550 | ret = PREFIX_EXIST; |
b1905489 JB |
2551 | q = REX_PREFIX; |
2552 | } | |
3e73aa7c | 2553 | else |
b1905489 JB |
2554 | { |
2555 | switch (prefix) | |
2556 | { | |
2557 | default: | |
2558 | abort (); | |
2559 | ||
b1905489 | 2560 | case DS_PREFIX_OPCODE: |
04ef582a L |
2561 | ret = PREFIX_DS; |
2562 | /* Fall through. */ | |
2563 | case CS_PREFIX_OPCODE: | |
b1905489 JB |
2564 | case ES_PREFIX_OPCODE: |
2565 | case FS_PREFIX_OPCODE: | |
2566 | case GS_PREFIX_OPCODE: | |
2567 | case SS_PREFIX_OPCODE: | |
2568 | q = SEG_PREFIX; | |
2569 | break; | |
2570 | ||
2571 | case REPNE_PREFIX_OPCODE: | |
2572 | case REPE_PREFIX_OPCODE: | |
c32fa91d L |
2573 | q = REP_PREFIX; |
2574 | ret = PREFIX_REP; | |
2575 | break; | |
2576 | ||
b1905489 | 2577 | case LOCK_PREFIX_OPCODE: |
c32fa91d L |
2578 | q = LOCK_PREFIX; |
2579 | ret = PREFIX_LOCK; | |
b1905489 JB |
2580 | break; |
2581 | ||
2582 | case FWAIT_OPCODE: | |
2583 | q = WAIT_PREFIX; | |
2584 | break; | |
2585 | ||
2586 | case ADDR_PREFIX_OPCODE: | |
2587 | q = ADDR_PREFIX; | |
2588 | break; | |
2589 | ||
2590 | case DATA_PREFIX_OPCODE: | |
2591 | q = DATA_PREFIX; | |
2592 | break; | |
2593 | } | |
2594 | if (i.prefix[q] != 0) | |
c32fa91d | 2595 | ret = PREFIX_EXIST; |
b1905489 | 2596 | } |
252b5132 | 2597 | |
b1905489 | 2598 | if (ret) |
252b5132 | 2599 | { |
b1905489 JB |
2600 | if (!i.prefix[q]) |
2601 | ++i.prefixes; | |
2602 | i.prefix[q] |= prefix; | |
252b5132 | 2603 | } |
b1905489 JB |
2604 | else |
2605 | as_bad (_("same type of prefix used twice")); | |
252b5132 | 2606 | |
252b5132 RH |
2607 | return ret; |
2608 | } | |
2609 | ||
2610 | static void | |
78f12dd3 | 2611 | update_code_flag (int value, int check) |
eecb386c | 2612 | { |
b44fef84 JB |
2613 | PRINTF_LIKE ((*as_error)) = check ? as_fatal : as_bad; |
2614 | ||
da5f9eb4 | 2615 | if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpu64 ) |
b44fef84 JB |
2616 | { |
2617 | as_error (_("64bit mode not supported on `%s'."), | |
2618 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2619 | return; | |
2620 | } | |
2621 | ||
2622 | if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386) | |
2623 | { | |
2624 | as_error (_("32bit mode not supported on `%s'."), | |
2625 | cpu_arch_name ? cpu_arch_name : default_arch); | |
2626 | return; | |
2627 | } | |
78f12dd3 | 2628 | |
1e9cc1c2 | 2629 | flag_code = (enum flag_code) value; |
b44fef84 | 2630 | |
eecb386c AM |
2631 | stackop_size = '\0'; |
2632 | } | |
2633 | ||
78f12dd3 L |
2634 | static void |
2635 | set_code_flag (int value) | |
2636 | { | |
2637 | update_code_flag (value, 0); | |
2638 | } | |
2639 | ||
eecb386c | 2640 | static void |
e3bb37b5 | 2641 | set_16bit_gcc_code_flag (int new_code_flag) |
252b5132 | 2642 | { |
1e9cc1c2 | 2643 | flag_code = (enum flag_code) new_code_flag; |
40fb9820 L |
2644 | if (flag_code != CODE_16BIT) |
2645 | abort (); | |
9306ca4a | 2646 | stackop_size = LONG_MNEM_SUFFIX; |
252b5132 RH |
2647 | } |
2648 | ||
2649 | static void | |
e3bb37b5 | 2650 | set_intel_syntax (int syntax_flag) |
252b5132 RH |
2651 | { |
2652 | /* Find out if register prefixing is specified. */ | |
2653 | int ask_naked_reg = 0; | |
2654 | ||
2655 | SKIP_WHITESPACE (); | |
29b0f896 | 2656 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
252b5132 | 2657 | { |
d02603dc NC |
2658 | char *string; |
2659 | int e = get_symbol_name (&string); | |
252b5132 | 2660 | |
47926f60 | 2661 | if (strcmp (string, "prefix") == 0) |
252b5132 | 2662 | ask_naked_reg = 1; |
47926f60 | 2663 | else if (strcmp (string, "noprefix") == 0) |
252b5132 RH |
2664 | ask_naked_reg = -1; |
2665 | else | |
d0b47220 | 2666 | as_bad (_("bad argument to syntax directive.")); |
d02603dc | 2667 | (void) restore_line_pointer (e); |
252b5132 RH |
2668 | } |
2669 | demand_empty_rest_of_line (); | |
c3332e24 | 2670 | |
252b5132 RH |
2671 | intel_syntax = syntax_flag; |
2672 | ||
2673 | if (ask_naked_reg == 0) | |
f86103b7 AM |
2674 | allow_naked_reg = (intel_syntax |
2675 | && (bfd_get_symbol_leading_char (stdoutput) != '\0')); | |
252b5132 RH |
2676 | else |
2677 | allow_naked_reg = (ask_naked_reg < 0); | |
9306ca4a | 2678 | |
ee86248c | 2679 | expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0); |
7ab9ffdd | 2680 | |
e4a3b5a4 | 2681 | register_prefix = allow_naked_reg ? "" : "%"; |
252b5132 RH |
2682 | } |
2683 | ||
1efbbeb4 L |
2684 | static void |
2685 | set_intel_mnemonic (int mnemonic_flag) | |
2686 | { | |
e1d4d893 | 2687 | intel_mnemonic = mnemonic_flag; |
1efbbeb4 L |
2688 | } |
2689 | ||
db51cc60 L |
2690 | static void |
2691 | set_allow_index_reg (int flag) | |
2692 | { | |
2693 | allow_index_reg = flag; | |
2694 | } | |
2695 | ||
cb19c032 | 2696 | static void |
7bab8ab5 | 2697 | set_check (int what) |
cb19c032 | 2698 | { |
7bab8ab5 JB |
2699 | enum check_kind *kind; |
2700 | const char *str; | |
2701 | ||
2702 | if (what) | |
2703 | { | |
2704 | kind = &operand_check; | |
2705 | str = "operand"; | |
2706 | } | |
2707 | else | |
2708 | { | |
2709 | kind = &sse_check; | |
2710 | str = "sse"; | |
2711 | } | |
2712 | ||
cb19c032 L |
2713 | SKIP_WHITESPACE (); |
2714 | ||
2715 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
2716 | { | |
d02603dc NC |
2717 | char *string; |
2718 | int e = get_symbol_name (&string); | |
cb19c032 L |
2719 | |
2720 | if (strcmp (string, "none") == 0) | |
7bab8ab5 | 2721 | *kind = check_none; |
cb19c032 | 2722 | else if (strcmp (string, "warning") == 0) |
7bab8ab5 | 2723 | *kind = check_warning; |
cb19c032 | 2724 | else if (strcmp (string, "error") == 0) |
7bab8ab5 | 2725 | *kind = check_error; |
cb19c032 | 2726 | else |
7bab8ab5 | 2727 | as_bad (_("bad argument to %s_check directive."), str); |
d02603dc | 2728 | (void) restore_line_pointer (e); |
cb19c032 L |
2729 | } |
2730 | else | |
7bab8ab5 | 2731 | as_bad (_("missing argument for %s_check directive"), str); |
cb19c032 L |
2732 | |
2733 | demand_empty_rest_of_line (); | |
2734 | } | |
2735 | ||
8a9036a4 L |
2736 | static void |
2737 | check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED, | |
1e9cc1c2 | 2738 | i386_cpu_flags new_flag ATTRIBUTE_UNUSED) |
8a9036a4 L |
2739 | { |
2740 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
2741 | static const char *arch; | |
2742 | ||
c085ab00 | 2743 | /* Intel MCU is only supported on ELF. */ |
8a9036a4 L |
2744 | if (!IS_ELF) |
2745 | return; | |
2746 | ||
2747 | if (!arch) | |
2748 | { | |
2749 | /* Use cpu_arch_name if it is set in md_parse_option. Otherwise | |
2750 | use default_arch. */ | |
2751 | arch = cpu_arch_name; | |
2752 | if (!arch) | |
2753 | arch = default_arch; | |
2754 | } | |
2755 | ||
81486035 | 2756 | /* If we are targeting Intel MCU, we must enable it. */ |
648d04db JB |
2757 | if ((get_elf_backend_data (stdoutput)->elf_machine_code == EM_IAMCU) |
2758 | == new_flag.bitfield.cpuiamcu) | |
81486035 L |
2759 | return; |
2760 | ||
8a9036a4 L |
2761 | as_bad (_("`%s' is not supported on `%s'"), name, arch); |
2762 | #endif | |
2763 | } | |
2764 | ||
8180707f JB |
2765 | static void |
2766 | extend_cpu_sub_arch_name (const char *name) | |
2767 | { | |
2768 | if (cpu_sub_arch_name) | |
2769 | cpu_sub_arch_name = reconcat (cpu_sub_arch_name, cpu_sub_arch_name, | |
ae89daec | 2770 | ".", name, (const char *) NULL); |
8180707f | 2771 | else |
ae89daec | 2772 | cpu_sub_arch_name = concat (".", name, (const char *) NULL); |
8180707f JB |
2773 | } |
2774 | ||
e413e4e9 | 2775 | static void |
e3bb37b5 | 2776 | set_cpu_arch (int dummy ATTRIBUTE_UNUSED) |
e413e4e9 | 2777 | { |
f68697e8 JB |
2778 | typedef struct arch_stack_entry |
2779 | { | |
2780 | const struct arch_stack_entry *prev; | |
2781 | const char *name; | |
2782 | char *sub_name; | |
2783 | i386_cpu_flags flags; | |
2784 | i386_cpu_flags isa_flags; | |
2785 | enum processor_type isa; | |
2786 | enum flag_code flag_code; | |
4fc85f37 | 2787 | unsigned int vector_size; |
f68697e8 JB |
2788 | char stackop_size; |
2789 | bool no_cond_jump_promotion; | |
2790 | } arch_stack_entry; | |
2791 | static const arch_stack_entry *arch_stack_top; | |
dfab07b9 JB |
2792 | char *s; |
2793 | int e; | |
2794 | const char *string; | |
2795 | unsigned int j = 0; | |
2796 | i386_cpu_flags flags; | |
f68697e8 | 2797 | |
47926f60 | 2798 | SKIP_WHITESPACE (); |
e413e4e9 | 2799 | |
dfab07b9 JB |
2800 | if (is_end_of_line[(unsigned char) *input_line_pointer]) |
2801 | { | |
2802 | as_bad (_("missing cpu architecture")); | |
2803 | input_line_pointer++; | |
2804 | return; | |
2805 | } | |
2806 | ||
2807 | e = get_symbol_name (&s); | |
2808 | string = s; | |
2809 | ||
2810 | if (strcmp (string, "push") == 0) | |
e413e4e9 | 2811 | { |
dfab07b9 | 2812 | arch_stack_entry *top = XNEW (arch_stack_entry); |
e413e4e9 | 2813 | |
dfab07b9 JB |
2814 | top->name = cpu_arch_name; |
2815 | if (cpu_sub_arch_name) | |
2816 | top->sub_name = xstrdup (cpu_sub_arch_name); | |
2817 | else | |
2818 | top->sub_name = NULL; | |
2819 | top->flags = cpu_arch_flags; | |
2820 | top->isa = cpu_arch_isa; | |
2821 | top->isa_flags = cpu_arch_isa_flags; | |
2822 | top->flag_code = flag_code; | |
4fc85f37 | 2823 | top->vector_size = vector_size; |
dfab07b9 JB |
2824 | top->stackop_size = stackop_size; |
2825 | top->no_cond_jump_promotion = no_cond_jump_promotion; | |
2826 | ||
2827 | top->prev = arch_stack_top; | |
2828 | arch_stack_top = top; | |
2829 | ||
2830 | (void) restore_line_pointer (e); | |
2831 | demand_empty_rest_of_line (); | |
2832 | return; | |
2833 | } | |
2834 | ||
2835 | if (strcmp (string, "pop") == 0) | |
2836 | { | |
2837 | const arch_stack_entry *top = arch_stack_top; | |
2838 | ||
2839 | if (!top) | |
2840 | as_bad (_(".arch stack is empty")); | |
2841 | else if (top->flag_code != flag_code | |
2842 | || top->stackop_size != stackop_size) | |
2843 | { | |
2844 | static const unsigned int bits[] = { | |
2845 | [CODE_16BIT] = 16, | |
2846 | [CODE_32BIT] = 32, | |
2847 | [CODE_64BIT] = 64, | |
2848 | }; | |
2849 | ||
2850 | as_bad (_("this `.arch pop' requires `.code%u%s' to be in effect"), | |
2851 | bits[top->flag_code], | |
2852 | top->stackop_size == LONG_MNEM_SUFFIX ? "gcc" : ""); | |
2853 | } | |
2854 | else | |
3ce2ebcf | 2855 | { |
dfab07b9 JB |
2856 | arch_stack_top = top->prev; |
2857 | ||
2858 | cpu_arch_name = top->name; | |
2859 | free (cpu_sub_arch_name); | |
2860 | cpu_sub_arch_name = top->sub_name; | |
2861 | cpu_arch_flags = top->flags; | |
2862 | cpu_arch_isa = top->isa; | |
2863 | cpu_arch_isa_flags = top->isa_flags; | |
4fc85f37 | 2864 | vector_size = top->vector_size; |
dfab07b9 JB |
2865 | no_cond_jump_promotion = top->no_cond_jump_promotion; |
2866 | ||
2867 | XDELETE (top); | |
2868 | } | |
2869 | ||
2870 | (void) restore_line_pointer (e); | |
2871 | demand_empty_rest_of_line (); | |
2872 | return; | |
2873 | } | |
2874 | ||
2875 | if (strcmp (string, "default") == 0) | |
2876 | { | |
2877 | if (strcmp (default_arch, "iamcu") == 0) | |
2878 | string = default_arch; | |
2879 | else | |
2880 | { | |
2881 | static const i386_cpu_flags cpu_unknown_flags = CPU_UNKNOWN_FLAGS; | |
2882 | ||
2883 | cpu_arch_name = NULL; | |
2884 | free (cpu_sub_arch_name); | |
2885 | cpu_sub_arch_name = NULL; | |
2886 | cpu_arch_flags = cpu_unknown_flags; | |
dfab07b9 JB |
2887 | cpu_arch_isa = PROCESSOR_UNKNOWN; |
2888 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; | |
2889 | if (!cpu_arch_tune_set) | |
2890 | { | |
2891 | cpu_arch_tune = cpu_arch_isa; | |
2892 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2893 | } | |
2894 | ||
4fc85f37 JB |
2895 | vector_size = VSZ_DEFAULT; |
2896 | ||
dfab07b9 JB |
2897 | j = ARRAY_SIZE (cpu_arch) + 1; |
2898 | } | |
2899 | } | |
2900 | ||
2901 | for (; j < ARRAY_SIZE (cpu_arch); j++) | |
2902 | { | |
2903 | if (strcmp (string + (*string == '.'), cpu_arch[j].name) == 0 | |
2904 | && (*string == '.') == (cpu_arch[j].type == PROCESSOR_NONE)) | |
2905 | { | |
2906 | if (*string != '.') | |
2907 | { | |
2908 | check_cpu_arch_compatible (string, cpu_arch[j].enable); | |
3ce2ebcf | 2909 | |
da5f9eb4 | 2910 | if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpu64 ) |
1d07cfb4 JB |
2911 | { |
2912 | as_bad (_("64bit mode not supported on `%s'."), | |
2913 | cpu_arch[j].name); | |
2914 | (void) restore_line_pointer (e); | |
2915 | ignore_rest_of_line (); | |
2916 | return; | |
2917 | } | |
2918 | ||
2919 | if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386) | |
2920 | { | |
2921 | as_bad (_("32bit mode not supported on `%s'."), | |
2922 | cpu_arch[j].name); | |
2923 | (void) restore_line_pointer (e); | |
2924 | ignore_rest_of_line (); | |
2925 | return; | |
2926 | } | |
2927 | ||
dfab07b9 | 2928 | cpu_arch_name = cpu_arch[j].name; |
3ce2ebcf JB |
2929 | free (cpu_sub_arch_name); |
2930 | cpu_sub_arch_name = NULL; | |
dfab07b9 | 2931 | cpu_arch_flags = cpu_arch[j].enable; |
dfab07b9 JB |
2932 | cpu_arch_isa = cpu_arch[j].type; |
2933 | cpu_arch_isa_flags = cpu_arch[j].enable; | |
3ce2ebcf JB |
2934 | if (!cpu_arch_tune_set) |
2935 | { | |
2936 | cpu_arch_tune = cpu_arch_isa; | |
2937 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
2938 | } | |
4fc85f37 JB |
2939 | |
2940 | vector_size = VSZ_DEFAULT; | |
2941 | ||
dfab07b9 JB |
2942 | pre_386_16bit_warned = false; |
2943 | break; | |
3ce2ebcf | 2944 | } |
f68697e8 | 2945 | |
dfab07b9 JB |
2946 | if (cpu_flags_all_zero (&cpu_arch[j].enable)) |
2947 | continue; | |
f68697e8 | 2948 | |
dfab07b9 | 2949 | flags = cpu_flags_or (cpu_arch_flags, cpu_arch[j].enable); |
f68697e8 | 2950 | |
dfab07b9 | 2951 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
f68697e8 | 2952 | { |
dfab07b9 JB |
2953 | extend_cpu_sub_arch_name (string + 1); |
2954 | cpu_arch_flags = flags; | |
2955 | cpu_arch_isa_flags = flags; | |
f68697e8 JB |
2956 | } |
2957 | else | |
dfab07b9 JB |
2958 | cpu_arch_isa_flags |
2959 | = cpu_flags_or (cpu_arch_isa_flags, cpu_arch[j].enable); | |
f68697e8 JB |
2960 | |
2961 | (void) restore_line_pointer (e); | |
4fc85f37 JB |
2962 | |
2963 | switch (cpu_arch[j].vsz) | |
2964 | { | |
2965 | default: | |
2966 | break; | |
2967 | ||
2968 | case vsz_set: | |
2969 | #ifdef SVR4_COMMENT_CHARS | |
2970 | if (*input_line_pointer == ':' || *input_line_pointer == '/') | |
2971 | #else | |
2972 | if (*input_line_pointer == '/') | |
2973 | #endif | |
2974 | { | |
2975 | ++input_line_pointer; | |
2976 | switch (get_absolute_expression ()) | |
2977 | { | |
2978 | case 512: vector_size = VSZ512; break; | |
2979 | case 256: vector_size = VSZ256; break; | |
2980 | case 128: vector_size = VSZ128; break; | |
2981 | default: | |
2982 | as_bad (_("Unrecognized vector size specifier")); | |
2983 | ignore_rest_of_line (); | |
2984 | return; | |
2985 | } | |
2986 | break; | |
2987 | } | |
2988 | /* Fall through. */ | |
2989 | case vsz_reset: | |
2990 | vector_size = VSZ_DEFAULT; | |
2991 | break; | |
2992 | } | |
2993 | ||
f68697e8 JB |
2994 | demand_empty_rest_of_line (); |
2995 | return; | |
2996 | } | |
dfab07b9 | 2997 | } |
3ce2ebcf | 2998 | |
dfab07b9 JB |
2999 | if (startswith (string, ".no") && j >= ARRAY_SIZE (cpu_arch)) |
3000 | { | |
3001 | /* Disable an ISA extension. */ | |
3002 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) | |
3003 | if (cpu_arch[j].type == PROCESSOR_NONE | |
3004 | && strcmp (string + 3, cpu_arch[j].name) == 0) | |
3005 | { | |
3006 | flags = cpu_flags_and_not (cpu_arch_flags, cpu_arch[j].disable); | |
3007 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) | |
293f5f65 | 3008 | { |
dfab07b9 JB |
3009 | extend_cpu_sub_arch_name (string + 1); |
3010 | cpu_arch_flags = flags; | |
3011 | cpu_arch_isa_flags = flags; | |
293f5f65 | 3012 | } |
e413e4e9 | 3013 | |
4fc85f37 JB |
3014 | if (cpu_arch[j].vsz == vsz_set) |
3015 | vector_size = VSZ_DEFAULT; | |
3016 | ||
dfab07b9 JB |
3017 | (void) restore_line_pointer (e); |
3018 | demand_empty_rest_of_line (); | |
3019 | return; | |
3020 | } | |
e413e4e9 | 3021 | } |
dfab07b9 JB |
3022 | |
3023 | if (j == ARRAY_SIZE (cpu_arch)) | |
3024 | as_bad (_("no such architecture: `%s'"), string); | |
3025 | ||
3026 | *input_line_pointer = e; | |
e413e4e9 | 3027 | |
fddf5b5b AM |
3028 | no_cond_jump_promotion = 0; |
3029 | if (*input_line_pointer == ',' | |
29b0f896 | 3030 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
fddf5b5b | 3031 | { |
d02603dc | 3032 | ++input_line_pointer; |
dfab07b9 JB |
3033 | e = get_symbol_name (&s); |
3034 | string = s; | |
fddf5b5b AM |
3035 | |
3036 | if (strcmp (string, "nojumps") == 0) | |
3037 | no_cond_jump_promotion = 1; | |
3038 | else if (strcmp (string, "jumps") == 0) | |
3039 | ; | |
3040 | else | |
3041 | as_bad (_("no such architecture modifier: `%s'"), string); | |
3042 | ||
d02603dc | 3043 | (void) restore_line_pointer (e); |
fddf5b5b AM |
3044 | } |
3045 | ||
e413e4e9 AM |
3046 | demand_empty_rest_of_line (); |
3047 | } | |
3048 | ||
8a9036a4 L |
3049 | enum bfd_architecture |
3050 | i386_arch (void) | |
3051 | { | |
c085ab00 | 3052 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
3053 | { |
3054 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour | |
3055 | || flag_code == CODE_64BIT) | |
3056 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3057 | return bfd_arch_iamcu; | |
3058 | } | |
8a9036a4 L |
3059 | else |
3060 | return bfd_arch_i386; | |
3061 | } | |
3062 | ||
b9d79e03 | 3063 | unsigned long |
7016a5d5 | 3064 | i386_mach (void) |
b9d79e03 | 3065 | { |
d34049e8 | 3066 | if (startswith (default_arch, "x86_64")) |
8a9036a4 | 3067 | { |
c085ab00 | 3068 | if (default_arch[6] == '\0') |
8a9036a4 | 3069 | return bfd_mach_x86_64; |
351f65ca L |
3070 | else |
3071 | return bfd_mach_x64_32; | |
8a9036a4 | 3072 | } |
5197d474 L |
3073 | else if (!strcmp (default_arch, "i386") |
3074 | || !strcmp (default_arch, "iamcu")) | |
81486035 L |
3075 | { |
3076 | if (cpu_arch_isa == PROCESSOR_IAMCU) | |
3077 | { | |
3078 | if (OUTPUT_FLAVOR != bfd_target_elf_flavour) | |
3079 | as_fatal (_("Intel MCU is 32bit ELF only")); | |
3080 | return bfd_mach_i386_iamcu; | |
3081 | } | |
3082 | else | |
3083 | return bfd_mach_i386_i386; | |
3084 | } | |
b9d79e03 | 3085 | else |
2b5d6a91 | 3086 | as_fatal (_("unknown architecture")); |
b9d79e03 | 3087 | } |
b9d79e03 | 3088 | \f |
99f0fb12 JB |
3089 | #include "opcodes/i386-tbl.h" |
3090 | ||
252b5132 | 3091 | void |
7016a5d5 | 3092 | md_begin (void) |
252b5132 | 3093 | { |
86fa6981 L |
3094 | /* Support pseudo prefixes like {disp32}. */ |
3095 | lex_type ['{'] = LEX_BEGIN_NAME; | |
3096 | ||
47926f60 | 3097 | /* Initialize op_hash hash table. */ |
629310ab | 3098 | op_hash = str_htab_create (); |
252b5132 RH |
3099 | |
3100 | { | |
65f440c8 JB |
3101 | const insn_template *const *sets = i386_op_sets; |
3102 | const insn_template *const *end = sets + ARRAY_SIZE (i386_op_sets) - 1; | |
3103 | ||
3104 | /* Type checks to compensate for the conversion through void * which | |
3105 | occurs during hash table insertion / lookup. */ | |
eb993861 JB |
3106 | (void) sizeof (sets == ¤t_templates->start); |
3107 | (void) sizeof (end == ¤t_templates->end); | |
65f440c8 | 3108 | for (; sets < end; ++sets) |
76d3f746 JB |
3109 | if (str_hash_insert (op_hash, insn_name (*sets), sets, 0)) |
3110 | as_fatal (_("duplicate %s"), insn_name (*sets)); | |
252b5132 RH |
3111 | } |
3112 | ||
47926f60 | 3113 | /* Initialize reg_hash hash table. */ |
629310ab | 3114 | reg_hash = str_htab_create (); |
252b5132 | 3115 | { |
29b0f896 | 3116 | const reg_entry *regtab; |
c3fe08fa | 3117 | unsigned int regtab_size = i386_regtab_size; |
252b5132 | 3118 | |
c3fe08fa | 3119 | for (regtab = i386_regtab; regtab_size--; regtab++) |
6225c532 | 3120 | { |
6288d05f JB |
3121 | switch (regtab->reg_type.bitfield.class) |
3122 | { | |
3123 | case Reg: | |
34684862 JB |
3124 | if (regtab->reg_type.bitfield.dword) |
3125 | { | |
3126 | if (regtab->reg_type.bitfield.instance == Accum) | |
3127 | reg_eax = regtab; | |
3128 | } | |
3129 | else if (regtab->reg_type.bitfield.tbyte) | |
6288d05f JB |
3130 | { |
3131 | /* There's no point inserting st(<N>) in the hash table, as | |
3132 | parentheses aren't included in register_chars[] anyway. */ | |
3133 | if (regtab->reg_type.bitfield.instance != Accum) | |
3134 | continue; | |
3135 | reg_st0 = regtab; | |
3136 | } | |
3137 | break; | |
3138 | ||
5e042380 JB |
3139 | case SReg: |
3140 | switch (regtab->reg_num) | |
3141 | { | |
3142 | case 0: reg_es = regtab; break; | |
3143 | case 2: reg_ss = regtab; break; | |
3144 | case 3: reg_ds = regtab; break; | |
3145 | } | |
3146 | break; | |
3147 | ||
6288d05f JB |
3148 | case RegMask: |
3149 | if (!regtab->reg_num) | |
3150 | reg_k0 = regtab; | |
3151 | break; | |
3152 | } | |
3153 | ||
6225c532 JB |
3154 | if (str_hash_insert (reg_hash, regtab->reg_name, regtab, 0) != NULL) |
3155 | as_fatal (_("duplicate %s"), regtab->reg_name); | |
6225c532 | 3156 | } |
252b5132 RH |
3157 | } |
3158 | ||
47926f60 | 3159 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
252b5132 | 3160 | { |
29b0f896 | 3161 | int c; |
d2b1a14d | 3162 | const char *p; |
252b5132 RH |
3163 | |
3164 | for (c = 0; c < 256; c++) | |
3165 | { | |
014fbcda | 3166 | if (ISDIGIT (c) || ISLOWER (c)) |
252b5132 RH |
3167 | { |
3168 | mnemonic_chars[c] = c; | |
3169 | register_chars[c] = c; | |
3170 | operand_chars[c] = c; | |
3171 | } | |
3882b010 | 3172 | else if (ISUPPER (c)) |
252b5132 | 3173 | { |
3882b010 | 3174 | mnemonic_chars[c] = TOLOWER (c); |
252b5132 RH |
3175 | register_chars[c] = mnemonic_chars[c]; |
3176 | operand_chars[c] = c; | |
3177 | } | |
b3983e5f JB |
3178 | #ifdef SVR4_COMMENT_CHARS |
3179 | else if (c == '\\' && strchr (i386_comment_chars, '/')) | |
3180 | operand_chars[c] = c; | |
3181 | #endif | |
252b5132 | 3182 | |
4795cd4a JB |
3183 | if (c >= 128) |
3184 | operand_chars[c] = c; | |
252b5132 RH |
3185 | } |
3186 | ||
c0f3af97 | 3187 | mnemonic_chars['_'] = '_'; |
791fe849 | 3188 | mnemonic_chars['-'] = '-'; |
0003779b | 3189 | mnemonic_chars['.'] = '.'; |
252b5132 | 3190 | |
d2b1a14d JB |
3191 | for (p = extra_symbol_chars; *p != '\0'; p++) |
3192 | operand_chars[(unsigned char) *p] = *p; | |
252b5132 RH |
3193 | for (p = operand_special_chars; *p != '\0'; p++) |
3194 | operand_chars[(unsigned char) *p] = *p; | |
3195 | } | |
3196 | ||
a4447b93 RH |
3197 | if (flag_code == CODE_64BIT) |
3198 | { | |
ca19b261 KT |
3199 | #if defined (OBJ_COFF) && defined (TE_PE) |
3200 | x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour | |
3201 | ? 32 : 16); | |
3202 | #else | |
a4447b93 | 3203 | x86_dwarf2_return_column = 16; |
ca19b261 | 3204 | #endif |
61ff971f | 3205 | x86_cie_data_alignment = -8; |
b52c4ee4 IB |
3206 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3207 | x86_sframe_cfa_sp_reg = 7; | |
3208 | x86_sframe_cfa_fp_reg = 6; | |
3209 | #endif | |
a4447b93 RH |
3210 | } |
3211 | else | |
3212 | { | |
3213 | x86_dwarf2_return_column = 8; | |
3214 | x86_cie_data_alignment = -4; | |
3215 | } | |
e379e5f3 L |
3216 | |
3217 | /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it | |
3218 | can be turned into BRANCH_PREFIX frag. */ | |
3219 | if (align_branch_prefix_size > MAX_FUSED_JCC_PADDING_SIZE) | |
3220 | abort (); | |
252b5132 RH |
3221 | } |
3222 | ||
3223 | void | |
e3bb37b5 | 3224 | i386_print_statistics (FILE *file) |
252b5132 | 3225 | { |
629310ab ML |
3226 | htab_print_statistics (file, "i386 opcode", op_hash); |
3227 | htab_print_statistics (file, "i386 register", reg_hash); | |
252b5132 | 3228 | } |
654d6f31 AM |
3229 | |
3230 | void | |
3231 | i386_md_end (void) | |
3232 | { | |
3233 | htab_delete (op_hash); | |
3234 | htab_delete (reg_hash); | |
3235 | } | |
252b5132 | 3236 | \f |
252b5132 RH |
3237 | #ifdef DEBUG386 |
3238 | ||
ce8a8b2f | 3239 | /* Debugging routines for md_assemble. */ |
d3ce72d0 | 3240 | static void pte (insn_template *); |
40fb9820 | 3241 | static void pt (i386_operand_type); |
e3bb37b5 L |
3242 | static void pe (expressionS *); |
3243 | static void ps (symbolS *); | |
252b5132 RH |
3244 | |
3245 | static void | |
2c703856 | 3246 | pi (const char *line, i386_insn *x) |
252b5132 | 3247 | { |
09137c09 | 3248 | unsigned int j; |
252b5132 RH |
3249 | |
3250 | fprintf (stdout, "%s: template ", line); | |
3251 | pte (&x->tm); | |
09f131f2 JH |
3252 | fprintf (stdout, " address: base %s index %s scale %x\n", |
3253 | x->base_reg ? x->base_reg->reg_name : "none", | |
3254 | x->index_reg ? x->index_reg->reg_name : "none", | |
3255 | x->log2_scale_factor); | |
3256 | fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", | |
252b5132 | 3257 | x->rm.mode, x->rm.reg, x->rm.regmem); |
09f131f2 JH |
3258 | fprintf (stdout, " sib: base %x index %x scale %x\n", |
3259 | x->sib.base, x->sib.index, x->sib.scale); | |
3260 | fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", | |
161a04f6 L |
3261 | (x->rex & REX_W) != 0, |
3262 | (x->rex & REX_R) != 0, | |
3263 | (x->rex & REX_X) != 0, | |
3264 | (x->rex & REX_B) != 0); | |
09137c09 | 3265 | for (j = 0; j < x->operands; j++) |
252b5132 | 3266 | { |
09137c09 SP |
3267 | fprintf (stdout, " #%d: ", j + 1); |
3268 | pt (x->types[j]); | |
252b5132 | 3269 | fprintf (stdout, "\n"); |
bab6aec1 | 3270 | if (x->types[j].bitfield.class == Reg |
3528c362 JB |
3271 | || x->types[j].bitfield.class == RegMMX |
3272 | || x->types[j].bitfield.class == RegSIMD | |
dd6b8a0b | 3273 | || x->types[j].bitfield.class == RegMask |
00cee14f | 3274 | || x->types[j].bitfield.class == SReg |
4a5c67ed JB |
3275 | || x->types[j].bitfield.class == RegCR |
3276 | || x->types[j].bitfield.class == RegDR | |
dd6b8a0b JB |
3277 | || x->types[j].bitfield.class == RegTR |
3278 | || x->types[j].bitfield.class == RegBND) | |
09137c09 SP |
3279 | fprintf (stdout, "%s\n", x->op[j].regs->reg_name); |
3280 | if (operand_type_check (x->types[j], imm)) | |
3281 | pe (x->op[j].imms); | |
3282 | if (operand_type_check (x->types[j], disp)) | |
3283 | pe (x->op[j].disps); | |
252b5132 RH |
3284 | } |
3285 | } | |
3286 | ||
3287 | static void | |
d3ce72d0 | 3288 | pte (insn_template *t) |
252b5132 | 3289 | { |
b933fa4b | 3290 | static const unsigned char opc_pfx[] = { 0, 0x66, 0xf3, 0xf2 }; |
441f6aca | 3291 | static const char *const opc_spc[] = { |
0cc78721 | 3292 | NULL, "0f", "0f38", "0f3a", NULL, "evexmap5", "evexmap6", NULL, |
441f6aca JB |
3293 | "XOP08", "XOP09", "XOP0A", |
3294 | }; | |
09137c09 | 3295 | unsigned int j; |
441f6aca | 3296 | |
252b5132 | 3297 | fprintf (stdout, " %d operands ", t->operands); |
441f6aca JB |
3298 | if (opc_pfx[t->opcode_modifier.opcodeprefix]) |
3299 | fprintf (stdout, "pfx %x ", opc_pfx[t->opcode_modifier.opcodeprefix]); | |
ddb62495 JB |
3300 | if (opc_spc[t->opcode_space]) |
3301 | fprintf (stdout, "space %s ", opc_spc[t->opcode_space]); | |
47926f60 | 3302 | fprintf (stdout, "opcode %x ", t->base_opcode); |
252b5132 RH |
3303 | if (t->extension_opcode != None) |
3304 | fprintf (stdout, "ext %x ", t->extension_opcode); | |
40fb9820 | 3305 | if (t->opcode_modifier.d) |
252b5132 | 3306 | fprintf (stdout, "D"); |
40fb9820 | 3307 | if (t->opcode_modifier.w) |
252b5132 RH |
3308 | fprintf (stdout, "W"); |
3309 | fprintf (stdout, "\n"); | |
09137c09 | 3310 | for (j = 0; j < t->operands; j++) |
252b5132 | 3311 | { |
09137c09 SP |
3312 | fprintf (stdout, " #%d type ", j + 1); |
3313 | pt (t->operand_types[j]); | |
252b5132 RH |
3314 | fprintf (stdout, "\n"); |
3315 | } | |
3316 | } | |
3317 | ||
3318 | static void | |
e3bb37b5 | 3319 | pe (expressionS *e) |
252b5132 | 3320 | { |
24eab124 | 3321 | fprintf (stdout, " operation %d\n", e->X_op); |
b8281767 AM |
3322 | fprintf (stdout, " add_number %" PRId64 " (%" PRIx64 ")\n", |
3323 | (int64_t) e->X_add_number, (uint64_t) (valueT) e->X_add_number); | |
252b5132 RH |
3324 | if (e->X_add_symbol) |
3325 | { | |
3326 | fprintf (stdout, " add_symbol "); | |
3327 | ps (e->X_add_symbol); | |
3328 | fprintf (stdout, "\n"); | |
3329 | } | |
3330 | if (e->X_op_symbol) | |
3331 | { | |
3332 | fprintf (stdout, " op_symbol "); | |
3333 | ps (e->X_op_symbol); | |
3334 | fprintf (stdout, "\n"); | |
3335 | } | |
3336 | } | |
3337 | ||
3338 | static void | |
e3bb37b5 | 3339 | ps (symbolS *s) |
252b5132 RH |
3340 | { |
3341 | fprintf (stdout, "%s type %s%s", | |
3342 | S_GET_NAME (s), | |
3343 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", | |
3344 | segment_name (S_GET_SEGMENT (s))); | |
3345 | } | |
3346 | ||
7b81dfbb | 3347 | static struct type_name |
252b5132 | 3348 | { |
40fb9820 L |
3349 | i386_operand_type mask; |
3350 | const char *name; | |
252b5132 | 3351 | } |
7b81dfbb | 3352 | const type_names[] = |
252b5132 | 3353 | { |
05909f23 JB |
3354 | { { .bitfield = { .class = Reg, .byte = 1 } }, "r8" }, |
3355 | { { .bitfield = { .class = Reg, .word = 1 } }, "r16" }, | |
3356 | { { .bitfield = { .class = Reg, .dword = 1 } }, "r32" }, | |
3357 | { { .bitfield = { .class = Reg, .qword = 1 } }, "r64" }, | |
3358 | { { .bitfield = { .instance = Accum, .byte = 1 } }, "acc8" }, | |
3359 | { { .bitfield = { .instance = Accum, .word = 1 } }, "acc16" }, | |
3360 | { { .bitfield = { .instance = Accum, .dword = 1 } }, "acc32" }, | |
3361 | { { .bitfield = { .instance = Accum, .qword = 1 } }, "acc64" }, | |
3362 | { { .bitfield = { .imm8 = 1 } }, "i8" }, | |
3363 | { { .bitfield = { .imm8s = 1 } }, "i8s" }, | |
3364 | { { .bitfield = { .imm16 = 1 } }, "i16" }, | |
3365 | { { .bitfield = { .imm32 = 1 } }, "i32" }, | |
3366 | { { .bitfield = { .imm32s = 1 } }, "i32s" }, | |
3367 | { { .bitfield = { .imm64 = 1 } }, "i64" }, | |
3368 | { { .bitfield = { .imm1 = 1 } }, "i1" }, | |
3369 | { { .bitfield = { .baseindex = 1 } }, "BaseIndex" }, | |
3370 | { { .bitfield = { .disp8 = 1 } }, "d8" }, | |
3371 | { { .bitfield = { .disp16 = 1 } }, "d16" }, | |
3372 | { { .bitfield = { .disp32 = 1 } }, "d32" }, | |
3373 | { { .bitfield = { .disp64 = 1 } }, "d64" }, | |
3374 | { { .bitfield = { .instance = RegD, .word = 1 } }, "InOutPortReg" }, | |
3375 | { { .bitfield = { .instance = RegC, .byte = 1 } }, "ShiftCount" }, | |
3376 | { { .bitfield = { .class = RegCR } }, "control reg" }, | |
3377 | { { .bitfield = { .class = RegTR } }, "test reg" }, | |
3378 | { { .bitfield = { .class = RegDR } }, "debug reg" }, | |
3379 | { { .bitfield = { .class = Reg, .tbyte = 1 } }, "FReg" }, | |
3380 | { { .bitfield = { .instance = Accum, .tbyte = 1 } }, "FAcc" }, | |
3381 | { { .bitfield = { .class = SReg } }, "SReg" }, | |
3382 | { { .bitfield = { .class = RegMMX } }, "rMMX" }, | |
3383 | { { .bitfield = { .class = RegSIMD, .xmmword = 1 } }, "rXMM" }, | |
3384 | { { .bitfield = { .class = RegSIMD, .ymmword = 1 } }, "rYMM" }, | |
3385 | { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" }, | |
3386 | { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" }, | |
3387 | { { .bitfield = { .class = RegMask } }, "Mask reg" }, | |
252b5132 RH |
3388 | }; |
3389 | ||
3390 | static void | |
40fb9820 | 3391 | pt (i386_operand_type t) |
252b5132 | 3392 | { |
40fb9820 | 3393 | unsigned int j; |
c6fb90c8 | 3394 | i386_operand_type a; |
252b5132 | 3395 | |
40fb9820 | 3396 | for (j = 0; j < ARRAY_SIZE (type_names); j++) |
c6fb90c8 L |
3397 | { |
3398 | a = operand_type_and (t, type_names[j].mask); | |
2c703856 | 3399 | if (operand_type_equal (&a, &type_names[j].mask)) |
c6fb90c8 L |
3400 | fprintf (stdout, "%s, ", type_names[j].name); |
3401 | } | |
252b5132 RH |
3402 | fflush (stdout); |
3403 | } | |
3404 | ||
3405 | #endif /* DEBUG386 */ | |
3406 | \f | |
252b5132 | 3407 | static bfd_reloc_code_real_type |
3956db08 | 3408 | reloc (unsigned int size, |
64e74474 AM |
3409 | int pcrel, |
3410 | int sign, | |
3411 | bfd_reloc_code_real_type other) | |
252b5132 | 3412 | { |
47926f60 | 3413 | if (other != NO_RELOC) |
3956db08 | 3414 | { |
91d6fa6a | 3415 | reloc_howto_type *rel; |
3956db08 JB |
3416 | |
3417 | if (size == 8) | |
3418 | switch (other) | |
3419 | { | |
64e74474 AM |
3420 | case BFD_RELOC_X86_64_GOT32: |
3421 | return BFD_RELOC_X86_64_GOT64; | |
3422 | break; | |
553d1284 L |
3423 | case BFD_RELOC_X86_64_GOTPLT64: |
3424 | return BFD_RELOC_X86_64_GOTPLT64; | |
3425 | break; | |
64e74474 AM |
3426 | case BFD_RELOC_X86_64_PLTOFF64: |
3427 | return BFD_RELOC_X86_64_PLTOFF64; | |
3428 | break; | |
3429 | case BFD_RELOC_X86_64_GOTPC32: | |
3430 | other = BFD_RELOC_X86_64_GOTPC64; | |
3431 | break; | |
3432 | case BFD_RELOC_X86_64_GOTPCREL: | |
3433 | other = BFD_RELOC_X86_64_GOTPCREL64; | |
3434 | break; | |
3435 | case BFD_RELOC_X86_64_TPOFF32: | |
3436 | other = BFD_RELOC_X86_64_TPOFF64; | |
3437 | break; | |
3438 | case BFD_RELOC_X86_64_DTPOFF32: | |
3439 | other = BFD_RELOC_X86_64_DTPOFF64; | |
3440 | break; | |
3441 | default: | |
3442 | break; | |
3956db08 | 3443 | } |
e05278af | 3444 | |
8ce3d284 | 3445 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
3446 | if (other == BFD_RELOC_SIZE32) |
3447 | { | |
3448 | if (size == 8) | |
1ab668bf | 3449 | other = BFD_RELOC_SIZE64; |
8fd4256d | 3450 | if (pcrel) |
1ab668bf AM |
3451 | { |
3452 | as_bad (_("there are no pc-relative size relocations")); | |
3453 | return NO_RELOC; | |
3454 | } | |
8fd4256d | 3455 | } |
8ce3d284 | 3456 | #endif |
8fd4256d | 3457 | |
e05278af | 3458 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
f2d8a97c | 3459 | if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc)) |
e05278af JB |
3460 | sign = -1; |
3461 | ||
91d6fa6a NC |
3462 | rel = bfd_reloc_type_lookup (stdoutput, other); |
3463 | if (!rel) | |
3956db08 | 3464 | as_bad (_("unknown relocation (%u)"), other); |
91d6fa6a | 3465 | else if (size != bfd_get_reloc_size (rel)) |
3956db08 | 3466 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field"), |
91d6fa6a | 3467 | bfd_get_reloc_size (rel), |
3956db08 | 3468 | size); |
91d6fa6a | 3469 | else if (pcrel && !rel->pc_relative) |
3956db08 | 3470 | as_bad (_("non-pc-relative relocation for pc-relative field")); |
91d6fa6a | 3471 | else if ((rel->complain_on_overflow == complain_overflow_signed |
3956db08 | 3472 | && !sign) |
91d6fa6a | 3473 | || (rel->complain_on_overflow == complain_overflow_unsigned |
64e74474 | 3474 | && sign > 0)) |
3956db08 JB |
3475 | as_bad (_("relocated field and relocation type differ in signedness")); |
3476 | else | |
3477 | return other; | |
3478 | return NO_RELOC; | |
3479 | } | |
252b5132 RH |
3480 | |
3481 | if (pcrel) | |
3482 | { | |
3e73aa7c | 3483 | if (!sign) |
3956db08 | 3484 | as_bad (_("there are no unsigned pc-relative relocations")); |
252b5132 RH |
3485 | switch (size) |
3486 | { | |
3487 | case 1: return BFD_RELOC_8_PCREL; | |
3488 | case 2: return BFD_RELOC_16_PCREL; | |
d258b828 | 3489 | case 4: return BFD_RELOC_32_PCREL; |
d6ab8113 | 3490 | case 8: return BFD_RELOC_64_PCREL; |
252b5132 | 3491 | } |
3956db08 | 3492 | as_bad (_("cannot do %u byte pc-relative relocation"), size); |
252b5132 RH |
3493 | } |
3494 | else | |
3495 | { | |
3956db08 | 3496 | if (sign > 0) |
e5cb08ac | 3497 | switch (size) |
3e73aa7c JH |
3498 | { |
3499 | case 4: return BFD_RELOC_X86_64_32S; | |
3500 | } | |
3501 | else | |
3502 | switch (size) | |
3503 | { | |
3504 | case 1: return BFD_RELOC_8; | |
3505 | case 2: return BFD_RELOC_16; | |
3506 | case 4: return BFD_RELOC_32; | |
3507 | case 8: return BFD_RELOC_64; | |
3508 | } | |
3956db08 JB |
3509 | as_bad (_("cannot do %s %u byte relocation"), |
3510 | sign > 0 ? "signed" : "unsigned", size); | |
252b5132 RH |
3511 | } |
3512 | ||
0cc9e1d3 | 3513 | return NO_RELOC; |
252b5132 RH |
3514 | } |
3515 | ||
47926f60 KH |
3516 | /* Here we decide which fixups can be adjusted to make them relative to |
3517 | the beginning of the section instead of the symbol. Basically we need | |
3518 | to make sure that the dynamic relocations are done correctly, so in | |
3519 | some cases we force the original symbol to be used. */ | |
3520 | ||
252b5132 | 3521 | int |
e3bb37b5 | 3522 | tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED) |
252b5132 | 3523 | { |
6d249963 | 3524 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 3525 | if (!IS_ELF) |
31312f95 AM |
3526 | return 1; |
3527 | ||
a161fe53 AM |
3528 | /* Don't adjust pc-relative references to merge sections in 64-bit |
3529 | mode. */ | |
3530 | if (use_rela_relocations | |
3531 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 | |
3532 | && fixP->fx_pcrel) | |
252b5132 | 3533 | return 0; |
31312f95 | 3534 | |
8d01d9a9 AJ |
3535 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
3536 | and changed later by validate_fix. */ | |
3537 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol | |
3538 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) | |
3539 | return 0; | |
3540 | ||
8fd4256d L |
3541 | /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol |
3542 | for size relocations. */ | |
3543 | if (fixP->fx_r_type == BFD_RELOC_SIZE32 | |
3544 | || fixP->fx_r_type == BFD_RELOC_SIZE64 | |
3545 | || fixP->fx_r_type == BFD_RELOC_386_GOTOFF | |
252b5132 | 3546 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
02a86693 | 3547 | || fixP->fx_r_type == BFD_RELOC_386_GOT32X |
13ae64f3 JJ |
3548 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
3549 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM | |
3550 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 | |
3551 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 | |
37e55690 JJ |
3552 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
3553 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE | |
13ae64f3 JJ |
3554 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
3555 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE | |
67a4f2b7 AO |
3556 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
3557 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL | |
3e73aa7c | 3558 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
80b3ee89 | 3559 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
56ceb5b5 L |
3560 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCRELX |
3561 | || fixP->fx_r_type == BFD_RELOC_X86_64_REX_GOTPCRELX | |
bffbf940 JJ |
3562 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
3563 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD | |
3564 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 | |
d6ab8113 | 3565 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
bffbf940 JJ |
3566 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
3567 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 | |
d6ab8113 JB |
3568 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
3569 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 | |
67a4f2b7 AO |
3570 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
3571 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL | |
252b5132 RH |
3572 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
3573 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
3574 | return 0; | |
31312f95 | 3575 | #endif |
252b5132 RH |
3576 | return 1; |
3577 | } | |
252b5132 | 3578 | |
a9aabc23 JB |
3579 | static INLINE bool |
3580 | want_disp32 (const insn_template *t) | |
3581 | { | |
3582 | return flag_code != CODE_64BIT | |
3583 | || i.prefix[ADDR_PREFIX] | |
7fc69528 | 3584 | || (t->mnem_off == MN_lea |
fe134c65 JB |
3585 | && (!i.types[1].bitfield.qword |
3586 | || t->opcode_modifier.size == SIZE32)); | |
a9aabc23 JB |
3587 | } |
3588 | ||
b4cac588 | 3589 | static int |
e3bb37b5 | 3590 | intel_float_operand (const char *mnemonic) |
252b5132 | 3591 | { |
9306ca4a JB |
3592 | /* Note that the value returned is meaningful only for opcodes with (memory) |
3593 | operands, hence the code here is free to improperly handle opcodes that | |
3594 | have no operands (for better performance and smaller code). */ | |
3595 | ||
3596 | if (mnemonic[0] != 'f') | |
3597 | return 0; /* non-math */ | |
3598 | ||
3599 | switch (mnemonic[1]) | |
3600 | { | |
3601 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and | |
3602 | the fs segment override prefix not currently handled because no | |
3603 | call path can make opcodes without operands get here */ | |
3604 | case 'i': | |
3605 | return 2 /* integer op */; | |
3606 | case 'l': | |
3607 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) | |
3608 | return 3; /* fldcw/fldenv */ | |
3609 | break; | |
3610 | case 'n': | |
3611 | if (mnemonic[2] != 'o' /* fnop */) | |
3612 | return 3; /* non-waiting control op */ | |
3613 | break; | |
3614 | case 'r': | |
3615 | if (mnemonic[2] == 's') | |
3616 | return 3; /* frstor/frstpm */ | |
3617 | break; | |
3618 | case 's': | |
3619 | if (mnemonic[2] == 'a') | |
3620 | return 3; /* fsave */ | |
3621 | if (mnemonic[2] == 't') | |
3622 | { | |
3623 | switch (mnemonic[3]) | |
3624 | { | |
3625 | case 'c': /* fstcw */ | |
3626 | case 'd': /* fstdw */ | |
3627 | case 'e': /* fstenv */ | |
3628 | case 's': /* fsts[gw] */ | |
3629 | return 3; | |
3630 | } | |
3631 | } | |
3632 | break; | |
3633 | case 'x': | |
3634 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') | |
3635 | return 0; /* fxsave/fxrstor are not really math ops */ | |
3636 | break; | |
3637 | } | |
252b5132 | 3638 | |
9306ca4a | 3639 | return 1; |
252b5132 RH |
3640 | } |
3641 | ||
9a182d04 JB |
3642 | static INLINE void |
3643 | install_template (const insn_template *t) | |
3644 | { | |
3645 | unsigned int l; | |
3646 | ||
3647 | i.tm = *t; | |
3648 | ||
3649 | /* Note that for pseudo prefixes this produces a length of 1. But for them | |
3650 | the length isn't interesting at all. */ | |
3651 | for (l = 1; l < 4; ++l) | |
3652 | if (!(t->base_opcode >> (8 * l))) | |
3653 | break; | |
3654 | ||
3655 | i.opcode_length = l; | |
3656 | } | |
3657 | ||
c0f3af97 L |
3658 | /* Build the VEX prefix. */ |
3659 | ||
3660 | static void | |
d3ce72d0 | 3661 | build_vex_prefix (const insn_template *t) |
c0f3af97 L |
3662 | { |
3663 | unsigned int register_specifier; | |
c0f3af97 | 3664 | unsigned int vector_length; |
03751133 | 3665 | unsigned int w; |
c0f3af97 L |
3666 | |
3667 | /* Check register specifier. */ | |
3668 | if (i.vex.register_specifier) | |
43234a1e L |
3669 | { |
3670 | register_specifier = | |
3671 | ~register_number (i.vex.register_specifier) & 0xf; | |
3672 | gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0); | |
3673 | } | |
c0f3af97 L |
3674 | else |
3675 | register_specifier = 0xf; | |
3676 | ||
79f0fa25 L |
3677 | /* Use 2-byte VEX prefix by swapping destination and source operand |
3678 | if there are more than 1 register operand. */ | |
3679 | if (i.reg_operands > 1 | |
3680 | && i.vec_encoding != vex_encoding_vex3 | |
86fa6981 | 3681 | && i.dir_encoding == dir_encoding_default |
fa99fab2 | 3682 | && i.operands == i.reg_operands |
dbbc8b7e | 3683 | && operand_type_equal (&i.types[0], &i.types[i.operands - 1]) |
ddb62495 | 3684 | && i.tm.opcode_space == SPACE_0F |
dbbc8b7e | 3685 | && (i.tm.opcode_modifier.load || i.tm.opcode_modifier.d) |
fa99fab2 L |
3686 | && i.rex == REX_B) |
3687 | { | |
67748abf | 3688 | unsigned int xchg; |
fa99fab2 | 3689 | |
67748abf | 3690 | swap_2_operands (0, i.operands - 1); |
fa99fab2 | 3691 | |
9c2799c2 | 3692 | gas_assert (i.rm.mode == 3); |
fa99fab2 L |
3693 | |
3694 | i.rex = REX_R; | |
3695 | xchg = i.rm.regmem; | |
3696 | i.rm.regmem = i.rm.reg; | |
3697 | i.rm.reg = xchg; | |
3698 | ||
dbbc8b7e JB |
3699 | if (i.tm.opcode_modifier.d) |
3700 | i.tm.base_opcode ^= (i.tm.base_opcode & 0xee) != 0x6e | |
2c735193 | 3701 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
dbbc8b7e | 3702 | else /* Use the next insn. */ |
9a182d04 | 3703 | install_template (&t[1]); |
fa99fab2 L |
3704 | } |
3705 | ||
79dec6b7 JB |
3706 | /* Use 2-byte VEX prefix by swapping commutative source operands if there |
3707 | are no memory operands and at least 3 register ones. */ | |
3708 | if (i.reg_operands >= 3 | |
3709 | && i.vec_encoding != vex_encoding_vex3 | |
3710 | && i.reg_operands == i.operands - i.imm_operands | |
3711 | && i.tm.opcode_modifier.vex | |
3712 | && i.tm.opcode_modifier.commutative | |
33740f21 JB |
3713 | && (i.tm.opcode_modifier.sse2avx |
3714 | || (optimize > 1 && !i.no_optimize)) | |
79dec6b7 JB |
3715 | && i.rex == REX_B |
3716 | && i.vex.register_specifier | |
3717 | && !(i.vex.register_specifier->reg_flags & RegRex)) | |
3718 | { | |
3719 | unsigned int xchg = i.operands - i.reg_operands; | |
79dec6b7 | 3720 | |
ddb62495 | 3721 | gas_assert (i.tm.opcode_space == SPACE_0F); |
79dec6b7 JB |
3722 | gas_assert (!i.tm.opcode_modifier.sae); |
3723 | gas_assert (operand_type_equal (&i.types[i.operands - 2], | |
3724 | &i.types[i.operands - 3])); | |
3725 | gas_assert (i.rm.mode == 3); | |
3726 | ||
67748abf | 3727 | swap_2_operands (xchg, xchg + 1); |
79dec6b7 JB |
3728 | |
3729 | i.rex = 0; | |
3730 | xchg = i.rm.regmem | 8; | |
3731 | i.rm.regmem = ~register_specifier & 0xf; | |
3732 | gas_assert (!(i.rm.regmem & 8)); | |
3733 | i.vex.register_specifier += xchg - i.rm.regmem; | |
3734 | register_specifier = ~xchg & 0xf; | |
3735 | } | |
3736 | ||
539f890d L |
3737 | if (i.tm.opcode_modifier.vex == VEXScalar) |
3738 | vector_length = avxscalar; | |
10c17abd JB |
3739 | else if (i.tm.opcode_modifier.vex == VEX256) |
3740 | vector_length = 1; | |
d0c2e3ec JB |
3741 | else if (dot_insn () && i.tm.opcode_modifier.vex == VEX128) |
3742 | vector_length = 0; | |
539f890d | 3743 | else |
10c17abd | 3744 | { |
56522fc5 | 3745 | unsigned int op; |
10c17abd | 3746 | |
c7213af9 L |
3747 | /* Determine vector length from the last multi-length vector |
3748 | operand. */ | |
10c17abd | 3749 | vector_length = 0; |
56522fc5 | 3750 | for (op = t->operands; op--;) |
10c17abd JB |
3751 | if (t->operand_types[op].bitfield.xmmword |
3752 | && t->operand_types[op].bitfield.ymmword | |
3753 | && i.types[op].bitfield.ymmword) | |
3754 | { | |
3755 | vector_length = 1; | |
3756 | break; | |
3757 | } | |
3758 | } | |
c0f3af97 | 3759 | |
03751133 L |
3760 | /* Check the REX.W bit and VEXW. */ |
3761 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3762 | w = (vexwig == vexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3763 | else if (i.tm.opcode_modifier.vexw) | |
3764 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3765 | else | |
931d03b7 | 3766 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : vexwig == vexw1) ? 1 : 0; |
03751133 | 3767 | |
c0f3af97 | 3768 | /* Use 2-byte VEX prefix if possible. */ |
03751133 L |
3769 | if (w == 0 |
3770 | && i.vec_encoding != vex_encoding_vex3 | |
ddb62495 | 3771 | && i.tm.opcode_space == SPACE_0F |
c0f3af97 L |
3772 | && (i.rex & (REX_W | REX_X | REX_B)) == 0) |
3773 | { | |
3774 | /* 2-byte VEX prefix. */ | |
3775 | unsigned int r; | |
3776 | ||
3777 | i.vex.length = 2; | |
3778 | i.vex.bytes[0] = 0xc5; | |
3779 | ||
3780 | /* Check the REX.R bit. */ | |
3781 | r = (i.rex & REX_R) ? 0 : 1; | |
3782 | i.vex.bytes[1] = (r << 7 | |
3783 | | register_specifier << 3 | |
3784 | | vector_length << 2 | |
35648716 | 3785 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3786 | } |
3787 | else | |
3788 | { | |
3789 | /* 3-byte VEX prefix. */ | |
f88c9eb0 | 3790 | i.vex.length = 3; |
f88c9eb0 | 3791 | |
ddb62495 | 3792 | switch (i.tm.opcode_space) |
5dd85c99 | 3793 | { |
441f6aca JB |
3794 | case SPACE_0F: |
3795 | case SPACE_0F38: | |
3796 | case SPACE_0F3A: | |
80de6e00 | 3797 | i.vex.bytes[0] = 0xc4; |
7f399153 | 3798 | break; |
441f6aca JB |
3799 | case SPACE_XOP08: |
3800 | case SPACE_XOP09: | |
3801 | case SPACE_XOP0A: | |
f88c9eb0 | 3802 | i.vex.bytes[0] = 0x8f; |
7f399153 L |
3803 | break; |
3804 | default: | |
3805 | abort (); | |
f88c9eb0 | 3806 | } |
c0f3af97 | 3807 | |
c0f3af97 L |
3808 | /* The high 3 bits of the second VEX byte are 1's compliment |
3809 | of RXB bits from REX. */ | |
d0c2e3ec JB |
3810 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
3811 | | (!dot_insn () ? i.tm.opcode_space | |
3812 | : i.insn_opcode_space); | |
c0f3af97 | 3813 | |
c0f3af97 L |
3814 | i.vex.bytes[2] = (w << 7 |
3815 | | register_specifier << 3 | |
3816 | | vector_length << 2 | |
35648716 | 3817 | | i.tm.opcode_modifier.opcodeprefix); |
c0f3af97 L |
3818 | } |
3819 | } | |
3820 | ||
5b7c81bd | 3821 | static INLINE bool |
e771e7c9 JB |
3822 | is_evex_encoding (const insn_template *t) |
3823 | { | |
7091c612 | 3824 | return t->opcode_modifier.evex || t->opcode_modifier.disp8memshift |
e771e7c9 | 3825 | || t->opcode_modifier.broadcast || t->opcode_modifier.masking |
a80195f1 | 3826 | || t->opcode_modifier.sae; |
e771e7c9 JB |
3827 | } |
3828 | ||
5b7c81bd | 3829 | static INLINE bool |
7a8655d2 JB |
3830 | is_any_vex_encoding (const insn_template *t) |
3831 | { | |
7b47a312 | 3832 | return t->opcode_modifier.vex || is_evex_encoding (t); |
7a8655d2 JB |
3833 | } |
3834 | ||
a5748e0d JB |
3835 | static unsigned int |
3836 | get_broadcast_bytes (const insn_template *t, bool diag) | |
3837 | { | |
3838 | unsigned int op, bytes; | |
3839 | const i386_operand_type *types; | |
3840 | ||
3841 | if (i.broadcast.type) | |
9b345ce8 | 3842 | return (1 << (t->opcode_modifier.broadcast - 1)) * i.broadcast.type; |
a5748e0d JB |
3843 | |
3844 | gas_assert (intel_syntax); | |
3845 | ||
3846 | for (op = 0; op < t->operands; ++op) | |
3847 | if (t->operand_types[op].bitfield.baseindex) | |
3848 | break; | |
3849 | ||
3850 | gas_assert (op < t->operands); | |
3851 | ||
3852 | if (t->opcode_modifier.evex | |
3853 | && t->opcode_modifier.evex != EVEXDYN) | |
3854 | switch (i.broadcast.bytes) | |
3855 | { | |
3856 | case 1: | |
3857 | if (t->operand_types[op].bitfield.word) | |
3858 | return 2; | |
3859 | /* Fall through. */ | |
3860 | case 2: | |
3861 | if (t->operand_types[op].bitfield.dword) | |
3862 | return 4; | |
3863 | /* Fall through. */ | |
3864 | case 4: | |
3865 | if (t->operand_types[op].bitfield.qword) | |
3866 | return 8; | |
3867 | /* Fall through. */ | |
3868 | case 8: | |
3869 | if (t->operand_types[op].bitfield.xmmword) | |
3870 | return 16; | |
3871 | if (t->operand_types[op].bitfield.ymmword) | |
3872 | return 32; | |
3873 | if (t->operand_types[op].bitfield.zmmword) | |
3874 | return 64; | |
3875 | /* Fall through. */ | |
3876 | default: | |
3877 | abort (); | |
3878 | } | |
3879 | ||
3880 | gas_assert (op + 1 < t->operands); | |
3881 | ||
3882 | if (t->operand_types[op + 1].bitfield.xmmword | |
3883 | + t->operand_types[op + 1].bitfield.ymmword | |
3884 | + t->operand_types[op + 1].bitfield.zmmword > 1) | |
3885 | { | |
3886 | types = &i.types[op + 1]; | |
3887 | diag = false; | |
3888 | } | |
3889 | else /* Ambiguous - guess with a preference to non-AVX512VL forms. */ | |
3890 | types = &t->operand_types[op]; | |
3891 | ||
3892 | if (types->bitfield.zmmword) | |
3893 | bytes = 64; | |
3894 | else if (types->bitfield.ymmword) | |
3895 | bytes = 32; | |
3896 | else | |
3897 | bytes = 16; | |
3898 | ||
3899 | if (diag) | |
3900 | as_warn (_("ambiguous broadcast for `%s', using %u-bit form"), | |
76d3f746 | 3901 | insn_name (t), bytes * 8); |
a5748e0d JB |
3902 | |
3903 | return bytes; | |
3904 | } | |
3905 | ||
43234a1e L |
3906 | /* Build the EVEX prefix. */ |
3907 | ||
3908 | static void | |
3909 | build_evex_prefix (void) | |
3910 | { | |
35648716 | 3911 | unsigned int register_specifier, w; |
43234a1e L |
3912 | rex_byte vrex_used = 0; |
3913 | ||
3914 | /* Check register specifier. */ | |
3915 | if (i.vex.register_specifier) | |
3916 | { | |
3917 | gas_assert ((i.vrex & REX_X) == 0); | |
3918 | ||
3919 | register_specifier = i.vex.register_specifier->reg_num; | |
3920 | if ((i.vex.register_specifier->reg_flags & RegRex)) | |
3921 | register_specifier += 8; | |
3922 | /* The upper 16 registers are encoded in the fourth byte of the | |
3923 | EVEX prefix. */ | |
3924 | if (!(i.vex.register_specifier->reg_flags & RegVRex)) | |
3925 | i.vex.bytes[3] = 0x8; | |
3926 | register_specifier = ~register_specifier & 0xf; | |
3927 | } | |
3928 | else | |
3929 | { | |
3930 | register_specifier = 0xf; | |
3931 | ||
3932 | /* Encode upper 16 vector index register in the fourth byte of | |
3933 | the EVEX prefix. */ | |
3934 | if (!(i.vrex & REX_X)) | |
3935 | i.vex.bytes[3] = 0x8; | |
3936 | else | |
3937 | vrex_used |= REX_X; | |
3938 | } | |
3939 | ||
43234a1e L |
3940 | /* 4 byte EVEX prefix. */ |
3941 | i.vex.length = 4; | |
3942 | i.vex.bytes[0] = 0x62; | |
3943 | ||
43234a1e L |
3944 | /* The high 3 bits of the second EVEX byte are 1's compliment of RXB |
3945 | bits from REX. */ | |
ddb62495 JB |
3946 | gas_assert (i.tm.opcode_space >= SPACE_0F); |
3947 | gas_assert (i.tm.opcode_space <= SPACE_EVEXMAP6); | |
d0c2e3ec JB |
3948 | i.vex.bytes[1] = ((~i.rex & 7) << 5) |
3949 | | (!dot_insn () ? i.tm.opcode_space | |
3950 | : i.insn_opcode_space); | |
43234a1e L |
3951 | |
3952 | /* The fifth bit of the second EVEX byte is 1's compliment of the | |
3953 | REX_R bit in VREX. */ | |
3954 | if (!(i.vrex & REX_R)) | |
3955 | i.vex.bytes[1] |= 0x10; | |
3956 | else | |
3957 | vrex_used |= REX_R; | |
3958 | ||
3959 | if ((i.reg_operands + i.imm_operands) == i.operands) | |
3960 | { | |
3961 | /* When all operands are registers, the REX_X bit in REX is not | |
3962 | used. We reuse it to encode the upper 16 registers, which is | |
3963 | indicated by the REX_B bit in VREX. The REX_X bit is encoded | |
3964 | as 1's compliment. */ | |
3965 | if ((i.vrex & REX_B)) | |
3966 | { | |
3967 | vrex_used |= REX_B; | |
3968 | i.vex.bytes[1] &= ~0x40; | |
3969 | } | |
3970 | } | |
3971 | ||
3972 | /* EVEX instructions shouldn't need the REX prefix. */ | |
3973 | i.vrex &= ~vrex_used; | |
3974 | gas_assert (i.vrex == 0); | |
3975 | ||
6865c043 L |
3976 | /* Check the REX.W bit and VEXW. */ |
3977 | if (i.tm.opcode_modifier.vexw == VEXWIG) | |
3978 | w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0; | |
3979 | else if (i.tm.opcode_modifier.vexw) | |
3980 | w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0; | |
3981 | else | |
931d03b7 | 3982 | w = (flag_code == CODE_64BIT ? i.rex & REX_W : evexwig == evexw1) ? 1 : 0; |
43234a1e | 3983 | |
43234a1e | 3984 | /* The third byte of the EVEX prefix. */ |
35648716 JB |
3985 | i.vex.bytes[2] = ((w << 7) |
3986 | | (register_specifier << 3) | |
3987 | | 4 /* Encode the U bit. */ | |
3988 | | i.tm.opcode_modifier.opcodeprefix); | |
43234a1e L |
3989 | |
3990 | /* The fourth byte of the EVEX prefix. */ | |
3991 | /* The zeroing-masking bit. */ | |
6225c532 | 3992 | if (i.mask.reg && i.mask.zeroing) |
43234a1e L |
3993 | i.vex.bytes[3] |= 0x80; |
3994 | ||
3995 | /* Don't always set the broadcast bit if there is no RC. */ | |
ca5312a2 | 3996 | if (i.rounding.type == rc_none) |
43234a1e L |
3997 | { |
3998 | /* Encode the vector length. */ | |
3999 | unsigned int vec_length; | |
4000 | ||
e771e7c9 JB |
4001 | if (!i.tm.opcode_modifier.evex |
4002 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
4003 | { | |
56522fc5 | 4004 | unsigned int op; |
e771e7c9 | 4005 | |
c7213af9 L |
4006 | /* Determine vector length from the last multi-length vector |
4007 | operand. */ | |
56522fc5 | 4008 | for (op = i.operands; op--;) |
e771e7c9 JB |
4009 | if (i.tm.operand_types[op].bitfield.xmmword |
4010 | + i.tm.operand_types[op].bitfield.ymmword | |
4011 | + i.tm.operand_types[op].bitfield.zmmword > 1) | |
4012 | { | |
4013 | if (i.types[op].bitfield.zmmword) | |
c7213af9 L |
4014 | { |
4015 | i.tm.opcode_modifier.evex = EVEX512; | |
4016 | break; | |
4017 | } | |
e771e7c9 | 4018 | else if (i.types[op].bitfield.ymmword) |
c7213af9 L |
4019 | { |
4020 | i.tm.opcode_modifier.evex = EVEX256; | |
4021 | break; | |
4022 | } | |
e771e7c9 | 4023 | else if (i.types[op].bitfield.xmmword) |
c7213af9 L |
4024 | { |
4025 | i.tm.opcode_modifier.evex = EVEX128; | |
4026 | break; | |
4027 | } | |
9b345ce8 JB |
4028 | else if ((i.broadcast.type || i.broadcast.bytes) |
4029 | && op == i.broadcast.operand) | |
625cbd7a | 4030 | { |
a5748e0d | 4031 | switch (get_broadcast_bytes (&i.tm, true)) |
625cbd7a JB |
4032 | { |
4033 | case 64: | |
4034 | i.tm.opcode_modifier.evex = EVEX512; | |
4035 | break; | |
4036 | case 32: | |
4037 | i.tm.opcode_modifier.evex = EVEX256; | |
4038 | break; | |
4039 | case 16: | |
4040 | i.tm.opcode_modifier.evex = EVEX128; | |
4041 | break; | |
4042 | default: | |
c7213af9 | 4043 | abort (); |
625cbd7a | 4044 | } |
c7213af9 | 4045 | break; |
625cbd7a | 4046 | } |
e771e7c9 | 4047 | } |
c7213af9 | 4048 | |
56522fc5 | 4049 | if (op >= MAX_OPERANDS) |
c7213af9 | 4050 | abort (); |
e771e7c9 JB |
4051 | } |
4052 | ||
43234a1e L |
4053 | switch (i.tm.opcode_modifier.evex) |
4054 | { | |
4055 | case EVEXLIG: /* LL' is ignored */ | |
4056 | vec_length = evexlig << 5; | |
4057 | break; | |
4058 | case EVEX128: | |
4059 | vec_length = 0 << 5; | |
4060 | break; | |
4061 | case EVEX256: | |
4062 | vec_length = 1 << 5; | |
4063 | break; | |
4064 | case EVEX512: | |
4065 | vec_length = 2 << 5; | |
4066 | break; | |
d0c2e3ec JB |
4067 | case EVEX_L3: |
4068 | if (dot_insn ()) | |
4069 | { | |
4070 | vec_length = 3 << 5; | |
4071 | break; | |
4072 | } | |
4073 | /* Fall through. */ | |
43234a1e L |
4074 | default: |
4075 | abort (); | |
4076 | break; | |
4077 | } | |
4078 | i.vex.bytes[3] |= vec_length; | |
4079 | /* Encode the broadcast bit. */ | |
9b345ce8 | 4080 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e L |
4081 | i.vex.bytes[3] |= 0x10; |
4082 | } | |
ca5312a2 JB |
4083 | else if (i.rounding.type != saeonly) |
4084 | i.vex.bytes[3] |= 0x10 | (i.rounding.type << 5); | |
43234a1e | 4085 | else |
ca5312a2 | 4086 | i.vex.bytes[3] |= 0x10 | (evexrcig << 5); |
43234a1e | 4087 | |
6225c532 JB |
4088 | if (i.mask.reg) |
4089 | i.vex.bytes[3] |= i.mask.reg->reg_num; | |
43234a1e L |
4090 | } |
4091 | ||
65da13b5 L |
4092 | static void |
4093 | process_immext (void) | |
4094 | { | |
4095 | expressionS *exp; | |
4096 | ||
c0f3af97 | 4097 | /* These AMD 3DNow! and SSE2 instructions have an opcode suffix |
65da13b5 L |
4098 | which is coded in the same place as an 8-bit immediate field |
4099 | would be. Here we fake an 8-bit immediate operand from the | |
4100 | opcode suffix stored in tm.extension_opcode. | |
4101 | ||
c1e679ec | 4102 | AVX instructions also use this encoding, for some of |
c0f3af97 | 4103 | 3 argument instructions. */ |
65da13b5 | 4104 | |
43234a1e | 4105 | gas_assert (i.imm_operands <= 1 |
7ab9ffdd | 4106 | && (i.operands <= 2 |
7a8655d2 | 4107 | || (is_any_vex_encoding (&i.tm) |
7ab9ffdd | 4108 | && i.operands <= 4))); |
65da13b5 L |
4109 | |
4110 | exp = &im_expressions[i.imm_operands++]; | |
4111 | i.op[i.operands].imms = exp; | |
be1643ff | 4112 | i.types[i.operands].bitfield.imm8 = 1; |
65da13b5 L |
4113 | i.operands++; |
4114 | exp->X_op = O_constant; | |
4115 | exp->X_add_number = i.tm.extension_opcode; | |
4116 | i.tm.extension_opcode = None; | |
4117 | } | |
4118 | ||
42164a71 L |
4119 | |
4120 | static int | |
4121 | check_hle (void) | |
4122 | { | |
742732c7 | 4123 | switch (i.tm.opcode_modifier.prefixok) |
42164a71 L |
4124 | { |
4125 | default: | |
4126 | abort (); | |
742732c7 JB |
4127 | case PrefixLock: |
4128 | case PrefixNone: | |
4129 | case PrefixNoTrack: | |
4130 | case PrefixRep: | |
165de32a | 4131 | as_bad (_("invalid instruction `%s' after `%s'"), |
76d3f746 | 4132 | insn_name (&i.tm), i.hle_prefix); |
42164a71 | 4133 | return 0; |
742732c7 | 4134 | case PrefixHLELock: |
42164a71 L |
4135 | if (i.prefix[LOCK_PREFIX]) |
4136 | return 1; | |
165de32a | 4137 | as_bad (_("missing `lock' with `%s'"), i.hle_prefix); |
42164a71 | 4138 | return 0; |
742732c7 | 4139 | case PrefixHLEAny: |
42164a71 | 4140 | return 1; |
742732c7 | 4141 | case PrefixHLERelease: |
42164a71 L |
4142 | if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE) |
4143 | { | |
4144 | as_bad (_("instruction `%s' after `xacquire' not allowed"), | |
76d3f746 | 4145 | insn_name (&i.tm)); |
42164a71 L |
4146 | return 0; |
4147 | } | |
8dc0818e | 4148 | if (i.mem_operands == 0 || !(i.flags[i.operands - 1] & Operand_Mem)) |
42164a71 L |
4149 | { |
4150 | as_bad (_("memory destination needed for instruction `%s'" | |
76d3f746 | 4151 | " after `xrelease'"), insn_name (&i.tm)); |
42164a71 L |
4152 | return 0; |
4153 | } | |
4154 | return 1; | |
4155 | } | |
4156 | } | |
4157 | ||
c8480b58 L |
4158 | /* Encode aligned vector move as unaligned vector move. */ |
4159 | ||
4160 | static void | |
4161 | encode_with_unaligned_vector_move (void) | |
4162 | { | |
4163 | switch (i.tm.base_opcode) | |
4164 | { | |
b3a9fe6f L |
4165 | case 0x28: /* Load instructions. */ |
4166 | case 0x29: /* Store instructions. */ | |
c8480b58 | 4167 | /* movaps/movapd/vmovaps/vmovapd. */ |
ddb62495 | 4168 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 | 4169 | && i.tm.opcode_modifier.opcodeprefix <= PREFIX_0X66) |
b3a9fe6f | 4170 | i.tm.base_opcode = 0x10 | (i.tm.base_opcode & 1); |
c8480b58 | 4171 | break; |
b3a9fe6f L |
4172 | case 0x6f: /* Load instructions. */ |
4173 | case 0x7f: /* Store instructions. */ | |
c8480b58 | 4174 | /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */ |
ddb62495 | 4175 | if (i.tm.opcode_space == SPACE_0F |
c8480b58 L |
4176 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0X66) |
4177 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
4178 | break; | |
4179 | default: | |
4180 | break; | |
4181 | } | |
4182 | } | |
4183 | ||
b6f8c7c4 L |
4184 | /* Try the shortest encoding by shortening operand size. */ |
4185 | ||
4186 | static void | |
4187 | optimize_encoding (void) | |
4188 | { | |
a0a1771e | 4189 | unsigned int j; |
b6f8c7c4 | 4190 | |
7fc69528 | 4191 | if (i.tm.mnem_off == MN_lea) |
fe134c65 JB |
4192 | { |
4193 | /* Optimize: -O: | |
4194 | lea symbol, %rN -> mov $symbol, %rN | |
4195 | lea (%rM), %rN -> mov %rM, %rN | |
4196 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4197 | ||
4198 | and in 32-bit mode for 16-bit addressing | |
4199 | ||
4200 | lea (%rM), %rN -> movzx %rM, %rN | |
4201 | ||
4202 | and in 64-bit mode zap 32-bit addressing in favor of using a | |
4203 | 32-bit (or less) destination. | |
4204 | */ | |
4205 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
4206 | { | |
4207 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4208 | i.tm.opcode_modifier.size = SIZE32; | |
4209 | i.prefix[ADDR_PREFIX] = 0; | |
4210 | } | |
4211 | ||
4212 | if (!i.index_reg && !i.base_reg) | |
4213 | { | |
4214 | /* Handle: | |
4215 | lea symbol, %rN -> mov $symbol, %rN | |
4216 | */ | |
4217 | if (flag_code == CODE_64BIT) | |
4218 | { | |
4219 | /* Don't transform a relocation to a 16-bit one. */ | |
4220 | if (i.op[0].disps | |
4221 | && i.op[0].disps->X_op != O_constant | |
4222 | && i.op[1].regs->reg_type.bitfield.word) | |
4223 | return; | |
4224 | ||
4225 | if (!i.op[1].regs->reg_type.bitfield.qword | |
4226 | || i.tm.opcode_modifier.size == SIZE32) | |
4227 | { | |
4228 | i.tm.base_opcode = 0xb8; | |
4229 | i.tm.opcode_modifier.modrm = 0; | |
4230 | if (!i.op[1].regs->reg_type.bitfield.word) | |
4231 | i.types[0].bitfield.imm32 = 1; | |
4232 | else | |
4233 | { | |
4234 | i.tm.opcode_modifier.size = SIZE16; | |
4235 | i.types[0].bitfield.imm16 = 1; | |
4236 | } | |
4237 | } | |
4238 | else | |
4239 | { | |
4240 | /* Subject to further optimization below. */ | |
4241 | i.tm.base_opcode = 0xc7; | |
4242 | i.tm.extension_opcode = 0; | |
4243 | i.types[0].bitfield.imm32s = 1; | |
4244 | i.types[0].bitfield.baseindex = 0; | |
4245 | } | |
4246 | } | |
4247 | /* Outside of 64-bit mode address and operand sizes have to match if | |
4248 | a relocation is involved, as otherwise we wouldn't (currently) or | |
4249 | even couldn't express the relocation correctly. */ | |
4250 | else if (i.op[0].disps | |
4251 | && i.op[0].disps->X_op != O_constant | |
4252 | && ((!i.prefix[ADDR_PREFIX]) | |
4253 | != (flag_code == CODE_32BIT | |
4254 | ? i.op[1].regs->reg_type.bitfield.dword | |
4255 | : i.op[1].regs->reg_type.bitfield.word))) | |
4256 | return; | |
7772f168 JB |
4257 | /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit |
4258 | destination is going to grow encoding size. */ | |
4259 | else if (flag_code == CODE_16BIT | |
4260 | && (optimize <= 1 || optimize_for_space) | |
4261 | && !i.prefix[ADDR_PREFIX] | |
4262 | && i.op[1].regs->reg_type.bitfield.dword) | |
4263 | return; | |
fe134c65 JB |
4264 | else |
4265 | { | |
4266 | i.tm.base_opcode = 0xb8; | |
4267 | i.tm.opcode_modifier.modrm = 0; | |
4268 | if (i.op[1].regs->reg_type.bitfield.dword) | |
4269 | i.types[0].bitfield.imm32 = 1; | |
4270 | else | |
4271 | i.types[0].bitfield.imm16 = 1; | |
4272 | ||
4273 | if (i.op[0].disps | |
4274 | && i.op[0].disps->X_op == O_constant | |
4275 | && i.op[1].regs->reg_type.bitfield.dword | |
60cfa10c L |
4276 | /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence |
4277 | GCC 5. */ | |
4278 | && (!i.prefix[ADDR_PREFIX]) != (flag_code == CODE_32BIT)) | |
fe134c65 JB |
4279 | i.op[0].disps->X_add_number &= 0xffff; |
4280 | } | |
4281 | ||
4282 | i.tm.operand_types[0] = i.types[0]; | |
4283 | i.imm_operands = 1; | |
4284 | if (!i.op[0].imms) | |
4285 | { | |
4286 | i.op[0].imms = &im_expressions[0]; | |
4287 | i.op[0].imms->X_op = O_absent; | |
4288 | } | |
4289 | } | |
4290 | else if (i.op[0].disps | |
4291 | && (i.op[0].disps->X_op != O_constant | |
4292 | || i.op[0].disps->X_add_number)) | |
4293 | return; | |
4294 | else | |
4295 | { | |
4296 | /* Handle: | |
4297 | lea (%rM), %rN -> mov %rM, %rN | |
4298 | lea (,%rM,1), %rN -> mov %rM, %rN | |
4299 | lea (%rM), %rN -> movzx %rM, %rN | |
4300 | */ | |
4301 | const reg_entry *addr_reg; | |
4302 | ||
4303 | if (!i.index_reg && i.base_reg->reg_num != RegIP) | |
4304 | addr_reg = i.base_reg; | |
4305 | else if (!i.base_reg | |
4306 | && i.index_reg->reg_num != RegIZ | |
4307 | && !i.log2_scale_factor) | |
4308 | addr_reg = i.index_reg; | |
4309 | else | |
4310 | return; | |
4311 | ||
4312 | if (addr_reg->reg_type.bitfield.word | |
4313 | && i.op[1].regs->reg_type.bitfield.dword) | |
4314 | { | |
4315 | if (flag_code != CODE_32BIT) | |
4316 | return; | |
ddb62495 | 4317 | i.tm.opcode_space = SPACE_0F; |
fe134c65 JB |
4318 | i.tm.base_opcode = 0xb7; |
4319 | } | |
4320 | else | |
4321 | i.tm.base_opcode = 0x8b; | |
4322 | ||
4323 | if (addr_reg->reg_type.bitfield.dword | |
4324 | && i.op[1].regs->reg_type.bitfield.qword) | |
4325 | i.tm.opcode_modifier.size = SIZE32; | |
4326 | ||
4327 | i.op[0].regs = addr_reg; | |
4328 | i.reg_operands = 2; | |
4329 | } | |
4330 | ||
4331 | i.mem_operands = 0; | |
4332 | i.disp_operands = 0; | |
4333 | i.prefix[ADDR_PREFIX] = 0; | |
4334 | i.prefix[SEG_PREFIX] = 0; | |
4335 | i.seg[0] = NULL; | |
4336 | } | |
4337 | ||
b6f8c7c4 | 4338 | if (optimize_for_space |
7fc69528 | 4339 | && i.tm.mnem_off == MN_test |
b6f8c7c4 L |
4340 | && i.reg_operands == 1 |
4341 | && i.imm_operands == 1 | |
4342 | && !i.types[1].bitfield.byte | |
4343 | && i.op[0].imms->X_op == O_constant | |
7fc69528 | 4344 | && fits_in_imm7 (i.op[0].imms->X_add_number)) |
b6f8c7c4 L |
4345 | { |
4346 | /* Optimize: -Os: | |
4347 | test $imm7, %r64/%r32/%r16 -> test $imm7, %r8 | |
4348 | */ | |
4349 | unsigned int base_regnum = i.op[1].regs->reg_num; | |
4350 | if (flag_code == CODE_64BIT || base_regnum < 4) | |
4351 | { | |
4352 | i.types[1].bitfield.byte = 1; | |
4353 | /* Ignore the suffix. */ | |
4354 | i.suffix = 0; | |
7697afb6 JB |
4355 | /* Convert to byte registers. */ |
4356 | if (i.types[1].bitfield.word) | |
4357 | j = 16; | |
4358 | else if (i.types[1].bitfield.dword) | |
4359 | j = 32; | |
4360 | else | |
4361 | j = 48; | |
4362 | if (!(i.op[1].regs->reg_flags & RegRex) && base_regnum < 4) | |
4363 | j += 8; | |
4364 | i.op[1].regs -= j; | |
b6f8c7c4 L |
4365 | } |
4366 | } | |
4367 | else if (flag_code == CODE_64BIT | |
ddb62495 | 4368 | && i.tm.opcode_space == SPACE_BASE |
d3d50934 L |
4369 | && ((i.types[1].bitfield.qword |
4370 | && i.reg_operands == 1 | |
b6f8c7c4 L |
4371 | && i.imm_operands == 1 |
4372 | && i.op[0].imms->X_op == O_constant | |
507916b8 | 4373 | && ((i.tm.base_opcode == 0xb8 |
b6f8c7c4 L |
4374 | && i.tm.extension_opcode == None |
4375 | && fits_in_unsigned_long (i.op[0].imms->X_add_number)) | |
4376 | || (fits_in_imm31 (i.op[0].imms->X_add_number) | |
7fc69528 | 4377 | && (i.tm.base_opcode == 0x24 |
b6f8c7c4 L |
4378 | || (i.tm.base_opcode == 0x80 |
4379 | && i.tm.extension_opcode == 0x4) | |
7fc69528 JB |
4380 | || i.tm.mnem_off == MN_test |
4381 | || ((i.tm.base_opcode | 1) == 0xc7 | |
b8364fa7 JB |
4382 | && i.tm.extension_opcode == 0x0))) |
4383 | || (fits_in_imm7 (i.op[0].imms->X_add_number) | |
4384 | && i.tm.base_opcode == 0x83 | |
4385 | && i.tm.extension_opcode == 0x4))) | |
d3d50934 L |
4386 | || (i.types[0].bitfield.qword |
4387 | && ((i.reg_operands == 2 | |
4388 | && i.op[0].regs == i.op[1].regs | |
7fc69528 JB |
4389 | && (i.tm.mnem_off == MN_xor |
4390 | || i.tm.mnem_off == MN_sub)) | |
4391 | || i.tm.mnem_off == MN_clr)))) | |
b6f8c7c4 L |
4392 | { |
4393 | /* Optimize: -O: | |
4394 | andq $imm31, %r64 -> andl $imm31, %r32 | |
b8364fa7 | 4395 | andq $imm7, %r64 -> andl $imm7, %r32 |
b6f8c7c4 L |
4396 | testq $imm31, %r64 -> testl $imm31, %r32 |
4397 | xorq %r64, %r64 -> xorl %r32, %r32 | |
4398 | subq %r64, %r64 -> subl %r32, %r32 | |
4399 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4400 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4401 | */ | |
04784e33 JB |
4402 | i.tm.opcode_modifier.size = SIZE32; |
4403 | if (i.imm_operands) | |
4404 | { | |
4405 | i.types[0].bitfield.imm32 = 1; | |
4406 | i.types[0].bitfield.imm32s = 0; | |
4407 | i.types[0].bitfield.imm64 = 0; | |
4408 | } | |
4409 | else | |
4410 | { | |
4411 | i.types[0].bitfield.dword = 1; | |
4412 | i.types[0].bitfield.qword = 0; | |
4413 | } | |
4414 | i.types[1].bitfield.dword = 1; | |
4415 | i.types[1].bitfield.qword = 0; | |
7fc69528 | 4416 | if (i.tm.mnem_off == MN_mov || i.tm.mnem_off == MN_lea) |
b6f8c7c4 L |
4417 | { |
4418 | /* Handle | |
4419 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4420 | movq $imm32, %r64 -> movl $imm32, %r32 | |
4421 | */ | |
4422 | i.tm.operand_types[0].bitfield.imm32 = 1; | |
4423 | i.tm.operand_types[0].bitfield.imm32s = 0; | |
4424 | i.tm.operand_types[0].bitfield.imm64 = 0; | |
507916b8 | 4425 | if ((i.tm.base_opcode | 1) == 0xc7) |
b6f8c7c4 L |
4426 | { |
4427 | /* Handle | |
4428 | movq $imm31, %r64 -> movl $imm31, %r32 | |
4429 | */ | |
507916b8 | 4430 | i.tm.base_opcode = 0xb8; |
b6f8c7c4 | 4431 | i.tm.extension_opcode = None; |
507916b8 | 4432 | i.tm.opcode_modifier.w = 0; |
b6f8c7c4 L |
4433 | i.tm.opcode_modifier.modrm = 0; |
4434 | } | |
4435 | } | |
4436 | } | |
5641ec01 JB |
4437 | else if (optimize > 1 |
4438 | && !optimize_for_space | |
4439 | && i.reg_operands == 2 | |
4440 | && i.op[0].regs == i.op[1].regs | |
7fc69528 | 4441 | && (i.tm.mnem_off == MN_and || i.tm.mnem_off == MN_or) |
5641ec01 JB |
4442 | && (flag_code != CODE_64BIT || !i.types[0].bitfield.dword)) |
4443 | { | |
4444 | /* Optimize: -O2: | |
4445 | andb %rN, %rN -> testb %rN, %rN | |
4446 | andw %rN, %rN -> testw %rN, %rN | |
4447 | andq %rN, %rN -> testq %rN, %rN | |
4448 | orb %rN, %rN -> testb %rN, %rN | |
4449 | orw %rN, %rN -> testw %rN, %rN | |
4450 | orq %rN, %rN -> testq %rN, %rN | |
4451 | ||
4452 | and outside of 64-bit mode | |
4453 | ||
4454 | andl %rN, %rN -> testl %rN, %rN | |
4455 | orl %rN, %rN -> testl %rN, %rN | |
4456 | */ | |
4457 | i.tm.base_opcode = 0x84 | (i.tm.base_opcode & 1); | |
4458 | } | |
ad2f4436 JB |
4459 | else if (i.tm.base_opcode == 0xba |
4460 | && i.tm.opcode_space == SPACE_0F | |
4461 | && i.reg_operands == 1 | |
4462 | && i.op[0].imms->X_op == O_constant | |
4463 | && i.op[0].imms->X_add_number >= 0) | |
4464 | { | |
4465 | /* Optimize: -O: | |
4466 | btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16) | |
4467 | btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8) | |
4468 | btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4469 | ||
4470 | With <BT> one of bts, btr, and bts also: | |
4471 | <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16) | |
4472 | <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16) | |
4473 | */ | |
4474 | switch (flag_code) | |
4475 | { | |
4476 | case CODE_64BIT: | |
4477 | if (i.tm.extension_opcode != 4) | |
4478 | break; | |
4479 | if (i.types[1].bitfield.qword | |
4480 | && i.op[0].imms->X_add_number < 32 | |
4481 | && !(i.op[1].regs->reg_flags & RegRex)) | |
4482 | i.tm.opcode_modifier.size = SIZE32; | |
4483 | /* Fall through. */ | |
4484 | case CODE_32BIT: | |
4485 | if (i.types[1].bitfield.word | |
4486 | && i.op[0].imms->X_add_number < 16) | |
4487 | i.tm.opcode_modifier.size = SIZE32; | |
4488 | break; | |
4489 | case CODE_16BIT: | |
4490 | if (i.op[0].imms->X_add_number < 16) | |
4491 | i.tm.opcode_modifier.size = SIZE16; | |
4492 | break; | |
4493 | } | |
4494 | } | |
99112332 | 4495 | else if (i.reg_operands == 3 |
b6f8c7c4 L |
4496 | && i.op[0].regs == i.op[1].regs |
4497 | && !i.types[2].bitfield.xmmword | |
4498 | && (i.tm.opcode_modifier.vex | |
6225c532 | 4499 | || ((!i.mask.reg || i.mask.zeroing) |
e771e7c9 | 4500 | && is_evex_encoding (&i.tm) |
80c34c38 | 4501 | && (i.vec_encoding != vex_encoding_evex |
dd22218c | 4502 | || cpu_arch_isa_flags.bitfield.cpuavx512vl |
734dfd1c | 4503 | || is_cpu (&i.tm, CpuAVX512VL) |
7091c612 | 4504 | || (i.tm.operand_types[2].bitfield.zmmword |
dd22218c | 4505 | && i.types[2].bitfield.ymmword)))) |
ddb62495 | 4506 | && i.tm.opcode_space == SPACE_0F |
5844ccaa JB |
4507 | && ((i.tm.base_opcode | 2) == 0x57 |
4508 | || i.tm.base_opcode == 0xdf | |
4509 | || i.tm.base_opcode == 0xef | |
4510 | || (i.tm.base_opcode | 3) == 0xfb | |
4511 | || i.tm.base_opcode == 0x42 | |
4512 | || i.tm.base_opcode == 0x47)) | |
b6f8c7c4 | 4513 | { |
99112332 | 4514 | /* Optimize: -O1: |
8305403a L |
4515 | VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd, |
4516 | vpsubq and vpsubw: | |
b6f8c7c4 L |
4517 | EVEX VOP %zmmM, %zmmM, %zmmN |
4518 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4519 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4520 | EVEX VOP %ymmM, %ymmM, %ymmN |
4521 | -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4522 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4523 | VEX VOP %ymmM, %ymmM, %ymmN |
4524 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4525 | VOP, one of vpandn and vpxor: | |
4526 | VEX VOP %ymmM, %ymmM, %ymmN | |
4527 | -> VEX VOP %xmmM, %xmmM, %xmmN | |
4528 | VOP, one of vpandnd and vpandnq: | |
4529 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4530 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4531 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4532 | EVEX VOP %ymmM, %ymmM, %ymmN |
4533 | -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4534 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4535 | VOP, one of vpxord and vpxorq: |
4536 | EVEX VOP %zmmM, %zmmM, %zmmN | |
4537 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4538 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
b6f8c7c4 L |
4539 | EVEX VOP %ymmM, %ymmM, %ymmN |
4540 | -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16) | |
99112332 | 4541 | -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2) |
1424ad86 JB |
4542 | VOP, one of kxord and kxorq: |
4543 | VEX VOP %kM, %kM, %kN | |
4544 | -> VEX kxorw %kM, %kM, %kN | |
4545 | VOP, one of kandnd and kandnq: | |
4546 | VEX VOP %kM, %kM, %kN | |
4547 | -> VEX kandnw %kM, %kM, %kN | |
b6f8c7c4 | 4548 | */ |
e771e7c9 | 4549 | if (is_evex_encoding (&i.tm)) |
b6f8c7c4 | 4550 | { |
7b1d7ca1 | 4551 | if (i.vec_encoding != vex_encoding_evex) |
b6f8c7c4 L |
4552 | { |
4553 | i.tm.opcode_modifier.vex = VEX128; | |
4554 | i.tm.opcode_modifier.vexw = VEXW0; | |
4555 | i.tm.opcode_modifier.evex = 0; | |
4556 | } | |
7b1d7ca1 | 4557 | else if (optimize > 1) |
dd22218c L |
4558 | i.tm.opcode_modifier.evex = EVEX128; |
4559 | else | |
4560 | return; | |
b6f8c7c4 | 4561 | } |
f74a6307 | 4562 | else if (i.tm.operand_types[0].bitfield.class == RegMask) |
1424ad86 | 4563 | { |
35648716 | 4564 | i.tm.opcode_modifier.opcodeprefix = PREFIX_NONE; |
1424ad86 JB |
4565 | i.tm.opcode_modifier.vexw = VEXW0; |
4566 | } | |
b6f8c7c4 L |
4567 | else |
4568 | i.tm.opcode_modifier.vex = VEX128; | |
4569 | ||
4570 | if (i.tm.opcode_modifier.vex) | |
4571 | for (j = 0; j < 3; j++) | |
4572 | { | |
4573 | i.types[j].bitfield.xmmword = 1; | |
4574 | i.types[j].bitfield.ymmword = 0; | |
4575 | } | |
4576 | } | |
392a5972 | 4577 | else if (i.vec_encoding != vex_encoding_evex |
97ed31ae | 4578 | && !i.types[0].bitfield.zmmword |
392a5972 | 4579 | && !i.types[1].bitfield.zmmword |
6225c532 | 4580 | && !i.mask.reg |
9b345ce8 | 4581 | && !i.broadcast.type |
a5748e0d | 4582 | && !i.broadcast.bytes |
97ed31ae | 4583 | && is_evex_encoding (&i.tm) |
35648716 JB |
4584 | && ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4585 | || (i.tm.base_opcode & ~4) == 0xdb | |
4586 | || (i.tm.base_opcode & ~4) == 0xeb) | |
97ed31ae L |
4587 | && i.tm.extension_opcode == None) |
4588 | { | |
4589 | /* Optimize: -O1: | |
4590 | VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, | |
4591 | vmovdqu32 and vmovdqu64: | |
4592 | EVEX VOP %xmmM, %xmmN | |
4593 | -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16) | |
4594 | EVEX VOP %ymmM, %ymmN | |
4595 | -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16) | |
4596 | EVEX VOP %xmmM, mem | |
4597 | -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16) | |
4598 | EVEX VOP %ymmM, mem | |
4599 | -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16) | |
4600 | EVEX VOP mem, %xmmN | |
4601 | -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16) | |
4602 | EVEX VOP mem, %ymmN | |
4603 | -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16) | |
a0a1771e JB |
4604 | VOP, one of vpand, vpandn, vpor, vpxor: |
4605 | EVEX VOP{d,q} %xmmL, %xmmM, %xmmN | |
4606 | -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16) | |
4607 | EVEX VOP{d,q} %ymmL, %ymmM, %ymmN | |
4608 | -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16) | |
4609 | EVEX VOP{d,q} mem, %xmmM, %xmmN | |
4610 | -> VEX VOP mem, %xmmM, %xmmN (M and N < 16) | |
4611 | EVEX VOP{d,q} mem, %ymmM, %ymmN | |
4612 | -> VEX VOP mem, %ymmM, %ymmN (M and N < 16) | |
97ed31ae | 4613 | */ |
a0a1771e | 4614 | for (j = 0; j < i.operands; j++) |
392a5972 L |
4615 | if (operand_type_check (i.types[j], disp) |
4616 | && i.op[j].disps->X_op == O_constant) | |
4617 | { | |
4618 | /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix | |
4619 | has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4 | |
4620 | bytes, we choose EVEX Disp8 over VEX Disp32. */ | |
4621 | int evex_disp8, vex_disp8; | |
4622 | unsigned int memshift = i.memshift; | |
4623 | offsetT n = i.op[j].disps->X_add_number; | |
4624 | ||
4625 | evex_disp8 = fits_in_disp8 (n); | |
4626 | i.memshift = 0; | |
4627 | vex_disp8 = fits_in_disp8 (n); | |
4628 | if (evex_disp8 != vex_disp8) | |
4629 | { | |
4630 | i.memshift = memshift; | |
4631 | return; | |
4632 | } | |
4633 | ||
4634 | i.types[j].bitfield.disp8 = vex_disp8; | |
4635 | break; | |
4636 | } | |
35648716 JB |
4637 | if ((i.tm.base_opcode & ~Opcode_SIMD_IntD) == 0x6f |
4638 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_0XF2) | |
4639 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
97ed31ae L |
4640 | i.tm.opcode_modifier.vex |
4641 | = i.types[0].bitfield.ymmword ? VEX256 : VEX128; | |
4642 | i.tm.opcode_modifier.vexw = VEXW0; | |
79dec6b7 | 4643 | /* VPAND, VPOR, and VPXOR are commutative. */ |
35648716 | 4644 | if (i.reg_operands == 3 && i.tm.base_opcode != 0xdf) |
79dec6b7 | 4645 | i.tm.opcode_modifier.commutative = 1; |
97ed31ae L |
4646 | i.tm.opcode_modifier.evex = 0; |
4647 | i.tm.opcode_modifier.masking = 0; | |
a0a1771e | 4648 | i.tm.opcode_modifier.broadcast = 0; |
97ed31ae L |
4649 | i.tm.opcode_modifier.disp8memshift = 0; |
4650 | i.memshift = 0; | |
a0a1771e JB |
4651 | if (j < i.operands) |
4652 | i.types[j].bitfield.disp8 | |
4653 | = fits_in_disp8 (i.op[j].disps->X_add_number); | |
97ed31ae | 4654 | } |
b5c37946 SJ |
4655 | else if (optimize_for_space |
4656 | && i.tm.base_opcode == 0x29 | |
4657 | && i.tm.opcode_space == SPACE_0F38 | |
4658 | && i.operands == i.reg_operands | |
4659 | && i.op[0].regs == i.op[1].regs | |
4660 | && (!i.tm.opcode_modifier.vex | |
4661 | || !(i.op[0].regs->reg_flags & RegRex)) | |
4662 | && !is_evex_encoding (&i.tm)) | |
4663 | { | |
4664 | /* Optimize: -Os: | |
4665 | pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN | |
4666 | vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8) | |
4667 | vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8) | |
4668 | */ | |
4669 | i.tm.opcode_space = SPACE_0F; | |
4670 | i.tm.base_opcode = 0x76; | |
4671 | } | |
4672 | else if (((i.tm.base_opcode >= 0x64 | |
4673 | && i.tm.base_opcode <= 0x66 | |
4674 | && i.tm.opcode_space == SPACE_0F) | |
4675 | || (i.tm.base_opcode == 0x37 | |
4676 | && i.tm.opcode_space == SPACE_0F38)) | |
4677 | && i.operands == i.reg_operands | |
4678 | && i.op[0].regs == i.op[1].regs | |
4679 | && !is_evex_encoding (&i.tm)) | |
4680 | { | |
4681 | /* Optimize: -O: | |
4682 | pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN | |
4683 | pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN | |
4684 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8) | |
4685 | vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7) | |
4686 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8) | |
4687 | vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7) | |
4688 | */ | |
4689 | i.tm.opcode_space = SPACE_0F; | |
4690 | i.tm.base_opcode = 0xef; | |
4691 | if (i.tm.opcode_modifier.vex && (i.op[0].regs->reg_flags & RegRex)) | |
4692 | { | |
4693 | if (i.operands == 2) | |
4694 | { | |
4695 | gas_assert (i.tm.opcode_modifier.sse2avx); | |
4696 | ||
4697 | i.operands = 3; | |
4698 | i.reg_operands = 3; | |
4699 | i.tm.operands = 3; | |
4700 | ||
4701 | i.op[2].regs = i.op[0].regs; | |
4702 | i.types[2] = i.types[0]; | |
4703 | i.flags[2] = i.flags[0]; | |
4704 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
4705 | ||
4706 | i.tm.opcode_modifier.sse2avx = 0; | |
4707 | } | |
4708 | i.op[0].regs -= i.op[0].regs->reg_num + 8; | |
4709 | i.op[1].regs = i.op[0].regs; | |
4710 | } | |
4711 | } | |
4712 | else if (optimize_for_space | |
4713 | && i.tm.base_opcode == 0x59 | |
4714 | && i.tm.opcode_space == SPACE_0F38 | |
4715 | && i.operands == i.reg_operands | |
4716 | && i.tm.opcode_modifier.vex | |
4717 | && !(i.op[0].regs->reg_flags & RegRex) | |
4718 | && i.op[0].regs->reg_type.bitfield.xmmword | |
4719 | && i.vec_encoding != vex_encoding_vex3) | |
4720 | { | |
4721 | /* Optimize: -Os: | |
4722 | vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8) | |
4723 | */ | |
4724 | i.tm.opcode_space = SPACE_0F; | |
4725 | i.tm.base_opcode = 0x6c; | |
4726 | i.tm.opcode_modifier.vexvvvv = 1; | |
4727 | ||
4728 | ++i.operands; | |
4729 | ++i.reg_operands; | |
4730 | ++i.tm.operands; | |
4731 | ||
4732 | i.op[2].regs = i.op[0].regs; | |
4733 | i.types[2] = i.types[0]; | |
4734 | i.flags[2] = i.flags[0]; | |
4735 | i.tm.operand_types[2] = i.tm.operand_types[0]; | |
4736 | ||
4737 | swap_2_operands (1, 2); | |
4738 | } | |
b6f8c7c4 L |
4739 | } |
4740 | ||
ae531041 L |
4741 | /* Return non-zero for load instruction. */ |
4742 | ||
4743 | static int | |
4744 | load_insn_p (void) | |
4745 | { | |
4746 | unsigned int dest; | |
4747 | int any_vex_p = is_any_vex_encoding (&i.tm); | |
4748 | unsigned int base_opcode = i.tm.base_opcode | 1; | |
4749 | ||
4750 | if (!any_vex_p) | |
4751 | { | |
ef07be45 CL |
4752 | /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu, |
4753 | bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */ | |
255571cd | 4754 | if (i.tm.opcode_modifier.operandconstraint == ANY_SIZE) |
ae531041 L |
4755 | return 0; |
4756 | ||
389d00a5 | 4757 | /* pop. */ |
6d86a545 | 4758 | if (i.tm.mnem_off == MN_pop) |
389d00a5 JB |
4759 | return 1; |
4760 | } | |
4761 | ||
ddb62495 | 4762 | if (i.tm.opcode_space == SPACE_BASE) |
389d00a5 JB |
4763 | { |
4764 | /* popf, popa. */ | |
4765 | if (i.tm.base_opcode == 0x9d | |
a09f656b | 4766 | || i.tm.base_opcode == 0x61) |
ae531041 L |
4767 | return 1; |
4768 | ||
4769 | /* movs, cmps, lods, scas. */ | |
4770 | if ((i.tm.base_opcode | 0xb) == 0xaf) | |
4771 | return 1; | |
4772 | ||
a09f656b | 4773 | /* outs, xlatb. */ |
4774 | if (base_opcode == 0x6f | |
4775 | || i.tm.base_opcode == 0xd7) | |
ae531041 | 4776 | return 1; |
a09f656b | 4777 | /* NB: For AMD-specific insns with implicit memory operands, |
4778 | they're intentionally not covered. */ | |
ae531041 L |
4779 | } |
4780 | ||
4781 | /* No memory operand. */ | |
4782 | if (!i.mem_operands) | |
4783 | return 0; | |
4784 | ||
4785 | if (any_vex_p) | |
4786 | { | |
7fc69528 | 4787 | if (i.tm.mnem_off == MN_vldmxcsr) |
ae531041 L |
4788 | return 1; |
4789 | } | |
ddb62495 | 4790 | else if (i.tm.opcode_space == SPACE_BASE) |
ae531041 L |
4791 | { |
4792 | /* test, not, neg, mul, imul, div, idiv. */ | |
aa4c197d | 4793 | if (base_opcode == 0xf7 && i.tm.extension_opcode != 1) |
ae531041 L |
4794 | return 1; |
4795 | ||
4796 | /* inc, dec. */ | |
4797 | if (base_opcode == 0xff && i.tm.extension_opcode <= 1) | |
4798 | return 1; | |
4799 | ||
4800 | /* add, or, adc, sbb, and, sub, xor, cmp. */ | |
4801 | if (i.tm.base_opcode >= 0x80 && i.tm.base_opcode <= 0x83) | |
4802 | return 1; | |
4803 | ||
ae531041 | 4804 | /* rol, ror, rcl, rcr, shl/sal, shr, sar. */ |
aa4c197d | 4805 | if ((base_opcode == 0xc1 || (base_opcode | 2) == 0xd3) |
ae531041 L |
4806 | && i.tm.extension_opcode != 6) |
4807 | return 1; | |
4808 | ||
ae531041 | 4809 | /* Check for x87 instructions. */ |
aa4c197d | 4810 | if ((base_opcode | 6) == 0xdf) |
ae531041 L |
4811 | { |
4812 | /* Skip fst, fstp, fstenv, fstcw. */ | |
4813 | if (i.tm.base_opcode == 0xd9 | |
4814 | && (i.tm.extension_opcode == 2 | |
4815 | || i.tm.extension_opcode == 3 | |
4816 | || i.tm.extension_opcode == 6 | |
4817 | || i.tm.extension_opcode == 7)) | |
4818 | return 0; | |
4819 | ||
4820 | /* Skip fisttp, fist, fistp, fstp. */ | |
4821 | if (i.tm.base_opcode == 0xdb | |
4822 | && (i.tm.extension_opcode == 1 | |
4823 | || i.tm.extension_opcode == 2 | |
4824 | || i.tm.extension_opcode == 3 | |
4825 | || i.tm.extension_opcode == 7)) | |
4826 | return 0; | |
4827 | ||
4828 | /* Skip fisttp, fst, fstp, fsave, fstsw. */ | |
4829 | if (i.tm.base_opcode == 0xdd | |
4830 | && (i.tm.extension_opcode == 1 | |
4831 | || i.tm.extension_opcode == 2 | |
4832 | || i.tm.extension_opcode == 3 | |
4833 | || i.tm.extension_opcode == 6 | |
4834 | || i.tm.extension_opcode == 7)) | |
4835 | return 0; | |
4836 | ||
4837 | /* Skip fisttp, fist, fistp, fbstp, fistp. */ | |
4838 | if (i.tm.base_opcode == 0xdf | |
4839 | && (i.tm.extension_opcode == 1 | |
4840 | || i.tm.extension_opcode == 2 | |
4841 | || i.tm.extension_opcode == 3 | |
4842 | || i.tm.extension_opcode == 6 | |
4843 | || i.tm.extension_opcode == 7)) | |
4844 | return 0; | |
4845 | ||
4846 | return 1; | |
4847 | } | |
4848 | } | |
ddb62495 | 4849 | else if (i.tm.opcode_space == SPACE_0F) |
389d00a5 JB |
4850 | { |
4851 | /* bt, bts, btr, btc. */ | |
4852 | if (i.tm.base_opcode == 0xba | |
aa4c197d | 4853 | && (i.tm.extension_opcode | 3) == 7) |
389d00a5 JB |
4854 | return 1; |
4855 | ||
4856 | /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */ | |
4857 | if (i.tm.base_opcode == 0xc7 | |
4858 | && i.tm.opcode_modifier.opcodeprefix == PREFIX_NONE | |
4859 | && (i.tm.extension_opcode == 1 || i.tm.extension_opcode == 3 | |
4860 | || i.tm.extension_opcode == 6)) | |
4861 | return 1; | |
4862 | ||
4863 | /* fxrstor, ldmxcsr, xrstor. */ | |
4864 | if (i.tm.base_opcode == 0xae | |
4865 | && (i.tm.extension_opcode == 1 | |
4866 | || i.tm.extension_opcode == 2 | |
4867 | || i.tm.extension_opcode == 5)) | |
4868 | return 1; | |
4869 | ||
4870 | /* lgdt, lidt, lmsw. */ | |
4871 | if (i.tm.base_opcode == 0x01 | |
4872 | && (i.tm.extension_opcode == 2 | |
4873 | || i.tm.extension_opcode == 3 | |
4874 | || i.tm.extension_opcode == 6)) | |
4875 | return 1; | |
4876 | } | |
ae531041 L |
4877 | |
4878 | dest = i.operands - 1; | |
4879 | ||
4880 | /* Check fake imm8 operand and 3 source operands. */ | |
4881 | if ((i.tm.opcode_modifier.immext | |
aa180741 | 4882 | || i.reg_operands + i.mem_operands == 4) |
ae531041 L |
4883 | && i.types[dest].bitfield.imm8) |
4884 | dest--; | |
4885 | ||
389d00a5 | 4886 | /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */ |
ddb62495 | 4887 | if (i.tm.opcode_space == SPACE_BASE |
aa4c197d | 4888 | && ((base_opcode | 0x38) == 0x39 |
389d00a5 JB |
4889 | || (base_opcode | 2) == 0x87)) |
4890 | return 1; | |
4891 | ||
7fc69528 | 4892 | if (i.tm.mnem_off == MN_xadd) |
ae531041 L |
4893 | return 1; |
4894 | ||
4895 | /* Check for load instruction. */ | |
4896 | return (i.types[dest].bitfield.class != ClassNone | |
4897 | || i.types[dest].bitfield.instance == Accum); | |
4898 | } | |
4899 | ||
4900 | /* Output lfence, 0xfaee8, after instruction. */ | |
4901 | ||
4902 | static void | |
4903 | insert_lfence_after (void) | |
4904 | { | |
4905 | if (lfence_after_load && load_insn_p ()) | |
4906 | { | |
a09f656b | 4907 | /* There are also two REP string instructions that require |
4908 | special treatment. Specifically, the compare string (CMPS) | |
4909 | and scan string (SCAS) instructions set EFLAGS in a manner | |
4910 | that depends on the data being compared/scanned. When used | |
4911 | with a REP prefix, the number of iterations may therefore | |
4912 | vary depending on this data. If the data is a program secret | |
4913 | chosen by the adversary using an LVI method, | |
4914 | then this data-dependent behavior may leak some aspect | |
4915 | of the secret. */ | |
aa4c197d | 4916 | if (((i.tm.base_opcode | 0x9) == 0xaf) |
a09f656b | 4917 | && i.prefix[REP_PREFIX]) |
4918 | { | |
4919 | as_warn (_("`%s` changes flags which would affect control flow behavior"), | |
76d3f746 | 4920 | insn_name (&i.tm)); |
a09f656b | 4921 | } |
ae531041 L |
4922 | char *p = frag_more (3); |
4923 | *p++ = 0xf; | |
4924 | *p++ = 0xae; | |
4925 | *p = 0xe8; | |
4926 | } | |
4927 | } | |
4928 | ||
4929 | /* Output lfence, 0xfaee8, before instruction. */ | |
4930 | ||
4931 | static void | |
4932 | insert_lfence_before (void) | |
4933 | { | |
4934 | char *p; | |
4935 | ||
ddb62495 | 4936 | if (i.tm.opcode_space != SPACE_BASE) |
ae531041 L |
4937 | return; |
4938 | ||
4939 | if (i.tm.base_opcode == 0xff | |
4940 | && (i.tm.extension_opcode == 2 || i.tm.extension_opcode == 4)) | |
4941 | { | |
4942 | /* Insert lfence before indirect branch if needed. */ | |
4943 | ||
4944 | if (lfence_before_indirect_branch == lfence_branch_none) | |
4945 | return; | |
4946 | ||
4947 | if (i.operands != 1) | |
4948 | abort (); | |
4949 | ||
4950 | if (i.reg_operands == 1) | |
4951 | { | |
4952 | /* Indirect branch via register. Don't insert lfence with | |
4953 | -mlfence-after-load=yes. */ | |
4954 | if (lfence_after_load | |
4955 | || lfence_before_indirect_branch == lfence_branch_memory) | |
4956 | return; | |
4957 | } | |
4958 | else if (i.mem_operands == 1 | |
4959 | && lfence_before_indirect_branch != lfence_branch_register) | |
4960 | { | |
4961 | as_warn (_("indirect `%s` with memory operand should be avoided"), | |
76d3f746 | 4962 | insn_name (&i.tm)); |
ae531041 L |
4963 | return; |
4964 | } | |
4965 | else | |
4966 | return; | |
4967 | ||
4968 | if (last_insn.kind != last_insn_other | |
4969 | && last_insn.seg == now_seg) | |
4970 | { | |
4971 | as_warn_where (last_insn.file, last_insn.line, | |
4972 | _("`%s` skips -mlfence-before-indirect-branch on `%s`"), | |
76d3f746 | 4973 | last_insn.name, insn_name (&i.tm)); |
ae531041 L |
4974 | return; |
4975 | } | |
4976 | ||
4977 | p = frag_more (3); | |
4978 | *p++ = 0xf; | |
4979 | *p++ = 0xae; | |
4980 | *p = 0xe8; | |
4981 | return; | |
4982 | } | |
4983 | ||
503648e4 | 4984 | /* Output or/not/shl and lfence before near ret. */ |
ae531041 | 4985 | if (lfence_before_ret != lfence_before_ret_none |
aa4c197d | 4986 | && (i.tm.base_opcode | 1) == 0xc3) |
ae531041 L |
4987 | { |
4988 | if (last_insn.kind != last_insn_other | |
4989 | && last_insn.seg == now_seg) | |
4990 | { | |
4991 | as_warn_where (last_insn.file, last_insn.line, | |
4992 | _("`%s` skips -mlfence-before-ret on `%s`"), | |
76d3f746 | 4993 | last_insn.name, insn_name (&i.tm)); |
ae531041 L |
4994 | return; |
4995 | } | |
a09f656b | 4996 | |
a09f656b | 4997 | /* Near ret ingore operand size override under CPU64. */ |
503648e4 | 4998 | char prefix = flag_code == CODE_64BIT |
4999 | ? 0x48 | |
5000 | : i.prefix[DATA_PREFIX] ? 0x66 : 0x0; | |
a09f656b | 5001 | |
5002 | if (lfence_before_ret == lfence_before_ret_not) | |
5003 | { | |
5004 | /* not: 0xf71424, may add prefix | |
5005 | for operand size override or 64-bit code. */ | |
5006 | p = frag_more ((prefix ? 2 : 0) + 6 + 3); | |
5007 | if (prefix) | |
5008 | *p++ = prefix; | |
ae531041 L |
5009 | *p++ = 0xf7; |
5010 | *p++ = 0x14; | |
5011 | *p++ = 0x24; | |
a09f656b | 5012 | if (prefix) |
5013 | *p++ = prefix; | |
ae531041 L |
5014 | *p++ = 0xf7; |
5015 | *p++ = 0x14; | |
5016 | *p++ = 0x24; | |
5017 | } | |
a09f656b | 5018 | else |
5019 | { | |
5020 | p = frag_more ((prefix ? 1 : 0) + 4 + 3); | |
5021 | if (prefix) | |
5022 | *p++ = prefix; | |
5023 | if (lfence_before_ret == lfence_before_ret_or) | |
5024 | { | |
5025 | /* or: 0x830c2400, may add prefix | |
5026 | for operand size override or 64-bit code. */ | |
5027 | *p++ = 0x83; | |
5028 | *p++ = 0x0c; | |
5029 | } | |
5030 | else | |
5031 | { | |
5032 | /* shl: 0xc1242400, may add prefix | |
5033 | for operand size override or 64-bit code. */ | |
5034 | *p++ = 0xc1; | |
5035 | *p++ = 0x24; | |
5036 | } | |
5037 | ||
5038 | *p++ = 0x24; | |
5039 | *p++ = 0x0; | |
5040 | } | |
5041 | ||
ae531041 L |
5042 | *p++ = 0xf; |
5043 | *p++ = 0xae; | |
5044 | *p = 0xe8; | |
5045 | } | |
5046 | } | |
5047 | ||
edd67638 JB |
5048 | /* Shared helper for md_assemble() and s_insn(). */ |
5049 | static void init_globals (void) | |
5050 | { | |
5051 | unsigned int j; | |
5052 | ||
5053 | memset (&i, '\0', sizeof (i)); | |
5054 | i.rounding.type = rc_none; | |
5055 | for (j = 0; j < MAX_OPERANDS; j++) | |
5056 | i.reloc[j] = NO_RELOC; | |
5057 | memset (disp_expressions, '\0', sizeof (disp_expressions)); | |
5058 | memset (im_expressions, '\0', sizeof (im_expressions)); | |
5059 | save_stack_p = save_stack; | |
5060 | } | |
5061 | ||
04784e33 JB |
5062 | /* Helper for md_assemble() to decide whether to prepare for a possible 2nd |
5063 | parsing pass. Instead of introducing a rarely use new insn attribute this | |
5064 | utilizes a common pattern between affected templates. It is deemed | |
5065 | acceptable that this will lead to unnecessary pass 2 preparations in a | |
5066 | limited set of cases. */ | |
5067 | static INLINE bool may_need_pass2 (const insn_template *t) | |
5068 | { | |
5069 | return t->opcode_modifier.sse2avx | |
5070 | /* Note that all SSE2AVX templates have at least one operand. */ | |
a28fedbc | 5071 | ? t->operand_types[t->operands - 1].bitfield.class == RegSIMD |
ddb62495 | 5072 | : (t->opcode_space == SPACE_0F |
a28fedbc | 5073 | && (t->base_opcode | 1) == 0xbf) |
ddb62495 | 5074 | || (t->opcode_space == SPACE_BASE |
a28fedbc | 5075 | && t->base_opcode == 0x63); |
04784e33 JB |
5076 | } |
5077 | ||
252b5132 RH |
5078 | /* This is the guts of the machine-dependent assembler. LINE points to a |
5079 | machine dependent instruction. This function is supposed to emit | |
5080 | the frags/bytes it assembles to. */ | |
5081 | ||
5082 | void | |
65da13b5 | 5083 | md_assemble (char *line) |
252b5132 | 5084 | { |
40fb9820 | 5085 | unsigned int j; |
9db83a32 | 5086 | char mnemonic[MAX_MNEM_SIZE], mnem_suffix = 0, *copy = NULL; |
04784e33 JB |
5087 | const char *end, *pass1_mnem = NULL; |
5088 | enum i386_error pass1_err = 0; | |
d3ce72d0 | 5089 | const insn_template *t; |
252b5132 | 5090 | |
47926f60 | 5091 | /* Initialize globals. */ |
04784e33 JB |
5092 | current_templates = NULL; |
5093 | retry: | |
edd67638 | 5094 | init_globals (); |
252b5132 RH |
5095 | |
5096 | /* First parse an instruction mnemonic & call i386_operand for the operands. | |
5097 | We assume that the scrubber has arranged it so that line[0] is the valid | |
47926f60 | 5098 | start of a (possibly prefixed) mnemonic. */ |
252b5132 | 5099 | |
edd67638 | 5100 | end = parse_insn (line, mnemonic, false); |
5317ad2c | 5101 | if (end == NULL) |
04784e33 JB |
5102 | { |
5103 | if (pass1_mnem != NULL) | |
5104 | goto match_error; | |
9db83a32 JB |
5105 | if (i.error != no_error) |
5106 | { | |
5107 | gas_assert (current_templates != NULL); | |
5108 | if (may_need_pass2 (current_templates->start) && !i.suffix) | |
5109 | goto no_match; | |
5110 | /* No point in trying a 2nd pass - it'll only find the same suffix | |
5111 | again. */ | |
5112 | mnem_suffix = i.suffix; | |
5113 | goto match_error; | |
5114 | } | |
04784e33 JB |
5115 | return; |
5116 | } | |
6d86a545 JB |
5117 | t = current_templates->start; |
5118 | if (may_need_pass2 (t)) | |
04784e33 JB |
5119 | { |
5120 | /* Make a copy of the full line in case we need to retry. */ | |
5121 | copy = xstrdup (line); | |
5122 | } | |
5317ad2c | 5123 | line += end - line; |
83b16ac6 | 5124 | mnem_suffix = i.suffix; |
252b5132 | 5125 | |
29b0f896 | 5126 | line = parse_operands (line, mnemonic); |
ee86248c | 5127 | this_operand = -1; |
29b0f896 | 5128 | if (line == NULL) |
04784e33 JB |
5129 | { |
5130 | free (copy); | |
5131 | return; | |
5132 | } | |
252b5132 | 5133 | |
29b0f896 AM |
5134 | /* Now we've parsed the mnemonic into a set of templates, and have the |
5135 | operands at hand. */ | |
5136 | ||
b630c145 | 5137 | /* All Intel opcodes have reversed operands except for "bound", "enter", |
c0e54661 | 5138 | "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate", |
b0e8fa7f TJ |
5139 | "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse |
5140 | intersegment "jmp" and "call" instructions with 2 immediate operands so | |
5141 | that the immediate segment precedes the offset consistently in Intel and | |
5142 | AT&T modes. */ | |
4d456e3d L |
5143 | if (intel_syntax |
5144 | && i.operands > 1 | |
6d86a545 JB |
5145 | && (t->mnem_off != MN_bound) |
5146 | && !startswith (mnemonic, "invlpg") | |
d34049e8 ML |
5147 | && !startswith (mnemonic, "monitor") |
5148 | && !startswith (mnemonic, "mwait") | |
6d86a545 | 5149 | && (t->mnem_off != MN_pvalidate) |
d34049e8 | 5150 | && !startswith (mnemonic, "rmp") |
6d86a545 JB |
5151 | && (t->mnem_off != MN_tpause) |
5152 | && (t->mnem_off != MN_umwait) | |
47c0279b JB |
5153 | && !(i.operands == 2 |
5154 | && operand_type_check (i.types[0], imm) | |
40fb9820 | 5155 | && operand_type_check (i.types[1], imm))) |
29b0f896 AM |
5156 | swap_operands (); |
5157 | ||
ec56d5c0 JB |
5158 | /* The order of the immediates should be reversed |
5159 | for 2 immediates extrq and insertq instructions */ | |
5160 | if (i.imm_operands == 2 | |
6d86a545 | 5161 | && (t->mnem_off == MN_extrq || t->mnem_off == MN_insertq)) |
ec56d5c0 JB |
5162 | swap_2_operands (0, 1); |
5163 | ||
29b0f896 AM |
5164 | if (i.imm_operands) |
5165 | optimize_imm (); | |
5166 | ||
0de704b9 JB |
5167 | if (i.disp_operands && !optimize_disp (t)) |
5168 | return; | |
29b0f896 AM |
5169 | |
5170 | /* Next, we find a template that matches the given insn, | |
5171 | making sure the overlap of the given operands types is consistent | |
5172 | with the template operand types. */ | |
252b5132 | 5173 | |
83b16ac6 | 5174 | if (!(t = match_template (mnem_suffix))) |
04784e33 JB |
5175 | { |
5176 | const char *err_msg; | |
5177 | ||
5178 | if (copy && !mnem_suffix) | |
5179 | { | |
5180 | line = copy; | |
5181 | copy = NULL; | |
9db83a32 | 5182 | no_match: |
04784e33 | 5183 | pass1_err = i.error; |
76d3f746 | 5184 | pass1_mnem = insn_name (current_templates->start); |
04784e33 JB |
5185 | goto retry; |
5186 | } | |
9db83a32 JB |
5187 | |
5188 | /* If a non-/only-64bit template (group) was found in pass 1, and if | |
5189 | _some_ template (group) was found in pass 2, squash pass 1's | |
5190 | error. */ | |
5191 | if (pass1_err == unsupported_64bit) | |
5192 | pass1_mnem = NULL; | |
5193 | ||
04784e33 | 5194 | match_error: |
9db83a32 JB |
5195 | free (copy); |
5196 | ||
04784e33 JB |
5197 | switch (pass1_mnem ? pass1_err : i.error) |
5198 | { | |
5199 | default: | |
5200 | abort (); | |
5201 | case operand_size_mismatch: | |
5202 | err_msg = _("operand size mismatch"); | |
5203 | break; | |
5204 | case operand_type_mismatch: | |
5205 | err_msg = _("operand type mismatch"); | |
5206 | break; | |
5207 | case register_type_mismatch: | |
5208 | err_msg = _("register type mismatch"); | |
5209 | break; | |
5210 | case number_of_operands_mismatch: | |
5211 | err_msg = _("number of operands mismatch"); | |
5212 | break; | |
5213 | case invalid_instruction_suffix: | |
5214 | err_msg = _("invalid instruction suffix"); | |
5215 | break; | |
5216 | case bad_imm4: | |
5217 | err_msg = _("constant doesn't fit in 4 bits"); | |
5218 | break; | |
5219 | case unsupported_with_intel_mnemonic: | |
5220 | err_msg = _("unsupported with Intel mnemonic"); | |
5221 | break; | |
5222 | case unsupported_syntax: | |
5223 | err_msg = _("unsupported syntax"); | |
5224 | break; | |
5225 | case unsupported: | |
5226 | as_bad (_("unsupported instruction `%s'"), | |
76d3f746 | 5227 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
04784e33 | 5228 | return; |
9db83a32 JB |
5229 | case unsupported_on_arch: |
5230 | as_bad (_("`%s' is not supported on `%s%s'"), | |
76d3f746 | 5231 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start), |
9db83a32 JB |
5232 | cpu_arch_name ? cpu_arch_name : default_arch, |
5233 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); | |
5234 | return; | |
5235 | case unsupported_64bit: | |
5236 | if (ISLOWER (mnem_suffix)) | |
e8b4b7b2 NC |
5237 | { |
5238 | if (flag_code == CODE_64BIT) | |
5239 | as_bad (_("`%s%c' is not supported in 64-bit mode"), | |
76d3f746 | 5240 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start), |
e8b4b7b2 NC |
5241 | mnem_suffix); |
5242 | else | |
5243 | as_bad (_("`%s%c' is only supported in 64-bit mode"), | |
76d3f746 | 5244 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start), |
e8b4b7b2 NC |
5245 | mnem_suffix); |
5246 | } | |
9db83a32 | 5247 | else |
e8b4b7b2 NC |
5248 | { |
5249 | if (flag_code == CODE_64BIT) | |
5250 | as_bad (_("`%s' is not supported in 64-bit mode"), | |
76d3f746 | 5251 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
e8b4b7b2 NC |
5252 | else |
5253 | as_bad (_("`%s' is only supported in 64-bit mode"), | |
76d3f746 | 5254 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
e8b4b7b2 | 5255 | } |
9db83a32 | 5256 | return; |
04784e33 JB |
5257 | case invalid_sib_address: |
5258 | err_msg = _("invalid SIB address"); | |
5259 | break; | |
5260 | case invalid_vsib_address: | |
5261 | err_msg = _("invalid VSIB address"); | |
5262 | break; | |
5263 | case invalid_vector_register_set: | |
5264 | err_msg = _("mask, index, and destination registers must be distinct"); | |
5265 | break; | |
5266 | case invalid_tmm_register_set: | |
5267 | err_msg = _("all tmm registers must be distinct"); | |
5268 | break; | |
5269 | case invalid_dest_and_src_register_set: | |
5270 | err_msg = _("destination and source registers must be distinct"); | |
5271 | break; | |
5272 | case unsupported_vector_index_register: | |
5273 | err_msg = _("unsupported vector index register"); | |
5274 | break; | |
5275 | case unsupported_broadcast: | |
5276 | err_msg = _("unsupported broadcast"); | |
5277 | break; | |
5278 | case broadcast_needed: | |
5279 | err_msg = _("broadcast is needed for operand of such type"); | |
5280 | break; | |
5281 | case unsupported_masking: | |
5282 | err_msg = _("unsupported masking"); | |
5283 | break; | |
5284 | case mask_not_on_destination: | |
5285 | err_msg = _("mask not on destination operand"); | |
5286 | break; | |
5287 | case no_default_mask: | |
5288 | err_msg = _("default mask isn't allowed"); | |
5289 | break; | |
5290 | case unsupported_rc_sae: | |
5291 | err_msg = _("unsupported static rounding/sae"); | |
5292 | break; | |
5293 | case invalid_register_operand: | |
5294 | err_msg = _("invalid register operand"); | |
5295 | break; | |
5296 | } | |
5297 | as_bad (_("%s for `%s'"), err_msg, | |
76d3f746 | 5298 | pass1_mnem ? pass1_mnem : insn_name (current_templates->start)); |
04784e33 JB |
5299 | return; |
5300 | } | |
5301 | ||
5302 | free (copy); | |
252b5132 | 5303 | |
7bab8ab5 | 5304 | if (sse_check != check_none |
ffb86450 JB |
5305 | /* The opcode space check isn't strictly needed; it's there only to |
5306 | bypass the logic below when easily possible. */ | |
ddb62495 JB |
5307 | && t->opcode_space >= SPACE_0F |
5308 | && t->opcode_space <= SPACE_0F3A | |
734dfd1c | 5309 | && !is_cpu (&i.tm, CpuSSE4a) |
ffb86450 | 5310 | && !is_any_vex_encoding (t)) |
daf50ae7 | 5311 | { |
ffb86450 JB |
5312 | bool simd = false; |
5313 | ||
5314 | for (j = 0; j < t->operands; ++j) | |
5315 | { | |
5316 | if (t->operand_types[j].bitfield.class == RegMMX) | |
5317 | break; | |
5318 | if (t->operand_types[j].bitfield.class == RegSIMD) | |
5319 | simd = true; | |
5320 | } | |
5321 | ||
5322 | if (j >= t->operands && simd) | |
5323 | (sse_check == check_warning | |
5324 | ? as_warn | |
76d3f746 | 5325 | : as_bad) (_("SSE instruction `%s' is used"), insn_name (&i.tm)); |
daf50ae7 L |
5326 | } |
5327 | ||
40fb9820 | 5328 | if (i.tm.opcode_modifier.fwait) |
29b0f896 AM |
5329 | if (!add_prefix (FWAIT_OPCODE)) |
5330 | return; | |
252b5132 | 5331 | |
d5de92cf | 5332 | /* Check if REP prefix is OK. */ |
742732c7 | 5333 | if (i.rep_prefix && i.tm.opcode_modifier.prefixok != PrefixRep) |
d5de92cf L |
5334 | { |
5335 | as_bad (_("invalid instruction `%s' after `%s'"), | |
76d3f746 | 5336 | insn_name (&i.tm), i.rep_prefix); |
d5de92cf L |
5337 | return; |
5338 | } | |
5339 | ||
c1ba0266 L |
5340 | /* Check for lock without a lockable instruction. Destination operand |
5341 | must be memory unless it is xchg (0x86). */ | |
9a4a4499 JB |
5342 | if (i.prefix[LOCK_PREFIX]) |
5343 | { | |
5344 | if (i.tm.opcode_modifier.prefixok < PrefixLock | |
c1ba0266 L |
5345 | || i.mem_operands == 0 |
5346 | || (i.tm.base_opcode != 0x86 | |
9a4a4499 JB |
5347 | && !(i.flags[i.operands - 1] & Operand_Mem))) |
5348 | { | |
5349 | as_bad (_("expecting lockable instruction after `lock'")); | |
5350 | return; | |
5351 | } | |
5352 | ||
5353 | /* Zap the redundant prefix from XCHG when optimizing. */ | |
5354 | if (i.tm.base_opcode == 0x86 && optimize && !i.no_optimize) | |
5355 | i.prefix[LOCK_PREFIX] = 0; | |
c32fa91d L |
5356 | } |
5357 | ||
e3669c7f JB |
5358 | if (is_any_vex_encoding (&i.tm) |
5359 | || i.tm.operand_types[i.imm_operands].bitfield.class >= RegMMX | |
5360 | || i.tm.operand_types[i.imm_operands + 1].bitfield.class >= RegMMX) | |
7a8655d2 | 5361 | { |
e3669c7f JB |
5362 | /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */ |
5363 | if (i.prefix[DATA_PREFIX]) | |
5364 | { | |
76d3f746 | 5365 | as_bad (_("data size prefix invalid with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
5366 | return; |
5367 | } | |
5368 | ||
5369 | /* Don't allow e.g. KMOV in TLS code sequences. */ | |
5370 | for (j = i.imm_operands; j < i.operands; ++j) | |
5371 | switch (i.reloc[j]) | |
5372 | { | |
5373 | case BFD_RELOC_386_TLS_GOTIE: | |
5374 | case BFD_RELOC_386_TLS_LE_32: | |
5375 | case BFD_RELOC_X86_64_GOTTPOFF: | |
5376 | case BFD_RELOC_X86_64_TLSLD: | |
76d3f746 | 5377 | as_bad (_("TLS relocation cannot be used with `%s'"), insn_name (&i.tm)); |
e3669c7f JB |
5378 | return; |
5379 | default: | |
5380 | break; | |
5381 | } | |
7a8655d2 JB |
5382 | } |
5383 | ||
42164a71 | 5384 | /* Check if HLE prefix is OK. */ |
165de32a | 5385 | if (i.hle_prefix && !check_hle ()) |
42164a71 L |
5386 | return; |
5387 | ||
7e8b059b L |
5388 | /* Check BND prefix. */ |
5389 | if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok) | |
5390 | as_bad (_("expecting valid branch instruction after `bnd'")); | |
5391 | ||
04ef582a | 5392 | /* Check NOTRACK prefix. */ |
742732c7 | 5393 | if (i.notrack_prefix && i.tm.opcode_modifier.prefixok != PrefixNoTrack) |
9fef80d6 | 5394 | as_bad (_("expecting indirect branch instruction after `notrack'")); |
04ef582a | 5395 | |
734dfd1c | 5396 | if (is_cpu (&i.tm, CpuMPX)) |
327e8c42 JB |
5397 | { |
5398 | if (flag_code == CODE_64BIT && i.prefix[ADDR_PREFIX]) | |
5399 | as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions.")); | |
5400 | else if (flag_code != CODE_16BIT | |
5401 | ? i.prefix[ADDR_PREFIX] | |
5402 | : i.mem_operands && !i.prefix[ADDR_PREFIX]) | |
5403 | as_bad (_("16-bit address isn't allowed in MPX instructions")); | |
5404 | } | |
7e8b059b L |
5405 | |
5406 | /* Insert BND prefix. */ | |
76d3a78a JB |
5407 | if (add_bnd_prefix && i.tm.opcode_modifier.bndprefixok) |
5408 | { | |
5409 | if (!i.prefix[BND_PREFIX]) | |
5410 | add_prefix (BND_PREFIX_OPCODE); | |
5411 | else if (i.prefix[BND_PREFIX] != BND_PREFIX_OPCODE) | |
5412 | { | |
5413 | as_warn (_("replacing `rep'/`repe' prefix by `bnd'")); | |
5414 | i.prefix[BND_PREFIX] = BND_PREFIX_OPCODE; | |
5415 | } | |
5416 | } | |
7e8b059b | 5417 | |
29b0f896 | 5418 | /* Check string instruction segment overrides. */ |
51c8edf6 | 5419 | if (i.tm.opcode_modifier.isstring >= IS_STRING_ES_OP0) |
29b0f896 | 5420 | { |
51c8edf6 | 5421 | gas_assert (i.mem_operands); |
29b0f896 | 5422 | if (!check_string ()) |
5dd0794d | 5423 | return; |
fc0763e6 | 5424 | i.disp_operands = 0; |
29b0f896 | 5425 | } |
5dd0794d | 5426 | |
9373f275 L |
5427 | /* The memory operand of (%dx) should be only used with input/output |
5428 | instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */ | |
5429 | if (i.input_output_operand | |
5430 | && ((i.tm.base_opcode | 0x82) != 0xee | |
ddb62495 | 5431 | || i.tm.opcode_space != SPACE_BASE)) |
9373f275 L |
5432 | { |
5433 | as_bad (_("input/output port address isn't allowed with `%s'"), | |
76d3f746 | 5434 | insn_name (&i.tm)); |
9373f275 L |
5435 | return; |
5436 | } | |
5437 | ||
b6f8c7c4 L |
5438 | if (optimize && !i.no_optimize && i.tm.opcode_modifier.optimize) |
5439 | optimize_encoding (); | |
5440 | ||
c8480b58 L |
5441 | if (use_unaligned_vector_move) |
5442 | encode_with_unaligned_vector_move (); | |
5443 | ||
29b0f896 AM |
5444 | if (!process_suffix ()) |
5445 | return; | |
e413e4e9 | 5446 | |
ef07be45 | 5447 | /* Check if IP-relative addressing requirements can be satisfied. */ |
734dfd1c | 5448 | if (is_cpu (&i.tm, CpuPREFETCHI) |
ef07be45 | 5449 | && !(i.base_reg && i.base_reg->reg_num == RegIP)) |
76d3f746 | 5450 | as_warn (_("'%s' only supports RIP-relative address"), insn_name (&i.tm)); |
ef07be45 | 5451 | |
921eafea | 5452 | /* Update operand types and check extended states. */ |
bc0844ae | 5453 | for (j = 0; j < i.operands; j++) |
921eafea L |
5454 | { |
5455 | i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]); | |
3d70986f | 5456 | switch (i.tm.operand_types[j].bitfield.class) |
921eafea L |
5457 | { |
5458 | default: | |
5459 | break; | |
5460 | case RegMMX: | |
5461 | i.xstate |= xstate_mmx; | |
5462 | break; | |
5463 | case RegMask: | |
32930e4e | 5464 | i.xstate |= xstate_mask; |
921eafea L |
5465 | break; |
5466 | case RegSIMD: | |
3d70986f | 5467 | if (i.tm.operand_types[j].bitfield.tmmword) |
921eafea | 5468 | i.xstate |= xstate_tmm; |
4fc85f37 JB |
5469 | else if (i.tm.operand_types[j].bitfield.zmmword |
5470 | && vector_size >= VSZ512) | |
921eafea | 5471 | i.xstate |= xstate_zmm; |
4fc85f37 JB |
5472 | else if (i.tm.operand_types[j].bitfield.ymmword |
5473 | && vector_size >= VSZ256) | |
921eafea | 5474 | i.xstate |= xstate_ymm; |
3d70986f | 5475 | else if (i.tm.operand_types[j].bitfield.xmmword) |
921eafea L |
5476 | i.xstate |= xstate_xmm; |
5477 | break; | |
5478 | } | |
5479 | } | |
bc0844ae | 5480 | |
29b0f896 AM |
5481 | /* Make still unresolved immediate matches conform to size of immediate |
5482 | given in i.suffix. */ | |
5483 | if (!finalize_imm ()) | |
5484 | return; | |
252b5132 | 5485 | |
40fb9820 | 5486 | if (i.types[0].bitfield.imm1) |
29b0f896 | 5487 | i.imm_operands = 0; /* kludge for shift insns. */ |
252b5132 | 5488 | |
29b0f896 AM |
5489 | /* For insns with operands there are more diddles to do to the opcode. */ |
5490 | if (i.operands) | |
5491 | { | |
5492 | if (!process_operands ()) | |
5493 | return; | |
5494 | } | |
255571cd | 5495 | else if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) |
29b0f896 AM |
5496 | { |
5497 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ | |
76d3f746 | 5498 | as_warn (_("translating to `%sp'"), insn_name (&i.tm)); |
29b0f896 | 5499 | } |
252b5132 | 5500 | |
7a8655d2 | 5501 | if (is_any_vex_encoding (&i.tm)) |
9e5e5283 | 5502 | { |
c1dc7af5 | 5503 | if (!cpu_arch_flags.bitfield.cpui286) |
9e5e5283 | 5504 | { |
c1dc7af5 | 5505 | as_bad (_("instruction `%s' isn't supported outside of protected mode."), |
76d3f746 | 5506 | insn_name (&i.tm)); |
9e5e5283 L |
5507 | return; |
5508 | } | |
c0f3af97 | 5509 | |
0b9404fd JB |
5510 | /* Check for explicit REX prefix. */ |
5511 | if (i.prefix[REX_PREFIX] || i.rex_encoding) | |
5512 | { | |
76d3f746 | 5513 | as_bad (_("REX prefix invalid with `%s'"), insn_name (&i.tm)); |
0b9404fd JB |
5514 | return; |
5515 | } | |
5516 | ||
9e5e5283 L |
5517 | if (i.tm.opcode_modifier.vex) |
5518 | build_vex_prefix (t); | |
5519 | else | |
5520 | build_evex_prefix (); | |
0b9404fd JB |
5521 | |
5522 | /* The individual REX.RXBW bits got consumed. */ | |
5523 | i.rex &= REX_OPCODE; | |
9e5e5283 | 5524 | } |
43234a1e | 5525 | |
7fc69528 JB |
5526 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
5527 | if (i.tm.mnem_off == MN_int | |
a6461c02 | 5528 | && i.op[0].imms->X_add_number == 3) |
29b0f896 AM |
5529 | { |
5530 | i.tm.base_opcode = INT3_OPCODE; | |
5531 | i.imm_operands = 0; | |
5532 | } | |
252b5132 | 5533 | |
0cfa3eb3 JB |
5534 | if ((i.tm.opcode_modifier.jump == JUMP |
5535 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
5536 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 AM |
5537 | && i.op[0].disps->X_op == O_constant) |
5538 | { | |
5539 | /* Convert "jmp constant" (and "call constant") to a jump (call) to | |
5540 | the absolute address given by the constant. Since ix86 jumps and | |
5541 | calls are pc relative, we need to generate a reloc. */ | |
5542 | i.op[0].disps->X_add_symbol = &abs_symbol; | |
5543 | i.op[0].disps->X_op = O_symbol; | |
5544 | } | |
252b5132 | 5545 | |
29b0f896 AM |
5546 | /* For 8 bit registers we need an empty rex prefix. Also if the |
5547 | instruction already has a prefix, we need to convert old | |
5548 | registers to new ones. */ | |
773f551c | 5549 | |
bab6aec1 | 5550 | if ((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte |
29b0f896 | 5551 | && (i.op[0].regs->reg_flags & RegRex64) != 0) |
bab6aec1 | 5552 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte |
29b0f896 | 5553 | && (i.op[1].regs->reg_flags & RegRex64) != 0) |
bab6aec1 JB |
5554 | || (((i.types[0].bitfield.class == Reg && i.types[0].bitfield.byte) |
5555 | || (i.types[1].bitfield.class == Reg && i.types[1].bitfield.byte)) | |
29b0f896 AM |
5556 | && i.rex != 0)) |
5557 | { | |
5558 | int x; | |
726c5dcd | 5559 | |
29b0f896 AM |
5560 | i.rex |= REX_OPCODE; |
5561 | for (x = 0; x < 2; x++) | |
5562 | { | |
5563 | /* Look for 8 bit operand that uses old registers. */ | |
bab6aec1 | 5564 | if (i.types[x].bitfield.class == Reg && i.types[x].bitfield.byte |
29b0f896 | 5565 | && (i.op[x].regs->reg_flags & RegRex64) == 0) |
773f551c | 5566 | { |
3f93af61 | 5567 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
29b0f896 AM |
5568 | /* In case it is "hi" register, give up. */ |
5569 | if (i.op[x].regs->reg_num > 3) | |
a540244d | 5570 | as_bad (_("can't encode register '%s%s' in an " |
4eed87de | 5571 | "instruction requiring REX prefix."), |
a540244d | 5572 | register_prefix, i.op[x].regs->reg_name); |
773f551c | 5573 | |
29b0f896 AM |
5574 | /* Otherwise it is equivalent to the extended register. |
5575 | Since the encoding doesn't change this is merely | |
5576 | cosmetic cleanup for debug output. */ | |
5577 | ||
5578 | i.op[x].regs = i.op[x].regs + 8; | |
773f551c | 5579 | } |
29b0f896 AM |
5580 | } |
5581 | } | |
773f551c | 5582 | |
6b6b6807 L |
5583 | if (i.rex == 0 && i.rex_encoding) |
5584 | { | |
5585 | /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand | |
3f93af61 | 5586 | that uses legacy register. If it is "hi" register, don't add |
6b6b6807 L |
5587 | the REX_OPCODE byte. */ |
5588 | int x; | |
5589 | for (x = 0; x < 2; x++) | |
bab6aec1 | 5590 | if (i.types[x].bitfield.class == Reg |
6b6b6807 L |
5591 | && i.types[x].bitfield.byte |
5592 | && (i.op[x].regs->reg_flags & RegRex64) == 0 | |
5593 | && i.op[x].regs->reg_num > 3) | |
5594 | { | |
3f93af61 | 5595 | gas_assert (!(i.op[x].regs->reg_flags & RegRex)); |
5b7c81bd | 5596 | i.rex_encoding = false; |
6b6b6807 L |
5597 | break; |
5598 | } | |
5599 | ||
5600 | if (i.rex_encoding) | |
5601 | i.rex = REX_OPCODE; | |
5602 | } | |
5603 | ||
7ab9ffdd | 5604 | if (i.rex != 0) |
29b0f896 AM |
5605 | add_prefix (REX_OPCODE | i.rex); |
5606 | ||
ae531041 L |
5607 | insert_lfence_before (); |
5608 | ||
29b0f896 AM |
5609 | /* We are ready to output the insn. */ |
5610 | output_insn (); | |
e379e5f3 | 5611 | |
ae531041 L |
5612 | insert_lfence_after (); |
5613 | ||
e379e5f3 L |
5614 | last_insn.seg = now_seg; |
5615 | ||
5616 | if (i.tm.opcode_modifier.isprefix) | |
5617 | { | |
5618 | last_insn.kind = last_insn_prefix; | |
76d3f746 | 5619 | last_insn.name = insn_name (&i.tm); |
e379e5f3 L |
5620 | last_insn.file = as_where (&last_insn.line); |
5621 | } | |
5622 | else | |
5623 | last_insn.kind = last_insn_other; | |
29b0f896 AM |
5624 | } |
5625 | ||
9db83a32 JB |
5626 | /* The Q suffix is generally valid only in 64-bit mode, with very few |
5627 | exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild | |
5628 | and fisttp only one of their two templates is matched below: That's | |
5629 | sufficient since other relevant attributes are the same between both | |
5630 | respective templates. */ | |
5631 | static INLINE bool q_suffix_allowed(const insn_template *t) | |
5632 | { | |
5633 | return flag_code == CODE_64BIT | |
ddb62495 | 5634 | || (t->opcode_space == SPACE_BASE |
9db83a32 JB |
5635 | && t->base_opcode == 0xdf |
5636 | && (t->extension_opcode & 1)) /* fild / fistp / fisttp */ | |
7fc69528 | 5637 | || t->mnem_off == MN_cmpxchg8b; |
9db83a32 JB |
5638 | } |
5639 | ||
5317ad2c | 5640 | static const char * |
edd67638 | 5641 | parse_insn (const char *line, char *mnemonic, bool prefix_only) |
29b0f896 | 5642 | { |
5317ad2c | 5643 | const char *l = line, *token_start = l; |
29b0f896 | 5644 | char *mnem_p; |
04784e33 | 5645 | bool pass1 = !current_templates; |
5c6af06e | 5646 | int supported; |
d3ce72d0 | 5647 | const insn_template *t; |
b6169b20 | 5648 | char *dot_p = NULL; |
29b0f896 | 5649 | |
29b0f896 AM |
5650 | while (1) |
5651 | { | |
5652 | mnem_p = mnemonic; | |
778415f5 JB |
5653 | /* Pseudo-prefixes start with an opening figure brace. */ |
5654 | if ((*mnem_p = *l) == '{') | |
5655 | { | |
5656 | ++mnem_p; | |
5657 | ++l; | |
5658 | } | |
29b0f896 AM |
5659 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
5660 | { | |
b6169b20 L |
5661 | if (*mnem_p == '.') |
5662 | dot_p = mnem_p; | |
29b0f896 AM |
5663 | mnem_p++; |
5664 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
45288df1 | 5665 | { |
778415f5 | 5666 | too_long: |
29b0f896 AM |
5667 | as_bad (_("no such instruction: `%s'"), token_start); |
5668 | return NULL; | |
5669 | } | |
5670 | l++; | |
5671 | } | |
778415f5 JB |
5672 | /* Pseudo-prefixes end with a closing figure brace. */ |
5673 | if (*mnemonic == '{' && *l == '}') | |
5674 | { | |
5675 | *mnem_p++ = *l++; | |
5676 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE) | |
5677 | goto too_long; | |
5678 | *mnem_p = '\0'; | |
5679 | ||
5680 | /* Point l at the closing brace if there's no other separator. */ | |
5681 | if (*l != END_OF_INSN && !is_space_char (*l) | |
5682 | && *l != PREFIX_SEPARATOR) | |
5683 | --l; | |
5684 | } | |
5685 | else if (!is_space_char (*l) | |
5686 | && *l != END_OF_INSN | |
5687 | && (intel_syntax | |
5688 | || (*l != PREFIX_SEPARATOR && *l != ','))) | |
29b0f896 | 5689 | { |
edd67638 JB |
5690 | if (prefix_only) |
5691 | break; | |
29b0f896 AM |
5692 | as_bad (_("invalid character %s in mnemonic"), |
5693 | output_invalid (*l)); | |
5694 | return NULL; | |
5695 | } | |
5696 | if (token_start == l) | |
5697 | { | |
e44823cf | 5698 | if (!intel_syntax && *l == PREFIX_SEPARATOR) |
29b0f896 AM |
5699 | as_bad (_("expecting prefix; got nothing")); |
5700 | else | |
5701 | as_bad (_("expecting mnemonic; got nothing")); | |
5702 | return NULL; | |
5703 | } | |
45288df1 | 5704 | |
29b0f896 | 5705 | /* Look up instruction (or prefix) via hash table. */ |
629310ab | 5706 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
47926f60 | 5707 | |
29b0f896 AM |
5708 | if (*l != END_OF_INSN |
5709 | && (!is_space_char (*l) || l[1] != END_OF_INSN) | |
5710 | && current_templates | |
40fb9820 | 5711 | && current_templates->start->opcode_modifier.isprefix) |
29b0f896 | 5712 | { |
c0260ac6 | 5713 | if (!cpu_flags_check_cpu64 (current_templates->start)) |
2dd88dca JB |
5714 | { |
5715 | as_bad ((flag_code != CODE_64BIT | |
5716 | ? _("`%s' is only supported in 64-bit mode") | |
5717 | : _("`%s' is not supported in 64-bit mode")), | |
76d3f746 | 5718 | insn_name (current_templates->start)); |
2dd88dca JB |
5719 | return NULL; |
5720 | } | |
29b0f896 AM |
5721 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
5722 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ | |
673fe0f0 JB |
5723 | if ((current_templates->start->opcode_modifier.size == SIZE16 |
5724 | || current_templates->start->opcode_modifier.size == SIZE32) | |
29b0f896 | 5725 | && flag_code != CODE_64BIT |
673fe0f0 | 5726 | && ((current_templates->start->opcode_modifier.size == SIZE32) |
29b0f896 AM |
5727 | ^ (flag_code == CODE_16BIT))) |
5728 | { | |
5729 | as_bad (_("redundant %s prefix"), | |
76d3f746 | 5730 | insn_name (current_templates->start)); |
29b0f896 | 5731 | return NULL; |
45288df1 | 5732 | } |
31184569 JB |
5733 | |
5734 | if (current_templates->start->base_opcode == PSEUDO_PREFIX) | |
29b0f896 | 5735 | { |
86fa6981 | 5736 | /* Handle pseudo prefixes. */ |
31184569 | 5737 | switch (current_templates->start->extension_opcode) |
86fa6981 | 5738 | { |
41eb8e88 | 5739 | case Prefix_Disp8: |
86fa6981 L |
5740 | /* {disp8} */ |
5741 | i.disp_encoding = disp_encoding_8bit; | |
5742 | break; | |
41eb8e88 L |
5743 | case Prefix_Disp16: |
5744 | /* {disp16} */ | |
5745 | i.disp_encoding = disp_encoding_16bit; | |
5746 | break; | |
5747 | case Prefix_Disp32: | |
86fa6981 L |
5748 | /* {disp32} */ |
5749 | i.disp_encoding = disp_encoding_32bit; | |
5750 | break; | |
41eb8e88 | 5751 | case Prefix_Load: |
86fa6981 L |
5752 | /* {load} */ |
5753 | i.dir_encoding = dir_encoding_load; | |
5754 | break; | |
41eb8e88 | 5755 | case Prefix_Store: |
86fa6981 L |
5756 | /* {store} */ |
5757 | i.dir_encoding = dir_encoding_store; | |
5758 | break; | |
41eb8e88 | 5759 | case Prefix_VEX: |
42e04b36 L |
5760 | /* {vex} */ |
5761 | i.vec_encoding = vex_encoding_vex; | |
86fa6981 | 5762 | break; |
41eb8e88 | 5763 | case Prefix_VEX3: |
86fa6981 L |
5764 | /* {vex3} */ |
5765 | i.vec_encoding = vex_encoding_vex3; | |
5766 | break; | |
41eb8e88 | 5767 | case Prefix_EVEX: |
86fa6981 L |
5768 | /* {evex} */ |
5769 | i.vec_encoding = vex_encoding_evex; | |
5770 | break; | |
41eb8e88 | 5771 | case Prefix_REX: |
6b6b6807 | 5772 | /* {rex} */ |
5b7c81bd | 5773 | i.rex_encoding = true; |
6b6b6807 | 5774 | break; |
41eb8e88 | 5775 | case Prefix_NoOptimize: |
b6f8c7c4 | 5776 | /* {nooptimize} */ |
5b7c81bd | 5777 | i.no_optimize = true; |
b6f8c7c4 | 5778 | break; |
86fa6981 L |
5779 | default: |
5780 | abort (); | |
5781 | } | |
5782 | } | |
5783 | else | |
5784 | { | |
5785 | /* Add prefix, checking for repeated prefixes. */ | |
4e9ac44a | 5786 | switch (add_prefix (current_templates->start->base_opcode)) |
86fa6981 | 5787 | { |
4e9ac44a L |
5788 | case PREFIX_EXIST: |
5789 | return NULL; | |
5790 | case PREFIX_DS: | |
734dfd1c | 5791 | if (is_cpu (current_templates->start, CpuIBT)) |
76d3f746 | 5792 | i.notrack_prefix = insn_name (current_templates->start); |
4e9ac44a L |
5793 | break; |
5794 | case PREFIX_REP: | |
734dfd1c | 5795 | if (is_cpu (current_templates->start, CpuHLE)) |
76d3f746 | 5796 | i.hle_prefix = insn_name (current_templates->start); |
734dfd1c | 5797 | else if (is_cpu (current_templates->start, CpuMPX)) |
76d3f746 | 5798 | i.bnd_prefix = insn_name (current_templates->start); |
4e9ac44a | 5799 | else |
76d3f746 | 5800 | i.rep_prefix = insn_name (current_templates->start); |
4e9ac44a L |
5801 | break; |
5802 | default: | |
5803 | break; | |
86fa6981 | 5804 | } |
29b0f896 AM |
5805 | } |
5806 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ | |
5807 | token_start = ++l; | |
5808 | } | |
5809 | else | |
5810 | break; | |
5811 | } | |
45288df1 | 5812 | |
edd67638 JB |
5813 | if (prefix_only) |
5814 | return token_start; | |
5815 | ||
30a55f88 | 5816 | if (!current_templates) |
b6169b20 | 5817 | { |
07d5e953 JB |
5818 | /* Deprecated functionality (new code should use pseudo-prefixes instead): |
5819 | Check if we should swap operand or force 32bit displacement in | |
f8a5c266 | 5820 | encoding. */ |
30a55f88 | 5821 | if (mnem_p - 2 == dot_p && dot_p[1] == 's') |
64c49ab3 | 5822 | i.dir_encoding = dir_encoding_swap; |
8d63c93e | 5823 | else if (mnem_p - 3 == dot_p |
a501d77e L |
5824 | && dot_p[1] == 'd' |
5825 | && dot_p[2] == '8') | |
5826 | i.disp_encoding = disp_encoding_8bit; | |
8d63c93e | 5827 | else if (mnem_p - 4 == dot_p |
f8a5c266 L |
5828 | && dot_p[1] == 'd' |
5829 | && dot_p[2] == '3' | |
5830 | && dot_p[3] == '2') | |
a501d77e | 5831 | i.disp_encoding = disp_encoding_32bit; |
30a55f88 L |
5832 | else |
5833 | goto check_suffix; | |
5834 | mnem_p = dot_p; | |
5835 | *dot_p = '\0'; | |
629310ab | 5836 | current_templates = (const templates *) str_hash_find (op_hash, mnemonic); |
b6169b20 L |
5837 | } |
5838 | ||
04784e33 | 5839 | if (!current_templates || !pass1) |
29b0f896 | 5840 | { |
04784e33 JB |
5841 | current_templates = NULL; |
5842 | ||
dc1e8a47 | 5843 | check_suffix: |
1c529385 | 5844 | if (mnem_p > mnemonic) |
29b0f896 | 5845 | { |
1c529385 LH |
5846 | /* See if we can get a match by trimming off a suffix. */ |
5847 | switch (mnem_p[-1]) | |
29b0f896 | 5848 | { |
1c529385 LH |
5849 | case WORD_MNEM_SUFFIX: |
5850 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) | |
29b0f896 AM |
5851 | i.suffix = SHORT_MNEM_SUFFIX; |
5852 | else | |
1c529385 LH |
5853 | /* Fall through. */ |
5854 | case BYTE_MNEM_SUFFIX: | |
5855 | case QWORD_MNEM_SUFFIX: | |
5856 | i.suffix = mnem_p[-1]; | |
29b0f896 | 5857 | mnem_p[-1] = '\0'; |
fe0e921f AM |
5858 | current_templates |
5859 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5860 | break; |
5861 | case SHORT_MNEM_SUFFIX: | |
5862 | case LONG_MNEM_SUFFIX: | |
5863 | if (!intel_syntax) | |
5864 | { | |
5865 | i.suffix = mnem_p[-1]; | |
5866 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5867 | current_templates |
5868 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 LH |
5869 | } |
5870 | break; | |
5871 | ||
5872 | /* Intel Syntax. */ | |
5873 | case 'd': | |
5874 | if (intel_syntax) | |
5875 | { | |
5876 | if (intel_float_operand (mnemonic) == 1) | |
5877 | i.suffix = SHORT_MNEM_SUFFIX; | |
5878 | else | |
5879 | i.suffix = LONG_MNEM_SUFFIX; | |
5880 | mnem_p[-1] = '\0'; | |
fe0e921f AM |
5881 | current_templates |
5882 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
1c529385 | 5883 | } |
04784e33 JB |
5884 | /* For compatibility reasons accept MOVSD and CMPSD without |
5885 | operands even in AT&T mode. */ | |
5886 | else if (*l == END_OF_INSN | |
5887 | || (is_space_char (*l) && l[1] == END_OF_INSN)) | |
5888 | { | |
5889 | mnem_p[-1] = '\0'; | |
5890 | current_templates | |
5891 | = (const templates *) str_hash_find (op_hash, mnemonic); | |
5892 | if (current_templates != NULL | |
5893 | /* MOVS or CMPS */ | |
5894 | && (current_templates->start->base_opcode | 2) == 0xa6 | |
ddb62495 | 5895 | && current_templates->start->opcode_space |
04784e33 JB |
5896 | == SPACE_BASE |
5897 | && mnem_p[-2] == 's') | |
5898 | { | |
5899 | as_warn (_("found `%sd'; assuming `%sl' was meant"), | |
5900 | mnemonic, mnemonic); | |
5901 | i.suffix = LONG_MNEM_SUFFIX; | |
5902 | } | |
5903 | else | |
5904 | { | |
5905 | current_templates = NULL; | |
5906 | mnem_p[-1] = 'd'; | |
5907 | } | |
5908 | } | |
1c529385 | 5909 | break; |
29b0f896 | 5910 | } |
29b0f896 | 5911 | } |
1c529385 | 5912 | |
29b0f896 AM |
5913 | if (!current_templates) |
5914 | { | |
04784e33 JB |
5915 | if (pass1) |
5916 | as_bad (_("no such instruction: `%s'"), token_start); | |
29b0f896 AM |
5917 | return NULL; |
5918 | } | |
5919 | } | |
252b5132 | 5920 | |
0cfa3eb3 JB |
5921 | if (current_templates->start->opcode_modifier.jump == JUMP |
5922 | || current_templates->start->opcode_modifier.jump == JUMP_BYTE) | |
29b0f896 AM |
5923 | { |
5924 | /* Check for a branch hint. We allow ",pt" and ",pn" for | |
5925 | predict taken and predict not taken respectively. | |
5926 | I'm not sure that branch hints actually do anything on loop | |
5927 | and jcxz insns (JumpByte) for current Pentium4 chips. They | |
5928 | may work in the future and it doesn't hurt to accept them | |
5929 | now. */ | |
5930 | if (l[0] == ',' && l[1] == 'p') | |
5931 | { | |
5932 | if (l[2] == 't') | |
5933 | { | |
5934 | if (!add_prefix (DS_PREFIX_OPCODE)) | |
5935 | return NULL; | |
5936 | l += 3; | |
5937 | } | |
5938 | else if (l[2] == 'n') | |
5939 | { | |
5940 | if (!add_prefix (CS_PREFIX_OPCODE)) | |
5941 | return NULL; | |
5942 | l += 3; | |
5943 | } | |
5944 | } | |
5945 | } | |
5946 | /* Any other comma loses. */ | |
5947 | if (*l == ',') | |
5948 | { | |
5949 | as_bad (_("invalid character %s in mnemonic"), | |
5950 | output_invalid (*l)); | |
5951 | return NULL; | |
5952 | } | |
252b5132 | 5953 | |
29b0f896 | 5954 | /* Check if instruction is supported on specified architecture. */ |
5c6af06e JB |
5955 | supported = 0; |
5956 | for (t = current_templates->start; t < current_templates->end; ++t) | |
5957 | { | |
c0f3af97 | 5958 | supported |= cpu_flags_match (t); |
9db83a32 JB |
5959 | |
5960 | if (i.suffix == QWORD_MNEM_SUFFIX && !q_suffix_allowed (t)) | |
5961 | supported &= ~CPU_FLAGS_64BIT_MATCH; | |
5962 | ||
c0f3af97 | 5963 | if (supported == CPU_FLAGS_PERFECT_MATCH) |
d59a54c2 | 5964 | return l; |
29b0f896 | 5965 | } |
3629bb00 | 5966 | |
9db83a32 JB |
5967 | if (pass1) |
5968 | { | |
5969 | if (supported & CPU_FLAGS_64BIT_MATCH) | |
5970 | i.error = unsupported_on_arch; | |
5971 | else | |
5972 | i.error = unsupported_64bit; | |
5973 | } | |
252b5132 | 5974 | |
548d0ee6 | 5975 | return NULL; |
29b0f896 | 5976 | } |
252b5132 | 5977 | |
29b0f896 | 5978 | static char * |
e3bb37b5 | 5979 | parse_operands (char *l, const char *mnemonic) |
29b0f896 AM |
5980 | { |
5981 | char *token_start; | |
3138f287 | 5982 | |
29b0f896 AM |
5983 | /* 1 if operand is pending after ','. */ |
5984 | unsigned int expecting_operand = 0; | |
252b5132 | 5985 | |
29b0f896 AM |
5986 | while (*l != END_OF_INSN) |
5987 | { | |
e68c3d59 JB |
5988 | /* Non-zero if operand parens not balanced. */ |
5989 | unsigned int paren_not_balanced = 0; | |
5990 | /* True if inside double quotes. */ | |
5991 | bool in_quotes = false; | |
5992 | ||
29b0f896 AM |
5993 | /* Skip optional white space before operand. */ |
5994 | if (is_space_char (*l)) | |
5995 | ++l; | |
d02603dc | 5996 | if (!is_operand_char (*l) && *l != END_OF_INSN && *l != '"') |
29b0f896 AM |
5997 | { |
5998 | as_bad (_("invalid character %s before operand %d"), | |
5999 | output_invalid (*l), | |
6000 | i.operands + 1); | |
6001 | return NULL; | |
6002 | } | |
d02603dc | 6003 | token_start = l; /* After white space. */ |
e68c3d59 | 6004 | while (in_quotes || paren_not_balanced || *l != ',') |
29b0f896 AM |
6005 | { |
6006 | if (*l == END_OF_INSN) | |
6007 | { | |
e68c3d59 JB |
6008 | if (in_quotes) |
6009 | { | |
6010 | as_bad (_("unbalanced double quotes in operand %d."), | |
6011 | i.operands + 1); | |
6012 | return NULL; | |
6013 | } | |
29b0f896 AM |
6014 | if (paren_not_balanced) |
6015 | { | |
98ff9f1c JB |
6016 | know (!intel_syntax); |
6017 | as_bad (_("unbalanced parenthesis in operand %d."), | |
6018 | i.operands + 1); | |
29b0f896 AM |
6019 | return NULL; |
6020 | } | |
6021 | else | |
6022 | break; /* we are done */ | |
6023 | } | |
e68c3d59 JB |
6024 | else if (*l == '\\' && l[1] == '"') |
6025 | ++l; | |
6026 | else if (*l == '"') | |
6027 | in_quotes = !in_quotes; | |
6028 | else if (!in_quotes && !is_operand_char (*l) && !is_space_char (*l)) | |
29b0f896 AM |
6029 | { |
6030 | as_bad (_("invalid character %s in operand %d"), | |
6031 | output_invalid (*l), | |
6032 | i.operands + 1); | |
6033 | return NULL; | |
6034 | } | |
e68c3d59 | 6035 | if (!intel_syntax && !in_quotes) |
29b0f896 AM |
6036 | { |
6037 | if (*l == '(') | |
6038 | ++paren_not_balanced; | |
6039 | if (*l == ')') | |
6040 | --paren_not_balanced; | |
6041 | } | |
29b0f896 AM |
6042 | l++; |
6043 | } | |
6044 | if (l != token_start) | |
6045 | { /* Yes, we've read in another operand. */ | |
6046 | unsigned int operand_ok; | |
6047 | this_operand = i.operands++; | |
6048 | if (i.operands > MAX_OPERANDS) | |
6049 | { | |
6050 | as_bad (_("spurious operands; (%d operands/instruction max)"), | |
6051 | MAX_OPERANDS); | |
6052 | return NULL; | |
6053 | } | |
9d46ce34 | 6054 | i.types[this_operand].bitfield.unspecified = 1; |
29b0f896 AM |
6055 | /* Now parse operand adding info to 'i' as we go along. */ |
6056 | END_STRING_AND_SAVE (l); | |
6057 | ||
1286ab78 L |
6058 | if (i.mem_operands > 1) |
6059 | { | |
6060 | as_bad (_("too many memory references for `%s'"), | |
6061 | mnemonic); | |
6062 | return 0; | |
6063 | } | |
6064 | ||
29b0f896 AM |
6065 | if (intel_syntax) |
6066 | operand_ok = | |
6067 | i386_intel_operand (token_start, | |
6068 | intel_float_operand (mnemonic)); | |
6069 | else | |
a7619375 | 6070 | operand_ok = i386_att_operand (token_start); |
29b0f896 AM |
6071 | |
6072 | RESTORE_END_STRING (l); | |
6073 | if (!operand_ok) | |
6074 | return NULL; | |
6075 | } | |
6076 | else | |
6077 | { | |
6078 | if (expecting_operand) | |
6079 | { | |
6080 | expecting_operand_after_comma: | |
6081 | as_bad (_("expecting operand after ','; got nothing")); | |
6082 | return NULL; | |
6083 | } | |
6084 | if (*l == ',') | |
6085 | { | |
6086 | as_bad (_("expecting operand before ','; got nothing")); | |
6087 | return NULL; | |
6088 | } | |
6089 | } | |
7f3f1ea2 | 6090 | |
29b0f896 AM |
6091 | /* Now *l must be either ',' or END_OF_INSN. */ |
6092 | if (*l == ',') | |
6093 | { | |
6094 | if (*++l == END_OF_INSN) | |
6095 | { | |
6096 | /* Just skip it, if it's \n complain. */ | |
6097 | goto expecting_operand_after_comma; | |
6098 | } | |
6099 | expecting_operand = 1; | |
6100 | } | |
6101 | } | |
6102 | return l; | |
6103 | } | |
7f3f1ea2 | 6104 | |
050dfa73 | 6105 | static void |
783c187b | 6106 | swap_2_operands (unsigned int xchg1, unsigned int xchg2) |
050dfa73 MM |
6107 | { |
6108 | union i386_op temp_op; | |
40fb9820 | 6109 | i386_operand_type temp_type; |
c48dadc9 | 6110 | unsigned int temp_flags; |
050dfa73 | 6111 | enum bfd_reloc_code_real temp_reloc; |
4eed87de | 6112 | |
050dfa73 MM |
6113 | temp_type = i.types[xchg2]; |
6114 | i.types[xchg2] = i.types[xchg1]; | |
6115 | i.types[xchg1] = temp_type; | |
c48dadc9 JB |
6116 | |
6117 | temp_flags = i.flags[xchg2]; | |
6118 | i.flags[xchg2] = i.flags[xchg1]; | |
6119 | i.flags[xchg1] = temp_flags; | |
6120 | ||
050dfa73 MM |
6121 | temp_op = i.op[xchg2]; |
6122 | i.op[xchg2] = i.op[xchg1]; | |
6123 | i.op[xchg1] = temp_op; | |
c48dadc9 | 6124 | |
050dfa73 MM |
6125 | temp_reloc = i.reloc[xchg2]; |
6126 | i.reloc[xchg2] = i.reloc[xchg1]; | |
6127 | i.reloc[xchg1] = temp_reloc; | |
43234a1e | 6128 | |
c032bc4f JB |
6129 | temp_flags = i.imm_bits[xchg2]; |
6130 | i.imm_bits[xchg2] = i.imm_bits[xchg1]; | |
6131 | i.imm_bits[xchg1] = temp_flags; | |
6132 | ||
6225c532 | 6133 | if (i.mask.reg) |
43234a1e | 6134 | { |
6225c532 JB |
6135 | if (i.mask.operand == xchg1) |
6136 | i.mask.operand = xchg2; | |
6137 | else if (i.mask.operand == xchg2) | |
6138 | i.mask.operand = xchg1; | |
43234a1e | 6139 | } |
a5748e0d | 6140 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 6141 | { |
5273a3cd JB |
6142 | if (i.broadcast.operand == xchg1) |
6143 | i.broadcast.operand = xchg2; | |
6144 | else if (i.broadcast.operand == xchg2) | |
6145 | i.broadcast.operand = xchg1; | |
43234a1e | 6146 | } |
050dfa73 MM |
6147 | } |
6148 | ||
29b0f896 | 6149 | static void |
e3bb37b5 | 6150 | swap_operands (void) |
29b0f896 | 6151 | { |
b7c61d9a | 6152 | switch (i.operands) |
050dfa73 | 6153 | { |
c0f3af97 | 6154 | case 5: |
b7c61d9a | 6155 | case 4: |
4d456e3d | 6156 | swap_2_operands (1, i.operands - 2); |
1a0670f3 | 6157 | /* Fall through. */ |
b7c61d9a L |
6158 | case 3: |
6159 | case 2: | |
4d456e3d | 6160 | swap_2_operands (0, i.operands - 1); |
b7c61d9a L |
6161 | break; |
6162 | default: | |
6163 | abort (); | |
29b0f896 | 6164 | } |
29b0f896 AM |
6165 | |
6166 | if (i.mem_operands == 2) | |
6167 | { | |
5e042380 | 6168 | const reg_entry *temp_seg; |
29b0f896 AM |
6169 | temp_seg = i.seg[0]; |
6170 | i.seg[0] = i.seg[1]; | |
6171 | i.seg[1] = temp_seg; | |
6172 | } | |
6173 | } | |
252b5132 | 6174 | |
29b0f896 AM |
6175 | /* Try to ensure constant immediates are represented in the smallest |
6176 | opcode possible. */ | |
6177 | static void | |
e3bb37b5 | 6178 | optimize_imm (void) |
29b0f896 AM |
6179 | { |
6180 | char guess_suffix = 0; | |
6181 | int op; | |
252b5132 | 6182 | |
29b0f896 AM |
6183 | if (i.suffix) |
6184 | guess_suffix = i.suffix; | |
6185 | else if (i.reg_operands) | |
6186 | { | |
6187 | /* Figure out a suffix from the last register operand specified. | |
75e5731b JB |
6188 | We can't do this properly yet, i.e. excluding special register |
6189 | instances, but the following works for instructions with | |
6190 | immediates. In any case, we can't set i.suffix yet. */ | |
29b0f896 | 6191 | for (op = i.operands; --op >= 0;) |
bab6aec1 JB |
6192 | if (i.types[op].bitfield.class != Reg) |
6193 | continue; | |
6194 | else if (i.types[op].bitfield.byte) | |
7ab9ffdd | 6195 | { |
40fb9820 L |
6196 | guess_suffix = BYTE_MNEM_SUFFIX; |
6197 | break; | |
6198 | } | |
bab6aec1 | 6199 | else if (i.types[op].bitfield.word) |
252b5132 | 6200 | { |
40fb9820 L |
6201 | guess_suffix = WORD_MNEM_SUFFIX; |
6202 | break; | |
6203 | } | |
bab6aec1 | 6204 | else if (i.types[op].bitfield.dword) |
40fb9820 L |
6205 | { |
6206 | guess_suffix = LONG_MNEM_SUFFIX; | |
6207 | break; | |
6208 | } | |
bab6aec1 | 6209 | else if (i.types[op].bitfield.qword) |
40fb9820 L |
6210 | { |
6211 | guess_suffix = QWORD_MNEM_SUFFIX; | |
29b0f896 | 6212 | break; |
252b5132 | 6213 | } |
29b0f896 AM |
6214 | } |
6215 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) | |
6216 | guess_suffix = WORD_MNEM_SUFFIX; | |
5cc00775 JB |
6217 | else if (flag_code != CODE_64BIT || !(i.prefix[REX_PREFIX] & REX_W)) |
6218 | guess_suffix = LONG_MNEM_SUFFIX; | |
29b0f896 AM |
6219 | |
6220 | for (op = i.operands; --op >= 0;) | |
40fb9820 | 6221 | if (operand_type_check (i.types[op], imm)) |
29b0f896 AM |
6222 | { |
6223 | switch (i.op[op].imms->X_op) | |
252b5132 | 6224 | { |
29b0f896 AM |
6225 | case O_constant: |
6226 | /* If a suffix is given, this operand may be shortened. */ | |
6227 | switch (guess_suffix) | |
252b5132 | 6228 | { |
29b0f896 | 6229 | case LONG_MNEM_SUFFIX: |
40fb9820 L |
6230 | i.types[op].bitfield.imm32 = 1; |
6231 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
6232 | break; |
6233 | case WORD_MNEM_SUFFIX: | |
40fb9820 L |
6234 | i.types[op].bitfield.imm16 = 1; |
6235 | i.types[op].bitfield.imm32 = 1; | |
6236 | i.types[op].bitfield.imm32s = 1; | |
6237 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 AM |
6238 | break; |
6239 | case BYTE_MNEM_SUFFIX: | |
40fb9820 L |
6240 | i.types[op].bitfield.imm8 = 1; |
6241 | i.types[op].bitfield.imm8s = 1; | |
6242 | i.types[op].bitfield.imm16 = 1; | |
6243 | i.types[op].bitfield.imm32 = 1; | |
6244 | i.types[op].bitfield.imm32s = 1; | |
6245 | i.types[op].bitfield.imm64 = 1; | |
29b0f896 | 6246 | break; |
252b5132 | 6247 | } |
252b5132 | 6248 | |
29b0f896 AM |
6249 | /* If this operand is at most 16 bits, convert it |
6250 | to a signed 16 bit number before trying to see | |
6251 | whether it will fit in an even smaller size. | |
6252 | This allows a 16-bit operand such as $0xffe0 to | |
6253 | be recognised as within Imm8S range. */ | |
40fb9820 | 6254 | if ((i.types[op].bitfield.imm16) |
7e96fb68 | 6255 | && fits_in_unsigned_word (i.op[op].imms->X_add_number)) |
252b5132 | 6256 | { |
87ed972d JB |
6257 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
6258 | ^ 0x8000) - 0x8000); | |
29b0f896 | 6259 | } |
a28def75 L |
6260 | #ifdef BFD64 |
6261 | /* Store 32-bit immediate in 64-bit for 64-bit BFD. */ | |
40fb9820 | 6262 | if ((i.types[op].bitfield.imm32) |
7e96fb68 | 6263 | && fits_in_unsigned_long (i.op[op].imms->X_add_number)) |
29b0f896 AM |
6264 | { |
6265 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number | |
6266 | ^ ((offsetT) 1 << 31)) | |
6267 | - ((offsetT) 1 << 31)); | |
6268 | } | |
a28def75 | 6269 | #endif |
40fb9820 | 6270 | i.types[op] |
c6fb90c8 L |
6271 | = operand_type_or (i.types[op], |
6272 | smallest_imm_type (i.op[op].imms->X_add_number)); | |
252b5132 | 6273 | |
29b0f896 AM |
6274 | /* We must avoid matching of Imm32 templates when 64bit |
6275 | only immediate is available. */ | |
6276 | if (guess_suffix == QWORD_MNEM_SUFFIX) | |
40fb9820 | 6277 | i.types[op].bitfield.imm32 = 0; |
29b0f896 | 6278 | break; |
252b5132 | 6279 | |
29b0f896 AM |
6280 | case O_absent: |
6281 | case O_register: | |
6282 | abort (); | |
6283 | ||
6284 | /* Symbols and expressions. */ | |
6285 | default: | |
9cd96992 JB |
6286 | /* Convert symbolic operand to proper sizes for matching, but don't |
6287 | prevent matching a set of insns that only supports sizes other | |
6288 | than those matching the insn suffix. */ | |
6289 | { | |
40fb9820 | 6290 | i386_operand_type mask, allowed; |
87ed972d | 6291 | const insn_template *t = current_templates->start; |
9cd96992 | 6292 | |
0dfbf9d7 | 6293 | operand_type_set (&mask, 0); |
9cd96992 JB |
6294 | switch (guess_suffix) |
6295 | { | |
6296 | case QWORD_MNEM_SUFFIX: | |
40fb9820 L |
6297 | mask.bitfield.imm64 = 1; |
6298 | mask.bitfield.imm32s = 1; | |
9cd96992 JB |
6299 | break; |
6300 | case LONG_MNEM_SUFFIX: | |
40fb9820 | 6301 | mask.bitfield.imm32 = 1; |
9cd96992 JB |
6302 | break; |
6303 | case WORD_MNEM_SUFFIX: | |
40fb9820 | 6304 | mask.bitfield.imm16 = 1; |
9cd96992 JB |
6305 | break; |
6306 | case BYTE_MNEM_SUFFIX: | |
40fb9820 | 6307 | mask.bitfield.imm8 = 1; |
9cd96992 JB |
6308 | break; |
6309 | default: | |
9cd96992 JB |
6310 | break; |
6311 | } | |
8f0212ac JB |
6312 | |
6313 | allowed = operand_type_and (t->operand_types[op], mask); | |
6314 | while (++t < current_templates->end) | |
6315 | { | |
6316 | allowed = operand_type_or (allowed, t->operand_types[op]); | |
6317 | allowed = operand_type_and (allowed, mask); | |
6318 | } | |
6319 | ||
0dfbf9d7 | 6320 | if (!operand_type_all_zero (&allowed)) |
c6fb90c8 | 6321 | i.types[op] = operand_type_and (i.types[op], mask); |
9cd96992 | 6322 | } |
29b0f896 | 6323 | break; |
252b5132 | 6324 | } |
29b0f896 AM |
6325 | } |
6326 | } | |
47926f60 | 6327 | |
29b0f896 | 6328 | /* Try to use the smallest displacement type too. */ |
0de704b9 JB |
6329 | static bool |
6330 | optimize_disp (const insn_template *t) | |
29b0f896 | 6331 | { |
0de704b9 | 6332 | unsigned int op; |
3e73aa7c | 6333 | |
0de704b9 JB |
6334 | if (!want_disp32 (t) |
6335 | && (!t->opcode_modifier.jump | |
6336 | || i.jumpabsolute || i.types[0].bitfield.baseindex)) | |
6337 | { | |
6338 | for (op = 0; op < i.operands; ++op) | |
6339 | { | |
6340 | const expressionS *exp = i.op[op].disps; | |
6341 | ||
6342 | if (!operand_type_check (i.types[op], disp)) | |
6343 | continue; | |
6344 | ||
6345 | if (exp->X_op != O_constant) | |
6346 | continue; | |
6347 | ||
6348 | /* Since displacement is signed extended to 64bit, don't allow | |
6349 | disp32 if it is out of range. */ | |
6350 | if (fits_in_signed_long (exp->X_add_number)) | |
6351 | continue; | |
6352 | ||
6353 | i.types[op].bitfield.disp32 = 0; | |
6354 | if (i.types[op].bitfield.baseindex) | |
6355 | { | |
6356 | as_bad (_("0x%" PRIx64 " out of range of signed 32bit displacement"), | |
6357 | (uint64_t) exp->X_add_number); | |
6358 | return false; | |
6359 | } | |
6360 | } | |
6361 | } | |
6362 | ||
6363 | /* Don't optimize displacement for movabs since it only takes 64bit | |
6364 | displacement. */ | |
6365 | if (i.disp_encoding > disp_encoding_8bit | |
6366 | || (flag_code == CODE_64BIT && t->mnem_off == MN_movabs)) | |
6367 | return true; | |
6368 | ||
6369 | for (op = i.operands; op-- > 0;) | |
40fb9820 | 6370 | if (operand_type_check (i.types[op], disp)) |
252b5132 | 6371 | { |
b300c311 | 6372 | if (i.op[op].disps->X_op == O_constant) |
252b5132 | 6373 | { |
91d6fa6a | 6374 | offsetT op_disp = i.op[op].disps->X_add_number; |
29b0f896 | 6375 | |
91d6fa6a | 6376 | if (!op_disp && i.types[op].bitfield.baseindex) |
b300c311 | 6377 | { |
2f2be86b JB |
6378 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
6379 | i.op[op].disps = NULL; | |
b300c311 | 6380 | i.disp_operands--; |
f185acdd JB |
6381 | continue; |
6382 | } | |
6383 | ||
6384 | if (i.types[op].bitfield.disp16 | |
cd613c1f | 6385 | && fits_in_unsigned_word (op_disp)) |
f185acdd JB |
6386 | { |
6387 | /* If this operand is at most 16 bits, convert | |
6388 | to a signed 16 bit number and don't use 64bit | |
6389 | displacement. */ | |
6390 | op_disp = ((op_disp ^ 0x8000) - 0x8000); | |
6391 | i.types[op].bitfield.disp64 = 0; | |
b300c311 | 6392 | } |
f185acdd | 6393 | |
28a167a4 | 6394 | #ifdef BFD64 |
a50187b2 | 6395 | /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */ |
a775efc8 JB |
6396 | if ((flag_code != CODE_64BIT |
6397 | ? i.types[op].bitfield.disp32 | |
0de704b9 JB |
6398 | : want_disp32 (t) |
6399 | && (!t->opcode_modifier.jump | |
a775efc8 | 6400 | || i.jumpabsolute || i.types[op].bitfield.baseindex)) |
a50187b2 | 6401 | && fits_in_unsigned_long (op_disp)) |
b300c311 | 6402 | { |
a50187b2 JB |
6403 | /* If this operand is at most 32 bits, convert |
6404 | to a signed 32 bit number and don't use 64bit | |
6405 | displacement. */ | |
6406 | op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); | |
6407 | i.types[op].bitfield.disp64 = 0; | |
6408 | i.types[op].bitfield.disp32 = 1; | |
6409 | } | |
28a167a4 | 6410 | |
a50187b2 JB |
6411 | if (flag_code == CODE_64BIT && fits_in_signed_long (op_disp)) |
6412 | { | |
6413 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 6414 | i.types[op].bitfield.disp32 = 1; |
b300c311 | 6415 | } |
28a167a4 | 6416 | #endif |
40fb9820 | 6417 | if ((i.types[op].bitfield.disp32 |
40fb9820 | 6418 | || i.types[op].bitfield.disp16) |
b5014f7a | 6419 | && fits_in_disp8 (op_disp)) |
40fb9820 | 6420 | i.types[op].bitfield.disp8 = 1; |
77c59789 JB |
6421 | |
6422 | i.op[op].disps->X_add_number = op_disp; | |
252b5132 | 6423 | } |
67a4f2b7 AO |
6424 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
6425 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) | |
6426 | { | |
6427 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, | |
6428 | i.op[op].disps, 0, i.reloc[op]); | |
2f2be86b | 6429 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
67a4f2b7 AO |
6430 | } |
6431 | else | |
b300c311 | 6432 | /* We only support 64bit displacement on constants. */ |
40fb9820 | 6433 | i.types[op].bitfield.disp64 = 0; |
252b5132 | 6434 | } |
0de704b9 JB |
6435 | |
6436 | return true; | |
29b0f896 AM |
6437 | } |
6438 | ||
4a1b91ea L |
6439 | /* Return 1 if there is a match in broadcast bytes between operand |
6440 | GIVEN and instruction template T. */ | |
6441 | ||
6442 | static INLINE int | |
6443 | match_broadcast_size (const insn_template *t, unsigned int given) | |
6444 | { | |
6445 | return ((t->opcode_modifier.broadcast == BYTE_BROADCAST | |
6446 | && i.types[given].bitfield.byte) | |
6447 | || (t->opcode_modifier.broadcast == WORD_BROADCAST | |
6448 | && i.types[given].bitfield.word) | |
6449 | || (t->opcode_modifier.broadcast == DWORD_BROADCAST | |
6450 | && i.types[given].bitfield.dword) | |
6451 | || (t->opcode_modifier.broadcast == QWORD_BROADCAST | |
6452 | && i.types[given].bitfield.qword)); | |
6453 | } | |
6454 | ||
6c30d220 L |
6455 | /* Check if operands are valid for the instruction. */ |
6456 | ||
6457 | static int | |
6458 | check_VecOperands (const insn_template *t) | |
6459 | { | |
43234a1e | 6460 | unsigned int op; |
e2195274 | 6461 | i386_cpu_flags cpu; |
e2195274 JB |
6462 | |
6463 | /* Templates allowing for ZMMword as well as YMMword and/or XMMword for | |
6464 | any one operand are implicity requiring AVX512VL support if the actual | |
6465 | operand size is YMMword or XMMword. Since this function runs after | |
a61cb9db L |
6466 | template matching, there's no need to check for YMMword/XMMword in |
6467 | the template. */ | |
734dfd1c | 6468 | cpu = cpu_flags_and (cpu_flags_from_attr (t->cpu), avx512); |
e2195274 | 6469 | if (!cpu_flags_all_zero (&cpu) |
734dfd1c | 6470 | && !is_cpu (t, CpuAVX512VL) |
e2195274 JB |
6471 | && !cpu_arch_flags.bitfield.cpuavx512vl) |
6472 | { | |
6473 | for (op = 0; op < t->operands; ++op) | |
6474 | { | |
6475 | if (t->operand_types[op].bitfield.zmmword | |
6476 | && (i.types[op].bitfield.ymmword | |
6477 | || i.types[op].bitfield.xmmword)) | |
6478 | { | |
6479 | i.error = unsupported; | |
6480 | return 1; | |
6481 | } | |
6482 | } | |
6483 | } | |
43234a1e | 6484 | |
22c36940 JB |
6485 | /* Somewhat similarly, templates specifying both AVX and AVX2 are |
6486 | requiring AVX2 support if the actual operand size is YMMword. */ | |
734dfd1c | 6487 | if (is_cpu (t, CpuAVX) && is_cpu (t, CpuAVX2) |
22c36940 JB |
6488 | && !cpu_arch_flags.bitfield.cpuavx2) |
6489 | { | |
6490 | for (op = 0; op < t->operands; ++op) | |
6491 | { | |
6492 | if (t->operand_types[op].bitfield.xmmword | |
6493 | && i.types[op].bitfield.ymmword) | |
6494 | { | |
6495 | i.error = unsupported; | |
6496 | return 1; | |
6497 | } | |
6498 | } | |
6499 | } | |
6500 | ||
6c30d220 | 6501 | /* Without VSIB byte, we can't have a vector register for index. */ |
63112cd6 | 6502 | if (!t->opcode_modifier.sib |
6c30d220 | 6503 | && i.index_reg |
1b54b8d7 JB |
6504 | && (i.index_reg->reg_type.bitfield.xmmword |
6505 | || i.index_reg->reg_type.bitfield.ymmword | |
6506 | || i.index_reg->reg_type.bitfield.zmmword)) | |
6c30d220 L |
6507 | { |
6508 | i.error = unsupported_vector_index_register; | |
6509 | return 1; | |
6510 | } | |
6511 | ||
ad8ecc81 | 6512 | /* Check if default mask is allowed. */ |
255571cd | 6513 | if (t->opcode_modifier.operandconstraint == NO_DEFAULT_MASK |
6225c532 | 6514 | && (!i.mask.reg || i.mask.reg->reg_num == 0)) |
ad8ecc81 MZ |
6515 | { |
6516 | i.error = no_default_mask; | |
6517 | return 1; | |
6518 | } | |
6519 | ||
7bab8ab5 JB |
6520 | /* For VSIB byte, we need a vector register for index, and all vector |
6521 | registers must be distinct. */ | |
260cd341 | 6522 | if (t->opcode_modifier.sib && t->opcode_modifier.sib != SIBMEM) |
7bab8ab5 JB |
6523 | { |
6524 | if (!i.index_reg | |
63112cd6 | 6525 | || !((t->opcode_modifier.sib == VECSIB128 |
1b54b8d7 | 6526 | && i.index_reg->reg_type.bitfield.xmmword) |
63112cd6 | 6527 | || (t->opcode_modifier.sib == VECSIB256 |
1b54b8d7 | 6528 | && i.index_reg->reg_type.bitfield.ymmword) |
63112cd6 | 6529 | || (t->opcode_modifier.sib == VECSIB512 |
1b54b8d7 | 6530 | && i.index_reg->reg_type.bitfield.zmmword))) |
7bab8ab5 JB |
6531 | { |
6532 | i.error = invalid_vsib_address; | |
6533 | return 1; | |
6534 | } | |
6535 | ||
6225c532 JB |
6536 | gas_assert (i.reg_operands == 2 || i.mask.reg); |
6537 | if (i.reg_operands == 2 && !i.mask.reg) | |
43234a1e | 6538 | { |
3528c362 | 6539 | gas_assert (i.types[0].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6540 | gas_assert (i.types[0].bitfield.xmmword |
6541 | || i.types[0].bitfield.ymmword); | |
3528c362 | 6542 | gas_assert (i.types[2].bitfield.class == RegSIMD); |
1b54b8d7 JB |
6543 | gas_assert (i.types[2].bitfield.xmmword |
6544 | || i.types[2].bitfield.ymmword); | |
43234a1e L |
6545 | if (operand_check == check_none) |
6546 | return 0; | |
6547 | if (register_number (i.op[0].regs) | |
6548 | != register_number (i.index_reg) | |
6549 | && register_number (i.op[2].regs) | |
6550 | != register_number (i.index_reg) | |
6551 | && register_number (i.op[0].regs) | |
6552 | != register_number (i.op[2].regs)) | |
6553 | return 0; | |
6554 | if (operand_check == check_error) | |
6555 | { | |
6556 | i.error = invalid_vector_register_set; | |
6557 | return 1; | |
6558 | } | |
6559 | as_warn (_("mask, index, and destination registers should be distinct")); | |
6560 | } | |
6225c532 | 6561 | else if (i.reg_operands == 1 && i.mask.reg) |
8444f82a | 6562 | { |
3528c362 | 6563 | if (i.types[1].bitfield.class == RegSIMD |
1b54b8d7 JB |
6564 | && (i.types[1].bitfield.xmmword |
6565 | || i.types[1].bitfield.ymmword | |
6566 | || i.types[1].bitfield.zmmword) | |
8444f82a MZ |
6567 | && (register_number (i.op[1].regs) |
6568 | == register_number (i.index_reg))) | |
6569 | { | |
6570 | if (operand_check == check_error) | |
6571 | { | |
6572 | i.error = invalid_vector_register_set; | |
6573 | return 1; | |
6574 | } | |
6575 | if (operand_check != check_none) | |
6576 | as_warn (_("index and destination registers should be distinct")); | |
6577 | } | |
6578 | } | |
43234a1e | 6579 | } |
7bab8ab5 | 6580 | |
fc141319 L |
6581 | /* For AMX instructions with 3 TMM register operands, all operands |
6582 | must be distinct. */ | |
6583 | if (i.reg_operands == 3 | |
6584 | && t->operand_types[0].bitfield.tmmword | |
6585 | && (i.op[0].regs == i.op[1].regs | |
6586 | || i.op[0].regs == i.op[2].regs | |
6587 | || i.op[1].regs == i.op[2].regs)) | |
6588 | { | |
6589 | i.error = invalid_tmm_register_set; | |
6590 | return 1; | |
260cd341 LC |
6591 | } |
6592 | ||
0cc78721 CL |
6593 | /* For some special instructions require that destination must be distinct |
6594 | from source registers. */ | |
255571cd | 6595 | if (t->opcode_modifier.operandconstraint == DISTINCT_DEST) |
0cc78721 CL |
6596 | { |
6597 | unsigned int dest_reg = i.operands - 1; | |
6598 | ||
6599 | know (i.operands >= 3); | |
6600 | ||
6601 | /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */ | |
6602 | if (i.op[dest_reg - 1].regs == i.op[dest_reg].regs | |
6603 | || (i.reg_operands > 2 | |
6604 | && i.op[dest_reg - 2].regs == i.op[dest_reg].regs)) | |
6605 | { | |
6606 | i.error = invalid_dest_and_src_register_set; | |
6607 | return 1; | |
6608 | } | |
6609 | } | |
6610 | ||
43234a1e L |
6611 | /* Check if broadcast is supported by the instruction and is applied |
6612 | to the memory operand. */ | |
a5748e0d | 6613 | if (i.broadcast.type || i.broadcast.bytes) |
43234a1e | 6614 | { |
8e6e0792 | 6615 | i386_operand_type type, overlap; |
43234a1e L |
6616 | |
6617 | /* Check if specified broadcast is supported in this instruction, | |
4a1b91ea | 6618 | and its broadcast bytes match the memory operand. */ |
5273a3cd | 6619 | op = i.broadcast.operand; |
8e6e0792 | 6620 | if (!t->opcode_modifier.broadcast |
c48dadc9 | 6621 | || !(i.flags[op] & Operand_Mem) |
c39e5b26 | 6622 | || (!i.types[op].bitfield.unspecified |
4a1b91ea | 6623 | && !match_broadcast_size (t, op))) |
43234a1e L |
6624 | { |
6625 | bad_broadcast: | |
6626 | i.error = unsupported_broadcast; | |
6627 | return 1; | |
6628 | } | |
8e6e0792 JB |
6629 | |
6630 | operand_type_set (&type, 0); | |
a5748e0d | 6631 | switch (get_broadcast_bytes (t, false)) |
8e6e0792 | 6632 | { |
4a1b91ea L |
6633 | case 2: |
6634 | type.bitfield.word = 1; | |
6635 | break; | |
6636 | case 4: | |
6637 | type.bitfield.dword = 1; | |
6638 | break; | |
8e6e0792 JB |
6639 | case 8: |
6640 | type.bitfield.qword = 1; | |
6641 | break; | |
6642 | case 16: | |
6643 | type.bitfield.xmmword = 1; | |
6644 | break; | |
6645 | case 32: | |
4fc85f37 JB |
6646 | if (vector_size < VSZ256) |
6647 | goto bad_broadcast; | |
8e6e0792 JB |
6648 | type.bitfield.ymmword = 1; |
6649 | break; | |
6650 | case 64: | |
4fc85f37 JB |
6651 | if (vector_size < VSZ512) |
6652 | goto bad_broadcast; | |
8e6e0792 JB |
6653 | type.bitfield.zmmword = 1; |
6654 | break; | |
6655 | default: | |
6656 | goto bad_broadcast; | |
6657 | } | |
6658 | ||
6659 | overlap = operand_type_and (type, t->operand_types[op]); | |
bc49bfd8 JB |
6660 | if (t->operand_types[op].bitfield.class == RegSIMD |
6661 | && t->operand_types[op].bitfield.byte | |
6662 | + t->operand_types[op].bitfield.word | |
6663 | + t->operand_types[op].bitfield.dword | |
6664 | + t->operand_types[op].bitfield.qword > 1) | |
6665 | { | |
6666 | overlap.bitfield.xmmword = 0; | |
6667 | overlap.bitfield.ymmword = 0; | |
6668 | overlap.bitfield.zmmword = 0; | |
6669 | } | |
8e6e0792 JB |
6670 | if (operand_type_all_zero (&overlap)) |
6671 | goto bad_broadcast; | |
6672 | ||
9c19e9ec | 6673 | if (t->opcode_modifier.checkoperandsize) |
8e6e0792 JB |
6674 | { |
6675 | unsigned int j; | |
6676 | ||
e2195274 | 6677 | type.bitfield.baseindex = 1; |
8e6e0792 JB |
6678 | for (j = 0; j < i.operands; ++j) |
6679 | { | |
6680 | if (j != op | |
6681 | && !operand_type_register_match(i.types[j], | |
6682 | t->operand_types[j], | |
6683 | type, | |
6684 | t->operand_types[op])) | |
6685 | goto bad_broadcast; | |
6686 | } | |
6687 | } | |
43234a1e L |
6688 | } |
6689 | /* If broadcast is supported in this instruction, we need to check if | |
6690 | operand of one-element size isn't specified without broadcast. */ | |
6691 | else if (t->opcode_modifier.broadcast && i.mem_operands) | |
6692 | { | |
6693 | /* Find memory operand. */ | |
6694 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6695 | if (i.flags[op] & Operand_Mem) |
43234a1e L |
6696 | break; |
6697 | gas_assert (op < i.operands); | |
6698 | /* Check size of the memory operand. */ | |
4a1b91ea | 6699 | if (match_broadcast_size (t, op)) |
43234a1e L |
6700 | { |
6701 | i.error = broadcast_needed; | |
6702 | return 1; | |
6703 | } | |
6704 | } | |
c39e5b26 JB |
6705 | else |
6706 | op = MAX_OPERANDS - 1; /* Avoid uninitialized variable warning. */ | |
43234a1e L |
6707 | |
6708 | /* Check if requested masking is supported. */ | |
6225c532 | 6709 | if (i.mask.reg) |
43234a1e | 6710 | { |
b1c79256 | 6711 | if (!t->opcode_modifier.masking) |
ae2387fe | 6712 | { |
b1c79256 JB |
6713 | i.error = unsupported_masking; |
6714 | return 1; | |
6715 | } | |
6716 | ||
6717 | /* Common rules for masking: | |
6718 | - mask register destinations permit only zeroing-masking, without | |
6719 | that actually being expressed by a {z} operand suffix or EVEX.z, | |
6720 | - memory destinations allow only merging-masking, | |
6721 | - scatter/gather insns (i.e. ones using vSIB) only allow merging- | |
6722 | masking. */ | |
6723 | if (i.mask.zeroing | |
6724 | && (t->operand_types[t->operands - 1].bitfield.class == RegMask | |
6725 | || (i.flags[t->operands - 1] & Operand_Mem) | |
6726 | || t->opcode_modifier.sib)) | |
6727 | { | |
6728 | i.error = unsupported_masking; | |
6729 | return 1; | |
ae2387fe | 6730 | } |
43234a1e L |
6731 | } |
6732 | ||
6733 | /* Check if masking is applied to dest operand. */ | |
6225c532 | 6734 | if (i.mask.reg && (i.mask.operand != i.operands - 1)) |
43234a1e L |
6735 | { |
6736 | i.error = mask_not_on_destination; | |
6737 | return 1; | |
6738 | } | |
6739 | ||
43234a1e | 6740 | /* Check RC/SAE. */ |
ca5312a2 | 6741 | if (i.rounding.type != rc_none) |
43234a1e | 6742 | { |
a80195f1 | 6743 | if (!t->opcode_modifier.sae |
cf665fee JB |
6744 | || ((i.rounding.type != saeonly) != t->opcode_modifier.staticrounding) |
6745 | || i.mem_operands) | |
43234a1e L |
6746 | { |
6747 | i.error = unsupported_rc_sae; | |
6748 | return 1; | |
6749 | } | |
cf665fee JB |
6750 | |
6751 | /* Non-EVEX.LIG forms need to have a ZMM register as at least one | |
6752 | operand. */ | |
6753 | if (t->opcode_modifier.evex != EVEXLIG) | |
7bab8ab5 | 6754 | { |
cf665fee JB |
6755 | for (op = 0; op < t->operands; ++op) |
6756 | if (i.types[op].bitfield.zmmword) | |
6757 | break; | |
6758 | if (op >= t->operands) | |
6759 | { | |
6760 | i.error = operand_size_mismatch; | |
6761 | return 1; | |
6762 | } | |
7bab8ab5 | 6763 | } |
6c30d220 L |
6764 | } |
6765 | ||
da4977e0 | 6766 | /* Check the special Imm4 cases; must be the first operand. */ |
734dfd1c | 6767 | if (is_cpu (t, CpuXOP) && t->operands == 5) |
da4977e0 JB |
6768 | { |
6769 | if (i.op[0].imms->X_op != O_constant | |
6770 | || !fits_in_imm4 (i.op[0].imms->X_add_number)) | |
6771 | { | |
6772 | i.error = bad_imm4; | |
6773 | return 1; | |
6774 | } | |
6775 | ||
6776 | /* Turn off Imm<N> so that update_imm won't complain. */ | |
6777 | operand_type_set (&i.types[0], 0); | |
6778 | } | |
6779 | ||
43234a1e | 6780 | /* Check vector Disp8 operand. */ |
b5014f7a | 6781 | if (t->opcode_modifier.disp8memshift |
1a42a9fe | 6782 | && i.disp_encoding <= disp_encoding_8bit) |
43234a1e | 6783 | { |
9b345ce8 | 6784 | if (i.broadcast.type || i.broadcast.bytes) |
4a1b91ea | 6785 | i.memshift = t->opcode_modifier.broadcast - 1; |
7091c612 | 6786 | else if (t->opcode_modifier.disp8memshift != DISP8_SHIFT_VL) |
43234a1e | 6787 | i.memshift = t->opcode_modifier.disp8memshift; |
7091c612 JB |
6788 | else |
6789 | { | |
125ff819 | 6790 | const i386_operand_type *type = NULL, *fallback = NULL; |
7091c612 JB |
6791 | |
6792 | i.memshift = 0; | |
6793 | for (op = 0; op < i.operands; op++) | |
8dc0818e | 6794 | if (i.flags[op] & Operand_Mem) |
7091c612 | 6795 | { |
4174bfff JB |
6796 | if (t->opcode_modifier.evex == EVEXLIG) |
6797 | i.memshift = 2 + (i.suffix == QWORD_MNEM_SUFFIX); | |
6798 | else if (t->operand_types[op].bitfield.xmmword | |
6799 | + t->operand_types[op].bitfield.ymmword | |
6800 | + t->operand_types[op].bitfield.zmmword <= 1) | |
7091c612 JB |
6801 | type = &t->operand_types[op]; |
6802 | else if (!i.types[op].bitfield.unspecified) | |
6803 | type = &i.types[op]; | |
125ff819 JB |
6804 | else /* Ambiguities get resolved elsewhere. */ |
6805 | fallback = &t->operand_types[op]; | |
7091c612 | 6806 | } |
3528c362 | 6807 | else if (i.types[op].bitfield.class == RegSIMD |
4174bfff | 6808 | && t->opcode_modifier.evex != EVEXLIG) |
7091c612 JB |
6809 | { |
6810 | if (i.types[op].bitfield.zmmword) | |
6811 | i.memshift = 6; | |
6812 | else if (i.types[op].bitfield.ymmword && i.memshift < 5) | |
6813 | i.memshift = 5; | |
6814 | else if (i.types[op].bitfield.xmmword && i.memshift < 4) | |
6815 | i.memshift = 4; | |
6816 | } | |
6817 | ||
125ff819 JB |
6818 | if (!type && !i.memshift) |
6819 | type = fallback; | |
7091c612 JB |
6820 | if (type) |
6821 | { | |
6822 | if (type->bitfield.zmmword) | |
6823 | i.memshift = 6; | |
6824 | else if (type->bitfield.ymmword) | |
6825 | i.memshift = 5; | |
6826 | else if (type->bitfield.xmmword) | |
6827 | i.memshift = 4; | |
6828 | } | |
6829 | ||
6830 | /* For the check in fits_in_disp8(). */ | |
6831 | if (i.memshift == 0) | |
6832 | i.memshift = -1; | |
6833 | } | |
43234a1e L |
6834 | |
6835 | for (op = 0; op < i.operands; op++) | |
6836 | if (operand_type_check (i.types[op], disp) | |
6837 | && i.op[op].disps->X_op == O_constant) | |
6838 | { | |
b5014f7a | 6839 | if (fits_in_disp8 (i.op[op].disps->X_add_number)) |
43234a1e | 6840 | { |
b5014f7a JB |
6841 | i.types[op].bitfield.disp8 = 1; |
6842 | return 0; | |
43234a1e | 6843 | } |
b5014f7a | 6844 | i.types[op].bitfield.disp8 = 0; |
43234a1e L |
6845 | } |
6846 | } | |
b5014f7a JB |
6847 | |
6848 | i.memshift = 0; | |
43234a1e | 6849 | |
6c30d220 L |
6850 | return 0; |
6851 | } | |
6852 | ||
da4977e0 | 6853 | /* Check if encoding requirements are met by the instruction. */ |
a683cc34 SP |
6854 | |
6855 | static int | |
da4977e0 | 6856 | VEX_check_encoding (const insn_template *t) |
a683cc34 | 6857 | { |
da4977e0 JB |
6858 | if (i.vec_encoding == vex_encoding_error) |
6859 | { | |
6860 | i.error = unsupported; | |
6861 | return 1; | |
6862 | } | |
6863 | ||
4fc85f37 JB |
6864 | /* Vector size restrictions. */ |
6865 | if ((vector_size < VSZ512 | |
6866 | && (t->opcode_modifier.evex == EVEX512 | |
6867 | || t->opcode_modifier.vsz >= VSZ512)) | |
6868 | || (vector_size < VSZ256 | |
6869 | && (t->opcode_modifier.evex == EVEX256 | |
6870 | || t->opcode_modifier.vex == VEX256 | |
6871 | || t->opcode_modifier.vsz >= VSZ256))) | |
6872 | { | |
6873 | i.error = unsupported; | |
6874 | return 1; | |
6875 | } | |
6876 | ||
86fa6981 | 6877 | if (i.vec_encoding == vex_encoding_evex) |
43234a1e | 6878 | { |
86fa6981 | 6879 | /* This instruction must be encoded with EVEX prefix. */ |
e771e7c9 | 6880 | if (!is_evex_encoding (t)) |
86fa6981 L |
6881 | { |
6882 | i.error = unsupported; | |
6883 | return 1; | |
6884 | } | |
6885 | return 0; | |
43234a1e L |
6886 | } |
6887 | ||
a683cc34 | 6888 | if (!t->opcode_modifier.vex) |
86fa6981 L |
6889 | { |
6890 | /* This instruction template doesn't have VEX prefix. */ | |
6891 | if (i.vec_encoding != vex_encoding_default) | |
6892 | { | |
6893 | i.error = unsupported; | |
6894 | return 1; | |
6895 | } | |
6896 | return 0; | |
6897 | } | |
a683cc34 | 6898 | |
a683cc34 SP |
6899 | return 0; |
6900 | } | |
6901 | ||
7b94647a JB |
6902 | /* Helper function for the progress() macro in match_template(). */ |
6903 | static INLINE enum i386_error progress (enum i386_error new, | |
6904 | enum i386_error last, | |
6905 | unsigned int line, unsigned int *line_p) | |
6906 | { | |
6907 | if (line <= *line_p) | |
6908 | return last; | |
6909 | *line_p = line; | |
6910 | return new; | |
6911 | } | |
6912 | ||
d3ce72d0 | 6913 | static const insn_template * |
83b16ac6 | 6914 | match_template (char mnem_suffix) |
29b0f896 AM |
6915 | { |
6916 | /* Points to template once we've found it. */ | |
d3ce72d0 | 6917 | const insn_template *t; |
40fb9820 | 6918 | i386_operand_type overlap0, overlap1, overlap2, overlap3; |
c0f3af97 | 6919 | i386_operand_type overlap4; |
29b0f896 | 6920 | unsigned int found_reverse_match; |
40fb9820 | 6921 | i386_operand_type operand_types [MAX_OPERANDS]; |
539e75ad | 6922 | int addr_prefix_disp; |
7b94647a JB |
6923 | unsigned int j, size_match, check_register, errline = __LINE__; |
6924 | enum i386_error specific_error = number_of_operands_mismatch; | |
6925 | #define progress(err) progress (err, specific_error, __LINE__, &errline) | |
29b0f896 | 6926 | |
c0f3af97 L |
6927 | #if MAX_OPERANDS != 5 |
6928 | # error "MAX_OPERANDS must be 5." | |
f48ff2ae L |
6929 | #endif |
6930 | ||
29b0f896 | 6931 | found_reverse_match = 0; |
539e75ad | 6932 | addr_prefix_disp = -1; |
40fb9820 | 6933 | |
45aa61fe | 6934 | for (t = current_templates->start; t < current_templates->end; t++) |
29b0f896 | 6935 | { |
539e75ad | 6936 | addr_prefix_disp = -1; |
dbbc8b7e | 6937 | found_reverse_match = 0; |
539e75ad | 6938 | |
7b94647a | 6939 | /* Must have right number of operands. */ |
29b0f896 AM |
6940 | if (i.operands != t->operands) |
6941 | continue; | |
6942 | ||
50aecf8c | 6943 | /* Check processor support. */ |
7b94647a | 6944 | specific_error = progress (unsupported); |
45a4bb20 | 6945 | if (cpu_flags_match (t) != CPU_FLAGS_PERFECT_MATCH) |
50aecf8c L |
6946 | continue; |
6947 | ||
e1d4d893 | 6948 | /* Check AT&T mnemonic. */ |
7b94647a | 6949 | specific_error = progress (unsupported_with_intel_mnemonic); |
e1d4d893 | 6950 | if (intel_mnemonic && t->opcode_modifier.attmnemonic) |
1efbbeb4 L |
6951 | continue; |
6952 | ||
4b5aaf5f | 6953 | /* Check AT&T/Intel syntax. */ |
7b94647a | 6954 | specific_error = progress (unsupported_syntax); |
5c07affc | 6955 | if ((intel_syntax && t->opcode_modifier.attsyntax) |
4b5aaf5f | 6956 | || (!intel_syntax && t->opcode_modifier.intelsyntax)) |
1efbbeb4 L |
6957 | continue; |
6958 | ||
4b5aaf5f L |
6959 | /* Check Intel64/AMD64 ISA. */ |
6960 | switch (isa64) | |
6961 | { | |
6962 | default: | |
6963 | /* Default: Don't accept Intel64. */ | |
6964 | if (t->opcode_modifier.isa64 == INTEL64) | |
6965 | continue; | |
6966 | break; | |
6967 | case amd64: | |
6968 | /* -mamd64: Don't accept Intel64 and Intel64 only. */ | |
6969 | if (t->opcode_modifier.isa64 >= INTEL64) | |
6970 | continue; | |
6971 | break; | |
6972 | case intel64: | |
6973 | /* -mintel64: Don't accept AMD64. */ | |
5990e377 | 6974 | if (t->opcode_modifier.isa64 == AMD64 && flag_code == CODE_64BIT) |
4b5aaf5f L |
6975 | continue; |
6976 | break; | |
6977 | } | |
6978 | ||
dc2be329 | 6979 | /* Check the suffix. */ |
7b94647a | 6980 | specific_error = progress (invalid_instruction_suffix); |
7505bb03 JB |
6981 | if ((t->opcode_modifier.no_bsuf && mnem_suffix == BYTE_MNEM_SUFFIX) |
6982 | || (t->opcode_modifier.no_wsuf && mnem_suffix == WORD_MNEM_SUFFIX) | |
6983 | || (t->opcode_modifier.no_lsuf && mnem_suffix == LONG_MNEM_SUFFIX) | |
6984 | || (t->opcode_modifier.no_ssuf && mnem_suffix == SHORT_MNEM_SUFFIX) | |
6985 | || (t->opcode_modifier.no_qsuf && mnem_suffix == QWORD_MNEM_SUFFIX)) | |
83b16ac6 | 6986 | continue; |
29b0f896 | 6987 | |
7b94647a | 6988 | specific_error = progress (operand_size_mismatch); |
3ac21baa JB |
6989 | size_match = operand_size_match (t); |
6990 | if (!size_match) | |
7d5e4556 | 6991 | continue; |
539e75ad | 6992 | |
6f2f06be JB |
6993 | /* This is intentionally not |
6994 | ||
0cfa3eb3 | 6995 | if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE)) |
6f2f06be JB |
6996 | |
6997 | as the case of a missing * on the operand is accepted (perhaps with | |
6998 | a warning, issued further down). */ | |
7b94647a | 6999 | specific_error = progress (operand_type_mismatch); |
0cfa3eb3 | 7000 | if (i.jumpabsolute && t->opcode_modifier.jump != JUMP_ABSOLUTE) |
7b94647a | 7001 | continue; |
6f2f06be | 7002 | |
a4d3acd2 JB |
7003 | /* In Intel syntax, normally we can check for memory operand size when |
7004 | there is no mnemonic suffix. But jmp and call have 2 different | |
7005 | encodings with Dword memory operand size. Skip the "near" one | |
7006 | (permitting a register operand) when "far" was requested. */ | |
7007 | if (i.far_branch | |
7008 | && t->opcode_modifier.jump == JUMP_ABSOLUTE | |
7009 | && t->operand_types[0].bitfield.class == Reg) | |
7010 | continue; | |
7011 | ||
5c07affc L |
7012 | for (j = 0; j < MAX_OPERANDS; j++) |
7013 | operand_types[j] = t->operand_types[j]; | |
7014 | ||
9db83a32 | 7015 | /* In general, don't allow 32-bit operands on pre-386. */ |
7b94647a JB |
7016 | specific_error = progress (mnem_suffix ? invalid_instruction_suffix |
7017 | : operand_size_mismatch); | |
4873e243 | 7018 | j = i.imm_operands + (t->operands > i.imm_operands + 1); |
9db83a32 JB |
7019 | if (i.suffix == LONG_MNEM_SUFFIX |
7020 | && !cpu_arch_flags.bitfield.cpui386 | |
45aa61fe | 7021 | && (intel_syntax |
3cd7f3e3 | 7022 | ? (t->opcode_modifier.mnemonicsize != IGNORESIZE |
76d3f746 JB |
7023 | && !intel_float_operand (insn_name (t))) |
7024 | : intel_float_operand (insn_name (t)) != 2) | |
4873e243 JB |
7025 | && (t->operands == i.imm_operands |
7026 | || (operand_types[i.imm_operands].bitfield.class != RegMMX | |
7027 | && operand_types[i.imm_operands].bitfield.class != RegSIMD | |
7028 | && operand_types[i.imm_operands].bitfield.class != RegMask) | |
7029 | || (operand_types[j].bitfield.class != RegMMX | |
7030 | && operand_types[j].bitfield.class != RegSIMD | |
7031 | && operand_types[j].bitfield.class != RegMask)) | |
63112cd6 | 7032 | && !t->opcode_modifier.sib) |
192dc9c6 JB |
7033 | continue; |
7034 | ||
29b0f896 | 7035 | /* Do not verify operands when there are none. */ |
e365e234 | 7036 | if (!t->operands) |
da4977e0 JB |
7037 | { |
7038 | if (VEX_check_encoding (t)) | |
7039 | { | |
7b94647a | 7040 | specific_error = progress (i.error); |
da4977e0 JB |
7041 | continue; |
7042 | } | |
7043 | ||
7044 | /* We've found a match; break out of loop. */ | |
7045 | break; | |
7046 | } | |
252b5132 | 7047 | |
48bcea9f JB |
7048 | if (!t->opcode_modifier.jump |
7049 | || t->opcode_modifier.jump == JUMP_ABSOLUTE) | |
7050 | { | |
7051 | /* There should be only one Disp operand. */ | |
7052 | for (j = 0; j < MAX_OPERANDS; j++) | |
7053 | if (operand_type_check (operand_types[j], disp)) | |
539e75ad | 7054 | break; |
48bcea9f JB |
7055 | if (j < MAX_OPERANDS) |
7056 | { | |
5b7c81bd | 7057 | bool override = (i.prefix[ADDR_PREFIX] != 0); |
48bcea9f JB |
7058 | |
7059 | addr_prefix_disp = j; | |
7060 | ||
a775efc8 JB |
7061 | /* Address size prefix will turn Disp64 operand into Disp32 and |
7062 | Disp32/Disp16 one into Disp16/Disp32 respectively. */ | |
48bcea9f | 7063 | switch (flag_code) |
40fb9820 | 7064 | { |
48bcea9f JB |
7065 | case CODE_16BIT: |
7066 | override = !override; | |
7067 | /* Fall through. */ | |
7068 | case CODE_32BIT: | |
7069 | if (operand_types[j].bitfield.disp32 | |
7070 | && operand_types[j].bitfield.disp16) | |
40fb9820 | 7071 | { |
48bcea9f JB |
7072 | operand_types[j].bitfield.disp16 = override; |
7073 | operand_types[j].bitfield.disp32 = !override; | |
40fb9820 | 7074 | } |
a775efc8 | 7075 | gas_assert (!operand_types[j].bitfield.disp64); |
48bcea9f JB |
7076 | break; |
7077 | ||
7078 | case CODE_64BIT: | |
a775efc8 | 7079 | if (operand_types[j].bitfield.disp64) |
40fb9820 | 7080 | { |
a775efc8 | 7081 | gas_assert (!operand_types[j].bitfield.disp32); |
48bcea9f | 7082 | operand_types[j].bitfield.disp32 = override; |
a775efc8 | 7083 | operand_types[j].bitfield.disp64 = !override; |
40fb9820 | 7084 | } |
48bcea9f JB |
7085 | operand_types[j].bitfield.disp16 = 0; |
7086 | break; | |
40fb9820 | 7087 | } |
539e75ad | 7088 | } |
48bcea9f | 7089 | } |
539e75ad | 7090 | |
56ffb741 | 7091 | /* We check register size if needed. */ |
9c19e9ec | 7092 | if (t->opcode_modifier.checkoperandsize) |
e2195274 JB |
7093 | { |
7094 | check_register = (1 << t->operands) - 1; | |
a5748e0d | 7095 | if (i.broadcast.type || i.broadcast.bytes) |
5273a3cd | 7096 | check_register &= ~(1 << i.broadcast.operand); |
e2195274 JB |
7097 | } |
7098 | else | |
7099 | check_register = 0; | |
7100 | ||
c6fb90c8 | 7101 | overlap0 = operand_type_and (i.types[0], operand_types[0]); |
29b0f896 AM |
7102 | switch (t->operands) |
7103 | { | |
7104 | case 1: | |
40fb9820 | 7105 | if (!operand_type_match (overlap0, i.types[0])) |
29b0f896 | 7106 | continue; |
ae9a0a51 JB |
7107 | |
7108 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
7109 | {store} pseudo prefix on an applicable insn. */ | |
7110 | if (!t->opcode_modifier.modrm | |
7111 | && i.reg_operands == 1 | |
7112 | && ((i.dir_encoding == dir_encoding_load | |
7113 | && t->mnem_off != MN_pop) | |
7114 | || (i.dir_encoding == dir_encoding_store | |
7115 | && t->mnem_off != MN_push)) | |
7116 | /* Avoid BSWAP. */ | |
7117 | && t->mnem_off != MN_bswap) | |
7118 | continue; | |
29b0f896 | 7119 | break; |
ae9a0a51 | 7120 | |
29b0f896 | 7121 | case 2: |
33eaf5de | 7122 | /* xchg %eax, %eax is a special case. It is an alias for nop |
8b38ad71 L |
7123 | only in 32bit mode and we can use opcode 0x90. In 64bit |
7124 | mode, we can't use 0x90 for xchg %eax, %eax since it should | |
7125 | zero-extend %eax to %rax. */ | |
ae9a0a51 JB |
7126 | if (t->base_opcode == 0x90 |
7127 | && t->opcode_space == SPACE_BASE) | |
7128 | { | |
7129 | if (flag_code == CODE_64BIT | |
7130 | && i.types[0].bitfield.instance == Accum | |
7131 | && i.types[0].bitfield.dword | |
7132 | && i.types[1].bitfield.instance == Accum) | |
7133 | continue; | |
7134 | ||
7135 | /* Allow the ModR/M encoding to be requested by using the | |
7136 | {load} or {store} pseudo prefix. */ | |
7137 | if (i.dir_encoding == dir_encoding_load | |
7138 | || i.dir_encoding == dir_encoding_store) | |
7139 | continue; | |
7140 | } | |
e3669c7f JB |
7141 | |
7142 | if (t->base_opcode == MOV_AX_DISP32 | |
ddb62495 | 7143 | && t->opcode_space == SPACE_BASE |
69196391 | 7144 | && t->mnem_off != MN_movabs) |
e3669c7f JB |
7145 | { |
7146 | /* Force 0x8b encoding for "mov foo@GOT, %eax". */ | |
7147 | if (i.reloc[0] == BFD_RELOC_386_GOT32) | |
7148 | continue; | |
7149 | ||
7150 | /* xrelease mov %eax, <disp> is another special case. It must not | |
7151 | match the accumulator-only encoding of mov. */ | |
7152 | if (i.hle_prefix) | |
7153 | continue; | |
ae9a0a51 JB |
7154 | |
7155 | /* Allow the ModR/M encoding to be requested by using a suitable | |
7156 | {load} or {store} pseudo prefix. */ | |
7157 | if (i.dir_encoding == (i.types[0].bitfield.instance == Accum | |
7158 | ? dir_encoding_store | |
7159 | : dir_encoding_load) | |
7160 | && !i.types[0].bitfield.disp64 | |
7161 | && !i.types[1].bitfield.disp64) | |
7162 | continue; | |
7163 | } | |
7164 | ||
7165 | /* Allow the ModR/M encoding to be requested by using the {load} or | |
7166 | {store} pseudo prefix on an applicable insn. */ | |
7167 | if (!t->opcode_modifier.modrm | |
7168 | && i.reg_operands == 1 | |
7169 | && i.imm_operands == 1 | |
7170 | && (i.dir_encoding == dir_encoding_load | |
7171 | || i.dir_encoding == dir_encoding_store) | |
7172 | && t->opcode_space == SPACE_BASE) | |
7173 | { | |
7174 | if (t->base_opcode == 0xb0 /* mov $imm, %reg */ | |
7175 | && i.dir_encoding == dir_encoding_store) | |
7176 | continue; | |
7177 | ||
7178 | if ((t->base_opcode | 0x38) == 0x3c /* <alu> $imm, %acc */ | |
7179 | && (t->base_opcode != 0x3c /* cmp $imm, %acc */ | |
7180 | || i.dir_encoding == dir_encoding_load)) | |
7181 | continue; | |
7182 | ||
7183 | if (t->base_opcode == 0xa8 /* test $imm, %acc */ | |
7184 | && i.dir_encoding == dir_encoding_load) | |
7185 | continue; | |
e3669c7f | 7186 | } |
f5eb1d70 JB |
7187 | /* Fall through. */ |
7188 | ||
7189 | case 3: | |
3ac21baa JB |
7190 | if (!(size_match & MATCH_STRAIGHT)) |
7191 | goto check_reverse; | |
64c49ab3 JB |
7192 | /* Reverse direction of operands if swapping is possible in the first |
7193 | place (operands need to be symmetric) and | |
7194 | - the load form is requested, and the template is a store form, | |
7195 | - the store form is requested, and the template is a load form, | |
7196 | - the non-default (swapped) form is requested. */ | |
7197 | overlap1 = operand_type_and (operand_types[0], operand_types[1]); | |
f5eb1d70 | 7198 | if (t->opcode_modifier.d && i.reg_operands == i.operands |
64c49ab3 JB |
7199 | && !operand_type_all_zero (&overlap1)) |
7200 | switch (i.dir_encoding) | |
7201 | { | |
7202 | case dir_encoding_load: | |
7203 | if (operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 7204 | || t->opcode_modifier.regmem) |
64c49ab3 JB |
7205 | goto check_reverse; |
7206 | break; | |
7207 | ||
7208 | case dir_encoding_store: | |
7209 | if (!operand_type_check (operand_types[i.operands - 1], anymem) | |
dfd69174 | 7210 | && !t->opcode_modifier.regmem) |
64c49ab3 JB |
7211 | goto check_reverse; |
7212 | break; | |
7213 | ||
7214 | case dir_encoding_swap: | |
7215 | goto check_reverse; | |
7216 | ||
7217 | case dir_encoding_default: | |
7218 | break; | |
7219 | } | |
86fa6981 | 7220 | /* If we want store form, we skip the current load. */ |
64c49ab3 JB |
7221 | if ((i.dir_encoding == dir_encoding_store |
7222 | || i.dir_encoding == dir_encoding_swap) | |
86fa6981 L |
7223 | && i.mem_operands == 0 |
7224 | && t->opcode_modifier.load) | |
fa99fab2 | 7225 | continue; |
1a0670f3 | 7226 | /* Fall through. */ |
f48ff2ae | 7227 | case 4: |
c0f3af97 | 7228 | case 5: |
c6fb90c8 | 7229 | overlap1 = operand_type_and (i.types[1], operand_types[1]); |
40fb9820 L |
7230 | if (!operand_type_match (overlap0, i.types[0]) |
7231 | || !operand_type_match (overlap1, i.types[1]) | |
e2195274 | 7232 | || ((check_register & 3) == 3 |
dc821c5f | 7233 | && !operand_type_register_match (i.types[0], |
40fb9820 | 7234 | operand_types[0], |
dc821c5f | 7235 | i.types[1], |
40fb9820 | 7236 | operand_types[1]))) |
29b0f896 | 7237 | { |
7b94647a JB |
7238 | specific_error = progress (i.error); |
7239 | ||
29b0f896 | 7240 | /* Check if other direction is valid ... */ |
38e314eb | 7241 | if (!t->opcode_modifier.d) |
29b0f896 AM |
7242 | continue; |
7243 | ||
dc1e8a47 | 7244 | check_reverse: |
3ac21baa JB |
7245 | if (!(size_match & MATCH_REVERSE)) |
7246 | continue; | |
29b0f896 | 7247 | /* Try reversing direction of operands. */ |
734dfd1c JB |
7248 | j = is_cpu (t, CpuFMA4) |
7249 | || is_cpu (t, CpuXOP) ? 1 : i.operands - 1; | |
8bd915b7 JB |
7250 | overlap0 = operand_type_and (i.types[0], operand_types[j]); |
7251 | overlap1 = operand_type_and (i.types[j], operand_types[0]); | |
c975cec5 JB |
7252 | overlap2 = operand_type_and (i.types[1], operand_types[1]); |
7253 | gas_assert (t->operands != 3 || !check_register); | |
40fb9820 | 7254 | if (!operand_type_match (overlap0, i.types[0]) |
8bd915b7 | 7255 | || !operand_type_match (overlap1, i.types[j]) |
c975cec5 JB |
7256 | || (t->operands == 3 |
7257 | && !operand_type_match (overlap2, i.types[1])) | |
45664ddb | 7258 | || (check_register |
dc821c5f | 7259 | && !operand_type_register_match (i.types[0], |
8bd915b7 JB |
7260 | operand_types[j], |
7261 | i.types[j], | |
45664ddb | 7262 | operand_types[0]))) |
29b0f896 AM |
7263 | { |
7264 | /* Does not match either direction. */ | |
7b94647a | 7265 | specific_error = progress (i.error); |
29b0f896 AM |
7266 | continue; |
7267 | } | |
ac9226cf | 7268 | /* found_reverse_match holds which variant of D |
29b0f896 | 7269 | we've found. */ |
38e314eb JB |
7270 | if (!t->opcode_modifier.d) |
7271 | found_reverse_match = 0; | |
7272 | else if (operand_types[0].bitfield.tbyte) | |
ac9226cf | 7273 | { |
4943d587 JB |
7274 | if (t->opcode_modifier.operandconstraint != UGH) |
7275 | found_reverse_match = Opcode_FloatD; | |
bd782808 JB |
7276 | else |
7277 | found_reverse_match = ~0; | |
ac9226cf | 7278 | /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */ |
bd782808 | 7279 | if ((t->extension_opcode & 4) |
ac9226cf JB |
7280 | && (intel_syntax || intel_mnemonic)) |
7281 | found_reverse_match |= Opcode_FloatR; | |
7282 | } | |
734dfd1c | 7283 | else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)) |
8bd915b7 JB |
7284 | { |
7285 | found_reverse_match = Opcode_VexW; | |
7286 | goto check_operands_345; | |
7287 | } | |
ddb62495 JB |
7288 | else if (t->opcode_space != SPACE_BASE |
7289 | && (t->opcode_space != SPACE_0F | |
2c735193 JB |
7290 | /* MOV to/from CR/DR/TR, as an exception, follow |
7291 | the base opcode space encoding model. */ | |
7292 | || (t->base_opcode | 7) != 0x27)) | |
dbbc8b7e | 7293 | found_reverse_match = (t->base_opcode & 0xee) != 0x6e |
2c735193 | 7294 | ? Opcode_ExtD : Opcode_SIMD_IntD; |
a33ef3c2 | 7295 | else if (!t->opcode_modifier.commutative) |
38e314eb | 7296 | found_reverse_match = Opcode_D; |
a33ef3c2 JB |
7297 | else |
7298 | found_reverse_match = ~0; | |
29b0f896 | 7299 | } |
f48ff2ae | 7300 | else |
29b0f896 | 7301 | { |
f48ff2ae | 7302 | /* Found a forward 2 operand match here. */ |
8bd915b7 | 7303 | check_operands_345: |
d1cbb4db L |
7304 | switch (t->operands) |
7305 | { | |
c0f3af97 | 7306 | case 5: |
3d0738af | 7307 | overlap4 = operand_type_and (i.types[4], operand_types[4]); |
c0f3af97 | 7308 | if (!operand_type_match (overlap4, i.types[4]) |
dc821c5f | 7309 | || !operand_type_register_match (i.types[3], |
c0f3af97 | 7310 | operand_types[3], |
c0f3af97 L |
7311 | i.types[4], |
7312 | operand_types[4])) | |
7b94647a JB |
7313 | { |
7314 | specific_error = progress (i.error); | |
7315 | continue; | |
7316 | } | |
1a0670f3 | 7317 | /* Fall through. */ |
f48ff2ae | 7318 | case 4: |
3d0738af | 7319 | overlap3 = operand_type_and (i.types[3], operand_types[3]); |
40fb9820 | 7320 | if (!operand_type_match (overlap3, i.types[3]) |
e2195274 JB |
7321 | || ((check_register & 0xa) == 0xa |
7322 | && !operand_type_register_match (i.types[1], | |
f7768225 JB |
7323 | operand_types[1], |
7324 | i.types[3], | |
e2195274 JB |
7325 | operand_types[3])) |
7326 | || ((check_register & 0xc) == 0xc | |
7327 | && !operand_type_register_match (i.types[2], | |
7328 | operand_types[2], | |
7329 | i.types[3], | |
7330 | operand_types[3]))) | |
7b94647a JB |
7331 | { |
7332 | specific_error = progress (i.error); | |
7333 | continue; | |
7334 | } | |
1a0670f3 | 7335 | /* Fall through. */ |
f48ff2ae | 7336 | case 3: |
3d0738af | 7337 | overlap2 = operand_type_and (i.types[2], operand_types[2]); |
40fb9820 | 7338 | if (!operand_type_match (overlap2, i.types[2]) |
e2195274 JB |
7339 | || ((check_register & 5) == 5 |
7340 | && !operand_type_register_match (i.types[0], | |
23e42951 JB |
7341 | operand_types[0], |
7342 | i.types[2], | |
e2195274 JB |
7343 | operand_types[2])) |
7344 | || ((check_register & 6) == 6 | |
7345 | && !operand_type_register_match (i.types[1], | |
7346 | operand_types[1], | |
7347 | i.types[2], | |
7348 | operand_types[2]))) | |
7b94647a JB |
7349 | { |
7350 | specific_error = progress (i.error); | |
7351 | continue; | |
7352 | } | |
f48ff2ae L |
7353 | break; |
7354 | } | |
29b0f896 | 7355 | } |
f48ff2ae | 7356 | /* Found either forward/reverse 2, 3 or 4 operand match here: |
29b0f896 AM |
7357 | slip through to break. */ |
7358 | } | |
c0f3af97 | 7359 | |
9bb4d860 L |
7360 | /* Check if VEX/EVEX encoding requirements can be satisfied. */ |
7361 | if (VEX_check_encoding (t)) | |
da4977e0 | 7362 | { |
7b94647a | 7363 | specific_error = progress (i.error); |
da4977e0 JB |
7364 | continue; |
7365 | } | |
7366 | ||
9bb4d860 L |
7367 | /* Check if vector operands are valid. */ |
7368 | if (check_VecOperands (t)) | |
5614d22c | 7369 | { |
7b94647a | 7370 | specific_error = progress (i.error); |
5614d22c JB |
7371 | continue; |
7372 | } | |
a683cc34 | 7373 | |
29b0f896 AM |
7374 | /* We've found a match; break out of loop. */ |
7375 | break; | |
7376 | } | |
7377 | ||
7b94647a JB |
7378 | #undef progress |
7379 | ||
29b0f896 AM |
7380 | if (t == current_templates->end) |
7381 | { | |
7382 | /* We found no match. */ | |
04784e33 | 7383 | i.error = specific_error; |
fa99fab2 | 7384 | return NULL; |
29b0f896 | 7385 | } |
252b5132 | 7386 | |
29b0f896 AM |
7387 | if (!quiet_warnings) |
7388 | { | |
7389 | if (!intel_syntax | |
0cfa3eb3 | 7390 | && (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))) |
76d3f746 | 7391 | as_warn (_("indirect %s without `*'"), insn_name (t)); |
29b0f896 | 7392 | |
40fb9820 | 7393 | if (t->opcode_modifier.isprefix |
3cd7f3e3 | 7394 | && t->opcode_modifier.mnemonicsize == IGNORESIZE) |
29b0f896 AM |
7395 | { |
7396 | /* Warn them that a data or address size prefix doesn't | |
7397 | affect assembly of the next line of code. */ | |
76d3f746 | 7398 | as_warn (_("stand-alone `%s' prefix"), insn_name (t)); |
29b0f896 AM |
7399 | } |
7400 | } | |
7401 | ||
7402 | /* Copy the template we found. */ | |
9a182d04 | 7403 | install_template (t); |
539e75ad L |
7404 | |
7405 | if (addr_prefix_disp != -1) | |
7406 | i.tm.operand_types[addr_prefix_disp] | |
7407 | = operand_types[addr_prefix_disp]; | |
7408 | ||
8bd915b7 | 7409 | switch (found_reverse_match) |
29b0f896 | 7410 | { |
8bd915b7 JB |
7411 | case 0: |
7412 | break; | |
7413 | ||
bd782808 JB |
7414 | case Opcode_FloatR: |
7415 | case Opcode_FloatR | Opcode_FloatD: | |
7416 | i.tm.extension_opcode ^= Opcode_FloatR >> 3; | |
7417 | found_reverse_match &= Opcode_FloatD; | |
7418 | ||
7419 | /* Fall through. */ | |
8bd915b7 | 7420 | default: |
dfd69174 JB |
7421 | /* If we found a reverse match we must alter the opcode direction |
7422 | bit and clear/flip the regmem modifier one. found_reverse_match | |
7423 | holds bits to change (different for int & float insns). */ | |
29b0f896 AM |
7424 | |
7425 | i.tm.base_opcode ^= found_reverse_match; | |
7426 | ||
dfd69174 JB |
7427 | /* Certain SIMD insns have their load forms specified in the opcode |
7428 | table, and hence we need to _set_ RegMem instead of clearing it. | |
7429 | We need to avoid setting the bit though on insns like KMOVW. */ | |
7430 | i.tm.opcode_modifier.regmem | |
7431 | = i.tm.opcode_modifier.modrm && i.tm.opcode_modifier.d | |
7432 | && i.tm.operands > 2U - i.tm.opcode_modifier.sse2avx | |
7433 | && !i.tm.opcode_modifier.regmem; | |
a33ef3c2 JB |
7434 | |
7435 | /* Fall through. */ | |
7436 | case ~0: | |
7437 | i.tm.operand_types[0] = operand_types[i.operands - 1]; | |
7438 | i.tm.operand_types[i.operands - 1] = operand_types[0]; | |
8bd915b7 JB |
7439 | break; |
7440 | ||
7441 | case Opcode_VexW: | |
7442 | /* Only the first two register operands need reversing, alongside | |
7443 | flipping VEX.W. */ | |
7444 | i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1; | |
7445 | ||
7446 | j = i.tm.operand_types[0].bitfield.imm8; | |
7447 | i.tm.operand_types[j] = operand_types[j + 1]; | |
7448 | i.tm.operand_types[j + 1] = operand_types[j]; | |
7449 | break; | |
29b0f896 AM |
7450 | } |
7451 | ||
fa99fab2 | 7452 | return t; |
29b0f896 AM |
7453 | } |
7454 | ||
7455 | static int | |
e3bb37b5 | 7456 | check_string (void) |
29b0f896 | 7457 | { |
51c8edf6 JB |
7458 | unsigned int es_op = i.tm.opcode_modifier.isstring - IS_STRING_ES_OP0; |
7459 | unsigned int op = i.tm.operand_types[0].bitfield.baseindex ? es_op : 0; | |
8dc0818e | 7460 | |
5e042380 | 7461 | if (i.seg[op] != NULL && i.seg[op] != reg_es) |
29b0f896 | 7462 | { |
51c8edf6 | 7463 | as_bad (_("`%s' operand %u must use `%ses' segment"), |
76d3f746 | 7464 | insn_name (&i.tm), |
51c8edf6 JB |
7465 | intel_syntax ? i.tm.operands - es_op : es_op + 1, |
7466 | register_prefix); | |
7467 | return 0; | |
29b0f896 | 7468 | } |
51c8edf6 JB |
7469 | |
7470 | /* There's only ever one segment override allowed per instruction. | |
7471 | This instruction possibly has a legal segment override on the | |
7472 | second operand, so copy the segment to where non-string | |
7473 | instructions store it, allowing common code. */ | |
7474 | i.seg[op] = i.seg[1]; | |
7475 | ||
29b0f896 AM |
7476 | return 1; |
7477 | } | |
7478 | ||
7479 | static int | |
543613e9 | 7480 | process_suffix (void) |
29b0f896 | 7481 | { |
7fc69528 | 7482 | bool is_movx = false; |
8b65b895 | 7483 | |
29b0f896 AM |
7484 | /* If matched instruction specifies an explicit instruction mnemonic |
7485 | suffix, use it. */ | |
673fe0f0 | 7486 | if (i.tm.opcode_modifier.size == SIZE16) |
40fb9820 | 7487 | i.suffix = WORD_MNEM_SUFFIX; |
673fe0f0 | 7488 | else if (i.tm.opcode_modifier.size == SIZE32) |
40fb9820 | 7489 | i.suffix = LONG_MNEM_SUFFIX; |
673fe0f0 | 7490 | else if (i.tm.opcode_modifier.size == SIZE64) |
40fb9820 | 7491 | i.suffix = QWORD_MNEM_SUFFIX; |
13e600d0 | 7492 | else if (i.reg_operands |
c8f8eebc | 7493 | && (i.operands > 1 || i.types[0].bitfield.class == Reg) |
255571cd | 7494 | && i.tm.opcode_modifier.operandconstraint != ADDR_PREFIX_OP_REG) |
29b0f896 | 7495 | { |
65fca059 | 7496 | unsigned int numop = i.operands; |
389d00a5 JB |
7497 | |
7498 | /* MOVSX/MOVZX */ | |
ddb62495 | 7499 | is_movx = (i.tm.opcode_space == SPACE_0F |
389d00a5 | 7500 | && (i.tm.base_opcode | 8) == 0xbe) |
ddb62495 | 7501 | || (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 7502 | && i.tm.base_opcode == 0x63 |
734dfd1c | 7503 | && is_cpu (&i.tm, Cpu64)); |
389d00a5 | 7504 | |
65fca059 JB |
7505 | /* movsx/movzx want only their source operand considered here, for the |
7506 | ambiguity checking below. The suffix will be replaced afterwards | |
7507 | to represent the destination (register). */ | |
389d00a5 | 7508 | if (is_movx && (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63)) |
65fca059 JB |
7509 | --i.operands; |
7510 | ||
643bb870 | 7511 | /* crc32 needs REX.W set regardless of suffix / source operand size. */ |
7fc69528 | 7512 | if (i.tm.mnem_off == MN_crc32 && i.tm.operand_types[1].bitfield.qword) |
643bb870 JB |
7513 | i.rex |= REX_W; |
7514 | ||
29b0f896 | 7515 | /* If there's no instruction mnemonic suffix we try to invent one |
13e600d0 | 7516 | based on GPR operands. */ |
29b0f896 AM |
7517 | if (!i.suffix) |
7518 | { | |
7519 | /* We take i.suffix from the last register operand specified, | |
7520 | Destination register type is more significant than source | |
381d071f L |
7521 | register type. crc32 in SSE4.2 prefers source register |
7522 | type. */ | |
7fc69528 | 7523 | unsigned int op = i.tm.mnem_off == MN_crc32 ? 1 : i.operands; |
20592a94 | 7524 | |
1a035124 JB |
7525 | while (op--) |
7526 | if (i.tm.operand_types[op].bitfield.instance == InstanceNone | |
7527 | || i.tm.operand_types[op].bitfield.instance == Accum) | |
7528 | { | |
7529 | if (i.types[op].bitfield.class != Reg) | |
7530 | continue; | |
7531 | if (i.types[op].bitfield.byte) | |
7532 | i.suffix = BYTE_MNEM_SUFFIX; | |
7533 | else if (i.types[op].bitfield.word) | |
7534 | i.suffix = WORD_MNEM_SUFFIX; | |
7535 | else if (i.types[op].bitfield.dword) | |
7536 | i.suffix = LONG_MNEM_SUFFIX; | |
7537 | else if (i.types[op].bitfield.qword) | |
7538 | i.suffix = QWORD_MNEM_SUFFIX; | |
7539 | else | |
7540 | continue; | |
7541 | break; | |
7542 | } | |
65fca059 JB |
7543 | |
7544 | /* As an exception, movsx/movzx silently default to a byte source | |
7545 | in AT&T mode. */ | |
389d00a5 | 7546 | if (is_movx && i.tm.opcode_modifier.w && !i.suffix && !intel_syntax) |
65fca059 | 7547 | i.suffix = BYTE_MNEM_SUFFIX; |
29b0f896 AM |
7548 | } |
7549 | else if (i.suffix == BYTE_MNEM_SUFFIX) | |
7550 | { | |
1cb0ab18 | 7551 | if (!check_byte_reg ()) |
29b0f896 AM |
7552 | return 0; |
7553 | } | |
7554 | else if (i.suffix == LONG_MNEM_SUFFIX) | |
7555 | { | |
1cb0ab18 | 7556 | if (!check_long_reg ()) |
29b0f896 AM |
7557 | return 0; |
7558 | } | |
7559 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
7560 | { | |
1cb0ab18 | 7561 | if (!check_qword_reg ()) |
29b0f896 AM |
7562 | return 0; |
7563 | } | |
7564 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
7565 | { | |
1cb0ab18 | 7566 | if (!check_word_reg ()) |
29b0f896 AM |
7567 | return 0; |
7568 | } | |
3cd7f3e3 L |
7569 | else if (intel_syntax |
7570 | && i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
29b0f896 AM |
7571 | /* Do nothing if the instruction is going to ignore the prefix. */ |
7572 | ; | |
7573 | else | |
7574 | abort (); | |
65fca059 JB |
7575 | |
7576 | /* Undo the movsx/movzx change done above. */ | |
7577 | i.operands = numop; | |
29b0f896 | 7578 | } |
3cd7f3e3 L |
7579 | else if (i.tm.opcode_modifier.mnemonicsize == DEFAULTSIZE |
7580 | && !i.suffix) | |
29b0f896 | 7581 | { |
13e600d0 JB |
7582 | i.suffix = stackop_size; |
7583 | if (stackop_size == LONG_MNEM_SUFFIX) | |
06f74c5c L |
7584 | { |
7585 | /* stackop_size is set to LONG_MNEM_SUFFIX for the | |
7586 | .code16gcc directive to support 16-bit mode with | |
7587 | 32-bit address. For IRET without a suffix, generate | |
7588 | 16-bit IRET (opcode 0xcf) to return from an interrupt | |
7589 | handler. */ | |
13e600d0 JB |
7590 | if (i.tm.base_opcode == 0xcf) |
7591 | { | |
7592 | i.suffix = WORD_MNEM_SUFFIX; | |
7593 | as_warn (_("generating 16-bit `iret' for .code16gcc directive")); | |
7594 | } | |
7595 | /* Warn about changed behavior for segment register push/pop. */ | |
7596 | else if ((i.tm.base_opcode | 1) == 0x07) | |
7597 | as_warn (_("generating 32-bit `%s', unlike earlier gas versions"), | |
76d3f746 | 7598 | insn_name (&i.tm)); |
06f74c5c | 7599 | } |
29b0f896 | 7600 | } |
c006a730 | 7601 | else if (!i.suffix |
0cfa3eb3 JB |
7602 | && (i.tm.opcode_modifier.jump == JUMP_ABSOLUTE |
7603 | || i.tm.opcode_modifier.jump == JUMP_BYTE | |
7604 | || i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT | |
ddb62495 | 7605 | || (i.tm.opcode_space == SPACE_0F |
389d00a5 | 7606 | && i.tm.base_opcode == 0x01 /* [ls][gi]dt */ |
64e74474 | 7607 | && i.tm.extension_opcode <= 3))) |
9306ca4a JB |
7608 | { |
7609 | switch (flag_code) | |
7610 | { | |
7611 | case CODE_64BIT: | |
40fb9820 | 7612 | if (!i.tm.opcode_modifier.no_qsuf) |
9306ca4a | 7613 | { |
828c2a25 JB |
7614 | if (i.tm.opcode_modifier.jump == JUMP_BYTE |
7615 | || i.tm.opcode_modifier.no_lsuf) | |
7616 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a JB |
7617 | break; |
7618 | } | |
1a0670f3 | 7619 | /* Fall through. */ |
9306ca4a | 7620 | case CODE_32BIT: |
40fb9820 | 7621 | if (!i.tm.opcode_modifier.no_lsuf) |
9306ca4a JB |
7622 | i.suffix = LONG_MNEM_SUFFIX; |
7623 | break; | |
7624 | case CODE_16BIT: | |
40fb9820 | 7625 | if (!i.tm.opcode_modifier.no_wsuf) |
9306ca4a JB |
7626 | i.suffix = WORD_MNEM_SUFFIX; |
7627 | break; | |
7628 | } | |
7629 | } | |
252b5132 | 7630 | |
c006a730 | 7631 | if (!i.suffix |
3cd7f3e3 | 7632 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 JB |
7633 | /* Also cover lret/retf/iret in 64-bit mode. */ |
7634 | || (flag_code == CODE_64BIT | |
7635 | && !i.tm.opcode_modifier.no_lsuf | |
7636 | && !i.tm.opcode_modifier.no_qsuf)) | |
3cd7f3e3 | 7637 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
8bbb3ad8 JB |
7638 | /* Explicit sizing prefixes are assumed to disambiguate insns. */ |
7639 | && !i.prefix[DATA_PREFIX] && !(i.prefix[REX_PREFIX] & REX_W) | |
62b3f548 JB |
7640 | /* Accept FLDENV et al without suffix. */ |
7641 | && (i.tm.opcode_modifier.no_ssuf || i.tm.opcode_modifier.floatmf)) | |
29b0f896 | 7642 | { |
6c0946d0 | 7643 | unsigned int suffixes, evex = 0; |
c006a730 JB |
7644 | |
7645 | suffixes = !i.tm.opcode_modifier.no_bsuf; | |
7646 | if (!i.tm.opcode_modifier.no_wsuf) | |
7647 | suffixes |= 1 << 1; | |
7648 | if (!i.tm.opcode_modifier.no_lsuf) | |
7649 | suffixes |= 1 << 2; | |
c006a730 JB |
7650 | if (!i.tm.opcode_modifier.no_ssuf) |
7651 | suffixes |= 1 << 4; | |
7652 | if (flag_code == CODE_64BIT && !i.tm.opcode_modifier.no_qsuf) | |
7653 | suffixes |= 1 << 5; | |
7654 | ||
6c0946d0 JB |
7655 | /* For [XYZ]MMWORD operands inspect operand sizes. While generally |
7656 | also suitable for AT&T syntax mode, it was requested that this be | |
7657 | restricted to just Intel syntax. */ | |
a5748e0d JB |
7658 | if (intel_syntax && is_any_vex_encoding (&i.tm) |
7659 | && !i.broadcast.type && !i.broadcast.bytes) | |
6c0946d0 | 7660 | { |
b9915cbc | 7661 | unsigned int op; |
6c0946d0 | 7662 | |
b9915cbc | 7663 | for (op = 0; op < i.tm.operands; ++op) |
6c0946d0 | 7664 | { |
4fc85f37 JB |
7665 | if (vector_size < VSZ512) |
7666 | { | |
7667 | i.tm.operand_types[op].bitfield.zmmword = 0; | |
7668 | if (vector_size < VSZ256) | |
7669 | { | |
7670 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
7671 | if (i.tm.operand_types[op].bitfield.xmmword | |
7672 | && (i.tm.opcode_modifier.evex == EVEXDYN | |
7673 | || (!i.tm.opcode_modifier.evex | |
7674 | && is_evex_encoding (&i.tm)))) | |
7675 | i.tm.opcode_modifier.evex = EVEX128; | |
7676 | } | |
7677 | else if (i.tm.operand_types[op].bitfield.ymmword | |
7678 | && !i.tm.operand_types[op].bitfield.xmmword | |
7679 | && (i.tm.opcode_modifier.evex == EVEXDYN | |
7680 | || (!i.tm.opcode_modifier.evex | |
7681 | && is_evex_encoding (&i.tm)))) | |
7682 | i.tm.opcode_modifier.evex = EVEX256; | |
7683 | } | |
7684 | else if (is_evex_encoding (&i.tm) | |
7685 | && !cpu_arch_flags.bitfield.cpuavx512vl) | |
6c0946d0 | 7686 | { |
b9915cbc JB |
7687 | if (i.tm.operand_types[op].bitfield.ymmword) |
7688 | i.tm.operand_types[op].bitfield.xmmword = 0; | |
7689 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7690 | i.tm.operand_types[op].bitfield.ymmword = 0; | |
7691 | if (!i.tm.opcode_modifier.evex | |
7692 | || i.tm.opcode_modifier.evex == EVEXDYN) | |
7693 | i.tm.opcode_modifier.evex = EVEX512; | |
7694 | } | |
6c0946d0 | 7695 | |
b9915cbc JB |
7696 | if (i.tm.operand_types[op].bitfield.xmmword |
7697 | + i.tm.operand_types[op].bitfield.ymmword | |
7698 | + i.tm.operand_types[op].bitfield.zmmword < 2) | |
7699 | continue; | |
6c0946d0 | 7700 | |
b9915cbc JB |
7701 | /* Any properly sized operand disambiguates the insn. */ |
7702 | if (i.types[op].bitfield.xmmword | |
7703 | || i.types[op].bitfield.ymmword | |
7704 | || i.types[op].bitfield.zmmword) | |
7705 | { | |
7706 | suffixes &= ~(7 << 6); | |
7707 | evex = 0; | |
7708 | break; | |
7709 | } | |
6c0946d0 | 7710 | |
b9915cbc JB |
7711 | if ((i.flags[op] & Operand_Mem) |
7712 | && i.tm.operand_types[op].bitfield.unspecified) | |
7713 | { | |
7714 | if (i.tm.operand_types[op].bitfield.xmmword) | |
7715 | suffixes |= 1 << 6; | |
7716 | if (i.tm.operand_types[op].bitfield.ymmword) | |
7717 | suffixes |= 1 << 7; | |
7718 | if (i.tm.operand_types[op].bitfield.zmmword) | |
7719 | suffixes |= 1 << 8; | |
7720 | if (is_evex_encoding (&i.tm)) | |
7721 | evex = EVEX512; | |
6c0946d0 JB |
7722 | } |
7723 | } | |
7724 | } | |
7725 | ||
7726 | /* Are multiple suffixes / operand sizes allowed? */ | |
c006a730 | 7727 | if (suffixes & (suffixes - 1)) |
9306ca4a | 7728 | { |
873494c8 | 7729 | if (intel_syntax |
3cd7f3e3 | 7730 | && (i.tm.opcode_modifier.mnemonicsize != DEFAULTSIZE |
873494c8 | 7731 | || operand_check == check_error)) |
9306ca4a | 7732 | { |
76d3f746 | 7733 | as_bad (_("ambiguous operand size for `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
7734 | return 0; |
7735 | } | |
c006a730 | 7736 | if (operand_check == check_error) |
9306ca4a | 7737 | { |
c006a730 | 7738 | as_bad (_("no instruction mnemonic suffix given and " |
76d3f746 | 7739 | "no register operands; can't size `%s'"), insn_name (&i.tm)); |
9306ca4a JB |
7740 | return 0; |
7741 | } | |
c006a730 | 7742 | if (operand_check == check_warning) |
873494c8 JB |
7743 | as_warn (_("%s; using default for `%s'"), |
7744 | intel_syntax | |
7745 | ? _("ambiguous operand size") | |
7746 | : _("no instruction mnemonic suffix given and " | |
7747 | "no register operands"), | |
76d3f746 | 7748 | insn_name (&i.tm)); |
c006a730 JB |
7749 | |
7750 | if (i.tm.opcode_modifier.floatmf) | |
7751 | i.suffix = SHORT_MNEM_SUFFIX; | |
389d00a5 | 7752 | else if (is_movx) |
65fca059 | 7753 | /* handled below */; |
6c0946d0 JB |
7754 | else if (evex) |
7755 | i.tm.opcode_modifier.evex = evex; | |
c006a730 JB |
7756 | else if (flag_code == CODE_16BIT) |
7757 | i.suffix = WORD_MNEM_SUFFIX; | |
1a035124 | 7758 | else if (!i.tm.opcode_modifier.no_lsuf) |
c006a730 | 7759 | i.suffix = LONG_MNEM_SUFFIX; |
1a035124 JB |
7760 | else |
7761 | i.suffix = QWORD_MNEM_SUFFIX; | |
9306ca4a | 7762 | } |
29b0f896 | 7763 | } |
252b5132 | 7764 | |
389d00a5 | 7765 | if (is_movx) |
65fca059 JB |
7766 | { |
7767 | /* In Intel syntax, movsx/movzx must have a "suffix" (checked above). | |
7768 | In AT&T syntax, if there is no suffix (warned about above), the default | |
7769 | will be byte extension. */ | |
7770 | if (i.tm.opcode_modifier.w && i.suffix && i.suffix != BYTE_MNEM_SUFFIX) | |
7771 | i.tm.base_opcode |= 1; | |
7772 | ||
7773 | /* For further processing, the suffix should represent the destination | |
7774 | (register). This is already the case when one was used with | |
7775 | mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was | |
7776 | no suffix to begin with. */ | |
7777 | if (i.tm.opcode_modifier.w || i.tm.base_opcode == 0x63 || !i.suffix) | |
7778 | { | |
7779 | if (i.types[1].bitfield.word) | |
7780 | i.suffix = WORD_MNEM_SUFFIX; | |
7781 | else if (i.types[1].bitfield.qword) | |
7782 | i.suffix = QWORD_MNEM_SUFFIX; | |
7783 | else | |
7784 | i.suffix = LONG_MNEM_SUFFIX; | |
7785 | ||
7786 | i.tm.opcode_modifier.w = 0; | |
7787 | } | |
7788 | } | |
7789 | ||
50128d0c JB |
7790 | if (!i.tm.opcode_modifier.modrm && i.reg_operands && i.tm.operands < 3) |
7791 | i.short_form = (i.tm.operand_types[0].bitfield.class == Reg) | |
7792 | != (i.tm.operand_types[1].bitfield.class == Reg); | |
7793 | ||
d2224064 JB |
7794 | /* Change the opcode based on the operand size given by i.suffix. */ |
7795 | switch (i.suffix) | |
29b0f896 | 7796 | { |
d2224064 JB |
7797 | /* Size floating point instruction. */ |
7798 | case LONG_MNEM_SUFFIX: | |
7799 | if (i.tm.opcode_modifier.floatmf) | |
7800 | { | |
7801 | i.tm.base_opcode ^= 4; | |
7802 | break; | |
7803 | } | |
7804 | /* fall through */ | |
7805 | case WORD_MNEM_SUFFIX: | |
7806 | case QWORD_MNEM_SUFFIX: | |
29b0f896 | 7807 | /* It's not a byte, select word/dword operation. */ |
40fb9820 | 7808 | if (i.tm.opcode_modifier.w) |
29b0f896 | 7809 | { |
50128d0c | 7810 | if (i.short_form) |
29b0f896 AM |
7811 | i.tm.base_opcode |= 8; |
7812 | else | |
7813 | i.tm.base_opcode |= 1; | |
7814 | } | |
d2224064 JB |
7815 | /* fall through */ |
7816 | case SHORT_MNEM_SUFFIX: | |
29b0f896 AM |
7817 | /* Now select between word & dword operations via the operand |
7818 | size prefix, except for instructions that will ignore this | |
7819 | prefix anyway. */ | |
c8f8eebc | 7820 | if (i.suffix != QWORD_MNEM_SUFFIX |
3cd7f3e3 | 7821 | && i.tm.opcode_modifier.mnemonicsize != IGNORESIZE |
c8f8eebc JB |
7822 | && !i.tm.opcode_modifier.floatmf |
7823 | && !is_any_vex_encoding (&i.tm) | |
7824 | && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) | |
7825 | || (flag_code == CODE_64BIT | |
7826 | && i.tm.opcode_modifier.jump == JUMP_BYTE))) | |
24eab124 AM |
7827 | { |
7828 | unsigned int prefix = DATA_PREFIX_OPCODE; | |
543613e9 | 7829 | |
0cfa3eb3 | 7830 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) /* jcxz, loop */ |
29b0f896 | 7831 | prefix = ADDR_PREFIX_OPCODE; |
252b5132 | 7832 | |
29b0f896 AM |
7833 | if (!add_prefix (prefix)) |
7834 | return 0; | |
24eab124 | 7835 | } |
252b5132 | 7836 | |
29b0f896 AM |
7837 | /* Set mode64 for an operand. */ |
7838 | if (i.suffix == QWORD_MNEM_SUFFIX | |
9146926a | 7839 | && flag_code == CODE_64BIT |
d2224064 | 7840 | && !i.tm.opcode_modifier.norex64 |
4ed21b58 | 7841 | && !i.tm.opcode_modifier.vexw |
46e883c5 | 7842 | /* Special case for xchg %rax,%rax. It is NOP and doesn't |
d2224064 JB |
7843 | need rex64. */ |
7844 | && ! (i.operands == 2 | |
7845 | && i.tm.base_opcode == 0x90 | |
ddb62495 | 7846 | && i.tm.opcode_space == SPACE_BASE |
75e5731b JB |
7847 | && i.types[0].bitfield.instance == Accum |
7848 | && i.types[0].bitfield.qword | |
44732014 | 7849 | && i.types[1].bitfield.instance == Accum)) |
d2224064 | 7850 | i.rex |= REX_W; |
3e73aa7c | 7851 | |
d2224064 | 7852 | break; |
8bbb3ad8 JB |
7853 | |
7854 | case 0: | |
f9a6a8f0 | 7855 | /* Select word/dword/qword operation with explicit data sizing prefix |
8bbb3ad8 JB |
7856 | when there are no suitable register operands. */ |
7857 | if (i.tm.opcode_modifier.w | |
7858 | && (i.prefix[DATA_PREFIX] || (i.prefix[REX_PREFIX] & REX_W)) | |
7859 | && (!i.reg_operands | |
7860 | || (i.reg_operands == 1 | |
7861 | /* ShiftCount */ | |
7862 | && (i.tm.operand_types[0].bitfield.instance == RegC | |
7863 | /* InOutPortReg */ | |
7864 | || i.tm.operand_types[0].bitfield.instance == RegD | |
7865 | || i.tm.operand_types[1].bitfield.instance == RegD | |
7fc69528 | 7866 | || i.tm.mnem_off == MN_crc32)))) |
8bbb3ad8 JB |
7867 | i.tm.base_opcode |= 1; |
7868 | break; | |
29b0f896 | 7869 | } |
7ecd2f8b | 7870 | |
255571cd | 7871 | if (i.tm.opcode_modifier.operandconstraint == ADDR_PREFIX_OP_REG) |
c0a30a9f | 7872 | { |
c8f8eebc JB |
7873 | gas_assert (!i.suffix); |
7874 | gas_assert (i.reg_operands); | |
c0a30a9f | 7875 | |
c8f8eebc JB |
7876 | if (i.tm.operand_types[0].bitfield.instance == Accum |
7877 | || i.operands == 1) | |
7878 | { | |
7879 | /* The address size override prefix changes the size of the | |
7880 | first operand. */ | |
7881 | if (flag_code == CODE_64BIT | |
7882 | && i.op[0].regs->reg_type.bitfield.word) | |
7883 | { | |
7884 | as_bad (_("16-bit addressing unavailable for `%s'"), | |
76d3f746 | 7885 | insn_name (&i.tm)); |
c8f8eebc JB |
7886 | return 0; |
7887 | } | |
7888 | ||
7889 | if ((flag_code == CODE_32BIT | |
7890 | ? i.op[0].regs->reg_type.bitfield.word | |
7891 | : i.op[0].regs->reg_type.bitfield.dword) | |
7892 | && !add_prefix (ADDR_PREFIX_OPCODE)) | |
7893 | return 0; | |
7894 | } | |
c0a30a9f L |
7895 | else |
7896 | { | |
c8f8eebc JB |
7897 | /* Check invalid register operand when the address size override |
7898 | prefix changes the size of register operands. */ | |
7899 | unsigned int op; | |
7900 | enum { need_word, need_dword, need_qword } need; | |
7901 | ||
27f13469 | 7902 | /* Check the register operand for the address size prefix if |
b3a3496f | 7903 | the memory operand has no real registers, like symbol, DISP |
829f3fe1 | 7904 | or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */ |
27f13469 L |
7905 | if (i.mem_operands == 1 |
7906 | && i.reg_operands == 1 | |
7907 | && i.operands == 2 | |
27f13469 | 7908 | && i.types[1].bitfield.class == Reg |
b3a3496f L |
7909 | && (flag_code == CODE_32BIT |
7910 | ? i.op[1].regs->reg_type.bitfield.word | |
7911 | : i.op[1].regs->reg_type.bitfield.dword) | |
7912 | && ((i.base_reg == NULL && i.index_reg == NULL) | |
829f3fe1 JB |
7913 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
7914 | || (x86_elf_abi == X86_64_X32_ABI | |
7915 | && i.base_reg | |
b3a3496f L |
7916 | && i.base_reg->reg_num == RegIP |
7917 | && i.base_reg->reg_type.bitfield.qword)) | |
829f3fe1 JB |
7918 | #else |
7919 | || 0) | |
7920 | #endif | |
27f13469 L |
7921 | && !add_prefix (ADDR_PREFIX_OPCODE)) |
7922 | return 0; | |
7923 | ||
c8f8eebc JB |
7924 | if (flag_code == CODE_32BIT) |
7925 | need = i.prefix[ADDR_PREFIX] ? need_word : need_dword; | |
7926 | else if (i.prefix[ADDR_PREFIX]) | |
c0a30a9f L |
7927 | need = need_dword; |
7928 | else | |
7929 | need = flag_code == CODE_64BIT ? need_qword : need_word; | |
c0a30a9f | 7930 | |
c8f8eebc JB |
7931 | for (op = 0; op < i.operands; op++) |
7932 | { | |
7933 | if (i.types[op].bitfield.class != Reg) | |
7934 | continue; | |
7935 | ||
7936 | switch (need) | |
7937 | { | |
7938 | case need_word: | |
7939 | if (i.op[op].regs->reg_type.bitfield.word) | |
7940 | continue; | |
7941 | break; | |
7942 | case need_dword: | |
7943 | if (i.op[op].regs->reg_type.bitfield.dword) | |
7944 | continue; | |
7945 | break; | |
7946 | case need_qword: | |
7947 | if (i.op[op].regs->reg_type.bitfield.qword) | |
7948 | continue; | |
7949 | break; | |
7950 | } | |
7951 | ||
7952 | as_bad (_("invalid register operand size for `%s'"), | |
76d3f746 | 7953 | insn_name (&i.tm)); |
c8f8eebc JB |
7954 | return 0; |
7955 | } | |
7956 | } | |
c0a30a9f L |
7957 | } |
7958 | ||
29b0f896 AM |
7959 | return 1; |
7960 | } | |
3e73aa7c | 7961 | |
29b0f896 | 7962 | static int |
543613e9 | 7963 | check_byte_reg (void) |
29b0f896 AM |
7964 | { |
7965 | int op; | |
543613e9 | 7966 | |
29b0f896 AM |
7967 | for (op = i.operands; --op >= 0;) |
7968 | { | |
dc821c5f | 7969 | /* Skip non-register operands. */ |
bab6aec1 | 7970 | if (i.types[op].bitfield.class != Reg) |
dc821c5f JB |
7971 | continue; |
7972 | ||
29b0f896 AM |
7973 | /* If this is an eight bit register, it's OK. If it's the 16 or |
7974 | 32 bit version of an eight bit register, we will just use the | |
7975 | low portion, and that's OK too. */ | |
dc821c5f | 7976 | if (i.types[op].bitfield.byte) |
29b0f896 AM |
7977 | continue; |
7978 | ||
5a819eb9 | 7979 | /* I/O port address operands are OK too. */ |
75e5731b JB |
7980 | if (i.tm.operand_types[op].bitfield.instance == RegD |
7981 | && i.tm.operand_types[op].bitfield.word) | |
5a819eb9 JB |
7982 | continue; |
7983 | ||
9706160a | 7984 | /* crc32 only wants its source operand checked here. */ |
7fc69528 | 7985 | if (i.tm.mnem_off == MN_crc32 && op != 0) |
9344ff29 L |
7986 | continue; |
7987 | ||
29b0f896 | 7988 | /* Any other register is bad. */ |
73c76375 JB |
7989 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
7990 | register_prefix, i.op[op].regs->reg_name, | |
76d3f746 | 7991 | insn_name (&i.tm), i.suffix); |
73c76375 | 7992 | return 0; |
29b0f896 AM |
7993 | } |
7994 | return 1; | |
7995 | } | |
7996 | ||
7997 | static int | |
e3bb37b5 | 7998 | check_long_reg (void) |
29b0f896 AM |
7999 | { |
8000 | int op; | |
8001 | ||
8002 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 8003 | /* Skip non-register operands. */ |
bab6aec1 | 8004 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 8005 | continue; |
29b0f896 AM |
8006 | /* Reject eight bit registers, except where the template requires |
8007 | them. (eg. movzb) */ | |
dc821c5f | 8008 | else if (i.types[op].bitfield.byte |
bab6aec1 | 8009 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8010 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
8011 | && (i.tm.operand_types[op].bitfield.word |
8012 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 8013 | { |
a540244d L |
8014 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
8015 | register_prefix, | |
29b0f896 | 8016 | i.op[op].regs->reg_name, |
76d3f746 | 8017 | insn_name (&i.tm), |
29b0f896 AM |
8018 | i.suffix); |
8019 | return 0; | |
8020 | } | |
be4c5e58 L |
8021 | /* Error if the e prefix on a general reg is missing. */ |
8022 | else if (i.types[op].bitfield.word | |
bab6aec1 | 8023 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8024 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8025 | && i.tm.operand_types[op].bitfield.dword) |
29b0f896 | 8026 | { |
be4c5e58 L |
8027 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
8028 | register_prefix, i.op[op].regs->reg_name, | |
8029 | i.suffix); | |
8030 | return 0; | |
252b5132 | 8031 | } |
e4630f71 | 8032 | /* Warn if the r prefix on a general reg is present. */ |
dc821c5f | 8033 | else if (i.types[op].bitfield.qword |
bab6aec1 | 8034 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8035 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8036 | && i.tm.operand_types[op].bitfield.dword) |
252b5132 | 8037 | { |
1cb0ab18 JB |
8038 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
8039 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
8040 | return 0; | |
29b0f896 AM |
8041 | } |
8042 | return 1; | |
8043 | } | |
252b5132 | 8044 | |
29b0f896 | 8045 | static int |
e3bb37b5 | 8046 | check_qword_reg (void) |
29b0f896 AM |
8047 | { |
8048 | int op; | |
252b5132 | 8049 | |
29b0f896 | 8050 | for (op = i.operands; --op >= 0; ) |
dc821c5f | 8051 | /* Skip non-register operands. */ |
bab6aec1 | 8052 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 8053 | continue; |
29b0f896 AM |
8054 | /* Reject eight bit registers, except where the template requires |
8055 | them. (eg. movzb) */ | |
dc821c5f | 8056 | else if (i.types[op].bitfield.byte |
bab6aec1 | 8057 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8058 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
8059 | && (i.tm.operand_types[op].bitfield.word |
8060 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 8061 | { |
a540244d L |
8062 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
8063 | register_prefix, | |
29b0f896 | 8064 | i.op[op].regs->reg_name, |
76d3f746 | 8065 | insn_name (&i.tm), |
29b0f896 AM |
8066 | i.suffix); |
8067 | return 0; | |
8068 | } | |
e4630f71 | 8069 | /* Warn if the r prefix on a general reg is missing. */ |
dc821c5f JB |
8070 | else if ((i.types[op].bitfield.word |
8071 | || i.types[op].bitfield.dword) | |
bab6aec1 | 8072 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8073 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8074 | && i.tm.operand_types[op].bitfield.qword) |
29b0f896 AM |
8075 | { |
8076 | /* Prohibit these changes in the 64bit mode, since the | |
8077 | lowering is more complicated. */ | |
1cb0ab18 JB |
8078 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
8079 | register_prefix, i.op[op].regs->reg_name, i.suffix); | |
8080 | return 0; | |
252b5132 | 8081 | } |
29b0f896 AM |
8082 | return 1; |
8083 | } | |
252b5132 | 8084 | |
29b0f896 | 8085 | static int |
e3bb37b5 | 8086 | check_word_reg (void) |
29b0f896 AM |
8087 | { |
8088 | int op; | |
8089 | for (op = i.operands; --op >= 0;) | |
dc821c5f | 8090 | /* Skip non-register operands. */ |
bab6aec1 | 8091 | if (i.types[op].bitfield.class != Reg) |
dc821c5f | 8092 | continue; |
29b0f896 AM |
8093 | /* Reject eight bit registers, except where the template requires |
8094 | them. (eg. movzb) */ | |
dc821c5f | 8095 | else if (i.types[op].bitfield.byte |
bab6aec1 | 8096 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8097 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f JB |
8098 | && (i.tm.operand_types[op].bitfield.word |
8099 | || i.tm.operand_types[op].bitfield.dword)) | |
29b0f896 | 8100 | { |
a540244d L |
8101 | as_bad (_("`%s%s' not allowed with `%s%c'"), |
8102 | register_prefix, | |
29b0f896 | 8103 | i.op[op].regs->reg_name, |
76d3f746 | 8104 | insn_name (&i.tm), |
29b0f896 AM |
8105 | i.suffix); |
8106 | return 0; | |
8107 | } | |
9706160a JB |
8108 | /* Error if the e or r prefix on a general reg is present. */ |
8109 | else if ((i.types[op].bitfield.dword | |
dc821c5f | 8110 | || i.types[op].bitfield.qword) |
bab6aec1 | 8111 | && (i.tm.operand_types[op].bitfield.class == Reg |
75e5731b | 8112 | || i.tm.operand_types[op].bitfield.instance == Accum) |
dc821c5f | 8113 | && i.tm.operand_types[op].bitfield.word) |
252b5132 | 8114 | { |
9706160a JB |
8115 | as_bad (_("incorrect register `%s%s' used with `%c' suffix"), |
8116 | register_prefix, i.op[op].regs->reg_name, | |
8117 | i.suffix); | |
8118 | return 0; | |
29b0f896 AM |
8119 | } |
8120 | return 1; | |
8121 | } | |
252b5132 | 8122 | |
29b0f896 | 8123 | static int |
40fb9820 | 8124 | update_imm (unsigned int j) |
29b0f896 | 8125 | { |
bc0844ae | 8126 | i386_operand_type overlap = i.types[j]; |
c34d1cc9 JB |
8127 | |
8128 | if (i.tm.operand_types[j].bitfield.imm8 | |
8129 | && i.tm.operand_types[j].bitfield.imm8s | |
8130 | && overlap.bitfield.imm8 && overlap.bitfield.imm8s) | |
8131 | { | |
8132 | /* This combination is used on 8-bit immediates where e.g. $~0 is | |
8133 | desirable to permit. We're past operand type matching, so simply | |
8134 | put things back in the shape they were before introducing the | |
8135 | distinction between Imm8, Imm8S, and Imm8|Imm8S. */ | |
8136 | overlap.bitfield.imm8s = 0; | |
8137 | } | |
8138 | ||
be1643ff JB |
8139 | if (overlap.bitfield.imm8 |
8140 | + overlap.bitfield.imm8s | |
8141 | + overlap.bitfield.imm16 | |
8142 | + overlap.bitfield.imm32 | |
8143 | + overlap.bitfield.imm32s | |
8144 | + overlap.bitfield.imm64 > 1) | |
29b0f896 | 8145 | { |
05909f23 JB |
8146 | static const i386_operand_type imm16 = { .bitfield = { .imm16 = 1 } }; |
8147 | static const i386_operand_type imm32 = { .bitfield = { .imm32 = 1 } }; | |
8148 | static const i386_operand_type imm32s = { .bitfield = { .imm32s = 1 } }; | |
8149 | static const i386_operand_type imm16_32 = { .bitfield = | |
8150 | { .imm16 = 1, .imm32 = 1 } | |
8151 | }; | |
8152 | static const i386_operand_type imm16_32s = { .bitfield = | |
8153 | { .imm16 = 1, .imm32s = 1 } | |
8154 | }; | |
8155 | static const i386_operand_type imm16_32_32s = { .bitfield = | |
8156 | { .imm16 = 1, .imm32 = 1, .imm32s = 1 } | |
8157 | }; | |
8158 | ||
29b0f896 AM |
8159 | if (i.suffix) |
8160 | { | |
40fb9820 L |
8161 | i386_operand_type temp; |
8162 | ||
0dfbf9d7 | 8163 | operand_type_set (&temp, 0); |
7ab9ffdd | 8164 | if (i.suffix == BYTE_MNEM_SUFFIX) |
40fb9820 L |
8165 | { |
8166 | temp.bitfield.imm8 = overlap.bitfield.imm8; | |
8167 | temp.bitfield.imm8s = overlap.bitfield.imm8s; | |
8168 | } | |
8169 | else if (i.suffix == WORD_MNEM_SUFFIX) | |
8170 | temp.bitfield.imm16 = overlap.bitfield.imm16; | |
8171 | else if (i.suffix == QWORD_MNEM_SUFFIX) | |
8172 | { | |
8173 | temp.bitfield.imm64 = overlap.bitfield.imm64; | |
8174 | temp.bitfield.imm32s = overlap.bitfield.imm32s; | |
8175 | } | |
8176 | else | |
8177 | temp.bitfield.imm32 = overlap.bitfield.imm32; | |
8178 | overlap = temp; | |
29b0f896 | 8179 | } |
0dfbf9d7 L |
8180 | else if (operand_type_equal (&overlap, &imm16_32_32s) |
8181 | || operand_type_equal (&overlap, &imm16_32) | |
8182 | || operand_type_equal (&overlap, &imm16_32s)) | |
29b0f896 | 8183 | { |
40fb9820 | 8184 | if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) |
65da13b5 | 8185 | overlap = imm16; |
40fb9820 | 8186 | else |
65da13b5 | 8187 | overlap = imm32s; |
29b0f896 | 8188 | } |
8bbb3ad8 JB |
8189 | else if (i.prefix[REX_PREFIX] & REX_W) |
8190 | overlap = operand_type_and (overlap, imm32s); | |
8191 | else if (i.prefix[DATA_PREFIX]) | |
8192 | overlap = operand_type_and (overlap, | |
8193 | flag_code != CODE_16BIT ? imm16 : imm32); | |
be1643ff JB |
8194 | if (overlap.bitfield.imm8 |
8195 | + overlap.bitfield.imm8s | |
8196 | + overlap.bitfield.imm16 | |
8197 | + overlap.bitfield.imm32 | |
8198 | + overlap.bitfield.imm32s | |
8199 | + overlap.bitfield.imm64 != 1) | |
29b0f896 | 8200 | { |
4eed87de AM |
8201 | as_bad (_("no instruction mnemonic suffix given; " |
8202 | "can't determine immediate size")); | |
29b0f896 AM |
8203 | return 0; |
8204 | } | |
8205 | } | |
40fb9820 | 8206 | i.types[j] = overlap; |
29b0f896 | 8207 | |
40fb9820 L |
8208 | return 1; |
8209 | } | |
8210 | ||
8211 | static int | |
8212 | finalize_imm (void) | |
8213 | { | |
bc0844ae | 8214 | unsigned int j, n; |
29b0f896 | 8215 | |
bc0844ae L |
8216 | /* Update the first 2 immediate operands. */ |
8217 | n = i.operands > 2 ? 2 : i.operands; | |
8218 | if (n) | |
8219 | { | |
8220 | for (j = 0; j < n; j++) | |
8221 | if (update_imm (j) == 0) | |
8222 | return 0; | |
40fb9820 | 8223 | |
bc0844ae L |
8224 | /* The 3rd operand can't be immediate operand. */ |
8225 | gas_assert (operand_type_check (i.types[2], imm) == 0); | |
8226 | } | |
29b0f896 AM |
8227 | |
8228 | return 1; | |
8229 | } | |
8230 | ||
0a3eba42 JB |
8231 | static INLINE void set_rex_vrex (const reg_entry *r, unsigned int rex_bit, |
8232 | bool do_sse2avx) | |
8233 | { | |
8234 | if (r->reg_flags & RegRex) | |
8235 | { | |
8236 | if (i.rex & rex_bit) | |
8237 | as_bad (_("same type of prefix used twice")); | |
8238 | i.rex |= rex_bit; | |
8239 | } | |
8240 | else if (do_sse2avx && (i.rex & rex_bit) && i.vex.register_specifier) | |
8241 | { | |
8242 | gas_assert (i.vex.register_specifier == r); | |
8243 | i.vex.register_specifier += 8; | |
8244 | } | |
8245 | ||
8246 | if (r->reg_flags & RegVRex) | |
8247 | i.vrex |= rex_bit; | |
8248 | } | |
8249 | ||
29b0f896 | 8250 | static int |
e3bb37b5 | 8251 | process_operands (void) |
29b0f896 AM |
8252 | { |
8253 | /* Default segment register this instruction will use for memory | |
8254 | accesses. 0 means unknown. This is only for optimizing out | |
8255 | unnecessary segment overrides. */ | |
5e042380 | 8256 | const reg_entry *default_seg = NULL; |
29b0f896 | 8257 | |
31b4cda3 JB |
8258 | /* We only need to check those implicit registers for instructions |
8259 | with 3 operands or less. */ | |
8260 | if (i.operands <= 3) | |
8261 | for (unsigned int j = 0; j < i.operands; j++) | |
8262 | if (i.types[j].bitfield.instance != InstanceNone) | |
8263 | i.reg_operands--; | |
8264 | ||
a5aeccd9 JB |
8265 | if (i.tm.opcode_modifier.sse2avx) |
8266 | { | |
8267 | /* Legacy encoded insns allow explicit REX prefixes, so these prefixes | |
8268 | need converting. */ | |
8269 | i.rex |= i.prefix[REX_PREFIX] & (REX_W | REX_R | REX_X | REX_B); | |
8270 | i.prefix[REX_PREFIX] = 0; | |
8271 | i.rex_encoding = 0; | |
8272 | } | |
c423d21a JB |
8273 | /* ImmExt should be processed after SSE2AVX. */ |
8274 | else if (i.tm.opcode_modifier.immext) | |
8275 | process_immext (); | |
a5aeccd9 | 8276 | |
ecb96e55 JB |
8277 | /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg, |
8278 | not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a | |
8279 | new destination operand here, while converting the source one to register | |
8280 | number 0. */ | |
8281 | if (i.tm.mnem_off == MN_tilezero) | |
8282 | { | |
8283 | i.op[1].regs = i.op[0].regs; | |
8284 | i.op[0].regs -= i.op[0].regs->reg_num; | |
8285 | i.types[1] = i.types[0]; | |
8286 | i.tm.operand_types[1] = i.tm.operand_types[0]; | |
8287 | i.flags[1] = i.flags[0]; | |
8288 | i.operands++; | |
8289 | i.reg_operands++; | |
8290 | i.tm.operands++; | |
8291 | } | |
8292 | ||
2426c15f | 8293 | if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv) |
29b0f896 | 8294 | { |
05909f23 JB |
8295 | static const i386_operand_type regxmm = { |
8296 | .bitfield = { .class = RegSIMD, .xmmword = 1 } | |
8297 | }; | |
91d6fa6a NC |
8298 | unsigned int dupl = i.operands; |
8299 | unsigned int dest = dupl - 1; | |
9fcfb3d7 L |
8300 | unsigned int j; |
8301 | ||
c0f3af97 | 8302 | /* The destination must be an xmm register. */ |
9c2799c2 | 8303 | gas_assert (i.reg_operands |
91d6fa6a | 8304 | && MAX_OPERANDS > dupl |
7ab9ffdd | 8305 | && operand_type_equal (&i.types[dest], ®xmm)); |
c0f3af97 | 8306 | |
75e5731b | 8307 | if (i.tm.operand_types[0].bitfield.instance == Accum |
1b54b8d7 | 8308 | && i.tm.operand_types[0].bitfield.xmmword) |
e2ec9d29 | 8309 | { |
95dfdd85 JB |
8310 | /* Keep xmm0 for instructions with VEX prefix and 3 |
8311 | sources. */ | |
8312 | i.tm.operand_types[0].bitfield.instance = InstanceNone; | |
8313 | i.tm.operand_types[0].bitfield.class = RegSIMD; | |
31b4cda3 | 8314 | i.reg_operands++; |
95dfdd85 | 8315 | goto duplicate; |
c0f3af97 | 8316 | } |
95dfdd85 JB |
8317 | |
8318 | if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_1ST_XMM0) | |
7ab9ffdd | 8319 | { |
aa180741 | 8320 | gas_assert ((MAX_OPERANDS - 1) > dupl); |
c0f3af97 L |
8321 | |
8322 | /* Add the implicit xmm0 for instructions with VEX prefix | |
8323 | and 3 sources. */ | |
8324 | for (j = i.operands; j > 0; j--) | |
8325 | { | |
8326 | i.op[j] = i.op[j - 1]; | |
8327 | i.types[j] = i.types[j - 1]; | |
8328 | i.tm.operand_types[j] = i.tm.operand_types[j - 1]; | |
8dc0818e | 8329 | i.flags[j] = i.flags[j - 1]; |
c0f3af97 L |
8330 | } |
8331 | i.op[0].regs | |
629310ab | 8332 | = (const reg_entry *) str_hash_find (reg_hash, "xmm0"); |
7ab9ffdd | 8333 | i.types[0] = regxmm; |
c0f3af97 L |
8334 | i.tm.operand_types[0] = regxmm; |
8335 | ||
8336 | i.operands += 2; | |
8337 | i.reg_operands += 2; | |
8338 | i.tm.operands += 2; | |
8339 | ||
91d6fa6a | 8340 | dupl++; |
c0f3af97 | 8341 | dest++; |
91d6fa6a NC |
8342 | i.op[dupl] = i.op[dest]; |
8343 | i.types[dupl] = i.types[dest]; | |
8344 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 8345 | i.flags[dupl] = i.flags[dest]; |
e2ec9d29 | 8346 | } |
c0f3af97 L |
8347 | else |
8348 | { | |
dc1e8a47 | 8349 | duplicate: |
c0f3af97 L |
8350 | i.operands++; |
8351 | i.reg_operands++; | |
8352 | i.tm.operands++; | |
8353 | ||
91d6fa6a NC |
8354 | i.op[dupl] = i.op[dest]; |
8355 | i.types[dupl] = i.types[dest]; | |
8356 | i.tm.operand_types[dupl] = i.tm.operand_types[dest]; | |
8dc0818e | 8357 | i.flags[dupl] = i.flags[dest]; |
c0f3af97 L |
8358 | } |
8359 | ||
8360 | if (i.tm.opcode_modifier.immext) | |
8361 | process_immext (); | |
8362 | } | |
75e5731b | 8363 | else if (i.tm.operand_types[0].bitfield.instance == Accum |
bd782808 | 8364 | && i.tm.opcode_modifier.modrm) |
c0f3af97 L |
8365 | { |
8366 | unsigned int j; | |
8367 | ||
9fcfb3d7 L |
8368 | for (j = 1; j < i.operands; j++) |
8369 | { | |
8370 | i.op[j - 1] = i.op[j]; | |
8371 | i.types[j - 1] = i.types[j]; | |
8372 | ||
8373 | /* We need to adjust fields in i.tm since they are used by | |
8374 | build_modrm_byte. */ | |
8375 | i.tm.operand_types [j - 1] = i.tm.operand_types [j]; | |
8dc0818e JB |
8376 | |
8377 | i.flags[j - 1] = i.flags[j]; | |
9fcfb3d7 L |
8378 | } |
8379 | ||
31b4cda3 JB |
8380 | /* No adjustment to i.reg_operands: This was already done at the top |
8381 | of the function. */ | |
e2ec9d29 | 8382 | i.operands--; |
e2ec9d29 L |
8383 | i.tm.operands--; |
8384 | } | |
255571cd | 8385 | else if (i.tm.opcode_modifier.operandconstraint == IMPLICIT_QUAD_GROUP) |
920d2ddc | 8386 | { |
a477a8c4 JB |
8387 | unsigned int regnum, first_reg_in_group, last_reg_in_group; |
8388 | ||
920d2ddc | 8389 | /* The second operand must be {x,y,z}mmN, where N is a multiple of 4. */ |
3528c362 | 8390 | gas_assert (i.operands >= 2 && i.types[1].bitfield.class == RegSIMD); |
a477a8c4 JB |
8391 | regnum = register_number (i.op[1].regs); |
8392 | first_reg_in_group = regnum & ~3; | |
8393 | last_reg_in_group = first_reg_in_group + 3; | |
8394 | if (regnum != first_reg_in_group) | |
8395 | as_warn (_("source register `%s%s' implicitly denotes" | |
8396 | " `%s%.3s%u' to `%s%.3s%u' source group in `%s'"), | |
8397 | register_prefix, i.op[1].regs->reg_name, | |
8398 | register_prefix, i.op[1].regs->reg_name, first_reg_in_group, | |
8399 | register_prefix, i.op[1].regs->reg_name, last_reg_in_group, | |
76d3f746 | 8400 | insn_name (&i.tm)); |
a477a8c4 | 8401 | } |
255571cd | 8402 | else if (i.tm.opcode_modifier.operandconstraint == REG_KLUDGE) |
e2ec9d29 L |
8403 | { |
8404 | /* The imul $imm, %reg instruction is converted into | |
8405 | imul $imm, %reg, %reg, and the clr %reg instruction | |
8406 | is converted into xor %reg, %reg. */ | |
8407 | ||
8408 | unsigned int first_reg_op; | |
8409 | ||
8410 | if (operand_type_check (i.types[0], reg)) | |
8411 | first_reg_op = 0; | |
8412 | else | |
8413 | first_reg_op = 1; | |
8414 | /* Pretend we saw the extra register operand. */ | |
9c2799c2 | 8415 | gas_assert (i.reg_operands == 1 |
7ab9ffdd | 8416 | && i.op[first_reg_op + 1].regs == 0); |
e2ec9d29 L |
8417 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
8418 | i.types[first_reg_op + 1] = i.types[first_reg_op]; | |
8419 | i.operands++; | |
8420 | i.reg_operands++; | |
29b0f896 AM |
8421 | } |
8422 | ||
85b80b0f | 8423 | if (i.tm.opcode_modifier.modrm) |
29b0f896 AM |
8424 | { |
8425 | /* The opcode is completed (modulo i.tm.extension_opcode which | |
52271982 AM |
8426 | must be put into the modrm byte). Now, we make the modrm and |
8427 | index base bytes based on all the info we've collected. */ | |
29b0f896 AM |
8428 | |
8429 | default_seg = build_modrm_byte (); | |
bd782808 JB |
8430 | |
8431 | if (!quiet_warnings && i.tm.opcode_modifier.operandconstraint == UGH) | |
8432 | { | |
8433 | /* Warn about some common errors, but press on regardless. */ | |
8434 | if (i.operands == 2) | |
8435 | { | |
8436 | /* Reversed arguments on faddp or fmulp. */ | |
8437 | as_warn (_("translating to `%s %s%s,%s%s'"), insn_name (&i.tm), | |
8438 | register_prefix, i.op[!intel_syntax].regs->reg_name, | |
8439 | register_prefix, i.op[intel_syntax].regs->reg_name); | |
8440 | } | |
8441 | else if (i.tm.opcode_modifier.mnemonicsize == IGNORESIZE) | |
8442 | { | |
8443 | /* Extraneous `l' suffix on fp insn. */ | |
8444 | as_warn (_("translating to `%s %s%s'"), insn_name (&i.tm), | |
8445 | register_prefix, i.op[0].regs->reg_name); | |
8446 | } | |
8447 | } | |
29b0f896 | 8448 | } |
0ff3b7d0 | 8449 | else if (i.types[0].bitfield.class == SReg && !dot_insn ()) |
85b80b0f JB |
8450 | { |
8451 | if (flag_code != CODE_64BIT | |
8452 | ? i.tm.base_opcode == POP_SEG_SHORT | |
8453 | && i.op[0].regs->reg_num == 1 | |
389d00a5 | 8454 | : (i.tm.base_opcode | 1) == (POP_SEG386_SHORT & 0xff) |
85b80b0f JB |
8455 | && i.op[0].regs->reg_num < 4) |
8456 | { | |
8457 | as_bad (_("you can't `%s %s%s'"), | |
76d3f746 | 8458 | insn_name (&i.tm), register_prefix, i.op[0].regs->reg_name); |
85b80b0f JB |
8459 | return 0; |
8460 | } | |
389d00a5 | 8461 | if (i.op[0].regs->reg_num > 3 |
ddb62495 | 8462 | && i.tm.opcode_space == SPACE_BASE ) |
85b80b0f | 8463 | { |
389d00a5 | 8464 | i.tm.base_opcode ^= (POP_SEG_SHORT ^ POP_SEG386_SHORT) & 0xff; |
ddb62495 | 8465 | i.tm.opcode_space = SPACE_0F; |
85b80b0f JB |
8466 | } |
8467 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); | |
8468 | } | |
ddb62495 | 8469 | else if (i.tm.opcode_space == SPACE_BASE |
389d00a5 | 8470 | && (i.tm.base_opcode & ~3) == MOV_AX_DISP32) |
29b0f896 | 8471 | { |
5e042380 | 8472 | default_seg = reg_ds; |
29b0f896 | 8473 | } |
40fb9820 | 8474 | else if (i.tm.opcode_modifier.isstring) |
29b0f896 AM |
8475 | { |
8476 | /* For the string instructions that allow a segment override | |
8477 | on one of their operands, the default segment is ds. */ | |
5e042380 | 8478 | default_seg = reg_ds; |
29b0f896 | 8479 | } |
50128d0c | 8480 | else if (i.short_form) |
85b80b0f | 8481 | { |
0ff3b7d0 JB |
8482 | /* The register operand is in the 1st or 2nd non-immediate operand. */ |
8483 | const reg_entry *r = i.op[i.imm_operands].regs; | |
85b80b0f | 8484 | |
0ff3b7d0 JB |
8485 | if (!dot_insn () |
8486 | && r->reg_type.bitfield.instance == Accum | |
8487 | && i.op[i.imm_operands + 1].regs) | |
8488 | r = i.op[i.imm_operands + 1].regs; | |
85b80b0f | 8489 | /* Register goes in low 3 bits of opcode. */ |
4943d587 | 8490 | i.tm.base_opcode |= r->reg_num; |
0a3eba42 | 8491 | set_rex_vrex (r, REX_B, false); |
0ff3b7d0 JB |
8492 | |
8493 | if (dot_insn () && i.reg_operands == 2) | |
8494 | { | |
8495 | gas_assert (is_any_vex_encoding (&i.tm) | |
8496 | || i.vec_encoding != vex_encoding_default); | |
8497 | i.vex.register_specifier = i.op[i.operands - 1].regs; | |
8498 | } | |
8499 | } | |
8500 | else if (i.reg_operands == 1 | |
8501 | && !i.flags[i.operands - 1] | |
8502 | && i.tm.operand_types[i.operands - 1].bitfield.instance | |
8503 | == InstanceNone) | |
8504 | { | |
8505 | gas_assert (is_any_vex_encoding (&i.tm) | |
8506 | || i.vec_encoding != vex_encoding_default); | |
8507 | i.vex.register_specifier = i.op[i.operands - 1].regs; | |
85b80b0f | 8508 | } |
29b0f896 | 8509 | |
514a8bb0 | 8510 | if ((i.seg[0] || i.prefix[SEG_PREFIX]) |
7fc69528 | 8511 | && i.tm.mnem_off == MN_lea) |
92334ad2 JB |
8512 | { |
8513 | if (!quiet_warnings) | |
76d3f746 | 8514 | as_warn (_("segment override on `%s' is ineffectual"), insn_name (&i.tm)); |
739d7649 | 8515 | if (optimize && !i.no_optimize) |
92334ad2 JB |
8516 | { |
8517 | i.seg[0] = NULL; | |
8518 | i.prefix[SEG_PREFIX] = 0; | |
8519 | } | |
8520 | } | |
52271982 AM |
8521 | |
8522 | /* If a segment was explicitly specified, and the specified segment | |
b6773884 JB |
8523 | is neither the default nor the one already recorded from a prefix, |
8524 | use an opcode prefix to select it. If we never figured out what | |
8525 | the default segment is, then default_seg will be zero at this | |
8526 | point, and the specified segment prefix will always be used. */ | |
8527 | if (i.seg[0] | |
8528 | && i.seg[0] != default_seg | |
5e042380 | 8529 | && i386_seg_prefixes[i.seg[0]->reg_num] != i.prefix[SEG_PREFIX]) |
29b0f896 | 8530 | { |
5e042380 | 8531 | if (!add_prefix (i386_seg_prefixes[i.seg[0]->reg_num])) |
29b0f896 AM |
8532 | return 0; |
8533 | } | |
8534 | return 1; | |
8535 | } | |
8536 | ||
5e042380 | 8537 | static const reg_entry * |
e3bb37b5 | 8538 | build_modrm_byte (void) |
29b0f896 | 8539 | { |
5e042380 | 8540 | const reg_entry *default_seg = NULL; |
ecb96e55 JB |
8541 | unsigned int source = i.imm_operands - i.tm.opcode_modifier.immext |
8542 | /* Compensate for kludge in md_assemble(). */ | |
8543 | + i.tm.operand_types[0].bitfield.imm1; | |
8544 | unsigned int dest = i.operands - 1 - i.tm.opcode_modifier.immext; | |
8545 | unsigned int v, op, reg_slot = ~0; | |
8546 | ||
8547 | /* Accumulator (in particular %st), shift count (%cl), and alike need | |
8548 | to be skipped just like immediate operands do. */ | |
8549 | if (i.tm.operand_types[source].bitfield.instance) | |
8550 | ++source; | |
8551 | while (i.tm.operand_types[dest].bitfield.instance) | |
8552 | --dest; | |
8553 | ||
8554 | for (op = source; op < i.operands; ++op) | |
8555 | if (i.tm.operand_types[op].bitfield.baseindex) | |
8556 | break; | |
c0f3af97 | 8557 | |
ecb96e55 | 8558 | if (i.reg_operands + i.mem_operands + (i.tm.extension_opcode != None) == 4) |
c0f3af97 | 8559 | { |
4c2c6516 | 8560 | expressionS *exp; |
c0f3af97 | 8561 | |
a683cc34 | 8562 | /* There are 2 kinds of instructions: |
bed3d976 | 8563 | 1. 5 operands: 4 register operands or 3 register operands |
9d3bf266 | 8564 | plus 1 memory operand plus one Imm4 operand, VexXDS, and |
bed3d976 | 8565 | VexW0 or VexW1. The destination must be either XMM, YMM or |
43234a1e | 8566 | ZMM register. |
bed3d976 | 8567 | 2. 4 operands: 4 register operands or 3 register operands |
0ff3b7d0 JB |
8568 | plus 1 memory operand, with VexXDS. |
8569 | 3. Other equivalent combinations when coming from s_insn(). */ | |
eea96d3f | 8570 | gas_assert (i.tm.opcode_modifier.vexvvvv |
0ff3b7d0 JB |
8571 | && i.tm.opcode_modifier.vexw); |
8572 | gas_assert (dot_insn () | |
8573 | || i.tm.operand_types[dest].bitfield.class == RegSIMD); | |
a683cc34 | 8574 | |
ecb96e55 JB |
8575 | /* Of the first two non-immediate operands the one with the template |
8576 | not allowing for a memory one is encoded in the immediate operand. */ | |
8577 | if (source == op) | |
8578 | reg_slot = source + 1; | |
48db9223 | 8579 | else |
ecb96e55 | 8580 | reg_slot = source++; |
48db9223 | 8581 | |
0ff3b7d0 JB |
8582 | if (!dot_insn ()) |
8583 | { | |
8584 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class == RegSIMD); | |
8585 | gas_assert (!(i.op[reg_slot].regs->reg_flags & RegVRex)); | |
8586 | } | |
8587 | else | |
8588 | gas_assert (i.tm.operand_types[reg_slot].bitfield.class != ClassNone); | |
8589 | ||
a683cc34 | 8590 | if (i.imm_operands == 0) |
bed3d976 JB |
8591 | { |
8592 | /* When there is no immediate operand, generate an 8bit | |
8593 | immediate operand to encode the first operand. */ | |
8594 | exp = &im_expressions[i.imm_operands++]; | |
8595 | i.op[i.operands].imms = exp; | |
be1643ff | 8596 | i.types[i.operands].bitfield.imm8 = 1; |
bed3d976 JB |
8597 | i.operands++; |
8598 | ||
bed3d976 | 8599 | exp->X_op = O_constant; |
43234a1e | 8600 | } |
922d8de8 | 8601 | else |
bed3d976 | 8602 | { |
9d3bf266 JB |
8603 | gas_assert (i.imm_operands == 1); |
8604 | gas_assert (fits_in_imm4 (i.op[0].imms->X_add_number)); | |
8605 | gas_assert (!i.tm.opcode_modifier.immext); | |
a683cc34 | 8606 | |
9d3bf266 JB |
8607 | /* Turn on Imm8 again so that output_imm will generate it. */ |
8608 | i.types[0].bitfield.imm8 = 1; | |
bed3d976 | 8609 | |
0ff3b7d0 | 8610 | exp = i.op[0].imms; |
bed3d976 | 8611 | } |
0ff3b7d0 JB |
8612 | exp->X_add_number |= register_number (i.op[reg_slot].regs) |
8613 | << (3 + !(is_evex_encoding (&i.tm) | |
8614 | || i.vec_encoding == vex_encoding_evex)); | |
c0f3af97 | 8615 | } |
f12dc422 | 8616 | |
ecb96e55 JB |
8617 | for (v = source + 1; v < dest; ++v) |
8618 | if (v != reg_slot) | |
8619 | break; | |
8620 | if (v >= dest) | |
8621 | v = ~0; | |
8622 | if (i.tm.extension_opcode != None) | |
8623 | { | |
8624 | if (dest != source) | |
8625 | v = dest; | |
8626 | dest = ~0; | |
8627 | } | |
8628 | gas_assert (source < dest); | |
8629 | if (i.tm.opcode_modifier.operandconstraint == SWAP_SOURCES | |
8630 | && source != op) | |
8631 | { | |
8632 | unsigned int tmp = source; | |
f12dc422 | 8633 | |
ecb96e55 JB |
8634 | source = v; |
8635 | v = tmp; | |
8636 | } | |
29b0f896 | 8637 | |
ecb96e55 JB |
8638 | if (v < MAX_OPERANDS) |
8639 | { | |
8640 | gas_assert (i.tm.opcode_modifier.vexvvvv); | |
8641 | i.vex.register_specifier = i.op[v].regs; | |
29b0f896 | 8642 | } |
c0f3af97 | 8643 | |
ecb96e55 JB |
8644 | if (op < i.operands) |
8645 | { | |
29b0f896 AM |
8646 | if (i.mem_operands) |
8647 | { | |
8648 | unsigned int fake_zero_displacement = 0; | |
4eed87de | 8649 | |
ecb96e55 | 8650 | gas_assert (i.flags[op] & Operand_Mem); |
29b0f896 | 8651 | |
63112cd6 | 8652 | if (i.tm.opcode_modifier.sib) |
6c30d220 | 8653 | { |
260cd341 LC |
8654 | /* The index register of VSIB shouldn't be RegIZ. */ |
8655 | if (i.tm.opcode_modifier.sib != SIBMEM | |
8656 | && i.index_reg->reg_num == RegIZ) | |
6c30d220 L |
8657 | abort (); |
8658 | ||
8659 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8660 | if (!i.base_reg) | |
8661 | { | |
8662 | i.sib.base = NO_BASE_REGISTER; | |
8663 | i.sib.scale = i.log2_scale_factor; | |
2f2be86b | 8664 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 8665 | i.types[op].bitfield.disp32 = 1; |
6c30d220 | 8666 | } |
260cd341 LC |
8667 | |
8668 | /* Since the mandatory SIB always has index register, so | |
8669 | the code logic remains unchanged. The non-mandatory SIB | |
8670 | without index register is allowed and will be handled | |
8671 | later. */ | |
8672 | if (i.index_reg) | |
8673 | { | |
8674 | if (i.index_reg->reg_num == RegIZ) | |
8675 | i.sib.index = NO_INDEX_REGISTER; | |
8676 | else | |
8677 | i.sib.index = i.index_reg->reg_num; | |
5b7c81bd | 8678 | set_rex_vrex (i.index_reg, REX_X, false); |
260cd341 | 8679 | } |
6c30d220 L |
8680 | } |
8681 | ||
5e042380 | 8682 | default_seg = reg_ds; |
29b0f896 AM |
8683 | |
8684 | if (i.base_reg == 0) | |
8685 | { | |
8686 | i.rm.mode = 0; | |
8687 | if (!i.disp_operands) | |
9bb129e8 | 8688 | fake_zero_displacement = 1; |
29b0f896 AM |
8689 | if (i.index_reg == 0) |
8690 | { | |
260cd341 LC |
8691 | /* Both check for VSIB and mandatory non-vector SIB. */ |
8692 | gas_assert (!i.tm.opcode_modifier.sib | |
8693 | || i.tm.opcode_modifier.sib == SIBMEM); | |
29b0f896 | 8694 | /* Operand is just <disp> */ |
2f2be86b | 8695 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
20f0a1fc | 8696 | if (flag_code == CODE_64BIT) |
29b0f896 AM |
8697 | { |
8698 | /* 64bit mode overwrites the 32bit absolute | |
8699 | addressing by RIP relative addressing and | |
8700 | absolute addressing is encoded by one of the | |
8701 | redundant SIB forms. */ | |
8702 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
8703 | i.sib.base = NO_BASE_REGISTER; | |
8704 | i.sib.index = NO_INDEX_REGISTER; | |
a775efc8 | 8705 | i.types[op].bitfield.disp32 = 1; |
20f0a1fc | 8706 | } |
fc225355 L |
8707 | else if ((flag_code == CODE_16BIT) |
8708 | ^ (i.prefix[ADDR_PREFIX] != 0)) | |
20f0a1fc NC |
8709 | { |
8710 | i.rm.regmem = NO_BASE_REGISTER_16; | |
2f2be86b | 8711 | i.types[op].bitfield.disp16 = 1; |
20f0a1fc NC |
8712 | } |
8713 | else | |
8714 | { | |
8715 | i.rm.regmem = NO_BASE_REGISTER; | |
2f2be86b | 8716 | i.types[op].bitfield.disp32 = 1; |
29b0f896 AM |
8717 | } |
8718 | } | |
63112cd6 | 8719 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8720 | { |
6c30d220 | 8721 | /* !i.base_reg && i.index_reg */ |
e968fc9b | 8722 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8723 | i.sib.index = NO_INDEX_REGISTER; |
8724 | else | |
8725 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8726 | i.sib.base = NO_BASE_REGISTER; |
8727 | i.sib.scale = i.log2_scale_factor; | |
8728 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; | |
2f2be86b | 8729 | i.types[op] = operand_type_and_not (i.types[op], anydisp); |
a775efc8 | 8730 | i.types[op].bitfield.disp32 = 1; |
29b0f896 | 8731 | if ((i.index_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8732 | i.rex |= REX_X; |
29b0f896 AM |
8733 | } |
8734 | } | |
8735 | /* RIP addressing for 64bit mode. */ | |
e968fc9b | 8736 | else if (i.base_reg->reg_num == RegIP) |
29b0f896 | 8737 | { |
63112cd6 | 8738 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 | 8739 | i.rm.regmem = NO_BASE_REGISTER; |
40fb9820 L |
8740 | i.types[op].bitfield.disp8 = 0; |
8741 | i.types[op].bitfield.disp16 = 0; | |
a775efc8 | 8742 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 8743 | i.types[op].bitfield.disp64 = 0; |
71903a11 | 8744 | i.flags[op] |= Operand_PCrel; |
20f0a1fc NC |
8745 | if (! i.disp_operands) |
8746 | fake_zero_displacement = 1; | |
29b0f896 | 8747 | } |
dc821c5f | 8748 | else if (i.base_reg->reg_type.bitfield.word) |
29b0f896 | 8749 | { |
63112cd6 | 8750 | gas_assert (!i.tm.opcode_modifier.sib); |
29b0f896 AM |
8751 | switch (i.base_reg->reg_num) |
8752 | { | |
8753 | case 3: /* (%bx) */ | |
8754 | if (i.index_reg == 0) | |
8755 | i.rm.regmem = 7; | |
8756 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ | |
8757 | i.rm.regmem = i.index_reg->reg_num - 6; | |
8758 | break; | |
8759 | case 5: /* (%bp) */ | |
5e042380 | 8760 | default_seg = reg_ss; |
29b0f896 AM |
8761 | if (i.index_reg == 0) |
8762 | { | |
8763 | i.rm.regmem = 6; | |
40fb9820 | 8764 | if (operand_type_check (i.types[op], disp) == 0) |
29b0f896 AM |
8765 | { |
8766 | /* fake (%bp) into 0(%bp) */ | |
41eb8e88 | 8767 | if (i.disp_encoding == disp_encoding_16bit) |
1a02d6b0 L |
8768 | i.types[op].bitfield.disp16 = 1; |
8769 | else | |
8770 | i.types[op].bitfield.disp8 = 1; | |
252b5132 | 8771 | fake_zero_displacement = 1; |
29b0f896 AM |
8772 | } |
8773 | } | |
8774 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ | |
8775 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; | |
8776 | break; | |
8777 | default: /* (%si) -> 4 or (%di) -> 5 */ | |
8778 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; | |
8779 | } | |
41eb8e88 L |
8780 | if (!fake_zero_displacement |
8781 | && !i.disp_operands | |
8782 | && i.disp_encoding) | |
8783 | { | |
8784 | fake_zero_displacement = 1; | |
8785 | if (i.disp_encoding == disp_encoding_8bit) | |
8786 | i.types[op].bitfield.disp8 = 1; | |
8787 | else | |
8788 | i.types[op].bitfield.disp16 = 1; | |
8789 | } | |
29b0f896 AM |
8790 | i.rm.mode = mode_from_disp_size (i.types[op]); |
8791 | } | |
8792 | else /* i.base_reg and 32/64 bit mode */ | |
8793 | { | |
a9aabc23 | 8794 | if (operand_type_check (i.types[op], disp)) |
40fb9820 | 8795 | { |
73053c1f JB |
8796 | i.types[op].bitfield.disp16 = 0; |
8797 | i.types[op].bitfield.disp64 = 0; | |
a775efc8 | 8798 | i.types[op].bitfield.disp32 = 1; |
40fb9820 | 8799 | } |
20f0a1fc | 8800 | |
63112cd6 | 8801 | if (!i.tm.opcode_modifier.sib) |
6c30d220 | 8802 | i.rm.regmem = i.base_reg->reg_num; |
29b0f896 | 8803 | if ((i.base_reg->reg_flags & RegRex) != 0) |
161a04f6 | 8804 | i.rex |= REX_B; |
29b0f896 AM |
8805 | i.sib.base = i.base_reg->reg_num; |
8806 | /* x86-64 ignores REX prefix bit here to avoid decoder | |
8807 | complications. */ | |
848930b2 JB |
8808 | if (!(i.base_reg->reg_flags & RegRex) |
8809 | && (i.base_reg->reg_num == EBP_REG_NUM | |
8810 | || i.base_reg->reg_num == ESP_REG_NUM)) | |
5e042380 | 8811 | default_seg = reg_ss; |
848930b2 | 8812 | if (i.base_reg->reg_num == 5 && i.disp_operands == 0) |
29b0f896 | 8813 | { |
848930b2 | 8814 | fake_zero_displacement = 1; |
1a02d6b0 L |
8815 | if (i.disp_encoding == disp_encoding_32bit) |
8816 | i.types[op].bitfield.disp32 = 1; | |
8817 | else | |
8818 | i.types[op].bitfield.disp8 = 1; | |
29b0f896 AM |
8819 | } |
8820 | i.sib.scale = i.log2_scale_factor; | |
8821 | if (i.index_reg == 0) | |
8822 | { | |
260cd341 LC |
8823 | /* Only check for VSIB. */ |
8824 | gas_assert (i.tm.opcode_modifier.sib != VECSIB128 | |
8825 | && i.tm.opcode_modifier.sib != VECSIB256 | |
8826 | && i.tm.opcode_modifier.sib != VECSIB512); | |
8827 | ||
29b0f896 AM |
8828 | /* <disp>(%esp) becomes two byte modrm with no index |
8829 | register. We've already stored the code for esp | |
8830 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. | |
8831 | Any base register besides %esp will not use the | |
8832 | extra modrm byte. */ | |
8833 | i.sib.index = NO_INDEX_REGISTER; | |
29b0f896 | 8834 | } |
63112cd6 | 8835 | else if (!i.tm.opcode_modifier.sib) |
29b0f896 | 8836 | { |
e968fc9b | 8837 | if (i.index_reg->reg_num == RegIZ) |
db51cc60 L |
8838 | i.sib.index = NO_INDEX_REGISTER; |
8839 | else | |
8840 | i.sib.index = i.index_reg->reg_num; | |
29b0f896 AM |
8841 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; |
8842 | if ((i.index_reg->reg_flags & RegRex) != 0) | |
161a04f6 | 8843 | i.rex |= REX_X; |
29b0f896 | 8844 | } |
67a4f2b7 AO |
8845 | |
8846 | if (i.disp_operands | |
8847 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL | |
8848 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) | |
8849 | i.rm.mode = 0; | |
8850 | else | |
a501d77e L |
8851 | { |
8852 | if (!fake_zero_displacement | |
8853 | && !i.disp_operands | |
8854 | && i.disp_encoding) | |
8855 | { | |
8856 | fake_zero_displacement = 1; | |
8857 | if (i.disp_encoding == disp_encoding_8bit) | |
8858 | i.types[op].bitfield.disp8 = 1; | |
8859 | else | |
8860 | i.types[op].bitfield.disp32 = 1; | |
8861 | } | |
8862 | i.rm.mode = mode_from_disp_size (i.types[op]); | |
8863 | } | |
29b0f896 | 8864 | } |
252b5132 | 8865 | |
29b0f896 AM |
8866 | if (fake_zero_displacement) |
8867 | { | |
8868 | /* Fakes a zero displacement assuming that i.types[op] | |
8869 | holds the correct displacement size. */ | |
8870 | expressionS *exp; | |
8871 | ||
9c2799c2 | 8872 | gas_assert (i.op[op].disps == 0); |
29b0f896 AM |
8873 | exp = &disp_expressions[i.disp_operands++]; |
8874 | i.op[op].disps = exp; | |
8875 | exp->X_op = O_constant; | |
8876 | exp->X_add_number = 0; | |
8877 | exp->X_add_symbol = (symbolS *) 0; | |
8878 | exp->X_op_symbol = (symbolS *) 0; | |
8879 | } | |
8880 | } | |
ecb96e55 JB |
8881 | else |
8882 | { | |
8883 | i.rm.mode = 3; | |
8884 | i.rm.regmem = i.op[op].regs->reg_num; | |
8885 | set_rex_vrex (i.op[op].regs, REX_B, false); | |
8886 | } | |
252b5132 | 8887 | |
ecb96e55 JB |
8888 | if (op == dest) |
8889 | dest = ~0; | |
8890 | if (op == source) | |
8891 | source = ~0; | |
8892 | } | |
8893 | else | |
8894 | { | |
8895 | i.rm.mode = 3; | |
8896 | if (!i.tm.opcode_modifier.regmem) | |
f88c9eb0 | 8897 | { |
ecb96e55 JB |
8898 | gas_assert (source < MAX_OPERANDS); |
8899 | i.rm.regmem = i.op[source].regs->reg_num; | |
8900 | set_rex_vrex (i.op[source].regs, REX_B, | |
8901 | dest >= MAX_OPERANDS && i.tm.opcode_modifier.sse2avx); | |
8902 | source = ~0; | |
f88c9eb0 | 8903 | } |
ecb96e55 | 8904 | else |
29b0f896 | 8905 | { |
ecb96e55 JB |
8906 | gas_assert (dest < MAX_OPERANDS); |
8907 | i.rm.regmem = i.op[dest].regs->reg_num; | |
8908 | set_rex_vrex (i.op[dest].regs, REX_B, i.tm.opcode_modifier.sse2avx); | |
8909 | dest = ~0; | |
29b0f896 | 8910 | } |
ecb96e55 | 8911 | } |
252b5132 | 8912 | |
ecb96e55 JB |
8913 | /* Fill in i.rm.reg field with extension opcode (if any) or the |
8914 | appropriate register. */ | |
8915 | if (i.tm.extension_opcode != None) | |
8916 | i.rm.reg = i.tm.extension_opcode; | |
8917 | else if (!i.tm.opcode_modifier.regmem && dest < MAX_OPERANDS) | |
8918 | { | |
8919 | i.rm.reg = i.op[dest].regs->reg_num; | |
8920 | set_rex_vrex (i.op[dest].regs, REX_R, i.tm.opcode_modifier.sse2avx); | |
8921 | } | |
8922 | else | |
8923 | { | |
8924 | gas_assert (source < MAX_OPERANDS); | |
8925 | i.rm.reg = i.op[source].regs->reg_num; | |
8926 | set_rex_vrex (i.op[source].regs, REX_R, false); | |
29b0f896 | 8927 | } |
ecb96e55 JB |
8928 | |
8929 | if (flag_code != CODE_64BIT && (i.rex & REX_R)) | |
8930 | { | |
8931 | gas_assert (i.types[!i.tm.opcode_modifier.regmem].bitfield.class == RegCR); | |
8932 | i.rex &= ~REX_R; | |
8933 | add_prefix (LOCK_PREFIX_OPCODE); | |
8934 | } | |
8935 | ||
29b0f896 AM |
8936 | return default_seg; |
8937 | } | |
252b5132 | 8938 | |
48ef937e JB |
8939 | static INLINE void |
8940 | frag_opcode_byte (unsigned char byte) | |
8941 | { | |
8942 | if (now_seg != absolute_section) | |
8943 | FRAG_APPEND_1_CHAR (byte); | |
8944 | else | |
8945 | ++abs_section_offset; | |
8946 | } | |
8947 | ||
376cd056 JB |
8948 | static unsigned int |
8949 | flip_code16 (unsigned int code16) | |
8950 | { | |
8951 | gas_assert (i.tm.operands == 1); | |
8952 | ||
8953 | return !(i.prefix[REX_PREFIX] & REX_W) | |
8954 | && (code16 ? i.tm.operand_types[0].bitfield.disp32 | |
376cd056 JB |
8955 | : i.tm.operand_types[0].bitfield.disp16) |
8956 | ? CODE16 : 0; | |
8957 | } | |
8958 | ||
29b0f896 | 8959 | static void |
e3bb37b5 | 8960 | output_branch (void) |
29b0f896 AM |
8961 | { |
8962 | char *p; | |
f8a5c266 | 8963 | int size; |
29b0f896 AM |
8964 | int code16; |
8965 | int prefix; | |
8966 | relax_substateT subtype; | |
8967 | symbolS *sym; | |
8968 | offsetT off; | |
8969 | ||
48ef937e JB |
8970 | if (now_seg == absolute_section) |
8971 | { | |
8972 | as_bad (_("relaxable branches not supported in absolute section")); | |
8973 | return; | |
8974 | } | |
8975 | ||
f8a5c266 | 8976 | code16 = flag_code == CODE_16BIT ? CODE16 : 0; |
1a42a9fe | 8977 | size = i.disp_encoding > disp_encoding_8bit ? BIG : SMALL; |
29b0f896 AM |
8978 | |
8979 | prefix = 0; | |
8980 | if (i.prefix[DATA_PREFIX] != 0) | |
252b5132 | 8981 | { |
29b0f896 AM |
8982 | prefix = 1; |
8983 | i.prefixes -= 1; | |
376cd056 | 8984 | code16 ^= flip_code16(code16); |
252b5132 | 8985 | } |
29b0f896 AM |
8986 | /* Pentium4 branch hints. */ |
8987 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
8988 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
2f66722d | 8989 | { |
29b0f896 AM |
8990 | prefix++; |
8991 | i.prefixes--; | |
8992 | } | |
8993 | if (i.prefix[REX_PREFIX] != 0) | |
8994 | { | |
8995 | prefix++; | |
8996 | i.prefixes--; | |
2f66722d AM |
8997 | } |
8998 | ||
7e8b059b L |
8999 | /* BND prefixed jump. */ |
9000 | if (i.prefix[BND_PREFIX] != 0) | |
9001 | { | |
6cb0a70e JB |
9002 | prefix++; |
9003 | i.prefixes--; | |
7e8b059b L |
9004 | } |
9005 | ||
f2810fe0 | 9006 | if (i.prefixes != 0) |
76d3f746 | 9007 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
29b0f896 AM |
9008 | |
9009 | /* It's always a symbol; End frag & setup for relax. | |
9010 | Make sure there is enough room in this frag for the largest | |
9011 | instruction we may generate in md_convert_frag. This is 2 | |
9012 | bytes for the opcode and room for the prefix and largest | |
9013 | displacement. */ | |
9014 | frag_grow (prefix + 2 + 4); | |
9015 | /* Prefix and 1 opcode byte go in fr_fix. */ | |
9016 | p = frag_more (prefix + 1); | |
9017 | if (i.prefix[DATA_PREFIX] != 0) | |
9018 | *p++ = DATA_PREFIX_OPCODE; | |
9019 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE | |
9020 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) | |
9021 | *p++ = i.prefix[SEG_PREFIX]; | |
6cb0a70e JB |
9022 | if (i.prefix[BND_PREFIX] != 0) |
9023 | *p++ = BND_PREFIX_OPCODE; | |
29b0f896 AM |
9024 | if (i.prefix[REX_PREFIX] != 0) |
9025 | *p++ = i.prefix[REX_PREFIX]; | |
9026 | *p = i.tm.base_opcode; | |
9027 | ||
9028 | if ((unsigned char) *p == JUMP_PC_RELATIVE) | |
f8a5c266 | 9029 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size); |
40fb9820 | 9030 | else if (cpu_arch_flags.bitfield.cpui386) |
f8a5c266 | 9031 | subtype = ENCODE_RELAX_STATE (COND_JUMP, size); |
29b0f896 | 9032 | else |
f8a5c266 | 9033 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, size); |
29b0f896 | 9034 | subtype |= code16; |
3e73aa7c | 9035 | |
29b0f896 AM |
9036 | sym = i.op[0].disps->X_add_symbol; |
9037 | off = i.op[0].disps->X_add_number; | |
3e73aa7c | 9038 | |
29b0f896 AM |
9039 | if (i.op[0].disps->X_op != O_constant |
9040 | && i.op[0].disps->X_op != O_symbol) | |
3e73aa7c | 9041 | { |
29b0f896 AM |
9042 | /* Handle complex expressions. */ |
9043 | sym = make_expr_symbol (i.op[0].disps); | |
9044 | off = 0; | |
9045 | } | |
3e73aa7c | 9046 | |
1ef3994a JB |
9047 | frag_now->tc_frag_data.code64 = flag_code == CODE_64BIT; |
9048 | ||
29b0f896 AM |
9049 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
9050 | Pass reloc in fr_var. */ | |
d258b828 | 9051 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
29b0f896 | 9052 | } |
3e73aa7c | 9053 | |
bd7ab16b L |
9054 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9055 | /* Return TRUE iff PLT32 relocation should be used for branching to | |
9056 | symbol S. */ | |
9057 | ||
5b7c81bd | 9058 | static bool |
bd7ab16b L |
9059 | need_plt32_p (symbolS *s) |
9060 | { | |
9061 | /* PLT32 relocation is ELF only. */ | |
9062 | if (!IS_ELF) | |
5b7c81bd | 9063 | return false; |
bd7ab16b | 9064 | |
a5def729 RO |
9065 | #ifdef TE_SOLARIS |
9066 | /* Don't emit PLT32 relocation on Solaris: neither native linker nor | |
9067 | krtld support it. */ | |
5b7c81bd | 9068 | return false; |
a5def729 RO |
9069 | #endif |
9070 | ||
bd7ab16b L |
9071 | /* Since there is no need to prepare for PLT branch on x86-64, we |
9072 | can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can | |
9073 | be used as a marker for 32-bit PC-relative branches. */ | |
9074 | if (!object_64bit) | |
5b7c81bd | 9075 | return false; |
bd7ab16b | 9076 | |
44365e88 | 9077 | if (s == NULL) |
5b7c81bd | 9078 | return false; |
44365e88 | 9079 | |
bd7ab16b L |
9080 | /* Weak or undefined symbol need PLT32 relocation. */ |
9081 | if (S_IS_WEAK (s) || !S_IS_DEFINED (s)) | |
5b7c81bd | 9082 | return true; |
bd7ab16b L |
9083 | |
9084 | /* Non-global symbol doesn't need PLT32 relocation. */ | |
9085 | if (! S_IS_EXTERNAL (s)) | |
5b7c81bd | 9086 | return false; |
bd7ab16b L |
9087 | |
9088 | /* Other global symbols need PLT32 relocation. NB: Symbol with | |
9089 | non-default visibilities are treated as normal global symbol | |
9090 | so that PLT32 relocation can be used as a marker for 32-bit | |
9091 | PC-relative branches. It is useful for linker relaxation. */ | |
5b7c81bd | 9092 | return true; |
bd7ab16b L |
9093 | } |
9094 | #endif | |
9095 | ||
29b0f896 | 9096 | static void |
e3bb37b5 | 9097 | output_jump (void) |
29b0f896 AM |
9098 | { |
9099 | char *p; | |
9100 | int size; | |
3e02c1cc | 9101 | fixS *fixP; |
bd7ab16b | 9102 | bfd_reloc_code_real_type jump_reloc = i.reloc[0]; |
29b0f896 | 9103 | |
0cfa3eb3 | 9104 | if (i.tm.opcode_modifier.jump == JUMP_BYTE) |
29b0f896 AM |
9105 | { |
9106 | /* This is a loop or jecxz type instruction. */ | |
9107 | size = 1; | |
9108 | if (i.prefix[ADDR_PREFIX] != 0) | |
9109 | { | |
48ef937e | 9110 | frag_opcode_byte (ADDR_PREFIX_OPCODE); |
29b0f896 AM |
9111 | i.prefixes -= 1; |
9112 | } | |
9113 | /* Pentium4 branch hints. */ | |
9114 | if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ | |
9115 | || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) | |
9116 | { | |
48ef937e | 9117 | frag_opcode_byte (i.prefix[SEG_PREFIX]); |
29b0f896 | 9118 | i.prefixes--; |
3e73aa7c JH |
9119 | } |
9120 | } | |
29b0f896 AM |
9121 | else |
9122 | { | |
9123 | int code16; | |
3e73aa7c | 9124 | |
29b0f896 AM |
9125 | code16 = 0; |
9126 | if (flag_code == CODE_16BIT) | |
9127 | code16 = CODE16; | |
3e73aa7c | 9128 | |
29b0f896 AM |
9129 | if (i.prefix[DATA_PREFIX] != 0) |
9130 | { | |
48ef937e | 9131 | frag_opcode_byte (DATA_PREFIX_OPCODE); |
29b0f896 | 9132 | i.prefixes -= 1; |
376cd056 | 9133 | code16 ^= flip_code16(code16); |
29b0f896 | 9134 | } |
252b5132 | 9135 | |
29b0f896 AM |
9136 | size = 4; |
9137 | if (code16) | |
9138 | size = 2; | |
9139 | } | |
9fcc94b6 | 9140 | |
6cb0a70e JB |
9141 | /* BND prefixed jump. */ |
9142 | if (i.prefix[BND_PREFIX] != 0) | |
29b0f896 | 9143 | { |
48ef937e | 9144 | frag_opcode_byte (i.prefix[BND_PREFIX]); |
29b0f896 AM |
9145 | i.prefixes -= 1; |
9146 | } | |
252b5132 | 9147 | |
6cb0a70e | 9148 | if (i.prefix[REX_PREFIX] != 0) |
7e8b059b | 9149 | { |
48ef937e | 9150 | frag_opcode_byte (i.prefix[REX_PREFIX]); |
7e8b059b L |
9151 | i.prefixes -= 1; |
9152 | } | |
9153 | ||
f2810fe0 | 9154 | if (i.prefixes != 0) |
76d3f746 | 9155 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
e0890092 | 9156 | |
48ef937e JB |
9157 | if (now_seg == absolute_section) |
9158 | { | |
9a182d04 | 9159 | abs_section_offset += i.opcode_length + size; |
48ef937e JB |
9160 | return; |
9161 | } | |
9162 | ||
9a182d04 JB |
9163 | p = frag_more (i.opcode_length + size); |
9164 | switch (i.opcode_length) | |
42164a71 L |
9165 | { |
9166 | case 2: | |
9167 | *p++ = i.tm.base_opcode >> 8; | |
1a0670f3 | 9168 | /* Fall through. */ |
42164a71 L |
9169 | case 1: |
9170 | *p++ = i.tm.base_opcode; | |
9171 | break; | |
9172 | default: | |
9173 | abort (); | |
9174 | } | |
e0890092 | 9175 | |
bd7ab16b | 9176 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
9177 | if (flag_code == CODE_64BIT && size == 4 |
9178 | && jump_reloc == NO_RELOC && i.op[0].disps->X_add_number == 0 | |
bd7ab16b L |
9179 | && need_plt32_p (i.op[0].disps->X_add_symbol)) |
9180 | jump_reloc = BFD_RELOC_X86_64_PLT32; | |
9181 | #endif | |
9182 | ||
9183 | jump_reloc = reloc (size, 1, 1, jump_reloc); | |
9184 | ||
3e02c1cc | 9185 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
bd7ab16b | 9186 | i.op[0].disps, 1, jump_reloc); |
3e02c1cc | 9187 | |
eb19308f JB |
9188 | /* All jumps handled here are signed, but don't unconditionally use a |
9189 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
9190 | around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN) | |
9191 | respectively. */ | |
9192 | switch (size) | |
9193 | { | |
9194 | case 1: | |
9195 | fixP->fx_signed = 1; | |
9196 | break; | |
9197 | ||
9198 | case 2: | |
7fc69528 | 9199 | if (i.tm.mnem_off == MN_xbegin) |
eb19308f JB |
9200 | fixP->fx_signed = 1; |
9201 | break; | |
9202 | ||
9203 | case 4: | |
9204 | if (flag_code == CODE_64BIT) | |
9205 | fixP->fx_signed = 1; | |
9206 | break; | |
9207 | } | |
29b0f896 | 9208 | } |
e0890092 | 9209 | |
29b0f896 | 9210 | static void |
e3bb37b5 | 9211 | output_interseg_jump (void) |
29b0f896 AM |
9212 | { |
9213 | char *p; | |
9214 | int size; | |
9215 | int prefix; | |
9216 | int code16; | |
252b5132 | 9217 | |
29b0f896 AM |
9218 | code16 = 0; |
9219 | if (flag_code == CODE_16BIT) | |
9220 | code16 = CODE16; | |
a217f122 | 9221 | |
29b0f896 AM |
9222 | prefix = 0; |
9223 | if (i.prefix[DATA_PREFIX] != 0) | |
9224 | { | |
9225 | prefix = 1; | |
9226 | i.prefixes -= 1; | |
9227 | code16 ^= CODE16; | |
9228 | } | |
6cb0a70e JB |
9229 | |
9230 | gas_assert (!i.prefix[REX_PREFIX]); | |
252b5132 | 9231 | |
29b0f896 AM |
9232 | size = 4; |
9233 | if (code16) | |
9234 | size = 2; | |
252b5132 | 9235 | |
f2810fe0 | 9236 | if (i.prefixes != 0) |
76d3f746 | 9237 | as_warn (_("skipping prefixes on `%s'"), insn_name (&i.tm)); |
252b5132 | 9238 | |
48ef937e JB |
9239 | if (now_seg == absolute_section) |
9240 | { | |
9241 | abs_section_offset += prefix + 1 + 2 + size; | |
9242 | return; | |
9243 | } | |
9244 | ||
29b0f896 AM |
9245 | /* 1 opcode; 2 segment; offset */ |
9246 | p = frag_more (prefix + 1 + 2 + size); | |
3e73aa7c | 9247 | |
29b0f896 AM |
9248 | if (i.prefix[DATA_PREFIX] != 0) |
9249 | *p++ = DATA_PREFIX_OPCODE; | |
252b5132 | 9250 | |
29b0f896 AM |
9251 | if (i.prefix[REX_PREFIX] != 0) |
9252 | *p++ = i.prefix[REX_PREFIX]; | |
252b5132 | 9253 | |
29b0f896 AM |
9254 | *p++ = i.tm.base_opcode; |
9255 | if (i.op[1].imms->X_op == O_constant) | |
9256 | { | |
9257 | offsetT n = i.op[1].imms->X_add_number; | |
252b5132 | 9258 | |
29b0f896 AM |
9259 | if (size == 2 |
9260 | && !fits_in_unsigned_word (n) | |
9261 | && !fits_in_signed_word (n)) | |
9262 | { | |
9263 | as_bad (_("16-bit jump out of range")); | |
9264 | return; | |
9265 | } | |
9266 | md_number_to_chars (p, n, size); | |
9267 | } | |
9268 | else | |
9269 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, | |
d258b828 | 9270 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
6d96a594 C |
9271 | |
9272 | p += size; | |
9273 | if (i.op[0].imms->X_op == O_constant) | |
9274 | md_number_to_chars (p, (valueT) i.op[0].imms->X_add_number, 2); | |
9275 | else | |
9276 | fix_new_exp (frag_now, p - frag_now->fr_literal, 2, | |
9277 | i.op[0].imms, 0, reloc (2, 0, 0, i.reloc[0])); | |
29b0f896 | 9278 | } |
a217f122 | 9279 | |
b4a3a7b4 L |
9280 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
9281 | void | |
9282 | x86_cleanup (void) | |
9283 | { | |
9284 | char *p; | |
9285 | asection *seg = now_seg; | |
9286 | subsegT subseg = now_subseg; | |
9287 | asection *sec; | |
9288 | unsigned int alignment, align_size_1; | |
9289 | unsigned int isa_1_descsz, feature_2_descsz, descsz; | |
9290 | unsigned int isa_1_descsz_raw, feature_2_descsz_raw; | |
9291 | unsigned int padding; | |
9292 | ||
1273b2f8 | 9293 | if (!IS_ELF || !x86_used_note) |
b4a3a7b4 L |
9294 | return; |
9295 | ||
b4a3a7b4 L |
9296 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X86; |
9297 | ||
9298 | /* The .note.gnu.property section layout: | |
9299 | ||
9300 | Field Length Contents | |
9301 | ---- ---- ---- | |
9302 | n_namsz 4 4 | |
9303 | n_descsz 4 The note descriptor size | |
9304 | n_type 4 NT_GNU_PROPERTY_TYPE_0 | |
9305 | n_name 4 "GNU" | |
9306 | n_desc n_descsz The program property array | |
9307 | .... .... .... | |
9308 | */ | |
9309 | ||
9310 | /* Create the .note.gnu.property section. */ | |
9311 | sec = subseg_new (NOTE_GNU_PROPERTY_SECTION_NAME, 0); | |
fd361982 | 9312 | bfd_set_section_flags (sec, |
b4a3a7b4 L |
9313 | (SEC_ALLOC |
9314 | | SEC_LOAD | |
9315 | | SEC_DATA | |
9316 | | SEC_HAS_CONTENTS | |
9317 | | SEC_READONLY)); | |
9318 | ||
9319 | if (get_elf_backend_data (stdoutput)->s->elfclass == ELFCLASS64) | |
9320 | { | |
9321 | align_size_1 = 7; | |
9322 | alignment = 3; | |
9323 | } | |
9324 | else | |
9325 | { | |
9326 | align_size_1 = 3; | |
9327 | alignment = 2; | |
9328 | } | |
9329 | ||
fd361982 | 9330 | bfd_set_section_alignment (sec, alignment); |
b4a3a7b4 L |
9331 | elf_section_type (sec) = SHT_NOTE; |
9332 | ||
1273b2f8 L |
9333 | /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size |
9334 | + 4-byte data */ | |
9335 | isa_1_descsz_raw = 4 + 4 + 4; | |
9336 | /* Align GNU_PROPERTY_X86_ISA_1_USED. */ | |
9337 | isa_1_descsz = (isa_1_descsz_raw + align_size_1) & ~align_size_1; | |
b4a3a7b4 L |
9338 | |
9339 | feature_2_descsz_raw = isa_1_descsz; | |
9340 | /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size | |
1273b2f8 | 9341 | + 4-byte data */ |
b4a3a7b4 L |
9342 | feature_2_descsz_raw += 4 + 4 + 4; |
9343 | /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */ | |
9344 | feature_2_descsz = ((feature_2_descsz_raw + align_size_1) | |
9345 | & ~align_size_1); | |
9346 | ||
9347 | descsz = feature_2_descsz; | |
9348 | /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */ | |
9349 | p = frag_more (4 + 4 + 4 + 4 + descsz); | |
9350 | ||
9351 | /* Write n_namsz. */ | |
9352 | md_number_to_chars (p, (valueT) 4, 4); | |
9353 | ||
9354 | /* Write n_descsz. */ | |
9355 | md_number_to_chars (p + 4, (valueT) descsz, 4); | |
9356 | ||
9357 | /* Write n_type. */ | |
9358 | md_number_to_chars (p + 4 * 2, (valueT) NT_GNU_PROPERTY_TYPE_0, 4); | |
9359 | ||
9360 | /* Write n_name. */ | |
9361 | memcpy (p + 4 * 3, "GNU", 4); | |
9362 | ||
1273b2f8 L |
9363 | /* Write 4-byte type. */ |
9364 | md_number_to_chars (p + 4 * 4, | |
9365 | (valueT) GNU_PROPERTY_X86_ISA_1_USED, 4); | |
b4a3a7b4 | 9366 | |
1273b2f8 L |
9367 | /* Write 4-byte data size. */ |
9368 | md_number_to_chars (p + 4 * 5, (valueT) 4, 4); | |
b4a3a7b4 | 9369 | |
1273b2f8 L |
9370 | /* Write 4-byte data. */ |
9371 | md_number_to_chars (p + 4 * 6, (valueT) x86_isa_1_used, 4); | |
b4a3a7b4 | 9372 | |
1273b2f8 L |
9373 | /* Zero out paddings. */ |
9374 | padding = isa_1_descsz - isa_1_descsz_raw; | |
9375 | if (padding) | |
9376 | memset (p + 4 * 7, 0, padding); | |
b4a3a7b4 L |
9377 | |
9378 | /* Write 4-byte type. */ | |
9379 | md_number_to_chars (p + isa_1_descsz + 4 * 4, | |
9380 | (valueT) GNU_PROPERTY_X86_FEATURE_2_USED, 4); | |
9381 | ||
9382 | /* Write 4-byte data size. */ | |
9383 | md_number_to_chars (p + isa_1_descsz + 4 * 5, (valueT) 4, 4); | |
9384 | ||
9385 | /* Write 4-byte data. */ | |
9386 | md_number_to_chars (p + isa_1_descsz + 4 * 6, | |
9387 | (valueT) x86_feature_2_used, 4); | |
9388 | ||
9389 | /* Zero out paddings. */ | |
9390 | padding = feature_2_descsz - feature_2_descsz_raw; | |
9391 | if (padding) | |
9392 | memset (p + isa_1_descsz + 4 * 7, 0, padding); | |
9393 | ||
9394 | /* We probably can't restore the current segment, for there likely | |
9395 | isn't one yet... */ | |
9396 | if (seg && subseg) | |
9397 | subseg_set (seg, subseg); | |
9398 | } | |
b52c4ee4 IB |
9399 | |
9400 | bool | |
9401 | x86_support_sframe_p (void) | |
9402 | { | |
3e3e792a | 9403 | /* At this time, SFrame stack trace is supported for AMD64 ABI only. */ |
b52c4ee4 IB |
9404 | return (x86_elf_abi == X86_64_ABI); |
9405 | } | |
9406 | ||
9407 | bool | |
9408 | x86_sframe_ra_tracking_p (void) | |
9409 | { | |
9410 | /* In AMD64, return address is always stored on the stack at a fixed offset | |
9411 | from the CFA (provided via x86_sframe_cfa_ra_offset ()). | |
9412 | Do not track explicitly via an SFrame Frame Row Entry. */ | |
9413 | return false; | |
9414 | } | |
9415 | ||
9416 | offsetT | |
9417 | x86_sframe_cfa_ra_offset (void) | |
9418 | { | |
9419 | gas_assert (x86_elf_abi == X86_64_ABI); | |
9420 | return (offsetT) -8; | |
9421 | } | |
9422 | ||
9423 | unsigned char | |
9424 | x86_sframe_get_abi_arch (void) | |
9425 | { | |
9426 | unsigned char sframe_abi_arch = 0; | |
9427 | ||
9428 | if (x86_support_sframe_p ()) | |
9429 | { | |
9430 | gas_assert (!target_big_endian); | |
9431 | sframe_abi_arch = SFRAME_ABI_AMD64_ENDIAN_LITTLE; | |
9432 | } | |
9433 | ||
9434 | return sframe_abi_arch; | |
9435 | } | |
9436 | ||
b4a3a7b4 L |
9437 | #endif |
9438 | ||
9c33702b JB |
9439 | static unsigned int |
9440 | encoding_length (const fragS *start_frag, offsetT start_off, | |
9441 | const char *frag_now_ptr) | |
9442 | { | |
9443 | unsigned int len = 0; | |
9444 | ||
9445 | if (start_frag != frag_now) | |
9446 | { | |
9447 | const fragS *fr = start_frag; | |
9448 | ||
9449 | do { | |
9450 | len += fr->fr_fix; | |
9451 | fr = fr->fr_next; | |
9452 | } while (fr && fr != frag_now); | |
9453 | } | |
9454 | ||
9455 | return len - start_off + (frag_now_ptr - frag_now->fr_literal); | |
9456 | } | |
9457 | ||
e379e5f3 | 9458 | /* Return 1 for test, and, cmp, add, sub, inc and dec which may |
79d72f45 HL |
9459 | be macro-fused with conditional jumps. |
9460 | NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address, | |
9461 | or is one of the following format: | |
9462 | ||
9463 | cmp m, imm | |
9464 | add m, imm | |
9465 | sub m, imm | |
9466 | test m, imm | |
9467 | and m, imm | |
9468 | inc m | |
9469 | dec m | |
9470 | ||
9471 | it is unfusible. */ | |
e379e5f3 L |
9472 | |
9473 | static int | |
79d72f45 | 9474 | maybe_fused_with_jcc_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9475 | { |
9476 | /* No RIP address. */ | |
9477 | if (i.base_reg && i.base_reg->reg_num == RegIP) | |
9478 | return 0; | |
9479 | ||
389d00a5 | 9480 | /* No opcodes outside of base encoding space. */ |
ddb62495 | 9481 | if (i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
9482 | return 0; |
9483 | ||
79d72f45 HL |
9484 | /* add, sub without add/sub m, imm. */ |
9485 | if (i.tm.base_opcode <= 5 | |
e379e5f3 L |
9486 | || (i.tm.base_opcode >= 0x28 && i.tm.base_opcode <= 0x2d) |
9487 | || ((i.tm.base_opcode | 3) == 0x83 | |
79d72f45 | 9488 | && (i.tm.extension_opcode == 0x5 |
e379e5f3 | 9489 | || i.tm.extension_opcode == 0x0))) |
79d72f45 HL |
9490 | { |
9491 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9492 | return !(i.mem_operands && i.imm_operands); | |
9493 | } | |
e379e5f3 | 9494 | |
79d72f45 HL |
9495 | /* and without and m, imm. */ |
9496 | if ((i.tm.base_opcode >= 0x20 && i.tm.base_opcode <= 0x25) | |
9497 | || ((i.tm.base_opcode | 3) == 0x83 | |
9498 | && i.tm.extension_opcode == 0x4)) | |
9499 | { | |
9500 | *mf_cmp_p = mf_cmp_test_and; | |
9501 | return !(i.mem_operands && i.imm_operands); | |
9502 | } | |
9503 | ||
9504 | /* test without test m imm. */ | |
e379e5f3 L |
9505 | if ((i.tm.base_opcode | 1) == 0x85 |
9506 | || (i.tm.base_opcode | 1) == 0xa9 | |
9507 | || ((i.tm.base_opcode | 1) == 0xf7 | |
79d72f45 HL |
9508 | && i.tm.extension_opcode == 0)) |
9509 | { | |
9510 | *mf_cmp_p = mf_cmp_test_and; | |
9511 | return !(i.mem_operands && i.imm_operands); | |
9512 | } | |
9513 | ||
9514 | /* cmp without cmp m, imm. */ | |
9515 | if ((i.tm.base_opcode >= 0x38 && i.tm.base_opcode <= 0x3d) | |
e379e5f3 L |
9516 | || ((i.tm.base_opcode | 3) == 0x83 |
9517 | && (i.tm.extension_opcode == 0x7))) | |
79d72f45 HL |
9518 | { |
9519 | *mf_cmp_p = mf_cmp_alu_cmp; | |
9520 | return !(i.mem_operands && i.imm_operands); | |
9521 | } | |
e379e5f3 | 9522 | |
79d72f45 | 9523 | /* inc, dec without inc/dec m. */ |
734dfd1c | 9524 | if ((is_cpu (&i.tm, CpuNo64) |
e379e5f3 L |
9525 | && (i.tm.base_opcode | 0xf) == 0x4f) |
9526 | || ((i.tm.base_opcode | 1) == 0xff | |
9527 | && i.tm.extension_opcode <= 0x1)) | |
79d72f45 HL |
9528 | { |
9529 | *mf_cmp_p = mf_cmp_incdec; | |
9530 | return !i.mem_operands; | |
9531 | } | |
e379e5f3 L |
9532 | |
9533 | return 0; | |
9534 | } | |
9535 | ||
9536 | /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */ | |
9537 | ||
9538 | static int | |
79d72f45 | 9539 | add_fused_jcc_padding_frag_p (enum mf_cmp_kind* mf_cmp_p) |
e379e5f3 L |
9540 | { |
9541 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9542 | if (!align_branch_power | |
9543 | || now_seg == absolute_section | |
9544 | || !cpu_arch_flags.bitfield.cpui386 | |
9545 | || !(align_branch & align_branch_fused_bit)) | |
9546 | return 0; | |
9547 | ||
79d72f45 | 9548 | if (maybe_fused_with_jcc_p (mf_cmp_p)) |
e379e5f3 L |
9549 | { |
9550 | if (last_insn.kind == last_insn_other | |
9551 | || last_insn.seg != now_seg) | |
9552 | return 1; | |
9553 | if (flag_debug) | |
9554 | as_warn_where (last_insn.file, last_insn.line, | |
9555 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
76d3f746 | 9556 | last_insn.name, insn_name (&i.tm)); |
e379e5f3 L |
9557 | } |
9558 | ||
9559 | return 0; | |
9560 | } | |
9561 | ||
9562 | /* Return 1 if a BRANCH_PREFIX frag should be generated. */ | |
9563 | ||
9564 | static int | |
9565 | add_branch_prefix_frag_p (void) | |
9566 | { | |
9567 | /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix | |
9568 | to PadLock instructions since they include prefixes in opcode. */ | |
9569 | if (!align_branch_power | |
9570 | || !align_branch_prefix_size | |
9571 | || now_seg == absolute_section | |
734dfd1c | 9572 | || is_cpu (&i.tm, CpuPadLock) |
e379e5f3 L |
9573 | || !cpu_arch_flags.bitfield.cpui386) |
9574 | return 0; | |
9575 | ||
9576 | /* Don't add prefix if it is a prefix or there is no operand in case | |
9577 | that segment prefix is special. */ | |
9578 | if (!i.operands || i.tm.opcode_modifier.isprefix) | |
9579 | return 0; | |
9580 | ||
9581 | if (last_insn.kind == last_insn_other | |
9582 | || last_insn.seg != now_seg) | |
9583 | return 1; | |
9584 | ||
9585 | if (flag_debug) | |
9586 | as_warn_where (last_insn.file, last_insn.line, | |
9587 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
76d3f746 | 9588 | last_insn.name, insn_name (&i.tm)); |
e379e5f3 L |
9589 | |
9590 | return 0; | |
9591 | } | |
9592 | ||
9593 | /* Return 1 if a BRANCH_PADDING frag should be generated. */ | |
9594 | ||
9595 | static int | |
79d72f45 HL |
9596 | add_branch_padding_frag_p (enum align_branch_kind *branch_p, |
9597 | enum mf_jcc_kind *mf_jcc_p) | |
e379e5f3 L |
9598 | { |
9599 | int add_padding; | |
9600 | ||
9601 | /* NB: Don't work with COND_JUMP86 without i386. */ | |
9602 | if (!align_branch_power | |
9603 | || now_seg == absolute_section | |
389d00a5 | 9604 | || !cpu_arch_flags.bitfield.cpui386 |
ddb62495 | 9605 | || i.tm.opcode_space != SPACE_BASE) |
e379e5f3 L |
9606 | return 0; |
9607 | ||
9608 | add_padding = 0; | |
9609 | ||
9610 | /* Check for jcc and direct jmp. */ | |
9611 | if (i.tm.opcode_modifier.jump == JUMP) | |
9612 | { | |
9613 | if (i.tm.base_opcode == JUMP_PC_RELATIVE) | |
9614 | { | |
9615 | *branch_p = align_branch_jmp; | |
9616 | add_padding = align_branch & align_branch_jmp_bit; | |
9617 | } | |
9618 | else | |
9619 | { | |
79d72f45 HL |
9620 | /* Because J<cc> and JN<cc> share same group in macro-fusible table, |
9621 | igore the lowest bit. */ | |
9622 | *mf_jcc_p = (i.tm.base_opcode & 0x0e) >> 1; | |
e379e5f3 L |
9623 | *branch_p = align_branch_jcc; |
9624 | if ((align_branch & align_branch_jcc_bit)) | |
9625 | add_padding = 1; | |
9626 | } | |
9627 | } | |
e379e5f3 L |
9628 | else if ((i.tm.base_opcode | 1) == 0xc3) |
9629 | { | |
9630 | /* Near ret. */ | |
9631 | *branch_p = align_branch_ret; | |
9632 | if ((align_branch & align_branch_ret_bit)) | |
9633 | add_padding = 1; | |
9634 | } | |
9635 | else | |
9636 | { | |
9637 | /* Check for indirect jmp, direct and indirect calls. */ | |
9638 | if (i.tm.base_opcode == 0xe8) | |
9639 | { | |
9640 | /* Direct call. */ | |
9641 | *branch_p = align_branch_call; | |
9642 | if ((align_branch & align_branch_call_bit)) | |
9643 | add_padding = 1; | |
9644 | } | |
9645 | else if (i.tm.base_opcode == 0xff | |
9646 | && (i.tm.extension_opcode == 2 | |
9647 | || i.tm.extension_opcode == 4)) | |
9648 | { | |
9649 | /* Indirect call and jmp. */ | |
9650 | *branch_p = align_branch_indirect; | |
9651 | if ((align_branch & align_branch_indirect_bit)) | |
9652 | add_padding = 1; | |
9653 | } | |
9654 | ||
9655 | if (add_padding | |
9656 | && i.disp_operands | |
9657 | && tls_get_addr | |
9658 | && (i.op[0].disps->X_op == O_symbol | |
9659 | || (i.op[0].disps->X_op == O_subtract | |
9660 | && i.op[0].disps->X_op_symbol == GOT_symbol))) | |
9661 | { | |
9662 | symbolS *s = i.op[0].disps->X_add_symbol; | |
9663 | /* No padding to call to global or undefined tls_get_addr. */ | |
9664 | if ((S_IS_EXTERNAL (s) || !S_IS_DEFINED (s)) | |
9665 | && strcmp (S_GET_NAME (s), tls_get_addr) == 0) | |
9666 | return 0; | |
9667 | } | |
9668 | } | |
9669 | ||
9670 | if (add_padding | |
9671 | && last_insn.kind != last_insn_other | |
9672 | && last_insn.seg == now_seg) | |
9673 | { | |
9674 | if (flag_debug) | |
9675 | as_warn_where (last_insn.file, last_insn.line, | |
9676 | _("`%s` skips -malign-branch-boundary on `%s`"), | |
76d3f746 | 9677 | last_insn.name, insn_name (&i.tm)); |
e379e5f3 L |
9678 | return 0; |
9679 | } | |
9680 | ||
9681 | return add_padding; | |
9682 | } | |
9683 | ||
29b0f896 | 9684 | static void |
e3bb37b5 | 9685 | output_insn (void) |
29b0f896 | 9686 | { |
2bbd9c25 JJ |
9687 | fragS *insn_start_frag; |
9688 | offsetT insn_start_off; | |
e379e5f3 L |
9689 | fragS *fragP = NULL; |
9690 | enum align_branch_kind branch = align_branch_none; | |
79d72f45 HL |
9691 | /* The initializer is arbitrary just to avoid uninitialized error. |
9692 | it's actually either assigned in add_branch_padding_frag_p | |
9693 | or never be used. */ | |
9694 | enum mf_jcc_kind mf_jcc = mf_jcc_jo; | |
2bbd9c25 | 9695 | |
b4a3a7b4 | 9696 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
48ef937e | 9697 | if (IS_ELF && x86_used_note && now_seg != absolute_section) |
b4a3a7b4 | 9698 | { |
32930e4e | 9699 | if ((i.xstate & xstate_tmm) == xstate_tmm |
734dfd1c | 9700 | || is_cpu (&i.tm, CpuAMX_TILE)) |
32930e4e L |
9701 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM; |
9702 | ||
734dfd1c JB |
9703 | if (is_cpu (&i.tm, Cpu8087) |
9704 | || is_cpu (&i.tm, Cpu287) | |
9705 | || is_cpu (&i.tm, Cpu387) | |
9706 | || is_cpu (&i.tm, Cpu687) | |
9707 | || is_cpu (&i.tm, CpuFISTTP)) | |
b4a3a7b4 | 9708 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_X87; |
014d61ea | 9709 | |
921eafea | 9710 | if ((i.xstate & xstate_mmx) |
7fc69528 JB |
9711 | || i.tm.mnem_off == MN_emms |
9712 | || i.tm.mnem_off == MN_femms) | |
b4a3a7b4 | 9713 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MMX; |
014d61ea | 9714 | |
32930e4e L |
9715 | if (i.index_reg) |
9716 | { | |
9717 | if (i.index_reg->reg_type.bitfield.zmmword) | |
9718 | i.xstate |= xstate_zmm; | |
9719 | else if (i.index_reg->reg_type.bitfield.ymmword) | |
9720 | i.xstate |= xstate_ymm; | |
9721 | else if (i.index_reg->reg_type.bitfield.xmmword) | |
9722 | i.xstate |= xstate_xmm; | |
9723 | } | |
014d61ea JB |
9724 | |
9725 | /* vzeroall / vzeroupper */ | |
734dfd1c | 9726 | if (i.tm.base_opcode == 0x77 && is_cpu (&i.tm, CpuAVX)) |
014d61ea JB |
9727 | i.xstate |= xstate_ymm; |
9728 | ||
c4694f17 | 9729 | if ((i.xstate & xstate_xmm) |
389d00a5 JB |
9730 | /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */ |
9731 | || (i.tm.base_opcode == 0xae | |
734dfd1c JB |
9732 | && (is_cpu (&i.tm, CpuSSE) |
9733 | || is_cpu (&i.tm, CpuAVX))) | |
9734 | || is_cpu (&i.tm, CpuWideKL) | |
9735 | || is_cpu (&i.tm, CpuKL)) | |
b4a3a7b4 | 9736 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XMM; |
014d61ea | 9737 | |
921eafea | 9738 | if ((i.xstate & xstate_ymm) == xstate_ymm) |
b4a3a7b4 | 9739 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_YMM; |
921eafea | 9740 | if ((i.xstate & xstate_zmm) == xstate_zmm) |
b4a3a7b4 | 9741 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_ZMM; |
6225c532 | 9742 | if (i.mask.reg || (i.xstate & xstate_mask) == xstate_mask) |
32930e4e | 9743 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_MASK; |
734dfd1c | 9744 | if (is_cpu (&i.tm, CpuFXSR)) |
b4a3a7b4 | 9745 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_FXSR; |
734dfd1c | 9746 | if (is_cpu (&i.tm, CpuXsave)) |
b4a3a7b4 | 9747 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVE; |
734dfd1c | 9748 | if (is_cpu (&i.tm, CpuXsaveopt)) |
b4a3a7b4 | 9749 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT; |
734dfd1c | 9750 | if (is_cpu (&i.tm, CpuXSAVEC)) |
b4a3a7b4 | 9751 | x86_feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_XSAVEC; |
b0ab0693 L |
9752 | |
9753 | if (x86_feature_2_used | |
734dfd1c JB |
9754 | || is_cpu (&i.tm, CpuCMOV) |
9755 | || is_cpu (&i.tm, CpuSYSCALL) | |
7fc69528 | 9756 | || i.tm.mnem_off == MN_cmpxchg8b) |
b0ab0693 | 9757 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_BASELINE; |
734dfd1c JB |
9758 | if (is_cpu (&i.tm, CpuSSE3) |
9759 | || is_cpu (&i.tm, CpuSSSE3) | |
9760 | || is_cpu (&i.tm, CpuSSE4_1) | |
9761 | || is_cpu (&i.tm, CpuSSE4_2) | |
9762 | || is_cpu (&i.tm, CpuCX16) | |
9763 | || is_cpu (&i.tm, CpuPOPCNT) | |
b0ab0693 L |
9764 | /* LAHF-SAHF insns in 64-bit mode. */ |
9765 | || (flag_code == CODE_64BIT | |
35648716 | 9766 | && (i.tm.base_opcode | 1) == 0x9f |
ddb62495 | 9767 | && i.tm.opcode_space == SPACE_BASE)) |
b0ab0693 | 9768 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V2; |
734dfd1c JB |
9769 | if (is_cpu (&i.tm, CpuAVX) |
9770 | || is_cpu (&i.tm, CpuAVX2) | |
a9860005 JB |
9771 | /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ, |
9772 | XOP, FMA4, LPW, TBM, and AMX. */ | |
b0ab0693 | 9773 | || (i.tm.opcode_modifier.vex |
734dfd1c JB |
9774 | && !is_cpu (&i.tm, CpuAVX512F) |
9775 | && !is_cpu (&i.tm, CpuAVX512BW) | |
9776 | && !is_cpu (&i.tm, CpuAVX512DQ) | |
9777 | && !is_cpu (&i.tm, CpuXOP) | |
9778 | && !is_cpu (&i.tm, CpuFMA4) | |
9779 | && !is_cpu (&i.tm, CpuLWP) | |
9780 | && !is_cpu (&i.tm, CpuTBM) | |
b0ab0693 | 9781 | && !(x86_feature_2_used & GNU_PROPERTY_X86_FEATURE_2_TMM)) |
734dfd1c JB |
9782 | || is_cpu (&i.tm, CpuF16C) |
9783 | || is_cpu (&i.tm, CpuFMA) | |
9784 | || is_cpu (&i.tm, CpuLZCNT) | |
9785 | || is_cpu (&i.tm, CpuMovbe) | |
9786 | || is_cpu (&i.tm, CpuXSAVES) | |
b0ab0693 L |
9787 | || (x86_feature_2_used |
9788 | & (GNU_PROPERTY_X86_FEATURE_2_XSAVE | |
9789 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT | |
9790 | | GNU_PROPERTY_X86_FEATURE_2_XSAVEC)) != 0) | |
9791 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V3; | |
734dfd1c JB |
9792 | if (is_cpu (&i.tm, CpuAVX512F) |
9793 | || is_cpu (&i.tm, CpuAVX512BW) | |
9794 | || is_cpu (&i.tm, CpuAVX512DQ) | |
9795 | || is_cpu (&i.tm, CpuAVX512VL) | |
a9860005 JB |
9796 | /* Any EVEX encoded insns except for AVX512ER, AVX512PF, |
9797 | AVX512-4FMAPS, and AVX512-4VNNIW. */ | |
b0ab0693 | 9798 | || (i.tm.opcode_modifier.evex |
734dfd1c JB |
9799 | && !is_cpu (&i.tm, CpuAVX512ER) |
9800 | && !is_cpu (&i.tm, CpuAVX512PF) | |
9801 | && !is_cpu (&i.tm, CpuAVX512_4FMAPS) | |
9802 | && !is_cpu (&i.tm, CpuAVX512_4VNNIW))) | |
b0ab0693 | 9803 | x86_isa_1_used |= GNU_PROPERTY_X86_ISA_1_V4; |
b4a3a7b4 L |
9804 | } |
9805 | #endif | |
9806 | ||
29b0f896 AM |
9807 | /* Tie dwarf2 debug info to the address at the start of the insn. |
9808 | We can't do this after the insn has been output as the current | |
9809 | frag may have been closed off. eg. by frag_var. */ | |
9810 | dwarf2_emit_insn (0); | |
9811 | ||
2bbd9c25 JJ |
9812 | insn_start_frag = frag_now; |
9813 | insn_start_off = frag_now_fix (); | |
9814 | ||
79d72f45 | 9815 | if (add_branch_padding_frag_p (&branch, &mf_jcc)) |
e379e5f3 L |
9816 | { |
9817 | char *p; | |
9818 | /* Branch can be 8 bytes. Leave some room for prefixes. */ | |
9819 | unsigned int max_branch_padding_size = 14; | |
9820 | ||
9821 | /* Align section to boundary. */ | |
9822 | record_alignment (now_seg, align_branch_power); | |
9823 | ||
9824 | /* Make room for padding. */ | |
9825 | frag_grow (max_branch_padding_size); | |
9826 | ||
9827 | /* Start of the padding. */ | |
9828 | p = frag_more (0); | |
9829 | ||
9830 | fragP = frag_now; | |
9831 | ||
9832 | frag_var (rs_machine_dependent, max_branch_padding_size, 0, | |
9833 | ENCODE_RELAX_STATE (BRANCH_PADDING, 0), | |
9834 | NULL, 0, p); | |
9835 | ||
79d72f45 | 9836 | fragP->tc_frag_data.mf_type = mf_jcc; |
e379e5f3 L |
9837 | fragP->tc_frag_data.branch_type = branch; |
9838 | fragP->tc_frag_data.max_bytes = max_branch_padding_size; | |
9839 | } | |
9840 | ||
d59a54c2 JB |
9841 | if (!cpu_arch_flags.bitfield.cpui386 && (flag_code != CODE_16BIT) |
9842 | && !pre_386_16bit_warned) | |
9843 | { | |
9844 | as_warn (_("use .code16 to ensure correct addressing mode")); | |
9845 | pre_386_16bit_warned = true; | |
9846 | } | |
9847 | ||
29b0f896 | 9848 | /* Output jumps. */ |
0cfa3eb3 | 9849 | if (i.tm.opcode_modifier.jump == JUMP) |
29b0f896 | 9850 | output_branch (); |
0cfa3eb3 JB |
9851 | else if (i.tm.opcode_modifier.jump == JUMP_BYTE |
9852 | || i.tm.opcode_modifier.jump == JUMP_DWORD) | |
29b0f896 | 9853 | output_jump (); |
0cfa3eb3 | 9854 | else if (i.tm.opcode_modifier.jump == JUMP_INTERSEGMENT) |
29b0f896 AM |
9855 | output_interseg_jump (); |
9856 | else | |
9857 | { | |
9858 | /* Output normal instructions here. */ | |
9859 | char *p; | |
9860 | unsigned char *q; | |
47465058 | 9861 | unsigned int j; |
79d72f45 | 9862 | enum mf_cmp_kind mf_cmp; |
4dffcebc | 9863 | |
e4e00185 | 9864 | if (avoid_fence |
389d00a5 JB |
9865 | && (i.tm.base_opcode == 0xaee8 |
9866 | || i.tm.base_opcode == 0xaef0 | |
9867 | || i.tm.base_opcode == 0xaef8)) | |
48ef937e JB |
9868 | { |
9869 | /* Encode lfence, mfence, and sfence as | |
9870 | f0 83 04 24 00 lock addl $0x0, (%{re}sp). */ | |
47f4115a | 9871 | if (flag_code == CODE_16BIT) |
76d3f746 | 9872 | as_bad (_("Cannot convert `%s' in 16-bit mode"), insn_name (&i.tm)); |
47f4115a JB |
9873 | else if (omit_lock_prefix) |
9874 | as_bad (_("Cannot convert `%s' with `-momit-lock-prefix=yes' in effect"), | |
76d3f746 | 9875 | insn_name (&i.tm)); |
47f4115a | 9876 | else if (now_seg != absolute_section) |
48ef937e JB |
9877 | { |
9878 | offsetT val = 0x240483f0ULL; | |
9879 | ||
9880 | p = frag_more (5); | |
9881 | md_number_to_chars (p, val, 5); | |
9882 | } | |
9883 | else | |
9884 | abs_section_offset += 5; | |
9885 | return; | |
9886 | } | |
e4e00185 | 9887 | |
d022bddd IT |
9888 | /* Some processors fail on LOCK prefix. This options makes |
9889 | assembler ignore LOCK prefix and serves as a workaround. */ | |
9890 | if (omit_lock_prefix) | |
9891 | { | |
35648716 JB |
9892 | if (i.tm.base_opcode == LOCK_PREFIX_OPCODE |
9893 | && i.tm.opcode_modifier.isprefix) | |
d022bddd IT |
9894 | return; |
9895 | i.prefix[LOCK_PREFIX] = 0; | |
9896 | } | |
9897 | ||
e379e5f3 L |
9898 | if (branch) |
9899 | /* Skip if this is a branch. */ | |
9900 | ; | |
79d72f45 | 9901 | else if (add_fused_jcc_padding_frag_p (&mf_cmp)) |
e379e5f3 L |
9902 | { |
9903 | /* Make room for padding. */ | |
9904 | frag_grow (MAX_FUSED_JCC_PADDING_SIZE); | |
9905 | p = frag_more (0); | |
9906 | ||
9907 | fragP = frag_now; | |
9908 | ||
9909 | frag_var (rs_machine_dependent, MAX_FUSED_JCC_PADDING_SIZE, 0, | |
9910 | ENCODE_RELAX_STATE (FUSED_JCC_PADDING, 0), | |
9911 | NULL, 0, p); | |
9912 | ||
79d72f45 | 9913 | fragP->tc_frag_data.mf_type = mf_cmp; |
e379e5f3 L |
9914 | fragP->tc_frag_data.branch_type = align_branch_fused; |
9915 | fragP->tc_frag_data.max_bytes = MAX_FUSED_JCC_PADDING_SIZE; | |
9916 | } | |
9917 | else if (add_branch_prefix_frag_p ()) | |
9918 | { | |
9919 | unsigned int max_prefix_size = align_branch_prefix_size; | |
9920 | ||
9921 | /* Make room for padding. */ | |
9922 | frag_grow (max_prefix_size); | |
9923 | p = frag_more (0); | |
9924 | ||
9925 | fragP = frag_now; | |
9926 | ||
9927 | frag_var (rs_machine_dependent, max_prefix_size, 0, | |
9928 | ENCODE_RELAX_STATE (BRANCH_PREFIX, 0), | |
9929 | NULL, 0, p); | |
9930 | ||
9931 | fragP->tc_frag_data.max_bytes = max_prefix_size; | |
9932 | } | |
9933 | ||
43234a1e L |
9934 | /* Since the VEX/EVEX prefix contains the implicit prefix, we |
9935 | don't need the explicit prefix. */ | |
cf665fee | 9936 | if (!is_any_vex_encoding (&i.tm)) |
bc4bd9ab | 9937 | { |
7b47a312 | 9938 | switch (i.tm.opcode_modifier.opcodeprefix) |
bc4bd9ab | 9939 | { |
7b47a312 L |
9940 | case PREFIX_0X66: |
9941 | add_prefix (0x66); | |
9942 | break; | |
9943 | case PREFIX_0XF2: | |
9944 | add_prefix (0xf2); | |
9945 | break; | |
9946 | case PREFIX_0XF3: | |
734dfd1c | 9947 | if (!is_cpu (&i.tm, CpuPadLock) |
8b65b895 L |
9948 | || (i.prefix[REP_PREFIX] != 0xf3)) |
9949 | add_prefix (0xf3); | |
c0f3af97 | 9950 | break; |
7b47a312 | 9951 | case PREFIX_NONE: |
9a182d04 | 9952 | switch (i.opcode_length) |
c0f3af97 | 9953 | { |
7b47a312 | 9954 | case 2: |
7b47a312 | 9955 | break; |
9a182d04 | 9956 | case 1: |
7b47a312 | 9957 | /* Check for pseudo prefixes. */ |
9a182d04 JB |
9958 | if (!i.tm.opcode_modifier.isprefix || i.tm.base_opcode) |
9959 | break; | |
7b47a312 L |
9960 | as_bad_where (insn_start_frag->fr_file, |
9961 | insn_start_frag->fr_line, | |
9962 | _("pseudo prefix without instruction")); | |
9963 | return; | |
9964 | default: | |
9965 | abort (); | |
4dffcebc | 9966 | } |
c0f3af97 | 9967 | break; |
c0f3af97 L |
9968 | default: |
9969 | abort (); | |
bc4bd9ab | 9970 | } |
c0f3af97 | 9971 | |
6d19a37a | 9972 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
cf61b747 L |
9973 | /* For x32, add a dummy REX_OPCODE prefix for mov/add with |
9974 | R_X86_64_GOTTPOFF relocation so that linker can safely | |
14470f07 L |
9975 | perform IE->LE optimization. A dummy REX_OPCODE prefix |
9976 | is also needed for lea with R_X86_64_GOTPC32_TLSDESC | |
9977 | relocation for GDesc -> IE/LE optimization. */ | |
cf61b747 L |
9978 | if (x86_elf_abi == X86_64_X32_ABI |
9979 | && i.operands == 2 | |
14470f07 L |
9980 | && (i.reloc[0] == BFD_RELOC_X86_64_GOTTPOFF |
9981 | || i.reloc[0] == BFD_RELOC_X86_64_GOTPC32_TLSDESC) | |
cf61b747 L |
9982 | && i.prefix[REX_PREFIX] == 0) |
9983 | add_prefix (REX_OPCODE); | |
6d19a37a | 9984 | #endif |
cf61b747 | 9985 | |
c0f3af97 L |
9986 | /* The prefix bytes. */ |
9987 | for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++) | |
9988 | if (*q) | |
48ef937e | 9989 | frag_opcode_byte (*q); |
0f10071e | 9990 | } |
ae5c1c7b | 9991 | else |
c0f3af97 L |
9992 | { |
9993 | for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++) | |
9994 | if (*q) | |
9995 | switch (j) | |
9996 | { | |
c0f3af97 L |
9997 | case SEG_PREFIX: |
9998 | case ADDR_PREFIX: | |
48ef937e | 9999 | frag_opcode_byte (*q); |
c0f3af97 L |
10000 | break; |
10001 | default: | |
10002 | /* There should be no other prefixes for instructions | |
10003 | with VEX prefix. */ | |
10004 | abort (); | |
10005 | } | |
10006 | ||
43234a1e L |
10007 | /* For EVEX instructions i.vrex should become 0 after |
10008 | build_evex_prefix. For VEX instructions upper 16 registers | |
10009 | aren't available, so VREX should be 0. */ | |
10010 | if (i.vrex) | |
10011 | abort (); | |
c0f3af97 | 10012 | /* Now the VEX prefix. */ |
48ef937e JB |
10013 | if (now_seg != absolute_section) |
10014 | { | |
10015 | p = frag_more (i.vex.length); | |
10016 | for (j = 0; j < i.vex.length; j++) | |
10017 | p[j] = i.vex.bytes[j]; | |
10018 | } | |
10019 | else | |
10020 | abs_section_offset += i.vex.length; | |
c0f3af97 | 10021 | } |
252b5132 | 10022 | |
29b0f896 | 10023 | /* Now the opcode; be careful about word order here! */ |
389d00a5 JB |
10024 | j = i.opcode_length; |
10025 | if (!i.vex.length) | |
ddb62495 | 10026 | switch (i.tm.opcode_space) |
389d00a5 JB |
10027 | { |
10028 | case SPACE_BASE: | |
10029 | break; | |
10030 | case SPACE_0F: | |
10031 | ++j; | |
10032 | break; | |
10033 | case SPACE_0F38: | |
10034 | case SPACE_0F3A: | |
10035 | j += 2; | |
10036 | break; | |
10037 | default: | |
10038 | abort (); | |
10039 | } | |
10040 | ||
48ef937e | 10041 | if (now_seg == absolute_section) |
389d00a5 JB |
10042 | abs_section_offset += j; |
10043 | else if (j == 1) | |
29b0f896 AM |
10044 | { |
10045 | FRAG_APPEND_1_CHAR (i.tm.base_opcode); | |
10046 | } | |
10047 | else | |
10048 | { | |
389d00a5 JB |
10049 | p = frag_more (j); |
10050 | if (!i.vex.length | |
ddb62495 | 10051 | && i.tm.opcode_space != SPACE_BASE) |
389d00a5 JB |
10052 | { |
10053 | *p++ = 0x0f; | |
ddb62495 JB |
10054 | if (i.tm.opcode_space != SPACE_0F) |
10055 | *p++ = i.tm.opcode_space == SPACE_0F38 | |
389d00a5 JB |
10056 | ? 0x38 : 0x3a; |
10057 | } | |
10058 | ||
9a182d04 | 10059 | switch (i.opcode_length) |
331d2d0d | 10060 | { |
4dffcebc | 10061 | case 2: |
389d00a5 JB |
10062 | /* Put out high byte first: can't use md_number_to_chars! */ |
10063 | *p++ = (i.tm.base_opcode >> 8) & 0xff; | |
10064 | /* Fall through. */ | |
10065 | case 1: | |
10066 | *p = i.tm.base_opcode & 0xff; | |
4dffcebc L |
10067 | break; |
10068 | default: | |
10069 | abort (); | |
10070 | break; | |
331d2d0d | 10071 | } |
0f10071e | 10072 | |
29b0f896 | 10073 | } |
3e73aa7c | 10074 | |
29b0f896 | 10075 | /* Now the modrm byte and sib byte (if present). */ |
40fb9820 | 10076 | if (i.tm.opcode_modifier.modrm) |
29b0f896 | 10077 | { |
48ef937e JB |
10078 | frag_opcode_byte ((i.rm.regmem << 0) |
10079 | | (i.rm.reg << 3) | |
10080 | | (i.rm.mode << 6)); | |
29b0f896 AM |
10081 | /* If i.rm.regmem == ESP (4) |
10082 | && i.rm.mode != (Register mode) | |
10083 | && not 16 bit | |
10084 | ==> need second modrm byte. */ | |
10085 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING | |
10086 | && i.rm.mode != 3 | |
dc821c5f | 10087 | && !(i.base_reg && i.base_reg->reg_type.bitfield.word)) |
48ef937e JB |
10088 | frag_opcode_byte ((i.sib.base << 0) |
10089 | | (i.sib.index << 3) | |
10090 | | (i.sib.scale << 6)); | |
29b0f896 | 10091 | } |
3e73aa7c | 10092 | |
29b0f896 | 10093 | if (i.disp_operands) |
2bbd9c25 | 10094 | output_disp (insn_start_frag, insn_start_off); |
3e73aa7c | 10095 | |
29b0f896 | 10096 | if (i.imm_operands) |
2bbd9c25 | 10097 | output_imm (insn_start_frag, insn_start_off); |
9c33702b JB |
10098 | |
10099 | /* | |
10100 | * frag_now_fix () returning plain abs_section_offset when we're in the | |
10101 | * absolute section, and abs_section_offset not getting updated as data | |
10102 | * gets added to the frag breaks the logic below. | |
10103 | */ | |
10104 | if (now_seg != absolute_section) | |
10105 | { | |
10106 | j = encoding_length (insn_start_frag, insn_start_off, frag_more (0)); | |
10107 | if (j > 15) | |
10108 | as_warn (_("instruction length of %u bytes exceeds the limit of 15"), | |
10109 | j); | |
e379e5f3 L |
10110 | else if (fragP) |
10111 | { | |
10112 | /* NB: Don't add prefix with GOTPC relocation since | |
10113 | output_disp() above depends on the fixed encoding | |
10114 | length. Can't add prefix with TLS relocation since | |
10115 | it breaks TLS linker optimization. */ | |
10116 | unsigned int max = i.has_gotpc_tls_reloc ? 0 : 15 - j; | |
10117 | /* Prefix count on the current instruction. */ | |
10118 | unsigned int count = i.vex.length; | |
10119 | unsigned int k; | |
10120 | for (k = 0; k < ARRAY_SIZE (i.prefix); k++) | |
10121 | /* REX byte is encoded in VEX/EVEX prefix. */ | |
10122 | if (i.prefix[k] && (k != REX_PREFIX || !i.vex.length)) | |
10123 | count++; | |
10124 | ||
10125 | /* Count prefixes for extended opcode maps. */ | |
10126 | if (!i.vex.length) | |
ddb62495 | 10127 | switch (i.tm.opcode_space) |
e379e5f3 | 10128 | { |
389d00a5 | 10129 | case SPACE_BASE: |
e379e5f3 | 10130 | break; |
389d00a5 JB |
10131 | case SPACE_0F: |
10132 | count++; | |
e379e5f3 | 10133 | break; |
389d00a5 JB |
10134 | case SPACE_0F38: |
10135 | case SPACE_0F3A: | |
10136 | count += 2; | |
e379e5f3 L |
10137 | break; |
10138 | default: | |
10139 | abort (); | |
10140 | } | |
10141 | ||
10142 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
10143 | == BRANCH_PREFIX) | |
10144 | { | |
10145 | /* Set the maximum prefix size in BRANCH_PREFIX | |
10146 | frag. */ | |
10147 | if (fragP->tc_frag_data.max_bytes > max) | |
10148 | fragP->tc_frag_data.max_bytes = max; | |
10149 | if (fragP->tc_frag_data.max_bytes > count) | |
10150 | fragP->tc_frag_data.max_bytes -= count; | |
10151 | else | |
10152 | fragP->tc_frag_data.max_bytes = 0; | |
10153 | } | |
10154 | else | |
10155 | { | |
10156 | /* Remember the maximum prefix size in FUSED_JCC_PADDING | |
10157 | frag. */ | |
10158 | unsigned int max_prefix_size; | |
10159 | if (align_branch_prefix_size > max) | |
10160 | max_prefix_size = max; | |
10161 | else | |
10162 | max_prefix_size = align_branch_prefix_size; | |
10163 | if (max_prefix_size > count) | |
10164 | fragP->tc_frag_data.max_prefix_length | |
10165 | = max_prefix_size - count; | |
10166 | } | |
10167 | ||
10168 | /* Use existing segment prefix if possible. Use CS | |
10169 | segment prefix in 64-bit mode. In 32-bit mode, use SS | |
10170 | segment prefix with ESP/EBP base register and use DS | |
10171 | segment prefix without ESP/EBP base register. */ | |
10172 | if (i.prefix[SEG_PREFIX]) | |
10173 | fragP->tc_frag_data.default_prefix = i.prefix[SEG_PREFIX]; | |
10174 | else if (flag_code == CODE_64BIT) | |
10175 | fragP->tc_frag_data.default_prefix = CS_PREFIX_OPCODE; | |
10176 | else if (i.base_reg | |
10177 | && (i.base_reg->reg_num == 4 | |
10178 | || i.base_reg->reg_num == 5)) | |
10179 | fragP->tc_frag_data.default_prefix = SS_PREFIX_OPCODE; | |
10180 | else | |
10181 | fragP->tc_frag_data.default_prefix = DS_PREFIX_OPCODE; | |
10182 | } | |
9c33702b | 10183 | } |
29b0f896 | 10184 | } |
252b5132 | 10185 | |
e379e5f3 L |
10186 | /* NB: Don't work with COND_JUMP86 without i386. */ |
10187 | if (align_branch_power | |
10188 | && now_seg != absolute_section | |
10189 | && cpu_arch_flags.bitfield.cpui386) | |
10190 | { | |
10191 | /* Terminate each frag so that we can add prefix and check for | |
10192 | fused jcc. */ | |
10193 | frag_wane (frag_now); | |
10194 | frag_new (0); | |
10195 | } | |
10196 | ||
29b0f896 AM |
10197 | #ifdef DEBUG386 |
10198 | if (flag_debug) | |
10199 | { | |
7b81dfbb | 10200 | pi ("" /*line*/, &i); |
29b0f896 AM |
10201 | } |
10202 | #endif /* DEBUG386 */ | |
10203 | } | |
252b5132 | 10204 | |
e205caa7 L |
10205 | /* Return the size of the displacement operand N. */ |
10206 | ||
10207 | static int | |
10208 | disp_size (unsigned int n) | |
10209 | { | |
10210 | int size = 4; | |
43234a1e | 10211 | |
b5014f7a | 10212 | if (i.types[n].bitfield.disp64) |
40fb9820 L |
10213 | size = 8; |
10214 | else if (i.types[n].bitfield.disp8) | |
10215 | size = 1; | |
10216 | else if (i.types[n].bitfield.disp16) | |
10217 | size = 2; | |
e205caa7 L |
10218 | return size; |
10219 | } | |
10220 | ||
10221 | /* Return the size of the immediate operand N. */ | |
10222 | ||
10223 | static int | |
10224 | imm_size (unsigned int n) | |
10225 | { | |
10226 | int size = 4; | |
40fb9820 L |
10227 | if (i.types[n].bitfield.imm64) |
10228 | size = 8; | |
10229 | else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s) | |
10230 | size = 1; | |
10231 | else if (i.types[n].bitfield.imm16) | |
10232 | size = 2; | |
e205caa7 L |
10233 | return size; |
10234 | } | |
10235 | ||
29b0f896 | 10236 | static void |
64e74474 | 10237 | output_disp (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10238 | { |
10239 | char *p; | |
10240 | unsigned int n; | |
252b5132 | 10241 | |
29b0f896 AM |
10242 | for (n = 0; n < i.operands; n++) |
10243 | { | |
b5014f7a | 10244 | if (operand_type_check (i.types[n], disp)) |
29b0f896 | 10245 | { |
48ef937e JB |
10246 | int size = disp_size (n); |
10247 | ||
10248 | if (now_seg == absolute_section) | |
10249 | abs_section_offset += size; | |
10250 | else if (i.op[n].disps->X_op == O_constant) | |
29b0f896 | 10251 | { |
43234a1e | 10252 | offsetT val = i.op[n].disps->X_add_number; |
252b5132 | 10253 | |
629cfaf1 JB |
10254 | val = offset_in_range (val >> (size == 1 ? i.memshift : 0), |
10255 | size); | |
29b0f896 AM |
10256 | p = frag_more (size); |
10257 | md_number_to_chars (p, val, size); | |
10258 | } | |
10259 | else | |
10260 | { | |
f86103b7 | 10261 | enum bfd_reloc_code_real reloc_type; |
a775efc8 JB |
10262 | bool pcrel = (i.flags[n] & Operand_PCrel) != 0; |
10263 | bool sign = (flag_code == CODE_64BIT && size == 4 | |
10264 | && (!want_disp32 (&i.tm) | |
10265 | || (i.tm.opcode_modifier.jump && !i.jumpabsolute | |
10266 | && !i.types[n].bitfield.baseindex))) | |
10267 | || pcrel; | |
02a86693 | 10268 | fixS *fixP; |
29b0f896 | 10269 | |
e205caa7 | 10270 | /* We can't have 8 bit displacement here. */ |
9c2799c2 | 10271 | gas_assert (!i.types[n].bitfield.disp8); |
e205caa7 | 10272 | |
29b0f896 AM |
10273 | /* The PC relative address is computed relative |
10274 | to the instruction boundary, so in case immediate | |
10275 | fields follows, we need to adjust the value. */ | |
10276 | if (pcrel && i.imm_operands) | |
10277 | { | |
29b0f896 | 10278 | unsigned int n1; |
e205caa7 | 10279 | int sz = 0; |
252b5132 | 10280 | |
29b0f896 | 10281 | for (n1 = 0; n1 < i.operands; n1++) |
40fb9820 | 10282 | if (operand_type_check (i.types[n1], imm)) |
252b5132 | 10283 | { |
e205caa7 | 10284 | /* Only one immediate is allowed for PC |
e3bf0aad JB |
10285 | relative address, except with .insn. */ |
10286 | gas_assert (sz == 0 || dot_insn ()); | |
10287 | sz += imm_size (n1); | |
252b5132 | 10288 | } |
e3bf0aad | 10289 | /* We should find at least one immediate. */ |
9c2799c2 | 10290 | gas_assert (sz != 0); |
e3bf0aad | 10291 | i.op[n].disps->X_add_number -= sz; |
29b0f896 | 10292 | } |
520dc8e8 | 10293 | |
29b0f896 | 10294 | p = frag_more (size); |
d258b828 | 10295 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
d6ab8113 | 10296 | if (GOT_symbol |
2bbd9c25 | 10297 | && GOT_symbol == i.op[n].disps->X_add_symbol |
d6ab8113 | 10298 | && (((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10299 | || reloc_type == BFD_RELOC_X86_64_32S |
10300 | || (reloc_type == BFD_RELOC_64 | |
10301 | && object_64bit)) | |
d6ab8113 JB |
10302 | && (i.op[n].disps->X_op == O_symbol |
10303 | || (i.op[n].disps->X_op == O_add | |
10304 | && ((symbol_get_value_expression | |
10305 | (i.op[n].disps->X_op_symbol)->X_op) | |
10306 | == O_subtract)))) | |
10307 | || reloc_type == BFD_RELOC_32_PCREL)) | |
2bbd9c25 | 10308 | { |
4fa24527 | 10309 | if (!object_64bit) |
7b81dfbb AJ |
10310 | { |
10311 | reloc_type = BFD_RELOC_386_GOTPC; | |
5b7c81bd | 10312 | i.has_gotpc_tls_reloc = true; |
98da05bf | 10313 | i.op[n].disps->X_add_number += |
d583596c | 10314 | encoding_length (insn_start_frag, insn_start_off, p); |
7b81dfbb AJ |
10315 | } |
10316 | else if (reloc_type == BFD_RELOC_64) | |
10317 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
d6ab8113 | 10318 | else |
7b81dfbb AJ |
10319 | /* Don't do the adjustment for x86-64, as there |
10320 | the pcrel addressing is relative to the _next_ | |
10321 | insn, and that is taken care of in other code. */ | |
d6ab8113 | 10322 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
2bbd9c25 | 10323 | } |
e379e5f3 L |
10324 | else if (align_branch_power) |
10325 | { | |
10326 | switch (reloc_type) | |
10327 | { | |
10328 | case BFD_RELOC_386_TLS_GD: | |
10329 | case BFD_RELOC_386_TLS_LDM: | |
10330 | case BFD_RELOC_386_TLS_IE: | |
10331 | case BFD_RELOC_386_TLS_IE_32: | |
10332 | case BFD_RELOC_386_TLS_GOTIE: | |
10333 | case BFD_RELOC_386_TLS_GOTDESC: | |
10334 | case BFD_RELOC_386_TLS_DESC_CALL: | |
10335 | case BFD_RELOC_X86_64_TLSGD: | |
10336 | case BFD_RELOC_X86_64_TLSLD: | |
10337 | case BFD_RELOC_X86_64_GOTTPOFF: | |
10338 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: | |
10339 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
5b7c81bd | 10340 | i.has_gotpc_tls_reloc = true; |
e379e5f3 L |
10341 | default: |
10342 | break; | |
10343 | } | |
10344 | } | |
02a86693 L |
10345 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, |
10346 | size, i.op[n].disps, pcrel, | |
10347 | reloc_type); | |
eb19308f JB |
10348 | |
10349 | if (flag_code == CODE_64BIT && size == 4 && pcrel | |
10350 | && !i.prefix[ADDR_PREFIX]) | |
10351 | fixP->fx_signed = 1; | |
10352 | ||
02a86693 L |
10353 | /* Check for "call/jmp *mem", "mov mem, %reg", |
10354 | "test %reg, mem" and "binop mem, %reg" where binop | |
10355 | is one of adc, add, and, cmp, or, sbb, sub, xor | |
e60f4d3b L |
10356 | instructions without data prefix. Always generate |
10357 | R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */ | |
10358 | if (i.prefix[DATA_PREFIX] == 0 | |
10359 | && (generate_relax_relocations | |
10360 | || (!object_64bit | |
10361 | && i.rm.mode == 0 | |
10362 | && i.rm.regmem == 5)) | |
0cb4071e L |
10363 | && (i.rm.mode == 2 |
10364 | || (i.rm.mode == 0 && i.rm.regmem == 5)) | |
ddb62495 | 10365 | && i.tm.opcode_space == SPACE_BASE |
02a86693 L |
10366 | && ((i.operands == 1 |
10367 | && i.tm.base_opcode == 0xff | |
10368 | && (i.rm.reg == 2 || i.rm.reg == 4)) | |
10369 | || (i.operands == 2 | |
10370 | && (i.tm.base_opcode == 0x8b | |
10371 | || i.tm.base_opcode == 0x85 | |
2ae4c703 | 10372 | || (i.tm.base_opcode & ~0x38) == 0x03)))) |
02a86693 L |
10373 | { |
10374 | if (object_64bit) | |
10375 | { | |
10376 | fixP->fx_tcbit = i.rex != 0; | |
10377 | if (i.base_reg | |
e968fc9b | 10378 | && (i.base_reg->reg_num == RegIP)) |
02a86693 L |
10379 | fixP->fx_tcbit2 = 1; |
10380 | } | |
10381 | else | |
10382 | fixP->fx_tcbit2 = 1; | |
10383 | } | |
29b0f896 AM |
10384 | } |
10385 | } | |
10386 | } | |
10387 | } | |
252b5132 | 10388 | |
29b0f896 | 10389 | static void |
64e74474 | 10390 | output_imm (fragS *insn_start_frag, offsetT insn_start_off) |
29b0f896 AM |
10391 | { |
10392 | char *p; | |
10393 | unsigned int n; | |
252b5132 | 10394 | |
29b0f896 AM |
10395 | for (n = 0; n < i.operands; n++) |
10396 | { | |
40fb9820 | 10397 | if (operand_type_check (i.types[n], imm)) |
29b0f896 | 10398 | { |
48ef937e JB |
10399 | int size = imm_size (n); |
10400 | ||
10401 | if (now_seg == absolute_section) | |
10402 | abs_section_offset += size; | |
10403 | else if (i.op[n].imms->X_op == O_constant) | |
29b0f896 | 10404 | { |
29b0f896 | 10405 | offsetT val; |
b4cac588 | 10406 | |
29b0f896 AM |
10407 | val = offset_in_range (i.op[n].imms->X_add_number, |
10408 | size); | |
10409 | p = frag_more (size); | |
10410 | md_number_to_chars (p, val, size); | |
10411 | } | |
10412 | else | |
10413 | { | |
10414 | /* Not absolute_section. | |
10415 | Need a 32-bit fixup (don't support 8bit | |
10416 | non-absolute imms). Try to support other | |
10417 | sizes ... */ | |
f86103b7 | 10418 | enum bfd_reloc_code_real reloc_type; |
e205caa7 | 10419 | int sign; |
29b0f896 | 10420 | |
40fb9820 | 10421 | if (i.types[n].bitfield.imm32s |
a7d61044 | 10422 | && (i.suffix == QWORD_MNEM_SUFFIX |
c032bc4f JB |
10423 | || (!i.suffix && i.tm.opcode_modifier.no_lsuf) |
10424 | || dot_insn ())) | |
29b0f896 | 10425 | sign = 1; |
e205caa7 L |
10426 | else |
10427 | sign = 0; | |
520dc8e8 | 10428 | |
29b0f896 | 10429 | p = frag_more (size); |
d258b828 | 10430 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
f86103b7 | 10431 | |
2bbd9c25 JJ |
10432 | /* This is tough to explain. We end up with this one if we |
10433 | * have operands that look like | |
10434 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to | |
10435 | * obtain the absolute address of the GOT, and it is strongly | |
10436 | * preferable from a performance point of view to avoid using | |
10437 | * a runtime relocation for this. The actual sequence of | |
10438 | * instructions often look something like: | |
10439 | * | |
10440 | * call .L66 | |
10441 | * .L66: | |
10442 | * popl %ebx | |
10443 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx | |
10444 | * | |
10445 | * The call and pop essentially return the absolute address | |
10446 | * of the label .L66 and store it in %ebx. The linker itself | |
10447 | * will ultimately change the first operand of the addl so | |
10448 | * that %ebx points to the GOT, but to keep things simple, the | |
10449 | * .o file must have this operand set so that it generates not | |
10450 | * the absolute address of .L66, but the absolute address of | |
10451 | * itself. This allows the linker itself simply treat a GOTPC | |
10452 | * relocation as asking for a pcrel offset to the GOT to be | |
10453 | * added in, and the addend of the relocation is stored in the | |
10454 | * operand field for the instruction itself. | |
10455 | * | |
10456 | * Our job here is to fix the operand so that it would add | |
10457 | * the correct offset so that %ebx would point to itself. The | |
10458 | * thing that is tricky is that .-.L66 will point to the | |
10459 | * beginning of the instruction, so we need to further modify | |
10460 | * the operand so that it will point to itself. There are | |
10461 | * other cases where you have something like: | |
10462 | * | |
10463 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] | |
10464 | * | |
10465 | * and here no correction would be required. Internally in | |
10466 | * the assembler we treat operands of this form as not being | |
10467 | * pcrel since the '.' is explicitly mentioned, and I wonder | |
10468 | * whether it would simplify matters to do it this way. Who | |
10469 | * knows. In earlier versions of the PIC patches, the | |
10470 | * pcrel_adjust field was used to store the correction, but | |
10471 | * since the expression is not pcrel, I felt it would be | |
10472 | * confusing to do it this way. */ | |
10473 | ||
d6ab8113 | 10474 | if ((reloc_type == BFD_RELOC_32 |
7b81dfbb AJ |
10475 | || reloc_type == BFD_RELOC_X86_64_32S |
10476 | || reloc_type == BFD_RELOC_64) | |
29b0f896 AM |
10477 | && GOT_symbol |
10478 | && GOT_symbol == i.op[n].imms->X_add_symbol | |
10479 | && (i.op[n].imms->X_op == O_symbol | |
10480 | || (i.op[n].imms->X_op == O_add | |
10481 | && ((symbol_get_value_expression | |
10482 | (i.op[n].imms->X_op_symbol)->X_op) | |
10483 | == O_subtract)))) | |
10484 | { | |
4fa24527 | 10485 | if (!object_64bit) |
d6ab8113 | 10486 | reloc_type = BFD_RELOC_386_GOTPC; |
7b81dfbb | 10487 | else if (size == 4) |
d6ab8113 | 10488 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
7b81dfbb AJ |
10489 | else if (size == 8) |
10490 | reloc_type = BFD_RELOC_X86_64_GOTPC64; | |
5b7c81bd | 10491 | i.has_gotpc_tls_reloc = true; |
d583596c JB |
10492 | i.op[n].imms->X_add_number += |
10493 | encoding_length (insn_start_frag, insn_start_off, p); | |
29b0f896 | 10494 | } |
29b0f896 AM |
10495 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
10496 | i.op[n].imms, 0, reloc_type); | |
10497 | } | |
10498 | } | |
10499 | } | |
252b5132 RH |
10500 | } |
10501 | \f | |
d182319b JB |
10502 | /* x86_cons_fix_new is called via the expression parsing code when a |
10503 | reloc is needed. We use this hook to get the correct .got reloc. */ | |
d182319b JB |
10504 | static int cons_sign = -1; |
10505 | ||
10506 | void | |
e3bb37b5 | 10507 | x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, |
62ebcb5c | 10508 | expressionS *exp, bfd_reloc_code_real_type r) |
d182319b | 10509 | { |
d258b828 | 10510 | r = reloc (len, 0, cons_sign, r); |
d182319b JB |
10511 | |
10512 | #ifdef TE_PE | |
10513 | if (exp->X_op == O_secrel) | |
10514 | { | |
10515 | exp->X_op = O_symbol; | |
10516 | r = BFD_RELOC_32_SECREL; | |
10517 | } | |
145667f8 MH |
10518 | else if (exp->X_op == O_secidx) |
10519 | r = BFD_RELOC_16_SECIDX; | |
d182319b JB |
10520 | #endif |
10521 | ||
10522 | fix_new_exp (frag, off, len, exp, 0, r); | |
10523 | } | |
10524 | ||
357d1bd8 L |
10525 | /* Export the ABI address size for use by TC_ADDRESS_BYTES for the |
10526 | purpose of the `.dc.a' internal pseudo-op. */ | |
10527 | ||
10528 | int | |
10529 | x86_address_bytes (void) | |
10530 | { | |
10531 | if ((stdoutput->arch_info->mach & bfd_mach_x64_32)) | |
10532 | return 4; | |
10533 | return stdoutput->arch_info->bits_per_address / 8; | |
10534 | } | |
10535 | ||
deea4973 JB |
10536 | #if (!(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \ |
10537 | || defined (LEX_AT)) && !defined (TE_PE) | |
d258b828 | 10538 | # define lex_got(reloc, adjust, types) NULL |
718ddfc0 | 10539 | #else |
f3c180ae AM |
10540 | /* Parse operands of the form |
10541 | <symbol>@GOTOFF+<nnn> | |
10542 | and similar .plt or .got references. | |
10543 | ||
10544 | If we find one, set up the correct relocation in RELOC and copy the | |
10545 | input string, minus the `@GOTOFF' into a malloc'd buffer for | |
10546 | parsing by the calling routine. Return this buffer, and if ADJUST | |
10547 | is non-null set it to the length of the string we removed from the | |
10548 | input line. Otherwise return NULL. */ | |
10549 | static char * | |
91d6fa6a | 10550 | lex_got (enum bfd_reloc_code_real *rel, |
64e74474 | 10551 | int *adjust, |
d258b828 | 10552 | i386_operand_type *types) |
f3c180ae | 10553 | { |
7b81dfbb AJ |
10554 | /* Some of the relocations depend on the size of what field is to |
10555 | be relocated. But in our callers i386_immediate and i386_displacement | |
10556 | we don't yet know the operand size (this will be set by insn | |
10557 | matching). Hence we record the word32 relocation here, | |
10558 | and adjust the reloc according to the real size in reloc(). */ | |
145667f8 MH |
10559 | static const struct |
10560 | { | |
f3c180ae | 10561 | const char *str; |
cff8d58a | 10562 | int len; |
4fa24527 | 10563 | const enum bfd_reloc_code_real rel[2]; |
40fb9820 | 10564 | const i386_operand_type types64; |
5b7c81bd | 10565 | bool need_GOT_symbol; |
145667f8 MH |
10566 | } |
10567 | gotrel[] = | |
10568 | { | |
05909f23 JB |
10569 | |
10570 | #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \ | |
10571 | { .imm32 = 1, .imm32s = 1, .disp32 = 1 } } | |
10572 | #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \ | |
10573 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } } | |
10574 | #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \ | |
10575 | { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } } | |
10576 | #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \ | |
10577 | { .imm64 = 1, .disp64 = 1 } } | |
10578 | ||
deea4973 | 10579 | #ifndef TE_PE |
8ce3d284 | 10580 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8fd4256d L |
10581 | { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32, |
10582 | BFD_RELOC_SIZE32 }, | |
05909f23 | 10583 | { .bitfield = { .imm32 = 1, .imm64 = 1 } }, false }, |
8ce3d284 | 10584 | #endif |
cff8d58a L |
10585 | { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real, |
10586 | BFD_RELOC_X86_64_PLTOFF64 }, | |
05909f23 | 10587 | { .bitfield = { .imm64 = 1 } }, true }, |
cff8d58a L |
10588 | { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32, |
10589 | BFD_RELOC_X86_64_PLT32 }, | |
a775efc8 | 10590 | OPERAND_TYPE_IMM32_32S_DISP32, false }, |
cff8d58a L |
10591 | { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real, |
10592 | BFD_RELOC_X86_64_GOTPLT64 }, | |
5b7c81bd | 10593 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10594 | { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF, |
10595 | BFD_RELOC_X86_64_GOTOFF64 }, | |
5b7c81bd | 10596 | OPERAND_TYPE_IMM64_DISP64, true }, |
cff8d58a L |
10597 | { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real, |
10598 | BFD_RELOC_X86_64_GOTPCREL }, | |
a775efc8 | 10599 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10600 | { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD, |
10601 | BFD_RELOC_X86_64_TLSGD }, | |
a775efc8 | 10602 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10603 | { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM, |
10604 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10605 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10606 | { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real, |
10607 | BFD_RELOC_X86_64_TLSLD }, | |
a775efc8 | 10608 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10609 | { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32, |
10610 | BFD_RELOC_X86_64_GOTTPOFF }, | |
a775efc8 | 10611 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10612 | { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32, |
10613 | BFD_RELOC_X86_64_TPOFF32 }, | |
a775efc8 | 10614 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10615 | { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE, |
10616 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10617 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10618 | { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32, |
10619 | BFD_RELOC_X86_64_DTPOFF32 }, | |
a775efc8 | 10620 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, true }, |
cff8d58a L |
10621 | { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE, |
10622 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10623 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10624 | { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE, |
10625 | _dummy_first_bfd_reloc_code_real }, | |
5b7c81bd | 10626 | OPERAND_TYPE_NONE, true }, |
cff8d58a L |
10627 | { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32, |
10628 | BFD_RELOC_X86_64_GOT32 }, | |
a775efc8 | 10629 | OPERAND_TYPE_IMM32_32S_64_DISP32, true }, |
cff8d58a L |
10630 | { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC, |
10631 | BFD_RELOC_X86_64_GOTPC32_TLSDESC }, | |
a775efc8 | 10632 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
cff8d58a L |
10633 | { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL, |
10634 | BFD_RELOC_X86_64_TLSDESC_CALL }, | |
a775efc8 | 10635 | OPERAND_TYPE_IMM32_32S_DISP32, true }, |
deea4973 JB |
10636 | #else /* TE_PE */ |
10637 | { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL, | |
10638 | BFD_RELOC_32_SECREL }, | |
a775efc8 | 10639 | OPERAND_TYPE_IMM32_32S_64_DISP32_64, false }, |
deea4973 | 10640 | #endif |
05909f23 JB |
10641 | |
10642 | #undef OPERAND_TYPE_IMM32_32S_DISP32 | |
10643 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32 | |
10644 | #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64 | |
10645 | #undef OPERAND_TYPE_IMM64_DISP64 | |
10646 | ||
f3c180ae AM |
10647 | }; |
10648 | char *cp; | |
10649 | unsigned int j; | |
10650 | ||
deea4973 | 10651 | #if defined (OBJ_MAYBE_ELF) && !defined (TE_PE) |
718ddfc0 JB |
10652 | if (!IS_ELF) |
10653 | return NULL; | |
d382c579 | 10654 | #endif |
718ddfc0 | 10655 | |
f3c180ae | 10656 | for (cp = input_line_pointer; *cp != '@'; cp++) |
67c11a9b | 10657 | if (is_end_of_line[(unsigned char) *cp] || *cp == ',') |
f3c180ae AM |
10658 | return NULL; |
10659 | ||
47465058 | 10660 | for (j = 0; j < ARRAY_SIZE (gotrel); j++) |
f3c180ae | 10661 | { |
cff8d58a | 10662 | int len = gotrel[j].len; |
28f81592 | 10663 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
f3c180ae | 10664 | { |
4fa24527 | 10665 | if (gotrel[j].rel[object_64bit] != 0) |
f3c180ae | 10666 | { |
28f81592 AM |
10667 | int first, second; |
10668 | char *tmpbuf, *past_reloc; | |
f3c180ae | 10669 | |
91d6fa6a | 10670 | *rel = gotrel[j].rel[object_64bit]; |
f3c180ae | 10671 | |
3956db08 JB |
10672 | if (types) |
10673 | { | |
10674 | if (flag_code != CODE_64BIT) | |
40fb9820 L |
10675 | { |
10676 | types->bitfield.imm32 = 1; | |
10677 | types->bitfield.disp32 = 1; | |
10678 | } | |
3956db08 JB |
10679 | else |
10680 | *types = gotrel[j].types64; | |
10681 | } | |
10682 | ||
844bf810 | 10683 | if (gotrel[j].need_GOT_symbol && GOT_symbol == NULL) |
f3c180ae AM |
10684 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); |
10685 | ||
28f81592 | 10686 | /* The length of the first part of our input line. */ |
f3c180ae | 10687 | first = cp - input_line_pointer; |
28f81592 AM |
10688 | |
10689 | /* The second part goes from after the reloc token until | |
67c11a9b | 10690 | (and including) an end_of_line char or comma. */ |
28f81592 | 10691 | past_reloc = cp + 1 + len; |
67c11a9b AM |
10692 | cp = past_reloc; |
10693 | while (!is_end_of_line[(unsigned char) *cp] && *cp != ',') | |
10694 | ++cp; | |
10695 | second = cp + 1 - past_reloc; | |
28f81592 AM |
10696 | |
10697 | /* Allocate and copy string. The trailing NUL shouldn't | |
10698 | be necessary, but be safe. */ | |
add39d23 | 10699 | tmpbuf = XNEWVEC (char, first + second + 2); |
f3c180ae | 10700 | memcpy (tmpbuf, input_line_pointer, first); |
0787a12d AM |
10701 | if (second != 0 && *past_reloc != ' ') |
10702 | /* Replace the relocation token with ' ', so that | |
10703 | errors like foo@GOTOFF1 will be detected. */ | |
10704 | tmpbuf[first++] = ' '; | |
af89796a L |
10705 | else |
10706 | /* Increment length by 1 if the relocation token is | |
10707 | removed. */ | |
10708 | len++; | |
10709 | if (adjust) | |
10710 | *adjust = len; | |
0787a12d AM |
10711 | memcpy (tmpbuf + first, past_reloc, second); |
10712 | tmpbuf[first + second] = '\0'; | |
f3c180ae AM |
10713 | return tmpbuf; |
10714 | } | |
10715 | ||
4fa24527 JB |
10716 | as_bad (_("@%s reloc is not supported with %d-bit output format"), |
10717 | gotrel[j].str, 1 << (5 + object_64bit)); | |
f3c180ae AM |
10718 | return NULL; |
10719 | } | |
10720 | } | |
10721 | ||
10722 | /* Might be a symbol version string. Don't as_bad here. */ | |
10723 | return NULL; | |
10724 | } | |
4e4f7c87 | 10725 | #endif |
f3c180ae | 10726 | |
62ebcb5c | 10727 | bfd_reloc_code_real_type |
e3bb37b5 | 10728 | x86_cons (expressionS *exp, int size) |
f3c180ae | 10729 | { |
62ebcb5c AM |
10730 | bfd_reloc_code_real_type got_reloc = NO_RELOC; |
10731 | ||
6b50f5f4 JB |
10732 | intel_syntax = -intel_syntax; |
10733 | exp->X_md = 0; | |
5cc00775 | 10734 | expr_mode = expr_operator_none; |
6b50f5f4 | 10735 | |
2748c1b1 L |
10736 | #if ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ |
10737 | && !defined (LEX_AT)) \ | |
10738 | || defined (TE_PE) | |
4fa24527 | 10739 | if (size == 4 || (object_64bit && size == 8)) |
f3c180ae AM |
10740 | { |
10741 | /* Handle @GOTOFF and the like in an expression. */ | |
10742 | char *save; | |
10743 | char *gotfree_input_line; | |
4a57f2cf | 10744 | int adjust = 0; |
f3c180ae AM |
10745 | |
10746 | save = input_line_pointer; | |
d258b828 | 10747 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL); |
f3c180ae AM |
10748 | if (gotfree_input_line) |
10749 | input_line_pointer = gotfree_input_line; | |
10750 | ||
10751 | expression (exp); | |
10752 | ||
10753 | if (gotfree_input_line) | |
10754 | { | |
10755 | /* expression () has merrily parsed up to the end of line, | |
10756 | or a comma - in the wrong buffer. Transfer how far | |
10757 | input_line_pointer has moved to the right buffer. */ | |
10758 | input_line_pointer = (save | |
10759 | + (input_line_pointer - gotfree_input_line) | |
10760 | + adjust); | |
10761 | free (gotfree_input_line); | |
3992d3b7 AM |
10762 | if (exp->X_op == O_constant |
10763 | || exp->X_op == O_absent | |
10764 | || exp->X_op == O_illegal | |
0398aac5 | 10765 | || exp->X_op == O_register |
3992d3b7 AM |
10766 | || exp->X_op == O_big) |
10767 | { | |
10768 | char c = *input_line_pointer; | |
10769 | *input_line_pointer = 0; | |
10770 | as_bad (_("missing or invalid expression `%s'"), save); | |
10771 | *input_line_pointer = c; | |
10772 | } | |
b9519cfe L |
10773 | else if ((got_reloc == BFD_RELOC_386_PLT32 |
10774 | || got_reloc == BFD_RELOC_X86_64_PLT32) | |
10775 | && exp->X_op != O_symbol) | |
10776 | { | |
10777 | char c = *input_line_pointer; | |
10778 | *input_line_pointer = 0; | |
10779 | as_bad (_("invalid PLT expression `%s'"), save); | |
10780 | *input_line_pointer = c; | |
10781 | } | |
f3c180ae AM |
10782 | } |
10783 | } | |
10784 | else | |
6b50f5f4 | 10785 | #endif |
f3c180ae | 10786 | expression (exp); |
ee86248c JB |
10787 | |
10788 | intel_syntax = -intel_syntax; | |
10789 | ||
10790 | if (intel_syntax) | |
10791 | i386_intel_simplify (exp); | |
62ebcb5c | 10792 | |
a442cac5 | 10793 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ |
5cc00775 JB |
10794 | if (size <= 4 && expr_mode == expr_operator_present |
10795 | && exp->X_op == O_constant && !object_64bit) | |
a442cac5 JB |
10796 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
10797 | ||
62ebcb5c | 10798 | return got_reloc; |
f3c180ae | 10799 | } |
f3c180ae | 10800 | |
9f32dd5b L |
10801 | static void |
10802 | signed_cons (int size) | |
6482c264 | 10803 | { |
a442cac5 | 10804 | if (object_64bit) |
d182319b JB |
10805 | cons_sign = 1; |
10806 | cons (size); | |
10807 | cons_sign = -1; | |
6482c264 NC |
10808 | } |
10809 | ||
edd67638 JB |
10810 | static void |
10811 | s_insn (int dummy ATTRIBUTE_UNUSED) | |
10812 | { | |
393fbe8d | 10813 | char mnemonic[MAX_MNEM_SIZE], *line = input_line_pointer, *ptr; |
edd67638 JB |
10814 | char *saved_ilp = find_end_of_line (line, false), saved_char; |
10815 | const char *end; | |
10816 | unsigned int j; | |
10817 | valueT val; | |
10818 | bool vex = false, xop = false, evex = false; | |
10819 | static const templates tt = { &i.tm, &i.tm + 1 }; | |
10820 | ||
10821 | init_globals (); | |
10822 | ||
10823 | saved_char = *saved_ilp; | |
10824 | *saved_ilp = 0; | |
10825 | ||
10826 | end = parse_insn (line, mnemonic, true); | |
10827 | if (end == NULL) | |
10828 | { | |
10829 | bad: | |
10830 | *saved_ilp = saved_char; | |
10831 | ignore_rest_of_line (); | |
d0c2e3ec | 10832 | i.tm.mnem_off = 0; |
edd67638 JB |
10833 | return; |
10834 | } | |
10835 | line += end - line; | |
10836 | ||
10837 | current_templates = &tt; | |
10838 | i.tm.mnem_off = MN__insn; | |
393fbe8d | 10839 | i.tm.extension_opcode = None; |
edd67638 JB |
10840 | |
10841 | if (startswith (line, "VEX") | |
10842 | && (line[3] == '.' || is_space_char (line[3]))) | |
10843 | { | |
10844 | vex = true; | |
10845 | line += 3; | |
10846 | } | |
10847 | else if (startswith (line, "XOP") && ISDIGIT (line[3])) | |
10848 | { | |
10849 | char *e; | |
10850 | unsigned long n = strtoul (line + 3, &e, 16); | |
10851 | ||
10852 | if (e == line + 5 && n >= 0x08 && n <= 0x1f | |
10853 | && (*e == '.' || is_space_char (*e))) | |
10854 | { | |
10855 | xop = true; | |
d0c2e3ec JB |
10856 | /* Arrange for build_vex_prefix() to emit 0x8f. */ |
10857 | i.tm.opcode_space = SPACE_XOP08; | |
10858 | i.insn_opcode_space = n; | |
edd67638 JB |
10859 | line = e; |
10860 | } | |
10861 | } | |
10862 | else if (startswith (line, "EVEX") | |
10863 | && (line[4] == '.' || is_space_char (line[4]))) | |
10864 | { | |
10865 | evex = true; | |
10866 | line += 4; | |
10867 | } | |
10868 | ||
10869 | if (vex || xop | |
10870 | ? i.vec_encoding == vex_encoding_evex | |
10871 | : evex | |
10872 | ? i.vec_encoding == vex_encoding_vex | |
10873 | || i.vec_encoding == vex_encoding_vex3 | |
10874 | : i.vec_encoding != vex_encoding_default) | |
10875 | { | |
10876 | as_bad (_("pseudo-prefix conflicts with encoding specifier")); | |
10877 | goto bad; | |
10878 | } | |
10879 | ||
0ff3b7d0 JB |
10880 | if (line > end && i.vec_encoding == vex_encoding_default) |
10881 | i.vec_encoding = evex ? vex_encoding_evex : vex_encoding_vex; | |
10882 | ||
1adecddd JB |
10883 | if (i.vec_encoding != vex_encoding_default) |
10884 | { | |
10885 | /* Only address size and segment override prefixes are permitted with | |
10886 | VEX/XOP/EVEX encodings. */ | |
10887 | const unsigned char *p = i.prefix; | |
10888 | ||
10889 | for (j = 0; j < ARRAY_SIZE (i.prefix); ++j, ++p) | |
10890 | { | |
10891 | if (!*p) | |
10892 | continue; | |
10893 | ||
10894 | switch (j) | |
10895 | { | |
10896 | case SEG_PREFIX: | |
10897 | case ADDR_PREFIX: | |
10898 | break; | |
10899 | default: | |
10900 | as_bad (_("illegal prefix used with VEX/XOP/EVEX")); | |
10901 | goto bad; | |
10902 | } | |
10903 | } | |
10904 | } | |
10905 | ||
edd67638 JB |
10906 | if (line > end && *line == '.') |
10907 | { | |
d0c2e3ec JB |
10908 | /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */ |
10909 | switch (line[1]) | |
10910 | { | |
10911 | case 'L': | |
10912 | switch (line[2]) | |
10913 | { | |
10914 | case '0': | |
10915 | if (evex) | |
10916 | i.tm.opcode_modifier.evex = EVEX128; | |
10917 | else | |
10918 | i.tm.opcode_modifier.vex = VEX128; | |
10919 | break; | |
10920 | ||
10921 | case '1': | |
10922 | if (evex) | |
10923 | i.tm.opcode_modifier.evex = EVEX256; | |
10924 | else | |
10925 | i.tm.opcode_modifier.vex = VEX256; | |
10926 | break; | |
10927 | ||
10928 | case '2': | |
10929 | if (evex) | |
10930 | i.tm.opcode_modifier.evex = EVEX512; | |
10931 | break; | |
10932 | ||
10933 | case '3': | |
10934 | if (evex) | |
10935 | i.tm.opcode_modifier.evex = EVEX_L3; | |
10936 | break; | |
10937 | ||
10938 | case 'I': | |
10939 | if (line[3] == 'G') | |
10940 | { | |
10941 | if (evex) | |
10942 | i.tm.opcode_modifier.evex = EVEXLIG; | |
10943 | else | |
10944 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
10945 | ++line; | |
10946 | } | |
10947 | break; | |
10948 | } | |
10949 | ||
10950 | if (i.tm.opcode_modifier.vex || i.tm.opcode_modifier.evex) | |
10951 | line += 3; | |
10952 | break; | |
10953 | ||
10954 | case '1': | |
10955 | if (line[2] == '2' && line[3] == '8') | |
10956 | { | |
10957 | if (evex) | |
10958 | i.tm.opcode_modifier.evex = EVEX128; | |
10959 | else | |
10960 | i.tm.opcode_modifier.vex = VEX128; | |
10961 | line += 4; | |
10962 | } | |
10963 | break; | |
10964 | ||
10965 | case '2': | |
10966 | if (line[2] == '5' && line[3] == '6') | |
10967 | { | |
10968 | if (evex) | |
10969 | i.tm.opcode_modifier.evex = EVEX256; | |
10970 | else | |
10971 | i.tm.opcode_modifier.vex = VEX256; | |
10972 | line += 4; | |
10973 | } | |
10974 | break; | |
10975 | ||
10976 | case '5': | |
10977 | if (evex && line[2] == '1' && line[3] == '2') | |
10978 | { | |
10979 | i.tm.opcode_modifier.evex = EVEX512; | |
10980 | line += 4; | |
10981 | } | |
10982 | break; | |
10983 | } | |
10984 | } | |
10985 | ||
10986 | if (line > end && *line == '.') | |
10987 | { | |
10988 | /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */ | |
10989 | switch (line[1]) | |
10990 | { | |
10991 | case 'N': | |
10992 | if (line[2] == 'P') | |
10993 | line += 3; | |
10994 | break; | |
10995 | ||
10996 | case '6': | |
10997 | if (line[2] == '6') | |
10998 | { | |
10999 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0X66; | |
11000 | line += 3; | |
11001 | } | |
11002 | break; | |
11003 | ||
11004 | case 'F': case 'f': | |
11005 | if (line[2] == '3') | |
11006 | { | |
11007 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF3; | |
11008 | line += 3; | |
11009 | } | |
11010 | else if (line[2] == '2') | |
11011 | { | |
11012 | i.tm.opcode_modifier.opcodeprefix = PREFIX_0XF2; | |
11013 | line += 3; | |
11014 | } | |
11015 | break; | |
11016 | } | |
11017 | } | |
11018 | ||
11019 | if (line > end && !xop && *line == '.') | |
11020 | { | |
11021 | /* Encoding space (VEX.mmmmm, EVEX.mmmm). */ | |
11022 | switch (line[1]) | |
11023 | { | |
11024 | case '0': | |
11025 | if (TOUPPER (line[2]) != 'F') | |
11026 | break; | |
11027 | if (line[3] == '.' || is_space_char (line[3])) | |
11028 | { | |
11029 | i.insn_opcode_space = SPACE_0F; | |
11030 | line += 3; | |
11031 | } | |
11032 | else if (line[3] == '3' | |
11033 | && (line[4] == '8' || TOUPPER (line[4]) == 'A') | |
11034 | && (line[5] == '.' || is_space_char (line[5]))) | |
11035 | { | |
11036 | i.insn_opcode_space = line[4] == '8' ? SPACE_0F38 : SPACE_0F3A; | |
11037 | line += 5; | |
11038 | } | |
11039 | break; | |
11040 | ||
11041 | case 'M': | |
11042 | if (ISDIGIT (line[2]) && line[2] != '0') | |
11043 | { | |
11044 | char *e; | |
11045 | unsigned long n = strtoul (line + 2, &e, 10); | |
11046 | ||
11047 | if (n <= (evex ? 15 : 31) | |
11048 | && (*e == '.' || is_space_char (*e))) | |
11049 | { | |
11050 | i.insn_opcode_space = n; | |
11051 | line = e; | |
11052 | } | |
11053 | } | |
11054 | break; | |
11055 | } | |
11056 | } | |
11057 | ||
11058 | if (line > end && *line == '.' && line[1] == 'W') | |
11059 | { | |
11060 | /* VEX.W, XOP.W, EVEX.W */ | |
11061 | switch (line[2]) | |
11062 | { | |
11063 | case '0': | |
11064 | i.tm.opcode_modifier.vexw = VEXW0; | |
11065 | break; | |
11066 | ||
11067 | case '1': | |
11068 | i.tm.opcode_modifier.vexw = VEXW1; | |
11069 | break; | |
11070 | ||
11071 | case 'I': | |
11072 | if (line[3] == 'G') | |
11073 | { | |
11074 | i.tm.opcode_modifier.vexw = VEXWIG; | |
11075 | ++line; | |
11076 | } | |
11077 | break; | |
11078 | } | |
11079 | ||
11080 | if (i.tm.opcode_modifier.vexw) | |
11081 | line += 3; | |
11082 | } | |
11083 | ||
11084 | if (line > end && *line && !is_space_char (*line)) | |
11085 | { | |
11086 | /* Improve diagnostic a little. */ | |
11087 | if (*line == '.' && line[1] && !is_space_char (line[1])) | |
11088 | ++line; | |
11089 | goto done; | |
edd67638 JB |
11090 | } |
11091 | ||
393fbe8d JB |
11092 | /* Before processing the opcode expression, find trailing "+r" or |
11093 | "/<digit>" specifiers. */ | |
11094 | for (ptr = line; ; ++ptr) | |
11095 | { | |
11096 | unsigned long n; | |
11097 | char *e; | |
11098 | ||
11099 | ptr = strpbrk (ptr, "+/,"); | |
11100 | if (ptr == NULL || *ptr == ',') | |
11101 | break; | |
11102 | ||
11103 | if (*ptr == '+' && ptr[1] == 'r' | |
11104 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
11105 | { | |
11106 | *ptr = ' '; | |
11107 | ptr[1] = ' '; | |
11108 | i.short_form = true; | |
11109 | break; | |
11110 | } | |
11111 | ||
11112 | if (*ptr == '/' && ISDIGIT (ptr[1]) | |
11113 | && (n = strtoul (ptr + 1, &e, 8)) < 8 | |
11114 | && e == ptr + 2 | |
11115 | && (ptr[2] == ',' || (is_space_char (ptr[2]) && ptr[3] == ','))) | |
11116 | { | |
11117 | *ptr = ' '; | |
11118 | ptr[1] = ' '; | |
11119 | i.tm.extension_opcode = n; | |
11120 | i.tm.opcode_modifier.modrm = 1; | |
11121 | break; | |
11122 | } | |
11123 | } | |
11124 | ||
edd67638 JB |
11125 | input_line_pointer = line; |
11126 | val = get_absolute_expression (); | |
11127 | line = input_line_pointer; | |
11128 | ||
393fbe8d JB |
11129 | if (i.short_form && (val & 7)) |
11130 | as_warn ("`+r' assumes low three opcode bits to be clear"); | |
11131 | ||
edd67638 JB |
11132 | for (j = 1; j < sizeof(val); ++j) |
11133 | if (!(val >> (j * 8))) | |
11134 | break; | |
11135 | ||
11136 | /* Trim off a prefix if present. */ | |
11137 | if (j > 1 && !vex && !xop && !evex) | |
11138 | { | |
11139 | uint8_t byte = val >> ((j - 1) * 8); | |
11140 | ||
11141 | switch (byte) | |
11142 | { | |
11143 | case DATA_PREFIX_OPCODE: | |
11144 | case REPE_PREFIX_OPCODE: | |
11145 | case REPNE_PREFIX_OPCODE: | |
11146 | if (!add_prefix (byte)) | |
11147 | goto bad; | |
11148 | val &= ((uint64_t)1 << (--j * 8)) - 1; | |
11149 | break; | |
11150 | } | |
11151 | } | |
11152 | ||
11153 | /* Trim off encoding space. */ | |
d0c2e3ec | 11154 | if (j > 1 && !i.insn_opcode_space && (val >> ((j - 1) * 8)) == 0x0f) |
edd67638 JB |
11155 | { |
11156 | uint8_t byte = val >> ((--j - 1) * 8); | |
11157 | ||
d0c2e3ec | 11158 | i.insn_opcode_space = SPACE_0F; |
edd67638 JB |
11159 | switch (byte & -(j > 1)) |
11160 | { | |
11161 | case 0x38: | |
d0c2e3ec | 11162 | i.insn_opcode_space = SPACE_0F38; |
edd67638 JB |
11163 | --j; |
11164 | break; | |
11165 | case 0x3a: | |
d0c2e3ec | 11166 | i.insn_opcode_space = SPACE_0F3A; |
edd67638 JB |
11167 | --j; |
11168 | break; | |
11169 | } | |
d0c2e3ec | 11170 | i.tm.opcode_space = i.insn_opcode_space; |
edd67638 JB |
11171 | val &= ((uint64_t)1 << (j * 8)) - 1; |
11172 | } | |
d0c2e3ec JB |
11173 | if (!i.tm.opcode_space && (vex || evex)) |
11174 | /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5. | |
11175 | Also avoid hitting abort() there or in build_evex_prefix(). */ | |
11176 | i.tm.opcode_space = i.insn_opcode_space == SPACE_0F ? SPACE_0F | |
11177 | : SPACE_0F38; | |
edd67638 JB |
11178 | |
11179 | if (j > 2) | |
11180 | { | |
11181 | as_bad (_("opcode residual (%#"PRIx64") too wide"), (uint64_t) val); | |
11182 | goto bad; | |
11183 | } | |
11184 | i.opcode_length = j; | |
0ff3b7d0 JB |
11185 | |
11186 | /* Handle operands, if any. */ | |
11187 | if (*line == ',') | |
11188 | { | |
11189 | i386_operand_type combined; | |
f7377a91 | 11190 | expressionS *disp_exp = NULL; |
0ff3b7d0 JB |
11191 | bool changed; |
11192 | ||
f7377a91 JB |
11193 | i.memshift = -1; |
11194 | ||
0ff3b7d0 JB |
11195 | ptr = parse_operands (line + 1, &i386_mnemonics[MN__insn]); |
11196 | this_operand = -1; | |
11197 | if (!ptr) | |
11198 | goto bad; | |
11199 | line = ptr; | |
11200 | ||
11201 | if (!i.operands) | |
11202 | { | |
11203 | as_bad (_("expecting operand after ','; got nothing")); | |
11204 | goto done; | |
11205 | } | |
11206 | ||
11207 | if (i.mem_operands > 1) | |
11208 | { | |
11209 | as_bad (_("too many memory references for `%s'"), | |
11210 | &i386_mnemonics[MN__insn]); | |
11211 | goto done; | |
11212 | } | |
11213 | ||
11214 | /* Are we to emit ModR/M encoding? */ | |
11215 | if (!i.short_form | |
11216 | && (i.mem_operands | |
11217 | || i.reg_operands > (i.vec_encoding != vex_encoding_default) | |
11218 | || i.tm.extension_opcode != None)) | |
11219 | i.tm.opcode_modifier.modrm = 1; | |
11220 | ||
11221 | if (!i.tm.opcode_modifier.modrm | |
11222 | && (i.reg_operands | |
11223 | > i.short_form + 0U + (i.vec_encoding != vex_encoding_default) | |
11224 | || i.mem_operands)) | |
11225 | { | |
11226 | as_bad (_("too many register/memory operands")); | |
11227 | goto done; | |
11228 | } | |
11229 | ||
11230 | /* Enforce certain constraints on operands. */ | |
11231 | switch (i.reg_operands + i.mem_operands | |
11232 | + (i.tm.extension_opcode != None)) | |
11233 | { | |
11234 | case 0: | |
11235 | if (i.short_form) | |
11236 | { | |
11237 | as_bad (_("too few register/memory operands")); | |
11238 | goto done; | |
11239 | } | |
11240 | /* Fall through. */ | |
11241 | case 1: | |
11242 | if (i.tm.opcode_modifier.modrm) | |
11243 | { | |
11244 | as_bad (_("too few register/memory operands")); | |
11245 | goto done; | |
11246 | } | |
11247 | break; | |
11248 | ||
11249 | case 2: | |
11250 | break; | |
11251 | ||
11252 | case 4: | |
11253 | if (i.imm_operands | |
11254 | && (i.op[0].imms->X_op != O_constant | |
11255 | || !fits_in_imm4 (i.op[0].imms->X_add_number))) | |
11256 | { | |
11257 | as_bad (_("constant doesn't fit in %d bits"), evex ? 3 : 4); | |
11258 | goto done; | |
11259 | } | |
11260 | /* Fall through. */ | |
11261 | case 3: | |
11262 | if (i.vec_encoding != vex_encoding_default) | |
11263 | { | |
11264 | i.tm.opcode_modifier.vexvvvv = 1; | |
11265 | break; | |
11266 | } | |
11267 | /* Fall through. */ | |
11268 | default: | |
11269 | as_bad (_("too many register/memory operands")); | |
11270 | goto done; | |
11271 | } | |
11272 | ||
11273 | /* Bring operands into canonical order (imm, mem, reg). */ | |
11274 | do | |
11275 | { | |
11276 | changed = false; | |
11277 | ||
11278 | for (j = 1; j < i.operands; ++j) | |
11279 | { | |
11280 | if ((!operand_type_check (i.types[j - 1], imm) | |
11281 | && operand_type_check (i.types[j], imm)) | |
11282 | || (i.types[j - 1].bitfield.class != ClassNone | |
11283 | && i.types[j].bitfield.class == ClassNone)) | |
11284 | { | |
11285 | swap_2_operands (j - 1, j); | |
11286 | changed = true; | |
11287 | } | |
11288 | } | |
11289 | } | |
11290 | while (changed); | |
11291 | ||
11292 | /* For Intel syntax swap the order of register operands. */ | |
11293 | if (intel_syntax) | |
11294 | switch (i.reg_operands) | |
11295 | { | |
11296 | case 0: | |
11297 | case 1: | |
11298 | break; | |
11299 | ||
11300 | case 4: | |
11301 | swap_2_operands (i.imm_operands + i.mem_operands + 1, i.operands - 2); | |
11302 | /* Fall through. */ | |
11303 | case 3: | |
11304 | case 2: | |
11305 | swap_2_operands (i.imm_operands + i.mem_operands, i.operands - 1); | |
11306 | break; | |
11307 | ||
11308 | default: | |
11309 | abort (); | |
11310 | } | |
11311 | ||
11312 | /* Enforce constraints when using VSIB. */ | |
11313 | if (i.index_reg | |
11314 | && (i.index_reg->reg_type.bitfield.xmmword | |
11315 | || i.index_reg->reg_type.bitfield.ymmword | |
11316 | || i.index_reg->reg_type.bitfield.zmmword)) | |
11317 | { | |
11318 | if (i.vec_encoding == vex_encoding_default) | |
11319 | { | |
11320 | as_bad (_("VSIB unavailable with legacy encoding")); | |
11321 | goto done; | |
11322 | } | |
11323 | ||
11324 | if (i.vec_encoding == vex_encoding_evex | |
11325 | && i.reg_operands > 1) | |
11326 | { | |
11327 | /* We could allow two register operands, encoding the 2nd one in | |
11328 | an 8-bit immediate like for 4-register-operand insns, but that | |
11329 | would require ugly fiddling with process_operands() and/or | |
11330 | build_modrm_byte(). */ | |
11331 | as_bad (_("too many register operands with VSIB")); | |
11332 | goto done; | |
11333 | } | |
11334 | ||
11335 | i.tm.opcode_modifier.sib = 1; | |
11336 | } | |
11337 | ||
11338 | /* Establish operand size encoding. */ | |
11339 | operand_type_set (&combined, 0); | |
f7377a91 | 11340 | |
0ff3b7d0 JB |
11341 | for (j = i.imm_operands; j < i.operands; ++j) |
11342 | { | |
11343 | i.types[j].bitfield.instance = InstanceNone; | |
11344 | ||
11345 | if (operand_type_check (i.types[j], disp)) | |
f7377a91 JB |
11346 | { |
11347 | i.types[j].bitfield.baseindex = 1; | |
11348 | disp_exp = i.op[j].disps; | |
11349 | } | |
11350 | ||
11351 | if (evex && i.types[j].bitfield.baseindex) | |
11352 | { | |
11353 | unsigned int n = i.memshift; | |
11354 | ||
11355 | if (i.types[j].bitfield.byte) | |
11356 | n = 0; | |
11357 | else if (i.types[j].bitfield.word) | |
11358 | n = 1; | |
11359 | else if (i.types[j].bitfield.dword) | |
11360 | n = 2; | |
11361 | else if (i.types[j].bitfield.qword) | |
11362 | n = 3; | |
11363 | else if (i.types[j].bitfield.xmmword) | |
11364 | n = 4; | |
11365 | else if (i.types[j].bitfield.ymmword) | |
11366 | n = 5; | |
11367 | else if (i.types[j].bitfield.zmmword) | |
11368 | n = 6; | |
11369 | ||
11370 | if (i.memshift < 32 && n != i.memshift) | |
11371 | as_warn ("conflicting memory operand size specifiers"); | |
11372 | i.memshift = n; | |
11373 | } | |
0ff3b7d0 JB |
11374 | |
11375 | if ((i.broadcast.type || i.broadcast.bytes) | |
11376 | && j == i.broadcast.operand) | |
11377 | continue; | |
11378 | ||
11379 | combined = operand_type_or (combined, i.types[j]); | |
11380 | combined.bitfield.class = ClassNone; | |
11381 | } | |
11382 | ||
f7377a91 JB |
11383 | switch ((i.broadcast.type ? i.broadcast.type : 1) |
11384 | << (i.memshift < 32 ? i.memshift : 0)) | |
11385 | { | |
11386 | case 64: combined.bitfield.zmmword = 1; break; | |
11387 | case 32: combined.bitfield.ymmword = 1; break; | |
11388 | case 16: combined.bitfield.xmmword = 1; break; | |
11389 | case 8: combined.bitfield.qword = 1; break; | |
11390 | case 4: combined.bitfield.dword = 1; break; | |
11391 | } | |
11392 | ||
0ff3b7d0 JB |
11393 | if (i.vec_encoding == vex_encoding_default) |
11394 | { | |
11395 | if (flag_code == CODE_64BIT && combined.bitfield.qword) | |
11396 | i.rex |= REX_W; | |
11397 | else if ((flag_code == CODE_16BIT ? combined.bitfield.dword | |
11398 | : combined.bitfield.word) | |
11399 | && !add_prefix (DATA_PREFIX_OPCODE)) | |
11400 | goto done; | |
11401 | } | |
11402 | else if (!i.tm.opcode_modifier.vexw) | |
11403 | { | |
11404 | if (flag_code == CODE_64BIT) | |
11405 | { | |
11406 | if (combined.bitfield.qword) | |
11407 | i.tm.opcode_modifier.vexw = VEXW1; | |
11408 | else if (combined.bitfield.dword) | |
11409 | i.tm.opcode_modifier.vexw = VEXW0; | |
11410 | } | |
11411 | ||
11412 | if (!i.tm.opcode_modifier.vexw) | |
11413 | i.tm.opcode_modifier.vexw = VEXWIG; | |
11414 | } | |
11415 | ||
11416 | if (vex || xop) | |
11417 | { | |
11418 | if (!i.tm.opcode_modifier.vex) | |
11419 | { | |
11420 | if (combined.bitfield.ymmword) | |
11421 | i.tm.opcode_modifier.vex = VEX256; | |
11422 | else if (combined.bitfield.xmmword) | |
11423 | i.tm.opcode_modifier.vex = VEX128; | |
11424 | } | |
11425 | } | |
11426 | else if (evex) | |
11427 | { | |
11428 | if (!i.tm.opcode_modifier.evex) | |
11429 | { | |
11430 | /* Do _not_ consider AVX512VL here. */ | |
11431 | if (i.rounding.type != rc_none || combined.bitfield.zmmword) | |
11432 | i.tm.opcode_modifier.evex = EVEX512; | |
11433 | else if (combined.bitfield.ymmword) | |
11434 | i.tm.opcode_modifier.evex = EVEX256; | |
11435 | else if (combined.bitfield.xmmword) | |
11436 | i.tm.opcode_modifier.evex = EVEX128; | |
11437 | } | |
f7377a91 JB |
11438 | |
11439 | if (i.memshift >= 32) | |
11440 | { | |
11441 | unsigned int n = 0; | |
11442 | ||
11443 | switch (i.tm.opcode_modifier.evex) | |
11444 | { | |
11445 | case EVEX512: n = 64; break; | |
11446 | case EVEX256: n = 32; break; | |
11447 | case EVEX128: n = 16; break; | |
11448 | } | |
11449 | ||
11450 | if (i.broadcast.type) | |
11451 | n /= i.broadcast.type; | |
11452 | ||
11453 | if (n > 0) | |
11454 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
11455 | ++i.memshift; | |
11456 | else if (disp_exp != NULL && disp_exp->X_op == O_constant | |
11457 | && disp_exp->X_add_number != 0 | |
11458 | && i.disp_encoding != disp_encoding_32bit) | |
11459 | { | |
11460 | if (!quiet_warnings) | |
11461 | as_warn ("cannot determine memory operand size"); | |
11462 | i.disp_encoding = disp_encoding_32bit; | |
11463 | } | |
11464 | } | |
0ff3b7d0 JB |
11465 | } |
11466 | ||
f7377a91 JB |
11467 | if (i.memshift >= 32) |
11468 | i.memshift = 0; | |
11469 | else if (!evex) | |
11470 | i.vec_encoding = vex_encoding_error; | |
11471 | ||
0ff3b7d0 JB |
11472 | if (i.disp_operands && !optimize_disp (&i.tm)) |
11473 | goto done; | |
11474 | ||
c032bc4f JB |
11475 | /* Establish size for immediate operands. */ |
11476 | for (j = 0; j < i.imm_operands; ++j) | |
11477 | { | |
11478 | expressionS *expP = i.op[j].imms; | |
11479 | ||
11480 | gas_assert (operand_type_check (i.types[j], imm)); | |
11481 | operand_type_set (&i.types[j], 0); | |
11482 | ||
11483 | if (i.imm_bits[j] > 32) | |
11484 | i.types[j].bitfield.imm64 = 1; | |
11485 | else if (i.imm_bits[j] > 16) | |
11486 | { | |
11487 | if (flag_code == CODE_64BIT && (i.flags[j] & Operand_Signed)) | |
11488 | i.types[j].bitfield.imm32s = 1; | |
11489 | else | |
11490 | i.types[j].bitfield.imm32 = 1; | |
11491 | } | |
11492 | else if (i.imm_bits[j] > 8) | |
11493 | i.types[j].bitfield.imm16 = 1; | |
11494 | else if (i.imm_bits[j] > 0) | |
11495 | { | |
11496 | if (i.flags[j] & Operand_Signed) | |
11497 | i.types[j].bitfield.imm8s = 1; | |
11498 | else | |
11499 | i.types[j].bitfield.imm8 = 1; | |
11500 | } | |
11501 | else if (expP->X_op == O_constant) | |
11502 | { | |
11503 | i.types[j] = smallest_imm_type (expP->X_add_number); | |
11504 | i.types[j].bitfield.imm1 = 0; | |
11505 | /* Oddly enough imm_size() checks imm64 first, so the bit needs | |
11506 | zapping since smallest_imm_type() sets it unconditionally. */ | |
11507 | if (flag_code != CODE_64BIT) | |
11508 | { | |
11509 | i.types[j].bitfield.imm64 = 0; | |
11510 | i.types[j].bitfield.imm32s = 0; | |
11511 | i.types[j].bitfield.imm32 = 1; | |
11512 | } | |
11513 | else if (i.types[j].bitfield.imm32 || i.types[j].bitfield.imm32s) | |
11514 | i.types[j].bitfield.imm64 = 0; | |
11515 | } | |
11516 | else | |
11517 | /* Non-constant expressions are sized heuristically. */ | |
11518 | switch (flag_code) | |
11519 | { | |
11520 | case CODE_64BIT: i.types[j].bitfield.imm32s = 1; break; | |
11521 | case CODE_32BIT: i.types[j].bitfield.imm32 = 1; break; | |
11522 | case CODE_16BIT: i.types[j].bitfield.imm16 = 1; break; | |
11523 | } | |
11524 | } | |
11525 | ||
0ff3b7d0 JB |
11526 | for (j = 0; j < i.operands; ++j) |
11527 | i.tm.operand_types[j] = i.types[j]; | |
11528 | ||
11529 | process_operands (); | |
11530 | } | |
11531 | ||
11532 | /* Don't set opcode until after processing operands, to avoid any | |
11533 | potential special casing there. */ | |
11534 | i.tm.base_opcode |= val; | |
11535 | ||
11536 | if (i.vec_encoding == vex_encoding_error | |
11537 | || (i.vec_encoding != vex_encoding_evex | |
11538 | ? i.broadcast.type || i.broadcast.bytes | |
11539 | || i.rounding.type != rc_none | |
11540 | || i.mask.reg | |
11541 | : (i.broadcast.type || i.broadcast.bytes) | |
11542 | && i.rounding.type != rc_none)) | |
11543 | { | |
11544 | as_bad (_("conflicting .insn operands")); | |
11545 | goto done; | |
11546 | } | |
edd67638 | 11547 | |
d0c2e3ec JB |
11548 | if (vex || xop) |
11549 | { | |
11550 | if (!i.tm.opcode_modifier.vex) | |
11551 | i.tm.opcode_modifier.vex = VEXScalar; /* LIG */ | |
11552 | ||
11553 | build_vex_prefix (NULL); | |
11554 | i.rex &= REX_OPCODE; | |
11555 | } | |
11556 | else if (evex) | |
11557 | { | |
11558 | if (!i.tm.opcode_modifier.evex) | |
11559 | i.tm.opcode_modifier.evex = EVEXLIG; | |
11560 | ||
11561 | build_evex_prefix (); | |
11562 | i.rex &= REX_OPCODE; | |
11563 | } | |
0ff3b7d0 JB |
11564 | else if (i.rex != 0) |
11565 | add_prefix (REX_OPCODE | i.rex); | |
d0c2e3ec | 11566 | |
edd67638 JB |
11567 | output_insn (); |
11568 | ||
d0c2e3ec | 11569 | done: |
edd67638 JB |
11570 | *saved_ilp = saved_char; |
11571 | input_line_pointer = line; | |
11572 | ||
11573 | demand_empty_rest_of_line (); | |
d0c2e3ec JB |
11574 | |
11575 | /* Make sure dot_insn() won't yield "true" anymore. */ | |
11576 | i.tm.mnem_off = 0; | |
edd67638 JB |
11577 | } |
11578 | ||
d182319b | 11579 | #ifdef TE_PE |
6482c264 | 11580 | static void |
7016a5d5 | 11581 | pe_directive_secrel (int dummy ATTRIBUTE_UNUSED) |
6482c264 NC |
11582 | { |
11583 | expressionS exp; | |
11584 | ||
11585 | do | |
11586 | { | |
11587 | expression (&exp); | |
11588 | if (exp.X_op == O_symbol) | |
11589 | exp.X_op = O_secrel; | |
11590 | ||
11591 | emit_expr (&exp, 4); | |
11592 | } | |
11593 | while (*input_line_pointer++ == ','); | |
11594 | ||
11595 | input_line_pointer--; | |
11596 | demand_empty_rest_of_line (); | |
11597 | } | |
145667f8 MH |
11598 | |
11599 | static void | |
11600 | pe_directive_secidx (int dummy ATTRIBUTE_UNUSED) | |
11601 | { | |
11602 | expressionS exp; | |
11603 | ||
11604 | do | |
11605 | { | |
11606 | expression (&exp); | |
11607 | if (exp.X_op == O_symbol) | |
11608 | exp.X_op = O_secidx; | |
11609 | ||
11610 | emit_expr (&exp, 2); | |
11611 | } | |
11612 | while (*input_line_pointer++ == ','); | |
11613 | ||
11614 | input_line_pointer--; | |
11615 | demand_empty_rest_of_line (); | |
11616 | } | |
6482c264 NC |
11617 | #endif |
11618 | ||
7063667e JB |
11619 | /* Handle Rounding Control / SAE specifiers. */ |
11620 | ||
11621 | static char * | |
11622 | RC_SAE_specifier (const char *pstr) | |
11623 | { | |
11624 | unsigned int j; | |
11625 | ||
11626 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++) | |
11627 | { | |
11628 | if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len)) | |
11629 | { | |
11630 | if (i.rounding.type != rc_none) | |
11631 | { | |
11632 | as_bad (_("duplicated `{%s}'"), RC_NamesTable[j].name); | |
11633 | return NULL; | |
11634 | } | |
11635 | ||
11636 | i.rounding.type = RC_NamesTable[j].type; | |
11637 | ||
11638 | return (char *)(pstr + RC_NamesTable[j].len); | |
11639 | } | |
11640 | } | |
11641 | ||
11642 | return NULL; | |
11643 | } | |
11644 | ||
43234a1e L |
11645 | /* Handle Vector operations. */ |
11646 | ||
11647 | static char * | |
f70c6814 | 11648 | check_VecOperations (char *op_string) |
43234a1e L |
11649 | { |
11650 | const reg_entry *mask; | |
11651 | const char *saved; | |
11652 | char *end_op; | |
11653 | ||
f70c6814 | 11654 | while (*op_string) |
43234a1e L |
11655 | { |
11656 | saved = op_string; | |
11657 | if (*op_string == '{') | |
11658 | { | |
11659 | op_string++; | |
11660 | ||
11661 | /* Check broadcasts. */ | |
d34049e8 | 11662 | if (startswith (op_string, "1to")) |
43234a1e | 11663 | { |
5273a3cd | 11664 | unsigned int bcst_type; |
43234a1e | 11665 | |
5273a3cd | 11666 | if (i.broadcast.type) |
43234a1e L |
11667 | goto duplicated_vec_op; |
11668 | ||
11669 | op_string += 3; | |
11670 | if (*op_string == '8') | |
8e6e0792 | 11671 | bcst_type = 8; |
b28d1bda | 11672 | else if (*op_string == '4') |
8e6e0792 | 11673 | bcst_type = 4; |
b28d1bda | 11674 | else if (*op_string == '2') |
8e6e0792 | 11675 | bcst_type = 2; |
43234a1e L |
11676 | else if (*op_string == '1' |
11677 | && *(op_string+1) == '6') | |
11678 | { | |
8e6e0792 | 11679 | bcst_type = 16; |
43234a1e L |
11680 | op_string++; |
11681 | } | |
0cc78721 CL |
11682 | else if (*op_string == '3' |
11683 | && *(op_string+1) == '2') | |
11684 | { | |
11685 | bcst_type = 32; | |
11686 | op_string++; | |
11687 | } | |
43234a1e L |
11688 | else |
11689 | { | |
11690 | as_bad (_("Unsupported broadcast: `%s'"), saved); | |
11691 | return NULL; | |
11692 | } | |
11693 | op_string++; | |
11694 | ||
5273a3cd JB |
11695 | i.broadcast.type = bcst_type; |
11696 | i.broadcast.operand = this_operand; | |
f7377a91 JB |
11697 | |
11698 | /* For .insn a data size specifier may be appended. */ | |
11699 | if (dot_insn () && *op_string == ':') | |
11700 | goto dot_insn_modifier; | |
11701 | } | |
11702 | /* Check .insn special cases. */ | |
11703 | else if (dot_insn () && *op_string == ':') | |
11704 | { | |
11705 | dot_insn_modifier: | |
c032bc4f | 11706 | switch (op_string[1]) |
f7377a91 JB |
11707 | { |
11708 | unsigned long n; | |
11709 | ||
c032bc4f | 11710 | case 'd': |
f7377a91 JB |
11711 | if (i.memshift < 32) |
11712 | goto duplicated_vec_op; | |
11713 | ||
11714 | n = strtoul (op_string + 2, &end_op, 0); | |
11715 | if (n) | |
11716 | for (i.memshift = 0; !(n & 1); n >>= 1) | |
11717 | ++i.memshift; | |
11718 | if (i.memshift < 32 && n == 1) | |
11719 | op_string = end_op; | |
c032bc4f JB |
11720 | break; |
11721 | ||
11722 | case 's': case 'u': | |
11723 | /* This isn't really a "vector" operation, but a sign/size | |
11724 | specifier for immediate operands of .insn. Note that AT&T | |
11725 | syntax handles the same in i386_immediate(). */ | |
11726 | if (!intel_syntax) | |
11727 | break; | |
11728 | ||
11729 | if (i.imm_bits[this_operand]) | |
11730 | goto duplicated_vec_op; | |
11731 | ||
11732 | n = strtoul (op_string + 2, &end_op, 0); | |
11733 | if (n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
11734 | { | |
11735 | i.imm_bits[this_operand] = n; | |
11736 | if (op_string[1] == 's') | |
11737 | i.flags[this_operand] |= Operand_Signed; | |
11738 | op_string = end_op; | |
11739 | } | |
11740 | break; | |
f7377a91 | 11741 | } |
43234a1e L |
11742 | } |
11743 | /* Check masking operation. */ | |
11744 | else if ((mask = parse_register (op_string, &end_op)) != NULL) | |
11745 | { | |
8a6fb3f9 JB |
11746 | if (mask == &bad_reg) |
11747 | return NULL; | |
11748 | ||
43234a1e | 11749 | /* k0 can't be used for write mask. */ |
f74a6307 | 11750 | if (mask->reg_type.bitfield.class != RegMask || !mask->reg_num) |
43234a1e | 11751 | { |
6d2cd6b2 JB |
11752 | as_bad (_("`%s%s' can't be used for write mask"), |
11753 | register_prefix, mask->reg_name); | |
43234a1e L |
11754 | return NULL; |
11755 | } | |
11756 | ||
6225c532 | 11757 | if (!i.mask.reg) |
43234a1e | 11758 | { |
6225c532 JB |
11759 | i.mask.reg = mask; |
11760 | i.mask.operand = this_operand; | |
43234a1e | 11761 | } |
6225c532 JB |
11762 | else if (i.mask.reg->reg_num) |
11763 | goto duplicated_vec_op; | |
43234a1e L |
11764 | else |
11765 | { | |
6225c532 | 11766 | i.mask.reg = mask; |
43234a1e L |
11767 | |
11768 | /* Only "{z}" is allowed here. No need to check | |
11769 | zeroing mask explicitly. */ | |
6225c532 | 11770 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
11771 | { |
11772 | as_bad (_("invalid write mask `%s'"), saved); | |
11773 | return NULL; | |
11774 | } | |
11775 | } | |
11776 | ||
11777 | op_string = end_op; | |
11778 | } | |
11779 | /* Check zeroing-flag for masking operation. */ | |
11780 | else if (*op_string == 'z') | |
11781 | { | |
6225c532 | 11782 | if (!i.mask.reg) |
43234a1e | 11783 | { |
6225c532 JB |
11784 | i.mask.reg = reg_k0; |
11785 | i.mask.zeroing = 1; | |
11786 | i.mask.operand = this_operand; | |
43234a1e L |
11787 | } |
11788 | else | |
11789 | { | |
6225c532 | 11790 | if (i.mask.zeroing) |
43234a1e L |
11791 | { |
11792 | duplicated_vec_op: | |
11793 | as_bad (_("duplicated `%s'"), saved); | |
11794 | return NULL; | |
11795 | } | |
11796 | ||
6225c532 | 11797 | i.mask.zeroing = 1; |
43234a1e L |
11798 | |
11799 | /* Only "{%k}" is allowed here. No need to check mask | |
11800 | register explicitly. */ | |
6225c532 | 11801 | if (i.mask.operand != (unsigned int) this_operand) |
43234a1e L |
11802 | { |
11803 | as_bad (_("invalid zeroing-masking `%s'"), | |
11804 | saved); | |
11805 | return NULL; | |
11806 | } | |
11807 | } | |
11808 | ||
11809 | op_string++; | |
11810 | } | |
7063667e JB |
11811 | else if (intel_syntax |
11812 | && (op_string = RC_SAE_specifier (op_string)) != NULL) | |
11813 | i.rounding.modifier = true; | |
43234a1e L |
11814 | else |
11815 | goto unknown_vec_op; | |
11816 | ||
11817 | if (*op_string != '}') | |
11818 | { | |
11819 | as_bad (_("missing `}' in `%s'"), saved); | |
11820 | return NULL; | |
11821 | } | |
11822 | op_string++; | |
0ba3a731 L |
11823 | |
11824 | /* Strip whitespace since the addition of pseudo prefixes | |
11825 | changed how the scrubber treats '{'. */ | |
11826 | if (is_space_char (*op_string)) | |
11827 | ++op_string; | |
11828 | ||
43234a1e L |
11829 | continue; |
11830 | } | |
11831 | unknown_vec_op: | |
11832 | /* We don't know this one. */ | |
11833 | as_bad (_("unknown vector operation: `%s'"), saved); | |
11834 | return NULL; | |
11835 | } | |
11836 | ||
6225c532 | 11837 | if (i.mask.reg && i.mask.zeroing && !i.mask.reg->reg_num) |
6d2cd6b2 JB |
11838 | { |
11839 | as_bad (_("zeroing-masking only allowed with write mask")); | |
11840 | return NULL; | |
11841 | } | |
11842 | ||
43234a1e L |
11843 | return op_string; |
11844 | } | |
11845 | ||
252b5132 | 11846 | static int |
70e41ade | 11847 | i386_immediate (char *imm_start) |
252b5132 RH |
11848 | { |
11849 | char *save_input_line_pointer; | |
f3c180ae | 11850 | char *gotfree_input_line; |
252b5132 | 11851 | segT exp_seg = 0; |
47926f60 | 11852 | expressionS *exp; |
40fb9820 L |
11853 | i386_operand_type types; |
11854 | ||
0dfbf9d7 | 11855 | operand_type_set (&types, ~0); |
252b5132 RH |
11856 | |
11857 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS) | |
11858 | { | |
31b2323c L |
11859 | as_bad (_("at most %d immediate operands are allowed"), |
11860 | MAX_IMMEDIATE_OPERANDS); | |
252b5132 RH |
11861 | return 0; |
11862 | } | |
11863 | ||
11864 | exp = &im_expressions[i.imm_operands++]; | |
520dc8e8 | 11865 | i.op[this_operand].imms = exp; |
252b5132 RH |
11866 | |
11867 | if (is_space_char (*imm_start)) | |
11868 | ++imm_start; | |
11869 | ||
11870 | save_input_line_pointer = input_line_pointer; | |
11871 | input_line_pointer = imm_start; | |
11872 | ||
d258b828 | 11873 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
11874 | if (gotfree_input_line) |
11875 | input_line_pointer = gotfree_input_line; | |
252b5132 | 11876 | |
5cc00775 | 11877 | expr_mode = expr_operator_none; |
252b5132 RH |
11878 | exp_seg = expression (exp); |
11879 | ||
c032bc4f JB |
11880 | /* For .insn immediates there may be a size specifier. */ |
11881 | if (dot_insn () && *input_line_pointer == '{' && input_line_pointer[1] == ':' | |
11882 | && (input_line_pointer[2] == 's' || input_line_pointer[2] == 'u')) | |
11883 | { | |
11884 | char *e; | |
11885 | unsigned long n = strtoul (input_line_pointer + 3, &e, 0); | |
11886 | ||
11887 | if (*e == '}' && n && n <= (flag_code == CODE_64BIT ? 64 : 32)) | |
11888 | { | |
11889 | i.imm_bits[this_operand] = n; | |
11890 | if (input_line_pointer[2] == 's') | |
11891 | i.flags[this_operand] |= Operand_Signed; | |
11892 | input_line_pointer = e + 1; | |
11893 | } | |
11894 | } | |
11895 | ||
83183c0c | 11896 | SKIP_WHITESPACE (); |
252b5132 | 11897 | if (*input_line_pointer) |
f3c180ae | 11898 | as_bad (_("junk `%s' after expression"), input_line_pointer); |
252b5132 RH |
11899 | |
11900 | input_line_pointer = save_input_line_pointer; | |
f3c180ae | 11901 | if (gotfree_input_line) |
ee86248c JB |
11902 | { |
11903 | free (gotfree_input_line); | |
11904 | ||
9aac24b1 | 11905 | if (exp->X_op == O_constant) |
ee86248c JB |
11906 | exp->X_op = O_illegal; |
11907 | } | |
11908 | ||
9aac24b1 JB |
11909 | if (exp_seg == reg_section) |
11910 | { | |
11911 | as_bad (_("illegal immediate register operand %s"), imm_start); | |
11912 | return 0; | |
11913 | } | |
11914 | ||
ee86248c JB |
11915 | return i386_finalize_immediate (exp_seg, exp, types, imm_start); |
11916 | } | |
252b5132 | 11917 | |
ee86248c JB |
11918 | static int |
11919 | i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
11920 | i386_operand_type types, const char *imm_start) | |
11921 | { | |
11922 | if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big) | |
252b5132 | 11923 | { |
313c53d1 L |
11924 | if (imm_start) |
11925 | as_bad (_("missing or invalid immediate expression `%s'"), | |
11926 | imm_start); | |
3992d3b7 | 11927 | return 0; |
252b5132 | 11928 | } |
3e73aa7c | 11929 | else if (exp->X_op == O_constant) |
252b5132 | 11930 | { |
47926f60 | 11931 | /* Size it properly later. */ |
40fb9820 | 11932 | i.types[this_operand].bitfield.imm64 = 1; |
a442cac5 JB |
11933 | |
11934 | /* If not 64bit, sign/zero extend val, to account for wraparound | |
11935 | when !BFD64. */ | |
5cc00775 JB |
11936 | if (expr_mode == expr_operator_present |
11937 | && flag_code != CODE_64BIT && !object_64bit) | |
a442cac5 | 11938 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
252b5132 | 11939 | } |
4c63da97 | 11940 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
f86103b7 | 11941 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
31312f95 | 11942 | && exp_seg != absolute_section |
47926f60 | 11943 | && exp_seg != text_section |
24eab124 AM |
11944 | && exp_seg != data_section |
11945 | && exp_seg != bss_section | |
11946 | && exp_seg != undefined_section | |
f86103b7 | 11947 | && !bfd_is_com_section (exp_seg)) |
252b5132 | 11948 | { |
d0b47220 | 11949 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
252b5132 RH |
11950 | return 0; |
11951 | } | |
11952 | #endif | |
11953 | else | |
11954 | { | |
11955 | /* This is an address. The size of the address will be | |
24eab124 | 11956 | determined later, depending on destination register, |
3e73aa7c | 11957 | suffix, or the default for the section. */ |
40fb9820 L |
11958 | i.types[this_operand].bitfield.imm8 = 1; |
11959 | i.types[this_operand].bitfield.imm16 = 1; | |
11960 | i.types[this_operand].bitfield.imm32 = 1; | |
11961 | i.types[this_operand].bitfield.imm32s = 1; | |
11962 | i.types[this_operand].bitfield.imm64 = 1; | |
c6fb90c8 L |
11963 | i.types[this_operand] = operand_type_and (i.types[this_operand], |
11964 | types); | |
252b5132 RH |
11965 | } |
11966 | ||
11967 | return 1; | |
11968 | } | |
11969 | ||
551c1ca1 | 11970 | static char * |
e3bb37b5 | 11971 | i386_scale (char *scale) |
252b5132 | 11972 | { |
551c1ca1 AM |
11973 | offsetT val; |
11974 | char *save = input_line_pointer; | |
252b5132 | 11975 | |
551c1ca1 AM |
11976 | input_line_pointer = scale; |
11977 | val = get_absolute_expression (); | |
11978 | ||
11979 | switch (val) | |
252b5132 | 11980 | { |
551c1ca1 | 11981 | case 1: |
252b5132 RH |
11982 | i.log2_scale_factor = 0; |
11983 | break; | |
551c1ca1 | 11984 | case 2: |
252b5132 RH |
11985 | i.log2_scale_factor = 1; |
11986 | break; | |
551c1ca1 | 11987 | case 4: |
252b5132 RH |
11988 | i.log2_scale_factor = 2; |
11989 | break; | |
551c1ca1 | 11990 | case 8: |
252b5132 RH |
11991 | i.log2_scale_factor = 3; |
11992 | break; | |
11993 | default: | |
a724f0f4 JB |
11994 | { |
11995 | char sep = *input_line_pointer; | |
11996 | ||
11997 | *input_line_pointer = '\0'; | |
11998 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), | |
11999 | scale); | |
12000 | *input_line_pointer = sep; | |
12001 | input_line_pointer = save; | |
12002 | return NULL; | |
12003 | } | |
252b5132 | 12004 | } |
29b0f896 | 12005 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
252b5132 RH |
12006 | { |
12007 | as_warn (_("scale factor of %d without an index register"), | |
24eab124 | 12008 | 1 << i.log2_scale_factor); |
252b5132 | 12009 | i.log2_scale_factor = 0; |
252b5132 | 12010 | } |
551c1ca1 AM |
12011 | scale = input_line_pointer; |
12012 | input_line_pointer = save; | |
12013 | return scale; | |
252b5132 RH |
12014 | } |
12015 | ||
252b5132 | 12016 | static int |
e3bb37b5 | 12017 | i386_displacement (char *disp_start, char *disp_end) |
252b5132 | 12018 | { |
29b0f896 | 12019 | expressionS *exp; |
252b5132 RH |
12020 | segT exp_seg = 0; |
12021 | char *save_input_line_pointer; | |
f3c180ae | 12022 | char *gotfree_input_line; |
40fb9820 L |
12023 | int override; |
12024 | i386_operand_type bigdisp, types = anydisp; | |
3992d3b7 | 12025 | int ret; |
252b5132 | 12026 | |
31b2323c L |
12027 | if (i.disp_operands == MAX_MEMORY_OPERANDS) |
12028 | { | |
12029 | as_bad (_("at most %d displacement operands are allowed"), | |
12030 | MAX_MEMORY_OPERANDS); | |
12031 | return 0; | |
12032 | } | |
12033 | ||
0dfbf9d7 | 12034 | operand_type_set (&bigdisp, 0); |
6f2f06be | 12035 | if (i.jumpabsolute |
48bcea9f | 12036 | || i.types[this_operand].bitfield.baseindex |
0cfa3eb3 JB |
12037 | || (current_templates->start->opcode_modifier.jump != JUMP |
12038 | && current_templates->start->opcode_modifier.jump != JUMP_DWORD)) | |
e05278af | 12039 | { |
48bcea9f | 12040 | i386_addressing_mode (); |
e05278af | 12041 | override = (i.prefix[ADDR_PREFIX] != 0); |
40fb9820 L |
12042 | if (flag_code == CODE_64BIT) |
12043 | { | |
a775efc8 | 12044 | bigdisp.bitfield.disp32 = 1; |
40fb9820 | 12045 | if (!override) |
a775efc8 | 12046 | bigdisp.bitfield.disp64 = 1; |
40fb9820 L |
12047 | } |
12048 | else if ((flag_code == CODE_16BIT) ^ override) | |
40fb9820 | 12049 | bigdisp.bitfield.disp16 = 1; |
48bcea9f JB |
12050 | else |
12051 | bigdisp.bitfield.disp32 = 1; | |
e05278af JB |
12052 | } |
12053 | else | |
12054 | { | |
376cd056 JB |
12055 | /* For PC-relative branches, the width of the displacement may be |
12056 | dependent upon data size, but is never dependent upon address size. | |
12057 | Also make sure to not unintentionally match against a non-PC-relative | |
12058 | branch template. */ | |
12059 | static templates aux_templates; | |
12060 | const insn_template *t = current_templates->start; | |
5b7c81bd | 12061 | bool has_intel64 = false; |
376cd056 JB |
12062 | |
12063 | aux_templates.start = t; | |
12064 | while (++t < current_templates->end) | |
12065 | { | |
12066 | if (t->opcode_modifier.jump | |
12067 | != current_templates->start->opcode_modifier.jump) | |
12068 | break; | |
4b5aaf5f | 12069 | if ((t->opcode_modifier.isa64 >= INTEL64)) |
5b7c81bd | 12070 | has_intel64 = true; |
376cd056 JB |
12071 | } |
12072 | if (t < current_templates->end) | |
12073 | { | |
12074 | aux_templates.end = t; | |
12075 | current_templates = &aux_templates; | |
12076 | } | |
12077 | ||
e05278af | 12078 | override = (i.prefix[DATA_PREFIX] != 0); |
40fb9820 L |
12079 | if (flag_code == CODE_64BIT) |
12080 | { | |
376cd056 JB |
12081 | if ((override || i.suffix == WORD_MNEM_SUFFIX) |
12082 | && (!intel64 || !has_intel64)) | |
40fb9820 L |
12083 | bigdisp.bitfield.disp16 = 1; |
12084 | else | |
a775efc8 | 12085 | bigdisp.bitfield.disp32 = 1; |
40fb9820 L |
12086 | } |
12087 | else | |
e05278af JB |
12088 | { |
12089 | if (!override) | |
12090 | override = (i.suffix == (flag_code != CODE_16BIT | |
12091 | ? WORD_MNEM_SUFFIX | |
12092 | : LONG_MNEM_SUFFIX)); | |
40fb9820 L |
12093 | bigdisp.bitfield.disp32 = 1; |
12094 | if ((flag_code == CODE_16BIT) ^ override) | |
12095 | { | |
12096 | bigdisp.bitfield.disp32 = 0; | |
12097 | bigdisp.bitfield.disp16 = 1; | |
12098 | } | |
e05278af | 12099 | } |
e05278af | 12100 | } |
c6fb90c8 L |
12101 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
12102 | bigdisp); | |
252b5132 RH |
12103 | |
12104 | exp = &disp_expressions[i.disp_operands]; | |
520dc8e8 | 12105 | i.op[this_operand].disps = exp; |
252b5132 RH |
12106 | i.disp_operands++; |
12107 | save_input_line_pointer = input_line_pointer; | |
12108 | input_line_pointer = disp_start; | |
12109 | END_STRING_AND_SAVE (disp_end); | |
12110 | ||
12111 | #ifndef GCC_ASM_O_HACK | |
12112 | #define GCC_ASM_O_HACK 0 | |
12113 | #endif | |
12114 | #if GCC_ASM_O_HACK | |
12115 | END_STRING_AND_SAVE (disp_end + 1); | |
40fb9820 | 12116 | if (i.types[this_operand].bitfield.baseIndex |
24eab124 | 12117 | && displacement_string_end[-1] == '+') |
252b5132 RH |
12118 | { |
12119 | /* This hack is to avoid a warning when using the "o" | |
24eab124 AM |
12120 | constraint within gcc asm statements. |
12121 | For instance: | |
12122 | ||
12123 | #define _set_tssldt_desc(n,addr,limit,type) \ | |
12124 | __asm__ __volatile__ ( \ | |
12125 | "movw %w2,%0\n\t" \ | |
12126 | "movw %w1,2+%0\n\t" \ | |
12127 | "rorl $16,%1\n\t" \ | |
12128 | "movb %b1,4+%0\n\t" \ | |
12129 | "movb %4,5+%0\n\t" \ | |
12130 | "movb $0,6+%0\n\t" \ | |
12131 | "movb %h1,7+%0\n\t" \ | |
12132 | "rorl $16,%1" \ | |
12133 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) | |
12134 | ||
12135 | This works great except that the output assembler ends | |
12136 | up looking a bit weird if it turns out that there is | |
12137 | no offset. You end up producing code that looks like: | |
12138 | ||
12139 | #APP | |
12140 | movw $235,(%eax) | |
12141 | movw %dx,2+(%eax) | |
12142 | rorl $16,%edx | |
12143 | movb %dl,4+(%eax) | |
12144 | movb $137,5+(%eax) | |
12145 | movb $0,6+(%eax) | |
12146 | movb %dh,7+(%eax) | |
12147 | rorl $16,%edx | |
12148 | #NO_APP | |
12149 | ||
47926f60 | 12150 | So here we provide the missing zero. */ |
24eab124 AM |
12151 | |
12152 | *displacement_string_end = '0'; | |
252b5132 RH |
12153 | } |
12154 | #endif | |
d258b828 | 12155 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types); |
f3c180ae AM |
12156 | if (gotfree_input_line) |
12157 | input_line_pointer = gotfree_input_line; | |
252b5132 | 12158 | |
5cc00775 | 12159 | expr_mode = expr_operator_none; |
24eab124 | 12160 | exp_seg = expression (exp); |
252b5132 | 12161 | |
636c26b0 AM |
12162 | SKIP_WHITESPACE (); |
12163 | if (*input_line_pointer) | |
12164 | as_bad (_("junk `%s' after expression"), input_line_pointer); | |
12165 | #if GCC_ASM_O_HACK | |
12166 | RESTORE_END_STRING (disp_end + 1); | |
12167 | #endif | |
636c26b0 | 12168 | input_line_pointer = save_input_line_pointer; |
636c26b0 | 12169 | if (gotfree_input_line) |
ee86248c JB |
12170 | { |
12171 | free (gotfree_input_line); | |
12172 | ||
12173 | if (exp->X_op == O_constant || exp->X_op == O_register) | |
12174 | exp->X_op = O_illegal; | |
12175 | } | |
12176 | ||
12177 | ret = i386_finalize_displacement (exp_seg, exp, types, disp_start); | |
12178 | ||
12179 | RESTORE_END_STRING (disp_end); | |
12180 | ||
12181 | return ret; | |
12182 | } | |
12183 | ||
12184 | static int | |
12185 | i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp, | |
12186 | i386_operand_type types, const char *disp_start) | |
12187 | { | |
ee86248c | 12188 | int ret = 1; |
636c26b0 | 12189 | |
24eab124 AM |
12190 | /* We do this to make sure that the section symbol is in |
12191 | the symbol table. We will ultimately change the relocation | |
47926f60 | 12192 | to be relative to the beginning of the section. */ |
1ae12ab7 | 12193 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
d6ab8113 JB |
12194 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
12195 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) | |
24eab124 | 12196 | { |
636c26b0 | 12197 | if (exp->X_op != O_symbol) |
3992d3b7 | 12198 | goto inv_disp; |
636c26b0 | 12199 | |
e5cb08ac | 12200 | if (S_IS_LOCAL (exp->X_add_symbol) |
c64efb4b L |
12201 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section |
12202 | && S_GET_SEGMENT (exp->X_add_symbol) != expr_section) | |
24eab124 | 12203 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
24eab124 AM |
12204 | exp->X_op = O_subtract; |
12205 | exp->X_op_symbol = GOT_symbol; | |
1ae12ab7 | 12206 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
29b0f896 | 12207 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
d6ab8113 JB |
12208 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
12209 | i.reloc[this_operand] = BFD_RELOC_64; | |
23df1078 | 12210 | else |
29b0f896 | 12211 | i.reloc[this_operand] = BFD_RELOC_32; |
24eab124 | 12212 | } |
252b5132 | 12213 | |
3992d3b7 AM |
12214 | else if (exp->X_op == O_absent |
12215 | || exp->X_op == O_illegal | |
ee86248c | 12216 | || exp->X_op == O_big) |
2daf4fd8 | 12217 | { |
3992d3b7 AM |
12218 | inv_disp: |
12219 | as_bad (_("missing or invalid displacement expression `%s'"), | |
2daf4fd8 | 12220 | disp_start); |
3992d3b7 | 12221 | ret = 0; |
2daf4fd8 AM |
12222 | } |
12223 | ||
a50187b2 JB |
12224 | else if (exp->X_op == O_constant) |
12225 | { | |
12226 | /* Sizing gets taken care of by optimize_disp(). | |
12227 | ||
12228 | If not 64bit, sign/zero extend val, to account for wraparound | |
12229 | when !BFD64. */ | |
5cc00775 JB |
12230 | if (expr_mode == expr_operator_present |
12231 | && flag_code != CODE_64BIT && !object_64bit) | |
a50187b2 JB |
12232 | exp->X_add_number = extend_to_32bit_address (exp->X_add_number); |
12233 | } | |
12234 | ||
4c63da97 | 12235 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
a50187b2 | 12236 | else if (OUTPUT_FLAVOR == bfd_target_aout_flavour |
3992d3b7 AM |
12237 | && exp_seg != absolute_section |
12238 | && exp_seg != text_section | |
12239 | && exp_seg != data_section | |
12240 | && exp_seg != bss_section | |
12241 | && exp_seg != undefined_section | |
12242 | && !bfd_is_com_section (exp_seg)) | |
24eab124 | 12243 | { |
d0b47220 | 12244 | as_bad (_("unimplemented segment %s in operand"), exp_seg->name); |
3992d3b7 | 12245 | ret = 0; |
24eab124 | 12246 | } |
252b5132 | 12247 | #endif |
3956db08 | 12248 | |
a50187b2 | 12249 | else if (current_templates->start->opcode_modifier.jump == JUMP_BYTE) |
48bcea9f JB |
12250 | i.types[this_operand].bitfield.disp8 = 1; |
12251 | ||
40fb9820 | 12252 | /* Check if this is a displacement only operand. */ |
02b83698 JB |
12253 | if (!i.types[this_operand].bitfield.baseindex) |
12254 | i.types[this_operand] = | |
12255 | operand_type_or (operand_type_and_not (i.types[this_operand], anydisp), | |
12256 | operand_type_and (i.types[this_operand], types)); | |
3956db08 | 12257 | |
3992d3b7 | 12258 | return ret; |
252b5132 RH |
12259 | } |
12260 | ||
2abc2bec JB |
12261 | /* Return the active addressing mode, taking address override and |
12262 | registers forming the address into consideration. Update the | |
12263 | address override prefix if necessary. */ | |
47926f60 | 12264 | |
2abc2bec JB |
12265 | static enum flag_code |
12266 | i386_addressing_mode (void) | |
252b5132 | 12267 | { |
be05d201 L |
12268 | enum flag_code addr_mode; |
12269 | ||
12270 | if (i.prefix[ADDR_PREFIX]) | |
12271 | addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT; | |
a23b33b3 | 12272 | else if (flag_code == CODE_16BIT |
734dfd1c | 12273 | && is_cpu (current_templates->start, CpuMPX) |
a23b33b3 JB |
12274 | /* Avoid replacing the "16-bit addressing not allowed" diagnostic |
12275 | from md_assemble() by "is not a valid base/index expression" | |
12276 | when there is a base and/or index. */ | |
12277 | && !i.types[this_operand].bitfield.baseindex) | |
12278 | { | |
12279 | /* MPX insn memory operands with neither base nor index must be forced | |
12280 | to use 32-bit addressing in 16-bit mode. */ | |
12281 | addr_mode = CODE_32BIT; | |
12282 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
12283 | ++i.prefixes; | |
12284 | gas_assert (!i.types[this_operand].bitfield.disp16); | |
12285 | gas_assert (!i.types[this_operand].bitfield.disp32); | |
12286 | } | |
be05d201 L |
12287 | else |
12288 | { | |
12289 | addr_mode = flag_code; | |
12290 | ||
24eab124 | 12291 | #if INFER_ADDR_PREFIX |
be05d201 L |
12292 | if (i.mem_operands == 0) |
12293 | { | |
12294 | /* Infer address prefix from the first memory operand. */ | |
12295 | const reg_entry *addr_reg = i.base_reg; | |
12296 | ||
12297 | if (addr_reg == NULL) | |
12298 | addr_reg = i.index_reg; | |
eecb386c | 12299 | |
be05d201 L |
12300 | if (addr_reg) |
12301 | { | |
e968fc9b | 12302 | if (addr_reg->reg_type.bitfield.dword) |
be05d201 L |
12303 | addr_mode = CODE_32BIT; |
12304 | else if (flag_code != CODE_64BIT | |
dc821c5f | 12305 | && addr_reg->reg_type.bitfield.word) |
be05d201 L |
12306 | addr_mode = CODE_16BIT; |
12307 | ||
12308 | if (addr_mode != flag_code) | |
12309 | { | |
12310 | i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; | |
12311 | i.prefixes += 1; | |
12312 | /* Change the size of any displacement too. At most one | |
12313 | of Disp16 or Disp32 is set. | |
12314 | FIXME. There doesn't seem to be any real need for | |
12315 | separate Disp16 and Disp32 flags. The same goes for | |
12316 | Imm16 and Imm32. Removing them would probably clean | |
12317 | up the code quite a lot. */ | |
12318 | if (flag_code != CODE_64BIT | |
12319 | && (i.types[this_operand].bitfield.disp16 | |
12320 | || i.types[this_operand].bitfield.disp32)) | |
05909f23 JB |
12321 | { |
12322 | static const i386_operand_type disp16_32 = { | |
12323 | .bitfield = { .disp16 = 1, .disp32 = 1 } | |
12324 | }; | |
12325 | ||
12326 | i.types[this_operand] | |
12327 | = operand_type_xor (i.types[this_operand], disp16_32); | |
12328 | } | |
be05d201 L |
12329 | } |
12330 | } | |
12331 | } | |
24eab124 | 12332 | #endif |
be05d201 L |
12333 | } |
12334 | ||
2abc2bec JB |
12335 | return addr_mode; |
12336 | } | |
12337 | ||
12338 | /* Make sure the memory operand we've been dealt is valid. | |
12339 | Return 1 on success, 0 on a failure. */ | |
12340 | ||
12341 | static int | |
12342 | i386_index_check (const char *operand_string) | |
12343 | { | |
12344 | const char *kind = "base/index"; | |
12345 | enum flag_code addr_mode = i386_addressing_mode (); | |
77a19f0e | 12346 | const insn_template *t = current_templates->end - 1; |
2abc2bec | 12347 | |
77a19f0e | 12348 | if (t->opcode_modifier.isstring) |
fc0763e6 JB |
12349 | { |
12350 | /* Memory operands of string insns are special in that they only allow | |
12351 | a single register (rDI, rSI, or rBX) as their memory address. */ | |
be05d201 | 12352 | const reg_entry *expected_reg; |
069a1561 | 12353 | static const char di_si[][2][4] = |
be05d201 L |
12354 | { |
12355 | { "esi", "edi" }, | |
12356 | { "si", "di" }, | |
12357 | { "rsi", "rdi" } | |
12358 | }; | |
069a1561 | 12359 | static const char bx[][4] = { "ebx", "bx", "rbx" }; |
fc0763e6 JB |
12360 | |
12361 | kind = "string address"; | |
12362 | ||
a152332d | 12363 | if (t->opcode_modifier.prefixok == PrefixRep) |
fc0763e6 | 12364 | { |
77a19f0e | 12365 | int es_op = t->opcode_modifier.isstring - IS_STRING_ES_OP0; |
51c8edf6 | 12366 | int op = 0; |
fc0763e6 | 12367 | |
77a19f0e | 12368 | if (!t->operand_types[0].bitfield.baseindex |
fc0763e6 | 12369 | || ((!i.mem_operands != !intel_syntax) |
77a19f0e | 12370 | && t->operand_types[1].bitfield.baseindex)) |
51c8edf6 | 12371 | op = 1; |
fe0e921f AM |
12372 | expected_reg |
12373 | = (const reg_entry *) str_hash_find (reg_hash, | |
12374 | di_si[addr_mode][op == es_op]); | |
fc0763e6 JB |
12375 | } |
12376 | else | |
fe0e921f AM |
12377 | expected_reg |
12378 | = (const reg_entry *)str_hash_find (reg_hash, bx[addr_mode]); | |
fc0763e6 | 12379 | |
be05d201 L |
12380 | if (i.base_reg != expected_reg |
12381 | || i.index_reg | |
fc0763e6 | 12382 | || operand_type_check (i.types[this_operand], disp)) |
fc0763e6 | 12383 | { |
be05d201 L |
12384 | /* The second memory operand must have the same size as |
12385 | the first one. */ | |
12386 | if (i.mem_operands | |
12387 | && i.base_reg | |
12388 | && !((addr_mode == CODE_64BIT | |
dc821c5f | 12389 | && i.base_reg->reg_type.bitfield.qword) |
be05d201 | 12390 | || (addr_mode == CODE_32BIT |
dc821c5f JB |
12391 | ? i.base_reg->reg_type.bitfield.dword |
12392 | : i.base_reg->reg_type.bitfield.word))) | |
be05d201 L |
12393 | goto bad_address; |
12394 | ||
fc0763e6 JB |
12395 | as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"), |
12396 | operand_string, | |
12397 | intel_syntax ? '[' : '(', | |
12398 | register_prefix, | |
be05d201 | 12399 | expected_reg->reg_name, |
fc0763e6 | 12400 | intel_syntax ? ']' : ')'); |
be05d201 | 12401 | return 1; |
fc0763e6 | 12402 | } |
be05d201 L |
12403 | else |
12404 | return 1; | |
12405 | ||
dc1e8a47 | 12406 | bad_address: |
be05d201 L |
12407 | as_bad (_("`%s' is not a valid %s expression"), |
12408 | operand_string, kind); | |
12409 | return 0; | |
3e73aa7c JH |
12410 | } |
12411 | else | |
12412 | { | |
77a19f0e JB |
12413 | t = current_templates->start; |
12414 | ||
be05d201 L |
12415 | if (addr_mode != CODE_16BIT) |
12416 | { | |
12417 | /* 32-bit/64-bit checks. */ | |
41eb8e88 L |
12418 | if (i.disp_encoding == disp_encoding_16bit) |
12419 | { | |
12420 | bad_disp: | |
12421 | as_bad (_("invalid `%s' prefix"), | |
12422 | addr_mode == CODE_16BIT ? "{disp32}" : "{disp16}"); | |
12423 | return 0; | |
12424 | } | |
12425 | ||
be05d201 | 12426 | if ((i.base_reg |
e968fc9b JB |
12427 | && ((addr_mode == CODE_64BIT |
12428 | ? !i.base_reg->reg_type.bitfield.qword | |
12429 | : !i.base_reg->reg_type.bitfield.dword) | |
12430 | || (i.index_reg && i.base_reg->reg_num == RegIP) | |
12431 | || i.base_reg->reg_num == RegIZ)) | |
be05d201 | 12432 | || (i.index_reg |
1b54b8d7 JB |
12433 | && !i.index_reg->reg_type.bitfield.xmmword |
12434 | && !i.index_reg->reg_type.bitfield.ymmword | |
12435 | && !i.index_reg->reg_type.bitfield.zmmword | |
be05d201 | 12436 | && ((addr_mode == CODE_64BIT |
e968fc9b JB |
12437 | ? !i.index_reg->reg_type.bitfield.qword |
12438 | : !i.index_reg->reg_type.bitfield.dword) | |
be05d201 L |
12439 | || !i.index_reg->reg_type.bitfield.baseindex))) |
12440 | goto bad_address; | |
8178be5b | 12441 | |
260cd341 | 12442 | /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */ |
7fc69528 JB |
12443 | if (t->mnem_off == MN_bndmk |
12444 | || t->mnem_off == MN_bndldx | |
12445 | || t->mnem_off == MN_bndstx | |
a152332d | 12446 | || t->opcode_modifier.sib == SIBMEM) |
8178be5b JB |
12447 | { |
12448 | /* They cannot use RIP-relative addressing. */ | |
e968fc9b | 12449 | if (i.base_reg && i.base_reg->reg_num == RegIP) |
8178be5b JB |
12450 | { |
12451 | as_bad (_("`%s' cannot be used here"), operand_string); | |
12452 | return 0; | |
12453 | } | |
12454 | ||
12455 | /* bndldx and bndstx ignore their scale factor. */ | |
7fc69528 | 12456 | if ((t->mnem_off == MN_bndldx || t->mnem_off == MN_bndstx) |
8178be5b JB |
12457 | && i.log2_scale_factor) |
12458 | as_warn (_("register scaling is being ignored here")); | |
12459 | } | |
be05d201 L |
12460 | } |
12461 | else | |
3e73aa7c | 12462 | { |
be05d201 | 12463 | /* 16-bit checks. */ |
41eb8e88 L |
12464 | if (i.disp_encoding == disp_encoding_32bit) |
12465 | goto bad_disp; | |
12466 | ||
3e73aa7c | 12467 | if ((i.base_reg |
dc821c5f | 12468 | && (!i.base_reg->reg_type.bitfield.word |
40fb9820 | 12469 | || !i.base_reg->reg_type.bitfield.baseindex)) |
3e73aa7c | 12470 | || (i.index_reg |
dc821c5f | 12471 | && (!i.index_reg->reg_type.bitfield.word |
40fb9820 | 12472 | || !i.index_reg->reg_type.bitfield.baseindex |
29b0f896 AM |
12473 | || !(i.base_reg |
12474 | && i.base_reg->reg_num < 6 | |
12475 | && i.index_reg->reg_num >= 6 | |
12476 | && i.log2_scale_factor == 0)))) | |
be05d201 | 12477 | goto bad_address; |
3e73aa7c JH |
12478 | } |
12479 | } | |
be05d201 | 12480 | return 1; |
24eab124 | 12481 | } |
252b5132 | 12482 | |
43234a1e L |
12483 | /* Handle vector immediates. */ |
12484 | ||
12485 | static int | |
12486 | RC_SAE_immediate (const char *imm_start) | |
12487 | { | |
43234a1e | 12488 | const char *pstr = imm_start; |
43234a1e L |
12489 | |
12490 | if (*pstr != '{') | |
12491 | return 0; | |
12492 | ||
7063667e JB |
12493 | pstr = RC_SAE_specifier (pstr + 1); |
12494 | if (pstr == NULL) | |
43234a1e L |
12495 | return 0; |
12496 | ||
12497 | if (*pstr++ != '}') | |
12498 | { | |
12499 | as_bad (_("Missing '}': '%s'"), imm_start); | |
12500 | return 0; | |
12501 | } | |
12502 | /* RC/SAE immediate string should contain nothing more. */; | |
12503 | if (*pstr != 0) | |
12504 | { | |
12505 | as_bad (_("Junk after '}': '%s'"), imm_start); | |
12506 | return 0; | |
12507 | } | |
12508 | ||
cf665fee JB |
12509 | /* Internally this doesn't count as an operand. */ |
12510 | --i.operands; | |
43234a1e | 12511 | |
43234a1e L |
12512 | return 1; |
12513 | } | |
12514 | ||
9d299bea JB |
12515 | static INLINE bool starts_memory_operand (char c) |
12516 | { | |
014fbcda | 12517 | return ISDIGIT (c) |
4795cd4a | 12518 | || is_name_beginner (c) |
014fbcda | 12519 | || strchr ("([\"+-!~", c); |
9d299bea JB |
12520 | } |
12521 | ||
fc0763e6 | 12522 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero |
47926f60 | 12523 | on error. */ |
252b5132 | 12524 | |
252b5132 | 12525 | static int |
a7619375 | 12526 | i386_att_operand (char *operand_string) |
252b5132 | 12527 | { |
af6bdddf AM |
12528 | const reg_entry *r; |
12529 | char *end_op; | |
24eab124 | 12530 | char *op_string = operand_string; |
252b5132 | 12531 | |
24eab124 | 12532 | if (is_space_char (*op_string)) |
252b5132 RH |
12533 | ++op_string; |
12534 | ||
24eab124 | 12535 | /* We check for an absolute prefix (differentiating, |
47926f60 | 12536 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
ccb05c9c JB |
12537 | if (*op_string == ABSOLUTE_PREFIX |
12538 | && current_templates->start->opcode_modifier.jump) | |
24eab124 AM |
12539 | { |
12540 | ++op_string; | |
12541 | if (is_space_char (*op_string)) | |
12542 | ++op_string; | |
5b7c81bd | 12543 | i.jumpabsolute = true; |
24eab124 | 12544 | } |
252b5132 | 12545 | |
47926f60 | 12546 | /* Check if operand is a register. */ |
4d1bb795 | 12547 | if ((r = parse_register (op_string, &end_op)) != NULL) |
24eab124 | 12548 | { |
40fb9820 L |
12549 | i386_operand_type temp; |
12550 | ||
8a6fb3f9 JB |
12551 | if (r == &bad_reg) |
12552 | return 0; | |
12553 | ||
24eab124 AM |
12554 | /* Check for a segment override by searching for ':' after a |
12555 | segment register. */ | |
12556 | op_string = end_op; | |
12557 | if (is_space_char (*op_string)) | |
12558 | ++op_string; | |
00cee14f | 12559 | if (*op_string == ':' && r->reg_type.bitfield.class == SReg) |
24eab124 | 12560 | { |
5e042380 | 12561 | i.seg[i.mem_operands] = r; |
252b5132 | 12562 | |
24eab124 | 12563 | /* Skip the ':' and whitespace. */ |
252b5132 RH |
12564 | ++op_string; |
12565 | if (is_space_char (*op_string)) | |
24eab124 | 12566 | ++op_string; |
252b5132 | 12567 | |
47926f60 | 12568 | /* Handle case of %es:*foo. */ |
ccb05c9c JB |
12569 | if (!i.jumpabsolute && *op_string == ABSOLUTE_PREFIX |
12570 | && current_templates->start->opcode_modifier.jump) | |
24eab124 AM |
12571 | { |
12572 | ++op_string; | |
12573 | if (is_space_char (*op_string)) | |
12574 | ++op_string; | |
5b7c81bd | 12575 | i.jumpabsolute = true; |
24eab124 | 12576 | } |
c8d541e2 | 12577 | |
9d299bea | 12578 | if (!starts_memory_operand (*op_string)) |
c8d541e2 JB |
12579 | { |
12580 | as_bad (_("bad memory operand `%s'"), op_string); | |
12581 | return 0; | |
12582 | } | |
24eab124 AM |
12583 | goto do_memory_reference; |
12584 | } | |
43234a1e L |
12585 | |
12586 | /* Handle vector operations. */ | |
12587 | if (*op_string == '{') | |
12588 | { | |
f70c6814 | 12589 | op_string = check_VecOperations (op_string); |
43234a1e L |
12590 | if (op_string == NULL) |
12591 | return 0; | |
12592 | } | |
12593 | ||
24eab124 AM |
12594 | if (*op_string) |
12595 | { | |
d0b47220 | 12596 | as_bad (_("junk `%s' after register"), op_string); |
24eab124 AM |
12597 | return 0; |
12598 | } | |
0ff3b7d0 JB |
12599 | |
12600 | /* Reject pseudo registers for .insn. */ | |
12601 | if (dot_insn () && r->reg_type.bitfield.class == ClassNone) | |
12602 | { | |
12603 | as_bad (_("`%s%s' cannot be used here"), | |
12604 | register_prefix, r->reg_name); | |
12605 | return 0; | |
12606 | } | |
12607 | ||
40fb9820 L |
12608 | temp = r->reg_type; |
12609 | temp.bitfield.baseindex = 0; | |
c6fb90c8 L |
12610 | i.types[this_operand] = operand_type_or (i.types[this_operand], |
12611 | temp); | |
7d5e4556 | 12612 | i.types[this_operand].bitfield.unspecified = 0; |
520dc8e8 | 12613 | i.op[this_operand].regs = r; |
24eab124 | 12614 | i.reg_operands++; |
cf665fee JB |
12615 | |
12616 | /* A GPR may follow an RC or SAE immediate only if a (vector) register | |
12617 | operand was also present earlier on. */ | |
12618 | if (i.rounding.type != rc_none && temp.bitfield.class == Reg | |
12619 | && i.reg_operands == 1) | |
12620 | { | |
12621 | unsigned int j; | |
12622 | ||
12623 | for (j = 0; j < ARRAY_SIZE (RC_NamesTable); ++j) | |
12624 | if (i.rounding.type == RC_NamesTable[j].type) | |
12625 | break; | |
12626 | as_bad (_("`%s': misplaced `{%s}'"), | |
76d3f746 | 12627 | insn_name (current_templates->start), RC_NamesTable[j].name); |
cf665fee JB |
12628 | return 0; |
12629 | } | |
24eab124 | 12630 | } |
af6bdddf AM |
12631 | else if (*op_string == REGISTER_PREFIX) |
12632 | { | |
12633 | as_bad (_("bad register name `%s'"), op_string); | |
12634 | return 0; | |
12635 | } | |
24eab124 | 12636 | else if (*op_string == IMMEDIATE_PREFIX) |
ce8a8b2f | 12637 | { |
24eab124 | 12638 | ++op_string; |
6f2f06be | 12639 | if (i.jumpabsolute) |
24eab124 | 12640 | { |
d0b47220 | 12641 | as_bad (_("immediate operand illegal with absolute jump")); |
24eab124 AM |
12642 | return 0; |
12643 | } | |
12644 | if (!i386_immediate (op_string)) | |
12645 | return 0; | |
cf665fee JB |
12646 | if (i.rounding.type != rc_none) |
12647 | { | |
12648 | as_bad (_("`%s': RC/SAE operand must follow immediate operands"), | |
76d3f746 | 12649 | insn_name (current_templates->start)); |
cf665fee JB |
12650 | return 0; |
12651 | } | |
24eab124 | 12652 | } |
43234a1e L |
12653 | else if (RC_SAE_immediate (operand_string)) |
12654 | { | |
cf665fee JB |
12655 | /* If it is a RC or SAE immediate, do the necessary placement check: |
12656 | Only another immediate or a GPR may precede it. */ | |
12657 | if (i.mem_operands || i.reg_operands + i.imm_operands > 1 | |
12658 | || (i.reg_operands == 1 | |
12659 | && i.op[0].regs->reg_type.bitfield.class != Reg)) | |
12660 | { | |
12661 | as_bad (_("`%s': misplaced `%s'"), | |
76d3f746 | 12662 | insn_name (current_templates->start), operand_string); |
cf665fee JB |
12663 | return 0; |
12664 | } | |
43234a1e | 12665 | } |
9d299bea | 12666 | else if (starts_memory_operand (*op_string)) |
24eab124 | 12667 | { |
47926f60 | 12668 | /* This is a memory reference of some sort. */ |
af6bdddf | 12669 | char *base_string; |
252b5132 | 12670 | |
47926f60 | 12671 | /* Start and end of displacement string expression (if found). */ |
eecb386c AM |
12672 | char *displacement_string_start; |
12673 | char *displacement_string_end; | |
252b5132 | 12674 | |
24eab124 | 12675 | do_memory_reference: |
24eab124 AM |
12676 | /* Check for base index form. We detect the base index form by |
12677 | looking for an ')' at the end of the operand, searching | |
12678 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' | |
12679 | after the '('. */ | |
af6bdddf | 12680 | base_string = op_string + strlen (op_string); |
c3332e24 | 12681 | |
43234a1e | 12682 | /* Handle vector operations. */ |
6b5ba0d4 JB |
12683 | --base_string; |
12684 | if (is_space_char (*base_string)) | |
12685 | --base_string; | |
12686 | ||
12687 | if (*base_string == '}') | |
43234a1e | 12688 | { |
6b5ba0d4 JB |
12689 | char *vop_start = NULL; |
12690 | ||
12691 | while (base_string-- > op_string) | |
12692 | { | |
12693 | if (*base_string == '"') | |
12694 | break; | |
12695 | if (*base_string != '{') | |
12696 | continue; | |
12697 | ||
12698 | vop_start = base_string; | |
12699 | ||
12700 | --base_string; | |
12701 | if (is_space_char (*base_string)) | |
12702 | --base_string; | |
12703 | ||
12704 | if (*base_string != '}') | |
12705 | break; | |
12706 | ||
12707 | vop_start = NULL; | |
12708 | } | |
12709 | ||
12710 | if (!vop_start) | |
12711 | { | |
12712 | as_bad (_("unbalanced figure braces")); | |
12713 | return 0; | |
12714 | } | |
12715 | ||
f70c6814 | 12716 | if (check_VecOperations (vop_start) == NULL) |
43234a1e | 12717 | return 0; |
43234a1e L |
12718 | } |
12719 | ||
47926f60 | 12720 | /* If we only have a displacement, set-up for it to be parsed later. */ |
af6bdddf AM |
12721 | displacement_string_start = op_string; |
12722 | displacement_string_end = base_string + 1; | |
252b5132 | 12723 | |
24eab124 AM |
12724 | if (*base_string == ')') |
12725 | { | |
af6bdddf | 12726 | char *temp_string; |
e87fb6a6 JB |
12727 | unsigned int parens_not_balanced = 0; |
12728 | bool in_quotes = false; | |
e68c3d59 | 12729 | |
24eab124 | 12730 | /* We've already checked that the number of left & right ()'s are |
e87fb6a6 JB |
12731 | equal, and that there's a matching set of double quotes. */ |
12732 | end_op = base_string; | |
12733 | for (temp_string = op_string; temp_string < end_op; temp_string++) | |
24eab124 | 12734 | { |
e87fb6a6 JB |
12735 | if (*temp_string == '\\' && temp_string[1] == '"') |
12736 | ++temp_string; | |
12737 | else if (*temp_string == '"') | |
12738 | in_quotes = !in_quotes; | |
12739 | else if (!in_quotes) | |
12740 | { | |
12741 | if (*temp_string == '(' && !parens_not_balanced++) | |
12742 | base_string = temp_string; | |
12743 | if (*temp_string == ')') | |
12744 | --parens_not_balanced; | |
12745 | } | |
24eab124 | 12746 | } |
c3332e24 | 12747 | |
af6bdddf | 12748 | temp_string = base_string; |
c3332e24 | 12749 | |
24eab124 | 12750 | /* Skip past '(' and whitespace. */ |
4f081312 | 12751 | gas_assert (*base_string == '('); |
e87fb6a6 | 12752 | ++base_string; |
252b5132 | 12753 | if (is_space_char (*base_string)) |
24eab124 | 12754 | ++base_string; |
252b5132 | 12755 | |
af6bdddf | 12756 | if (*base_string == ',' |
4eed87de AM |
12757 | || ((i.base_reg = parse_register (base_string, &end_op)) |
12758 | != NULL)) | |
252b5132 | 12759 | { |
af6bdddf | 12760 | displacement_string_end = temp_string; |
252b5132 | 12761 | |
40fb9820 | 12762 | i.types[this_operand].bitfield.baseindex = 1; |
252b5132 | 12763 | |
af6bdddf | 12764 | if (i.base_reg) |
24eab124 | 12765 | { |
8a6fb3f9 JB |
12766 | if (i.base_reg == &bad_reg) |
12767 | return 0; | |
24eab124 AM |
12768 | base_string = end_op; |
12769 | if (is_space_char (*base_string)) | |
12770 | ++base_string; | |
af6bdddf AM |
12771 | } |
12772 | ||
12773 | /* There may be an index reg or scale factor here. */ | |
12774 | if (*base_string == ',') | |
12775 | { | |
12776 | ++base_string; | |
12777 | if (is_space_char (*base_string)) | |
12778 | ++base_string; | |
12779 | ||
4eed87de AM |
12780 | if ((i.index_reg = parse_register (base_string, &end_op)) |
12781 | != NULL) | |
24eab124 | 12782 | { |
8a6fb3f9 JB |
12783 | if (i.index_reg == &bad_reg) |
12784 | return 0; | |
af6bdddf | 12785 | base_string = end_op; |
24eab124 AM |
12786 | if (is_space_char (*base_string)) |
12787 | ++base_string; | |
af6bdddf AM |
12788 | if (*base_string == ',') |
12789 | { | |
12790 | ++base_string; | |
12791 | if (is_space_char (*base_string)) | |
12792 | ++base_string; | |
12793 | } | |
e5cb08ac | 12794 | else if (*base_string != ')') |
af6bdddf | 12795 | { |
4eed87de AM |
12796 | as_bad (_("expecting `,' or `)' " |
12797 | "after index register in `%s'"), | |
af6bdddf AM |
12798 | operand_string); |
12799 | return 0; | |
12800 | } | |
24eab124 | 12801 | } |
af6bdddf | 12802 | else if (*base_string == REGISTER_PREFIX) |
24eab124 | 12803 | { |
f76bf5e0 L |
12804 | end_op = strchr (base_string, ','); |
12805 | if (end_op) | |
12806 | *end_op = '\0'; | |
af6bdddf | 12807 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 AM |
12808 | return 0; |
12809 | } | |
252b5132 | 12810 | |
47926f60 | 12811 | /* Check for scale factor. */ |
551c1ca1 | 12812 | if (*base_string != ')') |
af6bdddf | 12813 | { |
551c1ca1 AM |
12814 | char *end_scale = i386_scale (base_string); |
12815 | ||
12816 | if (!end_scale) | |
af6bdddf | 12817 | return 0; |
24eab124 | 12818 | |
551c1ca1 | 12819 | base_string = end_scale; |
af6bdddf AM |
12820 | if (is_space_char (*base_string)) |
12821 | ++base_string; | |
12822 | if (*base_string != ')') | |
12823 | { | |
4eed87de AM |
12824 | as_bad (_("expecting `)' " |
12825 | "after scale factor in `%s'"), | |
af6bdddf AM |
12826 | operand_string); |
12827 | return 0; | |
12828 | } | |
12829 | } | |
12830 | else if (!i.index_reg) | |
24eab124 | 12831 | { |
4eed87de AM |
12832 | as_bad (_("expecting index register or scale factor " |
12833 | "after `,'; got '%c'"), | |
af6bdddf | 12834 | *base_string); |
24eab124 AM |
12835 | return 0; |
12836 | } | |
12837 | } | |
af6bdddf | 12838 | else if (*base_string != ')') |
24eab124 | 12839 | { |
4eed87de AM |
12840 | as_bad (_("expecting `,' or `)' " |
12841 | "after base register in `%s'"), | |
af6bdddf | 12842 | operand_string); |
24eab124 AM |
12843 | return 0; |
12844 | } | |
c3332e24 | 12845 | } |
af6bdddf | 12846 | else if (*base_string == REGISTER_PREFIX) |
c3332e24 | 12847 | { |
f76bf5e0 L |
12848 | end_op = strchr (base_string, ','); |
12849 | if (end_op) | |
12850 | *end_op = '\0'; | |
af6bdddf | 12851 | as_bad (_("bad register name `%s'"), base_string); |
24eab124 | 12852 | return 0; |
c3332e24 | 12853 | } |
24eab124 AM |
12854 | } |
12855 | ||
12856 | /* If there's an expression beginning the operand, parse it, | |
12857 | assuming displacement_string_start and | |
12858 | displacement_string_end are meaningful. */ | |
12859 | if (displacement_string_start != displacement_string_end) | |
12860 | { | |
12861 | if (!i386_displacement (displacement_string_start, | |
12862 | displacement_string_end)) | |
12863 | return 0; | |
12864 | } | |
12865 | ||
12866 | /* Special case for (%dx) while doing input/output op. */ | |
12867 | if (i.base_reg | |
75e5731b JB |
12868 | && i.base_reg->reg_type.bitfield.instance == RegD |
12869 | && i.base_reg->reg_type.bitfield.word | |
24eab124 AM |
12870 | && i.index_reg == 0 |
12871 | && i.log2_scale_factor == 0 | |
12872 | && i.seg[i.mem_operands] == 0 | |
40fb9820 | 12873 | && !operand_type_check (i.types[this_operand], disp)) |
24eab124 | 12874 | { |
2fb5be8d | 12875 | i.types[this_operand] = i.base_reg->reg_type; |
9373f275 | 12876 | i.input_output_operand = true; |
24eab124 AM |
12877 | return 1; |
12878 | } | |
12879 | ||
eecb386c AM |
12880 | if (i386_index_check (operand_string) == 0) |
12881 | return 0; | |
c48dadc9 | 12882 | i.flags[this_operand] |= Operand_Mem; |
24eab124 AM |
12883 | i.mem_operands++; |
12884 | } | |
12885 | else | |
ce8a8b2f AM |
12886 | { |
12887 | /* It's not a memory operand; argh! */ | |
24eab124 AM |
12888 | as_bad (_("invalid char %s beginning operand %d `%s'"), |
12889 | output_invalid (*op_string), | |
12890 | this_operand + 1, | |
12891 | op_string); | |
12892 | return 0; | |
12893 | } | |
47926f60 | 12894 | return 1; /* Normal return. */ |
252b5132 RH |
12895 | } |
12896 | \f | |
fa94de6b RM |
12897 | /* Calculate the maximum variable size (i.e., excluding fr_fix) |
12898 | that an rs_machine_dependent frag may reach. */ | |
12899 | ||
12900 | unsigned int | |
12901 | i386_frag_max_var (fragS *frag) | |
12902 | { | |
12903 | /* The only relaxable frags are for jumps. | |
12904 | Unconditional jumps can grow by 4 bytes and others by 5 bytes. */ | |
12905 | gas_assert (frag->fr_type == rs_machine_dependent); | |
12906 | return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5; | |
12907 | } | |
12908 | ||
b084df0b L |
12909 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
12910 | static int | |
8dcea932 | 12911 | elf_symbol_resolved_in_segment_p (symbolS *fr_symbol, offsetT fr_var) |
b084df0b L |
12912 | { |
12913 | /* STT_GNU_IFUNC symbol must go through PLT. */ | |
12914 | if ((symbol_get_bfdsym (fr_symbol)->flags | |
12915 | & BSF_GNU_INDIRECT_FUNCTION) != 0) | |
12916 | return 0; | |
12917 | ||
12918 | if (!S_IS_EXTERNAL (fr_symbol)) | |
12919 | /* Symbol may be weak or local. */ | |
12920 | return !S_IS_WEAK (fr_symbol); | |
12921 | ||
8dcea932 L |
12922 | /* Global symbols with non-default visibility can't be preempted. */ |
12923 | if (ELF_ST_VISIBILITY (S_GET_OTHER (fr_symbol)) != STV_DEFAULT) | |
12924 | return 1; | |
12925 | ||
12926 | if (fr_var != NO_RELOC) | |
12927 | switch ((enum bfd_reloc_code_real) fr_var) | |
12928 | { | |
12929 | case BFD_RELOC_386_PLT32: | |
12930 | case BFD_RELOC_X86_64_PLT32: | |
33eaf5de | 12931 | /* Symbol with PLT relocation may be preempted. */ |
8dcea932 L |
12932 | return 0; |
12933 | default: | |
12934 | abort (); | |
12935 | } | |
12936 | ||
b084df0b L |
12937 | /* Global symbols with default visibility in a shared library may be |
12938 | preempted by another definition. */ | |
8dcea932 | 12939 | return !shared; |
b084df0b L |
12940 | } |
12941 | #endif | |
12942 | ||
79d72f45 HL |
12943 | /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture |
12944 | Note also work for Skylake and Cascadelake. | |
12945 | --------------------------------------------------------------------- | |
12946 | | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND | | |
12947 | | ------ | ----------- | ------- | -------- | | |
12948 | | Jo | N | N | Y | | |
12949 | | Jno | N | N | Y | | |
12950 | | Jc/Jb | Y | N | Y | | |
12951 | | Jae/Jnb | Y | N | Y | | |
12952 | | Je/Jz | Y | Y | Y | | |
12953 | | Jne/Jnz | Y | Y | Y | | |
12954 | | Jna/Jbe | Y | N | Y | | |
12955 | | Ja/Jnbe | Y | N | Y | | |
12956 | | Js | N | N | Y | | |
12957 | | Jns | N | N | Y | | |
12958 | | Jp/Jpe | N | N | Y | | |
12959 | | Jnp/Jpo | N | N | Y | | |
12960 | | Jl/Jnge | Y | Y | Y | | |
12961 | | Jge/Jnl | Y | Y | Y | | |
12962 | | Jle/Jng | Y | Y | Y | | |
12963 | | Jg/Jnle | Y | Y | Y | | |
12964 | --------------------------------------------------------------------- */ | |
12965 | static int | |
12966 | i386_macro_fusible_p (enum mf_cmp_kind mf_cmp, enum mf_jcc_kind mf_jcc) | |
12967 | { | |
12968 | if (mf_cmp == mf_cmp_alu_cmp) | |
12969 | return ((mf_jcc >= mf_jcc_jc && mf_jcc <= mf_jcc_jna) | |
12970 | || mf_jcc == mf_jcc_jl || mf_jcc == mf_jcc_jle); | |
12971 | if (mf_cmp == mf_cmp_incdec) | |
12972 | return (mf_jcc == mf_jcc_je || mf_jcc == mf_jcc_jl | |
12973 | || mf_jcc == mf_jcc_jle); | |
12974 | if (mf_cmp == mf_cmp_test_and) | |
12975 | return 1; | |
12976 | return 0; | |
12977 | } | |
12978 | ||
e379e5f3 L |
12979 | /* Return the next non-empty frag. */ |
12980 | ||
12981 | static fragS * | |
12982 | i386_next_non_empty_frag (fragS *fragP) | |
12983 | { | |
12984 | /* There may be a frag with a ".fill 0" when there is no room in | |
12985 | the current frag for frag_grow in output_insn. */ | |
12986 | for (fragP = fragP->fr_next; | |
12987 | (fragP != NULL | |
12988 | && fragP->fr_type == rs_fill | |
12989 | && fragP->fr_fix == 0); | |
12990 | fragP = fragP->fr_next) | |
12991 | ; | |
12992 | return fragP; | |
12993 | } | |
12994 | ||
12995 | /* Return the next jcc frag after BRANCH_PADDING. */ | |
12996 | ||
12997 | static fragS * | |
79d72f45 | 12998 | i386_next_fusible_jcc_frag (fragS *maybe_cmp_fragP, fragS *pad_fragP) |
e379e5f3 | 12999 | { |
79d72f45 HL |
13000 | fragS *branch_fragP; |
13001 | if (!pad_fragP) | |
e379e5f3 L |
13002 | return NULL; |
13003 | ||
79d72f45 HL |
13004 | if (pad_fragP->fr_type == rs_machine_dependent |
13005 | && (TYPE_FROM_RELAX_STATE (pad_fragP->fr_subtype) | |
e379e5f3 L |
13006 | == BRANCH_PADDING)) |
13007 | { | |
79d72f45 HL |
13008 | branch_fragP = i386_next_non_empty_frag (pad_fragP); |
13009 | if (branch_fragP->fr_type != rs_machine_dependent) | |
e379e5f3 | 13010 | return NULL; |
79d72f45 HL |
13011 | if (TYPE_FROM_RELAX_STATE (branch_fragP->fr_subtype) == COND_JUMP |
13012 | && i386_macro_fusible_p (maybe_cmp_fragP->tc_frag_data.mf_type, | |
13013 | pad_fragP->tc_frag_data.mf_type)) | |
13014 | return branch_fragP; | |
e379e5f3 L |
13015 | } |
13016 | ||
13017 | return NULL; | |
13018 | } | |
13019 | ||
13020 | /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */ | |
13021 | ||
13022 | static void | |
13023 | i386_classify_machine_dependent_frag (fragS *fragP) | |
13024 | { | |
13025 | fragS *cmp_fragP; | |
13026 | fragS *pad_fragP; | |
13027 | fragS *branch_fragP; | |
13028 | fragS *next_fragP; | |
13029 | unsigned int max_prefix_length; | |
13030 | ||
13031 | if (fragP->tc_frag_data.classified) | |
13032 | return; | |
13033 | ||
13034 | /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert | |
13035 | FUSED_JCC_PADDING and merge BRANCH_PADDING. */ | |
13036 | for (next_fragP = fragP; | |
13037 | next_fragP != NULL; | |
13038 | next_fragP = next_fragP->fr_next) | |
13039 | { | |
13040 | next_fragP->tc_frag_data.classified = 1; | |
13041 | if (next_fragP->fr_type == rs_machine_dependent) | |
13042 | switch (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype)) | |
13043 | { | |
13044 | case BRANCH_PADDING: | |
13045 | /* The BRANCH_PADDING frag must be followed by a branch | |
13046 | frag. */ | |
13047 | branch_fragP = i386_next_non_empty_frag (next_fragP); | |
13048 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
13049 | break; | |
13050 | case FUSED_JCC_PADDING: | |
13051 | /* Check if this is a fused jcc: | |
13052 | FUSED_JCC_PADDING | |
13053 | CMP like instruction | |
13054 | BRANCH_PADDING | |
13055 | COND_JUMP | |
13056 | */ | |
13057 | cmp_fragP = i386_next_non_empty_frag (next_fragP); | |
13058 | pad_fragP = i386_next_non_empty_frag (cmp_fragP); | |
79d72f45 | 13059 | branch_fragP = i386_next_fusible_jcc_frag (next_fragP, pad_fragP); |
e379e5f3 L |
13060 | if (branch_fragP) |
13061 | { | |
13062 | /* The BRANCH_PADDING frag is merged with the | |
13063 | FUSED_JCC_PADDING frag. */ | |
13064 | next_fragP->tc_frag_data.u.branch_fragP = branch_fragP; | |
13065 | /* CMP like instruction size. */ | |
13066 | next_fragP->tc_frag_data.cmp_size = cmp_fragP->fr_fix; | |
13067 | frag_wane (pad_fragP); | |
13068 | /* Skip to branch_fragP. */ | |
13069 | next_fragP = branch_fragP; | |
13070 | } | |
13071 | else if (next_fragP->tc_frag_data.max_prefix_length) | |
13072 | { | |
13073 | /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't | |
13074 | a fused jcc. */ | |
13075 | next_fragP->fr_subtype | |
13076 | = ENCODE_RELAX_STATE (BRANCH_PREFIX, 0); | |
13077 | next_fragP->tc_frag_data.max_bytes | |
13078 | = next_fragP->tc_frag_data.max_prefix_length; | |
13079 | /* This will be updated in the BRANCH_PREFIX scan. */ | |
13080 | next_fragP->tc_frag_data.max_prefix_length = 0; | |
13081 | } | |
13082 | else | |
13083 | frag_wane (next_fragP); | |
13084 | break; | |
13085 | } | |
13086 | } | |
13087 | ||
13088 | /* Stop if there is no BRANCH_PREFIX. */ | |
13089 | if (!align_branch_prefix_size) | |
13090 | return; | |
13091 | ||
13092 | /* Scan for BRANCH_PREFIX. */ | |
13093 | for (; fragP != NULL; fragP = fragP->fr_next) | |
13094 | { | |
13095 | if (fragP->fr_type != rs_machine_dependent | |
13096 | || (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
13097 | != BRANCH_PREFIX)) | |
13098 | continue; | |
13099 | ||
13100 | /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and | |
13101 | COND_JUMP_PREFIX. */ | |
13102 | max_prefix_length = 0; | |
13103 | for (next_fragP = fragP; | |
13104 | next_fragP != NULL; | |
13105 | next_fragP = next_fragP->fr_next) | |
13106 | { | |
13107 | if (next_fragP->fr_type == rs_fill) | |
13108 | /* Skip rs_fill frags. */ | |
13109 | continue; | |
13110 | else if (next_fragP->fr_type != rs_machine_dependent) | |
13111 | /* Stop for all other frags. */ | |
13112 | break; | |
13113 | ||
13114 | /* rs_machine_dependent frags. */ | |
13115 | if (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13116 | == BRANCH_PREFIX) | |
13117 | { | |
13118 | /* Count BRANCH_PREFIX frags. */ | |
13119 | if (max_prefix_length >= MAX_FUSED_JCC_PADDING_SIZE) | |
13120 | { | |
13121 | max_prefix_length = MAX_FUSED_JCC_PADDING_SIZE; | |
13122 | frag_wane (next_fragP); | |
13123 | } | |
13124 | else | |
13125 | max_prefix_length | |
13126 | += next_fragP->tc_frag_data.max_bytes; | |
13127 | } | |
13128 | else if ((TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13129 | == BRANCH_PADDING) | |
13130 | || (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13131 | == FUSED_JCC_PADDING)) | |
13132 | { | |
13133 | /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */ | |
13134 | fragP->tc_frag_data.u.padding_fragP = next_fragP; | |
13135 | break; | |
13136 | } | |
13137 | else | |
13138 | /* Stop for other rs_machine_dependent frags. */ | |
13139 | break; | |
13140 | } | |
13141 | ||
13142 | fragP->tc_frag_data.max_prefix_length = max_prefix_length; | |
13143 | ||
13144 | /* Skip to the next frag. */ | |
13145 | fragP = next_fragP; | |
13146 | } | |
13147 | } | |
13148 | ||
13149 | /* Compute padding size for | |
13150 | ||
13151 | FUSED_JCC_PADDING | |
13152 | CMP like instruction | |
13153 | BRANCH_PADDING | |
13154 | COND_JUMP/UNCOND_JUMP | |
13155 | ||
13156 | or | |
13157 | ||
13158 | BRANCH_PADDING | |
13159 | COND_JUMP/UNCOND_JUMP | |
13160 | */ | |
13161 | ||
13162 | static int | |
13163 | i386_branch_padding_size (fragS *fragP, offsetT address) | |
13164 | { | |
13165 | unsigned int offset, size, padding_size; | |
13166 | fragS *branch_fragP = fragP->tc_frag_data.u.branch_fragP; | |
13167 | ||
13168 | /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */ | |
13169 | if (!address) | |
13170 | address = fragP->fr_address; | |
13171 | address += fragP->fr_fix; | |
13172 | ||
13173 | /* CMP like instrunction size. */ | |
13174 | size = fragP->tc_frag_data.cmp_size; | |
13175 | ||
13176 | /* The base size of the branch frag. */ | |
13177 | size += branch_fragP->fr_fix; | |
13178 | ||
13179 | /* Add opcode and displacement bytes for the rs_machine_dependent | |
13180 | branch frag. */ | |
13181 | if (branch_fragP->fr_type == rs_machine_dependent) | |
13182 | size += md_relax_table[branch_fragP->fr_subtype].rlx_length; | |
13183 | ||
13184 | /* Check if branch is within boundary and doesn't end at the last | |
13185 | byte. */ | |
13186 | offset = address & ((1U << align_branch_power) - 1); | |
13187 | if ((offset + size) >= (1U << align_branch_power)) | |
13188 | /* Padding needed to avoid crossing boundary. */ | |
13189 | padding_size = (1U << align_branch_power) - offset; | |
13190 | else | |
13191 | /* No padding needed. */ | |
13192 | padding_size = 0; | |
13193 | ||
13194 | /* The return value may be saved in tc_frag_data.length which is | |
13195 | unsigned byte. */ | |
13196 | if (!fits_in_unsigned_byte (padding_size)) | |
13197 | abort (); | |
13198 | ||
13199 | return padding_size; | |
13200 | } | |
13201 | ||
13202 | /* i386_generic_table_relax_frag() | |
13203 | ||
13204 | Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to | |
13205 | grow/shrink padding to align branch frags. Hand others to | |
13206 | relax_frag(). */ | |
13207 | ||
13208 | long | |
13209 | i386_generic_table_relax_frag (segT segment, fragS *fragP, long stretch) | |
13210 | { | |
13211 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING | |
13212 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
13213 | { | |
13214 | long padding_size = i386_branch_padding_size (fragP, 0); | |
13215 | long grow = padding_size - fragP->tc_frag_data.length; | |
13216 | ||
13217 | /* When the BRANCH_PREFIX frag is used, the computed address | |
13218 | must match the actual address and there should be no padding. */ | |
13219 | if (fragP->tc_frag_data.padding_address | |
13220 | && (fragP->tc_frag_data.padding_address != fragP->fr_address | |
13221 | || padding_size)) | |
13222 | abort (); | |
13223 | ||
13224 | /* Update the padding size. */ | |
13225 | if (grow) | |
13226 | fragP->tc_frag_data.length = padding_size; | |
13227 | ||
13228 | return grow; | |
13229 | } | |
13230 | else if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
13231 | { | |
13232 | fragS *padding_fragP, *next_fragP; | |
13233 | long padding_size, left_size, last_size; | |
13234 | ||
13235 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
13236 | if (!padding_fragP) | |
13237 | /* Use the padding set by the leading BRANCH_PREFIX frag. */ | |
13238 | return (fragP->tc_frag_data.length | |
13239 | - fragP->tc_frag_data.last_length); | |
13240 | ||
13241 | /* Compute the relative address of the padding frag in the very | |
13242 | first time where the BRANCH_PREFIX frag sizes are zero. */ | |
13243 | if (!fragP->tc_frag_data.padding_address) | |
13244 | fragP->tc_frag_data.padding_address | |
13245 | = padding_fragP->fr_address - (fragP->fr_address - stretch); | |
13246 | ||
13247 | /* First update the last length from the previous interation. */ | |
13248 | left_size = fragP->tc_frag_data.prefix_length; | |
13249 | for (next_fragP = fragP; | |
13250 | next_fragP != padding_fragP; | |
13251 | next_fragP = next_fragP->fr_next) | |
13252 | if (next_fragP->fr_type == rs_machine_dependent | |
13253 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13254 | == BRANCH_PREFIX)) | |
13255 | { | |
13256 | if (left_size) | |
13257 | { | |
13258 | int max = next_fragP->tc_frag_data.max_bytes; | |
13259 | if (max) | |
13260 | { | |
13261 | int size; | |
13262 | if (max > left_size) | |
13263 | size = left_size; | |
13264 | else | |
13265 | size = max; | |
13266 | left_size -= size; | |
13267 | next_fragP->tc_frag_data.last_length = size; | |
13268 | } | |
13269 | } | |
13270 | else | |
13271 | next_fragP->tc_frag_data.last_length = 0; | |
13272 | } | |
13273 | ||
13274 | /* Check the padding size for the padding frag. */ | |
13275 | padding_size = i386_branch_padding_size | |
13276 | (padding_fragP, (fragP->fr_address | |
13277 | + fragP->tc_frag_data.padding_address)); | |
13278 | ||
13279 | last_size = fragP->tc_frag_data.prefix_length; | |
13280 | /* Check if there is change from the last interation. */ | |
13281 | if (padding_size == last_size) | |
13282 | { | |
13283 | /* Update the expected address of the padding frag. */ | |
13284 | padding_fragP->tc_frag_data.padding_address | |
13285 | = (fragP->fr_address + padding_size | |
13286 | + fragP->tc_frag_data.padding_address); | |
13287 | return 0; | |
13288 | } | |
13289 | ||
13290 | if (padding_size > fragP->tc_frag_data.max_prefix_length) | |
13291 | { | |
13292 | /* No padding if there is no sufficient room. Clear the | |
13293 | expected address of the padding frag. */ | |
13294 | padding_fragP->tc_frag_data.padding_address = 0; | |
13295 | padding_size = 0; | |
13296 | } | |
13297 | else | |
13298 | /* Store the expected address of the padding frag. */ | |
13299 | padding_fragP->tc_frag_data.padding_address | |
13300 | = (fragP->fr_address + padding_size | |
13301 | + fragP->tc_frag_data.padding_address); | |
13302 | ||
13303 | fragP->tc_frag_data.prefix_length = padding_size; | |
13304 | ||
13305 | /* Update the length for the current interation. */ | |
13306 | left_size = padding_size; | |
13307 | for (next_fragP = fragP; | |
13308 | next_fragP != padding_fragP; | |
13309 | next_fragP = next_fragP->fr_next) | |
13310 | if (next_fragP->fr_type == rs_machine_dependent | |
13311 | && (TYPE_FROM_RELAX_STATE (next_fragP->fr_subtype) | |
13312 | == BRANCH_PREFIX)) | |
13313 | { | |
13314 | if (left_size) | |
13315 | { | |
13316 | int max = next_fragP->tc_frag_data.max_bytes; | |
13317 | if (max) | |
13318 | { | |
13319 | int size; | |
13320 | if (max > left_size) | |
13321 | size = left_size; | |
13322 | else | |
13323 | size = max; | |
13324 | left_size -= size; | |
13325 | next_fragP->tc_frag_data.length = size; | |
13326 | } | |
13327 | } | |
13328 | else | |
13329 | next_fragP->tc_frag_data.length = 0; | |
13330 | } | |
13331 | ||
13332 | return (fragP->tc_frag_data.length | |
13333 | - fragP->tc_frag_data.last_length); | |
13334 | } | |
13335 | return relax_frag (segment, fragP, stretch); | |
13336 | } | |
13337 | ||
ee7fcc42 AM |
13338 | /* md_estimate_size_before_relax() |
13339 | ||
13340 | Called just before relax() for rs_machine_dependent frags. The x86 | |
13341 | assembler uses these frags to handle variable size jump | |
13342 | instructions. | |
13343 | ||
13344 | Any symbol that is now undefined will not become defined. | |
13345 | Return the correct fr_subtype in the frag. | |
13346 | Return the initial "guess for variable size of frag" to caller. | |
13347 | The guess is actually the growth beyond the fixed part. Whatever | |
13348 | we do to grow the fixed or variable part contributes to our | |
13349 | returned value. */ | |
13350 | ||
252b5132 | 13351 | int |
7016a5d5 | 13352 | md_estimate_size_before_relax (fragS *fragP, segT segment) |
252b5132 | 13353 | { |
e379e5f3 L |
13354 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
13355 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX | |
13356 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING) | |
13357 | { | |
13358 | i386_classify_machine_dependent_frag (fragP); | |
13359 | return fragP->tc_frag_data.length; | |
13360 | } | |
13361 | ||
252b5132 | 13362 | /* We've already got fragP->fr_subtype right; all we have to do is |
b98ef147 AM |
13363 | check for un-relaxable symbols. On an ELF system, we can't relax |
13364 | an externally visible symbol, because it may be overridden by a | |
13365 | shared library. */ | |
13366 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment | |
6d249963 | 13367 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 13368 | || (IS_ELF |
8dcea932 L |
13369 | && !elf_symbol_resolved_in_segment_p (fragP->fr_symbol, |
13370 | fragP->fr_var)) | |
fbeb56a4 DK |
13371 | #endif |
13372 | #if defined (OBJ_COFF) && defined (TE_PE) | |
7ab9ffdd | 13373 | || (OUTPUT_FLAVOR == bfd_target_coff_flavour |
fbeb56a4 | 13374 | && S_IS_WEAK (fragP->fr_symbol)) |
b98ef147 AM |
13375 | #endif |
13376 | ) | |
252b5132 | 13377 | { |
b98ef147 AM |
13378 | /* Symbol is undefined in this segment, or we need to keep a |
13379 | reloc so that weak symbols can be overridden. */ | |
13380 | int size = (fragP->fr_subtype & CODE16) ? 2 : 4; | |
f86103b7 | 13381 | enum bfd_reloc_code_real reloc_type; |
ee7fcc42 AM |
13382 | unsigned char *opcode; |
13383 | int old_fr_fix; | |
eb19308f | 13384 | fixS *fixP = NULL; |
f6af82bd | 13385 | |
ee7fcc42 | 13386 | if (fragP->fr_var != NO_RELOC) |
1e9cc1c2 | 13387 | reloc_type = (enum bfd_reloc_code_real) fragP->fr_var; |
b98ef147 | 13388 | else if (size == 2) |
f6af82bd | 13389 | reloc_type = BFD_RELOC_16_PCREL; |
bd7ab16b | 13390 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
1ef3994a JB |
13391 | else if (fragP->tc_frag_data.code64 && fragP->fr_offset == 0 |
13392 | && need_plt32_p (fragP->fr_symbol)) | |
bd7ab16b L |
13393 | reloc_type = BFD_RELOC_X86_64_PLT32; |
13394 | #endif | |
f6af82bd AM |
13395 | else |
13396 | reloc_type = BFD_RELOC_32_PCREL; | |
252b5132 | 13397 | |
ee7fcc42 AM |
13398 | old_fr_fix = fragP->fr_fix; |
13399 | opcode = (unsigned char *) fragP->fr_opcode; | |
13400 | ||
fddf5b5b | 13401 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) |
252b5132 | 13402 | { |
fddf5b5b AM |
13403 | case UNCOND_JUMP: |
13404 | /* Make jmp (0xeb) a (d)word displacement jump. */ | |
47926f60 | 13405 | opcode[0] = 0xe9; |
252b5132 | 13406 | fragP->fr_fix += size; |
eb19308f JB |
13407 | fixP = fix_new (fragP, old_fr_fix, size, |
13408 | fragP->fr_symbol, | |
13409 | fragP->fr_offset, 1, | |
13410 | reloc_type); | |
252b5132 RH |
13411 | break; |
13412 | ||
fddf5b5b | 13413 | case COND_JUMP86: |
412167cb AM |
13414 | if (size == 2 |
13415 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) | |
fddf5b5b AM |
13416 | { |
13417 | /* Negate the condition, and branch past an | |
13418 | unconditional jump. */ | |
13419 | opcode[0] ^= 1; | |
13420 | opcode[1] = 3; | |
13421 | /* Insert an unconditional jump. */ | |
13422 | opcode[2] = 0xe9; | |
13423 | /* We added two extra opcode bytes, and have a two byte | |
13424 | offset. */ | |
13425 | fragP->fr_fix += 2 + 2; | |
062cd5e7 AS |
13426 | fix_new (fragP, old_fr_fix + 2, 2, |
13427 | fragP->fr_symbol, | |
13428 | fragP->fr_offset, 1, | |
13429 | reloc_type); | |
fddf5b5b AM |
13430 | break; |
13431 | } | |
13432 | /* Fall through. */ | |
13433 | ||
13434 | case COND_JUMP: | |
412167cb AM |
13435 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) |
13436 | { | |
13437 | fragP->fr_fix += 1; | |
3e02c1cc AM |
13438 | fixP = fix_new (fragP, old_fr_fix, 1, |
13439 | fragP->fr_symbol, | |
13440 | fragP->fr_offset, 1, | |
13441 | BFD_RELOC_8_PCREL); | |
13442 | fixP->fx_signed = 1; | |
412167cb AM |
13443 | break; |
13444 | } | |
93c2a809 | 13445 | |
24eab124 | 13446 | /* This changes the byte-displacement jump 0x7N |
fddf5b5b | 13447 | to the (d)word-displacement jump 0x0f,0x8N. */ |
252b5132 | 13448 | opcode[1] = opcode[0] + 0x10; |
f6af82bd | 13449 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; |
47926f60 KH |
13450 | /* We've added an opcode byte. */ |
13451 | fragP->fr_fix += 1 + size; | |
eb19308f JB |
13452 | fixP = fix_new (fragP, old_fr_fix + 1, size, |
13453 | fragP->fr_symbol, | |
13454 | fragP->fr_offset, 1, | |
13455 | reloc_type); | |
252b5132 | 13456 | break; |
fddf5b5b AM |
13457 | |
13458 | default: | |
13459 | BAD_CASE (fragP->fr_subtype); | |
13460 | break; | |
252b5132 | 13461 | } |
eb19308f JB |
13462 | |
13463 | /* All jumps handled here are signed, but don't unconditionally use a | |
13464 | signed limit check for 32 and 16 bit jumps as we want to allow wrap | |
13465 | around at 4G (outside of 64-bit mode) and 64k. */ | |
13466 | if (size == 4 && flag_code == CODE_64BIT) | |
13467 | fixP->fx_signed = 1; | |
13468 | ||
252b5132 | 13469 | frag_wane (fragP); |
ee7fcc42 | 13470 | return fragP->fr_fix - old_fr_fix; |
252b5132 | 13471 | } |
93c2a809 | 13472 | |
93c2a809 AM |
13473 | /* Guess size depending on current relax state. Initially the relax |
13474 | state will correspond to a short jump and we return 1, because | |
13475 | the variable part of the frag (the branch offset) is one byte | |
13476 | long. However, we can relax a section more than once and in that | |
13477 | case we must either set fr_subtype back to the unrelaxed state, | |
13478 | or return the value for the appropriate branch. */ | |
13479 | return md_relax_table[fragP->fr_subtype].rlx_length; | |
ee7fcc42 AM |
13480 | } |
13481 | ||
47926f60 KH |
13482 | /* Called after relax() is finished. |
13483 | ||
13484 | In: Address of frag. | |
13485 | fr_type == rs_machine_dependent. | |
13486 | fr_subtype is what the address relaxed to. | |
13487 | ||
13488 | Out: Any fixSs and constants are set up. | |
13489 | Caller will turn frag into a ".space 0". */ | |
13490 | ||
252b5132 | 13491 | void |
7016a5d5 TG |
13492 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED, |
13493 | fragS *fragP) | |
252b5132 | 13494 | { |
29b0f896 | 13495 | unsigned char *opcode; |
252b5132 | 13496 | unsigned char *where_to_put_displacement = NULL; |
847f7ad4 AM |
13497 | offsetT target_address; |
13498 | offsetT opcode_address; | |
252b5132 | 13499 | unsigned int extension = 0; |
847f7ad4 | 13500 | offsetT displacement_from_opcode_start; |
252b5132 | 13501 | |
e379e5f3 L |
13502 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PADDING |
13503 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == FUSED_JCC_PADDING | |
13504 | || TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
13505 | { | |
13506 | /* Generate nop padding. */ | |
13507 | unsigned int size = fragP->tc_frag_data.length; | |
13508 | if (size) | |
13509 | { | |
13510 | if (size > fragP->tc_frag_data.max_bytes) | |
13511 | abort (); | |
13512 | ||
13513 | if (flag_debug) | |
13514 | { | |
13515 | const char *msg; | |
13516 | const char *branch = "branch"; | |
13517 | const char *prefix = ""; | |
13518 | fragS *padding_fragP; | |
13519 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) | |
13520 | == BRANCH_PREFIX) | |
13521 | { | |
13522 | padding_fragP = fragP->tc_frag_data.u.padding_fragP; | |
13523 | switch (fragP->tc_frag_data.default_prefix) | |
13524 | { | |
13525 | default: | |
13526 | abort (); | |
13527 | break; | |
13528 | case CS_PREFIX_OPCODE: | |
13529 | prefix = " cs"; | |
13530 | break; | |
13531 | case DS_PREFIX_OPCODE: | |
13532 | prefix = " ds"; | |
13533 | break; | |
13534 | case ES_PREFIX_OPCODE: | |
13535 | prefix = " es"; | |
13536 | break; | |
13537 | case FS_PREFIX_OPCODE: | |
13538 | prefix = " fs"; | |
13539 | break; | |
13540 | case GS_PREFIX_OPCODE: | |
13541 | prefix = " gs"; | |
13542 | break; | |
13543 | case SS_PREFIX_OPCODE: | |
13544 | prefix = " ss"; | |
13545 | break; | |
13546 | } | |
13547 | if (padding_fragP) | |
13548 | msg = _("%s:%u: add %d%s at 0x%llx to align " | |
13549 | "%s within %d-byte boundary\n"); | |
13550 | else | |
13551 | msg = _("%s:%u: add additional %d%s at 0x%llx to " | |
13552 | "align %s within %d-byte boundary\n"); | |
13553 | } | |
13554 | else | |
13555 | { | |
13556 | padding_fragP = fragP; | |
13557 | msg = _("%s:%u: add %d%s-byte nop at 0x%llx to align " | |
13558 | "%s within %d-byte boundary\n"); | |
13559 | } | |
13560 | ||
13561 | if (padding_fragP) | |
13562 | switch (padding_fragP->tc_frag_data.branch_type) | |
13563 | { | |
13564 | case align_branch_jcc: | |
13565 | branch = "jcc"; | |
13566 | break; | |
13567 | case align_branch_fused: | |
13568 | branch = "fused jcc"; | |
13569 | break; | |
13570 | case align_branch_jmp: | |
13571 | branch = "jmp"; | |
13572 | break; | |
13573 | case align_branch_call: | |
13574 | branch = "call"; | |
13575 | break; | |
13576 | case align_branch_indirect: | |
13577 | branch = "indiret branch"; | |
13578 | break; | |
13579 | case align_branch_ret: | |
13580 | branch = "ret"; | |
13581 | break; | |
13582 | default: | |
13583 | break; | |
13584 | } | |
13585 | ||
13586 | fprintf (stdout, msg, | |
13587 | fragP->fr_file, fragP->fr_line, size, prefix, | |
13588 | (long long) fragP->fr_address, branch, | |
13589 | 1 << align_branch_power); | |
13590 | } | |
13591 | if (TYPE_FROM_RELAX_STATE (fragP->fr_subtype) == BRANCH_PREFIX) | |
13592 | memset (fragP->fr_opcode, | |
13593 | fragP->tc_frag_data.default_prefix, size); | |
13594 | else | |
13595 | i386_generate_nops (fragP, (char *) fragP->fr_opcode, | |
13596 | size, 0); | |
13597 | fragP->fr_fix += size; | |
13598 | } | |
13599 | return; | |
13600 | } | |
13601 | ||
252b5132 RH |
13602 | opcode = (unsigned char *) fragP->fr_opcode; |
13603 | ||
47926f60 | 13604 | /* Address we want to reach in file space. */ |
252b5132 | 13605 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
252b5132 | 13606 | |
47926f60 | 13607 | /* Address opcode resides at in file space. */ |
252b5132 RH |
13608 | opcode_address = fragP->fr_address + fragP->fr_fix; |
13609 | ||
47926f60 | 13610 | /* Displacement from opcode start to fill into instruction. */ |
252b5132 RH |
13611 | displacement_from_opcode_start = target_address - opcode_address; |
13612 | ||
fddf5b5b | 13613 | if ((fragP->fr_subtype & BIG) == 0) |
252b5132 | 13614 | { |
47926f60 KH |
13615 | /* Don't have to change opcode. */ |
13616 | extension = 1; /* 1 opcode + 1 displacement */ | |
252b5132 | 13617 | where_to_put_displacement = &opcode[1]; |
fddf5b5b AM |
13618 | } |
13619 | else | |
13620 | { | |
13621 | if (no_cond_jump_promotion | |
13622 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) | |
4eed87de AM |
13623 | as_warn_where (fragP->fr_file, fragP->fr_line, |
13624 | _("long jump required")); | |
252b5132 | 13625 | |
fddf5b5b AM |
13626 | switch (fragP->fr_subtype) |
13627 | { | |
13628 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): | |
13629 | extension = 4; /* 1 opcode + 4 displacement */ | |
13630 | opcode[0] = 0xe9; | |
13631 | where_to_put_displacement = &opcode[1]; | |
13632 | break; | |
252b5132 | 13633 | |
fddf5b5b AM |
13634 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): |
13635 | extension = 2; /* 1 opcode + 2 displacement */ | |
13636 | opcode[0] = 0xe9; | |
13637 | where_to_put_displacement = &opcode[1]; | |
13638 | break; | |
252b5132 | 13639 | |
fddf5b5b AM |
13640 | case ENCODE_RELAX_STATE (COND_JUMP, BIG): |
13641 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG): | |
13642 | extension = 5; /* 2 opcode + 4 displacement */ | |
13643 | opcode[1] = opcode[0] + 0x10; | |
13644 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
13645 | where_to_put_displacement = &opcode[2]; | |
13646 | break; | |
252b5132 | 13647 | |
fddf5b5b AM |
13648 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16): |
13649 | extension = 3; /* 2 opcode + 2 displacement */ | |
13650 | opcode[1] = opcode[0] + 0x10; | |
13651 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE; | |
13652 | where_to_put_displacement = &opcode[2]; | |
13653 | break; | |
252b5132 | 13654 | |
fddf5b5b AM |
13655 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): |
13656 | extension = 4; | |
13657 | opcode[0] ^= 1; | |
13658 | opcode[1] = 3; | |
13659 | opcode[2] = 0xe9; | |
13660 | where_to_put_displacement = &opcode[3]; | |
13661 | break; | |
13662 | ||
13663 | default: | |
13664 | BAD_CASE (fragP->fr_subtype); | |
13665 | break; | |
13666 | } | |
252b5132 | 13667 | } |
fddf5b5b | 13668 | |
7b81dfbb AJ |
13669 | /* If size if less then four we are sure that the operand fits, |
13670 | but if it's 4, then it could be that the displacement is larger | |
13671 | then -/+ 2GB. */ | |
13672 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4 | |
13673 | && object_64bit | |
13674 | && ((addressT) (displacement_from_opcode_start - extension | |
4eed87de AM |
13675 | + ((addressT) 1 << 31)) |
13676 | > (((addressT) 2 << 31) - 1))) | |
7b81dfbb AJ |
13677 | { |
13678 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
13679 | _("jump target out of range")); | |
13680 | /* Make us emit 0. */ | |
13681 | displacement_from_opcode_start = extension; | |
13682 | } | |
47926f60 | 13683 | /* Now put displacement after opcode. */ |
252b5132 RH |
13684 | md_number_to_chars ((char *) where_to_put_displacement, |
13685 | (valueT) (displacement_from_opcode_start - extension), | |
fddf5b5b | 13686 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); |
252b5132 RH |
13687 | fragP->fr_fix += extension; |
13688 | } | |
13689 | \f | |
7016a5d5 | 13690 | /* Apply a fixup (fixP) to segment data, once it has been determined |
252b5132 RH |
13691 | by our caller that we have all the info we need to fix it up. |
13692 | ||
7016a5d5 TG |
13693 | Parameter valP is the pointer to the value of the bits. |
13694 | ||
252b5132 RH |
13695 | On the 386, immediates, displacements, and data pointers are all in |
13696 | the same (little-endian) format, so we don't need to care about which | |
13697 | we are handling. */ | |
13698 | ||
94f592af | 13699 | void |
7016a5d5 | 13700 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 13701 | { |
94f592af | 13702 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
c6682705 | 13703 | valueT value = *valP; |
252b5132 | 13704 | |
f86103b7 | 13705 | #if !defined (TE_Mach) |
93382f6d AM |
13706 | if (fixP->fx_pcrel) |
13707 | { | |
13708 | switch (fixP->fx_r_type) | |
13709 | { | |
5865bb77 ILT |
13710 | default: |
13711 | break; | |
13712 | ||
d6ab8113 JB |
13713 | case BFD_RELOC_64: |
13714 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
13715 | break; | |
93382f6d | 13716 | case BFD_RELOC_32: |
ae8887b5 | 13717 | case BFD_RELOC_X86_64_32S: |
93382f6d AM |
13718 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
13719 | break; | |
13720 | case BFD_RELOC_16: | |
13721 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
13722 | break; | |
13723 | case BFD_RELOC_8: | |
13724 | fixP->fx_r_type = BFD_RELOC_8_PCREL; | |
13725 | break; | |
13726 | } | |
13727 | } | |
252b5132 | 13728 | |
a161fe53 | 13729 | if (fixP->fx_addsy != NULL |
31312f95 | 13730 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
d6ab8113 | 13731 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
31312f95 | 13732 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
d258b828 | 13733 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
31312f95 | 13734 | && !use_rela_relocations) |
252b5132 | 13735 | { |
31312f95 AM |
13736 | /* This is a hack. There should be a better way to handle this. |
13737 | This covers for the fact that bfd_install_relocation will | |
13738 | subtract the current location (for partial_inplace, PC relative | |
13739 | relocations); see more below. */ | |
252b5132 | 13740 | #ifndef OBJ_AOUT |
718ddfc0 | 13741 | if (IS_ELF |
252b5132 RH |
13742 | #ifdef TE_PE |
13743 | || OUTPUT_FLAVOR == bfd_target_coff_flavour | |
13744 | #endif | |
13745 | ) | |
13746 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
13747 | #endif | |
13748 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
718ddfc0 | 13749 | if (IS_ELF) |
252b5132 | 13750 | { |
6539b54b | 13751 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
2f66722d | 13752 | |
6539b54b | 13753 | if ((sym_seg == seg |
2f66722d | 13754 | || (symbol_section_p (fixP->fx_addsy) |
6539b54b | 13755 | && sym_seg != absolute_section)) |
af65af87 | 13756 | && !generic_force_reloc (fixP)) |
2f66722d AM |
13757 | { |
13758 | /* Yes, we add the values in twice. This is because | |
6539b54b AM |
13759 | bfd_install_relocation subtracts them out again. I think |
13760 | bfd_install_relocation is broken, but I don't dare change | |
2f66722d AM |
13761 | it. FIXME. */ |
13762 | value += fixP->fx_where + fixP->fx_frag->fr_address; | |
13763 | } | |
252b5132 RH |
13764 | } |
13765 | #endif | |
13766 | #if defined (OBJ_COFF) && defined (TE_PE) | |
977cdf5a NC |
13767 | /* For some reason, the PE format does not store a |
13768 | section address offset for a PC relative symbol. */ | |
13769 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg | |
7be1c489 | 13770 | || S_IS_WEAK (fixP->fx_addsy)) |
252b5132 RH |
13771 | value += md_pcrel_from (fixP); |
13772 | #endif | |
13773 | } | |
fbeb56a4 | 13774 | #if defined (OBJ_COFF) && defined (TE_PE) |
f01c1a09 NC |
13775 | if (fixP->fx_addsy != NULL |
13776 | && S_IS_WEAK (fixP->fx_addsy) | |
13777 | /* PR 16858: Do not modify weak function references. */ | |
13778 | && ! fixP->fx_pcrel) | |
fbeb56a4 | 13779 | { |
296a8689 NC |
13780 | #if !defined (TE_PEP) |
13781 | /* For x86 PE weak function symbols are neither PC-relative | |
13782 | nor do they set S_IS_FUNCTION. So the only reliable way | |
13783 | to detect them is to check the flags of their containing | |
13784 | section. */ | |
13785 | if (S_GET_SEGMENT (fixP->fx_addsy) != NULL | |
13786 | && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) | |
13787 | ; | |
13788 | else | |
13789 | #endif | |
fbeb56a4 DK |
13790 | value -= S_GET_VALUE (fixP->fx_addsy); |
13791 | } | |
13792 | #endif | |
252b5132 RH |
13793 | |
13794 | /* Fix a few things - the dynamic linker expects certain values here, | |
0234cb7c | 13795 | and we must not disappoint it. */ |
252b5132 | 13796 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
718ddfc0 | 13797 | if (IS_ELF && fixP->fx_addsy) |
47926f60 KH |
13798 | switch (fixP->fx_r_type) |
13799 | { | |
13800 | case BFD_RELOC_386_PLT32: | |
3e73aa7c | 13801 | case BFD_RELOC_X86_64_PLT32: |
b9519cfe L |
13802 | /* Make the jump instruction point to the address of the operand. |
13803 | At runtime we merely add the offset to the actual PLT entry. | |
13804 | NB: Subtract the offset size only for jump instructions. */ | |
13805 | if (fixP->fx_pcrel) | |
13806 | value = -4; | |
47926f60 | 13807 | break; |
31312f95 | 13808 | |
13ae64f3 JJ |
13809 | case BFD_RELOC_386_TLS_GD: |
13810 | case BFD_RELOC_386_TLS_LDM: | |
13ae64f3 | 13811 | case BFD_RELOC_386_TLS_IE_32: |
37e55690 JJ |
13812 | case BFD_RELOC_386_TLS_IE: |
13813 | case BFD_RELOC_386_TLS_GOTIE: | |
67a4f2b7 | 13814 | case BFD_RELOC_386_TLS_GOTDESC: |
bffbf940 JJ |
13815 | case BFD_RELOC_X86_64_TLSGD: |
13816 | case BFD_RELOC_X86_64_TLSLD: | |
13817 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 | 13818 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
00f7efb6 JJ |
13819 | value = 0; /* Fully resolved at runtime. No addend. */ |
13820 | /* Fallthrough */ | |
13821 | case BFD_RELOC_386_TLS_LE: | |
13822 | case BFD_RELOC_386_TLS_LDO_32: | |
13823 | case BFD_RELOC_386_TLS_LE_32: | |
13824 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 13825 | case BFD_RELOC_X86_64_DTPOFF64: |
00f7efb6 | 13826 | case BFD_RELOC_X86_64_TPOFF32: |
d6ab8113 | 13827 | case BFD_RELOC_X86_64_TPOFF64: |
00f7efb6 JJ |
13828 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
13829 | break; | |
13830 | ||
67a4f2b7 AO |
13831 | case BFD_RELOC_386_TLS_DESC_CALL: |
13832 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
13833 | value = 0; /* Fully resolved at runtime. No addend. */ | |
13834 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
13835 | fixP->fx_done = 0; | |
13836 | return; | |
13837 | ||
47926f60 KH |
13838 | case BFD_RELOC_VTABLE_INHERIT: |
13839 | case BFD_RELOC_VTABLE_ENTRY: | |
13840 | fixP->fx_done = 0; | |
94f592af | 13841 | return; |
47926f60 KH |
13842 | |
13843 | default: | |
13844 | break; | |
13845 | } | |
13846 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ | |
a442cac5 JB |
13847 | |
13848 | /* If not 64bit, massage value, to account for wraparound when !BFD64. */ | |
13849 | if (!object_64bit) | |
13850 | value = extend_to_32bit_address (value); | |
13851 | ||
c6682705 | 13852 | *valP = value; |
f86103b7 | 13853 | #endif /* !defined (TE_Mach) */ |
3e73aa7c | 13854 | |
3e73aa7c | 13855 | /* Are we finished with this relocation now? */ |
c6682705 | 13856 | if (fixP->fx_addsy == NULL) |
b8188555 JB |
13857 | { |
13858 | fixP->fx_done = 1; | |
13859 | switch (fixP->fx_r_type) | |
13860 | { | |
13861 | case BFD_RELOC_X86_64_32S: | |
13862 | fixP->fx_signed = 1; | |
13863 | break; | |
13864 | ||
13865 | default: | |
13866 | break; | |
13867 | } | |
13868 | } | |
fbeb56a4 DK |
13869 | #if defined (OBJ_COFF) && defined (TE_PE) |
13870 | else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) | |
13871 | { | |
13872 | fixP->fx_done = 0; | |
13873 | /* Remember value for tc_gen_reloc. */ | |
13874 | fixP->fx_addnumber = value; | |
13875 | /* Clear out the frag for now. */ | |
13876 | value = 0; | |
13877 | } | |
13878 | #endif | |
3e73aa7c JH |
13879 | else if (use_rela_relocations) |
13880 | { | |
46fb6d5a JB |
13881 | if (!disallow_64bit_reloc || fixP->fx_r_type == NO_RELOC) |
13882 | fixP->fx_no_overflow = 1; | |
062cd5e7 AS |
13883 | /* Remember value for tc_gen_reloc. */ |
13884 | fixP->fx_addnumber = value; | |
3e73aa7c JH |
13885 | value = 0; |
13886 | } | |
f86103b7 | 13887 | |
94f592af | 13888 | md_number_to_chars (p, value, fixP->fx_size); |
252b5132 | 13889 | } |
252b5132 | 13890 | \f |
6d4af3c2 | 13891 | const char * |
499ac353 | 13892 | md_atof (int type, char *litP, int *sizeP) |
252b5132 | 13893 | { |
499ac353 NC |
13894 | /* This outputs the LITTLENUMs in REVERSE order; |
13895 | in accord with the bigendian 386. */ | |
5b7c81bd | 13896 | return ieee_md_atof (type, litP, sizeP, false); |
252b5132 RH |
13897 | } |
13898 | \f | |
2d545b82 | 13899 | static char output_invalid_buf[sizeof (unsigned char) * 2 + 6]; |
252b5132 | 13900 | |
252b5132 | 13901 | static char * |
e3bb37b5 | 13902 | output_invalid (int c) |
252b5132 | 13903 | { |
3882b010 | 13904 | if (ISPRINT (c)) |
f9f21a03 L |
13905 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
13906 | "'%c'", c); | |
252b5132 | 13907 | else |
f9f21a03 | 13908 | snprintf (output_invalid_buf, sizeof (output_invalid_buf), |
2d545b82 | 13909 | "(0x%x)", (unsigned char) c); |
252b5132 RH |
13910 | return output_invalid_buf; |
13911 | } | |
13912 | ||
8a6fb3f9 JB |
13913 | /* Verify that @r can be used in the current context. */ |
13914 | ||
5b7c81bd | 13915 | static bool check_register (const reg_entry *r) |
8a6fb3f9 JB |
13916 | { |
13917 | if (allow_pseudo_reg) | |
5b7c81bd | 13918 | return true; |
8a6fb3f9 JB |
13919 | |
13920 | if (operand_type_all_zero (&r->reg_type)) | |
5b7c81bd | 13921 | return false; |
8a6fb3f9 JB |
13922 | |
13923 | if ((r->reg_type.bitfield.dword | |
13924 | || (r->reg_type.bitfield.class == SReg && r->reg_num > 3) | |
13925 | || r->reg_type.bitfield.class == RegCR | |
22e00a3f | 13926 | || r->reg_type.bitfield.class == RegDR) |
8a6fb3f9 | 13927 | && !cpu_arch_flags.bitfield.cpui386) |
5b7c81bd | 13928 | return false; |
8a6fb3f9 | 13929 | |
22e00a3f JB |
13930 | if (r->reg_type.bitfield.class == RegTR |
13931 | && (flag_code == CODE_64BIT | |
13932 | || !cpu_arch_flags.bitfield.cpui386 | |
13933 | || cpu_arch_isa_flags.bitfield.cpui586 | |
13934 | || cpu_arch_isa_flags.bitfield.cpui686)) | |
5b7c81bd | 13935 | return false; |
22e00a3f | 13936 | |
8a6fb3f9 | 13937 | if (r->reg_type.bitfield.class == RegMMX && !cpu_arch_flags.bitfield.cpummx) |
5b7c81bd | 13938 | return false; |
8a6fb3f9 JB |
13939 | |
13940 | if (!cpu_arch_flags.bitfield.cpuavx512f) | |
13941 | { | |
13942 | if (r->reg_type.bitfield.zmmword | |
13943 | || r->reg_type.bitfield.class == RegMask) | |
5b7c81bd | 13944 | return false; |
8a6fb3f9 JB |
13945 | |
13946 | if (!cpu_arch_flags.bitfield.cpuavx) | |
13947 | { | |
13948 | if (r->reg_type.bitfield.ymmword) | |
5b7c81bd | 13949 | return false; |
8a6fb3f9 JB |
13950 | |
13951 | if (!cpu_arch_flags.bitfield.cpusse && r->reg_type.bitfield.xmmword) | |
5b7c81bd | 13952 | return false; |
8a6fb3f9 JB |
13953 | } |
13954 | } | |
13955 | ||
4fc85f37 JB |
13956 | if (vector_size < VSZ512 && r->reg_type.bitfield.zmmword) |
13957 | return false; | |
13958 | ||
13959 | if (vector_size < VSZ256 && r->reg_type.bitfield.ymmword) | |
13960 | return false; | |
13961 | ||
260cd341 LC |
13962 | if (r->reg_type.bitfield.tmmword |
13963 | && (!cpu_arch_flags.bitfield.cpuamx_tile | |
13964 | || flag_code != CODE_64BIT)) | |
5b7c81bd | 13965 | return false; |
260cd341 | 13966 | |
8a6fb3f9 | 13967 | if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx) |
5b7c81bd | 13968 | return false; |
8a6fb3f9 JB |
13969 | |
13970 | /* Don't allow fake index register unless allow_index_reg isn't 0. */ | |
13971 | if (!allow_index_reg && r->reg_num == RegIZ) | |
5b7c81bd | 13972 | return false; |
8a6fb3f9 JB |
13973 | |
13974 | /* Upper 16 vector registers are only available with VREX in 64bit | |
13975 | mode, and require EVEX encoding. */ | |
13976 | if (r->reg_flags & RegVRex) | |
13977 | { | |
13978 | if (!cpu_arch_flags.bitfield.cpuavx512f | |
13979 | || flag_code != CODE_64BIT) | |
5b7c81bd | 13980 | return false; |
8a6fb3f9 | 13981 | |
da4977e0 JB |
13982 | if (i.vec_encoding == vex_encoding_default) |
13983 | i.vec_encoding = vex_encoding_evex; | |
13984 | else if (i.vec_encoding != vex_encoding_evex) | |
13985 | i.vec_encoding = vex_encoding_error; | |
8a6fb3f9 JB |
13986 | } |
13987 | ||
13988 | if (((r->reg_flags & (RegRex64 | RegRex)) || r->reg_type.bitfield.qword) | |
da5f9eb4 | 13989 | && (!cpu_arch_flags.bitfield.cpu64 |
0ff3b7d0 JB |
13990 | || r->reg_type.bitfield.class != RegCR |
13991 | || dot_insn ()) | |
8a6fb3f9 | 13992 | && flag_code != CODE_64BIT) |
5b7c81bd | 13993 | return false; |
8a6fb3f9 JB |
13994 | |
13995 | if (r->reg_type.bitfield.class == SReg && r->reg_num == RegFlat | |
13996 | && !intel_syntax) | |
5b7c81bd | 13997 | return false; |
8a6fb3f9 | 13998 | |
5b7c81bd | 13999 | return true; |
8a6fb3f9 JB |
14000 | } |
14001 | ||
af6bdddf | 14002 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
252b5132 RH |
14003 | |
14004 | static const reg_entry * | |
74e05e01 | 14005 | parse_real_register (const char *reg_string, char **end_op) |
252b5132 | 14006 | { |
74e05e01 | 14007 | const char *s = reg_string; |
af6bdddf | 14008 | char *p; |
252b5132 RH |
14009 | char reg_name_given[MAX_REG_NAME_SIZE + 1]; |
14010 | const reg_entry *r; | |
14011 | ||
14012 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ | |
14013 | if (*s == REGISTER_PREFIX) | |
14014 | ++s; | |
14015 | ||
14016 | if (is_space_char (*s)) | |
14017 | ++s; | |
14018 | ||
14019 | p = reg_name_given; | |
af6bdddf | 14020 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
252b5132 RH |
14021 | { |
14022 | if (p >= reg_name_given + MAX_REG_NAME_SIZE) | |
af6bdddf AM |
14023 | return (const reg_entry *) NULL; |
14024 | s++; | |
252b5132 RH |
14025 | } |
14026 | ||
4795cd4a | 14027 | if (is_part_of_name (*s)) |
6588847e DN |
14028 | return (const reg_entry *) NULL; |
14029 | ||
74e05e01 | 14030 | *end_op = (char *) s; |
252b5132 | 14031 | |
629310ab | 14032 | r = (const reg_entry *) str_hash_find (reg_hash, reg_name_given); |
252b5132 | 14033 | |
5f47d35b | 14034 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
6288d05f | 14035 | if (r == reg_st0) |
5f47d35b | 14036 | { |
0e0eea78 JB |
14037 | if (!cpu_arch_flags.bitfield.cpu8087 |
14038 | && !cpu_arch_flags.bitfield.cpu287 | |
af32b722 JB |
14039 | && !cpu_arch_flags.bitfield.cpu387 |
14040 | && !allow_pseudo_reg) | |
0e0eea78 JB |
14041 | return (const reg_entry *) NULL; |
14042 | ||
5f47d35b AM |
14043 | if (is_space_char (*s)) |
14044 | ++s; | |
14045 | if (*s == '(') | |
14046 | { | |
af6bdddf | 14047 | ++s; |
5f47d35b AM |
14048 | if (is_space_char (*s)) |
14049 | ++s; | |
14050 | if (*s >= '0' && *s <= '7') | |
14051 | { | |
db557034 | 14052 | int fpr = *s - '0'; |
af6bdddf | 14053 | ++s; |
5f47d35b AM |
14054 | if (is_space_char (*s)) |
14055 | ++s; | |
14056 | if (*s == ')') | |
14057 | { | |
74e05e01 | 14058 | *end_op = (char *) s + 1; |
6288d05f | 14059 | know (r[fpr].reg_num == fpr); |
db557034 | 14060 | return r + fpr; |
5f47d35b | 14061 | } |
5f47d35b | 14062 | } |
47926f60 | 14063 | /* We have "%st(" then garbage. */ |
5f47d35b AM |
14064 | return (const reg_entry *) NULL; |
14065 | } | |
14066 | } | |
14067 | ||
8a6fb3f9 | 14068 | return r && check_register (r) ? r : NULL; |
252b5132 | 14069 | } |
4d1bb795 JB |
14070 | |
14071 | /* REG_STRING starts *before* REGISTER_PREFIX. */ | |
14072 | ||
14073 | static const reg_entry * | |
4f081312 | 14074 | parse_register (const char *reg_string, char **end_op) |
4d1bb795 JB |
14075 | { |
14076 | const reg_entry *r; | |
14077 | ||
14078 | if (*reg_string == REGISTER_PREFIX || allow_naked_reg) | |
14079 | r = parse_real_register (reg_string, end_op); | |
14080 | else | |
14081 | r = NULL; | |
14082 | if (!r) | |
14083 | { | |
14084 | char *save = input_line_pointer; | |
4f081312 | 14085 | char *buf = xstrdup (reg_string), *name; |
4d1bb795 JB |
14086 | symbolS *symbolP; |
14087 | ||
4f081312 JB |
14088 | input_line_pointer = buf; |
14089 | get_symbol_name (&name); | |
14090 | symbolP = symbol_find (name); | |
d50c498a | 14091 | while (symbolP && symbol_equated_p (symbolP)) |
64d23078 JB |
14092 | { |
14093 | const expressionS *e = symbol_get_value_expression(symbolP); | |
14094 | ||
d50c498a | 14095 | if (e->X_add_number) |
64d23078 JB |
14096 | break; |
14097 | symbolP = e->X_add_symbol; | |
14098 | } | |
4d1bb795 JB |
14099 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
14100 | { | |
14101 | const expressionS *e = symbol_get_value_expression (symbolP); | |
14102 | ||
0ccade1a JB |
14103 | if (e->X_op == O_register) |
14104 | { | |
14105 | know (e->X_add_number >= 0 | |
14106 | && (valueT) e->X_add_number < i386_regtab_size); | |
14107 | r = i386_regtab + e->X_add_number; | |
4f081312 | 14108 | *end_op = (char *) reg_string + (input_line_pointer - buf); |
0ccade1a JB |
14109 | } |
14110 | if (r && !check_register (r)) | |
8a6fb3f9 | 14111 | { |
3b55a1d0 JB |
14112 | as_bad (_("register '%s%s' cannot be used here"), |
14113 | register_prefix, r->reg_name); | |
14114 | r = &bad_reg; | |
8a6fb3f9 | 14115 | } |
4d1bb795 | 14116 | } |
4d1bb795 | 14117 | input_line_pointer = save; |
4f081312 | 14118 | free (buf); |
4d1bb795 JB |
14119 | } |
14120 | return r; | |
14121 | } | |
14122 | ||
14123 | int | |
14124 | i386_parse_name (char *name, expressionS *e, char *nextcharP) | |
14125 | { | |
4faaa10f | 14126 | const reg_entry *r = NULL; |
4d1bb795 JB |
14127 | char *end = input_line_pointer; |
14128 | ||
6acf9130 JB |
14129 | /* We only know the terminating character here. It being double quote could |
14130 | be the closing one of a quoted symbol name, or an opening one from a | |
14131 | following string (or another quoted symbol name). Since the latter can't | |
14132 | be valid syntax for anything, bailing in either case is good enough. */ | |
14133 | if (*nextcharP == '"') | |
14134 | return 0; | |
14135 | ||
4d1bb795 | 14136 | *end = *nextcharP; |
4faaa10f JB |
14137 | if (*name == REGISTER_PREFIX || allow_naked_reg) |
14138 | r = parse_real_register (name, &input_line_pointer); | |
4d1bb795 JB |
14139 | if (r && end <= input_line_pointer) |
14140 | { | |
14141 | *nextcharP = *input_line_pointer; | |
14142 | *input_line_pointer = 0; | |
f847749a JB |
14143 | e->X_op = O_register; |
14144 | e->X_add_number = r - i386_regtab; | |
4d1bb795 JB |
14145 | return 1; |
14146 | } | |
14147 | input_line_pointer = end; | |
14148 | *end = 0; | |
ee86248c | 14149 | return intel_syntax ? i386_intel_parse_name (name, e) : 0; |
4d1bb795 JB |
14150 | } |
14151 | ||
14152 | void | |
14153 | md_operand (expressionS *e) | |
14154 | { | |
ee86248c JB |
14155 | char *end; |
14156 | const reg_entry *r; | |
4d1bb795 | 14157 | |
ee86248c JB |
14158 | switch (*input_line_pointer) |
14159 | { | |
14160 | case REGISTER_PREFIX: | |
14161 | r = parse_real_register (input_line_pointer, &end); | |
4d1bb795 JB |
14162 | if (r) |
14163 | { | |
14164 | e->X_op = O_register; | |
14165 | e->X_add_number = r - i386_regtab; | |
14166 | input_line_pointer = end; | |
14167 | } | |
ee86248c JB |
14168 | break; |
14169 | ||
14170 | case '[': | |
9c2799c2 | 14171 | gas_assert (intel_syntax); |
ee86248c JB |
14172 | end = input_line_pointer++; |
14173 | expression (e); | |
14174 | if (*input_line_pointer == ']') | |
14175 | { | |
14176 | ++input_line_pointer; | |
14177 | e->X_op_symbol = make_expr_symbol (e); | |
14178 | e->X_add_symbol = NULL; | |
14179 | e->X_add_number = 0; | |
14180 | e->X_op = O_index; | |
14181 | } | |
14182 | else | |
14183 | { | |
14184 | e->X_op = O_absent; | |
14185 | input_line_pointer = end; | |
14186 | } | |
14187 | break; | |
4d1bb795 JB |
14188 | } |
14189 | } | |
14190 | ||
5cc00775 JB |
14191 | #ifdef BFD64 |
14192 | /* To maintain consistency with !BFD64 builds of gas record, whether any | |
14193 | (binary) operator was involved in an expression. As expressions are | |
14194 | evaluated in only 32 bits when !BFD64, we use this to decide whether to | |
14195 | truncate results. */ | |
14196 | bool i386_record_operator (operatorT op, | |
14197 | const expressionS *left, | |
14198 | const expressionS *right) | |
14199 | { | |
14200 | if (op == O_absent) | |
14201 | return false; | |
14202 | ||
14203 | if (!left) | |
14204 | { | |
14205 | /* Since the expression parser applies unary operators fine to bignum | |
14206 | operands, we don't need to be concerned of respective operands not | |
14207 | fitting in 32 bits. */ | |
14208 | if (right->X_op == O_constant && right->X_unsigned | |
14209 | && !fits_in_unsigned_long (right->X_add_number)) | |
14210 | return false; | |
14211 | } | |
14212 | /* This isn't entirely right: The pattern can also result when constant | |
14213 | expressions are folded (e.g. 0xffffffff + 1). */ | |
14214 | else if ((left->X_op == O_constant && left->X_unsigned | |
14215 | && !fits_in_unsigned_long (left->X_add_number)) | |
14216 | || (right->X_op == O_constant && right->X_unsigned | |
14217 | && !fits_in_unsigned_long (right->X_add_number))) | |
14218 | expr_mode = expr_large_value; | |
14219 | ||
14220 | if (expr_mode != expr_large_value) | |
14221 | expr_mode = expr_operator_present; | |
14222 | ||
14223 | return false; | |
14224 | } | |
14225 | #endif | |
252b5132 | 14226 | \f |
4cc782b5 | 14227 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
b6f8c7c4 | 14228 | const char *md_shortopts = "kVQ:sqnO::"; |
252b5132 | 14229 | #else |
b6f8c7c4 | 14230 | const char *md_shortopts = "qnO::"; |
252b5132 | 14231 | #endif |
6e0b89ee | 14232 | |
3e73aa7c | 14233 | #define OPTION_32 (OPTION_MD_BASE + 0) |
b3b91714 AM |
14234 | #define OPTION_64 (OPTION_MD_BASE + 1) |
14235 | #define OPTION_DIVIDE (OPTION_MD_BASE + 2) | |
9103f4f4 L |
14236 | #define OPTION_MARCH (OPTION_MD_BASE + 3) |
14237 | #define OPTION_MTUNE (OPTION_MD_BASE + 4) | |
1efbbeb4 L |
14238 | #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5) |
14239 | #define OPTION_MSYNTAX (OPTION_MD_BASE + 6) | |
14240 | #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7) | |
14241 | #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8) | |
bd5dea88 | 14242 | #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9) |
c0f3af97 | 14243 | #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10) |
daf50ae7 | 14244 | #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11) |
7bab8ab5 JB |
14245 | #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12) |
14246 | #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13) | |
14247 | #define OPTION_X32 (OPTION_MD_BASE + 14) | |
7e8b059b | 14248 | #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) |
43234a1e L |
14249 | #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) |
14250 | #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) | |
167ad85b | 14251 | #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) |
d1982f93 | 14252 | #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19) |
d3d3c6db | 14253 | #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20) |
8dcea932 | 14254 | #define OPTION_MSHARED (OPTION_MD_BASE + 21) |
5db04b09 L |
14255 | #define OPTION_MAMD64 (OPTION_MD_BASE + 22) |
14256 | #define OPTION_MINTEL64 (OPTION_MD_BASE + 23) | |
e4e00185 | 14257 | #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24) |
b4a3a7b4 | 14258 | #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25) |
03751133 | 14259 | #define OPTION_MVEXWIG (OPTION_MD_BASE + 26) |
e379e5f3 L |
14260 | #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27) |
14261 | #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28) | |
14262 | #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29) | |
76cf450b | 14263 | #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30) |
ae531041 L |
14264 | #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31) |
14265 | #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32) | |
14266 | #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33) | |
c8480b58 | 14267 | #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34) |
b3b91714 | 14268 | |
99ad8390 NC |
14269 | struct option md_longopts[] = |
14270 | { | |
3e73aa7c | 14271 | {"32", no_argument, NULL, OPTION_32}, |
321098a5 | 14272 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 14273 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c | 14274 | {"64", no_argument, NULL, OPTION_64}, |
351f65ca L |
14275 | #endif |
14276 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
570561f7 | 14277 | {"x32", no_argument, NULL, OPTION_X32}, |
8dcea932 | 14278 | {"mshared", no_argument, NULL, OPTION_MSHARED}, |
b4a3a7b4 | 14279 | {"mx86-used-note", required_argument, NULL, OPTION_X86_USED_NOTE}, |
6e0b89ee | 14280 | #endif |
b3b91714 | 14281 | {"divide", no_argument, NULL, OPTION_DIVIDE}, |
9103f4f4 L |
14282 | {"march", required_argument, NULL, OPTION_MARCH}, |
14283 | {"mtune", required_argument, NULL, OPTION_MTUNE}, | |
1efbbeb4 L |
14284 | {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC}, |
14285 | {"msyntax", required_argument, NULL, OPTION_MSYNTAX}, | |
14286 | {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG}, | |
14287 | {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG}, | |
c0f3af97 | 14288 | {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX}, |
c8480b58 | 14289 | {"muse-unaligned-vector-move", no_argument, NULL, OPTION_MUSE_UNALIGNED_VECTOR_MOVE}, |
daf50ae7 | 14290 | {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK}, |
7bab8ab5 | 14291 | {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK}, |
539f890d | 14292 | {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR}, |
03751133 | 14293 | {"mvexwig", required_argument, NULL, OPTION_MVEXWIG}, |
7e8b059b | 14294 | {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, |
43234a1e L |
14295 | {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, |
14296 | {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, | |
167ad85b TG |
14297 | # if defined (TE_PE) || defined (TE_PEP) |
14298 | {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, | |
14299 | #endif | |
d1982f93 | 14300 | {"momit-lock-prefix", required_argument, NULL, OPTION_MOMIT_LOCK_PREFIX}, |
e4e00185 | 14301 | {"mfence-as-lock-add", required_argument, NULL, OPTION_MFENCE_AS_LOCK_ADD}, |
0cb4071e | 14302 | {"mrelax-relocations", required_argument, NULL, OPTION_MRELAX_RELOCATIONS}, |
d3d3c6db | 14303 | {"mevexrcig", required_argument, NULL, OPTION_MEVEXRCIG}, |
e379e5f3 L |
14304 | {"malign-branch-boundary", required_argument, NULL, OPTION_MALIGN_BRANCH_BOUNDARY}, |
14305 | {"malign-branch-prefix-size", required_argument, NULL, OPTION_MALIGN_BRANCH_PREFIX_SIZE}, | |
14306 | {"malign-branch", required_argument, NULL, OPTION_MALIGN_BRANCH}, | |
76cf450b | 14307 | {"mbranches-within-32B-boundaries", no_argument, NULL, OPTION_MBRANCHES_WITH_32B_BOUNDARIES}, |
ae531041 L |
14308 | {"mlfence-after-load", required_argument, NULL, OPTION_MLFENCE_AFTER_LOAD}, |
14309 | {"mlfence-before-indirect-branch", required_argument, NULL, | |
14310 | OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH}, | |
14311 | {"mlfence-before-ret", required_argument, NULL, OPTION_MLFENCE_BEFORE_RET}, | |
5db04b09 L |
14312 | {"mamd64", no_argument, NULL, OPTION_MAMD64}, |
14313 | {"mintel64", no_argument, NULL, OPTION_MINTEL64}, | |
252b5132 RH |
14314 | {NULL, no_argument, NULL, 0} |
14315 | }; | |
14316 | size_t md_longopts_size = sizeof (md_longopts); | |
14317 | ||
14318 | int | |
17b9d67d | 14319 | md_parse_option (int c, const char *arg) |
252b5132 | 14320 | { |
91d6fa6a | 14321 | unsigned int j; |
e379e5f3 | 14322 | char *arch, *next, *saved, *type; |
9103f4f4 | 14323 | |
252b5132 RH |
14324 | switch (c) |
14325 | { | |
12b55ccc L |
14326 | case 'n': |
14327 | optimize_align_code = 0; | |
14328 | break; | |
14329 | ||
a38cf1db AM |
14330 | case 'q': |
14331 | quiet_warnings = 1; | |
252b5132 RH |
14332 | break; |
14333 | ||
14334 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
a38cf1db AM |
14335 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
14336 | should be emitted or not. FIXME: Not implemented. */ | |
14337 | case 'Q': | |
d4693039 JB |
14338 | if ((arg[0] != 'y' && arg[0] != 'n') || arg[1]) |
14339 | return 0; | |
252b5132 RH |
14340 | break; |
14341 | ||
14342 | /* -V: SVR4 argument to print version ID. */ | |
14343 | case 'V': | |
14344 | print_version_id (); | |
14345 | break; | |
14346 | ||
a38cf1db AM |
14347 | /* -k: Ignore for FreeBSD compatibility. */ |
14348 | case 'k': | |
252b5132 | 14349 | break; |
4cc782b5 ILT |
14350 | |
14351 | case 's': | |
14352 | /* -s: On i386 Solaris, this tells the native assembler to use | |
29b0f896 | 14353 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
4cc782b5 | 14354 | break; |
8dcea932 L |
14355 | |
14356 | case OPTION_MSHARED: | |
14357 | shared = 1; | |
14358 | break; | |
b4a3a7b4 L |
14359 | |
14360 | case OPTION_X86_USED_NOTE: | |
14361 | if (strcasecmp (arg, "yes") == 0) | |
14362 | x86_used_note = 1; | |
14363 | else if (strcasecmp (arg, "no") == 0) | |
14364 | x86_used_note = 0; | |
14365 | else | |
14366 | as_fatal (_("invalid -mx86-used-note= option: `%s'"), arg); | |
14367 | break; | |
14368 | ||
14369 | ||
99ad8390 | 14370 | #endif |
321098a5 | 14371 | #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
d382c579 | 14372 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
3e73aa7c JH |
14373 | case OPTION_64: |
14374 | { | |
14375 | const char **list, **l; | |
14376 | ||
3e73aa7c JH |
14377 | list = bfd_target_list (); |
14378 | for (l = list; *l != NULL; l++) | |
08dedd66 | 14379 | if (startswith (*l, "elf64-x86-64") |
99ad8390 NC |
14380 | || strcmp (*l, "coff-x86-64") == 0 |
14381 | || strcmp (*l, "pe-x86-64") == 0 | |
d382c579 TG |
14382 | || strcmp (*l, "pei-x86-64") == 0 |
14383 | || strcmp (*l, "mach-o-x86-64") == 0) | |
6e0b89ee AM |
14384 | { |
14385 | default_arch = "x86_64"; | |
14386 | break; | |
14387 | } | |
3e73aa7c | 14388 | if (*l == NULL) |
2b5d6a91 | 14389 | as_fatal (_("no compiled in support for x86_64")); |
3e73aa7c JH |
14390 | free (list); |
14391 | } | |
14392 | break; | |
14393 | #endif | |
252b5132 | 14394 | |
351f65ca | 14395 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
570561f7 | 14396 | case OPTION_X32: |
351f65ca L |
14397 | if (IS_ELF) |
14398 | { | |
14399 | const char **list, **l; | |
14400 | ||
14401 | list = bfd_target_list (); | |
14402 | for (l = list; *l != NULL; l++) | |
08dedd66 | 14403 | if (startswith (*l, "elf32-x86-64")) |
351f65ca L |
14404 | { |
14405 | default_arch = "x86_64:32"; | |
14406 | break; | |
14407 | } | |
14408 | if (*l == NULL) | |
2b5d6a91 | 14409 | as_fatal (_("no compiled in support for 32bit x86_64")); |
351f65ca L |
14410 | free (list); |
14411 | } | |
14412 | else | |
14413 | as_fatal (_("32bit x86_64 is only supported for ELF")); | |
14414 | break; | |
14415 | #endif | |
14416 | ||
6e0b89ee | 14417 | case OPTION_32: |
590a0fed JB |
14418 | { |
14419 | const char **list, **l; | |
14420 | ||
14421 | list = bfd_target_list (); | |
14422 | for (l = list; *l != NULL; l++) | |
14423 | if (strstr (*l, "-i386") | |
14424 | || strstr (*l, "-go32")) | |
14425 | { | |
14426 | default_arch = "i386"; | |
14427 | break; | |
14428 | } | |
14429 | if (*l == NULL) | |
14430 | as_fatal (_("no compiled in support for ix86")); | |
14431 | free (list); | |
14432 | } | |
6e0b89ee AM |
14433 | break; |
14434 | ||
b3b91714 AM |
14435 | case OPTION_DIVIDE: |
14436 | #ifdef SVR4_COMMENT_CHARS | |
14437 | { | |
14438 | char *n, *t; | |
14439 | const char *s; | |
14440 | ||
add39d23 | 14441 | n = XNEWVEC (char, strlen (i386_comment_chars) + 1); |
b3b91714 AM |
14442 | t = n; |
14443 | for (s = i386_comment_chars; *s != '\0'; s++) | |
14444 | if (*s != '/') | |
14445 | *t++ = *s; | |
14446 | *t = '\0'; | |
14447 | i386_comment_chars = n; | |
14448 | } | |
14449 | #endif | |
14450 | break; | |
14451 | ||
9103f4f4 | 14452 | case OPTION_MARCH: |
293f5f65 L |
14453 | saved = xstrdup (arg); |
14454 | arch = saved; | |
14455 | /* Allow -march=+nosse. */ | |
14456 | if (*arch == '+') | |
14457 | arch++; | |
6305a203 | 14458 | do |
9103f4f4 | 14459 | { |
4fc85f37 JB |
14460 | char *vsz; |
14461 | ||
6305a203 | 14462 | if (*arch == '.') |
2b5d6a91 | 14463 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
14464 | next = strchr (arch, '+'); |
14465 | if (next) | |
14466 | *next++ = '\0'; | |
4fc85f37 JB |
14467 | vsz = strchr (arch, '/'); |
14468 | if (vsz) | |
14469 | *vsz++ = '\0'; | |
91d6fa6a | 14470 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 14471 | { |
4fc85f37 JB |
14472 | if (vsz && cpu_arch[j].vsz != vsz_set) |
14473 | continue; | |
14474 | ||
ae89daec JB |
14475 | if (arch == saved && cpu_arch[j].type != PROCESSOR_NONE |
14476 | && strcmp (arch, cpu_arch[j].name) == 0) | |
ccc9c027 | 14477 | { |
6305a203 | 14478 | /* Processor. */ |
ae89daec | 14479 | if (! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
14480 | continue; |
14481 | ||
91d6fa6a | 14482 | cpu_arch_name = cpu_arch[j].name; |
d92c7521 | 14483 | free (cpu_sub_arch_name); |
6305a203 | 14484 | cpu_sub_arch_name = NULL; |
ae89daec | 14485 | cpu_arch_flags = cpu_arch[j].enable; |
91d6fa6a | 14486 | cpu_arch_isa = cpu_arch[j].type; |
ae89daec | 14487 | cpu_arch_isa_flags = cpu_arch[j].enable; |
6305a203 L |
14488 | if (!cpu_arch_tune_set) |
14489 | { | |
14490 | cpu_arch_tune = cpu_arch_isa; | |
14491 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
14492 | } | |
4fc85f37 | 14493 | vector_size = VSZ_DEFAULT; |
6305a203 L |
14494 | break; |
14495 | } | |
ae89daec JB |
14496 | else if (cpu_arch[j].type == PROCESSOR_NONE |
14497 | && strcmp (arch, cpu_arch[j].name) == 0 | |
14498 | && !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
6305a203 | 14499 | { |
33eaf5de | 14500 | /* ISA extension. */ |
6305a203 | 14501 | i386_cpu_flags flags; |
309d3373 | 14502 | |
293f5f65 | 14503 | flags = cpu_flags_or (cpu_arch_flags, |
ae89daec | 14504 | cpu_arch[j].enable); |
81486035 | 14505 | |
5b64d091 | 14506 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
6305a203 | 14507 | { |
ae89daec | 14508 | extend_cpu_sub_arch_name (arch); |
6305a203 | 14509 | cpu_arch_flags = flags; |
a586129e | 14510 | cpu_arch_isa_flags = flags; |
6305a203 | 14511 | } |
0089dace L |
14512 | else |
14513 | cpu_arch_isa_flags | |
14514 | = cpu_flags_or (cpu_arch_isa_flags, | |
ae89daec | 14515 | cpu_arch[j].enable); |
4fc85f37 JB |
14516 | |
14517 | switch (cpu_arch[j].vsz) | |
14518 | { | |
14519 | default: | |
14520 | break; | |
14521 | ||
14522 | case vsz_set: | |
14523 | if (vsz) | |
14524 | { | |
14525 | char *end; | |
14526 | unsigned long val = strtoul (vsz, &end, 0); | |
14527 | ||
14528 | if (*end) | |
14529 | val = 0; | |
14530 | switch (val) | |
14531 | { | |
14532 | case 512: vector_size = VSZ512; break; | |
14533 | case 256: vector_size = VSZ256; break; | |
14534 | case 128: vector_size = VSZ128; break; | |
14535 | default: | |
14536 | as_warn (_("Unrecognized vector size specifier ignored")); | |
14537 | break; | |
14538 | } | |
14539 | break; | |
14540 | } | |
14541 | /* Fall through. */ | |
14542 | case vsz_reset: | |
14543 | vector_size = VSZ_DEFAULT; | |
14544 | break; | |
14545 | } | |
14546 | ||
6305a203 | 14547 | break; |
ccc9c027 | 14548 | } |
9103f4f4 | 14549 | } |
6305a203 | 14550 | |
ae89daec | 14551 | if (j >= ARRAY_SIZE (cpu_arch) && startswith (arch, "no")) |
293f5f65 | 14552 | { |
33eaf5de | 14553 | /* Disable an ISA extension. */ |
ae89daec JB |
14554 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
14555 | if (cpu_arch[j].type == PROCESSOR_NONE | |
14556 | && strcmp (arch + 2, cpu_arch[j].name) == 0) | |
293f5f65 L |
14557 | { |
14558 | i386_cpu_flags flags; | |
14559 | ||
14560 | flags = cpu_flags_and_not (cpu_arch_flags, | |
ae89daec | 14561 | cpu_arch[j].disable); |
293f5f65 L |
14562 | if (!cpu_flags_equal (&flags, &cpu_arch_flags)) |
14563 | { | |
8180707f | 14564 | extend_cpu_sub_arch_name (arch); |
293f5f65 L |
14565 | cpu_arch_flags = flags; |
14566 | cpu_arch_isa_flags = flags; | |
14567 | } | |
4fc85f37 JB |
14568 | if (cpu_arch[j].vsz == vsz_set) |
14569 | vector_size = VSZ_DEFAULT; | |
293f5f65 L |
14570 | break; |
14571 | } | |
293f5f65 L |
14572 | } |
14573 | ||
91d6fa6a | 14574 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 14575 | as_fatal (_("invalid -march= option: `%s'"), arg); |
6305a203 L |
14576 | |
14577 | arch = next; | |
9103f4f4 | 14578 | } |
293f5f65 L |
14579 | while (next != NULL); |
14580 | free (saved); | |
9103f4f4 L |
14581 | break; |
14582 | ||
14583 | case OPTION_MTUNE: | |
14584 | if (*arg == '.') | |
2b5d6a91 | 14585 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
91d6fa6a | 14586 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
9103f4f4 | 14587 | { |
ae89daec JB |
14588 | if (cpu_arch[j].type != PROCESSOR_NONE |
14589 | && strcmp (arg, cpu_arch[j].name) == 0) | |
9103f4f4 | 14590 | { |
ccc9c027 | 14591 | cpu_arch_tune_set = 1; |
91d6fa6a | 14592 | cpu_arch_tune = cpu_arch [j].type; |
ae89daec | 14593 | cpu_arch_tune_flags = cpu_arch[j].enable; |
9103f4f4 L |
14594 | break; |
14595 | } | |
14596 | } | |
91d6fa6a | 14597 | if (j >= ARRAY_SIZE (cpu_arch)) |
2b5d6a91 | 14598 | as_fatal (_("invalid -mtune= option: `%s'"), arg); |
9103f4f4 L |
14599 | break; |
14600 | ||
1efbbeb4 L |
14601 | case OPTION_MMNEMONIC: |
14602 | if (strcasecmp (arg, "att") == 0) | |
14603 | intel_mnemonic = 0; | |
14604 | else if (strcasecmp (arg, "intel") == 0) | |
14605 | intel_mnemonic = 1; | |
14606 | else | |
2b5d6a91 | 14607 | as_fatal (_("invalid -mmnemonic= option: `%s'"), arg); |
1efbbeb4 L |
14608 | break; |
14609 | ||
14610 | case OPTION_MSYNTAX: | |
14611 | if (strcasecmp (arg, "att") == 0) | |
14612 | intel_syntax = 0; | |
14613 | else if (strcasecmp (arg, "intel") == 0) | |
14614 | intel_syntax = 1; | |
14615 | else | |
2b5d6a91 | 14616 | as_fatal (_("invalid -msyntax= option: `%s'"), arg); |
1efbbeb4 L |
14617 | break; |
14618 | ||
14619 | case OPTION_MINDEX_REG: | |
14620 | allow_index_reg = 1; | |
14621 | break; | |
14622 | ||
14623 | case OPTION_MNAKED_REG: | |
14624 | allow_naked_reg = 1; | |
14625 | break; | |
14626 | ||
c0f3af97 L |
14627 | case OPTION_MSSE2AVX: |
14628 | sse2avx = 1; | |
14629 | break; | |
14630 | ||
c8480b58 L |
14631 | case OPTION_MUSE_UNALIGNED_VECTOR_MOVE: |
14632 | use_unaligned_vector_move = 1; | |
14633 | break; | |
14634 | ||
daf50ae7 L |
14635 | case OPTION_MSSE_CHECK: |
14636 | if (strcasecmp (arg, "error") == 0) | |
7bab8ab5 | 14637 | sse_check = check_error; |
daf50ae7 | 14638 | else if (strcasecmp (arg, "warning") == 0) |
7bab8ab5 | 14639 | sse_check = check_warning; |
daf50ae7 | 14640 | else if (strcasecmp (arg, "none") == 0) |
7bab8ab5 | 14641 | sse_check = check_none; |
daf50ae7 | 14642 | else |
2b5d6a91 | 14643 | as_fatal (_("invalid -msse-check= option: `%s'"), arg); |
daf50ae7 L |
14644 | break; |
14645 | ||
7bab8ab5 JB |
14646 | case OPTION_MOPERAND_CHECK: |
14647 | if (strcasecmp (arg, "error") == 0) | |
14648 | operand_check = check_error; | |
14649 | else if (strcasecmp (arg, "warning") == 0) | |
14650 | operand_check = check_warning; | |
14651 | else if (strcasecmp (arg, "none") == 0) | |
14652 | operand_check = check_none; | |
14653 | else | |
14654 | as_fatal (_("invalid -moperand-check= option: `%s'"), arg); | |
14655 | break; | |
14656 | ||
539f890d L |
14657 | case OPTION_MAVXSCALAR: |
14658 | if (strcasecmp (arg, "128") == 0) | |
14659 | avxscalar = vex128; | |
14660 | else if (strcasecmp (arg, "256") == 0) | |
14661 | avxscalar = vex256; | |
14662 | else | |
2b5d6a91 | 14663 | as_fatal (_("invalid -mavxscalar= option: `%s'"), arg); |
539f890d L |
14664 | break; |
14665 | ||
03751133 L |
14666 | case OPTION_MVEXWIG: |
14667 | if (strcmp (arg, "0") == 0) | |
40c9c8de | 14668 | vexwig = vexw0; |
03751133 | 14669 | else if (strcmp (arg, "1") == 0) |
40c9c8de | 14670 | vexwig = vexw1; |
03751133 L |
14671 | else |
14672 | as_fatal (_("invalid -mvexwig= option: `%s'"), arg); | |
14673 | break; | |
14674 | ||
7e8b059b L |
14675 | case OPTION_MADD_BND_PREFIX: |
14676 | add_bnd_prefix = 1; | |
14677 | break; | |
14678 | ||
43234a1e L |
14679 | case OPTION_MEVEXLIG: |
14680 | if (strcmp (arg, "128") == 0) | |
14681 | evexlig = evexl128; | |
14682 | else if (strcmp (arg, "256") == 0) | |
14683 | evexlig = evexl256; | |
14684 | else if (strcmp (arg, "512") == 0) | |
14685 | evexlig = evexl512; | |
14686 | else | |
14687 | as_fatal (_("invalid -mevexlig= option: `%s'"), arg); | |
14688 | break; | |
14689 | ||
d3d3c6db IT |
14690 | case OPTION_MEVEXRCIG: |
14691 | if (strcmp (arg, "rne") == 0) | |
14692 | evexrcig = rne; | |
14693 | else if (strcmp (arg, "rd") == 0) | |
14694 | evexrcig = rd; | |
14695 | else if (strcmp (arg, "ru") == 0) | |
14696 | evexrcig = ru; | |
14697 | else if (strcmp (arg, "rz") == 0) | |
14698 | evexrcig = rz; | |
14699 | else | |
14700 | as_fatal (_("invalid -mevexrcig= option: `%s'"), arg); | |
14701 | break; | |
14702 | ||
43234a1e L |
14703 | case OPTION_MEVEXWIG: |
14704 | if (strcmp (arg, "0") == 0) | |
14705 | evexwig = evexw0; | |
14706 | else if (strcmp (arg, "1") == 0) | |
14707 | evexwig = evexw1; | |
14708 | else | |
14709 | as_fatal (_("invalid -mevexwig= option: `%s'"), arg); | |
14710 | break; | |
14711 | ||
167ad85b TG |
14712 | # if defined (TE_PE) || defined (TE_PEP) |
14713 | case OPTION_MBIG_OBJ: | |
14714 | use_big_obj = 1; | |
14715 | break; | |
14716 | #endif | |
14717 | ||
d1982f93 | 14718 | case OPTION_MOMIT_LOCK_PREFIX: |
d022bddd IT |
14719 | if (strcasecmp (arg, "yes") == 0) |
14720 | omit_lock_prefix = 1; | |
14721 | else if (strcasecmp (arg, "no") == 0) | |
14722 | omit_lock_prefix = 0; | |
14723 | else | |
14724 | as_fatal (_("invalid -momit-lock-prefix= option: `%s'"), arg); | |
14725 | break; | |
14726 | ||
e4e00185 AS |
14727 | case OPTION_MFENCE_AS_LOCK_ADD: |
14728 | if (strcasecmp (arg, "yes") == 0) | |
14729 | avoid_fence = 1; | |
14730 | else if (strcasecmp (arg, "no") == 0) | |
14731 | avoid_fence = 0; | |
14732 | else | |
14733 | as_fatal (_("invalid -mfence-as-lock-add= option: `%s'"), arg); | |
14734 | break; | |
14735 | ||
ae531041 L |
14736 | case OPTION_MLFENCE_AFTER_LOAD: |
14737 | if (strcasecmp (arg, "yes") == 0) | |
14738 | lfence_after_load = 1; | |
14739 | else if (strcasecmp (arg, "no") == 0) | |
14740 | lfence_after_load = 0; | |
14741 | else | |
14742 | as_fatal (_("invalid -mlfence-after-load= option: `%s'"), arg); | |
14743 | break; | |
14744 | ||
14745 | case OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH: | |
14746 | if (strcasecmp (arg, "all") == 0) | |
a09f656b | 14747 | { |
14748 | lfence_before_indirect_branch = lfence_branch_all; | |
14749 | if (lfence_before_ret == lfence_before_ret_none) | |
14750 | lfence_before_ret = lfence_before_ret_shl; | |
14751 | } | |
ae531041 L |
14752 | else if (strcasecmp (arg, "memory") == 0) |
14753 | lfence_before_indirect_branch = lfence_branch_memory; | |
14754 | else if (strcasecmp (arg, "register") == 0) | |
14755 | lfence_before_indirect_branch = lfence_branch_register; | |
14756 | else if (strcasecmp (arg, "none") == 0) | |
14757 | lfence_before_indirect_branch = lfence_branch_none; | |
14758 | else | |
14759 | as_fatal (_("invalid -mlfence-before-indirect-branch= option: `%s'"), | |
14760 | arg); | |
14761 | break; | |
14762 | ||
14763 | case OPTION_MLFENCE_BEFORE_RET: | |
14764 | if (strcasecmp (arg, "or") == 0) | |
14765 | lfence_before_ret = lfence_before_ret_or; | |
14766 | else if (strcasecmp (arg, "not") == 0) | |
14767 | lfence_before_ret = lfence_before_ret_not; | |
a09f656b | 14768 | else if (strcasecmp (arg, "shl") == 0 || strcasecmp (arg, "yes") == 0) |
14769 | lfence_before_ret = lfence_before_ret_shl; | |
ae531041 L |
14770 | else if (strcasecmp (arg, "none") == 0) |
14771 | lfence_before_ret = lfence_before_ret_none; | |
14772 | else | |
14773 | as_fatal (_("invalid -mlfence-before-ret= option: `%s'"), | |
14774 | arg); | |
14775 | break; | |
14776 | ||
0cb4071e L |
14777 | case OPTION_MRELAX_RELOCATIONS: |
14778 | if (strcasecmp (arg, "yes") == 0) | |
14779 | generate_relax_relocations = 1; | |
14780 | else if (strcasecmp (arg, "no") == 0) | |
14781 | generate_relax_relocations = 0; | |
14782 | else | |
14783 | as_fatal (_("invalid -mrelax-relocations= option: `%s'"), arg); | |
14784 | break; | |
14785 | ||
e379e5f3 L |
14786 | case OPTION_MALIGN_BRANCH_BOUNDARY: |
14787 | { | |
14788 | char *end; | |
14789 | long int align = strtoul (arg, &end, 0); | |
14790 | if (*end == '\0') | |
14791 | { | |
14792 | if (align == 0) | |
14793 | { | |
14794 | align_branch_power = 0; | |
14795 | break; | |
14796 | } | |
14797 | else if (align >= 16) | |
14798 | { | |
14799 | int align_power; | |
14800 | for (align_power = 0; | |
14801 | (align & 1) == 0; | |
14802 | align >>= 1, align_power++) | |
14803 | continue; | |
14804 | /* Limit alignment power to 31. */ | |
14805 | if (align == 1 && align_power < 32) | |
14806 | { | |
14807 | align_branch_power = align_power; | |
14808 | break; | |
14809 | } | |
14810 | } | |
14811 | } | |
14812 | as_fatal (_("invalid -malign-branch-boundary= value: %s"), arg); | |
14813 | } | |
14814 | break; | |
14815 | ||
14816 | case OPTION_MALIGN_BRANCH_PREFIX_SIZE: | |
14817 | { | |
14818 | char *end; | |
14819 | int align = strtoul (arg, &end, 0); | |
14820 | /* Some processors only support 5 prefixes. */ | |
14821 | if (*end == '\0' && align >= 0 && align < 6) | |
14822 | { | |
14823 | align_branch_prefix_size = align; | |
14824 | break; | |
14825 | } | |
14826 | as_fatal (_("invalid -malign-branch-prefix-size= value: %s"), | |
14827 | arg); | |
14828 | } | |
14829 | break; | |
14830 | ||
14831 | case OPTION_MALIGN_BRANCH: | |
14832 | align_branch = 0; | |
14833 | saved = xstrdup (arg); | |
14834 | type = saved; | |
14835 | do | |
14836 | { | |
14837 | next = strchr (type, '+'); | |
14838 | if (next) | |
14839 | *next++ = '\0'; | |
14840 | if (strcasecmp (type, "jcc") == 0) | |
14841 | align_branch |= align_branch_jcc_bit; | |
14842 | else if (strcasecmp (type, "fused") == 0) | |
14843 | align_branch |= align_branch_fused_bit; | |
14844 | else if (strcasecmp (type, "jmp") == 0) | |
14845 | align_branch |= align_branch_jmp_bit; | |
14846 | else if (strcasecmp (type, "call") == 0) | |
14847 | align_branch |= align_branch_call_bit; | |
14848 | else if (strcasecmp (type, "ret") == 0) | |
14849 | align_branch |= align_branch_ret_bit; | |
14850 | else if (strcasecmp (type, "indirect") == 0) | |
14851 | align_branch |= align_branch_indirect_bit; | |
14852 | else | |
14853 | as_fatal (_("invalid -malign-branch= option: `%s'"), arg); | |
14854 | type = next; | |
14855 | } | |
14856 | while (next != NULL); | |
14857 | free (saved); | |
14858 | break; | |
14859 | ||
76cf450b L |
14860 | case OPTION_MBRANCHES_WITH_32B_BOUNDARIES: |
14861 | align_branch_power = 5; | |
14862 | align_branch_prefix_size = 5; | |
14863 | align_branch = (align_branch_jcc_bit | |
14864 | | align_branch_fused_bit | |
14865 | | align_branch_jmp_bit); | |
14866 | break; | |
14867 | ||
5db04b09 | 14868 | case OPTION_MAMD64: |
4b5aaf5f | 14869 | isa64 = amd64; |
5db04b09 L |
14870 | break; |
14871 | ||
14872 | case OPTION_MINTEL64: | |
4b5aaf5f | 14873 | isa64 = intel64; |
5db04b09 L |
14874 | break; |
14875 | ||
b6f8c7c4 L |
14876 | case 'O': |
14877 | if (arg == NULL) | |
14878 | { | |
14879 | optimize = 1; | |
14880 | /* Turn off -Os. */ | |
14881 | optimize_for_space = 0; | |
14882 | } | |
14883 | else if (*arg == 's') | |
14884 | { | |
14885 | optimize_for_space = 1; | |
14886 | /* Turn on all encoding optimizations. */ | |
41fd2579 | 14887 | optimize = INT_MAX; |
b6f8c7c4 L |
14888 | } |
14889 | else | |
14890 | { | |
14891 | optimize = atoi (arg); | |
14892 | /* Turn off -Os. */ | |
14893 | optimize_for_space = 0; | |
14894 | } | |
14895 | break; | |
14896 | ||
252b5132 RH |
14897 | default: |
14898 | return 0; | |
14899 | } | |
14900 | return 1; | |
14901 | } | |
14902 | ||
8a2c8fef L |
14903 | #define MESSAGE_TEMPLATE \ |
14904 | " " | |
14905 | ||
293f5f65 L |
14906 | static char * |
14907 | output_message (FILE *stream, char *p, char *message, char *start, | |
14908 | int *left_p, const char *name, int len) | |
14909 | { | |
14910 | int size = sizeof (MESSAGE_TEMPLATE); | |
14911 | int left = *left_p; | |
14912 | ||
14913 | /* Reserve 2 spaces for ", " or ",\0" */ | |
14914 | left -= len + 2; | |
14915 | ||
14916 | /* Check if there is any room. */ | |
14917 | if (left >= 0) | |
14918 | { | |
14919 | if (p != start) | |
14920 | { | |
14921 | *p++ = ','; | |
14922 | *p++ = ' '; | |
14923 | } | |
14924 | p = mempcpy (p, name, len); | |
14925 | } | |
14926 | else | |
14927 | { | |
14928 | /* Output the current message now and start a new one. */ | |
14929 | *p++ = ','; | |
14930 | *p = '\0'; | |
14931 | fprintf (stream, "%s\n", message); | |
14932 | p = start; | |
14933 | left = size - (start - message) - len - 2; | |
14934 | ||
14935 | gas_assert (left >= 0); | |
14936 | ||
14937 | p = mempcpy (p, name, len); | |
14938 | } | |
14939 | ||
14940 | *left_p = left; | |
14941 | return p; | |
14942 | } | |
14943 | ||
8a2c8fef | 14944 | static void |
1ded5609 | 14945 | show_arch (FILE *stream, int ext, int check) |
8a2c8fef L |
14946 | { |
14947 | static char message[] = MESSAGE_TEMPLATE; | |
14948 | char *start = message + 27; | |
14949 | char *p; | |
14950 | int size = sizeof (MESSAGE_TEMPLATE); | |
14951 | int left; | |
14952 | const char *name; | |
14953 | int len; | |
14954 | unsigned int j; | |
14955 | ||
14956 | p = start; | |
14957 | left = size - (start - message); | |
3ce2ebcf JB |
14958 | |
14959 | if (!ext && check) | |
14960 | { | |
14961 | p = output_message (stream, p, message, start, &left, | |
14962 | STRING_COMMA_LEN ("default")); | |
f68697e8 JB |
14963 | p = output_message (stream, p, message, start, &left, |
14964 | STRING_COMMA_LEN ("push")); | |
14965 | p = output_message (stream, p, message, start, &left, | |
14966 | STRING_COMMA_LEN ("pop")); | |
3ce2ebcf JB |
14967 | } |
14968 | ||
8a2c8fef L |
14969 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
14970 | { | |
14971 | /* Should it be skipped? */ | |
14972 | if (cpu_arch [j].skip) | |
14973 | continue; | |
14974 | ||
14975 | name = cpu_arch [j].name; | |
14976 | len = cpu_arch [j].len; | |
ae89daec | 14977 | if (cpu_arch[j].type == PROCESSOR_NONE) |
8a2c8fef L |
14978 | { |
14979 | /* It is an extension. Skip if we aren't asked to show it. */ | |
ae89daec | 14980 | if (!ext || cpu_flags_all_zero (&cpu_arch[j].enable)) |
8a2c8fef L |
14981 | continue; |
14982 | } | |
14983 | else if (ext) | |
14984 | { | |
14985 | /* It is an processor. Skip if we show only extension. */ | |
14986 | continue; | |
14987 | } | |
ae89daec | 14988 | else if (check && ! cpu_arch[j].enable.bitfield.cpui386) |
1ded5609 JB |
14989 | { |
14990 | /* It is an impossible processor - skip. */ | |
14991 | continue; | |
14992 | } | |
8a2c8fef | 14993 | |
293f5f65 | 14994 | p = output_message (stream, p, message, start, &left, name, len); |
8a2c8fef L |
14995 | } |
14996 | ||
293f5f65 L |
14997 | /* Display disabled extensions. */ |
14998 | if (ext) | |
ae89daec | 14999 | for (j = 0; j < ARRAY_SIZE (cpu_arch); j++) |
293f5f65 | 15000 | { |
ae89daec JB |
15001 | char *str; |
15002 | ||
15003 | if (cpu_arch[j].type != PROCESSOR_NONE | |
15004 | || !cpu_flags_all_zero (&cpu_arch[j].enable)) | |
15005 | continue; | |
15006 | str = xasprintf ("no%s", cpu_arch[j].name); | |
15007 | p = output_message (stream, p, message, start, &left, str, | |
15008 | strlen (str)); | |
15009 | free (str); | |
293f5f65 L |
15010 | } |
15011 | ||
8a2c8fef L |
15012 | *p = '\0'; |
15013 | fprintf (stream, "%s\n", message); | |
15014 | } | |
15015 | ||
252b5132 | 15016 | void |
8a2c8fef | 15017 | md_show_usage (FILE *stream) |
252b5132 | 15018 | { |
4cc782b5 ILT |
15019 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
15020 | fprintf (stream, _("\ | |
d4693039 | 15021 | -Qy, -Qn ignored\n\ |
a38cf1db | 15022 | -V print assembler version number\n\ |
b3b91714 AM |
15023 | -k ignored\n")); |
15024 | #endif | |
15025 | fprintf (stream, _("\ | |
7ebd68d1 NC |
15026 | -n do not optimize code alignment\n\ |
15027 | -O{012s} attempt some code optimizations\n\ | |
b3b91714 AM |
15028 | -q quieten some warnings\n")); |
15029 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15030 | fprintf (stream, _("\ | |
a38cf1db | 15031 | -s ignored\n")); |
b3b91714 | 15032 | #endif |
b00af7c8 JB |
15033 | #ifdef BFD64 |
15034 | # if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15035 | fprintf (stream, _("\ | |
15036 | --32/--64/--x32 generate 32bit/64bit/x32 object\n")); | |
15037 | # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O) | |
751d281c | 15038 | fprintf (stream, _("\ |
b00af7c8 JB |
15039 | --32/--64 generate 32bit/64bit object\n")); |
15040 | # endif | |
751d281c | 15041 | #endif |
b3b91714 AM |
15042 | #ifdef SVR4_COMMENT_CHARS |
15043 | fprintf (stream, _("\ | |
15044 | --divide do not treat `/' as a comment character\n")); | |
a38cf1db AM |
15045 | #else |
15046 | fprintf (stream, _("\ | |
b3b91714 | 15047 | --divide ignored\n")); |
4cc782b5 | 15048 | #endif |
9103f4f4 | 15049 | fprintf (stream, _("\ |
6305a203 | 15050 | -march=CPU[,+EXTENSION...]\n\ |
8a2c8fef | 15051 | generate code for CPU and EXTENSION, CPU is one of:\n")); |
1ded5609 | 15052 | show_arch (stream, 0, 1); |
8a2c8fef | 15053 | fprintf (stream, _("\ |
ae89daec | 15054 | EXTENSION is combination of (possibly \"no\"-prefixed):\n")); |
1ded5609 | 15055 | show_arch (stream, 1, 0); |
6305a203 | 15056 | fprintf (stream, _("\ |
8a2c8fef | 15057 | -mtune=CPU optimize for CPU, CPU is one of:\n")); |
1ded5609 | 15058 | show_arch (stream, 0, 0); |
ba104c83 | 15059 | fprintf (stream, _("\ |
c0f3af97 L |
15060 | -msse2avx encode SSE instructions with VEX prefix\n")); |
15061 | fprintf (stream, _("\ | |
c8480b58 L |
15062 | -muse-unaligned-vector-move\n\ |
15063 | encode aligned vector move as unaligned vector move\n")); | |
15064 | fprintf (stream, _("\ | |
7c5c05ef | 15065 | -msse-check=[none|error|warning] (default: warning)\n\ |
daf50ae7 L |
15066 | check SSE instructions\n")); |
15067 | fprintf (stream, _("\ | |
7c5c05ef | 15068 | -moperand-check=[none|error|warning] (default: warning)\n\ |
7bab8ab5 JB |
15069 | check operand combinations for validity\n")); |
15070 | fprintf (stream, _("\ | |
7c5c05ef L |
15071 | -mavxscalar=[128|256] (default: 128)\n\ |
15072 | encode scalar AVX instructions with specific vector\n\ | |
539f890d L |
15073 | length\n")); |
15074 | fprintf (stream, _("\ | |
03751133 L |
15075 | -mvexwig=[0|1] (default: 0)\n\ |
15076 | encode VEX instructions with specific VEX.W value\n\ | |
15077 | for VEX.W bit ignored instructions\n")); | |
15078 | fprintf (stream, _("\ | |
7c5c05ef L |
15079 | -mevexlig=[128|256|512] (default: 128)\n\ |
15080 | encode scalar EVEX instructions with specific vector\n\ | |
43234a1e L |
15081 | length\n")); |
15082 | fprintf (stream, _("\ | |
7c5c05ef L |
15083 | -mevexwig=[0|1] (default: 0)\n\ |
15084 | encode EVEX instructions with specific EVEX.W value\n\ | |
43234a1e L |
15085 | for EVEX.W bit ignored instructions\n")); |
15086 | fprintf (stream, _("\ | |
7c5c05ef | 15087 | -mevexrcig=[rne|rd|ru|rz] (default: rne)\n\ |
d3d3c6db IT |
15088 | encode EVEX instructions with specific EVEX.RC value\n\ |
15089 | for SAE-only ignored instructions\n")); | |
15090 | fprintf (stream, _("\ | |
7c5c05ef L |
15091 | -mmnemonic=[att|intel] ")); |
15092 | if (SYSV386_COMPAT) | |
15093 | fprintf (stream, _("(default: att)\n")); | |
15094 | else | |
15095 | fprintf (stream, _("(default: intel)\n")); | |
15096 | fprintf (stream, _("\ | |
15097 | use AT&T/Intel mnemonic\n")); | |
ba104c83 | 15098 | fprintf (stream, _("\ |
7c5c05ef L |
15099 | -msyntax=[att|intel] (default: att)\n\ |
15100 | use AT&T/Intel syntax\n")); | |
ba104c83 L |
15101 | fprintf (stream, _("\ |
15102 | -mindex-reg support pseudo index registers\n")); | |
15103 | fprintf (stream, _("\ | |
15104 | -mnaked-reg don't require `%%' prefix for registers\n")); | |
15105 | fprintf (stream, _("\ | |
7e8b059b | 15106 | -madd-bnd-prefix add BND prefix for all valid branches\n")); |
b4a3a7b4 | 15107 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
8dcea932 L |
15108 | fprintf (stream, _("\ |
15109 | -mshared disable branch optimization for shared code\n")); | |
b4a3a7b4 L |
15110 | fprintf (stream, _("\ |
15111 | -mx86-used-note=[no|yes] ")); | |
15112 | if (DEFAULT_X86_USED_NOTE) | |
15113 | fprintf (stream, _("(default: yes)\n")); | |
15114 | else | |
15115 | fprintf (stream, _("(default: no)\n")); | |
15116 | fprintf (stream, _("\ | |
15117 | generate x86 used ISA and feature properties\n")); | |
15118 | #endif | |
15119 | #if defined (TE_PE) || defined (TE_PEP) | |
167ad85b TG |
15120 | fprintf (stream, _("\ |
15121 | -mbig-obj generate big object files\n")); | |
15122 | #endif | |
d022bddd | 15123 | fprintf (stream, _("\ |
7c5c05ef | 15124 | -momit-lock-prefix=[no|yes] (default: no)\n\ |
d022bddd | 15125 | strip all lock prefixes\n")); |
5db04b09 | 15126 | fprintf (stream, _("\ |
7c5c05ef | 15127 | -mfence-as-lock-add=[no|yes] (default: no)\n\ |
e4e00185 AS |
15128 | encode lfence, mfence and sfence as\n\ |
15129 | lock addl $0x0, (%%{re}sp)\n")); | |
15130 | fprintf (stream, _("\ | |
7c5c05ef L |
15131 | -mrelax-relocations=[no|yes] ")); |
15132 | if (DEFAULT_GENERATE_X86_RELAX_RELOCATIONS) | |
15133 | fprintf (stream, _("(default: yes)\n")); | |
15134 | else | |
15135 | fprintf (stream, _("(default: no)\n")); | |
15136 | fprintf (stream, _("\ | |
0cb4071e L |
15137 | generate relax relocations\n")); |
15138 | fprintf (stream, _("\ | |
e379e5f3 L |
15139 | -malign-branch-boundary=NUM (default: 0)\n\ |
15140 | align branches within NUM byte boundary\n")); | |
15141 | fprintf (stream, _("\ | |
15142 | -malign-branch=TYPE[+TYPE...] (default: jcc+fused+jmp)\n\ | |
15143 | TYPE is combination of jcc, fused, jmp, call, ret,\n\ | |
15144 | indirect\n\ | |
15145 | specify types of branches to align\n")); | |
15146 | fprintf (stream, _("\ | |
15147 | -malign-branch-prefix-size=NUM (default: 5)\n\ | |
15148 | align branches with NUM prefixes per instruction\n")); | |
15149 | fprintf (stream, _("\ | |
76cf450b L |
15150 | -mbranches-within-32B-boundaries\n\ |
15151 | align branches within 32 byte boundary\n")); | |
15152 | fprintf (stream, _("\ | |
ae531041 L |
15153 | -mlfence-after-load=[no|yes] (default: no)\n\ |
15154 | generate lfence after load\n")); | |
15155 | fprintf (stream, _("\ | |
15156 | -mlfence-before-indirect-branch=[none|all|register|memory] (default: none)\n\ | |
15157 | generate lfence before indirect near branch\n")); | |
15158 | fprintf (stream, _("\ | |
a09f656b | 15159 | -mlfence-before-ret=[none|or|not|shl|yes] (default: none)\n\ |
ae531041 L |
15160 | generate lfence before ret\n")); |
15161 | fprintf (stream, _("\ | |
7c5c05ef | 15162 | -mamd64 accept only AMD64 ISA [default]\n")); |
5db04b09 L |
15163 | fprintf (stream, _("\ |
15164 | -mintel64 accept only Intel64 ISA\n")); | |
252b5132 RH |
15165 | } |
15166 | ||
3e73aa7c | 15167 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
321098a5 | 15168 | || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \ |
e57f8c65 | 15169 | || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)) |
252b5132 RH |
15170 | |
15171 | /* Pick the target format to use. */ | |
15172 | ||
47926f60 | 15173 | const char * |
e3bb37b5 | 15174 | i386_target_format (void) |
252b5132 | 15175 | { |
d34049e8 | 15176 | if (startswith (default_arch, "x86_64")) |
351f65ca L |
15177 | { |
15178 | update_code_flag (CODE_64BIT, 1); | |
15179 | if (default_arch[6] == '\0') | |
7f56bc95 | 15180 | x86_elf_abi = X86_64_ABI; |
351f65ca | 15181 | else |
7f56bc95 | 15182 | x86_elf_abi = X86_64_X32_ABI; |
351f65ca | 15183 | } |
3e73aa7c | 15184 | else if (!strcmp (default_arch, "i386")) |
78f12dd3 | 15185 | update_code_flag (CODE_32BIT, 1); |
5197d474 L |
15186 | else if (!strcmp (default_arch, "iamcu")) |
15187 | { | |
15188 | update_code_flag (CODE_32BIT, 1); | |
15189 | if (cpu_arch_isa == PROCESSOR_UNKNOWN) | |
15190 | { | |
15191 | static const i386_cpu_flags iamcu_flags = CPU_IAMCU_FLAGS; | |
15192 | cpu_arch_name = "iamcu"; | |
d92c7521 | 15193 | free (cpu_sub_arch_name); |
5197d474 L |
15194 | cpu_sub_arch_name = NULL; |
15195 | cpu_arch_flags = iamcu_flags; | |
15196 | cpu_arch_isa = PROCESSOR_IAMCU; | |
15197 | cpu_arch_isa_flags = iamcu_flags; | |
15198 | if (!cpu_arch_tune_set) | |
15199 | { | |
15200 | cpu_arch_tune = cpu_arch_isa; | |
15201 | cpu_arch_tune_flags = cpu_arch_isa_flags; | |
15202 | } | |
15203 | } | |
8d471ec1 | 15204 | else if (cpu_arch_isa != PROCESSOR_IAMCU) |
5197d474 L |
15205 | as_fatal (_("Intel MCU doesn't support `%s' architecture"), |
15206 | cpu_arch_name); | |
15207 | } | |
3e73aa7c | 15208 | else |
2b5d6a91 | 15209 | as_fatal (_("unknown architecture")); |
89507696 JB |
15210 | |
15211 | if (cpu_flags_all_zero (&cpu_arch_isa_flags)) | |
ae89daec | 15212 | cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 15213 | if (cpu_flags_all_zero (&cpu_arch_tune_flags)) |
ae89daec | 15214 | cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].enable; |
89507696 | 15215 | |
252b5132 RH |
15216 | switch (OUTPUT_FLAVOR) |
15217 | { | |
9384f2ff | 15218 | #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT) |
4c63da97 | 15219 | case bfd_target_aout_flavour: |
47926f60 | 15220 | return AOUT_TARGET_FORMAT; |
4c63da97 | 15221 | #endif |
9384f2ff AM |
15222 | #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) |
15223 | # if defined (TE_PE) || defined (TE_PEP) | |
15224 | case bfd_target_coff_flavour: | |
167ad85b | 15225 | if (flag_code == CODE_64BIT) |
eb19308f JB |
15226 | { |
15227 | object_64bit = 1; | |
15228 | return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; | |
15229 | } | |
15230 | return use_big_obj ? "pe-bigobj-i386" : "pe-i386"; | |
9384f2ff | 15231 | # elif defined (TE_GO32) |
0561d57c JK |
15232 | case bfd_target_coff_flavour: |
15233 | return "coff-go32"; | |
9384f2ff | 15234 | # else |
252b5132 RH |
15235 | case bfd_target_coff_flavour: |
15236 | return "coff-i386"; | |
9384f2ff | 15237 | # endif |
4c63da97 | 15238 | #endif |
3e73aa7c | 15239 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) |
252b5132 | 15240 | case bfd_target_elf_flavour: |
3e73aa7c | 15241 | { |
351f65ca L |
15242 | const char *format; |
15243 | ||
15244 | switch (x86_elf_abi) | |
4fa24527 | 15245 | { |
351f65ca L |
15246 | default: |
15247 | format = ELF_TARGET_FORMAT; | |
e379e5f3 L |
15248 | #ifndef TE_SOLARIS |
15249 | tls_get_addr = "___tls_get_addr"; | |
15250 | #endif | |
351f65ca | 15251 | break; |
7f56bc95 | 15252 | case X86_64_ABI: |
351f65ca | 15253 | use_rela_relocations = 1; |
4fa24527 | 15254 | object_64bit = 1; |
e379e5f3 L |
15255 | #ifndef TE_SOLARIS |
15256 | tls_get_addr = "__tls_get_addr"; | |
15257 | #endif | |
351f65ca L |
15258 | format = ELF_TARGET_FORMAT64; |
15259 | break; | |
7f56bc95 | 15260 | case X86_64_X32_ABI: |
4fa24527 | 15261 | use_rela_relocations = 1; |
351f65ca | 15262 | object_64bit = 1; |
e379e5f3 L |
15263 | #ifndef TE_SOLARIS |
15264 | tls_get_addr = "__tls_get_addr"; | |
15265 | #endif | |
862be3fb | 15266 | disallow_64bit_reloc = 1; |
351f65ca L |
15267 | format = ELF_TARGET_FORMAT32; |
15268 | break; | |
4fa24527 | 15269 | } |
c085ab00 | 15270 | if (cpu_arch_isa == PROCESSOR_IAMCU) |
81486035 L |
15271 | { |
15272 | if (x86_elf_abi != I386_ABI) | |
15273 | as_fatal (_("Intel MCU is 32bit only")); | |
15274 | return ELF_TARGET_IAMCU_FORMAT; | |
15275 | } | |
8a9036a4 | 15276 | else |
351f65ca | 15277 | return format; |
3e73aa7c | 15278 | } |
e57f8c65 TG |
15279 | #endif |
15280 | #if defined (OBJ_MACH_O) | |
15281 | case bfd_target_mach_o_flavour: | |
d382c579 TG |
15282 | if (flag_code == CODE_64BIT) |
15283 | { | |
15284 | use_rela_relocations = 1; | |
15285 | object_64bit = 1; | |
15286 | return "mach-o-x86-64"; | |
15287 | } | |
15288 | else | |
15289 | return "mach-o-i386"; | |
4c63da97 | 15290 | #endif |
252b5132 RH |
15291 | default: |
15292 | abort (); | |
15293 | return NULL; | |
15294 | } | |
15295 | } | |
15296 | ||
47926f60 | 15297 | #endif /* OBJ_MAYBE_ more than one */ |
252b5132 | 15298 | \f |
252b5132 | 15299 | symbolS * |
7016a5d5 | 15300 | md_undefined_symbol (char *name) |
252b5132 | 15301 | { |
18dc2407 ILT |
15302 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0] |
15303 | && name[1] == GLOBAL_OFFSET_TABLE_NAME[1] | |
15304 | && name[2] == GLOBAL_OFFSET_TABLE_NAME[2] | |
15305 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0) | |
24eab124 AM |
15306 | { |
15307 | if (!GOT_symbol) | |
15308 | { | |
15309 | if (symbol_find (name)) | |
15310 | as_bad (_("GOT already in symbol table")); | |
15311 | GOT_symbol = symbol_new (name, undefined_section, | |
e01e1cee | 15312 | &zero_address_frag, 0); |
24eab124 AM |
15313 | }; |
15314 | return GOT_symbol; | |
15315 | } | |
252b5132 RH |
15316 | return 0; |
15317 | } | |
15318 | ||
15319 | /* Round up a section size to the appropriate boundary. */ | |
47926f60 | 15320 | |
252b5132 | 15321 | valueT |
7016a5d5 | 15322 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
252b5132 | 15323 | { |
4c63da97 AM |
15324 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
15325 | if (OUTPUT_FLAVOR == bfd_target_aout_flavour) | |
15326 | { | |
15327 | /* For a.out, force the section size to be aligned. If we don't do | |
15328 | this, BFD will align it for us, but it will not write out the | |
15329 | final bytes of the section. This may be a bug in BFD, but it is | |
15330 | easier to fix it here since that is how the other a.out targets | |
15331 | work. */ | |
15332 | int align; | |
15333 | ||
fd361982 | 15334 | align = bfd_section_alignment (segment); |
8d3842cd | 15335 | size = ((size + (1 << align) - 1) & (-((valueT) 1 << align))); |
4c63da97 | 15336 | } |
252b5132 RH |
15337 | #endif |
15338 | ||
15339 | return size; | |
15340 | } | |
15341 | ||
15342 | /* On the i386, PC-relative offsets are relative to the start of the | |
15343 | next instruction. That is, the address of the offset, plus its | |
15344 | size, since the offset is always the last part of the insn. */ | |
15345 | ||
15346 | long | |
e3bb37b5 | 15347 | md_pcrel_from (fixS *fixP) |
252b5132 RH |
15348 | { |
15349 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; | |
15350 | } | |
15351 | ||
15352 | #ifndef I386COFF | |
15353 | ||
15354 | static void | |
e3bb37b5 | 15355 | s_bss (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 15356 | { |
29b0f896 | 15357 | int temp; |
252b5132 | 15358 | |
8a75718c JB |
15359 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
15360 | if (IS_ELF) | |
15361 | obj_elf_section_change_hook (); | |
15362 | #endif | |
252b5132 RH |
15363 | temp = get_absolute_expression (); |
15364 | subseg_set (bss_section, (subsegT) temp); | |
15365 | demand_empty_rest_of_line (); | |
15366 | } | |
15367 | ||
15368 | #endif | |
15369 | ||
e379e5f3 L |
15370 | /* Remember constant directive. */ |
15371 | ||
15372 | void | |
15373 | i386_cons_align (int ignore ATTRIBUTE_UNUSED) | |
15374 | { | |
15375 | if (last_insn.kind != last_insn_directive | |
15376 | && (bfd_section_flags (now_seg) & SEC_CODE)) | |
15377 | { | |
15378 | last_insn.seg = now_seg; | |
15379 | last_insn.kind = last_insn_directive; | |
15380 | last_insn.name = "constant directive"; | |
15381 | last_insn.file = as_where (&last_insn.line); | |
ae531041 L |
15382 | if (lfence_before_ret != lfence_before_ret_none) |
15383 | { | |
15384 | if (lfence_before_indirect_branch != lfence_branch_none) | |
15385 | as_warn (_("constant directive skips -mlfence-before-ret " | |
15386 | "and -mlfence-before-indirect-branch")); | |
15387 | else | |
15388 | as_warn (_("constant directive skips -mlfence-before-ret")); | |
15389 | } | |
15390 | else if (lfence_before_indirect_branch != lfence_branch_none) | |
15391 | as_warn (_("constant directive skips -mlfence-before-indirect-branch")); | |
e379e5f3 L |
15392 | } |
15393 | } | |
15394 | ||
3abbafc2 | 15395 | int |
e3bb37b5 | 15396 | i386_validate_fix (fixS *fixp) |
252b5132 | 15397 | { |
e52a16f2 JB |
15398 | if (fixp->fx_addsy && S_GET_SEGMENT(fixp->fx_addsy) == reg_section) |
15399 | { | |
15400 | reloc_howto_type *howto; | |
15401 | ||
15402 | howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
15403 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
15404 | _("invalid %s relocation against register"), | |
15405 | howto ? howto->name : "<unknown>"); | |
15406 | return 0; | |
15407 | } | |
15408 | ||
3abbafc2 JB |
15409 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
15410 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 | |
15411 | || fixp->fx_r_type == BFD_RELOC_SIZE64) | |
15412 | return IS_ELF && fixp->fx_addsy | |
15413 | && (!S_IS_DEFINED (fixp->fx_addsy) | |
15414 | || S_IS_EXTERNAL (fixp->fx_addsy)); | |
15415 | #endif | |
15416 | ||
02a86693 | 15417 | if (fixp->fx_subsy) |
252b5132 | 15418 | { |
02a86693 | 15419 | if (fixp->fx_subsy == GOT_symbol) |
23df1078 | 15420 | { |
02a86693 L |
15421 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
15422 | { | |
15423 | if (!object_64bit) | |
15424 | abort (); | |
15425 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15426 | if (fixp->fx_tcbit2) | |
56ceb5b5 L |
15427 | fixp->fx_r_type = (fixp->fx_tcbit |
15428 | ? BFD_RELOC_X86_64_REX_GOTPCRELX | |
15429 | : BFD_RELOC_X86_64_GOTPCRELX); | |
02a86693 L |
15430 | else |
15431 | #endif | |
15432 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; | |
15433 | } | |
d6ab8113 | 15434 | else |
02a86693 L |
15435 | { |
15436 | if (!object_64bit) | |
15437 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; | |
15438 | else | |
15439 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; | |
15440 | } | |
15441 | fixp->fx_subsy = 0; | |
23df1078 | 15442 | } |
252b5132 | 15443 | } |
02a86693 | 15444 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
2585b7a5 | 15445 | else |
02a86693 | 15446 | { |
2585b7a5 L |
15447 | /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol |
15448 | to section. Since PLT32 relocation must be against symbols, | |
15449 | turn such PLT32 relocation into PC32 relocation. */ | |
15450 | if (fixp->fx_addsy | |
15451 | && (fixp->fx_r_type == BFD_RELOC_386_PLT32 | |
15452 | || fixp->fx_r_type == BFD_RELOC_X86_64_PLT32) | |
15453 | && symbol_section_p (fixp->fx_addsy)) | |
15454 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
15455 | if (!object_64bit) | |
15456 | { | |
15457 | if (fixp->fx_r_type == BFD_RELOC_386_GOT32 | |
15458 | && fixp->fx_tcbit2) | |
15459 | fixp->fx_r_type = BFD_RELOC_386_GOT32X; | |
15460 | } | |
02a86693 L |
15461 | } |
15462 | #endif | |
3abbafc2 JB |
15463 | |
15464 | return 1; | |
252b5132 RH |
15465 | } |
15466 | ||
252b5132 | 15467 | arelent * |
7016a5d5 | 15468 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
15469 | { |
15470 | arelent *rel; | |
15471 | bfd_reloc_code_real_type code; | |
15472 | ||
15473 | switch (fixp->fx_r_type) | |
15474 | { | |
8ce3d284 | 15475 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) |
3abbafc2 JB |
15476 | symbolS *sym; |
15477 | ||
8fd4256d L |
15478 | case BFD_RELOC_SIZE32: |
15479 | case BFD_RELOC_SIZE64: | |
3abbafc2 JB |
15480 | if (fixp->fx_addsy |
15481 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)) | |
15482 | && (!fixp->fx_subsy | |
15483 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)))) | |
15484 | sym = fixp->fx_addsy; | |
15485 | else if (fixp->fx_subsy | |
15486 | && !bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_subsy)) | |
15487 | && (!fixp->fx_addsy | |
15488 | || bfd_is_abs_section (S_GET_SEGMENT (fixp->fx_addsy)))) | |
15489 | sym = fixp->fx_subsy; | |
15490 | else | |
15491 | sym = NULL; | |
15492 | if (IS_ELF && sym && S_IS_DEFINED (sym) && !S_IS_EXTERNAL (sym)) | |
8fd4256d L |
15493 | { |
15494 | /* Resolve size relocation against local symbol to size of | |
15495 | the symbol plus addend. */ | |
3abbafc2 | 15496 | valueT value = S_GET_SIZE (sym); |
44f87162 | 15497 | |
3abbafc2 JB |
15498 | if (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) |
15499 | value = bfd_section_size (S_GET_SEGMENT (sym)); | |
15500 | if (sym == fixp->fx_subsy) | |
15501 | { | |
15502 | value = -value; | |
15503 | if (fixp->fx_addsy) | |
15504 | value += S_GET_VALUE (fixp->fx_addsy); | |
15505 | } | |
15506 | else if (fixp->fx_subsy) | |
15507 | value -= S_GET_VALUE (fixp->fx_subsy); | |
44f87162 | 15508 | value += fixp->fx_offset; |
8fd4256d | 15509 | if (fixp->fx_r_type == BFD_RELOC_SIZE32 |
d965814f | 15510 | && object_64bit |
8fd4256d L |
15511 | && !fits_in_unsigned_long (value)) |
15512 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
15513 | _("symbol size computation overflow")); | |
15514 | fixp->fx_addsy = NULL; | |
15515 | fixp->fx_subsy = NULL; | |
15516 | md_apply_fix (fixp, (valueT *) &value, NULL); | |
15517 | return NULL; | |
15518 | } | |
3abbafc2 JB |
15519 | if (!fixp->fx_addsy || fixp->fx_subsy) |
15520 | { | |
15521 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
15522 | "unsupported expression involving @size"); | |
15523 | return NULL; | |
15524 | } | |
8ce3d284 | 15525 | #endif |
1a0670f3 | 15526 | /* Fall through. */ |
8fd4256d | 15527 | |
3e73aa7c JH |
15528 | case BFD_RELOC_X86_64_PLT32: |
15529 | case BFD_RELOC_X86_64_GOT32: | |
15530 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
15531 | case BFD_RELOC_X86_64_GOTPCRELX: |
15532 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
252b5132 RH |
15533 | case BFD_RELOC_386_PLT32: |
15534 | case BFD_RELOC_386_GOT32: | |
02a86693 | 15535 | case BFD_RELOC_386_GOT32X: |
252b5132 RH |
15536 | case BFD_RELOC_386_GOTOFF: |
15537 | case BFD_RELOC_386_GOTPC: | |
13ae64f3 JJ |
15538 | case BFD_RELOC_386_TLS_GD: |
15539 | case BFD_RELOC_386_TLS_LDM: | |
15540 | case BFD_RELOC_386_TLS_LDO_32: | |
15541 | case BFD_RELOC_386_TLS_IE_32: | |
37e55690 JJ |
15542 | case BFD_RELOC_386_TLS_IE: |
15543 | case BFD_RELOC_386_TLS_GOTIE: | |
13ae64f3 JJ |
15544 | case BFD_RELOC_386_TLS_LE_32: |
15545 | case BFD_RELOC_386_TLS_LE: | |
67a4f2b7 AO |
15546 | case BFD_RELOC_386_TLS_GOTDESC: |
15547 | case BFD_RELOC_386_TLS_DESC_CALL: | |
bffbf940 JJ |
15548 | case BFD_RELOC_X86_64_TLSGD: |
15549 | case BFD_RELOC_X86_64_TLSLD: | |
15550 | case BFD_RELOC_X86_64_DTPOFF32: | |
d6ab8113 | 15551 | case BFD_RELOC_X86_64_DTPOFF64: |
bffbf940 JJ |
15552 | case BFD_RELOC_X86_64_GOTTPOFF: |
15553 | case BFD_RELOC_X86_64_TPOFF32: | |
d6ab8113 JB |
15554 | case BFD_RELOC_X86_64_TPOFF64: |
15555 | case BFD_RELOC_X86_64_GOTOFF64: | |
15556 | case BFD_RELOC_X86_64_GOTPC32: | |
7b81dfbb AJ |
15557 | case BFD_RELOC_X86_64_GOT64: |
15558 | case BFD_RELOC_X86_64_GOTPCREL64: | |
15559 | case BFD_RELOC_X86_64_GOTPC64: | |
15560 | case BFD_RELOC_X86_64_GOTPLT64: | |
15561 | case BFD_RELOC_X86_64_PLTOFF64: | |
67a4f2b7 AO |
15562 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
15563 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
252b5132 RH |
15564 | case BFD_RELOC_RVA: |
15565 | case BFD_RELOC_VTABLE_ENTRY: | |
15566 | case BFD_RELOC_VTABLE_INHERIT: | |
6482c264 NC |
15567 | #ifdef TE_PE |
15568 | case BFD_RELOC_32_SECREL: | |
145667f8 | 15569 | case BFD_RELOC_16_SECIDX: |
6482c264 | 15570 | #endif |
252b5132 RH |
15571 | code = fixp->fx_r_type; |
15572 | break; | |
dbbaec26 L |
15573 | case BFD_RELOC_X86_64_32S: |
15574 | if (!fixp->fx_pcrel) | |
15575 | { | |
15576 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ | |
15577 | code = fixp->fx_r_type; | |
15578 | break; | |
15579 | } | |
1a0670f3 | 15580 | /* Fall through. */ |
252b5132 | 15581 | default: |
93382f6d | 15582 | if (fixp->fx_pcrel) |
252b5132 | 15583 | { |
93382f6d AM |
15584 | switch (fixp->fx_size) |
15585 | { | |
15586 | default: | |
b091f402 AM |
15587 | as_bad_where (fixp->fx_file, fixp->fx_line, |
15588 | _("can not do %d byte pc-relative relocation"), | |
15589 | fixp->fx_size); | |
93382f6d AM |
15590 | code = BFD_RELOC_32_PCREL; |
15591 | break; | |
15592 | case 1: code = BFD_RELOC_8_PCREL; break; | |
15593 | case 2: code = BFD_RELOC_16_PCREL; break; | |
d258b828 | 15594 | case 4: code = BFD_RELOC_32_PCREL; break; |
d6ab8113 JB |
15595 | #ifdef BFD64 |
15596 | case 8: code = BFD_RELOC_64_PCREL; break; | |
15597 | #endif | |
93382f6d AM |
15598 | } |
15599 | } | |
15600 | else | |
15601 | { | |
15602 | switch (fixp->fx_size) | |
15603 | { | |
15604 | default: | |
b091f402 AM |
15605 | as_bad_where (fixp->fx_file, fixp->fx_line, |
15606 | _("can not do %d byte relocation"), | |
15607 | fixp->fx_size); | |
93382f6d AM |
15608 | code = BFD_RELOC_32; |
15609 | break; | |
15610 | case 1: code = BFD_RELOC_8; break; | |
15611 | case 2: code = BFD_RELOC_16; break; | |
15612 | case 4: code = BFD_RELOC_32; break; | |
937149dd | 15613 | #ifdef BFD64 |
3e73aa7c | 15614 | case 8: code = BFD_RELOC_64; break; |
937149dd | 15615 | #endif |
93382f6d | 15616 | } |
252b5132 RH |
15617 | } |
15618 | break; | |
15619 | } | |
252b5132 | 15620 | |
d182319b JB |
15621 | if ((code == BFD_RELOC_32 |
15622 | || code == BFD_RELOC_32_PCREL | |
15623 | || code == BFD_RELOC_X86_64_32S) | |
252b5132 RH |
15624 | && GOT_symbol |
15625 | && fixp->fx_addsy == GOT_symbol) | |
3e73aa7c | 15626 | { |
4fa24527 | 15627 | if (!object_64bit) |
d6ab8113 JB |
15628 | code = BFD_RELOC_386_GOTPC; |
15629 | else | |
15630 | code = BFD_RELOC_X86_64_GOTPC32; | |
3e73aa7c | 15631 | } |
7b81dfbb AJ |
15632 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
15633 | && GOT_symbol | |
15634 | && fixp->fx_addsy == GOT_symbol) | |
15635 | { | |
15636 | code = BFD_RELOC_X86_64_GOTPC64; | |
15637 | } | |
252b5132 | 15638 | |
add39d23 TS |
15639 | rel = XNEW (arelent); |
15640 | rel->sym_ptr_ptr = XNEW (asymbol *); | |
49309057 | 15641 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 RH |
15642 | |
15643 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
c87db184 | 15644 | |
3e73aa7c JH |
15645 | if (!use_rela_relocations) |
15646 | { | |
15647 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the | |
15648 | vtable entry to be used in the relocation's section offset. */ | |
15649 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
15650 | rel->address = fixp->fx_offset; | |
fbeb56a4 DK |
15651 | #if defined (OBJ_COFF) && defined (TE_PE) |
15652 | else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy)) | |
15653 | rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2); | |
15654 | else | |
15655 | #endif | |
c6682705 | 15656 | rel->addend = 0; |
3e73aa7c JH |
15657 | } |
15658 | /* Use the rela in 64bit mode. */ | |
252b5132 | 15659 | else |
3e73aa7c | 15660 | { |
862be3fb L |
15661 | if (disallow_64bit_reloc) |
15662 | switch (code) | |
15663 | { | |
862be3fb L |
15664 | case BFD_RELOC_X86_64_DTPOFF64: |
15665 | case BFD_RELOC_X86_64_TPOFF64: | |
15666 | case BFD_RELOC_64_PCREL: | |
15667 | case BFD_RELOC_X86_64_GOTOFF64: | |
15668 | case BFD_RELOC_X86_64_GOT64: | |
15669 | case BFD_RELOC_X86_64_GOTPCREL64: | |
15670 | case BFD_RELOC_X86_64_GOTPC64: | |
15671 | case BFD_RELOC_X86_64_GOTPLT64: | |
15672 | case BFD_RELOC_X86_64_PLTOFF64: | |
15673 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
15674 | _("cannot represent relocation type %s in x32 mode"), | |
15675 | bfd_get_reloc_code_name (code)); | |
15676 | break; | |
15677 | default: | |
15678 | break; | |
15679 | } | |
15680 | ||
062cd5e7 AS |
15681 | if (!fixp->fx_pcrel) |
15682 | rel->addend = fixp->fx_offset; | |
15683 | else | |
15684 | switch (code) | |
15685 | { | |
15686 | case BFD_RELOC_X86_64_PLT32: | |
15687 | case BFD_RELOC_X86_64_GOT32: | |
15688 | case BFD_RELOC_X86_64_GOTPCREL: | |
56ceb5b5 L |
15689 | case BFD_RELOC_X86_64_GOTPCRELX: |
15690 | case BFD_RELOC_X86_64_REX_GOTPCRELX: | |
bffbf940 JJ |
15691 | case BFD_RELOC_X86_64_TLSGD: |
15692 | case BFD_RELOC_X86_64_TLSLD: | |
15693 | case BFD_RELOC_X86_64_GOTTPOFF: | |
67a4f2b7 AO |
15694 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
15695 | case BFD_RELOC_X86_64_TLSDESC_CALL: | |
062cd5e7 AS |
15696 | rel->addend = fixp->fx_offset - fixp->fx_size; |
15697 | break; | |
15698 | default: | |
15699 | rel->addend = (section->vma | |
15700 | - fixp->fx_size | |
15701 | + fixp->fx_addnumber | |
15702 | + md_pcrel_from (fixp)); | |
15703 | break; | |
15704 | } | |
3e73aa7c JH |
15705 | } |
15706 | ||
252b5132 RH |
15707 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
15708 | if (rel->howto == NULL) | |
15709 | { | |
15710 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d0b47220 | 15711 | _("cannot represent relocation type %s"), |
252b5132 RH |
15712 | bfd_get_reloc_code_name (code)); |
15713 | /* Set howto to a garbage value so that we can keep going. */ | |
15714 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); | |
9c2799c2 | 15715 | gas_assert (rel->howto != NULL); |
252b5132 RH |
15716 | } |
15717 | ||
15718 | return rel; | |
15719 | } | |
15720 | ||
ee86248c | 15721 | #include "tc-i386-intel.c" |
54cfded0 | 15722 | |
a60de03c JB |
15723 | void |
15724 | tc_x86_parse_to_dw2regnum (expressionS *exp) | |
54cfded0 | 15725 | { |
a60de03c JB |
15726 | int saved_naked_reg; |
15727 | char saved_register_dot; | |
54cfded0 | 15728 | |
a60de03c JB |
15729 | saved_naked_reg = allow_naked_reg; |
15730 | allow_naked_reg = 1; | |
15731 | saved_register_dot = register_chars['.']; | |
15732 | register_chars['.'] = '.'; | |
15733 | allow_pseudo_reg = 1; | |
15734 | expression_and_evaluate (exp); | |
15735 | allow_pseudo_reg = 0; | |
15736 | register_chars['.'] = saved_register_dot; | |
15737 | allow_naked_reg = saved_naked_reg; | |
15738 | ||
e96d56a1 | 15739 | if (exp->X_op == O_register && exp->X_add_number >= 0) |
54cfded0 | 15740 | { |
a60de03c JB |
15741 | if ((addressT) exp->X_add_number < i386_regtab_size) |
15742 | { | |
15743 | exp->X_op = O_constant; | |
15744 | exp->X_add_number = i386_regtab[exp->X_add_number] | |
15745 | .dw2_regnum[flag_code >> 1]; | |
15746 | } | |
15747 | else | |
15748 | exp->X_op = O_illegal; | |
54cfded0 | 15749 | } |
54cfded0 AM |
15750 | } |
15751 | ||
15752 | void | |
15753 | tc_x86_frame_initial_instructions (void) | |
15754 | { | |
a60de03c JB |
15755 | static unsigned int sp_regno[2]; |
15756 | ||
15757 | if (!sp_regno[flag_code >> 1]) | |
15758 | { | |
15759 | char *saved_input = input_line_pointer; | |
15760 | char sp[][4] = {"esp", "rsp"}; | |
15761 | expressionS exp; | |
a4447b93 | 15762 | |
a60de03c JB |
15763 | input_line_pointer = sp[flag_code >> 1]; |
15764 | tc_x86_parse_to_dw2regnum (&exp); | |
9c2799c2 | 15765 | gas_assert (exp.X_op == O_constant); |
a60de03c JB |
15766 | sp_regno[flag_code >> 1] = exp.X_add_number; |
15767 | input_line_pointer = saved_input; | |
15768 | } | |
a4447b93 | 15769 | |
61ff971f L |
15770 | cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment); |
15771 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); | |
54cfded0 | 15772 | } |
d2b2c203 | 15773 | |
d7921315 L |
15774 | int |
15775 | x86_dwarf2_addr_size (void) | |
15776 | { | |
15777 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) | |
15778 | if (x86_elf_abi == X86_64_X32_ABI) | |
15779 | return 4; | |
15780 | #endif | |
15781 | return bfd_arch_bits_per_address (stdoutput) / 8; | |
15782 | } | |
15783 | ||
d2b2c203 DJ |
15784 | int |
15785 | i386_elf_section_type (const char *str, size_t len) | |
15786 | { | |
15787 | if (flag_code == CODE_64BIT | |
15788 | && len == sizeof ("unwind") - 1 | |
d34049e8 | 15789 | && startswith (str, "unwind")) |
d2b2c203 DJ |
15790 | return SHT_X86_64_UNWIND; |
15791 | ||
15792 | return -1; | |
15793 | } | |
bb41ade5 | 15794 | |
ad5fec3b EB |
15795 | #ifdef TE_SOLARIS |
15796 | void | |
15797 | i386_solaris_fix_up_eh_frame (segT sec) | |
15798 | { | |
15799 | if (flag_code == CODE_64BIT) | |
15800 | elf_section_type (sec) = SHT_X86_64_UNWIND; | |
15801 | } | |
15802 | #endif | |
15803 | ||
bb41ade5 AM |
15804 | #ifdef TE_PE |
15805 | void | |
15806 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
15807 | { | |
91d6fa6a | 15808 | expressionS exp; |
bb41ade5 | 15809 | |
91d6fa6a NC |
15810 | exp.X_op = O_secrel; |
15811 | exp.X_add_symbol = symbol; | |
15812 | exp.X_add_number = 0; | |
15813 | emit_expr (&exp, size); | |
bb41ade5 AM |
15814 | } |
15815 | #endif | |
3b22753a L |
15816 | |
15817 | #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) | |
15818 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ | |
15819 | ||
01e1a5bc | 15820 | bfd_vma |
6d4af3c2 | 15821 | x86_64_section_letter (int letter, const char **ptr_msg) |
3b22753a L |
15822 | { |
15823 | if (flag_code == CODE_64BIT) | |
15824 | { | |
15825 | if (letter == 'l') | |
15826 | return SHF_X86_64_LARGE; | |
15827 | ||
8f3bae45 | 15828 | *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string"); |
64e74474 | 15829 | } |
3b22753a | 15830 | else |
8f3bae45 | 15831 | *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string"); |
3b22753a L |
15832 | return -1; |
15833 | } | |
15834 | ||
3b22753a L |
15835 | static void |
15836 | handle_large_common (int small ATTRIBUTE_UNUSED) | |
15837 | { | |
15838 | if (flag_code != CODE_64BIT) | |
15839 | { | |
15840 | s_comm_internal (0, elf_common_parse); | |
15841 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")); | |
15842 | } | |
15843 | else | |
15844 | { | |
15845 | static segT lbss_section; | |
15846 | asection *saved_com_section_ptr = elf_com_section_ptr; | |
15847 | asection *saved_bss_section = bss_section; | |
15848 | ||
15849 | if (lbss_section == NULL) | |
15850 | { | |
15851 | flagword applicable; | |
15852 | segT seg = now_seg; | |
15853 | subsegT subseg = now_subseg; | |
15854 | ||
15855 | /* The .lbss section is for local .largecomm symbols. */ | |
15856 | lbss_section = subseg_new (".lbss", 0); | |
15857 | applicable = bfd_applicable_section_flags (stdoutput); | |
fd361982 | 15858 | bfd_set_section_flags (lbss_section, applicable & SEC_ALLOC); |
3b22753a L |
15859 | seg_info (lbss_section)->bss = 1; |
15860 | ||
15861 | subseg_set (seg, subseg); | |
15862 | } | |
15863 | ||
15864 | elf_com_section_ptr = &_bfd_elf_large_com_section; | |
15865 | bss_section = lbss_section; | |
15866 | ||
15867 | s_comm_internal (0, elf_common_parse); | |
15868 | ||
15869 | elf_com_section_ptr = saved_com_section_ptr; | |
15870 | bss_section = saved_bss_section; | |
15871 | } | |
15872 | } | |
15873 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |