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[thirdparty/binutils-gdb.git] / gas / config / tc-i386.c
CommitLineData
b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
5dd15031 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
e3bb37b5
L		 58static void set_code_flag (int);
59static void set_16bit_gcc_code_flag (int);
60static void set_intel_syntax (int);
1efbbeb4 61static void set_intel_mnemonic (int);
db51cc60 62static void set_allow_index_reg (int);
e3bb37b5 63static void set_cpu_arch (int);
6482c264 64#ifdef TE_PE
e3bb37b5 65static void pe_directive_secrel (int);
6482c264 66#endif
e3bb37b5
L		 67static void signed_cons (int);
68static char *output_invalid (int c);
a7619375 69static int i386_att_operand (char *);
e3bb37b5
L		 70static int i386_intel_operand (char *, int);
71static const reg_entry *parse_register (char *, char **);
72static char *parse_insn (char *, char *);
73static char *parse_operands (char *, const char *);
74static void swap_operands (void);
4d456e3d 75static void swap_2_operands (int, int);
e3bb37b5
L		 76static void optimize_imm (void);
77static void optimize_disp (void);
78static int match_template (void);
79static int check_string (void);
80static int process_suffix (void);
81static int check_byte_reg (void);
82static int check_long_reg (void);
83static int check_qword_reg (void);
84static int check_word_reg (void);
85static int finalize_imm (void);
85f10a01 86static void process_drex (void);
e3bb37b5
L		 87static int process_operands (void);
88static const seg_entry *build_modrm_byte (void);
89static void output_insn (void);
90static void output_imm (fragS *, offsetT);
91static void output_disp (fragS *, offsetT);
29b0f896 92#ifndef I386COFF
e3bb37b5 93static void s_bss (int);
252b5132 94#endif
17d4e2a2
L		 95#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
96static void handle_large_common (int small ATTRIBUTE_UNUSED);
97#endif
252b5132 98
a847613f 99static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 100
252b5132 101/* 'md_assemble ()' gathers together information and puts it into a
47926f60 102 i386_insn. */
252b5132 103
520dc8e8
AM		 104union i386_op
105 {
106 expressionS *disps;
107 expressionS *imms;
108 const reg_entry *regs;
109 };
110
252b5132
RH		 111struct _i386_insn
112 {
47926f60 113 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 114 template tm;
115
7d5e4556
L		 116 /* SUFFIX holds the instruction size suffix for byte, word, dword
117 or qword, if given. */
252b5132
RH		 118 char suffix;
119
47926f60 120 /* OPERANDS gives the number of given operands. */
252b5132
RH		 121 unsigned int operands;
122
123 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
124 of given register, displacement, memory operands and immediate
47926f60 125 operands. */
252b5132
RH		 126 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
127
128 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 129 use OP[i] for the corresponding operand. */
40fb9820 130 i386_operand_type types[MAX_OPERANDS];
252b5132 131
520dc8e8
AM		 132 /* Displacement expression, immediate expression, or register for each
133 operand. */
134 union i386_op op[MAX_OPERANDS];
252b5132 135
3e73aa7c
JH		 136 /* Flags for operands. */
137 unsigned int flags[MAX_OPERANDS];
138#define Operand_PCrel 1
139
252b5132 140 /* Relocation type for operand */
f86103b7 141 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 142
252b5132
RH		 143 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
144 the base index byte below. */
145 const reg_entry *base_reg;
146 const reg_entry *index_reg;
147 unsigned int log2_scale_factor;
148
149 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 150 explicit segment overrides are given. */
ce8a8b2f 151 const seg_entry *seg[2];
252b5132
RH		 152
153 /* PREFIX holds all the given prefix opcodes (usually null).
154 PREFIXES is the number of prefix opcodes. */
155 unsigned int prefixes;
156 unsigned char prefix[MAX_PREFIXES];
157
158 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 159 addressing modes of this insn are encoded. DREX is the byte
160 added by the SSE5 instructions. */
252b5132
RH		 161
162 modrm_byte rm;
3e73aa7c 163 rex_byte rex;
252b5132 164 sib_byte sib;
85f10a01 165 drex_byte drex;
252b5132
RH		 166 };
167
168typedef struct _i386_insn i386_insn;
169
170/* List of chars besides those in app.c:symbol_chars that can start an
171 operand. Used to prevent the scrubber eating vital white-space. */
32137342 172const char extra_symbol_chars[] = "*%-(["
252b5132 173#ifdef LEX_AT
32137342
NC		 174 "@"
175#endif
176#ifdef LEX_QM
177 "?"
252b5132 178#endif
32137342 179 ;
252b5132 180
29b0f896
AM		 181#if (defined (TE_I386AIX) \
182 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 183 && !defined (TE_GNU) \
29b0f896 184 && !defined (TE_LINUX) \
32137342 185 && !defined (TE_NETWARE) \
29b0f896
AM		 186 && !defined (TE_FreeBSD) \
187 && !defined (TE_NetBSD)))
252b5132 188/* This array holds the chars that always start a comment. If the
b3b91714
AM		 189 pre-processor is disabled, these aren't very useful. The option
190 --divide will remove '/' from this list. */
191const char *i386_comment_chars = "#/";
192#define SVR4_COMMENT_CHARS 1
252b5132 193#define PREFIX_SEPARATOR '\\'
252b5132 194
b3b91714
AM		 195#else
196const char *i386_comment_chars = "#";
197#define PREFIX_SEPARATOR '/'
198#endif
199
252b5132
RH		 200/* This array holds the chars that only start a comment at the beginning of
201 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 202 .line and .file directives will appear in the pre-processed output.
203 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 204 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 205 #NO_APP at the beginning of its output.
206 Also note that comments started like this one will always work if
252b5132 207 '/' isn't otherwise defined. */
b3b91714 208const char line_comment_chars[] = "#/";
252b5132 209
63a0b638 210const char line_separator_chars[] = ";";
252b5132 211
ce8a8b2f
AM		 212/* Chars that can be used to separate mant from exp in floating point
213 nums. */
252b5132
RH		 214const char EXP_CHARS[] = "eE";
215
ce8a8b2f
AM		 216/* Chars that mean this number is a floating point constant
217 As in 0f12.456
218 or 0d1.2345e12. */
252b5132
RH		 219const char FLT_CHARS[] = "fFdDxX";
220
ce8a8b2f 221/* Tables for lexical analysis. */
252b5132
RH		 222static char mnemonic_chars[256];
223static char register_chars[256];
224static char operand_chars[256];
225static char identifier_chars[256];
226static char digit_chars[256];
227
ce8a8b2f 228/* Lexical macros. */
252b5132
RH		 229#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
230#define is_operand_char(x) (operand_chars[(unsigned char) x])
231#define is_register_char(x) (register_chars[(unsigned char) x])
232#define is_space_char(x) ((x) == ' ')
233#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
234#define is_digit_char(x) (digit_chars[(unsigned char) x])
235
0234cb7c 236/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 237static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
238
239/* md_assemble() always leaves the strings it's passed unaltered. To
240 effect this we maintain a stack of saved characters that we've smashed
241 with '\0's (indicating end of strings for various sub-fields of the
47926f60 242 assembler instruction). */
252b5132 243static char save_stack[32];
ce8a8b2f 244static char *save_stack_p;
252b5132
RH		 245#define END_STRING_AND_SAVE(s) \
246 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
247#define RESTORE_END_STRING(s) \
248 do { *(s) = *--save_stack_p; } while (0)
249
47926f60 250/* The instruction we're assembling. */
252b5132
RH		 251static i386_insn i;
252
253/* Possible templates for current insn. */
254static const templates *current_templates;
255
31b2323c
L		 256/* Per instruction expressionS buffers: max displacements & immediates. */
257static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
258static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 259
47926f60
KH		 260/* Current operand we are working on. */
261static int this_operand;
252b5132 262
3e73aa7c
JH		 263/* We support four different modes. FLAG_CODE variable is used to distinguish
264 these. */
265
266enum flag_code {
267 CODE_32BIT,
268 CODE_16BIT,
269 CODE_64BIT };
270
271static enum flag_code flag_code;
4fa24527 272static unsigned int object_64bit;
3e73aa7c
JH		 273static int use_rela_relocations = 0;
274
275/* The names used to print error messages. */
b77a7acd 276static const char *flag_code_names[] =
3e73aa7c
JH		 277 {
278 "32",
279 "16",
280 "64"
281 };
252b5132 282
47926f60
KH		 283/* 1 for intel syntax,
284 0 if att syntax. */
285static int intel_syntax = 0;
252b5132 286
1efbbeb4
L		 287/* 1 for intel mnemonic,
288 0 if att mnemonic. */
289static int intel_mnemonic = !SYSV386_COMPAT;
290
5209009a 291/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 292static int old_gcc = OLDGCC_COMPAT;
293
47926f60
KH		 294/* 1 if register prefix % not required. */
295static int allow_naked_reg = 0;
252b5132 296
ba104c83 297/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 298static int allow_index_reg = 0;
299
2ca3ace5
L		 300/* Register prefix used for error message. */
301static const char *register_prefix = "%";
302
47926f60
KH		 303/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
304 leave, push, and pop instructions so that gcc has the same stack
305 frame as in 32 bit mode. */
306static char stackop_size = '\0';
eecb386c 307
12b55ccc
L		 308/* Non-zero to optimize code alignment. */
309int optimize_align_code = 1;
310
47926f60
KH		 311/* Non-zero to quieten some warnings. */
312static int quiet_warnings = 0;
a38cf1db 313
47926f60
KH		 314/* CPU name. */
315static const char *cpu_arch_name = NULL;
5c6af06e 316static const char *cpu_sub_arch_name = NULL;
a38cf1db 317
47926f60 318/* CPU feature flags. */
40fb9820
L		 319static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
320
ccc9c027
L		 321/* If we have selected a cpu we are generating instructions for. */
322static int cpu_arch_tune_set = 0;
323
9103f4f4
L		 324/* Cpu we are generating instructions for. */
325static enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
326
327/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 328static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 329
ccc9c027
L		 330/* CPU instruction set architecture used. */
331static enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
332
9103f4f4 333/* CPU feature flags of instruction set architecture used. */
40fb9820 334static i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 335
fddf5b5b
AM		 336/* If set, conditional jumps are not automatically promoted to handle
337 larger than a byte offset. */
338static unsigned int no_cond_jump_promotion = 0;
339
29b0f896 340/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 341static symbolS *GOT_symbol;
29b0f896 342
a4447b93
RH		 343/* The dwarf2 return column, adjusted for 32 or 64 bit. */
344unsigned int x86_dwarf2_return_column;
345
346/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
347int x86_cie_data_alignment;
348
252b5132 349/* Interface to relax_segment.
fddf5b5b
AM		 350 There are 3 major relax states for 386 jump insns because the
351 different types of jumps add different sizes to frags when we're
352 figuring out what sort of jump to choose to reach a given label. */
252b5132 353
47926f60 354/* Types. */
93c2a809
AM		 355#define UNCOND_JUMP 0
356#define COND_JUMP 1
357#define COND_JUMP86 2
fddf5b5b 358
47926f60 359/* Sizes. */
252b5132
RH		 360#define CODE16 1
361#define SMALL 0
29b0f896 362#define SMALL16 (SMALL | CODE16)
252b5132 363#define BIG 2
29b0f896 364#define BIG16 (BIG | CODE16)
252b5132
RH		 365
366#ifndef INLINE
367#ifdef __GNUC__
368#define INLINE __inline__
369#else
370#define INLINE
371#endif
372#endif
373
fddf5b5b
AM		 374#define ENCODE_RELAX_STATE(type, size) \
375 ((relax_substateT) (((type) << 2) | (size)))
376#define TYPE_FROM_RELAX_STATE(s) \
377 ((s) >> 2)
378#define DISP_SIZE_FROM_RELAX_STATE(s) \
379 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 380
381/* This table is used by relax_frag to promote short jumps to long
382 ones where necessary. SMALL (short) jumps may be promoted to BIG
383 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
384 don't allow a short jump in a 32 bit code segment to be promoted to
385 a 16 bit offset jump because it's slower (requires data size
386 prefix), and doesn't work, unless the destination is in the bottom
387 64k of the code segment (The top 16 bits of eip are zeroed). */
388
389const relax_typeS md_relax_table[] =
390{
24eab124
AM		 391 /* The fields are:
392 1) most positive reach of this state,
393 2) most negative reach of this state,
93c2a809 394 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 395 4) which index into the table to try if we can't fit into this one. */
252b5132 396
fddf5b5b 397 /* UNCOND_JUMP states. */
93c2a809
AM		 398 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
399 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
400 /* dword jmp adds 4 bytes to frag:
401 0 extra opcode bytes, 4 displacement bytes. */
252b5132 402 {0, 0, 4, 0},
93c2a809
AM		 403 /* word jmp adds 2 byte2 to frag:
404 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 405 {0, 0, 2, 0},
406
93c2a809
AM		 407 /* COND_JUMP states. */
408 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
409 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
410 /* dword conditionals adds 5 bytes to frag:
411 1 extra opcode byte, 4 displacement bytes. */
412 {0, 0, 5, 0},
fddf5b5b 413 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 414 1 extra opcode byte, 2 displacement bytes. */
415 {0, 0, 3, 0},
416
417 /* COND_JUMP86 states. */
418 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
419 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
420 /* dword conditionals adds 5 bytes to frag:
421 1 extra opcode byte, 4 displacement bytes. */
422 {0, 0, 5, 0},
423 /* word conditionals add 4 bytes to frag:
424 1 displacement byte and a 3 byte long branch insn. */
425 {0, 0, 4, 0}
252b5132
RH		 426};
427
9103f4f4
L		 428static const arch_entry cpu_arch[] =
429{
430 {"generic32", PROCESSOR_GENERIC32,
40fb9820 431 CPU_GENERIC32_FLAGS },
9103f4f4 432 {"generic64", PROCESSOR_GENERIC64,
40fb9820 433 CPU_GENERIC64_FLAGS },
9103f4f4 434 {"i8086", PROCESSOR_UNKNOWN,
40fb9820 435 CPU_NONE_FLAGS },
9103f4f4 436 {"i186", PROCESSOR_UNKNOWN,
40fb9820 437 CPU_I186_FLAGS },
9103f4f4 438 {"i286", PROCESSOR_UNKNOWN,
40fb9820 439 CPU_I286_FLAGS },
76bc74dc 440 {"i386", PROCESSOR_I386,
40fb9820 441 CPU_I386_FLAGS },
9103f4f4 442 {"i486", PROCESSOR_I486,
40fb9820 443 CPU_I486_FLAGS },
9103f4f4 444 {"i586", PROCESSOR_PENTIUM,
40fb9820 445 CPU_I586_FLAGS },
9103f4f4 446 {"i686", PROCESSOR_PENTIUMPRO,
40fb9820 447 CPU_I686_FLAGS },
9103f4f4 448 {"pentium", PROCESSOR_PENTIUM,
40fb9820 449 CPU_I586_FLAGS },
9103f4f4 450 {"pentiumpro",PROCESSOR_PENTIUMPRO,
40fb9820 451 CPU_I686_FLAGS },
9103f4f4 452 {"pentiumii", PROCESSOR_PENTIUMPRO,
40fb9820 453 CPU_P2_FLAGS },
9103f4f4 454 {"pentiumiii",PROCESSOR_PENTIUMPRO,
40fb9820 455 CPU_P3_FLAGS },
9103f4f4 456 {"pentium4", PROCESSOR_PENTIUM4,
40fb9820 457 CPU_P4_FLAGS },
9103f4f4 458 {"prescott", PROCESSOR_NOCONA,
40fb9820 459 CPU_CORE_FLAGS },
9103f4f4 460 {"nocona", PROCESSOR_NOCONA,
40fb9820 461 CPU_NOCONA_FLAGS },
ef05d495 462 {"yonah", PROCESSOR_CORE,
40fb9820 463 CPU_CORE_FLAGS },
ef05d495 464 {"core", PROCESSOR_CORE,
40fb9820 465 CPU_CORE_FLAGS },
ef05d495 466 {"merom", PROCESSOR_CORE2,
40fb9820 467 CPU_CORE2_FLAGS },
ef05d495 468 {"core2", PROCESSOR_CORE2,
40fb9820 469 CPU_CORE2_FLAGS },
9103f4f4 470 {"k6", PROCESSOR_K6,
40fb9820 471 CPU_K6_FLAGS },
9103f4f4 472 {"k6_2", PROCESSOR_K6,
40fb9820 473 CPU_K6_2_FLAGS },
9103f4f4 474 {"athlon", PROCESSOR_ATHLON,
40fb9820 475 CPU_ATHLON_FLAGS },
9103f4f4 476 {"sledgehammer", PROCESSOR_K8,
40fb9820 477 CPU_K8_FLAGS },
9103f4f4 478 {"opteron", PROCESSOR_K8,
40fb9820 479 CPU_K8_FLAGS },
9103f4f4 480 {"k8", PROCESSOR_K8,
40fb9820 481 CPU_K8_FLAGS },
050dfa73 482 {"amdfam10", PROCESSOR_AMDFAM10,
40fb9820 483 CPU_AMDFAM10_FLAGS },
9103f4f4 484 {".mmx", PROCESSOR_UNKNOWN,
40fb9820 485 CPU_MMX_FLAGS },
9103f4f4 486 {".sse", PROCESSOR_UNKNOWN,
40fb9820 487 CPU_SSE_FLAGS },
9103f4f4 488 {".sse2", PROCESSOR_UNKNOWN,
40fb9820 489 CPU_SSE2_FLAGS },
9103f4f4 490 {".sse3", PROCESSOR_UNKNOWN,
40fb9820 491 CPU_SSE3_FLAGS },
ef05d495 492 {".ssse3", PROCESSOR_UNKNOWN,
40fb9820 493 CPU_SSSE3_FLAGS },
42903f7f 494 {".sse4.1", PROCESSOR_UNKNOWN,
40fb9820 495 CPU_SSE4_1_FLAGS },
381d071f 496 {".sse4.2", PROCESSOR_UNKNOWN,
40fb9820 497 CPU_SSE4_2_FLAGS },
381d071f 498 {".sse4", PROCESSOR_UNKNOWN,
40fb9820 499 CPU_SSE4_2_FLAGS },
9103f4f4 500 {".3dnow", PROCESSOR_UNKNOWN,
40fb9820 501 CPU_3DNOW_FLAGS },
9103f4f4 502 {".3dnowa", PROCESSOR_UNKNOWN,
40fb9820 503 CPU_3DNOWA_FLAGS },
9103f4f4 504 {".padlock", PROCESSOR_UNKNOWN,
40fb9820 505 CPU_PADLOCK_FLAGS },
9103f4f4 506 {".pacifica", PROCESSOR_UNKNOWN,
40fb9820 507 CPU_SVME_FLAGS },
9103f4f4 508 {".svme", PROCESSOR_UNKNOWN,
40fb9820 509 CPU_SVME_FLAGS },
050dfa73 510 {".sse4a", PROCESSOR_UNKNOWN,
40fb9820 511 CPU_SSE4A_FLAGS },
050dfa73 512 {".abm", PROCESSOR_UNKNOWN,
40fb9820 513 CPU_ABM_FLAGS },
85f10a01
MM		 514 {".sse5", PROCESSOR_UNKNOWN,
515 CPU_SSE5_FLAGS },
e413e4e9
AM		 516};
517
29b0f896
AM		 518const pseudo_typeS md_pseudo_table[] =
519{
520#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
521 {"align", s_align_bytes, 0},
522#else
523 {"align", s_align_ptwo, 0},
524#endif
525 {"arch", set_cpu_arch, 0},
526#ifndef I386COFF
527 {"bss", s_bss, 0},
528#endif
529 {"ffloat", float_cons, 'f'},
530 {"dfloat", float_cons, 'd'},
531 {"tfloat", float_cons, 'x'},
532 {"value", cons, 2},
d182319b 533 {"slong", signed_cons, 4},
29b0f896
AM		 534 {"noopt", s_ignore, 0},
535 {"optim", s_ignore, 0},
536 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
537 {"code16", set_code_flag, CODE_16BIT},
538 {"code32", set_code_flag, CODE_32BIT},
539 {"code64", set_code_flag, CODE_64BIT},
540 {"intel_syntax", set_intel_syntax, 1},
541 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 542 {"intel_mnemonic", set_intel_mnemonic, 1},
543 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 544 {"allow_index_reg", set_allow_index_reg, 1},
545 {"disallow_index_reg", set_allow_index_reg, 0},
3b22753a
L		 546#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
547 {"largecomm", handle_large_common, 0},
07a53e5c 548#else
e3bb37b5 549 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 550 {"loc", dwarf2_directive_loc, 0},
551 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 552#endif
6482c264
NC		 553#ifdef TE_PE
554 {"secrel32", pe_directive_secrel, 0},
555#endif
29b0f896
AM		 556 {0, 0, 0}
557};
558
559/* For interface with expression (). */
560extern char *input_line_pointer;
561
562/* Hash table for instruction mnemonic lookup. */
563static struct hash_control *op_hash;
564
565/* Hash table for register lookup. */
566static struct hash_control *reg_hash;
567\f
252b5132 568void
e3bb37b5 569i386_align_code (fragS *fragP, int count)
252b5132 570{
ce8a8b2f
AM		 571 /* Various efficient no-op patterns for aligning code labels.
572 Note: Don't try to assemble the instructions in the comments.
573 0L and 0w are not legal. */
252b5132
RH		 574 static const char f32_1[] =
575 {0x90}; /* nop */
576 static const char f32_2[] =
ccc9c027 577 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 578 static const char f32_3[] =
579 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
580 static const char f32_4[] =
581 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
582 static const char f32_5[] =
583 {0x90, /* nop */
584 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
585 static const char f32_6[] =
586 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
587 static const char f32_7[] =
588 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
589 static const char f32_8[] =
590 {0x90, /* nop */
591 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
592 static const char f32_9[] =
593 {0x89,0xf6, /* movl %esi,%esi */
594 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
595 static const char f32_10[] =
596 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
597 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
598 static const char f32_11[] =
599 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
600 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
601 static const char f32_12[] =
602 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
603 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
604 static const char f32_13[] =
605 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
606 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
607 static const char f32_14[] =
608 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
609 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 610 static const char f16_3[] =
611 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 612 static const char f16_4[] =
613 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
614 static const char f16_5[] =
615 {0x90, /* nop */
616 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
617 static const char f16_6[] =
618 {0x89,0xf6, /* mov %si,%si */
619 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
620 static const char f16_7[] =
621 {0x8d,0x74,0x00, /* lea 0(%si),%si */
622 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
623 static const char f16_8[] =
624 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
625 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 626 static const char jump_31[] =
627 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
628 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
629 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
630 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 631 static const char *const f32_patt[] = {
632 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 633 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 634 };
635 static const char *const f16_patt[] = {
76bc74dc 636 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 637 };
ccc9c027
L		 638 /* nopl (%[re]ax) */
639 static const char alt_3[] =
640 {0x0f,0x1f,0x00};
641 /* nopl 0(%[re]ax) */
642 static const char alt_4[] =
643 {0x0f,0x1f,0x40,0x00};
644 /* nopl 0(%[re]ax,%[re]ax,1) */
645 static const char alt_5[] =
646 {0x0f,0x1f,0x44,0x00,0x00};
647 /* nopw 0(%[re]ax,%[re]ax,1) */
648 static const char alt_6[] =
649 {0x66,0x0f,0x1f,0x44,0x00,0x00};
650 /* nopl 0L(%[re]ax) */
651 static const char alt_7[] =
652 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
653 /* nopl 0L(%[re]ax,%[re]ax,1) */
654 static const char alt_8[] =
655 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
656 /* nopw 0L(%[re]ax,%[re]ax,1) */
657 static const char alt_9[] =
658 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
659 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
660 static const char alt_10[] =
661 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
662 /* data16
663 nopw %cs:0L(%[re]ax,%[re]ax,1) */
664 static const char alt_long_11[] =
665 {0x66,
666 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
667 /* data16
668 data16
669 nopw %cs:0L(%[re]ax,%[re]ax,1) */
670 static const char alt_long_12[] =
671 {0x66,
672 0x66,
673 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
674 /* data16
675 data16
676 data16
677 nopw %cs:0L(%[re]ax,%[re]ax,1) */
678 static const char alt_long_13[] =
679 {0x66,
680 0x66,
681 0x66,
682 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
683 /* data16
684 data16
685 data16
686 data16
687 nopw %cs:0L(%[re]ax,%[re]ax,1) */
688 static const char alt_long_14[] =
689 {0x66,
690 0x66,
691 0x66,
692 0x66,
693 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
694 /* data16
695 data16
696 data16
697 data16
698 data16
699 nopw %cs:0L(%[re]ax,%[re]ax,1) */
700 static const char alt_long_15[] =
701 {0x66,
702 0x66,
703 0x66,
704 0x66,
705 0x66,
706 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
707 /* nopl 0(%[re]ax,%[re]ax,1)
708 nopw 0(%[re]ax,%[re]ax,1) */
709 static const char alt_short_11[] =
710 {0x0f,0x1f,0x44,0x00,0x00,
711 0x66,0x0f,0x1f,0x44,0x00,0x00};
712 /* nopw 0(%[re]ax,%[re]ax,1)
713 nopw 0(%[re]ax,%[re]ax,1) */
714 static const char alt_short_12[] =
715 {0x66,0x0f,0x1f,0x44,0x00,0x00,
716 0x66,0x0f,0x1f,0x44,0x00,0x00};
717 /* nopw 0(%[re]ax,%[re]ax,1)
718 nopl 0L(%[re]ax) */
719 static const char alt_short_13[] =
720 {0x66,0x0f,0x1f,0x44,0x00,0x00,
721 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
722 /* nopl 0L(%[re]ax)
723 nopl 0L(%[re]ax) */
724 static const char alt_short_14[] =
725 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
726 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
727 /* nopl 0L(%[re]ax)
728 nopl 0L(%[re]ax,%[re]ax,1) */
729 static const char alt_short_15[] =
730 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
731 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
732 static const char *const alt_short_patt[] = {
733 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
734 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
735 alt_short_14, alt_short_15
736 };
737 static const char *const alt_long_patt[] = {
738 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
739 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
740 alt_long_14, alt_long_15
741 };
252b5132 742
76bc74dc
L		 743 /* Only align for at least a positive non-zero boundary. */
744 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 745 return;
3e73aa7c 746
ccc9c027
L		 747 /* We need to decide which NOP sequence to use for 32bit and
748 64bit. When -mtune= is used:
4eed87de 749
76bc74dc
L		 750 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
751 PROCESSOR_GENERIC32, f32_patt will be used.
752 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
753 PROCESSOR_CORE, PROCESSOR_CORE2, and PROCESSOR_GENERIC64,
754 alt_long_patt will be used.
755 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
756 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 757
76bc74dc
L		 758 When -mtune= isn't used, alt_long_patt will be used if
759 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
760 be used.
ccc9c027
L		 761
762 When -march= or .arch is used, we can't use anything beyond
763 cpu_arch_isa_flags. */
764
765 if (flag_code == CODE_16BIT)
766 {
ccc9c027 767 if (count > 8)
33fef721 768 {
76bc74dc
L		 769 memcpy (fragP->fr_literal + fragP->fr_fix,
770 jump_31, count);
771 /* Adjust jump offset. */
772 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 773 }
76bc74dc
L		 774 else
775 memcpy (fragP->fr_literal + fragP->fr_fix,
776 f16_patt[count - 1], count);
252b5132 777 }
33fef721 778 else
ccc9c027
L		 779 {
780 const char *const *patt = NULL;
781
782 if (cpu_arch_isa == PROCESSOR_UNKNOWN)
783 {
784 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
785 switch (cpu_arch_tune)
786 {
787 case PROCESSOR_UNKNOWN:
788 /* We use cpu_arch_isa_flags to check if we SHOULD
789 optimize for Cpu686. */
40fb9820 790 if (cpu_arch_isa_flags.bitfield.cpui686)
76bc74dc 791 patt = alt_long_patt;
ccc9c027
L		 792 else
793 patt = f32_patt;
794 break;
ccc9c027
L		 795 case PROCESSOR_PENTIUMPRO:
796 case PROCESSOR_PENTIUM4:
797 case PROCESSOR_NOCONA:
ef05d495 798 case PROCESSOR_CORE:
76bc74dc
L		 799 case PROCESSOR_CORE2:
800 case PROCESSOR_GENERIC64:
801 patt = alt_long_patt;
802 break;
ccc9c027
L		 803 case PROCESSOR_K6:
804 case PROCESSOR_ATHLON:
805 case PROCESSOR_K8:
4eed87de 806 case PROCESSOR_AMDFAM10:
ccc9c027
L		 807 patt = alt_short_patt;
808 break;
76bc74dc 809 case PROCESSOR_I386:
ccc9c027
L		 810 case PROCESSOR_I486:
811 case PROCESSOR_PENTIUM:
812 case PROCESSOR_GENERIC32:
813 patt = f32_patt;
814 break;
4eed87de 815 }
ccc9c027
L		 816 }
817 else
818 {
819 switch (cpu_arch_tune)
820 {
821 case PROCESSOR_UNKNOWN:
822 /* When cpu_arch_isa is net, cpu_arch_tune shouldn't be
823 PROCESSOR_UNKNOWN. */
824 abort ();
825 break;
826
76bc74dc 827 case PROCESSOR_I386:
ccc9c027
L		 828 case PROCESSOR_I486:
829 case PROCESSOR_PENTIUM:
ccc9c027
L		 830 case PROCESSOR_K6:
831 case PROCESSOR_ATHLON:
832 case PROCESSOR_K8:
4eed87de 833 case PROCESSOR_AMDFAM10:
ccc9c027
L		 834 case PROCESSOR_GENERIC32:
835 /* We use cpu_arch_isa_flags to check if we CAN optimize
836 for Cpu686. */
40fb9820 837 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 838 patt = alt_short_patt;
839 else
840 patt = f32_patt;
841 break;
76bc74dc
L		 842 case PROCESSOR_PENTIUMPRO:
843 case PROCESSOR_PENTIUM4:
844 case PROCESSOR_NOCONA:
845 case PROCESSOR_CORE:
ef05d495 846 case PROCESSOR_CORE2:
40fb9820 847 if (cpu_arch_isa_flags.bitfield.cpui686)
ccc9c027
L		 848 patt = alt_long_patt;
849 else
850 patt = f32_patt;
851 break;
852 case PROCESSOR_GENERIC64:
76bc74dc 853 patt = alt_long_patt;
ccc9c027 854 break;
4eed87de 855 }
ccc9c027
L		 856 }
857
76bc74dc
L		 858 if (patt == f32_patt)
859 {
860 /* If the padding is less than 15 bytes, we use the normal
861 ones. Otherwise, we use a jump instruction and adjust
862 its offset. */
863 if (count < 15)
864 memcpy (fragP->fr_literal + fragP->fr_fix,
865 patt[count - 1], count);
866 else
867 {
868 memcpy (fragP->fr_literal + fragP->fr_fix,
869 jump_31, count);
870 /* Adjust jump offset. */
871 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
872 }
873 }
874 else
875 {
876 /* Maximum length of an instruction is 15 byte. If the
877 padding is greater than 15 bytes and we don't use jump,
878 we have to break it into smaller pieces. */
879 int padding = count;
880 while (padding > 15)
881 {
882 padding -= 15;
883 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
884 patt [14], 15);
885 }
886
887 if (padding)
888 memcpy (fragP->fr_literal + fragP->fr_fix,
889 patt [padding - 1], padding);
890 }
ccc9c027 891 }
33fef721 892 fragP->fr_var = count;
252b5132
RH		 893}
894
c6fb90c8
L		 895static INLINE int
896uints_all_zero (const unsigned int *x, unsigned int size)
40fb9820 897{
c6fb90c8
L		 898 switch (size)
899 {
900 case 3:
901 if (x[2])
902 return 0;
903 case 2:
904 if (x[1])
905 return 0;
906 case 1:
907 return !x[0];
908 default:
909 abort ();
910 }
40fb9820
L		 911}
912
c6fb90c8
L		 913static INLINE void
914uints_set (unsigned int *x, unsigned int v, unsigned int size)
40fb9820 915{
c6fb90c8
L		 916 switch (size)
917 {
918 case 3:
919 x[2] = v;
920 case 2:
921 x[1] = v;
922 case 1:
923 x[0] = v;
924 break;
925 default:
926 abort ();
927 }
928}
40fb9820 929
c6fb90c8
L		 930static INLINE int
931uints_equal (const unsigned int *x, const unsigned int *y,
932 unsigned int size)
933{
934 switch (size)
935 {
936 case 3:
937 if (x[2] != y [2])
938 return 0;
939 case 2:
940 if (x[1] != y [1])
941 return 0;
942 case 1:
943 return x[0] == y [0];
944 break;
945 default:
946 abort ();
947 }
948}
40fb9820 949
c6fb90c8
L		 950#define UINTS_ALL_ZERO(x) \
951 uints_all_zero ((x).array, ARRAY_SIZE ((x).array))
952#define UINTS_SET(x, v) \
953 uints_set ((x).array, v, ARRAY_SIZE ((x).array))
954#define UINTS_CLEAR(x) \
955 uints_set ((x).array, 0, ARRAY_SIZE ((x).array))
956#define UINTS_EQUAL(x, y) \
957 uints_equal ((x).array, (y).array, ARRAY_SIZE ((x).array))
958
959static INLINE int
960cpu_flags_check_cpu64 (i386_cpu_flags f)
961{
962 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
963 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 964}
965
c6fb90c8
L		 966static INLINE i386_cpu_flags
967cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 968{
c6fb90c8
L		 969 switch (ARRAY_SIZE (x.array))
970 {
971 case 3:
972 x.array [2] &= y.array [2];
973 case 2:
974 x.array [1] &= y.array [1];
975 case 1:
976 x.array [0] &= y.array [0];
977 break;
978 default:
979 abort ();
980 }
981 return x;
982}
40fb9820 983
c6fb90c8
L		 984static INLINE i386_cpu_flags
985cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 986{
c6fb90c8 987 switch (ARRAY_SIZE (x.array))
40fb9820 988 {
c6fb90c8
L		 989 case 3:
990 x.array [2] |= y.array [2];
991 case 2:
992 x.array [1] |= y.array [1];
993 case 1:
994 x.array [0] |= y.array [0];
40fb9820
L		 995 break;
996 default:
997 abort ();
998 }
40fb9820
L		 999 return x;
1000}
1001
3629bb00
L		 1002/* Return 3 if there is a perfect match, 2 if compatible with 64bit,
1003 1 if compatible with arch, 0 if there is no match. */
1004
40fb9820
L		 1005static int
1006cpu_flags_match (i386_cpu_flags x)
1007{
3629bb00 1008 int overlap = cpu_flags_check_cpu64 (x) ? 2 : 0;
40fb9820
L		 1009
1010 x.bitfield.cpu64 = 0;
1011 x.bitfield.cpuno64 = 0;
1012
3629bb00
L		 1013 if (UINTS_ALL_ZERO (x))
1014 overlap |= 1;
1015 else
1016 {
1017 i386_cpu_flags cpu = cpu_arch_flags;
1018
1019 cpu.bitfield.cpu64 = 0;
1020 cpu.bitfield.cpuno64 = 0;
1021 cpu = cpu_flags_and (x, cpu);
1022 overlap |= UINTS_ALL_ZERO (cpu) ? 0 : 1;
1023 }
1024 return overlap;
40fb9820
L		 1025}
1026
c6fb90c8
L		 1027static INLINE i386_operand_type
1028operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1029{
c6fb90c8
L		 1030 switch (ARRAY_SIZE (x.array))
1031 {
1032 case 3:
1033 x.array [2] &= y.array [2];
1034 case 2:
1035 x.array [1] &= y.array [1];
1036 case 1:
1037 x.array [0] &= y.array [0];
1038 break;
1039 default:
1040 abort ();
1041 }
1042 return x;
40fb9820
L		 1043}
1044
c6fb90c8
L		 1045static INLINE i386_operand_type
1046operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1047{
c6fb90c8 1048 switch (ARRAY_SIZE (x.array))
40fb9820 1049 {
c6fb90c8
L		 1050 case 3:
1051 x.array [2] |= y.array [2];
1052 case 2:
1053 x.array [1] |= y.array [1];
1054 case 1:
1055 x.array [0] |= y.array [0];
40fb9820
L		 1056 break;
1057 default:
1058 abort ();
1059 }
c6fb90c8
L		 1060 return x;
1061}
40fb9820 1062
c6fb90c8
L		 1063static INLINE i386_operand_type
1064operand_type_xor (i386_operand_type x, i386_operand_type y)
1065{
1066 switch (ARRAY_SIZE (x.array))
1067 {
1068 case 3:
1069 x.array [2] ^= y.array [2];
1070 case 2:
1071 x.array [1] ^= y.array [1];
1072 case 1:
1073 x.array [0] ^= y.array [0];
1074 break;
1075 default:
1076 abort ();
1077 }
40fb9820
L		 1078 return x;
1079}
1080
1081static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1082static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1083static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1084static const i386_operand_type reg16_inoutportreg
1085 = OPERAND_TYPE_REG16_INOUTPORTREG;
1086static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1087static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1088static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1089static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1090static const i386_operand_type anydisp
1091 = OPERAND_TYPE_ANYDISP;
40fb9820
L		 1092static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1093static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1094static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1095static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1096static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1097static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1098static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1099static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1100static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1101static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1102
1103enum operand_type
1104{
1105 reg,
40fb9820
L		 1106 imm,
1107 disp,
1108 anymem
1109};
1110
c6fb90c8 1111static INLINE int
40fb9820
L		 1112operand_type_check (i386_operand_type t, enum operand_type c)
1113{
1114 switch (c)
1115 {
1116 case reg:
1117 return (t.bitfield.reg8
1118 || t.bitfield.reg16
1119 || t.bitfield.reg32
1120 || t.bitfield.reg64);
1121
40fb9820
L		 1122 case imm:
1123 return (t.bitfield.imm8
1124 || t.bitfield.imm8s
1125 || t.bitfield.imm16
1126 || t.bitfield.imm32
1127 || t.bitfield.imm32s
1128 || t.bitfield.imm64);
1129
1130 case disp:
1131 return (t.bitfield.disp8
1132 || t.bitfield.disp16
1133 || t.bitfield.disp32
1134 || t.bitfield.disp32s
1135 || t.bitfield.disp64);
1136
1137 case anymem:
1138 return (t.bitfield.disp8
1139 || t.bitfield.disp16
1140 || t.bitfield.disp32
1141 || t.bitfield.disp32s
1142 || t.bitfield.disp64
1143 || t.bitfield.baseindex);
1144
1145 default:
1146 abort ();
1147 }
1148}
1149
5c07affc
L		 1150/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1151 operand J for instruction template T. */
1152
1153static INLINE int
1154match_reg_size (const template *t, unsigned int j)
1155{
1156 return !((i.types[j].bitfield.byte
1157 && !t->operand_types[j].bitfield.byte)
1158 || (i.types[j].bitfield.word
1159 && !t->operand_types[j].bitfield.word)
1160 || (i.types[j].bitfield.dword
1161 && !t->operand_types[j].bitfield.dword)
1162 || (i.types[j].bitfield.qword
1163 && !t->operand_types[j].bitfield.qword));
1164}
1165
1166/* Return 1 if there is no conflict in any size on operand J for
1167 instruction template T. */
1168
1169static INLINE int
1170match_mem_size (const template *t, unsigned int j)
1171{
1172 return (match_reg_size (t, j)
1173 && !((i.types[j].bitfield.unspecified
1174 && !t->operand_types[j].bitfield.unspecified)
1175 || (i.types[j].bitfield.fword
1176 && !t->operand_types[j].bitfield.fword)
1177 || (i.types[j].bitfield.tbyte
1178 && !t->operand_types[j].bitfield.tbyte)
1179 || (i.types[j].bitfield.xmmword
1180 && !t->operand_types[j].bitfield.xmmword)));
1181}
1182
1183/* Return 1 if there is no size conflict on any operands for
1184 instruction template T. */
1185
1186static INLINE int
1187operand_size_match (const template *t)
1188{
1189 unsigned int j;
1190 int match = 1;
1191
1192 /* Don't check jump instructions. */
1193 if (t->opcode_modifier.jump
1194 || t->opcode_modifier.jumpbyte
1195 || t->opcode_modifier.jumpdword
1196 || t->opcode_modifier.jumpintersegment)
1197 return match;
1198
1199 /* Check memory and accumulator operand size. */
1200 for (j = 0; j < i.operands; j++)
1201 {
1202 if (t->operand_types[j].bitfield.anysize)
1203 continue;
1204
1205 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1206 {
1207 match = 0;
1208 break;
1209 }
1210
1211 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1212 {
1213 match = 0;
1214 break;
1215 }
1216 }
1217
1218 if (match
1219 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1220 return match;
1221
1222 /* Check reverse. */
1223 assert (i.operands == 2);
1224
1225 match = 1;
1226 for (j = 0; j < 2; j++)
1227 {
1228 if (t->operand_types[j].bitfield.acc
1229 && !match_reg_size (t, j ? 0 : 1))
1230 {
1231 match = 0;
1232 break;
1233 }
1234
1235 if (i.types[j].bitfield.mem
1236 && !match_mem_size (t, j ? 0 : 1))
1237 {
1238 match = 0;
1239 break;
1240 }
1241 }
1242
1243 return match;
1244}
1245
c6fb90c8 1246static INLINE int
40fb9820
L		 1247operand_type_match (i386_operand_type overlap,
1248 i386_operand_type given)
1249{
1250 i386_operand_type temp = overlap;
1251
1252 temp.bitfield.jumpabsolute = 0;
7d5e4556 1253 temp.bitfield.unspecified = 0;
5c07affc
L		 1254 temp.bitfield.byte = 0;
1255 temp.bitfield.word = 0;
1256 temp.bitfield.dword = 0;
1257 temp.bitfield.fword = 0;
1258 temp.bitfield.qword = 0;
1259 temp.bitfield.tbyte = 0;
1260 temp.bitfield.xmmword = 0;
c6fb90c8 1261 if (UINTS_ALL_ZERO (temp))
40fb9820
L		 1262 return 0;
1263
1264 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1265 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1266}
1267
7d5e4556 1268/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1269 unless the expected operand type register overlap is null.
1270 Note that Acc in a template matches every size of reg. */
1271
c6fb90c8 1272static INLINE int
40fb9820
L		 1273operand_type_register_match (i386_operand_type m0,
1274 i386_operand_type g0,
1275 i386_operand_type t0,
1276 i386_operand_type m1,
1277 i386_operand_type g1,
1278 i386_operand_type t1)
1279{
1280 if (!operand_type_check (g0, reg))
1281 return 1;
1282
1283 if (!operand_type_check (g1, reg))
1284 return 1;
1285
1286 if (g0.bitfield.reg8 == g1.bitfield.reg8
1287 && g0.bitfield.reg16 == g1.bitfield.reg16
1288 && g0.bitfield.reg32 == g1.bitfield.reg32
1289 && g0.bitfield.reg64 == g1.bitfield.reg64)
1290 return 1;
1291
1292 if (m0.bitfield.acc)
1293 {
1294 t0.bitfield.reg8 = 1;
1295 t0.bitfield.reg16 = 1;
1296 t0.bitfield.reg32 = 1;
1297 t0.bitfield.reg64 = 1;
1298 }
1299
1300 if (m1.bitfield.acc)
1301 {
1302 t1.bitfield.reg8 = 1;
1303 t1.bitfield.reg16 = 1;
1304 t1.bitfield.reg32 = 1;
1305 t1.bitfield.reg64 = 1;
1306 }
1307
1308 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1309 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1310 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1311 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1312}
1313
252b5132 1314static INLINE unsigned int
40fb9820 1315mode_from_disp_size (i386_operand_type t)
252b5132 1316{
40fb9820
L		 1317 if (t.bitfield.disp8)
1318 return 1;
1319 else if (t.bitfield.disp16
1320 || t.bitfield.disp32
1321 || t.bitfield.disp32s)
1322 return 2;
1323 else
1324 return 0;
252b5132
RH		 1325}
1326
1327static INLINE int
e3bb37b5 1328fits_in_signed_byte (offsetT num)
252b5132
RH		 1329{
1330 return (num >= -128) && (num <= 127);
47926f60 1331}
252b5132
RH		 1332
1333static INLINE int
e3bb37b5 1334fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1335{
1336 return (num & 0xff) == num;
47926f60 1337}
252b5132
RH		 1338
1339static INLINE int
e3bb37b5 1340fits_in_unsigned_word (offsetT num)
252b5132
RH		 1341{
1342 return (num & 0xffff) == num;
47926f60 1343}
252b5132
RH		 1344
1345static INLINE int
e3bb37b5 1346fits_in_signed_word (offsetT num)
252b5132
RH		 1347{
1348 return (-32768 <= num) && (num <= 32767);
47926f60 1349}
2a962e6d 1350
3e73aa7c 1351static INLINE int
e3bb37b5 1352fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1353{
1354#ifndef BFD64
1355 return 1;
1356#else
1357 return (!(((offsetT) -1 << 31) & num)
1358 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1359#endif
1360} /* fits_in_signed_long() */
2a962e6d 1361
3e73aa7c 1362static INLINE int
e3bb37b5 1363fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1364{
1365#ifndef BFD64
1366 return 1;
1367#else
1368 return (num & (((offsetT) 2 << 31) - 1)) == num;
1369#endif
1370} /* fits_in_unsigned_long() */
252b5132 1371
40fb9820 1372static i386_operand_type
e3bb37b5 1373smallest_imm_type (offsetT num)
252b5132 1374{
40fb9820
L		 1375 i386_operand_type t;
1376
c6fb90c8 1377 UINTS_CLEAR (t);
40fb9820
L		 1378 t.bitfield.imm64 = 1;
1379
1380 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1381 {
1382 /* This code is disabled on the 486 because all the Imm1 forms
1383 in the opcode table are slower on the i486. They're the
1384 versions with the implicitly specified single-position
1385 displacement, which has another syntax if you really want to
1386 use that form. */
40fb9820
L		 1387 t.bitfield.imm1 = 1;
1388 t.bitfield.imm8 = 1;
1389 t.bitfield.imm8s = 1;
1390 t.bitfield.imm16 = 1;
1391 t.bitfield.imm32 = 1;
1392 t.bitfield.imm32s = 1;
1393 }
1394 else if (fits_in_signed_byte (num))
1395 {
1396 t.bitfield.imm8 = 1;
1397 t.bitfield.imm8s = 1;
1398 t.bitfield.imm16 = 1;
1399 t.bitfield.imm32 = 1;
1400 t.bitfield.imm32s = 1;
1401 }
1402 else if (fits_in_unsigned_byte (num))
1403 {
1404 t.bitfield.imm8 = 1;
1405 t.bitfield.imm16 = 1;
1406 t.bitfield.imm32 = 1;
1407 t.bitfield.imm32s = 1;
1408 }
1409 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1410 {
1411 t.bitfield.imm16 = 1;
1412 t.bitfield.imm32 = 1;
1413 t.bitfield.imm32s = 1;
1414 }
1415 else if (fits_in_signed_long (num))
1416 {
1417 t.bitfield.imm32 = 1;
1418 t.bitfield.imm32s = 1;
1419 }
1420 else if (fits_in_unsigned_long (num))
1421 t.bitfield.imm32 = 1;
1422
1423 return t;
47926f60 1424}
252b5132 1425
847f7ad4 1426static offsetT
e3bb37b5 1427offset_in_range (offsetT val, int size)
847f7ad4 1428{
508866be 1429 addressT mask;
ba2adb93 1430
847f7ad4
AM		 1431 switch (size)
1432 {
508866be
L		 1433 case 1: mask = ((addressT) 1 << 8) - 1; break;
1434 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1435 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1436#ifdef BFD64
1437 case 8: mask = ((addressT) 2 << 63) - 1; break;
1438#endif
47926f60 1439 default: abort ();
847f7ad4
AM		 1440 }
1441
ba2adb93 1442 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1443 if (!use_rela_relocations)
1444 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1445 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1446
47926f60 1447 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1448 {
1449 char buf1[40], buf2[40];
1450
1451 sprint_value (buf1, val);
1452 sprint_value (buf2, val & mask);
1453 as_warn (_("%s shortened to %s"), buf1, buf2);
1454 }
1455 return val & mask;
1456}
1457
252b5132
RH		 1458/* Returns 0 if attempting to add a prefix where one from the same
1459 class already exists, 1 if non rep/repne added, 2 if rep/repne
1460 added. */
1461static int
e3bb37b5 1462add_prefix (unsigned int prefix)
252b5132
RH		 1463{
1464 int ret = 1;
b1905489 1465 unsigned int q;
252b5132 1466
29b0f896
AM		 1467 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1468 && flag_code == CODE_64BIT)
b1905489 1469 {
161a04f6
L		 1470 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1471 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1472 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1473 ret = 0;
1474 q = REX_PREFIX;
1475 }
3e73aa7c 1476 else
b1905489
JB		 1477 {
1478 switch (prefix)
1479 {
1480 default:
1481 abort ();
1482
1483 case CS_PREFIX_OPCODE:
1484 case DS_PREFIX_OPCODE:
1485 case ES_PREFIX_OPCODE:
1486 case FS_PREFIX_OPCODE:
1487 case GS_PREFIX_OPCODE:
1488 case SS_PREFIX_OPCODE:
1489 q = SEG_PREFIX;
1490 break;
1491
1492 case REPNE_PREFIX_OPCODE:
1493 case REPE_PREFIX_OPCODE:
1494 ret = 2;
1495 /* fall thru */
1496 case LOCK_PREFIX_OPCODE:
1497 q = LOCKREP_PREFIX;
1498 break;
1499
1500 case FWAIT_OPCODE:
1501 q = WAIT_PREFIX;
1502 break;
1503
1504 case ADDR_PREFIX_OPCODE:
1505 q = ADDR_PREFIX;
1506 break;
1507
1508 case DATA_PREFIX_OPCODE:
1509 q = DATA_PREFIX;
1510 break;
1511 }
1512 if (i.prefix[q] != 0)
1513 ret = 0;
1514 }
252b5132 1515
b1905489 1516 if (ret)
252b5132 1517 {
b1905489
JB		 1518 if (!i.prefix[q])
1519 ++i.prefixes;
1520 i.prefix[q] |= prefix;
252b5132 1521 }
b1905489
JB		 1522 else
1523 as_bad (_("same type of prefix used twice"));
252b5132 1524
252b5132
RH		 1525 return ret;
1526}
1527
1528static void
e3bb37b5 1529set_code_flag (int value)
eecb386c 1530{
3e73aa7c 1531 flag_code = value;
40fb9820
L		 1532 if (flag_code == CODE_64BIT)
1533 {
1534 cpu_arch_flags.bitfield.cpu64 = 1;
1535 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1536 }
1537 else
1538 {
1539 cpu_arch_flags.bitfield.cpu64 = 0;
1540 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1541 }
1542 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1543 {
1544 as_bad (_("64bit mode not supported on this CPU."));
1545 }
40fb9820 1546 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1547 {
1548 as_bad (_("32bit mode not supported on this CPU."));
1549 }
eecb386c
AM		 1550 stackop_size = '\0';
1551}
1552
1553static void
e3bb37b5 1554set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1555{
3e73aa7c 1556 flag_code = new_code_flag;
40fb9820
L		 1557 if (flag_code != CODE_16BIT)
1558 abort ();
1559 cpu_arch_flags.bitfield.cpu64 = 0;
1560 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1561 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1562}
1563
1564static void
e3bb37b5 1565set_intel_syntax (int syntax_flag)
252b5132
RH		 1566{
1567 /* Find out if register prefixing is specified. */
1568 int ask_naked_reg = 0;
1569
1570 SKIP_WHITESPACE ();
29b0f896 1571 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1572 {
1573 char *string = input_line_pointer;
1574 int e = get_symbol_end ();
1575
47926f60 1576 if (strcmp (string, "prefix") == 0)
252b5132 1577 ask_naked_reg = 1;
47926f60 1578 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1579 ask_naked_reg = -1;
1580 else
d0b47220 1581 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1582 *input_line_pointer = e;
1583 }
1584 demand_empty_rest_of_line ();
c3332e24 1585
252b5132
RH		 1586 intel_syntax = syntax_flag;
1587
1588 if (ask_naked_reg == 0)
f86103b7
AM		 1589 allow_naked_reg = (intel_syntax
1590 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1591 else
1592 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1593
e4a3b5a4 1594 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1595 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1596 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1597}
1598
1efbbeb4
L		 1599static void
1600set_intel_mnemonic (int mnemonic_flag)
1601{
e1d4d893 1602 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1603}
1604
db51cc60
L		 1605static void
1606set_allow_index_reg (int flag)
1607{
1608 allow_index_reg = flag;
1609}
1610
e413e4e9 1611static void
e3bb37b5 1612set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1613{
47926f60 1614 SKIP_WHITESPACE ();
e413e4e9 1615
29b0f896 1616 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1617 {
1618 char *string = input_line_pointer;
1619 int e = get_symbol_end ();
9103f4f4 1620 unsigned int i;
40fb9820 1621 i386_cpu_flags flags;
e413e4e9 1622
9103f4f4 1623 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1624 {
1625 if (strcmp (string, cpu_arch[i].name) == 0)
1626 {
5c6af06e
JB		 1627 if (*string != '.')
1628 {
1629 cpu_arch_name = cpu_arch[i].name;
1630 cpu_sub_arch_name = NULL;
40fb9820
L		 1631 cpu_arch_flags = cpu_arch[i].flags;
1632 if (flag_code == CODE_64BIT)
1633 {
1634 cpu_arch_flags.bitfield.cpu64 = 1;
1635 cpu_arch_flags.bitfield.cpuno64 = 0;
1636 }
1637 else
1638 {
1639 cpu_arch_flags.bitfield.cpu64 = 0;
1640 cpu_arch_flags.bitfield.cpuno64 = 1;
1641 }
ccc9c027 1642 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1643 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1644 if (!cpu_arch_tune_set)
1645 {
1646 cpu_arch_tune = cpu_arch_isa;
1647 cpu_arch_tune_flags = cpu_arch_isa_flags;
1648 }
5c6af06e
JB		 1649 break;
1650 }
40fb9820 1651
c6fb90c8
L		 1652 flags = cpu_flags_or (cpu_arch_flags,
1653 cpu_arch[i].flags);
1654 if (!UINTS_EQUAL (flags, cpu_arch_flags))
5c6af06e
JB		 1655 {
1656 cpu_sub_arch_name = cpu_arch[i].name;
40fb9820 1657 cpu_arch_flags = flags;
5c6af06e
JB		 1658 }
1659 *input_line_pointer = e;
1660 demand_empty_rest_of_line ();
1661 return;
e413e4e9
AM		 1662 }
1663 }
9103f4f4 1664 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 1665 as_bad (_("no such architecture: `%s'"), string);
1666
1667 *input_line_pointer = e;
1668 }
1669 else
1670 as_bad (_("missing cpu architecture"));
1671
fddf5b5b
AM		 1672 no_cond_jump_promotion = 0;
1673 if (*input_line_pointer == ','
29b0f896 1674 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 1675 {
1676 char *string = ++input_line_pointer;
1677 int e = get_symbol_end ();
1678
1679 if (strcmp (string, "nojumps") == 0)
1680 no_cond_jump_promotion = 1;
1681 else if (strcmp (string, "jumps") == 0)
1682 ;
1683 else
1684 as_bad (_("no such architecture modifier: `%s'"), string);
1685
1686 *input_line_pointer = e;
1687 }
1688
e413e4e9
AM		 1689 demand_empty_rest_of_line ();
1690}
1691
b9d79e03
JH		 1692unsigned long
1693i386_mach ()
1694{
1695 if (!strcmp (default_arch, "x86_64"))
1696 return bfd_mach_x86_64;
1697 else if (!strcmp (default_arch, "i386"))
1698 return bfd_mach_i386_i386;
1699 else
1700 as_fatal (_("Unknown architecture"));
1701}
b9d79e03 1702\f
252b5132
RH		 1703void
1704md_begin ()
1705{
1706 const char *hash_err;
1707
47926f60 1708 /* Initialize op_hash hash table. */
252b5132
RH		 1709 op_hash = hash_new ();
1710
1711 {
29b0f896
AM		 1712 const template *optab;
1713 templates *core_optab;
252b5132 1714
47926f60
KH		 1715 /* Setup for loop. */
1716 optab = i386_optab;
252b5132
RH		 1717 core_optab = (templates *) xmalloc (sizeof (templates));
1718 core_optab->start = optab;
1719
1720 while (1)
1721 {
1722 ++optab;
1723 if (optab->name == NULL
1724 || strcmp (optab->name, (optab - 1)->name) != 0)
1725 {
1726 /* different name --> ship out current template list;
47926f60 1727 add to hash table; & begin anew. */
252b5132
RH		 1728 core_optab->end = optab;
1729 hash_err = hash_insert (op_hash,
1730 (optab - 1)->name,
1731 (PTR) core_optab);
1732 if (hash_err)
1733 {
252b5132
RH		 1734 as_fatal (_("Internal Error: Can't hash %s: %s"),
1735 (optab - 1)->name,
1736 hash_err);
1737 }
1738 if (optab->name == NULL)
1739 break;
1740 core_optab = (templates *) xmalloc (sizeof (templates));
1741 core_optab->start = optab;
1742 }
1743 }
1744 }
1745
47926f60 1746 /* Initialize reg_hash hash table. */
252b5132
RH		 1747 reg_hash = hash_new ();
1748 {
29b0f896 1749 const reg_entry *regtab;
c3fe08fa 1750 unsigned int regtab_size = i386_regtab_size;
252b5132 1751
c3fe08fa 1752 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132
RH		 1753 {
1754 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
1755 if (hash_err)
3e73aa7c
JH		 1756 as_fatal (_("Internal Error: Can't hash %s: %s"),
1757 regtab->reg_name,
1758 hash_err);
252b5132
RH		 1759 }
1760 }
1761
47926f60 1762 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 1763 {
29b0f896
AM		 1764 int c;
1765 char *p;
252b5132
RH		 1766
1767 for (c = 0; c < 256; c++)
1768 {
3882b010 1769 if (ISDIGIT (c))
252b5132
RH		 1770 {
1771 digit_chars[c] = c;
1772 mnemonic_chars[c] = c;
1773 register_chars[c] = c;
1774 operand_chars[c] = c;
1775 }
3882b010 1776 else if (ISLOWER (c))
252b5132
RH		 1777 {
1778 mnemonic_chars[c] = c;
1779 register_chars[c] = c;
1780 operand_chars[c] = c;
1781 }
3882b010 1782 else if (ISUPPER (c))
252b5132 1783 {
3882b010 1784 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 1785 register_chars[c] = mnemonic_chars[c];
1786 operand_chars[c] = c;
1787 }
1788
3882b010 1789 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 1790 identifier_chars[c] = c;
1791 else if (c >= 128)
1792 {
1793 identifier_chars[c] = c;
1794 operand_chars[c] = c;
1795 }
1796 }
1797
1798#ifdef LEX_AT
1799 identifier_chars['@'] = '@';
32137342
NC		 1800#endif
1801#ifdef LEX_QM
1802 identifier_chars['?'] = '?';
1803 operand_chars['?'] = '?';
252b5132 1804#endif
252b5132 1805 digit_chars['-'] = '-';
791fe849 1806 mnemonic_chars['-'] = '-';
0003779b 1807 mnemonic_chars['.'] = '.';
252b5132
RH		 1808 identifier_chars['_'] = '_';
1809 identifier_chars['.'] = '.';
1810
1811 for (p = operand_special_chars; *p != '\0'; p++)
1812 operand_chars[(unsigned char) *p] = *p;
1813 }
1814
1815#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 1816 if (IS_ELF)
252b5132
RH		 1817 {
1818 record_alignment (text_section, 2);
1819 record_alignment (data_section, 2);
1820 record_alignment (bss_section, 2);
1821 }
1822#endif
a4447b93
RH		 1823
1824 if (flag_code == CODE_64BIT)
1825 {
1826 x86_dwarf2_return_column = 16;
1827 x86_cie_data_alignment = -8;
1828 }
1829 else
1830 {
1831 x86_dwarf2_return_column = 8;
1832 x86_cie_data_alignment = -4;
1833 }
252b5132
RH		 1834}
1835
1836void
e3bb37b5 1837i386_print_statistics (FILE *file)
252b5132
RH		 1838{
1839 hash_print_statistics (file, "i386 opcode", op_hash);
1840 hash_print_statistics (file, "i386 register", reg_hash);
1841}
1842\f
252b5132
RH		 1843#ifdef DEBUG386
1844
ce8a8b2f 1845/* Debugging routines for md_assemble. */
e3bb37b5 1846static void pte (template *);
40fb9820 1847static void pt (i386_operand_type);
e3bb37b5
L		 1848static void pe (expressionS *);
1849static void ps (symbolS *);
252b5132
RH		 1850
1851static void
e3bb37b5 1852pi (char *line, i386_insn *x)
252b5132 1853{
09f131f2 1854 unsigned int i;
252b5132
RH		 1855
1856 fprintf (stdout, "%s: template ", line);
1857 pte (&x->tm);
09f131f2
JH		 1858 fprintf (stdout, " address: base %s index %s scale %x\n",
1859 x->base_reg ? x->base_reg->reg_name : "none",
1860 x->index_reg ? x->index_reg->reg_name : "none",
1861 x->log2_scale_factor);
1862 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 1863 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 1864 fprintf (stdout, " sib: base %x index %x scale %x\n",
1865 x->sib.base, x->sib.index, x->sib.scale);
1866 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 1867 (x->rex & REX_W) != 0,
1868 (x->rex & REX_R) != 0,
1869 (x->rex & REX_X) != 0,
1870 (x->rex & REX_B) != 0);
85f10a01
MM		 1871 fprintf (stdout, " drex: reg %d rex 0x%x\n",
1872 x->drex.reg, x->drex.rex);
252b5132
RH		 1873 for (i = 0; i < x->operands; i++)
1874 {
1875 fprintf (stdout, " #%d: ", i + 1);
1876 pt (x->types[i]);
1877 fprintf (stdout, "\n");
40fb9820
L		 1878 if (x->types[i].bitfield.reg8
1879 || x->types[i].bitfield.reg16
1880 || x->types[i].bitfield.reg32
1881 || x->types[i].bitfield.reg64
1882 || x->types[i].bitfield.regmmx
1883 || x->types[i].bitfield.regxmm
1884 || x->types[i].bitfield.sreg2
1885 || x->types[i].bitfield.sreg3
1886 || x->types[i].bitfield.control
1887 || x->types[i].bitfield.debug
1888 || x->types[i].bitfield.test)
520dc8e8 1889 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 1890 if (operand_type_check (x->types[i], imm))
520dc8e8 1891 pe (x->op[i].imms);
40fb9820 1892 if (operand_type_check (x->types[i], disp))
520dc8e8 1893 pe (x->op[i].disps);
252b5132
RH		 1894 }
1895}
1896
1897static void
e3bb37b5 1898pte (template *t)
252b5132 1899{
09f131f2 1900 unsigned int i;
252b5132 1901 fprintf (stdout, " %d operands ", t->operands);
47926f60 1902 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 1903 if (t->extension_opcode != None)
1904 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 1905 if (t->opcode_modifier.d)
252b5132 1906 fprintf (stdout, "D");
40fb9820 1907 if (t->opcode_modifier.w)
252b5132
RH		 1908 fprintf (stdout, "W");
1909 fprintf (stdout, "\n");
1910 for (i = 0; i < t->operands; i++)
1911 {
1912 fprintf (stdout, " #%d type ", i + 1);
1913 pt (t->operand_types[i]);
1914 fprintf (stdout, "\n");
1915 }
1916}
1917
1918static void
e3bb37b5 1919pe (expressionS *e)
252b5132 1920{
24eab124 1921 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 1922 fprintf (stdout, " add_number %ld (%lx)\n",
1923 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 1924 if (e->X_add_symbol)
1925 {
1926 fprintf (stdout, " add_symbol ");
1927 ps (e->X_add_symbol);
1928 fprintf (stdout, "\n");
1929 }
1930 if (e->X_op_symbol)
1931 {
1932 fprintf (stdout, " op_symbol ");
1933 ps (e->X_op_symbol);
1934 fprintf (stdout, "\n");
1935 }
1936}
1937
1938static void
e3bb37b5 1939ps (symbolS *s)
252b5132
RH		 1940{
1941 fprintf (stdout, "%s type %s%s",
1942 S_GET_NAME (s),
1943 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1944 segment_name (S_GET_SEGMENT (s)));
1945}
1946
7b81dfbb 1947static struct type_name
252b5132 1948 {
40fb9820
L		 1949 i386_operand_type mask;
1950 const char *name;
252b5132 1951 }
7b81dfbb 1952const type_names[] =
252b5132 1953{
40fb9820
L		 1954 { OPERAND_TYPE_REG8, "r8" },
1955 { OPERAND_TYPE_REG16, "r16" },
1956 { OPERAND_TYPE_REG32, "r32" },
1957 { OPERAND_TYPE_REG64, "r64" },
1958 { OPERAND_TYPE_IMM8, "i8" },
1959 { OPERAND_TYPE_IMM8, "i8s" },
1960 { OPERAND_TYPE_IMM16, "i16" },
1961 { OPERAND_TYPE_IMM32, "i32" },
1962 { OPERAND_TYPE_IMM32S, "i32s" },
1963 { OPERAND_TYPE_IMM64, "i64" },
1964 { OPERAND_TYPE_IMM1, "i1" },
1965 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
1966 { OPERAND_TYPE_DISP8, "d8" },
1967 { OPERAND_TYPE_DISP16, "d16" },
1968 { OPERAND_TYPE_DISP32, "d32" },
1969 { OPERAND_TYPE_DISP32S, "d32s" },
1970 { OPERAND_TYPE_DISP64, "d64" },
1971 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
1972 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
1973 { OPERAND_TYPE_CONTROL, "control reg" },
1974 { OPERAND_TYPE_TEST, "test reg" },
1975 { OPERAND_TYPE_DEBUG, "debug reg" },
1976 { OPERAND_TYPE_FLOATREG, "FReg" },
1977 { OPERAND_TYPE_FLOATACC, "FAcc" },
1978 { OPERAND_TYPE_SREG2, "SReg2" },
1979 { OPERAND_TYPE_SREG3, "SReg3" },
1980 { OPERAND_TYPE_ACC, "Acc" },
1981 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
1982 { OPERAND_TYPE_REGMMX, "rMMX" },
1983 { OPERAND_TYPE_REGXMM, "rXMM" },
1984 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 1985};
1986
1987static void
40fb9820 1988pt (i386_operand_type t)
252b5132 1989{
40fb9820 1990 unsigned int j;
c6fb90c8 1991 i386_operand_type a;
252b5132 1992
40fb9820 1993 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 1994 {
1995 a = operand_type_and (t, type_names[j].mask);
1996 if (!UINTS_ALL_ZERO (a))
1997 fprintf (stdout, "%s, ", type_names[j].name);
1998 }
252b5132
RH		 1999 fflush (stdout);
2000}
2001
2002#endif /* DEBUG386 */
2003\f
252b5132 2004static bfd_reloc_code_real_type
3956db08 2005reloc (unsigned int size,
64e74474
AM		 2006 int pcrel,
2007 int sign,
2008 bfd_reloc_code_real_type other)
252b5132 2009{
47926f60 2010 if (other != NO_RELOC)
3956db08
JB		 2011 {
2012 reloc_howto_type *reloc;
2013
2014 if (size == 8)
2015 switch (other)
2016 {
64e74474
AM		 2017 case BFD_RELOC_X86_64_GOT32:
2018 return BFD_RELOC_X86_64_GOT64;
2019 break;
2020 case BFD_RELOC_X86_64_PLTOFF64:
2021 return BFD_RELOC_X86_64_PLTOFF64;
2022 break;
2023 case BFD_RELOC_X86_64_GOTPC32:
2024 other = BFD_RELOC_X86_64_GOTPC64;
2025 break;
2026 case BFD_RELOC_X86_64_GOTPCREL:
2027 other = BFD_RELOC_X86_64_GOTPCREL64;
2028 break;
2029 case BFD_RELOC_X86_64_TPOFF32:
2030 other = BFD_RELOC_X86_64_TPOFF64;
2031 break;
2032 case BFD_RELOC_X86_64_DTPOFF32:
2033 other = BFD_RELOC_X86_64_DTPOFF64;
2034 break;
2035 default:
2036 break;
3956db08 2037 }
e05278af
JB		 2038
2039 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2040 if (size == 4 && flag_code != CODE_64BIT)
2041 sign = -1;
2042
3956db08
JB		 2043 reloc = bfd_reloc_type_lookup (stdoutput, other);
2044 if (!reloc)
2045 as_bad (_("unknown relocation (%u)"), other);
2046 else if (size != bfd_get_reloc_size (reloc))
2047 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2048 bfd_get_reloc_size (reloc),
2049 size);
2050 else if (pcrel && !reloc->pc_relative)
2051 as_bad (_("non-pc-relative relocation for pc-relative field"));
2052 else if ((reloc->complain_on_overflow == complain_overflow_signed
2053 && !sign)
2054 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2055 && sign > 0))
3956db08
JB		 2056 as_bad (_("relocated field and relocation type differ in signedness"));
2057 else
2058 return other;
2059 return NO_RELOC;
2060 }
252b5132
RH		 2061
2062 if (pcrel)
2063 {
3e73aa7c 2064 if (!sign)
3956db08 2065 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2066 switch (size)
2067 {
2068 case 1: return BFD_RELOC_8_PCREL;
2069 case 2: return BFD_RELOC_16_PCREL;
2070 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2071 case 8: return BFD_RELOC_64_PCREL;
252b5132 2072 }
3956db08 2073 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2074 }
2075 else
2076 {
3956db08 2077 if (sign > 0)
e5cb08ac 2078 switch (size)
3e73aa7c
JH		 2079 {
2080 case 4: return BFD_RELOC_X86_64_32S;
2081 }
2082 else
2083 switch (size)
2084 {
2085 case 1: return BFD_RELOC_8;
2086 case 2: return BFD_RELOC_16;
2087 case 4: return BFD_RELOC_32;
2088 case 8: return BFD_RELOC_64;
2089 }
3956db08
JB		 2090 as_bad (_("cannot do %s %u byte relocation"),
2091 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2092 }
2093
bfb32b52 2094 abort ();
252b5132
RH		 2095 return BFD_RELOC_NONE;
2096}
2097
47926f60
KH		 2098/* Here we decide which fixups can be adjusted to make them relative to
2099 the beginning of the section instead of the symbol. Basically we need
2100 to make sure that the dynamic relocations are done correctly, so in
2101 some cases we force the original symbol to be used. */
2102
252b5132 2103int
e3bb37b5 2104tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2105{
6d249963 2106#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2107 if (!IS_ELF)
31312f95
AM		 2108 return 1;
2109
a161fe53
AM		 2110 /* Don't adjust pc-relative references to merge sections in 64-bit
2111 mode. */
2112 if (use_rela_relocations
2113 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2114 && fixP->fx_pcrel)
252b5132 2115 return 0;
31312f95 2116
8d01d9a9
AJ		 2117 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2118 and changed later by validate_fix. */
2119 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2120 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2121 return 0;
2122
ce8a8b2f 2123 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2124 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2125 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2126 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2127 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2128 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2129 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2130 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2131 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2132 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2133 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2134 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2135 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2136 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2137 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2138 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2139 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2140 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2141 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2142 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2143 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2144 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2145 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2146 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2147 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2148 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2149 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2150 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2151 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2152 return 0;
31312f95 2153#endif
252b5132
RH		 2154 return 1;
2155}
252b5132 2156
b4cac588 2157static int
e3bb37b5 2158intel_float_operand (const char *mnemonic)
252b5132 2159{
9306ca4a
JB		 2160 /* Note that the value returned is meaningful only for opcodes with (memory)
2161 operands, hence the code here is free to improperly handle opcodes that
2162 have no operands (for better performance and smaller code). */
2163
2164 if (mnemonic[0] != 'f')
2165 return 0; /* non-math */
2166
2167 switch (mnemonic[1])
2168 {
2169 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2170 the fs segment override prefix not currently handled because no
2171 call path can make opcodes without operands get here */
2172 case 'i':
2173 return 2 /* integer op */;
2174 case 'l':
2175 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2176 return 3; /* fldcw/fldenv */
2177 break;
2178 case 'n':
2179 if (mnemonic[2] != 'o' /* fnop */)
2180 return 3; /* non-waiting control op */
2181 break;
2182 case 'r':
2183 if (mnemonic[2] == 's')
2184 return 3; /* frstor/frstpm */
2185 break;
2186 case 's':
2187 if (mnemonic[2] == 'a')
2188 return 3; /* fsave */
2189 if (mnemonic[2] == 't')
2190 {
2191 switch (mnemonic[3])
2192 {
2193 case 'c': /* fstcw */
2194 case 'd': /* fstdw */
2195 case 'e': /* fstenv */
2196 case 's': /* fsts[gw] */
2197 return 3;
2198 }
2199 }
2200 break;
2201 case 'x':
2202 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2203 return 0; /* fxsave/fxrstor are not really math ops */
2204 break;
2205 }
252b5132 2206
9306ca4a 2207 return 1;
252b5132
RH		 2208}
2209
2210/* This is the guts of the machine-dependent assembler. LINE points to a
2211 machine dependent instruction. This function is supposed to emit
2212 the frags/bytes it assembles to. */
2213
2214void
2215md_assemble (line)
2216 char *line;
2217{
40fb9820 2218 unsigned int j;
252b5132
RH		 2219 char mnemonic[MAX_MNEM_SIZE];
2220
47926f60 2221 /* Initialize globals. */
252b5132
RH		 2222 memset (&i, '\0', sizeof (i));
2223 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2224 i.reloc[j] = NO_RELOC;
252b5132
RH		 2225 memset (disp_expressions, '\0', sizeof (disp_expressions));
2226 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2227 save_stack_p = save_stack;
252b5132
RH		 2228
2229 /* First parse an instruction mnemonic & call i386_operand for the operands.
2230 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2231 start of a (possibly prefixed) mnemonic. */
252b5132 2232
29b0f896
AM		 2233 line = parse_insn (line, mnemonic);
2234 if (line == NULL)
2235 return;
252b5132 2236
29b0f896
AM		 2237 line = parse_operands (line, mnemonic);
2238 if (line == NULL)
2239 return;
252b5132 2240
29b0f896
AM		 2241 /* Now we've parsed the mnemonic into a set of templates, and have the
2242 operands at hand. */
2243
2244 /* All intel opcodes have reversed operands except for "bound" and
2245 "enter". We also don't reverse intersegment "jmp" and "call"
2246 instructions with 2 immediate operands so that the immediate segment
050dfa73 2247 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2248 if (intel_syntax
2249 && i.operands > 1
29b0f896 2250 && (strcmp (mnemonic, "bound") != 0)
30123838 2251 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2252 && !(operand_type_check (i.types[0], imm)
2253 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2254 swap_operands ();
2255
ec56d5c0
JB		 2256 /* The order of the immediates should be reversed
2257 for 2 immediates extrq and insertq instructions */
2258 if (i.imm_operands == 2
2259 && (strcmp (mnemonic, "extrq") == 0
2260 || strcmp (mnemonic, "insertq") == 0))
2261 swap_2_operands (0, 1);
2262
29b0f896
AM		 2263 if (i.imm_operands)
2264 optimize_imm ();
2265
b300c311
L		 2266 /* Don't optimize displacement for movabs since it only takes 64bit
2267 displacement. */
2268 if (i.disp_operands
2269 && (flag_code != CODE_64BIT
2270 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2271 optimize_disp ();
2272
2273 /* Next, we find a template that matches the given insn,
2274 making sure the overlap of the given operands types is consistent
2275 with the template operand types. */
252b5132 2276
29b0f896
AM		 2277 if (!match_template ())
2278 return;
252b5132 2279
321fd21e
L		 2280 /* Zap movzx and movsx suffix. The suffix has been set from
2281 "word ptr" or "byte ptr" on the source operand in Intel syntax
2282 or extracted from mnemonic in AT&T syntax. But we'll use
2283 the destination register to choose the suffix for encoding. */
2284 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2285 {
321fd21e
L		 2286 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2287 there is no suffix, the default will be byte extension. */
2288 if (i.reg_operands != 2
2289 && !i.suffix
2290 && intel_syntax)
2291 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2292
2293 i.suffix = 0;
cd61ebfe 2294 }
24eab124 2295
40fb9820 2296 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2297 if (!add_prefix (FWAIT_OPCODE))
2298 return;
252b5132 2299
29b0f896 2300 /* Check string instruction segment overrides. */
40fb9820 2301 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2302 {
2303 if (!check_string ())
5dd0794d 2304 return;
29b0f896 2305 }
5dd0794d 2306
29b0f896
AM		 2307 if (!process_suffix ())
2308 return;
e413e4e9 2309
29b0f896
AM		 2310 /* Make still unresolved immediate matches conform to size of immediate
2311 given in i.suffix. */
2312 if (!finalize_imm ())
2313 return;
252b5132 2314
40fb9820 2315 if (i.types[0].bitfield.imm1)
29b0f896 2316 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2317
40fb9820 2318 for (j = 0; j < 3; j++)
c6fb90c8
L		 2319 if (i.types[j].bitfield.inoutportreg
2320 || i.types[j].bitfield.shiftcount
2321 || i.types[j].bitfield.acc
2322 || i.types[j].bitfield.floatacc)
40fb9820
L		 2323 i.reg_operands--;
2324
2325 if (i.tm.opcode_modifier.immext)
29b0f896 2326 {
02fc3089
L		 2327 expressionS *exp;
2328
40fb9820 2329 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
ca164297 2330 {
b7d9ef37 2331 /* Streaming SIMD extensions 3 Instructions have the fixed
ca164297
L		 2332 operands with an opcode suffix which is coded in the same
2333 place as an 8-bit immediate field would be. Here we check
2334 those operands and remove them afterwards. */
2335 unsigned int x;
2336
a4622f40 2337 for (x = 0; x < i.operands; x++)
ca164297 2338 if (i.op[x].regs->reg_num != x)
a540244d
L		 2339 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2340 register_prefix,
2341 i.op[x].regs->reg_name,
2342 x + 1,
2343 i.tm.name);
ca164297
L		 2344 i.operands = 0;
2345 }
2346
29b0f896
AM		 2347 /* These AMD 3DNow! and Intel Katmai New Instructions have an
2348 opcode suffix which is coded in the same place as an 8-bit
2349 immediate field would be. Here we fake an 8-bit immediate
85f10a01
MM		 2350 operand from the opcode suffix stored in tm.extension_opcode.
2351 SSE5 also uses this encoding, for some of its 3 argument
2352 instructions. */
252b5132 2353
85f10a01
MM		 2354 assert (i.imm_operands == 0
2355 && (i.operands <= 2
2356 || (i.tm.cpu_flags.bitfield.cpusse5
2357 && i.operands <= 3)));
252b5132 2358
29b0f896
AM		 2359 exp = &im_expressions[i.imm_operands++];
2360 i.op[i.operands].imms = exp;
c6fb90c8 2361 UINTS_CLEAR (i.types[i.operands]);
40fb9820
L		 2362 i.types[i.operands].bitfield.imm8 = 1;
2363 i.operands++;
29b0f896
AM		 2364 exp->X_op = O_constant;
2365 exp->X_add_number = i.tm.extension_opcode;
2366 i.tm.extension_opcode = None;
2367 }
252b5132 2368
29b0f896
AM		 2369 /* For insns with operands there are more diddles to do to the opcode. */
2370 if (i.operands)
2371 {
2372 if (!process_operands ())
2373 return;
2374 }
40fb9820 2375 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2376 {
2377 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2378 as_warn (_("translating to `%sp'"), i.tm.name);
2379 }
252b5132 2380
29b0f896
AM		 2381 /* Handle conversion of 'int $3' --> special int3 insn. */
2382 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2383 {
2384 i.tm.base_opcode = INT3_OPCODE;
2385 i.imm_operands = 0;
2386 }
252b5132 2387
40fb9820
L		 2388 if ((i.tm.opcode_modifier.jump
2389 || i.tm.opcode_modifier.jumpbyte
2390 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2391 && i.op[0].disps->X_op == O_constant)
2392 {
2393 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2394 the absolute address given by the constant. Since ix86 jumps and
2395 calls are pc relative, we need to generate a reloc. */
2396 i.op[0].disps->X_add_symbol = &abs_symbol;
2397 i.op[0].disps->X_op = O_symbol;
2398 }
252b5132 2399
40fb9820 2400 if (i.tm.opcode_modifier.rex64)
161a04f6 2401 i.rex |= REX_W;
252b5132 2402
29b0f896
AM		 2403 /* For 8 bit registers we need an empty rex prefix. Also if the
2404 instruction already has a prefix, we need to convert old
2405 registers to new ones. */
773f551c 2406
40fb9820 2407 if ((i.types[0].bitfield.reg8
29b0f896 2408 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2409 || (i.types[1].bitfield.reg8
29b0f896 2410 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2411 || ((i.types[0].bitfield.reg8
2412 || i.types[1].bitfield.reg8)
29b0f896
AM		 2413 && i.rex != 0))
2414 {
2415 int x;
726c5dcd 2416
29b0f896
AM		 2417 i.rex |= REX_OPCODE;
2418 for (x = 0; x < 2; x++)
2419 {
2420 /* Look for 8 bit operand that uses old registers. */
40fb9820 2421 if (i.types[x].bitfield.reg8
29b0f896 2422 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2423 {
29b0f896
AM		 2424 /* In case it is "hi" register, give up. */
2425 if (i.op[x].regs->reg_num > 3)
a540244d 2426 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2427 "instruction requiring REX prefix."),
a540244d 2428 register_prefix, i.op[x].regs->reg_name);
773f551c 2429
29b0f896
AM		 2430 /* Otherwise it is equivalent to the extended register.
2431 Since the encoding doesn't change this is merely
2432 cosmetic cleanup for debug output. */
2433
2434 i.op[x].regs = i.op[x].regs + 8;
773f551c 2435 }
29b0f896
AM		 2436 }
2437 }
773f551c 2438
85f10a01
MM		 2439 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2440 REX prefix. */
2441 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2442 {
2443 i.drex.rex = i.rex;
2444 i.rex = 0;
2445 }
2446 else if (i.rex != 0)
29b0f896
AM		 2447 add_prefix (REX_OPCODE | i.rex);
2448
2449 /* We are ready to output the insn. */
2450 output_insn ();
2451}
2452
2453static char *
e3bb37b5 2454parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2455{
2456 char *l = line;
2457 char *token_start = l;
2458 char *mnem_p;
5c6af06e
JB		 2459 int supported;
2460 const template *t;
29b0f896
AM		 2461
2462 /* Non-zero if we found a prefix only acceptable with string insns. */
2463 const char *expecting_string_instruction = NULL;
45288df1 2464
29b0f896
AM		 2465 while (1)
2466 {
2467 mnem_p = mnemonic;
2468 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2469 {
2470 mnem_p++;
2471 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2472 {
29b0f896
AM		 2473 as_bad (_("no such instruction: `%s'"), token_start);
2474 return NULL;
2475 }
2476 l++;
2477 }
2478 if (!is_space_char (*l)
2479 && *l != END_OF_INSN
e44823cf
JB		 2480 && (intel_syntax
2481 || (*l != PREFIX_SEPARATOR
2482 && *l != ',')))
29b0f896
AM		 2483 {
2484 as_bad (_("invalid character %s in mnemonic"),
2485 output_invalid (*l));
2486 return NULL;
2487 }
2488 if (token_start == l)
2489 {
e44823cf 2490 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2491 as_bad (_("expecting prefix; got nothing"));
2492 else
2493 as_bad (_("expecting mnemonic; got nothing"));
2494 return NULL;
2495 }
45288df1 2496
29b0f896
AM		 2497 /* Look up instruction (or prefix) via hash table. */
2498 current_templates = hash_find (op_hash, mnemonic);
47926f60 2499
29b0f896
AM		 2500 if (*l != END_OF_INSN
2501 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2502 && current_templates
40fb9820 2503 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2504 {
c6fb90c8 2505 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 2506 {
2507 as_bad ((flag_code != CODE_64BIT
2508 ? _("`%s' is only supported in 64-bit mode")
2509 : _("`%s' is not supported in 64-bit mode")),
2510 current_templates->start->name);
2511 return NULL;
2512 }
29b0f896
AM		 2513 /* If we are in 16-bit mode, do not allow addr16 or data16.
2514 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 2515 if ((current_templates->start->opcode_modifier.size16
2516 || current_templates->start->opcode_modifier.size32)
29b0f896 2517 && flag_code != CODE_64BIT
40fb9820 2518 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 2519 ^ (flag_code == CODE_16BIT)))
2520 {
2521 as_bad (_("redundant %s prefix"),
2522 current_templates->start->name);
2523 return NULL;
45288df1 2524 }
29b0f896
AM		 2525 /* Add prefix, checking for repeated prefixes. */
2526 switch (add_prefix (current_templates->start->base_opcode))
2527 {
2528 case 0:
2529 return NULL;
2530 case 2:
2531 expecting_string_instruction = current_templates->start->name;
2532 break;
2533 }
2534 /* Skip past PREFIX_SEPARATOR and reset token_start. */
2535 token_start = ++l;
2536 }
2537 else
2538 break;
2539 }
45288df1 2540
29b0f896
AM		 2541 if (!current_templates)
2542 {
2543 /* See if we can get a match by trimming off a suffix. */
2544 switch (mnem_p[-1])
2545 {
2546 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 2547 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
2548 i.suffix = SHORT_MNEM_SUFFIX;
2549 else
29b0f896
AM		 2550 case BYTE_MNEM_SUFFIX:
2551 case QWORD_MNEM_SUFFIX:
2552 i.suffix = mnem_p[-1];
2553 mnem_p[-1] = '\0';
2554 current_templates = hash_find (op_hash, mnemonic);
2555 break;
2556 case SHORT_MNEM_SUFFIX:
2557 case LONG_MNEM_SUFFIX:
2558 if (!intel_syntax)
2559 {
2560 i.suffix = mnem_p[-1];
2561 mnem_p[-1] = '\0';
2562 current_templates = hash_find (op_hash, mnemonic);
2563 }
2564 break;
252b5132 2565
29b0f896
AM		 2566 /* Intel Syntax. */
2567 case 'd':
2568 if (intel_syntax)
2569 {
9306ca4a 2570 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 2571 i.suffix = SHORT_MNEM_SUFFIX;
2572 else
2573 i.suffix = LONG_MNEM_SUFFIX;
2574 mnem_p[-1] = '\0';
2575 current_templates = hash_find (op_hash, mnemonic);
2576 }
2577 break;
2578 }
2579 if (!current_templates)
2580 {
2581 as_bad (_("no such instruction: `%s'"), token_start);
2582 return NULL;
2583 }
2584 }
252b5132 2585
40fb9820
L		 2586 if (current_templates->start->opcode_modifier.jump
2587 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 2588 {
2589 /* Check for a branch hint. We allow ",pt" and ",pn" for
2590 predict taken and predict not taken respectively.
2591 I'm not sure that branch hints actually do anything on loop
2592 and jcxz insns (JumpByte) for current Pentium4 chips. They
2593 may work in the future and it doesn't hurt to accept them
2594 now. */
2595 if (l[0] == ',' && l[1] == 'p')
2596 {
2597 if (l[2] == 't')
2598 {
2599 if (!add_prefix (DS_PREFIX_OPCODE))
2600 return NULL;
2601 l += 3;
2602 }
2603 else if (l[2] == 'n')
2604 {
2605 if (!add_prefix (CS_PREFIX_OPCODE))
2606 return NULL;
2607 l += 3;
2608 }
2609 }
2610 }
2611 /* Any other comma loses. */
2612 if (*l == ',')
2613 {
2614 as_bad (_("invalid character %s in mnemonic"),
2615 output_invalid (*l));
2616 return NULL;
2617 }
252b5132 2618
29b0f896 2619 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 2620 supported = 0;
2621 for (t = current_templates->start; t < current_templates->end; ++t)
2622 {
3629bb00
L		 2623 supported |= cpu_flags_match (t->cpu_flags);
2624 if (supported == 3)
2625 goto skip;
5c6af06e 2626 }
3629bb00 2627
5c6af06e
JB		 2628 if (!(supported & 2))
2629 {
2630 as_bad (flag_code == CODE_64BIT
2631 ? _("`%s' is not supported in 64-bit mode")
2632 : _("`%s' is only supported in 64-bit mode"),
2633 current_templates->start->name);
2634 return NULL;
2635 }
2636 if (!(supported & 1))
29b0f896 2637 {
3629bb00
L		 2638 as_bad (_("`%s' is not supported on `%s%s'"),
2639 current_templates->start->name, cpu_arch_name,
2640 cpu_sub_arch_name ? cpu_sub_arch_name : "");
2641 return NULL;
29b0f896 2642 }
3629bb00
L		 2643
2644skip:
2645 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 2646 && (flag_code != CODE_16BIT))
29b0f896
AM		 2647 {
2648 as_warn (_("use .code16 to ensure correct addressing mode"));
2649 }
252b5132 2650
29b0f896 2651 /* Check for rep/repne without a string instruction. */
f41bbced 2652 if (expecting_string_instruction)
29b0f896 2653 {
f41bbced
JB		 2654 static templates override;
2655
2656 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 2657 if (t->opcode_modifier.isstring)
f41bbced
JB		 2658 break;
2659 if (t >= current_templates->end)
2660 {
2661 as_bad (_("expecting string instruction after `%s'"),
64e74474 2662 expecting_string_instruction);
f41bbced
JB		 2663 return NULL;
2664 }
2665 for (override.start = t; t < current_templates->end; ++t)
40fb9820 2666 if (!t->opcode_modifier.isstring)
f41bbced
JB		 2667 break;
2668 override.end = t;
2669 current_templates = &override;
29b0f896 2670 }
252b5132 2671
29b0f896
AM		 2672 return l;
2673}
252b5132 2674
29b0f896 2675static char *
e3bb37b5 2676parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 2677{
2678 char *token_start;
3138f287 2679
29b0f896
AM		 2680 /* 1 if operand is pending after ','. */
2681 unsigned int expecting_operand = 0;
252b5132 2682
29b0f896
AM		 2683 /* Non-zero if operand parens not balanced. */
2684 unsigned int paren_not_balanced;
2685
2686 while (*l != END_OF_INSN)
2687 {
2688 /* Skip optional white space before operand. */
2689 if (is_space_char (*l))
2690 ++l;
2691 if (!is_operand_char (*l) && *l != END_OF_INSN)
2692 {
2693 as_bad (_("invalid character %s before operand %d"),
2694 output_invalid (*l),
2695 i.operands + 1);
2696 return NULL;
2697 }
2698 token_start = l; /* after white space */
2699 paren_not_balanced = 0;
2700 while (paren_not_balanced || *l != ',')
2701 {
2702 if (*l == END_OF_INSN)
2703 {
2704 if (paren_not_balanced)
2705 {
2706 if (!intel_syntax)
2707 as_bad (_("unbalanced parenthesis in operand %d."),
2708 i.operands + 1);
2709 else
2710 as_bad (_("unbalanced brackets in operand %d."),
2711 i.operands + 1);
2712 return NULL;
2713 }
2714 else
2715 break; /* we are done */
2716 }
2717 else if (!is_operand_char (*l) && !is_space_char (*l))
2718 {
2719 as_bad (_("invalid character %s in operand %d"),
2720 output_invalid (*l),
2721 i.operands + 1);
2722 return NULL;
2723 }
2724 if (!intel_syntax)
2725 {
2726 if (*l == '(')
2727 ++paren_not_balanced;
2728 if (*l == ')')
2729 --paren_not_balanced;
2730 }
2731 else
2732 {
2733 if (*l == '[')
2734 ++paren_not_balanced;
2735 if (*l == ']')
2736 --paren_not_balanced;
2737 }
2738 l++;
2739 }
2740 if (l != token_start)
2741 { /* Yes, we've read in another operand. */
2742 unsigned int operand_ok;
2743 this_operand = i.operands++;
7d5e4556 2744 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 2745 if (i.operands > MAX_OPERANDS)
2746 {
2747 as_bad (_("spurious operands; (%d operands/instruction max)"),
2748 MAX_OPERANDS);
2749 return NULL;
2750 }
2751 /* Now parse operand adding info to 'i' as we go along. */
2752 END_STRING_AND_SAVE (l);
2753
2754 if (intel_syntax)
2755 operand_ok =
2756 i386_intel_operand (token_start,
2757 intel_float_operand (mnemonic));
2758 else
a7619375 2759 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 2760
2761 RESTORE_END_STRING (l);
2762 if (!operand_ok)
2763 return NULL;
2764 }
2765 else
2766 {
2767 if (expecting_operand)
2768 {
2769 expecting_operand_after_comma:
2770 as_bad (_("expecting operand after ','; got nothing"));
2771 return NULL;
2772 }
2773 if (*l == ',')
2774 {
2775 as_bad (_("expecting operand before ','; got nothing"));
2776 return NULL;
2777 }
2778 }
7f3f1ea2 2779
29b0f896
AM		 2780 /* Now *l must be either ',' or END_OF_INSN. */
2781 if (*l == ',')
2782 {
2783 if (*++l == END_OF_INSN)
2784 {
2785 /* Just skip it, if it's \n complain. */
2786 goto expecting_operand_after_comma;
2787 }
2788 expecting_operand = 1;
2789 }
2790 }
2791 return l;
2792}
7f3f1ea2 2793
050dfa73 2794static void
4d456e3d 2795swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 2796{
2797 union i386_op temp_op;
40fb9820 2798 i386_operand_type temp_type;
050dfa73 2799 enum bfd_reloc_code_real temp_reloc;
4eed87de 2800
050dfa73
MM		 2801 temp_type = i.types[xchg2];
2802 i.types[xchg2] = i.types[xchg1];
2803 i.types[xchg1] = temp_type;
2804 temp_op = i.op[xchg2];
2805 i.op[xchg2] = i.op[xchg1];
2806 i.op[xchg1] = temp_op;
2807 temp_reloc = i.reloc[xchg2];
2808 i.reloc[xchg2] = i.reloc[xchg1];
2809 i.reloc[xchg1] = temp_reloc;
2810}
2811
29b0f896 2812static void
e3bb37b5 2813swap_operands (void)
29b0f896 2814{
b7c61d9a 2815 switch (i.operands)
050dfa73 2816 {
b7c61d9a 2817 case 4:
4d456e3d 2818 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 2819 case 3:
2820 case 2:
4d456e3d 2821 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 2822 break;
2823 default:
2824 abort ();
29b0f896 2825 }
29b0f896
AM		 2826
2827 if (i.mem_operands == 2)
2828 {
2829 const seg_entry *temp_seg;
2830 temp_seg = i.seg[0];
2831 i.seg[0] = i.seg[1];
2832 i.seg[1] = temp_seg;
2833 }
2834}
252b5132 2835
29b0f896
AM		 2836/* Try to ensure constant immediates are represented in the smallest
2837 opcode possible. */
2838static void
e3bb37b5 2839optimize_imm (void)
29b0f896
AM		 2840{
2841 char guess_suffix = 0;
2842 int op;
252b5132 2843
29b0f896
AM		 2844 if (i.suffix)
2845 guess_suffix = i.suffix;
2846 else if (i.reg_operands)
2847 {
2848 /* Figure out a suffix from the last register operand specified.
2849 We can't do this properly yet, ie. excluding InOutPortReg,
2850 but the following works for instructions with immediates.
2851 In any case, we can't set i.suffix yet. */
2852 for (op = i.operands; --op >= 0;)
40fb9820
L		 2853 if (i.types[op].bitfield.reg8)
2854 {
2855 guess_suffix = BYTE_MNEM_SUFFIX;
2856 break;
2857 }
2858 else if (i.types[op].bitfield.reg16)
252b5132 2859 {
40fb9820
L		 2860 guess_suffix = WORD_MNEM_SUFFIX;
2861 break;
2862 }
2863 else if (i.types[op].bitfield.reg32)
2864 {
2865 guess_suffix = LONG_MNEM_SUFFIX;
2866 break;
2867 }
2868 else if (i.types[op].bitfield.reg64)
2869 {
2870 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 2871 break;
252b5132 2872 }
29b0f896
AM		 2873 }
2874 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
2875 guess_suffix = WORD_MNEM_SUFFIX;
2876
2877 for (op = i.operands; --op >= 0;)
40fb9820 2878 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 2879 {
2880 switch (i.op[op].imms->X_op)
252b5132 2881 {
29b0f896
AM		 2882 case O_constant:
2883 /* If a suffix is given, this operand may be shortened. */
2884 switch (guess_suffix)
252b5132 2885 {
29b0f896 2886 case LONG_MNEM_SUFFIX:
40fb9820
L		 2887 i.types[op].bitfield.imm32 = 1;
2888 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2889 break;
2890 case WORD_MNEM_SUFFIX:
40fb9820
L		 2891 i.types[op].bitfield.imm16 = 1;
2892 i.types[op].bitfield.imm32 = 1;
2893 i.types[op].bitfield.imm32s = 1;
2894 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 2895 break;
2896 case BYTE_MNEM_SUFFIX:
40fb9820
L		 2897 i.types[op].bitfield.imm8 = 1;
2898 i.types[op].bitfield.imm8s = 1;
2899 i.types[op].bitfield.imm16 = 1;
2900 i.types[op].bitfield.imm32 = 1;
2901 i.types[op].bitfield.imm32s = 1;
2902 i.types[op].bitfield.imm64 = 1;
29b0f896 2903 break;
252b5132 2904 }
252b5132 2905
29b0f896
AM		 2906 /* If this operand is at most 16 bits, convert it
2907 to a signed 16 bit number before trying to see
2908 whether it will fit in an even smaller size.
2909 This allows a 16-bit operand such as $0xffe0 to
2910 be recognised as within Imm8S range. */
40fb9820 2911 if ((i.types[op].bitfield.imm16)
29b0f896 2912 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 2913 {
29b0f896
AM		 2914 i.op[op].imms->X_add_number =
2915 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
2916 }
40fb9820 2917 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 2918 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
2919 == 0))
2920 {
2921 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
2922 ^ ((offsetT) 1 << 31))
2923 - ((offsetT) 1 << 31));
2924 }
40fb9820 2925 i.types[op]
c6fb90c8
L		 2926 = operand_type_or (i.types[op],
2927 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 2928
29b0f896
AM		 2929 /* We must avoid matching of Imm32 templates when 64bit
2930 only immediate is available. */
2931 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 2932 i.types[op].bitfield.imm32 = 0;
29b0f896 2933 break;
252b5132 2934
29b0f896
AM		 2935 case O_absent:
2936 case O_register:
2937 abort ();
2938
2939 /* Symbols and expressions. */
2940 default:
9cd96992
JB		 2941 /* Convert symbolic operand to proper sizes for matching, but don't
2942 prevent matching a set of insns that only supports sizes other
2943 than those matching the insn suffix. */
2944 {
40fb9820 2945 i386_operand_type mask, allowed;
9cd96992
JB		 2946 const template *t;
2947
c6fb90c8
L		 2948 UINTS_CLEAR (mask);
2949 UINTS_CLEAR (allowed);
40fb9820 2950
4eed87de
AM		 2951 for (t = current_templates->start;
2952 t < current_templates->end;
2953 ++t)
c6fb90c8
L		 2954 allowed = operand_type_or (allowed,
2955 t->operand_types[op]);
9cd96992
JB		 2956 switch (guess_suffix)
2957 {
2958 case QWORD_MNEM_SUFFIX:
40fb9820
L		 2959 mask.bitfield.imm64 = 1;
2960 mask.bitfield.imm32s = 1;
9cd96992
JB		 2961 break;
2962 case LONG_MNEM_SUFFIX:
40fb9820 2963 mask.bitfield.imm32 = 1;
9cd96992
JB		 2964 break;
2965 case WORD_MNEM_SUFFIX:
40fb9820 2966 mask.bitfield.imm16 = 1;
9cd96992
JB		 2967 break;
2968 case BYTE_MNEM_SUFFIX:
40fb9820 2969 mask.bitfield.imm8 = 1;
9cd96992
JB		 2970 break;
2971 default:
9cd96992
JB		 2972 break;
2973 }
c6fb90c8
L		 2974 allowed = operand_type_and (mask, allowed);
2975 if (!UINTS_ALL_ZERO (allowed))
2976 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 2977 }
29b0f896 2978 break;
252b5132 2979 }
29b0f896
AM		 2980 }
2981}
47926f60 2982
29b0f896
AM		 2983/* Try to use the smallest displacement type too. */
2984static void
e3bb37b5 2985optimize_disp (void)
29b0f896
AM		 2986{
2987 int op;
3e73aa7c 2988
29b0f896 2989 for (op = i.operands; --op >= 0;)
40fb9820 2990 if (operand_type_check (i.types[op], disp))
252b5132 2991 {
b300c311 2992 if (i.op[op].disps->X_op == O_constant)
252b5132 2993 {
b300c311 2994 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 2995
40fb9820 2996 if (i.types[op].bitfield.disp16
b300c311
L		 2997 && (disp & ~(offsetT) 0xffff) == 0)
2998 {
2999 /* If this operand is at most 16 bits, convert
3000 to a signed 16 bit number and don't use 64bit
3001 displacement. */
3002 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3003 i.types[op].bitfield.disp64 = 0;
b300c311 3004 }
40fb9820 3005 if (i.types[op].bitfield.disp32
b300c311
L		 3006 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3007 {
3008 /* If this operand is at most 32 bits, convert
3009 to a signed 32 bit number and don't use 64bit
3010 displacement. */
3011 disp &= (((offsetT) 2 << 31) - 1);
3012 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3013 i.types[op].bitfield.disp64 = 0;
b300c311 3014 }
40fb9820 3015 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3016 {
40fb9820
L		 3017 i.types[op].bitfield.disp8 = 0;
3018 i.types[op].bitfield.disp16 = 0;
3019 i.types[op].bitfield.disp32 = 0;
3020 i.types[op].bitfield.disp32s = 0;
3021 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3022 i.op[op].disps = 0;
3023 i.disp_operands--;
3024 }
3025 else if (flag_code == CODE_64BIT)
3026 {
3027 if (fits_in_signed_long (disp))
28a9d8f5 3028 {
40fb9820
L		 3029 i.types[op].bitfield.disp64 = 0;
3030 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3031 }
b300c311 3032 if (fits_in_unsigned_long (disp))
40fb9820 3033 i.types[op].bitfield.disp32 = 1;
b300c311 3034 }
40fb9820
L		 3035 if ((i.types[op].bitfield.disp32
3036 || i.types[op].bitfield.disp32s
3037 || i.types[op].bitfield.disp16)
b300c311 3038 && fits_in_signed_byte (disp))
40fb9820 3039 i.types[op].bitfield.disp8 = 1;
252b5132 3040 }
67a4f2b7
AO		 3041 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3042 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3043 {
3044 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3045 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3046 i.types[op].bitfield.disp8 = 0;
3047 i.types[op].bitfield.disp16 = 0;
3048 i.types[op].bitfield.disp32 = 0;
3049 i.types[op].bitfield.disp32s = 0;
3050 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3051 }
3052 else
b300c311 3053 /* We only support 64bit displacement on constants. */
40fb9820 3054 i.types[op].bitfield.disp64 = 0;
252b5132 3055 }
29b0f896
AM		 3056}
3057
3058static int
e3bb37b5 3059match_template (void)
29b0f896
AM		 3060{
3061 /* Points to template once we've found it. */
3062 const template *t;
40fb9820 3063 i386_operand_type overlap0, overlap1, overlap2, overlap3;
29b0f896 3064 unsigned int found_reverse_match;
40fb9820
L		 3065 i386_opcode_modifier suffix_check;
3066 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3067 int addr_prefix_disp;
a5c311ca 3068 unsigned int j;
3629bb00 3069 unsigned int found_cpu_match;
45664ddb 3070 unsigned int check_register;
29b0f896 3071
f48ff2ae
L		 3072#if MAX_OPERANDS != 4
3073# error "MAX_OPERANDS must be 4."
3074#endif
3075
29b0f896 3076 found_reverse_match = 0;
539e75ad 3077 addr_prefix_disp = -1;
40fb9820
L		 3078
3079 memset (&suffix_check, 0, sizeof (suffix_check));
3080 if (i.suffix == BYTE_MNEM_SUFFIX)
3081 suffix_check.no_bsuf = 1;
3082 else if (i.suffix == WORD_MNEM_SUFFIX)
3083 suffix_check.no_wsuf = 1;
3084 else if (i.suffix == SHORT_MNEM_SUFFIX)
3085 suffix_check.no_ssuf = 1;
3086 else if (i.suffix == LONG_MNEM_SUFFIX)
3087 suffix_check.no_lsuf = 1;
3088 else if (i.suffix == QWORD_MNEM_SUFFIX)
3089 suffix_check.no_qsuf = 1;
3090 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3091 suffix_check.no_ldsuf = 1;
29b0f896 3092
45aa61fe 3093 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3094 {
539e75ad
L		 3095 addr_prefix_disp = -1;
3096
29b0f896
AM		 3097 /* Must have right number of operands. */
3098 if (i.operands != t->operands)
3099 continue;
3100
50aecf8c
L		 3101 /* Check processor support. */
3102 found_cpu_match = cpu_flags_match (t->cpu_flags) == 3;
3103 if (!found_cpu_match)
3104 continue;
3105
e1d4d893
L		 3106 /* Check old gcc support. */
3107 if (!old_gcc && t->opcode_modifier.oldgcc)
3108 continue;
3109
3110 /* Check AT&T mnemonic. */
3111 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3112 continue;
3113
5c07affc
L		 3114 /* Check AT&T syntax Intel syntax. */
3115 if ((intel_syntax && t->opcode_modifier.attsyntax)
3116 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3117 continue;
3118
20592a94 3119 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3120 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3121 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3122 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3123 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3124 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3125 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3126 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3127 continue;
3128
5c07affc 3129 if (!operand_size_match (t))
7d5e4556 3130 continue;
539e75ad 3131
5c07affc
L		 3132 for (j = 0; j < MAX_OPERANDS; j++)
3133 operand_types[j] = t->operand_types[j];
3134
45aa61fe
AM		 3135 /* In general, don't allow 64-bit operands in 32-bit mode. */
3136 if (i.suffix == QWORD_MNEM_SUFFIX
3137 && flag_code != CODE_64BIT
3138 && (intel_syntax
40fb9820 3139 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3140 && !intel_float_operand (t->name))
3141 : intel_float_operand (t->name) != 2)
40fb9820
L		 3142 && ((!operand_types[0].bitfield.regmmx
3143 && !operand_types[0].bitfield.regxmm)
3144 || (!operand_types[t->operands > 1].bitfield.regmmx
3145 && !!operand_types[t->operands > 1].bitfield.regxmm))
45aa61fe
AM		 3146 && (t->base_opcode != 0x0fc7
3147 || t->extension_opcode != 1 /* cmpxchg8b */))
3148 continue;
3149
29b0f896 3150 /* Do not verify operands when there are none. */
50aecf8c 3151 else
29b0f896 3152 {
c6fb90c8 3153 if (!t->operands)
2dbab7d5
L		 3154 /* We've found a match; break out of loop. */
3155 break;
29b0f896 3156 }
252b5132 3157
539e75ad
L		 3158 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3159 into Disp32/Disp16/Disp32 operand. */
3160 if (i.prefix[ADDR_PREFIX] != 0)
3161 {
40fb9820 3162 /* There should be only one Disp operand. */
539e75ad
L		 3163 switch (flag_code)
3164 {
3165 case CODE_16BIT:
40fb9820
L		 3166 for (j = 0; j < MAX_OPERANDS; j++)
3167 {
3168 if (operand_types[j].bitfield.disp16)
3169 {
3170 addr_prefix_disp = j;
3171 operand_types[j].bitfield.disp32 = 1;
3172 operand_types[j].bitfield.disp16 = 0;
3173 break;
3174 }
3175 }
539e75ad
L		 3176 break;
3177 case CODE_32BIT:
40fb9820
L		 3178 for (j = 0; j < MAX_OPERANDS; j++)
3179 {
3180 if (operand_types[j].bitfield.disp32)
3181 {
3182 addr_prefix_disp = j;
3183 operand_types[j].bitfield.disp32 = 0;
3184 operand_types[j].bitfield.disp16 = 1;
3185 break;
3186 }
3187 }
539e75ad
L		 3188 break;
3189 case CODE_64BIT:
40fb9820
L		 3190 for (j = 0; j < MAX_OPERANDS; j++)
3191 {
3192 if (operand_types[j].bitfield.disp64)
3193 {
3194 addr_prefix_disp = j;
3195 operand_types[j].bitfield.disp64 = 0;
3196 operand_types[j].bitfield.disp32 = 1;
3197 break;
3198 }
3199 }
539e75ad
L		 3200 break;
3201 }
539e75ad
L		 3202 }
3203
45664ddb
L		 3204 /* We check register size only if size of operands can be
3205 encoded the canonical way. */
3206 check_register = t->opcode_modifier.w;
c6fb90c8 3207 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3208 switch (t->operands)
3209 {
3210 case 1:
40fb9820 3211 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3212 continue;
3213 break;
3214 case 2:
8b38ad71
L		 3215 /* xchg %eax, %eax is a special case. It is an aliase for nop
3216 only in 32bit mode and we can use opcode 0x90. In 64bit
3217 mode, we can't use 0x90 for xchg %eax, %eax since it should
3218 zero-extend %eax to %rax. */
3219 if (flag_code == CODE_64BIT
3220 && t->base_opcode == 0x90
c6fb90c8
L		 3221 && UINTS_EQUAL (i.types [0], acc32)
3222 && UINTS_EQUAL (i.types [1], acc32))
8b38ad71 3223 continue;
29b0f896 3224 case 3:
f48ff2ae 3225 case 4:
c6fb90c8 3226 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3227 if (!operand_type_match (overlap0, i.types[0])
3228 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3229 || (check_register
3230 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3231 operand_types[0],
3232 overlap1, i.types[1],
3233 operand_types[1])))
29b0f896
AM		 3234 {
3235 /* Check if other direction is valid ... */
40fb9820 3236 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3237 continue;
3238
3239 /* Try reversing direction of operands. */
c6fb90c8
L		 3240 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3241 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3242 if (!operand_type_match (overlap0, i.types[0])
3243 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3244 || (check_register
3245 && !operand_type_register_match (overlap0,
3246 i.types[0],
3247 operand_types[1],
3248 overlap1,
3249 i.types[1],
3250 operand_types[0])))
29b0f896
AM		 3251 {
3252 /* Does not match either direction. */
3253 continue;
3254 }
3255 /* found_reverse_match holds which of D or FloatDR
3256 we've found. */
40fb9820 3257 if (t->opcode_modifier.d)
8a2ed489 3258 found_reverse_match = Opcode_D;
40fb9820 3259 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3260 found_reverse_match = Opcode_FloatD;
3261 else
3262 found_reverse_match = 0;
40fb9820 3263 if (t->opcode_modifier.floatr)
8a2ed489 3264 found_reverse_match |= Opcode_FloatR;
29b0f896 3265 }
f48ff2ae 3266 else
29b0f896 3267 {
f48ff2ae 3268 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3269 switch (t->operands)
3270 {
3271 case 4:
c6fb90c8
L		 3272 overlap3 = operand_type_and (i.types[3],
3273 operand_types[3]);
d1cbb4db 3274 case 3:
c6fb90c8
L		 3275 overlap2 = operand_type_and (i.types[2],
3276 operand_types[2]);
d1cbb4db
L		 3277 break;
3278 }
29b0f896 3279
f48ff2ae
L		 3280 switch (t->operands)
3281 {
3282 case 4:
40fb9820 3283 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3284 || (check_register
3285 && !operand_type_register_match (overlap2,
3286 i.types[2],
3287 operand_types[2],
3288 overlap3,
3289 i.types[3],
3290 operand_types[3])))
f48ff2ae
L		 3291 continue;
3292 case 3:
3293 /* Here we make use of the fact that there are no
3294 reverse match 3 operand instructions, and all 3
3295 operand instructions only need to be checked for
3296 register consistency between operands 2 and 3. */
40fb9820 3297 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3298 || (check_register
3299 && !operand_type_register_match (overlap1,
3300 i.types[1],
3301 operand_types[1],
3302 overlap2,
3303 i.types[2],
3304 operand_types[2])))
f48ff2ae
L		 3305 continue;
3306 break;
3307 }
29b0f896 3308 }
f48ff2ae 3309 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3310 slip through to break. */
3311 }
3629bb00 3312 if (!found_cpu_match)
29b0f896
AM		 3313 {
3314 found_reverse_match = 0;
3315 continue;
3316 }
3317 /* We've found a match; break out of loop. */
3318 break;
3319 }
3320
3321 if (t == current_templates->end)
3322 {
3323 /* We found no match. */
3324 as_bad (_("suffix or operands invalid for `%s'"),
3325 current_templates->start->name);
3326 return 0;
3327 }
252b5132 3328
29b0f896
AM		 3329 if (!quiet_warnings)
3330 {
3331 if (!intel_syntax
40fb9820
L		 3332 && (i.types[0].bitfield.jumpabsolute
3333 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3334 {
3335 as_warn (_("indirect %s without `*'"), t->name);
3336 }
3337
40fb9820
L		 3338 if (t->opcode_modifier.isprefix
3339 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3340 {
3341 /* Warn them that a data or address size prefix doesn't
3342 affect assembly of the next line of code. */
3343 as_warn (_("stand-alone `%s' prefix"), t->name);
3344 }
3345 }
3346
3347 /* Copy the template we found. */
3348 i.tm = *t;
539e75ad
L		 3349
3350 if (addr_prefix_disp != -1)
3351 i.tm.operand_types[addr_prefix_disp]
3352 = operand_types[addr_prefix_disp];
3353
29b0f896
AM		 3354 if (found_reverse_match)
3355 {
3356 /* If we found a reverse match we must alter the opcode
3357 direction bit. found_reverse_match holds bits to change
3358 (different for int & float insns). */
3359
3360 i.tm.base_opcode ^= found_reverse_match;
3361
539e75ad
L		 3362 i.tm.operand_types[0] = operand_types[1];
3363 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3364 }
3365
3366 return 1;
3367}
3368
3369static int
e3bb37b5 3370check_string (void)
29b0f896 3371{
40fb9820
L		 3372 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3373 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3374 {
3375 if (i.seg[0] != NULL && i.seg[0] != &es)
3376 {
3377 as_bad (_("`%s' operand %d must use `%%es' segment"),
3378 i.tm.name,
3379 mem_op + 1);
3380 return 0;
3381 }
3382 /* There's only ever one segment override allowed per instruction.
3383 This instruction possibly has a legal segment override on the
3384 second operand, so copy the segment to where non-string
3385 instructions store it, allowing common code. */
3386 i.seg[0] = i.seg[1];
3387 }
40fb9820 3388 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3389 {
3390 if (i.seg[1] != NULL && i.seg[1] != &es)
3391 {
3392 as_bad (_("`%s' operand %d must use `%%es' segment"),
3393 i.tm.name,
3394 mem_op + 2);
3395 return 0;
3396 }
3397 }
3398 return 1;
3399}
3400
3401static int
543613e9 3402process_suffix (void)
29b0f896
AM		 3403{
3404 /* If matched instruction specifies an explicit instruction mnemonic
3405 suffix, use it. */
40fb9820
L		 3406 if (i.tm.opcode_modifier.size16)
3407 i.suffix = WORD_MNEM_SUFFIX;
3408 else if (i.tm.opcode_modifier.size32)
3409 i.suffix = LONG_MNEM_SUFFIX;
3410 else if (i.tm.opcode_modifier.size64)
3411 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3412 else if (i.reg_operands)
3413 {
3414 /* If there's no instruction mnemonic suffix we try to invent one
3415 based on register operands. */
3416 if (!i.suffix)
3417 {
3418 /* We take i.suffix from the last register operand specified,
3419 Destination register type is more significant than source
381d071f
L		 3420 register type. crc32 in SSE4.2 prefers source register
3421 type. */
3422 if (i.tm.base_opcode == 0xf20f38f1)
3423 {
40fb9820
L		 3424 if (i.types[0].bitfield.reg16)
3425 i.suffix = WORD_MNEM_SUFFIX;
3426 else if (i.types[0].bitfield.reg32)
3427 i.suffix = LONG_MNEM_SUFFIX;
3428 else if (i.types[0].bitfield.reg64)
3429 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3430 }
9344ff29 3431 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3432 {
40fb9820 3433 if (i.types[0].bitfield.reg8)
20592a94
L		 3434 i.suffix = BYTE_MNEM_SUFFIX;
3435 }
381d071f
L		 3436
3437 if (!i.suffix)
3438 {
3439 int op;
3440
20592a94
L		 3441 if (i.tm.base_opcode == 0xf20f38f1
3442 || i.tm.base_opcode == 0xf20f38f0)
3443 {
3444 /* We have to know the operand size for crc32. */
3445 as_bad (_("ambiguous memory operand size for `%s`"),
3446 i.tm.name);
3447 return 0;
3448 }
3449
381d071f 3450 for (op = i.operands; --op >= 0;)
40fb9820 3451 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 3452 {
40fb9820
L		 3453 if (i.types[op].bitfield.reg8)
3454 {
3455 i.suffix = BYTE_MNEM_SUFFIX;
3456 break;
3457 }
3458 else if (i.types[op].bitfield.reg16)
3459 {
3460 i.suffix = WORD_MNEM_SUFFIX;
3461 break;
3462 }
3463 else if (i.types[op].bitfield.reg32)
3464 {
3465 i.suffix = LONG_MNEM_SUFFIX;
3466 break;
3467 }
3468 else if (i.types[op].bitfield.reg64)
3469 {
3470 i.suffix = QWORD_MNEM_SUFFIX;
3471 break;
3472 }
381d071f
L		 3473 }
3474 }
29b0f896
AM		 3475 }
3476 else if (i.suffix == BYTE_MNEM_SUFFIX)
3477 {
3478 if (!check_byte_reg ())
3479 return 0;
3480 }
3481 else if (i.suffix == LONG_MNEM_SUFFIX)
3482 {
3483 if (!check_long_reg ())
3484 return 0;
3485 }
3486 else if (i.suffix == QWORD_MNEM_SUFFIX)
3487 {
955e1e6a
L		 3488 if (intel_syntax
3489 && i.tm.opcode_modifier.ignoresize
3490 && i.tm.opcode_modifier.no_qsuf)
3491 i.suffix = 0;
3492 else if (!check_qword_reg ())
29b0f896
AM		 3493 return 0;
3494 }
3495 else if (i.suffix == WORD_MNEM_SUFFIX)
3496 {
3497 if (!check_word_reg ())
3498 return 0;
3499 }
582d5edd
L		 3500 else if (i.suffix == XMMWORD_MNEM_SUFFIX)
3501 {
3502 /* Skip if the instruction has x suffix. match_template
3503 should check if it is a valid suffix. */
3504 }
40fb9820 3505 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 3506 /* Do nothing if the instruction is going to ignore the prefix. */
3507 ;
3508 else
3509 abort ();
3510 }
40fb9820 3511 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 3512 && !i.suffix
3513 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 3514 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 3515 {
3516 i.suffix = stackop_size;
3517 }
9306ca4a
JB		 3518 else if (intel_syntax
3519 && !i.suffix
40fb9820
L		 3520 && (i.tm.operand_types[0].bitfield.jumpabsolute
3521 || i.tm.opcode_modifier.jumpbyte
3522 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 3523 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
3524 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 3525 {
3526 switch (flag_code)
3527 {
3528 case CODE_64BIT:
40fb9820 3529 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 3530 {
3531 i.suffix = QWORD_MNEM_SUFFIX;
3532 break;
3533 }
3534 case CODE_32BIT:
40fb9820 3535 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 3536 i.suffix = LONG_MNEM_SUFFIX;
3537 break;
3538 case CODE_16BIT:
40fb9820 3539 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 3540 i.suffix = WORD_MNEM_SUFFIX;
3541 break;
3542 }
3543 }
252b5132 3544
9306ca4a 3545 if (!i.suffix)
29b0f896 3546 {
9306ca4a
JB		 3547 if (!intel_syntax)
3548 {
40fb9820 3549 if (i.tm.opcode_modifier.w)
9306ca4a 3550 {
4eed87de
AM		 3551 as_bad (_("no instruction mnemonic suffix given and "
3552 "no register operands; can't size instruction"));
9306ca4a
JB		 3553 return 0;
3554 }
3555 }
3556 else
3557 {
40fb9820
L		 3558 unsigned int suffixes;
3559
3560 suffixes = !i.tm.opcode_modifier.no_bsuf;
3561 if (!i.tm.opcode_modifier.no_wsuf)
3562 suffixes |= 1 << 1;
3563 if (!i.tm.opcode_modifier.no_lsuf)
3564 suffixes |= 1 << 2;
fc4adea1 3565 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 3566 suffixes |= 1 << 3;
3567 if (!i.tm.opcode_modifier.no_ssuf)
3568 suffixes |= 1 << 4;
3569 if (!i.tm.opcode_modifier.no_qsuf)
3570 suffixes |= 1 << 5;
3571
3572 /* There are more than suffix matches. */
3573 if (i.tm.opcode_modifier.w
9306ca4a 3574 || ((suffixes & (suffixes - 1))
40fb9820
L		 3575 && !i.tm.opcode_modifier.defaultsize
3576 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 3577 {
3578 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3579 return 0;
3580 }
3581 }
29b0f896 3582 }
252b5132 3583
9306ca4a
JB		 3584 /* Change the opcode based on the operand size given by i.suffix;
3585 We don't need to change things for byte insns. */
3586
582d5edd
L		 3587 if (i.suffix
3588 && i.suffix != BYTE_MNEM_SUFFIX
3589 && i.suffix != XMMWORD_MNEM_SUFFIX)
29b0f896
AM		 3590 {
3591 /* It's not a byte, select word/dword operation. */
40fb9820 3592 if (i.tm.opcode_modifier.w)
29b0f896 3593 {
40fb9820 3594 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 3595 i.tm.base_opcode |= 8;
3596 else
3597 i.tm.base_opcode |= 1;
3598 }
0f3f3d8b 3599
29b0f896
AM		 3600 /* Now select between word & dword operations via the operand
3601 size prefix, except for instructions that will ignore this
3602 prefix anyway. */
ca61edf2 3603 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 3604 {
ca61edf2
L		 3605 /* The address size override prefix changes the size of the
3606 first operand. */
40fb9820
L		 3607 if ((flag_code == CODE_32BIT
3608 && i.op->regs[0].reg_type.bitfield.reg16)
3609 || (flag_code != CODE_32BIT
3610 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 3611 if (!add_prefix (ADDR_PREFIX_OPCODE))
3612 return 0;
3613 }
3614 else if (i.suffix != QWORD_MNEM_SUFFIX
3615 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 3616 && !i.tm.opcode_modifier.ignoresize
3617 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 3618 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
3619 || (flag_code == CODE_64BIT
40fb9820 3620 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 3621 {
3622 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 3623
40fb9820 3624 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 3625 prefix = ADDR_PREFIX_OPCODE;
252b5132 3626
29b0f896
AM		 3627 if (!add_prefix (prefix))
3628 return 0;
24eab124 3629 }
252b5132 3630
29b0f896
AM		 3631 /* Set mode64 for an operand. */
3632 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 3633 && flag_code == CODE_64BIT
40fb9820 3634 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 3635 {
3636 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 3637 need rex64. cmpxchg8b is also a special case. */
3638 if (! (i.operands == 2
3639 && i.tm.base_opcode == 0x90
3640 && i.tm.extension_opcode == None
c6fb90c8
L		 3641 && UINTS_EQUAL (i.types [0], acc64)
3642 && UINTS_EQUAL (i.types [1], acc64))
d9a5e5e5
L		 3643 && ! (i.operands == 1
3644 && i.tm.base_opcode == 0xfc7
3645 && i.tm.extension_opcode == 1
40fb9820
L		 3646 && !operand_type_check (i.types [0], reg)
3647 && operand_type_check (i.types [0], anymem)))
f6bee062 3648 i.rex |= REX_W;
46e883c5 3649 }
3e73aa7c 3650
29b0f896
AM		 3651 /* Size floating point instruction. */
3652 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 3653 if (i.tm.opcode_modifier.floatmf)
543613e9 3654 i.tm.base_opcode ^= 4;
29b0f896 3655 }
7ecd2f8b 3656
29b0f896
AM		 3657 return 1;
3658}
3e73aa7c 3659
29b0f896 3660static int
543613e9 3661check_byte_reg (void)
29b0f896
AM		 3662{
3663 int op;
543613e9 3664
29b0f896
AM		 3665 for (op = i.operands; --op >= 0;)
3666 {
3667 /* If this is an eight bit register, it's OK. If it's the 16 or
3668 32 bit version of an eight bit register, we will just use the
3669 low portion, and that's OK too. */
40fb9820 3670 if (i.types[op].bitfield.reg8)
29b0f896
AM		 3671 continue;
3672
ca61edf2
L		 3673 /* Don't generate this warning if not needed. */
3674 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 3675 continue;
3676
9344ff29
L		 3677 /* crc32 doesn't generate this warning. */
3678 if (i.tm.base_opcode == 0xf20f38f0)
3679 continue;
3680
40fb9820
L		 3681 if ((i.types[op].bitfield.reg16
3682 || i.types[op].bitfield.reg32
3683 || i.types[op].bitfield.reg64)
3684 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 3685 {
3686 /* Prohibit these changes in the 64bit mode, since the
3687 lowering is more complicated. */
3688 if (flag_code == CODE_64BIT
40fb9820 3689 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 3690 {
2ca3ace5
L		 3691 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3692 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3693 i.suffix);
3694 return 0;
3695 }
3696#if REGISTER_WARNINGS
3697 if (!quiet_warnings
40fb9820 3698 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 3699 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3700 register_prefix,
40fb9820 3701 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 3702 ? REGNAM_AL - REGNAM_AX
3703 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 3704 register_prefix,
29b0f896
AM		 3705 i.op[op].regs->reg_name,
3706 i.suffix);
3707#endif
3708 continue;
3709 }
3710 /* Any other register is bad. */
40fb9820
L		 3711 if (i.types[op].bitfield.reg16
3712 || i.types[op].bitfield.reg32
3713 || i.types[op].bitfield.reg64
3714 || i.types[op].bitfield.regmmx
3715 || i.types[op].bitfield.regxmm
3716 || i.types[op].bitfield.sreg2
3717 || i.types[op].bitfield.sreg3
3718 || i.types[op].bitfield.control
3719 || i.types[op].bitfield.debug
3720 || i.types[op].bitfield.test
3721 || i.types[op].bitfield.floatreg
3722 || i.types[op].bitfield.floatacc)
29b0f896 3723 {
a540244d
L		 3724 as_bad (_("`%s%s' not allowed with `%s%c'"),
3725 register_prefix,
29b0f896
AM		 3726 i.op[op].regs->reg_name,
3727 i.tm.name,
3728 i.suffix);
3729 return 0;
3730 }
3731 }
3732 return 1;
3733}
3734
3735static int
e3bb37b5 3736check_long_reg (void)
29b0f896
AM		 3737{
3738 int op;
3739
3740 for (op = i.operands; --op >= 0;)
3741 /* Reject eight bit registers, except where the template requires
3742 them. (eg. movzb) */
40fb9820
L		 3743 if (i.types[op].bitfield.reg8
3744 && (i.tm.operand_types[op].bitfield.reg16
3745 || i.tm.operand_types[op].bitfield.reg32
3746 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3747 {
a540244d
L		 3748 as_bad (_("`%s%s' not allowed with `%s%c'"),
3749 register_prefix,
29b0f896
AM		 3750 i.op[op].regs->reg_name,
3751 i.tm.name,
3752 i.suffix);
3753 return 0;
3754 }
3755 /* Warn if the e prefix on a general reg is missing. */
3756 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3757 && i.types[op].bitfield.reg16
3758 && (i.tm.operand_types[op].bitfield.reg32
3759 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3760 {
3761 /* Prohibit these changes in the 64bit mode, since the
3762 lowering is more complicated. */
3763 if (flag_code == CODE_64BIT)
252b5132 3764 {
2ca3ace5
L		 3765 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3766 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3767 i.suffix);
3768 return 0;
252b5132 3769 }
29b0f896
AM		 3770#if REGISTER_WARNINGS
3771 else
a540244d
L		 3772 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3773 register_prefix,
29b0f896 3774 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 3775 register_prefix,
29b0f896
AM		 3776 i.op[op].regs->reg_name,
3777 i.suffix);
3778#endif
252b5132 3779 }
29b0f896 3780 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 3781 else if (i.types[op].bitfield.reg64
3782 && (i.tm.operand_types[op].bitfield.reg32
3783 || i.tm.operand_types[op].bitfield.acc))
252b5132 3784 {
34828aad 3785 if (intel_syntax
ca61edf2 3786 && i.tm.opcode_modifier.toqword
40fb9820 3787 && !i.types[0].bitfield.regxmm)
34828aad 3788 {
ca61edf2 3789 /* Convert to QWORD. We want REX byte. */
34828aad
L		 3790 i.suffix = QWORD_MNEM_SUFFIX;
3791 }
3792 else
3793 {
3794 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3795 register_prefix, i.op[op].regs->reg_name,
3796 i.suffix);
3797 return 0;
3798 }
29b0f896
AM		 3799 }
3800 return 1;
3801}
252b5132 3802
29b0f896 3803static int
e3bb37b5 3804check_qword_reg (void)
29b0f896
AM		 3805{
3806 int op;
252b5132 3807
29b0f896
AM		 3808 for (op = i.operands; --op >= 0; )
3809 /* Reject eight bit registers, except where the template requires
3810 them. (eg. movzb) */
40fb9820
L		 3811 if (i.types[op].bitfield.reg8
3812 && (i.tm.operand_types[op].bitfield.reg16
3813 || i.tm.operand_types[op].bitfield.reg32
3814 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3815 {
a540244d
L		 3816 as_bad (_("`%s%s' not allowed with `%s%c'"),
3817 register_prefix,
29b0f896
AM		 3818 i.op[op].regs->reg_name,
3819 i.tm.name,
3820 i.suffix);
3821 return 0;
3822 }
3823 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 3824 else if ((i.types[op].bitfield.reg16
3825 || i.types[op].bitfield.reg32)
3826 && (i.tm.operand_types[op].bitfield.reg32
3827 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 3828 {
3829 /* Prohibit these changes in the 64bit mode, since the
3830 lowering is more complicated. */
34828aad 3831 if (intel_syntax
ca61edf2 3832 && i.tm.opcode_modifier.todword
40fb9820 3833 && !i.types[0].bitfield.regxmm)
34828aad 3834 {
ca61edf2 3835 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 3836 i.suffix = LONG_MNEM_SUFFIX;
3837 }
3838 else
3839 {
3840 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3841 register_prefix, i.op[op].regs->reg_name,
3842 i.suffix);
3843 return 0;
3844 }
252b5132 3845 }
29b0f896
AM		 3846 return 1;
3847}
252b5132 3848
29b0f896 3849static int
e3bb37b5 3850check_word_reg (void)
29b0f896
AM		 3851{
3852 int op;
3853 for (op = i.operands; --op >= 0;)
3854 /* Reject eight bit registers, except where the template requires
3855 them. (eg. movzb) */
40fb9820
L		 3856 if (i.types[op].bitfield.reg8
3857 && (i.tm.operand_types[op].bitfield.reg16
3858 || i.tm.operand_types[op].bitfield.reg32
3859 || i.tm.operand_types[op].bitfield.acc))
29b0f896 3860 {
a540244d
L		 3861 as_bad (_("`%s%s' not allowed with `%s%c'"),
3862 register_prefix,
29b0f896
AM		 3863 i.op[op].regs->reg_name,
3864 i.tm.name,
3865 i.suffix);
3866 return 0;
3867 }
3868 /* Warn if the e prefix on a general reg is present. */
3869 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 3870 && i.types[op].bitfield.reg32
3871 && (i.tm.operand_types[op].bitfield.reg16
3872 || i.tm.operand_types[op].bitfield.acc))
252b5132 3873 {
29b0f896
AM		 3874 /* Prohibit these changes in the 64bit mode, since the
3875 lowering is more complicated. */
3876 if (flag_code == CODE_64BIT)
252b5132 3877 {
2ca3ace5
L		 3878 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
3879 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 3880 i.suffix);
3881 return 0;
252b5132 3882 }
29b0f896
AM		 3883 else
3884#if REGISTER_WARNINGS
a540244d
L		 3885 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
3886 register_prefix,
29b0f896 3887 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 3888 register_prefix,
29b0f896
AM		 3889 i.op[op].regs->reg_name,
3890 i.suffix);
3891#endif
3892 }
3893 return 1;
3894}
252b5132 3895
29b0f896 3896static int
40fb9820 3897update_imm (unsigned int j)
29b0f896 3898{
40fb9820
L		 3899 i386_operand_type overlap;
3900
c6fb90c8 3901 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 3902 if ((overlap.bitfield.imm8
3903 || overlap.bitfield.imm8s
3904 || overlap.bitfield.imm16
3905 || overlap.bitfield.imm32
3906 || overlap.bitfield.imm32s
3907 || overlap.bitfield.imm64)
c6fb90c8
L		 3908 && !UINTS_EQUAL (overlap, imm8)
3909 && !UINTS_EQUAL (overlap, imm8s)
3910 && !UINTS_EQUAL (overlap, imm16)
3911 && !UINTS_EQUAL (overlap, imm32)
3912 && !UINTS_EQUAL (overlap, imm32s)
3913 && !UINTS_EQUAL (overlap, imm64))
29b0f896
AM		 3914 {
3915 if (i.suffix)
3916 {
40fb9820
L		 3917 i386_operand_type temp;
3918
c6fb90c8 3919 UINTS_CLEAR (temp);
40fb9820
L		 3920 if (i.suffix == BYTE_MNEM_SUFFIX)
3921 {
3922 temp.bitfield.imm8 = overlap.bitfield.imm8;
3923 temp.bitfield.imm8s = overlap.bitfield.imm8s;
3924 }
3925 else if (i.suffix == WORD_MNEM_SUFFIX)
3926 temp.bitfield.imm16 = overlap.bitfield.imm16;
3927 else if (i.suffix == QWORD_MNEM_SUFFIX)
3928 {
3929 temp.bitfield.imm64 = overlap.bitfield.imm64;
3930 temp.bitfield.imm32s = overlap.bitfield.imm32s;
3931 }
3932 else
3933 temp.bitfield.imm32 = overlap.bitfield.imm32;
3934 overlap = temp;
29b0f896 3935 }
c6fb90c8
L		 3936 else if (UINTS_EQUAL (overlap, imm16_32_32s)
3937 || UINTS_EQUAL (overlap, imm16_32)
3938 || UINTS_EQUAL (overlap, imm16_32s))
29b0f896 3939 {
c6fb90c8 3940 UINTS_CLEAR (overlap);
40fb9820
L		 3941 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3942 overlap.bitfield.imm16 = 1;
3943 else
3944 overlap.bitfield.imm32s = 1;
29b0f896 3945 }
c6fb90c8
L		 3946 if (!UINTS_EQUAL (overlap, imm8)
3947 && !UINTS_EQUAL (overlap, imm8s)
3948 && !UINTS_EQUAL (overlap, imm16)
3949 && !UINTS_EQUAL (overlap, imm32)
3950 && !UINTS_EQUAL (overlap, imm32s)
3951 && !UINTS_EQUAL (overlap, imm64))
29b0f896 3952 {
4eed87de
AM		 3953 as_bad (_("no instruction mnemonic suffix given; "
3954 "can't determine immediate size"));
29b0f896
AM		 3955 return 0;
3956 }
3957 }
40fb9820 3958 i.types[j] = overlap;
29b0f896 3959
40fb9820
L		 3960 return 1;
3961}
3962
3963static int
3964finalize_imm (void)
3965{
3966 unsigned int j;
29b0f896 3967
40fb9820
L		 3968 for (j = 0; j < 2; j++)
3969 if (update_imm (j) == 0)
3970 return 0;
3971
c6fb90c8 3972 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 3973 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 3974
3975 return 1;
3976}
3977
85f10a01
MM		 3978static void
3979process_drex (void)
3980{
5dd15031
JJ		 3981 i.drex.modrm_reg = 0;
3982 i.drex.modrm_regmem = 0;
85f10a01
MM		 3983
3984 /* SSE5 4 operand instructions must have the destination the same as
3985 one of the inputs. Figure out the destination register and cache
3986 it away in the drex field, and remember which fields to use for
3987 the modrm byte. */
3988 if (i.tm.opcode_modifier.drex
3989 && i.tm.opcode_modifier.drexv
3990 && i.operands == 4)
3991 {
3992 i.tm.extension_opcode = None;
3993
3994 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
3995 if (i.types[0].bitfield.regxmm != 0
3996 && i.types[1].bitfield.regxmm != 0
3997 && i.types[2].bitfield.regxmm != 0
3998 && i.types[3].bitfield.regxmm != 0
3999 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4000 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4001 {
4002 /* Clear the arguments that are stored in drex. */
4003 UINTS_CLEAR (i.types[0]);
4004 UINTS_CLEAR (i.types[3]);
4005 i.reg_operands -= 2;
4006
4007 /* There are two different ways to encode a 4 operand
4008 instruction with all registers that uses OC1 set to
4009 0 or 1. Favor setting OC1 to 0 since this mimics the
4010 actions of other SSE5 assemblers. Use modrm encoding 2
4011 for register/register. Include the high order bit that
4012 is normally stored in the REX byte in the register
4013 field. */
4014 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4015 i.drex.modrm_reg = 2;
4016 i.drex.modrm_regmem = 1;
4017 i.drex.reg = (i.op[3].regs->reg_num
4018 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4019 }
4020
4021 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4022 else if (i.types[0].bitfield.regxmm != 0
4023 && i.types[1].bitfield.regxmm != 0
4024 && (i.types[2].bitfield.regxmm
4025 || operand_type_check (i.types[2], anymem))
4026 && i.types[3].bitfield.regxmm != 0
4027 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4028 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4029 {
4030 /* clear the arguments that are stored in drex */
4031 UINTS_CLEAR (i.types[0]);
4032 UINTS_CLEAR (i.types[3]);
4033 i.reg_operands -= 2;
4034
4035 /* Specify the modrm encoding for memory addressing. Include
4036 the high order bit that is normally stored in the REX byte
4037 in the register field. */
4038 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4039 i.drex.modrm_reg = 1;
4040 i.drex.modrm_regmem = 2;
4041 i.drex.reg = (i.op[3].regs->reg_num
4042 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4043 }
4044
4045 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4046 else if (i.types[0].bitfield.regxmm != 0
4047 && operand_type_check (i.types[1], anymem) != 0
4048 && i.types[2].bitfield.regxmm != 0
4049 && i.types[3].bitfield.regxmm != 0
4050 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4051 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4052 {
4053 /* Clear the arguments that are stored in drex. */
4054 UINTS_CLEAR (i.types[0]);
4055 UINTS_CLEAR (i.types[3]);
4056 i.reg_operands -= 2;
4057
4058 /* Specify the modrm encoding for memory addressing. Include
4059 the high order bit that is normally stored in the REX byte
4060 in the register field. */
4061 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4062 i.drex.modrm_reg = 2;
4063 i.drex.modrm_regmem = 1;
4064 i.drex.reg = (i.op[3].regs->reg_num
4065 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4066 }
4067
4068 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4069 else if (i.types[0].bitfield.regxmm != 0
4070 && i.types[1].bitfield.regxmm != 0
4071 && i.types[2].bitfield.regxmm != 0
4072 && i.types[3].bitfield.regxmm != 0
4073 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4074 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4075 {
4076 /* clear the arguments that are stored in drex */
4077 UINTS_CLEAR (i.types[2]);
4078 UINTS_CLEAR (i.types[3]);
4079 i.reg_operands -= 2;
4080
4081 /* There are two different ways to encode a 4 operand
4082 instruction with all registers that uses OC1 set to
4083 0 or 1. Favor setting OC1 to 0 since this mimics the
4084 actions of other SSE5 assemblers. Use modrm encoding
4085 2 for register/register. Include the high order bit that
4086 is normally stored in the REX byte in the register
4087 field. */
4088 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4089 i.drex.modrm_reg = 1;
4090 i.drex.modrm_regmem = 0;
4091
4092 /* Remember the register, including the upper bits */
4093 i.drex.reg = (i.op[3].regs->reg_num
4094 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4095 }
4096
4097 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4098 else if (i.types[0].bitfield.regxmm != 0
4099 && (i.types[1].bitfield.regxmm
4100 || operand_type_check (i.types[1], anymem))
4101 && i.types[2].bitfield.regxmm != 0
4102 && i.types[3].bitfield.regxmm != 0
4103 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4104 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4105 {
4106 /* Clear the arguments that are stored in drex. */
4107 UINTS_CLEAR (i.types[2]);
4108 UINTS_CLEAR (i.types[3]);
4109 i.reg_operands -= 2;
4110
4111 /* Specify the modrm encoding and remember the register
4112 including the bits normally stored in the REX byte. */
4113 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4114 i.drex.modrm_reg = 0;
4115 i.drex.modrm_regmem = 1;
4116 i.drex.reg = (i.op[3].regs->reg_num
4117 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4118 }
4119
4120 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4121 else if (operand_type_check (i.types[0], anymem) != 0
4122 && i.types[1].bitfield.regxmm != 0
4123 && i.types[2].bitfield.regxmm != 0
4124 && i.types[3].bitfield.regxmm != 0
4125 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4126 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4127 {
4128 /* clear the arguments that are stored in drex */
4129 UINTS_CLEAR (i.types[2]);
4130 UINTS_CLEAR (i.types[3]);
4131 i.reg_operands -= 2;
4132
4133 /* Specify the modrm encoding and remember the register
4134 including the bits normally stored in the REX byte. */
4135 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4136 i.drex.modrm_reg = 1;
4137 i.drex.modrm_regmem = 0;
4138 i.drex.reg = (i.op[3].regs->reg_num
4139 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4140 }
4141
4142 else
4143 as_bad (_("Incorrect operands for the '%s' instruction"),
4144 i.tm.name);
4145 }
4146
4147 /* SSE5 instructions with the DREX byte where the only memory operand
4148 is in the 2nd argument, and the first and last xmm register must
4149 match, and is encoded in the DREX byte. */
4150 else if (i.tm.opcode_modifier.drex
4151 && !i.tm.opcode_modifier.drexv
4152 && i.operands == 4)
4153 {
4154 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4155 if (i.types[0].bitfield.regxmm != 0
4156 && (i.types[1].bitfield.regxmm
4157 || operand_type_check(i.types[1], anymem))
4158 && i.types[2].bitfield.regxmm != 0
4159 && i.types[3].bitfield.regxmm != 0
4160 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4161 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4162 {
4163 /* clear the arguments that are stored in drex */
4164 UINTS_CLEAR (i.types[0]);
4165 UINTS_CLEAR (i.types[3]);
4166 i.reg_operands -= 2;
4167
4168 /* Specify the modrm encoding and remember the register
4169 including the high bit normally stored in the REX
4170 byte. */
4171 i.drex.modrm_reg = 2;
4172 i.drex.modrm_regmem = 1;
4173 i.drex.reg = (i.op[3].regs->reg_num
4174 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4175 }
4176
4177 else
4178 as_bad (_("Incorrect operands for the '%s' instruction"),
4179 i.tm.name);
4180 }
4181
4182 /* SSE5 3 operand instructions that the result is a register, being
4183 either operand can be a memory operand, using OC0 to note which
4184 one is the memory. */
4185 else if (i.tm.opcode_modifier.drex
4186 && i.tm.opcode_modifier.drexv
4187 && i.operands == 3)
4188 {
4189 i.tm.extension_opcode = None;
4190
4191 /* Case 1: 3 operand insn, src1 = register. */
4192 if (i.types[0].bitfield.regxmm != 0
4193 && i.types[1].bitfield.regxmm != 0
4194 && i.types[2].bitfield.regxmm != 0)
4195 {
4196 /* Clear the arguments that are stored in drex. */
4197 UINTS_CLEAR (i.types[2]);
4198 i.reg_operands--;
4199
4200 /* Specify the modrm encoding and remember the register
4201 including the high bit normally stored in the REX byte. */
4202 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4203 i.drex.modrm_reg = 1;
4204 i.drex.modrm_regmem = 0;
4205 i.drex.reg = (i.op[2].regs->reg_num
4206 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4207 }
4208
4209 /* Case 2: 3 operand insn, src1 = memory. */
4210 else if (operand_type_check (i.types[0], anymem) != 0
4211 && i.types[1].bitfield.regxmm != 0
4212 && i.types[2].bitfield.regxmm != 0)
4213 {
4214 /* Clear the arguments that are stored in drex. */
4215 UINTS_CLEAR (i.types[2]);
4216 i.reg_operands--;
4217
4218 /* Specify the modrm encoding and remember the register
4219 including the high bit normally stored in the REX
4220 byte. */
4221 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4222 i.drex.modrm_reg = 1;
4223 i.drex.modrm_regmem = 0;
4224 i.drex.reg = (i.op[2].regs->reg_num
4225 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4226 }
4227
4228 /* Case 3: 3 operand insn, src2 = memory. */
4229 else if (i.types[0].bitfield.regxmm != 0
4230 && operand_type_check (i.types[1], anymem) != 0
4231 && i.types[2].bitfield.regxmm != 0)
4232 {
4233 /* Clear the arguments that are stored in drex. */
4234 UINTS_CLEAR (i.types[2]);
4235 i.reg_operands--;
4236
4237 /* Specify the modrm encoding and remember the register
4238 including the high bit normally stored in the REX byte. */
4239 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4240 i.drex.modrm_reg = 0;
4241 i.drex.modrm_regmem = 1;
4242 i.drex.reg = (i.op[2].regs->reg_num
4243 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4244 }
4245
4246 else
4247 as_bad (_("Incorrect operands for the '%s' instruction"),
4248 i.tm.name);
4249 }
4250
4251 /* SSE5 4 operand instructions that are the comparison instructions
4252 where the first operand is the immediate value of the comparison
4253 to be done. */
4254 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4255 {
4256 /* Case 1: 4 operand insn, src1 = reg/memory. */
4257 if (operand_type_check (i.types[0], imm) != 0
4258 && (i.types[1].bitfield.regxmm
4259 || operand_type_check (i.types[1], anymem))
4260 && i.types[2].bitfield.regxmm != 0
4261 && i.types[3].bitfield.regxmm != 0)
4262 {
4263 /* clear the arguments that are stored in drex */
4264 UINTS_CLEAR (i.types[3]);
4265 i.reg_operands--;
4266
4267 /* Specify the modrm encoding and remember the register
4268 including the high bit normally stored in the REX byte. */
4269 i.drex.modrm_reg = 2;
4270 i.drex.modrm_regmem = 1;
4271 i.drex.reg = (i.op[3].regs->reg_num
4272 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4273 }
4274
4275 /* Case 2: 3 operand insn with ImmExt that places the
4276 opcode_extension as an immediate argument. This is used for
4277 all of the varients of comparison that supplies the appropriate
4278 value as part of the instruction. */
4279 else if ((i.types[0].bitfield.regxmm
4280 || operand_type_check (i.types[0], anymem))
4281 && i.types[1].bitfield.regxmm != 0
4282 && i.types[2].bitfield.regxmm != 0
4283 && operand_type_check (i.types[3], imm) != 0)
4284 {
4285 /* clear the arguments that are stored in drex */
4286 UINTS_CLEAR (i.types[2]);
4287 i.reg_operands--;
4288
4289 /* Specify the modrm encoding and remember the register
4290 including the high bit normally stored in the REX byte. */
4291 i.drex.modrm_reg = 1;
4292 i.drex.modrm_regmem = 0;
4293 i.drex.reg = (i.op[2].regs->reg_num
4294 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4295 }
4296
4297 else
4298 as_bad (_("Incorrect operands for the '%s' instruction"),
4299 i.tm.name);
4300 }
4301
4302 else if (i.tm.opcode_modifier.drex
4303 || i.tm.opcode_modifier.drexv
4304 || i.tm.opcode_modifier.drexc)
4305 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4306}
4307
29b0f896 4308static int
e3bb37b5 4309process_operands (void)
29b0f896
AM		 4310{
4311 /* Default segment register this instruction will use for memory
4312 accesses. 0 means unknown. This is only for optimizing out
4313 unnecessary segment overrides. */
4314 const seg_entry *default_seg = 0;
4315
85f10a01
MM		 4316 /* Handle all of the DREX munging that SSE5 needs. */
4317 if (i.tm.opcode_modifier.drex
4318 || i.tm.opcode_modifier.drexv
4319 || i.tm.opcode_modifier.drexc)
4320 process_drex ();
4321
e2ec9d29 4322 if (i.tm.opcode_modifier.firstxmm0)
29b0f896 4323 {
9fcfb3d7
L		 4324 unsigned int j;
4325
e2ec9d29
L		 4326 /* The first operand is implicit and must be xmm0. */
4327 assert (i.reg_operands && UINTS_EQUAL (i.types[0], regxmm));
4328 if (i.op[0].regs->reg_num != 0)
4329 {
4330 if (intel_syntax)
4331 as_bad (_("the last operand of `%s' must be `%sxmm0'"),
4332 i.tm.name, register_prefix);
4333 else
4334 as_bad (_("the first operand of `%s' must be `%sxmm0'"),
4335 i.tm.name, register_prefix);
4336 return 0;
4337 }
9fcfb3d7
L		 4338
4339 for (j = 1; j < i.operands; j++)
4340 {
4341 i.op[j - 1] = i.op[j];
4342 i.types[j - 1] = i.types[j];
4343
4344 /* We need to adjust fields in i.tm since they are used by
4345 build_modrm_byte. */
4346 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4347 }
4348
e2ec9d29
L		 4349 i.operands--;
4350 i.reg_operands--;
e2ec9d29
L		 4351 i.tm.operands--;
4352 }
4353 else if (i.tm.opcode_modifier.regkludge)
4354 {
4355 /* The imul $imm, %reg instruction is converted into
4356 imul $imm, %reg, %reg, and the clr %reg instruction
4357 is converted into xor %reg, %reg. */
4358
4359 unsigned int first_reg_op;
4360
4361 if (operand_type_check (i.types[0], reg))
4362 first_reg_op = 0;
4363 else
4364 first_reg_op = 1;
4365 /* Pretend we saw the extra register operand. */
4366 assert (i.reg_operands == 1
4367 && i.op[first_reg_op + 1].regs == 0);
4368 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
4369 i.types[first_reg_op + 1] = i.types[first_reg_op];
4370 i.operands++;
4371 i.reg_operands++;
29b0f896
AM		 4372 }
4373
40fb9820 4374 if (i.tm.opcode_modifier.shortform)
29b0f896 4375 {
40fb9820
L		 4376 if (i.types[0].bitfield.sreg2
4377 || i.types[0].bitfield.sreg3)
29b0f896 4378 {
4eed87de
AM		 4379 if (i.tm.base_opcode == POP_SEG_SHORT
4380 && i.op[0].regs->reg_num == 1)
29b0f896 4381 {
4eed87de
AM		 4382 as_bad (_("you can't `pop %%cs'"));
4383 return 0;
29b0f896 4384 }
4eed87de
AM		 4385 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
4386 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 4387 i.rex |= REX_B;
4eed87de
AM		 4388 }
4389 else
4390 {
85f10a01
MM		 4391 /* The register or float register operand is in operand
4392 0 or 1. */
40fb9820
L		 4393 unsigned int op;
4394
4395 if (i.types[0].bitfield.floatreg
4396 || operand_type_check (i.types[0], reg))
4397 op = 0;
4398 else
4399 op = 1;
4eed87de
AM		 4400 /* Register goes in low 3 bits of opcode. */
4401 i.tm.base_opcode |= i.op[op].regs->reg_num;
4402 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 4403 i.rex |= REX_B;
40fb9820 4404 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 4405 {
4eed87de
AM		 4406 /* Warn about some common errors, but press on regardless.
4407 The first case can be generated by gcc (<= 2.8.1). */
4408 if (i.operands == 2)
4409 {
4410 /* Reversed arguments on faddp, fsubp, etc. */
a540244d
L		 4411 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
4412 register_prefix, i.op[1].regs->reg_name,
4413 register_prefix, i.op[0].regs->reg_name);
4eed87de
AM		 4414 }
4415 else
4416 {
4417 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 4418 as_warn (_("translating to `%s %s%s'"), i.tm.name,
4419 register_prefix, i.op[0].regs->reg_name);
4eed87de 4420 }
29b0f896
AM		 4421 }
4422 }
4423 }
40fb9820 4424 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 4425 {
4426 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 4427 must be put into the modrm byte). Now, we make the modrm and
4428 index base bytes based on all the info we've collected. */
29b0f896
AM		 4429
4430 default_seg = build_modrm_byte ();
4431 }
8a2ed489 4432 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 4433 {
4434 default_seg = &ds;
4435 }
40fb9820 4436 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 4437 {
4438 /* For the string instructions that allow a segment override
4439 on one of their operands, the default segment is ds. */
4440 default_seg = &ds;
4441 }
4442
75178d9d
L		 4443 if (i.tm.base_opcode == 0x8d /* lea */
4444 && i.seg[0]
4445 && !quiet_warnings)
30123838 4446 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 4447
4448 /* If a segment was explicitly specified, and the specified segment
4449 is not the default, use an opcode prefix to select it. If we
4450 never figured out what the default segment is, then default_seg
4451 will be zero at this point, and the specified segment prefix will
4452 always be used. */
29b0f896
AM		 4453 if ((i.seg[0]) && (i.seg[0] != default_seg))
4454 {
4455 if (!add_prefix (i.seg[0]->seg_prefix))
4456 return 0;
4457 }
4458 return 1;
4459}
4460
4461static const seg_entry *
e3bb37b5 4462build_modrm_byte (void)
29b0f896
AM		 4463{
4464 const seg_entry *default_seg = 0;
4465
85f10a01
MM		 4466 /* SSE5 4 operand instructions are encoded in such a way that one of
4467 the inputs must match the destination register. Process_drex hides
4468 the 3rd argument in the drex field, so that by the time we get
4469 here, it looks to GAS as if this is a 2 operand instruction. */
4470 if ((i.tm.opcode_modifier.drex
4471 || i.tm.opcode_modifier.drexv
b5016f89 4472 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4473 && i.reg_operands == 2)
4474 {
4475 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
4476 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
4477
4478 i.rm.reg = reg->reg_num;
4479 i.rm.regmem = regmem->reg_num;
4480 i.rm.mode = 3;
4481 if ((reg->reg_flags & RegRex) != 0)
4482 i.rex |= REX_R;
4483 if ((regmem->reg_flags & RegRex) != 0)
4484 i.rex |= REX_B;
4485 }
4486
29b0f896
AM		 4487 /* i.reg_operands MUST be the number of real register operands;
4488 implicit registers do not count. */
85f10a01 4489 else if (i.reg_operands == 2)
29b0f896
AM		 4490 {
4491 unsigned int source, dest;
cab737b9
L		 4492
4493 switch (i.operands)
4494 {
4495 case 2:
4496 source = 0;
4497 break;
4498 case 3:
c81128dc
L		 4499 /* When there are 3 operands, one of them may be immediate,
4500 which may be the first or the last operand. Otherwise,
4501 the first operand must be shift count register (cl). */
4502 assert (i.imm_operands == 1
4503 || (i.imm_operands == 0
40fb9820
L		 4504 && i.types[0].bitfield.shiftcount));
4505 if (operand_type_check (i.types[0], imm)
4506 || i.types[0].bitfield.shiftcount)
4507 source = 1;
4508 else
4509 source = 0;
cab737b9
L		 4510 break;
4511 case 4:
368d64cc
L		 4512 /* When there are 4 operands, the first two must be 8bit
4513 immediate operands. The source operand will be the 3rd
4514 one. */
cab737b9 4515 assert (i.imm_operands == 2
368d64cc
L		 4516 && i.types[0].bitfield.imm8
4517 && i.types[1].bitfield.imm8);
cab737b9
L		 4518 source = 2;
4519 break;
4520 default:
4521 abort ();
4522 }
4523
29b0f896
AM		 4524 dest = source + 1;
4525
4526 i.rm.mode = 3;
4527 /* One of the register operands will be encoded in the i.tm.reg
4528 field, the other in the combined i.tm.mode and i.tm.regmem
4529 fields. If no form of this instruction supports a memory
4530 destination operand, then we assume the source operand may
4531 sometimes be a memory operand and so we need to store the
4532 destination in the i.rm.reg field. */
40fb9820
L		 4533 if (!i.tm.operand_types[dest].bitfield.regmem
4534 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 4535 {
4536 i.rm.reg = i.op[dest].regs->reg_num;
4537 i.rm.regmem = i.op[source].regs->reg_num;
4538 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4539 i.rex |= REX_R;
29b0f896 4540 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4541 i.rex |= REX_B;
29b0f896
AM		 4542 }
4543 else
4544 {
4545 i.rm.reg = i.op[source].regs->reg_num;
4546 i.rm.regmem = i.op[dest].regs->reg_num;
4547 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 4548 i.rex |= REX_B;
29b0f896 4549 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 4550 i.rex |= REX_R;
29b0f896 4551 }
161a04f6 4552 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 4553 {
40fb9820
L		 4554 if (!i.types[0].bitfield.control
4555 && !i.types[1].bitfield.control)
c4a530c5 4556 abort ();
161a04f6 4557 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 4558 add_prefix (LOCK_PREFIX_OPCODE);
4559 }
29b0f896
AM		 4560 }
4561 else
4562 { /* If it's not 2 reg operands... */
4563 if (i.mem_operands)
4564 {
4565 unsigned int fake_zero_displacement = 0;
99018f42 4566 unsigned int op;
4eed87de 4567
85f10a01
MM		 4568 /* This has been precalculated for SSE5 instructions
4569 that have a DREX field earlier in process_drex. */
b5016f89
L		 4570 if (i.tm.opcode_modifier.drex
4571 || i.tm.opcode_modifier.drexv
4572 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4573 op = i.drex.modrm_regmem;
4574 else
4575 {
c0209578
L		 4576 for (op = 0; op < i.operands; op++)
4577 if (operand_type_check (i.types[op], anymem))
4578 break;
4579 assert (op < i.operands);
85f10a01 4580 }
29b0f896
AM		 4581
4582 default_seg = &ds;
4583
4584 if (i.base_reg == 0)
4585 {
4586 i.rm.mode = 0;
4587 if (!i.disp_operands)
4588 fake_zero_displacement = 1;
4589 if (i.index_reg == 0)
4590 {
4591 /* Operand is just <disp> */
20f0a1fc 4592 if (flag_code == CODE_64BIT)
29b0f896
AM		 4593 {
4594 /* 64bit mode overwrites the 32bit absolute
4595 addressing by RIP relative addressing and
4596 absolute addressing is encoded by one of the
4597 redundant SIB forms. */
4598 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4599 i.sib.base = NO_BASE_REGISTER;
4600 i.sib.index = NO_INDEX_REGISTER;
fc225355 4601 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 4602 ? disp32s : disp32);
20f0a1fc 4603 }
fc225355
L		 4604 else if ((flag_code == CODE_16BIT)
4605 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 4606 {
4607 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 4608 i.types[op] = disp16;
20f0a1fc
NC		 4609 }
4610 else
4611 {
4612 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 4613 i.types[op] = disp32;
29b0f896
AM		 4614 }
4615 }
4616 else /* !i.base_reg && i.index_reg */
4617 {
db51cc60
L		 4618 if (i.index_reg->reg_num == RegEiz
4619 || i.index_reg->reg_num == RegRiz)
4620 i.sib.index = NO_INDEX_REGISTER;
4621 else
4622 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4623 i.sib.base = NO_BASE_REGISTER;
4624 i.sib.scale = i.log2_scale_factor;
4625 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 4626 i.types[op].bitfield.disp8 = 0;
4627 i.types[op].bitfield.disp16 = 0;
4628 i.types[op].bitfield.disp64 = 0;
29b0f896 4629 if (flag_code != CODE_64BIT)
40fb9820
L		 4630 {
4631 /* Must be 32 bit */
4632 i.types[op].bitfield.disp32 = 1;
4633 i.types[op].bitfield.disp32s = 0;
4634 }
29b0f896 4635 else
40fb9820
L		 4636 {
4637 i.types[op].bitfield.disp32 = 0;
4638 i.types[op].bitfield.disp32s = 1;
4639 }
29b0f896 4640 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4641 i.rex |= REX_X;
29b0f896
AM		 4642 }
4643 }
4644 /* RIP addressing for 64bit mode. */
9a04903e
JB		 4645 else if (i.base_reg->reg_num == RegRip ||
4646 i.base_reg->reg_num == RegEip)
29b0f896
AM		 4647 {
4648 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 4649 i.types[op].bitfield.disp8 = 0;
4650 i.types[op].bitfield.disp16 = 0;
4651 i.types[op].bitfield.disp32 = 0;
4652 i.types[op].bitfield.disp32s = 1;
4653 i.types[op].bitfield.disp64 = 0;
71903a11 4654 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 4655 if (! i.disp_operands)
4656 fake_zero_displacement = 1;
29b0f896 4657 }
40fb9820 4658 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 4659 {
4660 switch (i.base_reg->reg_num)
4661 {
4662 case 3: /* (%bx) */
4663 if (i.index_reg == 0)
4664 i.rm.regmem = 7;
4665 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
4666 i.rm.regmem = i.index_reg->reg_num - 6;
4667 break;
4668 case 5: /* (%bp) */
4669 default_seg = &ss;
4670 if (i.index_reg == 0)
4671 {
4672 i.rm.regmem = 6;
40fb9820 4673 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 4674 {
4675 /* fake (%bp) into 0(%bp) */
40fb9820 4676 i.types[op].bitfield.disp8 = 1;
252b5132 4677 fake_zero_displacement = 1;
29b0f896
AM		 4678 }
4679 }
4680 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
4681 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
4682 break;
4683 default: /* (%si) -> 4 or (%di) -> 5 */
4684 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
4685 }
4686 i.rm.mode = mode_from_disp_size (i.types[op]);
4687 }
4688 else /* i.base_reg and 32/64 bit mode */
4689 {
4690 if (flag_code == CODE_64BIT
40fb9820
L		 4691 && operand_type_check (i.types[op], disp))
4692 {
4693 i386_operand_type temp;
c6fb90c8 4694 UINTS_CLEAR (temp);
40fb9820
L		 4695 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
4696 i.types[op] = temp;
4697 if (i.prefix[ADDR_PREFIX] == 0)
4698 i.types[op].bitfield.disp32s = 1;
4699 else
4700 i.types[op].bitfield.disp32 = 1;
4701 }
20f0a1fc 4702
29b0f896
AM		 4703 i.rm.regmem = i.base_reg->reg_num;
4704 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 4705 i.rex |= REX_B;
29b0f896
AM		 4706 i.sib.base = i.base_reg->reg_num;
4707 /* x86-64 ignores REX prefix bit here to avoid decoder
4708 complications. */
4709 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
4710 {
4711 default_seg = &ss;
4712 if (i.disp_operands == 0)
4713 {
4714 fake_zero_displacement = 1;
40fb9820 4715 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 4716 }
4717 }
4718 else if (i.base_reg->reg_num == ESP_REG_NUM)
4719 {
4720 default_seg = &ss;
4721 }
4722 i.sib.scale = i.log2_scale_factor;
4723 if (i.index_reg == 0)
4724 {
4725 /* <disp>(%esp) becomes two byte modrm with no index
4726 register. We've already stored the code for esp
4727 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
4728 Any base register besides %esp will not use the
4729 extra modrm byte. */
4730 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 4731 }
4732 else
4733 {
db51cc60
L		 4734 if (i.index_reg->reg_num == RegEiz
4735 || i.index_reg->reg_num == RegRiz)
4736 i.sib.index = NO_INDEX_REGISTER;
4737 else
4738 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 4739 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
4740 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 4741 i.rex |= REX_X;
29b0f896 4742 }
67a4f2b7
AO		 4743
4744 if (i.disp_operands
4745 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4746 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
4747 i.rm.mode = 0;
4748 else
4749 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 4750 }
252b5132 4751
29b0f896
AM		 4752 if (fake_zero_displacement)
4753 {
4754 /* Fakes a zero displacement assuming that i.types[op]
4755 holds the correct displacement size. */
4756 expressionS *exp;
4757
4758 assert (i.op[op].disps == 0);
4759 exp = &disp_expressions[i.disp_operands++];
4760 i.op[op].disps = exp;
4761 exp->X_op = O_constant;
4762 exp->X_add_number = 0;
4763 exp->X_add_symbol = (symbolS *) 0;
4764 exp->X_op_symbol = (symbolS *) 0;
4765 }
4766 }
252b5132 4767
29b0f896
AM		 4768 /* Fill in i.rm.reg or i.rm.regmem field with register operand
4769 (if any) based on i.tm.extension_opcode. Again, we must be
4770 careful to make sure that segment/control/debug/test/MMX
4771 registers are coded into the i.rm.reg field. */
4772 if (i.reg_operands)
4773 {
99018f42
L		 4774 unsigned int op;
4775
85f10a01
MM		 4776 /* This has been precalculated for SSE5 instructions
4777 that have a DREX field earlier in process_drex. */
b5016f89
L		 4778 if (i.tm.opcode_modifier.drex
4779 || i.tm.opcode_modifier.drexv
4780 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 4781 {
4782 op = i.drex.modrm_reg;
4783 i.rm.reg = i.op[op].regs->reg_num;
4784 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4785 i.rex |= REX_R;
4786 }
4787 else
4788 {
c0209578
L		 4789 for (op = 0; op < i.operands; op++)
4790 if (i.types[op].bitfield.reg8
4791 || i.types[op].bitfield.reg16
4792 || i.types[op].bitfield.reg32
4793 || i.types[op].bitfield.reg64
4794 || i.types[op].bitfield.regmmx
4795 || i.types[op].bitfield.regxmm
4796 || i.types[op].bitfield.sreg2
4797 || i.types[op].bitfield.sreg3
4798 || i.types[op].bitfield.control
4799 || i.types[op].bitfield.debug
4800 || i.types[op].bitfield.test)
4801 break;
4802
4803 assert (op < i.operands);
99018f42 4804
85f10a01
MM		 4805 /* If there is an extension opcode to put here, the
4806 register number must be put into the regmem field. */
c0209578
L		 4807 if (i.tm.extension_opcode != None)
4808 {
4809 i.rm.regmem = i.op[op].regs->reg_num;
4810 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4811 i.rex |= REX_B;
4812 }
4813 else
4814 {
4815 i.rm.reg = i.op[op].regs->reg_num;
4816 if ((i.op[op].regs->reg_flags & RegRex) != 0)
4817 i.rex |= REX_R;
4818 }
85f10a01 4819 }
252b5132 4820
29b0f896
AM		 4821 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
4822 must set it to 3 to indicate this is a register operand
4823 in the regmem field. */
4824 if (!i.mem_operands)
4825 i.rm.mode = 3;
4826 }
252b5132 4827
29b0f896 4828 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 4829 if (i.tm.extension_opcode != None
4830 && !(i.tm.opcode_modifier.drex
4831 || i.tm.opcode_modifier.drexv
4832 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 4833 i.rm.reg = i.tm.extension_opcode;
4834 }
4835 return default_seg;
4836}
252b5132 4837
29b0f896 4838static void
e3bb37b5 4839output_branch (void)
29b0f896
AM		 4840{
4841 char *p;
4842 int code16;
4843 int prefix;
4844 relax_substateT subtype;
4845 symbolS *sym;
4846 offsetT off;
4847
4848 code16 = 0;
4849 if (flag_code == CODE_16BIT)
4850 code16 = CODE16;
4851
4852 prefix = 0;
4853 if (i.prefix[DATA_PREFIX] != 0)
252b5132 4854 {
29b0f896
AM		 4855 prefix = 1;
4856 i.prefixes -= 1;
4857 code16 ^= CODE16;
252b5132 4858 }
29b0f896
AM		 4859 /* Pentium4 branch hints. */
4860 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4861 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 4862 {
29b0f896
AM		 4863 prefix++;
4864 i.prefixes--;
4865 }
4866 if (i.prefix[REX_PREFIX] != 0)
4867 {
4868 prefix++;
4869 i.prefixes--;
2f66722d
AM		 4870 }
4871
29b0f896
AM		 4872 if (i.prefixes != 0 && !intel_syntax)
4873 as_warn (_("skipping prefixes on this instruction"));
4874
4875 /* It's always a symbol; End frag & setup for relax.
4876 Make sure there is enough room in this frag for the largest
4877 instruction we may generate in md_convert_frag. This is 2
4878 bytes for the opcode and room for the prefix and largest
4879 displacement. */
4880 frag_grow (prefix + 2 + 4);
4881 /* Prefix and 1 opcode byte go in fr_fix. */
4882 p = frag_more (prefix + 1);
4883 if (i.prefix[DATA_PREFIX] != 0)
4884 *p++ = DATA_PREFIX_OPCODE;
4885 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
4886 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
4887 *p++ = i.prefix[SEG_PREFIX];
4888 if (i.prefix[REX_PREFIX] != 0)
4889 *p++ = i.prefix[REX_PREFIX];
4890 *p = i.tm.base_opcode;
4891
4892 if ((unsigned char) *p == JUMP_PC_RELATIVE)
4893 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 4894 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 4895 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
4896 else
4897 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
4898 subtype |= code16;
3e73aa7c 4899
29b0f896
AM		 4900 sym = i.op[0].disps->X_add_symbol;
4901 off = i.op[0].disps->X_add_number;
3e73aa7c 4902
29b0f896
AM		 4903 if (i.op[0].disps->X_op != O_constant
4904 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 4905 {
29b0f896
AM		 4906 /* Handle complex expressions. */
4907 sym = make_expr_symbol (i.op[0].disps);
4908 off = 0;
4909 }
3e73aa7c 4910
29b0f896
AM		 4911 /* 1 possible extra opcode + 4 byte displacement go in var part.
4912 Pass reloc in fr_var. */
4913 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
4914}
3e73aa7c 4915
29b0f896 4916static void
e3bb37b5 4917output_jump (void)
29b0f896
AM		 4918{
4919 char *p;
4920 int size;
3e02c1cc 4921 fixS *fixP;
29b0f896 4922
40fb9820 4923 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 4924 {
4925 /* This is a loop or jecxz type instruction. */
4926 size = 1;
4927 if (i.prefix[ADDR_PREFIX] != 0)
4928 {
4929 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
4930 i.prefixes -= 1;
4931 }
4932 /* Pentium4 branch hints. */
4933 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
4934 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
4935 {
4936 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
4937 i.prefixes--;
3e73aa7c
JH		 4938 }
4939 }
29b0f896
AM		 4940 else
4941 {
4942 int code16;
3e73aa7c 4943
29b0f896
AM		 4944 code16 = 0;
4945 if (flag_code == CODE_16BIT)
4946 code16 = CODE16;
3e73aa7c 4947
29b0f896
AM		 4948 if (i.prefix[DATA_PREFIX] != 0)
4949 {
4950 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
4951 i.prefixes -= 1;
4952 code16 ^= CODE16;
4953 }
252b5132 4954
29b0f896
AM		 4955 size = 4;
4956 if (code16)
4957 size = 2;
4958 }
9fcc94b6 4959
29b0f896
AM		 4960 if (i.prefix[REX_PREFIX] != 0)
4961 {
4962 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
4963 i.prefixes -= 1;
4964 }
252b5132 4965
29b0f896
AM		 4966 if (i.prefixes != 0 && !intel_syntax)
4967 as_warn (_("skipping prefixes on this instruction"));
e0890092 4968
29b0f896
AM		 4969 p = frag_more (1 + size);
4970 *p++ = i.tm.base_opcode;
e0890092 4971
3e02c1cc
AM		 4972 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
4973 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
4974
4975 /* All jumps handled here are signed, but don't use a signed limit
4976 check for 32 and 16 bit jumps as we want to allow wrap around at
4977 4G and 64k respectively. */
4978 if (size == 1)
4979 fixP->fx_signed = 1;
29b0f896 4980}
e0890092 4981
29b0f896 4982static void
e3bb37b5 4983output_interseg_jump (void)
29b0f896
AM		 4984{
4985 char *p;
4986 int size;
4987 int prefix;
4988 int code16;
252b5132 4989
29b0f896
AM		 4990 code16 = 0;
4991 if (flag_code == CODE_16BIT)
4992 code16 = CODE16;
a217f122 4993
29b0f896
AM		 4994 prefix = 0;
4995 if (i.prefix[DATA_PREFIX] != 0)
4996 {
4997 prefix = 1;
4998 i.prefixes -= 1;
4999 code16 ^= CODE16;
5000 }
5001 if (i.prefix[REX_PREFIX] != 0)
5002 {
5003 prefix++;
5004 i.prefixes -= 1;
5005 }
252b5132 5006
29b0f896
AM		 5007 size = 4;
5008 if (code16)
5009 size = 2;
252b5132 5010
29b0f896
AM		 5011 if (i.prefixes != 0 && !intel_syntax)
5012 as_warn (_("skipping prefixes on this instruction"));
252b5132 5013
29b0f896
AM		 5014 /* 1 opcode; 2 segment; offset */
5015 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5016
29b0f896
AM		 5017 if (i.prefix[DATA_PREFIX] != 0)
5018 *p++ = DATA_PREFIX_OPCODE;
252b5132 5019
29b0f896
AM		 5020 if (i.prefix[REX_PREFIX] != 0)
5021 *p++ = i.prefix[REX_PREFIX];
252b5132 5022
29b0f896
AM		 5023 *p++ = i.tm.base_opcode;
5024 if (i.op[1].imms->X_op == O_constant)
5025 {
5026 offsetT n = i.op[1].imms->X_add_number;
252b5132 5027
29b0f896
AM		 5028 if (size == 2
5029 && !fits_in_unsigned_word (n)
5030 && !fits_in_signed_word (n))
5031 {
5032 as_bad (_("16-bit jump out of range"));
5033 return;
5034 }
5035 md_number_to_chars (p, n, size);
5036 }
5037 else
5038 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5039 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5040 if (i.op[0].imms->X_op != O_constant)
5041 as_bad (_("can't handle non absolute segment in `%s'"),
5042 i.tm.name);
5043 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5044}
a217f122 5045
29b0f896 5046static void
e3bb37b5 5047output_insn (void)
29b0f896 5048{
2bbd9c25
JJ		 5049 fragS *insn_start_frag;
5050 offsetT insn_start_off;
5051
29b0f896
AM		 5052 /* Tie dwarf2 debug info to the address at the start of the insn.
5053 We can't do this after the insn has been output as the current
5054 frag may have been closed off. eg. by frag_var. */
5055 dwarf2_emit_insn (0);
5056
2bbd9c25
JJ		 5057 insn_start_frag = frag_now;
5058 insn_start_off = frag_now_fix ();
5059
29b0f896 5060 /* Output jumps. */
40fb9820 5061 if (i.tm.opcode_modifier.jump)
29b0f896 5062 output_branch ();
40fb9820
L		 5063 else if (i.tm.opcode_modifier.jumpbyte
5064 || i.tm.opcode_modifier.jumpdword)
29b0f896 5065 output_jump ();
40fb9820 5066 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5067 output_interseg_jump ();
5068 else
5069 {
5070 /* Output normal instructions here. */
5071 char *p;
5072 unsigned char *q;
47465058 5073 unsigned int j;
331d2d0d 5074 unsigned int prefix;
4dffcebc
L		 5075
5076 switch (i.tm.opcode_length)
bc4bd9ab 5077 {
4dffcebc 5078 case 3:
331d2d0d
L		 5079 if (i.tm.base_opcode & 0xff000000)
5080 {
5081 prefix = (i.tm.base_opcode >> 24) & 0xff;
5082 goto check_prefix;
5083 }
4dffcebc
L		 5084 break;
5085 case 2:
5086 if ((i.tm.base_opcode & 0xff0000) != 0)
bc4bd9ab 5087 {
4dffcebc
L		 5088 prefix = (i.tm.base_opcode >> 16) & 0xff;
5089 if (i.tm.cpu_flags.bitfield.cpupadlock)
5090 {
5091check_prefix:
5092 if (prefix != REPE_PREFIX_OPCODE
5093 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
5094 add_prefix (prefix);
5095 }
5096 else
bc4bd9ab
MK		 5097 add_prefix (prefix);
5098 }
4dffcebc
L		 5099 break;
5100 case 1:
5101 break;
5102 default:
5103 abort ();
0f10071e 5104 }
252b5132 5105
29b0f896 5106 /* The prefix bytes. */
47465058
L		 5107 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5108 if (*q)
5109 FRAG_APPEND_1_CHAR (*q);
252b5132 5110
29b0f896 5111 /* Now the opcode; be careful about word order here! */
4dffcebc 5112 if (i.tm.opcode_length == 1)
29b0f896
AM		 5113 {
5114 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5115 }
5116 else
5117 {
4dffcebc 5118 switch (i.tm.opcode_length)
331d2d0d 5119 {
4dffcebc 5120 case 3:
331d2d0d
L		 5121 p = frag_more (3);
5122 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5123 break;
5124 case 2:
5125 p = frag_more (2);
5126 break;
5127 default:
5128 abort ();
5129 break;
331d2d0d 5130 }
0f10071e 5131
29b0f896
AM		 5132 /* Put out high byte first: can't use md_number_to_chars! */
5133 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5134 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5135
5136 /* On SSE5, encode the OC1 bit in the DREX field if this
5137 encoding has multiple formats. */
5138 if (i.tm.opcode_modifier.drex
5139 && i.tm.opcode_modifier.drexv
5140 && DREX_OC1 (i.tm.extension_opcode))
5141 *p |= DREX_OC1_MASK;
29b0f896 5142 }
3e73aa7c 5143
29b0f896 5144 /* Now the modrm byte and sib byte (if present). */
40fb9820 5145 if (i.tm.opcode_modifier.modrm)
29b0f896 5146 {
4a3523fa
L		 5147 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5148 | i.rm.reg << 3
5149 | i.rm.mode << 6));
29b0f896
AM		 5150 /* If i.rm.regmem == ESP (4)
5151 && i.rm.mode != (Register mode)
5152 && not 16 bit
5153 ==> need second modrm byte. */
5154 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5155 && i.rm.mode != 3
40fb9820 5156 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5157 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5158 | i.sib.index << 3
5159 | i.sib.scale << 6));
29b0f896 5160 }
3e73aa7c 5161
85f10a01
MM		 5162 /* Write the DREX byte if needed. */
5163 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5164 {
5165 p = frag_more (1);
5166 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5167
5168 /* Encode the OC0 bit if this encoding has multiple
5169 formats. */
5170 if ((i.tm.opcode_modifier.drex
5171 || i.tm.opcode_modifier.drexv)
5172 && DREX_OC0 (i.tm.extension_opcode))
5173 *p |= DREX_OC0_MASK;
5174 }
5175
29b0f896 5176 if (i.disp_operands)
2bbd9c25 5177 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 5178
29b0f896 5179 if (i.imm_operands)
2bbd9c25 5180 output_imm (insn_start_frag, insn_start_off);
29b0f896 5181 }
252b5132 5182
29b0f896
AM		 5183#ifdef DEBUG386
5184 if (flag_debug)
5185 {
7b81dfbb 5186 pi ("" /*line*/, &i);
29b0f896
AM		 5187 }
5188#endif /* DEBUG386 */
5189}
252b5132 5190
e205caa7
L		 5191/* Return the size of the displacement operand N. */
5192
5193static int
5194disp_size (unsigned int n)
5195{
5196 int size = 4;
40fb9820
L		 5197 if (i.types[n].bitfield.disp64)
5198 size = 8;
5199 else if (i.types[n].bitfield.disp8)
5200 size = 1;
5201 else if (i.types[n].bitfield.disp16)
5202 size = 2;
e205caa7
L		 5203 return size;
5204}
5205
5206/* Return the size of the immediate operand N. */
5207
5208static int
5209imm_size (unsigned int n)
5210{
5211 int size = 4;
40fb9820
L		 5212 if (i.types[n].bitfield.imm64)
5213 size = 8;
5214 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
5215 size = 1;
5216 else if (i.types[n].bitfield.imm16)
5217 size = 2;
e205caa7
L		 5218 return size;
5219}
5220
29b0f896 5221static void
64e74474 5222output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5223{
5224 char *p;
5225 unsigned int n;
252b5132 5226
29b0f896
AM		 5227 for (n = 0; n < i.operands; n++)
5228 {
40fb9820 5229 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 5230 {
5231 if (i.op[n].disps->X_op == O_constant)
5232 {
e205caa7 5233 int size = disp_size (n);
29b0f896 5234 offsetT val;
252b5132 5235
29b0f896
AM		 5236 val = offset_in_range (i.op[n].disps->X_add_number,
5237 size);
5238 p = frag_more (size);
5239 md_number_to_chars (p, val, size);
5240 }
5241 else
5242 {
f86103b7 5243 enum bfd_reloc_code_real reloc_type;
e205caa7 5244 int size = disp_size (n);
40fb9820 5245 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 5246 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
5247
e205caa7 5248 /* We can't have 8 bit displacement here. */
40fb9820 5249 assert (!i.types[n].bitfield.disp8);
e205caa7 5250
29b0f896
AM		 5251 /* The PC relative address is computed relative
5252 to the instruction boundary, so in case immediate
5253 fields follows, we need to adjust the value. */
5254 if (pcrel && i.imm_operands)
5255 {
29b0f896 5256 unsigned int n1;
e205caa7 5257 int sz = 0;
252b5132 5258
29b0f896 5259 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 5260 if (operand_type_check (i.types[n1], imm))
252b5132 5261 {
e205caa7
L		 5262 /* Only one immediate is allowed for PC
5263 relative address. */
5264 assert (sz == 0);
5265 sz = imm_size (n1);
5266 i.op[n].disps->X_add_number -= sz;
252b5132 5267 }
29b0f896 5268 /* We should find the immediate. */
e205caa7 5269 assert (sz != 0);
29b0f896 5270 }
520dc8e8 5271
29b0f896 5272 p = frag_more (size);
2bbd9c25 5273 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 5274 if (GOT_symbol
2bbd9c25 5275 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 5276 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5277 || reloc_type == BFD_RELOC_X86_64_32S
5278 || (reloc_type == BFD_RELOC_64
5279 && object_64bit))
d6ab8113
JB		 5280 && (i.op[n].disps->X_op == O_symbol
5281 || (i.op[n].disps->X_op == O_add
5282 && ((symbol_get_value_expression
5283 (i.op[n].disps->X_op_symbol)->X_op)
5284 == O_subtract))))
5285 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 5286 {
5287 offsetT add;
5288
5289 if (insn_start_frag == frag_now)
5290 add = (p - frag_now->fr_literal) - insn_start_off;
5291 else
5292 {
5293 fragS *fr;
5294
5295 add = insn_start_frag->fr_fix - insn_start_off;
5296 for (fr = insn_start_frag->fr_next;
5297 fr && fr != frag_now; fr = fr->fr_next)
5298 add += fr->fr_fix;
5299 add += p - frag_now->fr_literal;
5300 }
5301
4fa24527 5302 if (!object_64bit)
7b81dfbb
AJ		 5303 {
5304 reloc_type = BFD_RELOC_386_GOTPC;
5305 i.op[n].imms->X_add_number += add;
5306 }
5307 else if (reloc_type == BFD_RELOC_64)
5308 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 5309 else
7b81dfbb
AJ		 5310 /* Don't do the adjustment for x86-64, as there
5311 the pcrel addressing is relative to the _next_
5312 insn, and that is taken care of in other code. */
d6ab8113 5313 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 5314 }
062cd5e7 5315 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 5316 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 5317 }
5318 }
5319 }
5320}
252b5132 5321
29b0f896 5322static void
64e74474 5323output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 5324{
5325 char *p;
5326 unsigned int n;
252b5132 5327
29b0f896
AM		 5328 for (n = 0; n < i.operands; n++)
5329 {
40fb9820 5330 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 5331 {
5332 if (i.op[n].imms->X_op == O_constant)
5333 {
e205caa7 5334 int size = imm_size (n);
29b0f896 5335 offsetT val;
b4cac588 5336
29b0f896
AM		 5337 val = offset_in_range (i.op[n].imms->X_add_number,
5338 size);
5339 p = frag_more (size);
5340 md_number_to_chars (p, val, size);
5341 }
5342 else
5343 {
5344 /* Not absolute_section.
5345 Need a 32-bit fixup (don't support 8bit
5346 non-absolute imms). Try to support other
5347 sizes ... */
f86103b7 5348 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 5349 int size = imm_size (n);
5350 int sign;
29b0f896 5351
40fb9820 5352 if (i.types[n].bitfield.imm32s
a7d61044 5353 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 5354 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 5355 sign = 1;
e205caa7
L		 5356 else
5357 sign = 0;
520dc8e8 5358
29b0f896
AM		 5359 p = frag_more (size);
5360 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 5361
2bbd9c25
JJ		 5362 /* This is tough to explain. We end up with this one if we
5363 * have operands that look like
5364 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5365 * obtain the absolute address of the GOT, and it is strongly
5366 * preferable from a performance point of view to avoid using
5367 * a runtime relocation for this. The actual sequence of
5368 * instructions often look something like:
5369 *
5370 * call .L66
5371 * .L66:
5372 * popl %ebx
5373 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5374 *
5375 * The call and pop essentially return the absolute address
5376 * of the label .L66 and store it in %ebx. The linker itself
5377 * will ultimately change the first operand of the addl so
5378 * that %ebx points to the GOT, but to keep things simple, the
5379 * .o file must have this operand set so that it generates not
5380 * the absolute address of .L66, but the absolute address of
5381 * itself. This allows the linker itself simply treat a GOTPC
5382 * relocation as asking for a pcrel offset to the GOT to be
5383 * added in, and the addend of the relocation is stored in the
5384 * operand field for the instruction itself.
5385 *
5386 * Our job here is to fix the operand so that it would add
5387 * the correct offset so that %ebx would point to itself. The
5388 * thing that is tricky is that .-.L66 will point to the
5389 * beginning of the instruction, so we need to further modify
5390 * the operand so that it will point to itself. There are
5391 * other cases where you have something like:
5392 *
5393 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5394 *
5395 * and here no correction would be required. Internally in
5396 * the assembler we treat operands of this form as not being
5397 * pcrel since the '.' is explicitly mentioned, and I wonder
5398 * whether it would simplify matters to do it this way. Who
5399 * knows. In earlier versions of the PIC patches, the
5400 * pcrel_adjust field was used to store the correction, but
5401 * since the expression is not pcrel, I felt it would be
5402 * confusing to do it this way. */
5403
d6ab8113 5404 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 5405 || reloc_type == BFD_RELOC_X86_64_32S
5406 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 5407 && GOT_symbol
5408 && GOT_symbol == i.op[n].imms->X_add_symbol
5409 && (i.op[n].imms->X_op == O_symbol
5410 || (i.op[n].imms->X_op == O_add
5411 && ((symbol_get_value_expression
5412 (i.op[n].imms->X_op_symbol)->X_op)
5413 == O_subtract))))
5414 {
2bbd9c25
JJ		 5415 offsetT add;
5416
5417 if (insn_start_frag == frag_now)
5418 add = (p - frag_now->fr_literal) - insn_start_off;
5419 else
5420 {
5421 fragS *fr;
5422
5423 add = insn_start_frag->fr_fix - insn_start_off;
5424 for (fr = insn_start_frag->fr_next;
5425 fr && fr != frag_now; fr = fr->fr_next)
5426 add += fr->fr_fix;
5427 add += p - frag_now->fr_literal;
5428 }
5429
4fa24527 5430 if (!object_64bit)
d6ab8113 5431 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 5432 else if (size == 4)
d6ab8113 5433 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 5434 else if (size == 8)
5435 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 5436 i.op[n].imms->X_add_number += add;
29b0f896 5437 }
29b0f896
AM		 5438 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5439 i.op[n].imms, 0, reloc_type);
5440 }
5441 }
5442 }
252b5132
RH		 5443}
5444\f
d182319b
JB		 5445/* x86_cons_fix_new is called via the expression parsing code when a
5446 reloc is needed. We use this hook to get the correct .got reloc. */
5447static enum bfd_reloc_code_real got_reloc = NO_RELOC;
5448static int cons_sign = -1;
5449
5450void
e3bb37b5 5451x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 5452 expressionS *exp)
d182319b
JB		 5453{
5454 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
5455
5456 got_reloc = NO_RELOC;
5457
5458#ifdef TE_PE
5459 if (exp->X_op == O_secrel)
5460 {
5461 exp->X_op = O_symbol;
5462 r = BFD_RELOC_32_SECREL;
5463 }
5464#endif
5465
5466 fix_new_exp (frag, off, len, exp, 0, r);
5467}
5468
718ddfc0
JB		 5469#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5470# define lex_got(reloc, adjust, types) NULL
5471#else
f3c180ae
AM		 5472/* Parse operands of the form
5473 <symbol>@GOTOFF+<nnn>
5474 and similar .plt or .got references.
5475
5476 If we find one, set up the correct relocation in RELOC and copy the
5477 input string, minus the `@GOTOFF' into a malloc'd buffer for
5478 parsing by the calling routine. Return this buffer, and if ADJUST
5479 is non-null set it to the length of the string we removed from the
5480 input line. Otherwise return NULL. */
5481static char *
3956db08 5482lex_got (enum bfd_reloc_code_real *reloc,
64e74474 5483 int *adjust,
40fb9820 5484 i386_operand_type *types)
f3c180ae 5485{
7b81dfbb
AJ		 5486 /* Some of the relocations depend on the size of what field is to
5487 be relocated. But in our callers i386_immediate and i386_displacement
5488 we don't yet know the operand size (this will be set by insn
5489 matching). Hence we record the word32 relocation here,
5490 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 5491 static const struct {
5492 const char *str;
4fa24527 5493 const enum bfd_reloc_code_real rel[2];
40fb9820 5494 const i386_operand_type types64;
f3c180ae 5495 } gotrel[] = {
4eed87de
AM		 5496 { "PLTOFF", { 0,
5497 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 5498 OPERAND_TYPE_IMM64 },
4eed87de
AM		 5499 { "PLT", { BFD_RELOC_386_PLT32,
5500 BFD_RELOC_X86_64_PLT32 },
40fb9820 5501 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5502 { "GOTPLT", { 0,
5503 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 5504 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5505 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
5506 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 5507 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 5508 { "GOTPCREL", { 0,
5509 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 5510 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5511 { "TLSGD", { BFD_RELOC_386_TLS_GD,
5512 BFD_RELOC_X86_64_TLSGD },
40fb9820 5513 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5514 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
5515 0 },
40fb9820 5516 OPERAND_TYPE_NONE },
4eed87de
AM		 5517 { "TLSLD", { 0,
5518 BFD_RELOC_X86_64_TLSLD },
40fb9820 5519 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5520 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
5521 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 5522 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5523 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
5524 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 5525 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5526 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
5527 0 },
40fb9820 5528 OPERAND_TYPE_NONE },
4eed87de
AM		 5529 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
5530 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 5531
5532 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 5533 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
5534 0 },
40fb9820 5535 OPERAND_TYPE_NONE },
4eed87de
AM		 5536 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
5537 0 },
40fb9820 5538 OPERAND_TYPE_NONE },
4eed87de
AM		 5539 { "GOT", { BFD_RELOC_386_GOT32,
5540 BFD_RELOC_X86_64_GOT32 },
40fb9820 5541 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 5542 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
5543 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 5544 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 5545 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
5546 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 5547 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 5548 };
5549 char *cp;
5550 unsigned int j;
5551
718ddfc0
JB		 5552 if (!IS_ELF)
5553 return NULL;
5554
f3c180ae 5555 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 5556 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 5557 return NULL;
5558
47465058 5559 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 5560 {
5561 int len;
5562
5563 len = strlen (gotrel[j].str);
28f81592 5564 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 5565 {
4fa24527 5566 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 5567 {
28f81592
AM		 5568 int first, second;
5569 char *tmpbuf, *past_reloc;
f3c180ae 5570
4fa24527 5571 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 5572 if (adjust)
5573 *adjust = len;
f3c180ae 5574
3956db08
JB		 5575 if (types)
5576 {
5577 if (flag_code != CODE_64BIT)
40fb9820
L		 5578 {
5579 types->bitfield.imm32 = 1;
5580 types->bitfield.disp32 = 1;
5581 }
3956db08
JB		 5582 else
5583 *types = gotrel[j].types64;
5584 }
5585
f3c180ae
AM		 5586 if (GOT_symbol == NULL)
5587 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
5588
28f81592 5589 /* The length of the first part of our input line. */
f3c180ae 5590 first = cp - input_line_pointer;
28f81592
AM		 5591
5592 /* The second part goes from after the reloc token until
67c11a9b 5593 (and including) an end_of_line char or comma. */
28f81592 5594 past_reloc = cp + 1 + len;
67c11a9b
AM		 5595 cp = past_reloc;
5596 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
5597 ++cp;
5598 second = cp + 1 - past_reloc;
28f81592
AM		 5599
5600 /* Allocate and copy string. The trailing NUL shouldn't
5601 be necessary, but be safe. */
5602 tmpbuf = xmalloc (first + second + 2);
f3c180ae 5603 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 5604 if (second != 0 && *past_reloc != ' ')
5605 /* Replace the relocation token with ' ', so that
5606 errors like foo@GOTOFF1 will be detected. */
5607 tmpbuf[first++] = ' ';
5608 memcpy (tmpbuf + first, past_reloc, second);
5609 tmpbuf[first + second] = '\0';
f3c180ae
AM		 5610 return tmpbuf;
5611 }
5612
4fa24527
JB		 5613 as_bad (_("@%s reloc is not supported with %d-bit output format"),
5614 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 5615 return NULL;
5616 }
5617 }
5618
5619 /* Might be a symbol version string. Don't as_bad here. */
5620 return NULL;
5621}
5622
f3c180ae 5623void
e3bb37b5 5624x86_cons (expressionS *exp, int size)
f3c180ae 5625{
4fa24527 5626 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 5627 {
5628 /* Handle @GOTOFF and the like in an expression. */
5629 char *save;
5630 char *gotfree_input_line;
5631 int adjust;
5632
5633 save = input_line_pointer;
3956db08 5634 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 5635 if (gotfree_input_line)
5636 input_line_pointer = gotfree_input_line;
5637
5638 expression (exp);
5639
5640 if (gotfree_input_line)
5641 {
5642 /* expression () has merrily parsed up to the end of line,
5643 or a comma - in the wrong buffer. Transfer how far
5644 input_line_pointer has moved to the right buffer. */
5645 input_line_pointer = (save
5646 + (input_line_pointer - gotfree_input_line)
5647 + adjust);
5648 free (gotfree_input_line);
3992d3b7
AM		 5649 if (exp->X_op == O_constant
5650 || exp->X_op == O_absent
5651 || exp->X_op == O_illegal
5652 || exp->X_op == O_register
5653 || exp->X_op == O_big)
5654 {
5655 char c = *input_line_pointer;
5656 *input_line_pointer = 0;
5657 as_bad (_("missing or invalid expression `%s'"), save);
5658 *input_line_pointer = c;
5659 }
f3c180ae
AM		 5660 }
5661 }
5662 else
5663 expression (exp);
5664}
5665#endif
5666
d182319b 5667static void signed_cons (int size)
6482c264 5668{
d182319b
JB		 5669 if (flag_code == CODE_64BIT)
5670 cons_sign = 1;
5671 cons (size);
5672 cons_sign = -1;
6482c264
NC		 5673}
5674
d182319b 5675#ifdef TE_PE
6482c264
NC		 5676static void
5677pe_directive_secrel (dummy)
5678 int dummy ATTRIBUTE_UNUSED;
5679{
5680 expressionS exp;
5681
5682 do
5683 {
5684 expression (&exp);
5685 if (exp.X_op == O_symbol)
5686 exp.X_op = O_secrel;
5687
5688 emit_expr (&exp, 4);
5689 }
5690 while (*input_line_pointer++ == ',');
5691
5692 input_line_pointer--;
5693 demand_empty_rest_of_line ();
5694}
6482c264
NC		 5695#endif
5696
252b5132 5697static int
70e41ade 5698i386_immediate (char *imm_start)
252b5132
RH		 5699{
5700 char *save_input_line_pointer;
f3c180ae 5701 char *gotfree_input_line;
252b5132 5702 segT exp_seg = 0;
47926f60 5703 expressionS *exp;
40fb9820
L		 5704 i386_operand_type types;
5705
c6fb90c8 5706 UINTS_SET (types, ~0);
252b5132
RH		 5707
5708 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
5709 {
31b2323c
L		 5710 as_bad (_("at most %d immediate operands are allowed"),
5711 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 5712 return 0;
5713 }
5714
5715 exp = &im_expressions[i.imm_operands++];
520dc8e8 5716 i.op[this_operand].imms = exp;
252b5132
RH		 5717
5718 if (is_space_char (*imm_start))
5719 ++imm_start;
5720
5721 save_input_line_pointer = input_line_pointer;
5722 input_line_pointer = imm_start;
5723
3956db08 5724 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5725 if (gotfree_input_line)
5726 input_line_pointer = gotfree_input_line;
252b5132
RH		 5727
5728 exp_seg = expression (exp);
5729
83183c0c 5730 SKIP_WHITESPACE ();
252b5132 5731 if (*input_line_pointer)
f3c180ae 5732 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 5733
5734 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 5735 if (gotfree_input_line)
5736 free (gotfree_input_line);
252b5132 5737
3992d3b7
AM		 5738 if (exp->X_op == O_absent
5739 || exp->X_op == O_illegal
5740 || exp->X_op == O_big
5741 || (gotfree_input_line
5742 && (exp->X_op == O_constant
5743 || exp->X_op == O_register)))
252b5132 5744 {
3992d3b7 5745 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 5746 imm_start);
3992d3b7 5747 return 0;
252b5132 5748 }
3e73aa7c 5749 else if (exp->X_op == O_constant)
252b5132 5750 {
47926f60 5751 /* Size it properly later. */
40fb9820 5752 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 5753 /* If BFD64, sign extend val. */
4eed87de
AM		 5754 if (!use_rela_relocations
5755 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
5756 exp->X_add_number
5757 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 5758 }
4c63da97 5759#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 5760 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 5761 && exp_seg != absolute_section
47926f60 5762 && exp_seg != text_section
24eab124
AM		 5763 && exp_seg != data_section
5764 && exp_seg != bss_section
5765 && exp_seg != undefined_section
f86103b7 5766 && !bfd_is_com_section (exp_seg))
252b5132 5767 {
d0b47220 5768 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 5769 return 0;
5770 }
5771#endif
bb8f5920
L		 5772 else if (!intel_syntax && exp->X_op == O_register)
5773 {
5774 as_bad (_("illegal immediate register operand %s"), imm_start);
5775 return 0;
5776 }
252b5132
RH		 5777 else
5778 {
5779 /* This is an address. The size of the address will be
24eab124 5780 determined later, depending on destination register,
3e73aa7c 5781 suffix, or the default for the section. */
40fb9820
L		 5782 i.types[this_operand].bitfield.imm8 = 1;
5783 i.types[this_operand].bitfield.imm16 = 1;
5784 i.types[this_operand].bitfield.imm32 = 1;
5785 i.types[this_operand].bitfield.imm32s = 1;
5786 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 5787 i.types[this_operand] = operand_type_and (i.types[this_operand],
5788 types);
252b5132
RH		 5789 }
5790
5791 return 1;
5792}
5793
551c1ca1 5794static char *
e3bb37b5 5795i386_scale (char *scale)
252b5132 5796{
551c1ca1
AM		 5797 offsetT val;
5798 char *save = input_line_pointer;
252b5132 5799
551c1ca1
AM		 5800 input_line_pointer = scale;
5801 val = get_absolute_expression ();
5802
5803 switch (val)
252b5132 5804 {
551c1ca1 5805 case 1:
252b5132
RH		 5806 i.log2_scale_factor = 0;
5807 break;
551c1ca1 5808 case 2:
252b5132
RH		 5809 i.log2_scale_factor = 1;
5810 break;
551c1ca1 5811 case 4:
252b5132
RH		 5812 i.log2_scale_factor = 2;
5813 break;
551c1ca1 5814 case 8:
252b5132
RH		 5815 i.log2_scale_factor = 3;
5816 break;
5817 default:
a724f0f4
JB		 5818 {
5819 char sep = *input_line_pointer;
5820
5821 *input_line_pointer = '\0';
5822 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5823 scale);
5824 *input_line_pointer = sep;
5825 input_line_pointer = save;
5826 return NULL;
5827 }
252b5132 5828 }
29b0f896 5829 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 5830 {
5831 as_warn (_("scale factor of %d without an index register"),
24eab124 5832 1 << i.log2_scale_factor);
252b5132 5833 i.log2_scale_factor = 0;
252b5132 5834 }
551c1ca1
AM		 5835 scale = input_line_pointer;
5836 input_line_pointer = save;
5837 return scale;
252b5132
RH		 5838}
5839
252b5132 5840static int
e3bb37b5 5841i386_displacement (char *disp_start, char *disp_end)
252b5132 5842{
29b0f896 5843 expressionS *exp;
252b5132
RH		 5844 segT exp_seg = 0;
5845 char *save_input_line_pointer;
f3c180ae 5846 char *gotfree_input_line;
40fb9820
L		 5847 int override;
5848 i386_operand_type bigdisp, types = anydisp;
3992d3b7 5849 int ret;
252b5132 5850
31b2323c
L		 5851 if (i.disp_operands == MAX_MEMORY_OPERANDS)
5852 {
5853 as_bad (_("at most %d displacement operands are allowed"),
5854 MAX_MEMORY_OPERANDS);
5855 return 0;
5856 }
5857
c6fb90c8 5858 UINTS_CLEAR (bigdisp);
40fb9820
L		 5859 if ((i.types[this_operand].bitfield.jumpabsolute)
5860 || (!current_templates->start->opcode_modifier.jump
5861 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 5862 {
40fb9820 5863 bigdisp.bitfield.disp32 = 1;
e05278af 5864 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 5865 if (flag_code == CODE_64BIT)
5866 {
5867 if (!override)
5868 {
5869 bigdisp.bitfield.disp32s = 1;
5870 bigdisp.bitfield.disp64 = 1;
5871 }
5872 }
5873 else if ((flag_code == CODE_16BIT) ^ override)
5874 {
5875 bigdisp.bitfield.disp32 = 0;
5876 bigdisp.bitfield.disp16 = 1;
5877 }
e05278af
JB		 5878 }
5879 else
5880 {
5881 /* For PC-relative branches, the width of the displacement
5882 is dependent upon data size, not address size. */
e05278af 5883 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 5884 if (flag_code == CODE_64BIT)
5885 {
5886 if (override || i.suffix == WORD_MNEM_SUFFIX)
5887 bigdisp.bitfield.disp16 = 1;
5888 else
5889 {
5890 bigdisp.bitfield.disp32 = 1;
5891 bigdisp.bitfield.disp32s = 1;
5892 }
5893 }
5894 else
e05278af
JB		 5895 {
5896 if (!override)
5897 override = (i.suffix == (flag_code != CODE_16BIT
5898 ? WORD_MNEM_SUFFIX
5899 : LONG_MNEM_SUFFIX));
40fb9820
L		 5900 bigdisp.bitfield.disp32 = 1;
5901 if ((flag_code == CODE_16BIT) ^ override)
5902 {
5903 bigdisp.bitfield.disp32 = 0;
5904 bigdisp.bitfield.disp16 = 1;
5905 }
e05278af 5906 }
e05278af 5907 }
c6fb90c8
L		 5908 i.types[this_operand] = operand_type_or (i.types[this_operand],
5909 bigdisp);
252b5132
RH		 5910
5911 exp = &disp_expressions[i.disp_operands];
520dc8e8 5912 i.op[this_operand].disps = exp;
252b5132
RH		 5913 i.disp_operands++;
5914 save_input_line_pointer = input_line_pointer;
5915 input_line_pointer = disp_start;
5916 END_STRING_AND_SAVE (disp_end);
5917
5918#ifndef GCC_ASM_O_HACK
5919#define GCC_ASM_O_HACK 0
5920#endif
5921#if GCC_ASM_O_HACK
5922 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 5923 if (i.types[this_operand].bitfield.baseIndex
24eab124 5924 && displacement_string_end[-1] == '+')
252b5132
RH		 5925 {
5926 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 5927 constraint within gcc asm statements.
5928 For instance:
5929
5930 #define _set_tssldt_desc(n,addr,limit,type) \
5931 __asm__ __volatile__ ( \
5932 "movw %w2,%0\n\t" \
5933 "movw %w1,2+%0\n\t" \
5934 "rorl $16,%1\n\t" \
5935 "movb %b1,4+%0\n\t" \
5936 "movb %4,5+%0\n\t" \
5937 "movb $0,6+%0\n\t" \
5938 "movb %h1,7+%0\n\t" \
5939 "rorl $16,%1" \
5940 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
5941
5942 This works great except that the output assembler ends
5943 up looking a bit weird if it turns out that there is
5944 no offset. You end up producing code that looks like:
5945
5946 #APP
5947 movw $235,(%eax)
5948 movw %dx,2+(%eax)
5949 rorl $16,%edx
5950 movb %dl,4+(%eax)
5951 movb $137,5+(%eax)
5952 movb $0,6+(%eax)
5953 movb %dh,7+(%eax)
5954 rorl $16,%edx
5955 #NO_APP
5956
47926f60 5957 So here we provide the missing zero. */
24eab124
AM		 5958
5959 *displacement_string_end = '0';
252b5132
RH		 5960 }
5961#endif
3956db08 5962 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 5963 if (gotfree_input_line)
5964 input_line_pointer = gotfree_input_line;
252b5132 5965
24eab124 5966 exp_seg = expression (exp);
252b5132 5967
636c26b0
AM		 5968 SKIP_WHITESPACE ();
5969 if (*input_line_pointer)
5970 as_bad (_("junk `%s' after expression"), input_line_pointer);
5971#if GCC_ASM_O_HACK
5972 RESTORE_END_STRING (disp_end + 1);
5973#endif
636c26b0 5974 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 5975 if (gotfree_input_line)
5976 free (gotfree_input_line);
3992d3b7 5977 ret = 1;
636c26b0 5978
24eab124
AM		 5979 /* We do this to make sure that the section symbol is in
5980 the symbol table. We will ultimately change the relocation
47926f60 5981 to be relative to the beginning of the section. */
1ae12ab7 5982 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 5983 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
5984 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 5985 {
636c26b0 5986 if (exp->X_op != O_symbol)
3992d3b7 5987 goto inv_disp;
636c26b0 5988
e5cb08ac 5989 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 5990 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
5991 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 5992 exp->X_op = O_subtract;
5993 exp->X_op_symbol = GOT_symbol;
1ae12ab7 5994 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 5995 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 5996 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
5997 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 5998 else
29b0f896 5999 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6000 }
252b5132 6001
3992d3b7
AM		 6002 else if (exp->X_op == O_absent
6003 || exp->X_op == O_illegal
6004 || exp->X_op == O_big
6005 || (gotfree_input_line
6006 && (exp->X_op == O_constant
6007 || exp->X_op == O_register)))
2daf4fd8 6008 {
3992d3b7
AM		 6009 inv_disp:
6010 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6011 disp_start);
3992d3b7 6012 ret = 0;
2daf4fd8
AM		 6013 }
6014
4c63da97 6015#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6016 else if (exp->X_op != O_constant
6017 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6018 && exp_seg != absolute_section
6019 && exp_seg != text_section
6020 && exp_seg != data_section
6021 && exp_seg != bss_section
6022 && exp_seg != undefined_section
6023 && !bfd_is_com_section (exp_seg))
24eab124 6024 {
d0b47220 6025 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6026 ret = 0;
24eab124 6027 }
252b5132 6028#endif
3956db08 6029
3992d3b7
AM		 6030 RESTORE_END_STRING (disp_end);
6031
40fb9820
L		 6032 /* Check if this is a displacement only operand. */
6033 bigdisp = i.types[this_operand];
6034 bigdisp.bitfield.disp8 = 0;
6035 bigdisp.bitfield.disp16 = 0;
6036 bigdisp.bitfield.disp32 = 0;
6037 bigdisp.bitfield.disp32s = 0;
6038 bigdisp.bitfield.disp64 = 0;
c6fb90c8
L		 6039 if (UINTS_ALL_ZERO (bigdisp))
6040 i.types[this_operand] = operand_type_and (i.types[this_operand],
6041 types);
3956db08 6042
3992d3b7 6043 return ret;
252b5132
RH		 6044}
6045
eecb386c 6046/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6047 Return 1 on success, 0 on a failure. */
6048
252b5132 6049static int
e3bb37b5 6050i386_index_check (const char *operand_string)
252b5132 6051{
3e73aa7c 6052 int ok;
24eab124 6053#if INFER_ADDR_PREFIX
eecb386c
AM		 6054 int fudged = 0;
6055
24eab124
AM		 6056 tryprefix:
6057#endif
3e73aa7c 6058 ok = 1;
75178d9d 6059 if (flag_code == CODE_64BIT)
64e74474 6060 {
64e74474 6061 if ((i.base_reg
40fb9820
L		 6062 && ((i.prefix[ADDR_PREFIX] == 0
6063 && !i.base_reg->reg_type.bitfield.reg64)
6064 || (i.prefix[ADDR_PREFIX]
6065 && !i.base_reg->reg_type.bitfield.reg32))
6066 && (i.index_reg
9a04903e
JB		 6067 || i.base_reg->reg_num !=
6068 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6069 || (i.index_reg
40fb9820
L		 6070 && (!i.index_reg->reg_type.bitfield.baseindex
6071 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6072 && i.index_reg->reg_num != RegRiz
6073 && !i.index_reg->reg_type.bitfield.reg64
6074 )
40fb9820 6075 || (i.prefix[ADDR_PREFIX]
db51cc60 6076 && i.index_reg->reg_num != RegEiz
40fb9820 6077 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6078 ok = 0;
3e73aa7c
JH		 6079 }
6080 else
6081 {
6082 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6083 {
6084 /* 16bit checks. */
6085 if ((i.base_reg
40fb9820
L		 6086 && (!i.base_reg->reg_type.bitfield.reg16
6087 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6088 || (i.index_reg
40fb9820
L		 6089 && (!i.index_reg->reg_type.bitfield.reg16
6090 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6091 || !(i.base_reg
6092 && i.base_reg->reg_num < 6
6093 && i.index_reg->reg_num >= 6
6094 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6095 ok = 0;
6096 }
6097 else
e5cb08ac 6098 {
3e73aa7c
JH		 6099 /* 32bit checks. */
6100 if ((i.base_reg
40fb9820 6101 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6102 || (i.index_reg
db51cc60
L		 6103 && ((!i.index_reg->reg_type.bitfield.reg32
6104 && i.index_reg->reg_num != RegEiz)
40fb9820 6105 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 6106 ok = 0;
3e73aa7c
JH		 6107 }
6108 }
6109 if (!ok)
24eab124
AM		 6110 {
6111#if INFER_ADDR_PREFIX
20f0a1fc 6112 if (i.prefix[ADDR_PREFIX] == 0)
24eab124
AM		 6113 {
6114 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
6115 i.prefixes += 1;
b23bac36
AM		 6116 /* Change the size of any displacement too. At most one of
6117 Disp16 or Disp32 is set.
6118 FIXME. There doesn't seem to be any real need for separate
6119 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 6120 Removing them would probably clean up the code quite a lot. */
4eed87de 6121 if (flag_code != CODE_64BIT
40fb9820
L		 6122 && (i.types[this_operand].bitfield.disp16
6123 || i.types[this_operand].bitfield.disp32))
6124 i.types[this_operand]
c6fb90c8 6125 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 6126 fudged = 1;
24eab124
AM		 6127 goto tryprefix;
6128 }
eecb386c
AM		 6129 if (fudged)
6130 as_bad (_("`%s' is not a valid base/index expression"),
6131 operand_string);
6132 else
c388dee8 6133#endif
eecb386c
AM		 6134 as_bad (_("`%s' is not a valid %s bit base/index expression"),
6135 operand_string,
3e73aa7c 6136 flag_code_names[flag_code]);
24eab124 6137 }
20f0a1fc 6138 return ok;
24eab124 6139}
252b5132 6140
252b5132 6141/* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
47926f60 6142 on error. */
252b5132 6143
252b5132 6144static int
a7619375 6145i386_att_operand (char *operand_string)
252b5132 6146{
af6bdddf
AM		 6147 const reg_entry *r;
6148 char *end_op;
24eab124 6149 char *op_string = operand_string;
252b5132 6150
24eab124 6151 if (is_space_char (*op_string))
252b5132
RH		 6152 ++op_string;
6153
24eab124 6154 /* We check for an absolute prefix (differentiating,
47926f60 6155 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 6156 if (*op_string == ABSOLUTE_PREFIX)
6157 {
6158 ++op_string;
6159 if (is_space_char (*op_string))
6160 ++op_string;
40fb9820 6161 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 6162 }
252b5132 6163
47926f60 6164 /* Check if operand is a register. */
4d1bb795 6165 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 6166 {
40fb9820
L		 6167 i386_operand_type temp;
6168
24eab124
AM		 6169 /* Check for a segment override by searching for ':' after a
6170 segment register. */
6171 op_string = end_op;
6172 if (is_space_char (*op_string))
6173 ++op_string;
40fb9820
L		 6174 if (*op_string == ':'
6175 && (r->reg_type.bitfield.sreg2
6176 || r->reg_type.bitfield.sreg3))
24eab124
AM		 6177 {
6178 switch (r->reg_num)
6179 {
6180 case 0:
6181 i.seg[i.mem_operands] = &es;
6182 break;
6183 case 1:
6184 i.seg[i.mem_operands] = &cs;
6185 break;
6186 case 2:
6187 i.seg[i.mem_operands] = &ss;
6188 break;
6189 case 3:
6190 i.seg[i.mem_operands] = &ds;
6191 break;
6192 case 4:
6193 i.seg[i.mem_operands] = &fs;
6194 break;
6195 case 5:
6196 i.seg[i.mem_operands] = &gs;
6197 break;
6198 }
252b5132 6199
24eab124 6200 /* Skip the ':' and whitespace. */
252b5132
RH		 6201 ++op_string;
6202 if (is_space_char (*op_string))
24eab124 6203 ++op_string;
252b5132 6204
24eab124
AM		 6205 if (!is_digit_char (*op_string)
6206 && !is_identifier_char (*op_string)
6207 && *op_string != '('
6208 && *op_string != ABSOLUTE_PREFIX)
6209 {
6210 as_bad (_("bad memory operand `%s'"), op_string);
6211 return 0;
6212 }
47926f60 6213 /* Handle case of %es:*foo. */
24eab124
AM		 6214 if (*op_string == ABSOLUTE_PREFIX)
6215 {
6216 ++op_string;
6217 if (is_space_char (*op_string))
6218 ++op_string;
40fb9820 6219 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 6220 }
6221 goto do_memory_reference;
6222 }
6223 if (*op_string)
6224 {
d0b47220 6225 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 6226 return 0;
6227 }
40fb9820
L		 6228 temp = r->reg_type;
6229 temp.bitfield.baseindex = 0;
c6fb90c8
L		 6230 i.types[this_operand] = operand_type_or (i.types[this_operand],
6231 temp);
7d5e4556 6232 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 6233 i.op[this_operand].regs = r;
24eab124
AM		 6234 i.reg_operands++;
6235 }
af6bdddf
AM		 6236 else if (*op_string == REGISTER_PREFIX)
6237 {
6238 as_bad (_("bad register name `%s'"), op_string);
6239 return 0;
6240 }
24eab124 6241 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 6242 {
24eab124 6243 ++op_string;
40fb9820 6244 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 6245 {
d0b47220 6246 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 6247 return 0;
6248 }
6249 if (!i386_immediate (op_string))
6250 return 0;
6251 }
6252 else if (is_digit_char (*op_string)
6253 || is_identifier_char (*op_string)
e5cb08ac 6254 || *op_string == '(')
24eab124 6255 {
47926f60 6256 /* This is a memory reference of some sort. */
af6bdddf 6257 char *base_string;
252b5132 6258
47926f60 6259 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 6260 char *displacement_string_start;
6261 char *displacement_string_end;
252b5132 6262
24eab124 6263 do_memory_reference:
24eab124 6264 if ((i.mem_operands == 1
40fb9820 6265 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 6266 || i.mem_operands == 2)
6267 {
6268 as_bad (_("too many memory references for `%s'"),
6269 current_templates->start->name);
6270 return 0;
6271 }
252b5132 6272
24eab124
AM		 6273 /* Check for base index form. We detect the base index form by
6274 looking for an ')' at the end of the operand, searching
6275 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6276 after the '('. */
af6bdddf 6277 base_string = op_string + strlen (op_string);
c3332e24 6278
af6bdddf
AM		 6279 --base_string;
6280 if (is_space_char (*base_string))
6281 --base_string;
252b5132 6282
47926f60 6283 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 6284 displacement_string_start = op_string;
6285 displacement_string_end = base_string + 1;
252b5132 6286
24eab124
AM		 6287 if (*base_string == ')')
6288 {
af6bdddf 6289 char *temp_string;
24eab124
AM		 6290 unsigned int parens_balanced = 1;
6291 /* We've already checked that the number of left & right ()'s are
47926f60 6292 equal, so this loop will not be infinite. */
24eab124
AM		 6293 do
6294 {
6295 base_string--;
6296 if (*base_string == ')')
6297 parens_balanced++;
6298 if (*base_string == '(')
6299 parens_balanced--;
6300 }
6301 while (parens_balanced);
c3332e24 6302
af6bdddf 6303 temp_string = base_string;
c3332e24 6304
24eab124 6305 /* Skip past '(' and whitespace. */
252b5132
RH		 6306 ++base_string;
6307 if (is_space_char (*base_string))
24eab124 6308 ++base_string;
252b5132 6309
af6bdddf 6310 if (*base_string == ','
4eed87de
AM		 6311 || ((i.base_reg = parse_register (base_string, &end_op))
6312 != NULL))
252b5132 6313 {
af6bdddf 6314 displacement_string_end = temp_string;
252b5132 6315
40fb9820 6316 i.types[this_operand].bitfield.baseindex = 1;
252b5132 6317
af6bdddf 6318 if (i.base_reg)
24eab124 6319 {
24eab124
AM		 6320 base_string = end_op;
6321 if (is_space_char (*base_string))
6322 ++base_string;
af6bdddf
AM		 6323 }
6324
6325 /* There may be an index reg or scale factor here. */
6326 if (*base_string == ',')
6327 {
6328 ++base_string;
6329 if (is_space_char (*base_string))
6330 ++base_string;
6331
4eed87de
AM		 6332 if ((i.index_reg = parse_register (base_string, &end_op))
6333 != NULL)
24eab124 6334 {
af6bdddf 6335 base_string = end_op;
24eab124
AM		 6336 if (is_space_char (*base_string))
6337 ++base_string;
af6bdddf
AM		 6338 if (*base_string == ',')
6339 {
6340 ++base_string;
6341 if (is_space_char (*base_string))
6342 ++base_string;
6343 }
e5cb08ac 6344 else if (*base_string != ')')
af6bdddf 6345 {
4eed87de
AM		 6346 as_bad (_("expecting `,' or `)' "
6347 "after index register in `%s'"),
af6bdddf
AM		 6348 operand_string);
6349 return 0;
6350 }
24eab124 6351 }
af6bdddf 6352 else if (*base_string == REGISTER_PREFIX)
24eab124 6353 {
af6bdddf 6354 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 6355 return 0;
6356 }
252b5132 6357
47926f60 6358 /* Check for scale factor. */
551c1ca1 6359 if (*base_string != ')')
af6bdddf 6360 {
551c1ca1
AM		 6361 char *end_scale = i386_scale (base_string);
6362
6363 if (!end_scale)
af6bdddf 6364 return 0;
24eab124 6365
551c1ca1 6366 base_string = end_scale;
af6bdddf
AM		 6367 if (is_space_char (*base_string))
6368 ++base_string;
6369 if (*base_string != ')')
6370 {
4eed87de
AM		 6371 as_bad (_("expecting `)' "
6372 "after scale factor in `%s'"),
af6bdddf
AM		 6373 operand_string);
6374 return 0;
6375 }
6376 }
6377 else if (!i.index_reg)
24eab124 6378 {
4eed87de
AM		 6379 as_bad (_("expecting index register or scale factor "
6380 "after `,'; got '%c'"),
af6bdddf 6381 *base_string);
24eab124
AM		 6382 return 0;
6383 }
6384 }
af6bdddf 6385 else if (*base_string != ')')
24eab124 6386 {
4eed87de
AM		 6387 as_bad (_("expecting `,' or `)' "
6388 "after base register in `%s'"),
af6bdddf 6389 operand_string);
24eab124
AM		 6390 return 0;
6391 }
c3332e24 6392 }
af6bdddf 6393 else if (*base_string == REGISTER_PREFIX)
c3332e24 6394 {
af6bdddf 6395 as_bad (_("bad register name `%s'"), base_string);
24eab124 6396 return 0;
c3332e24 6397 }
24eab124
AM		 6398 }
6399
6400 /* If there's an expression beginning the operand, parse it,
6401 assuming displacement_string_start and
6402 displacement_string_end are meaningful. */
6403 if (displacement_string_start != displacement_string_end)
6404 {
6405 if (!i386_displacement (displacement_string_start,
6406 displacement_string_end))
6407 return 0;
6408 }
6409
6410 /* Special case for (%dx) while doing input/output op. */
6411 if (i.base_reg
c6fb90c8 6412 && UINTS_EQUAL (i.base_reg->reg_type, reg16_inoutportreg)
24eab124
AM		 6413 && i.index_reg == 0
6414 && i.log2_scale_factor == 0
6415 && i.seg[i.mem_operands] == 0
40fb9820 6416 && !operand_type_check (i.types[this_operand], disp))
24eab124 6417 {
c6fb90c8 6418 UINTS_CLEAR (i.types[this_operand]);
40fb9820 6419 i.types[this_operand].bitfield.inoutportreg = 1;
24eab124
AM		 6420 return 1;
6421 }
6422
eecb386c
AM		 6423 if (i386_index_check (operand_string) == 0)
6424 return 0;
5c07affc 6425 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 6426 i.mem_operands++;
6427 }
6428 else
ce8a8b2f
AM		 6429 {
6430 /* It's not a memory operand; argh! */
24eab124
AM		 6431 as_bad (_("invalid char %s beginning operand %d `%s'"),
6432 output_invalid (*op_string),
6433 this_operand + 1,
6434 op_string);
6435 return 0;
6436 }
47926f60 6437 return 1; /* Normal return. */
252b5132
RH		 6438}
6439\f
ee7fcc42
AM		 6440/* md_estimate_size_before_relax()
6441
6442 Called just before relax() for rs_machine_dependent frags. The x86
6443 assembler uses these frags to handle variable size jump
6444 instructions.
6445
6446 Any symbol that is now undefined will not become defined.
6447 Return the correct fr_subtype in the frag.
6448 Return the initial "guess for variable size of frag" to caller.
6449 The guess is actually the growth beyond the fixed part. Whatever
6450 we do to grow the fixed or variable part contributes to our
6451 returned value. */
6452
252b5132
RH		 6453int
6454md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 6455 fragS *fragP;
6456 segT segment;
252b5132 6457{
252b5132 6458 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 6459 check for un-relaxable symbols. On an ELF system, we can't relax
6460 an externally visible symbol, because it may be overridden by a
6461 shared library. */
6462 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 6463#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6464 || (IS_ELF
31312f95
AM		 6465 && (S_IS_EXTERNAL (fragP->fr_symbol)
6466 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 6467#endif
6468 )
252b5132 6469 {
b98ef147
AM		 6470 /* Symbol is undefined in this segment, or we need to keep a
6471 reloc so that weak symbols can be overridden. */
6472 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 6473 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 6474 unsigned char *opcode;
6475 int old_fr_fix;
f6af82bd 6476
ee7fcc42
AM		 6477 if (fragP->fr_var != NO_RELOC)
6478 reloc_type = fragP->fr_var;
b98ef147 6479 else if (size == 2)
f6af82bd
AM		 6480 reloc_type = BFD_RELOC_16_PCREL;
6481 else
6482 reloc_type = BFD_RELOC_32_PCREL;
252b5132 6483
ee7fcc42
AM		 6484 old_fr_fix = fragP->fr_fix;
6485 opcode = (unsigned char *) fragP->fr_opcode;
6486
fddf5b5b 6487 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 6488 {
fddf5b5b
AM		 6489 case UNCOND_JUMP:
6490 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 6491 opcode[0] = 0xe9;
252b5132 6492 fragP->fr_fix += size;
062cd5e7
AS		 6493 fix_new (fragP, old_fr_fix, size,
6494 fragP->fr_symbol,
6495 fragP->fr_offset, 1,
6496 reloc_type);
252b5132
RH		 6497 break;
6498
fddf5b5b 6499 case COND_JUMP86:
412167cb
AM		 6500 if (size == 2
6501 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 6502 {
6503 /* Negate the condition, and branch past an
6504 unconditional jump. */
6505 opcode[0] ^= 1;
6506 opcode[1] = 3;
6507 /* Insert an unconditional jump. */
6508 opcode[2] = 0xe9;
6509 /* We added two extra opcode bytes, and have a two byte
6510 offset. */
6511 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 6512 fix_new (fragP, old_fr_fix + 2, 2,
6513 fragP->fr_symbol,
6514 fragP->fr_offset, 1,
6515 reloc_type);
fddf5b5b
AM		 6516 break;
6517 }
6518 /* Fall through. */
6519
6520 case COND_JUMP:
412167cb
AM		 6521 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
6522 {
3e02c1cc
AM		 6523 fixS *fixP;
6524
412167cb 6525 fragP->fr_fix += 1;
3e02c1cc
AM		 6526 fixP = fix_new (fragP, old_fr_fix, 1,
6527 fragP->fr_symbol,
6528 fragP->fr_offset, 1,
6529 BFD_RELOC_8_PCREL);
6530 fixP->fx_signed = 1;
412167cb
AM		 6531 break;
6532 }
93c2a809 6533
24eab124 6534 /* This changes the byte-displacement jump 0x7N
fddf5b5b 6535 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 6536 opcode[1] = opcode[0] + 0x10;
f6af82bd 6537 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 6538 /* We've added an opcode byte. */
6539 fragP->fr_fix += 1 + size;
062cd5e7
AS		 6540 fix_new (fragP, old_fr_fix + 1, size,
6541 fragP->fr_symbol,
6542 fragP->fr_offset, 1,
6543 reloc_type);
252b5132 6544 break;
fddf5b5b
AM		 6545
6546 default:
6547 BAD_CASE (fragP->fr_subtype);
6548 break;
252b5132
RH		 6549 }
6550 frag_wane (fragP);
ee7fcc42 6551 return fragP->fr_fix - old_fr_fix;
252b5132 6552 }
93c2a809 6553
93c2a809
AM		 6554 /* Guess size depending on current relax state. Initially the relax
6555 state will correspond to a short jump and we return 1, because
6556 the variable part of the frag (the branch offset) is one byte
6557 long. However, we can relax a section more than once and in that
6558 case we must either set fr_subtype back to the unrelaxed state,
6559 or return the value for the appropriate branch. */
6560 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 6561}
6562
47926f60
KH		 6563/* Called after relax() is finished.
6564
6565 In: Address of frag.
6566 fr_type == rs_machine_dependent.
6567 fr_subtype is what the address relaxed to.
6568
6569 Out: Any fixSs and constants are set up.
6570 Caller will turn frag into a ".space 0". */
6571
252b5132
RH		 6572void
6573md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 6574 bfd *abfd ATTRIBUTE_UNUSED;
6575 segT sec ATTRIBUTE_UNUSED;
29b0f896 6576 fragS *fragP;
252b5132 6577{
29b0f896 6578 unsigned char *opcode;
252b5132 6579 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 6580 offsetT target_address;
6581 offsetT opcode_address;
252b5132 6582 unsigned int extension = 0;
847f7ad4 6583 offsetT displacement_from_opcode_start;
252b5132
RH		 6584
6585 opcode = (unsigned char *) fragP->fr_opcode;
6586
47926f60 6587 /* Address we want to reach in file space. */
252b5132 6588 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 6589
47926f60 6590 /* Address opcode resides at in file space. */
252b5132
RH		 6591 opcode_address = fragP->fr_address + fragP->fr_fix;
6592
47926f60 6593 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 6594 displacement_from_opcode_start = target_address - opcode_address;
6595
fddf5b5b 6596 if ((fragP->fr_subtype & BIG) == 0)
252b5132 6597 {
47926f60
KH		 6598 /* Don't have to change opcode. */
6599 extension = 1; /* 1 opcode + 1 displacement */
252b5132 6600 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 6601 }
6602 else
6603 {
6604 if (no_cond_jump_promotion
6605 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 6606 as_warn_where (fragP->fr_file, fragP->fr_line,
6607 _("long jump required"));
252b5132 6608
fddf5b5b
AM		 6609 switch (fragP->fr_subtype)
6610 {
6611 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
6612 extension = 4; /* 1 opcode + 4 displacement */
6613 opcode[0] = 0xe9;
6614 where_to_put_displacement = &opcode[1];
6615 break;
252b5132 6616
fddf5b5b
AM		 6617 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
6618 extension = 2; /* 1 opcode + 2 displacement */
6619 opcode[0] = 0xe9;
6620 where_to_put_displacement = &opcode[1];
6621 break;
252b5132 6622
fddf5b5b
AM		 6623 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
6624 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
6625 extension = 5; /* 2 opcode + 4 displacement */
6626 opcode[1] = opcode[0] + 0x10;
6627 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6628 where_to_put_displacement = &opcode[2];
6629 break;
252b5132 6630
fddf5b5b
AM		 6631 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
6632 extension = 3; /* 2 opcode + 2 displacement */
6633 opcode[1] = opcode[0] + 0x10;
6634 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
6635 where_to_put_displacement = &opcode[2];
6636 break;
252b5132 6637
fddf5b5b
AM		 6638 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
6639 extension = 4;
6640 opcode[0] ^= 1;
6641 opcode[1] = 3;
6642 opcode[2] = 0xe9;
6643 where_to_put_displacement = &opcode[3];
6644 break;
6645
6646 default:
6647 BAD_CASE (fragP->fr_subtype);
6648 break;
6649 }
252b5132 6650 }
fddf5b5b 6651
7b81dfbb
AJ		 6652 /* If size if less then four we are sure that the operand fits,
6653 but if it's 4, then it could be that the displacement is larger
6654 then -/+ 2GB. */
6655 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
6656 && object_64bit
6657 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 6658 + ((addressT) 1 << 31))
6659 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 6660 {
6661 as_bad_where (fragP->fr_file, fragP->fr_line,
6662 _("jump target out of range"));
6663 /* Make us emit 0. */
6664 displacement_from_opcode_start = extension;
6665 }
47926f60 6666 /* Now put displacement after opcode. */
252b5132
RH		 6667 md_number_to_chars ((char *) where_to_put_displacement,
6668 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 6669 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 6670 fragP->fr_fix += extension;
6671}
6672\f
252b5132
RH		 6673/* Apply a fixup (fixS) to segment data, once it has been determined
6674 by our caller that we have all the info we need to fix it up.
6675
6676 On the 386, immediates, displacements, and data pointers are all in
6677 the same (little-endian) format, so we don't need to care about which
6678 we are handling. */
6679
94f592af 6680void
55cf6793 6681md_apply_fix (fixP, valP, seg)
47926f60
KH		 6682 /* The fix we're to put in. */
6683 fixS *fixP;
47926f60 6684 /* Pointer to the value of the bits. */
c6682705 6685 valueT *valP;
47926f60
KH		 6686 /* Segment fix is from. */
6687 segT seg ATTRIBUTE_UNUSED;
252b5132 6688{
94f592af 6689 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 6690 valueT value = *valP;
252b5132 6691
f86103b7 6692#if !defined (TE_Mach)
93382f6d
AM		 6693 if (fixP->fx_pcrel)
6694 {
6695 switch (fixP->fx_r_type)
6696 {
5865bb77
ILT		 6697 default:
6698 break;
6699
d6ab8113
JB		 6700 case BFD_RELOC_64:
6701 fixP->fx_r_type = BFD_RELOC_64_PCREL;
6702 break;
93382f6d 6703 case BFD_RELOC_32:
ae8887b5 6704 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 6705 fixP->fx_r_type = BFD_RELOC_32_PCREL;
6706 break;
6707 case BFD_RELOC_16:
6708 fixP->fx_r_type = BFD_RELOC_16_PCREL;
6709 break;
6710 case BFD_RELOC_8:
6711 fixP->fx_r_type = BFD_RELOC_8_PCREL;
6712 break;
6713 }
6714 }
252b5132 6715
a161fe53 6716 if (fixP->fx_addsy != NULL
31312f95 6717 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 6718 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 6719 || fixP->fx_r_type == BFD_RELOC_16_PCREL
6720 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
6721 && !use_rela_relocations)
252b5132 6722 {
31312f95
AM		 6723 /* This is a hack. There should be a better way to handle this.
6724 This covers for the fact that bfd_install_relocation will
6725 subtract the current location (for partial_inplace, PC relative
6726 relocations); see more below. */
252b5132 6727#ifndef OBJ_AOUT
718ddfc0 6728 if (IS_ELF
252b5132
RH		 6729#ifdef TE_PE
6730 || OUTPUT_FLAVOR == bfd_target_coff_flavour
6731#endif
6732 )
6733 value += fixP->fx_where + fixP->fx_frag->fr_address;
6734#endif
6735#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6736 if (IS_ELF)
252b5132 6737 {
6539b54b 6738 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 6739
6539b54b 6740 if ((sym_seg == seg
2f66722d 6741 || (symbol_section_p (fixP->fx_addsy)
6539b54b 6742 && sym_seg != absolute_section))
ae6063d4 6743 && !generic_force_reloc (fixP))
2f66722d
AM		 6744 {
6745 /* Yes, we add the values in twice. This is because
6539b54b
AM		 6746 bfd_install_relocation subtracts them out again. I think
6747 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 6748 it. FIXME. */
6749 value += fixP->fx_where + fixP->fx_frag->fr_address;
6750 }
252b5132
RH		 6751 }
6752#endif
6753#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 6754 /* For some reason, the PE format does not store a
6755 section address offset for a PC relative symbol. */
6756 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 6757 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 6758 value += md_pcrel_from (fixP);
6759#endif
6760 }
6761
6762 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 6763 and we must not disappoint it. */
252b5132 6764#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 6765 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 6766 switch (fixP->fx_r_type)
6767 {
6768 case BFD_RELOC_386_PLT32:
3e73aa7c 6769 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 6770 /* Make the jump instruction point to the address of the operand. At
6771 runtime we merely add the offset to the actual PLT entry. */
6772 value = -4;
6773 break;
31312f95 6774
13ae64f3
JJ		 6775 case BFD_RELOC_386_TLS_GD:
6776 case BFD_RELOC_386_TLS_LDM:
13ae64f3 6777 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 6778 case BFD_RELOC_386_TLS_IE:
6779 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 6780 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 6781 case BFD_RELOC_X86_64_TLSGD:
6782 case BFD_RELOC_X86_64_TLSLD:
6783 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 6784 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 6785 value = 0; /* Fully resolved at runtime. No addend. */
6786 /* Fallthrough */
6787 case BFD_RELOC_386_TLS_LE:
6788 case BFD_RELOC_386_TLS_LDO_32:
6789 case BFD_RELOC_386_TLS_LE_32:
6790 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 6791 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 6792 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 6793 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 6794 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6795 break;
6796
67a4f2b7
AO		 6797 case BFD_RELOC_386_TLS_DESC_CALL:
6798 case BFD_RELOC_X86_64_TLSDESC_CALL:
6799 value = 0; /* Fully resolved at runtime. No addend. */
6800 S_SET_THREAD_LOCAL (fixP->fx_addsy);
6801 fixP->fx_done = 0;
6802 return;
6803
00f7efb6
JJ		 6804 case BFD_RELOC_386_GOT32:
6805 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 6806 value = 0; /* Fully resolved at runtime. No addend. */
6807 break;
47926f60
KH		 6808
6809 case BFD_RELOC_VTABLE_INHERIT:
6810 case BFD_RELOC_VTABLE_ENTRY:
6811 fixP->fx_done = 0;
94f592af 6812 return;
47926f60
KH		 6813
6814 default:
6815 break;
6816 }
6817#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 6818 *valP = value;
f86103b7 6819#endif /* !defined (TE_Mach) */
3e73aa7c 6820
3e73aa7c 6821 /* Are we finished with this relocation now? */
c6682705 6822 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 6823 fixP->fx_done = 1;
6824 else if (use_rela_relocations)
6825 {
6826 fixP->fx_no_overflow = 1;
062cd5e7
AS		 6827 /* Remember value for tc_gen_reloc. */
6828 fixP->fx_addnumber = value;
3e73aa7c
JH		 6829 value = 0;
6830 }
f86103b7 6831
94f592af 6832 md_number_to_chars (p, value, fixP->fx_size);
252b5132 6833}
252b5132 6834\f
252b5132 6835char *
499ac353 6836md_atof (int type, char *litP, int *sizeP)
252b5132 6837{
499ac353
NC		 6838 /* This outputs the LITTLENUMs in REVERSE order;
6839 in accord with the bigendian 386. */
6840 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 6841}
6842\f
2d545b82 6843static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 6844
252b5132 6845static char *
e3bb37b5 6846output_invalid (int c)
252b5132 6847{
3882b010 6848 if (ISPRINT (c))
f9f21a03
L		 6849 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
6850 "'%c'", c);
252b5132 6851 else
f9f21a03 6852 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 6853 "(0x%x)", (unsigned char) c);
252b5132
RH		 6854 return output_invalid_buf;
6855}
6856
af6bdddf 6857/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 6858
6859static const reg_entry *
4d1bb795 6860parse_real_register (char *reg_string, char **end_op)
252b5132 6861{
af6bdddf
AM		 6862 char *s = reg_string;
6863 char *p;
252b5132
RH		 6864 char reg_name_given[MAX_REG_NAME_SIZE + 1];
6865 const reg_entry *r;
6866
6867 /* Skip possible REGISTER_PREFIX and possible whitespace. */
6868 if (*s == REGISTER_PREFIX)
6869 ++s;
6870
6871 if (is_space_char (*s))
6872 ++s;
6873
6874 p = reg_name_given;
af6bdddf 6875 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 6876 {
6877 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 6878 return (const reg_entry *) NULL;
6879 s++;
252b5132
RH		 6880 }
6881
6588847e
DN		 6882 /* For naked regs, make sure that we are not dealing with an identifier.
6883 This prevents confusing an identifier like `eax_var' with register
6884 `eax'. */
6885 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
6886 return (const reg_entry *) NULL;
6887
af6bdddf 6888 *end_op = s;
252b5132
RH		 6889
6890 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
6891
5f47d35b 6892 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 6893 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 6894 {
5f47d35b
AM		 6895 if (is_space_char (*s))
6896 ++s;
6897 if (*s == '(')
6898 {
af6bdddf 6899 ++s;
5f47d35b
AM		 6900 if (is_space_char (*s))
6901 ++s;
6902 if (*s >= '0' && *s <= '7')
6903 {
db557034 6904 int fpr = *s - '0';
af6bdddf 6905 ++s;
5f47d35b
AM		 6906 if (is_space_char (*s))
6907 ++s;
6908 if (*s == ')')
6909 {
6910 *end_op = s + 1;
db557034
AM		 6911 r = hash_find (reg_hash, "st(0)");
6912 know (r);
6913 return r + fpr;
5f47d35b 6914 }
5f47d35b 6915 }
47926f60 6916 /* We have "%st(" then garbage. */
5f47d35b
AM		 6917 return (const reg_entry *) NULL;
6918 }
6919 }
6920
db51cc60
L		 6921 /* Don't allow fake index register unless allow_index_reg isn't 0. */
6922 if (r != NULL
6923 && !allow_index_reg
6924 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
6925 return (const reg_entry *) NULL;
6926
1ae00879 6927 if (r != NULL
d946b91f 6928 && ((r->reg_flags & (RegRex64 | RegRex))
40fb9820
L		 6929 || r->reg_type.bitfield.reg64)
6930 && (!cpu_arch_flags.bitfield.cpulm
c6fb90c8 6931 || !UINTS_EQUAL (r->reg_type, control))
1ae00879 6932 && flag_code != CODE_64BIT)
20f0a1fc 6933 return (const reg_entry *) NULL;
1ae00879 6934
252b5132
RH		 6935 return r;
6936}
4d1bb795
JB		 6937
6938/* REG_STRING starts *before* REGISTER_PREFIX. */
6939
6940static const reg_entry *
6941parse_register (char *reg_string, char **end_op)
6942{
6943 const reg_entry *r;
6944
6945 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
6946 r = parse_real_register (reg_string, end_op);
6947 else
6948 r = NULL;
6949 if (!r)
6950 {
6951 char *save = input_line_pointer;
6952 char c;
6953 symbolS *symbolP;
6954
6955 input_line_pointer = reg_string;
6956 c = get_symbol_end ();
6957 symbolP = symbol_find (reg_string);
6958 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
6959 {
6960 const expressionS *e = symbol_get_value_expression (symbolP);
6961
6962 know (e->X_op == O_register);
4eed87de 6963 know (e->X_add_number >= 0
c3fe08fa 6964 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 6965 r = i386_regtab + e->X_add_number;
6966 *end_op = input_line_pointer;
6967 }
6968 *input_line_pointer = c;
6969 input_line_pointer = save;
6970 }
6971 return r;
6972}
6973
6974int
6975i386_parse_name (char *name, expressionS *e, char *nextcharP)
6976{
6977 const reg_entry *r;
6978 char *end = input_line_pointer;
6979
6980 *end = *nextcharP;
6981 r = parse_register (name, &input_line_pointer);
6982 if (r && end <= input_line_pointer)
6983 {
6984 *nextcharP = *input_line_pointer;
6985 *input_line_pointer = 0;
6986 e->X_op = O_register;
6987 e->X_add_number = r - i386_regtab;
6988 return 1;
6989 }
6990 input_line_pointer = end;
6991 *end = 0;
6992 return 0;
6993}
6994
6995void
6996md_operand (expressionS *e)
6997{
6998 if (*input_line_pointer == REGISTER_PREFIX)
6999 {
7000 char *end;
7001 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7002
7003 if (r)
7004 {
7005 e->X_op = O_register;
7006 e->X_add_number = r - i386_regtab;
7007 input_line_pointer = end;
7008 }
7009 }
7010}
7011
252b5132 7012\f
4cc782b5 7013#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7014const char *md_shortopts = "kVQ:sqn";
252b5132 7015#else
12b55ccc 7016const char *md_shortopts = "qn";
252b5132 7017#endif
6e0b89ee 7018
3e73aa7c 7019#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7020#define OPTION_64 (OPTION_MD_BASE + 1)
7021#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7022#define OPTION_MARCH (OPTION_MD_BASE + 3)
7023#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7024#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7025#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7026#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7027#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7028#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
b3b91714 7029
99ad8390
NC		 7030struct option md_longopts[] =
7031{
3e73aa7c 7032 {"32", no_argument, NULL, OPTION_32},
99ad8390 7033#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7034 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7035#endif
b3b91714 7036 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7037 {"march", required_argument, NULL, OPTION_MARCH},
7038 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7039 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7040 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7041 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7042 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7043 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
252b5132
RH		 7044 {NULL, no_argument, NULL, 0}
7045};
7046size_t md_longopts_size = sizeof (md_longopts);
7047
7048int
9103f4f4 7049md_parse_option (int c, char *arg)
252b5132 7050{
9103f4f4
L		 7051 unsigned int i;
7052
252b5132
RH		 7053 switch (c)
7054 {
12b55ccc
L		 7055 case 'n':
7056 optimize_align_code = 0;
7057 break;
7058
a38cf1db
AM		 7059 case 'q':
7060 quiet_warnings = 1;
252b5132
RH		 7061 break;
7062
7063#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7064 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7065 should be emitted or not. FIXME: Not implemented. */
7066 case 'Q':
252b5132
RH		 7067 break;
7068
7069 /* -V: SVR4 argument to print version ID. */
7070 case 'V':
7071 print_version_id ();
7072 break;
7073
a38cf1db
AM		 7074 /* -k: Ignore for FreeBSD compatibility. */
7075 case 'k':
252b5132 7076 break;
4cc782b5
ILT		 7077
7078 case 's':
7079 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 7080 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 7081 break;
99ad8390
NC		 7082#endif
7083#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 7084 case OPTION_64:
7085 {
7086 const char **list, **l;
7087
3e73aa7c
JH		 7088 list = bfd_target_list ();
7089 for (l = list; *l != NULL; l++)
8620418b 7090 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 7091 || strcmp (*l, "coff-x86-64") == 0
7092 || strcmp (*l, "pe-x86-64") == 0
7093 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 7094 {
7095 default_arch = "x86_64";
7096 break;
7097 }
3e73aa7c 7098 if (*l == NULL)
6e0b89ee 7099 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 7100 free (list);
7101 }
7102 break;
7103#endif
252b5132 7104
6e0b89ee
AM		 7105 case OPTION_32:
7106 default_arch = "i386";
7107 break;
7108
b3b91714
AM		 7109 case OPTION_DIVIDE:
7110#ifdef SVR4_COMMENT_CHARS
7111 {
7112 char *n, *t;
7113 const char *s;
7114
7115 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
7116 t = n;
7117 for (s = i386_comment_chars; *s != '\0'; s++)
7118 if (*s != '/')
7119 *t++ = *s;
7120 *t = '\0';
7121 i386_comment_chars = n;
7122 }
7123#endif
7124 break;
7125
9103f4f4
L		 7126 case OPTION_MARCH:
7127 if (*arg == '.')
7128 as_fatal (_("Invalid -march= option: `%s'"), arg);
7129 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7130 {
7131 if (strcmp (arg, cpu_arch [i].name) == 0)
7132 {
ccc9c027 7133 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 7134 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 7135 if (!cpu_arch_tune_set)
7136 {
7137 cpu_arch_tune = cpu_arch_isa;
7138 cpu_arch_tune_flags = cpu_arch_isa_flags;
7139 }
9103f4f4
L		 7140 break;
7141 }
7142 }
7143 if (i >= ARRAY_SIZE (cpu_arch))
7144 as_fatal (_("Invalid -march= option: `%s'"), arg);
7145 break;
7146
7147 case OPTION_MTUNE:
7148 if (*arg == '.')
7149 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7150 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
7151 {
7152 if (strcmp (arg, cpu_arch [i].name) == 0)
7153 {
ccc9c027 7154 cpu_arch_tune_set = 1;
9103f4f4
L		 7155 cpu_arch_tune = cpu_arch [i].type;
7156 cpu_arch_tune_flags = cpu_arch[i].flags;
7157 break;
7158 }
7159 }
7160 if (i >= ARRAY_SIZE (cpu_arch))
7161 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
7162 break;
7163
1efbbeb4
L		 7164 case OPTION_MMNEMONIC:
7165 if (strcasecmp (arg, "att") == 0)
7166 intel_mnemonic = 0;
7167 else if (strcasecmp (arg, "intel") == 0)
7168 intel_mnemonic = 1;
7169 else
7170 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
7171 break;
7172
7173 case OPTION_MSYNTAX:
7174 if (strcasecmp (arg, "att") == 0)
7175 intel_syntax = 0;
7176 else if (strcasecmp (arg, "intel") == 0)
7177 intel_syntax = 1;
7178 else
7179 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
7180 break;
7181
7182 case OPTION_MINDEX_REG:
7183 allow_index_reg = 1;
7184 break;
7185
7186 case OPTION_MNAKED_REG:
7187 allow_naked_reg = 1;
7188 break;
7189
7190 case OPTION_MOLD_GCC:
7191 old_gcc = 1;
1efbbeb4
L		 7192 break;
7193
252b5132
RH		 7194 default:
7195 return 0;
7196 }
7197 return 1;
7198}
7199
7200void
7201md_show_usage (stream)
7202 FILE *stream;
7203{
4cc782b5
ILT		 7204#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7205 fprintf (stream, _("\
a38cf1db
AM		 7206 -Q ignored\n\
7207 -V print assembler version number\n\
b3b91714
AM		 7208 -k ignored\n"));
7209#endif
7210 fprintf (stream, _("\
12b55ccc 7211 -n Do not optimize code alignment\n\
b3b91714
AM		 7212 -q quieten some warnings\n"));
7213#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7214 fprintf (stream, _("\
a38cf1db 7215 -s ignored\n"));
b3b91714 7216#endif
751d281c
L		 7217#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7218 fprintf (stream, _("\
7219 --32/--64 generate 32bit/64bit code\n"));
7220#endif
b3b91714
AM		 7221#ifdef SVR4_COMMENT_CHARS
7222 fprintf (stream, _("\
7223 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 7224#else
7225 fprintf (stream, _("\
b3b91714 7226 --divide ignored\n"));
4cc782b5 7227#endif
9103f4f4
L		 7228 fprintf (stream, _("\
7229 -march=CPU/-mtune=CPU generate code/optimize for CPU, where CPU is one of:\n\
7230 i386, i486, pentium, pentiumpro, pentium4, nocona,\n\
4eed87de 7231 core, core2, k6, athlon, k8, generic32, generic64\n"));
ba104c83
L		 7232 fprintf (stream, _("\
7233 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7234 fprintf (stream, _("\
7235 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7236 fprintf (stream, _("\
7237 -mindex-reg support pseudo index registers\n"));
7238 fprintf (stream, _("\
7239 -mnaked-reg don't require `%%' prefix for registers\n"));
7240 fprintf (stream, _("\
7241 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 7242}
7243
3e73aa7c 7244#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 7245 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 7246
7247/* Pick the target format to use. */
7248
47926f60 7249const char *
e3bb37b5 7250i386_target_format (void)
252b5132 7251{
3e73aa7c 7252 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 7253 {
7254 set_code_flag (CODE_64BIT);
c6fb90c8 7255 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7256 {
7257 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7258 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7259 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7260 cpu_arch_isa_flags.bitfield.cpui486 = 1;
7261 cpu_arch_isa_flags.bitfield.cpui586 = 1;
7262 cpu_arch_isa_flags.bitfield.cpui686 = 1;
7263 cpu_arch_isa_flags.bitfield.cpup4 = 1;
7264 cpu_arch_isa_flags.bitfield.cpummx= 1;
7265 cpu_arch_isa_flags.bitfield.cpummx2 = 1;
7266 cpu_arch_isa_flags.bitfield.cpusse = 1;
7267 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
7268 }
c6fb90c8 7269 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7270 {
7271 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7272 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7273 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7274 cpu_arch_tune_flags.bitfield.cpui486 = 1;
7275 cpu_arch_tune_flags.bitfield.cpui586 = 1;
7276 cpu_arch_tune_flags.bitfield.cpui686 = 1;
7277 cpu_arch_tune_flags.bitfield.cpup4 = 1;
7278 cpu_arch_tune_flags.bitfield.cpummx= 1;
7279 cpu_arch_tune_flags.bitfield.cpummx2 = 1;
7280 cpu_arch_tune_flags.bitfield.cpusse = 1;
7281 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
7282 }
9103f4f4 7283 }
3e73aa7c 7284 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 7285 {
7286 set_code_flag (CODE_32BIT);
c6fb90c8 7287 if (UINTS_ALL_ZERO (cpu_arch_isa_flags))
40fb9820
L		 7288 {
7289 cpu_arch_isa_flags.bitfield.cpui186 = 1;
7290 cpu_arch_isa_flags.bitfield.cpui286 = 1;
7291 cpu_arch_isa_flags.bitfield.cpui386 = 1;
7292 }
c6fb90c8 7293 if (UINTS_ALL_ZERO (cpu_arch_tune_flags))
40fb9820
L		 7294 {
7295 cpu_arch_tune_flags.bitfield.cpui186 = 1;
7296 cpu_arch_tune_flags.bitfield.cpui286 = 1;
7297 cpu_arch_tune_flags.bitfield.cpui386 = 1;
7298 }
9103f4f4 7299 }
3e73aa7c
JH		 7300 else
7301 as_fatal (_("Unknown architecture"));
252b5132
RH		 7302 switch (OUTPUT_FLAVOR)
7303 {
872ce6ff
L		 7304#ifdef TE_PEP
7305 case bfd_target_coff_flavour:
7306 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "coff-i386";
7307 break;
7308#endif
4c63da97
AM		 7309#ifdef OBJ_MAYBE_AOUT
7310 case bfd_target_aout_flavour:
47926f60 7311 return AOUT_TARGET_FORMAT;
4c63da97
AM		 7312#endif
7313#ifdef OBJ_MAYBE_COFF
252b5132
RH		 7314 case bfd_target_coff_flavour:
7315 return "coff-i386";
4c63da97 7316#endif
3e73aa7c 7317#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 7318 case bfd_target_elf_flavour:
3e73aa7c 7319 {
e5cb08ac 7320 if (flag_code == CODE_64BIT)
4fa24527
JB		 7321 {
7322 object_64bit = 1;
7323 use_rela_relocations = 1;
7324 }
9d7cbccd 7325 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 7326 }
4c63da97 7327#endif
252b5132
RH		 7328 default:
7329 abort ();
7330 return NULL;
7331 }
7332}
7333
47926f60 7334#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 7335
7336#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 7337void
7338i386_elf_emit_arch_note (void)
a847613f 7339{
718ddfc0 7340 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 7341 {
7342 char *p;
7343 asection *seg = now_seg;
7344 subsegT subseg = now_subseg;
7345 Elf_Internal_Note i_note;
7346 Elf_External_Note e_note;
7347 asection *note_secp;
7348 int len;
7349
7350 /* Create the .note section. */
7351 note_secp = subseg_new (".note", 0);
7352 bfd_set_section_flags (stdoutput,
7353 note_secp,
7354 SEC_HAS_CONTENTS | SEC_READONLY);
7355
7356 /* Process the arch string. */
7357 len = strlen (cpu_arch_name);
7358
7359 i_note.namesz = len + 1;
7360 i_note.descsz = 0;
7361 i_note.type = NT_ARCH;
7362 p = frag_more (sizeof (e_note.namesz));
7363 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
7364 p = frag_more (sizeof (e_note.descsz));
7365 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
7366 p = frag_more (sizeof (e_note.type));
7367 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
7368 p = frag_more (len + 1);
7369 strcpy (p, cpu_arch_name);
7370
7371 frag_align (2, 0, 0);
7372
7373 subseg_set (seg, subseg);
7374 }
7375}
7376#endif
252b5132 7377\f
252b5132
RH		 7378symbolS *
7379md_undefined_symbol (name)
7380 char *name;
7381{
18dc2407
ILT		 7382 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
7383 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
7384 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
7385 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 7386 {
7387 if (!GOT_symbol)
7388 {
7389 if (symbol_find (name))
7390 as_bad (_("GOT already in symbol table"));
7391 GOT_symbol = symbol_new (name, undefined_section,
7392 (valueT) 0, &zero_address_frag);
7393 };
7394 return GOT_symbol;
7395 }
252b5132
RH		 7396 return 0;
7397}
7398
7399/* Round up a section size to the appropriate boundary. */
47926f60 7400
252b5132
RH		 7401valueT
7402md_section_align (segment, size)
ab9da554 7403 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7404 valueT size;
7405{
4c63da97
AM		 7406#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7407 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
7408 {
7409 /* For a.out, force the section size to be aligned. If we don't do
7410 this, BFD will align it for us, but it will not write out the
7411 final bytes of the section. This may be a bug in BFD, but it is
7412 easier to fix it here since that is how the other a.out targets
7413 work. */
7414 int align;
7415
7416 align = bfd_get_section_alignment (stdoutput, segment);
7417 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7418 }
252b5132
RH		 7419#endif
7420
7421 return size;
7422}
7423
7424/* On the i386, PC-relative offsets are relative to the start of the
7425 next instruction. That is, the address of the offset, plus its
7426 size, since the offset is always the last part of the insn. */
7427
7428long
e3bb37b5 7429md_pcrel_from (fixS *fixP)
252b5132
RH		 7430{
7431 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
7432}
7433
7434#ifndef I386COFF
7435
7436static void
e3bb37b5 7437s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 7438{
29b0f896 7439 int temp;
252b5132 7440
8a75718c
JB		 7441#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7442 if (IS_ELF)
7443 obj_elf_section_change_hook ();
7444#endif
252b5132
RH		 7445 temp = get_absolute_expression ();
7446 subseg_set (bss_section, (subsegT) temp);
7447 demand_empty_rest_of_line ();
7448}
7449
7450#endif
7451
252b5132 7452void
e3bb37b5 7453i386_validate_fix (fixS *fixp)
252b5132
RH		 7454{
7455 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
7456 {
23df1078
JH		 7457 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
7458 {
4fa24527 7459 if (!object_64bit)
23df1078
JH		 7460 abort ();
7461 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
7462 }
7463 else
7464 {
4fa24527 7465 if (!object_64bit)
d6ab8113
JB		 7466 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
7467 else
7468 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 7469 }
252b5132
RH		 7470 fixp->fx_subsy = 0;
7471 }
7472}
7473
252b5132
RH		 7474arelent *
7475tc_gen_reloc (section, fixp)
ab9da554 7476 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 7477 fixS *fixp;
7478{
7479 arelent *rel;
7480 bfd_reloc_code_real_type code;
7481
7482 switch (fixp->fx_r_type)
7483 {
3e73aa7c
JH		 7484 case BFD_RELOC_X86_64_PLT32:
7485 case BFD_RELOC_X86_64_GOT32:
7486 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 7487 case BFD_RELOC_386_PLT32:
7488 case BFD_RELOC_386_GOT32:
7489 case BFD_RELOC_386_GOTOFF:
7490 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 7491 case BFD_RELOC_386_TLS_GD:
7492 case BFD_RELOC_386_TLS_LDM:
7493 case BFD_RELOC_386_TLS_LDO_32:
7494 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7495 case BFD_RELOC_386_TLS_IE:
7496 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 7497 case BFD_RELOC_386_TLS_LE_32:
7498 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 7499 case BFD_RELOC_386_TLS_GOTDESC:
7500 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 7501 case BFD_RELOC_X86_64_TLSGD:
7502 case BFD_RELOC_X86_64_TLSLD:
7503 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7504 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 7505 case BFD_RELOC_X86_64_GOTTPOFF:
7506 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 7507 case BFD_RELOC_X86_64_TPOFF64:
7508 case BFD_RELOC_X86_64_GOTOFF64:
7509 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 7510 case BFD_RELOC_X86_64_GOT64:
7511 case BFD_RELOC_X86_64_GOTPCREL64:
7512 case BFD_RELOC_X86_64_GOTPC64:
7513 case BFD_RELOC_X86_64_GOTPLT64:
7514 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 7515 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7516 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 7517 case BFD_RELOC_RVA:
7518 case BFD_RELOC_VTABLE_ENTRY:
7519 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 7520#ifdef TE_PE
7521 case BFD_RELOC_32_SECREL:
7522#endif
252b5132
RH		 7523 code = fixp->fx_r_type;
7524 break;
dbbaec26
L		 7525 case BFD_RELOC_X86_64_32S:
7526 if (!fixp->fx_pcrel)
7527 {
7528 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
7529 code = fixp->fx_r_type;
7530 break;
7531 }
252b5132 7532 default:
93382f6d 7533 if (fixp->fx_pcrel)
252b5132 7534 {
93382f6d
AM		 7535 switch (fixp->fx_size)
7536 {
7537 default:
b091f402
AM		 7538 as_bad_where (fixp->fx_file, fixp->fx_line,
7539 _("can not do %d byte pc-relative relocation"),
7540 fixp->fx_size);
93382f6d
AM		 7541 code = BFD_RELOC_32_PCREL;
7542 break;
7543 case 1: code = BFD_RELOC_8_PCREL; break;
7544 case 2: code = BFD_RELOC_16_PCREL; break;
7545 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 7546#ifdef BFD64
7547 case 8: code = BFD_RELOC_64_PCREL; break;
7548#endif
93382f6d
AM		 7549 }
7550 }
7551 else
7552 {
7553 switch (fixp->fx_size)
7554 {
7555 default:
b091f402
AM		 7556 as_bad_where (fixp->fx_file, fixp->fx_line,
7557 _("can not do %d byte relocation"),
7558 fixp->fx_size);
93382f6d
AM		 7559 code = BFD_RELOC_32;
7560 break;
7561 case 1: code = BFD_RELOC_8; break;
7562 case 2: code = BFD_RELOC_16; break;
7563 case 4: code = BFD_RELOC_32; break;
937149dd 7564#ifdef BFD64
3e73aa7c 7565 case 8: code = BFD_RELOC_64; break;
937149dd 7566#endif
93382f6d 7567 }
252b5132
RH		 7568 }
7569 break;
7570 }
252b5132 7571
d182319b
JB		 7572 if ((code == BFD_RELOC_32
7573 || code == BFD_RELOC_32_PCREL
7574 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 7575 && GOT_symbol
7576 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 7577 {
4fa24527 7578 if (!object_64bit)
d6ab8113
JB		 7579 code = BFD_RELOC_386_GOTPC;
7580 else
7581 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 7582 }
7b81dfbb
AJ		 7583 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
7584 && GOT_symbol
7585 && fixp->fx_addsy == GOT_symbol)
7586 {
7587 code = BFD_RELOC_X86_64_GOTPC64;
7588 }
252b5132
RH		 7589
7590 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 7591 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
7592 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 7593
7594 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 7595
3e73aa7c
JH		 7596 if (!use_rela_relocations)
7597 {
7598 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
7599 vtable entry to be used in the relocation's section offset. */
7600 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
7601 rel->address = fixp->fx_offset;
252b5132 7602
c6682705 7603 rel->addend = 0;
3e73aa7c
JH		 7604 }
7605 /* Use the rela in 64bit mode. */
252b5132 7606 else
3e73aa7c 7607 {
062cd5e7
AS		 7608 if (!fixp->fx_pcrel)
7609 rel->addend = fixp->fx_offset;
7610 else
7611 switch (code)
7612 {
7613 case BFD_RELOC_X86_64_PLT32:
7614 case BFD_RELOC_X86_64_GOT32:
7615 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 7616 case BFD_RELOC_X86_64_TLSGD:
7617 case BFD_RELOC_X86_64_TLSLD:
7618 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 7619 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
7620 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 7621 rel->addend = fixp->fx_offset - fixp->fx_size;
7622 break;
7623 default:
7624 rel->addend = (section->vma
7625 - fixp->fx_size
7626 + fixp->fx_addnumber
7627 + md_pcrel_from (fixp));
7628 break;
7629 }
3e73aa7c
JH		 7630 }
7631
252b5132
RH		 7632 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
7633 if (rel->howto == NULL)
7634 {
7635 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 7636 _("cannot represent relocation type %s"),
252b5132
RH		 7637 bfd_get_reloc_code_name (code));
7638 /* Set howto to a garbage value so that we can keep going. */
7639 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
7640 assert (rel->howto != NULL);
7641 }
7642
7643 return rel;
7644}
7645
64a0c779
DN		 7646\f
7647/* Parse operands using Intel syntax. This implements a recursive descent
7648 parser based on the BNF grammar published in Appendix B of the MASM 6.1
7649 Programmer's Guide.
7650
7651 FIXME: We do not recognize the full operand grammar defined in the MASM
7652 documentation. In particular, all the structure/union and
7653 high-level macro operands are missing.
7654
7655 Uppercase words are terminals, lower case words are non-terminals.
7656 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
7657 bars '|' denote choices. Most grammar productions are implemented in
7658 functions called 'intel_<production>'.
7659
7660 Initial production is 'expr'.
7661
9306ca4a 7662 addOp + | -
64a0c779
DN		 7663
7664 alpha [a-zA-Z]
7665
9306ca4a
JB		 7666 binOp & | AND | \| | OR | ^ | XOR
7667
64a0c779
DN		 7668 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
7669
7670 constant digits [[ radixOverride ]]
7671
9306ca4a 7672 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD
64a0c779
DN		 7673
7674 digits decdigit
b77a7acd
AJ		 7675 | digits decdigit
7676 | digits hexdigit
64a0c779
DN		 7677
7678 decdigit [0-9]
7679
9306ca4a
JB		 7680 e04 e04 addOp e05
7681 | e05
7682
7683 e05 e05 binOp e06
b77a7acd 7684 | e06
64a0c779
DN		 7685
7686 e06 e06 mulOp e09
b77a7acd 7687 | e09
64a0c779
DN		 7688
7689 e09 OFFSET e10
a724f0f4
JB		 7690 | SHORT e10
7691 | + e10
7692 | - e10
9306ca4a
JB		 7693 | ~ e10
7694 | NOT e10
64a0c779
DN		 7695 | e09 PTR e10
7696 | e09 : e10
7697 | e10
7698
7699 e10 e10 [ expr ]
b77a7acd 7700 | e11
64a0c779
DN		 7701
7702 e11 ( expr )
b77a7acd 7703 | [ expr ]
64a0c779
DN		 7704 | constant
7705 | dataType
7706 | id
7707 | $
7708 | register
7709
a724f0f4 7710 => expr expr cmpOp e04
9306ca4a 7711 | e04
64a0c779
DN		 7712
7713 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 7714 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 7715
7716 hexdigit a | b | c | d | e | f
b77a7acd 7717 | A | B | C | D | E | F
64a0c779
DN		 7718
7719 id alpha
b77a7acd 7720 | id alpha
64a0c779
DN		 7721 | id decdigit
7722
9306ca4a 7723 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 7724
7725 quote " | '
7726
7727 register specialRegister
b77a7acd 7728 | gpRegister
64a0c779
DN		 7729 | byteRegister
7730
7731 segmentRegister CS | DS | ES | FS | GS | SS
7732
9306ca4a 7733 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 7734 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 7735 | TR3 | TR4 | TR5 | TR6 | TR7
7736
64a0c779
DN		 7737 We simplify the grammar in obvious places (e.g., register parsing is
7738 done by calling parse_register) and eliminate immediate left recursion
7739 to implement a recursive-descent parser.
7740
a724f0f4
JB		 7741 expr e04 expr'
7742
7743 expr' cmpOp e04 expr'
7744 | Empty
9306ca4a
JB		 7745
7746 e04 e05 e04'
7747
7748 e04' addOp e05 e04'
7749 | Empty
64a0c779
DN		 7750
7751 e05 e06 e05'
7752
9306ca4a 7753 e05' binOp e06 e05'
b77a7acd 7754 | Empty
64a0c779
DN		 7755
7756 e06 e09 e06'
7757
7758 e06' mulOp e09 e06'
b77a7acd 7759 | Empty
64a0c779
DN		 7760
7761 e09 OFFSET e10 e09'
a724f0f4
JB		 7762 | SHORT e10'
7763 | + e10'
7764 | - e10'
7765 | ~ e10'
7766 | NOT e10'
b77a7acd 7767 | e10 e09'
64a0c779
DN		 7768
7769 e09' PTR e10 e09'
b77a7acd 7770 | : e10 e09'
64a0c779
DN		 7771 | Empty
7772
7773 e10 e11 e10'
7774
7775 e10' [ expr ] e10'
b77a7acd 7776 | Empty
64a0c779
DN		 7777
7778 e11 ( expr )
b77a7acd 7779 | [ expr ]
64a0c779
DN		 7780 | BYTE
7781 | WORD
7782 | DWORD
9306ca4a 7783 | FWORD
64a0c779 7784 | QWORD
9306ca4a
JB		 7785 | TBYTE
7786 | OWORD
7787 | XMMWORD
64a0c779
DN		 7788 | .
7789 | $
7790 | register
7791 | id
7792 | constant */
7793
7794/* Parsing structure for the intel syntax parser. Used to implement the
7795 semantic actions for the operand grammar. */
7796struct intel_parser_s
7797 {
7798 char *op_string; /* The string being parsed. */
7799 int got_a_float; /* Whether the operand is a float. */
4a1805b1 7800 int op_modifier; /* Operand modifier. */
64a0c779 7801 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 7802 int in_offset; /* >=1 if parsing operand of offset. */
7803 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 7804 const reg_entry *reg; /* Last register reference found. */
7805 char *disp; /* Displacement string being built. */
a724f0f4 7806 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 7807 };
7808
7809static struct intel_parser_s intel_parser;
7810
7811/* Token structure for parsing intel syntax. */
7812struct intel_token
7813 {
7814 int code; /* Token code. */
7815 const reg_entry *reg; /* Register entry for register tokens. */
7816 char *str; /* String representation. */
7817 };
7818
7819static struct intel_token cur_token, prev_token;
7820
50705ef4
AM		 7821/* Token codes for the intel parser. Since T_SHORT is already used
7822 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 7823#define T_NIL -1
7824#define T_CONST 1
7825#define T_REG 2
7826#define T_BYTE 3
7827#define T_WORD 4
9306ca4a
JB		 7828#define T_DWORD 5
7829#define T_FWORD 6
7830#define T_QWORD 7
7831#define T_TBYTE 8
7832#define T_XMMWORD 9
50705ef4 7833#undef T_SHORT
9306ca4a
JB		 7834#define T_SHORT 10
7835#define T_OFFSET 11
7836#define T_PTR 12
7837#define T_ID 13
7838#define T_SHL 14
7839#define T_SHR 15
64a0c779
DN		 7840
7841/* Prototypes for intel parser functions. */
e3bb37b5
L		 7842static int intel_match_token (int);
7843static void intel_putback_token (void);
7844static void intel_get_token (void);
7845static int intel_expr (void);
7846static int intel_e04 (void);
7847static int intel_e05 (void);
7848static int intel_e06 (void);
7849static int intel_e09 (void);
7850static int intel_e10 (void);
7851static int intel_e11 (void);
64a0c779 7852
64a0c779 7853static int
e3bb37b5 7854i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 7855{
7856 int ret;
7857 char *p;
7858
a724f0f4
JB		 7859 p = intel_parser.op_string = xstrdup (operand_string);
7860 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
7861
7862 for (;;)
64a0c779 7863 {
a724f0f4
JB		 7864 /* Initialize token holders. */
7865 cur_token.code = prev_token.code = T_NIL;
7866 cur_token.reg = prev_token.reg = NULL;
7867 cur_token.str = prev_token.str = NULL;
7868
7869 /* Initialize parser structure. */
7870 intel_parser.got_a_float = got_a_float;
7871 intel_parser.op_modifier = 0;
7872 intel_parser.is_mem = 0;
7873 intel_parser.in_offset = 0;
7874 intel_parser.in_bracket = 0;
7875 intel_parser.reg = NULL;
7876 intel_parser.disp[0] = '\0';
7877 intel_parser.next_operand = NULL;
7878
7879 /* Read the first token and start the parser. */
7880 intel_get_token ();
7881 ret = intel_expr ();
7882
7883 if (!ret)
7884 break;
7885
9306ca4a
JB		 7886 if (cur_token.code != T_NIL)
7887 {
7888 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
7889 current_templates->start->name, cur_token.str);
7890 ret = 0;
7891 }
64a0c779
DN		 7892 /* If we found a memory reference, hand it over to i386_displacement
7893 to fill in the rest of the operand fields. */
9306ca4a 7894 else if (intel_parser.is_mem)
64a0c779
DN		 7895 {
7896 if ((i.mem_operands == 1
40fb9820 7897 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 7898 || i.mem_operands == 2)
7899 {
7900 as_bad (_("too many memory references for '%s'"),
7901 current_templates->start->name);
7902 ret = 0;
7903 }
7904 else
7905 {
7906 char *s = intel_parser.disp;
5c07affc 7907 i.types[this_operand].bitfield.mem = 1;
64a0c779
DN		 7908 i.mem_operands++;
7909
a724f0f4
JB		 7910 if (!quiet_warnings && intel_parser.is_mem < 0)
7911 /* See the comments in intel_bracket_expr. */
7912 as_warn (_("Treating `%s' as memory reference"), operand_string);
7913
64a0c779
DN		 7914 /* Add the displacement expression. */
7915 if (*s != '\0')
a4622f40
AM		 7916 ret = i386_displacement (s, s + strlen (s));
7917 if (ret)
a724f0f4
JB		 7918 {
7919 /* Swap base and index in 16-bit memory operands like
7920 [si+bx]. Since i386_index_check is also used in AT&T
7921 mode we have to do that here. */
7922 if (i.base_reg
7923 && i.index_reg
40fb9820
L		 7924 && i.base_reg->reg_type.bitfield.reg16
7925 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 7926 && i.base_reg->reg_num >= 6
7927 && i.index_reg->reg_num < 6)
7928 {
7929 const reg_entry *base = i.index_reg;
7930
7931 i.index_reg = i.base_reg;
7932 i.base_reg = base;
7933 }
7934 ret = i386_index_check (operand_string);
7935 }
64a0c779
DN		 7936 }
7937 }
7938
7939 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 7940 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779
DN		 7941 || intel_parser.reg == NULL)
7942 ret = i386_immediate (intel_parser.disp);
a724f0f4
JB		 7943
7944 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 7945 ret = 0;
a724f0f4
JB		 7946 if (!ret || !intel_parser.next_operand)
7947 break;
7948 intel_parser.op_string = intel_parser.next_operand;
7949 this_operand = i.operands++;
7d5e4556 7950 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 7951 }
7952
7953 free (p);
7954 free (intel_parser.disp);
7955
7956 return ret;
7957}
7958
a724f0f4
JB		 7959#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
7960
7961/* expr e04 expr'
7962
7963 expr' cmpOp e04 expr'
7964 | Empty */
64a0c779 7965static int
e3bb37b5 7966intel_expr (void)
64a0c779 7967{
a724f0f4
JB		 7968 /* XXX Implement the comparison operators. */
7969 return intel_e04 ();
9306ca4a
JB		 7970}
7971
a724f0f4 7972/* e04 e05 e04'
9306ca4a 7973
a724f0f4 7974 e04' addOp e05 e04'
9306ca4a
JB		 7975 | Empty */
7976static int
e3bb37b5 7977intel_e04 (void)
9306ca4a 7978{
a724f0f4 7979 int nregs = -1;
9306ca4a 7980
a724f0f4 7981 for (;;)
9306ca4a 7982 {
a724f0f4
JB		 7983 if (!intel_e05())
7984 return 0;
9306ca4a 7985
a724f0f4
JB		 7986 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
7987 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 7988
a724f0f4
JB		 7989 if (cur_token.code == '+')
7990 nregs = -1;
7991 else if (cur_token.code == '-')
7992 nregs = NUM_ADDRESS_REGS;
7993 else
7994 return 1;
64a0c779 7995
a724f0f4
JB		 7996 strcat (intel_parser.disp, cur_token.str);
7997 intel_match_token (cur_token.code);
7998 }
64a0c779
DN		 7999}
8000
64a0c779
DN		 8001/* e05 e06 e05'
8002
9306ca4a 8003 e05' binOp e06 e05'
64a0c779
DN		 8004 | Empty */
8005static int
e3bb37b5 8006intel_e05 (void)
64a0c779 8007{
a724f0f4 8008 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8009
a724f0f4 8010 for (;;)
64a0c779 8011 {
a724f0f4
JB		 8012 if (!intel_e06())
8013 return 0;
8014
4eed87de
AM		 8015 if (cur_token.code == '&'
8016 || cur_token.code == '|'
8017 || cur_token.code == '^')
a724f0f4
JB		 8018 {
8019 char str[2];
8020
8021 str[0] = cur_token.code;
8022 str[1] = 0;
8023 strcat (intel_parser.disp, str);
8024 }
8025 else
8026 break;
9306ca4a 8027
64a0c779
DN		 8028 intel_match_token (cur_token.code);
8029
a724f0f4
JB		 8030 if (nregs < 0)
8031 nregs = ~nregs;
64a0c779 8032 }
a724f0f4
JB		 8033 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8034 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
8035 return 1;
4a1805b1 8036}
64a0c779
DN		 8037
8038/* e06 e09 e06'
8039
8040 e06' mulOp e09 e06'
b77a7acd 8041 | Empty */
64a0c779 8042static int
e3bb37b5 8043intel_e06 (void)
64a0c779 8044{
a724f0f4 8045 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 8046
a724f0f4 8047 for (;;)
64a0c779 8048 {
a724f0f4
JB		 8049 if (!intel_e09())
8050 return 0;
9306ca4a 8051
4eed87de
AM		 8052 if (cur_token.code == '*'
8053 || cur_token.code == '/'
8054 || cur_token.code == '%')
a724f0f4
JB		 8055 {
8056 char str[2];
9306ca4a 8057
a724f0f4
JB		 8058 str[0] = cur_token.code;
8059 str[1] = 0;
8060 strcat (intel_parser.disp, str);
8061 }
8062 else if (cur_token.code == T_SHL)
8063 strcat (intel_parser.disp, "<<");
8064 else if (cur_token.code == T_SHR)
8065 strcat (intel_parser.disp, ">>");
8066 else
8067 break;
9306ca4a 8068
64e74474 8069 intel_match_token (cur_token.code);
64a0c779 8070
a724f0f4
JB		 8071 if (nregs < 0)
8072 nregs = ~nregs;
64a0c779 8073 }
a724f0f4
JB		 8074 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8075 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
8076 return 1;
64a0c779
DN		 8077}
8078
a724f0f4
JB		 8079/* e09 OFFSET e09
8080 | SHORT e09
8081 | + e09
8082 | - e09
8083 | ~ e09
8084 | NOT e09
9306ca4a
JB		 8085 | e10 e09'
8086
64a0c779 8087 e09' PTR e10 e09'
b77a7acd 8088 | : e10 e09'
64a0c779
DN		 8089 | Empty */
8090static int
e3bb37b5 8091intel_e09 (void)
64a0c779 8092{
a724f0f4
JB		 8093 int nregs = ~NUM_ADDRESS_REGS;
8094 int in_offset = 0;
8095
8096 for (;;)
64a0c779 8097 {
a724f0f4
JB		 8098 /* Don't consume constants here. */
8099 if (cur_token.code == '+' || cur_token.code == '-')
8100 {
8101 /* Need to look one token ahead - if the next token
8102 is a constant, the current token is its sign. */
8103 int next_code;
8104
8105 intel_match_token (cur_token.code);
8106 next_code = cur_token.code;
8107 intel_putback_token ();
8108 if (next_code == T_CONST)
8109 break;
8110 }
8111
8112 /* e09 OFFSET e09 */
8113 if (cur_token.code == T_OFFSET)
8114 {
8115 if (!in_offset++)
8116 ++intel_parser.in_offset;
8117 }
8118
8119 /* e09 SHORT e09 */
8120 else if (cur_token.code == T_SHORT)
8121 intel_parser.op_modifier |= 1 << T_SHORT;
8122
8123 /* e09 + e09 */
8124 else if (cur_token.code == '+')
8125 strcat (intel_parser.disp, "+");
8126
8127 /* e09 - e09
8128 | ~ e09
8129 | NOT e09 */
8130 else if (cur_token.code == '-' || cur_token.code == '~')
8131 {
8132 char str[2];
64a0c779 8133
a724f0f4
JB		 8134 if (nregs < 0)
8135 nregs = ~nregs;
8136 str[0] = cur_token.code;
8137 str[1] = 0;
8138 strcat (intel_parser.disp, str);
8139 }
8140
8141 /* e09 e10 e09' */
8142 else
8143 break;
8144
8145 intel_match_token (cur_token.code);
64a0c779
DN		 8146 }
8147
a724f0f4 8148 for (;;)
9306ca4a 8149 {
a724f0f4
JB		 8150 if (!intel_e10 ())
8151 return 0;
9306ca4a 8152
a724f0f4
JB		 8153 /* e09' PTR e10 e09' */
8154 if (cur_token.code == T_PTR)
8155 {
8156 char suffix;
9306ca4a 8157
a724f0f4 8158 if (prev_token.code == T_BYTE)
7d5e4556
L		 8159 {
8160 suffix = BYTE_MNEM_SUFFIX;
8161 i.types[this_operand].bitfield.byte = 1;
8162 }
9306ca4a 8163
a724f0f4
JB		 8164 else if (prev_token.code == T_WORD)
8165 {
8166 if (current_templates->start->name[0] == 'l'
8167 && current_templates->start->name[2] == 's'
8168 && current_templates->start->name[3] == 0)
8169 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8170 else if (intel_parser.got_a_float == 2) /* "fi..." */
8171 suffix = SHORT_MNEM_SUFFIX;
8172 else
8173 suffix = WORD_MNEM_SUFFIX;
7d5e4556 8174 i.types[this_operand].bitfield.word = 1;
a724f0f4 8175 }
64a0c779 8176
a724f0f4
JB		 8177 else if (prev_token.code == T_DWORD)
8178 {
8179 if (current_templates->start->name[0] == 'l'
8180 && current_templates->start->name[2] == 's'
8181 && current_templates->start->name[3] == 0)
8182 suffix = WORD_MNEM_SUFFIX;
8183 else if (flag_code == CODE_16BIT
40fb9820
L		 8184 && (current_templates->start->opcode_modifier.jump
8185 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 8186 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8187 else if (intel_parser.got_a_float == 1) /* "f..." */
8188 suffix = SHORT_MNEM_SUFFIX;
8189 else
8190 suffix = LONG_MNEM_SUFFIX;
7d5e4556 8191 i.types[this_operand].bitfield.dword = 1;
a724f0f4 8192 }
9306ca4a 8193
a724f0f4
JB		 8194 else if (prev_token.code == T_FWORD)
8195 {
8196 if (current_templates->start->name[0] == 'l'
8197 && current_templates->start->name[2] == 's'
8198 && current_templates->start->name[3] == 0)
8199 suffix = LONG_MNEM_SUFFIX;
8200 else if (!intel_parser.got_a_float)
8201 {
8202 if (flag_code == CODE_16BIT)
8203 add_prefix (DATA_PREFIX_OPCODE);
8204 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8205 }
8206 else
8207 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 8208 i.types[this_operand].bitfield.fword = 1;
a724f0f4 8209 }
64a0c779 8210
a724f0f4
JB		 8211 else if (prev_token.code == T_QWORD)
8212 {
8213 if (intel_parser.got_a_float == 1) /* "f..." */
8214 suffix = LONG_MNEM_SUFFIX;
8215 else
7d5e4556
L		 8216 suffix = QWORD_MNEM_SUFFIX;
8217 i.types[this_operand].bitfield.qword = 1;
a724f0f4 8218 }
64a0c779 8219
a724f0f4
JB		 8220 else if (prev_token.code == T_TBYTE)
8221 {
8222 if (intel_parser.got_a_float == 1)
8223 suffix = LONG_DOUBLE_MNEM_SUFFIX;
8224 else
8225 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
8226 }
9306ca4a 8227
a724f0f4 8228 else if (prev_token.code == T_XMMWORD)
9306ca4a 8229 {
582d5edd 8230 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 8231 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 8232 }
64a0c779 8233
f16b83df 8234 else
a724f0f4
JB		 8235 {
8236 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
8237 return 0;
8238 }
8239
7d5e4556
L		 8240 i.types[this_operand].bitfield.unspecified = 0;
8241
435acd52
JB		 8242 /* Operands for jump/call using 'ptr' notation denote absolute
8243 addresses. */
40fb9820
L		 8244 if (current_templates->start->opcode_modifier.jump
8245 || current_templates->start->opcode_modifier.jumpdword)
8246 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8247
a724f0f4
JB		 8248 if (current_templates->start->base_opcode == 0x8d /* lea */)
8249 ;
8250 else if (!i.suffix)
8251 i.suffix = suffix;
8252 else if (i.suffix != suffix)
8253 {
8254 as_bad (_("Conflicting operand modifiers"));
8255 return 0;
8256 }
64a0c779 8257
9306ca4a
JB		 8258 }
8259
a724f0f4
JB		 8260 /* e09' : e10 e09' */
8261 else if (cur_token.code == ':')
9306ca4a 8262 {
a724f0f4
JB		 8263 if (prev_token.code != T_REG)
8264 {
8265 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
8266 segment/group identifier (which we don't have), using comma
8267 as the operand separator there is even less consistent, since
8268 there all branches only have a single operand. */
8269 if (this_operand != 0
8270 || intel_parser.in_offset
8271 || intel_parser.in_bracket
40fb9820
L		 8272 || (!current_templates->start->opcode_modifier.jump
8273 && !current_templates->start->opcode_modifier.jumpdword
8274 && !current_templates->start->opcode_modifier.jumpintersegment
8275 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 8276 return intel_match_token (T_NIL);
8277 /* Remember the start of the 2nd operand and terminate 1st
8278 operand here.
8279 XXX This isn't right, yet (when SSSS:OOOO is right operand of
8280 another expression), but it gets at least the simplest case
8281 (a plain number or symbol on the left side) right. */
8282 intel_parser.next_operand = intel_parser.op_string;
8283 *--intel_parser.op_string = '\0';
8284 return intel_match_token (':');
8285 }
9306ca4a 8286 }
64a0c779 8287
a724f0f4 8288 /* e09' Empty */
64a0c779 8289 else
a724f0f4 8290 break;
64a0c779 8291
a724f0f4
JB		 8292 intel_match_token (cur_token.code);
8293
8294 }
8295
8296 if (in_offset)
8297 {
8298 --intel_parser.in_offset;
8299 if (nregs < 0)
8300 nregs = ~nregs;
8301 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 8302 {
a724f0f4 8303 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 8304 return 0;
8305 }
a724f0f4
JB		 8306 intel_parser.op_modifier |= 1 << T_OFFSET;
8307 }
9306ca4a 8308
a724f0f4
JB		 8309 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
8310 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
8311 return 1;
8312}
64a0c779 8313
a724f0f4 8314static int
e3bb37b5 8315intel_bracket_expr (void)
a724f0f4
JB		 8316{
8317 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
8318 const char *start = intel_parser.op_string;
8319 int len;
8320
8321 if (i.op[this_operand].regs)
8322 return intel_match_token (T_NIL);
8323
8324 intel_match_token ('[');
8325
8326 /* Mark as a memory operand only if it's not already known to be an
8327 offset expression. If it's an offset expression, we need to keep
8328 the brace in. */
8329 if (!intel_parser.in_offset)
8330 {
8331 ++intel_parser.in_bracket;
435acd52
JB		 8332
8333 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 8334 if (current_templates->start->opcode_modifier.jump
8335 || current_templates->start->opcode_modifier.jumpdword)
8336 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 8337
a724f0f4
JB		 8338 /* Unfortunately gas always diverged from MASM in a respect that can't
8339 be easily fixed without risking to break code sequences likely to be
8340 encountered (the testsuite even check for this): MASM doesn't consider
8341 an expression inside brackets unconditionally as a memory reference.
8342 When that is e.g. a constant, an offset expression, or the sum of the
8343 two, this is still taken as a constant load. gas, however, always
8344 treated these as memory references. As a compromise, we'll try to make
8345 offset expressions inside brackets work the MASM way (since that's
8346 less likely to be found in real world code), but make constants alone
8347 continue to work the traditional gas way. In either case, issue a
8348 warning. */
8349 intel_parser.op_modifier &= ~was_offset;
64a0c779 8350 }
a724f0f4 8351 else
64e74474 8352 strcat (intel_parser.disp, "[");
a724f0f4
JB		 8353
8354 /* Add a '+' to the displacement string if necessary. */
8355 if (*intel_parser.disp != '\0'
8356 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
8357 strcat (intel_parser.disp, "+");
64a0c779 8358
a724f0f4
JB		 8359 if (intel_expr ()
8360 && (len = intel_parser.op_string - start - 1,
8361 intel_match_token (']')))
64a0c779 8362 {
a724f0f4
JB		 8363 /* Preserve brackets when the operand is an offset expression. */
8364 if (intel_parser.in_offset)
8365 strcat (intel_parser.disp, "]");
8366 else
8367 {
8368 --intel_parser.in_bracket;
8369 if (i.base_reg || i.index_reg)
8370 intel_parser.is_mem = 1;
8371 if (!intel_parser.is_mem)
8372 {
8373 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8374 /* Defer the warning until all of the operand was parsed. */
8375 intel_parser.is_mem = -1;
8376 else if (!quiet_warnings)
4eed87de
AM		 8377 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
8378 len, start, len, start);
a724f0f4
JB		 8379 }
8380 }
8381 intel_parser.op_modifier |= was_offset;
64a0c779 8382
a724f0f4 8383 return 1;
64a0c779 8384 }
a724f0f4 8385 return 0;
64a0c779
DN		 8386}
8387
8388/* e10 e11 e10'
8389
8390 e10' [ expr ] e10'
b77a7acd 8391 | Empty */
64a0c779 8392static int
e3bb37b5 8393intel_e10 (void)
64a0c779 8394{
a724f0f4
JB		 8395 if (!intel_e11 ())
8396 return 0;
64a0c779 8397
a724f0f4 8398 while (cur_token.code == '[')
64a0c779 8399 {
a724f0f4 8400 if (!intel_bracket_expr ())
21d6c4af 8401 return 0;
64a0c779
DN		 8402 }
8403
a724f0f4 8404 return 1;
64a0c779
DN		 8405}
8406
64a0c779 8407/* e11 ( expr )
b77a7acd 8408 | [ expr ]
64a0c779
DN		 8409 | BYTE
8410 | WORD
8411 | DWORD
9306ca4a 8412 | FWORD
64a0c779 8413 | QWORD
9306ca4a
JB		 8414 | TBYTE
8415 | OWORD
8416 | XMMWORD
4a1805b1 8417 | $
64a0c779
DN		 8418 | .
8419 | register
8420 | id
8421 | constant */
8422static int
e3bb37b5 8423intel_e11 (void)
64a0c779 8424{
a724f0f4 8425 switch (cur_token.code)
64a0c779 8426 {
a724f0f4
JB		 8427 /* e11 ( expr ) */
8428 case '(':
64a0c779
DN		 8429 intel_match_token ('(');
8430 strcat (intel_parser.disp, "(");
8431
8432 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 8433 {
8434 strcat (intel_parser.disp, ")");
8435 return 1;
8436 }
a724f0f4 8437 return 0;
4a1805b1 8438
a724f0f4
JB		 8439 /* e11 [ expr ] */
8440 case '[':
a724f0f4 8441 return intel_bracket_expr ();
64a0c779 8442
a724f0f4
JB		 8443 /* e11 $
8444 | . */
8445 case '.':
64a0c779
DN		 8446 strcat (intel_parser.disp, cur_token.str);
8447 intel_match_token (cur_token.code);
21d6c4af
DN		 8448
8449 /* Mark as a memory operand only if it's not already known to be an
8450 offset expression. */
a724f0f4 8451 if (!intel_parser.in_offset)
21d6c4af 8452 intel_parser.is_mem = 1;
64a0c779
DN		 8453
8454 return 1;
64a0c779 8455
a724f0f4
JB		 8456 /* e11 register */
8457 case T_REG:
8458 {
8459 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 8460
a724f0f4 8461 intel_match_token (T_REG);
64a0c779 8462
a724f0f4
JB		 8463 /* Check for segment change. */
8464 if (cur_token.code == ':')
8465 {
40fb9820
L		 8466 if (!reg->reg_type.bitfield.sreg2
8467 && !reg->reg_type.bitfield.sreg3)
a724f0f4 8468 {
4eed87de
AM		 8469 as_bad (_("`%s' is not a valid segment register"),
8470 reg->reg_name);
a724f0f4
JB		 8471 return 0;
8472 }
8473 else if (i.seg[i.mem_operands])
8474 as_warn (_("Extra segment override ignored"));
8475 else
8476 {
8477 if (!intel_parser.in_offset)
8478 intel_parser.is_mem = 1;
8479 switch (reg->reg_num)
8480 {
8481 case 0:
8482 i.seg[i.mem_operands] = &es;
8483 break;
8484 case 1:
8485 i.seg[i.mem_operands] = &cs;
8486 break;
8487 case 2:
8488 i.seg[i.mem_operands] = &ss;
8489 break;
8490 case 3:
8491 i.seg[i.mem_operands] = &ds;
8492 break;
8493 case 4:
8494 i.seg[i.mem_operands] = &fs;
8495 break;
8496 case 5:
8497 i.seg[i.mem_operands] = &gs;
8498 break;
8499 }
8500 }
8501 }
64a0c779 8502
a724f0f4
JB		 8503 /* Not a segment register. Check for register scaling. */
8504 else if (cur_token.code == '*')
8505 {
8506 if (!intel_parser.in_bracket)
8507 {
8508 as_bad (_("Register scaling only allowed in memory operands"));
8509 return 0;
8510 }
64a0c779 8511
40fb9820 8512 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 8513 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
8514 else if (i.index_reg)
8515 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 8516
a724f0f4
JB		 8517 /* What follows must be a valid scale. */
8518 intel_match_token ('*');
8519 i.index_reg = reg;
40fb9820 8520 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 8521
a724f0f4
JB		 8522 /* Set the scale after setting the register (otherwise,
8523 i386_scale will complain) */
8524 if (cur_token.code == '+' || cur_token.code == '-')
8525 {
8526 char *str, sign = cur_token.code;
8527 intel_match_token (cur_token.code);
8528 if (cur_token.code != T_CONST)
8529 {
8530 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8531 cur_token.str);
8532 return 0;
8533 }
8534 str = (char *) xmalloc (strlen (cur_token.str) + 2);
8535 strcpy (str + 1, cur_token.str);
8536 *str = sign;
8537 if (!i386_scale (str))
8538 return 0;
8539 free (str);
8540 }
8541 else if (!i386_scale (cur_token.str))
64a0c779 8542 return 0;
a724f0f4
JB		 8543 intel_match_token (cur_token.code);
8544 }
64a0c779 8545
a724f0f4
JB		 8546 /* No scaling. If this is a memory operand, the register is either a
8547 base register (first occurrence) or an index register (second
8548 occurrence). */
7b0441f6 8549 else if (intel_parser.in_bracket)
a724f0f4 8550 {
64a0c779 8551
a724f0f4
JB		 8552 if (!i.base_reg)
8553 i.base_reg = reg;
8554 else if (!i.index_reg)
8555 i.index_reg = reg;
8556 else
8557 {
8558 as_bad (_("Too many register references in memory operand"));
8559 return 0;
8560 }
64a0c779 8561
40fb9820 8562 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 8563 }
4a1805b1 8564
4d1bb795
JB		 8565 /* It's neither base nor index. */
8566 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 8567 {
40fb9820
L		 8568 i386_operand_type temp = reg->reg_type;
8569 temp.bitfield.baseindex = 0;
c6fb90c8
L		 8570 i.types[this_operand] = operand_type_or (i.types[this_operand],
8571 temp);
7d5e4556 8572 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 8573 i.op[this_operand].regs = reg;
8574 i.reg_operands++;
8575 }
8576 else
8577 {
8578 as_bad (_("Invalid use of register"));
8579 return 0;
8580 }
64a0c779 8581
a724f0f4
JB		 8582 /* Since registers are not part of the displacement string (except
8583 when we're parsing offset operands), we may need to remove any
8584 preceding '+' from the displacement string. */
8585 if (*intel_parser.disp != '\0'
8586 && !intel_parser.in_offset)
8587 {
8588 char *s = intel_parser.disp;
8589 s += strlen (s) - 1;
8590 if (*s == '+')
8591 *s = '\0';
8592 }
4a1805b1 8593
a724f0f4
JB		 8594 return 1;
8595 }
8596
8597 /* e11 BYTE
8598 | WORD
8599 | DWORD
8600 | FWORD
8601 | QWORD
8602 | TBYTE
8603 | OWORD
8604 | XMMWORD */
8605 case T_BYTE:
8606 case T_WORD:
8607 case T_DWORD:
8608 case T_FWORD:
8609 case T_QWORD:
8610 case T_TBYTE:
8611 case T_XMMWORD:
8612 intel_match_token (cur_token.code);
64a0c779 8613
a724f0f4
JB		 8614 if (cur_token.code == T_PTR)
8615 return 1;
8616
8617 /* It must have been an identifier. */
8618 intel_putback_token ();
8619 cur_token.code = T_ID;
8620 /* FALLTHRU */
8621
8622 /* e11 id
8623 | constant */
8624 case T_ID:
8625 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 8626 {
8627 symbolS *symbolP;
8628
a724f0f4
JB		 8629 /* The identifier represents a memory reference only if it's not
8630 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 8631 symbolP = symbol_find(cur_token.str);
8632 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
8633 intel_parser.is_mem = 1;
8634 }
a724f0f4 8635 /* FALLTHRU */
64a0c779 8636
a724f0f4
JB		 8637 case T_CONST:
8638 case '-':
8639 case '+':
8640 {
8641 char *save_str, sign = 0;
64a0c779 8642
a724f0f4
JB		 8643 /* Allow constants that start with `+' or `-'. */
8644 if (cur_token.code == '-' || cur_token.code == '+')
8645 {
8646 sign = cur_token.code;
8647 intel_match_token (cur_token.code);
8648 if (cur_token.code != T_CONST)
8649 {
8650 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
8651 cur_token.str);
8652 return 0;
8653 }
8654 }
64a0c779 8655
a724f0f4
JB		 8656 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
8657 strcpy (save_str + !!sign, cur_token.str);
8658 if (sign)
8659 *save_str = sign;
64a0c779 8660
a724f0f4
JB		 8661 /* Get the next token to check for register scaling. */
8662 intel_match_token (cur_token.code);
64a0c779 8663
4eed87de
AM		 8664 /* Check if this constant is a scaling factor for an
8665 index register. */
a724f0f4
JB		 8666 if (cur_token.code == '*')
8667 {
8668 if (intel_match_token ('*') && cur_token.code == T_REG)
8669 {
8670 const reg_entry *reg = cur_token.reg;
8671
8672 if (!intel_parser.in_bracket)
8673 {
4eed87de
AM		 8674 as_bad (_("Register scaling only allowed "
8675 "in memory operands"));
a724f0f4
JB		 8676 return 0;
8677 }
8678
4eed87de
AM		 8679 /* Disallow things like [1*si].
8680 sp and esp are invalid as index. */
40fb9820 8681 if (reg->reg_type.bitfield.reg16)
4eed87de 8682 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 8683 else if (i.index_reg)
4eed87de 8684 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 8685
8686 /* The constant is followed by `* reg', so it must be
8687 a valid scale. */
8688 i.index_reg = reg;
40fb9820 8689 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 8690
8691 /* Set the scale after setting the register (otherwise,
8692 i386_scale will complain) */
8693 if (!i386_scale (save_str))
64a0c779 8694 return 0;
a724f0f4
JB		 8695 intel_match_token (T_REG);
8696
8697 /* Since registers are not part of the displacement
8698 string, we may need to remove any preceding '+' from
8699 the displacement string. */
8700 if (*intel_parser.disp != '\0')
8701 {
8702 char *s = intel_parser.disp;
8703 s += strlen (s) - 1;
8704 if (*s == '+')
8705 *s = '\0';
8706 }
8707
8708 free (save_str);
8709
8710 return 1;
8711 }
64a0c779 8712
a724f0f4
JB		 8713 /* The constant was not used for register scaling. Since we have
8714 already consumed the token following `*' we now need to put it
8715 back in the stream. */
64a0c779 8716 intel_putback_token ();
a724f0f4 8717 }
64a0c779 8718
a724f0f4
JB		 8719 /* Add the constant to the displacement string. */
8720 strcat (intel_parser.disp, save_str);
8721 free (save_str);
64a0c779 8722
a724f0f4
JB		 8723 return 1;
8724 }
64a0c779
DN		 8725 }
8726
64a0c779
DN		 8727 as_bad (_("Unrecognized token '%s'"), cur_token.str);
8728 return 0;
8729}
8730
64a0c779
DN		 8731/* Match the given token against cur_token. If they match, read the next
8732 token from the operand string. */
8733static int
e3bb37b5 8734intel_match_token (int code)
64a0c779
DN		 8735{
8736 if (cur_token.code == code)
8737 {
8738 intel_get_token ();
8739 return 1;
8740 }
8741 else
8742 {
0477af35 8743 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 8744 return 0;
8745 }
8746}
8747
64a0c779
DN		 8748/* Read a new token from intel_parser.op_string and store it in cur_token. */
8749static void
e3bb37b5 8750intel_get_token (void)
64a0c779
DN		 8751{
8752 char *end_op;
8753 const reg_entry *reg;
8754 struct intel_token new_token;
8755
8756 new_token.code = T_NIL;
8757 new_token.reg = NULL;
8758 new_token.str = NULL;
8759
4a1805b1 8760 /* Free the memory allocated to the previous token and move
64a0c779
DN		 8761 cur_token to prev_token. */
8762 if (prev_token.str)
8763 free (prev_token.str);
8764
8765 prev_token = cur_token;
8766
8767 /* Skip whitespace. */
8768 while (is_space_char (*intel_parser.op_string))
8769 intel_parser.op_string++;
8770
8771 /* Return an empty token if we find nothing else on the line. */
8772 if (*intel_parser.op_string == '\0')
8773 {
8774 cur_token = new_token;
8775 return;
8776 }
8777
8778 /* The new token cannot be larger than the remainder of the operand
8779 string. */
a724f0f4 8780 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 8781 new_token.str[0] = '\0';
8782
8783 if (strchr ("0123456789", *intel_parser.op_string))
8784 {
8785 char *p = new_token.str;
8786 char *q = intel_parser.op_string;
8787 new_token.code = T_CONST;
8788
8789 /* Allow any kind of identifier char to encompass floating point and
8790 hexadecimal numbers. */
8791 while (is_identifier_char (*q))
8792 *p++ = *q++;
8793 *p = '\0';
8794
8795 /* Recognize special symbol names [0-9][bf]. */
8796 if (strlen (intel_parser.op_string) == 2
4a1805b1 8797 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 8798 || intel_parser.op_string[1] == 'f'))
8799 new_token.code = T_ID;
8800 }
8801
4d1bb795 8802 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 8803 {
4d1bb795
JB		 8804 size_t len = end_op - intel_parser.op_string;
8805
64a0c779
DN		 8806 new_token.code = T_REG;
8807 new_token.reg = reg;
8808
4d1bb795
JB		 8809 memcpy (new_token.str, intel_parser.op_string, len);
8810 new_token.str[len] = '\0';
64a0c779
DN		 8811 }
8812
8813 else if (is_identifier_char (*intel_parser.op_string))
8814 {
8815 char *p = new_token.str;
8816 char *q = intel_parser.op_string;
8817
8818 /* A '.' or '$' followed by an identifier char is an identifier.
8819 Otherwise, it's operator '.' followed by an expression. */
8820 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
8821 {
9306ca4a
JB		 8822 new_token.code = '.';
8823 new_token.str[0] = '.';
64a0c779
DN		 8824 new_token.str[1] = '\0';
8825 }
8826 else
8827 {
8828 while (is_identifier_char (*q) || *q == '@')
8829 *p++ = *q++;
8830 *p = '\0';
8831
9306ca4a
JB		 8832 if (strcasecmp (new_token.str, "NOT") == 0)
8833 new_token.code = '~';
8834
8835 else if (strcasecmp (new_token.str, "MOD") == 0)
8836 new_token.code = '%';
8837
8838 else if (strcasecmp (new_token.str, "AND") == 0)
8839 new_token.code = '&';
8840
8841 else if (strcasecmp (new_token.str, "OR") == 0)
8842 new_token.code = '|';
8843
8844 else if (strcasecmp (new_token.str, "XOR") == 0)
8845 new_token.code = '^';
8846
8847 else if (strcasecmp (new_token.str, "SHL") == 0)
8848 new_token.code = T_SHL;
8849
8850 else if (strcasecmp (new_token.str, "SHR") == 0)
8851 new_token.code = T_SHR;
8852
8853 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 8854 new_token.code = T_BYTE;
8855
8856 else if (strcasecmp (new_token.str, "WORD") == 0)
8857 new_token.code = T_WORD;
8858
8859 else if (strcasecmp (new_token.str, "DWORD") == 0)
8860 new_token.code = T_DWORD;
8861
9306ca4a
JB		 8862 else if (strcasecmp (new_token.str, "FWORD") == 0)
8863 new_token.code = T_FWORD;
8864
64a0c779
DN		 8865 else if (strcasecmp (new_token.str, "QWORD") == 0)
8866 new_token.code = T_QWORD;
8867
9306ca4a
JB		 8868 else if (strcasecmp (new_token.str, "TBYTE") == 0
8869 /* XXX remove (gcc still uses it) */
8870 || strcasecmp (new_token.str, "XWORD") == 0)
8871 new_token.code = T_TBYTE;
8872
8873 else if (strcasecmp (new_token.str, "XMMWORD") == 0
8874 || strcasecmp (new_token.str, "OWORD") == 0)
8875 new_token.code = T_XMMWORD;
64a0c779
DN		 8876
8877 else if (strcasecmp (new_token.str, "PTR") == 0)
8878 new_token.code = T_PTR;
8879
8880 else if (strcasecmp (new_token.str, "SHORT") == 0)
8881 new_token.code = T_SHORT;
8882
8883 else if (strcasecmp (new_token.str, "OFFSET") == 0)
8884 {
8885 new_token.code = T_OFFSET;
8886
8887 /* ??? This is not mentioned in the MASM grammar but gcc
8888 makes use of it with -mintel-syntax. OFFSET may be
8889 followed by FLAT: */
8890 if (strncasecmp (q, " FLAT:", 6) == 0)
8891 strcat (new_token.str, " FLAT:");
8892 }
8893
8894 /* ??? This is not mentioned in the MASM grammar. */
8895 else if (strcasecmp (new_token.str, "FLAT") == 0)
a724f0f4
JB		 8896 {
8897 new_token.code = T_OFFSET;
8898 if (*q == ':')
8899 strcat (new_token.str, ":");
8900 else
8901 as_bad (_("`:' expected"));
8902 }
64a0c779
DN		 8903
8904 else
8905 new_token.code = T_ID;
8906 }
8907 }
8908
9306ca4a
JB		 8909 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
8910 {
8911 new_token.code = *intel_parser.op_string;
8912 new_token.str[0] = *intel_parser.op_string;
8913 new_token.str[1] = '\0';
8914 }
8915
8916 else if (strchr ("<>", *intel_parser.op_string)
8917 && *intel_parser.op_string == *(intel_parser.op_string + 1))
8918 {
8919 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
8920 new_token.str[0] = *intel_parser.op_string;
8921 new_token.str[1] = *intel_parser.op_string;
8922 new_token.str[2] = '\0';
8923 }
8924
64a0c779 8925 else
0477af35 8926 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 8927
8928 intel_parser.op_string += strlen (new_token.str);
8929 cur_token = new_token;
8930}
8931
64a0c779
DN		 8932/* Put cur_token back into the token stream and make cur_token point to
8933 prev_token. */
8934static void
e3bb37b5 8935intel_putback_token (void)
64a0c779 8936{
a724f0f4
JB		 8937 if (cur_token.code != T_NIL)
8938 {
8939 intel_parser.op_string -= strlen (cur_token.str);
8940 free (cur_token.str);
8941 }
64a0c779 8942 cur_token = prev_token;
4a1805b1 8943
64a0c779
DN		 8944 /* Forget prev_token. */
8945 prev_token.code = T_NIL;
8946 prev_token.reg = NULL;
8947 prev_token.str = NULL;
8948}
54cfded0 8949
a4447b93 8950int
1df69f4f 8951tc_x86_regname_to_dw2regnum (char *regname)
54cfded0
AM		 8952{
8953 unsigned int regnum;
8954 unsigned int regnames_count;
089dfecd 8955 static const char *const regnames_32[] =
54cfded0 8956 {
a4447b93
RH		 8957 "eax", "ecx", "edx", "ebx",
8958 "esp", "ebp", "esi", "edi",
089dfecd
JB		 8959 "eip", "eflags", NULL,
8960 "st0", "st1", "st2", "st3",
8961 "st4", "st5", "st6", "st7",
8962 NULL, NULL,
8963 "xmm0", "xmm1", "xmm2", "xmm3",
8964 "xmm4", "xmm5", "xmm6", "xmm7",
8965 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8966 "mm4", "mm5", "mm6", "mm7",
8967 "fcw", "fsw", "mxcsr",
8968 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8969 "tr", "ldtr"
54cfded0 8970 };
089dfecd 8971 static const char *const regnames_64[] =
54cfded0 8972 {
089dfecd
JB		 8973 "rax", "rdx", "rcx", "rbx",
8974 "rsi", "rdi", "rbp", "rsp",
8975 "r8", "r9", "r10", "r11",
54cfded0 8976 "r12", "r13", "r14", "r15",
089dfecd
JB		 8977 "rip",
8978 "xmm0", "xmm1", "xmm2", "xmm3",
8979 "xmm4", "xmm5", "xmm6", "xmm7",
8980 "xmm8", "xmm9", "xmm10", "xmm11",
8981 "xmm12", "xmm13", "xmm14", "xmm15",
8982 "st0", "st1", "st2", "st3",
8983 "st4", "st5", "st6", "st7",
8984 "mm0", "mm1", "mm2", "mm3",
43fd16e4
JB		 8985 "mm4", "mm5", "mm6", "mm7",
8986 "rflags",
8987 "es", "cs", "ss", "ds", "fs", "gs", NULL, NULL,
8988 "fs.base", "gs.base", NULL, NULL,
8989 "tr", "ldtr",
8990 "mxcsr", "fcw", "fsw"
54cfded0 8991 };
089dfecd 8992 const char *const *regnames;
54cfded0
AM		 8993
8994 if (flag_code == CODE_64BIT)
8995 {
8996 regnames = regnames_64;
0cea6190 8997 regnames_count = ARRAY_SIZE (regnames_64);
54cfded0
AM		 8998 }
8999 else
9000 {
9001 regnames = regnames_32;
0cea6190 9002 regnames_count = ARRAY_SIZE (regnames_32);
54cfded0
AM		 9003 }
9004
9005 for (regnum = 0; regnum < regnames_count; regnum++)
089dfecd
JB		 9006 if (regnames[regnum] != NULL
9007 && strcmp (regname, regnames[regnum]) == 0)
54cfded0
AM		 9008 return regnum;
9009
54cfded0
AM		 9010 return -1;
9011}
9012
9013void
9014tc_x86_frame_initial_instructions (void)
9015{
a4447b93
RH		 9016 static unsigned int sp_regno;
9017
9018 if (!sp_regno)
9019 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
9020 ? "rsp" : "esp");
9021
9022 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
9023 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 9024}
d2b2c203
DJ		 9025
9026int
9027i386_elf_section_type (const char *str, size_t len)
9028{
9029 if (flag_code == CODE_64BIT
9030 && len == sizeof ("unwind") - 1
9031 && strncmp (str, "unwind", 6) == 0)
9032 return SHT_X86_64_UNWIND;
9033
9034 return -1;
9035}
bb41ade5
AM		 9036
9037#ifdef TE_PE
9038void
9039tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
9040{
9041 expressionS expr;
9042
9043 expr.X_op = O_secrel;
9044 expr.X_add_symbol = symbol;
9045 expr.X_add_number = 0;
9046 emit_expr (&expr, size);
9047}
9048#endif
3b22753a
L		 9049
9050#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9051/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9052
9053int
9054x86_64_section_letter (int letter, char **ptr_msg)
9055{
9056 if (flag_code == CODE_64BIT)
9057 {
9058 if (letter == 'l')
9059 return SHF_X86_64_LARGE;
9060
9061 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 9062 }
3b22753a 9063 else
64e74474 9064 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 9065 return -1;
9066}
9067
9068int
9069x86_64_section_word (char *str, size_t len)
9070{
8620418b 9071 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 9072 return SHF_X86_64_LARGE;
9073
9074 return -1;
9075}
9076
9077static void
9078handle_large_common (int small ATTRIBUTE_UNUSED)
9079{
9080 if (flag_code != CODE_64BIT)
9081 {
9082 s_comm_internal (0, elf_common_parse);
9083 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9084 }
9085 else
9086 {
9087 static segT lbss_section;
9088 asection *saved_com_section_ptr = elf_com_section_ptr;
9089 asection *saved_bss_section = bss_section;
9090
9091 if (lbss_section == NULL)
9092 {
9093 flagword applicable;
9094 segT seg = now_seg;
9095 subsegT subseg = now_subseg;
9096
9097 /* The .lbss section is for local .largecomm symbols. */
9098 lbss_section = subseg_new (".lbss", 0);
9099 applicable = bfd_applicable_section_flags (stdoutput);
9100 bfd_set_section_flags (stdoutput, lbss_section,
9101 applicable & SEC_ALLOC);
9102 seg_info (lbss_section)->bss = 1;
9103
9104 subseg_set (seg, subseg);
9105 }
9106
9107 elf_com_section_ptr = &_bfd_elf_large_com_section;
9108 bss_section = lbss_section;
9109
9110 s_comm_internal (0, elf_common_parse);
9111
9112 elf_com_section_ptr = saved_com_section_ptr;
9113 bss_section = saved_bss_section;
9114 }
9115}
9116#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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