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b534c6d3 1/* tc-i386.c -- Assemble code for the Intel 80386
f7e42eb4 2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
0bfee649 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
47926f60 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
47926f60
KH		 23/* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
3e73aa7c 25 x86_64 support by Jan Hubicka (jh@suse.cz)
0f10071e 26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
47926f60
KH		 27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
252b5132 29
252b5132 30#include "as.h"
3882b010 31#include "safe-ctype.h"
252b5132 32#include "subsegs.h"
316e2c05 33#include "dwarf2dbg.h"
54cfded0 34#include "dw2gencfi.h"
d2b2c203 35#include "elf/x86-64.h"
40fb9820 36#include "opcodes/i386-init.h"
252b5132 37
252b5132
RH		 38#ifndef REGISTER_WARNINGS
39#define REGISTER_WARNINGS 1
40#endif
41
c3332e24 42#ifndef INFER_ADDR_PREFIX
eecb386c 43#define INFER_ADDR_PREFIX 1
c3332e24
AM		 44#endif
45
29b0f896
AM		 46#ifndef DEFAULT_ARCH
47#define DEFAULT_ARCH "i386"
246fcdee 48#endif
252b5132 49
edde18a5
AM		 50#ifndef INLINE
51#if __GNUC__ >= 2
52#define INLINE __inline__
53#else
54#define INLINE
55#endif
56#endif
57
6305a203
L		 58/* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 LOCKREP_PREFIX. */
63#define WAIT_PREFIX 0
64#define SEG_PREFIX 1
65#define ADDR_PREFIX 2
66#define DATA_PREFIX 3
67#define LOCKREP_PREFIX 4
68#define REX_PREFIX 5 /* must come last. */
69#define MAX_PREFIXES 6 /* max prefixes per opcode */
70
71/* we define the syntax here (modulo base,index,scale syntax) */
72#define REGISTER_PREFIX '%'
73#define IMMEDIATE_PREFIX '$'
74#define ABSOLUTE_PREFIX '*'
75
76/* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78#define WORD_MNEM_SUFFIX 'w'
79#define BYTE_MNEM_SUFFIX 'b'
80#define SHORT_MNEM_SUFFIX 's'
81#define LONG_MNEM_SUFFIX 'l'
82#define QWORD_MNEM_SUFFIX 'q'
83#define XMMWORD_MNEM_SUFFIX 'x'
c0f3af97 84#define YMMWORD_MNEM_SUFFIX 'y'
6305a203
L		 85/* Intel Syntax. Use a non-ascii letter since since it never appears
86 in instructions. */
87#define LONG_DOUBLE_MNEM_SUFFIX '\1'
88
89#define END_OF_INSN '\0'
90
91/*
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
96 END.
97 */
98typedef struct
99{
100 const template *start;
101 const template *end;
102}
103templates;
104
105/* 386 operand encoding bytes: see 386 book for details of this. */
106typedef struct
107{
108 unsigned int regmem; /* codes register or memory operand */
109 unsigned int reg; /* codes register operand (or extended opcode) */
110 unsigned int mode; /* how to interpret regmem & reg */
111}
112modrm_byte;
113
114/* x86-64 extension prefix. */
115typedef int rex_byte;
116
117/* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120#define DREX_OC0(x) (((x) & 1) != 0)
121#define DREX_OC1(x) (((x) & 2) != 0)
122
123#define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124#define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
125
126/* OC mappings */
127#define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128#define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129#define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130#define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
131
132#define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133#define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
134
135/* Information needed to create the DREX byte in SSE5 instructions. */
136typedef struct
137{
138 unsigned int reg; /* register */
139 unsigned int rex; /* REX flags */
140 unsigned int modrm_reg; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem; /* which arg goes in the modrm.regmem field */
142} drex_byte;
143
144/* 386 opcode byte to code indirect addressing. */
145typedef struct
146{
147 unsigned base;
148 unsigned index;
149 unsigned scale;
150}
151sib_byte;
152
6305a203
L		 153/* x86 arch names, types and features */
154typedef struct
155{
156 const char *name; /* arch name */
157 enum processor_type type; /* arch type */
158 i386_cpu_flags flags; /* cpu feature flags */
159}
160arch_entry;
161
e3bb37b5
L		 162static void set_code_flag (int);
163static void set_16bit_gcc_code_flag (int);
164static void set_intel_syntax (int);
1efbbeb4 165static void set_intel_mnemonic (int);
db51cc60 166static void set_allow_index_reg (int);
cb19c032 167static void set_sse_check (int);
e3bb37b5 168static void set_cpu_arch (int);
6482c264 169#ifdef TE_PE
e3bb37b5 170static void pe_directive_secrel (int);
6482c264 171#endif
e3bb37b5
L		 172static void signed_cons (int);
173static char *output_invalid (int c);
a7619375 174static int i386_att_operand (char *);
e3bb37b5
L		 175static int i386_intel_operand (char *, int);
176static const reg_entry *parse_register (char *, char **);
177static char *parse_insn (char *, char *);
178static char *parse_operands (char *, const char *);
179static void swap_operands (void);
4d456e3d 180static void swap_2_operands (int, int);
e3bb37b5
L		 181static void optimize_imm (void);
182static void optimize_disp (void);
fa99fab2 183static const template *match_template (void);
e3bb37b5
L		 184static int check_string (void);
185static int process_suffix (void);
186static int check_byte_reg (void);
187static int check_long_reg (void);
188static int check_qword_reg (void);
189static int check_word_reg (void);
190static int finalize_imm (void);
85f10a01 191static void process_drex (void);
e3bb37b5
L		 192static int process_operands (void);
193static const seg_entry *build_modrm_byte (void);
194static void output_insn (void);
195static void output_imm (fragS *, offsetT);
196static void output_disp (fragS *, offsetT);
29b0f896 197#ifndef I386COFF
e3bb37b5 198static void s_bss (int);
252b5132 199#endif
17d4e2a2
L		 200#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201static void handle_large_common (int small ATTRIBUTE_UNUSED);
202#endif
252b5132 203
a847613f 204static const char *default_arch = DEFAULT_ARCH;
3e73aa7c 205
c0f3af97
L		 206/* VEX prefix. */
207typedef struct
208{
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes[3];
211 unsigned int length;
212 /* Destination or source register specifier. */
213 const reg_entry *register_specifier;
214} vex_prefix;
215
252b5132 216/* 'md_assemble ()' gathers together information and puts it into a
47926f60 217 i386_insn. */
252b5132 218
520dc8e8
AM		 219union i386_op
220 {
221 expressionS *disps;
222 expressionS *imms;
223 const reg_entry *regs;
224 };
225
252b5132
RH		 226struct _i386_insn
227 {
47926f60 228 /* TM holds the template for the insn were currently assembling. */
252b5132
RH		 229 template tm;
230
7d5e4556
L		 231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
252b5132
RH		 233 char suffix;
234
47926f60 235 /* OPERANDS gives the number of given operands. */
252b5132
RH		 236 unsigned int operands;
237
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
47926f60 240 operands. */
252b5132
RH		 241 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
242
243 /* TYPES [i] is the type (see above #defines) which tells us how to
520dc8e8 244 use OP[i] for the corresponding operand. */
40fb9820 245 i386_operand_type types[MAX_OPERANDS];
252b5132 246
520dc8e8
AM		 247 /* Displacement expression, immediate expression, or register for each
248 operand. */
249 union i386_op op[MAX_OPERANDS];
252b5132 250
3e73aa7c
JH		 251 /* Flags for operands. */
252 unsigned int flags[MAX_OPERANDS];
253#define Operand_PCrel 1
254
252b5132 255 /* Relocation type for operand */
f86103b7 256 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
252b5132 257
252b5132
RH		 258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry *base_reg;
261 const reg_entry *index_reg;
262 unsigned int log2_scale_factor;
263
264 /* SEG gives the seg_entries of this insn. They are zero unless
47926f60 265 explicit segment overrides are given. */
ce8a8b2f 266 const seg_entry *seg[2];
252b5132
RH		 267
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes;
271 unsigned char prefix[MAX_PREFIXES];
272
273 /* RM and SIB are the modrm byte and the sib byte where the
85f10a01
MM		 274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
252b5132
RH		 276
277 modrm_byte rm;
3e73aa7c 278 rex_byte rex;
252b5132 279 sib_byte sib;
85f10a01 280 drex_byte drex;
c0f3af97 281 vex_prefix vex;
b6169b20
L		 282
283 /* Swap operand in encoding. */
284 unsigned int swap_operand : 1;
252b5132
RH		 285 };
286
287typedef struct _i386_insn i386_insn;
288
289/* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
32137342 291const char extra_symbol_chars[] = "*%-(["
252b5132 292#ifdef LEX_AT
32137342
NC		 293 "@"
294#endif
295#ifdef LEX_QM
296 "?"
252b5132 297#endif
32137342 298 ;
252b5132 299
29b0f896
AM		 300#if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
3896cfd5 302 && !defined (TE_GNU) \
29b0f896 303 && !defined (TE_LINUX) \
32137342 304 && !defined (TE_NETWARE) \
29b0f896
AM		 305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
252b5132 307/* This array holds the chars that always start a comment. If the
b3b91714
AM		 308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310const char *i386_comment_chars = "#/";
311#define SVR4_COMMENT_CHARS 1
252b5132 312#define PREFIX_SEPARATOR '\\'
252b5132 313
b3b91714
AM		 314#else
315const char *i386_comment_chars = "#";
316#define PREFIX_SEPARATOR '/'
317#endif
318
252b5132
RH		 319/* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
ce8a8b2f
AM		 321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
252b5132 323 first line of the input file. This is because the compiler outputs
ce8a8b2f
AM		 324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
252b5132 326 '/' isn't otherwise defined. */
b3b91714 327const char line_comment_chars[] = "#/";
252b5132 328
63a0b638 329const char line_separator_chars[] = ";";
252b5132 330
ce8a8b2f
AM		 331/* Chars that can be used to separate mant from exp in floating point
332 nums. */
252b5132
RH		 333const char EXP_CHARS[] = "eE";
334
ce8a8b2f
AM		 335/* Chars that mean this number is a floating point constant
336 As in 0f12.456
337 or 0d1.2345e12. */
252b5132
RH		 338const char FLT_CHARS[] = "fFdDxX";
339
ce8a8b2f 340/* Tables for lexical analysis. */
252b5132
RH		 341static char mnemonic_chars[256];
342static char register_chars[256];
343static char operand_chars[256];
344static char identifier_chars[256];
345static char digit_chars[256];
346
ce8a8b2f 347/* Lexical macros. */
252b5132
RH		 348#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349#define is_operand_char(x) (operand_chars[(unsigned char) x])
350#define is_register_char(x) (register_chars[(unsigned char) x])
351#define is_space_char(x) ((x) == ' ')
352#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353#define is_digit_char(x) (digit_chars[(unsigned char) x])
354
0234cb7c 355/* All non-digit non-letter characters that may occur in an operand. */
252b5132
RH		 356static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
357
358/* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
47926f60 361 assembler instruction). */
252b5132 362static char save_stack[32];
ce8a8b2f 363static char *save_stack_p;
252b5132
RH		 364#define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366#define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
368
47926f60 369/* The instruction we're assembling. */
252b5132
RH		 370static i386_insn i;
371
372/* Possible templates for current insn. */
373static const templates *current_templates;
374
31b2323c
L		 375/* Per instruction expressionS buffers: max displacements & immediates. */
376static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
377static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
252b5132 378
47926f60
KH		 379/* Current operand we are working on. */
380static int this_operand;
252b5132 381
3e73aa7c
JH		 382/* We support four different modes. FLAG_CODE variable is used to distinguish
383 these. */
384
385enum flag_code {
386 CODE_32BIT,
387 CODE_16BIT,
388 CODE_64BIT };
389
390static enum flag_code flag_code;
4fa24527 391static unsigned int object_64bit;
3e73aa7c
JH		 392static int use_rela_relocations = 0;
393
394/* The names used to print error messages. */
b77a7acd 395static const char *flag_code_names[] =
3e73aa7c
JH		 396 {
397 "32",
398 "16",
399 "64"
400 };
252b5132 401
47926f60
KH		 402/* 1 for intel syntax,
403 0 if att syntax. */
404static int intel_syntax = 0;
252b5132 405
1efbbeb4
L		 406/* 1 for intel mnemonic,
407 0 if att mnemonic. */
408static int intel_mnemonic = !SYSV386_COMPAT;
409
5209009a 410/* 1 if support old (<= 2.8.1) versions of gcc. */
1efbbeb4
L		 411static int old_gcc = OLDGCC_COMPAT;
412
a60de03c
JB		 413/* 1 if pseudo registers are permitted. */
414static int allow_pseudo_reg = 0;
415
47926f60
KH		 416/* 1 if register prefix % not required. */
417static int allow_naked_reg = 0;
252b5132 418
ba104c83 419/* 1 if pseudo index register, eiz/riz, is allowed . */
db51cc60
L		 420static int allow_index_reg = 0;
421
daf50ae7
L		 422static enum
423 {
424 sse_check_none = 0,
425 sse_check_warning,
426 sse_check_error
427 }
428sse_check;
429
2ca3ace5
L		 430/* Register prefix used for error message. */
431static const char *register_prefix = "%";
432
47926f60
KH		 433/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436static char stackop_size = '\0';
eecb386c 437
12b55ccc
L		 438/* Non-zero to optimize code alignment. */
439int optimize_align_code = 1;
440
47926f60
KH		 441/* Non-zero to quieten some warnings. */
442static int quiet_warnings = 0;
a38cf1db 443
47926f60
KH		 444/* CPU name. */
445static const char *cpu_arch_name = NULL;
6305a203 446static char *cpu_sub_arch_name = NULL;
a38cf1db 447
47926f60 448/* CPU feature flags. */
40fb9820
L		 449static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
450
ccc9c027
L		 451/* If we have selected a cpu we are generating instructions for. */
452static int cpu_arch_tune_set = 0;
453
9103f4f4 454/* Cpu we are generating instructions for. */
fbf3f584 455enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
9103f4f4
L		 456
457/* CPU feature flags of cpu we are generating instructions for. */
40fb9820 458static i386_cpu_flags cpu_arch_tune_flags;
9103f4f4 459
ccc9c027 460/* CPU instruction set architecture used. */
fbf3f584 461enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
ccc9c027 462
9103f4f4 463/* CPU feature flags of instruction set architecture used. */
fbf3f584 464i386_cpu_flags cpu_arch_isa_flags;
9103f4f4 465
fddf5b5b
AM		 466/* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468static unsigned int no_cond_jump_promotion = 0;
469
c0f3af97
L		 470/* Encode SSE instructions with VEX prefix. */
471static unsigned int sse2avx;
472
29b0f896 473/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
87c245cc 474static symbolS *GOT_symbol;
29b0f896 475
a4447b93
RH		 476/* The dwarf2 return column, adjusted for 32 or 64 bit. */
477unsigned int x86_dwarf2_return_column;
478
479/* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480int x86_cie_data_alignment;
481
252b5132 482/* Interface to relax_segment.
fddf5b5b
AM		 483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
252b5132 486
47926f60 487/* Types. */
93c2a809
AM		 488#define UNCOND_JUMP 0
489#define COND_JUMP 1
490#define COND_JUMP86 2
fddf5b5b 491
47926f60 492/* Sizes. */
252b5132
RH		 493#define CODE16 1
494#define SMALL 0
29b0f896 495#define SMALL16 (SMALL | CODE16)
252b5132 496#define BIG 2
29b0f896 497#define BIG16 (BIG | CODE16)
252b5132
RH		 498
499#ifndef INLINE
500#ifdef __GNUC__
501#define INLINE __inline__
502#else
503#define INLINE
504#endif
505#endif
506
fddf5b5b
AM		 507#define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509#define TYPE_FROM_RELAX_STATE(s) \
510 ((s) >> 2)
511#define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
252b5132
RH		 513
514/* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
521
522const relax_typeS md_relax_table[] =
523{
24eab124
AM		 524 /* The fields are:
525 1) most positive reach of this state,
526 2) most negative reach of this state,
93c2a809 527 3) how many bytes this mode will have in the variable part of the frag
ce8a8b2f 528 4) which index into the table to try if we can't fit into this one. */
252b5132 529
fddf5b5b 530 /* UNCOND_JUMP states. */
93c2a809
AM		 531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
252b5132 535 {0, 0, 4, 0},
93c2a809
AM		 536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
252b5132
RH		 538 {0, 0, 2, 0},
539
93c2a809
AM		 540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
545 {0, 0, 5, 0},
fddf5b5b 546 /* word conditionals add 3 bytes to frag:
93c2a809
AM		 547 1 extra opcode byte, 2 displacement bytes. */
548 {0, 0, 3, 0},
549
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
555 {0, 0, 5, 0},
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
558 {0, 0, 4, 0}
252b5132
RH		 559};
560
9103f4f4
L		 561static const arch_entry cpu_arch[] =
562{
6305a203
L		 563 { "generic32", PROCESSOR_GENERIC32,
564 CPU_GENERIC32_FLAGS },
565 { "generic64", PROCESSOR_GENERIC64,
566 CPU_GENERIC64_FLAGS },
567 { "i8086", PROCESSOR_UNKNOWN,
568 CPU_NONE_FLAGS },
569 { "i186", PROCESSOR_UNKNOWN,
570 CPU_I186_FLAGS },
571 { "i286", PROCESSOR_UNKNOWN,
572 CPU_I286_FLAGS },
573 { "i386", PROCESSOR_I386,
574 CPU_I386_FLAGS },
575 { "i486", PROCESSOR_I486,
576 CPU_I486_FLAGS },
577 { "i586", PROCESSOR_PENTIUM,
578 CPU_I586_FLAGS },
579 { "i686", PROCESSOR_PENTIUMPRO,
580 CPU_I686_FLAGS },
581 { "pentium", PROCESSOR_PENTIUM,
582 CPU_I586_FLAGS },
583 { "pentiumpro", PROCESSOR_PENTIUMPRO,
584 CPU_I686_FLAGS },
585 { "pentiumii", PROCESSOR_PENTIUMPRO,
586 CPU_P2_FLAGS },
587 { "pentiumiii",PROCESSOR_PENTIUMPRO,
588 CPU_P3_FLAGS },
589 { "pentium4", PROCESSOR_PENTIUM4,
590 CPU_P4_FLAGS },
591 { "prescott", PROCESSOR_NOCONA,
592 CPU_CORE_FLAGS },
593 { "nocona", PROCESSOR_NOCONA,
594 CPU_NOCONA_FLAGS },
595 { "yonah", PROCESSOR_CORE,
596 CPU_CORE_FLAGS },
597 { "core", PROCESSOR_CORE,
598 CPU_CORE_FLAGS },
599 { "merom", PROCESSOR_CORE2,
600 CPU_CORE2_FLAGS },
601 { "core2", PROCESSOR_CORE2,
602 CPU_CORE2_FLAGS },
bd5295b2
L		 603 { "corei7", PROCESSOR_COREI7,
604 CPU_COREI7_FLAGS },
6305a203
L		 605 { "k6", PROCESSOR_K6,
606 CPU_K6_FLAGS },
607 { "k6_2", PROCESSOR_K6,
608 CPU_K6_2_FLAGS },
609 { "athlon", PROCESSOR_ATHLON,
610 CPU_ATHLON_FLAGS },
611 { "sledgehammer", PROCESSOR_K8,
612 CPU_K8_FLAGS },
613 { "opteron", PROCESSOR_K8,
614 CPU_K8_FLAGS },
615 { "k8", PROCESSOR_K8,
616 CPU_K8_FLAGS },
617 { "amdfam10", PROCESSOR_AMDFAM10,
618 CPU_AMDFAM10_FLAGS },
619 { ".mmx", PROCESSOR_UNKNOWN,
620 CPU_MMX_FLAGS },
621 { ".sse", PROCESSOR_UNKNOWN,
622 CPU_SSE_FLAGS },
623 { ".sse2", PROCESSOR_UNKNOWN,
624 CPU_SSE2_FLAGS },
625 { ".sse3", PROCESSOR_UNKNOWN,
626 CPU_SSE3_FLAGS },
627 { ".ssse3", PROCESSOR_UNKNOWN,
628 CPU_SSSE3_FLAGS },
629 { ".sse4.1", PROCESSOR_UNKNOWN,
630 CPU_SSE4_1_FLAGS },
631 { ".sse4.2", PROCESSOR_UNKNOWN,
632 CPU_SSE4_2_FLAGS },
633 { ".sse4", PROCESSOR_UNKNOWN,
634 CPU_SSE4_2_FLAGS },
c0f3af97
L		 635 { ".avx", PROCESSOR_UNKNOWN,
636 CPU_AVX_FLAGS },
6305a203
L		 637 { ".vmx", PROCESSOR_UNKNOWN,
638 CPU_VMX_FLAGS },
639 { ".smx", PROCESSOR_UNKNOWN,
640 CPU_SMX_FLAGS },
f03fe4c1
L		 641 { ".xsave", PROCESSOR_UNKNOWN,
642 CPU_XSAVE_FLAGS },
c0f3af97
L		 643 { ".aes", PROCESSOR_UNKNOWN,
644 CPU_AES_FLAGS },
594ab6a3
L		 645 { ".pclmul", PROCESSOR_UNKNOWN,
646 CPU_PCLMUL_FLAGS },
c0f3af97 647 { ".clmul", PROCESSOR_UNKNOWN,
594ab6a3 648 CPU_PCLMUL_FLAGS },
c0f3af97
L		 649 { ".fma", PROCESSOR_UNKNOWN,
650 CPU_FMA_FLAGS },
f1f8f695
L		 651 { ".movbe", PROCESSOR_UNKNOWN,
652 CPU_MOVBE_FLAGS },
653 { ".ept", PROCESSOR_UNKNOWN,
654 CPU_EPT_FLAGS },
bd5295b2
L		 655 { ".clflush", PROCESSOR_UNKNOWN,
656 CPU_CLFLUSH_FLAGS },
657 { ".syscall", PROCESSOR_UNKNOWN,
658 CPU_SYSCALL_FLAGS },
1b7f3fb0
L		 659 { ".rdtscp", PROCESSOR_UNKNOWN,
660 CPU_RDTSCP_FLAGS },
6305a203
L		 661 { ".3dnow", PROCESSOR_UNKNOWN,
662 CPU_3DNOW_FLAGS },
663 { ".3dnowa", PROCESSOR_UNKNOWN,
664 CPU_3DNOWA_FLAGS },
665 { ".padlock", PROCESSOR_UNKNOWN,
666 CPU_PADLOCK_FLAGS },
667 { ".pacifica", PROCESSOR_UNKNOWN,
668 CPU_SVME_FLAGS },
669 { ".svme", PROCESSOR_UNKNOWN,
670 CPU_SVME_FLAGS },
671 { ".sse4a", PROCESSOR_UNKNOWN,
672 CPU_SSE4A_FLAGS },
673 { ".abm", PROCESSOR_UNKNOWN,
674 CPU_ABM_FLAGS },
675 { ".sse5", PROCESSOR_UNKNOWN,
676 CPU_SSE5_FLAGS },
e413e4e9
AM		 677};
678
704209c0 679#ifdef I386COFF
a6c24e68
NC		 680/* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
682
683static symbolS *
684pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
685{
686 addressT align = 0;
687
688 SKIP_WHITESPACE ();
689
690 if (needs_align
691 && *input_line_pointer == ',')
692 {
693 align = parse_align (needs_align - 1);
694
695 if (align == (addressT) -1)
696 return NULL;
697 }
698 else
699 {
700 if (size >= 8)
701 align = 3;
702 else if (size >= 4)
703 align = 2;
704 else if (size >= 2)
705 align = 1;
706 else
707 align = 0;
708 }
709
710 bss_alloc (symbolP, size, align);
711 return symbolP;
712}
713
704209c0 714static void
a6c24e68
NC		 715pe_lcomm (int needs_align)
716{
717 s_comm_internal (needs_align * 2, pe_lcomm_internal);
718}
704209c0 719#endif
a6c24e68 720
29b0f896
AM		 721const pseudo_typeS md_pseudo_table[] =
722{
723#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes, 0},
725#else
726 {"align", s_align_ptwo, 0},
727#endif
728 {"arch", set_cpu_arch, 0},
729#ifndef I386COFF
730 {"bss", s_bss, 0},
a6c24e68
NC		 731#else
732 {"lcomm", pe_lcomm, 1},
29b0f896
AM		 733#endif
734 {"ffloat", float_cons, 'f'},
735 {"dfloat", float_cons, 'd'},
736 {"tfloat", float_cons, 'x'},
737 {"value", cons, 2},
d182319b 738 {"slong", signed_cons, 4},
29b0f896
AM		 739 {"noopt", s_ignore, 0},
740 {"optim", s_ignore, 0},
741 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
742 {"code16", set_code_flag, CODE_16BIT},
743 {"code32", set_code_flag, CODE_32BIT},
744 {"code64", set_code_flag, CODE_64BIT},
745 {"intel_syntax", set_intel_syntax, 1},
746 {"att_syntax", set_intel_syntax, 0},
1efbbeb4
L		 747 {"intel_mnemonic", set_intel_mnemonic, 1},
748 {"att_mnemonic", set_intel_mnemonic, 0},
db51cc60
L		 749 {"allow_index_reg", set_allow_index_reg, 1},
750 {"disallow_index_reg", set_allow_index_reg, 0},
cb19c032 751 {"sse_check", set_sse_check, 0},
3b22753a
L		 752#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common, 0},
07a53e5c 754#else
e3bb37b5 755 {"file", (void (*) (int)) dwarf2_directive_file, 0},
07a53e5c
RH		 756 {"loc", dwarf2_directive_loc, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
3b22753a 758#endif
6482c264
NC		 759#ifdef TE_PE
760 {"secrel32", pe_directive_secrel, 0},
761#endif
29b0f896
AM		 762 {0, 0, 0}
763};
764
765/* For interface with expression (). */
766extern char *input_line_pointer;
767
768/* Hash table for instruction mnemonic lookup. */
769static struct hash_control *op_hash;
770
771/* Hash table for register lookup. */
772static struct hash_control *reg_hash;
773\f
252b5132 774void
e3bb37b5 775i386_align_code (fragS *fragP, int count)
252b5132 776{
ce8a8b2f
AM		 777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
252b5132
RH		 780 static const char f32_1[] =
781 {0x90}; /* nop */
782 static const char f32_2[] =
ccc9c027 783 {0x66,0x90}; /* xchg %ax,%ax */
252b5132
RH		 784 static const char f32_3[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5[] =
789 {0x90, /* nop */
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8[] =
796 {0x90, /* nop */
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
c3332e24
AM		 816 static const char f16_3[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
252b5132
RH		 818 static const char f16_4[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5[] =
821 {0x90, /* nop */
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
76bc74dc
L		 832 static const char jump_31[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
252b5132
RH		 837 static const char *const f32_patt[] = {
838 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
76bc74dc 839 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
252b5132
RH		 840 };
841 static const char *const f16_patt[] = {
76bc74dc 842 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
252b5132 843 };
ccc9c027
L		 844 /* nopl (%[re]ax) */
845 static const char alt_3[] =
846 {0x0f,0x1f,0x00};
847 /* nopl 0(%[re]ax) */
848 static const char alt_4[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* data16
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11[] =
871 {0x66,
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 /* data16
874 data16
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12[] =
877 {0x66,
878 0x66,
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
880 /* data16
881 data16
882 data16
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13[] =
885 {0x66,
886 0x66,
887 0x66,
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* data16
890 data16
891 data16
892 data16
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14[] =
895 {0x66,
896 0x66,
897 0x66,
898 0x66,
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* data16
901 data16
902 data16
903 data16
904 data16
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15[] =
907 {0x66,
908 0x66,
909 0x66,
910 0x66,
911 0x66,
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
924 nopl 0L(%[re]ax) */
925 static const char alt_short_13[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 /* nopl 0L(%[re]ax)
929 nopl 0L(%[re]ax) */
930 static const char alt_short_14[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
933 /* nopl 0L(%[re]ax)
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt[] = {
939 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
940 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
941 alt_short_14, alt_short_15
942 };
943 static const char *const alt_long_patt[] = {
944 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
945 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
946 alt_long_14, alt_long_15
947 };
252b5132 948
76bc74dc
L		 949 /* Only align for at least a positive non-zero boundary. */
950 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
33fef721 951 return;
3e73aa7c 952
ccc9c027
L		 953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
4eed87de 955
76bc74dc
L		 956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
bd5295b2
L		 959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
76bc74dc
L		 961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
ccc9c027 963
76bc74dc
L		 964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
966 be used.
ccc9c027
L		 967
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
970
971 if (flag_code == CODE_16BIT)
972 {
ccc9c027 973 if (count > 8)
33fef721 974 {
76bc74dc
L		 975 memcpy (fragP->fr_literal + fragP->fr_fix,
976 jump_31, count);
977 /* Adjust jump offset. */
978 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
252b5132 979 }
76bc74dc
L		 980 else
981 memcpy (fragP->fr_literal + fragP->fr_fix,
982 f16_patt[count - 1], count);
252b5132 983 }
33fef721 984 else
ccc9c027
L		 985 {
986 const char *const *patt = NULL;
987
fbf3f584 988 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
ccc9c027
L		 989 {
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune)
992 {
993 case PROCESSOR_UNKNOWN:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
fbf3f584 996 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
76bc74dc 997 patt = alt_long_patt;
ccc9c027
L		 998 else
999 patt = f32_patt;
1000 break;
ccc9c027
L		 1001 case PROCESSOR_PENTIUMPRO:
1002 case PROCESSOR_PENTIUM4:
1003 case PROCESSOR_NOCONA:
ef05d495 1004 case PROCESSOR_CORE:
76bc74dc 1005 case PROCESSOR_CORE2:
bd5295b2 1006 case PROCESSOR_COREI7:
76bc74dc
L		 1007 case PROCESSOR_GENERIC64:
1008 patt = alt_long_patt;
1009 break;
ccc9c027
L		 1010 case PROCESSOR_K6:
1011 case PROCESSOR_ATHLON:
1012 case PROCESSOR_K8:
4eed87de 1013 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1014 patt = alt_short_patt;
1015 break;
76bc74dc 1016 case PROCESSOR_I386:
ccc9c027
L		 1017 case PROCESSOR_I486:
1018 case PROCESSOR_PENTIUM:
1019 case PROCESSOR_GENERIC32:
1020 patt = f32_patt;
1021 break;
4eed87de 1022 }
ccc9c027
L		 1023 }
1024 else
1025 {
fbf3f584 1026 switch (fragP->tc_frag_data.tune)
ccc9c027
L		 1027 {
1028 case PROCESSOR_UNKNOWN:
e6a14101 1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
ccc9c027
L		 1030 PROCESSOR_UNKNOWN. */
1031 abort ();
1032 break;
1033
76bc74dc 1034 case PROCESSOR_I386:
ccc9c027
L		 1035 case PROCESSOR_I486:
1036 case PROCESSOR_PENTIUM:
ccc9c027
L		 1037 case PROCESSOR_K6:
1038 case PROCESSOR_ATHLON:
1039 case PROCESSOR_K8:
4eed87de 1040 case PROCESSOR_AMDFAM10:
ccc9c027
L		 1041 case PROCESSOR_GENERIC32:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1043 for Cpu686. */
fbf3f584 1044 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1045 patt = alt_short_patt;
1046 else
1047 patt = f32_patt;
1048 break;
76bc74dc
L		 1049 case PROCESSOR_PENTIUMPRO:
1050 case PROCESSOR_PENTIUM4:
1051 case PROCESSOR_NOCONA:
1052 case PROCESSOR_CORE:
ef05d495 1053 case PROCESSOR_CORE2:
bd5295b2 1054 case PROCESSOR_COREI7:
fbf3f584 1055 if (fragP->tc_frag_data.isa_flags.bitfield.cpui686)
ccc9c027
L		 1056 patt = alt_long_patt;
1057 else
1058 patt = f32_patt;
1059 break;
1060 case PROCESSOR_GENERIC64:
76bc74dc 1061 patt = alt_long_patt;
ccc9c027 1062 break;
4eed87de 1063 }
ccc9c027
L		 1064 }
1065
76bc74dc
L		 1066 if (patt == f32_patt)
1067 {
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1070 its offset. */
1071 if (count < 15)
1072 memcpy (fragP->fr_literal + fragP->fr_fix,
1073 patt[count - 1], count);
1074 else
1075 {
1076 memcpy (fragP->fr_literal + fragP->fr_fix,
1077 jump_31, count);
1078 /* Adjust jump offset. */
1079 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1080 }
1081 }
1082 else
1083 {
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding = count;
1088 while (padding > 15)
1089 {
1090 padding -= 15;
1091 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1092 patt [14], 15);
1093 }
1094
1095 if (padding)
1096 memcpy (fragP->fr_literal + fragP->fr_fix,
1097 patt [padding - 1], padding);
1098 }
ccc9c027 1099 }
33fef721 1100 fragP->fr_var = count;
252b5132
RH		 1101}
1102
c6fb90c8 1103static INLINE int
0dfbf9d7 1104operand_type_all_zero (const union i386_operand_type *x)
40fb9820 1105{
0dfbf9d7 1106 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1107 {
1108 case 3:
0dfbf9d7 1109 if (x->array[2])
c6fb90c8
L		 1110 return 0;
1111 case 2:
0dfbf9d7 1112 if (x->array[1])
c6fb90c8
L		 1113 return 0;
1114 case 1:
0dfbf9d7 1115 return !x->array[0];
c6fb90c8
L		 1116 default:
1117 abort ();
1118 }
40fb9820
L		 1119}
1120
c6fb90c8 1121static INLINE void
0dfbf9d7 1122operand_type_set (union i386_operand_type *x, unsigned int v)
40fb9820 1123{
0dfbf9d7 1124 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1125 {
1126 case 3:
0dfbf9d7 1127 x->array[2] = v;
c6fb90c8 1128 case 2:
0dfbf9d7 1129 x->array[1] = v;
c6fb90c8 1130 case 1:
0dfbf9d7 1131 x->array[0] = v;
c6fb90c8
L		 1132 break;
1133 default:
1134 abort ();
1135 }
1136}
40fb9820 1137
c6fb90c8 1138static INLINE int
0dfbf9d7
L		 1139operand_type_equal (const union i386_operand_type *x,
1140 const union i386_operand_type *y)
c6fb90c8 1141{
0dfbf9d7 1142 switch (ARRAY_SIZE(x->array))
c6fb90c8
L		 1143 {
1144 case 3:
0dfbf9d7 1145 if (x->array[2] != y->array[2])
c6fb90c8
L		 1146 return 0;
1147 case 2:
0dfbf9d7 1148 if (x->array[1] != y->array[1])
c6fb90c8
L		 1149 return 0;
1150 case 1:
0dfbf9d7 1151 return x->array[0] == y->array[0];
c6fb90c8
L		 1152 break;
1153 default:
1154 abort ();
1155 }
1156}
40fb9820 1157
0dfbf9d7
L		 1158static INLINE int
1159cpu_flags_all_zero (const union i386_cpu_flags *x)
1160{
1161 switch (ARRAY_SIZE(x->array))
1162 {
1163 case 3:
1164 if (x->array[2])
1165 return 0;
1166 case 2:
1167 if (x->array[1])
1168 return 0;
1169 case 1:
1170 return !x->array[0];
1171 default:
1172 abort ();
1173 }
1174}
1175
1176static INLINE void
1177cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1178{
1179 switch (ARRAY_SIZE(x->array))
1180 {
1181 case 3:
1182 x->array[2] = v;
1183 case 2:
1184 x->array[1] = v;
1185 case 1:
1186 x->array[0] = v;
1187 break;
1188 default:
1189 abort ();
1190 }
1191}
1192
1193static INLINE int
1194cpu_flags_equal (const union i386_cpu_flags *x,
1195 const union i386_cpu_flags *y)
1196{
1197 switch (ARRAY_SIZE(x->array))
1198 {
1199 case 3:
1200 if (x->array[2] != y->array[2])
1201 return 0;
1202 case 2:
1203 if (x->array[1] != y->array[1])
1204 return 0;
1205 case 1:
1206 return x->array[0] == y->array[0];
1207 break;
1208 default:
1209 abort ();
1210 }
1211}
c6fb90c8
L		 1212
1213static INLINE int
1214cpu_flags_check_cpu64 (i386_cpu_flags f)
1215{
1216 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1217 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
40fb9820
L		 1218}
1219
c6fb90c8
L		 1220static INLINE i386_cpu_flags
1221cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1222{
c6fb90c8
L		 1223 switch (ARRAY_SIZE (x.array))
1224 {
1225 case 3:
1226 x.array [2] &= y.array [2];
1227 case 2:
1228 x.array [1] &= y.array [1];
1229 case 1:
1230 x.array [0] &= y.array [0];
1231 break;
1232 default:
1233 abort ();
1234 }
1235 return x;
1236}
40fb9820 1237
c6fb90c8
L		 1238static INLINE i386_cpu_flags
1239cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
40fb9820 1240{
c6fb90c8 1241 switch (ARRAY_SIZE (x.array))
40fb9820 1242 {
c6fb90c8
L		 1243 case 3:
1244 x.array [2] |= y.array [2];
1245 case 2:
1246 x.array [1] |= y.array [1];
1247 case 1:
1248 x.array [0] |= y.array [0];
40fb9820
L		 1249 break;
1250 default:
1251 abort ();
1252 }
40fb9820
L		 1253 return x;
1254}
1255
c0f3af97
L		 1256#define CPU_FLAGS_ARCH_MATCH 0x1
1257#define CPU_FLAGS_64BIT_MATCH 0x2
a5ff0eb2 1258#define CPU_FLAGS_AES_MATCH 0x4
ce2f5b3c
L		 1259#define CPU_FLAGS_PCLMUL_MATCH 0x8
1260#define CPU_FLAGS_AVX_MATCH 0x10
c0f3af97 1261
a5ff0eb2 1262#define CPU_FLAGS_32BIT_MATCH \
ce2f5b3c
L		 1263 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1264 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
c0f3af97
L		 1265#define CPU_FLAGS_PERFECT_MATCH \
1266 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1267
1268/* Return CPU flags match bits. */
3629bb00 1269
40fb9820 1270static int
c0f3af97 1271cpu_flags_match (const template *t)
40fb9820 1272{
c0f3af97
L		 1273 i386_cpu_flags x = t->cpu_flags;
1274 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
40fb9820
L		 1275
1276 x.bitfield.cpu64 = 0;
1277 x.bitfield.cpuno64 = 0;
1278
0dfbf9d7 1279 if (cpu_flags_all_zero (&x))
c0f3af97
L		 1280 {
1281 /* This instruction is available on all archs. */
1282 match |= CPU_FLAGS_32BIT_MATCH;
1283 }
3629bb00
L		 1284 else
1285 {
c0f3af97 1286 /* This instruction is available only on some archs. */
3629bb00
L		 1287 i386_cpu_flags cpu = cpu_arch_flags;
1288
1289 cpu.bitfield.cpu64 = 0;
1290 cpu.bitfield.cpuno64 = 0;
1291 cpu = cpu_flags_and (x, cpu);
c0f3af97
L		 1292 if (!cpu_flags_all_zero (&cpu))
1293 {
a5ff0eb2
L		 1294 if (x.bitfield.cpuavx)
1295 {
ce2f5b3c 1296 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
a5ff0eb2
L		 1297 if (cpu.bitfield.cpuavx)
1298 {
1299 /* Check SSE2AVX. */
1300 if (!t->opcode_modifier.sse2avx|| sse2avx)
1301 {
1302 match |= (CPU_FLAGS_ARCH_MATCH
1303 | CPU_FLAGS_AVX_MATCH);
1304 /* Check AES. */
1305 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1306 match |= CPU_FLAGS_AES_MATCH;
ce2f5b3c
L		 1307 /* Check PCLMUL. */
1308 if (!x.bitfield.cpupclmul
1309 || cpu.bitfield.cpupclmul)
1310 match |= CPU_FLAGS_PCLMUL_MATCH;
a5ff0eb2
L		 1311 }
1312 }
1313 else
1314 match |= CPU_FLAGS_ARCH_MATCH;
1315 }
1316 else
c0f3af97
L		 1317 match |= CPU_FLAGS_32BIT_MATCH;
1318 }
3629bb00 1319 }
c0f3af97 1320 return match;
40fb9820
L		 1321}
1322
c6fb90c8
L		 1323static INLINE i386_operand_type
1324operand_type_and (i386_operand_type x, i386_operand_type y)
40fb9820 1325{
c6fb90c8
L		 1326 switch (ARRAY_SIZE (x.array))
1327 {
1328 case 3:
1329 x.array [2] &= y.array [2];
1330 case 2:
1331 x.array [1] &= y.array [1];
1332 case 1:
1333 x.array [0] &= y.array [0];
1334 break;
1335 default:
1336 abort ();
1337 }
1338 return x;
40fb9820
L		 1339}
1340
c6fb90c8
L		 1341static INLINE i386_operand_type
1342operand_type_or (i386_operand_type x, i386_operand_type y)
40fb9820 1343{
c6fb90c8 1344 switch (ARRAY_SIZE (x.array))
40fb9820 1345 {
c6fb90c8
L		 1346 case 3:
1347 x.array [2] |= y.array [2];
1348 case 2:
1349 x.array [1] |= y.array [1];
1350 case 1:
1351 x.array [0] |= y.array [0];
40fb9820
L		 1352 break;
1353 default:
1354 abort ();
1355 }
c6fb90c8
L		 1356 return x;
1357}
40fb9820 1358
c6fb90c8
L		 1359static INLINE i386_operand_type
1360operand_type_xor (i386_operand_type x, i386_operand_type y)
1361{
1362 switch (ARRAY_SIZE (x.array))
1363 {
1364 case 3:
1365 x.array [2] ^= y.array [2];
1366 case 2:
1367 x.array [1] ^= y.array [1];
1368 case 1:
1369 x.array [0] ^= y.array [0];
1370 break;
1371 default:
1372 abort ();
1373 }
40fb9820
L		 1374 return x;
1375}
1376
1377static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1378static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1379static const i386_operand_type control = OPERAND_TYPE_CONTROL;
65da13b5
L		 1380static const i386_operand_type inoutportreg
1381 = OPERAND_TYPE_INOUTPORTREG;
40fb9820
L		 1382static const i386_operand_type reg16_inoutportreg
1383 = OPERAND_TYPE_REG16_INOUTPORTREG;
1384static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1385static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1386static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1387static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1388static const i386_operand_type anydisp
1389 = OPERAND_TYPE_ANYDISP;
40fb9820 1390static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
c0f3af97 1391static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
40fb9820
L		 1392static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1393static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1394static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1395static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1396static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1397static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1398static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1399static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1400static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1401
1402enum operand_type
1403{
1404 reg,
40fb9820
L		 1405 imm,
1406 disp,
1407 anymem
1408};
1409
c6fb90c8 1410static INLINE int
40fb9820
L		 1411operand_type_check (i386_operand_type t, enum operand_type c)
1412{
1413 switch (c)
1414 {
1415 case reg:
1416 return (t.bitfield.reg8
1417 || t.bitfield.reg16
1418 || t.bitfield.reg32
1419 || t.bitfield.reg64);
1420
40fb9820
L		 1421 case imm:
1422 return (t.bitfield.imm8
1423 || t.bitfield.imm8s
1424 || t.bitfield.imm16
1425 || t.bitfield.imm32
1426 || t.bitfield.imm32s
1427 || t.bitfield.imm64);
1428
1429 case disp:
1430 return (t.bitfield.disp8
1431 || t.bitfield.disp16
1432 || t.bitfield.disp32
1433 || t.bitfield.disp32s
1434 || t.bitfield.disp64);
1435
1436 case anymem:
1437 return (t.bitfield.disp8
1438 || t.bitfield.disp16
1439 || t.bitfield.disp32
1440 || t.bitfield.disp32s
1441 || t.bitfield.disp64
1442 || t.bitfield.baseindex);
1443
1444 default:
1445 abort ();
1446 }
2cfe26b6
AM		 1447
1448 return 0;
40fb9820
L		 1449}
1450
5c07affc
L		 1451/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1452 operand J for instruction template T. */
1453
1454static INLINE int
1455match_reg_size (const template *t, unsigned int j)
1456{
1457 return !((i.types[j].bitfield.byte
1458 && !t->operand_types[j].bitfield.byte)
1459 || (i.types[j].bitfield.word
1460 && !t->operand_types[j].bitfield.word)
1461 || (i.types[j].bitfield.dword
1462 && !t->operand_types[j].bitfield.dword)
1463 || (i.types[j].bitfield.qword
1464 && !t->operand_types[j].bitfield.qword));
1465}
1466
1467/* Return 1 if there is no conflict in any size on operand J for
1468 instruction template T. */
1469
1470static INLINE int
1471match_mem_size (const template *t, unsigned int j)
1472{
1473 return (match_reg_size (t, j)
1474 && !((i.types[j].bitfield.unspecified
1475 && !t->operand_types[j].bitfield.unspecified)
1476 || (i.types[j].bitfield.fword
1477 && !t->operand_types[j].bitfield.fword)
1478 || (i.types[j].bitfield.tbyte
1479 && !t->operand_types[j].bitfield.tbyte)
1480 || (i.types[j].bitfield.xmmword
c0f3af97
L		 1481 && !t->operand_types[j].bitfield.xmmword)
1482 || (i.types[j].bitfield.ymmword
1483 && !t->operand_types[j].bitfield.ymmword)));
5c07affc
L		 1484}
1485
1486/* Return 1 if there is no size conflict on any operands for
1487 instruction template T. */
1488
1489static INLINE int
1490operand_size_match (const template *t)
1491{
1492 unsigned int j;
1493 int match = 1;
1494
1495 /* Don't check jump instructions. */
1496 if (t->opcode_modifier.jump
1497 || t->opcode_modifier.jumpbyte
1498 || t->opcode_modifier.jumpdword
1499 || t->opcode_modifier.jumpintersegment)
1500 return match;
1501
1502 /* Check memory and accumulator operand size. */
1503 for (j = 0; j < i.operands; j++)
1504 {
1505 if (t->operand_types[j].bitfield.anysize)
1506 continue;
1507
1508 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1509 {
1510 match = 0;
1511 break;
1512 }
1513
1514 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1515 {
1516 match = 0;
1517 break;
1518 }
1519 }
1520
1521 if (match
1522 || (!t->opcode_modifier.d && !t->opcode_modifier.floatd))
1523 return match;
1524
1525 /* Check reverse. */
1526 assert (i.operands == 2);
1527
1528 match = 1;
1529 for (j = 0; j < 2; j++)
1530 {
1531 if (t->operand_types[j].bitfield.acc
1532 && !match_reg_size (t, j ? 0 : 1))
1533 {
1534 match = 0;
1535 break;
1536 }
1537
1538 if (i.types[j].bitfield.mem
1539 && !match_mem_size (t, j ? 0 : 1))
1540 {
1541 match = 0;
1542 break;
1543 }
1544 }
1545
1546 return match;
1547}
1548
c6fb90c8 1549static INLINE int
40fb9820
L		 1550operand_type_match (i386_operand_type overlap,
1551 i386_operand_type given)
1552{
1553 i386_operand_type temp = overlap;
1554
1555 temp.bitfield.jumpabsolute = 0;
7d5e4556 1556 temp.bitfield.unspecified = 0;
5c07affc
L		 1557 temp.bitfield.byte = 0;
1558 temp.bitfield.word = 0;
1559 temp.bitfield.dword = 0;
1560 temp.bitfield.fword = 0;
1561 temp.bitfield.qword = 0;
1562 temp.bitfield.tbyte = 0;
1563 temp.bitfield.xmmword = 0;
c0f3af97 1564 temp.bitfield.ymmword = 0;
0dfbf9d7 1565 if (operand_type_all_zero (&temp))
40fb9820
L		 1566 return 0;
1567
1568 return (given.bitfield.baseindex == overlap.bitfield.baseindex
1569 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute);
1570}
1571
7d5e4556 1572/* If given types g0 and g1 are registers they must be of the same type
40fb9820
L		 1573 unless the expected operand type register overlap is null.
1574 Note that Acc in a template matches every size of reg. */
1575
c6fb90c8 1576static INLINE int
40fb9820
L		 1577operand_type_register_match (i386_operand_type m0,
1578 i386_operand_type g0,
1579 i386_operand_type t0,
1580 i386_operand_type m1,
1581 i386_operand_type g1,
1582 i386_operand_type t1)
1583{
1584 if (!operand_type_check (g0, reg))
1585 return 1;
1586
1587 if (!operand_type_check (g1, reg))
1588 return 1;
1589
1590 if (g0.bitfield.reg8 == g1.bitfield.reg8
1591 && g0.bitfield.reg16 == g1.bitfield.reg16
1592 && g0.bitfield.reg32 == g1.bitfield.reg32
1593 && g0.bitfield.reg64 == g1.bitfield.reg64)
1594 return 1;
1595
1596 if (m0.bitfield.acc)
1597 {
1598 t0.bitfield.reg8 = 1;
1599 t0.bitfield.reg16 = 1;
1600 t0.bitfield.reg32 = 1;
1601 t0.bitfield.reg64 = 1;
1602 }
1603
1604 if (m1.bitfield.acc)
1605 {
1606 t1.bitfield.reg8 = 1;
1607 t1.bitfield.reg16 = 1;
1608 t1.bitfield.reg32 = 1;
1609 t1.bitfield.reg64 = 1;
1610 }
1611
1612 return (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1613 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1614 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1615 && !(t0.bitfield.reg64 & t1.bitfield.reg64));
1616}
1617
252b5132 1618static INLINE unsigned int
40fb9820 1619mode_from_disp_size (i386_operand_type t)
252b5132 1620{
40fb9820
L		 1621 if (t.bitfield.disp8)
1622 return 1;
1623 else if (t.bitfield.disp16
1624 || t.bitfield.disp32
1625 || t.bitfield.disp32s)
1626 return 2;
1627 else
1628 return 0;
252b5132
RH		 1629}
1630
1631static INLINE int
e3bb37b5 1632fits_in_signed_byte (offsetT num)
252b5132
RH		 1633{
1634 return (num >= -128) && (num <= 127);
47926f60 1635}
252b5132
RH		 1636
1637static INLINE int
e3bb37b5 1638fits_in_unsigned_byte (offsetT num)
252b5132
RH		 1639{
1640 return (num & 0xff) == num;
47926f60 1641}
252b5132
RH		 1642
1643static INLINE int
e3bb37b5 1644fits_in_unsigned_word (offsetT num)
252b5132
RH		 1645{
1646 return (num & 0xffff) == num;
47926f60 1647}
252b5132
RH		 1648
1649static INLINE int
e3bb37b5 1650fits_in_signed_word (offsetT num)
252b5132
RH		 1651{
1652 return (-32768 <= num) && (num <= 32767);
47926f60 1653}
2a962e6d 1654
3e73aa7c 1655static INLINE int
e3bb37b5 1656fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1657{
1658#ifndef BFD64
1659 return 1;
1660#else
1661 return (!(((offsetT) -1 << 31) & num)
1662 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1663#endif
1664} /* fits_in_signed_long() */
2a962e6d 1665
3e73aa7c 1666static INLINE int
e3bb37b5 1667fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
3e73aa7c
JH		 1668{
1669#ifndef BFD64
1670 return 1;
1671#else
1672 return (num & (((offsetT) 2 << 31) - 1)) == num;
1673#endif
1674} /* fits_in_unsigned_long() */
252b5132 1675
40fb9820 1676static i386_operand_type
e3bb37b5 1677smallest_imm_type (offsetT num)
252b5132 1678{
40fb9820
L		 1679 i386_operand_type t;
1680
0dfbf9d7 1681 operand_type_set (&t, 0);
40fb9820
L		 1682 t.bitfield.imm64 = 1;
1683
1684 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
e413e4e9
AM		 1685 {
1686 /* This code is disabled on the 486 because all the Imm1 forms
1687 in the opcode table are slower on the i486. They're the
1688 versions with the implicitly specified single-position
1689 displacement, which has another syntax if you really want to
1690 use that form. */
40fb9820
L		 1691 t.bitfield.imm1 = 1;
1692 t.bitfield.imm8 = 1;
1693 t.bitfield.imm8s = 1;
1694 t.bitfield.imm16 = 1;
1695 t.bitfield.imm32 = 1;
1696 t.bitfield.imm32s = 1;
1697 }
1698 else if (fits_in_signed_byte (num))
1699 {
1700 t.bitfield.imm8 = 1;
1701 t.bitfield.imm8s = 1;
1702 t.bitfield.imm16 = 1;
1703 t.bitfield.imm32 = 1;
1704 t.bitfield.imm32s = 1;
1705 }
1706 else if (fits_in_unsigned_byte (num))
1707 {
1708 t.bitfield.imm8 = 1;
1709 t.bitfield.imm16 = 1;
1710 t.bitfield.imm32 = 1;
1711 t.bitfield.imm32s = 1;
1712 }
1713 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1714 {
1715 t.bitfield.imm16 = 1;
1716 t.bitfield.imm32 = 1;
1717 t.bitfield.imm32s = 1;
1718 }
1719 else if (fits_in_signed_long (num))
1720 {
1721 t.bitfield.imm32 = 1;
1722 t.bitfield.imm32s = 1;
1723 }
1724 else if (fits_in_unsigned_long (num))
1725 t.bitfield.imm32 = 1;
1726
1727 return t;
47926f60 1728}
252b5132 1729
847f7ad4 1730static offsetT
e3bb37b5 1731offset_in_range (offsetT val, int size)
847f7ad4 1732{
508866be 1733 addressT mask;
ba2adb93 1734
847f7ad4
AM		 1735 switch (size)
1736 {
508866be
L		 1737 case 1: mask = ((addressT) 1 << 8) - 1; break;
1738 case 2: mask = ((addressT) 1 << 16) - 1; break;
3b0ec529 1739 case 4: mask = ((addressT) 2 << 31) - 1; break;
3e73aa7c
JH		 1740#ifdef BFD64
1741 case 8: mask = ((addressT) 2 << 63) - 1; break;
1742#endif
47926f60 1743 default: abort ();
847f7ad4
AM		 1744 }
1745
ba2adb93 1746 /* If BFD64, sign extend val. */
3e73aa7c
JH		 1747 if (!use_rela_relocations)
1748 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1749 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
ba2adb93 1750
47926f60 1751 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
847f7ad4
AM		 1752 {
1753 char buf1[40], buf2[40];
1754
1755 sprint_value (buf1, val);
1756 sprint_value (buf2, val & mask);
1757 as_warn (_("%s shortened to %s"), buf1, buf2);
1758 }
1759 return val & mask;
1760}
1761
252b5132
RH		 1762/* Returns 0 if attempting to add a prefix where one from the same
1763 class already exists, 1 if non rep/repne added, 2 if rep/repne
1764 added. */
1765static int
e3bb37b5 1766add_prefix (unsigned int prefix)
252b5132
RH		 1767{
1768 int ret = 1;
b1905489 1769 unsigned int q;
252b5132 1770
29b0f896
AM		 1771 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1772 && flag_code == CODE_64BIT)
b1905489 1773 {
161a04f6
L		 1774 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1775 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1776 && (prefix & (REX_R | REX_X | REX_B))))
b1905489
JB		 1777 ret = 0;
1778 q = REX_PREFIX;
1779 }
3e73aa7c 1780 else
b1905489
JB		 1781 {
1782 switch (prefix)
1783 {
1784 default:
1785 abort ();
1786
1787 case CS_PREFIX_OPCODE:
1788 case DS_PREFIX_OPCODE:
1789 case ES_PREFIX_OPCODE:
1790 case FS_PREFIX_OPCODE:
1791 case GS_PREFIX_OPCODE:
1792 case SS_PREFIX_OPCODE:
1793 q = SEG_PREFIX;
1794 break;
1795
1796 case REPNE_PREFIX_OPCODE:
1797 case REPE_PREFIX_OPCODE:
1798 ret = 2;
1799 /* fall thru */
1800 case LOCK_PREFIX_OPCODE:
1801 q = LOCKREP_PREFIX;
1802 break;
1803
1804 case FWAIT_OPCODE:
1805 q = WAIT_PREFIX;
1806 break;
1807
1808 case ADDR_PREFIX_OPCODE:
1809 q = ADDR_PREFIX;
1810 break;
1811
1812 case DATA_PREFIX_OPCODE:
1813 q = DATA_PREFIX;
1814 break;
1815 }
1816 if (i.prefix[q] != 0)
1817 ret = 0;
1818 }
252b5132 1819
b1905489 1820 if (ret)
252b5132 1821 {
b1905489
JB		 1822 if (!i.prefix[q])
1823 ++i.prefixes;
1824 i.prefix[q] |= prefix;
252b5132 1825 }
b1905489
JB		 1826 else
1827 as_bad (_("same type of prefix used twice"));
252b5132 1828
252b5132
RH		 1829 return ret;
1830}
1831
1832static void
e3bb37b5 1833set_code_flag (int value)
eecb386c 1834{
3e73aa7c 1835 flag_code = value;
40fb9820
L		 1836 if (flag_code == CODE_64BIT)
1837 {
1838 cpu_arch_flags.bitfield.cpu64 = 1;
1839 cpu_arch_flags.bitfield.cpuno64 = 0;
40fb9820
L		 1840 }
1841 else
1842 {
1843 cpu_arch_flags.bitfield.cpu64 = 0;
1844 cpu_arch_flags.bitfield.cpuno64 = 1;
40fb9820
L		 1845 }
1846 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
3e73aa7c
JH		 1847 {
1848 as_bad (_("64bit mode not supported on this CPU."));
1849 }
40fb9820 1850 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
3e73aa7c
JH		 1851 {
1852 as_bad (_("32bit mode not supported on this CPU."));
1853 }
eecb386c
AM		 1854 stackop_size = '\0';
1855}
1856
1857static void
e3bb37b5 1858set_16bit_gcc_code_flag (int new_code_flag)
252b5132 1859{
3e73aa7c 1860 flag_code = new_code_flag;
40fb9820
L		 1861 if (flag_code != CODE_16BIT)
1862 abort ();
1863 cpu_arch_flags.bitfield.cpu64 = 0;
1864 cpu_arch_flags.bitfield.cpuno64 = 1;
9306ca4a 1865 stackop_size = LONG_MNEM_SUFFIX;
252b5132
RH		 1866}
1867
1868static void
e3bb37b5 1869set_intel_syntax (int syntax_flag)
252b5132
RH		 1870{
1871 /* Find out if register prefixing is specified. */
1872 int ask_naked_reg = 0;
1873
1874 SKIP_WHITESPACE ();
29b0f896 1875 if (!is_end_of_line[(unsigned char) *input_line_pointer])
252b5132
RH		 1876 {
1877 char *string = input_line_pointer;
1878 int e = get_symbol_end ();
1879
47926f60 1880 if (strcmp (string, "prefix") == 0)
252b5132 1881 ask_naked_reg = 1;
47926f60 1882 else if (strcmp (string, "noprefix") == 0)
252b5132
RH		 1883 ask_naked_reg = -1;
1884 else
d0b47220 1885 as_bad (_("bad argument to syntax directive."));
252b5132
RH		 1886 *input_line_pointer = e;
1887 }
1888 demand_empty_rest_of_line ();
c3332e24 1889
252b5132
RH		 1890 intel_syntax = syntax_flag;
1891
1892 if (ask_naked_reg == 0)
f86103b7
AM		 1893 allow_naked_reg = (intel_syntax
1894 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
252b5132
RH		 1895 else
1896 allow_naked_reg = (ask_naked_reg < 0);
9306ca4a 1897
e4a3b5a4 1898 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
9306ca4a 1899 identifier_chars['$'] = intel_syntax ? '$' : 0;
e4a3b5a4 1900 register_prefix = allow_naked_reg ? "" : "%";
252b5132
RH		 1901}
1902
1efbbeb4
L		 1903static void
1904set_intel_mnemonic (int mnemonic_flag)
1905{
e1d4d893 1906 intel_mnemonic = mnemonic_flag;
1efbbeb4
L		 1907}
1908
db51cc60
L		 1909static void
1910set_allow_index_reg (int flag)
1911{
1912 allow_index_reg = flag;
1913}
1914
cb19c032
L		 1915static void
1916set_sse_check (int dummy ATTRIBUTE_UNUSED)
1917{
1918 SKIP_WHITESPACE ();
1919
1920 if (!is_end_of_line[(unsigned char) *input_line_pointer])
1921 {
1922 char *string = input_line_pointer;
1923 int e = get_symbol_end ();
1924
1925 if (strcmp (string, "none") == 0)
1926 sse_check = sse_check_none;
1927 else if (strcmp (string, "warning") == 0)
1928 sse_check = sse_check_warning;
1929 else if (strcmp (string, "error") == 0)
1930 sse_check = sse_check_error;
1931 else
1932 as_bad (_("bad argument to sse_check directive."));
1933 *input_line_pointer = e;
1934 }
1935 else
1936 as_bad (_("missing argument for sse_check directive"));
1937
1938 demand_empty_rest_of_line ();
1939}
1940
e413e4e9 1941static void
e3bb37b5 1942set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
e413e4e9 1943{
47926f60 1944 SKIP_WHITESPACE ();
e413e4e9 1945
29b0f896 1946 if (!is_end_of_line[(unsigned char) *input_line_pointer])
e413e4e9
AM		 1947 {
1948 char *string = input_line_pointer;
1949 int e = get_symbol_end ();
9103f4f4 1950 unsigned int i;
40fb9820 1951 i386_cpu_flags flags;
e413e4e9 1952
9103f4f4 1953 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
e413e4e9
AM		 1954 {
1955 if (strcmp (string, cpu_arch[i].name) == 0)
1956 {
5c6af06e
JB		 1957 if (*string != '.')
1958 {
1959 cpu_arch_name = cpu_arch[i].name;
1960 cpu_sub_arch_name = NULL;
40fb9820
L		 1961 cpu_arch_flags = cpu_arch[i].flags;
1962 if (flag_code == CODE_64BIT)
1963 {
1964 cpu_arch_flags.bitfield.cpu64 = 1;
1965 cpu_arch_flags.bitfield.cpuno64 = 0;
1966 }
1967 else
1968 {
1969 cpu_arch_flags.bitfield.cpu64 = 0;
1970 cpu_arch_flags.bitfield.cpuno64 = 1;
1971 }
ccc9c027 1972 cpu_arch_isa = cpu_arch[i].type;
9103f4f4 1973 cpu_arch_isa_flags = cpu_arch[i].flags;
ccc9c027
L		 1974 if (!cpu_arch_tune_set)
1975 {
1976 cpu_arch_tune = cpu_arch_isa;
1977 cpu_arch_tune_flags = cpu_arch_isa_flags;
1978 }
5c6af06e
JB		 1979 break;
1980 }
40fb9820 1981
c6fb90c8
L		 1982 flags = cpu_flags_or (cpu_arch_flags,
1983 cpu_arch[i].flags);
0dfbf9d7 1984 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
5c6af06e 1985 {
6305a203
L		 1986 if (cpu_sub_arch_name)
1987 {
1988 char *name = cpu_sub_arch_name;
1989 cpu_sub_arch_name = concat (name,
1990 cpu_arch[i].name,
1bf57e9f 1991 (const char *) NULL);
6305a203
L		 1992 free (name);
1993 }
1994 else
1995 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
40fb9820 1996 cpu_arch_flags = flags;
5c6af06e
JB		 1997 }
1998 *input_line_pointer = e;
1999 demand_empty_rest_of_line ();
2000 return;
e413e4e9
AM		 2001 }
2002 }
9103f4f4 2003 if (i >= ARRAY_SIZE (cpu_arch))
e413e4e9
AM		 2004 as_bad (_("no such architecture: `%s'"), string);
2005
2006 *input_line_pointer = e;
2007 }
2008 else
2009 as_bad (_("missing cpu architecture"));
2010
fddf5b5b
AM		 2011 no_cond_jump_promotion = 0;
2012 if (*input_line_pointer == ','
29b0f896 2013 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
fddf5b5b
AM		 2014 {
2015 char *string = ++input_line_pointer;
2016 int e = get_symbol_end ();
2017
2018 if (strcmp (string, "nojumps") == 0)
2019 no_cond_jump_promotion = 1;
2020 else if (strcmp (string, "jumps") == 0)
2021 ;
2022 else
2023 as_bad (_("no such architecture modifier: `%s'"), string);
2024
2025 *input_line_pointer = e;
2026 }
2027
e413e4e9
AM		 2028 demand_empty_rest_of_line ();
2029}
2030
b9d79e03
JH		 2031unsigned long
2032i386_mach ()
2033{
2034 if (!strcmp (default_arch, "x86_64"))
2035 return bfd_mach_x86_64;
2036 else if (!strcmp (default_arch, "i386"))
2037 return bfd_mach_i386_i386;
2038 else
2039 as_fatal (_("Unknown architecture"));
2040}
b9d79e03 2041\f
252b5132
RH		 2042void
2043md_begin ()
2044{
2045 const char *hash_err;
2046
47926f60 2047 /* Initialize op_hash hash table. */
252b5132
RH		 2048 op_hash = hash_new ();
2049
2050 {
29b0f896
AM		 2051 const template *optab;
2052 templates *core_optab;
252b5132 2053
47926f60
KH		 2054 /* Setup for loop. */
2055 optab = i386_optab;
252b5132
RH		 2056 core_optab = (templates *) xmalloc (sizeof (templates));
2057 core_optab->start = optab;
2058
2059 while (1)
2060 {
2061 ++optab;
2062 if (optab->name == NULL
2063 || strcmp (optab->name, (optab - 1)->name) != 0)
2064 {
2065 /* different name --> ship out current template list;
47926f60 2066 add to hash table; & begin anew. */
252b5132
RH		 2067 core_optab->end = optab;
2068 hash_err = hash_insert (op_hash,
2069 (optab - 1)->name,
5a49b8ac 2070 (void *) core_optab);
252b5132
RH		 2071 if (hash_err)
2072 {
252b5132
RH		 2073 as_fatal (_("Internal Error: Can't hash %s: %s"),
2074 (optab - 1)->name,
2075 hash_err);
2076 }
2077 if (optab->name == NULL)
2078 break;
2079 core_optab = (templates *) xmalloc (sizeof (templates));
2080 core_optab->start = optab;
2081 }
2082 }
2083 }
2084
47926f60 2085 /* Initialize reg_hash hash table. */
252b5132
RH		 2086 reg_hash = hash_new ();
2087 {
29b0f896 2088 const reg_entry *regtab;
c3fe08fa 2089 unsigned int regtab_size = i386_regtab_size;
252b5132 2090
c3fe08fa 2091 for (regtab = i386_regtab; regtab_size--; regtab++)
252b5132 2092 {
5a49b8ac 2093 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
252b5132 2094 if (hash_err)
3e73aa7c
JH		 2095 as_fatal (_("Internal Error: Can't hash %s: %s"),
2096 regtab->reg_name,
2097 hash_err);
252b5132
RH		 2098 }
2099 }
2100
47926f60 2101 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
252b5132 2102 {
29b0f896
AM		 2103 int c;
2104 char *p;
252b5132
RH		 2105
2106 for (c = 0; c < 256; c++)
2107 {
3882b010 2108 if (ISDIGIT (c))
252b5132
RH		 2109 {
2110 digit_chars[c] = c;
2111 mnemonic_chars[c] = c;
2112 register_chars[c] = c;
2113 operand_chars[c] = c;
2114 }
3882b010 2115 else if (ISLOWER (c))
252b5132
RH		 2116 {
2117 mnemonic_chars[c] = c;
2118 register_chars[c] = c;
2119 operand_chars[c] = c;
2120 }
3882b010 2121 else if (ISUPPER (c))
252b5132 2122 {
3882b010 2123 mnemonic_chars[c] = TOLOWER (c);
252b5132
RH		 2124 register_chars[c] = mnemonic_chars[c];
2125 operand_chars[c] = c;
2126 }
2127
3882b010 2128 if (ISALPHA (c) || ISDIGIT (c))
252b5132
RH		 2129 identifier_chars[c] = c;
2130 else if (c >= 128)
2131 {
2132 identifier_chars[c] = c;
2133 operand_chars[c] = c;
2134 }
2135 }
2136
2137#ifdef LEX_AT
2138 identifier_chars['@'] = '@';
32137342
NC		 2139#endif
2140#ifdef LEX_QM
2141 identifier_chars['?'] = '?';
2142 operand_chars['?'] = '?';
252b5132 2143#endif
252b5132 2144 digit_chars['-'] = '-';
c0f3af97 2145 mnemonic_chars['_'] = '_';
791fe849 2146 mnemonic_chars['-'] = '-';
0003779b 2147 mnemonic_chars['.'] = '.';
252b5132
RH		 2148 identifier_chars['_'] = '_';
2149 identifier_chars['.'] = '.';
2150
2151 for (p = operand_special_chars; *p != '\0'; p++)
2152 operand_chars[(unsigned char) *p] = *p;
2153 }
2154
2155#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2156 if (IS_ELF)
252b5132
RH		 2157 {
2158 record_alignment (text_section, 2);
2159 record_alignment (data_section, 2);
2160 record_alignment (bss_section, 2);
2161 }
2162#endif
a4447b93
RH		 2163
2164 if (flag_code == CODE_64BIT)
2165 {
2166 x86_dwarf2_return_column = 16;
2167 x86_cie_data_alignment = -8;
2168 }
2169 else
2170 {
2171 x86_dwarf2_return_column = 8;
2172 x86_cie_data_alignment = -4;
2173 }
252b5132
RH		 2174}
2175
2176void
e3bb37b5 2177i386_print_statistics (FILE *file)
252b5132
RH		 2178{
2179 hash_print_statistics (file, "i386 opcode", op_hash);
2180 hash_print_statistics (file, "i386 register", reg_hash);
2181}
2182\f
252b5132
RH		 2183#ifdef DEBUG386
2184
ce8a8b2f 2185/* Debugging routines for md_assemble. */
e3bb37b5 2186static void pte (template *);
40fb9820 2187static void pt (i386_operand_type);
e3bb37b5
L		 2188static void pe (expressionS *);
2189static void ps (symbolS *);
252b5132
RH		 2190
2191static void
e3bb37b5 2192pi (char *line, i386_insn *x)
252b5132 2193{
09f131f2 2194 unsigned int i;
252b5132
RH		 2195
2196 fprintf (stdout, "%s: template ", line);
2197 pte (&x->tm);
09f131f2
JH		 2198 fprintf (stdout, " address: base %s index %s scale %x\n",
2199 x->base_reg ? x->base_reg->reg_name : "none",
2200 x->index_reg ? x->index_reg->reg_name : "none",
2201 x->log2_scale_factor);
2202 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
252b5132 2203 x->rm.mode, x->rm.reg, x->rm.regmem);
09f131f2
JH		 2204 fprintf (stdout, " sib: base %x index %x scale %x\n",
2205 x->sib.base, x->sib.index, x->sib.scale);
2206 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
161a04f6
L		 2207 (x->rex & REX_W) != 0,
2208 (x->rex & REX_R) != 0,
2209 (x->rex & REX_X) != 0,
2210 (x->rex & REX_B) != 0);
85f10a01
MM		 2211 fprintf (stdout, " drex: reg %d rex 0x%x\n",
2212 x->drex.reg, x->drex.rex);
252b5132
RH		 2213 for (i = 0; i < x->operands; i++)
2214 {
2215 fprintf (stdout, " #%d: ", i + 1);
2216 pt (x->types[i]);
2217 fprintf (stdout, "\n");
40fb9820
L		 2218 if (x->types[i].bitfield.reg8
2219 || x->types[i].bitfield.reg16
2220 || x->types[i].bitfield.reg32
2221 || x->types[i].bitfield.reg64
2222 || x->types[i].bitfield.regmmx
2223 || x->types[i].bitfield.regxmm
c0f3af97 2224 || x->types[i].bitfield.regymm
40fb9820
L		 2225 || x->types[i].bitfield.sreg2
2226 || x->types[i].bitfield.sreg3
2227 || x->types[i].bitfield.control
2228 || x->types[i].bitfield.debug
2229 || x->types[i].bitfield.test)
520dc8e8 2230 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
40fb9820 2231 if (operand_type_check (x->types[i], imm))
520dc8e8 2232 pe (x->op[i].imms);
40fb9820 2233 if (operand_type_check (x->types[i], disp))
520dc8e8 2234 pe (x->op[i].disps);
252b5132
RH		 2235 }
2236}
2237
2238static void
e3bb37b5 2239pte (template *t)
252b5132 2240{
09f131f2 2241 unsigned int i;
252b5132 2242 fprintf (stdout, " %d operands ", t->operands);
47926f60 2243 fprintf (stdout, "opcode %x ", t->base_opcode);
252b5132
RH		 2244 if (t->extension_opcode != None)
2245 fprintf (stdout, "ext %x ", t->extension_opcode);
40fb9820 2246 if (t->opcode_modifier.d)
252b5132 2247 fprintf (stdout, "D");
40fb9820 2248 if (t->opcode_modifier.w)
252b5132
RH		 2249 fprintf (stdout, "W");
2250 fprintf (stdout, "\n");
2251 for (i = 0; i < t->operands; i++)
2252 {
2253 fprintf (stdout, " #%d type ", i + 1);
2254 pt (t->operand_types[i]);
2255 fprintf (stdout, "\n");
2256 }
2257}
2258
2259static void
e3bb37b5 2260pe (expressionS *e)
252b5132 2261{
24eab124 2262 fprintf (stdout, " operation %d\n", e->X_op);
b77ad1d4
AM		 2263 fprintf (stdout, " add_number %ld (%lx)\n",
2264 (long) e->X_add_number, (long) e->X_add_number);
252b5132
RH		 2265 if (e->X_add_symbol)
2266 {
2267 fprintf (stdout, " add_symbol ");
2268 ps (e->X_add_symbol);
2269 fprintf (stdout, "\n");
2270 }
2271 if (e->X_op_symbol)
2272 {
2273 fprintf (stdout, " op_symbol ");
2274 ps (e->X_op_symbol);
2275 fprintf (stdout, "\n");
2276 }
2277}
2278
2279static void
e3bb37b5 2280ps (symbolS *s)
252b5132
RH		 2281{
2282 fprintf (stdout, "%s type %s%s",
2283 S_GET_NAME (s),
2284 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2285 segment_name (S_GET_SEGMENT (s)));
2286}
2287
7b81dfbb 2288static struct type_name
252b5132 2289 {
40fb9820
L		 2290 i386_operand_type mask;
2291 const char *name;
252b5132 2292 }
7b81dfbb 2293const type_names[] =
252b5132 2294{
40fb9820
L		 2295 { OPERAND_TYPE_REG8, "r8" },
2296 { OPERAND_TYPE_REG16, "r16" },
2297 { OPERAND_TYPE_REG32, "r32" },
2298 { OPERAND_TYPE_REG64, "r64" },
2299 { OPERAND_TYPE_IMM8, "i8" },
2300 { OPERAND_TYPE_IMM8, "i8s" },
2301 { OPERAND_TYPE_IMM16, "i16" },
2302 { OPERAND_TYPE_IMM32, "i32" },
2303 { OPERAND_TYPE_IMM32S, "i32s" },
2304 { OPERAND_TYPE_IMM64, "i64" },
2305 { OPERAND_TYPE_IMM1, "i1" },
2306 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2307 { OPERAND_TYPE_DISP8, "d8" },
2308 { OPERAND_TYPE_DISP16, "d16" },
2309 { OPERAND_TYPE_DISP32, "d32" },
2310 { OPERAND_TYPE_DISP32S, "d32s" },
2311 { OPERAND_TYPE_DISP64, "d64" },
2312 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2313 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2314 { OPERAND_TYPE_CONTROL, "control reg" },
2315 { OPERAND_TYPE_TEST, "test reg" },
2316 { OPERAND_TYPE_DEBUG, "debug reg" },
2317 { OPERAND_TYPE_FLOATREG, "FReg" },
2318 { OPERAND_TYPE_FLOATACC, "FAcc" },
2319 { OPERAND_TYPE_SREG2, "SReg2" },
2320 { OPERAND_TYPE_SREG3, "SReg3" },
2321 { OPERAND_TYPE_ACC, "Acc" },
2322 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2323 { OPERAND_TYPE_REGMMX, "rMMX" },
2324 { OPERAND_TYPE_REGXMM, "rXMM" },
0349dc08 2325 { OPERAND_TYPE_REGYMM, "rYMM" },
40fb9820 2326 { OPERAND_TYPE_ESSEG, "es" },
252b5132
RH		 2327};
2328
2329static void
40fb9820 2330pt (i386_operand_type t)
252b5132 2331{
40fb9820 2332 unsigned int j;
c6fb90c8 2333 i386_operand_type a;
252b5132 2334
40fb9820 2335 for (j = 0; j < ARRAY_SIZE (type_names); j++)
c6fb90c8
L		 2336 {
2337 a = operand_type_and (t, type_names[j].mask);
0349dc08 2338 if (!operand_type_all_zero (&a))
c6fb90c8
L		 2339 fprintf (stdout, "%s, ", type_names[j].name);
2340 }
252b5132
RH		 2341 fflush (stdout);
2342}
2343
2344#endif /* DEBUG386 */
2345\f
252b5132 2346static bfd_reloc_code_real_type
3956db08 2347reloc (unsigned int size,
64e74474
AM		 2348 int pcrel,
2349 int sign,
2350 bfd_reloc_code_real_type other)
252b5132 2351{
47926f60 2352 if (other != NO_RELOC)
3956db08
JB		 2353 {
2354 reloc_howto_type *reloc;
2355
2356 if (size == 8)
2357 switch (other)
2358 {
64e74474
AM		 2359 case BFD_RELOC_X86_64_GOT32:
2360 return BFD_RELOC_X86_64_GOT64;
2361 break;
2362 case BFD_RELOC_X86_64_PLTOFF64:
2363 return BFD_RELOC_X86_64_PLTOFF64;
2364 break;
2365 case BFD_RELOC_X86_64_GOTPC32:
2366 other = BFD_RELOC_X86_64_GOTPC64;
2367 break;
2368 case BFD_RELOC_X86_64_GOTPCREL:
2369 other = BFD_RELOC_X86_64_GOTPCREL64;
2370 break;
2371 case BFD_RELOC_X86_64_TPOFF32:
2372 other = BFD_RELOC_X86_64_TPOFF64;
2373 break;
2374 case BFD_RELOC_X86_64_DTPOFF32:
2375 other = BFD_RELOC_X86_64_DTPOFF64;
2376 break;
2377 default:
2378 break;
3956db08 2379 }
e05278af
JB		 2380
2381 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2382 if (size == 4 && flag_code != CODE_64BIT)
2383 sign = -1;
2384
3956db08
JB		 2385 reloc = bfd_reloc_type_lookup (stdoutput, other);
2386 if (!reloc)
2387 as_bad (_("unknown relocation (%u)"), other);
2388 else if (size != bfd_get_reloc_size (reloc))
2389 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2390 bfd_get_reloc_size (reloc),
2391 size);
2392 else if (pcrel && !reloc->pc_relative)
2393 as_bad (_("non-pc-relative relocation for pc-relative field"));
2394 else if ((reloc->complain_on_overflow == complain_overflow_signed
2395 && !sign)
2396 || (reloc->complain_on_overflow == complain_overflow_unsigned
64e74474 2397 && sign > 0))
3956db08
JB		 2398 as_bad (_("relocated field and relocation type differ in signedness"));
2399 else
2400 return other;
2401 return NO_RELOC;
2402 }
252b5132
RH		 2403
2404 if (pcrel)
2405 {
3e73aa7c 2406 if (!sign)
3956db08 2407 as_bad (_("there are no unsigned pc-relative relocations"));
252b5132
RH		 2408 switch (size)
2409 {
2410 case 1: return BFD_RELOC_8_PCREL;
2411 case 2: return BFD_RELOC_16_PCREL;
2412 case 4: return BFD_RELOC_32_PCREL;
d6ab8113 2413 case 8: return BFD_RELOC_64_PCREL;
252b5132 2414 }
3956db08 2415 as_bad (_("cannot do %u byte pc-relative relocation"), size);
252b5132
RH		 2416 }
2417 else
2418 {
3956db08 2419 if (sign > 0)
e5cb08ac 2420 switch (size)
3e73aa7c
JH		 2421 {
2422 case 4: return BFD_RELOC_X86_64_32S;
2423 }
2424 else
2425 switch (size)
2426 {
2427 case 1: return BFD_RELOC_8;
2428 case 2: return BFD_RELOC_16;
2429 case 4: return BFD_RELOC_32;
2430 case 8: return BFD_RELOC_64;
2431 }
3956db08
JB		 2432 as_bad (_("cannot do %s %u byte relocation"),
2433 sign > 0 ? "signed" : "unsigned", size);
252b5132
RH		 2434 }
2435
0cc9e1d3 2436 return NO_RELOC;
252b5132
RH		 2437}
2438
47926f60
KH		 2439/* Here we decide which fixups can be adjusted to make them relative to
2440 the beginning of the section instead of the symbol. Basically we need
2441 to make sure that the dynamic relocations are done correctly, so in
2442 some cases we force the original symbol to be used. */
2443
252b5132 2444int
e3bb37b5 2445tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
252b5132 2446{
6d249963 2447#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 2448 if (!IS_ELF)
31312f95
AM		 2449 return 1;
2450
a161fe53
AM		 2451 /* Don't adjust pc-relative references to merge sections in 64-bit
2452 mode. */
2453 if (use_rela_relocations
2454 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2455 && fixP->fx_pcrel)
252b5132 2456 return 0;
31312f95 2457
8d01d9a9
AJ		 2458 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2459 and changed later by validate_fix. */
2460 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2461 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2462 return 0;
2463
ce8a8b2f 2464 /* adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 2465 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2466 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2467 || fixP->fx_r_type == BFD_RELOC_386_GOT32
13ae64f3
JJ		 2468 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2469 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2470 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2471 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
37e55690
JJ		 2472 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2473 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
13ae64f3
JJ		 2474 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2475 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
67a4f2b7
AO		 2476 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2477 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
3e73aa7c
JH		 2478 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2479 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
80b3ee89 2480 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
bffbf940
JJ		 2481 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2482 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2483 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
d6ab8113 2484 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
bffbf940
JJ		 2485 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2486 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
d6ab8113
JB		 2487 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2488 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
67a4f2b7
AO		 2489 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2490 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
252b5132
RH		 2491 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2492 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2493 return 0;
31312f95 2494#endif
252b5132
RH		 2495 return 1;
2496}
252b5132 2497
b4cac588 2498static int
e3bb37b5 2499intel_float_operand (const char *mnemonic)
252b5132 2500{
9306ca4a
JB		 2501 /* Note that the value returned is meaningful only for opcodes with (memory)
2502 operands, hence the code here is free to improperly handle opcodes that
2503 have no operands (for better performance and smaller code). */
2504
2505 if (mnemonic[0] != 'f')
2506 return 0; /* non-math */
2507
2508 switch (mnemonic[1])
2509 {
2510 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2511 the fs segment override prefix not currently handled because no
2512 call path can make opcodes without operands get here */
2513 case 'i':
2514 return 2 /* integer op */;
2515 case 'l':
2516 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2517 return 3; /* fldcw/fldenv */
2518 break;
2519 case 'n':
2520 if (mnemonic[2] != 'o' /* fnop */)
2521 return 3; /* non-waiting control op */
2522 break;
2523 case 'r':
2524 if (mnemonic[2] == 's')
2525 return 3; /* frstor/frstpm */
2526 break;
2527 case 's':
2528 if (mnemonic[2] == 'a')
2529 return 3; /* fsave */
2530 if (mnemonic[2] == 't')
2531 {
2532 switch (mnemonic[3])
2533 {
2534 case 'c': /* fstcw */
2535 case 'd': /* fstdw */
2536 case 'e': /* fstenv */
2537 case 's': /* fsts[gw] */
2538 return 3;
2539 }
2540 }
2541 break;
2542 case 'x':
2543 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2544 return 0; /* fxsave/fxrstor are not really math ops */
2545 break;
2546 }
252b5132 2547
9306ca4a 2548 return 1;
252b5132
RH		 2549}
2550
c0f3af97
L		 2551/* Build the VEX prefix. */
2552
2553static void
fa99fab2 2554build_vex_prefix (const template *t)
c0f3af97
L		 2555{
2556 unsigned int register_specifier;
2557 unsigned int implied_prefix;
2558 unsigned int vector_length;
2559
2560 /* Check register specifier. */
2561 if (i.vex.register_specifier)
2562 {
2563 register_specifier = i.vex.register_specifier->reg_num;
2564 if ((i.vex.register_specifier->reg_flags & RegRex))
2565 register_specifier += 8;
2566 register_specifier = ~register_specifier & 0xf;
2567 }
2568 else
2569 register_specifier = 0xf;
2570
fa99fab2
L		 2571 /* Use 2-byte VEX prefix by swappping destination and source
2572 operand. */
2573 if (!i.swap_operand
2574 && i.operands == i.reg_operands
2575 && i.tm.opcode_modifier.vex0f
2576 && i.tm.opcode_modifier.s
2577 && i.rex == REX_B)
2578 {
2579 unsigned int xchg = i.operands - 1;
2580 union i386_op temp_op;
2581 i386_operand_type temp_type;
2582
2583 temp_type = i.types[xchg];
2584 i.types[xchg] = i.types[0];
2585 i.types[0] = temp_type;
2586 temp_op = i.op[xchg];
2587 i.op[xchg] = i.op[0];
2588 i.op[0] = temp_op;
2589
2590 assert (i.rm.mode == 3);
2591
2592 i.rex = REX_R;
2593 xchg = i.rm.regmem;
2594 i.rm.regmem = i.rm.reg;
2595 i.rm.reg = xchg;
2596
2597 /* Use the next insn. */
2598 i.tm = t[1];
2599 }
2600
c0f3af97
L		 2601 vector_length = i.tm.opcode_modifier.vex256 ? 1 : 0;
2602
2603 switch ((i.tm.base_opcode >> 8) & 0xff)
2604 {
2605 case 0:
2606 implied_prefix = 0;
2607 break;
2608 case DATA_PREFIX_OPCODE:
2609 implied_prefix = 1;
2610 break;
2611 case REPE_PREFIX_OPCODE:
2612 implied_prefix = 2;
2613 break;
2614 case REPNE_PREFIX_OPCODE:
2615 implied_prefix = 3;
2616 break;
2617 default:
2618 abort ();
2619 }
2620
2621 /* Use 2-byte VEX prefix if possible. */
2622 if (i.tm.opcode_modifier.vex0f
2623 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2624 {
2625 /* 2-byte VEX prefix. */
2626 unsigned int r;
2627
2628 i.vex.length = 2;
2629 i.vex.bytes[0] = 0xc5;
2630
2631 /* Check the REX.R bit. */
2632 r = (i.rex & REX_R) ? 0 : 1;
2633 i.vex.bytes[1] = (r << 7
2634 | register_specifier << 3
2635 | vector_length << 2
2636 | implied_prefix);
2637 }
2638 else
2639 {
2640 /* 3-byte VEX prefix. */
2641 unsigned int m, w;
2642
2643 if (i.tm.opcode_modifier.vex0f)
2644 m = 0x1;
2645 else if (i.tm.opcode_modifier.vex0f38)
2646 m = 0x2;
2647 else if (i.tm.opcode_modifier.vex0f3a)
2648 m = 0x3;
2649 else
2650 abort ();
2651
2652 i.vex.length = 3;
2653 i.vex.bytes[0] = 0xc4;
2654
2655 /* The high 3 bits of the second VEX byte are 1's compliment
2656 of RXB bits from REX. */
2657 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2658
2659 /* Check the REX.W bit. */
2660 w = (i.rex & REX_W) ? 1 : 0;
2661 if (i.tm.opcode_modifier.vexw0 || i.tm.opcode_modifier.vexw1)
2662 {
2663 if (w)
2664 abort ();
2665
2666 if (i.tm.opcode_modifier.vexw1)
2667 w = 1;
2668 }
2669
2670 i.vex.bytes[2] = (w << 7
2671 | register_specifier << 3
2672 | vector_length << 2
2673 | implied_prefix);
2674 }
2675}
2676
65da13b5
L		 2677static void
2678process_immext (void)
2679{
2680 expressionS *exp;
2681
2682 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2683 {
1fed0ba1
L		 2684 /* SSE3 Instructions have the fixed operands with an opcode
2685 suffix which is coded in the same place as an 8-bit immediate
2686 field would be. Here we check those operands and remove them
2687 afterwards. */
65da13b5
L		 2688 unsigned int x;
2689
2690 for (x = 0; x < i.operands; x++)
2691 if (i.op[x].regs->reg_num != x)
2692 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
1fed0ba1
L		 2693 register_prefix, i.op[x].regs->reg_name, x + 1,
2694 i.tm.name);
2695
2696 i.operands = 0;
65da13b5
L		 2697 }
2698
c0f3af97 2699 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
65da13b5
L		 2700 which is coded in the same place as an 8-bit immediate field
2701 would be. Here we fake an 8-bit immediate operand from the
2702 opcode suffix stored in tm.extension_opcode.
2703
c0f3af97
L		 2704 SSE5 and AVX instructions also use this encoding, for some of
2705 3 argument instructions. */
65da13b5
L		 2706
2707 assert (i.imm_operands == 0
2708 && (i.operands <= 2
2709 || (i.tm.cpu_flags.bitfield.cpusse5
c0f3af97
L		 2710 && i.operands <= 3)
2711 || (i.tm.opcode_modifier.vex
2712 && i.operands <= 4)));
65da13b5
L		 2713
2714 exp = &im_expressions[i.imm_operands++];
2715 i.op[i.operands].imms = exp;
2716 i.types[i.operands] = imm8;
2717 i.operands++;
2718 exp->X_op = O_constant;
2719 exp->X_add_number = i.tm.extension_opcode;
2720 i.tm.extension_opcode = None;
2721}
2722
252b5132
RH		 2723/* This is the guts of the machine-dependent assembler. LINE points to a
2724 machine dependent instruction. This function is supposed to emit
2725 the frags/bytes it assembles to. */
2726
2727void
65da13b5 2728md_assemble (char *line)
252b5132 2729{
40fb9820 2730 unsigned int j;
252b5132 2731 char mnemonic[MAX_MNEM_SIZE];
fa99fab2 2732 const template *t;
252b5132 2733
47926f60 2734 /* Initialize globals. */
252b5132
RH		 2735 memset (&i, '\0', sizeof (i));
2736 for (j = 0; j < MAX_OPERANDS; j++)
1ae12ab7 2737 i.reloc[j] = NO_RELOC;
252b5132
RH		 2738 memset (disp_expressions, '\0', sizeof (disp_expressions));
2739 memset (im_expressions, '\0', sizeof (im_expressions));
ce8a8b2f 2740 save_stack_p = save_stack;
252b5132
RH		 2741
2742 /* First parse an instruction mnemonic & call i386_operand for the operands.
2743 We assume that the scrubber has arranged it so that line[0] is the valid
47926f60 2744 start of a (possibly prefixed) mnemonic. */
252b5132 2745
29b0f896
AM		 2746 line = parse_insn (line, mnemonic);
2747 if (line == NULL)
2748 return;
252b5132 2749
29b0f896
AM		 2750 line = parse_operands (line, mnemonic);
2751 if (line == NULL)
2752 return;
252b5132 2753
29b0f896
AM		 2754 /* Now we've parsed the mnemonic into a set of templates, and have the
2755 operands at hand. */
2756
2757 /* All intel opcodes have reversed operands except for "bound" and
2758 "enter". We also don't reverse intersegment "jmp" and "call"
2759 instructions with 2 immediate operands so that the immediate segment
050dfa73 2760 precedes the offset, as it does when in AT&T mode. */
4d456e3d
L		 2761 if (intel_syntax
2762 && i.operands > 1
29b0f896 2763 && (strcmp (mnemonic, "bound") != 0)
30123838 2764 && (strcmp (mnemonic, "invlpga") != 0)
40fb9820
L		 2765 && !(operand_type_check (i.types[0], imm)
2766 && operand_type_check (i.types[1], imm)))
29b0f896
AM		 2767 swap_operands ();
2768
ec56d5c0
JB		 2769 /* The order of the immediates should be reversed
2770 for 2 immediates extrq and insertq instructions */
2771 if (i.imm_operands == 2
2772 && (strcmp (mnemonic, "extrq") == 0
2773 || strcmp (mnemonic, "insertq") == 0))
2774 swap_2_operands (0, 1);
2775
29b0f896
AM		 2776 if (i.imm_operands)
2777 optimize_imm ();
2778
b300c311
L		 2779 /* Don't optimize displacement for movabs since it only takes 64bit
2780 displacement. */
2781 if (i.disp_operands
2782 && (flag_code != CODE_64BIT
2783 || strcmp (mnemonic, "movabs") != 0))
29b0f896
AM		 2784 optimize_disp ();
2785
2786 /* Next, we find a template that matches the given insn,
2787 making sure the overlap of the given operands types is consistent
2788 with the template operand types. */
252b5132 2789
fa99fab2 2790 if (!(t = match_template ()))
29b0f896 2791 return;
252b5132 2792
daf50ae7 2793 if (sse_check != sse_check_none
81f8a913 2794 && !i.tm.opcode_modifier.noavx
daf50ae7
L		 2795 && (i.tm.cpu_flags.bitfield.cpusse
2796 || i.tm.cpu_flags.bitfield.cpusse2
2797 || i.tm.cpu_flags.bitfield.cpusse3
2798 || i.tm.cpu_flags.bitfield.cpussse3
2799 || i.tm.cpu_flags.bitfield.cpusse4_1
2800 || i.tm.cpu_flags.bitfield.cpusse4_2))
2801 {
2802 (sse_check == sse_check_warning
2803 ? as_warn
2804 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
2805 }
2806
321fd21e
L		 2807 /* Zap movzx and movsx suffix. The suffix has been set from
2808 "word ptr" or "byte ptr" on the source operand in Intel syntax
2809 or extracted from mnemonic in AT&T syntax. But we'll use
2810 the destination register to choose the suffix for encoding. */
2811 if ((i.tm.base_opcode & ~9) == 0x0fb6)
cd61ebfe 2812 {
321fd21e
L		 2813 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2814 there is no suffix, the default will be byte extension. */
2815 if (i.reg_operands != 2
2816 && !i.suffix
2817 && intel_syntax)
2818 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
2819
2820 i.suffix = 0;
cd61ebfe 2821 }
24eab124 2822
40fb9820 2823 if (i.tm.opcode_modifier.fwait)
29b0f896
AM		 2824 if (!add_prefix (FWAIT_OPCODE))
2825 return;
252b5132 2826
29b0f896 2827 /* Check string instruction segment overrides. */
40fb9820 2828 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
29b0f896
AM		 2829 {
2830 if (!check_string ())
5dd0794d 2831 return;
fc0763e6 2832 i.disp_operands = 0;
29b0f896 2833 }
5dd0794d 2834
29b0f896
AM		 2835 if (!process_suffix ())
2836 return;
e413e4e9 2837
29b0f896
AM		 2838 /* Make still unresolved immediate matches conform to size of immediate
2839 given in i.suffix. */
2840 if (!finalize_imm ())
2841 return;
252b5132 2842
40fb9820 2843 if (i.types[0].bitfield.imm1)
29b0f896 2844 i.imm_operands = 0; /* kludge for shift insns. */
252b5132 2845
40fb9820 2846 for (j = 0; j < 3; j++)
c6fb90c8
L		 2847 if (i.types[j].bitfield.inoutportreg
2848 || i.types[j].bitfield.shiftcount
2849 || i.types[j].bitfield.acc
2850 || i.types[j].bitfield.floatacc)
40fb9820
L		 2851 i.reg_operands--;
2852
c0f3af97
L		 2853 /* ImmExt should be processed after SSE2AVX. */
2854 if (!i.tm.opcode_modifier.sse2avx
2855 && i.tm.opcode_modifier.immext)
65da13b5 2856 process_immext ();
252b5132 2857
29b0f896
AM		 2858 /* For insns with operands there are more diddles to do to the opcode. */
2859 if (i.operands)
2860 {
2861 if (!process_operands ())
2862 return;
2863 }
40fb9820 2864 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896
AM		 2865 {
2866 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2867 as_warn (_("translating to `%sp'"), i.tm.name);
2868 }
252b5132 2869
c0f3af97 2870 if (i.tm.opcode_modifier.vex)
fa99fab2 2871 build_vex_prefix (t);
c0f3af97 2872
29b0f896
AM		 2873 /* Handle conversion of 'int $3' --> special int3 insn. */
2874 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
2875 {
2876 i.tm.base_opcode = INT3_OPCODE;
2877 i.imm_operands = 0;
2878 }
252b5132 2879
40fb9820
L		 2880 if ((i.tm.opcode_modifier.jump
2881 || i.tm.opcode_modifier.jumpbyte
2882 || i.tm.opcode_modifier.jumpdword)
29b0f896
AM		 2883 && i.op[0].disps->X_op == O_constant)
2884 {
2885 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2886 the absolute address given by the constant. Since ix86 jumps and
2887 calls are pc relative, we need to generate a reloc. */
2888 i.op[0].disps->X_add_symbol = &abs_symbol;
2889 i.op[0].disps->X_op = O_symbol;
2890 }
252b5132 2891
40fb9820 2892 if (i.tm.opcode_modifier.rex64)
161a04f6 2893 i.rex |= REX_W;
252b5132 2894
29b0f896
AM		 2895 /* For 8 bit registers we need an empty rex prefix. Also if the
2896 instruction already has a prefix, we need to convert old
2897 registers to new ones. */
773f551c 2898
40fb9820 2899 if ((i.types[0].bitfield.reg8
29b0f896 2900 && (i.op[0].regs->reg_flags & RegRex64) != 0)
40fb9820 2901 || (i.types[1].bitfield.reg8
29b0f896 2902 && (i.op[1].regs->reg_flags & RegRex64) != 0)
40fb9820
L		 2903 || ((i.types[0].bitfield.reg8
2904 || i.types[1].bitfield.reg8)
29b0f896
AM		 2905 && i.rex != 0))
2906 {
2907 int x;
726c5dcd 2908
29b0f896
AM		 2909 i.rex |= REX_OPCODE;
2910 for (x = 0; x < 2; x++)
2911 {
2912 /* Look for 8 bit operand that uses old registers. */
40fb9820 2913 if (i.types[x].bitfield.reg8
29b0f896 2914 && (i.op[x].regs->reg_flags & RegRex64) == 0)
773f551c 2915 {
29b0f896
AM		 2916 /* In case it is "hi" register, give up. */
2917 if (i.op[x].regs->reg_num > 3)
a540244d 2918 as_bad (_("can't encode register '%s%s' in an "
4eed87de 2919 "instruction requiring REX prefix."),
a540244d 2920 register_prefix, i.op[x].regs->reg_name);
773f551c 2921
29b0f896
AM		 2922 /* Otherwise it is equivalent to the extended register.
2923 Since the encoding doesn't change this is merely
2924 cosmetic cleanup for debug output. */
2925
2926 i.op[x].regs = i.op[x].regs + 8;
773f551c 2927 }
29b0f896
AM		 2928 }
2929 }
773f551c 2930
85f10a01
MM		 2931 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2932 REX prefix. */
2933 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
2934 {
2935 i.drex.rex = i.rex;
2936 i.rex = 0;
2937 }
2938 else if (i.rex != 0)
29b0f896
AM		 2939 add_prefix (REX_OPCODE | i.rex);
2940
2941 /* We are ready to output the insn. */
2942 output_insn ();
2943}
2944
2945static char *
e3bb37b5 2946parse_insn (char *line, char *mnemonic)
29b0f896
AM		 2947{
2948 char *l = line;
2949 char *token_start = l;
2950 char *mnem_p;
5c6af06e
JB		 2951 int supported;
2952 const template *t;
b6169b20 2953 char *dot_p = NULL;
29b0f896
AM		 2954
2955 /* Non-zero if we found a prefix only acceptable with string insns. */
2956 const char *expecting_string_instruction = NULL;
45288df1 2957
29b0f896
AM		 2958 while (1)
2959 {
2960 mnem_p = mnemonic;
2961 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
2962 {
b6169b20
L		 2963 if (*mnem_p == '.')
2964 dot_p = mnem_p;
29b0f896
AM		 2965 mnem_p++;
2966 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
45288df1 2967 {
29b0f896
AM		 2968 as_bad (_("no such instruction: `%s'"), token_start);
2969 return NULL;
2970 }
2971 l++;
2972 }
2973 if (!is_space_char (*l)
2974 && *l != END_OF_INSN
e44823cf
JB		 2975 && (intel_syntax
2976 || (*l != PREFIX_SEPARATOR
2977 && *l != ',')))
29b0f896
AM		 2978 {
2979 as_bad (_("invalid character %s in mnemonic"),
2980 output_invalid (*l));
2981 return NULL;
2982 }
2983 if (token_start == l)
2984 {
e44823cf 2985 if (!intel_syntax && *l == PREFIX_SEPARATOR)
29b0f896
AM		 2986 as_bad (_("expecting prefix; got nothing"));
2987 else
2988 as_bad (_("expecting mnemonic; got nothing"));
2989 return NULL;
2990 }
45288df1 2991
29b0f896
AM		 2992 /* Look up instruction (or prefix) via hash table. */
2993 current_templates = hash_find (op_hash, mnemonic);
47926f60 2994
29b0f896
AM		 2995 if (*l != END_OF_INSN
2996 && (!is_space_char (*l) || l[1] != END_OF_INSN)
2997 && current_templates
40fb9820 2998 && current_templates->start->opcode_modifier.isprefix)
29b0f896 2999 {
c6fb90c8 3000 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
2dd88dca
JB		 3001 {
3002 as_bad ((flag_code != CODE_64BIT
3003 ? _("`%s' is only supported in 64-bit mode")
3004 : _("`%s' is not supported in 64-bit mode")),
3005 current_templates->start->name);
3006 return NULL;
3007 }
29b0f896
AM		 3008 /* If we are in 16-bit mode, do not allow addr16 or data16.
3009 Similarly, in 32-bit mode, do not allow addr32 or data32. */
40fb9820
L		 3010 if ((current_templates->start->opcode_modifier.size16
3011 || current_templates->start->opcode_modifier.size32)
29b0f896 3012 && flag_code != CODE_64BIT
40fb9820 3013 && (current_templates->start->opcode_modifier.size32
29b0f896
AM		 3014 ^ (flag_code == CODE_16BIT)))
3015 {
3016 as_bad (_("redundant %s prefix"),
3017 current_templates->start->name);
3018 return NULL;
45288df1 3019 }
29b0f896
AM		 3020 /* Add prefix, checking for repeated prefixes. */
3021 switch (add_prefix (current_templates->start->base_opcode))
3022 {
3023 case 0:
3024 return NULL;
3025 case 2:
3026 expecting_string_instruction = current_templates->start->name;
3027 break;
3028 }
3029 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3030 token_start = ++l;
3031 }
3032 else
3033 break;
3034 }
45288df1 3035
30a55f88 3036 if (!current_templates)
b6169b20 3037 {
30a55f88
L		 3038 /* Check if we should swap operand in encoding. */
3039 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3040 i.swap_operand = 1;
3041 else
3042 goto check_suffix;
3043 mnem_p = dot_p;
3044 *dot_p = '\0';
3045 current_templates = hash_find (op_hash, mnemonic);
b6169b20
L		 3046 }
3047
29b0f896
AM		 3048 if (!current_templates)
3049 {
b6169b20 3050check_suffix:
29b0f896
AM		 3051 /* See if we can get a match by trimming off a suffix. */
3052 switch (mnem_p[-1])
3053 {
3054 case WORD_MNEM_SUFFIX:
9306ca4a
JB		 3055 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3056 i.suffix = SHORT_MNEM_SUFFIX;
3057 else
29b0f896
AM		 3058 case BYTE_MNEM_SUFFIX:
3059 case QWORD_MNEM_SUFFIX:
3060 i.suffix = mnem_p[-1];
3061 mnem_p[-1] = '\0';
3062 current_templates = hash_find (op_hash, mnemonic);
3063 break;
3064 case SHORT_MNEM_SUFFIX:
3065 case LONG_MNEM_SUFFIX:
3066 if (!intel_syntax)
3067 {
3068 i.suffix = mnem_p[-1];
3069 mnem_p[-1] = '\0';
3070 current_templates = hash_find (op_hash, mnemonic);
3071 }
3072 break;
252b5132 3073
29b0f896
AM		 3074 /* Intel Syntax. */
3075 case 'd':
3076 if (intel_syntax)
3077 {
9306ca4a 3078 if (intel_float_operand (mnemonic) == 1)
29b0f896
AM		 3079 i.suffix = SHORT_MNEM_SUFFIX;
3080 else
3081 i.suffix = LONG_MNEM_SUFFIX;
3082 mnem_p[-1] = '\0';
3083 current_templates = hash_find (op_hash, mnemonic);
3084 }
3085 break;
3086 }
3087 if (!current_templates)
3088 {
3089 as_bad (_("no such instruction: `%s'"), token_start);
3090 return NULL;
3091 }
3092 }
252b5132 3093
40fb9820
L		 3094 if (current_templates->start->opcode_modifier.jump
3095 || current_templates->start->opcode_modifier.jumpbyte)
29b0f896
AM		 3096 {
3097 /* Check for a branch hint. We allow ",pt" and ",pn" for
3098 predict taken and predict not taken respectively.
3099 I'm not sure that branch hints actually do anything on loop
3100 and jcxz insns (JumpByte) for current Pentium4 chips. They
3101 may work in the future and it doesn't hurt to accept them
3102 now. */
3103 if (l[0] == ',' && l[1] == 'p')
3104 {
3105 if (l[2] == 't')
3106 {
3107 if (!add_prefix (DS_PREFIX_OPCODE))
3108 return NULL;
3109 l += 3;
3110 }
3111 else if (l[2] == 'n')
3112 {
3113 if (!add_prefix (CS_PREFIX_OPCODE))
3114 return NULL;
3115 l += 3;
3116 }
3117 }
3118 }
3119 /* Any other comma loses. */
3120 if (*l == ',')
3121 {
3122 as_bad (_("invalid character %s in mnemonic"),
3123 output_invalid (*l));
3124 return NULL;
3125 }
252b5132 3126
29b0f896 3127 /* Check if instruction is supported on specified architecture. */
5c6af06e
JB		 3128 supported = 0;
3129 for (t = current_templates->start; t < current_templates->end; ++t)
3130 {
c0f3af97
L		 3131 supported |= cpu_flags_match (t);
3132 if (supported == CPU_FLAGS_PERFECT_MATCH)
3629bb00 3133 goto skip;
5c6af06e 3134 }
3629bb00 3135
c0f3af97 3136 if (!(supported & CPU_FLAGS_64BIT_MATCH))
5c6af06e
JB		 3137 {
3138 as_bad (flag_code == CODE_64BIT
3139 ? _("`%s' is not supported in 64-bit mode")
3140 : _("`%s' is only supported in 64-bit mode"),
3141 current_templates->start->name);
3142 return NULL;
3143 }
c0f3af97 3144 if (supported != CPU_FLAGS_PERFECT_MATCH)
29b0f896 3145 {
3629bb00 3146 as_bad (_("`%s' is not supported on `%s%s'"),
41aacd83
L		 3147 current_templates->start->name,
3148 cpu_arch_name ? cpu_arch_name : default_arch,
3629bb00
L		 3149 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3150 return NULL;
29b0f896 3151 }
3629bb00
L		 3152
3153skip:
3154 if (!cpu_arch_flags.bitfield.cpui386
40fb9820 3155 && (flag_code != CODE_16BIT))
29b0f896
AM		 3156 {
3157 as_warn (_("use .code16 to ensure correct addressing mode"));
3158 }
252b5132 3159
29b0f896 3160 /* Check for rep/repne without a string instruction. */
f41bbced 3161 if (expecting_string_instruction)
29b0f896 3162 {
f41bbced
JB		 3163 static templates override;
3164
3165 for (t = current_templates->start; t < current_templates->end; ++t)
40fb9820 3166 if (t->opcode_modifier.isstring)
f41bbced
JB		 3167 break;
3168 if (t >= current_templates->end)
3169 {
3170 as_bad (_("expecting string instruction after `%s'"),
64e74474 3171 expecting_string_instruction);
f41bbced
JB		 3172 return NULL;
3173 }
3174 for (override.start = t; t < current_templates->end; ++t)
40fb9820 3175 if (!t->opcode_modifier.isstring)
f41bbced
JB		 3176 break;
3177 override.end = t;
3178 current_templates = &override;
29b0f896 3179 }
252b5132 3180
29b0f896
AM		 3181 return l;
3182}
252b5132 3183
29b0f896 3184static char *
e3bb37b5 3185parse_operands (char *l, const char *mnemonic)
29b0f896
AM		 3186{
3187 char *token_start;
3138f287 3188
29b0f896
AM		 3189 /* 1 if operand is pending after ','. */
3190 unsigned int expecting_operand = 0;
252b5132 3191
29b0f896
AM		 3192 /* Non-zero if operand parens not balanced. */
3193 unsigned int paren_not_balanced;
3194
3195 while (*l != END_OF_INSN)
3196 {
3197 /* Skip optional white space before operand. */
3198 if (is_space_char (*l))
3199 ++l;
3200 if (!is_operand_char (*l) && *l != END_OF_INSN)
3201 {
3202 as_bad (_("invalid character %s before operand %d"),
3203 output_invalid (*l),
3204 i.operands + 1);
3205 return NULL;
3206 }
3207 token_start = l; /* after white space */
3208 paren_not_balanced = 0;
3209 while (paren_not_balanced || *l != ',')
3210 {
3211 if (*l == END_OF_INSN)
3212 {
3213 if (paren_not_balanced)
3214 {
3215 if (!intel_syntax)
3216 as_bad (_("unbalanced parenthesis in operand %d."),
3217 i.operands + 1);
3218 else
3219 as_bad (_("unbalanced brackets in operand %d."),
3220 i.operands + 1);
3221 return NULL;
3222 }
3223 else
3224 break; /* we are done */
3225 }
3226 else if (!is_operand_char (*l) && !is_space_char (*l))
3227 {
3228 as_bad (_("invalid character %s in operand %d"),
3229 output_invalid (*l),
3230 i.operands + 1);
3231 return NULL;
3232 }
3233 if (!intel_syntax)
3234 {
3235 if (*l == '(')
3236 ++paren_not_balanced;
3237 if (*l == ')')
3238 --paren_not_balanced;
3239 }
3240 else
3241 {
3242 if (*l == '[')
3243 ++paren_not_balanced;
3244 if (*l == ']')
3245 --paren_not_balanced;
3246 }
3247 l++;
3248 }
3249 if (l != token_start)
3250 { /* Yes, we've read in another operand. */
3251 unsigned int operand_ok;
3252 this_operand = i.operands++;
7d5e4556 3253 i.types[this_operand].bitfield.unspecified = 1;
29b0f896
AM		 3254 if (i.operands > MAX_OPERANDS)
3255 {
3256 as_bad (_("spurious operands; (%d operands/instruction max)"),
3257 MAX_OPERANDS);
3258 return NULL;
3259 }
3260 /* Now parse operand adding info to 'i' as we go along. */
3261 END_STRING_AND_SAVE (l);
3262
3263 if (intel_syntax)
3264 operand_ok =
3265 i386_intel_operand (token_start,
3266 intel_float_operand (mnemonic));
3267 else
a7619375 3268 operand_ok = i386_att_operand (token_start);
29b0f896
AM		 3269
3270 RESTORE_END_STRING (l);
3271 if (!operand_ok)
3272 return NULL;
3273 }
3274 else
3275 {
3276 if (expecting_operand)
3277 {
3278 expecting_operand_after_comma:
3279 as_bad (_("expecting operand after ','; got nothing"));
3280 return NULL;
3281 }
3282 if (*l == ',')
3283 {
3284 as_bad (_("expecting operand before ','; got nothing"));
3285 return NULL;
3286 }
3287 }
7f3f1ea2 3288
29b0f896
AM		 3289 /* Now *l must be either ',' or END_OF_INSN. */
3290 if (*l == ',')
3291 {
3292 if (*++l == END_OF_INSN)
3293 {
3294 /* Just skip it, if it's \n complain. */
3295 goto expecting_operand_after_comma;
3296 }
3297 expecting_operand = 1;
3298 }
3299 }
3300 return l;
3301}
7f3f1ea2 3302
050dfa73 3303static void
4d456e3d 3304swap_2_operands (int xchg1, int xchg2)
050dfa73
MM		 3305{
3306 union i386_op temp_op;
40fb9820 3307 i386_operand_type temp_type;
050dfa73 3308 enum bfd_reloc_code_real temp_reloc;
4eed87de 3309
050dfa73
MM		 3310 temp_type = i.types[xchg2];
3311 i.types[xchg2] = i.types[xchg1];
3312 i.types[xchg1] = temp_type;
3313 temp_op = i.op[xchg2];
3314 i.op[xchg2] = i.op[xchg1];
3315 i.op[xchg1] = temp_op;
3316 temp_reloc = i.reloc[xchg2];
3317 i.reloc[xchg2] = i.reloc[xchg1];
3318 i.reloc[xchg1] = temp_reloc;
3319}
3320
29b0f896 3321static void
e3bb37b5 3322swap_operands (void)
29b0f896 3323{
b7c61d9a 3324 switch (i.operands)
050dfa73 3325 {
c0f3af97 3326 case 5:
b7c61d9a 3327 case 4:
4d456e3d 3328 swap_2_operands (1, i.operands - 2);
b7c61d9a
L		 3329 case 3:
3330 case 2:
4d456e3d 3331 swap_2_operands (0, i.operands - 1);
b7c61d9a
L		 3332 break;
3333 default:
3334 abort ();
29b0f896 3335 }
29b0f896
AM		 3336
3337 if (i.mem_operands == 2)
3338 {
3339 const seg_entry *temp_seg;
3340 temp_seg = i.seg[0];
3341 i.seg[0] = i.seg[1];
3342 i.seg[1] = temp_seg;
3343 }
3344}
252b5132 3345
29b0f896
AM		 3346/* Try to ensure constant immediates are represented in the smallest
3347 opcode possible. */
3348static void
e3bb37b5 3349optimize_imm (void)
29b0f896
AM		 3350{
3351 char guess_suffix = 0;
3352 int op;
252b5132 3353
29b0f896
AM		 3354 if (i.suffix)
3355 guess_suffix = i.suffix;
3356 else if (i.reg_operands)
3357 {
3358 /* Figure out a suffix from the last register operand specified.
3359 We can't do this properly yet, ie. excluding InOutPortReg,
3360 but the following works for instructions with immediates.
3361 In any case, we can't set i.suffix yet. */
3362 for (op = i.operands; --op >= 0;)
40fb9820
L		 3363 if (i.types[op].bitfield.reg8)
3364 {
3365 guess_suffix = BYTE_MNEM_SUFFIX;
3366 break;
3367 }
3368 else if (i.types[op].bitfield.reg16)
252b5132 3369 {
40fb9820
L		 3370 guess_suffix = WORD_MNEM_SUFFIX;
3371 break;
3372 }
3373 else if (i.types[op].bitfield.reg32)
3374 {
3375 guess_suffix = LONG_MNEM_SUFFIX;
3376 break;
3377 }
3378 else if (i.types[op].bitfield.reg64)
3379 {
3380 guess_suffix = QWORD_MNEM_SUFFIX;
29b0f896 3381 break;
252b5132 3382 }
29b0f896
AM		 3383 }
3384 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3385 guess_suffix = WORD_MNEM_SUFFIX;
3386
3387 for (op = i.operands; --op >= 0;)
40fb9820 3388 if (operand_type_check (i.types[op], imm))
29b0f896
AM		 3389 {
3390 switch (i.op[op].imms->X_op)
252b5132 3391 {
29b0f896
AM		 3392 case O_constant:
3393 /* If a suffix is given, this operand may be shortened. */
3394 switch (guess_suffix)
252b5132 3395 {
29b0f896 3396 case LONG_MNEM_SUFFIX:
40fb9820
L		 3397 i.types[op].bitfield.imm32 = 1;
3398 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3399 break;
3400 case WORD_MNEM_SUFFIX:
40fb9820
L		 3401 i.types[op].bitfield.imm16 = 1;
3402 i.types[op].bitfield.imm32 = 1;
3403 i.types[op].bitfield.imm32s = 1;
3404 i.types[op].bitfield.imm64 = 1;
29b0f896
AM		 3405 break;
3406 case BYTE_MNEM_SUFFIX:
40fb9820
L		 3407 i.types[op].bitfield.imm8 = 1;
3408 i.types[op].bitfield.imm8s = 1;
3409 i.types[op].bitfield.imm16 = 1;
3410 i.types[op].bitfield.imm32 = 1;
3411 i.types[op].bitfield.imm32s = 1;
3412 i.types[op].bitfield.imm64 = 1;
29b0f896 3413 break;
252b5132 3414 }
252b5132 3415
29b0f896
AM		 3416 /* If this operand is at most 16 bits, convert it
3417 to a signed 16 bit number before trying to see
3418 whether it will fit in an even smaller size.
3419 This allows a 16-bit operand such as $0xffe0 to
3420 be recognised as within Imm8S range. */
40fb9820 3421 if ((i.types[op].bitfield.imm16)
29b0f896 3422 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
252b5132 3423 {
29b0f896
AM		 3424 i.op[op].imms->X_add_number =
3425 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3426 }
40fb9820 3427 if ((i.types[op].bitfield.imm32)
29b0f896
AM		 3428 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3429 == 0))
3430 {
3431 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3432 ^ ((offsetT) 1 << 31))
3433 - ((offsetT) 1 << 31));
3434 }
40fb9820 3435 i.types[op]
c6fb90c8
L		 3436 = operand_type_or (i.types[op],
3437 smallest_imm_type (i.op[op].imms->X_add_number));
252b5132 3438
29b0f896
AM		 3439 /* We must avoid matching of Imm32 templates when 64bit
3440 only immediate is available. */
3441 if (guess_suffix == QWORD_MNEM_SUFFIX)
40fb9820 3442 i.types[op].bitfield.imm32 = 0;
29b0f896 3443 break;
252b5132 3444
29b0f896
AM		 3445 case O_absent:
3446 case O_register:
3447 abort ();
3448
3449 /* Symbols and expressions. */
3450 default:
9cd96992
JB		 3451 /* Convert symbolic operand to proper sizes for matching, but don't
3452 prevent matching a set of insns that only supports sizes other
3453 than those matching the insn suffix. */
3454 {
40fb9820 3455 i386_operand_type mask, allowed;
9cd96992
JB		 3456 const template *t;
3457
0dfbf9d7
L		 3458 operand_type_set (&mask, 0);
3459 operand_type_set (&allowed, 0);
40fb9820 3460
4eed87de
AM		 3461 for (t = current_templates->start;
3462 t < current_templates->end;
3463 ++t)
c6fb90c8
L		 3464 allowed = operand_type_or (allowed,
3465 t->operand_types[op]);
9cd96992
JB		 3466 switch (guess_suffix)
3467 {
3468 case QWORD_MNEM_SUFFIX:
40fb9820
L		 3469 mask.bitfield.imm64 = 1;
3470 mask.bitfield.imm32s = 1;
9cd96992
JB		 3471 break;
3472 case LONG_MNEM_SUFFIX:
40fb9820 3473 mask.bitfield.imm32 = 1;
9cd96992
JB		 3474 break;
3475 case WORD_MNEM_SUFFIX:
40fb9820 3476 mask.bitfield.imm16 = 1;
9cd96992
JB		 3477 break;
3478 case BYTE_MNEM_SUFFIX:
40fb9820 3479 mask.bitfield.imm8 = 1;
9cd96992
JB		 3480 break;
3481 default:
9cd96992
JB		 3482 break;
3483 }
c6fb90c8 3484 allowed = operand_type_and (mask, allowed);
0dfbf9d7 3485 if (!operand_type_all_zero (&allowed))
c6fb90c8 3486 i.types[op] = operand_type_and (i.types[op], mask);
9cd96992 3487 }
29b0f896 3488 break;
252b5132 3489 }
29b0f896
AM		 3490 }
3491}
47926f60 3492
29b0f896
AM		 3493/* Try to use the smallest displacement type too. */
3494static void
e3bb37b5 3495optimize_disp (void)
29b0f896
AM		 3496{
3497 int op;
3e73aa7c 3498
29b0f896 3499 for (op = i.operands; --op >= 0;)
40fb9820 3500 if (operand_type_check (i.types[op], disp))
252b5132 3501 {
b300c311 3502 if (i.op[op].disps->X_op == O_constant)
252b5132 3503 {
b300c311 3504 offsetT disp = i.op[op].disps->X_add_number;
29b0f896 3505
40fb9820 3506 if (i.types[op].bitfield.disp16
b300c311
L		 3507 && (disp & ~(offsetT) 0xffff) == 0)
3508 {
3509 /* If this operand is at most 16 bits, convert
3510 to a signed 16 bit number and don't use 64bit
3511 displacement. */
3512 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
40fb9820 3513 i.types[op].bitfield.disp64 = 0;
b300c311 3514 }
40fb9820 3515 if (i.types[op].bitfield.disp32
b300c311
L		 3516 && (disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3517 {
3518 /* If this operand is at most 32 bits, convert
3519 to a signed 32 bit number and don't use 64bit
3520 displacement. */
3521 disp &= (((offsetT) 2 << 31) - 1);
3522 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
40fb9820 3523 i.types[op].bitfield.disp64 = 0;
b300c311 3524 }
40fb9820 3525 if (!disp && i.types[op].bitfield.baseindex)
b300c311 3526 {
40fb9820
L		 3527 i.types[op].bitfield.disp8 = 0;
3528 i.types[op].bitfield.disp16 = 0;
3529 i.types[op].bitfield.disp32 = 0;
3530 i.types[op].bitfield.disp32s = 0;
3531 i.types[op].bitfield.disp64 = 0;
b300c311
L		 3532 i.op[op].disps = 0;
3533 i.disp_operands--;
3534 }
3535 else if (flag_code == CODE_64BIT)
3536 {
3537 if (fits_in_signed_long (disp))
28a9d8f5 3538 {
40fb9820
L		 3539 i.types[op].bitfield.disp64 = 0;
3540 i.types[op].bitfield.disp32s = 1;
28a9d8f5 3541 }
b300c311 3542 if (fits_in_unsigned_long (disp))
40fb9820 3543 i.types[op].bitfield.disp32 = 1;
b300c311 3544 }
40fb9820
L		 3545 if ((i.types[op].bitfield.disp32
3546 || i.types[op].bitfield.disp32s
3547 || i.types[op].bitfield.disp16)
b300c311 3548 && fits_in_signed_byte (disp))
40fb9820 3549 i.types[op].bitfield.disp8 = 1;
252b5132 3550 }
67a4f2b7
AO		 3551 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3552 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3553 {
3554 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3555 i.op[op].disps, 0, i.reloc[op]);
40fb9820
L		 3556 i.types[op].bitfield.disp8 = 0;
3557 i.types[op].bitfield.disp16 = 0;
3558 i.types[op].bitfield.disp32 = 0;
3559 i.types[op].bitfield.disp32s = 0;
3560 i.types[op].bitfield.disp64 = 0;
67a4f2b7
AO		 3561 }
3562 else
b300c311 3563 /* We only support 64bit displacement on constants. */
40fb9820 3564 i.types[op].bitfield.disp64 = 0;
252b5132 3565 }
29b0f896
AM		 3566}
3567
fa99fab2 3568static const template *
e3bb37b5 3569match_template (void)
29b0f896
AM		 3570{
3571 /* Points to template once we've found it. */
3572 const template *t;
40fb9820 3573 i386_operand_type overlap0, overlap1, overlap2, overlap3;
c0f3af97 3574 i386_operand_type overlap4;
29b0f896 3575 unsigned int found_reverse_match;
40fb9820
L		 3576 i386_opcode_modifier suffix_check;
3577 i386_operand_type operand_types [MAX_OPERANDS];
539e75ad 3578 int addr_prefix_disp;
a5c311ca 3579 unsigned int j;
3629bb00 3580 unsigned int found_cpu_match;
45664ddb 3581 unsigned int check_register;
29b0f896 3582
c0f3af97
L		 3583#if MAX_OPERANDS != 5
3584# error "MAX_OPERANDS must be 5."
f48ff2ae
L		 3585#endif
3586
29b0f896 3587 found_reverse_match = 0;
539e75ad 3588 addr_prefix_disp = -1;
40fb9820
L		 3589
3590 memset (&suffix_check, 0, sizeof (suffix_check));
3591 if (i.suffix == BYTE_MNEM_SUFFIX)
3592 suffix_check.no_bsuf = 1;
3593 else if (i.suffix == WORD_MNEM_SUFFIX)
3594 suffix_check.no_wsuf = 1;
3595 else if (i.suffix == SHORT_MNEM_SUFFIX)
3596 suffix_check.no_ssuf = 1;
3597 else if (i.suffix == LONG_MNEM_SUFFIX)
3598 suffix_check.no_lsuf = 1;
3599 else if (i.suffix == QWORD_MNEM_SUFFIX)
3600 suffix_check.no_qsuf = 1;
3601 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
7ce189b3 3602 suffix_check.no_ldsuf = 1;
29b0f896 3603
45aa61fe 3604 for (t = current_templates->start; t < current_templates->end; t++)
29b0f896 3605 {
539e75ad
L		 3606 addr_prefix_disp = -1;
3607
29b0f896
AM		 3608 /* Must have right number of operands. */
3609 if (i.operands != t->operands)
3610 continue;
3611
50aecf8c 3612 /* Check processor support. */
c0f3af97
L		 3613 found_cpu_match = (cpu_flags_match (t)
3614 == CPU_FLAGS_PERFECT_MATCH);
50aecf8c
L		 3615 if (!found_cpu_match)
3616 continue;
3617
e1d4d893
L		 3618 /* Check old gcc support. */
3619 if (!old_gcc && t->opcode_modifier.oldgcc)
3620 continue;
3621
3622 /* Check AT&T mnemonic. */
3623 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
1efbbeb4
L		 3624 continue;
3625
5c07affc
L		 3626 /* Check AT&T syntax Intel syntax. */
3627 if ((intel_syntax && t->opcode_modifier.attsyntax)
3628 || (!intel_syntax && t->opcode_modifier.intelsyntax))
1efbbeb4
L		 3629 continue;
3630
20592a94 3631 /* Check the suffix, except for some instructions in intel mode. */
567e4e96
L		 3632 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
3633 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
3634 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
3635 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
3636 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
3637 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
3638 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
29b0f896
AM		 3639 continue;
3640
5c07affc 3641 if (!operand_size_match (t))
7d5e4556 3642 continue;
539e75ad 3643
5c07affc
L		 3644 for (j = 0; j < MAX_OPERANDS; j++)
3645 operand_types[j] = t->operand_types[j];
3646
45aa61fe
AM		 3647 /* In general, don't allow 64-bit operands in 32-bit mode. */
3648 if (i.suffix == QWORD_MNEM_SUFFIX
3649 && flag_code != CODE_64BIT
3650 && (intel_syntax
40fb9820 3651 ? (!t->opcode_modifier.ignoresize
45aa61fe
AM		 3652 && !intel_float_operand (t->name))
3653 : intel_float_operand (t->name) != 2)
40fb9820 3654 && ((!operand_types[0].bitfield.regmmx
c0f3af97
L		 3655 && !operand_types[0].bitfield.regxmm
3656 && !operand_types[0].bitfield.regymm)
40fb9820 3657 || (!operand_types[t->operands > 1].bitfield.regmmx
c0f3af97
L		 3658 && !!operand_types[t->operands > 1].bitfield.regxmm
3659 && !!operand_types[t->operands > 1].bitfield.regymm))
45aa61fe
AM		 3660 && (t->base_opcode != 0x0fc7
3661 || t->extension_opcode != 1 /* cmpxchg8b */))
3662 continue;
3663
192dc9c6
JB		 3664 /* In general, don't allow 32-bit operands on pre-386. */
3665 else if (i.suffix == LONG_MNEM_SUFFIX
3666 && !cpu_arch_flags.bitfield.cpui386
3667 && (intel_syntax
3668 ? (!t->opcode_modifier.ignoresize
3669 && !intel_float_operand (t->name))
3670 : intel_float_operand (t->name) != 2)
3671 && ((!operand_types[0].bitfield.regmmx
3672 && !operand_types[0].bitfield.regxmm)
3673 || (!operand_types[t->operands > 1].bitfield.regmmx
3674 && !!operand_types[t->operands > 1].bitfield.regxmm)))
3675 continue;
3676
29b0f896 3677 /* Do not verify operands when there are none. */
50aecf8c 3678 else
29b0f896 3679 {
c6fb90c8 3680 if (!t->operands)
2dbab7d5
L		 3681 /* We've found a match; break out of loop. */
3682 break;
29b0f896 3683 }
252b5132 3684
539e75ad
L		 3685 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3686 into Disp32/Disp16/Disp32 operand. */
3687 if (i.prefix[ADDR_PREFIX] != 0)
3688 {
40fb9820 3689 /* There should be only one Disp operand. */
539e75ad
L		 3690 switch (flag_code)
3691 {
3692 case CODE_16BIT:
40fb9820
L		 3693 for (j = 0; j < MAX_OPERANDS; j++)
3694 {
3695 if (operand_types[j].bitfield.disp16)
3696 {
3697 addr_prefix_disp = j;
3698 operand_types[j].bitfield.disp32 = 1;
3699 operand_types[j].bitfield.disp16 = 0;
3700 break;
3701 }
3702 }
539e75ad
L		 3703 break;
3704 case CODE_32BIT:
40fb9820
L		 3705 for (j = 0; j < MAX_OPERANDS; j++)
3706 {
3707 if (operand_types[j].bitfield.disp32)
3708 {
3709 addr_prefix_disp = j;
3710 operand_types[j].bitfield.disp32 = 0;
3711 operand_types[j].bitfield.disp16 = 1;
3712 break;
3713 }
3714 }
539e75ad
L		 3715 break;
3716 case CODE_64BIT:
40fb9820
L		 3717 for (j = 0; j < MAX_OPERANDS; j++)
3718 {
3719 if (operand_types[j].bitfield.disp64)
3720 {
3721 addr_prefix_disp = j;
3722 operand_types[j].bitfield.disp64 = 0;
3723 operand_types[j].bitfield.disp32 = 1;
3724 break;
3725 }
3726 }
539e75ad
L		 3727 break;
3728 }
539e75ad
L		 3729 }
3730
45664ddb
L		 3731 /* We check register size only if size of operands can be
3732 encoded the canonical way. */
3733 check_register = t->opcode_modifier.w;
c6fb90c8 3734 overlap0 = operand_type_and (i.types[0], operand_types[0]);
29b0f896
AM		 3735 switch (t->operands)
3736 {
3737 case 1:
40fb9820 3738 if (!operand_type_match (overlap0, i.types[0]))
29b0f896
AM		 3739 continue;
3740 break;
3741 case 2:
8b38ad71
L		 3742 /* xchg %eax, %eax is a special case. It is an aliase for nop
3743 only in 32bit mode and we can use opcode 0x90. In 64bit
3744 mode, we can't use 0x90 for xchg %eax, %eax since it should
3745 zero-extend %eax to %rax. */
3746 if (flag_code == CODE_64BIT
3747 && t->base_opcode == 0x90
0dfbf9d7
L		 3748 && operand_type_equal (&i.types [0], &acc32)
3749 && operand_type_equal (&i.types [1], &acc32))
8b38ad71 3750 continue;
b6169b20
L		 3751 if (i.swap_operand)
3752 {
3753 /* If we swap operand in encoding, we either match
3754 the next one or reverse direction of operands. */
3755 if (t->opcode_modifier.s)
3756 continue;
3757 else if (t->opcode_modifier.d)
3758 goto check_reverse;
3759 }
3760
29b0f896 3761 case 3:
fa99fab2
L		 3762 /* If we swap operand in encoding, we match the next one. */
3763 if (i.swap_operand && t->opcode_modifier.s)
3764 continue;
f48ff2ae 3765 case 4:
c0f3af97 3766 case 5:
c6fb90c8 3767 overlap1 = operand_type_and (i.types[1], operand_types[1]);
40fb9820
L		 3768 if (!operand_type_match (overlap0, i.types[0])
3769 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3770 || (check_register
3771 && !operand_type_register_match (overlap0, i.types[0],
40fb9820
L		 3772 operand_types[0],
3773 overlap1, i.types[1],
3774 operand_types[1])))
29b0f896
AM		 3775 {
3776 /* Check if other direction is valid ... */
40fb9820 3777 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
29b0f896
AM		 3778 continue;
3779
b6169b20 3780check_reverse:
29b0f896 3781 /* Try reversing direction of operands. */
c6fb90c8
L		 3782 overlap0 = operand_type_and (i.types[0], operand_types[1]);
3783 overlap1 = operand_type_and (i.types[1], operand_types[0]);
40fb9820
L		 3784 if (!operand_type_match (overlap0, i.types[0])
3785 || !operand_type_match (overlap1, i.types[1])
45664ddb
L		 3786 || (check_register
3787 && !operand_type_register_match (overlap0,
3788 i.types[0],
3789 operand_types[1],
3790 overlap1,
3791 i.types[1],
3792 operand_types[0])))
29b0f896
AM		 3793 {
3794 /* Does not match either direction. */
3795 continue;
3796 }
3797 /* found_reverse_match holds which of D or FloatDR
3798 we've found. */
40fb9820 3799 if (t->opcode_modifier.d)
8a2ed489 3800 found_reverse_match = Opcode_D;
40fb9820 3801 else if (t->opcode_modifier.floatd)
8a2ed489
L		 3802 found_reverse_match = Opcode_FloatD;
3803 else
3804 found_reverse_match = 0;
40fb9820 3805 if (t->opcode_modifier.floatr)
8a2ed489 3806 found_reverse_match |= Opcode_FloatR;
29b0f896 3807 }
f48ff2ae 3808 else
29b0f896 3809 {
f48ff2ae 3810 /* Found a forward 2 operand match here. */
d1cbb4db
L		 3811 switch (t->operands)
3812 {
c0f3af97
L		 3813 case 5:
3814 overlap4 = operand_type_and (i.types[4],
3815 operand_types[4]);
d1cbb4db 3816 case 4:
c6fb90c8
L		 3817 overlap3 = operand_type_and (i.types[3],
3818 operand_types[3]);
d1cbb4db 3819 case 3:
c6fb90c8
L		 3820 overlap2 = operand_type_and (i.types[2],
3821 operand_types[2]);
d1cbb4db
L		 3822 break;
3823 }
29b0f896 3824
f48ff2ae
L		 3825 switch (t->operands)
3826 {
c0f3af97
L		 3827 case 5:
3828 if (!operand_type_match (overlap4, i.types[4])
3829 || !operand_type_register_match (overlap3,
3830 i.types[3],
3831 operand_types[3],
3832 overlap4,
3833 i.types[4],
3834 operand_types[4]))
3835 continue;
f48ff2ae 3836 case 4:
40fb9820 3837 if (!operand_type_match (overlap3, i.types[3])
45664ddb
L		 3838 || (check_register
3839 && !operand_type_register_match (overlap2,
3840 i.types[2],
3841 operand_types[2],
3842 overlap3,
3843 i.types[3],
3844 operand_types[3])))
f48ff2ae
L		 3845 continue;
3846 case 3:
3847 /* Here we make use of the fact that there are no
3848 reverse match 3 operand instructions, and all 3
3849 operand instructions only need to be checked for
3850 register consistency between operands 2 and 3. */
40fb9820 3851 if (!operand_type_match (overlap2, i.types[2])
45664ddb
L		 3852 || (check_register
3853 && !operand_type_register_match (overlap1,
3854 i.types[1],
3855 operand_types[1],
3856 overlap2,
3857 i.types[2],
3858 operand_types[2])))
f48ff2ae
L		 3859 continue;
3860 break;
3861 }
29b0f896 3862 }
f48ff2ae 3863 /* Found either forward/reverse 2, 3 or 4 operand match here:
29b0f896
AM		 3864 slip through to break. */
3865 }
3629bb00 3866 if (!found_cpu_match)
29b0f896
AM		 3867 {
3868 found_reverse_match = 0;
3869 continue;
3870 }
c0f3af97 3871
29b0f896
AM		 3872 /* We've found a match; break out of loop. */
3873 break;
3874 }
3875
3876 if (t == current_templates->end)
3877 {
3878 /* We found no match. */
95f283e8
L		 3879 if (intel_syntax)
3880 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3881 current_templates->start->name);
3882 else
3883 as_bad (_("suffix or operands invalid for `%s'"),
3884 current_templates->start->name);
fa99fab2 3885 return NULL;
29b0f896 3886 }
252b5132 3887
29b0f896
AM		 3888 if (!quiet_warnings)
3889 {
3890 if (!intel_syntax
40fb9820
L		 3891 && (i.types[0].bitfield.jumpabsolute
3892 != operand_types[0].bitfield.jumpabsolute))
29b0f896
AM		 3893 {
3894 as_warn (_("indirect %s without `*'"), t->name);
3895 }
3896
40fb9820
L		 3897 if (t->opcode_modifier.isprefix
3898 && t->opcode_modifier.ignoresize)
29b0f896
AM		 3899 {
3900 /* Warn them that a data or address size prefix doesn't
3901 affect assembly of the next line of code. */
3902 as_warn (_("stand-alone `%s' prefix"), t->name);
3903 }
3904 }
3905
3906 /* Copy the template we found. */
3907 i.tm = *t;
539e75ad
L		 3908
3909 if (addr_prefix_disp != -1)
3910 i.tm.operand_types[addr_prefix_disp]
3911 = operand_types[addr_prefix_disp];
3912
29b0f896
AM		 3913 if (found_reverse_match)
3914 {
3915 /* If we found a reverse match we must alter the opcode
3916 direction bit. found_reverse_match holds bits to change
3917 (different for int & float insns). */
3918
3919 i.tm.base_opcode ^= found_reverse_match;
3920
539e75ad
L		 3921 i.tm.operand_types[0] = operand_types[1];
3922 i.tm.operand_types[1] = operand_types[0];
29b0f896
AM		 3923 }
3924
fa99fab2 3925 return t;
29b0f896
AM		 3926}
3927
3928static int
e3bb37b5 3929check_string (void)
29b0f896 3930{
40fb9820
L		 3931 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
3932 if (i.tm.operand_types[mem_op].bitfield.esseg)
29b0f896
AM		 3933 {
3934 if (i.seg[0] != NULL && i.seg[0] != &es)
3935 {
a87af027 3936 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3937 i.tm.name,
a87af027
JB		 3938 mem_op + 1,
3939 register_prefix);
29b0f896
AM		 3940 return 0;
3941 }
3942 /* There's only ever one segment override allowed per instruction.
3943 This instruction possibly has a legal segment override on the
3944 second operand, so copy the segment to where non-string
3945 instructions store it, allowing common code. */
3946 i.seg[0] = i.seg[1];
3947 }
40fb9820 3948 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
29b0f896
AM		 3949 {
3950 if (i.seg[1] != NULL && i.seg[1] != &es)
3951 {
a87af027 3952 as_bad (_("`%s' operand %d must use `%ses' segment"),
29b0f896 3953 i.tm.name,
a87af027
JB		 3954 mem_op + 2,
3955 register_prefix);
29b0f896
AM		 3956 return 0;
3957 }
3958 }
3959 return 1;
3960}
3961
3962static int
543613e9 3963process_suffix (void)
29b0f896
AM		 3964{
3965 /* If matched instruction specifies an explicit instruction mnemonic
3966 suffix, use it. */
40fb9820
L		 3967 if (i.tm.opcode_modifier.size16)
3968 i.suffix = WORD_MNEM_SUFFIX;
3969 else if (i.tm.opcode_modifier.size32)
3970 i.suffix = LONG_MNEM_SUFFIX;
3971 else if (i.tm.opcode_modifier.size64)
3972 i.suffix = QWORD_MNEM_SUFFIX;
29b0f896
AM		 3973 else if (i.reg_operands)
3974 {
3975 /* If there's no instruction mnemonic suffix we try to invent one
3976 based on register operands. */
3977 if (!i.suffix)
3978 {
3979 /* We take i.suffix from the last register operand specified,
3980 Destination register type is more significant than source
381d071f
L		 3981 register type. crc32 in SSE4.2 prefers source register
3982 type. */
3983 if (i.tm.base_opcode == 0xf20f38f1)
3984 {
40fb9820
L		 3985 if (i.types[0].bitfield.reg16)
3986 i.suffix = WORD_MNEM_SUFFIX;
3987 else if (i.types[0].bitfield.reg32)
3988 i.suffix = LONG_MNEM_SUFFIX;
3989 else if (i.types[0].bitfield.reg64)
3990 i.suffix = QWORD_MNEM_SUFFIX;
381d071f 3991 }
9344ff29 3992 else if (i.tm.base_opcode == 0xf20f38f0)
20592a94 3993 {
40fb9820 3994 if (i.types[0].bitfield.reg8)
20592a94
L		 3995 i.suffix = BYTE_MNEM_SUFFIX;
3996 }
381d071f
L		 3997
3998 if (!i.suffix)
3999 {
4000 int op;
4001
20592a94
L		 4002 if (i.tm.base_opcode == 0xf20f38f1
4003 || i.tm.base_opcode == 0xf20f38f0)
4004 {
4005 /* We have to know the operand size for crc32. */
4006 as_bad (_("ambiguous memory operand size for `%s`"),
4007 i.tm.name);
4008 return 0;
4009 }
4010
381d071f 4011 for (op = i.operands; --op >= 0;)
40fb9820 4012 if (!i.tm.operand_types[op].bitfield.inoutportreg)
381d071f 4013 {
40fb9820
L		 4014 if (i.types[op].bitfield.reg8)
4015 {
4016 i.suffix = BYTE_MNEM_SUFFIX;
4017 break;
4018 }
4019 else if (i.types[op].bitfield.reg16)
4020 {
4021 i.suffix = WORD_MNEM_SUFFIX;
4022 break;
4023 }
4024 else if (i.types[op].bitfield.reg32)
4025 {
4026 i.suffix = LONG_MNEM_SUFFIX;
4027 break;
4028 }
4029 else if (i.types[op].bitfield.reg64)
4030 {
4031 i.suffix = QWORD_MNEM_SUFFIX;
4032 break;
4033 }
381d071f
L		 4034 }
4035 }
29b0f896
AM		 4036 }
4037 else if (i.suffix == BYTE_MNEM_SUFFIX)
4038 {
4039 if (!check_byte_reg ())
4040 return 0;
4041 }
4042 else if (i.suffix == LONG_MNEM_SUFFIX)
4043 {
4044 if (!check_long_reg ())
4045 return 0;
4046 }
4047 else if (i.suffix == QWORD_MNEM_SUFFIX)
4048 {
955e1e6a
L		 4049 if (intel_syntax
4050 && i.tm.opcode_modifier.ignoresize
4051 && i.tm.opcode_modifier.no_qsuf)
4052 i.suffix = 0;
4053 else if (!check_qword_reg ())
29b0f896
AM		 4054 return 0;
4055 }
4056 else if (i.suffix == WORD_MNEM_SUFFIX)
4057 {
4058 if (!check_word_reg ())
4059 return 0;
4060 }
c0f3af97
L		 4061 else if (i.suffix == XMMWORD_MNEM_SUFFIX
4062 || i.suffix == YMMWORD_MNEM_SUFFIX)
582d5edd 4063 {
c0f3af97 4064 /* Skip if the instruction has x/y suffix. match_template
582d5edd
L		 4065 should check if it is a valid suffix. */
4066 }
40fb9820 4067 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
29b0f896
AM		 4068 /* Do nothing if the instruction is going to ignore the prefix. */
4069 ;
4070 else
4071 abort ();
4072 }
40fb9820 4073 else if (i.tm.opcode_modifier.defaultsize
9306ca4a
JB		 4074 && !i.suffix
4075 /* exclude fldenv/frstor/fsave/fstenv */
40fb9820 4076 && i.tm.opcode_modifier.no_ssuf)
29b0f896
AM		 4077 {
4078 i.suffix = stackop_size;
4079 }
9306ca4a
JB		 4080 else if (intel_syntax
4081 && !i.suffix
40fb9820
L		 4082 && (i.tm.operand_types[0].bitfield.jumpabsolute
4083 || i.tm.opcode_modifier.jumpbyte
4084 || i.tm.opcode_modifier.jumpintersegment
64e74474
AM		 4085 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
4086 && i.tm.extension_opcode <= 3)))
9306ca4a
JB		 4087 {
4088 switch (flag_code)
4089 {
4090 case CODE_64BIT:
40fb9820 4091 if (!i.tm.opcode_modifier.no_qsuf)
9306ca4a
JB		 4092 {
4093 i.suffix = QWORD_MNEM_SUFFIX;
4094 break;
4095 }
4096 case CODE_32BIT:
40fb9820 4097 if (!i.tm.opcode_modifier.no_lsuf)
9306ca4a
JB		 4098 i.suffix = LONG_MNEM_SUFFIX;
4099 break;
4100 case CODE_16BIT:
40fb9820 4101 if (!i.tm.opcode_modifier.no_wsuf)
9306ca4a
JB		 4102 i.suffix = WORD_MNEM_SUFFIX;
4103 break;
4104 }
4105 }
252b5132 4106
9306ca4a 4107 if (!i.suffix)
29b0f896 4108 {
9306ca4a
JB		 4109 if (!intel_syntax)
4110 {
40fb9820 4111 if (i.tm.opcode_modifier.w)
9306ca4a 4112 {
4eed87de
AM		 4113 as_bad (_("no instruction mnemonic suffix given and "
4114 "no register operands; can't size instruction"));
9306ca4a
JB		 4115 return 0;
4116 }
4117 }
4118 else
4119 {
40fb9820
L		 4120 unsigned int suffixes;
4121
4122 suffixes = !i.tm.opcode_modifier.no_bsuf;
4123 if (!i.tm.opcode_modifier.no_wsuf)
4124 suffixes |= 1 << 1;
4125 if (!i.tm.opcode_modifier.no_lsuf)
4126 suffixes |= 1 << 2;
fc4adea1 4127 if (!i.tm.opcode_modifier.no_ldsuf)
40fb9820
L		 4128 suffixes |= 1 << 3;
4129 if (!i.tm.opcode_modifier.no_ssuf)
4130 suffixes |= 1 << 4;
4131 if (!i.tm.opcode_modifier.no_qsuf)
4132 suffixes |= 1 << 5;
4133
4134 /* There are more than suffix matches. */
4135 if (i.tm.opcode_modifier.w
9306ca4a 4136 || ((suffixes & (suffixes - 1))
40fb9820
L		 4137 && !i.tm.opcode_modifier.defaultsize
4138 && !i.tm.opcode_modifier.ignoresize))
9306ca4a
JB		 4139 {
4140 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
4141 return 0;
4142 }
4143 }
29b0f896 4144 }
252b5132 4145
9306ca4a
JB		 4146 /* Change the opcode based on the operand size given by i.suffix;
4147 We don't need to change things for byte insns. */
4148
582d5edd
L		 4149 if (i.suffix
4150 && i.suffix != BYTE_MNEM_SUFFIX
c0f3af97
L		 4151 && i.suffix != XMMWORD_MNEM_SUFFIX
4152 && i.suffix != YMMWORD_MNEM_SUFFIX)
29b0f896
AM		 4153 {
4154 /* It's not a byte, select word/dword operation. */
40fb9820 4155 if (i.tm.opcode_modifier.w)
29b0f896 4156 {
40fb9820 4157 if (i.tm.opcode_modifier.shortform)
29b0f896
AM		 4158 i.tm.base_opcode |= 8;
4159 else
4160 i.tm.base_opcode |= 1;
4161 }
0f3f3d8b 4162
29b0f896
AM		 4163 /* Now select between word & dword operations via the operand
4164 size prefix, except for instructions that will ignore this
4165 prefix anyway. */
ca61edf2 4166 if (i.tm.opcode_modifier.addrprefixop0)
cb712a9e 4167 {
ca61edf2
L		 4168 /* The address size override prefix changes the size of the
4169 first operand. */
40fb9820
L		 4170 if ((flag_code == CODE_32BIT
4171 && i.op->regs[0].reg_type.bitfield.reg16)
4172 || (flag_code != CODE_32BIT
4173 && i.op->regs[0].reg_type.bitfield.reg32))
cb712a9e
L		 4174 if (!add_prefix (ADDR_PREFIX_OPCODE))
4175 return 0;
4176 }
4177 else if (i.suffix != QWORD_MNEM_SUFFIX
4178 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
40fb9820
L		 4179 && !i.tm.opcode_modifier.ignoresize
4180 && !i.tm.opcode_modifier.floatmf
cb712a9e
L		 4181 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
4182 || (flag_code == CODE_64BIT
40fb9820 4183 && i.tm.opcode_modifier.jumpbyte)))
24eab124
AM		 4184 {
4185 unsigned int prefix = DATA_PREFIX_OPCODE;
543613e9 4186
40fb9820 4187 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
29b0f896 4188 prefix = ADDR_PREFIX_OPCODE;
252b5132 4189
29b0f896
AM		 4190 if (!add_prefix (prefix))
4191 return 0;
24eab124 4192 }
252b5132 4193
29b0f896
AM		 4194 /* Set mode64 for an operand. */
4195 if (i.suffix == QWORD_MNEM_SUFFIX
9146926a 4196 && flag_code == CODE_64BIT
40fb9820 4197 && !i.tm.opcode_modifier.norex64)
46e883c5
L		 4198 {
4199 /* Special case for xchg %rax,%rax. It is NOP and doesn't
d9a5e5e5
L		 4200 need rex64. cmpxchg8b is also a special case. */
4201 if (! (i.operands == 2
4202 && i.tm.base_opcode == 0x90
4203 && i.tm.extension_opcode == None
0dfbf9d7
L		 4204 && operand_type_equal (&i.types [0], &acc64)
4205 && operand_type_equal (&i.types [1], &acc64))
d9a5e5e5
L		 4206 && ! (i.operands == 1
4207 && i.tm.base_opcode == 0xfc7
4208 && i.tm.extension_opcode == 1
40fb9820
L		 4209 && !operand_type_check (i.types [0], reg)
4210 && operand_type_check (i.types [0], anymem)))
f6bee062 4211 i.rex |= REX_W;
46e883c5 4212 }
3e73aa7c 4213
29b0f896
AM		 4214 /* Size floating point instruction. */
4215 if (i.suffix == LONG_MNEM_SUFFIX)
40fb9820 4216 if (i.tm.opcode_modifier.floatmf)
543613e9 4217 i.tm.base_opcode ^= 4;
29b0f896 4218 }
7ecd2f8b 4219
29b0f896
AM		 4220 return 1;
4221}
3e73aa7c 4222
29b0f896 4223static int
543613e9 4224check_byte_reg (void)
29b0f896
AM		 4225{
4226 int op;
543613e9 4227
29b0f896
AM		 4228 for (op = i.operands; --op >= 0;)
4229 {
4230 /* If this is an eight bit register, it's OK. If it's the 16 or
4231 32 bit version of an eight bit register, we will just use the
4232 low portion, and that's OK too. */
40fb9820 4233 if (i.types[op].bitfield.reg8)
29b0f896
AM		 4234 continue;
4235
ca61edf2
L		 4236 /* Don't generate this warning if not needed. */
4237 if (intel_syntax && i.tm.opcode_modifier.byteokintel)
29b0f896
AM		 4238 continue;
4239
9344ff29
L		 4240 /* crc32 doesn't generate this warning. */
4241 if (i.tm.base_opcode == 0xf20f38f0)
4242 continue;
4243
40fb9820
L		 4244 if ((i.types[op].bitfield.reg16
4245 || i.types[op].bitfield.reg32
4246 || i.types[op].bitfield.reg64)
4247 && i.op[op].regs->reg_num < 4)
29b0f896
AM		 4248 {
4249 /* Prohibit these changes in the 64bit mode, since the
4250 lowering is more complicated. */
4251 if (flag_code == CODE_64BIT
40fb9820 4252 && !i.tm.operand_types[op].bitfield.inoutportreg)
29b0f896 4253 {
2ca3ace5
L		 4254 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4255 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4256 i.suffix);
4257 return 0;
4258 }
4259#if REGISTER_WARNINGS
4260 if (!quiet_warnings
40fb9820 4261 && !i.tm.operand_types[op].bitfield.inoutportreg)
a540244d
L		 4262 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4263 register_prefix,
40fb9820 4264 (i.op[op].regs + (i.types[op].bitfield.reg16
29b0f896
AM		 4265 ? REGNAM_AL - REGNAM_AX
4266 : REGNAM_AL - REGNAM_EAX))->reg_name,
a540244d 4267 register_prefix,
29b0f896
AM		 4268 i.op[op].regs->reg_name,
4269 i.suffix);
4270#endif
4271 continue;
4272 }
4273 /* Any other register is bad. */
40fb9820
L		 4274 if (i.types[op].bitfield.reg16
4275 || i.types[op].bitfield.reg32
4276 || i.types[op].bitfield.reg64
4277 || i.types[op].bitfield.regmmx
4278 || i.types[op].bitfield.regxmm
c0f3af97 4279 || i.types[op].bitfield.regymm
40fb9820
L		 4280 || i.types[op].bitfield.sreg2
4281 || i.types[op].bitfield.sreg3
4282 || i.types[op].bitfield.control
4283 || i.types[op].bitfield.debug
4284 || i.types[op].bitfield.test
4285 || i.types[op].bitfield.floatreg
4286 || i.types[op].bitfield.floatacc)
29b0f896 4287 {
a540244d
L		 4288 as_bad (_("`%s%s' not allowed with `%s%c'"),
4289 register_prefix,
29b0f896
AM		 4290 i.op[op].regs->reg_name,
4291 i.tm.name,
4292 i.suffix);
4293 return 0;
4294 }
4295 }
4296 return 1;
4297}
4298
4299static int
e3bb37b5 4300check_long_reg (void)
29b0f896
AM		 4301{
4302 int op;
4303
4304 for (op = i.operands; --op >= 0;)
4305 /* Reject eight bit registers, except where the template requires
4306 them. (eg. movzb) */
40fb9820
L		 4307 if (i.types[op].bitfield.reg8
4308 && (i.tm.operand_types[op].bitfield.reg16
4309 || i.tm.operand_types[op].bitfield.reg32
4310 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4311 {
a540244d
L		 4312 as_bad (_("`%s%s' not allowed with `%s%c'"),
4313 register_prefix,
29b0f896
AM		 4314 i.op[op].regs->reg_name,
4315 i.tm.name,
4316 i.suffix);
4317 return 0;
4318 }
4319 /* Warn if the e prefix on a general reg is missing. */
4320 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4321 && i.types[op].bitfield.reg16
4322 && (i.tm.operand_types[op].bitfield.reg32
4323 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4324 {
4325 /* Prohibit these changes in the 64bit mode, since the
4326 lowering is more complicated. */
4327 if (flag_code == CODE_64BIT)
252b5132 4328 {
2ca3ace5
L		 4329 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4330 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4331 i.suffix);
4332 return 0;
252b5132 4333 }
29b0f896
AM		 4334#if REGISTER_WARNINGS
4335 else
a540244d
L		 4336 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4337 register_prefix,
29b0f896 4338 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
a540244d 4339 register_prefix,
29b0f896
AM		 4340 i.op[op].regs->reg_name,
4341 i.suffix);
4342#endif
252b5132 4343 }
29b0f896 4344 /* Warn if the r prefix on a general reg is missing. */
40fb9820
L		 4345 else if (i.types[op].bitfield.reg64
4346 && (i.tm.operand_types[op].bitfield.reg32
4347 || i.tm.operand_types[op].bitfield.acc))
252b5132 4348 {
34828aad 4349 if (intel_syntax
ca61edf2 4350 && i.tm.opcode_modifier.toqword
40fb9820 4351 && !i.types[0].bitfield.regxmm)
34828aad 4352 {
ca61edf2 4353 /* Convert to QWORD. We want REX byte. */
34828aad
L		 4354 i.suffix = QWORD_MNEM_SUFFIX;
4355 }
4356 else
4357 {
4358 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4359 register_prefix, i.op[op].regs->reg_name,
4360 i.suffix);
4361 return 0;
4362 }
29b0f896
AM		 4363 }
4364 return 1;
4365}
252b5132 4366
29b0f896 4367static int
e3bb37b5 4368check_qword_reg (void)
29b0f896
AM		 4369{
4370 int op;
252b5132 4371
29b0f896
AM		 4372 for (op = i.operands; --op >= 0; )
4373 /* Reject eight bit registers, except where the template requires
4374 them. (eg. movzb) */
40fb9820
L		 4375 if (i.types[op].bitfield.reg8
4376 && (i.tm.operand_types[op].bitfield.reg16
4377 || i.tm.operand_types[op].bitfield.reg32
4378 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4379 {
a540244d
L		 4380 as_bad (_("`%s%s' not allowed with `%s%c'"),
4381 register_prefix,
29b0f896
AM		 4382 i.op[op].regs->reg_name,
4383 i.tm.name,
4384 i.suffix);
4385 return 0;
4386 }
4387 /* Warn if the e prefix on a general reg is missing. */
40fb9820
L		 4388 else if ((i.types[op].bitfield.reg16
4389 || i.types[op].bitfield.reg32)
4390 && (i.tm.operand_types[op].bitfield.reg32
4391 || i.tm.operand_types[op].bitfield.acc))
29b0f896
AM		 4392 {
4393 /* Prohibit these changes in the 64bit mode, since the
4394 lowering is more complicated. */
34828aad 4395 if (intel_syntax
ca61edf2 4396 && i.tm.opcode_modifier.todword
40fb9820 4397 && !i.types[0].bitfield.regxmm)
34828aad 4398 {
ca61edf2 4399 /* Convert to DWORD. We don't want REX byte. */
34828aad
L		 4400 i.suffix = LONG_MNEM_SUFFIX;
4401 }
4402 else
4403 {
4404 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4405 register_prefix, i.op[op].regs->reg_name,
4406 i.suffix);
4407 return 0;
4408 }
252b5132 4409 }
29b0f896
AM		 4410 return 1;
4411}
252b5132 4412
29b0f896 4413static int
e3bb37b5 4414check_word_reg (void)
29b0f896
AM		 4415{
4416 int op;
4417 for (op = i.operands; --op >= 0;)
4418 /* Reject eight bit registers, except where the template requires
4419 them. (eg. movzb) */
40fb9820
L		 4420 if (i.types[op].bitfield.reg8
4421 && (i.tm.operand_types[op].bitfield.reg16
4422 || i.tm.operand_types[op].bitfield.reg32
4423 || i.tm.operand_types[op].bitfield.acc))
29b0f896 4424 {
a540244d
L		 4425 as_bad (_("`%s%s' not allowed with `%s%c'"),
4426 register_prefix,
29b0f896
AM		 4427 i.op[op].regs->reg_name,
4428 i.tm.name,
4429 i.suffix);
4430 return 0;
4431 }
4432 /* Warn if the e prefix on a general reg is present. */
4433 else if ((!quiet_warnings || flag_code == CODE_64BIT)
40fb9820
L		 4434 && i.types[op].bitfield.reg32
4435 && (i.tm.operand_types[op].bitfield.reg16
4436 || i.tm.operand_types[op].bitfield.acc))
252b5132 4437 {
29b0f896
AM		 4438 /* Prohibit these changes in the 64bit mode, since the
4439 lowering is more complicated. */
4440 if (flag_code == CODE_64BIT)
252b5132 4441 {
2ca3ace5
L		 4442 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4443 register_prefix, i.op[op].regs->reg_name,
29b0f896
AM		 4444 i.suffix);
4445 return 0;
252b5132 4446 }
29b0f896
AM		 4447 else
4448#if REGISTER_WARNINGS
a540244d
L		 4449 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4450 register_prefix,
29b0f896 4451 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
a540244d 4452 register_prefix,
29b0f896
AM		 4453 i.op[op].regs->reg_name,
4454 i.suffix);
4455#endif
4456 }
4457 return 1;
4458}
252b5132 4459
29b0f896 4460static int
40fb9820 4461update_imm (unsigned int j)
29b0f896 4462{
40fb9820
L		 4463 i386_operand_type overlap;
4464
c6fb90c8 4465 overlap = operand_type_and (i.types[j], i.tm.operand_types[j]);
40fb9820
L		 4466 if ((overlap.bitfield.imm8
4467 || overlap.bitfield.imm8s
4468 || overlap.bitfield.imm16
4469 || overlap.bitfield.imm32
4470 || overlap.bitfield.imm32s
4471 || overlap.bitfield.imm64)
0dfbf9d7
L		 4472 && !operand_type_equal (&overlap, &imm8)
4473 && !operand_type_equal (&overlap, &imm8s)
4474 && !operand_type_equal (&overlap, &imm16)
4475 && !operand_type_equal (&overlap, &imm32)
4476 && !operand_type_equal (&overlap, &imm32s)
4477 && !operand_type_equal (&overlap, &imm64))
29b0f896
AM		 4478 {
4479 if (i.suffix)
4480 {
40fb9820
L		 4481 i386_operand_type temp;
4482
0dfbf9d7 4483 operand_type_set (&temp, 0);
40fb9820
L		 4484 if (i.suffix == BYTE_MNEM_SUFFIX)
4485 {
4486 temp.bitfield.imm8 = overlap.bitfield.imm8;
4487 temp.bitfield.imm8s = overlap.bitfield.imm8s;
4488 }
4489 else if (i.suffix == WORD_MNEM_SUFFIX)
4490 temp.bitfield.imm16 = overlap.bitfield.imm16;
4491 else if (i.suffix == QWORD_MNEM_SUFFIX)
4492 {
4493 temp.bitfield.imm64 = overlap.bitfield.imm64;
4494 temp.bitfield.imm32s = overlap.bitfield.imm32s;
4495 }
4496 else
4497 temp.bitfield.imm32 = overlap.bitfield.imm32;
4498 overlap = temp;
29b0f896 4499 }
0dfbf9d7
L		 4500 else if (operand_type_equal (&overlap, &imm16_32_32s)
4501 || operand_type_equal (&overlap, &imm16_32)
4502 || operand_type_equal (&overlap, &imm16_32s))
29b0f896 4503 {
40fb9820 4504 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
65da13b5 4505 overlap = imm16;
40fb9820 4506 else
65da13b5 4507 overlap = imm32s;
29b0f896 4508 }
0dfbf9d7
L		 4509 if (!operand_type_equal (&overlap, &imm8)
4510 && !operand_type_equal (&overlap, &imm8s)
4511 && !operand_type_equal (&overlap, &imm16)
4512 && !operand_type_equal (&overlap, &imm32)
4513 && !operand_type_equal (&overlap, &imm32s)
4514 && !operand_type_equal (&overlap, &imm64))
29b0f896 4515 {
4eed87de
AM		 4516 as_bad (_("no instruction mnemonic suffix given; "
4517 "can't determine immediate size"));
29b0f896
AM		 4518 return 0;
4519 }
4520 }
40fb9820 4521 i.types[j] = overlap;
29b0f896 4522
40fb9820
L		 4523 return 1;
4524}
4525
4526static int
4527finalize_imm (void)
4528{
4529 unsigned int j;
29b0f896 4530
40fb9820
L		 4531 for (j = 0; j < 2; j++)
4532 if (update_imm (j) == 0)
4533 return 0;
4534
c6fb90c8 4535 i.types[2] = operand_type_and (i.types[2], i.tm.operand_types[2]);
40fb9820 4536 assert (operand_type_check (i.types[2], imm) == 0);
29b0f896
AM		 4537
4538 return 1;
4539}
4540
85f10a01
MM		 4541static void
4542process_drex (void)
4543{
5dd15031
JJ		 4544 i.drex.modrm_reg = 0;
4545 i.drex.modrm_regmem = 0;
85f10a01
MM		 4546
4547 /* SSE5 4 operand instructions must have the destination the same as
4548 one of the inputs. Figure out the destination register and cache
4549 it away in the drex field, and remember which fields to use for
4550 the modrm byte. */
4551 if (i.tm.opcode_modifier.drex
4552 && i.tm.opcode_modifier.drexv
4553 && i.operands == 4)
4554 {
4555 i.tm.extension_opcode = None;
4556
4557 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4558 if (i.types[0].bitfield.regxmm != 0
4559 && i.types[1].bitfield.regxmm != 0
4560 && i.types[2].bitfield.regxmm != 0
4561 && i.types[3].bitfield.regxmm != 0
4562 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4563 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4564 {
4565 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4566 operand_type_set (&i.types[0], 0);
4567 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4568 i.reg_operands -= 2;
4569
4570 /* There are two different ways to encode a 4 operand
4571 instruction with all registers that uses OC1 set to
4572 0 or 1. Favor setting OC1 to 0 since this mimics the
4573 actions of other SSE5 assemblers. Use modrm encoding 2
4574 for register/register. Include the high order bit that
4575 is normally stored in the REX byte in the register
4576 field. */
4577 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4578 i.drex.modrm_reg = 2;
4579 i.drex.modrm_regmem = 1;
4580 i.drex.reg = (i.op[3].regs->reg_num
4581 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4582 }
4583
4584 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4585 else if (i.types[0].bitfield.regxmm != 0
4586 && i.types[1].bitfield.regxmm != 0
4587 && (i.types[2].bitfield.regxmm
4588 || operand_type_check (i.types[2], anymem))
4589 && i.types[3].bitfield.regxmm != 0
4590 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4591 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4592 {
4593 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4594 operand_type_set (&i.types[0], 0);
4595 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4596 i.reg_operands -= 2;
4597
4598 /* Specify the modrm encoding for memory addressing. Include
4599 the high order bit that is normally stored in the REX byte
4600 in the register field. */
4601 i.tm.extension_opcode = DREX_X1_X2_XMEM_X1;
4602 i.drex.modrm_reg = 1;
4603 i.drex.modrm_regmem = 2;
4604 i.drex.reg = (i.op[3].regs->reg_num
4605 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4606 }
4607
4608 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4609 else if (i.types[0].bitfield.regxmm != 0
4610 && operand_type_check (i.types[1], anymem) != 0
4611 && i.types[2].bitfield.regxmm != 0
4612 && i.types[3].bitfield.regxmm != 0
4613 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4614 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4615 {
4616 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4617 operand_type_set (&i.types[0], 0);
4618 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4619 i.reg_operands -= 2;
4620
4621 /* Specify the modrm encoding for memory addressing. Include
4622 the high order bit that is normally stored in the REX byte
4623 in the register field. */
4624 i.tm.extension_opcode = DREX_X1_XMEM_X2_X1;
4625 i.drex.modrm_reg = 2;
4626 i.drex.modrm_regmem = 1;
4627 i.drex.reg = (i.op[3].regs->reg_num
4628 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4629 }
4630
4631 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4632 else if (i.types[0].bitfield.regxmm != 0
4633 && i.types[1].bitfield.regxmm != 0
4634 && i.types[2].bitfield.regxmm != 0
4635 && i.types[3].bitfield.regxmm != 0
4636 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4637 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4638 {
4639 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4640 operand_type_set (&i.types[2], 0);
4641 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4642 i.reg_operands -= 2;
4643
4644 /* There are two different ways to encode a 4 operand
4645 instruction with all registers that uses OC1 set to
4646 0 or 1. Favor setting OC1 to 0 since this mimics the
4647 actions of other SSE5 assemblers. Use modrm encoding
4648 2 for register/register. Include the high order bit that
4649 is normally stored in the REX byte in the register
4650 field. */
4651 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4652 i.drex.modrm_reg = 1;
4653 i.drex.modrm_regmem = 0;
4654
4655 /* Remember the register, including the upper bits */
4656 i.drex.reg = (i.op[3].regs->reg_num
4657 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4658 }
4659
4660 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4661 else if (i.types[0].bitfield.regxmm != 0
4662 && (i.types[1].bitfield.regxmm
4663 || operand_type_check (i.types[1], anymem))
4664 && i.types[2].bitfield.regxmm != 0
4665 && i.types[3].bitfield.regxmm != 0
4666 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4667 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4668 {
4669 /* Clear the arguments that are stored in drex. */
0dfbf9d7
L		 4670 operand_type_set (&i.types[2], 0);
4671 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4672 i.reg_operands -= 2;
4673
4674 /* Specify the modrm encoding and remember the register
4675 including the bits normally stored in the REX byte. */
4676 i.tm.extension_opcode = DREX_X1_XMEM_X2_X2;
4677 i.drex.modrm_reg = 0;
4678 i.drex.modrm_regmem = 1;
4679 i.drex.reg = (i.op[3].regs->reg_num
4680 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4681 }
4682
4683 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4684 else if (operand_type_check (i.types[0], anymem) != 0
4685 && i.types[1].bitfield.regxmm != 0
4686 && i.types[2].bitfield.regxmm != 0
4687 && i.types[3].bitfield.regxmm != 0
4688 && i.op[2].regs->reg_num == i.op[3].regs->reg_num
4689 && i.op[2].regs->reg_flags == i.op[3].regs->reg_flags)
4690 {
4691 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4692 operand_type_set (&i.types[2], 0);
4693 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4694 i.reg_operands -= 2;
4695
4696 /* Specify the modrm encoding and remember the register
4697 including the bits normally stored in the REX byte. */
4698 i.tm.extension_opcode = DREX_XMEM_X1_X2_X2;
4699 i.drex.modrm_reg = 1;
4700 i.drex.modrm_regmem = 0;
4701 i.drex.reg = (i.op[3].regs->reg_num
4702 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4703 }
4704
4705 else
4706 as_bad (_("Incorrect operands for the '%s' instruction"),
4707 i.tm.name);
4708 }
4709
4710 /* SSE5 instructions with the DREX byte where the only memory operand
4711 is in the 2nd argument, and the first and last xmm register must
4712 match, and is encoded in the DREX byte. */
4713 else if (i.tm.opcode_modifier.drex
4714 && !i.tm.opcode_modifier.drexv
4715 && i.operands == 4)
4716 {
4717 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4718 if (i.types[0].bitfield.regxmm != 0
4719 && (i.types[1].bitfield.regxmm
4720 || operand_type_check(i.types[1], anymem))
4721 && i.types[2].bitfield.regxmm != 0
4722 && i.types[3].bitfield.regxmm != 0
4723 && i.op[0].regs->reg_num == i.op[3].regs->reg_num
4724 && i.op[0].regs->reg_flags == i.op[3].regs->reg_flags)
4725 {
4726 /* clear the arguments that are stored in drex */
0dfbf9d7
L		 4727 operand_type_set (&i.types[0], 0);
4728 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4729 i.reg_operands -= 2;
4730
4731 /* Specify the modrm encoding and remember the register
4732 including the high bit normally stored in the REX
4733 byte. */
4734 i.drex.modrm_reg = 2;
4735 i.drex.modrm_regmem = 1;
4736 i.drex.reg = (i.op[3].regs->reg_num
4737 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4738 }
4739
4740 else
4741 as_bad (_("Incorrect operands for the '%s' instruction"),
4742 i.tm.name);
4743 }
4744
4745 /* SSE5 3 operand instructions that the result is a register, being
4746 either operand can be a memory operand, using OC0 to note which
4747 one is the memory. */
4748 else if (i.tm.opcode_modifier.drex
4749 && i.tm.opcode_modifier.drexv
4750 && i.operands == 3)
4751 {
4752 i.tm.extension_opcode = None;
4753
4754 /* Case 1: 3 operand insn, src1 = register. */
4755 if (i.types[0].bitfield.regxmm != 0
4756 && i.types[1].bitfield.regxmm != 0
4757 && i.types[2].bitfield.regxmm != 0)
4758 {
4759 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4760 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4761 i.reg_operands--;
4762
4763 /* Specify the modrm encoding and remember the register
4764 including the high bit normally stored in the REX byte. */
4765 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4766 i.drex.modrm_reg = 1;
4767 i.drex.modrm_regmem = 0;
4768 i.drex.reg = (i.op[2].regs->reg_num
4769 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4770 }
4771
4772 /* Case 2: 3 operand insn, src1 = memory. */
4773 else if (operand_type_check (i.types[0], anymem) != 0
4774 && i.types[1].bitfield.regxmm != 0
4775 && i.types[2].bitfield.regxmm != 0)
4776 {
4777 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4778 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4779 i.reg_operands--;
4780
4781 /* Specify the modrm encoding and remember the register
4782 including the high bit normally stored in the REX
4783 byte. */
4784 i.tm.extension_opcode = DREX_XMEM_X1_X2;
4785 i.drex.modrm_reg = 1;
4786 i.drex.modrm_regmem = 0;
4787 i.drex.reg = (i.op[2].regs->reg_num
4788 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4789 }
4790
4791 /* Case 3: 3 operand insn, src2 = memory. */
4792 else if (i.types[0].bitfield.regxmm != 0
4793 && operand_type_check (i.types[1], anymem) != 0
4794 && i.types[2].bitfield.regxmm != 0)
4795 {
4796 /* Clear the arguments that are stored in drex. */
0dfbf9d7 4797 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4798 i.reg_operands--;
4799
4800 /* Specify the modrm encoding and remember the register
4801 including the high bit normally stored in the REX byte. */
4802 i.tm.extension_opcode = DREX_X1_XMEM_X2;
4803 i.drex.modrm_reg = 0;
4804 i.drex.modrm_regmem = 1;
4805 i.drex.reg = (i.op[2].regs->reg_num
4806 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4807 }
4808
4809 else
4810 as_bad (_("Incorrect operands for the '%s' instruction"),
4811 i.tm.name);
4812 }
4813
4814 /* SSE5 4 operand instructions that are the comparison instructions
4815 where the first operand is the immediate value of the comparison
4816 to be done. */
4817 else if (i.tm.opcode_modifier.drexc != 0 && i.operands == 4)
4818 {
4819 /* Case 1: 4 operand insn, src1 = reg/memory. */
4820 if (operand_type_check (i.types[0], imm) != 0
4821 && (i.types[1].bitfield.regxmm
4822 || operand_type_check (i.types[1], anymem))
4823 && i.types[2].bitfield.regxmm != 0
4824 && i.types[3].bitfield.regxmm != 0)
4825 {
4826 /* clear the arguments that are stored in drex */
0dfbf9d7 4827 operand_type_set (&i.types[3], 0);
85f10a01
MM		 4828 i.reg_operands--;
4829
4830 /* Specify the modrm encoding and remember the register
4831 including the high bit normally stored in the REX byte. */
4832 i.drex.modrm_reg = 2;
4833 i.drex.modrm_regmem = 1;
4834 i.drex.reg = (i.op[3].regs->reg_num
4835 + ((i.op[3].regs->reg_flags & RegRex) ? 8 : 0));
4836 }
4837
4838 /* Case 2: 3 operand insn with ImmExt that places the
4839 opcode_extension as an immediate argument. This is used for
4840 all of the varients of comparison that supplies the appropriate
4841 value as part of the instruction. */
4842 else if ((i.types[0].bitfield.regxmm
4843 || operand_type_check (i.types[0], anymem))
4844 && i.types[1].bitfield.regxmm != 0
4845 && i.types[2].bitfield.regxmm != 0
4846 && operand_type_check (i.types[3], imm) != 0)
4847 {
4848 /* clear the arguments that are stored in drex */
0dfbf9d7 4849 operand_type_set (&i.types[2], 0);
85f10a01
MM		 4850 i.reg_operands--;
4851
4852 /* Specify the modrm encoding and remember the register
4853 including the high bit normally stored in the REX byte. */
4854 i.drex.modrm_reg = 1;
4855 i.drex.modrm_regmem = 0;
4856 i.drex.reg = (i.op[2].regs->reg_num
4857 + ((i.op[2].regs->reg_flags & RegRex) ? 8 : 0));
4858 }
4859
4860 else
4861 as_bad (_("Incorrect operands for the '%s' instruction"),
4862 i.tm.name);
4863 }
4864
4865 else if (i.tm.opcode_modifier.drex
4866 || i.tm.opcode_modifier.drexv
4867 || i.tm.opcode_modifier.drexc)
4868 as_bad (_("Internal error for the '%s' instruction"), i.tm.name);
4869}
4870
c0f3af97
L		 4871static int
4872bad_implicit_operand (int xmm)
4873{
4874 const char *reg = xmm ? "xmm0" : "ymm0";
4875 if (intel_syntax)
4876 as_bad (_("the last operand of `%s' must be `%s%s'"),
4877 i.tm.name, register_prefix, reg);
4878 else
4879 as_bad (_("the first operand of `%s' must be `%s%s'"),
4880 i.tm.name, register_prefix, reg);
4881 return 0;
4882}
4883
29b0f896 4884static int
e3bb37b5 4885process_operands (void)
29b0f896
AM		 4886{
4887 /* Default segment register this instruction will use for memory
4888 accesses. 0 means unknown. This is only for optimizing out
4889 unnecessary segment overrides. */
4890 const seg_entry *default_seg = 0;
4891
85f10a01
MM		 4892 /* Handle all of the DREX munging that SSE5 needs. */
4893 if (i.tm.opcode_modifier.drex
4894 || i.tm.opcode_modifier.drexv
4895 || i.tm.opcode_modifier.drexc)
4896 process_drex ();
4897
c0f3af97
L		 4898 if (i.tm.opcode_modifier.sse2avx
4899 && (i.tm.opcode_modifier.vexnds
4900 || i.tm.opcode_modifier.vexndd))
29b0f896 4901 {
c0f3af97
L		 4902 unsigned int dup = i.operands;
4903 unsigned int dest = dup - 1;
9fcfb3d7
L		 4904 unsigned int j;
4905
c0f3af97 4906 /* The destination must be an xmm register. */
0dfbf9d7 4907 assert (i.reg_operands
c0f3af97
L		 4908 && MAX_OPERANDS > dup
4909 && operand_type_equal (&i.types[dest], &regxmm));
4910
4911 if (i.tm.opcode_modifier.firstxmm0)
e2ec9d29 4912 {
c0f3af97
L		 4913 /* The first operand is implicit and must be xmm0. */
4914 assert (operand_type_equal (&i.types[0], &regxmm));
4915 if (i.op[0].regs->reg_num != 0)
4916 return bad_implicit_operand (1);
4917
4918 if (i.tm.opcode_modifier.vex3sources)
4919 {
4920 /* Keep xmm0 for instructions with VEX prefix and 3
4921 sources. */
4922 goto duplicate;
4923 }
e2ec9d29 4924 else
c0f3af97
L		 4925 {
4926 /* We remove the first xmm0 and keep the number of
4927 operands unchanged, which in fact duplicates the
4928 destination. */
4929 for (j = 1; j < i.operands; j++)
4930 {
4931 i.op[j - 1] = i.op[j];
4932 i.types[j - 1] = i.types[j];
4933 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
4934 }
4935 }
4936 }
4937 else if (i.tm.opcode_modifier.implicit1stxmm0)
4938 {
4939 assert ((MAX_OPERANDS - 1) > dup
4940 && i.tm.opcode_modifier.vex3sources);
4941
4942 /* Add the implicit xmm0 for instructions with VEX prefix
4943 and 3 sources. */
4944 for (j = i.operands; j > 0; j--)
4945 {
4946 i.op[j] = i.op[j - 1];
4947 i.types[j] = i.types[j - 1];
4948 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
4949 }
4950 i.op[0].regs
4951 = (const reg_entry *) hash_find (reg_hash, "xmm0");
4952 i.types[0] = regxmm;
4953 i.tm.operand_types[0] = regxmm;
4954
4955 i.operands += 2;
4956 i.reg_operands += 2;
4957 i.tm.operands += 2;
4958
4959 dup++;
4960 dest++;
4961 i.op[dup] = i.op[dest];
4962 i.types[dup] = i.types[dest];
4963 i.tm.operand_types[dup] = i.tm.operand_types[dest];
e2ec9d29 4964 }
c0f3af97
L		 4965 else
4966 {
4967duplicate:
4968 i.operands++;
4969 i.reg_operands++;
4970 i.tm.operands++;
4971
4972 i.op[dup] = i.op[dest];
4973 i.types[dup] = i.types[dest];
4974 i.tm.operand_types[dup] = i.tm.operand_types[dest];
4975 }
4976
4977 if (i.tm.opcode_modifier.immext)
4978 process_immext ();
4979 }
4980 else if (i.tm.opcode_modifier.firstxmm0)
4981 {
4982 unsigned int j;
4983
4984 /* The first operand is implicit and must be xmm0/ymm0. */
4985 assert (i.reg_operands
4986 && (operand_type_equal (&i.types[0], &regxmm)
4987 || operand_type_equal (&i.types[0], &regymm)));
4988 if (i.op[0].regs->reg_num != 0)
4989 return bad_implicit_operand (i.types[0].bitfield.regxmm);
9fcfb3d7
L		 4990
4991 for (j = 1; j < i.operands; j++)
4992 {
4993 i.op[j - 1] = i.op[j];
4994 i.types[j - 1] = i.types[j];
4995
4996 /* We need to adjust fields in i.tm since they are used by
4997 build_modrm_byte. */
4998 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
4999 }
5000
e2ec9d29
L		 5001 i.operands--;
5002 i.reg_operands--;
e2ec9d29
L		 5003 i.tm.operands--;
5004 }
5005 else if (i.tm.opcode_modifier.regkludge)
5006 {
5007 /* The imul $imm, %reg instruction is converted into
5008 imul $imm, %reg, %reg, and the clr %reg instruction
5009 is converted into xor %reg, %reg. */
5010
5011 unsigned int first_reg_op;
5012
5013 if (operand_type_check (i.types[0], reg))
5014 first_reg_op = 0;
5015 else
5016 first_reg_op = 1;
5017 /* Pretend we saw the extra register operand. */
5018 assert (i.reg_operands == 1
5019 && i.op[first_reg_op + 1].regs == 0);
5020 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5021 i.types[first_reg_op + 1] = i.types[first_reg_op];
5022 i.operands++;
5023 i.reg_operands++;
29b0f896
AM		 5024 }
5025
40fb9820 5026 if (i.tm.opcode_modifier.shortform)
29b0f896 5027 {
40fb9820
L		 5028 if (i.types[0].bitfield.sreg2
5029 || i.types[0].bitfield.sreg3)
29b0f896 5030 {
4eed87de
AM		 5031 if (i.tm.base_opcode == POP_SEG_SHORT
5032 && i.op[0].regs->reg_num == 1)
29b0f896 5033 {
a87af027 5034 as_bad (_("you can't `pop %scs'"), register_prefix);
4eed87de 5035 return 0;
29b0f896 5036 }
4eed87de
AM		 5037 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5038 if ((i.op[0].regs->reg_flags & RegRex) != 0)
161a04f6 5039 i.rex |= REX_B;
4eed87de
AM		 5040 }
5041 else
5042 {
85f10a01
MM		 5043 /* The register or float register operand is in operand
5044 0 or 1. */
40fb9820
L		 5045 unsigned int op;
5046
5047 if (i.types[0].bitfield.floatreg
5048 || operand_type_check (i.types[0], reg))
5049 op = 0;
5050 else
5051 op = 1;
4eed87de
AM		 5052 /* Register goes in low 3 bits of opcode. */
5053 i.tm.base_opcode |= i.op[op].regs->reg_num;
5054 if ((i.op[op].regs->reg_flags & RegRex) != 0)
161a04f6 5055 i.rex |= REX_B;
40fb9820 5056 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
29b0f896 5057 {
4eed87de
AM		 5058 /* Warn about some common errors, but press on regardless.
5059 The first case can be generated by gcc (<= 2.8.1). */
5060 if (i.operands == 2)
5061 {
5062 /* Reversed arguments on faddp, fsubp, etc. */
a540244d 5063 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
d8a1b51e
JB		 5064 register_prefix, i.op[!intel_syntax].regs->reg_name,
5065 register_prefix, i.op[intel_syntax].regs->reg_name);
4eed87de
AM		 5066 }
5067 else
5068 {
5069 /* Extraneous `l' suffix on fp insn. */
a540244d
L		 5070 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5071 register_prefix, i.op[0].regs->reg_name);
4eed87de 5072 }
29b0f896
AM		 5073 }
5074 }
5075 }
40fb9820 5076 else if (i.tm.opcode_modifier.modrm)
29b0f896
AM		 5077 {
5078 /* The opcode is completed (modulo i.tm.extension_opcode which
52271982
AM		 5079 must be put into the modrm byte). Now, we make the modrm and
5080 index base bytes based on all the info we've collected. */
29b0f896
AM		 5081
5082 default_seg = build_modrm_byte ();
5083 }
8a2ed489 5084 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
29b0f896
AM		 5085 {
5086 default_seg = &ds;
5087 }
40fb9820 5088 else if (i.tm.opcode_modifier.isstring)
29b0f896
AM		 5089 {
5090 /* For the string instructions that allow a segment override
5091 on one of their operands, the default segment is ds. */
5092 default_seg = &ds;
5093 }
5094
75178d9d
L		 5095 if (i.tm.base_opcode == 0x8d /* lea */
5096 && i.seg[0]
5097 && !quiet_warnings)
30123838 5098 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
52271982
AM		 5099
5100 /* If a segment was explicitly specified, and the specified segment
5101 is not the default, use an opcode prefix to select it. If we
5102 never figured out what the default segment is, then default_seg
5103 will be zero at this point, and the specified segment prefix will
5104 always be used. */
29b0f896
AM		 5105 if ((i.seg[0]) && (i.seg[0] != default_seg))
5106 {
5107 if (!add_prefix (i.seg[0]->seg_prefix))
5108 return 0;
5109 }
5110 return 1;
5111}
5112
5113static const seg_entry *
e3bb37b5 5114build_modrm_byte (void)
29b0f896
AM		 5115{
5116 const seg_entry *default_seg = 0;
c0f3af97
L		 5117 unsigned int source, dest;
5118 int vex_3_sources;
5119
5120 /* The first operand of instructions with VEX prefix and 3 sources
5121 must be VEX_Imm4. */
5122 vex_3_sources = i.tm.opcode_modifier.vex3sources;
5123 if (vex_3_sources)
5124 {
5125 unsigned int nds, reg;
5126
0bfee649 5127 dest = i.operands - 1;
c0f3af97 5128 nds = dest - 1;
0bfee649
L		 5129 source = 1;
5130 reg = 0;
5131
5132 /* This instruction must have 4 operands: 4 register operands
5133 or 3 register operands plus 1 memory operand. It must have
5134 VexNDS and VexImmExt. */
5135 assert (i.operands == 4
5136 && (i.reg_operands == 4
5137 || (i.reg_operands == 3 && i.mem_operands == 1))
5138 && i.tm.opcode_modifier.vexnds
5139 && i.tm.opcode_modifier.veximmext
5140 && (operand_type_equal (&i.tm.operand_types[dest],
5141 &regxmm)
5142 || operand_type_equal (&i.tm.operand_types[dest],
5143 &regymm))
5144 && (operand_type_equal (&i.tm.operand_types[nds],
5145 &regxmm)
5146 || operand_type_equal (&i.tm.operand_types[nds],
5147 &regymm))
5148 && (operand_type_equal (&i.tm.operand_types[reg],
5149 &regxmm)
c0f3af97 5150 || operand_type_equal (&i.tm.operand_types[reg],
0bfee649 5151 &regymm)));
c0f3af97 5152
0bfee649
L		 5153 /* Generate an 8bit immediate operand to encode the register
5154 operand. */
5155 expressionS *exp = &im_expressions[i.imm_operands++];
5156 i.op[i.operands].imms = exp;
5157 i.types[i.operands] = imm8;
5158 i.operands++;
5159 exp->X_op = O_constant;
5160 exp->X_add_number
5161 = ((i.op[0].regs->reg_num
5162 + ((i.op[0].regs->reg_flags & RegRex) ? 8 : 0)) << 4);
dae39acc 5163
dae39acc 5164 i.vex.register_specifier = i.op[nds].regs;
c0f3af97
L		 5165 }
5166 else
5167 source = dest = 0;
29b0f896 5168
85f10a01
MM		 5169 /* SSE5 4 operand instructions are encoded in such a way that one of
5170 the inputs must match the destination register. Process_drex hides
5171 the 3rd argument in the drex field, so that by the time we get
5172 here, it looks to GAS as if this is a 2 operand instruction. */
5173 if ((i.tm.opcode_modifier.drex
5174 || i.tm.opcode_modifier.drexv
b5016f89 5175 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5176 && i.reg_operands == 2)
5177 {
5178 const reg_entry *reg = i.op[i.drex.modrm_reg].regs;
5179 const reg_entry *regmem = i.op[i.drex.modrm_regmem].regs;
5180
5181 i.rm.reg = reg->reg_num;
5182 i.rm.regmem = regmem->reg_num;
5183 i.rm.mode = 3;
5184 if ((reg->reg_flags & RegRex) != 0)
5185 i.rex |= REX_R;
5186 if ((regmem->reg_flags & RegRex) != 0)
5187 i.rex |= REX_B;
5188 }
5189
29b0f896 5190 /* i.reg_operands MUST be the number of real register operands;
c0f3af97
L		 5191 implicit registers do not count. If there are 3 register
5192 operands, it must be a instruction with VexNDS. For a
5193 instruction with VexNDD, the destination register is encoded
5194 in VEX prefix. If there are 4 register operands, it must be
5195 a instruction with VEX prefix and 3 sources. */
5196 else if (i.mem_operands == 0
5197 && ((i.reg_operands == 2
5198 && !i.tm.opcode_modifier.vexndd)
5199 || (i.reg_operands == 3
5200 && i.tm.opcode_modifier.vexnds)
5201 || (i.reg_operands == 4 && vex_3_sources)))
29b0f896 5202 {
cab737b9
L		 5203 switch (i.operands)
5204 {
5205 case 2:
5206 source = 0;
5207 break;
5208 case 3:
c81128dc
L		 5209 /* When there are 3 operands, one of them may be immediate,
5210 which may be the first or the last operand. Otherwise,
c0f3af97
L		 5211 the first operand must be shift count register (cl) or it
5212 is an instruction with VexNDS. */
c81128dc
L		 5213 assert (i.imm_operands == 1
5214 || (i.imm_operands == 0
c0f3af97
L		 5215 && (i.tm.opcode_modifier.vexnds
5216 || i.types[0].bitfield.shiftcount)));
40fb9820
L		 5217 if (operand_type_check (i.types[0], imm)
5218 || i.types[0].bitfield.shiftcount)
5219 source = 1;
5220 else
5221 source = 0;
cab737b9
L		 5222 break;
5223 case 4:
368d64cc
L		 5224 /* When there are 4 operands, the first two must be 8bit
5225 immediate operands. The source operand will be the 3rd
c0f3af97
L		 5226 one.
5227
5228 For instructions with VexNDS, if the first operand
5229 an imm8, the source operand is the 2nd one. If the last
5230 operand is imm8, the source operand is the first one. */
5231 assert ((i.imm_operands == 2
5232 && i.types[0].bitfield.imm8
5233 && i.types[1].bitfield.imm8)
5234 || (i.tm.opcode_modifier.vexnds
5235 && i.imm_operands == 1
5236 && (i.types[0].bitfield.imm8
5237 || i.types[i.operands - 1].bitfield.imm8)));
5238 if (i.tm.opcode_modifier.vexnds)
5239 {
5240 if (i.types[0].bitfield.imm8)
5241 source = 1;
5242 else
5243 source = 0;
5244 }
5245 else
5246 source = 2;
5247 break;
5248 case 5:
cab737b9
L		 5249 break;
5250 default:
5251 abort ();
5252 }
5253
c0f3af97
L		 5254 if (!vex_3_sources)
5255 {
5256 dest = source + 1;
5257
5258 if (i.tm.opcode_modifier.vexnds)
5259 {
5260 /* For instructions with VexNDS, the register-only
5261 source operand must be XMM or YMM register. It is
fa99fab2
L		 5262 encoded in VEX prefix. We need to clear RegMem bit
5263 before calling operand_type_equal. */
5264 i386_operand_type op = i.tm.operand_types[dest];
5265 op.bitfield.regmem = 0;
c0f3af97 5266 if ((dest + 1) >= i.operands
fa99fab2
L		 5267 || (!operand_type_equal (&op, &regxmm)
5268 && !operand_type_equal (&op, &regymm)))
c0f3af97
L		 5269 abort ();
5270 i.vex.register_specifier = i.op[dest].regs;
5271 dest++;
5272 }
5273 }
29b0f896
AM		 5274
5275 i.rm.mode = 3;
5276 /* One of the register operands will be encoded in the i.tm.reg
5277 field, the other in the combined i.tm.mode and i.tm.regmem
5278 fields. If no form of this instruction supports a memory
5279 destination operand, then we assume the source operand may
5280 sometimes be a memory operand and so we need to store the
5281 destination in the i.rm.reg field. */
40fb9820
L		 5282 if (!i.tm.operand_types[dest].bitfield.regmem
5283 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
29b0f896
AM		 5284 {
5285 i.rm.reg = i.op[dest].regs->reg_num;
5286 i.rm.regmem = i.op[source].regs->reg_num;
5287 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5288 i.rex |= REX_R;
29b0f896 5289 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5290 i.rex |= REX_B;
29b0f896
AM		 5291 }
5292 else
5293 {
5294 i.rm.reg = i.op[source].regs->reg_num;
5295 i.rm.regmem = i.op[dest].regs->reg_num;
5296 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
161a04f6 5297 i.rex |= REX_B;
29b0f896 5298 if ((i.op[source].regs->reg_flags & RegRex) != 0)
161a04f6 5299 i.rex |= REX_R;
29b0f896 5300 }
161a04f6 5301 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
c4a530c5 5302 {
40fb9820
L		 5303 if (!i.types[0].bitfield.control
5304 && !i.types[1].bitfield.control)
c4a530c5 5305 abort ();
161a04f6 5306 i.rex &= ~(REX_R | REX_B);
c4a530c5
JB		 5307 add_prefix (LOCK_PREFIX_OPCODE);
5308 }
29b0f896
AM		 5309 }
5310 else
5311 { /* If it's not 2 reg operands... */
c0f3af97
L		 5312 unsigned int mem;
5313
29b0f896
AM		 5314 if (i.mem_operands)
5315 {
5316 unsigned int fake_zero_displacement = 0;
99018f42 5317 unsigned int op;
4eed87de 5318
85f10a01
MM		 5319 /* This has been precalculated for SSE5 instructions
5320 that have a DREX field earlier in process_drex. */
b5016f89
L		 5321 if (i.tm.opcode_modifier.drex
5322 || i.tm.opcode_modifier.drexv
5323 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5324 op = i.drex.modrm_regmem;
5325 else
5326 {
c0209578
L		 5327 for (op = 0; op < i.operands; op++)
5328 if (operand_type_check (i.types[op], anymem))
5329 break;
5330 assert (op < i.operands);
85f10a01 5331 }
29b0f896
AM		 5332
5333 default_seg = &ds;
5334
5335 if (i.base_reg == 0)
5336 {
5337 i.rm.mode = 0;
5338 if (!i.disp_operands)
5339 fake_zero_displacement = 1;
5340 if (i.index_reg == 0)
5341 {
5342 /* Operand is just <disp> */
20f0a1fc 5343 if (flag_code == CODE_64BIT)
29b0f896
AM		 5344 {
5345 /* 64bit mode overwrites the 32bit absolute
5346 addressing by RIP relative addressing and
5347 absolute addressing is encoded by one of the
5348 redundant SIB forms. */
5349 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5350 i.sib.base = NO_BASE_REGISTER;
5351 i.sib.index = NO_INDEX_REGISTER;
fc225355 5352 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
40fb9820 5353 ? disp32s : disp32);
20f0a1fc 5354 }
fc225355
L		 5355 else if ((flag_code == CODE_16BIT)
5356 ^ (i.prefix[ADDR_PREFIX] != 0))
20f0a1fc
NC		 5357 {
5358 i.rm.regmem = NO_BASE_REGISTER_16;
40fb9820 5359 i.types[op] = disp16;
20f0a1fc
NC		 5360 }
5361 else
5362 {
5363 i.rm.regmem = NO_BASE_REGISTER;
40fb9820 5364 i.types[op] = disp32;
29b0f896
AM		 5365 }
5366 }
5367 else /* !i.base_reg && i.index_reg */
5368 {
db51cc60
L		 5369 if (i.index_reg->reg_num == RegEiz
5370 || i.index_reg->reg_num == RegRiz)
5371 i.sib.index = NO_INDEX_REGISTER;
5372 else
5373 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5374 i.sib.base = NO_BASE_REGISTER;
5375 i.sib.scale = i.log2_scale_factor;
5376 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
40fb9820
L		 5377 i.types[op].bitfield.disp8 = 0;
5378 i.types[op].bitfield.disp16 = 0;
5379 i.types[op].bitfield.disp64 = 0;
29b0f896 5380 if (flag_code != CODE_64BIT)
40fb9820
L		 5381 {
5382 /* Must be 32 bit */
5383 i.types[op].bitfield.disp32 = 1;
5384 i.types[op].bitfield.disp32s = 0;
5385 }
29b0f896 5386 else
40fb9820
L		 5387 {
5388 i.types[op].bitfield.disp32 = 0;
5389 i.types[op].bitfield.disp32s = 1;
5390 }
29b0f896 5391 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5392 i.rex |= REX_X;
29b0f896
AM		 5393 }
5394 }
5395 /* RIP addressing for 64bit mode. */
9a04903e
JB		 5396 else if (i.base_reg->reg_num == RegRip ||
5397 i.base_reg->reg_num == RegEip)
29b0f896
AM		 5398 {
5399 i.rm.regmem = NO_BASE_REGISTER;
40fb9820
L		 5400 i.types[op].bitfield.disp8 = 0;
5401 i.types[op].bitfield.disp16 = 0;
5402 i.types[op].bitfield.disp32 = 0;
5403 i.types[op].bitfield.disp32s = 1;
5404 i.types[op].bitfield.disp64 = 0;
71903a11 5405 i.flags[op] |= Operand_PCrel;
20f0a1fc
NC		 5406 if (! i.disp_operands)
5407 fake_zero_displacement = 1;
29b0f896 5408 }
40fb9820 5409 else if (i.base_reg->reg_type.bitfield.reg16)
29b0f896
AM		 5410 {
5411 switch (i.base_reg->reg_num)
5412 {
5413 case 3: /* (%bx) */
5414 if (i.index_reg == 0)
5415 i.rm.regmem = 7;
5416 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5417 i.rm.regmem = i.index_reg->reg_num - 6;
5418 break;
5419 case 5: /* (%bp) */
5420 default_seg = &ss;
5421 if (i.index_reg == 0)
5422 {
5423 i.rm.regmem = 6;
40fb9820 5424 if (operand_type_check (i.types[op], disp) == 0)
29b0f896
AM		 5425 {
5426 /* fake (%bp) into 0(%bp) */
40fb9820 5427 i.types[op].bitfield.disp8 = 1;
252b5132 5428 fake_zero_displacement = 1;
29b0f896
AM		 5429 }
5430 }
5431 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5432 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
5433 break;
5434 default: /* (%si) -> 4 or (%di) -> 5 */
5435 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
5436 }
5437 i.rm.mode = mode_from_disp_size (i.types[op]);
5438 }
5439 else /* i.base_reg and 32/64 bit mode */
5440 {
5441 if (flag_code == CODE_64BIT
40fb9820
L		 5442 && operand_type_check (i.types[op], disp))
5443 {
5444 i386_operand_type temp;
0dfbf9d7 5445 operand_type_set (&temp, 0);
40fb9820
L		 5446 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
5447 i.types[op] = temp;
5448 if (i.prefix[ADDR_PREFIX] == 0)
5449 i.types[op].bitfield.disp32s = 1;
5450 else
5451 i.types[op].bitfield.disp32 = 1;
5452 }
20f0a1fc 5453
29b0f896
AM		 5454 i.rm.regmem = i.base_reg->reg_num;
5455 if ((i.base_reg->reg_flags & RegRex) != 0)
161a04f6 5456 i.rex |= REX_B;
29b0f896
AM		 5457 i.sib.base = i.base_reg->reg_num;
5458 /* x86-64 ignores REX prefix bit here to avoid decoder
5459 complications. */
5460 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
5461 {
5462 default_seg = &ss;
5463 if (i.disp_operands == 0)
5464 {
5465 fake_zero_displacement = 1;
40fb9820 5466 i.types[op].bitfield.disp8 = 1;
29b0f896
AM		 5467 }
5468 }
5469 else if (i.base_reg->reg_num == ESP_REG_NUM)
5470 {
5471 default_seg = &ss;
5472 }
5473 i.sib.scale = i.log2_scale_factor;
5474 if (i.index_reg == 0)
5475 {
5476 /* <disp>(%esp) becomes two byte modrm with no index
5477 register. We've already stored the code for esp
5478 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5479 Any base register besides %esp will not use the
5480 extra modrm byte. */
5481 i.sib.index = NO_INDEX_REGISTER;
29b0f896
AM		 5482 }
5483 else
5484 {
db51cc60
L		 5485 if (i.index_reg->reg_num == RegEiz
5486 || i.index_reg->reg_num == RegRiz)
5487 i.sib.index = NO_INDEX_REGISTER;
5488 else
5489 i.sib.index = i.index_reg->reg_num;
29b0f896
AM		 5490 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
5491 if ((i.index_reg->reg_flags & RegRex) != 0)
161a04f6 5492 i.rex |= REX_X;
29b0f896 5493 }
67a4f2b7
AO		 5494
5495 if (i.disp_operands
5496 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
5497 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
5498 i.rm.mode = 0;
5499 else
5500 i.rm.mode = mode_from_disp_size (i.types[op]);
29b0f896 5501 }
252b5132 5502
29b0f896
AM		 5503 if (fake_zero_displacement)
5504 {
5505 /* Fakes a zero displacement assuming that i.types[op]
5506 holds the correct displacement size. */
5507 expressionS *exp;
5508
5509 assert (i.op[op].disps == 0);
5510 exp = &disp_expressions[i.disp_operands++];
5511 i.op[op].disps = exp;
5512 exp->X_op = O_constant;
5513 exp->X_add_number = 0;
5514 exp->X_add_symbol = (symbolS *) 0;
5515 exp->X_op_symbol = (symbolS *) 0;
5516 }
c0f3af97
L		 5517
5518 mem = op;
29b0f896 5519 }
c0f3af97
L		 5520 else
5521 mem = ~0;
252b5132 5522
29b0f896
AM		 5523 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5524 (if any) based on i.tm.extension_opcode. Again, we must be
5525 careful to make sure that segment/control/debug/test/MMX
5526 registers are coded into the i.rm.reg field. */
5527 if (i.reg_operands)
5528 {
99018f42
L		 5529 unsigned int op;
5530
85f10a01
MM		 5531 /* This has been precalculated for SSE5 instructions
5532 that have a DREX field earlier in process_drex. */
b5016f89
L		 5533 if (i.tm.opcode_modifier.drex
5534 || i.tm.opcode_modifier.drexv
5535 || i.tm.opcode_modifier.drexc)
85f10a01
MM		 5536 {
5537 op = i.drex.modrm_reg;
5538 i.rm.reg = i.op[op].regs->reg_num;
5539 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5540 i.rex |= REX_R;
5541 }
5542 else
5543 {
c0f3af97
L		 5544 unsigned int vex_reg = ~0;
5545
c0209578
L		 5546 for (op = 0; op < i.operands; op++)
5547 if (i.types[op].bitfield.reg8
5548 || i.types[op].bitfield.reg16
5549 || i.types[op].bitfield.reg32
5550 || i.types[op].bitfield.reg64
5551 || i.types[op].bitfield.regmmx
5552 || i.types[op].bitfield.regxmm
c0f3af97 5553 || i.types[op].bitfield.regymm
c0209578
L		 5554 || i.types[op].bitfield.sreg2
5555 || i.types[op].bitfield.sreg3
5556 || i.types[op].bitfield.control
5557 || i.types[op].bitfield.debug
5558 || i.types[op].bitfield.test)
5559 break;
5560
c0f3af97
L		 5561 if (vex_3_sources)
5562 op = dest;
5563 else if (i.tm.opcode_modifier.vexnds)
5564 {
5565 /* For instructions with VexNDS, the register-only
5566 source operand is encoded in VEX prefix. */
5567 assert (mem != (unsigned int) ~0);
5568
5569 if (op > mem)
5570 {
5571 vex_reg = op++;
5572 assert (op < i.operands);
5573 }
5574 else
5575 {
5576 vex_reg = op + 1;
5577 assert (vex_reg < i.operands);
5578 }
5579 }
5580 else if (i.tm.opcode_modifier.vexndd)
5581 {
5582 /* For instructions with VexNDD, there should be
5583 no memory operand and the register destination
5584 is encoded in VEX prefix. */
5585 assert (i.mem_operands == 0
5586 && (op + 2) == i.operands);
5587 vex_reg = op + 1;
5588 }
5589 else
5590 assert (op < i.operands);
5591
5592 if (vex_reg != (unsigned int) ~0)
5593 {
5594 assert (i.reg_operands == 2);
5595
5596 if (!operand_type_equal (&i.tm.operand_types[vex_reg],
5597 & regxmm)
5598 && !operand_type_equal (&i.tm.operand_types[vex_reg],
5599 &regymm))
5600 abort ();
5601 i.vex.register_specifier = i.op[vex_reg].regs;
5602 }
99018f42 5603
85f10a01
MM		 5604 /* If there is an extension opcode to put here, the
5605 register number must be put into the regmem field. */
c0209578
L		 5606 if (i.tm.extension_opcode != None)
5607 {
5608 i.rm.regmem = i.op[op].regs->reg_num;
5609 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5610 i.rex |= REX_B;
5611 }
5612 else
5613 {
5614 i.rm.reg = i.op[op].regs->reg_num;
5615 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5616 i.rex |= REX_R;
5617 }
85f10a01 5618 }
252b5132 5619
29b0f896
AM		 5620 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5621 must set it to 3 to indicate this is a register operand
5622 in the regmem field. */
5623 if (!i.mem_operands)
5624 i.rm.mode = 3;
5625 }
252b5132 5626
29b0f896 5627 /* Fill in i.rm.reg field with extension opcode (if any). */
85f10a01
MM		 5628 if (i.tm.extension_opcode != None
5629 && !(i.tm.opcode_modifier.drex
5630 || i.tm.opcode_modifier.drexv
5631 || i.tm.opcode_modifier.drexc))
29b0f896
AM		 5632 i.rm.reg = i.tm.extension_opcode;
5633 }
5634 return default_seg;
5635}
252b5132 5636
29b0f896 5637static void
e3bb37b5 5638output_branch (void)
29b0f896
AM		 5639{
5640 char *p;
5641 int code16;
5642 int prefix;
5643 relax_substateT subtype;
5644 symbolS *sym;
5645 offsetT off;
5646
5647 code16 = 0;
5648 if (flag_code == CODE_16BIT)
5649 code16 = CODE16;
5650
5651 prefix = 0;
5652 if (i.prefix[DATA_PREFIX] != 0)
252b5132 5653 {
29b0f896
AM		 5654 prefix = 1;
5655 i.prefixes -= 1;
5656 code16 ^= CODE16;
252b5132 5657 }
29b0f896
AM		 5658 /* Pentium4 branch hints. */
5659 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5660 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2f66722d 5661 {
29b0f896
AM		 5662 prefix++;
5663 i.prefixes--;
5664 }
5665 if (i.prefix[REX_PREFIX] != 0)
5666 {
5667 prefix++;
5668 i.prefixes--;
2f66722d
AM		 5669 }
5670
29b0f896
AM		 5671 if (i.prefixes != 0 && !intel_syntax)
5672 as_warn (_("skipping prefixes on this instruction"));
5673
5674 /* It's always a symbol; End frag & setup for relax.
5675 Make sure there is enough room in this frag for the largest
5676 instruction we may generate in md_convert_frag. This is 2
5677 bytes for the opcode and room for the prefix and largest
5678 displacement. */
5679 frag_grow (prefix + 2 + 4);
5680 /* Prefix and 1 opcode byte go in fr_fix. */
5681 p = frag_more (prefix + 1);
5682 if (i.prefix[DATA_PREFIX] != 0)
5683 *p++ = DATA_PREFIX_OPCODE;
5684 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
5685 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
5686 *p++ = i.prefix[SEG_PREFIX];
5687 if (i.prefix[REX_PREFIX] != 0)
5688 *p++ = i.prefix[REX_PREFIX];
5689 *p = i.tm.base_opcode;
5690
5691 if ((unsigned char) *p == JUMP_PC_RELATIVE)
5692 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
40fb9820 5693 else if (cpu_arch_flags.bitfield.cpui386)
29b0f896
AM		 5694 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
5695 else
5696 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
5697 subtype |= code16;
3e73aa7c 5698
29b0f896
AM		 5699 sym = i.op[0].disps->X_add_symbol;
5700 off = i.op[0].disps->X_add_number;
3e73aa7c 5701
29b0f896
AM		 5702 if (i.op[0].disps->X_op != O_constant
5703 && i.op[0].disps->X_op != O_symbol)
3e73aa7c 5704 {
29b0f896
AM		 5705 /* Handle complex expressions. */
5706 sym = make_expr_symbol (i.op[0].disps);
5707 off = 0;
5708 }
3e73aa7c 5709
29b0f896
AM		 5710 /* 1 possible extra opcode + 4 byte displacement go in var part.
5711 Pass reloc in fr_var. */
5712 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
5713}
3e73aa7c 5714
29b0f896 5715static void
e3bb37b5 5716output_jump (void)
29b0f896
AM		 5717{
5718 char *p;
5719 int size;
3e02c1cc 5720 fixS *fixP;
29b0f896 5721
40fb9820 5722 if (i.tm.opcode_modifier.jumpbyte)
29b0f896
AM		 5723 {
5724 /* This is a loop or jecxz type instruction. */
5725 size = 1;
5726 if (i.prefix[ADDR_PREFIX] != 0)
5727 {
5728 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
5729 i.prefixes -= 1;
5730 }
5731 /* Pentium4 branch hints. */
5732 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
5733 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
5734 {
5735 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
5736 i.prefixes--;
3e73aa7c
JH		 5737 }
5738 }
29b0f896
AM		 5739 else
5740 {
5741 int code16;
3e73aa7c 5742
29b0f896
AM		 5743 code16 = 0;
5744 if (flag_code == CODE_16BIT)
5745 code16 = CODE16;
3e73aa7c 5746
29b0f896
AM		 5747 if (i.prefix[DATA_PREFIX] != 0)
5748 {
5749 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
5750 i.prefixes -= 1;
5751 code16 ^= CODE16;
5752 }
252b5132 5753
29b0f896
AM		 5754 size = 4;
5755 if (code16)
5756 size = 2;
5757 }
9fcc94b6 5758
29b0f896
AM		 5759 if (i.prefix[REX_PREFIX] != 0)
5760 {
5761 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
5762 i.prefixes -= 1;
5763 }
252b5132 5764
29b0f896
AM		 5765 if (i.prefixes != 0 && !intel_syntax)
5766 as_warn (_("skipping prefixes on this instruction"));
e0890092 5767
29b0f896
AM		 5768 p = frag_more (1 + size);
5769 *p++ = i.tm.base_opcode;
e0890092 5770
3e02c1cc
AM		 5771 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5772 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
5773
5774 /* All jumps handled here are signed, but don't use a signed limit
5775 check for 32 and 16 bit jumps as we want to allow wrap around at
5776 4G and 64k respectively. */
5777 if (size == 1)
5778 fixP->fx_signed = 1;
29b0f896 5779}
e0890092 5780
29b0f896 5781static void
e3bb37b5 5782output_interseg_jump (void)
29b0f896
AM		 5783{
5784 char *p;
5785 int size;
5786 int prefix;
5787 int code16;
252b5132 5788
29b0f896
AM		 5789 code16 = 0;
5790 if (flag_code == CODE_16BIT)
5791 code16 = CODE16;
a217f122 5792
29b0f896
AM		 5793 prefix = 0;
5794 if (i.prefix[DATA_PREFIX] != 0)
5795 {
5796 prefix = 1;
5797 i.prefixes -= 1;
5798 code16 ^= CODE16;
5799 }
5800 if (i.prefix[REX_PREFIX] != 0)
5801 {
5802 prefix++;
5803 i.prefixes -= 1;
5804 }
252b5132 5805
29b0f896
AM		 5806 size = 4;
5807 if (code16)
5808 size = 2;
252b5132 5809
29b0f896
AM		 5810 if (i.prefixes != 0 && !intel_syntax)
5811 as_warn (_("skipping prefixes on this instruction"));
252b5132 5812
29b0f896
AM		 5813 /* 1 opcode; 2 segment; offset */
5814 p = frag_more (prefix + 1 + 2 + size);
3e73aa7c 5815
29b0f896
AM		 5816 if (i.prefix[DATA_PREFIX] != 0)
5817 *p++ = DATA_PREFIX_OPCODE;
252b5132 5818
29b0f896
AM		 5819 if (i.prefix[REX_PREFIX] != 0)
5820 *p++ = i.prefix[REX_PREFIX];
252b5132 5821
29b0f896
AM		 5822 *p++ = i.tm.base_opcode;
5823 if (i.op[1].imms->X_op == O_constant)
5824 {
5825 offsetT n = i.op[1].imms->X_add_number;
252b5132 5826
29b0f896
AM		 5827 if (size == 2
5828 && !fits_in_unsigned_word (n)
5829 && !fits_in_signed_word (n))
5830 {
5831 as_bad (_("16-bit jump out of range"));
5832 return;
5833 }
5834 md_number_to_chars (p, n, size);
5835 }
5836 else
5837 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
5838 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
5839 if (i.op[0].imms->X_op != O_constant)
5840 as_bad (_("can't handle non absolute segment in `%s'"),
5841 i.tm.name);
5842 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
5843}
a217f122 5844
29b0f896 5845static void
e3bb37b5 5846output_insn (void)
29b0f896 5847{
2bbd9c25
JJ		 5848 fragS *insn_start_frag;
5849 offsetT insn_start_off;
5850
29b0f896
AM		 5851 /* Tie dwarf2 debug info to the address at the start of the insn.
5852 We can't do this after the insn has been output as the current
5853 frag may have been closed off. eg. by frag_var. */
5854 dwarf2_emit_insn (0);
5855
2bbd9c25
JJ		 5856 insn_start_frag = frag_now;
5857 insn_start_off = frag_now_fix ();
5858
29b0f896 5859 /* Output jumps. */
40fb9820 5860 if (i.tm.opcode_modifier.jump)
29b0f896 5861 output_branch ();
40fb9820
L		 5862 else if (i.tm.opcode_modifier.jumpbyte
5863 || i.tm.opcode_modifier.jumpdword)
29b0f896 5864 output_jump ();
40fb9820 5865 else if (i.tm.opcode_modifier.jumpintersegment)
29b0f896
AM		 5866 output_interseg_jump ();
5867 else
5868 {
5869 /* Output normal instructions here. */
5870 char *p;
5871 unsigned char *q;
47465058 5872 unsigned int j;
331d2d0d 5873 unsigned int prefix;
4dffcebc 5874
c0f3af97
L		 5875 /* Since the VEX prefix contains the implicit prefix, we don't
5876 need the explicit prefix. */
5877 if (!i.tm.opcode_modifier.vex)
bc4bd9ab 5878 {
c0f3af97 5879 switch (i.tm.opcode_length)
bc4bd9ab 5880 {
c0f3af97
L		 5881 case 3:
5882 if (i.tm.base_opcode & 0xff000000)
4dffcebc 5883 {
c0f3af97
L		 5884 prefix = (i.tm.base_opcode >> 24) & 0xff;
5885 goto check_prefix;
5886 }
5887 break;
5888 case 2:
5889 if ((i.tm.base_opcode & 0xff0000) != 0)
5890 {
5891 prefix = (i.tm.base_opcode >> 16) & 0xff;
5892 if (i.tm.cpu_flags.bitfield.cpupadlock)
5893 {
4dffcebc 5894check_prefix:
c0f3af97
L		 5895 if (prefix != REPE_PREFIX_OPCODE
5896 || (i.prefix[LOCKREP_PREFIX]
5897 != REPE_PREFIX_OPCODE))
5898 add_prefix (prefix);
5899 }
5900 else
4dffcebc
L		 5901 add_prefix (prefix);
5902 }
c0f3af97
L		 5903 break;
5904 case 1:
5905 break;
5906 default:
5907 abort ();
bc4bd9ab 5908 }
c0f3af97
L		 5909
5910 /* The prefix bytes. */
5911 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
5912 if (*q)
5913 FRAG_APPEND_1_CHAR (*q);
0f10071e 5914 }
252b5132 5915
c0f3af97
L		 5916 if (i.tm.opcode_modifier.vex)
5917 {
5918 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
5919 if (*q)
5920 switch (j)
5921 {
5922 case REX_PREFIX:
5923 /* REX byte is encoded in VEX prefix. */
5924 break;
5925 case SEG_PREFIX:
5926 case ADDR_PREFIX:
5927 FRAG_APPEND_1_CHAR (*q);
5928 break;
5929 default:
5930 /* There should be no other prefixes for instructions
5931 with VEX prefix. */
5932 abort ();
5933 }
5934
5935 /* Now the VEX prefix. */
5936 p = frag_more (i.vex.length);
5937 for (j = 0; j < i.vex.length; j++)
5938 p[j] = i.vex.bytes[j];
5939 }
252b5132 5940
29b0f896 5941 /* Now the opcode; be careful about word order here! */
4dffcebc 5942 if (i.tm.opcode_length == 1)
29b0f896
AM		 5943 {
5944 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
5945 }
5946 else
5947 {
4dffcebc 5948 switch (i.tm.opcode_length)
331d2d0d 5949 {
4dffcebc 5950 case 3:
331d2d0d
L		 5951 p = frag_more (3);
5952 *p++ = (i.tm.base_opcode >> 16) & 0xff;
4dffcebc
L		 5953 break;
5954 case 2:
5955 p = frag_more (2);
5956 break;
5957 default:
5958 abort ();
5959 break;
331d2d0d 5960 }
0f10071e 5961
29b0f896
AM		 5962 /* Put out high byte first: can't use md_number_to_chars! */
5963 *p++ = (i.tm.base_opcode >> 8) & 0xff;
5964 *p = i.tm.base_opcode & 0xff;
85f10a01
MM		 5965
5966 /* On SSE5, encode the OC1 bit in the DREX field if this
5967 encoding has multiple formats. */
5968 if (i.tm.opcode_modifier.drex
5969 && i.tm.opcode_modifier.drexv
5970 && DREX_OC1 (i.tm.extension_opcode))
5971 *p |= DREX_OC1_MASK;
29b0f896 5972 }
3e73aa7c 5973
29b0f896 5974 /* Now the modrm byte and sib byte (if present). */
40fb9820 5975 if (i.tm.opcode_modifier.modrm)
29b0f896 5976 {
4a3523fa
L		 5977 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
5978 | i.rm.reg << 3
5979 | i.rm.mode << 6));
29b0f896
AM		 5980 /* If i.rm.regmem == ESP (4)
5981 && i.rm.mode != (Register mode)
5982 && not 16 bit
5983 ==> need second modrm byte. */
5984 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
5985 && i.rm.mode != 3
40fb9820 5986 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
4a3523fa
L		 5987 FRAG_APPEND_1_CHAR ((i.sib.base << 0
5988 | i.sib.index << 3
5989 | i.sib.scale << 6));
29b0f896 5990 }
3e73aa7c 5991
85f10a01
MM		 5992 /* Write the DREX byte if needed. */
5993 if (i.tm.opcode_modifier.drex || i.tm.opcode_modifier.drexc)
5994 {
5995 p = frag_more (1);
5996 *p = (((i.drex.reg & 0xf) << 4) | (i.drex.rex & 0x7));
5997
5998 /* Encode the OC0 bit if this encoding has multiple
5999 formats. */
6000 if ((i.tm.opcode_modifier.drex
6001 || i.tm.opcode_modifier.drexv)
6002 && DREX_OC0 (i.tm.extension_opcode))
6003 *p |= DREX_OC0_MASK;
6004 }
6005
29b0f896 6006 if (i.disp_operands)
2bbd9c25 6007 output_disp (insn_start_frag, insn_start_off);
3e73aa7c 6008
29b0f896 6009 if (i.imm_operands)
2bbd9c25 6010 output_imm (insn_start_frag, insn_start_off);
29b0f896 6011 }
252b5132 6012
29b0f896
AM		 6013#ifdef DEBUG386
6014 if (flag_debug)
6015 {
7b81dfbb 6016 pi ("" /*line*/, &i);
29b0f896
AM		 6017 }
6018#endif /* DEBUG386 */
6019}
252b5132 6020
e205caa7
L		 6021/* Return the size of the displacement operand N. */
6022
6023static int
6024disp_size (unsigned int n)
6025{
6026 int size = 4;
40fb9820
L		 6027 if (i.types[n].bitfield.disp64)
6028 size = 8;
6029 else if (i.types[n].bitfield.disp8)
6030 size = 1;
6031 else if (i.types[n].bitfield.disp16)
6032 size = 2;
e205caa7
L		 6033 return size;
6034}
6035
6036/* Return the size of the immediate operand N. */
6037
6038static int
6039imm_size (unsigned int n)
6040{
6041 int size = 4;
40fb9820
L		 6042 if (i.types[n].bitfield.imm64)
6043 size = 8;
6044 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
6045 size = 1;
6046 else if (i.types[n].bitfield.imm16)
6047 size = 2;
e205caa7
L		 6048 return size;
6049}
6050
29b0f896 6051static void
64e74474 6052output_disp (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6053{
6054 char *p;
6055 unsigned int n;
252b5132 6056
29b0f896
AM		 6057 for (n = 0; n < i.operands; n++)
6058 {
40fb9820 6059 if (operand_type_check (i.types[n], disp))
29b0f896
AM		 6060 {
6061 if (i.op[n].disps->X_op == O_constant)
6062 {
e205caa7 6063 int size = disp_size (n);
29b0f896 6064 offsetT val;
252b5132 6065
29b0f896
AM		 6066 val = offset_in_range (i.op[n].disps->X_add_number,
6067 size);
6068 p = frag_more (size);
6069 md_number_to_chars (p, val, size);
6070 }
6071 else
6072 {
f86103b7 6073 enum bfd_reloc_code_real reloc_type;
e205caa7 6074 int size = disp_size (n);
40fb9820 6075 int sign = i.types[n].bitfield.disp32s;
29b0f896
AM		 6076 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
6077
e205caa7 6078 /* We can't have 8 bit displacement here. */
40fb9820 6079 assert (!i.types[n].bitfield.disp8);
e205caa7 6080
29b0f896
AM		 6081 /* The PC relative address is computed relative
6082 to the instruction boundary, so in case immediate
6083 fields follows, we need to adjust the value. */
6084 if (pcrel && i.imm_operands)
6085 {
29b0f896 6086 unsigned int n1;
e205caa7 6087 int sz = 0;
252b5132 6088
29b0f896 6089 for (n1 = 0; n1 < i.operands; n1++)
40fb9820 6090 if (operand_type_check (i.types[n1], imm))
252b5132 6091 {
e205caa7
L		 6092 /* Only one immediate is allowed for PC
6093 relative address. */
6094 assert (sz == 0);
6095 sz = imm_size (n1);
6096 i.op[n].disps->X_add_number -= sz;
252b5132 6097 }
29b0f896 6098 /* We should find the immediate. */
e205caa7 6099 assert (sz != 0);
29b0f896 6100 }
520dc8e8 6101
29b0f896 6102 p = frag_more (size);
2bbd9c25 6103 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
d6ab8113 6104 if (GOT_symbol
2bbd9c25 6105 && GOT_symbol == i.op[n].disps->X_add_symbol
d6ab8113 6106 && (((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6107 || reloc_type == BFD_RELOC_X86_64_32S
6108 || (reloc_type == BFD_RELOC_64
6109 && object_64bit))
d6ab8113
JB		 6110 && (i.op[n].disps->X_op == O_symbol
6111 || (i.op[n].disps->X_op == O_add
6112 && ((symbol_get_value_expression
6113 (i.op[n].disps->X_op_symbol)->X_op)
6114 == O_subtract))))
6115 || reloc_type == BFD_RELOC_32_PCREL))
2bbd9c25
JJ		 6116 {
6117 offsetT add;
6118
6119 if (insn_start_frag == frag_now)
6120 add = (p - frag_now->fr_literal) - insn_start_off;
6121 else
6122 {
6123 fragS *fr;
6124
6125 add = insn_start_frag->fr_fix - insn_start_off;
6126 for (fr = insn_start_frag->fr_next;
6127 fr && fr != frag_now; fr = fr->fr_next)
6128 add += fr->fr_fix;
6129 add += p - frag_now->fr_literal;
6130 }
6131
4fa24527 6132 if (!object_64bit)
7b81dfbb
AJ		 6133 {
6134 reloc_type = BFD_RELOC_386_GOTPC;
6135 i.op[n].imms->X_add_number += add;
6136 }
6137 else if (reloc_type == BFD_RELOC_64)
6138 reloc_type = BFD_RELOC_X86_64_GOTPC64;
d6ab8113 6139 else
7b81dfbb
AJ		 6140 /* Don't do the adjustment for x86-64, as there
6141 the pcrel addressing is relative to the _next_
6142 insn, and that is taken care of in other code. */
d6ab8113 6143 reloc_type = BFD_RELOC_X86_64_GOTPC32;
2bbd9c25 6144 }
062cd5e7 6145 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
2bbd9c25 6146 i.op[n].disps, pcrel, reloc_type);
29b0f896
AM		 6147 }
6148 }
6149 }
6150}
252b5132 6151
29b0f896 6152static void
64e74474 6153output_imm (fragS *insn_start_frag, offsetT insn_start_off)
29b0f896
AM		 6154{
6155 char *p;
6156 unsigned int n;
252b5132 6157
29b0f896
AM		 6158 for (n = 0; n < i.operands; n++)
6159 {
40fb9820 6160 if (operand_type_check (i.types[n], imm))
29b0f896
AM		 6161 {
6162 if (i.op[n].imms->X_op == O_constant)
6163 {
e205caa7 6164 int size = imm_size (n);
29b0f896 6165 offsetT val;
b4cac588 6166
29b0f896
AM		 6167 val = offset_in_range (i.op[n].imms->X_add_number,
6168 size);
6169 p = frag_more (size);
6170 md_number_to_chars (p, val, size);
6171 }
6172 else
6173 {
6174 /* Not absolute_section.
6175 Need a 32-bit fixup (don't support 8bit
6176 non-absolute imms). Try to support other
6177 sizes ... */
f86103b7 6178 enum bfd_reloc_code_real reloc_type;
e205caa7
L		 6179 int size = imm_size (n);
6180 int sign;
29b0f896 6181
40fb9820 6182 if (i.types[n].bitfield.imm32s
a7d61044 6183 && (i.suffix == QWORD_MNEM_SUFFIX
40fb9820 6184 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
29b0f896 6185 sign = 1;
e205caa7
L		 6186 else
6187 sign = 0;
520dc8e8 6188
29b0f896
AM		 6189 p = frag_more (size);
6190 reloc_type = reloc (size, 0, sign, i.reloc[n]);
f86103b7 6191
2bbd9c25
JJ		 6192 /* This is tough to explain. We end up with this one if we
6193 * have operands that look like
6194 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6195 * obtain the absolute address of the GOT, and it is strongly
6196 * preferable from a performance point of view to avoid using
6197 * a runtime relocation for this. The actual sequence of
6198 * instructions often look something like:
6199 *
6200 * call .L66
6201 * .L66:
6202 * popl %ebx
6203 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6204 *
6205 * The call and pop essentially return the absolute address
6206 * of the label .L66 and store it in %ebx. The linker itself
6207 * will ultimately change the first operand of the addl so
6208 * that %ebx points to the GOT, but to keep things simple, the
6209 * .o file must have this operand set so that it generates not
6210 * the absolute address of .L66, but the absolute address of
6211 * itself. This allows the linker itself simply treat a GOTPC
6212 * relocation as asking for a pcrel offset to the GOT to be
6213 * added in, and the addend of the relocation is stored in the
6214 * operand field for the instruction itself.
6215 *
6216 * Our job here is to fix the operand so that it would add
6217 * the correct offset so that %ebx would point to itself. The
6218 * thing that is tricky is that .-.L66 will point to the
6219 * beginning of the instruction, so we need to further modify
6220 * the operand so that it will point to itself. There are
6221 * other cases where you have something like:
6222 *
6223 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6224 *
6225 * and here no correction would be required. Internally in
6226 * the assembler we treat operands of this form as not being
6227 * pcrel since the '.' is explicitly mentioned, and I wonder
6228 * whether it would simplify matters to do it this way. Who
6229 * knows. In earlier versions of the PIC patches, the
6230 * pcrel_adjust field was used to store the correction, but
6231 * since the expression is not pcrel, I felt it would be
6232 * confusing to do it this way. */
6233
d6ab8113 6234 if ((reloc_type == BFD_RELOC_32
7b81dfbb
AJ		 6235 || reloc_type == BFD_RELOC_X86_64_32S
6236 || reloc_type == BFD_RELOC_64)
29b0f896
AM		 6237 && GOT_symbol
6238 && GOT_symbol == i.op[n].imms->X_add_symbol
6239 && (i.op[n].imms->X_op == O_symbol
6240 || (i.op[n].imms->X_op == O_add
6241 && ((symbol_get_value_expression
6242 (i.op[n].imms->X_op_symbol)->X_op)
6243 == O_subtract))))
6244 {
2bbd9c25
JJ		 6245 offsetT add;
6246
6247 if (insn_start_frag == frag_now)
6248 add = (p - frag_now->fr_literal) - insn_start_off;
6249 else
6250 {
6251 fragS *fr;
6252
6253 add = insn_start_frag->fr_fix - insn_start_off;
6254 for (fr = insn_start_frag->fr_next;
6255 fr && fr != frag_now; fr = fr->fr_next)
6256 add += fr->fr_fix;
6257 add += p - frag_now->fr_literal;
6258 }
6259
4fa24527 6260 if (!object_64bit)
d6ab8113 6261 reloc_type = BFD_RELOC_386_GOTPC;
7b81dfbb 6262 else if (size == 4)
d6ab8113 6263 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7b81dfbb
AJ		 6264 else if (size == 8)
6265 reloc_type = BFD_RELOC_X86_64_GOTPC64;
2bbd9c25 6266 i.op[n].imms->X_add_number += add;
29b0f896 6267 }
29b0f896
AM		 6268 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6269 i.op[n].imms, 0, reloc_type);
6270 }
6271 }
6272 }
252b5132
RH		 6273}
6274\f
d182319b
JB		 6275/* x86_cons_fix_new is called via the expression parsing code when a
6276 reloc is needed. We use this hook to get the correct .got reloc. */
6277static enum bfd_reloc_code_real got_reloc = NO_RELOC;
6278static int cons_sign = -1;
6279
6280void
e3bb37b5 6281x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
64e74474 6282 expressionS *exp)
d182319b
JB		 6283{
6284 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc);
6285
6286 got_reloc = NO_RELOC;
6287
6288#ifdef TE_PE
6289 if (exp->X_op == O_secrel)
6290 {
6291 exp->X_op = O_symbol;
6292 r = BFD_RELOC_32_SECREL;
6293 }
6294#endif
6295
6296 fix_new_exp (frag, off, len, exp, 0, r);
6297}
6298
718ddfc0
JB		 6299#if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6300# define lex_got(reloc, adjust, types) NULL
6301#else
f3c180ae
AM		 6302/* Parse operands of the form
6303 <symbol>@GOTOFF+<nnn>
6304 and similar .plt or .got references.
6305
6306 If we find one, set up the correct relocation in RELOC and copy the
6307 input string, minus the `@GOTOFF' into a malloc'd buffer for
6308 parsing by the calling routine. Return this buffer, and if ADJUST
6309 is non-null set it to the length of the string we removed from the
6310 input line. Otherwise return NULL. */
6311static char *
3956db08 6312lex_got (enum bfd_reloc_code_real *reloc,
64e74474 6313 int *adjust,
40fb9820 6314 i386_operand_type *types)
f3c180ae 6315{
7b81dfbb
AJ		 6316 /* Some of the relocations depend on the size of what field is to
6317 be relocated. But in our callers i386_immediate and i386_displacement
6318 we don't yet know the operand size (this will be set by insn
6319 matching). Hence we record the word32 relocation here,
6320 and adjust the reloc according to the real size in reloc(). */
f3c180ae
AM		 6321 static const struct {
6322 const char *str;
4fa24527 6323 const enum bfd_reloc_code_real rel[2];
40fb9820 6324 const i386_operand_type types64;
f3c180ae 6325 } gotrel[] = {
4eed87de
AM		 6326 { "PLTOFF", { 0,
6327 BFD_RELOC_X86_64_PLTOFF64 },
40fb9820 6328 OPERAND_TYPE_IMM64 },
4eed87de
AM		 6329 { "PLT", { BFD_RELOC_386_PLT32,
6330 BFD_RELOC_X86_64_PLT32 },
40fb9820 6331 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6332 { "GOTPLT", { 0,
6333 BFD_RELOC_X86_64_GOTPLT64 },
40fb9820 6334 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6335 { "GOTOFF", { BFD_RELOC_386_GOTOFF,
6336 BFD_RELOC_X86_64_GOTOFF64 },
40fb9820 6337 OPERAND_TYPE_IMM64_DISP64 },
4eed87de
AM		 6338 { "GOTPCREL", { 0,
6339 BFD_RELOC_X86_64_GOTPCREL },
40fb9820 6340 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6341 { "TLSGD", { BFD_RELOC_386_TLS_GD,
6342 BFD_RELOC_X86_64_TLSGD },
40fb9820 6343 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6344 { "TLSLDM", { BFD_RELOC_386_TLS_LDM,
6345 0 },
40fb9820 6346 OPERAND_TYPE_NONE },
4eed87de
AM		 6347 { "TLSLD", { 0,
6348 BFD_RELOC_X86_64_TLSLD },
40fb9820 6349 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6350 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32,
6351 BFD_RELOC_X86_64_GOTTPOFF },
40fb9820 6352 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6353 { "TPOFF", { BFD_RELOC_386_TLS_LE_32,
6354 BFD_RELOC_X86_64_TPOFF32 },
40fb9820 6355 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6356 { "NTPOFF", { BFD_RELOC_386_TLS_LE,
6357 0 },
40fb9820 6358 OPERAND_TYPE_NONE },
4eed87de
AM		 6359 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32,
6360 BFD_RELOC_X86_64_DTPOFF32 },
40fb9820
L		 6361
6362 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
4eed87de
AM		 6363 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE,
6364 0 },
40fb9820 6365 OPERAND_TYPE_NONE },
4eed87de
AM		 6366 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE,
6367 0 },
40fb9820 6368 OPERAND_TYPE_NONE },
4eed87de
AM		 6369 { "GOT", { BFD_RELOC_386_GOT32,
6370 BFD_RELOC_X86_64_GOT32 },
40fb9820 6371 OPERAND_TYPE_IMM32_32S_64_DISP32 },
4eed87de
AM		 6372 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC,
6373 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
40fb9820 6374 OPERAND_TYPE_IMM32_32S_DISP32 },
4eed87de
AM		 6375 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL,
6376 BFD_RELOC_X86_64_TLSDESC_CALL },
40fb9820 6377 OPERAND_TYPE_IMM32_32S_DISP32 },
f3c180ae
AM		 6378 };
6379 char *cp;
6380 unsigned int j;
6381
718ddfc0
JB		 6382 if (!IS_ELF)
6383 return NULL;
6384
f3c180ae 6385 for (cp = input_line_pointer; *cp != '@'; cp++)
67c11a9b 6386 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
f3c180ae
AM		 6387 return NULL;
6388
47465058 6389 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
f3c180ae
AM		 6390 {
6391 int len;
6392
6393 len = strlen (gotrel[j].str);
28f81592 6394 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
f3c180ae 6395 {
4fa24527 6396 if (gotrel[j].rel[object_64bit] != 0)
f3c180ae 6397 {
28f81592
AM		 6398 int first, second;
6399 char *tmpbuf, *past_reloc;
f3c180ae 6400
4fa24527 6401 *reloc = gotrel[j].rel[object_64bit];
28f81592
AM		 6402 if (adjust)
6403 *adjust = len;
f3c180ae 6404
3956db08
JB		 6405 if (types)
6406 {
6407 if (flag_code != CODE_64BIT)
40fb9820
L		 6408 {
6409 types->bitfield.imm32 = 1;
6410 types->bitfield.disp32 = 1;
6411 }
3956db08
JB		 6412 else
6413 *types = gotrel[j].types64;
6414 }
6415
f3c180ae
AM		 6416 if (GOT_symbol == NULL)
6417 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
6418
28f81592 6419 /* The length of the first part of our input line. */
f3c180ae 6420 first = cp - input_line_pointer;
28f81592
AM		 6421
6422 /* The second part goes from after the reloc token until
67c11a9b 6423 (and including) an end_of_line char or comma. */
28f81592 6424 past_reloc = cp + 1 + len;
67c11a9b
AM		 6425 cp = past_reloc;
6426 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
6427 ++cp;
6428 second = cp + 1 - past_reloc;
28f81592
AM		 6429
6430 /* Allocate and copy string. The trailing NUL shouldn't
6431 be necessary, but be safe. */
6432 tmpbuf = xmalloc (first + second + 2);
f3c180ae 6433 memcpy (tmpbuf, input_line_pointer, first);
0787a12d
AM		 6434 if (second != 0 && *past_reloc != ' ')
6435 /* Replace the relocation token with ' ', so that
6436 errors like foo@GOTOFF1 will be detected. */
6437 tmpbuf[first++] = ' ';
6438 memcpy (tmpbuf + first, past_reloc, second);
6439 tmpbuf[first + second] = '\0';
f3c180ae
AM		 6440 return tmpbuf;
6441 }
6442
4fa24527
JB		 6443 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6444 gotrel[j].str, 1 << (5 + object_64bit));
f3c180ae
AM		 6445 return NULL;
6446 }
6447 }
6448
6449 /* Might be a symbol version string. Don't as_bad here. */
6450 return NULL;
6451}
6452
f3c180ae 6453void
e3bb37b5 6454x86_cons (expressionS *exp, int size)
f3c180ae 6455{
4fa24527 6456 if (size == 4 || (object_64bit && size == 8))
f3c180ae
AM		 6457 {
6458 /* Handle @GOTOFF and the like in an expression. */
6459 char *save;
6460 char *gotfree_input_line;
6461 int adjust;
6462
6463 save = input_line_pointer;
3956db08 6464 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL);
f3c180ae
AM		 6465 if (gotfree_input_line)
6466 input_line_pointer = gotfree_input_line;
6467
6468 expression (exp);
6469
6470 if (gotfree_input_line)
6471 {
6472 /* expression () has merrily parsed up to the end of line,
6473 or a comma - in the wrong buffer. Transfer how far
6474 input_line_pointer has moved to the right buffer. */
6475 input_line_pointer = (save
6476 + (input_line_pointer - gotfree_input_line)
6477 + adjust);
6478 free (gotfree_input_line);
3992d3b7
AM		 6479 if (exp->X_op == O_constant
6480 || exp->X_op == O_absent
6481 || exp->X_op == O_illegal
6482 || exp->X_op == O_register
6483 || exp->X_op == O_big)
6484 {
6485 char c = *input_line_pointer;
6486 *input_line_pointer = 0;
6487 as_bad (_("missing or invalid expression `%s'"), save);
6488 *input_line_pointer = c;
6489 }
f3c180ae
AM		 6490 }
6491 }
6492 else
6493 expression (exp);
6494}
6495#endif
6496
d182319b 6497static void signed_cons (int size)
6482c264 6498{
d182319b
JB		 6499 if (flag_code == CODE_64BIT)
6500 cons_sign = 1;
6501 cons (size);
6502 cons_sign = -1;
6482c264
NC		 6503}
6504
d182319b 6505#ifdef TE_PE
6482c264
NC		 6506static void
6507pe_directive_secrel (dummy)
6508 int dummy ATTRIBUTE_UNUSED;
6509{
6510 expressionS exp;
6511
6512 do
6513 {
6514 expression (&exp);
6515 if (exp.X_op == O_symbol)
6516 exp.X_op = O_secrel;
6517
6518 emit_expr (&exp, 4);
6519 }
6520 while (*input_line_pointer++ == ',');
6521
6522 input_line_pointer--;
6523 demand_empty_rest_of_line ();
6524}
6482c264
NC		 6525#endif
6526
252b5132 6527static int
70e41ade 6528i386_immediate (char *imm_start)
252b5132
RH		 6529{
6530 char *save_input_line_pointer;
f3c180ae 6531 char *gotfree_input_line;
252b5132 6532 segT exp_seg = 0;
47926f60 6533 expressionS *exp;
40fb9820
L		 6534 i386_operand_type types;
6535
0dfbf9d7 6536 operand_type_set (&types, ~0);
252b5132
RH		 6537
6538 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
6539 {
31b2323c
L		 6540 as_bad (_("at most %d immediate operands are allowed"),
6541 MAX_IMMEDIATE_OPERANDS);
252b5132
RH		 6542 return 0;
6543 }
6544
6545 exp = &im_expressions[i.imm_operands++];
520dc8e8 6546 i.op[this_operand].imms = exp;
252b5132
RH		 6547
6548 if (is_space_char (*imm_start))
6549 ++imm_start;
6550
6551 save_input_line_pointer = input_line_pointer;
6552 input_line_pointer = imm_start;
6553
3956db08 6554 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6555 if (gotfree_input_line)
6556 input_line_pointer = gotfree_input_line;
252b5132
RH		 6557
6558 exp_seg = expression (exp);
6559
83183c0c 6560 SKIP_WHITESPACE ();
252b5132 6561 if (*input_line_pointer)
f3c180ae 6562 as_bad (_("junk `%s' after expression"), input_line_pointer);
252b5132
RH		 6563
6564 input_line_pointer = save_input_line_pointer;
f3c180ae
AM		 6565 if (gotfree_input_line)
6566 free (gotfree_input_line);
252b5132 6567
3992d3b7
AM		 6568 if (exp->X_op == O_absent
6569 || exp->X_op == O_illegal
6570 || exp->X_op == O_big
6571 || (gotfree_input_line
6572 && (exp->X_op == O_constant
6573 || exp->X_op == O_register)))
252b5132 6574 {
3992d3b7 6575 as_bad (_("missing or invalid immediate expression `%s'"),
24eab124 6576 imm_start);
3992d3b7 6577 return 0;
252b5132 6578 }
3e73aa7c 6579 else if (exp->X_op == O_constant)
252b5132 6580 {
47926f60 6581 /* Size it properly later. */
40fb9820 6582 i.types[this_operand].bitfield.imm64 = 1;
3e73aa7c 6583 /* If BFD64, sign extend val. */
4eed87de
AM		 6584 if (!use_rela_relocations
6585 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
6586 exp->X_add_number
6587 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
252b5132 6588 }
4c63da97 6589#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
f86103b7 6590 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
31312f95 6591 && exp_seg != absolute_section
47926f60 6592 && exp_seg != text_section
24eab124
AM		 6593 && exp_seg != data_section
6594 && exp_seg != bss_section
6595 && exp_seg != undefined_section
f86103b7 6596 && !bfd_is_com_section (exp_seg))
252b5132 6597 {
d0b47220 6598 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
252b5132
RH		 6599 return 0;
6600 }
6601#endif
bb8f5920
L		 6602 else if (!intel_syntax && exp->X_op == O_register)
6603 {
6604 as_bad (_("illegal immediate register operand %s"), imm_start);
6605 return 0;
6606 }
252b5132
RH		 6607 else
6608 {
6609 /* This is an address. The size of the address will be
24eab124 6610 determined later, depending on destination register,
3e73aa7c 6611 suffix, or the default for the section. */
40fb9820
L		 6612 i.types[this_operand].bitfield.imm8 = 1;
6613 i.types[this_operand].bitfield.imm16 = 1;
6614 i.types[this_operand].bitfield.imm32 = 1;
6615 i.types[this_operand].bitfield.imm32s = 1;
6616 i.types[this_operand].bitfield.imm64 = 1;
c6fb90c8
L		 6617 i.types[this_operand] = operand_type_and (i.types[this_operand],
6618 types);
252b5132
RH		 6619 }
6620
6621 return 1;
6622}
6623
551c1ca1 6624static char *
e3bb37b5 6625i386_scale (char *scale)
252b5132 6626{
551c1ca1
AM		 6627 offsetT val;
6628 char *save = input_line_pointer;
252b5132 6629
551c1ca1
AM		 6630 input_line_pointer = scale;
6631 val = get_absolute_expression ();
6632
6633 switch (val)
252b5132 6634 {
551c1ca1 6635 case 1:
252b5132
RH		 6636 i.log2_scale_factor = 0;
6637 break;
551c1ca1 6638 case 2:
252b5132
RH		 6639 i.log2_scale_factor = 1;
6640 break;
551c1ca1 6641 case 4:
252b5132
RH		 6642 i.log2_scale_factor = 2;
6643 break;
551c1ca1 6644 case 8:
252b5132
RH		 6645 i.log2_scale_factor = 3;
6646 break;
6647 default:
a724f0f4
JB		 6648 {
6649 char sep = *input_line_pointer;
6650
6651 *input_line_pointer = '\0';
6652 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6653 scale);
6654 *input_line_pointer = sep;
6655 input_line_pointer = save;
6656 return NULL;
6657 }
252b5132 6658 }
29b0f896 6659 if (i.log2_scale_factor != 0 && i.index_reg == 0)
252b5132
RH		 6660 {
6661 as_warn (_("scale factor of %d without an index register"),
24eab124 6662 1 << i.log2_scale_factor);
252b5132 6663 i.log2_scale_factor = 0;
252b5132 6664 }
551c1ca1
AM		 6665 scale = input_line_pointer;
6666 input_line_pointer = save;
6667 return scale;
252b5132
RH		 6668}
6669
252b5132 6670static int
e3bb37b5 6671i386_displacement (char *disp_start, char *disp_end)
252b5132 6672{
29b0f896 6673 expressionS *exp;
252b5132
RH		 6674 segT exp_seg = 0;
6675 char *save_input_line_pointer;
f3c180ae 6676 char *gotfree_input_line;
40fb9820
L		 6677 int override;
6678 i386_operand_type bigdisp, types = anydisp;
3992d3b7 6679 int ret;
252b5132 6680
31b2323c
L		 6681 if (i.disp_operands == MAX_MEMORY_OPERANDS)
6682 {
6683 as_bad (_("at most %d displacement operands are allowed"),
6684 MAX_MEMORY_OPERANDS);
6685 return 0;
6686 }
6687
0dfbf9d7 6688 operand_type_set (&bigdisp, 0);
40fb9820
L		 6689 if ((i.types[this_operand].bitfield.jumpabsolute)
6690 || (!current_templates->start->opcode_modifier.jump
6691 && !current_templates->start->opcode_modifier.jumpdword))
e05278af 6692 {
40fb9820 6693 bigdisp.bitfield.disp32 = 1;
e05278af 6694 override = (i.prefix[ADDR_PREFIX] != 0);
40fb9820
L		 6695 if (flag_code == CODE_64BIT)
6696 {
6697 if (!override)
6698 {
6699 bigdisp.bitfield.disp32s = 1;
6700 bigdisp.bitfield.disp64 = 1;
6701 }
6702 }
6703 else if ((flag_code == CODE_16BIT) ^ override)
6704 {
6705 bigdisp.bitfield.disp32 = 0;
6706 bigdisp.bitfield.disp16 = 1;
6707 }
e05278af
JB		 6708 }
6709 else
6710 {
6711 /* For PC-relative branches, the width of the displacement
6712 is dependent upon data size, not address size. */
e05278af 6713 override = (i.prefix[DATA_PREFIX] != 0);
40fb9820
L		 6714 if (flag_code == CODE_64BIT)
6715 {
6716 if (override || i.suffix == WORD_MNEM_SUFFIX)
6717 bigdisp.bitfield.disp16 = 1;
6718 else
6719 {
6720 bigdisp.bitfield.disp32 = 1;
6721 bigdisp.bitfield.disp32s = 1;
6722 }
6723 }
6724 else
e05278af
JB		 6725 {
6726 if (!override)
6727 override = (i.suffix == (flag_code != CODE_16BIT
6728 ? WORD_MNEM_SUFFIX
6729 : LONG_MNEM_SUFFIX));
40fb9820
L		 6730 bigdisp.bitfield.disp32 = 1;
6731 if ((flag_code == CODE_16BIT) ^ override)
6732 {
6733 bigdisp.bitfield.disp32 = 0;
6734 bigdisp.bitfield.disp16 = 1;
6735 }
e05278af 6736 }
e05278af 6737 }
c6fb90c8
L		 6738 i.types[this_operand] = operand_type_or (i.types[this_operand],
6739 bigdisp);
252b5132
RH		 6740
6741 exp = &disp_expressions[i.disp_operands];
520dc8e8 6742 i.op[this_operand].disps = exp;
252b5132
RH		 6743 i.disp_operands++;
6744 save_input_line_pointer = input_line_pointer;
6745 input_line_pointer = disp_start;
6746 END_STRING_AND_SAVE (disp_end);
6747
6748#ifndef GCC_ASM_O_HACK
6749#define GCC_ASM_O_HACK 0
6750#endif
6751#if GCC_ASM_O_HACK
6752 END_STRING_AND_SAVE (disp_end + 1);
40fb9820 6753 if (i.types[this_operand].bitfield.baseIndex
24eab124 6754 && displacement_string_end[-1] == '+')
252b5132
RH		 6755 {
6756 /* This hack is to avoid a warning when using the "o"
24eab124
AM		 6757 constraint within gcc asm statements.
6758 For instance:
6759
6760 #define _set_tssldt_desc(n,addr,limit,type) \
6761 __asm__ __volatile__ ( \
6762 "movw %w2,%0\n\t" \
6763 "movw %w1,2+%0\n\t" \
6764 "rorl $16,%1\n\t" \
6765 "movb %b1,4+%0\n\t" \
6766 "movb %4,5+%0\n\t" \
6767 "movb $0,6+%0\n\t" \
6768 "movb %h1,7+%0\n\t" \
6769 "rorl $16,%1" \
6770 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6771
6772 This works great except that the output assembler ends
6773 up looking a bit weird if it turns out that there is
6774 no offset. You end up producing code that looks like:
6775
6776 #APP
6777 movw $235,(%eax)
6778 movw %dx,2+(%eax)
6779 rorl $16,%edx
6780 movb %dl,4+(%eax)
6781 movb $137,5+(%eax)
6782 movb $0,6+(%eax)
6783 movb %dh,7+(%eax)
6784 rorl $16,%edx
6785 #NO_APP
6786
47926f60 6787 So here we provide the missing zero. */
24eab124
AM		 6788
6789 *displacement_string_end = '0';
252b5132
RH		 6790 }
6791#endif
3956db08 6792 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types);
f3c180ae
AM		 6793 if (gotfree_input_line)
6794 input_line_pointer = gotfree_input_line;
252b5132 6795
24eab124 6796 exp_seg = expression (exp);
252b5132 6797
636c26b0
AM		 6798 SKIP_WHITESPACE ();
6799 if (*input_line_pointer)
6800 as_bad (_("junk `%s' after expression"), input_line_pointer);
6801#if GCC_ASM_O_HACK
6802 RESTORE_END_STRING (disp_end + 1);
6803#endif
636c26b0 6804 input_line_pointer = save_input_line_pointer;
636c26b0
AM		 6805 if (gotfree_input_line)
6806 free (gotfree_input_line);
3992d3b7 6807 ret = 1;
636c26b0 6808
24eab124
AM		 6809 /* We do this to make sure that the section symbol is in
6810 the symbol table. We will ultimately change the relocation
47926f60 6811 to be relative to the beginning of the section. */
1ae12ab7 6812 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
d6ab8113
JB		 6813 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
6814 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
24eab124 6815 {
636c26b0 6816 if (exp->X_op != O_symbol)
3992d3b7 6817 goto inv_disp;
636c26b0 6818
e5cb08ac 6819 if (S_IS_LOCAL (exp->X_add_symbol)
24eab124
AM		 6820 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
6821 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
24eab124
AM		 6822 exp->X_op = O_subtract;
6823 exp->X_op_symbol = GOT_symbol;
1ae12ab7 6824 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
29b0f896 6825 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
d6ab8113
JB		 6826 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
6827 i.reloc[this_operand] = BFD_RELOC_64;
23df1078 6828 else
29b0f896 6829 i.reloc[this_operand] = BFD_RELOC_32;
24eab124 6830 }
252b5132 6831
3992d3b7
AM		 6832 else if (exp->X_op == O_absent
6833 || exp->X_op == O_illegal
6834 || exp->X_op == O_big
6835 || (gotfree_input_line
6836 && (exp->X_op == O_constant
6837 || exp->X_op == O_register)))
2daf4fd8 6838 {
3992d3b7
AM		 6839 inv_disp:
6840 as_bad (_("missing or invalid displacement expression `%s'"),
2daf4fd8 6841 disp_start);
3992d3b7 6842 ret = 0;
2daf4fd8
AM		 6843 }
6844
4c63da97 6845#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3992d3b7
AM		 6846 else if (exp->X_op != O_constant
6847 && OUTPUT_FLAVOR == bfd_target_aout_flavour
6848 && exp_seg != absolute_section
6849 && exp_seg != text_section
6850 && exp_seg != data_section
6851 && exp_seg != bss_section
6852 && exp_seg != undefined_section
6853 && !bfd_is_com_section (exp_seg))
24eab124 6854 {
d0b47220 6855 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3992d3b7 6856 ret = 0;
24eab124 6857 }
252b5132 6858#endif
3956db08 6859
3992d3b7
AM		 6860 RESTORE_END_STRING (disp_end);
6861
40fb9820
L		 6862 /* Check if this is a displacement only operand. */
6863 bigdisp = i.types[this_operand];
6864 bigdisp.bitfield.disp8 = 0;
6865 bigdisp.bitfield.disp16 = 0;
6866 bigdisp.bitfield.disp32 = 0;
6867 bigdisp.bitfield.disp32s = 0;
6868 bigdisp.bitfield.disp64 = 0;
0dfbf9d7 6869 if (operand_type_all_zero (&bigdisp))
c6fb90c8
L		 6870 i.types[this_operand] = operand_type_and (i.types[this_operand],
6871 types);
3956db08 6872
3992d3b7 6873 return ret;
252b5132
RH		 6874}
6875
eecb386c 6876/* Make sure the memory operand we've been dealt is valid.
47926f60
KH		 6877 Return 1 on success, 0 on a failure. */
6878
252b5132 6879static int
e3bb37b5 6880i386_index_check (const char *operand_string)
252b5132 6881{
3e73aa7c 6882 int ok;
fc0763e6 6883 const char *kind = "base/index";
24eab124 6884#if INFER_ADDR_PREFIX
eecb386c
AM		 6885 int fudged = 0;
6886
24eab124
AM		 6887 tryprefix:
6888#endif
3e73aa7c 6889 ok = 1;
fc0763e6
JB		 6890 if (current_templates->start->opcode_modifier.isstring
6891 && !current_templates->start->opcode_modifier.immext
6892 && (current_templates->end[-1].opcode_modifier.isstring
6893 || i.mem_operands))
6894 {
6895 /* Memory operands of string insns are special in that they only allow
6896 a single register (rDI, rSI, or rBX) as their memory address. */
6897 unsigned int expected;
6898
6899 kind = "string address";
6900
6901 if (current_templates->start->opcode_modifier.w)
6902 {
6903 i386_operand_type type = current_templates->end[-1].operand_types[0];
6904
6905 if (!type.bitfield.baseindex
6906 || ((!i.mem_operands != !intel_syntax)
6907 && current_templates->end[-1].operand_types[1]
6908 .bitfield.baseindex))
6909 type = current_templates->end[-1].operand_types[1];
6910 expected = type.bitfield.esseg ? 7 /* rDI */ : 6 /* rSI */;
6911 }
6912 else
6913 expected = 3 /* rBX */;
6914
6915 if (!i.base_reg || i.index_reg
6916 || operand_type_check (i.types[this_operand], disp))
6917 ok = -1;
6918 else if (!(flag_code == CODE_64BIT
6919 ? i.prefix[ADDR_PREFIX]
6920 ? i.base_reg->reg_type.bitfield.reg32
6921 : i.base_reg->reg_type.bitfield.reg64
6922 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6923 ? i.base_reg->reg_type.bitfield.reg32
6924 : i.base_reg->reg_type.bitfield.reg16))
6925 ok = 0;
6926 else if (i.base_reg->reg_num != expected)
6927 ok = -1;
6928
6929 if (ok < 0)
6930 {
6931 unsigned int j;
6932
6933 for (j = 0; j < i386_regtab_size; ++j)
6934 if ((flag_code == CODE_64BIT
6935 ? i.prefix[ADDR_PREFIX]
6936 ? i386_regtab[j].reg_type.bitfield.reg32
6937 : i386_regtab[j].reg_type.bitfield.reg64
6938 : (flag_code == CODE_16BIT) ^ !i.prefix[ADDR_PREFIX]
6939 ? i386_regtab[j].reg_type.bitfield.reg32
6940 : i386_regtab[j].reg_type.bitfield.reg16)
6941 && i386_regtab[j].reg_num == expected)
6942 break;
6943 assert (j < i386_regtab_size);
6944 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6945 operand_string,
6946 intel_syntax ? '[' : '(',
6947 register_prefix,
6948 i386_regtab[j].reg_name,
6949 intel_syntax ? ']' : ')');
6950 ok = 1;
6951 }
6952 }
6953 else if (flag_code == CODE_64BIT)
64e74474 6954 {
64e74474 6955 if ((i.base_reg
40fb9820
L		 6956 && ((i.prefix[ADDR_PREFIX] == 0
6957 && !i.base_reg->reg_type.bitfield.reg64)
6958 || (i.prefix[ADDR_PREFIX]
6959 && !i.base_reg->reg_type.bitfield.reg32))
6960 && (i.index_reg
9a04903e
JB		 6961 || i.base_reg->reg_num !=
6962 (i.prefix[ADDR_PREFIX] == 0 ? RegRip : RegEip)))
64e74474 6963 || (i.index_reg
40fb9820
L		 6964 && (!i.index_reg->reg_type.bitfield.baseindex
6965 || (i.prefix[ADDR_PREFIX] == 0
db51cc60
L		 6966 && i.index_reg->reg_num != RegRiz
6967 && !i.index_reg->reg_type.bitfield.reg64
6968 )
40fb9820 6969 || (i.prefix[ADDR_PREFIX]
db51cc60 6970 && i.index_reg->reg_num != RegEiz
40fb9820 6971 && !i.index_reg->reg_type.bitfield.reg32))))
64e74474 6972 ok = 0;
3e73aa7c
JH		 6973 }
6974 else
6975 {
6976 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
6977 {
6978 /* 16bit checks. */
6979 if ((i.base_reg
40fb9820
L		 6980 && (!i.base_reg->reg_type.bitfield.reg16
6981 || !i.base_reg->reg_type.bitfield.baseindex))
3e73aa7c 6982 || (i.index_reg
40fb9820
L		 6983 && (!i.index_reg->reg_type.bitfield.reg16
6984 || !i.index_reg->reg_type.bitfield.baseindex
29b0f896
AM		 6985 || !(i.base_reg
6986 && i.base_reg->reg_num < 6
6987 && i.index_reg->reg_num >= 6
6988 && i.log2_scale_factor == 0))))
3e73aa7c
JH		 6989 ok = 0;
6990 }
6991 else
e5cb08ac 6992 {
3e73aa7c
JH		 6993 /* 32bit checks. */
6994 if ((i.base_reg
40fb9820 6995 && !i.base_reg->reg_type.bitfield.reg32)
3e73aa7c 6996 || (i.index_reg
db51cc60
L		 6997 && ((!i.index_reg->reg_type.bitfield.reg32
6998 && i.index_reg->reg_num != RegEiz)
40fb9820 6999 || !i.index_reg->reg_type.bitfield.baseindex)))
e5cb08ac 7000 ok = 0;
3e73aa7c
JH		 7001 }
7002 }
7003 if (!ok)
24eab124
AM		 7004 {
7005#if INFER_ADDR_PREFIX
fc0763e6 7006 if (!i.mem_operands && !i.prefix[ADDR_PREFIX])
24eab124
AM		 7007 {
7008 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
7009 i.prefixes += 1;
b23bac36
AM		 7010 /* Change the size of any displacement too. At most one of
7011 Disp16 or Disp32 is set.
7012 FIXME. There doesn't seem to be any real need for separate
7013 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
47926f60 7014 Removing them would probably clean up the code quite a lot. */
4eed87de 7015 if (flag_code != CODE_64BIT
40fb9820
L		 7016 && (i.types[this_operand].bitfield.disp16
7017 || i.types[this_operand].bitfield.disp32))
7018 i.types[this_operand]
c6fb90c8 7019 = operand_type_xor (i.types[this_operand], disp16_32);
eecb386c 7020 fudged = 1;
24eab124
AM		 7021 goto tryprefix;
7022 }
eecb386c 7023 if (fudged)
fc0763e6
JB		 7024 as_bad (_("`%s' is not a valid %s expression"),
7025 operand_string,
7026 kind);
eecb386c 7027 else
c388dee8 7028#endif
fc0763e6 7029 as_bad (_("`%s' is not a valid %s-bit %s expression"),
eecb386c 7030 operand_string,
fc0763e6
JB		 7031 flag_code_names[i.prefix[ADDR_PREFIX]
7032 ? flag_code == CODE_32BIT
7033 ? CODE_16BIT
7034 : CODE_32BIT
7035 : flag_code],
7036 kind);
24eab124 7037 }
20f0a1fc 7038 return ok;
24eab124 7039}
252b5132 7040
fc0763e6 7041/* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
47926f60 7042 on error. */
252b5132 7043
252b5132 7044static int
a7619375 7045i386_att_operand (char *operand_string)
252b5132 7046{
af6bdddf
AM		 7047 const reg_entry *r;
7048 char *end_op;
24eab124 7049 char *op_string = operand_string;
252b5132 7050
24eab124 7051 if (is_space_char (*op_string))
252b5132
RH		 7052 ++op_string;
7053
24eab124 7054 /* We check for an absolute prefix (differentiating,
47926f60 7055 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
24eab124
AM		 7056 if (*op_string == ABSOLUTE_PREFIX)
7057 {
7058 ++op_string;
7059 if (is_space_char (*op_string))
7060 ++op_string;
40fb9820 7061 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124 7062 }
252b5132 7063
47926f60 7064 /* Check if operand is a register. */
4d1bb795 7065 if ((r = parse_register (op_string, &end_op)) != NULL)
24eab124 7066 {
40fb9820
L		 7067 i386_operand_type temp;
7068
24eab124
AM		 7069 /* Check for a segment override by searching for ':' after a
7070 segment register. */
7071 op_string = end_op;
7072 if (is_space_char (*op_string))
7073 ++op_string;
40fb9820
L		 7074 if (*op_string == ':'
7075 && (r->reg_type.bitfield.sreg2
7076 || r->reg_type.bitfield.sreg3))
24eab124
AM		 7077 {
7078 switch (r->reg_num)
7079 {
7080 case 0:
7081 i.seg[i.mem_operands] = &es;
7082 break;
7083 case 1:
7084 i.seg[i.mem_operands] = &cs;
7085 break;
7086 case 2:
7087 i.seg[i.mem_operands] = &ss;
7088 break;
7089 case 3:
7090 i.seg[i.mem_operands] = &ds;
7091 break;
7092 case 4:
7093 i.seg[i.mem_operands] = &fs;
7094 break;
7095 case 5:
7096 i.seg[i.mem_operands] = &gs;
7097 break;
7098 }
252b5132 7099
24eab124 7100 /* Skip the ':' and whitespace. */
252b5132
RH		 7101 ++op_string;
7102 if (is_space_char (*op_string))
24eab124 7103 ++op_string;
252b5132 7104
24eab124
AM		 7105 if (!is_digit_char (*op_string)
7106 && !is_identifier_char (*op_string)
7107 && *op_string != '('
7108 && *op_string != ABSOLUTE_PREFIX)
7109 {
7110 as_bad (_("bad memory operand `%s'"), op_string);
7111 return 0;
7112 }
47926f60 7113 /* Handle case of %es:*foo. */
24eab124
AM		 7114 if (*op_string == ABSOLUTE_PREFIX)
7115 {
7116 ++op_string;
7117 if (is_space_char (*op_string))
7118 ++op_string;
40fb9820 7119 i.types[this_operand].bitfield.jumpabsolute = 1;
24eab124
AM		 7120 }
7121 goto do_memory_reference;
7122 }
7123 if (*op_string)
7124 {
d0b47220 7125 as_bad (_("junk `%s' after register"), op_string);
24eab124
AM		 7126 return 0;
7127 }
40fb9820
L		 7128 temp = r->reg_type;
7129 temp.bitfield.baseindex = 0;
c6fb90c8
L		 7130 i.types[this_operand] = operand_type_or (i.types[this_operand],
7131 temp);
7d5e4556 7132 i.types[this_operand].bitfield.unspecified = 0;
520dc8e8 7133 i.op[this_operand].regs = r;
24eab124
AM		 7134 i.reg_operands++;
7135 }
af6bdddf
AM		 7136 else if (*op_string == REGISTER_PREFIX)
7137 {
7138 as_bad (_("bad register name `%s'"), op_string);
7139 return 0;
7140 }
24eab124 7141 else if (*op_string == IMMEDIATE_PREFIX)
ce8a8b2f 7142 {
24eab124 7143 ++op_string;
40fb9820 7144 if (i.types[this_operand].bitfield.jumpabsolute)
24eab124 7145 {
d0b47220 7146 as_bad (_("immediate operand illegal with absolute jump"));
24eab124
AM		 7147 return 0;
7148 }
7149 if (!i386_immediate (op_string))
7150 return 0;
7151 }
7152 else if (is_digit_char (*op_string)
7153 || is_identifier_char (*op_string)
e5cb08ac 7154 || *op_string == '(')
24eab124 7155 {
47926f60 7156 /* This is a memory reference of some sort. */
af6bdddf 7157 char *base_string;
252b5132 7158
47926f60 7159 /* Start and end of displacement string expression (if found). */
eecb386c
AM		 7160 char *displacement_string_start;
7161 char *displacement_string_end;
252b5132 7162
24eab124 7163 do_memory_reference:
24eab124 7164 if ((i.mem_operands == 1
40fb9820 7165 && !current_templates->start->opcode_modifier.isstring)
24eab124
AM		 7166 || i.mem_operands == 2)
7167 {
7168 as_bad (_("too many memory references for `%s'"),
7169 current_templates->start->name);
7170 return 0;
7171 }
252b5132 7172
24eab124
AM		 7173 /* Check for base index form. We detect the base index form by
7174 looking for an ')' at the end of the operand, searching
7175 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7176 after the '('. */
af6bdddf 7177 base_string = op_string + strlen (op_string);
c3332e24 7178
af6bdddf
AM		 7179 --base_string;
7180 if (is_space_char (*base_string))
7181 --base_string;
252b5132 7182
47926f60 7183 /* If we only have a displacement, set-up for it to be parsed later. */
af6bdddf
AM		 7184 displacement_string_start = op_string;
7185 displacement_string_end = base_string + 1;
252b5132 7186
24eab124
AM		 7187 if (*base_string == ')')
7188 {
af6bdddf 7189 char *temp_string;
24eab124
AM		 7190 unsigned int parens_balanced = 1;
7191 /* We've already checked that the number of left & right ()'s are
47926f60 7192 equal, so this loop will not be infinite. */
24eab124
AM		 7193 do
7194 {
7195 base_string--;
7196 if (*base_string == ')')
7197 parens_balanced++;
7198 if (*base_string == '(')
7199 parens_balanced--;
7200 }
7201 while (parens_balanced);
c3332e24 7202
af6bdddf 7203 temp_string = base_string;
c3332e24 7204
24eab124 7205 /* Skip past '(' and whitespace. */
252b5132
RH		 7206 ++base_string;
7207 if (is_space_char (*base_string))
24eab124 7208 ++base_string;
252b5132 7209
af6bdddf 7210 if (*base_string == ','
4eed87de
AM		 7211 || ((i.base_reg = parse_register (base_string, &end_op))
7212 != NULL))
252b5132 7213 {
af6bdddf 7214 displacement_string_end = temp_string;
252b5132 7215
40fb9820 7216 i.types[this_operand].bitfield.baseindex = 1;
252b5132 7217
af6bdddf 7218 if (i.base_reg)
24eab124 7219 {
24eab124
AM		 7220 base_string = end_op;
7221 if (is_space_char (*base_string))
7222 ++base_string;
af6bdddf
AM		 7223 }
7224
7225 /* There may be an index reg or scale factor here. */
7226 if (*base_string == ',')
7227 {
7228 ++base_string;
7229 if (is_space_char (*base_string))
7230 ++base_string;
7231
4eed87de
AM		 7232 if ((i.index_reg = parse_register (base_string, &end_op))
7233 != NULL)
24eab124 7234 {
af6bdddf 7235 base_string = end_op;
24eab124
AM		 7236 if (is_space_char (*base_string))
7237 ++base_string;
af6bdddf
AM		 7238 if (*base_string == ',')
7239 {
7240 ++base_string;
7241 if (is_space_char (*base_string))
7242 ++base_string;
7243 }
e5cb08ac 7244 else if (*base_string != ')')
af6bdddf 7245 {
4eed87de
AM		 7246 as_bad (_("expecting `,' or `)' "
7247 "after index register in `%s'"),
af6bdddf
AM		 7248 operand_string);
7249 return 0;
7250 }
24eab124 7251 }
af6bdddf 7252 else if (*base_string == REGISTER_PREFIX)
24eab124 7253 {
af6bdddf 7254 as_bad (_("bad register name `%s'"), base_string);
24eab124
AM		 7255 return 0;
7256 }
252b5132 7257
47926f60 7258 /* Check for scale factor. */
551c1ca1 7259 if (*base_string != ')')
af6bdddf 7260 {
551c1ca1
AM		 7261 char *end_scale = i386_scale (base_string);
7262
7263 if (!end_scale)
af6bdddf 7264 return 0;
24eab124 7265
551c1ca1 7266 base_string = end_scale;
af6bdddf
AM		 7267 if (is_space_char (*base_string))
7268 ++base_string;
7269 if (*base_string != ')')
7270 {
4eed87de
AM		 7271 as_bad (_("expecting `)' "
7272 "after scale factor in `%s'"),
af6bdddf
AM		 7273 operand_string);
7274 return 0;
7275 }
7276 }
7277 else if (!i.index_reg)
24eab124 7278 {
4eed87de
AM		 7279 as_bad (_("expecting index register or scale factor "
7280 "after `,'; got '%c'"),
af6bdddf 7281 *base_string);
24eab124
AM		 7282 return 0;
7283 }
7284 }
af6bdddf 7285 else if (*base_string != ')')
24eab124 7286 {
4eed87de
AM		 7287 as_bad (_("expecting `,' or `)' "
7288 "after base register in `%s'"),
af6bdddf 7289 operand_string);
24eab124
AM		 7290 return 0;
7291 }
c3332e24 7292 }
af6bdddf 7293 else if (*base_string == REGISTER_PREFIX)
c3332e24 7294 {
af6bdddf 7295 as_bad (_("bad register name `%s'"), base_string);
24eab124 7296 return 0;
c3332e24 7297 }
24eab124
AM		 7298 }
7299
7300 /* If there's an expression beginning the operand, parse it,
7301 assuming displacement_string_start and
7302 displacement_string_end are meaningful. */
7303 if (displacement_string_start != displacement_string_end)
7304 {
7305 if (!i386_displacement (displacement_string_start,
7306 displacement_string_end))
7307 return 0;
7308 }
7309
7310 /* Special case for (%dx) while doing input/output op. */
7311 if (i.base_reg
0dfbf9d7
L		 7312 && operand_type_equal (&i.base_reg->reg_type,
7313 &reg16_inoutportreg)
24eab124
AM		 7314 && i.index_reg == 0
7315 && i.log2_scale_factor == 0
7316 && i.seg[i.mem_operands] == 0
40fb9820 7317 && !operand_type_check (i.types[this_operand], disp))
24eab124 7318 {
65da13b5 7319 i.types[this_operand] = inoutportreg;
24eab124
AM		 7320 return 1;
7321 }
7322
eecb386c
AM		 7323 if (i386_index_check (operand_string) == 0)
7324 return 0;
5c07affc 7325 i.types[this_operand].bitfield.mem = 1;
24eab124
AM		 7326 i.mem_operands++;
7327 }
7328 else
ce8a8b2f
AM		 7329 {
7330 /* It's not a memory operand; argh! */
24eab124
AM		 7331 as_bad (_("invalid char %s beginning operand %d `%s'"),
7332 output_invalid (*op_string),
7333 this_operand + 1,
7334 op_string);
7335 return 0;
7336 }
47926f60 7337 return 1; /* Normal return. */
252b5132
RH		 7338}
7339\f
ee7fcc42
AM		 7340/* md_estimate_size_before_relax()
7341
7342 Called just before relax() for rs_machine_dependent frags. The x86
7343 assembler uses these frags to handle variable size jump
7344 instructions.
7345
7346 Any symbol that is now undefined will not become defined.
7347 Return the correct fr_subtype in the frag.
7348 Return the initial "guess for variable size of frag" to caller.
7349 The guess is actually the growth beyond the fixed part. Whatever
7350 we do to grow the fixed or variable part contributes to our
7351 returned value. */
7352
252b5132
RH		 7353int
7354md_estimate_size_before_relax (fragP, segment)
29b0f896
AM		 7355 fragS *fragP;
7356 segT segment;
252b5132 7357{
252b5132 7358 /* We've already got fragP->fr_subtype right; all we have to do is
b98ef147
AM		 7359 check for un-relaxable symbols. On an ELF system, we can't relax
7360 an externally visible symbol, because it may be overridden by a
7361 shared library. */
7362 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
6d249963 7363#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7364 || (IS_ELF
31312f95
AM		 7365 && (S_IS_EXTERNAL (fragP->fr_symbol)
7366 || S_IS_WEAK (fragP->fr_symbol)))
b98ef147
AM		 7367#endif
7368 )
252b5132 7369 {
b98ef147
AM		 7370 /* Symbol is undefined in this segment, or we need to keep a
7371 reloc so that weak symbols can be overridden. */
7372 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
f86103b7 7373 enum bfd_reloc_code_real reloc_type;
ee7fcc42
AM		 7374 unsigned char *opcode;
7375 int old_fr_fix;
f6af82bd 7376
ee7fcc42
AM		 7377 if (fragP->fr_var != NO_RELOC)
7378 reloc_type = fragP->fr_var;
b98ef147 7379 else if (size == 2)
f6af82bd
AM		 7380 reloc_type = BFD_RELOC_16_PCREL;
7381 else
7382 reloc_type = BFD_RELOC_32_PCREL;
252b5132 7383
ee7fcc42
AM		 7384 old_fr_fix = fragP->fr_fix;
7385 opcode = (unsigned char *) fragP->fr_opcode;
7386
fddf5b5b 7387 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
252b5132 7388 {
fddf5b5b
AM		 7389 case UNCOND_JUMP:
7390 /* Make jmp (0xeb) a (d)word displacement jump. */
47926f60 7391 opcode[0] = 0xe9;
252b5132 7392 fragP->fr_fix += size;
062cd5e7
AS		 7393 fix_new (fragP, old_fr_fix, size,
7394 fragP->fr_symbol,
7395 fragP->fr_offset, 1,
7396 reloc_type);
252b5132
RH		 7397 break;
7398
fddf5b5b 7399 case COND_JUMP86:
412167cb
AM		 7400 if (size == 2
7401 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
fddf5b5b
AM		 7402 {
7403 /* Negate the condition, and branch past an
7404 unconditional jump. */
7405 opcode[0] ^= 1;
7406 opcode[1] = 3;
7407 /* Insert an unconditional jump. */
7408 opcode[2] = 0xe9;
7409 /* We added two extra opcode bytes, and have a two byte
7410 offset. */
7411 fragP->fr_fix += 2 + 2;
062cd5e7
AS		 7412 fix_new (fragP, old_fr_fix + 2, 2,
7413 fragP->fr_symbol,
7414 fragP->fr_offset, 1,
7415 reloc_type);
fddf5b5b
AM		 7416 break;
7417 }
7418 /* Fall through. */
7419
7420 case COND_JUMP:
412167cb
AM		 7421 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
7422 {
3e02c1cc
AM		 7423 fixS *fixP;
7424
412167cb 7425 fragP->fr_fix += 1;
3e02c1cc
AM		 7426 fixP = fix_new (fragP, old_fr_fix, 1,
7427 fragP->fr_symbol,
7428 fragP->fr_offset, 1,
7429 BFD_RELOC_8_PCREL);
7430 fixP->fx_signed = 1;
412167cb
AM		 7431 break;
7432 }
93c2a809 7433
24eab124 7434 /* This changes the byte-displacement jump 0x7N
fddf5b5b 7435 to the (d)word-displacement jump 0x0f,0x8N. */
252b5132 7436 opcode[1] = opcode[0] + 0x10;
f6af82bd 7437 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
47926f60
KH		 7438 /* We've added an opcode byte. */
7439 fragP->fr_fix += 1 + size;
062cd5e7
AS		 7440 fix_new (fragP, old_fr_fix + 1, size,
7441 fragP->fr_symbol,
7442 fragP->fr_offset, 1,
7443 reloc_type);
252b5132 7444 break;
fddf5b5b
AM		 7445
7446 default:
7447 BAD_CASE (fragP->fr_subtype);
7448 break;
252b5132
RH		 7449 }
7450 frag_wane (fragP);
ee7fcc42 7451 return fragP->fr_fix - old_fr_fix;
252b5132 7452 }
93c2a809 7453
93c2a809
AM		 7454 /* Guess size depending on current relax state. Initially the relax
7455 state will correspond to a short jump and we return 1, because
7456 the variable part of the frag (the branch offset) is one byte
7457 long. However, we can relax a section more than once and in that
7458 case we must either set fr_subtype back to the unrelaxed state,
7459 or return the value for the appropriate branch. */
7460 return md_relax_table[fragP->fr_subtype].rlx_length;
ee7fcc42
AM		 7461}
7462
47926f60
KH		 7463/* Called after relax() is finished.
7464
7465 In: Address of frag.
7466 fr_type == rs_machine_dependent.
7467 fr_subtype is what the address relaxed to.
7468
7469 Out: Any fixSs and constants are set up.
7470 Caller will turn frag into a ".space 0". */
7471
252b5132
RH		 7472void
7473md_convert_frag (abfd, sec, fragP)
ab9da554
ILT		 7474 bfd *abfd ATTRIBUTE_UNUSED;
7475 segT sec ATTRIBUTE_UNUSED;
29b0f896 7476 fragS *fragP;
252b5132 7477{
29b0f896 7478 unsigned char *opcode;
252b5132 7479 unsigned char *where_to_put_displacement = NULL;
847f7ad4
AM		 7480 offsetT target_address;
7481 offsetT opcode_address;
252b5132 7482 unsigned int extension = 0;
847f7ad4 7483 offsetT displacement_from_opcode_start;
252b5132
RH		 7484
7485 opcode = (unsigned char *) fragP->fr_opcode;
7486
47926f60 7487 /* Address we want to reach in file space. */
252b5132 7488 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
252b5132 7489
47926f60 7490 /* Address opcode resides at in file space. */
252b5132
RH		 7491 opcode_address = fragP->fr_address + fragP->fr_fix;
7492
47926f60 7493 /* Displacement from opcode start to fill into instruction. */
252b5132
RH		 7494 displacement_from_opcode_start = target_address - opcode_address;
7495
fddf5b5b 7496 if ((fragP->fr_subtype & BIG) == 0)
252b5132 7497 {
47926f60
KH		 7498 /* Don't have to change opcode. */
7499 extension = 1; /* 1 opcode + 1 displacement */
252b5132 7500 where_to_put_displacement = &opcode[1];
fddf5b5b
AM		 7501 }
7502 else
7503 {
7504 if (no_cond_jump_promotion
7505 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4eed87de
AM		 7506 as_warn_where (fragP->fr_file, fragP->fr_line,
7507 _("long jump required"));
252b5132 7508
fddf5b5b
AM		 7509 switch (fragP->fr_subtype)
7510 {
7511 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
7512 extension = 4; /* 1 opcode + 4 displacement */
7513 opcode[0] = 0xe9;
7514 where_to_put_displacement = &opcode[1];
7515 break;
252b5132 7516
fddf5b5b
AM		 7517 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
7518 extension = 2; /* 1 opcode + 2 displacement */
7519 opcode[0] = 0xe9;
7520 where_to_put_displacement = &opcode[1];
7521 break;
252b5132 7522
fddf5b5b
AM		 7523 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
7524 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
7525 extension = 5; /* 2 opcode + 4 displacement */
7526 opcode[1] = opcode[0] + 0x10;
7527 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7528 where_to_put_displacement = &opcode[2];
7529 break;
252b5132 7530
fddf5b5b
AM		 7531 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
7532 extension = 3; /* 2 opcode + 2 displacement */
7533 opcode[1] = opcode[0] + 0x10;
7534 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
7535 where_to_put_displacement = &opcode[2];
7536 break;
252b5132 7537
fddf5b5b
AM		 7538 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
7539 extension = 4;
7540 opcode[0] ^= 1;
7541 opcode[1] = 3;
7542 opcode[2] = 0xe9;
7543 where_to_put_displacement = &opcode[3];
7544 break;
7545
7546 default:
7547 BAD_CASE (fragP->fr_subtype);
7548 break;
7549 }
252b5132 7550 }
fddf5b5b 7551
7b81dfbb
AJ		 7552 /* If size if less then four we are sure that the operand fits,
7553 but if it's 4, then it could be that the displacement is larger
7554 then -/+ 2GB. */
7555 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
7556 && object_64bit
7557 && ((addressT) (displacement_from_opcode_start - extension
4eed87de
AM		 7558 + ((addressT) 1 << 31))
7559 > (((addressT) 2 << 31) - 1)))
7b81dfbb
AJ		 7560 {
7561 as_bad_where (fragP->fr_file, fragP->fr_line,
7562 _("jump target out of range"));
7563 /* Make us emit 0. */
7564 displacement_from_opcode_start = extension;
7565 }
47926f60 7566 /* Now put displacement after opcode. */
252b5132
RH		 7567 md_number_to_chars ((char *) where_to_put_displacement,
7568 (valueT) (displacement_from_opcode_start - extension),
fddf5b5b 7569 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
252b5132
RH		 7570 fragP->fr_fix += extension;
7571}
7572\f
252b5132
RH		 7573/* Apply a fixup (fixS) to segment data, once it has been determined
7574 by our caller that we have all the info we need to fix it up.
7575
7576 On the 386, immediates, displacements, and data pointers are all in
7577 the same (little-endian) format, so we don't need to care about which
7578 we are handling. */
7579
94f592af 7580void
55cf6793 7581md_apply_fix (fixP, valP, seg)
47926f60
KH		 7582 /* The fix we're to put in. */
7583 fixS *fixP;
47926f60 7584 /* Pointer to the value of the bits. */
c6682705 7585 valueT *valP;
47926f60
KH		 7586 /* Segment fix is from. */
7587 segT seg ATTRIBUTE_UNUSED;
252b5132 7588{
94f592af 7589 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
c6682705 7590 valueT value = *valP;
252b5132 7591
f86103b7 7592#if !defined (TE_Mach)
93382f6d
AM		 7593 if (fixP->fx_pcrel)
7594 {
7595 switch (fixP->fx_r_type)
7596 {
5865bb77
ILT		 7597 default:
7598 break;
7599
d6ab8113
JB		 7600 case BFD_RELOC_64:
7601 fixP->fx_r_type = BFD_RELOC_64_PCREL;
7602 break;
93382f6d 7603 case BFD_RELOC_32:
ae8887b5 7604 case BFD_RELOC_X86_64_32S:
93382f6d
AM		 7605 fixP->fx_r_type = BFD_RELOC_32_PCREL;
7606 break;
7607 case BFD_RELOC_16:
7608 fixP->fx_r_type = BFD_RELOC_16_PCREL;
7609 break;
7610 case BFD_RELOC_8:
7611 fixP->fx_r_type = BFD_RELOC_8_PCREL;
7612 break;
7613 }
7614 }
252b5132 7615
a161fe53 7616 if (fixP->fx_addsy != NULL
31312f95 7617 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
d6ab8113 7618 || fixP->fx_r_type == BFD_RELOC_64_PCREL
31312f95
AM		 7619 || fixP->fx_r_type == BFD_RELOC_16_PCREL
7620 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
7621 && !use_rela_relocations)
252b5132 7622 {
31312f95
AM		 7623 /* This is a hack. There should be a better way to handle this.
7624 This covers for the fact that bfd_install_relocation will
7625 subtract the current location (for partial_inplace, PC relative
7626 relocations); see more below. */
252b5132 7627#ifndef OBJ_AOUT
718ddfc0 7628 if (IS_ELF
252b5132
RH		 7629#ifdef TE_PE
7630 || OUTPUT_FLAVOR == bfd_target_coff_flavour
7631#endif
7632 )
7633 value += fixP->fx_where + fixP->fx_frag->fr_address;
7634#endif
7635#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7636 if (IS_ELF)
252b5132 7637 {
6539b54b 7638 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
2f66722d 7639
6539b54b 7640 if ((sym_seg == seg
2f66722d 7641 || (symbol_section_p (fixP->fx_addsy)
6539b54b 7642 && sym_seg != absolute_section))
ae6063d4 7643 && !generic_force_reloc (fixP))
2f66722d
AM		 7644 {
7645 /* Yes, we add the values in twice. This is because
6539b54b
AM		 7646 bfd_install_relocation subtracts them out again. I think
7647 bfd_install_relocation is broken, but I don't dare change
2f66722d
AM		 7648 it. FIXME. */
7649 value += fixP->fx_where + fixP->fx_frag->fr_address;
7650 }
252b5132
RH		 7651 }
7652#endif
7653#if defined (OBJ_COFF) && defined (TE_PE)
977cdf5a
NC		 7654 /* For some reason, the PE format does not store a
7655 section address offset for a PC relative symbol. */
7656 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
7be1c489 7657 || S_IS_WEAK (fixP->fx_addsy))
252b5132
RH		 7658 value += md_pcrel_from (fixP);
7659#endif
7660 }
7661
7662 /* Fix a few things - the dynamic linker expects certain values here,
0234cb7c 7663 and we must not disappoint it. */
252b5132 7664#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
718ddfc0 7665 if (IS_ELF && fixP->fx_addsy)
47926f60
KH		 7666 switch (fixP->fx_r_type)
7667 {
7668 case BFD_RELOC_386_PLT32:
3e73aa7c 7669 case BFD_RELOC_X86_64_PLT32:
47926f60
KH		 7670 /* Make the jump instruction point to the address of the operand. At
7671 runtime we merely add the offset to the actual PLT entry. */
7672 value = -4;
7673 break;
31312f95 7674
13ae64f3
JJ		 7675 case BFD_RELOC_386_TLS_GD:
7676 case BFD_RELOC_386_TLS_LDM:
13ae64f3 7677 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 7678 case BFD_RELOC_386_TLS_IE:
7679 case BFD_RELOC_386_TLS_GOTIE:
67a4f2b7 7680 case BFD_RELOC_386_TLS_GOTDESC:
bffbf940
JJ		 7681 case BFD_RELOC_X86_64_TLSGD:
7682 case BFD_RELOC_X86_64_TLSLD:
7683 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7 7684 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
00f7efb6
JJ		 7685 value = 0; /* Fully resolved at runtime. No addend. */
7686 /* Fallthrough */
7687 case BFD_RELOC_386_TLS_LE:
7688 case BFD_RELOC_386_TLS_LDO_32:
7689 case BFD_RELOC_386_TLS_LE_32:
7690 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 7691 case BFD_RELOC_X86_64_DTPOFF64:
00f7efb6 7692 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113 7693 case BFD_RELOC_X86_64_TPOFF64:
00f7efb6
JJ		 7694 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7695 break;
7696
67a4f2b7
AO		 7697 case BFD_RELOC_386_TLS_DESC_CALL:
7698 case BFD_RELOC_X86_64_TLSDESC_CALL:
7699 value = 0; /* Fully resolved at runtime. No addend. */
7700 S_SET_THREAD_LOCAL (fixP->fx_addsy);
7701 fixP->fx_done = 0;
7702 return;
7703
00f7efb6
JJ		 7704 case BFD_RELOC_386_GOT32:
7705 case BFD_RELOC_X86_64_GOT32:
47926f60
KH		 7706 value = 0; /* Fully resolved at runtime. No addend. */
7707 break;
47926f60
KH		 7708
7709 case BFD_RELOC_VTABLE_INHERIT:
7710 case BFD_RELOC_VTABLE_ENTRY:
7711 fixP->fx_done = 0;
94f592af 7712 return;
47926f60
KH		 7713
7714 default:
7715 break;
7716 }
7717#endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
c6682705 7718 *valP = value;
f86103b7 7719#endif /* !defined (TE_Mach) */
3e73aa7c 7720
3e73aa7c 7721 /* Are we finished with this relocation now? */
c6682705 7722 if (fixP->fx_addsy == NULL)
3e73aa7c
JH		 7723 fixP->fx_done = 1;
7724 else if (use_rela_relocations)
7725 {
7726 fixP->fx_no_overflow = 1;
062cd5e7
AS		 7727 /* Remember value for tc_gen_reloc. */
7728 fixP->fx_addnumber = value;
3e73aa7c
JH		 7729 value = 0;
7730 }
f86103b7 7731
94f592af 7732 md_number_to_chars (p, value, fixP->fx_size);
252b5132 7733}
252b5132 7734\f
252b5132 7735char *
499ac353 7736md_atof (int type, char *litP, int *sizeP)
252b5132 7737{
499ac353
NC		 7738 /* This outputs the LITTLENUMs in REVERSE order;
7739 in accord with the bigendian 386. */
7740 return ieee_md_atof (type, litP, sizeP, FALSE);
252b5132
RH		 7741}
7742\f
2d545b82 7743static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
252b5132 7744
252b5132 7745static char *
e3bb37b5 7746output_invalid (int c)
252b5132 7747{
3882b010 7748 if (ISPRINT (c))
f9f21a03
L		 7749 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
7750 "'%c'", c);
252b5132 7751 else
f9f21a03 7752 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
2d545b82 7753 "(0x%x)", (unsigned char) c);
252b5132
RH		 7754 return output_invalid_buf;
7755}
7756
af6bdddf 7757/* REG_STRING starts *before* REGISTER_PREFIX. */
252b5132
RH		 7758
7759static const reg_entry *
4d1bb795 7760parse_real_register (char *reg_string, char **end_op)
252b5132 7761{
af6bdddf
AM		 7762 char *s = reg_string;
7763 char *p;
252b5132
RH		 7764 char reg_name_given[MAX_REG_NAME_SIZE + 1];
7765 const reg_entry *r;
7766
7767 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7768 if (*s == REGISTER_PREFIX)
7769 ++s;
7770
7771 if (is_space_char (*s))
7772 ++s;
7773
7774 p = reg_name_given;
af6bdddf 7775 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
252b5132
RH		 7776 {
7777 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
af6bdddf
AM		 7778 return (const reg_entry *) NULL;
7779 s++;
252b5132
RH		 7780 }
7781
6588847e
DN		 7782 /* For naked regs, make sure that we are not dealing with an identifier.
7783 This prevents confusing an identifier like `eax_var' with register
7784 `eax'. */
7785 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
7786 return (const reg_entry *) NULL;
7787
af6bdddf 7788 *end_op = s;
252b5132
RH		 7789
7790 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
7791
5f47d35b 7792 /* Handle floating point regs, allowing spaces in the (i) part. */
47926f60 7793 if (r == i386_regtab /* %st is first entry of table */)
5f47d35b 7794 {
5f47d35b
AM		 7795 if (is_space_char (*s))
7796 ++s;
7797 if (*s == '(')
7798 {
af6bdddf 7799 ++s;
5f47d35b
AM		 7800 if (is_space_char (*s))
7801 ++s;
7802 if (*s >= '0' && *s <= '7')
7803 {
db557034 7804 int fpr = *s - '0';
af6bdddf 7805 ++s;
5f47d35b
AM		 7806 if (is_space_char (*s))
7807 ++s;
7808 if (*s == ')')
7809 {
7810 *end_op = s + 1;
db557034
AM		 7811 r = hash_find (reg_hash, "st(0)");
7812 know (r);
7813 return r + fpr;
5f47d35b 7814 }
5f47d35b 7815 }
47926f60 7816 /* We have "%st(" then garbage. */
5f47d35b
AM		 7817 return (const reg_entry *) NULL;
7818 }
7819 }
7820
a60de03c
JB		 7821 if (r == NULL || allow_pseudo_reg)
7822 return r;
7823
0dfbf9d7 7824 if (operand_type_all_zero (&r->reg_type))
a60de03c
JB		 7825 return (const reg_entry *) NULL;
7826
192dc9c6
JB		 7827 if ((r->reg_type.bitfield.reg32
7828 || r->reg_type.bitfield.sreg3
7829 || r->reg_type.bitfield.control
7830 || r->reg_type.bitfield.debug
7831 || r->reg_type.bitfield.test)
7832 && !cpu_arch_flags.bitfield.cpui386)
7833 return (const reg_entry *) NULL;
7834
7835 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
7836 return (const reg_entry *) NULL;
7837
7838 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
7839 return (const reg_entry *) NULL;
7840
40f12533
L		 7841 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
7842 return (const reg_entry *) NULL;
7843
db51cc60 7844 /* Don't allow fake index register unless allow_index_reg isn't 0. */
a60de03c 7845 if (!allow_index_reg
db51cc60
L		 7846 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
7847 return (const reg_entry *) NULL;
7848
a60de03c
JB		 7849 if (((r->reg_flags & (RegRex64 | RegRex))
7850 || r->reg_type.bitfield.reg64)
40fb9820 7851 && (!cpu_arch_flags.bitfield.cpulm
0dfbf9d7 7852 || !operand_type_equal (&r->reg_type, &control))
1ae00879 7853 && flag_code != CODE_64BIT)
20f0a1fc 7854 return (const reg_entry *) NULL;
1ae00879 7855
b7240065
JB		 7856 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
7857 return (const reg_entry *) NULL;
7858
252b5132
RH		 7859 return r;
7860}
4d1bb795
JB		 7861
7862/* REG_STRING starts *before* REGISTER_PREFIX. */
7863
7864static const reg_entry *
7865parse_register (char *reg_string, char **end_op)
7866{
7867 const reg_entry *r;
7868
7869 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
7870 r = parse_real_register (reg_string, end_op);
7871 else
7872 r = NULL;
7873 if (!r)
7874 {
7875 char *save = input_line_pointer;
7876 char c;
7877 symbolS *symbolP;
7878
7879 input_line_pointer = reg_string;
7880 c = get_symbol_end ();
7881 symbolP = symbol_find (reg_string);
7882 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
7883 {
7884 const expressionS *e = symbol_get_value_expression (symbolP);
7885
7886 know (e->X_op == O_register);
4eed87de 7887 know (e->X_add_number >= 0
c3fe08fa 7888 && (valueT) e->X_add_number < i386_regtab_size);
4d1bb795
JB		 7889 r = i386_regtab + e->X_add_number;
7890 *end_op = input_line_pointer;
7891 }
7892 *input_line_pointer = c;
7893 input_line_pointer = save;
7894 }
7895 return r;
7896}
7897
7898int
7899i386_parse_name (char *name, expressionS *e, char *nextcharP)
7900{
7901 const reg_entry *r;
7902 char *end = input_line_pointer;
7903
7904 *end = *nextcharP;
7905 r = parse_register (name, &input_line_pointer);
7906 if (r && end <= input_line_pointer)
7907 {
7908 *nextcharP = *input_line_pointer;
7909 *input_line_pointer = 0;
7910 e->X_op = O_register;
7911 e->X_add_number = r - i386_regtab;
7912 return 1;
7913 }
7914 input_line_pointer = end;
7915 *end = 0;
7916 return 0;
7917}
7918
7919void
7920md_operand (expressionS *e)
7921{
7922 if (*input_line_pointer == REGISTER_PREFIX)
7923 {
7924 char *end;
7925 const reg_entry *r = parse_real_register (input_line_pointer, &end);
7926
7927 if (r)
7928 {
7929 e->X_op = O_register;
7930 e->X_add_number = r - i386_regtab;
7931 input_line_pointer = end;
7932 }
7933 }
7934}
7935
252b5132 7936\f
4cc782b5 7937#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
12b55ccc 7938const char *md_shortopts = "kVQ:sqn";
252b5132 7939#else
12b55ccc 7940const char *md_shortopts = "qn";
252b5132 7941#endif
6e0b89ee 7942
3e73aa7c 7943#define OPTION_32 (OPTION_MD_BASE + 0)
b3b91714
AM		 7944#define OPTION_64 (OPTION_MD_BASE + 1)
7945#define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9103f4f4
L		 7946#define OPTION_MARCH (OPTION_MD_BASE + 3)
7947#define OPTION_MTUNE (OPTION_MD_BASE + 4)
1efbbeb4
L		 7948#define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7949#define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7950#define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7951#define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7952#define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
c0f3af97 7953#define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
daf50ae7 7954#define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
b3b91714 7955
99ad8390
NC		 7956struct option md_longopts[] =
7957{
3e73aa7c 7958 {"32", no_argument, NULL, OPTION_32},
99ad8390 7959#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c 7960 {"64", no_argument, NULL, OPTION_64},
6e0b89ee 7961#endif
b3b91714 7962 {"divide", no_argument, NULL, OPTION_DIVIDE},
9103f4f4
L		 7963 {"march", required_argument, NULL, OPTION_MARCH},
7964 {"mtune", required_argument, NULL, OPTION_MTUNE},
1efbbeb4
L		 7965 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
7966 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
7967 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
7968 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
7969 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
c0f3af97 7970 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
daf50ae7 7971 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
252b5132
RH		 7972 {NULL, no_argument, NULL, 0}
7973};
7974size_t md_longopts_size = sizeof (md_longopts);
7975
7976int
9103f4f4 7977md_parse_option (int c, char *arg)
252b5132 7978{
9103f4f4 7979 unsigned int i;
6305a203 7980 char *arch, *next;
9103f4f4 7981
252b5132
RH		 7982 switch (c)
7983 {
12b55ccc
L		 7984 case 'n':
7985 optimize_align_code = 0;
7986 break;
7987
a38cf1db
AM		 7988 case 'q':
7989 quiet_warnings = 1;
252b5132
RH		 7990 break;
7991
7992#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
a38cf1db
AM		 7993 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7994 should be emitted or not. FIXME: Not implemented. */
7995 case 'Q':
252b5132
RH		 7996 break;
7997
7998 /* -V: SVR4 argument to print version ID. */
7999 case 'V':
8000 print_version_id ();
8001 break;
8002
a38cf1db
AM		 8003 /* -k: Ignore for FreeBSD compatibility. */
8004 case 'k':
252b5132 8005 break;
4cc782b5
ILT		 8006
8007 case 's':
8008 /* -s: On i386 Solaris, this tells the native assembler to use
29b0f896 8009 .stab instead of .stab.excl. We always use .stab anyhow. */
4cc782b5 8010 break;
99ad8390
NC		 8011#endif
8012#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
3e73aa7c
JH		 8013 case OPTION_64:
8014 {
8015 const char **list, **l;
8016
3e73aa7c
JH		 8017 list = bfd_target_list ();
8018 for (l = list; *l != NULL; l++)
8620418b 8019 if (CONST_STRNEQ (*l, "elf64-x86-64")
99ad8390
NC		 8020 || strcmp (*l, "coff-x86-64") == 0
8021 || strcmp (*l, "pe-x86-64") == 0
8022 || strcmp (*l, "pei-x86-64") == 0)
6e0b89ee
AM		 8023 {
8024 default_arch = "x86_64";
8025 break;
8026 }
3e73aa7c 8027 if (*l == NULL)
6e0b89ee 8028 as_fatal (_("No compiled in support for x86_64"));
3e73aa7c
JH		 8029 free (list);
8030 }
8031 break;
8032#endif
252b5132 8033
6e0b89ee
AM		 8034 case OPTION_32:
8035 default_arch = "i386";
8036 break;
8037
b3b91714
AM		 8038 case OPTION_DIVIDE:
8039#ifdef SVR4_COMMENT_CHARS
8040 {
8041 char *n, *t;
8042 const char *s;
8043
8044 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
8045 t = n;
8046 for (s = i386_comment_chars; *s != '\0'; s++)
8047 if (*s != '/')
8048 *t++ = *s;
8049 *t = '\0';
8050 i386_comment_chars = n;
8051 }
8052#endif
8053 break;
8054
9103f4f4 8055 case OPTION_MARCH:
6305a203
L		 8056 arch = xstrdup (arg);
8057 do
9103f4f4 8058 {
6305a203
L		 8059 if (*arch == '.')
8060 as_fatal (_("Invalid -march= option: `%s'"), arg);
8061 next = strchr (arch, '+');
8062 if (next)
8063 *next++ = '\0';
8064 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
9103f4f4 8065 {
6305a203 8066 if (strcmp (arch, cpu_arch [i].name) == 0)
ccc9c027 8067 {
6305a203
L		 8068 /* Processor. */
8069 cpu_arch_name = cpu_arch[i].name;
8070 cpu_sub_arch_name = NULL;
8071 cpu_arch_flags = cpu_arch[i].flags;
8072 cpu_arch_isa = cpu_arch[i].type;
8073 cpu_arch_isa_flags = cpu_arch[i].flags;
8074 if (!cpu_arch_tune_set)
8075 {
8076 cpu_arch_tune = cpu_arch_isa;
8077 cpu_arch_tune_flags = cpu_arch_isa_flags;
8078 }
8079 break;
8080 }
8081 else if (*cpu_arch [i].name == '.'
8082 && strcmp (arch, cpu_arch [i].name + 1) == 0)
8083 {
8084 /* ISA entension. */
8085 i386_cpu_flags flags;
8086 flags = cpu_flags_or (cpu_arch_flags,
8087 cpu_arch[i].flags);
0dfbf9d7 8088 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
6305a203
L		 8089 {
8090 if (cpu_sub_arch_name)
8091 {
8092 char *name = cpu_sub_arch_name;
8093 cpu_sub_arch_name = concat (name,
8094 cpu_arch[i].name,
1bf57e9f 8095 (const char *) NULL);
6305a203
L		 8096 free (name);
8097 }
8098 else
8099 cpu_sub_arch_name = xstrdup (cpu_arch[i].name);
8100 cpu_arch_flags = flags;
8101 }
8102 break;
ccc9c027 8103 }
9103f4f4 8104 }
6305a203
L		 8105
8106 if (i >= ARRAY_SIZE (cpu_arch))
8107 as_fatal (_("Invalid -march= option: `%s'"), arg);
8108
8109 arch = next;
9103f4f4 8110 }
6305a203 8111 while (next != NULL );
9103f4f4
L		 8112 break;
8113
8114 case OPTION_MTUNE:
8115 if (*arg == '.')
8116 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8117 for (i = 0; i < ARRAY_SIZE (cpu_arch); i++)
8118 {
8119 if (strcmp (arg, cpu_arch [i].name) == 0)
8120 {
ccc9c027 8121 cpu_arch_tune_set = 1;
9103f4f4
L		 8122 cpu_arch_tune = cpu_arch [i].type;
8123 cpu_arch_tune_flags = cpu_arch[i].flags;
8124 break;
8125 }
8126 }
8127 if (i >= ARRAY_SIZE (cpu_arch))
8128 as_fatal (_("Invalid -mtune= option: `%s'"), arg);
8129 break;
8130
1efbbeb4
L		 8131 case OPTION_MMNEMONIC:
8132 if (strcasecmp (arg, "att") == 0)
8133 intel_mnemonic = 0;
8134 else if (strcasecmp (arg, "intel") == 0)
8135 intel_mnemonic = 1;
8136 else
8137 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg);
8138 break;
8139
8140 case OPTION_MSYNTAX:
8141 if (strcasecmp (arg, "att") == 0)
8142 intel_syntax = 0;
8143 else if (strcasecmp (arg, "intel") == 0)
8144 intel_syntax = 1;
8145 else
8146 as_fatal (_("Invalid -msyntax= option: `%s'"), arg);
8147 break;
8148
8149 case OPTION_MINDEX_REG:
8150 allow_index_reg = 1;
8151 break;
8152
8153 case OPTION_MNAKED_REG:
8154 allow_naked_reg = 1;
8155 break;
8156
8157 case OPTION_MOLD_GCC:
8158 old_gcc = 1;
1efbbeb4
L		 8159 break;
8160
c0f3af97
L		 8161 case OPTION_MSSE2AVX:
8162 sse2avx = 1;
8163 break;
8164
daf50ae7
L		 8165 case OPTION_MSSE_CHECK:
8166 if (strcasecmp (arg, "error") == 0)
8167 sse_check = sse_check_error;
8168 else if (strcasecmp (arg, "warning") == 0)
8169 sse_check = sse_check_warning;
8170 else if (strcasecmp (arg, "none") == 0)
8171 sse_check = sse_check_none;
8172 else
8173 as_fatal (_("Invalid -msse-check= option: `%s'"), arg);
8174 break;
8175
252b5132
RH		 8176 default:
8177 return 0;
8178 }
8179 return 1;
8180}
8181
8182void
8183md_show_usage (stream)
8184 FILE *stream;
8185{
4cc782b5
ILT		 8186#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8187 fprintf (stream, _("\
a38cf1db
AM		 8188 -Q ignored\n\
8189 -V print assembler version number\n\
b3b91714
AM		 8190 -k ignored\n"));
8191#endif
8192 fprintf (stream, _("\
12b55ccc 8193 -n Do not optimize code alignment\n\
b3b91714
AM		 8194 -q quieten some warnings\n"));
8195#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8196 fprintf (stream, _("\
a38cf1db 8197 -s ignored\n"));
b3b91714 8198#endif
751d281c
L		 8199#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8200 fprintf (stream, _("\
8201 --32/--64 generate 32bit/64bit code\n"));
8202#endif
b3b91714
AM		 8203#ifdef SVR4_COMMENT_CHARS
8204 fprintf (stream, _("\
8205 --divide do not treat `/' as a comment character\n"));
a38cf1db
AM		 8206#else
8207 fprintf (stream, _("\
b3b91714 8208 --divide ignored\n"));
4cc782b5 8209#endif
9103f4f4 8210 fprintf (stream, _("\
6305a203
L		 8211 -march=CPU[,+EXTENSION...]\n\
8212 generate code for CPU and EXTENSION, CPU is one of:\n\
2cb4f3d5
L		 8213 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8214 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8215 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8216 generic32, generic64\n\
599121aa
L		 8217 EXTENSION is combination of:\n\
8218 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
f1f8f695 8219 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
bd5295b2
L		 8220 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8221 sse5, svme, abm, padlock\n"));
6305a203 8222 fprintf (stream, _("\
2cb4f3d5
L		 8223 -mtune=CPU optimize for CPU, CPU is one of:\n\
8224 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8225 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
bd5295b2 8226 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
2cb4f3d5 8227 generic32, generic64\n"));
ba104c83 8228 fprintf (stream, _("\
c0f3af97
L		 8229 -msse2avx encode SSE instructions with VEX prefix\n"));
8230 fprintf (stream, _("\
daf50ae7
L		 8231 -msse-check=[none|error|warning]\n\
8232 check SSE instructions\n"));
8233 fprintf (stream, _("\
ba104c83
L		 8234 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8235 fprintf (stream, _("\
8236 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8237 fprintf (stream, _("\
8238 -mindex-reg support pseudo index registers\n"));
8239 fprintf (stream, _("\
8240 -mnaked-reg don't require `%%' prefix for registers\n"));
8241 fprintf (stream, _("\
8242 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
252b5132
RH		 8243}
8244
3e73aa7c 8245#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
872ce6ff 8246 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
252b5132
RH		 8247
8248/* Pick the target format to use. */
8249
47926f60 8250const char *
e3bb37b5 8251i386_target_format (void)
252b5132 8252{
3e73aa7c 8253 if (!strcmp (default_arch, "x86_64"))
9103f4f4
L		 8254 {
8255 set_code_flag (CODE_64BIT);
0dfbf9d7 8256 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8257 {
8258 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8259 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8260 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8261 cpu_arch_isa_flags.bitfield.cpui486 = 1;
8262 cpu_arch_isa_flags.bitfield.cpui586 = 1;
8263 cpu_arch_isa_flags.bitfield.cpui686 = 1;
bd5295b2 8264 cpu_arch_isa_flags.bitfield.cpuclflush = 1;
40fb9820 8265 cpu_arch_isa_flags.bitfield.cpummx= 1;
40fb9820
L		 8266 cpu_arch_isa_flags.bitfield.cpusse = 1;
8267 cpu_arch_isa_flags.bitfield.cpusse2 = 1;
8268 }
0dfbf9d7 8269 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8270 {
8271 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8272 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8273 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8274 cpu_arch_tune_flags.bitfield.cpui486 = 1;
8275 cpu_arch_tune_flags.bitfield.cpui586 = 1;
8276 cpu_arch_tune_flags.bitfield.cpui686 = 1;
bd5295b2 8277 cpu_arch_tune_flags.bitfield.cpuclflush = 1;
40fb9820 8278 cpu_arch_tune_flags.bitfield.cpummx= 1;
40fb9820
L		 8279 cpu_arch_tune_flags.bitfield.cpusse = 1;
8280 cpu_arch_tune_flags.bitfield.cpusse2 = 1;
8281 }
9103f4f4 8282 }
3e73aa7c 8283 else if (!strcmp (default_arch, "i386"))
9103f4f4
L		 8284 {
8285 set_code_flag (CODE_32BIT);
0dfbf9d7 8286 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
40fb9820
L		 8287 {
8288 cpu_arch_isa_flags.bitfield.cpui186 = 1;
8289 cpu_arch_isa_flags.bitfield.cpui286 = 1;
8290 cpu_arch_isa_flags.bitfield.cpui386 = 1;
8291 }
0dfbf9d7 8292 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
40fb9820
L		 8293 {
8294 cpu_arch_tune_flags.bitfield.cpui186 = 1;
8295 cpu_arch_tune_flags.bitfield.cpui286 = 1;
8296 cpu_arch_tune_flags.bitfield.cpui386 = 1;
8297 }
9103f4f4 8298 }
3e73aa7c
JH		 8299 else
8300 as_fatal (_("Unknown architecture"));
252b5132
RH		 8301 switch (OUTPUT_FLAVOR)
8302 {
872ce6ff
L		 8303#ifdef TE_PEP
8304 case bfd_target_coff_flavour:
b01ee69d 8305 return flag_code == CODE_64BIT ? COFF_TARGET_FORMAT : "pe-i386";
872ce6ff
L		 8306 break;
8307#endif
4c63da97
AM		 8308#ifdef OBJ_MAYBE_AOUT
8309 case bfd_target_aout_flavour:
47926f60 8310 return AOUT_TARGET_FORMAT;
4c63da97
AM		 8311#endif
8312#ifdef OBJ_MAYBE_COFF
252b5132
RH		 8313 case bfd_target_coff_flavour:
8314 return "coff-i386";
4c63da97 8315#endif
3e73aa7c 8316#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
252b5132 8317 case bfd_target_elf_flavour:
3e73aa7c 8318 {
e5cb08ac 8319 if (flag_code == CODE_64BIT)
4fa24527
JB		 8320 {
8321 object_64bit = 1;
8322 use_rela_relocations = 1;
8323 }
9d7cbccd 8324 return flag_code == CODE_64BIT ? ELF_TARGET_FORMAT64 : ELF_TARGET_FORMAT;
3e73aa7c 8325 }
4c63da97 8326#endif
252b5132
RH		 8327 default:
8328 abort ();
8329 return NULL;
8330 }
8331}
8332
47926f60 8333#endif /* OBJ_MAYBE_ more than one */
a847613f
AM		 8334
8335#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
e3bb37b5
L		 8336void
8337i386_elf_emit_arch_note (void)
a847613f 8338{
718ddfc0 8339 if (IS_ELF && cpu_arch_name != NULL)
a847613f
AM		 8340 {
8341 char *p;
8342 asection *seg = now_seg;
8343 subsegT subseg = now_subseg;
8344 Elf_Internal_Note i_note;
8345 Elf_External_Note e_note;
8346 asection *note_secp;
8347 int len;
8348
8349 /* Create the .note section. */
8350 note_secp = subseg_new (".note", 0);
8351 bfd_set_section_flags (stdoutput,
8352 note_secp,
8353 SEC_HAS_CONTENTS | SEC_READONLY);
8354
8355 /* Process the arch string. */
8356 len = strlen (cpu_arch_name);
8357
8358 i_note.namesz = len + 1;
8359 i_note.descsz = 0;
8360 i_note.type = NT_ARCH;
8361 p = frag_more (sizeof (e_note.namesz));
8362 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
8363 p = frag_more (sizeof (e_note.descsz));
8364 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
8365 p = frag_more (sizeof (e_note.type));
8366 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
8367 p = frag_more (len + 1);
8368 strcpy (p, cpu_arch_name);
8369
8370 frag_align (2, 0, 0);
8371
8372 subseg_set (seg, subseg);
8373 }
8374}
8375#endif
252b5132 8376\f
252b5132
RH		 8377symbolS *
8378md_undefined_symbol (name)
8379 char *name;
8380{
18dc2407
ILT		 8381 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
8382 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
8383 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
8384 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
24eab124
AM		 8385 {
8386 if (!GOT_symbol)
8387 {
8388 if (symbol_find (name))
8389 as_bad (_("GOT already in symbol table"));
8390 GOT_symbol = symbol_new (name, undefined_section,
8391 (valueT) 0, &zero_address_frag);
8392 };
8393 return GOT_symbol;
8394 }
252b5132
RH		 8395 return 0;
8396}
8397
8398/* Round up a section size to the appropriate boundary. */
47926f60 8399
252b5132
RH		 8400valueT
8401md_section_align (segment, size)
ab9da554 8402 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 8403 valueT size;
8404{
4c63da97
AM		 8405#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8406 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
8407 {
8408 /* For a.out, force the section size to be aligned. If we don't do
8409 this, BFD will align it for us, but it will not write out the
8410 final bytes of the section. This may be a bug in BFD, but it is
8411 easier to fix it here since that is how the other a.out targets
8412 work. */
8413 int align;
8414
8415 align = bfd_get_section_alignment (stdoutput, segment);
8416 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
8417 }
252b5132
RH		 8418#endif
8419
8420 return size;
8421}
8422
8423/* On the i386, PC-relative offsets are relative to the start of the
8424 next instruction. That is, the address of the offset, plus its
8425 size, since the offset is always the last part of the insn. */
8426
8427long
e3bb37b5 8428md_pcrel_from (fixS *fixP)
252b5132
RH		 8429{
8430 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
8431}
8432
8433#ifndef I386COFF
8434
8435static void
e3bb37b5 8436s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132 8437{
29b0f896 8438 int temp;
252b5132 8439
8a75718c
JB		 8440#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8441 if (IS_ELF)
8442 obj_elf_section_change_hook ();
8443#endif
252b5132
RH		 8444 temp = get_absolute_expression ();
8445 subseg_set (bss_section, (subsegT) temp);
8446 demand_empty_rest_of_line ();
8447}
8448
8449#endif
8450
252b5132 8451void
e3bb37b5 8452i386_validate_fix (fixS *fixp)
252b5132
RH		 8453{
8454 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
8455 {
23df1078
JH		 8456 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
8457 {
4fa24527 8458 if (!object_64bit)
23df1078
JH		 8459 abort ();
8460 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
8461 }
8462 else
8463 {
4fa24527 8464 if (!object_64bit)
d6ab8113
JB		 8465 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
8466 else
8467 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
23df1078 8468 }
252b5132
RH		 8469 fixp->fx_subsy = 0;
8470 }
8471}
8472
252b5132
RH		 8473arelent *
8474tc_gen_reloc (section, fixp)
ab9da554 8475 asection *section ATTRIBUTE_UNUSED;
252b5132
RH		 8476 fixS *fixp;
8477{
8478 arelent *rel;
8479 bfd_reloc_code_real_type code;
8480
8481 switch (fixp->fx_r_type)
8482 {
3e73aa7c
JH		 8483 case BFD_RELOC_X86_64_PLT32:
8484 case BFD_RELOC_X86_64_GOT32:
8485 case BFD_RELOC_X86_64_GOTPCREL:
252b5132
RH		 8486 case BFD_RELOC_386_PLT32:
8487 case BFD_RELOC_386_GOT32:
8488 case BFD_RELOC_386_GOTOFF:
8489 case BFD_RELOC_386_GOTPC:
13ae64f3
JJ		 8490 case BFD_RELOC_386_TLS_GD:
8491 case BFD_RELOC_386_TLS_LDM:
8492 case BFD_RELOC_386_TLS_LDO_32:
8493 case BFD_RELOC_386_TLS_IE_32:
37e55690
JJ		 8494 case BFD_RELOC_386_TLS_IE:
8495 case BFD_RELOC_386_TLS_GOTIE:
13ae64f3
JJ		 8496 case BFD_RELOC_386_TLS_LE_32:
8497 case BFD_RELOC_386_TLS_LE:
67a4f2b7
AO		 8498 case BFD_RELOC_386_TLS_GOTDESC:
8499 case BFD_RELOC_386_TLS_DESC_CALL:
bffbf940
JJ		 8500 case BFD_RELOC_X86_64_TLSGD:
8501 case BFD_RELOC_X86_64_TLSLD:
8502 case BFD_RELOC_X86_64_DTPOFF32:
d6ab8113 8503 case BFD_RELOC_X86_64_DTPOFF64:
bffbf940
JJ		 8504 case BFD_RELOC_X86_64_GOTTPOFF:
8505 case BFD_RELOC_X86_64_TPOFF32:
d6ab8113
JB		 8506 case BFD_RELOC_X86_64_TPOFF64:
8507 case BFD_RELOC_X86_64_GOTOFF64:
8508 case BFD_RELOC_X86_64_GOTPC32:
7b81dfbb
AJ		 8509 case BFD_RELOC_X86_64_GOT64:
8510 case BFD_RELOC_X86_64_GOTPCREL64:
8511 case BFD_RELOC_X86_64_GOTPC64:
8512 case BFD_RELOC_X86_64_GOTPLT64:
8513 case BFD_RELOC_X86_64_PLTOFF64:
67a4f2b7
AO		 8514 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8515 case BFD_RELOC_X86_64_TLSDESC_CALL:
252b5132
RH		 8516 case BFD_RELOC_RVA:
8517 case BFD_RELOC_VTABLE_ENTRY:
8518 case BFD_RELOC_VTABLE_INHERIT:
6482c264
NC		 8519#ifdef TE_PE
8520 case BFD_RELOC_32_SECREL:
8521#endif
252b5132
RH		 8522 code = fixp->fx_r_type;
8523 break;
dbbaec26
L		 8524 case BFD_RELOC_X86_64_32S:
8525 if (!fixp->fx_pcrel)
8526 {
8527 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8528 code = fixp->fx_r_type;
8529 break;
8530 }
252b5132 8531 default:
93382f6d 8532 if (fixp->fx_pcrel)
252b5132 8533 {
93382f6d
AM		 8534 switch (fixp->fx_size)
8535 {
8536 default:
b091f402
AM		 8537 as_bad_where (fixp->fx_file, fixp->fx_line,
8538 _("can not do %d byte pc-relative relocation"),
8539 fixp->fx_size);
93382f6d
AM		 8540 code = BFD_RELOC_32_PCREL;
8541 break;
8542 case 1: code = BFD_RELOC_8_PCREL; break;
8543 case 2: code = BFD_RELOC_16_PCREL; break;
8544 case 4: code = BFD_RELOC_32_PCREL; break;
d6ab8113
JB		 8545#ifdef BFD64
8546 case 8: code = BFD_RELOC_64_PCREL; break;
8547#endif
93382f6d
AM		 8548 }
8549 }
8550 else
8551 {
8552 switch (fixp->fx_size)
8553 {
8554 default:
b091f402
AM		 8555 as_bad_where (fixp->fx_file, fixp->fx_line,
8556 _("can not do %d byte relocation"),
8557 fixp->fx_size);
93382f6d
AM		 8558 code = BFD_RELOC_32;
8559 break;
8560 case 1: code = BFD_RELOC_8; break;
8561 case 2: code = BFD_RELOC_16; break;
8562 case 4: code = BFD_RELOC_32; break;
937149dd 8563#ifdef BFD64
3e73aa7c 8564 case 8: code = BFD_RELOC_64; break;
937149dd 8565#endif
93382f6d 8566 }
252b5132
RH		 8567 }
8568 break;
8569 }
252b5132 8570
d182319b
JB		 8571 if ((code == BFD_RELOC_32
8572 || code == BFD_RELOC_32_PCREL
8573 || code == BFD_RELOC_X86_64_32S)
252b5132
RH		 8574 && GOT_symbol
8575 && fixp->fx_addsy == GOT_symbol)
3e73aa7c 8576 {
4fa24527 8577 if (!object_64bit)
d6ab8113
JB		 8578 code = BFD_RELOC_386_GOTPC;
8579 else
8580 code = BFD_RELOC_X86_64_GOTPC32;
3e73aa7c 8581 }
7b81dfbb
AJ		 8582 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
8583 && GOT_symbol
8584 && fixp->fx_addsy == GOT_symbol)
8585 {
8586 code = BFD_RELOC_X86_64_GOTPC64;
8587 }
252b5132
RH		 8588
8589 rel = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 8590 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
8591 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 8592
8593 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
c87db184 8594
3e73aa7c
JH		 8595 if (!use_rela_relocations)
8596 {
8597 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8598 vtable entry to be used in the relocation's section offset. */
8599 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
8600 rel->address = fixp->fx_offset;
252b5132 8601
c6682705 8602 rel->addend = 0;
3e73aa7c
JH		 8603 }
8604 /* Use the rela in 64bit mode. */
252b5132 8605 else
3e73aa7c 8606 {
062cd5e7
AS		 8607 if (!fixp->fx_pcrel)
8608 rel->addend = fixp->fx_offset;
8609 else
8610 switch (code)
8611 {
8612 case BFD_RELOC_X86_64_PLT32:
8613 case BFD_RELOC_X86_64_GOT32:
8614 case BFD_RELOC_X86_64_GOTPCREL:
bffbf940
JJ		 8615 case BFD_RELOC_X86_64_TLSGD:
8616 case BFD_RELOC_X86_64_TLSLD:
8617 case BFD_RELOC_X86_64_GOTTPOFF:
67a4f2b7
AO		 8618 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
8619 case BFD_RELOC_X86_64_TLSDESC_CALL:
062cd5e7
AS		 8620 rel->addend = fixp->fx_offset - fixp->fx_size;
8621 break;
8622 default:
8623 rel->addend = (section->vma
8624 - fixp->fx_size
8625 + fixp->fx_addnumber
8626 + md_pcrel_from (fixp));
8627 break;
8628 }
3e73aa7c
JH		 8629 }
8630
252b5132
RH		 8631 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
8632 if (rel->howto == NULL)
8633 {
8634 as_bad_where (fixp->fx_file, fixp->fx_line,
d0b47220 8635 _("cannot represent relocation type %s"),
252b5132
RH		 8636 bfd_get_reloc_code_name (code));
8637 /* Set howto to a garbage value so that we can keep going. */
8638 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
8639 assert (rel->howto != NULL);
8640 }
8641
8642 return rel;
8643}
8644
64a0c779
DN		 8645\f
8646/* Parse operands using Intel syntax. This implements a recursive descent
8647 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8648 Programmer's Guide.
8649
8650 FIXME: We do not recognize the full operand grammar defined in the MASM
8651 documentation. In particular, all the structure/union and
8652 high-level macro operands are missing.
8653
8654 Uppercase words are terminals, lower case words are non-terminals.
8655 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8656 bars '|' denote choices. Most grammar productions are implemented in
8657 functions called 'intel_<production>'.
8658
8659 Initial production is 'expr'.
8660
9306ca4a 8661 addOp + | -
64a0c779
DN		 8662
8663 alpha [a-zA-Z]
8664
9306ca4a
JB		 8665 binOp & | AND | \| | OR | ^ | XOR
8666
64a0c779
DN		 8667 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8668
8669 constant digits [[ radixOverride ]]
8670
c0f3af97 8671 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
64a0c779
DN		 8672
8673 digits decdigit
b77a7acd
AJ		 8674 | digits decdigit
8675 | digits hexdigit
64a0c779
DN		 8676
8677 decdigit [0-9]
8678
9306ca4a
JB		 8679 e04 e04 addOp e05
8680 | e05
8681
8682 e05 e05 binOp e06
b77a7acd 8683 | e06
64a0c779
DN		 8684
8685 e06 e06 mulOp e09
b77a7acd 8686 | e09
64a0c779
DN		 8687
8688 e09 OFFSET e10
a724f0f4
JB		 8689 | SHORT e10
8690 | + e10
8691 | - e10
9306ca4a
JB		 8692 | ~ e10
8693 | NOT e10
64a0c779
DN		 8694 | e09 PTR e10
8695 | e09 : e10
8696 | e10
8697
8698 e10 e10 [ expr ]
b77a7acd 8699 | e11
64a0c779
DN		 8700
8701 e11 ( expr )
b77a7acd 8702 | [ expr ]
64a0c779
DN		 8703 | constant
8704 | dataType
8705 | id
8706 | $
8707 | register
8708
a724f0f4 8709 => expr expr cmpOp e04
9306ca4a 8710 | e04
64a0c779
DN		 8711
8712 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
b77a7acd 8713 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
64a0c779
DN		 8714
8715 hexdigit a | b | c | d | e | f
b77a7acd 8716 | A | B | C | D | E | F
64a0c779
DN		 8717
8718 id alpha
b77a7acd 8719 | id alpha
64a0c779
DN		 8720 | id decdigit
8721
9306ca4a 8722 mulOp * | / | % | MOD | << | SHL | >> | SHR
64a0c779
DN		 8723
8724 quote " | '
8725
8726 register specialRegister
b77a7acd 8727 | gpRegister
64a0c779
DN		 8728 | byteRegister
8729
8730 segmentRegister CS | DS | ES | FS | GS | SS
8731
9306ca4a 8732 specialRegister CR0 | CR2 | CR3 | CR4
b77a7acd 8733 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
64a0c779
DN		 8734 | TR3 | TR4 | TR5 | TR6 | TR7
8735
64a0c779
DN		 8736 We simplify the grammar in obvious places (e.g., register parsing is
8737 done by calling parse_register) and eliminate immediate left recursion
8738 to implement a recursive-descent parser.
8739
a724f0f4
JB		 8740 expr e04 expr'
8741
8742 expr' cmpOp e04 expr'
8743 | Empty
9306ca4a
JB		 8744
8745 e04 e05 e04'
8746
8747 e04' addOp e05 e04'
8748 | Empty
64a0c779
DN		 8749
8750 e05 e06 e05'
8751
9306ca4a 8752 e05' binOp e06 e05'
b77a7acd 8753 | Empty
64a0c779
DN		 8754
8755 e06 e09 e06'
8756
8757 e06' mulOp e09 e06'
b77a7acd 8758 | Empty
64a0c779
DN		 8759
8760 e09 OFFSET e10 e09'
a724f0f4
JB		 8761 | SHORT e10'
8762 | + e10'
8763 | - e10'
8764 | ~ e10'
8765 | NOT e10'
b77a7acd 8766 | e10 e09'
64a0c779
DN		 8767
8768 e09' PTR e10 e09'
b77a7acd 8769 | : e10 e09'
64a0c779
DN		 8770 | Empty
8771
8772 e10 e11 e10'
8773
8774 e10' [ expr ] e10'
b77a7acd 8775 | Empty
64a0c779
DN		 8776
8777 e11 ( expr )
b77a7acd 8778 | [ expr ]
64a0c779
DN		 8779 | BYTE
8780 | WORD
8781 | DWORD
9306ca4a 8782 | FWORD
64a0c779 8783 | QWORD
9306ca4a
JB		 8784 | TBYTE
8785 | OWORD
8786 | XMMWORD
c0f3af97 8787 | YMMWORD
64a0c779
DN		 8788 | .
8789 | $
8790 | register
8791 | id
8792 | constant */
8793
8794/* Parsing structure for the intel syntax parser. Used to implement the
8795 semantic actions for the operand grammar. */
8796struct intel_parser_s
8797 {
8798 char *op_string; /* The string being parsed. */
8799 int got_a_float; /* Whether the operand is a float. */
4a1805b1 8800 int op_modifier; /* Operand modifier. */
64a0c779 8801 int is_mem; /* 1 if operand is memory reference. */
4eed87de
AM		 8802 int in_offset; /* >=1 if parsing operand of offset. */
8803 int in_bracket; /* >=1 if parsing operand in brackets. */
64a0c779
DN		 8804 const reg_entry *reg; /* Last register reference found. */
8805 char *disp; /* Displacement string being built. */
a724f0f4 8806 char *next_operand; /* Resume point when splitting operands. */
64a0c779
DN		 8807 };
8808
8809static struct intel_parser_s intel_parser;
8810
8811/* Token structure for parsing intel syntax. */
8812struct intel_token
8813 {
8814 int code; /* Token code. */
8815 const reg_entry *reg; /* Register entry for register tokens. */
8816 char *str; /* String representation. */
8817 };
8818
8819static struct intel_token cur_token, prev_token;
8820
50705ef4
AM		 8821/* Token codes for the intel parser. Since T_SHORT is already used
8822 by COFF, undefine it first to prevent a warning. */
64a0c779
DN		 8823#define T_NIL -1
8824#define T_CONST 1
8825#define T_REG 2
8826#define T_BYTE 3
8827#define T_WORD 4
9306ca4a
JB		 8828#define T_DWORD 5
8829#define T_FWORD 6
8830#define T_QWORD 7
8831#define T_TBYTE 8
8832#define T_XMMWORD 9
50705ef4 8833#undef T_SHORT
9306ca4a
JB		 8834#define T_SHORT 10
8835#define T_OFFSET 11
8836#define T_PTR 12
8837#define T_ID 13
8838#define T_SHL 14
8839#define T_SHR 15
c0f3af97 8840#define T_YMMWORD 16
64a0c779
DN		 8841
8842/* Prototypes for intel parser functions. */
e3bb37b5
L		 8843static int intel_match_token (int);
8844static void intel_putback_token (void);
8845static void intel_get_token (void);
8846static int intel_expr (void);
8847static int intel_e04 (void);
8848static int intel_e05 (void);
8849static int intel_e06 (void);
8850static int intel_e09 (void);
8851static int intel_e10 (void);
8852static int intel_e11 (void);
64a0c779 8853
64a0c779 8854static int
e3bb37b5 8855i386_intel_operand (char *operand_string, int got_a_float)
64a0c779
DN		 8856{
8857 int ret;
8858 char *p;
fc0763e6
JB		 8859 const reg_entry *final_base = i.base_reg;
8860 const reg_entry *final_index = i.index_reg;
64a0c779 8861
a724f0f4
JB		 8862 p = intel_parser.op_string = xstrdup (operand_string);
8863 intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1);
8864
8865 for (;;)
64a0c779 8866 {
a724f0f4
JB		 8867 /* Initialize token holders. */
8868 cur_token.code = prev_token.code = T_NIL;
8869 cur_token.reg = prev_token.reg = NULL;
8870 cur_token.str = prev_token.str = NULL;
8871
8872 /* Initialize parser structure. */
8873 intel_parser.got_a_float = got_a_float;
8874 intel_parser.op_modifier = 0;
8875 intel_parser.is_mem = 0;
8876 intel_parser.in_offset = 0;
8877 intel_parser.in_bracket = 0;
8878 intel_parser.reg = NULL;
8879 intel_parser.disp[0] = '\0';
8880 intel_parser.next_operand = NULL;
8881
fc0763e6
JB		 8882 i.base_reg = NULL;
8883 i.index_reg = NULL;
8884
a724f0f4
JB		 8885 /* Read the first token and start the parser. */
8886 intel_get_token ();
8887 ret = intel_expr ();
8888
8889 if (!ret)
8890 break;
8891
9306ca4a
JB		 8892 if (cur_token.code != T_NIL)
8893 {
8894 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8895 current_templates->start->name, cur_token.str);
8896 ret = 0;
8897 }
64a0c779
DN		 8898 /* If we found a memory reference, hand it over to i386_displacement
8899 to fill in the rest of the operand fields. */
9306ca4a 8900 else if (intel_parser.is_mem)
64a0c779
DN		 8901 {
8902 if ((i.mem_operands == 1
40fb9820 8903 && !current_templates->start->opcode_modifier.isstring)
64a0c779
DN		 8904 || i.mem_operands == 2)
8905 {
8906 as_bad (_("too many memory references for '%s'"),
8907 current_templates->start->name);
8908 ret = 0;
8909 }
8910 else
8911 {
8912 char *s = intel_parser.disp;
64a0c779 8913
a724f0f4
JB		 8914 if (!quiet_warnings && intel_parser.is_mem < 0)
8915 /* See the comments in intel_bracket_expr. */
8916 as_warn (_("Treating `%s' as memory reference"), operand_string);
8917
64a0c779
DN		 8918 /* Add the displacement expression. */
8919 if (*s != '\0')
a4622f40
AM		 8920 ret = i386_displacement (s, s + strlen (s));
8921 if (ret)
a724f0f4
JB		 8922 {
8923 /* Swap base and index in 16-bit memory operands like
8924 [si+bx]. Since i386_index_check is also used in AT&T
8925 mode we have to do that here. */
8926 if (i.base_reg
8927 && i.index_reg
40fb9820
L		 8928 && i.base_reg->reg_type.bitfield.reg16
8929 && i.index_reg->reg_type.bitfield.reg16
a724f0f4
JB		 8930 && i.base_reg->reg_num >= 6
8931 && i.index_reg->reg_num < 6)
8932 {
8933 const reg_entry *base = i.index_reg;
8934
8935 i.index_reg = i.base_reg;
8936 i.base_reg = base;
8937 }
8938 ret = i386_index_check (operand_string);
8939 }
fc0763e6
JB		 8940 if (ret)
8941 {
8942 i.types[this_operand].bitfield.mem = 1;
8943 i.mem_operands++;
8944 }
64a0c779
DN		 8945 }
8946 }
8947
8948 /* Constant and OFFSET expressions are handled by i386_immediate. */
a724f0f4 8949 else if ((intel_parser.op_modifier & (1 << T_OFFSET))
64a0c779 8950 || intel_parser.reg == NULL)
b7240065
JB		 8951 {
8952 if (i.mem_operands < 2 && i.seg[i.mem_operands])
8953 {
8954 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
8955 as_warn (_("Segment override ignored"));
8956 i.seg[i.mem_operands] = NULL;
8957 }
8958 ret = i386_immediate (intel_parser.disp);
8959 }
a724f0f4 8960
fc0763e6
JB		 8961 if (!final_base && !final_index)
8962 {
8963 final_base = i.base_reg;
8964 final_index = i.index_reg;
8965 }
8966
a724f0f4 8967 if (intel_parser.next_operand && this_operand >= MAX_OPERANDS - 1)
4eed87de 8968 ret = 0;
a724f0f4
JB		 8969 if (!ret || !intel_parser.next_operand)
8970 break;
8971 intel_parser.op_string = intel_parser.next_operand;
8972 this_operand = i.operands++;
7d5e4556 8973 i.types[this_operand].bitfield.unspecified = 1;
64a0c779
DN		 8974 }
8975
8976 free (p);
8977 free (intel_parser.disp);
8978
fc0763e6
JB		 8979 if (final_base || final_index)
8980 {
8981 i.base_reg = final_base;
8982 i.index_reg = final_index;
8983 }
8984
64a0c779
DN		 8985 return ret;
8986}
8987
a724f0f4
JB		 8988#define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8989
8990/* expr e04 expr'
8991
8992 expr' cmpOp e04 expr'
8993 | Empty */
64a0c779 8994static int
e3bb37b5 8995intel_expr (void)
64a0c779 8996{
a724f0f4
JB		 8997 /* XXX Implement the comparison operators. */
8998 return intel_e04 ();
9306ca4a
JB		 8999}
9000
a724f0f4 9001/* e04 e05 e04'
9306ca4a 9002
a724f0f4 9003 e04' addOp e05 e04'
9306ca4a
JB		 9004 | Empty */
9005static int
e3bb37b5 9006intel_e04 (void)
9306ca4a 9007{
a724f0f4 9008 int nregs = -1;
9306ca4a 9009
a724f0f4 9010 for (;;)
9306ca4a 9011 {
a724f0f4
JB		 9012 if (!intel_e05())
9013 return 0;
9306ca4a 9014
a724f0f4
JB		 9015 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9016 i.base_reg = i386_regtab + REGNAM_AL; /* al is invalid as base */
9306ca4a 9017
a724f0f4
JB		 9018 if (cur_token.code == '+')
9019 nregs = -1;
9020 else if (cur_token.code == '-')
9021 nregs = NUM_ADDRESS_REGS;
9022 else
9023 return 1;
64a0c779 9024
a724f0f4
JB		 9025 strcat (intel_parser.disp, cur_token.str);
9026 intel_match_token (cur_token.code);
9027 }
64a0c779
DN		 9028}
9029
64a0c779
DN		 9030/* e05 e06 e05'
9031
9306ca4a 9032 e05' binOp e06 e05'
64a0c779
DN		 9033 | Empty */
9034static int
e3bb37b5 9035intel_e05 (void)
64a0c779 9036{
a724f0f4 9037 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9038
a724f0f4 9039 for (;;)
64a0c779 9040 {
a724f0f4
JB		 9041 if (!intel_e06())
9042 return 0;
9043
4eed87de
AM		 9044 if (cur_token.code == '&'
9045 || cur_token.code == '|'
9046 || cur_token.code == '^')
a724f0f4
JB		 9047 {
9048 char str[2];
9049
9050 str[0] = cur_token.code;
9051 str[1] = 0;
9052 strcat (intel_parser.disp, str);
9053 }
9054 else
9055 break;
9306ca4a 9056
64a0c779
DN		 9057 intel_match_token (cur_token.code);
9058
a724f0f4
JB		 9059 if (nregs < 0)
9060 nregs = ~nregs;
64a0c779 9061 }
a724f0f4
JB		 9062 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9063 i.base_reg = i386_regtab + REGNAM_AL + 1; /* cl is invalid as base */
9064 return 1;
4a1805b1 9065}
64a0c779
DN		 9066
9067/* e06 e09 e06'
9068
9069 e06' mulOp e09 e06'
b77a7acd 9070 | Empty */
64a0c779 9071static int
e3bb37b5 9072intel_e06 (void)
64a0c779 9073{
a724f0f4 9074 int nregs = ~NUM_ADDRESS_REGS;
64a0c779 9075
a724f0f4 9076 for (;;)
64a0c779 9077 {
a724f0f4
JB		 9078 if (!intel_e09())
9079 return 0;
9306ca4a 9080
4eed87de
AM		 9081 if (cur_token.code == '*'
9082 || cur_token.code == '/'
9083 || cur_token.code == '%')
a724f0f4
JB		 9084 {
9085 char str[2];
9306ca4a 9086
a724f0f4
JB		 9087 str[0] = cur_token.code;
9088 str[1] = 0;
9089 strcat (intel_parser.disp, str);
9090 }
9091 else if (cur_token.code == T_SHL)
9092 strcat (intel_parser.disp, "<<");
9093 else if (cur_token.code == T_SHR)
9094 strcat (intel_parser.disp, ">>");
9095 else
9096 break;
9306ca4a 9097
64e74474 9098 intel_match_token (cur_token.code);
64a0c779 9099
a724f0f4
JB		 9100 if (nregs < 0)
9101 nregs = ~nregs;
64a0c779 9102 }
a724f0f4
JB		 9103 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9104 i.base_reg = i386_regtab + REGNAM_AL + 2; /* dl is invalid as base */
9105 return 1;
64a0c779
DN		 9106}
9107
a724f0f4
JB		 9108/* e09 OFFSET e09
9109 | SHORT e09
9110 | + e09
9111 | - e09
9112 | ~ e09
9113 | NOT e09
9306ca4a
JB		 9114 | e10 e09'
9115
64a0c779 9116 e09' PTR e10 e09'
b77a7acd 9117 | : e10 e09'
64a0c779
DN		 9118 | Empty */
9119static int
e3bb37b5 9120intel_e09 (void)
64a0c779 9121{
a724f0f4
JB		 9122 int nregs = ~NUM_ADDRESS_REGS;
9123 int in_offset = 0;
9124
9125 for (;;)
64a0c779 9126 {
a724f0f4
JB		 9127 /* Don't consume constants here. */
9128 if (cur_token.code == '+' || cur_token.code == '-')
9129 {
9130 /* Need to look one token ahead - if the next token
9131 is a constant, the current token is its sign. */
9132 int next_code;
9133
9134 intel_match_token (cur_token.code);
9135 next_code = cur_token.code;
9136 intel_putback_token ();
9137 if (next_code == T_CONST)
9138 break;
9139 }
9140
9141 /* e09 OFFSET e09 */
9142 if (cur_token.code == T_OFFSET)
9143 {
9144 if (!in_offset++)
9145 ++intel_parser.in_offset;
9146 }
9147
9148 /* e09 SHORT e09 */
9149 else if (cur_token.code == T_SHORT)
9150 intel_parser.op_modifier |= 1 << T_SHORT;
9151
9152 /* e09 + e09 */
9153 else if (cur_token.code == '+')
9154 strcat (intel_parser.disp, "+");
9155
9156 /* e09 - e09
9157 | ~ e09
9158 | NOT e09 */
9159 else if (cur_token.code == '-' || cur_token.code == '~')
9160 {
9161 char str[2];
64a0c779 9162
a724f0f4
JB		 9163 if (nregs < 0)
9164 nregs = ~nregs;
9165 str[0] = cur_token.code;
9166 str[1] = 0;
9167 strcat (intel_parser.disp, str);
9168 }
9169
9170 /* e09 e10 e09' */
9171 else
9172 break;
9173
9174 intel_match_token (cur_token.code);
64a0c779
DN		 9175 }
9176
a724f0f4 9177 for (;;)
9306ca4a 9178 {
a724f0f4
JB		 9179 if (!intel_e10 ())
9180 return 0;
9306ca4a 9181
a724f0f4
JB		 9182 /* e09' PTR e10 e09' */
9183 if (cur_token.code == T_PTR)
9184 {
9185 char suffix;
9306ca4a 9186
a724f0f4 9187 if (prev_token.code == T_BYTE)
7d5e4556
L		 9188 {
9189 suffix = BYTE_MNEM_SUFFIX;
9190 i.types[this_operand].bitfield.byte = 1;
9191 }
9306ca4a 9192
a724f0f4
JB		 9193 else if (prev_token.code == T_WORD)
9194 {
34b772a6
JB		 9195 if ((current_templates->start->name[0] == 'l'
9196 && current_templates->start->name[2] == 's'
9197 && current_templates->start->name[3] == 0)
9198 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9199 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9200 else if (intel_parser.got_a_float == 2) /* "fi..." */
9201 suffix = SHORT_MNEM_SUFFIX;
9202 else
9203 suffix = WORD_MNEM_SUFFIX;
7d5e4556 9204 i.types[this_operand].bitfield.word = 1;
a724f0f4 9205 }
64a0c779 9206
a724f0f4
JB		 9207 else if (prev_token.code == T_DWORD)
9208 {
34b772a6
JB		 9209 if ((current_templates->start->name[0] == 'l'
9210 && current_templates->start->name[2] == 's'
9211 && current_templates->start->name[3] == 0)
9212 || current_templates->start->base_opcode == 0x62 /* bound */)
a724f0f4
JB		 9213 suffix = WORD_MNEM_SUFFIX;
9214 else if (flag_code == CODE_16BIT
40fb9820
L		 9215 && (current_templates->start->opcode_modifier.jump
9216 || current_templates->start->opcode_modifier.jumpdword))
a724f0f4
JB		 9217 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9218 else if (intel_parser.got_a_float == 1) /* "f..." */
9219 suffix = SHORT_MNEM_SUFFIX;
9220 else
9221 suffix = LONG_MNEM_SUFFIX;
7d5e4556 9222 i.types[this_operand].bitfield.dword = 1;
a724f0f4 9223 }
9306ca4a 9224
a724f0f4
JB		 9225 else if (prev_token.code == T_FWORD)
9226 {
9227 if (current_templates->start->name[0] == 'l'
9228 && current_templates->start->name[2] == 's'
9229 && current_templates->start->name[3] == 0)
9230 suffix = LONG_MNEM_SUFFIX;
9231 else if (!intel_parser.got_a_float)
9232 {
9233 if (flag_code == CODE_16BIT)
9234 add_prefix (DATA_PREFIX_OPCODE);
9235 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9236 }
9237 else
9238 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
7d5e4556 9239 i.types[this_operand].bitfield.fword = 1;
a724f0f4 9240 }
64a0c779 9241
a724f0f4
JB		 9242 else if (prev_token.code == T_QWORD)
9243 {
34b772a6
JB		 9244 if (current_templates->start->base_opcode == 0x62 /* bound */
9245 || intel_parser.got_a_float == 1) /* "f..." */
a724f0f4
JB		 9246 suffix = LONG_MNEM_SUFFIX;
9247 else
34b772a6 9248 suffix = QWORD_MNEM_SUFFIX;
7d5e4556 9249 i.types[this_operand].bitfield.qword = 1;
a724f0f4 9250 }
64a0c779 9251
a724f0f4
JB		 9252 else if (prev_token.code == T_TBYTE)
9253 {
9254 if (intel_parser.got_a_float == 1)
9255 suffix = LONG_DOUBLE_MNEM_SUFFIX;
9256 else
9257 suffix = BYTE_MNEM_SUFFIX; /* so it will cause an error */
9258 }
9306ca4a 9259
a724f0f4 9260 else if (prev_token.code == T_XMMWORD)
9306ca4a 9261 {
582d5edd 9262 suffix = XMMWORD_MNEM_SUFFIX;
7d5e4556 9263 i.types[this_operand].bitfield.xmmword = 1;
9306ca4a 9264 }
64a0c779 9265
c0f3af97
L		 9266 else if (prev_token.code == T_YMMWORD)
9267 {
9268 suffix = YMMWORD_MNEM_SUFFIX;
9269 i.types[this_operand].bitfield.ymmword = 1;
9270 }
9271
f16b83df 9272 else
a724f0f4
JB		 9273 {
9274 as_bad (_("Unknown operand modifier `%s'"), prev_token.str);
9275 return 0;
9276 }
9277
7d5e4556
L		 9278 i.types[this_operand].bitfield.unspecified = 0;
9279
435acd52
JB		 9280 /* Operands for jump/call using 'ptr' notation denote absolute
9281 addresses. */
40fb9820
L		 9282 if (current_templates->start->opcode_modifier.jump
9283 || current_templates->start->opcode_modifier.jumpdword)
9284 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9285
a724f0f4
JB		 9286 if (current_templates->start->base_opcode == 0x8d /* lea */)
9287 ;
9288 else if (!i.suffix)
9289 i.suffix = suffix;
9290 else if (i.suffix != suffix)
9291 {
9292 as_bad (_("Conflicting operand modifiers"));
9293 return 0;
9294 }
64a0c779 9295
9306ca4a
JB		 9296 }
9297
a724f0f4
JB		 9298 /* e09' : e10 e09' */
9299 else if (cur_token.code == ':')
9306ca4a 9300 {
a724f0f4
JB		 9301 if (prev_token.code != T_REG)
9302 {
9303 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9304 segment/group identifier (which we don't have), using comma
9305 as the operand separator there is even less consistent, since
9306 there all branches only have a single operand. */
9307 if (this_operand != 0
9308 || intel_parser.in_offset
9309 || intel_parser.in_bracket
40fb9820
L		 9310 || (!current_templates->start->opcode_modifier.jump
9311 && !current_templates->start->opcode_modifier.jumpdword
9312 && !current_templates->start->opcode_modifier.jumpintersegment
9313 && !current_templates->start->operand_types[0].bitfield.jumpabsolute))
a724f0f4
JB		 9314 return intel_match_token (T_NIL);
9315 /* Remember the start of the 2nd operand and terminate 1st
9316 operand here.
9317 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9318 another expression), but it gets at least the simplest case
9319 (a plain number or symbol on the left side) right. */
9320 intel_parser.next_operand = intel_parser.op_string;
9321 *--intel_parser.op_string = '\0';
9322 return intel_match_token (':');
9323 }
9306ca4a 9324 }
64a0c779 9325
a724f0f4 9326 /* e09' Empty */
64a0c779 9327 else
a724f0f4 9328 break;
64a0c779 9329
a724f0f4
JB		 9330 intel_match_token (cur_token.code);
9331
9332 }
9333
9334 if (in_offset)
9335 {
9336 --intel_parser.in_offset;
9337 if (nregs < 0)
9338 nregs = ~nregs;
9339 if (NUM_ADDRESS_REGS > nregs)
9306ca4a 9340 {
a724f0f4 9341 as_bad (_("Invalid operand to `OFFSET'"));
9306ca4a
JB		 9342 return 0;
9343 }
a724f0f4
JB		 9344 intel_parser.op_modifier |= 1 << T_OFFSET;
9345 }
9306ca4a 9346
a724f0f4
JB		 9347 if (nregs >= 0 && NUM_ADDRESS_REGS > nregs)
9348 i.base_reg = i386_regtab + REGNAM_AL + 3; /* bl is invalid as base */
9349 return 1;
9350}
64a0c779 9351
a724f0f4 9352static int
e3bb37b5 9353intel_bracket_expr (void)
a724f0f4
JB		 9354{
9355 int was_offset = intel_parser.op_modifier & (1 << T_OFFSET);
9356 const char *start = intel_parser.op_string;
9357 int len;
9358
9359 if (i.op[this_operand].regs)
9360 return intel_match_token (T_NIL);
9361
9362 intel_match_token ('[');
9363
9364 /* Mark as a memory operand only if it's not already known to be an
9365 offset expression. If it's an offset expression, we need to keep
9366 the brace in. */
9367 if (!intel_parser.in_offset)
9368 {
9369 ++intel_parser.in_bracket;
435acd52
JB		 9370
9371 /* Operands for jump/call inside brackets denote absolute addresses. */
40fb9820
L		 9372 if (current_templates->start->opcode_modifier.jump
9373 || current_templates->start->opcode_modifier.jumpdword)
9374 i.types[this_operand].bitfield.jumpabsolute = 1;
435acd52 9375
a724f0f4
JB		 9376 /* Unfortunately gas always diverged from MASM in a respect that can't
9377 be easily fixed without risking to break code sequences likely to be
9378 encountered (the testsuite even check for this): MASM doesn't consider
9379 an expression inside brackets unconditionally as a memory reference.
9380 When that is e.g. a constant, an offset expression, or the sum of the
9381 two, this is still taken as a constant load. gas, however, always
9382 treated these as memory references. As a compromise, we'll try to make
9383 offset expressions inside brackets work the MASM way (since that's
9384 less likely to be found in real world code), but make constants alone
9385 continue to work the traditional gas way. In either case, issue a
9386 warning. */
9387 intel_parser.op_modifier &= ~was_offset;
64a0c779 9388 }
a724f0f4 9389 else
64e74474 9390 strcat (intel_parser.disp, "[");
a724f0f4
JB		 9391
9392 /* Add a '+' to the displacement string if necessary. */
9393 if (*intel_parser.disp != '\0'
9394 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
9395 strcat (intel_parser.disp, "+");
64a0c779 9396
a724f0f4
JB		 9397 if (intel_expr ()
9398 && (len = intel_parser.op_string - start - 1,
9399 intel_match_token (']')))
64a0c779 9400 {
a724f0f4
JB		 9401 /* Preserve brackets when the operand is an offset expression. */
9402 if (intel_parser.in_offset)
9403 strcat (intel_parser.disp, "]");
9404 else
9405 {
9406 --intel_parser.in_bracket;
9407 if (i.base_reg || i.index_reg)
9408 intel_parser.is_mem = 1;
9409 if (!intel_parser.is_mem)
9410 {
9411 if (!(intel_parser.op_modifier & (1 << T_OFFSET)))
9412 /* Defer the warning until all of the operand was parsed. */
9413 intel_parser.is_mem = -1;
9414 else if (!quiet_warnings)
4eed87de
AM		 9415 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9416 len, start, len, start);
a724f0f4
JB		 9417 }
9418 }
9419 intel_parser.op_modifier |= was_offset;
64a0c779 9420
a724f0f4 9421 return 1;
64a0c779 9422 }
a724f0f4 9423 return 0;
64a0c779
DN		 9424}
9425
9426/* e10 e11 e10'
9427
9428 e10' [ expr ] e10'
b77a7acd 9429 | Empty */
64a0c779 9430static int
e3bb37b5 9431intel_e10 (void)
64a0c779 9432{
a724f0f4
JB		 9433 if (!intel_e11 ())
9434 return 0;
64a0c779 9435
a724f0f4 9436 while (cur_token.code == '[')
64a0c779 9437 {
a724f0f4 9438 if (!intel_bracket_expr ())
21d6c4af 9439 return 0;
64a0c779
DN		 9440 }
9441
a724f0f4 9442 return 1;
64a0c779
DN		 9443}
9444
64a0c779 9445/* e11 ( expr )
b77a7acd 9446 | [ expr ]
64a0c779
DN		 9447 | BYTE
9448 | WORD
9449 | DWORD
9306ca4a 9450 | FWORD
64a0c779 9451 | QWORD
9306ca4a
JB		 9452 | TBYTE
9453 | OWORD
9454 | XMMWORD
c0f3af97 9455 | YMMWORD
4a1805b1 9456 | $
64a0c779
DN		 9457 | .
9458 | register
9459 | id
9460 | constant */
9461static int
e3bb37b5 9462intel_e11 (void)
64a0c779 9463{
a724f0f4 9464 switch (cur_token.code)
64a0c779 9465 {
a724f0f4
JB		 9466 /* e11 ( expr ) */
9467 case '(':
64a0c779
DN		 9468 intel_match_token ('(');
9469 strcat (intel_parser.disp, "(");
9470
9471 if (intel_expr () && intel_match_token (')'))
e5cb08ac
KH		 9472 {
9473 strcat (intel_parser.disp, ")");
9474 return 1;
9475 }
a724f0f4 9476 return 0;
4a1805b1 9477
a724f0f4
JB		 9478 /* e11 [ expr ] */
9479 case '[':
a724f0f4 9480 return intel_bracket_expr ();
64a0c779 9481
a724f0f4
JB		 9482 /* e11 $
9483 | . */
9484 case '.':
64a0c779
DN		 9485 strcat (intel_parser.disp, cur_token.str);
9486 intel_match_token (cur_token.code);
21d6c4af
DN		 9487
9488 /* Mark as a memory operand only if it's not already known to be an
9489 offset expression. */
a724f0f4 9490 if (!intel_parser.in_offset)
21d6c4af 9491 intel_parser.is_mem = 1;
64a0c779
DN		 9492
9493 return 1;
64a0c779 9494
a724f0f4
JB		 9495 /* e11 register */
9496 case T_REG:
9497 {
9498 const reg_entry *reg = intel_parser.reg = cur_token.reg;
64a0c779 9499
a724f0f4 9500 intel_match_token (T_REG);
64a0c779 9501
a724f0f4
JB		 9502 /* Check for segment change. */
9503 if (cur_token.code == ':')
9504 {
40fb9820
L		 9505 if (!reg->reg_type.bitfield.sreg2
9506 && !reg->reg_type.bitfield.sreg3)
a724f0f4 9507 {
4eed87de
AM		 9508 as_bad (_("`%s' is not a valid segment register"),
9509 reg->reg_name);
a724f0f4
JB		 9510 return 0;
9511 }
b7240065
JB		 9512 else if (i.mem_operands >= 2)
9513 as_warn (_("Segment override ignored"));
a724f0f4
JB		 9514 else if (i.seg[i.mem_operands])
9515 as_warn (_("Extra segment override ignored"));
9516 else
9517 {
9518 if (!intel_parser.in_offset)
9519 intel_parser.is_mem = 1;
9520 switch (reg->reg_num)
9521 {
9522 case 0:
9523 i.seg[i.mem_operands] = &es;
9524 break;
9525 case 1:
9526 i.seg[i.mem_operands] = &cs;
9527 break;
9528 case 2:
9529 i.seg[i.mem_operands] = &ss;
9530 break;
9531 case 3:
9532 i.seg[i.mem_operands] = &ds;
9533 break;
9534 case 4:
9535 i.seg[i.mem_operands] = &fs;
9536 break;
9537 case 5:
9538 i.seg[i.mem_operands] = &gs;
9539 break;
9540 }
9541 }
9542 }
64a0c779 9543
b7240065
JB		 9544 else if (reg->reg_type.bitfield.sreg3 && reg->reg_num == RegFlat)
9545 {
9546 as_bad (_("cannot use `FLAT' here"));
9547 return 0;
9548 }
9549
a724f0f4
JB		 9550 /* Not a segment register. Check for register scaling. */
9551 else if (cur_token.code == '*')
9552 {
9553 if (!intel_parser.in_bracket)
9554 {
9555 as_bad (_("Register scaling only allowed in memory operands"));
9556 return 0;
9557 }
64a0c779 9558
40fb9820 9559 if (reg->reg_type.bitfield.reg16) /* Disallow things like [si*1]. */
a724f0f4
JB		 9560 reg = i386_regtab + REGNAM_AX + 4; /* sp is invalid as index */
9561 else if (i.index_reg)
9562 reg = i386_regtab + REGNAM_EAX + 4; /* esp is invalid as index */
64a0c779 9563
a724f0f4
JB		 9564 /* What follows must be a valid scale. */
9565 intel_match_token ('*');
9566 i.index_reg = reg;
40fb9820 9567 i.types[this_operand].bitfield.baseindex = 1;
64a0c779 9568
a724f0f4
JB		 9569 /* Set the scale after setting the register (otherwise,
9570 i386_scale will complain) */
9571 if (cur_token.code == '+' || cur_token.code == '-')
9572 {
9573 char *str, sign = cur_token.code;
9574 intel_match_token (cur_token.code);
9575 if (cur_token.code != T_CONST)
9576 {
9577 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9578 cur_token.str);
9579 return 0;
9580 }
9581 str = (char *) xmalloc (strlen (cur_token.str) + 2);
9582 strcpy (str + 1, cur_token.str);
9583 *str = sign;
9584 if (!i386_scale (str))
9585 return 0;
9586 free (str);
9587 }
9588 else if (!i386_scale (cur_token.str))
64a0c779 9589 return 0;
a724f0f4
JB		 9590 intel_match_token (cur_token.code);
9591 }
64a0c779 9592
a724f0f4
JB		 9593 /* No scaling. If this is a memory operand, the register is either a
9594 base register (first occurrence) or an index register (second
9595 occurrence). */
7b0441f6 9596 else if (intel_parser.in_bracket)
a724f0f4 9597 {
64a0c779 9598
a724f0f4
JB		 9599 if (!i.base_reg)
9600 i.base_reg = reg;
9601 else if (!i.index_reg)
9602 i.index_reg = reg;
9603 else
9604 {
9605 as_bad (_("Too many register references in memory operand"));
9606 return 0;
9607 }
64a0c779 9608
40fb9820 9609 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4 9610 }
4a1805b1 9611
4d1bb795
JB		 9612 /* It's neither base nor index. */
9613 else if (!intel_parser.in_offset && !intel_parser.is_mem)
a724f0f4 9614 {
40fb9820
L		 9615 i386_operand_type temp = reg->reg_type;
9616 temp.bitfield.baseindex = 0;
c6fb90c8
L		 9617 i.types[this_operand] = operand_type_or (i.types[this_operand],
9618 temp);
7d5e4556 9619 i.types[this_operand].bitfield.unspecified = 0;
a724f0f4
JB		 9620 i.op[this_operand].regs = reg;
9621 i.reg_operands++;
9622 }
9623 else
9624 {
9625 as_bad (_("Invalid use of register"));
9626 return 0;
9627 }
64a0c779 9628
a724f0f4
JB		 9629 /* Since registers are not part of the displacement string (except
9630 when we're parsing offset operands), we may need to remove any
9631 preceding '+' from the displacement string. */
9632 if (*intel_parser.disp != '\0'
9633 && !intel_parser.in_offset)
9634 {
9635 char *s = intel_parser.disp;
9636 s += strlen (s) - 1;
9637 if (*s == '+')
9638 *s = '\0';
9639 }
4a1805b1 9640
a724f0f4
JB		 9641 return 1;
9642 }
9643
9644 /* e11 BYTE
9645 | WORD
9646 | DWORD
9647 | FWORD
9648 | QWORD
9649 | TBYTE
9650 | OWORD
c0f3af97
L		 9651 | XMMWORD
9652 | YMMWORD */
a724f0f4
JB		 9653 case T_BYTE:
9654 case T_WORD:
9655 case T_DWORD:
9656 case T_FWORD:
9657 case T_QWORD:
9658 case T_TBYTE:
9659 case T_XMMWORD:
c0f3af97 9660 case T_YMMWORD:
a724f0f4 9661 intel_match_token (cur_token.code);
64a0c779 9662
a724f0f4
JB		 9663 if (cur_token.code == T_PTR)
9664 return 1;
9665
9666 /* It must have been an identifier. */
9667 intel_putback_token ();
9668 cur_token.code = T_ID;
9669 /* FALLTHRU */
9670
9671 /* e11 id
9672 | constant */
9673 case T_ID:
9674 if (!intel_parser.in_offset && intel_parser.is_mem <= 0)
9306ca4a
JB		 9675 {
9676 symbolS *symbolP;
9677
a724f0f4
JB		 9678 /* The identifier represents a memory reference only if it's not
9679 preceded by an offset modifier and if it's not an equate. */
9306ca4a
JB		 9680 symbolP = symbol_find(cur_token.str);
9681 if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section)
9682 intel_parser.is_mem = 1;
9683 }
a724f0f4 9684 /* FALLTHRU */
64a0c779 9685
a724f0f4
JB		 9686 case T_CONST:
9687 case '-':
9688 case '+':
9689 {
9690 char *save_str, sign = 0;
64a0c779 9691
a724f0f4
JB		 9692 /* Allow constants that start with `+' or `-'. */
9693 if (cur_token.code == '-' || cur_token.code == '+')
9694 {
9695 sign = cur_token.code;
9696 intel_match_token (cur_token.code);
9697 if (cur_token.code != T_CONST)
9698 {
9699 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9700 cur_token.str);
9701 return 0;
9702 }
9703 }
64a0c779 9704
a724f0f4
JB		 9705 save_str = (char *) xmalloc (strlen (cur_token.str) + 2);
9706 strcpy (save_str + !!sign, cur_token.str);
9707 if (sign)
9708 *save_str = sign;
64a0c779 9709
a724f0f4
JB		 9710 /* Get the next token to check for register scaling. */
9711 intel_match_token (cur_token.code);
64a0c779 9712
4eed87de
AM		 9713 /* Check if this constant is a scaling factor for an
9714 index register. */
a724f0f4
JB		 9715 if (cur_token.code == '*')
9716 {
9717 if (intel_match_token ('*') && cur_token.code == T_REG)
9718 {
9719 const reg_entry *reg = cur_token.reg;
9720
9721 if (!intel_parser.in_bracket)
9722 {
4eed87de
AM		 9723 as_bad (_("Register scaling only allowed "
9724 "in memory operands"));
a724f0f4
JB		 9725 return 0;
9726 }
9727
4eed87de
AM		 9728 /* Disallow things like [1*si].
9729 sp and esp are invalid as index. */
40fb9820 9730 if (reg->reg_type.bitfield.reg16)
4eed87de 9731 reg = i386_regtab + REGNAM_AX + 4;
a724f0f4 9732 else if (i.index_reg)
4eed87de 9733 reg = i386_regtab + REGNAM_EAX + 4;
a724f0f4
JB		 9734
9735 /* The constant is followed by `* reg', so it must be
9736 a valid scale. */
9737 i.index_reg = reg;
40fb9820 9738 i.types[this_operand].bitfield.baseindex = 1;
a724f0f4
JB		 9739
9740 /* Set the scale after setting the register (otherwise,
9741 i386_scale will complain) */
9742 if (!i386_scale (save_str))
64a0c779 9743 return 0;
a724f0f4
JB		 9744 intel_match_token (T_REG);
9745
9746 /* Since registers are not part of the displacement
9747 string, we may need to remove any preceding '+' from
9748 the displacement string. */
9749 if (*intel_parser.disp != '\0')
9750 {
9751 char *s = intel_parser.disp;
9752 s += strlen (s) - 1;
9753 if (*s == '+')
9754 *s = '\0';
9755 }
9756
9757 free (save_str);
9758
9759 return 1;
9760 }
64a0c779 9761
a724f0f4
JB		 9762 /* The constant was not used for register scaling. Since we have
9763 already consumed the token following `*' we now need to put it
9764 back in the stream. */
64a0c779 9765 intel_putback_token ();
a724f0f4 9766 }
64a0c779 9767
a724f0f4
JB		 9768 /* Add the constant to the displacement string. */
9769 strcat (intel_parser.disp, save_str);
9770 free (save_str);
64a0c779 9771
a724f0f4
JB		 9772 return 1;
9773 }
64a0c779
DN		 9774 }
9775
64a0c779
DN		 9776 as_bad (_("Unrecognized token '%s'"), cur_token.str);
9777 return 0;
9778}
9779
64a0c779
DN		 9780/* Match the given token against cur_token. If they match, read the next
9781 token from the operand string. */
9782static int
e3bb37b5 9783intel_match_token (int code)
64a0c779
DN		 9784{
9785 if (cur_token.code == code)
9786 {
9787 intel_get_token ();
9788 return 1;
9789 }
9790 else
9791 {
0477af35 9792 as_bad (_("Unexpected token `%s'"), cur_token.str);
64a0c779
DN		 9793 return 0;
9794 }
9795}
9796
64a0c779
DN		 9797/* Read a new token from intel_parser.op_string and store it in cur_token. */
9798static void
e3bb37b5 9799intel_get_token (void)
64a0c779
DN		 9800{
9801 char *end_op;
9802 const reg_entry *reg;
9803 struct intel_token new_token;
9804
9805 new_token.code = T_NIL;
9806 new_token.reg = NULL;
9807 new_token.str = NULL;
9808
4a1805b1 9809 /* Free the memory allocated to the previous token and move
64a0c779
DN		 9810 cur_token to prev_token. */
9811 if (prev_token.str)
9812 free (prev_token.str);
9813
9814 prev_token = cur_token;
9815
9816 /* Skip whitespace. */
9817 while (is_space_char (*intel_parser.op_string))
9818 intel_parser.op_string++;
9819
9820 /* Return an empty token if we find nothing else on the line. */
9821 if (*intel_parser.op_string == '\0')
9822 {
9823 cur_token = new_token;
9824 return;
9825 }
9826
9827 /* The new token cannot be larger than the remainder of the operand
9828 string. */
a724f0f4 9829 new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1);
64a0c779
DN		 9830 new_token.str[0] = '\0';
9831
9832 if (strchr ("0123456789", *intel_parser.op_string))
9833 {
9834 char *p = new_token.str;
9835 char *q = intel_parser.op_string;
9836 new_token.code = T_CONST;
9837
9838 /* Allow any kind of identifier char to encompass floating point and
9839 hexadecimal numbers. */
9840 while (is_identifier_char (*q))
9841 *p++ = *q++;
9842 *p = '\0';
9843
9844 /* Recognize special symbol names [0-9][bf]. */
9845 if (strlen (intel_parser.op_string) == 2
4a1805b1 9846 && (intel_parser.op_string[1] == 'b'
64a0c779
DN		 9847 || intel_parser.op_string[1] == 'f'))
9848 new_token.code = T_ID;
9849 }
9850
4d1bb795 9851 else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL)
64a0c779 9852 {
4d1bb795
JB		 9853 size_t len = end_op - intel_parser.op_string;
9854
64a0c779
DN		 9855 new_token.code = T_REG;
9856 new_token.reg = reg;
9857
4d1bb795
JB		 9858 memcpy (new_token.str, intel_parser.op_string, len);
9859 new_token.str[len] = '\0';
64a0c779
DN		 9860 }
9861
9862 else if (is_identifier_char (*intel_parser.op_string))
9863 {
9864 char *p = new_token.str;
9865 char *q = intel_parser.op_string;
9866
9867 /* A '.' or '$' followed by an identifier char is an identifier.
9868 Otherwise, it's operator '.' followed by an expression. */
9869 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
9870 {
9306ca4a
JB		 9871 new_token.code = '.';
9872 new_token.str[0] = '.';
64a0c779
DN		 9873 new_token.str[1] = '\0';
9874 }
9875 else
9876 {
9877 while (is_identifier_char (*q) || *q == '@')
9878 *p++ = *q++;
9879 *p = '\0';
9880
9306ca4a
JB		 9881 if (strcasecmp (new_token.str, "NOT") == 0)
9882 new_token.code = '~';
9883
9884 else if (strcasecmp (new_token.str, "MOD") == 0)
9885 new_token.code = '%';
9886
9887 else if (strcasecmp (new_token.str, "AND") == 0)
9888 new_token.code = '&';
9889
9890 else if (strcasecmp (new_token.str, "OR") == 0)
9891 new_token.code = '|';
9892
9893 else if (strcasecmp (new_token.str, "XOR") == 0)
9894 new_token.code = '^';
9895
9896 else if (strcasecmp (new_token.str, "SHL") == 0)
9897 new_token.code = T_SHL;
9898
9899 else if (strcasecmp (new_token.str, "SHR") == 0)
9900 new_token.code = T_SHR;
9901
9902 else if (strcasecmp (new_token.str, "BYTE") == 0)
64a0c779
DN		 9903 new_token.code = T_BYTE;
9904
9905 else if (strcasecmp (new_token.str, "WORD") == 0)
9906 new_token.code = T_WORD;
9907
9908 else if (strcasecmp (new_token.str, "DWORD") == 0)
9909 new_token.code = T_DWORD;
9910
9306ca4a
JB		 9911 else if (strcasecmp (new_token.str, "FWORD") == 0)
9912 new_token.code = T_FWORD;
9913
64a0c779
DN		 9914 else if (strcasecmp (new_token.str, "QWORD") == 0)
9915 new_token.code = T_QWORD;
9916
9306ca4a
JB		 9917 else if (strcasecmp (new_token.str, "TBYTE") == 0
9918 /* XXX remove (gcc still uses it) */
9919 || strcasecmp (new_token.str, "XWORD") == 0)
9920 new_token.code = T_TBYTE;
9921
9922 else if (strcasecmp (new_token.str, "XMMWORD") == 0
9923 || strcasecmp (new_token.str, "OWORD") == 0)
9924 new_token.code = T_XMMWORD;
64a0c779 9925
c0f3af97
L		 9926 else if (strcasecmp (new_token.str, "YMMWORD") == 0)
9927 new_token.code = T_YMMWORD;
9928
64a0c779
DN		 9929 else if (strcasecmp (new_token.str, "PTR") == 0)
9930 new_token.code = T_PTR;
9931
9932 else if (strcasecmp (new_token.str, "SHORT") == 0)
9933 new_token.code = T_SHORT;
9934
9935 else if (strcasecmp (new_token.str, "OFFSET") == 0)
9936 {
9937 new_token.code = T_OFFSET;
9938
9939 /* ??? This is not mentioned in the MASM grammar but gcc
9940 makes use of it with -mintel-syntax. OFFSET may be
9941 followed by FLAT: */
9942 if (strncasecmp (q, " FLAT:", 6) == 0)
9943 strcat (new_token.str, " FLAT:");
9944 }
9945
64a0c779
DN		 9946 else
9947 new_token.code = T_ID;
9948 }
9949 }
9950
9306ca4a
JB		 9951 else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string))
9952 {
9953 new_token.code = *intel_parser.op_string;
9954 new_token.str[0] = *intel_parser.op_string;
9955 new_token.str[1] = '\0';
9956 }
9957
9958 else if (strchr ("<>", *intel_parser.op_string)
9959 && *intel_parser.op_string == *(intel_parser.op_string + 1))
9960 {
9961 new_token.code = *intel_parser.op_string == '<' ? T_SHL : T_SHR;
9962 new_token.str[0] = *intel_parser.op_string;
9963 new_token.str[1] = *intel_parser.op_string;
9964 new_token.str[2] = '\0';
9965 }
9966
64a0c779 9967 else
0477af35 9968 as_bad (_("Unrecognized token `%s'"), intel_parser.op_string);
64a0c779
DN		 9969
9970 intel_parser.op_string += strlen (new_token.str);
9971 cur_token = new_token;
9972}
9973
64a0c779
DN		 9974/* Put cur_token back into the token stream and make cur_token point to
9975 prev_token. */
9976static void
e3bb37b5 9977intel_putback_token (void)
64a0c779 9978{
a724f0f4
JB		 9979 if (cur_token.code != T_NIL)
9980 {
9981 intel_parser.op_string -= strlen (cur_token.str);
9982 free (cur_token.str);
9983 }
64a0c779 9984 cur_token = prev_token;
4a1805b1 9985
64a0c779
DN		 9986 /* Forget prev_token. */
9987 prev_token.code = T_NIL;
9988 prev_token.reg = NULL;
9989 prev_token.str = NULL;
9990}
54cfded0 9991
a60de03c
JB		 9992void
9993tc_x86_parse_to_dw2regnum (expressionS *exp)
54cfded0 9994{
a60de03c
JB		 9995 int saved_naked_reg;
9996 char saved_register_dot;
54cfded0 9997
a60de03c
JB		 9998 saved_naked_reg = allow_naked_reg;
9999 allow_naked_reg = 1;
10000 saved_register_dot = register_chars['.'];
10001 register_chars['.'] = '.';
10002 allow_pseudo_reg = 1;
10003 expression_and_evaluate (exp);
10004 allow_pseudo_reg = 0;
10005 register_chars['.'] = saved_register_dot;
10006 allow_naked_reg = saved_naked_reg;
10007
10008 if (exp->X_op == O_register && exp->X_add_number >= 0)
54cfded0 10009 {
a60de03c
JB		 10010 if ((addressT) exp->X_add_number < i386_regtab_size)
10011 {
10012 exp->X_op = O_constant;
10013 exp->X_add_number = i386_regtab[exp->X_add_number]
10014 .dw2_regnum[flag_code >> 1];
10015 }
10016 else
10017 exp->X_op = O_illegal;
54cfded0 10018 }
54cfded0
AM		 10019}
10020
10021void
10022tc_x86_frame_initial_instructions (void)
10023{
a60de03c
JB		 10024 static unsigned int sp_regno[2];
10025
10026 if (!sp_regno[flag_code >> 1])
10027 {
10028 char *saved_input = input_line_pointer;
10029 char sp[][4] = {"esp", "rsp"};
10030 expressionS exp;
a4447b93 10031
a60de03c
JB		 10032 input_line_pointer = sp[flag_code >> 1];
10033 tc_x86_parse_to_dw2regnum (&exp);
10034 assert (exp.X_op == O_constant);
10035 sp_regno[flag_code >> 1] = exp.X_add_number;
10036 input_line_pointer = saved_input;
10037 }
a4447b93 10038
a60de03c 10039 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
a4447b93 10040 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
54cfded0 10041}
d2b2c203
DJ		 10042
10043int
10044i386_elf_section_type (const char *str, size_t len)
10045{
10046 if (flag_code == CODE_64BIT
10047 && len == sizeof ("unwind") - 1
10048 && strncmp (str, "unwind", 6) == 0)
10049 return SHT_X86_64_UNWIND;
10050
10051 return -1;
10052}
bb41ade5 10053
ad5fec3b
EB		 10054#ifdef TE_SOLARIS
10055void
10056i386_solaris_fix_up_eh_frame (segT sec)
10057{
10058 if (flag_code == CODE_64BIT)
10059 elf_section_type (sec) = SHT_X86_64_UNWIND;
10060}
10061#endif
10062
bb41ade5
AM		 10063#ifdef TE_PE
10064void
10065tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10066{
10067 expressionS expr;
10068
10069 expr.X_op = O_secrel;
10070 expr.X_add_symbol = symbol;
10071 expr.X_add_number = 0;
10072 emit_expr (&expr, size);
10073}
10074#endif
3b22753a
L		 10075
10076#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10077/* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10078
01e1a5bc 10079bfd_vma
3b22753a
L		 10080x86_64_section_letter (int letter, char **ptr_msg)
10081{
10082 if (flag_code == CODE_64BIT)
10083 {
10084 if (letter == 'l')
10085 return SHF_X86_64_LARGE;
10086
10087 *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
64e74474 10088 }
3b22753a 10089 else
64e74474 10090 *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string");
3b22753a
L		 10091 return -1;
10092}
10093
01e1a5bc 10094bfd_vma
3b22753a
L		 10095x86_64_section_word (char *str, size_t len)
10096{
8620418b 10097 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
3b22753a
L		 10098 return SHF_X86_64_LARGE;
10099
10100 return -1;
10101}
10102
10103static void
10104handle_large_common (int small ATTRIBUTE_UNUSED)
10105{
10106 if (flag_code != CODE_64BIT)
10107 {
10108 s_comm_internal (0, elf_common_parse);
10109 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10110 }
10111 else
10112 {
10113 static segT lbss_section;
10114 asection *saved_com_section_ptr = elf_com_section_ptr;
10115 asection *saved_bss_section = bss_section;
10116
10117 if (lbss_section == NULL)
10118 {
10119 flagword applicable;
10120 segT seg = now_seg;
10121 subsegT subseg = now_subseg;
10122
10123 /* The .lbss section is for local .largecomm symbols. */
10124 lbss_section = subseg_new (".lbss", 0);
10125 applicable = bfd_applicable_section_flags (stdoutput);
10126 bfd_set_section_flags (stdoutput, lbss_section,
10127 applicable & SEC_ALLOC);
10128 seg_info (lbss_section)->bss = 1;
10129
10130 subseg_set (seg, subseg);
10131 }
10132
10133 elf_com_section_ptr = &_bfd_elf_large_com_section;
10134 bss_section = lbss_section;
10135
10136 s_comm_internal (0, elf_common_parse);
10137
10138 elf_com_section_ptr = saved_com_section_ptr;
10139 bss_section = saved_bss_section;
10140 }
10141}
10142#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
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