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800eeca4 | 1 | /* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. |
b3dfd7fe | 2 | Copyright 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
800eeca4 JW |
3 | Contributed by David Mosberger-Tang <davidm@hpl.hp.com> |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | /* | |
23 | TODO: | |
24 | ||
25 | - optional operands | |
26 | - directives: | |
27 | .alias | |
28 | .eb | |
29 | .estate | |
30 | .lb | |
31 | .popsection | |
32 | .previous | |
33 | .psr | |
34 | .pushsection | |
800eeca4 JW |
35 | - labels are wrong if automatic alignment is introduced |
36 | (e.g., checkout the second real10 definition in test-data.s) | |
37 | - DV-related stuff: | |
542d6675 KH |
38 | <reg>.safe_across_calls and any other DV-related directives I don't |
39 | have documentation for. | |
40 | verify mod-sched-brs reads/writes are checked/marked (and other | |
41 | notes) | |
800eeca4 JW |
42 | |
43 | */ | |
44 | ||
45 | #include "as.h" | |
3882b010 | 46 | #include "safe-ctype.h" |
800eeca4 JW |
47 | #include "dwarf2dbg.h" |
48 | #include "subsegs.h" | |
49 | ||
50 | #include "opcode/ia64.h" | |
51 | ||
52 | #include "elf/ia64.h" | |
53 | ||
54 | #define NELEMS(a) ((int) (sizeof (a)/sizeof ((a)[0]))) | |
55 | #define MIN(a,b) ((a) < (b) ? (a) : (b)) | |
56 | ||
57 | #define NUM_SLOTS 4 | |
58 | #define PREV_SLOT md.slot[(md.curr_slot + NUM_SLOTS - 1) % NUM_SLOTS] | |
59 | #define CURR_SLOT md.slot[md.curr_slot] | |
60 | ||
61 | #define O_pseudo_fixup (O_max + 1) | |
62 | ||
63 | enum special_section | |
64 | { | |
557debba | 65 | /* IA-64 ABI section pseudo-ops. */ |
800eeca4 JW |
66 | SPECIAL_SECTION_BSS = 0, |
67 | SPECIAL_SECTION_SBSS, | |
68 | SPECIAL_SECTION_SDATA, | |
69 | SPECIAL_SECTION_RODATA, | |
70 | SPECIAL_SECTION_COMMENT, | |
71 | SPECIAL_SECTION_UNWIND, | |
557debba JW |
72 | SPECIAL_SECTION_UNWIND_INFO, |
73 | /* HPUX specific section pseudo-ops. */ | |
74 | SPECIAL_SECTION_INIT_ARRAY, | |
75 | SPECIAL_SECTION_FINI_ARRAY, | |
800eeca4 JW |
76 | }; |
77 | ||
78 | enum reloc_func | |
79 | { | |
13ae64f3 JJ |
80 | FUNC_DTP_MODULE, |
81 | FUNC_DTP_RELATIVE, | |
800eeca4 JW |
82 | FUNC_FPTR_RELATIVE, |
83 | FUNC_GP_RELATIVE, | |
84 | FUNC_LT_RELATIVE, | |
fa2c7eff | 85 | FUNC_LT_RELATIVE_X, |
c67e42c9 | 86 | FUNC_PC_RELATIVE, |
800eeca4 JW |
87 | FUNC_PLT_RELATIVE, |
88 | FUNC_SEC_RELATIVE, | |
89 | FUNC_SEG_RELATIVE, | |
13ae64f3 | 90 | FUNC_TP_RELATIVE, |
800eeca4 JW |
91 | FUNC_LTV_RELATIVE, |
92 | FUNC_LT_FPTR_RELATIVE, | |
13ae64f3 JJ |
93 | FUNC_LT_DTP_MODULE, |
94 | FUNC_LT_DTP_RELATIVE, | |
95 | FUNC_LT_TP_RELATIVE, | |
3969b680 | 96 | FUNC_IPLT_RELOC, |
800eeca4 JW |
97 | }; |
98 | ||
99 | enum reg_symbol | |
100 | { | |
101 | REG_GR = 0, | |
102 | REG_FR = (REG_GR + 128), | |
103 | REG_AR = (REG_FR + 128), | |
104 | REG_CR = (REG_AR + 128), | |
105 | REG_P = (REG_CR + 128), | |
106 | REG_BR = (REG_P + 64), | |
107 | REG_IP = (REG_BR + 8), | |
108 | REG_CFM, | |
109 | REG_PR, | |
110 | REG_PR_ROT, | |
111 | REG_PSR, | |
112 | REG_PSR_L, | |
113 | REG_PSR_UM, | |
114 | /* The following are pseudo-registers for use by gas only. */ | |
115 | IND_CPUID, | |
116 | IND_DBR, | |
117 | IND_DTR, | |
118 | IND_ITR, | |
119 | IND_IBR, | |
120 | IND_MEM, | |
121 | IND_MSR, | |
122 | IND_PKR, | |
123 | IND_PMC, | |
124 | IND_PMD, | |
125 | IND_RR, | |
542d6675 | 126 | /* The following pseudo-registers are used for unwind directives only: */ |
e0c9811a JW |
127 | REG_PSP, |
128 | REG_PRIUNAT, | |
800eeca4 JW |
129 | REG_NUM |
130 | }; | |
131 | ||
132 | enum dynreg_type | |
133 | { | |
134 | DYNREG_GR = 0, /* dynamic general purpose register */ | |
135 | DYNREG_FR, /* dynamic floating point register */ | |
136 | DYNREG_PR, /* dynamic predicate register */ | |
137 | DYNREG_NUM_TYPES | |
138 | }; | |
139 | ||
87f8eb97 JW |
140 | enum operand_match_result |
141 | { | |
142 | OPERAND_MATCH, | |
143 | OPERAND_OUT_OF_RANGE, | |
144 | OPERAND_MISMATCH | |
145 | }; | |
146 | ||
800eeca4 JW |
147 | /* On the ia64, we can't know the address of a text label until the |
148 | instructions are packed into a bundle. To handle this, we keep | |
149 | track of the list of labels that appear in front of each | |
150 | instruction. */ | |
151 | struct label_fix | |
542d6675 KH |
152 | { |
153 | struct label_fix *next; | |
154 | struct symbol *sym; | |
155 | }; | |
800eeca4 JW |
156 | |
157 | extern int target_big_endian; | |
158 | ||
10a98291 L |
159 | void (*ia64_number_to_chars) PARAMS ((char *, valueT, int)); |
160 | ||
161 | static void ia64_float_to_chars_bigendian | |
162 | PARAMS ((char *, LITTLENUM_TYPE *, int)); | |
163 | static void ia64_float_to_chars_littleendian | |
164 | PARAMS ((char *, LITTLENUM_TYPE *, int)); | |
165 | static void (*ia64_float_to_chars) | |
166 | PARAMS ((char *, LITTLENUM_TYPE *, int)); | |
167 | ||
800eeca4 JW |
168 | /* Characters which always start a comment. */ |
169 | const char comment_chars[] = ""; | |
170 | ||
171 | /* Characters which start a comment at the beginning of a line. */ | |
172 | const char line_comment_chars[] = "#"; | |
173 | ||
174 | /* Characters which may be used to separate multiple commands on a | |
175 | single line. */ | |
176 | const char line_separator_chars[] = ";"; | |
177 | ||
178 | /* Characters which are used to indicate an exponent in a floating | |
179 | point number. */ | |
180 | const char EXP_CHARS[] = "eE"; | |
181 | ||
182 | /* Characters which mean that a number is a floating point constant, | |
183 | as in 0d1.0. */ | |
184 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
185 | ||
542d6675 | 186 | /* ia64-specific option processing: */ |
800eeca4 | 187 | |
44f5c83a | 188 | const char *md_shortopts = "m:N:x::"; |
800eeca4 JW |
189 | |
190 | struct option md_longopts[] = | |
191 | { | |
c43c2cc5 JW |
192 | #define OPTION_MCONSTANT_GP (OPTION_MD_BASE + 1) |
193 | {"mconstant-gp", no_argument, NULL, OPTION_MCONSTANT_GP}, | |
194 | #define OPTION_MAUTO_PIC (OPTION_MD_BASE + 2) | |
195 | {"mauto-pic", no_argument, NULL, OPTION_MAUTO_PIC} | |
800eeca4 JW |
196 | }; |
197 | ||
198 | size_t md_longopts_size = sizeof (md_longopts); | |
199 | ||
200 | static struct | |
201 | { | |
202 | struct hash_control *pseudo_hash; /* pseudo opcode hash table */ | |
203 | struct hash_control *reg_hash; /* register name hash table */ | |
204 | struct hash_control *dynreg_hash; /* dynamic register hash table */ | |
205 | struct hash_control *const_hash; /* constant hash table */ | |
206 | struct hash_control *entry_hash; /* code entry hint hash table */ | |
207 | ||
208 | symbolS *regsym[REG_NUM]; | |
209 | ||
210 | /* If X_op is != O_absent, the registername for the instruction's | |
211 | qualifying predicate. If NULL, p0 is assumed for instructions | |
212 | that are predicatable. */ | |
213 | expressionS qp; | |
214 | ||
215 | unsigned int | |
197865e8 | 216 | manual_bundling : 1, |
800eeca4 JW |
217 | debug_dv: 1, |
218 | detect_dv: 1, | |
219 | explicit_mode : 1, /* which mode we're in */ | |
220 | default_explicit_mode : 1, /* which mode is the default */ | |
221 | mode_explicitly_set : 1, /* was the current mode explicitly set? */ | |
4d5a53ff JW |
222 | auto_align : 1, |
223 | keep_pending_output : 1; | |
800eeca4 JW |
224 | |
225 | /* Each bundle consists of up to three instructions. We keep | |
226 | track of four most recent instructions so we can correctly set | |
197865e8 | 227 | the end_of_insn_group for the last instruction in a bundle. */ |
800eeca4 JW |
228 | int curr_slot; |
229 | int num_slots_in_use; | |
230 | struct slot | |
231 | { | |
232 | unsigned int | |
233 | end_of_insn_group : 1, | |
234 | manual_bundling_on : 1, | |
235 | manual_bundling_off : 1; | |
236 | signed char user_template; /* user-selected template, if any */ | |
237 | unsigned char qp_regno; /* qualifying predicate */ | |
238 | /* This duplicates a good fraction of "struct fix" but we | |
239 | can't use a "struct fix" instead since we can't call | |
240 | fix_new_exp() until we know the address of the instruction. */ | |
241 | int num_fixups; | |
242 | struct insn_fix | |
243 | { | |
244 | bfd_reloc_code_real_type code; | |
245 | enum ia64_opnd opnd; /* type of operand in need of fix */ | |
246 | unsigned int is_pcrel : 1; /* is operand pc-relative? */ | |
247 | expressionS expr; /* the value to be inserted */ | |
248 | } | |
249 | fixup[2]; /* at most two fixups per insn */ | |
250 | struct ia64_opcode *idesc; | |
251 | struct label_fix *label_fixups; | |
f1bcba5b | 252 | struct label_fix *tag_fixups; |
800eeca4 JW |
253 | struct unw_rec_list *unwind_record; /* Unwind directive. */ |
254 | expressionS opnd[6]; | |
255 | char *src_file; | |
256 | unsigned int src_line; | |
257 | struct dwarf2_line_info debug_line; | |
258 | } | |
259 | slot[NUM_SLOTS]; | |
260 | ||
261 | segT last_text_seg; | |
262 | ||
263 | struct dynreg | |
264 | { | |
265 | struct dynreg *next; /* next dynamic register */ | |
266 | const char *name; | |
267 | unsigned short base; /* the base register number */ | |
268 | unsigned short num_regs; /* # of registers in this set */ | |
269 | } | |
270 | *dynreg[DYNREG_NUM_TYPES], in, loc, out, rot; | |
271 | ||
272 | flagword flags; /* ELF-header flags */ | |
273 | ||
274 | struct mem_offset { | |
275 | unsigned hint:1; /* is this hint currently valid? */ | |
276 | bfd_vma offset; /* mem.offset offset */ | |
277 | bfd_vma base; /* mem.offset base */ | |
278 | } mem_offset; | |
279 | ||
280 | int path; /* number of alt. entry points seen */ | |
281 | const char **entry_labels; /* labels of all alternate paths in | |
542d6675 | 282 | the current DV-checking block. */ |
800eeca4 | 283 | int maxpaths; /* size currently allocated for |
542d6675 | 284 | entry_labels */ |
88be23ec BS |
285 | /* Support for hardware errata workarounds. */ |
286 | ||
287 | /* Record data about the last three insn groups. */ | |
288 | struct group | |
289 | { | |
290 | /* B-step workaround. | |
291 | For each predicate register, this is set if the corresponding insn | |
292 | group conditionally sets this register with one of the affected | |
293 | instructions. */ | |
294 | int p_reg_set[64]; | |
295 | /* B-step workaround. | |
296 | For each general register, this is set if the corresponding insn | |
297 | a) is conditional one one of the predicate registers for which | |
298 | P_REG_SET is 1 in the corresponding entry of the previous group, | |
299 | b) sets this general register with one of the affected | |
300 | instructions. */ | |
301 | int g_reg_set_conditionally[128]; | |
302 | } last_groups[3]; | |
303 | int group_idx; | |
557debba JW |
304 | |
305 | int pointer_size; /* size in bytes of a pointer */ | |
306 | int pointer_size_shift; /* shift size of a pointer for alignment */ | |
800eeca4 JW |
307 | } |
308 | md; | |
309 | ||
542d6675 | 310 | /* application registers: */ |
800eeca4 | 311 | |
e0c9811a JW |
312 | #define AR_K0 0 |
313 | #define AR_K7 7 | |
314 | #define AR_RSC 16 | |
315 | #define AR_BSP 17 | |
316 | #define AR_BSPSTORE 18 | |
317 | #define AR_RNAT 19 | |
318 | #define AR_UNAT 36 | |
319 | #define AR_FPSR 40 | |
320 | #define AR_ITC 44 | |
321 | #define AR_PFS 64 | |
322 | #define AR_LC 65 | |
800eeca4 JW |
323 | |
324 | static const struct | |
325 | { | |
326 | const char *name; | |
327 | int regnum; | |
328 | } | |
329 | ar[] = | |
330 | { | |
331 | {"ar.k0", 0}, {"ar.k1", 1}, {"ar.k2", 2}, {"ar.k3", 3}, | |
332 | {"ar.k4", 4}, {"ar.k5", 5}, {"ar.k6", 6}, {"ar.k7", 7}, | |
333 | {"ar.rsc", 16}, {"ar.bsp", 17}, | |
334 | {"ar.bspstore", 18}, {"ar.rnat", 19}, | |
335 | {"ar.fcr", 21}, {"ar.eflag", 24}, | |
336 | {"ar.csd", 25}, {"ar.ssd", 26}, | |
337 | {"ar.cflg", 27}, {"ar.fsr", 28}, | |
338 | {"ar.fir", 29}, {"ar.fdr", 30}, | |
339 | {"ar.ccv", 32}, {"ar.unat", 36}, | |
340 | {"ar.fpsr", 40}, {"ar.itc", 44}, | |
341 | {"ar.pfs", 64}, {"ar.lc", 65}, | |
197865e8 | 342 | {"ar.ec", 66}, |
800eeca4 JW |
343 | }; |
344 | ||
345 | #define CR_IPSR 16 | |
346 | #define CR_ISR 17 | |
347 | #define CR_IIP 19 | |
348 | #define CR_IFA 20 | |
349 | #define CR_ITIR 21 | |
350 | #define CR_IIPA 22 | |
351 | #define CR_IFS 23 | |
352 | #define CR_IIM 24 | |
353 | #define CR_IHA 25 | |
354 | #define CR_IVR 65 | |
355 | #define CR_TPR 66 | |
356 | #define CR_EOI 67 | |
357 | #define CR_IRR0 68 | |
358 | #define CR_IRR3 71 | |
359 | #define CR_LRR0 80 | |
360 | #define CR_LRR1 81 | |
361 | ||
542d6675 | 362 | /* control registers: */ |
800eeca4 JW |
363 | static const struct |
364 | { | |
365 | const char *name; | |
366 | int regnum; | |
367 | } | |
368 | cr[] = | |
369 | { | |
370 | {"cr.dcr", 0}, | |
371 | {"cr.itm", 1}, | |
372 | {"cr.iva", 2}, | |
373 | {"cr.pta", 8}, | |
374 | {"cr.gpta", 9}, | |
375 | {"cr.ipsr", 16}, | |
376 | {"cr.isr", 17}, | |
377 | {"cr.iip", 19}, | |
378 | {"cr.ifa", 20}, | |
379 | {"cr.itir", 21}, | |
380 | {"cr.iipa", 22}, | |
381 | {"cr.ifs", 23}, | |
382 | {"cr.iim", 24}, | |
383 | {"cr.iha", 25}, | |
384 | {"cr.lid", 64}, | |
385 | {"cr.ivr", 65}, | |
386 | {"cr.tpr", 66}, | |
387 | {"cr.eoi", 67}, | |
388 | {"cr.irr0", 68}, | |
389 | {"cr.irr1", 69}, | |
390 | {"cr.irr2", 70}, | |
391 | {"cr.irr3", 71}, | |
392 | {"cr.itv", 72}, | |
393 | {"cr.pmv", 73}, | |
394 | {"cr.cmcv", 74}, | |
395 | {"cr.lrr0", 80}, | |
396 | {"cr.lrr1", 81} | |
397 | }; | |
398 | ||
399 | #define PSR_MFL 4 | |
400 | #define PSR_IC 13 | |
401 | #define PSR_DFL 18 | |
402 | #define PSR_CPL 32 | |
403 | ||
404 | static const struct const_desc | |
405 | { | |
406 | const char *name; | |
407 | valueT value; | |
408 | } | |
409 | const_bits[] = | |
410 | { | |
542d6675 | 411 | /* PSR constant masks: */ |
800eeca4 JW |
412 | |
413 | /* 0: reserved */ | |
414 | {"psr.be", ((valueT) 1) << 1}, | |
415 | {"psr.up", ((valueT) 1) << 2}, | |
416 | {"psr.ac", ((valueT) 1) << 3}, | |
417 | {"psr.mfl", ((valueT) 1) << 4}, | |
418 | {"psr.mfh", ((valueT) 1) << 5}, | |
419 | /* 6-12: reserved */ | |
420 | {"psr.ic", ((valueT) 1) << 13}, | |
421 | {"psr.i", ((valueT) 1) << 14}, | |
422 | {"psr.pk", ((valueT) 1) << 15}, | |
423 | /* 16: reserved */ | |
424 | {"psr.dt", ((valueT) 1) << 17}, | |
425 | {"psr.dfl", ((valueT) 1) << 18}, | |
426 | {"psr.dfh", ((valueT) 1) << 19}, | |
427 | {"psr.sp", ((valueT) 1) << 20}, | |
428 | {"psr.pp", ((valueT) 1) << 21}, | |
429 | {"psr.di", ((valueT) 1) << 22}, | |
430 | {"psr.si", ((valueT) 1) << 23}, | |
431 | {"psr.db", ((valueT) 1) << 24}, | |
432 | {"psr.lp", ((valueT) 1) << 25}, | |
433 | {"psr.tb", ((valueT) 1) << 26}, | |
434 | {"psr.rt", ((valueT) 1) << 27}, | |
435 | /* 28-31: reserved */ | |
436 | /* 32-33: cpl (current privilege level) */ | |
437 | {"psr.is", ((valueT) 1) << 34}, | |
438 | {"psr.mc", ((valueT) 1) << 35}, | |
439 | {"psr.it", ((valueT) 1) << 36}, | |
440 | {"psr.id", ((valueT) 1) << 37}, | |
441 | {"psr.da", ((valueT) 1) << 38}, | |
442 | {"psr.dd", ((valueT) 1) << 39}, | |
443 | {"psr.ss", ((valueT) 1) << 40}, | |
444 | /* 41-42: ri (restart instruction) */ | |
445 | {"psr.ed", ((valueT) 1) << 43}, | |
446 | {"psr.bn", ((valueT) 1) << 44}, | |
447 | }; | |
448 | ||
542d6675 | 449 | /* indirect register-sets/memory: */ |
800eeca4 JW |
450 | |
451 | static const struct | |
452 | { | |
453 | const char *name; | |
454 | int regnum; | |
455 | } | |
456 | indirect_reg[] = | |
457 | { | |
458 | { "CPUID", IND_CPUID }, | |
459 | { "cpuid", IND_CPUID }, | |
460 | { "dbr", IND_DBR }, | |
461 | { "dtr", IND_DTR }, | |
462 | { "itr", IND_ITR }, | |
463 | { "ibr", IND_IBR }, | |
464 | { "msr", IND_MSR }, | |
465 | { "pkr", IND_PKR }, | |
466 | { "pmc", IND_PMC }, | |
467 | { "pmd", IND_PMD }, | |
468 | { "rr", IND_RR }, | |
469 | }; | |
470 | ||
471 | /* Pseudo functions used to indicate relocation types (these functions | |
472 | start with an at sign (@). */ | |
473 | static struct | |
474 | { | |
475 | const char *name; | |
476 | enum pseudo_type | |
477 | { | |
478 | PSEUDO_FUNC_NONE, | |
479 | PSEUDO_FUNC_RELOC, | |
480 | PSEUDO_FUNC_CONST, | |
e0c9811a | 481 | PSEUDO_FUNC_REG, |
800eeca4 JW |
482 | PSEUDO_FUNC_FLOAT |
483 | } | |
484 | type; | |
485 | union | |
486 | { | |
487 | unsigned long ival; | |
488 | symbolS *sym; | |
489 | } | |
490 | u; | |
491 | } | |
492 | pseudo_func[] = | |
493 | { | |
542d6675 | 494 | /* reloc pseudo functions (these must come first!): */ |
13ae64f3 JJ |
495 | { "dtpmod", PSEUDO_FUNC_RELOC, { 0 } }, |
496 | { "dtprel", PSEUDO_FUNC_RELOC, { 0 } }, | |
2434f565 JW |
497 | { "fptr", PSEUDO_FUNC_RELOC, { 0 } }, |
498 | { "gprel", PSEUDO_FUNC_RELOC, { 0 } }, | |
499 | { "ltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
fa2c7eff | 500 | { "ltoffx", PSEUDO_FUNC_RELOC, { 0 } }, |
2434f565 JW |
501 | { "pcrel", PSEUDO_FUNC_RELOC, { 0 } }, |
502 | { "pltoff", PSEUDO_FUNC_RELOC, { 0 } }, | |
503 | { "secrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
504 | { "segrel", PSEUDO_FUNC_RELOC, { 0 } }, | |
13ae64f3 | 505 | { "tprel", PSEUDO_FUNC_RELOC, { 0 } }, |
2434f565 JW |
506 | { "ltv", PSEUDO_FUNC_RELOC, { 0 } }, |
507 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_FPTR_RELATIVE */ | |
13ae64f3 JJ |
508 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_MODULE */ |
509 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_DTP_RELATIVE */ | |
510 | { "", 0, { 0 } }, /* placeholder for FUNC_LT_TP_RELATIVE */ | |
3969b680 | 511 | { "iplt", PSEUDO_FUNC_RELOC, { 0 } }, |
800eeca4 | 512 | |
542d6675 | 513 | /* mbtype4 constants: */ |
800eeca4 JW |
514 | { "alt", PSEUDO_FUNC_CONST, { 0xa } }, |
515 | { "brcst", PSEUDO_FUNC_CONST, { 0x0 } }, | |
516 | { "mix", PSEUDO_FUNC_CONST, { 0x8 } }, | |
517 | { "rev", PSEUDO_FUNC_CONST, { 0xb } }, | |
518 | { "shuf", PSEUDO_FUNC_CONST, { 0x9 } }, | |
519 | ||
542d6675 | 520 | /* fclass constants: */ |
bf3ca999 | 521 | { "nat", PSEUDO_FUNC_CONST, { 0x100 } }, |
800eeca4 JW |
522 | { "qnan", PSEUDO_FUNC_CONST, { 0x080 } }, |
523 | { "snan", PSEUDO_FUNC_CONST, { 0x040 } }, | |
524 | { "pos", PSEUDO_FUNC_CONST, { 0x001 } }, | |
525 | { "neg", PSEUDO_FUNC_CONST, { 0x002 } }, | |
526 | { "zero", PSEUDO_FUNC_CONST, { 0x004 } }, | |
527 | { "unorm", PSEUDO_FUNC_CONST, { 0x008 } }, | |
528 | { "norm", PSEUDO_FUNC_CONST, { 0x010 } }, | |
529 | { "inf", PSEUDO_FUNC_CONST, { 0x020 } }, | |
bf3ca999 TW |
530 | |
531 | { "natval", PSEUDO_FUNC_CONST, { 0x100 } }, /* old usage */ | |
e0c9811a | 532 | |
c10d9d8f JW |
533 | /* hint constants: */ |
534 | { "pause", PSEUDO_FUNC_CONST, { 0x0 } }, | |
535 | ||
542d6675 | 536 | /* unwind-related constants: */ |
e0c9811a JW |
537 | { "svr4", PSEUDO_FUNC_CONST, { 0 } }, |
538 | { "hpux", PSEUDO_FUNC_CONST, { 1 } }, | |
539 | { "nt", PSEUDO_FUNC_CONST, { 2 } }, | |
540 | ||
542d6675 | 541 | /* unwind-related registers: */ |
e0c9811a | 542 | { "priunat",PSEUDO_FUNC_REG, { REG_PRIUNAT } } |
800eeca4 JW |
543 | }; |
544 | ||
542d6675 | 545 | /* 41-bit nop opcodes (one per unit): */ |
800eeca4 JW |
546 | static const bfd_vma nop[IA64_NUM_UNITS] = |
547 | { | |
548 | 0x0000000000LL, /* NIL => break 0 */ | |
549 | 0x0008000000LL, /* I-unit nop */ | |
550 | 0x0008000000LL, /* M-unit nop */ | |
551 | 0x4000000000LL, /* B-unit nop */ | |
552 | 0x0008000000LL, /* F-unit nop */ | |
553 | 0x0008000000LL, /* L-"unit" nop */ | |
554 | 0x0008000000LL, /* X-unit nop */ | |
555 | }; | |
556 | ||
557 | /* Can't be `const' as it's passed to input routines (which have the | |
558 | habit of setting temporary sentinels. */ | |
559 | static char special_section_name[][20] = | |
560 | { | |
561 | {".bss"}, {".sbss"}, {".sdata"}, {".rodata"}, {".comment"}, | |
557debba JW |
562 | {".IA_64.unwind"}, {".IA_64.unwind_info"}, |
563 | {".init_array"}, {".fini_array"} | |
800eeca4 JW |
564 | }; |
565 | ||
579f31ac JJ |
566 | static char *special_linkonce_name[] = |
567 | { | |
568 | ".gnu.linkonce.ia64unw.", ".gnu.linkonce.ia64unwi." | |
569 | }; | |
570 | ||
800eeca4 JW |
571 | /* The best template for a particular sequence of up to three |
572 | instructions: */ | |
573 | #define N IA64_NUM_TYPES | |
574 | static unsigned char best_template[N][N][N]; | |
575 | #undef N | |
576 | ||
577 | /* Resource dependencies currently in effect */ | |
578 | static struct rsrc { | |
579 | int depind; /* dependency index */ | |
580 | const struct ia64_dependency *dependency; /* actual dependency */ | |
581 | unsigned specific:1, /* is this a specific bit/regno? */ | |
582 | link_to_qp_branch:1; /* will a branch on the same QP clear it?*/ | |
583 | int index; /* specific regno/bit within dependency */ | |
584 | int note; /* optional qualifying note (0 if none) */ | |
585 | #define STATE_NONE 0 | |
586 | #define STATE_STOP 1 | |
587 | #define STATE_SRLZ 2 | |
588 | int insn_srlz; /* current insn serialization state */ | |
589 | int data_srlz; /* current data serialization state */ | |
590 | int qp_regno; /* qualifying predicate for this usage */ | |
591 | char *file; /* what file marked this dependency */ | |
2434f565 | 592 | unsigned int line; /* what line marked this dependency */ |
800eeca4 | 593 | struct mem_offset mem_offset; /* optional memory offset hint */ |
7484b8e6 | 594 | enum { CMP_NONE, CMP_OR, CMP_AND } cmp_type; /* OR or AND compare? */ |
800eeca4 JW |
595 | int path; /* corresponding code entry index */ |
596 | } *regdeps = NULL; | |
597 | static int regdepslen = 0; | |
598 | static int regdepstotlen = 0; | |
599 | static const char *dv_mode[] = { "RAW", "WAW", "WAR" }; | |
600 | static const char *dv_sem[] = { "none", "implied", "impliedf", | |
139368c9 | 601 | "data", "instr", "specific", "stop", "other" }; |
7484b8e6 | 602 | static const char *dv_cmp_type[] = { "none", "OR", "AND" }; |
800eeca4 JW |
603 | |
604 | /* Current state of PR mutexation */ | |
605 | static struct qpmutex { | |
606 | valueT prmask; | |
607 | int path; | |
608 | } *qp_mutexes = NULL; /* QP mutex bitmasks */ | |
609 | static int qp_mutexeslen = 0; | |
610 | static int qp_mutexestotlen = 0; | |
197865e8 | 611 | static valueT qp_safe_across_calls = 0; |
800eeca4 JW |
612 | |
613 | /* Current state of PR implications */ | |
614 | static struct qp_imply { | |
615 | unsigned p1:6; | |
616 | unsigned p2:6; | |
617 | unsigned p2_branched:1; | |
618 | int path; | |
619 | } *qp_implies = NULL; | |
620 | static int qp_implieslen = 0; | |
621 | static int qp_impliestotlen = 0; | |
622 | ||
197865e8 KH |
623 | /* Keep track of static GR values so that indirect register usage can |
624 | sometimes be tracked. */ | |
800eeca4 JW |
625 | static struct gr { |
626 | unsigned known:1; | |
627 | int path; | |
628 | valueT value; | |
2434f565 | 629 | } gr_values[128] = {{ 1, 0, 0 }}; |
800eeca4 JW |
630 | |
631 | /* These are the routines required to output the various types of | |
632 | unwind records. */ | |
633 | ||
f5a30c2e JW |
634 | /* A slot_number is a frag address plus the slot index (0-2). We use the |
635 | frag address here so that if there is a section switch in the middle of | |
636 | a function, then instructions emitted to a different section are not | |
637 | counted. Since there may be more than one frag for a function, this | |
638 | means we also need to keep track of which frag this address belongs to | |
639 | so we can compute inter-frag distances. This also nicely solves the | |
640 | problem with nops emitted for align directives, which can't easily be | |
641 | counted, but can easily be derived from frag sizes. */ | |
642 | ||
800eeca4 JW |
643 | typedef struct unw_rec_list { |
644 | unwind_record r; | |
e0c9811a | 645 | unsigned long slot_number; |
f5a30c2e | 646 | fragS *slot_frag; |
800eeca4 JW |
647 | struct unw_rec_list *next; |
648 | } unw_rec_list; | |
649 | ||
2434f565 | 650 | #define SLOT_NUM_NOT_SET (unsigned)-1 |
800eeca4 | 651 | |
6290819d NC |
652 | /* Linked list of saved prologue counts. A very poor |
653 | implementation of a map from label numbers to prologue counts. */ | |
654 | typedef struct label_prologue_count | |
655 | { | |
656 | struct label_prologue_count *next; | |
657 | unsigned long label_number; | |
658 | unsigned int prologue_count; | |
659 | } label_prologue_count; | |
660 | ||
e0c9811a JW |
661 | static struct |
662 | { | |
663 | unsigned long next_slot_number; | |
f5a30c2e | 664 | fragS *next_slot_frag; |
e0c9811a JW |
665 | |
666 | /* Maintain a list of unwind entries for the current function. */ | |
667 | unw_rec_list *list; | |
668 | unw_rec_list *tail; | |
800eeca4 | 669 | |
e0c9811a JW |
670 | /* Any unwind entires that should be attached to the current slot |
671 | that an insn is being constructed for. */ | |
672 | unw_rec_list *current_entry; | |
800eeca4 | 673 | |
e0c9811a JW |
674 | /* These are used to create the unwind table entry for this function. */ |
675 | symbolS *proc_start; | |
676 | symbolS *proc_end; | |
677 | symbolS *info; /* pointer to unwind info */ | |
678 | symbolS *personality_routine; | |
91a2ae2a RH |
679 | segT saved_text_seg; |
680 | subsegT saved_text_subseg; | |
681 | unsigned int force_unwind_entry : 1; /* force generation of unwind entry? */ | |
800eeca4 | 682 | |
e0c9811a JW |
683 | /* TRUE if processing unwind directives in a prologue region. */ |
684 | int prologue; | |
30d25259 | 685 | int prologue_mask; |
33d01f33 | 686 | unsigned int prologue_count; /* number of .prologues seen so far */ |
6290819d NC |
687 | /* Prologue counts at previous .label_state directives. */ |
688 | struct label_prologue_count * saved_prologue_counts; | |
e0c9811a | 689 | } unwind; |
800eeca4 JW |
690 | |
691 | typedef void (*vbyte_func) PARAMS ((int, char *, char *)); | |
692 | ||
542d6675 | 693 | /* Forward delarations: */ |
800eeca4 JW |
694 | static int ar_is_in_integer_unit PARAMS ((int regnum)); |
695 | static void set_section PARAMS ((char *name)); | |
696 | static unsigned int set_regstack PARAMS ((unsigned int, unsigned int, | |
697 | unsigned int, unsigned int)); | |
698 | static void dot_radix PARAMS ((int)); | |
699 | static void dot_special_section PARAMS ((int)); | |
700 | static void dot_proc PARAMS ((int)); | |
701 | static void dot_fframe PARAMS ((int)); | |
702 | static void dot_vframe PARAMS ((int)); | |
150f24a2 JW |
703 | static void dot_vframesp PARAMS ((int)); |
704 | static void dot_vframepsp PARAMS ((int)); | |
800eeca4 JW |
705 | static void dot_save PARAMS ((int)); |
706 | static void dot_restore PARAMS ((int)); | |
150f24a2 JW |
707 | static void dot_restorereg PARAMS ((int)); |
708 | static void dot_restorereg_p PARAMS ((int)); | |
800eeca4 JW |
709 | static void dot_handlerdata PARAMS ((int)); |
710 | static void dot_unwentry PARAMS ((int)); | |
711 | static void dot_altrp PARAMS ((int)); | |
e0c9811a | 712 | static void dot_savemem PARAMS ((int)); |
800eeca4 JW |
713 | static void dot_saveg PARAMS ((int)); |
714 | static void dot_savef PARAMS ((int)); | |
715 | static void dot_saveb PARAMS ((int)); | |
716 | static void dot_savegf PARAMS ((int)); | |
717 | static void dot_spill PARAMS ((int)); | |
150f24a2 JW |
718 | static void dot_spillreg PARAMS ((int)); |
719 | static void dot_spillmem PARAMS ((int)); | |
720 | static void dot_spillreg_p PARAMS ((int)); | |
721 | static void dot_spillmem_p PARAMS ((int)); | |
722 | static void dot_label_state PARAMS ((int)); | |
723 | static void dot_copy_state PARAMS ((int)); | |
800eeca4 JW |
724 | static void dot_unwabi PARAMS ((int)); |
725 | static void dot_personality PARAMS ((int)); | |
726 | static void dot_body PARAMS ((int)); | |
727 | static void dot_prologue PARAMS ((int)); | |
728 | static void dot_endp PARAMS ((int)); | |
729 | static void dot_template PARAMS ((int)); | |
730 | static void dot_regstk PARAMS ((int)); | |
731 | static void dot_rot PARAMS ((int)); | |
732 | static void dot_byteorder PARAMS ((int)); | |
733 | static void dot_psr PARAMS ((int)); | |
734 | static void dot_alias PARAMS ((int)); | |
735 | static void dot_ln PARAMS ((int)); | |
736 | static char *parse_section_name PARAMS ((void)); | |
737 | static void dot_xdata PARAMS ((int)); | |
738 | static void stmt_float_cons PARAMS ((int)); | |
739 | static void stmt_cons_ua PARAMS ((int)); | |
740 | static void dot_xfloat_cons PARAMS ((int)); | |
741 | static void dot_xstringer PARAMS ((int)); | |
742 | static void dot_xdata_ua PARAMS ((int)); | |
743 | static void dot_xfloat_cons_ua PARAMS ((int)); | |
150f24a2 | 744 | static void print_prmask PARAMS ((valueT mask)); |
800eeca4 JW |
745 | static void dot_pred_rel PARAMS ((int)); |
746 | static void dot_reg_val PARAMS ((int)); | |
747 | static void dot_dv_mode PARAMS ((int)); | |
748 | static void dot_entry PARAMS ((int)); | |
749 | static void dot_mem_offset PARAMS ((int)); | |
e0c9811a | 750 | static void add_unwind_entry PARAMS((unw_rec_list *ptr)); |
542d6675 | 751 | static symbolS *declare_register PARAMS ((const char *name, int regnum)); |
800eeca4 JW |
752 | static void declare_register_set PARAMS ((const char *, int, int)); |
753 | static unsigned int operand_width PARAMS ((enum ia64_opnd)); | |
87f8eb97 JW |
754 | static enum operand_match_result operand_match PARAMS ((const struct ia64_opcode *idesc, |
755 | int index, | |
756 | expressionS *e)); | |
800eeca4 JW |
757 | static int parse_operand PARAMS ((expressionS *e)); |
758 | static struct ia64_opcode * parse_operands PARAMS ((struct ia64_opcode *)); | |
86cf98f3 | 759 | static int errata_nop_necessary_p PARAMS ((struct slot *, enum ia64_unit)); |
800eeca4 JW |
760 | static void build_insn PARAMS ((struct slot *, bfd_vma *)); |
761 | static void emit_one_bundle PARAMS ((void)); | |
762 | static void fix_insn PARAMS ((fixS *, const struct ia64_operand *, valueT)); | |
197865e8 | 763 | static bfd_reloc_code_real_type ia64_gen_real_reloc_type PARAMS ((struct symbol *sym, |
800eeca4 JW |
764 | bfd_reloc_code_real_type r_type)); |
765 | static void insn_group_break PARAMS ((int, int, int)); | |
150f24a2 JW |
766 | static void mark_resource PARAMS ((struct ia64_opcode *, const struct ia64_dependency *, |
767 | struct rsrc *, int depind, int path)); | |
800eeca4 JW |
768 | static void add_qp_mutex PARAMS((valueT mask)); |
769 | static void add_qp_imply PARAMS((int p1, int p2)); | |
770 | static void clear_qp_branch_flag PARAMS((valueT mask)); | |
771 | static void clear_qp_mutex PARAMS((valueT mask)); | |
772 | static void clear_qp_implies PARAMS((valueT p1_mask, valueT p2_mask)); | |
cb5301b6 | 773 | static int has_suffix_p PARAMS((const char *, const char *)); |
800eeca4 JW |
774 | static void clear_register_values PARAMS ((void)); |
775 | static void print_dependency PARAMS ((const char *action, int depind)); | |
150f24a2 JW |
776 | static void instruction_serialization PARAMS ((void)); |
777 | static void data_serialization PARAMS ((void)); | |
778 | static void remove_marked_resource PARAMS ((struct rsrc *)); | |
800eeca4 | 779 | static int is_conditional_branch PARAMS ((struct ia64_opcode *)); |
150f24a2 | 780 | static int is_taken_branch PARAMS ((struct ia64_opcode *)); |
800eeca4 | 781 | static int is_interruption_or_rfi PARAMS ((struct ia64_opcode *)); |
150f24a2 JW |
782 | static int depends_on PARAMS ((int, struct ia64_opcode *)); |
783 | static int specify_resource PARAMS ((const struct ia64_dependency *, | |
784 | struct ia64_opcode *, int, struct rsrc [], int, int)); | |
800eeca4 JW |
785 | static int check_dv PARAMS((struct ia64_opcode *idesc)); |
786 | static void check_dependencies PARAMS((struct ia64_opcode *)); | |
787 | static void mark_resources PARAMS((struct ia64_opcode *)); | |
788 | static void update_dependencies PARAMS((struct ia64_opcode *)); | |
789 | static void note_register_values PARAMS((struct ia64_opcode *)); | |
150f24a2 JW |
790 | static int qp_mutex PARAMS ((int, int, int)); |
791 | static int resources_match PARAMS ((struct rsrc *, struct ia64_opcode *, int, int, int)); | |
792 | static void output_vbyte_mem PARAMS ((int, char *, char *)); | |
793 | static void count_output PARAMS ((int, char *, char *)); | |
794 | static void output_R1_format PARAMS ((vbyte_func, unw_record_type, int)); | |
795 | static void output_R2_format PARAMS ((vbyte_func, int, int, unsigned long)); | |
800eeca4 | 796 | static void output_R3_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); |
150f24a2 JW |
797 | static void output_P1_format PARAMS ((vbyte_func, int)); |
798 | static void output_P2_format PARAMS ((vbyte_func, int, int)); | |
799 | static void output_P3_format PARAMS ((vbyte_func, unw_record_type, int)); | |
800 | static void output_P4_format PARAMS ((vbyte_func, unsigned char *, unsigned long)); | |
801 | static void output_P5_format PARAMS ((vbyte_func, int, unsigned long)); | |
802 | static void output_P6_format PARAMS ((vbyte_func, unw_record_type, int)); | |
803 | static void output_P7_format PARAMS ((vbyte_func, unw_record_type, unsigned long, unsigned long)); | |
804 | static void output_P8_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
805 | static void output_P9_format PARAMS ((vbyte_func, int, int)); | |
806 | static void output_P10_format PARAMS ((vbyte_func, int, int)); | |
807 | static void output_B1_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
808 | static void output_B2_format PARAMS ((vbyte_func, unsigned long, unsigned long)); | |
800eeca4 JW |
809 | static void output_B3_format PARAMS ((vbyte_func, unsigned long, unsigned long)); |
810 | static void output_B4_format PARAMS ((vbyte_func, unw_record_type, unsigned long)); | |
150f24a2 JW |
811 | static char format_ab_reg PARAMS ((int, int)); |
812 | static void output_X1_format PARAMS ((vbyte_func, unw_record_type, int, int, unsigned long, | |
813 | unsigned long)); | |
814 | static void output_X2_format PARAMS ((vbyte_func, int, int, int, int, int, unsigned long)); | |
815 | static void output_X3_format PARAMS ((vbyte_func, unw_record_type, int, int, int, unsigned long, | |
816 | unsigned long)); | |
817 | static void output_X4_format PARAMS ((vbyte_func, int, int, int, int, int, int, unsigned long)); | |
818 | static void free_list_records PARAMS ((unw_rec_list *)); | |
819 | static unw_rec_list *output_prologue PARAMS ((void)); | |
820 | static unw_rec_list *output_prologue_gr PARAMS ((unsigned int, unsigned int)); | |
821 | static unw_rec_list *output_body PARAMS ((void)); | |
822 | static unw_rec_list *output_mem_stack_f PARAMS ((unsigned int)); | |
823 | static unw_rec_list *output_mem_stack_v PARAMS ((void)); | |
824 | static unw_rec_list *output_psp_gr PARAMS ((unsigned int)); | |
825 | static unw_rec_list *output_psp_sprel PARAMS ((unsigned int)); | |
826 | static unw_rec_list *output_rp_when PARAMS ((void)); | |
827 | static unw_rec_list *output_rp_gr PARAMS ((unsigned int)); | |
828 | static unw_rec_list *output_rp_br PARAMS ((unsigned int)); | |
829 | static unw_rec_list *output_rp_psprel PARAMS ((unsigned int)); | |
830 | static unw_rec_list *output_rp_sprel PARAMS ((unsigned int)); | |
831 | static unw_rec_list *output_pfs_when PARAMS ((void)); | |
832 | static unw_rec_list *output_pfs_gr PARAMS ((unsigned int)); | |
833 | static unw_rec_list *output_pfs_psprel PARAMS ((unsigned int)); | |
834 | static unw_rec_list *output_pfs_sprel PARAMS ((unsigned int)); | |
835 | static unw_rec_list *output_preds_when PARAMS ((void)); | |
836 | static unw_rec_list *output_preds_gr PARAMS ((unsigned int)); | |
837 | static unw_rec_list *output_preds_psprel PARAMS ((unsigned int)); | |
838 | static unw_rec_list *output_preds_sprel PARAMS ((unsigned int)); | |
839 | static unw_rec_list *output_fr_mem PARAMS ((unsigned int)); | |
840 | static unw_rec_list *output_frgr_mem PARAMS ((unsigned int, unsigned int)); | |
841 | static unw_rec_list *output_gr_gr PARAMS ((unsigned int, unsigned int)); | |
842 | static unw_rec_list *output_gr_mem PARAMS ((unsigned int)); | |
843 | static unw_rec_list *output_br_mem PARAMS ((unsigned int)); | |
844 | static unw_rec_list *output_br_gr PARAMS ((unsigned int, unsigned int)); | |
845 | static unw_rec_list *output_spill_base PARAMS ((unsigned int)); | |
846 | static unw_rec_list *output_unat_when PARAMS ((void)); | |
847 | static unw_rec_list *output_unat_gr PARAMS ((unsigned int)); | |
848 | static unw_rec_list *output_unat_psprel PARAMS ((unsigned int)); | |
849 | static unw_rec_list *output_unat_sprel PARAMS ((unsigned int)); | |
850 | static unw_rec_list *output_lc_when PARAMS ((void)); | |
851 | static unw_rec_list *output_lc_gr PARAMS ((unsigned int)); | |
852 | static unw_rec_list *output_lc_psprel PARAMS ((unsigned int)); | |
853 | static unw_rec_list *output_lc_sprel PARAMS ((unsigned int)); | |
854 | static unw_rec_list *output_fpsr_when PARAMS ((void)); | |
855 | static unw_rec_list *output_fpsr_gr PARAMS ((unsigned int)); | |
856 | static unw_rec_list *output_fpsr_psprel PARAMS ((unsigned int)); | |
857 | static unw_rec_list *output_fpsr_sprel PARAMS ((unsigned int)); | |
858 | static unw_rec_list *output_priunat_when_gr PARAMS ((void)); | |
859 | static unw_rec_list *output_priunat_when_mem PARAMS ((void)); | |
860 | static unw_rec_list *output_priunat_gr PARAMS ((unsigned int)); | |
861 | static unw_rec_list *output_priunat_psprel PARAMS ((unsigned int)); | |
862 | static unw_rec_list *output_priunat_sprel PARAMS ((unsigned int)); | |
863 | static unw_rec_list *output_bsp_when PARAMS ((void)); | |
864 | static unw_rec_list *output_bsp_gr PARAMS ((unsigned int)); | |
865 | static unw_rec_list *output_bsp_psprel PARAMS ((unsigned int)); | |
866 | static unw_rec_list *output_bsp_sprel PARAMS ((unsigned int)); | |
867 | static unw_rec_list *output_bspstore_when PARAMS ((void)); | |
868 | static unw_rec_list *output_bspstore_gr PARAMS ((unsigned int)); | |
869 | static unw_rec_list *output_bspstore_psprel PARAMS ((unsigned int)); | |
870 | static unw_rec_list *output_bspstore_sprel PARAMS ((unsigned int)); | |
871 | static unw_rec_list *output_rnat_when PARAMS ((void)); | |
872 | static unw_rec_list *output_rnat_gr PARAMS ((unsigned int)); | |
873 | static unw_rec_list *output_rnat_psprel PARAMS ((unsigned int)); | |
874 | static unw_rec_list *output_rnat_sprel PARAMS ((unsigned int)); | |
875 | static unw_rec_list *output_unwabi PARAMS ((unsigned long, unsigned long)); | |
876 | static unw_rec_list *output_epilogue PARAMS ((unsigned long)); | |
877 | static unw_rec_list *output_label_state PARAMS ((unsigned long)); | |
878 | static unw_rec_list *output_copy_state PARAMS ((unsigned long)); | |
879 | static unw_rec_list *output_spill_psprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
880 | static unw_rec_list *output_spill_sprel PARAMS ((unsigned int, unsigned int, unsigned int)); | |
881 | static unw_rec_list *output_spill_psprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
882 | unsigned int)); | |
883 | static unw_rec_list *output_spill_sprel_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
884 | unsigned int)); | |
885 | static unw_rec_list *output_spill_reg PARAMS ((unsigned int, unsigned int, unsigned int, | |
886 | unsigned int)); | |
887 | static unw_rec_list *output_spill_reg_p PARAMS ((unsigned int, unsigned int, unsigned int, | |
888 | unsigned int, unsigned int)); | |
889 | static void process_one_record PARAMS ((unw_rec_list *, vbyte_func)); | |
890 | static void process_unw_records PARAMS ((unw_rec_list *, vbyte_func)); | |
891 | static int calc_record_size PARAMS ((unw_rec_list *)); | |
892 | static void set_imask PARAMS ((unw_rec_list *, unsigned long, unsigned long, unsigned int)); | |
893 | static int count_bits PARAMS ((unsigned long)); | |
f5a30c2e JW |
894 | static unsigned long slot_index PARAMS ((unsigned long, fragS *, |
895 | unsigned long, fragS *)); | |
91a2ae2a | 896 | static unw_rec_list *optimize_unw_records PARAMS ((unw_rec_list *)); |
150f24a2 JW |
897 | static void fixup_unw_records PARAMS ((unw_rec_list *)); |
898 | static int output_unw_records PARAMS ((unw_rec_list *, void **)); | |
899 | static int convert_expr_to_ab_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
900 | static int convert_expr_to_xy_reg PARAMS ((expressionS *, unsigned int *, unsigned int *)); | |
91a2ae2a | 901 | static int generate_unwind_image PARAMS ((const char *)); |
6290819d NC |
902 | static unsigned int get_saved_prologue_count PARAMS ((unsigned long)); |
903 | static void save_prologue_count PARAMS ((unsigned long, unsigned int)); | |
904 | static void free_saved_prologue_counts PARAMS ((void)); | |
91a2ae2a RH |
905 | |
906 | /* Build the unwind section name by appending the (possibly stripped) | |
907 | text section NAME to the unwind PREFIX. The resulting string | |
908 | pointer is assigned to RESULT. The string is allocated on the | |
40449e9f | 909 | stack, so this must be a macro... */ |
91a2ae2a RH |
910 | #define make_unw_section_name(special, text_name, result) \ |
911 | { \ | |
86cf98f3 RH |
912 | const char *_prefix = special_section_name[special]; \ |
913 | const char *_suffix = text_name; \ | |
579f31ac JJ |
914 | size_t _prefix_len, _suffix_len; \ |
915 | char *_result; \ | |
916 | if (strncmp (text_name, ".gnu.linkonce.t.", \ | |
917 | sizeof (".gnu.linkonce.t.") - 1) == 0) \ | |
918 | { \ | |
919 | _prefix = special_linkonce_name[special - SPECIAL_SECTION_UNWIND]; \ | |
920 | _suffix += sizeof (".gnu.linkonce.t.") - 1; \ | |
921 | } \ | |
922 | _prefix_len = strlen (_prefix), _suffix_len = strlen (_suffix); \ | |
923 | _result = alloca (_prefix_len + _suffix_len + 1); \ | |
07726851 KH |
924 | memcpy (_result, _prefix, _prefix_len); \ |
925 | memcpy (_result + _prefix_len, _suffix, _suffix_len); \ | |
579f31ac | 926 | _result[_prefix_len + _suffix_len] = '\0'; \ |
91a2ae2a RH |
927 | result = _result; \ |
928 | } \ | |
929 | while (0) | |
800eeca4 JW |
930 | |
931 | /* Determine if application register REGNUM resides in the integer | |
932 | unit (as opposed to the memory unit). */ | |
933 | static int | |
934 | ar_is_in_integer_unit (reg) | |
935 | int reg; | |
936 | { | |
937 | reg -= REG_AR; | |
938 | ||
939 | return (reg == 64 /* pfs */ | |
940 | || reg == 65 /* lc */ | |
941 | || reg == 66 /* ec */ | |
942 | /* ??? ias accepts and puts these in the integer unit. */ | |
943 | || (reg >= 112 && reg <= 127)); | |
944 | } | |
945 | ||
946 | /* Switch to section NAME and create section if necessary. It's | |
947 | rather ugly that we have to manipulate input_line_pointer but I | |
948 | don't see any other way to accomplish the same thing without | |
949 | changing obj-elf.c (which may be the Right Thing, in the end). */ | |
950 | static void | |
951 | set_section (name) | |
952 | char *name; | |
953 | { | |
954 | char *saved_input_line_pointer; | |
955 | ||
956 | saved_input_line_pointer = input_line_pointer; | |
957 | input_line_pointer = name; | |
958 | obj_elf_section (0); | |
959 | input_line_pointer = saved_input_line_pointer; | |
960 | } | |
961 | ||
d61a78a7 RH |
962 | /* Map 's' to SHF_IA_64_SHORT. */ |
963 | ||
964 | int | |
965 | ia64_elf_section_letter (letter, ptr_msg) | |
966 | int letter; | |
967 | char **ptr_msg; | |
968 | { | |
969 | if (letter == 's') | |
970 | return SHF_IA_64_SHORT; | |
971 | ||
13ae64f3 | 972 | *ptr_msg = _("Bad .section directive: want a,s,w,x,M,S,G,T in string"); |
d61a78a7 RH |
973 | return 0; |
974 | } | |
975 | ||
800eeca4 JW |
976 | /* Map SHF_IA_64_SHORT to SEC_SMALL_DATA. */ |
977 | ||
978 | flagword | |
979 | ia64_elf_section_flags (flags, attr, type) | |
980 | flagword flags; | |
2434f565 | 981 | int attr, type ATTRIBUTE_UNUSED; |
800eeca4 JW |
982 | { |
983 | if (attr & SHF_IA_64_SHORT) | |
984 | flags |= SEC_SMALL_DATA; | |
985 | return flags; | |
986 | } | |
987 | ||
91a2ae2a RH |
988 | int |
989 | ia64_elf_section_type (str, len) | |
40449e9f KH |
990 | const char *str; |
991 | size_t len; | |
91a2ae2a | 992 | { |
1cd8ff38 | 993 | #define STREQ(s) ((len == sizeof (s) - 1) && (strncmp (str, s, sizeof (s) - 1) == 0)) |
40449e9f | 994 | |
1cd8ff38 | 995 | if (STREQ (ELF_STRING_ia64_unwind_info)) |
91a2ae2a RH |
996 | return SHT_PROGBITS; |
997 | ||
1cd8ff38 | 998 | if (STREQ (ELF_STRING_ia64_unwind_info_once)) |
579f31ac JJ |
999 | return SHT_PROGBITS; |
1000 | ||
1cd8ff38 | 1001 | if (STREQ (ELF_STRING_ia64_unwind)) |
91a2ae2a RH |
1002 | return SHT_IA_64_UNWIND; |
1003 | ||
1cd8ff38 | 1004 | if (STREQ (ELF_STRING_ia64_unwind_once)) |
579f31ac JJ |
1005 | return SHT_IA_64_UNWIND; |
1006 | ||
1cd8ff38 NC |
1007 | if (STREQ ("init_array")) |
1008 | return SHT_INIT_ARRAY; | |
40449e9f | 1009 | |
1cd8ff38 NC |
1010 | if (STREQ ("fini_array")) |
1011 | return SHT_FINI_ARRAY; | |
40449e9f | 1012 | |
91a2ae2a | 1013 | return -1; |
1cd8ff38 | 1014 | #undef STREQ |
91a2ae2a RH |
1015 | } |
1016 | ||
800eeca4 JW |
1017 | static unsigned int |
1018 | set_regstack (ins, locs, outs, rots) | |
1019 | unsigned int ins, locs, outs, rots; | |
1020 | { | |
542d6675 KH |
1021 | /* Size of frame. */ |
1022 | unsigned int sof; | |
800eeca4 JW |
1023 | |
1024 | sof = ins + locs + outs; | |
1025 | if (sof > 96) | |
1026 | { | |
1027 | as_bad ("Size of frame exceeds maximum of 96 registers"); | |
1028 | return 0; | |
1029 | } | |
1030 | if (rots > sof) | |
1031 | { | |
1032 | as_warn ("Size of rotating registers exceeds frame size"); | |
1033 | return 0; | |
1034 | } | |
1035 | md.in.base = REG_GR + 32; | |
1036 | md.loc.base = md.in.base + ins; | |
1037 | md.out.base = md.loc.base + locs; | |
1038 | ||
1039 | md.in.num_regs = ins; | |
1040 | md.loc.num_regs = locs; | |
1041 | md.out.num_regs = outs; | |
1042 | md.rot.num_regs = rots; | |
1043 | return sof; | |
1044 | } | |
1045 | ||
1046 | void | |
1047 | ia64_flush_insns () | |
1048 | { | |
1049 | struct label_fix *lfix; | |
1050 | segT saved_seg; | |
1051 | subsegT saved_subseg; | |
b44b1b85 | 1052 | unw_rec_list *ptr; |
800eeca4 JW |
1053 | |
1054 | if (!md.last_text_seg) | |
1055 | return; | |
1056 | ||
1057 | saved_seg = now_seg; | |
1058 | saved_subseg = now_subseg; | |
1059 | ||
1060 | subseg_set (md.last_text_seg, 0); | |
1061 | ||
1062 | while (md.num_slots_in_use > 0) | |
1063 | emit_one_bundle (); /* force out queued instructions */ | |
1064 | ||
1065 | /* In case there are labels following the last instruction, resolve | |
542d6675 | 1066 | those now: */ |
800eeca4 JW |
1067 | for (lfix = CURR_SLOT.label_fixups; lfix; lfix = lfix->next) |
1068 | { | |
1069 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
1070 | symbol_set_frag (lfix->sym, frag_now); | |
1071 | } | |
1072 | CURR_SLOT.label_fixups = 0; | |
f1bcba5b JW |
1073 | for (lfix = CURR_SLOT.tag_fixups; lfix; lfix = lfix->next) |
1074 | { | |
1075 | S_SET_VALUE (lfix->sym, frag_now_fix ()); | |
1076 | symbol_set_frag (lfix->sym, frag_now); | |
1077 | } | |
1078 | CURR_SLOT.tag_fixups = 0; | |
800eeca4 | 1079 | |
b44b1b85 JW |
1080 | /* In case there are unwind directives following the last instruction, |
1081 | resolve those now. We only handle body and prologue directives here. | |
1082 | Give an error for others. */ | |
1083 | for (ptr = unwind.current_entry; ptr; ptr = ptr->next) | |
1084 | { | |
1085 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr | |
1086 | || ptr->r.type == body) | |
1087 | { | |
1088 | ptr->slot_number = (unsigned long) frag_more (0); | |
1089 | ptr->slot_frag = frag_now; | |
1090 | } | |
1091 | else | |
1092 | as_bad (_("Unwind directive not followed by an instruction.")); | |
1093 | } | |
1094 | unwind.current_entry = NULL; | |
1095 | ||
800eeca4 | 1096 | subseg_set (saved_seg, saved_subseg); |
f1bcba5b JW |
1097 | |
1098 | if (md.qp.X_op == O_register) | |
1099 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
1100 | } |
1101 | ||
1102 | void | |
1103 | ia64_do_align (nbytes) | |
1104 | int nbytes; | |
1105 | { | |
1106 | char *saved_input_line_pointer = input_line_pointer; | |
1107 | ||
1108 | input_line_pointer = ""; | |
1109 | s_align_bytes (nbytes); | |
1110 | input_line_pointer = saved_input_line_pointer; | |
1111 | } | |
1112 | ||
1113 | void | |
1114 | ia64_cons_align (nbytes) | |
1115 | int nbytes; | |
1116 | { | |
1117 | if (md.auto_align) | |
1118 | { | |
1119 | char *saved_input_line_pointer = input_line_pointer; | |
1120 | input_line_pointer = ""; | |
1121 | s_align_bytes (nbytes); | |
1122 | input_line_pointer = saved_input_line_pointer; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | /* Output COUNT bytes to a memory location. */ | |
1127 | static unsigned char *vbyte_mem_ptr = NULL; | |
1128 | ||
197865e8 | 1129 | void |
800eeca4 JW |
1130 | output_vbyte_mem (count, ptr, comment) |
1131 | int count; | |
1132 | char *ptr; | |
2434f565 | 1133 | char *comment ATTRIBUTE_UNUSED; |
800eeca4 JW |
1134 | { |
1135 | int x; | |
1136 | if (vbyte_mem_ptr == NULL) | |
1137 | abort (); | |
1138 | ||
1139 | if (count == 0) | |
1140 | return; | |
1141 | for (x = 0; x < count; x++) | |
1142 | *(vbyte_mem_ptr++) = ptr[x]; | |
1143 | } | |
1144 | ||
1145 | /* Count the number of bytes required for records. */ | |
1146 | static int vbyte_count = 0; | |
197865e8 | 1147 | void |
800eeca4 JW |
1148 | count_output (count, ptr, comment) |
1149 | int count; | |
2434f565 JW |
1150 | char *ptr ATTRIBUTE_UNUSED; |
1151 | char *comment ATTRIBUTE_UNUSED; | |
800eeca4 JW |
1152 | { |
1153 | vbyte_count += count; | |
1154 | } | |
1155 | ||
1156 | static void | |
1157 | output_R1_format (f, rtype, rlen) | |
1158 | vbyte_func f; | |
1159 | unw_record_type rtype; | |
1160 | int rlen; | |
1161 | { | |
e0c9811a | 1162 | int r = 0; |
800eeca4 JW |
1163 | char byte; |
1164 | if (rlen > 0x1f) | |
1165 | { | |
1166 | output_R3_format (f, rtype, rlen); | |
1167 | return; | |
1168 | } | |
197865e8 | 1169 | |
e0c9811a JW |
1170 | if (rtype == body) |
1171 | r = 1; | |
1172 | else if (rtype != prologue) | |
1173 | as_bad ("record type is not valid"); | |
1174 | ||
800eeca4 JW |
1175 | byte = UNW_R1 | (r << 5) | (rlen & 0x1f); |
1176 | (*f) (1, &byte, NULL); | |
1177 | } | |
1178 | ||
1179 | static void | |
1180 | output_R2_format (f, mask, grsave, rlen) | |
1181 | vbyte_func f; | |
1182 | int mask, grsave; | |
1183 | unsigned long rlen; | |
1184 | { | |
1185 | char bytes[20]; | |
1186 | int count = 2; | |
1187 | mask = (mask & 0x0f); | |
1188 | grsave = (grsave & 0x7f); | |
1189 | ||
1190 | bytes[0] = (UNW_R2 | (mask >> 1)); | |
1191 | bytes[1] = (((mask & 0x01) << 7) | grsave); | |
1192 | count += output_leb128 (bytes + 2, rlen, 0); | |
1193 | (*f) (count, bytes, NULL); | |
1194 | } | |
1195 | ||
1196 | static void | |
1197 | output_R3_format (f, rtype, rlen) | |
1198 | vbyte_func f; | |
1199 | unw_record_type rtype; | |
1200 | unsigned long rlen; | |
1201 | { | |
e0c9811a | 1202 | int r = 0, count; |
800eeca4 JW |
1203 | char bytes[20]; |
1204 | if (rlen <= 0x1f) | |
1205 | { | |
1206 | output_R1_format (f, rtype, rlen); | |
1207 | return; | |
1208 | } | |
197865e8 | 1209 | |
e0c9811a JW |
1210 | if (rtype == body) |
1211 | r = 1; | |
1212 | else if (rtype != prologue) | |
1213 | as_bad ("record type is not valid"); | |
800eeca4 JW |
1214 | bytes[0] = (UNW_R3 | r); |
1215 | count = output_leb128 (bytes + 1, rlen, 0); | |
1216 | (*f) (count + 1, bytes, NULL); | |
1217 | } | |
1218 | ||
1219 | static void | |
1220 | output_P1_format (f, brmask) | |
1221 | vbyte_func f; | |
1222 | int brmask; | |
1223 | { | |
1224 | char byte; | |
1225 | byte = UNW_P1 | (brmask & 0x1f); | |
1226 | (*f) (1, &byte, NULL); | |
1227 | } | |
1228 | ||
1229 | static void | |
1230 | output_P2_format (f, brmask, gr) | |
1231 | vbyte_func f; | |
1232 | int brmask; | |
1233 | int gr; | |
1234 | { | |
1235 | char bytes[2]; | |
1236 | brmask = (brmask & 0x1f); | |
1237 | bytes[0] = UNW_P2 | (brmask >> 1); | |
1238 | bytes[1] = (((brmask & 1) << 7) | gr); | |
1239 | (*f) (2, bytes, NULL); | |
1240 | } | |
1241 | ||
1242 | static void | |
1243 | output_P3_format (f, rtype, reg) | |
1244 | vbyte_func f; | |
1245 | unw_record_type rtype; | |
1246 | int reg; | |
1247 | { | |
1248 | char bytes[2]; | |
e0c9811a | 1249 | int r = 0; |
800eeca4 JW |
1250 | reg = (reg & 0x7f); |
1251 | switch (rtype) | |
542d6675 | 1252 | { |
800eeca4 JW |
1253 | case psp_gr: |
1254 | r = 0; | |
1255 | break; | |
1256 | case rp_gr: | |
1257 | r = 1; | |
1258 | break; | |
1259 | case pfs_gr: | |
1260 | r = 2; | |
1261 | break; | |
1262 | case preds_gr: | |
1263 | r = 3; | |
1264 | break; | |
1265 | case unat_gr: | |
1266 | r = 4; | |
1267 | break; | |
1268 | case lc_gr: | |
1269 | r = 5; | |
1270 | break; | |
1271 | case rp_br: | |
1272 | r = 6; | |
1273 | break; | |
1274 | case rnat_gr: | |
1275 | r = 7; | |
1276 | break; | |
1277 | case bsp_gr: | |
1278 | r = 8; | |
1279 | break; | |
1280 | case bspstore_gr: | |
1281 | r = 9; | |
1282 | break; | |
1283 | case fpsr_gr: | |
1284 | r = 10; | |
1285 | break; | |
1286 | case priunat_gr: | |
1287 | r = 11; | |
1288 | break; | |
1289 | default: | |
1290 | as_bad ("Invalid record type for P3 format."); | |
542d6675 | 1291 | } |
800eeca4 JW |
1292 | bytes[0] = (UNW_P3 | (r >> 1)); |
1293 | bytes[1] = (((r & 1) << 7) | reg); | |
1294 | (*f) (2, bytes, NULL); | |
1295 | } | |
1296 | ||
800eeca4 | 1297 | static void |
e0c9811a | 1298 | output_P4_format (f, imask, imask_size) |
800eeca4 | 1299 | vbyte_func f; |
e0c9811a JW |
1300 | unsigned char *imask; |
1301 | unsigned long imask_size; | |
800eeca4 | 1302 | { |
e0c9811a JW |
1303 | imask[0] = UNW_P4; |
1304 | (*f) (imask_size, imask, NULL); | |
800eeca4 JW |
1305 | } |
1306 | ||
1307 | static void | |
1308 | output_P5_format (f, grmask, frmask) | |
1309 | vbyte_func f; | |
1310 | int grmask; | |
1311 | unsigned long frmask; | |
1312 | { | |
1313 | char bytes[4]; | |
1314 | grmask = (grmask & 0x0f); | |
1315 | ||
1316 | bytes[0] = UNW_P5; | |
1317 | bytes[1] = ((grmask << 4) | ((frmask & 0x000f0000) >> 16)); | |
1318 | bytes[2] = ((frmask & 0x0000ff00) >> 8); | |
1319 | bytes[3] = (frmask & 0x000000ff); | |
1320 | (*f) (4, bytes, NULL); | |
1321 | } | |
1322 | ||
1323 | static void | |
1324 | output_P6_format (f, rtype, rmask) | |
1325 | vbyte_func f; | |
1326 | unw_record_type rtype; | |
1327 | int rmask; | |
1328 | { | |
1329 | char byte; | |
e0c9811a | 1330 | int r = 0; |
197865e8 | 1331 | |
e0c9811a JW |
1332 | if (rtype == gr_mem) |
1333 | r = 1; | |
1334 | else if (rtype != fr_mem) | |
1335 | as_bad ("Invalid record type for format P6"); | |
800eeca4 JW |
1336 | byte = (UNW_P6 | (r << 4) | (rmask & 0x0f)); |
1337 | (*f) (1, &byte, NULL); | |
1338 | } | |
1339 | ||
1340 | static void | |
1341 | output_P7_format (f, rtype, w1, w2) | |
1342 | vbyte_func f; | |
1343 | unw_record_type rtype; | |
1344 | unsigned long w1; | |
1345 | unsigned long w2; | |
1346 | { | |
1347 | char bytes[20]; | |
1348 | int count = 1; | |
e0c9811a | 1349 | int r = 0; |
800eeca4 JW |
1350 | count += output_leb128 (bytes + 1, w1, 0); |
1351 | switch (rtype) | |
1352 | { | |
542d6675 KH |
1353 | case mem_stack_f: |
1354 | r = 0; | |
1355 | count += output_leb128 (bytes + count, w2 >> 4, 0); | |
1356 | break; | |
1357 | case mem_stack_v: | |
1358 | r = 1; | |
1359 | break; | |
1360 | case spill_base: | |
1361 | r = 2; | |
1362 | break; | |
1363 | case psp_sprel: | |
1364 | r = 3; | |
1365 | break; | |
1366 | case rp_when: | |
1367 | r = 4; | |
1368 | break; | |
1369 | case rp_psprel: | |
1370 | r = 5; | |
1371 | break; | |
1372 | case pfs_when: | |
1373 | r = 6; | |
1374 | break; | |
1375 | case pfs_psprel: | |
1376 | r = 7; | |
1377 | break; | |
1378 | case preds_when: | |
1379 | r = 8; | |
1380 | break; | |
1381 | case preds_psprel: | |
1382 | r = 9; | |
1383 | break; | |
1384 | case lc_when: | |
1385 | r = 10; | |
1386 | break; | |
1387 | case lc_psprel: | |
1388 | r = 11; | |
1389 | break; | |
1390 | case unat_when: | |
1391 | r = 12; | |
1392 | break; | |
1393 | case unat_psprel: | |
1394 | r = 13; | |
1395 | break; | |
1396 | case fpsr_when: | |
1397 | r = 14; | |
1398 | break; | |
1399 | case fpsr_psprel: | |
1400 | r = 15; | |
1401 | break; | |
1402 | default: | |
1403 | break; | |
800eeca4 JW |
1404 | } |
1405 | bytes[0] = (UNW_P7 | r); | |
1406 | (*f) (count, bytes, NULL); | |
1407 | } | |
1408 | ||
1409 | static void | |
1410 | output_P8_format (f, rtype, t) | |
1411 | vbyte_func f; | |
1412 | unw_record_type rtype; | |
1413 | unsigned long t; | |
1414 | { | |
1415 | char bytes[20]; | |
e0c9811a | 1416 | int r = 0; |
800eeca4 JW |
1417 | int count = 2; |
1418 | bytes[0] = UNW_P8; | |
1419 | switch (rtype) | |
1420 | { | |
542d6675 KH |
1421 | case rp_sprel: |
1422 | r = 1; | |
1423 | break; | |
1424 | case pfs_sprel: | |
1425 | r = 2; | |
1426 | break; | |
1427 | case preds_sprel: | |
1428 | r = 3; | |
1429 | break; | |
1430 | case lc_sprel: | |
1431 | r = 4; | |
1432 | break; | |
1433 | case unat_sprel: | |
1434 | r = 5; | |
1435 | break; | |
1436 | case fpsr_sprel: | |
1437 | r = 6; | |
1438 | break; | |
1439 | case bsp_when: | |
1440 | r = 7; | |
1441 | break; | |
1442 | case bsp_psprel: | |
1443 | r = 8; | |
1444 | break; | |
1445 | case bsp_sprel: | |
1446 | r = 9; | |
1447 | break; | |
1448 | case bspstore_when: | |
1449 | r = 10; | |
1450 | break; | |
1451 | case bspstore_psprel: | |
1452 | r = 11; | |
1453 | break; | |
1454 | case bspstore_sprel: | |
1455 | r = 12; | |
1456 | break; | |
1457 | case rnat_when: | |
1458 | r = 13; | |
1459 | break; | |
1460 | case rnat_psprel: | |
1461 | r = 14; | |
1462 | break; | |
1463 | case rnat_sprel: | |
1464 | r = 15; | |
1465 | break; | |
1466 | case priunat_when_gr: | |
1467 | r = 16; | |
1468 | break; | |
1469 | case priunat_psprel: | |
1470 | r = 17; | |
1471 | break; | |
1472 | case priunat_sprel: | |
1473 | r = 18; | |
1474 | break; | |
1475 | case priunat_when_mem: | |
1476 | r = 19; | |
1477 | break; | |
1478 | default: | |
1479 | break; | |
800eeca4 JW |
1480 | } |
1481 | bytes[1] = r; | |
1482 | count += output_leb128 (bytes + 2, t, 0); | |
1483 | (*f) (count, bytes, NULL); | |
1484 | } | |
1485 | ||
1486 | static void | |
1487 | output_P9_format (f, grmask, gr) | |
1488 | vbyte_func f; | |
1489 | int grmask; | |
1490 | int gr; | |
1491 | { | |
1492 | char bytes[3]; | |
1493 | bytes[0] = UNW_P9; | |
1494 | bytes[1] = (grmask & 0x0f); | |
1495 | bytes[2] = (gr & 0x7f); | |
1496 | (*f) (3, bytes, NULL); | |
1497 | } | |
1498 | ||
1499 | static void | |
1500 | output_P10_format (f, abi, context) | |
1501 | vbyte_func f; | |
1502 | int abi; | |
1503 | int context; | |
1504 | { | |
1505 | char bytes[3]; | |
1506 | bytes[0] = UNW_P10; | |
1507 | bytes[1] = (abi & 0xff); | |
1508 | bytes[2] = (context & 0xff); | |
1509 | (*f) (3, bytes, NULL); | |
1510 | } | |
1511 | ||
1512 | static void | |
1513 | output_B1_format (f, rtype, label) | |
1514 | vbyte_func f; | |
1515 | unw_record_type rtype; | |
1516 | unsigned long label; | |
1517 | { | |
1518 | char byte; | |
e0c9811a | 1519 | int r = 0; |
197865e8 | 1520 | if (label > 0x1f) |
800eeca4 JW |
1521 | { |
1522 | output_B4_format (f, rtype, label); | |
1523 | return; | |
1524 | } | |
e0c9811a JW |
1525 | if (rtype == copy_state) |
1526 | r = 1; | |
1527 | else if (rtype != label_state) | |
1528 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1529 | |
1530 | byte = (UNW_B1 | (r << 5) | (label & 0x1f)); | |
1531 | (*f) (1, &byte, NULL); | |
1532 | } | |
1533 | ||
1534 | static void | |
1535 | output_B2_format (f, ecount, t) | |
1536 | vbyte_func f; | |
1537 | unsigned long ecount; | |
1538 | unsigned long t; | |
1539 | { | |
1540 | char bytes[20]; | |
1541 | int count = 1; | |
1542 | if (ecount > 0x1f) | |
1543 | { | |
1544 | output_B3_format (f, ecount, t); | |
1545 | return; | |
1546 | } | |
1547 | bytes[0] = (UNW_B2 | (ecount & 0x1f)); | |
1548 | count += output_leb128 (bytes + 1, t, 0); | |
1549 | (*f) (count, bytes, NULL); | |
1550 | } | |
1551 | ||
1552 | static void | |
1553 | output_B3_format (f, ecount, t) | |
1554 | vbyte_func f; | |
1555 | unsigned long ecount; | |
1556 | unsigned long t; | |
1557 | { | |
1558 | char bytes[20]; | |
1559 | int count = 1; | |
1560 | if (ecount <= 0x1f) | |
1561 | { | |
1562 | output_B2_format (f, ecount, t); | |
1563 | return; | |
1564 | } | |
1565 | bytes[0] = UNW_B3; | |
1566 | count += output_leb128 (bytes + 1, t, 0); | |
1567 | count += output_leb128 (bytes + count, ecount, 0); | |
1568 | (*f) (count, bytes, NULL); | |
1569 | } | |
1570 | ||
1571 | static void | |
1572 | output_B4_format (f, rtype, label) | |
1573 | vbyte_func f; | |
1574 | unw_record_type rtype; | |
1575 | unsigned long label; | |
1576 | { | |
1577 | char bytes[20]; | |
e0c9811a | 1578 | int r = 0; |
800eeca4 | 1579 | int count = 1; |
197865e8 | 1580 | if (label <= 0x1f) |
800eeca4 JW |
1581 | { |
1582 | output_B1_format (f, rtype, label); | |
1583 | return; | |
1584 | } | |
197865e8 | 1585 | |
e0c9811a JW |
1586 | if (rtype == copy_state) |
1587 | r = 1; | |
1588 | else if (rtype != label_state) | |
1589 | as_bad ("Invalid record type for format B1"); | |
800eeca4 JW |
1590 | |
1591 | bytes[0] = (UNW_B4 | (r << 3)); | |
1592 | count += output_leb128 (bytes + 1, label, 0); | |
1593 | (*f) (count, bytes, NULL); | |
1594 | } | |
1595 | ||
1596 | static char | |
e0c9811a | 1597 | format_ab_reg (ab, reg) |
542d6675 KH |
1598 | int ab; |
1599 | int reg; | |
800eeca4 JW |
1600 | { |
1601 | int ret; | |
e0c9811a | 1602 | ab = (ab & 3); |
800eeca4 | 1603 | reg = (reg & 0x1f); |
e0c9811a | 1604 | ret = (ab << 5) | reg; |
800eeca4 JW |
1605 | return ret; |
1606 | } | |
1607 | ||
1608 | static void | |
e0c9811a | 1609 | output_X1_format (f, rtype, ab, reg, t, w1) |
800eeca4 JW |
1610 | vbyte_func f; |
1611 | unw_record_type rtype; | |
e0c9811a | 1612 | int ab, reg; |
800eeca4 JW |
1613 | unsigned long t; |
1614 | unsigned long w1; | |
1615 | { | |
1616 | char bytes[20]; | |
e0c9811a | 1617 | int r = 0; |
800eeca4 JW |
1618 | int count = 2; |
1619 | bytes[0] = UNW_X1; | |
197865e8 | 1620 | |
e0c9811a JW |
1621 | if (rtype == spill_sprel) |
1622 | r = 1; | |
1623 | else if (rtype != spill_psprel) | |
1624 | as_bad ("Invalid record type for format X1"); | |
1625 | bytes[1] = ((r << 7) | format_ab_reg (ab, reg)); | |
800eeca4 JW |
1626 | count += output_leb128 (bytes + 2, t, 0); |
1627 | count += output_leb128 (bytes + count, w1, 0); | |
1628 | (*f) (count, bytes, NULL); | |
1629 | } | |
1630 | ||
1631 | static void | |
e0c9811a | 1632 | output_X2_format (f, ab, reg, x, y, treg, t) |
800eeca4 | 1633 | vbyte_func f; |
e0c9811a | 1634 | int ab, reg; |
800eeca4 JW |
1635 | int x, y, treg; |
1636 | unsigned long t; | |
1637 | { | |
1638 | char bytes[20]; | |
800eeca4 JW |
1639 | int count = 3; |
1640 | bytes[0] = UNW_X2; | |
e0c9811a | 1641 | bytes[1] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1642 | bytes[2] = (((y & 1) << 7) | (treg & 0x7f)); |
1643 | count += output_leb128 (bytes + 3, t, 0); | |
1644 | (*f) (count, bytes, NULL); | |
1645 | } | |
1646 | ||
1647 | static void | |
e0c9811a | 1648 | output_X3_format (f, rtype, qp, ab, reg, t, w1) |
800eeca4 JW |
1649 | vbyte_func f; |
1650 | unw_record_type rtype; | |
1651 | int qp; | |
e0c9811a | 1652 | int ab, reg; |
800eeca4 JW |
1653 | unsigned long t; |
1654 | unsigned long w1; | |
1655 | { | |
1656 | char bytes[20]; | |
e0c9811a | 1657 | int r = 0; |
800eeca4 | 1658 | int count = 3; |
e0c9811a JW |
1659 | bytes[0] = UNW_X3; |
1660 | ||
1661 | if (rtype == spill_sprel_p) | |
1662 | r = 1; | |
1663 | else if (rtype != spill_psprel_p) | |
1664 | as_bad ("Invalid record type for format X3"); | |
800eeca4 | 1665 | bytes[1] = ((r << 7) | (qp & 0x3f)); |
e0c9811a | 1666 | bytes[2] = format_ab_reg (ab, reg); |
800eeca4 JW |
1667 | count += output_leb128 (bytes + 3, t, 0); |
1668 | count += output_leb128 (bytes + count, w1, 0); | |
1669 | (*f) (count, bytes, NULL); | |
1670 | } | |
1671 | ||
1672 | static void | |
e0c9811a | 1673 | output_X4_format (f, qp, ab, reg, x, y, treg, t) |
800eeca4 JW |
1674 | vbyte_func f; |
1675 | int qp; | |
e0c9811a | 1676 | int ab, reg; |
800eeca4 JW |
1677 | int x, y, treg; |
1678 | unsigned long t; | |
1679 | { | |
1680 | char bytes[20]; | |
800eeca4 | 1681 | int count = 4; |
e0c9811a | 1682 | bytes[0] = UNW_X4; |
800eeca4 | 1683 | bytes[1] = (qp & 0x3f); |
e0c9811a | 1684 | bytes[2] = (((x & 1) << 7) | format_ab_reg (ab, reg)); |
800eeca4 JW |
1685 | bytes[3] = (((y & 1) << 7) | (treg & 0x7f)); |
1686 | count += output_leb128 (bytes + 4, t, 0); | |
1687 | (*f) (count, bytes, NULL); | |
1688 | } | |
1689 | ||
1690 | /* This function allocates a record list structure, and initializes fields. */ | |
542d6675 | 1691 | |
800eeca4 | 1692 | static unw_rec_list * |
197865e8 | 1693 | alloc_record (unw_record_type t) |
800eeca4 JW |
1694 | { |
1695 | unw_rec_list *ptr; | |
1696 | ptr = xmalloc (sizeof (*ptr)); | |
1697 | ptr->next = NULL; | |
1698 | ptr->slot_number = SLOT_NUM_NOT_SET; | |
1699 | ptr->r.type = t; | |
1700 | return ptr; | |
1701 | } | |
1702 | ||
800eeca4 | 1703 | /* This function frees an entire list of record structures. */ |
542d6675 | 1704 | |
800eeca4 JW |
1705 | void |
1706 | free_list_records (unw_rec_list *first) | |
1707 | { | |
1708 | unw_rec_list *ptr; | |
542d6675 | 1709 | for (ptr = first; ptr != NULL;) |
800eeca4 JW |
1710 | { |
1711 | unw_rec_list *tmp = ptr; | |
e0c9811a JW |
1712 | |
1713 | if ((tmp->r.type == prologue || tmp->r.type == prologue_gr) | |
1714 | && tmp->r.record.r.mask.i) | |
1715 | free (tmp->r.record.r.mask.i); | |
1716 | ||
800eeca4 JW |
1717 | ptr = ptr->next; |
1718 | free (tmp); | |
1719 | } | |
1720 | } | |
1721 | ||
1722 | static unw_rec_list * | |
1723 | output_prologue () | |
1724 | { | |
1725 | unw_rec_list *ptr = alloc_record (prologue); | |
e0c9811a | 1726 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
800eeca4 JW |
1727 | return ptr; |
1728 | } | |
1729 | ||
1730 | static unw_rec_list * | |
1731 | output_prologue_gr (saved_mask, reg) | |
1732 | unsigned int saved_mask; | |
1733 | unsigned int reg; | |
1734 | { | |
1735 | unw_rec_list *ptr = alloc_record (prologue_gr); | |
e0c9811a JW |
1736 | memset (&ptr->r.record.r.mask, 0, sizeof (ptr->r.record.r.mask)); |
1737 | ptr->r.record.r.grmask = saved_mask; | |
800eeca4 JW |
1738 | ptr->r.record.r.grsave = reg; |
1739 | return ptr; | |
1740 | } | |
1741 | ||
1742 | static unw_rec_list * | |
1743 | output_body () | |
1744 | { | |
1745 | unw_rec_list *ptr = alloc_record (body); | |
1746 | return ptr; | |
1747 | } | |
1748 | ||
1749 | static unw_rec_list * | |
1750 | output_mem_stack_f (size) | |
1751 | unsigned int size; | |
1752 | { | |
1753 | unw_rec_list *ptr = alloc_record (mem_stack_f); | |
1754 | ptr->r.record.p.size = size; | |
1755 | return ptr; | |
1756 | } | |
1757 | ||
1758 | static unw_rec_list * | |
1759 | output_mem_stack_v () | |
1760 | { | |
1761 | unw_rec_list *ptr = alloc_record (mem_stack_v); | |
1762 | return ptr; | |
1763 | } | |
1764 | ||
1765 | static unw_rec_list * | |
1766 | output_psp_gr (gr) | |
1767 | unsigned int gr; | |
1768 | { | |
1769 | unw_rec_list *ptr = alloc_record (psp_gr); | |
1770 | ptr->r.record.p.gr = gr; | |
1771 | return ptr; | |
1772 | } | |
1773 | ||
1774 | static unw_rec_list * | |
1775 | output_psp_sprel (offset) | |
1776 | unsigned int offset; | |
1777 | { | |
1778 | unw_rec_list *ptr = alloc_record (psp_sprel); | |
542d6675 | 1779 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1780 | return ptr; |
1781 | } | |
1782 | ||
1783 | static unw_rec_list * | |
1784 | output_rp_when () | |
1785 | { | |
1786 | unw_rec_list *ptr = alloc_record (rp_when); | |
1787 | return ptr; | |
1788 | } | |
1789 | ||
1790 | static unw_rec_list * | |
1791 | output_rp_gr (gr) | |
1792 | unsigned int gr; | |
1793 | { | |
1794 | unw_rec_list *ptr = alloc_record (rp_gr); | |
1795 | ptr->r.record.p.gr = gr; | |
1796 | return ptr; | |
1797 | } | |
1798 | ||
1799 | static unw_rec_list * | |
1800 | output_rp_br (br) | |
1801 | unsigned int br; | |
1802 | { | |
1803 | unw_rec_list *ptr = alloc_record (rp_br); | |
1804 | ptr->r.record.p.br = br; | |
1805 | return ptr; | |
1806 | } | |
1807 | ||
1808 | static unw_rec_list * | |
1809 | output_rp_psprel (offset) | |
1810 | unsigned int offset; | |
1811 | { | |
1812 | unw_rec_list *ptr = alloc_record (rp_psprel); | |
542d6675 | 1813 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1814 | return ptr; |
1815 | } | |
1816 | ||
1817 | static unw_rec_list * | |
1818 | output_rp_sprel (offset) | |
1819 | unsigned int offset; | |
1820 | { | |
1821 | unw_rec_list *ptr = alloc_record (rp_sprel); | |
542d6675 | 1822 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1823 | return ptr; |
1824 | } | |
1825 | ||
1826 | static unw_rec_list * | |
1827 | output_pfs_when () | |
1828 | { | |
1829 | unw_rec_list *ptr = alloc_record (pfs_when); | |
1830 | return ptr; | |
1831 | } | |
1832 | ||
1833 | static unw_rec_list * | |
1834 | output_pfs_gr (gr) | |
1835 | unsigned int gr; | |
1836 | { | |
1837 | unw_rec_list *ptr = alloc_record (pfs_gr); | |
1838 | ptr->r.record.p.gr = gr; | |
1839 | return ptr; | |
1840 | } | |
1841 | ||
1842 | static unw_rec_list * | |
1843 | output_pfs_psprel (offset) | |
1844 | unsigned int offset; | |
1845 | { | |
1846 | unw_rec_list *ptr = alloc_record (pfs_psprel); | |
542d6675 | 1847 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1848 | return ptr; |
1849 | } | |
1850 | ||
1851 | static unw_rec_list * | |
1852 | output_pfs_sprel (offset) | |
1853 | unsigned int offset; | |
1854 | { | |
1855 | unw_rec_list *ptr = alloc_record (pfs_sprel); | |
542d6675 | 1856 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1857 | return ptr; |
1858 | } | |
1859 | ||
1860 | static unw_rec_list * | |
1861 | output_preds_when () | |
1862 | { | |
1863 | unw_rec_list *ptr = alloc_record (preds_when); | |
1864 | return ptr; | |
1865 | } | |
1866 | ||
1867 | static unw_rec_list * | |
1868 | output_preds_gr (gr) | |
1869 | unsigned int gr; | |
1870 | { | |
1871 | unw_rec_list *ptr = alloc_record (preds_gr); | |
1872 | ptr->r.record.p.gr = gr; | |
1873 | return ptr; | |
1874 | } | |
1875 | ||
1876 | static unw_rec_list * | |
1877 | output_preds_psprel (offset) | |
1878 | unsigned int offset; | |
1879 | { | |
1880 | unw_rec_list *ptr = alloc_record (preds_psprel); | |
542d6675 | 1881 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1882 | return ptr; |
1883 | } | |
1884 | ||
1885 | static unw_rec_list * | |
1886 | output_preds_sprel (offset) | |
1887 | unsigned int offset; | |
1888 | { | |
1889 | unw_rec_list *ptr = alloc_record (preds_sprel); | |
542d6675 | 1890 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1891 | return ptr; |
1892 | } | |
1893 | ||
1894 | static unw_rec_list * | |
1895 | output_fr_mem (mask) | |
1896 | unsigned int mask; | |
1897 | { | |
1898 | unw_rec_list *ptr = alloc_record (fr_mem); | |
1899 | ptr->r.record.p.rmask = mask; | |
1900 | return ptr; | |
1901 | } | |
1902 | ||
1903 | static unw_rec_list * | |
1904 | output_frgr_mem (gr_mask, fr_mask) | |
1905 | unsigned int gr_mask; | |
1906 | unsigned int fr_mask; | |
1907 | { | |
1908 | unw_rec_list *ptr = alloc_record (frgr_mem); | |
1909 | ptr->r.record.p.grmask = gr_mask; | |
1910 | ptr->r.record.p.frmask = fr_mask; | |
1911 | return ptr; | |
1912 | } | |
1913 | ||
1914 | static unw_rec_list * | |
1915 | output_gr_gr (mask, reg) | |
1916 | unsigned int mask; | |
1917 | unsigned int reg; | |
1918 | { | |
1919 | unw_rec_list *ptr = alloc_record (gr_gr); | |
1920 | ptr->r.record.p.grmask = mask; | |
1921 | ptr->r.record.p.gr = reg; | |
1922 | return ptr; | |
1923 | } | |
1924 | ||
1925 | static unw_rec_list * | |
1926 | output_gr_mem (mask) | |
1927 | unsigned int mask; | |
1928 | { | |
1929 | unw_rec_list *ptr = alloc_record (gr_mem); | |
1930 | ptr->r.record.p.rmask = mask; | |
1931 | return ptr; | |
1932 | } | |
1933 | ||
1934 | static unw_rec_list * | |
1935 | output_br_mem (unsigned int mask) | |
1936 | { | |
1937 | unw_rec_list *ptr = alloc_record (br_mem); | |
1938 | ptr->r.record.p.brmask = mask; | |
1939 | return ptr; | |
1940 | } | |
1941 | ||
1942 | static unw_rec_list * | |
1943 | output_br_gr (save_mask, reg) | |
1944 | unsigned int save_mask; | |
1945 | unsigned int reg; | |
1946 | { | |
1947 | unw_rec_list *ptr = alloc_record (br_gr); | |
1948 | ptr->r.record.p.brmask = save_mask; | |
1949 | ptr->r.record.p.gr = reg; | |
1950 | return ptr; | |
1951 | } | |
1952 | ||
1953 | static unw_rec_list * | |
1954 | output_spill_base (offset) | |
1955 | unsigned int offset; | |
1956 | { | |
1957 | unw_rec_list *ptr = alloc_record (spill_base); | |
542d6675 | 1958 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1959 | return ptr; |
1960 | } | |
1961 | ||
1962 | static unw_rec_list * | |
1963 | output_unat_when () | |
1964 | { | |
1965 | unw_rec_list *ptr = alloc_record (unat_when); | |
1966 | return ptr; | |
1967 | } | |
1968 | ||
1969 | static unw_rec_list * | |
1970 | output_unat_gr (gr) | |
1971 | unsigned int gr; | |
1972 | { | |
1973 | unw_rec_list *ptr = alloc_record (unat_gr); | |
1974 | ptr->r.record.p.gr = gr; | |
1975 | return ptr; | |
1976 | } | |
1977 | ||
1978 | static unw_rec_list * | |
1979 | output_unat_psprel (offset) | |
1980 | unsigned int offset; | |
1981 | { | |
1982 | unw_rec_list *ptr = alloc_record (unat_psprel); | |
542d6675 | 1983 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
1984 | return ptr; |
1985 | } | |
1986 | ||
1987 | static unw_rec_list * | |
1988 | output_unat_sprel (offset) | |
1989 | unsigned int offset; | |
1990 | { | |
1991 | unw_rec_list *ptr = alloc_record (unat_sprel); | |
542d6675 | 1992 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
1993 | return ptr; |
1994 | } | |
1995 | ||
1996 | static unw_rec_list * | |
1997 | output_lc_when () | |
1998 | { | |
1999 | unw_rec_list *ptr = alloc_record (lc_when); | |
2000 | return ptr; | |
2001 | } | |
2002 | ||
2003 | static unw_rec_list * | |
2004 | output_lc_gr (gr) | |
2005 | unsigned int gr; | |
2006 | { | |
2007 | unw_rec_list *ptr = alloc_record (lc_gr); | |
2008 | ptr->r.record.p.gr = gr; | |
2009 | return ptr; | |
2010 | } | |
2011 | ||
2012 | static unw_rec_list * | |
2013 | output_lc_psprel (offset) | |
2014 | unsigned int offset; | |
2015 | { | |
2016 | unw_rec_list *ptr = alloc_record (lc_psprel); | |
542d6675 | 2017 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2018 | return ptr; |
2019 | } | |
2020 | ||
2021 | static unw_rec_list * | |
2022 | output_lc_sprel (offset) | |
2023 | unsigned int offset; | |
2024 | { | |
2025 | unw_rec_list *ptr = alloc_record (lc_sprel); | |
542d6675 | 2026 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2027 | return ptr; |
2028 | } | |
2029 | ||
2030 | static unw_rec_list * | |
2031 | output_fpsr_when () | |
2032 | { | |
2033 | unw_rec_list *ptr = alloc_record (fpsr_when); | |
2034 | return ptr; | |
2035 | } | |
2036 | ||
2037 | static unw_rec_list * | |
2038 | output_fpsr_gr (gr) | |
2039 | unsigned int gr; | |
2040 | { | |
2041 | unw_rec_list *ptr = alloc_record (fpsr_gr); | |
2042 | ptr->r.record.p.gr = gr; | |
2043 | return ptr; | |
2044 | } | |
2045 | ||
2046 | static unw_rec_list * | |
2047 | output_fpsr_psprel (offset) | |
2048 | unsigned int offset; | |
2049 | { | |
2050 | unw_rec_list *ptr = alloc_record (fpsr_psprel); | |
542d6675 | 2051 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2052 | return ptr; |
2053 | } | |
2054 | ||
2055 | static unw_rec_list * | |
2056 | output_fpsr_sprel (offset) | |
2057 | unsigned int offset; | |
2058 | { | |
2059 | unw_rec_list *ptr = alloc_record (fpsr_sprel); | |
542d6675 | 2060 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2061 | return ptr; |
2062 | } | |
2063 | ||
2064 | static unw_rec_list * | |
2065 | output_priunat_when_gr () | |
2066 | { | |
2067 | unw_rec_list *ptr = alloc_record (priunat_when_gr); | |
2068 | return ptr; | |
2069 | } | |
2070 | ||
2071 | static unw_rec_list * | |
2072 | output_priunat_when_mem () | |
2073 | { | |
2074 | unw_rec_list *ptr = alloc_record (priunat_when_mem); | |
2075 | return ptr; | |
2076 | } | |
2077 | ||
2078 | static unw_rec_list * | |
2079 | output_priunat_gr (gr) | |
2080 | unsigned int gr; | |
2081 | { | |
2082 | unw_rec_list *ptr = alloc_record (priunat_gr); | |
2083 | ptr->r.record.p.gr = gr; | |
2084 | return ptr; | |
2085 | } | |
2086 | ||
2087 | static unw_rec_list * | |
2088 | output_priunat_psprel (offset) | |
2089 | unsigned int offset; | |
2090 | { | |
2091 | unw_rec_list *ptr = alloc_record (priunat_psprel); | |
542d6675 | 2092 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2093 | return ptr; |
2094 | } | |
2095 | ||
2096 | static unw_rec_list * | |
2097 | output_priunat_sprel (offset) | |
2098 | unsigned int offset; | |
2099 | { | |
2100 | unw_rec_list *ptr = alloc_record (priunat_sprel); | |
542d6675 | 2101 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2102 | return ptr; |
2103 | } | |
2104 | ||
2105 | static unw_rec_list * | |
2106 | output_bsp_when () | |
2107 | { | |
2108 | unw_rec_list *ptr = alloc_record (bsp_when); | |
2109 | return ptr; | |
2110 | } | |
2111 | ||
2112 | static unw_rec_list * | |
2113 | output_bsp_gr (gr) | |
2114 | unsigned int gr; | |
2115 | { | |
2116 | unw_rec_list *ptr = alloc_record (bsp_gr); | |
2117 | ptr->r.record.p.gr = gr; | |
2118 | return ptr; | |
2119 | } | |
2120 | ||
2121 | static unw_rec_list * | |
2122 | output_bsp_psprel (offset) | |
2123 | unsigned int offset; | |
2124 | { | |
2125 | unw_rec_list *ptr = alloc_record (bsp_psprel); | |
542d6675 | 2126 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2127 | return ptr; |
2128 | } | |
2129 | ||
2130 | static unw_rec_list * | |
2131 | output_bsp_sprel (offset) | |
2132 | unsigned int offset; | |
2133 | { | |
2134 | unw_rec_list *ptr = alloc_record (bsp_sprel); | |
542d6675 | 2135 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2136 | return ptr; |
2137 | } | |
2138 | ||
2139 | static unw_rec_list * | |
2140 | output_bspstore_when () | |
2141 | { | |
2142 | unw_rec_list *ptr = alloc_record (bspstore_when); | |
2143 | return ptr; | |
2144 | } | |
2145 | ||
2146 | static unw_rec_list * | |
2147 | output_bspstore_gr (gr) | |
2148 | unsigned int gr; | |
2149 | { | |
2150 | unw_rec_list *ptr = alloc_record (bspstore_gr); | |
2151 | ptr->r.record.p.gr = gr; | |
2152 | return ptr; | |
2153 | } | |
2154 | ||
2155 | static unw_rec_list * | |
2156 | output_bspstore_psprel (offset) | |
2157 | unsigned int offset; | |
2158 | { | |
2159 | unw_rec_list *ptr = alloc_record (bspstore_psprel); | |
542d6675 | 2160 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2161 | return ptr; |
2162 | } | |
2163 | ||
2164 | static unw_rec_list * | |
2165 | output_bspstore_sprel (offset) | |
2166 | unsigned int offset; | |
2167 | { | |
2168 | unw_rec_list *ptr = alloc_record (bspstore_sprel); | |
542d6675 | 2169 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2170 | return ptr; |
2171 | } | |
2172 | ||
2173 | static unw_rec_list * | |
2174 | output_rnat_when () | |
2175 | { | |
2176 | unw_rec_list *ptr = alloc_record (rnat_when); | |
2177 | return ptr; | |
2178 | } | |
2179 | ||
2180 | static unw_rec_list * | |
2181 | output_rnat_gr (gr) | |
2182 | unsigned int gr; | |
2183 | { | |
2184 | unw_rec_list *ptr = alloc_record (rnat_gr); | |
2185 | ptr->r.record.p.gr = gr; | |
2186 | return ptr; | |
2187 | } | |
2188 | ||
2189 | static unw_rec_list * | |
2190 | output_rnat_psprel (offset) | |
2191 | unsigned int offset; | |
2192 | { | |
2193 | unw_rec_list *ptr = alloc_record (rnat_psprel); | |
542d6675 | 2194 | ptr->r.record.p.pspoff = offset / 4; |
800eeca4 JW |
2195 | return ptr; |
2196 | } | |
2197 | ||
2198 | static unw_rec_list * | |
2199 | output_rnat_sprel (offset) | |
2200 | unsigned int offset; | |
2201 | { | |
2202 | unw_rec_list *ptr = alloc_record (rnat_sprel); | |
542d6675 | 2203 | ptr->r.record.p.spoff = offset / 4; |
800eeca4 JW |
2204 | return ptr; |
2205 | } | |
2206 | ||
2207 | static unw_rec_list * | |
e0c9811a JW |
2208 | output_unwabi (abi, context) |
2209 | unsigned long abi; | |
2210 | unsigned long context; | |
800eeca4 | 2211 | { |
e0c9811a JW |
2212 | unw_rec_list *ptr = alloc_record (unwabi); |
2213 | ptr->r.record.p.abi = abi; | |
2214 | ptr->r.record.p.context = context; | |
800eeca4 JW |
2215 | return ptr; |
2216 | } | |
2217 | ||
2218 | static unw_rec_list * | |
e0c9811a | 2219 | output_epilogue (unsigned long ecount) |
800eeca4 | 2220 | { |
e0c9811a JW |
2221 | unw_rec_list *ptr = alloc_record (epilogue); |
2222 | ptr->r.record.b.ecount = ecount; | |
800eeca4 JW |
2223 | return ptr; |
2224 | } | |
2225 | ||
2226 | static unw_rec_list * | |
e0c9811a | 2227 | output_label_state (unsigned long label) |
800eeca4 | 2228 | { |
e0c9811a JW |
2229 | unw_rec_list *ptr = alloc_record (label_state); |
2230 | ptr->r.record.b.label = label; | |
800eeca4 JW |
2231 | return ptr; |
2232 | } | |
2233 | ||
2234 | static unw_rec_list * | |
e0c9811a JW |
2235 | output_copy_state (unsigned long label) |
2236 | { | |
2237 | unw_rec_list *ptr = alloc_record (copy_state); | |
2238 | ptr->r.record.b.label = label; | |
2239 | return ptr; | |
2240 | } | |
2241 | ||
2242 | static unw_rec_list * | |
2243 | output_spill_psprel (ab, reg, offset) | |
2244 | unsigned int ab; | |
800eeca4 JW |
2245 | unsigned int reg; |
2246 | unsigned int offset; | |
2247 | { | |
2248 | unw_rec_list *ptr = alloc_record (spill_psprel); | |
e0c9811a | 2249 | ptr->r.record.x.ab = ab; |
800eeca4 | 2250 | ptr->r.record.x.reg = reg; |
542d6675 | 2251 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2252 | return ptr; |
2253 | } | |
2254 | ||
2255 | static unw_rec_list * | |
e0c9811a JW |
2256 | output_spill_sprel (ab, reg, offset) |
2257 | unsigned int ab; | |
800eeca4 JW |
2258 | unsigned int reg; |
2259 | unsigned int offset; | |
2260 | { | |
2261 | unw_rec_list *ptr = alloc_record (spill_sprel); | |
e0c9811a | 2262 | ptr->r.record.x.ab = ab; |
800eeca4 | 2263 | ptr->r.record.x.reg = reg; |
542d6675 | 2264 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2265 | return ptr; |
2266 | } | |
2267 | ||
2268 | static unw_rec_list * | |
e0c9811a JW |
2269 | output_spill_psprel_p (ab, reg, offset, predicate) |
2270 | unsigned int ab; | |
800eeca4 JW |
2271 | unsigned int reg; |
2272 | unsigned int offset; | |
2273 | unsigned int predicate; | |
2274 | { | |
2275 | unw_rec_list *ptr = alloc_record (spill_psprel_p); | |
e0c9811a | 2276 | ptr->r.record.x.ab = ab; |
800eeca4 | 2277 | ptr->r.record.x.reg = reg; |
542d6675 | 2278 | ptr->r.record.x.pspoff = offset / 4; |
800eeca4 JW |
2279 | ptr->r.record.x.qp = predicate; |
2280 | return ptr; | |
2281 | } | |
2282 | ||
2283 | static unw_rec_list * | |
e0c9811a JW |
2284 | output_spill_sprel_p (ab, reg, offset, predicate) |
2285 | unsigned int ab; | |
800eeca4 JW |
2286 | unsigned int reg; |
2287 | unsigned int offset; | |
2288 | unsigned int predicate; | |
2289 | { | |
2290 | unw_rec_list *ptr = alloc_record (spill_sprel_p); | |
e0c9811a | 2291 | ptr->r.record.x.ab = ab; |
800eeca4 | 2292 | ptr->r.record.x.reg = reg; |
542d6675 | 2293 | ptr->r.record.x.spoff = offset / 4; |
800eeca4 JW |
2294 | ptr->r.record.x.qp = predicate; |
2295 | return ptr; | |
2296 | } | |
2297 | ||
2298 | static unw_rec_list * | |
e0c9811a JW |
2299 | output_spill_reg (ab, reg, targ_reg, xy) |
2300 | unsigned int ab; | |
800eeca4 JW |
2301 | unsigned int reg; |
2302 | unsigned int targ_reg; | |
2303 | unsigned int xy; | |
2304 | { | |
2305 | unw_rec_list *ptr = alloc_record (spill_reg); | |
e0c9811a | 2306 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2307 | ptr->r.record.x.reg = reg; |
2308 | ptr->r.record.x.treg = targ_reg; | |
2309 | ptr->r.record.x.xy = xy; | |
2310 | return ptr; | |
2311 | } | |
2312 | ||
2313 | static unw_rec_list * | |
e0c9811a JW |
2314 | output_spill_reg_p (ab, reg, targ_reg, xy, predicate) |
2315 | unsigned int ab; | |
800eeca4 JW |
2316 | unsigned int reg; |
2317 | unsigned int targ_reg; | |
2318 | unsigned int xy; | |
2319 | unsigned int predicate; | |
2320 | { | |
2321 | unw_rec_list *ptr = alloc_record (spill_reg_p); | |
e0c9811a | 2322 | ptr->r.record.x.ab = ab; |
800eeca4 JW |
2323 | ptr->r.record.x.reg = reg; |
2324 | ptr->r.record.x.treg = targ_reg; | |
2325 | ptr->r.record.x.xy = xy; | |
2326 | ptr->r.record.x.qp = predicate; | |
2327 | return ptr; | |
2328 | } | |
2329 | ||
197865e8 | 2330 | /* Given a unw_rec_list process the correct format with the |
800eeca4 | 2331 | specified function. */ |
542d6675 | 2332 | |
800eeca4 JW |
2333 | static void |
2334 | process_one_record (ptr, f) | |
2335 | unw_rec_list *ptr; | |
2336 | vbyte_func f; | |
2337 | { | |
e0c9811a JW |
2338 | unsigned long fr_mask, gr_mask; |
2339 | ||
197865e8 | 2340 | switch (ptr->r.type) |
800eeca4 | 2341 | { |
542d6675 KH |
2342 | case gr_mem: |
2343 | case fr_mem: | |
2344 | case br_mem: | |
2345 | case frgr_mem: | |
2346 | /* These are taken care of by prologue/prologue_gr. */ | |
2347 | break; | |
e0c9811a | 2348 | |
542d6675 KH |
2349 | case prologue_gr: |
2350 | case prologue: | |
2351 | if (ptr->r.type == prologue_gr) | |
2352 | output_R2_format (f, ptr->r.record.r.grmask, | |
2353 | ptr->r.record.r.grsave, ptr->r.record.r.rlen); | |
2354 | else | |
800eeca4 | 2355 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); |
542d6675 KH |
2356 | |
2357 | /* Output descriptor(s) for union of register spills (if any). */ | |
2358 | gr_mask = ptr->r.record.r.mask.gr_mem; | |
2359 | fr_mask = ptr->r.record.r.mask.fr_mem; | |
2360 | if (fr_mask) | |
2361 | { | |
2362 | if ((fr_mask & ~0xfUL) == 0) | |
2363 | output_P6_format (f, fr_mem, fr_mask); | |
2364 | else | |
2365 | { | |
2366 | output_P5_format (f, gr_mask, fr_mask); | |
2367 | gr_mask = 0; | |
2368 | } | |
2369 | } | |
2370 | if (gr_mask) | |
2371 | output_P6_format (f, gr_mem, gr_mask); | |
2372 | if (ptr->r.record.r.mask.br_mem) | |
2373 | output_P1_format (f, ptr->r.record.r.mask.br_mem); | |
2374 | ||
2375 | /* output imask descriptor if necessary: */ | |
2376 | if (ptr->r.record.r.mask.i) | |
2377 | output_P4_format (f, ptr->r.record.r.mask.i, | |
2378 | ptr->r.record.r.imask_size); | |
2379 | break; | |
2380 | ||
2381 | case body: | |
2382 | output_R1_format (f, ptr->r.type, ptr->r.record.r.rlen); | |
2383 | break; | |
2384 | case mem_stack_f: | |
2385 | case mem_stack_v: | |
2386 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, | |
2387 | ptr->r.record.p.size); | |
2388 | break; | |
2389 | case psp_gr: | |
2390 | case rp_gr: | |
2391 | case pfs_gr: | |
2392 | case preds_gr: | |
2393 | case unat_gr: | |
2394 | case lc_gr: | |
2395 | case fpsr_gr: | |
2396 | case priunat_gr: | |
2397 | case bsp_gr: | |
2398 | case bspstore_gr: | |
2399 | case rnat_gr: | |
2400 | output_P3_format (f, ptr->r.type, ptr->r.record.p.gr); | |
2401 | break; | |
2402 | case rp_br: | |
2403 | output_P3_format (f, rp_br, ptr->r.record.p.br); | |
2404 | break; | |
2405 | case psp_sprel: | |
2406 | output_P7_format (f, psp_sprel, ptr->r.record.p.spoff, 0); | |
2407 | break; | |
2408 | case rp_when: | |
2409 | case pfs_when: | |
2410 | case preds_when: | |
2411 | case unat_when: | |
2412 | case lc_when: | |
2413 | case fpsr_when: | |
2414 | output_P7_format (f, ptr->r.type, ptr->r.record.p.t, 0); | |
2415 | break; | |
2416 | case rp_psprel: | |
2417 | case pfs_psprel: | |
2418 | case preds_psprel: | |
2419 | case unat_psprel: | |
2420 | case lc_psprel: | |
2421 | case fpsr_psprel: | |
2422 | case spill_base: | |
2423 | output_P7_format (f, ptr->r.type, ptr->r.record.p.pspoff, 0); | |
2424 | break; | |
2425 | case rp_sprel: | |
2426 | case pfs_sprel: | |
2427 | case preds_sprel: | |
2428 | case unat_sprel: | |
2429 | case lc_sprel: | |
2430 | case fpsr_sprel: | |
2431 | case priunat_sprel: | |
2432 | case bsp_sprel: | |
2433 | case bspstore_sprel: | |
2434 | case rnat_sprel: | |
2435 | output_P8_format (f, ptr->r.type, ptr->r.record.p.spoff); | |
2436 | break; | |
2437 | case gr_gr: | |
2438 | output_P9_format (f, ptr->r.record.p.grmask, ptr->r.record.p.gr); | |
2439 | break; | |
2440 | case br_gr: | |
2441 | output_P2_format (f, ptr->r.record.p.brmask, ptr->r.record.p.gr); | |
2442 | break; | |
2443 | case spill_mask: | |
2444 | as_bad ("spill_mask record unimplemented."); | |
2445 | break; | |
2446 | case priunat_when_gr: | |
2447 | case priunat_when_mem: | |
2448 | case bsp_when: | |
2449 | case bspstore_when: | |
2450 | case rnat_when: | |
2451 | output_P8_format (f, ptr->r.type, ptr->r.record.p.t); | |
2452 | break; | |
2453 | case priunat_psprel: | |
2454 | case bsp_psprel: | |
2455 | case bspstore_psprel: | |
2456 | case rnat_psprel: | |
2457 | output_P8_format (f, ptr->r.type, ptr->r.record.p.pspoff); | |
2458 | break; | |
2459 | case unwabi: | |
2460 | output_P10_format (f, ptr->r.record.p.abi, ptr->r.record.p.context); | |
2461 | break; | |
2462 | case epilogue: | |
2463 | output_B3_format (f, ptr->r.record.b.ecount, ptr->r.record.b.t); | |
2464 | break; | |
2465 | case label_state: | |
2466 | case copy_state: | |
2467 | output_B4_format (f, ptr->r.type, ptr->r.record.b.label); | |
2468 | break; | |
2469 | case spill_psprel: | |
2470 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2471 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2472 | ptr->r.record.x.pspoff); | |
2473 | break; | |
2474 | case spill_sprel: | |
2475 | output_X1_format (f, ptr->r.type, ptr->r.record.x.ab, | |
2476 | ptr->r.record.x.reg, ptr->r.record.x.t, | |
2477 | ptr->r.record.x.spoff); | |
2478 | break; | |
2479 | case spill_reg: | |
2480 | output_X2_format (f, ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2481 | ptr->r.record.x.xy >> 1, ptr->r.record.x.xy, | |
2482 | ptr->r.record.x.treg, ptr->r.record.x.t); | |
2483 | break; | |
2484 | case spill_psprel_p: | |
2485 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2486 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2487 | ptr->r.record.x.t, ptr->r.record.x.pspoff); | |
2488 | break; | |
2489 | case spill_sprel_p: | |
2490 | output_X3_format (f, ptr->r.type, ptr->r.record.x.qp, | |
2491 | ptr->r.record.x.ab, ptr->r.record.x.reg, | |
2492 | ptr->r.record.x.t, ptr->r.record.x.spoff); | |
2493 | break; | |
2494 | case spill_reg_p: | |
2495 | output_X4_format (f, ptr->r.record.x.qp, ptr->r.record.x.ab, | |
2496 | ptr->r.record.x.reg, ptr->r.record.x.xy >> 1, | |
2497 | ptr->r.record.x.xy, ptr->r.record.x.treg, | |
2498 | ptr->r.record.x.t); | |
2499 | break; | |
2500 | default: | |
2501 | as_bad ("record_type_not_valid"); | |
2502 | break; | |
800eeca4 JW |
2503 | } |
2504 | } | |
2505 | ||
197865e8 | 2506 | /* Given a unw_rec_list list, process all the records with |
800eeca4 JW |
2507 | the specified function. */ |
2508 | static void | |
2509 | process_unw_records (list, f) | |
2510 | unw_rec_list *list; | |
2511 | vbyte_func f; | |
2512 | { | |
2513 | unw_rec_list *ptr; | |
2514 | for (ptr = list; ptr; ptr = ptr->next) | |
2515 | process_one_record (ptr, f); | |
2516 | } | |
2517 | ||
2518 | /* Determine the size of a record list in bytes. */ | |
2519 | static int | |
2520 | calc_record_size (list) | |
2521 | unw_rec_list *list; | |
2522 | { | |
2523 | vbyte_count = 0; | |
2524 | process_unw_records (list, count_output); | |
2525 | return vbyte_count; | |
2526 | } | |
2527 | ||
e0c9811a JW |
2528 | /* Update IMASK bitmask to reflect the fact that one or more registers |
2529 | of type TYPE are saved starting at instruction with index T. If N | |
2530 | bits are set in REGMASK, it is assumed that instructions T through | |
2531 | T+N-1 save these registers. | |
2532 | ||
2533 | TYPE values: | |
2534 | 0: no save | |
2535 | 1: instruction saves next fp reg | |
2536 | 2: instruction saves next general reg | |
2537 | 3: instruction saves next branch reg */ | |
2538 | static void | |
2539 | set_imask (region, regmask, t, type) | |
2540 | unw_rec_list *region; | |
2541 | unsigned long regmask; | |
2542 | unsigned long t; | |
2543 | unsigned int type; | |
2544 | { | |
2545 | unsigned char *imask; | |
2546 | unsigned long imask_size; | |
2547 | unsigned int i; | |
2548 | int pos; | |
2549 | ||
2550 | imask = region->r.record.r.mask.i; | |
2551 | imask_size = region->r.record.r.imask_size; | |
2552 | if (!imask) | |
2553 | { | |
542d6675 | 2554 | imask_size = (region->r.record.r.rlen * 2 + 7) / 8 + 1; |
e0c9811a JW |
2555 | imask = xmalloc (imask_size); |
2556 | memset (imask, 0, imask_size); | |
2557 | ||
2558 | region->r.record.r.imask_size = imask_size; | |
2559 | region->r.record.r.mask.i = imask; | |
2560 | } | |
2561 | ||
542d6675 KH |
2562 | i = (t / 4) + 1; |
2563 | pos = 2 * (3 - t % 4); | |
e0c9811a JW |
2564 | while (regmask) |
2565 | { | |
2566 | if (i >= imask_size) | |
2567 | { | |
2568 | as_bad ("Ignoring attempt to spill beyond end of region"); | |
2569 | return; | |
2570 | } | |
2571 | ||
2572 | imask[i] |= (type & 0x3) << pos; | |
197865e8 | 2573 | |
e0c9811a JW |
2574 | regmask &= (regmask - 1); |
2575 | pos -= 2; | |
2576 | if (pos < 0) | |
2577 | { | |
2578 | pos = 0; | |
2579 | ++i; | |
2580 | } | |
2581 | } | |
2582 | } | |
2583 | ||
2584 | static int | |
2585 | count_bits (unsigned long mask) | |
2586 | { | |
2587 | int n = 0; | |
2588 | ||
2589 | while (mask) | |
2590 | { | |
2591 | mask &= mask - 1; | |
2592 | ++n; | |
2593 | } | |
2594 | return n; | |
2595 | } | |
2596 | ||
f5a30c2e JW |
2597 | /* Return the number of instruction slots from FIRST_ADDR to SLOT_ADDR. |
2598 | SLOT_FRAG is the frag containing SLOT_ADDR, and FIRST_FRAG is the frag | |
2599 | containing FIRST_ADDR. */ | |
2600 | ||
e0c9811a | 2601 | unsigned long |
f5a30c2e JW |
2602 | slot_index (slot_addr, slot_frag, first_addr, first_frag) |
2603 | unsigned long slot_addr; | |
2604 | fragS *slot_frag; | |
2605 | unsigned long first_addr; | |
2606 | fragS *first_frag; | |
e0c9811a | 2607 | { |
f5a30c2e JW |
2608 | unsigned long index = 0; |
2609 | ||
2610 | /* First time we are called, the initial address and frag are invalid. */ | |
2611 | if (first_addr == 0) | |
2612 | return 0; | |
2613 | ||
2614 | /* If the two addresses are in different frags, then we need to add in | |
2615 | the remaining size of this frag, and then the entire size of intermediate | |
2616 | frags. */ | |
2617 | while (slot_frag != first_frag) | |
2618 | { | |
2619 | unsigned long start_addr = (unsigned long) &first_frag->fr_literal; | |
2620 | ||
2621 | /* Add in the full size of the frag converted to instruction slots. */ | |
2622 | index += 3 * (first_frag->fr_fix >> 4); | |
2623 | /* Subtract away the initial part before first_addr. */ | |
2624 | index -= (3 * ((first_addr >> 4) - (start_addr >> 4)) | |
2625 | + ((first_addr & 0x3) - (start_addr & 0x3))); | |
e0c9811a | 2626 | |
f5a30c2e JW |
2627 | /* Move to the beginning of the next frag. */ |
2628 | first_frag = first_frag->fr_next; | |
2629 | first_addr = (unsigned long) &first_frag->fr_literal; | |
2630 | } | |
2631 | ||
2632 | /* Add in the used part of the last frag. */ | |
2633 | index += (3 * ((slot_addr >> 4) - (first_addr >> 4)) | |
2634 | + ((slot_addr & 0x3) - (first_addr & 0x3))); | |
2635 | return index; | |
2636 | } | |
4a1805b1 | 2637 | |
91a2ae2a RH |
2638 | /* Optimize unwind record directives. */ |
2639 | ||
2640 | static unw_rec_list * | |
2641 | optimize_unw_records (list) | |
2642 | unw_rec_list *list; | |
2643 | { | |
2644 | if (!list) | |
2645 | return NULL; | |
2646 | ||
2647 | /* If the only unwind record is ".prologue" or ".prologue" followed | |
2648 | by ".body", then we can optimize the unwind directives away. */ | |
2649 | if (list->r.type == prologue | |
2650 | && (list->next == NULL | |
2651 | || (list->next->r.type == body && list->next->next == NULL))) | |
2652 | return NULL; | |
2653 | ||
2654 | return list; | |
2655 | } | |
2656 | ||
800eeca4 JW |
2657 | /* Given a complete record list, process any records which have |
2658 | unresolved fields, (ie length counts for a prologue). After | |
197865e8 | 2659 | this has been run, all neccessary information should be available |
800eeca4 | 2660 | within each record to generate an image. */ |
542d6675 | 2661 | |
800eeca4 JW |
2662 | static void |
2663 | fixup_unw_records (list) | |
2664 | unw_rec_list *list; | |
2665 | { | |
e0c9811a JW |
2666 | unw_rec_list *ptr, *region = 0; |
2667 | unsigned long first_addr = 0, rlen = 0, t; | |
f5a30c2e | 2668 | fragS *first_frag = 0; |
e0c9811a | 2669 | |
800eeca4 JW |
2670 | for (ptr = list; ptr; ptr = ptr->next) |
2671 | { | |
2672 | if (ptr->slot_number == SLOT_NUM_NOT_SET) | |
542d6675 | 2673 | as_bad (" Insn slot not set in unwind record."); |
f5a30c2e JW |
2674 | t = slot_index (ptr->slot_number, ptr->slot_frag, |
2675 | first_addr, first_frag); | |
800eeca4 JW |
2676 | switch (ptr->r.type) |
2677 | { | |
542d6675 KH |
2678 | case prologue: |
2679 | case prologue_gr: | |
2680 | case body: | |
2681 | { | |
2682 | unw_rec_list *last; | |
2683 | int size, dir_len = 0; | |
2684 | unsigned long last_addr; | |
f5a30c2e | 2685 | fragS *last_frag; |
542d6675 KH |
2686 | |
2687 | first_addr = ptr->slot_number; | |
f5a30c2e | 2688 | first_frag = ptr->slot_frag; |
542d6675 KH |
2689 | ptr->slot_number = 0; |
2690 | /* Find either the next body/prologue start, or the end of | |
2691 | the list, and determine the size of the region. */ | |
2692 | last_addr = unwind.next_slot_number; | |
f5a30c2e | 2693 | last_frag = unwind.next_slot_frag; |
542d6675 KH |
2694 | for (last = ptr->next; last != NULL; last = last->next) |
2695 | if (last->r.type == prologue || last->r.type == prologue_gr | |
2696 | || last->r.type == body) | |
2697 | { | |
2698 | last_addr = last->slot_number; | |
f5a30c2e | 2699 | last_frag = last->slot_frag; |
542d6675 KH |
2700 | break; |
2701 | } | |
2702 | else if (!last->next) | |
2703 | { | |
2704 | /* In the absence of an explicit .body directive, | |
2705 | the prologue ends after the last instruction | |
2706 | covered by an unwind directive. */ | |
2707 | if (ptr->r.type != body) | |
2708 | { | |
2709 | last_addr = last->slot_number; | |
f5a30c2e | 2710 | last_frag = last->slot_frag; |
542d6675 KH |
2711 | switch (last->r.type) |
2712 | { | |
2713 | case frgr_mem: | |
2714 | dir_len = (count_bits (last->r.record.p.frmask) | |
2715 | + count_bits (last->r.record.p.grmask)); | |
2716 | break; | |
2717 | case fr_mem: | |
2718 | case gr_mem: | |
2719 | dir_len += count_bits (last->r.record.p.rmask); | |
2720 | break; | |
2721 | case br_mem: | |
2722 | case br_gr: | |
2723 | dir_len += count_bits (last->r.record.p.brmask); | |
2724 | break; | |
2725 | case gr_gr: | |
2726 | dir_len += count_bits (last->r.record.p.grmask); | |
2727 | break; | |
2728 | default: | |
2729 | dir_len = 1; | |
2730 | break; | |
2731 | } | |
2732 | } | |
2733 | break; | |
2734 | } | |
f5a30c2e JW |
2735 | size = (slot_index (last_addr, last_frag, first_addr, first_frag) |
2736 | + dir_len); | |
542d6675 | 2737 | rlen = ptr->r.record.r.rlen = size; |
1e16b528 AS |
2738 | if (ptr->r.type == body) |
2739 | /* End of region. */ | |
2740 | region = 0; | |
2741 | else | |
2742 | region = ptr; | |
e0c9811a | 2743 | break; |
542d6675 KH |
2744 | } |
2745 | case epilogue: | |
2746 | ptr->r.record.b.t = rlen - 1 - t; | |
2747 | break; | |
e0c9811a | 2748 | |
542d6675 KH |
2749 | case mem_stack_f: |
2750 | case mem_stack_v: | |
2751 | case rp_when: | |
2752 | case pfs_when: | |
2753 | case preds_when: | |
2754 | case unat_when: | |
2755 | case lc_when: | |
2756 | case fpsr_when: | |
2757 | case priunat_when_gr: | |
2758 | case priunat_when_mem: | |
2759 | case bsp_when: | |
2760 | case bspstore_when: | |
2761 | case rnat_when: | |
2762 | ptr->r.record.p.t = t; | |
2763 | break; | |
e0c9811a | 2764 | |
542d6675 KH |
2765 | case spill_reg: |
2766 | case spill_sprel: | |
2767 | case spill_psprel: | |
2768 | case spill_reg_p: | |
2769 | case spill_sprel_p: | |
2770 | case spill_psprel_p: | |
2771 | ptr->r.record.x.t = t; | |
2772 | break; | |
e0c9811a | 2773 | |
542d6675 KH |
2774 | case frgr_mem: |
2775 | if (!region) | |
2776 | { | |
2777 | as_bad ("frgr_mem record before region record!\n"); | |
2778 | return; | |
2779 | } | |
2780 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.frmask; | |
2781 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.grmask; | |
2782 | set_imask (region, ptr->r.record.p.frmask, t, 1); | |
2783 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2784 | break; | |
2785 | case fr_mem: | |
2786 | if (!region) | |
2787 | { | |
2788 | as_bad ("fr_mem record before region record!\n"); | |
2789 | return; | |
2790 | } | |
2791 | region->r.record.r.mask.fr_mem |= ptr->r.record.p.rmask; | |
2792 | set_imask (region, ptr->r.record.p.rmask, t, 1); | |
2793 | break; | |
2794 | case gr_mem: | |
2795 | if (!region) | |
2796 | { | |
2797 | as_bad ("gr_mem record before region record!\n"); | |
2798 | return; | |
2799 | } | |
2800 | region->r.record.r.mask.gr_mem |= ptr->r.record.p.rmask; | |
2801 | set_imask (region, ptr->r.record.p.rmask, t, 2); | |
2802 | break; | |
2803 | case br_mem: | |
2804 | if (!region) | |
2805 | { | |
2806 | as_bad ("br_mem record before region record!\n"); | |
2807 | return; | |
2808 | } | |
2809 | region->r.record.r.mask.br_mem |= ptr->r.record.p.brmask; | |
2810 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2811 | break; | |
e0c9811a | 2812 | |
542d6675 KH |
2813 | case gr_gr: |
2814 | if (!region) | |
2815 | { | |
2816 | as_bad ("gr_gr record before region record!\n"); | |
2817 | return; | |
2818 | } | |
2819 | set_imask (region, ptr->r.record.p.grmask, t, 2); | |
2820 | break; | |
2821 | case br_gr: | |
2822 | if (!region) | |
2823 | { | |
2824 | as_bad ("br_gr record before region record!\n"); | |
2825 | return; | |
2826 | } | |
2827 | set_imask (region, ptr->r.record.p.brmask, t, 3); | |
2828 | break; | |
e0c9811a | 2829 | |
542d6675 KH |
2830 | default: |
2831 | break; | |
800eeca4 JW |
2832 | } |
2833 | } | |
2834 | } | |
2835 | ||
557debba JW |
2836 | /* Helper routine for output_unw_records. Emits the header for the unwind |
2837 | info. */ | |
2838 | ||
2839 | static int | |
07726851 | 2840 | setup_unwind_header (int size, unsigned char **mem) |
557debba JW |
2841 | { |
2842 | int x, extra = 0; | |
1cd8ff38 | 2843 | valueT flag_value; |
557debba JW |
2844 | |
2845 | /* pad to pointer-size boundry. */ | |
2846 | x = size % md.pointer_size; | |
2847 | if (x != 0) | |
2848 | extra = md.pointer_size - x; | |
2849 | ||
40449e9f | 2850 | /* Add 8 for the header + a pointer for the |
557debba JW |
2851 | personality offset. */ |
2852 | *mem = xmalloc (size + extra + 8 + md.pointer_size); | |
2853 | ||
2854 | /* Clear the padding area and personality. */ | |
40449e9f | 2855 | memset (*mem + 8 + size, 0, extra + md.pointer_size); |
1cd8ff38 | 2856 | |
557debba | 2857 | /* Initialize the header area. */ |
1cd8ff38 NC |
2858 | if (unwind.personality_routine) |
2859 | { | |
2860 | if (md.flags & EF_IA_64_ABI64) | |
2861 | flag_value = (bfd_vma) 3 << 32; | |
2862 | else | |
2863 | /* 32-bit unwind info block. */ | |
2864 | flag_value = (bfd_vma) 0x1003 << 32; | |
2865 | } | |
2866 | else | |
2867 | flag_value = 0; | |
557debba | 2868 | |
1cd8ff38 NC |
2869 | md_number_to_chars (*mem, (((bfd_vma) 1 << 48) /* Version. */ |
2870 | | flag_value /* U & E handler flags. */ | |
2871 | | ((size + extra) / md.pointer_size)), /* Length. */ | |
557debba JW |
2872 | 8); |
2873 | ||
2874 | return extra; | |
2875 | } | |
2876 | ||
800eeca4 JW |
2877 | /* Generate an unwind image from a record list. Returns the number of |
2878 | bytes in the resulting image. The memory image itselof is returned | |
2879 | in the 'ptr' parameter. */ | |
2880 | static int | |
2881 | output_unw_records (list, ptr) | |
2882 | unw_rec_list *list; | |
2883 | void **ptr; | |
2884 | { | |
557debba | 2885 | int size, extra; |
800eeca4 JW |
2886 | unsigned char *mem; |
2887 | ||
91a2ae2a RH |
2888 | *ptr = NULL; |
2889 | ||
2890 | list = optimize_unw_records (list); | |
800eeca4 JW |
2891 | fixup_unw_records (list); |
2892 | size = calc_record_size (list); | |
2893 | ||
91a2ae2a RH |
2894 | if (size > 0 || unwind.force_unwind_entry) |
2895 | { | |
2896 | unwind.force_unwind_entry = 0; | |
07726851 | 2897 | extra = setup_unwind_header (size, &mem); |
800eeca4 | 2898 | |
91a2ae2a | 2899 | vbyte_mem_ptr = mem + 8; |
91a2ae2a RH |
2900 | process_unw_records (list, output_vbyte_mem); |
2901 | ||
2902 | *ptr = mem; | |
2903 | ||
557debba | 2904 | size += extra + 8 + md.pointer_size; |
91a2ae2a RH |
2905 | } |
2906 | return size; | |
800eeca4 JW |
2907 | } |
2908 | ||
e0c9811a JW |
2909 | static int |
2910 | convert_expr_to_ab_reg (e, ab, regp) | |
2911 | expressionS *e; | |
2912 | unsigned int *ab; | |
2913 | unsigned int *regp; | |
2914 | { | |
2915 | unsigned int reg; | |
2916 | ||
2917 | if (e->X_op != O_register) | |
2918 | return 0; | |
2919 | ||
2920 | reg = e->X_add_number; | |
2434f565 | 2921 | if (reg >= (REG_GR + 4) && reg <= (REG_GR + 7)) |
e0c9811a JW |
2922 | { |
2923 | *ab = 0; | |
2924 | *regp = reg - REG_GR; | |
2925 | } | |
2434f565 JW |
2926 | else if ((reg >= (REG_FR + 2) && reg <= (REG_FR + 5)) |
2927 | || (reg >= (REG_FR + 16) && reg <= (REG_FR + 31))) | |
e0c9811a JW |
2928 | { |
2929 | *ab = 1; | |
2930 | *regp = reg - REG_FR; | |
2931 | } | |
2434f565 | 2932 | else if (reg >= (REG_BR + 1) && reg <= (REG_BR + 5)) |
e0c9811a JW |
2933 | { |
2934 | *ab = 2; | |
2935 | *regp = reg - REG_BR; | |
2936 | } | |
2937 | else | |
2938 | { | |
2939 | *ab = 3; | |
2940 | switch (reg) | |
2941 | { | |
2942 | case REG_PR: *regp = 0; break; | |
2943 | case REG_PSP: *regp = 1; break; | |
2944 | case REG_PRIUNAT: *regp = 2; break; | |
2945 | case REG_BR + 0: *regp = 3; break; | |
2946 | case REG_AR + AR_BSP: *regp = 4; break; | |
2947 | case REG_AR + AR_BSPSTORE: *regp = 5; break; | |
2948 | case REG_AR + AR_RNAT: *regp = 6; break; | |
2949 | case REG_AR + AR_UNAT: *regp = 7; break; | |
2950 | case REG_AR + AR_FPSR: *regp = 8; break; | |
2951 | case REG_AR + AR_PFS: *regp = 9; break; | |
2952 | case REG_AR + AR_LC: *regp = 10; break; | |
2953 | ||
2954 | default: | |
2955 | return 0; | |
2956 | } | |
2957 | } | |
2958 | return 1; | |
197865e8 | 2959 | } |
e0c9811a JW |
2960 | |
2961 | static int | |
2962 | convert_expr_to_xy_reg (e, xy, regp) | |
2963 | expressionS *e; | |
2964 | unsigned int *xy; | |
2965 | unsigned int *regp; | |
2966 | { | |
2967 | unsigned int reg; | |
2968 | ||
2969 | if (e->X_op != O_register) | |
2970 | return 0; | |
2971 | ||
2972 | reg = e->X_add_number; | |
2973 | ||
2434f565 | 2974 | if (/* reg >= REG_GR && */ reg <= (REG_GR + 127)) |
e0c9811a JW |
2975 | { |
2976 | *xy = 0; | |
2977 | *regp = reg - REG_GR; | |
2978 | } | |
2434f565 | 2979 | else if (reg >= REG_FR && reg <= (REG_FR + 127)) |
e0c9811a JW |
2980 | { |
2981 | *xy = 1; | |
2982 | *regp = reg - REG_FR; | |
2983 | } | |
2434f565 | 2984 | else if (reg >= REG_BR && reg <= (REG_BR + 7)) |
e0c9811a JW |
2985 | { |
2986 | *xy = 2; | |
2987 | *regp = reg - REG_BR; | |
2988 | } | |
2989 | else | |
2990 | return -1; | |
2991 | return 1; | |
197865e8 | 2992 | } |
e0c9811a | 2993 | |
800eeca4 JW |
2994 | static void |
2995 | dot_radix (dummy) | |
2434f565 | 2996 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
2997 | { |
2998 | int radix; | |
2999 | ||
3000 | SKIP_WHITESPACE (); | |
3001 | radix = *input_line_pointer++; | |
3002 | ||
3003 | if (radix != 'C' && !is_end_of_line[(unsigned char) radix]) | |
3004 | { | |
3005 | as_bad ("Radix `%c' unsupported", *input_line_pointer); | |
542d6675 | 3006 | ignore_rest_of_line (); |
800eeca4 JW |
3007 | return; |
3008 | } | |
3009 | } | |
3010 | ||
3011 | /* .sbss, .bss etc. are macros that expand into ".section SECNAME". */ | |
3012 | static void | |
3013 | dot_special_section (which) | |
3014 | int which; | |
3015 | { | |
3016 | set_section ((char *) special_section_name[which]); | |
3017 | } | |
3018 | ||
3019 | static void | |
3020 | add_unwind_entry (ptr) | |
3021 | unw_rec_list *ptr; | |
3022 | { | |
e0c9811a JW |
3023 | if (unwind.tail) |
3024 | unwind.tail->next = ptr; | |
800eeca4 | 3025 | else |
e0c9811a JW |
3026 | unwind.list = ptr; |
3027 | unwind.tail = ptr; | |
800eeca4 JW |
3028 | |
3029 | /* The current entry can in fact be a chain of unwind entries. */ | |
e0c9811a JW |
3030 | if (unwind.current_entry == NULL) |
3031 | unwind.current_entry = ptr; | |
800eeca4 JW |
3032 | } |
3033 | ||
197865e8 | 3034 | static void |
800eeca4 | 3035 | dot_fframe (dummy) |
2434f565 | 3036 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3037 | { |
3038 | expressionS e; | |
e0c9811a | 3039 | |
800eeca4 | 3040 | parse_operand (&e); |
197865e8 | 3041 | |
800eeca4 JW |
3042 | if (e.X_op != O_constant) |
3043 | as_bad ("Operand to .fframe must be a constant"); | |
3044 | else | |
e0c9811a JW |
3045 | add_unwind_entry (output_mem_stack_f (e.X_add_number)); |
3046 | } | |
3047 | ||
197865e8 | 3048 | static void |
e0c9811a | 3049 | dot_vframe (dummy) |
2434f565 | 3050 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3051 | { |
3052 | expressionS e; | |
3053 | unsigned reg; | |
3054 | ||
3055 | parse_operand (&e); | |
3056 | reg = e.X_add_number - REG_GR; | |
3057 | if (e.X_op == O_register && reg < 128) | |
800eeca4 | 3058 | { |
e0c9811a | 3059 | add_unwind_entry (output_mem_stack_v ()); |
30d25259 RH |
3060 | if (! (unwind.prologue_mask & 2)) |
3061 | add_unwind_entry (output_psp_gr (reg)); | |
800eeca4 | 3062 | } |
e0c9811a JW |
3063 | else |
3064 | as_bad ("First operand to .vframe must be a general register"); | |
800eeca4 JW |
3065 | } |
3066 | ||
197865e8 | 3067 | static void |
e0c9811a | 3068 | dot_vframesp (dummy) |
2434f565 | 3069 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3070 | { |
e0c9811a JW |
3071 | expressionS e; |
3072 | ||
3073 | parse_operand (&e); | |
3074 | if (e.X_op == O_constant) | |
3075 | { | |
3076 | add_unwind_entry (output_mem_stack_v ()); | |
3077 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
3078 | } | |
3079 | else | |
69906a9b | 3080 | as_bad ("Operand to .vframesp must be a constant (sp-relative offset)"); |
e0c9811a JW |
3081 | } |
3082 | ||
197865e8 | 3083 | static void |
e0c9811a | 3084 | dot_vframepsp (dummy) |
2434f565 | 3085 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3086 | { |
3087 | expressionS e; | |
3088 | ||
3089 | parse_operand (&e); | |
3090 | if (e.X_op == O_constant) | |
3091 | { | |
3092 | add_unwind_entry (output_mem_stack_v ()); | |
3093 | add_unwind_entry (output_psp_sprel (e.X_add_number)); | |
3094 | } | |
3095 | else | |
69906a9b | 3096 | as_bad ("Operand to .vframepsp must be a constant (psp-relative offset)"); |
800eeca4 JW |
3097 | } |
3098 | ||
197865e8 | 3099 | static void |
800eeca4 | 3100 | dot_save (dummy) |
2434f565 | 3101 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3102 | { |
3103 | expressionS e1, e2; | |
3104 | int sep; | |
3105 | int reg1, reg2; | |
3106 | ||
3107 | sep = parse_operand (&e1); | |
3108 | if (sep != ',') | |
3109 | as_bad ("No second operand to .save"); | |
3110 | sep = parse_operand (&e2); | |
3111 | ||
e0c9811a | 3112 | reg1 = e1.X_add_number; |
800eeca4 | 3113 | reg2 = e2.X_add_number - REG_GR; |
197865e8 | 3114 | |
800eeca4 | 3115 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 3116 | if (e1.X_op == O_register) |
800eeca4 | 3117 | { |
542d6675 | 3118 | if (e2.X_op == O_register && reg2 >= 0 && reg2 < 128) |
800eeca4 JW |
3119 | { |
3120 | switch (reg1) | |
3121 | { | |
542d6675 KH |
3122 | case REG_AR + AR_BSP: |
3123 | add_unwind_entry (output_bsp_when ()); | |
3124 | add_unwind_entry (output_bsp_gr (reg2)); | |
3125 | break; | |
3126 | case REG_AR + AR_BSPSTORE: | |
3127 | add_unwind_entry (output_bspstore_when ()); | |
3128 | add_unwind_entry (output_bspstore_gr (reg2)); | |
3129 | break; | |
3130 | case REG_AR + AR_RNAT: | |
3131 | add_unwind_entry (output_rnat_when ()); | |
3132 | add_unwind_entry (output_rnat_gr (reg2)); | |
3133 | break; | |
3134 | case REG_AR + AR_UNAT: | |
3135 | add_unwind_entry (output_unat_when ()); | |
3136 | add_unwind_entry (output_unat_gr (reg2)); | |
3137 | break; | |
3138 | case REG_AR + AR_FPSR: | |
3139 | add_unwind_entry (output_fpsr_when ()); | |
3140 | add_unwind_entry (output_fpsr_gr (reg2)); | |
3141 | break; | |
3142 | case REG_AR + AR_PFS: | |
3143 | add_unwind_entry (output_pfs_when ()); | |
3144 | if (! (unwind.prologue_mask & 4)) | |
3145 | add_unwind_entry (output_pfs_gr (reg2)); | |
3146 | break; | |
3147 | case REG_AR + AR_LC: | |
3148 | add_unwind_entry (output_lc_when ()); | |
3149 | add_unwind_entry (output_lc_gr (reg2)); | |
3150 | break; | |
3151 | case REG_BR: | |
3152 | add_unwind_entry (output_rp_when ()); | |
3153 | if (! (unwind.prologue_mask & 8)) | |
3154 | add_unwind_entry (output_rp_gr (reg2)); | |
3155 | break; | |
3156 | case REG_PR: | |
3157 | add_unwind_entry (output_preds_when ()); | |
3158 | if (! (unwind.prologue_mask & 1)) | |
3159 | add_unwind_entry (output_preds_gr (reg2)); | |
3160 | break; | |
3161 | case REG_PRIUNAT: | |
3162 | add_unwind_entry (output_priunat_when_gr ()); | |
3163 | add_unwind_entry (output_priunat_gr (reg2)); | |
3164 | break; | |
3165 | default: | |
3166 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3167 | } |
3168 | } | |
3169 | else | |
3170 | as_bad (" Second operand not a valid register"); | |
3171 | } | |
3172 | else | |
e0c9811a | 3173 | as_bad ("First operand not a register"); |
800eeca4 JW |
3174 | } |
3175 | ||
197865e8 | 3176 | static void |
800eeca4 | 3177 | dot_restore (dummy) |
2434f565 | 3178 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3179 | { |
e0c9811a | 3180 | expressionS e1, e2; |
33d01f33 | 3181 | unsigned long ecount; /* # of _additional_ regions to pop */ |
e0c9811a JW |
3182 | int sep; |
3183 | ||
3184 | sep = parse_operand (&e1); | |
3185 | if (e1.X_op != O_register || e1.X_add_number != REG_GR + 12) | |
3186 | { | |
3187 | as_bad ("First operand to .restore must be stack pointer (sp)"); | |
3188 | return; | |
3189 | } | |
3190 | ||
3191 | if (sep == ',') | |
3192 | { | |
3193 | parse_operand (&e2); | |
33d01f33 | 3194 | if (e2.X_op != O_constant || e2.X_add_number < 0) |
e0c9811a | 3195 | { |
33d01f33 | 3196 | as_bad ("Second operand to .restore must be a constant >= 0"); |
e0c9811a JW |
3197 | return; |
3198 | } | |
33d01f33 | 3199 | ecount = e2.X_add_number; |
e0c9811a | 3200 | } |
33d01f33 JW |
3201 | else |
3202 | ecount = unwind.prologue_count - 1; | |
6290819d NC |
3203 | |
3204 | if (ecount >= unwind.prologue_count) | |
3205 | { | |
3206 | as_bad ("Epilogue count of %lu exceeds number of nested prologues (%u)", | |
3207 | ecount + 1, unwind.prologue_count); | |
3208 | return; | |
3209 | } | |
3210 | ||
e0c9811a | 3211 | add_unwind_entry (output_epilogue (ecount)); |
33d01f33 JW |
3212 | |
3213 | if (ecount < unwind.prologue_count) | |
3214 | unwind.prologue_count -= ecount + 1; | |
3215 | else | |
3216 | unwind.prologue_count = 0; | |
e0c9811a JW |
3217 | } |
3218 | ||
197865e8 | 3219 | static void |
e0c9811a | 3220 | dot_restorereg (dummy) |
2434f565 | 3221 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3222 | { |
3223 | unsigned int ab, reg; | |
3224 | expressionS e; | |
3225 | ||
3226 | parse_operand (&e); | |
3227 | ||
3228 | if (!convert_expr_to_ab_reg (&e, &ab, ®)) | |
3229 | { | |
3230 | as_bad ("First operand to .restorereg must be a preserved register"); | |
3231 | return; | |
3232 | } | |
3233 | add_unwind_entry (output_spill_reg (ab, reg, 0, 0)); | |
3234 | } | |
3235 | ||
197865e8 | 3236 | static void |
e0c9811a | 3237 | dot_restorereg_p (dummy) |
2434f565 | 3238 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3239 | { |
3240 | unsigned int qp, ab, reg; | |
3241 | expressionS e1, e2; | |
3242 | int sep; | |
3243 | ||
3244 | sep = parse_operand (&e1); | |
3245 | if (sep != ',') | |
3246 | { | |
3247 | as_bad ("No second operand to .restorereg.p"); | |
3248 | return; | |
3249 | } | |
3250 | ||
3251 | parse_operand (&e2); | |
3252 | ||
3253 | qp = e1.X_add_number - REG_P; | |
3254 | if (e1.X_op != O_register || qp > 63) | |
3255 | { | |
3256 | as_bad ("First operand to .restorereg.p must be a predicate"); | |
3257 | return; | |
3258 | } | |
3259 | ||
3260 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3261 | { | |
3262 | as_bad ("Second operand to .restorereg.p must be a preserved register"); | |
3263 | return; | |
3264 | } | |
3265 | add_unwind_entry (output_spill_reg_p (ab, reg, 0, 0, qp)); | |
800eeca4 JW |
3266 | } |
3267 | ||
3268 | static int | |
91a2ae2a RH |
3269 | generate_unwind_image (text_name) |
3270 | const char *text_name; | |
800eeca4 JW |
3271 | { |
3272 | int size; | |
e39edc66 | 3273 | void *unw_rec; |
800eeca4 | 3274 | |
10850f29 JW |
3275 | /* Force out pending instructions, to make sure all unwind records have |
3276 | a valid slot_number field. */ | |
3277 | ia64_flush_insns (); | |
3278 | ||
800eeca4 | 3279 | /* Generate the unwind record. */ |
e39edc66 | 3280 | size = output_unw_records (unwind.list, &unw_rec); |
557debba JW |
3281 | if (size % md.pointer_size != 0) |
3282 | as_bad ("Unwind record is not a multiple of %d bytes.", md.pointer_size); | |
6290819d | 3283 | |
800eeca4 JW |
3284 | /* If there are unwind records, switch sections, and output the info. */ |
3285 | if (size != 0) | |
3286 | { | |
800eeca4 | 3287 | unsigned char *where; |
91a2ae2a | 3288 | char *sec_name; |
800eeca4 | 3289 | expressionS exp; |
1cd8ff38 | 3290 | bfd_reloc_code_real_type reloc; |
91a2ae2a RH |
3291 | |
3292 | make_unw_section_name (SPECIAL_SECTION_UNWIND_INFO, text_name, sec_name); | |
3293 | set_section (sec_name); | |
3294 | bfd_set_section_flags (stdoutput, now_seg, | |
3295 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); | |
800eeca4 | 3296 | |
557debba JW |
3297 | /* Make sure the section has 4 byte alignment for ILP32 and |
3298 | 8 byte alignment for LP64. */ | |
3299 | frag_align (md.pointer_size_shift, 0, 0); | |
3300 | record_alignment (now_seg, md.pointer_size_shift); | |
5e7474a7 | 3301 | |
800eeca4 | 3302 | /* Set expression which points to start of unwind descriptor area. */ |
e0c9811a | 3303 | unwind.info = expr_build_dot (); |
800eeca4 | 3304 | |
542d6675 | 3305 | where = (unsigned char *) frag_more (size); |
800eeca4 JW |
3306 | |
3307 | /* Issue a label for this address, and keep track of it to put it | |
3308 | in the unwind section. */ | |
3309 | ||
3310 | /* Copy the information from the unwind record into this section. The | |
3311 | data is already in the correct byte order. */ | |
3312 | memcpy (where, unw_rec, size); | |
91a2ae2a | 3313 | |
800eeca4 | 3314 | /* Add the personality address to the image. */ |
e0c9811a | 3315 | if (unwind.personality_routine != 0) |
542d6675 | 3316 | { |
40449e9f | 3317 | exp.X_op = O_symbol; |
e0c9811a | 3318 | exp.X_add_symbol = unwind.personality_routine; |
800eeca4 | 3319 | exp.X_add_number = 0; |
1cd8ff38 NC |
3320 | |
3321 | if (md.flags & EF_IA_64_BE) | |
3322 | { | |
3323 | if (md.flags & EF_IA_64_ABI64) | |
3324 | reloc = BFD_RELOC_IA64_LTOFF_FPTR64MSB; | |
3325 | else | |
3326 | reloc = BFD_RELOC_IA64_LTOFF_FPTR32MSB; | |
3327 | } | |
40449e9f | 3328 | else |
1cd8ff38 NC |
3329 | { |
3330 | if (md.flags & EF_IA_64_ABI64) | |
3331 | reloc = BFD_RELOC_IA64_LTOFF_FPTR64LSB; | |
3332 | else | |
3333 | reloc = BFD_RELOC_IA64_LTOFF_FPTR32LSB; | |
3334 | } | |
3335 | ||
3336 | fix_new_exp (frag_now, frag_now_fix () - md.pointer_size, | |
40449e9f | 3337 | md.pointer_size, &exp, 0, reloc); |
e0c9811a | 3338 | unwind.personality_routine = 0; |
542d6675 | 3339 | } |
800eeca4 JW |
3340 | } |
3341 | ||
e0c9811a | 3342 | free_list_records (unwind.list); |
6290819d | 3343 | free_saved_prologue_counts (); |
e0c9811a | 3344 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
800eeca4 JW |
3345 | |
3346 | return size; | |
3347 | } | |
3348 | ||
197865e8 | 3349 | static void |
542d6675 | 3350 | dot_handlerdata (dummy) |
2434f565 | 3351 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3352 | { |
91a2ae2a RH |
3353 | const char *text_name = segment_name (now_seg); |
3354 | ||
3355 | /* If text section name starts with ".text" (which it should), | |
3356 | strip this prefix off. */ | |
3357 | if (strcmp (text_name, ".text") == 0) | |
3358 | text_name = ""; | |
3359 | ||
3360 | unwind.force_unwind_entry = 1; | |
3361 | ||
3362 | /* Remember which segment we're in so we can switch back after .endp */ | |
3363 | unwind.saved_text_seg = now_seg; | |
3364 | unwind.saved_text_subseg = now_subseg; | |
3365 | ||
3366 | /* Generate unwind info into unwind-info section and then leave that | |
3367 | section as the currently active one so dataXX directives go into | |
3368 | the language specific data area of the unwind info block. */ | |
3369 | generate_unwind_image (text_name); | |
e0c9811a | 3370 | demand_empty_rest_of_line (); |
800eeca4 JW |
3371 | } |
3372 | ||
197865e8 | 3373 | static void |
800eeca4 | 3374 | dot_unwentry (dummy) |
2434f565 | 3375 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3376 | { |
91a2ae2a | 3377 | unwind.force_unwind_entry = 1; |
e0c9811a | 3378 | demand_empty_rest_of_line (); |
800eeca4 JW |
3379 | } |
3380 | ||
197865e8 | 3381 | static void |
800eeca4 | 3382 | dot_altrp (dummy) |
2434f565 | 3383 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3384 | { |
e0c9811a JW |
3385 | expressionS e; |
3386 | unsigned reg; | |
3387 | ||
3388 | parse_operand (&e); | |
3389 | reg = e.X_add_number - REG_BR; | |
3390 | if (e.X_op == O_register && reg < 8) | |
3391 | add_unwind_entry (output_rp_br (reg)); | |
3392 | else | |
3393 | as_bad ("First operand not a valid branch register"); | |
800eeca4 JW |
3394 | } |
3395 | ||
197865e8 | 3396 | static void |
e0c9811a JW |
3397 | dot_savemem (psprel) |
3398 | int psprel; | |
800eeca4 JW |
3399 | { |
3400 | expressionS e1, e2; | |
3401 | int sep; | |
3402 | int reg1, val; | |
3403 | ||
3404 | sep = parse_operand (&e1); | |
3405 | if (sep != ',') | |
e0c9811a | 3406 | as_bad ("No second operand to .save%ssp", psprel ? "p" : ""); |
800eeca4 JW |
3407 | sep = parse_operand (&e2); |
3408 | ||
e0c9811a | 3409 | reg1 = e1.X_add_number; |
800eeca4 | 3410 | val = e2.X_add_number; |
197865e8 | 3411 | |
800eeca4 | 3412 | /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */ |
e0c9811a | 3413 | if (e1.X_op == O_register) |
800eeca4 JW |
3414 | { |
3415 | if (e2.X_op == O_constant) | |
3416 | { | |
3417 | switch (reg1) | |
3418 | { | |
542d6675 KH |
3419 | case REG_AR + AR_BSP: |
3420 | add_unwind_entry (output_bsp_when ()); | |
3421 | add_unwind_entry ((psprel | |
3422 | ? output_bsp_psprel | |
3423 | : output_bsp_sprel) (val)); | |
3424 | break; | |
3425 | case REG_AR + AR_BSPSTORE: | |
3426 | add_unwind_entry (output_bspstore_when ()); | |
3427 | add_unwind_entry ((psprel | |
3428 | ? output_bspstore_psprel | |
3429 | : output_bspstore_sprel) (val)); | |
3430 | break; | |
3431 | case REG_AR + AR_RNAT: | |
3432 | add_unwind_entry (output_rnat_when ()); | |
3433 | add_unwind_entry ((psprel | |
3434 | ? output_rnat_psprel | |
3435 | : output_rnat_sprel) (val)); | |
3436 | break; | |
3437 | case REG_AR + AR_UNAT: | |
3438 | add_unwind_entry (output_unat_when ()); | |
3439 | add_unwind_entry ((psprel | |
3440 | ? output_unat_psprel | |
3441 | : output_unat_sprel) (val)); | |
3442 | break; | |
3443 | case REG_AR + AR_FPSR: | |
3444 | add_unwind_entry (output_fpsr_when ()); | |
3445 | add_unwind_entry ((psprel | |
3446 | ? output_fpsr_psprel | |
3447 | : output_fpsr_sprel) (val)); | |
3448 | break; | |
3449 | case REG_AR + AR_PFS: | |
3450 | add_unwind_entry (output_pfs_when ()); | |
3451 | add_unwind_entry ((psprel | |
3452 | ? output_pfs_psprel | |
3453 | : output_pfs_sprel) (val)); | |
3454 | break; | |
3455 | case REG_AR + AR_LC: | |
3456 | add_unwind_entry (output_lc_when ()); | |
3457 | add_unwind_entry ((psprel | |
3458 | ? output_lc_psprel | |
3459 | : output_lc_sprel) (val)); | |
3460 | break; | |
3461 | case REG_BR: | |
3462 | add_unwind_entry (output_rp_when ()); | |
3463 | add_unwind_entry ((psprel | |
3464 | ? output_rp_psprel | |
3465 | : output_rp_sprel) (val)); | |
3466 | break; | |
3467 | case REG_PR: | |
3468 | add_unwind_entry (output_preds_when ()); | |
3469 | add_unwind_entry ((psprel | |
3470 | ? output_preds_psprel | |
3471 | : output_preds_sprel) (val)); | |
3472 | break; | |
3473 | case REG_PRIUNAT: | |
3474 | add_unwind_entry (output_priunat_when_mem ()); | |
3475 | add_unwind_entry ((psprel | |
3476 | ? output_priunat_psprel | |
3477 | : output_priunat_sprel) (val)); | |
3478 | break; | |
3479 | default: | |
3480 | as_bad ("First operand not a valid register"); | |
800eeca4 JW |
3481 | } |
3482 | } | |
3483 | else | |
3484 | as_bad (" Second operand not a valid constant"); | |
3485 | } | |
3486 | else | |
e0c9811a | 3487 | as_bad ("First operand not a register"); |
800eeca4 JW |
3488 | } |
3489 | ||
197865e8 | 3490 | static void |
800eeca4 | 3491 | dot_saveg (dummy) |
2434f565 | 3492 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3493 | { |
3494 | expressionS e1, e2; | |
3495 | int sep; | |
3496 | sep = parse_operand (&e1); | |
3497 | if (sep == ',') | |
3498 | parse_operand (&e2); | |
197865e8 | 3499 | |
800eeca4 JW |
3500 | if (e1.X_op != O_constant) |
3501 | as_bad ("First operand to .save.g must be a constant."); | |
3502 | else | |
3503 | { | |
3504 | int grmask = e1.X_add_number; | |
3505 | if (sep != ',') | |
3506 | add_unwind_entry (output_gr_mem (grmask)); | |
3507 | else | |
542d6675 | 3508 | { |
800eeca4 | 3509 | int reg = e2.X_add_number - REG_GR; |
542d6675 | 3510 | if (e2.X_op == O_register && reg >= 0 && reg < 128) |
800eeca4 JW |
3511 | add_unwind_entry (output_gr_gr (grmask, reg)); |
3512 | else | |
3513 | as_bad ("Second operand is an invalid register."); | |
3514 | } | |
3515 | } | |
3516 | } | |
3517 | ||
197865e8 | 3518 | static void |
800eeca4 | 3519 | dot_savef (dummy) |
2434f565 | 3520 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3521 | { |
e0c9811a | 3522 | expressionS e1; |
800eeca4 JW |
3523 | int sep; |
3524 | sep = parse_operand (&e1); | |
197865e8 | 3525 | |
800eeca4 JW |
3526 | if (e1.X_op != O_constant) |
3527 | as_bad ("Operand to .save.f must be a constant."); | |
3528 | else | |
e0c9811a | 3529 | add_unwind_entry (output_fr_mem (e1.X_add_number)); |
800eeca4 JW |
3530 | } |
3531 | ||
197865e8 | 3532 | static void |
800eeca4 | 3533 | dot_saveb (dummy) |
2434f565 | 3534 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3535 | { |
e0c9811a JW |
3536 | expressionS e1, e2; |
3537 | unsigned int reg; | |
3538 | unsigned char sep; | |
3539 | int brmask; | |
3540 | ||
800eeca4 | 3541 | sep = parse_operand (&e1); |
800eeca4 | 3542 | if (e1.X_op != O_constant) |
800eeca4 | 3543 | { |
e0c9811a JW |
3544 | as_bad ("First operand to .save.b must be a constant."); |
3545 | return; | |
800eeca4 | 3546 | } |
e0c9811a JW |
3547 | brmask = e1.X_add_number; |
3548 | ||
3549 | if (sep == ',') | |
3550 | { | |
3551 | sep = parse_operand (&e2); | |
3552 | reg = e2.X_add_number - REG_GR; | |
3553 | if (e2.X_op != O_register || reg > 127) | |
3554 | { | |
3555 | as_bad ("Second operand to .save.b must be a general register."); | |
3556 | return; | |
3557 | } | |
3558 | add_unwind_entry (output_br_gr (brmask, e2.X_add_number)); | |
3559 | } | |
3560 | else | |
3561 | add_unwind_entry (output_br_mem (brmask)); | |
3562 | ||
3563 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3564 | ignore_rest_of_line (); | |
800eeca4 JW |
3565 | } |
3566 | ||
197865e8 | 3567 | static void |
800eeca4 | 3568 | dot_savegf (dummy) |
2434f565 | 3569 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3570 | { |
3571 | expressionS e1, e2; | |
3572 | int sep; | |
3573 | sep = parse_operand (&e1); | |
3574 | if (sep == ',') | |
3575 | parse_operand (&e2); | |
197865e8 | 3576 | |
800eeca4 JW |
3577 | if (e1.X_op != O_constant || sep != ',' || e2.X_op != O_constant) |
3578 | as_bad ("Both operands of .save.gf must be constants."); | |
3579 | else | |
3580 | { | |
3581 | int grmask = e1.X_add_number; | |
3582 | int frmask = e2.X_add_number; | |
3583 | add_unwind_entry (output_frgr_mem (grmask, frmask)); | |
3584 | } | |
3585 | } | |
3586 | ||
197865e8 | 3587 | static void |
800eeca4 | 3588 | dot_spill (dummy) |
2434f565 | 3589 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3590 | { |
3591 | expressionS e; | |
e0c9811a JW |
3592 | unsigned char sep; |
3593 | ||
3594 | sep = parse_operand (&e); | |
3595 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3596 | ignore_rest_of_line (); | |
197865e8 | 3597 | |
800eeca4 JW |
3598 | if (e.X_op != O_constant) |
3599 | as_bad ("Operand to .spill must be a constant"); | |
3600 | else | |
e0c9811a JW |
3601 | add_unwind_entry (output_spill_base (e.X_add_number)); |
3602 | } | |
3603 | ||
3604 | static void | |
3605 | dot_spillreg (dummy) | |
2434f565 | 3606 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3607 | { |
3608 | int sep, ab, xy, reg, treg; | |
3609 | expressionS e1, e2; | |
3610 | ||
3611 | sep = parse_operand (&e1); | |
3612 | if (sep != ',') | |
3613 | { | |
3614 | as_bad ("No second operand to .spillreg"); | |
3615 | return; | |
3616 | } | |
3617 | ||
3618 | parse_operand (&e2); | |
3619 | ||
3620 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
800eeca4 | 3621 | { |
e0c9811a JW |
3622 | as_bad ("First operand to .spillreg must be a preserved register"); |
3623 | return; | |
800eeca4 | 3624 | } |
e0c9811a JW |
3625 | |
3626 | if (!convert_expr_to_xy_reg (&e2, &xy, &treg)) | |
3627 | { | |
3628 | as_bad ("Second operand to .spillreg must be a register"); | |
3629 | return; | |
3630 | } | |
3631 | ||
3632 | add_unwind_entry (output_spill_reg (ab, reg, treg, xy)); | |
3633 | } | |
3634 | ||
3635 | static void | |
3636 | dot_spillmem (psprel) | |
3637 | int psprel; | |
3638 | { | |
3639 | expressionS e1, e2; | |
3640 | int sep, ab, reg; | |
3641 | ||
3642 | sep = parse_operand (&e1); | |
3643 | if (sep != ',') | |
3644 | { | |
3645 | as_bad ("Second operand missing"); | |
3646 | return; | |
3647 | } | |
3648 | ||
3649 | parse_operand (&e2); | |
3650 | ||
3651 | if (!convert_expr_to_ab_reg (&e1, &ab, ®)) | |
3652 | { | |
3653 | as_bad ("First operand to .spill%s must be a preserved register", | |
3654 | psprel ? "psp" : "sp"); | |
3655 | return; | |
3656 | } | |
3657 | ||
3658 | if (e2.X_op != O_constant) | |
3659 | { | |
3660 | as_bad ("Second operand to .spill%s must be a constant", | |
3661 | psprel ? "psp" : "sp"); | |
3662 | return; | |
3663 | } | |
3664 | ||
3665 | if (psprel) | |
3666 | add_unwind_entry (output_spill_psprel (ab, reg, e2.X_add_number)); | |
3667 | else | |
3668 | add_unwind_entry (output_spill_sprel (ab, reg, e2.X_add_number)); | |
3669 | } | |
3670 | ||
3671 | static void | |
3672 | dot_spillreg_p (dummy) | |
2434f565 | 3673 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3674 | { |
3675 | int sep, ab, xy, reg, treg; | |
3676 | expressionS e1, e2, e3; | |
3677 | unsigned int qp; | |
3678 | ||
3679 | sep = parse_operand (&e1); | |
3680 | if (sep != ',') | |
3681 | { | |
3682 | as_bad ("No second and third operand to .spillreg.p"); | |
3683 | return; | |
3684 | } | |
3685 | ||
3686 | sep = parse_operand (&e2); | |
3687 | if (sep != ',') | |
3688 | { | |
3689 | as_bad ("No third operand to .spillreg.p"); | |
3690 | return; | |
3691 | } | |
3692 | ||
3693 | parse_operand (&e3); | |
3694 | ||
3695 | qp = e1.X_add_number - REG_P; | |
3696 | ||
3697 | if (e1.X_op != O_register || qp > 63) | |
3698 | { | |
3699 | as_bad ("First operand to .spillreg.p must be a predicate"); | |
3700 | return; | |
3701 | } | |
3702 | ||
3703 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3704 | { | |
3705 | as_bad ("Second operand to .spillreg.p must be a preserved register"); | |
3706 | return; | |
3707 | } | |
3708 | ||
3709 | if (!convert_expr_to_xy_reg (&e3, &xy, &treg)) | |
3710 | { | |
3711 | as_bad ("Third operand to .spillreg.p must be a register"); | |
3712 | return; | |
3713 | } | |
3714 | ||
3715 | add_unwind_entry (output_spill_reg_p (ab, reg, treg, xy, qp)); | |
3716 | } | |
3717 | ||
3718 | static void | |
3719 | dot_spillmem_p (psprel) | |
3720 | int psprel; | |
3721 | { | |
3722 | expressionS e1, e2, e3; | |
3723 | int sep, ab, reg; | |
3724 | unsigned int qp; | |
3725 | ||
3726 | sep = parse_operand (&e1); | |
3727 | if (sep != ',') | |
3728 | { | |
3729 | as_bad ("Second operand missing"); | |
3730 | return; | |
3731 | } | |
3732 | ||
3733 | parse_operand (&e2); | |
3734 | if (sep != ',') | |
3735 | { | |
3736 | as_bad ("Second operand missing"); | |
3737 | return; | |
3738 | } | |
3739 | ||
3740 | parse_operand (&e3); | |
3741 | ||
3742 | qp = e1.X_add_number - REG_P; | |
3743 | if (e1.X_op != O_register || qp > 63) | |
3744 | { | |
3745 | as_bad ("First operand to .spill%s_p must be a predicate", | |
3746 | psprel ? "psp" : "sp"); | |
3747 | return; | |
3748 | } | |
3749 | ||
3750 | if (!convert_expr_to_ab_reg (&e2, &ab, ®)) | |
3751 | { | |
3752 | as_bad ("Second operand to .spill%s_p must be a preserved register", | |
3753 | psprel ? "psp" : "sp"); | |
3754 | return; | |
3755 | } | |
3756 | ||
3757 | if (e3.X_op != O_constant) | |
3758 | { | |
3759 | as_bad ("Third operand to .spill%s_p must be a constant", | |
3760 | psprel ? "psp" : "sp"); | |
3761 | return; | |
3762 | } | |
3763 | ||
3764 | if (psprel) | |
fa7fda74 | 3765 | add_unwind_entry (output_spill_psprel_p (ab, reg, e3.X_add_number, qp)); |
e0c9811a | 3766 | else |
fa7fda74 | 3767 | add_unwind_entry (output_spill_sprel_p (ab, reg, e3.X_add_number, qp)); |
e0c9811a JW |
3768 | } |
3769 | ||
6290819d NC |
3770 | static unsigned int |
3771 | get_saved_prologue_count (lbl) | |
3772 | unsigned long lbl; | |
3773 | { | |
3774 | label_prologue_count *lpc = unwind.saved_prologue_counts; | |
3775 | ||
3776 | while (lpc != NULL && lpc->label_number != lbl) | |
3777 | lpc = lpc->next; | |
3778 | ||
3779 | if (lpc != NULL) | |
3780 | return lpc->prologue_count; | |
3781 | ||
3782 | as_bad ("Missing .label_state %ld", lbl); | |
3783 | return 1; | |
3784 | } | |
3785 | ||
3786 | static void | |
3787 | save_prologue_count (lbl, count) | |
3788 | unsigned long lbl; | |
3789 | unsigned int count; | |
3790 | { | |
3791 | label_prologue_count *lpc = unwind.saved_prologue_counts; | |
3792 | ||
3793 | while (lpc != NULL && lpc->label_number != lbl) | |
3794 | lpc = lpc->next; | |
3795 | ||
3796 | if (lpc != NULL) | |
3797 | lpc->prologue_count = count; | |
3798 | else | |
3799 | { | |
40449e9f | 3800 | label_prologue_count *new_lpc = xmalloc (sizeof (* new_lpc)); |
6290819d NC |
3801 | |
3802 | new_lpc->next = unwind.saved_prologue_counts; | |
3803 | new_lpc->label_number = lbl; | |
3804 | new_lpc->prologue_count = count; | |
3805 | unwind.saved_prologue_counts = new_lpc; | |
3806 | } | |
3807 | } | |
3808 | ||
3809 | static void | |
3810 | free_saved_prologue_counts () | |
3811 | { | |
40449e9f KH |
3812 | label_prologue_count *lpc = unwind.saved_prologue_counts; |
3813 | label_prologue_count *next; | |
6290819d NC |
3814 | |
3815 | while (lpc != NULL) | |
3816 | { | |
3817 | next = lpc->next; | |
3818 | free (lpc); | |
3819 | lpc = next; | |
3820 | } | |
3821 | ||
3822 | unwind.saved_prologue_counts = NULL; | |
3823 | } | |
3824 | ||
e0c9811a JW |
3825 | static void |
3826 | dot_label_state (dummy) | |
2434f565 | 3827 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3828 | { |
3829 | expressionS e; | |
3830 | ||
3831 | parse_operand (&e); | |
3832 | if (e.X_op != O_constant) | |
3833 | { | |
3834 | as_bad ("Operand to .label_state must be a constant"); | |
3835 | return; | |
3836 | } | |
3837 | add_unwind_entry (output_label_state (e.X_add_number)); | |
6290819d | 3838 | save_prologue_count (e.X_add_number, unwind.prologue_count); |
e0c9811a JW |
3839 | } |
3840 | ||
3841 | static void | |
3842 | dot_copy_state (dummy) | |
2434f565 | 3843 | int dummy ATTRIBUTE_UNUSED; |
e0c9811a JW |
3844 | { |
3845 | expressionS e; | |
3846 | ||
3847 | parse_operand (&e); | |
3848 | if (e.X_op != O_constant) | |
3849 | { | |
3850 | as_bad ("Operand to .copy_state must be a constant"); | |
3851 | return; | |
3852 | } | |
3853 | add_unwind_entry (output_copy_state (e.X_add_number)); | |
6290819d | 3854 | unwind.prologue_count = get_saved_prologue_count (e.X_add_number); |
800eeca4 JW |
3855 | } |
3856 | ||
197865e8 | 3857 | static void |
800eeca4 | 3858 | dot_unwabi (dummy) |
2434f565 | 3859 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3860 | { |
e0c9811a JW |
3861 | expressionS e1, e2; |
3862 | unsigned char sep; | |
3863 | ||
3864 | sep = parse_operand (&e1); | |
3865 | if (sep != ',') | |
3866 | { | |
3867 | as_bad ("Second operand to .unwabi missing"); | |
3868 | return; | |
3869 | } | |
3870 | sep = parse_operand (&e2); | |
3871 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) | |
3872 | ignore_rest_of_line (); | |
3873 | ||
3874 | if (e1.X_op != O_constant) | |
3875 | { | |
3876 | as_bad ("First operand to .unwabi must be a constant"); | |
3877 | return; | |
3878 | } | |
3879 | ||
3880 | if (e2.X_op != O_constant) | |
3881 | { | |
3882 | as_bad ("Second operand to .unwabi must be a constant"); | |
3883 | return; | |
3884 | } | |
3885 | ||
3886 | add_unwind_entry (output_unwabi (e1.X_add_number, e2.X_add_number)); | |
800eeca4 JW |
3887 | } |
3888 | ||
197865e8 | 3889 | static void |
800eeca4 | 3890 | dot_personality (dummy) |
2434f565 | 3891 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3892 | { |
3893 | char *name, *p, c; | |
3894 | SKIP_WHITESPACE (); | |
3895 | name = input_line_pointer; | |
3896 | c = get_symbol_end (); | |
3897 | p = input_line_pointer; | |
e0c9811a | 3898 | unwind.personality_routine = symbol_find_or_make (name); |
91a2ae2a | 3899 | unwind.force_unwind_entry = 1; |
800eeca4 JW |
3900 | *p = c; |
3901 | SKIP_WHITESPACE (); | |
3902 | demand_empty_rest_of_line (); | |
3903 | } | |
3904 | ||
3905 | static void | |
3906 | dot_proc (dummy) | |
2434f565 | 3907 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3908 | { |
3909 | char *name, *p, c; | |
3910 | symbolS *sym; | |
3911 | ||
e0c9811a JW |
3912 | unwind.proc_start = expr_build_dot (); |
3913 | /* Parse names of main and alternate entry points and mark them as | |
542d6675 | 3914 | function symbols: */ |
800eeca4 JW |
3915 | while (1) |
3916 | { | |
3917 | SKIP_WHITESPACE (); | |
3918 | name = input_line_pointer; | |
3919 | c = get_symbol_end (); | |
3920 | p = input_line_pointer; | |
3921 | sym = symbol_find_or_make (name); | |
e0c9811a | 3922 | if (unwind.proc_start == 0) |
542d6675 | 3923 | { |
e0c9811a | 3924 | unwind.proc_start = sym; |
800eeca4 JW |
3925 | } |
3926 | symbol_get_bfdsym (sym)->flags |= BSF_FUNCTION; | |
3927 | *p = c; | |
3928 | SKIP_WHITESPACE (); | |
3929 | if (*input_line_pointer != ',') | |
3930 | break; | |
3931 | ++input_line_pointer; | |
3932 | } | |
3933 | demand_empty_rest_of_line (); | |
3934 | ia64_do_align (16); | |
3935 | ||
33d01f33 | 3936 | unwind.prologue_count = 0; |
e0c9811a JW |
3937 | unwind.list = unwind.tail = unwind.current_entry = NULL; |
3938 | unwind.personality_routine = 0; | |
800eeca4 JW |
3939 | } |
3940 | ||
3941 | static void | |
3942 | dot_body (dummy) | |
2434f565 | 3943 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3944 | { |
e0c9811a | 3945 | unwind.prologue = 0; |
30d25259 RH |
3946 | unwind.prologue_mask = 0; |
3947 | ||
800eeca4 | 3948 | add_unwind_entry (output_body ()); |
e0c9811a | 3949 | demand_empty_rest_of_line (); |
800eeca4 JW |
3950 | } |
3951 | ||
3952 | static void | |
3953 | dot_prologue (dummy) | |
2434f565 | 3954 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 | 3955 | { |
e0c9811a | 3956 | unsigned char sep; |
2434f565 | 3957 | int mask = 0, grsave = 0; |
e0c9811a | 3958 | |
e0c9811a | 3959 | if (!is_it_end_of_statement ()) |
800eeca4 JW |
3960 | { |
3961 | expressionS e1, e2; | |
800eeca4 JW |
3962 | sep = parse_operand (&e1); |
3963 | if (sep != ',') | |
3964 | as_bad ("No second operand to .prologue"); | |
3965 | sep = parse_operand (&e2); | |
e0c9811a | 3966 | if (!is_end_of_line[sep] && !is_it_end_of_statement ()) |
542d6675 | 3967 | ignore_rest_of_line (); |
800eeca4 JW |
3968 | |
3969 | if (e1.X_op == O_constant) | |
542d6675 | 3970 | { |
30d25259 RH |
3971 | mask = e1.X_add_number; |
3972 | ||
800eeca4 | 3973 | if (e2.X_op == O_constant) |
30d25259 RH |
3974 | grsave = e2.X_add_number; |
3975 | else if (e2.X_op == O_register | |
3976 | && (grsave = e2.X_add_number - REG_GR) < 128) | |
3977 | ; | |
800eeca4 | 3978 | else |
30d25259 RH |
3979 | as_bad ("Second operand not a constant or general register"); |
3980 | ||
3981 | add_unwind_entry (output_prologue_gr (mask, grsave)); | |
800eeca4 JW |
3982 | } |
3983 | else | |
3984 | as_bad ("First operand not a constant"); | |
3985 | } | |
3986 | else | |
3987 | add_unwind_entry (output_prologue ()); | |
30d25259 RH |
3988 | |
3989 | unwind.prologue = 1; | |
3990 | unwind.prologue_mask = mask; | |
33d01f33 | 3991 | ++unwind.prologue_count; |
800eeca4 JW |
3992 | } |
3993 | ||
3994 | static void | |
3995 | dot_endp (dummy) | |
2434f565 | 3996 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
3997 | { |
3998 | expressionS e; | |
3999 | unsigned char *ptr; | |
44f5c83a | 4000 | int bytes_per_address; |
800eeca4 JW |
4001 | long where; |
4002 | segT saved_seg; | |
4003 | subsegT saved_subseg; | |
91a2ae2a | 4004 | const char *sec_name, *text_name; |
c538998c JJ |
4005 | char *name, *p, c; |
4006 | symbolS *sym; | |
800eeca4 | 4007 | |
91a2ae2a RH |
4008 | if (unwind.saved_text_seg) |
4009 | { | |
4010 | saved_seg = unwind.saved_text_seg; | |
4011 | saved_subseg = unwind.saved_text_subseg; | |
4012 | unwind.saved_text_seg = NULL; | |
4013 | } | |
4014 | else | |
4015 | { | |
4016 | saved_seg = now_seg; | |
4017 | saved_subseg = now_subseg; | |
4018 | } | |
4019 | ||
4020 | /* | |
4021 | Use a slightly ugly scheme to derive the unwind section names from | |
4022 | the text section name: | |
4023 | ||
4024 | text sect. unwind table sect. | |
4025 | name: name: comments: | |
4026 | ---------- ----------------- -------------------------------- | |
4027 | .text .IA_64.unwind | |
4028 | .text.foo .IA_64.unwind.text.foo | |
4029 | .foo .IA_64.unwind.foo | |
579f31ac JJ |
4030 | .gnu.linkonce.t.foo |
4031 | .gnu.linkonce.ia64unw.foo | |
91a2ae2a RH |
4032 | _info .IA_64.unwind_info gas issues error message (ditto) |
4033 | _infoFOO .IA_64.unwind_infoFOO gas issues error message (ditto) | |
4034 | ||
4035 | This mapping is done so that: | |
4036 | ||
4037 | (a) An object file with unwind info only in .text will use | |
4038 | unwind section names .IA_64.unwind and .IA_64.unwind_info. | |
4039 | This follows the letter of the ABI and also ensures backwards | |
4040 | compatibility with older toolchains. | |
4041 | ||
4042 | (b) An object file with unwind info in multiple text sections | |
4043 | will use separate unwind sections for each text section. | |
4044 | This allows us to properly set the "sh_info" and "sh_link" | |
4045 | fields in SHT_IA_64_UNWIND as required by the ABI and also | |
4046 | lets GNU ld support programs with multiple segments | |
4047 | containing unwind info (as might be the case for certain | |
4048 | embedded applications). | |
40449e9f | 4049 | |
91a2ae2a RH |
4050 | (c) An error is issued if there would be a name clash. |
4051 | */ | |
4052 | text_name = segment_name (saved_seg); | |
4053 | if (strncmp (text_name, "_info", 5) == 0) | |
4054 | { | |
4055 | as_bad ("Illegal section name `%s' (causes unwind section name clash)", | |
4056 | text_name); | |
4057 | ignore_rest_of_line (); | |
4058 | return; | |
4059 | } | |
4060 | if (strcmp (text_name, ".text") == 0) | |
4061 | text_name = ""; | |
800eeca4 | 4062 | |
800eeca4 | 4063 | insn_group_break (1, 0, 0); |
800eeca4 | 4064 | |
91a2ae2a RH |
4065 | /* If there wasn't a .handlerdata, we haven't generated an image yet. */ |
4066 | if (!unwind.info) | |
4067 | generate_unwind_image (text_name); | |
800eeca4 | 4068 | |
91a2ae2a RH |
4069 | if (unwind.info || unwind.force_unwind_entry) |
4070 | { | |
4071 | subseg_set (md.last_text_seg, 0); | |
4072 | unwind.proc_end = expr_build_dot (); | |
5e7474a7 | 4073 | |
91a2ae2a RH |
4074 | make_unw_section_name (SPECIAL_SECTION_UNWIND, text_name, sec_name); |
4075 | set_section ((char *) sec_name); | |
4076 | bfd_set_section_flags (stdoutput, now_seg, | |
4077 | SEC_LOAD | SEC_ALLOC | SEC_READONLY); | |
5e7474a7 | 4078 | |
557debba JW |
4079 | /* Make sure that section has 4 byte alignment for ILP32 and |
4080 | 8 byte alignment for LP64. */ | |
4081 | record_alignment (now_seg, md.pointer_size_shift); | |
800eeca4 | 4082 | |
557debba JW |
4083 | /* Need space for 3 pointers for procedure start, procedure end, |
4084 | and unwind info. */ | |
4085 | ptr = frag_more (3 * md.pointer_size); | |
4086 | where = frag_now_fix () - (3 * md.pointer_size); | |
91a2ae2a | 4087 | bytes_per_address = bfd_arch_bits_per_address (stdoutput) / 8; |
800eeca4 | 4088 | |
40449e9f | 4089 | /* Issue the values of a) Proc Begin, b) Proc End, c) Unwind Record. */ |
91a2ae2a RH |
4090 | e.X_op = O_pseudo_fixup; |
4091 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
4092 | e.X_add_number = 0; | |
4093 | e.X_add_symbol = unwind.proc_start; | |
4094 | ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); | |
800eeca4 | 4095 | |
800eeca4 JW |
4096 | e.X_op = O_pseudo_fixup; |
4097 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
4098 | e.X_add_number = 0; | |
91a2ae2a RH |
4099 | e.X_add_symbol = unwind.proc_end; |
4100 | ia64_cons_fix_new (frag_now, where + bytes_per_address, | |
4101 | bytes_per_address, &e); | |
4102 | ||
4103 | if (unwind.info) | |
4104 | { | |
4105 | e.X_op = O_pseudo_fixup; | |
4106 | e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; | |
4107 | e.X_add_number = 0; | |
4108 | e.X_add_symbol = unwind.info; | |
4109 | ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), | |
4110 | bytes_per_address, &e); | |
4111 | } | |
4112 | else | |
4113 | md_number_to_chars (ptr + (bytes_per_address * 2), 0, | |
4114 | bytes_per_address); | |
800eeca4 | 4115 | |
91a2ae2a | 4116 | } |
800eeca4 | 4117 | subseg_set (saved_seg, saved_subseg); |
c538998c JJ |
4118 | |
4119 | /* Parse names of main and alternate entry points and set symbol sizes. */ | |
4120 | while (1) | |
4121 | { | |
4122 | SKIP_WHITESPACE (); | |
4123 | name = input_line_pointer; | |
4124 | c = get_symbol_end (); | |
4125 | p = input_line_pointer; | |
4126 | sym = symbol_find (name); | |
4127 | if (sym && unwind.proc_start | |
4128 | && (symbol_get_bfdsym (sym)->flags & BSF_FUNCTION) | |
4129 | && S_GET_SIZE (sym) == 0 && symbol_get_obj (sym)->size == NULL) | |
4130 | { | |
4131 | fragS *fr = symbol_get_frag (unwind.proc_start); | |
4132 | fragS *frag = symbol_get_frag (sym); | |
4133 | ||
4134 | /* Check whether the function label is at or beyond last | |
4135 | .proc directive. */ | |
4136 | while (fr && fr != frag) | |
4137 | fr = fr->fr_next; | |
4138 | if (fr) | |
4139 | { | |
4140 | if (frag == frag_now && SEG_NORMAL (now_seg)) | |
4141 | S_SET_SIZE (sym, frag_now_fix () - S_GET_VALUE (sym)); | |
4142 | else | |
4143 | { | |
4144 | symbol_get_obj (sym)->size = | |
4145 | (expressionS *) xmalloc (sizeof (expressionS)); | |
4146 | symbol_get_obj (sym)->size->X_op = O_subtract; | |
4147 | symbol_get_obj (sym)->size->X_add_symbol | |
4148 | = symbol_new (FAKE_LABEL_NAME, now_seg, | |
4149 | frag_now_fix (), frag_now); | |
4150 | symbol_get_obj (sym)->size->X_op_symbol = sym; | |
4151 | symbol_get_obj (sym)->size->X_add_number = 0; | |
4152 | } | |
4153 | } | |
4154 | } | |
4155 | *p = c; | |
4156 | SKIP_WHITESPACE (); | |
4157 | if (*input_line_pointer != ',') | |
4158 | break; | |
4159 | ++input_line_pointer; | |
4160 | } | |
4161 | demand_empty_rest_of_line (); | |
e0c9811a | 4162 | unwind.proc_start = unwind.proc_end = unwind.info = 0; |
800eeca4 JW |
4163 | } |
4164 | ||
4165 | static void | |
4166 | dot_template (template) | |
4167 | int template; | |
4168 | { | |
4169 | CURR_SLOT.user_template = template; | |
4170 | } | |
4171 | ||
4172 | static void | |
4173 | dot_regstk (dummy) | |
2434f565 | 4174 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4175 | { |
4176 | int ins, locs, outs, rots; | |
4177 | ||
4178 | if (is_it_end_of_statement ()) | |
4179 | ins = locs = outs = rots = 0; | |
4180 | else | |
4181 | { | |
4182 | ins = get_absolute_expression (); | |
4183 | if (*input_line_pointer++ != ',') | |
4184 | goto err; | |
4185 | locs = get_absolute_expression (); | |
4186 | if (*input_line_pointer++ != ',') | |
4187 | goto err; | |
4188 | outs = get_absolute_expression (); | |
4189 | if (*input_line_pointer++ != ',') | |
4190 | goto err; | |
4191 | rots = get_absolute_expression (); | |
4192 | } | |
4193 | set_regstack (ins, locs, outs, rots); | |
4194 | return; | |
4195 | ||
4196 | err: | |
4197 | as_bad ("Comma expected"); | |
4198 | ignore_rest_of_line (); | |
4199 | } | |
4200 | ||
4201 | static void | |
4202 | dot_rot (type) | |
4203 | int type; | |
4204 | { | |
4205 | unsigned num_regs, num_alloced = 0; | |
4206 | struct dynreg **drpp, *dr; | |
4207 | int ch, base_reg = 0; | |
4208 | char *name, *start; | |
4209 | size_t len; | |
4210 | ||
4211 | switch (type) | |
4212 | { | |
4213 | case DYNREG_GR: base_reg = REG_GR + 32; break; | |
4214 | case DYNREG_FR: base_reg = REG_FR + 32; break; | |
4215 | case DYNREG_PR: base_reg = REG_P + 16; break; | |
4216 | default: break; | |
4217 | } | |
4218 | ||
542d6675 | 4219 | /* First, remove existing names from hash table. */ |
800eeca4 JW |
4220 | for (dr = md.dynreg[type]; dr && dr->num_regs; dr = dr->next) |
4221 | { | |
4222 | hash_delete (md.dynreg_hash, dr->name); | |
4223 | dr->num_regs = 0; | |
4224 | } | |
4225 | ||
4226 | drpp = &md.dynreg[type]; | |
4227 | while (1) | |
4228 | { | |
4229 | start = input_line_pointer; | |
4230 | ch = get_symbol_end (); | |
4231 | *input_line_pointer = ch; | |
4232 | len = (input_line_pointer - start); | |
4233 | ||
4234 | SKIP_WHITESPACE (); | |
4235 | if (*input_line_pointer != '[') | |
4236 | { | |
4237 | as_bad ("Expected '['"); | |
4238 | goto err; | |
4239 | } | |
4240 | ++input_line_pointer; /* skip '[' */ | |
4241 | ||
4242 | num_regs = get_absolute_expression (); | |
4243 | ||
4244 | if (*input_line_pointer++ != ']') | |
4245 | { | |
4246 | as_bad ("Expected ']'"); | |
4247 | goto err; | |
4248 | } | |
4249 | SKIP_WHITESPACE (); | |
4250 | ||
4251 | num_alloced += num_regs; | |
4252 | switch (type) | |
4253 | { | |
4254 | case DYNREG_GR: | |
4255 | if (num_alloced > md.rot.num_regs) | |
4256 | { | |
4257 | as_bad ("Used more than the declared %d rotating registers", | |
4258 | md.rot.num_regs); | |
4259 | goto err; | |
4260 | } | |
4261 | break; | |
4262 | case DYNREG_FR: | |
4263 | if (num_alloced > 96) | |
4264 | { | |
4265 | as_bad ("Used more than the available 96 rotating registers"); | |
4266 | goto err; | |
4267 | } | |
4268 | break; | |
4269 | case DYNREG_PR: | |
4270 | if (num_alloced > 48) | |
4271 | { | |
4272 | as_bad ("Used more than the available 48 rotating registers"); | |
4273 | goto err; | |
4274 | } | |
4275 | break; | |
4276 | ||
4277 | default: | |
4278 | break; | |
4279 | } | |
4280 | ||
4281 | name = obstack_alloc (¬es, len + 1); | |
4282 | memcpy (name, start, len); | |
4283 | name[len] = '\0'; | |
4284 | ||
4285 | if (!*drpp) | |
4286 | { | |
4287 | *drpp = obstack_alloc (¬es, sizeof (*dr)); | |
4288 | memset (*drpp, 0, sizeof (*dr)); | |
4289 | } | |
4290 | ||
4291 | dr = *drpp; | |
4292 | dr->name = name; | |
4293 | dr->num_regs = num_regs; | |
4294 | dr->base = base_reg; | |
4295 | drpp = &dr->next; | |
4296 | base_reg += num_regs; | |
4297 | ||
4298 | if (hash_insert (md.dynreg_hash, name, dr)) | |
4299 | { | |
4300 | as_bad ("Attempt to redefine register set `%s'", name); | |
4301 | goto err; | |
4302 | } | |
4303 | ||
4304 | if (*input_line_pointer != ',') | |
4305 | break; | |
4306 | ++input_line_pointer; /* skip comma */ | |
4307 | SKIP_WHITESPACE (); | |
4308 | } | |
4309 | demand_empty_rest_of_line (); | |
4310 | return; | |
4311 | ||
4312 | err: | |
4313 | ignore_rest_of_line (); | |
4314 | } | |
4315 | ||
4316 | static void | |
4317 | dot_byteorder (byteorder) | |
4318 | int byteorder; | |
4319 | { | |
10a98291 L |
4320 | segment_info_type *seginfo = seg_info (now_seg); |
4321 | ||
4322 | if (byteorder == -1) | |
4323 | { | |
4324 | if (seginfo->tc_segment_info_data.endian == 0) | |
4325 | seginfo->tc_segment_info_data.endian | |
4326 | = TARGET_BYTES_BIG_ENDIAN ? 1 : 2; | |
4327 | byteorder = seginfo->tc_segment_info_data.endian == 1; | |
4328 | } | |
4329 | else | |
4330 | seginfo->tc_segment_info_data.endian = byteorder ? 1 : 2; | |
4331 | ||
4332 | if (target_big_endian != byteorder) | |
4333 | { | |
4334 | target_big_endian = byteorder; | |
4335 | if (target_big_endian) | |
4336 | { | |
4337 | ia64_number_to_chars = number_to_chars_bigendian; | |
4338 | ia64_float_to_chars = ia64_float_to_chars_bigendian; | |
4339 | } | |
4340 | else | |
4341 | { | |
4342 | ia64_number_to_chars = number_to_chars_littleendian; | |
4343 | ia64_float_to_chars = ia64_float_to_chars_littleendian; | |
4344 | } | |
4345 | } | |
800eeca4 JW |
4346 | } |
4347 | ||
4348 | static void | |
4349 | dot_psr (dummy) | |
2434f565 | 4350 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4351 | { |
4352 | char *option; | |
4353 | int ch; | |
4354 | ||
4355 | while (1) | |
4356 | { | |
4357 | option = input_line_pointer; | |
4358 | ch = get_symbol_end (); | |
4359 | if (strcmp (option, "lsb") == 0) | |
4360 | md.flags &= ~EF_IA_64_BE; | |
4361 | else if (strcmp (option, "msb") == 0) | |
4362 | md.flags |= EF_IA_64_BE; | |
4363 | else if (strcmp (option, "abi32") == 0) | |
4364 | md.flags &= ~EF_IA_64_ABI64; | |
4365 | else if (strcmp (option, "abi64") == 0) | |
4366 | md.flags |= EF_IA_64_ABI64; | |
4367 | else | |
4368 | as_bad ("Unknown psr option `%s'", option); | |
4369 | *input_line_pointer = ch; | |
4370 | ||
4371 | SKIP_WHITESPACE (); | |
4372 | if (*input_line_pointer != ',') | |
4373 | break; | |
4374 | ||
4375 | ++input_line_pointer; | |
4376 | SKIP_WHITESPACE (); | |
4377 | } | |
4378 | demand_empty_rest_of_line (); | |
4379 | } | |
4380 | ||
4381 | static void | |
4382 | dot_alias (dummy) | |
2434f565 | 4383 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4384 | { |
4385 | as_bad (".alias not implemented yet"); | |
4386 | } | |
4387 | ||
4388 | static void | |
4389 | dot_ln (dummy) | |
2434f565 | 4390 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4391 | { |
4392 | new_logical_line (0, get_absolute_expression ()); | |
4393 | demand_empty_rest_of_line (); | |
4394 | } | |
4395 | ||
542d6675 | 4396 | static char * |
800eeca4 JW |
4397 | parse_section_name () |
4398 | { | |
4399 | char *name; | |
4400 | int len; | |
4401 | ||
4402 | SKIP_WHITESPACE (); | |
4403 | if (*input_line_pointer != '"') | |
4404 | { | |
4405 | as_bad ("Missing section name"); | |
4406 | ignore_rest_of_line (); | |
4407 | return 0; | |
4408 | } | |
4409 | name = demand_copy_C_string (&len); | |
4410 | if (!name) | |
4411 | { | |
4412 | ignore_rest_of_line (); | |
4413 | return 0; | |
4414 | } | |
4415 | SKIP_WHITESPACE (); | |
4416 | if (*input_line_pointer != ',') | |
4417 | { | |
4418 | as_bad ("Comma expected after section name"); | |
4419 | ignore_rest_of_line (); | |
4420 | return 0; | |
4421 | } | |
4422 | ++input_line_pointer; /* skip comma */ | |
4423 | return name; | |
4424 | } | |
4425 | ||
4426 | static void | |
4427 | dot_xdata (size) | |
4428 | int size; | |
4429 | { | |
4430 | char *name = parse_section_name (); | |
4431 | if (!name) | |
4432 | return; | |
4433 | ||
4d5a53ff | 4434 | md.keep_pending_output = 1; |
800eeca4 JW |
4435 | set_section (name); |
4436 | cons (size); | |
4437 | obj_elf_previous (0); | |
4d5a53ff | 4438 | md.keep_pending_output = 0; |
800eeca4 JW |
4439 | } |
4440 | ||
4441 | /* Why doesn't float_cons() call md_cons_align() the way cons() does? */ | |
542d6675 | 4442 | |
800eeca4 JW |
4443 | static void |
4444 | stmt_float_cons (kind) | |
4445 | int kind; | |
4446 | { | |
165a7f90 | 4447 | size_t alignment; |
800eeca4 JW |
4448 | |
4449 | switch (kind) | |
4450 | { | |
165a7f90 L |
4451 | case 'd': |
4452 | alignment = 8; | |
4453 | break; | |
4454 | ||
4455 | case 'x': | |
4456 | case 'X': | |
4457 | alignment = 16; | |
4458 | break; | |
800eeca4 JW |
4459 | |
4460 | case 'f': | |
4461 | default: | |
165a7f90 | 4462 | alignment = 4; |
800eeca4 JW |
4463 | break; |
4464 | } | |
165a7f90 | 4465 | ia64_do_align (alignment); |
800eeca4 JW |
4466 | float_cons (kind); |
4467 | } | |
4468 | ||
4469 | static void | |
4470 | stmt_cons_ua (size) | |
4471 | int size; | |
4472 | { | |
4473 | int saved_auto_align = md.auto_align; | |
4474 | ||
4475 | md.auto_align = 0; | |
4476 | cons (size); | |
4477 | md.auto_align = saved_auto_align; | |
4478 | } | |
4479 | ||
4480 | static void | |
4481 | dot_xfloat_cons (kind) | |
4482 | int kind; | |
4483 | { | |
4484 | char *name = parse_section_name (); | |
4485 | if (!name) | |
4486 | return; | |
4487 | ||
4d5a53ff | 4488 | md.keep_pending_output = 1; |
800eeca4 JW |
4489 | set_section (name); |
4490 | stmt_float_cons (kind); | |
4491 | obj_elf_previous (0); | |
4d5a53ff | 4492 | md.keep_pending_output = 0; |
800eeca4 JW |
4493 | } |
4494 | ||
4495 | static void | |
4496 | dot_xstringer (zero) | |
4497 | int zero; | |
4498 | { | |
4499 | char *name = parse_section_name (); | |
4500 | if (!name) | |
4501 | return; | |
4502 | ||
4d5a53ff | 4503 | md.keep_pending_output = 1; |
800eeca4 JW |
4504 | set_section (name); |
4505 | stringer (zero); | |
4506 | obj_elf_previous (0); | |
4d5a53ff | 4507 | md.keep_pending_output = 0; |
800eeca4 JW |
4508 | } |
4509 | ||
4510 | static void | |
4511 | dot_xdata_ua (size) | |
4512 | int size; | |
4513 | { | |
4514 | int saved_auto_align = md.auto_align; | |
4515 | char *name = parse_section_name (); | |
4516 | if (!name) | |
4517 | return; | |
4518 | ||
4d5a53ff | 4519 | md.keep_pending_output = 1; |
800eeca4 JW |
4520 | set_section (name); |
4521 | md.auto_align = 0; | |
4522 | cons (size); | |
4523 | md.auto_align = saved_auto_align; | |
4524 | obj_elf_previous (0); | |
4d5a53ff | 4525 | md.keep_pending_output = 0; |
800eeca4 JW |
4526 | } |
4527 | ||
4528 | static void | |
4529 | dot_xfloat_cons_ua (kind) | |
4530 | int kind; | |
4531 | { | |
4532 | int saved_auto_align = md.auto_align; | |
4533 | char *name = parse_section_name (); | |
4534 | if (!name) | |
4535 | return; | |
4536 | ||
4d5a53ff | 4537 | md.keep_pending_output = 1; |
800eeca4 JW |
4538 | set_section (name); |
4539 | md.auto_align = 0; | |
4540 | stmt_float_cons (kind); | |
4541 | md.auto_align = saved_auto_align; | |
4542 | obj_elf_previous (0); | |
4d5a53ff | 4543 | md.keep_pending_output = 0; |
800eeca4 JW |
4544 | } |
4545 | ||
4546 | /* .reg.val <regname>,value */ | |
542d6675 | 4547 | |
800eeca4 JW |
4548 | static void |
4549 | dot_reg_val (dummy) | |
2434f565 | 4550 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4551 | { |
4552 | expressionS reg; | |
4553 | ||
4554 | expression (®); | |
4555 | if (reg.X_op != O_register) | |
4556 | { | |
4557 | as_bad (_("Register name expected")); | |
4558 | ignore_rest_of_line (); | |
4559 | } | |
4560 | else if (*input_line_pointer++ != ',') | |
4561 | { | |
4562 | as_bad (_("Comma expected")); | |
4563 | ignore_rest_of_line (); | |
4564 | } | |
197865e8 | 4565 | else |
800eeca4 JW |
4566 | { |
4567 | valueT value = get_absolute_expression (); | |
4568 | int regno = reg.X_add_number; | |
542d6675 KH |
4569 | if (regno < REG_GR || regno > REG_GR + 128) |
4570 | as_warn (_("Register value annotation ignored")); | |
800eeca4 | 4571 | else |
542d6675 KH |
4572 | { |
4573 | gr_values[regno - REG_GR].known = 1; | |
4574 | gr_values[regno - REG_GR].value = value; | |
4575 | gr_values[regno - REG_GR].path = md.path; | |
4576 | } | |
800eeca4 JW |
4577 | } |
4578 | demand_empty_rest_of_line (); | |
4579 | } | |
4580 | ||
197865e8 | 4581 | /* select dv checking mode |
800eeca4 JW |
4582 | .auto |
4583 | .explicit | |
4584 | .default | |
4585 | ||
197865e8 | 4586 | A stop is inserted when changing modes |
800eeca4 | 4587 | */ |
542d6675 | 4588 | |
800eeca4 JW |
4589 | static void |
4590 | dot_dv_mode (type) | |
542d6675 | 4591 | int type; |
800eeca4 JW |
4592 | { |
4593 | if (md.manual_bundling) | |
4594 | as_warn (_("Directive invalid within a bundle")); | |
4595 | ||
4596 | if (type == 'E' || type == 'A') | |
4597 | md.mode_explicitly_set = 0; | |
4598 | else | |
4599 | md.mode_explicitly_set = 1; | |
4600 | ||
4601 | md.detect_dv = 1; | |
4602 | switch (type) | |
4603 | { | |
4604 | case 'A': | |
4605 | case 'a': | |
4606 | if (md.explicit_mode) | |
542d6675 | 4607 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4608 | md.explicit_mode = 0; |
4609 | break; | |
4610 | case 'E': | |
4611 | case 'e': | |
4612 | if (!md.explicit_mode) | |
542d6675 | 4613 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4614 | md.explicit_mode = 1; |
4615 | break; | |
4616 | default: | |
4617 | case 'd': | |
4618 | if (md.explicit_mode != md.default_explicit_mode) | |
542d6675 | 4619 | insn_group_break (1, 0, 0); |
800eeca4 JW |
4620 | md.explicit_mode = md.default_explicit_mode; |
4621 | md.mode_explicitly_set = 0; | |
4622 | break; | |
4623 | } | |
4624 | } | |
4625 | ||
4626 | static void | |
4627 | print_prmask (mask) | |
542d6675 | 4628 | valueT mask; |
800eeca4 JW |
4629 | { |
4630 | int regno; | |
4631 | char *comma = ""; | |
542d6675 | 4632 | for (regno = 0; regno < 64; regno++) |
800eeca4 | 4633 | { |
542d6675 KH |
4634 | if (mask & ((valueT) 1 << regno)) |
4635 | { | |
4636 | fprintf (stderr, "%s p%d", comma, regno); | |
4637 | comma = ","; | |
4638 | } | |
800eeca4 JW |
4639 | } |
4640 | } | |
4641 | ||
4642 | /* | |
4643 | .pred.rel.clear [p1 [,p2 [,...]]] (also .pred.rel "clear") | |
4644 | .pred.rel.imply p1, p2 (also .pred.rel "imply") | |
4645 | .pred.rel.mutex p1, p2 [,...] (also .pred.rel "mutex") | |
4646 | .pred.safe_across_calls p1 [, p2 [,...]] | |
4647 | */ | |
542d6675 | 4648 | |
800eeca4 JW |
4649 | static void |
4650 | dot_pred_rel (type) | |
542d6675 | 4651 | int type; |
800eeca4 JW |
4652 | { |
4653 | valueT mask = 0; | |
4654 | int count = 0; | |
4655 | int p1 = -1, p2 = -1; | |
4656 | ||
4657 | if (type == 0) | |
4658 | { | |
4659 | if (*input_line_pointer != '"') | |
542d6675 KH |
4660 | { |
4661 | as_bad (_("Missing predicate relation type")); | |
4662 | ignore_rest_of_line (); | |
4663 | return; | |
4664 | } | |
197865e8 | 4665 | else |
542d6675 KH |
4666 | { |
4667 | int len; | |
4668 | char *form = demand_copy_C_string (&len); | |
4669 | if (strcmp (form, "mutex") == 0) | |
4670 | type = 'm'; | |
4671 | else if (strcmp (form, "clear") == 0) | |
4672 | type = 'c'; | |
4673 | else if (strcmp (form, "imply") == 0) | |
4674 | type = 'i'; | |
4675 | else | |
4676 | { | |
4677 | as_bad (_("Unrecognized predicate relation type")); | |
4678 | ignore_rest_of_line (); | |
4679 | return; | |
4680 | } | |
4681 | } | |
800eeca4 | 4682 | if (*input_line_pointer == ',') |
542d6675 | 4683 | ++input_line_pointer; |
800eeca4 JW |
4684 | SKIP_WHITESPACE (); |
4685 | } | |
4686 | ||
4687 | SKIP_WHITESPACE (); | |
4688 | while (1) | |
4689 | { | |
4690 | valueT bit = 1; | |
4691 | int regno; | |
197865e8 | 4692 | |
3882b010 | 4693 | if (TOUPPER (*input_line_pointer) != 'P' |
542d6675 KH |
4694 | || (regno = atoi (++input_line_pointer)) < 0 |
4695 | || regno > 63) | |
4696 | { | |
4697 | as_bad (_("Predicate register expected")); | |
4698 | ignore_rest_of_line (); | |
4699 | return; | |
4700 | } | |
3882b010 | 4701 | while (ISDIGIT (*input_line_pointer)) |
542d6675 | 4702 | ++input_line_pointer; |
800eeca4 | 4703 | if (p1 == -1) |
542d6675 | 4704 | p1 = regno; |
800eeca4 | 4705 | else if (p2 == -1) |
542d6675 | 4706 | p2 = regno; |
800eeca4 JW |
4707 | bit <<= regno; |
4708 | if (mask & bit) | |
542d6675 KH |
4709 | as_warn (_("Duplicate predicate register ignored")); |
4710 | mask |= bit; | |
4711 | count++; | |
4712 | /* See if it's a range. */ | |
800eeca4 | 4713 | if (*input_line_pointer == '-') |
542d6675 KH |
4714 | { |
4715 | valueT stop = 1; | |
4716 | ++input_line_pointer; | |
4717 | ||
3882b010 | 4718 | if (TOUPPER (*input_line_pointer) != 'P' |
542d6675 KH |
4719 | || (regno = atoi (++input_line_pointer)) < 0 |
4720 | || regno > 63) | |
4721 | { | |
4722 | as_bad (_("Predicate register expected")); | |
4723 | ignore_rest_of_line (); | |
4724 | return; | |
4725 | } | |
3882b010 | 4726 | while (ISDIGIT (*input_line_pointer)) |
542d6675 KH |
4727 | ++input_line_pointer; |
4728 | stop <<= regno; | |
4729 | if (bit >= stop) | |
4730 | { | |
4731 | as_bad (_("Bad register range")); | |
4732 | ignore_rest_of_line (); | |
4733 | return; | |
4734 | } | |
4735 | while (bit < stop) | |
4736 | { | |
4737 | bit <<= 1; | |
4738 | mask |= bit; | |
4739 | count++; | |
4740 | } | |
4741 | SKIP_WHITESPACE (); | |
4742 | } | |
800eeca4 | 4743 | if (*input_line_pointer != ',') |
542d6675 | 4744 | break; |
800eeca4 JW |
4745 | ++input_line_pointer; |
4746 | SKIP_WHITESPACE (); | |
4747 | } | |
4748 | ||
4749 | switch (type) | |
4750 | { | |
4751 | case 'c': | |
4752 | if (count == 0) | |
542d6675 | 4753 | mask = ~(valueT) 0; |
800eeca4 | 4754 | clear_qp_mutex (mask); |
197865e8 | 4755 | clear_qp_implies (mask, (valueT) 0); |
800eeca4 JW |
4756 | break; |
4757 | case 'i': | |
4758 | if (count != 2 || p1 == -1 || p2 == -1) | |
542d6675 | 4759 | as_bad (_("Predicate source and target required")); |
800eeca4 | 4760 | else if (p1 == 0 || p2 == 0) |
542d6675 | 4761 | as_bad (_("Use of p0 is not valid in this context")); |
800eeca4 | 4762 | else |
542d6675 | 4763 | add_qp_imply (p1, p2); |
800eeca4 JW |
4764 | break; |
4765 | case 'm': | |
4766 | if (count < 2) | |
542d6675 KH |
4767 | { |
4768 | as_bad (_("At least two PR arguments expected")); | |
4769 | break; | |
4770 | } | |
800eeca4 | 4771 | else if (mask & 1) |
542d6675 KH |
4772 | { |
4773 | as_bad (_("Use of p0 is not valid in this context")); | |
4774 | break; | |
4775 | } | |
800eeca4 JW |
4776 | add_qp_mutex (mask); |
4777 | break; | |
4778 | case 's': | |
4779 | /* note that we don't override any existing relations */ | |
4780 | if (count == 0) | |
542d6675 KH |
4781 | { |
4782 | as_bad (_("At least one PR argument expected")); | |
4783 | break; | |
4784 | } | |
800eeca4 | 4785 | if (md.debug_dv) |
542d6675 KH |
4786 | { |
4787 | fprintf (stderr, "Safe across calls: "); | |
4788 | print_prmask (mask); | |
4789 | fprintf (stderr, "\n"); | |
4790 | } | |
800eeca4 JW |
4791 | qp_safe_across_calls = mask; |
4792 | break; | |
4793 | } | |
4794 | demand_empty_rest_of_line (); | |
4795 | } | |
4796 | ||
4797 | /* .entry label [, label [, ...]] | |
4798 | Hint to DV code that the given labels are to be considered entry points. | |
542d6675 KH |
4799 | Otherwise, only global labels are considered entry points. */ |
4800 | ||
800eeca4 JW |
4801 | static void |
4802 | dot_entry (dummy) | |
2434f565 | 4803 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4804 | { |
4805 | const char *err; | |
4806 | char *name; | |
4807 | int c; | |
4808 | symbolS *symbolP; | |
4809 | ||
4810 | do | |
4811 | { | |
4812 | name = input_line_pointer; | |
4813 | c = get_symbol_end (); | |
4814 | symbolP = symbol_find_or_make (name); | |
4815 | ||
4816 | err = hash_insert (md.entry_hash, S_GET_NAME (symbolP), (PTR) symbolP); | |
4817 | if (err) | |
542d6675 KH |
4818 | as_fatal (_("Inserting \"%s\" into entry hint table failed: %s"), |
4819 | name, err); | |
800eeca4 JW |
4820 | |
4821 | *input_line_pointer = c; | |
4822 | SKIP_WHITESPACE (); | |
4823 | c = *input_line_pointer; | |
4824 | if (c == ',') | |
4825 | { | |
4826 | input_line_pointer++; | |
4827 | SKIP_WHITESPACE (); | |
4828 | if (*input_line_pointer == '\n') | |
4829 | c = '\n'; | |
4830 | } | |
4831 | } | |
4832 | while (c == ','); | |
4833 | ||
4834 | demand_empty_rest_of_line (); | |
4835 | } | |
4836 | ||
197865e8 | 4837 | /* .mem.offset offset, base |
542d6675 KH |
4838 | "base" is used to distinguish between offsets from a different base. */ |
4839 | ||
800eeca4 JW |
4840 | static void |
4841 | dot_mem_offset (dummy) | |
2434f565 | 4842 | int dummy ATTRIBUTE_UNUSED; |
800eeca4 JW |
4843 | { |
4844 | md.mem_offset.hint = 1; | |
4845 | md.mem_offset.offset = get_absolute_expression (); | |
4846 | if (*input_line_pointer != ',') | |
4847 | { | |
4848 | as_bad (_("Comma expected")); | |
4849 | ignore_rest_of_line (); | |
4850 | return; | |
4851 | } | |
4852 | ++input_line_pointer; | |
4853 | md.mem_offset.base = get_absolute_expression (); | |
4854 | demand_empty_rest_of_line (); | |
4855 | } | |
4856 | ||
542d6675 | 4857 | /* ia64-specific pseudo-ops: */ |
800eeca4 JW |
4858 | const pseudo_typeS md_pseudo_table[] = |
4859 | { | |
4860 | { "radix", dot_radix, 0 }, | |
4861 | { "lcomm", s_lcomm_bytes, 1 }, | |
4862 | { "bss", dot_special_section, SPECIAL_SECTION_BSS }, | |
4863 | { "sbss", dot_special_section, SPECIAL_SECTION_SBSS }, | |
4864 | { "sdata", dot_special_section, SPECIAL_SECTION_SDATA }, | |
4865 | { "rodata", dot_special_section, SPECIAL_SECTION_RODATA }, | |
4866 | { "comment", dot_special_section, SPECIAL_SECTION_COMMENT }, | |
4867 | { "ia_64.unwind", dot_special_section, SPECIAL_SECTION_UNWIND }, | |
4868 | { "ia_64.unwind_info", dot_special_section, SPECIAL_SECTION_UNWIND_INFO }, | |
557debba JW |
4869 | { "init_array", dot_special_section, SPECIAL_SECTION_INIT_ARRAY }, |
4870 | { "fini_array", dot_special_section, SPECIAL_SECTION_FINI_ARRAY }, | |
800eeca4 JW |
4871 | { "proc", dot_proc, 0 }, |
4872 | { "body", dot_body, 0 }, | |
4873 | { "prologue", dot_prologue, 0 }, | |
2434f565 | 4874 | { "endp", dot_endp, 0 }, |
9f1838ed | 4875 | { "file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0 }, |
2434f565 JW |
4876 | { "loc", dwarf2_directive_loc, 0 }, |
4877 | ||
4878 | { "fframe", dot_fframe, 0 }, | |
4879 | { "vframe", dot_vframe, 0 }, | |
4880 | { "vframesp", dot_vframesp, 0 }, | |
4881 | { "vframepsp", dot_vframepsp, 0 }, | |
4882 | { "save", dot_save, 0 }, | |
4883 | { "restore", dot_restore, 0 }, | |
4884 | { "restorereg", dot_restorereg, 0 }, | |
4885 | { "restorereg.p", dot_restorereg_p, 0 }, | |
4886 | { "handlerdata", dot_handlerdata, 0 }, | |
4887 | { "unwentry", dot_unwentry, 0 }, | |
4888 | { "altrp", dot_altrp, 0 }, | |
e0c9811a JW |
4889 | { "savesp", dot_savemem, 0 }, |
4890 | { "savepsp", dot_savemem, 1 }, | |
2434f565 JW |
4891 | { "save.g", dot_saveg, 0 }, |
4892 | { "save.f", dot_savef, 0 }, | |
4893 | { "save.b", dot_saveb, 0 }, | |
4894 | { "save.gf", dot_savegf, 0 }, | |
4895 | { "spill", dot_spill, 0 }, | |
4896 | { "spillreg", dot_spillreg, 0 }, | |
e0c9811a JW |
4897 | { "spillsp", dot_spillmem, 0 }, |
4898 | { "spillpsp", dot_spillmem, 1 }, | |
2434f565 | 4899 | { "spillreg.p", dot_spillreg_p, 0 }, |
e0c9811a JW |
4900 | { "spillsp.p", dot_spillmem_p, 0 }, |
4901 | { "spillpsp.p", dot_spillmem_p, 1 }, | |
2434f565 JW |
4902 | { "label_state", dot_label_state, 0 }, |
4903 | { "copy_state", dot_copy_state, 0 }, | |
4904 | { "unwabi", dot_unwabi, 0 }, | |
4905 | { "personality", dot_personality, 0 }, | |
800eeca4 | 4906 | #if 0 |
2434f565 | 4907 | { "estate", dot_estate, 0 }, |
800eeca4 JW |
4908 | #endif |
4909 | { "mii", dot_template, 0x0 }, | |
4910 | { "mli", dot_template, 0x2 }, /* old format, for compatibility */ | |
4911 | { "mlx", dot_template, 0x2 }, | |
4912 | { "mmi", dot_template, 0x4 }, | |
4913 | { "mfi", dot_template, 0x6 }, | |
4914 | { "mmf", dot_template, 0x7 }, | |
4915 | { "mib", dot_template, 0x8 }, | |
4916 | { "mbb", dot_template, 0x9 }, | |
4917 | { "bbb", dot_template, 0xb }, | |
4918 | { "mmb", dot_template, 0xc }, | |
4919 | { "mfb", dot_template, 0xe }, | |
4920 | #if 0 | |
4921 | { "lb", dot_scope, 0 }, | |
4922 | { "le", dot_scope, 1 }, | |
4923 | #endif | |
4924 | { "align", s_align_bytes, 0 }, | |
4925 | { "regstk", dot_regstk, 0 }, | |
4926 | { "rotr", dot_rot, DYNREG_GR }, | |
4927 | { "rotf", dot_rot, DYNREG_FR }, | |
4928 | { "rotp", dot_rot, DYNREG_PR }, | |
4929 | { "lsb", dot_byteorder, 0 }, | |
4930 | { "msb", dot_byteorder, 1 }, | |
4931 | { "psr", dot_psr, 0 }, | |
4932 | { "alias", dot_alias, 0 }, | |
4933 | { "ln", dot_ln, 0 }, /* source line info (for debugging) */ | |
4934 | ||
4935 | { "xdata1", dot_xdata, 1 }, | |
4936 | { "xdata2", dot_xdata, 2 }, | |
4937 | { "xdata4", dot_xdata, 4 }, | |
4938 | { "xdata8", dot_xdata, 8 }, | |
4939 | { "xreal4", dot_xfloat_cons, 'f' }, | |
4940 | { "xreal8", dot_xfloat_cons, 'd' }, | |
4941 | { "xreal10", dot_xfloat_cons, 'x' }, | |
165a7f90 | 4942 | { "xreal16", dot_xfloat_cons, 'X' }, |
800eeca4 JW |
4943 | { "xstring", dot_xstringer, 0 }, |
4944 | { "xstringz", dot_xstringer, 1 }, | |
4945 | ||
542d6675 | 4946 | /* unaligned versions: */ |
800eeca4 JW |
4947 | { "xdata2.ua", dot_xdata_ua, 2 }, |
4948 | { "xdata4.ua", dot_xdata_ua, 4 }, | |
4949 | { "xdata8.ua", dot_xdata_ua, 8 }, | |
4950 | { "xreal4.ua", dot_xfloat_cons_ua, 'f' }, | |
4951 | { "xreal8.ua", dot_xfloat_cons_ua, 'd' }, | |
4952 | { "xreal10.ua", dot_xfloat_cons_ua, 'x' }, | |
165a7f90 | 4953 | { "xreal16.ua", dot_xfloat_cons_ua, 'X' }, |
800eeca4 JW |
4954 | |
4955 | /* annotations/DV checking support */ | |
4956 | { "entry", dot_entry, 0 }, | |
2434f565 | 4957 | { "mem.offset", dot_mem_offset, 0 }, |
800eeca4 JW |
4958 | { "pred.rel", dot_pred_rel, 0 }, |
4959 | { "pred.rel.clear", dot_pred_rel, 'c' }, | |
4960 | { "pred.rel.imply", dot_pred_rel, 'i' }, | |
4961 | { "pred.rel.mutex", dot_pred_rel, 'm' }, | |
4962 | { "pred.safe_across_calls", dot_pred_rel, 's' }, | |
2434f565 | 4963 | { "reg.val", dot_reg_val, 0 }, |
800eeca4 JW |
4964 | { "auto", dot_dv_mode, 'a' }, |
4965 | { "explicit", dot_dv_mode, 'e' }, | |
4966 | { "default", dot_dv_mode, 'd' }, | |
4967 | ||
87885043 JW |
4968 | /* ??? These are needed to make gas/testsuite/gas/elf/ehopt.s work. |
4969 | IA-64 aligns data allocation pseudo-ops by default, so we have to | |
4970 | tell it that these ones are supposed to be unaligned. Long term, | |
4971 | should rewrite so that only IA-64 specific data allocation pseudo-ops | |
4972 | are aligned by default. */ | |
4973 | {"2byte", stmt_cons_ua, 2}, | |
4974 | {"4byte", stmt_cons_ua, 4}, | |
4975 | {"8byte", stmt_cons_ua, 8}, | |
4976 | ||
800eeca4 JW |
4977 | { NULL, 0, 0 } |
4978 | }; | |
4979 | ||
4980 | static const struct pseudo_opcode | |
4981 | { | |
4982 | const char *name; | |
4983 | void (*handler) (int); | |
4984 | int arg; | |
4985 | } | |
4986 | pseudo_opcode[] = | |
4987 | { | |
4988 | /* these are more like pseudo-ops, but don't start with a dot */ | |
4989 | { "data1", cons, 1 }, | |
4990 | { "data2", cons, 2 }, | |
4991 | { "data4", cons, 4 }, | |
4992 | { "data8", cons, 8 }, | |
3969b680 | 4993 | { "data16", cons, 16 }, |
800eeca4 JW |
4994 | { "real4", stmt_float_cons, 'f' }, |
4995 | { "real8", stmt_float_cons, 'd' }, | |
4996 | { "real10", stmt_float_cons, 'x' }, | |
165a7f90 | 4997 | { "real16", stmt_float_cons, 'X' }, |
800eeca4 JW |
4998 | { "string", stringer, 0 }, |
4999 | { "stringz", stringer, 1 }, | |
5000 | ||
542d6675 | 5001 | /* unaligned versions: */ |
800eeca4 JW |
5002 | { "data2.ua", stmt_cons_ua, 2 }, |
5003 | { "data4.ua", stmt_cons_ua, 4 }, | |
5004 | { "data8.ua", stmt_cons_ua, 8 }, | |
3969b680 | 5005 | { "data16.ua", stmt_cons_ua, 16 }, |
800eeca4 JW |
5006 | { "real4.ua", float_cons, 'f' }, |
5007 | { "real8.ua", float_cons, 'd' }, | |
5008 | { "real10.ua", float_cons, 'x' }, | |
165a7f90 | 5009 | { "real16.ua", float_cons, 'X' }, |
800eeca4 JW |
5010 | }; |
5011 | ||
5012 | /* Declare a register by creating a symbol for it and entering it in | |
5013 | the symbol table. */ | |
542d6675 KH |
5014 | |
5015 | static symbolS * | |
800eeca4 JW |
5016 | declare_register (name, regnum) |
5017 | const char *name; | |
5018 | int regnum; | |
5019 | { | |
5020 | const char *err; | |
5021 | symbolS *sym; | |
5022 | ||
5023 | sym = symbol_new (name, reg_section, regnum, &zero_address_frag); | |
5024 | ||
5025 | err = hash_insert (md.reg_hash, S_GET_NAME (sym), (PTR) sym); | |
5026 | if (err) | |
5027 | as_fatal ("Inserting \"%s\" into register table failed: %s", | |
5028 | name, err); | |
5029 | ||
5030 | return sym; | |
5031 | } | |
5032 | ||
5033 | static void | |
5034 | declare_register_set (prefix, num_regs, base_regnum) | |
5035 | const char *prefix; | |
5036 | int num_regs; | |
5037 | int base_regnum; | |
5038 | { | |
5039 | char name[8]; | |
5040 | int i; | |
5041 | ||
5042 | for (i = 0; i < num_regs; ++i) | |
5043 | { | |
5044 | sprintf (name, "%s%u", prefix, i); | |
5045 | declare_register (name, base_regnum + i); | |
5046 | } | |
5047 | } | |
5048 | ||
5049 | static unsigned int | |
5050 | operand_width (opnd) | |
5051 | enum ia64_opnd opnd; | |
5052 | { | |
5053 | const struct ia64_operand *odesc = &elf64_ia64_operands[opnd]; | |
5054 | unsigned int bits = 0; | |
5055 | int i; | |
5056 | ||
5057 | bits = 0; | |
5058 | for (i = 0; i < NELEMS (odesc->field) && odesc->field[i].bits; ++i) | |
5059 | bits += odesc->field[i].bits; | |
5060 | ||
5061 | return bits; | |
5062 | } | |
5063 | ||
87f8eb97 | 5064 | static enum operand_match_result |
800eeca4 JW |
5065 | operand_match (idesc, index, e) |
5066 | const struct ia64_opcode *idesc; | |
5067 | int index; | |
5068 | expressionS *e; | |
5069 | { | |
5070 | enum ia64_opnd opnd = idesc->operands[index]; | |
5071 | int bits, relocatable = 0; | |
5072 | struct insn_fix *fix; | |
5073 | bfd_signed_vma val; | |
5074 | ||
5075 | switch (opnd) | |
5076 | { | |
542d6675 | 5077 | /* constants: */ |
800eeca4 JW |
5078 | |
5079 | case IA64_OPND_AR_CCV: | |
5080 | if (e->X_op == O_register && e->X_add_number == REG_AR + 32) | |
87f8eb97 | 5081 | return OPERAND_MATCH; |
800eeca4 JW |
5082 | break; |
5083 | ||
c10d9d8f JW |
5084 | case IA64_OPND_AR_CSD: |
5085 | if (e->X_op == O_register && e->X_add_number == REG_AR + 25) | |
5086 | return OPERAND_MATCH; | |
5087 | break; | |
5088 | ||
800eeca4 JW |
5089 | case IA64_OPND_AR_PFS: |
5090 | if (e->X_op == O_register && e->X_add_number == REG_AR + 64) | |
87f8eb97 | 5091 | return OPERAND_MATCH; |
800eeca4 JW |
5092 | break; |
5093 | ||
5094 | case IA64_OPND_GR0: | |
5095 | if (e->X_op == O_register && e->X_add_number == REG_GR + 0) | |
87f8eb97 | 5096 | return OPERAND_MATCH; |
800eeca4 JW |
5097 | break; |
5098 | ||
5099 | case IA64_OPND_IP: | |
5100 | if (e->X_op == O_register && e->X_add_number == REG_IP) | |
87f8eb97 | 5101 | return OPERAND_MATCH; |
800eeca4 JW |
5102 | break; |
5103 | ||
5104 | case IA64_OPND_PR: | |
5105 | if (e->X_op == O_register && e->X_add_number == REG_PR) | |
87f8eb97 | 5106 | return OPERAND_MATCH; |
800eeca4 JW |
5107 | break; |
5108 | ||
5109 | case IA64_OPND_PR_ROT: | |
5110 | if (e->X_op == O_register && e->X_add_number == REG_PR_ROT) | |
87f8eb97 | 5111 | return OPERAND_MATCH; |
800eeca4 JW |
5112 | break; |
5113 | ||
5114 | case IA64_OPND_PSR: | |
5115 | if (e->X_op == O_register && e->X_add_number == REG_PSR) | |
87f8eb97 | 5116 | return OPERAND_MATCH; |
800eeca4 JW |
5117 | break; |
5118 | ||
5119 | case IA64_OPND_PSR_L: | |
5120 | if (e->X_op == O_register && e->X_add_number == REG_PSR_L) | |
87f8eb97 | 5121 | return OPERAND_MATCH; |
800eeca4 JW |
5122 | break; |
5123 | ||
5124 | case IA64_OPND_PSR_UM: | |
5125 | if (e->X_op == O_register && e->X_add_number == REG_PSR_UM) | |
87f8eb97 | 5126 | return OPERAND_MATCH; |
800eeca4 JW |
5127 | break; |
5128 | ||
5129 | case IA64_OPND_C1: | |
87f8eb97 JW |
5130 | if (e->X_op == O_constant) |
5131 | { | |
5132 | if (e->X_add_number == 1) | |
5133 | return OPERAND_MATCH; | |
5134 | else | |
5135 | return OPERAND_OUT_OF_RANGE; | |
5136 | } | |
800eeca4 JW |
5137 | break; |
5138 | ||
5139 | case IA64_OPND_C8: | |
87f8eb97 JW |
5140 | if (e->X_op == O_constant) |
5141 | { | |
5142 | if (e->X_add_number == 8) | |
5143 | return OPERAND_MATCH; | |
5144 | else | |
5145 | return OPERAND_OUT_OF_RANGE; | |
5146 | } | |
800eeca4 JW |
5147 | break; |
5148 | ||
5149 | case IA64_OPND_C16: | |
87f8eb97 JW |
5150 | if (e->X_op == O_constant) |
5151 | { | |
5152 | if (e->X_add_number == 16) | |
5153 | return OPERAND_MATCH; | |
5154 | else | |
5155 | return OPERAND_OUT_OF_RANGE; | |
5156 | } | |
800eeca4 JW |
5157 | break; |
5158 | ||
542d6675 | 5159 | /* register operands: */ |
800eeca4 JW |
5160 | |
5161 | case IA64_OPND_AR3: | |
5162 | if (e->X_op == O_register && e->X_add_number >= REG_AR | |
5163 | && e->X_add_number < REG_AR + 128) | |
87f8eb97 | 5164 | return OPERAND_MATCH; |
800eeca4 JW |
5165 | break; |
5166 | ||
5167 | case IA64_OPND_B1: | |
5168 | case IA64_OPND_B2: | |
5169 | if (e->X_op == O_register && e->X_add_number >= REG_BR | |
5170 | && e->X_add_number < REG_BR + 8) | |
87f8eb97 | 5171 | return OPERAND_MATCH; |
800eeca4 JW |
5172 | break; |
5173 | ||
5174 | case IA64_OPND_CR3: | |
5175 | if (e->X_op == O_register && e->X_add_number >= REG_CR | |
5176 | && e->X_add_number < REG_CR + 128) | |
87f8eb97 | 5177 | return OPERAND_MATCH; |
800eeca4 JW |
5178 | break; |
5179 | ||
5180 | case IA64_OPND_F1: | |
5181 | case IA64_OPND_F2: | |
5182 | case IA64_OPND_F3: | |
5183 | case IA64_OPND_F4: | |
5184 | if (e->X_op == O_register && e->X_add_number >= REG_FR | |
5185 | && e->X_add_number < REG_FR + 128) | |
87f8eb97 | 5186 | return OPERAND_MATCH; |
800eeca4 JW |
5187 | break; |
5188 | ||
5189 | case IA64_OPND_P1: | |
5190 | case IA64_OPND_P2: | |
5191 | if (e->X_op == O_register && e->X_add_number >= REG_P | |
5192 | && e->X_add_number < REG_P + 64) | |
87f8eb97 | 5193 | return OPERAND_MATCH; |
800eeca4 JW |
5194 | break; |
5195 | ||
5196 | case IA64_OPND_R1: | |
5197 | case IA64_OPND_R2: | |
5198 | case IA64_OPND_R3: | |
5199 | if (e->X_op == O_register && e->X_add_number >= REG_GR | |
5200 | && e->X_add_number < REG_GR + 128) | |
87f8eb97 | 5201 | return OPERAND_MATCH; |
800eeca4 JW |
5202 | break; |
5203 | ||
5204 | case IA64_OPND_R3_2: | |
87f8eb97 | 5205 | if (e->X_op == O_register && e->X_add_number >= REG_GR) |
40449e9f | 5206 | { |
87f8eb97 JW |
5207 | if (e->X_add_number < REG_GR + 4) |
5208 | return OPERAND_MATCH; | |
5209 | else if (e->X_add_number < REG_GR + 128) | |
5210 | return OPERAND_OUT_OF_RANGE; | |
5211 | } | |
800eeca4 JW |
5212 | break; |
5213 | ||
542d6675 | 5214 | /* indirect operands: */ |
800eeca4 JW |
5215 | case IA64_OPND_CPUID_R3: |
5216 | case IA64_OPND_DBR_R3: | |
5217 | case IA64_OPND_DTR_R3: | |
5218 | case IA64_OPND_ITR_R3: | |
5219 | case IA64_OPND_IBR_R3: | |
5220 | case IA64_OPND_MSR_R3: | |
5221 | case IA64_OPND_PKR_R3: | |
5222 | case IA64_OPND_PMC_R3: | |
5223 | case IA64_OPND_PMD_R3: | |
5224 | case IA64_OPND_RR_R3: | |
5225 | if (e->X_op == O_index && e->X_op_symbol | |
5226 | && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID | |
5227 | == opnd - IA64_OPND_CPUID_R3)) | |
87f8eb97 | 5228 | return OPERAND_MATCH; |
800eeca4 JW |
5229 | break; |
5230 | ||
5231 | case IA64_OPND_MR3: | |
5232 | if (e->X_op == O_index && !e->X_op_symbol) | |
87f8eb97 | 5233 | return OPERAND_MATCH; |
800eeca4 JW |
5234 | break; |
5235 | ||
542d6675 | 5236 | /* immediate operands: */ |
800eeca4 JW |
5237 | case IA64_OPND_CNT2a: |
5238 | case IA64_OPND_LEN4: | |
5239 | case IA64_OPND_LEN6: | |
5240 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 JW |
5241 | if (e->X_op == O_constant) |
5242 | { | |
5243 | if ((bfd_vma) (e->X_add_number - 1) < ((bfd_vma) 1 << bits)) | |
5244 | return OPERAND_MATCH; | |
5245 | else | |
5246 | return OPERAND_OUT_OF_RANGE; | |
5247 | } | |
800eeca4 JW |
5248 | break; |
5249 | ||
5250 | case IA64_OPND_CNT2b: | |
87f8eb97 JW |
5251 | if (e->X_op == O_constant) |
5252 | { | |
5253 | if ((bfd_vma) (e->X_add_number - 1) < 3) | |
5254 | return OPERAND_MATCH; | |
5255 | else | |
5256 | return OPERAND_OUT_OF_RANGE; | |
5257 | } | |
800eeca4 JW |
5258 | break; |
5259 | ||
5260 | case IA64_OPND_CNT2c: | |
5261 | val = e->X_add_number; | |
87f8eb97 JW |
5262 | if (e->X_op == O_constant) |
5263 | { | |
5264 | if ((val == 0 || val == 7 || val == 15 || val == 16)) | |
5265 | return OPERAND_MATCH; | |
5266 | else | |
5267 | return OPERAND_OUT_OF_RANGE; | |
5268 | } | |
800eeca4 JW |
5269 | break; |
5270 | ||
5271 | case IA64_OPND_SOR: | |
5272 | /* SOR must be an integer multiple of 8 */ | |
87f8eb97 JW |
5273 | if (e->X_op == O_constant && e->X_add_number & 0x7) |
5274 | return OPERAND_OUT_OF_RANGE; | |
800eeca4 JW |
5275 | case IA64_OPND_SOF: |
5276 | case IA64_OPND_SOL: | |
87f8eb97 JW |
5277 | if (e->X_op == O_constant) |
5278 | { | |
5279 | if ((bfd_vma) e->X_add_number <= 96) | |
5280 | return OPERAND_MATCH; | |
5281 | else | |
5282 | return OPERAND_OUT_OF_RANGE; | |
5283 | } | |
800eeca4 JW |
5284 | break; |
5285 | ||
5286 | case IA64_OPND_IMMU62: | |
5287 | if (e->X_op == O_constant) | |
542d6675 | 5288 | { |
800eeca4 | 5289 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << 62)) |
87f8eb97 JW |
5290 | return OPERAND_MATCH; |
5291 | else | |
5292 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5293 | } |
197865e8 | 5294 | else |
542d6675 KH |
5295 | { |
5296 | /* FIXME -- need 62-bit relocation type */ | |
5297 | as_bad (_("62-bit relocation not yet implemented")); | |
5298 | } | |
800eeca4 JW |
5299 | break; |
5300 | ||
5301 | case IA64_OPND_IMMU64: | |
5302 | if (e->X_op == O_symbol || e->X_op == O_pseudo_fixup | |
5303 | || e->X_op == O_subtract) | |
5304 | { | |
5305 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5306 | fix->code = BFD_RELOC_IA64_IMM64; | |
5307 | if (e->X_op != O_subtract) | |
5308 | { | |
5309 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
5310 | if (e->X_op == O_pseudo_fixup) | |
5311 | e->X_op = O_symbol; | |
5312 | } | |
5313 | ||
5314 | fix->opnd = idesc->operands[index]; | |
5315 | fix->expr = *e; | |
5316 | fix->is_pcrel = 0; | |
5317 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5318 | return OPERAND_MATCH; |
800eeca4 JW |
5319 | } |
5320 | else if (e->X_op == O_constant) | |
87f8eb97 | 5321 | return OPERAND_MATCH; |
800eeca4 JW |
5322 | break; |
5323 | ||
5324 | case IA64_OPND_CCNT5: | |
5325 | case IA64_OPND_CNT5: | |
5326 | case IA64_OPND_CNT6: | |
5327 | case IA64_OPND_CPOS6a: | |
5328 | case IA64_OPND_CPOS6b: | |
5329 | case IA64_OPND_CPOS6c: | |
5330 | case IA64_OPND_IMMU2: | |
5331 | case IA64_OPND_IMMU7a: | |
5332 | case IA64_OPND_IMMU7b: | |
800eeca4 JW |
5333 | case IA64_OPND_IMMU21: |
5334 | case IA64_OPND_IMMU24: | |
5335 | case IA64_OPND_MBTYPE4: | |
5336 | case IA64_OPND_MHTYPE8: | |
5337 | case IA64_OPND_POS6: | |
5338 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 JW |
5339 | if (e->X_op == O_constant) |
5340 | { | |
5341 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) | |
5342 | return OPERAND_MATCH; | |
5343 | else | |
5344 | return OPERAND_OUT_OF_RANGE; | |
5345 | } | |
800eeca4 JW |
5346 | break; |
5347 | ||
bf3ca999 TW |
5348 | case IA64_OPND_IMMU9: |
5349 | bits = operand_width (idesc->operands[index]); | |
87f8eb97 | 5350 | if (e->X_op == O_constant) |
542d6675 | 5351 | { |
87f8eb97 JW |
5352 | if ((bfd_vma) e->X_add_number < ((bfd_vma) 1 << bits)) |
5353 | { | |
5354 | int lobits = e->X_add_number & 0x3; | |
5355 | if (((bfd_vma) e->X_add_number & 0x3C) != 0 && lobits == 0) | |
5356 | e->X_add_number |= (bfd_vma) 0x3; | |
5357 | return OPERAND_MATCH; | |
5358 | } | |
5359 | else | |
5360 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5361 | } |
bf3ca999 TW |
5362 | break; |
5363 | ||
800eeca4 JW |
5364 | case IA64_OPND_IMM44: |
5365 | /* least 16 bits must be zero */ | |
5366 | if ((e->X_add_number & 0xffff) != 0) | |
87f8eb97 JW |
5367 | /* XXX technically, this is wrong: we should not be issuing warning |
5368 | messages until we're sure this instruction pattern is going to | |
5369 | be used! */ | |
542d6675 | 5370 | as_warn (_("lower 16 bits of mask ignored")); |
800eeca4 | 5371 | |
87f8eb97 | 5372 | if (e->X_op == O_constant) |
542d6675 | 5373 | { |
87f8eb97 JW |
5374 | if (((e->X_add_number >= 0 |
5375 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 44)) | |
5376 | || (e->X_add_number < 0 | |
5377 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 44)))) | |
542d6675 | 5378 | { |
87f8eb97 JW |
5379 | /* sign-extend */ |
5380 | if (e->X_add_number >= 0 | |
5381 | && (e->X_add_number & ((bfd_vma) 1 << 43)) != 0) | |
5382 | { | |
5383 | e->X_add_number |= ~(((bfd_vma) 1 << 44) - 1); | |
5384 | } | |
5385 | return OPERAND_MATCH; | |
542d6675 | 5386 | } |
87f8eb97 JW |
5387 | else |
5388 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5389 | } |
800eeca4 JW |
5390 | break; |
5391 | ||
5392 | case IA64_OPND_IMM17: | |
5393 | /* bit 0 is a don't care (pr0 is hardwired to 1) */ | |
87f8eb97 | 5394 | if (e->X_op == O_constant) |
542d6675 | 5395 | { |
87f8eb97 JW |
5396 | if (((e->X_add_number >= 0 |
5397 | && (bfd_vma) e->X_add_number < ((bfd_vma) 1 << 17)) | |
5398 | || (e->X_add_number < 0 | |
5399 | && (bfd_vma) -e->X_add_number <= ((bfd_vma) 1 << 17)))) | |
542d6675 | 5400 | { |
87f8eb97 JW |
5401 | /* sign-extend */ |
5402 | if (e->X_add_number >= 0 | |
5403 | && (e->X_add_number & ((bfd_vma) 1 << 16)) != 0) | |
5404 | { | |
5405 | e->X_add_number |= ~(((bfd_vma) 1 << 17) - 1); | |
5406 | } | |
5407 | return OPERAND_MATCH; | |
542d6675 | 5408 | } |
87f8eb97 JW |
5409 | else |
5410 | return OPERAND_OUT_OF_RANGE; | |
542d6675 | 5411 | } |
800eeca4 JW |
5412 | break; |
5413 | ||
5414 | case IA64_OPND_IMM14: | |
5415 | case IA64_OPND_IMM22: | |
5416 | relocatable = 1; | |
5417 | case IA64_OPND_IMM1: | |
5418 | case IA64_OPND_IMM8: | |
5419 | case IA64_OPND_IMM8U4: | |
5420 | case IA64_OPND_IMM8M1: | |
5421 | case IA64_OPND_IMM8M1U4: | |
5422 | case IA64_OPND_IMM8M1U8: | |
5423 | case IA64_OPND_IMM9a: | |
5424 | case IA64_OPND_IMM9b: | |
5425 | bits = operand_width (idesc->operands[index]); | |
5426 | if (relocatable && (e->X_op == O_symbol | |
5427 | || e->X_op == O_subtract | |
5428 | || e->X_op == O_pseudo_fixup)) | |
5429 | { | |
5430 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5431 | ||
5432 | if (idesc->operands[index] == IA64_OPND_IMM14) | |
5433 | fix->code = BFD_RELOC_IA64_IMM14; | |
5434 | else | |
5435 | fix->code = BFD_RELOC_IA64_IMM22; | |
5436 | ||
5437 | if (e->X_op != O_subtract) | |
5438 | { | |
5439 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
5440 | if (e->X_op == O_pseudo_fixup) | |
5441 | e->X_op = O_symbol; | |
5442 | } | |
5443 | ||
5444 | fix->opnd = idesc->operands[index]; | |
5445 | fix->expr = *e; | |
5446 | fix->is_pcrel = 0; | |
5447 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5448 | return OPERAND_MATCH; |
800eeca4 JW |
5449 | } |
5450 | else if (e->X_op != O_constant | |
5451 | && ! (e->X_op == O_big && opnd == IA64_OPND_IMM8M1U8)) | |
87f8eb97 | 5452 | return OPERAND_MISMATCH; |
800eeca4 JW |
5453 | |
5454 | if (opnd == IA64_OPND_IMM8M1U4) | |
5455 | { | |
5456 | /* Zero is not valid for unsigned compares that take an adjusted | |
5457 | constant immediate range. */ | |
5458 | if (e->X_add_number == 0) | |
87f8eb97 | 5459 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5460 | |
5461 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
5462 | checks will work. */ | |
5463 | val = e->X_add_number; | |
197865e8 KH |
5464 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
5465 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
5466 | val = ((val << 32) >> 32); |
5467 | ||
5468 | /* Check for 0x100000000. This is valid because | |
5469 | 0x100000000-1 is the same as ((uint32_t) -1). */ | |
5470 | if (val == ((bfd_signed_vma) 1 << 32)) | |
87f8eb97 | 5471 | return OPERAND_MATCH; |
800eeca4 JW |
5472 | |
5473 | val = val - 1; | |
5474 | } | |
5475 | else if (opnd == IA64_OPND_IMM8M1U8) | |
5476 | { | |
5477 | /* Zero is not valid for unsigned compares that take an adjusted | |
5478 | constant immediate range. */ | |
5479 | if (e->X_add_number == 0) | |
87f8eb97 | 5480 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5481 | |
5482 | /* Check for 0x10000000000000000. */ | |
5483 | if (e->X_op == O_big) | |
5484 | { | |
5485 | if (generic_bignum[0] == 0 | |
5486 | && generic_bignum[1] == 0 | |
5487 | && generic_bignum[2] == 0 | |
5488 | && generic_bignum[3] == 0 | |
5489 | && generic_bignum[4] == 1) | |
87f8eb97 | 5490 | return OPERAND_MATCH; |
800eeca4 | 5491 | else |
87f8eb97 | 5492 | return OPERAND_OUT_OF_RANGE; |
800eeca4 JW |
5493 | } |
5494 | else | |
5495 | val = e->X_add_number - 1; | |
5496 | } | |
5497 | else if (opnd == IA64_OPND_IMM8M1) | |
5498 | val = e->X_add_number - 1; | |
5499 | else if (opnd == IA64_OPND_IMM8U4) | |
5500 | { | |
5501 | /* Sign-extend 32-bit unsigned numbers, so that the following range | |
5502 | checks will work. */ | |
5503 | val = e->X_add_number; | |
197865e8 KH |
5504 | if (((val & (~(bfd_vma) 0 << 32)) == 0) |
5505 | && ((val & ((bfd_vma) 1 << 31)) != 0)) | |
800eeca4 JW |
5506 | val = ((val << 32) >> 32); |
5507 | } | |
5508 | else | |
5509 | val = e->X_add_number; | |
5510 | ||
2434f565 JW |
5511 | if ((val >= 0 && (bfd_vma) val < ((bfd_vma) 1 << (bits - 1))) |
5512 | || (val < 0 && (bfd_vma) -val <= ((bfd_vma) 1 << (bits - 1)))) | |
87f8eb97 JW |
5513 | return OPERAND_MATCH; |
5514 | else | |
5515 | return OPERAND_OUT_OF_RANGE; | |
800eeca4 JW |
5516 | |
5517 | case IA64_OPND_INC3: | |
5518 | /* +/- 1, 4, 8, 16 */ | |
5519 | val = e->X_add_number; | |
5520 | if (val < 0) | |
5521 | val = -val; | |
87f8eb97 JW |
5522 | if (e->X_op == O_constant) |
5523 | { | |
5524 | if ((val == 1 || val == 4 || val == 8 || val == 16)) | |
5525 | return OPERAND_MATCH; | |
5526 | else | |
5527 | return OPERAND_OUT_OF_RANGE; | |
5528 | } | |
800eeca4 JW |
5529 | break; |
5530 | ||
5531 | case IA64_OPND_TGT25: | |
5532 | case IA64_OPND_TGT25b: | |
5533 | case IA64_OPND_TGT25c: | |
5534 | case IA64_OPND_TGT64: | |
5535 | if (e->X_op == O_symbol) | |
5536 | { | |
5537 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5538 | if (opnd == IA64_OPND_TGT25) | |
5539 | fix->code = BFD_RELOC_IA64_PCREL21F; | |
5540 | else if (opnd == IA64_OPND_TGT25b) | |
5541 | fix->code = BFD_RELOC_IA64_PCREL21M; | |
5542 | else if (opnd == IA64_OPND_TGT25c) | |
5543 | fix->code = BFD_RELOC_IA64_PCREL21B; | |
542d6675 | 5544 | else if (opnd == IA64_OPND_TGT64) |
c67e42c9 RH |
5545 | fix->code = BFD_RELOC_IA64_PCREL60B; |
5546 | else | |
5547 | abort (); | |
5548 | ||
800eeca4 JW |
5549 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); |
5550 | fix->opnd = idesc->operands[index]; | |
5551 | fix->expr = *e; | |
5552 | fix->is_pcrel = 1; | |
5553 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5554 | return OPERAND_MATCH; |
800eeca4 JW |
5555 | } |
5556 | case IA64_OPND_TAG13: | |
5557 | case IA64_OPND_TAG13b: | |
5558 | switch (e->X_op) | |
5559 | { | |
5560 | case O_constant: | |
87f8eb97 | 5561 | return OPERAND_MATCH; |
800eeca4 JW |
5562 | |
5563 | case O_symbol: | |
5564 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
fa1cb89c JW |
5565 | /* There are no external relocs for TAG13/TAG13b fields, so we |
5566 | create a dummy reloc. This will not live past md_apply_fix3. */ | |
5567 | fix->code = BFD_RELOC_UNUSED; | |
5568 | fix->code = ia64_gen_real_reloc_type (e->X_op_symbol, fix->code); | |
800eeca4 JW |
5569 | fix->opnd = idesc->operands[index]; |
5570 | fix->expr = *e; | |
5571 | fix->is_pcrel = 1; | |
5572 | ++CURR_SLOT.num_fixups; | |
87f8eb97 | 5573 | return OPERAND_MATCH; |
800eeca4 JW |
5574 | |
5575 | default: | |
5576 | break; | |
5577 | } | |
5578 | break; | |
5579 | ||
a823923b RH |
5580 | case IA64_OPND_LDXMOV: |
5581 | fix = CURR_SLOT.fixup + CURR_SLOT.num_fixups; | |
5582 | fix->code = BFD_RELOC_IA64_LDXMOV; | |
5583 | fix->opnd = idesc->operands[index]; | |
5584 | fix->expr = *e; | |
5585 | fix->is_pcrel = 0; | |
5586 | ++CURR_SLOT.num_fixups; | |
5587 | return OPERAND_MATCH; | |
5588 | ||
800eeca4 JW |
5589 | default: |
5590 | break; | |
5591 | } | |
87f8eb97 | 5592 | return OPERAND_MISMATCH; |
800eeca4 JW |
5593 | } |
5594 | ||
5595 | static int | |
5596 | parse_operand (e) | |
5597 | expressionS *e; | |
5598 | { | |
5599 | int sep = '\0'; | |
5600 | ||
5601 | memset (e, 0, sizeof (*e)); | |
5602 | e->X_op = O_absent; | |
5603 | SKIP_WHITESPACE (); | |
5604 | if (*input_line_pointer != '}') | |
5605 | expression (e); | |
5606 | sep = *input_line_pointer++; | |
5607 | ||
5608 | if (sep == '}') | |
5609 | { | |
5610 | if (!md.manual_bundling) | |
5611 | as_warn ("Found '}' when manual bundling is off"); | |
5612 | else | |
5613 | CURR_SLOT.manual_bundling_off = 1; | |
5614 | md.manual_bundling = 0; | |
5615 | sep = '\0'; | |
5616 | } | |
5617 | return sep; | |
5618 | } | |
5619 | ||
5620 | /* Returns the next entry in the opcode table that matches the one in | |
5621 | IDESC, and frees the entry in IDESC. If no matching entry is | |
197865e8 | 5622 | found, NULL is returned instead. */ |
800eeca4 JW |
5623 | |
5624 | static struct ia64_opcode * | |
5625 | get_next_opcode (struct ia64_opcode *idesc) | |
5626 | { | |
5627 | struct ia64_opcode *next = ia64_find_next_opcode (idesc); | |
5628 | ia64_free_opcode (idesc); | |
5629 | return next; | |
5630 | } | |
5631 | ||
5632 | /* Parse the operands for the opcode and find the opcode variant that | |
5633 | matches the specified operands, or NULL if no match is possible. */ | |
542d6675 KH |
5634 | |
5635 | static struct ia64_opcode * | |
800eeca4 JW |
5636 | parse_operands (idesc) |
5637 | struct ia64_opcode *idesc; | |
5638 | { | |
5639 | int i = 0, highest_unmatched_operand, num_operands = 0, num_outputs = 0; | |
87f8eb97 | 5640 | int error_pos, out_of_range_pos, curr_out_of_range_pos, sep = 0; |
800eeca4 | 5641 | enum ia64_opnd expected_operand = IA64_OPND_NIL; |
87f8eb97 | 5642 | enum operand_match_result result; |
800eeca4 JW |
5643 | char mnemonic[129]; |
5644 | char *first_arg = 0, *end, *saved_input_pointer; | |
5645 | unsigned int sof; | |
5646 | ||
5647 | assert (strlen (idesc->name) <= 128); | |
5648 | ||
5649 | strcpy (mnemonic, idesc->name); | |
5650 | if (idesc->operands[2] == IA64_OPND_SOF) | |
5651 | { | |
5652 | /* To make the common idiom "alloc loc?=ar.pfs,0,1,0,0" work, we | |
5653 | can't parse the first operand until we have parsed the | |
5654 | remaining operands of the "alloc" instruction. */ | |
5655 | SKIP_WHITESPACE (); | |
5656 | first_arg = input_line_pointer; | |
5657 | end = strchr (input_line_pointer, '='); | |
5658 | if (!end) | |
5659 | { | |
5660 | as_bad ("Expected separator `='"); | |
5661 | return 0; | |
5662 | } | |
5663 | input_line_pointer = end + 1; | |
5664 | ++i; | |
5665 | ++num_outputs; | |
5666 | } | |
5667 | ||
5668 | for (; i < NELEMS (CURR_SLOT.opnd); ++i) | |
5669 | { | |
5670 | sep = parse_operand (CURR_SLOT.opnd + i); | |
5671 | if (CURR_SLOT.opnd[i].X_op == O_absent) | |
5672 | break; | |
5673 | ||
5674 | ++num_operands; | |
5675 | ||
5676 | if (sep != '=' && sep != ',') | |
5677 | break; | |
5678 | ||
5679 | if (sep == '=') | |
5680 | { | |
5681 | if (num_outputs > 0) | |
5682 | as_bad ("Duplicate equal sign (=) in instruction"); | |
5683 | else | |
5684 | num_outputs = i + 1; | |
5685 | } | |
5686 | } | |
5687 | if (sep != '\0') | |
5688 | { | |
5689 | as_bad ("Illegal operand separator `%c'", sep); | |
5690 | return 0; | |
5691 | } | |
197865e8 | 5692 | |
800eeca4 JW |
5693 | if (idesc->operands[2] == IA64_OPND_SOF) |
5694 | { | |
5695 | /* map alloc r1=ar.pfs,i,l,o,r to alloc r1=ar.pfs,(i+l+o),(i+l),r */ | |
5696 | know (strcmp (idesc->name, "alloc") == 0); | |
5697 | if (num_operands == 5 /* first_arg not included in this count! */ | |
5698 | && CURR_SLOT.opnd[2].X_op == O_constant | |
5699 | && CURR_SLOT.opnd[3].X_op == O_constant | |
5700 | && CURR_SLOT.opnd[4].X_op == O_constant | |
5701 | && CURR_SLOT.opnd[5].X_op == O_constant) | |
5702 | { | |
5703 | sof = set_regstack (CURR_SLOT.opnd[2].X_add_number, | |
5704 | CURR_SLOT.opnd[3].X_add_number, | |
5705 | CURR_SLOT.opnd[4].X_add_number, | |
5706 | CURR_SLOT.opnd[5].X_add_number); | |
5707 | ||
542d6675 | 5708 | /* now we can parse the first arg: */ |
800eeca4 JW |
5709 | saved_input_pointer = input_line_pointer; |
5710 | input_line_pointer = first_arg; | |
5711 | sep = parse_operand (CURR_SLOT.opnd + 0); | |
5712 | if (sep != '=') | |
5713 | --num_outputs; /* force error */ | |
5714 | input_line_pointer = saved_input_pointer; | |
5715 | ||
5716 | CURR_SLOT.opnd[2].X_add_number = sof; | |
5717 | CURR_SLOT.opnd[3].X_add_number | |
5718 | = sof - CURR_SLOT.opnd[4].X_add_number; | |
5719 | CURR_SLOT.opnd[4] = CURR_SLOT.opnd[5]; | |
5720 | } | |
5721 | } | |
5722 | ||
5723 | highest_unmatched_operand = 0; | |
87f8eb97 JW |
5724 | curr_out_of_range_pos = -1; |
5725 | error_pos = 0; | |
800eeca4 JW |
5726 | expected_operand = idesc->operands[0]; |
5727 | for (; idesc; idesc = get_next_opcode (idesc)) | |
5728 | { | |
5729 | if (num_outputs != idesc->num_outputs) | |
5730 | continue; /* mismatch in # of outputs */ | |
5731 | ||
5732 | CURR_SLOT.num_fixups = 0; | |
87f8eb97 JW |
5733 | |
5734 | /* Try to match all operands. If we see an out-of-range operand, | |
5735 | then continue trying to match the rest of the operands, since if | |
5736 | the rest match, then this idesc will give the best error message. */ | |
5737 | ||
5738 | out_of_range_pos = -1; | |
800eeca4 | 5739 | for (i = 0; i < num_operands && idesc->operands[i]; ++i) |
87f8eb97 JW |
5740 | { |
5741 | result = operand_match (idesc, i, CURR_SLOT.opnd + i); | |
5742 | if (result != OPERAND_MATCH) | |
5743 | { | |
5744 | if (result != OPERAND_OUT_OF_RANGE) | |
5745 | break; | |
5746 | if (out_of_range_pos < 0) | |
5747 | /* remember position of the first out-of-range operand: */ | |
5748 | out_of_range_pos = i; | |
5749 | } | |
5750 | } | |
800eeca4 | 5751 | |
87f8eb97 JW |
5752 | /* If we did not match all operands, or if at least one operand was |
5753 | out-of-range, then this idesc does not match. Keep track of which | |
5754 | idesc matched the most operands before failing. If we have two | |
5755 | idescs that failed at the same position, and one had an out-of-range | |
5756 | operand, then prefer the out-of-range operand. Thus if we have | |
5757 | "add r0=0x1000000,r1" we get an error saying the constant is out | |
5758 | of range instead of an error saying that the constant should have been | |
5759 | a register. */ | |
5760 | ||
5761 | if (i != num_operands || out_of_range_pos >= 0) | |
800eeca4 | 5762 | { |
87f8eb97 JW |
5763 | if (i > highest_unmatched_operand |
5764 | || (i == highest_unmatched_operand | |
5765 | && out_of_range_pos > curr_out_of_range_pos)) | |
800eeca4 JW |
5766 | { |
5767 | highest_unmatched_operand = i; | |
87f8eb97 JW |
5768 | if (out_of_range_pos >= 0) |
5769 | { | |
5770 | expected_operand = idesc->operands[out_of_range_pos]; | |
5771 | error_pos = out_of_range_pos; | |
5772 | } | |
5773 | else | |
5774 | { | |
5775 | expected_operand = idesc->operands[i]; | |
5776 | error_pos = i; | |
5777 | } | |
5778 | curr_out_of_range_pos = out_of_range_pos; | |
800eeca4 JW |
5779 | } |
5780 | continue; | |
5781 | } | |
5782 | ||
5783 | if (num_operands < NELEMS (idesc->operands) | |
5784 | && idesc->operands[num_operands]) | |
5785 | continue; /* mismatch in number of arguments */ | |
5786 | ||
5787 | break; | |
5788 | } | |
5789 | if (!idesc) | |
5790 | { | |
5791 | if (expected_operand) | |
5792 | as_bad ("Operand %u of `%s' should be %s", | |
87f8eb97 | 5793 | error_pos + 1, mnemonic, |
800eeca4 JW |
5794 | elf64_ia64_operands[expected_operand].desc); |
5795 | else | |
5796 | as_bad ("Operand mismatch"); | |
5797 | return 0; | |
5798 | } | |
5799 | return idesc; | |
5800 | } | |
5801 | ||
88be23ec BS |
5802 | /* Keep track of state necessary to determine whether a NOP is necessary |
5803 | to avoid an erratum in A and B step Itanium chips, and return 1 if we | |
5804 | detect a case where additional NOPs may be necessary. */ | |
5805 | static int | |
5806 | errata_nop_necessary_p (slot, insn_unit) | |
5807 | struct slot *slot; | |
5808 | enum ia64_unit insn_unit; | |
5809 | { | |
5810 | int i; | |
5811 | struct group *this_group = md.last_groups + md.group_idx; | |
5812 | struct group *prev_group = md.last_groups + (md.group_idx + 2) % 3; | |
5813 | struct ia64_opcode *idesc = slot->idesc; | |
5814 | ||
5815 | /* Test whether this could be the first insn in a problematic sequence. */ | |
5816 | if (insn_unit == IA64_UNIT_F) | |
5817 | { | |
5818 | for (i = 0; i < idesc->num_outputs; i++) | |
5819 | if (idesc->operands[i] == IA64_OPND_P1 | |
5820 | || idesc->operands[i] == IA64_OPND_P2) | |
5821 | { | |
5822 | int regno = slot->opnd[i].X_add_number - REG_P; | |
3557da92 | 5823 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5824 | if (regno >= 64) |
3557da92 | 5825 | return 0; |
88be23ec BS |
5826 | this_group->p_reg_set[regno] = 1; |
5827 | } | |
5828 | } | |
5829 | ||
5830 | /* Test whether this could be the second insn in a problematic sequence. */ | |
5831 | if (insn_unit == IA64_UNIT_M && slot->qp_regno > 0 | |
5832 | && prev_group->p_reg_set[slot->qp_regno]) | |
5833 | { | |
5834 | for (i = 0; i < idesc->num_outputs; i++) | |
5835 | if (idesc->operands[i] == IA64_OPND_R1 | |
5836 | || idesc->operands[i] == IA64_OPND_R2 | |
5837 | || idesc->operands[i] == IA64_OPND_R3) | |
5838 | { | |
5839 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5840 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5841 | if (regno >= 128) |
3557da92 | 5842 | return 0; |
88be23ec BS |
5843 | if (strncmp (idesc->name, "add", 3) != 0 |
5844 | && strncmp (idesc->name, "sub", 3) != 0 | |
5845 | && strncmp (idesc->name, "shladd", 6) != 0 | |
5846 | && (idesc->flags & IA64_OPCODE_POSTINC) == 0) | |
5847 | this_group->g_reg_set_conditionally[regno] = 1; | |
5848 | } | |
5849 | } | |
5850 | ||
5851 | /* Test whether this could be the third insn in a problematic sequence. */ | |
5852 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; i++) | |
5853 | { | |
5854 | if (/* For fc, ptc, ptr, tak, thash, tpa, ttag, probe, ptr, ptc. */ | |
5855 | idesc->operands[i] == IA64_OPND_R3 | |
5856 | /* For mov indirect. */ | |
5857 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
5858 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
5859 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
5860 | || idesc->operands[i] == IA64_OPND_PKR_R3 | |
5861 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
5862 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
5863 | || idesc->operands[i] == IA64_OPND_MSR_R3 | |
5864 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
5865 | /* For itr. */ | |
5866 | || idesc->operands[i] == IA64_OPND_ITR_R3 | |
5867 | || idesc->operands[i] == IA64_OPND_DTR_R3 | |
5868 | /* Normal memory addresses (load, store, xchg, cmpxchg, etc.). */ | |
5869 | || idesc->operands[i] == IA64_OPND_MR3) | |
5870 | { | |
5871 | int regno = slot->opnd[i].X_add_number - REG_GR; | |
3557da92 | 5872 | /* Ignore invalid operands; they generate errors elsewhere. */ |
ca683b78 | 5873 | if (regno >= 128) |
3557da92 | 5874 | return 0; |
88be23ec BS |
5875 | if (idesc->operands[i] == IA64_OPND_R3) |
5876 | { | |
5877 | if (strcmp (idesc->name, "fc") != 0 | |
5878 | && strcmp (idesc->name, "tak") != 0 | |
5879 | && strcmp (idesc->name, "thash") != 0 | |
5880 | && strcmp (idesc->name, "tpa") != 0 | |
5881 | && strcmp (idesc->name, "ttag") != 0 | |
5882 | && strncmp (idesc->name, "ptr", 3) != 0 | |
5883 | && strncmp (idesc->name, "ptc", 3) != 0 | |
5884 | && strncmp (idesc->name, "probe", 5) != 0) | |
40449e9f | 5885 | return 0; |
88be23ec | 5886 | } |
bc805888 | 5887 | if (prev_group->g_reg_set_conditionally[regno]) |
88be23ec BS |
5888 | return 1; |
5889 | } | |
5890 | } | |
5891 | return 0; | |
5892 | } | |
5893 | ||
800eeca4 JW |
5894 | static void |
5895 | build_insn (slot, insnp) | |
5896 | struct slot *slot; | |
5897 | bfd_vma *insnp; | |
5898 | { | |
5899 | const struct ia64_operand *odesc, *o2desc; | |
5900 | struct ia64_opcode *idesc = slot->idesc; | |
5901 | bfd_signed_vma insn, val; | |
5902 | const char *err; | |
5903 | int i; | |
5904 | ||
5905 | insn = idesc->opcode | slot->qp_regno; | |
5906 | ||
5907 | for (i = 0; i < NELEMS (idesc->operands) && idesc->operands[i]; ++i) | |
5908 | { | |
c67e42c9 RH |
5909 | if (slot->opnd[i].X_op == O_register |
5910 | || slot->opnd[i].X_op == O_constant | |
5911 | || slot->opnd[i].X_op == O_index) | |
5912 | val = slot->opnd[i].X_add_number; | |
5913 | else if (slot->opnd[i].X_op == O_big) | |
800eeca4 | 5914 | { |
c67e42c9 RH |
5915 | /* This must be the value 0x10000000000000000. */ |
5916 | assert (idesc->operands[i] == IA64_OPND_IMM8M1U8); | |
5917 | val = 0; | |
5918 | } | |
5919 | else | |
5920 | val = 0; | |
5921 | ||
5922 | switch (idesc->operands[i]) | |
5923 | { | |
5924 | case IA64_OPND_IMMU64: | |
800eeca4 JW |
5925 | *insnp++ = (val >> 22) & 0x1ffffffffffLL; |
5926 | insn |= (((val & 0x7f) << 13) | (((val >> 7) & 0x1ff) << 27) | |
5927 | | (((val >> 16) & 0x1f) << 22) | (((val >> 21) & 0x1) << 21) | |
5928 | | (((val >> 63) & 0x1) << 36)); | |
c67e42c9 RH |
5929 | continue; |
5930 | ||
5931 | case IA64_OPND_IMMU62: | |
542d6675 KH |
5932 | val &= 0x3fffffffffffffffULL; |
5933 | if (val != slot->opnd[i].X_add_number) | |
5934 | as_warn (_("Value truncated to 62 bits")); | |
5935 | *insnp++ = (val >> 21) & 0x1ffffffffffLL; | |
5936 | insn |= (((val & 0xfffff) << 6) | (((val >> 20) & 0x1) << 36)); | |
c67e42c9 | 5937 | continue; |
800eeca4 | 5938 | |
c67e42c9 RH |
5939 | case IA64_OPND_TGT64: |
5940 | val >>= 4; | |
5941 | *insnp++ = ((val >> 20) & 0x7fffffffffLL) << 2; | |
5942 | insn |= ((((val >> 59) & 0x1) << 36) | |
5943 | | (((val >> 0) & 0xfffff) << 13)); | |
5944 | continue; | |
800eeca4 | 5945 | |
c67e42c9 RH |
5946 | case IA64_OPND_AR3: |
5947 | val -= REG_AR; | |
5948 | break; | |
5949 | ||
5950 | case IA64_OPND_B1: | |
5951 | case IA64_OPND_B2: | |
5952 | val -= REG_BR; | |
5953 | break; | |
5954 | ||
5955 | case IA64_OPND_CR3: | |
5956 | val -= REG_CR; | |
5957 | break; | |
5958 | ||
5959 | case IA64_OPND_F1: | |
5960 | case IA64_OPND_F2: | |
5961 | case IA64_OPND_F3: | |
5962 | case IA64_OPND_F4: | |
5963 | val -= REG_FR; | |
5964 | break; | |
5965 | ||
5966 | case IA64_OPND_P1: | |
5967 | case IA64_OPND_P2: | |
5968 | val -= REG_P; | |
5969 | break; | |
5970 | ||
5971 | case IA64_OPND_R1: | |
5972 | case IA64_OPND_R2: | |
5973 | case IA64_OPND_R3: | |
5974 | case IA64_OPND_R3_2: | |
5975 | case IA64_OPND_CPUID_R3: | |
5976 | case IA64_OPND_DBR_R3: | |
5977 | case IA64_OPND_DTR_R3: | |
5978 | case IA64_OPND_ITR_R3: | |
5979 | case IA64_OPND_IBR_R3: | |
5980 | case IA64_OPND_MR3: | |
5981 | case IA64_OPND_MSR_R3: | |
5982 | case IA64_OPND_PKR_R3: | |
5983 | case IA64_OPND_PMC_R3: | |
5984 | case IA64_OPND_PMD_R3: | |
197865e8 | 5985 | case IA64_OPND_RR_R3: |
c67e42c9 RH |
5986 | val -= REG_GR; |
5987 | break; | |
5988 | ||
5989 | default: | |
5990 | break; | |
5991 | } | |
5992 | ||
5993 | odesc = elf64_ia64_operands + idesc->operands[i]; | |
5994 | err = (*odesc->insert) (odesc, val, &insn); | |
5995 | if (err) | |
5996 | as_bad_where (slot->src_file, slot->src_line, | |
5997 | "Bad operand value: %s", err); | |
5998 | if (idesc->flags & IA64_OPCODE_PSEUDO) | |
5999 | { | |
6000 | if ((idesc->flags & IA64_OPCODE_F2_EQ_F3) | |
6001 | && odesc == elf64_ia64_operands + IA64_OPND_F3) | |
6002 | { | |
6003 | o2desc = elf64_ia64_operands + IA64_OPND_F2; | |
6004 | (*o2desc->insert) (o2desc, val, &insn); | |
800eeca4 | 6005 | } |
c67e42c9 RH |
6006 | if ((idesc->flags & IA64_OPCODE_LEN_EQ_64MCNT) |
6007 | && (odesc == elf64_ia64_operands + IA64_OPND_CPOS6a | |
6008 | || odesc == elf64_ia64_operands + IA64_OPND_POS6)) | |
800eeca4 | 6009 | { |
c67e42c9 RH |
6010 | o2desc = elf64_ia64_operands + IA64_OPND_LEN6; |
6011 | (*o2desc->insert) (o2desc, 64 - val, &insn); | |
800eeca4 JW |
6012 | } |
6013 | } | |
6014 | } | |
6015 | *insnp = insn; | |
6016 | } | |
6017 | ||
6018 | static void | |
6019 | emit_one_bundle () | |
6020 | { | |
6021 | unsigned int manual_bundling_on = 0, manual_bundling_off = 0; | |
6022 | unsigned int manual_bundling = 0; | |
6023 | enum ia64_unit required_unit, insn_unit = 0; | |
6024 | enum ia64_insn_type type[3], insn_type; | |
6025 | unsigned int template, orig_template; | |
542d6675 | 6026 | bfd_vma insn[3] = { -1, -1, -1 }; |
800eeca4 JW |
6027 | struct ia64_opcode *idesc; |
6028 | int end_of_insn_group = 0, user_template = -1; | |
6029 | int n, i, j, first, curr; | |
2434f565 | 6030 | unw_rec_list *ptr; |
800eeca4 JW |
6031 | bfd_vma t0 = 0, t1 = 0; |
6032 | struct label_fix *lfix; | |
6033 | struct insn_fix *ifix; | |
6034 | char mnemonic[16]; | |
6035 | fixS *fix; | |
6036 | char *f; | |
6037 | ||
6038 | first = (md.curr_slot + NUM_SLOTS - md.num_slots_in_use) % NUM_SLOTS; | |
6039 | know (first >= 0 & first < NUM_SLOTS); | |
6040 | n = MIN (3, md.num_slots_in_use); | |
6041 | ||
6042 | /* Determine template: user user_template if specified, best match | |
542d6675 | 6043 | otherwise: */ |
800eeca4 JW |
6044 | |
6045 | if (md.slot[first].user_template >= 0) | |
6046 | user_template = template = md.slot[first].user_template; | |
6047 | else | |
6048 | { | |
032efc85 | 6049 | /* Auto select appropriate template. */ |
800eeca4 JW |
6050 | memset (type, 0, sizeof (type)); |
6051 | curr = first; | |
6052 | for (i = 0; i < n; ++i) | |
6053 | { | |
032efc85 RH |
6054 | if (md.slot[curr].label_fixups && i != 0) |
6055 | break; | |
800eeca4 JW |
6056 | type[i] = md.slot[curr].idesc->type; |
6057 | curr = (curr + 1) % NUM_SLOTS; | |
6058 | } | |
6059 | template = best_template[type[0]][type[1]][type[2]]; | |
6060 | } | |
6061 | ||
542d6675 | 6062 | /* initialize instructions with appropriate nops: */ |
800eeca4 JW |
6063 | for (i = 0; i < 3; ++i) |
6064 | insn[i] = nop[ia64_templ_desc[template].exec_unit[i]]; | |
6065 | ||
6066 | f = frag_more (16); | |
6067 | ||
542d6675 | 6068 | /* now fill in slots with as many insns as possible: */ |
800eeca4 JW |
6069 | curr = first; |
6070 | idesc = md.slot[curr].idesc; | |
6071 | end_of_insn_group = 0; | |
6072 | for (i = 0; i < 3 && md.num_slots_in_use > 0; ++i) | |
6073 | { | |
e0c9811a JW |
6074 | /* Set the slot number for prologue/body records now as those |
6075 | refer to the current point, not the point after the | |
542d6675 | 6076 | instruction has been issued: */ |
10850f29 JW |
6077 | /* Don't try to delete prologue/body records here, as that will cause |
6078 | them to also be deleted from the master list of unwind records. */ | |
e0c9811a | 6079 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) |
10850f29 JW |
6080 | if (ptr->r.type == prologue || ptr->r.type == prologue_gr |
6081 | || ptr->r.type == body) | |
f5a30c2e JW |
6082 | { |
6083 | ptr->slot_number = (unsigned long) f + i; | |
6084 | ptr->slot_frag = frag_now; | |
6085 | } | |
e0c9811a | 6086 | |
800eeca4 JW |
6087 | if (idesc->flags & IA64_OPCODE_SLOT2) |
6088 | { | |
6089 | if (manual_bundling && i != 2) | |
6090 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6091 | "`%s' must be last in bundle", idesc->name); | |
6092 | else | |
6093 | i = 2; | |
6094 | } | |
6095 | if (idesc->flags & IA64_OPCODE_LAST) | |
6096 | { | |
2434f565 JW |
6097 | int required_slot; |
6098 | unsigned int required_template; | |
800eeca4 JW |
6099 | |
6100 | /* If we need a stop bit after an M slot, our only choice is | |
6101 | template 5 (M;;MI). If we need a stop bit after a B | |
6102 | slot, our only choice is to place it at the end of the | |
6103 | bundle, because the only available templates are MIB, | |
6104 | MBB, BBB, MMB, and MFB. We don't handle anything other | |
6105 | than M and B slots because these are the only kind of | |
6106 | instructions that can have the IA64_OPCODE_LAST bit set. */ | |
6107 | required_template = template; | |
6108 | switch (idesc->type) | |
6109 | { | |
6110 | case IA64_TYPE_M: | |
6111 | required_slot = 0; | |
6112 | required_template = 5; | |
6113 | break; | |
6114 | ||
6115 | case IA64_TYPE_B: | |
6116 | required_slot = 2; | |
6117 | break; | |
6118 | ||
6119 | default: | |
6120 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6121 | "Internal error: don't know how to force %s to end" | |
6122 | "of instruction group", idesc->name); | |
6123 | required_slot = i; | |
6124 | break; | |
6125 | } | |
6126 | if (manual_bundling && i != required_slot) | |
6127 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6128 | "`%s' must be last in instruction group", | |
6129 | idesc->name); | |
6130 | if (required_slot < i) | |
6131 | /* Can't fit this instruction. */ | |
6132 | break; | |
6133 | ||
6134 | i = required_slot; | |
6135 | if (required_template != template) | |
6136 | { | |
6137 | /* If we switch the template, we need to reset the NOPs | |
6138 | after slot i. The slot-types of the instructions ahead | |
6139 | of i never change, so we don't need to worry about | |
6140 | changing NOPs in front of this slot. */ | |
6141 | for (j = i; j < 3; ++j) | |
6142 | insn[j] = nop[ia64_templ_desc[required_template].exec_unit[j]]; | |
6143 | } | |
6144 | template = required_template; | |
6145 | } | |
6146 | if (curr != first && md.slot[curr].label_fixups) | |
6147 | { | |
6148 | if (manual_bundling_on) | |
6149 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6150 | "Label must be first in a bundle"); | |
6151 | /* This insn must go into the first slot of a bundle. */ | |
6152 | break; | |
6153 | } | |
6154 | ||
6155 | manual_bundling_on = md.slot[curr].manual_bundling_on; | |
6156 | manual_bundling_off = md.slot[curr].manual_bundling_off; | |
6157 | ||
6158 | if (manual_bundling_on) | |
6159 | { | |
6160 | if (curr == first) | |
6161 | manual_bundling = 1; | |
6162 | else | |
6163 | break; /* need to start a new bundle */ | |
6164 | } | |
6165 | ||
6166 | if (end_of_insn_group && md.num_slots_in_use >= 1) | |
6167 | { | |
6168 | /* We need an instruction group boundary in the middle of a | |
6169 | bundle. See if we can switch to an other template with | |
6170 | an appropriate boundary. */ | |
6171 | ||
6172 | orig_template = template; | |
6173 | if (i == 1 && (user_template == 4 | |
6174 | || (user_template < 0 | |
6175 | && (ia64_templ_desc[template].exec_unit[0] | |
6176 | == IA64_UNIT_M)))) | |
6177 | { | |
6178 | template = 5; | |
6179 | end_of_insn_group = 0; | |
6180 | } | |
6181 | else if (i == 2 && (user_template == 0 | |
6182 | || (user_template < 0 | |
6183 | && (ia64_templ_desc[template].exec_unit[1] | |
6184 | == IA64_UNIT_I))) | |
6185 | /* This test makes sure we don't switch the template if | |
6186 | the next instruction is one that needs to be first in | |
6187 | an instruction group. Since all those instructions are | |
6188 | in the M group, there is no way such an instruction can | |
6189 | fit in this bundle even if we switch the template. The | |
6190 | reason we have to check for this is that otherwise we | |
6191 | may end up generating "MI;;I M.." which has the deadly | |
6192 | effect that the second M instruction is no longer the | |
6193 | first in the bundle! --davidm 99/12/16 */ | |
6194 | && (idesc->flags & IA64_OPCODE_FIRST) == 0) | |
6195 | { | |
6196 | template = 1; | |
6197 | end_of_insn_group = 0; | |
6198 | } | |
6199 | else if (curr != first) | |
6200 | /* can't fit this insn */ | |
6201 | break; | |
6202 | ||
6203 | if (template != orig_template) | |
6204 | /* if we switch the template, we need to reset the NOPs | |
6205 | after slot i. The slot-types of the instructions ahead | |
6206 | of i never change, so we don't need to worry about | |
6207 | changing NOPs in front of this slot. */ | |
6208 | for (j = i; j < 3; ++j) | |
6209 | insn[j] = nop[ia64_templ_desc[template].exec_unit[j]]; | |
6210 | } | |
6211 | required_unit = ia64_templ_desc[template].exec_unit[i]; | |
6212 | ||
c10d9d8f | 6213 | /* resolve dynamic opcodes such as "break", "hint", and "nop": */ |
800eeca4 JW |
6214 | if (idesc->type == IA64_TYPE_DYN) |
6215 | { | |
6216 | if ((strcmp (idesc->name, "nop") == 0) | |
c10d9d8f | 6217 | || (strcmp (idesc->name, "hint") == 0) |
800eeca4 JW |
6218 | || (strcmp (idesc->name, "break") == 0)) |
6219 | insn_unit = required_unit; | |
6220 | else if (strcmp (idesc->name, "chk.s") == 0) | |
6221 | { | |
6222 | insn_unit = IA64_UNIT_M; | |
6223 | if (required_unit == IA64_UNIT_I) | |
6224 | insn_unit = IA64_UNIT_I; | |
6225 | } | |
6226 | else | |
6227 | as_fatal ("emit_one_bundle: unexpected dynamic op"); | |
6228 | ||
6229 | sprintf (mnemonic, "%s.%c", idesc->name, "?imbf??"[insn_unit]); | |
3d56ab85 | 6230 | ia64_free_opcode (idesc); |
800eeca4 JW |
6231 | md.slot[curr].idesc = idesc = ia64_find_opcode (mnemonic); |
6232 | #if 0 | |
6233 | know (!idesc->next); /* no resolved dynamic ops have collisions */ | |
6234 | #endif | |
6235 | } | |
6236 | else | |
6237 | { | |
6238 | insn_type = idesc->type; | |
6239 | insn_unit = IA64_UNIT_NIL; | |
6240 | switch (insn_type) | |
6241 | { | |
6242 | case IA64_TYPE_A: | |
6243 | if (required_unit == IA64_UNIT_I || required_unit == IA64_UNIT_M) | |
6244 | insn_unit = required_unit; | |
6245 | break; | |
542d6675 | 6246 | case IA64_TYPE_X: insn_unit = IA64_UNIT_L; break; |
800eeca4 JW |
6247 | case IA64_TYPE_I: insn_unit = IA64_UNIT_I; break; |
6248 | case IA64_TYPE_M: insn_unit = IA64_UNIT_M; break; | |
6249 | case IA64_TYPE_B: insn_unit = IA64_UNIT_B; break; | |
6250 | case IA64_TYPE_F: insn_unit = IA64_UNIT_F; break; | |
6251 | default: break; | |
6252 | } | |
6253 | } | |
6254 | ||
6255 | if (insn_unit != required_unit) | |
6256 | { | |
6257 | if (required_unit == IA64_UNIT_L | |
542d6675 | 6258 | && insn_unit == IA64_UNIT_I |
800eeca4 JW |
6259 | && !(idesc->flags & IA64_OPCODE_X_IN_MLX)) |
6260 | { | |
6261 | /* we got ourselves an MLX template but the current | |
197865e8 | 6262 | instruction isn't an X-unit, or an I-unit instruction |
800eeca4 JW |
6263 | that can go into the X slot of an MLX template. Duh. */ |
6264 | if (md.num_slots_in_use >= NUM_SLOTS) | |
6265 | { | |
6266 | as_bad_where (md.slot[curr].src_file, | |
6267 | md.slot[curr].src_line, | |
6268 | "`%s' can't go in X slot of " | |
6269 | "MLX template", idesc->name); | |
542d6675 | 6270 | /* drop this insn so we don't livelock: */ |
800eeca4 JW |
6271 | --md.num_slots_in_use; |
6272 | } | |
6273 | break; | |
6274 | } | |
6275 | continue; /* try next slot */ | |
6276 | } | |
6277 | ||
40449e9f KH |
6278 | { |
6279 | bfd_vma addr; | |
800eeca4 | 6280 | |
40449e9f KH |
6281 | addr = frag_now->fr_address + frag_now_fix () - 16 + i; |
6282 | dwarf2_gen_line_info (addr, &md.slot[curr].debug_line); | |
6283 | } | |
800eeca4 | 6284 | |
88be23ec BS |
6285 | if (errata_nop_necessary_p (md.slot + curr, insn_unit)) |
6286 | as_warn (_("Additional NOP may be necessary to workaround Itanium processor A/B step errata")); | |
6287 | ||
800eeca4 JW |
6288 | build_insn (md.slot + curr, insn + i); |
6289 | ||
10850f29 JW |
6290 | /* Set slot counts for non prologue/body unwind records. */ |
6291 | for (ptr = md.slot[curr].unwind_record; ptr; ptr = ptr->next) | |
6292 | if (ptr->r.type != prologue && ptr->r.type != prologue_gr | |
6293 | && ptr->r.type != body) | |
f5a30c2e JW |
6294 | { |
6295 | ptr->slot_number = (unsigned long) f + i; | |
6296 | ptr->slot_frag = frag_now; | |
6297 | } | |
10850f29 | 6298 | md.slot[curr].unwind_record = NULL; |
10850f29 | 6299 | |
800eeca4 JW |
6300 | if (required_unit == IA64_UNIT_L) |
6301 | { | |
6302 | know (i == 1); | |
6303 | /* skip one slot for long/X-unit instructions */ | |
6304 | ++i; | |
6305 | } | |
6306 | --md.num_slots_in_use; | |
6307 | ||
542d6675 | 6308 | /* now is a good time to fix up the labels for this insn: */ |
800eeca4 JW |
6309 | for (lfix = md.slot[curr].label_fixups; lfix; lfix = lfix->next) |
6310 | { | |
6311 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16); | |
6312 | symbol_set_frag (lfix->sym, frag_now); | |
6313 | } | |
f1bcba5b JW |
6314 | /* and fix up the tags also. */ |
6315 | for (lfix = md.slot[curr].tag_fixups; lfix; lfix = lfix->next) | |
6316 | { | |
6317 | S_SET_VALUE (lfix->sym, frag_now_fix () - 16 + i); | |
6318 | symbol_set_frag (lfix->sym, frag_now); | |
6319 | } | |
800eeca4 JW |
6320 | |
6321 | for (j = 0; j < md.slot[curr].num_fixups; ++j) | |
6322 | { | |
6323 | ifix = md.slot[curr].fixup + j; | |
5a080f89 | 6324 | fix = fix_new_exp (frag_now, frag_now_fix () - 16 + i, 8, |
800eeca4 JW |
6325 | &ifix->expr, ifix->is_pcrel, ifix->code); |
6326 | fix->tc_fix_data.opnd = ifix->opnd; | |
6327 | fix->fx_plt = (fix->fx_r_type == BFD_RELOC_IA64_PLTOFF22); | |
6328 | fix->fx_file = md.slot[curr].src_file; | |
6329 | fix->fx_line = md.slot[curr].src_line; | |
6330 | } | |
6331 | ||
6332 | end_of_insn_group = md.slot[curr].end_of_insn_group; | |
6333 | ||
88be23ec BS |
6334 | if (end_of_insn_group) |
6335 | { | |
6336 | md.group_idx = (md.group_idx + 1) % 3; | |
6337 | memset (md.last_groups + md.group_idx, 0, sizeof md.last_groups[0]); | |
6338 | } | |
6339 | ||
542d6675 | 6340 | /* clear slot: */ |
800eeca4 JW |
6341 | ia64_free_opcode (md.slot[curr].idesc); |
6342 | memset (md.slot + curr, 0, sizeof (md.slot[curr])); | |
6343 | md.slot[curr].user_template = -1; | |
6344 | ||
6345 | if (manual_bundling_off) | |
6346 | { | |
6347 | manual_bundling = 0; | |
6348 | break; | |
6349 | } | |
6350 | curr = (curr + 1) % NUM_SLOTS; | |
6351 | idesc = md.slot[curr].idesc; | |
6352 | } | |
6353 | if (manual_bundling) | |
6354 | { | |
6355 | if (md.num_slots_in_use > 0) | |
6356 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6357 | "`%s' does not fit into %s template", | |
6358 | idesc->name, ia64_templ_desc[template].name); | |
6359 | else | |
6360 | as_bad_where (md.slot[curr].src_file, md.slot[curr].src_line, | |
6361 | "Missing '}' at end of file"); | |
6362 | } | |
6363 | know (md.num_slots_in_use < NUM_SLOTS); | |
6364 | ||
6365 | t0 = end_of_insn_group | (template << 1) | (insn[0] << 5) | (insn[1] << 46); | |
6366 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
6367 | ||
44f5c83a JW |
6368 | number_to_chars_littleendian (f + 0, t0, 8); |
6369 | number_to_chars_littleendian (f + 8, t1, 8); | |
f5a30c2e JW |
6370 | |
6371 | unwind.next_slot_number = (unsigned long) f + 16; | |
6372 | unwind.next_slot_frag = frag_now; | |
800eeca4 JW |
6373 | } |
6374 | ||
6375 | int | |
6376 | md_parse_option (c, arg) | |
6377 | int c; | |
6378 | char *arg; | |
6379 | { | |
7463c317 | 6380 | |
800eeca4 JW |
6381 | switch (c) |
6382 | { | |
c43c2cc5 | 6383 | /* Switches from the Intel assembler. */ |
44f5c83a | 6384 | case 'm': |
800eeca4 JW |
6385 | if (strcmp (arg, "ilp64") == 0 |
6386 | || strcmp (arg, "lp64") == 0 | |
6387 | || strcmp (arg, "p64") == 0) | |
6388 | { | |
6389 | md.flags |= EF_IA_64_ABI64; | |
6390 | } | |
6391 | else if (strcmp (arg, "ilp32") == 0) | |
6392 | { | |
6393 | md.flags &= ~EF_IA_64_ABI64; | |
6394 | } | |
6395 | else if (strcmp (arg, "le") == 0) | |
6396 | { | |
6397 | md.flags &= ~EF_IA_64_BE; | |
6398 | } | |
6399 | else if (strcmp (arg, "be") == 0) | |
6400 | { | |
6401 | md.flags |= EF_IA_64_BE; | |
6402 | } | |
6403 | else | |
6404 | return 0; | |
6405 | break; | |
6406 | ||
6407 | case 'N': | |
6408 | if (strcmp (arg, "so") == 0) | |
6409 | { | |
542d6675 | 6410 | /* Suppress signon message. */ |
800eeca4 JW |
6411 | } |
6412 | else if (strcmp (arg, "pi") == 0) | |
6413 | { | |
6414 | /* Reject privileged instructions. FIXME */ | |
6415 | } | |
6416 | else if (strcmp (arg, "us") == 0) | |
6417 | { | |
6418 | /* Allow union of signed and unsigned range. FIXME */ | |
6419 | } | |
6420 | else if (strcmp (arg, "close_fcalls") == 0) | |
6421 | { | |
6422 | /* Do not resolve global function calls. */ | |
6423 | } | |
6424 | else | |
6425 | return 0; | |
6426 | break; | |
6427 | ||
6428 | case 'C': | |
6429 | /* temp[="prefix"] Insert temporary labels into the object file | |
6430 | symbol table prefixed by "prefix". | |
6431 | Default prefix is ":temp:". | |
6432 | */ | |
6433 | break; | |
6434 | ||
6435 | case 'a': | |
800eeca4 JW |
6436 | /* indirect=<tgt> Assume unannotated indirect branches behavior |
6437 | according to <tgt> -- | |
6438 | exit: branch out from the current context (default) | |
6439 | labels: all labels in context may be branch targets | |
6440 | */ | |
85b40035 L |
6441 | if (strncmp (arg, "indirect=", 9) != 0) |
6442 | return 0; | |
800eeca4 JW |
6443 | break; |
6444 | ||
6445 | case 'x': | |
6446 | /* -X conflicts with an ignored option, use -x instead */ | |
6447 | md.detect_dv = 1; | |
6448 | if (!arg || strcmp (arg, "explicit") == 0) | |
542d6675 KH |
6449 | { |
6450 | /* set default mode to explicit */ | |
6451 | md.default_explicit_mode = 1; | |
6452 | break; | |
6453 | } | |
800eeca4 | 6454 | else if (strcmp (arg, "auto") == 0) |
542d6675 KH |
6455 | { |
6456 | md.default_explicit_mode = 0; | |
6457 | } | |
800eeca4 | 6458 | else if (strcmp (arg, "debug") == 0) |
542d6675 KH |
6459 | { |
6460 | md.debug_dv = 1; | |
6461 | } | |
800eeca4 | 6462 | else if (strcmp (arg, "debugx") == 0) |
542d6675 KH |
6463 | { |
6464 | md.default_explicit_mode = 1; | |
6465 | md.debug_dv = 1; | |
6466 | } | |
800eeca4 | 6467 | else |
542d6675 KH |
6468 | { |
6469 | as_bad (_("Unrecognized option '-x%s'"), arg); | |
6470 | } | |
800eeca4 JW |
6471 | break; |
6472 | ||
6473 | case 'S': | |
6474 | /* nops Print nops statistics. */ | |
6475 | break; | |
6476 | ||
c43c2cc5 JW |
6477 | /* GNU specific switches for gcc. */ |
6478 | case OPTION_MCONSTANT_GP: | |
6479 | md.flags |= EF_IA_64_CONS_GP; | |
6480 | break; | |
6481 | ||
6482 | case OPTION_MAUTO_PIC: | |
6483 | md.flags |= EF_IA_64_NOFUNCDESC_CONS_GP; | |
6484 | break; | |
6485 | ||
800eeca4 JW |
6486 | default: |
6487 | return 0; | |
6488 | } | |
6489 | ||
6490 | return 1; | |
6491 | } | |
6492 | ||
6493 | void | |
6494 | md_show_usage (stream) | |
6495 | FILE *stream; | |
6496 | { | |
542d6675 | 6497 | fputs (_("\ |
800eeca4 | 6498 | IA-64 options:\n\ |
6290819d NC |
6499 | --mconstant-gp mark output file as using the constant-GP model\n\ |
6500 | (sets ELF header flag EF_IA_64_CONS_GP)\n\ | |
6501 | --mauto-pic mark output file as using the constant-GP model\n\ | |
6502 | without function descriptors (sets ELF header flag\n\ | |
6503 | EF_IA_64_NOFUNCDESC_CONS_GP)\n\ | |
44f5c83a JW |
6504 | -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64)\n\ |
6505 | -mle | -mbe select little- or big-endian byte order (default -mle)\n\ | |
800eeca4 JW |
6506 | -x | -xexplicit turn on dependency violation checking (default)\n\ |
6507 | -xauto automagically remove dependency violations\n\ | |
6508 | -xdebug debug dependency violation checker\n"), | |
6509 | stream); | |
6510 | } | |
6511 | ||
acebd4ce AS |
6512 | void |
6513 | ia64_after_parse_args () | |
6514 | { | |
6515 | if (debug_type == DEBUG_STABS) | |
6516 | as_fatal (_("--gstabs is not supported for ia64")); | |
6517 | } | |
6518 | ||
44576e1f RH |
6519 | /* Return true if TYPE fits in TEMPL at SLOT. */ |
6520 | ||
6521 | static int | |
800eeca4 JW |
6522 | match (int templ, int type, int slot) |
6523 | { | |
6524 | enum ia64_unit unit; | |
6525 | int result; | |
6526 | ||
6527 | unit = ia64_templ_desc[templ].exec_unit[slot]; | |
6528 | switch (type) | |
6529 | { | |
6530 | case IA64_TYPE_DYN: result = 1; break; /* for nop and break */ | |
6531 | case IA64_TYPE_A: | |
6532 | result = (unit == IA64_UNIT_I || unit == IA64_UNIT_M); | |
6533 | break; | |
6534 | case IA64_TYPE_X: result = (unit == IA64_UNIT_L); break; | |
6535 | case IA64_TYPE_I: result = (unit == IA64_UNIT_I); break; | |
6536 | case IA64_TYPE_M: result = (unit == IA64_UNIT_M); break; | |
6537 | case IA64_TYPE_B: result = (unit == IA64_UNIT_B); break; | |
6538 | case IA64_TYPE_F: result = (unit == IA64_UNIT_F); break; | |
6539 | default: result = 0; break; | |
6540 | } | |
6541 | return result; | |
6542 | } | |
6543 | ||
44576e1f RH |
6544 | /* Add a bit of extra goodness if a nop of type F or B would fit |
6545 | in TEMPL at SLOT. */ | |
6546 | ||
6547 | static inline int | |
6548 | extra_goodness (int templ, int slot) | |
6549 | { | |
ebeeafe6 | 6550 | if (slot == 1 && match (templ, IA64_TYPE_F, slot)) |
44576e1f | 6551 | return 2; |
ebeeafe6 | 6552 | if (slot == 2 && match (templ, IA64_TYPE_B, slot)) |
44576e1f RH |
6553 | return 1; |
6554 | return 0; | |
6555 | } | |
6556 | ||
800eeca4 JW |
6557 | /* This function is called once, at assembler startup time. It sets |
6558 | up all the tables, etc. that the MD part of the assembler will need | |
6559 | that can be determined before arguments are parsed. */ | |
6560 | void | |
6561 | md_begin () | |
6562 | { | |
44f5c83a | 6563 | int i, j, k, t, total, ar_base, cr_base, goodness, best, regnum, ok; |
800eeca4 JW |
6564 | const char *err; |
6565 | char name[8]; | |
6566 | ||
6567 | md.auto_align = 1; | |
6568 | md.explicit_mode = md.default_explicit_mode; | |
6569 | ||
6570 | bfd_set_section_alignment (stdoutput, text_section, 4); | |
6571 | ||
10a98291 L |
6572 | /* Make sure fucntion pointers get initialized. */ |
6573 | target_big_endian = -1; | |
6574 | dot_byteorder (TARGET_BYTES_BIG_ENDIAN); | |
6575 | ||
13ae64f3 JJ |
6576 | pseudo_func[FUNC_DTP_MODULE].u.sym = |
6577 | symbol_new (".<dtpmod>", undefined_section, FUNC_DTP_MODULE, | |
6578 | &zero_address_frag); | |
6579 | ||
6580 | pseudo_func[FUNC_DTP_RELATIVE].u.sym = | |
6581 | symbol_new (".<dtprel>", undefined_section, FUNC_DTP_RELATIVE, | |
6582 | &zero_address_frag); | |
6583 | ||
800eeca4 | 6584 | pseudo_func[FUNC_FPTR_RELATIVE].u.sym = |
542d6675 KH |
6585 | symbol_new (".<fptr>", undefined_section, FUNC_FPTR_RELATIVE, |
6586 | &zero_address_frag); | |
800eeca4 JW |
6587 | |
6588 | pseudo_func[FUNC_GP_RELATIVE].u.sym = | |
542d6675 KH |
6589 | symbol_new (".<gprel>", undefined_section, FUNC_GP_RELATIVE, |
6590 | &zero_address_frag); | |
800eeca4 JW |
6591 | |
6592 | pseudo_func[FUNC_LT_RELATIVE].u.sym = | |
542d6675 KH |
6593 | symbol_new (".<ltoff>", undefined_section, FUNC_LT_RELATIVE, |
6594 | &zero_address_frag); | |
800eeca4 | 6595 | |
fa2c7eff RH |
6596 | pseudo_func[FUNC_LT_RELATIVE_X].u.sym = |
6597 | symbol_new (".<ltoffx>", undefined_section, FUNC_LT_RELATIVE_X, | |
6598 | &zero_address_frag); | |
6599 | ||
c67e42c9 | 6600 | pseudo_func[FUNC_PC_RELATIVE].u.sym = |
542d6675 KH |
6601 | symbol_new (".<pcrel>", undefined_section, FUNC_PC_RELATIVE, |
6602 | &zero_address_frag); | |
c67e42c9 | 6603 | |
800eeca4 | 6604 | pseudo_func[FUNC_PLT_RELATIVE].u.sym = |
542d6675 KH |
6605 | symbol_new (".<pltoff>", undefined_section, FUNC_PLT_RELATIVE, |
6606 | &zero_address_frag); | |
800eeca4 JW |
6607 | |
6608 | pseudo_func[FUNC_SEC_RELATIVE].u.sym = | |
542d6675 KH |
6609 | symbol_new (".<secrel>", undefined_section, FUNC_SEC_RELATIVE, |
6610 | &zero_address_frag); | |
800eeca4 JW |
6611 | |
6612 | pseudo_func[FUNC_SEG_RELATIVE].u.sym = | |
542d6675 KH |
6613 | symbol_new (".<segrel>", undefined_section, FUNC_SEG_RELATIVE, |
6614 | &zero_address_frag); | |
800eeca4 | 6615 | |
13ae64f3 JJ |
6616 | pseudo_func[FUNC_TP_RELATIVE].u.sym = |
6617 | symbol_new (".<tprel>", undefined_section, FUNC_TP_RELATIVE, | |
6618 | &zero_address_frag); | |
6619 | ||
800eeca4 | 6620 | pseudo_func[FUNC_LTV_RELATIVE].u.sym = |
542d6675 KH |
6621 | symbol_new (".<ltv>", undefined_section, FUNC_LTV_RELATIVE, |
6622 | &zero_address_frag); | |
800eeca4 JW |
6623 | |
6624 | pseudo_func[FUNC_LT_FPTR_RELATIVE].u.sym = | |
542d6675 KH |
6625 | symbol_new (".<ltoff.fptr>", undefined_section, FUNC_LT_FPTR_RELATIVE, |
6626 | &zero_address_frag); | |
800eeca4 | 6627 | |
13ae64f3 JJ |
6628 | pseudo_func[FUNC_LT_DTP_MODULE].u.sym = |
6629 | symbol_new (".<ltoff.dtpmod>", undefined_section, FUNC_LT_DTP_MODULE, | |
6630 | &zero_address_frag); | |
6631 | ||
6632 | pseudo_func[FUNC_LT_DTP_RELATIVE].u.sym = | |
6633 | symbol_new (".<ltoff.dptrel>", undefined_section, FUNC_LT_DTP_RELATIVE, | |
6634 | &zero_address_frag); | |
6635 | ||
6636 | pseudo_func[FUNC_LT_TP_RELATIVE].u.sym = | |
6637 | symbol_new (".<ltoff.tprel>", undefined_section, FUNC_LT_TP_RELATIVE, | |
6638 | &zero_address_frag); | |
6639 | ||
3969b680 RH |
6640 | pseudo_func[FUNC_IPLT_RELOC].u.sym = |
6641 | symbol_new (".<iplt>", undefined_section, FUNC_IPLT_RELOC, | |
6642 | &zero_address_frag); | |
6643 | ||
197865e8 | 6644 | /* Compute the table of best templates. We compute goodness as a |
44576e1f RH |
6645 | base 4 value, in which each match counts for 3, each F counts |
6646 | for 2, each B counts for 1. This should maximize the number of | |
6647 | F and B nops in the chosen bundles, which is good because these | |
6648 | pipelines are least likely to be overcommitted. */ | |
800eeca4 JW |
6649 | for (i = 0; i < IA64_NUM_TYPES; ++i) |
6650 | for (j = 0; j < IA64_NUM_TYPES; ++j) | |
6651 | for (k = 0; k < IA64_NUM_TYPES; ++k) | |
6652 | { | |
6653 | best = 0; | |
6654 | for (t = 0; t < NELEMS (ia64_templ_desc); ++t) | |
6655 | { | |
6656 | goodness = 0; | |
6657 | if (match (t, i, 0)) | |
6658 | { | |
6659 | if (match (t, j, 1)) | |
6660 | { | |
6661 | if (match (t, k, 2)) | |
44576e1f | 6662 | goodness = 3 + 3 + 3; |
800eeca4 | 6663 | else |
44576e1f | 6664 | goodness = 3 + 3 + extra_goodness (t, 2); |
800eeca4 JW |
6665 | } |
6666 | else if (match (t, j, 2)) | |
44576e1f | 6667 | goodness = 3 + 3 + extra_goodness (t, 1); |
800eeca4 | 6668 | else |
44576e1f RH |
6669 | { |
6670 | goodness = 3; | |
6671 | goodness += extra_goodness (t, 1); | |
6672 | goodness += extra_goodness (t, 2); | |
6673 | } | |
800eeca4 JW |
6674 | } |
6675 | else if (match (t, i, 1)) | |
6676 | { | |
6677 | if (match (t, j, 2)) | |
44576e1f | 6678 | goodness = 3 + 3; |
800eeca4 | 6679 | else |
44576e1f | 6680 | goodness = 3 + extra_goodness (t, 2); |
800eeca4 JW |
6681 | } |
6682 | else if (match (t, i, 2)) | |
44576e1f | 6683 | goodness = 3 + extra_goodness (t, 1); |
800eeca4 JW |
6684 | |
6685 | if (goodness > best) | |
6686 | { | |
6687 | best = goodness; | |
6688 | best_template[i][j][k] = t; | |
6689 | } | |
6690 | } | |
6691 | } | |
6692 | ||
6693 | for (i = 0; i < NUM_SLOTS; ++i) | |
6694 | md.slot[i].user_template = -1; | |
6695 | ||
6696 | md.pseudo_hash = hash_new (); | |
6697 | for (i = 0; i < NELEMS (pseudo_opcode); ++i) | |
6698 | { | |
6699 | err = hash_insert (md.pseudo_hash, pseudo_opcode[i].name, | |
6700 | (void *) (pseudo_opcode + i)); | |
6701 | if (err) | |
6702 | as_fatal ("ia64.md_begin: can't hash `%s': %s", | |
6703 | pseudo_opcode[i].name, err); | |
6704 | } | |
6705 | ||
6706 | md.reg_hash = hash_new (); | |
6707 | md.dynreg_hash = hash_new (); | |
6708 | md.const_hash = hash_new (); | |
6709 | md.entry_hash = hash_new (); | |
6710 | ||
542d6675 | 6711 | /* general registers: */ |
800eeca4 JW |
6712 | |
6713 | total = 128; | |
6714 | for (i = 0; i < total; ++i) | |
6715 | { | |
6716 | sprintf (name, "r%d", i - REG_GR); | |
6717 | md.regsym[i] = declare_register (name, i); | |
6718 | } | |
6719 | ||
542d6675 | 6720 | /* floating point registers: */ |
800eeca4 JW |
6721 | total += 128; |
6722 | for (; i < total; ++i) | |
6723 | { | |
6724 | sprintf (name, "f%d", i - REG_FR); | |
6725 | md.regsym[i] = declare_register (name, i); | |
6726 | } | |
6727 | ||
542d6675 | 6728 | /* application registers: */ |
800eeca4 JW |
6729 | total += 128; |
6730 | ar_base = i; | |
6731 | for (; i < total; ++i) | |
6732 | { | |
6733 | sprintf (name, "ar%d", i - REG_AR); | |
6734 | md.regsym[i] = declare_register (name, i); | |
6735 | } | |
6736 | ||
542d6675 | 6737 | /* control registers: */ |
800eeca4 JW |
6738 | total += 128; |
6739 | cr_base = i; | |
6740 | for (; i < total; ++i) | |
6741 | { | |
6742 | sprintf (name, "cr%d", i - REG_CR); | |
6743 | md.regsym[i] = declare_register (name, i); | |
6744 | } | |
6745 | ||
542d6675 | 6746 | /* predicate registers: */ |
800eeca4 JW |
6747 | total += 64; |
6748 | for (; i < total; ++i) | |
6749 | { | |
6750 | sprintf (name, "p%d", i - REG_P); | |
6751 | md.regsym[i] = declare_register (name, i); | |
6752 | } | |
6753 | ||
542d6675 | 6754 | /* branch registers: */ |
800eeca4 JW |
6755 | total += 8; |
6756 | for (; i < total; ++i) | |
6757 | { | |
6758 | sprintf (name, "b%d", i - REG_BR); | |
6759 | md.regsym[i] = declare_register (name, i); | |
6760 | } | |
6761 | ||
6762 | md.regsym[REG_IP] = declare_register ("ip", REG_IP); | |
6763 | md.regsym[REG_CFM] = declare_register ("cfm", REG_CFM); | |
6764 | md.regsym[REG_PR] = declare_register ("pr", REG_PR); | |
6765 | md.regsym[REG_PR_ROT] = declare_register ("pr.rot", REG_PR_ROT); | |
6766 | md.regsym[REG_PSR] = declare_register ("psr", REG_PSR); | |
6767 | md.regsym[REG_PSR_L] = declare_register ("psr.l", REG_PSR_L); | |
6768 | md.regsym[REG_PSR_UM] = declare_register ("psr.um", REG_PSR_UM); | |
6769 | ||
6770 | for (i = 0; i < NELEMS (indirect_reg); ++i) | |
6771 | { | |
6772 | regnum = indirect_reg[i].regnum; | |
6773 | md.regsym[regnum] = declare_register (indirect_reg[i].name, regnum); | |
6774 | } | |
6775 | ||
542d6675 | 6776 | /* define synonyms for application registers: */ |
800eeca4 JW |
6777 | for (i = REG_AR; i < REG_AR + NELEMS (ar); ++i) |
6778 | md.regsym[i] = declare_register (ar[i - REG_AR].name, | |
6779 | REG_AR + ar[i - REG_AR].regnum); | |
6780 | ||
542d6675 | 6781 | /* define synonyms for control registers: */ |
800eeca4 JW |
6782 | for (i = REG_CR; i < REG_CR + NELEMS (cr); ++i) |
6783 | md.regsym[i] = declare_register (cr[i - REG_CR].name, | |
6784 | REG_CR + cr[i - REG_CR].regnum); | |
6785 | ||
6786 | declare_register ("gp", REG_GR + 1); | |
6787 | declare_register ("sp", REG_GR + 12); | |
6788 | declare_register ("rp", REG_BR + 0); | |
6789 | ||
542d6675 | 6790 | /* pseudo-registers used to specify unwind info: */ |
e0c9811a JW |
6791 | declare_register ("psp", REG_PSP); |
6792 | ||
800eeca4 JW |
6793 | declare_register_set ("ret", 4, REG_GR + 8); |
6794 | declare_register_set ("farg", 8, REG_FR + 8); | |
6795 | declare_register_set ("fret", 8, REG_FR + 8); | |
6796 | ||
6797 | for (i = 0; i < NELEMS (const_bits); ++i) | |
6798 | { | |
6799 | err = hash_insert (md.const_hash, const_bits[i].name, | |
6800 | (PTR) (const_bits + i)); | |
6801 | if (err) | |
6802 | as_fatal ("Inserting \"%s\" into constant hash table failed: %s", | |
6803 | name, err); | |
6804 | } | |
6805 | ||
44f5c83a JW |
6806 | /* Set the architecture and machine depending on defaults and command line |
6807 | options. */ | |
6808 | if (md.flags & EF_IA_64_ABI64) | |
6809 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf64); | |
6810 | else | |
6811 | ok = bfd_set_arch_mach (stdoutput, bfd_arch_ia64, bfd_mach_ia64_elf32); | |
6812 | ||
6813 | if (! ok) | |
6814 | as_warn (_("Could not set architecture and machine")); | |
800eeca4 | 6815 | |
557debba JW |
6816 | /* Set the pointer size and pointer shift size depending on md.flags */ |
6817 | ||
6818 | if (md.flags & EF_IA_64_ABI64) | |
6819 | { | |
6820 | md.pointer_size = 8; /* pointers are 8 bytes */ | |
6821 | md.pointer_size_shift = 3; /* alignment is 8 bytes = 2^2 */ | |
6822 | } | |
6823 | else | |
6824 | { | |
6825 | md.pointer_size = 4; /* pointers are 4 bytes */ | |
6826 | md.pointer_size_shift = 2; /* alignment is 4 bytes = 2^2 */ | |
6827 | } | |
6828 | ||
800eeca4 JW |
6829 | md.mem_offset.hint = 0; |
6830 | md.path = 0; | |
6831 | md.maxpaths = 0; | |
6832 | md.entry_labels = NULL; | |
6833 | } | |
6834 | ||
44f5c83a JW |
6835 | /* Set the elf type to 64 bit ABI by default. Cannot do this in md_begin |
6836 | because that is called after md_parse_option which is where we do the | |
6837 | dynamic changing of md.flags based on -mlp64 or -milp32. Also, set the | |
6838 | default endianness. */ | |
6839 | ||
6840 | void | |
6841 | ia64_init (argc, argv) | |
2434f565 JW |
6842 | int argc ATTRIBUTE_UNUSED; |
6843 | char **argv ATTRIBUTE_UNUSED; | |
44f5c83a | 6844 | { |
1cd8ff38 | 6845 | md.flags = MD_FLAGS_DEFAULT; |
44f5c83a JW |
6846 | } |
6847 | ||
6848 | /* Return a string for the target object file format. */ | |
6849 | ||
6850 | const char * | |
6851 | ia64_target_format () | |
6852 | { | |
6853 | if (OUTPUT_FLAVOR == bfd_target_elf_flavour) | |
6854 | { | |
72a76794 JW |
6855 | if (md.flags & EF_IA_64_BE) |
6856 | { | |
6857 | if (md.flags & EF_IA_64_ABI64) | |
1cd8ff38 | 6858 | #if defined(TE_AIX50) |
7463c317 | 6859 | return "elf64-ia64-aix-big"; |
1cd8ff38 NC |
6860 | #elif defined(TE_HPUX) |
6861 | return "elf64-ia64-hpux-big"; | |
7463c317 | 6862 | #else |
72a76794 | 6863 | return "elf64-ia64-big"; |
7463c317 | 6864 | #endif |
72a76794 | 6865 | else |
1cd8ff38 | 6866 | #if defined(TE_AIX50) |
7463c317 | 6867 | return "elf32-ia64-aix-big"; |
1cd8ff38 NC |
6868 | #elif defined(TE_HPUX) |
6869 | return "elf32-ia64-hpux-big"; | |
7463c317 | 6870 | #else |
72a76794 | 6871 | return "elf32-ia64-big"; |
7463c317 | 6872 | #endif |
72a76794 | 6873 | } |
44f5c83a | 6874 | else |
72a76794 JW |
6875 | { |
6876 | if (md.flags & EF_IA_64_ABI64) | |
7463c317 TW |
6877 | #ifdef TE_AIX50 |
6878 | return "elf64-ia64-aix-little"; | |
6879 | #else | |
72a76794 | 6880 | return "elf64-ia64-little"; |
7463c317 | 6881 | #endif |
72a76794 | 6882 | else |
7463c317 TW |
6883 | #ifdef TE_AIX50 |
6884 | return "elf32-ia64-aix-little"; | |
6885 | #else | |
72a76794 | 6886 | return "elf32-ia64-little"; |
7463c317 | 6887 | #endif |
72a76794 | 6888 | } |
44f5c83a JW |
6889 | } |
6890 | else | |
6891 | return "unknown-format"; | |
6892 | } | |
6893 | ||
800eeca4 JW |
6894 | void |
6895 | ia64_end_of_source () | |
6896 | { | |
542d6675 | 6897 | /* terminate insn group upon reaching end of file: */ |
800eeca4 JW |
6898 | insn_group_break (1, 0, 0); |
6899 | ||
542d6675 | 6900 | /* emits slots we haven't written yet: */ |
800eeca4 JW |
6901 | ia64_flush_insns (); |
6902 | ||
6903 | bfd_set_private_flags (stdoutput, md.flags); | |
6904 | ||
800eeca4 JW |
6905 | md.mem_offset.hint = 0; |
6906 | } | |
6907 | ||
6908 | void | |
6909 | ia64_start_line () | |
6910 | { | |
f1bcba5b JW |
6911 | if (md.qp.X_op == O_register) |
6912 | as_bad ("qualifying predicate not followed by instruction"); | |
800eeca4 JW |
6913 | md.qp.X_op = O_absent; |
6914 | ||
6915 | if (ignore_input ()) | |
6916 | return; | |
6917 | ||
6918 | if (input_line_pointer[0] == ';' && input_line_pointer[-1] == ';') | |
6919 | { | |
6920 | if (md.detect_dv && !md.explicit_mode) | |
542d6675 | 6921 | as_warn (_("Explicit stops are ignored in auto mode")); |
800eeca4 | 6922 | else |
542d6675 | 6923 | insn_group_break (1, 0, 0); |
800eeca4 JW |
6924 | } |
6925 | } | |
6926 | ||
f1bcba5b JW |
6927 | /* This is a hook for ia64_frob_label, so that it can distinguish tags from |
6928 | labels. */ | |
6929 | static int defining_tag = 0; | |
6930 | ||
800eeca4 JW |
6931 | int |
6932 | ia64_unrecognized_line (ch) | |
6933 | int ch; | |
6934 | { | |
6935 | switch (ch) | |
6936 | { | |
6937 | case '(': | |
6938 | expression (&md.qp); | |
6939 | if (*input_line_pointer++ != ')') | |
6940 | { | |
6941 | as_bad ("Expected ')'"); | |
6942 | return 0; | |
6943 | } | |
6944 | if (md.qp.X_op != O_register) | |
6945 | { | |
6946 | as_bad ("Qualifying predicate expected"); | |
6947 | return 0; | |
6948 | } | |
6949 | if (md.qp.X_add_number < REG_P || md.qp.X_add_number >= REG_P + 64) | |
6950 | { | |
6951 | as_bad ("Predicate register expected"); | |
6952 | return 0; | |
6953 | } | |
6954 | return 1; | |
6955 | ||
6956 | case '{': | |
6957 | if (md.manual_bundling) | |
6958 | as_warn ("Found '{' when manual bundling is already turned on"); | |
6959 | else | |
6960 | CURR_SLOT.manual_bundling_on = 1; | |
6961 | md.manual_bundling = 1; | |
6962 | ||
542d6675 KH |
6963 | /* Bundling is only acceptable in explicit mode |
6964 | or when in default automatic mode. */ | |
800eeca4 | 6965 | if (md.detect_dv && !md.explicit_mode) |
542d6675 KH |
6966 | { |
6967 | if (!md.mode_explicitly_set | |
6968 | && !md.default_explicit_mode) | |
6969 | dot_dv_mode ('E'); | |
6970 | else | |
6971 | as_warn (_("Found '{' after explicit switch to automatic mode")); | |
6972 | } | |
800eeca4 JW |
6973 | return 1; |
6974 | ||
6975 | case '}': | |
6976 | if (!md.manual_bundling) | |
6977 | as_warn ("Found '}' when manual bundling is off"); | |
6978 | else | |
6979 | PREV_SLOT.manual_bundling_off = 1; | |
6980 | md.manual_bundling = 0; | |
6981 | ||
6982 | /* switch back to automatic mode, if applicable */ | |
197865e8 | 6983 | if (md.detect_dv |
542d6675 KH |
6984 | && md.explicit_mode |
6985 | && !md.mode_explicitly_set | |
6986 | && !md.default_explicit_mode) | |
6987 | dot_dv_mode ('A'); | |
800eeca4 JW |
6988 | |
6989 | /* Allow '{' to follow on the same line. We also allow ";;", but that | |
6990 | happens automatically because ';' is an end of line marker. */ | |
6991 | SKIP_WHITESPACE (); | |
6992 | if (input_line_pointer[0] == '{') | |
6993 | { | |
6994 | input_line_pointer++; | |
6995 | return ia64_unrecognized_line ('{'); | |
6996 | } | |
6997 | ||
6998 | demand_empty_rest_of_line (); | |
6999 | return 1; | |
7000 | ||
f1bcba5b JW |
7001 | case '[': |
7002 | { | |
7003 | char *s; | |
7004 | char c; | |
7005 | symbolS *tag; | |
4d5a53ff | 7006 | int temp; |
f1bcba5b JW |
7007 | |
7008 | if (md.qp.X_op == O_register) | |
7009 | { | |
7010 | as_bad ("Tag must come before qualifying predicate."); | |
7011 | return 0; | |
7012 | } | |
4d5a53ff JW |
7013 | |
7014 | /* This implements just enough of read_a_source_file in read.c to | |
7015 | recognize labels. */ | |
7016 | if (is_name_beginner (*input_line_pointer)) | |
7017 | { | |
7018 | s = input_line_pointer; | |
7019 | c = get_symbol_end (); | |
7020 | } | |
7021 | else if (LOCAL_LABELS_FB | |
3882b010 | 7022 | && ISDIGIT (*input_line_pointer)) |
4d5a53ff JW |
7023 | { |
7024 | temp = 0; | |
3882b010 | 7025 | while (ISDIGIT (*input_line_pointer)) |
4d5a53ff JW |
7026 | temp = (temp * 10) + *input_line_pointer++ - '0'; |
7027 | fb_label_instance_inc (temp); | |
7028 | s = fb_label_name (temp, 0); | |
7029 | c = *input_line_pointer; | |
7030 | } | |
7031 | else | |
7032 | { | |
7033 | s = NULL; | |
7034 | c = '\0'; | |
7035 | } | |
f1bcba5b JW |
7036 | if (c != ':') |
7037 | { | |
7038 | /* Put ':' back for error messages' sake. */ | |
7039 | *input_line_pointer++ = ':'; | |
7040 | as_bad ("Expected ':'"); | |
7041 | return 0; | |
7042 | } | |
4d5a53ff | 7043 | |
f1bcba5b JW |
7044 | defining_tag = 1; |
7045 | tag = colon (s); | |
7046 | defining_tag = 0; | |
7047 | /* Put ':' back for error messages' sake. */ | |
7048 | *input_line_pointer++ = ':'; | |
7049 | if (*input_line_pointer++ != ']') | |
7050 | { | |
7051 | as_bad ("Expected ']'"); | |
7052 | return 0; | |
7053 | } | |
7054 | if (! tag) | |
7055 | { | |
7056 | as_bad ("Tag name expected"); | |
7057 | return 0; | |
7058 | } | |
7059 | return 1; | |
7060 | } | |
7061 | ||
800eeca4 JW |
7062 | default: |
7063 | break; | |
7064 | } | |
542d6675 KH |
7065 | |
7066 | /* Not a valid line. */ | |
7067 | return 0; | |
800eeca4 JW |
7068 | } |
7069 | ||
7070 | void | |
7071 | ia64_frob_label (sym) | |
7072 | struct symbol *sym; | |
7073 | { | |
7074 | struct label_fix *fix; | |
7075 | ||
f1bcba5b JW |
7076 | /* Tags need special handling since they are not bundle breaks like |
7077 | labels. */ | |
7078 | if (defining_tag) | |
7079 | { | |
7080 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
7081 | fix->sym = sym; | |
7082 | fix->next = CURR_SLOT.tag_fixups; | |
7083 | CURR_SLOT.tag_fixups = fix; | |
7084 | ||
7085 | return; | |
7086 | } | |
7087 | ||
800eeca4 JW |
7088 | if (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) |
7089 | { | |
7090 | md.last_text_seg = now_seg; | |
7091 | fix = obstack_alloc (¬es, sizeof (*fix)); | |
7092 | fix->sym = sym; | |
7093 | fix->next = CURR_SLOT.label_fixups; | |
7094 | CURR_SLOT.label_fixups = fix; | |
7095 | ||
542d6675 | 7096 | /* Keep track of how many code entry points we've seen. */ |
800eeca4 | 7097 | if (md.path == md.maxpaths) |
542d6675 KH |
7098 | { |
7099 | md.maxpaths += 20; | |
7100 | md.entry_labels = (const char **) | |
7101 | xrealloc ((void *) md.entry_labels, | |
7102 | md.maxpaths * sizeof (char *)); | |
7103 | } | |
800eeca4 JW |
7104 | md.entry_labels[md.path++] = S_GET_NAME (sym); |
7105 | } | |
7106 | } | |
7107 | ||
7108 | void | |
7109 | ia64_flush_pending_output () | |
7110 | { | |
4d5a53ff JW |
7111 | if (!md.keep_pending_output |
7112 | && bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) | |
800eeca4 JW |
7113 | { |
7114 | /* ??? This causes many unnecessary stop bits to be emitted. | |
7115 | Unfortunately, it isn't clear if it is safe to remove this. */ | |
7116 | insn_group_break (1, 0, 0); | |
7117 | ia64_flush_insns (); | |
7118 | } | |
7119 | } | |
7120 | ||
7121 | /* Do ia64-specific expression optimization. All that's done here is | |
7122 | to transform index expressions that are either due to the indexing | |
7123 | of rotating registers or due to the indexing of indirect register | |
7124 | sets. */ | |
7125 | int | |
7126 | ia64_optimize_expr (l, op, r) | |
7127 | expressionS *l; | |
7128 | operatorT op; | |
7129 | expressionS *r; | |
7130 | { | |
7131 | unsigned num_regs; | |
7132 | ||
7133 | if (op == O_index) | |
7134 | { | |
7135 | if (l->X_op == O_register && r->X_op == O_constant) | |
7136 | { | |
7137 | num_regs = (l->X_add_number >> 16); | |
7138 | if ((unsigned) r->X_add_number >= num_regs) | |
7139 | { | |
7140 | if (!num_regs) | |
7141 | as_bad ("No current frame"); | |
7142 | else | |
7143 | as_bad ("Index out of range 0..%u", num_regs - 1); | |
7144 | r->X_add_number = 0; | |
7145 | } | |
7146 | l->X_add_number = (l->X_add_number & 0xffff) + r->X_add_number; | |
7147 | return 1; | |
7148 | } | |
7149 | else if (l->X_op == O_register && r->X_op == O_register) | |
7150 | { | |
7151 | if (l->X_add_number < IND_CPUID || l->X_add_number > IND_RR | |
7152 | || l->X_add_number == IND_MEM) | |
7153 | { | |
7154 | as_bad ("Indirect register set name expected"); | |
7155 | l->X_add_number = IND_CPUID; | |
7156 | } | |
7157 | l->X_op = O_index; | |
7158 | l->X_op_symbol = md.regsym[l->X_add_number]; | |
7159 | l->X_add_number = r->X_add_number; | |
7160 | return 1; | |
7161 | } | |
7162 | } | |
7163 | return 0; | |
7164 | } | |
7165 | ||
7166 | int | |
7167 | ia64_parse_name (name, e) | |
7168 | char *name; | |
7169 | expressionS *e; | |
7170 | { | |
7171 | struct const_desc *cdesc; | |
7172 | struct dynreg *dr = 0; | |
7173 | unsigned int regnum; | |
7174 | struct symbol *sym; | |
7175 | char *end; | |
7176 | ||
542d6675 | 7177 | /* first see if NAME is a known register name: */ |
800eeca4 JW |
7178 | sym = hash_find (md.reg_hash, name); |
7179 | if (sym) | |
7180 | { | |
7181 | e->X_op = O_register; | |
7182 | e->X_add_number = S_GET_VALUE (sym); | |
7183 | return 1; | |
7184 | } | |
7185 | ||
7186 | cdesc = hash_find (md.const_hash, name); | |
7187 | if (cdesc) | |
7188 | { | |
7189 | e->X_op = O_constant; | |
7190 | e->X_add_number = cdesc->value; | |
7191 | return 1; | |
7192 | } | |
7193 | ||
542d6675 | 7194 | /* check for inN, locN, or outN: */ |
800eeca4 JW |
7195 | switch (name[0]) |
7196 | { | |
7197 | case 'i': | |
3882b010 | 7198 | if (name[1] == 'n' && ISDIGIT (name[2])) |
800eeca4 JW |
7199 | { |
7200 | dr = &md.in; | |
7201 | name += 2; | |
7202 | } | |
7203 | break; | |
7204 | ||
7205 | case 'l': | |
3882b010 | 7206 | if (name[1] == 'o' && name[2] == 'c' && ISDIGIT (name[3])) |
800eeca4 JW |
7207 | { |
7208 | dr = &md.loc; | |
7209 | name += 3; | |
7210 | } | |
7211 | break; | |
7212 | ||
7213 | case 'o': | |
3882b010 | 7214 | if (name[1] == 'u' && name[2] == 't' && ISDIGIT (name[3])) |
800eeca4 JW |
7215 | { |
7216 | dr = &md.out; | |
7217 | name += 3; | |
7218 | } | |
7219 | break; | |
7220 | ||
7221 | default: | |
7222 | break; | |
7223 | } | |
7224 | ||
7225 | if (dr) | |
7226 | { | |
542d6675 | 7227 | /* The name is inN, locN, or outN; parse the register number. */ |
800eeca4 JW |
7228 | regnum = strtoul (name, &end, 10); |
7229 | if (end > name && *end == '\0') | |
7230 | { | |
7231 | if ((unsigned) regnum >= dr->num_regs) | |
7232 | { | |
7233 | if (!dr->num_regs) | |
7234 | as_bad ("No current frame"); | |
7235 | else | |
542d6675 KH |
7236 | as_bad ("Register number out of range 0..%u", |
7237 | dr->num_regs - 1); | |
800eeca4 JW |
7238 | regnum = 0; |
7239 | } | |
7240 | e->X_op = O_register; | |
7241 | e->X_add_number = dr->base + regnum; | |
7242 | return 1; | |
7243 | } | |
7244 | } | |
7245 | ||
7246 | if ((dr = hash_find (md.dynreg_hash, name))) | |
7247 | { | |
7248 | /* We've got ourselves the name of a rotating register set. | |
542d6675 KH |
7249 | Store the base register number in the low 16 bits of |
7250 | X_add_number and the size of the register set in the top 16 | |
7251 | bits. */ | |
800eeca4 JW |
7252 | e->X_op = O_register; |
7253 | e->X_add_number = dr->base | (dr->num_regs << 16); | |
7254 | return 1; | |
7255 | } | |
7256 | return 0; | |
7257 | } | |
7258 | ||
7259 | /* Remove the '#' suffix that indicates a symbol as opposed to a register. */ | |
7260 | ||
7261 | char * | |
7262 | ia64_canonicalize_symbol_name (name) | |
7263 | char *name; | |
7264 | { | |
542d6675 KH |
7265 | size_t len = strlen (name); |
7266 | if (len > 1 && name[len - 1] == '#') | |
7267 | name[len - 1] = '\0'; | |
800eeca4 JW |
7268 | return name; |
7269 | } | |
7270 | ||
3e37788f JW |
7271 | /* Return true if idesc is a conditional branch instruction. This excludes |
7272 | the modulo scheduled branches, and br.ia. Mod-sched branches are excluded | |
7273 | because they always read/write resources regardless of the value of the | |
7274 | qualifying predicate. br.ia must always use p0, and hence is always | |
7275 | taken. Thus this function returns true for branches which can fall | |
7276 | through, and which use no resources if they do fall through. */ | |
1deb8127 | 7277 | |
800eeca4 JW |
7278 | static int |
7279 | is_conditional_branch (idesc) | |
542d6675 | 7280 | struct ia64_opcode *idesc; |
800eeca4 | 7281 | { |
1deb8127 | 7282 | /* br is a conditional branch. Everything that starts with br. except |
3e37788f JW |
7283 | br.ia, br.c{loop,top,exit}, and br.w{top,exit} is a conditional branch. |
7284 | Everything that starts with brl is a conditional branch. */ | |
1deb8127 JW |
7285 | return (idesc->name[0] == 'b' && idesc->name[1] == 'r' |
7286 | && (idesc->name[2] == '\0' | |
3e37788f JW |
7287 | || (idesc->name[2] == '.' && idesc->name[3] != 'i' |
7288 | && idesc->name[3] != 'c' && idesc->name[3] != 'w') | |
7289 | || idesc->name[2] == 'l' | |
7290 | /* br.cond, br.call, br.clr */ | |
7291 | || (idesc->name[2] == '.' && idesc->name[3] == 'c' | |
7292 | && (idesc->name[4] == 'a' || idesc->name[4] == 'o' | |
7293 | || (idesc->name[4] == 'l' && idesc->name[5] == 'r'))))); | |
800eeca4 JW |
7294 | } |
7295 | ||
7296 | /* Return whether the given opcode is a taken branch. If there's any doubt, | |
542d6675 KH |
7297 | returns zero. */ |
7298 | ||
800eeca4 JW |
7299 | static int |
7300 | is_taken_branch (idesc) | |
542d6675 | 7301 | struct ia64_opcode *idesc; |
800eeca4 JW |
7302 | { |
7303 | return ((is_conditional_branch (idesc) && CURR_SLOT.qp_regno == 0) | |
542d6675 | 7304 | || strncmp (idesc->name, "br.ia", 5) == 0); |
800eeca4 JW |
7305 | } |
7306 | ||
7307 | /* Return whether the given opcode is an interruption or rfi. If there's any | |
542d6675 KH |
7308 | doubt, returns zero. */ |
7309 | ||
800eeca4 JW |
7310 | static int |
7311 | is_interruption_or_rfi (idesc) | |
542d6675 | 7312 | struct ia64_opcode *idesc; |
800eeca4 JW |
7313 | { |
7314 | if (strcmp (idesc->name, "rfi") == 0) | |
7315 | return 1; | |
7316 | return 0; | |
7317 | } | |
7318 | ||
7319 | /* Returns the index of the given dependency in the opcode's list of chks, or | |
7320 | -1 if there is no dependency. */ | |
542d6675 | 7321 | |
800eeca4 JW |
7322 | static int |
7323 | depends_on (depind, idesc) | |
542d6675 KH |
7324 | int depind; |
7325 | struct ia64_opcode *idesc; | |
800eeca4 JW |
7326 | { |
7327 | int i; | |
7328 | const struct ia64_opcode_dependency *dep = idesc->dependencies; | |
542d6675 | 7329 | for (i = 0; i < dep->nchks; i++) |
800eeca4 | 7330 | { |
542d6675 KH |
7331 | if (depind == DEP (dep->chks[i])) |
7332 | return i; | |
800eeca4 JW |
7333 | } |
7334 | return -1; | |
7335 | } | |
7336 | ||
7337 | /* Determine a set of specific resources used for a particular resource | |
7338 | class. Returns the number of specific resources identified For those | |
7339 | cases which are not determinable statically, the resource returned is | |
197865e8 | 7340 | marked nonspecific. |
800eeca4 JW |
7341 | |
7342 | Meanings of value in 'NOTE': | |
7343 | 1) only read/write when the register number is explicitly encoded in the | |
7344 | insn. | |
7345 | 2) only read CFM when accessing a rotating GR, FR, or PR. mov pr only | |
197865e8 | 7346 | accesses CFM when qualifying predicate is in the rotating region. |
800eeca4 JW |
7347 | 3) general register value is used to specify an indirect register; not |
7348 | determinable statically. | |
7349 | 4) only read the given resource when bits 7:0 of the indirect index | |
7350 | register value does not match the register number of the resource; not | |
7351 | determinable statically. | |
7352 | 5) all rules are implementation specific. | |
7353 | 6) only when both the index specified by the reader and the index specified | |
7354 | by the writer have the same value in bits 63:61; not determinable | |
197865e8 | 7355 | statically. |
800eeca4 | 7356 | 7) only access the specified resource when the corresponding mask bit is |
197865e8 | 7357 | set |
800eeca4 JW |
7358 | 8) PSR.dfh is only read when these insns reference FR32-127. PSR.dfl is |
7359 | only read when these insns reference FR2-31 | |
7360 | 9) PSR.mfl is only written when these insns write FR2-31. PSR.mfh is only | |
7361 | written when these insns write FR32-127 | |
7362 | 10) The PSR.bn bit is only accessed when one of GR16-31 is specified in the | |
7363 | instruction | |
7364 | 11) The target predicates are written independently of PR[qp], but source | |
7365 | registers are only read if PR[qp] is true. Since the state of PR[qp] | |
7366 | cannot statically be determined, all source registers are marked used. | |
7367 | 12) This insn only reads the specified predicate register when that | |
7368 | register is the PR[qp]. | |
7369 | 13) This reference to ld-c only applies to teh GR whose value is loaded | |
197865e8 | 7370 | with data returned from memory, not the post-incremented address register. |
800eeca4 JW |
7371 | 14) The RSE resource includes the implementation-specific RSE internal |
7372 | state resources. At least one (and possibly more) of these resources are | |
7373 | read by each instruction listed in IC:rse-readers. At least one (and | |
7374 | possibly more) of these resources are written by each insn listed in | |
197865e8 | 7375 | IC:rse-writers. |
800eeca4 | 7376 | 15+16) Represents reserved instructions, which the assembler does not |
197865e8 | 7377 | generate. |
800eeca4 JW |
7378 | |
7379 | Memory resources (i.e. locations in memory) are *not* marked or tracked by | |
7380 | this code; there are no dependency violations based on memory access. | |
800eeca4 JW |
7381 | */ |
7382 | ||
7383 | #define MAX_SPECS 256 | |
7384 | #define DV_CHK 1 | |
7385 | #define DV_REG 0 | |
7386 | ||
7387 | static int | |
7388 | specify_resource (dep, idesc, type, specs, note, path) | |
542d6675 KH |
7389 | const struct ia64_dependency *dep; |
7390 | struct ia64_opcode *idesc; | |
7391 | int type; /* is this a DV chk or a DV reg? */ | |
7392 | struct rsrc specs[MAX_SPECS]; /* returned specific resources */ | |
7393 | int note; /* resource note for this insn's usage */ | |
7394 | int path; /* which execution path to examine */ | |
800eeca4 JW |
7395 | { |
7396 | int count = 0; | |
7397 | int i; | |
7398 | int rsrc_write = 0; | |
7399 | struct rsrc tmpl; | |
197865e8 | 7400 | |
800eeca4 JW |
7401 | if (dep->mode == IA64_DV_WAW |
7402 | || (dep->mode == IA64_DV_RAW && type == DV_REG) | |
7403 | || (dep->mode == IA64_DV_WAR && type == DV_CHK)) | |
7404 | rsrc_write = 1; | |
7405 | ||
7406 | /* template for any resources we identify */ | |
7407 | tmpl.dependency = dep; | |
7408 | tmpl.note = note; | |
7409 | tmpl.insn_srlz = tmpl.data_srlz = 0; | |
7410 | tmpl.qp_regno = CURR_SLOT.qp_regno; | |
7411 | tmpl.link_to_qp_branch = 1; | |
7412 | tmpl.mem_offset.hint = 0; | |
7413 | tmpl.specific = 1; | |
7414 | tmpl.index = 0; | |
7484b8e6 | 7415 | tmpl.cmp_type = CMP_NONE; |
800eeca4 JW |
7416 | |
7417 | #define UNHANDLED \ | |
7418 | as_warn (_("Unhandled dependency %s for %s (%s), note %d"), \ | |
7419 | dep->name, idesc->name, (rsrc_write?"write":"read"), note) | |
7420 | #define KNOWN(REG) (gr_values[REG].known && gr_values[REG].path >= path) | |
7421 | ||
7422 | /* we don't need to track these */ | |
7423 | if (dep->semantics == IA64_DVS_NONE) | |
7424 | return 0; | |
7425 | ||
7426 | switch (dep->specifier) | |
7427 | { | |
7428 | case IA64_RS_AR_K: | |
7429 | if (note == 1) | |
542d6675 KH |
7430 | { |
7431 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7432 | { | |
7433 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7434 | if (regno >= 0 && regno <= 7) | |
7435 | { | |
7436 | specs[count] = tmpl; | |
7437 | specs[count++].index = regno; | |
7438 | } | |
7439 | } | |
7440 | } | |
800eeca4 | 7441 | else if (note == 0) |
542d6675 KH |
7442 | { |
7443 | for (i = 0; i < 8; i++) | |
7444 | { | |
7445 | specs[count] = tmpl; | |
7446 | specs[count++].index = i; | |
7447 | } | |
7448 | } | |
800eeca4 | 7449 | else |
542d6675 KH |
7450 | { |
7451 | UNHANDLED; | |
7452 | } | |
800eeca4 JW |
7453 | break; |
7454 | ||
7455 | case IA64_RS_AR_UNAT: | |
7456 | /* This is a mov =AR or mov AR= instruction. */ | |
7457 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7458 | { | |
7459 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7460 | if (regno == AR_UNAT) | |
7461 | { | |
7462 | specs[count++] = tmpl; | |
7463 | } | |
7464 | } | |
7465 | else | |
7466 | { | |
7467 | /* This is a spill/fill, or other instruction that modifies the | |
7468 | unat register. */ | |
7469 | ||
7470 | /* Unless we can determine the specific bits used, mark the whole | |
7471 | thing; bits 8:3 of the memory address indicate the bit used in | |
7472 | UNAT. The .mem.offset hint may be used to eliminate a small | |
7473 | subset of conflicts. */ | |
7474 | specs[count] = tmpl; | |
7475 | if (md.mem_offset.hint) | |
7476 | { | |
542d6675 KH |
7477 | if (md.debug_dv) |
7478 | fprintf (stderr, " Using hint for spill/fill\n"); | |
7479 | /* The index isn't actually used, just set it to something | |
7480 | approximating the bit index. */ | |
800eeca4 JW |
7481 | specs[count].index = (md.mem_offset.offset >> 3) & 0x3F; |
7482 | specs[count].mem_offset.hint = 1; | |
7483 | specs[count].mem_offset.offset = md.mem_offset.offset; | |
7484 | specs[count++].mem_offset.base = md.mem_offset.base; | |
7485 | } | |
7486 | else | |
7487 | { | |
7488 | specs[count++].specific = 0; | |
7489 | } | |
7490 | } | |
7491 | break; | |
7492 | ||
7493 | case IA64_RS_AR: | |
7494 | if (note == 1) | |
542d6675 KH |
7495 | { |
7496 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7497 | { | |
7498 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7499 | if ((regno >= 8 && regno <= 15) | |
7500 | || (regno >= 20 && regno <= 23) | |
7501 | || (regno >= 31 && regno <= 39) | |
7502 | || (regno >= 41 && regno <= 47) | |
7503 | || (regno >= 67 && regno <= 111)) | |
7504 | { | |
7505 | specs[count] = tmpl; | |
7506 | specs[count++].index = regno; | |
7507 | } | |
7508 | } | |
7509 | } | |
800eeca4 | 7510 | else |
542d6675 KH |
7511 | { |
7512 | UNHANDLED; | |
7513 | } | |
800eeca4 JW |
7514 | break; |
7515 | ||
7516 | case IA64_RS_ARb: | |
7517 | if (note == 1) | |
542d6675 KH |
7518 | { |
7519 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
7520 | { | |
7521 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
7522 | if ((regno >= 48 && regno <= 63) | |
7523 | || (regno >= 112 && regno <= 127)) | |
7524 | { | |
7525 | specs[count] = tmpl; | |
7526 | specs[count++].index = regno; | |
7527 | } | |
7528 | } | |
7529 | } | |
800eeca4 | 7530 | else if (note == 0) |
542d6675 KH |
7531 | { |
7532 | for (i = 48; i < 64; i++) | |
7533 | { | |
7534 | specs[count] = tmpl; | |
7535 | specs[count++].index = i; | |
7536 | } | |
7537 | for (i = 112; i < 128; i++) | |
7538 | { | |
7539 | specs[count] = tmpl; | |
7540 | specs[count++].index = i; | |
7541 | } | |
7542 | } | |
197865e8 | 7543 | else |
542d6675 KH |
7544 | { |
7545 | UNHANDLED; | |
7546 | } | |
800eeca4 JW |
7547 | break; |
7548 | ||
7549 | case IA64_RS_BR: | |
7550 | if (note != 1) | |
542d6675 KH |
7551 | { |
7552 | UNHANDLED; | |
7553 | } | |
800eeca4 | 7554 | else |
542d6675 KH |
7555 | { |
7556 | if (rsrc_write) | |
7557 | { | |
7558 | for (i = 0; i < idesc->num_outputs; i++) | |
7559 | if (idesc->operands[i] == IA64_OPND_B1 | |
7560 | || idesc->operands[i] == IA64_OPND_B2) | |
7561 | { | |
7562 | specs[count] = tmpl; | |
7563 | specs[count++].index = | |
7564 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
7565 | } | |
7566 | } | |
7567 | else | |
7568 | { | |
40449e9f | 7569 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) |
542d6675 KH |
7570 | if (idesc->operands[i] == IA64_OPND_B1 |
7571 | || idesc->operands[i] == IA64_OPND_B2) | |
7572 | { | |
7573 | specs[count] = tmpl; | |
7574 | specs[count++].index = | |
7575 | CURR_SLOT.opnd[i].X_add_number - REG_BR; | |
7576 | } | |
7577 | } | |
7578 | } | |
800eeca4 JW |
7579 | break; |
7580 | ||
7581 | case IA64_RS_CPUID: /* four or more registers */ | |
7582 | if (note == 3) | |
542d6675 KH |
7583 | { |
7584 | if (idesc->operands[!rsrc_write] == IA64_OPND_CPUID_R3) | |
7585 | { | |
7586 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7587 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7588 | && KNOWN (regno)) | |
7589 | { | |
7590 | specs[count] = tmpl; | |
7591 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7592 | } | |
7593 | else | |
7594 | { | |
7595 | specs[count] = tmpl; | |
7596 | specs[count++].specific = 0; | |
7597 | } | |
7598 | } | |
7599 | } | |
800eeca4 | 7600 | else |
542d6675 KH |
7601 | { |
7602 | UNHANDLED; | |
7603 | } | |
800eeca4 JW |
7604 | break; |
7605 | ||
7606 | case IA64_RS_DBR: /* four or more registers */ | |
7607 | if (note == 3) | |
542d6675 KH |
7608 | { |
7609 | if (idesc->operands[!rsrc_write] == IA64_OPND_DBR_R3) | |
7610 | { | |
7611 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7612 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7613 | && KNOWN (regno)) | |
7614 | { | |
7615 | specs[count] = tmpl; | |
7616 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7617 | } | |
7618 | else | |
7619 | { | |
7620 | specs[count] = tmpl; | |
7621 | specs[count++].specific = 0; | |
7622 | } | |
7623 | } | |
7624 | } | |
800eeca4 | 7625 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
7626 | { |
7627 | specs[count] = tmpl; | |
7628 | specs[count++].specific = 0; | |
7629 | } | |
800eeca4 | 7630 | else |
542d6675 KH |
7631 | { |
7632 | UNHANDLED; | |
7633 | } | |
800eeca4 JW |
7634 | break; |
7635 | ||
7636 | case IA64_RS_IBR: /* four or more registers */ | |
7637 | if (note == 3) | |
542d6675 KH |
7638 | { |
7639 | if (idesc->operands[!rsrc_write] == IA64_OPND_IBR_R3) | |
7640 | { | |
7641 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7642 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7643 | && KNOWN (regno)) | |
7644 | { | |
7645 | specs[count] = tmpl; | |
7646 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7647 | } | |
7648 | else | |
7649 | { | |
7650 | specs[count] = tmpl; | |
7651 | specs[count++].specific = 0; | |
7652 | } | |
7653 | } | |
7654 | } | |
800eeca4 | 7655 | else |
542d6675 KH |
7656 | { |
7657 | UNHANDLED; | |
7658 | } | |
800eeca4 JW |
7659 | break; |
7660 | ||
7661 | case IA64_RS_MSR: | |
7662 | if (note == 5) | |
7663 | { | |
7664 | /* These are implementation specific. Force all references to | |
7665 | conflict with all other references. */ | |
7666 | specs[count] = tmpl; | |
7667 | specs[count++].specific = 0; | |
7668 | } | |
7669 | else | |
7670 | { | |
7671 | UNHANDLED; | |
7672 | } | |
7673 | break; | |
7674 | ||
7675 | case IA64_RS_PKR: /* 16 or more registers */ | |
7676 | if (note == 3 || note == 4) | |
542d6675 KH |
7677 | { |
7678 | if (idesc->operands[!rsrc_write] == IA64_OPND_PKR_R3) | |
7679 | { | |
7680 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7681 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7682 | && KNOWN (regno)) | |
7683 | { | |
7684 | if (note == 3) | |
7685 | { | |
7686 | specs[count] = tmpl; | |
7687 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7688 | } | |
7689 | else | |
7690 | for (i = 0; i < NELEMS (gr_values); i++) | |
7691 | { | |
7692 | /* Uses all registers *except* the one in R3. */ | |
2434f565 | 7693 | if ((unsigned)i != (gr_values[regno].value & 0xFF)) |
542d6675 KH |
7694 | { |
7695 | specs[count] = tmpl; | |
7696 | specs[count++].index = i; | |
7697 | } | |
7698 | } | |
7699 | } | |
7700 | else | |
7701 | { | |
7702 | specs[count] = tmpl; | |
7703 | specs[count++].specific = 0; | |
7704 | } | |
7705 | } | |
7706 | } | |
7707 | else if (note == 0) | |
7708 | { | |
7709 | /* probe et al. */ | |
7710 | specs[count] = tmpl; | |
7711 | specs[count++].specific = 0; | |
7712 | } | |
7713 | break; | |
7714 | ||
7715 | case IA64_RS_PMC: /* four or more registers */ | |
7716 | if (note == 3) | |
7717 | { | |
7718 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMC_R3 | |
7719 | || (!rsrc_write && idesc->operands[1] == IA64_OPND_PMD_R3)) | |
7720 | ||
7721 | { | |
7722 | int index = ((idesc->operands[1] == IA64_OPND_R3 && !rsrc_write) | |
7723 | ? 1 : !rsrc_write); | |
7724 | int regno = CURR_SLOT.opnd[index].X_add_number - REG_GR; | |
7725 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7726 | && KNOWN (regno)) | |
7727 | { | |
7728 | specs[count] = tmpl; | |
7729 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7730 | } | |
7731 | else | |
7732 | { | |
7733 | specs[count] = tmpl; | |
7734 | specs[count++].specific = 0; | |
7735 | } | |
7736 | } | |
7737 | } | |
7738 | else | |
7739 | { | |
7740 | UNHANDLED; | |
7741 | } | |
800eeca4 JW |
7742 | break; |
7743 | ||
7744 | case IA64_RS_PMD: /* four or more registers */ | |
7745 | if (note == 3) | |
542d6675 KH |
7746 | { |
7747 | if (idesc->operands[!rsrc_write] == IA64_OPND_PMD_R3) | |
7748 | { | |
7749 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7750 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7751 | && KNOWN (regno)) | |
7752 | { | |
7753 | specs[count] = tmpl; | |
7754 | specs[count++].index = gr_values[regno].value & 0xFF; | |
7755 | } | |
7756 | else | |
7757 | { | |
7758 | specs[count] = tmpl; | |
7759 | specs[count++].specific = 0; | |
7760 | } | |
7761 | } | |
7762 | } | |
800eeca4 | 7763 | else |
542d6675 KH |
7764 | { |
7765 | UNHANDLED; | |
7766 | } | |
800eeca4 JW |
7767 | break; |
7768 | ||
7769 | case IA64_RS_RR: /* eight registers */ | |
7770 | if (note == 6) | |
542d6675 KH |
7771 | { |
7772 | if (idesc->operands[!rsrc_write] == IA64_OPND_RR_R3) | |
7773 | { | |
7774 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_GR; | |
7775 | if (regno >= 0 && regno < NELEMS (gr_values) | |
7776 | && KNOWN (regno)) | |
7777 | { | |
7778 | specs[count] = tmpl; | |
7779 | specs[count++].index = (gr_values[regno].value >> 61) & 0x7; | |
7780 | } | |
7781 | else | |
7782 | { | |
7783 | specs[count] = tmpl; | |
7784 | specs[count++].specific = 0; | |
7785 | } | |
7786 | } | |
7787 | } | |
800eeca4 | 7788 | else if (note == 0 && !rsrc_write) |
542d6675 KH |
7789 | { |
7790 | specs[count] = tmpl; | |
7791 | specs[count++].specific = 0; | |
7792 | } | |
197865e8 | 7793 | else |
542d6675 KH |
7794 | { |
7795 | UNHANDLED; | |
7796 | } | |
800eeca4 JW |
7797 | break; |
7798 | ||
7799 | case IA64_RS_CR_IRR: | |
197865e8 | 7800 | if (note == 0) |
542d6675 KH |
7801 | { |
7802 | /* handle mov-from-CR-IVR; it's a read that writes CR[IRR] */ | |
7803 | int regno = CURR_SLOT.opnd[1].X_add_number - REG_CR; | |
7804 | if (rsrc_write | |
7805 | && idesc->operands[1] == IA64_OPND_CR3 | |
7806 | && regno == CR_IVR) | |
7807 | { | |
7808 | for (i = 0; i < 4; i++) | |
7809 | { | |
7810 | specs[count] = tmpl; | |
7811 | specs[count++].index = CR_IRR0 + i; | |
7812 | } | |
7813 | } | |
7814 | } | |
800eeca4 | 7815 | else if (note == 1) |
542d6675 KH |
7816 | { |
7817 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7818 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7819 | && regno >= CR_IRR0 | |
7820 | && regno <= CR_IRR3) | |
7821 | { | |
7822 | specs[count] = tmpl; | |
7823 | specs[count++].index = regno; | |
7824 | } | |
7825 | } | |
800eeca4 | 7826 | else |
542d6675 KH |
7827 | { |
7828 | UNHANDLED; | |
7829 | } | |
800eeca4 JW |
7830 | break; |
7831 | ||
7832 | case IA64_RS_CR_LRR: | |
7833 | if (note != 1) | |
542d6675 KH |
7834 | { |
7835 | UNHANDLED; | |
7836 | } | |
197865e8 | 7837 | else |
542d6675 KH |
7838 | { |
7839 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7840 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3 | |
7841 | && (regno == CR_LRR0 || regno == CR_LRR1)) | |
7842 | { | |
7843 | specs[count] = tmpl; | |
7844 | specs[count++].index = regno; | |
7845 | } | |
7846 | } | |
800eeca4 JW |
7847 | break; |
7848 | ||
7849 | case IA64_RS_CR: | |
7850 | if (note == 1) | |
542d6675 KH |
7851 | { |
7852 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
7853 | { | |
7854 | specs[count] = tmpl; | |
7855 | specs[count++].index = | |
7856 | CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
7857 | } | |
7858 | } | |
800eeca4 | 7859 | else |
542d6675 KH |
7860 | { |
7861 | UNHANDLED; | |
7862 | } | |
800eeca4 JW |
7863 | break; |
7864 | ||
7865 | case IA64_RS_FR: | |
7866 | case IA64_RS_FRb: | |
7867 | if (note != 1) | |
542d6675 KH |
7868 | { |
7869 | UNHANDLED; | |
7870 | } | |
800eeca4 | 7871 | else if (rsrc_write) |
542d6675 KH |
7872 | { |
7873 | if (dep->specifier == IA64_RS_FRb | |
7874 | && idesc->operands[0] == IA64_OPND_F1) | |
7875 | { | |
7876 | specs[count] = tmpl; | |
7877 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_FR; | |
7878 | } | |
7879 | } | |
800eeca4 | 7880 | else |
542d6675 KH |
7881 | { |
7882 | for (i = idesc->num_outputs; i < NELEMS (idesc->operands); i++) | |
7883 | { | |
7884 | if (idesc->operands[i] == IA64_OPND_F2 | |
7885 | || idesc->operands[i] == IA64_OPND_F3 | |
7886 | || idesc->operands[i] == IA64_OPND_F4) | |
7887 | { | |
7888 | specs[count] = tmpl; | |
7889 | specs[count++].index = | |
7890 | CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
7891 | } | |
7892 | } | |
7893 | } | |
800eeca4 JW |
7894 | break; |
7895 | ||
7896 | case IA64_RS_GR: | |
7897 | if (note == 13) | |
542d6675 KH |
7898 | { |
7899 | /* This reference applies only to the GR whose value is loaded with | |
7900 | data returned from memory. */ | |
7901 | specs[count] = tmpl; | |
7902 | specs[count++].index = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
7903 | } | |
800eeca4 | 7904 | else if (note == 1) |
542d6675 KH |
7905 | { |
7906 | if (rsrc_write) | |
7907 | { | |
7908 | for (i = 0; i < idesc->num_outputs; i++) | |
50b81f19 JW |
7909 | if (idesc->operands[i] == IA64_OPND_R1 |
7910 | || idesc->operands[i] == IA64_OPND_R2 | |
7911 | || idesc->operands[i] == IA64_OPND_R3) | |
7912 | { | |
7913 | specs[count] = tmpl; | |
197865e8 | 7914 | specs[count++].index = |
50b81f19 JW |
7915 | CURR_SLOT.opnd[i].X_add_number - REG_GR; |
7916 | } | |
7917 | if (idesc->flags & IA64_OPCODE_POSTINC) | |
7918 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7919 | if (idesc->operands[i] == IA64_OPND_MR3) | |
7920 | { | |
7921 | specs[count] = tmpl; | |
7922 | specs[count++].index = | |
7923 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7924 | } | |
542d6675 KH |
7925 | } |
7926 | else | |
7927 | { | |
7928 | /* Look for anything that reads a GR. */ | |
7929 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
7930 | { | |
7931 | if (idesc->operands[i] == IA64_OPND_MR3 | |
7932 | || idesc->operands[i] == IA64_OPND_CPUID_R3 | |
7933 | || idesc->operands[i] == IA64_OPND_DBR_R3 | |
7934 | || idesc->operands[i] == IA64_OPND_IBR_R3 | |
800eeca4 | 7935 | || idesc->operands[i] == IA64_OPND_MSR_R3 |
542d6675 KH |
7936 | || idesc->operands[i] == IA64_OPND_PKR_R3 |
7937 | || idesc->operands[i] == IA64_OPND_PMC_R3 | |
7938 | || idesc->operands[i] == IA64_OPND_PMD_R3 | |
7939 | || idesc->operands[i] == IA64_OPND_RR_R3 | |
7940 | || ((i >= idesc->num_outputs) | |
7941 | && (idesc->operands[i] == IA64_OPND_R1 | |
7942 | || idesc->operands[i] == IA64_OPND_R2 | |
7943 | || idesc->operands[i] == IA64_OPND_R3 | |
50b81f19 JW |
7944 | /* addl source register. */ |
7945 | || idesc->operands[i] == IA64_OPND_R3_2))) | |
542d6675 KH |
7946 | { |
7947 | specs[count] = tmpl; | |
7948 | specs[count++].index = | |
7949 | CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
7950 | } | |
7951 | } | |
7952 | } | |
7953 | } | |
197865e8 | 7954 | else |
542d6675 KH |
7955 | { |
7956 | UNHANDLED; | |
7957 | } | |
800eeca4 JW |
7958 | break; |
7959 | ||
139368c9 JW |
7960 | /* This is the same as IA64_RS_PRr, except that the register range is |
7961 | from 1 - 15, and there are no rotating register reads/writes here. */ | |
800eeca4 JW |
7962 | case IA64_RS_PR: |
7963 | if (note == 0) | |
542d6675 | 7964 | { |
139368c9 | 7965 | for (i = 1; i < 16; i++) |
542d6675 | 7966 | { |
139368c9 JW |
7967 | specs[count] = tmpl; |
7968 | specs[count++].index = i; | |
7969 | } | |
7970 | } | |
7971 | else if (note == 7) | |
7972 | { | |
7973 | valueT mask = 0; | |
7974 | /* Mark only those registers indicated by the mask. */ | |
7975 | if (rsrc_write) | |
7976 | { | |
7977 | mask = CURR_SLOT.opnd[2].X_add_number; | |
7978 | for (i = 1; i < 16; i++) | |
7979 | if (mask & ((valueT) 1 << i)) | |
7980 | { | |
7981 | specs[count] = tmpl; | |
7982 | specs[count++].index = i; | |
7983 | } | |
7984 | } | |
7985 | else | |
7986 | { | |
7987 | UNHANDLED; | |
7988 | } | |
7989 | } | |
7990 | else if (note == 11) /* note 11 implies note 1 as well */ | |
7991 | { | |
7992 | if (rsrc_write) | |
7993 | { | |
7994 | for (i = 0; i < idesc->num_outputs; i++) | |
7995 | { | |
7996 | if (idesc->operands[i] == IA64_OPND_P1 | |
7997 | || idesc->operands[i] == IA64_OPND_P2) | |
7998 | { | |
7999 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8000 | if (regno >= 1 && regno < 16) | |
8001 | { | |
8002 | specs[count] = tmpl; | |
8003 | specs[count++].index = regno; | |
8004 | } | |
8005 | } | |
8006 | } | |
8007 | } | |
8008 | else | |
8009 | { | |
8010 | UNHANDLED; | |
8011 | } | |
8012 | } | |
8013 | else if (note == 12) | |
8014 | { | |
8015 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) | |
8016 | { | |
8017 | specs[count] = tmpl; | |
8018 | specs[count++].index = CURR_SLOT.qp_regno; | |
8019 | } | |
8020 | } | |
8021 | else if (note == 1) | |
8022 | { | |
8023 | if (rsrc_write) | |
8024 | { | |
8025 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
8026 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
07726851 KH |
8027 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
8028 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; | |
139368c9 JW |
8029 | |
8030 | if ((idesc->operands[0] == IA64_OPND_P1 | |
8031 | || idesc->operands[0] == IA64_OPND_P2) | |
8032 | && p1 >= 1 && p1 < 16) | |
542d6675 KH |
8033 | { |
8034 | specs[count] = tmpl; | |
139368c9 JW |
8035 | specs[count].cmp_type = |
8036 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); | |
8037 | specs[count++].index = p1; | |
8038 | } | |
8039 | if ((idesc->operands[1] == IA64_OPND_P1 | |
8040 | || idesc->operands[1] == IA64_OPND_P2) | |
8041 | && p2 >= 1 && p2 < 16) | |
8042 | { | |
8043 | specs[count] = tmpl; | |
8044 | specs[count].cmp_type = | |
8045 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); | |
8046 | specs[count++].index = p2; | |
542d6675 KH |
8047 | } |
8048 | } | |
8049 | else | |
8050 | { | |
139368c9 | 8051 | if (CURR_SLOT.qp_regno >= 1 && CURR_SLOT.qp_regno < 16) |
542d6675 KH |
8052 | { |
8053 | specs[count] = tmpl; | |
139368c9 JW |
8054 | specs[count++].index = CURR_SLOT.qp_regno; |
8055 | } | |
8056 | if (idesc->operands[1] == IA64_OPND_PR) | |
8057 | { | |
8058 | for (i = 1; i < 16; i++) | |
8059 | { | |
8060 | specs[count] = tmpl; | |
8061 | specs[count++].index = i; | |
8062 | } | |
542d6675 KH |
8063 | } |
8064 | } | |
8065 | } | |
139368c9 JW |
8066 | else |
8067 | { | |
8068 | UNHANDLED; | |
8069 | } | |
8070 | break; | |
8071 | ||
8072 | /* This is the general case for PRs. IA64_RS_PR and IA64_RS_PR63 are | |
8073 | simplified cases of this. */ | |
8074 | case IA64_RS_PRr: | |
8075 | if (note == 0) | |
8076 | { | |
8077 | for (i = 16; i < 63; i++) | |
8078 | { | |
8079 | specs[count] = tmpl; | |
8080 | specs[count++].index = i; | |
8081 | } | |
8082 | } | |
800eeca4 | 8083 | else if (note == 7) |
542d6675 KH |
8084 | { |
8085 | valueT mask = 0; | |
8086 | /* Mark only those registers indicated by the mask. */ | |
8087 | if (rsrc_write | |
8088 | && idesc->operands[0] == IA64_OPND_PR) | |
8089 | { | |
8090 | mask = CURR_SLOT.opnd[2].X_add_number; | |
40449e9f | 8091 | if (mask & ((valueT) 1 << 16)) |
139368c9 JW |
8092 | for (i = 16; i < 63; i++) |
8093 | { | |
8094 | specs[count] = tmpl; | |
8095 | specs[count++].index = i; | |
8096 | } | |
542d6675 KH |
8097 | } |
8098 | else if (rsrc_write | |
8099 | && idesc->operands[0] == IA64_OPND_PR_ROT) | |
8100 | { | |
8101 | for (i = 16; i < 63; i++) | |
8102 | { | |
8103 | specs[count] = tmpl; | |
8104 | specs[count++].index = i; | |
8105 | } | |
8106 | } | |
8107 | else | |
8108 | { | |
8109 | UNHANDLED; | |
8110 | } | |
8111 | } | |
800eeca4 | 8112 | else if (note == 11) /* note 11 implies note 1 as well */ |
542d6675 KH |
8113 | { |
8114 | if (rsrc_write) | |
8115 | { | |
8116 | for (i = 0; i < idesc->num_outputs; i++) | |
8117 | { | |
8118 | if (idesc->operands[i] == IA64_OPND_P1 | |
8119 | || idesc->operands[i] == IA64_OPND_P2) | |
8120 | { | |
8121 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
139368c9 | 8122 | if (regno >= 16 && regno < 63) |
542d6675 KH |
8123 | { |
8124 | specs[count] = tmpl; | |
8125 | specs[count++].index = regno; | |
8126 | } | |
8127 | } | |
8128 | } | |
8129 | } | |
8130 | else | |
8131 | { | |
8132 | UNHANDLED; | |
8133 | } | |
8134 | } | |
800eeca4 | 8135 | else if (note == 12) |
542d6675 | 8136 | { |
139368c9 | 8137 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
8138 | { |
8139 | specs[count] = tmpl; | |
8140 | specs[count++].index = CURR_SLOT.qp_regno; | |
8141 | } | |
8142 | } | |
800eeca4 | 8143 | else if (note == 1) |
542d6675 KH |
8144 | { |
8145 | if (rsrc_write) | |
8146 | { | |
8147 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
8148 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
07726851 KH |
8149 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
8150 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; | |
7484b8e6 | 8151 | |
542d6675 KH |
8152 | if ((idesc->operands[0] == IA64_OPND_P1 |
8153 | || idesc->operands[0] == IA64_OPND_P2) | |
139368c9 | 8154 | && p1 >= 16 && p1 < 63) |
542d6675 KH |
8155 | { |
8156 | specs[count] = tmpl; | |
4a4f25cf | 8157 | specs[count].cmp_type = |
7484b8e6 | 8158 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
542d6675 KH |
8159 | specs[count++].index = p1; |
8160 | } | |
8161 | if ((idesc->operands[1] == IA64_OPND_P1 | |
8162 | || idesc->operands[1] == IA64_OPND_P2) | |
139368c9 | 8163 | && p2 >= 16 && p2 < 63) |
542d6675 KH |
8164 | { |
8165 | specs[count] = tmpl; | |
4a4f25cf | 8166 | specs[count].cmp_type = |
7484b8e6 | 8167 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
542d6675 KH |
8168 | specs[count++].index = p2; |
8169 | } | |
8170 | } | |
8171 | else | |
8172 | { | |
139368c9 | 8173 | if (CURR_SLOT.qp_regno >= 16 && CURR_SLOT.qp_regno < 63) |
542d6675 KH |
8174 | { |
8175 | specs[count] = tmpl; | |
8176 | specs[count++].index = CURR_SLOT.qp_regno; | |
8177 | } | |
8178 | if (idesc->operands[1] == IA64_OPND_PR) | |
8179 | { | |
139368c9 | 8180 | for (i = 16; i < 63; i++) |
542d6675 KH |
8181 | { |
8182 | specs[count] = tmpl; | |
8183 | specs[count++].index = i; | |
8184 | } | |
8185 | } | |
8186 | } | |
8187 | } | |
197865e8 | 8188 | else |
542d6675 KH |
8189 | { |
8190 | UNHANDLED; | |
8191 | } | |
800eeca4 JW |
8192 | break; |
8193 | ||
8194 | case IA64_RS_PSR: | |
197865e8 | 8195 | /* Verify that the instruction is using the PSR bit indicated in |
542d6675 | 8196 | dep->regindex. */ |
800eeca4 | 8197 | if (note == 0) |
542d6675 KH |
8198 | { |
8199 | if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_UM) | |
8200 | { | |
8201 | if (dep->regindex < 6) | |
8202 | { | |
8203 | specs[count++] = tmpl; | |
8204 | } | |
8205 | } | |
8206 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR) | |
8207 | { | |
8208 | if (dep->regindex < 32 | |
8209 | || dep->regindex == 35 | |
8210 | || dep->regindex == 36 | |
8211 | || (!rsrc_write && dep->regindex == PSR_CPL)) | |
8212 | { | |
8213 | specs[count++] = tmpl; | |
8214 | } | |
8215 | } | |
8216 | else if (idesc->operands[!rsrc_write] == IA64_OPND_PSR_L) | |
8217 | { | |
8218 | if (dep->regindex < 32 | |
8219 | || dep->regindex == 35 | |
8220 | || dep->regindex == 36 | |
8221 | || (rsrc_write && dep->regindex == PSR_CPL)) | |
8222 | { | |
8223 | specs[count++] = tmpl; | |
8224 | } | |
8225 | } | |
8226 | else | |
8227 | { | |
8228 | /* Several PSR bits have very specific dependencies. */ | |
8229 | switch (dep->regindex) | |
8230 | { | |
8231 | default: | |
8232 | specs[count++] = tmpl; | |
8233 | break; | |
8234 | case PSR_IC: | |
8235 | if (rsrc_write) | |
8236 | { | |
8237 | specs[count++] = tmpl; | |
8238 | } | |
8239 | else | |
8240 | { | |
8241 | /* Only certain CR accesses use PSR.ic */ | |
8242 | if (idesc->operands[0] == IA64_OPND_CR3 | |
8243 | || idesc->operands[1] == IA64_OPND_CR3) | |
8244 | { | |
8245 | int index = | |
8246 | ((idesc->operands[0] == IA64_OPND_CR3) | |
8247 | ? 0 : 1); | |
8248 | int regno = | |
8249 | CURR_SLOT.opnd[index].X_add_number - REG_CR; | |
8250 | ||
8251 | switch (regno) | |
8252 | { | |
8253 | default: | |
8254 | break; | |
8255 | case CR_ITIR: | |
8256 | case CR_IFS: | |
8257 | case CR_IIM: | |
8258 | case CR_IIP: | |
8259 | case CR_IPSR: | |
8260 | case CR_ISR: | |
8261 | case CR_IFA: | |
8262 | case CR_IHA: | |
8263 | case CR_IIPA: | |
8264 | specs[count++] = tmpl; | |
8265 | break; | |
8266 | } | |
8267 | } | |
8268 | } | |
8269 | break; | |
8270 | case PSR_CPL: | |
8271 | if (rsrc_write) | |
8272 | { | |
8273 | specs[count++] = tmpl; | |
8274 | } | |
8275 | else | |
8276 | { | |
8277 | /* Only some AR accesses use cpl */ | |
8278 | if (idesc->operands[0] == IA64_OPND_AR3 | |
8279 | || idesc->operands[1] == IA64_OPND_AR3) | |
8280 | { | |
8281 | int index = | |
8282 | ((idesc->operands[0] == IA64_OPND_AR3) | |
8283 | ? 0 : 1); | |
8284 | int regno = | |
8285 | CURR_SLOT.opnd[index].X_add_number - REG_AR; | |
8286 | ||
8287 | if (regno == AR_ITC | |
8288 | || (index == 0 | |
8289 | && (regno == AR_ITC | |
8290 | || regno == AR_RSC | |
8291 | || (regno >= AR_K0 | |
8292 | && regno <= AR_K7)))) | |
8293 | { | |
8294 | specs[count++] = tmpl; | |
8295 | } | |
8296 | } | |
8297 | else | |
8298 | { | |
8299 | specs[count++] = tmpl; | |
8300 | } | |
8301 | break; | |
8302 | } | |
8303 | } | |
8304 | } | |
8305 | } | |
800eeca4 | 8306 | else if (note == 7) |
542d6675 KH |
8307 | { |
8308 | valueT mask = 0; | |
8309 | if (idesc->operands[0] == IA64_OPND_IMMU24) | |
8310 | { | |
8311 | mask = CURR_SLOT.opnd[0].X_add_number; | |
8312 | } | |
8313 | else | |
8314 | { | |
8315 | UNHANDLED; | |
8316 | } | |
8317 | if (mask & ((valueT) 1 << dep->regindex)) | |
8318 | { | |
8319 | specs[count++] = tmpl; | |
8320 | } | |
8321 | } | |
800eeca4 | 8322 | else if (note == 8) |
542d6675 KH |
8323 | { |
8324 | int min = dep->regindex == PSR_DFL ? 2 : 32; | |
8325 | int max = dep->regindex == PSR_DFL ? 31 : 127; | |
8326 | /* dfh is read on FR32-127; dfl is read on FR2-31 */ | |
8327 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
8328 | { | |
8329 | if (idesc->operands[i] == IA64_OPND_F1 | |
8330 | || idesc->operands[i] == IA64_OPND_F2 | |
8331 | || idesc->operands[i] == IA64_OPND_F3 | |
8332 | || idesc->operands[i] == IA64_OPND_F4) | |
8333 | { | |
8334 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
8335 | if (reg >= min && reg <= max) | |
8336 | { | |
8337 | specs[count++] = tmpl; | |
8338 | } | |
8339 | } | |
8340 | } | |
8341 | } | |
800eeca4 | 8342 | else if (note == 9) |
542d6675 KH |
8343 | { |
8344 | int min = dep->regindex == PSR_MFL ? 2 : 32; | |
8345 | int max = dep->regindex == PSR_MFL ? 31 : 127; | |
8346 | /* mfh is read on writes to FR32-127; mfl is read on writes to | |
8347 | FR2-31 */ | |
8348 | for (i = 0; i < idesc->num_outputs; i++) | |
8349 | { | |
8350 | if (idesc->operands[i] == IA64_OPND_F1) | |
8351 | { | |
8352 | int reg = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
8353 | if (reg >= min && reg <= max) | |
8354 | { | |
8355 | specs[count++] = tmpl; | |
8356 | } | |
8357 | } | |
8358 | } | |
8359 | } | |
800eeca4 | 8360 | else if (note == 10) |
542d6675 KH |
8361 | { |
8362 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
8363 | { | |
8364 | if (idesc->operands[i] == IA64_OPND_R1 | |
8365 | || idesc->operands[i] == IA64_OPND_R2 | |
8366 | || idesc->operands[i] == IA64_OPND_R3) | |
8367 | { | |
8368 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8369 | if (regno >= 16 && regno <= 31) | |
8370 | { | |
8371 | specs[count++] = tmpl; | |
8372 | } | |
8373 | } | |
8374 | } | |
8375 | } | |
800eeca4 | 8376 | else |
542d6675 KH |
8377 | { |
8378 | UNHANDLED; | |
8379 | } | |
800eeca4 JW |
8380 | break; |
8381 | ||
8382 | case IA64_RS_AR_FPSR: | |
8383 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3) | |
542d6675 KH |
8384 | { |
8385 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
8386 | if (regno == AR_FPSR) | |
8387 | { | |
8388 | specs[count++] = tmpl; | |
8389 | } | |
8390 | } | |
800eeca4 | 8391 | else |
542d6675 KH |
8392 | { |
8393 | specs[count++] = tmpl; | |
8394 | } | |
800eeca4 JW |
8395 | break; |
8396 | ||
197865e8 | 8397 | case IA64_RS_ARX: |
800eeca4 JW |
8398 | /* Handle all AR[REG] resources */ |
8399 | if (note == 0 || note == 1) | |
542d6675 KH |
8400 | { |
8401 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_AR; | |
8402 | if (idesc->operands[!rsrc_write] == IA64_OPND_AR3 | |
8403 | && regno == dep->regindex) | |
8404 | { | |
8405 | specs[count++] = tmpl; | |
8406 | } | |
8407 | /* other AR[REG] resources may be affected by AR accesses */ | |
8408 | else if (idesc->operands[0] == IA64_OPND_AR3) | |
8409 | { | |
8410 | /* AR[] writes */ | |
8411 | regno = CURR_SLOT.opnd[0].X_add_number - REG_AR; | |
8412 | switch (dep->regindex) | |
8413 | { | |
8414 | default: | |
8415 | break; | |
8416 | case AR_BSP: | |
8417 | case AR_RNAT: | |
8418 | if (regno == AR_BSPSTORE) | |
8419 | { | |
8420 | specs[count++] = tmpl; | |
8421 | } | |
8422 | case AR_RSC: | |
8423 | if (!rsrc_write && | |
8424 | (regno == AR_BSPSTORE | |
8425 | || regno == AR_RNAT)) | |
8426 | { | |
8427 | specs[count++] = tmpl; | |
8428 | } | |
8429 | break; | |
8430 | } | |
8431 | } | |
8432 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
8433 | { | |
8434 | /* AR[] reads */ | |
8435 | regno = CURR_SLOT.opnd[1].X_add_number - REG_AR; | |
8436 | switch (dep->regindex) | |
8437 | { | |
8438 | default: | |
8439 | break; | |
8440 | case AR_RSC: | |
8441 | if (regno == AR_BSPSTORE || regno == AR_RNAT) | |
8442 | { | |
8443 | specs[count++] = tmpl; | |
8444 | } | |
8445 | break; | |
8446 | } | |
8447 | } | |
8448 | else | |
8449 | { | |
8450 | specs[count++] = tmpl; | |
8451 | } | |
8452 | } | |
800eeca4 | 8453 | else |
542d6675 KH |
8454 | { |
8455 | UNHANDLED; | |
8456 | } | |
800eeca4 JW |
8457 | break; |
8458 | ||
8459 | case IA64_RS_CRX: | |
8460 | /* Handle all CR[REG] resources */ | |
8461 | if (note == 0 || note == 1) | |
542d6675 KH |
8462 | { |
8463 | if (idesc->operands[!rsrc_write] == IA64_OPND_CR3) | |
8464 | { | |
8465 | int regno = CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_CR; | |
8466 | if (regno == dep->regindex) | |
8467 | { | |
8468 | specs[count++] = tmpl; | |
8469 | } | |
8470 | else if (!rsrc_write) | |
8471 | { | |
8472 | /* Reads from CR[IVR] affect other resources. */ | |
8473 | if (regno == CR_IVR) | |
8474 | { | |
8475 | if ((dep->regindex >= CR_IRR0 | |
8476 | && dep->regindex <= CR_IRR3) | |
8477 | || dep->regindex == CR_TPR) | |
8478 | { | |
8479 | specs[count++] = tmpl; | |
8480 | } | |
8481 | } | |
8482 | } | |
8483 | } | |
8484 | else | |
8485 | { | |
8486 | specs[count++] = tmpl; | |
8487 | } | |
8488 | } | |
800eeca4 | 8489 | else |
542d6675 KH |
8490 | { |
8491 | UNHANDLED; | |
8492 | } | |
800eeca4 JW |
8493 | break; |
8494 | ||
8495 | case IA64_RS_INSERVICE: | |
8496 | /* look for write of EOI (67) or read of IVR (65) */ | |
8497 | if ((idesc->operands[0] == IA64_OPND_CR3 | |
542d6675 KH |
8498 | && CURR_SLOT.opnd[0].X_add_number - REG_CR == CR_EOI) |
8499 | || (idesc->operands[1] == IA64_OPND_CR3 | |
8500 | && CURR_SLOT.opnd[1].X_add_number - REG_CR == CR_IVR)) | |
8501 | { | |
8502 | specs[count++] = tmpl; | |
8503 | } | |
800eeca4 JW |
8504 | break; |
8505 | ||
8506 | case IA64_RS_GR0: | |
8507 | if (note == 1) | |
542d6675 KH |
8508 | { |
8509 | specs[count++] = tmpl; | |
8510 | } | |
800eeca4 | 8511 | else |
542d6675 KH |
8512 | { |
8513 | UNHANDLED; | |
8514 | } | |
800eeca4 JW |
8515 | break; |
8516 | ||
8517 | case IA64_RS_CFM: | |
8518 | if (note != 2) | |
542d6675 KH |
8519 | { |
8520 | specs[count++] = tmpl; | |
8521 | } | |
800eeca4 | 8522 | else |
542d6675 KH |
8523 | { |
8524 | /* Check if any of the registers accessed are in the rotating region. | |
8525 | mov to/from pr accesses CFM only when qp_regno is in the rotating | |
8526 | region */ | |
8527 | for (i = 0; i < NELEMS (idesc->operands); i++) | |
8528 | { | |
8529 | if (idesc->operands[i] == IA64_OPND_R1 | |
8530 | || idesc->operands[i] == IA64_OPND_R2 | |
8531 | || idesc->operands[i] == IA64_OPND_R3) | |
8532 | { | |
8533 | int num = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8534 | /* Assumes that md.rot.num_regs is always valid */ | |
8535 | if (md.rot.num_regs > 0 | |
8536 | && num > 31 | |
8537 | && num < 31 + md.rot.num_regs) | |
8538 | { | |
8539 | specs[count] = tmpl; | |
8540 | specs[count++].specific = 0; | |
8541 | } | |
8542 | } | |
8543 | else if (idesc->operands[i] == IA64_OPND_F1 | |
8544 | || idesc->operands[i] == IA64_OPND_F2 | |
8545 | || idesc->operands[i] == IA64_OPND_F3 | |
8546 | || idesc->operands[i] == IA64_OPND_F4) | |
8547 | { | |
8548 | int num = CURR_SLOT.opnd[i].X_add_number - REG_FR; | |
8549 | if (num > 31) | |
8550 | { | |
8551 | specs[count] = tmpl; | |
8552 | specs[count++].specific = 0; | |
8553 | } | |
8554 | } | |
8555 | else if (idesc->operands[i] == IA64_OPND_P1 | |
8556 | || idesc->operands[i] == IA64_OPND_P2) | |
8557 | { | |
8558 | int num = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8559 | if (num > 15) | |
8560 | { | |
8561 | specs[count] = tmpl; | |
8562 | specs[count++].specific = 0; | |
8563 | } | |
8564 | } | |
8565 | } | |
8566 | if (CURR_SLOT.qp_regno > 15) | |
8567 | { | |
8568 | specs[count] = tmpl; | |
8569 | specs[count++].specific = 0; | |
8570 | } | |
8571 | } | |
800eeca4 JW |
8572 | break; |
8573 | ||
139368c9 JW |
8574 | /* This is the same as IA64_RS_PRr, except simplified to account for |
8575 | the fact that there is only one register. */ | |
800eeca4 JW |
8576 | case IA64_RS_PR63: |
8577 | if (note == 0) | |
542d6675 KH |
8578 | { |
8579 | specs[count++] = tmpl; | |
8580 | } | |
139368c9 | 8581 | else if (note == 7) |
40449e9f KH |
8582 | { |
8583 | valueT mask = 0; | |
8584 | if (idesc->operands[2] == IA64_OPND_IMM17) | |
8585 | mask = CURR_SLOT.opnd[2].X_add_number; | |
8586 | if (mask & ((valueT) 1 << 63)) | |
139368c9 | 8587 | specs[count++] = tmpl; |
40449e9f | 8588 | } |
800eeca4 | 8589 | else if (note == 11) |
542d6675 KH |
8590 | { |
8591 | if ((idesc->operands[0] == IA64_OPND_P1 | |
8592 | && CURR_SLOT.opnd[0].X_add_number - REG_P == 63) | |
8593 | || (idesc->operands[1] == IA64_OPND_P2 | |
8594 | && CURR_SLOT.opnd[1].X_add_number - REG_P == 63)) | |
8595 | { | |
8596 | specs[count++] = tmpl; | |
8597 | } | |
8598 | } | |
800eeca4 | 8599 | else if (note == 12) |
542d6675 KH |
8600 | { |
8601 | if (CURR_SLOT.qp_regno == 63) | |
8602 | { | |
8603 | specs[count++] = tmpl; | |
8604 | } | |
8605 | } | |
800eeca4 | 8606 | else if (note == 1) |
542d6675 KH |
8607 | { |
8608 | if (rsrc_write) | |
8609 | { | |
40449e9f KH |
8610 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; |
8611 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; | |
07726851 KH |
8612 | int or_andcm = strstr (idesc->name, "or.andcm") != NULL; |
8613 | int and_orcm = strstr (idesc->name, "and.orcm") != NULL; | |
7484b8e6 | 8614 | |
4a4f25cf | 8615 | if (p1 == 63 |
7484b8e6 TW |
8616 | && (idesc->operands[0] == IA64_OPND_P1 |
8617 | || idesc->operands[0] == IA64_OPND_P2)) | |
8618 | { | |
40449e9f | 8619 | specs[count] = tmpl; |
4a4f25cf | 8620 | specs[count++].cmp_type = |
7484b8e6 TW |
8621 | (or_andcm ? CMP_OR : (and_orcm ? CMP_AND : CMP_NONE)); |
8622 | } | |
8623 | if (p2 == 63 | |
8624 | && (idesc->operands[1] == IA64_OPND_P1 | |
8625 | || idesc->operands[1] == IA64_OPND_P2)) | |
8626 | { | |
40449e9f | 8627 | specs[count] = tmpl; |
4a4f25cf | 8628 | specs[count++].cmp_type = |
7484b8e6 TW |
8629 | (or_andcm ? CMP_AND : (and_orcm ? CMP_OR : CMP_NONE)); |
8630 | } | |
542d6675 KH |
8631 | } |
8632 | else | |
8633 | { | |
8634 | if (CURR_SLOT.qp_regno == 63) | |
8635 | { | |
8636 | specs[count++] = tmpl; | |
8637 | } | |
8638 | } | |
8639 | } | |
800eeca4 | 8640 | else |
542d6675 KH |
8641 | { |
8642 | UNHANDLED; | |
8643 | } | |
800eeca4 JW |
8644 | break; |
8645 | ||
8646 | case IA64_RS_RSE: | |
8647 | /* FIXME we can identify some individual RSE written resources, but RSE | |
542d6675 KH |
8648 | read resources have not yet been completely identified, so for now |
8649 | treat RSE as a single resource */ | |
800eeca4 | 8650 | if (strncmp (idesc->name, "mov", 3) == 0) |
542d6675 KH |
8651 | { |
8652 | if (rsrc_write) | |
8653 | { | |
8654 | if (idesc->operands[0] == IA64_OPND_AR3 | |
8655 | && CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE) | |
8656 | { | |
8657 | specs[count] = tmpl; | |
8658 | specs[count++].index = 0; /* IA64_RSE_BSPLOAD/RNATBITINDEX */ | |
8659 | } | |
8660 | } | |
8661 | else | |
8662 | { | |
8663 | if (idesc->operands[0] == IA64_OPND_AR3) | |
8664 | { | |
8665 | if (CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_BSPSTORE | |
8666 | || CURR_SLOT.opnd[0].X_add_number - REG_AR == AR_RNAT) | |
8667 | { | |
8668 | specs[count++] = tmpl; | |
8669 | } | |
8670 | } | |
8671 | else if (idesc->operands[1] == IA64_OPND_AR3) | |
8672 | { | |
8673 | if (CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSP | |
8674 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_BSPSTORE | |
8675 | || CURR_SLOT.opnd[1].X_add_number - REG_AR == AR_RNAT) | |
8676 | { | |
8677 | specs[count++] = tmpl; | |
8678 | } | |
8679 | } | |
8680 | } | |
8681 | } | |
197865e8 | 8682 | else |
542d6675 KH |
8683 | { |
8684 | specs[count++] = tmpl; | |
8685 | } | |
800eeca4 JW |
8686 | break; |
8687 | ||
8688 | case IA64_RS_ANY: | |
8689 | /* FIXME -- do any of these need to be non-specific? */ | |
8690 | specs[count++] = tmpl; | |
8691 | break; | |
8692 | ||
8693 | default: | |
8694 | as_bad (_("Unrecognized dependency specifier %d\n"), dep->specifier); | |
8695 | break; | |
8696 | } | |
8697 | ||
8698 | return count; | |
8699 | } | |
8700 | ||
8701 | /* Clear branch flags on marked resources. This breaks the link between the | |
542d6675 KH |
8702 | QP of the marking instruction and a subsequent branch on the same QP. */ |
8703 | ||
800eeca4 JW |
8704 | static void |
8705 | clear_qp_branch_flag (mask) | |
542d6675 | 8706 | valueT mask; |
800eeca4 JW |
8707 | { |
8708 | int i; | |
542d6675 | 8709 | for (i = 0; i < regdepslen; i++) |
800eeca4 | 8710 | { |
197865e8 | 8711 | valueT bit = ((valueT) 1 << regdeps[i].qp_regno); |
800eeca4 | 8712 | if ((bit & mask) != 0) |
542d6675 KH |
8713 | { |
8714 | regdeps[i].link_to_qp_branch = 0; | |
8715 | } | |
800eeca4 JW |
8716 | } |
8717 | } | |
8718 | ||
197865e8 | 8719 | /* Remove any mutexes which contain any of the PRs indicated in the mask. |
800eeca4 | 8720 | |
542d6675 KH |
8721 | Any changes to a PR clears the mutex relations which include that PR. */ |
8722 | ||
800eeca4 JW |
8723 | static void |
8724 | clear_qp_mutex (mask) | |
542d6675 | 8725 | valueT mask; |
800eeca4 JW |
8726 | { |
8727 | int i; | |
8728 | ||
8729 | i = 0; | |
8730 | while (i < qp_mutexeslen) | |
8731 | { | |
8732 | if ((qp_mutexes[i].prmask & mask) != 0) | |
542d6675 KH |
8733 | { |
8734 | if (md.debug_dv) | |
8735 | { | |
8736 | fprintf (stderr, " Clearing mutex relation"); | |
8737 | print_prmask (qp_mutexes[i].prmask); | |
8738 | fprintf (stderr, "\n"); | |
8739 | } | |
8740 | qp_mutexes[i] = qp_mutexes[--qp_mutexeslen]; | |
8741 | } | |
800eeca4 | 8742 | else |
542d6675 | 8743 | ++i; |
800eeca4 JW |
8744 | } |
8745 | } | |
8746 | ||
8747 | /* Clear implies relations which contain PRs in the given masks. | |
8748 | P1_MASK indicates the source of the implies relation, while P2_MASK | |
542d6675 KH |
8749 | indicates the implied PR. */ |
8750 | ||
800eeca4 JW |
8751 | static void |
8752 | clear_qp_implies (p1_mask, p2_mask) | |
542d6675 KH |
8753 | valueT p1_mask; |
8754 | valueT p2_mask; | |
800eeca4 JW |
8755 | { |
8756 | int i; | |
8757 | ||
8758 | i = 0; | |
8759 | while (i < qp_implieslen) | |
8760 | { | |
197865e8 | 8761 | if ((((valueT) 1 << qp_implies[i].p1) & p1_mask) != 0 |
542d6675 KH |
8762 | || (((valueT) 1 << qp_implies[i].p2) & p2_mask) != 0) |
8763 | { | |
8764 | if (md.debug_dv) | |
8765 | fprintf (stderr, "Clearing implied relation PR%d->PR%d\n", | |
8766 | qp_implies[i].p1, qp_implies[i].p2); | |
8767 | qp_implies[i] = qp_implies[--qp_implieslen]; | |
8768 | } | |
197865e8 | 8769 | else |
542d6675 | 8770 | ++i; |
800eeca4 JW |
8771 | } |
8772 | } | |
8773 | ||
542d6675 KH |
8774 | /* Add the PRs specified to the list of implied relations. */ |
8775 | ||
800eeca4 JW |
8776 | static void |
8777 | add_qp_imply (p1, p2) | |
542d6675 | 8778 | int p1, p2; |
800eeca4 JW |
8779 | { |
8780 | valueT mask; | |
8781 | valueT bit; | |
8782 | int i; | |
8783 | ||
542d6675 | 8784 | /* p0 is not meaningful here. */ |
800eeca4 JW |
8785 | if (p1 == 0 || p2 == 0) |
8786 | abort (); | |
8787 | ||
8788 | if (p1 == p2) | |
8789 | return; | |
8790 | ||
542d6675 KH |
8791 | /* If it exists already, ignore it. */ |
8792 | for (i = 0; i < qp_implieslen; i++) | |
800eeca4 | 8793 | { |
197865e8 | 8794 | if (qp_implies[i].p1 == p1 |
542d6675 KH |
8795 | && qp_implies[i].p2 == p2 |
8796 | && qp_implies[i].path == md.path | |
8797 | && !qp_implies[i].p2_branched) | |
8798 | return; | |
800eeca4 JW |
8799 | } |
8800 | ||
8801 | if (qp_implieslen == qp_impliestotlen) | |
8802 | { | |
8803 | qp_impliestotlen += 20; | |
8804 | qp_implies = (struct qp_imply *) | |
542d6675 KH |
8805 | xrealloc ((void *) qp_implies, |
8806 | qp_impliestotlen * sizeof (struct qp_imply)); | |
800eeca4 JW |
8807 | } |
8808 | if (md.debug_dv) | |
8809 | fprintf (stderr, " Registering PR%d implies PR%d\n", p1, p2); | |
8810 | qp_implies[qp_implieslen].p1 = p1; | |
8811 | qp_implies[qp_implieslen].p2 = p2; | |
8812 | qp_implies[qp_implieslen].path = md.path; | |
8813 | qp_implies[qp_implieslen++].p2_branched = 0; | |
8814 | ||
8815 | /* Add in the implied transitive relations; for everything that p2 implies, | |
8816 | make p1 imply that, too; for everything that implies p1, make it imply p2 | |
197865e8 | 8817 | as well. */ |
542d6675 | 8818 | for (i = 0; i < qp_implieslen; i++) |
800eeca4 JW |
8819 | { |
8820 | if (qp_implies[i].p1 == p2) | |
542d6675 | 8821 | add_qp_imply (p1, qp_implies[i].p2); |
800eeca4 | 8822 | if (qp_implies[i].p2 == p1) |
542d6675 | 8823 | add_qp_imply (qp_implies[i].p1, p2); |
800eeca4 JW |
8824 | } |
8825 | /* Add in mutex relations implied by this implies relation; for each mutex | |
197865e8 KH |
8826 | relation containing p2, duplicate it and replace p2 with p1. */ |
8827 | bit = (valueT) 1 << p1; | |
8828 | mask = (valueT) 1 << p2; | |
542d6675 | 8829 | for (i = 0; i < qp_mutexeslen; i++) |
800eeca4 JW |
8830 | { |
8831 | if (qp_mutexes[i].prmask & mask) | |
542d6675 | 8832 | add_qp_mutex ((qp_mutexes[i].prmask & ~mask) | bit); |
800eeca4 JW |
8833 | } |
8834 | } | |
8835 | ||
800eeca4 JW |
8836 | /* Add the PRs specified in the mask to the mutex list; this means that only |
8837 | one of the PRs can be true at any time. PR0 should never be included in | |
8838 | the mask. */ | |
542d6675 | 8839 | |
800eeca4 JW |
8840 | static void |
8841 | add_qp_mutex (mask) | |
542d6675 | 8842 | valueT mask; |
800eeca4 JW |
8843 | { |
8844 | if (mask & 0x1) | |
8845 | abort (); | |
8846 | ||
8847 | if (qp_mutexeslen == qp_mutexestotlen) | |
8848 | { | |
8849 | qp_mutexestotlen += 20; | |
8850 | qp_mutexes = (struct qpmutex *) | |
542d6675 KH |
8851 | xrealloc ((void *) qp_mutexes, |
8852 | qp_mutexestotlen * sizeof (struct qpmutex)); | |
800eeca4 JW |
8853 | } |
8854 | if (md.debug_dv) | |
8855 | { | |
8856 | fprintf (stderr, " Registering mutex on"); | |
8857 | print_prmask (mask); | |
8858 | fprintf (stderr, "\n"); | |
8859 | } | |
8860 | qp_mutexes[qp_mutexeslen].path = md.path; | |
8861 | qp_mutexes[qp_mutexeslen++].prmask = mask; | |
8862 | } | |
8863 | ||
cb5301b6 RH |
8864 | static int |
8865 | has_suffix_p (name, suffix) | |
40449e9f KH |
8866 | const char *name; |
8867 | const char *suffix; | |
cb5301b6 RH |
8868 | { |
8869 | size_t namelen = strlen (name); | |
8870 | size_t sufflen = strlen (suffix); | |
8871 | ||
8872 | if (namelen <= sufflen) | |
8873 | return 0; | |
8874 | return strcmp (name + namelen - sufflen, suffix) == 0; | |
8875 | } | |
8876 | ||
800eeca4 JW |
8877 | static void |
8878 | clear_register_values () | |
8879 | { | |
8880 | int i; | |
8881 | if (md.debug_dv) | |
8882 | fprintf (stderr, " Clearing register values\n"); | |
542d6675 | 8883 | for (i = 1; i < NELEMS (gr_values); i++) |
800eeca4 JW |
8884 | gr_values[i].known = 0; |
8885 | } | |
8886 | ||
8887 | /* Keep track of register values/changes which affect DV tracking. | |
8888 | ||
8889 | optimization note: should add a flag to classes of insns where otherwise we | |
542d6675 | 8890 | have to examine a group of strings to identify them. */ |
800eeca4 | 8891 | |
800eeca4 JW |
8892 | static void |
8893 | note_register_values (idesc) | |
542d6675 | 8894 | struct ia64_opcode *idesc; |
800eeca4 JW |
8895 | { |
8896 | valueT qp_changemask = 0; | |
8897 | int i; | |
8898 | ||
542d6675 KH |
8899 | /* Invalidate values for registers being written to. */ |
8900 | for (i = 0; i < idesc->num_outputs; i++) | |
800eeca4 | 8901 | { |
197865e8 | 8902 | if (idesc->operands[i] == IA64_OPND_R1 |
542d6675 KH |
8903 | || idesc->operands[i] == IA64_OPND_R2 |
8904 | || idesc->operands[i] == IA64_OPND_R3) | |
8905 | { | |
8906 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8907 | if (regno > 0 && regno < NELEMS (gr_values)) | |
8908 | gr_values[regno].known = 0; | |
8909 | } | |
50b81f19 JW |
8910 | else if (idesc->operands[i] == IA64_OPND_R3_2) |
8911 | { | |
8912 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; | |
8913 | if (regno > 0 && regno < 4) | |
8914 | gr_values[regno].known = 0; | |
8915 | } | |
197865e8 | 8916 | else if (idesc->operands[i] == IA64_OPND_P1 |
542d6675 KH |
8917 | || idesc->operands[i] == IA64_OPND_P2) |
8918 | { | |
8919 | int regno = CURR_SLOT.opnd[i].X_add_number - REG_P; | |
8920 | qp_changemask |= (valueT) 1 << regno; | |
8921 | } | |
800eeca4 | 8922 | else if (idesc->operands[i] == IA64_OPND_PR) |
542d6675 KH |
8923 | { |
8924 | if (idesc->operands[2] & (valueT) 0x10000) | |
8925 | qp_changemask = ~(valueT) 0x1FFFF | idesc->operands[2]; | |
8926 | else | |
8927 | qp_changemask = idesc->operands[2]; | |
8928 | break; | |
8929 | } | |
800eeca4 | 8930 | else if (idesc->operands[i] == IA64_OPND_PR_ROT) |
542d6675 KH |
8931 | { |
8932 | if (idesc->operands[1] & ((valueT) 1 << 43)) | |
8933 | qp_changemask = ~(valueT) 0xFFFFFFFFFFF | idesc->operands[1]; | |
8934 | else | |
8935 | qp_changemask = idesc->operands[1]; | |
8936 | qp_changemask &= ~(valueT) 0xFFFF; | |
8937 | break; | |
8938 | } | |
8939 | } | |
8940 | ||
8941 | /* Always clear qp branch flags on any PR change. */ | |
8942 | /* FIXME there may be exceptions for certain compares. */ | |
800eeca4 JW |
8943 | clear_qp_branch_flag (qp_changemask); |
8944 | ||
542d6675 | 8945 | /* Invalidate rotating registers on insns which affect RRBs in CFM. */ |
800eeca4 JW |
8946 | if (idesc->flags & IA64_OPCODE_MOD_RRBS) |
8947 | { | |
197865e8 | 8948 | qp_changemask |= ~(valueT) 0xFFFF; |
800eeca4 | 8949 | if (strcmp (idesc->name, "clrrrb.pr") != 0) |
542d6675 KH |
8950 | { |
8951 | for (i = 32; i < 32 + md.rot.num_regs; i++) | |
8952 | gr_values[i].known = 0; | |
8953 | } | |
800eeca4 JW |
8954 | clear_qp_mutex (qp_changemask); |
8955 | clear_qp_implies (qp_changemask, qp_changemask); | |
8956 | } | |
542d6675 KH |
8957 | /* After a call, all register values are undefined, except those marked |
8958 | as "safe". */ | |
800eeca4 | 8959 | else if (strncmp (idesc->name, "br.call", 6) == 0 |
542d6675 | 8960 | || strncmp (idesc->name, "brl.call", 7) == 0) |
800eeca4 | 8961 | { |
56d27c17 | 8962 | /* FIXME keep GR values which are marked as "safe_across_calls" */ |
800eeca4 JW |
8963 | clear_register_values (); |
8964 | clear_qp_mutex (~qp_safe_across_calls); | |
8965 | clear_qp_implies (~qp_safe_across_calls, ~qp_safe_across_calls); | |
8966 | clear_qp_branch_flag (~qp_safe_across_calls); | |
8967 | } | |
e9718fe1 | 8968 | else if (is_interruption_or_rfi (idesc) |
542d6675 | 8969 | || is_taken_branch (idesc)) |
e9718fe1 TW |
8970 | { |
8971 | clear_register_values (); | |
197865e8 KH |
8972 | clear_qp_mutex (~(valueT) 0); |
8973 | clear_qp_implies (~(valueT) 0, ~(valueT) 0); | |
e9718fe1 | 8974 | } |
542d6675 | 8975 | /* Look for mutex and implies relations. */ |
197865e8 | 8976 | else if ((idesc->operands[0] == IA64_OPND_P1 |
542d6675 KH |
8977 | || idesc->operands[0] == IA64_OPND_P2) |
8978 | && (idesc->operands[1] == IA64_OPND_P1 | |
8979 | || idesc->operands[1] == IA64_OPND_P2)) | |
800eeca4 JW |
8980 | { |
8981 | int p1 = CURR_SLOT.opnd[0].X_add_number - REG_P; | |
197865e8 KH |
8982 | int p2 = CURR_SLOT.opnd[1].X_add_number - REG_P; |
8983 | valueT p1mask = (valueT) 1 << p1; | |
8984 | valueT p2mask = (valueT) 1 << p2; | |
800eeca4 | 8985 | |
542d6675 | 8986 | /* If one of the PRs is PR0, we can't really do anything. */ |
800eeca4 | 8987 | if (p1 == 0 || p2 == 0) |
542d6675 KH |
8988 | { |
8989 | if (md.debug_dv) | |
8990 | fprintf (stderr, " Ignoring PRs due to inclusion of p0\n"); | |
8991 | } | |
800eeca4 | 8992 | /* In general, clear mutexes and implies which include P1 or P2, |
542d6675 | 8993 | with the following exceptions. */ |
cb5301b6 RH |
8994 | else if (has_suffix_p (idesc->name, ".or.andcm") |
8995 | || has_suffix_p (idesc->name, ".and.orcm")) | |
542d6675 KH |
8996 | { |
8997 | add_qp_mutex (p1mask | p2mask); | |
8998 | clear_qp_implies (p2mask, p1mask); | |
8999 | } | |
cb5301b6 RH |
9000 | else if (has_suffix_p (idesc->name, ".andcm") |
9001 | || has_suffix_p (idesc->name, ".and")) | |
542d6675 KH |
9002 | { |
9003 | clear_qp_implies (0, p1mask | p2mask); | |
9004 | } | |
cb5301b6 RH |
9005 | else if (has_suffix_p (idesc->name, ".orcm") |
9006 | || has_suffix_p (idesc->name, ".or")) | |
542d6675 KH |
9007 | { |
9008 | clear_qp_mutex (p1mask | p2mask); | |
9009 | clear_qp_implies (p1mask | p2mask, 0); | |
9010 | } | |
800eeca4 | 9011 | else |
542d6675 KH |
9012 | { |
9013 | clear_qp_implies (p1mask | p2mask, p1mask | p2mask); | |
cb5301b6 | 9014 | if (has_suffix_p (idesc->name, ".unc")) |
542d6675 KH |
9015 | { |
9016 | add_qp_mutex (p1mask | p2mask); | |
9017 | if (CURR_SLOT.qp_regno != 0) | |
9018 | { | |
9019 | add_qp_imply (CURR_SLOT.opnd[0].X_add_number - REG_P, | |
9020 | CURR_SLOT.qp_regno); | |
9021 | add_qp_imply (CURR_SLOT.opnd[1].X_add_number - REG_P, | |
9022 | CURR_SLOT.qp_regno); | |
9023 | } | |
9024 | } | |
9025 | else if (CURR_SLOT.qp_regno == 0) | |
9026 | { | |
9027 | add_qp_mutex (p1mask | p2mask); | |
9028 | } | |
9029 | else | |
9030 | { | |
9031 | clear_qp_mutex (p1mask | p2mask); | |
9032 | } | |
9033 | } | |
9034 | } | |
9035 | /* Look for mov imm insns into GRs. */ | |
800eeca4 | 9036 | else if (idesc->operands[0] == IA64_OPND_R1 |
542d6675 KH |
9037 | && (idesc->operands[1] == IA64_OPND_IMM22 |
9038 | || idesc->operands[1] == IA64_OPND_IMMU64) | |
9039 | && (strcmp (idesc->name, "mov") == 0 | |
9040 | || strcmp (idesc->name, "movl") == 0)) | |
800eeca4 JW |
9041 | { |
9042 | int regno = CURR_SLOT.opnd[0].X_add_number - REG_GR; | |
542d6675 KH |
9043 | if (regno > 0 && regno < NELEMS (gr_values)) |
9044 | { | |
9045 | gr_values[regno].known = 1; | |
9046 | gr_values[regno].value = CURR_SLOT.opnd[1].X_add_number; | |
9047 | gr_values[regno].path = md.path; | |
9048 | if (md.debug_dv) | |
2434f565 JW |
9049 | { |
9050 | fprintf (stderr, " Know gr%d = ", regno); | |
9051 | fprintf_vma (stderr, gr_values[regno].value); | |
9052 | fputs ("\n", stderr); | |
9053 | } | |
542d6675 | 9054 | } |
800eeca4 | 9055 | } |
197865e8 | 9056 | else |
800eeca4 JW |
9057 | { |
9058 | clear_qp_mutex (qp_changemask); | |
9059 | clear_qp_implies (qp_changemask, qp_changemask); | |
9060 | } | |
9061 | } | |
9062 | ||
542d6675 KH |
9063 | /* Return whether the given predicate registers are currently mutex. */ |
9064 | ||
800eeca4 JW |
9065 | static int |
9066 | qp_mutex (p1, p2, path) | |
542d6675 KH |
9067 | int p1; |
9068 | int p2; | |
9069 | int path; | |
800eeca4 JW |
9070 | { |
9071 | int i; | |
9072 | valueT mask; | |
9073 | ||
9074 | if (p1 != p2) | |
9075 | { | |
542d6675 KH |
9076 | mask = ((valueT) 1 << p1) | (valueT) 1 << p2; |
9077 | for (i = 0; i < qp_mutexeslen; i++) | |
9078 | { | |
9079 | if (qp_mutexes[i].path >= path | |
9080 | && (qp_mutexes[i].prmask & mask) == mask) | |
9081 | return 1; | |
9082 | } | |
800eeca4 JW |
9083 | } |
9084 | return 0; | |
9085 | } | |
9086 | ||
9087 | /* Return whether the given resource is in the given insn's list of chks | |
9088 | Return 1 if the conflict is absolutely determined, 2 if it's a potential | |
542d6675 KH |
9089 | conflict. */ |
9090 | ||
800eeca4 JW |
9091 | static int |
9092 | resources_match (rs, idesc, note, qp_regno, path) | |
542d6675 KH |
9093 | struct rsrc *rs; |
9094 | struct ia64_opcode *idesc; | |
9095 | int note; | |
9096 | int qp_regno; | |
9097 | int path; | |
800eeca4 JW |
9098 | { |
9099 | struct rsrc specs[MAX_SPECS]; | |
9100 | int count; | |
9101 | ||
9102 | /* If the marked resource's qp_regno and the given qp_regno are mutex, | |
9103 | we don't need to check. One exception is note 11, which indicates that | |
9104 | target predicates are written regardless of PR[qp]. */ | |
197865e8 | 9105 | if (qp_mutex (rs->qp_regno, qp_regno, path) |
800eeca4 JW |
9106 | && note != 11) |
9107 | return 0; | |
9108 | ||
9109 | count = specify_resource (rs->dependency, idesc, DV_CHK, specs, note, path); | |
9110 | while (count-- > 0) | |
9111 | { | |
9112 | /* UNAT checking is a bit more specific than other resources */ | |
9113 | if (rs->dependency->specifier == IA64_RS_AR_UNAT | |
542d6675 KH |
9114 | && specs[count].mem_offset.hint |
9115 | && rs->mem_offset.hint) | |
9116 | { | |
9117 | if (rs->mem_offset.base == specs[count].mem_offset.base) | |
9118 | { | |
9119 | if (((rs->mem_offset.offset >> 3) & 0x3F) == | |
9120 | ((specs[count].mem_offset.offset >> 3) & 0x3F)) | |
9121 | return 1; | |
9122 | else | |
9123 | continue; | |
9124 | } | |
9125 | } | |
800eeca4 | 9126 | |
7484b8e6 | 9127 | /* Skip apparent PR write conflicts where both writes are an AND or both |
4a4f25cf | 9128 | writes are an OR. */ |
7484b8e6 | 9129 | if (rs->dependency->specifier == IA64_RS_PR |
afa680f8 | 9130 | || rs->dependency->specifier == IA64_RS_PRr |
7484b8e6 TW |
9131 | || rs->dependency->specifier == IA64_RS_PR63) |
9132 | { | |
9133 | if (specs[count].cmp_type != CMP_NONE | |
9134 | && specs[count].cmp_type == rs->cmp_type) | |
9135 | { | |
9136 | if (md.debug_dv) | |
9137 | fprintf (stderr, " %s on parallel compare allowed (PR%d)\n", | |
9138 | dv_mode[rs->dependency->mode], | |
afa680f8 | 9139 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 TW |
9140 | specs[count].index : 63); |
9141 | continue; | |
9142 | } | |
9143 | if (md.debug_dv) | |
4a4f25cf | 9144 | fprintf (stderr, |
7484b8e6 TW |
9145 | " %s on parallel compare conflict %s vs %s on PR%d\n", |
9146 | dv_mode[rs->dependency->mode], | |
4a4f25cf | 9147 | dv_cmp_type[rs->cmp_type], |
7484b8e6 | 9148 | dv_cmp_type[specs[count].cmp_type], |
afa680f8 | 9149 | rs->dependency->specifier != IA64_RS_PR63 ? |
7484b8e6 | 9150 | specs[count].index : 63); |
4a4f25cf | 9151 | |
7484b8e6 TW |
9152 | } |
9153 | ||
800eeca4 | 9154 | /* If either resource is not specific, conservatively assume a conflict |
197865e8 | 9155 | */ |
800eeca4 | 9156 | if (!specs[count].specific || !rs->specific) |
542d6675 | 9157 | return 2; |
800eeca4 | 9158 | else if (specs[count].index == rs->index) |
542d6675 | 9159 | return 1; |
800eeca4 JW |
9160 | } |
9161 | #if 0 | |
9162 | if (md.debug_dv) | |
9163 | fprintf (stderr, " No %s conflicts\n", rs->dependency->name); | |
9164 | #endif | |
9165 | ||
9166 | return 0; | |
9167 | } | |
9168 | ||
9169 | /* Indicate an instruction group break; if INSERT_STOP is non-zero, then | |
9170 | insert a stop to create the break. Update all resource dependencies | |
9171 | appropriately. If QP_REGNO is non-zero, only apply the break to resources | |
9172 | which use the same QP_REGNO and have the link_to_qp_branch flag set. | |
9173 | If SAVE_CURRENT is non-zero, don't affect resources marked by the current | |
542d6675 | 9174 | instruction. */ |
800eeca4 JW |
9175 | |
9176 | static void | |
9177 | insn_group_break (insert_stop, qp_regno, save_current) | |
542d6675 KH |
9178 | int insert_stop; |
9179 | int qp_regno; | |
9180 | int save_current; | |
800eeca4 JW |
9181 | { |
9182 | int i; | |
9183 | ||
9184 | if (insert_stop && md.num_slots_in_use > 0) | |
9185 | PREV_SLOT.end_of_insn_group = 1; | |
9186 | ||
9187 | if (md.debug_dv) | |
9188 | { | |
197865e8 | 9189 | fprintf (stderr, " Insn group break%s", |
542d6675 | 9190 | (insert_stop ? " (w/stop)" : "")); |
800eeca4 | 9191 | if (qp_regno != 0) |
542d6675 | 9192 | fprintf (stderr, " effective for QP=%d", qp_regno); |
800eeca4 JW |
9193 | fprintf (stderr, "\n"); |
9194 | } | |
9195 | ||
9196 | i = 0; | |
9197 | while (i < regdepslen) | |
9198 | { | |
9199 | const struct ia64_dependency *dep = regdeps[i].dependency; | |
9200 | ||
9201 | if (qp_regno != 0 | |
542d6675 KH |
9202 | && regdeps[i].qp_regno != qp_regno) |
9203 | { | |
9204 | ++i; | |
9205 | continue; | |
9206 | } | |
800eeca4 JW |
9207 | |
9208 | if (save_current | |
542d6675 KH |
9209 | && CURR_SLOT.src_file == regdeps[i].file |
9210 | && CURR_SLOT.src_line == regdeps[i].line) | |
9211 | { | |
9212 | ++i; | |
9213 | continue; | |
9214 | } | |
800eeca4 JW |
9215 | |
9216 | /* clear dependencies which are automatically cleared by a stop, or | |
542d6675 | 9217 | those that have reached the appropriate state of insn serialization */ |
800eeca4 | 9218 | if (dep->semantics == IA64_DVS_IMPLIED |
542d6675 KH |
9219 | || dep->semantics == IA64_DVS_IMPLIEDF |
9220 | || regdeps[i].insn_srlz == STATE_SRLZ) | |
9221 | { | |
9222 | print_dependency ("Removing", i); | |
9223 | regdeps[i] = regdeps[--regdepslen]; | |
9224 | } | |
800eeca4 | 9225 | else |
542d6675 KH |
9226 | { |
9227 | if (dep->semantics == IA64_DVS_DATA | |
9228 | || dep->semantics == IA64_DVS_INSTR | |
800eeca4 | 9229 | || dep->semantics == IA64_DVS_SPECIFIC) |
542d6675 KH |
9230 | { |
9231 | if (regdeps[i].insn_srlz == STATE_NONE) | |
9232 | regdeps[i].insn_srlz = STATE_STOP; | |
9233 | if (regdeps[i].data_srlz == STATE_NONE) | |
9234 | regdeps[i].data_srlz = STATE_STOP; | |
9235 | } | |
9236 | ++i; | |
9237 | } | |
800eeca4 JW |
9238 | } |
9239 | } | |
9240 | ||
542d6675 KH |
9241 | /* Add the given resource usage spec to the list of active dependencies. */ |
9242 | ||
197865e8 | 9243 | static void |
800eeca4 | 9244 | mark_resource (idesc, dep, spec, depind, path) |
2434f565 JW |
9245 | struct ia64_opcode *idesc ATTRIBUTE_UNUSED; |
9246 | const struct ia64_dependency *dep ATTRIBUTE_UNUSED; | |
542d6675 KH |
9247 | struct rsrc *spec; |
9248 | int depind; | |
9249 | int path; | |
800eeca4 JW |
9250 | { |
9251 | if (regdepslen == regdepstotlen) | |
9252 | { | |
9253 | regdepstotlen += 20; | |
9254 | regdeps = (struct rsrc *) | |
542d6675 | 9255 | xrealloc ((void *) regdeps, |
bc805888 | 9256 | regdepstotlen * sizeof (struct rsrc)); |
800eeca4 JW |
9257 | } |
9258 | ||
9259 | regdeps[regdepslen] = *spec; | |
9260 | regdeps[regdepslen].depind = depind; | |
9261 | regdeps[regdepslen].path = path; | |
9262 | regdeps[regdepslen].file = CURR_SLOT.src_file; | |
9263 | regdeps[regdepslen].line = CURR_SLOT.src_line; | |
9264 | ||
9265 | print_dependency ("Adding", regdepslen); | |
9266 | ||
9267 | ++regdepslen; | |
9268 | } | |
9269 | ||
9270 | static void | |
9271 | print_dependency (action, depind) | |
542d6675 KH |
9272 | const char *action; |
9273 | int depind; | |
800eeca4 JW |
9274 | { |
9275 | if (md.debug_dv) | |
9276 | { | |
197865e8 | 9277 | fprintf (stderr, " %s %s '%s'", |
542d6675 KH |
9278 | action, dv_mode[(regdeps[depind].dependency)->mode], |
9279 | (regdeps[depind].dependency)->name); | |
800eeca4 | 9280 | if (regdeps[depind].specific && regdeps[depind].index != 0) |
542d6675 | 9281 | fprintf (stderr, " (%d)", regdeps[depind].index); |
800eeca4 | 9282 | if (regdeps[depind].mem_offset.hint) |
2434f565 JW |
9283 | { |
9284 | fputs (" ", stderr); | |
9285 | fprintf_vma (stderr, regdeps[depind].mem_offset.base); | |
9286 | fputs ("+", stderr); | |
9287 | fprintf_vma (stderr, regdeps[depind].mem_offset.offset); | |
9288 | } | |
800eeca4 JW |
9289 | fprintf (stderr, "\n"); |
9290 | } | |
9291 | } | |
9292 | ||
9293 | static void | |
9294 | instruction_serialization () | |
9295 | { | |
9296 | int i; | |
9297 | if (md.debug_dv) | |
9298 | fprintf (stderr, " Instruction serialization\n"); | |
542d6675 | 9299 | for (i = 0; i < regdepslen; i++) |
800eeca4 JW |
9300 | if (regdeps[i].insn_srlz == STATE_STOP) |
9301 | regdeps[i].insn_srlz = STATE_SRLZ; | |
9302 | } | |
9303 | ||
9304 | static void | |
9305 | data_serialization () | |
9306 | { | |
9307 | int i = 0; | |
9308 | if (md.debug_dv) | |
9309 | fprintf (stderr, " Data serialization\n"); | |
9310 | while (i < regdepslen) | |
9311 | { | |
9312 | if (regdeps[i].data_srlz == STATE_STOP | |
542d6675 KH |
9313 | /* Note: as of 991210, all "other" dependencies are cleared by a |
9314 | data serialization. This might change with new tables */ | |
9315 | || (regdeps[i].dependency)->semantics == IA64_DVS_OTHER) | |
9316 | { | |
9317 | print_dependency ("Removing", i); | |
9318 | regdeps[i] = regdeps[--regdepslen]; | |
9319 | } | |
800eeca4 | 9320 | else |
542d6675 | 9321 | ++i; |
800eeca4 JW |
9322 | } |
9323 | } | |
9324 | ||
542d6675 KH |
9325 | /* Insert stops and serializations as needed to avoid DVs. */ |
9326 | ||
800eeca4 JW |
9327 | static void |
9328 | remove_marked_resource (rs) | |
542d6675 | 9329 | struct rsrc *rs; |
800eeca4 JW |
9330 | { |
9331 | switch (rs->dependency->semantics) | |
9332 | { | |
9333 | case IA64_DVS_SPECIFIC: | |
9334 | if (md.debug_dv) | |
9335 | fprintf (stderr, "Implementation-specific, assume worst case...\n"); | |
197865e8 | 9336 | /* ...fall through... */ |
800eeca4 JW |
9337 | case IA64_DVS_INSTR: |
9338 | if (md.debug_dv) | |
542d6675 | 9339 | fprintf (stderr, "Inserting instr serialization\n"); |
800eeca4 | 9340 | if (rs->insn_srlz < STATE_STOP) |
542d6675 | 9341 | insn_group_break (1, 0, 0); |
800eeca4 | 9342 | if (rs->insn_srlz < STATE_SRLZ) |
542d6675 KH |
9343 | { |
9344 | int oldqp = CURR_SLOT.qp_regno; | |
9345 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
9346 | /* Manually jam a srlz.i insn into the stream */ | |
9347 | CURR_SLOT.qp_regno = 0; | |
9348 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.i"); | |
9349 | instruction_serialization (); | |
9350 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9351 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9352 | emit_one_bundle (); | |
9353 | CURR_SLOT.qp_regno = oldqp; | |
9354 | CURR_SLOT.idesc = oldidesc; | |
9355 | } | |
800eeca4 JW |
9356 | insn_group_break (1, 0, 0); |
9357 | break; | |
9358 | case IA64_DVS_OTHER: /* as of rev2 (991220) of the DV tables, all | |
542d6675 KH |
9359 | "other" types of DV are eliminated |
9360 | by a data serialization */ | |
800eeca4 JW |
9361 | case IA64_DVS_DATA: |
9362 | if (md.debug_dv) | |
542d6675 | 9363 | fprintf (stderr, "Inserting data serialization\n"); |
800eeca4 | 9364 | if (rs->data_srlz < STATE_STOP) |
542d6675 | 9365 | insn_group_break (1, 0, 0); |
800eeca4 | 9366 | { |
542d6675 KH |
9367 | int oldqp = CURR_SLOT.qp_regno; |
9368 | struct ia64_opcode *oldidesc = CURR_SLOT.idesc; | |
9369 | /* Manually jam a srlz.d insn into the stream */ | |
9370 | CURR_SLOT.qp_regno = 0; | |
9371 | CURR_SLOT.idesc = ia64_find_opcode ("srlz.d"); | |
9372 | data_serialization (); | |
9373 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9374 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9375 | emit_one_bundle (); | |
9376 | CURR_SLOT.qp_regno = oldqp; | |
9377 | CURR_SLOT.idesc = oldidesc; | |
800eeca4 JW |
9378 | } |
9379 | break; | |
9380 | case IA64_DVS_IMPLIED: | |
9381 | case IA64_DVS_IMPLIEDF: | |
9382 | if (md.debug_dv) | |
542d6675 | 9383 | fprintf (stderr, "Inserting stop\n"); |
800eeca4 JW |
9384 | insn_group_break (1, 0, 0); |
9385 | break; | |
9386 | default: | |
9387 | break; | |
9388 | } | |
9389 | } | |
9390 | ||
9391 | /* Check the resources used by the given opcode against the current dependency | |
197865e8 | 9392 | list. |
800eeca4 JW |
9393 | |
9394 | The check is run once for each execution path encountered. In this case, | |
9395 | a unique execution path is the sequence of instructions following a code | |
9396 | entry point, e.g. the following has three execution paths, one starting | |
9397 | at L0, one at L1, and one at L2. | |
197865e8 | 9398 | |
800eeca4 JW |
9399 | L0: nop |
9400 | L1: add | |
9401 | L2: add | |
197865e8 | 9402 | br.ret |
800eeca4 | 9403 | */ |
542d6675 | 9404 | |
800eeca4 JW |
9405 | static void |
9406 | check_dependencies (idesc) | |
542d6675 | 9407 | struct ia64_opcode *idesc; |
800eeca4 JW |
9408 | { |
9409 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
9410 | int path; | |
9411 | int i; | |
9412 | ||
9413 | /* Note that the number of marked resources may change within the | |
197865e8 | 9414 | loop if in auto mode. */ |
800eeca4 JW |
9415 | i = 0; |
9416 | while (i < regdepslen) | |
9417 | { | |
9418 | struct rsrc *rs = ®deps[i]; | |
9419 | const struct ia64_dependency *dep = rs->dependency; | |
9420 | int chkind; | |
9421 | int note; | |
9422 | int start_over = 0; | |
9423 | ||
9424 | if (dep->semantics == IA64_DVS_NONE | |
542d6675 KH |
9425 | || (chkind = depends_on (rs->depind, idesc)) == -1) |
9426 | { | |
9427 | ++i; | |
9428 | continue; | |
9429 | } | |
9430 | ||
9431 | note = NOTE (opdeps->chks[chkind]); | |
9432 | ||
9433 | /* Check this resource against each execution path seen thus far. */ | |
9434 | for (path = 0; path <= md.path; path++) | |
9435 | { | |
9436 | int matchtype; | |
9437 | ||
9438 | /* If the dependency wasn't on the path being checked, ignore it. */ | |
9439 | if (rs->path < path) | |
9440 | continue; | |
9441 | ||
9442 | /* If the QP for this insn implies a QP which has branched, don't | |
9443 | bother checking. Ed. NOTE: I don't think this check is terribly | |
9444 | useful; what's the point of generating code which will only be | |
9445 | reached if its QP is zero? | |
9446 | This code was specifically inserted to handle the following code, | |
9447 | based on notes from Intel's DV checking code, where p1 implies p2. | |
9448 | ||
9449 | mov r4 = 2 | |
9450 | (p2) br.cond L | |
9451 | (p1) mov r4 = 7 | |
9452 | */ | |
9453 | if (CURR_SLOT.qp_regno != 0) | |
9454 | { | |
9455 | int skip = 0; | |
9456 | int implies; | |
9457 | for (implies = 0; implies < qp_implieslen; implies++) | |
9458 | { | |
9459 | if (qp_implies[implies].path >= path | |
9460 | && qp_implies[implies].p1 == CURR_SLOT.qp_regno | |
9461 | && qp_implies[implies].p2_branched) | |
9462 | { | |
9463 | skip = 1; | |
9464 | break; | |
9465 | } | |
9466 | } | |
9467 | if (skip) | |
9468 | continue; | |
9469 | } | |
9470 | ||
9471 | if ((matchtype = resources_match (rs, idesc, note, | |
9472 | CURR_SLOT.qp_regno, path)) != 0) | |
9473 | { | |
9474 | char msg[1024]; | |
9475 | char pathmsg[256] = ""; | |
9476 | char indexmsg[256] = ""; | |
9477 | int certain = (matchtype == 1 && CURR_SLOT.qp_regno == 0); | |
9478 | ||
9479 | if (path != 0) | |
9480 | sprintf (pathmsg, " when entry is at label '%s'", | |
9481 | md.entry_labels[path - 1]); | |
9482 | if (rs->specific && rs->index != 0) | |
9483 | sprintf (indexmsg, ", specific resource number is %d", | |
9484 | rs->index); | |
9485 | sprintf (msg, "Use of '%s' %s %s dependency '%s' (%s)%s%s", | |
9486 | idesc->name, | |
9487 | (certain ? "violates" : "may violate"), | |
9488 | dv_mode[dep->mode], dep->name, | |
9489 | dv_sem[dep->semantics], | |
9490 | pathmsg, indexmsg); | |
9491 | ||
9492 | if (md.explicit_mode) | |
9493 | { | |
9494 | as_warn ("%s", msg); | |
9495 | if (path < md.path) | |
9496 | as_warn (_("Only the first path encountering the conflict " | |
9497 | "is reported")); | |
9498 | as_warn_where (rs->file, rs->line, | |
9499 | _("This is the location of the " | |
9500 | "conflicting usage")); | |
9501 | /* Don't bother checking other paths, to avoid duplicating | |
9502 | the same warning */ | |
9503 | break; | |
9504 | } | |
9505 | else | |
9506 | { | |
9507 | if (md.debug_dv) | |
9508 | fprintf (stderr, "%s @ %s:%d\n", msg, rs->file, rs->line); | |
9509 | ||
9510 | remove_marked_resource (rs); | |
9511 | ||
9512 | /* since the set of dependencies has changed, start over */ | |
9513 | /* FIXME -- since we're removing dvs as we go, we | |
9514 | probably don't really need to start over... */ | |
9515 | start_over = 1; | |
9516 | break; | |
9517 | } | |
9518 | } | |
9519 | } | |
800eeca4 | 9520 | if (start_over) |
542d6675 | 9521 | i = 0; |
800eeca4 | 9522 | else |
542d6675 | 9523 | ++i; |
800eeca4 JW |
9524 | } |
9525 | } | |
9526 | ||
542d6675 KH |
9527 | /* Register new dependencies based on the given opcode. */ |
9528 | ||
800eeca4 JW |
9529 | static void |
9530 | mark_resources (idesc) | |
542d6675 | 9531 | struct ia64_opcode *idesc; |
800eeca4 JW |
9532 | { |
9533 | int i; | |
9534 | const struct ia64_opcode_dependency *opdeps = idesc->dependencies; | |
9535 | int add_only_qp_reads = 0; | |
9536 | ||
9537 | /* A conditional branch only uses its resources if it is taken; if it is | |
9538 | taken, we stop following that path. The other branch types effectively | |
9539 | *always* write their resources. If it's not taken, register only QP | |
197865e8 | 9540 | reads. */ |
800eeca4 JW |
9541 | if (is_conditional_branch (idesc) || is_interruption_or_rfi (idesc)) |
9542 | { | |
9543 | add_only_qp_reads = 1; | |
9544 | } | |
9545 | ||
9546 | if (md.debug_dv) | |
9547 | fprintf (stderr, "Registering '%s' resource usage\n", idesc->name); | |
9548 | ||
542d6675 | 9549 | for (i = 0; i < opdeps->nregs; i++) |
800eeca4 JW |
9550 | { |
9551 | const struct ia64_dependency *dep; | |
9552 | struct rsrc specs[MAX_SPECS]; | |
9553 | int note; | |
9554 | int path; | |
9555 | int count; | |
197865e8 | 9556 | |
800eeca4 | 9557 | dep = ia64_find_dependency (opdeps->regs[i]); |
542d6675 | 9558 | note = NOTE (opdeps->regs[i]); |
800eeca4 JW |
9559 | |
9560 | if (add_only_qp_reads | |
542d6675 KH |
9561 | && !(dep->mode == IA64_DV_WAR |
9562 | && (dep->specifier == IA64_RS_PR | |
139368c9 | 9563 | || dep->specifier == IA64_RS_PRr |
542d6675 KH |
9564 | || dep->specifier == IA64_RS_PR63))) |
9565 | continue; | |
800eeca4 JW |
9566 | |
9567 | count = specify_resource (dep, idesc, DV_REG, specs, note, md.path); | |
9568 | ||
9569 | #if 0 | |
9570 | if (md.debug_dv && !count) | |
542d6675 KH |
9571 | fprintf (stderr, " No %s %s usage found (path %d)\n", |
9572 | dv_mode[dep->mode], dep->name, md.path); | |
800eeca4 | 9573 | #endif |
197865e8 | 9574 | |
800eeca4 | 9575 | while (count-- > 0) |
542d6675 KH |
9576 | { |
9577 | mark_resource (idesc, dep, &specs[count], | |
9578 | DEP (opdeps->regs[i]), md.path); | |
9579 | } | |
800eeca4 JW |
9580 | |
9581 | /* The execution path may affect register values, which may in turn | |
542d6675 | 9582 | affect which indirect-access resources are accessed. */ |
800eeca4 | 9583 | switch (dep->specifier) |
542d6675 KH |
9584 | { |
9585 | default: | |
9586 | break; | |
9587 | case IA64_RS_CPUID: | |
9588 | case IA64_RS_DBR: | |
9589 | case IA64_RS_IBR: | |
800eeca4 | 9590 | case IA64_RS_MSR: |
542d6675 KH |
9591 | case IA64_RS_PKR: |
9592 | case IA64_RS_PMC: | |
9593 | case IA64_RS_PMD: | |
9594 | case IA64_RS_RR: | |
9595 | for (path = 0; path < md.path; path++) | |
9596 | { | |
9597 | count = specify_resource (dep, idesc, DV_REG, specs, note, path); | |
9598 | while (count-- > 0) | |
9599 | mark_resource (idesc, dep, &specs[count], | |
9600 | DEP (opdeps->regs[i]), path); | |
9601 | } | |
9602 | break; | |
9603 | } | |
9604 | } | |
9605 | } | |
9606 | ||
9607 | /* Remove dependencies when they no longer apply. */ | |
9608 | ||
800eeca4 JW |
9609 | static void |
9610 | update_dependencies (idesc) | |
542d6675 | 9611 | struct ia64_opcode *idesc; |
800eeca4 JW |
9612 | { |
9613 | int i; | |
9614 | ||
9615 | if (strcmp (idesc->name, "srlz.i") == 0) | |
9616 | { | |
9617 | instruction_serialization (); | |
9618 | } | |
9619 | else if (strcmp (idesc->name, "srlz.d") == 0) | |
9620 | { | |
9621 | data_serialization (); | |
9622 | } | |
9623 | else if (is_interruption_or_rfi (idesc) | |
542d6675 | 9624 | || is_taken_branch (idesc)) |
800eeca4 | 9625 | { |
542d6675 KH |
9626 | /* Although technically the taken branch doesn't clear dependencies |
9627 | which require a srlz.[id], we don't follow the branch; the next | |
9628 | instruction is assumed to start with a clean slate. */ | |
800eeca4 | 9629 | regdepslen = 0; |
800eeca4 JW |
9630 | md.path = 0; |
9631 | } | |
9632 | else if (is_conditional_branch (idesc) | |
542d6675 | 9633 | && CURR_SLOT.qp_regno != 0) |
800eeca4 JW |
9634 | { |
9635 | int is_call = strstr (idesc->name, ".call") != NULL; | |
9636 | ||
542d6675 KH |
9637 | for (i = 0; i < qp_implieslen; i++) |
9638 | { | |
9639 | /* If the conditional branch's predicate is implied by the predicate | |
9640 | in an existing dependency, remove that dependency. */ | |
9641 | if (qp_implies[i].p2 == CURR_SLOT.qp_regno) | |
9642 | { | |
9643 | int depind = 0; | |
9644 | /* Note that this implied predicate takes a branch so that if | |
9645 | a later insn generates a DV but its predicate implies this | |
9646 | one, we can avoid the false DV warning. */ | |
9647 | qp_implies[i].p2_branched = 1; | |
9648 | while (depind < regdepslen) | |
9649 | { | |
9650 | if (regdeps[depind].qp_regno == qp_implies[i].p1) | |
9651 | { | |
9652 | print_dependency ("Removing", depind); | |
9653 | regdeps[depind] = regdeps[--regdepslen]; | |
9654 | } | |
9655 | else | |
9656 | ++depind; | |
9657 | } | |
9658 | } | |
9659 | } | |
800eeca4 | 9660 | /* Any marked resources which have this same predicate should be |
542d6675 KH |
9661 | cleared, provided that the QP hasn't been modified between the |
9662 | marking instruction and the branch. */ | |
800eeca4 | 9663 | if (is_call) |
542d6675 KH |
9664 | { |
9665 | insn_group_break (0, CURR_SLOT.qp_regno, 1); | |
9666 | } | |
800eeca4 | 9667 | else |
542d6675 KH |
9668 | { |
9669 | i = 0; | |
9670 | while (i < regdepslen) | |
9671 | { | |
9672 | if (regdeps[i].qp_regno == CURR_SLOT.qp_regno | |
9673 | && regdeps[i].link_to_qp_branch | |
9674 | && (regdeps[i].file != CURR_SLOT.src_file | |
9675 | || regdeps[i].line != CURR_SLOT.src_line)) | |
9676 | { | |
9677 | /* Treat like a taken branch */ | |
9678 | print_dependency ("Removing", i); | |
9679 | regdeps[i] = regdeps[--regdepslen]; | |
9680 | } | |
9681 | else | |
9682 | ++i; | |
9683 | } | |
9684 | } | |
800eeca4 JW |
9685 | } |
9686 | } | |
9687 | ||
9688 | /* Examine the current instruction for dependency violations. */ | |
542d6675 | 9689 | |
800eeca4 JW |
9690 | static int |
9691 | check_dv (idesc) | |
542d6675 | 9692 | struct ia64_opcode *idesc; |
800eeca4 JW |
9693 | { |
9694 | if (md.debug_dv) | |
9695 | { | |
197865e8 | 9696 | fprintf (stderr, "Checking %s for violations (line %d, %d/%d)\n", |
542d6675 KH |
9697 | idesc->name, CURR_SLOT.src_line, |
9698 | idesc->dependencies->nchks, | |
9699 | idesc->dependencies->nregs); | |
800eeca4 JW |
9700 | } |
9701 | ||
197865e8 | 9702 | /* Look through the list of currently marked resources; if the current |
800eeca4 | 9703 | instruction has the dependency in its chks list which uses that resource, |
542d6675 | 9704 | check against the specific resources used. */ |
800eeca4 JW |
9705 | check_dependencies (idesc); |
9706 | ||
542d6675 KH |
9707 | /* Look up the instruction's regdeps (RAW writes, WAW writes, and WAR reads), |
9708 | then add them to the list of marked resources. */ | |
800eeca4 JW |
9709 | mark_resources (idesc); |
9710 | ||
9711 | /* There are several types of dependency semantics, and each has its own | |
197865e8 KH |
9712 | requirements for being cleared |
9713 | ||
800eeca4 JW |
9714 | Instruction serialization (insns separated by interruption, rfi, or |
9715 | writer + srlz.i + reader, all in separate groups) clears DVS_INSTR. | |
9716 | ||
9717 | Data serialization (instruction serialization, or writer + srlz.d + | |
9718 | reader, where writer and srlz.d are in separate groups) clears | |
9719 | DVS_DATA. (This also clears DVS_OTHER, but that is not guaranteed to | |
9720 | always be the case). | |
9721 | ||
9722 | Instruction group break (groups separated by stop, taken branch, | |
9723 | interruption or rfi) clears DVS_IMPLIED and DVS_IMPLIEDF. | |
9724 | */ | |
9725 | update_dependencies (idesc); | |
9726 | ||
9727 | /* Sometimes, knowing a register value allows us to avoid giving a false DV | |
197865e8 | 9728 | warning. Keep track of as many as possible that are useful. */ |
800eeca4 JW |
9729 | note_register_values (idesc); |
9730 | ||
197865e8 | 9731 | /* We don't need or want this anymore. */ |
800eeca4 JW |
9732 | md.mem_offset.hint = 0; |
9733 | ||
9734 | return 0; | |
9735 | } | |
9736 | ||
9737 | /* Translate one line of assembly. Pseudo ops and labels do not show | |
9738 | here. */ | |
9739 | void | |
9740 | md_assemble (str) | |
9741 | char *str; | |
9742 | { | |
9743 | char *saved_input_line_pointer, *mnemonic; | |
9744 | const struct pseudo_opcode *pdesc; | |
9745 | struct ia64_opcode *idesc; | |
9746 | unsigned char qp_regno; | |
9747 | unsigned int flags; | |
9748 | int ch; | |
9749 | ||
9750 | saved_input_line_pointer = input_line_pointer; | |
9751 | input_line_pointer = str; | |
9752 | ||
542d6675 | 9753 | /* extract the opcode (mnemonic): */ |
800eeca4 JW |
9754 | |
9755 | mnemonic = input_line_pointer; | |
9756 | ch = get_symbol_end (); | |
9757 | pdesc = (struct pseudo_opcode *) hash_find (md.pseudo_hash, mnemonic); | |
9758 | if (pdesc) | |
9759 | { | |
9760 | *input_line_pointer = ch; | |
9761 | (*pdesc->handler) (pdesc->arg); | |
9762 | goto done; | |
9763 | } | |
9764 | ||
542d6675 | 9765 | /* Find the instruction descriptor matching the arguments. */ |
800eeca4 JW |
9766 | |
9767 | idesc = ia64_find_opcode (mnemonic); | |
9768 | *input_line_pointer = ch; | |
9769 | if (!idesc) | |
9770 | { | |
9771 | as_bad ("Unknown opcode `%s'", mnemonic); | |
9772 | goto done; | |
9773 | } | |
9774 | ||
9775 | idesc = parse_operands (idesc); | |
9776 | if (!idesc) | |
9777 | goto done; | |
9778 | ||
542d6675 | 9779 | /* Handle the dynamic ops we can handle now: */ |
800eeca4 JW |
9780 | if (idesc->type == IA64_TYPE_DYN) |
9781 | { | |
9782 | if (strcmp (idesc->name, "add") == 0) | |
9783 | { | |
9784 | if (CURR_SLOT.opnd[2].X_op == O_register | |
9785 | && CURR_SLOT.opnd[2].X_add_number < 4) | |
9786 | mnemonic = "addl"; | |
9787 | else | |
9788 | mnemonic = "adds"; | |
3d56ab85 | 9789 | ia64_free_opcode (idesc); |
800eeca4 JW |
9790 | idesc = ia64_find_opcode (mnemonic); |
9791 | #if 0 | |
9792 | know (!idesc->next); | |
9793 | #endif | |
9794 | } | |
9795 | else if (strcmp (idesc->name, "mov") == 0) | |
9796 | { | |
9797 | enum ia64_opnd opnd1, opnd2; | |
9798 | int rop; | |
9799 | ||
9800 | opnd1 = idesc->operands[0]; | |
9801 | opnd2 = idesc->operands[1]; | |
9802 | if (opnd1 == IA64_OPND_AR3) | |
9803 | rop = 0; | |
9804 | else if (opnd2 == IA64_OPND_AR3) | |
9805 | rop = 1; | |
9806 | else | |
9807 | abort (); | |
9808 | if (CURR_SLOT.opnd[rop].X_op == O_register | |
9809 | && ar_is_in_integer_unit (CURR_SLOT.opnd[rop].X_add_number)) | |
9810 | mnemonic = "mov.i"; | |
9811 | else | |
9812 | mnemonic = "mov.m"; | |
3d56ab85 | 9813 | ia64_free_opcode (idesc); |
800eeca4 JW |
9814 | idesc = ia64_find_opcode (mnemonic); |
9815 | while (idesc != NULL | |
9816 | && (idesc->operands[0] != opnd1 | |
9817 | || idesc->operands[1] != opnd2)) | |
9818 | idesc = get_next_opcode (idesc); | |
9819 | } | |
9820 | } | |
9821 | ||
9822 | qp_regno = 0; | |
9823 | if (md.qp.X_op == O_register) | |
f1bcba5b JW |
9824 | { |
9825 | qp_regno = md.qp.X_add_number - REG_P; | |
9826 | md.qp.X_op = O_absent; | |
9827 | } | |
800eeca4 JW |
9828 | |
9829 | flags = idesc->flags; | |
9830 | ||
9831 | if ((flags & IA64_OPCODE_FIRST) != 0) | |
9832 | insn_group_break (1, 0, 0); | |
9833 | ||
9834 | if ((flags & IA64_OPCODE_NO_PRED) != 0 && qp_regno != 0) | |
9835 | { | |
9836 | as_bad ("`%s' cannot be predicated", idesc->name); | |
9837 | goto done; | |
9838 | } | |
9839 | ||
542d6675 | 9840 | /* Build the instruction. */ |
800eeca4 JW |
9841 | CURR_SLOT.qp_regno = qp_regno; |
9842 | CURR_SLOT.idesc = idesc; | |
9843 | as_where (&CURR_SLOT.src_file, &CURR_SLOT.src_line); | |
4dc7ead9 | 9844 | dwarf2_where (&CURR_SLOT.debug_line); |
800eeca4 JW |
9845 | |
9846 | /* Add unwind entry, if there is one. */ | |
e0c9811a | 9847 | if (unwind.current_entry) |
800eeca4 | 9848 | { |
e0c9811a JW |
9849 | CURR_SLOT.unwind_record = unwind.current_entry; |
9850 | unwind.current_entry = NULL; | |
800eeca4 JW |
9851 | } |
9852 | ||
542d6675 | 9853 | /* Check for dependency violations. */ |
800eeca4 | 9854 | if (md.detect_dv) |
542d6675 | 9855 | check_dv (idesc); |
800eeca4 JW |
9856 | |
9857 | md.curr_slot = (md.curr_slot + 1) % NUM_SLOTS; | |
9858 | if (++md.num_slots_in_use >= NUM_SLOTS) | |
9859 | emit_one_bundle (); | |
9860 | ||
9861 | if ((flags & IA64_OPCODE_LAST) != 0) | |
9862 | insn_group_break (1, 0, 0); | |
9863 | ||
9864 | md.last_text_seg = now_seg; | |
9865 | ||
9866 | done: | |
9867 | input_line_pointer = saved_input_line_pointer; | |
9868 | } | |
9869 | ||
9870 | /* Called when symbol NAME cannot be found in the symbol table. | |
9871 | Should be used for dynamic valued symbols only. */ | |
542d6675 KH |
9872 | |
9873 | symbolS * | |
800eeca4 | 9874 | md_undefined_symbol (name) |
2434f565 | 9875 | char *name ATTRIBUTE_UNUSED; |
800eeca4 JW |
9876 | { |
9877 | return 0; | |
9878 | } | |
9879 | ||
9880 | /* Called for any expression that can not be recognized. When the | |
9881 | function is called, `input_line_pointer' will point to the start of | |
9882 | the expression. */ | |
542d6675 | 9883 | |
800eeca4 JW |
9884 | void |
9885 | md_operand (e) | |
9886 | expressionS *e; | |
9887 | { | |
9888 | enum pseudo_type pseudo_type; | |
e0c9811a | 9889 | const char *name; |
800eeca4 JW |
9890 | size_t len; |
9891 | int ch, i; | |
9892 | ||
9893 | switch (*input_line_pointer) | |
9894 | { | |
9895 | case '@': | |
542d6675 | 9896 | /* Find what relocation pseudo-function we're dealing with. */ |
800eeca4 JW |
9897 | pseudo_type = 0; |
9898 | ch = *++input_line_pointer; | |
9899 | for (i = 0; i < NELEMS (pseudo_func); ++i) | |
9900 | if (pseudo_func[i].name && pseudo_func[i].name[0] == ch) | |
9901 | { | |
9902 | len = strlen (pseudo_func[i].name); | |
9903 | if (strncmp (pseudo_func[i].name + 1, | |
9904 | input_line_pointer + 1, len - 1) == 0 | |
9905 | && !is_part_of_name (input_line_pointer[len])) | |
9906 | { | |
9907 | input_line_pointer += len; | |
9908 | pseudo_type = pseudo_func[i].type; | |
9909 | break; | |
9910 | } | |
9911 | } | |
9912 | switch (pseudo_type) | |
9913 | { | |
9914 | case PSEUDO_FUNC_RELOC: | |
9915 | SKIP_WHITESPACE (); | |
9916 | if (*input_line_pointer != '(') | |
9917 | { | |
9918 | as_bad ("Expected '('"); | |
9919 | goto err; | |
9920 | } | |
542d6675 KH |
9921 | /* Skip '('. */ |
9922 | ++input_line_pointer; | |
800eeca4 JW |
9923 | expression (e); |
9924 | if (*input_line_pointer++ != ')') | |
9925 | { | |
9926 | as_bad ("Missing ')'"); | |
9927 | goto err; | |
9928 | } | |
9929 | if (e->X_op != O_symbol) | |
9930 | { | |
9931 | if (e->X_op != O_pseudo_fixup) | |
9932 | { | |
9933 | as_bad ("Not a symbolic expression"); | |
9934 | goto err; | |
9935 | } | |
13ae64f3 JJ |
9936 | if (i != FUNC_LT_RELATIVE) |
9937 | { | |
9938 | as_bad ("Illegal combination of relocation functions"); | |
9939 | goto err; | |
9940 | } | |
9941 | switch (S_GET_VALUE (e->X_op_symbol)) | |
800eeca4 | 9942 | { |
13ae64f3 JJ |
9943 | case FUNC_FPTR_RELATIVE: |
9944 | i = FUNC_LT_FPTR_RELATIVE; break; | |
9945 | case FUNC_DTP_MODULE: | |
9946 | i = FUNC_LT_DTP_MODULE; break; | |
9947 | case FUNC_DTP_RELATIVE: | |
9948 | i = FUNC_LT_DTP_RELATIVE; break; | |
9949 | case FUNC_TP_RELATIVE: | |
9950 | i = FUNC_LT_TP_RELATIVE; break; | |
9951 | default: | |
800eeca4 JW |
9952 | as_bad ("Illegal combination of relocation functions"); |
9953 | goto err; | |
9954 | } | |
9955 | } | |
542d6675 KH |
9956 | /* Make sure gas doesn't get rid of local symbols that are used |
9957 | in relocs. */ | |
800eeca4 JW |
9958 | e->X_op = O_pseudo_fixup; |
9959 | e->X_op_symbol = pseudo_func[i].u.sym; | |
9960 | break; | |
9961 | ||
9962 | case PSEUDO_FUNC_CONST: | |
9963 | e->X_op = O_constant; | |
9964 | e->X_add_number = pseudo_func[i].u.ival; | |
9965 | break; | |
9966 | ||
e0c9811a JW |
9967 | case PSEUDO_FUNC_REG: |
9968 | e->X_op = O_register; | |
9969 | e->X_add_number = pseudo_func[i].u.ival; | |
9970 | break; | |
9971 | ||
800eeca4 | 9972 | default: |
e0c9811a JW |
9973 | name = input_line_pointer - 1; |
9974 | get_symbol_end (); | |
9975 | as_bad ("Unknown pseudo function `%s'", name); | |
800eeca4 JW |
9976 | goto err; |
9977 | } | |
9978 | break; | |
9979 | ||
9980 | case '[': | |
9981 | ++input_line_pointer; | |
9982 | expression (e); | |
9983 | if (*input_line_pointer != ']') | |
9984 | { | |
9985 | as_bad ("Closing bracket misssing"); | |
9986 | goto err; | |
9987 | } | |
9988 | else | |
9989 | { | |
9990 | if (e->X_op != O_register) | |
9991 | as_bad ("Register expected as index"); | |
9992 | ||
9993 | ++input_line_pointer; | |
9994 | e->X_op = O_index; | |
9995 | } | |
9996 | break; | |
9997 | ||
9998 | default: | |
9999 | break; | |
10000 | } | |
10001 | return; | |
10002 | ||
10003 | err: | |
10004 | ignore_rest_of_line (); | |
10005 | } | |
10006 | ||
10007 | /* Return 1 if it's OK to adjust a reloc by replacing the symbol with | |
10008 | a section symbol plus some offset. For relocs involving @fptr(), | |
10009 | directives we don't want such adjustments since we need to have the | |
10010 | original symbol's name in the reloc. */ | |
10011 | int | |
10012 | ia64_fix_adjustable (fix) | |
10013 | fixS *fix; | |
10014 | { | |
10015 | /* Prevent all adjustments to global symbols */ | |
10016 | if (S_IS_EXTERN (fix->fx_addsy) || S_IS_WEAK (fix->fx_addsy)) | |
10017 | return 0; | |
10018 | ||
10019 | switch (fix->fx_r_type) | |
10020 | { | |
10021 | case BFD_RELOC_IA64_FPTR64I: | |
10022 | case BFD_RELOC_IA64_FPTR32MSB: | |
10023 | case BFD_RELOC_IA64_FPTR32LSB: | |
10024 | case BFD_RELOC_IA64_FPTR64MSB: | |
10025 | case BFD_RELOC_IA64_FPTR64LSB: | |
10026 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
10027 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
10028 | return 0; | |
10029 | default: | |
10030 | break; | |
10031 | } | |
10032 | ||
10033 | return 1; | |
10034 | } | |
10035 | ||
10036 | int | |
10037 | ia64_force_relocation (fix) | |
10038 | fixS *fix; | |
10039 | { | |
10040 | switch (fix->fx_r_type) | |
10041 | { | |
10042 | case BFD_RELOC_IA64_FPTR64I: | |
10043 | case BFD_RELOC_IA64_FPTR32MSB: | |
10044 | case BFD_RELOC_IA64_FPTR32LSB: | |
10045 | case BFD_RELOC_IA64_FPTR64MSB: | |
10046 | case BFD_RELOC_IA64_FPTR64LSB: | |
10047 | ||
10048 | case BFD_RELOC_IA64_LTOFF22: | |
10049 | case BFD_RELOC_IA64_LTOFF64I: | |
10050 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
10051 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
10052 | case BFD_RELOC_IA64_PLTOFF22: | |
10053 | case BFD_RELOC_IA64_PLTOFF64I: | |
10054 | case BFD_RELOC_IA64_PLTOFF64MSB: | |
10055 | case BFD_RELOC_IA64_PLTOFF64LSB: | |
fa2c7eff RH |
10056 | |
10057 | case BFD_RELOC_IA64_LTOFF22X: | |
10058 | case BFD_RELOC_IA64_LDXMOV: | |
800eeca4 JW |
10059 | return 1; |
10060 | ||
10061 | default: | |
a161fe53 | 10062 | break; |
800eeca4 | 10063 | } |
a161fe53 | 10064 | |
ae6063d4 | 10065 | return generic_force_reloc (fix); |
800eeca4 JW |
10066 | } |
10067 | ||
10068 | /* Decide from what point a pc-relative relocation is relative to, | |
10069 | relative to the pc-relative fixup. Er, relatively speaking. */ | |
10070 | long | |
10071 | ia64_pcrel_from_section (fix, sec) | |
10072 | fixS *fix; | |
10073 | segT sec; | |
10074 | { | |
10075 | unsigned long off = fix->fx_frag->fr_address + fix->fx_where; | |
197865e8 | 10076 | |
800eeca4 JW |
10077 | if (bfd_get_section_flags (stdoutput, sec) & SEC_CODE) |
10078 | off &= ~0xfUL; | |
10079 | ||
10080 | return off; | |
10081 | } | |
10082 | ||
6174d9c8 RH |
10083 | |
10084 | /* Used to emit section-relative relocs for the dwarf2 debug data. */ | |
10085 | void | |
10086 | ia64_dwarf2_emit_offset (symbolS *symbol, unsigned int size) | |
10087 | { | |
10088 | expressionS expr; | |
10089 | ||
10090 | expr.X_op = O_pseudo_fixup; | |
10091 | expr.X_op_symbol = pseudo_func[FUNC_SEC_RELATIVE].u.sym; | |
10092 | expr.X_add_number = 0; | |
10093 | expr.X_add_symbol = symbol; | |
10094 | emit_expr (&expr, size); | |
10095 | } | |
10096 | ||
800eeca4 JW |
10097 | /* This is called whenever some data item (not an instruction) needs a |
10098 | fixup. We pick the right reloc code depending on the byteorder | |
10099 | currently in effect. */ | |
10100 | void | |
10101 | ia64_cons_fix_new (f, where, nbytes, exp) | |
10102 | fragS *f; | |
10103 | int where; | |
10104 | int nbytes; | |
10105 | expressionS *exp; | |
10106 | { | |
10107 | bfd_reloc_code_real_type code; | |
10108 | fixS *fix; | |
10109 | ||
10110 | switch (nbytes) | |
10111 | { | |
10112 | /* There are no reloc for 8 and 16 bit quantities, but we allow | |
10113 | them here since they will work fine as long as the expression | |
10114 | is fully defined at the end of the pass over the source file. */ | |
10115 | case 1: code = BFD_RELOC_8; break; | |
10116 | case 2: code = BFD_RELOC_16; break; | |
10117 | case 4: | |
10118 | if (target_big_endian) | |
10119 | code = BFD_RELOC_IA64_DIR32MSB; | |
10120 | else | |
10121 | code = BFD_RELOC_IA64_DIR32LSB; | |
10122 | break; | |
10123 | ||
10124 | case 8: | |
40449e9f | 10125 | /* In 32-bit mode, data8 could mean function descriptors too. */ |
5f44c186 | 10126 | if (exp->X_op == O_pseudo_fixup |
40449e9f KH |
10127 | && exp->X_op_symbol |
10128 | && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC | |
10129 | && !(md.flags & EF_IA_64_ABI64)) | |
10130 | { | |
10131 | if (target_big_endian) | |
10132 | code = BFD_RELOC_IA64_IPLTMSB; | |
10133 | else | |
10134 | code = BFD_RELOC_IA64_IPLTLSB; | |
10135 | exp->X_op = O_symbol; | |
10136 | break; | |
10137 | } | |
10138 | else | |
10139 | { | |
10140 | if (target_big_endian) | |
10141 | code = BFD_RELOC_IA64_DIR64MSB; | |
10142 | else | |
10143 | code = BFD_RELOC_IA64_DIR64LSB; | |
10144 | break; | |
10145 | } | |
800eeca4 | 10146 | |
3969b680 RH |
10147 | case 16: |
10148 | if (exp->X_op == O_pseudo_fixup | |
10149 | && exp->X_op_symbol | |
10150 | && S_GET_VALUE (exp->X_op_symbol) == FUNC_IPLT_RELOC) | |
10151 | { | |
10152 | if (target_big_endian) | |
10153 | code = BFD_RELOC_IA64_IPLTMSB; | |
10154 | else | |
10155 | code = BFD_RELOC_IA64_IPLTLSB; | |
3969b680 RH |
10156 | exp->X_op = O_symbol; |
10157 | break; | |
10158 | } | |
10159 | /* FALLTHRU */ | |
10160 | ||
800eeca4 JW |
10161 | default: |
10162 | as_bad ("Unsupported fixup size %d", nbytes); | |
10163 | ignore_rest_of_line (); | |
10164 | return; | |
10165 | } | |
6174d9c8 | 10166 | |
800eeca4 JW |
10167 | if (exp->X_op == O_pseudo_fixup) |
10168 | { | |
800eeca4 JW |
10169 | exp->X_op = O_symbol; |
10170 | code = ia64_gen_real_reloc_type (exp->X_op_symbol, code); | |
6174d9c8 | 10171 | /* ??? If code unchanged, unsupported. */ |
800eeca4 | 10172 | } |
3969b680 | 10173 | |
800eeca4 JW |
10174 | fix = fix_new_exp (f, where, nbytes, exp, 0, code); |
10175 | /* We need to store the byte order in effect in case we're going | |
10176 | to fix an 8 or 16 bit relocation (for which there no real | |
94f592af | 10177 | relocs available). See md_apply_fix3(). */ |
800eeca4 JW |
10178 | fix->tc_fix_data.bigendian = target_big_endian; |
10179 | } | |
10180 | ||
10181 | /* Return the actual relocation we wish to associate with the pseudo | |
10182 | reloc described by SYM and R_TYPE. SYM should be one of the | |
197865e8 | 10183 | symbols in the pseudo_func array, or NULL. */ |
800eeca4 JW |
10184 | |
10185 | static bfd_reloc_code_real_type | |
10186 | ia64_gen_real_reloc_type (sym, r_type) | |
10187 | struct symbol *sym; | |
10188 | bfd_reloc_code_real_type r_type; | |
10189 | { | |
10190 | bfd_reloc_code_real_type new = 0; | |
10191 | ||
10192 | if (sym == NULL) | |
10193 | { | |
10194 | return r_type; | |
10195 | } | |
10196 | ||
10197 | switch (S_GET_VALUE (sym)) | |
10198 | { | |
10199 | case FUNC_FPTR_RELATIVE: | |
10200 | switch (r_type) | |
10201 | { | |
10202 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_FPTR64I; break; | |
10203 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_FPTR32MSB; break; | |
10204 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_FPTR32LSB; break; | |
10205 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_FPTR64MSB; break; | |
10206 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_FPTR64LSB; break; | |
10207 | default: break; | |
10208 | } | |
10209 | break; | |
10210 | ||
10211 | case FUNC_GP_RELATIVE: | |
10212 | switch (r_type) | |
10213 | { | |
10214 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_GPREL22; break; | |
10215 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_GPREL64I; break; | |
10216 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_GPREL32MSB; break; | |
10217 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_GPREL32LSB; break; | |
10218 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_GPREL64MSB; break; | |
10219 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_GPREL64LSB; break; | |
10220 | default: break; | |
10221 | } | |
10222 | break; | |
10223 | ||
10224 | case FUNC_LT_RELATIVE: | |
10225 | switch (r_type) | |
10226 | { | |
10227 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22; break; | |
10228 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_LTOFF64I; break; | |
10229 | default: break; | |
10230 | } | |
10231 | break; | |
10232 | ||
fa2c7eff RH |
10233 | case FUNC_LT_RELATIVE_X: |
10234 | switch (r_type) | |
10235 | { | |
10236 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_LTOFF22X; break; | |
10237 | default: break; | |
10238 | } | |
10239 | break; | |
10240 | ||
c67e42c9 RH |
10241 | case FUNC_PC_RELATIVE: |
10242 | switch (r_type) | |
10243 | { | |
10244 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PCREL22; break; | |
10245 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PCREL64I; break; | |
10246 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_PCREL32MSB; break; | |
10247 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_PCREL32LSB; break; | |
10248 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PCREL64MSB; break; | |
10249 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PCREL64LSB; break; | |
10250 | default: break; | |
10251 | } | |
10252 | break; | |
10253 | ||
800eeca4 JW |
10254 | case FUNC_PLT_RELATIVE: |
10255 | switch (r_type) | |
10256 | { | |
10257 | case BFD_RELOC_IA64_IMM22: new = BFD_RELOC_IA64_PLTOFF22; break; | |
10258 | case BFD_RELOC_IA64_IMM64: new = BFD_RELOC_IA64_PLTOFF64I; break; | |
10259 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_PLTOFF64MSB;break; | |
10260 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_PLTOFF64LSB;break; | |
10261 | default: break; | |
10262 | } | |
10263 | break; | |
10264 | ||
10265 | case FUNC_SEC_RELATIVE: | |
10266 | switch (r_type) | |
10267 | { | |
10268 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SECREL32MSB;break; | |
10269 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SECREL32LSB;break; | |
10270 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SECREL64MSB;break; | |
10271 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SECREL64LSB;break; | |
10272 | default: break; | |
10273 | } | |
10274 | break; | |
10275 | ||
10276 | case FUNC_SEG_RELATIVE: | |
10277 | switch (r_type) | |
10278 | { | |
10279 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_SEGREL32MSB;break; | |
10280 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_SEGREL32LSB;break; | |
10281 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_SEGREL64MSB;break; | |
10282 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_SEGREL64LSB;break; | |
10283 | default: break; | |
10284 | } | |
10285 | break; | |
10286 | ||
10287 | case FUNC_LTV_RELATIVE: | |
10288 | switch (r_type) | |
10289 | { | |
10290 | case BFD_RELOC_IA64_DIR32MSB: new = BFD_RELOC_IA64_LTV32MSB; break; | |
10291 | case BFD_RELOC_IA64_DIR32LSB: new = BFD_RELOC_IA64_LTV32LSB; break; | |
10292 | case BFD_RELOC_IA64_DIR64MSB: new = BFD_RELOC_IA64_LTV64MSB; break; | |
10293 | case BFD_RELOC_IA64_DIR64LSB: new = BFD_RELOC_IA64_LTV64LSB; break; | |
10294 | default: break; | |
10295 | } | |
10296 | break; | |
10297 | ||
10298 | case FUNC_LT_FPTR_RELATIVE: | |
10299 | switch (r_type) | |
10300 | { | |
10301 | case BFD_RELOC_IA64_IMM22: | |
10302 | new = BFD_RELOC_IA64_LTOFF_FPTR22; break; | |
10303 | case BFD_RELOC_IA64_IMM64: | |
10304 | new = BFD_RELOC_IA64_LTOFF_FPTR64I; break; | |
10305 | default: | |
10306 | break; | |
10307 | } | |
10308 | break; | |
3969b680 | 10309 | |
13ae64f3 JJ |
10310 | case FUNC_TP_RELATIVE: |
10311 | switch (r_type) | |
10312 | { | |
10313 | case BFD_RELOC_IA64_IMM14: | |
10314 | new = BFD_RELOC_IA64_TPREL14; break; | |
10315 | case BFD_RELOC_IA64_IMM22: | |
10316 | new = BFD_RELOC_IA64_TPREL22; break; | |
10317 | case BFD_RELOC_IA64_IMM64: | |
10318 | new = BFD_RELOC_IA64_TPREL64I; break; | |
10319 | default: | |
10320 | break; | |
10321 | } | |
10322 | break; | |
10323 | ||
10324 | case FUNC_LT_TP_RELATIVE: | |
10325 | switch (r_type) | |
10326 | { | |
10327 | case BFD_RELOC_IA64_IMM22: | |
10328 | new = BFD_RELOC_IA64_LTOFF_TPREL22; break; | |
10329 | default: | |
10330 | break; | |
10331 | } | |
10332 | break; | |
10333 | ||
10334 | case FUNC_LT_DTP_MODULE: | |
10335 | switch (r_type) | |
10336 | { | |
10337 | case BFD_RELOC_IA64_IMM22: | |
10338 | new = BFD_RELOC_IA64_LTOFF_DTPMOD22; break; | |
10339 | default: | |
10340 | break; | |
10341 | } | |
10342 | break; | |
10343 | ||
10344 | case FUNC_DTP_RELATIVE: | |
10345 | switch (r_type) | |
10346 | { | |
6174d9c8 RH |
10347 | case BFD_RELOC_IA64_DIR64MSB: |
10348 | new = BFD_RELOC_IA64_DTPREL64MSB; break; | |
10349 | case BFD_RELOC_IA64_DIR64LSB: | |
10350 | new = BFD_RELOC_IA64_DTPREL64LSB; break; | |
13ae64f3 JJ |
10351 | case BFD_RELOC_IA64_IMM14: |
10352 | new = BFD_RELOC_IA64_DTPREL14; break; | |
10353 | case BFD_RELOC_IA64_IMM22: | |
10354 | new = BFD_RELOC_IA64_DTPREL22; break; | |
10355 | case BFD_RELOC_IA64_IMM64: | |
10356 | new = BFD_RELOC_IA64_DTPREL64I; break; | |
10357 | default: | |
10358 | break; | |
10359 | } | |
10360 | break; | |
10361 | ||
10362 | case FUNC_LT_DTP_RELATIVE: | |
10363 | switch (r_type) | |
10364 | { | |
10365 | case BFD_RELOC_IA64_IMM22: | |
10366 | new = BFD_RELOC_IA64_LTOFF_DTPREL22; break; | |
10367 | default: | |
10368 | break; | |
10369 | } | |
10370 | break; | |
10371 | ||
40449e9f KH |
10372 | case FUNC_IPLT_RELOC: |
10373 | break; | |
1cd8ff38 | 10374 | |
800eeca4 JW |
10375 | default: |
10376 | abort (); | |
10377 | } | |
6174d9c8 | 10378 | |
800eeca4 JW |
10379 | /* Hmmmm. Should this ever occur? */ |
10380 | if (new) | |
10381 | return new; | |
10382 | else | |
10383 | return r_type; | |
10384 | } | |
10385 | ||
10386 | /* Here is where generate the appropriate reloc for pseudo relocation | |
10387 | functions. */ | |
10388 | void | |
10389 | ia64_validate_fix (fix) | |
10390 | fixS *fix; | |
10391 | { | |
10392 | switch (fix->fx_r_type) | |
10393 | { | |
10394 | case BFD_RELOC_IA64_FPTR64I: | |
10395 | case BFD_RELOC_IA64_FPTR32MSB: | |
10396 | case BFD_RELOC_IA64_FPTR64LSB: | |
10397 | case BFD_RELOC_IA64_LTOFF_FPTR22: | |
10398 | case BFD_RELOC_IA64_LTOFF_FPTR64I: | |
10399 | if (fix->fx_offset != 0) | |
10400 | as_bad_where (fix->fx_file, fix->fx_line, | |
10401 | "No addend allowed in @fptr() relocation"); | |
10402 | break; | |
10403 | default: | |
10404 | break; | |
10405 | } | |
10406 | ||
10407 | return; | |
10408 | } | |
10409 | ||
10410 | static void | |
10411 | fix_insn (fix, odesc, value) | |
10412 | fixS *fix; | |
10413 | const struct ia64_operand *odesc; | |
10414 | valueT value; | |
10415 | { | |
10416 | bfd_vma insn[3], t0, t1, control_bits; | |
10417 | const char *err; | |
10418 | char *fixpos; | |
10419 | long slot; | |
10420 | ||
10421 | slot = fix->fx_where & 0x3; | |
10422 | fixpos = fix->fx_frag->fr_literal + (fix->fx_where - slot); | |
10423 | ||
c67e42c9 | 10424 | /* Bundles are always in little-endian byte order */ |
800eeca4 JW |
10425 | t0 = bfd_getl64 (fixpos); |
10426 | t1 = bfd_getl64 (fixpos + 8); | |
10427 | control_bits = t0 & 0x1f; | |
10428 | insn[0] = (t0 >> 5) & 0x1ffffffffffLL; | |
10429 | insn[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18); | |
10430 | insn[2] = (t1 >> 23) & 0x1ffffffffffLL; | |
10431 | ||
c67e42c9 RH |
10432 | err = NULL; |
10433 | if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64) | |
800eeca4 | 10434 | { |
c67e42c9 RH |
10435 | insn[1] = (value >> 22) & 0x1ffffffffffLL; |
10436 | insn[2] |= (((value & 0x7f) << 13) | |
10437 | | (((value >> 7) & 0x1ff) << 27) | |
10438 | | (((value >> 16) & 0x1f) << 22) | |
10439 | | (((value >> 21) & 0x1) << 21) | |
10440 | | (((value >> 63) & 0x1) << 36)); | |
800eeca4 | 10441 | } |
c67e42c9 RH |
10442 | else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62) |
10443 | { | |
10444 | if (value & ~0x3fffffffffffffffULL) | |
10445 | err = "integer operand out of range"; | |
10446 | insn[1] = (value >> 21) & 0x1ffffffffffLL; | |
10447 | insn[2] |= (((value & 0xfffff) << 6) | (((value >> 20) & 0x1) << 36)); | |
10448 | } | |
10449 | else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) | |
10450 | { | |
10451 | value >>= 4; | |
10452 | insn[1] = ((value >> 20) & 0x7fffffffffLL) << 2; | |
10453 | insn[2] |= ((((value >> 59) & 0x1) << 36) | |
10454 | | (((value >> 0) & 0xfffff) << 13)); | |
10455 | } | |
10456 | else | |
10457 | err = (*odesc->insert) (odesc, value, insn + slot); | |
10458 | ||
10459 | if (err) | |
10460 | as_bad_where (fix->fx_file, fix->fx_line, err); | |
800eeca4 JW |
10461 | |
10462 | t0 = control_bits | (insn[0] << 5) | (insn[1] << 46); | |
10463 | t1 = ((insn[1] >> 18) & 0x7fffff) | (insn[2] << 23); | |
44f5c83a JW |
10464 | number_to_chars_littleendian (fixpos + 0, t0, 8); |
10465 | number_to_chars_littleendian (fixpos + 8, t1, 8); | |
800eeca4 JW |
10466 | } |
10467 | ||
10468 | /* Attempt to simplify or even eliminate a fixup. The return value is | |
10469 | ignored; perhaps it was once meaningful, but now it is historical. | |
10470 | To indicate that a fixup has been eliminated, set FIXP->FX_DONE. | |
10471 | ||
10472 | If fixp->fx_addsy is non-NULL, we'll have to generate a reloc entry | |
197865e8 | 10473 | (if possible). */ |
94f592af NC |
10474 | |
10475 | void | |
10476 | md_apply_fix3 (fix, valP, seg) | |
800eeca4 | 10477 | fixS *fix; |
40449e9f | 10478 | valueT *valP; |
2434f565 | 10479 | segT seg ATTRIBUTE_UNUSED; |
800eeca4 JW |
10480 | { |
10481 | char *fixpos; | |
40449e9f | 10482 | valueT value = *valP; |
800eeca4 JW |
10483 | |
10484 | fixpos = fix->fx_frag->fr_literal + fix->fx_where; | |
10485 | ||
10486 | if (fix->fx_pcrel) | |
10487 | { | |
10488 | switch (fix->fx_r_type) | |
10489 | { | |
10490 | case BFD_RELOC_IA64_DIR32MSB: | |
10491 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB; | |
800eeca4 JW |
10492 | break; |
10493 | ||
10494 | case BFD_RELOC_IA64_DIR32LSB: | |
10495 | fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB; | |
800eeca4 JW |
10496 | break; |
10497 | ||
10498 | case BFD_RELOC_IA64_DIR64MSB: | |
10499 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB; | |
800eeca4 JW |
10500 | break; |
10501 | ||
10502 | case BFD_RELOC_IA64_DIR64LSB: | |
10503 | fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB; | |
800eeca4 JW |
10504 | break; |
10505 | ||
10506 | default: | |
10507 | break; | |
10508 | } | |
10509 | } | |
10510 | if (fix->fx_addsy) | |
10511 | { | |
00f7efb6 | 10512 | switch (fix->fx_r_type) |
800eeca4 | 10513 | { |
00f7efb6 | 10514 | case BFD_RELOC_UNUSED: |
fa1cb89c JW |
10515 | /* This must be a TAG13 or TAG13b operand. There are no external |
10516 | relocs defined for them, so we must give an error. */ | |
800eeca4 JW |
10517 | as_bad_where (fix->fx_file, fix->fx_line, |
10518 | "%s must have a constant value", | |
10519 | elf64_ia64_operands[fix->tc_fix_data.opnd].desc); | |
fa1cb89c | 10520 | fix->fx_done = 1; |
94f592af | 10521 | return; |
00f7efb6 JJ |
10522 | |
10523 | case BFD_RELOC_IA64_TPREL14: | |
10524 | case BFD_RELOC_IA64_TPREL22: | |
10525 | case BFD_RELOC_IA64_TPREL64I: | |
10526 | case BFD_RELOC_IA64_LTOFF_TPREL22: | |
10527 | case BFD_RELOC_IA64_LTOFF_DTPMOD22: | |
10528 | case BFD_RELOC_IA64_DTPREL14: | |
10529 | case BFD_RELOC_IA64_DTPREL22: | |
10530 | case BFD_RELOC_IA64_DTPREL64I: | |
10531 | case BFD_RELOC_IA64_LTOFF_DTPREL22: | |
10532 | S_SET_THREAD_LOCAL (fix->fx_addsy); | |
10533 | break; | |
7925dd68 JJ |
10534 | |
10535 | default: | |
10536 | break; | |
800eeca4 | 10537 | } |
800eeca4 JW |
10538 | } |
10539 | else if (fix->tc_fix_data.opnd == IA64_OPND_NIL) | |
10540 | { | |
10541 | if (fix->tc_fix_data.bigendian) | |
10542 | number_to_chars_bigendian (fixpos, value, fix->fx_size); | |
10543 | else | |
10544 | number_to_chars_littleendian (fixpos, value, fix->fx_size); | |
10545 | fix->fx_done = 1; | |
800eeca4 JW |
10546 | } |
10547 | else | |
10548 | { | |
10549 | fix_insn (fix, elf64_ia64_operands + fix->tc_fix_data.opnd, value); | |
10550 | fix->fx_done = 1; | |
800eeca4 | 10551 | } |
800eeca4 JW |
10552 | } |
10553 | ||
10554 | /* Generate the BFD reloc to be stuck in the object file from the | |
10555 | fixup used internally in the assembler. */ | |
542d6675 KH |
10556 | |
10557 | arelent * | |
800eeca4 | 10558 | tc_gen_reloc (sec, fixp) |
2434f565 | 10559 | asection *sec ATTRIBUTE_UNUSED; |
800eeca4 JW |
10560 | fixS *fixp; |
10561 | { | |
10562 | arelent *reloc; | |
10563 | ||
10564 | reloc = xmalloc (sizeof (*reloc)); | |
10565 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
10566 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
10567 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
10568 | reloc->addend = fixp->fx_offset; | |
10569 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
10570 | ||
10571 | if (!reloc->howto) | |
10572 | { | |
10573 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
10574 | "Cannot represent %s relocation in object file", | |
10575 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
10576 | } | |
10577 | return reloc; | |
10578 | } | |
10579 | ||
10580 | /* Turn a string in input_line_pointer into a floating point constant | |
bc0d738a NC |
10581 | of type TYPE, and store the appropriate bytes in *LIT. The number |
10582 | of LITTLENUMS emitted is stored in *SIZE. An error message is | |
800eeca4 JW |
10583 | returned, or NULL on OK. */ |
10584 | ||
10585 | #define MAX_LITTLENUMS 5 | |
10586 | ||
542d6675 | 10587 | char * |
800eeca4 JW |
10588 | md_atof (type, lit, size) |
10589 | int type; | |
10590 | char *lit; | |
10591 | int *size; | |
10592 | { | |
10593 | LITTLENUM_TYPE words[MAX_LITTLENUMS]; | |
800eeca4 JW |
10594 | char *t; |
10595 | int prec; | |
10596 | ||
10597 | switch (type) | |
10598 | { | |
10599 | /* IEEE floats */ | |
10600 | case 'f': | |
10601 | case 'F': | |
10602 | case 's': | |
10603 | case 'S': | |
10604 | prec = 2; | |
10605 | break; | |
10606 | ||
10607 | case 'd': | |
10608 | case 'D': | |
10609 | case 'r': | |
10610 | case 'R': | |
10611 | prec = 4; | |
10612 | break; | |
10613 | ||
10614 | case 'x': | |
10615 | case 'X': | |
10616 | case 'p': | |
10617 | case 'P': | |
10618 | prec = 5; | |
10619 | break; | |
10620 | ||
10621 | default: | |
10622 | *size = 0; | |
10623 | return "Bad call to MD_ATOF()"; | |
10624 | } | |
10625 | t = atof_ieee (input_line_pointer, type, words); | |
10626 | if (t) | |
10627 | input_line_pointer = t; | |
800eeca4 | 10628 | |
10a98291 L |
10629 | (*ia64_float_to_chars) (lit, words, prec); |
10630 | ||
165a7f90 L |
10631 | if (type == 'X') |
10632 | { | |
10633 | /* It is 10 byte floating point with 6 byte padding. */ | |
10a98291 | 10634 | memset (&lit [10], 0, 6); |
165a7f90 L |
10635 | *size = 8 * sizeof (LITTLENUM_TYPE); |
10636 | } | |
10a98291 L |
10637 | else |
10638 | *size = prec * sizeof (LITTLENUM_TYPE); | |
10639 | ||
800eeca4 JW |
10640 | return 0; |
10641 | } | |
10642 | ||
800eeca4 JW |
10643 | /* Handle ia64 specific semantics of the align directive. */ |
10644 | ||
0a9ef439 | 10645 | void |
800eeca4 | 10646 | ia64_md_do_align (n, fill, len, max) |
91a2ae2a RH |
10647 | int n ATTRIBUTE_UNUSED; |
10648 | const char *fill ATTRIBUTE_UNUSED; | |
2434f565 | 10649 | int len ATTRIBUTE_UNUSED; |
91a2ae2a | 10650 | int max ATTRIBUTE_UNUSED; |
800eeca4 | 10651 | { |
0a9ef439 | 10652 | if (subseg_text_p (now_seg)) |
800eeca4 | 10653 | ia64_flush_insns (); |
0a9ef439 | 10654 | } |
800eeca4 | 10655 | |
0a9ef439 RH |
10656 | /* This is called from HANDLE_ALIGN in write.c. Fill in the contents |
10657 | of an rs_align_code fragment. */ | |
800eeca4 | 10658 | |
0a9ef439 RH |
10659 | void |
10660 | ia64_handle_align (fragp) | |
10661 | fragS *fragp; | |
10662 | { | |
10663 | /* Use mfi bundle of nops with no stop bits. */ | |
10664 | static const unsigned char be_nop[] | |
10665 | = { 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, | |
10666 | 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0c}; | |
10667 | static const unsigned char le_nop[] | |
10668 | = { 0x0c, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, | |
10669 | 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00}; | |
10670 | ||
10671 | int bytes; | |
10672 | char *p; | |
10673 | ||
10674 | if (fragp->fr_type != rs_align_code) | |
10675 | return; | |
10676 | ||
10677 | bytes = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; | |
10678 | p = fragp->fr_literal + fragp->fr_fix; | |
10679 | ||
10680 | /* Make sure we are on a 16-byte boundary, in case someone has been | |
10681 | putting data into a text section. */ | |
10682 | if (bytes & 15) | |
10683 | { | |
10684 | int fix = bytes & 15; | |
10685 | memset (p, 0, fix); | |
10686 | p += fix; | |
10687 | bytes -= fix; | |
10688 | fragp->fr_fix += fix; | |
800eeca4 JW |
10689 | } |
10690 | ||
0a9ef439 RH |
10691 | memcpy (p, (target_big_endian ? be_nop : le_nop), 16); |
10692 | fragp->fr_var = 16; | |
800eeca4 | 10693 | } |
10a98291 L |
10694 | |
10695 | static void | |
10696 | ia64_float_to_chars_bigendian (char *lit, LITTLENUM_TYPE *words, | |
10697 | int prec) | |
10698 | { | |
10699 | while (prec--) | |
10700 | { | |
10701 | number_to_chars_bigendian (lit, (long) (*words++), | |
10702 | sizeof (LITTLENUM_TYPE)); | |
10703 | lit += sizeof (LITTLENUM_TYPE); | |
10704 | } | |
10705 | } | |
10706 | ||
10707 | static void | |
10708 | ia64_float_to_chars_littleendian (char *lit, LITTLENUM_TYPE *words, | |
10709 | int prec) | |
10710 | { | |
10711 | while (prec--) | |
10712 | { | |
10713 | number_to_chars_littleendian (lit, (long) (words[prec]), | |
10714 | sizeof (LITTLENUM_TYPE)); | |
10715 | lit += sizeof (LITTLENUM_TYPE); | |
10716 | } | |
10717 | } | |
10718 | ||
10719 | void | |
10720 | ia64_elf_section_change_hook (void) | |
10721 | { | |
10722 | dot_byteorder (-1); | |
10723 | } |