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[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
82704155 2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
252b5132
RH		 3
4 This file is part of GAS, the GNU Assembler.
5
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
ec2655a6 8 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 9 any later version.
10
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
252b5132 20
252b5132 21#include "as.h"
3882b010 22#include "safe-ctype.h"
252b5132
RH		 23#include "obstack.h"
24#include "subsegs.h"
f27a3839 25#include "dwarf2dbg.h"
c04898f8 26#include "dw2gencfi.h"
252b5132
RH		 27
28#include "opcode/m68k.h"
29#include "m68k-parse.h"
0d96863f 30#include "elf/m68k.h"
31302357 31
cf869cce 32static void m68k_elf_cons (int);
cf869cce 33
252b5132
RH		 34/* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38#if defined (TE_SVR4) || defined (TE_DELTA)
39const char *m68k_comment_chars = "|#";
40#else
41const char *m68k_comment_chars = "|";
42#endif
43
44/* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47/* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
92774660
KH		 49 #NO_APP at the beginning of its output. */
50/* Also note that comments like this one will always work. */
252b5132
RH		 51const char line_comment_chars[] = "#*";
52
63a0b638 53const char line_separator_chars[] = ";";
252b5132 54
36759679 55/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 56const char EXP_CHARS[] = "eE";
252b5132
RH		 57
58/* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
5a38dc70 61const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 62
63/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
252b5132
RH		 67/* Are we trying to generate PIC code? If so, absolute references
68 ought to be made into linkage table references or pc-relative
92774660 69 references. Not implemented. For ELF there are other means
252b5132
RH		 70 to denote pic relocations. */
71int flag_want_pic;
72
36759679
NC		 73static int flag_short_refs; /* -l option. */
74static int flag_long_jumps; /* -S option. */
28e7409f 75static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 76
77#ifdef REGISTER_PREFIX_OPTIONAL
78int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
79#else
80int flag_reg_prefix_optional;
81#endif
82
83/* Whether --register-prefix-optional was used on the command line. */
84static int reg_prefix_optional_seen;
85
86/* The floating point coprocessor to use by default. */
87static enum m68k_register m68k_float_copnum = COP1;
88
89/* If this is non-zero, then references to number(%pc) will be taken
90 to refer to number, rather than to %pc + number. */
91static int m68k_abspcadd;
92
93/* If this is non-zero, then the quick forms of the move, add, and sub
94 instructions are used when possible. */
95static int m68k_quick = 1;
96
97/* If this is non-zero, then if the size is not specified for a base
98 or outer displacement, the assembler assumes that the size should
99 be 32 bits. */
100static int m68k_rel32 = 1;
101
102/* This is non-zero if m68k_rel32 was set from the command line. */
103static int m68k_rel32_from_cmdline;
104
105/* The default width to use for an index register when using a base
106 displacement. */
107static enum m68k_size m68k_index_width_default = SIZE_LONG;
108
109/* We want to warn if any text labels are misaligned. In order to get
110 the right line number, we need to record the line number for each
111 label. */
252b5132
RH		 112struct label_line
113{
114 struct label_line *next;
115 symbolS *label;
3b4dbbbf 116 const char *file;
252b5132
RH		 117 unsigned int line;
118 int text;
119};
120
121/* The list of labels. */
122
123static struct label_line *labels;
124
125/* The current label. */
126
127static struct label_line *current_label;
128
60fed2d3
NC		 129/* Pointer to list holding the opcodes sorted by name. */
130static struct m68k_opcode const ** m68k_sorted_opcodes;
131
33eaf5de 132/* It's an arbitrary name: This means I don't approve of it.
36759679 133 See flames below. */
252b5132
RH		 134static struct obstack robyn;
135
252b5132
RH		 136struct m68k_incant
137 {
138 const char *m_operands;
139 unsigned long m_opcode;
140 short m_opnum;
141 short m_codenum;
142 int m_arch;
143 struct m68k_incant *m_next;
144 };
145
146#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
147#define gettwo(x) (((x)->m_opcode)&0xffff)
148
2da12c60
NS		 149static const enum m68k_register m68000_ctrl[] = { 0 };
150static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 151 SFC, DFC, USP, VBR,
152 0
153};
2da12c60 154static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 155 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
156 0
157};
2da12c60 158static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
160 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
161 0
162};
2da12c60 163static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 164 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
165 USP, VBR, URP, SRP, PCR,
166 0
167};
2da12c60 168static const enum m68k_register mcf_ctrl[] = {
3e602632 169 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 170 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
171 0
172};
87298967
NS		 173static const enum m68k_register mcf51_ctrl[] = {
174 VBR, CPUCR,
f75192f2
KH		 175 0
176};
78336706 177static const enum m68k_register mcf5206_ctrl[] = {
0d999f33 178 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 179 0
180};
2da12c60 181static const enum m68k_register mcf5208_ctrl[] = {
78336706 182 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 183 0
184};
96e0bbcc 185static const enum m68k_register mcf5210a_ctrl[] = {
78336706 186 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 187 0
188};
2da12c60 189static const enum m68k_register mcf5213_ctrl[] = {
78336706 190 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 191 0
192};
2da12c60 193static const enum m68k_register mcf5216_ctrl[] = {
78336706 194 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 195 0
196};
46203761
MK		 197static const enum m68k_register mcf5221x_ctrl[] = {
198 VBR, FLASHBAR, RAMBAR, RAMBAR1,
199 0
200};
d5be9593 201static const enum m68k_register mcf52223_ctrl[] = {
0d999f33 202 VBR, FLASHBAR, RAMBAR, RAMBAR1,
d5be9593
NS		 203 0
204};
96e0bbcc 205static const enum m68k_register mcf52235_ctrl[] = {
b345c8c2 206 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 207 0
208};
209static const enum m68k_register mcf5225_ctrl[] = {
78336706 210 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 211 0
212};
87298967
NS		 213static const enum m68k_register mcf52259_ctrl[] = {
214 VBR, FLASHBAR, RAMBAR, RAMBAR1,
215 0
216};
217static const enum m68k_register mcf52277_ctrl[] = {
218 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
219 0
220};
2da12c60 221static const enum m68k_register mcf5235_ctrl[] = {
78336706 222 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 223 0
224};
2da12c60 225static const enum m68k_register mcf5249_ctrl[] = {
78336706 226 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 227 0
228};
2da12c60
NS		 229static const enum m68k_register mcf5250_ctrl[] = {
230 VBR,
231 0
232};
d5be9593 233static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 234 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 235 0
236};
2da12c60 237static const enum m68k_register mcf5271_ctrl[] = {
78336706 238 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 239 0
240};
241static const enum m68k_register mcf5272_ctrl[] = {
78336706 242 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 243 0
244};
245static const enum m68k_register mcf5275_ctrl[] = {
78336706 246 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 247 0
248};
249static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 250 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
251 0
252};
87298967 253static const enum m68k_register mcf53017_ctrl[] = {
b345c8c2 254 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
87298967
NS		 255 0
256};
78336706 257static const enum m68k_register mcf5307_ctrl[] = {
87298967 258 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 259 0
260};
261static const enum m68k_register mcf5329_ctrl[] = {
78336706 262 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 263 0
264};
265static const enum m68k_register mcf5373_ctrl[] = {
78336706 266 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 267 0
268};
269static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 270 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
271 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
272 MBAR, SECMBAR,
273 MPCR /* Multiprocessor Control register */,
274 EDRAMBAR /* Embedded DRAM Base Address Register */,
275 /* Permutation control registers. */
3e602632
NC		 276 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
277 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 278 /* Legacy names */
279 TC /* ASID */, BUSCR /* MMUBAR */,
280 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
281 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 282 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 283 0
284};
def8fc92
KH		 285static const enum m68k_register mcf5407_ctrl[] = {
286 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
287 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
288 /* Legacy names */
289 TC /* ASID */,
290 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
291 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
292 0
293};
0d999f33
MK		 294static const enum m68k_register mcf54418_ctrl[] = {
295 CACR, ASID, ACR0, ACR1, ACR2, ACR3, ACR4, ACR5, ACR6, ACR7, MMUBAR, RGPIOBAR,
296 VBR, PC, RAMBAR1,
297 /* Legacy names */
298 TC /* ASID */, BUSCR /* MMUBAR */,
299 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
300 RAMBAR /* RAMBAR1 */,
301 0
302};
9a2e615a
NS		 303static const enum m68k_register mcf54455_ctrl[] = {
304 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
0d999f33 305 VBR, PC, RAMBAR1,
9a2e615a
NS		 306 /* Legacy names */
307 TC /* ASID */, BUSCR /* MMUBAR */,
308 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
0d999f33 309 RAMBAR /* RAMBAR1 */,
9a2e615a
NS		 310 0
311};
a8e24a56
NS		 312static const enum m68k_register mcf5475_ctrl[] = {
313 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
314 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
315 /* Legacy names */
316 TC /* ASID */, BUSCR /* MMUBAR */,
317 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 318 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 319 0
320};
321static const enum m68k_register mcf5485_ctrl[] = {
322 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
323 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
324 /* Legacy names */
325 TC /* ASID */, BUSCR /* MMUBAR */,
326 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 327 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 328 0
329};
f7ec513b 330static const enum m68k_register fido_ctrl[] = {
d0fa1372 331 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 332 0
333};
2da12c60 334#define cpu32_ctrl m68010_ctrl
252b5132
RH		 335
336static const enum m68k_register *control_regs;
337
36759679 338/* Internal form of a 68020 instruction. */
252b5132
RH		 339struct m68k_it
340{
341 const char *error;
36759679 342 const char *args; /* List of opcode info. */
252b5132
RH		 343 int numargs;
344
36759679 345 int numo; /* Number of shorts in opcode. */
252b5132
RH		 346 short opcode[11];
347
348 struct m68k_op operands[6];
349
36759679 350 int nexp; /* Number of exprs in use. */
252b5132
RH		 351 struct m68k_exp exprs[4];
352
36759679 353 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 354 struct
355 {
36759679 356 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 357 symbolS *fadd;
358 offsetT foff;
359 int fragty;
360 }
361 fragb[4];
362
33eaf5de 363 int nrel; /* Num of reloc structs in use. */
252b5132
RH		 364 struct
365 {
366 int n;
367 expressionS exp;
368 char wid;
369 char pcrel;
370 /* In a pc relative address the difference between the address
371 of the offset and the address that the offset is relative
372 to. This depends on the addressing mode. Basically this
373 is the value to put in the offset field to address the
374 first byte of the offset, without regarding the special
375 significance of some values (in the branch instruction, for
376 example). */
377 int pcrel_fix;
252b5132
RH		 378 /* Whether this expression needs special pic relocation, and if
379 so, which. */
380 enum pic_relocation pic_reloc;
252b5132 381 }
36759679 382 reloc[5]; /* Five is enough??? */
252b5132
RH		 383};
384
9840d27e 385#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 386#define float_of_arch(x) ((x) & mfloat)
387#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 388#define arch_coldfire_p(x) ((x) & mcfisa_a)
389#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 390
36759679 391/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 392#define HAVE_LONG_DISP(x) \
393 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
394#define HAVE_LONG_CALL(x) \
395 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
396#define HAVE_LONG_COND(x) \
397 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
398#define HAVE_LONG_BRANCH(x) \
399 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 400#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 401
36759679 402static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 403
404#define op(ex) ((ex)->exp.X_op)
405#define adds(ex) ((ex)->exp.X_add_symbol)
406#define subs(ex) ((ex)->exp.X_op_symbol)
407#define offs(ex) ((ex)->exp.X_add_number)
408
36759679 409/* Macros for adding things to the m68k_it struct. */
31302357 410#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 411
36759679
NC		 412/* Like addword, but goes BEFORE general operands. */
413
252b5132 414static void
31302357 415insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 416{
417 int z;
07726851 418 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 419 the_ins.opcode[z] = the_ins.opcode[z - 1];
420 for (z = 0; z < the_ins.nrel; z++)
421 the_ins.reloc[z].n += 2;
252b5132
RH		 422 for (z = 0; z < the_ins.nfrag; z++)
423 the_ins.fragb[z].fragoff++;
8a104df9 424 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 425 the_ins.numo++;
426}
427
428/* The numo+1 kludge is so we can hit the low order byte of the prev word.
429 Blecch. */
430static void
31302357 431add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 432{
31302357
AS		 433 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
434 ? the_ins.numo * 2 - 1
435 : (width == 'b'
436 ? the_ins.numo * 2 + 1
437 : the_ins.numo * 2));
252b5132
RH		 438 the_ins.reloc[the_ins.nrel].exp = exp->exp;
439 the_ins.reloc[the_ins.nrel].wid = width;
440 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
252b5132 441 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
252b5132
RH		 442 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
443}
444
445/* Cause an extra frag to be generated here, inserting up to 10 bytes
446 (that value is chosen in the frag_var call in md_assemble). TYPE
447 is the subtype of the frag to be generated; its primary type is
448 rs_machine_dependent.
449
450 The TYPE parameter is also used by md_convert_frag_1 and
451 md_estimate_size_before_relax. The appropriate type of fixup will
452 be emitted by md_convert_frag_1.
453
454 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
455static void
31302357 456add_frag (symbolS *add, offsetT off, int type)
252b5132 457{
8a104df9
KH		 458 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
459 the_ins.fragb[the_ins.nfrag].fadd = add;
460 the_ins.fragb[the_ins.nfrag].foff = off;
461 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 462}
463
464#define isvar(ex) \
465 (op (ex) != O_constant && op (ex) != O_big)
466
31302357
AS		 467static char *crack_operand (char *str, struct m68k_op *opP);
468static int get_num (struct m68k_exp *exp, int ok);
469static int reverse_16_bits (int in);
470static int reverse_8_bits (int in);
471static void install_gen_operand (int mode, int val);
472static void install_operand (int mode, int val);
473static void s_bss (int);
474static void s_data1 (int);
475static void s_data2 (int);
476static void s_even (int);
477static void s_proc (int);
478static void s_chip (int);
479static void s_fopt (int);
480static void s_opt (int);
481static void s_reg (int);
482static void s_restore (int);
483static void s_save (int);
484static void s_mri_if (int);
485static void s_mri_else (int);
486static void s_mri_endi (int);
487static void s_mri_break (int);
488static void s_mri_next (int);
489static void s_mri_for (int);
490static void s_mri_endf (int);
491static void s_mri_repeat (int);
492static void s_mri_until (int);
493static void s_mri_while (int);
494static void s_mri_endw (int);
266abb8f
NS		 495static void s_m68k_cpu (int);
496static void s_m68k_arch (int);
497
498struct m68k_cpu
499{
500 unsigned long arch; /* Architecture features. */
2da12c60 501 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 502 const char *name; /* Name */
2b0f3761 503 int alias; /* Alias for a canonical name. If 1, then
0b2e31dc
NS		 504 succeeds canonical name, if -1 then
505 succeeds canonical name, if <-1 ||>1 this is a
506 deprecated name, and the next/previous name
507 should be used. */
266abb8f 508};
252b5132 509
266abb8f
NS		 510/* We hold flags for features explicitly enabled and explicitly
511 disabled. */
252b5132 512static int current_architecture;
266abb8f 513static int not_current_architecture;
266abb8f
NS		 514static const struct m68k_cpu *selected_arch;
515static const struct m68k_cpu *selected_cpu;
516static int initialized;
252b5132 517
266abb8f
NS		 518/* Architecture models. */
519static const struct m68k_cpu m68k_archs[] =
520{
2da12c60
NS		 521 {m68000, m68000_ctrl, "68000", 0},
522 {m68010, m68010_ctrl, "68010", 0},
523 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
524 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
525 {m68040, m68040_ctrl, "68040", 0},
526 {m68060, m68060_ctrl, "68060", 0},
527 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 528 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 529 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
530 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
531 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 532 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 533 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
534 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 535 {0,0,NULL, 0}
536};
252b5132 537
87298967
NS		 538/* For -mno-mac we want to turn off all types of mac. */
539static const unsigned no_mac = mcfmac | mcfemac;
540
0b2e31dc
NS		 541/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
542 for either. */
266abb8f
NS		 543static const struct m68k_cpu m68k_extensions[] =
544{
2da12c60
NS		 545 {m68851, NULL, "68851", -1},
546 {m68881, NULL, "68881", -1},
547 {m68881, NULL, "68882", -1},
cf869cce 548
2da12c60 549 {cfloat|m68881, NULL, "float", 0},
cf869cce 550
2da12c60
NS		 551 {mcfhwdiv, NULL, "div", 1},
552 {mcfusp, NULL, "usp", 1},
87298967 553 {mcfmac, (void *)&no_mac, "mac", 1},
2da12c60 554 {mcfemac, NULL, "emac", 1},
cf869cce 555
2da12c60 556 {0,NULL,NULL, 0}
266abb8f
NS		 557};
558
559/* Processor list */
560static const struct m68k_cpu m68k_cpus[] =
561{
2da12c60
NS		 562 {m68000, m68000_ctrl, "68000", 0},
563 {m68000, m68000_ctrl, "68ec000", 1},
564 {m68000, m68000_ctrl, "68hc000", 1},
565 {m68000, m68000_ctrl, "68hc001", 1},
566 {m68000, m68000_ctrl, "68008", 1},
567 {m68000, m68000_ctrl, "68302", 1},
568 {m68000, m68000_ctrl, "68306", 1},
569 {m68000, m68000_ctrl, "68307", 1},
570 {m68000, m68000_ctrl, "68322", 1},
571 {m68000, m68000_ctrl, "68356", 1},
572 {m68010, m68010_ctrl, "68010", 0},
573 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
574 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
575 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
576 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
577 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
578 {m68040, m68040_ctrl, "68040", 0},
579 {m68040, m68040_ctrl, "68ec040", 1},
580 {m68060, m68060_ctrl, "68060", 0},
581 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 582
2da12c60
NS		 583 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
584 {cpu32|m68881, cpu32_ctrl, "68330", 1},
585 {cpu32|m68881, cpu32_ctrl, "68331", 1},
586 {cpu32|m68881, cpu32_ctrl, "68332", 1},
587 {cpu32|m68881, cpu32_ctrl, "68333", 1},
588 {cpu32|m68881, cpu32_ctrl, "68334", 1},
589 {cpu32|m68881, cpu32_ctrl, "68336", 1},
590 {cpu32|m68881, cpu32_ctrl, "68340", 1},
591 {cpu32|m68881, cpu32_ctrl, "68341", 1},
592 {cpu32|m68881, cpu32_ctrl, "68349", 1},
593 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2 594
87298967
NS		 595 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
596 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
c1c30076 597 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ag", 1},
87298967
NS		 598 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
599 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
c1c30076
NS		 600 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51je", 1},
601 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jf", 1},
602 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51jg", 1},
87298967 603 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
c1c30076 604 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51mm", 1},
87298967 605 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
c1c30076 606 {mcfisa_a|mcfisa_c|mcfusp|mcfemac, mcf51_ctrl, "51qm", 1},
cf869cce 607
2da12c60
NS		 608 {mcfisa_a, mcf_ctrl, "5200", 0},
609 {mcfisa_a, mcf_ctrl, "5202", 1},
610 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 611 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 612
78336706 613 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 614
2da12c60
NS		 615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 617
96e0bbcc
NS		 618 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 620
2da12c60
NS		 621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 624
2da12c60
NS		 625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
628
46203761
MK		 629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
630
d5be9593
NS		 631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
633
96e0bbcc
NS		 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 638
96e0bbcc
NS		 639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 641
87298967
NS		 642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
3739860c 644
2da12c60
NS		 645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
3739860c 650
2da12c60
NS		 651 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
652 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 653 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
87298967
NS		 654
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
3739860c 661
2da12c60
NS		 662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
3739860c 664
2da12c60 665 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
3739860c 666
2da12c60
NS		 667 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
3739860c 669
2da12c60
NS		 670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
3739860c 674
87298967
NS		 675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
3739860c 682
78336706 683 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
3739860c 684
2da12c60
NS		 685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
3739860c 689
2da12c60
NS		 690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
3739860c 693
def8fc92 694 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a 695
0d999f33
MK		 696 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54410", -1},
697 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54415", -1},
698 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54416", -1},
699 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54417", -1},
700 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54418_ctrl, "54418", 0},
701
9a2e615a
NS		 702 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
703 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
704 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
705 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
706 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
707 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
3739860c 708
a8e24a56
NS		 709 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
710 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
711 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
712 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
713 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
714 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
715 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
3739860c 716
a8e24a56
NS		 717 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
718 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
719 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
720 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
721 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
722 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
723 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
3739860c 724
b3768379 725 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 726 {fido_a, fido_ctrl, "fido", 1},
9840d27e 727
2da12c60 728 {0,NULL,NULL, 0}
dc84e067 729 };
252b5132 730
266abb8f
NS		 731static const struct m68k_cpu *m68k_lookup_cpu
732(const char *, const struct m68k_cpu *, int, int *);
733static int m68k_set_arch (const char *, int, int);
734static int m68k_set_cpu (const char *, int, int);
735static int m68k_set_extension (const char *, int, int);
736static void m68k_init_arch (void);
252b5132 737
151337e8
NC		 738/* This is the assembler relaxation table for m68k. m68k is a rich CISC
739 architecture and we have a lot of relaxation modes. */
252b5132 740
151337e8
NC		 741/* Macros used in the relaxation code. */
742#define TAB(x,y) (((x) << 2) + (y))
743#define TABTYPE(x) ((x) >> 2)
744
745/* Relaxation states. */
746#define BYTE 0
747#define SHORT 1
748#define LONG 2
749#define SZ_UNDEF 3
750
751/* Here are all the relaxation modes we support. First we can relax ordinary
752 branches. On 68020 and higher and on CPU32 all branch instructions take
753 three forms, so on these CPUs all branches always remain as such. When we
754 have to expand to the LONG form on a 68000, though, we substitute an
755 absolute jump instead. This is a direct replacement for unconditional
756 branches and a branch over a jump for conditional branches. However, if the
757 user requires PIC and disables this with --pcrel, we can only relax between
758 BYTE and SHORT forms, punting if that isn't enough. This gives us four
759 different relaxation modes for branches: */
760
36759679
NC		 761#define BRANCHBWL 0 /* Branch byte, word, or long. */
762#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
763#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
764#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 765
766/* We also relax coprocessor branches and DBcc's. All CPUs that support
767 coprocessor branches support them in word and long forms, so we have only
768 one relaxation mode for them. DBcc's are word only on all CPUs. We can
769 relax them to the LONG form with a branch-around sequence. This sequence
770 can use a long branch (if available) or an absolute jump (if acceptable).
771 This gives us two relaxation modes. If long branches are not available and
772 absolute jumps are not acceptable, we don't relax DBcc's. */
773
36759679
NC		 774#define FBRANCH 4 /* Coprocessor branch. */
775#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
776#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 777
778/* That's all for instruction relaxation. However, we also relax PC-relative
779 operands. Specifically, we have three operand relaxation modes. On the
780 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
781 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
782 two. Also PC+displacement+index operands in their simple form (with a non-
783 suppressed index without memory indirection) are supported on all CPUs, but
784 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
785 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
786 form of the PC+displacement+index operand. Finally, some absolute operands
787 can be relaxed down to 16-bit PC-relative. */
788
36759679
NC		 789#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
790#define PCINDEX 8 /* PC + displacement + index. */
791#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 792
cac27205
NC		 793/* This relaxation is required for branches where there is no long
794 branch and we are in pcrel mode. We generate a bne/beq pair. */
795#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
796 */
797
252b5132 798/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 799 needed; this is currently 12 bytes for bne/beq pair. */
800#define FRAG_VAR_SIZE 12
252b5132
RH		 801
802/* The fields are:
803 How far Forward this mode will reach:
804 How far Backward this mode will reach:
805 How many bytes this mode will add to the size of the frag
806 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 807
808 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 809relax_typeS md_relax_table[] =
810{
ac62c346
AM		 811 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
812 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
813 { 0, 0, 4, 0 },
814 { 1, 1, 0, 0 },
815
816 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
817 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
818 { 0, 0, 4, 0 },
819 { 1, 1, 0, 0 },
820
821 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
822 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
823 { 0, 0, 6, 0 },
824 { 1, 1, 0, 0 },
825
826 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
827 { 0, 0, 2, 0 },
828 { 1, 1, 0, 0 },
829 { 1, 1, 0, 0 },
830
36759679 831 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 832 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
833 { 0, 0, 4, 0 },
834 { 1, 1, 0, 0 },
835
36759679 836 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 837 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
838 { 0, 0, 10, 0 },
839 { 1, 1, 0, 0 },
840
36759679 841 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 842 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
843 { 0, 0, 10, 0 },
844 { 1, 1, 0, 0 },
845
36759679 846 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 847 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
848 { 0, 0, 6, 0 },
849 { 1, 1, 0, 0 },
850
851 { 125, -130, 0, TAB (PCINDEX, SHORT) },
852 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
853 { 0, 0, 4, 0 },
854 { 1, 1, 0, 0 },
855
36759679 856 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 857 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
858 { 0, 0, 4, 0 },
859 { 1, 1, 0, 0 },
3739860c 860
cac27205
NC		 861 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
862 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
863 { 0, 0, 10, 0 },
864 { 1, 1, 0, 0 },
252b5132
RH		 865};
866
867/* These are the machine dependent pseudo-ops. These are included so
868 the assembler can work on the output from the SUN C compiler, which
36759679 869 generates these. */
252b5132
RH		 870
871/* This table describes all the machine specific pseudo-ops the assembler
872 has to support. The fields are:
873 pseudo-op name without dot
874 function to call to execute this pseudo-op
36759679 875 Integer arg to pass to the function. */
252b5132
RH		 876const pseudo_typeS md_pseudo_table[] =
877{
878 {"data1", s_data1, 0},
879 {"data2", s_data2, 0},
880 {"bss", s_bss, 0},
881 {"even", s_even, 0},
882 {"skip", s_space, 0},
883 {"proc", s_proc, 0},
252b5132 884 {"align", s_align_bytes, 0},
252b5132 885 {"swbeg", s_ignore, 0},
cf869cce 886 {"long", m68k_elf_cons, 4},
252b5132
RH		 887 {"extend", float_cons, 'x'},
888 {"ldouble", float_cons, 'x'},
889
266abb8f
NS		 890 {"arch", s_m68k_arch, 0},
891 {"cpu", s_m68k_cpu, 0},
892
252b5132
RH		 893 /* The following pseudo-ops are supported for MRI compatibility. */
894 {"chip", s_chip, 0},
895 {"comline", s_space, 1},
896 {"fopt", s_fopt, 0},
897 {"mask2", s_ignore, 0},
898 {"opt", s_opt, 0},
899 {"reg", s_reg, 0},
900 {"restore", s_restore, 0},
901 {"save", s_save, 0},
902
903 {"if", s_mri_if, 0},
904 {"if.b", s_mri_if, 'b'},
905 {"if.w", s_mri_if, 'w'},
906 {"if.l", s_mri_if, 'l'},
907 {"else", s_mri_else, 0},
908 {"else.s", s_mri_else, 's'},
909 {"else.l", s_mri_else, 'l'},
910 {"endi", s_mri_endi, 0},
911 {"break", s_mri_break, 0},
912 {"break.s", s_mri_break, 's'},
913 {"break.l", s_mri_break, 'l'},
914 {"next", s_mri_next, 0},
915 {"next.s", s_mri_next, 's'},
916 {"next.l", s_mri_next, 'l'},
917 {"for", s_mri_for, 0},
918 {"for.b", s_mri_for, 'b'},
919 {"for.w", s_mri_for, 'w'},
920 {"for.l", s_mri_for, 'l'},
921 {"endf", s_mri_endf, 0},
922 {"repeat", s_mri_repeat, 0},
923 {"until", s_mri_until, 0},
924 {"until.b", s_mri_until, 'b'},
925 {"until.w", s_mri_until, 'w'},
926 {"until.l", s_mri_until, 'l'},
927 {"while", s_mri_while, 0},
928 {"while.b", s_mri_while, 'b'},
929 {"while.w", s_mri_while, 'w'},
930 {"while.l", s_mri_while, 'l'},
931 {"endw", s_mri_endw, 0},
932
933 {0, 0, 0}
934};
935
252b5132 936/* The mote pseudo ops are put into the opcode table, since they
31302357 937 don't start with a . they look like opcodes to gas. */
252b5132 938
5a38dc70 939const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 940{
941
942 {"dcl", cons, 4},
943 {"dc", cons, 2},
944 {"dcw", cons, 2},
945 {"dcb", cons, 1},
946
947 {"dsl", s_space, 4},
948 {"ds", s_space, 2},
949 {"dsw", s_space, 2},
950 {"dsb", s_space, 1},
951
952 {"xdef", s_globl, 0},
252b5132 953 {"align", s_align_bytes, 0},
252b5132
RH		 954 {0, 0, 0}
955};
956
bd17c2c3
AM		 957/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
958 gives identical results to a 32-bit host. */
959#define TRUNC(X) ((valueT) (X) & 0xffffffff)
960#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
961
962#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
963#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
964#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
965#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
966
967#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
968#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 969#define islong(x) (1)
970
252b5132
RH		 971static char notend_table[256];
972static char alt_notend_table[256];
973#define notend(s) \
974 (! (notend_table[(unsigned char) *s] \
975 || (*s == ':' \
976 && alt_notend_table[(unsigned char) s[1]])))
977
252b5132 978
c801568a
AM		 979/* Return zero if the reference to SYMBOL from within the same segment may
980 be relaxed. */
981
982/* On an ELF system, we can't relax an externally visible symbol,
983 because it may be overridden by a shared library. However, if
984 TARGET_OS is "elf", then we presume that we are assembling for an
985 embedded system, in which case we don't have to worry about shared
986 libraries, and we can relax any external sym. */
987
988#define relaxable_symbol(symbol) \
6358301e 989 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 990 || S_IS_WEAK (symbol)))
991
252b5132
RH		 992/* Compute the relocation code for a fixup of SIZE bytes, using pc
993 relative relocation if PCREL is non-zero. PIC says whether a special
994 pic relocation was requested. */
995
252b5132 996static bfd_reloc_code_real_type
31302357 997get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 998{
999 switch (pic)
1000 {
1001 case pic_got_pcrel:
1002 switch (size)
1003 {
1004 case 1:
1005 return BFD_RELOC_8_GOT_PCREL;
1006 case 2:
1007 return BFD_RELOC_16_GOT_PCREL;
1008 case 4:
1009 return BFD_RELOC_32_GOT_PCREL;
1010 }
1011 break;
1012
1013 case pic_got_off:
1014 switch (size)
1015 {
1016 case 1:
1017 return BFD_RELOC_8_GOTOFF;
1018 case 2:
1019 return BFD_RELOC_16_GOTOFF;
1020 case 4:
1021 return BFD_RELOC_32_GOTOFF;
1022 }
1023 break;
1024
1025 case pic_plt_pcrel:
1026 switch (size)
1027 {
1028 case 1:
1029 return BFD_RELOC_8_PLT_PCREL;
1030 case 2:
1031 return BFD_RELOC_16_PLT_PCREL;
1032 case 4:
1033 return BFD_RELOC_32_PLT_PCREL;
1034 }
1035 break;
1036
1037 case pic_plt_off:
1038 switch (size)
1039 {
1040 case 1:
1041 return BFD_RELOC_8_PLTOFF;
1042 case 2:
1043 return BFD_RELOC_16_PLTOFF;
1044 case 4:
1045 return BFD_RELOC_32_PLTOFF;
1046 }
1047 break;
1048
cf869cce
NC		 1049 case pic_tls_gd:
1050 switch (size)
1051 {
1052 case 1:
1053 return BFD_RELOC_68K_TLS_GD8;
1054 case 2:
1055 return BFD_RELOC_68K_TLS_GD16;
1056 case 4:
1057 return BFD_RELOC_68K_TLS_GD32;
1058 }
1059 break;
1060
1061 case pic_tls_ldm:
1062 switch (size)
1063 {
1064 case 1:
1065 return BFD_RELOC_68K_TLS_LDM8;
1066 case 2:
1067 return BFD_RELOC_68K_TLS_LDM16;
1068 case 4:
1069 return BFD_RELOC_68K_TLS_LDM32;
1070 }
1071 break;
1072
1073 case pic_tls_ldo:
1074 switch (size)
1075 {
1076 case 1:
1077 return BFD_RELOC_68K_TLS_LDO8;
1078 case 2:
1079 return BFD_RELOC_68K_TLS_LDO16;
1080 case 4:
1081 return BFD_RELOC_68K_TLS_LDO32;
1082 }
1083 break;
1084
1085 case pic_tls_ie:
1086 switch (size)
1087 {
1088 case 1:
1089 return BFD_RELOC_68K_TLS_IE8;
1090 case 2:
1091 return BFD_RELOC_68K_TLS_IE16;
1092 case 4:
1093 return BFD_RELOC_68K_TLS_IE32;
1094 }
1095 break;
1096
1097 case pic_tls_le:
1098 switch (size)
1099 {
1100 case 1:
1101 return BFD_RELOC_68K_TLS_LE8;
1102 case 2:
1103 return BFD_RELOC_68K_TLS_LE16;
1104 case 4:
1105 return BFD_RELOC_68K_TLS_LE32;
1106 }
1107 break;
1108
252b5132
RH		 1109 case pic_none:
1110 if (pcrel)
1111 {
1112 switch (size)
1113 {
1114 case 1:
1115 return BFD_RELOC_8_PCREL;
1116 case 2:
1117 return BFD_RELOC_16_PCREL;
1118 case 4:
1119 return BFD_RELOC_32_PCREL;
1120 }
1121 }
1122 else
1123 {
1124 switch (size)
1125 {
1126 case 1:
1127 return BFD_RELOC_8;
1128 case 2:
1129 return BFD_RELOC_16;
1130 case 4:
1131 return BFD_RELOC_32;
1132 }
1133 }
1134 }
1135
1136 if (pcrel)
1137 {
1138 if (pic == pic_none)
1139 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1140 else
1141 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1142 }
1143 else
1144 {
1145 if (pic == pic_none)
1146 as_bad (_("Can not do %d byte relocation"), size);
1147 else
1148 as_bad (_("Can not do %d byte pic relocation"), size);
1149 }
1150
1151 return BFD_RELOC_NONE;
1152}
1153
1154/* Here we decide which fixups can be adjusted to make them relative
1155 to the beginning of the section instead of the symbol. Basically
1156 we need to make sure that the dynamic relocations are done
1157 correctly, so in some cases we force the original symbol to be
1158 used. */
1159int
31302357 1160tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1161{
36759679 1162 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1163 switch (fixP->fx_r_type)
1164 {
1165 case BFD_RELOC_8_GOT_PCREL:
1166 case BFD_RELOC_16_GOT_PCREL:
1167 case BFD_RELOC_32_GOT_PCREL:
1168 case BFD_RELOC_8_GOTOFF:
1169 case BFD_RELOC_16_GOTOFF:
1170 case BFD_RELOC_32_GOTOFF:
1171 case BFD_RELOC_8_PLT_PCREL:
1172 case BFD_RELOC_16_PLT_PCREL:
1173 case BFD_RELOC_32_PLT_PCREL:
1174 case BFD_RELOC_8_PLTOFF:
1175 case BFD_RELOC_16_PLTOFF:
1176 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1177 case BFD_RELOC_68K_TLS_GD32:
1178 case BFD_RELOC_68K_TLS_GD16:
1179 case BFD_RELOC_68K_TLS_GD8:
1180 case BFD_RELOC_68K_TLS_LDM32:
1181 case BFD_RELOC_68K_TLS_LDM16:
1182 case BFD_RELOC_68K_TLS_LDM8:
1183 case BFD_RELOC_68K_TLS_LDO32:
1184 case BFD_RELOC_68K_TLS_LDO16:
1185 case BFD_RELOC_68K_TLS_LDO8:
1186 case BFD_RELOC_68K_TLS_IE32:
1187 case BFD_RELOC_68K_TLS_IE16:
1188 case BFD_RELOC_68K_TLS_IE8:
1189 case BFD_RELOC_68K_TLS_LE32:
1190 case BFD_RELOC_68K_TLS_LE16:
1191 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1192 return 0;
1193
1194 case BFD_RELOC_VTABLE_INHERIT:
1195 case BFD_RELOC_VTABLE_ENTRY:
1196 return 0;
1197
1198 default:
1199 return 1;
1200 }
1201}
1202
252b5132 1203arelent *
31302357 1204tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1205{
1206 arelent *reloc;
1207 bfd_reloc_code_real_type code;
1208
8ec6253e
NC		 1209 /* If the tcbit is set, then this was a fixup of a negative value
1210 that was never resolved. We do not have a reloc to handle this,
1211 so just return. We assume that other code will have detected this
1212 situation and produced a helpful error message, so we just tell the
1213 user that the reloc cannot be produced. */
252b5132 1214 if (fixp->fx_tcbit)
8ec6253e
NC		 1215 {
1216 if (fixp->fx_addsy)
b091f402
AM		 1217 as_bad_where (fixp->fx_file, fixp->fx_line,
1218 _("Unable to produce reloc against symbol '%s'"),
1219 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1220 return NULL;
1221 }
252b5132
RH		 1222
1223 if (fixp->fx_r_type != BFD_RELOC_NONE)
1224 {
1225 code = fixp->fx_r_type;
1226
1227 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1228 that fixup_segment converted a non-PC relative reloc into a
1229 PC relative reloc. In such a case, we need to convert the
1230 reloc code. */
1231 if (fixp->fx_pcrel)
1232 {
1233 switch (code)
1234 {
1235 case BFD_RELOC_8:
1236 code = BFD_RELOC_8_PCREL;
1237 break;
1238 case BFD_RELOC_16:
1239 code = BFD_RELOC_16_PCREL;
1240 break;
1241 case BFD_RELOC_32:
1242 code = BFD_RELOC_32_PCREL;
1243 break;
1244 case BFD_RELOC_8_PCREL:
1245 case BFD_RELOC_16_PCREL:
1246 case BFD_RELOC_32_PCREL:
1247 case BFD_RELOC_8_GOT_PCREL:
1248 case BFD_RELOC_16_GOT_PCREL:
1249 case BFD_RELOC_32_GOT_PCREL:
1250 case BFD_RELOC_8_GOTOFF:
1251 case BFD_RELOC_16_GOTOFF:
1252 case BFD_RELOC_32_GOTOFF:
1253 case BFD_RELOC_8_PLT_PCREL:
1254 case BFD_RELOC_16_PLT_PCREL:
1255 case BFD_RELOC_32_PLT_PCREL:
1256 case BFD_RELOC_8_PLTOFF:
1257 case BFD_RELOC_16_PLTOFF:
1258 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1259 case BFD_RELOC_68K_TLS_GD32:
1260 case BFD_RELOC_68K_TLS_GD16:
1261 case BFD_RELOC_68K_TLS_GD8:
1262 case BFD_RELOC_68K_TLS_LDM32:
1263 case BFD_RELOC_68K_TLS_LDM16:
1264 case BFD_RELOC_68K_TLS_LDM8:
1265 case BFD_RELOC_68K_TLS_LDO32:
1266 case BFD_RELOC_68K_TLS_LDO16:
1267 case BFD_RELOC_68K_TLS_LDO8:
1268 case BFD_RELOC_68K_TLS_IE32:
1269 case BFD_RELOC_68K_TLS_IE16:
1270 case BFD_RELOC_68K_TLS_IE8:
1271 case BFD_RELOC_68K_TLS_LE32:
1272 case BFD_RELOC_68K_TLS_LE16:
1273 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1274 break;
1275 default:
1276 as_bad_where (fixp->fx_file, fixp->fx_line,
1277 _("Cannot make %s relocation PC relative"),
1278 bfd_get_reloc_code_name (code));
1279 }
1280 }
1281 }
1282 else
1283 {
1284#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1285 switch (F (fixp->fx_size, fixp->fx_pcrel))
1286 {
1287#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1288 MAP (1, 0, BFD_RELOC_8);
1289 MAP (2, 0, BFD_RELOC_16);
1290 MAP (4, 0, BFD_RELOC_32);
1291 MAP (1, 1, BFD_RELOC_8_PCREL);
1292 MAP (2, 1, BFD_RELOC_16_PCREL);
1293 MAP (4, 1, BFD_RELOC_32_PCREL);
1294 default:
1295 abort ();
1296 }
1297 }
1298#undef F
1299#undef MAP
1300
add39d23
TS		 1301 reloc = XNEW (arelent);
1302 reloc->sym_ptr_ptr = XNEW (asymbol *);
49309057 1303 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132 1304 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
252b5132
RH		 1305 if (!fixp->fx_pcrel)
1306 reloc->addend = fixp->fx_addnumber;
1307 else
1308 reloc->addend = (section->vma
552c607f 1309 + fixp->fx_pcrel_adjust
252b5132
RH		 1310 + fixp->fx_addnumber
1311 + md_pcrel_from (fixp));
252b5132
RH		 1312
1313 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9c2799c2 1314 gas_assert (reloc->howto != 0);
252b5132
RH		 1315
1316 return reloc;
1317}
1318
252b5132
RH		 1319/* Handle of the OPCODE hash table. NULL means any use before
1320 m68k_ip_begin() will crash. */
1321static struct hash_control *op_hash;
1322\f
1323/* Assemble an m68k instruction. */
1324
1325static void
31302357 1326m68k_ip (char *instring)
252b5132 1327{
ed9e98c2
AM		 1328 char *p;
1329 struct m68k_op *opP;
1330 const struct m68k_incant *opcode;
1331 const char *s;
1332 int tmpreg = 0, baseo = 0, outro = 0, nextword;
252b5132
RH		 1333 char *pdot, *pdotmove;
1334 enum m68k_size siz1, siz2;
1335 char c;
1336 int losing;
1337 int opsfound;
03b13e59 1338 struct m68k_op operands_backup[6];
252b5132
RH		 1339 LITTLENUM_TYPE words[6];
1340 LITTLENUM_TYPE *wordp;
1341 unsigned long ok_arch = 0;
1342
1343 if (*instring == ' ')
36759679 1344 instring++; /* Skip leading whitespace. */
252b5132
RH		 1345
1346 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1347 or exactly 1 space. */
252b5132
RH		 1348 pdot = 0;
1349 for (p = instring; *p != '\0'; p++)
1350 {
1351 if (*p == ' ')
1352 break;
1353 if (*p == '.')
1354 pdot = p;
1355 }
1356
1357 if (p == instring)
1358 {
1359 the_ins.error = _("No operator");
1360 return;
1361 }
1362
1363 /* p now points to the end of the opcode name, probably whitespace.
1364 Make sure the name is null terminated by clobbering the
1365 whitespace, look it up in the hash table, then fix it back.
1366 Remove a dot, first, since the opcode tables have none. */
1367 if (pdot != NULL)
1368 {
1369 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1370 *pdotmove = pdotmove[1];
1371 p--;
1372 }
1373
1374 c = *p;
1375 *p = '\0';
1376 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1377 *p = c;
1378
1379 if (pdot != NULL)
1380 {
1381 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1382 *pdotmove = pdotmove[-1];
1383 *pdot = '.';
1384 ++p;
1385 }
1386
1387 if (opcode == NULL)
1388 {
1389 the_ins.error = _("Unknown operator");
1390 return;
1391 }
1392
36759679 1393 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1394 while (*p == ' ')
1395 ++p;
1396
1397 if (opcode->m_operands == 0)
1398 {
1399 char *old = input_line_pointer;
1400 *old = '\n';
1401 input_line_pointer = p;
2b0f3761 1402 /* Ahh - it's a motorola style pseudo op. */
252b5132
RH		 1403 mote_pseudo_table[opcode->m_opnum].poc_handler
1404 (mote_pseudo_table[opcode->m_opnum].poc_val);
1405 input_line_pointer = old;
1406 *old = 0;
1407
1408 return;
1409 }
1410
1411 if (flag_mri && opcode->m_opnum == 0)
1412 {
1413 /* In MRI mode, random garbage is allowed after an instruction
1414 which accepts no operands. */
1415 the_ins.args = opcode->m_operands;
1416 the_ins.numargs = opcode->m_opnum;
1417 the_ins.numo = opcode->m_codenum;
1418 the_ins.opcode[0] = getone (opcode);
1419 the_ins.opcode[1] = gettwo (opcode);
1420 return;
1421 }
1422
1423 for (opP = &the_ins.operands[0]; *p; opP++)
1424 {
1425 p = crack_operand (p, opP);
1426
1427 if (opP->error)
1428 {
1429 the_ins.error = opP->error;
1430 return;
1431 }
1432 }
1433
1434 opsfound = opP - &the_ins.operands[0];
1435
1436 /* This ugly hack is to support the floating pt opcodes in their
33eaf5de 1437 standard form. Essentially, we fake a first entry of type COP#1 */
252b5132
RH		 1438 if (opcode->m_operands[0] == 'I')
1439 {
1440 int n;
1441
1442 for (n = opsfound; n > 0; --n)
1443 the_ins.operands[n] = the_ins.operands[n - 1];
1444
31302357 1445 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1446 the_ins.operands[0].mode = CONTROL;
1447 the_ins.operands[0].reg = m68k_float_copnum;
1448 opsfound++;
1449 }
1450
36759679 1451 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1452 for (losing = 0;;)
1453 {
1454 /* If we didn't get the right number of ops, or we have no
92774660 1455 common model with this pattern then reject this pattern. */
252b5132
RH		 1456
1457 ok_arch |= opcode->m_arch;
1458 if (opsfound != opcode->m_opnum
1459 || ((opcode->m_arch & current_architecture) == 0))
1460 ++losing;
1461 else
1462 {
03b13e59
NC		 1463 int i;
1464
1465 /* Make a copy of the operands of this insn so that
1466 we can modify them safely, should we want to. */
9c2799c2 1467 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
03b13e59
NC		 1468 for (i = 0; i < opsfound; i++)
1469 operands_backup[i] = the_ins.operands[i];
1470
1471 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1472 *s && !losing;
1473 s += 2, opP++)
1474 {
1475 /* Warning: this switch is huge! */
1476 /* I've tried to organize the cases into this order:
1477 non-alpha first, then alpha by letter. Lower-case
1478 goes directly before uppercase counterpart. */
1479 /* Code with multiple case ...: gets sorted by the lowest
1480 case ... it belongs to. I hope this makes sense. */
1481 switch (*s)
1482 {
1483 case '!':
1484 switch (opP->mode)
1485 {
1486 case IMMED:
1487 case DREG:
1488 case AREG:
1489 case FPREG:
1490 case CONTROL:
1491 case AINC:
1492 case ADEC:
1493 case REGLST:
1494 losing++;
1495 break;
1496 default:
1497 break;
1498 }
1499 break;
1500
1501 case '<':
1502 switch (opP->mode)
1503 {
1504 case DREG:
1505 case AREG:
1506 case FPREG:
1507 case CONTROL:
1508 case IMMED:
1509 case ADEC:
1510 case REGLST:
1511 losing++;
1512 break;
1513 default:
1514 break;
1515 }
1516 break;
1517
1518 case '>':
1519 switch (opP->mode)
1520 {
1521 case DREG:
1522 case AREG:
1523 case FPREG:
1524 case CONTROL:
1525 case IMMED:
1526 case AINC:
1527 case REGLST:
1528 losing++;
1529 break;
1530 case ABSL:
1531 break;
1532 default:
1533 if (opP->reg == PC
1534 || opP->reg == ZPC)
1535 losing++;
1536 break;
1537 }
1538 break;
1539
1540 case 'm':
1541 switch (opP->mode)
1542 {
1543 case DREG:
1544 case AREG:
1545 case AINDR:
1546 case AINC:
1547 case ADEC:
1548 break;
1549 default:
1550 losing++;
1551 }
8a104df9 1552 break;
252b5132
RH		 1553
1554 case 'n':
1555 switch (opP->mode)
1556 {
1557 case DISP:
1558 break;
1559 default:
1560 losing++;
1561 }
8a104df9 1562 break;
252b5132
RH		 1563
1564 case 'o':
1565 switch (opP->mode)
1566 {
1567 case BASE:
1568 case ABSL:
1569 case IMMED:
1570 break;
1571 default:
1572 losing++;
1573 }
8a104df9 1574 break;
252b5132
RH		 1575
1576 case 'p':
1577 switch (opP->mode)
1578 {
1579 case DREG:
1580 case AREG:
1581 case AINDR:
1582 case AINC:
1583 case ADEC:
1584 break;
1585 case DISP:
1586 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1587 losing++;
252b5132
RH		 1588 break;
1589 default:
1590 losing++;
1591 }
8a104df9 1592 break;
252b5132
RH		 1593
1594 case 'q':
1595 switch (opP->mode)
1596 {
1597 case DREG:
1598 case AINDR:
1599 case AINC:
1600 case ADEC:
1601 break;
1602 case DISP:
1603 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1604 losing++;
252b5132
RH		 1605 break;
1606 default:
1607 losing++;
1608 break;
1609 }
8a104df9 1610 break;
252b5132
RH		 1611
1612 case 'v':
1613 switch (opP->mode)
1614 {
1615 case DREG:
1616 case AINDR:
1617 case AINC:
1618 case ADEC:
1619 case ABSL:
1620 break;
1621 case DISP:
1622 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1623 losing++;
252b5132
RH		 1624 break;
1625 default:
1626 losing++;
1627 break;
1628 }
1629 break;
1630
1631 case '#':
1632 if (opP->mode != IMMED)
1633 losing++;
1634 else if (s[1] == 'b'
1635 && ! isvar (&opP->disp)
1636 && (opP->disp.exp.X_op != O_constant
1637 || ! isbyte (opP->disp.exp.X_add_number)))
1638 losing++;
1639 else if (s[1] == 'B'
1640 && ! isvar (&opP->disp)
1641 && (opP->disp.exp.X_op != O_constant
1642 || ! issbyte (opP->disp.exp.X_add_number)))
1643 losing++;
1644 else if (s[1] == 'w'
1645 && ! isvar (&opP->disp)
1646 && (opP->disp.exp.X_op != O_constant
1647 || ! isword (opP->disp.exp.X_add_number)))
1648 losing++;
1649 else if (s[1] == 'W'
1650 && ! isvar (&opP->disp)
1651 && (opP->disp.exp.X_op != O_constant
1652 || ! issword (opP->disp.exp.X_add_number)))
1653 losing++;
1654 break;
1655
1656 case '^':
1657 case 'T':
1658 if (opP->mode != IMMED)
1659 losing++;
1660 break;
1661
1662 case '$':
1663 if (opP->mode == AREG
1664 || opP->mode == CONTROL
1665 || opP->mode == FPREG
1666 || opP->mode == IMMED
1667 || opP->mode == REGLST
1668 || (opP->mode != ABSL
1669 && (opP->reg == PC
1670 || opP->reg == ZPC)))
1671 losing++;
1672 break;
1673
1674 case '%':
1675 if (opP->mode == CONTROL
1676 || opP->mode == FPREG
1677 || opP->mode == REGLST
1678 || opP->mode == IMMED
1679 || (opP->mode != ABSL
1680 && (opP->reg == PC
1681 || opP->reg == ZPC)))
1682 losing++;
1683 break;
1684
1685 case '&':
1686 switch (opP->mode)
1687 {
1688 case DREG:
1689 case AREG:
1690 case FPREG:
1691 case CONTROL:
1692 case IMMED:
1693 case AINC:
1694 case ADEC:
1695 case REGLST:
1696 losing++;
1697 break;
1698 case ABSL:
1699 break;
1700 default:
1701 if (opP->reg == PC
1702 || opP->reg == ZPC)
1703 losing++;
1704 break;
1705 }
1706 break;
1707
1708 case '*':
1709 if (opP->mode == CONTROL
1710 || opP->mode == FPREG
1711 || opP->mode == REGLST)
1712 losing++;
1713 break;
1714
1715 case '+':
1716 if (opP->mode != AINC)
1717 losing++;
1718 break;
1719
1720 case '-':
1721 if (opP->mode != ADEC)
1722 losing++;
1723 break;
1724
1725 case '/':
1726 switch (opP->mode)
1727 {
1728 case AREG:
1729 case CONTROL:
1730 case FPREG:
1731 case AINC:
1732 case ADEC:
1733 case IMMED:
1734 case REGLST:
1735 losing++;
1736 break;
1737 default:
1738 break;
1739 }
1740 break;
1741
1742 case ';':
1743 switch (opP->mode)
1744 {
1745 case AREG:
1746 case CONTROL:
1747 case FPREG:
1748 case REGLST:
1749 losing++;
1750 break;
1751 default:
1752 break;
1753 }
1754 break;
1755
1756 case '?':
1757 switch (opP->mode)
1758 {
1759 case AREG:
1760 case CONTROL:
1761 case FPREG:
1762 case AINC:
1763 case ADEC:
1764 case IMMED:
1765 case REGLST:
1766 losing++;
1767 break;
1768 case ABSL:
1769 break;
1770 default:
1771 if (opP->reg == PC || opP->reg == ZPC)
1772 losing++;
1773 break;
1774 }
1775 break;
1776
1777 case '@':
1778 switch (opP->mode)
1779 {
1780 case AREG:
1781 case CONTROL:
1782 case FPREG:
1783 case IMMED:
1784 case REGLST:
1785 losing++;
1786 break;
1787 default:
1788 break;
1789 }
1790 break;
1791
1792 case '~': /* For now! (JF FOO is this right?) */
1793 switch (opP->mode)
1794 {
1795 case DREG:
1796 case AREG:
1797 case CONTROL:
1798 case FPREG:
1799 case IMMED:
1800 case REGLST:
1801 losing++;
1802 break;
1803 case ABSL:
1804 break;
1805 default:
1806 if (opP->reg == PC
1807 || opP->reg == ZPC)
1808 losing++;
1809 break;
1810 }
1811 break;
1812
1813 case '3':
1814 if (opP->mode != CONTROL
1815 || (opP->reg != TT0 && opP->reg != TT1))
1816 losing++;
1817 break;
1818
1819 case 'A':
1820 if (opP->mode != AREG)
1821 losing++;
1822 break;
1823
1824 case 'a':
1825 if (opP->mode != AINDR)
1826 ++losing;
1827 break;
1828
fd99574b
NC		 1829 case '4':
1830 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1831 && (opP->mode != DISP
1832 || opP->reg < ADDR0
1833 || opP->reg > ADDR7))
1834 ++losing;
1835 break;
1836
252b5132
RH		 1837 case 'B': /* FOO */
1838 if (opP->mode != ABSL
1839 || (flag_long_jumps
1840 && strncmp (instring, "jbsr", 4) == 0))
1841 losing++;
1842 break;
1843
3e602632
NC		 1844 case 'b':
1845 switch (opP->mode)
1846 {
1847 case IMMED:
1848 case ABSL:
1849 case AREG:
1850 case FPREG:
1851 case CONTROL:
1852 case POST:
1853 case PRE:
1854 case REGLST:
1855 losing++;
1856 break;
1857 default:
1858 break;
1859 }
1860 break;
1861
252b5132
RH		 1862 case 'C':
1863 if (opP->mode != CONTROL || opP->reg != CCR)
1864 losing++;
1865 break;
1866
1867 case 'd':
1868 if (opP->mode != DISP
1869 || opP->reg < ADDR0
1870 || opP->reg > ADDR7)
1871 losing++;
1872 break;
1873
1874 case 'D':
1875 if (opP->mode != DREG)
1876 losing++;
1877 break;
1878
6da466c7
ILT		 1879 case 'E':
1880 if (opP->reg != ACC)
1881 losing++;
1882 break;
1883
fd99574b
NC		 1884 case 'e':
1885 if (opP->reg != ACC && opP->reg != ACC1
1886 && opP->reg != ACC2 && opP->reg != ACC3)
1887 losing++;
1888 break;
1889
252b5132
RH		 1890 case 'F':
1891 if (opP->mode != FPREG)
1892 losing++;
1893 break;
1894
6da466c7
ILT		 1895 case 'G':
1896 if (opP->reg != MACSR)
1897 losing++;
1898 break;
1899
fd99574b
NC		 1900 case 'g':
1901 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1902 losing++;
1903 break;
1904
6da466c7
ILT		 1905 case 'H':
1906 if (opP->reg != MASK)
1907 losing++;
1908 break;
1909
252b5132
RH		 1910 case 'I':
1911 if (opP->mode != CONTROL
1912 || opP->reg < COP0
1913 || opP->reg > COP7)
1914 losing++;
1915 break;
1916
fd99574b
NC		 1917 case 'i':
1918 if (opP->mode != LSH && opP->mode != RSH)
1919 losing++;
1920 break;
1921
252b5132
RH		 1922 case 'J':
1923 if (opP->mode != CONTROL
1924 || opP->reg < USP
0b2e31dc
NS		 1925 || opP->reg > last_movec_reg
1926 || !control_regs)
252b5132
RH		 1927 losing++;
1928 else
1929 {
1930 const enum m68k_register *rp;
3739860c 1931
252b5132 1932 for (rp = control_regs; *rp; rp++)
78336706
NS		 1933 {
1934 if (*rp == opP->reg)
1935 break;
1936 /* In most CPUs RAMBAR refers to control reg
1937 c05 (RAMBAR1), but a few CPUs have it
1938 refer to c04 (RAMBAR0). */
1939 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1940 {
1941 opP->reg = RAMBAR_ALT;
1942 break;
1943 }
1944 }
252b5132
RH		 1945 if (*rp == 0)
1946 losing++;
1947 }
1948 break;
1949
1950 case 'k':
1951 if (opP->mode != IMMED)
1952 losing++;
1953 break;
1954
1955 case 'l':
1956 case 'L':
1957 if (opP->mode == DREG
1958 || opP->mode == AREG
1959 || opP->mode == FPREG)
1960 {
1961 if (s[1] == '8')
1962 losing++;
1963 else
1964 {
1965 switch (opP->mode)
1966 {
1967 case DREG:
1968 opP->mask = 1 << (opP->reg - DATA0);
1969 break;
1970 case AREG:
1971 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1972 break;
1973 case FPREG:
1974 opP->mask = 1 << (opP->reg - FP0 + 16);
1975 break;
1976 default:
1977 abort ();
1978 }
1979 opP->mode = REGLST;
1980 }
1981 }
1982 else if (opP->mode == CONTROL)
1983 {
1984 if (s[1] != '8')
1985 losing++;
1986 else
1987 {
1988 switch (opP->reg)
1989 {
1990 case FPI:
1991 opP->mask = 1 << 24;
1992 break;
1993 case FPS:
1994 opP->mask = 1 << 25;
1995 break;
1996 case FPC:
1997 opP->mask = 1 << 26;
1998 break;
1999 default:
2000 losing++;
2001 break;
2002 }
2003 opP->mode = REGLST;
2004 }
2005 }
2006 else if (opP->mode != REGLST)
2007 losing++;
2008 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2009 losing++;
2010 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2011 losing++;
2012 break;
2013
2014 case 'M':
2015 if (opP->mode != IMMED)
2016 losing++;
2017 else if (opP->disp.exp.X_op != O_constant
2018 || ! issbyte (opP->disp.exp.X_add_number))
2019 losing++;
2020 else if (! m68k_quick
2021 && instring[3] != 'q'
2022 && instring[4] != 'q')
2023 losing++;
2024 break;
2025
2026 case 'O':
2027 if (opP->mode != DREG
2028 && opP->mode != IMMED
2029 && opP->mode != ABSL)
2030 losing++;
2031 break;
2032
2033 case 'Q':
2034 if (opP->mode != IMMED)
2035 losing++;
2036 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2037 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2038 losing++;
2039 else if (! m68k_quick
2040 && (strncmp (instring, "add", 3) == 0
2041 || strncmp (instring, "sub", 3) == 0)
2042 && instring[3] != 'q')
2043 losing++;
2044 break;
2045
2046 case 'R':
2047 if (opP->mode != DREG && opP->mode != AREG)
2048 losing++;
2049 break;
2050
2051 case 'r':
2052 if (opP->mode != AINDR
2053 && (opP->mode != BASE
2054 || (opP->reg != 0
2055 && opP->reg != ZADDR0)
2056 || opP->disp.exp.X_op != O_absent
2057 || ((opP->index.reg < DATA0
2058 || opP->index.reg > DATA7)
2059 && (opP->index.reg < ADDR0
2060 || opP->index.reg > ADDR7))
2061 || opP->index.size != SIZE_UNSPEC
2062 || opP->index.scale != 1))
2063 losing++;
2064 break;
2065
2066 case 's':
2067 if (opP->mode != CONTROL
2068 || ! (opP->reg == FPI
2069 || opP->reg == FPS
2070 || opP->reg == FPC))
2071 losing++;
2072 break;
2073
2074 case 'S':
2075 if (opP->mode != CONTROL || opP->reg != SR)
2076 losing++;
2077 break;
2078
2079 case 't':
2080 if (opP->mode != IMMED)
2081 losing++;
2082 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2083 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2084 losing++;
2085 break;
2086
2087 case 'U':
2088 if (opP->mode != CONTROL || opP->reg != USP)
2089 losing++;
2090 break;
2091
3e602632
NC		 2092 case 'x':
2093 if (opP->mode != IMMED)
2094 losing++;
2095 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2096 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2097 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2098 losing++;
2099 break;
2100
afa2158f
NS		 2101 case 'j':
2102 if (opP->mode != IMMED)
2103 losing++;
2104 else if (opP->disp.exp.X_op != O_constant
2105 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2106 losing++;
2107 break;
2108
2109 case 'K':
2110 if (opP->mode != IMMED)
2111 losing++;
2112 else if (opP->disp.exp.X_op != O_constant
2113 || TRUNC (opP->disp.exp.X_add_number) > 511)
2114 losing++;
2115 break;
2116
252b5132
RH		 2117 /* JF these are out of order. We could put them
2118 in order if we were willing to put up with
2119 bunches of #ifdef m68851s in the code.
2120
2121 Don't forget that you need these operands
2122 to use 68030 MMU instructions. */
2123#ifndef NO_68851
36759679 2124 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2125 case '|':
2126 if (opP->mode == CONTROL
2127 || opP->mode == FPREG
2128 || opP->mode == DREG
2129 || opP->mode == AREG
2130 || opP->mode == REGLST)
2131 losing++;
2132 /* We should accept immediate operands, but they
2133 supposedly have to be quad word, and we don't
2134 handle that. I would like to see what a Motorola
2135 assembler does before doing something here. */
2136 if (opP->mode == IMMED)
2137 losing++;
2138 break;
2139
2140 case 'f':
2141 if (opP->mode != CONTROL
2142 || (opP->reg != SFC && opP->reg != DFC))
2143 losing++;
2144 break;
2145
2146 case '0':
2147 if (opP->mode != CONTROL || opP->reg != TC)
2148 losing++;
2149 break;
2150
2151 case '1':
2152 if (opP->mode != CONTROL || opP->reg != AC)
2153 losing++;
2154 break;
2155
2156 case '2':
2157 if (opP->mode != CONTROL
2158 || (opP->reg != CAL
2159 && opP->reg != VAL
2160 && opP->reg != SCC))
2161 losing++;
2162 break;
2163
2164 case 'V':
2165 if (opP->mode != CONTROL
2166 || opP->reg != VAL)
2167 losing++;
2168 break;
2169
2170 case 'W':
2171 if (opP->mode != CONTROL
2172 || (opP->reg != DRP
2173 && opP->reg != SRP
2174 && opP->reg != CRP))
2175 losing++;
2176 break;
2177
3e602632
NC		 2178 case 'w':
2179 switch (opP->mode)
2180 {
2181 case IMMED:
2182 case ABSL:
2183 case AREG:
2184 case DREG:
2185 case FPREG:
2186 case CONTROL:
2187 case POST:
2188 case PRE:
2189 case REGLST:
2190 losing++;
2191 break;
2192 default:
2193 break;
2194 }
2195 break;
2196
252b5132
RH		 2197 case 'X':
2198 if (opP->mode != CONTROL
2199 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2200 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2201 losing++;
2202 break;
2203
2204 case 'Y':
2205 if (opP->mode != CONTROL || opP->reg != PSR)
2206 losing++;
2207 break;
2208
2209 case 'Z':
2210 if (opP->mode != CONTROL || opP->reg != PCSR)
2211 losing++;
2212 break;
2213#endif
2214 case 'c':
2215 if (opP->mode != CONTROL
2216 || (opP->reg != NC
2217 && opP->reg != IC
2218 && opP->reg != DC
2219 && opP->reg != BC))
36759679 2220 losing++;
252b5132
RH		 2221 break;
2222
2223 case '_':
2224 if (opP->mode != ABSL)
2225 ++losing;
2226 break;
2227
6da466c7
ILT		 2228 case 'u':
2229 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2230 losing++;
2231 /* FIXME: kludge instead of fixing parser:
2232 upper/lower registers are *not* CONTROL
92774660 2233 registers, but ordinary ones. */
6da466c7
ILT		 2234 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2235 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2236 opP->mode = DREG;
2237 else
2238 opP->mode = AREG;
2239 break;
2240
3e602632
NC		 2241 case 'y':
2242 if (!(opP->mode == AINDR
31302357
AS		 2243 || (opP->mode == DISP
2244 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2245 losing++;
2246 break;
2247
2248 case 'z':
2249 if (!(opP->mode == AINDR || opP->mode == DISP))
2250 losing++;
2251 break;
2252
252b5132
RH		 2253 default:
2254 abort ();
36759679 2255 }
252b5132
RH		 2256
2257 if (losing)
2258 break;
36759679 2259 }
03b13e59
NC		 2260
2261 /* Since we have found the correct instruction, copy
2262 in the modifications that we may have made. */
2263 if (!losing)
2264 for (i = 0; i < opsfound; i++)
2265 the_ins.operands[i] = operands_backup[i];
36759679 2266 }
252b5132
RH		 2267
2268 if (!losing)
36759679 2269 break;
252b5132
RH		 2270
2271 opcode = opcode->m_next;
2272
2273 if (!opcode)
2274 {
2275 if (ok_arch
2276 && !(ok_arch & current_architecture))
2277 {
6d89cc8f
NS		 2278 const struct m68k_cpu *cpu;
2279 int any = 0;
2280 size_t space = 400;
325801bd 2281 char *buf = XNEWVEC (char, space + 1);
6d89cc8f
NS		 2282 size_t len;
2283 int paren = 1;
2284
2285 the_ins.error = buf;
2286 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2287 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2288 buf[space] = 0;
2289#define APPEND(STRING) \
2290 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2291
2292 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2293 switch (ok_arch)
2294 {
6b6e92f4 2295 case mcfisa_a:
b2f58c0c 2296 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2297 break;
2298 case mcfhwdiv:
b2f58c0c
NC		 2299 APPEND ("ColdFire ");
2300 APPEND (_("hardware divide"));
6b6e92f4
NC		 2301 break;
2302 case mcfisa_aa:
b2f58c0c 2303 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2304 break;
2305 case mcfisa_b:
b2f58c0c 2306 APPEND ("ColdFire ISA_B");
6b6e92f4 2307 break;
8d100c32 2308 case mcfisa_c:
b2f58c0c 2309 APPEND ("ColdFire ISA_C");
8d100c32 2310 break;
3e602632 2311 case cfloat:
b2f58c0c 2312 APPEND ("ColdFire fpu");
3e602632 2313 break;
252b5132 2314 case mfloat:
b2f58c0c 2315 APPEND ("M68K fpu");
252b5132
RH		 2316 break;
2317 case mmmu:
b2f58c0c 2318 APPEND ("M68K mmu");
252b5132
RH		 2319 break;
2320 case m68020up:
b2f58c0c
NC		 2321 APPEND ("68020 ");
2322 APPEND (_("or higher"));
252b5132
RH		 2323 break;
2324 case m68000up:
b2f58c0c
NC		 2325 APPEND ("68000 ");
2326 APPEND (_("or higher"));
252b5132
RH		 2327 break;
2328 case m68010up:
b2f58c0c
NC		 2329 APPEND ("68010 ");
2330 APPEND (_("or higher"));
252b5132
RH		 2331 break;
2332 default:
6d89cc8f
NS		 2333 paren = 0;
2334 }
2335 if (paren)
2336 APPEND (" (");
6b6e92f4 2337
6d89cc8f
NS		 2338 for (cpu = m68k_cpus; cpu->name; cpu++)
2339 if (!cpu->alias && (cpu->arch & ok_arch))
2340 {
2341 const struct m68k_cpu *alias;
869ddf2a 2342 int seen_master = 0;
3739860c 2343
6d89cc8f
NS		 2344 if (any)
2345 APPEND (", ");
2346 any = 0;
2347 APPEND (cpu->name);
869ddf2a
NS		 2348 for (alias = cpu; alias != m68k_cpus; alias--)
2349 if (alias[-1].alias >= 0)
2350 break;
2351 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2352 {
869ddf2a
NS		 2353 if (!alias->alias)
2354 seen_master = 1;
2355 else
2356 {
2357 if (any)
2358 APPEND (", ");
2359 else
2360 APPEND (" [");
2361 APPEND (alias->name);
2362 any = 1;
2363 }
6d89cc8f 2364 }
869ddf2a
NS		 2365 if (any)
2366 APPEND ("]");
6d89cc8f 2367 any = 1;
252b5132 2368 }
6d89cc8f
NS		 2369 if (paren)
2370 APPEND (")");
2371#undef APPEND
2372 if (!space)
2373 {
b2f58c0c 2374 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2375 with ellipsis. */
2376 buf -= 4;
2377 while (*buf != ' ')
2378 buf--;
2379 strcpy (buf, " ...");
252b5132 2380 }
252b5132
RH		 2381 }
2382 else
2383 the_ins.error = _("operands mismatch");
2384 return;
36759679 2385 }
252b5132
RH		 2386
2387 losing = 0;
2388 }
2389
36759679 2390 /* Now assemble it. */
252b5132
RH		 2391 the_ins.args = opcode->m_operands;
2392 the_ins.numargs = opcode->m_opnum;
2393 the_ins.numo = opcode->m_codenum;
2394 the_ins.opcode[0] = getone (opcode);
2395 the_ins.opcode[1] = gettwo (opcode);
2396
2397 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2398 {
9a2e615a 2399 int have_disp = 0;
cac27205 2400 int use_pl = 0;
3739860c 2401
252b5132 2402 /* This switch is a doozy.
33eaf5de 2403 Watch the first step; it's a big one! */
252b5132
RH		 2404 switch (s[0])
2405 {
2406
2407 case '*':
2408 case '~':
2409 case '%':
2410 case ';':
2411 case '@':
2412 case '!':
2413 case '&':
2414 case '$':
2415 case '?':
2416 case '/':
2417 case '<':
2418 case '>':
3e602632 2419 case 'b':
252b5132
RH		 2420 case 'm':
2421 case 'n':
2422 case 'o':
2423 case 'p':
2424 case 'q':
2425 case 'v':
3e602632
NC		 2426 case 'w':
2427 case 'y':
2428 case 'z':
fd99574b 2429 case '4':
252b5132
RH		 2430#ifndef NO_68851
2431 case '|':
2432#endif
2433 switch (opP->mode)
2434 {
2435 case IMMED:
2436 tmpreg = 0x3c; /* 7.4 */
2437 if (strchr ("bwl", s[1]))
3e602632 2438 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2439 else
2440 nextword = get_num (&opP->disp, 0);
2441 if (isvar (&opP->disp))
2442 add_fix (s[1], &opP->disp, 0, 0);
2443 switch (s[1])
2444 {
2445 case 'b':
2446 if (!isbyte (nextword))
2447 opP->error = _("operand out of range");
2448 addword (nextword);
2449 baseo = 0;
2450 break;
2451 case 'w':
2452 if (!isword (nextword))
2453 opP->error = _("operand out of range");
2454 addword (nextword);
2455 baseo = 0;
2456 break;
2457 case 'W':
2458 if (!issword (nextword))
2459 opP->error = _("operand out of range");
2460 addword (nextword);
2461 baseo = 0;
2462 break;
2463 case 'l':
2464 addword (nextword >> 16);
2465 addword (nextword);
2466 baseo = 0;
2467 break;
2468
2469 case 'f':
2470 baseo = 2;
2471 outro = 8;
2472 break;
2473 case 'F':
2474 baseo = 4;
2475 outro = 11;
2476 break;
2477 case 'x':
2478 baseo = 6;
2479 outro = 15;
2480 break;
2481 case 'p':
2482 baseo = 6;
2483 outro = -1;
2484 break;
2485 default:
2486 abort ();
2487 }
2488 if (!baseo)
2489 break;
2490
36759679 2491 /* We gotta put out some float. */
252b5132
RH		 2492 if (op (&opP->disp) != O_big)
2493 {
2494 valueT val;
2495 int gencnt;
2496
2497 /* Can other cases happen here? */
2498 if (op (&opP->disp) != O_constant)
2499 abort ();
2500
2501 val = (valueT) offs (&opP->disp);
2502 gencnt = 0;
2503 do
2504 {
2505 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2506 val >>= LITTLENUM_NUMBER_OF_BITS;
2507 ++gencnt;
2508 }
2509 while (val != 0);
2510 offs (&opP->disp) = gencnt;
2511 }
2512 if (offs (&opP->disp) > 0)
2513 {
2514 if (offs (&opP->disp) > baseo)
2515 {
2516 as_warn (_("Bignum too big for %c format; truncated"),
2517 s[1]);
2518 offs (&opP->disp) = baseo;
2519 }
2520 baseo -= offs (&opP->disp);
2521 while (baseo--)
2522 addword (0);
2523 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2524 offs (&opP->disp)--;
2525 --wordp)
2526 addword (*wordp);
2527 break;
2528 }
2529 gen_to_words (words, baseo, (long) outro);
2530 for (wordp = words; baseo--; wordp++)
2531 addword (*wordp);
2532 break;
2533 case DREG:
2534 tmpreg = opP->reg - DATA; /* 0.dreg */
2535 break;
2536 case AREG:
2537 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2538 break;
2539 case AINDR:
2540 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2541 break;
2542 case ADEC:
2543 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2544 break;
2545 case AINC:
2546 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2547 break;
2548 case DISP:
2549
3e602632 2550 nextword = get_num (&opP->disp, 90);
252b5132 2551
580b9172
NC		 2552 /* Convert mode 5 addressing with a zero offset into
2553 mode 2 addressing to reduce the instruction size by a
2554 word. */
2555 if (! isvar (&opP->disp)
2556 && (nextword == 0)
2557 && (opP->disp.size == SIZE_UNSPEC)
2558 && (opP->reg >= ADDR0)
2559 && (opP->reg <= ADDR7))
2560 {
2561 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2562 break;
2563 }
2564
252b5132
RH		 2565 if (opP->reg == PC
2566 && ! isvar (&opP->disp)
2567 && m68k_abspcadd)
2568 {
2569 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2570 opP->disp.exp.X_add_symbol =
2571 section_symbol (absolute_section);
252b5132
RH		 2572 }
2573
36759679 2574 /* Force into index mode. Hope this works. */
252b5132
RH		 2575
2576 /* We do the first bit for 32-bit displacements, and the
2577 second bit for 16 bit ones. It is possible that we
2578 should make the default be WORD instead of LONG, but
2579 I think that'd break GCC, so we put up with a little
2580 inefficiency for the sake of working output. */
2581
2582 if (!issword (nextword)
2583 || (isvar (&opP->disp)
2584 && ((opP->disp.size == SIZE_UNSPEC
2585 && flag_short_refs == 0
2586 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2587 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2588 || opP->disp.size == SIZE_LONG)))
2589 {
2590 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2591 || arch_coldfire_p (current_architecture))
252b5132
RH		 2592 opP->error =
2593 _("displacement too large for this architecture; needs 68020 or higher");
2594 if (opP->reg == PC)
2595 tmpreg = 0x3B; /* 7.3 */
2596 else
2597 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2598 if (isvar (&opP->disp))
2599 {
2600 if (opP->reg == PC)
2601 {
2602 if (opP->disp.size == SIZE_LONG
252b5132
RH		 2603 /* If the displacement needs pic
2604 relocation it cannot be relaxed. */
dc12032b 2605 || opP->disp.pic_reloc != pic_none)
252b5132
RH		 2606 {
2607 addword (0x0170);
2608 add_fix ('l', &opP->disp, 1, 2);
2609 }
2610 else
2611 {
2612 add_frag (adds (&opP->disp),
bd17c2c3 2613 SEXT (offs (&opP->disp)),
151337e8 2614 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2615 break;
2616 }
2617 }
2618 else
2619 {
2620 addword (0x0170);
2621 add_fix ('l', &opP->disp, 0, 0);
2622 }
2623 }
2624 else
2625 addword (0x0170);
2626 addword (nextword >> 16);
2627 }
2628 else
2629 {
2630 if (opP->reg == PC)
2631 tmpreg = 0x3A; /* 7.2 */
2632 else
2633 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2634
2635 if (isvar (&opP->disp))
2636 {
2637 if (opP->reg == PC)
2638 {
2639 add_fix ('w', &opP->disp, 1, 0);
2640 }
2641 else
2642 add_fix ('w', &opP->disp, 0, 0);
2643 }
2644 }
2645 addword (nextword);
2646 break;
2647
2648 case POST:
2649 case PRE:
2650 case BASE:
2651 nextword = 0;
3e602632 2652 baseo = get_num (&opP->disp, 90);
252b5132 2653 if (opP->mode == POST || opP->mode == PRE)
3e602632 2654 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2655 /* Figure out the `addressing mode'.
2656 Also turn on the BASE_DISABLE bit, if needed. */
2657 if (opP->reg == PC || opP->reg == ZPC)
2658 {
2659 tmpreg = 0x3b; /* 7.3 */
2660 if (opP->reg == ZPC)
2661 nextword |= 0x80;
2662 }
2663 else if (opP->reg == 0)
2664 {
2665 nextword |= 0x80;
2666 tmpreg = 0x30; /* 6.garbage */
2667 }
2668 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2669 {
2670 nextword |= 0x80;
2671 tmpreg = 0x30 + opP->reg - ZADDR0;
2672 }
2673 else
2674 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2675
2676 siz1 = opP->disp.size;
2677 if (opP->mode == POST || opP->mode == PRE)
2678 siz2 = opP->odisp.size;
2679 else
2680 siz2 = SIZE_UNSPEC;
2681
36759679 2682 /* Index register stuff. */
252b5132
RH		 2683 if (opP->index.reg != 0
2684 && opP->index.reg >= DATA
2685 && opP->index.reg <= ADDR7)
2686 {
2687 nextword |= (opP->index.reg - DATA) << 12;
2688
2689 if (opP->index.size == SIZE_LONG
2690 || (opP->index.size == SIZE_UNSPEC
2691 && m68k_index_width_default == SIZE_LONG))
2692 nextword |= 0x800;
2693
92774660 2694 if ((opP->index.scale != 1
252b5132 2695 && cpu_of_arch (current_architecture) < m68020)
92774660 2696 || (opP->index.scale == 8
3e602632 2697 && (arch_coldfire_p (current_architecture)
6b6e92f4 2698 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2699 {
2700 opP->error =
2701 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2702 }
2703
6da466c7
ILT		 2704 if (arch_coldfire_p (current_architecture)
2705 && opP->index.size == SIZE_WORD)
2706 opP->error = _("invalid index size for coldfire");
2707
252b5132
RH		 2708 switch (opP->index.scale)
2709 {
2710 case 1:
2711 break;
2712 case 2:
2713 nextword |= 0x200;
2714 break;
2715 case 4:
2716 nextword |= 0x400;
2717 break;
2718 case 8:
2719 nextword |= 0x600;
2720 break;
2721 default:
2722 abort ();
2723 }
33eaf5de 2724 /* IF it's simple,
252b5132
RH		 2725 GET US OUT OF HERE! */
2726
2727 /* Must be INDEX, with an index register. Address
2728 register cannot be ZERO-PC, and either :b was
2729 forced, or we know it will fit. For a 68000 or
2730 68010, force this mode anyways, because the
2731 larger modes aren't supported. */
2732 if (opP->mode == BASE
2733 && ((opP->reg >= ADDR0
2734 && opP->reg <= ADDR7)
2735 || opP->reg == PC))
2736 {
2737 if (siz1 == SIZE_BYTE
2738 || cpu_of_arch (current_architecture) < m68020
6da466c7 2739 || arch_coldfire_p (current_architecture)
252b5132
RH		 2740 || (siz1 == SIZE_UNSPEC
2741 && ! isvar (&opP->disp)
2742 && issbyte (baseo)))
2743 {
2744 nextword += baseo & 0xff;
2745 addword (nextword);
2746 if (isvar (&opP->disp))
2747 {
2748 /* Do a byte relocation. If it doesn't
2749 fit (possible on m68000) let the
2750 fixup processing complain later. */
2751 if (opP->reg == PC)
2752 add_fix ('B', &opP->disp, 1, 1);
2753 else
2754 add_fix ('B', &opP->disp, 0, 0);
2755 }
2756 else if (siz1 != SIZE_BYTE)
2757 {
2758 if (siz1 != SIZE_UNSPEC)
2759 as_warn (_("Forcing byte displacement"));
2760 if (! issbyte (baseo))
2761 opP->error = _("byte displacement out of range");
2762 }
2763
2764 break;
2765 }
2766 else if (siz1 == SIZE_UNSPEC
2767 && opP->reg == PC
2768 && isvar (&opP->disp)
2769 && subs (&opP->disp) == NULL
252b5132
RH		 2770 /* If the displacement needs pic
2771 relocation it cannot be relaxed. */
dc12032b 2772 && opP->disp.pic_reloc == pic_none)
252b5132
RH		 2773 {
2774 /* The code in md_convert_frag_1 needs to be
2775 able to adjust nextword. Call frag_grow
2776 to ensure that we have enough space in
2777 the frag obstack to make all the bytes
2778 contiguous. */
2779 frag_grow (14);
8a104df9
KH		 2780 nextword += baseo & 0xff;
2781 addword (nextword);
bd17c2c3
AM		 2782 add_frag (adds (&opP->disp),
2783 SEXT (offs (&opP->disp)),
8a104df9 2784 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2785
2786 break;
8a104df9 2787 }
252b5132
RH		 2788 }
2789 }
2790 else
2791 {
36759679 2792 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2793 if (opP->index.reg >= ZDATA0
2794 && opP->index.reg <= ZDATA7)
2795 nextword |= (opP->index.reg - ZDATA0) << 12;
2796 else if (opP->index.reg >= ZADDR0
2797 || opP->index.reg <= ZADDR7)
2798 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2799 }
2800
2801 /* It isn't simple. */
2802
2803 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2804 || arch_coldfire_p (current_architecture))
252b5132
RH		 2805 opP->error =
2806 _("invalid operand mode for this architecture; needs 68020 or higher");
2807
2808 nextword |= 0x100;
2809 /* If the guy specified a width, we assume that it is
2810 wide enough. Maybe it isn't. If so, we lose. */
2811 switch (siz1)
2812 {
2813 case SIZE_UNSPEC:
2814 if (isvar (&opP->disp)
2815 ? m68k_rel32
2816 : ! issword (baseo))
2817 {
2818 siz1 = SIZE_LONG;
2819 nextword |= 0x30;
2820 }
2821 else if (! isvar (&opP->disp) && baseo == 0)
2822 nextword |= 0x10;
2823 else
2824 {
2825 nextword |= 0x20;
2826 siz1 = SIZE_WORD;
2827 }
2828 break;
2829 case SIZE_BYTE:
2830 as_warn (_(":b not permitted; defaulting to :w"));
2831 /* Fall through. */
2832 case SIZE_WORD:
2833 nextword |= 0x20;
2834 break;
2835 case SIZE_LONG:
2836 nextword |= 0x30;
2837 break;
2838 }
2839
67c1ffbe 2840 /* Figure out inner displacement stuff. */
252b5132
RH		 2841 if (opP->mode == POST || opP->mode == PRE)
2842 {
2843 if (cpu_of_arch (current_architecture) & cpu32)
2844 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2845 switch (siz2)
2846 {
2847 case SIZE_UNSPEC:
2848 if (isvar (&opP->odisp)
2849 ? m68k_rel32
2850 : ! issword (outro))
2851 {
2852 siz2 = SIZE_LONG;
2853 nextword |= 0x3;
2854 }
2855 else if (! isvar (&opP->odisp) && outro == 0)
2856 nextword |= 0x1;
2857 else
2858 {
2859 nextword |= 0x2;
2860 siz2 = SIZE_WORD;
2861 }
2862 break;
2863 case 1:
2864 as_warn (_(":b not permitted; defaulting to :w"));
2865 /* Fall through. */
2866 case 2:
2867 nextword |= 0x2;
2868 break;
2869 case 3:
2870 nextword |= 0x3;
2871 break;
2872 }
2873 if (opP->mode == POST
2874 && (nextword & 0x40) == 0)
2875 nextword |= 0x04;
2876 }
2877 addword (nextword);
2878
2879 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2880 {
2881 if (opP->reg == PC || opP->reg == ZPC)
2882 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2883 else
2884 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2885 }
2886 if (siz1 == SIZE_LONG)
2887 addword (baseo >> 16);
2888 if (siz1 != SIZE_UNSPEC)
2889 addword (baseo);
2890
2891 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2892 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2893 if (siz2 == SIZE_LONG)
2894 addword (outro >> 16);
2895 if (siz2 != SIZE_UNSPEC)
2896 addword (outro);
2897
2898 break;
2899
2900 case ABSL:
3e602632 2901 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2902 switch (opP->disp.size)
2903 {
2904 default:
2905 abort ();
2906 case SIZE_UNSPEC:
2907 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2908 {
2909 tmpreg = 0x38; /* 7.0 */
2910 addword (nextword);
2911 break;
2912 }
252b5132
RH		 2913 if (isvar (&opP->disp)
2914 && !subs (&opP->disp)
2915 && adds (&opP->disp)
252b5132
RH		 2916 /* If the displacement needs pic relocation it
2917 cannot be relaxed. */
2918 && opP->disp.pic_reloc == pic_none
252b5132
RH		 2919 && !flag_long_jumps
2920 && !strchr ("~%&$?", s[0]))
2921 {
2922 tmpreg = 0x3A; /* 7.2 */
2923 add_frag (adds (&opP->disp),
bd17c2c3 2924 SEXT (offs (&opP->disp)),
151337e8 2925 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2926 break;
2927 }
1a0670f3 2928 /* Fall through. */
252b5132
RH		 2929 case SIZE_LONG:
2930 if (isvar (&opP->disp))
2931 add_fix ('l', &opP->disp, 0, 0);
2932
2933 tmpreg = 0x39;/* 7.1 mode */
2934 addword (nextword >> 16);
2935 addword (nextword);
2936 break;
2937
2938 case SIZE_BYTE:
2939 as_bad (_("unsupported byte value; use a different suffix"));
2940 /* Fall through. */
36759679
NC		 2941
2942 case SIZE_WORD:
252b5132
RH		 2943 if (isvar (&opP->disp))
2944 add_fix ('w', &opP->disp, 0, 0);
2945
2946 tmpreg = 0x38;/* 7.0 mode */
2947 addword (nextword);
2948 break;
2949 }
2950 break;
2951 case CONTROL:
2952 case FPREG:
2953 default:
2954 as_bad (_("unknown/incorrect operand"));
bc805888 2955 /* abort (); */
252b5132 2956 }
fd99574b
NC		 2957
2958 /* If s[0] is '4', then this is for the mac instructions
2959 that can have a trailing_ampersand set. If so, set 0x100
2960 bit on tmpreg so install_gen_operand can check for it and
2961 set the appropriate bit (word2, bit 5). */
2962 if (s[0] == '4')
2963 {
2964 if (opP->trailing_ampersand)
2965 tmpreg |= 0x100;
2966 }
252b5132
RH		 2967 install_gen_operand (s[1], tmpreg);
2968 break;
2969
2970 case '#':
2971 case '^':
2972 switch (s[1])
2973 { /* JF: I hate floating point! */
2974 case 'j':
2975 tmpreg = 70;
2976 break;
2977 case '8':
2978 tmpreg = 20;
2979 break;
2980 case 'C':
2981 tmpreg = 50;
2982 break;
2983 case '3':
2984 default:
3e602632 2985 tmpreg = 90;
252b5132
RH		 2986 break;
2987 }
2988 tmpreg = get_num (&opP->disp, tmpreg);
2989 if (isvar (&opP->disp))
2990 add_fix (s[1], &opP->disp, 0, 0);
2991 switch (s[1])
2992 {
2993 case 'b': /* Danger: These do no check for
2994 certain types of overflow.
2995 user beware! */
2996 if (!isbyte (tmpreg))
2997 opP->error = _("out of range");
2998 insop (tmpreg, opcode);
2999 if (isvar (&opP->disp))
3000 the_ins.reloc[the_ins.nrel - 1].n =
3001 (opcode->m_codenum) * 2 + 1;
3002 break;
3003 case 'B':
3004 if (!issbyte (tmpreg))
3005 opP->error = _("out of range");
3006 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3007 if (isvar (&opP->disp))
3008 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3009 break;
3010 case 'w':
3011 if (!isword (tmpreg))
3012 opP->error = _("out of range");
3013 insop (tmpreg, opcode);
3014 if (isvar (&opP->disp))
3015 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3016 break;
3017 case 'W':
3018 if (!issword (tmpreg))
3019 opP->error = _("out of range");
3020 insop (tmpreg, opcode);
3021 if (isvar (&opP->disp))
3022 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3023 break;
3024 case 'l':
3025 /* Because of the way insop works, we put these two out
3026 backwards. */
3027 insop (tmpreg, opcode);
3028 insop (tmpreg >> 16, opcode);
3029 if (isvar (&opP->disp))
3030 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3031 break;
3032 case '3':
3033 tmpreg &= 0xFF;
1a0670f3 3034 /* Fall through. */
252b5132
RH		 3035 case '8':
3036 case 'C':
3037 case 'j':
3038 install_operand (s[1], tmpreg);
3039 break;
3040 default:
3041 abort ();
3042 }
3043 break;
3044
3045 case '+':
3046 case '-':
3047 case 'A':
3048 case 'a':
3049 install_operand (s[1], opP->reg - ADDR);
3050 break;
3051
3052 case 'B':
3e602632 3053 tmpreg = get_num (&opP->disp, 90);
3739860c 3054
252b5132
RH		 3055 switch (s[1])
3056 {
3057 case 'B':
8390138c 3058 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3059 break;
3060 case 'W':
3061 add_fix ('w', &opP->disp, 1, 0);
3062 addword (0);
3063 break;
3064 case 'L':
3065 long_branch:
151337e8 3066 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3067 add_fix ('l', &opP->disp, 1, 0);
3068 addword (0);
3069 addword (0);
3070 break;
9a2e615a
NS		 3071 case 'g': /* Conditional branch */
3072 have_disp = HAVE_LONG_CALL (current_architecture);
3073 goto var_branch;
3739860c 3074
9a2e615a
NS		 3075 case 'b': /* Unconditional branch */
3076 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3077 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a 3078 goto var_branch;
3739860c 3079
9a2e615a
NS		 3080 case 's': /* Unconditional subroutine */
3081 have_disp = HAVE_LONG_CALL (current_architecture);
3739860c 3082
9a2e615a
NS		 3083 var_branch:
3084 if (subs (&opP->disp) /* We can't relax it. */
9a2e615a
NS		 3085 /* If the displacement needs pic relocation it cannot be
3086 relaxed. */
dc12032b 3087 || opP->disp.pic_reloc != pic_none)
9a2e615a
NS		 3088 {
3089 if (!have_disp)
3090 as_warn (_("Can't use long branches on this architecture"));
3091 goto long_branch;
3092 }
3739860c 3093
252b5132 3094 /* This could either be a symbol, or an absolute
151337e8
NC		 3095 address. If it's an absolute address, turn it into
3096 an absolute jump right here and keep it out of the
3097 relaxer. */
3098 if (adds (&opP->disp) == 0)
3099 {
3100 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3101 the_ins.opcode[0] = 0x4EF9;
151337e8 3102 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3103 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3104 else /* jCC */
3105 {
3106 the_ins.opcode[0] ^= 0x0100;
3107 the_ins.opcode[0] |= 0x0006;
18566f55 3108 addword (0x4EF9);
151337e8
NC		 3109 }
3110 add_fix ('l', &opP->disp, 0, 0);
3111 addword (0);
3112 addword (0);
3113 break;
3114 }
3115
3116 /* Now we know it's going into the relaxer. Now figure
3117 out which mode. We try in this order of preference:
3118 long branch, absolute jump, byte/word branches only. */
9a2e615a 3119 if (have_disp)
bd17c2c3
AM		 3120 add_frag (adds (&opP->disp),
3121 SEXT (offs (&opP->disp)),
151337e8
NC		 3122 TAB (BRANCHBWL, SZ_UNDEF));
3123 else if (! flag_keep_pcrel)
3124 {
3125 if ((the_ins.opcode[0] == 0x6000)
3126 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3127 add_frag (adds (&opP->disp),
3128 SEXT (offs (&opP->disp)),
151337e8
NC		 3129 TAB (BRABSJUNC, SZ_UNDEF));
3130 else
bd17c2c3
AM		 3131 add_frag (adds (&opP->disp),
3132 SEXT (offs (&opP->disp)),
151337e8
NC		 3133 TAB (BRABSJCOND, SZ_UNDEF));
3134 }
252b5132 3135 else
bd17c2c3
AM		 3136 add_frag (adds (&opP->disp),
3137 SEXT (offs (&opP->disp)),
cac27205
NC		 3138 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3139 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3140 break;
3141 case 'w':
3142 if (isvar (&opP->disp))
3143 {
151337e8
NC		 3144 /* Check for DBcc instructions. We can relax them,
3145 but only if we have long branches and/or absolute
3146 jumps. */
3147 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3148 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3149 || ! flag_keep_pcrel))
252b5132 3150 {
151337e8 3151 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3152 add_frag (adds (&opP->disp),
3153 SEXT (offs (&opP->disp)),
151337e8
NC		 3154 TAB (DBCCLBR, SZ_UNDEF));
3155 else
bd17c2c3
AM		 3156 add_frag (adds (&opP->disp),
3157 SEXT (offs (&opP->disp)),
151337e8 3158 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3159 break;
3160 }
252b5132
RH		 3161 add_fix ('w', &opP->disp, 1, 0);
3162 }
3163 addword (0);
3164 break;
36759679 3165 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3166 add_fix ('l', &opP->disp, 1, 0);
3167 addword (0);
3168 addword (0);
3169 break;
36759679 3170 case 'c': /* Var size Coprocesssor branches. */
151337e8 3171 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3172 {
252b5132
RH		 3173 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3174 add_fix ('l', &opP->disp, 1, 0);
3175 addword (0);
3176 addword (0);
3177 }
151337e8 3178 else
bd17c2c3
AM		 3179 add_frag (adds (&opP->disp),
3180 SEXT (offs (&opP->disp)),
151337e8 3181 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3182 break;
3183 default:
3184 abort ();
3185 }
3186 break;
3187
36759679 3188 case 'C': /* Ignore it. */
252b5132
RH		 3189 break;
3190
36759679 3191 case 'd': /* JF this is a kludge. */
252b5132 3192 install_operand ('s', opP->reg - ADDR);
3e602632 3193 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3194 if (!issword (tmpreg))
3195 {
3196 as_warn (_("Expression out of range, using 0"));
3197 tmpreg = 0;
3198 }
3199 addword (tmpreg);
3200 break;
3201
3202 case 'D':
3203 install_operand (s[1], opP->reg - DATA);
3204 break;
3205
fd99574b
NC		 3206 case 'e': /* EMAC ACCx, reg/reg. */
3207 install_operand (s[1], opP->reg - ACC);
3208 break;
3739860c 3209
36759679 3210 case 'E': /* Ignore it. */
6da466c7
ILT		 3211 break;
3212
252b5132
RH		 3213 case 'F':
3214 install_operand (s[1], opP->reg - FP0);
3215 break;
3216
fd99574b
NC		 3217 case 'g': /* EMAC ACCEXTx. */
3218 install_operand (s[1], opP->reg - ACCEXT01);
3219 break;
3220
36759679 3221 case 'G': /* Ignore it. */
6da466c7
ILT		 3222 case 'H':
3223 break;
3224
252b5132
RH		 3225 case 'I':
3226 tmpreg = opP->reg - COP0;
3227 install_operand (s[1], tmpreg);
3228 break;
3229
fd99574b
NC		 3230 case 'i': /* MAC/EMAC scale factor. */
3231 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3232 break;
3233
36759679 3234 case 'J': /* JF foo. */
252b5132
RH		 3235 switch (opP->reg)
3236 {
3237 case SFC:
3238 tmpreg = 0x000;
3239 break;
3240 case DFC:
3241 tmpreg = 0x001;
3242 break;
3243 case CACR:
3244 tmpreg = 0x002;
3245 break;
3246 case TC:
a8e24a56 3247 case ASID:
252b5132
RH		 3248 tmpreg = 0x003;
3249 break;
3e602632 3250 case ACR0:
252b5132
RH		 3251 case ITT0:
3252 tmpreg = 0x004;
3253 break;
3e602632 3254 case ACR1:
252b5132
RH		 3255 case ITT1:
3256 tmpreg = 0x005;
3257 break;
3e602632 3258 case ACR2:
252b5132
RH		 3259 case DTT0:
3260 tmpreg = 0x006;
3261 break;
3e602632 3262 case ACR3:
252b5132
RH		 3263 case DTT1:
3264 tmpreg = 0x007;
3265 break;
3266 case BUSCR:
a8e24a56 3267 case MMUBAR:
252b5132
RH		 3268 tmpreg = 0x008;
3269 break;
0d999f33
MK		 3270 case RGPIOBAR:
3271 tmpreg = 0x009;
3272 break;
3273 case ACR4:
3274 case ACR5:
3275 case ACR6:
3276 case ACR7:
3277 tmpreg = 0x00c + (opP->reg - ACR4);
3278 break;
252b5132
RH		 3279
3280 case USP:
3281 tmpreg = 0x800;
3282 break;
3283 case VBR:
3284 tmpreg = 0x801;
3285 break;
3286 case CAAR:
87298967 3287 case CPUCR:
252b5132
RH		 3288 tmpreg = 0x802;
3289 break;
3290 case MSP:
3291 tmpreg = 0x803;
3292 break;
3293 case ISP:
3294 tmpreg = 0x804;
3295 break;
3296 case MMUSR:
3297 tmpreg = 0x805;
3298 break;
3299 case URP:
3300 tmpreg = 0x806;
3301 break;
3302 case SRP:
3303 tmpreg = 0x807;
3304 break;
3305 case PCR:
3306 tmpreg = 0x808;
3307 break;
3308 case ROMBAR:
a8e24a56 3309 case ROMBAR0:
252b5132
RH		 3310 tmpreg = 0xC00;
3311 break;
3e602632
NC		 3312 case ROMBAR1:
3313 tmpreg = 0xC01;
3314 break;
3315 case FLASHBAR:
252b5132 3316 case RAMBAR0:
78336706 3317 case RAMBAR_ALT:
252b5132
RH		 3318 tmpreg = 0xC04;
3319 break;
3e602632 3320 case RAMBAR:
252b5132
RH		 3321 case RAMBAR1:
3322 tmpreg = 0xC05;
3323 break;
3e602632
NC		 3324 case MPCR:
3325 tmpreg = 0xC0C;
3326 break;
3327 case EDRAMBAR:
3328 tmpreg = 0xC0D;
3329 break;
3330 case MBAR0:
e80e0390 3331 case MBAR2:
3e602632
NC		 3332 case SECMBAR:
3333 tmpreg = 0xC0E;
3334 break;
3335 case MBAR1:
252b5132
RH		 3336 case MBAR:
3337 tmpreg = 0xC0F;
3338 break;
3e602632
NC		 3339 case PCR1U0:
3340 tmpreg = 0xD02;
3341 break;
3342 case PCR1L0:
3343 tmpreg = 0xD03;
3344 break;
3345 case PCR2U0:
3346 tmpreg = 0xD04;
3347 break;
3348 case PCR2L0:
3349 tmpreg = 0xD05;
3350 break;
3351 case PCR3U0:
3352 tmpreg = 0xD06;
3353 break;
3354 case PCR3L0:
3355 tmpreg = 0xD07;
3356 break;
3357 case PCR1L1:
3358 tmpreg = 0xD0A;
3359 break;
3360 case PCR1U1:
3361 tmpreg = 0xD0B;
3362 break;
3363 case PCR2L1:
3364 tmpreg = 0xD0C;
3365 break;
3366 case PCR2U1:
3367 tmpreg = 0xD0D;
3368 break;
3369 case PCR3L1:
3370 tmpreg = 0xD0E;
3371 break;
3372 case PCR3U1:
3373 tmpreg = 0xD0F;
3374 break;
f7ec513b
KH		 3375 case CAC:
3376 tmpreg = 0xFFE;
3377 break;
d0fa1372 3378 case MBO:
f7ec513b
KH		 3379 tmpreg = 0xFFF;
3380 break;
252b5132
RH		 3381 default:
3382 abort ();
3383 }
3384 install_operand (s[1], tmpreg);
3385 break;
3386
3387 case 'k':
3388 tmpreg = get_num (&opP->disp, 55);
3389 install_operand (s[1], tmpreg & 0x7f);
3390 break;
3391
3392 case 'l':
3393 tmpreg = opP->mask;
3394 if (s[1] == 'w')
3395 {
3396 if (tmpreg & 0x7FF0000)
3397 as_bad (_("Floating point register in register list"));
3398 insop (reverse_16_bits (tmpreg), opcode);
3399 }
3400 else
3401 {
3402 if (tmpreg & 0x700FFFF)
3403 as_bad (_("Wrong register in floating-point reglist"));
3404 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3405 }
3406 break;
3407
3408 case 'L':
3409 tmpreg = opP->mask;
3410 if (s[1] == 'w')
3411 {
3412 if (tmpreg & 0x7FF0000)
3413 as_bad (_("Floating point register in register list"));
3414 insop (tmpreg, opcode);
3415 }
3416 else if (s[1] == '8')
3417 {
3418 if (tmpreg & 0x0FFFFFF)
3419 as_bad (_("incorrect register in reglist"));
3420 install_operand (s[1], tmpreg >> 24);
3421 }
3422 else
3423 {
3424 if (tmpreg & 0x700FFFF)
3425 as_bad (_("wrong register in floating-point reglist"));
3426 else
3427 install_operand (s[1], tmpreg >> 16);
3428 }
3429 break;
3430
3431 case 'M':
3432 install_operand (s[1], get_num (&opP->disp, 60));
3433 break;
3434
3435 case 'O':
3436 tmpreg = ((opP->mode == DREG)
8fce3f5e 3437 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3438 : (get_num (&opP->disp, 40) & 0x1F));
3439 install_operand (s[1], tmpreg);
3440 break;
3441
3442 case 'Q':
3443 tmpreg = get_num (&opP->disp, 10);
3444 if (tmpreg == 8)
3445 tmpreg = 0;
3446 install_operand (s[1], tmpreg);
3447 break;
3448
3449 case 'R':
3450 /* This depends on the fact that ADDR registers are eight
3451 more than their corresponding DATA regs, so the result
36759679 3452 will have the ADDR_REG bit set. */
252b5132
RH		 3453 install_operand (s[1], opP->reg - DATA);
3454 break;
3455
3456 case 'r':
3457 if (opP->mode == AINDR)
3458 install_operand (s[1], opP->reg - DATA);
3459 else
3460 install_operand (s[1], opP->index.reg - DATA);
3461 break;
3462
3463 case 's':
3464 if (opP->reg == FPI)
3465 tmpreg = 0x1;
3466 else if (opP->reg == FPS)
3467 tmpreg = 0x2;
3468 else if (opP->reg == FPC)
3469 tmpreg = 0x4;
3470 else
3471 abort ();
3472 install_operand (s[1], tmpreg);
3473 break;
3474
36759679 3475 case 'S': /* Ignore it. */
252b5132
RH		 3476 break;
3477
3478 case 'T':
3479 install_operand (s[1], get_num (&opP->disp, 30));
3480 break;
3481
36759679 3482 case 'U': /* Ignore it. */
252b5132
RH		 3483 break;
3484
3485 case 'c':
3486 switch (opP->reg)
3487 {
3488 case NC:
3489 tmpreg = 0;
3490 break;
3491 case DC:
3492 tmpreg = 1;
3493 break;
3494 case IC:
3495 tmpreg = 2;
3496 break;
3497 case BC:
3498 tmpreg = 3;
3499 break;
3500 default:
3501 as_fatal (_("failed sanity check"));
36759679 3502 } /* switch on cache token. */
252b5132
RH		 3503 install_operand (s[1], tmpreg);
3504 break;
3505#ifndef NO_68851
92774660 3506 /* JF: These are out of order, I fear. */
252b5132
RH		 3507 case 'f':
3508 switch (opP->reg)
3509 {
3510 case SFC:
3511 tmpreg = 0;
3512 break;
3513 case DFC:
3514 tmpreg = 1;
3515 break;
3516 default:
3517 abort ();
3518 }
3519 install_operand (s[1], tmpreg);
3520 break;
3521
3522 case '0':
3523 case '1':
3524 case '2':
3525 switch (opP->reg)
3526 {
3527 case TC:
3528 tmpreg = 0;
3529 break;
3530 case CAL:
3531 tmpreg = 4;
3532 break;
3533 case VAL:
3534 tmpreg = 5;
3535 break;
3536 case SCC:
3537 tmpreg = 6;
3538 break;
3539 case AC:
3540 tmpreg = 7;
3541 break;
3542 default:
3543 abort ();
3544 }
3545 install_operand (s[1], tmpreg);
3546 break;
3547
3548 case 'V':
3549 if (opP->reg == VAL)
3550 break;
3551 abort ();
3552
3553 case 'W':
3554 switch (opP->reg)
3555 {
3556 case DRP:
3557 tmpreg = 1;
3558 break;
3559 case SRP:
3560 tmpreg = 2;
3561 break;
3562 case CRP:
3563 tmpreg = 3;
3564 break;
3565 default:
3566 abort ();
3567 }
3568 install_operand (s[1], tmpreg);
3569 break;
3570
3571 case 'X':
3572 switch (opP->reg)
3573 {
3574 case BAD:
3575 case BAD + 1:
3576 case BAD + 2:
3577 case BAD + 3:
3578 case BAD + 4:
3579 case BAD + 5:
3580 case BAD + 6:
3581 case BAD + 7:
3582 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3583 break;
3584
3585 case BAC:
3586 case BAC + 1:
3587 case BAC + 2:
3588 case BAC + 3:
3589 case BAC + 4:
3590 case BAC + 5:
3591 case BAC + 6:
3592 case BAC + 7:
3593 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3594 break;
3595
3596 default:
3597 abort ();
3598 }
3599 install_operand (s[1], tmpreg);
3600 break;
3601 case 'Y':
3602 know (opP->reg == PSR);
3603 break;
3604 case 'Z':
3605 know (opP->reg == PCSR);
3606 break;
3607#endif /* m68851 */
3608 case '3':
3609 switch (opP->reg)
3610 {
3611 case TT0:
3612 tmpreg = 2;
3613 break;
3614 case TT1:
3615 tmpreg = 3;
3616 break;
3617 default:
3618 abort ();
3619 }
3620 install_operand (s[1], tmpreg);
3621 break;
3622 case 't':
3623 tmpreg = get_num (&opP->disp, 20);
3624 install_operand (s[1], tmpreg);
3625 break;
36759679 3626 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3627 if (isvar (&opP->disp))
3628 add_fix ('l', &opP->disp, 0, 0);
3e602632 3629 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3630 addword (tmpreg >> 16);
3631 addword (tmpreg & 0xFFFF);
3632 break;
6da466c7
ILT		 3633 case 'u':
3634 install_operand (s[1], opP->reg - DATA0L);
3635 opP->reg -= (DATA0L);
36759679 3636 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3637 break;
3e602632
NC		 3638 case 'x':
3639 tmpreg = get_num (&opP->disp, 80);
3640 if (tmpreg == -1)
3641 tmpreg = 0;
3642 install_operand (s[1], tmpreg);
3643 break;
afa2158f
NS		 3644 case 'j':
3645 tmpreg = get_num (&opP->disp, 10);
3646 install_operand (s[1], tmpreg - 1);
3647 break;
3648 case 'K':
3649 tmpreg = get_num (&opP->disp, 65);
3650 install_operand (s[1], tmpreg);
3651 break;
252b5132
RH		 3652 default:
3653 abort ();
3654 }
3655 }
3656
33eaf5de 3657 /* By the time when get here (FINALLY) the_ins contains the complete
92774660 3658 instruction, ready to be emitted. . . */
252b5132
RH		 3659}
3660
3661static int
31302357 3662reverse_16_bits (int in)
252b5132
RH		 3663{
3664 int out = 0;
3665 int n;
3666
3667 static int mask[16] =
3668 {
3669 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3670 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3671 };
3672 for (n = 0; n < 16; n++)
3673 {
3674 if (in & mask[n])
3675 out |= mask[15 - n];
3676 }
3677 return out;
3678} /* reverse_16_bits() */
3679
3680static int
31302357 3681reverse_8_bits (int in)
252b5132
RH		 3682{
3683 int out = 0;
3684 int n;
3685
3686 static int mask[8] =
3687 {
3688 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3689 };
3690
3691 for (n = 0; n < 8; n++)
3692 {
3693 if (in & mask[n])
3694 out |= mask[7 - n];
3695 }
3696 return out;
3697} /* reverse_8_bits() */
3698
cac27205
NC		 3699/* Cause an extra frag to be generated here, inserting up to
3700 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3701 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3702
3703 The TYPE parameter is also used by md_convert_frag_1 and
3704 md_estimate_size_before_relax. The appropriate type of fixup will
3705 be emitted by md_convert_frag_1.
3706
3707 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3708static void
31302357 3709install_operand (int mode, int val)
252b5132
RH		 3710{
3711 switch (mode)
3712 {
3713 case 's':
36759679 3714 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3715 break;
3716 case 'd':
3717 the_ins.opcode[0] |= val << 9;
3718 break;
afa2158f
NS		 3719 case 'E':
3720 the_ins.opcode[1] |= val << 9;
3721 break;
252b5132
RH		 3722 case '1':
3723 the_ins.opcode[1] |= val << 12;
3724 break;
3725 case '2':
3726 the_ins.opcode[1] |= val << 6;
3727 break;
3728 case '3':
3729 the_ins.opcode[1] |= val;
3730 break;
3731 case '4':
3732 the_ins.opcode[2] |= val << 12;
3733 break;
3734 case '5':
3735 the_ins.opcode[2] |= val << 6;
3736 break;
3737 case '6':
3738 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3739 three words long! */
3740 the_ins.numo++;
3741 the_ins.opcode[2] |= val;
3742 break;
3743 case '7':
3744 the_ins.opcode[1] |= val << 7;
3745 break;
3746 case '8':
3747 the_ins.opcode[1] |= val << 10;
3748 break;
3749#ifndef NO_68851
3750 case '9':
3751 the_ins.opcode[1] |= val << 5;
3752 break;
3753#endif
3754
3755 case 't':
3756 the_ins.opcode[1] |= (val << 10) | (val << 7);
3757 break;
3758 case 'D':
3759 the_ins.opcode[1] |= (val << 12) | val;
3760 break;
3761 case 'g':
3762 the_ins.opcode[0] |= val = 0xff;
3763 break;
3764 case 'i':
3765 the_ins.opcode[0] |= val << 9;
3766 break;
3767 case 'C':
3768 the_ins.opcode[1] |= val;
3769 break;
3770 case 'j':
3771 the_ins.opcode[1] |= val;
36759679 3772 the_ins.numo++; /* What a hack. */
252b5132
RH		 3773 break;
3774 case 'k':
3775 the_ins.opcode[1] |= val << 4;
3776 break;
3777 case 'b':
3778 case 'w':
3779 case 'W':
3780 case 'l':
3781 break;
3782 case 'e':
3783 the_ins.opcode[0] |= (val << 6);
3784 break;
3785 case 'L':
3786 the_ins.opcode[1] = (val >> 16);
3787 the_ins.opcode[2] = val & 0xffff;
3788 break;
6da466c7
ILT		 3789 case 'm':
3790 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3791 the_ins.opcode[0] |= ((val & 0x7) << 9);
3792 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3793 break;
fd99574b 3794 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3795 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3796 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3797 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3798 break;
fd99574b 3799 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3800 the_ins.opcode[1] |= val << 12;
3801 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3802 break;
fd99574b 3803 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3804 the_ins.opcode[0] |= (val & 0xF);
3805 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3806 break;
fd99574b 3807 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3808 the_ins.opcode[1] |= (val & 0xF);
3809 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3810 break;
3811 case 'h':
3812 the_ins.opcode[1] |= ((val != 1) << 10);
3813 break;
fd99574b
NC		 3814 case 'F':
3815 the_ins.opcode[0] |= ((val & 0x3) << 9);
3816 break;
3817 case 'f':
3818 the_ins.opcode[0] |= ((val & 0x3) << 0);
3819 break;
be8c092b 3820 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3821 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3822 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3823 break;
be8c092b 3824 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3825 the_ins.opcode[0] |= ((val & 0x1) << 7);
3826 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3827 break;
3828 case 'I':
3829 the_ins.opcode[1] |= ((val & 0x3) << 9);
3830 break;
3831 case ']':
3832 the_ins.opcode[0] |= (val & 0x1) <<10;
3833 break;
252b5132
RH		 3834 case 'c':
3835 default:
3836 as_fatal (_("failed sanity check."));
3837 }
6b6e92f4 3838}
252b5132
RH		 3839
3840static void
31302357 3841install_gen_operand (int mode, int val)
252b5132
RH		 3842{
3843 switch (mode)
3844 {
fd99574b 3845 case '/': /* Special for mask loads for mac/msac insns with
33eaf5de 3846 possible mask; trailing_ampersand set in bit 8. */
fd99574b
NC		 3847 the_ins.opcode[0] |= (val & 0x3f);
3848 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3849 break;
252b5132
RH		 3850 case 's':
3851 the_ins.opcode[0] |= val;
3852 break;
3853 case 'd':
3854 /* This is a kludge!!! */
3855 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3856 break;
3857 case 'b':
3858 case 'w':
3859 case 'l':
3860 case 'f':
3861 case 'F':
3862 case 'x':
3863 case 'p':
3864 the_ins.opcode[0] |= val;
3865 break;
36759679 3866 /* more stuff goes here. */
252b5132
RH		 3867 default:
3868 as_fatal (_("failed sanity check."));
3869 }
6b6e92f4 3870}
252b5132 3871
6b6e92f4
NC		 3872/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3873 then deal with the bitfield hack. */
252b5132
RH		 3874
3875static char *
31302357 3876crack_operand (char *str, struct m68k_op *opP)
252b5132 3877{
ed9e98c2
AM		 3878 int parens;
3879 int c;
3880 char *beg_str;
252b5132
RH		 3881 int inquote = 0;
3882
3883 if (!str)
3884 {
3885 return str;
3886 }
3887 beg_str = str;
3888 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3889 {
3890 if (! inquote)
3891 {
3892 if (*str == '(')
3893 parens++;
3894 else if (*str == ')')
3895 {
3896 if (!parens)
36759679 3897 { /* ERROR. */
252b5132
RH		 3898 opP->error = _("Extra )");
3899 return str;
3900 }
3901 --parens;
3902 }
3903 }
3904 if (flag_mri && *str == '\'')
3905 inquote = ! inquote;
3906 }
3907 if (!*str && parens)
36759679 3908 { /* ERROR. */
252b5132
RH		 3909 opP->error = _("Missing )");
3910 return str;
3911 }
3912 c = *str;
3913 *str = '\0';
3914 if (m68k_ip_op (beg_str, opP) != 0)
3915 {
3916 *str = c;
3917 return str;
3918 }
3919 *str = c;
3920 if (c == '}')
36759679 3921 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3922 if (c)
3923 {
3924 c = *++str;
3925 if (!c)
3926 as_bad (_("Missing operand"));
3927 }
3928
3929 /* Detect MRI REG symbols and convert them to REGLSTs. */
3930 if (opP->mode == CONTROL && (int)opP->reg < 0)
3931 {
3932 opP->mode = REGLST;
3933 opP->mask = ~(int)opP->reg;
3934 opP->reg = 0;
3935 }
3936
3937 return str;
3938}
3939
3940/* This is the guts of the machine-dependent assembler. STR points to a
3941 machine dependent instruction. This function is supposed to emit
3942 the frags/bytes it assembles to.
3943 */
3944
3945static void
31302357 3946insert_reg (const char *regname, int regnum)
252b5132
RH		 3947{
3948 char buf[100];
3949 int i;
3950
3951#ifdef REGISTER_PREFIX
3952 if (!flag_reg_prefix_optional)
3953 {
3954 buf[0] = REGISTER_PREFIX;
3955 strcpy (buf + 1, regname);
3956 regname = buf;
3957 }
3958#endif
3959
3960 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3961 &zero_address_frag));
3962
3963 for (i = 0; regname[i]; i++)
3882b010 3964 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3965 buf[i] = '\0';
3966
3967 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3968 &zero_address_frag));
3969}
3970
3971struct init_entry
3972 {
3973 const char *name;
3974 int number;
3975 };
3976
3977static const struct init_entry init_table[] =
3978{
3979 { "d0", DATA0 },
3980 { "d1", DATA1 },
3981 { "d2", DATA2 },
3982 { "d3", DATA3 },
3983 { "d4", DATA4 },
3984 { "d5", DATA5 },
3985 { "d6", DATA6 },
3986 { "d7", DATA7 },
3987 { "a0", ADDR0 },
3988 { "a1", ADDR1 },
3989 { "a2", ADDR2 },
3990 { "a3", ADDR3 },
3991 { "a4", ADDR4 },
3992 { "a5", ADDR5 },
3993 { "a6", ADDR6 },
3994 { "fp", ADDR6 },
3995 { "a7", ADDR7 },
3996 { "sp", ADDR7 },
3997 { "ssp", ADDR7 },
3998 { "fp0", FP0 },
3999 { "fp1", FP1 },
4000 { "fp2", FP2 },
4001 { "fp3", FP3 },
4002 { "fp4", FP4 },
4003 { "fp5", FP5 },
4004 { "fp6", FP6 },
4005 { "fp7", FP7 },
4006 { "fpi", FPI },
4007 { "fpiar", FPI },
4008 { "fpc", FPI },
4009 { "fps", FPS },
4010 { "fpsr", FPS },
4011 { "fpc", FPC },
4012 { "fpcr", FPC },
4013 { "control", FPC },
4014 { "status", FPS },
4015 { "iaddr", FPI },
4016
4017 { "cop0", COP0 },
4018 { "cop1", COP1 },
4019 { "cop2", COP2 },
4020 { "cop3", COP3 },
4021 { "cop4", COP4 },
4022 { "cop5", COP5 },
4023 { "cop6", COP6 },
4024 { "cop7", COP7 },
4025 { "pc", PC },
4026 { "zpc", ZPC },
4027 { "sr", SR },
4028
4029 { "ccr", CCR },
4030 { "cc", CCR },
4031
6da466c7 4032 { "acc", ACC },
fd99574b
NC		 4033 { "acc0", ACC },
4034 { "acc1", ACC1 },
4035 { "acc2", ACC2 },
4036 { "acc3", ACC3 },
4037 { "accext01", ACCEXT01 },
4038 { "accext23", ACCEXT23 },
6da466c7
ILT		 4039 { "macsr", MACSR },
4040 { "mask", MASK },
4041
36759679
NC		 4042 /* Control registers. */
4043 { "sfc", SFC }, /* Source Function Code. */
252b5132 4044 { "sfcr", SFC },
36759679 4045 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4046 { "dfcr", DFC },
36759679
NC		 4047 { "cacr", CACR }, /* Cache Control Register. */
4048 { "caar", CAAR }, /* Cache Address Register. */
87298967 4049 { "cpucr", CPUCR }, /* CPU Control Register. */
252b5132 4050
36759679
NC		 4051 { "usp", USP }, /* User Stack Pointer. */
4052 { "vbr", VBR }, /* Vector Base Register. */
4053 { "msp", MSP }, /* Master Stack Pointer. */
4054 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4055
36759679
NC		 4056 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4057 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4058 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4059 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4060
4061 /* 68ec040 versions of same */
36759679
NC		 4062 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4063 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4064 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4065 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4066
a8e24a56 4067 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4068 manual indicated that the order is 2,3,0,1, but Ken Rose
4069 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4070 { "acr0", ACR0 }, /* Access Control Unit 0. */
4071 { "acr1", ACR1 }, /* Access Control Unit 1. */
4072 { "acr2", ACR2 }, /* Access Control Unit 2. */
4073 { "acr3", ACR3 }, /* Access Control Unit 3. */
0d999f33
MK		 4074 { "acr4", ACR4 }, /* Access Control Unit 4. */
4075 { "acr5", ACR5 }, /* Access Control Unit 5. */
4076 { "acr6", ACR6 }, /* Access Control Unit 6. */
4077 { "acr7", ACR7 }, /* Access Control Unit 7. */
252b5132 4078
36759679 4079 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4080 { "tcr", TC },
a8e24a56 4081 { "asid", ASID },
252b5132 4082
36759679
NC		 4083 { "mmusr", MMUSR }, /* MMU Status Register. */
4084 { "srp", SRP }, /* User Root Pointer. */
4085 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4086
4087 { "buscr", BUSCR },
a8e24a56 4088 { "mmubar", MMUBAR },
252b5132
RH		 4089 { "pcr", PCR },
4090
36759679
NC		 4091 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4092 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4093 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4094 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4095
4096 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4097 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4098 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4099 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4100 { "mpcr", MPCR }, /* mcfv4e registers. */
4101 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4102 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4103 { "asid", TC }, /* mcfv4e registers. */
4104 { "mmubar", BUSCR }, /* mcfv4e registers. */
4105 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4106 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4107 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4108 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4109 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4110 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4111 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4112 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4113 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4114 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4115 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4116 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4117
4118 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4119 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4120
4121 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b 4122
0d999f33
MK		 4123 { "rgpiobar", RGPIOBAR }, /* mcf54418 registers. */
4124
f7ec513b 4125 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4126 { "mbb", MBO }, /* fido registers (obsolete). */
4127 { "mbo", MBO }, /* fido registers. */
36759679 4128 /* End of control registers. */
252b5132
RH		 4129
4130 { "ac", AC },
4131 { "bc", BC },
4132 { "cal", CAL },
4133 { "crp", CRP },
4134 { "drp", DRP },
4135 { "pcsr", PCSR },
4136 { "psr", PSR },
4137 { "scc", SCC },
4138 { "val", VAL },
4139 { "bad0", BAD0 },
4140 { "bad1", BAD1 },
4141 { "bad2", BAD2 },
4142 { "bad3", BAD3 },
4143 { "bad4", BAD4 },
4144 { "bad5", BAD5 },
4145 { "bad6", BAD6 },
4146 { "bad7", BAD7 },
4147 { "bac0", BAC0 },
4148 { "bac1", BAC1 },
4149 { "bac2", BAC2 },
4150 { "bac3", BAC3 },
4151 { "bac4", BAC4 },
4152 { "bac5", BAC5 },
4153 { "bac6", BAC6 },
4154 { "bac7", BAC7 },
4155
4156 { "ic", IC },
4157 { "dc", DC },
4158 { "nc", NC },
4159
4160 { "tt0", TT0 },
4161 { "tt1", TT1 },
36759679 4162 /* 68ec030 versions of same. */
252b5132
RH		 4163 { "ac0", TT0 },
4164 { "ac1", TT1 },
36759679 4165 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4166 { "acusr", PSR },
4167
4168 /* Suppressed data and address registers. */
4169 { "zd0", ZDATA0 },
4170 { "zd1", ZDATA1 },
4171 { "zd2", ZDATA2 },
4172 { "zd3", ZDATA3 },
4173 { "zd4", ZDATA4 },
4174 { "zd5", ZDATA5 },
4175 { "zd6", ZDATA6 },
4176 { "zd7", ZDATA7 },
4177 { "za0", ZADDR0 },
4178 { "za1", ZADDR1 },
4179 { "za2", ZADDR2 },
4180 { "za3", ZADDR3 },
4181 { "za4", ZADDR4 },
4182 { "za5", ZADDR5 },
4183 { "za6", ZADDR6 },
4184 { "za7", ZADDR7 },
4185
92774660 4186 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4187 { "d0l", DATA0L },
4188 { "d1l", DATA1L },
4189 { "d2l", DATA2L },
4190 { "d3l", DATA3L },
4191 { "d4l", DATA4L },
4192 { "d5l", DATA5L },
4193 { "d6l", DATA6L },
4194 { "d7l", DATA7L },
4195
4196 { "a0l", ADDR0L },
4197 { "a1l", ADDR1L },
4198 { "a2l", ADDR2L },
4199 { "a3l", ADDR3L },
4200 { "a4l", ADDR4L },
4201 { "a5l", ADDR5L },
4202 { "a6l", ADDR6L },
4203 { "a7l", ADDR7L },
4204
4205 { "d0u", DATA0U },
4206 { "d1u", DATA1U },
4207 { "d2u", DATA2U },
4208 { "d3u", DATA3U },
4209 { "d4u", DATA4U },
4210 { "d5u", DATA5U },
4211 { "d6u", DATA6U },
4212 { "d7u", DATA7U },
4213
4214 { "a0u", ADDR0U },
4215 { "a1u", ADDR1U },
4216 { "a2u", ADDR2U },
4217 { "a3u", ADDR3U },
4218 { "a4u", ADDR4U },
4219 { "a5u", ADDR5U },
4220 { "a6u", ADDR6U },
4221 { "a7u", ADDR7U },
4222
252b5132
RH		 4223 { 0, 0 }
4224};
4225
4226static void
31302357 4227init_regtable (void)
252b5132
RH		 4228{
4229 int i;
4230 for (i = 0; init_table[i].name; i++)
4231 insert_reg (init_table[i].name, init_table[i].number);
4232}
4233
252b5132 4234void
31302357 4235md_assemble (char *str)
252b5132
RH		 4236{
4237 const char *er;
4238 short *fromP;
4239 char *toP = NULL;
4240 int m, n = 0;
4241 char *to_beg_P;
4242 int shorts_this_frag;
4243 fixS *fixP;
4244
266abb8f
NS		 4245 if (!selected_cpu && !selected_arch)
4246 {
4247 /* We've not selected an architecture yet. Set the default
4248 now. We do this lazily so that an initial .cpu or .arch directive
4249 can specify. */
4250 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4251 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4252 }
4253 if (!initialized)
4254 m68k_init_arch ();
3739860c 4255
252b5132
RH		 4256 /* In MRI mode, the instruction and operands are separated by a
4257 space. Anything following the operands is a comment. The label
4258 has already been removed. */
4259 if (flag_mri)
4260 {
4261 char *s;
4262 int fields = 0;
4263 int infield = 0;
4264 int inquote = 0;
4265
4266 for (s = str; *s != '\0'; s++)
4267 {
4268 if ((*s == ' ' || *s == '\t') && ! inquote)
4269 {
4270 if (infield)
4271 {
4272 ++fields;
4273 if (fields >= 2)
4274 {
4275 *s = '\0';
4276 break;
4277 }
4278 infield = 0;
4279 }
4280 }
4281 else
4282 {
4283 if (! infield)
4284 infield = 1;
4285 if (*s == '\'')
4286 inquote = ! inquote;
4287 }
4288 }
4289 }
4290
31302357 4291 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4292 m68k_ip (str);
4293 er = the_ins.error;
4294 if (!er)
4295 {
4296 for (n = 0; n < the_ins.numargs; n++)
4297 if (the_ins.operands[n].error)
4298 {
4299 er = the_ins.operands[n].error;
4300 break;
4301 }
4302 }
4303 if (er)
4304 {
4305 as_bad (_("%s -- statement `%s' ignored"), er, str);
4306 return;
4307 }
4308
4309 /* If there is a current label, record that it marks an instruction. */
4310 if (current_label != NULL)
4311 {
4312 current_label->text = 1;
4313 current_label = NULL;
4314 }
4315
f27a3839
AS		 4316 /* Tie dwarf2 debug info to the address at the start of the insn. */
4317 dwarf2_emit_insn (0);
f27a3839 4318
252b5132
RH		 4319 if (the_ins.nfrag == 0)
4320 {
36759679 4321 /* No frag hacking involved; just put it out. */
252b5132
RH		 4322 toP = frag_more (2 * the_ins.numo);
4323 fromP = &the_ins.opcode[0];
4324 for (m = the_ins.numo; m; --m)
4325 {
4326 md_number_to_chars (toP, (long) (*fromP), 2);
4327 toP += 2;
4328 fromP++;
4329 }
36759679 4330 /* Put out symbol-dependent info. */
252b5132
RH		 4331 for (m = 0; m < the_ins.nrel; m++)
4332 {
4333 switch (the_ins.reloc[m].wid)
4334 {
4335 case 'B':
4336 n = 1;
4337 break;
4338 case 'b':
4339 n = 1;
4340 break;
4341 case '3':
4342 n = 1;
4343 break;
4344 case 'w':
4345 case 'W':
4346 n = 2;
4347 break;
4348 case 'l':
4349 n = 4;
4350 break;
4351 default:
33eaf5de 4352 as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
252b5132
RH		 4353 the_ins.reloc[m].wid);
4354 }
4355
4356 fixP = fix_new_exp (frag_now,
4357 ((toP - frag_now->fr_literal)
4358 - the_ins.numo * 2 + the_ins.reloc[m].n),
4359 n,
4360 &the_ins.reloc[m].exp,
4361 the_ins.reloc[m].pcrel,
4362 get_reloc_code (n, the_ins.reloc[m].pcrel,
4363 the_ins.reloc[m].pic_reloc));
4364 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4365 if (the_ins.reloc[m].wid == 'B')
4366 fixP->fx_signed = 1;
4367 }
4368 return;
4369 }
4370
36759679 4371 /* There's some frag hacking. */
fbe572f9
AM		 4372 {
4373 /* Calculate the max frag size. */
4374 int wid;
4375
4376 wid = 2 * the_ins.fragb[0].fragoff;
4377 for (n = 1; n < the_ins.nfrag; n++)
4378 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4379 /* frag_var part. */
cac27205 4380 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4381 /* Make sure the whole insn fits in one chunk, in particular that
4382 the var part is attached, as we access one byte before the
4383 variable frag for byte branches. */
4384 frag_grow (wid);
4385 }
4386
252b5132
RH		 4387 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4388 {
4389 int wid;
4390
4391 if (n == 0)
4392 wid = 2 * the_ins.fragb[n].fragoff;
4393 else
4394 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4395 toP = frag_more (wid);
4396 to_beg_P = toP;
4397 shorts_this_frag = 0;
4398 for (m = wid / 2; m; --m)
4399 {
4400 md_number_to_chars (toP, (long) (*fromP), 2);
4401 toP += 2;
4402 fromP++;
4403 shorts_this_frag++;
4404 }
4405 for (m = 0; m < the_ins.nrel; m++)
4406 {
4407 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4408 {
4409 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4410 break;
4411 }
4412 wid = the_ins.reloc[m].wid;
4413 if (wid == 0)
4414 continue;
4415 the_ins.reloc[m].wid = 0;
4416 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4417
4418 fixP = fix_new_exp (frag_now,
4419 ((toP - frag_now->fr_literal)
4420 - the_ins.numo * 2 + the_ins.reloc[m].n),
4421 wid,
4422 &the_ins.reloc[m].exp,
4423 the_ins.reloc[m].pcrel,
4424 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4425 the_ins.reloc[m].pic_reloc));
4426 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4427 }
cac27205 4428 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4429 (relax_substateT) (the_ins.fragb[n].fragty),
4430 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4431 }
28a0da39
AM		 4432 gas_assert (the_ins.nfrag >= 1);
4433 n = the_ins.numo - the_ins.fragb[the_ins.nfrag - 1].fragoff;
252b5132
RH		 4434 shorts_this_frag = 0;
4435 if (n)
4436 {
055d1eb0 4437 toP = frag_more (n * 2);
252b5132
RH		 4438 while (n--)
4439 {
4440 md_number_to_chars (toP, (long) (*fromP), 2);
4441 toP += 2;
4442 fromP++;
4443 shorts_this_frag++;
4444 }
4445 }
4446 for (m = 0; m < the_ins.nrel; m++)
4447 {
4448 int wid;
4449
4450 wid = the_ins.reloc[m].wid;
4451 if (wid == 0)
4452 continue;
4453 the_ins.reloc[m].wid = 0;
4454 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4455
4456 fixP = fix_new_exp (frag_now,
4457 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4458 - shorts_this_frag * 2),
4459 wid,
4460 &the_ins.reloc[m].exp,
4461 the_ins.reloc[m].pcrel,
4462 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4463 the_ins.reloc[m].pic_reloc));
4464 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4465 }
4466}
4467
60fed2d3
NC		 4468/* Comparison function used by qsort to rank the opcode entries by name. */
4469
4470static int
4471m68k_compare_opcode (const void * v1, const void * v2)
4472{
4473 struct m68k_opcode * op1, * op2;
4474 int ret;
4475
03b13e59
NC		 4476 if (v1 == v2)
4477 return 0;
4478
60fed2d3
NC		 4479 op1 = *(struct m68k_opcode **) v1;
4480 op2 = *(struct m68k_opcode **) v2;
4481
4482 /* Compare the two names. If different, return the comparison.
4483 If the same, return the order they are in the opcode table. */
4484 ret = strcmp (op1->name, op2->name);
4485 if (ret)
4486 return ret;
4487 if (op1 < op2)
4488 return -1;
03b13e59 4489 return 1;
60fed2d3
NC		 4490}
4491
252b5132 4492void
60fed2d3 4493md_begin (void)
252b5132 4494{
60fed2d3
NC		 4495 const struct m68k_opcode *ins;
4496 struct m68k_incant *hack, *slak;
4497 const char *retval = 0; /* Empty string, or error msg text. */
4498 int i;
4499
4500 /* Set up hash tables with 68000 instructions.
4501 similar to what the vax assembler does. */
252b5132
RH		 4502 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4503 a copy of it at runtime, adding in the information we want but isn't
4504 there. I think it'd be better to have an awk script hack the table
4505 at compile time. Or even just xstr the table and use it as-is. But
4506 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4507 names. */
4508
252b5132
RH		 4509 if (flag_mri)
4510 {
4511 flag_reg_prefix_optional = 1;
4512 m68k_abspcadd = 1;
4513 if (! m68k_rel32_from_cmdline)
4514 m68k_rel32 = 0;
4515 }
4516
2b0f3761 4517 /* First sort the opcode table into alphabetical order to separate
60fed2d3
NC		 4518 the order that the assembler wants to see the opcodes from the
4519 order that the disassembler wants to see them. */
325801bd 4520 m68k_sorted_opcodes = XNEWVEC (const struct m68k_opcode *, m68k_numopcodes);
60fed2d3
NC		 4521
4522 for (i = m68k_numopcodes; i--;)
4523 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4524
4525 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4526 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4527
252b5132
RH		 4528 op_hash = hash_new ();
4529
4530 obstack_begin (&robyn, 4000);
4531 for (i = 0; i < m68k_numopcodes; i++)
4532 {
aff7ae12 4533 hack = slak = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4534 do
4535 {
60fed2d3
NC		 4536 ins = m68k_sorted_opcodes[i];
4537
afa2158f
NS		 4538 /* We must enter all insns into the table, because .arch and
4539 .cpu directives can change things. */
252b5132 4540 slak->m_operands = ins->args;
252b5132
RH		 4541 slak->m_arch = ins->arch;
4542 slak->m_opcode = ins->opcode;
3739860c 4543
afa2158f
NS		 4544 /* In most cases we can determine the number of opcode words
4545 by checking the second word of the mask. Unfortunately
4546 some instructions have 2 opcode words, but no fixed bits
4547 in the second word. A leading dot in the operands
4548 string also indicates 2 opcodes. */
4549 if (*slak->m_operands == '.')
4550 {
4551 slak->m_operands++;
4552 slak->m_codenum = 2;
4553 }
4554 else if (ins->match & 0xffffL)
4555 slak->m_codenum = 2;
4556 else
4557 slak->m_codenum = 1;
4558 slak->m_opnum = strlen (slak->m_operands) / 2;
3739860c 4559
252b5132 4560 if (i + 1 != m68k_numopcodes
60fed2d3 4561 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4562 {
aff7ae12 4563 slak->m_next = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4564 i++;
4565 }
4566 else
4567 slak->m_next = 0;
4568 slak = slak->m_next;
4569 }
4570 while (slak);
4571
4572 retval = hash_insert (op_hash, ins->name, (char *) hack);
4573 if (retval)
4574 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4575 }
4576
4577 for (i = 0; i < m68k_numaliases; i++)
4578 {
4579 const char *name = m68k_opcode_aliases[i].primary;
4580 const char *alias = m68k_opcode_aliases[i].alias;
5a49b8ac 4581 void *val = hash_find (op_hash, name);
60fed2d3 4582
252b5132
RH		 4583 if (!val)
4584 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4585 retval = hash_insert (op_hash, alias, val);
4586 if (retval)
4587 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4588 }
4589
4590 /* In MRI mode, all unsized branches are variable sized. Normally,
4591 they are word sized. */
4592 if (flag_mri)
4593 {
4594 static struct m68k_opcode_alias mri_aliases[] =
4595 {
4596 { "bhi", "jhi", },
4597 { "bls", "jls", },
4598 { "bcc", "jcc", },
4599 { "bcs", "jcs", },
4600 { "bne", "jne", },
4601 { "beq", "jeq", },
4602 { "bvc", "jvc", },
4603 { "bvs", "jvs", },
4604 { "bpl", "jpl", },
4605 { "bmi", "jmi", },
4606 { "bge", "jge", },
4607 { "blt", "jlt", },
4608 { "bgt", "jgt", },
4609 { "ble", "jle", },
4610 { "bra", "jra", },
4611 { "bsr", "jbsr", },
4612 };
4613
8fce3f5e
AM		 4614 for (i = 0;
4615 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4616 i++)
252b5132
RH		 4617 {
4618 const char *name = mri_aliases[i].primary;
4619 const char *alias = mri_aliases[i].alias;
5a49b8ac 4620 void *val = hash_find (op_hash, name);
60fed2d3 4621
252b5132
RH		 4622 if (!val)
4623 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4624 retval = hash_jam (op_hash, alias, val);
4625 if (retval)
4626 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4627 }
4628 }
4629
8fce3f5e 4630 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4631 {
4632 notend_table[i] = 0;
4633 alt_notend_table[i] = 0;
4634 }
60fed2d3 4635
252b5132
RH		 4636 notend_table[','] = 1;
4637 notend_table['{'] = 1;
4638 notend_table['}'] = 1;
4639 alt_notend_table['a'] = 1;
4640 alt_notend_table['A'] = 1;
4641 alt_notend_table['d'] = 1;
4642 alt_notend_table['D'] = 1;
4643 alt_notend_table['#'] = 1;
4644 alt_notend_table['&'] = 1;
4645 alt_notend_table['f'] = 1;
4646 alt_notend_table['F'] = 1;
4647#ifdef REGISTER_PREFIX
4648 alt_notend_table[REGISTER_PREFIX] = 1;
4649#endif
4650
4651 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4652 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4653 alt_notend_table['('] = 1;
4654
4655 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4656 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4657 alt_notend_table['@'] = 1;
4658
4659 /* We need to put digits in alt_notend_table to handle
60fed2d3 4660 bfextu %d0{24:1},%d0 */
252b5132
RH		 4661 alt_notend_table['0'] = 1;
4662 alt_notend_table['1'] = 1;
4663 alt_notend_table['2'] = 1;
4664 alt_notend_table['3'] = 1;
4665 alt_notend_table['4'] = 1;
4666 alt_notend_table['5'] = 1;
4667 alt_notend_table['6'] = 1;
4668 alt_notend_table['7'] = 1;
4669 alt_notend_table['8'] = 1;
4670 alt_notend_table['9'] = 1;
4671
4672#ifndef MIT_SYNTAX_ONLY
4673 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4674 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4675 {
4676 int n = 0;
60fed2d3 4677
252b5132
RH		 4678 while (mote_pseudo_table[n].poc_name)
4679 {
aff7ae12 4680 hack = XOBNEW (&robyn, struct m68k_incant);
252b5132
RH		 4681 hash_insert (op_hash,
4682 mote_pseudo_table[n].poc_name, (char *) hack);
4683 hack->m_operands = 0;
4684 hack->m_opnum = n;
4685 n++;
4686 }
4687 }
4688#endif
4689
4690 init_regtable ();
4691
252b5132
RH		 4692 record_alignment (text_section, 2);
4693 record_alignment (data_section, 2);
4694 record_alignment (bss_section, 2);
252b5132
RH		 4695}
4696
252b5132
RH		 4697\f
4698/* This is called when a label is defined. */
4699
4700void
31302357 4701m68k_frob_label (symbolS *sym)
252b5132
RH		 4702{
4703 struct label_line *n;
4704
add39d23 4705 n = XNEW (struct label_line);
252b5132
RH		 4706 n->next = labels;
4707 n->label = sym;
3b4dbbbf 4708 n->file = as_where (&n->line);
252b5132
RH		 4709 n->text = 0;
4710 labels = n;
4711 current_label = n;
07a53e5c 4712
07a53e5c 4713 dwarf2_emit_label (sym);
252b5132
RH		 4714}
4715
4716/* This is called when a value that is not an instruction is emitted. */
4717
4718void
31302357 4719m68k_flush_pending_output (void)
252b5132
RH		 4720{
4721 current_label = NULL;
4722}
4723
4724/* This is called at the end of the assembly, when the final value of
4725 the label is known. We warn if this is a text symbol aligned at an
4726 odd location. */
4727
4728void
31302357 4729m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4730{
4731 if (S_GET_SEGMENT (sym) == reg_section
4732 && (int) S_GET_VALUE (sym) < 0)
4733 {
4734 S_SET_SEGMENT (sym, absolute_section);
4735 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4736 }
4737 else if ((S_GET_VALUE (sym) & 1) != 0)
4738 {
4739 struct label_line *l;
4740
4741 for (l = labels; l != NULL; l = l->next)
4742 {
4743 if (l->label == sym)
4744 {
4745 if (l->text)
4746 as_warn_where (l->file, l->line,
4747 _("text label `%s' aligned to odd boundary"),
4748 S_GET_NAME (sym));
4749 break;
4750 }
4751 }
4752 }
4753}
4754\f
4755/* This is called if we go in or out of MRI mode because of the .mri
4756 pseudo-op. */
4757
4758void
31302357 4759m68k_mri_mode_change (int on)
252b5132
RH		 4760{
4761 if (on)
4762 {
4763 if (! flag_reg_prefix_optional)
4764 {
4765 flag_reg_prefix_optional = 1;
4766#ifdef REGISTER_PREFIX
4767 init_regtable ();
4768#endif
4769 }
4770 m68k_abspcadd = 1;
4771 if (! m68k_rel32_from_cmdline)
4772 m68k_rel32 = 0;
4773 }
4774 else
4775 {
4776 if (! reg_prefix_optional_seen)
4777 {
4778#ifdef REGISTER_PREFIX_OPTIONAL
4779 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4780#else
4781 flag_reg_prefix_optional = 0;
4782#endif
4783#ifdef REGISTER_PREFIX
4784 init_regtable ();
4785#endif
4786 }
4787 m68k_abspcadd = 0;
4788 if (! m68k_rel32_from_cmdline)
4789 m68k_rel32 = 1;
4790 }
4791}
4792
6d4af3c2 4793const char *
31302357 4794md_atof (int type, char *litP, int *sizeP)
252b5132 4795{
499ac353 4796 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH		 4797}
4798
4799void
31302357 4800md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4801{
4802 number_to_chars_bigendian (buf, val, n);
4803}
4804
94f592af 4805void
55cf6793 4806md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4807{
bbe8ef22 4808 offsetT val = *valP;
252b5132
RH		 4809 addressT upper_limit;
4810 offsetT lower_limit;
4811
4812 /* This is unnecessary but it convinces the native rs6000 compiler
4813 to generate the code we want. */
4814 char *buf = fixP->fx_frag->fr_literal;
4815 buf += fixP->fx_where;
36759679 4816 /* End ibm compiler workaround. */
252b5132 4817
bd17c2c3 4818 val = SEXT (val);
252b5132 4819
94f592af
NC		 4820 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4821 fixP->fx_done = 1;
4822
252b5132
RH		 4823 if (fixP->fx_addsy)
4824 {
4825 memset (buf, 0, fixP->fx_size);
36759679 4826 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4827
4828 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4829 && !S_IS_DEFINED (fixP->fx_addsy)
4830 && !S_IS_WEAK (fixP->fx_addsy))
4831 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4832
4833 switch (fixP->fx_r_type)
4834 {
4835 case BFD_RELOC_68K_TLS_GD32:
4836 case BFD_RELOC_68K_TLS_GD16:
4837 case BFD_RELOC_68K_TLS_GD8:
4838 case BFD_RELOC_68K_TLS_LDM32:
4839 case BFD_RELOC_68K_TLS_LDM16:
4840 case BFD_RELOC_68K_TLS_LDM8:
4841 case BFD_RELOC_68K_TLS_LDO32:
4842 case BFD_RELOC_68K_TLS_LDO16:
4843 case BFD_RELOC_68K_TLS_LDO8:
4844 case BFD_RELOC_68K_TLS_IE32:
4845 case BFD_RELOC_68K_TLS_IE16:
4846 case BFD_RELOC_68K_TLS_IE8:
4847 case BFD_RELOC_68K_TLS_LE32:
4848 case BFD_RELOC_68K_TLS_LE16:
4849 case BFD_RELOC_68K_TLS_LE8:
4850 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4851 break;
4852
4853 default:
4854 break;
4855 }
4856
252b5132
RH		 4857 return;
4858 }
252b5132 4859
252b5132
RH		 4860 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4861 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4862 return;
252b5132
RH		 4863
4864 switch (fixP->fx_size)
4865 {
94f592af
NC		 4866 /* The cast to offsetT below are necessary to make code
4867 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4868 case 1:
4869 *buf++ = val;
4870 upper_limit = 0x7f;
4871 lower_limit = - (offsetT) 0x80;
4872 break;
4873 case 2:
4874 *buf++ = (val >> 8);
4875 *buf++ = val;
4876 upper_limit = 0x7fff;
4877 lower_limit = - (offsetT) 0x8000;
4878 break;
4879 case 4:
4880 *buf++ = (val >> 24);
4881 *buf++ = (val >> 16);
4882 *buf++ = (val >> 8);
4883 *buf++ = val;
4884 upper_limit = 0x7fffffff;
36759679 4885 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4886 break;
4887 default:
4888 BAD_CASE (fixP->fx_size);
4889 }
4890
4891 /* Fix up a negative reloc. */
4892 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4893 {
4894 fixP->fx_addsy = fixP->fx_subsy;
4895 fixP->fx_subsy = NULL;
4896 fixP->fx_tcbit = 1;
4897 }
4898
4899 /* For non-pc-relative values, it's conceivable we might get something
4900 like "0xff" for a byte field. So extend the upper part of the range
4901 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4902 so that we can do any range checking at all. */
4903 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4904 upper_limit = upper_limit * 2 + 1;
4905
4906 if ((addressT) val > upper_limit
4907 && (val > 0 || val < lower_limit))
2b878742
NS		 4908 as_bad_where (fixP->fx_file, fixP->fx_line,
4909 _("value %ld out of range"), (long)val);
252b5132
RH		 4910
4911 /* A one byte PC-relative reloc means a short branch. We can't use
4912 a short branch with a value of 0 or -1, because those indicate
4913 different opcodes (branches with longer offsets). fixup_segment
4914 in write.c may have clobbered fx_pcrel, so we need to examine the
4915 reloc type. */
4916 if ((fixP->fx_pcrel
7be1c489 4917 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4918 && fixP->fx_size == 1
4919 && (fixP->fx_addsy == NULL
4920 || S_IS_DEFINED (fixP->fx_addsy))
4921 && (val == 0 || val == -1))
2b878742
NS		 4922 as_bad_where (fixP->fx_file, fixP->fx_line,
4923 _("invalid byte branch offset"));
252b5132
RH		 4924}
4925
252b5132
RH		 4926/* *fragP has been relaxed to its final size, and now needs to have
4927 the bytes inside it modified to conform to the new size There is UGLY
4928 MAGIC here. ..
4929 */
4930static void
31302357 4931md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4932{
4933 long disp;
2b878742 4934 fixS *fixP = NULL;
252b5132
RH		 4935
4936 /* Address in object code of the displacement. */
ed9e98c2 4937 int object_address = fragP->fr_fix + fragP->fr_address;
252b5132
RH		 4938
4939 /* Address in gas core of the place to store the displacement. */
4940 /* This convinces the native rs6000 compiler to generate the code we
92774660 4941 want. */
ed9e98c2 4942 char *buffer_address = fragP->fr_literal;
252b5132 4943 buffer_address += fragP->fr_fix;
36759679 4944 /* End ibm compiler workaround. */
252b5132
RH		 4945
4946 /* The displacement of the address, from current location. */
4947 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4948 disp = (disp + fragP->fr_offset) - object_address;
4949
252b5132
RH		 4950 switch (fragP->fr_subtype)
4951 {
151337e8
NC		 4952 case TAB (BRANCHBWL, BYTE):
4953 case TAB (BRABSJUNC, BYTE):
4954 case TAB (BRABSJCOND, BYTE):
4955 case TAB (BRANCHBW, BYTE):
cac27205 4956 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 4957 know (issbyte (disp));
4958 if (disp == 0)
b091f402
AM		 4959 as_bad_where (fragP->fr_file, fragP->fr_line,
4960 _("short branch with zero offset: use :w"));
151337e8 4961 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4962 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4963 fixP->fx_pcrel_adjust = -1;
252b5132 4964 break;
151337e8
NC		 4965 case TAB (BRANCHBWL, SHORT):
4966 case TAB (BRABSJUNC, SHORT):
4967 case TAB (BRABSJCOND, SHORT):
4968 case TAB (BRANCHBW, SHORT):
cac27205 4969 case TAB (BRANCHBWPL, SHORT):
252b5132 4970 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 4971 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4972 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4973 fragP->fr_fix += 2;
4974 break;
4975 case TAB (BRANCHBWL, LONG):
4976 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 4977 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4978 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 4979 fragP->fr_fix += 4;
252b5132 4980 break;
cac27205
NC		 4981 case TAB (BRANCHBWPL, LONG):
4982 /* Here we are converting an unconditional branch into a pair of
4983 conditional branches, in order to get the range. */
4984 fragP->fr_opcode[0] = 0x66; /* bne */
4985 fragP->fr_opcode[1] = 0xFF;
4986 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4987 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4988 fixP->fx_file = fragP->fr_file;
4989 fixP->fx_line = fragP->fr_line;
4990 fragP->fr_fix += 4; /* Skip first offset */
4991 buffer_address += 4;
4992 *buffer_address++ = 0x67; /* beq */
4993 *buffer_address++ = 0xff;
4994 fragP->fr_fix += 2; /* Skip second branch opcode */
4995 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4996 fragP->fr_offset, 1, RELAX_RELOC_PC32);
4997 fragP->fr_fix += 4;
4998 break;
151337e8
NC		 4999 case TAB (BRABSJUNC, LONG):
5000 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 5001 {
36759679 5002 if (flag_keep_pcrel)
2b878742
NS		 5003 as_bad_where (fragP->fr_file, fragP->fr_line,
5004 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 5005 fragP->fr_opcode[0] = 0x4E;
36759679 5006 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 5007 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5008 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5009 fragP->fr_fix += 4;
5010 }
5011 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5012 {
36759679 5013 if (flag_keep_pcrel)
2b878742
NS		 5014 as_bad_where (fragP->fr_file, fragP->fr_line,
5015 _("Conversion of PC relative branch to absolute jump"));
151337e8 5016 fragP->fr_opcode[0] = 0x4E;
36759679 5017 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 5018 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5019 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5020 fragP->fr_fix += 4;
252b5132
RH		 5021 }
5022 else
5023 {
151337e8
NC		 5024 /* This cannot happen, because jbsr and jbra are the only two
5025 unconditional branches. */
5026 abort ();
252b5132
RH		 5027 }
5028 break;
151337e8 5029 case TAB (BRABSJCOND, LONG):
36759679 5030 if (flag_keep_pcrel)
2b878742
NS		 5031 as_bad_where (fragP->fr_file, fragP->fr_line,
5032 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5033
36759679
NC		 5034 /* Only Bcc 68000 instructions can come here
5035 Change bcc into b!cc/jmp absl long. */
5036 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5037 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5038
5039 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5040 different frag, in which case referring to them is a no-no.
92774660 5041 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5042 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5043 *buffer_address++ = (char) 0xf9;
36759679 5044 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5045 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5046 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5047 fragP->fr_fix += 4;
5048 break;
5049 case TAB (FBRANCH, SHORT):
5050 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5051 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5052 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5053 fragP->fr_fix += 2;
5054 break;
5055 case TAB (FBRANCH, LONG):
36759679 5056 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5057 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5058 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5059 fragP->fr_fix += 4;
252b5132 5060 break;
151337e8
NC		 5061 case TAB (DBCCLBR, SHORT):
5062 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5063 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5064 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5065 fragP->fr_fix += 2;
5066 break;
5067 case TAB (DBCCLBR, LONG):
36759679
NC		 5068 /* Only DBcc instructions can come here.
5069 Change dbcc into dbcc/bral.
5070 JF: these used to be fr_opcode[2-7], but that's wrong. */
36759679 5071 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5072 *buffer_address++ = 0x04;
36759679 5073 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5074 *buffer_address++ = 0x06;
151337e8
NC		 5075 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5076 *buffer_address++ = (char) 0xff;
252b5132 5077
36759679 5078 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5079 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5080 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5081 fragP->fr_fix += 4;
252b5132 5082 break;
151337e8 5083 case TAB (DBCCABSJ, LONG):
36759679
NC		 5084 /* Only DBcc instructions can come here.
5085 Change dbcc into dbcc/jmp.
5086 JF: these used to be fr_opcode[2-7], but that's wrong. */
5087 if (flag_keep_pcrel)
2b878742
NS		 5088 as_bad_where (fragP->fr_file, fragP->fr_line,
5089 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5090
36759679 5091 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5092 *buffer_address++ = 0x04;
36759679 5093 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5094 *buffer_address++ = 0x06;
36759679 5095 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5096 *buffer_address++ = (char) 0xf9;
5097
36759679 5098 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5099 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5100 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5101 fragP->fr_fix += 4;
252b5132 5102 break;
151337e8 5103 case TAB (PCREL1632, SHORT):
252b5132
RH		 5104 fragP->fr_opcode[1] &= ~0x3F;
5105 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5106 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5107 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5108 fragP->fr_fix += 2;
252b5132 5109 break;
151337e8 5110 case TAB (PCREL1632, LONG):
252b5132
RH		 5111 /* Already set to mode 7.3; this indicates: PC indirect with
5112 suppressed index, 32-bit displacement. */
5113 *buffer_address++ = 0x01;
5114 *buffer_address++ = 0x70;
5115 fragP->fr_fix += 2;
151337e8 5116 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5117 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5118 fixP->fx_pcrel_adjust = 2;
5119 fragP->fr_fix += 4;
252b5132 5120 break;
252b5132 5121 case TAB (PCINDEX, BYTE):
9c2799c2 5122 gas_assert (fragP->fr_fix >= 2);
252b5132 5123 buffer_address[-2] &= ~1;
151337e8 5124 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5125 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5126 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5127 break;
5128 case TAB (PCINDEX, SHORT):
9c2799c2 5129 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5130 buffer_address[-2] |= 0x1;
5131 buffer_address[-1] = 0x20;
5132 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5133 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5134 fixP->fx_pcrel_adjust = 2;
151337e8 5135 fragP->fr_fix += 2;
252b5132
RH		 5136 break;
5137 case TAB (PCINDEX, LONG):
9c2799c2 5138 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5139 buffer_address[-2] |= 0x1;
5140 buffer_address[-1] = 0x30;
151337e8 5141 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5142 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5143 fixP->fx_pcrel_adjust = 2;
5144 fragP->fr_fix += 4;
5145 break;
5146 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5147 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5148 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5149 fragP->fr_fix += 2;
5150 break;
5151 case TAB (ABSTOPCREL, LONG):
36759679 5152 if (flag_keep_pcrel)
025987ea
NS		 5153 as_bad_where (fragP->fr_file, fragP->fr_line,
5154 _("Conversion of PC relative displacement to absolute"));
151337e8 5155 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5156 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5157 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5158 abort ();
5159 fragP->fr_opcode[1] &= ~0x3F;
5160 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5161 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5162 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5163 fragP->fr_fix += 4;
252b5132 5164 break;
252b5132 5165 }
2b878742
NS		 5166 if (fixP)
5167 {
5168 fixP->fx_file = fragP->fr_file;
5169 fixP->fx_line = fragP->fr_line;
5170 }
252b5132
RH		 5171}
5172
252b5132 5173void
31302357
AS		 5174md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5175 segT sec ATTRIBUTE_UNUSED,
5176 fragS *fragP)
252b5132
RH		 5177{
5178 md_convert_frag_1 (fragP);
5179}
252b5132
RH		 5180
5181/* Force truly undefined symbols to their maximum size, and generally set up
5182 the frag list to be relaxed
5183 */
5184int
31302357 5185md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5186{
151337e8 5187 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5188 switch (fragP->fr_subtype)
5189 {
151337e8 5190 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5191 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5192 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5193 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5194 {
151337e8
NC		 5195 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5196 && relaxable_symbol (fragP->fr_symbol))
252b5132 5197 {
151337e8
NC		 5198 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5199 }
5200 else if (flag_short_refs)
5201 {
5202 /* Symbol is undefined and we want short ref. */
5203 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5204 }
5205 else
5206 {
151337e8
NC		 5207 /* Symbol is still undefined. Make it LONG. */
5208 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5209 }
5210 break;
151337e8 5211 }
252b5132 5212
151337e8 5213 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5214 {
151337e8
NC		 5215 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5216 && relaxable_symbol (fragP->fr_symbol))
252b5132 5217 {
151337e8 5218 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5219 }
5220 else
5221 {
151337e8
NC		 5222 /* Symbol is undefined and we don't have long branches. */
5223 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5224 }
5225 break;
151337e8 5226 }
252b5132 5227
151337e8 5228 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5229 case TAB (DBCCLBR, SZ_UNDEF):
5230 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5231 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5232 {
8ec6253e
NC		 5233 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5234 && relaxable_symbol (fragP->fr_symbol))
151337e8 5235 || flag_short_refs)
252b5132 5236 {
151337e8 5237 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5238 }
5239 else
5240 {
151337e8 5241 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5242 }
5243 break;
151337e8 5244 }
81d4177b 5245
252b5132
RH		 5246 case TAB (PCINDEX, SZ_UNDEF):
5247 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5248 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5249 {
5250 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5251 }
5252 else
5253 {
5254 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5255 }
5256 break;
5257
151337e8
NC		 5258 case TAB (ABSTOPCREL, SZ_UNDEF):
5259 {
5260 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5261 && relaxable_symbol (fragP->fr_symbol)))
5262 {
5263 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5264 }
5265 else
5266 {
5267 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5268 }
5269 break;
5270 }
5271
252b5132
RH		 5272 default:
5273 break;
5274 }
5275
151337e8 5276 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5277 switch (fragP->fr_subtype)
5278 {
151337e8
NC		 5279 case TAB (BRANCHBWL, BYTE):
5280 case TAB (BRABSJUNC, BYTE):
5281 case TAB (BRABSJCOND, BYTE):
5282 case TAB (BRANCHBW, BYTE):
252b5132 5283 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5284 case we force word mode. If the symbol is at the start of a
5285 frag, and it is the next frag with any data in it (usually
5286 this is just the next frag, but assembler listings may
5287 introduce empty frags), we must use word mode. */
5288 if (fragP->fr_symbol)
252b5132 5289 {
ac62c346 5290 fragS *sym_frag;
252b5132 5291
ac62c346
AM		 5292 sym_frag = symbol_get_frag (fragP->fr_symbol);
5293 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5294 {
ac62c346
AM		 5295 fragS *l;
5296
23b7f870 5297 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5298 if (l->fr_fix != 0)
5299 break;
5300 if (l == sym_frag)
5301 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5302 }
5303 }
5304 break;
5305 default:
5306 break;
5307 }
ac62c346 5308 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5309}
5310
252b5132 5311#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5312int md_short_jump_size = 4;
5313int md_long_jump_size = 6;
252b5132
RH		 5314
5315void
31302357
AS		 5316md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5317 fragS *frag ATTRIBUTE_UNUSED,
5318 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5319{
5320 valueT offset;
5321
5322 offset = to_addr - (from_addr + 2);
5323
5324 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5325 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5326}
5327
5328void
31302357
AS		 5329md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5330 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5331{
5332 valueT offset;
5333
6b6e92f4 5334 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5335 {
36759679 5336 if (flag_keep_pcrel)
6b6e92f4 5337 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5338 offset = to_addr - S_GET_VALUE (to_symbol);
5339 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5340 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5341 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5342 0, NO_RELOC);
5343 }
5344 else
5345 {
5346 offset = to_addr - (from_addr + 2);
5347 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5348 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5349 }
5350}
5351
5352#endif
5353
33eaf5de 5354/* Different values of OK tell what it's OK to return. Things that
252b5132
RH		 5355 aren't OK are an error (what a shock, no?)
5356
5357 0: Everything is OK
3e602632
NC		 5358 10: Absolute 1:8 only
5359 20: Absolute 0:7 only
5360 30: absolute 0:15 only
5361 40: Absolute 0:31 only
5362 50: absolute 0:127 only
252b5132 5363 55: absolute -64:63 only
3e602632 5364 60: absolute -128:127 only
afa2158f 5365 65: absolute 0:511 only
3e602632
NC		 5366 70: absolute 0:4095 only
5367 80: absolute -1, 1:7 only
5368 90: No bignums. */
252b5132
RH		 5369
5370static int
31302357 5371get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5372{
5373 if (exp->exp.X_op == O_absent)
5374 {
36759679 5375 /* Do the same thing the VAX asm does. */
252b5132
RH		 5376 op (exp) = O_constant;
5377 adds (exp) = 0;
5378 subs (exp) = 0;
5379 offs (exp) = 0;
5380 if (ok == 10)
5381 {
5382 as_warn (_("expression out of range: defaulting to 1"));
5383 offs (exp) = 1;
5384 }
5385 }
5386 else if (exp->exp.X_op == O_constant)
5387 {
5388 switch (ok)
5389 {
5390 case 10:
bd17c2c3 5391 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5392 {
5393 as_warn (_("expression out of range: defaulting to 1"));
5394 offs (exp) = 1;
5395 }
5396 break;
5397 case 20:
bd17c2c3 5398 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5399 goto outrange;
5400 break;
5401 case 30:
bd17c2c3 5402 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5403 goto outrange;
5404 break;
5405 case 40:
bd17c2c3 5406 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5407 goto outrange;
5408 break;
5409 case 50:
bd17c2c3 5410 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5411 goto outrange;
5412 break;
5413 case 55:
bd17c2c3 5414 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5415 goto outrange;
5416 break;
5417 case 60:
bd17c2c3 5418 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5419 goto outrange;
afa2158f
NS		 5420 break;
5421 case 65:
5422 if ((valueT) TRUNC (offs (exp)) > 511)
5423 goto outrange;
252b5132
RH		 5424 break;
5425 case 70:
bd17c2c3 5426 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5427 {
5428 outrange:
5429 as_warn (_("expression out of range: defaulting to 0"));
5430 offs (exp) = 0;
5431 }
5432 break;
3e602632 5433 case 80:
bd17c2c3
AM		 5434 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5435 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5436 {
5437 as_warn (_("expression out of range: defaulting to 1"));
5438 offs (exp) = 1;
5439 }
5440 break;
252b5132
RH		 5441 default:
5442 break;
5443 }
5444 }
5445 else if (exp->exp.X_op == O_big)
5446 {
36759679 5447 if (offs (exp) <= 0 /* flonum. */
3e602632 5448 && (ok == 90 /* no bignums */
36759679 5449 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5450 /* If we have a flonum zero, a zero integer should
5451 do as well (e.g., in moveq). */
5452 && generic_floating_point_number.exponent == 0
5453 && generic_floating_point_number.low[0] == 0)))
5454 {
36759679 5455 /* HACK! Turn it into a long. */
252b5132
RH		 5456 LITTLENUM_TYPE words[6];
5457
36759679 5458 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5459 op (exp) = O_constant;
5460 adds (exp) = 0;
5461 subs (exp) = 0;
5462 offs (exp) = words[1] | (words[0] << 16);
5463 }
5464 else if (ok != 0)
5465 {
5466 op (exp) = O_constant;
5467 adds (exp) = 0;
5468 subs (exp) = 0;
5469 offs (exp) = (ok == 10) ? 1 : 0;
5470 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5471 (long) offs (exp));
252b5132
RH		 5472 }
5473 }
5474 else
5475 {
3e602632 5476 if (ok >= 10 && ok <= 80)
252b5132
RH		 5477 {
5478 op (exp) = O_constant;
5479 adds (exp) = 0;
5480 subs (exp) = 0;
5481 offs (exp) = (ok == 10) ? 1 : 0;
5482 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5483 (long) offs (exp));
252b5132
RH		 5484 }
5485 }
5486
5487 if (exp->size != SIZE_UNSPEC)
5488 {
5489 switch (exp->size)
5490 {
5491 case SIZE_UNSPEC:
5492 case SIZE_LONG:
5493 break;
5494 case SIZE_BYTE:
5495 if (!isbyte (offs (exp)))
5496 as_warn (_("expression doesn't fit in BYTE"));
5497 break;
5498 case SIZE_WORD:
5499 if (!isword (offs (exp)))
5500 as_warn (_("expression doesn't fit in WORD"));
5501 break;
5502 }
5503 }
5504
5505 return offs (exp);
5506}
5507
5508/* These are the back-ends for the various machine dependent pseudo-ops. */
5509
5510static void
31302357 5511s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5512{
5513 subseg_set (data_section, 1);
5514 demand_empty_rest_of_line ();
5515}
5516
5517static void
31302357 5518s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5519{
5520 subseg_set (data_section, 2);
5521 demand_empty_rest_of_line ();
5522}
5523
5524static void
31302357 5525s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5526{
5527 /* We don't support putting frags in the BSS segment, we fake it
5528 by marking in_bss, then looking at s_skip for clues. */
5529
5530 subseg_set (bss_section, 0);
5531 demand_empty_rest_of_line ();
5532}
5533
5534static void
31302357 5535s_even (int ignore ATTRIBUTE_UNUSED)
252b5132 5536{
ed9e98c2
AM		 5537 int temp;
5538 long temp_fill;
252b5132
RH		 5539
5540 temp = 1; /* JF should be 2? */
5541 temp_fill = get_absolute_expression ();
92774660 5542 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5543 frag_align (temp, (int) temp_fill, 0);
5544 demand_empty_rest_of_line ();
5545 record_alignment (now_seg, temp);
5546}
5547
5548static void
31302357 5549s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5550{
5551 demand_empty_rest_of_line ();
5552}
5553\f
5554/* Pseudo-ops handled for MRI compatibility. */
5555
5556/* This function returns non-zero if the argument is a conditional
5557 pseudo-op. This is called when checking whether a pending
5558 alignment is needed. */
5559
5560int
31302357 5561m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5562{
5563 return (pop->poc_handler == s_mri_if
5564 || pop->poc_handler == s_mri_else);
5565}
5566
5567/* Handle an MRI style chip specification. */
5568
5569static void
31302357 5570mri_chip (void)
252b5132
RH		 5571{
5572 char *s;
5573 char c;
5574 int i;
5575
5576 s = input_line_pointer;
d02603dc 5577 /* We can't use get_symbol_name since the processor names are not proper
252b5132
RH		 5578 symbols. */
5579 while (is_part_of_name (c = *input_line_pointer++))
5580 ;
5581 *--input_line_pointer = 0;
266abb8f
NS		 5582 for (i = 0; m68k_cpus[i].name; i++)
5583 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5584 break;
266abb8f 5585 if (!m68k_cpus[i].name)
252b5132
RH		 5586 {
5587 as_bad (_("%s: unrecognized processor name"), s);
5588 *input_line_pointer = c;
5589 ignore_rest_of_line ();
5590 return;
5591 }
5592 *input_line_pointer = c;
5593
5594 if (*input_line_pointer == '/')
5595 current_architecture = 0;
5596 else
5597 current_architecture &= m68881 | m68851;
266abb8f 5598 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5599 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5600
5601 while (*input_line_pointer == '/')
5602 {
5603 ++input_line_pointer;
5604 s = input_line_pointer;
d02603dc 5605 /* We can't use get_symbol_name since the processor names are not
252b5132
RH		 5606 proper symbols. */
5607 while (is_part_of_name (c = *input_line_pointer++))
5608 ;
5609 *--input_line_pointer = 0;
5610 if (strcmp (s, "68881") == 0)
5611 current_architecture |= m68881;
5612 else if (strcmp (s, "68851") == 0)
5613 current_architecture |= m68851;
5614 *input_line_pointer = c;
5615 }
252b5132
RH		 5616}
5617
5618/* The MRI CHIP pseudo-op. */
5619
5620static void
31302357 5621s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5622{
5623 char *stop = NULL;
5624 char stopc;
5625
5626 if (flag_mri)
5627 stop = mri_comment_field (&stopc);
5628 mri_chip ();
5629 if (flag_mri)
5630 mri_comment_end (stop, stopc);
5631 demand_empty_rest_of_line ();
5632}
5633
5634/* The MRI FOPT pseudo-op. */
5635
5636static void
31302357 5637s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5638{
5639 SKIP_WHITESPACE ();
5640
5641 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5642 {
5643 int temp;
5644
5645 input_line_pointer += 3;
5646 temp = get_absolute_expression ();
5647 if (temp < 0 || temp > 7)
5648 as_bad (_("bad coprocessor id"));
5649 else
5650 m68k_float_copnum = COP0 + temp;
5651 }
5652 else
5653 {
5654 as_bad (_("unrecognized fopt option"));
5655 ignore_rest_of_line ();
5656 return;
5657 }
5658
5659 demand_empty_rest_of_line ();
5660}
5661
5662/* The structure used to handle the MRI OPT pseudo-op. */
5663
5664struct opt_action
5665{
5666 /* The name of the option. */
5667 const char *name;
5668
5669 /* If this is not NULL, just call this function. The first argument
5670 is the ARG field of this structure, the second argument is
5671 whether the option was negated. */
31302357 5672 void (*pfn) (int arg, int on);
252b5132
RH		 5673
5674 /* If this is not NULL, and the PFN field is NULL, set the variable
5675 this points to. Set it to the ARG field if the option was not
5676 negated, and the NOTARG field otherwise. */
5677 int *pvar;
5678
5679 /* The value to pass to PFN or to assign to *PVAR. */
5680 int arg;
5681
5682 /* The value to assign to *PVAR if the option is negated. If PFN is
5683 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5684 the option may not be negated. */
5685 int notarg;
5686};
5687
5688/* The table used to handle the MRI OPT pseudo-op. */
5689
31302357
AS		 5690static void skip_to_comma (int, int);
5691static void opt_nest (int, int);
5692static void opt_chip (int, int);
5693static void opt_list (int, int);
5694static void opt_list_symbols (int, int);
252b5132
RH		 5695
5696static const struct opt_action opt_table[] =
5697{
5698 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5699
5700 /* We do relaxing, so there is little use for these options. */
5701 { "b", 0, 0, 0, 0 },
5702 { "brs", 0, 0, 0, 0 },
5703 { "brb", 0, 0, 0, 0 },
5704 { "brl", 0, 0, 0, 0 },
5705 { "brw", 0, 0, 0, 0 },
5706
5707 { "c", 0, 0, 0, 0 },
5708 { "cex", 0, 0, 0, 0 },
5709 { "case", 0, &symbols_case_sensitive, 1, 0 },
5710 { "cl", 0, 0, 0, 0 },
5711 { "cre", 0, 0, 0, 0 },
5712 { "d", 0, &flag_keep_locals, 1, 0 },
5713 { "e", 0, 0, 0, 0 },
5714 { "f", 0, &flag_short_refs, 1, 0 },
5715 { "frs", 0, &flag_short_refs, 1, 0 },
5716 { "frl", 0, &flag_short_refs, 0, 1 },
5717 { "g", 0, 0, 0, 0 },
5718 { "i", 0, 0, 0, 0 },
5719 { "m", 0, 0, 0, 0 },
5720 { "mex", 0, 0, 0, 0 },
5721 { "mc", 0, 0, 0, 0 },
5722 { "md", 0, 0, 0, 0 },
5723 { "nest", opt_nest, 0, 0, 0 },
5724 { "next", skip_to_comma, 0, 0, 0 },
5725 { "o", 0, 0, 0, 0 },
5726 { "old", 0, 0, 0, 0 },
5727 { "op", skip_to_comma, 0, 0, 0 },
5728 { "pco", 0, 0, 0, 0 },
5729 { "p", opt_chip, 0, 0, 0 },
5730 { "pcr", 0, 0, 0, 0 },
5731 { "pcs", 0, 0, 0, 0 },
5732 { "r", 0, 0, 0, 0 },
5733 { "quick", 0, &m68k_quick, 1, 0 },
5734 { "rel32", 0, &m68k_rel32, 1, 0 },
5735 { "s", opt_list, 0, 0, 0 },
5736 { "t", opt_list_symbols, 0, 0, 0 },
5737 { "w", 0, &flag_no_warnings, 0, 1 },
5738 { "x", 0, 0, 0, 0 }
5739};
5740
8fce3f5e 5741#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5742
5743/* The MRI OPT pseudo-op. */
5744
5745static void
31302357 5746s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5747{
5748 do
5749 {
5750 int t;
5751 char *s;
5752 char c;
5753 int i;
5754 const struct opt_action *o;
5755
5756 SKIP_WHITESPACE ();
5757
5758 t = 1;
5759 if (*input_line_pointer == '-')
5760 {
5761 ++input_line_pointer;
5762 t = 0;
5763 }
5764 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5765 {
5766 input_line_pointer += 2;
5767 t = 0;
5768 }
5769
d02603dc 5770 c = get_symbol_name (&s);
252b5132
RH		 5771
5772 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5773 {
5774 if (strcasecmp (s, o->name) == 0)
5775 {
5776 if (o->pfn)
5777 {
5778 /* Restore input_line_pointer now in case the option
5779 takes arguments. */
d02603dc 5780 (void) restore_line_pointer (c);
252b5132
RH		 5781 (*o->pfn) (o->arg, t);
5782 }
5783 else if (o->pvar != NULL)
5784 {
5785 if (! t && o->arg == o->notarg)
5786 as_bad (_("option `%s' may not be negated"), s);
d02603dc 5787 restore_line_pointer (c);
252b5132
RH		 5788 *o->pvar = t ? o->arg : o->notarg;
5789 }
5790 else
5791 *input_line_pointer = c;
5792 break;
5793 }
5794 }
5795 if (i >= OPTCOUNT)
5796 {
5797 as_bad (_("option `%s' not recognized"), s);
d02603dc 5798 restore_line_pointer (c);
252b5132
RH		 5799 }
5800 }
5801 while (*input_line_pointer++ == ',');
5802
5803 /* Move back to terminating character. */
5804 --input_line_pointer;
5805 demand_empty_rest_of_line ();
5806}
5807
5808/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5809 not support and which take arguments. */
252b5132
RH		 5810
5811static void
31302357 5812skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5813{
5814 while (*input_line_pointer != ','
5815 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5816 ++input_line_pointer;
5817}
5818
5819/* Handle the OPT NEST=depth option. */
5820
5821static void
31302357 5822opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5823{
5824 if (*input_line_pointer != '=')
5825 {
5826 as_bad (_("bad format of OPT NEST=depth"));
5827 return;
5828 }
5829
5830 ++input_line_pointer;
5831 max_macro_nest = get_absolute_expression ();
5832}
5833
5834/* Handle the OPT P=chip option. */
5835
5836static void
31302357 5837opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5838{
5839 if (*input_line_pointer != '=')
5840 {
5841 /* This is just OPT P, which we do not support. */
5842 return;
5843 }
5844
5845 ++input_line_pointer;
5846 mri_chip ();
5847}
5848
5849/* Handle the OPT S option. */
5850
5851static void
31302357 5852opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5853{
5854 listing_list (on);
5855}
5856
5857/* Handle the OPT T option. */
5858
5859static void
31302357 5860opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5861{
5862 if (on)
5863 listing |= LISTING_SYMBOLS;
5864 else
8a104df9 5865 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5866}
5867
5868/* Handle the MRI REG pseudo-op. */
5869
5870static void
31302357 5871s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5872{
5873 char *s;
5874 int c;
5875 struct m68k_op rop;
5876 int mask;
5877 char *stop = NULL;
5878 char stopc;
5879
5880 if (line_label == NULL)
5881 {
5882 as_bad (_("missing label"));
5883 ignore_rest_of_line ();
5884 return;
5885 }
5886
5887 if (flag_mri)
5888 stop = mri_comment_field (&stopc);
5889
5890 SKIP_WHITESPACE ();
5891
5892 s = input_line_pointer;
3882b010 5893 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5894#ifdef REGISTER_PREFIX
5895 || *input_line_pointer == REGISTER_PREFIX
5896#endif
5897 || *input_line_pointer == '/'
5898 || *input_line_pointer == '-')
5899 ++input_line_pointer;
5900 c = *input_line_pointer;
5901 *input_line_pointer = '\0';
5902
5903 if (m68k_ip_op (s, &rop) != 0)
5904 {
5905 if (rop.error == NULL)
5906 as_bad (_("bad register list"));
5907 else
5908 as_bad (_("bad register list: %s"), rop.error);
5909 *input_line_pointer = c;
5910 ignore_rest_of_line ();
5911 return;
5912 }
5913
5914 *input_line_pointer = c;
5915
5916 if (rop.mode == REGLST)
5917 mask = rop.mask;
5918 else if (rop.mode == DREG)
5919 mask = 1 << (rop.reg - DATA0);
5920 else if (rop.mode == AREG)
5921 mask = 1 << (rop.reg - ADDR0 + 8);
5922 else if (rop.mode == FPREG)
5923 mask = 1 << (rop.reg - FP0 + 16);
5924 else if (rop.mode == CONTROL
5925 && rop.reg == FPI)
5926 mask = 1 << 24;
5927 else if (rop.mode == CONTROL
5928 && rop.reg == FPS)
5929 mask = 1 << 25;
5930 else if (rop.mode == CONTROL
5931 && rop.reg == FPC)
5932 mask = 1 << 26;
5933 else
5934 {
5935 as_bad (_("bad register list"));
5936 ignore_rest_of_line ();
5937 return;
5938 }
5939
5940 S_SET_SEGMENT (line_label, reg_section);
5941 S_SET_VALUE (line_label, ~mask);
49309057 5942 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5943
5944 if (flag_mri)
5945 mri_comment_end (stop, stopc);
5946
5947 demand_empty_rest_of_line ();
5948}
5949
5950/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5951
5952struct save_opts
5953{
5954 struct save_opts *next;
5955 int abspcadd;
5956 int symbols_case_sensitive;
5957 int keep_locals;
5958 int short_refs;
5959 int architecture;
2da12c60 5960 const enum m68k_register *control_regs;
252b5132
RH		 5961 int quick;
5962 int rel32;
5963 int listing;
5964 int no_warnings;
5965 /* FIXME: We don't save OPT S. */
5966};
5967
5968/* This variable holds the stack of saved options. */
5969
5970static struct save_opts *save_stack;
5971
5972/* The MRI SAVE pseudo-op. */
5973
5974static void
31302357 5975s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5976{
5977 struct save_opts *s;
5978
add39d23 5979 s = XNEW (struct save_opts);
252b5132
RH		 5980 s->abspcadd = m68k_abspcadd;
5981 s->symbols_case_sensitive = symbols_case_sensitive;
5982 s->keep_locals = flag_keep_locals;
5983 s->short_refs = flag_short_refs;
5984 s->architecture = current_architecture;
2da12c60 5985 s->control_regs = control_regs;
252b5132
RH		 5986 s->quick = m68k_quick;
5987 s->rel32 = m68k_rel32;
5988 s->listing = listing;
5989 s->no_warnings = flag_no_warnings;
5990
5991 s->next = save_stack;
5992 save_stack = s;
5993
5994 demand_empty_rest_of_line ();
5995}
5996
5997/* The MRI RESTORE pseudo-op. */
5998
5999static void
31302357 6000s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6001{
6002 struct save_opts *s;
6003
6004 if (save_stack == NULL)
6005 {
6006 as_bad (_("restore without save"));
6007 ignore_rest_of_line ();
6008 return;
6009 }
6010
6011 s = save_stack;
6012 save_stack = s->next;
6013
6014 m68k_abspcadd = s->abspcadd;
6015 symbols_case_sensitive = s->symbols_case_sensitive;
6016 flag_keep_locals = s->keep_locals;
6017 flag_short_refs = s->short_refs;
6018 current_architecture = s->architecture;
2da12c60 6019 control_regs = s->control_regs;
252b5132
RH		 6020 m68k_quick = s->quick;
6021 m68k_rel32 = s->rel32;
6022 listing = s->listing;
6023 flag_no_warnings = s->no_warnings;
6024
6025 free (s);
6026
6027 demand_empty_rest_of_line ();
6028}
6029
6030/* Types of MRI structured control directives. */
6031
6032enum mri_control_type
6033{
6034 mri_for,
6035 mri_if,
6036 mri_repeat,
6037 mri_while
6038};
6039
6040/* This structure is used to stack the MRI structured control
6041 directives. */
6042
6043struct mri_control_info
6044{
6045 /* The directive within which this one is enclosed. */
6046 struct mri_control_info *outer;
6047
6048 /* The type of directive. */
6049 enum mri_control_type type;
6050
6051 /* Whether an ELSE has been in an IF. */
6052 int else_seen;
6053
6054 /* The add or sub statement at the end of a FOR. */
6055 char *incr;
6056
6057 /* The label of the top of a FOR or REPEAT loop. */
6058 char *top;
6059
6060 /* The label to jump to for the next iteration, or the else
6061 expression of a conditional. */
6062 char *next;
6063
6064 /* The label to jump to to break out of the loop, or the label past
6065 the end of a conditional. */
6066 char *bottom;
6067};
6068
6069/* The stack of MRI structured control directives. */
6070
6071static struct mri_control_info *mri_control_stack;
6072
6073/* The current MRI structured control directive index number, used to
6074 generate label names. */
6075
6076static int mri_control_index;
6077
252b5132
RH		 6078/* Assemble an instruction for an MRI structured control directive. */
6079
6080static void
31302357 6081mri_assemble (char *str)
252b5132
RH		 6082{
6083 char *s;
6084
6085 /* md_assemble expects the opcode to be in lower case. */
6086 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6087 *s = TOLOWER (*s);
252b5132
RH		 6088
6089 md_assemble (str);
6090}
6091
6092/* Generate a new MRI label structured control directive label name. */
6093
6094static char *
31302357 6095mri_control_label (void)
252b5132
RH		 6096{
6097 char *n;
6098
add39d23 6099 n = XNEWVEC (char, 20);
252b5132
RH		 6100 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6101 ++mri_control_index;
6102 return n;
6103}
6104
6105/* Create a new MRI structured control directive. */
6106
6107static struct mri_control_info *
31302357 6108push_mri_control (enum mri_control_type type)
252b5132
RH		 6109{
6110 struct mri_control_info *n;
6111
add39d23 6112 n = XNEW (struct mri_control_info);
252b5132
RH		 6113
6114 n->type = type;
6115 n->else_seen = 0;
6116 if (type == mri_if || type == mri_while)
6117 n->top = NULL;
6118 else
6119 n->top = mri_control_label ();
6120 n->next = mri_control_label ();
6121 n->bottom = mri_control_label ();
6122
6123 n->outer = mri_control_stack;
6124 mri_control_stack = n;
6125
6126 return n;
6127}
6128
6129/* Pop off the stack of MRI structured control directives. */
6130
6131static void
31302357 6132pop_mri_control (void)
252b5132
RH		 6133{
6134 struct mri_control_info *n;
6135
6136 n = mri_control_stack;
6137 mri_control_stack = n->outer;
6138 if (n->top != NULL)
6139 free (n->top);
6140 free (n->next);
6141 free (n->bottom);
6142 free (n);
6143}
6144
6145/* Recognize a condition code in an MRI structured control expression. */
6146
6147static int
31302357 6148parse_mri_condition (int *pcc)
252b5132
RH		 6149{
6150 char c1, c2;
6151
6152 know (*input_line_pointer == '<');
6153
6154 ++input_line_pointer;
6155 c1 = *input_line_pointer++;
6156 c2 = *input_line_pointer++;
6157
6158 if (*input_line_pointer != '>')
6159 {
6160 as_bad (_("syntax error in structured control directive"));
6161 return 0;
6162 }
6163
6164 ++input_line_pointer;
6165 SKIP_WHITESPACE ();
6166
3882b010
L		 6167 c1 = TOLOWER (c1);
6168 c2 = TOLOWER (c2);
252b5132
RH		 6169
6170 *pcc = (c1 << 8) | c2;
6171
6172 return 1;
6173}
6174
6175/* Parse a single operand in an MRI structured control expression. */
6176
6177static int
31302357
AS		 6178parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6179 char **rightstart, char **rightstop)
252b5132
RH		 6180{
6181 char *s;
6182
6183 SKIP_WHITESPACE ();
6184
6185 *pcc = -1;
6186 *leftstart = NULL;
6187 *leftstop = NULL;
6188 *rightstart = NULL;
6189 *rightstop = NULL;
6190
6191 if (*input_line_pointer == '<')
6192 {
6193 /* It's just a condition code. */
6194 return parse_mri_condition (pcc);
6195 }
6196
6197 /* Look ahead for the condition code. */
6198 for (s = input_line_pointer; *s != '\0'; ++s)
6199 {
6200 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6201 break;
6202 }
6203 if (*s == '\0')
6204 {
6205 as_bad (_("missing condition code in structured control directive"));
6206 return 0;
6207 }
6208
6209 *leftstart = input_line_pointer;
6210 *leftstop = s;
6211 if (*leftstop > *leftstart
6212 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6213 --*leftstop;
6214
6215 input_line_pointer = s;
6216 if (! parse_mri_condition (pcc))
6217 return 0;
6218
6219 /* Look ahead for AND or OR or end of line. */
6220 for (s = input_line_pointer; *s != '\0'; ++s)
6221 {
e1f44d10
NC		 6222 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6223 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6224 ^^^ ^^ */
8a104df9
KH		 6225 if ((s == input_line_pointer
6226 || *(s-1) == ' '
6227 || *(s-1) == '\t')
6228 && ((strncasecmp (s, "AND", 3) == 0
6229 && (s[3] == '.' || ! is_part_of_name (s[3])))
6230 || (strncasecmp (s, "OR", 2) == 0
6231 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6232 break;
252b5132
RH		 6233 }
6234
6235 *rightstart = input_line_pointer;
6236 *rightstop = s;
6237 if (*rightstop > *rightstart
6238 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6239 --*rightstop;
6240
6241 input_line_pointer = s;
6242
6243 return 1;
6244}
6245
6246#define MCC(b1, b2) (((b1) << 8) | (b2))
6247
6248/* Swap the sense of a condition. This changes the condition so that
6249 it generates the same result when the operands are swapped. */
6250
6251static int
31302357 6252swap_mri_condition (int cc)
252b5132
RH		 6253{
6254 switch (cc)
6255 {
6256 case MCC ('h', 'i'): return MCC ('c', 's');
6257 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6258 /* <HS> is an alias for <CC>. */
e1f44d10 6259 case MCC ('h', 's'):
252b5132 6260 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6261 /* <LO> is an alias for <CS>. */
e1f44d10 6262 case MCC ('l', 'o'):
252b5132
RH		 6263 case MCC ('c', 's'): return MCC ('h', 'i');
6264 case MCC ('p', 'l'): return MCC ('m', 'i');
6265 case MCC ('m', 'i'): return MCC ('p', 'l');
6266 case MCC ('g', 'e'): return MCC ('l', 'e');
6267 case MCC ('l', 't'): return MCC ('g', 't');
6268 case MCC ('g', 't'): return MCC ('l', 't');
6269 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6270 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6271 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6272 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6273 case MCC ('v', 'c'):
6274 case MCC ('v', 's'):
6275 default :
6276 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6277 (char) (cc >> 8), (char) (cc));
6278 break;
252b5132
RH		 6279 }
6280 return cc;
6281}
6282
6283/* Reverse the sense of a condition. */
6284
6285static int
31302357 6286reverse_mri_condition (int cc)
252b5132
RH		 6287{
6288 switch (cc)
6289 {
6290 case MCC ('h', 'i'): return MCC ('l', 's');
6291 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6292 /* <HS> is an alias for <CC> */
6293 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6294 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6295 /* <LO> is an alias for <CS> */
6296 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6297 case MCC ('c', 's'): return MCC ('c', 'c');
6298 case MCC ('n', 'e'): return MCC ('e', 'q');
6299 case MCC ('e', 'q'): return MCC ('n', 'e');
6300 case MCC ('v', 'c'): return MCC ('v', 's');
6301 case MCC ('v', 's'): return MCC ('v', 'c');
6302 case MCC ('p', 'l'): return MCC ('m', 'i');
6303 case MCC ('m', 'i'): return MCC ('p', 'l');
6304 case MCC ('g', 'e'): return MCC ('l', 't');
6305 case MCC ('l', 't'): return MCC ('g', 'e');
6306 case MCC ('g', 't'): return MCC ('l', 'e');
6307 case MCC ('l', 'e'): return MCC ('g', 't');
6308 }
6309 return cc;
6310}
6311
6312/* Build an MRI structured control expression. This generates test
6313 and branch instructions. It goes to TRUELAB if the condition is
6314 true, and to FALSELAB if the condition is false. Exactly one of
6315 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6316 is the size qualifier for the expression. EXTENT is the size to
6317 use for the branch. */
6318
6319static void
31302357
AS		 6320build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6321 char *rightstart, char *rightstop,
6322 const char *truelab, const char *falselab,
6323 int extent)
252b5132
RH		 6324{
6325 char *buf;
6326 char *s;
6327
6328 if (leftstart != NULL)
6329 {
6330 struct m68k_op leftop, rightop;
6331 char c;
6332
6333 /* Swap the compare operands, if necessary, to produce a legal
6334 m68k compare instruction. Comparing a register operand with
6335 a non-register operand requires the register to be on the
6336 right (cmp, cmpa). Comparing an immediate value with
6337 anything requires the immediate value to be on the left
6338 (cmpi). */
6339
6340 c = *leftstop;
6341 *leftstop = '\0';
6342 (void) m68k_ip_op (leftstart, &leftop);
6343 *leftstop = c;
6344
6345 c = *rightstop;
6346 *rightstop = '\0';
6347 (void) m68k_ip_op (rightstart, &rightop);
6348 *rightstop = c;
6349
6350 if (rightop.mode == IMMED
6351 || ((leftop.mode == DREG || leftop.mode == AREG)
6352 && (rightop.mode != DREG && rightop.mode != AREG)))
6353 {
6354 char *temp;
6355
31302357
AS		 6356 /* Correct conditional handling:
6357 if #1 <lt> d0 then ;means if (1 < d0)
6358 ...
6359 endi
e1f44d10 6360
31302357 6361 should assemble to:
e1f44d10 6362
31302357
AS		 6363 cmp #1,d0 if we do *not* swap the operands
6364 bgt true we need the swapped condition!
6365 ble false
6366 true:
6367 ...
6368 false:
6369 */
252b5132
RH		 6370 temp = leftstart;
6371 leftstart = rightstart;
6372 rightstart = temp;
6373 temp = leftstop;
6374 leftstop = rightstop;
6375 rightstop = temp;
8a104df9
KH		 6376 }
6377 else
6378 {
e1f44d10 6379 cc = swap_mri_condition (cc);
252b5132
RH		 6380 }
6381 }
6382
6383 if (truelab == NULL)
6384 {
6385 cc = reverse_mri_condition (cc);
6386 truelab = falselab;
6387 }
92774660 6388
252b5132
RH		 6389 if (leftstart != NULL)
6390 {
add39d23
TS		 6391 buf = XNEWVEC (char, (20
6392 + (leftstop - leftstart)
6393 + (rightstop - rightstart)));
252b5132
RH		 6394 s = buf;
6395 *s++ = 'c';
6396 *s++ = 'm';
6397 *s++ = 'p';
6398 if (qual != '\0')
3882b010 6399 *s++ = TOLOWER (qual);
252b5132
RH		 6400 *s++ = ' ';
6401 memcpy (s, leftstart, leftstop - leftstart);
6402 s += leftstop - leftstart;
6403 *s++ = ',';
6404 memcpy (s, rightstart, rightstop - rightstart);
6405 s += rightstop - rightstart;
6406 *s = '\0';
6407 mri_assemble (buf);
6408 free (buf);
6409 }
92774660 6410
add39d23 6411 buf = XNEWVEC (char, 20 + strlen (truelab));
252b5132
RH		 6412 s = buf;
6413 *s++ = 'b';
6414 *s++ = cc >> 8;
6415 *s++ = cc & 0xff;
6416 if (extent != '\0')
3882b010 6417 *s++ = TOLOWER (extent);
252b5132
RH		 6418 *s++ = ' ';
6419 strcpy (s, truelab);
6420 mri_assemble (buf);
6421 free (buf);
6422}
6423
6424/* Parse an MRI structured control expression. This generates test
6425 and branch instructions. STOP is where the expression ends. It
6426 goes to TRUELAB if the condition is true, and to FALSELAB if the
6427 condition is false. Exactly one of TRUELAB and FALSELAB will be
6428 NULL, meaning to fall through. QUAL is the size qualifier for the
6429 expression. EXTENT is the size to use for the branch. */
6430
6431static void
31302357
AS		 6432parse_mri_control_expression (char *stop, int qual, const char *truelab,
6433 const char *falselab, int extent)
252b5132
RH		 6434{
6435 int c;
6436 int cc;
6437 char *leftstart;
6438 char *leftstop;
6439 char *rightstart;
6440 char *rightstop;
6441
6442 c = *stop;
6443 *stop = '\0';
6444
6445 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6446 &rightstart, &rightstop))
6447 {
6448 *stop = c;
6449 return;
6450 }
6451
6452 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6453 {
6454 const char *flab;
6455
6456 if (falselab != NULL)
6457 flab = falselab;
6458 else
6459 flab = mri_control_label ();
6460
6461 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6462 rightstop, (const char *) NULL, flab, extent);
6463
6464 input_line_pointer += 3;
6465 if (*input_line_pointer != '.'
6466 || input_line_pointer[1] == '\0')
6467 qual = '\0';
6468 else
6469 {
6470 qual = input_line_pointer[1];
6471 input_line_pointer += 2;
6472 }
6473
6474 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6475 &rightstart, &rightstop))
6476 {
6477 *stop = c;
6478 return;
6479 }
6480
6481 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6482 rightstop, truelab, falselab, extent);
6483
6484 if (falselab == NULL)
6485 colon (flab);
6486 }
6487 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6488 {
6489 const char *tlab;
6490
6491 if (truelab != NULL)
6492 tlab = truelab;
6493 else
6494 tlab = mri_control_label ();
6495
6496 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6497 rightstop, tlab, (const char *) NULL, extent);
6498
6499 input_line_pointer += 2;
6500 if (*input_line_pointer != '.'
6501 || input_line_pointer[1] == '\0')
6502 qual = '\0';
6503 else
6504 {
6505 qual = input_line_pointer[1];
6506 input_line_pointer += 2;
6507 }
6508
6509 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6510 &rightstart, &rightstop))
6511 {
6512 *stop = c;
6513 return;
6514 }
6515
6516 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6517 rightstop, truelab, falselab, extent);
6518
6519 if (truelab == NULL)
6520 colon (tlab);
6521 }
6522 else
6523 {
6524 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6525 rightstop, truelab, falselab, extent);
6526 }
6527
6528 *stop = c;
6529 if (input_line_pointer != stop)
6530 as_bad (_("syntax error in structured control directive"));
6531}
6532
6533/* Handle the MRI IF pseudo-op. This may be a structured control
6534 directive, or it may be a regular assembler conditional, depending
6535 on its operands. */
6536
6537static void
31302357 6538s_mri_if (int qual)
252b5132
RH		 6539{
6540 char *s;
6541 int c;
6542 struct mri_control_info *n;
6543
6544 /* A structured control directive must end with THEN with an
6545 optional qualifier. */
6546 s = input_line_pointer;
e1f44d10
NC		 6547 /* We only accept '*' as introduction of comments if preceded by white space
6548 or at first column of a line (I think this can't actually happen here?)
6549 This is important when assembling:
6550 if d0 <ne> 12(a0,d0*2) then
36759679 6551 if d0 <ne> #CONST*20 then. */
31302357
AS		 6552 while (! (is_end_of_line[(unsigned char) *s]
6553 || (flag_mri
6554 && *s == '*'
6555 && (s == input_line_pointer
6556 || *(s-1) == ' '
6557 || *(s-1) == '\t'))))
252b5132
RH		 6558 ++s;
6559 --s;
6560 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6561 --s;
6562
6563 if (s - input_line_pointer > 1
6564 && s[-1] == '.')
6565 s -= 2;
6566
6567 if (s - input_line_pointer < 3
6568 || strncasecmp (s - 3, "THEN", 4) != 0)
6569 {
6570 if (qual != '\0')
6571 {
6572 as_bad (_("missing then"));
6573 ignore_rest_of_line ();
6574 return;
6575 }
6576
6577 /* It's a conditional. */
6578 s_if (O_ne);
6579 return;
6580 }
6581
6582 /* Since this might be a conditional if, this pseudo-op will be
6583 called even if we are supported to be ignoring input. Double
6584 check now. Clobber *input_line_pointer so that ignore_input
6585 thinks that this is not a special pseudo-op. */
6586 c = *input_line_pointer;
6587 *input_line_pointer = 0;
6588 if (ignore_input ())
6589 {
6590 *input_line_pointer = c;
6591 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6592 ++input_line_pointer;
6593 demand_empty_rest_of_line ();
6594 return;
6595 }
6596 *input_line_pointer = c;
6597
6598 n = push_mri_control (mri_if);
6599
6600 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6601 n->next, s[1] == '.' ? s[2] : '\0');
6602
6603 if (s[1] == '.')
6604 input_line_pointer = s + 3;
6605 else
6606 input_line_pointer = s + 1;
6607
6608 if (flag_mri)
6609 {
6610 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6611 ++input_line_pointer;
6612 }
6613
6614 demand_empty_rest_of_line ();
6615}
6616
6617/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6618 structured IF, associate the ELSE with the IF. Otherwise, assume
6619 it is a conditional else. */
6620
6621static void
31302357 6622s_mri_else (int qual)
252b5132
RH		 6623{
6624 int c;
6625 char *buf;
6626 char q[2];
6627
6628 if (qual == '\0'
6629 && (mri_control_stack == NULL
6630 || mri_control_stack->type != mri_if
6631 || mri_control_stack->else_seen))
6632 {
6633 s_else (0);
6634 return;
6635 }
6636
6637 c = *input_line_pointer;
6638 *input_line_pointer = 0;
6639 if (ignore_input ())
6640 {
6641 *input_line_pointer = c;
6642 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6643 ++input_line_pointer;
6644 demand_empty_rest_of_line ();
6645 return;
6646 }
6647 *input_line_pointer = c;
6648
6649 if (mri_control_stack == NULL
6650 || mri_control_stack->type != mri_if
6651 || mri_control_stack->else_seen)
6652 {
6653 as_bad (_("else without matching if"));
6654 ignore_rest_of_line ();
6655 return;
6656 }
6657
6658 mri_control_stack->else_seen = 1;
6659
add39d23 6660 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->bottom));
3882b010 6661 q[0] = TOLOWER (qual);
252b5132
RH		 6662 q[1] = '\0';
6663 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6664 mri_assemble (buf);
6665 free (buf);
6666
6667 colon (mri_control_stack->next);
6668
6669 if (flag_mri)
6670 {
6671 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6672 ++input_line_pointer;
6673 }
6674
6675 demand_empty_rest_of_line ();
6676}
6677
6678/* Handle the MRI ENDI pseudo-op. */
6679
6680static void
31302357 6681s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6682{
6683 if (mri_control_stack == NULL
6684 || mri_control_stack->type != mri_if)
6685 {
6686 as_bad (_("endi without matching if"));
6687 ignore_rest_of_line ();
6688 return;
6689 }
6690
6691 /* ignore_input will not return true for ENDI, so we don't need to
6692 worry about checking it again here. */
6693
6694 if (! mri_control_stack->else_seen)
6695 colon (mri_control_stack->next);
6696 colon (mri_control_stack->bottom);
6697
6698 pop_mri_control ();
6699
6700 if (flag_mri)
6701 {
6702 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6703 ++input_line_pointer;
6704 }
6705
6706 demand_empty_rest_of_line ();
6707}
6708
6709/* Handle the MRI BREAK pseudo-op. */
6710
6711static void
31302357 6712s_mri_break (int extent)
252b5132
RH		 6713{
6714 struct mri_control_info *n;
6715 char *buf;
6716 char ex[2];
6717
6718 n = mri_control_stack;
6719 while (n != NULL
6720 && n->type != mri_for
6721 && n->type != mri_repeat
6722 && n->type != mri_while)
6723 n = n->outer;
6724 if (n == NULL)
6725 {
6726 as_bad (_("break outside of structured loop"));
6727 ignore_rest_of_line ();
6728 return;
6729 }
6730
add39d23 6731 buf = XNEWVEC (char, 20 + strlen (n->bottom));
3882b010 6732 ex[0] = TOLOWER (extent);
252b5132
RH		 6733 ex[1] = '\0';
6734 sprintf (buf, "bra%s %s", ex, n->bottom);
6735 mri_assemble (buf);
6736 free (buf);
6737
6738 if (flag_mri)
6739 {
6740 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6741 ++input_line_pointer;
6742 }
6743
6744 demand_empty_rest_of_line ();
6745}
6746
6747/* Handle the MRI NEXT pseudo-op. */
6748
6749static void
31302357 6750s_mri_next (int extent)
252b5132
RH		 6751{
6752 struct mri_control_info *n;
6753 char *buf;
6754 char ex[2];
6755
6756 n = mri_control_stack;
6757 while (n != NULL
6758 && n->type != mri_for
6759 && n->type != mri_repeat
6760 && n->type != mri_while)
6761 n = n->outer;
6762 if (n == NULL)
6763 {
6764 as_bad (_("next outside of structured loop"));
6765 ignore_rest_of_line ();
6766 return;
6767 }
6768
add39d23 6769 buf = XNEWVEC (char, 20 + strlen (n->next));
3882b010 6770 ex[0] = TOLOWER (extent);
252b5132
RH		 6771 ex[1] = '\0';
6772 sprintf (buf, "bra%s %s", ex, n->next);
6773 mri_assemble (buf);
6774 free (buf);
6775
6776 if (flag_mri)
6777 {
6778 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6779 ++input_line_pointer;
6780 }
6781
6782 demand_empty_rest_of_line ();
6783}
6784
6785/* Handle the MRI FOR pseudo-op. */
6786
6787static void
31302357 6788s_mri_for (int qual)
252b5132
RH		 6789{
6790 const char *varstart, *varstop;
6791 const char *initstart, *initstop;
6792 const char *endstart, *endstop;
6793 const char *bystart, *bystop;
6794 int up;
6795 int by;
6796 int extent;
6797 struct mri_control_info *n;
6798 char *buf;
6799 char *s;
6800 char ex[2];
6801
6802 /* The syntax is
6803 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6804 */
6805
6806 SKIP_WHITESPACE ();
6807 varstart = input_line_pointer;
6808
6809 /* Look for the '='. */
6810 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6811 && *input_line_pointer != '=')
6812 ++input_line_pointer;
6813 if (*input_line_pointer != '=')
6814 {
6815 as_bad (_("missing ="));
6816 ignore_rest_of_line ();
6817 return;
6818 }
6819
6820 varstop = input_line_pointer;
6821 if (varstop > varstart
6822 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6823 --varstop;
6824
6825 ++input_line_pointer;
6826
6827 initstart = input_line_pointer;
6828
6829 /* Look for TO or DOWNTO. */
6830 up = 1;
6831 initstop = NULL;
6832 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6833 {
6834 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6835 && ! is_part_of_name (input_line_pointer[2]))
6836 {
6837 initstop = input_line_pointer;
6838 input_line_pointer += 2;
6839 break;
6840 }
6841 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6842 && ! is_part_of_name (input_line_pointer[6]))
6843 {
6844 initstop = input_line_pointer;
6845 up = 0;
6846 input_line_pointer += 6;
6847 break;
6848 }
6849 ++input_line_pointer;
6850 }
6851 if (initstop == NULL)
6852 {
6853 as_bad (_("missing to or downto"));
6854 ignore_rest_of_line ();
6855 return;
6856 }
6857 if (initstop > initstart
6858 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6859 --initstop;
6860
6861 SKIP_WHITESPACE ();
6862 endstart = input_line_pointer;
6863
6864 /* Look for BY or DO. */
6865 by = 0;
6866 endstop = NULL;
6867 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6868 {
6869 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6870 && ! is_part_of_name (input_line_pointer[2]))
6871 {
6872 endstop = input_line_pointer;
6873 by = 1;
6874 input_line_pointer += 2;
6875 break;
6876 }
6877 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6878 && (input_line_pointer[2] == '.'
6879 || ! is_part_of_name (input_line_pointer[2])))
6880 {
6881 endstop = input_line_pointer;
6882 input_line_pointer += 2;
6883 break;
6884 }
6885 ++input_line_pointer;
6886 }
6887 if (endstop == NULL)
6888 {
6889 as_bad (_("missing do"));
6890 ignore_rest_of_line ();
6891 return;
6892 }
6893 if (endstop > endstart
6894 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6895 --endstop;
6896
6897 if (! by)
6898 {
6899 bystart = "#1";
6900 bystop = bystart + 2;
6901 }
6902 else
6903 {
6904 SKIP_WHITESPACE ();
6905 bystart = input_line_pointer;
6906
6907 /* Look for DO. */
6908 bystop = NULL;
6909 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6910 {
6911 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6912 && (input_line_pointer[2] == '.'
6913 || ! is_part_of_name (input_line_pointer[2])))
6914 {
6915 bystop = input_line_pointer;
6916 input_line_pointer += 2;
6917 break;
6918 }
6919 ++input_line_pointer;
6920 }
6921 if (bystop == NULL)
6922 {
6923 as_bad (_("missing do"));
6924 ignore_rest_of_line ();
6925 return;
6926 }
6927 if (bystop > bystart
6928 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6929 --bystop;
6930 }
6931
6932 if (*input_line_pointer != '.')
6933 extent = '\0';
6934 else
6935 {
6936 extent = input_line_pointer[1];
6937 input_line_pointer += 2;
6938 }
6939
6940 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6941 n = push_mri_control (mri_for);
6942
add39d23 6943 buf = XNEWVEC (char, 50 + (input_line_pointer - varstart));
252b5132 6944
36759679 6945 /* Move init,var. */
252b5132
RH		 6946 s = buf;
6947 *s++ = 'm';
6948 *s++ = 'o';
6949 *s++ = 'v';
6950 *s++ = 'e';
6951 if (qual != '\0')
3882b010 6952 *s++ = TOLOWER (qual);
252b5132
RH		 6953 *s++ = ' ';
6954 memcpy (s, initstart, initstop - initstart);
6955 s += initstop - initstart;
6956 *s++ = ',';
6957 memcpy (s, varstart, varstop - varstart);
6958 s += varstop - varstart;
6959 *s = '\0';
6960 mri_assemble (buf);
6961
6962 colon (n->top);
6963
36759679 6964 /* cmp end,var. */
252b5132
RH		 6965 s = buf;
6966 *s++ = 'c';
6967 *s++ = 'm';
6968 *s++ = 'p';
6969 if (qual != '\0')
3882b010 6970 *s++ = TOLOWER (qual);
252b5132
RH		 6971 *s++ = ' ';
6972 memcpy (s, endstart, endstop - endstart);
6973 s += endstop - endstart;
6974 *s++ = ',';
6975 memcpy (s, varstart, varstop - varstart);
6976 s += varstop - varstart;
6977 *s = '\0';
6978 mri_assemble (buf);
6979
36759679 6980 /* bcc bottom. */
3882b010 6981 ex[0] = TOLOWER (extent);
252b5132
RH		 6982 ex[1] = '\0';
6983 if (up)
6984 sprintf (buf, "blt%s %s", ex, n->bottom);
6985 else
6986 sprintf (buf, "bgt%s %s", ex, n->bottom);
6987 mri_assemble (buf);
6988
6989 /* Put together the add or sub instruction used by ENDF. */
6990 s = buf;
6991 if (up)
6992 strcpy (s, "add");
6993 else
6994 strcpy (s, "sub");
6995 s += 3;
6996 if (qual != '\0')
3882b010 6997 *s++ = TOLOWER (qual);
252b5132
RH		 6998 *s++ = ' ';
6999 memcpy (s, bystart, bystop - bystart);
7000 s += bystop - bystart;
7001 *s++ = ',';
7002 memcpy (s, varstart, varstop - varstart);
7003 s += varstop - varstart;
7004 *s = '\0';
7005 n->incr = buf;
7006
7007 if (flag_mri)
7008 {
7009 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7010 ++input_line_pointer;
7011 }
7012
7013 demand_empty_rest_of_line ();
7014}
7015
7016/* Handle the MRI ENDF pseudo-op. */
7017
7018static void
31302357 7019s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7020{
7021 if (mri_control_stack == NULL
7022 || mri_control_stack->type != mri_for)
7023 {
7024 as_bad (_("endf without for"));
7025 ignore_rest_of_line ();
7026 return;
7027 }
7028
7029 colon (mri_control_stack->next);
7030
7031 mri_assemble (mri_control_stack->incr);
7032
7033 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7034 mri_assemble (mri_control_stack->incr);
7035
7036 free (mri_control_stack->incr);
7037
7038 colon (mri_control_stack->bottom);
7039
7040 pop_mri_control ();
7041
7042 if (flag_mri)
7043 {
7044 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7045 ++input_line_pointer;
7046 }
7047
7048 demand_empty_rest_of_line ();
7049}
7050
7051/* Handle the MRI REPEAT pseudo-op. */
7052
7053static void
31302357 7054s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7055{
7056 struct mri_control_info *n;
7057
7058 n = push_mri_control (mri_repeat);
7059 colon (n->top);
7060 if (flag_mri)
7061 {
7062 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7063 ++input_line_pointer;
7064 }
7065 demand_empty_rest_of_line ();
7066}
7067
7068/* Handle the MRI UNTIL pseudo-op. */
7069
7070static void
31302357 7071s_mri_until (int qual)
252b5132
RH		 7072{
7073 char *s;
7074
7075 if (mri_control_stack == NULL
7076 || mri_control_stack->type != mri_repeat)
7077 {
7078 as_bad (_("until without repeat"));
7079 ignore_rest_of_line ();
7080 return;
7081 }
7082
7083 colon (mri_control_stack->next);
7084
7085 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7086 ;
7087
7088 parse_mri_control_expression (s, qual, (const char *) NULL,
7089 mri_control_stack->top, '\0');
7090
7091 colon (mri_control_stack->bottom);
7092
7093 input_line_pointer = s;
7094
7095 pop_mri_control ();
7096
7097 if (flag_mri)
7098 {
7099 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7100 ++input_line_pointer;
7101 }
7102
7103 demand_empty_rest_of_line ();
7104}
7105
7106/* Handle the MRI WHILE pseudo-op. */
7107
7108static void
31302357 7109s_mri_while (int qual)
252b5132
RH		 7110{
7111 char *s;
7112
7113 struct mri_control_info *n;
7114
7115 s = input_line_pointer;
e1f44d10
NC		 7116 /* We only accept '*' as introduction of comments if preceded by white space
7117 or at first column of a line (I think this can't actually happen here?)
7118 This is important when assembling:
7119 while d0 <ne> 12(a0,d0*2) do
36759679 7120 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7121 while (! (is_end_of_line[(unsigned char) *s]
7122 || (flag_mri
7123 && *s == '*'
7124 && (s == input_line_pointer
7125 || *(s-1) == ' '
7126 || *(s-1) == '\t'))))
252b5132
RH		 7127 s++;
7128 --s;
7129 while (*s == ' ' || *s == '\t')
7130 --s;
7131 if (s - input_line_pointer > 1
7132 && s[-1] == '.')
7133 s -= 2;
7134 if (s - input_line_pointer < 2
7135 || strncasecmp (s - 1, "DO", 2) != 0)
7136 {
7137 as_bad (_("missing do"));
7138 ignore_rest_of_line ();
7139 return;
7140 }
7141
7142 n = push_mri_control (mri_while);
7143
7144 colon (n->next);
7145
7146 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7147 s[1] == '.' ? s[2] : '\0');
7148
7149 input_line_pointer = s + 1;
7150 if (*input_line_pointer == '.')
7151 input_line_pointer += 2;
7152
7153 if (flag_mri)
7154 {
7155 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7156 ++input_line_pointer;
7157 }
7158
7159 demand_empty_rest_of_line ();
7160}
7161
7162/* Handle the MRI ENDW pseudo-op. */
7163
7164static void
31302357 7165s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7166{
7167 char *buf;
7168
7169 if (mri_control_stack == NULL
7170 || mri_control_stack->type != mri_while)
7171 {
7172 as_bad (_("endw without while"));
7173 ignore_rest_of_line ();
7174 return;
7175 }
7176
add39d23 7177 buf = XNEWVEC (char, 20 + strlen (mri_control_stack->next));
252b5132
RH		 7178 sprintf (buf, "bra %s", mri_control_stack->next);
7179 mri_assemble (buf);
7180 free (buf);
7181
7182 colon (mri_control_stack->bottom);
7183
7184 pop_mri_control ();
7185
7186 if (flag_mri)
7187 {
7188 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7189 ++input_line_pointer;
7190 }
7191
7192 demand_empty_rest_of_line ();
7193}
7194\f
266abb8f
NS		 7195/* Parse a .cpu directive. */
7196
7197static void
7198s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7199{
7200 char saved_char;
7201 char *name;
7202
7203 if (initialized)
7204 {
7205 as_bad (_("already assembled instructions"));
7206 ignore_rest_of_line ();
7207 return;
7208 }
3739860c 7209
266abb8f
NS		 7210 name = input_line_pointer;
7211 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7212 input_line_pointer++;
7213 saved_char = *input_line_pointer;
7214 *input_line_pointer = 0;
7215
7216 m68k_set_cpu (name, 1, 0);
3739860c 7217
266abb8f
NS		 7218 *input_line_pointer = saved_char;
7219 demand_empty_rest_of_line ();
7220 return;
7221}
7222
7223/* Parse a .arch directive. */
7224
7225static void
7226s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7227{
7228 char saved_char;
7229 char *name;
7230
7231 if (initialized)
7232 {
7233 as_bad (_("already assembled instructions"));
7234 ignore_rest_of_line ();
7235 return;
7236 }
3739860c 7237
266abb8f
NS		 7238 name = input_line_pointer;
7239 while (*input_line_pointer && *input_line_pointer != ','
7240 && !ISSPACE (*input_line_pointer))
7241 input_line_pointer++;
7242 saved_char = *input_line_pointer;
7243 *input_line_pointer = 0;
7244
7245 if (m68k_set_arch (name, 1, 0))
7246 {
7247 /* Scan extensions. */
7248 do
7249 {
7250 *input_line_pointer++ = saved_char;
7251 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7252 break;
7253 name = input_line_pointer;
7254 while (*input_line_pointer && *input_line_pointer != ','
7255 && !ISSPACE (*input_line_pointer))
7256 input_line_pointer++;
7257 saved_char = *input_line_pointer;
7258 *input_line_pointer = 0;
7259 }
7260 while (m68k_set_extension (name, 1, 0));
7261 }
3739860c 7262
266abb8f
NS		 7263 *input_line_pointer = saved_char;
7264 demand_empty_rest_of_line ();
7265 return;
7266}
7267\f
7268/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7269 if none is found, the caller is responsible for emitting an error
7270 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7271 cpu name, if it begins with a '6' (possibly skipping an intervening
7272 'c'. We also allow a 'c' in the same place. if NEGATED is
7273 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7274 the option is indeed negated. */
7275
7276static const struct m68k_cpu *
7277m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7278 int allow_m, int *negated)
7279{
7280 /* allow negated value? */
7281 if (negated)
7282 {
7283 *negated = 0;
7284
7285 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7286 {
7287 arg += 3;
7288 *negated = 1;
7289 }
7290 }
3739860c 7291
266abb8f
NS		 7292 /* Remove 'm' or 'mc' prefix from 68k variants. */
7293 if (allow_m)
7294 {
7295 if (arg[0] == 'm')
7296 {
7297 if (arg[1] == '6')
7298 arg += 1;
7299 else if (arg[1] == 'c' && arg[2] == '6')
7300 arg += 2;
7301 }
7302 }
7303 else if (arg[0] == 'c' && arg[1] == '6')
7304 arg += 1;
7305
7306 for (; table->name; table++)
7307 if (!strcmp (arg, table->name))
2da12c60
NS		 7308 {
7309 if (table->alias < -1 || table->alias > 1)
7310 as_bad (_("`%s' is deprecated, use `%s'"),
7311 table->name, table[table->alias < 0 ? 1 : -1].name);
7312 return table;
7313 }
266abb8f
NS		 7314 return 0;
7315}
7316
bfbba8e4 7317/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7318
7319static int
7320m68k_set_cpu (char const *name, int allow_m, int silent)
7321{
7322 const struct m68k_cpu *cpu;
7323
7324 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7325
7326 if (!cpu)
7327 {
7328 if (!silent)
7329 as_bad (_("cpu `%s' unrecognized"), name);
7330 return 0;
7331 }
266abb8f
NS		 7332 selected_cpu = cpu;
7333 return 1;
7334}
7335
bfbba8e4 7336/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7337
7338static int
7339m68k_set_arch (char const *name, int allow_m, int silent)
7340{
7341 const struct m68k_cpu *arch;
7342
7343 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7344
7345 if (!arch)
7346 {
7347 if (!silent)
7348 as_bad (_("architecture `%s' unrecognized"), name);
7349 return 0;
7350 }
266abb8f
NS		 7351 selected_arch = arch;
7352 return 1;
7353}
7354
7355/* Set the architecture extension, issuing errors if it is
7356 unrecognized, or invalid */
7357
7358static int
7359m68k_set_extension (char const *name, int allow_m, int silent)
7360{
7361 int negated;
7362 const struct m68k_cpu *ext;
7363
7364 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7365
7366 if (!ext)
7367 {
7368 if (!silent)
7369 as_bad (_("extension `%s' unrecognized"), name);
7370 return 0;
7371 }
7372
7373 if (negated)
87298967
NS		 7374 not_current_architecture |= (ext->control_regs
7375 ? *(unsigned *)ext->control_regs: ext->arch);
266abb8f
NS		 7376 else
7377 current_architecture |= ext->arch;
7378 return 1;
7379}
7380
31302357
AS		 7381/* md_parse_option
7382 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7383 */
252b5132 7384
5a38dc70 7385const char *md_shortopts = "lSA:m:kQ:V";
252b5132
RH		 7386
7387struct option md_longopts[] = {
7388#define OPTION_PIC (OPTION_MD_BASE)
7389 {"pic", no_argument, NULL, OPTION_PIC},
7390#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7391 {"register-prefix-optional", no_argument, NULL,
7392 OPTION_REGISTER_PREFIX_OPTIONAL},
7393#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7394 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7395#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7396 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7397#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7398 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7399#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7400 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7401#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7402 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7403#define OPTION_PCREL (OPTION_MD_BASE + 7)
7404 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7405 {NULL, no_argument, NULL, 0}
7406};
bc805888 7407size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7408
7409int
17b9d67d 7410md_parse_option (int c, const char *arg)
252b5132
RH		 7411{
7412 switch (c)
7413 {
7414 case 'l': /* -l means keep external to 2 bit offset
36759679 7415 rather than 16 bit one. */
252b5132
RH		 7416 flag_short_refs = 1;
7417 break;
7418
7419 case 'S': /* -S means that jbsr's always turn into
7420 jsr's. */
7421 flag_long_jumps = 1;
7422 break;
7423
28e7409f
NC		 7424 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7425 branches into absolute jumps. */
7426 flag_keep_pcrel = 1;
7427 break;
7428
252b5132
RH		 7429 case OPTION_PIC:
7430 case 'k':
7431 flag_want_pic = 1;
36759679 7432 break; /* -pic, Position Independent Code. */
252b5132
RH		 7433
7434 case OPTION_REGISTER_PREFIX_OPTIONAL:
7435 flag_reg_prefix_optional = 1;
7436 reg_prefix_optional_seen = 1;
7437 break;
7438
7439 /* -V: SVR4 argument to print version ID. */
7440 case 'V':
7441 print_version_id ();
7442 break;
7443
7444 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7445 should be emitted or not. FIXME: Not implemented. */
7446 case 'Q':
7447 break;
7448
7449 case OPTION_BITWISE_OR:
7450 {
7451 char *n, *t;
7452 const char *s;
7453
add39d23 7454 n = XNEWVEC (char, strlen (m68k_comment_chars) + 1);
252b5132
RH		 7455 t = n;
7456 for (s = m68k_comment_chars; *s != '\0'; s++)
7457 if (*s != '|')
7458 *t++ = *s;
7459 *t = '\0';
7460 m68k_comment_chars = n;
7461 }
7462 break;
7463
7464 case OPTION_BASE_SIZE_DEFAULT_16:
7465 m68k_index_width_default = SIZE_WORD;
7466 break;
7467
7468 case OPTION_BASE_SIZE_DEFAULT_32:
7469 m68k_index_width_default = SIZE_LONG;
7470 break;
7471
7472 case OPTION_DISP_SIZE_DEFAULT_16:
7473 m68k_rel32 = 0;
7474 m68k_rel32_from_cmdline = 1;
7475 break;
7476
7477 case OPTION_DISP_SIZE_DEFAULT_32:
7478 m68k_rel32 = 1;
7479 m68k_rel32_from_cmdline = 1;
7480 break;
7481
266abb8f
NS		 7482 case 'A':
7483#if WARN_DEPRECATED
7484 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7485 arg, arg));
7486#endif
7487 /* Intentional fall-through. */
7488 case 'm':
7489 if (!strncmp (arg, "arch=", 5))
7490 m68k_set_arch (arg + 5, 1, 0);
7491 else if (!strncmp (arg, "cpu=", 4))
7492 m68k_set_cpu (arg + 4, 1, 0);
7493 else if (m68k_set_extension (arg, 0, 1))
7494 ;
0b2e31dc
NS		 7495 else if (m68k_set_arch (arg, 0, 1))
7496 ;
266abb8f
NS		 7497 else if (m68k_set_cpu (arg, 0, 1))
7498 ;
7499 else
7500 return 0;
7501 break;
7502
252b5132
RH		 7503 default:
7504 return 0;
7505 }
7506
7507 return 1;
7508}
7509
266abb8f
NS		 7510/* Setup tables from the selected arch and/or cpu */
7511
7512static void
7513m68k_init_arch (void)
7514{
266abb8f
NS		 7515 if (not_current_architecture & current_architecture)
7516 {
7517 as_bad (_("architecture features both enabled and disabled"));
7518 not_current_architecture &= ~current_architecture;
7519 }
7520 if (selected_arch)
2da12c60
NS		 7521 {
7522 current_architecture |= selected_arch->arch;
7523 control_regs = selected_arch->control_regs;
7524 }
0b2e31dc
NS		 7525 else
7526 current_architecture |= selected_cpu->arch;
3739860c 7527
2da12c60
NS		 7528 current_architecture &= ~not_current_architecture;
7529
377260ba
NS		 7530 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7531 {
7532 /* Determine which float is really meant. */
7533 if (current_architecture & (m68k_mask & ~m68881))
7534 current_architecture ^= cfloat;
7535 else
7536 current_architecture ^= m68881;
7537 }
7538
0b2e31dc 7539 if (selected_cpu)
266abb8f 7540 {
2da12c60 7541 control_regs = selected_cpu->control_regs;
0b2e31dc 7542 if (current_architecture & ~selected_cpu->arch)
266abb8f 7543 {
0b2e31dc
NS		 7544 as_bad (_("selected processor does not have all features of selected architecture"));
7545 current_architecture
7546 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7547 }
7548 }
266abb8f 7549
266abb8f
NS		 7550 if ((current_architecture & m68k_mask)
7551 && (current_architecture & ~m68k_mask))
7552 {
7553 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7554 if (current_architecture & m68k_mask)
266abb8f
NS		 7555 current_architecture &= m68k_mask;
7556 else
7557 current_architecture &= ~m68k_mask;
7558 }
3739860c 7559
266abb8f
NS		 7560 /* Permit m68881 specification with all cpus; those that can't work
7561 with a coprocessor could be doing emulation. */
7562 if (current_architecture & m68851)
7563 {
7564 if (current_architecture & m68040)
7565 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7566 }
7567 /* What other incompatibilities could we check for? */
7568
266abb8f
NS		 7569 if (cpu_of_arch (current_architecture) < m68020
7570 || arch_coldfire_p (current_architecture))
7571 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
3739860c 7572
266abb8f
NS		 7573 initialized = 1;
7574}
7575
252b5132 7576void
31302357 7577md_show_usage (FILE *stream)
252b5132 7578{
76f57f3a 7579 const char *default_cpu = TARGET_CPU;
f1f5ef86 7580 int i;
76f57f3a 7581
8a104df9 7582 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7583 if (*default_cpu == 'm')
7584 default_cpu++;
266abb8f 7585 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7586 {
266abb8f 7587 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7588 {
2da12c60
NS		 7589 while (m68k_cpus[i].alias > 0)
7590 i--;
7591 while (m68k_cpus[i].alias < 0)
7592 i++;
7593 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7594 }
7595 }
7596
bc805888 7597 fprintf (stream, _("\
266abb8f
NS		 7598-march=<arch> set architecture\n\
7599-mcpu=<cpu> set cpu [default %s]\n\
7600"), default_cpu);
7601 for (i = 0; m68k_extensions[i].name; i++)
7602 fprintf (stream, _("\
33eaf5de 7603-m[no-]%-16s enable/disable %s architecture extension\n\
0b2e31dc
NS		 7604"), m68k_extensions[i].name,
7605 m68k_extensions[i].alias > 0 ? " ColdFire"
7606 : m68k_extensions[i].alias < 0 ? " m68k" : "");
3739860c 7607
bc805888 7608 fprintf (stream, _("\
266abb8f 7609-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7610-pic, -k generate position independent code\n\
7611-S turn jbsr into jsr\n\
28e7409f 7612--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7613--register-prefix-optional\n\
7614 recognize register names without prefix character\n\
266abb8f 7615--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7616--base-size-default-16 base reg without size is 16 bits\n\
7617--base-size-default-32 base reg without size is 32 bits (default)\n\
7618--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7619--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7620"));
3739860c 7621
266abb8f
NS		 7622 fprintf (stream, _("Architecture variants are: "));
7623 for (i = 0; m68k_archs[i].name; i++)
7624 {
7625 if (i)
7626 fprintf (stream, " | ");
87298967 7627 fprintf (stream, "%s", m68k_archs[i].name);
266abb8f
NS		 7628 }
7629 fprintf (stream, "\n");
7630
7631 fprintf (stream, _("Processor variants are: "));
7632 for (i = 0; m68k_cpus[i].name; i++)
7633 {
7634 if (i)
7635 fprintf (stream, " | ");
87298967 7636 fprintf (stream, "%s", m68k_cpus[i].name);
266abb8f
NS		 7637 }
7638 fprintf (stream, _("\n"));
252b5132
RH		 7639}
7640\f
7641#ifdef TEST2
7642
7643/* TEST2: Test md_assemble() */
36759679
NC		 7644/* Warning, this routine probably doesn't work anymore. */
7645int
31302357 7646main (void)
252b5132
RH		 7647{
7648 struct m68k_it the_ins;
7649 char buf[120];
7650 char *cp;
7651 int n;
7652
7653 m68k_ip_begin ();
7654 for (;;)
7655 {
7656 if (!gets (buf) || !*buf)
7657 break;
7658 if (buf[0] == '|' || buf[1] == '.')
7659 continue;
7660 for (cp = buf; *cp; cp++)
7661 if (*cp == '\t')
7662 *cp = ' ';
7663 if (is_label (buf))
7664 continue;
7665 memset (&the_ins, '\0', sizeof (the_ins));
7666 m68k_ip (&the_ins, buf);
7667 if (the_ins.error)
7668 {
7669 printf (_("Error %s in %s\n"), the_ins.error, buf);
7670 }
7671 else
7672 {
7673 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7674 for (n = 0; n < the_ins.numo; n++)
7675 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7676 printf (" ");
7677 print_the_insn (&the_ins.opcode[0], stdout);
7678 (void) putchar ('\n');
7679 }
7680 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7681 {
7682 if (the_ins.operands[n].error)
7683 {
7684 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7685 continue;
7686 }
31302357
AS		 7687 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7688 the_ins.operands[n].reg);
252b5132 7689 if (the_ins.operands[n].b_const)
31302357
AS		 7690 printf ("Constant: '%.*s', ",
7691 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7692 the_ins.operands[n].b_const);
7693 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7694 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7695 if (the_ins.operands[n].b_iadd)
31302357
AS		 7696 printf ("Iadd: '%.*s',",
7697 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7698 the_ins.operands[n].b_iadd);
7699 putchar ('\n');
252b5132
RH		 7700 }
7701 }
7702 m68k_ip_end ();
7703 return 0;
7704}
7705
31302357
AS		 7706int
7707is_label (char *str)
252b5132
RH		 7708{
7709 while (*str == ' ')
7710 str++;
7711 while (*str && *str != ' ')
7712 str++;
7713 if (str[-1] == ':' || str[1] == '=')
7714 return 1;
7715 return 0;
7716}
7717
7718#endif
7719
7720/* Possible states for relaxation:
7721
7722 0 0 branch offset byte (bra, etc)
7723 0 1 word
7724 0 2 long
7725
7726 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7727 1 1 word
7728 1 2 long
7729
7730 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7731 2 1 word-long
7732 2 2 long-word
7733 2 3 long-long
7734
7735 */
7736
7737/* We have no need to default values of symbols. */
7738
252b5132 7739symbolS *
31302357 7740md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7741{
7742 return 0;
7743}
7744
7745/* Round up a section size to the appropriate boundary. */
7746valueT
31302357 7747md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132 7748{
252b5132
RH		 7749 return size;
7750}
7751
7752/* Exactly what point is a PC-relative offset relative TO?
7753 On the 68k, it is relative to the address of the first extension
7754 word. The difference between the addresses of the offset and the
92774660 7755 first extension word is stored in fx_pcrel_adjust. */
252b5132 7756long
31302357 7757md_pcrel_from (fixS *fixP)
252b5132
RH		 7758{
7759 int adjust;
7760
552c607f 7761 adjust = fixP->fx_pcrel_adjust;
252b5132
RH		 7762 if (adjust == 64)
7763 adjust = -1;
7764 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7765}
7766
8a104df9 7767void
31302357 7768m68k_elf_final_processing (void)
0d96863f 7769{
266abb8f 7770 unsigned flags = 0;
3739860c 7771
238d258f 7772 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7773 flags |= EF_M68K_CFV4E;
7774 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7775 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7776 flags |= EF_M68K_CPU32;
7777 else if (cpu_of_arch (current_architecture) & fido_a)
7778 flags |= EF_M68K_FIDO;
8a104df9
KH		 7779 else if ((cpu_of_arch (current_architecture) & m68000up)
7780 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f 7781 flags |= EF_M68K_M68000;
3739860c 7782
266abb8f
NS		 7783 if (current_architecture & mcfisa_a)
7784 {
0b2e31dc
NS		 7785 static const unsigned isa_features[][2] =
7786 {
9a2e615a 7787 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7788 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7789 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7790 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7791 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7792 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7793 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7794 {0,0},
7795 };
7796 static const unsigned mac_features[][2] =
7797 {
c694fd50
KH		 7798 {EF_M68K_CF_MAC, mcfmac},
7799 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7800 {0,0},
7801 };
7802 unsigned ix;
7803 unsigned pattern;
3739860c 7804
0b2e31dc 7805 pattern = (current_architecture
9a2e615a 7806 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7807 for (ix = 0; isa_features[ix][1]; ix++)
7808 {
7809 if (pattern == isa_features[ix][1])
7810 {
7811 flags |= isa_features[ix][0];
7812 break;
7813 }
7814 }
7815 if (!isa_features[ix][1])
7816 {
7817 cf_bad:
7818 as_warn (_("Not a defined coldfire architecture"));
7819 }
7820 else
7821 {
7822 if (current_architecture & cfloat)
c694fd50 7823 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7824
0b2e31dc
NS		 7825 pattern = current_architecture & (mcfmac|mcfemac);
7826 if (pattern)
7827 {
7828 for (ix = 0; mac_features[ix][1]; ix++)
7829 {
7830 if (pattern == mac_features[ix][1])
7831 {
7832 flags |= mac_features[ix][0];
7833 break;
7834 }
7835 }
7836 if (!mac_features[ix][1])
7837 goto cf_bad;
7838 }
7839 }
266abb8f
NS		 7840 }
7841 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7842}
cf869cce
NC		 7843
7844/* Parse @TLSLDO and return the desired relocation. */
7845static bfd_reloc_code_real_type
7846m68k_elf_suffix (char **str_p, expressionS *exp_p)
7847{
7848 char ident[20];
7849 char *str = *str_p;
7850 char *str2;
7851 int ch;
7852 int len;
7853
7854 if (*str++ != '@')
7855 return BFD_RELOC_UNUSED;
7856
7857 for (ch = *str, str2 = ident;
7858 (str2 < ident + sizeof (ident) - 1
7859 && (ISALNUM (ch) || ch == '@'));
7860 ch = *++str)
7861 {
7862 *str2++ = ch;
7863 }
7864
7865 *str2 = '\0';
7866 len = str2 - ident;
7867
7868 if (strncmp (ident, "TLSLDO", 6) == 0
7869 && len == 6)
7870 {
7871 /* Now check for identifier@suffix+constant. */
7872 if (*str == '-' || *str == '+')
7873 {
7874 char *orig_line = input_line_pointer;
7875 expressionS new_exp;
7876
7877 input_line_pointer = str;
7878 expression (&new_exp);
7879 if (new_exp.X_op == O_constant)
7880 {
7881 exp_p->X_add_number += new_exp.X_add_number;
7882 str = input_line_pointer;
7883 }
7884
7885 if (&input_line_pointer != str_p)
7886 input_line_pointer = orig_line;
7887 }
7888 *str_p = str;
7889
7890 return BFD_RELOC_68K_TLS_LDO32;
7891 }
7892
7893 return BFD_RELOC_UNUSED;
7894}
7895
7896/* Handles .long <tls_symbol>+0x8000 debug info.
7897 Clobbers input_line_pointer, checks end-of-line.
7898 Adapted from tc-ppc.c:ppc_elf_cons. */
7899static void
7900m68k_elf_cons (int nbytes /* 4=.long */)
7901{
7902 if (is_it_end_of_statement ())
7903 {
7904 demand_empty_rest_of_line ();
7905 return;
7906 }
7907
7908 do
7909 {
7910 expressionS exp;
7911 bfd_reloc_code_real_type reloc;
7912
7913 expression (&exp);
7914 if (exp.X_op == O_symbol
7915 && *input_line_pointer == '@'
7916 && (reloc = m68k_elf_suffix (&input_line_pointer,
7917 &exp)) != BFD_RELOC_UNUSED)
7918 {
7919 reloc_howto_type *reloc_howto;
7920 int size;
7921
7922 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
7923 size = bfd_get_reloc_size (reloc_howto);
7924
7925 if (size > nbytes)
7926 {
992a06ee
AM		 7927 as_bad (ngettext ("%s relocations do not fit in %u byte",
7928 "%s relocations do not fit in %u bytes",
7929 nbytes),
cf869cce
NC		 7930 reloc_howto->name, nbytes);
7931 }
7932 else
7933 {
7934 char *p;
7935 int offset;
7936
7937 p = frag_more (nbytes);
7938 offset = 0;
7939 if (target_big_endian)
7940 offset = nbytes - size;
7941 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
7942 &exp, 0, reloc);
7943 }
7944 }
7945 else
7946 emit_expr (&exp, (unsigned int) nbytes);
7947 }
7948 while (*input_line_pointer++ == ',');
7949
7950 /* Put terminator back into stream. */
7951 input_line_pointer--;
7952 demand_empty_rest_of_line ();
7953}
c04898f8
AS		 7954
7955int
e0471c16 7956tc_m68k_regname_to_dw2regnum (const char *regname)
c04898f8
AS		 7957{
7958 unsigned int regnum;
7959 static const char *const regnames[] =
7960 {
7961 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7962 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7963 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7964 "pc"
7965 };
7966
7967 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7968 if (strcmp (regname, regnames[regnum]) == 0)
7969 return regnum;
7970
7971 return -1;
7972}
7973
7974void
7975tc_m68k_frame_initial_instructions (void)
7976{
7977 static int sp_regno = -1;
7978
7979 if (sp_regno < 0)
7980 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7981
7982 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7983 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7984}
909c7f9c
NC		 7985
7986/* Check and emit error if broken-word handling has failed to fix up a
7987 case-table. This is called from write.c, after doing everything it
7988 knows about how to handle broken words. */
7989
7990void
7991tc_m68k_check_adjusted_broken_word (offsetT new_offset, struct broken_word *brokwP)
7992{
7993 if (new_offset > 32767 || new_offset < -32768)
7994 as_bad_where (brokwP->frag->fr_file, brokwP->frag->fr_line,
7995 _("Adjusted signed .word (%#lx) overflows: `switch'-statement too large."),
7996 (long) new_offset);
7997}
7998
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