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2009-10-12 Tristan Gingold <gingold@adacore.com>
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
CommitLineData
252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
cf869cce 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
5a49b8ac 4 Free Software Foundation, Inc.
252b5132
RH		 5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
ec2655a6 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
252b5132 22
252b5132 23#include "as.h"
3882b010 24#include "safe-ctype.h"
252b5132
RH		 25#include "obstack.h"
26#include "subsegs.h"
f27a3839 27#include "dwarf2dbg.h"
c04898f8 28#include "dw2gencfi.h"
252b5132
RH		 29
30#include "opcode/m68k.h"
31#include "m68k-parse.h"
32
0d96863f
CM		 33#if defined (OBJ_ELF)
34#include "elf/m68k.h"
35#endif
36
31302357
AS		 37#ifdef M68KCOFF
38#include "obj-coff.h"
39#endif
40
cf869cce
NC		 41#ifdef OBJ_ELF
42static void m68k_elf_cons (int);
43#endif
44
252b5132
RH		 45/* This string holds the chars that always start a comment. If the
46 pre-processor is disabled, these aren't very useful. The macro
47 tc_comment_chars points to this. We use this, rather than the
48 usual comment_chars, so that the --bitwise-or option will work. */
49#if defined (TE_SVR4) || defined (TE_DELTA)
50const char *m68k_comment_chars = "|#";
51#else
52const char *m68k_comment_chars = "|";
53#endif
54
55/* This array holds the chars that only start a comment at the beginning of
56 a line. If the line seems to have the form '# 123 filename'
57 .line and .file directives will appear in the pre-processed output */
58/* Note that input_file.c hand checks for '#' at the beginning of the
59 first line of the input file. This is because the compiler outputs
92774660
KH		 60 #NO_APP at the beginning of its output. */
61/* Also note that comments like this one will always work. */
252b5132
RH		 62const char line_comment_chars[] = "#*";
63
63a0b638 64const char line_separator_chars[] = ";";
252b5132 65
36759679 66/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 67const char EXP_CHARS[] = "eE";
252b5132
RH		 68
69/* Chars that mean this number is a floating point constant, as
70 in "0f12.456" or "0d1.2345e12". */
71
5a38dc70 72const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 73
74/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
75 changed in read.c . Ideally it shouldn't have to know about it at all,
76 but nothing is ideal around here. */
77
252b5132
RH		 78/* Are we trying to generate PIC code? If so, absolute references
79 ought to be made into linkage table references or pc-relative
92774660 80 references. Not implemented. For ELF there are other means
252b5132
RH		 81 to denote pic relocations. */
82int flag_want_pic;
83
36759679
NC		 84static int flag_short_refs; /* -l option. */
85static int flag_long_jumps; /* -S option. */
28e7409f 86static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 87
88#ifdef REGISTER_PREFIX_OPTIONAL
89int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
90#else
91int flag_reg_prefix_optional;
92#endif
93
94/* Whether --register-prefix-optional was used on the command line. */
95static int reg_prefix_optional_seen;
96
97/* The floating point coprocessor to use by default. */
98static enum m68k_register m68k_float_copnum = COP1;
99
100/* If this is non-zero, then references to number(%pc) will be taken
101 to refer to number, rather than to %pc + number. */
102static int m68k_abspcadd;
103
104/* If this is non-zero, then the quick forms of the move, add, and sub
105 instructions are used when possible. */
106static int m68k_quick = 1;
107
108/* If this is non-zero, then if the size is not specified for a base
109 or outer displacement, the assembler assumes that the size should
110 be 32 bits. */
111static int m68k_rel32 = 1;
112
113/* This is non-zero if m68k_rel32 was set from the command line. */
114static int m68k_rel32_from_cmdline;
115
116/* The default width to use for an index register when using a base
117 displacement. */
118static enum m68k_size m68k_index_width_default = SIZE_LONG;
119
120/* We want to warn if any text labels are misaligned. In order to get
121 the right line number, we need to record the line number for each
122 label. */
252b5132
RH		 123struct label_line
124{
125 struct label_line *next;
126 symbolS *label;
127 char *file;
128 unsigned int line;
129 int text;
130};
131
132/* The list of labels. */
133
134static struct label_line *labels;
135
136/* The current label. */
137
138static struct label_line *current_label;
139
60fed2d3
NC		 140/* Pointer to list holding the opcodes sorted by name. */
141static struct m68k_opcode const ** m68k_sorted_opcodes;
142
36759679
NC		 143/* Its an arbitrary name: This means I don't approve of it.
144 See flames below. */
252b5132
RH		 145static struct obstack robyn;
146
252b5132
RH		 147struct m68k_incant
148 {
149 const char *m_operands;
150 unsigned long m_opcode;
151 short m_opnum;
152 short m_codenum;
153 int m_arch;
154 struct m68k_incant *m_next;
155 };
156
157#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
158#define gettwo(x) (((x)->m_opcode)&0xffff)
159
2da12c60
NS		 160static const enum m68k_register m68000_ctrl[] = { 0 };
161static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 162 SFC, DFC, USP, VBR,
163 0
164};
2da12c60 165static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 166 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
167 0
168};
2da12c60 169static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
171 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
172 0
173};
2da12c60 174static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 175 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
176 USP, VBR, URP, SRP, PCR,
177 0
178};
2da12c60 179static const enum m68k_register mcf_ctrl[] = {
3e602632 180 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 181 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
182 0
183};
87298967
NS		 184static const enum m68k_register mcf51_ctrl[] = {
185 VBR, CPUCR,
f75192f2
KH		 186 0
187};
78336706
NS		 188static const enum m68k_register mcf5206_ctrl[] = {
189 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 190 0
191};
2da12c60 192static const enum m68k_register mcf5208_ctrl[] = {
78336706 193 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 194 0
195};
96e0bbcc 196static const enum m68k_register mcf5210a_ctrl[] = {
78336706 197 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 198 0
199};
2da12c60 200static const enum m68k_register mcf5213_ctrl[] = {
78336706 201 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 202 0
203};
2da12c60 204static const enum m68k_register mcf5216_ctrl[] = {
78336706 205 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 206 0
207};
46203761
MK		 208static const enum m68k_register mcf5221x_ctrl[] = {
209 VBR, FLASHBAR, RAMBAR, RAMBAR1,
210 0
211};
d5be9593
NS		 212static const enum m68k_register mcf52223_ctrl[] = {
213 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
214 0
215};
96e0bbcc 216static const enum m68k_register mcf52235_ctrl[] = {
b345c8c2 217 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 218 0
219};
220static const enum m68k_register mcf5225_ctrl[] = {
78336706 221 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 222 0
223};
87298967
NS		 224static const enum m68k_register mcf52259_ctrl[] = {
225 VBR, FLASHBAR, RAMBAR, RAMBAR1,
226 0
227};
228static const enum m68k_register mcf52277_ctrl[] = {
229 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
230 0
231};
2da12c60 232static const enum m68k_register mcf5235_ctrl[] = {
78336706 233 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 234 0
235};
2da12c60 236static const enum m68k_register mcf5249_ctrl[] = {
78336706 237 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 238 0
239};
2da12c60
NS		 240static const enum m68k_register mcf5250_ctrl[] = {
241 VBR,
242 0
243};
d5be9593 244static const enum m68k_register mcf5253_ctrl[] = {
def8fc92 245 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
d5be9593
NS		 246 0
247};
2da12c60 248static const enum m68k_register mcf5271_ctrl[] = {
78336706 249 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 250 0
251};
252static const enum m68k_register mcf5272_ctrl[] = {
78336706 253 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 254 0
255};
256static const enum m68k_register mcf5275_ctrl[] = {
78336706 257 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 258 0
259};
260static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 261 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
262 0
263};
87298967 264static const enum m68k_register mcf53017_ctrl[] = {
b345c8c2 265 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
87298967
NS		 266 0
267};
78336706 268static const enum m68k_register mcf5307_ctrl[] = {
87298967 269 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 270 0
271};
272static const enum m68k_register mcf5329_ctrl[] = {
78336706 273 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 274 0
275};
276static const enum m68k_register mcf5373_ctrl[] = {
78336706 277 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 278 0
279};
280static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
283 MBAR, SECMBAR,
284 MPCR /* Multiprocessor Control register */,
285 EDRAMBAR /* Embedded DRAM Base Address Register */,
286 /* Permutation control registers. */
3e602632
NC		 287 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
288 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 289 /* Legacy names */
290 TC /* ASID */, BUSCR /* MMUBAR */,
291 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
292 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 293 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 294 0
295};
def8fc92
KH		 296static const enum m68k_register mcf5407_ctrl[] = {
297 CACR, ASID, ACR0, ACR1, ACR2, ACR3,
298 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
299 /* Legacy names */
300 TC /* ASID */,
301 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
302 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
303 0
304};
9a2e615a
NS		 305static const enum m68k_register mcf54455_ctrl[] = {
306 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
307 VBR, PC, RAMBAR1, MBAR,
308 /* Legacy names */
309 TC /* ASID */, BUSCR /* MMUBAR */,
310 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
311 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
312 0
313};
a8e24a56
NS		 314static const enum m68k_register mcf5475_ctrl[] = {
315 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
316 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
317 /* Legacy names */
318 TC /* ASID */, BUSCR /* MMUBAR */,
319 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 320 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 321 0
322};
323static const enum m68k_register mcf5485_ctrl[] = {
324 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
325 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
326 /* Legacy names */
327 TC /* ASID */, BUSCR /* MMUBAR */,
328 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 329 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 330 0
331};
f7ec513b 332static const enum m68k_register fido_ctrl[] = {
d0fa1372 333 SFC, DFC, USP, VBR, CAC, MBO,
f7ec513b
KH		 334 0
335};
2da12c60 336#define cpu32_ctrl m68010_ctrl
252b5132
RH		 337
338static const enum m68k_register *control_regs;
339
36759679 340/* Internal form of a 68020 instruction. */
252b5132
RH		 341struct m68k_it
342{
343 const char *error;
36759679 344 const char *args; /* List of opcode info. */
252b5132
RH		 345 int numargs;
346
36759679 347 int numo; /* Number of shorts in opcode. */
252b5132
RH		 348 short opcode[11];
349
350 struct m68k_op operands[6];
351
36759679 352 int nexp; /* Number of exprs in use. */
252b5132
RH		 353 struct m68k_exp exprs[4];
354
36759679 355 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 356 struct
357 {
36759679 358 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 359 symbolS *fadd;
360 offsetT foff;
361 int fragty;
362 }
363 fragb[4];
364
36759679 365 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 366 struct
367 {
368 int n;
369 expressionS exp;
370 char wid;
371 char pcrel;
372 /* In a pc relative address the difference between the address
373 of the offset and the address that the offset is relative
374 to. This depends on the addressing mode. Basically this
375 is the value to put in the offset field to address the
376 first byte of the offset, without regarding the special
377 significance of some values (in the branch instruction, for
378 example). */
379 int pcrel_fix;
380#ifdef OBJ_ELF
381 /* Whether this expression needs special pic relocation, and if
382 so, which. */
383 enum pic_relocation pic_reloc;
384#endif
385 }
36759679 386 reloc[5]; /* Five is enough??? */
252b5132
RH		 387};
388
9840d27e 389#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 390#define float_of_arch(x) ((x) & mfloat)
391#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 392#define arch_coldfire_p(x) ((x) & mcfisa_a)
393#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 394
36759679 395/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 396#define HAVE_LONG_DISP(x) \
397 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
398#define HAVE_LONG_CALL(x) \
399 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
400#define HAVE_LONG_COND(x) \
401 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
402#define HAVE_LONG_BRANCH(x) \
403 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
cac27205 404#define LONG_BRANCH_VIA_COND(x) (HAVE_LONG_COND(x) && !HAVE_LONG_BRANCH(x))
252b5132 405
36759679 406static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 407
408#define op(ex) ((ex)->exp.X_op)
409#define adds(ex) ((ex)->exp.X_add_symbol)
410#define subs(ex) ((ex)->exp.X_op_symbol)
411#define offs(ex) ((ex)->exp.X_add_number)
412
36759679 413/* Macros for adding things to the m68k_it struct. */
31302357 414#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 415
36759679
NC		 416/* Like addword, but goes BEFORE general operands. */
417
252b5132 418static void
31302357 419insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 420{
421 int z;
07726851 422 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 423 the_ins.opcode[z] = the_ins.opcode[z - 1];
424 for (z = 0; z < the_ins.nrel; z++)
425 the_ins.reloc[z].n += 2;
252b5132
RH		 426 for (z = 0; z < the_ins.nfrag; z++)
427 the_ins.fragb[z].fragoff++;
8a104df9 428 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 429 the_ins.numo++;
430}
431
432/* The numo+1 kludge is so we can hit the low order byte of the prev word.
433 Blecch. */
434static void
31302357 435add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 436{
31302357
AS		 437 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
438 ? the_ins.numo * 2 - 1
439 : (width == 'b'
440 ? the_ins.numo * 2 + 1
441 : the_ins.numo * 2));
252b5132
RH		 442 the_ins.reloc[the_ins.nrel].exp = exp->exp;
443 the_ins.reloc[the_ins.nrel].wid = width;
444 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
445#ifdef OBJ_ELF
446 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
447#endif
448 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
449}
450
451/* Cause an extra frag to be generated here, inserting up to 10 bytes
452 (that value is chosen in the frag_var call in md_assemble). TYPE
453 is the subtype of the frag to be generated; its primary type is
454 rs_machine_dependent.
455
456 The TYPE parameter is also used by md_convert_frag_1 and
457 md_estimate_size_before_relax. The appropriate type of fixup will
458 be emitted by md_convert_frag_1.
459
460 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
461static void
31302357 462add_frag (symbolS *add, offsetT off, int type)
252b5132 463{
8a104df9
KH		 464 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
465 the_ins.fragb[the_ins.nfrag].fadd = add;
466 the_ins.fragb[the_ins.nfrag].foff = off;
467 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 468}
469
470#define isvar(ex) \
471 (op (ex) != O_constant && op (ex) != O_big)
472
31302357
AS		 473static char *crack_operand (char *str, struct m68k_op *opP);
474static int get_num (struct m68k_exp *exp, int ok);
475static int reverse_16_bits (int in);
476static int reverse_8_bits (int in);
477static void install_gen_operand (int mode, int val);
478static void install_operand (int mode, int val);
479static void s_bss (int);
480static void s_data1 (int);
481static void s_data2 (int);
482static void s_even (int);
483static void s_proc (int);
484static void s_chip (int);
485static void s_fopt (int);
486static void s_opt (int);
487static void s_reg (int);
488static void s_restore (int);
489static void s_save (int);
490static void s_mri_if (int);
491static void s_mri_else (int);
492static void s_mri_endi (int);
493static void s_mri_break (int);
494static void s_mri_next (int);
495static void s_mri_for (int);
496static void s_mri_endf (int);
497static void s_mri_repeat (int);
498static void s_mri_until (int);
499static void s_mri_while (int);
500static void s_mri_endw (int);
266abb8f
NS		 501static void s_m68k_cpu (int);
502static void s_m68k_arch (int);
503
504struct m68k_cpu
505{
506 unsigned long arch; /* Architecture features. */
2da12c60 507 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 508 const char *name; /* Name */
0b2e31dc
NS		 509 int alias; /* Alias for a cannonical name. If 1, then
510 succeeds canonical name, if -1 then
511 succeeds canonical name, if <-1 ||>1 this is a
512 deprecated name, and the next/previous name
513 should be used. */
266abb8f 514};
252b5132 515
266abb8f
NS		 516/* We hold flags for features explicitly enabled and explicitly
517 disabled. */
252b5132 518static int current_architecture;
266abb8f 519static int not_current_architecture;
266abb8f
NS		 520static const struct m68k_cpu *selected_arch;
521static const struct m68k_cpu *selected_cpu;
522static int initialized;
252b5132 523
266abb8f
NS		 524/* Architecture models. */
525static const struct m68k_cpu m68k_archs[] =
526{
2da12c60
NS		 527 {m68000, m68000_ctrl, "68000", 0},
528 {m68010, m68010_ctrl, "68010", 0},
529 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
530 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
531 {m68040, m68040_ctrl, "68040", 0},
532 {m68060, m68060_ctrl, "68060", 0},
533 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 534 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 535 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
536 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
537 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 538 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 539 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
540 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 541 {0,0,NULL, 0}
542};
252b5132 543
87298967
NS		 544/* For -mno-mac we want to turn off all types of mac. */
545static const unsigned no_mac = mcfmac | mcfemac;
546
0b2e31dc
NS		 547/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
548 for either. */
266abb8f
NS		 549static const struct m68k_cpu m68k_extensions[] =
550{
2da12c60
NS		 551 {m68851, NULL, "68851", -1},
552 {m68881, NULL, "68881", -1},
553 {m68881, NULL, "68882", -1},
cf869cce 554
2da12c60 555 {cfloat|m68881, NULL, "float", 0},
cf869cce 556
2da12c60
NS		 557 {mcfhwdiv, NULL, "div", 1},
558 {mcfusp, NULL, "usp", 1},
87298967 559 {mcfmac, (void *)&no_mac, "mac", 1},
2da12c60 560 {mcfemac, NULL, "emac", 1},
cf869cce 561
2da12c60 562 {0,NULL,NULL, 0}
266abb8f
NS		 563};
564
565/* Processor list */
566static const struct m68k_cpu m68k_cpus[] =
567{
2da12c60
NS		 568 {m68000, m68000_ctrl, "68000", 0},
569 {m68000, m68000_ctrl, "68ec000", 1},
570 {m68000, m68000_ctrl, "68hc000", 1},
571 {m68000, m68000_ctrl, "68hc001", 1},
572 {m68000, m68000_ctrl, "68008", 1},
573 {m68000, m68000_ctrl, "68302", 1},
574 {m68000, m68000_ctrl, "68306", 1},
575 {m68000, m68000_ctrl, "68307", 1},
576 {m68000, m68000_ctrl, "68322", 1},
577 {m68000, m68000_ctrl, "68356", 1},
578 {m68010, m68010_ctrl, "68010", 0},
579 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
580 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
581 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
582 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
583 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
584 {m68040, m68040_ctrl, "68040", 0},
585 {m68040, m68040_ctrl, "68ec040", 1},
586 {m68060, m68060_ctrl, "68060", 0},
587 {m68060, m68060_ctrl, "68ec060", 1},
cf869cce 588
2da12c60
NS		 589 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
590 {cpu32|m68881, cpu32_ctrl, "68330", 1},
591 {cpu32|m68881, cpu32_ctrl, "68331", 1},
592 {cpu32|m68881, cpu32_ctrl, "68332", 1},
593 {cpu32|m68881, cpu32_ctrl, "68333", 1},
594 {cpu32|m68881, cpu32_ctrl, "68334", 1},
595 {cpu32|m68881, cpu32_ctrl, "68336", 1},
596 {cpu32|m68881, cpu32_ctrl, "68340", 1},
597 {cpu32|m68881, cpu32_ctrl, "68341", 1},
598 {cpu32|m68881, cpu32_ctrl, "68349", 1},
599 {cpu32|m68881, cpu32_ctrl, "68360", 1},
f75192f2 600
87298967
NS		 601 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51", 0},
602 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51ac", 1},
603 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51cn", 1},
604 {mcfisa_a|mcfisa_c|mcfusp|mcfmac, mcf51_ctrl, "51em", 1},
605 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51jm", 1},
606 {mcfisa_a|mcfisa_c|mcfusp, mcf51_ctrl, "51qe", 1},
cf869cce 607
2da12c60
NS		 608 {mcfisa_a, mcf_ctrl, "5200", 0},
609 {mcfisa_a, mcf_ctrl, "5202", 1},
610 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 611 {mcfisa_a, mcf5206_ctrl, "5206", 1},
cf869cce 612
78336706 613 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
cf869cce 614
2da12c60
NS		 615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
cf869cce 617
96e0bbcc
NS		 618 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
619 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
cf869cce 620
2da12c60
NS		 621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
cf869cce 624
2da12c60
NS		 625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
628
46203761
MK		 629 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5221x_ctrl, "5221x", 0},
630
d5be9593
NS		 631 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
632 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
633
96e0bbcc
NS		 634 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
635 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
636 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
637 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
cf869cce 638
96e0bbcc
NS		 639 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
640 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
cf869cce 641
87298967
NS		 642 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52274", -1},
643 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52277_ctrl, "52277", 0},
644
2da12c60
NS		 645 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
646 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
647 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
648 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
649 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
650
651 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
652 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 653 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
87298967
NS		 654
655 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52252", -1},
656 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52254", -1},
657 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52255", -1},
658 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52256", -1},
659 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52258", -1},
660 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52259_ctrl, "52259", 0},
661
2da12c60
NS		 662 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
663 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
664
665 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
666
667 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
668 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
669
670 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
671 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
672 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
673 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
674
87298967
NS		 675 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53011", -1},
676 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53012", -1},
677 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53013", -1},
678 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53014", -1},
679 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53015", -1},
680 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53016", -1},
681 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf53017_ctrl, "53017", 0},
682
78336706 683 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
2da12c60
NS		 684
685 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
686 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
687 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
688 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
689
690 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
691 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
692 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
693
def8fc92 694 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf5407_ctrl, "5407",0},
9a2e615a
NS		 695
696 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
697 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
698 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
699 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
700 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
701 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
2da12c60 702
a8e24a56
NS		 703 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
704 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
705 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
706 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
707 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
708 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
709 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 710
a8e24a56
NS		 711 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
712 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
713 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
714 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
715 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
716 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
717 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 718
b3768379 719 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 720 {fido_a, fido_ctrl, "fido", 1},
9840d27e 721
2da12c60 722 {0,NULL,NULL, 0}
dc84e067 723 };
252b5132 724
266abb8f
NS		 725static const struct m68k_cpu *m68k_lookup_cpu
726(const char *, const struct m68k_cpu *, int, int *);
727static int m68k_set_arch (const char *, int, int);
728static int m68k_set_cpu (const char *, int, int);
729static int m68k_set_extension (const char *, int, int);
730static void m68k_init_arch (void);
252b5132 731
151337e8
NC		 732/* This is the assembler relaxation table for m68k. m68k is a rich CISC
733 architecture and we have a lot of relaxation modes. */
252b5132 734
151337e8
NC		 735/* Macros used in the relaxation code. */
736#define TAB(x,y) (((x) << 2) + (y))
737#define TABTYPE(x) ((x) >> 2)
738
739/* Relaxation states. */
740#define BYTE 0
741#define SHORT 1
742#define LONG 2
743#define SZ_UNDEF 3
744
745/* Here are all the relaxation modes we support. First we can relax ordinary
746 branches. On 68020 and higher and on CPU32 all branch instructions take
747 three forms, so on these CPUs all branches always remain as such. When we
748 have to expand to the LONG form on a 68000, though, we substitute an
749 absolute jump instead. This is a direct replacement for unconditional
750 branches and a branch over a jump for conditional branches. However, if the
751 user requires PIC and disables this with --pcrel, we can only relax between
752 BYTE and SHORT forms, punting if that isn't enough. This gives us four
753 different relaxation modes for branches: */
754
36759679
NC		 755#define BRANCHBWL 0 /* Branch byte, word, or long. */
756#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
757#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
758#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 759
760/* We also relax coprocessor branches and DBcc's. All CPUs that support
761 coprocessor branches support them in word and long forms, so we have only
762 one relaxation mode for them. DBcc's are word only on all CPUs. We can
763 relax them to the LONG form with a branch-around sequence. This sequence
764 can use a long branch (if available) or an absolute jump (if acceptable).
765 This gives us two relaxation modes. If long branches are not available and
766 absolute jumps are not acceptable, we don't relax DBcc's. */
767
36759679
NC		 768#define FBRANCH 4 /* Coprocessor branch. */
769#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
770#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 771
772/* That's all for instruction relaxation. However, we also relax PC-relative
773 operands. Specifically, we have three operand relaxation modes. On the
774 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
775 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
776 two. Also PC+displacement+index operands in their simple form (with a non-
777 suppressed index without memory indirection) are supported on all CPUs, but
778 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
779 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
780 form of the PC+displacement+index operand. Finally, some absolute operands
781 can be relaxed down to 16-bit PC-relative. */
782
36759679
NC		 783#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
784#define PCINDEX 8 /* PC + displacement + index. */
785#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132 786
cac27205
NC		 787/* This relaxation is required for branches where there is no long
788 branch and we are in pcrel mode. We generate a bne/beq pair. */
789#define BRANCHBWPL 10 /* Branch byte, word or pair of longs
790 */
791
252b5132 792/* Note that calls to frag_var need to specify the maximum expansion
cac27205
NC		 793 needed; this is currently 12 bytes for bne/beq pair. */
794#define FRAG_VAR_SIZE 12
252b5132
RH		 795
796/* The fields are:
797 How far Forward this mode will reach:
798 How far Backward this mode will reach:
799 How many bytes this mode will add to the size of the frag
800 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 801
802 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 803relax_typeS md_relax_table[] =
804{
ac62c346
AM		 805 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
806 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
807 { 0, 0, 4, 0 },
808 { 1, 1, 0, 0 },
809
810 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
811 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
812 { 0, 0, 4, 0 },
813 { 1, 1, 0, 0 },
814
815 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
816 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
817 { 0, 0, 6, 0 },
818 { 1, 1, 0, 0 },
819
820 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
821 { 0, 0, 2, 0 },
822 { 1, 1, 0, 0 },
823 { 1, 1, 0, 0 },
824
36759679 825 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 826 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
827 { 0, 0, 4, 0 },
828 { 1, 1, 0, 0 },
829
36759679 830 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 831 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
832 { 0, 0, 10, 0 },
833 { 1, 1, 0, 0 },
834
36759679 835 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 836 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
837 { 0, 0, 10, 0 },
838 { 1, 1, 0, 0 },
839
36759679 840 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 841 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
842 { 0, 0, 6, 0 },
843 { 1, 1, 0, 0 },
844
845 { 125, -130, 0, TAB (PCINDEX, SHORT) },
846 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
847 { 0, 0, 4, 0 },
848 { 1, 1, 0, 0 },
849
36759679 850 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 851 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
852 { 0, 0, 4, 0 },
853 { 1, 1, 0, 0 },
cac27205
NC		 854
855 { 127, -128, 0, TAB (BRANCHBWPL, SHORT) },
856 { 32767, -32768, 2, TAB (BRANCHBWPL, LONG) },
857 { 0, 0, 10, 0 },
858 { 1, 1, 0, 0 },
252b5132
RH		 859};
860
861/* These are the machine dependent pseudo-ops. These are included so
862 the assembler can work on the output from the SUN C compiler, which
36759679 863 generates these. */
252b5132
RH		 864
865/* This table describes all the machine specific pseudo-ops the assembler
866 has to support. The fields are:
867 pseudo-op name without dot
868 function to call to execute this pseudo-op
36759679 869 Integer arg to pass to the function. */
252b5132
RH		 870const pseudo_typeS md_pseudo_table[] =
871{
872 {"data1", s_data1, 0},
873 {"data2", s_data2, 0},
874 {"bss", s_bss, 0},
875 {"even", s_even, 0},
876 {"skip", s_space, 0},
877 {"proc", s_proc, 0},
878#if defined (TE_SUN3) || defined (OBJ_ELF)
879 {"align", s_align_bytes, 0},
880#endif
881#ifdef OBJ_ELF
882 {"swbeg", s_ignore, 0},
cf869cce 883 {"long", m68k_elf_cons, 4},
252b5132
RH		 884#endif
885 {"extend", float_cons, 'x'},
886 {"ldouble", float_cons, 'x'},
887
266abb8f
NS		 888 {"arch", s_m68k_arch, 0},
889 {"cpu", s_m68k_cpu, 0},
890
252b5132
RH		 891 /* The following pseudo-ops are supported for MRI compatibility. */
892 {"chip", s_chip, 0},
893 {"comline", s_space, 1},
894 {"fopt", s_fopt, 0},
895 {"mask2", s_ignore, 0},
896 {"opt", s_opt, 0},
897 {"reg", s_reg, 0},
898 {"restore", s_restore, 0},
899 {"save", s_save, 0},
900
901 {"if", s_mri_if, 0},
902 {"if.b", s_mri_if, 'b'},
903 {"if.w", s_mri_if, 'w'},
904 {"if.l", s_mri_if, 'l'},
905 {"else", s_mri_else, 0},
906 {"else.s", s_mri_else, 's'},
907 {"else.l", s_mri_else, 'l'},
908 {"endi", s_mri_endi, 0},
909 {"break", s_mri_break, 0},
910 {"break.s", s_mri_break, 's'},
911 {"break.l", s_mri_break, 'l'},
912 {"next", s_mri_next, 0},
913 {"next.s", s_mri_next, 's'},
914 {"next.l", s_mri_next, 'l'},
915 {"for", s_mri_for, 0},
916 {"for.b", s_mri_for, 'b'},
917 {"for.w", s_mri_for, 'w'},
918 {"for.l", s_mri_for, 'l'},
919 {"endf", s_mri_endf, 0},
920 {"repeat", s_mri_repeat, 0},
921 {"until", s_mri_until, 0},
922 {"until.b", s_mri_until, 'b'},
923 {"until.w", s_mri_until, 'w'},
924 {"until.l", s_mri_until, 'l'},
925 {"while", s_mri_while, 0},
926 {"while.b", s_mri_while, 'b'},
927 {"while.w", s_mri_while, 'w'},
928 {"while.l", s_mri_while, 'l'},
929 {"endw", s_mri_endw, 0},
930
931 {0, 0, 0}
932};
933
252b5132 934/* The mote pseudo ops are put into the opcode table, since they
31302357 935 don't start with a . they look like opcodes to gas. */
252b5132 936
5a38dc70 937const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 938{
939
940 {"dcl", cons, 4},
941 {"dc", cons, 2},
942 {"dcw", cons, 2},
943 {"dcb", cons, 1},
944
945 {"dsl", s_space, 4},
946 {"ds", s_space, 2},
947 {"dsw", s_space, 2},
948 {"dsb", s_space, 1},
949
950 {"xdef", s_globl, 0},
951#ifdef OBJ_ELF
952 {"align", s_align_bytes, 0},
953#else
954 {"align", s_align_ptwo, 0},
955#endif
956#ifdef M68KCOFF
957 {"sect", obj_coff_section, 0},
958 {"section", obj_coff_section, 0},
959#endif
960 {0, 0, 0}
961};
962
bd17c2c3
AM		 963/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
964 gives identical results to a 32-bit host. */
965#define TRUNC(X) ((valueT) (X) & 0xffffffff)
966#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
967
968#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
969#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
970#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
971#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
972
973#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
974#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 975#define islong(x) (1)
976
252b5132
RH		 977static char notend_table[256];
978static char alt_notend_table[256];
979#define notend(s) \
980 (! (notend_table[(unsigned char) *s] \
981 || (*s == ':' \
982 && alt_notend_table[(unsigned char) s[1]])))
983
252b5132
RH		 984#ifdef OBJ_ELF
985
c801568a
AM		 986/* Return zero if the reference to SYMBOL from within the same segment may
987 be relaxed. */
988
989/* On an ELF system, we can't relax an externally visible symbol,
990 because it may be overridden by a shared library. However, if
991 TARGET_OS is "elf", then we presume that we are assembling for an
992 embedded system, in which case we don't have to worry about shared
993 libraries, and we can relax any external sym. */
994
995#define relaxable_symbol(symbol) \
6358301e 996 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 997 || S_IS_WEAK (symbol)))
998
252b5132
RH		 999/* Compute the relocation code for a fixup of SIZE bytes, using pc
1000 relative relocation if PCREL is non-zero. PIC says whether a special
1001 pic relocation was requested. */
1002
252b5132 1003static bfd_reloc_code_real_type
31302357 1004get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 1005{
1006 switch (pic)
1007 {
1008 case pic_got_pcrel:
1009 switch (size)
1010 {
1011 case 1:
1012 return BFD_RELOC_8_GOT_PCREL;
1013 case 2:
1014 return BFD_RELOC_16_GOT_PCREL;
1015 case 4:
1016 return BFD_RELOC_32_GOT_PCREL;
1017 }
1018 break;
1019
1020 case pic_got_off:
1021 switch (size)
1022 {
1023 case 1:
1024 return BFD_RELOC_8_GOTOFF;
1025 case 2:
1026 return BFD_RELOC_16_GOTOFF;
1027 case 4:
1028 return BFD_RELOC_32_GOTOFF;
1029 }
1030 break;
1031
1032 case pic_plt_pcrel:
1033 switch (size)
1034 {
1035 case 1:
1036 return BFD_RELOC_8_PLT_PCREL;
1037 case 2:
1038 return BFD_RELOC_16_PLT_PCREL;
1039 case 4:
1040 return BFD_RELOC_32_PLT_PCREL;
1041 }
1042 break;
1043
1044 case pic_plt_off:
1045 switch (size)
1046 {
1047 case 1:
1048 return BFD_RELOC_8_PLTOFF;
1049 case 2:
1050 return BFD_RELOC_16_PLTOFF;
1051 case 4:
1052 return BFD_RELOC_32_PLTOFF;
1053 }
1054 break;
1055
cf869cce
NC		 1056 case pic_tls_gd:
1057 switch (size)
1058 {
1059 case 1:
1060 return BFD_RELOC_68K_TLS_GD8;
1061 case 2:
1062 return BFD_RELOC_68K_TLS_GD16;
1063 case 4:
1064 return BFD_RELOC_68K_TLS_GD32;
1065 }
1066 break;
1067
1068 case pic_tls_ldm:
1069 switch (size)
1070 {
1071 case 1:
1072 return BFD_RELOC_68K_TLS_LDM8;
1073 case 2:
1074 return BFD_RELOC_68K_TLS_LDM16;
1075 case 4:
1076 return BFD_RELOC_68K_TLS_LDM32;
1077 }
1078 break;
1079
1080 case pic_tls_ldo:
1081 switch (size)
1082 {
1083 case 1:
1084 return BFD_RELOC_68K_TLS_LDO8;
1085 case 2:
1086 return BFD_RELOC_68K_TLS_LDO16;
1087 case 4:
1088 return BFD_RELOC_68K_TLS_LDO32;
1089 }
1090 break;
1091
1092 case pic_tls_ie:
1093 switch (size)
1094 {
1095 case 1:
1096 return BFD_RELOC_68K_TLS_IE8;
1097 case 2:
1098 return BFD_RELOC_68K_TLS_IE16;
1099 case 4:
1100 return BFD_RELOC_68K_TLS_IE32;
1101 }
1102 break;
1103
1104 case pic_tls_le:
1105 switch (size)
1106 {
1107 case 1:
1108 return BFD_RELOC_68K_TLS_LE8;
1109 case 2:
1110 return BFD_RELOC_68K_TLS_LE16;
1111 case 4:
1112 return BFD_RELOC_68K_TLS_LE32;
1113 }
1114 break;
1115
252b5132
RH		 1116 case pic_none:
1117 if (pcrel)
1118 {
1119 switch (size)
1120 {
1121 case 1:
1122 return BFD_RELOC_8_PCREL;
1123 case 2:
1124 return BFD_RELOC_16_PCREL;
1125 case 4:
1126 return BFD_RELOC_32_PCREL;
1127 }
1128 }
1129 else
1130 {
1131 switch (size)
1132 {
1133 case 1:
1134 return BFD_RELOC_8;
1135 case 2:
1136 return BFD_RELOC_16;
1137 case 4:
1138 return BFD_RELOC_32;
1139 }
1140 }
1141 }
1142
1143 if (pcrel)
1144 {
1145 if (pic == pic_none)
1146 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1147 else
1148 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1149 }
1150 else
1151 {
1152 if (pic == pic_none)
1153 as_bad (_("Can not do %d byte relocation"), size);
1154 else
1155 as_bad (_("Can not do %d byte pic relocation"), size);
1156 }
1157
1158 return BFD_RELOC_NONE;
1159}
1160
1161/* Here we decide which fixups can be adjusted to make them relative
1162 to the beginning of the section instead of the symbol. Basically
1163 we need to make sure that the dynamic relocations are done
1164 correctly, so in some cases we force the original symbol to be
1165 used. */
1166int
31302357 1167tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1168{
36759679 1169 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1170 switch (fixP->fx_r_type)
1171 {
1172 case BFD_RELOC_8_GOT_PCREL:
1173 case BFD_RELOC_16_GOT_PCREL:
1174 case BFD_RELOC_32_GOT_PCREL:
1175 case BFD_RELOC_8_GOTOFF:
1176 case BFD_RELOC_16_GOTOFF:
1177 case BFD_RELOC_32_GOTOFF:
1178 case BFD_RELOC_8_PLT_PCREL:
1179 case BFD_RELOC_16_PLT_PCREL:
1180 case BFD_RELOC_32_PLT_PCREL:
1181 case BFD_RELOC_8_PLTOFF:
1182 case BFD_RELOC_16_PLTOFF:
1183 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1184 case BFD_RELOC_68K_TLS_GD32:
1185 case BFD_RELOC_68K_TLS_GD16:
1186 case BFD_RELOC_68K_TLS_GD8:
1187 case BFD_RELOC_68K_TLS_LDM32:
1188 case BFD_RELOC_68K_TLS_LDM16:
1189 case BFD_RELOC_68K_TLS_LDM8:
1190 case BFD_RELOC_68K_TLS_LDO32:
1191 case BFD_RELOC_68K_TLS_LDO16:
1192 case BFD_RELOC_68K_TLS_LDO8:
1193 case BFD_RELOC_68K_TLS_IE32:
1194 case BFD_RELOC_68K_TLS_IE16:
1195 case BFD_RELOC_68K_TLS_IE8:
1196 case BFD_RELOC_68K_TLS_LE32:
1197 case BFD_RELOC_68K_TLS_LE16:
1198 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1199 return 0;
1200
1201 case BFD_RELOC_VTABLE_INHERIT:
1202 case BFD_RELOC_VTABLE_ENTRY:
1203 return 0;
1204
1205 default:
1206 return 1;
1207 }
1208}
1209
1210#else /* !OBJ_ELF */
1211
1212#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1213
22184a77
NC		 1214/* PR gas/3041 Weak symbols are not relaxable
1215 because they must be treated as extern. */
1216#define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
c801568a 1217
252b5132
RH		 1218#endif /* OBJ_ELF */
1219
252b5132 1220arelent *
31302357 1221tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1222{
1223 arelent *reloc;
1224 bfd_reloc_code_real_type code;
1225
8ec6253e
NC		 1226 /* If the tcbit is set, then this was a fixup of a negative value
1227 that was never resolved. We do not have a reloc to handle this,
1228 so just return. We assume that other code will have detected this
1229 situation and produced a helpful error message, so we just tell the
1230 user that the reloc cannot be produced. */
252b5132 1231 if (fixp->fx_tcbit)
8ec6253e
NC		 1232 {
1233 if (fixp->fx_addsy)
b091f402
AM		 1234 as_bad_where (fixp->fx_file, fixp->fx_line,
1235 _("Unable to produce reloc against symbol '%s'"),
1236 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1237 return NULL;
1238 }
252b5132
RH		 1239
1240 if (fixp->fx_r_type != BFD_RELOC_NONE)
1241 {
1242 code = fixp->fx_r_type;
1243
1244 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1245 that fixup_segment converted a non-PC relative reloc into a
1246 PC relative reloc. In such a case, we need to convert the
1247 reloc code. */
1248 if (fixp->fx_pcrel)
1249 {
1250 switch (code)
1251 {
1252 case BFD_RELOC_8:
1253 code = BFD_RELOC_8_PCREL;
1254 break;
1255 case BFD_RELOC_16:
1256 code = BFD_RELOC_16_PCREL;
1257 break;
1258 case BFD_RELOC_32:
1259 code = BFD_RELOC_32_PCREL;
1260 break;
1261 case BFD_RELOC_8_PCREL:
1262 case BFD_RELOC_16_PCREL:
1263 case BFD_RELOC_32_PCREL:
1264 case BFD_RELOC_8_GOT_PCREL:
1265 case BFD_RELOC_16_GOT_PCREL:
1266 case BFD_RELOC_32_GOT_PCREL:
1267 case BFD_RELOC_8_GOTOFF:
1268 case BFD_RELOC_16_GOTOFF:
1269 case BFD_RELOC_32_GOTOFF:
1270 case BFD_RELOC_8_PLT_PCREL:
1271 case BFD_RELOC_16_PLT_PCREL:
1272 case BFD_RELOC_32_PLT_PCREL:
1273 case BFD_RELOC_8_PLTOFF:
1274 case BFD_RELOC_16_PLTOFF:
1275 case BFD_RELOC_32_PLTOFF:
cf869cce
NC		 1276 case BFD_RELOC_68K_TLS_GD32:
1277 case BFD_RELOC_68K_TLS_GD16:
1278 case BFD_RELOC_68K_TLS_GD8:
1279 case BFD_RELOC_68K_TLS_LDM32:
1280 case BFD_RELOC_68K_TLS_LDM16:
1281 case BFD_RELOC_68K_TLS_LDM8:
1282 case BFD_RELOC_68K_TLS_LDO32:
1283 case BFD_RELOC_68K_TLS_LDO16:
1284 case BFD_RELOC_68K_TLS_LDO8:
1285 case BFD_RELOC_68K_TLS_IE32:
1286 case BFD_RELOC_68K_TLS_IE16:
1287 case BFD_RELOC_68K_TLS_IE8:
1288 case BFD_RELOC_68K_TLS_LE32:
1289 case BFD_RELOC_68K_TLS_LE16:
1290 case BFD_RELOC_68K_TLS_LE8:
252b5132
RH		 1291 break;
1292 default:
1293 as_bad_where (fixp->fx_file, fixp->fx_line,
1294 _("Cannot make %s relocation PC relative"),
1295 bfd_get_reloc_code_name (code));
1296 }
1297 }
1298 }
1299 else
1300 {
1301#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1302 switch (F (fixp->fx_size, fixp->fx_pcrel))
1303 {
1304#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1305 MAP (1, 0, BFD_RELOC_8);
1306 MAP (2, 0, BFD_RELOC_16);
1307 MAP (4, 0, BFD_RELOC_32);
1308 MAP (1, 1, BFD_RELOC_8_PCREL);
1309 MAP (2, 1, BFD_RELOC_16_PCREL);
1310 MAP (4, 1, BFD_RELOC_32_PCREL);
1311 default:
1312 abort ();
1313 }
1314 }
1315#undef F
1316#undef MAP
1317
1318 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1319 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1320 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1321 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1322#ifndef OBJ_ELF
1323 if (fixp->fx_pcrel)
1324 reloc->addend = fixp->fx_addnumber;
22184a77
NC		 1325 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1326 && fixp->fx_addsy
1327 && S_IS_WEAK (fixp->fx_addsy)
1328 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1329 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1c3f20b4
NC		 1330 to put the symbol offset into frags referencing a weak symbol. */
1331 reloc->addend = fixp->fx_addnumber
1332 - (S_GET_VALUE (fixp->fx_addsy) * 2);
252b5132
RH		 1333 else
1334 reloc->addend = 0;
1335#else
1336 if (!fixp->fx_pcrel)
1337 reloc->addend = fixp->fx_addnumber;
1338 else
1339 reloc->addend = (section->vma
8390138c
AS		 1340 /* Explicit sign extension in case char is
1341 unsigned. */
1342 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1343 + fixp->fx_addnumber
1344 + md_pcrel_from (fixp));
1345#endif
1346
1347 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
9c2799c2 1348 gas_assert (reloc->howto != 0);
252b5132
RH		 1349
1350 return reloc;
1351}
1352
252b5132
RH		 1353/* Handle of the OPCODE hash table. NULL means any use before
1354 m68k_ip_begin() will crash. */
1355static struct hash_control *op_hash;
1356\f
1357/* Assemble an m68k instruction. */
1358
1359static void
31302357 1360m68k_ip (char *instring)
252b5132
RH		 1361{
1362 register char *p;
1363 register struct m68k_op *opP;
1364 register const struct m68k_incant *opcode;
1365 register const char *s;
1366 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1367 char *pdot, *pdotmove;
1368 enum m68k_size siz1, siz2;
1369 char c;
1370 int losing;
1371 int opsfound;
03b13e59 1372 struct m68k_op operands_backup[6];
252b5132
RH		 1373 LITTLENUM_TYPE words[6];
1374 LITTLENUM_TYPE *wordp;
1375 unsigned long ok_arch = 0;
1376
1377 if (*instring == ' ')
36759679 1378 instring++; /* Skip leading whitespace. */
252b5132
RH		 1379
1380 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1381 or exactly 1 space. */
252b5132
RH		 1382 pdot = 0;
1383 for (p = instring; *p != '\0'; p++)
1384 {
1385 if (*p == ' ')
1386 break;
1387 if (*p == '.')
1388 pdot = p;
1389 }
1390
1391 if (p == instring)
1392 {
1393 the_ins.error = _("No operator");
1394 return;
1395 }
1396
1397 /* p now points to the end of the opcode name, probably whitespace.
1398 Make sure the name is null terminated by clobbering the
1399 whitespace, look it up in the hash table, then fix it back.
1400 Remove a dot, first, since the opcode tables have none. */
1401 if (pdot != NULL)
1402 {
1403 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1404 *pdotmove = pdotmove[1];
1405 p--;
1406 }
1407
1408 c = *p;
1409 *p = '\0';
1410 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1411 *p = c;
1412
1413 if (pdot != NULL)
1414 {
1415 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1416 *pdotmove = pdotmove[-1];
1417 *pdot = '.';
1418 ++p;
1419 }
1420
1421 if (opcode == NULL)
1422 {
1423 the_ins.error = _("Unknown operator");
1424 return;
1425 }
1426
36759679 1427 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1428 while (*p == ' ')
1429 ++p;
1430
1431 if (opcode->m_operands == 0)
1432 {
1433 char *old = input_line_pointer;
1434 *old = '\n';
1435 input_line_pointer = p;
36759679 1436 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1437 mote_pseudo_table[opcode->m_opnum].poc_handler
1438 (mote_pseudo_table[opcode->m_opnum].poc_val);
1439 input_line_pointer = old;
1440 *old = 0;
1441
1442 return;
1443 }
1444
1445 if (flag_mri && opcode->m_opnum == 0)
1446 {
1447 /* In MRI mode, random garbage is allowed after an instruction
1448 which accepts no operands. */
1449 the_ins.args = opcode->m_operands;
1450 the_ins.numargs = opcode->m_opnum;
1451 the_ins.numo = opcode->m_codenum;
1452 the_ins.opcode[0] = getone (opcode);
1453 the_ins.opcode[1] = gettwo (opcode);
1454 return;
1455 }
1456
1457 for (opP = &the_ins.operands[0]; *p; opP++)
1458 {
1459 p = crack_operand (p, opP);
1460
1461 if (opP->error)
1462 {
1463 the_ins.error = opP->error;
1464 return;
1465 }
1466 }
1467
1468 opsfound = opP - &the_ins.operands[0];
1469
1470 /* This ugly hack is to support the floating pt opcodes in their
1471 standard form. Essentially, we fake a first enty of type COP#1 */
1472 if (opcode->m_operands[0] == 'I')
1473 {
1474 int n;
1475
1476 for (n = opsfound; n > 0; --n)
1477 the_ins.operands[n] = the_ins.operands[n - 1];
1478
31302357 1479 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1480 the_ins.operands[0].mode = CONTROL;
1481 the_ins.operands[0].reg = m68k_float_copnum;
1482 opsfound++;
1483 }
1484
36759679 1485 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1486 for (losing = 0;;)
1487 {
1488 /* If we didn't get the right number of ops, or we have no
92774660 1489 common model with this pattern then reject this pattern. */
252b5132
RH		 1490
1491 ok_arch |= opcode->m_arch;
1492 if (opsfound != opcode->m_opnum
1493 || ((opcode->m_arch & current_architecture) == 0))
1494 ++losing;
1495 else
1496 {
03b13e59
NC		 1497 int i;
1498
1499 /* Make a copy of the operands of this insn so that
1500 we can modify them safely, should we want to. */
9c2799c2 1501 gas_assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
03b13e59
NC		 1502 for (i = 0; i < opsfound; i++)
1503 operands_backup[i] = the_ins.operands[i];
1504
1505 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1506 *s && !losing;
1507 s += 2, opP++)
1508 {
1509 /* Warning: this switch is huge! */
1510 /* I've tried to organize the cases into this order:
1511 non-alpha first, then alpha by letter. Lower-case
1512 goes directly before uppercase counterpart. */
1513 /* Code with multiple case ...: gets sorted by the lowest
1514 case ... it belongs to. I hope this makes sense. */
1515 switch (*s)
1516 {
1517 case '!':
1518 switch (opP->mode)
1519 {
1520 case IMMED:
1521 case DREG:
1522 case AREG:
1523 case FPREG:
1524 case CONTROL:
1525 case AINC:
1526 case ADEC:
1527 case REGLST:
1528 losing++;
1529 break;
1530 default:
1531 break;
1532 }
1533 break;
1534
1535 case '<':
1536 switch (opP->mode)
1537 {
1538 case DREG:
1539 case AREG:
1540 case FPREG:
1541 case CONTROL:
1542 case IMMED:
1543 case ADEC:
1544 case REGLST:
1545 losing++;
1546 break;
1547 default:
1548 break;
1549 }
1550 break;
1551
1552 case '>':
1553 switch (opP->mode)
1554 {
1555 case DREG:
1556 case AREG:
1557 case FPREG:
1558 case CONTROL:
1559 case IMMED:
1560 case AINC:
1561 case REGLST:
1562 losing++;
1563 break;
1564 case ABSL:
1565 break;
1566 default:
1567 if (opP->reg == PC
1568 || opP->reg == ZPC)
1569 losing++;
1570 break;
1571 }
1572 break;
1573
1574 case 'm':
1575 switch (opP->mode)
1576 {
1577 case DREG:
1578 case AREG:
1579 case AINDR:
1580 case AINC:
1581 case ADEC:
1582 break;
1583 default:
1584 losing++;
1585 }
8a104df9 1586 break;
252b5132
RH		 1587
1588 case 'n':
1589 switch (opP->mode)
1590 {
1591 case DISP:
1592 break;
1593 default:
1594 losing++;
1595 }
8a104df9 1596 break;
252b5132
RH		 1597
1598 case 'o':
1599 switch (opP->mode)
1600 {
1601 case BASE:
1602 case ABSL:
1603 case IMMED:
1604 break;
1605 default:
1606 losing++;
1607 }
8a104df9 1608 break;
252b5132
RH		 1609
1610 case 'p':
1611 switch (opP->mode)
1612 {
1613 case DREG:
1614 case AREG:
1615 case AINDR:
1616 case AINC:
1617 case ADEC:
1618 break;
1619 case DISP:
1620 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1621 losing++;
252b5132
RH		 1622 break;
1623 default:
1624 losing++;
1625 }
8a104df9 1626 break;
252b5132
RH		 1627
1628 case 'q':
1629 switch (opP->mode)
1630 {
1631 case DREG:
1632 case AINDR:
1633 case AINC:
1634 case ADEC:
1635 break;
1636 case DISP:
1637 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1638 losing++;
252b5132
RH		 1639 break;
1640 default:
1641 losing++;
1642 break;
1643 }
8a104df9 1644 break;
252b5132
RH		 1645
1646 case 'v':
1647 switch (opP->mode)
1648 {
1649 case DREG:
1650 case AINDR:
1651 case AINC:
1652 case ADEC:
1653 case ABSL:
1654 break;
1655 case DISP:
1656 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1657 losing++;
252b5132
RH		 1658 break;
1659 default:
1660 losing++;
1661 break;
1662 }
1663 break;
1664
1665 case '#':
1666 if (opP->mode != IMMED)
1667 losing++;
1668 else if (s[1] == 'b'
1669 && ! isvar (&opP->disp)
1670 && (opP->disp.exp.X_op != O_constant
1671 || ! isbyte (opP->disp.exp.X_add_number)))
1672 losing++;
1673 else if (s[1] == 'B'
1674 && ! isvar (&opP->disp)
1675 && (opP->disp.exp.X_op != O_constant
1676 || ! issbyte (opP->disp.exp.X_add_number)))
1677 losing++;
1678 else if (s[1] == 'w'
1679 && ! isvar (&opP->disp)
1680 && (opP->disp.exp.X_op != O_constant
1681 || ! isword (opP->disp.exp.X_add_number)))
1682 losing++;
1683 else if (s[1] == 'W'
1684 && ! isvar (&opP->disp)
1685 && (opP->disp.exp.X_op != O_constant
1686 || ! issword (opP->disp.exp.X_add_number)))
1687 losing++;
1688 break;
1689
1690 case '^':
1691 case 'T':
1692 if (opP->mode != IMMED)
1693 losing++;
1694 break;
1695
1696 case '$':
1697 if (opP->mode == AREG
1698 || opP->mode == CONTROL
1699 || opP->mode == FPREG
1700 || opP->mode == IMMED
1701 || opP->mode == REGLST
1702 || (opP->mode != ABSL
1703 && (opP->reg == PC
1704 || opP->reg == ZPC)))
1705 losing++;
1706 break;
1707
1708 case '%':
1709 if (opP->mode == CONTROL
1710 || opP->mode == FPREG
1711 || opP->mode == REGLST
1712 || opP->mode == IMMED
1713 || (opP->mode != ABSL
1714 && (opP->reg == PC
1715 || opP->reg == ZPC)))
1716 losing++;
1717 break;
1718
1719 case '&':
1720 switch (opP->mode)
1721 {
1722 case DREG:
1723 case AREG:
1724 case FPREG:
1725 case CONTROL:
1726 case IMMED:
1727 case AINC:
1728 case ADEC:
1729 case REGLST:
1730 losing++;
1731 break;
1732 case ABSL:
1733 break;
1734 default:
1735 if (opP->reg == PC
1736 || opP->reg == ZPC)
1737 losing++;
1738 break;
1739 }
1740 break;
1741
1742 case '*':
1743 if (opP->mode == CONTROL
1744 || opP->mode == FPREG
1745 || opP->mode == REGLST)
1746 losing++;
1747 break;
1748
1749 case '+':
1750 if (opP->mode != AINC)
1751 losing++;
1752 break;
1753
1754 case '-':
1755 if (opP->mode != ADEC)
1756 losing++;
1757 break;
1758
1759 case '/':
1760 switch (opP->mode)
1761 {
1762 case AREG:
1763 case CONTROL:
1764 case FPREG:
1765 case AINC:
1766 case ADEC:
1767 case IMMED:
1768 case REGLST:
1769 losing++;
1770 break;
1771 default:
1772 break;
1773 }
1774 break;
1775
1776 case ';':
1777 switch (opP->mode)
1778 {
1779 case AREG:
1780 case CONTROL:
1781 case FPREG:
1782 case REGLST:
1783 losing++;
1784 break;
1785 default:
1786 break;
1787 }
1788 break;
1789
1790 case '?':
1791 switch (opP->mode)
1792 {
1793 case AREG:
1794 case CONTROL:
1795 case FPREG:
1796 case AINC:
1797 case ADEC:
1798 case IMMED:
1799 case REGLST:
1800 losing++;
1801 break;
1802 case ABSL:
1803 break;
1804 default:
1805 if (opP->reg == PC || opP->reg == ZPC)
1806 losing++;
1807 break;
1808 }
1809 break;
1810
1811 case '@':
1812 switch (opP->mode)
1813 {
1814 case AREG:
1815 case CONTROL:
1816 case FPREG:
1817 case IMMED:
1818 case REGLST:
1819 losing++;
1820 break;
1821 default:
1822 break;
1823 }
1824 break;
1825
1826 case '~': /* For now! (JF FOO is this right?) */
1827 switch (opP->mode)
1828 {
1829 case DREG:
1830 case AREG:
1831 case CONTROL:
1832 case FPREG:
1833 case IMMED:
1834 case REGLST:
1835 losing++;
1836 break;
1837 case ABSL:
1838 break;
1839 default:
1840 if (opP->reg == PC
1841 || opP->reg == ZPC)
1842 losing++;
1843 break;
1844 }
1845 break;
1846
1847 case '3':
1848 if (opP->mode != CONTROL
1849 || (opP->reg != TT0 && opP->reg != TT1))
1850 losing++;
1851 break;
1852
1853 case 'A':
1854 if (opP->mode != AREG)
1855 losing++;
1856 break;
1857
1858 case 'a':
1859 if (opP->mode != AINDR)
1860 ++losing;
1861 break;
1862
fd99574b
NC		 1863 case '4':
1864 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1865 && (opP->mode != DISP
1866 || opP->reg < ADDR0
1867 || opP->reg > ADDR7))
1868 ++losing;
1869 break;
1870
252b5132
RH		 1871 case 'B': /* FOO */
1872 if (opP->mode != ABSL
1873 || (flag_long_jumps
1874 && strncmp (instring, "jbsr", 4) == 0))
1875 losing++;
1876 break;
1877
3e602632
NC		 1878 case 'b':
1879 switch (opP->mode)
1880 {
1881 case IMMED:
1882 case ABSL:
1883 case AREG:
1884 case FPREG:
1885 case CONTROL:
1886 case POST:
1887 case PRE:
1888 case REGLST:
1889 losing++;
1890 break;
1891 default:
1892 break;
1893 }
1894 break;
1895
252b5132
RH		 1896 case 'C':
1897 if (opP->mode != CONTROL || opP->reg != CCR)
1898 losing++;
1899 break;
1900
1901 case 'd':
1902 if (opP->mode != DISP
1903 || opP->reg < ADDR0
1904 || opP->reg > ADDR7)
1905 losing++;
1906 break;
1907
1908 case 'D':
1909 if (opP->mode != DREG)
1910 losing++;
1911 break;
1912
6da466c7
ILT		 1913 case 'E':
1914 if (opP->reg != ACC)
1915 losing++;
1916 break;
1917
fd99574b
NC		 1918 case 'e':
1919 if (opP->reg != ACC && opP->reg != ACC1
1920 && opP->reg != ACC2 && opP->reg != ACC3)
1921 losing++;
1922 break;
1923
252b5132
RH		 1924 case 'F':
1925 if (opP->mode != FPREG)
1926 losing++;
1927 break;
1928
6da466c7
ILT		 1929 case 'G':
1930 if (opP->reg != MACSR)
1931 losing++;
1932 break;
1933
fd99574b
NC		 1934 case 'g':
1935 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1936 losing++;
1937 break;
1938
6da466c7
ILT		 1939 case 'H':
1940 if (opP->reg != MASK)
1941 losing++;
1942 break;
1943
252b5132
RH		 1944 case 'I':
1945 if (opP->mode != CONTROL
1946 || opP->reg < COP0
1947 || opP->reg > COP7)
1948 losing++;
1949 break;
1950
fd99574b
NC		 1951 case 'i':
1952 if (opP->mode != LSH && opP->mode != RSH)
1953 losing++;
1954 break;
1955
252b5132
RH		 1956 case 'J':
1957 if (opP->mode != CONTROL
1958 || opP->reg < USP
0b2e31dc
NS		 1959 || opP->reg > last_movec_reg
1960 || !control_regs)
252b5132
RH		 1961 losing++;
1962 else
1963 {
1964 const enum m68k_register *rp;
0b2e31dc 1965
252b5132 1966 for (rp = control_regs; *rp; rp++)
78336706
NS		 1967 {
1968 if (*rp == opP->reg)
1969 break;
1970 /* In most CPUs RAMBAR refers to control reg
1971 c05 (RAMBAR1), but a few CPUs have it
1972 refer to c04 (RAMBAR0). */
1973 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1974 {
1975 opP->reg = RAMBAR_ALT;
1976 break;
1977 }
1978 }
252b5132
RH		 1979 if (*rp == 0)
1980 losing++;
1981 }
1982 break;
1983
1984 case 'k':
1985 if (opP->mode != IMMED)
1986 losing++;
1987 break;
1988
1989 case 'l':
1990 case 'L':
1991 if (opP->mode == DREG
1992 || opP->mode == AREG
1993 || opP->mode == FPREG)
1994 {
1995 if (s[1] == '8')
1996 losing++;
1997 else
1998 {
1999 switch (opP->mode)
2000 {
2001 case DREG:
2002 opP->mask = 1 << (opP->reg - DATA0);
2003 break;
2004 case AREG:
2005 opP->mask = 1 << (opP->reg - ADDR0 + 8);
2006 break;
2007 case FPREG:
2008 opP->mask = 1 << (opP->reg - FP0 + 16);
2009 break;
2010 default:
2011 abort ();
2012 }
2013 opP->mode = REGLST;
2014 }
2015 }
2016 else if (opP->mode == CONTROL)
2017 {
2018 if (s[1] != '8')
2019 losing++;
2020 else
2021 {
2022 switch (opP->reg)
2023 {
2024 case FPI:
2025 opP->mask = 1 << 24;
2026 break;
2027 case FPS:
2028 opP->mask = 1 << 25;
2029 break;
2030 case FPC:
2031 opP->mask = 1 << 26;
2032 break;
2033 default:
2034 losing++;
2035 break;
2036 }
2037 opP->mode = REGLST;
2038 }
2039 }
2040 else if (opP->mode != REGLST)
2041 losing++;
2042 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
2043 losing++;
2044 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
2045 losing++;
2046 break;
2047
2048 case 'M':
2049 if (opP->mode != IMMED)
2050 losing++;
2051 else if (opP->disp.exp.X_op != O_constant
2052 || ! issbyte (opP->disp.exp.X_add_number))
2053 losing++;
2054 else if (! m68k_quick
2055 && instring[3] != 'q'
2056 && instring[4] != 'q')
2057 losing++;
2058 break;
2059
2060 case 'O':
2061 if (opP->mode != DREG
2062 && opP->mode != IMMED
2063 && opP->mode != ABSL)
2064 losing++;
2065 break;
2066
2067 case 'Q':
2068 if (opP->mode != IMMED)
2069 losing++;
2070 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2071 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 2072 losing++;
2073 else if (! m68k_quick
2074 && (strncmp (instring, "add", 3) == 0
2075 || strncmp (instring, "sub", 3) == 0)
2076 && instring[3] != 'q')
2077 losing++;
2078 break;
2079
2080 case 'R':
2081 if (opP->mode != DREG && opP->mode != AREG)
2082 losing++;
2083 break;
2084
2085 case 'r':
2086 if (opP->mode != AINDR
2087 && (opP->mode != BASE
2088 || (opP->reg != 0
2089 && opP->reg != ZADDR0)
2090 || opP->disp.exp.X_op != O_absent
2091 || ((opP->index.reg < DATA0
2092 || opP->index.reg > DATA7)
2093 && (opP->index.reg < ADDR0
2094 || opP->index.reg > ADDR7))
2095 || opP->index.size != SIZE_UNSPEC
2096 || opP->index.scale != 1))
2097 losing++;
2098 break;
2099
2100 case 's':
2101 if (opP->mode != CONTROL
2102 || ! (opP->reg == FPI
2103 || opP->reg == FPS
2104 || opP->reg == FPC))
2105 losing++;
2106 break;
2107
2108 case 'S':
2109 if (opP->mode != CONTROL || opP->reg != SR)
2110 losing++;
2111 break;
2112
2113 case 't':
2114 if (opP->mode != IMMED)
2115 losing++;
2116 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 2117 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 2118 losing++;
2119 break;
2120
2121 case 'U':
2122 if (opP->mode != CONTROL || opP->reg != USP)
2123 losing++;
2124 break;
2125
3e602632
NC		 2126 case 'x':
2127 if (opP->mode != IMMED)
2128 losing++;
2129 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 2130 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
2131 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 2132 losing++;
2133 break;
2134
afa2158f
NS		 2135 case 'j':
2136 if (opP->mode != IMMED)
2137 losing++;
2138 else if (opP->disp.exp.X_op != O_constant
2139 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
2140 losing++;
2141 break;
2142
2143 case 'K':
2144 if (opP->mode != IMMED)
2145 losing++;
2146 else if (opP->disp.exp.X_op != O_constant
2147 || TRUNC (opP->disp.exp.X_add_number) > 511)
2148 losing++;
2149 break;
2150
252b5132
RH		 2151 /* JF these are out of order. We could put them
2152 in order if we were willing to put up with
2153 bunches of #ifdef m68851s in the code.
2154
2155 Don't forget that you need these operands
2156 to use 68030 MMU instructions. */
2157#ifndef NO_68851
36759679 2158 /* Memory addressing mode used by pflushr. */
252b5132
RH		 2159 case '|':
2160 if (opP->mode == CONTROL
2161 || opP->mode == FPREG
2162 || opP->mode == DREG
2163 || opP->mode == AREG
2164 || opP->mode == REGLST)
2165 losing++;
2166 /* We should accept immediate operands, but they
2167 supposedly have to be quad word, and we don't
2168 handle that. I would like to see what a Motorola
2169 assembler does before doing something here. */
2170 if (opP->mode == IMMED)
2171 losing++;
2172 break;
2173
2174 case 'f':
2175 if (opP->mode != CONTROL
2176 || (opP->reg != SFC && opP->reg != DFC))
2177 losing++;
2178 break;
2179
2180 case '0':
2181 if (opP->mode != CONTROL || opP->reg != TC)
2182 losing++;
2183 break;
2184
2185 case '1':
2186 if (opP->mode != CONTROL || opP->reg != AC)
2187 losing++;
2188 break;
2189
2190 case '2':
2191 if (opP->mode != CONTROL
2192 || (opP->reg != CAL
2193 && opP->reg != VAL
2194 && opP->reg != SCC))
2195 losing++;
2196 break;
2197
2198 case 'V':
2199 if (opP->mode != CONTROL
2200 || opP->reg != VAL)
2201 losing++;
2202 break;
2203
2204 case 'W':
2205 if (opP->mode != CONTROL
2206 || (opP->reg != DRP
2207 && opP->reg != SRP
2208 && opP->reg != CRP))
2209 losing++;
2210 break;
2211
3e602632
NC		 2212 case 'w':
2213 switch (opP->mode)
2214 {
2215 case IMMED:
2216 case ABSL:
2217 case AREG:
2218 case DREG:
2219 case FPREG:
2220 case CONTROL:
2221 case POST:
2222 case PRE:
2223 case REGLST:
2224 losing++;
2225 break;
2226 default:
2227 break;
2228 }
2229 break;
2230
252b5132
RH		 2231 case 'X':
2232 if (opP->mode != CONTROL
2233 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2234 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2235 losing++;
2236 break;
2237
2238 case 'Y':
2239 if (opP->mode != CONTROL || opP->reg != PSR)
2240 losing++;
2241 break;
2242
2243 case 'Z':
2244 if (opP->mode != CONTROL || opP->reg != PCSR)
2245 losing++;
2246 break;
2247#endif
2248 case 'c':
2249 if (opP->mode != CONTROL
2250 || (opP->reg != NC
2251 && opP->reg != IC
2252 && opP->reg != DC
2253 && opP->reg != BC))
36759679 2254 losing++;
252b5132
RH		 2255 break;
2256
2257 case '_':
2258 if (opP->mode != ABSL)
2259 ++losing;
2260 break;
2261
6da466c7
ILT		 2262 case 'u':
2263 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2264 losing++;
2265 /* FIXME: kludge instead of fixing parser:
2266 upper/lower registers are *not* CONTROL
92774660 2267 registers, but ordinary ones. */
6da466c7
ILT		 2268 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2269 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2270 opP->mode = DREG;
2271 else
2272 opP->mode = AREG;
2273 break;
2274
3e602632
NC		 2275 case 'y':
2276 if (!(opP->mode == AINDR
31302357
AS		 2277 || (opP->mode == DISP
2278 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2279 losing++;
2280 break;
2281
2282 case 'z':
2283 if (!(opP->mode == AINDR || opP->mode == DISP))
2284 losing++;
2285 break;
2286
252b5132
RH		 2287 default:
2288 abort ();
36759679 2289 }
252b5132
RH		 2290
2291 if (losing)
2292 break;
36759679 2293 }
03b13e59
NC		 2294
2295 /* Since we have found the correct instruction, copy
2296 in the modifications that we may have made. */
2297 if (!losing)
2298 for (i = 0; i < opsfound; i++)
2299 the_ins.operands[i] = operands_backup[i];
36759679 2300 }
252b5132
RH		 2301
2302 if (!losing)
36759679 2303 break;
252b5132
RH		 2304
2305 opcode = opcode->m_next;
2306
2307 if (!opcode)
2308 {
2309 if (ok_arch
2310 && !(ok_arch & current_architecture))
2311 {
6d89cc8f
NS		 2312 const struct m68k_cpu *cpu;
2313 int any = 0;
2314 size_t space = 400;
2315 char *buf = xmalloc (space + 1);
2316 size_t len;
2317 int paren = 1;
2318
2319 the_ins.error = buf;
2320 /* Make sure there's a NUL at the end of the buffer -- strncpy
b2f58c0c 2321 won't write one when it runs out of buffer. */
6d89cc8f
NS		 2322 buf[space] = 0;
2323#define APPEND(STRING) \
2324 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2325
2326 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2327 switch (ok_arch)
2328 {
6b6e92f4 2329 case mcfisa_a:
b2f58c0c 2330 APPEND ("ColdFire ISA_A");
6b6e92f4
NC		 2331 break;
2332 case mcfhwdiv:
b2f58c0c
NC		 2333 APPEND ("ColdFire ");
2334 APPEND (_("hardware divide"));
6b6e92f4
NC		 2335 break;
2336 case mcfisa_aa:
b2f58c0c 2337 APPEND ("ColdFire ISA_A+");
6b6e92f4
NC		 2338 break;
2339 case mcfisa_b:
b2f58c0c 2340 APPEND ("ColdFire ISA_B");
6b6e92f4 2341 break;
8d100c32 2342 case mcfisa_c:
b2f58c0c 2343 APPEND ("ColdFire ISA_C");
8d100c32 2344 break;
3e602632 2345 case cfloat:
b2f58c0c 2346 APPEND ("ColdFire fpu");
3e602632 2347 break;
252b5132 2348 case mfloat:
b2f58c0c 2349 APPEND ("M68K fpu");
252b5132
RH		 2350 break;
2351 case mmmu:
b2f58c0c 2352 APPEND ("M68K mmu");
252b5132
RH		 2353 break;
2354 case m68020up:
b2f58c0c
NC		 2355 APPEND ("68020 ");
2356 APPEND (_("or higher"));
252b5132
RH		 2357 break;
2358 case m68000up:
b2f58c0c
NC		 2359 APPEND ("68000 ");
2360 APPEND (_("or higher"));
252b5132
RH		 2361 break;
2362 case m68010up:
b2f58c0c
NC		 2363 APPEND ("68010 ");
2364 APPEND (_("or higher"));
252b5132
RH		 2365 break;
2366 default:
6d89cc8f
NS		 2367 paren = 0;
2368 }
2369 if (paren)
2370 APPEND (" (");
6b6e92f4 2371
6d89cc8f
NS		 2372 for (cpu = m68k_cpus; cpu->name; cpu++)
2373 if (!cpu->alias && (cpu->arch & ok_arch))
2374 {
2375 const struct m68k_cpu *alias;
869ddf2a
NS		 2376 int seen_master = 0;
2377
6d89cc8f
NS		 2378 if (any)
2379 APPEND (", ");
2380 any = 0;
2381 APPEND (cpu->name);
869ddf2a
NS		 2382 for (alias = cpu; alias != m68k_cpus; alias--)
2383 if (alias[-1].alias >= 0)
2384 break;
2385 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2386 {
869ddf2a
NS		 2387 if (!alias->alias)
2388 seen_master = 1;
2389 else
2390 {
2391 if (any)
2392 APPEND (", ");
2393 else
2394 APPEND (" [");
2395 APPEND (alias->name);
2396 any = 1;
2397 }
6d89cc8f 2398 }
869ddf2a
NS		 2399 if (any)
2400 APPEND ("]");
6d89cc8f 2401 any = 1;
252b5132 2402 }
6d89cc8f
NS		 2403 if (paren)
2404 APPEND (")");
2405#undef APPEND
2406 if (!space)
2407 {
b2f58c0c 2408 /* We ran out of space, so replace the end of the list
6d89cc8f
NS		 2409 with ellipsis. */
2410 buf -= 4;
2411 while (*buf != ' ')
2412 buf--;
2413 strcpy (buf, " ...");
252b5132 2414 }
252b5132
RH		 2415 }
2416 else
2417 the_ins.error = _("operands mismatch");
2418 return;
36759679 2419 }
252b5132
RH		 2420
2421 losing = 0;
2422 }
2423
36759679 2424 /* Now assemble it. */
252b5132
RH		 2425 the_ins.args = opcode->m_operands;
2426 the_ins.numargs = opcode->m_opnum;
2427 the_ins.numo = opcode->m_codenum;
2428 the_ins.opcode[0] = getone (opcode);
2429 the_ins.opcode[1] = gettwo (opcode);
2430
2431 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2432 {
9a2e615a 2433 int have_disp = 0;
cac27205 2434 int use_pl = 0;
9a2e615a 2435
252b5132 2436 /* This switch is a doozy.
31302357 2437 Watch the first step; its a big one! */
252b5132
RH		 2438 switch (s[0])
2439 {
2440
2441 case '*':
2442 case '~':
2443 case '%':
2444 case ';':
2445 case '@':
2446 case '!':
2447 case '&':
2448 case '$':
2449 case '?':
2450 case '/':
2451 case '<':
2452 case '>':
3e602632 2453 case 'b':
252b5132
RH		 2454 case 'm':
2455 case 'n':
2456 case 'o':
2457 case 'p':
2458 case 'q':
2459 case 'v':
3e602632
NC		 2460 case 'w':
2461 case 'y':
2462 case 'z':
fd99574b 2463 case '4':
252b5132
RH		 2464#ifndef NO_68851
2465 case '|':
2466#endif
2467 switch (opP->mode)
2468 {
2469 case IMMED:
2470 tmpreg = 0x3c; /* 7.4 */
2471 if (strchr ("bwl", s[1]))
3e602632 2472 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2473 else
2474 nextword = get_num (&opP->disp, 0);
2475 if (isvar (&opP->disp))
2476 add_fix (s[1], &opP->disp, 0, 0);
2477 switch (s[1])
2478 {
2479 case 'b':
2480 if (!isbyte (nextword))
2481 opP->error = _("operand out of range");
2482 addword (nextword);
2483 baseo = 0;
2484 break;
2485 case 'w':
2486 if (!isword (nextword))
2487 opP->error = _("operand out of range");
2488 addword (nextword);
2489 baseo = 0;
2490 break;
2491 case 'W':
2492 if (!issword (nextword))
2493 opP->error = _("operand out of range");
2494 addword (nextword);
2495 baseo = 0;
2496 break;
2497 case 'l':
2498 addword (nextword >> 16);
2499 addword (nextword);
2500 baseo = 0;
2501 break;
2502
2503 case 'f':
2504 baseo = 2;
2505 outro = 8;
2506 break;
2507 case 'F':
2508 baseo = 4;
2509 outro = 11;
2510 break;
2511 case 'x':
2512 baseo = 6;
2513 outro = 15;
2514 break;
2515 case 'p':
2516 baseo = 6;
2517 outro = -1;
2518 break;
2519 default:
2520 abort ();
2521 }
2522 if (!baseo)
2523 break;
2524
36759679 2525 /* We gotta put out some float. */
252b5132
RH		 2526 if (op (&opP->disp) != O_big)
2527 {
2528 valueT val;
2529 int gencnt;
2530
2531 /* Can other cases happen here? */
2532 if (op (&opP->disp) != O_constant)
2533 abort ();
2534
2535 val = (valueT) offs (&opP->disp);
2536 gencnt = 0;
2537 do
2538 {
2539 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2540 val >>= LITTLENUM_NUMBER_OF_BITS;
2541 ++gencnt;
2542 }
2543 while (val != 0);
2544 offs (&opP->disp) = gencnt;
2545 }
2546 if (offs (&opP->disp) > 0)
2547 {
2548 if (offs (&opP->disp) > baseo)
2549 {
2550 as_warn (_("Bignum too big for %c format; truncated"),
2551 s[1]);
2552 offs (&opP->disp) = baseo;
2553 }
2554 baseo -= offs (&opP->disp);
2555 while (baseo--)
2556 addword (0);
2557 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2558 offs (&opP->disp)--;
2559 --wordp)
2560 addword (*wordp);
2561 break;
2562 }
2563 gen_to_words (words, baseo, (long) outro);
2564 for (wordp = words; baseo--; wordp++)
2565 addword (*wordp);
2566 break;
2567 case DREG:
2568 tmpreg = opP->reg - DATA; /* 0.dreg */
2569 break;
2570 case AREG:
2571 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2572 break;
2573 case AINDR:
2574 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2575 break;
2576 case ADEC:
2577 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2578 break;
2579 case AINC:
2580 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2581 break;
2582 case DISP:
2583
3e602632 2584 nextword = get_num (&opP->disp, 90);
252b5132 2585
580b9172
NC		 2586 /* Convert mode 5 addressing with a zero offset into
2587 mode 2 addressing to reduce the instruction size by a
2588 word. */
2589 if (! isvar (&opP->disp)
2590 && (nextword == 0)
2591 && (opP->disp.size == SIZE_UNSPEC)
2592 && (opP->reg >= ADDR0)
2593 && (opP->reg <= ADDR7))
2594 {
2595 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2596 break;
2597 }
2598
252b5132
RH		 2599 if (opP->reg == PC
2600 && ! isvar (&opP->disp)
2601 && m68k_abspcadd)
2602 {
2603 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2604 opP->disp.exp.X_add_symbol =
2605 section_symbol (absolute_section);
252b5132
RH		 2606 }
2607
36759679 2608 /* Force into index mode. Hope this works. */
252b5132
RH		 2609
2610 /* We do the first bit for 32-bit displacements, and the
2611 second bit for 16 bit ones. It is possible that we
2612 should make the default be WORD instead of LONG, but
2613 I think that'd break GCC, so we put up with a little
2614 inefficiency for the sake of working output. */
2615
2616 if (!issword (nextword)
2617 || (isvar (&opP->disp)
2618 && ((opP->disp.size == SIZE_UNSPEC
2619 && flag_short_refs == 0
2620 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2621 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2622 || opP->disp.size == SIZE_LONG)))
2623 {
2624 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2625 || arch_coldfire_p (current_architecture))
252b5132
RH		 2626 opP->error =
2627 _("displacement too large for this architecture; needs 68020 or higher");
2628 if (opP->reg == PC)
2629 tmpreg = 0x3B; /* 7.3 */
2630 else
2631 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2632 if (isvar (&opP->disp))
2633 {
2634 if (opP->reg == PC)
2635 {
2636 if (opP->disp.size == SIZE_LONG
2637#ifdef OBJ_ELF
2638 /* If the displacement needs pic
2639 relocation it cannot be relaxed. */
2640 || opP->disp.pic_reloc != pic_none
2641#endif
2642 )
2643 {
2644 addword (0x0170);
2645 add_fix ('l', &opP->disp, 1, 2);
2646 }
2647 else
2648 {
2649 add_frag (adds (&opP->disp),
bd17c2c3 2650 SEXT (offs (&opP->disp)),
151337e8 2651 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2652 break;
2653 }
2654 }
2655 else
2656 {
2657 addword (0x0170);
2658 add_fix ('l', &opP->disp, 0, 0);
2659 }
2660 }
2661 else
2662 addword (0x0170);
2663 addword (nextword >> 16);
2664 }
2665 else
2666 {
2667 if (opP->reg == PC)
2668 tmpreg = 0x3A; /* 7.2 */
2669 else
2670 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2671
2672 if (isvar (&opP->disp))
2673 {
2674 if (opP->reg == PC)
2675 {
2676 add_fix ('w', &opP->disp, 1, 0);
2677 }
2678 else
2679 add_fix ('w', &opP->disp, 0, 0);
2680 }
2681 }
2682 addword (nextword);
2683 break;
2684
2685 case POST:
2686 case PRE:
2687 case BASE:
2688 nextword = 0;
3e602632 2689 baseo = get_num (&opP->disp, 90);
252b5132 2690 if (opP->mode == POST || opP->mode == PRE)
3e602632 2691 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2692 /* Figure out the `addressing mode'.
2693 Also turn on the BASE_DISABLE bit, if needed. */
2694 if (opP->reg == PC || opP->reg == ZPC)
2695 {
2696 tmpreg = 0x3b; /* 7.3 */
2697 if (opP->reg == ZPC)
2698 nextword |= 0x80;
2699 }
2700 else if (opP->reg == 0)
2701 {
2702 nextword |= 0x80;
2703 tmpreg = 0x30; /* 6.garbage */
2704 }
2705 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2706 {
2707 nextword |= 0x80;
2708 tmpreg = 0x30 + opP->reg - ZADDR0;
2709 }
2710 else
2711 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2712
2713 siz1 = opP->disp.size;
2714 if (opP->mode == POST || opP->mode == PRE)
2715 siz2 = opP->odisp.size;
2716 else
2717 siz2 = SIZE_UNSPEC;
2718
36759679 2719 /* Index register stuff. */
252b5132
RH		 2720 if (opP->index.reg != 0
2721 && opP->index.reg >= DATA
2722 && opP->index.reg <= ADDR7)
2723 {
2724 nextword |= (opP->index.reg - DATA) << 12;
2725
2726 if (opP->index.size == SIZE_LONG
2727 || (opP->index.size == SIZE_UNSPEC
2728 && m68k_index_width_default == SIZE_LONG))
2729 nextword |= 0x800;
2730
92774660 2731 if ((opP->index.scale != 1
252b5132 2732 && cpu_of_arch (current_architecture) < m68020)
92774660 2733 || (opP->index.scale == 8
3e602632 2734 && (arch_coldfire_p (current_architecture)
6b6e92f4 2735 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2736 {
2737 opP->error =
2738 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2739 }
2740
6da466c7
ILT		 2741 if (arch_coldfire_p (current_architecture)
2742 && opP->index.size == SIZE_WORD)
2743 opP->error = _("invalid index size for coldfire");
2744
252b5132
RH		 2745 switch (opP->index.scale)
2746 {
2747 case 1:
2748 break;
2749 case 2:
2750 nextword |= 0x200;
2751 break;
2752 case 4:
2753 nextword |= 0x400;
2754 break;
2755 case 8:
2756 nextword |= 0x600;
2757 break;
2758 default:
2759 abort ();
2760 }
2761 /* IF its simple,
2762 GET US OUT OF HERE! */
2763
2764 /* Must be INDEX, with an index register. Address
2765 register cannot be ZERO-PC, and either :b was
2766 forced, or we know it will fit. For a 68000 or
2767 68010, force this mode anyways, because the
2768 larger modes aren't supported. */
2769 if (opP->mode == BASE
2770 && ((opP->reg >= ADDR0
2771 && opP->reg <= ADDR7)
2772 || opP->reg == PC))
2773 {
2774 if (siz1 == SIZE_BYTE
2775 || cpu_of_arch (current_architecture) < m68020
6da466c7 2776 || arch_coldfire_p (current_architecture)
252b5132
RH		 2777 || (siz1 == SIZE_UNSPEC
2778 && ! isvar (&opP->disp)
2779 && issbyte (baseo)))
2780 {
2781 nextword += baseo & 0xff;
2782 addword (nextword);
2783 if (isvar (&opP->disp))
2784 {
2785 /* Do a byte relocation. If it doesn't
2786 fit (possible on m68000) let the
2787 fixup processing complain later. */
2788 if (opP->reg == PC)
2789 add_fix ('B', &opP->disp, 1, 1);
2790 else
2791 add_fix ('B', &opP->disp, 0, 0);
2792 }
2793 else if (siz1 != SIZE_BYTE)
2794 {
2795 if (siz1 != SIZE_UNSPEC)
2796 as_warn (_("Forcing byte displacement"));
2797 if (! issbyte (baseo))
2798 opP->error = _("byte displacement out of range");
2799 }
2800
2801 break;
2802 }
2803 else if (siz1 == SIZE_UNSPEC
2804 && opP->reg == PC
2805 && isvar (&opP->disp)
2806 && subs (&opP->disp) == NULL
2807#ifdef OBJ_ELF
2808 /* If the displacement needs pic
2809 relocation it cannot be relaxed. */
2810 && opP->disp.pic_reloc == pic_none
2811#endif
2812 )
2813 {
2814 /* The code in md_convert_frag_1 needs to be
2815 able to adjust nextword. Call frag_grow
2816 to ensure that we have enough space in
2817 the frag obstack to make all the bytes
2818 contiguous. */
2819 frag_grow (14);
8a104df9
KH		 2820 nextword += baseo & 0xff;
2821 addword (nextword);
bd17c2c3
AM		 2822 add_frag (adds (&opP->disp),
2823 SEXT (offs (&opP->disp)),
8a104df9 2824 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2825
2826 break;
8a104df9 2827 }
252b5132
RH		 2828 }
2829 }
2830 else
2831 {
36759679 2832 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2833 if (opP->index.reg >= ZDATA0
2834 && opP->index.reg <= ZDATA7)
2835 nextword |= (opP->index.reg - ZDATA0) << 12;
2836 else if (opP->index.reg >= ZADDR0
2837 || opP->index.reg <= ZADDR7)
2838 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2839 }
2840
2841 /* It isn't simple. */
2842
2843 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2844 || arch_coldfire_p (current_architecture))
252b5132
RH		 2845 opP->error =
2846 _("invalid operand mode for this architecture; needs 68020 or higher");
2847
2848 nextword |= 0x100;
2849 /* If the guy specified a width, we assume that it is
2850 wide enough. Maybe it isn't. If so, we lose. */
2851 switch (siz1)
2852 {
2853 case SIZE_UNSPEC:
2854 if (isvar (&opP->disp)
2855 ? m68k_rel32
2856 : ! issword (baseo))
2857 {
2858 siz1 = SIZE_LONG;
2859 nextword |= 0x30;
2860 }
2861 else if (! isvar (&opP->disp) && baseo == 0)
2862 nextword |= 0x10;
2863 else
2864 {
2865 nextword |= 0x20;
2866 siz1 = SIZE_WORD;
2867 }
2868 break;
2869 case SIZE_BYTE:
2870 as_warn (_(":b not permitted; defaulting to :w"));
2871 /* Fall through. */
2872 case SIZE_WORD:
2873 nextword |= 0x20;
2874 break;
2875 case SIZE_LONG:
2876 nextword |= 0x30;
2877 break;
2878 }
2879
67c1ffbe 2880 /* Figure out inner displacement stuff. */
252b5132
RH		 2881 if (opP->mode == POST || opP->mode == PRE)
2882 {
2883 if (cpu_of_arch (current_architecture) & cpu32)
2884 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2885 switch (siz2)
2886 {
2887 case SIZE_UNSPEC:
2888 if (isvar (&opP->odisp)
2889 ? m68k_rel32
2890 : ! issword (outro))
2891 {
2892 siz2 = SIZE_LONG;
2893 nextword |= 0x3;
2894 }
2895 else if (! isvar (&opP->odisp) && outro == 0)
2896 nextword |= 0x1;
2897 else
2898 {
2899 nextword |= 0x2;
2900 siz2 = SIZE_WORD;
2901 }
2902 break;
2903 case 1:
2904 as_warn (_(":b not permitted; defaulting to :w"));
2905 /* Fall through. */
2906 case 2:
2907 nextword |= 0x2;
2908 break;
2909 case 3:
2910 nextword |= 0x3;
2911 break;
2912 }
2913 if (opP->mode == POST
2914 && (nextword & 0x40) == 0)
2915 nextword |= 0x04;
2916 }
2917 addword (nextword);
2918
2919 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2920 {
2921 if (opP->reg == PC || opP->reg == ZPC)
2922 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2923 else
2924 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2925 }
2926 if (siz1 == SIZE_LONG)
2927 addword (baseo >> 16);
2928 if (siz1 != SIZE_UNSPEC)
2929 addword (baseo);
2930
2931 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2932 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2933 if (siz2 == SIZE_LONG)
2934 addword (outro >> 16);
2935 if (siz2 != SIZE_UNSPEC)
2936 addword (outro);
2937
2938 break;
2939
2940 case ABSL:
3e602632 2941 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2942 switch (opP->disp.size)
2943 {
2944 default:
2945 abort ();
2946 case SIZE_UNSPEC:
2947 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2948 {
2949 tmpreg = 0x38; /* 7.0 */
2950 addword (nextword);
2951 break;
2952 }
252b5132
RH		 2953 if (isvar (&opP->disp)
2954 && !subs (&opP->disp)
2955 && adds (&opP->disp)
2956#ifdef OBJ_ELF
2957 /* If the displacement needs pic relocation it
2958 cannot be relaxed. */
2959 && opP->disp.pic_reloc == pic_none
2960#endif
252b5132
RH		 2961 && !flag_long_jumps
2962 && !strchr ("~%&$?", s[0]))
2963 {
2964 tmpreg = 0x3A; /* 7.2 */
2965 add_frag (adds (&opP->disp),
bd17c2c3 2966 SEXT (offs (&opP->disp)),
151337e8 2967 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2968 break;
2969 }
36759679 2970 /* Fall through into long. */
252b5132
RH		 2971 case SIZE_LONG:
2972 if (isvar (&opP->disp))
2973 add_fix ('l', &opP->disp, 0, 0);
2974
2975 tmpreg = 0x39;/* 7.1 mode */
2976 addword (nextword >> 16);
2977 addword (nextword);
2978 break;
2979
2980 case SIZE_BYTE:
2981 as_bad (_("unsupported byte value; use a different suffix"));
2982 /* Fall through. */
36759679
NC		 2983
2984 case SIZE_WORD:
252b5132
RH		 2985 if (isvar (&opP->disp))
2986 add_fix ('w', &opP->disp, 0, 0);
2987
2988 tmpreg = 0x38;/* 7.0 mode */
2989 addword (nextword);
2990 break;
2991 }
2992 break;
2993 case CONTROL:
2994 case FPREG:
2995 default:
2996 as_bad (_("unknown/incorrect operand"));
bc805888 2997 /* abort (); */
252b5132 2998 }
fd99574b
NC		 2999
3000 /* If s[0] is '4', then this is for the mac instructions
3001 that can have a trailing_ampersand set. If so, set 0x100
3002 bit on tmpreg so install_gen_operand can check for it and
3003 set the appropriate bit (word2, bit 5). */
3004 if (s[0] == '4')
3005 {
3006 if (opP->trailing_ampersand)
3007 tmpreg |= 0x100;
3008 }
252b5132
RH		 3009 install_gen_operand (s[1], tmpreg);
3010 break;
3011
3012 case '#':
3013 case '^':
3014 switch (s[1])
3015 { /* JF: I hate floating point! */
3016 case 'j':
3017 tmpreg = 70;
3018 break;
3019 case '8':
3020 tmpreg = 20;
3021 break;
3022 case 'C':
3023 tmpreg = 50;
3024 break;
3025 case '3':
3026 default:
3e602632 3027 tmpreg = 90;
252b5132
RH		 3028 break;
3029 }
3030 tmpreg = get_num (&opP->disp, tmpreg);
3031 if (isvar (&opP->disp))
3032 add_fix (s[1], &opP->disp, 0, 0);
3033 switch (s[1])
3034 {
3035 case 'b': /* Danger: These do no check for
3036 certain types of overflow.
3037 user beware! */
3038 if (!isbyte (tmpreg))
3039 opP->error = _("out of range");
3040 insop (tmpreg, opcode);
3041 if (isvar (&opP->disp))
3042 the_ins.reloc[the_ins.nrel - 1].n =
3043 (opcode->m_codenum) * 2 + 1;
3044 break;
3045 case 'B':
3046 if (!issbyte (tmpreg))
3047 opP->error = _("out of range");
3048 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
3049 if (isvar (&opP->disp))
3050 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
3051 break;
3052 case 'w':
3053 if (!isword (tmpreg))
3054 opP->error = _("out of range");
3055 insop (tmpreg, opcode);
3056 if (isvar (&opP->disp))
3057 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3058 break;
3059 case 'W':
3060 if (!issword (tmpreg))
3061 opP->error = _("out of range");
3062 insop (tmpreg, opcode);
3063 if (isvar (&opP->disp))
3064 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3065 break;
3066 case 'l':
3067 /* Because of the way insop works, we put these two out
3068 backwards. */
3069 insop (tmpreg, opcode);
3070 insop (tmpreg >> 16, opcode);
3071 if (isvar (&opP->disp))
3072 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
3073 break;
3074 case '3':
3075 tmpreg &= 0xFF;
3076 case '8':
3077 case 'C':
3078 case 'j':
3079 install_operand (s[1], tmpreg);
3080 break;
3081 default:
3082 abort ();
3083 }
3084 break;
3085
3086 case '+':
3087 case '-':
3088 case 'A':
3089 case 'a':
3090 install_operand (s[1], opP->reg - ADDR);
3091 break;
3092
3093 case 'B':
3e602632 3094 tmpreg = get_num (&opP->disp, 90);
9a2e615a 3095
252b5132
RH		 3096 switch (s[1])
3097 {
3098 case 'B':
8390138c 3099 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 3100 break;
3101 case 'W':
3102 add_fix ('w', &opP->disp, 1, 0);
3103 addword (0);
3104 break;
3105 case 'L':
3106 long_branch:
151337e8 3107 the_ins.opcode[0] |= 0xff;
252b5132
RH		 3108 add_fix ('l', &opP->disp, 1, 0);
3109 addword (0);
3110 addword (0);
3111 break;
9a2e615a
NS		 3112 case 'g': /* Conditional branch */
3113 have_disp = HAVE_LONG_CALL (current_architecture);
3114 goto var_branch;
3115
3116 case 'b': /* Unconditional branch */
3117 have_disp = HAVE_LONG_BRANCH (current_architecture);
cac27205 3118 use_pl = LONG_BRANCH_VIA_COND (current_architecture);
9a2e615a
NS		 3119 goto var_branch;
3120
3121 case 's': /* Unconditional subroutine */
3122 have_disp = HAVE_LONG_CALL (current_architecture);
3123
3124 var_branch:
3125 if (subs (&opP->disp) /* We can't relax it. */
252b5132 3126#ifdef OBJ_ELF
9a2e615a
NS		 3127 /* If the displacement needs pic relocation it cannot be
3128 relaxed. */
3129 || opP->disp.pic_reloc != pic_none
252b5132 3130#endif
9a2e615a
NS		 3131 || 0)
3132 {
3133 if (!have_disp)
3134 as_warn (_("Can't use long branches on this architecture"));
3135 goto long_branch;
3136 }
3137
252b5132 3138 /* This could either be a symbol, or an absolute
151337e8
NC		 3139 address. If it's an absolute address, turn it into
3140 an absolute jump right here and keep it out of the
3141 relaxer. */
3142 if (adds (&opP->disp) == 0)
3143 {
3144 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 3145 the_ins.opcode[0] = 0x4EF9;
151337e8 3146 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 3147 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 3148 else /* jCC */
3149 {
3150 the_ins.opcode[0] ^= 0x0100;
3151 the_ins.opcode[0] |= 0x0006;
18566f55 3152 addword (0x4EF9);
151337e8
NC		 3153 }
3154 add_fix ('l', &opP->disp, 0, 0);
3155 addword (0);
3156 addword (0);
3157 break;
3158 }
3159
3160 /* Now we know it's going into the relaxer. Now figure
3161 out which mode. We try in this order of preference:
3162 long branch, absolute jump, byte/word branches only. */
9a2e615a 3163 if (have_disp)
bd17c2c3
AM		 3164 add_frag (adds (&opP->disp),
3165 SEXT (offs (&opP->disp)),
151337e8
NC		 3166 TAB (BRANCHBWL, SZ_UNDEF));
3167 else if (! flag_keep_pcrel)
3168 {
3169 if ((the_ins.opcode[0] == 0x6000)
3170 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 3171 add_frag (adds (&opP->disp),
3172 SEXT (offs (&opP->disp)),
151337e8
NC		 3173 TAB (BRABSJUNC, SZ_UNDEF));
3174 else
bd17c2c3
AM		 3175 add_frag (adds (&opP->disp),
3176 SEXT (offs (&opP->disp)),
151337e8
NC		 3177 TAB (BRABSJCOND, SZ_UNDEF));
3178 }
252b5132 3179 else
bd17c2c3
AM		 3180 add_frag (adds (&opP->disp),
3181 SEXT (offs (&opP->disp)),
cac27205
NC		 3182 (use_pl ? TAB (BRANCHBWPL, SZ_UNDEF)
3183 : TAB (BRANCHBW, SZ_UNDEF)));
252b5132
RH		 3184 break;
3185 case 'w':
3186 if (isvar (&opP->disp))
3187 {
151337e8
NC		 3188 /* Check for DBcc instructions. We can relax them,
3189 but only if we have long branches and/or absolute
3190 jumps. */
3191 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
3192 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3193 || ! flag_keep_pcrel))
252b5132 3194 {
151337e8 3195 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3196 add_frag (adds (&opP->disp),
3197 SEXT (offs (&opP->disp)),
151337e8
NC		 3198 TAB (DBCCLBR, SZ_UNDEF));
3199 else
bd17c2c3
AM		 3200 add_frag (adds (&opP->disp),
3201 SEXT (offs (&opP->disp)),
151337e8 3202 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3203 break;
3204 }
252b5132
RH		 3205 add_fix ('w', &opP->disp, 1, 0);
3206 }
3207 addword (0);
3208 break;
36759679 3209 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3210 add_fix ('l', &opP->disp, 1, 0);
3211 addword (0);
3212 addword (0);
3213 break;
36759679 3214 case 'c': /* Var size Coprocesssor branches. */
151337e8 3215 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3216 {
252b5132
RH		 3217 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3218 add_fix ('l', &opP->disp, 1, 0);
3219 addword (0);
3220 addword (0);
3221 }
151337e8 3222 else
bd17c2c3
AM		 3223 add_frag (adds (&opP->disp),
3224 SEXT (offs (&opP->disp)),
151337e8 3225 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3226 break;
3227 default:
3228 abort ();
3229 }
3230 break;
3231
36759679 3232 case 'C': /* Ignore it. */
252b5132
RH		 3233 break;
3234
36759679 3235 case 'd': /* JF this is a kludge. */
252b5132 3236 install_operand ('s', opP->reg - ADDR);
3e602632 3237 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3238 if (!issword (tmpreg))
3239 {
3240 as_warn (_("Expression out of range, using 0"));
3241 tmpreg = 0;
3242 }
3243 addword (tmpreg);
3244 break;
3245
3246 case 'D':
3247 install_operand (s[1], opP->reg - DATA);
3248 break;
3249
fd99574b
NC		 3250 case 'e': /* EMAC ACCx, reg/reg. */
3251 install_operand (s[1], opP->reg - ACC);
3252 break;
3253
36759679 3254 case 'E': /* Ignore it. */
6da466c7
ILT		 3255 break;
3256
252b5132
RH		 3257 case 'F':
3258 install_operand (s[1], opP->reg - FP0);
3259 break;
3260
fd99574b
NC		 3261 case 'g': /* EMAC ACCEXTx. */
3262 install_operand (s[1], opP->reg - ACCEXT01);
3263 break;
3264
36759679 3265 case 'G': /* Ignore it. */
6da466c7
ILT		 3266 case 'H':
3267 break;
3268
252b5132
RH		 3269 case 'I':
3270 tmpreg = opP->reg - COP0;
3271 install_operand (s[1], tmpreg);
3272 break;
3273
fd99574b
NC		 3274 case 'i': /* MAC/EMAC scale factor. */
3275 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3276 break;
3277
36759679 3278 case 'J': /* JF foo. */
252b5132
RH		 3279 switch (opP->reg)
3280 {
3281 case SFC:
3282 tmpreg = 0x000;
3283 break;
3284 case DFC:
3285 tmpreg = 0x001;
3286 break;
3287 case CACR:
3288 tmpreg = 0x002;
3289 break;
3290 case TC:
a8e24a56 3291 case ASID:
252b5132
RH		 3292 tmpreg = 0x003;
3293 break;
3e602632 3294 case ACR0:
252b5132
RH		 3295 case ITT0:
3296 tmpreg = 0x004;
3297 break;
3e602632 3298 case ACR1:
252b5132
RH		 3299 case ITT1:
3300 tmpreg = 0x005;
3301 break;
3e602632 3302 case ACR2:
252b5132
RH		 3303 case DTT0:
3304 tmpreg = 0x006;
3305 break;
3e602632 3306 case ACR3:
252b5132
RH		 3307 case DTT1:
3308 tmpreg = 0x007;
3309 break;
3310 case BUSCR:
a8e24a56 3311 case MMUBAR:
252b5132
RH		 3312 tmpreg = 0x008;
3313 break;
3314
3315 case USP:
3316 tmpreg = 0x800;
3317 break;
3318 case VBR:
3319 tmpreg = 0x801;
3320 break;
3321 case CAAR:
87298967 3322 case CPUCR:
252b5132
RH		 3323 tmpreg = 0x802;
3324 break;
3325 case MSP:
3326 tmpreg = 0x803;
3327 break;
3328 case ISP:
3329 tmpreg = 0x804;
3330 break;
3331 case MMUSR:
3332 tmpreg = 0x805;
3333 break;
3334 case URP:
3335 tmpreg = 0x806;
3336 break;
3337 case SRP:
3338 tmpreg = 0x807;
3339 break;
3340 case PCR:
3341 tmpreg = 0x808;
3342 break;
3343 case ROMBAR:
a8e24a56 3344 case ROMBAR0:
252b5132
RH		 3345 tmpreg = 0xC00;
3346 break;
3e602632
NC		 3347 case ROMBAR1:
3348 tmpreg = 0xC01;
3349 break;
3350 case FLASHBAR:
252b5132 3351 case RAMBAR0:
78336706 3352 case RAMBAR_ALT:
252b5132
RH		 3353 tmpreg = 0xC04;
3354 break;
3e602632 3355 case RAMBAR:
252b5132
RH		 3356 case RAMBAR1:
3357 tmpreg = 0xC05;
3358 break;
3e602632
NC		 3359 case MPCR:
3360 tmpreg = 0xC0C;
3361 break;
3362 case EDRAMBAR:
3363 tmpreg = 0xC0D;
3364 break;
3365 case MBAR0:
e80e0390 3366 case MBAR2:
3e602632
NC		 3367 case SECMBAR:
3368 tmpreg = 0xC0E;
3369 break;
3370 case MBAR1:
252b5132
RH		 3371 case MBAR:
3372 tmpreg = 0xC0F;
3373 break;
3e602632
NC		 3374 case PCR1U0:
3375 tmpreg = 0xD02;
3376 break;
3377 case PCR1L0:
3378 tmpreg = 0xD03;
3379 break;
3380 case PCR2U0:
3381 tmpreg = 0xD04;
3382 break;
3383 case PCR2L0:
3384 tmpreg = 0xD05;
3385 break;
3386 case PCR3U0:
3387 tmpreg = 0xD06;
3388 break;
3389 case PCR3L0:
3390 tmpreg = 0xD07;
3391 break;
3392 case PCR1L1:
3393 tmpreg = 0xD0A;
3394 break;
3395 case PCR1U1:
3396 tmpreg = 0xD0B;
3397 break;
3398 case PCR2L1:
3399 tmpreg = 0xD0C;
3400 break;
3401 case PCR2U1:
3402 tmpreg = 0xD0D;
3403 break;
3404 case PCR3L1:
3405 tmpreg = 0xD0E;
3406 break;
3407 case PCR3U1:
3408 tmpreg = 0xD0F;
3409 break;
f7ec513b
KH		 3410 case CAC:
3411 tmpreg = 0xFFE;
3412 break;
d0fa1372 3413 case MBO:
f7ec513b
KH		 3414 tmpreg = 0xFFF;
3415 break;
252b5132
RH		 3416 default:
3417 abort ();
3418 }
3419 install_operand (s[1], tmpreg);
3420 break;
3421
3422 case 'k':
3423 tmpreg = get_num (&opP->disp, 55);
3424 install_operand (s[1], tmpreg & 0x7f);
3425 break;
3426
3427 case 'l':
3428 tmpreg = opP->mask;
3429 if (s[1] == 'w')
3430 {
3431 if (tmpreg & 0x7FF0000)
3432 as_bad (_("Floating point register in register list"));
3433 insop (reverse_16_bits (tmpreg), opcode);
3434 }
3435 else
3436 {
3437 if (tmpreg & 0x700FFFF)
3438 as_bad (_("Wrong register in floating-point reglist"));
3439 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3440 }
3441 break;
3442
3443 case 'L':
3444 tmpreg = opP->mask;
3445 if (s[1] == 'w')
3446 {
3447 if (tmpreg & 0x7FF0000)
3448 as_bad (_("Floating point register in register list"));
3449 insop (tmpreg, opcode);
3450 }
3451 else if (s[1] == '8')
3452 {
3453 if (tmpreg & 0x0FFFFFF)
3454 as_bad (_("incorrect register in reglist"));
3455 install_operand (s[1], tmpreg >> 24);
3456 }
3457 else
3458 {
3459 if (tmpreg & 0x700FFFF)
3460 as_bad (_("wrong register in floating-point reglist"));
3461 else
3462 install_operand (s[1], tmpreg >> 16);
3463 }
3464 break;
3465
3466 case 'M':
3467 install_operand (s[1], get_num (&opP->disp, 60));
3468 break;
3469
3470 case 'O':
3471 tmpreg = ((opP->mode == DREG)
8fce3f5e 3472 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3473 : (get_num (&opP->disp, 40) & 0x1F));
3474 install_operand (s[1], tmpreg);
3475 break;
3476
3477 case 'Q':
3478 tmpreg = get_num (&opP->disp, 10);
3479 if (tmpreg == 8)
3480 tmpreg = 0;
3481 install_operand (s[1], tmpreg);
3482 break;
3483
3484 case 'R':
3485 /* This depends on the fact that ADDR registers are eight
3486 more than their corresponding DATA regs, so the result
36759679 3487 will have the ADDR_REG bit set. */
252b5132
RH		 3488 install_operand (s[1], opP->reg - DATA);
3489 break;
3490
3491 case 'r':
3492 if (opP->mode == AINDR)
3493 install_operand (s[1], opP->reg - DATA);
3494 else
3495 install_operand (s[1], opP->index.reg - DATA);
3496 break;
3497
3498 case 's':
3499 if (opP->reg == FPI)
3500 tmpreg = 0x1;
3501 else if (opP->reg == FPS)
3502 tmpreg = 0x2;
3503 else if (opP->reg == FPC)
3504 tmpreg = 0x4;
3505 else
3506 abort ();
3507 install_operand (s[1], tmpreg);
3508 break;
3509
36759679 3510 case 'S': /* Ignore it. */
252b5132
RH		 3511 break;
3512
3513 case 'T':
3514 install_operand (s[1], get_num (&opP->disp, 30));
3515 break;
3516
36759679 3517 case 'U': /* Ignore it. */
252b5132
RH		 3518 break;
3519
3520 case 'c':
3521 switch (opP->reg)
3522 {
3523 case NC:
3524 tmpreg = 0;
3525 break;
3526 case DC:
3527 tmpreg = 1;
3528 break;
3529 case IC:
3530 tmpreg = 2;
3531 break;
3532 case BC:
3533 tmpreg = 3;
3534 break;
3535 default:
3536 as_fatal (_("failed sanity check"));
36759679 3537 } /* switch on cache token. */
252b5132
RH		 3538 install_operand (s[1], tmpreg);
3539 break;
3540#ifndef NO_68851
92774660 3541 /* JF: These are out of order, I fear. */
252b5132
RH		 3542 case 'f':
3543 switch (opP->reg)
3544 {
3545 case SFC:
3546 tmpreg = 0;
3547 break;
3548 case DFC:
3549 tmpreg = 1;
3550 break;
3551 default:
3552 abort ();
3553 }
3554 install_operand (s[1], tmpreg);
3555 break;
3556
3557 case '0':
3558 case '1':
3559 case '2':
3560 switch (opP->reg)
3561 {
3562 case TC:
3563 tmpreg = 0;
3564 break;
3565 case CAL:
3566 tmpreg = 4;
3567 break;
3568 case VAL:
3569 tmpreg = 5;
3570 break;
3571 case SCC:
3572 tmpreg = 6;
3573 break;
3574 case AC:
3575 tmpreg = 7;
3576 break;
3577 default:
3578 abort ();
3579 }
3580 install_operand (s[1], tmpreg);
3581 break;
3582
3583 case 'V':
3584 if (opP->reg == VAL)
3585 break;
3586 abort ();
3587
3588 case 'W':
3589 switch (opP->reg)
3590 {
3591 case DRP:
3592 tmpreg = 1;
3593 break;
3594 case SRP:
3595 tmpreg = 2;
3596 break;
3597 case CRP:
3598 tmpreg = 3;
3599 break;
3600 default:
3601 abort ();
3602 }
3603 install_operand (s[1], tmpreg);
3604 break;
3605
3606 case 'X':
3607 switch (opP->reg)
3608 {
3609 case BAD:
3610 case BAD + 1:
3611 case BAD + 2:
3612 case BAD + 3:
3613 case BAD + 4:
3614 case BAD + 5:
3615 case BAD + 6:
3616 case BAD + 7:
3617 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3618 break;
3619
3620 case BAC:
3621 case BAC + 1:
3622 case BAC + 2:
3623 case BAC + 3:
3624 case BAC + 4:
3625 case BAC + 5:
3626 case BAC + 6:
3627 case BAC + 7:
3628 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3629 break;
3630
3631 default:
3632 abort ();
3633 }
3634 install_operand (s[1], tmpreg);
3635 break;
3636 case 'Y':
3637 know (opP->reg == PSR);
3638 break;
3639 case 'Z':
3640 know (opP->reg == PCSR);
3641 break;
3642#endif /* m68851 */
3643 case '3':
3644 switch (opP->reg)
3645 {
3646 case TT0:
3647 tmpreg = 2;
3648 break;
3649 case TT1:
3650 tmpreg = 3;
3651 break;
3652 default:
3653 abort ();
3654 }
3655 install_operand (s[1], tmpreg);
3656 break;
3657 case 't':
3658 tmpreg = get_num (&opP->disp, 20);
3659 install_operand (s[1], tmpreg);
3660 break;
36759679 3661 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3662 if (isvar (&opP->disp))
3663 add_fix ('l', &opP->disp, 0, 0);
3e602632 3664 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3665 addword (tmpreg >> 16);
3666 addword (tmpreg & 0xFFFF);
3667 break;
6da466c7
ILT		 3668 case 'u':
3669 install_operand (s[1], opP->reg - DATA0L);
3670 opP->reg -= (DATA0L);
36759679 3671 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3672 break;
3e602632
NC		 3673 case 'x':
3674 tmpreg = get_num (&opP->disp, 80);
3675 if (tmpreg == -1)
3676 tmpreg = 0;
3677 install_operand (s[1], tmpreg);
3678 break;
afa2158f
NS		 3679 case 'j':
3680 tmpreg = get_num (&opP->disp, 10);
3681 install_operand (s[1], tmpreg - 1);
3682 break;
3683 case 'K':
3684 tmpreg = get_num (&opP->disp, 65);
3685 install_operand (s[1], tmpreg);
3686 break;
252b5132
RH		 3687 default:
3688 abort ();
3689 }
3690 }
3691
3692 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3693 instruction, ready to be emitted. . . */
252b5132
RH		 3694}
3695
3696static int
31302357 3697reverse_16_bits (int in)
252b5132
RH		 3698{
3699 int out = 0;
3700 int n;
3701
3702 static int mask[16] =
3703 {
3704 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3705 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3706 };
3707 for (n = 0; n < 16; n++)
3708 {
3709 if (in & mask[n])
3710 out |= mask[15 - n];
3711 }
3712 return out;
3713} /* reverse_16_bits() */
3714
3715static int
31302357 3716reverse_8_bits (int in)
252b5132
RH		 3717{
3718 int out = 0;
3719 int n;
3720
3721 static int mask[8] =
3722 {
3723 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3724 };
3725
3726 for (n = 0; n < 8; n++)
3727 {
3728 if (in & mask[n])
3729 out |= mask[7 - n];
3730 }
3731 return out;
3732} /* reverse_8_bits() */
3733
cac27205
NC		 3734/* Cause an extra frag to be generated here, inserting up to
3735 FRAG_VAR_SIZE bytes. TYPE is the subtype of the frag to be
3736 generated; its primary type is rs_machine_dependent.
252b5132
RH		 3737
3738 The TYPE parameter is also used by md_convert_frag_1 and
3739 md_estimate_size_before_relax. The appropriate type of fixup will
3740 be emitted by md_convert_frag_1.
3741
3742 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3743static void
31302357 3744install_operand (int mode, int val)
252b5132
RH		 3745{
3746 switch (mode)
3747 {
3748 case 's':
36759679 3749 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3750 break;
3751 case 'd':
3752 the_ins.opcode[0] |= val << 9;
3753 break;
afa2158f
NS		 3754 case 'E':
3755 the_ins.opcode[1] |= val << 9;
3756 break;
252b5132
RH		 3757 case '1':
3758 the_ins.opcode[1] |= val << 12;
3759 break;
3760 case '2':
3761 the_ins.opcode[1] |= val << 6;
3762 break;
3763 case '3':
3764 the_ins.opcode[1] |= val;
3765 break;
3766 case '4':
3767 the_ins.opcode[2] |= val << 12;
3768 break;
3769 case '5':
3770 the_ins.opcode[2] |= val << 6;
3771 break;
3772 case '6':
3773 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3774 three words long! */
3775 the_ins.numo++;
3776 the_ins.opcode[2] |= val;
3777 break;
3778 case '7':
3779 the_ins.opcode[1] |= val << 7;
3780 break;
3781 case '8':
3782 the_ins.opcode[1] |= val << 10;
3783 break;
3784#ifndef NO_68851
3785 case '9':
3786 the_ins.opcode[1] |= val << 5;
3787 break;
3788#endif
3789
3790 case 't':
3791 the_ins.opcode[1] |= (val << 10) | (val << 7);
3792 break;
3793 case 'D':
3794 the_ins.opcode[1] |= (val << 12) | val;
3795 break;
3796 case 'g':
3797 the_ins.opcode[0] |= val = 0xff;
3798 break;
3799 case 'i':
3800 the_ins.opcode[0] |= val << 9;
3801 break;
3802 case 'C':
3803 the_ins.opcode[1] |= val;
3804 break;
3805 case 'j':
3806 the_ins.opcode[1] |= val;
36759679 3807 the_ins.numo++; /* What a hack. */
252b5132
RH		 3808 break;
3809 case 'k':
3810 the_ins.opcode[1] |= val << 4;
3811 break;
3812 case 'b':
3813 case 'w':
3814 case 'W':
3815 case 'l':
3816 break;
3817 case 'e':
3818 the_ins.opcode[0] |= (val << 6);
3819 break;
3820 case 'L':
3821 the_ins.opcode[1] = (val >> 16);
3822 the_ins.opcode[2] = val & 0xffff;
3823 break;
6da466c7
ILT		 3824 case 'm':
3825 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3826 the_ins.opcode[0] |= ((val & 0x7) << 9);
3827 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3828 break;
fd99574b 3829 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3830 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3831 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3832 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3833 break;
fd99574b 3834 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3835 the_ins.opcode[1] |= val << 12;
3836 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3837 break;
fd99574b 3838 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3839 the_ins.opcode[0] |= (val & 0xF);
3840 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3841 break;
fd99574b 3842 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3843 the_ins.opcode[1] |= (val & 0xF);
3844 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3845 break;
3846 case 'h':
3847 the_ins.opcode[1] |= ((val != 1) << 10);
3848 break;
fd99574b
NC		 3849 case 'F':
3850 the_ins.opcode[0] |= ((val & 0x3) << 9);
3851 break;
3852 case 'f':
3853 the_ins.opcode[0] |= ((val & 0x3) << 0);
3854 break;
be8c092b 3855 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3856 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3857 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3858 break;
be8c092b 3859 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3860 the_ins.opcode[0] |= ((val & 0x1) << 7);
3861 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3862 break;
3863 case 'I':
3864 the_ins.opcode[1] |= ((val & 0x3) << 9);
3865 break;
3866 case ']':
3867 the_ins.opcode[0] |= (val & 0x1) <<10;
3868 break;
252b5132
RH		 3869 case 'c':
3870 default:
3871 as_fatal (_("failed sanity check."));
3872 }
6b6e92f4 3873}
252b5132
RH		 3874
3875static void
31302357 3876install_gen_operand (int mode, int val)
252b5132
RH		 3877{
3878 switch (mode)
3879 {
fd99574b
NC		 3880 case '/': /* Special for mask loads for mac/msac insns with
3881 possible mask; trailing_ampersend set in bit 8. */
3882 the_ins.opcode[0] |= (val & 0x3f);
3883 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3884 break;
252b5132
RH		 3885 case 's':
3886 the_ins.opcode[0] |= val;
3887 break;
3888 case 'd':
3889 /* This is a kludge!!! */
3890 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3891 break;
3892 case 'b':
3893 case 'w':
3894 case 'l':
3895 case 'f':
3896 case 'F':
3897 case 'x':
3898 case 'p':
3899 the_ins.opcode[0] |= val;
3900 break;
36759679 3901 /* more stuff goes here. */
252b5132
RH		 3902 default:
3903 as_fatal (_("failed sanity check."));
3904 }
6b6e92f4 3905}
252b5132 3906
6b6e92f4
NC		 3907/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3908 then deal with the bitfield hack. */
252b5132
RH		 3909
3910static char *
31302357 3911crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3912{
3913 register int parens;
3914 register int c;
3915 register char *beg_str;
3916 int inquote = 0;
3917
3918 if (!str)
3919 {
3920 return str;
3921 }
3922 beg_str = str;
3923 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3924 {
3925 if (! inquote)
3926 {
3927 if (*str == '(')
3928 parens++;
3929 else if (*str == ')')
3930 {
3931 if (!parens)
36759679 3932 { /* ERROR. */
252b5132
RH		 3933 opP->error = _("Extra )");
3934 return str;
3935 }
3936 --parens;
3937 }
3938 }
3939 if (flag_mri && *str == '\'')
3940 inquote = ! inquote;
3941 }
3942 if (!*str && parens)
36759679 3943 { /* ERROR. */
252b5132
RH		 3944 opP->error = _("Missing )");
3945 return str;
3946 }
3947 c = *str;
3948 *str = '\0';
3949 if (m68k_ip_op (beg_str, opP) != 0)
3950 {
3951 *str = c;
3952 return str;
3953 }
3954 *str = c;
3955 if (c == '}')
36759679 3956 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3957 if (c)
3958 {
3959 c = *++str;
3960 if (!c)
3961 as_bad (_("Missing operand"));
3962 }
3963
3964 /* Detect MRI REG symbols and convert them to REGLSTs. */
3965 if (opP->mode == CONTROL && (int)opP->reg < 0)
3966 {
3967 opP->mode = REGLST;
3968 opP->mask = ~(int)opP->reg;
3969 opP->reg = 0;
3970 }
3971
3972 return str;
3973}
3974
3975/* This is the guts of the machine-dependent assembler. STR points to a
3976 machine dependent instruction. This function is supposed to emit
3977 the frags/bytes it assembles to.
3978 */
3979
3980static void
31302357 3981insert_reg (const char *regname, int regnum)
252b5132
RH		 3982{
3983 char buf[100];
3984 int i;
3985
3986#ifdef REGISTER_PREFIX
3987 if (!flag_reg_prefix_optional)
3988 {
3989 buf[0] = REGISTER_PREFIX;
3990 strcpy (buf + 1, regname);
3991 regname = buf;
3992 }
3993#endif
3994
3995 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3996 &zero_address_frag));
3997
3998 for (i = 0; regname[i]; i++)
3882b010 3999 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 4000 buf[i] = '\0';
4001
4002 symbol_table_insert (symbol_new (buf, reg_section, regnum,
4003 &zero_address_frag));
4004}
4005
4006struct init_entry
4007 {
4008 const char *name;
4009 int number;
4010 };
4011
4012static const struct init_entry init_table[] =
4013{
4014 { "d0", DATA0 },
4015 { "d1", DATA1 },
4016 { "d2", DATA2 },
4017 { "d3", DATA3 },
4018 { "d4", DATA4 },
4019 { "d5", DATA5 },
4020 { "d6", DATA6 },
4021 { "d7", DATA7 },
4022 { "a0", ADDR0 },
4023 { "a1", ADDR1 },
4024 { "a2", ADDR2 },
4025 { "a3", ADDR3 },
4026 { "a4", ADDR4 },
4027 { "a5", ADDR5 },
4028 { "a6", ADDR6 },
4029 { "fp", ADDR6 },
4030 { "a7", ADDR7 },
4031 { "sp", ADDR7 },
4032 { "ssp", ADDR7 },
4033 { "fp0", FP0 },
4034 { "fp1", FP1 },
4035 { "fp2", FP2 },
4036 { "fp3", FP3 },
4037 { "fp4", FP4 },
4038 { "fp5", FP5 },
4039 { "fp6", FP6 },
4040 { "fp7", FP7 },
4041 { "fpi", FPI },
4042 { "fpiar", FPI },
4043 { "fpc", FPI },
4044 { "fps", FPS },
4045 { "fpsr", FPS },
4046 { "fpc", FPC },
4047 { "fpcr", FPC },
4048 { "control", FPC },
4049 { "status", FPS },
4050 { "iaddr", FPI },
4051
4052 { "cop0", COP0 },
4053 { "cop1", COP1 },
4054 { "cop2", COP2 },
4055 { "cop3", COP3 },
4056 { "cop4", COP4 },
4057 { "cop5", COP5 },
4058 { "cop6", COP6 },
4059 { "cop7", COP7 },
4060 { "pc", PC },
4061 { "zpc", ZPC },
4062 { "sr", SR },
4063
4064 { "ccr", CCR },
4065 { "cc", CCR },
4066
6da466c7 4067 { "acc", ACC },
fd99574b
NC		 4068 { "acc0", ACC },
4069 { "acc1", ACC1 },
4070 { "acc2", ACC2 },
4071 { "acc3", ACC3 },
4072 { "accext01", ACCEXT01 },
4073 { "accext23", ACCEXT23 },
6da466c7
ILT		 4074 { "macsr", MACSR },
4075 { "mask", MASK },
4076
36759679
NC		 4077 /* Control registers. */
4078 { "sfc", SFC }, /* Source Function Code. */
252b5132 4079 { "sfcr", SFC },
36759679 4080 { "dfc", DFC }, /* Destination Function Code. */
252b5132 4081 { "dfcr", DFC },
36759679
NC		 4082 { "cacr", CACR }, /* Cache Control Register. */
4083 { "caar", CAAR }, /* Cache Address Register. */
87298967 4084 { "cpucr", CPUCR }, /* CPU Control Register. */
252b5132 4085
36759679
NC		 4086 { "usp", USP }, /* User Stack Pointer. */
4087 { "vbr", VBR }, /* Vector Base Register. */
4088 { "msp", MSP }, /* Master Stack Pointer. */
4089 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 4090
36759679
NC		 4091 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
4092 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
4093 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
4094 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 4095
4096 /* 68ec040 versions of same */
36759679
NC		 4097 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
4098 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
4099 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
4100 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 4101
a8e24a56 4102 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 4103 manual indicated that the order is 2,3,0,1, but Ken Rose
4104 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 4105 { "acr0", ACR0 }, /* Access Control Unit 0. */
4106 { "acr1", ACR1 }, /* Access Control Unit 1. */
4107 { "acr2", ACR2 }, /* Access Control Unit 2. */
4108 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 4109
36759679 4110 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 4111 { "tcr", TC },
a8e24a56 4112 { "asid", ASID },
252b5132 4113
36759679
NC		 4114 { "mmusr", MMUSR }, /* MMU Status Register. */
4115 { "srp", SRP }, /* User Root Pointer. */
4116 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 4117
4118 { "buscr", BUSCR },
a8e24a56 4119 { "mmubar", MMUBAR },
252b5132
RH		 4120 { "pcr", PCR },
4121
36759679
NC		 4122 { "rombar", ROMBAR }, /* ROM Base Address Register. */
4123 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
4124 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
4125 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 4126
4127 { "mbar0", MBAR0 }, /* mcfv4e registers. */
4128 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 4129 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 4130 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
4131 { "mpcr", MPCR }, /* mcfv4e registers. */
4132 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
4133 { "secmbar", SECMBAR }, /* mcfv4e registers. */
4134 { "asid", TC }, /* mcfv4e registers. */
4135 { "mmubar", BUSCR }, /* mcfv4e registers. */
4136 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
4137 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
4138 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
4139 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
4140 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
4141 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
4142 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
4143 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
4144 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
4145 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
4146 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
4147 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
4148
4149 { "flashbar", FLASHBAR }, /* mcf528x registers. */
4150 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 4151
4152 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b
KH		 4153
4154 { "cac", CAC }, /* fido registers. */
d0fa1372
KH		 4155 { "mbb", MBO }, /* fido registers (obsolete). */
4156 { "mbo", MBO }, /* fido registers. */
36759679 4157 /* End of control registers. */
252b5132
RH		 4158
4159 { "ac", AC },
4160 { "bc", BC },
4161 { "cal", CAL },
4162 { "crp", CRP },
4163 { "drp", DRP },
4164 { "pcsr", PCSR },
4165 { "psr", PSR },
4166 { "scc", SCC },
4167 { "val", VAL },
4168 { "bad0", BAD0 },
4169 { "bad1", BAD1 },
4170 { "bad2", BAD2 },
4171 { "bad3", BAD3 },
4172 { "bad4", BAD4 },
4173 { "bad5", BAD5 },
4174 { "bad6", BAD6 },
4175 { "bad7", BAD7 },
4176 { "bac0", BAC0 },
4177 { "bac1", BAC1 },
4178 { "bac2", BAC2 },
4179 { "bac3", BAC3 },
4180 { "bac4", BAC4 },
4181 { "bac5", BAC5 },
4182 { "bac6", BAC6 },
4183 { "bac7", BAC7 },
4184
4185 { "ic", IC },
4186 { "dc", DC },
4187 { "nc", NC },
4188
4189 { "tt0", TT0 },
4190 { "tt1", TT1 },
36759679 4191 /* 68ec030 versions of same. */
252b5132
RH		 4192 { "ac0", TT0 },
4193 { "ac1", TT1 },
36759679 4194 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 4195 { "acusr", PSR },
4196
4197 /* Suppressed data and address registers. */
4198 { "zd0", ZDATA0 },
4199 { "zd1", ZDATA1 },
4200 { "zd2", ZDATA2 },
4201 { "zd3", ZDATA3 },
4202 { "zd4", ZDATA4 },
4203 { "zd5", ZDATA5 },
4204 { "zd6", ZDATA6 },
4205 { "zd7", ZDATA7 },
4206 { "za0", ZADDR0 },
4207 { "za1", ZADDR1 },
4208 { "za2", ZADDR2 },
4209 { "za3", ZADDR3 },
4210 { "za4", ZADDR4 },
4211 { "za5", ZADDR5 },
4212 { "za6", ZADDR6 },
4213 { "za7", ZADDR7 },
4214
92774660 4215 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4216 { "d0l", DATA0L },
4217 { "d1l", DATA1L },
4218 { "d2l", DATA2L },
4219 { "d3l", DATA3L },
4220 { "d4l", DATA4L },
4221 { "d5l", DATA5L },
4222 { "d6l", DATA6L },
4223 { "d7l", DATA7L },
4224
4225 { "a0l", ADDR0L },
4226 { "a1l", ADDR1L },
4227 { "a2l", ADDR2L },
4228 { "a3l", ADDR3L },
4229 { "a4l", ADDR4L },
4230 { "a5l", ADDR5L },
4231 { "a6l", ADDR6L },
4232 { "a7l", ADDR7L },
4233
4234 { "d0u", DATA0U },
4235 { "d1u", DATA1U },
4236 { "d2u", DATA2U },
4237 { "d3u", DATA3U },
4238 { "d4u", DATA4U },
4239 { "d5u", DATA5U },
4240 { "d6u", DATA6U },
4241 { "d7u", DATA7U },
4242
4243 { "a0u", ADDR0U },
4244 { "a1u", ADDR1U },
4245 { "a2u", ADDR2U },
4246 { "a3u", ADDR3U },
4247 { "a4u", ADDR4U },
4248 { "a5u", ADDR5U },
4249 { "a6u", ADDR6U },
4250 { "a7u", ADDR7U },
4251
252b5132
RH		 4252 { 0, 0 }
4253};
4254
4255static void
31302357 4256init_regtable (void)
252b5132
RH		 4257{
4258 int i;
4259 for (i = 0; init_table[i].name; i++)
4260 insert_reg (init_table[i].name, init_table[i].number);
4261}
4262
252b5132 4263void
31302357 4264md_assemble (char *str)
252b5132
RH		 4265{
4266 const char *er;
4267 short *fromP;
4268 char *toP = NULL;
4269 int m, n = 0;
4270 char *to_beg_P;
4271 int shorts_this_frag;
4272 fixS *fixP;
4273
266abb8f
NS		 4274 if (!selected_cpu && !selected_arch)
4275 {
4276 /* We've not selected an architecture yet. Set the default
4277 now. We do this lazily so that an initial .cpu or .arch directive
4278 can specify. */
4279 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4280 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4281 }
4282 if (!initialized)
4283 m68k_init_arch ();
4284
252b5132
RH		 4285 /* In MRI mode, the instruction and operands are separated by a
4286 space. Anything following the operands is a comment. The label
4287 has already been removed. */
4288 if (flag_mri)
4289 {
4290 char *s;
4291 int fields = 0;
4292 int infield = 0;
4293 int inquote = 0;
4294
4295 for (s = str; *s != '\0'; s++)
4296 {
4297 if ((*s == ' ' || *s == '\t') && ! inquote)
4298 {
4299 if (infield)
4300 {
4301 ++fields;
4302 if (fields >= 2)
4303 {
4304 *s = '\0';
4305 break;
4306 }
4307 infield = 0;
4308 }
4309 }
4310 else
4311 {
4312 if (! infield)
4313 infield = 1;
4314 if (*s == '\'')
4315 inquote = ! inquote;
4316 }
4317 }
4318 }
4319
31302357 4320 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4321 m68k_ip (str);
4322 er = the_ins.error;
4323 if (!er)
4324 {
4325 for (n = 0; n < the_ins.numargs; n++)
4326 if (the_ins.operands[n].error)
4327 {
4328 er = the_ins.operands[n].error;
4329 break;
4330 }
4331 }
4332 if (er)
4333 {
4334 as_bad (_("%s -- statement `%s' ignored"), er, str);
4335 return;
4336 }
4337
4338 /* If there is a current label, record that it marks an instruction. */
4339 if (current_label != NULL)
4340 {
4341 current_label->text = 1;
4342 current_label = NULL;
4343 }
4344
f27a3839
AS		 4345#ifdef OBJ_ELF
4346 /* Tie dwarf2 debug info to the address at the start of the insn. */
4347 dwarf2_emit_insn (0);
4348#endif
4349
252b5132
RH		 4350 if (the_ins.nfrag == 0)
4351 {
36759679 4352 /* No frag hacking involved; just put it out. */
252b5132
RH		 4353 toP = frag_more (2 * the_ins.numo);
4354 fromP = &the_ins.opcode[0];
4355 for (m = the_ins.numo; m; --m)
4356 {
4357 md_number_to_chars (toP, (long) (*fromP), 2);
4358 toP += 2;
4359 fromP++;
4360 }
36759679 4361 /* Put out symbol-dependent info. */
252b5132
RH		 4362 for (m = 0; m < the_ins.nrel; m++)
4363 {
4364 switch (the_ins.reloc[m].wid)
4365 {
4366 case 'B':
4367 n = 1;
4368 break;
4369 case 'b':
4370 n = 1;
4371 break;
4372 case '3':
4373 n = 1;
4374 break;
4375 case 'w':
4376 case 'W':
4377 n = 2;
4378 break;
4379 case 'l':
4380 n = 4;
4381 break;
4382 default:
4383 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4384 the_ins.reloc[m].wid);
4385 }
4386
4387 fixP = fix_new_exp (frag_now,
4388 ((toP - frag_now->fr_literal)
4389 - the_ins.numo * 2 + the_ins.reloc[m].n),
4390 n,
4391 &the_ins.reloc[m].exp,
4392 the_ins.reloc[m].pcrel,
4393 get_reloc_code (n, the_ins.reloc[m].pcrel,
4394 the_ins.reloc[m].pic_reloc));
4395 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4396 if (the_ins.reloc[m].wid == 'B')
4397 fixP->fx_signed = 1;
4398 }
4399 return;
4400 }
4401
36759679 4402 /* There's some frag hacking. */
fbe572f9
AM		 4403 {
4404 /* Calculate the max frag size. */
4405 int wid;
4406
4407 wid = 2 * the_ins.fragb[0].fragoff;
4408 for (n = 1; n < the_ins.nfrag; n++)
4409 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4410 /* frag_var part. */
cac27205 4411 wid += FRAG_VAR_SIZE;
fbe572f9
AM		 4412 /* Make sure the whole insn fits in one chunk, in particular that
4413 the var part is attached, as we access one byte before the
4414 variable frag for byte branches. */
4415 frag_grow (wid);
4416 }
4417
252b5132
RH		 4418 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4419 {
4420 int wid;
4421
4422 if (n == 0)
4423 wid = 2 * the_ins.fragb[n].fragoff;
4424 else
4425 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4426 toP = frag_more (wid);
4427 to_beg_P = toP;
4428 shorts_this_frag = 0;
4429 for (m = wid / 2; m; --m)
4430 {
4431 md_number_to_chars (toP, (long) (*fromP), 2);
4432 toP += 2;
4433 fromP++;
4434 shorts_this_frag++;
4435 }
4436 for (m = 0; m < the_ins.nrel; m++)
4437 {
4438 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4439 {
4440 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4441 break;
4442 }
4443 wid = the_ins.reloc[m].wid;
4444 if (wid == 0)
4445 continue;
4446 the_ins.reloc[m].wid = 0;
4447 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4448
4449 fixP = fix_new_exp (frag_now,
4450 ((toP - frag_now->fr_literal)
4451 - the_ins.numo * 2 + the_ins.reloc[m].n),
4452 wid,
4453 &the_ins.reloc[m].exp,
4454 the_ins.reloc[m].pcrel,
4455 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4456 the_ins.reloc[m].pic_reloc));
4457 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4458 }
cac27205 4459 (void) frag_var (rs_machine_dependent, FRAG_VAR_SIZE, 0,
252b5132
RH		 4460 (relax_substateT) (the_ins.fragb[n].fragty),
4461 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4462 }
4463 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4464 shorts_this_frag = 0;
4465 if (n)
4466 {
055d1eb0 4467 toP = frag_more (n * 2);
252b5132
RH		 4468 while (n--)
4469 {
4470 md_number_to_chars (toP, (long) (*fromP), 2);
4471 toP += 2;
4472 fromP++;
4473 shorts_this_frag++;
4474 }
4475 }
4476 for (m = 0; m < the_ins.nrel; m++)
4477 {
4478 int wid;
4479
4480 wid = the_ins.reloc[m].wid;
4481 if (wid == 0)
4482 continue;
4483 the_ins.reloc[m].wid = 0;
4484 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4485
4486 fixP = fix_new_exp (frag_now,
4487 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4488 - shorts_this_frag * 2),
4489 wid,
4490 &the_ins.reloc[m].exp,
4491 the_ins.reloc[m].pcrel,
4492 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4493 the_ins.reloc[m].pic_reloc));
4494 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4495 }
4496}
4497
60fed2d3
NC		 4498/* Comparison function used by qsort to rank the opcode entries by name. */
4499
4500static int
4501m68k_compare_opcode (const void * v1, const void * v2)
4502{
4503 struct m68k_opcode * op1, * op2;
4504 int ret;
4505
03b13e59
NC		 4506 if (v1 == v2)
4507 return 0;
4508
60fed2d3
NC		 4509 op1 = *(struct m68k_opcode **) v1;
4510 op2 = *(struct m68k_opcode **) v2;
4511
4512 /* Compare the two names. If different, return the comparison.
4513 If the same, return the order they are in the opcode table. */
4514 ret = strcmp (op1->name, op2->name);
4515 if (ret)
4516 return ret;
4517 if (op1 < op2)
4518 return -1;
03b13e59 4519 return 1;
60fed2d3
NC		 4520}
4521
252b5132 4522void
60fed2d3 4523md_begin (void)
252b5132 4524{
60fed2d3
NC		 4525 const struct m68k_opcode *ins;
4526 struct m68k_incant *hack, *slak;
4527 const char *retval = 0; /* Empty string, or error msg text. */
4528 int i;
4529
4530 /* Set up hash tables with 68000 instructions.
4531 similar to what the vax assembler does. */
252b5132
RH		 4532 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4533 a copy of it at runtime, adding in the information we want but isn't
4534 there. I think it'd be better to have an awk script hack the table
4535 at compile time. Or even just xstr the table and use it as-is. But
4536 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4537 names. */
4538
252b5132
RH		 4539 if (flag_mri)
4540 {
4541 flag_reg_prefix_optional = 1;
4542 m68k_abspcadd = 1;
4543 if (! m68k_rel32_from_cmdline)
4544 m68k_rel32 = 0;
4545 }
4546
60fed2d3
NC		 4547 /* First sort the opcode table into alphabetical order to seperate
4548 the order that the assembler wants to see the opcodes from the
4549 order that the disassembler wants to see them. */
4550 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4551 if (!m68k_sorted_opcodes)
4552 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4553 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4554
4555 for (i = m68k_numopcodes; i--;)
4556 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4557
4558 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4559 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4560
252b5132
RH		 4561 op_hash = hash_new ();
4562
4563 obstack_begin (&robyn, 4000);
4564 for (i = 0; i < m68k_numopcodes; i++)
4565 {
78aff5a5 4566 hack = slak = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4567 do
4568 {
60fed2d3
NC		 4569 ins = m68k_sorted_opcodes[i];
4570
afa2158f
NS		 4571 /* We must enter all insns into the table, because .arch and
4572 .cpu directives can change things. */
252b5132 4573 slak->m_operands = ins->args;
252b5132
RH		 4574 slak->m_arch = ins->arch;
4575 slak->m_opcode = ins->opcode;
afa2158f
NS		 4576
4577 /* In most cases we can determine the number of opcode words
4578 by checking the second word of the mask. Unfortunately
4579 some instructions have 2 opcode words, but no fixed bits
4580 in the second word. A leading dot in the operands
4581 string also indicates 2 opcodes. */
4582 if (*slak->m_operands == '.')
4583 {
4584 slak->m_operands++;
4585 slak->m_codenum = 2;
4586 }
4587 else if (ins->match & 0xffffL)
4588 slak->m_codenum = 2;
4589 else
4590 slak->m_codenum = 1;
4591 slak->m_opnum = strlen (slak->m_operands) / 2;
4592
252b5132 4593 if (i + 1 != m68k_numopcodes
60fed2d3 4594 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4595 {
60fed2d3 4596 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4597 i++;
4598 }
4599 else
4600 slak->m_next = 0;
4601 slak = slak->m_next;
4602 }
4603 while (slak);
4604
4605 retval = hash_insert (op_hash, ins->name, (char *) hack);
4606 if (retval)
4607 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4608 }
4609
4610 for (i = 0; i < m68k_numaliases; i++)
4611 {
4612 const char *name = m68k_opcode_aliases[i].primary;
4613 const char *alias = m68k_opcode_aliases[i].alias;
5a49b8ac 4614 void *val = hash_find (op_hash, name);
60fed2d3 4615
252b5132
RH		 4616 if (!val)
4617 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4618 retval = hash_insert (op_hash, alias, val);
4619 if (retval)
4620 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4621 }
4622
4623 /* In MRI mode, all unsized branches are variable sized. Normally,
4624 they are word sized. */
4625 if (flag_mri)
4626 {
4627 static struct m68k_opcode_alias mri_aliases[] =
4628 {
4629 { "bhi", "jhi", },
4630 { "bls", "jls", },
4631 { "bcc", "jcc", },
4632 { "bcs", "jcs", },
4633 { "bne", "jne", },
4634 { "beq", "jeq", },
4635 { "bvc", "jvc", },
4636 { "bvs", "jvs", },
4637 { "bpl", "jpl", },
4638 { "bmi", "jmi", },
4639 { "bge", "jge", },
4640 { "blt", "jlt", },
4641 { "bgt", "jgt", },
4642 { "ble", "jle", },
4643 { "bra", "jra", },
4644 { "bsr", "jbsr", },
4645 };
4646
8fce3f5e
AM		 4647 for (i = 0;
4648 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4649 i++)
252b5132
RH		 4650 {
4651 const char *name = mri_aliases[i].primary;
4652 const char *alias = mri_aliases[i].alias;
5a49b8ac 4653 void *val = hash_find (op_hash, name);
60fed2d3 4654
252b5132
RH		 4655 if (!val)
4656 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4657 retval = hash_jam (op_hash, alias, val);
4658 if (retval)
4659 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4660 }
4661 }
4662
8fce3f5e 4663 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4664 {
4665 notend_table[i] = 0;
4666 alt_notend_table[i] = 0;
4667 }
60fed2d3 4668
252b5132
RH		 4669 notend_table[','] = 1;
4670 notend_table['{'] = 1;
4671 notend_table['}'] = 1;
4672 alt_notend_table['a'] = 1;
4673 alt_notend_table['A'] = 1;
4674 alt_notend_table['d'] = 1;
4675 alt_notend_table['D'] = 1;
4676 alt_notend_table['#'] = 1;
4677 alt_notend_table['&'] = 1;
4678 alt_notend_table['f'] = 1;
4679 alt_notend_table['F'] = 1;
4680#ifdef REGISTER_PREFIX
4681 alt_notend_table[REGISTER_PREFIX] = 1;
4682#endif
4683
4684 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4685 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4686 alt_notend_table['('] = 1;
4687
4688 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4689 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4690 alt_notend_table['@'] = 1;
4691
4692 /* We need to put digits in alt_notend_table to handle
60fed2d3 4693 bfextu %d0{24:1},%d0 */
252b5132
RH		 4694 alt_notend_table['0'] = 1;
4695 alt_notend_table['1'] = 1;
4696 alt_notend_table['2'] = 1;
4697 alt_notend_table['3'] = 1;
4698 alt_notend_table['4'] = 1;
4699 alt_notend_table['5'] = 1;
4700 alt_notend_table['6'] = 1;
4701 alt_notend_table['7'] = 1;
4702 alt_notend_table['8'] = 1;
4703 alt_notend_table['9'] = 1;
4704
4705#ifndef MIT_SYNTAX_ONLY
4706 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4707 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4708 {
4709 int n = 0;
60fed2d3 4710
252b5132
RH		 4711 while (mote_pseudo_table[n].poc_name)
4712 {
60fed2d3 4713 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4714 hash_insert (op_hash,
4715 mote_pseudo_table[n].poc_name, (char *) hack);
4716 hack->m_operands = 0;
4717 hack->m_opnum = n;
4718 n++;
4719 }
4720 }
4721#endif
4722
4723 init_regtable ();
4724
4725#ifdef OBJ_ELF
4726 record_alignment (text_section, 2);
4727 record_alignment (data_section, 2);
4728 record_alignment (bss_section, 2);
4729#endif
4730}
4731
252b5132
RH		 4732\f
4733/* This is called when a label is defined. */
4734
4735void
31302357 4736m68k_frob_label (symbolS *sym)
252b5132
RH		 4737{
4738 struct label_line *n;
4739
4740 n = (struct label_line *) xmalloc (sizeof *n);
4741 n->next = labels;
4742 n->label = sym;
4743 as_where (&n->file, &n->line);
4744 n->text = 0;
4745 labels = n;
4746 current_label = n;
07a53e5c
RH		 4747
4748#ifdef OBJ_ELF
4749 dwarf2_emit_label (sym);
4750#endif
252b5132
RH		 4751}
4752
4753/* This is called when a value that is not an instruction is emitted. */
4754
4755void
31302357 4756m68k_flush_pending_output (void)
252b5132
RH		 4757{
4758 current_label = NULL;
4759}
4760
4761/* This is called at the end of the assembly, when the final value of
4762 the label is known. We warn if this is a text symbol aligned at an
4763 odd location. */
4764
4765void
31302357 4766m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4767{
4768 if (S_GET_SEGMENT (sym) == reg_section
4769 && (int) S_GET_VALUE (sym) < 0)
4770 {
4771 S_SET_SEGMENT (sym, absolute_section);
4772 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4773 }
4774 else if ((S_GET_VALUE (sym) & 1) != 0)
4775 {
4776 struct label_line *l;
4777
4778 for (l = labels; l != NULL; l = l->next)
4779 {
4780 if (l->label == sym)
4781 {
4782 if (l->text)
4783 as_warn_where (l->file, l->line,
4784 _("text label `%s' aligned to odd boundary"),
4785 S_GET_NAME (sym));
4786 break;
4787 }
4788 }
4789 }
4790}
4791\f
4792/* This is called if we go in or out of MRI mode because of the .mri
4793 pseudo-op. */
4794
4795void
31302357 4796m68k_mri_mode_change (int on)
252b5132
RH		 4797{
4798 if (on)
4799 {
4800 if (! flag_reg_prefix_optional)
4801 {
4802 flag_reg_prefix_optional = 1;
4803#ifdef REGISTER_PREFIX
4804 init_regtable ();
4805#endif
4806 }
4807 m68k_abspcadd = 1;
4808 if (! m68k_rel32_from_cmdline)
4809 m68k_rel32 = 0;
4810 }
4811 else
4812 {
4813 if (! reg_prefix_optional_seen)
4814 {
4815#ifdef REGISTER_PREFIX_OPTIONAL
4816 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4817#else
4818 flag_reg_prefix_optional = 0;
4819#endif
4820#ifdef REGISTER_PREFIX
4821 init_regtable ();
4822#endif
4823 }
4824 m68k_abspcadd = 0;
4825 if (! m68k_rel32_from_cmdline)
4826 m68k_rel32 = 1;
4827 }
4828}
4829
252b5132 4830char *
31302357 4831md_atof (int type, char *litP, int *sizeP)
252b5132 4832{
499ac353 4833 return ieee_md_atof (type, litP, sizeP, TRUE);
252b5132
RH		 4834}
4835
4836void
31302357 4837md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4838{
4839 number_to_chars_bigendian (buf, val, n);
4840}
4841
94f592af 4842void
55cf6793 4843md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4844{
bbe8ef22 4845 offsetT val = *valP;
252b5132
RH		 4846 addressT upper_limit;
4847 offsetT lower_limit;
4848
4849 /* This is unnecessary but it convinces the native rs6000 compiler
4850 to generate the code we want. */
4851 char *buf = fixP->fx_frag->fr_literal;
4852 buf += fixP->fx_where;
36759679 4853 /* End ibm compiler workaround. */
252b5132 4854
bd17c2c3 4855 val = SEXT (val);
252b5132 4856
94f592af
NC		 4857 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4858 fixP->fx_done = 1;
4859
252b5132
RH		 4860#ifdef OBJ_ELF
4861 if (fixP->fx_addsy)
4862 {
4863 memset (buf, 0, fixP->fx_size);
36759679 4864 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4865
4866 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4867 && !S_IS_DEFINED (fixP->fx_addsy)
4868 && !S_IS_WEAK (fixP->fx_addsy))
4869 S_SET_WEAK (fixP->fx_addsy);
cf869cce
NC		 4870
4871 switch (fixP->fx_r_type)
4872 {
4873 case BFD_RELOC_68K_TLS_GD32:
4874 case BFD_RELOC_68K_TLS_GD16:
4875 case BFD_RELOC_68K_TLS_GD8:
4876 case BFD_RELOC_68K_TLS_LDM32:
4877 case BFD_RELOC_68K_TLS_LDM16:
4878 case BFD_RELOC_68K_TLS_LDM8:
4879 case BFD_RELOC_68K_TLS_LDO32:
4880 case BFD_RELOC_68K_TLS_LDO16:
4881 case BFD_RELOC_68K_TLS_LDO8:
4882 case BFD_RELOC_68K_TLS_IE32:
4883 case BFD_RELOC_68K_TLS_IE16:
4884 case BFD_RELOC_68K_TLS_IE8:
4885 case BFD_RELOC_68K_TLS_LE32:
4886 case BFD_RELOC_68K_TLS_LE16:
4887 case BFD_RELOC_68K_TLS_LE8:
4888 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4889 break;
4890
4891 default:
4892 break;
4893 }
4894
252b5132
RH		 4895 return;
4896 }
22184a77 4897#elif defined(OBJ_AOUT)
1c3f20b4 4898 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
22184a77
NC		 4899 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4900 {
4901 memset (buf, 0, fixP->fx_size);
1c3f20b4 4902 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
22184a77
NC		 4903 return;
4904 }
252b5132
RH		 4905#endif
4906
252b5132
RH		 4907 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4908 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4909 return;
252b5132
RH		 4910
4911 switch (fixP->fx_size)
4912 {
94f592af
NC		 4913 /* The cast to offsetT below are necessary to make code
4914 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4915 case 1:
4916 *buf++ = val;
4917 upper_limit = 0x7f;
4918 lower_limit = - (offsetT) 0x80;
4919 break;
4920 case 2:
4921 *buf++ = (val >> 8);
4922 *buf++ = val;
4923 upper_limit = 0x7fff;
4924 lower_limit = - (offsetT) 0x8000;
4925 break;
4926 case 4:
4927 *buf++ = (val >> 24);
4928 *buf++ = (val >> 16);
4929 *buf++ = (val >> 8);
4930 *buf++ = val;
4931 upper_limit = 0x7fffffff;
36759679 4932 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4933 break;
4934 default:
4935 BAD_CASE (fixP->fx_size);
4936 }
4937
4938 /* Fix up a negative reloc. */
4939 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4940 {
4941 fixP->fx_addsy = fixP->fx_subsy;
4942 fixP->fx_subsy = NULL;
4943 fixP->fx_tcbit = 1;
4944 }
4945
4946 /* For non-pc-relative values, it's conceivable we might get something
4947 like "0xff" for a byte field. So extend the upper part of the range
4948 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4949 so that we can do any range checking at all. */
4950 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4951 upper_limit = upper_limit * 2 + 1;
4952
4953 if ((addressT) val > upper_limit
4954 && (val > 0 || val < lower_limit))
2b878742
NS		 4955 as_bad_where (fixP->fx_file, fixP->fx_line,
4956 _("value %ld out of range"), (long)val);
252b5132
RH		 4957
4958 /* A one byte PC-relative reloc means a short branch. We can't use
4959 a short branch with a value of 0 or -1, because those indicate
4960 different opcodes (branches with longer offsets). fixup_segment
4961 in write.c may have clobbered fx_pcrel, so we need to examine the
4962 reloc type. */
4963 if ((fixP->fx_pcrel
7be1c489 4964 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4965 && fixP->fx_size == 1
4966 && (fixP->fx_addsy == NULL
4967 || S_IS_DEFINED (fixP->fx_addsy))
4968 && (val == 0 || val == -1))
2b878742
NS		 4969 as_bad_where (fixP->fx_file, fixP->fx_line,
4970 _("invalid byte branch offset"));
252b5132
RH		 4971}
4972
252b5132
RH		 4973/* *fragP has been relaxed to its final size, and now needs to have
4974 the bytes inside it modified to conform to the new size There is UGLY
4975 MAGIC here. ..
4976 */
4977static void
31302357 4978md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4979{
4980 long disp;
2b878742 4981 fixS *fixP = NULL;
252b5132
RH		 4982
4983 /* Address in object code of the displacement. */
4984 register int object_address = fragP->fr_fix + fragP->fr_address;
4985
4986 /* Address in gas core of the place to store the displacement. */
4987 /* This convinces the native rs6000 compiler to generate the code we
92774660 4988 want. */
252b5132
RH		 4989 register char *buffer_address = fragP->fr_literal;
4990 buffer_address += fragP->fr_fix;
36759679 4991 /* End ibm compiler workaround. */
252b5132
RH		 4992
4993 /* The displacement of the address, from current location. */
4994 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4995 disp = (disp + fragP->fr_offset) - object_address;
4996
252b5132
RH		 4997 switch (fragP->fr_subtype)
4998 {
151337e8
NC		 4999 case TAB (BRANCHBWL, BYTE):
5000 case TAB (BRABSJUNC, BYTE):
5001 case TAB (BRABSJCOND, BYTE):
5002 case TAB (BRANCHBW, BYTE):
cac27205 5003 case TAB (BRANCHBWPL, BYTE):
252b5132
RH		 5004 know (issbyte (disp));
5005 if (disp == 0)
b091f402
AM		 5006 as_bad_where (fragP->fr_file, fragP->fr_line,
5007 _("short branch with zero offset: use :w"));
151337e8 5008 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5009 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5010 fixP->fx_pcrel_adjust = -1;
252b5132 5011 break;
151337e8
NC		 5012 case TAB (BRANCHBWL, SHORT):
5013 case TAB (BRABSJUNC, SHORT):
5014 case TAB (BRABSJCOND, SHORT):
5015 case TAB (BRANCHBW, SHORT):
cac27205 5016 case TAB (BRANCHBWPL, SHORT):
252b5132 5017 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 5018 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5019 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5020 fragP->fr_fix += 2;
5021 break;
5022 case TAB (BRANCHBWL, LONG):
5023 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 5024 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5025 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 5026 fragP->fr_fix += 4;
252b5132 5027 break;
cac27205
NC		 5028 case TAB (BRANCHBWPL, LONG):
5029 /* Here we are converting an unconditional branch into a pair of
5030 conditional branches, in order to get the range. */
5031 fragP->fr_opcode[0] = 0x66; /* bne */
5032 fragP->fr_opcode[1] = 0xFF;
5033 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5034 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5035 fixP->fx_file = fragP->fr_file;
5036 fixP->fx_line = fragP->fr_line;
5037 fragP->fr_fix += 4; /* Skip first offset */
5038 buffer_address += 4;
5039 *buffer_address++ = 0x67; /* beq */
5040 *buffer_address++ = 0xff;
5041 fragP->fr_fix += 2; /* Skip second branch opcode */
5042 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5043 fragP->fr_offset, 1, RELAX_RELOC_PC32);
5044 fragP->fr_fix += 4;
5045 break;
151337e8
NC		 5046 case TAB (BRABSJUNC, LONG):
5047 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 5048 {
36759679 5049 if (flag_keep_pcrel)
2b878742
NS		 5050 as_bad_where (fragP->fr_file, fragP->fr_line,
5051 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 5052 fragP->fr_opcode[0] = 0x4E;
36759679 5053 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 5054 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5055 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5056 fragP->fr_fix += 4;
5057 }
5058 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
5059 {
36759679 5060 if (flag_keep_pcrel)
2b878742
NS		 5061 as_bad_where (fragP->fr_file, fragP->fr_line,
5062 _("Conversion of PC relative branch to absolute jump"));
151337e8 5063 fragP->fr_opcode[0] = 0x4E;
36759679 5064 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 5065 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5066 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5067 fragP->fr_fix += 4;
252b5132
RH		 5068 }
5069 else
5070 {
151337e8
NC		 5071 /* This cannot happen, because jbsr and jbra are the only two
5072 unconditional branches. */
5073 abort ();
252b5132
RH		 5074 }
5075 break;
151337e8 5076 case TAB (BRABSJCOND, LONG):
36759679 5077 if (flag_keep_pcrel)
2b878742
NS		 5078 as_bad_where (fragP->fr_file, fragP->fr_line,
5079 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 5080
36759679
NC		 5081 /* Only Bcc 68000 instructions can come here
5082 Change bcc into b!cc/jmp absl long. */
5083 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
5084 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 5085
5086 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 5087 different frag, in which case referring to them is a no-no.
92774660 5088 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 5089 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
5090 *buffer_address++ = (char) 0xf9;
36759679 5091 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 5092 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5093 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 5094 fragP->fr_fix += 4;
5095 break;
5096 case TAB (FBRANCH, SHORT):
5097 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 5098 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5099 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5100 fragP->fr_fix += 2;
5101 break;
5102 case TAB (FBRANCH, LONG):
36759679 5103 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 5104 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5105 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5106 fragP->fr_fix += 4;
252b5132 5107 break;
151337e8
NC		 5108 case TAB (DBCCLBR, SHORT):
5109 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 5110 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5111 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5112 fragP->fr_fix += 2;
5113 break;
5114 case TAB (DBCCLBR, LONG):
36759679
NC		 5115 /* Only DBcc instructions can come here.
5116 Change dbcc into dbcc/bral.
5117 JF: these used to be fr_opcode[2-7], but that's wrong. */
5118 if (flag_keep_pcrel)
2b878742
NS		 5119 as_bad_where (fragP->fr_file, fragP->fr_line,
5120 _("Conversion of DBcc to absolute jump"));
28e7409f 5121
36759679 5122 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 5123 *buffer_address++ = 0x04;
36759679 5124 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 5125 *buffer_address++ = 0x06;
151337e8
NC		 5126 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
5127 *buffer_address++ = (char) 0xff;
252b5132 5128
36759679 5129 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5130 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5131 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 5132 fragP->fr_fix += 4;
252b5132 5133 break;
151337e8 5134 case TAB (DBCCABSJ, LONG):
36759679
NC		 5135 /* Only DBcc instructions can come here.
5136 Change dbcc into dbcc/jmp.
5137 JF: these used to be fr_opcode[2-7], but that's wrong. */
5138 if (flag_keep_pcrel)
2b878742
NS		 5139 as_bad_where (fragP->fr_file, fragP->fr_line,
5140 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 5141
36759679 5142 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 5143 *buffer_address++ = 0x04;
36759679 5144 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 5145 *buffer_address++ = 0x06;
36759679 5146 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 5147 *buffer_address++ = (char) 0xf9;
5148
36759679 5149 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 5150 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5151 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 5152 fragP->fr_fix += 4;
252b5132 5153 break;
151337e8 5154 case TAB (PCREL1632, SHORT):
252b5132
RH		 5155 fragP->fr_opcode[1] &= ~0x3F;
5156 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 5157 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5158 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 5159 fragP->fr_fix += 2;
252b5132 5160 break;
151337e8 5161 case TAB (PCREL1632, LONG):
252b5132
RH		 5162 /* Already set to mode 7.3; this indicates: PC indirect with
5163 suppressed index, 32-bit displacement. */
5164 *buffer_address++ = 0x01;
5165 *buffer_address++ = 0x70;
5166 fragP->fr_fix += 2;
151337e8 5167 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5168 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5169 fixP->fx_pcrel_adjust = 2;
5170 fragP->fr_fix += 4;
252b5132 5171 break;
252b5132 5172 case TAB (PCINDEX, BYTE):
9c2799c2 5173 gas_assert (fragP->fr_fix >= 2);
252b5132 5174 buffer_address[-2] &= ~1;
151337e8 5175 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 5176 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 5177 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 5178 break;
5179 case TAB (PCINDEX, SHORT):
9c2799c2 5180 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5181 buffer_address[-2] |= 0x1;
5182 buffer_address[-1] = 0x20;
5183 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 5184 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 5185 fixP->fx_pcrel_adjust = 2;
151337e8 5186 fragP->fr_fix += 2;
252b5132
RH		 5187 break;
5188 case TAB (PCINDEX, LONG):
9c2799c2 5189 gas_assert (fragP->fr_fix >= 2);
252b5132
RH		 5190 buffer_address[-2] |= 0x1;
5191 buffer_address[-1] = 0x30;
151337e8 5192 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 5193 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 5194 fixP->fx_pcrel_adjust = 2;
5195 fragP->fr_fix += 4;
5196 break;
5197 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 5198 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
5199 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 5200 fragP->fr_fix += 2;
5201 break;
5202 case TAB (ABSTOPCREL, LONG):
36759679 5203 if (flag_keep_pcrel)
025987ea
NS		 5204 as_bad_where (fragP->fr_file, fragP->fr_line,
5205 _("Conversion of PC relative displacement to absolute"));
151337e8 5206 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 5207 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 5208 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
5209 abort ();
5210 fragP->fr_opcode[1] &= ~0x3F;
5211 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 5212 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5213 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5214 fragP->fr_fix += 4;
252b5132 5215 break;
252b5132 5216 }
2b878742
NS		 5217 if (fixP)
5218 {
5219 fixP->fx_file = fragP->fr_file;
5220 fixP->fx_line = fragP->fr_line;
5221 }
252b5132
RH		 5222}
5223
252b5132 5224void
31302357
AS		 5225md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5226 segT sec ATTRIBUTE_UNUSED,
5227 fragS *fragP)
252b5132
RH		 5228{
5229 md_convert_frag_1 (fragP);
5230}
252b5132
RH		 5231
5232/* Force truly undefined symbols to their maximum size, and generally set up
5233 the frag list to be relaxed
5234 */
5235int
31302357 5236md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5237{
151337e8 5238 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5239 switch (fragP->fr_subtype)
5240 {
151337e8 5241 case TAB (BRANCHBWL, SZ_UNDEF):
cac27205 5242 case TAB (BRANCHBWPL, SZ_UNDEF):
151337e8 5243 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5244 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5245 {
151337e8
NC		 5246 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5247 && relaxable_symbol (fragP->fr_symbol))
252b5132 5248 {
151337e8
NC		 5249 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5250 }
5251 else if (flag_short_refs)
5252 {
5253 /* Symbol is undefined and we want short ref. */
5254 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5255 }
5256 else
5257 {
151337e8
NC		 5258 /* Symbol is still undefined. Make it LONG. */
5259 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5260 }
5261 break;
151337e8 5262 }
252b5132 5263
151337e8 5264 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5265 {
151337e8
NC		 5266 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5267 && relaxable_symbol (fragP->fr_symbol))
252b5132 5268 {
151337e8 5269 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5270 }
5271 else
5272 {
151337e8
NC		 5273 /* Symbol is undefined and we don't have long branches. */
5274 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5275 }
5276 break;
151337e8 5277 }
252b5132 5278
151337e8 5279 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5280 case TAB (DBCCLBR, SZ_UNDEF):
5281 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5282 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5283 {
8ec6253e
NC		 5284 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5285 && relaxable_symbol (fragP->fr_symbol))
151337e8 5286 || flag_short_refs)
252b5132 5287 {
151337e8 5288 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5289 }
5290 else
5291 {
151337e8 5292 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5293 }
5294 break;
151337e8 5295 }
81d4177b 5296
252b5132
RH		 5297 case TAB (PCINDEX, SZ_UNDEF):
5298 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5299 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5300 {
5301 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5302 }
5303 else
5304 {
5305 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5306 }
5307 break;
5308
151337e8
NC		 5309 case TAB (ABSTOPCREL, SZ_UNDEF):
5310 {
5311 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5312 && relaxable_symbol (fragP->fr_symbol)))
5313 {
5314 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5315 }
5316 else
5317 {
5318 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5319 }
5320 break;
5321 }
5322
252b5132
RH		 5323 default:
5324 break;
5325 }
5326
151337e8 5327 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5328 switch (fragP->fr_subtype)
5329 {
151337e8
NC		 5330 case TAB (BRANCHBWL, BYTE):
5331 case TAB (BRABSJUNC, BYTE):
5332 case TAB (BRABSJCOND, BYTE):
5333 case TAB (BRANCHBW, BYTE):
252b5132 5334 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5335 case we force word mode. If the symbol is at the start of a
5336 frag, and it is the next frag with any data in it (usually
5337 this is just the next frag, but assembler listings may
5338 introduce empty frags), we must use word mode. */
5339 if (fragP->fr_symbol)
252b5132 5340 {
ac62c346 5341 fragS *sym_frag;
252b5132 5342
ac62c346
AM		 5343 sym_frag = symbol_get_frag (fragP->fr_symbol);
5344 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5345 {
ac62c346
AM		 5346 fragS *l;
5347
23b7f870 5348 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5349 if (l->fr_fix != 0)
5350 break;
5351 if (l == sym_frag)
5352 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5353 }
5354 }
5355 break;
5356 default:
5357 break;
5358 }
ac62c346 5359 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5360}
5361
5362#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5363/* the bit-field entries in the relocation_info struct plays hell
5364 with the byte-order problems of cross-assembly. So as a hack,
5365 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5366 you there. -KWK */
252b5132
RH		 5367/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5368 are symbolnum, most sig. byte first. Last byte is broken up with
5369 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5370 nibble as nuthin. (on Sun 3 at least) */
5371/* Translate the internal relocation information into target-specific
92774660 5372 format. */
252b5132
RH		 5373#ifdef comment
5374void
31302357 5375md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5376{
36759679 5377 /* This is easy. */
252b5132 5378 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5379 /* Now the fun stuff. */
252b5132 5380 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5381 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5382 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5383 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5384 | ((ri->r_length << 5) & 0x60)
5385 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5386}
5387
36759679 5388#endif
252b5132 5389
252b5132
RH		 5390#endif /* OBJ_AOUT or OBJ_BOUT */
5391
5392#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5393int md_short_jump_size = 4;
5394int md_long_jump_size = 6;
252b5132
RH		 5395
5396void
31302357
AS		 5397md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5398 fragS *frag ATTRIBUTE_UNUSED,
5399 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5400{
5401 valueT offset;
5402
5403 offset = to_addr - (from_addr + 2);
5404
5405 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5406 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5407}
5408
5409void
31302357
AS		 5410md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5411 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5412{
5413 valueT offset;
5414
6b6e92f4 5415 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5416 {
36759679 5417 if (flag_keep_pcrel)
6b6e92f4 5418 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5419 offset = to_addr - S_GET_VALUE (to_symbol);
5420 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5421 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5422 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5423 0, NO_RELOC);
5424 }
5425 else
5426 {
5427 offset = to_addr - (from_addr + 2);
5428 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5429 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5430 }
5431}
5432
5433#endif
5434
5435/* Different values of OK tell what its OK to return. Things that
5436 aren't OK are an error (what a shock, no?)
5437
5438 0: Everything is OK
3e602632
NC		 5439 10: Absolute 1:8 only
5440 20: Absolute 0:7 only
5441 30: absolute 0:15 only
5442 40: Absolute 0:31 only
5443 50: absolute 0:127 only
252b5132 5444 55: absolute -64:63 only
3e602632 5445 60: absolute -128:127 only
afa2158f 5446 65: absolute 0:511 only
3e602632
NC		 5447 70: absolute 0:4095 only
5448 80: absolute -1, 1:7 only
5449 90: No bignums. */
252b5132
RH		 5450
5451static int
31302357 5452get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5453{
5454 if (exp->exp.X_op == O_absent)
5455 {
36759679 5456 /* Do the same thing the VAX asm does. */
252b5132
RH		 5457 op (exp) = O_constant;
5458 adds (exp) = 0;
5459 subs (exp) = 0;
5460 offs (exp) = 0;
5461 if (ok == 10)
5462 {
5463 as_warn (_("expression out of range: defaulting to 1"));
5464 offs (exp) = 1;
5465 }
5466 }
5467 else if (exp->exp.X_op == O_constant)
5468 {
5469 switch (ok)
5470 {
5471 case 10:
bd17c2c3 5472 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5473 {
5474 as_warn (_("expression out of range: defaulting to 1"));
5475 offs (exp) = 1;
5476 }
5477 break;
5478 case 20:
bd17c2c3 5479 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5480 goto outrange;
5481 break;
5482 case 30:
bd17c2c3 5483 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5484 goto outrange;
5485 break;
5486 case 40:
bd17c2c3 5487 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5488 goto outrange;
5489 break;
5490 case 50:
bd17c2c3 5491 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5492 goto outrange;
5493 break;
5494 case 55:
bd17c2c3 5495 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5496 goto outrange;
5497 break;
5498 case 60:
bd17c2c3 5499 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132 5500 goto outrange;
afa2158f
NS		 5501 break;
5502 case 65:
5503 if ((valueT) TRUNC (offs (exp)) > 511)
5504 goto outrange;
252b5132
RH		 5505 break;
5506 case 70:
bd17c2c3 5507 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5508 {
5509 outrange:
5510 as_warn (_("expression out of range: defaulting to 0"));
5511 offs (exp) = 0;
5512 }
5513 break;
3e602632 5514 case 80:
bd17c2c3
AM		 5515 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5516 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5517 {
5518 as_warn (_("expression out of range: defaulting to 1"));
5519 offs (exp) = 1;
5520 }
5521 break;
252b5132
RH		 5522 default:
5523 break;
5524 }
5525 }
5526 else if (exp->exp.X_op == O_big)
5527 {
36759679 5528 if (offs (exp) <= 0 /* flonum. */
3e602632 5529 && (ok == 90 /* no bignums */
36759679 5530 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5531 /* If we have a flonum zero, a zero integer should
5532 do as well (e.g., in moveq). */
5533 && generic_floating_point_number.exponent == 0
5534 && generic_floating_point_number.low[0] == 0)))
5535 {
36759679 5536 /* HACK! Turn it into a long. */
252b5132
RH		 5537 LITTLENUM_TYPE words[6];
5538
36759679 5539 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5540 op (exp) = O_constant;
5541 adds (exp) = 0;
5542 subs (exp) = 0;
5543 offs (exp) = words[1] | (words[0] << 16);
5544 }
5545 else if (ok != 0)
5546 {
5547 op (exp) = O_constant;
5548 adds (exp) = 0;
5549 subs (exp) = 0;
5550 offs (exp) = (ok == 10) ? 1 : 0;
5551 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5552 (long) offs (exp));
252b5132
RH		 5553 }
5554 }
5555 else
5556 {
3e602632 5557 if (ok >= 10 && ok <= 80)
252b5132
RH		 5558 {
5559 op (exp) = O_constant;
5560 adds (exp) = 0;
5561 subs (exp) = 0;
5562 offs (exp) = (ok == 10) ? 1 : 0;
5563 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5564 (long) offs (exp));
252b5132
RH		 5565 }
5566 }
5567
5568 if (exp->size != SIZE_UNSPEC)
5569 {
5570 switch (exp->size)
5571 {
5572 case SIZE_UNSPEC:
5573 case SIZE_LONG:
5574 break;
5575 case SIZE_BYTE:
5576 if (!isbyte (offs (exp)))
5577 as_warn (_("expression doesn't fit in BYTE"));
5578 break;
5579 case SIZE_WORD:
5580 if (!isword (offs (exp)))
5581 as_warn (_("expression doesn't fit in WORD"));
5582 break;
5583 }
5584 }
5585
5586 return offs (exp);
5587}
5588
5589/* These are the back-ends for the various machine dependent pseudo-ops. */
5590
5591static void
31302357 5592s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5593{
5594 subseg_set (data_section, 1);
5595 demand_empty_rest_of_line ();
5596}
5597
5598static void
31302357 5599s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5600{
5601 subseg_set (data_section, 2);
5602 demand_empty_rest_of_line ();
5603}
5604
5605static void
31302357 5606s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5607{
5608 /* We don't support putting frags in the BSS segment, we fake it
5609 by marking in_bss, then looking at s_skip for clues. */
5610
5611 subseg_set (bss_section, 0);
5612 demand_empty_rest_of_line ();
5613}
5614
5615static void
31302357 5616s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5617{
5618 register int temp;
5619 register long temp_fill;
5620
5621 temp = 1; /* JF should be 2? */
5622 temp_fill = get_absolute_expression ();
92774660 5623 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5624 frag_align (temp, (int) temp_fill, 0);
5625 demand_empty_rest_of_line ();
5626 record_alignment (now_seg, temp);
5627}
5628
5629static void
31302357 5630s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5631{
5632 demand_empty_rest_of_line ();
5633}
5634\f
5635/* Pseudo-ops handled for MRI compatibility. */
5636
5637/* This function returns non-zero if the argument is a conditional
5638 pseudo-op. This is called when checking whether a pending
5639 alignment is needed. */
5640
5641int
31302357 5642m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5643{
5644 return (pop->poc_handler == s_mri_if
5645 || pop->poc_handler == s_mri_else);
5646}
5647
5648/* Handle an MRI style chip specification. */
5649
5650static void
31302357 5651mri_chip (void)
252b5132
RH		 5652{
5653 char *s;
5654 char c;
5655 int i;
5656
5657 s = input_line_pointer;
5658 /* We can't use get_symbol_end since the processor names are not proper
5659 symbols. */
5660 while (is_part_of_name (c = *input_line_pointer++))
5661 ;
5662 *--input_line_pointer = 0;
266abb8f
NS		 5663 for (i = 0; m68k_cpus[i].name; i++)
5664 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5665 break;
266abb8f 5666 if (!m68k_cpus[i].name)
252b5132
RH		 5667 {
5668 as_bad (_("%s: unrecognized processor name"), s);
5669 *input_line_pointer = c;
5670 ignore_rest_of_line ();
5671 return;
5672 }
5673 *input_line_pointer = c;
5674
5675 if (*input_line_pointer == '/')
5676 current_architecture = 0;
5677 else
5678 current_architecture &= m68881 | m68851;
266abb8f 5679 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5680 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5681
5682 while (*input_line_pointer == '/')
5683 {
5684 ++input_line_pointer;
5685 s = input_line_pointer;
5686 /* We can't use get_symbol_end since the processor names are not
5687 proper symbols. */
5688 while (is_part_of_name (c = *input_line_pointer++))
5689 ;
5690 *--input_line_pointer = 0;
5691 if (strcmp (s, "68881") == 0)
5692 current_architecture |= m68881;
5693 else if (strcmp (s, "68851") == 0)
5694 current_architecture |= m68851;
5695 *input_line_pointer = c;
5696 }
252b5132
RH		 5697}
5698
5699/* The MRI CHIP pseudo-op. */
5700
5701static void
31302357 5702s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5703{
5704 char *stop = NULL;
5705 char stopc;
5706
5707 if (flag_mri)
5708 stop = mri_comment_field (&stopc);
5709 mri_chip ();
5710 if (flag_mri)
5711 mri_comment_end (stop, stopc);
5712 demand_empty_rest_of_line ();
5713}
5714
5715/* The MRI FOPT pseudo-op. */
5716
5717static void
31302357 5718s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5719{
5720 SKIP_WHITESPACE ();
5721
5722 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5723 {
5724 int temp;
5725
5726 input_line_pointer += 3;
5727 temp = get_absolute_expression ();
5728 if (temp < 0 || temp > 7)
5729 as_bad (_("bad coprocessor id"));
5730 else
5731 m68k_float_copnum = COP0 + temp;
5732 }
5733 else
5734 {
5735 as_bad (_("unrecognized fopt option"));
5736 ignore_rest_of_line ();
5737 return;
5738 }
5739
5740 demand_empty_rest_of_line ();
5741}
5742
5743/* The structure used to handle the MRI OPT pseudo-op. */
5744
5745struct opt_action
5746{
5747 /* The name of the option. */
5748 const char *name;
5749
5750 /* If this is not NULL, just call this function. The first argument
5751 is the ARG field of this structure, the second argument is
5752 whether the option was negated. */
31302357 5753 void (*pfn) (int arg, int on);
252b5132
RH		 5754
5755 /* If this is not NULL, and the PFN field is NULL, set the variable
5756 this points to. Set it to the ARG field if the option was not
5757 negated, and the NOTARG field otherwise. */
5758 int *pvar;
5759
5760 /* The value to pass to PFN or to assign to *PVAR. */
5761 int arg;
5762
5763 /* The value to assign to *PVAR if the option is negated. If PFN is
5764 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5765 the option may not be negated. */
5766 int notarg;
5767};
5768
5769/* The table used to handle the MRI OPT pseudo-op. */
5770
31302357
AS		 5771static void skip_to_comma (int, int);
5772static void opt_nest (int, int);
5773static void opt_chip (int, int);
5774static void opt_list (int, int);
5775static void opt_list_symbols (int, int);
252b5132
RH		 5776
5777static const struct opt_action opt_table[] =
5778{
5779 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5780
5781 /* We do relaxing, so there is little use for these options. */
5782 { "b", 0, 0, 0, 0 },
5783 { "brs", 0, 0, 0, 0 },
5784 { "brb", 0, 0, 0, 0 },
5785 { "brl", 0, 0, 0, 0 },
5786 { "brw", 0, 0, 0, 0 },
5787
5788 { "c", 0, 0, 0, 0 },
5789 { "cex", 0, 0, 0, 0 },
5790 { "case", 0, &symbols_case_sensitive, 1, 0 },
5791 { "cl", 0, 0, 0, 0 },
5792 { "cre", 0, 0, 0, 0 },
5793 { "d", 0, &flag_keep_locals, 1, 0 },
5794 { "e", 0, 0, 0, 0 },
5795 { "f", 0, &flag_short_refs, 1, 0 },
5796 { "frs", 0, &flag_short_refs, 1, 0 },
5797 { "frl", 0, &flag_short_refs, 0, 1 },
5798 { "g", 0, 0, 0, 0 },
5799 { "i", 0, 0, 0, 0 },
5800 { "m", 0, 0, 0, 0 },
5801 { "mex", 0, 0, 0, 0 },
5802 { "mc", 0, 0, 0, 0 },
5803 { "md", 0, 0, 0, 0 },
5804 { "nest", opt_nest, 0, 0, 0 },
5805 { "next", skip_to_comma, 0, 0, 0 },
5806 { "o", 0, 0, 0, 0 },
5807 { "old", 0, 0, 0, 0 },
5808 { "op", skip_to_comma, 0, 0, 0 },
5809 { "pco", 0, 0, 0, 0 },
5810 { "p", opt_chip, 0, 0, 0 },
5811 { "pcr", 0, 0, 0, 0 },
5812 { "pcs", 0, 0, 0, 0 },
5813 { "r", 0, 0, 0, 0 },
5814 { "quick", 0, &m68k_quick, 1, 0 },
5815 { "rel32", 0, &m68k_rel32, 1, 0 },
5816 { "s", opt_list, 0, 0, 0 },
5817 { "t", opt_list_symbols, 0, 0, 0 },
5818 { "w", 0, &flag_no_warnings, 0, 1 },
5819 { "x", 0, 0, 0, 0 }
5820};
5821
8fce3f5e 5822#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5823
5824/* The MRI OPT pseudo-op. */
5825
5826static void
31302357 5827s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5828{
5829 do
5830 {
5831 int t;
5832 char *s;
5833 char c;
5834 int i;
5835 const struct opt_action *o;
5836
5837 SKIP_WHITESPACE ();
5838
5839 t = 1;
5840 if (*input_line_pointer == '-')
5841 {
5842 ++input_line_pointer;
5843 t = 0;
5844 }
5845 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5846 {
5847 input_line_pointer += 2;
5848 t = 0;
5849 }
5850
5851 s = input_line_pointer;
5852 c = get_symbol_end ();
5853
5854 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5855 {
5856 if (strcasecmp (s, o->name) == 0)
5857 {
5858 if (o->pfn)
5859 {
5860 /* Restore input_line_pointer now in case the option
5861 takes arguments. */
5862 *input_line_pointer = c;
5863 (*o->pfn) (o->arg, t);
5864 }
5865 else if (o->pvar != NULL)
5866 {
5867 if (! t && o->arg == o->notarg)
5868 as_bad (_("option `%s' may not be negated"), s);
5869 *input_line_pointer = c;
5870 *o->pvar = t ? o->arg : o->notarg;
5871 }
5872 else
5873 *input_line_pointer = c;
5874 break;
5875 }
5876 }
5877 if (i >= OPTCOUNT)
5878 {
5879 as_bad (_("option `%s' not recognized"), s);
5880 *input_line_pointer = c;
5881 }
5882 }
5883 while (*input_line_pointer++ == ',');
5884
5885 /* Move back to terminating character. */
5886 --input_line_pointer;
5887 demand_empty_rest_of_line ();
5888}
5889
5890/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5891 not support and which take arguments. */
252b5132
RH		 5892
5893static void
31302357 5894skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5895{
5896 while (*input_line_pointer != ','
5897 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5898 ++input_line_pointer;
5899}
5900
5901/* Handle the OPT NEST=depth option. */
5902
5903static void
31302357 5904opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5905{
5906 if (*input_line_pointer != '=')
5907 {
5908 as_bad (_("bad format of OPT NEST=depth"));
5909 return;
5910 }
5911
5912 ++input_line_pointer;
5913 max_macro_nest = get_absolute_expression ();
5914}
5915
5916/* Handle the OPT P=chip option. */
5917
5918static void
31302357 5919opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5920{
5921 if (*input_line_pointer != '=')
5922 {
5923 /* This is just OPT P, which we do not support. */
5924 return;
5925 }
5926
5927 ++input_line_pointer;
5928 mri_chip ();
5929}
5930
5931/* Handle the OPT S option. */
5932
5933static void
31302357 5934opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5935{
5936 listing_list (on);
5937}
5938
5939/* Handle the OPT T option. */
5940
5941static void
31302357 5942opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5943{
5944 if (on)
5945 listing |= LISTING_SYMBOLS;
5946 else
8a104df9 5947 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5948}
5949
5950/* Handle the MRI REG pseudo-op. */
5951
5952static void
31302357 5953s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5954{
5955 char *s;
5956 int c;
5957 struct m68k_op rop;
5958 int mask;
5959 char *stop = NULL;
5960 char stopc;
5961
5962 if (line_label == NULL)
5963 {
5964 as_bad (_("missing label"));
5965 ignore_rest_of_line ();
5966 return;
5967 }
5968
5969 if (flag_mri)
5970 stop = mri_comment_field (&stopc);
5971
5972 SKIP_WHITESPACE ();
5973
5974 s = input_line_pointer;
3882b010 5975 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5976#ifdef REGISTER_PREFIX
5977 || *input_line_pointer == REGISTER_PREFIX
5978#endif
5979 || *input_line_pointer == '/'
5980 || *input_line_pointer == '-')
5981 ++input_line_pointer;
5982 c = *input_line_pointer;
5983 *input_line_pointer = '\0';
5984
5985 if (m68k_ip_op (s, &rop) != 0)
5986 {
5987 if (rop.error == NULL)
5988 as_bad (_("bad register list"));
5989 else
5990 as_bad (_("bad register list: %s"), rop.error);
5991 *input_line_pointer = c;
5992 ignore_rest_of_line ();
5993 return;
5994 }
5995
5996 *input_line_pointer = c;
5997
5998 if (rop.mode == REGLST)
5999 mask = rop.mask;
6000 else if (rop.mode == DREG)
6001 mask = 1 << (rop.reg - DATA0);
6002 else if (rop.mode == AREG)
6003 mask = 1 << (rop.reg - ADDR0 + 8);
6004 else if (rop.mode == FPREG)
6005 mask = 1 << (rop.reg - FP0 + 16);
6006 else if (rop.mode == CONTROL
6007 && rop.reg == FPI)
6008 mask = 1 << 24;
6009 else if (rop.mode == CONTROL
6010 && rop.reg == FPS)
6011 mask = 1 << 25;
6012 else if (rop.mode == CONTROL
6013 && rop.reg == FPC)
6014 mask = 1 << 26;
6015 else
6016 {
6017 as_bad (_("bad register list"));
6018 ignore_rest_of_line ();
6019 return;
6020 }
6021
6022 S_SET_SEGMENT (line_label, reg_section);
6023 S_SET_VALUE (line_label, ~mask);
49309057 6024 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 6025
6026 if (flag_mri)
6027 mri_comment_end (stop, stopc);
6028
6029 demand_empty_rest_of_line ();
6030}
6031
6032/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
6033
6034struct save_opts
6035{
6036 struct save_opts *next;
6037 int abspcadd;
6038 int symbols_case_sensitive;
6039 int keep_locals;
6040 int short_refs;
6041 int architecture;
2da12c60 6042 const enum m68k_register *control_regs;
252b5132
RH		 6043 int quick;
6044 int rel32;
6045 int listing;
6046 int no_warnings;
6047 /* FIXME: We don't save OPT S. */
6048};
6049
6050/* This variable holds the stack of saved options. */
6051
6052static struct save_opts *save_stack;
6053
6054/* The MRI SAVE pseudo-op. */
6055
6056static void
31302357 6057s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6058{
6059 struct save_opts *s;
6060
6061 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
6062 s->abspcadd = m68k_abspcadd;
6063 s->symbols_case_sensitive = symbols_case_sensitive;
6064 s->keep_locals = flag_keep_locals;
6065 s->short_refs = flag_short_refs;
6066 s->architecture = current_architecture;
2da12c60 6067 s->control_regs = control_regs;
252b5132
RH		 6068 s->quick = m68k_quick;
6069 s->rel32 = m68k_rel32;
6070 s->listing = listing;
6071 s->no_warnings = flag_no_warnings;
6072
6073 s->next = save_stack;
6074 save_stack = s;
6075
6076 demand_empty_rest_of_line ();
6077}
6078
6079/* The MRI RESTORE pseudo-op. */
6080
6081static void
31302357 6082s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6083{
6084 struct save_opts *s;
6085
6086 if (save_stack == NULL)
6087 {
6088 as_bad (_("restore without save"));
6089 ignore_rest_of_line ();
6090 return;
6091 }
6092
6093 s = save_stack;
6094 save_stack = s->next;
6095
6096 m68k_abspcadd = s->abspcadd;
6097 symbols_case_sensitive = s->symbols_case_sensitive;
6098 flag_keep_locals = s->keep_locals;
6099 flag_short_refs = s->short_refs;
6100 current_architecture = s->architecture;
2da12c60 6101 control_regs = s->control_regs;
252b5132
RH		 6102 m68k_quick = s->quick;
6103 m68k_rel32 = s->rel32;
6104 listing = s->listing;
6105 flag_no_warnings = s->no_warnings;
6106
6107 free (s);
6108
6109 demand_empty_rest_of_line ();
6110}
6111
6112/* Types of MRI structured control directives. */
6113
6114enum mri_control_type
6115{
6116 mri_for,
6117 mri_if,
6118 mri_repeat,
6119 mri_while
6120};
6121
6122/* This structure is used to stack the MRI structured control
6123 directives. */
6124
6125struct mri_control_info
6126{
6127 /* The directive within which this one is enclosed. */
6128 struct mri_control_info *outer;
6129
6130 /* The type of directive. */
6131 enum mri_control_type type;
6132
6133 /* Whether an ELSE has been in an IF. */
6134 int else_seen;
6135
6136 /* The add or sub statement at the end of a FOR. */
6137 char *incr;
6138
6139 /* The label of the top of a FOR or REPEAT loop. */
6140 char *top;
6141
6142 /* The label to jump to for the next iteration, or the else
6143 expression of a conditional. */
6144 char *next;
6145
6146 /* The label to jump to to break out of the loop, or the label past
6147 the end of a conditional. */
6148 char *bottom;
6149};
6150
6151/* The stack of MRI structured control directives. */
6152
6153static struct mri_control_info *mri_control_stack;
6154
6155/* The current MRI structured control directive index number, used to
6156 generate label names. */
6157
6158static int mri_control_index;
6159
252b5132
RH		 6160/* Assemble an instruction for an MRI structured control directive. */
6161
6162static void
31302357 6163mri_assemble (char *str)
252b5132
RH		 6164{
6165 char *s;
6166
6167 /* md_assemble expects the opcode to be in lower case. */
6168 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 6169 *s = TOLOWER (*s);
252b5132
RH		 6170
6171 md_assemble (str);
6172}
6173
6174/* Generate a new MRI label structured control directive label name. */
6175
6176static char *
31302357 6177mri_control_label (void)
252b5132
RH		 6178{
6179 char *n;
6180
6181 n = (char *) xmalloc (20);
6182 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
6183 ++mri_control_index;
6184 return n;
6185}
6186
6187/* Create a new MRI structured control directive. */
6188
6189static struct mri_control_info *
31302357 6190push_mri_control (enum mri_control_type type)
252b5132
RH		 6191{
6192 struct mri_control_info *n;
6193
6194 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
6195
6196 n->type = type;
6197 n->else_seen = 0;
6198 if (type == mri_if || type == mri_while)
6199 n->top = NULL;
6200 else
6201 n->top = mri_control_label ();
6202 n->next = mri_control_label ();
6203 n->bottom = mri_control_label ();
6204
6205 n->outer = mri_control_stack;
6206 mri_control_stack = n;
6207
6208 return n;
6209}
6210
6211/* Pop off the stack of MRI structured control directives. */
6212
6213static void
31302357 6214pop_mri_control (void)
252b5132
RH		 6215{
6216 struct mri_control_info *n;
6217
6218 n = mri_control_stack;
6219 mri_control_stack = n->outer;
6220 if (n->top != NULL)
6221 free (n->top);
6222 free (n->next);
6223 free (n->bottom);
6224 free (n);
6225}
6226
6227/* Recognize a condition code in an MRI structured control expression. */
6228
6229static int
31302357 6230parse_mri_condition (int *pcc)
252b5132
RH		 6231{
6232 char c1, c2;
6233
6234 know (*input_line_pointer == '<');
6235
6236 ++input_line_pointer;
6237 c1 = *input_line_pointer++;
6238 c2 = *input_line_pointer++;
6239
6240 if (*input_line_pointer != '>')
6241 {
6242 as_bad (_("syntax error in structured control directive"));
6243 return 0;
6244 }
6245
6246 ++input_line_pointer;
6247 SKIP_WHITESPACE ();
6248
3882b010
L		 6249 c1 = TOLOWER (c1);
6250 c2 = TOLOWER (c2);
252b5132
RH		 6251
6252 *pcc = (c1 << 8) | c2;
6253
6254 return 1;
6255}
6256
6257/* Parse a single operand in an MRI structured control expression. */
6258
6259static int
31302357
AS		 6260parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6261 char **rightstart, char **rightstop)
252b5132
RH		 6262{
6263 char *s;
6264
6265 SKIP_WHITESPACE ();
6266
6267 *pcc = -1;
6268 *leftstart = NULL;
6269 *leftstop = NULL;
6270 *rightstart = NULL;
6271 *rightstop = NULL;
6272
6273 if (*input_line_pointer == '<')
6274 {
6275 /* It's just a condition code. */
6276 return parse_mri_condition (pcc);
6277 }
6278
6279 /* Look ahead for the condition code. */
6280 for (s = input_line_pointer; *s != '\0'; ++s)
6281 {
6282 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6283 break;
6284 }
6285 if (*s == '\0')
6286 {
6287 as_bad (_("missing condition code in structured control directive"));
6288 return 0;
6289 }
6290
6291 *leftstart = input_line_pointer;
6292 *leftstop = s;
6293 if (*leftstop > *leftstart
6294 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6295 --*leftstop;
6296
6297 input_line_pointer = s;
6298 if (! parse_mri_condition (pcc))
6299 return 0;
6300
6301 /* Look ahead for AND or OR or end of line. */
6302 for (s = input_line_pointer; *s != '\0'; ++s)
6303 {
e1f44d10
NC		 6304 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6305 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6306 ^^^ ^^ */
8a104df9
KH		 6307 if ((s == input_line_pointer
6308 || *(s-1) == ' '
6309 || *(s-1) == '\t')
6310 && ((strncasecmp (s, "AND", 3) == 0
6311 && (s[3] == '.' || ! is_part_of_name (s[3])))
6312 || (strncasecmp (s, "OR", 2) == 0
6313 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6314 break;
252b5132
RH		 6315 }
6316
6317 *rightstart = input_line_pointer;
6318 *rightstop = s;
6319 if (*rightstop > *rightstart
6320 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6321 --*rightstop;
6322
6323 input_line_pointer = s;
6324
6325 return 1;
6326}
6327
6328#define MCC(b1, b2) (((b1) << 8) | (b2))
6329
6330/* Swap the sense of a condition. This changes the condition so that
6331 it generates the same result when the operands are swapped. */
6332
6333static int
31302357 6334swap_mri_condition (int cc)
252b5132
RH		 6335{
6336 switch (cc)
6337 {
6338 case MCC ('h', 'i'): return MCC ('c', 's');
6339 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6340 /* <HS> is an alias for <CC>. */
e1f44d10 6341 case MCC ('h', 's'):
252b5132 6342 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6343 /* <LO> is an alias for <CS>. */
e1f44d10 6344 case MCC ('l', 'o'):
252b5132
RH		 6345 case MCC ('c', 's'): return MCC ('h', 'i');
6346 case MCC ('p', 'l'): return MCC ('m', 'i');
6347 case MCC ('m', 'i'): return MCC ('p', 'l');
6348 case MCC ('g', 'e'): return MCC ('l', 'e');
6349 case MCC ('l', 't'): return MCC ('g', 't');
6350 case MCC ('g', 't'): return MCC ('l', 't');
6351 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6352 /* Issue a warning for conditions we can not swap. */
8fc4ee9b
AM		 6353 case MCC ('n', 'e'): return MCC ('n', 'e'); /* no problem here */
6354 case MCC ('e', 'q'): return MCC ('e', 'q'); /* also no problem */
e1f44d10
NC		 6355 case MCC ('v', 'c'):
6356 case MCC ('v', 's'):
6357 default :
6358 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6359 (char) (cc >> 8), (char) (cc));
6360 break;
252b5132
RH		 6361 }
6362 return cc;
6363}
6364
6365/* Reverse the sense of a condition. */
6366
6367static int
31302357 6368reverse_mri_condition (int cc)
252b5132
RH		 6369{
6370 switch (cc)
6371 {
6372 case MCC ('h', 'i'): return MCC ('l', 's');
6373 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6374 /* <HS> is an alias for <CC> */
6375 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6376 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6377 /* <LO> is an alias for <CS> */
6378 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6379 case MCC ('c', 's'): return MCC ('c', 'c');
6380 case MCC ('n', 'e'): return MCC ('e', 'q');
6381 case MCC ('e', 'q'): return MCC ('n', 'e');
6382 case MCC ('v', 'c'): return MCC ('v', 's');
6383 case MCC ('v', 's'): return MCC ('v', 'c');
6384 case MCC ('p', 'l'): return MCC ('m', 'i');
6385 case MCC ('m', 'i'): return MCC ('p', 'l');
6386 case MCC ('g', 'e'): return MCC ('l', 't');
6387 case MCC ('l', 't'): return MCC ('g', 'e');
6388 case MCC ('g', 't'): return MCC ('l', 'e');
6389 case MCC ('l', 'e'): return MCC ('g', 't');
6390 }
6391 return cc;
6392}
6393
6394/* Build an MRI structured control expression. This generates test
6395 and branch instructions. It goes to TRUELAB if the condition is
6396 true, and to FALSELAB if the condition is false. Exactly one of
6397 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6398 is the size qualifier for the expression. EXTENT is the size to
6399 use for the branch. */
6400
6401static void
31302357
AS		 6402build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6403 char *rightstart, char *rightstop,
6404 const char *truelab, const char *falselab,
6405 int extent)
252b5132
RH		 6406{
6407 char *buf;
6408 char *s;
6409
6410 if (leftstart != NULL)
6411 {
6412 struct m68k_op leftop, rightop;
6413 char c;
6414
6415 /* Swap the compare operands, if necessary, to produce a legal
6416 m68k compare instruction. Comparing a register operand with
6417 a non-register operand requires the register to be on the
6418 right (cmp, cmpa). Comparing an immediate value with
6419 anything requires the immediate value to be on the left
6420 (cmpi). */
6421
6422 c = *leftstop;
6423 *leftstop = '\0';
6424 (void) m68k_ip_op (leftstart, &leftop);
6425 *leftstop = c;
6426
6427 c = *rightstop;
6428 *rightstop = '\0';
6429 (void) m68k_ip_op (rightstart, &rightop);
6430 *rightstop = c;
6431
6432 if (rightop.mode == IMMED
6433 || ((leftop.mode == DREG || leftop.mode == AREG)
6434 && (rightop.mode != DREG && rightop.mode != AREG)))
6435 {
6436 char *temp;
6437
31302357
AS		 6438 /* Correct conditional handling:
6439 if #1 <lt> d0 then ;means if (1 < d0)
6440 ...
6441 endi
e1f44d10 6442
31302357 6443 should assemble to:
e1f44d10 6444
31302357
AS		 6445 cmp #1,d0 if we do *not* swap the operands
6446 bgt true we need the swapped condition!
6447 ble false
6448 true:
6449 ...
6450 false:
6451 */
252b5132
RH		 6452 temp = leftstart;
6453 leftstart = rightstart;
6454 rightstart = temp;
6455 temp = leftstop;
6456 leftstop = rightstop;
6457 rightstop = temp;
8a104df9
KH		 6458 }
6459 else
6460 {
e1f44d10 6461 cc = swap_mri_condition (cc);
252b5132
RH		 6462 }
6463 }
6464
6465 if (truelab == NULL)
6466 {
6467 cc = reverse_mri_condition (cc);
6468 truelab = falselab;
6469 }
92774660 6470
252b5132
RH		 6471 if (leftstart != NULL)
6472 {
6473 buf = (char *) xmalloc (20
6474 + (leftstop - leftstart)
6475 + (rightstop - rightstart));
6476 s = buf;
6477 *s++ = 'c';
6478 *s++ = 'm';
6479 *s++ = 'p';
6480 if (qual != '\0')
3882b010 6481 *s++ = TOLOWER (qual);
252b5132
RH		 6482 *s++ = ' ';
6483 memcpy (s, leftstart, leftstop - leftstart);
6484 s += leftstop - leftstart;
6485 *s++ = ',';
6486 memcpy (s, rightstart, rightstop - rightstart);
6487 s += rightstop - rightstart;
6488 *s = '\0';
6489 mri_assemble (buf);
6490 free (buf);
6491 }
92774660 6492
252b5132
RH		 6493 buf = (char *) xmalloc (20 + strlen (truelab));
6494 s = buf;
6495 *s++ = 'b';
6496 *s++ = cc >> 8;
6497 *s++ = cc & 0xff;
6498 if (extent != '\0')
3882b010 6499 *s++ = TOLOWER (extent);
252b5132
RH		 6500 *s++ = ' ';
6501 strcpy (s, truelab);
6502 mri_assemble (buf);
6503 free (buf);
6504}
6505
6506/* Parse an MRI structured control expression. This generates test
6507 and branch instructions. STOP is where the expression ends. It
6508 goes to TRUELAB if the condition is true, and to FALSELAB if the
6509 condition is false. Exactly one of TRUELAB and FALSELAB will be
6510 NULL, meaning to fall through. QUAL is the size qualifier for the
6511 expression. EXTENT is the size to use for the branch. */
6512
6513static void
31302357
AS		 6514parse_mri_control_expression (char *stop, int qual, const char *truelab,
6515 const char *falselab, int extent)
252b5132
RH		 6516{
6517 int c;
6518 int cc;
6519 char *leftstart;
6520 char *leftstop;
6521 char *rightstart;
6522 char *rightstop;
6523
6524 c = *stop;
6525 *stop = '\0';
6526
6527 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6528 &rightstart, &rightstop))
6529 {
6530 *stop = c;
6531 return;
6532 }
6533
6534 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6535 {
6536 const char *flab;
6537
6538 if (falselab != NULL)
6539 flab = falselab;
6540 else
6541 flab = mri_control_label ();
6542
6543 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6544 rightstop, (const char *) NULL, flab, extent);
6545
6546 input_line_pointer += 3;
6547 if (*input_line_pointer != '.'
6548 || input_line_pointer[1] == '\0')
6549 qual = '\0';
6550 else
6551 {
6552 qual = input_line_pointer[1];
6553 input_line_pointer += 2;
6554 }
6555
6556 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6557 &rightstart, &rightstop))
6558 {
6559 *stop = c;
6560 return;
6561 }
6562
6563 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6564 rightstop, truelab, falselab, extent);
6565
6566 if (falselab == NULL)
6567 colon (flab);
6568 }
6569 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6570 {
6571 const char *tlab;
6572
6573 if (truelab != NULL)
6574 tlab = truelab;
6575 else
6576 tlab = mri_control_label ();
6577
6578 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6579 rightstop, tlab, (const char *) NULL, extent);
6580
6581 input_line_pointer += 2;
6582 if (*input_line_pointer != '.'
6583 || input_line_pointer[1] == '\0')
6584 qual = '\0';
6585 else
6586 {
6587 qual = input_line_pointer[1];
6588 input_line_pointer += 2;
6589 }
6590
6591 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6592 &rightstart, &rightstop))
6593 {
6594 *stop = c;
6595 return;
6596 }
6597
6598 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6599 rightstop, truelab, falselab, extent);
6600
6601 if (truelab == NULL)
6602 colon (tlab);
6603 }
6604 else
6605 {
6606 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6607 rightstop, truelab, falselab, extent);
6608 }
6609
6610 *stop = c;
6611 if (input_line_pointer != stop)
6612 as_bad (_("syntax error in structured control directive"));
6613}
6614
6615/* Handle the MRI IF pseudo-op. This may be a structured control
6616 directive, or it may be a regular assembler conditional, depending
6617 on its operands. */
6618
6619static void
31302357 6620s_mri_if (int qual)
252b5132
RH		 6621{
6622 char *s;
6623 int c;
6624 struct mri_control_info *n;
6625
6626 /* A structured control directive must end with THEN with an
6627 optional qualifier. */
6628 s = input_line_pointer;
e1f44d10
NC		 6629 /* We only accept '*' as introduction of comments if preceded by white space
6630 or at first column of a line (I think this can't actually happen here?)
6631 This is important when assembling:
6632 if d0 <ne> 12(a0,d0*2) then
36759679 6633 if d0 <ne> #CONST*20 then. */
31302357
AS		 6634 while (! (is_end_of_line[(unsigned char) *s]
6635 || (flag_mri
6636 && *s == '*'
6637 && (s == input_line_pointer
6638 || *(s-1) == ' '
6639 || *(s-1) == '\t'))))
252b5132
RH		 6640 ++s;
6641 --s;
6642 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6643 --s;
6644
6645 if (s - input_line_pointer > 1
6646 && s[-1] == '.')
6647 s -= 2;
6648
6649 if (s - input_line_pointer < 3
6650 || strncasecmp (s - 3, "THEN", 4) != 0)
6651 {
6652 if (qual != '\0')
6653 {
6654 as_bad (_("missing then"));
6655 ignore_rest_of_line ();
6656 return;
6657 }
6658
6659 /* It's a conditional. */
6660 s_if (O_ne);
6661 return;
6662 }
6663
6664 /* Since this might be a conditional if, this pseudo-op will be
6665 called even if we are supported to be ignoring input. Double
6666 check now. Clobber *input_line_pointer so that ignore_input
6667 thinks that this is not a special pseudo-op. */
6668 c = *input_line_pointer;
6669 *input_line_pointer = 0;
6670 if (ignore_input ())
6671 {
6672 *input_line_pointer = c;
6673 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6674 ++input_line_pointer;
6675 demand_empty_rest_of_line ();
6676 return;
6677 }
6678 *input_line_pointer = c;
6679
6680 n = push_mri_control (mri_if);
6681
6682 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6683 n->next, s[1] == '.' ? s[2] : '\0');
6684
6685 if (s[1] == '.')
6686 input_line_pointer = s + 3;
6687 else
6688 input_line_pointer = s + 1;
6689
6690 if (flag_mri)
6691 {
6692 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6693 ++input_line_pointer;
6694 }
6695
6696 demand_empty_rest_of_line ();
6697}
6698
6699/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6700 structured IF, associate the ELSE with the IF. Otherwise, assume
6701 it is a conditional else. */
6702
6703static void
31302357 6704s_mri_else (int qual)
252b5132
RH		 6705{
6706 int c;
6707 char *buf;
6708 char q[2];
6709
6710 if (qual == '\0'
6711 && (mri_control_stack == NULL
6712 || mri_control_stack->type != mri_if
6713 || mri_control_stack->else_seen))
6714 {
6715 s_else (0);
6716 return;
6717 }
6718
6719 c = *input_line_pointer;
6720 *input_line_pointer = 0;
6721 if (ignore_input ())
6722 {
6723 *input_line_pointer = c;
6724 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6725 ++input_line_pointer;
6726 demand_empty_rest_of_line ();
6727 return;
6728 }
6729 *input_line_pointer = c;
6730
6731 if (mri_control_stack == NULL
6732 || mri_control_stack->type != mri_if
6733 || mri_control_stack->else_seen)
6734 {
6735 as_bad (_("else without matching if"));
6736 ignore_rest_of_line ();
6737 return;
6738 }
6739
6740 mri_control_stack->else_seen = 1;
6741
6742 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6743 q[0] = TOLOWER (qual);
252b5132
RH		 6744 q[1] = '\0';
6745 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6746 mri_assemble (buf);
6747 free (buf);
6748
6749 colon (mri_control_stack->next);
6750
6751 if (flag_mri)
6752 {
6753 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6754 ++input_line_pointer;
6755 }
6756
6757 demand_empty_rest_of_line ();
6758}
6759
6760/* Handle the MRI ENDI pseudo-op. */
6761
6762static void
31302357 6763s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6764{
6765 if (mri_control_stack == NULL
6766 || mri_control_stack->type != mri_if)
6767 {
6768 as_bad (_("endi without matching if"));
6769 ignore_rest_of_line ();
6770 return;
6771 }
6772
6773 /* ignore_input will not return true for ENDI, so we don't need to
6774 worry about checking it again here. */
6775
6776 if (! mri_control_stack->else_seen)
6777 colon (mri_control_stack->next);
6778 colon (mri_control_stack->bottom);
6779
6780 pop_mri_control ();
6781
6782 if (flag_mri)
6783 {
6784 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6785 ++input_line_pointer;
6786 }
6787
6788 demand_empty_rest_of_line ();
6789}
6790
6791/* Handle the MRI BREAK pseudo-op. */
6792
6793static void
31302357 6794s_mri_break (int extent)
252b5132
RH		 6795{
6796 struct mri_control_info *n;
6797 char *buf;
6798 char ex[2];
6799
6800 n = mri_control_stack;
6801 while (n != NULL
6802 && n->type != mri_for
6803 && n->type != mri_repeat
6804 && n->type != mri_while)
6805 n = n->outer;
6806 if (n == NULL)
6807 {
6808 as_bad (_("break outside of structured loop"));
6809 ignore_rest_of_line ();
6810 return;
6811 }
6812
6813 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6814 ex[0] = TOLOWER (extent);
252b5132
RH		 6815 ex[1] = '\0';
6816 sprintf (buf, "bra%s %s", ex, n->bottom);
6817 mri_assemble (buf);
6818 free (buf);
6819
6820 if (flag_mri)
6821 {
6822 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6823 ++input_line_pointer;
6824 }
6825
6826 demand_empty_rest_of_line ();
6827}
6828
6829/* Handle the MRI NEXT pseudo-op. */
6830
6831static void
31302357 6832s_mri_next (int extent)
252b5132
RH		 6833{
6834 struct mri_control_info *n;
6835 char *buf;
6836 char ex[2];
6837
6838 n = mri_control_stack;
6839 while (n != NULL
6840 && n->type != mri_for
6841 && n->type != mri_repeat
6842 && n->type != mri_while)
6843 n = n->outer;
6844 if (n == NULL)
6845 {
6846 as_bad (_("next outside of structured loop"));
6847 ignore_rest_of_line ();
6848 return;
6849 }
6850
6851 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6852 ex[0] = TOLOWER (extent);
252b5132
RH		 6853 ex[1] = '\0';
6854 sprintf (buf, "bra%s %s", ex, n->next);
6855 mri_assemble (buf);
6856 free (buf);
6857
6858 if (flag_mri)
6859 {
6860 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6861 ++input_line_pointer;
6862 }
6863
6864 demand_empty_rest_of_line ();
6865}
6866
6867/* Handle the MRI FOR pseudo-op. */
6868
6869static void
31302357 6870s_mri_for (int qual)
252b5132
RH		 6871{
6872 const char *varstart, *varstop;
6873 const char *initstart, *initstop;
6874 const char *endstart, *endstop;
6875 const char *bystart, *bystop;
6876 int up;
6877 int by;
6878 int extent;
6879 struct mri_control_info *n;
6880 char *buf;
6881 char *s;
6882 char ex[2];
6883
6884 /* The syntax is
6885 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6886 */
6887
6888 SKIP_WHITESPACE ();
6889 varstart = input_line_pointer;
6890
6891 /* Look for the '='. */
6892 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6893 && *input_line_pointer != '=')
6894 ++input_line_pointer;
6895 if (*input_line_pointer != '=')
6896 {
6897 as_bad (_("missing ="));
6898 ignore_rest_of_line ();
6899 return;
6900 }
6901
6902 varstop = input_line_pointer;
6903 if (varstop > varstart
6904 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6905 --varstop;
6906
6907 ++input_line_pointer;
6908
6909 initstart = input_line_pointer;
6910
6911 /* Look for TO or DOWNTO. */
6912 up = 1;
6913 initstop = NULL;
6914 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6915 {
6916 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6917 && ! is_part_of_name (input_line_pointer[2]))
6918 {
6919 initstop = input_line_pointer;
6920 input_line_pointer += 2;
6921 break;
6922 }
6923 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6924 && ! is_part_of_name (input_line_pointer[6]))
6925 {
6926 initstop = input_line_pointer;
6927 up = 0;
6928 input_line_pointer += 6;
6929 break;
6930 }
6931 ++input_line_pointer;
6932 }
6933 if (initstop == NULL)
6934 {
6935 as_bad (_("missing to or downto"));
6936 ignore_rest_of_line ();
6937 return;
6938 }
6939 if (initstop > initstart
6940 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6941 --initstop;
6942
6943 SKIP_WHITESPACE ();
6944 endstart = input_line_pointer;
6945
6946 /* Look for BY or DO. */
6947 by = 0;
6948 endstop = NULL;
6949 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6950 {
6951 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6952 && ! is_part_of_name (input_line_pointer[2]))
6953 {
6954 endstop = input_line_pointer;
6955 by = 1;
6956 input_line_pointer += 2;
6957 break;
6958 }
6959 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6960 && (input_line_pointer[2] == '.'
6961 || ! is_part_of_name (input_line_pointer[2])))
6962 {
6963 endstop = input_line_pointer;
6964 input_line_pointer += 2;
6965 break;
6966 }
6967 ++input_line_pointer;
6968 }
6969 if (endstop == NULL)
6970 {
6971 as_bad (_("missing do"));
6972 ignore_rest_of_line ();
6973 return;
6974 }
6975 if (endstop > endstart
6976 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6977 --endstop;
6978
6979 if (! by)
6980 {
6981 bystart = "#1";
6982 bystop = bystart + 2;
6983 }
6984 else
6985 {
6986 SKIP_WHITESPACE ();
6987 bystart = input_line_pointer;
6988
6989 /* Look for DO. */
6990 bystop = NULL;
6991 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6992 {
6993 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6994 && (input_line_pointer[2] == '.'
6995 || ! is_part_of_name (input_line_pointer[2])))
6996 {
6997 bystop = input_line_pointer;
6998 input_line_pointer += 2;
6999 break;
7000 }
7001 ++input_line_pointer;
7002 }
7003 if (bystop == NULL)
7004 {
7005 as_bad (_("missing do"));
7006 ignore_rest_of_line ();
7007 return;
7008 }
7009 if (bystop > bystart
7010 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
7011 --bystop;
7012 }
7013
7014 if (*input_line_pointer != '.')
7015 extent = '\0';
7016 else
7017 {
7018 extent = input_line_pointer[1];
7019 input_line_pointer += 2;
7020 }
7021
7022 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 7023 n = push_mri_control (mri_for);
7024
7025 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
7026
36759679 7027 /* Move init,var. */
252b5132
RH		 7028 s = buf;
7029 *s++ = 'm';
7030 *s++ = 'o';
7031 *s++ = 'v';
7032 *s++ = 'e';
7033 if (qual != '\0')
3882b010 7034 *s++ = TOLOWER (qual);
252b5132
RH		 7035 *s++ = ' ';
7036 memcpy (s, initstart, initstop - initstart);
7037 s += initstop - initstart;
7038 *s++ = ',';
7039 memcpy (s, varstart, varstop - varstart);
7040 s += varstop - varstart;
7041 *s = '\0';
7042 mri_assemble (buf);
7043
7044 colon (n->top);
7045
36759679 7046 /* cmp end,var. */
252b5132
RH		 7047 s = buf;
7048 *s++ = 'c';
7049 *s++ = 'm';
7050 *s++ = 'p';
7051 if (qual != '\0')
3882b010 7052 *s++ = TOLOWER (qual);
252b5132
RH		 7053 *s++ = ' ';
7054 memcpy (s, endstart, endstop - endstart);
7055 s += endstop - endstart;
7056 *s++ = ',';
7057 memcpy (s, varstart, varstop - varstart);
7058 s += varstop - varstart;
7059 *s = '\0';
7060 mri_assemble (buf);
7061
36759679 7062 /* bcc bottom. */
3882b010 7063 ex[0] = TOLOWER (extent);
252b5132
RH		 7064 ex[1] = '\0';
7065 if (up)
7066 sprintf (buf, "blt%s %s", ex, n->bottom);
7067 else
7068 sprintf (buf, "bgt%s %s", ex, n->bottom);
7069 mri_assemble (buf);
7070
7071 /* Put together the add or sub instruction used by ENDF. */
7072 s = buf;
7073 if (up)
7074 strcpy (s, "add");
7075 else
7076 strcpy (s, "sub");
7077 s += 3;
7078 if (qual != '\0')
3882b010 7079 *s++ = TOLOWER (qual);
252b5132
RH		 7080 *s++ = ' ';
7081 memcpy (s, bystart, bystop - bystart);
7082 s += bystop - bystart;
7083 *s++ = ',';
7084 memcpy (s, varstart, varstop - varstart);
7085 s += varstop - varstart;
7086 *s = '\0';
7087 n->incr = buf;
7088
7089 if (flag_mri)
7090 {
7091 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7092 ++input_line_pointer;
7093 }
7094
7095 demand_empty_rest_of_line ();
7096}
7097
7098/* Handle the MRI ENDF pseudo-op. */
7099
7100static void
31302357 7101s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7102{
7103 if (mri_control_stack == NULL
7104 || mri_control_stack->type != mri_for)
7105 {
7106 as_bad (_("endf without for"));
7107 ignore_rest_of_line ();
7108 return;
7109 }
7110
7111 colon (mri_control_stack->next);
7112
7113 mri_assemble (mri_control_stack->incr);
7114
7115 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
7116 mri_assemble (mri_control_stack->incr);
7117
7118 free (mri_control_stack->incr);
7119
7120 colon (mri_control_stack->bottom);
7121
7122 pop_mri_control ();
7123
7124 if (flag_mri)
7125 {
7126 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7127 ++input_line_pointer;
7128 }
7129
7130 demand_empty_rest_of_line ();
7131}
7132
7133/* Handle the MRI REPEAT pseudo-op. */
7134
7135static void
31302357 7136s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7137{
7138 struct mri_control_info *n;
7139
7140 n = push_mri_control (mri_repeat);
7141 colon (n->top);
7142 if (flag_mri)
7143 {
7144 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7145 ++input_line_pointer;
7146 }
7147 demand_empty_rest_of_line ();
7148}
7149
7150/* Handle the MRI UNTIL pseudo-op. */
7151
7152static void
31302357 7153s_mri_until (int qual)
252b5132
RH		 7154{
7155 char *s;
7156
7157 if (mri_control_stack == NULL
7158 || mri_control_stack->type != mri_repeat)
7159 {
7160 as_bad (_("until without repeat"));
7161 ignore_rest_of_line ();
7162 return;
7163 }
7164
7165 colon (mri_control_stack->next);
7166
7167 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
7168 ;
7169
7170 parse_mri_control_expression (s, qual, (const char *) NULL,
7171 mri_control_stack->top, '\0');
7172
7173 colon (mri_control_stack->bottom);
7174
7175 input_line_pointer = s;
7176
7177 pop_mri_control ();
7178
7179 if (flag_mri)
7180 {
7181 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7182 ++input_line_pointer;
7183 }
7184
7185 demand_empty_rest_of_line ();
7186}
7187
7188/* Handle the MRI WHILE pseudo-op. */
7189
7190static void
31302357 7191s_mri_while (int qual)
252b5132
RH		 7192{
7193 char *s;
7194
7195 struct mri_control_info *n;
7196
7197 s = input_line_pointer;
e1f44d10
NC		 7198 /* We only accept '*' as introduction of comments if preceded by white space
7199 or at first column of a line (I think this can't actually happen here?)
7200 This is important when assembling:
7201 while d0 <ne> 12(a0,d0*2) do
36759679 7202 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 7203 while (! (is_end_of_line[(unsigned char) *s]
7204 || (flag_mri
7205 && *s == '*'
7206 && (s == input_line_pointer
7207 || *(s-1) == ' '
7208 || *(s-1) == '\t'))))
252b5132
RH		 7209 s++;
7210 --s;
7211 while (*s == ' ' || *s == '\t')
7212 --s;
7213 if (s - input_line_pointer > 1
7214 && s[-1] == '.')
7215 s -= 2;
7216 if (s - input_line_pointer < 2
7217 || strncasecmp (s - 1, "DO", 2) != 0)
7218 {
7219 as_bad (_("missing do"));
7220 ignore_rest_of_line ();
7221 return;
7222 }
7223
7224 n = push_mri_control (mri_while);
7225
7226 colon (n->next);
7227
7228 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7229 s[1] == '.' ? s[2] : '\0');
7230
7231 input_line_pointer = s + 1;
7232 if (*input_line_pointer == '.')
7233 input_line_pointer += 2;
7234
7235 if (flag_mri)
7236 {
7237 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7238 ++input_line_pointer;
7239 }
7240
7241 demand_empty_rest_of_line ();
7242}
7243
7244/* Handle the MRI ENDW pseudo-op. */
7245
7246static void
31302357 7247s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7248{
7249 char *buf;
7250
7251 if (mri_control_stack == NULL
7252 || mri_control_stack->type != mri_while)
7253 {
7254 as_bad (_("endw without while"));
7255 ignore_rest_of_line ();
7256 return;
7257 }
7258
7259 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7260 sprintf (buf, "bra %s", mri_control_stack->next);
7261 mri_assemble (buf);
7262 free (buf);
7263
7264 colon (mri_control_stack->bottom);
7265
7266 pop_mri_control ();
7267
7268 if (flag_mri)
7269 {
7270 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7271 ++input_line_pointer;
7272 }
7273
7274 demand_empty_rest_of_line ();
7275}
7276\f
266abb8f
NS		 7277/* Parse a .cpu directive. */
7278
7279static void
7280s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7281{
7282 char saved_char;
7283 char *name;
7284
7285 if (initialized)
7286 {
7287 as_bad (_("already assembled instructions"));
7288 ignore_rest_of_line ();
7289 return;
7290 }
7291
7292 name = input_line_pointer;
7293 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7294 input_line_pointer++;
7295 saved_char = *input_line_pointer;
7296 *input_line_pointer = 0;
7297
7298 m68k_set_cpu (name, 1, 0);
7299
7300 *input_line_pointer = saved_char;
7301 demand_empty_rest_of_line ();
7302 return;
7303}
7304
7305/* Parse a .arch directive. */
7306
7307static void
7308s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7309{
7310 char saved_char;
7311 char *name;
7312
7313 if (initialized)
7314 {
7315 as_bad (_("already assembled instructions"));
7316 ignore_rest_of_line ();
7317 return;
7318 }
7319
7320 name = input_line_pointer;
7321 while (*input_line_pointer && *input_line_pointer != ','
7322 && !ISSPACE (*input_line_pointer))
7323 input_line_pointer++;
7324 saved_char = *input_line_pointer;
7325 *input_line_pointer = 0;
7326
7327 if (m68k_set_arch (name, 1, 0))
7328 {
7329 /* Scan extensions. */
7330 do
7331 {
7332 *input_line_pointer++ = saved_char;
7333 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7334 break;
7335 name = input_line_pointer;
7336 while (*input_line_pointer && *input_line_pointer != ','
7337 && !ISSPACE (*input_line_pointer))
7338 input_line_pointer++;
7339 saved_char = *input_line_pointer;
7340 *input_line_pointer = 0;
7341 }
7342 while (m68k_set_extension (name, 1, 0));
7343 }
7344
7345 *input_line_pointer = saved_char;
7346 demand_empty_rest_of_line ();
7347 return;
7348}
7349\f
7350/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7351 if none is found, the caller is responsible for emitting an error
7352 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7353 cpu name, if it begins with a '6' (possibly skipping an intervening
7354 'c'. We also allow a 'c' in the same place. if NEGATED is
7355 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7356 the option is indeed negated. */
7357
7358static const struct m68k_cpu *
7359m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7360 int allow_m, int *negated)
7361{
7362 /* allow negated value? */
7363 if (negated)
7364 {
7365 *negated = 0;
7366
7367 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7368 {
7369 arg += 3;
7370 *negated = 1;
7371 }
7372 }
7373
7374 /* Remove 'm' or 'mc' prefix from 68k variants. */
7375 if (allow_m)
7376 {
7377 if (arg[0] == 'm')
7378 {
7379 if (arg[1] == '6')
7380 arg += 1;
7381 else if (arg[1] == 'c' && arg[2] == '6')
7382 arg += 2;
7383 }
7384 }
7385 else if (arg[0] == 'c' && arg[1] == '6')
7386 arg += 1;
7387
7388 for (; table->name; table++)
7389 if (!strcmp (arg, table->name))
2da12c60
NS		 7390 {
7391 if (table->alias < -1 || table->alias > 1)
7392 as_bad (_("`%s' is deprecated, use `%s'"),
7393 table->name, table[table->alias < 0 ? 1 : -1].name);
7394 return table;
7395 }
266abb8f
NS		 7396 return 0;
7397}
7398
bfbba8e4 7399/* Set the cpu, issuing errors if it is unrecognized. */
266abb8f
NS		 7400
7401static int
7402m68k_set_cpu (char const *name, int allow_m, int silent)
7403{
7404 const struct m68k_cpu *cpu;
7405
7406 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7407
7408 if (!cpu)
7409 {
7410 if (!silent)
7411 as_bad (_("cpu `%s' unrecognized"), name);
7412 return 0;
7413 }
266abb8f
NS		 7414 selected_cpu = cpu;
7415 return 1;
7416}
7417
bfbba8e4 7418/* Set the architecture, issuing errors if it is unrecognized. */
266abb8f
NS		 7419
7420static int
7421m68k_set_arch (char const *name, int allow_m, int silent)
7422{
7423 const struct m68k_cpu *arch;
7424
7425 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7426
7427 if (!arch)
7428 {
7429 if (!silent)
7430 as_bad (_("architecture `%s' unrecognized"), name);
7431 return 0;
7432 }
266abb8f
NS		 7433 selected_arch = arch;
7434 return 1;
7435}
7436
7437/* Set the architecture extension, issuing errors if it is
7438 unrecognized, or invalid */
7439
7440static int
7441m68k_set_extension (char const *name, int allow_m, int silent)
7442{
7443 int negated;
7444 const struct m68k_cpu *ext;
7445
7446 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7447
7448 if (!ext)
7449 {
7450 if (!silent)
7451 as_bad (_("extension `%s' unrecognized"), name);
7452 return 0;
7453 }
7454
7455 if (negated)
87298967
NS		 7456 not_current_architecture |= (ext->control_regs
7457 ? *(unsigned *)ext->control_regs: ext->arch);
266abb8f
NS		 7458 else
7459 current_architecture |= ext->arch;
7460 return 1;
7461}
7462
31302357
AS		 7463/* md_parse_option
7464 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7465 */
252b5132
RH		 7466
7467#ifdef OBJ_ELF
5a38dc70 7468const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7469#else
5a38dc70 7470const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7471#endif
7472
7473struct option md_longopts[] = {
7474#define OPTION_PIC (OPTION_MD_BASE)
7475 {"pic", no_argument, NULL, OPTION_PIC},
7476#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7477 {"register-prefix-optional", no_argument, NULL,
7478 OPTION_REGISTER_PREFIX_OPTIONAL},
7479#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7480 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7481#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7482 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7483#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7484 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7485#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7486 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7487#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7488 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7489#define OPTION_PCREL (OPTION_MD_BASE + 7)
7490 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7491 {NULL, no_argument, NULL, 0}
7492};
bc805888 7493size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7494
7495int
31302357 7496md_parse_option (int c, char *arg)
252b5132
RH		 7497{
7498 switch (c)
7499 {
7500 case 'l': /* -l means keep external to 2 bit offset
36759679 7501 rather than 16 bit one. */
252b5132
RH		 7502 flag_short_refs = 1;
7503 break;
7504
7505 case 'S': /* -S means that jbsr's always turn into
7506 jsr's. */
7507 flag_long_jumps = 1;
7508 break;
7509
28e7409f
NC		 7510 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7511 branches into absolute jumps. */
7512 flag_keep_pcrel = 1;
7513 break;
7514
252b5132
RH		 7515 case OPTION_PIC:
7516 case 'k':
7517 flag_want_pic = 1;
36759679 7518 break; /* -pic, Position Independent Code. */
252b5132
RH		 7519
7520 case OPTION_REGISTER_PREFIX_OPTIONAL:
7521 flag_reg_prefix_optional = 1;
7522 reg_prefix_optional_seen = 1;
7523 break;
7524
7525 /* -V: SVR4 argument to print version ID. */
7526 case 'V':
7527 print_version_id ();
7528 break;
7529
7530 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7531 should be emitted or not. FIXME: Not implemented. */
7532 case 'Q':
7533 break;
7534
7535 case OPTION_BITWISE_OR:
7536 {
7537 char *n, *t;
7538 const char *s;
7539
7540 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7541 t = n;
7542 for (s = m68k_comment_chars; *s != '\0'; s++)
7543 if (*s != '|')
7544 *t++ = *s;
7545 *t = '\0';
7546 m68k_comment_chars = n;
7547 }
7548 break;
7549
7550 case OPTION_BASE_SIZE_DEFAULT_16:
7551 m68k_index_width_default = SIZE_WORD;
7552 break;
7553
7554 case OPTION_BASE_SIZE_DEFAULT_32:
7555 m68k_index_width_default = SIZE_LONG;
7556 break;
7557
7558 case OPTION_DISP_SIZE_DEFAULT_16:
7559 m68k_rel32 = 0;
7560 m68k_rel32_from_cmdline = 1;
7561 break;
7562
7563 case OPTION_DISP_SIZE_DEFAULT_32:
7564 m68k_rel32 = 1;
7565 m68k_rel32_from_cmdline = 1;
7566 break;
7567
266abb8f
NS		 7568 case 'A':
7569#if WARN_DEPRECATED
7570 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7571 arg, arg));
7572#endif
7573 /* Intentional fall-through. */
7574 case 'm':
7575 if (!strncmp (arg, "arch=", 5))
7576 m68k_set_arch (arg + 5, 1, 0);
7577 else if (!strncmp (arg, "cpu=", 4))
7578 m68k_set_cpu (arg + 4, 1, 0);
7579 else if (m68k_set_extension (arg, 0, 1))
7580 ;
0b2e31dc
NS		 7581 else if (m68k_set_arch (arg, 0, 1))
7582 ;
266abb8f
NS		 7583 else if (m68k_set_cpu (arg, 0, 1))
7584 ;
7585 else
7586 return 0;
7587 break;
7588
252b5132
RH		 7589 default:
7590 return 0;
7591 }
7592
7593 return 1;
7594}
7595
266abb8f
NS		 7596/* Setup tables from the selected arch and/or cpu */
7597
7598static void
7599m68k_init_arch (void)
7600{
266abb8f
NS		 7601 if (not_current_architecture & current_architecture)
7602 {
7603 as_bad (_("architecture features both enabled and disabled"));
7604 not_current_architecture &= ~current_architecture;
7605 }
7606 if (selected_arch)
2da12c60
NS		 7607 {
7608 current_architecture |= selected_arch->arch;
7609 control_regs = selected_arch->control_regs;
7610 }
0b2e31dc
NS		 7611 else
7612 current_architecture |= selected_cpu->arch;
0b2e31dc 7613
2da12c60
NS		 7614 current_architecture &= ~not_current_architecture;
7615
377260ba
NS		 7616 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7617 {
7618 /* Determine which float is really meant. */
7619 if (current_architecture & (m68k_mask & ~m68881))
7620 current_architecture ^= cfloat;
7621 else
7622 current_architecture ^= m68881;
7623 }
7624
0b2e31dc 7625 if (selected_cpu)
266abb8f 7626 {
2da12c60 7627 control_regs = selected_cpu->control_regs;
0b2e31dc 7628 if (current_architecture & ~selected_cpu->arch)
266abb8f 7629 {
0b2e31dc
NS		 7630 as_bad (_("selected processor does not have all features of selected architecture"));
7631 current_architecture
7632 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7633 }
7634 }
266abb8f 7635
266abb8f
NS		 7636 if ((current_architecture & m68k_mask)
7637 && (current_architecture & ~m68k_mask))
7638 {
7639 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7640 if (current_architecture & m68k_mask)
266abb8f
NS		 7641 current_architecture &= m68k_mask;
7642 else
7643 current_architecture &= ~m68k_mask;
7644 }
7645
7646 /* Permit m68881 specification with all cpus; those that can't work
7647 with a coprocessor could be doing emulation. */
7648 if (current_architecture & m68851)
7649 {
7650 if (current_architecture & m68040)
7651 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7652 }
7653 /* What other incompatibilities could we check for? */
7654
266abb8f
NS		 7655 if (cpu_of_arch (current_architecture) < m68020
7656 || arch_coldfire_p (current_architecture))
7657 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7658
7659 initialized = 1;
7660}
7661
252b5132 7662void
31302357 7663md_show_usage (FILE *stream)
252b5132 7664{
76f57f3a 7665 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7666 int i;
7667 unsigned int default_arch;
76f57f3a 7668
8a104df9 7669 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7670 if (*default_cpu == 'm')
7671 default_cpu++;
266abb8f 7672 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7673 {
266abb8f 7674 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7675 {
266abb8f 7676 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7677 while (m68k_cpus[i].alias > 0)
7678 i--;
7679 while (m68k_cpus[i].alias < 0)
7680 i++;
7681 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7682 }
7683 }
7684
bc805888 7685 fprintf (stream, _("\
266abb8f
NS		 7686-march=<arch> set architecture\n\
7687-mcpu=<cpu> set cpu [default %s]\n\
7688"), default_cpu);
7689 for (i = 0; m68k_extensions[i].name; i++)
7690 fprintf (stream, _("\
0b2e31dc
NS		 7691-m[no-]%-16s enable/disable%s architecture extension\n\
7692"), m68k_extensions[i].name,
7693 m68k_extensions[i].alias > 0 ? " ColdFire"
7694 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7695
bc805888 7696 fprintf (stream, _("\
266abb8f 7697-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7698-pic, -k generate position independent code\n\
7699-S turn jbsr into jsr\n\
28e7409f 7700--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7701--register-prefix-optional\n\
7702 recognize register names without prefix character\n\
266abb8f 7703--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7704--base-size-default-16 base reg without size is 16 bits\n\
7705--base-size-default-32 base reg without size is 32 bits (default)\n\
7706--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7707--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7708"));
7709
7710 fprintf (stream, _("Architecture variants are: "));
7711 for (i = 0; m68k_archs[i].name; i++)
7712 {
7713 if (i)
7714 fprintf (stream, " | ");
87298967 7715 fprintf (stream, "%s", m68k_archs[i].name);
266abb8f
NS		 7716 }
7717 fprintf (stream, "\n");
7718
7719 fprintf (stream, _("Processor variants are: "));
7720 for (i = 0; m68k_cpus[i].name; i++)
7721 {
7722 if (i)
7723 fprintf (stream, " | ");
87298967 7724 fprintf (stream, "%s", m68k_cpus[i].name);
266abb8f
NS		 7725 }
7726 fprintf (stream, _("\n"));
252b5132
RH		 7727}
7728\f
7729#ifdef TEST2
7730
7731/* TEST2: Test md_assemble() */
36759679
NC		 7732/* Warning, this routine probably doesn't work anymore. */
7733int
31302357 7734main (void)
252b5132
RH		 7735{
7736 struct m68k_it the_ins;
7737 char buf[120];
7738 char *cp;
7739 int n;
7740
7741 m68k_ip_begin ();
7742 for (;;)
7743 {
7744 if (!gets (buf) || !*buf)
7745 break;
7746 if (buf[0] == '|' || buf[1] == '.')
7747 continue;
7748 for (cp = buf; *cp; cp++)
7749 if (*cp == '\t')
7750 *cp = ' ';
7751 if (is_label (buf))
7752 continue;
7753 memset (&the_ins, '\0', sizeof (the_ins));
7754 m68k_ip (&the_ins, buf);
7755 if (the_ins.error)
7756 {
7757 printf (_("Error %s in %s\n"), the_ins.error, buf);
7758 }
7759 else
7760 {
7761 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7762 for (n = 0; n < the_ins.numo; n++)
7763 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7764 printf (" ");
7765 print_the_insn (&the_ins.opcode[0], stdout);
7766 (void) putchar ('\n');
7767 }
7768 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7769 {
7770 if (the_ins.operands[n].error)
7771 {
7772 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7773 continue;
7774 }
31302357
AS		 7775 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7776 the_ins.operands[n].reg);
252b5132 7777 if (the_ins.operands[n].b_const)
31302357
AS		 7778 printf ("Constant: '%.*s', ",
7779 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7780 the_ins.operands[n].b_const);
7781 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7782 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7783 if (the_ins.operands[n].b_iadd)
31302357
AS		 7784 printf ("Iadd: '%.*s',",
7785 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7786 the_ins.operands[n].b_iadd);
7787 putchar ('\n');
252b5132
RH		 7788 }
7789 }
7790 m68k_ip_end ();
7791 return 0;
7792}
7793
31302357
AS		 7794int
7795is_label (char *str)
252b5132
RH		 7796{
7797 while (*str == ' ')
7798 str++;
7799 while (*str && *str != ' ')
7800 str++;
7801 if (str[-1] == ':' || str[1] == '=')
7802 return 1;
7803 return 0;
7804}
7805
7806#endif
7807
7808/* Possible states for relaxation:
7809
7810 0 0 branch offset byte (bra, etc)
7811 0 1 word
7812 0 2 long
7813
7814 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7815 1 1 word
7816 1 2 long
7817
7818 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7819 2 1 word-long
7820 2 2 long-word
7821 2 3 long-long
7822
7823 */
7824
7825/* We have no need to default values of symbols. */
7826
252b5132 7827symbolS *
31302357 7828md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7829{
7830 return 0;
7831}
7832
7833/* Round up a section size to the appropriate boundary. */
7834valueT
31302357 7835md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7836{
7837#ifdef OBJ_AOUT
252b5132
RH		 7838 /* For a.out, force the section size to be aligned. If we don't do
7839 this, BFD will align it for us, but it will not write out the
7840 final bytes of the section. This may be a bug in BFD, but it is
7841 easier to fix it here since that is how the other a.out targets
7842 work. */
7843 int align;
7844
7845 align = bfd_get_section_alignment (stdoutput, segment);
7846 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7847#endif
7848
7849 return size;
7850}
7851
7852/* Exactly what point is a PC-relative offset relative TO?
7853 On the 68k, it is relative to the address of the first extension
7854 word. The difference between the addresses of the offset and the
92774660 7855 first extension word is stored in fx_pcrel_adjust. */
252b5132 7856long
31302357 7857md_pcrel_from (fixS *fixP)
252b5132
RH		 7858{
7859 int adjust;
7860
8390138c
AS		 7861 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7862 sign extend the value here. */
7863 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7864 if (adjust == 64)
7865 adjust = -1;
7866 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7867}
7868
0d96863f 7869#ifdef OBJ_ELF
8a104df9 7870void
31302357 7871m68k_elf_final_processing (void)
0d96863f 7872{
266abb8f
NS		 7873 unsigned flags = 0;
7874
238d258f 7875 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7876 flags |= EF_M68K_CFV4E;
7877 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7878 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7879 flags |= EF_M68K_CPU32;
7880 else if (cpu_of_arch (current_architecture) & fido_a)
7881 flags |= EF_M68K_FIDO;
8a104df9
KH		 7882 else if ((cpu_of_arch (current_architecture) & m68000up)
7883 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7884 flags |= EF_M68K_M68000;
7885
7886 if (current_architecture & mcfisa_a)
7887 {
0b2e31dc
NS		 7888 static const unsigned isa_features[][2] =
7889 {
9a2e615a 7890 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7891 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7892 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7893 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7894 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7895 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
8d100c32 7896 {EF_M68K_CF_ISA_C_NODIV,mcfisa_a|mcfisa_c|mcfusp},
0b2e31dc
NS		 7897 {0,0},
7898 };
7899 static const unsigned mac_features[][2] =
7900 {
c694fd50
KH		 7901 {EF_M68K_CF_MAC, mcfmac},
7902 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7903 {0,0},
7904 };
7905 unsigned ix;
7906 unsigned pattern;
266abb8f 7907
0b2e31dc 7908 pattern = (current_architecture
9a2e615a 7909 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7910 for (ix = 0; isa_features[ix][1]; ix++)
7911 {
7912 if (pattern == isa_features[ix][1])
7913 {
7914 flags |= isa_features[ix][0];
7915 break;
7916 }
7917 }
7918 if (!isa_features[ix][1])
7919 {
7920 cf_bad:
7921 as_warn (_("Not a defined coldfire architecture"));
7922 }
7923 else
7924 {
7925 if (current_architecture & cfloat)
c694fd50 7926 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7927
0b2e31dc
NS		 7928 pattern = current_architecture & (mcfmac|mcfemac);
7929 if (pattern)
7930 {
7931 for (ix = 0; mac_features[ix][1]; ix++)
7932 {
7933 if (pattern == mac_features[ix][1])
7934 {
7935 flags |= mac_features[ix][0];
7936 break;
7937 }
7938 }
7939 if (!mac_features[ix][1])
7940 goto cf_bad;
7941 }
7942 }
266abb8f
NS		 7943 }
7944 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f 7945}
cf869cce
NC		 7946
7947/* Parse @TLSLDO and return the desired relocation. */
7948static bfd_reloc_code_real_type
7949m68k_elf_suffix (char **str_p, expressionS *exp_p)
7950{
7951 char ident[20];
7952 char *str = *str_p;
7953 char *str2;
7954 int ch;
7955 int len;
7956
7957 if (*str++ != '@')
7958 return BFD_RELOC_UNUSED;
7959
7960 for (ch = *str, str2 = ident;
7961 (str2 < ident + sizeof (ident) - 1
7962 && (ISALNUM (ch) || ch == '@'));
7963 ch = *++str)
7964 {
7965 *str2++ = ch;
7966 }
7967
7968 *str2 = '\0';
7969 len = str2 - ident;
7970
7971 if (strncmp (ident, "TLSLDO", 6) == 0
7972 && len == 6)
7973 {
7974 /* Now check for identifier@suffix+constant. */
7975 if (*str == '-' || *str == '+')
7976 {
7977 char *orig_line = input_line_pointer;
7978 expressionS new_exp;
7979
7980 input_line_pointer = str;
7981 expression (&new_exp);
7982 if (new_exp.X_op == O_constant)
7983 {
7984 exp_p->X_add_number += new_exp.X_add_number;
7985 str = input_line_pointer;
7986 }
7987
7988 if (&input_line_pointer != str_p)
7989 input_line_pointer = orig_line;
7990 }
7991 *str_p = str;
7992
7993 return BFD_RELOC_68K_TLS_LDO32;
7994 }
7995
7996 return BFD_RELOC_UNUSED;
7997}
7998
7999/* Handles .long <tls_symbol>+0x8000 debug info.
8000 Clobbers input_line_pointer, checks end-of-line.
8001 Adapted from tc-ppc.c:ppc_elf_cons. */
8002static void
8003m68k_elf_cons (int nbytes /* 4=.long */)
8004{
8005 if (is_it_end_of_statement ())
8006 {
8007 demand_empty_rest_of_line ();
8008 return;
8009 }
8010
8011 do
8012 {
8013 expressionS exp;
8014 bfd_reloc_code_real_type reloc;
8015
8016 expression (&exp);
8017 if (exp.X_op == O_symbol
8018 && *input_line_pointer == '@'
8019 && (reloc = m68k_elf_suffix (&input_line_pointer,
8020 &exp)) != BFD_RELOC_UNUSED)
8021 {
8022 reloc_howto_type *reloc_howto;
8023 int size;
8024
8025 reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc);
8026 size = bfd_get_reloc_size (reloc_howto);
8027
8028 if (size > nbytes)
8029 {
8030 as_bad (_("%s relocations do not fit in %d bytes\n"),
8031 reloc_howto->name, nbytes);
8032 }
8033 else
8034 {
8035 char *p;
8036 int offset;
8037
8038 p = frag_more (nbytes);
8039 offset = 0;
8040 if (target_big_endian)
8041 offset = nbytes - size;
8042 fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size,
8043 &exp, 0, reloc);
8044 }
8045 }
8046 else
8047 emit_expr (&exp, (unsigned int) nbytes);
8048 }
8049 while (*input_line_pointer++ == ',');
8050
8051 /* Put terminator back into stream. */
8052 input_line_pointer--;
8053 demand_empty_rest_of_line ();
8054}
0d96863f 8055#endif
c04898f8
AS		 8056
8057int
1df69f4f 8058tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 8059{
8060 unsigned int regnum;
8061 static const char *const regnames[] =
8062 {
8063 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
8064 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
8065 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
8066 "pc"
8067 };
8068
8069 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
8070 if (strcmp (regname, regnames[regnum]) == 0)
8071 return regnum;
8072
8073 return -1;
8074}
8075
8076void
8077tc_m68k_frame_initial_instructions (void)
8078{
8079 static int sp_regno = -1;
8080
8081 if (sp_regno < 0)
8082 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
8083
8084 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
8085 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
8086}
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