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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
f17c130b 3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
155static const enum m68k_register m68000_control_regs[] = { 0 };
156static const enum m68k_register m68010_control_regs[] = {
157 SFC, DFC, USP, VBR,
158 0
159};
160static const enum m68k_register m68020_control_regs[] = {
161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
164static const enum m68k_register m68040_control_regs[] = {
165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
169static const enum m68k_register m68060_control_regs[] = {
170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
6da466c7 174static const enum m68k_register mcf_control_regs[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 176 RAMBAR0, RAMBAR1, MBAR,
177 0
178};
e80e0390
NC		 179static const enum m68k_register mcf5249_control_regs[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR1, MBAR, MBAR2,
181 0
182};
3e602632
NC		 183static const enum m68k_register mcf528x_control_regs[] = {
184 CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR,
185 0
186};
187static const enum m68k_register mcfv4e_control_regs[] = {
188 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
189 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
190 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
191 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
192 0
193};
252b5132
RH		 194#define cpu32_control_regs m68010_control_regs
195
196static const enum m68k_register *control_regs;
197
36759679 198/* Internal form of a 68020 instruction. */
252b5132
RH		 199struct m68k_it
200{
201 const char *error;
36759679 202 const char *args; /* List of opcode info. */
252b5132
RH		 203 int numargs;
204
36759679 205 int numo; /* Number of shorts in opcode. */
252b5132
RH		 206 short opcode[11];
207
208 struct m68k_op operands[6];
209
36759679 210 int nexp; /* Number of exprs in use. */
252b5132
RH		 211 struct m68k_exp exprs[4];
212
36759679 213 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 214 struct
215 {
36759679 216 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 217 symbolS *fadd;
218 offsetT foff;
219 int fragty;
220 }
221 fragb[4];
222
36759679 223 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 224 struct
225 {
226 int n;
227 expressionS exp;
228 char wid;
229 char pcrel;
230 /* In a pc relative address the difference between the address
231 of the offset and the address that the offset is relative
232 to. This depends on the addressing mode. Basically this
233 is the value to put in the offset field to address the
234 first byte of the offset, without regarding the special
235 significance of some values (in the branch instruction, for
236 example). */
237 int pcrel_fix;
238#ifdef OBJ_ELF
239 /* Whether this expression needs special pic relocation, and if
240 so, which. */
241 enum pic_relocation pic_reloc;
242#endif
243 }
36759679 244 reloc[5]; /* Five is enough??? */
252b5132
RH		 245};
246
6b6e92f4 247#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
252b5132
RH		 248#define float_of_arch(x) ((x) & mfloat)
249#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 250#define arch_coldfire_p(x) ((x) & mcfisa_a)
251#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 252
36759679 253/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 254#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 255
36759679 256static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 257
258#define op(ex) ((ex)->exp.X_op)
259#define adds(ex) ((ex)->exp.X_add_symbol)
260#define subs(ex) ((ex)->exp.X_op_symbol)
261#define offs(ex) ((ex)->exp.X_add_number)
262
36759679 263/* Macros for adding things to the m68k_it struct. */
31302357 264#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 265
36759679
NC		 266/* Like addword, but goes BEFORE general operands. */
267
252b5132 268static void
31302357 269insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 270{
271 int z;
07726851 272 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 273 the_ins.opcode[z] = the_ins.opcode[z - 1];
274 for (z = 0; z < the_ins.nrel; z++)
275 the_ins.reloc[z].n += 2;
252b5132
RH		 276 for (z = 0; z < the_ins.nfrag; z++)
277 the_ins.fragb[z].fragoff++;
8a104df9 278 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 279 the_ins.numo++;
280}
281
282/* The numo+1 kludge is so we can hit the low order byte of the prev word.
283 Blecch. */
284static void
31302357 285add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 286{
31302357
AS		 287 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
288 ? the_ins.numo * 2 - 1
289 : (width == 'b'
290 ? the_ins.numo * 2 + 1
291 : the_ins.numo * 2));
252b5132
RH		 292 the_ins.reloc[the_ins.nrel].exp = exp->exp;
293 the_ins.reloc[the_ins.nrel].wid = width;
294 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
295#ifdef OBJ_ELF
296 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
297#endif
298 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
299}
300
301/* Cause an extra frag to be generated here, inserting up to 10 bytes
302 (that value is chosen in the frag_var call in md_assemble). TYPE
303 is the subtype of the frag to be generated; its primary type is
304 rs_machine_dependent.
305
306 The TYPE parameter is also used by md_convert_frag_1 and
307 md_estimate_size_before_relax. The appropriate type of fixup will
308 be emitted by md_convert_frag_1.
309
310 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
311static void
31302357 312add_frag (symbolS *add, offsetT off, int type)
252b5132 313{
8a104df9
KH		 314 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
315 the_ins.fragb[the_ins.nfrag].fadd = add;
316 the_ins.fragb[the_ins.nfrag].foff = off;
317 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 318}
319
320#define isvar(ex) \
321 (op (ex) != O_constant && op (ex) != O_big)
322
31302357
AS		 323static char *crack_operand (char *str, struct m68k_op *opP);
324static int get_num (struct m68k_exp *exp, int ok);
325static int reverse_16_bits (int in);
326static int reverse_8_bits (int in);
327static void install_gen_operand (int mode, int val);
328static void install_operand (int mode, int val);
329static void s_bss (int);
330static void s_data1 (int);
331static void s_data2 (int);
332static void s_even (int);
333static void s_proc (int);
334static void s_chip (int);
335static void s_fopt (int);
336static void s_opt (int);
337static void s_reg (int);
338static void s_restore (int);
339static void s_save (int);
340static void s_mri_if (int);
341static void s_mri_else (int);
342static void s_mri_endi (int);
343static void s_mri_break (int);
344static void s_mri_next (int);
345static void s_mri_for (int);
346static void s_mri_endf (int);
347static void s_mri_repeat (int);
348static void s_mri_until (int);
349static void s_mri_while (int);
350static void s_mri_endw (int);
252b5132
RH		 351
352static int current_architecture;
6b6e92f4 353static int current_chip;
252b5132 354
dc84e067
NC		 355struct m68k_cpu
356 {
357 unsigned long arch;
6b6e92f4 358 unsigned long chip;
dc84e067
NC		 359 const char *name;
360 int alias;
361 };
252b5132 362
dc84e067
NC		 363static const struct m68k_cpu archs[] =
364 {
6b6e92f4
NC		 365 { m68000, m68000, "68000", 0 },
366 { m68010, m68010, "68010", 0 },
367 { m68020, m68020, "68020", 0 },
368 { m68030, m68030, "68030", 0 },
369 { m68040, m68040, "68040", 0 },
370 { m68060, m68060, "68060", 0 },
371 { cpu32, cpu32, "cpu32", 0 },
372 { m68881, m68881, "68881", 0 },
373 { m68851, m68851, "68851", 0 },
374 { mcfisa_a, mcf5200, "5200", 0 },
375 { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 },
376 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 },
377 { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 },
378 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 },
379 { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 },
380 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 },
381 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 },
382 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 },
dc84e067
NC		 383 /* Aliases (effectively, so far as gas is concerned) for the above
384 cpus. */
6b6e92f4
NC		 385 { m68020, m68020, "68k", 1 },
386 { m68000, m68000, "68008", 1 },
387 { m68000, m68000, "68302", 1 },
388 { m68000, m68000, "68306", 1 },
389 { m68000, m68000, "68307", 1 },
390 { m68000, m68000, "68322", 1 },
391 { m68000, m68000, "68356", 1 },
392 { m68000, m68000, "68ec000", 1 },
393 { m68000, m68000, "68hc000", 1 },
394 { m68000, m68000, "68hc001", 1 },
395 { m68020, m68020, "68ec020", 1 },
396 { m68030, m68030, "68ec030", 1 },
397 { m68040, m68040, "68ec040", 1 },
398 { m68060, m68060, "68ec060", 1 },
399 { cpu32, cpu32, "68330", 1 },
400 { cpu32, cpu32, "68331", 1 },
401 { cpu32, cpu32, "68332", 1 },
402 { cpu32, cpu32, "68333", 1 },
403 { cpu32, cpu32, "68334", 1 },
404 { cpu32, cpu32, "68336", 1 },
405 { cpu32, cpu32, "68340", 1 },
406 { cpu32, cpu32, "68341", 1 },
407 { cpu32, cpu32, "68349", 1 },
408 { cpu32, cpu32, "68360", 1 },
409 { m68881, m68881, "68882", 1 },
410 { mcfisa_a, mcf5200, "5202", 1 },
411 { mcfisa_a, mcf5200, "5204", 1 },
412 { mcfisa_a, mcf5200, "5206", 1 },
413 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 },
414 { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 },
415 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 },
416 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 },
417 { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 },
418 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 },
419 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 },
420 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 },
421 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 },
422 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 },
423 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 },
424 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 },
425 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 },
426 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 },
427 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 },
428 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 },
429 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 },
430 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 },
431 { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 },
dc84e067 432 };
252b5132
RH		 433
434static const int n_archs = sizeof (archs) / sizeof (archs[0]);
435
151337e8
NC		 436/* This is the assembler relaxation table for m68k. m68k is a rich CISC
437 architecture and we have a lot of relaxation modes. */
252b5132 438
151337e8
NC		 439/* Macros used in the relaxation code. */
440#define TAB(x,y) (((x) << 2) + (y))
441#define TABTYPE(x) ((x) >> 2)
442
443/* Relaxation states. */
444#define BYTE 0
445#define SHORT 1
446#define LONG 2
447#define SZ_UNDEF 3
448
449/* Here are all the relaxation modes we support. First we can relax ordinary
450 branches. On 68020 and higher and on CPU32 all branch instructions take
451 three forms, so on these CPUs all branches always remain as such. When we
452 have to expand to the LONG form on a 68000, though, we substitute an
453 absolute jump instead. This is a direct replacement for unconditional
454 branches and a branch over a jump for conditional branches. However, if the
455 user requires PIC and disables this with --pcrel, we can only relax between
456 BYTE and SHORT forms, punting if that isn't enough. This gives us four
457 different relaxation modes for branches: */
458
36759679
NC		 459#define BRANCHBWL 0 /* Branch byte, word, or long. */
460#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
461#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
462#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 463
464/* We also relax coprocessor branches and DBcc's. All CPUs that support
465 coprocessor branches support them in word and long forms, so we have only
466 one relaxation mode for them. DBcc's are word only on all CPUs. We can
467 relax them to the LONG form with a branch-around sequence. This sequence
468 can use a long branch (if available) or an absolute jump (if acceptable).
469 This gives us two relaxation modes. If long branches are not available and
470 absolute jumps are not acceptable, we don't relax DBcc's. */
471
36759679
NC		 472#define FBRANCH 4 /* Coprocessor branch. */
473#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
474#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 475
476/* That's all for instruction relaxation. However, we also relax PC-relative
477 operands. Specifically, we have three operand relaxation modes. On the
478 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
479 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
480 two. Also PC+displacement+index operands in their simple form (with a non-
481 suppressed index without memory indirection) are supported on all CPUs, but
482 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
483 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
484 form of the PC+displacement+index operand. Finally, some absolute operands
485 can be relaxed down to 16-bit PC-relative. */
486
36759679
NC		 487#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
488#define PCINDEX 8 /* PC + displacement + index. */
489#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 490
491/* Note that calls to frag_var need to specify the maximum expansion
492 needed; this is currently 10 bytes for DBCC. */
493
494/* The fields are:
495 How far Forward this mode will reach:
496 How far Backward this mode will reach:
497 How many bytes this mode will add to the size of the frag
498 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 499
500 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 501relax_typeS md_relax_table[] =
502{
ac62c346
AM		 503 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
504 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
505 { 0, 0, 4, 0 },
506 { 1, 1, 0, 0 },
507
508 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
509 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
510 { 0, 0, 4, 0 },
511 { 1, 1, 0, 0 },
512
513 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
514 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
515 { 0, 0, 6, 0 },
516 { 1, 1, 0, 0 },
517
518 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
519 { 0, 0, 2, 0 },
520 { 1, 1, 0, 0 },
521 { 1, 1, 0, 0 },
522
36759679 523 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 524 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
525 { 0, 0, 4, 0 },
526 { 1, 1, 0, 0 },
527
36759679 528 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 529 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
530 { 0, 0, 10, 0 },
531 { 1, 1, 0, 0 },
532
36759679 533 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 534 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
535 { 0, 0, 10, 0 },
536 { 1, 1, 0, 0 },
537
36759679 538 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 539 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
540 { 0, 0, 6, 0 },
541 { 1, 1, 0, 0 },
542
543 { 125, -130, 0, TAB (PCINDEX, SHORT) },
544 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
545 { 0, 0, 4, 0 },
546 { 1, 1, 0, 0 },
547
36759679 548 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 549 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
550 { 0, 0, 4, 0 },
551 { 1, 1, 0, 0 },
252b5132
RH		 552};
553
554/* These are the machine dependent pseudo-ops. These are included so
555 the assembler can work on the output from the SUN C compiler, which
36759679 556 generates these. */
252b5132
RH		 557
558/* This table describes all the machine specific pseudo-ops the assembler
559 has to support. The fields are:
560 pseudo-op name without dot
561 function to call to execute this pseudo-op
36759679 562 Integer arg to pass to the function. */
252b5132
RH		 563const pseudo_typeS md_pseudo_table[] =
564{
565 {"data1", s_data1, 0},
566 {"data2", s_data2, 0},
567 {"bss", s_bss, 0},
568 {"even", s_even, 0},
569 {"skip", s_space, 0},
570 {"proc", s_proc, 0},
571#if defined (TE_SUN3) || defined (OBJ_ELF)
572 {"align", s_align_bytes, 0},
573#endif
574#ifdef OBJ_ELF
575 {"swbeg", s_ignore, 0},
576#endif
577 {"extend", float_cons, 'x'},
578 {"ldouble", float_cons, 'x'},
579
580 /* The following pseudo-ops are supported for MRI compatibility. */
581 {"chip", s_chip, 0},
582 {"comline", s_space, 1},
583 {"fopt", s_fopt, 0},
584 {"mask2", s_ignore, 0},
585 {"opt", s_opt, 0},
586 {"reg", s_reg, 0},
587 {"restore", s_restore, 0},
588 {"save", s_save, 0},
589
590 {"if", s_mri_if, 0},
591 {"if.b", s_mri_if, 'b'},
592 {"if.w", s_mri_if, 'w'},
593 {"if.l", s_mri_if, 'l'},
594 {"else", s_mri_else, 0},
595 {"else.s", s_mri_else, 's'},
596 {"else.l", s_mri_else, 'l'},
597 {"endi", s_mri_endi, 0},
598 {"break", s_mri_break, 0},
599 {"break.s", s_mri_break, 's'},
600 {"break.l", s_mri_break, 'l'},
601 {"next", s_mri_next, 0},
602 {"next.s", s_mri_next, 's'},
603 {"next.l", s_mri_next, 'l'},
604 {"for", s_mri_for, 0},
605 {"for.b", s_mri_for, 'b'},
606 {"for.w", s_mri_for, 'w'},
607 {"for.l", s_mri_for, 'l'},
608 {"endf", s_mri_endf, 0},
609 {"repeat", s_mri_repeat, 0},
610 {"until", s_mri_until, 0},
611 {"until.b", s_mri_until, 'b'},
612 {"until.w", s_mri_until, 'w'},
613 {"until.l", s_mri_until, 'l'},
614 {"while", s_mri_while, 0},
615 {"while.b", s_mri_while, 'b'},
616 {"while.w", s_mri_while, 'w'},
617 {"while.l", s_mri_while, 'l'},
618 {"endw", s_mri_endw, 0},
619
620 {0, 0, 0}
621};
622
252b5132 623/* The mote pseudo ops are put into the opcode table, since they
31302357 624 don't start with a . they look like opcodes to gas. */
252b5132 625
5a38dc70 626const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 627{
628
629 {"dcl", cons, 4},
630 {"dc", cons, 2},
631 {"dcw", cons, 2},
632 {"dcb", cons, 1},
633
634 {"dsl", s_space, 4},
635 {"ds", s_space, 2},
636 {"dsw", s_space, 2},
637 {"dsb", s_space, 1},
638
639 {"xdef", s_globl, 0},
640#ifdef OBJ_ELF
641 {"align", s_align_bytes, 0},
642#else
643 {"align", s_align_ptwo, 0},
644#endif
645#ifdef M68KCOFF
646 {"sect", obj_coff_section, 0},
647 {"section", obj_coff_section, 0},
648#endif
649 {0, 0, 0}
650};
651
bd17c2c3
AM		 652/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
653 gives identical results to a 32-bit host. */
654#define TRUNC(X) ((valueT) (X) & 0xffffffff)
655#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
656
657#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
658#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
659#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
660#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
661
662#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
663#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 664#define islong(x) (1)
665
252b5132
RH		 666static char notend_table[256];
667static char alt_notend_table[256];
668#define notend(s) \
669 (! (notend_table[(unsigned char) *s] \
670 || (*s == ':' \
671 && alt_notend_table[(unsigned char) s[1]])))
672
6b6e92f4
NC		 673/* Return a human readable string holding the list of chips that are
674 valid for a particular architecture, suppressing aliases (unless
675 there is only one of them). */
676
677static char *
678find_cf_chip (int architecture)
679{
680 static char buf[1024];
681 int i, j, n_chips, n_alias;
682 char *cp;
683
684 strcpy (buf, " (");
685 cp = buf + strlen (buf);
686
687 for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i)
688 if (archs[i].arch & architecture)
689 {
690 n_chips++;
691 if (archs[i].alias)
692 n_alias++;
693 }
694
695 if (n_chips == 0)
696 as_fatal (_("no matching ColdFire architectures found"));
697
698 if (n_alias > 1)
699 n_chips -= n_alias;
700
701 for (i = 0, j = 0; i < n_archs && j < n_chips; ++i)
702 if (archs[i].arch & architecture)
703 {
704 if (j)
705 {
31302357 706 if ((j == n_chips - 1 && !(n_alias > 1)) || ! n_alias)
6b6e92f4
NC		 707 {
708 if (n_chips == 2)
709 {
710 strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf)));
711 cp += strlen (cp);
712 }
713 else
714 {
715 strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf)));
716 cp += strlen (cp);
717 }
718 }
719 else
720 {
721 strncpy (cp, ", ", (sizeof (buf) - (cp - buf)));
722 cp += strlen (cp);
723 }
724 }
725 strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf)));
726 cp += strlen (cp);
727 j++;
728 }
729
730 if (n_alias > 1)
731 {
732 strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf)));
733 cp += strlen (cp);
734 }
735
736 strncpy (cp, ")", (sizeof (buf) - (cp - buf)));
737
738 return buf;
739}
740
252b5132
RH		 741#ifdef OBJ_ELF
742
c801568a
AM		 743/* Return zero if the reference to SYMBOL from within the same segment may
744 be relaxed. */
745
746/* On an ELF system, we can't relax an externally visible symbol,
747 because it may be overridden by a shared library. However, if
748 TARGET_OS is "elf", then we presume that we are assembling for an
749 embedded system, in which case we don't have to worry about shared
750 libraries, and we can relax any external sym. */
751
752#define relaxable_symbol(symbol) \
6358301e 753 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 754 || S_IS_WEAK (symbol)))
755
252b5132
RH		 756/* Compute the relocation code for a fixup of SIZE bytes, using pc
757 relative relocation if PCREL is non-zero. PIC says whether a special
758 pic relocation was requested. */
759
252b5132 760static bfd_reloc_code_real_type
31302357 761get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 762{
763 switch (pic)
764 {
765 case pic_got_pcrel:
766 switch (size)
767 {
768 case 1:
769 return BFD_RELOC_8_GOT_PCREL;
770 case 2:
771 return BFD_RELOC_16_GOT_PCREL;
772 case 4:
773 return BFD_RELOC_32_GOT_PCREL;
774 }
775 break;
776
777 case pic_got_off:
778 switch (size)
779 {
780 case 1:
781 return BFD_RELOC_8_GOTOFF;
782 case 2:
783 return BFD_RELOC_16_GOTOFF;
784 case 4:
785 return BFD_RELOC_32_GOTOFF;
786 }
787 break;
788
789 case pic_plt_pcrel:
790 switch (size)
791 {
792 case 1:
793 return BFD_RELOC_8_PLT_PCREL;
794 case 2:
795 return BFD_RELOC_16_PLT_PCREL;
796 case 4:
797 return BFD_RELOC_32_PLT_PCREL;
798 }
799 break;
800
801 case pic_plt_off:
802 switch (size)
803 {
804 case 1:
805 return BFD_RELOC_8_PLTOFF;
806 case 2:
807 return BFD_RELOC_16_PLTOFF;
808 case 4:
809 return BFD_RELOC_32_PLTOFF;
810 }
811 break;
812
813 case pic_none:
814 if (pcrel)
815 {
816 switch (size)
817 {
818 case 1:
819 return BFD_RELOC_8_PCREL;
820 case 2:
821 return BFD_RELOC_16_PCREL;
822 case 4:
823 return BFD_RELOC_32_PCREL;
824 }
825 }
826 else
827 {
828 switch (size)
829 {
830 case 1:
831 return BFD_RELOC_8;
832 case 2:
833 return BFD_RELOC_16;
834 case 4:
835 return BFD_RELOC_32;
836 }
837 }
838 }
839
840 if (pcrel)
841 {
842 if (pic == pic_none)
843 as_bad (_("Can not do %d byte pc-relative relocation"), size);
844 else
845 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
846 }
847 else
848 {
849 if (pic == pic_none)
850 as_bad (_("Can not do %d byte relocation"), size);
851 else
852 as_bad (_("Can not do %d byte pic relocation"), size);
853 }
854
855 return BFD_RELOC_NONE;
856}
857
858/* Here we decide which fixups can be adjusted to make them relative
859 to the beginning of the section instead of the symbol. Basically
860 we need to make sure that the dynamic relocations are done
861 correctly, so in some cases we force the original symbol to be
862 used. */
863int
31302357 864tc_m68k_fix_adjustable (fixS *fixP)
252b5132 865{
36759679 866 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 867 switch (fixP->fx_r_type)
868 {
869 case BFD_RELOC_8_GOT_PCREL:
870 case BFD_RELOC_16_GOT_PCREL:
871 case BFD_RELOC_32_GOT_PCREL:
872 case BFD_RELOC_8_GOTOFF:
873 case BFD_RELOC_16_GOTOFF:
874 case BFD_RELOC_32_GOTOFF:
875 case BFD_RELOC_8_PLT_PCREL:
876 case BFD_RELOC_16_PLT_PCREL:
877 case BFD_RELOC_32_PLT_PCREL:
878 case BFD_RELOC_8_PLTOFF:
879 case BFD_RELOC_16_PLTOFF:
880 case BFD_RELOC_32_PLTOFF:
881 return 0;
882
883 case BFD_RELOC_VTABLE_INHERIT:
884 case BFD_RELOC_VTABLE_ENTRY:
885 return 0;
886
887 default:
888 return 1;
889 }
890}
891
892#else /* !OBJ_ELF */
893
894#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
895
c801568a
AM		 896#define relaxable_symbol(symbol) 1
897
252b5132
RH		 898#endif /* OBJ_ELF */
899
252b5132 900arelent *
31302357 901tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 902{
903 arelent *reloc;
904 bfd_reloc_code_real_type code;
905
8ec6253e
NC		 906 /* If the tcbit is set, then this was a fixup of a negative value
907 that was never resolved. We do not have a reloc to handle this,
908 so just return. We assume that other code will have detected this
909 situation and produced a helpful error message, so we just tell the
910 user that the reloc cannot be produced. */
252b5132 911 if (fixp->fx_tcbit)
8ec6253e
NC		 912 {
913 if (fixp->fx_addsy)
b091f402
AM		 914 as_bad_where (fixp->fx_file, fixp->fx_line,
915 _("Unable to produce reloc against symbol '%s'"),
916 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 917 return NULL;
918 }
252b5132
RH		 919
920 if (fixp->fx_r_type != BFD_RELOC_NONE)
921 {
922 code = fixp->fx_r_type;
923
924 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
925 that fixup_segment converted a non-PC relative reloc into a
926 PC relative reloc. In such a case, we need to convert the
927 reloc code. */
928 if (fixp->fx_pcrel)
929 {
930 switch (code)
931 {
932 case BFD_RELOC_8:
933 code = BFD_RELOC_8_PCREL;
934 break;
935 case BFD_RELOC_16:
936 code = BFD_RELOC_16_PCREL;
937 break;
938 case BFD_RELOC_32:
939 code = BFD_RELOC_32_PCREL;
940 break;
941 case BFD_RELOC_8_PCREL:
942 case BFD_RELOC_16_PCREL:
943 case BFD_RELOC_32_PCREL:
944 case BFD_RELOC_8_GOT_PCREL:
945 case BFD_RELOC_16_GOT_PCREL:
946 case BFD_RELOC_32_GOT_PCREL:
947 case BFD_RELOC_8_GOTOFF:
948 case BFD_RELOC_16_GOTOFF:
949 case BFD_RELOC_32_GOTOFF:
950 case BFD_RELOC_8_PLT_PCREL:
951 case BFD_RELOC_16_PLT_PCREL:
952 case BFD_RELOC_32_PLT_PCREL:
953 case BFD_RELOC_8_PLTOFF:
954 case BFD_RELOC_16_PLTOFF:
955 case BFD_RELOC_32_PLTOFF:
956 break;
957 default:
958 as_bad_where (fixp->fx_file, fixp->fx_line,
959 _("Cannot make %s relocation PC relative"),
960 bfd_get_reloc_code_name (code));
961 }
962 }
963 }
964 else
965 {
966#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
967 switch (F (fixp->fx_size, fixp->fx_pcrel))
968 {
969#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
970 MAP (1, 0, BFD_RELOC_8);
971 MAP (2, 0, BFD_RELOC_16);
972 MAP (4, 0, BFD_RELOC_32);
973 MAP (1, 1, BFD_RELOC_8_PCREL);
974 MAP (2, 1, BFD_RELOC_16_PCREL);
975 MAP (4, 1, BFD_RELOC_32_PCREL);
976 default:
977 abort ();
978 }
979 }
980#undef F
981#undef MAP
982
983 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 984 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
985 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 986 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
987#ifndef OBJ_ELF
988 if (fixp->fx_pcrel)
989 reloc->addend = fixp->fx_addnumber;
990 else
991 reloc->addend = 0;
992#else
993 if (!fixp->fx_pcrel)
994 reloc->addend = fixp->fx_addnumber;
995 else
996 reloc->addend = (section->vma
8390138c
AS		 997 /* Explicit sign extension in case char is
998 unsigned. */
999 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1000 + fixp->fx_addnumber
1001 + md_pcrel_from (fixp));
1002#endif
1003
1004 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1005 assert (reloc->howto != 0);
1006
1007 return reloc;
1008}
1009
252b5132
RH		 1010/* Handle of the OPCODE hash table. NULL means any use before
1011 m68k_ip_begin() will crash. */
1012static struct hash_control *op_hash;
1013\f
1014/* Assemble an m68k instruction. */
1015
1016static void
31302357 1017m68k_ip (char *instring)
252b5132
RH		 1018{
1019 register char *p;
1020 register struct m68k_op *opP;
1021 register const struct m68k_incant *opcode;
1022 register const char *s;
1023 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1024 char *pdot, *pdotmove;
1025 enum m68k_size siz1, siz2;
1026 char c;
1027 int losing;
1028 int opsfound;
03b13e59 1029 struct m68k_op operands_backup[6];
252b5132
RH		 1030 LITTLENUM_TYPE words[6];
1031 LITTLENUM_TYPE *wordp;
1032 unsigned long ok_arch = 0;
1033
1034 if (*instring == ' ')
36759679 1035 instring++; /* Skip leading whitespace. */
252b5132
RH		 1036
1037 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1038 or exactly 1 space. */
252b5132
RH		 1039 pdot = 0;
1040 for (p = instring; *p != '\0'; p++)
1041 {
1042 if (*p == ' ')
1043 break;
1044 if (*p == '.')
1045 pdot = p;
1046 }
1047
1048 if (p == instring)
1049 {
1050 the_ins.error = _("No operator");
1051 return;
1052 }
1053
1054 /* p now points to the end of the opcode name, probably whitespace.
1055 Make sure the name is null terminated by clobbering the
1056 whitespace, look it up in the hash table, then fix it back.
1057 Remove a dot, first, since the opcode tables have none. */
1058 if (pdot != NULL)
1059 {
1060 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1061 *pdotmove = pdotmove[1];
1062 p--;
1063 }
1064
1065 c = *p;
1066 *p = '\0';
1067 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1068 *p = c;
1069
1070 if (pdot != NULL)
1071 {
1072 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1073 *pdotmove = pdotmove[-1];
1074 *pdot = '.';
1075 ++p;
1076 }
1077
1078 if (opcode == NULL)
1079 {
1080 the_ins.error = _("Unknown operator");
1081 return;
1082 }
1083
36759679 1084 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1085 while (*p == ' ')
1086 ++p;
1087
1088 if (opcode->m_operands == 0)
1089 {
1090 char *old = input_line_pointer;
1091 *old = '\n';
1092 input_line_pointer = p;
36759679 1093 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1094 mote_pseudo_table[opcode->m_opnum].poc_handler
1095 (mote_pseudo_table[opcode->m_opnum].poc_val);
1096 input_line_pointer = old;
1097 *old = 0;
1098
1099 return;
1100 }
1101
1102 if (flag_mri && opcode->m_opnum == 0)
1103 {
1104 /* In MRI mode, random garbage is allowed after an instruction
1105 which accepts no operands. */
1106 the_ins.args = opcode->m_operands;
1107 the_ins.numargs = opcode->m_opnum;
1108 the_ins.numo = opcode->m_codenum;
1109 the_ins.opcode[0] = getone (opcode);
1110 the_ins.opcode[1] = gettwo (opcode);
1111 return;
1112 }
1113
1114 for (opP = &the_ins.operands[0]; *p; opP++)
1115 {
1116 p = crack_operand (p, opP);
1117
1118 if (opP->error)
1119 {
1120 the_ins.error = opP->error;
1121 return;
1122 }
1123 }
1124
1125 opsfound = opP - &the_ins.operands[0];
1126
1127 /* This ugly hack is to support the floating pt opcodes in their
1128 standard form. Essentially, we fake a first enty of type COP#1 */
1129 if (opcode->m_operands[0] == 'I')
1130 {
1131 int n;
1132
1133 for (n = opsfound; n > 0; --n)
1134 the_ins.operands[n] = the_ins.operands[n - 1];
1135
31302357 1136 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1137 the_ins.operands[0].mode = CONTROL;
1138 the_ins.operands[0].reg = m68k_float_copnum;
1139 opsfound++;
1140 }
1141
36759679 1142 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1143 for (losing = 0;;)
1144 {
1145 /* If we didn't get the right number of ops, or we have no
92774660 1146 common model with this pattern then reject this pattern. */
252b5132
RH		 1147
1148 ok_arch |= opcode->m_arch;
1149 if (opsfound != opcode->m_opnum
1150 || ((opcode->m_arch & current_architecture) == 0))
1151 ++losing;
1152 else
1153 {
03b13e59
NC		 1154 int i;
1155
1156 /* Make a copy of the operands of this insn so that
1157 we can modify them safely, should we want to. */
1158 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1159 for (i = 0; i < opsfound; i++)
1160 operands_backup[i] = the_ins.operands[i];
1161
1162 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1163 *s && !losing;
1164 s += 2, opP++)
1165 {
1166 /* Warning: this switch is huge! */
1167 /* I've tried to organize the cases into this order:
1168 non-alpha first, then alpha by letter. Lower-case
1169 goes directly before uppercase counterpart. */
1170 /* Code with multiple case ...: gets sorted by the lowest
1171 case ... it belongs to. I hope this makes sense. */
1172 switch (*s)
1173 {
1174 case '!':
1175 switch (opP->mode)
1176 {
1177 case IMMED:
1178 case DREG:
1179 case AREG:
1180 case FPREG:
1181 case CONTROL:
1182 case AINC:
1183 case ADEC:
1184 case REGLST:
1185 losing++;
1186 break;
1187 default:
1188 break;
1189 }
1190 break;
1191
1192 case '<':
1193 switch (opP->mode)
1194 {
1195 case DREG:
1196 case AREG:
1197 case FPREG:
1198 case CONTROL:
1199 case IMMED:
1200 case ADEC:
1201 case REGLST:
1202 losing++;
1203 break;
1204 default:
1205 break;
1206 }
1207 break;
1208
1209 case '>':
1210 switch (opP->mode)
1211 {
1212 case DREG:
1213 case AREG:
1214 case FPREG:
1215 case CONTROL:
1216 case IMMED:
1217 case AINC:
1218 case REGLST:
1219 losing++;
1220 break;
1221 case ABSL:
1222 break;
1223 default:
1224 if (opP->reg == PC
1225 || opP->reg == ZPC)
1226 losing++;
1227 break;
1228 }
1229 break;
1230
1231 case 'm':
1232 switch (opP->mode)
1233 {
1234 case DREG:
1235 case AREG:
1236 case AINDR:
1237 case AINC:
1238 case ADEC:
1239 break;
1240 default:
1241 losing++;
1242 }
8a104df9 1243 break;
252b5132
RH		 1244
1245 case 'n':
1246 switch (opP->mode)
1247 {
1248 case DISP:
1249 break;
1250 default:
1251 losing++;
1252 }
8a104df9 1253 break;
252b5132
RH		 1254
1255 case 'o':
1256 switch (opP->mode)
1257 {
1258 case BASE:
1259 case ABSL:
1260 case IMMED:
1261 break;
1262 default:
1263 losing++;
1264 }
8a104df9 1265 break;
252b5132
RH		 1266
1267 case 'p':
1268 switch (opP->mode)
1269 {
1270 case DREG:
1271 case AREG:
1272 case AINDR:
1273 case AINC:
1274 case ADEC:
1275 break;
1276 case DISP:
1277 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1278 losing++;
252b5132
RH		 1279 break;
1280 default:
1281 losing++;
1282 }
8a104df9 1283 break;
252b5132
RH		 1284
1285 case 'q':
1286 switch (opP->mode)
1287 {
1288 case DREG:
1289 case AINDR:
1290 case AINC:
1291 case ADEC:
1292 break;
1293 case DISP:
1294 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1295 losing++;
252b5132
RH		 1296 break;
1297 default:
1298 losing++;
1299 break;
1300 }
8a104df9 1301 break;
252b5132
RH		 1302
1303 case 'v':
1304 switch (opP->mode)
1305 {
1306 case DREG:
1307 case AINDR:
1308 case AINC:
1309 case ADEC:
1310 case ABSL:
1311 break;
1312 case DISP:
1313 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1314 losing++;
252b5132
RH		 1315 break;
1316 default:
1317 losing++;
1318 break;
1319 }
1320 break;
1321
1322 case '#':
1323 if (opP->mode != IMMED)
1324 losing++;
1325 else if (s[1] == 'b'
1326 && ! isvar (&opP->disp)
1327 && (opP->disp.exp.X_op != O_constant
1328 || ! isbyte (opP->disp.exp.X_add_number)))
1329 losing++;
1330 else if (s[1] == 'B'
1331 && ! isvar (&opP->disp)
1332 && (opP->disp.exp.X_op != O_constant
1333 || ! issbyte (opP->disp.exp.X_add_number)))
1334 losing++;
1335 else if (s[1] == 'w'
1336 && ! isvar (&opP->disp)
1337 && (opP->disp.exp.X_op != O_constant
1338 || ! isword (opP->disp.exp.X_add_number)))
1339 losing++;
1340 else if (s[1] == 'W'
1341 && ! isvar (&opP->disp)
1342 && (opP->disp.exp.X_op != O_constant
1343 || ! issword (opP->disp.exp.X_add_number)))
1344 losing++;
1345 break;
1346
1347 case '^':
1348 case 'T':
1349 if (opP->mode != IMMED)
1350 losing++;
1351 break;
1352
1353 case '$':
1354 if (opP->mode == AREG
1355 || opP->mode == CONTROL
1356 || opP->mode == FPREG
1357 || opP->mode == IMMED
1358 || opP->mode == REGLST
1359 || (opP->mode != ABSL
1360 && (opP->reg == PC
1361 || opP->reg == ZPC)))
1362 losing++;
1363 break;
1364
1365 case '%':
1366 if (opP->mode == CONTROL
1367 || opP->mode == FPREG
1368 || opP->mode == REGLST
1369 || opP->mode == IMMED
1370 || (opP->mode != ABSL
1371 && (opP->reg == PC
1372 || opP->reg == ZPC)))
1373 losing++;
1374 break;
1375
1376 case '&':
1377 switch (opP->mode)
1378 {
1379 case DREG:
1380 case AREG:
1381 case FPREG:
1382 case CONTROL:
1383 case IMMED:
1384 case AINC:
1385 case ADEC:
1386 case REGLST:
1387 losing++;
1388 break;
1389 case ABSL:
1390 break;
1391 default:
1392 if (opP->reg == PC
1393 || opP->reg == ZPC)
1394 losing++;
1395 break;
1396 }
1397 break;
1398
1399 case '*':
1400 if (opP->mode == CONTROL
1401 || opP->mode == FPREG
1402 || opP->mode == REGLST)
1403 losing++;
1404 break;
1405
1406 case '+':
1407 if (opP->mode != AINC)
1408 losing++;
1409 break;
1410
1411 case '-':
1412 if (opP->mode != ADEC)
1413 losing++;
1414 break;
1415
1416 case '/':
1417 switch (opP->mode)
1418 {
1419 case AREG:
1420 case CONTROL:
1421 case FPREG:
1422 case AINC:
1423 case ADEC:
1424 case IMMED:
1425 case REGLST:
1426 losing++;
1427 break;
1428 default:
1429 break;
1430 }
1431 break;
1432
1433 case ';':
1434 switch (opP->mode)
1435 {
1436 case AREG:
1437 case CONTROL:
1438 case FPREG:
1439 case REGLST:
1440 losing++;
1441 break;
1442 default:
1443 break;
1444 }
1445 break;
1446
1447 case '?':
1448 switch (opP->mode)
1449 {
1450 case AREG:
1451 case CONTROL:
1452 case FPREG:
1453 case AINC:
1454 case ADEC:
1455 case IMMED:
1456 case REGLST:
1457 losing++;
1458 break;
1459 case ABSL:
1460 break;
1461 default:
1462 if (opP->reg == PC || opP->reg == ZPC)
1463 losing++;
1464 break;
1465 }
1466 break;
1467
1468 case '@':
1469 switch (opP->mode)
1470 {
1471 case AREG:
1472 case CONTROL:
1473 case FPREG:
1474 case IMMED:
1475 case REGLST:
1476 losing++;
1477 break;
1478 default:
1479 break;
1480 }
1481 break;
1482
1483 case '~': /* For now! (JF FOO is this right?) */
1484 switch (opP->mode)
1485 {
1486 case DREG:
1487 case AREG:
1488 case CONTROL:
1489 case FPREG:
1490 case IMMED:
1491 case REGLST:
1492 losing++;
1493 break;
1494 case ABSL:
1495 break;
1496 default:
1497 if (opP->reg == PC
1498 || opP->reg == ZPC)
1499 losing++;
1500 break;
1501 }
1502 break;
1503
1504 case '3':
1505 if (opP->mode != CONTROL
1506 || (opP->reg != TT0 && opP->reg != TT1))
1507 losing++;
1508 break;
1509
1510 case 'A':
1511 if (opP->mode != AREG)
1512 losing++;
1513 break;
1514
1515 case 'a':
1516 if (opP->mode != AINDR)
1517 ++losing;
1518 break;
1519
fd99574b
NC		 1520 case '4':
1521 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1522 && (opP->mode != DISP
1523 || opP->reg < ADDR0
1524 || opP->reg > ADDR7))
1525 ++losing;
1526 break;
1527
252b5132
RH		 1528 case 'B': /* FOO */
1529 if (opP->mode != ABSL
1530 || (flag_long_jumps
1531 && strncmp (instring, "jbsr", 4) == 0))
1532 losing++;
1533 break;
1534
3e602632
NC		 1535 case 'b':
1536 switch (opP->mode)
1537 {
1538 case IMMED:
1539 case ABSL:
1540 case AREG:
1541 case FPREG:
1542 case CONTROL:
1543 case POST:
1544 case PRE:
1545 case REGLST:
1546 losing++;
1547 break;
1548 default:
1549 break;
1550 }
1551 break;
1552
252b5132
RH		 1553 case 'C':
1554 if (opP->mode != CONTROL || opP->reg != CCR)
1555 losing++;
1556 break;
1557
1558 case 'd':
1559 if (opP->mode != DISP
1560 || opP->reg < ADDR0
1561 || opP->reg > ADDR7)
1562 losing++;
1563 break;
1564
1565 case 'D':
1566 if (opP->mode != DREG)
1567 losing++;
1568 break;
1569
6da466c7
ILT		 1570 case 'E':
1571 if (opP->reg != ACC)
1572 losing++;
1573 break;
1574
fd99574b
NC		 1575 case 'e':
1576 if (opP->reg != ACC && opP->reg != ACC1
1577 && opP->reg != ACC2 && opP->reg != ACC3)
1578 losing++;
1579 break;
1580
252b5132
RH		 1581 case 'F':
1582 if (opP->mode != FPREG)
1583 losing++;
1584 break;
1585
6da466c7
ILT		 1586 case 'G':
1587 if (opP->reg != MACSR)
1588 losing++;
1589 break;
1590
fd99574b
NC		 1591 case 'g':
1592 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1593 losing++;
1594 break;
1595
6da466c7
ILT		 1596 case 'H':
1597 if (opP->reg != MASK)
1598 losing++;
1599 break;
1600
252b5132
RH		 1601 case 'I':
1602 if (opP->mode != CONTROL
1603 || opP->reg < COP0
1604 || opP->reg > COP7)
1605 losing++;
1606 break;
1607
fd99574b
NC		 1608 case 'i':
1609 if (opP->mode != LSH && opP->mode != RSH)
1610 losing++;
1611 break;
1612
252b5132
RH		 1613 case 'J':
1614 if (opP->mode != CONTROL
1615 || opP->reg < USP
1616 || opP->reg > last_movec_reg)
1617 losing++;
1618 else
1619 {
1620 const enum m68k_register *rp;
1621 for (rp = control_regs; *rp; rp++)
1622 if (*rp == opP->reg)
1623 break;
1624 if (*rp == 0)
1625 losing++;
1626 }
1627 break;
1628
1629 case 'k':
1630 if (opP->mode != IMMED)
1631 losing++;
1632 break;
1633
1634 case 'l':
1635 case 'L':
1636 if (opP->mode == DREG
1637 || opP->mode == AREG
1638 || opP->mode == FPREG)
1639 {
1640 if (s[1] == '8')
1641 losing++;
1642 else
1643 {
1644 switch (opP->mode)
1645 {
1646 case DREG:
1647 opP->mask = 1 << (opP->reg - DATA0);
1648 break;
1649 case AREG:
1650 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1651 break;
1652 case FPREG:
1653 opP->mask = 1 << (opP->reg - FP0 + 16);
1654 break;
1655 default:
1656 abort ();
1657 }
1658 opP->mode = REGLST;
1659 }
1660 }
1661 else if (opP->mode == CONTROL)
1662 {
1663 if (s[1] != '8')
1664 losing++;
1665 else
1666 {
1667 switch (opP->reg)
1668 {
1669 case FPI:
1670 opP->mask = 1 << 24;
1671 break;
1672 case FPS:
1673 opP->mask = 1 << 25;
1674 break;
1675 case FPC:
1676 opP->mask = 1 << 26;
1677 break;
1678 default:
1679 losing++;
1680 break;
1681 }
1682 opP->mode = REGLST;
1683 }
1684 }
1685 else if (opP->mode != REGLST)
1686 losing++;
1687 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1688 losing++;
1689 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1690 losing++;
1691 break;
1692
1693 case 'M':
1694 if (opP->mode != IMMED)
1695 losing++;
1696 else if (opP->disp.exp.X_op != O_constant
1697 || ! issbyte (opP->disp.exp.X_add_number))
1698 losing++;
1699 else if (! m68k_quick
1700 && instring[3] != 'q'
1701 && instring[4] != 'q')
1702 losing++;
1703 break;
1704
1705 case 'O':
1706 if (opP->mode != DREG
1707 && opP->mode != IMMED
1708 && opP->mode != ABSL)
1709 losing++;
1710 break;
1711
1712 case 'Q':
1713 if (opP->mode != IMMED)
1714 losing++;
1715 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1716 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1717 losing++;
1718 else if (! m68k_quick
1719 && (strncmp (instring, "add", 3) == 0
1720 || strncmp (instring, "sub", 3) == 0)
1721 && instring[3] != 'q')
1722 losing++;
1723 break;
1724
1725 case 'R':
1726 if (opP->mode != DREG && opP->mode != AREG)
1727 losing++;
1728 break;
1729
1730 case 'r':
1731 if (opP->mode != AINDR
1732 && (opP->mode != BASE
1733 || (opP->reg != 0
1734 && opP->reg != ZADDR0)
1735 || opP->disp.exp.X_op != O_absent
1736 || ((opP->index.reg < DATA0
1737 || opP->index.reg > DATA7)
1738 && (opP->index.reg < ADDR0
1739 || opP->index.reg > ADDR7))
1740 || opP->index.size != SIZE_UNSPEC
1741 || opP->index.scale != 1))
1742 losing++;
1743 break;
1744
1745 case 's':
1746 if (opP->mode != CONTROL
1747 || ! (opP->reg == FPI
1748 || opP->reg == FPS
1749 || opP->reg == FPC))
1750 losing++;
1751 break;
1752
1753 case 'S':
1754 if (opP->mode != CONTROL || opP->reg != SR)
1755 losing++;
1756 break;
1757
1758 case 't':
1759 if (opP->mode != IMMED)
1760 losing++;
1761 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1762 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1763 losing++;
1764 break;
1765
1766 case 'U':
1767 if (opP->mode != CONTROL || opP->reg != USP)
1768 losing++;
1769 break;
1770
3e602632
NC		 1771 case 'x':
1772 if (opP->mode != IMMED)
1773 losing++;
1774 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1775 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1776 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1777 losing++;
1778 break;
1779
252b5132
RH		 1780 /* JF these are out of order. We could put them
1781 in order if we were willing to put up with
1782 bunches of #ifdef m68851s in the code.
1783
1784 Don't forget that you need these operands
1785 to use 68030 MMU instructions. */
1786#ifndef NO_68851
36759679 1787 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1788 case '|':
1789 if (opP->mode == CONTROL
1790 || opP->mode == FPREG
1791 || opP->mode == DREG
1792 || opP->mode == AREG
1793 || opP->mode == REGLST)
1794 losing++;
1795 /* We should accept immediate operands, but they
1796 supposedly have to be quad word, and we don't
1797 handle that. I would like to see what a Motorola
1798 assembler does before doing something here. */
1799 if (opP->mode == IMMED)
1800 losing++;
1801 break;
1802
1803 case 'f':
1804 if (opP->mode != CONTROL
1805 || (opP->reg != SFC && opP->reg != DFC))
1806 losing++;
1807 break;
1808
1809 case '0':
1810 if (opP->mode != CONTROL || opP->reg != TC)
1811 losing++;
1812 break;
1813
1814 case '1':
1815 if (opP->mode != CONTROL || opP->reg != AC)
1816 losing++;
1817 break;
1818
1819 case '2':
1820 if (opP->mode != CONTROL
1821 || (opP->reg != CAL
1822 && opP->reg != VAL
1823 && opP->reg != SCC))
1824 losing++;
1825 break;
1826
1827 case 'V':
1828 if (opP->mode != CONTROL
1829 || opP->reg != VAL)
1830 losing++;
1831 break;
1832
1833 case 'W':
1834 if (opP->mode != CONTROL
1835 || (opP->reg != DRP
1836 && opP->reg != SRP
1837 && opP->reg != CRP))
1838 losing++;
1839 break;
1840
3e602632
NC		 1841 case 'w':
1842 switch (opP->mode)
1843 {
1844 case IMMED:
1845 case ABSL:
1846 case AREG:
1847 case DREG:
1848 case FPREG:
1849 case CONTROL:
1850 case POST:
1851 case PRE:
1852 case REGLST:
1853 losing++;
1854 break;
1855 default:
1856 break;
1857 }
1858 break;
1859
252b5132
RH		 1860 case 'X':
1861 if (opP->mode != CONTROL
1862 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1863 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1864 losing++;
1865 break;
1866
1867 case 'Y':
1868 if (opP->mode != CONTROL || opP->reg != PSR)
1869 losing++;
1870 break;
1871
1872 case 'Z':
1873 if (opP->mode != CONTROL || opP->reg != PCSR)
1874 losing++;
1875 break;
1876#endif
1877 case 'c':
1878 if (opP->mode != CONTROL
1879 || (opP->reg != NC
1880 && opP->reg != IC
1881 && opP->reg != DC
1882 && opP->reg != BC))
36759679 1883 losing++;
252b5132
RH		 1884 break;
1885
1886 case '_':
1887 if (opP->mode != ABSL)
1888 ++losing;
1889 break;
1890
6da466c7
ILT		 1891 case 'u':
1892 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1893 losing++;
1894 /* FIXME: kludge instead of fixing parser:
1895 upper/lower registers are *not* CONTROL
92774660 1896 registers, but ordinary ones. */
6da466c7
ILT		 1897 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1898 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1899 opP->mode = DREG;
1900 else
1901 opP->mode = AREG;
1902 break;
1903
3e602632
NC		 1904 case 'y':
1905 if (!(opP->mode == AINDR
31302357
AS		 1906 || (opP->mode == DISP
1907 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 1908 losing++;
1909 break;
1910
1911 case 'z':
1912 if (!(opP->mode == AINDR || opP->mode == DISP))
1913 losing++;
1914 break;
1915
252b5132
RH		 1916 default:
1917 abort ();
36759679 1918 }
252b5132
RH		 1919
1920 if (losing)
1921 break;
36759679 1922 }
03b13e59
NC		 1923
1924 /* Since we have found the correct instruction, copy
1925 in the modifications that we may have made. */
1926 if (!losing)
1927 for (i = 0; i < opsfound; i++)
1928 the_ins.operands[i] = operands_backup[i];
36759679 1929 }
252b5132
RH		 1930
1931 if (!losing)
36759679 1932 break;
252b5132
RH		 1933
1934 opcode = opcode->m_next;
1935
1936 if (!opcode)
1937 {
1938 if (ok_arch
1939 && !(ok_arch & current_architecture))
1940 {
1941 char buf[200], *cp;
1942
6b6e92f4 1943 strncpy (buf,
31302357
AS		 1944 _("invalid instruction for this architecture; needs "),
1945 sizeof (buf));
252b5132
RH		 1946 cp = buf + strlen (buf);
1947 switch (ok_arch)
1948 {
6b6e92f4 1949 case mcfisa_a:
31302357
AS		 1950 strncpy (cp, _("ColdFire ISA_A"),
1951 sizeof (buf) - (cp - buf));
6b6e92f4 1952 cp += strlen (cp);
31302357
AS		 1953 strncpy (cp, find_cf_chip (ok_arch),
1954 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 1955 cp += strlen (cp);
1956 break;
1957 case mcfhwdiv:
31302357
AS		 1958 strncpy (cp, _("ColdFire hardware divide"),
1959 sizeof (buf) - (cp - buf));
6b6e92f4 1960 cp += strlen (cp);
31302357
AS		 1961 strncpy (cp, find_cf_chip (ok_arch),
1962 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 1963 cp += strlen (cp);
1964 break;
1965 case mcfisa_aa:
31302357
AS		 1966 strncpy (cp, _("ColdFire ISA_A+"),
1967 sizeof (buf) - (cp - buf));
6b6e92f4 1968 cp += strlen (cp);
31302357
AS		 1969 strncpy (cp, find_cf_chip (ok_arch),
1970 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 1971 cp += strlen (cp);
1972 break;
1973 case mcfisa_b:
31302357
AS		 1974 strncpy (cp, _("ColdFire ISA_B"),
1975 sizeof (buf) - (cp - buf));
6b6e92f4 1976 cp += strlen (cp);
31302357
AS		 1977 strncpy (cp, find_cf_chip (ok_arch),
1978 sizeof (buf) - (cp - buf));
6b6e92f4
NC		 1979 cp += strlen (cp);
1980 break;
3e602632 1981 case cfloat:
31302357 1982 strncpy (cp, _("ColdFire fpu"), sizeof (buf) - (cp - buf));
6b6e92f4 1983 cp += strlen (cp);
31302357
AS		 1984 strncpy (cp, find_cf_chip (ok_arch),
1985 sizeof (buf) - (cp - buf));
6b6e92f4 1986 cp += strlen (cp);
3e602632 1987 break;
252b5132
RH		 1988 case mfloat:
1989 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1990 break;
1991 case mmmu:
1992 strcpy (cp, _("mmu (68030 or 68851)"));
1993 break;
1994 case m68020up:
1995 strcpy (cp, _("68020 or higher"));
1996 break;
1997 case m68000up:
1998 strcpy (cp, _("68000 or higher"));
1999 break;
2000 case m68010up:
2001 strcpy (cp, _("68010 or higher"));
2002 break;
2003 default:
2004 {
2005 int got_one = 0, idx;
6b6e92f4
NC		 2006
2007 for (idx = 0; idx < n_archs; idx++)
252b5132
RH		 2008 {
2009 if ((archs[idx].arch & ok_arch)
2010 && ! archs[idx].alias)
2011 {
2012 if (got_one)
2013 {
2014 strcpy (cp, " or ");
2015 cp += strlen (cp);
2016 }
2017 got_one = 1;
2018 strcpy (cp, archs[idx].name);
2019 cp += strlen (cp);
2020 }
2021 }
2022 }
2023 }
2024 cp = xmalloc (strlen (buf) + 1);
2025 strcpy (cp, buf);
2026 the_ins.error = cp;
2027 }
2028 else
2029 the_ins.error = _("operands mismatch");
2030 return;
36759679 2031 }
252b5132
RH		 2032
2033 losing = 0;
2034 }
2035
36759679 2036 /* Now assemble it. */
252b5132
RH		 2037 the_ins.args = opcode->m_operands;
2038 the_ins.numargs = opcode->m_opnum;
2039 the_ins.numo = opcode->m_codenum;
2040 the_ins.opcode[0] = getone (opcode);
2041 the_ins.opcode[1] = gettwo (opcode);
2042
2043 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2044 {
2045 /* This switch is a doozy.
31302357 2046 Watch the first step; its a big one! */
252b5132
RH		 2047 switch (s[0])
2048 {
2049
2050 case '*':
2051 case '~':
2052 case '%':
2053 case ';':
2054 case '@':
2055 case '!':
2056 case '&':
2057 case '$':
2058 case '?':
2059 case '/':
2060 case '<':
2061 case '>':
3e602632 2062 case 'b':
252b5132
RH		 2063 case 'm':
2064 case 'n':
2065 case 'o':
2066 case 'p':
2067 case 'q':
2068 case 'v':
3e602632
NC		 2069 case 'w':
2070 case 'y':
2071 case 'z':
fd99574b 2072 case '4':
252b5132
RH		 2073#ifndef NO_68851
2074 case '|':
2075#endif
2076 switch (opP->mode)
2077 {
2078 case IMMED:
2079 tmpreg = 0x3c; /* 7.4 */
2080 if (strchr ("bwl", s[1]))
3e602632 2081 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2082 else
2083 nextword = get_num (&opP->disp, 0);
2084 if (isvar (&opP->disp))
2085 add_fix (s[1], &opP->disp, 0, 0);
2086 switch (s[1])
2087 {
2088 case 'b':
2089 if (!isbyte (nextword))
2090 opP->error = _("operand out of range");
2091 addword (nextword);
2092 baseo = 0;
2093 break;
2094 case 'w':
2095 if (!isword (nextword))
2096 opP->error = _("operand out of range");
2097 addword (nextword);
2098 baseo = 0;
2099 break;
2100 case 'W':
2101 if (!issword (nextword))
2102 opP->error = _("operand out of range");
2103 addword (nextword);
2104 baseo = 0;
2105 break;
2106 case 'l':
2107 addword (nextword >> 16);
2108 addword (nextword);
2109 baseo = 0;
2110 break;
2111
2112 case 'f':
2113 baseo = 2;
2114 outro = 8;
2115 break;
2116 case 'F':
2117 baseo = 4;
2118 outro = 11;
2119 break;
2120 case 'x':
2121 baseo = 6;
2122 outro = 15;
2123 break;
2124 case 'p':
2125 baseo = 6;
2126 outro = -1;
2127 break;
2128 default:
2129 abort ();
2130 }
2131 if (!baseo)
2132 break;
2133
36759679 2134 /* We gotta put out some float. */
252b5132
RH		 2135 if (op (&opP->disp) != O_big)
2136 {
2137 valueT val;
2138 int gencnt;
2139
2140 /* Can other cases happen here? */
2141 if (op (&opP->disp) != O_constant)
2142 abort ();
2143
2144 val = (valueT) offs (&opP->disp);
2145 gencnt = 0;
2146 do
2147 {
2148 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2149 val >>= LITTLENUM_NUMBER_OF_BITS;
2150 ++gencnt;
2151 }
2152 while (val != 0);
2153 offs (&opP->disp) = gencnt;
2154 }
2155 if (offs (&opP->disp) > 0)
2156 {
2157 if (offs (&opP->disp) > baseo)
2158 {
2159 as_warn (_("Bignum too big for %c format; truncated"),
2160 s[1]);
2161 offs (&opP->disp) = baseo;
2162 }
2163 baseo -= offs (&opP->disp);
2164 while (baseo--)
2165 addword (0);
2166 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2167 offs (&opP->disp)--;
2168 --wordp)
2169 addword (*wordp);
2170 break;
2171 }
2172 gen_to_words (words, baseo, (long) outro);
2173 for (wordp = words; baseo--; wordp++)
2174 addword (*wordp);
2175 break;
2176 case DREG:
2177 tmpreg = opP->reg - DATA; /* 0.dreg */
2178 break;
2179 case AREG:
2180 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2181 break;
2182 case AINDR:
2183 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2184 break;
2185 case ADEC:
2186 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2187 break;
2188 case AINC:
2189 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2190 break;
2191 case DISP:
2192
3e602632 2193 nextword = get_num (&opP->disp, 90);
252b5132 2194
580b9172
NC		 2195 /* Convert mode 5 addressing with a zero offset into
2196 mode 2 addressing to reduce the instruction size by a
2197 word. */
2198 if (! isvar (&opP->disp)
2199 && (nextword == 0)
2200 && (opP->disp.size == SIZE_UNSPEC)
2201 && (opP->reg >= ADDR0)
2202 && (opP->reg <= ADDR7))
2203 {
2204 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2205 break;
2206 }
2207
252b5132
RH		 2208 if (opP->reg == PC
2209 && ! isvar (&opP->disp)
2210 && m68k_abspcadd)
2211 {
2212 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2213 opP->disp.exp.X_add_symbol =
2214 section_symbol (absolute_section);
252b5132
RH		 2215 }
2216
36759679 2217 /* Force into index mode. Hope this works. */
252b5132
RH		 2218
2219 /* We do the first bit for 32-bit displacements, and the
2220 second bit for 16 bit ones. It is possible that we
2221 should make the default be WORD instead of LONG, but
2222 I think that'd break GCC, so we put up with a little
2223 inefficiency for the sake of working output. */
2224
2225 if (!issword (nextword)
2226 || (isvar (&opP->disp)
2227 && ((opP->disp.size == SIZE_UNSPEC
2228 && flag_short_refs == 0
2229 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2230 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2231 || opP->disp.size == SIZE_LONG)))
2232 {
2233 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2234 || arch_coldfire_p (current_architecture))
252b5132
RH		 2235 opP->error =
2236 _("displacement too large for this architecture; needs 68020 or higher");
2237 if (opP->reg == PC)
2238 tmpreg = 0x3B; /* 7.3 */
2239 else
2240 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2241 if (isvar (&opP->disp))
2242 {
2243 if (opP->reg == PC)
2244 {
2245 if (opP->disp.size == SIZE_LONG
2246#ifdef OBJ_ELF
2247 /* If the displacement needs pic
2248 relocation it cannot be relaxed. */
2249 || opP->disp.pic_reloc != pic_none
2250#endif
2251 )
2252 {
2253 addword (0x0170);
2254 add_fix ('l', &opP->disp, 1, 2);
2255 }
2256 else
2257 {
2258 add_frag (adds (&opP->disp),
bd17c2c3 2259 SEXT (offs (&opP->disp)),
151337e8 2260 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2261 break;
2262 }
2263 }
2264 else
2265 {
2266 addword (0x0170);
2267 add_fix ('l', &opP->disp, 0, 0);
2268 }
2269 }
2270 else
2271 addword (0x0170);
2272 addword (nextword >> 16);
2273 }
2274 else
2275 {
2276 if (opP->reg == PC)
2277 tmpreg = 0x3A; /* 7.2 */
2278 else
2279 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2280
2281 if (isvar (&opP->disp))
2282 {
2283 if (opP->reg == PC)
2284 {
2285 add_fix ('w', &opP->disp, 1, 0);
2286 }
2287 else
2288 add_fix ('w', &opP->disp, 0, 0);
2289 }
2290 }
2291 addword (nextword);
2292 break;
2293
2294 case POST:
2295 case PRE:
2296 case BASE:
2297 nextword = 0;
3e602632 2298 baseo = get_num (&opP->disp, 90);
252b5132 2299 if (opP->mode == POST || opP->mode == PRE)
3e602632 2300 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2301 /* Figure out the `addressing mode'.
2302 Also turn on the BASE_DISABLE bit, if needed. */
2303 if (opP->reg == PC || opP->reg == ZPC)
2304 {
2305 tmpreg = 0x3b; /* 7.3 */
2306 if (opP->reg == ZPC)
2307 nextword |= 0x80;
2308 }
2309 else if (opP->reg == 0)
2310 {
2311 nextword |= 0x80;
2312 tmpreg = 0x30; /* 6.garbage */
2313 }
2314 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2315 {
2316 nextword |= 0x80;
2317 tmpreg = 0x30 + opP->reg - ZADDR0;
2318 }
2319 else
2320 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2321
2322 siz1 = opP->disp.size;
2323 if (opP->mode == POST || opP->mode == PRE)
2324 siz2 = opP->odisp.size;
2325 else
2326 siz2 = SIZE_UNSPEC;
2327
36759679 2328 /* Index register stuff. */
252b5132
RH		 2329 if (opP->index.reg != 0
2330 && opP->index.reg >= DATA
2331 && opP->index.reg <= ADDR7)
2332 {
2333 nextword |= (opP->index.reg - DATA) << 12;
2334
2335 if (opP->index.size == SIZE_LONG
2336 || (opP->index.size == SIZE_UNSPEC
2337 && m68k_index_width_default == SIZE_LONG))
2338 nextword |= 0x800;
2339
92774660 2340 if ((opP->index.scale != 1
252b5132 2341 && cpu_of_arch (current_architecture) < m68020)
92774660 2342 || (opP->index.scale == 8
3e602632 2343 && (arch_coldfire_p (current_architecture)
6b6e92f4 2344 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2345 {
2346 opP->error =
2347 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2348 }
2349
6da466c7
ILT		 2350 if (arch_coldfire_p (current_architecture)
2351 && opP->index.size == SIZE_WORD)
2352 opP->error = _("invalid index size for coldfire");
2353
252b5132
RH		 2354 switch (opP->index.scale)
2355 {
2356 case 1:
2357 break;
2358 case 2:
2359 nextword |= 0x200;
2360 break;
2361 case 4:
2362 nextword |= 0x400;
2363 break;
2364 case 8:
2365 nextword |= 0x600;
2366 break;
2367 default:
2368 abort ();
2369 }
2370 /* IF its simple,
2371 GET US OUT OF HERE! */
2372
2373 /* Must be INDEX, with an index register. Address
2374 register cannot be ZERO-PC, and either :b was
2375 forced, or we know it will fit. For a 68000 or
2376 68010, force this mode anyways, because the
2377 larger modes aren't supported. */
2378 if (opP->mode == BASE
2379 && ((opP->reg >= ADDR0
2380 && opP->reg <= ADDR7)
2381 || opP->reg == PC))
2382 {
2383 if (siz1 == SIZE_BYTE
2384 || cpu_of_arch (current_architecture) < m68020
6da466c7 2385 || arch_coldfire_p (current_architecture)
252b5132
RH		 2386 || (siz1 == SIZE_UNSPEC
2387 && ! isvar (&opP->disp)
2388 && issbyte (baseo)))
2389 {
2390 nextword += baseo & 0xff;
2391 addword (nextword);
2392 if (isvar (&opP->disp))
2393 {
2394 /* Do a byte relocation. If it doesn't
2395 fit (possible on m68000) let the
2396 fixup processing complain later. */
2397 if (opP->reg == PC)
2398 add_fix ('B', &opP->disp, 1, 1);
2399 else
2400 add_fix ('B', &opP->disp, 0, 0);
2401 }
2402 else if (siz1 != SIZE_BYTE)
2403 {
2404 if (siz1 != SIZE_UNSPEC)
2405 as_warn (_("Forcing byte displacement"));
2406 if (! issbyte (baseo))
2407 opP->error = _("byte displacement out of range");
2408 }
2409
2410 break;
2411 }
2412 else if (siz1 == SIZE_UNSPEC
2413 && opP->reg == PC
2414 && isvar (&opP->disp)
2415 && subs (&opP->disp) == NULL
2416#ifdef OBJ_ELF
2417 /* If the displacement needs pic
2418 relocation it cannot be relaxed. */
2419 && opP->disp.pic_reloc == pic_none
2420#endif
2421 )
2422 {
2423 /* The code in md_convert_frag_1 needs to be
2424 able to adjust nextword. Call frag_grow
2425 to ensure that we have enough space in
2426 the frag obstack to make all the bytes
2427 contiguous. */
2428 frag_grow (14);
8a104df9
KH		 2429 nextword += baseo & 0xff;
2430 addword (nextword);
bd17c2c3
AM		 2431 add_frag (adds (&opP->disp),
2432 SEXT (offs (&opP->disp)),
8a104df9 2433 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2434
2435 break;
8a104df9 2436 }
252b5132
RH		 2437 }
2438 }
2439 else
2440 {
36759679 2441 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2442 if (opP->index.reg >= ZDATA0
2443 && opP->index.reg <= ZDATA7)
2444 nextword |= (opP->index.reg - ZDATA0) << 12;
2445 else if (opP->index.reg >= ZADDR0
2446 || opP->index.reg <= ZADDR7)
2447 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2448 }
2449
2450 /* It isn't simple. */
2451
2452 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2453 || arch_coldfire_p (current_architecture))
252b5132
RH		 2454 opP->error =
2455 _("invalid operand mode for this architecture; needs 68020 or higher");
2456
2457 nextword |= 0x100;
2458 /* If the guy specified a width, we assume that it is
2459 wide enough. Maybe it isn't. If so, we lose. */
2460 switch (siz1)
2461 {
2462 case SIZE_UNSPEC:
2463 if (isvar (&opP->disp)
2464 ? m68k_rel32
2465 : ! issword (baseo))
2466 {
2467 siz1 = SIZE_LONG;
2468 nextword |= 0x30;
2469 }
2470 else if (! isvar (&opP->disp) && baseo == 0)
2471 nextword |= 0x10;
2472 else
2473 {
2474 nextword |= 0x20;
2475 siz1 = SIZE_WORD;
2476 }
2477 break;
2478 case SIZE_BYTE:
2479 as_warn (_(":b not permitted; defaulting to :w"));
2480 /* Fall through. */
2481 case SIZE_WORD:
2482 nextword |= 0x20;
2483 break;
2484 case SIZE_LONG:
2485 nextword |= 0x30;
2486 break;
2487 }
2488
67c1ffbe 2489 /* Figure out inner displacement stuff. */
252b5132
RH		 2490 if (opP->mode == POST || opP->mode == PRE)
2491 {
2492 if (cpu_of_arch (current_architecture) & cpu32)
2493 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2494 switch (siz2)
2495 {
2496 case SIZE_UNSPEC:
2497 if (isvar (&opP->odisp)
2498 ? m68k_rel32
2499 : ! issword (outro))
2500 {
2501 siz2 = SIZE_LONG;
2502 nextword |= 0x3;
2503 }
2504 else if (! isvar (&opP->odisp) && outro == 0)
2505 nextword |= 0x1;
2506 else
2507 {
2508 nextword |= 0x2;
2509 siz2 = SIZE_WORD;
2510 }
2511 break;
2512 case 1:
2513 as_warn (_(":b not permitted; defaulting to :w"));
2514 /* Fall through. */
2515 case 2:
2516 nextword |= 0x2;
2517 break;
2518 case 3:
2519 nextword |= 0x3;
2520 break;
2521 }
2522 if (opP->mode == POST
2523 && (nextword & 0x40) == 0)
2524 nextword |= 0x04;
2525 }
2526 addword (nextword);
2527
2528 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2529 {
2530 if (opP->reg == PC || opP->reg == ZPC)
2531 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2532 else
2533 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2534 }
2535 if (siz1 == SIZE_LONG)
2536 addword (baseo >> 16);
2537 if (siz1 != SIZE_UNSPEC)
2538 addword (baseo);
2539
2540 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2541 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2542 if (siz2 == SIZE_LONG)
2543 addword (outro >> 16);
2544 if (siz2 != SIZE_UNSPEC)
2545 addword (outro);
2546
2547 break;
2548
2549 case ABSL:
3e602632 2550 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2551 switch (opP->disp.size)
2552 {
2553 default:
2554 abort ();
2555 case SIZE_UNSPEC:
2556 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2557 {
2558 tmpreg = 0x38; /* 7.0 */
2559 addword (nextword);
2560 break;
2561 }
252b5132
RH		 2562 if (isvar (&opP->disp)
2563 && !subs (&opP->disp)
2564 && adds (&opP->disp)
2565#ifdef OBJ_ELF
2566 /* If the displacement needs pic relocation it
2567 cannot be relaxed. */
2568 && opP->disp.pic_reloc == pic_none
2569#endif
252b5132
RH		 2570 && !flag_long_jumps
2571 && !strchr ("~%&$?", s[0]))
2572 {
2573 tmpreg = 0x3A; /* 7.2 */
2574 add_frag (adds (&opP->disp),
bd17c2c3 2575 SEXT (offs (&opP->disp)),
151337e8 2576 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2577 break;
2578 }
36759679 2579 /* Fall through into long. */
252b5132
RH		 2580 case SIZE_LONG:
2581 if (isvar (&opP->disp))
2582 add_fix ('l', &opP->disp, 0, 0);
2583
2584 tmpreg = 0x39;/* 7.1 mode */
2585 addword (nextword >> 16);
2586 addword (nextword);
2587 break;
2588
2589 case SIZE_BYTE:
2590 as_bad (_("unsupported byte value; use a different suffix"));
2591 /* Fall through. */
36759679
NC		 2592
2593 case SIZE_WORD:
252b5132
RH		 2594 if (isvar (&opP->disp))
2595 add_fix ('w', &opP->disp, 0, 0);
2596
2597 tmpreg = 0x38;/* 7.0 mode */
2598 addword (nextword);
2599 break;
2600 }
2601 break;
2602 case CONTROL:
2603 case FPREG:
2604 default:
2605 as_bad (_("unknown/incorrect operand"));
bc805888 2606 /* abort (); */
252b5132 2607 }
fd99574b
NC		 2608
2609 /* If s[0] is '4', then this is for the mac instructions
2610 that can have a trailing_ampersand set. If so, set 0x100
2611 bit on tmpreg so install_gen_operand can check for it and
2612 set the appropriate bit (word2, bit 5). */
2613 if (s[0] == '4')
2614 {
2615 if (opP->trailing_ampersand)
2616 tmpreg |= 0x100;
2617 }
252b5132
RH		 2618 install_gen_operand (s[1], tmpreg);
2619 break;
2620
2621 case '#':
2622 case '^':
2623 switch (s[1])
2624 { /* JF: I hate floating point! */
2625 case 'j':
2626 tmpreg = 70;
2627 break;
2628 case '8':
2629 tmpreg = 20;
2630 break;
2631 case 'C':
2632 tmpreg = 50;
2633 break;
2634 case '3':
2635 default:
3e602632 2636 tmpreg = 90;
252b5132
RH		 2637 break;
2638 }
2639 tmpreg = get_num (&opP->disp, tmpreg);
2640 if (isvar (&opP->disp))
2641 add_fix (s[1], &opP->disp, 0, 0);
2642 switch (s[1])
2643 {
2644 case 'b': /* Danger: These do no check for
2645 certain types of overflow.
2646 user beware! */
2647 if (!isbyte (tmpreg))
2648 opP->error = _("out of range");
2649 insop (tmpreg, opcode);
2650 if (isvar (&opP->disp))
2651 the_ins.reloc[the_ins.nrel - 1].n =
2652 (opcode->m_codenum) * 2 + 1;
2653 break;
2654 case 'B':
2655 if (!issbyte (tmpreg))
2656 opP->error = _("out of range");
2657 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2658 if (isvar (&opP->disp))
2659 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2660 break;
2661 case 'w':
2662 if (!isword (tmpreg))
2663 opP->error = _("out of range");
2664 insop (tmpreg, opcode);
2665 if (isvar (&opP->disp))
2666 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2667 break;
2668 case 'W':
2669 if (!issword (tmpreg))
2670 opP->error = _("out of range");
2671 insop (tmpreg, opcode);
2672 if (isvar (&opP->disp))
2673 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2674 break;
2675 case 'l':
2676 /* Because of the way insop works, we put these two out
2677 backwards. */
2678 insop (tmpreg, opcode);
2679 insop (tmpreg >> 16, opcode);
2680 if (isvar (&opP->disp))
2681 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2682 break;
2683 case '3':
2684 tmpreg &= 0xFF;
2685 case '8':
2686 case 'C':
2687 case 'j':
2688 install_operand (s[1], tmpreg);
2689 break;
2690 default:
2691 abort ();
2692 }
2693 break;
2694
2695 case '+':
2696 case '-':
2697 case 'A':
2698 case 'a':
2699 install_operand (s[1], opP->reg - ADDR);
2700 break;
2701
2702 case 'B':
3e602632 2703 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2704 switch (s[1])
2705 {
2706 case 'B':
8390138c 2707 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2708 break;
2709 case 'W':
2710 add_fix ('w', &opP->disp, 1, 0);
2711 addword (0);
2712 break;
2713 case 'L':
2714 long_branch:
151337e8 2715 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2716 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2717 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2718 add_fix ('l', &opP->disp, 1, 0);
2719 addword (0);
2720 addword (0);
2721 break;
2722 case 'g':
36759679 2723 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2724 goto long_branch;
2725
2726#ifdef OBJ_ELF
2727 /* If the displacement needs pic relocation it cannot be
2728 relaxed. */
2729 if (opP->disp.pic_reloc != pic_none)
2730 goto long_branch;
2731#endif
252b5132 2732 /* This could either be a symbol, or an absolute
151337e8
NC		 2733 address. If it's an absolute address, turn it into
2734 an absolute jump right here and keep it out of the
2735 relaxer. */
2736 if (adds (&opP->disp) == 0)
2737 {
2738 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2739 the_ins.opcode[0] = 0x4EF9;
151337e8 2740 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2741 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2742 else /* jCC */
2743 {
2744 the_ins.opcode[0] ^= 0x0100;
2745 the_ins.opcode[0] |= 0x0006;
18566f55 2746 addword (0x4EF9);
151337e8
NC		 2747 }
2748 add_fix ('l', &opP->disp, 0, 0);
2749 addword (0);
2750 addword (0);
2751 break;
2752 }
2753
2754 /* Now we know it's going into the relaxer. Now figure
2755 out which mode. We try in this order of preference:
2756 long branch, absolute jump, byte/word branches only. */
2757 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2758 add_frag (adds (&opP->disp),
2759 SEXT (offs (&opP->disp)),
151337e8
NC		 2760 TAB (BRANCHBWL, SZ_UNDEF));
2761 else if (! flag_keep_pcrel)
2762 {
2763 if ((the_ins.opcode[0] == 0x6000)
2764 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2765 add_frag (adds (&opP->disp),
2766 SEXT (offs (&opP->disp)),
151337e8
NC		 2767 TAB (BRABSJUNC, SZ_UNDEF));
2768 else
bd17c2c3
AM		 2769 add_frag (adds (&opP->disp),
2770 SEXT (offs (&opP->disp)),
151337e8
NC		 2771 TAB (BRABSJCOND, SZ_UNDEF));
2772 }
252b5132 2773 else
bd17c2c3
AM		 2774 add_frag (adds (&opP->disp),
2775 SEXT (offs (&opP->disp)),
151337e8 2776 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2777 break;
2778 case 'w':
2779 if (isvar (&opP->disp))
2780 {
151337e8
NC		 2781 /* Check for DBcc instructions. We can relax them,
2782 but only if we have long branches and/or absolute
2783 jumps. */
2784 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2785 && (HAVE_LONG_BRANCH (current_architecture)
2786 || (! flag_keep_pcrel)))
252b5132 2787 {
151337e8 2788 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2789 add_frag (adds (&opP->disp),
2790 SEXT (offs (&opP->disp)),
151337e8
NC		 2791 TAB (DBCCLBR, SZ_UNDEF));
2792 else
bd17c2c3
AM		 2793 add_frag (adds (&opP->disp),
2794 SEXT (offs (&opP->disp)),
151337e8 2795 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2796 break;
2797 }
252b5132
RH		 2798 add_fix ('w', &opP->disp, 1, 0);
2799 }
2800 addword (0);
2801 break;
36759679 2802 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2803 add_fix ('l', &opP->disp, 1, 0);
2804 addword (0);
2805 addword (0);
2806 break;
36759679 2807 case 'c': /* Var size Coprocesssor branches. */
151337e8 2808 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2809 {
252b5132
RH		 2810 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2811 add_fix ('l', &opP->disp, 1, 0);
2812 addword (0);
2813 addword (0);
2814 }
151337e8 2815 else
bd17c2c3
AM		 2816 add_frag (adds (&opP->disp),
2817 SEXT (offs (&opP->disp)),
151337e8 2818 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2819 break;
2820 default:
2821 abort ();
2822 }
2823 break;
2824
36759679 2825 case 'C': /* Ignore it. */
252b5132
RH		 2826 break;
2827
36759679 2828 case 'd': /* JF this is a kludge. */
252b5132 2829 install_operand ('s', opP->reg - ADDR);
3e602632 2830 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2831 if (!issword (tmpreg))
2832 {
2833 as_warn (_("Expression out of range, using 0"));
2834 tmpreg = 0;
2835 }
2836 addword (tmpreg);
2837 break;
2838
2839 case 'D':
2840 install_operand (s[1], opP->reg - DATA);
2841 break;
2842
fd99574b
NC		 2843 case 'e': /* EMAC ACCx, reg/reg. */
2844 install_operand (s[1], opP->reg - ACC);
2845 break;
2846
36759679 2847 case 'E': /* Ignore it. */
6da466c7
ILT		 2848 break;
2849
252b5132
RH		 2850 case 'F':
2851 install_operand (s[1], opP->reg - FP0);
2852 break;
2853
fd99574b
NC		 2854 case 'g': /* EMAC ACCEXTx. */
2855 install_operand (s[1], opP->reg - ACCEXT01);
2856 break;
2857
36759679 2858 case 'G': /* Ignore it. */
6da466c7
ILT		 2859 case 'H':
2860 break;
2861
252b5132
RH		 2862 case 'I':
2863 tmpreg = opP->reg - COP0;
2864 install_operand (s[1], tmpreg);
2865 break;
2866
fd99574b
NC		 2867 case 'i': /* MAC/EMAC scale factor. */
2868 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2869 break;
2870
36759679 2871 case 'J': /* JF foo. */
252b5132
RH		 2872 switch (opP->reg)
2873 {
2874 case SFC:
2875 tmpreg = 0x000;
2876 break;
2877 case DFC:
2878 tmpreg = 0x001;
2879 break;
2880 case CACR:
2881 tmpreg = 0x002;
2882 break;
2883 case TC:
2884 tmpreg = 0x003;
2885 break;
3e602632 2886 case ACR0:
252b5132
RH		 2887 case ITT0:
2888 tmpreg = 0x004;
2889 break;
3e602632 2890 case ACR1:
252b5132
RH		 2891 case ITT1:
2892 tmpreg = 0x005;
2893 break;
3e602632 2894 case ACR2:
252b5132
RH		 2895 case DTT0:
2896 tmpreg = 0x006;
2897 break;
3e602632 2898 case ACR3:
252b5132
RH		 2899 case DTT1:
2900 tmpreg = 0x007;
2901 break;
2902 case BUSCR:
2903 tmpreg = 0x008;
2904 break;
2905
2906 case USP:
2907 tmpreg = 0x800;
2908 break;
2909 case VBR:
2910 tmpreg = 0x801;
2911 break;
2912 case CAAR:
2913 tmpreg = 0x802;
2914 break;
2915 case MSP:
2916 tmpreg = 0x803;
2917 break;
2918 case ISP:
2919 tmpreg = 0x804;
2920 break;
2921 case MMUSR:
2922 tmpreg = 0x805;
2923 break;
2924 case URP:
2925 tmpreg = 0x806;
2926 break;
2927 case SRP:
2928 tmpreg = 0x807;
2929 break;
2930 case PCR:
2931 tmpreg = 0x808;
2932 break;
2933 case ROMBAR:
2934 tmpreg = 0xC00;
2935 break;
3e602632
NC		 2936 case ROMBAR1:
2937 tmpreg = 0xC01;
2938 break;
2939 case FLASHBAR:
252b5132
RH		 2940 case RAMBAR0:
2941 tmpreg = 0xC04;
2942 break;
3e602632 2943 case RAMBAR:
252b5132
RH		 2944 case RAMBAR1:
2945 tmpreg = 0xC05;
2946 break;
3e602632
NC		 2947 case MPCR:
2948 tmpreg = 0xC0C;
2949 break;
2950 case EDRAMBAR:
2951 tmpreg = 0xC0D;
2952 break;
2953 case MBAR0:
e80e0390 2954 case MBAR2:
3e602632
NC		 2955 case SECMBAR:
2956 tmpreg = 0xC0E;
2957 break;
2958 case MBAR1:
252b5132
RH		 2959 case MBAR:
2960 tmpreg = 0xC0F;
2961 break;
3e602632
NC		 2962 case PCR1U0:
2963 tmpreg = 0xD02;
2964 break;
2965 case PCR1L0:
2966 tmpreg = 0xD03;
2967 break;
2968 case PCR2U0:
2969 tmpreg = 0xD04;
2970 break;
2971 case PCR2L0:
2972 tmpreg = 0xD05;
2973 break;
2974 case PCR3U0:
2975 tmpreg = 0xD06;
2976 break;
2977 case PCR3L0:
2978 tmpreg = 0xD07;
2979 break;
2980 case PCR1L1:
2981 tmpreg = 0xD0A;
2982 break;
2983 case PCR1U1:
2984 tmpreg = 0xD0B;
2985 break;
2986 case PCR2L1:
2987 tmpreg = 0xD0C;
2988 break;
2989 case PCR2U1:
2990 tmpreg = 0xD0D;
2991 break;
2992 case PCR3L1:
2993 tmpreg = 0xD0E;
2994 break;
2995 case PCR3U1:
2996 tmpreg = 0xD0F;
2997 break;
252b5132
RH		 2998 default:
2999 abort ();
3000 }
3001 install_operand (s[1], tmpreg);
3002 break;
3003
3004 case 'k':
3005 tmpreg = get_num (&opP->disp, 55);
3006 install_operand (s[1], tmpreg & 0x7f);
3007 break;
3008
3009 case 'l':
3010 tmpreg = opP->mask;
3011 if (s[1] == 'w')
3012 {
3013 if (tmpreg & 0x7FF0000)
3014 as_bad (_("Floating point register in register list"));
3015 insop (reverse_16_bits (tmpreg), opcode);
3016 }
3017 else
3018 {
3019 if (tmpreg & 0x700FFFF)
3020 as_bad (_("Wrong register in floating-point reglist"));
3021 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3022 }
3023 break;
3024
3025 case 'L':
3026 tmpreg = opP->mask;
3027 if (s[1] == 'w')
3028 {
3029 if (tmpreg & 0x7FF0000)
3030 as_bad (_("Floating point register in register list"));
3031 insop (tmpreg, opcode);
3032 }
3033 else if (s[1] == '8')
3034 {
3035 if (tmpreg & 0x0FFFFFF)
3036 as_bad (_("incorrect register in reglist"));
3037 install_operand (s[1], tmpreg >> 24);
3038 }
3039 else
3040 {
3041 if (tmpreg & 0x700FFFF)
3042 as_bad (_("wrong register in floating-point reglist"));
3043 else
3044 install_operand (s[1], tmpreg >> 16);
3045 }
3046 break;
3047
3048 case 'M':
3049 install_operand (s[1], get_num (&opP->disp, 60));
3050 break;
3051
3052 case 'O':
3053 tmpreg = ((opP->mode == DREG)
8fce3f5e 3054 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3055 : (get_num (&opP->disp, 40) & 0x1F));
3056 install_operand (s[1], tmpreg);
3057 break;
3058
3059 case 'Q':
3060 tmpreg = get_num (&opP->disp, 10);
3061 if (tmpreg == 8)
3062 tmpreg = 0;
3063 install_operand (s[1], tmpreg);
3064 break;
3065
3066 case 'R':
3067 /* This depends on the fact that ADDR registers are eight
3068 more than their corresponding DATA regs, so the result
36759679 3069 will have the ADDR_REG bit set. */
252b5132
RH		 3070 install_operand (s[1], opP->reg - DATA);
3071 break;
3072
3073 case 'r':
3074 if (opP->mode == AINDR)
3075 install_operand (s[1], opP->reg - DATA);
3076 else
3077 install_operand (s[1], opP->index.reg - DATA);
3078 break;
3079
3080 case 's':
3081 if (opP->reg == FPI)
3082 tmpreg = 0x1;
3083 else if (opP->reg == FPS)
3084 tmpreg = 0x2;
3085 else if (opP->reg == FPC)
3086 tmpreg = 0x4;
3087 else
3088 abort ();
3089 install_operand (s[1], tmpreg);
3090 break;
3091
36759679 3092 case 'S': /* Ignore it. */
252b5132
RH		 3093 break;
3094
3095 case 'T':
3096 install_operand (s[1], get_num (&opP->disp, 30));
3097 break;
3098
36759679 3099 case 'U': /* Ignore it. */
252b5132
RH		 3100 break;
3101
3102 case 'c':
3103 switch (opP->reg)
3104 {
3105 case NC:
3106 tmpreg = 0;
3107 break;
3108 case DC:
3109 tmpreg = 1;
3110 break;
3111 case IC:
3112 tmpreg = 2;
3113 break;
3114 case BC:
3115 tmpreg = 3;
3116 break;
3117 default:
3118 as_fatal (_("failed sanity check"));
36759679 3119 } /* switch on cache token. */
252b5132
RH		 3120 install_operand (s[1], tmpreg);
3121 break;
3122#ifndef NO_68851
92774660 3123 /* JF: These are out of order, I fear. */
252b5132
RH		 3124 case 'f':
3125 switch (opP->reg)
3126 {
3127 case SFC:
3128 tmpreg = 0;
3129 break;
3130 case DFC:
3131 tmpreg = 1;
3132 break;
3133 default:
3134 abort ();
3135 }
3136 install_operand (s[1], tmpreg);
3137 break;
3138
3139 case '0':
3140 case '1':
3141 case '2':
3142 switch (opP->reg)
3143 {
3144 case TC:
3145 tmpreg = 0;
3146 break;
3147 case CAL:
3148 tmpreg = 4;
3149 break;
3150 case VAL:
3151 tmpreg = 5;
3152 break;
3153 case SCC:
3154 tmpreg = 6;
3155 break;
3156 case AC:
3157 tmpreg = 7;
3158 break;
3159 default:
3160 abort ();
3161 }
3162 install_operand (s[1], tmpreg);
3163 break;
3164
3165 case 'V':
3166 if (opP->reg == VAL)
3167 break;
3168 abort ();
3169
3170 case 'W':
3171 switch (opP->reg)
3172 {
3173 case DRP:
3174 tmpreg = 1;
3175 break;
3176 case SRP:
3177 tmpreg = 2;
3178 break;
3179 case CRP:
3180 tmpreg = 3;
3181 break;
3182 default:
3183 abort ();
3184 }
3185 install_operand (s[1], tmpreg);
3186 break;
3187
3188 case 'X':
3189 switch (opP->reg)
3190 {
3191 case BAD:
3192 case BAD + 1:
3193 case BAD + 2:
3194 case BAD + 3:
3195 case BAD + 4:
3196 case BAD + 5:
3197 case BAD + 6:
3198 case BAD + 7:
3199 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3200 break;
3201
3202 case BAC:
3203 case BAC + 1:
3204 case BAC + 2:
3205 case BAC + 3:
3206 case BAC + 4:
3207 case BAC + 5:
3208 case BAC + 6:
3209 case BAC + 7:
3210 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3211 break;
3212
3213 default:
3214 abort ();
3215 }
3216 install_operand (s[1], tmpreg);
3217 break;
3218 case 'Y':
3219 know (opP->reg == PSR);
3220 break;
3221 case 'Z':
3222 know (opP->reg == PCSR);
3223 break;
3224#endif /* m68851 */
3225 case '3':
3226 switch (opP->reg)
3227 {
3228 case TT0:
3229 tmpreg = 2;
3230 break;
3231 case TT1:
3232 tmpreg = 3;
3233 break;
3234 default:
3235 abort ();
3236 }
3237 install_operand (s[1], tmpreg);
3238 break;
3239 case 't':
3240 tmpreg = get_num (&opP->disp, 20);
3241 install_operand (s[1], tmpreg);
3242 break;
36759679 3243 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3244 if (isvar (&opP->disp))
3245 add_fix ('l', &opP->disp, 0, 0);
3e602632 3246 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3247 addword (tmpreg >> 16);
3248 addword (tmpreg & 0xFFFF);
3249 break;
6da466c7
ILT		 3250 case 'u':
3251 install_operand (s[1], opP->reg - DATA0L);
3252 opP->reg -= (DATA0L);
36759679 3253 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3254 break;
3e602632
NC		 3255 case 'x':
3256 tmpreg = get_num (&opP->disp, 80);
3257 if (tmpreg == -1)
3258 tmpreg = 0;
3259 install_operand (s[1], tmpreg);
3260 break;
252b5132
RH		 3261 default:
3262 abort ();
3263 }
3264 }
3265
3266 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3267 instruction, ready to be emitted. . . */
252b5132
RH		 3268}
3269
3270static int
31302357 3271reverse_16_bits (int in)
252b5132
RH		 3272{
3273 int out = 0;
3274 int n;
3275
3276 static int mask[16] =
3277 {
3278 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3279 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3280 };
3281 for (n = 0; n < 16; n++)
3282 {
3283 if (in & mask[n])
3284 out |= mask[15 - n];
3285 }
3286 return out;
3287} /* reverse_16_bits() */
3288
3289static int
31302357 3290reverse_8_bits (int in)
252b5132
RH		 3291{
3292 int out = 0;
3293 int n;
3294
3295 static int mask[8] =
3296 {
3297 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3298 };
3299
3300 for (n = 0; n < 8; n++)
3301 {
3302 if (in & mask[n])
3303 out |= mask[7 - n];
3304 }
3305 return out;
3306} /* reverse_8_bits() */
3307
3308/* Cause an extra frag to be generated here, inserting up to 10 bytes
3309 (that value is chosen in the frag_var call in md_assemble). TYPE
3310 is the subtype of the frag to be generated; its primary type is
3311 rs_machine_dependent.
3312
3313 The TYPE parameter is also used by md_convert_frag_1 and
3314 md_estimate_size_before_relax. The appropriate type of fixup will
3315 be emitted by md_convert_frag_1.
3316
3317 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3318static void
31302357 3319install_operand (int mode, int val)
252b5132
RH		 3320{
3321 switch (mode)
3322 {
3323 case 's':
36759679 3324 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3325 break;
3326 case 'd':
3327 the_ins.opcode[0] |= val << 9;
3328 break;
3329 case '1':
3330 the_ins.opcode[1] |= val << 12;
3331 break;
3332 case '2':
3333 the_ins.opcode[1] |= val << 6;
3334 break;
3335 case '3':
3336 the_ins.opcode[1] |= val;
3337 break;
3338 case '4':
3339 the_ins.opcode[2] |= val << 12;
3340 break;
3341 case '5':
3342 the_ins.opcode[2] |= val << 6;
3343 break;
3344 case '6':
3345 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3346 three words long! */
3347 the_ins.numo++;
3348 the_ins.opcode[2] |= val;
3349 break;
3350 case '7':
3351 the_ins.opcode[1] |= val << 7;
3352 break;
3353 case '8':
3354 the_ins.opcode[1] |= val << 10;
3355 break;
3356#ifndef NO_68851
3357 case '9':
3358 the_ins.opcode[1] |= val << 5;
3359 break;
3360#endif
3361
3362 case 't':
3363 the_ins.opcode[1] |= (val << 10) | (val << 7);
3364 break;
3365 case 'D':
3366 the_ins.opcode[1] |= (val << 12) | val;
3367 break;
3368 case 'g':
3369 the_ins.opcode[0] |= val = 0xff;
3370 break;
3371 case 'i':
3372 the_ins.opcode[0] |= val << 9;
3373 break;
3374 case 'C':
3375 the_ins.opcode[1] |= val;
3376 break;
3377 case 'j':
3378 the_ins.opcode[1] |= val;
36759679 3379 the_ins.numo++; /* What a hack. */
252b5132
RH		 3380 break;
3381 case 'k':
3382 the_ins.opcode[1] |= val << 4;
3383 break;
3384 case 'b':
3385 case 'w':
3386 case 'W':
3387 case 'l':
3388 break;
3389 case 'e':
3390 the_ins.opcode[0] |= (val << 6);
3391 break;
3392 case 'L':
3393 the_ins.opcode[1] = (val >> 16);
3394 the_ins.opcode[2] = val & 0xffff;
3395 break;
6da466c7
ILT		 3396 case 'm':
3397 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3398 the_ins.opcode[0] |= ((val & 0x7) << 9);
3399 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3400 break;
fd99574b 3401 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3402 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3403 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3404 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3405 break;
fd99574b 3406 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3407 the_ins.opcode[1] |= val << 12;
3408 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3409 break;
fd99574b 3410 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3411 the_ins.opcode[0] |= (val & 0xF);
3412 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3413 break;
fd99574b 3414 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3415 the_ins.opcode[1] |= (val & 0xF);
3416 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3417 break;
3418 case 'h':
3419 the_ins.opcode[1] |= ((val != 1) << 10);
3420 break;
fd99574b
NC		 3421 case 'F':
3422 the_ins.opcode[0] |= ((val & 0x3) << 9);
3423 break;
3424 case 'f':
3425 the_ins.opcode[0] |= ((val & 0x3) << 0);
3426 break;
be8c092b 3427 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3428 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3429 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3430 break;
be8c092b 3431 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3432 the_ins.opcode[0] |= ((val & 0x1) << 7);
3433 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3434 break;
3435 case 'I':
3436 the_ins.opcode[1] |= ((val & 0x3) << 9);
3437 break;
3438 case ']':
3439 the_ins.opcode[0] |= (val & 0x1) <<10;
3440 break;
252b5132
RH		 3441 case 'c':
3442 default:
3443 as_fatal (_("failed sanity check."));
3444 }
6b6e92f4 3445}
252b5132
RH		 3446
3447static void
31302357 3448install_gen_operand (int mode, int val)
252b5132
RH		 3449{
3450 switch (mode)
3451 {
fd99574b
NC		 3452 case '/': /* Special for mask loads for mac/msac insns with
3453 possible mask; trailing_ampersend set in bit 8. */
3454 the_ins.opcode[0] |= (val & 0x3f);
3455 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3456 break;
252b5132
RH		 3457 case 's':
3458 the_ins.opcode[0] |= val;
3459 break;
3460 case 'd':
3461 /* This is a kludge!!! */
3462 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3463 break;
3464 case 'b':
3465 case 'w':
3466 case 'l':
3467 case 'f':
3468 case 'F':
3469 case 'x':
3470 case 'p':
3471 the_ins.opcode[0] |= val;
3472 break;
36759679 3473 /* more stuff goes here. */
252b5132
RH		 3474 default:
3475 as_fatal (_("failed sanity check."));
3476 }
6b6e92f4 3477}
252b5132 3478
6b6e92f4
NC		 3479/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3480 then deal with the bitfield hack. */
252b5132
RH		 3481
3482static char *
31302357 3483crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3484{
3485 register int parens;
3486 register int c;
3487 register char *beg_str;
3488 int inquote = 0;
3489
3490 if (!str)
3491 {
3492 return str;
3493 }
3494 beg_str = str;
3495 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3496 {
3497 if (! inquote)
3498 {
3499 if (*str == '(')
3500 parens++;
3501 else if (*str == ')')
3502 {
3503 if (!parens)
36759679 3504 { /* ERROR. */
252b5132
RH		 3505 opP->error = _("Extra )");
3506 return str;
3507 }
3508 --parens;
3509 }
3510 }
3511 if (flag_mri && *str == '\'')
3512 inquote = ! inquote;
3513 }
3514 if (!*str && parens)
36759679 3515 { /* ERROR. */
252b5132
RH		 3516 opP->error = _("Missing )");
3517 return str;
3518 }
3519 c = *str;
3520 *str = '\0';
3521 if (m68k_ip_op (beg_str, opP) != 0)
3522 {
3523 *str = c;
3524 return str;
3525 }
3526 *str = c;
3527 if (c == '}')
36759679 3528 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3529 if (c)
3530 {
3531 c = *++str;
3532 if (!c)
3533 as_bad (_("Missing operand"));
3534 }
3535
3536 /* Detect MRI REG symbols and convert them to REGLSTs. */
3537 if (opP->mode == CONTROL && (int)opP->reg < 0)
3538 {
3539 opP->mode = REGLST;
3540 opP->mask = ~(int)opP->reg;
3541 opP->reg = 0;
3542 }
3543
3544 return str;
3545}
3546
3547/* This is the guts of the machine-dependent assembler. STR points to a
3548 machine dependent instruction. This function is supposed to emit
3549 the frags/bytes it assembles to.
3550 */
3551
3552static void
31302357 3553insert_reg (const char *regname, int regnum)
252b5132
RH		 3554{
3555 char buf[100];
3556 int i;
3557
3558#ifdef REGISTER_PREFIX
3559 if (!flag_reg_prefix_optional)
3560 {
3561 buf[0] = REGISTER_PREFIX;
3562 strcpy (buf + 1, regname);
3563 regname = buf;
3564 }
3565#endif
3566
3567 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3568 &zero_address_frag));
3569
3570 for (i = 0; regname[i]; i++)
3882b010 3571 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3572 buf[i] = '\0';
3573
3574 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3575 &zero_address_frag));
3576}
3577
3578struct init_entry
3579 {
3580 const char *name;
3581 int number;
3582 };
3583
3584static const struct init_entry init_table[] =
3585{
3586 { "d0", DATA0 },
3587 { "d1", DATA1 },
3588 { "d2", DATA2 },
3589 { "d3", DATA3 },
3590 { "d4", DATA4 },
3591 { "d5", DATA5 },
3592 { "d6", DATA6 },
3593 { "d7", DATA7 },
3594 { "a0", ADDR0 },
3595 { "a1", ADDR1 },
3596 { "a2", ADDR2 },
3597 { "a3", ADDR3 },
3598 { "a4", ADDR4 },
3599 { "a5", ADDR5 },
3600 { "a6", ADDR6 },
3601 { "fp", ADDR6 },
3602 { "a7", ADDR7 },
3603 { "sp", ADDR7 },
3604 { "ssp", ADDR7 },
3605 { "fp0", FP0 },
3606 { "fp1", FP1 },
3607 { "fp2", FP2 },
3608 { "fp3", FP3 },
3609 { "fp4", FP4 },
3610 { "fp5", FP5 },
3611 { "fp6", FP6 },
3612 { "fp7", FP7 },
3613 { "fpi", FPI },
3614 { "fpiar", FPI },
3615 { "fpc", FPI },
3616 { "fps", FPS },
3617 { "fpsr", FPS },
3618 { "fpc", FPC },
3619 { "fpcr", FPC },
3620 { "control", FPC },
3621 { "status", FPS },
3622 { "iaddr", FPI },
3623
3624 { "cop0", COP0 },
3625 { "cop1", COP1 },
3626 { "cop2", COP2 },
3627 { "cop3", COP3 },
3628 { "cop4", COP4 },
3629 { "cop5", COP5 },
3630 { "cop6", COP6 },
3631 { "cop7", COP7 },
3632 { "pc", PC },
3633 { "zpc", ZPC },
3634 { "sr", SR },
3635
3636 { "ccr", CCR },
3637 { "cc", CCR },
3638
6da466c7 3639 { "acc", ACC },
fd99574b
NC		 3640 { "acc0", ACC },
3641 { "acc1", ACC1 },
3642 { "acc2", ACC2 },
3643 { "acc3", ACC3 },
3644 { "accext01", ACCEXT01 },
3645 { "accext23", ACCEXT23 },
6da466c7
ILT		 3646 { "macsr", MACSR },
3647 { "mask", MASK },
3648
36759679
NC		 3649 /* Control registers. */
3650 { "sfc", SFC }, /* Source Function Code. */
252b5132 3651 { "sfcr", SFC },
36759679 3652 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3653 { "dfcr", DFC },
36759679
NC		 3654 { "cacr", CACR }, /* Cache Control Register. */
3655 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3656
36759679
NC		 3657 { "usp", USP }, /* User Stack Pointer. */
3658 { "vbr", VBR }, /* Vector Base Register. */
3659 { "msp", MSP }, /* Master Stack Pointer. */
3660 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3661
36759679
NC		 3662 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3663 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3664 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3665 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3666
3667 /* 68ec040 versions of same */
36759679
NC		 3668 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3669 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3670 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3671 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3672
3673 /* mcf5200 versions of same. The ColdFire programmer's reference
3674 manual indicated that the order is 2,3,0,1, but Ken Rose
3675 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3676 { "acr0", ACR0 }, /* Access Control Unit 0. */
3677 { "acr1", ACR1 }, /* Access Control Unit 1. */
3678 { "acr2", ACR2 }, /* Access Control Unit 2. */
3679 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3680
36759679 3681 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3682 { "tcr", TC },
3683
36759679
NC		 3684 { "mmusr", MMUSR }, /* MMU Status Register. */
3685 { "srp", SRP }, /* User Root Pointer. */
3686 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3687
3688 { "buscr", BUSCR },
3689 { "pcr", PCR },
3690
36759679
NC		 3691 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3692 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3693 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3694 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3695
3696 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3697 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3698 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3699 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3700 { "mpcr", MPCR }, /* mcfv4e registers. */
3701 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3702 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3703 { "asid", TC }, /* mcfv4e registers. */
3704 { "mmubar", BUSCR }, /* mcfv4e registers. */
3705 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3706 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3707 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3708 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3709 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3710 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3711 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3712 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3713 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3714 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3715 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3716 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3717
3718 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3719 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3720
3721 { "mbar2", MBAR2 }, /* mcf5249 registers. */
36759679 3722 /* End of control registers. */
252b5132
RH		 3723
3724 { "ac", AC },
3725 { "bc", BC },
3726 { "cal", CAL },
3727 { "crp", CRP },
3728 { "drp", DRP },
3729 { "pcsr", PCSR },
3730 { "psr", PSR },
3731 { "scc", SCC },
3732 { "val", VAL },
3733 { "bad0", BAD0 },
3734 { "bad1", BAD1 },
3735 { "bad2", BAD2 },
3736 { "bad3", BAD3 },
3737 { "bad4", BAD4 },
3738 { "bad5", BAD5 },
3739 { "bad6", BAD6 },
3740 { "bad7", BAD7 },
3741 { "bac0", BAC0 },
3742 { "bac1", BAC1 },
3743 { "bac2", BAC2 },
3744 { "bac3", BAC3 },
3745 { "bac4", BAC4 },
3746 { "bac5", BAC5 },
3747 { "bac6", BAC6 },
3748 { "bac7", BAC7 },
3749
3750 { "ic", IC },
3751 { "dc", DC },
3752 { "nc", NC },
3753
3754 { "tt0", TT0 },
3755 { "tt1", TT1 },
36759679 3756 /* 68ec030 versions of same. */
252b5132
RH		 3757 { "ac0", TT0 },
3758 { "ac1", TT1 },
36759679 3759 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3760 { "acusr", PSR },
3761
3762 /* Suppressed data and address registers. */
3763 { "zd0", ZDATA0 },
3764 { "zd1", ZDATA1 },
3765 { "zd2", ZDATA2 },
3766 { "zd3", ZDATA3 },
3767 { "zd4", ZDATA4 },
3768 { "zd5", ZDATA5 },
3769 { "zd6", ZDATA6 },
3770 { "zd7", ZDATA7 },
3771 { "za0", ZADDR0 },
3772 { "za1", ZADDR1 },
3773 { "za2", ZADDR2 },
3774 { "za3", ZADDR3 },
3775 { "za4", ZADDR4 },
3776 { "za5", ZADDR5 },
3777 { "za6", ZADDR6 },
3778 { "za7", ZADDR7 },
3779
92774660 3780 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3781 { "d0l", DATA0L },
3782 { "d1l", DATA1L },
3783 { "d2l", DATA2L },
3784 { "d3l", DATA3L },
3785 { "d4l", DATA4L },
3786 { "d5l", DATA5L },
3787 { "d6l", DATA6L },
3788 { "d7l", DATA7L },
3789
3790 { "a0l", ADDR0L },
3791 { "a1l", ADDR1L },
3792 { "a2l", ADDR2L },
3793 { "a3l", ADDR3L },
3794 { "a4l", ADDR4L },
3795 { "a5l", ADDR5L },
3796 { "a6l", ADDR6L },
3797 { "a7l", ADDR7L },
3798
3799 { "d0u", DATA0U },
3800 { "d1u", DATA1U },
3801 { "d2u", DATA2U },
3802 { "d3u", DATA3U },
3803 { "d4u", DATA4U },
3804 { "d5u", DATA5U },
3805 { "d6u", DATA6U },
3806 { "d7u", DATA7U },
3807
3808 { "a0u", ADDR0U },
3809 { "a1u", ADDR1U },
3810 { "a2u", ADDR2U },
3811 { "a3u", ADDR3U },
3812 { "a4u", ADDR4U },
3813 { "a5u", ADDR5U },
3814 { "a6u", ADDR6U },
3815 { "a7u", ADDR7U },
3816
252b5132
RH		 3817 { 0, 0 }
3818};
3819
3820static void
31302357 3821init_regtable (void)
252b5132
RH		 3822{
3823 int i;
3824 for (i = 0; init_table[i].name; i++)
3825 insert_reg (init_table[i].name, init_table[i].number);
3826}
3827
3828static int no_68851, no_68881;
3829
252b5132 3830void
31302357 3831md_assemble (char *str)
252b5132
RH		 3832{
3833 const char *er;
3834 short *fromP;
3835 char *toP = NULL;
3836 int m, n = 0;
3837 char *to_beg_P;
3838 int shorts_this_frag;
3839 fixS *fixP;
3840
3841 /* In MRI mode, the instruction and operands are separated by a
3842 space. Anything following the operands is a comment. The label
3843 has already been removed. */
3844 if (flag_mri)
3845 {
3846 char *s;
3847 int fields = 0;
3848 int infield = 0;
3849 int inquote = 0;
3850
3851 for (s = str; *s != '\0'; s++)
3852 {
3853 if ((*s == ' ' || *s == '\t') && ! inquote)
3854 {
3855 if (infield)
3856 {
3857 ++fields;
3858 if (fields >= 2)
3859 {
3860 *s = '\0';
3861 break;
3862 }
3863 infield = 0;
3864 }
3865 }
3866 else
3867 {
3868 if (! infield)
3869 infield = 1;
3870 if (*s == '\'')
3871 inquote = ! inquote;
3872 }
3873 }
3874 }
3875
31302357 3876 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 3877 m68k_ip (str);
3878 er = the_ins.error;
3879 if (!er)
3880 {
3881 for (n = 0; n < the_ins.numargs; n++)
3882 if (the_ins.operands[n].error)
3883 {
3884 er = the_ins.operands[n].error;
3885 break;
3886 }
3887 }
3888 if (er)
3889 {
3890 as_bad (_("%s -- statement `%s' ignored"), er, str);
3891 return;
3892 }
3893
3894 /* If there is a current label, record that it marks an instruction. */
3895 if (current_label != NULL)
3896 {
3897 current_label->text = 1;
3898 current_label = NULL;
3899 }
3900
f27a3839
AS		 3901#ifdef OBJ_ELF
3902 /* Tie dwarf2 debug info to the address at the start of the insn. */
3903 dwarf2_emit_insn (0);
3904#endif
3905
252b5132
RH		 3906 if (the_ins.nfrag == 0)
3907 {
36759679 3908 /* No frag hacking involved; just put it out. */
252b5132
RH		 3909 toP = frag_more (2 * the_ins.numo);
3910 fromP = &the_ins.opcode[0];
3911 for (m = the_ins.numo; m; --m)
3912 {
3913 md_number_to_chars (toP, (long) (*fromP), 2);
3914 toP += 2;
3915 fromP++;
3916 }
36759679 3917 /* Put out symbol-dependent info. */
252b5132
RH		 3918 for (m = 0; m < the_ins.nrel; m++)
3919 {
3920 switch (the_ins.reloc[m].wid)
3921 {
3922 case 'B':
3923 n = 1;
3924 break;
3925 case 'b':
3926 n = 1;
3927 break;
3928 case '3':
3929 n = 1;
3930 break;
3931 case 'w':
3932 case 'W':
3933 n = 2;
3934 break;
3935 case 'l':
3936 n = 4;
3937 break;
3938 default:
3939 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3940 the_ins.reloc[m].wid);
3941 }
3942
3943 fixP = fix_new_exp (frag_now,
3944 ((toP - frag_now->fr_literal)
3945 - the_ins.numo * 2 + the_ins.reloc[m].n),
3946 n,
3947 &the_ins.reloc[m].exp,
3948 the_ins.reloc[m].pcrel,
3949 get_reloc_code (n, the_ins.reloc[m].pcrel,
3950 the_ins.reloc[m].pic_reloc));
3951 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3952 if (the_ins.reloc[m].wid == 'B')
3953 fixP->fx_signed = 1;
3954 }
3955 return;
3956 }
3957
36759679 3958 /* There's some frag hacking. */
fbe572f9
AM		 3959 {
3960 /* Calculate the max frag size. */
3961 int wid;
3962
3963 wid = 2 * the_ins.fragb[0].fragoff;
3964 for (n = 1; n < the_ins.nfrag; n++)
3965 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3966 /* frag_var part. */
3967 wid += 10;
3968 /* Make sure the whole insn fits in one chunk, in particular that
3969 the var part is attached, as we access one byte before the
3970 variable frag for byte branches. */
3971 frag_grow (wid);
3972 }
3973
252b5132
RH		 3974 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3975 {
3976 int wid;
3977
3978 if (n == 0)
3979 wid = 2 * the_ins.fragb[n].fragoff;
3980 else
3981 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3982 toP = frag_more (wid);
3983 to_beg_P = toP;
3984 shorts_this_frag = 0;
3985 for (m = wid / 2; m; --m)
3986 {
3987 md_number_to_chars (toP, (long) (*fromP), 2);
3988 toP += 2;
3989 fromP++;
3990 shorts_this_frag++;
3991 }
3992 for (m = 0; m < the_ins.nrel; m++)
3993 {
3994 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3995 {
3996 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3997 break;
3998 }
3999 wid = the_ins.reloc[m].wid;
4000 if (wid == 0)
4001 continue;
4002 the_ins.reloc[m].wid = 0;
4003 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4004
4005 fixP = fix_new_exp (frag_now,
4006 ((toP - frag_now->fr_literal)
4007 - the_ins.numo * 2 + the_ins.reloc[m].n),
4008 wid,
4009 &the_ins.reloc[m].exp,
4010 the_ins.reloc[m].pcrel,
4011 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4012 the_ins.reloc[m].pic_reloc));
4013 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4014 }
4015 (void) frag_var (rs_machine_dependent, 10, 0,
4016 (relax_substateT) (the_ins.fragb[n].fragty),
4017 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4018 }
4019 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4020 shorts_this_frag = 0;
4021 if (n)
4022 {
055d1eb0 4023 toP = frag_more (n * 2);
252b5132
RH		 4024 while (n--)
4025 {
4026 md_number_to_chars (toP, (long) (*fromP), 2);
4027 toP += 2;
4028 fromP++;
4029 shorts_this_frag++;
4030 }
4031 }
4032 for (m = 0; m < the_ins.nrel; m++)
4033 {
4034 int wid;
4035
4036 wid = the_ins.reloc[m].wid;
4037 if (wid == 0)
4038 continue;
4039 the_ins.reloc[m].wid = 0;
4040 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4041
4042 fixP = fix_new_exp (frag_now,
4043 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4044 - shorts_this_frag * 2),
4045 wid,
4046 &the_ins.reloc[m].exp,
4047 the_ins.reloc[m].pcrel,
4048 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4049 the_ins.reloc[m].pic_reloc));
4050 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4051 }
4052}
4053
60fed2d3
NC		 4054/* Comparison function used by qsort to rank the opcode entries by name. */
4055
4056static int
4057m68k_compare_opcode (const void * v1, const void * v2)
4058{
4059 struct m68k_opcode * op1, * op2;
4060 int ret;
4061
03b13e59
NC		 4062 if (v1 == v2)
4063 return 0;
4064
60fed2d3
NC		 4065 op1 = *(struct m68k_opcode **) v1;
4066 op2 = *(struct m68k_opcode **) v2;
4067
4068 /* Compare the two names. If different, return the comparison.
4069 If the same, return the order they are in the opcode table. */
4070 ret = strcmp (op1->name, op2->name);
4071 if (ret)
4072 return ret;
4073 if (op1 < op2)
4074 return -1;
03b13e59 4075 return 1;
60fed2d3
NC		 4076}
4077
252b5132 4078void
60fed2d3 4079md_begin (void)
252b5132 4080{
60fed2d3
NC		 4081 const struct m68k_opcode *ins;
4082 struct m68k_incant *hack, *slak;
4083 const char *retval = 0; /* Empty string, or error msg text. */
4084 int i;
4085
4086 /* Set up hash tables with 68000 instructions.
4087 similar to what the vax assembler does. */
252b5132
RH		 4088 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4089 a copy of it at runtime, adding in the information we want but isn't
4090 there. I think it'd be better to have an awk script hack the table
4091 at compile time. Or even just xstr the table and use it as-is. But
4092 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4093 names. */
4094
252b5132
RH		 4095 if (flag_mri)
4096 {
4097 flag_reg_prefix_optional = 1;
4098 m68k_abspcadd = 1;
4099 if (! m68k_rel32_from_cmdline)
4100 m68k_rel32 = 0;
4101 }
4102
60fed2d3
NC		 4103 /* First sort the opcode table into alphabetical order to seperate
4104 the order that the assembler wants to see the opcodes from the
4105 order that the disassembler wants to see them. */
4106 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4107 if (!m68k_sorted_opcodes)
4108 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4109 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4110
4111 for (i = m68k_numopcodes; i--;)
4112 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4113
4114 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4115 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4116
252b5132
RH		 4117 op_hash = hash_new ();
4118
4119 obstack_begin (&robyn, 4000);
4120 for (i = 0; i < m68k_numopcodes; i++)
4121 {
4122 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4123 do
4124 {
60fed2d3
NC		 4125 ins = m68k_sorted_opcodes[i];
4126
4127 /* We *could* ignore insns that don't match our
4128 arch here by just leaving them out of the hash. */
252b5132
RH		 4129 slak->m_operands = ins->args;
4130 slak->m_opnum = strlen (slak->m_operands) / 2;
4131 slak->m_arch = ins->arch;
4132 slak->m_opcode = ins->opcode;
36759679 4133 /* This is kludgey. */
252b5132
RH		 4134 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4135 if (i + 1 != m68k_numopcodes
60fed2d3 4136 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4137 {
60fed2d3 4138 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4139 i++;
4140 }
4141 else
4142 slak->m_next = 0;
4143 slak = slak->m_next;
4144 }
4145 while (slak);
4146
4147 retval = hash_insert (op_hash, ins->name, (char *) hack);
4148 if (retval)
4149 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4150 }
4151
4152 for (i = 0; i < m68k_numaliases; i++)
4153 {
4154 const char *name = m68k_opcode_aliases[i].primary;
4155 const char *alias = m68k_opcode_aliases[i].alias;
4156 PTR val = hash_find (op_hash, name);
60fed2d3 4157
252b5132
RH		 4158 if (!val)
4159 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4160 retval = hash_insert (op_hash, alias, val);
4161 if (retval)
4162 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4163 }
4164
4165 /* In MRI mode, all unsized branches are variable sized. Normally,
4166 they are word sized. */
4167 if (flag_mri)
4168 {
4169 static struct m68k_opcode_alias mri_aliases[] =
4170 {
4171 { "bhi", "jhi", },
4172 { "bls", "jls", },
4173 { "bcc", "jcc", },
4174 { "bcs", "jcs", },
4175 { "bne", "jne", },
4176 { "beq", "jeq", },
4177 { "bvc", "jvc", },
4178 { "bvs", "jvs", },
4179 { "bpl", "jpl", },
4180 { "bmi", "jmi", },
4181 { "bge", "jge", },
4182 { "blt", "jlt", },
4183 { "bgt", "jgt", },
4184 { "ble", "jle", },
4185 { "bra", "jra", },
4186 { "bsr", "jbsr", },
4187 };
4188
8fce3f5e
AM		 4189 for (i = 0;
4190 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4191 i++)
252b5132
RH		 4192 {
4193 const char *name = mri_aliases[i].primary;
4194 const char *alias = mri_aliases[i].alias;
4195 PTR val = hash_find (op_hash, name);
60fed2d3 4196
252b5132
RH		 4197 if (!val)
4198 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4199 retval = hash_jam (op_hash, alias, val);
4200 if (retval)
4201 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4202 }
4203 }
4204
8fce3f5e 4205 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4206 {
4207 notend_table[i] = 0;
4208 alt_notend_table[i] = 0;
4209 }
60fed2d3 4210
252b5132
RH		 4211 notend_table[','] = 1;
4212 notend_table['{'] = 1;
4213 notend_table['}'] = 1;
4214 alt_notend_table['a'] = 1;
4215 alt_notend_table['A'] = 1;
4216 alt_notend_table['d'] = 1;
4217 alt_notend_table['D'] = 1;
4218 alt_notend_table['#'] = 1;
4219 alt_notend_table['&'] = 1;
4220 alt_notend_table['f'] = 1;
4221 alt_notend_table['F'] = 1;
4222#ifdef REGISTER_PREFIX
4223 alt_notend_table[REGISTER_PREFIX] = 1;
4224#endif
4225
4226 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4227 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4228 alt_notend_table['('] = 1;
4229
4230 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4231 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4232 alt_notend_table['@'] = 1;
4233
4234 /* We need to put digits in alt_notend_table to handle
60fed2d3 4235 bfextu %d0{24:1},%d0 */
252b5132
RH		 4236 alt_notend_table['0'] = 1;
4237 alt_notend_table['1'] = 1;
4238 alt_notend_table['2'] = 1;
4239 alt_notend_table['3'] = 1;
4240 alt_notend_table['4'] = 1;
4241 alt_notend_table['5'] = 1;
4242 alt_notend_table['6'] = 1;
4243 alt_notend_table['7'] = 1;
4244 alt_notend_table['8'] = 1;
4245 alt_notend_table['9'] = 1;
4246
4247#ifndef MIT_SYNTAX_ONLY
4248 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4249 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4250 {
4251 int n = 0;
60fed2d3 4252
252b5132
RH		 4253 while (mote_pseudo_table[n].poc_name)
4254 {
60fed2d3 4255 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4256 hash_insert (op_hash,
4257 mote_pseudo_table[n].poc_name, (char *) hack);
4258 hack->m_operands = 0;
4259 hack->m_opnum = n;
4260 n++;
4261 }
4262 }
4263#endif
4264
4265 init_regtable ();
4266
4267#ifdef OBJ_ELF
4268 record_alignment (text_section, 2);
4269 record_alignment (data_section, 2);
4270 record_alignment (bss_section, 2);
4271#endif
4272}
4273
4274static void
31302357 4275select_control_regs (void)
252b5132
RH		 4276{
4277 /* Note which set of "movec" control registers is available. */
6b6e92f4 4278 switch (current_chip)
252b5132 4279 {
4f2a7c9e 4280 case 0:
6b6e92f4
NC		 4281 if (verbose)
4282 as_warn (_("architecture not yet selected: defaulting to 68020"));
4f2a7c9e
NC		 4283 control_regs = m68020_control_regs;
4284 break;
4285
252b5132
RH		 4286 case m68000:
4287 control_regs = m68000_control_regs;
4288 break;
4289 case m68010:
4290 control_regs = m68010_control_regs;
4291 break;
4292 case m68020:
4293 case m68030:
4294 control_regs = m68020_control_regs;
4295 break;
4296 case m68040:
4297 control_regs = m68040_control_regs;
4298 break;
4299 case m68060:
4300 control_regs = m68060_control_regs;
4301 break;
4302 case cpu32:
4303 control_regs = cpu32_control_regs;
4304 break;
4305 case mcf5200:
6da466c7
ILT		 4306 case mcf5206e:
4307 case mcf5307:
dc84e067 4308 case mcf5407:
6da466c7 4309 control_regs = mcf_control_regs;
252b5132 4310 break;
e80e0390
NC		 4311 case mcf5249:
4312 control_regs = mcf5249_control_regs;
4313 break;
3e602632 4314 case mcf528x:
6b6e92f4 4315 case mcf521x:
3e602632
NC		 4316 control_regs = mcf528x_control_regs;
4317 break;
6b6e92f4
NC		 4318 case mcf5470:
4319 case mcf5480:
3e602632
NC		 4320 control_regs = mcfv4e_control_regs;
4321 break;
252b5132
RH		 4322 default:
4323 abort ();
4324 }
4325}
4326
4327void
31302357 4328m68k_init_after_args (void)
252b5132
RH		 4329{
4330 if (cpu_of_arch (current_architecture) == 0)
4331 {
4332 int i;
4333 const char *default_cpu = TARGET_CPU;
4334
4335 if (*default_cpu == 'm')
4336 default_cpu++;
4337 for (i = 0; i < n_archs; i++)
4338 if (strcasecmp (default_cpu, archs[i].name) == 0)
4339 break;
4340 if (i == n_archs)
4341 {
4342 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
4343 current_architecture |= m68020;
4344 }
4345 else
4346 current_architecture |= archs[i].arch;
4347 }
4348 /* Permit m68881 specification with all cpus; those that can't work
4349 with a coprocessor could be doing emulation. */
4350 if (current_architecture & m68851)
4351 {
4352 if (current_architecture & m68040)
60fed2d3 4353 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
252b5132
RH		 4354 }
4355 /* What other incompatibilities could we check for? */
4356
4357 /* Toss in some default assumptions about coprocessors. */
4358 if (!no_68881
4359 && (cpu_of_arch (current_architecture)
4360 /* Can CPU32 have a 68881 coprocessor?? */
4361 & (m68020 | m68030 | cpu32)))
60fed2d3
NC		 4362 current_architecture |= m68881;
4363
252b5132
RH		 4364 if (!no_68851
4365 && (cpu_of_arch (current_architecture) & m68020up) != 0
4366 && (cpu_of_arch (current_architecture) & m68040up) == 0)
60fed2d3
NC		 4367 current_architecture |= m68851;
4368
252b5132
RH		 4369 if (no_68881 && (current_architecture & m68881))
4370 as_bad (_("options for 68881 and no-68881 both given"));
60fed2d3 4371
252b5132
RH		 4372 if (no_68851 && (current_architecture & m68851))
4373 as_bad (_("options for 68851 and no-68851 both given"));
4374
252b5132
RH		 4375 /* Note which set of "movec" control registers is available. */
4376 select_control_regs ();
4377
4378 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4379 || arch_coldfire_p (current_architecture))
252b5132
RH		 4380 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4381}
4382\f
4383/* This is called when a label is defined. */
4384
4385void
31302357 4386m68k_frob_label (symbolS *sym)
252b5132
RH		 4387{
4388 struct label_line *n;
4389
4390 n = (struct label_line *) xmalloc (sizeof *n);
4391 n->next = labels;
4392 n->label = sym;
4393 as_where (&n->file, &n->line);
4394 n->text = 0;
4395 labels = n;
4396 current_label = n;
4397}
4398
4399/* This is called when a value that is not an instruction is emitted. */
4400
4401void
31302357 4402m68k_flush_pending_output (void)
252b5132
RH		 4403{
4404 current_label = NULL;
4405}
4406
4407/* This is called at the end of the assembly, when the final value of
4408 the label is known. We warn if this is a text symbol aligned at an
4409 odd location. */
4410
4411void
31302357 4412m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4413{
4414 if (S_GET_SEGMENT (sym) == reg_section
4415 && (int) S_GET_VALUE (sym) < 0)
4416 {
4417 S_SET_SEGMENT (sym, absolute_section);
4418 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4419 }
4420 else if ((S_GET_VALUE (sym) & 1) != 0)
4421 {
4422 struct label_line *l;
4423
4424 for (l = labels; l != NULL; l = l->next)
4425 {
4426 if (l->label == sym)
4427 {
4428 if (l->text)
4429 as_warn_where (l->file, l->line,
4430 _("text label `%s' aligned to odd boundary"),
4431 S_GET_NAME (sym));
4432 break;
4433 }
4434 }
4435 }
4436}
4437\f
4438/* This is called if we go in or out of MRI mode because of the .mri
4439 pseudo-op. */
4440
4441void
31302357 4442m68k_mri_mode_change (int on)
252b5132
RH		 4443{
4444 if (on)
4445 {
4446 if (! flag_reg_prefix_optional)
4447 {
4448 flag_reg_prefix_optional = 1;
4449#ifdef REGISTER_PREFIX
4450 init_regtable ();
4451#endif
4452 }
4453 m68k_abspcadd = 1;
4454 if (! m68k_rel32_from_cmdline)
4455 m68k_rel32 = 0;
4456 }
4457 else
4458 {
4459 if (! reg_prefix_optional_seen)
4460 {
4461#ifdef REGISTER_PREFIX_OPTIONAL
4462 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4463#else
4464 flag_reg_prefix_optional = 0;
4465#endif
4466#ifdef REGISTER_PREFIX
4467 init_regtable ();
4468#endif
4469 }
4470 m68k_abspcadd = 0;
4471 if (! m68k_rel32_from_cmdline)
4472 m68k_rel32 = 1;
4473 }
4474}
4475
36759679 4476/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4477#define MAX_LITTLENUMS 6
4478
4479/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4480 of type TYPE, and store the appropriate bytes in *LITP. The number
4481 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4482 returned, or NULL on OK. */
4483
4484char *
31302357 4485md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4486{
4487 int prec;
4488 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4489 LITTLENUM_TYPE *wordP;
4490 char *t;
4491
4492 switch (type)
4493 {
4494 case 'f':
4495 case 'F':
4496 case 's':
4497 case 'S':
4498 prec = 2;
4499 break;
4500
4501 case 'd':
4502 case 'D':
4503 case 'r':
4504 case 'R':
4505 prec = 4;
4506 break;
4507
4508 case 'x':
4509 case 'X':
4510 prec = 6;
4511 break;
4512
4513 case 'p':
4514 case 'P':
4515 prec = 6;
4516 break;
4517
4518 default:
4519 *sizeP = 0;
4520 return _("Bad call to MD_ATOF()");
4521 }
4522 t = atof_ieee (input_line_pointer, type, words);
4523 if (t)
4524 input_line_pointer = t;
4525
4526 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4527 for (wordP = words; prec--;)
4528 {
4529 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4530 litP += sizeof (LITTLENUM_TYPE);
4531 }
4532 return 0;
4533}
4534
4535void
31302357 4536md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4537{
4538 number_to_chars_bigendian (buf, val, n);
4539}
4540
94f592af 4541void
55cf6793 4542md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4543{
bbe8ef22 4544 offsetT val = *valP;
252b5132
RH		 4545 addressT upper_limit;
4546 offsetT lower_limit;
4547
4548 /* This is unnecessary but it convinces the native rs6000 compiler
4549 to generate the code we want. */
4550 char *buf = fixP->fx_frag->fr_literal;
4551 buf += fixP->fx_where;
36759679 4552 /* End ibm compiler workaround. */
252b5132 4553
bd17c2c3 4554 val = SEXT (val);
252b5132 4555
94f592af
NC		 4556 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4557 fixP->fx_done = 1;
4558
252b5132
RH		 4559#ifdef OBJ_ELF
4560 if (fixP->fx_addsy)
4561 {
4562 memset (buf, 0, fixP->fx_size);
36759679 4563 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4564
4565 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4566 && !S_IS_DEFINED (fixP->fx_addsy)
4567 && !S_IS_WEAK (fixP->fx_addsy))
4568 S_SET_WEAK (fixP->fx_addsy);
4569 return;
4570 }
4571#endif
4572
252b5132
RH		 4573 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4574 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4575 return;
252b5132
RH		 4576
4577 switch (fixP->fx_size)
4578 {
94f592af
NC		 4579 /* The cast to offsetT below are necessary to make code
4580 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4581 case 1:
4582 *buf++ = val;
4583 upper_limit = 0x7f;
4584 lower_limit = - (offsetT) 0x80;
4585 break;
4586 case 2:
4587 *buf++ = (val >> 8);
4588 *buf++ = val;
4589 upper_limit = 0x7fff;
4590 lower_limit = - (offsetT) 0x8000;
4591 break;
4592 case 4:
4593 *buf++ = (val >> 24);
4594 *buf++ = (val >> 16);
4595 *buf++ = (val >> 8);
4596 *buf++ = val;
4597 upper_limit = 0x7fffffff;
36759679 4598 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4599 break;
4600 default:
4601 BAD_CASE (fixP->fx_size);
4602 }
4603
4604 /* Fix up a negative reloc. */
4605 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4606 {
4607 fixP->fx_addsy = fixP->fx_subsy;
4608 fixP->fx_subsy = NULL;
4609 fixP->fx_tcbit = 1;
4610 }
4611
4612 /* For non-pc-relative values, it's conceivable we might get something
4613 like "0xff" for a byte field. So extend the upper part of the range
4614 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4615 so that we can do any range checking at all. */
4616 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4617 upper_limit = upper_limit * 2 + 1;
4618
4619 if ((addressT) val > upper_limit
4620 && (val > 0 || val < lower_limit))
4621 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4622
4623 /* A one byte PC-relative reloc means a short branch. We can't use
4624 a short branch with a value of 0 or -1, because those indicate
4625 different opcodes (branches with longer offsets). fixup_segment
4626 in write.c may have clobbered fx_pcrel, so we need to examine the
4627 reloc type. */
4628 if ((fixP->fx_pcrel
7be1c489 4629 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4630 && fixP->fx_size == 1
4631 && (fixP->fx_addsy == NULL
4632 || S_IS_DEFINED (fixP->fx_addsy))
4633 && (val == 0 || val == -1))
4634 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4635}
4636
252b5132
RH		 4637/* *fragP has been relaxed to its final size, and now needs to have
4638 the bytes inside it modified to conform to the new size There is UGLY
4639 MAGIC here. ..
4640 */
4641static void
31302357 4642md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4643{
4644 long disp;
252b5132
RH		 4645 fixS *fixP;
4646
4647 /* Address in object code of the displacement. */
4648 register int object_address = fragP->fr_fix + fragP->fr_address;
4649
4650 /* Address in gas core of the place to store the displacement. */
4651 /* This convinces the native rs6000 compiler to generate the code we
92774660 4652 want. */
252b5132
RH		 4653 register char *buffer_address = fragP->fr_literal;
4654 buffer_address += fragP->fr_fix;
36759679 4655 /* End ibm compiler workaround. */
252b5132
RH		 4656
4657 /* The displacement of the address, from current location. */
4658 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4659 disp = (disp + fragP->fr_offset) - object_address;
4660
252b5132
RH		 4661 switch (fragP->fr_subtype)
4662 {
151337e8
NC		 4663 case TAB (BRANCHBWL, BYTE):
4664 case TAB (BRABSJUNC, BYTE):
4665 case TAB (BRABSJCOND, BYTE):
4666 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4667 know (issbyte (disp));
4668 if (disp == 0)
b091f402
AM		 4669 as_bad_where (fragP->fr_file, fragP->fr_line,
4670 _("short branch with zero offset: use :w"));
151337e8 4671 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4672 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4673 fixP->fx_pcrel_adjust = -1;
252b5132 4674 break;
151337e8
NC		 4675 case TAB (BRANCHBWL, SHORT):
4676 case TAB (BRABSJUNC, SHORT):
4677 case TAB (BRABSJCOND, SHORT):
4678 case TAB (BRANCHBW, SHORT):
252b5132 4679 fragP->fr_opcode[1] = 0x00;
151337e8 4680 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4681 1, RELAX_RELOC_PC16);
151337e8
NC		 4682 fragP->fr_fix += 2;
4683 break;
4684 case TAB (BRANCHBWL, LONG):
4685 fragP->fr_opcode[1] = (char) 0xFF;
4686 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4687 1, RELAX_RELOC_PC32);
151337e8 4688 fragP->fr_fix += 4;
252b5132 4689 break;
151337e8
NC		 4690 case TAB (BRABSJUNC, LONG):
4691 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4692 {
36759679 4693 if (flag_keep_pcrel)
6b6e92f4 4694 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4695 fragP->fr_opcode[0] = 0x4E;
36759679 4696 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4697 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4698 0, RELAX_RELOC_ABS32);
151337e8
NC		 4699 fragP->fr_fix += 4;
4700 }
4701 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4702 {
36759679 4703 if (flag_keep_pcrel)
6b6e92f4 4704 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4705 fragP->fr_opcode[0] = 0x4E;
36759679 4706 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4707 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4708 0, RELAX_RELOC_ABS32);
151337e8 4709 fragP->fr_fix += 4;
252b5132
RH		 4710 }
4711 else
4712 {
151337e8
NC		 4713 /* This cannot happen, because jbsr and jbra are the only two
4714 unconditional branches. */
4715 abort ();
252b5132
RH		 4716 }
4717 break;
151337e8 4718 case TAB (BRABSJCOND, LONG):
36759679 4719 if (flag_keep_pcrel)
6b6e92f4 4720 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4721
36759679
NC		 4722 /* Only Bcc 68000 instructions can come here
4723 Change bcc into b!cc/jmp absl long. */
4724 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4725 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4726
4727 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4728 different frag, in which case referring to them is a no-no.
92774660 4729 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4730 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4731 *buffer_address++ = (char) 0xf9;
36759679 4732 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4733 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4734 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4735 fragP->fr_fix += 4;
4736 break;
4737 case TAB (FBRANCH, SHORT):
4738 know ((fragP->fr_opcode[1] & 0x40) == 0);
4739 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4740 1, RELAX_RELOC_PC16);
151337e8
NC		 4741 fragP->fr_fix += 2;
4742 break;
4743 case TAB (FBRANCH, LONG):
36759679 4744 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4745 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4746 1, RELAX_RELOC_PC32);
252b5132 4747 fragP->fr_fix += 4;
252b5132 4748 break;
151337e8
NC		 4749 case TAB (DBCCLBR, SHORT):
4750 case TAB (DBCCABSJ, SHORT):
4751 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4752 1, RELAX_RELOC_PC16);
151337e8
NC		 4753 fragP->fr_fix += 2;
4754 break;
4755 case TAB (DBCCLBR, LONG):
36759679
NC		 4756 /* Only DBcc instructions can come here.
4757 Change dbcc into dbcc/bral.
4758 JF: these used to be fr_opcode[2-7], but that's wrong. */
4759 if (flag_keep_pcrel)
6b6e92f4 4760 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4761
36759679 4762 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4763 *buffer_address++ = 0x04;
36759679 4764 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4765 *buffer_address++ = 0x06;
151337e8
NC		 4766 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4767 *buffer_address++ = (char) 0xff;
252b5132 4768
36759679 4769 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4770 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4771 RELAX_RELOC_PC32);
252b5132 4772 fragP->fr_fix += 4;
252b5132 4773 break;
151337e8 4774 case TAB (DBCCABSJ, LONG):
36759679
NC		 4775 /* Only DBcc instructions can come here.
4776 Change dbcc into dbcc/jmp.
4777 JF: these used to be fr_opcode[2-7], but that's wrong. */
4778 if (flag_keep_pcrel)
6b6e92f4 4779 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4780
36759679 4781 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4782 *buffer_address++ = 0x04;
36759679 4783 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4784 *buffer_address++ = 0x06;
36759679 4785 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4786 *buffer_address++ = (char) 0xf9;
4787
36759679 4788 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4789 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4790 RELAX_RELOC_ABS32);
252b5132 4791 fragP->fr_fix += 4;
252b5132 4792 break;
151337e8 4793 case TAB (PCREL1632, SHORT):
252b5132
RH		 4794 fragP->fr_opcode[1] &= ~0x3F;
4795 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4796 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4797 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4798 fragP->fr_fix += 2;
252b5132 4799 break;
151337e8 4800 case TAB (PCREL1632, LONG):
252b5132
RH		 4801 /* Already set to mode 7.3; this indicates: PC indirect with
4802 suppressed index, 32-bit displacement. */
4803 *buffer_address++ = 0x01;
4804 *buffer_address++ = 0x70;
4805 fragP->fr_fix += 2;
151337e8 4806 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4807 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4808 fixP->fx_pcrel_adjust = 2;
4809 fragP->fr_fix += 4;
252b5132 4810 break;
252b5132 4811 case TAB (PCINDEX, BYTE):
252b5132
RH		 4812 assert (fragP->fr_fix >= 2);
4813 buffer_address[-2] &= ~1;
151337e8 4814 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4815 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4816 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4817 break;
4818 case TAB (PCINDEX, SHORT):
252b5132
RH		 4819 assert (fragP->fr_fix >= 2);
4820 buffer_address[-2] |= 0x1;
4821 buffer_address[-1] = 0x20;
4822 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4823 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4824 fixP->fx_pcrel_adjust = 2;
151337e8 4825 fragP->fr_fix += 2;
252b5132
RH		 4826 break;
4827 case TAB (PCINDEX, LONG):
252b5132
RH		 4828 assert (fragP->fr_fix >= 2);
4829 buffer_address[-2] |= 0x1;
4830 buffer_address[-1] = 0x30;
151337e8 4831 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4832 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4833 fixP->fx_pcrel_adjust = 2;
4834 fragP->fr_fix += 4;
4835 break;
4836 case TAB (ABSTOPCREL, SHORT):
4837 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4838 1, RELAX_RELOC_PC16);
151337e8
NC		 4839 fragP->fr_fix += 2;
4840 break;
4841 case TAB (ABSTOPCREL, LONG):
36759679 4842 if (flag_keep_pcrel)
6b6e92f4 4843 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4844 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4845 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4846 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4847 abort ();
4848 fragP->fr_opcode[1] &= ~0x3F;
4849 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4850 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4851 0, RELAX_RELOC_ABS32);
151337e8 4852 fragP->fr_fix += 4;
252b5132 4853 break;
252b5132
RH		 4854 }
4855}
4856
252b5132 4857void
31302357
AS		 4858md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4859 segT sec ATTRIBUTE_UNUSED,
4860 fragS *fragP)
252b5132
RH		 4861{
4862 md_convert_frag_1 (fragP);
4863}
252b5132
RH		 4864
4865/* Force truly undefined symbols to their maximum size, and generally set up
4866 the frag list to be relaxed
4867 */
4868int
31302357 4869md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4870{
151337e8 4871 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4872 switch (fragP->fr_subtype)
4873 {
151337e8
NC		 4874 case TAB (BRANCHBWL, SZ_UNDEF):
4875 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4876 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4877 {
151337e8
NC		 4878 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4879 && relaxable_symbol (fragP->fr_symbol))
252b5132 4880 {
151337e8
NC		 4881 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4882 }
4883 else if (flag_short_refs)
4884 {
4885 /* Symbol is undefined and we want short ref. */
4886 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4887 }
4888 else
4889 {
151337e8
NC		 4890 /* Symbol is still undefined. Make it LONG. */
4891 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4892 }
4893 break;
151337e8 4894 }
252b5132 4895
151337e8 4896 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4897 {
151337e8
NC		 4898 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4899 && relaxable_symbol (fragP->fr_symbol))
252b5132 4900 {
151337e8 4901 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4902 }
4903 else
4904 {
151337e8
NC		 4905 /* Symbol is undefined and we don't have long branches. */
4906 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4907 }
4908 break;
151337e8 4909 }
252b5132 4910
151337e8 4911 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4912 case TAB (DBCCLBR, SZ_UNDEF):
4913 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4914 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4915 {
8ec6253e
NC		 4916 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4917 && relaxable_symbol (fragP->fr_symbol))
151337e8 4918 || flag_short_refs)
252b5132 4919 {
151337e8 4920 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4921 }
4922 else
4923 {
151337e8 4924 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4925 }
4926 break;
151337e8 4927 }
81d4177b 4928
252b5132
RH		 4929 case TAB (PCINDEX, SZ_UNDEF):
4930 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4931 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4932 {
4933 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4934 }
4935 else
4936 {
4937 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4938 }
4939 break;
4940
151337e8
NC		 4941 case TAB (ABSTOPCREL, SZ_UNDEF):
4942 {
4943 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4944 && relaxable_symbol (fragP->fr_symbol)))
4945 {
4946 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4947 }
4948 else
4949 {
4950 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4951 }
4952 break;
4953 }
4954
252b5132
RH		 4955 default:
4956 break;
4957 }
4958
151337e8 4959 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4960 switch (fragP->fr_subtype)
4961 {
151337e8
NC		 4962 case TAB (BRANCHBWL, BYTE):
4963 case TAB (BRABSJUNC, BYTE):
4964 case TAB (BRABSJCOND, BYTE):
4965 case TAB (BRANCHBW, BYTE):
252b5132 4966 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4967 case we force word mode. If the symbol is at the start of a
4968 frag, and it is the next frag with any data in it (usually
4969 this is just the next frag, but assembler listings may
4970 introduce empty frags), we must use word mode. */
4971 if (fragP->fr_symbol)
252b5132 4972 {
ac62c346 4973 fragS *sym_frag;
252b5132 4974
ac62c346
AM		 4975 sym_frag = symbol_get_frag (fragP->fr_symbol);
4976 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4977 {
ac62c346
AM		 4978 fragS *l;
4979
23b7f870 4980 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4981 if (l->fr_fix != 0)
4982 break;
4983 if (l == sym_frag)
4984 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4985 }
4986 }
4987 break;
4988 default:
4989 break;
4990 }
ac62c346 4991 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4992}
4993
4994#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4995/* the bit-field entries in the relocation_info struct plays hell
4996 with the byte-order problems of cross-assembly. So as a hack,
4997 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 4998 you there. -KWK */
252b5132
RH		 4999/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5000 are symbolnum, most sig. byte first. Last byte is broken up with
5001 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5002 nibble as nuthin. (on Sun 3 at least) */
5003/* Translate the internal relocation information into target-specific
92774660 5004 format. */
252b5132
RH		 5005#ifdef comment
5006void
31302357 5007md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5008{
36759679 5009 /* This is easy. */
252b5132 5010 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5011 /* Now the fun stuff. */
252b5132 5012 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5013 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5014 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5015 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5016 | ((ri->r_length << 5) & 0x60)
5017 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5018}
5019
36759679 5020#endif
252b5132 5021
252b5132
RH		 5022#endif /* OBJ_AOUT or OBJ_BOUT */
5023
5024#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5025int md_short_jump_size = 4;
5026int md_long_jump_size = 6;
252b5132
RH		 5027
5028void
31302357
AS		 5029md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5030 fragS *frag ATTRIBUTE_UNUSED,
5031 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5032{
5033 valueT offset;
5034
5035 offset = to_addr - (from_addr + 2);
5036
5037 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5038 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5039}
5040
5041void
31302357
AS		 5042md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5043 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5044{
5045 valueT offset;
5046
6b6e92f4 5047 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5048 {
36759679 5049 if (flag_keep_pcrel)
6b6e92f4 5050 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5051 offset = to_addr - S_GET_VALUE (to_symbol);
5052 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5053 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5054 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5055 0, NO_RELOC);
5056 }
5057 else
5058 {
5059 offset = to_addr - (from_addr + 2);
5060 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5061 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5062 }
5063}
5064
5065#endif
5066
5067/* Different values of OK tell what its OK to return. Things that
5068 aren't OK are an error (what a shock, no?)
5069
5070 0: Everything is OK
3e602632
NC		 5071 10: Absolute 1:8 only
5072 20: Absolute 0:7 only
5073 30: absolute 0:15 only
5074 40: Absolute 0:31 only
5075 50: absolute 0:127 only
252b5132 5076 55: absolute -64:63 only
3e602632
NC		 5077 60: absolute -128:127 only
5078 70: absolute 0:4095 only
5079 80: absolute -1, 1:7 only
5080 90: No bignums. */
252b5132
RH		 5081
5082static int
31302357 5083get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5084{
5085 if (exp->exp.X_op == O_absent)
5086 {
36759679 5087 /* Do the same thing the VAX asm does. */
252b5132
RH		 5088 op (exp) = O_constant;
5089 adds (exp) = 0;
5090 subs (exp) = 0;
5091 offs (exp) = 0;
5092 if (ok == 10)
5093 {
5094 as_warn (_("expression out of range: defaulting to 1"));
5095 offs (exp) = 1;
5096 }
5097 }
5098 else if (exp->exp.X_op == O_constant)
5099 {
5100 switch (ok)
5101 {
5102 case 10:
bd17c2c3 5103 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5104 {
5105 as_warn (_("expression out of range: defaulting to 1"));
5106 offs (exp) = 1;
5107 }
5108 break;
5109 case 20:
bd17c2c3 5110 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5111 goto outrange;
5112 break;
5113 case 30:
bd17c2c3 5114 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5115 goto outrange;
5116 break;
5117 case 40:
bd17c2c3 5118 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5119 goto outrange;
5120 break;
5121 case 50:
bd17c2c3 5122 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5123 goto outrange;
5124 break;
5125 case 55:
bd17c2c3 5126 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5127 goto outrange;
5128 break;
5129 case 60:
bd17c2c3 5130 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5131 goto outrange;
5132 break;
5133 case 70:
bd17c2c3 5134 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5135 {
5136 outrange:
5137 as_warn (_("expression out of range: defaulting to 0"));
5138 offs (exp) = 0;
5139 }
5140 break;
3e602632 5141 case 80:
bd17c2c3
AM		 5142 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5143 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5144 {
5145 as_warn (_("expression out of range: defaulting to 1"));
5146 offs (exp) = 1;
5147 }
5148 break;
252b5132
RH		 5149 default:
5150 break;
5151 }
5152 }
5153 else if (exp->exp.X_op == O_big)
5154 {
36759679 5155 if (offs (exp) <= 0 /* flonum. */
3e602632 5156 && (ok == 90 /* no bignums */
36759679 5157 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5158 /* If we have a flonum zero, a zero integer should
5159 do as well (e.g., in moveq). */
5160 && generic_floating_point_number.exponent == 0
5161 && generic_floating_point_number.low[0] == 0)))
5162 {
36759679 5163 /* HACK! Turn it into a long. */
252b5132
RH		 5164 LITTLENUM_TYPE words[6];
5165
36759679 5166 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5167 op (exp) = O_constant;
5168 adds (exp) = 0;
5169 subs (exp) = 0;
5170 offs (exp) = words[1] | (words[0] << 16);
5171 }
5172 else if (ok != 0)
5173 {
5174 op (exp) = O_constant;
5175 adds (exp) = 0;
5176 subs (exp) = 0;
5177 offs (exp) = (ok == 10) ? 1 : 0;
5178 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5179 (long) offs (exp));
252b5132
RH		 5180 }
5181 }
5182 else
5183 {
3e602632 5184 if (ok >= 10 && ok <= 80)
252b5132
RH		 5185 {
5186 op (exp) = O_constant;
5187 adds (exp) = 0;
5188 subs (exp) = 0;
5189 offs (exp) = (ok == 10) ? 1 : 0;
5190 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5191 (long) offs (exp));
252b5132
RH		 5192 }
5193 }
5194
5195 if (exp->size != SIZE_UNSPEC)
5196 {
5197 switch (exp->size)
5198 {
5199 case SIZE_UNSPEC:
5200 case SIZE_LONG:
5201 break;
5202 case SIZE_BYTE:
5203 if (!isbyte (offs (exp)))
5204 as_warn (_("expression doesn't fit in BYTE"));
5205 break;
5206 case SIZE_WORD:
5207 if (!isword (offs (exp)))
5208 as_warn (_("expression doesn't fit in WORD"));
5209 break;
5210 }
5211 }
5212
5213 return offs (exp);
5214}
5215
5216/* These are the back-ends for the various machine dependent pseudo-ops. */
5217
5218static void
31302357 5219s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5220{
5221 subseg_set (data_section, 1);
5222 demand_empty_rest_of_line ();
5223}
5224
5225static void
31302357 5226s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5227{
5228 subseg_set (data_section, 2);
5229 demand_empty_rest_of_line ();
5230}
5231
5232static void
31302357 5233s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5234{
5235 /* We don't support putting frags in the BSS segment, we fake it
5236 by marking in_bss, then looking at s_skip for clues. */
5237
5238 subseg_set (bss_section, 0);
5239 demand_empty_rest_of_line ();
5240}
5241
5242static void
31302357 5243s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5244{
5245 register int temp;
5246 register long temp_fill;
5247
5248 temp = 1; /* JF should be 2? */
5249 temp_fill = get_absolute_expression ();
92774660 5250 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5251 frag_align (temp, (int) temp_fill, 0);
5252 demand_empty_rest_of_line ();
5253 record_alignment (now_seg, temp);
5254}
5255
5256static void
31302357 5257s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5258{
5259 demand_empty_rest_of_line ();
5260}
5261\f
5262/* Pseudo-ops handled for MRI compatibility. */
5263
5264/* This function returns non-zero if the argument is a conditional
5265 pseudo-op. This is called when checking whether a pending
5266 alignment is needed. */
5267
5268int
31302357 5269m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5270{
5271 return (pop->poc_handler == s_mri_if
5272 || pop->poc_handler == s_mri_else);
5273}
5274
5275/* Handle an MRI style chip specification. */
5276
5277static void
31302357 5278mri_chip (void)
252b5132
RH		 5279{
5280 char *s;
5281 char c;
5282 int i;
5283
5284 s = input_line_pointer;
5285 /* We can't use get_symbol_end since the processor names are not proper
5286 symbols. */
5287 while (is_part_of_name (c = *input_line_pointer++))
5288 ;
5289 *--input_line_pointer = 0;
5290 for (i = 0; i < n_archs; i++)
5291 if (strcasecmp (s, archs[i].name) == 0)
5292 break;
5293 if (i >= n_archs)
5294 {
5295 as_bad (_("%s: unrecognized processor name"), s);
5296 *input_line_pointer = c;
5297 ignore_rest_of_line ();
5298 return;
5299 }
5300 *input_line_pointer = c;
5301
5302 if (*input_line_pointer == '/')
5303 current_architecture = 0;
5304 else
5305 current_architecture &= m68881 | m68851;
5306 current_architecture |= archs[i].arch;
990ae22a 5307 current_chip = archs[i].chip;
252b5132
RH		 5308
5309 while (*input_line_pointer == '/')
5310 {
5311 ++input_line_pointer;
5312 s = input_line_pointer;
5313 /* We can't use get_symbol_end since the processor names are not
5314 proper symbols. */
5315 while (is_part_of_name (c = *input_line_pointer++))
5316 ;
5317 *--input_line_pointer = 0;
5318 if (strcmp (s, "68881") == 0)
5319 current_architecture |= m68881;
5320 else if (strcmp (s, "68851") == 0)
5321 current_architecture |= m68851;
5322 *input_line_pointer = c;
5323 }
5324
5325 /* Update info about available control registers. */
5326 select_control_regs ();
5327}
5328
5329/* The MRI CHIP pseudo-op. */
5330
5331static void
31302357 5332s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5333{
5334 char *stop = NULL;
5335 char stopc;
5336
5337 if (flag_mri)
5338 stop = mri_comment_field (&stopc);
5339 mri_chip ();
5340 if (flag_mri)
5341 mri_comment_end (stop, stopc);
5342 demand_empty_rest_of_line ();
5343}
5344
5345/* The MRI FOPT pseudo-op. */
5346
5347static void
31302357 5348s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5349{
5350 SKIP_WHITESPACE ();
5351
5352 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5353 {
5354 int temp;
5355
5356 input_line_pointer += 3;
5357 temp = get_absolute_expression ();
5358 if (temp < 0 || temp > 7)
5359 as_bad (_("bad coprocessor id"));
5360 else
5361 m68k_float_copnum = COP0 + temp;
5362 }
5363 else
5364 {
5365 as_bad (_("unrecognized fopt option"));
5366 ignore_rest_of_line ();
5367 return;
5368 }
5369
5370 demand_empty_rest_of_line ();
5371}
5372
5373/* The structure used to handle the MRI OPT pseudo-op. */
5374
5375struct opt_action
5376{
5377 /* The name of the option. */
5378 const char *name;
5379
5380 /* If this is not NULL, just call this function. The first argument
5381 is the ARG field of this structure, the second argument is
5382 whether the option was negated. */
31302357 5383 void (*pfn) (int arg, int on);
252b5132
RH		 5384
5385 /* If this is not NULL, and the PFN field is NULL, set the variable
5386 this points to. Set it to the ARG field if the option was not
5387 negated, and the NOTARG field otherwise. */
5388 int *pvar;
5389
5390 /* The value to pass to PFN or to assign to *PVAR. */
5391 int arg;
5392
5393 /* The value to assign to *PVAR if the option is negated. If PFN is
5394 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5395 the option may not be negated. */
5396 int notarg;
5397};
5398
5399/* The table used to handle the MRI OPT pseudo-op. */
5400
31302357
AS		 5401static void skip_to_comma (int, int);
5402static void opt_nest (int, int);
5403static void opt_chip (int, int);
5404static void opt_list (int, int);
5405static void opt_list_symbols (int, int);
252b5132
RH		 5406
5407static const struct opt_action opt_table[] =
5408{
5409 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5410
5411 /* We do relaxing, so there is little use for these options. */
5412 { "b", 0, 0, 0, 0 },
5413 { "brs", 0, 0, 0, 0 },
5414 { "brb", 0, 0, 0, 0 },
5415 { "brl", 0, 0, 0, 0 },
5416 { "brw", 0, 0, 0, 0 },
5417
5418 { "c", 0, 0, 0, 0 },
5419 { "cex", 0, 0, 0, 0 },
5420 { "case", 0, &symbols_case_sensitive, 1, 0 },
5421 { "cl", 0, 0, 0, 0 },
5422 { "cre", 0, 0, 0, 0 },
5423 { "d", 0, &flag_keep_locals, 1, 0 },
5424 { "e", 0, 0, 0, 0 },
5425 { "f", 0, &flag_short_refs, 1, 0 },
5426 { "frs", 0, &flag_short_refs, 1, 0 },
5427 { "frl", 0, &flag_short_refs, 0, 1 },
5428 { "g", 0, 0, 0, 0 },
5429 { "i", 0, 0, 0, 0 },
5430 { "m", 0, 0, 0, 0 },
5431 { "mex", 0, 0, 0, 0 },
5432 { "mc", 0, 0, 0, 0 },
5433 { "md", 0, 0, 0, 0 },
5434 { "nest", opt_nest, 0, 0, 0 },
5435 { "next", skip_to_comma, 0, 0, 0 },
5436 { "o", 0, 0, 0, 0 },
5437 { "old", 0, 0, 0, 0 },
5438 { "op", skip_to_comma, 0, 0, 0 },
5439 { "pco", 0, 0, 0, 0 },
5440 { "p", opt_chip, 0, 0, 0 },
5441 { "pcr", 0, 0, 0, 0 },
5442 { "pcs", 0, 0, 0, 0 },
5443 { "r", 0, 0, 0, 0 },
5444 { "quick", 0, &m68k_quick, 1, 0 },
5445 { "rel32", 0, &m68k_rel32, 1, 0 },
5446 { "s", opt_list, 0, 0, 0 },
5447 { "t", opt_list_symbols, 0, 0, 0 },
5448 { "w", 0, &flag_no_warnings, 0, 1 },
5449 { "x", 0, 0, 0, 0 }
5450};
5451
8fce3f5e 5452#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5453
5454/* The MRI OPT pseudo-op. */
5455
5456static void
31302357 5457s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5458{
5459 do
5460 {
5461 int t;
5462 char *s;
5463 char c;
5464 int i;
5465 const struct opt_action *o;
5466
5467 SKIP_WHITESPACE ();
5468
5469 t = 1;
5470 if (*input_line_pointer == '-')
5471 {
5472 ++input_line_pointer;
5473 t = 0;
5474 }
5475 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5476 {
5477 input_line_pointer += 2;
5478 t = 0;
5479 }
5480
5481 s = input_line_pointer;
5482 c = get_symbol_end ();
5483
5484 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5485 {
5486 if (strcasecmp (s, o->name) == 0)
5487 {
5488 if (o->pfn)
5489 {
5490 /* Restore input_line_pointer now in case the option
5491 takes arguments. */
5492 *input_line_pointer = c;
5493 (*o->pfn) (o->arg, t);
5494 }
5495 else if (o->pvar != NULL)
5496 {
5497 if (! t && o->arg == o->notarg)
5498 as_bad (_("option `%s' may not be negated"), s);
5499 *input_line_pointer = c;
5500 *o->pvar = t ? o->arg : o->notarg;
5501 }
5502 else
5503 *input_line_pointer = c;
5504 break;
5505 }
5506 }
5507 if (i >= OPTCOUNT)
5508 {
5509 as_bad (_("option `%s' not recognized"), s);
5510 *input_line_pointer = c;
5511 }
5512 }
5513 while (*input_line_pointer++ == ',');
5514
5515 /* Move back to terminating character. */
5516 --input_line_pointer;
5517 demand_empty_rest_of_line ();
5518}
5519
5520/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5521 not support and which take arguments. */
252b5132
RH		 5522
5523static void
31302357 5524skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5525{
5526 while (*input_line_pointer != ','
5527 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5528 ++input_line_pointer;
5529}
5530
5531/* Handle the OPT NEST=depth option. */
5532
5533static void
31302357 5534opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5535{
5536 if (*input_line_pointer != '=')
5537 {
5538 as_bad (_("bad format of OPT NEST=depth"));
5539 return;
5540 }
5541
5542 ++input_line_pointer;
5543 max_macro_nest = get_absolute_expression ();
5544}
5545
5546/* Handle the OPT P=chip option. */
5547
5548static void
31302357 5549opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5550{
5551 if (*input_line_pointer != '=')
5552 {
5553 /* This is just OPT P, which we do not support. */
5554 return;
5555 }
5556
5557 ++input_line_pointer;
5558 mri_chip ();
5559}
5560
5561/* Handle the OPT S option. */
5562
5563static void
31302357 5564opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5565{
5566 listing_list (on);
5567}
5568
5569/* Handle the OPT T option. */
5570
5571static void
31302357 5572opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5573{
5574 if (on)
5575 listing |= LISTING_SYMBOLS;
5576 else
8a104df9 5577 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5578}
5579
5580/* Handle the MRI REG pseudo-op. */
5581
5582static void
31302357 5583s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5584{
5585 char *s;
5586 int c;
5587 struct m68k_op rop;
5588 int mask;
5589 char *stop = NULL;
5590 char stopc;
5591
5592 if (line_label == NULL)
5593 {
5594 as_bad (_("missing label"));
5595 ignore_rest_of_line ();
5596 return;
5597 }
5598
5599 if (flag_mri)
5600 stop = mri_comment_field (&stopc);
5601
5602 SKIP_WHITESPACE ();
5603
5604 s = input_line_pointer;
3882b010 5605 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5606#ifdef REGISTER_PREFIX
5607 || *input_line_pointer == REGISTER_PREFIX
5608#endif
5609 || *input_line_pointer == '/'
5610 || *input_line_pointer == '-')
5611 ++input_line_pointer;
5612 c = *input_line_pointer;
5613 *input_line_pointer = '\0';
5614
5615 if (m68k_ip_op (s, &rop) != 0)
5616 {
5617 if (rop.error == NULL)
5618 as_bad (_("bad register list"));
5619 else
5620 as_bad (_("bad register list: %s"), rop.error);
5621 *input_line_pointer = c;
5622 ignore_rest_of_line ();
5623 return;
5624 }
5625
5626 *input_line_pointer = c;
5627
5628 if (rop.mode == REGLST)
5629 mask = rop.mask;
5630 else if (rop.mode == DREG)
5631 mask = 1 << (rop.reg - DATA0);
5632 else if (rop.mode == AREG)
5633 mask = 1 << (rop.reg - ADDR0 + 8);
5634 else if (rop.mode == FPREG)
5635 mask = 1 << (rop.reg - FP0 + 16);
5636 else if (rop.mode == CONTROL
5637 && rop.reg == FPI)
5638 mask = 1 << 24;
5639 else if (rop.mode == CONTROL
5640 && rop.reg == FPS)
5641 mask = 1 << 25;
5642 else if (rop.mode == CONTROL
5643 && rop.reg == FPC)
5644 mask = 1 << 26;
5645 else
5646 {
5647 as_bad (_("bad register list"));
5648 ignore_rest_of_line ();
5649 return;
5650 }
5651
5652 S_SET_SEGMENT (line_label, reg_section);
5653 S_SET_VALUE (line_label, ~mask);
49309057 5654 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5655
5656 if (flag_mri)
5657 mri_comment_end (stop, stopc);
5658
5659 demand_empty_rest_of_line ();
5660}
5661
5662/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5663
5664struct save_opts
5665{
5666 struct save_opts *next;
5667 int abspcadd;
5668 int symbols_case_sensitive;
5669 int keep_locals;
5670 int short_refs;
5671 int architecture;
6b6e92f4 5672 int chip;
252b5132
RH		 5673 int quick;
5674 int rel32;
5675 int listing;
5676 int no_warnings;
5677 /* FIXME: We don't save OPT S. */
5678};
5679
5680/* This variable holds the stack of saved options. */
5681
5682static struct save_opts *save_stack;
5683
5684/* The MRI SAVE pseudo-op. */
5685
5686static void
31302357 5687s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5688{
5689 struct save_opts *s;
5690
5691 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5692 s->abspcadd = m68k_abspcadd;
5693 s->symbols_case_sensitive = symbols_case_sensitive;
5694 s->keep_locals = flag_keep_locals;
5695 s->short_refs = flag_short_refs;
5696 s->architecture = current_architecture;
6b6e92f4 5697 s->chip = current_chip;
252b5132
RH		 5698 s->quick = m68k_quick;
5699 s->rel32 = m68k_rel32;
5700 s->listing = listing;
5701 s->no_warnings = flag_no_warnings;
5702
5703 s->next = save_stack;
5704 save_stack = s;
5705
5706 demand_empty_rest_of_line ();
5707}
5708
5709/* The MRI RESTORE pseudo-op. */
5710
5711static void
31302357 5712s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5713{
5714 struct save_opts *s;
5715
5716 if (save_stack == NULL)
5717 {
5718 as_bad (_("restore without save"));
5719 ignore_rest_of_line ();
5720 return;
5721 }
5722
5723 s = save_stack;
5724 save_stack = s->next;
5725
5726 m68k_abspcadd = s->abspcadd;
5727 symbols_case_sensitive = s->symbols_case_sensitive;
5728 flag_keep_locals = s->keep_locals;
5729 flag_short_refs = s->short_refs;
5730 current_architecture = s->architecture;
6b6e92f4 5731 current_chip = s->chip;
252b5132
RH		 5732 m68k_quick = s->quick;
5733 m68k_rel32 = s->rel32;
5734 listing = s->listing;
5735 flag_no_warnings = s->no_warnings;
5736
5737 free (s);
5738
5739 demand_empty_rest_of_line ();
5740}
5741
5742/* Types of MRI structured control directives. */
5743
5744enum mri_control_type
5745{
5746 mri_for,
5747 mri_if,
5748 mri_repeat,
5749 mri_while
5750};
5751
5752/* This structure is used to stack the MRI structured control
5753 directives. */
5754
5755struct mri_control_info
5756{
5757 /* The directive within which this one is enclosed. */
5758 struct mri_control_info *outer;
5759
5760 /* The type of directive. */
5761 enum mri_control_type type;
5762
5763 /* Whether an ELSE has been in an IF. */
5764 int else_seen;
5765
5766 /* The add or sub statement at the end of a FOR. */
5767 char *incr;
5768
5769 /* The label of the top of a FOR or REPEAT loop. */
5770 char *top;
5771
5772 /* The label to jump to for the next iteration, or the else
5773 expression of a conditional. */
5774 char *next;
5775
5776 /* The label to jump to to break out of the loop, or the label past
5777 the end of a conditional. */
5778 char *bottom;
5779};
5780
5781/* The stack of MRI structured control directives. */
5782
5783static struct mri_control_info *mri_control_stack;
5784
5785/* The current MRI structured control directive index number, used to
5786 generate label names. */
5787
5788static int mri_control_index;
5789
252b5132
RH		 5790/* Assemble an instruction for an MRI structured control directive. */
5791
5792static void
31302357 5793mri_assemble (char *str)
252b5132
RH		 5794{
5795 char *s;
5796
5797 /* md_assemble expects the opcode to be in lower case. */
5798 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5799 *s = TOLOWER (*s);
252b5132
RH		 5800
5801 md_assemble (str);
5802}
5803
5804/* Generate a new MRI label structured control directive label name. */
5805
5806static char *
31302357 5807mri_control_label (void)
252b5132
RH		 5808{
5809 char *n;
5810
5811 n = (char *) xmalloc (20);
5812 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5813 ++mri_control_index;
5814 return n;
5815}
5816
5817/* Create a new MRI structured control directive. */
5818
5819static struct mri_control_info *
31302357 5820push_mri_control (enum mri_control_type type)
252b5132
RH		 5821{
5822 struct mri_control_info *n;
5823
5824 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5825
5826 n->type = type;
5827 n->else_seen = 0;
5828 if (type == mri_if || type == mri_while)
5829 n->top = NULL;
5830 else
5831 n->top = mri_control_label ();
5832 n->next = mri_control_label ();
5833 n->bottom = mri_control_label ();
5834
5835 n->outer = mri_control_stack;
5836 mri_control_stack = n;
5837
5838 return n;
5839}
5840
5841/* Pop off the stack of MRI structured control directives. */
5842
5843static void
31302357 5844pop_mri_control (void)
252b5132
RH		 5845{
5846 struct mri_control_info *n;
5847
5848 n = mri_control_stack;
5849 mri_control_stack = n->outer;
5850 if (n->top != NULL)
5851 free (n->top);
5852 free (n->next);
5853 free (n->bottom);
5854 free (n);
5855}
5856
5857/* Recognize a condition code in an MRI structured control expression. */
5858
5859static int
31302357 5860parse_mri_condition (int *pcc)
252b5132
RH		 5861{
5862 char c1, c2;
5863
5864 know (*input_line_pointer == '<');
5865
5866 ++input_line_pointer;
5867 c1 = *input_line_pointer++;
5868 c2 = *input_line_pointer++;
5869
5870 if (*input_line_pointer != '>')
5871 {
5872 as_bad (_("syntax error in structured control directive"));
5873 return 0;
5874 }
5875
5876 ++input_line_pointer;
5877 SKIP_WHITESPACE ();
5878
3882b010
L		 5879 c1 = TOLOWER (c1);
5880 c2 = TOLOWER (c2);
252b5132
RH		 5881
5882 *pcc = (c1 << 8) | c2;
5883
5884 return 1;
5885}
5886
5887/* Parse a single operand in an MRI structured control expression. */
5888
5889static int
31302357
AS		 5890parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5891 char **rightstart, char **rightstop)
252b5132
RH		 5892{
5893 char *s;
5894
5895 SKIP_WHITESPACE ();
5896
5897 *pcc = -1;
5898 *leftstart = NULL;
5899 *leftstop = NULL;
5900 *rightstart = NULL;
5901 *rightstop = NULL;
5902
5903 if (*input_line_pointer == '<')
5904 {
5905 /* It's just a condition code. */
5906 return parse_mri_condition (pcc);
5907 }
5908
5909 /* Look ahead for the condition code. */
5910 for (s = input_line_pointer; *s != '\0'; ++s)
5911 {
5912 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5913 break;
5914 }
5915 if (*s == '\0')
5916 {
5917 as_bad (_("missing condition code in structured control directive"));
5918 return 0;
5919 }
5920
5921 *leftstart = input_line_pointer;
5922 *leftstop = s;
5923 if (*leftstop > *leftstart
5924 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5925 --*leftstop;
5926
5927 input_line_pointer = s;
5928 if (! parse_mri_condition (pcc))
5929 return 0;
5930
5931 /* Look ahead for AND or OR or end of line. */
5932 for (s = input_line_pointer; *s != '\0'; ++s)
5933 {
e1f44d10
NC		 5934 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5935 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5936 ^^^ ^^ */
8a104df9
KH		 5937 if ((s == input_line_pointer
5938 || *(s-1) == ' '
5939 || *(s-1) == '\t')
5940 && ((strncasecmp (s, "AND", 3) == 0
5941 && (s[3] == '.' || ! is_part_of_name (s[3])))
5942 || (strncasecmp (s, "OR", 2) == 0
5943 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5944 break;
252b5132
RH		 5945 }
5946
5947 *rightstart = input_line_pointer;
5948 *rightstop = s;
5949 if (*rightstop > *rightstart
5950 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5951 --*rightstop;
5952
5953 input_line_pointer = s;
5954
5955 return 1;
5956}
5957
5958#define MCC(b1, b2) (((b1) << 8) | (b2))
5959
5960/* Swap the sense of a condition. This changes the condition so that
5961 it generates the same result when the operands are swapped. */
5962
5963static int
31302357 5964swap_mri_condition (int cc)
252b5132
RH		 5965{
5966 switch (cc)
5967 {
5968 case MCC ('h', 'i'): return MCC ('c', 's');
5969 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 5970 /* <HS> is an alias for <CC>. */
e1f44d10 5971 case MCC ('h', 's'):
252b5132 5972 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 5973 /* <LO> is an alias for <CS>. */
e1f44d10 5974 case MCC ('l', 'o'):
252b5132
RH		 5975 case MCC ('c', 's'): return MCC ('h', 'i');
5976 case MCC ('p', 'l'): return MCC ('m', 'i');
5977 case MCC ('m', 'i'): return MCC ('p', 'l');
5978 case MCC ('g', 'e'): return MCC ('l', 'e');
5979 case MCC ('l', 't'): return MCC ('g', 't');
5980 case MCC ('g', 't'): return MCC ('l', 't');
5981 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 5982 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 5983 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5984 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5985 case MCC ('v', 'c'):
5986 case MCC ('v', 's'):
5987 default :
5988 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5989 (char) (cc >> 8), (char) (cc));
5990 break;
252b5132
RH		 5991 }
5992 return cc;
5993}
5994
5995/* Reverse the sense of a condition. */
5996
5997static int
31302357 5998reverse_mri_condition (int cc)
252b5132
RH		 5999{
6000 switch (cc)
6001 {
6002 case MCC ('h', 'i'): return MCC ('l', 's');
6003 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6004 /* <HS> is an alias for <CC> */
6005 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6006 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6007 /* <LO> is an alias for <CS> */
6008 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6009 case MCC ('c', 's'): return MCC ('c', 'c');
6010 case MCC ('n', 'e'): return MCC ('e', 'q');
6011 case MCC ('e', 'q'): return MCC ('n', 'e');
6012 case MCC ('v', 'c'): return MCC ('v', 's');
6013 case MCC ('v', 's'): return MCC ('v', 'c');
6014 case MCC ('p', 'l'): return MCC ('m', 'i');
6015 case MCC ('m', 'i'): return MCC ('p', 'l');
6016 case MCC ('g', 'e'): return MCC ('l', 't');
6017 case MCC ('l', 't'): return MCC ('g', 'e');
6018 case MCC ('g', 't'): return MCC ('l', 'e');
6019 case MCC ('l', 'e'): return MCC ('g', 't');
6020 }
6021 return cc;
6022}
6023
6024/* Build an MRI structured control expression. This generates test
6025 and branch instructions. It goes to TRUELAB if the condition is
6026 true, and to FALSELAB if the condition is false. Exactly one of
6027 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6028 is the size qualifier for the expression. EXTENT is the size to
6029 use for the branch. */
6030
6031static void
31302357
AS		 6032build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6033 char *rightstart, char *rightstop,
6034 const char *truelab, const char *falselab,
6035 int extent)
252b5132
RH		 6036{
6037 char *buf;
6038 char *s;
6039
6040 if (leftstart != NULL)
6041 {
6042 struct m68k_op leftop, rightop;
6043 char c;
6044
6045 /* Swap the compare operands, if necessary, to produce a legal
6046 m68k compare instruction. Comparing a register operand with
6047 a non-register operand requires the register to be on the
6048 right (cmp, cmpa). Comparing an immediate value with
6049 anything requires the immediate value to be on the left
6050 (cmpi). */
6051
6052 c = *leftstop;
6053 *leftstop = '\0';
6054 (void) m68k_ip_op (leftstart, &leftop);
6055 *leftstop = c;
6056
6057 c = *rightstop;
6058 *rightstop = '\0';
6059 (void) m68k_ip_op (rightstart, &rightop);
6060 *rightstop = c;
6061
6062 if (rightop.mode == IMMED
6063 || ((leftop.mode == DREG || leftop.mode == AREG)
6064 && (rightop.mode != DREG && rightop.mode != AREG)))
6065 {
6066 char *temp;
6067
31302357
AS		 6068 /* Correct conditional handling:
6069 if #1 <lt> d0 then ;means if (1 < d0)
6070 ...
6071 endi
e1f44d10 6072
31302357 6073 should assemble to:
e1f44d10 6074
31302357
AS		 6075 cmp #1,d0 if we do *not* swap the operands
6076 bgt true we need the swapped condition!
6077 ble false
6078 true:
6079 ...
6080 false:
6081 */
252b5132
RH		 6082 temp = leftstart;
6083 leftstart = rightstart;
6084 rightstart = temp;
6085 temp = leftstop;
6086 leftstop = rightstop;
6087 rightstop = temp;
8a104df9
KH		 6088 }
6089 else
6090 {
e1f44d10 6091 cc = swap_mri_condition (cc);
252b5132
RH		 6092 }
6093 }
6094
6095 if (truelab == NULL)
6096 {
6097 cc = reverse_mri_condition (cc);
6098 truelab = falselab;
6099 }
92774660 6100
252b5132
RH		 6101 if (leftstart != NULL)
6102 {
6103 buf = (char *) xmalloc (20
6104 + (leftstop - leftstart)
6105 + (rightstop - rightstart));
6106 s = buf;
6107 *s++ = 'c';
6108 *s++ = 'm';
6109 *s++ = 'p';
6110 if (qual != '\0')
3882b010 6111 *s++ = TOLOWER (qual);
252b5132
RH		 6112 *s++ = ' ';
6113 memcpy (s, leftstart, leftstop - leftstart);
6114 s += leftstop - leftstart;
6115 *s++ = ',';
6116 memcpy (s, rightstart, rightstop - rightstart);
6117 s += rightstop - rightstart;
6118 *s = '\0';
6119 mri_assemble (buf);
6120 free (buf);
6121 }
92774660 6122
252b5132
RH		 6123 buf = (char *) xmalloc (20 + strlen (truelab));
6124 s = buf;
6125 *s++ = 'b';
6126 *s++ = cc >> 8;
6127 *s++ = cc & 0xff;
6128 if (extent != '\0')
3882b010 6129 *s++ = TOLOWER (extent);
252b5132
RH		 6130 *s++ = ' ';
6131 strcpy (s, truelab);
6132 mri_assemble (buf);
6133 free (buf);
6134}
6135
6136/* Parse an MRI structured control expression. This generates test
6137 and branch instructions. STOP is where the expression ends. It
6138 goes to TRUELAB if the condition is true, and to FALSELAB if the
6139 condition is false. Exactly one of TRUELAB and FALSELAB will be
6140 NULL, meaning to fall through. QUAL is the size qualifier for the
6141 expression. EXTENT is the size to use for the branch. */
6142
6143static void
31302357
AS		 6144parse_mri_control_expression (char *stop, int qual, const char *truelab,
6145 const char *falselab, int extent)
252b5132
RH		 6146{
6147 int c;
6148 int cc;
6149 char *leftstart;
6150 char *leftstop;
6151 char *rightstart;
6152 char *rightstop;
6153
6154 c = *stop;
6155 *stop = '\0';
6156
6157 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6158 &rightstart, &rightstop))
6159 {
6160 *stop = c;
6161 return;
6162 }
6163
6164 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6165 {
6166 const char *flab;
6167
6168 if (falselab != NULL)
6169 flab = falselab;
6170 else
6171 flab = mri_control_label ();
6172
6173 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6174 rightstop, (const char *) NULL, flab, extent);
6175
6176 input_line_pointer += 3;
6177 if (*input_line_pointer != '.'
6178 || input_line_pointer[1] == '\0')
6179 qual = '\0';
6180 else
6181 {
6182 qual = input_line_pointer[1];
6183 input_line_pointer += 2;
6184 }
6185
6186 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6187 &rightstart, &rightstop))
6188 {
6189 *stop = c;
6190 return;
6191 }
6192
6193 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6194 rightstop, truelab, falselab, extent);
6195
6196 if (falselab == NULL)
6197 colon (flab);
6198 }
6199 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6200 {
6201 const char *tlab;
6202
6203 if (truelab != NULL)
6204 tlab = truelab;
6205 else
6206 tlab = mri_control_label ();
6207
6208 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6209 rightstop, tlab, (const char *) NULL, extent);
6210
6211 input_line_pointer += 2;
6212 if (*input_line_pointer != '.'
6213 || input_line_pointer[1] == '\0')
6214 qual = '\0';
6215 else
6216 {
6217 qual = input_line_pointer[1];
6218 input_line_pointer += 2;
6219 }
6220
6221 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6222 &rightstart, &rightstop))
6223 {
6224 *stop = c;
6225 return;
6226 }
6227
6228 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6229 rightstop, truelab, falselab, extent);
6230
6231 if (truelab == NULL)
6232 colon (tlab);
6233 }
6234 else
6235 {
6236 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6237 rightstop, truelab, falselab, extent);
6238 }
6239
6240 *stop = c;
6241 if (input_line_pointer != stop)
6242 as_bad (_("syntax error in structured control directive"));
6243}
6244
6245/* Handle the MRI IF pseudo-op. This may be a structured control
6246 directive, or it may be a regular assembler conditional, depending
6247 on its operands. */
6248
6249static void
31302357 6250s_mri_if (int qual)
252b5132
RH		 6251{
6252 char *s;
6253 int c;
6254 struct mri_control_info *n;
6255
6256 /* A structured control directive must end with THEN with an
6257 optional qualifier. */
6258 s = input_line_pointer;
e1f44d10
NC		 6259 /* We only accept '*' as introduction of comments if preceded by white space
6260 or at first column of a line (I think this can't actually happen here?)
6261 This is important when assembling:
6262 if d0 <ne> 12(a0,d0*2) then
36759679 6263 if d0 <ne> #CONST*20 then. */
31302357
AS		 6264 while (! (is_end_of_line[(unsigned char) *s]
6265 || (flag_mri
6266 && *s == '*'
6267 && (s == input_line_pointer
6268 || *(s-1) == ' '
6269 || *(s-1) == '\t'))))
252b5132
RH		 6270 ++s;
6271 --s;
6272 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6273 --s;
6274
6275 if (s - input_line_pointer > 1
6276 && s[-1] == '.')
6277 s -= 2;
6278
6279 if (s - input_line_pointer < 3
6280 || strncasecmp (s - 3, "THEN", 4) != 0)
6281 {
6282 if (qual != '\0')
6283 {
6284 as_bad (_("missing then"));
6285 ignore_rest_of_line ();
6286 return;
6287 }
6288
6289 /* It's a conditional. */
6290 s_if (O_ne);
6291 return;
6292 }
6293
6294 /* Since this might be a conditional if, this pseudo-op will be
6295 called even if we are supported to be ignoring input. Double
6296 check now. Clobber *input_line_pointer so that ignore_input
6297 thinks that this is not a special pseudo-op. */
6298 c = *input_line_pointer;
6299 *input_line_pointer = 0;
6300 if (ignore_input ())
6301 {
6302 *input_line_pointer = c;
6303 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6304 ++input_line_pointer;
6305 demand_empty_rest_of_line ();
6306 return;
6307 }
6308 *input_line_pointer = c;
6309
6310 n = push_mri_control (mri_if);
6311
6312 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6313 n->next, s[1] == '.' ? s[2] : '\0');
6314
6315 if (s[1] == '.')
6316 input_line_pointer = s + 3;
6317 else
6318 input_line_pointer = s + 1;
6319
6320 if (flag_mri)
6321 {
6322 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6323 ++input_line_pointer;
6324 }
6325
6326 demand_empty_rest_of_line ();
6327}
6328
6329/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6330 structured IF, associate the ELSE with the IF. Otherwise, assume
6331 it is a conditional else. */
6332
6333static void
31302357 6334s_mri_else (int qual)
252b5132
RH		 6335{
6336 int c;
6337 char *buf;
6338 char q[2];
6339
6340 if (qual == '\0'
6341 && (mri_control_stack == NULL
6342 || mri_control_stack->type != mri_if
6343 || mri_control_stack->else_seen))
6344 {
6345 s_else (0);
6346 return;
6347 }
6348
6349 c = *input_line_pointer;
6350 *input_line_pointer = 0;
6351 if (ignore_input ())
6352 {
6353 *input_line_pointer = c;
6354 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6355 ++input_line_pointer;
6356 demand_empty_rest_of_line ();
6357 return;
6358 }
6359 *input_line_pointer = c;
6360
6361 if (mri_control_stack == NULL
6362 || mri_control_stack->type != mri_if
6363 || mri_control_stack->else_seen)
6364 {
6365 as_bad (_("else without matching if"));
6366 ignore_rest_of_line ();
6367 return;
6368 }
6369
6370 mri_control_stack->else_seen = 1;
6371
6372 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6373 q[0] = TOLOWER (qual);
252b5132
RH		 6374 q[1] = '\0';
6375 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6376 mri_assemble (buf);
6377 free (buf);
6378
6379 colon (mri_control_stack->next);
6380
6381 if (flag_mri)
6382 {
6383 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6384 ++input_line_pointer;
6385 }
6386
6387 demand_empty_rest_of_line ();
6388}
6389
6390/* Handle the MRI ENDI pseudo-op. */
6391
6392static void
31302357 6393s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6394{
6395 if (mri_control_stack == NULL
6396 || mri_control_stack->type != mri_if)
6397 {
6398 as_bad (_("endi without matching if"));
6399 ignore_rest_of_line ();
6400 return;
6401 }
6402
6403 /* ignore_input will not return true for ENDI, so we don't need to
6404 worry about checking it again here. */
6405
6406 if (! mri_control_stack->else_seen)
6407 colon (mri_control_stack->next);
6408 colon (mri_control_stack->bottom);
6409
6410 pop_mri_control ();
6411
6412 if (flag_mri)
6413 {
6414 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6415 ++input_line_pointer;
6416 }
6417
6418 demand_empty_rest_of_line ();
6419}
6420
6421/* Handle the MRI BREAK pseudo-op. */
6422
6423static void
31302357 6424s_mri_break (int extent)
252b5132
RH		 6425{
6426 struct mri_control_info *n;
6427 char *buf;
6428 char ex[2];
6429
6430 n = mri_control_stack;
6431 while (n != NULL
6432 && n->type != mri_for
6433 && n->type != mri_repeat
6434 && n->type != mri_while)
6435 n = n->outer;
6436 if (n == NULL)
6437 {
6438 as_bad (_("break outside of structured loop"));
6439 ignore_rest_of_line ();
6440 return;
6441 }
6442
6443 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6444 ex[0] = TOLOWER (extent);
252b5132
RH		 6445 ex[1] = '\0';
6446 sprintf (buf, "bra%s %s", ex, n->bottom);
6447 mri_assemble (buf);
6448 free (buf);
6449
6450 if (flag_mri)
6451 {
6452 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6453 ++input_line_pointer;
6454 }
6455
6456 demand_empty_rest_of_line ();
6457}
6458
6459/* Handle the MRI NEXT pseudo-op. */
6460
6461static void
31302357 6462s_mri_next (int extent)
252b5132
RH		 6463{
6464 struct mri_control_info *n;
6465 char *buf;
6466 char ex[2];
6467
6468 n = mri_control_stack;
6469 while (n != NULL
6470 && n->type != mri_for
6471 && n->type != mri_repeat
6472 && n->type != mri_while)
6473 n = n->outer;
6474 if (n == NULL)
6475 {
6476 as_bad (_("next outside of structured loop"));
6477 ignore_rest_of_line ();
6478 return;
6479 }
6480
6481 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6482 ex[0] = TOLOWER (extent);
252b5132
RH		 6483 ex[1] = '\0';
6484 sprintf (buf, "bra%s %s", ex, n->next);
6485 mri_assemble (buf);
6486 free (buf);
6487
6488 if (flag_mri)
6489 {
6490 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6491 ++input_line_pointer;
6492 }
6493
6494 demand_empty_rest_of_line ();
6495}
6496
6497/* Handle the MRI FOR pseudo-op. */
6498
6499static void
31302357 6500s_mri_for (int qual)
252b5132
RH		 6501{
6502 const char *varstart, *varstop;
6503 const char *initstart, *initstop;
6504 const char *endstart, *endstop;
6505 const char *bystart, *bystop;
6506 int up;
6507 int by;
6508 int extent;
6509 struct mri_control_info *n;
6510 char *buf;
6511 char *s;
6512 char ex[2];
6513
6514 /* The syntax is
6515 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6516 */
6517
6518 SKIP_WHITESPACE ();
6519 varstart = input_line_pointer;
6520
6521 /* Look for the '='. */
6522 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6523 && *input_line_pointer != '=')
6524 ++input_line_pointer;
6525 if (*input_line_pointer != '=')
6526 {
6527 as_bad (_("missing ="));
6528 ignore_rest_of_line ();
6529 return;
6530 }
6531
6532 varstop = input_line_pointer;
6533 if (varstop > varstart
6534 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6535 --varstop;
6536
6537 ++input_line_pointer;
6538
6539 initstart = input_line_pointer;
6540
6541 /* Look for TO or DOWNTO. */
6542 up = 1;
6543 initstop = NULL;
6544 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6545 {
6546 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6547 && ! is_part_of_name (input_line_pointer[2]))
6548 {
6549 initstop = input_line_pointer;
6550 input_line_pointer += 2;
6551 break;
6552 }
6553 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6554 && ! is_part_of_name (input_line_pointer[6]))
6555 {
6556 initstop = input_line_pointer;
6557 up = 0;
6558 input_line_pointer += 6;
6559 break;
6560 }
6561 ++input_line_pointer;
6562 }
6563 if (initstop == NULL)
6564 {
6565 as_bad (_("missing to or downto"));
6566 ignore_rest_of_line ();
6567 return;
6568 }
6569 if (initstop > initstart
6570 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6571 --initstop;
6572
6573 SKIP_WHITESPACE ();
6574 endstart = input_line_pointer;
6575
6576 /* Look for BY or DO. */
6577 by = 0;
6578 endstop = NULL;
6579 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6580 {
6581 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6582 && ! is_part_of_name (input_line_pointer[2]))
6583 {
6584 endstop = input_line_pointer;
6585 by = 1;
6586 input_line_pointer += 2;
6587 break;
6588 }
6589 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6590 && (input_line_pointer[2] == '.'
6591 || ! is_part_of_name (input_line_pointer[2])))
6592 {
6593 endstop = input_line_pointer;
6594 input_line_pointer += 2;
6595 break;
6596 }
6597 ++input_line_pointer;
6598 }
6599 if (endstop == NULL)
6600 {
6601 as_bad (_("missing do"));
6602 ignore_rest_of_line ();
6603 return;
6604 }
6605 if (endstop > endstart
6606 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6607 --endstop;
6608
6609 if (! by)
6610 {
6611 bystart = "#1";
6612 bystop = bystart + 2;
6613 }
6614 else
6615 {
6616 SKIP_WHITESPACE ();
6617 bystart = input_line_pointer;
6618
6619 /* Look for DO. */
6620 bystop = NULL;
6621 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6622 {
6623 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6624 && (input_line_pointer[2] == '.'
6625 || ! is_part_of_name (input_line_pointer[2])))
6626 {
6627 bystop = input_line_pointer;
6628 input_line_pointer += 2;
6629 break;
6630 }
6631 ++input_line_pointer;
6632 }
6633 if (bystop == NULL)
6634 {
6635 as_bad (_("missing do"));
6636 ignore_rest_of_line ();
6637 return;
6638 }
6639 if (bystop > bystart
6640 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6641 --bystop;
6642 }
6643
6644 if (*input_line_pointer != '.')
6645 extent = '\0';
6646 else
6647 {
6648 extent = input_line_pointer[1];
6649 input_line_pointer += 2;
6650 }
6651
6652 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6653 n = push_mri_control (mri_for);
6654
6655 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6656
36759679 6657 /* Move init,var. */
252b5132
RH		 6658 s = buf;
6659 *s++ = 'm';
6660 *s++ = 'o';
6661 *s++ = 'v';
6662 *s++ = 'e';
6663 if (qual != '\0')
3882b010 6664 *s++ = TOLOWER (qual);
252b5132
RH		 6665 *s++ = ' ';
6666 memcpy (s, initstart, initstop - initstart);
6667 s += initstop - initstart;
6668 *s++ = ',';
6669 memcpy (s, varstart, varstop - varstart);
6670 s += varstop - varstart;
6671 *s = '\0';
6672 mri_assemble (buf);
6673
6674 colon (n->top);
6675
36759679 6676 /* cmp end,var. */
252b5132
RH		 6677 s = buf;
6678 *s++ = 'c';
6679 *s++ = 'm';
6680 *s++ = 'p';
6681 if (qual != '\0')
3882b010 6682 *s++ = TOLOWER (qual);
252b5132
RH		 6683 *s++ = ' ';
6684 memcpy (s, endstart, endstop - endstart);
6685 s += endstop - endstart;
6686 *s++ = ',';
6687 memcpy (s, varstart, varstop - varstart);
6688 s += varstop - varstart;
6689 *s = '\0';
6690 mri_assemble (buf);
6691
36759679 6692 /* bcc bottom. */
3882b010 6693 ex[0] = TOLOWER (extent);
252b5132
RH		 6694 ex[1] = '\0';
6695 if (up)
6696 sprintf (buf, "blt%s %s", ex, n->bottom);
6697 else
6698 sprintf (buf, "bgt%s %s", ex, n->bottom);
6699 mri_assemble (buf);
6700
6701 /* Put together the add or sub instruction used by ENDF. */
6702 s = buf;
6703 if (up)
6704 strcpy (s, "add");
6705 else
6706 strcpy (s, "sub");
6707 s += 3;
6708 if (qual != '\0')
3882b010 6709 *s++ = TOLOWER (qual);
252b5132
RH		 6710 *s++ = ' ';
6711 memcpy (s, bystart, bystop - bystart);
6712 s += bystop - bystart;
6713 *s++ = ',';
6714 memcpy (s, varstart, varstop - varstart);
6715 s += varstop - varstart;
6716 *s = '\0';
6717 n->incr = buf;
6718
6719 if (flag_mri)
6720 {
6721 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6722 ++input_line_pointer;
6723 }
6724
6725 demand_empty_rest_of_line ();
6726}
6727
6728/* Handle the MRI ENDF pseudo-op. */
6729
6730static void
31302357 6731s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6732{
6733 if (mri_control_stack == NULL
6734 || mri_control_stack->type != mri_for)
6735 {
6736 as_bad (_("endf without for"));
6737 ignore_rest_of_line ();
6738 return;
6739 }
6740
6741 colon (mri_control_stack->next);
6742
6743 mri_assemble (mri_control_stack->incr);
6744
6745 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6746 mri_assemble (mri_control_stack->incr);
6747
6748 free (mri_control_stack->incr);
6749
6750 colon (mri_control_stack->bottom);
6751
6752 pop_mri_control ();
6753
6754 if (flag_mri)
6755 {
6756 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6757 ++input_line_pointer;
6758 }
6759
6760 demand_empty_rest_of_line ();
6761}
6762
6763/* Handle the MRI REPEAT pseudo-op. */
6764
6765static void
31302357 6766s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6767{
6768 struct mri_control_info *n;
6769
6770 n = push_mri_control (mri_repeat);
6771 colon (n->top);
6772 if (flag_mri)
6773 {
6774 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6775 ++input_line_pointer;
6776 }
6777 demand_empty_rest_of_line ();
6778}
6779
6780/* Handle the MRI UNTIL pseudo-op. */
6781
6782static void
31302357 6783s_mri_until (int qual)
252b5132
RH		 6784{
6785 char *s;
6786
6787 if (mri_control_stack == NULL
6788 || mri_control_stack->type != mri_repeat)
6789 {
6790 as_bad (_("until without repeat"));
6791 ignore_rest_of_line ();
6792 return;
6793 }
6794
6795 colon (mri_control_stack->next);
6796
6797 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6798 ;
6799
6800 parse_mri_control_expression (s, qual, (const char *) NULL,
6801 mri_control_stack->top, '\0');
6802
6803 colon (mri_control_stack->bottom);
6804
6805 input_line_pointer = s;
6806
6807 pop_mri_control ();
6808
6809 if (flag_mri)
6810 {
6811 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6812 ++input_line_pointer;
6813 }
6814
6815 demand_empty_rest_of_line ();
6816}
6817
6818/* Handle the MRI WHILE pseudo-op. */
6819
6820static void
31302357 6821s_mri_while (int qual)
252b5132
RH		 6822{
6823 char *s;
6824
6825 struct mri_control_info *n;
6826
6827 s = input_line_pointer;
e1f44d10
NC		 6828 /* We only accept '*' as introduction of comments if preceded by white space
6829 or at first column of a line (I think this can't actually happen here?)
6830 This is important when assembling:
6831 while d0 <ne> 12(a0,d0*2) do
36759679 6832 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6833 while (! (is_end_of_line[(unsigned char) *s]
6834 || (flag_mri
6835 && *s == '*'
6836 && (s == input_line_pointer
6837 || *(s-1) == ' '
6838 || *(s-1) == '\t'))))
252b5132
RH		 6839 s++;
6840 --s;
6841 while (*s == ' ' || *s == '\t')
6842 --s;
6843 if (s - input_line_pointer > 1
6844 && s[-1] == '.')
6845 s -= 2;
6846 if (s - input_line_pointer < 2
6847 || strncasecmp (s - 1, "DO", 2) != 0)
6848 {
6849 as_bad (_("missing do"));
6850 ignore_rest_of_line ();
6851 return;
6852 }
6853
6854 n = push_mri_control (mri_while);
6855
6856 colon (n->next);
6857
6858 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6859 s[1] == '.' ? s[2] : '\0');
6860
6861 input_line_pointer = s + 1;
6862 if (*input_line_pointer == '.')
6863 input_line_pointer += 2;
6864
6865 if (flag_mri)
6866 {
6867 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6868 ++input_line_pointer;
6869 }
6870
6871 demand_empty_rest_of_line ();
6872}
6873
6874/* Handle the MRI ENDW pseudo-op. */
6875
6876static void
31302357 6877s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6878{
6879 char *buf;
6880
6881 if (mri_control_stack == NULL
6882 || mri_control_stack->type != mri_while)
6883 {
6884 as_bad (_("endw without while"));
6885 ignore_rest_of_line ();
6886 return;
6887 }
6888
6889 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6890 sprintf (buf, "bra %s", mri_control_stack->next);
6891 mri_assemble (buf);
6892 free (buf);
6893
6894 colon (mri_control_stack->bottom);
6895
6896 pop_mri_control ();
6897
6898 if (flag_mri)
6899 {
6900 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6901 ++input_line_pointer;
6902 }
6903
6904 demand_empty_rest_of_line ();
6905}
6906\f
31302357
AS		 6907/* md_parse_option
6908 Invocation line includes a switch not recognized by the base assembler.
6909 See if it's a processor-specific option. These are:
6910
6911 -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6912 -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6913 Select the architecture. Instructions or features not
6914 supported by the selected architecture cause fatal
6915 errors. More than one may be specified. The default is
6916 -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6917 for -m68000, and -m68882 is a synonym for -m68881.
6918 -[A]m[c]no-68851, -[A]m[c]no-68881
6919 Don't accept 688?1 instructions. (The "c" is kind of silly,
6920 so don't use or document it, but that's the way the parsing
6921 works).
6922
6923 -pic Indicates PIC.
6924 -k Indicates PIC. (Sun 3 only.)
6925 --pcrel
6926 Never turn PC-relative branches into absolute jumps.
6927 --bitwise-or
6928 Permit `|' to be used in expressions. */
252b5132
RH		 6929
6930#ifdef OBJ_ELF
5a38dc70 6931const char *md_shortopts = "lSA:m:kQ:V";
252b5132 6932#else
5a38dc70 6933const char *md_shortopts = "lSA:m:k";
252b5132
RH		 6934#endif
6935
6936struct option md_longopts[] = {
6937#define OPTION_PIC (OPTION_MD_BASE)
6938 {"pic", no_argument, NULL, OPTION_PIC},
6939#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6940 {"register-prefix-optional", no_argument, NULL,
6941 OPTION_REGISTER_PREFIX_OPTIONAL},
6942#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6943 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6944#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6945 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6946#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6947 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6948#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6949 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6950#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6951 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6952#define OPTION_PCREL (OPTION_MD_BASE + 7)
6953 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6954 {NULL, no_argument, NULL, 0}
6955};
bc805888 6956size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6957
6958int
31302357 6959md_parse_option (int c, char *arg)
252b5132
RH		 6960{
6961 switch (c)
6962 {
6963 case 'l': /* -l means keep external to 2 bit offset
36759679 6964 rather than 16 bit one. */
252b5132
RH		 6965 flag_short_refs = 1;
6966 break;
6967
6968 case 'S': /* -S means that jbsr's always turn into
6969 jsr's. */
6970 flag_long_jumps = 1;
6971 break;
6972
28e7409f
NC		 6973 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6974 branches into absolute jumps. */
6975 flag_keep_pcrel = 1;
6976 break;
6977
252b5132
RH		 6978 case 'A':
6979 if (*arg == 'm')
8a104df9 6980 arg++;
36759679 6981 /* Intentional fall-through. */
252b5132
RH		 6982 case 'm':
6983
6984 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6985 {
6986 int i;
6987 unsigned long arch;
252b5132
RH		 6988
6989 arg += 3;
6990 if (*arg == 'm')
6991 {
6992 arg++;
6993 if (arg[0] == 'c' && arg[1] == '6')
6994 arg++;
6995 }
6996 for (i = 0; i < n_archs; i++)
6997 if (!strcmp (arg, archs[i].name))
6998 break;
6999 if (i == n_archs)
329e276d
NC		 7000 return 0;
7001
252b5132
RH		 7002 arch = archs[i].arch;
7003 if (arch == m68881)
7004 no_68881 = 1;
7005 else if (arch == m68851)
7006 no_68851 = 1;
7007 else
329e276d 7008 return 0;
252b5132
RH		 7009 }
7010 else
7011 {
7012 int i;
7013
7014 if (arg[0] == 'c' && arg[1] == '6')
7015 arg++;
7016
7017 for (i = 0; i < n_archs; i++)
7018 if (!strcmp (arg, archs[i].name))
7019 {
7020 unsigned long arch = archs[i].arch;
329e276d 7021
252b5132
RH		 7022 if (cpu_of_arch (arch))
7023 /* It's a cpu spec. */
7024 {
7025 current_architecture &= ~m68000up;
7026 current_architecture |= arch;
990ae22a 7027 current_chip = archs[i].chip;
252b5132
RH		 7028 }
7029 else if (arch == m68881)
7030 {
7031 current_architecture |= m68881;
7032 no_68881 = 0;
7033 }
7034 else if (arch == m68851)
7035 {
7036 current_architecture |= m68851;
7037 no_68851 = 0;
7038 }
7039 else
7040 /* ??? */
7041 abort ();
7042 break;
7043 }
7044 if (i == n_archs)
7045 {
7046 as_bad (_("unrecognized architecture specification `%s'"), arg);
7047 return 0;
7048 }
7049 }
7050 break;
7051
7052 case OPTION_PIC:
7053 case 'k':
7054 flag_want_pic = 1;
36759679 7055 break; /* -pic, Position Independent Code. */
252b5132
RH		 7056
7057 case OPTION_REGISTER_PREFIX_OPTIONAL:
7058 flag_reg_prefix_optional = 1;
7059 reg_prefix_optional_seen = 1;
7060 break;
7061
7062 /* -V: SVR4 argument to print version ID. */
7063 case 'V':
7064 print_version_id ();
7065 break;
7066
7067 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7068 should be emitted or not. FIXME: Not implemented. */
7069 case 'Q':
7070 break;
7071
7072 case OPTION_BITWISE_OR:
7073 {
7074 char *n, *t;
7075 const char *s;
7076
7077 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7078 t = n;
7079 for (s = m68k_comment_chars; *s != '\0'; s++)
7080 if (*s != '|')
7081 *t++ = *s;
7082 *t = '\0';
7083 m68k_comment_chars = n;
7084 }
7085 break;
7086
7087 case OPTION_BASE_SIZE_DEFAULT_16:
7088 m68k_index_width_default = SIZE_WORD;
7089 break;
7090
7091 case OPTION_BASE_SIZE_DEFAULT_32:
7092 m68k_index_width_default = SIZE_LONG;
7093 break;
7094
7095 case OPTION_DISP_SIZE_DEFAULT_16:
7096 m68k_rel32 = 0;
7097 m68k_rel32_from_cmdline = 1;
7098 break;
7099
7100 case OPTION_DISP_SIZE_DEFAULT_32:
7101 m68k_rel32 = 1;
7102 m68k_rel32_from_cmdline = 1;
7103 break;
7104
7105 default:
7106 return 0;
7107 }
7108
7109 return 1;
7110}
7111
7112void
31302357 7113md_show_usage (FILE *stream)
252b5132 7114{
76f57f3a 7115 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7116 int i;
7117 unsigned int default_arch;
76f57f3a 7118
8a104df9 7119 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7120 if (*default_cpu == 'm')
7121 default_cpu++;
7122 for (i = 0; i < n_archs; i++)
7123 {
7124 if (strcasecmp (default_cpu, archs[i].name) == 0)
7125 {
7126 default_arch = archs[i].arch;
7127 for (i = 0; i < n_archs; i++)
7128 {
7129 if (archs[i].arch == default_arch
7130 && !archs[i].alias)
7131 {
7132 default_cpu = archs[i].name;
7133 break;
7134 }
7135 }
7136 }
7137 }
7138
bc805888 7139 fprintf (stream, _("\
252b5132
RH		 7140680X0 options:\n\
7141-l use 1 word for refs to undefined symbols [default 2]\n\
98b32482
NC		 7142-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\
7143-m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\
6b6e92f4
NC		 7144-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\
7145-m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\
76f57f3a 7146 specify variant of 680X0 architecture [default %s]\n\
252b5132
RH		 7147-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
7148 target has/lacks floating-point coprocessor\n\
76f57f3a
JT		 7149 [default yes for 68020, 68030, and cpu32]\n"),
7150 default_cpu);
bc805888 7151 fprintf (stream, _("\
252b5132
RH		 7152-m68851 | -mno-68851\n\
7153 target has/lacks memory-management unit coprocessor\n\
7154 [default yes for 68020 and up]\n\
7155-pic, -k generate position independent code\n\
7156-S turn jbsr into jsr\n\
28e7409f 7157--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7158--register-prefix-optional\n\
7159 recognize register names without prefix character\n\
7160--bitwise-or do not treat `|' as a comment character\n"));
7161 fprintf (stream, _("\
7162--base-size-default-16 base reg without size is 16 bits\n\
7163--base-size-default-32 base reg without size is 32 bits (default)\n\
7164--disp-size-default-16 displacement with unknown size is 16 bits\n\
7165--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
7166}
7167\f
7168#ifdef TEST2
7169
7170/* TEST2: Test md_assemble() */
36759679
NC		 7171/* Warning, this routine probably doesn't work anymore. */
7172int
31302357 7173main (void)
252b5132
RH		 7174{
7175 struct m68k_it the_ins;
7176 char buf[120];
7177 char *cp;
7178 int n;
7179
7180 m68k_ip_begin ();
7181 for (;;)
7182 {
7183 if (!gets (buf) || !*buf)
7184 break;
7185 if (buf[0] == '|' || buf[1] == '.')
7186 continue;
7187 for (cp = buf; *cp; cp++)
7188 if (*cp == '\t')
7189 *cp = ' ';
7190 if (is_label (buf))
7191 continue;
7192 memset (&the_ins, '\0', sizeof (the_ins));
7193 m68k_ip (&the_ins, buf);
7194 if (the_ins.error)
7195 {
7196 printf (_("Error %s in %s\n"), the_ins.error, buf);
7197 }
7198 else
7199 {
7200 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7201 for (n = 0; n < the_ins.numo; n++)
7202 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7203 printf (" ");
7204 print_the_insn (&the_ins.opcode[0], stdout);
7205 (void) putchar ('\n');
7206 }
7207 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7208 {
7209 if (the_ins.operands[n].error)
7210 {
7211 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7212 continue;
7213 }
31302357
AS		 7214 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7215 the_ins.operands[n].reg);
252b5132 7216 if (the_ins.operands[n].b_const)
31302357
AS		 7217 printf ("Constant: '%.*s', ",
7218 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7219 the_ins.operands[n].b_const);
7220 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7221 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7222 if (the_ins.operands[n].b_iadd)
31302357
AS		 7223 printf ("Iadd: '%.*s',",
7224 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7225 the_ins.operands[n].b_iadd);
7226 putchar ('\n');
252b5132
RH		 7227 }
7228 }
7229 m68k_ip_end ();
7230 return 0;
7231}
7232
31302357
AS		 7233int
7234is_label (char *str)
252b5132
RH		 7235{
7236 while (*str == ' ')
7237 str++;
7238 while (*str && *str != ' ')
7239 str++;
7240 if (str[-1] == ':' || str[1] == '=')
7241 return 1;
7242 return 0;
7243}
7244
7245#endif
7246
7247/* Possible states for relaxation:
7248
7249 0 0 branch offset byte (bra, etc)
7250 0 1 word
7251 0 2 long
7252
7253 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7254 1 1 word
7255 1 2 long
7256
7257 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7258 2 1 word-long
7259 2 2 long-word
7260 2 3 long-long
7261
7262 */
7263
7264/* We have no need to default values of symbols. */
7265
252b5132 7266symbolS *
31302357 7267md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7268{
7269 return 0;
7270}
7271
7272/* Round up a section size to the appropriate boundary. */
7273valueT
31302357 7274md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7275{
7276#ifdef OBJ_AOUT
252b5132
RH		 7277 /* For a.out, force the section size to be aligned. If we don't do
7278 this, BFD will align it for us, but it will not write out the
7279 final bytes of the section. This may be a bug in BFD, but it is
7280 easier to fix it here since that is how the other a.out targets
7281 work. */
7282 int align;
7283
7284 align = bfd_get_section_alignment (stdoutput, segment);
7285 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7286#endif
7287
7288 return size;
7289}
7290
7291/* Exactly what point is a PC-relative offset relative TO?
7292 On the 68k, it is relative to the address of the first extension
7293 word. The difference between the addresses of the offset and the
92774660 7294 first extension word is stored in fx_pcrel_adjust. */
252b5132 7295long
31302357 7296md_pcrel_from (fixS *fixP)
252b5132
RH		 7297{
7298 int adjust;
7299
8390138c
AS		 7300 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7301 sign extend the value here. */
7302 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7303 if (adjust == 64)
7304 adjust = -1;
7305 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7306}
7307
0d96863f 7308#ifdef OBJ_ELF
8a104df9 7309void
31302357 7310m68k_elf_final_processing (void)
0d96863f 7311{
36759679 7312 /* Set file-specific flags if this is a cpu32 processor. */
238d258f
NC		 7313 if (arch_coldfire_fpu (current_architecture))
7314 elf_elfheader (stdoutput)->e_flags |= EF_CFV4E;
8a104df9
KH		 7315 if (cpu_of_arch (current_architecture) & cpu32)
7316 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7317 else if ((cpu_of_arch (current_architecture) & m68000up)
7318 && !(cpu_of_arch (current_architecture) & m68020up))
7319 elf_elfheader (stdoutput)->e_flags |= EF_M68000;
0d96863f
CM		 7320}
7321#endif
c04898f8
AS		 7322
7323int
7324tc_m68k_regname_to_dw2regnum (const char *regname)
7325{
7326 unsigned int regnum;
7327 static const char *const regnames[] =
7328 {
7329 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7330 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7331 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7332 "pc"
7333 };
7334
7335 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7336 if (strcmp (regname, regnames[regnum]) == 0)
7337 return regnum;
7338
7339 return -1;
7340}
7341
7342void
7343tc_m68k_frame_initial_instructions (void)
7344{
7345 static int sp_regno = -1;
7346
7347 if (sp_regno < 0)
7348 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7349
7350 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7351 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7352}
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