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* config/m68k-parse.h (m68k_register): Add ROMBAR0, ASID.
[thirdparty/binutils-gdb.git] / gas / config / tc-m68k.c
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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
266abb8f 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 176 RAMBAR0, RAMBAR1, MBAR,
177 0
178};
2da12c60 179static const enum m68k_register mcf5208_ctrl[] = {
266abb8f
NS		 180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182};
2da12c60 183static const enum m68k_register mcf5213_ctrl[] = {
266abb8f
NS		 184 VBR, RAMBAR, FLASHBAR,
185 0
186};
2da12c60
NS		 187static const enum m68k_register mcf5216_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
266abb8f
NS		 189 0
190};
2da12c60
NS		 191static const enum m68k_register mcf5235_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, RAMBAR,
e80e0390
NC		 193 0
194};
2da12c60
NS		 195static const enum m68k_register mcf5249_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
3e602632
NC		 197 0
198};
2da12c60
NS		 199static const enum m68k_register mcf5250_ctrl[] = {
200 VBR,
201 0
202};
203static const enum m68k_register mcf5271_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206};
207static const enum m68k_register mcf5272_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
209 0
210};
211static const enum m68k_register mcf5275_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR,
213 0
214};
215static const enum m68k_register mcf5282_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
217 0
218};
219static const enum m68k_register mcf5329_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR,
221 0
222};
223static const enum m68k_register mcf5373_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226};
227static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 228 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
229 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
230 MBAR, SECMBAR,
231 MPCR /* Multiprocessor Control register */,
232 EDRAMBAR /* Embedded DRAM Base Address Register */,
233 /* Permutation control registers. */
3e602632
NC		 234 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
235 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 236 /* Legacy names */
237 TC /* ASID */, BUSCR /* MMUBAR */,
238 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
239 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
240 ROMBAR /* ROMBAR0 */,
241 0
242};
243static const enum m68k_register mcf5475_ctrl[] = {
244 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
245 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
246 /* Legacy names */
247 TC /* ASID */, BUSCR /* MMUBAR */,
248 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
249 MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
250 0
251};
252static const enum m68k_register mcf5485_ctrl[] = {
253 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
254 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
255 /* Legacy names */
256 TC /* ASID */, BUSCR /* MMUBAR */,
257 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
258 MBAR1 /* MBAR */, ROMBAR /* ROMBAR0 */,
3e602632
NC		 259 0
260};
f7ec513b
KH		 261static const enum m68k_register fido_ctrl[] = {
262 SFC, DFC, USP, VBR, CAC, MBB,
263 0
264};
2da12c60 265#define cpu32_ctrl m68010_ctrl
252b5132
RH		 266
267static const enum m68k_register *control_regs;
268
36759679 269/* Internal form of a 68020 instruction. */
252b5132
RH		 270struct m68k_it
271{
272 const char *error;
36759679 273 const char *args; /* List of opcode info. */
252b5132
RH		 274 int numargs;
275
36759679 276 int numo; /* Number of shorts in opcode. */
252b5132
RH		 277 short opcode[11];
278
279 struct m68k_op operands[6];
280
36759679 281 int nexp; /* Number of exprs in use. */
252b5132
RH		 282 struct m68k_exp exprs[4];
283
36759679 284 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 285 struct
286 {
36759679 287 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 288 symbolS *fadd;
289 offsetT foff;
290 int fragty;
291 }
292 fragb[4];
293
36759679 294 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 295 struct
296 {
297 int n;
298 expressionS exp;
299 char wid;
300 char pcrel;
301 /* In a pc relative address the difference between the address
302 of the offset and the address that the offset is relative
303 to. This depends on the addressing mode. Basically this
304 is the value to put in the offset field to address the
305 first byte of the offset, without regarding the special
306 significance of some values (in the branch instruction, for
307 example). */
308 int pcrel_fix;
309#ifdef OBJ_ELF
310 /* Whether this expression needs special pic relocation, and if
311 so, which. */
312 enum pic_relocation pic_reloc;
313#endif
314 }
36759679 315 reloc[5]; /* Five is enough??? */
252b5132
RH		 316};
317
9840d27e 318#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 319#define float_of_arch(x) ((x) & mfloat)
320#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 321#define arch_coldfire_p(x) ((x) & mcfisa_a)
322#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 323
36759679 324/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 325#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 326
36759679 327static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 328
329#define op(ex) ((ex)->exp.X_op)
330#define adds(ex) ((ex)->exp.X_add_symbol)
331#define subs(ex) ((ex)->exp.X_op_symbol)
332#define offs(ex) ((ex)->exp.X_add_number)
333
36759679 334/* Macros for adding things to the m68k_it struct. */
31302357 335#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 336
36759679
NC		 337/* Like addword, but goes BEFORE general operands. */
338
252b5132 339static void
31302357 340insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 341{
342 int z;
07726851 343 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 344 the_ins.opcode[z] = the_ins.opcode[z - 1];
345 for (z = 0; z < the_ins.nrel; z++)
346 the_ins.reloc[z].n += 2;
252b5132
RH		 347 for (z = 0; z < the_ins.nfrag; z++)
348 the_ins.fragb[z].fragoff++;
8a104df9 349 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 350 the_ins.numo++;
351}
352
353/* The numo+1 kludge is so we can hit the low order byte of the prev word.
354 Blecch. */
355static void
31302357 356add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 357{
31302357
AS		 358 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
359 ? the_ins.numo * 2 - 1
360 : (width == 'b'
361 ? the_ins.numo * 2 + 1
362 : the_ins.numo * 2));
252b5132
RH		 363 the_ins.reloc[the_ins.nrel].exp = exp->exp;
364 the_ins.reloc[the_ins.nrel].wid = width;
365 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
366#ifdef OBJ_ELF
367 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
368#endif
369 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
370}
371
372/* Cause an extra frag to be generated here, inserting up to 10 bytes
373 (that value is chosen in the frag_var call in md_assemble). TYPE
374 is the subtype of the frag to be generated; its primary type is
375 rs_machine_dependent.
376
377 The TYPE parameter is also used by md_convert_frag_1 and
378 md_estimate_size_before_relax. The appropriate type of fixup will
379 be emitted by md_convert_frag_1.
380
381 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
382static void
31302357 383add_frag (symbolS *add, offsetT off, int type)
252b5132 384{
8a104df9
KH		 385 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
386 the_ins.fragb[the_ins.nfrag].fadd = add;
387 the_ins.fragb[the_ins.nfrag].foff = off;
388 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 389}
390
391#define isvar(ex) \
392 (op (ex) != O_constant && op (ex) != O_big)
393
31302357
AS		 394static char *crack_operand (char *str, struct m68k_op *opP);
395static int get_num (struct m68k_exp *exp, int ok);
396static int reverse_16_bits (int in);
397static int reverse_8_bits (int in);
398static void install_gen_operand (int mode, int val);
399static void install_operand (int mode, int val);
400static void s_bss (int);
401static void s_data1 (int);
402static void s_data2 (int);
403static void s_even (int);
404static void s_proc (int);
405static void s_chip (int);
406static void s_fopt (int);
407static void s_opt (int);
408static void s_reg (int);
409static void s_restore (int);
410static void s_save (int);
411static void s_mri_if (int);
412static void s_mri_else (int);
413static void s_mri_endi (int);
414static void s_mri_break (int);
415static void s_mri_next (int);
416static void s_mri_for (int);
417static void s_mri_endf (int);
418static void s_mri_repeat (int);
419static void s_mri_until (int);
420static void s_mri_while (int);
421static void s_mri_endw (int);
266abb8f
NS		 422static void s_m68k_cpu (int);
423static void s_m68k_arch (int);
424
425struct m68k_cpu
426{
427 unsigned long arch; /* Architecture features. */
2da12c60 428 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 429 const char *name; /* Name */
0b2e31dc
NS		 430 int alias; /* Alias for a cannonical name. If 1, then
431 succeeds canonical name, if -1 then
432 succeeds canonical name, if <-1 ||>1 this is a
433 deprecated name, and the next/previous name
434 should be used. */
266abb8f 435};
252b5132 436
266abb8f
NS		 437/* We hold flags for features explicitly enabled and explicitly
438 disabled. */
252b5132 439static int current_architecture;
266abb8f 440static int not_current_architecture;
266abb8f
NS		 441static const struct m68k_cpu *selected_arch;
442static const struct m68k_cpu *selected_cpu;
443static int initialized;
252b5132 444
266abb8f
NS		 445/* Architecture models. */
446static const struct m68k_cpu m68k_archs[] =
447{
2da12c60
NS		 448 {m68000, m68000_ctrl, "68000", 0},
449 {m68010, m68010_ctrl, "68010", 0},
450 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
451 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
452 {m68040, m68040_ctrl, "68040", 0},
453 {m68060, m68060_ctrl, "68060", 0},
454 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 455 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 456 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
457 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
458 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
459 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
460 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 461 {0,0,NULL, 0}
462};
252b5132 463
0b2e31dc
NS		 464/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
465 for either. */
266abb8f
NS		 466static const struct m68k_cpu m68k_extensions[] =
467{
2da12c60
NS		 468 {m68851, NULL, "68851", -1},
469 {m68881, NULL, "68881", -1},
470 {m68881, NULL, "68882", -1},
0b2e31dc 471
2da12c60 472 {cfloat|m68881, NULL, "float", 0},
266abb8f 473
2da12c60
NS		 474 {mcfhwdiv, NULL, "div", 1},
475 {mcfusp, NULL, "usp", 1},
476 {mcfmac, NULL, "mac", 1},
477 {mcfemac, NULL, "emac", 1},
266abb8f 478
2da12c60 479 {0,NULL,NULL, 0}
266abb8f
NS		 480};
481
482/* Processor list */
483static const struct m68k_cpu m68k_cpus[] =
484{
2da12c60
NS		 485 {m68000, m68000_ctrl, "68000", 0},
486 {m68000, m68000_ctrl, "68ec000", 1},
487 {m68000, m68000_ctrl, "68hc000", 1},
488 {m68000, m68000_ctrl, "68hc001", 1},
489 {m68000, m68000_ctrl, "68008", 1},
490 {m68000, m68000_ctrl, "68302", 1},
491 {m68000, m68000_ctrl, "68306", 1},
492 {m68000, m68000_ctrl, "68307", 1},
493 {m68000, m68000_ctrl, "68322", 1},
494 {m68000, m68000_ctrl, "68356", 1},
495 {m68010, m68010_ctrl, "68010", 0},
496 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
497 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
498 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
499 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
500 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
501 {m68040, m68040_ctrl, "68040", 0},
502 {m68040, m68040_ctrl, "68ec040", 1},
503 {m68060, m68060_ctrl, "68060", 0},
504 {m68060, m68060_ctrl, "68ec060", 1},
505
506 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
507 {cpu32|m68881, cpu32_ctrl, "68330", 1},
508 {cpu32|m68881, cpu32_ctrl, "68331", 1},
509 {cpu32|m68881, cpu32_ctrl, "68332", 1},
510 {cpu32|m68881, cpu32_ctrl, "68333", 1},
511 {cpu32|m68881, cpu32_ctrl, "68334", 1},
512 {cpu32|m68881, cpu32_ctrl, "68336", 1},
513 {cpu32|m68881, cpu32_ctrl, "68340", 1},
514 {cpu32|m68881, cpu32_ctrl, "68341", 1},
515 {cpu32|m68881, cpu32_ctrl, "68349", 1},
516 {cpu32|m68881, cpu32_ctrl, "68360", 1},
517
518 {mcfisa_a, mcf_ctrl, "5200", 0},
519 {mcfisa_a, mcf_ctrl, "5202", 1},
520 {mcfisa_a, mcf_ctrl, "5204", 1},
521 {mcfisa_a, mcf_ctrl, "5206", 1},
522
523 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
524
525 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
526 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
527
528 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
530 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
531
532 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
533 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
534 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
535
536 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
537 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
538 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
539 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
540 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
541
542 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
543 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
544
545 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
546 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
547
548 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
549
550 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
551 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
552
553 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
554 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
555 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
556 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
557
558 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
559
560 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
561 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
562 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
563 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
564
565 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
566 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
567 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
568
569 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
570
a8e24a56
NS		 571 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
572 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
573 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
574 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
575 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
576 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
577 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 578
a8e24a56
NS		 579 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
580 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
581 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
582 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
583 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
584 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
585 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 586
3bdcfdf4 587 {fido_a, fido_ctrl, "fido", 1},
9840d27e 588
2da12c60 589 {0,NULL,NULL, 0}
dc84e067 590 };
252b5132 591
266abb8f
NS		 592static const struct m68k_cpu *m68k_lookup_cpu
593(const char *, const struct m68k_cpu *, int, int *);
594static int m68k_set_arch (const char *, int, int);
595static int m68k_set_cpu (const char *, int, int);
596static int m68k_set_extension (const char *, int, int);
597static void m68k_init_arch (void);
252b5132 598
151337e8
NC		 599/* This is the assembler relaxation table for m68k. m68k is a rich CISC
600 architecture and we have a lot of relaxation modes. */
252b5132 601
151337e8
NC		 602/* Macros used in the relaxation code. */
603#define TAB(x,y) (((x) << 2) + (y))
604#define TABTYPE(x) ((x) >> 2)
605
606/* Relaxation states. */
607#define BYTE 0
608#define SHORT 1
609#define LONG 2
610#define SZ_UNDEF 3
611
612/* Here are all the relaxation modes we support. First we can relax ordinary
613 branches. On 68020 and higher and on CPU32 all branch instructions take
614 three forms, so on these CPUs all branches always remain as such. When we
615 have to expand to the LONG form on a 68000, though, we substitute an
616 absolute jump instead. This is a direct replacement for unconditional
617 branches and a branch over a jump for conditional branches. However, if the
618 user requires PIC and disables this with --pcrel, we can only relax between
619 BYTE and SHORT forms, punting if that isn't enough. This gives us four
620 different relaxation modes for branches: */
621
36759679
NC		 622#define BRANCHBWL 0 /* Branch byte, word, or long. */
623#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
624#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
625#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 626
627/* We also relax coprocessor branches and DBcc's. All CPUs that support
628 coprocessor branches support them in word and long forms, so we have only
629 one relaxation mode for them. DBcc's are word only on all CPUs. We can
630 relax them to the LONG form with a branch-around sequence. This sequence
631 can use a long branch (if available) or an absolute jump (if acceptable).
632 This gives us two relaxation modes. If long branches are not available and
633 absolute jumps are not acceptable, we don't relax DBcc's. */
634
36759679
NC		 635#define FBRANCH 4 /* Coprocessor branch. */
636#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
637#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 638
639/* That's all for instruction relaxation. However, we also relax PC-relative
640 operands. Specifically, we have three operand relaxation modes. On the
641 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
642 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
643 two. Also PC+displacement+index operands in their simple form (with a non-
644 suppressed index without memory indirection) are supported on all CPUs, but
645 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
646 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
647 form of the PC+displacement+index operand. Finally, some absolute operands
648 can be relaxed down to 16-bit PC-relative. */
649
36759679
NC		 650#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
651#define PCINDEX 8 /* PC + displacement + index. */
652#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 653
654/* Note that calls to frag_var need to specify the maximum expansion
655 needed; this is currently 10 bytes for DBCC. */
656
657/* The fields are:
658 How far Forward this mode will reach:
659 How far Backward this mode will reach:
660 How many bytes this mode will add to the size of the frag
661 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 662
663 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 664relax_typeS md_relax_table[] =
665{
ac62c346
AM		 666 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
667 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
668 { 0, 0, 4, 0 },
669 { 1, 1, 0, 0 },
670
671 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
672 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
673 { 0, 0, 4, 0 },
674 { 1, 1, 0, 0 },
675
676 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
677 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
678 { 0, 0, 6, 0 },
679 { 1, 1, 0, 0 },
680
681 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
682 { 0, 0, 2, 0 },
683 { 1, 1, 0, 0 },
684 { 1, 1, 0, 0 },
685
36759679 686 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 687 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
688 { 0, 0, 4, 0 },
689 { 1, 1, 0, 0 },
690
36759679 691 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 692 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
693 { 0, 0, 10, 0 },
694 { 1, 1, 0, 0 },
695
36759679 696 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 697 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
698 { 0, 0, 10, 0 },
699 { 1, 1, 0, 0 },
700
36759679 701 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 702 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
703 { 0, 0, 6, 0 },
704 { 1, 1, 0, 0 },
705
706 { 125, -130, 0, TAB (PCINDEX, SHORT) },
707 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
708 { 0, 0, 4, 0 },
709 { 1, 1, 0, 0 },
710
36759679 711 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 712 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
713 { 0, 0, 4, 0 },
714 { 1, 1, 0, 0 },
252b5132
RH		 715};
716
717/* These are the machine dependent pseudo-ops. These are included so
718 the assembler can work on the output from the SUN C compiler, which
36759679 719 generates these. */
252b5132
RH		 720
721/* This table describes all the machine specific pseudo-ops the assembler
722 has to support. The fields are:
723 pseudo-op name without dot
724 function to call to execute this pseudo-op
36759679 725 Integer arg to pass to the function. */
252b5132
RH		 726const pseudo_typeS md_pseudo_table[] =
727{
728 {"data1", s_data1, 0},
729 {"data2", s_data2, 0},
730 {"bss", s_bss, 0},
731 {"even", s_even, 0},
732 {"skip", s_space, 0},
733 {"proc", s_proc, 0},
734#if defined (TE_SUN3) || defined (OBJ_ELF)
735 {"align", s_align_bytes, 0},
736#endif
737#ifdef OBJ_ELF
738 {"swbeg", s_ignore, 0},
739#endif
740 {"extend", float_cons, 'x'},
741 {"ldouble", float_cons, 'x'},
742
266abb8f
NS		 743 {"arch", s_m68k_arch, 0},
744 {"cpu", s_m68k_cpu, 0},
745
252b5132
RH		 746 /* The following pseudo-ops are supported for MRI compatibility. */
747 {"chip", s_chip, 0},
748 {"comline", s_space, 1},
749 {"fopt", s_fopt, 0},
750 {"mask2", s_ignore, 0},
751 {"opt", s_opt, 0},
752 {"reg", s_reg, 0},
753 {"restore", s_restore, 0},
754 {"save", s_save, 0},
755
756 {"if", s_mri_if, 0},
757 {"if.b", s_mri_if, 'b'},
758 {"if.w", s_mri_if, 'w'},
759 {"if.l", s_mri_if, 'l'},
760 {"else", s_mri_else, 0},
761 {"else.s", s_mri_else, 's'},
762 {"else.l", s_mri_else, 'l'},
763 {"endi", s_mri_endi, 0},
764 {"break", s_mri_break, 0},
765 {"break.s", s_mri_break, 's'},
766 {"break.l", s_mri_break, 'l'},
767 {"next", s_mri_next, 0},
768 {"next.s", s_mri_next, 's'},
769 {"next.l", s_mri_next, 'l'},
770 {"for", s_mri_for, 0},
771 {"for.b", s_mri_for, 'b'},
772 {"for.w", s_mri_for, 'w'},
773 {"for.l", s_mri_for, 'l'},
774 {"endf", s_mri_endf, 0},
775 {"repeat", s_mri_repeat, 0},
776 {"until", s_mri_until, 0},
777 {"until.b", s_mri_until, 'b'},
778 {"until.w", s_mri_until, 'w'},
779 {"until.l", s_mri_until, 'l'},
780 {"while", s_mri_while, 0},
781 {"while.b", s_mri_while, 'b'},
782 {"while.w", s_mri_while, 'w'},
783 {"while.l", s_mri_while, 'l'},
784 {"endw", s_mri_endw, 0},
785
786 {0, 0, 0}
787};
788
252b5132 789/* The mote pseudo ops are put into the opcode table, since they
31302357 790 don't start with a . they look like opcodes to gas. */
252b5132 791
5a38dc70 792const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 793{
794
795 {"dcl", cons, 4},
796 {"dc", cons, 2},
797 {"dcw", cons, 2},
798 {"dcb", cons, 1},
799
800 {"dsl", s_space, 4},
801 {"ds", s_space, 2},
802 {"dsw", s_space, 2},
803 {"dsb", s_space, 1},
804
805 {"xdef", s_globl, 0},
806#ifdef OBJ_ELF
807 {"align", s_align_bytes, 0},
808#else
809 {"align", s_align_ptwo, 0},
810#endif
811#ifdef M68KCOFF
812 {"sect", obj_coff_section, 0},
813 {"section", obj_coff_section, 0},
814#endif
815 {0, 0, 0}
816};
817
bd17c2c3
AM		 818/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
819 gives identical results to a 32-bit host. */
820#define TRUNC(X) ((valueT) (X) & 0xffffffff)
821#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
822
823#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
824#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
825#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
826#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
827
828#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
829#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 830#define islong(x) (1)
831
252b5132
RH		 832static char notend_table[256];
833static char alt_notend_table[256];
834#define notend(s) \
835 (! (notend_table[(unsigned char) *s] \
836 || (*s == ':' \
837 && alt_notend_table[(unsigned char) s[1]])))
838
252b5132
RH		 839#ifdef OBJ_ELF
840
c801568a
AM		 841/* Return zero if the reference to SYMBOL from within the same segment may
842 be relaxed. */
843
844/* On an ELF system, we can't relax an externally visible symbol,
845 because it may be overridden by a shared library. However, if
846 TARGET_OS is "elf", then we presume that we are assembling for an
847 embedded system, in which case we don't have to worry about shared
848 libraries, and we can relax any external sym. */
849
850#define relaxable_symbol(symbol) \
6358301e 851 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 852 || S_IS_WEAK (symbol)))
853
252b5132
RH		 854/* Compute the relocation code for a fixup of SIZE bytes, using pc
855 relative relocation if PCREL is non-zero. PIC says whether a special
856 pic relocation was requested. */
857
252b5132 858static bfd_reloc_code_real_type
31302357 859get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 860{
861 switch (pic)
862 {
863 case pic_got_pcrel:
864 switch (size)
865 {
866 case 1:
867 return BFD_RELOC_8_GOT_PCREL;
868 case 2:
869 return BFD_RELOC_16_GOT_PCREL;
870 case 4:
871 return BFD_RELOC_32_GOT_PCREL;
872 }
873 break;
874
875 case pic_got_off:
876 switch (size)
877 {
878 case 1:
879 return BFD_RELOC_8_GOTOFF;
880 case 2:
881 return BFD_RELOC_16_GOTOFF;
882 case 4:
883 return BFD_RELOC_32_GOTOFF;
884 }
885 break;
886
887 case pic_plt_pcrel:
888 switch (size)
889 {
890 case 1:
891 return BFD_RELOC_8_PLT_PCREL;
892 case 2:
893 return BFD_RELOC_16_PLT_PCREL;
894 case 4:
895 return BFD_RELOC_32_PLT_PCREL;
896 }
897 break;
898
899 case pic_plt_off:
900 switch (size)
901 {
902 case 1:
903 return BFD_RELOC_8_PLTOFF;
904 case 2:
905 return BFD_RELOC_16_PLTOFF;
906 case 4:
907 return BFD_RELOC_32_PLTOFF;
908 }
909 break;
910
911 case pic_none:
912 if (pcrel)
913 {
914 switch (size)
915 {
916 case 1:
917 return BFD_RELOC_8_PCREL;
918 case 2:
919 return BFD_RELOC_16_PCREL;
920 case 4:
921 return BFD_RELOC_32_PCREL;
922 }
923 }
924 else
925 {
926 switch (size)
927 {
928 case 1:
929 return BFD_RELOC_8;
930 case 2:
931 return BFD_RELOC_16;
932 case 4:
933 return BFD_RELOC_32;
934 }
935 }
936 }
937
938 if (pcrel)
939 {
940 if (pic == pic_none)
941 as_bad (_("Can not do %d byte pc-relative relocation"), size);
942 else
943 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
944 }
945 else
946 {
947 if (pic == pic_none)
948 as_bad (_("Can not do %d byte relocation"), size);
949 else
950 as_bad (_("Can not do %d byte pic relocation"), size);
951 }
952
953 return BFD_RELOC_NONE;
954}
955
956/* Here we decide which fixups can be adjusted to make them relative
957 to the beginning of the section instead of the symbol. Basically
958 we need to make sure that the dynamic relocations are done
959 correctly, so in some cases we force the original symbol to be
960 used. */
961int
31302357 962tc_m68k_fix_adjustable (fixS *fixP)
252b5132 963{
36759679 964 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 965 switch (fixP->fx_r_type)
966 {
967 case BFD_RELOC_8_GOT_PCREL:
968 case BFD_RELOC_16_GOT_PCREL:
969 case BFD_RELOC_32_GOT_PCREL:
970 case BFD_RELOC_8_GOTOFF:
971 case BFD_RELOC_16_GOTOFF:
972 case BFD_RELOC_32_GOTOFF:
973 case BFD_RELOC_8_PLT_PCREL:
974 case BFD_RELOC_16_PLT_PCREL:
975 case BFD_RELOC_32_PLT_PCREL:
976 case BFD_RELOC_8_PLTOFF:
977 case BFD_RELOC_16_PLTOFF:
978 case BFD_RELOC_32_PLTOFF:
979 return 0;
980
981 case BFD_RELOC_VTABLE_INHERIT:
982 case BFD_RELOC_VTABLE_ENTRY:
983 return 0;
984
985 default:
986 return 1;
987 }
988}
989
990#else /* !OBJ_ELF */
991
992#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
993
c801568a
AM		 994#define relaxable_symbol(symbol) 1
995
252b5132
RH		 996#endif /* OBJ_ELF */
997
252b5132 998arelent *
31302357 999tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1000{
1001 arelent *reloc;
1002 bfd_reloc_code_real_type code;
1003
8ec6253e
NC		 1004 /* If the tcbit is set, then this was a fixup of a negative value
1005 that was never resolved. We do not have a reloc to handle this,
1006 so just return. We assume that other code will have detected this
1007 situation and produced a helpful error message, so we just tell the
1008 user that the reloc cannot be produced. */
252b5132 1009 if (fixp->fx_tcbit)
8ec6253e
NC		 1010 {
1011 if (fixp->fx_addsy)
b091f402
AM		 1012 as_bad_where (fixp->fx_file, fixp->fx_line,
1013 _("Unable to produce reloc against symbol '%s'"),
1014 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1015 return NULL;
1016 }
252b5132
RH		 1017
1018 if (fixp->fx_r_type != BFD_RELOC_NONE)
1019 {
1020 code = fixp->fx_r_type;
1021
1022 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1023 that fixup_segment converted a non-PC relative reloc into a
1024 PC relative reloc. In such a case, we need to convert the
1025 reloc code. */
1026 if (fixp->fx_pcrel)
1027 {
1028 switch (code)
1029 {
1030 case BFD_RELOC_8:
1031 code = BFD_RELOC_8_PCREL;
1032 break;
1033 case BFD_RELOC_16:
1034 code = BFD_RELOC_16_PCREL;
1035 break;
1036 case BFD_RELOC_32:
1037 code = BFD_RELOC_32_PCREL;
1038 break;
1039 case BFD_RELOC_8_PCREL:
1040 case BFD_RELOC_16_PCREL:
1041 case BFD_RELOC_32_PCREL:
1042 case BFD_RELOC_8_GOT_PCREL:
1043 case BFD_RELOC_16_GOT_PCREL:
1044 case BFD_RELOC_32_GOT_PCREL:
1045 case BFD_RELOC_8_GOTOFF:
1046 case BFD_RELOC_16_GOTOFF:
1047 case BFD_RELOC_32_GOTOFF:
1048 case BFD_RELOC_8_PLT_PCREL:
1049 case BFD_RELOC_16_PLT_PCREL:
1050 case BFD_RELOC_32_PLT_PCREL:
1051 case BFD_RELOC_8_PLTOFF:
1052 case BFD_RELOC_16_PLTOFF:
1053 case BFD_RELOC_32_PLTOFF:
1054 break;
1055 default:
1056 as_bad_where (fixp->fx_file, fixp->fx_line,
1057 _("Cannot make %s relocation PC relative"),
1058 bfd_get_reloc_code_name (code));
1059 }
1060 }
1061 }
1062 else
1063 {
1064#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1065 switch (F (fixp->fx_size, fixp->fx_pcrel))
1066 {
1067#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1068 MAP (1, 0, BFD_RELOC_8);
1069 MAP (2, 0, BFD_RELOC_16);
1070 MAP (4, 0, BFD_RELOC_32);
1071 MAP (1, 1, BFD_RELOC_8_PCREL);
1072 MAP (2, 1, BFD_RELOC_16_PCREL);
1073 MAP (4, 1, BFD_RELOC_32_PCREL);
1074 default:
1075 abort ();
1076 }
1077 }
1078#undef F
1079#undef MAP
1080
1081 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1082 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1083 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1084 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1085#ifndef OBJ_ELF
1086 if (fixp->fx_pcrel)
1087 reloc->addend = fixp->fx_addnumber;
1088 else
1089 reloc->addend = 0;
1090#else
1091 if (!fixp->fx_pcrel)
1092 reloc->addend = fixp->fx_addnumber;
1093 else
1094 reloc->addend = (section->vma
8390138c
AS		 1095 /* Explicit sign extension in case char is
1096 unsigned. */
1097 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1098 + fixp->fx_addnumber
1099 + md_pcrel_from (fixp));
1100#endif
1101
1102 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1103 assert (reloc->howto != 0);
1104
1105 return reloc;
1106}
1107
252b5132
RH		 1108/* Handle of the OPCODE hash table. NULL means any use before
1109 m68k_ip_begin() will crash. */
1110static struct hash_control *op_hash;
1111\f
1112/* Assemble an m68k instruction. */
1113
1114static void
31302357 1115m68k_ip (char *instring)
252b5132
RH		 1116{
1117 register char *p;
1118 register struct m68k_op *opP;
1119 register const struct m68k_incant *opcode;
1120 register const char *s;
1121 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1122 char *pdot, *pdotmove;
1123 enum m68k_size siz1, siz2;
1124 char c;
1125 int losing;
1126 int opsfound;
03b13e59 1127 struct m68k_op operands_backup[6];
252b5132
RH		 1128 LITTLENUM_TYPE words[6];
1129 LITTLENUM_TYPE *wordp;
1130 unsigned long ok_arch = 0;
1131
1132 if (*instring == ' ')
36759679 1133 instring++; /* Skip leading whitespace. */
252b5132
RH		 1134
1135 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1136 or exactly 1 space. */
252b5132
RH		 1137 pdot = 0;
1138 for (p = instring; *p != '\0'; p++)
1139 {
1140 if (*p == ' ')
1141 break;
1142 if (*p == '.')
1143 pdot = p;
1144 }
1145
1146 if (p == instring)
1147 {
1148 the_ins.error = _("No operator");
1149 return;
1150 }
1151
1152 /* p now points to the end of the opcode name, probably whitespace.
1153 Make sure the name is null terminated by clobbering the
1154 whitespace, look it up in the hash table, then fix it back.
1155 Remove a dot, first, since the opcode tables have none. */
1156 if (pdot != NULL)
1157 {
1158 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1159 *pdotmove = pdotmove[1];
1160 p--;
1161 }
1162
1163 c = *p;
1164 *p = '\0';
1165 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1166 *p = c;
1167
1168 if (pdot != NULL)
1169 {
1170 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1171 *pdotmove = pdotmove[-1];
1172 *pdot = '.';
1173 ++p;
1174 }
1175
1176 if (opcode == NULL)
1177 {
1178 the_ins.error = _("Unknown operator");
1179 return;
1180 }
1181
36759679 1182 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1183 while (*p == ' ')
1184 ++p;
1185
1186 if (opcode->m_operands == 0)
1187 {
1188 char *old = input_line_pointer;
1189 *old = '\n';
1190 input_line_pointer = p;
36759679 1191 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1192 mote_pseudo_table[opcode->m_opnum].poc_handler
1193 (mote_pseudo_table[opcode->m_opnum].poc_val);
1194 input_line_pointer = old;
1195 *old = 0;
1196
1197 return;
1198 }
1199
1200 if (flag_mri && opcode->m_opnum == 0)
1201 {
1202 /* In MRI mode, random garbage is allowed after an instruction
1203 which accepts no operands. */
1204 the_ins.args = opcode->m_operands;
1205 the_ins.numargs = opcode->m_opnum;
1206 the_ins.numo = opcode->m_codenum;
1207 the_ins.opcode[0] = getone (opcode);
1208 the_ins.opcode[1] = gettwo (opcode);
1209 return;
1210 }
1211
1212 for (opP = &the_ins.operands[0]; *p; opP++)
1213 {
1214 p = crack_operand (p, opP);
1215
1216 if (opP->error)
1217 {
1218 the_ins.error = opP->error;
1219 return;
1220 }
1221 }
1222
1223 opsfound = opP - &the_ins.operands[0];
1224
1225 /* This ugly hack is to support the floating pt opcodes in their
1226 standard form. Essentially, we fake a first enty of type COP#1 */
1227 if (opcode->m_operands[0] == 'I')
1228 {
1229 int n;
1230
1231 for (n = opsfound; n > 0; --n)
1232 the_ins.operands[n] = the_ins.operands[n - 1];
1233
31302357 1234 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1235 the_ins.operands[0].mode = CONTROL;
1236 the_ins.operands[0].reg = m68k_float_copnum;
1237 opsfound++;
1238 }
1239
36759679 1240 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1241 for (losing = 0;;)
1242 {
1243 /* If we didn't get the right number of ops, or we have no
92774660 1244 common model with this pattern then reject this pattern. */
252b5132
RH		 1245
1246 ok_arch |= opcode->m_arch;
1247 if (opsfound != opcode->m_opnum
1248 || ((opcode->m_arch & current_architecture) == 0))
1249 ++losing;
1250 else
1251 {
03b13e59
NC		 1252 int i;
1253
1254 /* Make a copy of the operands of this insn so that
1255 we can modify them safely, should we want to. */
1256 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1257 for (i = 0; i < opsfound; i++)
1258 operands_backup[i] = the_ins.operands[i];
1259
1260 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1261 *s && !losing;
1262 s += 2, opP++)
1263 {
1264 /* Warning: this switch is huge! */
1265 /* I've tried to organize the cases into this order:
1266 non-alpha first, then alpha by letter. Lower-case
1267 goes directly before uppercase counterpart. */
1268 /* Code with multiple case ...: gets sorted by the lowest
1269 case ... it belongs to. I hope this makes sense. */
1270 switch (*s)
1271 {
1272 case '!':
1273 switch (opP->mode)
1274 {
1275 case IMMED:
1276 case DREG:
1277 case AREG:
1278 case FPREG:
1279 case CONTROL:
1280 case AINC:
1281 case ADEC:
1282 case REGLST:
1283 losing++;
1284 break;
1285 default:
1286 break;
1287 }
1288 break;
1289
1290 case '<':
1291 switch (opP->mode)
1292 {
1293 case DREG:
1294 case AREG:
1295 case FPREG:
1296 case CONTROL:
1297 case IMMED:
1298 case ADEC:
1299 case REGLST:
1300 losing++;
1301 break;
1302 default:
1303 break;
1304 }
1305 break;
1306
1307 case '>':
1308 switch (opP->mode)
1309 {
1310 case DREG:
1311 case AREG:
1312 case FPREG:
1313 case CONTROL:
1314 case IMMED:
1315 case AINC:
1316 case REGLST:
1317 losing++;
1318 break;
1319 case ABSL:
1320 break;
1321 default:
1322 if (opP->reg == PC
1323 || opP->reg == ZPC)
1324 losing++;
1325 break;
1326 }
1327 break;
1328
1329 case 'm':
1330 switch (opP->mode)
1331 {
1332 case DREG:
1333 case AREG:
1334 case AINDR:
1335 case AINC:
1336 case ADEC:
1337 break;
1338 default:
1339 losing++;
1340 }
8a104df9 1341 break;
252b5132
RH		 1342
1343 case 'n':
1344 switch (opP->mode)
1345 {
1346 case DISP:
1347 break;
1348 default:
1349 losing++;
1350 }
8a104df9 1351 break;
252b5132
RH		 1352
1353 case 'o':
1354 switch (opP->mode)
1355 {
1356 case BASE:
1357 case ABSL:
1358 case IMMED:
1359 break;
1360 default:
1361 losing++;
1362 }
8a104df9 1363 break;
252b5132
RH		 1364
1365 case 'p':
1366 switch (opP->mode)
1367 {
1368 case DREG:
1369 case AREG:
1370 case AINDR:
1371 case AINC:
1372 case ADEC:
1373 break;
1374 case DISP:
1375 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1376 losing++;
252b5132
RH		 1377 break;
1378 default:
1379 losing++;
1380 }
8a104df9 1381 break;
252b5132
RH		 1382
1383 case 'q':
1384 switch (opP->mode)
1385 {
1386 case DREG:
1387 case AINDR:
1388 case AINC:
1389 case ADEC:
1390 break;
1391 case DISP:
1392 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1393 losing++;
252b5132
RH		 1394 break;
1395 default:
1396 losing++;
1397 break;
1398 }
8a104df9 1399 break;
252b5132
RH		 1400
1401 case 'v':
1402 switch (opP->mode)
1403 {
1404 case DREG:
1405 case AINDR:
1406 case AINC:
1407 case ADEC:
1408 case ABSL:
1409 break;
1410 case DISP:
1411 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1412 losing++;
252b5132
RH		 1413 break;
1414 default:
1415 losing++;
1416 break;
1417 }
1418 break;
1419
1420 case '#':
1421 if (opP->mode != IMMED)
1422 losing++;
1423 else if (s[1] == 'b'
1424 && ! isvar (&opP->disp)
1425 && (opP->disp.exp.X_op != O_constant
1426 || ! isbyte (opP->disp.exp.X_add_number)))
1427 losing++;
1428 else if (s[1] == 'B'
1429 && ! isvar (&opP->disp)
1430 && (opP->disp.exp.X_op != O_constant
1431 || ! issbyte (opP->disp.exp.X_add_number)))
1432 losing++;
1433 else if (s[1] == 'w'
1434 && ! isvar (&opP->disp)
1435 && (opP->disp.exp.X_op != O_constant
1436 || ! isword (opP->disp.exp.X_add_number)))
1437 losing++;
1438 else if (s[1] == 'W'
1439 && ! isvar (&opP->disp)
1440 && (opP->disp.exp.X_op != O_constant
1441 || ! issword (opP->disp.exp.X_add_number)))
1442 losing++;
1443 break;
1444
1445 case '^':
1446 case 'T':
1447 if (opP->mode != IMMED)
1448 losing++;
1449 break;
1450
1451 case '$':
1452 if (opP->mode == AREG
1453 || opP->mode == CONTROL
1454 || opP->mode == FPREG
1455 || opP->mode == IMMED
1456 || opP->mode == REGLST
1457 || (opP->mode != ABSL
1458 && (opP->reg == PC
1459 || opP->reg == ZPC)))
1460 losing++;
1461 break;
1462
1463 case '%':
1464 if (opP->mode == CONTROL
1465 || opP->mode == FPREG
1466 || opP->mode == REGLST
1467 || opP->mode == IMMED
1468 || (opP->mode != ABSL
1469 && (opP->reg == PC
1470 || opP->reg == ZPC)))
1471 losing++;
1472 break;
1473
1474 case '&':
1475 switch (opP->mode)
1476 {
1477 case DREG:
1478 case AREG:
1479 case FPREG:
1480 case CONTROL:
1481 case IMMED:
1482 case AINC:
1483 case ADEC:
1484 case REGLST:
1485 losing++;
1486 break;
1487 case ABSL:
1488 break;
1489 default:
1490 if (opP->reg == PC
1491 || opP->reg == ZPC)
1492 losing++;
1493 break;
1494 }
1495 break;
1496
1497 case '*':
1498 if (opP->mode == CONTROL
1499 || opP->mode == FPREG
1500 || opP->mode == REGLST)
1501 losing++;
1502 break;
1503
1504 case '+':
1505 if (opP->mode != AINC)
1506 losing++;
1507 break;
1508
1509 case '-':
1510 if (opP->mode != ADEC)
1511 losing++;
1512 break;
1513
1514 case '/':
1515 switch (opP->mode)
1516 {
1517 case AREG:
1518 case CONTROL:
1519 case FPREG:
1520 case AINC:
1521 case ADEC:
1522 case IMMED:
1523 case REGLST:
1524 losing++;
1525 break;
1526 default:
1527 break;
1528 }
1529 break;
1530
1531 case ';':
1532 switch (opP->mode)
1533 {
1534 case AREG:
1535 case CONTROL:
1536 case FPREG:
1537 case REGLST:
1538 losing++;
1539 break;
1540 default:
1541 break;
1542 }
1543 break;
1544
1545 case '?':
1546 switch (opP->mode)
1547 {
1548 case AREG:
1549 case CONTROL:
1550 case FPREG:
1551 case AINC:
1552 case ADEC:
1553 case IMMED:
1554 case REGLST:
1555 losing++;
1556 break;
1557 case ABSL:
1558 break;
1559 default:
1560 if (opP->reg == PC || opP->reg == ZPC)
1561 losing++;
1562 break;
1563 }
1564 break;
1565
1566 case '@':
1567 switch (opP->mode)
1568 {
1569 case AREG:
1570 case CONTROL:
1571 case FPREG:
1572 case IMMED:
1573 case REGLST:
1574 losing++;
1575 break;
1576 default:
1577 break;
1578 }
1579 break;
1580
1581 case '~': /* For now! (JF FOO is this right?) */
1582 switch (opP->mode)
1583 {
1584 case DREG:
1585 case AREG:
1586 case CONTROL:
1587 case FPREG:
1588 case IMMED:
1589 case REGLST:
1590 losing++;
1591 break;
1592 case ABSL:
1593 break;
1594 default:
1595 if (opP->reg == PC
1596 || opP->reg == ZPC)
1597 losing++;
1598 break;
1599 }
1600 break;
1601
1602 case '3':
1603 if (opP->mode != CONTROL
1604 || (opP->reg != TT0 && opP->reg != TT1))
1605 losing++;
1606 break;
1607
1608 case 'A':
1609 if (opP->mode != AREG)
1610 losing++;
1611 break;
1612
1613 case 'a':
1614 if (opP->mode != AINDR)
1615 ++losing;
1616 break;
1617
fd99574b
NC		 1618 case '4':
1619 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1620 && (opP->mode != DISP
1621 || opP->reg < ADDR0
1622 || opP->reg > ADDR7))
1623 ++losing;
1624 break;
1625
252b5132
RH		 1626 case 'B': /* FOO */
1627 if (opP->mode != ABSL
1628 || (flag_long_jumps
1629 && strncmp (instring, "jbsr", 4) == 0))
1630 losing++;
1631 break;
1632
3e602632
NC		 1633 case 'b':
1634 switch (opP->mode)
1635 {
1636 case IMMED:
1637 case ABSL:
1638 case AREG:
1639 case FPREG:
1640 case CONTROL:
1641 case POST:
1642 case PRE:
1643 case REGLST:
1644 losing++;
1645 break;
1646 default:
1647 break;
1648 }
1649 break;
1650
252b5132
RH		 1651 case 'C':
1652 if (opP->mode != CONTROL || opP->reg != CCR)
1653 losing++;
1654 break;
1655
1656 case 'd':
1657 if (opP->mode != DISP
1658 || opP->reg < ADDR0
1659 || opP->reg > ADDR7)
1660 losing++;
1661 break;
1662
1663 case 'D':
1664 if (opP->mode != DREG)
1665 losing++;
1666 break;
1667
6da466c7
ILT		 1668 case 'E':
1669 if (opP->reg != ACC)
1670 losing++;
1671 break;
1672
fd99574b
NC		 1673 case 'e':
1674 if (opP->reg != ACC && opP->reg != ACC1
1675 && opP->reg != ACC2 && opP->reg != ACC3)
1676 losing++;
1677 break;
1678
252b5132
RH		 1679 case 'F':
1680 if (opP->mode != FPREG)
1681 losing++;
1682 break;
1683
6da466c7
ILT		 1684 case 'G':
1685 if (opP->reg != MACSR)
1686 losing++;
1687 break;
1688
fd99574b
NC		 1689 case 'g':
1690 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1691 losing++;
1692 break;
1693
6da466c7
ILT		 1694 case 'H':
1695 if (opP->reg != MASK)
1696 losing++;
1697 break;
1698
252b5132
RH		 1699 case 'I':
1700 if (opP->mode != CONTROL
1701 || opP->reg < COP0
1702 || opP->reg > COP7)
1703 losing++;
1704 break;
1705
fd99574b
NC		 1706 case 'i':
1707 if (opP->mode != LSH && opP->mode != RSH)
1708 losing++;
1709 break;
1710
252b5132
RH		 1711 case 'J':
1712 if (opP->mode != CONTROL
1713 || opP->reg < USP
0b2e31dc
NS		 1714 || opP->reg > last_movec_reg
1715 || !control_regs)
252b5132
RH		 1716 losing++;
1717 else
1718 {
1719 const enum m68k_register *rp;
0b2e31dc 1720
252b5132
RH		 1721 for (rp = control_regs; *rp; rp++)
1722 if (*rp == opP->reg)
1723 break;
1724 if (*rp == 0)
1725 losing++;
1726 }
1727 break;
1728
1729 case 'k':
1730 if (opP->mode != IMMED)
1731 losing++;
1732 break;
1733
1734 case 'l':
1735 case 'L':
1736 if (opP->mode == DREG
1737 || opP->mode == AREG
1738 || opP->mode == FPREG)
1739 {
1740 if (s[1] == '8')
1741 losing++;
1742 else
1743 {
1744 switch (opP->mode)
1745 {
1746 case DREG:
1747 opP->mask = 1 << (opP->reg - DATA0);
1748 break;
1749 case AREG:
1750 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1751 break;
1752 case FPREG:
1753 opP->mask = 1 << (opP->reg - FP0 + 16);
1754 break;
1755 default:
1756 abort ();
1757 }
1758 opP->mode = REGLST;
1759 }
1760 }
1761 else if (opP->mode == CONTROL)
1762 {
1763 if (s[1] != '8')
1764 losing++;
1765 else
1766 {
1767 switch (opP->reg)
1768 {
1769 case FPI:
1770 opP->mask = 1 << 24;
1771 break;
1772 case FPS:
1773 opP->mask = 1 << 25;
1774 break;
1775 case FPC:
1776 opP->mask = 1 << 26;
1777 break;
1778 default:
1779 losing++;
1780 break;
1781 }
1782 opP->mode = REGLST;
1783 }
1784 }
1785 else if (opP->mode != REGLST)
1786 losing++;
1787 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1788 losing++;
1789 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1790 losing++;
1791 break;
1792
1793 case 'M':
1794 if (opP->mode != IMMED)
1795 losing++;
1796 else if (opP->disp.exp.X_op != O_constant
1797 || ! issbyte (opP->disp.exp.X_add_number))
1798 losing++;
1799 else if (! m68k_quick
1800 && instring[3] != 'q'
1801 && instring[4] != 'q')
1802 losing++;
1803 break;
1804
1805 case 'O':
1806 if (opP->mode != DREG
1807 && opP->mode != IMMED
1808 && opP->mode != ABSL)
1809 losing++;
1810 break;
1811
1812 case 'Q':
1813 if (opP->mode != IMMED)
1814 losing++;
1815 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1816 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1817 losing++;
1818 else if (! m68k_quick
1819 && (strncmp (instring, "add", 3) == 0
1820 || strncmp (instring, "sub", 3) == 0)
1821 && instring[3] != 'q')
1822 losing++;
1823 break;
1824
1825 case 'R':
1826 if (opP->mode != DREG && opP->mode != AREG)
1827 losing++;
1828 break;
1829
1830 case 'r':
1831 if (opP->mode != AINDR
1832 && (opP->mode != BASE
1833 || (opP->reg != 0
1834 && opP->reg != ZADDR0)
1835 || opP->disp.exp.X_op != O_absent
1836 || ((opP->index.reg < DATA0
1837 || opP->index.reg > DATA7)
1838 && (opP->index.reg < ADDR0
1839 || opP->index.reg > ADDR7))
1840 || opP->index.size != SIZE_UNSPEC
1841 || opP->index.scale != 1))
1842 losing++;
1843 break;
1844
1845 case 's':
1846 if (opP->mode != CONTROL
1847 || ! (opP->reg == FPI
1848 || opP->reg == FPS
1849 || opP->reg == FPC))
1850 losing++;
1851 break;
1852
1853 case 'S':
1854 if (opP->mode != CONTROL || opP->reg != SR)
1855 losing++;
1856 break;
1857
1858 case 't':
1859 if (opP->mode != IMMED)
1860 losing++;
1861 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1862 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1863 losing++;
1864 break;
1865
1866 case 'U':
1867 if (opP->mode != CONTROL || opP->reg != USP)
1868 losing++;
1869 break;
1870
3e602632
NC		 1871 case 'x':
1872 if (opP->mode != IMMED)
1873 losing++;
1874 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1875 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1876 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1877 losing++;
1878 break;
1879
252b5132
RH		 1880 /* JF these are out of order. We could put them
1881 in order if we were willing to put up with
1882 bunches of #ifdef m68851s in the code.
1883
1884 Don't forget that you need these operands
1885 to use 68030 MMU instructions. */
1886#ifndef NO_68851
36759679 1887 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1888 case '|':
1889 if (opP->mode == CONTROL
1890 || opP->mode == FPREG
1891 || opP->mode == DREG
1892 || opP->mode == AREG
1893 || opP->mode == REGLST)
1894 losing++;
1895 /* We should accept immediate operands, but they
1896 supposedly have to be quad word, and we don't
1897 handle that. I would like to see what a Motorola
1898 assembler does before doing something here. */
1899 if (opP->mode == IMMED)
1900 losing++;
1901 break;
1902
1903 case 'f':
1904 if (opP->mode != CONTROL
1905 || (opP->reg != SFC && opP->reg != DFC))
1906 losing++;
1907 break;
1908
1909 case '0':
1910 if (opP->mode != CONTROL || opP->reg != TC)
1911 losing++;
1912 break;
1913
1914 case '1':
1915 if (opP->mode != CONTROL || opP->reg != AC)
1916 losing++;
1917 break;
1918
1919 case '2':
1920 if (opP->mode != CONTROL
1921 || (opP->reg != CAL
1922 && opP->reg != VAL
1923 && opP->reg != SCC))
1924 losing++;
1925 break;
1926
1927 case 'V':
1928 if (opP->mode != CONTROL
1929 || opP->reg != VAL)
1930 losing++;
1931 break;
1932
1933 case 'W':
1934 if (opP->mode != CONTROL
1935 || (opP->reg != DRP
1936 && opP->reg != SRP
1937 && opP->reg != CRP))
1938 losing++;
1939 break;
1940
3e602632
NC		 1941 case 'w':
1942 switch (opP->mode)
1943 {
1944 case IMMED:
1945 case ABSL:
1946 case AREG:
1947 case DREG:
1948 case FPREG:
1949 case CONTROL:
1950 case POST:
1951 case PRE:
1952 case REGLST:
1953 losing++;
1954 break;
1955 default:
1956 break;
1957 }
1958 break;
1959
252b5132
RH		 1960 case 'X':
1961 if (opP->mode != CONTROL
1962 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1963 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1964 losing++;
1965 break;
1966
1967 case 'Y':
1968 if (opP->mode != CONTROL || opP->reg != PSR)
1969 losing++;
1970 break;
1971
1972 case 'Z':
1973 if (opP->mode != CONTROL || opP->reg != PCSR)
1974 losing++;
1975 break;
1976#endif
1977 case 'c':
1978 if (opP->mode != CONTROL
1979 || (opP->reg != NC
1980 && opP->reg != IC
1981 && opP->reg != DC
1982 && opP->reg != BC))
36759679 1983 losing++;
252b5132
RH		 1984 break;
1985
1986 case '_':
1987 if (opP->mode != ABSL)
1988 ++losing;
1989 break;
1990
6da466c7
ILT		 1991 case 'u':
1992 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1993 losing++;
1994 /* FIXME: kludge instead of fixing parser:
1995 upper/lower registers are *not* CONTROL
92774660 1996 registers, but ordinary ones. */
6da466c7
ILT		 1997 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1998 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1999 opP->mode = DREG;
2000 else
2001 opP->mode = AREG;
2002 break;
2003
3e602632
NC		 2004 case 'y':
2005 if (!(opP->mode == AINDR
31302357
AS		 2006 || (opP->mode == DISP
2007 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2008 losing++;
2009 break;
2010
2011 case 'z':
2012 if (!(opP->mode == AINDR || opP->mode == DISP))
2013 losing++;
2014 break;
2015
252b5132
RH		 2016 default:
2017 abort ();
36759679 2018 }
252b5132
RH		 2019
2020 if (losing)
2021 break;
36759679 2022 }
03b13e59
NC		 2023
2024 /* Since we have found the correct instruction, copy
2025 in the modifications that we may have made. */
2026 if (!losing)
2027 for (i = 0; i < opsfound; i++)
2028 the_ins.operands[i] = operands_backup[i];
36759679 2029 }
252b5132
RH		 2030
2031 if (!losing)
36759679 2032 break;
252b5132
RH		 2033
2034 opcode = opcode->m_next;
2035
2036 if (!opcode)
2037 {
2038 if (ok_arch
2039 && !(ok_arch & current_architecture))
2040 {
6d89cc8f
NS		 2041 const struct m68k_cpu *cpu;
2042 int any = 0;
2043 size_t space = 400;
2044 char *buf = xmalloc (space + 1);
2045 size_t len;
2046 int paren = 1;
2047
2048 the_ins.error = buf;
2049 /* Make sure there's a NUL at the end of the buffer -- strncpy
2050 won't write one when it runs out of buffer */
2051 buf[space] = 0;
2052#define APPEND(STRING) \
2053 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2054
2055 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2056 switch (ok_arch)
2057 {
6b6e92f4 2058 case mcfisa_a:
6d89cc8f 2059 APPEND (_("ColdFire ISA_A"));
6b6e92f4
NC		 2060 break;
2061 case mcfhwdiv:
6d89cc8f 2062 APPEND (_("ColdFire hardware divide"));
6b6e92f4
NC		 2063 break;
2064 case mcfisa_aa:
6d89cc8f 2065 APPEND (_("ColdFire ISA_A+"));
6b6e92f4
NC		 2066 break;
2067 case mcfisa_b:
6d89cc8f 2068 APPEND (_("ColdFire ISA_B"));
6b6e92f4 2069 break;
3e602632 2070 case cfloat:
6d89cc8f 2071 APPEND (_("ColdFire fpu"));
3e602632 2072 break;
252b5132 2073 case mfloat:
6d89cc8f 2074 APPEND (_("M68K fpu"));
252b5132
RH		 2075 break;
2076 case mmmu:
6d89cc8f 2077 APPEND (_("M68K mmu"));
252b5132
RH		 2078 break;
2079 case m68020up:
6d89cc8f 2080 APPEND (_("68020 or higher"));
252b5132
RH		 2081 break;
2082 case m68000up:
6d89cc8f 2083 APPEND (_("68000 or higher"));
252b5132
RH		 2084 break;
2085 case m68010up:
6d89cc8f 2086 APPEND (_("68010 or higher"));
252b5132
RH		 2087 break;
2088 default:
6d89cc8f
NS		 2089 paren = 0;
2090 }
2091 if (paren)
2092 APPEND (" (");
6b6e92f4 2093
6d89cc8f
NS		 2094 for (cpu = m68k_cpus; cpu->name; cpu++)
2095 if (!cpu->alias && (cpu->arch & ok_arch))
2096 {
2097 const struct m68k_cpu *alias;
869ddf2a
NS		 2098 int seen_master = 0;
2099
6d89cc8f
NS		 2100 if (any)
2101 APPEND (", ");
2102 any = 0;
2103 APPEND (cpu->name);
869ddf2a
NS		 2104 for (alias = cpu; alias != m68k_cpus; alias--)
2105 if (alias[-1].alias >= 0)
2106 break;
2107 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2108 {
869ddf2a
NS		 2109 if (!alias->alias)
2110 seen_master = 1;
2111 else
2112 {
2113 if (any)
2114 APPEND (", ");
2115 else
2116 APPEND (" [");
2117 APPEND (alias->name);
2118 any = 1;
2119 }
6d89cc8f 2120 }
869ddf2a
NS		 2121 if (any)
2122 APPEND ("]");
6d89cc8f 2123 any = 1;
252b5132 2124 }
6d89cc8f
NS		 2125 if (paren)
2126 APPEND (")");
2127#undef APPEND
2128 if (!space)
2129 {
2130 /* we ran out of space, so replace the end of the list
2131 with ellipsis. */
2132 buf -= 4;
2133 while (*buf != ' ')
2134 buf--;
2135 strcpy (buf, " ...");
252b5132 2136 }
252b5132
RH		 2137 }
2138 else
2139 the_ins.error = _("operands mismatch");
2140 return;
36759679 2141 }
252b5132
RH		 2142
2143 losing = 0;
2144 }
2145
36759679 2146 /* Now assemble it. */
252b5132
RH		 2147 the_ins.args = opcode->m_operands;
2148 the_ins.numargs = opcode->m_opnum;
2149 the_ins.numo = opcode->m_codenum;
2150 the_ins.opcode[0] = getone (opcode);
2151 the_ins.opcode[1] = gettwo (opcode);
2152
2153 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2154 {
2155 /* This switch is a doozy.
31302357 2156 Watch the first step; its a big one! */
252b5132
RH		 2157 switch (s[0])
2158 {
2159
2160 case '*':
2161 case '~':
2162 case '%':
2163 case ';':
2164 case '@':
2165 case '!':
2166 case '&':
2167 case '$':
2168 case '?':
2169 case '/':
2170 case '<':
2171 case '>':
3e602632 2172 case 'b':
252b5132
RH		 2173 case 'm':
2174 case 'n':
2175 case 'o':
2176 case 'p':
2177 case 'q':
2178 case 'v':
3e602632
NC		 2179 case 'w':
2180 case 'y':
2181 case 'z':
fd99574b 2182 case '4':
252b5132
RH		 2183#ifndef NO_68851
2184 case '|':
2185#endif
2186 switch (opP->mode)
2187 {
2188 case IMMED:
2189 tmpreg = 0x3c; /* 7.4 */
2190 if (strchr ("bwl", s[1]))
3e602632 2191 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2192 else
2193 nextword = get_num (&opP->disp, 0);
2194 if (isvar (&opP->disp))
2195 add_fix (s[1], &opP->disp, 0, 0);
2196 switch (s[1])
2197 {
2198 case 'b':
2199 if (!isbyte (nextword))
2200 opP->error = _("operand out of range");
2201 addword (nextword);
2202 baseo = 0;
2203 break;
2204 case 'w':
2205 if (!isword (nextword))
2206 opP->error = _("operand out of range");
2207 addword (nextword);
2208 baseo = 0;
2209 break;
2210 case 'W':
2211 if (!issword (nextword))
2212 opP->error = _("operand out of range");
2213 addword (nextword);
2214 baseo = 0;
2215 break;
2216 case 'l':
2217 addword (nextword >> 16);
2218 addword (nextword);
2219 baseo = 0;
2220 break;
2221
2222 case 'f':
2223 baseo = 2;
2224 outro = 8;
2225 break;
2226 case 'F':
2227 baseo = 4;
2228 outro = 11;
2229 break;
2230 case 'x':
2231 baseo = 6;
2232 outro = 15;
2233 break;
2234 case 'p':
2235 baseo = 6;
2236 outro = -1;
2237 break;
2238 default:
2239 abort ();
2240 }
2241 if (!baseo)
2242 break;
2243
36759679 2244 /* We gotta put out some float. */
252b5132
RH		 2245 if (op (&opP->disp) != O_big)
2246 {
2247 valueT val;
2248 int gencnt;
2249
2250 /* Can other cases happen here? */
2251 if (op (&opP->disp) != O_constant)
2252 abort ();
2253
2254 val = (valueT) offs (&opP->disp);
2255 gencnt = 0;
2256 do
2257 {
2258 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2259 val >>= LITTLENUM_NUMBER_OF_BITS;
2260 ++gencnt;
2261 }
2262 while (val != 0);
2263 offs (&opP->disp) = gencnt;
2264 }
2265 if (offs (&opP->disp) > 0)
2266 {
2267 if (offs (&opP->disp) > baseo)
2268 {
2269 as_warn (_("Bignum too big for %c format; truncated"),
2270 s[1]);
2271 offs (&opP->disp) = baseo;
2272 }
2273 baseo -= offs (&opP->disp);
2274 while (baseo--)
2275 addword (0);
2276 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2277 offs (&opP->disp)--;
2278 --wordp)
2279 addword (*wordp);
2280 break;
2281 }
2282 gen_to_words (words, baseo, (long) outro);
2283 for (wordp = words; baseo--; wordp++)
2284 addword (*wordp);
2285 break;
2286 case DREG:
2287 tmpreg = opP->reg - DATA; /* 0.dreg */
2288 break;
2289 case AREG:
2290 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2291 break;
2292 case AINDR:
2293 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2294 break;
2295 case ADEC:
2296 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2297 break;
2298 case AINC:
2299 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2300 break;
2301 case DISP:
2302
3e602632 2303 nextword = get_num (&opP->disp, 90);
252b5132 2304
580b9172
NC		 2305 /* Convert mode 5 addressing with a zero offset into
2306 mode 2 addressing to reduce the instruction size by a
2307 word. */
2308 if (! isvar (&opP->disp)
2309 && (nextword == 0)
2310 && (opP->disp.size == SIZE_UNSPEC)
2311 && (opP->reg >= ADDR0)
2312 && (opP->reg <= ADDR7))
2313 {
2314 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2315 break;
2316 }
2317
252b5132
RH		 2318 if (opP->reg == PC
2319 && ! isvar (&opP->disp)
2320 && m68k_abspcadd)
2321 {
2322 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2323 opP->disp.exp.X_add_symbol =
2324 section_symbol (absolute_section);
252b5132
RH		 2325 }
2326
36759679 2327 /* Force into index mode. Hope this works. */
252b5132
RH		 2328
2329 /* We do the first bit for 32-bit displacements, and the
2330 second bit for 16 bit ones. It is possible that we
2331 should make the default be WORD instead of LONG, but
2332 I think that'd break GCC, so we put up with a little
2333 inefficiency for the sake of working output. */
2334
2335 if (!issword (nextword)
2336 || (isvar (&opP->disp)
2337 && ((opP->disp.size == SIZE_UNSPEC
2338 && flag_short_refs == 0
2339 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2340 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2341 || opP->disp.size == SIZE_LONG)))
2342 {
2343 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2344 || arch_coldfire_p (current_architecture))
252b5132
RH		 2345 opP->error =
2346 _("displacement too large for this architecture; needs 68020 or higher");
2347 if (opP->reg == PC)
2348 tmpreg = 0x3B; /* 7.3 */
2349 else
2350 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2351 if (isvar (&opP->disp))
2352 {
2353 if (opP->reg == PC)
2354 {
2355 if (opP->disp.size == SIZE_LONG
2356#ifdef OBJ_ELF
2357 /* If the displacement needs pic
2358 relocation it cannot be relaxed. */
2359 || opP->disp.pic_reloc != pic_none
2360#endif
2361 )
2362 {
2363 addword (0x0170);
2364 add_fix ('l', &opP->disp, 1, 2);
2365 }
2366 else
2367 {
2368 add_frag (adds (&opP->disp),
bd17c2c3 2369 SEXT (offs (&opP->disp)),
151337e8 2370 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2371 break;
2372 }
2373 }
2374 else
2375 {
2376 addword (0x0170);
2377 add_fix ('l', &opP->disp, 0, 0);
2378 }
2379 }
2380 else
2381 addword (0x0170);
2382 addword (nextword >> 16);
2383 }
2384 else
2385 {
2386 if (opP->reg == PC)
2387 tmpreg = 0x3A; /* 7.2 */
2388 else
2389 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2390
2391 if (isvar (&opP->disp))
2392 {
2393 if (opP->reg == PC)
2394 {
2395 add_fix ('w', &opP->disp, 1, 0);
2396 }
2397 else
2398 add_fix ('w', &opP->disp, 0, 0);
2399 }
2400 }
2401 addword (nextword);
2402 break;
2403
2404 case POST:
2405 case PRE:
2406 case BASE:
2407 nextword = 0;
3e602632 2408 baseo = get_num (&opP->disp, 90);
252b5132 2409 if (opP->mode == POST || opP->mode == PRE)
3e602632 2410 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2411 /* Figure out the `addressing mode'.
2412 Also turn on the BASE_DISABLE bit, if needed. */
2413 if (opP->reg == PC || opP->reg == ZPC)
2414 {
2415 tmpreg = 0x3b; /* 7.3 */
2416 if (opP->reg == ZPC)
2417 nextword |= 0x80;
2418 }
2419 else if (opP->reg == 0)
2420 {
2421 nextword |= 0x80;
2422 tmpreg = 0x30; /* 6.garbage */
2423 }
2424 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2425 {
2426 nextword |= 0x80;
2427 tmpreg = 0x30 + opP->reg - ZADDR0;
2428 }
2429 else
2430 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2431
2432 siz1 = opP->disp.size;
2433 if (opP->mode == POST || opP->mode == PRE)
2434 siz2 = opP->odisp.size;
2435 else
2436 siz2 = SIZE_UNSPEC;
2437
36759679 2438 /* Index register stuff. */
252b5132
RH		 2439 if (opP->index.reg != 0
2440 && opP->index.reg >= DATA
2441 && opP->index.reg <= ADDR7)
2442 {
2443 nextword |= (opP->index.reg - DATA) << 12;
2444
2445 if (opP->index.size == SIZE_LONG
2446 || (opP->index.size == SIZE_UNSPEC
2447 && m68k_index_width_default == SIZE_LONG))
2448 nextword |= 0x800;
2449
92774660 2450 if ((opP->index.scale != 1
252b5132 2451 && cpu_of_arch (current_architecture) < m68020)
92774660 2452 || (opP->index.scale == 8
3e602632 2453 && (arch_coldfire_p (current_architecture)
6b6e92f4 2454 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2455 {
2456 opP->error =
2457 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2458 }
2459
6da466c7
ILT		 2460 if (arch_coldfire_p (current_architecture)
2461 && opP->index.size == SIZE_WORD)
2462 opP->error = _("invalid index size for coldfire");
2463
252b5132
RH		 2464 switch (opP->index.scale)
2465 {
2466 case 1:
2467 break;
2468 case 2:
2469 nextword |= 0x200;
2470 break;
2471 case 4:
2472 nextword |= 0x400;
2473 break;
2474 case 8:
2475 nextword |= 0x600;
2476 break;
2477 default:
2478 abort ();
2479 }
2480 /* IF its simple,
2481 GET US OUT OF HERE! */
2482
2483 /* Must be INDEX, with an index register. Address
2484 register cannot be ZERO-PC, and either :b was
2485 forced, or we know it will fit. For a 68000 or
2486 68010, force this mode anyways, because the
2487 larger modes aren't supported. */
2488 if (opP->mode == BASE
2489 && ((opP->reg >= ADDR0
2490 && opP->reg <= ADDR7)
2491 || opP->reg == PC))
2492 {
2493 if (siz1 == SIZE_BYTE
2494 || cpu_of_arch (current_architecture) < m68020
6da466c7 2495 || arch_coldfire_p (current_architecture)
252b5132
RH		 2496 || (siz1 == SIZE_UNSPEC
2497 && ! isvar (&opP->disp)
2498 && issbyte (baseo)))
2499 {
2500 nextword += baseo & 0xff;
2501 addword (nextword);
2502 if (isvar (&opP->disp))
2503 {
2504 /* Do a byte relocation. If it doesn't
2505 fit (possible on m68000) let the
2506 fixup processing complain later. */
2507 if (opP->reg == PC)
2508 add_fix ('B', &opP->disp, 1, 1);
2509 else
2510 add_fix ('B', &opP->disp, 0, 0);
2511 }
2512 else if (siz1 != SIZE_BYTE)
2513 {
2514 if (siz1 != SIZE_UNSPEC)
2515 as_warn (_("Forcing byte displacement"));
2516 if (! issbyte (baseo))
2517 opP->error = _("byte displacement out of range");
2518 }
2519
2520 break;
2521 }
2522 else if (siz1 == SIZE_UNSPEC
2523 && opP->reg == PC
2524 && isvar (&opP->disp)
2525 && subs (&opP->disp) == NULL
2526#ifdef OBJ_ELF
2527 /* If the displacement needs pic
2528 relocation it cannot be relaxed. */
2529 && opP->disp.pic_reloc == pic_none
2530#endif
2531 )
2532 {
2533 /* The code in md_convert_frag_1 needs to be
2534 able to adjust nextword. Call frag_grow
2535 to ensure that we have enough space in
2536 the frag obstack to make all the bytes
2537 contiguous. */
2538 frag_grow (14);
8a104df9
KH		 2539 nextword += baseo & 0xff;
2540 addword (nextword);
bd17c2c3
AM		 2541 add_frag (adds (&opP->disp),
2542 SEXT (offs (&opP->disp)),
8a104df9 2543 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2544
2545 break;
8a104df9 2546 }
252b5132
RH		 2547 }
2548 }
2549 else
2550 {
36759679 2551 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2552 if (opP->index.reg >= ZDATA0
2553 && opP->index.reg <= ZDATA7)
2554 nextword |= (opP->index.reg - ZDATA0) << 12;
2555 else if (opP->index.reg >= ZADDR0
2556 || opP->index.reg <= ZADDR7)
2557 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2558 }
2559
2560 /* It isn't simple. */
2561
2562 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2563 || arch_coldfire_p (current_architecture))
252b5132
RH		 2564 opP->error =
2565 _("invalid operand mode for this architecture; needs 68020 or higher");
2566
2567 nextword |= 0x100;
2568 /* If the guy specified a width, we assume that it is
2569 wide enough. Maybe it isn't. If so, we lose. */
2570 switch (siz1)
2571 {
2572 case SIZE_UNSPEC:
2573 if (isvar (&opP->disp)
2574 ? m68k_rel32
2575 : ! issword (baseo))
2576 {
2577 siz1 = SIZE_LONG;
2578 nextword |= 0x30;
2579 }
2580 else if (! isvar (&opP->disp) && baseo == 0)
2581 nextword |= 0x10;
2582 else
2583 {
2584 nextword |= 0x20;
2585 siz1 = SIZE_WORD;
2586 }
2587 break;
2588 case SIZE_BYTE:
2589 as_warn (_(":b not permitted; defaulting to :w"));
2590 /* Fall through. */
2591 case SIZE_WORD:
2592 nextword |= 0x20;
2593 break;
2594 case SIZE_LONG:
2595 nextword |= 0x30;
2596 break;
2597 }
2598
67c1ffbe 2599 /* Figure out inner displacement stuff. */
252b5132
RH		 2600 if (opP->mode == POST || opP->mode == PRE)
2601 {
2602 if (cpu_of_arch (current_architecture) & cpu32)
2603 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2604 switch (siz2)
2605 {
2606 case SIZE_UNSPEC:
2607 if (isvar (&opP->odisp)
2608 ? m68k_rel32
2609 : ! issword (outro))
2610 {
2611 siz2 = SIZE_LONG;
2612 nextword |= 0x3;
2613 }
2614 else if (! isvar (&opP->odisp) && outro == 0)
2615 nextword |= 0x1;
2616 else
2617 {
2618 nextword |= 0x2;
2619 siz2 = SIZE_WORD;
2620 }
2621 break;
2622 case 1:
2623 as_warn (_(":b not permitted; defaulting to :w"));
2624 /* Fall through. */
2625 case 2:
2626 nextword |= 0x2;
2627 break;
2628 case 3:
2629 nextword |= 0x3;
2630 break;
2631 }
2632 if (opP->mode == POST
2633 && (nextword & 0x40) == 0)
2634 nextword |= 0x04;
2635 }
2636 addword (nextword);
2637
2638 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2639 {
2640 if (opP->reg == PC || opP->reg == ZPC)
2641 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2642 else
2643 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2644 }
2645 if (siz1 == SIZE_LONG)
2646 addword (baseo >> 16);
2647 if (siz1 != SIZE_UNSPEC)
2648 addword (baseo);
2649
2650 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2651 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2652 if (siz2 == SIZE_LONG)
2653 addword (outro >> 16);
2654 if (siz2 != SIZE_UNSPEC)
2655 addword (outro);
2656
2657 break;
2658
2659 case ABSL:
3e602632 2660 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2661 switch (opP->disp.size)
2662 {
2663 default:
2664 abort ();
2665 case SIZE_UNSPEC:
2666 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2667 {
2668 tmpreg = 0x38; /* 7.0 */
2669 addword (nextword);
2670 break;
2671 }
252b5132
RH		 2672 if (isvar (&opP->disp)
2673 && !subs (&opP->disp)
2674 && adds (&opP->disp)
2675#ifdef OBJ_ELF
2676 /* If the displacement needs pic relocation it
2677 cannot be relaxed. */
2678 && opP->disp.pic_reloc == pic_none
2679#endif
252b5132
RH		 2680 && !flag_long_jumps
2681 && !strchr ("~%&$?", s[0]))
2682 {
2683 tmpreg = 0x3A; /* 7.2 */
2684 add_frag (adds (&opP->disp),
bd17c2c3 2685 SEXT (offs (&opP->disp)),
151337e8 2686 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2687 break;
2688 }
36759679 2689 /* Fall through into long. */
252b5132
RH		 2690 case SIZE_LONG:
2691 if (isvar (&opP->disp))
2692 add_fix ('l', &opP->disp, 0, 0);
2693
2694 tmpreg = 0x39;/* 7.1 mode */
2695 addword (nextword >> 16);
2696 addword (nextword);
2697 break;
2698
2699 case SIZE_BYTE:
2700 as_bad (_("unsupported byte value; use a different suffix"));
2701 /* Fall through. */
36759679
NC		 2702
2703 case SIZE_WORD:
252b5132
RH		 2704 if (isvar (&opP->disp))
2705 add_fix ('w', &opP->disp, 0, 0);
2706
2707 tmpreg = 0x38;/* 7.0 mode */
2708 addword (nextword);
2709 break;
2710 }
2711 break;
2712 case CONTROL:
2713 case FPREG:
2714 default:
2715 as_bad (_("unknown/incorrect operand"));
bc805888 2716 /* abort (); */
252b5132 2717 }
fd99574b
NC		 2718
2719 /* If s[0] is '4', then this is for the mac instructions
2720 that can have a trailing_ampersand set. If so, set 0x100
2721 bit on tmpreg so install_gen_operand can check for it and
2722 set the appropriate bit (word2, bit 5). */
2723 if (s[0] == '4')
2724 {
2725 if (opP->trailing_ampersand)
2726 tmpreg |= 0x100;
2727 }
252b5132
RH		 2728 install_gen_operand (s[1], tmpreg);
2729 break;
2730
2731 case '#':
2732 case '^':
2733 switch (s[1])
2734 { /* JF: I hate floating point! */
2735 case 'j':
2736 tmpreg = 70;
2737 break;
2738 case '8':
2739 tmpreg = 20;
2740 break;
2741 case 'C':
2742 tmpreg = 50;
2743 break;
2744 case '3':
2745 default:
3e602632 2746 tmpreg = 90;
252b5132
RH		 2747 break;
2748 }
2749 tmpreg = get_num (&opP->disp, tmpreg);
2750 if (isvar (&opP->disp))
2751 add_fix (s[1], &opP->disp, 0, 0);
2752 switch (s[1])
2753 {
2754 case 'b': /* Danger: These do no check for
2755 certain types of overflow.
2756 user beware! */
2757 if (!isbyte (tmpreg))
2758 opP->error = _("out of range");
2759 insop (tmpreg, opcode);
2760 if (isvar (&opP->disp))
2761 the_ins.reloc[the_ins.nrel - 1].n =
2762 (opcode->m_codenum) * 2 + 1;
2763 break;
2764 case 'B':
2765 if (!issbyte (tmpreg))
2766 opP->error = _("out of range");
2767 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2768 if (isvar (&opP->disp))
2769 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2770 break;
2771 case 'w':
2772 if (!isword (tmpreg))
2773 opP->error = _("out of range");
2774 insop (tmpreg, opcode);
2775 if (isvar (&opP->disp))
2776 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2777 break;
2778 case 'W':
2779 if (!issword (tmpreg))
2780 opP->error = _("out of range");
2781 insop (tmpreg, opcode);
2782 if (isvar (&opP->disp))
2783 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2784 break;
2785 case 'l':
2786 /* Because of the way insop works, we put these two out
2787 backwards. */
2788 insop (tmpreg, opcode);
2789 insop (tmpreg >> 16, opcode);
2790 if (isvar (&opP->disp))
2791 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2792 break;
2793 case '3':
2794 tmpreg &= 0xFF;
2795 case '8':
2796 case 'C':
2797 case 'j':
2798 install_operand (s[1], tmpreg);
2799 break;
2800 default:
2801 abort ();
2802 }
2803 break;
2804
2805 case '+':
2806 case '-':
2807 case 'A':
2808 case 'a':
2809 install_operand (s[1], opP->reg - ADDR);
2810 break;
2811
2812 case 'B':
3e602632 2813 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2814 switch (s[1])
2815 {
2816 case 'B':
8390138c 2817 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2818 break;
2819 case 'W':
2820 add_fix ('w', &opP->disp, 1, 0);
2821 addword (0);
2822 break;
2823 case 'L':
2824 long_branch:
151337e8 2825 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2826 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2827 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2828 add_fix ('l', &opP->disp, 1, 0);
2829 addword (0);
2830 addword (0);
2831 break;
2832 case 'g':
36759679 2833 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2834 goto long_branch;
2835
2836#ifdef OBJ_ELF
2837 /* If the displacement needs pic relocation it cannot be
2838 relaxed. */
2839 if (opP->disp.pic_reloc != pic_none)
2840 goto long_branch;
2841#endif
252b5132 2842 /* This could either be a symbol, or an absolute
151337e8
NC		 2843 address. If it's an absolute address, turn it into
2844 an absolute jump right here and keep it out of the
2845 relaxer. */
2846 if (adds (&opP->disp) == 0)
2847 {
2848 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2849 the_ins.opcode[0] = 0x4EF9;
151337e8 2850 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2851 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2852 else /* jCC */
2853 {
2854 the_ins.opcode[0] ^= 0x0100;
2855 the_ins.opcode[0] |= 0x0006;
18566f55 2856 addword (0x4EF9);
151337e8
NC		 2857 }
2858 add_fix ('l', &opP->disp, 0, 0);
2859 addword (0);
2860 addword (0);
2861 break;
2862 }
2863
2864 /* Now we know it's going into the relaxer. Now figure
2865 out which mode. We try in this order of preference:
2866 long branch, absolute jump, byte/word branches only. */
2867 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2868 add_frag (adds (&opP->disp),
2869 SEXT (offs (&opP->disp)),
151337e8
NC		 2870 TAB (BRANCHBWL, SZ_UNDEF));
2871 else if (! flag_keep_pcrel)
2872 {
2873 if ((the_ins.opcode[0] == 0x6000)
2874 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2875 add_frag (adds (&opP->disp),
2876 SEXT (offs (&opP->disp)),
151337e8
NC		 2877 TAB (BRABSJUNC, SZ_UNDEF));
2878 else
bd17c2c3
AM		 2879 add_frag (adds (&opP->disp),
2880 SEXT (offs (&opP->disp)),
151337e8
NC		 2881 TAB (BRABSJCOND, SZ_UNDEF));
2882 }
252b5132 2883 else
bd17c2c3
AM		 2884 add_frag (adds (&opP->disp),
2885 SEXT (offs (&opP->disp)),
151337e8 2886 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2887 break;
2888 case 'w':
2889 if (isvar (&opP->disp))
2890 {
151337e8
NC		 2891 /* Check for DBcc instructions. We can relax them,
2892 but only if we have long branches and/or absolute
2893 jumps. */
2894 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2895 && (HAVE_LONG_BRANCH (current_architecture)
2896 || (! flag_keep_pcrel)))
252b5132 2897 {
151337e8 2898 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2899 add_frag (adds (&opP->disp),
2900 SEXT (offs (&opP->disp)),
151337e8
NC		 2901 TAB (DBCCLBR, SZ_UNDEF));
2902 else
bd17c2c3
AM		 2903 add_frag (adds (&opP->disp),
2904 SEXT (offs (&opP->disp)),
151337e8 2905 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2906 break;
2907 }
252b5132
RH		 2908 add_fix ('w', &opP->disp, 1, 0);
2909 }
2910 addword (0);
2911 break;
36759679 2912 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2913 add_fix ('l', &opP->disp, 1, 0);
2914 addword (0);
2915 addword (0);
2916 break;
36759679 2917 case 'c': /* Var size Coprocesssor branches. */
151337e8 2918 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2919 {
252b5132
RH		 2920 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2921 add_fix ('l', &opP->disp, 1, 0);
2922 addword (0);
2923 addword (0);
2924 }
151337e8 2925 else
bd17c2c3
AM		 2926 add_frag (adds (&opP->disp),
2927 SEXT (offs (&opP->disp)),
151337e8 2928 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2929 break;
2930 default:
2931 abort ();
2932 }
2933 break;
2934
36759679 2935 case 'C': /* Ignore it. */
252b5132
RH		 2936 break;
2937
36759679 2938 case 'd': /* JF this is a kludge. */
252b5132 2939 install_operand ('s', opP->reg - ADDR);
3e602632 2940 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2941 if (!issword (tmpreg))
2942 {
2943 as_warn (_("Expression out of range, using 0"));
2944 tmpreg = 0;
2945 }
2946 addword (tmpreg);
2947 break;
2948
2949 case 'D':
2950 install_operand (s[1], opP->reg - DATA);
2951 break;
2952
fd99574b
NC		 2953 case 'e': /* EMAC ACCx, reg/reg. */
2954 install_operand (s[1], opP->reg - ACC);
2955 break;
2956
36759679 2957 case 'E': /* Ignore it. */
6da466c7
ILT		 2958 break;
2959
252b5132
RH		 2960 case 'F':
2961 install_operand (s[1], opP->reg - FP0);
2962 break;
2963
fd99574b
NC		 2964 case 'g': /* EMAC ACCEXTx. */
2965 install_operand (s[1], opP->reg - ACCEXT01);
2966 break;
2967
36759679 2968 case 'G': /* Ignore it. */
6da466c7
ILT		 2969 case 'H':
2970 break;
2971
252b5132
RH		 2972 case 'I':
2973 tmpreg = opP->reg - COP0;
2974 install_operand (s[1], tmpreg);
2975 break;
2976
fd99574b
NC		 2977 case 'i': /* MAC/EMAC scale factor. */
2978 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2979 break;
2980
36759679 2981 case 'J': /* JF foo. */
252b5132
RH		 2982 switch (opP->reg)
2983 {
2984 case SFC:
2985 tmpreg = 0x000;
2986 break;
2987 case DFC:
2988 tmpreg = 0x001;
2989 break;
2990 case CACR:
2991 tmpreg = 0x002;
2992 break;
2993 case TC:
a8e24a56 2994 case ASID:
252b5132
RH		 2995 tmpreg = 0x003;
2996 break;
3e602632 2997 case ACR0:
252b5132
RH		 2998 case ITT0:
2999 tmpreg = 0x004;
3000 break;
3e602632 3001 case ACR1:
252b5132
RH		 3002 case ITT1:
3003 tmpreg = 0x005;
3004 break;
3e602632 3005 case ACR2:
252b5132
RH		 3006 case DTT0:
3007 tmpreg = 0x006;
3008 break;
3e602632 3009 case ACR3:
252b5132
RH		 3010 case DTT1:
3011 tmpreg = 0x007;
3012 break;
3013 case BUSCR:
a8e24a56 3014 case MMUBAR:
252b5132
RH		 3015 tmpreg = 0x008;
3016 break;
3017
3018 case USP:
3019 tmpreg = 0x800;
3020 break;
3021 case VBR:
3022 tmpreg = 0x801;
3023 break;
3024 case CAAR:
3025 tmpreg = 0x802;
3026 break;
3027 case MSP:
3028 tmpreg = 0x803;
3029 break;
3030 case ISP:
3031 tmpreg = 0x804;
3032 break;
3033 case MMUSR:
3034 tmpreg = 0x805;
3035 break;
3036 case URP:
3037 tmpreg = 0x806;
3038 break;
3039 case SRP:
3040 tmpreg = 0x807;
3041 break;
3042 case PCR:
3043 tmpreg = 0x808;
3044 break;
3045 case ROMBAR:
a8e24a56 3046 case ROMBAR0:
252b5132
RH		 3047 tmpreg = 0xC00;
3048 break;
3e602632
NC		 3049 case ROMBAR1:
3050 tmpreg = 0xC01;
3051 break;
3052 case FLASHBAR:
252b5132
RH		 3053 case RAMBAR0:
3054 tmpreg = 0xC04;
3055 break;
3e602632 3056 case RAMBAR:
252b5132
RH		 3057 case RAMBAR1:
3058 tmpreg = 0xC05;
3059 break;
3e602632
NC		 3060 case MPCR:
3061 tmpreg = 0xC0C;
3062 break;
3063 case EDRAMBAR:
3064 tmpreg = 0xC0D;
3065 break;
3066 case MBAR0:
e80e0390 3067 case MBAR2:
3e602632
NC		 3068 case SECMBAR:
3069 tmpreg = 0xC0E;
3070 break;
3071 case MBAR1:
252b5132
RH		 3072 case MBAR:
3073 tmpreg = 0xC0F;
3074 break;
3e602632
NC		 3075 case PCR1U0:
3076 tmpreg = 0xD02;
3077 break;
3078 case PCR1L0:
3079 tmpreg = 0xD03;
3080 break;
3081 case PCR2U0:
3082 tmpreg = 0xD04;
3083 break;
3084 case PCR2L0:
3085 tmpreg = 0xD05;
3086 break;
3087 case PCR3U0:
3088 tmpreg = 0xD06;
3089 break;
3090 case PCR3L0:
3091 tmpreg = 0xD07;
3092 break;
3093 case PCR1L1:
3094 tmpreg = 0xD0A;
3095 break;
3096 case PCR1U1:
3097 tmpreg = 0xD0B;
3098 break;
3099 case PCR2L1:
3100 tmpreg = 0xD0C;
3101 break;
3102 case PCR2U1:
3103 tmpreg = 0xD0D;
3104 break;
3105 case PCR3L1:
3106 tmpreg = 0xD0E;
3107 break;
3108 case PCR3U1:
3109 tmpreg = 0xD0F;
3110 break;
f7ec513b
KH		 3111 case CAC:
3112 tmpreg = 0xFFE;
3113 break;
3114 case MBB:
3115 tmpreg = 0xFFF;
3116 break;
252b5132
RH		 3117 default:
3118 abort ();
3119 }
3120 install_operand (s[1], tmpreg);
3121 break;
3122
3123 case 'k':
3124 tmpreg = get_num (&opP->disp, 55);
3125 install_operand (s[1], tmpreg & 0x7f);
3126 break;
3127
3128 case 'l':
3129 tmpreg = opP->mask;
3130 if (s[1] == 'w')
3131 {
3132 if (tmpreg & 0x7FF0000)
3133 as_bad (_("Floating point register in register list"));
3134 insop (reverse_16_bits (tmpreg), opcode);
3135 }
3136 else
3137 {
3138 if (tmpreg & 0x700FFFF)
3139 as_bad (_("Wrong register in floating-point reglist"));
3140 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3141 }
3142 break;
3143
3144 case 'L':
3145 tmpreg = opP->mask;
3146 if (s[1] == 'w')
3147 {
3148 if (tmpreg & 0x7FF0000)
3149 as_bad (_("Floating point register in register list"));
3150 insop (tmpreg, opcode);
3151 }
3152 else if (s[1] == '8')
3153 {
3154 if (tmpreg & 0x0FFFFFF)
3155 as_bad (_("incorrect register in reglist"));
3156 install_operand (s[1], tmpreg >> 24);
3157 }
3158 else
3159 {
3160 if (tmpreg & 0x700FFFF)
3161 as_bad (_("wrong register in floating-point reglist"));
3162 else
3163 install_operand (s[1], tmpreg >> 16);
3164 }
3165 break;
3166
3167 case 'M':
3168 install_operand (s[1], get_num (&opP->disp, 60));
3169 break;
3170
3171 case 'O':
3172 tmpreg = ((opP->mode == DREG)
8fce3f5e 3173 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3174 : (get_num (&opP->disp, 40) & 0x1F));
3175 install_operand (s[1], tmpreg);
3176 break;
3177
3178 case 'Q':
3179 tmpreg = get_num (&opP->disp, 10);
3180 if (tmpreg == 8)
3181 tmpreg = 0;
3182 install_operand (s[1], tmpreg);
3183 break;
3184
3185 case 'R':
3186 /* This depends on the fact that ADDR registers are eight
3187 more than their corresponding DATA regs, so the result
36759679 3188 will have the ADDR_REG bit set. */
252b5132
RH		 3189 install_operand (s[1], opP->reg - DATA);
3190 break;
3191
3192 case 'r':
3193 if (opP->mode == AINDR)
3194 install_operand (s[1], opP->reg - DATA);
3195 else
3196 install_operand (s[1], opP->index.reg - DATA);
3197 break;
3198
3199 case 's':
3200 if (opP->reg == FPI)
3201 tmpreg = 0x1;
3202 else if (opP->reg == FPS)
3203 tmpreg = 0x2;
3204 else if (opP->reg == FPC)
3205 tmpreg = 0x4;
3206 else
3207 abort ();
3208 install_operand (s[1], tmpreg);
3209 break;
3210
36759679 3211 case 'S': /* Ignore it. */
252b5132
RH		 3212 break;
3213
3214 case 'T':
3215 install_operand (s[1], get_num (&opP->disp, 30));
3216 break;
3217
36759679 3218 case 'U': /* Ignore it. */
252b5132
RH		 3219 break;
3220
3221 case 'c':
3222 switch (opP->reg)
3223 {
3224 case NC:
3225 tmpreg = 0;
3226 break;
3227 case DC:
3228 tmpreg = 1;
3229 break;
3230 case IC:
3231 tmpreg = 2;
3232 break;
3233 case BC:
3234 tmpreg = 3;
3235 break;
3236 default:
3237 as_fatal (_("failed sanity check"));
36759679 3238 } /* switch on cache token. */
252b5132
RH		 3239 install_operand (s[1], tmpreg);
3240 break;
3241#ifndef NO_68851
92774660 3242 /* JF: These are out of order, I fear. */
252b5132
RH		 3243 case 'f':
3244 switch (opP->reg)
3245 {
3246 case SFC:
3247 tmpreg = 0;
3248 break;
3249 case DFC:
3250 tmpreg = 1;
3251 break;
3252 default:
3253 abort ();
3254 }
3255 install_operand (s[1], tmpreg);
3256 break;
3257
3258 case '0':
3259 case '1':
3260 case '2':
3261 switch (opP->reg)
3262 {
3263 case TC:
3264 tmpreg = 0;
3265 break;
3266 case CAL:
3267 tmpreg = 4;
3268 break;
3269 case VAL:
3270 tmpreg = 5;
3271 break;
3272 case SCC:
3273 tmpreg = 6;
3274 break;
3275 case AC:
3276 tmpreg = 7;
3277 break;
3278 default:
3279 abort ();
3280 }
3281 install_operand (s[1], tmpreg);
3282 break;
3283
3284 case 'V':
3285 if (opP->reg == VAL)
3286 break;
3287 abort ();
3288
3289 case 'W':
3290 switch (opP->reg)
3291 {
3292 case DRP:
3293 tmpreg = 1;
3294 break;
3295 case SRP:
3296 tmpreg = 2;
3297 break;
3298 case CRP:
3299 tmpreg = 3;
3300 break;
3301 default:
3302 abort ();
3303 }
3304 install_operand (s[1], tmpreg);
3305 break;
3306
3307 case 'X':
3308 switch (opP->reg)
3309 {
3310 case BAD:
3311 case BAD + 1:
3312 case BAD + 2:
3313 case BAD + 3:
3314 case BAD + 4:
3315 case BAD + 5:
3316 case BAD + 6:
3317 case BAD + 7:
3318 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3319 break;
3320
3321 case BAC:
3322 case BAC + 1:
3323 case BAC + 2:
3324 case BAC + 3:
3325 case BAC + 4:
3326 case BAC + 5:
3327 case BAC + 6:
3328 case BAC + 7:
3329 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3330 break;
3331
3332 default:
3333 abort ();
3334 }
3335 install_operand (s[1], tmpreg);
3336 break;
3337 case 'Y':
3338 know (opP->reg == PSR);
3339 break;
3340 case 'Z':
3341 know (opP->reg == PCSR);
3342 break;
3343#endif /* m68851 */
3344 case '3':
3345 switch (opP->reg)
3346 {
3347 case TT0:
3348 tmpreg = 2;
3349 break;
3350 case TT1:
3351 tmpreg = 3;
3352 break;
3353 default:
3354 abort ();
3355 }
3356 install_operand (s[1], tmpreg);
3357 break;
3358 case 't':
3359 tmpreg = get_num (&opP->disp, 20);
3360 install_operand (s[1], tmpreg);
3361 break;
36759679 3362 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3363 if (isvar (&opP->disp))
3364 add_fix ('l', &opP->disp, 0, 0);
3e602632 3365 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3366 addword (tmpreg >> 16);
3367 addword (tmpreg & 0xFFFF);
3368 break;
6da466c7
ILT		 3369 case 'u':
3370 install_operand (s[1], opP->reg - DATA0L);
3371 opP->reg -= (DATA0L);
36759679 3372 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3373 break;
3e602632
NC		 3374 case 'x':
3375 tmpreg = get_num (&opP->disp, 80);
3376 if (tmpreg == -1)
3377 tmpreg = 0;
3378 install_operand (s[1], tmpreg);
3379 break;
252b5132
RH		 3380 default:
3381 abort ();
3382 }
3383 }
3384
3385 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3386 instruction, ready to be emitted. . . */
252b5132
RH		 3387}
3388
3389static int
31302357 3390reverse_16_bits (int in)
252b5132
RH		 3391{
3392 int out = 0;
3393 int n;
3394
3395 static int mask[16] =
3396 {
3397 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3398 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3399 };
3400 for (n = 0; n < 16; n++)
3401 {
3402 if (in & mask[n])
3403 out |= mask[15 - n];
3404 }
3405 return out;
3406} /* reverse_16_bits() */
3407
3408static int
31302357 3409reverse_8_bits (int in)
252b5132
RH		 3410{
3411 int out = 0;
3412 int n;
3413
3414 static int mask[8] =
3415 {
3416 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3417 };
3418
3419 for (n = 0; n < 8; n++)
3420 {
3421 if (in & mask[n])
3422 out |= mask[7 - n];
3423 }
3424 return out;
3425} /* reverse_8_bits() */
3426
3427/* Cause an extra frag to be generated here, inserting up to 10 bytes
3428 (that value is chosen in the frag_var call in md_assemble). TYPE
3429 is the subtype of the frag to be generated; its primary type is
3430 rs_machine_dependent.
3431
3432 The TYPE parameter is also used by md_convert_frag_1 and
3433 md_estimate_size_before_relax. The appropriate type of fixup will
3434 be emitted by md_convert_frag_1.
3435
3436 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3437static void
31302357 3438install_operand (int mode, int val)
252b5132
RH		 3439{
3440 switch (mode)
3441 {
3442 case 's':
36759679 3443 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3444 break;
3445 case 'd':
3446 the_ins.opcode[0] |= val << 9;
3447 break;
3448 case '1':
3449 the_ins.opcode[1] |= val << 12;
3450 break;
3451 case '2':
3452 the_ins.opcode[1] |= val << 6;
3453 break;
3454 case '3':
3455 the_ins.opcode[1] |= val;
3456 break;
3457 case '4':
3458 the_ins.opcode[2] |= val << 12;
3459 break;
3460 case '5':
3461 the_ins.opcode[2] |= val << 6;
3462 break;
3463 case '6':
3464 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3465 three words long! */
3466 the_ins.numo++;
3467 the_ins.opcode[2] |= val;
3468 break;
3469 case '7':
3470 the_ins.opcode[1] |= val << 7;
3471 break;
3472 case '8':
3473 the_ins.opcode[1] |= val << 10;
3474 break;
3475#ifndef NO_68851
3476 case '9':
3477 the_ins.opcode[1] |= val << 5;
3478 break;
3479#endif
3480
3481 case 't':
3482 the_ins.opcode[1] |= (val << 10) | (val << 7);
3483 break;
3484 case 'D':
3485 the_ins.opcode[1] |= (val << 12) | val;
3486 break;
3487 case 'g':
3488 the_ins.opcode[0] |= val = 0xff;
3489 break;
3490 case 'i':
3491 the_ins.opcode[0] |= val << 9;
3492 break;
3493 case 'C':
3494 the_ins.opcode[1] |= val;
3495 break;
3496 case 'j':
3497 the_ins.opcode[1] |= val;
36759679 3498 the_ins.numo++; /* What a hack. */
252b5132
RH		 3499 break;
3500 case 'k':
3501 the_ins.opcode[1] |= val << 4;
3502 break;
3503 case 'b':
3504 case 'w':
3505 case 'W':
3506 case 'l':
3507 break;
3508 case 'e':
3509 the_ins.opcode[0] |= (val << 6);
3510 break;
3511 case 'L':
3512 the_ins.opcode[1] = (val >> 16);
3513 the_ins.opcode[2] = val & 0xffff;
3514 break;
6da466c7
ILT		 3515 case 'm':
3516 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3517 the_ins.opcode[0] |= ((val & 0x7) << 9);
3518 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3519 break;
fd99574b 3520 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3521 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3522 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3523 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3524 break;
fd99574b 3525 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3526 the_ins.opcode[1] |= val << 12;
3527 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3528 break;
fd99574b 3529 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3530 the_ins.opcode[0] |= (val & 0xF);
3531 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3532 break;
fd99574b 3533 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3534 the_ins.opcode[1] |= (val & 0xF);
3535 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3536 break;
3537 case 'h':
3538 the_ins.opcode[1] |= ((val != 1) << 10);
3539 break;
fd99574b
NC		 3540 case 'F':
3541 the_ins.opcode[0] |= ((val & 0x3) << 9);
3542 break;
3543 case 'f':
3544 the_ins.opcode[0] |= ((val & 0x3) << 0);
3545 break;
be8c092b 3546 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3547 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3548 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3549 break;
be8c092b 3550 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3551 the_ins.opcode[0] |= ((val & 0x1) << 7);
3552 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3553 break;
3554 case 'I':
3555 the_ins.opcode[1] |= ((val & 0x3) << 9);
3556 break;
3557 case ']':
3558 the_ins.opcode[0] |= (val & 0x1) <<10;
3559 break;
252b5132
RH		 3560 case 'c':
3561 default:
3562 as_fatal (_("failed sanity check."));
3563 }
6b6e92f4 3564}
252b5132
RH		 3565
3566static void
31302357 3567install_gen_operand (int mode, int val)
252b5132
RH		 3568{
3569 switch (mode)
3570 {
fd99574b
NC		 3571 case '/': /* Special for mask loads for mac/msac insns with
3572 possible mask; trailing_ampersend set in bit 8. */
3573 the_ins.opcode[0] |= (val & 0x3f);
3574 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3575 break;
252b5132
RH		 3576 case 's':
3577 the_ins.opcode[0] |= val;
3578 break;
3579 case 'd':
3580 /* This is a kludge!!! */
3581 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3582 break;
3583 case 'b':
3584 case 'w':
3585 case 'l':
3586 case 'f':
3587 case 'F':
3588 case 'x':
3589 case 'p':
3590 the_ins.opcode[0] |= val;
3591 break;
36759679 3592 /* more stuff goes here. */
252b5132
RH		 3593 default:
3594 as_fatal (_("failed sanity check."));
3595 }
6b6e92f4 3596}
252b5132 3597
6b6e92f4
NC		 3598/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3599 then deal with the bitfield hack. */
252b5132
RH		 3600
3601static char *
31302357 3602crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3603{
3604 register int parens;
3605 register int c;
3606 register char *beg_str;
3607 int inquote = 0;
3608
3609 if (!str)
3610 {
3611 return str;
3612 }
3613 beg_str = str;
3614 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3615 {
3616 if (! inquote)
3617 {
3618 if (*str == '(')
3619 parens++;
3620 else if (*str == ')')
3621 {
3622 if (!parens)
36759679 3623 { /* ERROR. */
252b5132
RH		 3624 opP->error = _("Extra )");
3625 return str;
3626 }
3627 --parens;
3628 }
3629 }
3630 if (flag_mri && *str == '\'')
3631 inquote = ! inquote;
3632 }
3633 if (!*str && parens)
36759679 3634 { /* ERROR. */
252b5132
RH		 3635 opP->error = _("Missing )");
3636 return str;
3637 }
3638 c = *str;
3639 *str = '\0';
3640 if (m68k_ip_op (beg_str, opP) != 0)
3641 {
3642 *str = c;
3643 return str;
3644 }
3645 *str = c;
3646 if (c == '}')
36759679 3647 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3648 if (c)
3649 {
3650 c = *++str;
3651 if (!c)
3652 as_bad (_("Missing operand"));
3653 }
3654
3655 /* Detect MRI REG symbols and convert them to REGLSTs. */
3656 if (opP->mode == CONTROL && (int)opP->reg < 0)
3657 {
3658 opP->mode = REGLST;
3659 opP->mask = ~(int)opP->reg;
3660 opP->reg = 0;
3661 }
3662
3663 return str;
3664}
3665
3666/* This is the guts of the machine-dependent assembler. STR points to a
3667 machine dependent instruction. This function is supposed to emit
3668 the frags/bytes it assembles to.
3669 */
3670
3671static void
31302357 3672insert_reg (const char *regname, int regnum)
252b5132
RH		 3673{
3674 char buf[100];
3675 int i;
3676
3677#ifdef REGISTER_PREFIX
3678 if (!flag_reg_prefix_optional)
3679 {
3680 buf[0] = REGISTER_PREFIX;
3681 strcpy (buf + 1, regname);
3682 regname = buf;
3683 }
3684#endif
3685
3686 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3687 &zero_address_frag));
3688
3689 for (i = 0; regname[i]; i++)
3882b010 3690 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3691 buf[i] = '\0';
3692
3693 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3694 &zero_address_frag));
3695}
3696
3697struct init_entry
3698 {
3699 const char *name;
3700 int number;
3701 };
3702
3703static const struct init_entry init_table[] =
3704{
3705 { "d0", DATA0 },
3706 { "d1", DATA1 },
3707 { "d2", DATA2 },
3708 { "d3", DATA3 },
3709 { "d4", DATA4 },
3710 { "d5", DATA5 },
3711 { "d6", DATA6 },
3712 { "d7", DATA7 },
3713 { "a0", ADDR0 },
3714 { "a1", ADDR1 },
3715 { "a2", ADDR2 },
3716 { "a3", ADDR3 },
3717 { "a4", ADDR4 },
3718 { "a5", ADDR5 },
3719 { "a6", ADDR6 },
3720 { "fp", ADDR6 },
3721 { "a7", ADDR7 },
3722 { "sp", ADDR7 },
3723 { "ssp", ADDR7 },
3724 { "fp0", FP0 },
3725 { "fp1", FP1 },
3726 { "fp2", FP2 },
3727 { "fp3", FP3 },
3728 { "fp4", FP4 },
3729 { "fp5", FP5 },
3730 { "fp6", FP6 },
3731 { "fp7", FP7 },
3732 { "fpi", FPI },
3733 { "fpiar", FPI },
3734 { "fpc", FPI },
3735 { "fps", FPS },
3736 { "fpsr", FPS },
3737 { "fpc", FPC },
3738 { "fpcr", FPC },
3739 { "control", FPC },
3740 { "status", FPS },
3741 { "iaddr", FPI },
3742
3743 { "cop0", COP0 },
3744 { "cop1", COP1 },
3745 { "cop2", COP2 },
3746 { "cop3", COP3 },
3747 { "cop4", COP4 },
3748 { "cop5", COP5 },
3749 { "cop6", COP6 },
3750 { "cop7", COP7 },
3751 { "pc", PC },
3752 { "zpc", ZPC },
3753 { "sr", SR },
3754
3755 { "ccr", CCR },
3756 { "cc", CCR },
3757
6da466c7 3758 { "acc", ACC },
fd99574b
NC		 3759 { "acc0", ACC },
3760 { "acc1", ACC1 },
3761 { "acc2", ACC2 },
3762 { "acc3", ACC3 },
3763 { "accext01", ACCEXT01 },
3764 { "accext23", ACCEXT23 },
6da466c7
ILT		 3765 { "macsr", MACSR },
3766 { "mask", MASK },
3767
36759679
NC		 3768 /* Control registers. */
3769 { "sfc", SFC }, /* Source Function Code. */
252b5132 3770 { "sfcr", SFC },
36759679 3771 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3772 { "dfcr", DFC },
36759679
NC		 3773 { "cacr", CACR }, /* Cache Control Register. */
3774 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3775
36759679
NC		 3776 { "usp", USP }, /* User Stack Pointer. */
3777 { "vbr", VBR }, /* Vector Base Register. */
3778 { "msp", MSP }, /* Master Stack Pointer. */
3779 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3780
36759679
NC		 3781 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3782 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3783 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3784 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3785
3786 /* 68ec040 versions of same */
36759679
NC		 3787 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3788 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3789 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3790 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 3791
a8e24a56 3792 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 3793 manual indicated that the order is 2,3,0,1, but Ken Rose
3794 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3795 { "acr0", ACR0 }, /* Access Control Unit 0. */
3796 { "acr1", ACR1 }, /* Access Control Unit 1. */
3797 { "acr2", ACR2 }, /* Access Control Unit 2. */
3798 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3799
36759679 3800 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 3801 { "tcr", TC },
a8e24a56 3802 { "asid", ASID },
252b5132 3803
36759679
NC		 3804 { "mmusr", MMUSR }, /* MMU Status Register. */
3805 { "srp", SRP }, /* User Root Pointer. */
3806 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3807
3808 { "buscr", BUSCR },
a8e24a56 3809 { "mmubar", MMUBAR },
252b5132
RH		 3810 { "pcr", PCR },
3811
36759679
NC		 3812 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3813 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3814 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3815 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3816
3817 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3818 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 3819 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 3820 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3821 { "mpcr", MPCR }, /* mcfv4e registers. */
3822 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3823 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3824 { "asid", TC }, /* mcfv4e registers. */
3825 { "mmubar", BUSCR }, /* mcfv4e registers. */
3826 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3827 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3828 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3829 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3830 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3831 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3832 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3833 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3834 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3835 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3836 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3837 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3838
3839 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3840 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3841
3842 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b
KH		 3843
3844 { "cac", CAC }, /* fido registers. */
3845 { "mbb", MBB }, /* fido registers. */
36759679 3846 /* End of control registers. */
252b5132
RH		 3847
3848 { "ac", AC },
3849 { "bc", BC },
3850 { "cal", CAL },
3851 { "crp", CRP },
3852 { "drp", DRP },
3853 { "pcsr", PCSR },
3854 { "psr", PSR },
3855 { "scc", SCC },
3856 { "val", VAL },
3857 { "bad0", BAD0 },
3858 { "bad1", BAD1 },
3859 { "bad2", BAD2 },
3860 { "bad3", BAD3 },
3861 { "bad4", BAD4 },
3862 { "bad5", BAD5 },
3863 { "bad6", BAD6 },
3864 { "bad7", BAD7 },
3865 { "bac0", BAC0 },
3866 { "bac1", BAC1 },
3867 { "bac2", BAC2 },
3868 { "bac3", BAC3 },
3869 { "bac4", BAC4 },
3870 { "bac5", BAC5 },
3871 { "bac6", BAC6 },
3872 { "bac7", BAC7 },
3873
3874 { "ic", IC },
3875 { "dc", DC },
3876 { "nc", NC },
3877
3878 { "tt0", TT0 },
3879 { "tt1", TT1 },
36759679 3880 /* 68ec030 versions of same. */
252b5132
RH		 3881 { "ac0", TT0 },
3882 { "ac1", TT1 },
36759679 3883 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3884 { "acusr", PSR },
3885
3886 /* Suppressed data and address registers. */
3887 { "zd0", ZDATA0 },
3888 { "zd1", ZDATA1 },
3889 { "zd2", ZDATA2 },
3890 { "zd3", ZDATA3 },
3891 { "zd4", ZDATA4 },
3892 { "zd5", ZDATA5 },
3893 { "zd6", ZDATA6 },
3894 { "zd7", ZDATA7 },
3895 { "za0", ZADDR0 },
3896 { "za1", ZADDR1 },
3897 { "za2", ZADDR2 },
3898 { "za3", ZADDR3 },
3899 { "za4", ZADDR4 },
3900 { "za5", ZADDR5 },
3901 { "za6", ZADDR6 },
3902 { "za7", ZADDR7 },
3903
92774660 3904 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3905 { "d0l", DATA0L },
3906 { "d1l", DATA1L },
3907 { "d2l", DATA2L },
3908 { "d3l", DATA3L },
3909 { "d4l", DATA4L },
3910 { "d5l", DATA5L },
3911 { "d6l", DATA6L },
3912 { "d7l", DATA7L },
3913
3914 { "a0l", ADDR0L },
3915 { "a1l", ADDR1L },
3916 { "a2l", ADDR2L },
3917 { "a3l", ADDR3L },
3918 { "a4l", ADDR4L },
3919 { "a5l", ADDR5L },
3920 { "a6l", ADDR6L },
3921 { "a7l", ADDR7L },
3922
3923 { "d0u", DATA0U },
3924 { "d1u", DATA1U },
3925 { "d2u", DATA2U },
3926 { "d3u", DATA3U },
3927 { "d4u", DATA4U },
3928 { "d5u", DATA5U },
3929 { "d6u", DATA6U },
3930 { "d7u", DATA7U },
3931
3932 { "a0u", ADDR0U },
3933 { "a1u", ADDR1U },
3934 { "a2u", ADDR2U },
3935 { "a3u", ADDR3U },
3936 { "a4u", ADDR4U },
3937 { "a5u", ADDR5U },
3938 { "a6u", ADDR6U },
3939 { "a7u", ADDR7U },
3940
252b5132
RH		 3941 { 0, 0 }
3942};
3943
3944static void
31302357 3945init_regtable (void)
252b5132
RH		 3946{
3947 int i;
3948 for (i = 0; init_table[i].name; i++)
3949 insert_reg (init_table[i].name, init_table[i].number);
3950}
3951
252b5132 3952void
31302357 3953md_assemble (char *str)
252b5132
RH		 3954{
3955 const char *er;
3956 short *fromP;
3957 char *toP = NULL;
3958 int m, n = 0;
3959 char *to_beg_P;
3960 int shorts_this_frag;
3961 fixS *fixP;
3962
266abb8f
NS		 3963 if (!selected_cpu && !selected_arch)
3964 {
3965 /* We've not selected an architecture yet. Set the default
3966 now. We do this lazily so that an initial .cpu or .arch directive
3967 can specify. */
3968 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3969 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3970 }
3971 if (!initialized)
3972 m68k_init_arch ();
3973
252b5132
RH		 3974 /* In MRI mode, the instruction and operands are separated by a
3975 space. Anything following the operands is a comment. The label
3976 has already been removed. */
3977 if (flag_mri)
3978 {
3979 char *s;
3980 int fields = 0;
3981 int infield = 0;
3982 int inquote = 0;
3983
3984 for (s = str; *s != '\0'; s++)
3985 {
3986 if ((*s == ' ' || *s == '\t') && ! inquote)
3987 {
3988 if (infield)
3989 {
3990 ++fields;
3991 if (fields >= 2)
3992 {
3993 *s = '\0';
3994 break;
3995 }
3996 infield = 0;
3997 }
3998 }
3999 else
4000 {
4001 if (! infield)
4002 infield = 1;
4003 if (*s == '\'')
4004 inquote = ! inquote;
4005 }
4006 }
4007 }
4008
31302357 4009 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4010 m68k_ip (str);
4011 er = the_ins.error;
4012 if (!er)
4013 {
4014 for (n = 0; n < the_ins.numargs; n++)
4015 if (the_ins.operands[n].error)
4016 {
4017 er = the_ins.operands[n].error;
4018 break;
4019 }
4020 }
4021 if (er)
4022 {
4023 as_bad (_("%s -- statement `%s' ignored"), er, str);
4024 return;
4025 }
4026
4027 /* If there is a current label, record that it marks an instruction. */
4028 if (current_label != NULL)
4029 {
4030 current_label->text = 1;
4031 current_label = NULL;
4032 }
4033
f27a3839
AS		 4034#ifdef OBJ_ELF
4035 /* Tie dwarf2 debug info to the address at the start of the insn. */
4036 dwarf2_emit_insn (0);
4037#endif
4038
252b5132
RH		 4039 if (the_ins.nfrag == 0)
4040 {
36759679 4041 /* No frag hacking involved; just put it out. */
252b5132
RH		 4042 toP = frag_more (2 * the_ins.numo);
4043 fromP = &the_ins.opcode[0];
4044 for (m = the_ins.numo; m; --m)
4045 {
4046 md_number_to_chars (toP, (long) (*fromP), 2);
4047 toP += 2;
4048 fromP++;
4049 }
36759679 4050 /* Put out symbol-dependent info. */
252b5132
RH		 4051 for (m = 0; m < the_ins.nrel; m++)
4052 {
4053 switch (the_ins.reloc[m].wid)
4054 {
4055 case 'B':
4056 n = 1;
4057 break;
4058 case 'b':
4059 n = 1;
4060 break;
4061 case '3':
4062 n = 1;
4063 break;
4064 case 'w':
4065 case 'W':
4066 n = 2;
4067 break;
4068 case 'l':
4069 n = 4;
4070 break;
4071 default:
4072 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4073 the_ins.reloc[m].wid);
4074 }
4075
4076 fixP = fix_new_exp (frag_now,
4077 ((toP - frag_now->fr_literal)
4078 - the_ins.numo * 2 + the_ins.reloc[m].n),
4079 n,
4080 &the_ins.reloc[m].exp,
4081 the_ins.reloc[m].pcrel,
4082 get_reloc_code (n, the_ins.reloc[m].pcrel,
4083 the_ins.reloc[m].pic_reloc));
4084 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4085 if (the_ins.reloc[m].wid == 'B')
4086 fixP->fx_signed = 1;
4087 }
4088 return;
4089 }
4090
36759679 4091 /* There's some frag hacking. */
fbe572f9
AM		 4092 {
4093 /* Calculate the max frag size. */
4094 int wid;
4095
4096 wid = 2 * the_ins.fragb[0].fragoff;
4097 for (n = 1; n < the_ins.nfrag; n++)
4098 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4099 /* frag_var part. */
4100 wid += 10;
4101 /* Make sure the whole insn fits in one chunk, in particular that
4102 the var part is attached, as we access one byte before the
4103 variable frag for byte branches. */
4104 frag_grow (wid);
4105 }
4106
252b5132
RH		 4107 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4108 {
4109 int wid;
4110
4111 if (n == 0)
4112 wid = 2 * the_ins.fragb[n].fragoff;
4113 else
4114 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4115 toP = frag_more (wid);
4116 to_beg_P = toP;
4117 shorts_this_frag = 0;
4118 for (m = wid / 2; m; --m)
4119 {
4120 md_number_to_chars (toP, (long) (*fromP), 2);
4121 toP += 2;
4122 fromP++;
4123 shorts_this_frag++;
4124 }
4125 for (m = 0; m < the_ins.nrel; m++)
4126 {
4127 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4128 {
4129 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4130 break;
4131 }
4132 wid = the_ins.reloc[m].wid;
4133 if (wid == 0)
4134 continue;
4135 the_ins.reloc[m].wid = 0;
4136 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4137
4138 fixP = fix_new_exp (frag_now,
4139 ((toP - frag_now->fr_literal)
4140 - the_ins.numo * 2 + the_ins.reloc[m].n),
4141 wid,
4142 &the_ins.reloc[m].exp,
4143 the_ins.reloc[m].pcrel,
4144 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4145 the_ins.reloc[m].pic_reloc));
4146 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4147 }
4148 (void) frag_var (rs_machine_dependent, 10, 0,
4149 (relax_substateT) (the_ins.fragb[n].fragty),
4150 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4151 }
4152 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4153 shorts_this_frag = 0;
4154 if (n)
4155 {
055d1eb0 4156 toP = frag_more (n * 2);
252b5132
RH		 4157 while (n--)
4158 {
4159 md_number_to_chars (toP, (long) (*fromP), 2);
4160 toP += 2;
4161 fromP++;
4162 shorts_this_frag++;
4163 }
4164 }
4165 for (m = 0; m < the_ins.nrel; m++)
4166 {
4167 int wid;
4168
4169 wid = the_ins.reloc[m].wid;
4170 if (wid == 0)
4171 continue;
4172 the_ins.reloc[m].wid = 0;
4173 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4174
4175 fixP = fix_new_exp (frag_now,
4176 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4177 - shorts_this_frag * 2),
4178 wid,
4179 &the_ins.reloc[m].exp,
4180 the_ins.reloc[m].pcrel,
4181 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4182 the_ins.reloc[m].pic_reloc));
4183 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4184 }
4185}
4186
60fed2d3
NC		 4187/* Comparison function used by qsort to rank the opcode entries by name. */
4188
4189static int
4190m68k_compare_opcode (const void * v1, const void * v2)
4191{
4192 struct m68k_opcode * op1, * op2;
4193 int ret;
4194
03b13e59
NC		 4195 if (v1 == v2)
4196 return 0;
4197
60fed2d3
NC		 4198 op1 = *(struct m68k_opcode **) v1;
4199 op2 = *(struct m68k_opcode **) v2;
4200
4201 /* Compare the two names. If different, return the comparison.
4202 If the same, return the order they are in the opcode table. */
4203 ret = strcmp (op1->name, op2->name);
4204 if (ret)
4205 return ret;
4206 if (op1 < op2)
4207 return -1;
03b13e59 4208 return 1;
60fed2d3
NC		 4209}
4210
252b5132 4211void
60fed2d3 4212md_begin (void)
252b5132 4213{
60fed2d3
NC		 4214 const struct m68k_opcode *ins;
4215 struct m68k_incant *hack, *slak;
4216 const char *retval = 0; /* Empty string, or error msg text. */
4217 int i;
4218
4219 /* Set up hash tables with 68000 instructions.
4220 similar to what the vax assembler does. */
252b5132
RH		 4221 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4222 a copy of it at runtime, adding in the information we want but isn't
4223 there. I think it'd be better to have an awk script hack the table
4224 at compile time. Or even just xstr the table and use it as-is. But
4225 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4226 names. */
4227
252b5132
RH		 4228 if (flag_mri)
4229 {
4230 flag_reg_prefix_optional = 1;
4231 m68k_abspcadd = 1;
4232 if (! m68k_rel32_from_cmdline)
4233 m68k_rel32 = 0;
4234 }
4235
60fed2d3
NC		 4236 /* First sort the opcode table into alphabetical order to seperate
4237 the order that the assembler wants to see the opcodes from the
4238 order that the disassembler wants to see them. */
4239 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4240 if (!m68k_sorted_opcodes)
4241 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4242 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4243
4244 for (i = m68k_numopcodes; i--;)
4245 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4246
4247 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4248 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4249
252b5132
RH		 4250 op_hash = hash_new ();
4251
4252 obstack_begin (&robyn, 4000);
4253 for (i = 0; i < m68k_numopcodes; i++)
4254 {
4255 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4256 do
4257 {
60fed2d3
NC		 4258 ins = m68k_sorted_opcodes[i];
4259
4260 /* We *could* ignore insns that don't match our
4261 arch here by just leaving them out of the hash. */
252b5132
RH		 4262 slak->m_operands = ins->args;
4263 slak->m_opnum = strlen (slak->m_operands) / 2;
4264 slak->m_arch = ins->arch;
4265 slak->m_opcode = ins->opcode;
36759679 4266 /* This is kludgey. */
252b5132
RH		 4267 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4268 if (i + 1 != m68k_numopcodes
60fed2d3 4269 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4270 {
60fed2d3 4271 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4272 i++;
4273 }
4274 else
4275 slak->m_next = 0;
4276 slak = slak->m_next;
4277 }
4278 while (slak);
4279
4280 retval = hash_insert (op_hash, ins->name, (char *) hack);
4281 if (retval)
4282 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4283 }
4284
4285 for (i = 0; i < m68k_numaliases; i++)
4286 {
4287 const char *name = m68k_opcode_aliases[i].primary;
4288 const char *alias = m68k_opcode_aliases[i].alias;
4289 PTR val = hash_find (op_hash, name);
60fed2d3 4290
252b5132
RH		 4291 if (!val)
4292 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4293 retval = hash_insert (op_hash, alias, val);
4294 if (retval)
4295 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4296 }
4297
4298 /* In MRI mode, all unsized branches are variable sized. Normally,
4299 they are word sized. */
4300 if (flag_mri)
4301 {
4302 static struct m68k_opcode_alias mri_aliases[] =
4303 {
4304 { "bhi", "jhi", },
4305 { "bls", "jls", },
4306 { "bcc", "jcc", },
4307 { "bcs", "jcs", },
4308 { "bne", "jne", },
4309 { "beq", "jeq", },
4310 { "bvc", "jvc", },
4311 { "bvs", "jvs", },
4312 { "bpl", "jpl", },
4313 { "bmi", "jmi", },
4314 { "bge", "jge", },
4315 { "blt", "jlt", },
4316 { "bgt", "jgt", },
4317 { "ble", "jle", },
4318 { "bra", "jra", },
4319 { "bsr", "jbsr", },
4320 };
4321
8fce3f5e
AM		 4322 for (i = 0;
4323 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4324 i++)
252b5132
RH		 4325 {
4326 const char *name = mri_aliases[i].primary;
4327 const char *alias = mri_aliases[i].alias;
4328 PTR val = hash_find (op_hash, name);
60fed2d3 4329
252b5132
RH		 4330 if (!val)
4331 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4332 retval = hash_jam (op_hash, alias, val);
4333 if (retval)
4334 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4335 }
4336 }
4337
8fce3f5e 4338 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4339 {
4340 notend_table[i] = 0;
4341 alt_notend_table[i] = 0;
4342 }
60fed2d3 4343
252b5132
RH		 4344 notend_table[','] = 1;
4345 notend_table['{'] = 1;
4346 notend_table['}'] = 1;
4347 alt_notend_table['a'] = 1;
4348 alt_notend_table['A'] = 1;
4349 alt_notend_table['d'] = 1;
4350 alt_notend_table['D'] = 1;
4351 alt_notend_table['#'] = 1;
4352 alt_notend_table['&'] = 1;
4353 alt_notend_table['f'] = 1;
4354 alt_notend_table['F'] = 1;
4355#ifdef REGISTER_PREFIX
4356 alt_notend_table[REGISTER_PREFIX] = 1;
4357#endif
4358
4359 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4360 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4361 alt_notend_table['('] = 1;
4362
4363 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4364 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4365 alt_notend_table['@'] = 1;
4366
4367 /* We need to put digits in alt_notend_table to handle
60fed2d3 4368 bfextu %d0{24:1},%d0 */
252b5132
RH		 4369 alt_notend_table['0'] = 1;
4370 alt_notend_table['1'] = 1;
4371 alt_notend_table['2'] = 1;
4372 alt_notend_table['3'] = 1;
4373 alt_notend_table['4'] = 1;
4374 alt_notend_table['5'] = 1;
4375 alt_notend_table['6'] = 1;
4376 alt_notend_table['7'] = 1;
4377 alt_notend_table['8'] = 1;
4378 alt_notend_table['9'] = 1;
4379
4380#ifndef MIT_SYNTAX_ONLY
4381 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4382 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4383 {
4384 int n = 0;
60fed2d3 4385
252b5132
RH		 4386 while (mote_pseudo_table[n].poc_name)
4387 {
60fed2d3 4388 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4389 hash_insert (op_hash,
4390 mote_pseudo_table[n].poc_name, (char *) hack);
4391 hack->m_operands = 0;
4392 hack->m_opnum = n;
4393 n++;
4394 }
4395 }
4396#endif
4397
4398 init_regtable ();
4399
4400#ifdef OBJ_ELF
4401 record_alignment (text_section, 2);
4402 record_alignment (data_section, 2);
4403 record_alignment (bss_section, 2);
4404#endif
4405}
4406
252b5132
RH		 4407\f
4408/* This is called when a label is defined. */
4409
4410void
31302357 4411m68k_frob_label (symbolS *sym)
252b5132
RH		 4412{
4413 struct label_line *n;
4414
4415 n = (struct label_line *) xmalloc (sizeof *n);
4416 n->next = labels;
4417 n->label = sym;
4418 as_where (&n->file, &n->line);
4419 n->text = 0;
4420 labels = n;
4421 current_label = n;
07a53e5c
RH		 4422
4423#ifdef OBJ_ELF
4424 dwarf2_emit_label (sym);
4425#endif
252b5132
RH		 4426}
4427
4428/* This is called when a value that is not an instruction is emitted. */
4429
4430void
31302357 4431m68k_flush_pending_output (void)
252b5132
RH		 4432{
4433 current_label = NULL;
4434}
4435
4436/* This is called at the end of the assembly, when the final value of
4437 the label is known. We warn if this is a text symbol aligned at an
4438 odd location. */
4439
4440void
31302357 4441m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4442{
4443 if (S_GET_SEGMENT (sym) == reg_section
4444 && (int) S_GET_VALUE (sym) < 0)
4445 {
4446 S_SET_SEGMENT (sym, absolute_section);
4447 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4448 }
4449 else if ((S_GET_VALUE (sym) & 1) != 0)
4450 {
4451 struct label_line *l;
4452
4453 for (l = labels; l != NULL; l = l->next)
4454 {
4455 if (l->label == sym)
4456 {
4457 if (l->text)
4458 as_warn_where (l->file, l->line,
4459 _("text label `%s' aligned to odd boundary"),
4460 S_GET_NAME (sym));
4461 break;
4462 }
4463 }
4464 }
4465}
4466\f
4467/* This is called if we go in or out of MRI mode because of the .mri
4468 pseudo-op. */
4469
4470void
31302357 4471m68k_mri_mode_change (int on)
252b5132
RH		 4472{
4473 if (on)
4474 {
4475 if (! flag_reg_prefix_optional)
4476 {
4477 flag_reg_prefix_optional = 1;
4478#ifdef REGISTER_PREFIX
4479 init_regtable ();
4480#endif
4481 }
4482 m68k_abspcadd = 1;
4483 if (! m68k_rel32_from_cmdline)
4484 m68k_rel32 = 0;
4485 }
4486 else
4487 {
4488 if (! reg_prefix_optional_seen)
4489 {
4490#ifdef REGISTER_PREFIX_OPTIONAL
4491 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4492#else
4493 flag_reg_prefix_optional = 0;
4494#endif
4495#ifdef REGISTER_PREFIX
4496 init_regtable ();
4497#endif
4498 }
4499 m68k_abspcadd = 0;
4500 if (! m68k_rel32_from_cmdline)
4501 m68k_rel32 = 1;
4502 }
4503}
4504
36759679 4505/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4506#define MAX_LITTLENUMS 6
4507
4508/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4509 of type TYPE, and store the appropriate bytes in *LITP. The number
4510 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4511 returned, or NULL on OK. */
4512
4513char *
31302357 4514md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4515{
4516 int prec;
4517 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4518 LITTLENUM_TYPE *wordP;
4519 char *t;
4520
4521 switch (type)
4522 {
4523 case 'f':
4524 case 'F':
4525 case 's':
4526 case 'S':
4527 prec = 2;
4528 break;
4529
4530 case 'd':
4531 case 'D':
4532 case 'r':
4533 case 'R':
4534 prec = 4;
4535 break;
4536
4537 case 'x':
4538 case 'X':
4539 prec = 6;
4540 break;
4541
4542 case 'p':
4543 case 'P':
4544 prec = 6;
4545 break;
4546
4547 default:
4548 *sizeP = 0;
4549 return _("Bad call to MD_ATOF()");
4550 }
4551 t = atof_ieee (input_line_pointer, type, words);
4552 if (t)
4553 input_line_pointer = t;
4554
4555 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4556 for (wordP = words; prec--;)
4557 {
4558 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4559 litP += sizeof (LITTLENUM_TYPE);
4560 }
4561 return 0;
4562}
4563
4564void
31302357 4565md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4566{
4567 number_to_chars_bigendian (buf, val, n);
4568}
4569
94f592af 4570void
55cf6793 4571md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4572{
bbe8ef22 4573 offsetT val = *valP;
252b5132
RH		 4574 addressT upper_limit;
4575 offsetT lower_limit;
4576
4577 /* This is unnecessary but it convinces the native rs6000 compiler
4578 to generate the code we want. */
4579 char *buf = fixP->fx_frag->fr_literal;
4580 buf += fixP->fx_where;
36759679 4581 /* End ibm compiler workaround. */
252b5132 4582
bd17c2c3 4583 val = SEXT (val);
252b5132 4584
94f592af
NC		 4585 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4586 fixP->fx_done = 1;
4587
252b5132
RH		 4588#ifdef OBJ_ELF
4589 if (fixP->fx_addsy)
4590 {
4591 memset (buf, 0, fixP->fx_size);
36759679 4592 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4593
4594 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4595 && !S_IS_DEFINED (fixP->fx_addsy)
4596 && !S_IS_WEAK (fixP->fx_addsy))
4597 S_SET_WEAK (fixP->fx_addsy);
4598 return;
4599 }
4600#endif
4601
252b5132
RH		 4602 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4603 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4604 return;
252b5132
RH		 4605
4606 switch (fixP->fx_size)
4607 {
94f592af
NC		 4608 /* The cast to offsetT below are necessary to make code
4609 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4610 case 1:
4611 *buf++ = val;
4612 upper_limit = 0x7f;
4613 lower_limit = - (offsetT) 0x80;
4614 break;
4615 case 2:
4616 *buf++ = (val >> 8);
4617 *buf++ = val;
4618 upper_limit = 0x7fff;
4619 lower_limit = - (offsetT) 0x8000;
4620 break;
4621 case 4:
4622 *buf++ = (val >> 24);
4623 *buf++ = (val >> 16);
4624 *buf++ = (val >> 8);
4625 *buf++ = val;
4626 upper_limit = 0x7fffffff;
36759679 4627 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4628 break;
4629 default:
4630 BAD_CASE (fixP->fx_size);
4631 }
4632
4633 /* Fix up a negative reloc. */
4634 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4635 {
4636 fixP->fx_addsy = fixP->fx_subsy;
4637 fixP->fx_subsy = NULL;
4638 fixP->fx_tcbit = 1;
4639 }
4640
4641 /* For non-pc-relative values, it's conceivable we might get something
4642 like "0xff" for a byte field. So extend the upper part of the range
4643 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4644 so that we can do any range checking at all. */
4645 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4646 upper_limit = upper_limit * 2 + 1;
4647
4648 if ((addressT) val > upper_limit
4649 && (val > 0 || val < lower_limit))
4650 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4651
4652 /* A one byte PC-relative reloc means a short branch. We can't use
4653 a short branch with a value of 0 or -1, because those indicate
4654 different opcodes (branches with longer offsets). fixup_segment
4655 in write.c may have clobbered fx_pcrel, so we need to examine the
4656 reloc type. */
4657 if ((fixP->fx_pcrel
7be1c489 4658 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4659 && fixP->fx_size == 1
4660 && (fixP->fx_addsy == NULL
4661 || S_IS_DEFINED (fixP->fx_addsy))
4662 && (val == 0 || val == -1))
4663 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4664}
4665
252b5132
RH		 4666/* *fragP has been relaxed to its final size, and now needs to have
4667 the bytes inside it modified to conform to the new size There is UGLY
4668 MAGIC here. ..
4669 */
4670static void
31302357 4671md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4672{
4673 long disp;
252b5132
RH		 4674 fixS *fixP;
4675
4676 /* Address in object code of the displacement. */
4677 register int object_address = fragP->fr_fix + fragP->fr_address;
4678
4679 /* Address in gas core of the place to store the displacement. */
4680 /* This convinces the native rs6000 compiler to generate the code we
92774660 4681 want. */
252b5132
RH		 4682 register char *buffer_address = fragP->fr_literal;
4683 buffer_address += fragP->fr_fix;
36759679 4684 /* End ibm compiler workaround. */
252b5132
RH		 4685
4686 /* The displacement of the address, from current location. */
4687 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4688 disp = (disp + fragP->fr_offset) - object_address;
4689
252b5132
RH		 4690 switch (fragP->fr_subtype)
4691 {
151337e8
NC		 4692 case TAB (BRANCHBWL, BYTE):
4693 case TAB (BRABSJUNC, BYTE):
4694 case TAB (BRABSJCOND, BYTE):
4695 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4696 know (issbyte (disp));
4697 if (disp == 0)
b091f402
AM		 4698 as_bad_where (fragP->fr_file, fragP->fr_line,
4699 _("short branch with zero offset: use :w"));
151337e8 4700 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4701 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4702 fixP->fx_pcrel_adjust = -1;
252b5132 4703 break;
151337e8
NC		 4704 case TAB (BRANCHBWL, SHORT):
4705 case TAB (BRABSJUNC, SHORT):
4706 case TAB (BRABSJCOND, SHORT):
4707 case TAB (BRANCHBW, SHORT):
252b5132 4708 fragP->fr_opcode[1] = 0x00;
151337e8 4709 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4710 1, RELAX_RELOC_PC16);
151337e8
NC		 4711 fragP->fr_fix += 2;
4712 break;
4713 case TAB (BRANCHBWL, LONG):
4714 fragP->fr_opcode[1] = (char) 0xFF;
4715 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4716 1, RELAX_RELOC_PC32);
151337e8 4717 fragP->fr_fix += 4;
252b5132 4718 break;
151337e8
NC		 4719 case TAB (BRABSJUNC, LONG):
4720 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4721 {
36759679 4722 if (flag_keep_pcrel)
6b6e92f4 4723 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4724 fragP->fr_opcode[0] = 0x4E;
36759679 4725 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4726 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4727 0, RELAX_RELOC_ABS32);
151337e8
NC		 4728 fragP->fr_fix += 4;
4729 }
4730 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4731 {
36759679 4732 if (flag_keep_pcrel)
6b6e92f4 4733 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4734 fragP->fr_opcode[0] = 0x4E;
36759679 4735 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4736 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4737 0, RELAX_RELOC_ABS32);
151337e8 4738 fragP->fr_fix += 4;
252b5132
RH		 4739 }
4740 else
4741 {
151337e8
NC		 4742 /* This cannot happen, because jbsr and jbra are the only two
4743 unconditional branches. */
4744 abort ();
252b5132
RH		 4745 }
4746 break;
151337e8 4747 case TAB (BRABSJCOND, LONG):
36759679 4748 if (flag_keep_pcrel)
6b6e92f4 4749 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4750
36759679
NC		 4751 /* Only Bcc 68000 instructions can come here
4752 Change bcc into b!cc/jmp absl long. */
4753 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4754 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4755
4756 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4757 different frag, in which case referring to them is a no-no.
92774660 4758 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4759 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4760 *buffer_address++ = (char) 0xf9;
36759679 4761 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4762 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4763 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4764 fragP->fr_fix += 4;
4765 break;
4766 case TAB (FBRANCH, SHORT):
4767 know ((fragP->fr_opcode[1] & 0x40) == 0);
4768 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4769 1, RELAX_RELOC_PC16);
151337e8
NC		 4770 fragP->fr_fix += 2;
4771 break;
4772 case TAB (FBRANCH, LONG):
36759679 4773 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4774 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4775 1, RELAX_RELOC_PC32);
252b5132 4776 fragP->fr_fix += 4;
252b5132 4777 break;
151337e8
NC		 4778 case TAB (DBCCLBR, SHORT):
4779 case TAB (DBCCABSJ, SHORT):
4780 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4781 1, RELAX_RELOC_PC16);
151337e8
NC		 4782 fragP->fr_fix += 2;
4783 break;
4784 case TAB (DBCCLBR, LONG):
36759679
NC		 4785 /* Only DBcc instructions can come here.
4786 Change dbcc into dbcc/bral.
4787 JF: these used to be fr_opcode[2-7], but that's wrong. */
4788 if (flag_keep_pcrel)
6b6e92f4 4789 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4790
36759679 4791 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4792 *buffer_address++ = 0x04;
36759679 4793 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4794 *buffer_address++ = 0x06;
151337e8
NC		 4795 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4796 *buffer_address++ = (char) 0xff;
252b5132 4797
36759679 4798 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4799 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4800 RELAX_RELOC_PC32);
252b5132 4801 fragP->fr_fix += 4;
252b5132 4802 break;
151337e8 4803 case TAB (DBCCABSJ, LONG):
36759679
NC		 4804 /* Only DBcc instructions can come here.
4805 Change dbcc into dbcc/jmp.
4806 JF: these used to be fr_opcode[2-7], but that's wrong. */
4807 if (flag_keep_pcrel)
6b6e92f4 4808 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4809
36759679 4810 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4811 *buffer_address++ = 0x04;
36759679 4812 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4813 *buffer_address++ = 0x06;
36759679 4814 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4815 *buffer_address++ = (char) 0xf9;
4816
36759679 4817 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4818 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4819 RELAX_RELOC_ABS32);
252b5132 4820 fragP->fr_fix += 4;
252b5132 4821 break;
151337e8 4822 case TAB (PCREL1632, SHORT):
252b5132
RH		 4823 fragP->fr_opcode[1] &= ~0x3F;
4824 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4825 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4826 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4827 fragP->fr_fix += 2;
252b5132 4828 break;
151337e8 4829 case TAB (PCREL1632, LONG):
252b5132
RH		 4830 /* Already set to mode 7.3; this indicates: PC indirect with
4831 suppressed index, 32-bit displacement. */
4832 *buffer_address++ = 0x01;
4833 *buffer_address++ = 0x70;
4834 fragP->fr_fix += 2;
151337e8 4835 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4836 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4837 fixP->fx_pcrel_adjust = 2;
4838 fragP->fr_fix += 4;
252b5132 4839 break;
252b5132 4840 case TAB (PCINDEX, BYTE):
252b5132
RH		 4841 assert (fragP->fr_fix >= 2);
4842 buffer_address[-2] &= ~1;
151337e8 4843 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4844 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4845 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4846 break;
4847 case TAB (PCINDEX, SHORT):
252b5132
RH		 4848 assert (fragP->fr_fix >= 2);
4849 buffer_address[-2] |= 0x1;
4850 buffer_address[-1] = 0x20;
4851 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4852 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4853 fixP->fx_pcrel_adjust = 2;
151337e8 4854 fragP->fr_fix += 2;
252b5132
RH		 4855 break;
4856 case TAB (PCINDEX, LONG):
252b5132
RH		 4857 assert (fragP->fr_fix >= 2);
4858 buffer_address[-2] |= 0x1;
4859 buffer_address[-1] = 0x30;
151337e8 4860 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4861 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4862 fixP->fx_pcrel_adjust = 2;
4863 fragP->fr_fix += 4;
4864 break;
4865 case TAB (ABSTOPCREL, SHORT):
4866 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4867 1, RELAX_RELOC_PC16);
151337e8
NC		 4868 fragP->fr_fix += 2;
4869 break;
4870 case TAB (ABSTOPCREL, LONG):
36759679 4871 if (flag_keep_pcrel)
6b6e92f4 4872 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4873 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4874 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4875 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4876 abort ();
4877 fragP->fr_opcode[1] &= ~0x3F;
4878 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4879 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4880 0, RELAX_RELOC_ABS32);
151337e8 4881 fragP->fr_fix += 4;
252b5132 4882 break;
252b5132
RH		 4883 }
4884}
4885
252b5132 4886void
31302357
AS		 4887md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4888 segT sec ATTRIBUTE_UNUSED,
4889 fragS *fragP)
252b5132
RH		 4890{
4891 md_convert_frag_1 (fragP);
4892}
252b5132
RH		 4893
4894/* Force truly undefined symbols to their maximum size, and generally set up
4895 the frag list to be relaxed
4896 */
4897int
31302357 4898md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4899{
151337e8 4900 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4901 switch (fragP->fr_subtype)
4902 {
151337e8
NC		 4903 case TAB (BRANCHBWL, SZ_UNDEF):
4904 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4905 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4906 {
151337e8
NC		 4907 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4908 && relaxable_symbol (fragP->fr_symbol))
252b5132 4909 {
151337e8
NC		 4910 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4911 }
4912 else if (flag_short_refs)
4913 {
4914 /* Symbol is undefined and we want short ref. */
4915 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4916 }
4917 else
4918 {
151337e8
NC		 4919 /* Symbol is still undefined. Make it LONG. */
4920 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4921 }
4922 break;
151337e8 4923 }
252b5132 4924
151337e8 4925 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4926 {
151337e8
NC		 4927 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4928 && relaxable_symbol (fragP->fr_symbol))
252b5132 4929 {
151337e8 4930 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4931 }
4932 else
4933 {
151337e8
NC		 4934 /* Symbol is undefined and we don't have long branches. */
4935 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4936 }
4937 break;
151337e8 4938 }
252b5132 4939
151337e8 4940 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4941 case TAB (DBCCLBR, SZ_UNDEF):
4942 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4943 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4944 {
8ec6253e
NC		 4945 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4946 && relaxable_symbol (fragP->fr_symbol))
151337e8 4947 || flag_short_refs)
252b5132 4948 {
151337e8 4949 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4950 }
4951 else
4952 {
151337e8 4953 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4954 }
4955 break;
151337e8 4956 }
81d4177b 4957
252b5132
RH		 4958 case TAB (PCINDEX, SZ_UNDEF):
4959 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4960 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4961 {
4962 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4963 }
4964 else
4965 {
4966 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4967 }
4968 break;
4969
151337e8
NC		 4970 case TAB (ABSTOPCREL, SZ_UNDEF):
4971 {
4972 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4973 && relaxable_symbol (fragP->fr_symbol)))
4974 {
4975 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4976 }
4977 else
4978 {
4979 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4980 }
4981 break;
4982 }
4983
252b5132
RH		 4984 default:
4985 break;
4986 }
4987
151337e8 4988 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4989 switch (fragP->fr_subtype)
4990 {
151337e8
NC		 4991 case TAB (BRANCHBWL, BYTE):
4992 case TAB (BRABSJUNC, BYTE):
4993 case TAB (BRABSJCOND, BYTE):
4994 case TAB (BRANCHBW, BYTE):
252b5132 4995 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4996 case we force word mode. If the symbol is at the start of a
4997 frag, and it is the next frag with any data in it (usually
4998 this is just the next frag, but assembler listings may
4999 introduce empty frags), we must use word mode. */
5000 if (fragP->fr_symbol)
252b5132 5001 {
ac62c346 5002 fragS *sym_frag;
252b5132 5003
ac62c346
AM		 5004 sym_frag = symbol_get_frag (fragP->fr_symbol);
5005 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5006 {
ac62c346
AM		 5007 fragS *l;
5008
23b7f870 5009 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5010 if (l->fr_fix != 0)
5011 break;
5012 if (l == sym_frag)
5013 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5014 }
5015 }
5016 break;
5017 default:
5018 break;
5019 }
ac62c346 5020 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5021}
5022
5023#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5024/* the bit-field entries in the relocation_info struct plays hell
5025 with the byte-order problems of cross-assembly. So as a hack,
5026 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5027 you there. -KWK */
252b5132
RH		 5028/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5029 are symbolnum, most sig. byte first. Last byte is broken up with
5030 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5031 nibble as nuthin. (on Sun 3 at least) */
5032/* Translate the internal relocation information into target-specific
92774660 5033 format. */
252b5132
RH		 5034#ifdef comment
5035void
31302357 5036md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5037{
36759679 5038 /* This is easy. */
252b5132 5039 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5040 /* Now the fun stuff. */
252b5132 5041 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5042 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5043 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5044 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5045 | ((ri->r_length << 5) & 0x60)
5046 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5047}
5048
36759679 5049#endif
252b5132 5050
252b5132
RH		 5051#endif /* OBJ_AOUT or OBJ_BOUT */
5052
5053#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5054int md_short_jump_size = 4;
5055int md_long_jump_size = 6;
252b5132
RH		 5056
5057void
31302357
AS		 5058md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5059 fragS *frag ATTRIBUTE_UNUSED,
5060 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5061{
5062 valueT offset;
5063
5064 offset = to_addr - (from_addr + 2);
5065
5066 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5067 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5068}
5069
5070void
31302357
AS		 5071md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5072 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5073{
5074 valueT offset;
5075
6b6e92f4 5076 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5077 {
36759679 5078 if (flag_keep_pcrel)
6b6e92f4 5079 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5080 offset = to_addr - S_GET_VALUE (to_symbol);
5081 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5082 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5083 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5084 0, NO_RELOC);
5085 }
5086 else
5087 {
5088 offset = to_addr - (from_addr + 2);
5089 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5090 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5091 }
5092}
5093
5094#endif
5095
5096/* Different values of OK tell what its OK to return. Things that
5097 aren't OK are an error (what a shock, no?)
5098
5099 0: Everything is OK
3e602632
NC		 5100 10: Absolute 1:8 only
5101 20: Absolute 0:7 only
5102 30: absolute 0:15 only
5103 40: Absolute 0:31 only
5104 50: absolute 0:127 only
252b5132 5105 55: absolute -64:63 only
3e602632
NC		 5106 60: absolute -128:127 only
5107 70: absolute 0:4095 only
5108 80: absolute -1, 1:7 only
5109 90: No bignums. */
252b5132
RH		 5110
5111static int
31302357 5112get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5113{
5114 if (exp->exp.X_op == O_absent)
5115 {
36759679 5116 /* Do the same thing the VAX asm does. */
252b5132
RH		 5117 op (exp) = O_constant;
5118 adds (exp) = 0;
5119 subs (exp) = 0;
5120 offs (exp) = 0;
5121 if (ok == 10)
5122 {
5123 as_warn (_("expression out of range: defaulting to 1"));
5124 offs (exp) = 1;
5125 }
5126 }
5127 else if (exp->exp.X_op == O_constant)
5128 {
5129 switch (ok)
5130 {
5131 case 10:
bd17c2c3 5132 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5133 {
5134 as_warn (_("expression out of range: defaulting to 1"));
5135 offs (exp) = 1;
5136 }
5137 break;
5138 case 20:
bd17c2c3 5139 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5140 goto outrange;
5141 break;
5142 case 30:
bd17c2c3 5143 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5144 goto outrange;
5145 break;
5146 case 40:
bd17c2c3 5147 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5148 goto outrange;
5149 break;
5150 case 50:
bd17c2c3 5151 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5152 goto outrange;
5153 break;
5154 case 55:
bd17c2c3 5155 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5156 goto outrange;
5157 break;
5158 case 60:
bd17c2c3 5159 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5160 goto outrange;
5161 break;
5162 case 70:
bd17c2c3 5163 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5164 {
5165 outrange:
5166 as_warn (_("expression out of range: defaulting to 0"));
5167 offs (exp) = 0;
5168 }
5169 break;
3e602632 5170 case 80:
bd17c2c3
AM		 5171 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5172 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5173 {
5174 as_warn (_("expression out of range: defaulting to 1"));
5175 offs (exp) = 1;
5176 }
5177 break;
252b5132
RH		 5178 default:
5179 break;
5180 }
5181 }
5182 else if (exp->exp.X_op == O_big)
5183 {
36759679 5184 if (offs (exp) <= 0 /* flonum. */
3e602632 5185 && (ok == 90 /* no bignums */
36759679 5186 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5187 /* If we have a flonum zero, a zero integer should
5188 do as well (e.g., in moveq). */
5189 && generic_floating_point_number.exponent == 0
5190 && generic_floating_point_number.low[0] == 0)))
5191 {
36759679 5192 /* HACK! Turn it into a long. */
252b5132
RH		 5193 LITTLENUM_TYPE words[6];
5194
36759679 5195 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5196 op (exp) = O_constant;
5197 adds (exp) = 0;
5198 subs (exp) = 0;
5199 offs (exp) = words[1] | (words[0] << 16);
5200 }
5201 else if (ok != 0)
5202 {
5203 op (exp) = O_constant;
5204 adds (exp) = 0;
5205 subs (exp) = 0;
5206 offs (exp) = (ok == 10) ? 1 : 0;
5207 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5208 (long) offs (exp));
252b5132
RH		 5209 }
5210 }
5211 else
5212 {
3e602632 5213 if (ok >= 10 && ok <= 80)
252b5132
RH		 5214 {
5215 op (exp) = O_constant;
5216 adds (exp) = 0;
5217 subs (exp) = 0;
5218 offs (exp) = (ok == 10) ? 1 : 0;
5219 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5220 (long) offs (exp));
252b5132
RH		 5221 }
5222 }
5223
5224 if (exp->size != SIZE_UNSPEC)
5225 {
5226 switch (exp->size)
5227 {
5228 case SIZE_UNSPEC:
5229 case SIZE_LONG:
5230 break;
5231 case SIZE_BYTE:
5232 if (!isbyte (offs (exp)))
5233 as_warn (_("expression doesn't fit in BYTE"));
5234 break;
5235 case SIZE_WORD:
5236 if (!isword (offs (exp)))
5237 as_warn (_("expression doesn't fit in WORD"));
5238 break;
5239 }
5240 }
5241
5242 return offs (exp);
5243}
5244
5245/* These are the back-ends for the various machine dependent pseudo-ops. */
5246
5247static void
31302357 5248s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5249{
5250 subseg_set (data_section, 1);
5251 demand_empty_rest_of_line ();
5252}
5253
5254static void
31302357 5255s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5256{
5257 subseg_set (data_section, 2);
5258 demand_empty_rest_of_line ();
5259}
5260
5261static void
31302357 5262s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5263{
5264 /* We don't support putting frags in the BSS segment, we fake it
5265 by marking in_bss, then looking at s_skip for clues. */
5266
5267 subseg_set (bss_section, 0);
5268 demand_empty_rest_of_line ();
5269}
5270
5271static void
31302357 5272s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5273{
5274 register int temp;
5275 register long temp_fill;
5276
5277 temp = 1; /* JF should be 2? */
5278 temp_fill = get_absolute_expression ();
92774660 5279 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5280 frag_align (temp, (int) temp_fill, 0);
5281 demand_empty_rest_of_line ();
5282 record_alignment (now_seg, temp);
5283}
5284
5285static void
31302357 5286s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5287{
5288 demand_empty_rest_of_line ();
5289}
5290\f
5291/* Pseudo-ops handled for MRI compatibility. */
5292
5293/* This function returns non-zero if the argument is a conditional
5294 pseudo-op. This is called when checking whether a pending
5295 alignment is needed. */
5296
5297int
31302357 5298m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5299{
5300 return (pop->poc_handler == s_mri_if
5301 || pop->poc_handler == s_mri_else);
5302}
5303
5304/* Handle an MRI style chip specification. */
5305
5306static void
31302357 5307mri_chip (void)
252b5132
RH		 5308{
5309 char *s;
5310 char c;
5311 int i;
5312
5313 s = input_line_pointer;
5314 /* We can't use get_symbol_end since the processor names are not proper
5315 symbols. */
5316 while (is_part_of_name (c = *input_line_pointer++))
5317 ;
5318 *--input_line_pointer = 0;
266abb8f
NS		 5319 for (i = 0; m68k_cpus[i].name; i++)
5320 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5321 break;
266abb8f 5322 if (!m68k_cpus[i].name)
252b5132
RH		 5323 {
5324 as_bad (_("%s: unrecognized processor name"), s);
5325 *input_line_pointer = c;
5326 ignore_rest_of_line ();
5327 return;
5328 }
5329 *input_line_pointer = c;
5330
5331 if (*input_line_pointer == '/')
5332 current_architecture = 0;
5333 else
5334 current_architecture &= m68881 | m68851;
266abb8f 5335 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5336 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5337
5338 while (*input_line_pointer == '/')
5339 {
5340 ++input_line_pointer;
5341 s = input_line_pointer;
5342 /* We can't use get_symbol_end since the processor names are not
5343 proper symbols. */
5344 while (is_part_of_name (c = *input_line_pointer++))
5345 ;
5346 *--input_line_pointer = 0;
5347 if (strcmp (s, "68881") == 0)
5348 current_architecture |= m68881;
5349 else if (strcmp (s, "68851") == 0)
5350 current_architecture |= m68851;
5351 *input_line_pointer = c;
5352 }
252b5132
RH		 5353}
5354
5355/* The MRI CHIP pseudo-op. */
5356
5357static void
31302357 5358s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5359{
5360 char *stop = NULL;
5361 char stopc;
5362
5363 if (flag_mri)
5364 stop = mri_comment_field (&stopc);
5365 mri_chip ();
5366 if (flag_mri)
5367 mri_comment_end (stop, stopc);
5368 demand_empty_rest_of_line ();
5369}
5370
5371/* The MRI FOPT pseudo-op. */
5372
5373static void
31302357 5374s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5375{
5376 SKIP_WHITESPACE ();
5377
5378 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5379 {
5380 int temp;
5381
5382 input_line_pointer += 3;
5383 temp = get_absolute_expression ();
5384 if (temp < 0 || temp > 7)
5385 as_bad (_("bad coprocessor id"));
5386 else
5387 m68k_float_copnum = COP0 + temp;
5388 }
5389 else
5390 {
5391 as_bad (_("unrecognized fopt option"));
5392 ignore_rest_of_line ();
5393 return;
5394 }
5395
5396 demand_empty_rest_of_line ();
5397}
5398
5399/* The structure used to handle the MRI OPT pseudo-op. */
5400
5401struct opt_action
5402{
5403 /* The name of the option. */
5404 const char *name;
5405
5406 /* If this is not NULL, just call this function. The first argument
5407 is the ARG field of this structure, the second argument is
5408 whether the option was negated. */
31302357 5409 void (*pfn) (int arg, int on);
252b5132
RH		 5410
5411 /* If this is not NULL, and the PFN field is NULL, set the variable
5412 this points to. Set it to the ARG field if the option was not
5413 negated, and the NOTARG field otherwise. */
5414 int *pvar;
5415
5416 /* The value to pass to PFN or to assign to *PVAR. */
5417 int arg;
5418
5419 /* The value to assign to *PVAR if the option is negated. If PFN is
5420 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5421 the option may not be negated. */
5422 int notarg;
5423};
5424
5425/* The table used to handle the MRI OPT pseudo-op. */
5426
31302357
AS		 5427static void skip_to_comma (int, int);
5428static void opt_nest (int, int);
5429static void opt_chip (int, int);
5430static void opt_list (int, int);
5431static void opt_list_symbols (int, int);
252b5132
RH		 5432
5433static const struct opt_action opt_table[] =
5434{
5435 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5436
5437 /* We do relaxing, so there is little use for these options. */
5438 { "b", 0, 0, 0, 0 },
5439 { "brs", 0, 0, 0, 0 },
5440 { "brb", 0, 0, 0, 0 },
5441 { "brl", 0, 0, 0, 0 },
5442 { "brw", 0, 0, 0, 0 },
5443
5444 { "c", 0, 0, 0, 0 },
5445 { "cex", 0, 0, 0, 0 },
5446 { "case", 0, &symbols_case_sensitive, 1, 0 },
5447 { "cl", 0, 0, 0, 0 },
5448 { "cre", 0, 0, 0, 0 },
5449 { "d", 0, &flag_keep_locals, 1, 0 },
5450 { "e", 0, 0, 0, 0 },
5451 { "f", 0, &flag_short_refs, 1, 0 },
5452 { "frs", 0, &flag_short_refs, 1, 0 },
5453 { "frl", 0, &flag_short_refs, 0, 1 },
5454 { "g", 0, 0, 0, 0 },
5455 { "i", 0, 0, 0, 0 },
5456 { "m", 0, 0, 0, 0 },
5457 { "mex", 0, 0, 0, 0 },
5458 { "mc", 0, 0, 0, 0 },
5459 { "md", 0, 0, 0, 0 },
5460 { "nest", opt_nest, 0, 0, 0 },
5461 { "next", skip_to_comma, 0, 0, 0 },
5462 { "o", 0, 0, 0, 0 },
5463 { "old", 0, 0, 0, 0 },
5464 { "op", skip_to_comma, 0, 0, 0 },
5465 { "pco", 0, 0, 0, 0 },
5466 { "p", opt_chip, 0, 0, 0 },
5467 { "pcr", 0, 0, 0, 0 },
5468 { "pcs", 0, 0, 0, 0 },
5469 { "r", 0, 0, 0, 0 },
5470 { "quick", 0, &m68k_quick, 1, 0 },
5471 { "rel32", 0, &m68k_rel32, 1, 0 },
5472 { "s", opt_list, 0, 0, 0 },
5473 { "t", opt_list_symbols, 0, 0, 0 },
5474 { "w", 0, &flag_no_warnings, 0, 1 },
5475 { "x", 0, 0, 0, 0 }
5476};
5477
8fce3f5e 5478#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5479
5480/* The MRI OPT pseudo-op. */
5481
5482static void
31302357 5483s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5484{
5485 do
5486 {
5487 int t;
5488 char *s;
5489 char c;
5490 int i;
5491 const struct opt_action *o;
5492
5493 SKIP_WHITESPACE ();
5494
5495 t = 1;
5496 if (*input_line_pointer == '-')
5497 {
5498 ++input_line_pointer;
5499 t = 0;
5500 }
5501 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5502 {
5503 input_line_pointer += 2;
5504 t = 0;
5505 }
5506
5507 s = input_line_pointer;
5508 c = get_symbol_end ();
5509
5510 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5511 {
5512 if (strcasecmp (s, o->name) == 0)
5513 {
5514 if (o->pfn)
5515 {
5516 /* Restore input_line_pointer now in case the option
5517 takes arguments. */
5518 *input_line_pointer = c;
5519 (*o->pfn) (o->arg, t);
5520 }
5521 else if (o->pvar != NULL)
5522 {
5523 if (! t && o->arg == o->notarg)
5524 as_bad (_("option `%s' may not be negated"), s);
5525 *input_line_pointer = c;
5526 *o->pvar = t ? o->arg : o->notarg;
5527 }
5528 else
5529 *input_line_pointer = c;
5530 break;
5531 }
5532 }
5533 if (i >= OPTCOUNT)
5534 {
5535 as_bad (_("option `%s' not recognized"), s);
5536 *input_line_pointer = c;
5537 }
5538 }
5539 while (*input_line_pointer++ == ',');
5540
5541 /* Move back to terminating character. */
5542 --input_line_pointer;
5543 demand_empty_rest_of_line ();
5544}
5545
5546/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5547 not support and which take arguments. */
252b5132
RH		 5548
5549static void
31302357 5550skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5551{
5552 while (*input_line_pointer != ','
5553 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5554 ++input_line_pointer;
5555}
5556
5557/* Handle the OPT NEST=depth option. */
5558
5559static void
31302357 5560opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5561{
5562 if (*input_line_pointer != '=')
5563 {
5564 as_bad (_("bad format of OPT NEST=depth"));
5565 return;
5566 }
5567
5568 ++input_line_pointer;
5569 max_macro_nest = get_absolute_expression ();
5570}
5571
5572/* Handle the OPT P=chip option. */
5573
5574static void
31302357 5575opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5576{
5577 if (*input_line_pointer != '=')
5578 {
5579 /* This is just OPT P, which we do not support. */
5580 return;
5581 }
5582
5583 ++input_line_pointer;
5584 mri_chip ();
5585}
5586
5587/* Handle the OPT S option. */
5588
5589static void
31302357 5590opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5591{
5592 listing_list (on);
5593}
5594
5595/* Handle the OPT T option. */
5596
5597static void
31302357 5598opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5599{
5600 if (on)
5601 listing |= LISTING_SYMBOLS;
5602 else
8a104df9 5603 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5604}
5605
5606/* Handle the MRI REG pseudo-op. */
5607
5608static void
31302357 5609s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5610{
5611 char *s;
5612 int c;
5613 struct m68k_op rop;
5614 int mask;
5615 char *stop = NULL;
5616 char stopc;
5617
5618 if (line_label == NULL)
5619 {
5620 as_bad (_("missing label"));
5621 ignore_rest_of_line ();
5622 return;
5623 }
5624
5625 if (flag_mri)
5626 stop = mri_comment_field (&stopc);
5627
5628 SKIP_WHITESPACE ();
5629
5630 s = input_line_pointer;
3882b010 5631 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5632#ifdef REGISTER_PREFIX
5633 || *input_line_pointer == REGISTER_PREFIX
5634#endif
5635 || *input_line_pointer == '/'
5636 || *input_line_pointer == '-')
5637 ++input_line_pointer;
5638 c = *input_line_pointer;
5639 *input_line_pointer = '\0';
5640
5641 if (m68k_ip_op (s, &rop) != 0)
5642 {
5643 if (rop.error == NULL)
5644 as_bad (_("bad register list"));
5645 else
5646 as_bad (_("bad register list: %s"), rop.error);
5647 *input_line_pointer = c;
5648 ignore_rest_of_line ();
5649 return;
5650 }
5651
5652 *input_line_pointer = c;
5653
5654 if (rop.mode == REGLST)
5655 mask = rop.mask;
5656 else if (rop.mode == DREG)
5657 mask = 1 << (rop.reg - DATA0);
5658 else if (rop.mode == AREG)
5659 mask = 1 << (rop.reg - ADDR0 + 8);
5660 else if (rop.mode == FPREG)
5661 mask = 1 << (rop.reg - FP0 + 16);
5662 else if (rop.mode == CONTROL
5663 && rop.reg == FPI)
5664 mask = 1 << 24;
5665 else if (rop.mode == CONTROL
5666 && rop.reg == FPS)
5667 mask = 1 << 25;
5668 else if (rop.mode == CONTROL
5669 && rop.reg == FPC)
5670 mask = 1 << 26;
5671 else
5672 {
5673 as_bad (_("bad register list"));
5674 ignore_rest_of_line ();
5675 return;
5676 }
5677
5678 S_SET_SEGMENT (line_label, reg_section);
5679 S_SET_VALUE (line_label, ~mask);
49309057 5680 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5681
5682 if (flag_mri)
5683 mri_comment_end (stop, stopc);
5684
5685 demand_empty_rest_of_line ();
5686}
5687
5688/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5689
5690struct save_opts
5691{
5692 struct save_opts *next;
5693 int abspcadd;
5694 int symbols_case_sensitive;
5695 int keep_locals;
5696 int short_refs;
5697 int architecture;
2da12c60 5698 const enum m68k_register *control_regs;
252b5132
RH		 5699 int quick;
5700 int rel32;
5701 int listing;
5702 int no_warnings;
5703 /* FIXME: We don't save OPT S. */
5704};
5705
5706/* This variable holds the stack of saved options. */
5707
5708static struct save_opts *save_stack;
5709
5710/* The MRI SAVE pseudo-op. */
5711
5712static void
31302357 5713s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5714{
5715 struct save_opts *s;
5716
5717 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5718 s->abspcadd = m68k_abspcadd;
5719 s->symbols_case_sensitive = symbols_case_sensitive;
5720 s->keep_locals = flag_keep_locals;
5721 s->short_refs = flag_short_refs;
5722 s->architecture = current_architecture;
2da12c60 5723 s->control_regs = control_regs;
252b5132
RH		 5724 s->quick = m68k_quick;
5725 s->rel32 = m68k_rel32;
5726 s->listing = listing;
5727 s->no_warnings = flag_no_warnings;
5728
5729 s->next = save_stack;
5730 save_stack = s;
5731
5732 demand_empty_rest_of_line ();
5733}
5734
5735/* The MRI RESTORE pseudo-op. */
5736
5737static void
31302357 5738s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5739{
5740 struct save_opts *s;
5741
5742 if (save_stack == NULL)
5743 {
5744 as_bad (_("restore without save"));
5745 ignore_rest_of_line ();
5746 return;
5747 }
5748
5749 s = save_stack;
5750 save_stack = s->next;
5751
5752 m68k_abspcadd = s->abspcadd;
5753 symbols_case_sensitive = s->symbols_case_sensitive;
5754 flag_keep_locals = s->keep_locals;
5755 flag_short_refs = s->short_refs;
5756 current_architecture = s->architecture;
2da12c60 5757 control_regs = s->control_regs;
252b5132
RH		 5758 m68k_quick = s->quick;
5759 m68k_rel32 = s->rel32;
5760 listing = s->listing;
5761 flag_no_warnings = s->no_warnings;
5762
5763 free (s);
5764
5765 demand_empty_rest_of_line ();
5766}
5767
5768/* Types of MRI structured control directives. */
5769
5770enum mri_control_type
5771{
5772 mri_for,
5773 mri_if,
5774 mri_repeat,
5775 mri_while
5776};
5777
5778/* This structure is used to stack the MRI structured control
5779 directives. */
5780
5781struct mri_control_info
5782{
5783 /* The directive within which this one is enclosed. */
5784 struct mri_control_info *outer;
5785
5786 /* The type of directive. */
5787 enum mri_control_type type;
5788
5789 /* Whether an ELSE has been in an IF. */
5790 int else_seen;
5791
5792 /* The add or sub statement at the end of a FOR. */
5793 char *incr;
5794
5795 /* The label of the top of a FOR or REPEAT loop. */
5796 char *top;
5797
5798 /* The label to jump to for the next iteration, or the else
5799 expression of a conditional. */
5800 char *next;
5801
5802 /* The label to jump to to break out of the loop, or the label past
5803 the end of a conditional. */
5804 char *bottom;
5805};
5806
5807/* The stack of MRI structured control directives. */
5808
5809static struct mri_control_info *mri_control_stack;
5810
5811/* The current MRI structured control directive index number, used to
5812 generate label names. */
5813
5814static int mri_control_index;
5815
252b5132
RH		 5816/* Assemble an instruction for an MRI structured control directive. */
5817
5818static void
31302357 5819mri_assemble (char *str)
252b5132
RH		 5820{
5821 char *s;
5822
5823 /* md_assemble expects the opcode to be in lower case. */
5824 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5825 *s = TOLOWER (*s);
252b5132
RH		 5826
5827 md_assemble (str);
5828}
5829
5830/* Generate a new MRI label structured control directive label name. */
5831
5832static char *
31302357 5833mri_control_label (void)
252b5132
RH		 5834{
5835 char *n;
5836
5837 n = (char *) xmalloc (20);
5838 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5839 ++mri_control_index;
5840 return n;
5841}
5842
5843/* Create a new MRI structured control directive. */
5844
5845static struct mri_control_info *
31302357 5846push_mri_control (enum mri_control_type type)
252b5132
RH		 5847{
5848 struct mri_control_info *n;
5849
5850 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5851
5852 n->type = type;
5853 n->else_seen = 0;
5854 if (type == mri_if || type == mri_while)
5855 n->top = NULL;
5856 else
5857 n->top = mri_control_label ();
5858 n->next = mri_control_label ();
5859 n->bottom = mri_control_label ();
5860
5861 n->outer = mri_control_stack;
5862 mri_control_stack = n;
5863
5864 return n;
5865}
5866
5867/* Pop off the stack of MRI structured control directives. */
5868
5869static void
31302357 5870pop_mri_control (void)
252b5132
RH		 5871{
5872 struct mri_control_info *n;
5873
5874 n = mri_control_stack;
5875 mri_control_stack = n->outer;
5876 if (n->top != NULL)
5877 free (n->top);
5878 free (n->next);
5879 free (n->bottom);
5880 free (n);
5881}
5882
5883/* Recognize a condition code in an MRI structured control expression. */
5884
5885static int
31302357 5886parse_mri_condition (int *pcc)
252b5132
RH		 5887{
5888 char c1, c2;
5889
5890 know (*input_line_pointer == '<');
5891
5892 ++input_line_pointer;
5893 c1 = *input_line_pointer++;
5894 c2 = *input_line_pointer++;
5895
5896 if (*input_line_pointer != '>')
5897 {
5898 as_bad (_("syntax error in structured control directive"));
5899 return 0;
5900 }
5901
5902 ++input_line_pointer;
5903 SKIP_WHITESPACE ();
5904
3882b010
L		 5905 c1 = TOLOWER (c1);
5906 c2 = TOLOWER (c2);
252b5132
RH		 5907
5908 *pcc = (c1 << 8) | c2;
5909
5910 return 1;
5911}
5912
5913/* Parse a single operand in an MRI structured control expression. */
5914
5915static int
31302357
AS		 5916parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5917 char **rightstart, char **rightstop)
252b5132
RH		 5918{
5919 char *s;
5920
5921 SKIP_WHITESPACE ();
5922
5923 *pcc = -1;
5924 *leftstart = NULL;
5925 *leftstop = NULL;
5926 *rightstart = NULL;
5927 *rightstop = NULL;
5928
5929 if (*input_line_pointer == '<')
5930 {
5931 /* It's just a condition code. */
5932 return parse_mri_condition (pcc);
5933 }
5934
5935 /* Look ahead for the condition code. */
5936 for (s = input_line_pointer; *s != '\0'; ++s)
5937 {
5938 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5939 break;
5940 }
5941 if (*s == '\0')
5942 {
5943 as_bad (_("missing condition code in structured control directive"));
5944 return 0;
5945 }
5946
5947 *leftstart = input_line_pointer;
5948 *leftstop = s;
5949 if (*leftstop > *leftstart
5950 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5951 --*leftstop;
5952
5953 input_line_pointer = s;
5954 if (! parse_mri_condition (pcc))
5955 return 0;
5956
5957 /* Look ahead for AND or OR or end of line. */
5958 for (s = input_line_pointer; *s != '\0'; ++s)
5959 {
e1f44d10
NC		 5960 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5961 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5962 ^^^ ^^ */
8a104df9
KH		 5963 if ((s == input_line_pointer
5964 || *(s-1) == ' '
5965 || *(s-1) == '\t')
5966 && ((strncasecmp (s, "AND", 3) == 0
5967 && (s[3] == '.' || ! is_part_of_name (s[3])))
5968 || (strncasecmp (s, "OR", 2) == 0
5969 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5970 break;
252b5132
RH		 5971 }
5972
5973 *rightstart = input_line_pointer;
5974 *rightstop = s;
5975 if (*rightstop > *rightstart
5976 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5977 --*rightstop;
5978
5979 input_line_pointer = s;
5980
5981 return 1;
5982}
5983
5984#define MCC(b1, b2) (((b1) << 8) | (b2))
5985
5986/* Swap the sense of a condition. This changes the condition so that
5987 it generates the same result when the operands are swapped. */
5988
5989static int
31302357 5990swap_mri_condition (int cc)
252b5132
RH		 5991{
5992 switch (cc)
5993 {
5994 case MCC ('h', 'i'): return MCC ('c', 's');
5995 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 5996 /* <HS> is an alias for <CC>. */
e1f44d10 5997 case MCC ('h', 's'):
252b5132 5998 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 5999 /* <LO> is an alias for <CS>. */
e1f44d10 6000 case MCC ('l', 'o'):
252b5132
RH		 6001 case MCC ('c', 's'): return MCC ('h', 'i');
6002 case MCC ('p', 'l'): return MCC ('m', 'i');
6003 case MCC ('m', 'i'): return MCC ('p', 'l');
6004 case MCC ('g', 'e'): return MCC ('l', 'e');
6005 case MCC ('l', 't'): return MCC ('g', 't');
6006 case MCC ('g', 't'): return MCC ('l', 't');
6007 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6008 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6009 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6010 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6011 case MCC ('v', 'c'):
6012 case MCC ('v', 's'):
6013 default :
6014 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6015 (char) (cc >> 8), (char) (cc));
6016 break;
252b5132
RH		 6017 }
6018 return cc;
6019}
6020
6021/* Reverse the sense of a condition. */
6022
6023static int
31302357 6024reverse_mri_condition (int cc)
252b5132
RH		 6025{
6026 switch (cc)
6027 {
6028 case MCC ('h', 'i'): return MCC ('l', 's');
6029 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6030 /* <HS> is an alias for <CC> */
6031 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6032 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6033 /* <LO> is an alias for <CS> */
6034 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6035 case MCC ('c', 's'): return MCC ('c', 'c');
6036 case MCC ('n', 'e'): return MCC ('e', 'q');
6037 case MCC ('e', 'q'): return MCC ('n', 'e');
6038 case MCC ('v', 'c'): return MCC ('v', 's');
6039 case MCC ('v', 's'): return MCC ('v', 'c');
6040 case MCC ('p', 'l'): return MCC ('m', 'i');
6041 case MCC ('m', 'i'): return MCC ('p', 'l');
6042 case MCC ('g', 'e'): return MCC ('l', 't');
6043 case MCC ('l', 't'): return MCC ('g', 'e');
6044 case MCC ('g', 't'): return MCC ('l', 'e');
6045 case MCC ('l', 'e'): return MCC ('g', 't');
6046 }
6047 return cc;
6048}
6049
6050/* Build an MRI structured control expression. This generates test
6051 and branch instructions. It goes to TRUELAB if the condition is
6052 true, and to FALSELAB if the condition is false. Exactly one of
6053 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6054 is the size qualifier for the expression. EXTENT is the size to
6055 use for the branch. */
6056
6057static void
31302357
AS		 6058build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6059 char *rightstart, char *rightstop,
6060 const char *truelab, const char *falselab,
6061 int extent)
252b5132
RH		 6062{
6063 char *buf;
6064 char *s;
6065
6066 if (leftstart != NULL)
6067 {
6068 struct m68k_op leftop, rightop;
6069 char c;
6070
6071 /* Swap the compare operands, if necessary, to produce a legal
6072 m68k compare instruction. Comparing a register operand with
6073 a non-register operand requires the register to be on the
6074 right (cmp, cmpa). Comparing an immediate value with
6075 anything requires the immediate value to be on the left
6076 (cmpi). */
6077
6078 c = *leftstop;
6079 *leftstop = '\0';
6080 (void) m68k_ip_op (leftstart, &leftop);
6081 *leftstop = c;
6082
6083 c = *rightstop;
6084 *rightstop = '\0';
6085 (void) m68k_ip_op (rightstart, &rightop);
6086 *rightstop = c;
6087
6088 if (rightop.mode == IMMED
6089 || ((leftop.mode == DREG || leftop.mode == AREG)
6090 && (rightop.mode != DREG && rightop.mode != AREG)))
6091 {
6092 char *temp;
6093
31302357
AS		 6094 /* Correct conditional handling:
6095 if #1 <lt> d0 then ;means if (1 < d0)
6096 ...
6097 endi
e1f44d10 6098
31302357 6099 should assemble to:
e1f44d10 6100
31302357
AS		 6101 cmp #1,d0 if we do *not* swap the operands
6102 bgt true we need the swapped condition!
6103 ble false
6104 true:
6105 ...
6106 false:
6107 */
252b5132
RH		 6108 temp = leftstart;
6109 leftstart = rightstart;
6110 rightstart = temp;
6111 temp = leftstop;
6112 leftstop = rightstop;
6113 rightstop = temp;
8a104df9
KH		 6114 }
6115 else
6116 {
e1f44d10 6117 cc = swap_mri_condition (cc);
252b5132
RH		 6118 }
6119 }
6120
6121 if (truelab == NULL)
6122 {
6123 cc = reverse_mri_condition (cc);
6124 truelab = falselab;
6125 }
92774660 6126
252b5132
RH		 6127 if (leftstart != NULL)
6128 {
6129 buf = (char *) xmalloc (20
6130 + (leftstop - leftstart)
6131 + (rightstop - rightstart));
6132 s = buf;
6133 *s++ = 'c';
6134 *s++ = 'm';
6135 *s++ = 'p';
6136 if (qual != '\0')
3882b010 6137 *s++ = TOLOWER (qual);
252b5132
RH		 6138 *s++ = ' ';
6139 memcpy (s, leftstart, leftstop - leftstart);
6140 s += leftstop - leftstart;
6141 *s++ = ',';
6142 memcpy (s, rightstart, rightstop - rightstart);
6143 s += rightstop - rightstart;
6144 *s = '\0';
6145 mri_assemble (buf);
6146 free (buf);
6147 }
92774660 6148
252b5132
RH		 6149 buf = (char *) xmalloc (20 + strlen (truelab));
6150 s = buf;
6151 *s++ = 'b';
6152 *s++ = cc >> 8;
6153 *s++ = cc & 0xff;
6154 if (extent != '\0')
3882b010 6155 *s++ = TOLOWER (extent);
252b5132
RH		 6156 *s++ = ' ';
6157 strcpy (s, truelab);
6158 mri_assemble (buf);
6159 free (buf);
6160}
6161
6162/* Parse an MRI structured control expression. This generates test
6163 and branch instructions. STOP is where the expression ends. It
6164 goes to TRUELAB if the condition is true, and to FALSELAB if the
6165 condition is false. Exactly one of TRUELAB and FALSELAB will be
6166 NULL, meaning to fall through. QUAL is the size qualifier for the
6167 expression. EXTENT is the size to use for the branch. */
6168
6169static void
31302357
AS		 6170parse_mri_control_expression (char *stop, int qual, const char *truelab,
6171 const char *falselab, int extent)
252b5132
RH		 6172{
6173 int c;
6174 int cc;
6175 char *leftstart;
6176 char *leftstop;
6177 char *rightstart;
6178 char *rightstop;
6179
6180 c = *stop;
6181 *stop = '\0';
6182
6183 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6184 &rightstart, &rightstop))
6185 {
6186 *stop = c;
6187 return;
6188 }
6189
6190 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6191 {
6192 const char *flab;
6193
6194 if (falselab != NULL)
6195 flab = falselab;
6196 else
6197 flab = mri_control_label ();
6198
6199 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6200 rightstop, (const char *) NULL, flab, extent);
6201
6202 input_line_pointer += 3;
6203 if (*input_line_pointer != '.'
6204 || input_line_pointer[1] == '\0')
6205 qual = '\0';
6206 else
6207 {
6208 qual = input_line_pointer[1];
6209 input_line_pointer += 2;
6210 }
6211
6212 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6213 &rightstart, &rightstop))
6214 {
6215 *stop = c;
6216 return;
6217 }
6218
6219 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6220 rightstop, truelab, falselab, extent);
6221
6222 if (falselab == NULL)
6223 colon (flab);
6224 }
6225 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6226 {
6227 const char *tlab;
6228
6229 if (truelab != NULL)
6230 tlab = truelab;
6231 else
6232 tlab = mri_control_label ();
6233
6234 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6235 rightstop, tlab, (const char *) NULL, extent);
6236
6237 input_line_pointer += 2;
6238 if (*input_line_pointer != '.'
6239 || input_line_pointer[1] == '\0')
6240 qual = '\0';
6241 else
6242 {
6243 qual = input_line_pointer[1];
6244 input_line_pointer += 2;
6245 }
6246
6247 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6248 &rightstart, &rightstop))
6249 {
6250 *stop = c;
6251 return;
6252 }
6253
6254 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6255 rightstop, truelab, falselab, extent);
6256
6257 if (truelab == NULL)
6258 colon (tlab);
6259 }
6260 else
6261 {
6262 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6263 rightstop, truelab, falselab, extent);
6264 }
6265
6266 *stop = c;
6267 if (input_line_pointer != stop)
6268 as_bad (_("syntax error in structured control directive"));
6269}
6270
6271/* Handle the MRI IF pseudo-op. This may be a structured control
6272 directive, or it may be a regular assembler conditional, depending
6273 on its operands. */
6274
6275static void
31302357 6276s_mri_if (int qual)
252b5132
RH		 6277{
6278 char *s;
6279 int c;
6280 struct mri_control_info *n;
6281
6282 /* A structured control directive must end with THEN with an
6283 optional qualifier. */
6284 s = input_line_pointer;
e1f44d10
NC		 6285 /* We only accept '*' as introduction of comments if preceded by white space
6286 or at first column of a line (I think this can't actually happen here?)
6287 This is important when assembling:
6288 if d0 <ne> 12(a0,d0*2) then
36759679 6289 if d0 <ne> #CONST*20 then. */
31302357
AS		 6290 while (! (is_end_of_line[(unsigned char) *s]
6291 || (flag_mri
6292 && *s == '*'
6293 && (s == input_line_pointer
6294 || *(s-1) == ' '
6295 || *(s-1) == '\t'))))
252b5132
RH		 6296 ++s;
6297 --s;
6298 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6299 --s;
6300
6301 if (s - input_line_pointer > 1
6302 && s[-1] == '.')
6303 s -= 2;
6304
6305 if (s - input_line_pointer < 3
6306 || strncasecmp (s - 3, "THEN", 4) != 0)
6307 {
6308 if (qual != '\0')
6309 {
6310 as_bad (_("missing then"));
6311 ignore_rest_of_line ();
6312 return;
6313 }
6314
6315 /* It's a conditional. */
6316 s_if (O_ne);
6317 return;
6318 }
6319
6320 /* Since this might be a conditional if, this pseudo-op will be
6321 called even if we are supported to be ignoring input. Double
6322 check now. Clobber *input_line_pointer so that ignore_input
6323 thinks that this is not a special pseudo-op. */
6324 c = *input_line_pointer;
6325 *input_line_pointer = 0;
6326 if (ignore_input ())
6327 {
6328 *input_line_pointer = c;
6329 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6330 ++input_line_pointer;
6331 demand_empty_rest_of_line ();
6332 return;
6333 }
6334 *input_line_pointer = c;
6335
6336 n = push_mri_control (mri_if);
6337
6338 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6339 n->next, s[1] == '.' ? s[2] : '\0');
6340
6341 if (s[1] == '.')
6342 input_line_pointer = s + 3;
6343 else
6344 input_line_pointer = s + 1;
6345
6346 if (flag_mri)
6347 {
6348 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6349 ++input_line_pointer;
6350 }
6351
6352 demand_empty_rest_of_line ();
6353}
6354
6355/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6356 structured IF, associate the ELSE with the IF. Otherwise, assume
6357 it is a conditional else. */
6358
6359static void
31302357 6360s_mri_else (int qual)
252b5132
RH		 6361{
6362 int c;
6363 char *buf;
6364 char q[2];
6365
6366 if (qual == '\0'
6367 && (mri_control_stack == NULL
6368 || mri_control_stack->type != mri_if
6369 || mri_control_stack->else_seen))
6370 {
6371 s_else (0);
6372 return;
6373 }
6374
6375 c = *input_line_pointer;
6376 *input_line_pointer = 0;
6377 if (ignore_input ())
6378 {
6379 *input_line_pointer = c;
6380 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6381 ++input_line_pointer;
6382 demand_empty_rest_of_line ();
6383 return;
6384 }
6385 *input_line_pointer = c;
6386
6387 if (mri_control_stack == NULL
6388 || mri_control_stack->type != mri_if
6389 || mri_control_stack->else_seen)
6390 {
6391 as_bad (_("else without matching if"));
6392 ignore_rest_of_line ();
6393 return;
6394 }
6395
6396 mri_control_stack->else_seen = 1;
6397
6398 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6399 q[0] = TOLOWER (qual);
252b5132
RH		 6400 q[1] = '\0';
6401 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6402 mri_assemble (buf);
6403 free (buf);
6404
6405 colon (mri_control_stack->next);
6406
6407 if (flag_mri)
6408 {
6409 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6410 ++input_line_pointer;
6411 }
6412
6413 demand_empty_rest_of_line ();
6414}
6415
6416/* Handle the MRI ENDI pseudo-op. */
6417
6418static void
31302357 6419s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6420{
6421 if (mri_control_stack == NULL
6422 || mri_control_stack->type != mri_if)
6423 {
6424 as_bad (_("endi without matching if"));
6425 ignore_rest_of_line ();
6426 return;
6427 }
6428
6429 /* ignore_input will not return true for ENDI, so we don't need to
6430 worry about checking it again here. */
6431
6432 if (! mri_control_stack->else_seen)
6433 colon (mri_control_stack->next);
6434 colon (mri_control_stack->bottom);
6435
6436 pop_mri_control ();
6437
6438 if (flag_mri)
6439 {
6440 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6441 ++input_line_pointer;
6442 }
6443
6444 demand_empty_rest_of_line ();
6445}
6446
6447/* Handle the MRI BREAK pseudo-op. */
6448
6449static void
31302357 6450s_mri_break (int extent)
252b5132
RH		 6451{
6452 struct mri_control_info *n;
6453 char *buf;
6454 char ex[2];
6455
6456 n = mri_control_stack;
6457 while (n != NULL
6458 && n->type != mri_for
6459 && n->type != mri_repeat
6460 && n->type != mri_while)
6461 n = n->outer;
6462 if (n == NULL)
6463 {
6464 as_bad (_("break outside of structured loop"));
6465 ignore_rest_of_line ();
6466 return;
6467 }
6468
6469 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6470 ex[0] = TOLOWER (extent);
252b5132
RH		 6471 ex[1] = '\0';
6472 sprintf (buf, "bra%s %s", ex, n->bottom);
6473 mri_assemble (buf);
6474 free (buf);
6475
6476 if (flag_mri)
6477 {
6478 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6479 ++input_line_pointer;
6480 }
6481
6482 demand_empty_rest_of_line ();
6483}
6484
6485/* Handle the MRI NEXT pseudo-op. */
6486
6487static void
31302357 6488s_mri_next (int extent)
252b5132
RH		 6489{
6490 struct mri_control_info *n;
6491 char *buf;
6492 char ex[2];
6493
6494 n = mri_control_stack;
6495 while (n != NULL
6496 && n->type != mri_for
6497 && n->type != mri_repeat
6498 && n->type != mri_while)
6499 n = n->outer;
6500 if (n == NULL)
6501 {
6502 as_bad (_("next outside of structured loop"));
6503 ignore_rest_of_line ();
6504 return;
6505 }
6506
6507 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6508 ex[0] = TOLOWER (extent);
252b5132
RH		 6509 ex[1] = '\0';
6510 sprintf (buf, "bra%s %s", ex, n->next);
6511 mri_assemble (buf);
6512 free (buf);
6513
6514 if (flag_mri)
6515 {
6516 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6517 ++input_line_pointer;
6518 }
6519
6520 demand_empty_rest_of_line ();
6521}
6522
6523/* Handle the MRI FOR pseudo-op. */
6524
6525static void
31302357 6526s_mri_for (int qual)
252b5132
RH		 6527{
6528 const char *varstart, *varstop;
6529 const char *initstart, *initstop;
6530 const char *endstart, *endstop;
6531 const char *bystart, *bystop;
6532 int up;
6533 int by;
6534 int extent;
6535 struct mri_control_info *n;
6536 char *buf;
6537 char *s;
6538 char ex[2];
6539
6540 /* The syntax is
6541 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6542 */
6543
6544 SKIP_WHITESPACE ();
6545 varstart = input_line_pointer;
6546
6547 /* Look for the '='. */
6548 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6549 && *input_line_pointer != '=')
6550 ++input_line_pointer;
6551 if (*input_line_pointer != '=')
6552 {
6553 as_bad (_("missing ="));
6554 ignore_rest_of_line ();
6555 return;
6556 }
6557
6558 varstop = input_line_pointer;
6559 if (varstop > varstart
6560 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6561 --varstop;
6562
6563 ++input_line_pointer;
6564
6565 initstart = input_line_pointer;
6566
6567 /* Look for TO or DOWNTO. */
6568 up = 1;
6569 initstop = NULL;
6570 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6571 {
6572 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6573 && ! is_part_of_name (input_line_pointer[2]))
6574 {
6575 initstop = input_line_pointer;
6576 input_line_pointer += 2;
6577 break;
6578 }
6579 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6580 && ! is_part_of_name (input_line_pointer[6]))
6581 {
6582 initstop = input_line_pointer;
6583 up = 0;
6584 input_line_pointer += 6;
6585 break;
6586 }
6587 ++input_line_pointer;
6588 }
6589 if (initstop == NULL)
6590 {
6591 as_bad (_("missing to or downto"));
6592 ignore_rest_of_line ();
6593 return;
6594 }
6595 if (initstop > initstart
6596 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6597 --initstop;
6598
6599 SKIP_WHITESPACE ();
6600 endstart = input_line_pointer;
6601
6602 /* Look for BY or DO. */
6603 by = 0;
6604 endstop = NULL;
6605 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6606 {
6607 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6608 && ! is_part_of_name (input_line_pointer[2]))
6609 {
6610 endstop = input_line_pointer;
6611 by = 1;
6612 input_line_pointer += 2;
6613 break;
6614 }
6615 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6616 && (input_line_pointer[2] == '.'
6617 || ! is_part_of_name (input_line_pointer[2])))
6618 {
6619 endstop = input_line_pointer;
6620 input_line_pointer += 2;
6621 break;
6622 }
6623 ++input_line_pointer;
6624 }
6625 if (endstop == NULL)
6626 {
6627 as_bad (_("missing do"));
6628 ignore_rest_of_line ();
6629 return;
6630 }
6631 if (endstop > endstart
6632 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6633 --endstop;
6634
6635 if (! by)
6636 {
6637 bystart = "#1";
6638 bystop = bystart + 2;
6639 }
6640 else
6641 {
6642 SKIP_WHITESPACE ();
6643 bystart = input_line_pointer;
6644
6645 /* Look for DO. */
6646 bystop = NULL;
6647 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6648 {
6649 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6650 && (input_line_pointer[2] == '.'
6651 || ! is_part_of_name (input_line_pointer[2])))
6652 {
6653 bystop = input_line_pointer;
6654 input_line_pointer += 2;
6655 break;
6656 }
6657 ++input_line_pointer;
6658 }
6659 if (bystop == NULL)
6660 {
6661 as_bad (_("missing do"));
6662 ignore_rest_of_line ();
6663 return;
6664 }
6665 if (bystop > bystart
6666 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6667 --bystop;
6668 }
6669
6670 if (*input_line_pointer != '.')
6671 extent = '\0';
6672 else
6673 {
6674 extent = input_line_pointer[1];
6675 input_line_pointer += 2;
6676 }
6677
6678 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6679 n = push_mri_control (mri_for);
6680
6681 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6682
36759679 6683 /* Move init,var. */
252b5132
RH		 6684 s = buf;
6685 *s++ = 'm';
6686 *s++ = 'o';
6687 *s++ = 'v';
6688 *s++ = 'e';
6689 if (qual != '\0')
3882b010 6690 *s++ = TOLOWER (qual);
252b5132
RH		 6691 *s++ = ' ';
6692 memcpy (s, initstart, initstop - initstart);
6693 s += initstop - initstart;
6694 *s++ = ',';
6695 memcpy (s, varstart, varstop - varstart);
6696 s += varstop - varstart;
6697 *s = '\0';
6698 mri_assemble (buf);
6699
6700 colon (n->top);
6701
36759679 6702 /* cmp end,var. */
252b5132
RH		 6703 s = buf;
6704 *s++ = 'c';
6705 *s++ = 'm';
6706 *s++ = 'p';
6707 if (qual != '\0')
3882b010 6708 *s++ = TOLOWER (qual);
252b5132
RH		 6709 *s++ = ' ';
6710 memcpy (s, endstart, endstop - endstart);
6711 s += endstop - endstart;
6712 *s++ = ',';
6713 memcpy (s, varstart, varstop - varstart);
6714 s += varstop - varstart;
6715 *s = '\0';
6716 mri_assemble (buf);
6717
36759679 6718 /* bcc bottom. */
3882b010 6719 ex[0] = TOLOWER (extent);
252b5132
RH		 6720 ex[1] = '\0';
6721 if (up)
6722 sprintf (buf, "blt%s %s", ex, n->bottom);
6723 else
6724 sprintf (buf, "bgt%s %s", ex, n->bottom);
6725 mri_assemble (buf);
6726
6727 /* Put together the add or sub instruction used by ENDF. */
6728 s = buf;
6729 if (up)
6730 strcpy (s, "add");
6731 else
6732 strcpy (s, "sub");
6733 s += 3;
6734 if (qual != '\0')
3882b010 6735 *s++ = TOLOWER (qual);
252b5132
RH		 6736 *s++ = ' ';
6737 memcpy (s, bystart, bystop - bystart);
6738 s += bystop - bystart;
6739 *s++ = ',';
6740 memcpy (s, varstart, varstop - varstart);
6741 s += varstop - varstart;
6742 *s = '\0';
6743 n->incr = buf;
6744
6745 if (flag_mri)
6746 {
6747 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6748 ++input_line_pointer;
6749 }
6750
6751 demand_empty_rest_of_line ();
6752}
6753
6754/* Handle the MRI ENDF pseudo-op. */
6755
6756static void
31302357 6757s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6758{
6759 if (mri_control_stack == NULL
6760 || mri_control_stack->type != mri_for)
6761 {
6762 as_bad (_("endf without for"));
6763 ignore_rest_of_line ();
6764 return;
6765 }
6766
6767 colon (mri_control_stack->next);
6768
6769 mri_assemble (mri_control_stack->incr);
6770
6771 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6772 mri_assemble (mri_control_stack->incr);
6773
6774 free (mri_control_stack->incr);
6775
6776 colon (mri_control_stack->bottom);
6777
6778 pop_mri_control ();
6779
6780 if (flag_mri)
6781 {
6782 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6783 ++input_line_pointer;
6784 }
6785
6786 demand_empty_rest_of_line ();
6787}
6788
6789/* Handle the MRI REPEAT pseudo-op. */
6790
6791static void
31302357 6792s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6793{
6794 struct mri_control_info *n;
6795
6796 n = push_mri_control (mri_repeat);
6797 colon (n->top);
6798 if (flag_mri)
6799 {
6800 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6801 ++input_line_pointer;
6802 }
6803 demand_empty_rest_of_line ();
6804}
6805
6806/* Handle the MRI UNTIL pseudo-op. */
6807
6808static void
31302357 6809s_mri_until (int qual)
252b5132
RH		 6810{
6811 char *s;
6812
6813 if (mri_control_stack == NULL
6814 || mri_control_stack->type != mri_repeat)
6815 {
6816 as_bad (_("until without repeat"));
6817 ignore_rest_of_line ();
6818 return;
6819 }
6820
6821 colon (mri_control_stack->next);
6822
6823 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6824 ;
6825
6826 parse_mri_control_expression (s, qual, (const char *) NULL,
6827 mri_control_stack->top, '\0');
6828
6829 colon (mri_control_stack->bottom);
6830
6831 input_line_pointer = s;
6832
6833 pop_mri_control ();
6834
6835 if (flag_mri)
6836 {
6837 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6838 ++input_line_pointer;
6839 }
6840
6841 demand_empty_rest_of_line ();
6842}
6843
6844/* Handle the MRI WHILE pseudo-op. */
6845
6846static void
31302357 6847s_mri_while (int qual)
252b5132
RH		 6848{
6849 char *s;
6850
6851 struct mri_control_info *n;
6852
6853 s = input_line_pointer;
e1f44d10
NC		 6854 /* We only accept '*' as introduction of comments if preceded by white space
6855 or at first column of a line (I think this can't actually happen here?)
6856 This is important when assembling:
6857 while d0 <ne> 12(a0,d0*2) do
36759679 6858 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6859 while (! (is_end_of_line[(unsigned char) *s]
6860 || (flag_mri
6861 && *s == '*'
6862 && (s == input_line_pointer
6863 || *(s-1) == ' '
6864 || *(s-1) == '\t'))))
252b5132
RH		 6865 s++;
6866 --s;
6867 while (*s == ' ' || *s == '\t')
6868 --s;
6869 if (s - input_line_pointer > 1
6870 && s[-1] == '.')
6871 s -= 2;
6872 if (s - input_line_pointer < 2
6873 || strncasecmp (s - 1, "DO", 2) != 0)
6874 {
6875 as_bad (_("missing do"));
6876 ignore_rest_of_line ();
6877 return;
6878 }
6879
6880 n = push_mri_control (mri_while);
6881
6882 colon (n->next);
6883
6884 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6885 s[1] == '.' ? s[2] : '\0');
6886
6887 input_line_pointer = s + 1;
6888 if (*input_line_pointer == '.')
6889 input_line_pointer += 2;
6890
6891 if (flag_mri)
6892 {
6893 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6894 ++input_line_pointer;
6895 }
6896
6897 demand_empty_rest_of_line ();
6898}
6899
6900/* Handle the MRI ENDW pseudo-op. */
6901
6902static void
31302357 6903s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6904{
6905 char *buf;
6906
6907 if (mri_control_stack == NULL
6908 || mri_control_stack->type != mri_while)
6909 {
6910 as_bad (_("endw without while"));
6911 ignore_rest_of_line ();
6912 return;
6913 }
6914
6915 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6916 sprintf (buf, "bra %s", mri_control_stack->next);
6917 mri_assemble (buf);
6918 free (buf);
6919
6920 colon (mri_control_stack->bottom);
6921
6922 pop_mri_control ();
6923
6924 if (flag_mri)
6925 {
6926 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6927 ++input_line_pointer;
6928 }
6929
6930 demand_empty_rest_of_line ();
6931}
6932\f
266abb8f
NS		 6933/* Parse a .cpu directive. */
6934
6935static void
6936s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6937{
6938 char saved_char;
6939 char *name;
6940
6941 if (initialized)
6942 {
6943 as_bad (_("already assembled instructions"));
6944 ignore_rest_of_line ();
6945 return;
6946 }
6947
6948 name = input_line_pointer;
6949 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6950 input_line_pointer++;
6951 saved_char = *input_line_pointer;
6952 *input_line_pointer = 0;
6953
6954 m68k_set_cpu (name, 1, 0);
6955
6956 *input_line_pointer = saved_char;
6957 demand_empty_rest_of_line ();
6958 return;
6959}
6960
6961/* Parse a .arch directive. */
6962
6963static void
6964s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6965{
6966 char saved_char;
6967 char *name;
6968
6969 if (initialized)
6970 {
6971 as_bad (_("already assembled instructions"));
6972 ignore_rest_of_line ();
6973 return;
6974 }
6975
6976 name = input_line_pointer;
6977 while (*input_line_pointer && *input_line_pointer != ','
6978 && !ISSPACE (*input_line_pointer))
6979 input_line_pointer++;
6980 saved_char = *input_line_pointer;
6981 *input_line_pointer = 0;
6982
6983 if (m68k_set_arch (name, 1, 0))
6984 {
6985 /* Scan extensions. */
6986 do
6987 {
6988 *input_line_pointer++ = saved_char;
6989 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6990 break;
6991 name = input_line_pointer;
6992 while (*input_line_pointer && *input_line_pointer != ','
6993 && !ISSPACE (*input_line_pointer))
6994 input_line_pointer++;
6995 saved_char = *input_line_pointer;
6996 *input_line_pointer = 0;
6997 }
6998 while (m68k_set_extension (name, 1, 0));
6999 }
7000
7001 *input_line_pointer = saved_char;
7002 demand_empty_rest_of_line ();
7003 return;
7004}
7005\f
7006/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7007 if none is found, the caller is responsible for emitting an error
7008 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7009 cpu name, if it begins with a '6' (possibly skipping an intervening
7010 'c'. We also allow a 'c' in the same place. if NEGATED is
7011 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7012 the option is indeed negated. */
7013
7014static const struct m68k_cpu *
7015m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7016 int allow_m, int *negated)
7017{
7018 /* allow negated value? */
7019 if (negated)
7020 {
7021 *negated = 0;
7022
7023 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7024 {
7025 arg += 3;
7026 *negated = 1;
7027 }
7028 }
7029
7030 /* Remove 'm' or 'mc' prefix from 68k variants. */
7031 if (allow_m)
7032 {
7033 if (arg[0] == 'm')
7034 {
7035 if (arg[1] == '6')
7036 arg += 1;
7037 else if (arg[1] == 'c' && arg[2] == '6')
7038 arg += 2;
7039 }
7040 }
7041 else if (arg[0] == 'c' && arg[1] == '6')
7042 arg += 1;
7043
7044 for (; table->name; table++)
7045 if (!strcmp (arg, table->name))
2da12c60
NS		 7046 {
7047 if (table->alias < -1 || table->alias > 1)
7048 as_bad (_("`%s' is deprecated, use `%s'"),
7049 table->name, table[table->alias < 0 ? 1 : -1].name);
7050 return table;
7051 }
266abb8f
NS		 7052 return 0;
7053}
7054
7055/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7056
7057static int
7058m68k_set_cpu (char const *name, int allow_m, int silent)
7059{
7060 const struct m68k_cpu *cpu;
7061
7062 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7063
7064 if (!cpu)
7065 {
7066 if (!silent)
7067 as_bad (_("cpu `%s' unrecognized"), name);
7068 return 0;
7069 }
7070
7071 if (selected_cpu && selected_cpu != cpu)
7072 {
7073 as_bad (_("already selected `%s' processor"),
7074 selected_cpu->name);
7075 return 0;
7076 }
7077 selected_cpu = cpu;
7078 return 1;
7079}
7080
7081/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7082
7083static int
7084m68k_set_arch (char const *name, int allow_m, int silent)
7085{
7086 const struct m68k_cpu *arch;
7087
7088 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7089
7090 if (!arch)
7091 {
7092 if (!silent)
7093 as_bad (_("architecture `%s' unrecognized"), name);
7094 return 0;
7095 }
7096
7097 if (selected_arch && selected_arch != arch)
7098 {
7099 as_bad (_("already selected `%s' architecture"),
7100 selected_arch->name);
7101 return 0;
7102 }
7103
7104 selected_arch = arch;
7105 return 1;
7106}
7107
7108/* Set the architecture extension, issuing errors if it is
7109 unrecognized, or invalid */
7110
7111static int
7112m68k_set_extension (char const *name, int allow_m, int silent)
7113{
7114 int negated;
7115 const struct m68k_cpu *ext;
7116
7117 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7118
7119 if (!ext)
7120 {
7121 if (!silent)
7122 as_bad (_("extension `%s' unrecognized"), name);
7123 return 0;
7124 }
7125
7126 if (negated)
7127 not_current_architecture |= ext->arch;
7128 else
7129 current_architecture |= ext->arch;
7130 return 1;
7131}
7132
31302357
AS		 7133/* md_parse_option
7134 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7135 */
252b5132
RH		 7136
7137#ifdef OBJ_ELF
5a38dc70 7138const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7139#else
5a38dc70 7140const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7141#endif
7142
7143struct option md_longopts[] = {
7144#define OPTION_PIC (OPTION_MD_BASE)
7145 {"pic", no_argument, NULL, OPTION_PIC},
7146#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7147 {"register-prefix-optional", no_argument, NULL,
7148 OPTION_REGISTER_PREFIX_OPTIONAL},
7149#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7150 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7151#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7152 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7153#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7154 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7155#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7156 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7157#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7158 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7159#define OPTION_PCREL (OPTION_MD_BASE + 7)
7160 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7161 {NULL, no_argument, NULL, 0}
7162};
bc805888 7163size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7164
7165int
31302357 7166md_parse_option (int c, char *arg)
252b5132
RH		 7167{
7168 switch (c)
7169 {
7170 case 'l': /* -l means keep external to 2 bit offset
36759679 7171 rather than 16 bit one. */
252b5132
RH		 7172 flag_short_refs = 1;
7173 break;
7174
7175 case 'S': /* -S means that jbsr's always turn into
7176 jsr's. */
7177 flag_long_jumps = 1;
7178 break;
7179
28e7409f
NC		 7180 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7181 branches into absolute jumps. */
7182 flag_keep_pcrel = 1;
7183 break;
7184
252b5132
RH		 7185 case OPTION_PIC:
7186 case 'k':
7187 flag_want_pic = 1;
36759679 7188 break; /* -pic, Position Independent Code. */
252b5132
RH		 7189
7190 case OPTION_REGISTER_PREFIX_OPTIONAL:
7191 flag_reg_prefix_optional = 1;
7192 reg_prefix_optional_seen = 1;
7193 break;
7194
7195 /* -V: SVR4 argument to print version ID. */
7196 case 'V':
7197 print_version_id ();
7198 break;
7199
7200 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7201 should be emitted or not. FIXME: Not implemented. */
7202 case 'Q':
7203 break;
7204
7205 case OPTION_BITWISE_OR:
7206 {
7207 char *n, *t;
7208 const char *s;
7209
7210 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7211 t = n;
7212 for (s = m68k_comment_chars; *s != '\0'; s++)
7213 if (*s != '|')
7214 *t++ = *s;
7215 *t = '\0';
7216 m68k_comment_chars = n;
7217 }
7218 break;
7219
7220 case OPTION_BASE_SIZE_DEFAULT_16:
7221 m68k_index_width_default = SIZE_WORD;
7222 break;
7223
7224 case OPTION_BASE_SIZE_DEFAULT_32:
7225 m68k_index_width_default = SIZE_LONG;
7226 break;
7227
7228 case OPTION_DISP_SIZE_DEFAULT_16:
7229 m68k_rel32 = 0;
7230 m68k_rel32_from_cmdline = 1;
7231 break;
7232
7233 case OPTION_DISP_SIZE_DEFAULT_32:
7234 m68k_rel32 = 1;
7235 m68k_rel32_from_cmdline = 1;
7236 break;
7237
266abb8f
NS		 7238 case 'A':
7239#if WARN_DEPRECATED
7240 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7241 arg, arg));
7242#endif
7243 /* Intentional fall-through. */
7244 case 'm':
7245 if (!strncmp (arg, "arch=", 5))
7246 m68k_set_arch (arg + 5, 1, 0);
7247 else if (!strncmp (arg, "cpu=", 4))
7248 m68k_set_cpu (arg + 4, 1, 0);
7249 else if (m68k_set_extension (arg, 0, 1))
7250 ;
0b2e31dc
NS		 7251 else if (m68k_set_arch (arg, 0, 1))
7252 ;
266abb8f
NS		 7253 else if (m68k_set_cpu (arg, 0, 1))
7254 ;
7255 else
7256 return 0;
7257 break;
7258
252b5132
RH		 7259 default:
7260 return 0;
7261 }
7262
7263 return 1;
7264}
7265
266abb8f
NS		 7266/* Setup tables from the selected arch and/or cpu */
7267
7268static void
7269m68k_init_arch (void)
7270{
266abb8f
NS		 7271 if (not_current_architecture & current_architecture)
7272 {
7273 as_bad (_("architecture features both enabled and disabled"));
7274 not_current_architecture &= ~current_architecture;
7275 }
7276 if (selected_arch)
2da12c60
NS		 7277 {
7278 current_architecture |= selected_arch->arch;
7279 control_regs = selected_arch->control_regs;
7280 }
0b2e31dc
NS		 7281 else
7282 current_architecture |= selected_cpu->arch;
0b2e31dc 7283
2da12c60
NS		 7284 current_architecture &= ~not_current_architecture;
7285
377260ba
NS		 7286 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7287 {
7288 /* Determine which float is really meant. */
7289 if (current_architecture & (m68k_mask & ~m68881))
7290 current_architecture ^= cfloat;
7291 else
7292 current_architecture ^= m68881;
7293 }
7294
0b2e31dc 7295 if (selected_cpu)
266abb8f 7296 {
2da12c60 7297 control_regs = selected_cpu->control_regs;
0b2e31dc 7298 if (current_architecture & ~selected_cpu->arch)
266abb8f 7299 {
0b2e31dc
NS		 7300 as_bad (_("selected processor does not have all features of selected architecture"));
7301 current_architecture
7302 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7303 }
7304 }
266abb8f 7305
266abb8f
NS		 7306 if ((current_architecture & m68k_mask)
7307 && (current_architecture & ~m68k_mask))
7308 {
7309 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7310 if (current_architecture & m68k_mask)
266abb8f
NS		 7311 current_architecture &= m68k_mask;
7312 else
7313 current_architecture &= ~m68k_mask;
7314 }
7315
7316 /* Permit m68881 specification with all cpus; those that can't work
7317 with a coprocessor could be doing emulation. */
7318 if (current_architecture & m68851)
7319 {
7320 if (current_architecture & m68040)
7321 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7322 }
7323 /* What other incompatibilities could we check for? */
7324
266abb8f
NS		 7325 if (cpu_of_arch (current_architecture) < m68020
7326 || arch_coldfire_p (current_architecture))
7327 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7328
7329 initialized = 1;
7330}
7331
252b5132 7332void
31302357 7333md_show_usage (FILE *stream)
252b5132 7334{
76f57f3a 7335 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7336 int i;
7337 unsigned int default_arch;
76f57f3a 7338
8a104df9 7339 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7340 if (*default_cpu == 'm')
7341 default_cpu++;
266abb8f 7342 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7343 {
266abb8f 7344 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7345 {
266abb8f 7346 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7347 while (m68k_cpus[i].alias > 0)
7348 i--;
7349 while (m68k_cpus[i].alias < 0)
7350 i++;
7351 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7352 }
7353 }
7354
bc805888 7355 fprintf (stream, _("\
266abb8f
NS		 7356-march=<arch> set architecture\n\
7357-mcpu=<cpu> set cpu [default %s]\n\
7358"), default_cpu);
7359 for (i = 0; m68k_extensions[i].name; i++)
7360 fprintf (stream, _("\
0b2e31dc
NS		 7361-m[no-]%-16s enable/disable%s architecture extension\n\
7362"), m68k_extensions[i].name,
7363 m68k_extensions[i].alias > 0 ? " ColdFire"
7364 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7365
bc805888 7366 fprintf (stream, _("\
266abb8f 7367-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7368-pic, -k generate position independent code\n\
7369-S turn jbsr into jsr\n\
28e7409f 7370--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7371--register-prefix-optional\n\
7372 recognize register names without prefix character\n\
266abb8f 7373--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7374--base-size-default-16 base reg without size is 16 bits\n\
7375--base-size-default-32 base reg without size is 32 bits (default)\n\
7376--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7377--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7378"));
7379
7380 fprintf (stream, _("Architecture variants are: "));
7381 for (i = 0; m68k_archs[i].name; i++)
7382 {
7383 if (i)
7384 fprintf (stream, " | ");
7385 fprintf (stream, m68k_archs[i].name);
7386 }
7387 fprintf (stream, "\n");
7388
7389 fprintf (stream, _("Processor variants are: "));
7390 for (i = 0; m68k_cpus[i].name; i++)
7391 {
7392 if (i)
7393 fprintf (stream, " | ");
7394 fprintf (stream, m68k_cpus[i].name);
7395 }
7396 fprintf (stream, _("\n"));
252b5132
RH		 7397}
7398\f
7399#ifdef TEST2
7400
7401/* TEST2: Test md_assemble() */
36759679
NC		 7402/* Warning, this routine probably doesn't work anymore. */
7403int
31302357 7404main (void)
252b5132
RH		 7405{
7406 struct m68k_it the_ins;
7407 char buf[120];
7408 char *cp;
7409 int n;
7410
7411 m68k_ip_begin ();
7412 for (;;)
7413 {
7414 if (!gets (buf) || !*buf)
7415 break;
7416 if (buf[0] == '|' || buf[1] == '.')
7417 continue;
7418 for (cp = buf; *cp; cp++)
7419 if (*cp == '\t')
7420 *cp = ' ';
7421 if (is_label (buf))
7422 continue;
7423 memset (&the_ins, '\0', sizeof (the_ins));
7424 m68k_ip (&the_ins, buf);
7425 if (the_ins.error)
7426 {
7427 printf (_("Error %s in %s\n"), the_ins.error, buf);
7428 }
7429 else
7430 {
7431 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7432 for (n = 0; n < the_ins.numo; n++)
7433 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7434 printf (" ");
7435 print_the_insn (&the_ins.opcode[0], stdout);
7436 (void) putchar ('\n');
7437 }
7438 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7439 {
7440 if (the_ins.operands[n].error)
7441 {
7442 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7443 continue;
7444 }
31302357
AS		 7445 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7446 the_ins.operands[n].reg);
252b5132 7447 if (the_ins.operands[n].b_const)
31302357
AS		 7448 printf ("Constant: '%.*s', ",
7449 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7450 the_ins.operands[n].b_const);
7451 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7452 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7453 if (the_ins.operands[n].b_iadd)
31302357
AS		 7454 printf ("Iadd: '%.*s',",
7455 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7456 the_ins.operands[n].b_iadd);
7457 putchar ('\n');
252b5132
RH		 7458 }
7459 }
7460 m68k_ip_end ();
7461 return 0;
7462}
7463
31302357
AS		 7464int
7465is_label (char *str)
252b5132
RH		 7466{
7467 while (*str == ' ')
7468 str++;
7469 while (*str && *str != ' ')
7470 str++;
7471 if (str[-1] == ':' || str[1] == '=')
7472 return 1;
7473 return 0;
7474}
7475
7476#endif
7477
7478/* Possible states for relaxation:
7479
7480 0 0 branch offset byte (bra, etc)
7481 0 1 word
7482 0 2 long
7483
7484 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7485 1 1 word
7486 1 2 long
7487
7488 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7489 2 1 word-long
7490 2 2 long-word
7491 2 3 long-long
7492
7493 */
7494
7495/* We have no need to default values of symbols. */
7496
252b5132 7497symbolS *
31302357 7498md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7499{
7500 return 0;
7501}
7502
7503/* Round up a section size to the appropriate boundary. */
7504valueT
31302357 7505md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7506{
7507#ifdef OBJ_AOUT
252b5132
RH		 7508 /* For a.out, force the section size to be aligned. If we don't do
7509 this, BFD will align it for us, but it will not write out the
7510 final bytes of the section. This may be a bug in BFD, but it is
7511 easier to fix it here since that is how the other a.out targets
7512 work. */
7513 int align;
7514
7515 align = bfd_get_section_alignment (stdoutput, segment);
7516 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7517#endif
7518
7519 return size;
7520}
7521
7522/* Exactly what point is a PC-relative offset relative TO?
7523 On the 68k, it is relative to the address of the first extension
7524 word. The difference between the addresses of the offset and the
92774660 7525 first extension word is stored in fx_pcrel_adjust. */
252b5132 7526long
31302357 7527md_pcrel_from (fixS *fixP)
252b5132
RH		 7528{
7529 int adjust;
7530
8390138c
AS		 7531 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7532 sign extend the value here. */
7533 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7534 if (adjust == 64)
7535 adjust = -1;
7536 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7537}
7538
0d96863f 7539#ifdef OBJ_ELF
8a104df9 7540void
31302357 7541m68k_elf_final_processing (void)
0d96863f 7542{
266abb8f
NS		 7543 unsigned flags = 0;
7544
238d258f 7545 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7546 flags |= EF_M68K_CFV4E;
7547 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7548 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7549 flags |= EF_M68K_CPU32;
7550 else if (cpu_of_arch (current_architecture) & fido_a)
7551 flags |= EF_M68K_FIDO;
8a104df9
KH		 7552 else if ((cpu_of_arch (current_architecture) & m68000up)
7553 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7554 flags |= EF_M68K_M68000;
7555
7556 if (current_architecture & mcfisa_a)
7557 {
0b2e31dc
NS		 7558 static const unsigned isa_features[][2] =
7559 {
c694fd50
KH		 7560 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7561 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7562 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7563 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7564 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
0b2e31dc
NS		 7565 {0,0},
7566 };
7567 static const unsigned mac_features[][2] =
7568 {
c694fd50
KH		 7569 {EF_M68K_CF_MAC, mcfmac},
7570 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7571 {0,0},
7572 };
7573 unsigned ix;
7574 unsigned pattern;
266abb8f 7575
0b2e31dc
NS		 7576 pattern = (current_architecture
7577 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7578 for (ix = 0; isa_features[ix][1]; ix++)
7579 {
7580 if (pattern == isa_features[ix][1])
7581 {
7582 flags |= isa_features[ix][0];
7583 break;
7584 }
7585 }
7586 if (!isa_features[ix][1])
7587 {
7588 cf_bad:
7589 as_warn (_("Not a defined coldfire architecture"));
7590 }
7591 else
7592 {
7593 if (current_architecture & cfloat)
c694fd50 7594 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7595
0b2e31dc
NS		 7596 pattern = current_architecture & (mcfmac|mcfemac);
7597 if (pattern)
7598 {
7599 for (ix = 0; mac_features[ix][1]; ix++)
7600 {
7601 if (pattern == mac_features[ix][1])
7602 {
7603 flags |= mac_features[ix][0];
7604 break;
7605 }
7606 }
7607 if (!mac_features[ix][1])
7608 goto cf_bad;
7609 }
7610 }
266abb8f
NS		 7611 }
7612 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7613}
7614#endif
c04898f8
AS		 7615
7616int
1df69f4f 7617tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 7618{
7619 unsigned int regnum;
7620 static const char *const regnames[] =
7621 {
7622 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7623 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7624 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7625 "pc"
7626 };
7627
7628 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7629 if (strcmp (regname, regnames[regnum]) == 0)
7630 return regnum;
7631
7632 return -1;
7633}
7634
7635void
7636tc_m68k_frame_initial_instructions (void)
7637{
7638 static int sp_regno = -1;
7639
7640 if (sp_regno < 0)
7641 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7642
7643 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7644 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7645}
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