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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
22184a77 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
78336706
NS		 176 RAMBAR0, RAMBAR1, RAMBAR, MBAR,
177 0
178};
179static const enum m68k_register mcf5206_ctrl[] = {
180 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
252b5132
RH		 181 0
182};
2da12c60 183static const enum m68k_register mcf5208_ctrl[] = {
78336706 184 CACR, ACR0, ACR1, VBR, RAMBAR, RAMBAR1,
266abb8f
NS		 185 0
186};
96e0bbcc 187static const enum m68k_register mcf5210a_ctrl[] = {
78336706 188 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, RAMBAR1, MBAR,
96e0bbcc
NS		 189 0
190};
2da12c60 191static const enum m68k_register mcf5213_ctrl[] = {
78336706 192 VBR, RAMBAR, RAMBAR1, FLASHBAR,
266abb8f
NS		 193 0
194};
2da12c60 195static const enum m68k_register mcf5216_ctrl[] = {
78336706 196 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
266abb8f
NS		 197 0
198};
d5be9593
NS		 199static const enum m68k_register mcf52223_ctrl[] = {
200 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
201 0
202};
96e0bbcc 203static const enum m68k_register mcf52235_ctrl[] = {
78336706 204 VBR, FLASHBAR, RAMBAR, RAMBAR1,
96e0bbcc
NS		 205 0
206};
207static const enum m68k_register mcf5225_ctrl[] = {
78336706 208 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, MBAR, RAMBAR1,
96e0bbcc
NS		 209 0
210};
2da12c60 211static const enum m68k_register mcf5235_ctrl[] = {
78336706 212 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
e80e0390
NC		 213 0
214};
2da12c60 215static const enum m68k_register mcf5249_ctrl[] = {
78336706 216 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, RAMBAR, MBAR, MBAR2,
3e602632
NC		 217 0
218};
2da12c60
NS		 219static const enum m68k_register mcf5250_ctrl[] = {
220 VBR,
221 0
222};
d5be9593
NS		 223static const enum m68k_register mcf5253_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR,
225 0
226};
2da12c60 227static const enum m68k_register mcf5271_ctrl[] = {
78336706 228 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 229 0
230};
231static const enum m68k_register mcf5272_ctrl[] = {
78336706 232 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR_ALT, RAMBAR0, MBAR,
2da12c60
NS		 233 0
234};
235static const enum m68k_register mcf5275_ctrl[] = {
78336706 236 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 237 0
238};
239static const enum m68k_register mcf5282_ctrl[] = {
78336706
NS		 240 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR, RAMBAR1,
241 0
242};
243static const enum m68k_register mcf5307_ctrl[] = {
244 CACR, ACR0, ACR1, VBR, RAMBAR0, RAMBAR_ALT, MBAR,
2da12c60
NS		 245 0
246};
247static const enum m68k_register mcf5329_ctrl[] = {
78336706 248 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 249 0
250};
251static const enum m68k_register mcf5373_ctrl[] = {
78336706 252 VBR, CACR, ACR0, ACR1, RAMBAR, RAMBAR1,
2da12c60
NS		 253 0
254};
255static const enum m68k_register mcfv4e_ctrl[] = {
a8e24a56
NS		 256 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
257 VBR, PC, ROMBAR0, ROMBAR1, RAMBAR0, RAMBAR1,
258 MBAR, SECMBAR,
259 MPCR /* Multiprocessor Control register */,
260 EDRAMBAR /* Embedded DRAM Base Address Register */,
261 /* Permutation control registers. */
3e602632
NC		 262 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
263 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
a8e24a56
NS		 264 /* Legacy names */
265 TC /* ASID */, BUSCR /* MMUBAR */,
266 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
267 MBAR1 /* MBAR */, MBAR2 /* SECMBAR */, MBAR0 /* SECMBAR */,
78336706 268 ROMBAR /* ROMBAR0 */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 269 0
270};
9a2e615a
NS		 271static const enum m68k_register mcf54455_ctrl[] = {
272 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
273 VBR, PC, RAMBAR1, MBAR,
274 /* Legacy names */
275 TC /* ASID */, BUSCR /* MMUBAR */,
276 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
277 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
278 0
279};
a8e24a56
NS		 280static const enum m68k_register mcf5475_ctrl[] = {
281 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
282 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
283 /* Legacy names */
284 TC /* ASID */, BUSCR /* MMUBAR */,
285 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 286 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
a8e24a56
NS		 287 0
288};
289static const enum m68k_register mcf5485_ctrl[] = {
290 CACR, ASID, ACR0, ACR1, ACR2, ACR3, MMUBAR,
291 VBR, PC, RAMBAR0, RAMBAR1, MBAR,
292 /* Legacy names */
293 TC /* ASID */, BUSCR /* MMUBAR */,
294 ITT0 /* ACR0 */, ITT1 /* ACR1 */, DTT0 /* ACR2 */, DTT1 /* ACR3 */,
78336706 295 MBAR1 /* MBAR */, RAMBAR /* RAMBAR1 */,
3e602632
NC		 296 0
297};
f7ec513b
KH		 298static const enum m68k_register fido_ctrl[] = {
299 SFC, DFC, USP, VBR, CAC, MBB,
300 0
301};
2da12c60 302#define cpu32_ctrl m68010_ctrl
252b5132
RH		 303
304static const enum m68k_register *control_regs;
305
36759679 306/* Internal form of a 68020 instruction. */
252b5132
RH		 307struct m68k_it
308{
309 const char *error;
36759679 310 const char *args; /* List of opcode info. */
252b5132
RH		 311 int numargs;
312
36759679 313 int numo; /* Number of shorts in opcode. */
252b5132
RH		 314 short opcode[11];
315
316 struct m68k_op operands[6];
317
36759679 318 int nexp; /* Number of exprs in use. */
252b5132
RH		 319 struct m68k_exp exprs[4];
320
36759679 321 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 322 struct
323 {
36759679 324 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 325 symbolS *fadd;
326 offsetT foff;
327 int fragty;
328 }
329 fragb[4];
330
36759679 331 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 332 struct
333 {
334 int n;
335 expressionS exp;
336 char wid;
337 char pcrel;
338 /* In a pc relative address the difference between the address
339 of the offset and the address that the offset is relative
340 to. This depends on the addressing mode. Basically this
341 is the value to put in the offset field to address the
342 first byte of the offset, without regarding the special
343 significance of some values (in the branch instruction, for
344 example). */
345 int pcrel_fix;
346#ifdef OBJ_ELF
347 /* Whether this expression needs special pic relocation, and if
348 so, which. */
349 enum pic_relocation pic_reloc;
350#endif
351 }
36759679 352 reloc[5]; /* Five is enough??? */
252b5132
RH		 353};
354
9840d27e 355#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a | fido_a))
252b5132
RH		 356#define float_of_arch(x) ((x) & mfloat)
357#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 358#define arch_coldfire_p(x) ((x) & mcfisa_a)
359#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 360
36759679 361/* Macros for determining if cpu supports a specific addressing mode. */
9a2e615a
NS		 362#define HAVE_LONG_DISP(x) \
363 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
364#define HAVE_LONG_CALL(x) \
365 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
366#define HAVE_LONG_COND(x) \
367 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b|mcfisa_c))
368#define HAVE_LONG_BRANCH(x) \
369 ((x) & (m68020|m68030|m68040|m68060|cpu32|fido_a|mcfisa_b))
252b5132 370
36759679 371static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 372
373#define op(ex) ((ex)->exp.X_op)
374#define adds(ex) ((ex)->exp.X_add_symbol)
375#define subs(ex) ((ex)->exp.X_op_symbol)
376#define offs(ex) ((ex)->exp.X_add_number)
377
36759679 378/* Macros for adding things to the m68k_it struct. */
31302357 379#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 380
36759679
NC		 381/* Like addword, but goes BEFORE general operands. */
382
252b5132 383static void
31302357 384insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 385{
386 int z;
07726851 387 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 388 the_ins.opcode[z] = the_ins.opcode[z - 1];
389 for (z = 0; z < the_ins.nrel; z++)
390 the_ins.reloc[z].n += 2;
252b5132
RH		 391 for (z = 0; z < the_ins.nfrag; z++)
392 the_ins.fragb[z].fragoff++;
8a104df9 393 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 394 the_ins.numo++;
395}
396
397/* The numo+1 kludge is so we can hit the low order byte of the prev word.
398 Blecch. */
399static void
31302357 400add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 401{
31302357
AS		 402 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
403 ? the_ins.numo * 2 - 1
404 : (width == 'b'
405 ? the_ins.numo * 2 + 1
406 : the_ins.numo * 2));
252b5132
RH		 407 the_ins.reloc[the_ins.nrel].exp = exp->exp;
408 the_ins.reloc[the_ins.nrel].wid = width;
409 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
410#ifdef OBJ_ELF
411 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
412#endif
413 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
414}
415
416/* Cause an extra frag to be generated here, inserting up to 10 bytes
417 (that value is chosen in the frag_var call in md_assemble). TYPE
418 is the subtype of the frag to be generated; its primary type is
419 rs_machine_dependent.
420
421 The TYPE parameter is also used by md_convert_frag_1 and
422 md_estimate_size_before_relax. The appropriate type of fixup will
423 be emitted by md_convert_frag_1.
424
425 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
426static void
31302357 427add_frag (symbolS *add, offsetT off, int type)
252b5132 428{
8a104df9
KH		 429 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
430 the_ins.fragb[the_ins.nfrag].fadd = add;
431 the_ins.fragb[the_ins.nfrag].foff = off;
432 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 433}
434
435#define isvar(ex) \
436 (op (ex) != O_constant && op (ex) != O_big)
437
31302357
AS		 438static char *crack_operand (char *str, struct m68k_op *opP);
439static int get_num (struct m68k_exp *exp, int ok);
440static int reverse_16_bits (int in);
441static int reverse_8_bits (int in);
442static void install_gen_operand (int mode, int val);
443static void install_operand (int mode, int val);
444static void s_bss (int);
445static void s_data1 (int);
446static void s_data2 (int);
447static void s_even (int);
448static void s_proc (int);
449static void s_chip (int);
450static void s_fopt (int);
451static void s_opt (int);
452static void s_reg (int);
453static void s_restore (int);
454static void s_save (int);
455static void s_mri_if (int);
456static void s_mri_else (int);
457static void s_mri_endi (int);
458static void s_mri_break (int);
459static void s_mri_next (int);
460static void s_mri_for (int);
461static void s_mri_endf (int);
462static void s_mri_repeat (int);
463static void s_mri_until (int);
464static void s_mri_while (int);
465static void s_mri_endw (int);
266abb8f
NS		 466static void s_m68k_cpu (int);
467static void s_m68k_arch (int);
468
469struct m68k_cpu
470{
471 unsigned long arch; /* Architecture features. */
2da12c60 472 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 473 const char *name; /* Name */
0b2e31dc
NS		 474 int alias; /* Alias for a cannonical name. If 1, then
475 succeeds canonical name, if -1 then
476 succeeds canonical name, if <-1 ||>1 this is a
477 deprecated name, and the next/previous name
478 should be used. */
266abb8f 479};
252b5132 480
266abb8f
NS		 481/* We hold flags for features explicitly enabled and explicitly
482 disabled. */
252b5132 483static int current_architecture;
266abb8f 484static int not_current_architecture;
266abb8f
NS		 485static const struct m68k_cpu *selected_arch;
486static const struct m68k_cpu *selected_cpu;
487static int initialized;
252b5132 488
266abb8f
NS		 489/* Architecture models. */
490static const struct m68k_cpu m68k_archs[] =
491{
2da12c60
NS		 492 {m68000, m68000_ctrl, "68000", 0},
493 {m68010, m68010_ctrl, "68010", 0},
494 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
495 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
496 {m68040, m68040_ctrl, "68040", 0},
497 {m68060, m68060_ctrl, "68060", 0},
498 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
3bdcfdf4 499 {fido_a, fido_ctrl, "fidoa", 0},
2da12c60
NS		 500 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
501 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
502 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
9a2e615a 503 {mcfisa_a|mcfhwdiv|mcfisa_c|mcfusp, NULL, "isac", 0},
2da12c60
NS		 504 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
505 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 506 {0,0,NULL, 0}
507};
252b5132 508
0b2e31dc
NS		 509/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
510 for either. */
266abb8f
NS		 511static const struct m68k_cpu m68k_extensions[] =
512{
2da12c60
NS		 513 {m68851, NULL, "68851", -1},
514 {m68881, NULL, "68881", -1},
515 {m68881, NULL, "68882", -1},
0b2e31dc 516
2da12c60 517 {cfloat|m68881, NULL, "float", 0},
266abb8f 518
2da12c60
NS		 519 {mcfhwdiv, NULL, "div", 1},
520 {mcfusp, NULL, "usp", 1},
521 {mcfmac, NULL, "mac", 1},
522 {mcfemac, NULL, "emac", 1},
266abb8f 523
2da12c60 524 {0,NULL,NULL, 0}
266abb8f
NS		 525};
526
527/* Processor list */
528static const struct m68k_cpu m68k_cpus[] =
529{
2da12c60
NS		 530 {m68000, m68000_ctrl, "68000", 0},
531 {m68000, m68000_ctrl, "68ec000", 1},
532 {m68000, m68000_ctrl, "68hc000", 1},
533 {m68000, m68000_ctrl, "68hc001", 1},
534 {m68000, m68000_ctrl, "68008", 1},
535 {m68000, m68000_ctrl, "68302", 1},
536 {m68000, m68000_ctrl, "68306", 1},
537 {m68000, m68000_ctrl, "68307", 1},
538 {m68000, m68000_ctrl, "68322", 1},
539 {m68000, m68000_ctrl, "68356", 1},
540 {m68010, m68010_ctrl, "68010", 0},
541 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
542 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
543 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
544 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
545 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
546 {m68040, m68040_ctrl, "68040", 0},
547 {m68040, m68040_ctrl, "68ec040", 1},
548 {m68060, m68060_ctrl, "68060", 0},
549 {m68060, m68060_ctrl, "68ec060", 1},
550
551 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
552 {cpu32|m68881, cpu32_ctrl, "68330", 1},
553 {cpu32|m68881, cpu32_ctrl, "68331", 1},
554 {cpu32|m68881, cpu32_ctrl, "68332", 1},
555 {cpu32|m68881, cpu32_ctrl, "68333", 1},
556 {cpu32|m68881, cpu32_ctrl, "68334", 1},
557 {cpu32|m68881, cpu32_ctrl, "68336", 1},
558 {cpu32|m68881, cpu32_ctrl, "68340", 1},
559 {cpu32|m68881, cpu32_ctrl, "68341", 1},
560 {cpu32|m68881, cpu32_ctrl, "68349", 1},
561 {cpu32|m68881, cpu32_ctrl, "68360", 1},
562
563 {mcfisa_a, mcf_ctrl, "5200", 0},
564 {mcfisa_a, mcf_ctrl, "5202", 1},
565 {mcfisa_a, mcf_ctrl, "5204", 1},
78336706 566 {mcfisa_a, mcf5206_ctrl, "5206", 1},
2da12c60 567
78336706 568 {mcfisa_a|mcfhwdiv|mcfmac, mcf5206_ctrl, "5206e", 0},
2da12c60
NS		 569
570 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
571 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
572
96e0bbcc
NS		 573 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5210a", 0},
574 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5210a_ctrl, "5211a", 1},
575
2da12c60
NS		 576 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
577 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
578 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
579
580 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
581 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
582 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
583
d5be9593
NS		 584 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52221", -1},
585 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf52223_ctrl, "52223", 0},
586
96e0bbcc
NS		 587 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52230", -1},
588 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52233", -1},
589 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52234", -1},
590 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf52235_ctrl, "52235", 0},
591
592 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5224", -1},
593 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5225_ctrl, "5225", 0},
594
2da12c60
NS		 595 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
596 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
597 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
598 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
599 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
600
601 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
602 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
d5be9593 603 {mcfisa_a|mcfhwdiv|mcfemac, mcf5253_ctrl, "5253", 0},
2da12c60
NS		 604
605 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
606 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
607
608 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
609
610 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
611 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
612
613 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
614 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
615 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
616 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
617
78336706 618 {mcfisa_a|mcfhwdiv|mcfmac, mcf5307_ctrl, "5307", 0},
2da12c60
NS		 619
620 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
621 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
622 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
623 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
624
625 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
626 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
627 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
628
629 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
9a2e615a
NS		 630
631 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54450", -1},
632 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54451", -1},
633 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54452", -1},
634 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54453", -1},
635 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54454", -1},
636 {mcfisa_a|mcfisa_c|mcfhwdiv|mcfemac|mcfusp, mcf54455_ctrl, "54455", 0},
2da12c60 637
a8e24a56
NS		 638 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5470", -1},
639 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5471", -1},
640 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5472", -1},
641 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5473", -1},
642 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5474", -1},
643 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "5475", -1},
644 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5475_ctrl, "547x", 0},
2da12c60 645
a8e24a56
NS		 646 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5480", -1},
647 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5481", -1},
648 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5482", -1},
649 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5483", -1},
650 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5484", -1},
651 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "5485", -1},
652 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcf5485_ctrl, "548x", 0},
2da12c60 653
b3768379 654 {fido_a, fido_ctrl, "fidoa", 0},
3bdcfdf4 655 {fido_a, fido_ctrl, "fido", 1},
9840d27e 656
2da12c60 657 {0,NULL,NULL, 0}
dc84e067 658 };
252b5132 659
266abb8f
NS		 660static const struct m68k_cpu *m68k_lookup_cpu
661(const char *, const struct m68k_cpu *, int, int *);
662static int m68k_set_arch (const char *, int, int);
663static int m68k_set_cpu (const char *, int, int);
664static int m68k_set_extension (const char *, int, int);
665static void m68k_init_arch (void);
252b5132 666
151337e8
NC		 667/* This is the assembler relaxation table for m68k. m68k is a rich CISC
668 architecture and we have a lot of relaxation modes. */
252b5132 669
151337e8
NC		 670/* Macros used in the relaxation code. */
671#define TAB(x,y) (((x) << 2) + (y))
672#define TABTYPE(x) ((x) >> 2)
673
674/* Relaxation states. */
675#define BYTE 0
676#define SHORT 1
677#define LONG 2
678#define SZ_UNDEF 3
679
680/* Here are all the relaxation modes we support. First we can relax ordinary
681 branches. On 68020 and higher and on CPU32 all branch instructions take
682 three forms, so on these CPUs all branches always remain as such. When we
683 have to expand to the LONG form on a 68000, though, we substitute an
684 absolute jump instead. This is a direct replacement for unconditional
685 branches and a branch over a jump for conditional branches. However, if the
686 user requires PIC and disables this with --pcrel, we can only relax between
687 BYTE and SHORT forms, punting if that isn't enough. This gives us four
688 different relaxation modes for branches: */
689
36759679
NC		 690#define BRANCHBWL 0 /* Branch byte, word, or long. */
691#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
692#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
693#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 694
695/* We also relax coprocessor branches and DBcc's. All CPUs that support
696 coprocessor branches support them in word and long forms, so we have only
697 one relaxation mode for them. DBcc's are word only on all CPUs. We can
698 relax them to the LONG form with a branch-around sequence. This sequence
699 can use a long branch (if available) or an absolute jump (if acceptable).
700 This gives us two relaxation modes. If long branches are not available and
701 absolute jumps are not acceptable, we don't relax DBcc's. */
702
36759679
NC		 703#define FBRANCH 4 /* Coprocessor branch. */
704#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
705#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 706
707/* That's all for instruction relaxation. However, we also relax PC-relative
708 operands. Specifically, we have three operand relaxation modes. On the
709 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
710 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
711 two. Also PC+displacement+index operands in their simple form (with a non-
712 suppressed index without memory indirection) are supported on all CPUs, but
713 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
714 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
715 form of the PC+displacement+index operand. Finally, some absolute operands
716 can be relaxed down to 16-bit PC-relative. */
717
36759679
NC		 718#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
719#define PCINDEX 8 /* PC + displacement + index. */
720#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 721
722/* Note that calls to frag_var need to specify the maximum expansion
723 needed; this is currently 10 bytes for DBCC. */
724
725/* The fields are:
726 How far Forward this mode will reach:
727 How far Backward this mode will reach:
728 How many bytes this mode will add to the size of the frag
729 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 730
731 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 732relax_typeS md_relax_table[] =
733{
ac62c346
AM		 734 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
735 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
736 { 0, 0, 4, 0 },
737 { 1, 1, 0, 0 },
738
739 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
740 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
741 { 0, 0, 4, 0 },
742 { 1, 1, 0, 0 },
743
744 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
745 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
746 { 0, 0, 6, 0 },
747 { 1, 1, 0, 0 },
748
749 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
750 { 0, 0, 2, 0 },
751 { 1, 1, 0, 0 },
752 { 1, 1, 0, 0 },
753
36759679 754 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 755 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
756 { 0, 0, 4, 0 },
757 { 1, 1, 0, 0 },
758
36759679 759 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 760 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
761 { 0, 0, 10, 0 },
762 { 1, 1, 0, 0 },
763
36759679 764 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 765 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
766 { 0, 0, 10, 0 },
767 { 1, 1, 0, 0 },
768
36759679 769 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 770 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
771 { 0, 0, 6, 0 },
772 { 1, 1, 0, 0 },
773
774 { 125, -130, 0, TAB (PCINDEX, SHORT) },
775 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
776 { 0, 0, 4, 0 },
777 { 1, 1, 0, 0 },
778
36759679 779 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 780 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
781 { 0, 0, 4, 0 },
782 { 1, 1, 0, 0 },
252b5132
RH		 783};
784
785/* These are the machine dependent pseudo-ops. These are included so
786 the assembler can work on the output from the SUN C compiler, which
36759679 787 generates these. */
252b5132
RH		 788
789/* This table describes all the machine specific pseudo-ops the assembler
790 has to support. The fields are:
791 pseudo-op name without dot
792 function to call to execute this pseudo-op
36759679 793 Integer arg to pass to the function. */
252b5132
RH		 794const pseudo_typeS md_pseudo_table[] =
795{
796 {"data1", s_data1, 0},
797 {"data2", s_data2, 0},
798 {"bss", s_bss, 0},
799 {"even", s_even, 0},
800 {"skip", s_space, 0},
801 {"proc", s_proc, 0},
802#if defined (TE_SUN3) || defined (OBJ_ELF)
803 {"align", s_align_bytes, 0},
804#endif
805#ifdef OBJ_ELF
806 {"swbeg", s_ignore, 0},
807#endif
808 {"extend", float_cons, 'x'},
809 {"ldouble", float_cons, 'x'},
810
266abb8f
NS		 811 {"arch", s_m68k_arch, 0},
812 {"cpu", s_m68k_cpu, 0},
813
252b5132
RH		 814 /* The following pseudo-ops are supported for MRI compatibility. */
815 {"chip", s_chip, 0},
816 {"comline", s_space, 1},
817 {"fopt", s_fopt, 0},
818 {"mask2", s_ignore, 0},
819 {"opt", s_opt, 0},
820 {"reg", s_reg, 0},
821 {"restore", s_restore, 0},
822 {"save", s_save, 0},
823
824 {"if", s_mri_if, 0},
825 {"if.b", s_mri_if, 'b'},
826 {"if.w", s_mri_if, 'w'},
827 {"if.l", s_mri_if, 'l'},
828 {"else", s_mri_else, 0},
829 {"else.s", s_mri_else, 's'},
830 {"else.l", s_mri_else, 'l'},
831 {"endi", s_mri_endi, 0},
832 {"break", s_mri_break, 0},
833 {"break.s", s_mri_break, 's'},
834 {"break.l", s_mri_break, 'l'},
835 {"next", s_mri_next, 0},
836 {"next.s", s_mri_next, 's'},
837 {"next.l", s_mri_next, 'l'},
838 {"for", s_mri_for, 0},
839 {"for.b", s_mri_for, 'b'},
840 {"for.w", s_mri_for, 'w'},
841 {"for.l", s_mri_for, 'l'},
842 {"endf", s_mri_endf, 0},
843 {"repeat", s_mri_repeat, 0},
844 {"until", s_mri_until, 0},
845 {"until.b", s_mri_until, 'b'},
846 {"until.w", s_mri_until, 'w'},
847 {"until.l", s_mri_until, 'l'},
848 {"while", s_mri_while, 0},
849 {"while.b", s_mri_while, 'b'},
850 {"while.w", s_mri_while, 'w'},
851 {"while.l", s_mri_while, 'l'},
852 {"endw", s_mri_endw, 0},
853
854 {0, 0, 0}
855};
856
252b5132 857/* The mote pseudo ops are put into the opcode table, since they
31302357 858 don't start with a . they look like opcodes to gas. */
252b5132 859
5a38dc70 860const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 861{
862
863 {"dcl", cons, 4},
864 {"dc", cons, 2},
865 {"dcw", cons, 2},
866 {"dcb", cons, 1},
867
868 {"dsl", s_space, 4},
869 {"ds", s_space, 2},
870 {"dsw", s_space, 2},
871 {"dsb", s_space, 1},
872
873 {"xdef", s_globl, 0},
874#ifdef OBJ_ELF
875 {"align", s_align_bytes, 0},
876#else
877 {"align", s_align_ptwo, 0},
878#endif
879#ifdef M68KCOFF
880 {"sect", obj_coff_section, 0},
881 {"section", obj_coff_section, 0},
882#endif
883 {0, 0, 0}
884};
885
bd17c2c3
AM		 886/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
887 gives identical results to a 32-bit host. */
888#define TRUNC(X) ((valueT) (X) & 0xffffffff)
889#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
890
891#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
892#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
893#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
894#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
895
896#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
897#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 898#define islong(x) (1)
899
252b5132
RH		 900static char notend_table[256];
901static char alt_notend_table[256];
902#define notend(s) \
903 (! (notend_table[(unsigned char) *s] \
904 || (*s == ':' \
905 && alt_notend_table[(unsigned char) s[1]])))
906
252b5132
RH		 907#ifdef OBJ_ELF
908
c801568a
AM		 909/* Return zero if the reference to SYMBOL from within the same segment may
910 be relaxed. */
911
912/* On an ELF system, we can't relax an externally visible symbol,
913 because it may be overridden by a shared library. However, if
914 TARGET_OS is "elf", then we presume that we are assembling for an
915 embedded system, in which case we don't have to worry about shared
916 libraries, and we can relax any external sym. */
917
918#define relaxable_symbol(symbol) \
6358301e 919 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 920 || S_IS_WEAK (symbol)))
921
252b5132
RH		 922/* Compute the relocation code for a fixup of SIZE bytes, using pc
923 relative relocation if PCREL is non-zero. PIC says whether a special
924 pic relocation was requested. */
925
252b5132 926static bfd_reloc_code_real_type
31302357 927get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 928{
929 switch (pic)
930 {
931 case pic_got_pcrel:
932 switch (size)
933 {
934 case 1:
935 return BFD_RELOC_8_GOT_PCREL;
936 case 2:
937 return BFD_RELOC_16_GOT_PCREL;
938 case 4:
939 return BFD_RELOC_32_GOT_PCREL;
940 }
941 break;
942
943 case pic_got_off:
944 switch (size)
945 {
946 case 1:
947 return BFD_RELOC_8_GOTOFF;
948 case 2:
949 return BFD_RELOC_16_GOTOFF;
950 case 4:
951 return BFD_RELOC_32_GOTOFF;
952 }
953 break;
954
955 case pic_plt_pcrel:
956 switch (size)
957 {
958 case 1:
959 return BFD_RELOC_8_PLT_PCREL;
960 case 2:
961 return BFD_RELOC_16_PLT_PCREL;
962 case 4:
963 return BFD_RELOC_32_PLT_PCREL;
964 }
965 break;
966
967 case pic_plt_off:
968 switch (size)
969 {
970 case 1:
971 return BFD_RELOC_8_PLTOFF;
972 case 2:
973 return BFD_RELOC_16_PLTOFF;
974 case 4:
975 return BFD_RELOC_32_PLTOFF;
976 }
977 break;
978
979 case pic_none:
980 if (pcrel)
981 {
982 switch (size)
983 {
984 case 1:
985 return BFD_RELOC_8_PCREL;
986 case 2:
987 return BFD_RELOC_16_PCREL;
988 case 4:
989 return BFD_RELOC_32_PCREL;
990 }
991 }
992 else
993 {
994 switch (size)
995 {
996 case 1:
997 return BFD_RELOC_8;
998 case 2:
999 return BFD_RELOC_16;
1000 case 4:
1001 return BFD_RELOC_32;
1002 }
1003 }
1004 }
1005
1006 if (pcrel)
1007 {
1008 if (pic == pic_none)
1009 as_bad (_("Can not do %d byte pc-relative relocation"), size);
1010 else
1011 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
1012 }
1013 else
1014 {
1015 if (pic == pic_none)
1016 as_bad (_("Can not do %d byte relocation"), size);
1017 else
1018 as_bad (_("Can not do %d byte pic relocation"), size);
1019 }
1020
1021 return BFD_RELOC_NONE;
1022}
1023
1024/* Here we decide which fixups can be adjusted to make them relative
1025 to the beginning of the section instead of the symbol. Basically
1026 we need to make sure that the dynamic relocations are done
1027 correctly, so in some cases we force the original symbol to be
1028 used. */
1029int
31302357 1030tc_m68k_fix_adjustable (fixS *fixP)
252b5132 1031{
36759679 1032 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 1033 switch (fixP->fx_r_type)
1034 {
1035 case BFD_RELOC_8_GOT_PCREL:
1036 case BFD_RELOC_16_GOT_PCREL:
1037 case BFD_RELOC_32_GOT_PCREL:
1038 case BFD_RELOC_8_GOTOFF:
1039 case BFD_RELOC_16_GOTOFF:
1040 case BFD_RELOC_32_GOTOFF:
1041 case BFD_RELOC_8_PLT_PCREL:
1042 case BFD_RELOC_16_PLT_PCREL:
1043 case BFD_RELOC_32_PLT_PCREL:
1044 case BFD_RELOC_8_PLTOFF:
1045 case BFD_RELOC_16_PLTOFF:
1046 case BFD_RELOC_32_PLTOFF:
1047 return 0;
1048
1049 case BFD_RELOC_VTABLE_INHERIT:
1050 case BFD_RELOC_VTABLE_ENTRY:
1051 return 0;
1052
1053 default:
1054 return 1;
1055 }
1056}
1057
1058#else /* !OBJ_ELF */
1059
1060#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
1061
22184a77
NC		 1062/* PR gas/3041 Weak symbols are not relaxable
1063 because they must be treated as extern. */
1064#define relaxable_symbol(symbol) (!(S_IS_WEAK (symbol)))
c801568a 1065
252b5132
RH		 1066#endif /* OBJ_ELF */
1067
252b5132 1068arelent *
31302357 1069tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 1070{
1071 arelent *reloc;
1072 bfd_reloc_code_real_type code;
1073
8ec6253e
NC		 1074 /* If the tcbit is set, then this was a fixup of a negative value
1075 that was never resolved. We do not have a reloc to handle this,
1076 so just return. We assume that other code will have detected this
1077 situation and produced a helpful error message, so we just tell the
1078 user that the reloc cannot be produced. */
252b5132 1079 if (fixp->fx_tcbit)
8ec6253e
NC		 1080 {
1081 if (fixp->fx_addsy)
b091f402
AM		 1082 as_bad_where (fixp->fx_file, fixp->fx_line,
1083 _("Unable to produce reloc against symbol '%s'"),
1084 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 1085 return NULL;
1086 }
252b5132
RH		 1087
1088 if (fixp->fx_r_type != BFD_RELOC_NONE)
1089 {
1090 code = fixp->fx_r_type;
1091
1092 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
1093 that fixup_segment converted a non-PC relative reloc into a
1094 PC relative reloc. In such a case, we need to convert the
1095 reloc code. */
1096 if (fixp->fx_pcrel)
1097 {
1098 switch (code)
1099 {
1100 case BFD_RELOC_8:
1101 code = BFD_RELOC_8_PCREL;
1102 break;
1103 case BFD_RELOC_16:
1104 code = BFD_RELOC_16_PCREL;
1105 break;
1106 case BFD_RELOC_32:
1107 code = BFD_RELOC_32_PCREL;
1108 break;
1109 case BFD_RELOC_8_PCREL:
1110 case BFD_RELOC_16_PCREL:
1111 case BFD_RELOC_32_PCREL:
1112 case BFD_RELOC_8_GOT_PCREL:
1113 case BFD_RELOC_16_GOT_PCREL:
1114 case BFD_RELOC_32_GOT_PCREL:
1115 case BFD_RELOC_8_GOTOFF:
1116 case BFD_RELOC_16_GOTOFF:
1117 case BFD_RELOC_32_GOTOFF:
1118 case BFD_RELOC_8_PLT_PCREL:
1119 case BFD_RELOC_16_PLT_PCREL:
1120 case BFD_RELOC_32_PLT_PCREL:
1121 case BFD_RELOC_8_PLTOFF:
1122 case BFD_RELOC_16_PLTOFF:
1123 case BFD_RELOC_32_PLTOFF:
1124 break;
1125 default:
1126 as_bad_where (fixp->fx_file, fixp->fx_line,
1127 _("Cannot make %s relocation PC relative"),
1128 bfd_get_reloc_code_name (code));
1129 }
1130 }
1131 }
1132 else
1133 {
1134#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1135 switch (F (fixp->fx_size, fixp->fx_pcrel))
1136 {
1137#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1138 MAP (1, 0, BFD_RELOC_8);
1139 MAP (2, 0, BFD_RELOC_16);
1140 MAP (4, 0, BFD_RELOC_32);
1141 MAP (1, 1, BFD_RELOC_8_PCREL);
1142 MAP (2, 1, BFD_RELOC_16_PCREL);
1143 MAP (4, 1, BFD_RELOC_32_PCREL);
1144 default:
1145 abort ();
1146 }
1147 }
1148#undef F
1149#undef MAP
1150
1151 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1152 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1153 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1154 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1155#ifndef OBJ_ELF
1156 if (fixp->fx_pcrel)
1157 reloc->addend = fixp->fx_addnumber;
22184a77
NC		 1158 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
1159 && fixp->fx_addsy
1160 && S_IS_WEAK (fixp->fx_addsy)
1161 && ! bfd_is_und_section (S_GET_SEGMENT (fixp->fx_addsy)))
1162 /* PR gas/3041 Adjust addend in order to force bfd_install_relocation()
1c3f20b4
NC		 1163 to put the symbol offset into frags referencing a weak symbol. */
1164 reloc->addend = fixp->fx_addnumber
1165 - (S_GET_VALUE (fixp->fx_addsy) * 2);
252b5132
RH		 1166 else
1167 reloc->addend = 0;
1168#else
1169 if (!fixp->fx_pcrel)
1170 reloc->addend = fixp->fx_addnumber;
1171 else
1172 reloc->addend = (section->vma
8390138c
AS		 1173 /* Explicit sign extension in case char is
1174 unsigned. */
1175 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1176 + fixp->fx_addnumber
1177 + md_pcrel_from (fixp));
1178#endif
1179
1180 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1181 assert (reloc->howto != 0);
1182
1183 return reloc;
1184}
1185
252b5132
RH		 1186/* Handle of the OPCODE hash table. NULL means any use before
1187 m68k_ip_begin() will crash. */
1188static struct hash_control *op_hash;
1189\f
1190/* Assemble an m68k instruction. */
1191
1192static void
31302357 1193m68k_ip (char *instring)
252b5132
RH		 1194{
1195 register char *p;
1196 register struct m68k_op *opP;
1197 register const struct m68k_incant *opcode;
1198 register const char *s;
1199 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1200 char *pdot, *pdotmove;
1201 enum m68k_size siz1, siz2;
1202 char c;
1203 int losing;
1204 int opsfound;
03b13e59 1205 struct m68k_op operands_backup[6];
252b5132
RH		 1206 LITTLENUM_TYPE words[6];
1207 LITTLENUM_TYPE *wordp;
1208 unsigned long ok_arch = 0;
1209
1210 if (*instring == ' ')
36759679 1211 instring++; /* Skip leading whitespace. */
252b5132
RH		 1212
1213 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1214 or exactly 1 space. */
252b5132
RH		 1215 pdot = 0;
1216 for (p = instring; *p != '\0'; p++)
1217 {
1218 if (*p == ' ')
1219 break;
1220 if (*p == '.')
1221 pdot = p;
1222 }
1223
1224 if (p == instring)
1225 {
1226 the_ins.error = _("No operator");
1227 return;
1228 }
1229
1230 /* p now points to the end of the opcode name, probably whitespace.
1231 Make sure the name is null terminated by clobbering the
1232 whitespace, look it up in the hash table, then fix it back.
1233 Remove a dot, first, since the opcode tables have none. */
1234 if (pdot != NULL)
1235 {
1236 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1237 *pdotmove = pdotmove[1];
1238 p--;
1239 }
1240
1241 c = *p;
1242 *p = '\0';
1243 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1244 *p = c;
1245
1246 if (pdot != NULL)
1247 {
1248 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1249 *pdotmove = pdotmove[-1];
1250 *pdot = '.';
1251 ++p;
1252 }
1253
1254 if (opcode == NULL)
1255 {
1256 the_ins.error = _("Unknown operator");
1257 return;
1258 }
1259
36759679 1260 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1261 while (*p == ' ')
1262 ++p;
1263
1264 if (opcode->m_operands == 0)
1265 {
1266 char *old = input_line_pointer;
1267 *old = '\n';
1268 input_line_pointer = p;
36759679 1269 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1270 mote_pseudo_table[opcode->m_opnum].poc_handler
1271 (mote_pseudo_table[opcode->m_opnum].poc_val);
1272 input_line_pointer = old;
1273 *old = 0;
1274
1275 return;
1276 }
1277
1278 if (flag_mri && opcode->m_opnum == 0)
1279 {
1280 /* In MRI mode, random garbage is allowed after an instruction
1281 which accepts no operands. */
1282 the_ins.args = opcode->m_operands;
1283 the_ins.numargs = opcode->m_opnum;
1284 the_ins.numo = opcode->m_codenum;
1285 the_ins.opcode[0] = getone (opcode);
1286 the_ins.opcode[1] = gettwo (opcode);
1287 return;
1288 }
1289
1290 for (opP = &the_ins.operands[0]; *p; opP++)
1291 {
1292 p = crack_operand (p, opP);
1293
1294 if (opP->error)
1295 {
1296 the_ins.error = opP->error;
1297 return;
1298 }
1299 }
1300
1301 opsfound = opP - &the_ins.operands[0];
1302
1303 /* This ugly hack is to support the floating pt opcodes in their
1304 standard form. Essentially, we fake a first enty of type COP#1 */
1305 if (opcode->m_operands[0] == 'I')
1306 {
1307 int n;
1308
1309 for (n = opsfound; n > 0; --n)
1310 the_ins.operands[n] = the_ins.operands[n - 1];
1311
31302357 1312 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1313 the_ins.operands[0].mode = CONTROL;
1314 the_ins.operands[0].reg = m68k_float_copnum;
1315 opsfound++;
1316 }
1317
36759679 1318 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1319 for (losing = 0;;)
1320 {
1321 /* If we didn't get the right number of ops, or we have no
92774660 1322 common model with this pattern then reject this pattern. */
252b5132
RH		 1323
1324 ok_arch |= opcode->m_arch;
1325 if (opsfound != opcode->m_opnum
1326 || ((opcode->m_arch & current_architecture) == 0))
1327 ++losing;
1328 else
1329 {
03b13e59
NC		 1330 int i;
1331
1332 /* Make a copy of the operands of this insn so that
1333 we can modify them safely, should we want to. */
1334 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1335 for (i = 0; i < opsfound; i++)
1336 operands_backup[i] = the_ins.operands[i];
1337
1338 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1339 *s && !losing;
1340 s += 2, opP++)
1341 {
1342 /* Warning: this switch is huge! */
1343 /* I've tried to organize the cases into this order:
1344 non-alpha first, then alpha by letter. Lower-case
1345 goes directly before uppercase counterpart. */
1346 /* Code with multiple case ...: gets sorted by the lowest
1347 case ... it belongs to. I hope this makes sense. */
1348 switch (*s)
1349 {
1350 case '!':
1351 switch (opP->mode)
1352 {
1353 case IMMED:
1354 case DREG:
1355 case AREG:
1356 case FPREG:
1357 case CONTROL:
1358 case AINC:
1359 case ADEC:
1360 case REGLST:
1361 losing++;
1362 break;
1363 default:
1364 break;
1365 }
1366 break;
1367
1368 case '<':
1369 switch (opP->mode)
1370 {
1371 case DREG:
1372 case AREG:
1373 case FPREG:
1374 case CONTROL:
1375 case IMMED:
1376 case ADEC:
1377 case REGLST:
1378 losing++;
1379 break;
1380 default:
1381 break;
1382 }
1383 break;
1384
1385 case '>':
1386 switch (opP->mode)
1387 {
1388 case DREG:
1389 case AREG:
1390 case FPREG:
1391 case CONTROL:
1392 case IMMED:
1393 case AINC:
1394 case REGLST:
1395 losing++;
1396 break;
1397 case ABSL:
1398 break;
1399 default:
1400 if (opP->reg == PC
1401 || opP->reg == ZPC)
1402 losing++;
1403 break;
1404 }
1405 break;
1406
1407 case 'm':
1408 switch (opP->mode)
1409 {
1410 case DREG:
1411 case AREG:
1412 case AINDR:
1413 case AINC:
1414 case ADEC:
1415 break;
1416 default:
1417 losing++;
1418 }
8a104df9 1419 break;
252b5132
RH		 1420
1421 case 'n':
1422 switch (opP->mode)
1423 {
1424 case DISP:
1425 break;
1426 default:
1427 losing++;
1428 }
8a104df9 1429 break;
252b5132
RH		 1430
1431 case 'o':
1432 switch (opP->mode)
1433 {
1434 case BASE:
1435 case ABSL:
1436 case IMMED:
1437 break;
1438 default:
1439 losing++;
1440 }
8a104df9 1441 break;
252b5132
RH		 1442
1443 case 'p':
1444 switch (opP->mode)
1445 {
1446 case DREG:
1447 case AREG:
1448 case AINDR:
1449 case AINC:
1450 case ADEC:
1451 break;
1452 case DISP:
1453 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1454 losing++;
252b5132
RH		 1455 break;
1456 default:
1457 losing++;
1458 }
8a104df9 1459 break;
252b5132
RH		 1460
1461 case 'q':
1462 switch (opP->mode)
1463 {
1464 case DREG:
1465 case AINDR:
1466 case AINC:
1467 case ADEC:
1468 break;
1469 case DISP:
1470 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1471 losing++;
252b5132
RH		 1472 break;
1473 default:
1474 losing++;
1475 break;
1476 }
8a104df9 1477 break;
252b5132
RH		 1478
1479 case 'v':
1480 switch (opP->mode)
1481 {
1482 case DREG:
1483 case AINDR:
1484 case AINC:
1485 case ADEC:
1486 case ABSL:
1487 break;
1488 case DISP:
1489 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1490 losing++;
252b5132
RH		 1491 break;
1492 default:
1493 losing++;
1494 break;
1495 }
1496 break;
1497
1498 case '#':
1499 if (opP->mode != IMMED)
1500 losing++;
1501 else if (s[1] == 'b'
1502 && ! isvar (&opP->disp)
1503 && (opP->disp.exp.X_op != O_constant
1504 || ! isbyte (opP->disp.exp.X_add_number)))
1505 losing++;
1506 else if (s[1] == 'B'
1507 && ! isvar (&opP->disp)
1508 && (opP->disp.exp.X_op != O_constant
1509 || ! issbyte (opP->disp.exp.X_add_number)))
1510 losing++;
1511 else if (s[1] == 'w'
1512 && ! isvar (&opP->disp)
1513 && (opP->disp.exp.X_op != O_constant
1514 || ! isword (opP->disp.exp.X_add_number)))
1515 losing++;
1516 else if (s[1] == 'W'
1517 && ! isvar (&opP->disp)
1518 && (opP->disp.exp.X_op != O_constant
1519 || ! issword (opP->disp.exp.X_add_number)))
1520 losing++;
1521 break;
1522
1523 case '^':
1524 case 'T':
1525 if (opP->mode != IMMED)
1526 losing++;
1527 break;
1528
1529 case '$':
1530 if (opP->mode == AREG
1531 || opP->mode == CONTROL
1532 || opP->mode == FPREG
1533 || opP->mode == IMMED
1534 || opP->mode == REGLST
1535 || (opP->mode != ABSL
1536 && (opP->reg == PC
1537 || opP->reg == ZPC)))
1538 losing++;
1539 break;
1540
1541 case '%':
1542 if (opP->mode == CONTROL
1543 || opP->mode == FPREG
1544 || opP->mode == REGLST
1545 || opP->mode == IMMED
1546 || (opP->mode != ABSL
1547 && (opP->reg == PC
1548 || opP->reg == ZPC)))
1549 losing++;
1550 break;
1551
1552 case '&':
1553 switch (opP->mode)
1554 {
1555 case DREG:
1556 case AREG:
1557 case FPREG:
1558 case CONTROL:
1559 case IMMED:
1560 case AINC:
1561 case ADEC:
1562 case REGLST:
1563 losing++;
1564 break;
1565 case ABSL:
1566 break;
1567 default:
1568 if (opP->reg == PC
1569 || opP->reg == ZPC)
1570 losing++;
1571 break;
1572 }
1573 break;
1574
1575 case '*':
1576 if (opP->mode == CONTROL
1577 || opP->mode == FPREG
1578 || opP->mode == REGLST)
1579 losing++;
1580 break;
1581
1582 case '+':
1583 if (opP->mode != AINC)
1584 losing++;
1585 break;
1586
1587 case '-':
1588 if (opP->mode != ADEC)
1589 losing++;
1590 break;
1591
1592 case '/':
1593 switch (opP->mode)
1594 {
1595 case AREG:
1596 case CONTROL:
1597 case FPREG:
1598 case AINC:
1599 case ADEC:
1600 case IMMED:
1601 case REGLST:
1602 losing++;
1603 break;
1604 default:
1605 break;
1606 }
1607 break;
1608
1609 case ';':
1610 switch (opP->mode)
1611 {
1612 case AREG:
1613 case CONTROL:
1614 case FPREG:
1615 case REGLST:
1616 losing++;
1617 break;
1618 default:
1619 break;
1620 }
1621 break;
1622
1623 case '?':
1624 switch (opP->mode)
1625 {
1626 case AREG:
1627 case CONTROL:
1628 case FPREG:
1629 case AINC:
1630 case ADEC:
1631 case IMMED:
1632 case REGLST:
1633 losing++;
1634 break;
1635 case ABSL:
1636 break;
1637 default:
1638 if (opP->reg == PC || opP->reg == ZPC)
1639 losing++;
1640 break;
1641 }
1642 break;
1643
1644 case '@':
1645 switch (opP->mode)
1646 {
1647 case AREG:
1648 case CONTROL:
1649 case FPREG:
1650 case IMMED:
1651 case REGLST:
1652 losing++;
1653 break;
1654 default:
1655 break;
1656 }
1657 break;
1658
1659 case '~': /* For now! (JF FOO is this right?) */
1660 switch (opP->mode)
1661 {
1662 case DREG:
1663 case AREG:
1664 case CONTROL:
1665 case FPREG:
1666 case IMMED:
1667 case REGLST:
1668 losing++;
1669 break;
1670 case ABSL:
1671 break;
1672 default:
1673 if (opP->reg == PC
1674 || opP->reg == ZPC)
1675 losing++;
1676 break;
1677 }
1678 break;
1679
1680 case '3':
1681 if (opP->mode != CONTROL
1682 || (opP->reg != TT0 && opP->reg != TT1))
1683 losing++;
1684 break;
1685
1686 case 'A':
1687 if (opP->mode != AREG)
1688 losing++;
1689 break;
1690
1691 case 'a':
1692 if (opP->mode != AINDR)
1693 ++losing;
1694 break;
1695
fd99574b
NC		 1696 case '4':
1697 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1698 && (opP->mode != DISP
1699 || opP->reg < ADDR0
1700 || opP->reg > ADDR7))
1701 ++losing;
1702 break;
1703
252b5132
RH		 1704 case 'B': /* FOO */
1705 if (opP->mode != ABSL
1706 || (flag_long_jumps
1707 && strncmp (instring, "jbsr", 4) == 0))
1708 losing++;
1709 break;
1710
3e602632
NC		 1711 case 'b':
1712 switch (opP->mode)
1713 {
1714 case IMMED:
1715 case ABSL:
1716 case AREG:
1717 case FPREG:
1718 case CONTROL:
1719 case POST:
1720 case PRE:
1721 case REGLST:
1722 losing++;
1723 break;
1724 default:
1725 break;
1726 }
1727 break;
1728
252b5132
RH		 1729 case 'C':
1730 if (opP->mode != CONTROL || opP->reg != CCR)
1731 losing++;
1732 break;
1733
1734 case 'd':
1735 if (opP->mode != DISP
1736 || opP->reg < ADDR0
1737 || opP->reg > ADDR7)
1738 losing++;
1739 break;
1740
1741 case 'D':
1742 if (opP->mode != DREG)
1743 losing++;
1744 break;
1745
6da466c7
ILT		 1746 case 'E':
1747 if (opP->reg != ACC)
1748 losing++;
1749 break;
1750
fd99574b
NC		 1751 case 'e':
1752 if (opP->reg != ACC && opP->reg != ACC1
1753 && opP->reg != ACC2 && opP->reg != ACC3)
1754 losing++;
1755 break;
1756
252b5132
RH		 1757 case 'F':
1758 if (opP->mode != FPREG)
1759 losing++;
1760 break;
1761
6da466c7
ILT		 1762 case 'G':
1763 if (opP->reg != MACSR)
1764 losing++;
1765 break;
1766
fd99574b
NC		 1767 case 'g':
1768 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1769 losing++;
1770 break;
1771
6da466c7
ILT		 1772 case 'H':
1773 if (opP->reg != MASK)
1774 losing++;
1775 break;
1776
252b5132
RH		 1777 case 'I':
1778 if (opP->mode != CONTROL
1779 || opP->reg < COP0
1780 || opP->reg > COP7)
1781 losing++;
1782 break;
1783
fd99574b
NC		 1784 case 'i':
1785 if (opP->mode != LSH && opP->mode != RSH)
1786 losing++;
1787 break;
1788
252b5132
RH		 1789 case 'J':
1790 if (opP->mode != CONTROL
1791 || opP->reg < USP
0b2e31dc
NS		 1792 || opP->reg > last_movec_reg
1793 || !control_regs)
252b5132
RH		 1794 losing++;
1795 else
1796 {
1797 const enum m68k_register *rp;
0b2e31dc 1798
252b5132 1799 for (rp = control_regs; *rp; rp++)
78336706
NS		 1800 {
1801 if (*rp == opP->reg)
1802 break;
1803 /* In most CPUs RAMBAR refers to control reg
1804 c05 (RAMBAR1), but a few CPUs have it
1805 refer to c04 (RAMBAR0). */
1806 else if (*rp == RAMBAR_ALT && opP->reg == RAMBAR)
1807 {
1808 opP->reg = RAMBAR_ALT;
1809 break;
1810 }
1811 }
252b5132
RH		 1812 if (*rp == 0)
1813 losing++;
1814 }
1815 break;
1816
1817 case 'k':
1818 if (opP->mode != IMMED)
1819 losing++;
1820 break;
1821
1822 case 'l':
1823 case 'L':
1824 if (opP->mode == DREG
1825 || opP->mode == AREG
1826 || opP->mode == FPREG)
1827 {
1828 if (s[1] == '8')
1829 losing++;
1830 else
1831 {
1832 switch (opP->mode)
1833 {
1834 case DREG:
1835 opP->mask = 1 << (opP->reg - DATA0);
1836 break;
1837 case AREG:
1838 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1839 break;
1840 case FPREG:
1841 opP->mask = 1 << (opP->reg - FP0 + 16);
1842 break;
1843 default:
1844 abort ();
1845 }
1846 opP->mode = REGLST;
1847 }
1848 }
1849 else if (opP->mode == CONTROL)
1850 {
1851 if (s[1] != '8')
1852 losing++;
1853 else
1854 {
1855 switch (opP->reg)
1856 {
1857 case FPI:
1858 opP->mask = 1 << 24;
1859 break;
1860 case FPS:
1861 opP->mask = 1 << 25;
1862 break;
1863 case FPC:
1864 opP->mask = 1 << 26;
1865 break;
1866 default:
1867 losing++;
1868 break;
1869 }
1870 opP->mode = REGLST;
1871 }
1872 }
1873 else if (opP->mode != REGLST)
1874 losing++;
1875 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1876 losing++;
1877 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1878 losing++;
1879 break;
1880
1881 case 'M':
1882 if (opP->mode != IMMED)
1883 losing++;
1884 else if (opP->disp.exp.X_op != O_constant
1885 || ! issbyte (opP->disp.exp.X_add_number))
1886 losing++;
1887 else if (! m68k_quick
1888 && instring[3] != 'q'
1889 && instring[4] != 'q')
1890 losing++;
1891 break;
1892
1893 case 'O':
1894 if (opP->mode != DREG
1895 && opP->mode != IMMED
1896 && opP->mode != ABSL)
1897 losing++;
1898 break;
1899
1900 case 'Q':
1901 if (opP->mode != IMMED)
1902 losing++;
1903 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1904 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1905 losing++;
1906 else if (! m68k_quick
1907 && (strncmp (instring, "add", 3) == 0
1908 || strncmp (instring, "sub", 3) == 0)
1909 && instring[3] != 'q')
1910 losing++;
1911 break;
1912
1913 case 'R':
1914 if (opP->mode != DREG && opP->mode != AREG)
1915 losing++;
1916 break;
1917
1918 case 'r':
1919 if (opP->mode != AINDR
1920 && (opP->mode != BASE
1921 || (opP->reg != 0
1922 && opP->reg != ZADDR0)
1923 || opP->disp.exp.X_op != O_absent
1924 || ((opP->index.reg < DATA0
1925 || opP->index.reg > DATA7)
1926 && (opP->index.reg < ADDR0
1927 || opP->index.reg > ADDR7))
1928 || opP->index.size != SIZE_UNSPEC
1929 || opP->index.scale != 1))
1930 losing++;
1931 break;
1932
1933 case 's':
1934 if (opP->mode != CONTROL
1935 || ! (opP->reg == FPI
1936 || opP->reg == FPS
1937 || opP->reg == FPC))
1938 losing++;
1939 break;
1940
1941 case 'S':
1942 if (opP->mode != CONTROL || opP->reg != SR)
1943 losing++;
1944 break;
1945
1946 case 't':
1947 if (opP->mode != IMMED)
1948 losing++;
1949 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1950 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1951 losing++;
1952 break;
1953
1954 case 'U':
1955 if (opP->mode != CONTROL || opP->reg != USP)
1956 losing++;
1957 break;
1958
3e602632
NC		 1959 case 'x':
1960 if (opP->mode != IMMED)
1961 losing++;
1962 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1963 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1964 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1965 losing++;
1966 break;
1967
252b5132
RH		 1968 /* JF these are out of order. We could put them
1969 in order if we were willing to put up with
1970 bunches of #ifdef m68851s in the code.
1971
1972 Don't forget that you need these operands
1973 to use 68030 MMU instructions. */
1974#ifndef NO_68851
36759679 1975 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1976 case '|':
1977 if (opP->mode == CONTROL
1978 || opP->mode == FPREG
1979 || opP->mode == DREG
1980 || opP->mode == AREG
1981 || opP->mode == REGLST)
1982 losing++;
1983 /* We should accept immediate operands, but they
1984 supposedly have to be quad word, and we don't
1985 handle that. I would like to see what a Motorola
1986 assembler does before doing something here. */
1987 if (opP->mode == IMMED)
1988 losing++;
1989 break;
1990
1991 case 'f':
1992 if (opP->mode != CONTROL
1993 || (opP->reg != SFC && opP->reg != DFC))
1994 losing++;
1995 break;
1996
1997 case '0':
1998 if (opP->mode != CONTROL || opP->reg != TC)
1999 losing++;
2000 break;
2001
2002 case '1':
2003 if (opP->mode != CONTROL || opP->reg != AC)
2004 losing++;
2005 break;
2006
2007 case '2':
2008 if (opP->mode != CONTROL
2009 || (opP->reg != CAL
2010 && opP->reg != VAL
2011 && opP->reg != SCC))
2012 losing++;
2013 break;
2014
2015 case 'V':
2016 if (opP->mode != CONTROL
2017 || opP->reg != VAL)
2018 losing++;
2019 break;
2020
2021 case 'W':
2022 if (opP->mode != CONTROL
2023 || (opP->reg != DRP
2024 && opP->reg != SRP
2025 && opP->reg != CRP))
2026 losing++;
2027 break;
2028
3e602632
NC		 2029 case 'w':
2030 switch (opP->mode)
2031 {
2032 case IMMED:
2033 case ABSL:
2034 case AREG:
2035 case DREG:
2036 case FPREG:
2037 case CONTROL:
2038 case POST:
2039 case PRE:
2040 case REGLST:
2041 losing++;
2042 break;
2043 default:
2044 break;
2045 }
2046 break;
2047
252b5132
RH		 2048 case 'X':
2049 if (opP->mode != CONTROL
2050 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
2051 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
2052 losing++;
2053 break;
2054
2055 case 'Y':
2056 if (opP->mode != CONTROL || opP->reg != PSR)
2057 losing++;
2058 break;
2059
2060 case 'Z':
2061 if (opP->mode != CONTROL || opP->reg != PCSR)
2062 losing++;
2063 break;
2064#endif
2065 case 'c':
2066 if (opP->mode != CONTROL
2067 || (opP->reg != NC
2068 && opP->reg != IC
2069 && opP->reg != DC
2070 && opP->reg != BC))
36759679 2071 losing++;
252b5132
RH		 2072 break;
2073
2074 case '_':
2075 if (opP->mode != ABSL)
2076 ++losing;
2077 break;
2078
6da466c7
ILT		 2079 case 'u':
2080 if (opP->reg < DATA0L || opP->reg > ADDR7U)
2081 losing++;
2082 /* FIXME: kludge instead of fixing parser:
2083 upper/lower registers are *not* CONTROL
92774660 2084 registers, but ordinary ones. */
6da466c7
ILT		 2085 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
2086 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
2087 opP->mode = DREG;
2088 else
2089 opP->mode = AREG;
2090 break;
2091
3e602632
NC		 2092 case 'y':
2093 if (!(opP->mode == AINDR
31302357
AS		 2094 || (opP->mode == DISP
2095 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 2096 losing++;
2097 break;
2098
2099 case 'z':
2100 if (!(opP->mode == AINDR || opP->mode == DISP))
2101 losing++;
2102 break;
2103
252b5132
RH		 2104 default:
2105 abort ();
36759679 2106 }
252b5132
RH		 2107
2108 if (losing)
2109 break;
36759679 2110 }
03b13e59
NC		 2111
2112 /* Since we have found the correct instruction, copy
2113 in the modifications that we may have made. */
2114 if (!losing)
2115 for (i = 0; i < opsfound; i++)
2116 the_ins.operands[i] = operands_backup[i];
36759679 2117 }
252b5132
RH		 2118
2119 if (!losing)
36759679 2120 break;
252b5132
RH		 2121
2122 opcode = opcode->m_next;
2123
2124 if (!opcode)
2125 {
2126 if (ok_arch
2127 && !(ok_arch & current_architecture))
2128 {
6d89cc8f
NS		 2129 const struct m68k_cpu *cpu;
2130 int any = 0;
2131 size_t space = 400;
2132 char *buf = xmalloc (space + 1);
2133 size_t len;
2134 int paren = 1;
2135
2136 the_ins.error = buf;
2137 /* Make sure there's a NUL at the end of the buffer -- strncpy
2138 won't write one when it runs out of buffer */
2139 buf[space] = 0;
2140#define APPEND(STRING) \
2141 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2142
2143 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2144 switch (ok_arch)
2145 {
6b6e92f4 2146 case mcfisa_a:
6d89cc8f 2147 APPEND (_("ColdFire ISA_A"));
6b6e92f4
NC		 2148 break;
2149 case mcfhwdiv:
6d89cc8f 2150 APPEND (_("ColdFire hardware divide"));
6b6e92f4
NC		 2151 break;
2152 case mcfisa_aa:
6d89cc8f 2153 APPEND (_("ColdFire ISA_A+"));
6b6e92f4
NC		 2154 break;
2155 case mcfisa_b:
6d89cc8f 2156 APPEND (_("ColdFire ISA_B"));
6b6e92f4 2157 break;
3e602632 2158 case cfloat:
6d89cc8f 2159 APPEND (_("ColdFire fpu"));
3e602632 2160 break;
252b5132 2161 case mfloat:
6d89cc8f 2162 APPEND (_("M68K fpu"));
252b5132
RH		 2163 break;
2164 case mmmu:
6d89cc8f 2165 APPEND (_("M68K mmu"));
252b5132
RH		 2166 break;
2167 case m68020up:
6d89cc8f 2168 APPEND (_("68020 or higher"));
252b5132
RH		 2169 break;
2170 case m68000up:
6d89cc8f 2171 APPEND (_("68000 or higher"));
252b5132
RH		 2172 break;
2173 case m68010up:
6d89cc8f 2174 APPEND (_("68010 or higher"));
252b5132
RH		 2175 break;
2176 default:
6d89cc8f
NS		 2177 paren = 0;
2178 }
2179 if (paren)
2180 APPEND (" (");
6b6e92f4 2181
6d89cc8f
NS		 2182 for (cpu = m68k_cpus; cpu->name; cpu++)
2183 if (!cpu->alias && (cpu->arch & ok_arch))
2184 {
2185 const struct m68k_cpu *alias;
869ddf2a
NS		 2186 int seen_master = 0;
2187
6d89cc8f
NS		 2188 if (any)
2189 APPEND (", ");
2190 any = 0;
2191 APPEND (cpu->name);
869ddf2a
NS		 2192 for (alias = cpu; alias != m68k_cpus; alias--)
2193 if (alias[-1].alias >= 0)
2194 break;
2195 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2196 {
869ddf2a
NS		 2197 if (!alias->alias)
2198 seen_master = 1;
2199 else
2200 {
2201 if (any)
2202 APPEND (", ");
2203 else
2204 APPEND (" [");
2205 APPEND (alias->name);
2206 any = 1;
2207 }
6d89cc8f 2208 }
869ddf2a
NS		 2209 if (any)
2210 APPEND ("]");
6d89cc8f 2211 any = 1;
252b5132 2212 }
6d89cc8f
NS		 2213 if (paren)
2214 APPEND (")");
2215#undef APPEND
2216 if (!space)
2217 {
2218 /* we ran out of space, so replace the end of the list
2219 with ellipsis. */
2220 buf -= 4;
2221 while (*buf != ' ')
2222 buf--;
2223 strcpy (buf, " ...");
252b5132 2224 }
252b5132
RH		 2225 }
2226 else
2227 the_ins.error = _("operands mismatch");
2228 return;
36759679 2229 }
252b5132
RH		 2230
2231 losing = 0;
2232 }
2233
36759679 2234 /* Now assemble it. */
252b5132
RH		 2235 the_ins.args = opcode->m_operands;
2236 the_ins.numargs = opcode->m_opnum;
2237 the_ins.numo = opcode->m_codenum;
2238 the_ins.opcode[0] = getone (opcode);
2239 the_ins.opcode[1] = gettwo (opcode);
2240
2241 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2242 {
9a2e615a
NS		 2243 int have_disp = 0;
2244
252b5132 2245 /* This switch is a doozy.
31302357 2246 Watch the first step; its a big one! */
252b5132
RH		 2247 switch (s[0])
2248 {
2249
2250 case '*':
2251 case '~':
2252 case '%':
2253 case ';':
2254 case '@':
2255 case '!':
2256 case '&':
2257 case '$':
2258 case '?':
2259 case '/':
2260 case '<':
2261 case '>':
3e602632 2262 case 'b':
252b5132
RH		 2263 case 'm':
2264 case 'n':
2265 case 'o':
2266 case 'p':
2267 case 'q':
2268 case 'v':
3e602632
NC		 2269 case 'w':
2270 case 'y':
2271 case 'z':
fd99574b 2272 case '4':
252b5132
RH		 2273#ifndef NO_68851
2274 case '|':
2275#endif
2276 switch (opP->mode)
2277 {
2278 case IMMED:
2279 tmpreg = 0x3c; /* 7.4 */
2280 if (strchr ("bwl", s[1]))
3e602632 2281 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2282 else
2283 nextword = get_num (&opP->disp, 0);
2284 if (isvar (&opP->disp))
2285 add_fix (s[1], &opP->disp, 0, 0);
2286 switch (s[1])
2287 {
2288 case 'b':
2289 if (!isbyte (nextword))
2290 opP->error = _("operand out of range");
2291 addword (nextword);
2292 baseo = 0;
2293 break;
2294 case 'w':
2295 if (!isword (nextword))
2296 opP->error = _("operand out of range");
2297 addword (nextword);
2298 baseo = 0;
2299 break;
2300 case 'W':
2301 if (!issword (nextword))
2302 opP->error = _("operand out of range");
2303 addword (nextword);
2304 baseo = 0;
2305 break;
2306 case 'l':
2307 addword (nextword >> 16);
2308 addword (nextword);
2309 baseo = 0;
2310 break;
2311
2312 case 'f':
2313 baseo = 2;
2314 outro = 8;
2315 break;
2316 case 'F':
2317 baseo = 4;
2318 outro = 11;
2319 break;
2320 case 'x':
2321 baseo = 6;
2322 outro = 15;
2323 break;
2324 case 'p':
2325 baseo = 6;
2326 outro = -1;
2327 break;
2328 default:
2329 abort ();
2330 }
2331 if (!baseo)
2332 break;
2333
36759679 2334 /* We gotta put out some float. */
252b5132
RH		 2335 if (op (&opP->disp) != O_big)
2336 {
2337 valueT val;
2338 int gencnt;
2339
2340 /* Can other cases happen here? */
2341 if (op (&opP->disp) != O_constant)
2342 abort ();
2343
2344 val = (valueT) offs (&opP->disp);
2345 gencnt = 0;
2346 do
2347 {
2348 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2349 val >>= LITTLENUM_NUMBER_OF_BITS;
2350 ++gencnt;
2351 }
2352 while (val != 0);
2353 offs (&opP->disp) = gencnt;
2354 }
2355 if (offs (&opP->disp) > 0)
2356 {
2357 if (offs (&opP->disp) > baseo)
2358 {
2359 as_warn (_("Bignum too big for %c format; truncated"),
2360 s[1]);
2361 offs (&opP->disp) = baseo;
2362 }
2363 baseo -= offs (&opP->disp);
2364 while (baseo--)
2365 addword (0);
2366 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2367 offs (&opP->disp)--;
2368 --wordp)
2369 addword (*wordp);
2370 break;
2371 }
2372 gen_to_words (words, baseo, (long) outro);
2373 for (wordp = words; baseo--; wordp++)
2374 addword (*wordp);
2375 break;
2376 case DREG:
2377 tmpreg = opP->reg - DATA; /* 0.dreg */
2378 break;
2379 case AREG:
2380 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2381 break;
2382 case AINDR:
2383 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2384 break;
2385 case ADEC:
2386 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2387 break;
2388 case AINC:
2389 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2390 break;
2391 case DISP:
2392
3e602632 2393 nextword = get_num (&opP->disp, 90);
252b5132 2394
580b9172
NC		 2395 /* Convert mode 5 addressing with a zero offset into
2396 mode 2 addressing to reduce the instruction size by a
2397 word. */
2398 if (! isvar (&opP->disp)
2399 && (nextword == 0)
2400 && (opP->disp.size == SIZE_UNSPEC)
2401 && (opP->reg >= ADDR0)
2402 && (opP->reg <= ADDR7))
2403 {
2404 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2405 break;
2406 }
2407
252b5132
RH		 2408 if (opP->reg == PC
2409 && ! isvar (&opP->disp)
2410 && m68k_abspcadd)
2411 {
2412 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2413 opP->disp.exp.X_add_symbol =
2414 section_symbol (absolute_section);
252b5132
RH		 2415 }
2416
36759679 2417 /* Force into index mode. Hope this works. */
252b5132
RH		 2418
2419 /* We do the first bit for 32-bit displacements, and the
2420 second bit for 16 bit ones. It is possible that we
2421 should make the default be WORD instead of LONG, but
2422 I think that'd break GCC, so we put up with a little
2423 inefficiency for the sake of working output. */
2424
2425 if (!issword (nextword)
2426 || (isvar (&opP->disp)
2427 && ((opP->disp.size == SIZE_UNSPEC
2428 && flag_short_refs == 0
2429 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2430 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2431 || opP->disp.size == SIZE_LONG)))
2432 {
2433 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2434 || arch_coldfire_p (current_architecture))
252b5132
RH		 2435 opP->error =
2436 _("displacement too large for this architecture; needs 68020 or higher");
2437 if (opP->reg == PC)
2438 tmpreg = 0x3B; /* 7.3 */
2439 else
2440 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2441 if (isvar (&opP->disp))
2442 {
2443 if (opP->reg == PC)
2444 {
2445 if (opP->disp.size == SIZE_LONG
2446#ifdef OBJ_ELF
2447 /* If the displacement needs pic
2448 relocation it cannot be relaxed. */
2449 || opP->disp.pic_reloc != pic_none
2450#endif
2451 )
2452 {
2453 addword (0x0170);
2454 add_fix ('l', &opP->disp, 1, 2);
2455 }
2456 else
2457 {
2458 add_frag (adds (&opP->disp),
bd17c2c3 2459 SEXT (offs (&opP->disp)),
151337e8 2460 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2461 break;
2462 }
2463 }
2464 else
2465 {
2466 addword (0x0170);
2467 add_fix ('l', &opP->disp, 0, 0);
2468 }
2469 }
2470 else
2471 addword (0x0170);
2472 addword (nextword >> 16);
2473 }
2474 else
2475 {
2476 if (opP->reg == PC)
2477 tmpreg = 0x3A; /* 7.2 */
2478 else
2479 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2480
2481 if (isvar (&opP->disp))
2482 {
2483 if (opP->reg == PC)
2484 {
2485 add_fix ('w', &opP->disp, 1, 0);
2486 }
2487 else
2488 add_fix ('w', &opP->disp, 0, 0);
2489 }
2490 }
2491 addword (nextword);
2492 break;
2493
2494 case POST:
2495 case PRE:
2496 case BASE:
2497 nextword = 0;
3e602632 2498 baseo = get_num (&opP->disp, 90);
252b5132 2499 if (opP->mode == POST || opP->mode == PRE)
3e602632 2500 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2501 /* Figure out the `addressing mode'.
2502 Also turn on the BASE_DISABLE bit, if needed. */
2503 if (opP->reg == PC || opP->reg == ZPC)
2504 {
2505 tmpreg = 0x3b; /* 7.3 */
2506 if (opP->reg == ZPC)
2507 nextword |= 0x80;
2508 }
2509 else if (opP->reg == 0)
2510 {
2511 nextword |= 0x80;
2512 tmpreg = 0x30; /* 6.garbage */
2513 }
2514 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2515 {
2516 nextword |= 0x80;
2517 tmpreg = 0x30 + opP->reg - ZADDR0;
2518 }
2519 else
2520 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2521
2522 siz1 = opP->disp.size;
2523 if (opP->mode == POST || opP->mode == PRE)
2524 siz2 = opP->odisp.size;
2525 else
2526 siz2 = SIZE_UNSPEC;
2527
36759679 2528 /* Index register stuff. */
252b5132
RH		 2529 if (opP->index.reg != 0
2530 && opP->index.reg >= DATA
2531 && opP->index.reg <= ADDR7)
2532 {
2533 nextword |= (opP->index.reg - DATA) << 12;
2534
2535 if (opP->index.size == SIZE_LONG
2536 || (opP->index.size == SIZE_UNSPEC
2537 && m68k_index_width_default == SIZE_LONG))
2538 nextword |= 0x800;
2539
92774660 2540 if ((opP->index.scale != 1
252b5132 2541 && cpu_of_arch (current_architecture) < m68020)
92774660 2542 || (opP->index.scale == 8
3e602632 2543 && (arch_coldfire_p (current_architecture)
6b6e92f4 2544 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2545 {
2546 opP->error =
2547 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2548 }
2549
6da466c7
ILT		 2550 if (arch_coldfire_p (current_architecture)
2551 && opP->index.size == SIZE_WORD)
2552 opP->error = _("invalid index size for coldfire");
2553
252b5132
RH		 2554 switch (opP->index.scale)
2555 {
2556 case 1:
2557 break;
2558 case 2:
2559 nextword |= 0x200;
2560 break;
2561 case 4:
2562 nextword |= 0x400;
2563 break;
2564 case 8:
2565 nextword |= 0x600;
2566 break;
2567 default:
2568 abort ();
2569 }
2570 /* IF its simple,
2571 GET US OUT OF HERE! */
2572
2573 /* Must be INDEX, with an index register. Address
2574 register cannot be ZERO-PC, and either :b was
2575 forced, or we know it will fit. For a 68000 or
2576 68010, force this mode anyways, because the
2577 larger modes aren't supported. */
2578 if (opP->mode == BASE
2579 && ((opP->reg >= ADDR0
2580 && opP->reg <= ADDR7)
2581 || opP->reg == PC))
2582 {
2583 if (siz1 == SIZE_BYTE
2584 || cpu_of_arch (current_architecture) < m68020
6da466c7 2585 || arch_coldfire_p (current_architecture)
252b5132
RH		 2586 || (siz1 == SIZE_UNSPEC
2587 && ! isvar (&opP->disp)
2588 && issbyte (baseo)))
2589 {
2590 nextword += baseo & 0xff;
2591 addword (nextword);
2592 if (isvar (&opP->disp))
2593 {
2594 /* Do a byte relocation. If it doesn't
2595 fit (possible on m68000) let the
2596 fixup processing complain later. */
2597 if (opP->reg == PC)
2598 add_fix ('B', &opP->disp, 1, 1);
2599 else
2600 add_fix ('B', &opP->disp, 0, 0);
2601 }
2602 else if (siz1 != SIZE_BYTE)
2603 {
2604 if (siz1 != SIZE_UNSPEC)
2605 as_warn (_("Forcing byte displacement"));
2606 if (! issbyte (baseo))
2607 opP->error = _("byte displacement out of range");
2608 }
2609
2610 break;
2611 }
2612 else if (siz1 == SIZE_UNSPEC
2613 && opP->reg == PC
2614 && isvar (&opP->disp)
2615 && subs (&opP->disp) == NULL
2616#ifdef OBJ_ELF
2617 /* If the displacement needs pic
2618 relocation it cannot be relaxed. */
2619 && opP->disp.pic_reloc == pic_none
2620#endif
2621 )
2622 {
2623 /* The code in md_convert_frag_1 needs to be
2624 able to adjust nextword. Call frag_grow
2625 to ensure that we have enough space in
2626 the frag obstack to make all the bytes
2627 contiguous. */
2628 frag_grow (14);
8a104df9
KH		 2629 nextword += baseo & 0xff;
2630 addword (nextword);
bd17c2c3
AM		 2631 add_frag (adds (&opP->disp),
2632 SEXT (offs (&opP->disp)),
8a104df9 2633 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2634
2635 break;
8a104df9 2636 }
252b5132
RH		 2637 }
2638 }
2639 else
2640 {
36759679 2641 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2642 if (opP->index.reg >= ZDATA0
2643 && opP->index.reg <= ZDATA7)
2644 nextword |= (opP->index.reg - ZDATA0) << 12;
2645 else if (opP->index.reg >= ZADDR0
2646 || opP->index.reg <= ZADDR7)
2647 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2648 }
2649
2650 /* It isn't simple. */
2651
2652 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2653 || arch_coldfire_p (current_architecture))
252b5132
RH		 2654 opP->error =
2655 _("invalid operand mode for this architecture; needs 68020 or higher");
2656
2657 nextword |= 0x100;
2658 /* If the guy specified a width, we assume that it is
2659 wide enough. Maybe it isn't. If so, we lose. */
2660 switch (siz1)
2661 {
2662 case SIZE_UNSPEC:
2663 if (isvar (&opP->disp)
2664 ? m68k_rel32
2665 : ! issword (baseo))
2666 {
2667 siz1 = SIZE_LONG;
2668 nextword |= 0x30;
2669 }
2670 else if (! isvar (&opP->disp) && baseo == 0)
2671 nextword |= 0x10;
2672 else
2673 {
2674 nextword |= 0x20;
2675 siz1 = SIZE_WORD;
2676 }
2677 break;
2678 case SIZE_BYTE:
2679 as_warn (_(":b not permitted; defaulting to :w"));
2680 /* Fall through. */
2681 case SIZE_WORD:
2682 nextword |= 0x20;
2683 break;
2684 case SIZE_LONG:
2685 nextword |= 0x30;
2686 break;
2687 }
2688
67c1ffbe 2689 /* Figure out inner displacement stuff. */
252b5132
RH		 2690 if (opP->mode == POST || opP->mode == PRE)
2691 {
2692 if (cpu_of_arch (current_architecture) & cpu32)
2693 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2694 switch (siz2)
2695 {
2696 case SIZE_UNSPEC:
2697 if (isvar (&opP->odisp)
2698 ? m68k_rel32
2699 : ! issword (outro))
2700 {
2701 siz2 = SIZE_LONG;
2702 nextword |= 0x3;
2703 }
2704 else if (! isvar (&opP->odisp) && outro == 0)
2705 nextword |= 0x1;
2706 else
2707 {
2708 nextword |= 0x2;
2709 siz2 = SIZE_WORD;
2710 }
2711 break;
2712 case 1:
2713 as_warn (_(":b not permitted; defaulting to :w"));
2714 /* Fall through. */
2715 case 2:
2716 nextword |= 0x2;
2717 break;
2718 case 3:
2719 nextword |= 0x3;
2720 break;
2721 }
2722 if (opP->mode == POST
2723 && (nextword & 0x40) == 0)
2724 nextword |= 0x04;
2725 }
2726 addword (nextword);
2727
2728 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2729 {
2730 if (opP->reg == PC || opP->reg == ZPC)
2731 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2732 else
2733 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2734 }
2735 if (siz1 == SIZE_LONG)
2736 addword (baseo >> 16);
2737 if (siz1 != SIZE_UNSPEC)
2738 addword (baseo);
2739
2740 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2741 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2742 if (siz2 == SIZE_LONG)
2743 addword (outro >> 16);
2744 if (siz2 != SIZE_UNSPEC)
2745 addword (outro);
2746
2747 break;
2748
2749 case ABSL:
3e602632 2750 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2751 switch (opP->disp.size)
2752 {
2753 default:
2754 abort ();
2755 case SIZE_UNSPEC:
2756 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2757 {
2758 tmpreg = 0x38; /* 7.0 */
2759 addword (nextword);
2760 break;
2761 }
252b5132
RH		 2762 if (isvar (&opP->disp)
2763 && !subs (&opP->disp)
2764 && adds (&opP->disp)
2765#ifdef OBJ_ELF
2766 /* If the displacement needs pic relocation it
2767 cannot be relaxed. */
2768 && opP->disp.pic_reloc == pic_none
2769#endif
252b5132
RH		 2770 && !flag_long_jumps
2771 && !strchr ("~%&$?", s[0]))
2772 {
2773 tmpreg = 0x3A; /* 7.2 */
2774 add_frag (adds (&opP->disp),
bd17c2c3 2775 SEXT (offs (&opP->disp)),
151337e8 2776 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2777 break;
2778 }
36759679 2779 /* Fall through into long. */
252b5132
RH		 2780 case SIZE_LONG:
2781 if (isvar (&opP->disp))
2782 add_fix ('l', &opP->disp, 0, 0);
2783
2784 tmpreg = 0x39;/* 7.1 mode */
2785 addword (nextword >> 16);
2786 addword (nextword);
2787 break;
2788
2789 case SIZE_BYTE:
2790 as_bad (_("unsupported byte value; use a different suffix"));
2791 /* Fall through. */
36759679
NC		 2792
2793 case SIZE_WORD:
252b5132
RH		 2794 if (isvar (&opP->disp))
2795 add_fix ('w', &opP->disp, 0, 0);
2796
2797 tmpreg = 0x38;/* 7.0 mode */
2798 addword (nextword);
2799 break;
2800 }
2801 break;
2802 case CONTROL:
2803 case FPREG:
2804 default:
2805 as_bad (_("unknown/incorrect operand"));
bc805888 2806 /* abort (); */
252b5132 2807 }
fd99574b
NC		 2808
2809 /* If s[0] is '4', then this is for the mac instructions
2810 that can have a trailing_ampersand set. If so, set 0x100
2811 bit on tmpreg so install_gen_operand can check for it and
2812 set the appropriate bit (word2, bit 5). */
2813 if (s[0] == '4')
2814 {
2815 if (opP->trailing_ampersand)
2816 tmpreg |= 0x100;
2817 }
252b5132
RH		 2818 install_gen_operand (s[1], tmpreg);
2819 break;
2820
2821 case '#':
2822 case '^':
2823 switch (s[1])
2824 { /* JF: I hate floating point! */
2825 case 'j':
2826 tmpreg = 70;
2827 break;
2828 case '8':
2829 tmpreg = 20;
2830 break;
2831 case 'C':
2832 tmpreg = 50;
2833 break;
2834 case '3':
2835 default:
3e602632 2836 tmpreg = 90;
252b5132
RH		 2837 break;
2838 }
2839 tmpreg = get_num (&opP->disp, tmpreg);
2840 if (isvar (&opP->disp))
2841 add_fix (s[1], &opP->disp, 0, 0);
2842 switch (s[1])
2843 {
2844 case 'b': /* Danger: These do no check for
2845 certain types of overflow.
2846 user beware! */
2847 if (!isbyte (tmpreg))
2848 opP->error = _("out of range");
2849 insop (tmpreg, opcode);
2850 if (isvar (&opP->disp))
2851 the_ins.reloc[the_ins.nrel - 1].n =
2852 (opcode->m_codenum) * 2 + 1;
2853 break;
2854 case 'B':
2855 if (!issbyte (tmpreg))
2856 opP->error = _("out of range");
2857 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2858 if (isvar (&opP->disp))
2859 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2860 break;
2861 case 'w':
2862 if (!isword (tmpreg))
2863 opP->error = _("out of range");
2864 insop (tmpreg, opcode);
2865 if (isvar (&opP->disp))
2866 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2867 break;
2868 case 'W':
2869 if (!issword (tmpreg))
2870 opP->error = _("out of range");
2871 insop (tmpreg, opcode);
2872 if (isvar (&opP->disp))
2873 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2874 break;
2875 case 'l':
2876 /* Because of the way insop works, we put these two out
2877 backwards. */
2878 insop (tmpreg, opcode);
2879 insop (tmpreg >> 16, opcode);
2880 if (isvar (&opP->disp))
2881 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2882 break;
2883 case '3':
2884 tmpreg &= 0xFF;
2885 case '8':
2886 case 'C':
2887 case 'j':
2888 install_operand (s[1], tmpreg);
2889 break;
2890 default:
2891 abort ();
2892 }
2893 break;
2894
2895 case '+':
2896 case '-':
2897 case 'A':
2898 case 'a':
2899 install_operand (s[1], opP->reg - ADDR);
2900 break;
2901
2902 case 'B':
3e602632 2903 tmpreg = get_num (&opP->disp, 90);
9a2e615a 2904
252b5132
RH		 2905 switch (s[1])
2906 {
2907 case 'B':
8390138c 2908 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2909 break;
2910 case 'W':
2911 add_fix ('w', &opP->disp, 1, 0);
2912 addword (0);
2913 break;
2914 case 'L':
2915 long_branch:
151337e8 2916 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2917 add_fix ('l', &opP->disp, 1, 0);
2918 addword (0);
2919 addword (0);
2920 break;
9a2e615a
NS		 2921 case 'g': /* Conditional branch */
2922 have_disp = HAVE_LONG_CALL (current_architecture);
2923 goto var_branch;
2924
2925 case 'b': /* Unconditional branch */
2926 have_disp = HAVE_LONG_BRANCH (current_architecture);
2927 goto var_branch;
2928
2929 case 's': /* Unconditional subroutine */
2930 have_disp = HAVE_LONG_CALL (current_architecture);
2931
2932 var_branch:
2933 if (subs (&opP->disp) /* We can't relax it. */
252b5132 2934#ifdef OBJ_ELF
9a2e615a
NS		 2935 /* If the displacement needs pic relocation it cannot be
2936 relaxed. */
2937 || opP->disp.pic_reloc != pic_none
252b5132 2938#endif
9a2e615a
NS		 2939 || 0)
2940 {
2941 if (!have_disp)
2942 as_warn (_("Can't use long branches on this architecture"));
2943 goto long_branch;
2944 }
2945
252b5132 2946 /* This could either be a symbol, or an absolute
151337e8
NC		 2947 address. If it's an absolute address, turn it into
2948 an absolute jump right here and keep it out of the
2949 relaxer. */
2950 if (adds (&opP->disp) == 0)
2951 {
2952 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2953 the_ins.opcode[0] = 0x4EF9;
151337e8 2954 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2955 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2956 else /* jCC */
2957 {
2958 the_ins.opcode[0] ^= 0x0100;
2959 the_ins.opcode[0] |= 0x0006;
18566f55 2960 addword (0x4EF9);
151337e8
NC		 2961 }
2962 add_fix ('l', &opP->disp, 0, 0);
2963 addword (0);
2964 addword (0);
2965 break;
2966 }
2967
2968 /* Now we know it's going into the relaxer. Now figure
2969 out which mode. We try in this order of preference:
2970 long branch, absolute jump, byte/word branches only. */
9a2e615a 2971 if (have_disp)
bd17c2c3
AM		 2972 add_frag (adds (&opP->disp),
2973 SEXT (offs (&opP->disp)),
151337e8
NC		 2974 TAB (BRANCHBWL, SZ_UNDEF));
2975 else if (! flag_keep_pcrel)
2976 {
2977 if ((the_ins.opcode[0] == 0x6000)
2978 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2979 add_frag (adds (&opP->disp),
2980 SEXT (offs (&opP->disp)),
151337e8
NC		 2981 TAB (BRABSJUNC, SZ_UNDEF));
2982 else
bd17c2c3
AM		 2983 add_frag (adds (&opP->disp),
2984 SEXT (offs (&opP->disp)),
151337e8
NC		 2985 TAB (BRABSJCOND, SZ_UNDEF));
2986 }
252b5132 2987 else
bd17c2c3
AM		 2988 add_frag (adds (&opP->disp),
2989 SEXT (offs (&opP->disp)),
151337e8 2990 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2991 break;
2992 case 'w':
2993 if (isvar (&opP->disp))
2994 {
151337e8
NC		 2995 /* Check for DBcc instructions. We can relax them,
2996 but only if we have long branches and/or absolute
2997 jumps. */
2998 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2999 && (HAVE_LONG_BRANCH (current_architecture)
9a2e615a 3000 || ! flag_keep_pcrel))
252b5132 3001 {
151337e8 3002 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 3003 add_frag (adds (&opP->disp),
3004 SEXT (offs (&opP->disp)),
151337e8
NC		 3005 TAB (DBCCLBR, SZ_UNDEF));
3006 else
bd17c2c3
AM		 3007 add_frag (adds (&opP->disp),
3008 SEXT (offs (&opP->disp)),
151337e8 3009 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 3010 break;
3011 }
252b5132
RH		 3012 add_fix ('w', &opP->disp, 1, 0);
3013 }
3014 addword (0);
3015 break;
36759679 3016 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 3017 add_fix ('l', &opP->disp, 1, 0);
3018 addword (0);
3019 addword (0);
3020 break;
36759679 3021 case 'c': /* Var size Coprocesssor branches. */
151337e8 3022 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 3023 {
252b5132
RH		 3024 the_ins.opcode[the_ins.numo - 1] |= 0x40;
3025 add_fix ('l', &opP->disp, 1, 0);
3026 addword (0);
3027 addword (0);
3028 }
151337e8 3029 else
bd17c2c3
AM		 3030 add_frag (adds (&opP->disp),
3031 SEXT (offs (&opP->disp)),
151337e8 3032 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 3033 break;
3034 default:
3035 abort ();
3036 }
3037 break;
3038
36759679 3039 case 'C': /* Ignore it. */
252b5132
RH		 3040 break;
3041
36759679 3042 case 'd': /* JF this is a kludge. */
252b5132 3043 install_operand ('s', opP->reg - ADDR);
3e602632 3044 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3045 if (!issword (tmpreg))
3046 {
3047 as_warn (_("Expression out of range, using 0"));
3048 tmpreg = 0;
3049 }
3050 addword (tmpreg);
3051 break;
3052
3053 case 'D':
3054 install_operand (s[1], opP->reg - DATA);
3055 break;
3056
fd99574b
NC		 3057 case 'e': /* EMAC ACCx, reg/reg. */
3058 install_operand (s[1], opP->reg - ACC);
3059 break;
3060
36759679 3061 case 'E': /* Ignore it. */
6da466c7
ILT		 3062 break;
3063
252b5132
RH		 3064 case 'F':
3065 install_operand (s[1], opP->reg - FP0);
3066 break;
3067
fd99574b
NC		 3068 case 'g': /* EMAC ACCEXTx. */
3069 install_operand (s[1], opP->reg - ACCEXT01);
3070 break;
3071
36759679 3072 case 'G': /* Ignore it. */
6da466c7
ILT		 3073 case 'H':
3074 break;
3075
252b5132
RH		 3076 case 'I':
3077 tmpreg = opP->reg - COP0;
3078 install_operand (s[1], tmpreg);
3079 break;
3080
fd99574b
NC		 3081 case 'i': /* MAC/EMAC scale factor. */
3082 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
3083 break;
3084
36759679 3085 case 'J': /* JF foo. */
252b5132
RH		 3086 switch (opP->reg)
3087 {
3088 case SFC:
3089 tmpreg = 0x000;
3090 break;
3091 case DFC:
3092 tmpreg = 0x001;
3093 break;
3094 case CACR:
3095 tmpreg = 0x002;
3096 break;
3097 case TC:
a8e24a56 3098 case ASID:
252b5132
RH		 3099 tmpreg = 0x003;
3100 break;
3e602632 3101 case ACR0:
252b5132
RH		 3102 case ITT0:
3103 tmpreg = 0x004;
3104 break;
3e602632 3105 case ACR1:
252b5132
RH		 3106 case ITT1:
3107 tmpreg = 0x005;
3108 break;
3e602632 3109 case ACR2:
252b5132
RH		 3110 case DTT0:
3111 tmpreg = 0x006;
3112 break;
3e602632 3113 case ACR3:
252b5132
RH		 3114 case DTT1:
3115 tmpreg = 0x007;
3116 break;
3117 case BUSCR:
a8e24a56 3118 case MMUBAR:
252b5132
RH		 3119 tmpreg = 0x008;
3120 break;
3121
3122 case USP:
3123 tmpreg = 0x800;
3124 break;
3125 case VBR:
3126 tmpreg = 0x801;
3127 break;
3128 case CAAR:
3129 tmpreg = 0x802;
3130 break;
3131 case MSP:
3132 tmpreg = 0x803;
3133 break;
3134 case ISP:
3135 tmpreg = 0x804;
3136 break;
3137 case MMUSR:
3138 tmpreg = 0x805;
3139 break;
3140 case URP:
3141 tmpreg = 0x806;
3142 break;
3143 case SRP:
3144 tmpreg = 0x807;
3145 break;
3146 case PCR:
3147 tmpreg = 0x808;
3148 break;
3149 case ROMBAR:
a8e24a56 3150 case ROMBAR0:
252b5132
RH		 3151 tmpreg = 0xC00;
3152 break;
3e602632
NC		 3153 case ROMBAR1:
3154 tmpreg = 0xC01;
3155 break;
3156 case FLASHBAR:
252b5132 3157 case RAMBAR0:
78336706 3158 case RAMBAR_ALT:
252b5132
RH		 3159 tmpreg = 0xC04;
3160 break;
3e602632 3161 case RAMBAR:
252b5132
RH		 3162 case RAMBAR1:
3163 tmpreg = 0xC05;
3164 break;
3e602632
NC		 3165 case MPCR:
3166 tmpreg = 0xC0C;
3167 break;
3168 case EDRAMBAR:
3169 tmpreg = 0xC0D;
3170 break;
3171 case MBAR0:
e80e0390 3172 case MBAR2:
3e602632
NC		 3173 case SECMBAR:
3174 tmpreg = 0xC0E;
3175 break;
3176 case MBAR1:
252b5132
RH		 3177 case MBAR:
3178 tmpreg = 0xC0F;
3179 break;
3e602632
NC		 3180 case PCR1U0:
3181 tmpreg = 0xD02;
3182 break;
3183 case PCR1L0:
3184 tmpreg = 0xD03;
3185 break;
3186 case PCR2U0:
3187 tmpreg = 0xD04;
3188 break;
3189 case PCR2L0:
3190 tmpreg = 0xD05;
3191 break;
3192 case PCR3U0:
3193 tmpreg = 0xD06;
3194 break;
3195 case PCR3L0:
3196 tmpreg = 0xD07;
3197 break;
3198 case PCR1L1:
3199 tmpreg = 0xD0A;
3200 break;
3201 case PCR1U1:
3202 tmpreg = 0xD0B;
3203 break;
3204 case PCR2L1:
3205 tmpreg = 0xD0C;
3206 break;
3207 case PCR2U1:
3208 tmpreg = 0xD0D;
3209 break;
3210 case PCR3L1:
3211 tmpreg = 0xD0E;
3212 break;
3213 case PCR3U1:
3214 tmpreg = 0xD0F;
3215 break;
f7ec513b
KH		 3216 case CAC:
3217 tmpreg = 0xFFE;
3218 break;
3219 case MBB:
3220 tmpreg = 0xFFF;
3221 break;
252b5132
RH		 3222 default:
3223 abort ();
3224 }
3225 install_operand (s[1], tmpreg);
3226 break;
3227
3228 case 'k':
3229 tmpreg = get_num (&opP->disp, 55);
3230 install_operand (s[1], tmpreg & 0x7f);
3231 break;
3232
3233 case 'l':
3234 tmpreg = opP->mask;
3235 if (s[1] == 'w')
3236 {
3237 if (tmpreg & 0x7FF0000)
3238 as_bad (_("Floating point register in register list"));
3239 insop (reverse_16_bits (tmpreg), opcode);
3240 }
3241 else
3242 {
3243 if (tmpreg & 0x700FFFF)
3244 as_bad (_("Wrong register in floating-point reglist"));
3245 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3246 }
3247 break;
3248
3249 case 'L':
3250 tmpreg = opP->mask;
3251 if (s[1] == 'w')
3252 {
3253 if (tmpreg & 0x7FF0000)
3254 as_bad (_("Floating point register in register list"));
3255 insop (tmpreg, opcode);
3256 }
3257 else if (s[1] == '8')
3258 {
3259 if (tmpreg & 0x0FFFFFF)
3260 as_bad (_("incorrect register in reglist"));
3261 install_operand (s[1], tmpreg >> 24);
3262 }
3263 else
3264 {
3265 if (tmpreg & 0x700FFFF)
3266 as_bad (_("wrong register in floating-point reglist"));
3267 else
3268 install_operand (s[1], tmpreg >> 16);
3269 }
3270 break;
3271
3272 case 'M':
3273 install_operand (s[1], get_num (&opP->disp, 60));
3274 break;
3275
3276 case 'O':
3277 tmpreg = ((opP->mode == DREG)
8fce3f5e 3278 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3279 : (get_num (&opP->disp, 40) & 0x1F));
3280 install_operand (s[1], tmpreg);
3281 break;
3282
3283 case 'Q':
3284 tmpreg = get_num (&opP->disp, 10);
3285 if (tmpreg == 8)
3286 tmpreg = 0;
3287 install_operand (s[1], tmpreg);
3288 break;
3289
3290 case 'R':
3291 /* This depends on the fact that ADDR registers are eight
3292 more than their corresponding DATA regs, so the result
36759679 3293 will have the ADDR_REG bit set. */
252b5132
RH		 3294 install_operand (s[1], opP->reg - DATA);
3295 break;
3296
3297 case 'r':
3298 if (opP->mode == AINDR)
3299 install_operand (s[1], opP->reg - DATA);
3300 else
3301 install_operand (s[1], opP->index.reg - DATA);
3302 break;
3303
3304 case 's':
3305 if (opP->reg == FPI)
3306 tmpreg = 0x1;
3307 else if (opP->reg == FPS)
3308 tmpreg = 0x2;
3309 else if (opP->reg == FPC)
3310 tmpreg = 0x4;
3311 else
3312 abort ();
3313 install_operand (s[1], tmpreg);
3314 break;
3315
36759679 3316 case 'S': /* Ignore it. */
252b5132
RH		 3317 break;
3318
3319 case 'T':
3320 install_operand (s[1], get_num (&opP->disp, 30));
3321 break;
3322
36759679 3323 case 'U': /* Ignore it. */
252b5132
RH		 3324 break;
3325
3326 case 'c':
3327 switch (opP->reg)
3328 {
3329 case NC:
3330 tmpreg = 0;
3331 break;
3332 case DC:
3333 tmpreg = 1;
3334 break;
3335 case IC:
3336 tmpreg = 2;
3337 break;
3338 case BC:
3339 tmpreg = 3;
3340 break;
3341 default:
3342 as_fatal (_("failed sanity check"));
36759679 3343 } /* switch on cache token. */
252b5132
RH		 3344 install_operand (s[1], tmpreg);
3345 break;
3346#ifndef NO_68851
92774660 3347 /* JF: These are out of order, I fear. */
252b5132
RH		 3348 case 'f':
3349 switch (opP->reg)
3350 {
3351 case SFC:
3352 tmpreg = 0;
3353 break;
3354 case DFC:
3355 tmpreg = 1;
3356 break;
3357 default:
3358 abort ();
3359 }
3360 install_operand (s[1], tmpreg);
3361 break;
3362
3363 case '0':
3364 case '1':
3365 case '2':
3366 switch (opP->reg)
3367 {
3368 case TC:
3369 tmpreg = 0;
3370 break;
3371 case CAL:
3372 tmpreg = 4;
3373 break;
3374 case VAL:
3375 tmpreg = 5;
3376 break;
3377 case SCC:
3378 tmpreg = 6;
3379 break;
3380 case AC:
3381 tmpreg = 7;
3382 break;
3383 default:
3384 abort ();
3385 }
3386 install_operand (s[1], tmpreg);
3387 break;
3388
3389 case 'V':
3390 if (opP->reg == VAL)
3391 break;
3392 abort ();
3393
3394 case 'W':
3395 switch (opP->reg)
3396 {
3397 case DRP:
3398 tmpreg = 1;
3399 break;
3400 case SRP:
3401 tmpreg = 2;
3402 break;
3403 case CRP:
3404 tmpreg = 3;
3405 break;
3406 default:
3407 abort ();
3408 }
3409 install_operand (s[1], tmpreg);
3410 break;
3411
3412 case 'X':
3413 switch (opP->reg)
3414 {
3415 case BAD:
3416 case BAD + 1:
3417 case BAD + 2:
3418 case BAD + 3:
3419 case BAD + 4:
3420 case BAD + 5:
3421 case BAD + 6:
3422 case BAD + 7:
3423 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3424 break;
3425
3426 case BAC:
3427 case BAC + 1:
3428 case BAC + 2:
3429 case BAC + 3:
3430 case BAC + 4:
3431 case BAC + 5:
3432 case BAC + 6:
3433 case BAC + 7:
3434 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3435 break;
3436
3437 default:
3438 abort ();
3439 }
3440 install_operand (s[1], tmpreg);
3441 break;
3442 case 'Y':
3443 know (opP->reg == PSR);
3444 break;
3445 case 'Z':
3446 know (opP->reg == PCSR);
3447 break;
3448#endif /* m68851 */
3449 case '3':
3450 switch (opP->reg)
3451 {
3452 case TT0:
3453 tmpreg = 2;
3454 break;
3455 case TT1:
3456 tmpreg = 3;
3457 break;
3458 default:
3459 abort ();
3460 }
3461 install_operand (s[1], tmpreg);
3462 break;
3463 case 't':
3464 tmpreg = get_num (&opP->disp, 20);
3465 install_operand (s[1], tmpreg);
3466 break;
36759679 3467 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3468 if (isvar (&opP->disp))
3469 add_fix ('l', &opP->disp, 0, 0);
3e602632 3470 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3471 addword (tmpreg >> 16);
3472 addword (tmpreg & 0xFFFF);
3473 break;
6da466c7
ILT		 3474 case 'u':
3475 install_operand (s[1], opP->reg - DATA0L);
3476 opP->reg -= (DATA0L);
36759679 3477 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3478 break;
3e602632
NC		 3479 case 'x':
3480 tmpreg = get_num (&opP->disp, 80);
3481 if (tmpreg == -1)
3482 tmpreg = 0;
3483 install_operand (s[1], tmpreg);
3484 break;
252b5132
RH		 3485 default:
3486 abort ();
3487 }
3488 }
3489
3490 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3491 instruction, ready to be emitted. . . */
252b5132
RH		 3492}
3493
3494static int
31302357 3495reverse_16_bits (int in)
252b5132
RH		 3496{
3497 int out = 0;
3498 int n;
3499
3500 static int mask[16] =
3501 {
3502 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3503 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3504 };
3505 for (n = 0; n < 16; n++)
3506 {
3507 if (in & mask[n])
3508 out |= mask[15 - n];
3509 }
3510 return out;
3511} /* reverse_16_bits() */
3512
3513static int
31302357 3514reverse_8_bits (int in)
252b5132
RH		 3515{
3516 int out = 0;
3517 int n;
3518
3519 static int mask[8] =
3520 {
3521 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3522 };
3523
3524 for (n = 0; n < 8; n++)
3525 {
3526 if (in & mask[n])
3527 out |= mask[7 - n];
3528 }
3529 return out;
3530} /* reverse_8_bits() */
3531
3532/* Cause an extra frag to be generated here, inserting up to 10 bytes
3533 (that value is chosen in the frag_var call in md_assemble). TYPE
3534 is the subtype of the frag to be generated; its primary type is
3535 rs_machine_dependent.
3536
3537 The TYPE parameter is also used by md_convert_frag_1 and
3538 md_estimate_size_before_relax. The appropriate type of fixup will
3539 be emitted by md_convert_frag_1.
3540
3541 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3542static void
31302357 3543install_operand (int mode, int val)
252b5132
RH		 3544{
3545 switch (mode)
3546 {
3547 case 's':
36759679 3548 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3549 break;
3550 case 'd':
3551 the_ins.opcode[0] |= val << 9;
3552 break;
3553 case '1':
3554 the_ins.opcode[1] |= val << 12;
3555 break;
3556 case '2':
3557 the_ins.opcode[1] |= val << 6;
3558 break;
3559 case '3':
3560 the_ins.opcode[1] |= val;
3561 break;
3562 case '4':
3563 the_ins.opcode[2] |= val << 12;
3564 break;
3565 case '5':
3566 the_ins.opcode[2] |= val << 6;
3567 break;
3568 case '6':
3569 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3570 three words long! */
3571 the_ins.numo++;
3572 the_ins.opcode[2] |= val;
3573 break;
3574 case '7':
3575 the_ins.opcode[1] |= val << 7;
3576 break;
3577 case '8':
3578 the_ins.opcode[1] |= val << 10;
3579 break;
3580#ifndef NO_68851
3581 case '9':
3582 the_ins.opcode[1] |= val << 5;
3583 break;
3584#endif
3585
3586 case 't':
3587 the_ins.opcode[1] |= (val << 10) | (val << 7);
3588 break;
3589 case 'D':
3590 the_ins.opcode[1] |= (val << 12) | val;
3591 break;
3592 case 'g':
3593 the_ins.opcode[0] |= val = 0xff;
3594 break;
3595 case 'i':
3596 the_ins.opcode[0] |= val << 9;
3597 break;
3598 case 'C':
3599 the_ins.opcode[1] |= val;
3600 break;
3601 case 'j':
3602 the_ins.opcode[1] |= val;
36759679 3603 the_ins.numo++; /* What a hack. */
252b5132
RH		 3604 break;
3605 case 'k':
3606 the_ins.opcode[1] |= val << 4;
3607 break;
3608 case 'b':
3609 case 'w':
3610 case 'W':
3611 case 'l':
3612 break;
3613 case 'e':
3614 the_ins.opcode[0] |= (val << 6);
3615 break;
3616 case 'L':
3617 the_ins.opcode[1] = (val >> 16);
3618 the_ins.opcode[2] = val & 0xffff;
3619 break;
6da466c7
ILT		 3620 case 'm':
3621 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3622 the_ins.opcode[0] |= ((val & 0x7) << 9);
3623 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3624 break;
fd99574b 3625 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3626 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3627 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3628 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3629 break;
fd99574b 3630 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3631 the_ins.opcode[1] |= val << 12;
3632 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3633 break;
fd99574b 3634 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3635 the_ins.opcode[0] |= (val & 0xF);
3636 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3637 break;
fd99574b 3638 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3639 the_ins.opcode[1] |= (val & 0xF);
3640 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3641 break;
3642 case 'h':
3643 the_ins.opcode[1] |= ((val != 1) << 10);
3644 break;
fd99574b
NC		 3645 case 'F':
3646 the_ins.opcode[0] |= ((val & 0x3) << 9);
3647 break;
3648 case 'f':
3649 the_ins.opcode[0] |= ((val & 0x3) << 0);
3650 break;
be8c092b 3651 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3652 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3653 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3654 break;
be8c092b 3655 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3656 the_ins.opcode[0] |= ((val & 0x1) << 7);
3657 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3658 break;
3659 case 'I':
3660 the_ins.opcode[1] |= ((val & 0x3) << 9);
3661 break;
3662 case ']':
3663 the_ins.opcode[0] |= (val & 0x1) <<10;
3664 break;
252b5132
RH		 3665 case 'c':
3666 default:
3667 as_fatal (_("failed sanity check."));
3668 }
6b6e92f4 3669}
252b5132
RH		 3670
3671static void
31302357 3672install_gen_operand (int mode, int val)
252b5132
RH		 3673{
3674 switch (mode)
3675 {
fd99574b
NC		 3676 case '/': /* Special for mask loads for mac/msac insns with
3677 possible mask; trailing_ampersend set in bit 8. */
3678 the_ins.opcode[0] |= (val & 0x3f);
3679 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3680 break;
252b5132
RH		 3681 case 's':
3682 the_ins.opcode[0] |= val;
3683 break;
3684 case 'd':
3685 /* This is a kludge!!! */
3686 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3687 break;
3688 case 'b':
3689 case 'w':
3690 case 'l':
3691 case 'f':
3692 case 'F':
3693 case 'x':
3694 case 'p':
3695 the_ins.opcode[0] |= val;
3696 break;
36759679 3697 /* more stuff goes here. */
252b5132
RH		 3698 default:
3699 as_fatal (_("failed sanity check."));
3700 }
6b6e92f4 3701}
252b5132 3702
6b6e92f4
NC		 3703/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3704 then deal with the bitfield hack. */
252b5132
RH		 3705
3706static char *
31302357 3707crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3708{
3709 register int parens;
3710 register int c;
3711 register char *beg_str;
3712 int inquote = 0;
3713
3714 if (!str)
3715 {
3716 return str;
3717 }
3718 beg_str = str;
3719 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3720 {
3721 if (! inquote)
3722 {
3723 if (*str == '(')
3724 parens++;
3725 else if (*str == ')')
3726 {
3727 if (!parens)
36759679 3728 { /* ERROR. */
252b5132
RH		 3729 opP->error = _("Extra )");
3730 return str;
3731 }
3732 --parens;
3733 }
3734 }
3735 if (flag_mri && *str == '\'')
3736 inquote = ! inquote;
3737 }
3738 if (!*str && parens)
36759679 3739 { /* ERROR. */
252b5132
RH		 3740 opP->error = _("Missing )");
3741 return str;
3742 }
3743 c = *str;
3744 *str = '\0';
3745 if (m68k_ip_op (beg_str, opP) != 0)
3746 {
3747 *str = c;
3748 return str;
3749 }
3750 *str = c;
3751 if (c == '}')
36759679 3752 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3753 if (c)
3754 {
3755 c = *++str;
3756 if (!c)
3757 as_bad (_("Missing operand"));
3758 }
3759
3760 /* Detect MRI REG symbols and convert them to REGLSTs. */
3761 if (opP->mode == CONTROL && (int)opP->reg < 0)
3762 {
3763 opP->mode = REGLST;
3764 opP->mask = ~(int)opP->reg;
3765 opP->reg = 0;
3766 }
3767
3768 return str;
3769}
3770
3771/* This is the guts of the machine-dependent assembler. STR points to a
3772 machine dependent instruction. This function is supposed to emit
3773 the frags/bytes it assembles to.
3774 */
3775
3776static void
31302357 3777insert_reg (const char *regname, int regnum)
252b5132
RH		 3778{
3779 char buf[100];
3780 int i;
3781
3782#ifdef REGISTER_PREFIX
3783 if (!flag_reg_prefix_optional)
3784 {
3785 buf[0] = REGISTER_PREFIX;
3786 strcpy (buf + 1, regname);
3787 regname = buf;
3788 }
3789#endif
3790
3791 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3792 &zero_address_frag));
3793
3794 for (i = 0; regname[i]; i++)
3882b010 3795 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3796 buf[i] = '\0';
3797
3798 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3799 &zero_address_frag));
3800}
3801
3802struct init_entry
3803 {
3804 const char *name;
3805 int number;
3806 };
3807
3808static const struct init_entry init_table[] =
3809{
3810 { "d0", DATA0 },
3811 { "d1", DATA1 },
3812 { "d2", DATA2 },
3813 { "d3", DATA3 },
3814 { "d4", DATA4 },
3815 { "d5", DATA5 },
3816 { "d6", DATA6 },
3817 { "d7", DATA7 },
3818 { "a0", ADDR0 },
3819 { "a1", ADDR1 },
3820 { "a2", ADDR2 },
3821 { "a3", ADDR3 },
3822 { "a4", ADDR4 },
3823 { "a5", ADDR5 },
3824 { "a6", ADDR6 },
3825 { "fp", ADDR6 },
3826 { "a7", ADDR7 },
3827 { "sp", ADDR7 },
3828 { "ssp", ADDR7 },
3829 { "fp0", FP0 },
3830 { "fp1", FP1 },
3831 { "fp2", FP2 },
3832 { "fp3", FP3 },
3833 { "fp4", FP4 },
3834 { "fp5", FP5 },
3835 { "fp6", FP6 },
3836 { "fp7", FP7 },
3837 { "fpi", FPI },
3838 { "fpiar", FPI },
3839 { "fpc", FPI },
3840 { "fps", FPS },
3841 { "fpsr", FPS },
3842 { "fpc", FPC },
3843 { "fpcr", FPC },
3844 { "control", FPC },
3845 { "status", FPS },
3846 { "iaddr", FPI },
3847
3848 { "cop0", COP0 },
3849 { "cop1", COP1 },
3850 { "cop2", COP2 },
3851 { "cop3", COP3 },
3852 { "cop4", COP4 },
3853 { "cop5", COP5 },
3854 { "cop6", COP6 },
3855 { "cop7", COP7 },
3856 { "pc", PC },
3857 { "zpc", ZPC },
3858 { "sr", SR },
3859
3860 { "ccr", CCR },
3861 { "cc", CCR },
3862
6da466c7 3863 { "acc", ACC },
fd99574b
NC		 3864 { "acc0", ACC },
3865 { "acc1", ACC1 },
3866 { "acc2", ACC2 },
3867 { "acc3", ACC3 },
3868 { "accext01", ACCEXT01 },
3869 { "accext23", ACCEXT23 },
6da466c7
ILT		 3870 { "macsr", MACSR },
3871 { "mask", MASK },
3872
36759679
NC		 3873 /* Control registers. */
3874 { "sfc", SFC }, /* Source Function Code. */
252b5132 3875 { "sfcr", SFC },
36759679 3876 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3877 { "dfcr", DFC },
36759679
NC		 3878 { "cacr", CACR }, /* Cache Control Register. */
3879 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3880
36759679
NC		 3881 { "usp", USP }, /* User Stack Pointer. */
3882 { "vbr", VBR }, /* Vector Base Register. */
3883 { "msp", MSP }, /* Master Stack Pointer. */
3884 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3885
36759679
NC		 3886 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3887 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3888 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3889 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3890
3891 /* 68ec040 versions of same */
36759679
NC		 3892 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3893 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3894 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3895 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132 3896
a8e24a56 3897 /* Coldfire versions of same. The ColdFire programmer's reference
252b5132
RH		 3898 manual indicated that the order is 2,3,0,1, but Ken Rose
3899 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3900 { "acr0", ACR0 }, /* Access Control Unit 0. */
3901 { "acr1", ACR1 }, /* Access Control Unit 1. */
3902 { "acr2", ACR2 }, /* Access Control Unit 2. */
3903 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3904
36759679 3905 { "tc", TC }, /* MMU Translation Control Register. */
252b5132 3906 { "tcr", TC },
a8e24a56 3907 { "asid", ASID },
252b5132 3908
36759679
NC		 3909 { "mmusr", MMUSR }, /* MMU Status Register. */
3910 { "srp", SRP }, /* User Root Pointer. */
3911 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3912
3913 { "buscr", BUSCR },
a8e24a56 3914 { "mmubar", MMUBAR },
252b5132
RH		 3915 { "pcr", PCR },
3916
36759679
NC		 3917 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3918 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3919 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3920 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3921
3922 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3923 { "mbar1", MBAR1 }, /* mcfv4e registers. */
a8e24a56 3924 { "rombar0", ROMBAR0 }, /* mcfv4e registers. */
3e602632
NC		 3925 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3926 { "mpcr", MPCR }, /* mcfv4e registers. */
3927 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3928 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3929 { "asid", TC }, /* mcfv4e registers. */
3930 { "mmubar", BUSCR }, /* mcfv4e registers. */
3931 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3932 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3933 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3934 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3935 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3936 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3937 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3938 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3939 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3940 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3941 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3942 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3943
3944 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3945 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3946
3947 { "mbar2", MBAR2 }, /* mcf5249 registers. */
f7ec513b
KH		 3948
3949 { "cac", CAC }, /* fido registers. */
3950 { "mbb", MBB }, /* fido registers. */
36759679 3951 /* End of control registers. */
252b5132
RH		 3952
3953 { "ac", AC },
3954 { "bc", BC },
3955 { "cal", CAL },
3956 { "crp", CRP },
3957 { "drp", DRP },
3958 { "pcsr", PCSR },
3959 { "psr", PSR },
3960 { "scc", SCC },
3961 { "val", VAL },
3962 { "bad0", BAD0 },
3963 { "bad1", BAD1 },
3964 { "bad2", BAD2 },
3965 { "bad3", BAD3 },
3966 { "bad4", BAD4 },
3967 { "bad5", BAD5 },
3968 { "bad6", BAD6 },
3969 { "bad7", BAD7 },
3970 { "bac0", BAC0 },
3971 { "bac1", BAC1 },
3972 { "bac2", BAC2 },
3973 { "bac3", BAC3 },
3974 { "bac4", BAC4 },
3975 { "bac5", BAC5 },
3976 { "bac6", BAC6 },
3977 { "bac7", BAC7 },
3978
3979 { "ic", IC },
3980 { "dc", DC },
3981 { "nc", NC },
3982
3983 { "tt0", TT0 },
3984 { "tt1", TT1 },
36759679 3985 /* 68ec030 versions of same. */
252b5132
RH		 3986 { "ac0", TT0 },
3987 { "ac1", TT1 },
36759679 3988 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3989 { "acusr", PSR },
3990
3991 /* Suppressed data and address registers. */
3992 { "zd0", ZDATA0 },
3993 { "zd1", ZDATA1 },
3994 { "zd2", ZDATA2 },
3995 { "zd3", ZDATA3 },
3996 { "zd4", ZDATA4 },
3997 { "zd5", ZDATA5 },
3998 { "zd6", ZDATA6 },
3999 { "zd7", ZDATA7 },
4000 { "za0", ZADDR0 },
4001 { "za1", ZADDR1 },
4002 { "za2", ZADDR2 },
4003 { "za3", ZADDR3 },
4004 { "za4", ZADDR4 },
4005 { "za5", ZADDR5 },
4006 { "za6", ZADDR6 },
4007 { "za7", ZADDR7 },
4008
92774660 4009 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 4010 { "d0l", DATA0L },
4011 { "d1l", DATA1L },
4012 { "d2l", DATA2L },
4013 { "d3l", DATA3L },
4014 { "d4l", DATA4L },
4015 { "d5l", DATA5L },
4016 { "d6l", DATA6L },
4017 { "d7l", DATA7L },
4018
4019 { "a0l", ADDR0L },
4020 { "a1l", ADDR1L },
4021 { "a2l", ADDR2L },
4022 { "a3l", ADDR3L },
4023 { "a4l", ADDR4L },
4024 { "a5l", ADDR5L },
4025 { "a6l", ADDR6L },
4026 { "a7l", ADDR7L },
4027
4028 { "d0u", DATA0U },
4029 { "d1u", DATA1U },
4030 { "d2u", DATA2U },
4031 { "d3u", DATA3U },
4032 { "d4u", DATA4U },
4033 { "d5u", DATA5U },
4034 { "d6u", DATA6U },
4035 { "d7u", DATA7U },
4036
4037 { "a0u", ADDR0U },
4038 { "a1u", ADDR1U },
4039 { "a2u", ADDR2U },
4040 { "a3u", ADDR3U },
4041 { "a4u", ADDR4U },
4042 { "a5u", ADDR5U },
4043 { "a6u", ADDR6U },
4044 { "a7u", ADDR7U },
4045
252b5132
RH		 4046 { 0, 0 }
4047};
4048
4049static void
31302357 4050init_regtable (void)
252b5132
RH		 4051{
4052 int i;
4053 for (i = 0; init_table[i].name; i++)
4054 insert_reg (init_table[i].name, init_table[i].number);
4055}
4056
252b5132 4057void
31302357 4058md_assemble (char *str)
252b5132
RH		 4059{
4060 const char *er;
4061 short *fromP;
4062 char *toP = NULL;
4063 int m, n = 0;
4064 char *to_beg_P;
4065 int shorts_this_frag;
4066 fixS *fixP;
4067
266abb8f
NS		 4068 if (!selected_cpu && !selected_arch)
4069 {
4070 /* We've not selected an architecture yet. Set the default
4071 now. We do this lazily so that an initial .cpu or .arch directive
4072 can specify. */
4073 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
4074 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
4075 }
4076 if (!initialized)
4077 m68k_init_arch ();
4078
252b5132
RH		 4079 /* In MRI mode, the instruction and operands are separated by a
4080 space. Anything following the operands is a comment. The label
4081 has already been removed. */
4082 if (flag_mri)
4083 {
4084 char *s;
4085 int fields = 0;
4086 int infield = 0;
4087 int inquote = 0;
4088
4089 for (s = str; *s != '\0'; s++)
4090 {
4091 if ((*s == ' ' || *s == '\t') && ! inquote)
4092 {
4093 if (infield)
4094 {
4095 ++fields;
4096 if (fields >= 2)
4097 {
4098 *s = '\0';
4099 break;
4100 }
4101 infield = 0;
4102 }
4103 }
4104 else
4105 {
4106 if (! infield)
4107 infield = 1;
4108 if (*s == '\'')
4109 inquote = ! inquote;
4110 }
4111 }
4112 }
4113
31302357 4114 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 4115 m68k_ip (str);
4116 er = the_ins.error;
4117 if (!er)
4118 {
4119 for (n = 0; n < the_ins.numargs; n++)
4120 if (the_ins.operands[n].error)
4121 {
4122 er = the_ins.operands[n].error;
4123 break;
4124 }
4125 }
4126 if (er)
4127 {
4128 as_bad (_("%s -- statement `%s' ignored"), er, str);
4129 return;
4130 }
4131
4132 /* If there is a current label, record that it marks an instruction. */
4133 if (current_label != NULL)
4134 {
4135 current_label->text = 1;
4136 current_label = NULL;
4137 }
4138
f27a3839
AS		 4139#ifdef OBJ_ELF
4140 /* Tie dwarf2 debug info to the address at the start of the insn. */
4141 dwarf2_emit_insn (0);
4142#endif
4143
252b5132
RH		 4144 if (the_ins.nfrag == 0)
4145 {
36759679 4146 /* No frag hacking involved; just put it out. */
252b5132
RH		 4147 toP = frag_more (2 * the_ins.numo);
4148 fromP = &the_ins.opcode[0];
4149 for (m = the_ins.numo; m; --m)
4150 {
4151 md_number_to_chars (toP, (long) (*fromP), 2);
4152 toP += 2;
4153 fromP++;
4154 }
36759679 4155 /* Put out symbol-dependent info. */
252b5132
RH		 4156 for (m = 0; m < the_ins.nrel; m++)
4157 {
4158 switch (the_ins.reloc[m].wid)
4159 {
4160 case 'B':
4161 n = 1;
4162 break;
4163 case 'b':
4164 n = 1;
4165 break;
4166 case '3':
4167 n = 1;
4168 break;
4169 case 'w':
4170 case 'W':
4171 n = 2;
4172 break;
4173 case 'l':
4174 n = 4;
4175 break;
4176 default:
4177 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4178 the_ins.reloc[m].wid);
4179 }
4180
4181 fixP = fix_new_exp (frag_now,
4182 ((toP - frag_now->fr_literal)
4183 - the_ins.numo * 2 + the_ins.reloc[m].n),
4184 n,
4185 &the_ins.reloc[m].exp,
4186 the_ins.reloc[m].pcrel,
4187 get_reloc_code (n, the_ins.reloc[m].pcrel,
4188 the_ins.reloc[m].pic_reloc));
4189 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4190 if (the_ins.reloc[m].wid == 'B')
4191 fixP->fx_signed = 1;
4192 }
4193 return;
4194 }
4195
36759679 4196 /* There's some frag hacking. */
fbe572f9
AM		 4197 {
4198 /* Calculate the max frag size. */
4199 int wid;
4200
4201 wid = 2 * the_ins.fragb[0].fragoff;
4202 for (n = 1; n < the_ins.nfrag; n++)
4203 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4204 /* frag_var part. */
4205 wid += 10;
4206 /* Make sure the whole insn fits in one chunk, in particular that
4207 the var part is attached, as we access one byte before the
4208 variable frag for byte branches. */
4209 frag_grow (wid);
4210 }
4211
252b5132
RH		 4212 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4213 {
4214 int wid;
4215
4216 if (n == 0)
4217 wid = 2 * the_ins.fragb[n].fragoff;
4218 else
4219 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4220 toP = frag_more (wid);
4221 to_beg_P = toP;
4222 shorts_this_frag = 0;
4223 for (m = wid / 2; m; --m)
4224 {
4225 md_number_to_chars (toP, (long) (*fromP), 2);
4226 toP += 2;
4227 fromP++;
4228 shorts_this_frag++;
4229 }
4230 for (m = 0; m < the_ins.nrel; m++)
4231 {
4232 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4233 {
4234 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4235 break;
4236 }
4237 wid = the_ins.reloc[m].wid;
4238 if (wid == 0)
4239 continue;
4240 the_ins.reloc[m].wid = 0;
4241 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4242
4243 fixP = fix_new_exp (frag_now,
4244 ((toP - frag_now->fr_literal)
4245 - the_ins.numo * 2 + the_ins.reloc[m].n),
4246 wid,
4247 &the_ins.reloc[m].exp,
4248 the_ins.reloc[m].pcrel,
4249 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4250 the_ins.reloc[m].pic_reloc));
4251 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4252 }
4253 (void) frag_var (rs_machine_dependent, 10, 0,
4254 (relax_substateT) (the_ins.fragb[n].fragty),
4255 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4256 }
4257 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4258 shorts_this_frag = 0;
4259 if (n)
4260 {
055d1eb0 4261 toP = frag_more (n * 2);
252b5132
RH		 4262 while (n--)
4263 {
4264 md_number_to_chars (toP, (long) (*fromP), 2);
4265 toP += 2;
4266 fromP++;
4267 shorts_this_frag++;
4268 }
4269 }
4270 for (m = 0; m < the_ins.nrel; m++)
4271 {
4272 int wid;
4273
4274 wid = the_ins.reloc[m].wid;
4275 if (wid == 0)
4276 continue;
4277 the_ins.reloc[m].wid = 0;
4278 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4279
4280 fixP = fix_new_exp (frag_now,
4281 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4282 - shorts_this_frag * 2),
4283 wid,
4284 &the_ins.reloc[m].exp,
4285 the_ins.reloc[m].pcrel,
4286 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4287 the_ins.reloc[m].pic_reloc));
4288 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4289 }
4290}
4291
60fed2d3
NC		 4292/* Comparison function used by qsort to rank the opcode entries by name. */
4293
4294static int
4295m68k_compare_opcode (const void * v1, const void * v2)
4296{
4297 struct m68k_opcode * op1, * op2;
4298 int ret;
4299
03b13e59
NC		 4300 if (v1 == v2)
4301 return 0;
4302
60fed2d3
NC		 4303 op1 = *(struct m68k_opcode **) v1;
4304 op2 = *(struct m68k_opcode **) v2;
4305
4306 /* Compare the two names. If different, return the comparison.
4307 If the same, return the order they are in the opcode table. */
4308 ret = strcmp (op1->name, op2->name);
4309 if (ret)
4310 return ret;
4311 if (op1 < op2)
4312 return -1;
03b13e59 4313 return 1;
60fed2d3
NC		 4314}
4315
252b5132 4316void
60fed2d3 4317md_begin (void)
252b5132 4318{
60fed2d3
NC		 4319 const struct m68k_opcode *ins;
4320 struct m68k_incant *hack, *slak;
4321 const char *retval = 0; /* Empty string, or error msg text. */
4322 int i;
4323
4324 /* Set up hash tables with 68000 instructions.
4325 similar to what the vax assembler does. */
252b5132
RH		 4326 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4327 a copy of it at runtime, adding in the information we want but isn't
4328 there. I think it'd be better to have an awk script hack the table
4329 at compile time. Or even just xstr the table and use it as-is. But
4330 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4331 names. */
4332
252b5132
RH		 4333 if (flag_mri)
4334 {
4335 flag_reg_prefix_optional = 1;
4336 m68k_abspcadd = 1;
4337 if (! m68k_rel32_from_cmdline)
4338 m68k_rel32 = 0;
4339 }
4340
60fed2d3
NC		 4341 /* First sort the opcode table into alphabetical order to seperate
4342 the order that the assembler wants to see the opcodes from the
4343 order that the disassembler wants to see them. */
4344 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4345 if (!m68k_sorted_opcodes)
4346 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4347 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4348
4349 for (i = m68k_numopcodes; i--;)
4350 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4351
4352 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4353 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4354
252b5132
RH		 4355 op_hash = hash_new ();
4356
4357 obstack_begin (&robyn, 4000);
4358 for (i = 0; i < m68k_numopcodes; i++)
4359 {
4360 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4361 do
4362 {
60fed2d3
NC		 4363 ins = m68k_sorted_opcodes[i];
4364
4365 /* We *could* ignore insns that don't match our
4366 arch here by just leaving them out of the hash. */
252b5132
RH		 4367 slak->m_operands = ins->args;
4368 slak->m_opnum = strlen (slak->m_operands) / 2;
4369 slak->m_arch = ins->arch;
4370 slak->m_opcode = ins->opcode;
36759679 4371 /* This is kludgey. */
252b5132
RH		 4372 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4373 if (i + 1 != m68k_numopcodes
60fed2d3 4374 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4375 {
60fed2d3 4376 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4377 i++;
4378 }
4379 else
4380 slak->m_next = 0;
4381 slak = slak->m_next;
4382 }
4383 while (slak);
4384
4385 retval = hash_insert (op_hash, ins->name, (char *) hack);
4386 if (retval)
4387 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4388 }
4389
4390 for (i = 0; i < m68k_numaliases; i++)
4391 {
4392 const char *name = m68k_opcode_aliases[i].primary;
4393 const char *alias = m68k_opcode_aliases[i].alias;
4394 PTR val = hash_find (op_hash, name);
60fed2d3 4395
252b5132
RH		 4396 if (!val)
4397 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4398 retval = hash_insert (op_hash, alias, val);
4399 if (retval)
4400 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4401 }
4402
4403 /* In MRI mode, all unsized branches are variable sized. Normally,
4404 they are word sized. */
4405 if (flag_mri)
4406 {
4407 static struct m68k_opcode_alias mri_aliases[] =
4408 {
4409 { "bhi", "jhi", },
4410 { "bls", "jls", },
4411 { "bcc", "jcc", },
4412 { "bcs", "jcs", },
4413 { "bne", "jne", },
4414 { "beq", "jeq", },
4415 { "bvc", "jvc", },
4416 { "bvs", "jvs", },
4417 { "bpl", "jpl", },
4418 { "bmi", "jmi", },
4419 { "bge", "jge", },
4420 { "blt", "jlt", },
4421 { "bgt", "jgt", },
4422 { "ble", "jle", },
4423 { "bra", "jra", },
4424 { "bsr", "jbsr", },
4425 };
4426
8fce3f5e
AM		 4427 for (i = 0;
4428 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4429 i++)
252b5132
RH		 4430 {
4431 const char *name = mri_aliases[i].primary;
4432 const char *alias = mri_aliases[i].alias;
4433 PTR val = hash_find (op_hash, name);
60fed2d3 4434
252b5132
RH		 4435 if (!val)
4436 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4437 retval = hash_jam (op_hash, alias, val);
4438 if (retval)
4439 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4440 }
4441 }
4442
8fce3f5e 4443 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4444 {
4445 notend_table[i] = 0;
4446 alt_notend_table[i] = 0;
4447 }
60fed2d3 4448
252b5132
RH		 4449 notend_table[','] = 1;
4450 notend_table['{'] = 1;
4451 notend_table['}'] = 1;
4452 alt_notend_table['a'] = 1;
4453 alt_notend_table['A'] = 1;
4454 alt_notend_table['d'] = 1;
4455 alt_notend_table['D'] = 1;
4456 alt_notend_table['#'] = 1;
4457 alt_notend_table['&'] = 1;
4458 alt_notend_table['f'] = 1;
4459 alt_notend_table['F'] = 1;
4460#ifdef REGISTER_PREFIX
4461 alt_notend_table[REGISTER_PREFIX] = 1;
4462#endif
4463
4464 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4465 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4466 alt_notend_table['('] = 1;
4467
4468 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4469 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4470 alt_notend_table['@'] = 1;
4471
4472 /* We need to put digits in alt_notend_table to handle
60fed2d3 4473 bfextu %d0{24:1},%d0 */
252b5132
RH		 4474 alt_notend_table['0'] = 1;
4475 alt_notend_table['1'] = 1;
4476 alt_notend_table['2'] = 1;
4477 alt_notend_table['3'] = 1;
4478 alt_notend_table['4'] = 1;
4479 alt_notend_table['5'] = 1;
4480 alt_notend_table['6'] = 1;
4481 alt_notend_table['7'] = 1;
4482 alt_notend_table['8'] = 1;
4483 alt_notend_table['9'] = 1;
4484
4485#ifndef MIT_SYNTAX_ONLY
4486 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4487 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4488 {
4489 int n = 0;
60fed2d3 4490
252b5132
RH		 4491 while (mote_pseudo_table[n].poc_name)
4492 {
60fed2d3 4493 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4494 hash_insert (op_hash,
4495 mote_pseudo_table[n].poc_name, (char *) hack);
4496 hack->m_operands = 0;
4497 hack->m_opnum = n;
4498 n++;
4499 }
4500 }
4501#endif
4502
4503 init_regtable ();
4504
4505#ifdef OBJ_ELF
4506 record_alignment (text_section, 2);
4507 record_alignment (data_section, 2);
4508 record_alignment (bss_section, 2);
4509#endif
4510}
4511
252b5132
RH		 4512\f
4513/* This is called when a label is defined. */
4514
4515void
31302357 4516m68k_frob_label (symbolS *sym)
252b5132
RH		 4517{
4518 struct label_line *n;
4519
4520 n = (struct label_line *) xmalloc (sizeof *n);
4521 n->next = labels;
4522 n->label = sym;
4523 as_where (&n->file, &n->line);
4524 n->text = 0;
4525 labels = n;
4526 current_label = n;
07a53e5c
RH		 4527
4528#ifdef OBJ_ELF
4529 dwarf2_emit_label (sym);
4530#endif
252b5132
RH		 4531}
4532
4533/* This is called when a value that is not an instruction is emitted. */
4534
4535void
31302357 4536m68k_flush_pending_output (void)
252b5132
RH		 4537{
4538 current_label = NULL;
4539}
4540
4541/* This is called at the end of the assembly, when the final value of
4542 the label is known. We warn if this is a text symbol aligned at an
4543 odd location. */
4544
4545void
31302357 4546m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4547{
4548 if (S_GET_SEGMENT (sym) == reg_section
4549 && (int) S_GET_VALUE (sym) < 0)
4550 {
4551 S_SET_SEGMENT (sym, absolute_section);
4552 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4553 }
4554 else if ((S_GET_VALUE (sym) & 1) != 0)
4555 {
4556 struct label_line *l;
4557
4558 for (l = labels; l != NULL; l = l->next)
4559 {
4560 if (l->label == sym)
4561 {
4562 if (l->text)
4563 as_warn_where (l->file, l->line,
4564 _("text label `%s' aligned to odd boundary"),
4565 S_GET_NAME (sym));
4566 break;
4567 }
4568 }
4569 }
4570}
4571\f
4572/* This is called if we go in or out of MRI mode because of the .mri
4573 pseudo-op. */
4574
4575void
31302357 4576m68k_mri_mode_change (int on)
252b5132
RH		 4577{
4578 if (on)
4579 {
4580 if (! flag_reg_prefix_optional)
4581 {
4582 flag_reg_prefix_optional = 1;
4583#ifdef REGISTER_PREFIX
4584 init_regtable ();
4585#endif
4586 }
4587 m68k_abspcadd = 1;
4588 if (! m68k_rel32_from_cmdline)
4589 m68k_rel32 = 0;
4590 }
4591 else
4592 {
4593 if (! reg_prefix_optional_seen)
4594 {
4595#ifdef REGISTER_PREFIX_OPTIONAL
4596 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4597#else
4598 flag_reg_prefix_optional = 0;
4599#endif
4600#ifdef REGISTER_PREFIX
4601 init_regtable ();
4602#endif
4603 }
4604 m68k_abspcadd = 0;
4605 if (! m68k_rel32_from_cmdline)
4606 m68k_rel32 = 1;
4607 }
4608}
4609
36759679 4610/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4611#define MAX_LITTLENUMS 6
4612
4613/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4614 of type TYPE, and store the appropriate bytes in *LITP. The number
4615 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4616 returned, or NULL on OK. */
4617
4618char *
31302357 4619md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4620{
4621 int prec;
4622 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4623 LITTLENUM_TYPE *wordP;
4624 char *t;
4625
4626 switch (type)
4627 {
4628 case 'f':
4629 case 'F':
4630 case 's':
4631 case 'S':
4632 prec = 2;
4633 break;
4634
4635 case 'd':
4636 case 'D':
4637 case 'r':
4638 case 'R':
4639 prec = 4;
4640 break;
4641
4642 case 'x':
4643 case 'X':
4644 prec = 6;
4645 break;
4646
4647 case 'p':
4648 case 'P':
4649 prec = 6;
4650 break;
4651
4652 default:
4653 *sizeP = 0;
4654 return _("Bad call to MD_ATOF()");
4655 }
4656 t = atof_ieee (input_line_pointer, type, words);
4657 if (t)
4658 input_line_pointer = t;
4659
4660 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4661 for (wordP = words; prec--;)
4662 {
4663 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4664 litP += sizeof (LITTLENUM_TYPE);
4665 }
4666 return 0;
4667}
4668
4669void
31302357 4670md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4671{
4672 number_to_chars_bigendian (buf, val, n);
4673}
4674
94f592af 4675void
55cf6793 4676md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4677{
bbe8ef22 4678 offsetT val = *valP;
252b5132
RH		 4679 addressT upper_limit;
4680 offsetT lower_limit;
4681
4682 /* This is unnecessary but it convinces the native rs6000 compiler
4683 to generate the code we want. */
4684 char *buf = fixP->fx_frag->fr_literal;
4685 buf += fixP->fx_where;
36759679 4686 /* End ibm compiler workaround. */
252b5132 4687
bd17c2c3 4688 val = SEXT (val);
252b5132 4689
94f592af
NC		 4690 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4691 fixP->fx_done = 1;
4692
252b5132
RH		 4693#ifdef OBJ_ELF
4694 if (fixP->fx_addsy)
4695 {
4696 memset (buf, 0, fixP->fx_size);
36759679 4697 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4698
4699 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4700 && !S_IS_DEFINED (fixP->fx_addsy)
4701 && !S_IS_WEAK (fixP->fx_addsy))
4702 S_SET_WEAK (fixP->fx_addsy);
4703 return;
4704 }
22184a77 4705#elif defined(OBJ_AOUT)
1c3f20b4 4706 /* PR gas/3041 Do not fix frags referencing a weak symbol. */
22184a77
NC		 4707 if (fixP->fx_addsy && S_IS_WEAK (fixP->fx_addsy))
4708 {
4709 memset (buf, 0, fixP->fx_size);
1c3f20b4 4710 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
22184a77
NC		 4711 return;
4712 }
252b5132
RH		 4713#endif
4714
252b5132
RH		 4715 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4716 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4717 return;
252b5132
RH		 4718
4719 switch (fixP->fx_size)
4720 {
94f592af
NC		 4721 /* The cast to offsetT below are necessary to make code
4722 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4723 case 1:
4724 *buf++ = val;
4725 upper_limit = 0x7f;
4726 lower_limit = - (offsetT) 0x80;
4727 break;
4728 case 2:
4729 *buf++ = (val >> 8);
4730 *buf++ = val;
4731 upper_limit = 0x7fff;
4732 lower_limit = - (offsetT) 0x8000;
4733 break;
4734 case 4:
4735 *buf++ = (val >> 24);
4736 *buf++ = (val >> 16);
4737 *buf++ = (val >> 8);
4738 *buf++ = val;
4739 upper_limit = 0x7fffffff;
36759679 4740 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4741 break;
4742 default:
4743 BAD_CASE (fixP->fx_size);
4744 }
4745
4746 /* Fix up a negative reloc. */
4747 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4748 {
4749 fixP->fx_addsy = fixP->fx_subsy;
4750 fixP->fx_subsy = NULL;
4751 fixP->fx_tcbit = 1;
4752 }
4753
4754 /* For non-pc-relative values, it's conceivable we might get something
4755 like "0xff" for a byte field. So extend the upper part of the range
4756 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4757 so that we can do any range checking at all. */
4758 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4759 upper_limit = upper_limit * 2 + 1;
4760
4761 if ((addressT) val > upper_limit
4762 && (val > 0 || val < lower_limit))
2b878742
NS		 4763 as_bad_where (fixP->fx_file, fixP->fx_line,
4764 _("value %ld out of range"), (long)val);
252b5132
RH		 4765
4766 /* A one byte PC-relative reloc means a short branch. We can't use
4767 a short branch with a value of 0 or -1, because those indicate
4768 different opcodes (branches with longer offsets). fixup_segment
4769 in write.c may have clobbered fx_pcrel, so we need to examine the
4770 reloc type. */
4771 if ((fixP->fx_pcrel
7be1c489 4772 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4773 && fixP->fx_size == 1
4774 && (fixP->fx_addsy == NULL
4775 || S_IS_DEFINED (fixP->fx_addsy))
4776 && (val == 0 || val == -1))
2b878742
NS		 4777 as_bad_where (fixP->fx_file, fixP->fx_line,
4778 _("invalid byte branch offset"));
252b5132
RH		 4779}
4780
252b5132
RH		 4781/* *fragP has been relaxed to its final size, and now needs to have
4782 the bytes inside it modified to conform to the new size There is UGLY
4783 MAGIC here. ..
4784 */
4785static void
31302357 4786md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4787{
4788 long disp;
2b878742 4789 fixS *fixP = NULL;
252b5132
RH		 4790
4791 /* Address in object code of the displacement. */
4792 register int object_address = fragP->fr_fix + fragP->fr_address;
4793
4794 /* Address in gas core of the place to store the displacement. */
4795 /* This convinces the native rs6000 compiler to generate the code we
92774660 4796 want. */
252b5132
RH		 4797 register char *buffer_address = fragP->fr_literal;
4798 buffer_address += fragP->fr_fix;
36759679 4799 /* End ibm compiler workaround. */
252b5132
RH		 4800
4801 /* The displacement of the address, from current location. */
4802 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4803 disp = (disp + fragP->fr_offset) - object_address;
4804
252b5132
RH		 4805 switch (fragP->fr_subtype)
4806 {
151337e8
NC		 4807 case TAB (BRANCHBWL, BYTE):
4808 case TAB (BRABSJUNC, BYTE):
4809 case TAB (BRABSJCOND, BYTE):
4810 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4811 know (issbyte (disp));
4812 if (disp == 0)
b091f402
AM		 4813 as_bad_where (fragP->fr_file, fragP->fr_line,
4814 _("short branch with zero offset: use :w"));
151337e8 4815 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4816 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4817 fixP->fx_pcrel_adjust = -1;
252b5132 4818 break;
151337e8
NC		 4819 case TAB (BRANCHBWL, SHORT):
4820 case TAB (BRABSJUNC, SHORT):
4821 case TAB (BRABSJCOND, SHORT):
4822 case TAB (BRANCHBW, SHORT):
252b5132 4823 fragP->fr_opcode[1] = 0x00;
2b878742
NS		 4824 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4825 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4826 fragP->fr_fix += 2;
4827 break;
4828 case TAB (BRANCHBWL, LONG):
4829 fragP->fr_opcode[1] = (char) 0xFF;
2b878742
NS		 4830 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4831 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8 4832 fragP->fr_fix += 4;
252b5132 4833 break;
151337e8
NC		 4834 case TAB (BRABSJUNC, LONG):
4835 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4836 {
36759679 4837 if (flag_keep_pcrel)
2b878742
NS		 4838 as_bad_where (fragP->fr_file, fragP->fr_line,
4839 _("Conversion of PC relative BSR to absolute JSR"));
151337e8 4840 fragP->fr_opcode[0] = 0x4E;
36759679 4841 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
2b878742
NS		 4842 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4843 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4844 fragP->fr_fix += 4;
4845 }
4846 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4847 {
36759679 4848 if (flag_keep_pcrel)
2b878742
NS		 4849 as_bad_where (fragP->fr_file, fragP->fr_line,
4850 _("Conversion of PC relative branch to absolute jump"));
151337e8 4851 fragP->fr_opcode[0] = 0x4E;
36759679 4852 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
2b878742
NS		 4853 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4854 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 4855 fragP->fr_fix += 4;
252b5132
RH		 4856 }
4857 else
4858 {
151337e8
NC		 4859 /* This cannot happen, because jbsr and jbra are the only two
4860 unconditional branches. */
4861 abort ();
252b5132
RH		 4862 }
4863 break;
151337e8 4864 case TAB (BRABSJCOND, LONG):
36759679 4865 if (flag_keep_pcrel)
2b878742
NS		 4866 as_bad_where (fragP->fr_file, fragP->fr_line,
4867 _("Conversion of PC relative conditional branch to absolute jump"));
92774660 4868
36759679
NC		 4869 /* Only Bcc 68000 instructions can come here
4870 Change bcc into b!cc/jmp absl long. */
4871 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4872 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4873
4874 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4875 different frag, in which case referring to them is a no-no.
92774660 4876 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4877 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4878 *buffer_address++ = (char) 0xf9;
36759679 4879 fragP->fr_fix += 2; /* Account for jmp instruction. */
2b878742
NS		 4880 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4881 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4882 fragP->fr_fix += 4;
4883 break;
4884 case TAB (FBRANCH, SHORT):
4885 know ((fragP->fr_opcode[1] & 0x40) == 0);
2b878742
NS		 4886 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4887 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4888 fragP->fr_fix += 2;
4889 break;
4890 case TAB (FBRANCH, LONG):
36759679 4891 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
2b878742
NS		 4892 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4893 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 4894 fragP->fr_fix += 4;
252b5132 4895 break;
151337e8
NC		 4896 case TAB (DBCCLBR, SHORT):
4897 case TAB (DBCCABSJ, SHORT):
2b878742
NS		 4898 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4899 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4900 fragP->fr_fix += 2;
4901 break;
4902 case TAB (DBCCLBR, LONG):
36759679
NC		 4903 /* Only DBcc instructions can come here.
4904 Change dbcc into dbcc/bral.
4905 JF: these used to be fr_opcode[2-7], but that's wrong. */
4906 if (flag_keep_pcrel)
2b878742
NS		 4907 as_bad_where (fragP->fr_file, fragP->fr_line,
4908 _("Conversion of DBcc to absolute jump"));
28e7409f 4909
36759679 4910 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4911 *buffer_address++ = 0x04;
36759679 4912 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4913 *buffer_address++ = 0x06;
151337e8
NC		 4914 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4915 *buffer_address++ = (char) 0xff;
252b5132 4916
36759679 4917 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 4918 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4919 fragP->fr_offset, 1, RELAX_RELOC_PC32);
252b5132 4920 fragP->fr_fix += 4;
252b5132 4921 break;
151337e8 4922 case TAB (DBCCABSJ, LONG):
36759679
NC		 4923 /* Only DBcc instructions can come here.
4924 Change dbcc into dbcc/jmp.
4925 JF: these used to be fr_opcode[2-7], but that's wrong. */
4926 if (flag_keep_pcrel)
2b878742
NS		 4927 as_bad_where (fragP->fr_file, fragP->fr_line,
4928 _("Conversion of PC relative conditional branch to absolute jump"));
151337e8 4929
36759679 4930 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4931 *buffer_address++ = 0x04;
36759679 4932 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4933 *buffer_address++ = 0x06;
36759679 4934 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4935 *buffer_address++ = (char) 0xf9;
4936
36759679 4937 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
2b878742
NS		 4938 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
4939 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
252b5132 4940 fragP->fr_fix += 4;
252b5132 4941 break;
151337e8 4942 case TAB (PCREL1632, SHORT):
252b5132
RH		 4943 fragP->fr_opcode[1] &= ~0x3F;
4944 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
2b878742
NS		 4945 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
4946 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4947 fragP->fr_fix += 2;
252b5132 4948 break;
151337e8 4949 case TAB (PCREL1632, LONG):
252b5132
RH		 4950 /* Already set to mode 7.3; this indicates: PC indirect with
4951 suppressed index, 32-bit displacement. */
4952 *buffer_address++ = 0x01;
4953 *buffer_address++ = 0x70;
4954 fragP->fr_fix += 2;
151337e8 4955 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4956 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4957 fixP->fx_pcrel_adjust = 2;
4958 fragP->fr_fix += 4;
252b5132 4959 break;
252b5132 4960 case TAB (PCINDEX, BYTE):
252b5132
RH		 4961 assert (fragP->fr_fix >= 2);
4962 buffer_address[-2] &= ~1;
151337e8 4963 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4964 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4965 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4966 break;
4967 case TAB (PCINDEX, SHORT):
252b5132
RH		 4968 assert (fragP->fr_fix >= 2);
4969 buffer_address[-2] |= 0x1;
4970 buffer_address[-1] = 0x20;
4971 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4972 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4973 fixP->fx_pcrel_adjust = 2;
151337e8 4974 fragP->fr_fix += 2;
252b5132
RH		 4975 break;
4976 case TAB (PCINDEX, LONG):
252b5132
RH		 4977 assert (fragP->fr_fix >= 2);
4978 buffer_address[-2] |= 0x1;
4979 buffer_address[-1] = 0x30;
151337e8 4980 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4981 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4982 fixP->fx_pcrel_adjust = 2;
4983 fragP->fr_fix += 4;
4984 break;
4985 case TAB (ABSTOPCREL, SHORT):
2b878742
NS		 4986 fixP = fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol,
4987 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8
NC		 4988 fragP->fr_fix += 2;
4989 break;
4990 case TAB (ABSTOPCREL, LONG):
36759679 4991 if (flag_keep_pcrel)
2b878742 4992 as_fatal (_("Conversion of PC relative displacement to absolute"));
151337e8 4993 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4994 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4995 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4996 abort ();
4997 fragP->fr_opcode[1] &= ~0x3F;
4998 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
2b878742
NS		 4999 fixP = fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5000 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8 5001 fragP->fr_fix += 4;
252b5132 5002 break;
252b5132 5003 }
2b878742
NS		 5004 if (fixP)
5005 {
5006 fixP->fx_file = fragP->fr_file;
5007 fixP->fx_line = fragP->fr_line;
5008 }
252b5132
RH		 5009}
5010
252b5132 5011void
31302357
AS		 5012md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
5013 segT sec ATTRIBUTE_UNUSED,
5014 fragS *fragP)
252b5132
RH		 5015{
5016 md_convert_frag_1 (fragP);
5017}
252b5132
RH		 5018
5019/* Force truly undefined symbols to their maximum size, and generally set up
5020 the frag list to be relaxed
5021 */
5022int
31302357 5023md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 5024{
151337e8 5025 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 5026 switch (fragP->fr_subtype)
5027 {
151337e8
NC		 5028 case TAB (BRANCHBWL, SZ_UNDEF):
5029 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 5030 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 5031 {
151337e8
NC		 5032 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5033 && relaxable_symbol (fragP->fr_symbol))
252b5132 5034 {
151337e8
NC		 5035 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
5036 }
5037 else if (flag_short_refs)
5038 {
5039 /* Symbol is undefined and we want short ref. */
5040 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5041 }
5042 else
5043 {
151337e8
NC		 5044 /* Symbol is still undefined. Make it LONG. */
5045 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5046 }
5047 break;
151337e8 5048 }
252b5132 5049
151337e8 5050 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 5051 {
151337e8
NC		 5052 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
5053 && relaxable_symbol (fragP->fr_symbol))
252b5132 5054 {
151337e8 5055 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 5056 }
5057 else
5058 {
151337e8
NC		 5059 /* Symbol is undefined and we don't have long branches. */
5060 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5061 }
5062 break;
151337e8 5063 }
252b5132 5064
151337e8 5065 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 5066 case TAB (DBCCLBR, SZ_UNDEF):
5067 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 5068 case TAB (PCREL1632, SZ_UNDEF):
252b5132 5069 {
8ec6253e
NC		 5070 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5071 && relaxable_symbol (fragP->fr_symbol))
151337e8 5072 || flag_short_refs)
252b5132 5073 {
151337e8 5074 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5075 }
5076 else
5077 {
151337e8 5078 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 5079 }
5080 break;
151337e8 5081 }
81d4177b 5082
252b5132
RH		 5083 case TAB (PCINDEX, SZ_UNDEF):
5084 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 5085 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 5086 {
5087 fragP->fr_subtype = TAB (PCINDEX, BYTE);
5088 }
5089 else
5090 {
5091 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 5092 }
5093 break;
5094
151337e8
NC		 5095 case TAB (ABSTOPCREL, SZ_UNDEF):
5096 {
5097 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
5098 && relaxable_symbol (fragP->fr_symbol)))
5099 {
5100 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 5101 }
5102 else
5103 {
5104 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 5105 }
5106 break;
5107 }
5108
252b5132
RH		 5109 default:
5110 break;
5111 }
5112
151337e8 5113 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 5114 switch (fragP->fr_subtype)
5115 {
151337e8
NC		 5116 case TAB (BRANCHBWL, BYTE):
5117 case TAB (BRABSJUNC, BYTE):
5118 case TAB (BRABSJCOND, BYTE):
5119 case TAB (BRANCHBW, BYTE):
252b5132 5120 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 5121 case we force word mode. If the symbol is at the start of a
5122 frag, and it is the next frag with any data in it (usually
5123 this is just the next frag, but assembler listings may
5124 introduce empty frags), we must use word mode. */
5125 if (fragP->fr_symbol)
252b5132 5126 {
ac62c346 5127 fragS *sym_frag;
252b5132 5128
ac62c346
AM		 5129 sym_frag = symbol_get_frag (fragP->fr_symbol);
5130 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 5131 {
ac62c346
AM		 5132 fragS *l;
5133
23b7f870 5134 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 5135 if (l->fr_fix != 0)
5136 break;
5137 if (l == sym_frag)
5138 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 5139 }
5140 }
5141 break;
5142 default:
5143 break;
5144 }
ac62c346 5145 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 5146}
5147
5148#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
5149/* the bit-field entries in the relocation_info struct plays hell
5150 with the byte-order problems of cross-assembly. So as a hack,
5151 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 5152 you there. -KWK */
252b5132
RH		 5153/* on m68k: first 4 bytes are normal unsigned long, next three bytes
5154 are symbolnum, most sig. byte first. Last byte is broken up with
5155 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
5156 nibble as nuthin. (on Sun 3 at least) */
5157/* Translate the internal relocation information into target-specific
92774660 5158 format. */
252b5132
RH		 5159#ifdef comment
5160void
31302357 5161md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 5162{
36759679 5163 /* This is easy. */
252b5132 5164 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 5165 /* Now the fun stuff. */
252b5132 5166 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 5167 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
5168 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 5169 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
5170 | ((ri->r_length << 5) & 0x60)
5171 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 5172}
5173
36759679 5174#endif
252b5132 5175
252b5132
RH		 5176#endif /* OBJ_AOUT or OBJ_BOUT */
5177
5178#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5179int md_short_jump_size = 4;
5180int md_long_jump_size = 6;
252b5132
RH		 5181
5182void
31302357
AS		 5183md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5184 fragS *frag ATTRIBUTE_UNUSED,
5185 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5186{
5187 valueT offset;
5188
5189 offset = to_addr - (from_addr + 2);
5190
5191 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5192 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5193}
5194
5195void
31302357
AS		 5196md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5197 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5198{
5199 valueT offset;
5200
6b6e92f4 5201 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5202 {
36759679 5203 if (flag_keep_pcrel)
6b6e92f4 5204 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5205 offset = to_addr - S_GET_VALUE (to_symbol);
5206 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5207 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5208 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5209 0, NO_RELOC);
5210 }
5211 else
5212 {
5213 offset = to_addr - (from_addr + 2);
5214 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5215 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5216 }
5217}
5218
5219#endif
5220
5221/* Different values of OK tell what its OK to return. Things that
5222 aren't OK are an error (what a shock, no?)
5223
5224 0: Everything is OK
3e602632
NC		 5225 10: Absolute 1:8 only
5226 20: Absolute 0:7 only
5227 30: absolute 0:15 only
5228 40: Absolute 0:31 only
5229 50: absolute 0:127 only
252b5132 5230 55: absolute -64:63 only
3e602632
NC		 5231 60: absolute -128:127 only
5232 70: absolute 0:4095 only
5233 80: absolute -1, 1:7 only
5234 90: No bignums. */
252b5132
RH		 5235
5236static int
31302357 5237get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5238{
5239 if (exp->exp.X_op == O_absent)
5240 {
36759679 5241 /* Do the same thing the VAX asm does. */
252b5132
RH		 5242 op (exp) = O_constant;
5243 adds (exp) = 0;
5244 subs (exp) = 0;
5245 offs (exp) = 0;
5246 if (ok == 10)
5247 {
5248 as_warn (_("expression out of range: defaulting to 1"));
5249 offs (exp) = 1;
5250 }
5251 }
5252 else if (exp->exp.X_op == O_constant)
5253 {
5254 switch (ok)
5255 {
5256 case 10:
bd17c2c3 5257 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5258 {
5259 as_warn (_("expression out of range: defaulting to 1"));
5260 offs (exp) = 1;
5261 }
5262 break;
5263 case 20:
bd17c2c3 5264 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5265 goto outrange;
5266 break;
5267 case 30:
bd17c2c3 5268 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5269 goto outrange;
5270 break;
5271 case 40:
bd17c2c3 5272 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5273 goto outrange;
5274 break;
5275 case 50:
bd17c2c3 5276 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5277 goto outrange;
5278 break;
5279 case 55:
bd17c2c3 5280 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5281 goto outrange;
5282 break;
5283 case 60:
bd17c2c3 5284 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5285 goto outrange;
5286 break;
5287 case 70:
bd17c2c3 5288 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5289 {
5290 outrange:
5291 as_warn (_("expression out of range: defaulting to 0"));
5292 offs (exp) = 0;
5293 }
5294 break;
3e602632 5295 case 80:
bd17c2c3
AM		 5296 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5297 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5298 {
5299 as_warn (_("expression out of range: defaulting to 1"));
5300 offs (exp) = 1;
5301 }
5302 break;
252b5132
RH		 5303 default:
5304 break;
5305 }
5306 }
5307 else if (exp->exp.X_op == O_big)
5308 {
36759679 5309 if (offs (exp) <= 0 /* flonum. */
3e602632 5310 && (ok == 90 /* no bignums */
36759679 5311 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5312 /* If we have a flonum zero, a zero integer should
5313 do as well (e.g., in moveq). */
5314 && generic_floating_point_number.exponent == 0
5315 && generic_floating_point_number.low[0] == 0)))
5316 {
36759679 5317 /* HACK! Turn it into a long. */
252b5132
RH		 5318 LITTLENUM_TYPE words[6];
5319
36759679 5320 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5321 op (exp) = O_constant;
5322 adds (exp) = 0;
5323 subs (exp) = 0;
5324 offs (exp) = words[1] | (words[0] << 16);
5325 }
5326 else if (ok != 0)
5327 {
5328 op (exp) = O_constant;
5329 adds (exp) = 0;
5330 subs (exp) = 0;
5331 offs (exp) = (ok == 10) ? 1 : 0;
5332 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5333 (long) offs (exp));
252b5132
RH		 5334 }
5335 }
5336 else
5337 {
3e602632 5338 if (ok >= 10 && ok <= 80)
252b5132
RH		 5339 {
5340 op (exp) = O_constant;
5341 adds (exp) = 0;
5342 subs (exp) = 0;
5343 offs (exp) = (ok == 10) ? 1 : 0;
5344 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5345 (long) offs (exp));
252b5132
RH		 5346 }
5347 }
5348
5349 if (exp->size != SIZE_UNSPEC)
5350 {
5351 switch (exp->size)
5352 {
5353 case SIZE_UNSPEC:
5354 case SIZE_LONG:
5355 break;
5356 case SIZE_BYTE:
5357 if (!isbyte (offs (exp)))
5358 as_warn (_("expression doesn't fit in BYTE"));
5359 break;
5360 case SIZE_WORD:
5361 if (!isword (offs (exp)))
5362 as_warn (_("expression doesn't fit in WORD"));
5363 break;
5364 }
5365 }
5366
5367 return offs (exp);
5368}
5369
5370/* These are the back-ends for the various machine dependent pseudo-ops. */
5371
5372static void
31302357 5373s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5374{
5375 subseg_set (data_section, 1);
5376 demand_empty_rest_of_line ();
5377}
5378
5379static void
31302357 5380s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5381{
5382 subseg_set (data_section, 2);
5383 demand_empty_rest_of_line ();
5384}
5385
5386static void
31302357 5387s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5388{
5389 /* We don't support putting frags in the BSS segment, we fake it
5390 by marking in_bss, then looking at s_skip for clues. */
5391
5392 subseg_set (bss_section, 0);
5393 demand_empty_rest_of_line ();
5394}
5395
5396static void
31302357 5397s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5398{
5399 register int temp;
5400 register long temp_fill;
5401
5402 temp = 1; /* JF should be 2? */
5403 temp_fill = get_absolute_expression ();
92774660 5404 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5405 frag_align (temp, (int) temp_fill, 0);
5406 demand_empty_rest_of_line ();
5407 record_alignment (now_seg, temp);
5408}
5409
5410static void
31302357 5411s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5412{
5413 demand_empty_rest_of_line ();
5414}
5415\f
5416/* Pseudo-ops handled for MRI compatibility. */
5417
5418/* This function returns non-zero if the argument is a conditional
5419 pseudo-op. This is called when checking whether a pending
5420 alignment is needed. */
5421
5422int
31302357 5423m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5424{
5425 return (pop->poc_handler == s_mri_if
5426 || pop->poc_handler == s_mri_else);
5427}
5428
5429/* Handle an MRI style chip specification. */
5430
5431static void
31302357 5432mri_chip (void)
252b5132
RH		 5433{
5434 char *s;
5435 char c;
5436 int i;
5437
5438 s = input_line_pointer;
5439 /* We can't use get_symbol_end since the processor names are not proper
5440 symbols. */
5441 while (is_part_of_name (c = *input_line_pointer++))
5442 ;
5443 *--input_line_pointer = 0;
266abb8f
NS		 5444 for (i = 0; m68k_cpus[i].name; i++)
5445 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5446 break;
266abb8f 5447 if (!m68k_cpus[i].name)
252b5132
RH		 5448 {
5449 as_bad (_("%s: unrecognized processor name"), s);
5450 *input_line_pointer = c;
5451 ignore_rest_of_line ();
5452 return;
5453 }
5454 *input_line_pointer = c;
5455
5456 if (*input_line_pointer == '/')
5457 current_architecture = 0;
5458 else
5459 current_architecture &= m68881 | m68851;
266abb8f 5460 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5461 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5462
5463 while (*input_line_pointer == '/')
5464 {
5465 ++input_line_pointer;
5466 s = input_line_pointer;
5467 /* We can't use get_symbol_end since the processor names are not
5468 proper symbols. */
5469 while (is_part_of_name (c = *input_line_pointer++))
5470 ;
5471 *--input_line_pointer = 0;
5472 if (strcmp (s, "68881") == 0)
5473 current_architecture |= m68881;
5474 else if (strcmp (s, "68851") == 0)
5475 current_architecture |= m68851;
5476 *input_line_pointer = c;
5477 }
252b5132
RH		 5478}
5479
5480/* The MRI CHIP pseudo-op. */
5481
5482static void
31302357 5483s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5484{
5485 char *stop = NULL;
5486 char stopc;
5487
5488 if (flag_mri)
5489 stop = mri_comment_field (&stopc);
5490 mri_chip ();
5491 if (flag_mri)
5492 mri_comment_end (stop, stopc);
5493 demand_empty_rest_of_line ();
5494}
5495
5496/* The MRI FOPT pseudo-op. */
5497
5498static void
31302357 5499s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5500{
5501 SKIP_WHITESPACE ();
5502
5503 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5504 {
5505 int temp;
5506
5507 input_line_pointer += 3;
5508 temp = get_absolute_expression ();
5509 if (temp < 0 || temp > 7)
5510 as_bad (_("bad coprocessor id"));
5511 else
5512 m68k_float_copnum = COP0 + temp;
5513 }
5514 else
5515 {
5516 as_bad (_("unrecognized fopt option"));
5517 ignore_rest_of_line ();
5518 return;
5519 }
5520
5521 demand_empty_rest_of_line ();
5522}
5523
5524/* The structure used to handle the MRI OPT pseudo-op. */
5525
5526struct opt_action
5527{
5528 /* The name of the option. */
5529 const char *name;
5530
5531 /* If this is not NULL, just call this function. The first argument
5532 is the ARG field of this structure, the second argument is
5533 whether the option was negated. */
31302357 5534 void (*pfn) (int arg, int on);
252b5132
RH		 5535
5536 /* If this is not NULL, and the PFN field is NULL, set the variable
5537 this points to. Set it to the ARG field if the option was not
5538 negated, and the NOTARG field otherwise. */
5539 int *pvar;
5540
5541 /* The value to pass to PFN or to assign to *PVAR. */
5542 int arg;
5543
5544 /* The value to assign to *PVAR if the option is negated. If PFN is
5545 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5546 the option may not be negated. */
5547 int notarg;
5548};
5549
5550/* The table used to handle the MRI OPT pseudo-op. */
5551
31302357
AS		 5552static void skip_to_comma (int, int);
5553static void opt_nest (int, int);
5554static void opt_chip (int, int);
5555static void opt_list (int, int);
5556static void opt_list_symbols (int, int);
252b5132
RH		 5557
5558static const struct opt_action opt_table[] =
5559{
5560 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5561
5562 /* We do relaxing, so there is little use for these options. */
5563 { "b", 0, 0, 0, 0 },
5564 { "brs", 0, 0, 0, 0 },
5565 { "brb", 0, 0, 0, 0 },
5566 { "brl", 0, 0, 0, 0 },
5567 { "brw", 0, 0, 0, 0 },
5568
5569 { "c", 0, 0, 0, 0 },
5570 { "cex", 0, 0, 0, 0 },
5571 { "case", 0, &symbols_case_sensitive, 1, 0 },
5572 { "cl", 0, 0, 0, 0 },
5573 { "cre", 0, 0, 0, 0 },
5574 { "d", 0, &flag_keep_locals, 1, 0 },
5575 { "e", 0, 0, 0, 0 },
5576 { "f", 0, &flag_short_refs, 1, 0 },
5577 { "frs", 0, &flag_short_refs, 1, 0 },
5578 { "frl", 0, &flag_short_refs, 0, 1 },
5579 { "g", 0, 0, 0, 0 },
5580 { "i", 0, 0, 0, 0 },
5581 { "m", 0, 0, 0, 0 },
5582 { "mex", 0, 0, 0, 0 },
5583 { "mc", 0, 0, 0, 0 },
5584 { "md", 0, 0, 0, 0 },
5585 { "nest", opt_nest, 0, 0, 0 },
5586 { "next", skip_to_comma, 0, 0, 0 },
5587 { "o", 0, 0, 0, 0 },
5588 { "old", 0, 0, 0, 0 },
5589 { "op", skip_to_comma, 0, 0, 0 },
5590 { "pco", 0, 0, 0, 0 },
5591 { "p", opt_chip, 0, 0, 0 },
5592 { "pcr", 0, 0, 0, 0 },
5593 { "pcs", 0, 0, 0, 0 },
5594 { "r", 0, 0, 0, 0 },
5595 { "quick", 0, &m68k_quick, 1, 0 },
5596 { "rel32", 0, &m68k_rel32, 1, 0 },
5597 { "s", opt_list, 0, 0, 0 },
5598 { "t", opt_list_symbols, 0, 0, 0 },
5599 { "w", 0, &flag_no_warnings, 0, 1 },
5600 { "x", 0, 0, 0, 0 }
5601};
5602
8fce3f5e 5603#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5604
5605/* The MRI OPT pseudo-op. */
5606
5607static void
31302357 5608s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5609{
5610 do
5611 {
5612 int t;
5613 char *s;
5614 char c;
5615 int i;
5616 const struct opt_action *o;
5617
5618 SKIP_WHITESPACE ();
5619
5620 t = 1;
5621 if (*input_line_pointer == '-')
5622 {
5623 ++input_line_pointer;
5624 t = 0;
5625 }
5626 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5627 {
5628 input_line_pointer += 2;
5629 t = 0;
5630 }
5631
5632 s = input_line_pointer;
5633 c = get_symbol_end ();
5634
5635 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5636 {
5637 if (strcasecmp (s, o->name) == 0)
5638 {
5639 if (o->pfn)
5640 {
5641 /* Restore input_line_pointer now in case the option
5642 takes arguments. */
5643 *input_line_pointer = c;
5644 (*o->pfn) (o->arg, t);
5645 }
5646 else if (o->pvar != NULL)
5647 {
5648 if (! t && o->arg == o->notarg)
5649 as_bad (_("option `%s' may not be negated"), s);
5650 *input_line_pointer = c;
5651 *o->pvar = t ? o->arg : o->notarg;
5652 }
5653 else
5654 *input_line_pointer = c;
5655 break;
5656 }
5657 }
5658 if (i >= OPTCOUNT)
5659 {
5660 as_bad (_("option `%s' not recognized"), s);
5661 *input_line_pointer = c;
5662 }
5663 }
5664 while (*input_line_pointer++ == ',');
5665
5666 /* Move back to terminating character. */
5667 --input_line_pointer;
5668 demand_empty_rest_of_line ();
5669}
5670
5671/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5672 not support and which take arguments. */
252b5132
RH		 5673
5674static void
31302357 5675skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5676{
5677 while (*input_line_pointer != ','
5678 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5679 ++input_line_pointer;
5680}
5681
5682/* Handle the OPT NEST=depth option. */
5683
5684static void
31302357 5685opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5686{
5687 if (*input_line_pointer != '=')
5688 {
5689 as_bad (_("bad format of OPT NEST=depth"));
5690 return;
5691 }
5692
5693 ++input_line_pointer;
5694 max_macro_nest = get_absolute_expression ();
5695}
5696
5697/* Handle the OPT P=chip option. */
5698
5699static void
31302357 5700opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5701{
5702 if (*input_line_pointer != '=')
5703 {
5704 /* This is just OPT P, which we do not support. */
5705 return;
5706 }
5707
5708 ++input_line_pointer;
5709 mri_chip ();
5710}
5711
5712/* Handle the OPT S option. */
5713
5714static void
31302357 5715opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5716{
5717 listing_list (on);
5718}
5719
5720/* Handle the OPT T option. */
5721
5722static void
31302357 5723opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5724{
5725 if (on)
5726 listing |= LISTING_SYMBOLS;
5727 else
8a104df9 5728 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5729}
5730
5731/* Handle the MRI REG pseudo-op. */
5732
5733static void
31302357 5734s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5735{
5736 char *s;
5737 int c;
5738 struct m68k_op rop;
5739 int mask;
5740 char *stop = NULL;
5741 char stopc;
5742
5743 if (line_label == NULL)
5744 {
5745 as_bad (_("missing label"));
5746 ignore_rest_of_line ();
5747 return;
5748 }
5749
5750 if (flag_mri)
5751 stop = mri_comment_field (&stopc);
5752
5753 SKIP_WHITESPACE ();
5754
5755 s = input_line_pointer;
3882b010 5756 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5757#ifdef REGISTER_PREFIX
5758 || *input_line_pointer == REGISTER_PREFIX
5759#endif
5760 || *input_line_pointer == '/'
5761 || *input_line_pointer == '-')
5762 ++input_line_pointer;
5763 c = *input_line_pointer;
5764 *input_line_pointer = '\0';
5765
5766 if (m68k_ip_op (s, &rop) != 0)
5767 {
5768 if (rop.error == NULL)
5769 as_bad (_("bad register list"));
5770 else
5771 as_bad (_("bad register list: %s"), rop.error);
5772 *input_line_pointer = c;
5773 ignore_rest_of_line ();
5774 return;
5775 }
5776
5777 *input_line_pointer = c;
5778
5779 if (rop.mode == REGLST)
5780 mask = rop.mask;
5781 else if (rop.mode == DREG)
5782 mask = 1 << (rop.reg - DATA0);
5783 else if (rop.mode == AREG)
5784 mask = 1 << (rop.reg - ADDR0 + 8);
5785 else if (rop.mode == FPREG)
5786 mask = 1 << (rop.reg - FP0 + 16);
5787 else if (rop.mode == CONTROL
5788 && rop.reg == FPI)
5789 mask = 1 << 24;
5790 else if (rop.mode == CONTROL
5791 && rop.reg == FPS)
5792 mask = 1 << 25;
5793 else if (rop.mode == CONTROL
5794 && rop.reg == FPC)
5795 mask = 1 << 26;
5796 else
5797 {
5798 as_bad (_("bad register list"));
5799 ignore_rest_of_line ();
5800 return;
5801 }
5802
5803 S_SET_SEGMENT (line_label, reg_section);
5804 S_SET_VALUE (line_label, ~mask);
49309057 5805 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5806
5807 if (flag_mri)
5808 mri_comment_end (stop, stopc);
5809
5810 demand_empty_rest_of_line ();
5811}
5812
5813/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5814
5815struct save_opts
5816{
5817 struct save_opts *next;
5818 int abspcadd;
5819 int symbols_case_sensitive;
5820 int keep_locals;
5821 int short_refs;
5822 int architecture;
2da12c60 5823 const enum m68k_register *control_regs;
252b5132
RH		 5824 int quick;
5825 int rel32;
5826 int listing;
5827 int no_warnings;
5828 /* FIXME: We don't save OPT S. */
5829};
5830
5831/* This variable holds the stack of saved options. */
5832
5833static struct save_opts *save_stack;
5834
5835/* The MRI SAVE pseudo-op. */
5836
5837static void
31302357 5838s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5839{
5840 struct save_opts *s;
5841
5842 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5843 s->abspcadd = m68k_abspcadd;
5844 s->symbols_case_sensitive = symbols_case_sensitive;
5845 s->keep_locals = flag_keep_locals;
5846 s->short_refs = flag_short_refs;
5847 s->architecture = current_architecture;
2da12c60 5848 s->control_regs = control_regs;
252b5132
RH		 5849 s->quick = m68k_quick;
5850 s->rel32 = m68k_rel32;
5851 s->listing = listing;
5852 s->no_warnings = flag_no_warnings;
5853
5854 s->next = save_stack;
5855 save_stack = s;
5856
5857 demand_empty_rest_of_line ();
5858}
5859
5860/* The MRI RESTORE pseudo-op. */
5861
5862static void
31302357 5863s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5864{
5865 struct save_opts *s;
5866
5867 if (save_stack == NULL)
5868 {
5869 as_bad (_("restore without save"));
5870 ignore_rest_of_line ();
5871 return;
5872 }
5873
5874 s = save_stack;
5875 save_stack = s->next;
5876
5877 m68k_abspcadd = s->abspcadd;
5878 symbols_case_sensitive = s->symbols_case_sensitive;
5879 flag_keep_locals = s->keep_locals;
5880 flag_short_refs = s->short_refs;
5881 current_architecture = s->architecture;
2da12c60 5882 control_regs = s->control_regs;
252b5132
RH		 5883 m68k_quick = s->quick;
5884 m68k_rel32 = s->rel32;
5885 listing = s->listing;
5886 flag_no_warnings = s->no_warnings;
5887
5888 free (s);
5889
5890 demand_empty_rest_of_line ();
5891}
5892
5893/* Types of MRI structured control directives. */
5894
5895enum mri_control_type
5896{
5897 mri_for,
5898 mri_if,
5899 mri_repeat,
5900 mri_while
5901};
5902
5903/* This structure is used to stack the MRI structured control
5904 directives. */
5905
5906struct mri_control_info
5907{
5908 /* The directive within which this one is enclosed. */
5909 struct mri_control_info *outer;
5910
5911 /* The type of directive. */
5912 enum mri_control_type type;
5913
5914 /* Whether an ELSE has been in an IF. */
5915 int else_seen;
5916
5917 /* The add or sub statement at the end of a FOR. */
5918 char *incr;
5919
5920 /* The label of the top of a FOR or REPEAT loop. */
5921 char *top;
5922
5923 /* The label to jump to for the next iteration, or the else
5924 expression of a conditional. */
5925 char *next;
5926
5927 /* The label to jump to to break out of the loop, or the label past
5928 the end of a conditional. */
5929 char *bottom;
5930};
5931
5932/* The stack of MRI structured control directives. */
5933
5934static struct mri_control_info *mri_control_stack;
5935
5936/* The current MRI structured control directive index number, used to
5937 generate label names. */
5938
5939static int mri_control_index;
5940
252b5132
RH		 5941/* Assemble an instruction for an MRI structured control directive. */
5942
5943static void
31302357 5944mri_assemble (char *str)
252b5132
RH		 5945{
5946 char *s;
5947
5948 /* md_assemble expects the opcode to be in lower case. */
5949 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5950 *s = TOLOWER (*s);
252b5132
RH		 5951
5952 md_assemble (str);
5953}
5954
5955/* Generate a new MRI label structured control directive label name. */
5956
5957static char *
31302357 5958mri_control_label (void)
252b5132
RH		 5959{
5960 char *n;
5961
5962 n = (char *) xmalloc (20);
5963 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5964 ++mri_control_index;
5965 return n;
5966}
5967
5968/* Create a new MRI structured control directive. */
5969
5970static struct mri_control_info *
31302357 5971push_mri_control (enum mri_control_type type)
252b5132
RH		 5972{
5973 struct mri_control_info *n;
5974
5975 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5976
5977 n->type = type;
5978 n->else_seen = 0;
5979 if (type == mri_if || type == mri_while)
5980 n->top = NULL;
5981 else
5982 n->top = mri_control_label ();
5983 n->next = mri_control_label ();
5984 n->bottom = mri_control_label ();
5985
5986 n->outer = mri_control_stack;
5987 mri_control_stack = n;
5988
5989 return n;
5990}
5991
5992/* Pop off the stack of MRI structured control directives. */
5993
5994static void
31302357 5995pop_mri_control (void)
252b5132
RH		 5996{
5997 struct mri_control_info *n;
5998
5999 n = mri_control_stack;
6000 mri_control_stack = n->outer;
6001 if (n->top != NULL)
6002 free (n->top);
6003 free (n->next);
6004 free (n->bottom);
6005 free (n);
6006}
6007
6008/* Recognize a condition code in an MRI structured control expression. */
6009
6010static int
31302357 6011parse_mri_condition (int *pcc)
252b5132
RH		 6012{
6013 char c1, c2;
6014
6015 know (*input_line_pointer == '<');
6016
6017 ++input_line_pointer;
6018 c1 = *input_line_pointer++;
6019 c2 = *input_line_pointer++;
6020
6021 if (*input_line_pointer != '>')
6022 {
6023 as_bad (_("syntax error in structured control directive"));
6024 return 0;
6025 }
6026
6027 ++input_line_pointer;
6028 SKIP_WHITESPACE ();
6029
3882b010
L		 6030 c1 = TOLOWER (c1);
6031 c2 = TOLOWER (c2);
252b5132
RH		 6032
6033 *pcc = (c1 << 8) | c2;
6034
6035 return 1;
6036}
6037
6038/* Parse a single operand in an MRI structured control expression. */
6039
6040static int
31302357
AS		 6041parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
6042 char **rightstart, char **rightstop)
252b5132
RH		 6043{
6044 char *s;
6045
6046 SKIP_WHITESPACE ();
6047
6048 *pcc = -1;
6049 *leftstart = NULL;
6050 *leftstop = NULL;
6051 *rightstart = NULL;
6052 *rightstop = NULL;
6053
6054 if (*input_line_pointer == '<')
6055 {
6056 /* It's just a condition code. */
6057 return parse_mri_condition (pcc);
6058 }
6059
6060 /* Look ahead for the condition code. */
6061 for (s = input_line_pointer; *s != '\0'; ++s)
6062 {
6063 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
6064 break;
6065 }
6066 if (*s == '\0')
6067 {
6068 as_bad (_("missing condition code in structured control directive"));
6069 return 0;
6070 }
6071
6072 *leftstart = input_line_pointer;
6073 *leftstop = s;
6074 if (*leftstop > *leftstart
6075 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
6076 --*leftstop;
6077
6078 input_line_pointer = s;
6079 if (! parse_mri_condition (pcc))
6080 return 0;
6081
6082 /* Look ahead for AND or OR or end of line. */
6083 for (s = input_line_pointer; *s != '\0'; ++s)
6084 {
e1f44d10
NC		 6085 /* We must make sure we don't misinterpret AND/OR at the end of labels!
6086 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
6087 ^^^ ^^ */
8a104df9
KH		 6088 if ((s == input_line_pointer
6089 || *(s-1) == ' '
6090 || *(s-1) == '\t')
6091 && ((strncasecmp (s, "AND", 3) == 0
6092 && (s[3] == '.' || ! is_part_of_name (s[3])))
6093 || (strncasecmp (s, "OR", 2) == 0
6094 && (s[2] == '.' || ! is_part_of_name (s[2])))))
6095 break;
252b5132
RH		 6096 }
6097
6098 *rightstart = input_line_pointer;
6099 *rightstop = s;
6100 if (*rightstop > *rightstart
6101 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
6102 --*rightstop;
6103
6104 input_line_pointer = s;
6105
6106 return 1;
6107}
6108
6109#define MCC(b1, b2) (((b1) << 8) | (b2))
6110
6111/* Swap the sense of a condition. This changes the condition so that
6112 it generates the same result when the operands are swapped. */
6113
6114static int
31302357 6115swap_mri_condition (int cc)
252b5132
RH		 6116{
6117 switch (cc)
6118 {
6119 case MCC ('h', 'i'): return MCC ('c', 's');
6120 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 6121 /* <HS> is an alias for <CC>. */
e1f44d10 6122 case MCC ('h', 's'):
252b5132 6123 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 6124 /* <LO> is an alias for <CS>. */
e1f44d10 6125 case MCC ('l', 'o'):
252b5132
RH		 6126 case MCC ('c', 's'): return MCC ('h', 'i');
6127 case MCC ('p', 'l'): return MCC ('m', 'i');
6128 case MCC ('m', 'i'): return MCC ('p', 'l');
6129 case MCC ('g', 'e'): return MCC ('l', 'e');
6130 case MCC ('l', 't'): return MCC ('g', 't');
6131 case MCC ('g', 't'): return MCC ('l', 't');
6132 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 6133 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 6134 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
6135 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
6136 case MCC ('v', 'c'):
6137 case MCC ('v', 's'):
6138 default :
6139 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
6140 (char) (cc >> 8), (char) (cc));
6141 break;
252b5132
RH		 6142 }
6143 return cc;
6144}
6145
6146/* Reverse the sense of a condition. */
6147
6148static int
31302357 6149reverse_mri_condition (int cc)
252b5132
RH		 6150{
6151 switch (cc)
6152 {
6153 case MCC ('h', 'i'): return MCC ('l', 's');
6154 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 6155 /* <HS> is an alias for <CC> */
6156 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 6157 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 6158 /* <LO> is an alias for <CS> */
6159 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 6160 case MCC ('c', 's'): return MCC ('c', 'c');
6161 case MCC ('n', 'e'): return MCC ('e', 'q');
6162 case MCC ('e', 'q'): return MCC ('n', 'e');
6163 case MCC ('v', 'c'): return MCC ('v', 's');
6164 case MCC ('v', 's'): return MCC ('v', 'c');
6165 case MCC ('p', 'l'): return MCC ('m', 'i');
6166 case MCC ('m', 'i'): return MCC ('p', 'l');
6167 case MCC ('g', 'e'): return MCC ('l', 't');
6168 case MCC ('l', 't'): return MCC ('g', 'e');
6169 case MCC ('g', 't'): return MCC ('l', 'e');
6170 case MCC ('l', 'e'): return MCC ('g', 't');
6171 }
6172 return cc;
6173}
6174
6175/* Build an MRI structured control expression. This generates test
6176 and branch instructions. It goes to TRUELAB if the condition is
6177 true, and to FALSELAB if the condition is false. Exactly one of
6178 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6179 is the size qualifier for the expression. EXTENT is the size to
6180 use for the branch. */
6181
6182static void
31302357
AS		 6183build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6184 char *rightstart, char *rightstop,
6185 const char *truelab, const char *falselab,
6186 int extent)
252b5132
RH		 6187{
6188 char *buf;
6189 char *s;
6190
6191 if (leftstart != NULL)
6192 {
6193 struct m68k_op leftop, rightop;
6194 char c;
6195
6196 /* Swap the compare operands, if necessary, to produce a legal
6197 m68k compare instruction. Comparing a register operand with
6198 a non-register operand requires the register to be on the
6199 right (cmp, cmpa). Comparing an immediate value with
6200 anything requires the immediate value to be on the left
6201 (cmpi). */
6202
6203 c = *leftstop;
6204 *leftstop = '\0';
6205 (void) m68k_ip_op (leftstart, &leftop);
6206 *leftstop = c;
6207
6208 c = *rightstop;
6209 *rightstop = '\0';
6210 (void) m68k_ip_op (rightstart, &rightop);
6211 *rightstop = c;
6212
6213 if (rightop.mode == IMMED
6214 || ((leftop.mode == DREG || leftop.mode == AREG)
6215 && (rightop.mode != DREG && rightop.mode != AREG)))
6216 {
6217 char *temp;
6218
31302357
AS		 6219 /* Correct conditional handling:
6220 if #1 <lt> d0 then ;means if (1 < d0)
6221 ...
6222 endi
e1f44d10 6223
31302357 6224 should assemble to:
e1f44d10 6225
31302357
AS		 6226 cmp #1,d0 if we do *not* swap the operands
6227 bgt true we need the swapped condition!
6228 ble false
6229 true:
6230 ...
6231 false:
6232 */
252b5132
RH		 6233 temp = leftstart;
6234 leftstart = rightstart;
6235 rightstart = temp;
6236 temp = leftstop;
6237 leftstop = rightstop;
6238 rightstop = temp;
8a104df9
KH		 6239 }
6240 else
6241 {
e1f44d10 6242 cc = swap_mri_condition (cc);
252b5132
RH		 6243 }
6244 }
6245
6246 if (truelab == NULL)
6247 {
6248 cc = reverse_mri_condition (cc);
6249 truelab = falselab;
6250 }
92774660 6251
252b5132
RH		 6252 if (leftstart != NULL)
6253 {
6254 buf = (char *) xmalloc (20
6255 + (leftstop - leftstart)
6256 + (rightstop - rightstart));
6257 s = buf;
6258 *s++ = 'c';
6259 *s++ = 'm';
6260 *s++ = 'p';
6261 if (qual != '\0')
3882b010 6262 *s++ = TOLOWER (qual);
252b5132
RH		 6263 *s++ = ' ';
6264 memcpy (s, leftstart, leftstop - leftstart);
6265 s += leftstop - leftstart;
6266 *s++ = ',';
6267 memcpy (s, rightstart, rightstop - rightstart);
6268 s += rightstop - rightstart;
6269 *s = '\0';
6270 mri_assemble (buf);
6271 free (buf);
6272 }
92774660 6273
252b5132
RH		 6274 buf = (char *) xmalloc (20 + strlen (truelab));
6275 s = buf;
6276 *s++ = 'b';
6277 *s++ = cc >> 8;
6278 *s++ = cc & 0xff;
6279 if (extent != '\0')
3882b010 6280 *s++ = TOLOWER (extent);
252b5132
RH		 6281 *s++ = ' ';
6282 strcpy (s, truelab);
6283 mri_assemble (buf);
6284 free (buf);
6285}
6286
6287/* Parse an MRI structured control expression. This generates test
6288 and branch instructions. STOP is where the expression ends. It
6289 goes to TRUELAB if the condition is true, and to FALSELAB if the
6290 condition is false. Exactly one of TRUELAB and FALSELAB will be
6291 NULL, meaning to fall through. QUAL is the size qualifier for the
6292 expression. EXTENT is the size to use for the branch. */
6293
6294static void
31302357
AS		 6295parse_mri_control_expression (char *stop, int qual, const char *truelab,
6296 const char *falselab, int extent)
252b5132
RH		 6297{
6298 int c;
6299 int cc;
6300 char *leftstart;
6301 char *leftstop;
6302 char *rightstart;
6303 char *rightstop;
6304
6305 c = *stop;
6306 *stop = '\0';
6307
6308 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6309 &rightstart, &rightstop))
6310 {
6311 *stop = c;
6312 return;
6313 }
6314
6315 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6316 {
6317 const char *flab;
6318
6319 if (falselab != NULL)
6320 flab = falselab;
6321 else
6322 flab = mri_control_label ();
6323
6324 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6325 rightstop, (const char *) NULL, flab, extent);
6326
6327 input_line_pointer += 3;
6328 if (*input_line_pointer != '.'
6329 || input_line_pointer[1] == '\0')
6330 qual = '\0';
6331 else
6332 {
6333 qual = input_line_pointer[1];
6334 input_line_pointer += 2;
6335 }
6336
6337 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6338 &rightstart, &rightstop))
6339 {
6340 *stop = c;
6341 return;
6342 }
6343
6344 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6345 rightstop, truelab, falselab, extent);
6346
6347 if (falselab == NULL)
6348 colon (flab);
6349 }
6350 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6351 {
6352 const char *tlab;
6353
6354 if (truelab != NULL)
6355 tlab = truelab;
6356 else
6357 tlab = mri_control_label ();
6358
6359 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6360 rightstop, tlab, (const char *) NULL, extent);
6361
6362 input_line_pointer += 2;
6363 if (*input_line_pointer != '.'
6364 || input_line_pointer[1] == '\0')
6365 qual = '\0';
6366 else
6367 {
6368 qual = input_line_pointer[1];
6369 input_line_pointer += 2;
6370 }
6371
6372 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6373 &rightstart, &rightstop))
6374 {
6375 *stop = c;
6376 return;
6377 }
6378
6379 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6380 rightstop, truelab, falselab, extent);
6381
6382 if (truelab == NULL)
6383 colon (tlab);
6384 }
6385 else
6386 {
6387 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6388 rightstop, truelab, falselab, extent);
6389 }
6390
6391 *stop = c;
6392 if (input_line_pointer != stop)
6393 as_bad (_("syntax error in structured control directive"));
6394}
6395
6396/* Handle the MRI IF pseudo-op. This may be a structured control
6397 directive, or it may be a regular assembler conditional, depending
6398 on its operands. */
6399
6400static void
31302357 6401s_mri_if (int qual)
252b5132
RH		 6402{
6403 char *s;
6404 int c;
6405 struct mri_control_info *n;
6406
6407 /* A structured control directive must end with THEN with an
6408 optional qualifier. */
6409 s = input_line_pointer;
e1f44d10
NC		 6410 /* We only accept '*' as introduction of comments if preceded by white space
6411 or at first column of a line (I think this can't actually happen here?)
6412 This is important when assembling:
6413 if d0 <ne> 12(a0,d0*2) then
36759679 6414 if d0 <ne> #CONST*20 then. */
31302357
AS		 6415 while (! (is_end_of_line[(unsigned char) *s]
6416 || (flag_mri
6417 && *s == '*'
6418 && (s == input_line_pointer
6419 || *(s-1) == ' '
6420 || *(s-1) == '\t'))))
252b5132
RH		 6421 ++s;
6422 --s;
6423 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6424 --s;
6425
6426 if (s - input_line_pointer > 1
6427 && s[-1] == '.')
6428 s -= 2;
6429
6430 if (s - input_line_pointer < 3
6431 || strncasecmp (s - 3, "THEN", 4) != 0)
6432 {
6433 if (qual != '\0')
6434 {
6435 as_bad (_("missing then"));
6436 ignore_rest_of_line ();
6437 return;
6438 }
6439
6440 /* It's a conditional. */
6441 s_if (O_ne);
6442 return;
6443 }
6444
6445 /* Since this might be a conditional if, this pseudo-op will be
6446 called even if we are supported to be ignoring input. Double
6447 check now. Clobber *input_line_pointer so that ignore_input
6448 thinks that this is not a special pseudo-op. */
6449 c = *input_line_pointer;
6450 *input_line_pointer = 0;
6451 if (ignore_input ())
6452 {
6453 *input_line_pointer = c;
6454 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6455 ++input_line_pointer;
6456 demand_empty_rest_of_line ();
6457 return;
6458 }
6459 *input_line_pointer = c;
6460
6461 n = push_mri_control (mri_if);
6462
6463 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6464 n->next, s[1] == '.' ? s[2] : '\0');
6465
6466 if (s[1] == '.')
6467 input_line_pointer = s + 3;
6468 else
6469 input_line_pointer = s + 1;
6470
6471 if (flag_mri)
6472 {
6473 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6474 ++input_line_pointer;
6475 }
6476
6477 demand_empty_rest_of_line ();
6478}
6479
6480/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6481 structured IF, associate the ELSE with the IF. Otherwise, assume
6482 it is a conditional else. */
6483
6484static void
31302357 6485s_mri_else (int qual)
252b5132
RH		 6486{
6487 int c;
6488 char *buf;
6489 char q[2];
6490
6491 if (qual == '\0'
6492 && (mri_control_stack == NULL
6493 || mri_control_stack->type != mri_if
6494 || mri_control_stack->else_seen))
6495 {
6496 s_else (0);
6497 return;
6498 }
6499
6500 c = *input_line_pointer;
6501 *input_line_pointer = 0;
6502 if (ignore_input ())
6503 {
6504 *input_line_pointer = c;
6505 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6506 ++input_line_pointer;
6507 demand_empty_rest_of_line ();
6508 return;
6509 }
6510 *input_line_pointer = c;
6511
6512 if (mri_control_stack == NULL
6513 || mri_control_stack->type != mri_if
6514 || mri_control_stack->else_seen)
6515 {
6516 as_bad (_("else without matching if"));
6517 ignore_rest_of_line ();
6518 return;
6519 }
6520
6521 mri_control_stack->else_seen = 1;
6522
6523 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6524 q[0] = TOLOWER (qual);
252b5132
RH		 6525 q[1] = '\0';
6526 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6527 mri_assemble (buf);
6528 free (buf);
6529
6530 colon (mri_control_stack->next);
6531
6532 if (flag_mri)
6533 {
6534 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6535 ++input_line_pointer;
6536 }
6537
6538 demand_empty_rest_of_line ();
6539}
6540
6541/* Handle the MRI ENDI pseudo-op. */
6542
6543static void
31302357 6544s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6545{
6546 if (mri_control_stack == NULL
6547 || mri_control_stack->type != mri_if)
6548 {
6549 as_bad (_("endi without matching if"));
6550 ignore_rest_of_line ();
6551 return;
6552 }
6553
6554 /* ignore_input will not return true for ENDI, so we don't need to
6555 worry about checking it again here. */
6556
6557 if (! mri_control_stack->else_seen)
6558 colon (mri_control_stack->next);
6559 colon (mri_control_stack->bottom);
6560
6561 pop_mri_control ();
6562
6563 if (flag_mri)
6564 {
6565 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6566 ++input_line_pointer;
6567 }
6568
6569 demand_empty_rest_of_line ();
6570}
6571
6572/* Handle the MRI BREAK pseudo-op. */
6573
6574static void
31302357 6575s_mri_break (int extent)
252b5132
RH		 6576{
6577 struct mri_control_info *n;
6578 char *buf;
6579 char ex[2];
6580
6581 n = mri_control_stack;
6582 while (n != NULL
6583 && n->type != mri_for
6584 && n->type != mri_repeat
6585 && n->type != mri_while)
6586 n = n->outer;
6587 if (n == NULL)
6588 {
6589 as_bad (_("break outside of structured loop"));
6590 ignore_rest_of_line ();
6591 return;
6592 }
6593
6594 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6595 ex[0] = TOLOWER (extent);
252b5132
RH		 6596 ex[1] = '\0';
6597 sprintf (buf, "bra%s %s", ex, n->bottom);
6598 mri_assemble (buf);
6599 free (buf);
6600
6601 if (flag_mri)
6602 {
6603 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6604 ++input_line_pointer;
6605 }
6606
6607 demand_empty_rest_of_line ();
6608}
6609
6610/* Handle the MRI NEXT pseudo-op. */
6611
6612static void
31302357 6613s_mri_next (int extent)
252b5132
RH		 6614{
6615 struct mri_control_info *n;
6616 char *buf;
6617 char ex[2];
6618
6619 n = mri_control_stack;
6620 while (n != NULL
6621 && n->type != mri_for
6622 && n->type != mri_repeat
6623 && n->type != mri_while)
6624 n = n->outer;
6625 if (n == NULL)
6626 {
6627 as_bad (_("next outside of structured loop"));
6628 ignore_rest_of_line ();
6629 return;
6630 }
6631
6632 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6633 ex[0] = TOLOWER (extent);
252b5132
RH		 6634 ex[1] = '\0';
6635 sprintf (buf, "bra%s %s", ex, n->next);
6636 mri_assemble (buf);
6637 free (buf);
6638
6639 if (flag_mri)
6640 {
6641 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6642 ++input_line_pointer;
6643 }
6644
6645 demand_empty_rest_of_line ();
6646}
6647
6648/* Handle the MRI FOR pseudo-op. */
6649
6650static void
31302357 6651s_mri_for (int qual)
252b5132
RH		 6652{
6653 const char *varstart, *varstop;
6654 const char *initstart, *initstop;
6655 const char *endstart, *endstop;
6656 const char *bystart, *bystop;
6657 int up;
6658 int by;
6659 int extent;
6660 struct mri_control_info *n;
6661 char *buf;
6662 char *s;
6663 char ex[2];
6664
6665 /* The syntax is
6666 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6667 */
6668
6669 SKIP_WHITESPACE ();
6670 varstart = input_line_pointer;
6671
6672 /* Look for the '='. */
6673 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6674 && *input_line_pointer != '=')
6675 ++input_line_pointer;
6676 if (*input_line_pointer != '=')
6677 {
6678 as_bad (_("missing ="));
6679 ignore_rest_of_line ();
6680 return;
6681 }
6682
6683 varstop = input_line_pointer;
6684 if (varstop > varstart
6685 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6686 --varstop;
6687
6688 ++input_line_pointer;
6689
6690 initstart = input_line_pointer;
6691
6692 /* Look for TO or DOWNTO. */
6693 up = 1;
6694 initstop = NULL;
6695 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6696 {
6697 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6698 && ! is_part_of_name (input_line_pointer[2]))
6699 {
6700 initstop = input_line_pointer;
6701 input_line_pointer += 2;
6702 break;
6703 }
6704 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6705 && ! is_part_of_name (input_line_pointer[6]))
6706 {
6707 initstop = input_line_pointer;
6708 up = 0;
6709 input_line_pointer += 6;
6710 break;
6711 }
6712 ++input_line_pointer;
6713 }
6714 if (initstop == NULL)
6715 {
6716 as_bad (_("missing to or downto"));
6717 ignore_rest_of_line ();
6718 return;
6719 }
6720 if (initstop > initstart
6721 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6722 --initstop;
6723
6724 SKIP_WHITESPACE ();
6725 endstart = input_line_pointer;
6726
6727 /* Look for BY or DO. */
6728 by = 0;
6729 endstop = NULL;
6730 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6731 {
6732 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6733 && ! is_part_of_name (input_line_pointer[2]))
6734 {
6735 endstop = input_line_pointer;
6736 by = 1;
6737 input_line_pointer += 2;
6738 break;
6739 }
6740 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6741 && (input_line_pointer[2] == '.'
6742 || ! is_part_of_name (input_line_pointer[2])))
6743 {
6744 endstop = input_line_pointer;
6745 input_line_pointer += 2;
6746 break;
6747 }
6748 ++input_line_pointer;
6749 }
6750 if (endstop == NULL)
6751 {
6752 as_bad (_("missing do"));
6753 ignore_rest_of_line ();
6754 return;
6755 }
6756 if (endstop > endstart
6757 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6758 --endstop;
6759
6760 if (! by)
6761 {
6762 bystart = "#1";
6763 bystop = bystart + 2;
6764 }
6765 else
6766 {
6767 SKIP_WHITESPACE ();
6768 bystart = input_line_pointer;
6769
6770 /* Look for DO. */
6771 bystop = NULL;
6772 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6773 {
6774 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6775 && (input_line_pointer[2] == '.'
6776 || ! is_part_of_name (input_line_pointer[2])))
6777 {
6778 bystop = input_line_pointer;
6779 input_line_pointer += 2;
6780 break;
6781 }
6782 ++input_line_pointer;
6783 }
6784 if (bystop == NULL)
6785 {
6786 as_bad (_("missing do"));
6787 ignore_rest_of_line ();
6788 return;
6789 }
6790 if (bystop > bystart
6791 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6792 --bystop;
6793 }
6794
6795 if (*input_line_pointer != '.')
6796 extent = '\0';
6797 else
6798 {
6799 extent = input_line_pointer[1];
6800 input_line_pointer += 2;
6801 }
6802
6803 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6804 n = push_mri_control (mri_for);
6805
6806 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6807
36759679 6808 /* Move init,var. */
252b5132
RH		 6809 s = buf;
6810 *s++ = 'm';
6811 *s++ = 'o';
6812 *s++ = 'v';
6813 *s++ = 'e';
6814 if (qual != '\0')
3882b010 6815 *s++ = TOLOWER (qual);
252b5132
RH		 6816 *s++ = ' ';
6817 memcpy (s, initstart, initstop - initstart);
6818 s += initstop - initstart;
6819 *s++ = ',';
6820 memcpy (s, varstart, varstop - varstart);
6821 s += varstop - varstart;
6822 *s = '\0';
6823 mri_assemble (buf);
6824
6825 colon (n->top);
6826
36759679 6827 /* cmp end,var. */
252b5132
RH		 6828 s = buf;
6829 *s++ = 'c';
6830 *s++ = 'm';
6831 *s++ = 'p';
6832 if (qual != '\0')
3882b010 6833 *s++ = TOLOWER (qual);
252b5132
RH		 6834 *s++ = ' ';
6835 memcpy (s, endstart, endstop - endstart);
6836 s += endstop - endstart;
6837 *s++ = ',';
6838 memcpy (s, varstart, varstop - varstart);
6839 s += varstop - varstart;
6840 *s = '\0';
6841 mri_assemble (buf);
6842
36759679 6843 /* bcc bottom. */
3882b010 6844 ex[0] = TOLOWER (extent);
252b5132
RH		 6845 ex[1] = '\0';
6846 if (up)
6847 sprintf (buf, "blt%s %s", ex, n->bottom);
6848 else
6849 sprintf (buf, "bgt%s %s", ex, n->bottom);
6850 mri_assemble (buf);
6851
6852 /* Put together the add or sub instruction used by ENDF. */
6853 s = buf;
6854 if (up)
6855 strcpy (s, "add");
6856 else
6857 strcpy (s, "sub");
6858 s += 3;
6859 if (qual != '\0')
3882b010 6860 *s++ = TOLOWER (qual);
252b5132
RH		 6861 *s++ = ' ';
6862 memcpy (s, bystart, bystop - bystart);
6863 s += bystop - bystart;
6864 *s++ = ',';
6865 memcpy (s, varstart, varstop - varstart);
6866 s += varstop - varstart;
6867 *s = '\0';
6868 n->incr = buf;
6869
6870 if (flag_mri)
6871 {
6872 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6873 ++input_line_pointer;
6874 }
6875
6876 demand_empty_rest_of_line ();
6877}
6878
6879/* Handle the MRI ENDF pseudo-op. */
6880
6881static void
31302357 6882s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6883{
6884 if (mri_control_stack == NULL
6885 || mri_control_stack->type != mri_for)
6886 {
6887 as_bad (_("endf without for"));
6888 ignore_rest_of_line ();
6889 return;
6890 }
6891
6892 colon (mri_control_stack->next);
6893
6894 mri_assemble (mri_control_stack->incr);
6895
6896 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6897 mri_assemble (mri_control_stack->incr);
6898
6899 free (mri_control_stack->incr);
6900
6901 colon (mri_control_stack->bottom);
6902
6903 pop_mri_control ();
6904
6905 if (flag_mri)
6906 {
6907 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6908 ++input_line_pointer;
6909 }
6910
6911 demand_empty_rest_of_line ();
6912}
6913
6914/* Handle the MRI REPEAT pseudo-op. */
6915
6916static void
31302357 6917s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6918{
6919 struct mri_control_info *n;
6920
6921 n = push_mri_control (mri_repeat);
6922 colon (n->top);
6923 if (flag_mri)
6924 {
6925 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6926 ++input_line_pointer;
6927 }
6928 demand_empty_rest_of_line ();
6929}
6930
6931/* Handle the MRI UNTIL pseudo-op. */
6932
6933static void
31302357 6934s_mri_until (int qual)
252b5132
RH		 6935{
6936 char *s;
6937
6938 if (mri_control_stack == NULL
6939 || mri_control_stack->type != mri_repeat)
6940 {
6941 as_bad (_("until without repeat"));
6942 ignore_rest_of_line ();
6943 return;
6944 }
6945
6946 colon (mri_control_stack->next);
6947
6948 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6949 ;
6950
6951 parse_mri_control_expression (s, qual, (const char *) NULL,
6952 mri_control_stack->top, '\0');
6953
6954 colon (mri_control_stack->bottom);
6955
6956 input_line_pointer = s;
6957
6958 pop_mri_control ();
6959
6960 if (flag_mri)
6961 {
6962 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6963 ++input_line_pointer;
6964 }
6965
6966 demand_empty_rest_of_line ();
6967}
6968
6969/* Handle the MRI WHILE pseudo-op. */
6970
6971static void
31302357 6972s_mri_while (int qual)
252b5132
RH		 6973{
6974 char *s;
6975
6976 struct mri_control_info *n;
6977
6978 s = input_line_pointer;
e1f44d10
NC		 6979 /* We only accept '*' as introduction of comments if preceded by white space
6980 or at first column of a line (I think this can't actually happen here?)
6981 This is important when assembling:
6982 while d0 <ne> 12(a0,d0*2) do
36759679 6983 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6984 while (! (is_end_of_line[(unsigned char) *s]
6985 || (flag_mri
6986 && *s == '*'
6987 && (s == input_line_pointer
6988 || *(s-1) == ' '
6989 || *(s-1) == '\t'))))
252b5132
RH		 6990 s++;
6991 --s;
6992 while (*s == ' ' || *s == '\t')
6993 --s;
6994 if (s - input_line_pointer > 1
6995 && s[-1] == '.')
6996 s -= 2;
6997 if (s - input_line_pointer < 2
6998 || strncasecmp (s - 1, "DO", 2) != 0)
6999 {
7000 as_bad (_("missing do"));
7001 ignore_rest_of_line ();
7002 return;
7003 }
7004
7005 n = push_mri_control (mri_while);
7006
7007 colon (n->next);
7008
7009 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
7010 s[1] == '.' ? s[2] : '\0');
7011
7012 input_line_pointer = s + 1;
7013 if (*input_line_pointer == '.')
7014 input_line_pointer += 2;
7015
7016 if (flag_mri)
7017 {
7018 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7019 ++input_line_pointer;
7020 }
7021
7022 demand_empty_rest_of_line ();
7023}
7024
7025/* Handle the MRI ENDW pseudo-op. */
7026
7027static void
31302357 7028s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 7029{
7030 char *buf;
7031
7032 if (mri_control_stack == NULL
7033 || mri_control_stack->type != mri_while)
7034 {
7035 as_bad (_("endw without while"));
7036 ignore_rest_of_line ();
7037 return;
7038 }
7039
7040 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
7041 sprintf (buf, "bra %s", mri_control_stack->next);
7042 mri_assemble (buf);
7043 free (buf);
7044
7045 colon (mri_control_stack->bottom);
7046
7047 pop_mri_control ();
7048
7049 if (flag_mri)
7050 {
7051 while (! is_end_of_line[(unsigned char) *input_line_pointer])
7052 ++input_line_pointer;
7053 }
7054
7055 demand_empty_rest_of_line ();
7056}
7057\f
266abb8f
NS		 7058/* Parse a .cpu directive. */
7059
7060static void
7061s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
7062{
7063 char saved_char;
7064 char *name;
7065
7066 if (initialized)
7067 {
7068 as_bad (_("already assembled instructions"));
7069 ignore_rest_of_line ();
7070 return;
7071 }
7072
7073 name = input_line_pointer;
7074 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
7075 input_line_pointer++;
7076 saved_char = *input_line_pointer;
7077 *input_line_pointer = 0;
7078
7079 m68k_set_cpu (name, 1, 0);
7080
7081 *input_line_pointer = saved_char;
7082 demand_empty_rest_of_line ();
7083 return;
7084}
7085
7086/* Parse a .arch directive. */
7087
7088static void
7089s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
7090{
7091 char saved_char;
7092 char *name;
7093
7094 if (initialized)
7095 {
7096 as_bad (_("already assembled instructions"));
7097 ignore_rest_of_line ();
7098 return;
7099 }
7100
7101 name = input_line_pointer;
7102 while (*input_line_pointer && *input_line_pointer != ','
7103 && !ISSPACE (*input_line_pointer))
7104 input_line_pointer++;
7105 saved_char = *input_line_pointer;
7106 *input_line_pointer = 0;
7107
7108 if (m68k_set_arch (name, 1, 0))
7109 {
7110 /* Scan extensions. */
7111 do
7112 {
7113 *input_line_pointer++ = saved_char;
7114 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
7115 break;
7116 name = input_line_pointer;
7117 while (*input_line_pointer && *input_line_pointer != ','
7118 && !ISSPACE (*input_line_pointer))
7119 input_line_pointer++;
7120 saved_char = *input_line_pointer;
7121 *input_line_pointer = 0;
7122 }
7123 while (m68k_set_extension (name, 1, 0));
7124 }
7125
7126 *input_line_pointer = saved_char;
7127 demand_empty_rest_of_line ();
7128 return;
7129}
7130\f
7131/* Lookup a cpu name in TABLE and return the slot found. Return NULL
7132 if none is found, the caller is responsible for emitting an error
7133 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
7134 cpu name, if it begins with a '6' (possibly skipping an intervening
7135 'c'. We also allow a 'c' in the same place. if NEGATED is
7136 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
7137 the option is indeed negated. */
7138
7139static const struct m68k_cpu *
7140m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
7141 int allow_m, int *negated)
7142{
7143 /* allow negated value? */
7144 if (negated)
7145 {
7146 *negated = 0;
7147
7148 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
7149 {
7150 arg += 3;
7151 *negated = 1;
7152 }
7153 }
7154
7155 /* Remove 'm' or 'mc' prefix from 68k variants. */
7156 if (allow_m)
7157 {
7158 if (arg[0] == 'm')
7159 {
7160 if (arg[1] == '6')
7161 arg += 1;
7162 else if (arg[1] == 'c' && arg[2] == '6')
7163 arg += 2;
7164 }
7165 }
7166 else if (arg[0] == 'c' && arg[1] == '6')
7167 arg += 1;
7168
7169 for (; table->name; table++)
7170 if (!strcmp (arg, table->name))
2da12c60
NS		 7171 {
7172 if (table->alias < -1 || table->alias > 1)
7173 as_bad (_("`%s' is deprecated, use `%s'"),
7174 table->name, table[table->alias < 0 ? 1 : -1].name);
7175 return table;
7176 }
266abb8f
NS		 7177 return 0;
7178}
7179
7180/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7181
7182static int
7183m68k_set_cpu (char const *name, int allow_m, int silent)
7184{
7185 const struct m68k_cpu *cpu;
7186
7187 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7188
7189 if (!cpu)
7190 {
7191 if (!silent)
7192 as_bad (_("cpu `%s' unrecognized"), name);
7193 return 0;
7194 }
7195
7196 if (selected_cpu && selected_cpu != cpu)
7197 {
7198 as_bad (_("already selected `%s' processor"),
7199 selected_cpu->name);
7200 return 0;
7201 }
7202 selected_cpu = cpu;
7203 return 1;
7204}
7205
7206/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7207
7208static int
7209m68k_set_arch (char const *name, int allow_m, int silent)
7210{
7211 const struct m68k_cpu *arch;
7212
7213 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7214
7215 if (!arch)
7216 {
7217 if (!silent)
7218 as_bad (_("architecture `%s' unrecognized"), name);
7219 return 0;
7220 }
7221
7222 if (selected_arch && selected_arch != arch)
7223 {
7224 as_bad (_("already selected `%s' architecture"),
7225 selected_arch->name);
7226 return 0;
7227 }
7228
7229 selected_arch = arch;
7230 return 1;
7231}
7232
7233/* Set the architecture extension, issuing errors if it is
7234 unrecognized, or invalid */
7235
7236static int
7237m68k_set_extension (char const *name, int allow_m, int silent)
7238{
7239 int negated;
7240 const struct m68k_cpu *ext;
7241
7242 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7243
7244 if (!ext)
7245 {
7246 if (!silent)
7247 as_bad (_("extension `%s' unrecognized"), name);
7248 return 0;
7249 }
7250
7251 if (negated)
7252 not_current_architecture |= ext->arch;
7253 else
7254 current_architecture |= ext->arch;
7255 return 1;
7256}
7257
31302357
AS		 7258/* md_parse_option
7259 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7260 */
252b5132
RH		 7261
7262#ifdef OBJ_ELF
5a38dc70 7263const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7264#else
5a38dc70 7265const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7266#endif
7267
7268struct option md_longopts[] = {
7269#define OPTION_PIC (OPTION_MD_BASE)
7270 {"pic", no_argument, NULL, OPTION_PIC},
7271#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7272 {"register-prefix-optional", no_argument, NULL,
7273 OPTION_REGISTER_PREFIX_OPTIONAL},
7274#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7275 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7276#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7277 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7278#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7279 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7280#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7281 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7282#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7283 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7284#define OPTION_PCREL (OPTION_MD_BASE + 7)
7285 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7286 {NULL, no_argument, NULL, 0}
7287};
bc805888 7288size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7289
7290int
31302357 7291md_parse_option (int c, char *arg)
252b5132
RH		 7292{
7293 switch (c)
7294 {
7295 case 'l': /* -l means keep external to 2 bit offset
36759679 7296 rather than 16 bit one. */
252b5132
RH		 7297 flag_short_refs = 1;
7298 break;
7299
7300 case 'S': /* -S means that jbsr's always turn into
7301 jsr's. */
7302 flag_long_jumps = 1;
7303 break;
7304
28e7409f
NC		 7305 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7306 branches into absolute jumps. */
7307 flag_keep_pcrel = 1;
7308 break;
7309
252b5132
RH		 7310 case OPTION_PIC:
7311 case 'k':
7312 flag_want_pic = 1;
36759679 7313 break; /* -pic, Position Independent Code. */
252b5132
RH		 7314
7315 case OPTION_REGISTER_PREFIX_OPTIONAL:
7316 flag_reg_prefix_optional = 1;
7317 reg_prefix_optional_seen = 1;
7318 break;
7319
7320 /* -V: SVR4 argument to print version ID. */
7321 case 'V':
7322 print_version_id ();
7323 break;
7324
7325 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7326 should be emitted or not. FIXME: Not implemented. */
7327 case 'Q':
7328 break;
7329
7330 case OPTION_BITWISE_OR:
7331 {
7332 char *n, *t;
7333 const char *s;
7334
7335 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7336 t = n;
7337 for (s = m68k_comment_chars; *s != '\0'; s++)
7338 if (*s != '|')
7339 *t++ = *s;
7340 *t = '\0';
7341 m68k_comment_chars = n;
7342 }
7343 break;
7344
7345 case OPTION_BASE_SIZE_DEFAULT_16:
7346 m68k_index_width_default = SIZE_WORD;
7347 break;
7348
7349 case OPTION_BASE_SIZE_DEFAULT_32:
7350 m68k_index_width_default = SIZE_LONG;
7351 break;
7352
7353 case OPTION_DISP_SIZE_DEFAULT_16:
7354 m68k_rel32 = 0;
7355 m68k_rel32_from_cmdline = 1;
7356 break;
7357
7358 case OPTION_DISP_SIZE_DEFAULT_32:
7359 m68k_rel32 = 1;
7360 m68k_rel32_from_cmdline = 1;
7361 break;
7362
266abb8f
NS		 7363 case 'A':
7364#if WARN_DEPRECATED
7365 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7366 arg, arg));
7367#endif
7368 /* Intentional fall-through. */
7369 case 'm':
7370 if (!strncmp (arg, "arch=", 5))
7371 m68k_set_arch (arg + 5, 1, 0);
7372 else if (!strncmp (arg, "cpu=", 4))
7373 m68k_set_cpu (arg + 4, 1, 0);
7374 else if (m68k_set_extension (arg, 0, 1))
7375 ;
0b2e31dc
NS		 7376 else if (m68k_set_arch (arg, 0, 1))
7377 ;
266abb8f
NS		 7378 else if (m68k_set_cpu (arg, 0, 1))
7379 ;
7380 else
7381 return 0;
7382 break;
7383
252b5132
RH		 7384 default:
7385 return 0;
7386 }
7387
7388 return 1;
7389}
7390
266abb8f
NS		 7391/* Setup tables from the selected arch and/or cpu */
7392
7393static void
7394m68k_init_arch (void)
7395{
266abb8f
NS		 7396 if (not_current_architecture & current_architecture)
7397 {
7398 as_bad (_("architecture features both enabled and disabled"));
7399 not_current_architecture &= ~current_architecture;
7400 }
7401 if (selected_arch)
2da12c60
NS		 7402 {
7403 current_architecture |= selected_arch->arch;
7404 control_regs = selected_arch->control_regs;
7405 }
0b2e31dc
NS		 7406 else
7407 current_architecture |= selected_cpu->arch;
0b2e31dc 7408
2da12c60
NS		 7409 current_architecture &= ~not_current_architecture;
7410
377260ba
NS		 7411 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7412 {
7413 /* Determine which float is really meant. */
7414 if (current_architecture & (m68k_mask & ~m68881))
7415 current_architecture ^= cfloat;
7416 else
7417 current_architecture ^= m68881;
7418 }
7419
0b2e31dc 7420 if (selected_cpu)
266abb8f 7421 {
2da12c60 7422 control_regs = selected_cpu->control_regs;
0b2e31dc 7423 if (current_architecture & ~selected_cpu->arch)
266abb8f 7424 {
0b2e31dc
NS		 7425 as_bad (_("selected processor does not have all features of selected architecture"));
7426 current_architecture
7427 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7428 }
7429 }
266abb8f 7430
266abb8f
NS		 7431 if ((current_architecture & m68k_mask)
7432 && (current_architecture & ~m68k_mask))
7433 {
7434 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7435 if (current_architecture & m68k_mask)
266abb8f
NS		 7436 current_architecture &= m68k_mask;
7437 else
7438 current_architecture &= ~m68k_mask;
7439 }
7440
7441 /* Permit m68881 specification with all cpus; those that can't work
7442 with a coprocessor could be doing emulation. */
7443 if (current_architecture & m68851)
7444 {
7445 if (current_architecture & m68040)
7446 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7447 }
7448 /* What other incompatibilities could we check for? */
7449
266abb8f
NS		 7450 if (cpu_of_arch (current_architecture) < m68020
7451 || arch_coldfire_p (current_architecture))
7452 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7453
7454 initialized = 1;
7455}
7456
252b5132 7457void
31302357 7458md_show_usage (FILE *stream)
252b5132 7459{
76f57f3a 7460 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7461 int i;
7462 unsigned int default_arch;
76f57f3a 7463
8a104df9 7464 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7465 if (*default_cpu == 'm')
7466 default_cpu++;
266abb8f 7467 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7468 {
266abb8f 7469 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7470 {
266abb8f 7471 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7472 while (m68k_cpus[i].alias > 0)
7473 i--;
7474 while (m68k_cpus[i].alias < 0)
7475 i++;
7476 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7477 }
7478 }
7479
bc805888 7480 fprintf (stream, _("\
266abb8f
NS		 7481-march=<arch> set architecture\n\
7482-mcpu=<cpu> set cpu [default %s]\n\
7483"), default_cpu);
7484 for (i = 0; m68k_extensions[i].name; i++)
7485 fprintf (stream, _("\
0b2e31dc
NS		 7486-m[no-]%-16s enable/disable%s architecture extension\n\
7487"), m68k_extensions[i].name,
7488 m68k_extensions[i].alias > 0 ? " ColdFire"
7489 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7490
bc805888 7491 fprintf (stream, _("\
266abb8f 7492-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7493-pic, -k generate position independent code\n\
7494-S turn jbsr into jsr\n\
28e7409f 7495--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7496--register-prefix-optional\n\
7497 recognize register names without prefix character\n\
266abb8f 7498--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7499--base-size-default-16 base reg without size is 16 bits\n\
7500--base-size-default-32 base reg without size is 32 bits (default)\n\
7501--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7502--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7503"));
7504
7505 fprintf (stream, _("Architecture variants are: "));
7506 for (i = 0; m68k_archs[i].name; i++)
7507 {
7508 if (i)
7509 fprintf (stream, " | ");
7510 fprintf (stream, m68k_archs[i].name);
7511 }
7512 fprintf (stream, "\n");
7513
7514 fprintf (stream, _("Processor variants are: "));
7515 for (i = 0; m68k_cpus[i].name; i++)
7516 {
7517 if (i)
7518 fprintf (stream, " | ");
7519 fprintf (stream, m68k_cpus[i].name);
7520 }
7521 fprintf (stream, _("\n"));
252b5132
RH		 7522}
7523\f
7524#ifdef TEST2
7525
7526/* TEST2: Test md_assemble() */
36759679
NC		 7527/* Warning, this routine probably doesn't work anymore. */
7528int
31302357 7529main (void)
252b5132
RH		 7530{
7531 struct m68k_it the_ins;
7532 char buf[120];
7533 char *cp;
7534 int n;
7535
7536 m68k_ip_begin ();
7537 for (;;)
7538 {
7539 if (!gets (buf) || !*buf)
7540 break;
7541 if (buf[0] == '|' || buf[1] == '.')
7542 continue;
7543 for (cp = buf; *cp; cp++)
7544 if (*cp == '\t')
7545 *cp = ' ';
7546 if (is_label (buf))
7547 continue;
7548 memset (&the_ins, '\0', sizeof (the_ins));
7549 m68k_ip (&the_ins, buf);
7550 if (the_ins.error)
7551 {
7552 printf (_("Error %s in %s\n"), the_ins.error, buf);
7553 }
7554 else
7555 {
7556 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7557 for (n = 0; n < the_ins.numo; n++)
7558 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7559 printf (" ");
7560 print_the_insn (&the_ins.opcode[0], stdout);
7561 (void) putchar ('\n');
7562 }
7563 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7564 {
7565 if (the_ins.operands[n].error)
7566 {
7567 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7568 continue;
7569 }
31302357
AS		 7570 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7571 the_ins.operands[n].reg);
252b5132 7572 if (the_ins.operands[n].b_const)
31302357
AS		 7573 printf ("Constant: '%.*s', ",
7574 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7575 the_ins.operands[n].b_const);
7576 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7577 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7578 if (the_ins.operands[n].b_iadd)
31302357
AS		 7579 printf ("Iadd: '%.*s',",
7580 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7581 the_ins.operands[n].b_iadd);
7582 putchar ('\n');
252b5132
RH		 7583 }
7584 }
7585 m68k_ip_end ();
7586 return 0;
7587}
7588
31302357
AS		 7589int
7590is_label (char *str)
252b5132
RH		 7591{
7592 while (*str == ' ')
7593 str++;
7594 while (*str && *str != ' ')
7595 str++;
7596 if (str[-1] == ':' || str[1] == '=')
7597 return 1;
7598 return 0;
7599}
7600
7601#endif
7602
7603/* Possible states for relaxation:
7604
7605 0 0 branch offset byte (bra, etc)
7606 0 1 word
7607 0 2 long
7608
7609 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7610 1 1 word
7611 1 2 long
7612
7613 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7614 2 1 word-long
7615 2 2 long-word
7616 2 3 long-long
7617
7618 */
7619
7620/* We have no need to default values of symbols. */
7621
252b5132 7622symbolS *
31302357 7623md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7624{
7625 return 0;
7626}
7627
7628/* Round up a section size to the appropriate boundary. */
7629valueT
31302357 7630md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7631{
7632#ifdef OBJ_AOUT
252b5132
RH		 7633 /* For a.out, force the section size to be aligned. If we don't do
7634 this, BFD will align it for us, but it will not write out the
7635 final bytes of the section. This may be a bug in BFD, but it is
7636 easier to fix it here since that is how the other a.out targets
7637 work. */
7638 int align;
7639
7640 align = bfd_get_section_alignment (stdoutput, segment);
7641 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7642#endif
7643
7644 return size;
7645}
7646
7647/* Exactly what point is a PC-relative offset relative TO?
7648 On the 68k, it is relative to the address of the first extension
7649 word. The difference between the addresses of the offset and the
92774660 7650 first extension word is stored in fx_pcrel_adjust. */
252b5132 7651long
31302357 7652md_pcrel_from (fixS *fixP)
252b5132
RH		 7653{
7654 int adjust;
7655
8390138c
AS		 7656 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7657 sign extend the value here. */
7658 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7659 if (adjust == 64)
7660 adjust = -1;
7661 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7662}
7663
0d96863f 7664#ifdef OBJ_ELF
8a104df9 7665void
31302357 7666m68k_elf_final_processing (void)
0d96863f 7667{
266abb8f
NS		 7668 unsigned flags = 0;
7669
238d258f 7670 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7671 flags |= EF_M68K_CFV4E;
7672 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7673 if (cpu_of_arch (current_architecture) & cpu32)
3bdcfdf4
KH		 7674 flags |= EF_M68K_CPU32;
7675 else if (cpu_of_arch (current_architecture) & fido_a)
7676 flags |= EF_M68K_FIDO;
8a104df9
KH		 7677 else if ((cpu_of_arch (current_architecture) & m68000up)
7678 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7679 flags |= EF_M68K_M68000;
7680
7681 if (current_architecture & mcfisa_a)
7682 {
0b2e31dc
NS		 7683 static const unsigned isa_features[][2] =
7684 {
9a2e615a 7685 {EF_M68K_CF_ISA_A_NODIV,mcfisa_a},
c694fd50 7686 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
9a2e615a 7687 {EF_M68K_CF_ISA_A_PLUS, mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
c694fd50
KH		 7688 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7689 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
9a2e615a 7690 {EF_M68K_CF_ISA_C, mcfisa_a|mcfisa_c|mcfhwdiv|mcfusp},
0b2e31dc
NS		 7691 {0,0},
7692 };
7693 static const unsigned mac_features[][2] =
7694 {
c694fd50
KH		 7695 {EF_M68K_CF_MAC, mcfmac},
7696 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7697 {0,0},
7698 };
7699 unsigned ix;
7700 unsigned pattern;
266abb8f 7701
0b2e31dc 7702 pattern = (current_architecture
9a2e615a 7703 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfisa_c|mcfhwdiv|mcfusp));
0b2e31dc
NS		 7704 for (ix = 0; isa_features[ix][1]; ix++)
7705 {
7706 if (pattern == isa_features[ix][1])
7707 {
7708 flags |= isa_features[ix][0];
7709 break;
7710 }
7711 }
7712 if (!isa_features[ix][1])
7713 {
7714 cf_bad:
7715 as_warn (_("Not a defined coldfire architecture"));
7716 }
7717 else
7718 {
7719 if (current_architecture & cfloat)
c694fd50 7720 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7721
0b2e31dc
NS		 7722 pattern = current_architecture & (mcfmac|mcfemac);
7723 if (pattern)
7724 {
7725 for (ix = 0; mac_features[ix][1]; ix++)
7726 {
7727 if (pattern == mac_features[ix][1])
7728 {
7729 flags |= mac_features[ix][0];
7730 break;
7731 }
7732 }
7733 if (!mac_features[ix][1])
7734 goto cf_bad;
7735 }
7736 }
266abb8f
NS		 7737 }
7738 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7739}
7740#endif
c04898f8
AS		 7741
7742int
1df69f4f 7743tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 7744{
7745 unsigned int regnum;
7746 static const char *const regnames[] =
7747 {
7748 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7749 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7750 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7751 "pc"
7752 };
7753
7754 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7755 if (strcmp (regname, regnames[regnum]) == 0)
7756 return regnum;
7757
7758 return -1;
7759}
7760
7761void
7762tc_m68k_frame_initial_instructions (void)
7763{
7764 static int sp_regno = -1;
7765
7766 if (sp_regno < 0)
7767 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7768
7769 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7770 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7771}
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