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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
f7e42eb4 2 Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
266abb8f 3 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
252b5132
RH		 4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
4b4da160
NC		 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
20 02110-1301, USA. */
252b5132 21
252b5132 22#include "as.h"
3882b010 23#include "safe-ctype.h"
252b5132
RH		 24#include "obstack.h"
25#include "subsegs.h"
f27a3839 26#include "dwarf2dbg.h"
c04898f8 27#include "dw2gencfi.h"
252b5132
RH		 28
29#include "opcode/m68k.h"
30#include "m68k-parse.h"
31
0d96863f
CM		 32#if defined (OBJ_ELF)
33#include "elf/m68k.h"
34#endif
35
31302357
AS		 36#ifdef M68KCOFF
37#include "obj-coff.h"
38#endif
39
252b5132
RH		 40/* This string holds the chars that always start a comment. If the
41 pre-processor is disabled, these aren't very useful. The macro
42 tc_comment_chars points to this. We use this, rather than the
43 usual comment_chars, so that the --bitwise-or option will work. */
44#if defined (TE_SVR4) || defined (TE_DELTA)
45const char *m68k_comment_chars = "|#";
46#else
47const char *m68k_comment_chars = "|";
48#endif
49
50/* This array holds the chars that only start a comment at the beginning of
51 a line. If the line seems to have the form '# 123 filename'
52 .line and .file directives will appear in the pre-processed output */
53/* Note that input_file.c hand checks for '#' at the beginning of the
54 first line of the input file. This is because the compiler outputs
92774660
KH		 55 #NO_APP at the beginning of its output. */
56/* Also note that comments like this one will always work. */
252b5132
RH		 57const char line_comment_chars[] = "#*";
58
63a0b638 59const char line_separator_chars[] = ";";
252b5132 60
36759679 61/* Chars that can be used to separate mant from exp in floating point nums. */
5a38dc70 62const char EXP_CHARS[] = "eE";
252b5132
RH		 63
64/* Chars that mean this number is a floating point constant, as
65 in "0f12.456" or "0d1.2345e12". */
66
5a38dc70 67const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
252b5132
RH		 68
69/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
70 changed in read.c . Ideally it shouldn't have to know about it at all,
71 but nothing is ideal around here. */
72
252b5132
RH		 73/* Are we trying to generate PIC code? If so, absolute references
74 ought to be made into linkage table references or pc-relative
92774660 75 references. Not implemented. For ELF there are other means
252b5132
RH		 76 to denote pic relocations. */
77int flag_want_pic;
78
36759679
NC		 79static int flag_short_refs; /* -l option. */
80static int flag_long_jumps; /* -S option. */
28e7409f 81static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 82
83#ifdef REGISTER_PREFIX_OPTIONAL
84int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
85#else
86int flag_reg_prefix_optional;
87#endif
88
89/* Whether --register-prefix-optional was used on the command line. */
90static int reg_prefix_optional_seen;
91
92/* The floating point coprocessor to use by default. */
93static enum m68k_register m68k_float_copnum = COP1;
94
95/* If this is non-zero, then references to number(%pc) will be taken
96 to refer to number, rather than to %pc + number. */
97static int m68k_abspcadd;
98
99/* If this is non-zero, then the quick forms of the move, add, and sub
100 instructions are used when possible. */
101static int m68k_quick = 1;
102
103/* If this is non-zero, then if the size is not specified for a base
104 or outer displacement, the assembler assumes that the size should
105 be 32 bits. */
106static int m68k_rel32 = 1;
107
108/* This is non-zero if m68k_rel32 was set from the command line. */
109static int m68k_rel32_from_cmdline;
110
111/* The default width to use for an index register when using a base
112 displacement. */
113static enum m68k_size m68k_index_width_default = SIZE_LONG;
114
115/* We want to warn if any text labels are misaligned. In order to get
116 the right line number, we need to record the line number for each
117 label. */
252b5132
RH		 118struct label_line
119{
120 struct label_line *next;
121 symbolS *label;
122 char *file;
123 unsigned int line;
124 int text;
125};
126
127/* The list of labels. */
128
129static struct label_line *labels;
130
131/* The current label. */
132
133static struct label_line *current_label;
134
60fed2d3
NC		 135/* Pointer to list holding the opcodes sorted by name. */
136static struct m68k_opcode const ** m68k_sorted_opcodes;
137
36759679
NC		 138/* Its an arbitrary name: This means I don't approve of it.
139 See flames below. */
252b5132
RH		 140static struct obstack robyn;
141
252b5132
RH		 142struct m68k_incant
143 {
144 const char *m_operands;
145 unsigned long m_opcode;
146 short m_opnum;
147 short m_codenum;
148 int m_arch;
149 struct m68k_incant *m_next;
150 };
151
152#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
153#define gettwo(x) (((x)->m_opcode)&0xffff)
154
2da12c60
NS		 155static const enum m68k_register m68000_ctrl[] = { 0 };
156static const enum m68k_register m68010_ctrl[] = {
252b5132
RH		 157 SFC, DFC, USP, VBR,
158 0
159};
2da12c60 160static const enum m68k_register m68020_ctrl[] = {
252b5132
RH		 161 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
162 0
163};
2da12c60 164static const enum m68k_register m68040_ctrl[] = {
252b5132
RH		 165 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
166 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
167 0
168};
2da12c60 169static const enum m68k_register m68060_ctrl[] = {
252b5132
RH		 170 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
171 USP, VBR, URP, SRP, PCR,
172 0
173};
2da12c60 174static const enum m68k_register mcf_ctrl[] = {
3e602632 175 CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR,
252b5132
RH		 176 RAMBAR0, RAMBAR1, MBAR,
177 0
178};
2da12c60 179static const enum m68k_register mcf5208_ctrl[] = {
266abb8f
NS		 180 CACR, ACR0, ACR1, VBR, RAMBAR1,
181 0
182};
2da12c60 183static const enum m68k_register mcf5213_ctrl[] = {
266abb8f
NS		 184 VBR, RAMBAR, FLASHBAR,
185 0
186};
2da12c60
NS		 187static const enum m68k_register mcf5216_ctrl[] = {
188 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
266abb8f
NS		 189 0
190};
2da12c60
NS		 191static const enum m68k_register mcf5235_ctrl[] = {
192 VBR, CACR, ACR0, ACR1, RAMBAR,
e80e0390
NC		 193 0
194};
2da12c60
NS		 195static const enum m68k_register mcf5249_ctrl[] = {
196 VBR, CACR, ACR0, ACR1, RAMBAR0, RAMBAR1, MBAR, MBAR2,
3e602632
NC		 197 0
198};
2da12c60
NS		 199static const enum m68k_register mcf5250_ctrl[] = {
200 VBR,
201 0
202};
203static const enum m68k_register mcf5271_ctrl[] = {
204 VBR, CACR, ACR0, ACR1, RAMBAR,
205 0
206};
207static const enum m68k_register mcf5272_ctrl[] = {
208 VBR, CACR, ACR0, ACR1, ROMBAR, RAMBAR, MBAR,
209 0
210};
211static const enum m68k_register mcf5275_ctrl[] = {
212 VBR, CACR, ACR0, ACR1, RAMBAR,
213 0
214};
215static const enum m68k_register mcf5282_ctrl[] = {
216 VBR, CACR, ACR0, ACR1, FLASHBAR, RAMBAR,
217 0
218};
219static const enum m68k_register mcf5329_ctrl[] = {
220 VBR, CACR, ACR0, ACR1, RAMBAR,
221 0
222};
223static const enum m68k_register mcf5373_ctrl[] = {
224 VBR, CACR, ACR0, ACR1, RAMBAR,
225 0
226};
227static const enum m68k_register mcfv4e_ctrl[] = {
3e602632
NC		 228 CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR,
229 ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1,
230 PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1,
231 PCR3U0, PCR3L0, PCR3U1, PCR3L1,
232 0
233};
2da12c60 234#define cpu32_ctrl m68010_ctrl
252b5132
RH		 235
236static const enum m68k_register *control_regs;
237
36759679 238/* Internal form of a 68020 instruction. */
252b5132
RH		 239struct m68k_it
240{
241 const char *error;
36759679 242 const char *args; /* List of opcode info. */
252b5132
RH		 243 int numargs;
244
36759679 245 int numo; /* Number of shorts in opcode. */
252b5132
RH		 246 short opcode[11];
247
248 struct m68k_op operands[6];
249
36759679 250 int nexp; /* Number of exprs in use. */
252b5132
RH		 251 struct m68k_exp exprs[4];
252
36759679 253 int nfrag; /* Number of frags we have to produce. */
252b5132
RH		 254 struct
255 {
36759679 256 int fragoff; /* Where in the current opcode the frag ends. */
252b5132
RH		 257 symbolS *fadd;
258 offsetT foff;
259 int fragty;
260 }
261 fragb[4];
262
36759679 263 int nrel; /* Num of reloc strucs in use. */
252b5132
RH		 264 struct
265 {
266 int n;
267 expressionS exp;
268 char wid;
269 char pcrel;
270 /* In a pc relative address the difference between the address
271 of the offset and the address that the offset is relative
272 to. This depends on the addressing mode. Basically this
273 is the value to put in the offset field to address the
274 first byte of the offset, without regarding the special
275 significance of some values (in the branch instruction, for
276 example). */
277 int pcrel_fix;
278#ifdef OBJ_ELF
279 /* Whether this expression needs special pic relocation, and if
280 so, which. */
281 enum pic_relocation pic_reloc;
282#endif
283 }
36759679 284 reloc[5]; /* Five is enough??? */
252b5132
RH		 285};
286
6b6e92f4 287#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a))
252b5132
RH		 288#define float_of_arch(x) ((x) & mfloat)
289#define mmu_of_arch(x) ((x) & mmmu)
6b6e92f4
NC		 290#define arch_coldfire_p(x) ((x) & mcfisa_a)
291#define arch_coldfire_fpu(x) ((x) & cfloat)
252b5132 292
36759679 293/* Macros for determining if cpu supports a specific addressing mode. */
6b6e92f4 294#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b))
252b5132 295
36759679 296static struct m68k_it the_ins; /* The instruction being assembled. */
252b5132
RH		 297
298#define op(ex) ((ex)->exp.X_op)
299#define adds(ex) ((ex)->exp.X_add_symbol)
300#define subs(ex) ((ex)->exp.X_op_symbol)
301#define offs(ex) ((ex)->exp.X_add_number)
302
36759679 303/* Macros for adding things to the m68k_it struct. */
31302357 304#define addword(w) (the_ins.opcode[the_ins.numo++] = (w))
252b5132 305
36759679
NC		 306/* Like addword, but goes BEFORE general operands. */
307
252b5132 308static void
31302357 309insop (int w, const struct m68k_incant *opcode)
252b5132
RH		 310{
311 int z;
07726851 312 for (z = the_ins.numo; z > opcode->m_codenum; --z)
8a104df9
KH		 313 the_ins.opcode[z] = the_ins.opcode[z - 1];
314 for (z = 0; z < the_ins.nrel; z++)
315 the_ins.reloc[z].n += 2;
252b5132
RH		 316 for (z = 0; z < the_ins.nfrag; z++)
317 the_ins.fragb[z].fragoff++;
8a104df9 318 the_ins.opcode[opcode->m_codenum] = w;
252b5132
RH		 319 the_ins.numo++;
320}
321
322/* The numo+1 kludge is so we can hit the low order byte of the prev word.
323 Blecch. */
324static void
31302357 325add_fix (int width, struct m68k_exp *exp, int pc_rel, int pc_fix)
252b5132 326{
31302357
AS		 327 the_ins.reloc[the_ins.nrel].n = (width == 'B' || width == '3'
328 ? the_ins.numo * 2 - 1
329 : (width == 'b'
330 ? the_ins.numo * 2 + 1
331 : the_ins.numo * 2));
252b5132
RH		 332 the_ins.reloc[the_ins.nrel].exp = exp->exp;
333 the_ins.reloc[the_ins.nrel].wid = width;
334 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
335#ifdef OBJ_ELF
336 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
337#endif
338 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
339}
340
341/* Cause an extra frag to be generated here, inserting up to 10 bytes
342 (that value is chosen in the frag_var call in md_assemble). TYPE
343 is the subtype of the frag to be generated; its primary type is
344 rs_machine_dependent.
345
346 The TYPE parameter is also used by md_convert_frag_1 and
347 md_estimate_size_before_relax. The appropriate type of fixup will
348 be emitted by md_convert_frag_1.
349
350 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
351static void
31302357 352add_frag (symbolS *add, offsetT off, int type)
252b5132 353{
8a104df9
KH		 354 the_ins.fragb[the_ins.nfrag].fragoff = the_ins.numo;
355 the_ins.fragb[the_ins.nfrag].fadd = add;
356 the_ins.fragb[the_ins.nfrag].foff = off;
357 the_ins.fragb[the_ins.nfrag++].fragty = type;
252b5132
RH		 358}
359
360#define isvar(ex) \
361 (op (ex) != O_constant && op (ex) != O_big)
362
31302357
AS		 363static char *crack_operand (char *str, struct m68k_op *opP);
364static int get_num (struct m68k_exp *exp, int ok);
365static int reverse_16_bits (int in);
366static int reverse_8_bits (int in);
367static void install_gen_operand (int mode, int val);
368static void install_operand (int mode, int val);
369static void s_bss (int);
370static void s_data1 (int);
371static void s_data2 (int);
372static void s_even (int);
373static void s_proc (int);
374static void s_chip (int);
375static void s_fopt (int);
376static void s_opt (int);
377static void s_reg (int);
378static void s_restore (int);
379static void s_save (int);
380static void s_mri_if (int);
381static void s_mri_else (int);
382static void s_mri_endi (int);
383static void s_mri_break (int);
384static void s_mri_next (int);
385static void s_mri_for (int);
386static void s_mri_endf (int);
387static void s_mri_repeat (int);
388static void s_mri_until (int);
389static void s_mri_while (int);
390static void s_mri_endw (int);
266abb8f
NS		 391static void s_m68k_cpu (int);
392static void s_m68k_arch (int);
393
394struct m68k_cpu
395{
396 unsigned long arch; /* Architecture features. */
2da12c60 397 const enum m68k_register *control_regs; /* Control regs on chip */
266abb8f 398 const char *name; /* Name */
0b2e31dc
NS		 399 int alias; /* Alias for a cannonical name. If 1, then
400 succeeds canonical name, if -1 then
401 succeeds canonical name, if <-1 ||>1 this is a
402 deprecated name, and the next/previous name
403 should be used. */
266abb8f 404};
252b5132 405
266abb8f
NS		 406/* We hold flags for features explicitly enabled and explicitly
407 disabled. */
252b5132 408static int current_architecture;
266abb8f 409static int not_current_architecture;
266abb8f
NS		 410static const struct m68k_cpu *selected_arch;
411static const struct m68k_cpu *selected_cpu;
412static int initialized;
252b5132 413
266abb8f
NS		 414/* Architecture models. */
415static const struct m68k_cpu m68k_archs[] =
416{
2da12c60
NS		 417 {m68000, m68000_ctrl, "68000", 0},
418 {m68010, m68010_ctrl, "68010", 0},
419 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
420 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
421 {m68040, m68040_ctrl, "68040", 0},
422 {m68060, m68060_ctrl, "68060", 0},
423 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
424 {mcfisa_a|mcfhwdiv, NULL, "isaa", 0},
425 {mcfisa_a|mcfhwdiv|mcfisa_aa|mcfusp, NULL, "isaaplus", 0},
426 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfusp, NULL, "isab", 0},
427 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac|mcfusp, mcf_ctrl, "cfv4", 0},
428 {mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "cfv4e", 0},
266abb8f
NS		 429 {0,0,NULL, 0}
430};
252b5132 431
0b2e31dc
NS		 432/* Architecture extensions, here 'alias' -1 for m68k, +1 for cf and 0
433 for either. */
266abb8f
NS		 434static const struct m68k_cpu m68k_extensions[] =
435{
2da12c60
NS		 436 {m68851, NULL, "68851", -1},
437 {m68881, NULL, "68881", -1},
438 {m68881, NULL, "68882", -1},
0b2e31dc 439
2da12c60 440 {cfloat|m68881, NULL, "float", 0},
266abb8f 441
2da12c60
NS		 442 {mcfhwdiv, NULL, "div", 1},
443 {mcfusp, NULL, "usp", 1},
444 {mcfmac, NULL, "mac", 1},
445 {mcfemac, NULL, "emac", 1},
266abb8f 446
2da12c60 447 {0,NULL,NULL, 0}
266abb8f
NS		 448};
449
450/* Processor list */
451static const struct m68k_cpu m68k_cpus[] =
452{
2da12c60
NS		 453 {m68000, m68000_ctrl, "68000", 0},
454 {m68000, m68000_ctrl, "68ec000", 1},
455 {m68000, m68000_ctrl, "68hc000", 1},
456 {m68000, m68000_ctrl, "68hc001", 1},
457 {m68000, m68000_ctrl, "68008", 1},
458 {m68000, m68000_ctrl, "68302", 1},
459 {m68000, m68000_ctrl, "68306", 1},
460 {m68000, m68000_ctrl, "68307", 1},
461 {m68000, m68000_ctrl, "68322", 1},
462 {m68000, m68000_ctrl, "68356", 1},
463 {m68010, m68010_ctrl, "68010", 0},
464 {m68020|m68881|m68851, m68020_ctrl, "68020", 0},
465 {m68020|m68881|m68851, m68020_ctrl, "68k", 1},
466 {m68020|m68881|m68851, m68020_ctrl, "68ec020", 1},
467 {m68030|m68881|m68851, m68020_ctrl, "68030", 0},
468 {m68030|m68881|m68851, m68020_ctrl, "68ec030", 1},
469 {m68040, m68040_ctrl, "68040", 0},
470 {m68040, m68040_ctrl, "68ec040", 1},
471 {m68060, m68060_ctrl, "68060", 0},
472 {m68060, m68060_ctrl, "68ec060", 1},
473
474 {cpu32|m68881, cpu32_ctrl, "cpu32", 0},
475 {cpu32|m68881, cpu32_ctrl, "68330", 1},
476 {cpu32|m68881, cpu32_ctrl, "68331", 1},
477 {cpu32|m68881, cpu32_ctrl, "68332", 1},
478 {cpu32|m68881, cpu32_ctrl, "68333", 1},
479 {cpu32|m68881, cpu32_ctrl, "68334", 1},
480 {cpu32|m68881, cpu32_ctrl, "68336", 1},
481 {cpu32|m68881, cpu32_ctrl, "68340", 1},
482 {cpu32|m68881, cpu32_ctrl, "68341", 1},
483 {cpu32|m68881, cpu32_ctrl, "68349", 1},
484 {cpu32|m68881, cpu32_ctrl, "68360", 1},
485
486 {mcfisa_a, mcf_ctrl, "5200", 0},
487 {mcfisa_a, mcf_ctrl, "5202", 1},
488 {mcfisa_a, mcf_ctrl, "5204", 1},
489 {mcfisa_a, mcf_ctrl, "5206", 1},
490
491 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5206e", 0},
492
493 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5207", -1},
494 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5208_ctrl, "5208", 0},
495
496 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5211", -1},
497 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5212", -1},
498 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfmac|mcfusp, mcf5213_ctrl, "5213", 0},
499
500 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5214", -1},
501 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "5216", 0},
502 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5216_ctrl, "521x", 2},
503
504 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5232", -1},
505 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5233", -1},
506 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5234", -1},
507 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "5235", -1},
508 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5235_ctrl, "523x", 0},
509
510 {mcfisa_a|mcfhwdiv|mcfemac, mcf5249_ctrl, "5249", 0},
511 {mcfisa_a|mcfhwdiv|mcfemac, mcf5250_ctrl, "5250", 0},
512
513 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5270", -1},
514 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5271_ctrl, "5271", 0},
515
516 {mcfisa_a|mcfhwdiv|mcfmac, mcf5272_ctrl, "5272", 0},
517
518 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5274", -1},
519 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5275_ctrl, "5275", 0},
520
521 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5280", -1},
522 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5281", -1},
523 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "5282", -1},
524 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5282_ctrl, "528x", 0},
525
526 {mcfisa_a|mcfhwdiv|mcfmac, mcf_ctrl, "5307", 0},
527
528 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5327", -1},
529 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5328", -1},
530 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "5329", -1},
531 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5329_ctrl, "532x", 0},
532
533 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5372", -1},
534 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "5373", -1},
535 {mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf5373_ctrl, "537x", 0},
536
537 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfmac, mcf_ctrl, "5407",0},
538
539 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5470", -1},
540 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5471", -1},
541 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5472", -1},
542 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5473", -1},
543 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5474", -1},
544 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5475", -1},
545 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "547x", 0},
546
547 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5480", -1},
548 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5481", -1},
549 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5482", -1},
550 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5483", -1},
551 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5484", -1},
552 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "5485", -1},
553 {mcfisa_a|mcfisa_b|mcfhwdiv|mcfemac|mcfusp|cfloat, mcfv4e_ctrl, "548x", 0},
554
555 {0,NULL,NULL, 0}
dc84e067 556 };
252b5132 557
266abb8f
NS		 558static const struct m68k_cpu *m68k_lookup_cpu
559(const char *, const struct m68k_cpu *, int, int *);
560static int m68k_set_arch (const char *, int, int);
561static int m68k_set_cpu (const char *, int, int);
562static int m68k_set_extension (const char *, int, int);
563static void m68k_init_arch (void);
252b5132 564
151337e8
NC		 565/* This is the assembler relaxation table for m68k. m68k is a rich CISC
566 architecture and we have a lot of relaxation modes. */
252b5132 567
151337e8
NC		 568/* Macros used in the relaxation code. */
569#define TAB(x,y) (((x) << 2) + (y))
570#define TABTYPE(x) ((x) >> 2)
571
572/* Relaxation states. */
573#define BYTE 0
574#define SHORT 1
575#define LONG 2
576#define SZ_UNDEF 3
577
578/* Here are all the relaxation modes we support. First we can relax ordinary
579 branches. On 68020 and higher and on CPU32 all branch instructions take
580 three forms, so on these CPUs all branches always remain as such. When we
581 have to expand to the LONG form on a 68000, though, we substitute an
582 absolute jump instead. This is a direct replacement for unconditional
583 branches and a branch over a jump for conditional branches. However, if the
584 user requires PIC and disables this with --pcrel, we can only relax between
585 BYTE and SHORT forms, punting if that isn't enough. This gives us four
586 different relaxation modes for branches: */
587
36759679
NC		 588#define BRANCHBWL 0 /* Branch byte, word, or long. */
589#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */
590#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */
591#define BRANCHBW 3 /* Branch byte or word. */
151337e8
NC		 592
593/* We also relax coprocessor branches and DBcc's. All CPUs that support
594 coprocessor branches support them in word and long forms, so we have only
595 one relaxation mode for them. DBcc's are word only on all CPUs. We can
596 relax them to the LONG form with a branch-around sequence. This sequence
597 can use a long branch (if available) or an absolute jump (if acceptable).
598 This gives us two relaxation modes. If long branches are not available and
599 absolute jumps are not acceptable, we don't relax DBcc's. */
600
36759679
NC		 601#define FBRANCH 4 /* Coprocessor branch. */
602#define DBCCLBR 5 /* DBcc relaxable with a long branch. */
603#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */
151337e8
NC		 604
605/* That's all for instruction relaxation. However, we also relax PC-relative
606 operands. Specifically, we have three operand relaxation modes. On the
607 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
608 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
609 two. Also PC+displacement+index operands in their simple form (with a non-
610 suppressed index without memory indirection) are supported on all CPUs, but
611 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
612 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
613 form of the PC+displacement+index operand. Finally, some absolute operands
614 can be relaxed down to 16-bit PC-relative. */
615
36759679
NC		 616#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */
617#define PCINDEX 8 /* PC + displacement + index. */
618#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */
252b5132
RH		 619
620/* Note that calls to frag_var need to specify the maximum expansion
621 needed; this is currently 10 bytes for DBCC. */
622
623/* The fields are:
624 How far Forward this mode will reach:
625 How far Backward this mode will reach:
626 How many bytes this mode will add to the size of the frag
627 Which mode to go to if the offset won't fit in this one
d7861ad2
AM		 628
629 Please check tc-m68k.h:md_prepare_relax_scan if changing this table. */
252b5132
RH		 630relax_typeS md_relax_table[] =
631{
ac62c346
AM		 632 { 127, -128, 0, TAB (BRANCHBWL, SHORT) },
633 { 32767, -32768, 2, TAB (BRANCHBWL, LONG) },
634 { 0, 0, 4, 0 },
635 { 1, 1, 0, 0 },
636
637 { 127, -128, 0, TAB (BRABSJUNC, SHORT) },
638 { 32767, -32768, 2, TAB (BRABSJUNC, LONG) },
639 { 0, 0, 4, 0 },
640 { 1, 1, 0, 0 },
641
642 { 127, -128, 0, TAB (BRABSJCOND, SHORT) },
643 { 32767, -32768, 2, TAB (BRABSJCOND, LONG) },
644 { 0, 0, 6, 0 },
645 { 1, 1, 0, 0 },
646
647 { 127, -128, 0, TAB (BRANCHBW, SHORT) },
648 { 0, 0, 2, 0 },
649 { 1, 1, 0, 0 },
650 { 1, 1, 0, 0 },
651
36759679 652 { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */
ac62c346
AM		 653 { 32767, -32768, 2, TAB (FBRANCH, LONG) },
654 { 0, 0, 4, 0 },
655 { 1, 1, 0, 0 },
656
36759679 657 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 658 { 32767, -32768, 2, TAB (DBCCLBR, LONG) },
659 { 0, 0, 10, 0 },
660 { 1, 1, 0, 0 },
661
36759679 662 { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */
ac62c346
AM		 663 { 32767, -32768, 2, TAB (DBCCABSJ, LONG) },
664 { 0, 0, 10, 0 },
665 { 1, 1, 0, 0 },
666
36759679 667 { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */
ac62c346
AM		 668 { 32767, -32768, 2, TAB (PCREL1632, LONG) },
669 { 0, 0, 6, 0 },
670 { 1, 1, 0, 0 },
671
672 { 125, -130, 0, TAB (PCINDEX, SHORT) },
673 { 32765, -32770, 2, TAB (PCINDEX, LONG) },
674 { 0, 0, 4, 0 },
675 { 1, 1, 0, 0 },
676
36759679 677 { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */
ac62c346
AM		 678 { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) },
679 { 0, 0, 4, 0 },
680 { 1, 1, 0, 0 },
252b5132
RH		 681};
682
683/* These are the machine dependent pseudo-ops. These are included so
684 the assembler can work on the output from the SUN C compiler, which
36759679 685 generates these. */
252b5132
RH		 686
687/* This table describes all the machine specific pseudo-ops the assembler
688 has to support. The fields are:
689 pseudo-op name without dot
690 function to call to execute this pseudo-op
36759679 691 Integer arg to pass to the function. */
252b5132
RH		 692const pseudo_typeS md_pseudo_table[] =
693{
694 {"data1", s_data1, 0},
695 {"data2", s_data2, 0},
696 {"bss", s_bss, 0},
697 {"even", s_even, 0},
698 {"skip", s_space, 0},
699 {"proc", s_proc, 0},
700#if defined (TE_SUN3) || defined (OBJ_ELF)
701 {"align", s_align_bytes, 0},
702#endif
703#ifdef OBJ_ELF
704 {"swbeg", s_ignore, 0},
705#endif
706 {"extend", float_cons, 'x'},
707 {"ldouble", float_cons, 'x'},
708
266abb8f
NS		 709 {"arch", s_m68k_arch, 0},
710 {"cpu", s_m68k_cpu, 0},
711
252b5132
RH		 712 /* The following pseudo-ops are supported for MRI compatibility. */
713 {"chip", s_chip, 0},
714 {"comline", s_space, 1},
715 {"fopt", s_fopt, 0},
716 {"mask2", s_ignore, 0},
717 {"opt", s_opt, 0},
718 {"reg", s_reg, 0},
719 {"restore", s_restore, 0},
720 {"save", s_save, 0},
721
722 {"if", s_mri_if, 0},
723 {"if.b", s_mri_if, 'b'},
724 {"if.w", s_mri_if, 'w'},
725 {"if.l", s_mri_if, 'l'},
726 {"else", s_mri_else, 0},
727 {"else.s", s_mri_else, 's'},
728 {"else.l", s_mri_else, 'l'},
729 {"endi", s_mri_endi, 0},
730 {"break", s_mri_break, 0},
731 {"break.s", s_mri_break, 's'},
732 {"break.l", s_mri_break, 'l'},
733 {"next", s_mri_next, 0},
734 {"next.s", s_mri_next, 's'},
735 {"next.l", s_mri_next, 'l'},
736 {"for", s_mri_for, 0},
737 {"for.b", s_mri_for, 'b'},
738 {"for.w", s_mri_for, 'w'},
739 {"for.l", s_mri_for, 'l'},
740 {"endf", s_mri_endf, 0},
741 {"repeat", s_mri_repeat, 0},
742 {"until", s_mri_until, 0},
743 {"until.b", s_mri_until, 'b'},
744 {"until.w", s_mri_until, 'w'},
745 {"until.l", s_mri_until, 'l'},
746 {"while", s_mri_while, 0},
747 {"while.b", s_mri_while, 'b'},
748 {"while.w", s_mri_while, 'w'},
749 {"while.l", s_mri_while, 'l'},
750 {"endw", s_mri_endw, 0},
751
752 {0, 0, 0}
753};
754
252b5132 755/* The mote pseudo ops are put into the opcode table, since they
31302357 756 don't start with a . they look like opcodes to gas. */
252b5132 757
5a38dc70 758const pseudo_typeS mote_pseudo_table[] =
252b5132
RH		 759{
760
761 {"dcl", cons, 4},
762 {"dc", cons, 2},
763 {"dcw", cons, 2},
764 {"dcb", cons, 1},
765
766 {"dsl", s_space, 4},
767 {"ds", s_space, 2},
768 {"dsw", s_space, 2},
769 {"dsb", s_space, 1},
770
771 {"xdef", s_globl, 0},
772#ifdef OBJ_ELF
773 {"align", s_align_bytes, 0},
774#else
775 {"align", s_align_ptwo, 0},
776#endif
777#ifdef M68KCOFF
778 {"sect", obj_coff_section, 0},
779 {"section", obj_coff_section, 0},
780#endif
781 {0, 0, 0}
782};
783
bd17c2c3
AM		 784/* Truncate and sign-extend at 32 bits, so that building on a 64-bit host
785 gives identical results to a 32-bit host. */
786#define TRUNC(X) ((valueT) (X) & 0xffffffff)
787#define SEXT(X) ((TRUNC (X) ^ 0x80000000) - 0x80000000)
788
789#define issbyte(x) ((valueT) SEXT (x) + 0x80 < 0x100)
790#define isubyte(x) ((valueT) TRUNC (x) < 0x100)
791#define issword(x) ((valueT) SEXT (x) + 0x8000 < 0x10000)
792#define isuword(x) ((valueT) TRUNC (x) < 0x10000)
793
794#define isbyte(x) ((valueT) SEXT (x) + 0xff < 0x1ff)
795#define isword(x) ((valueT) SEXT (x) + 0xffff < 0x1ffff)
252b5132
RH		 796#define islong(x) (1)
797
252b5132
RH		 798static char notend_table[256];
799static char alt_notend_table[256];
800#define notend(s) \
801 (! (notend_table[(unsigned char) *s] \
802 || (*s == ':' \
803 && alt_notend_table[(unsigned char) s[1]])))
804
252b5132
RH		 805#ifdef OBJ_ELF
806
c801568a
AM		 807/* Return zero if the reference to SYMBOL from within the same segment may
808 be relaxed. */
809
810/* On an ELF system, we can't relax an externally visible symbol,
811 because it may be overridden by a shared library. However, if
812 TARGET_OS is "elf", then we presume that we are assembling for an
813 embedded system, in which case we don't have to worry about shared
814 libraries, and we can relax any external sym. */
815
816#define relaxable_symbol(symbol) \
6358301e 817 (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \
c801568a
AM		 818 || S_IS_WEAK (symbol)))
819
252b5132
RH		 820/* Compute the relocation code for a fixup of SIZE bytes, using pc
821 relative relocation if PCREL is non-zero. PIC says whether a special
822 pic relocation was requested. */
823
252b5132 824static bfd_reloc_code_real_type
31302357 825get_reloc_code (int size, int pcrel, enum pic_relocation pic)
252b5132
RH		 826{
827 switch (pic)
828 {
829 case pic_got_pcrel:
830 switch (size)
831 {
832 case 1:
833 return BFD_RELOC_8_GOT_PCREL;
834 case 2:
835 return BFD_RELOC_16_GOT_PCREL;
836 case 4:
837 return BFD_RELOC_32_GOT_PCREL;
838 }
839 break;
840
841 case pic_got_off:
842 switch (size)
843 {
844 case 1:
845 return BFD_RELOC_8_GOTOFF;
846 case 2:
847 return BFD_RELOC_16_GOTOFF;
848 case 4:
849 return BFD_RELOC_32_GOTOFF;
850 }
851 break;
852
853 case pic_plt_pcrel:
854 switch (size)
855 {
856 case 1:
857 return BFD_RELOC_8_PLT_PCREL;
858 case 2:
859 return BFD_RELOC_16_PLT_PCREL;
860 case 4:
861 return BFD_RELOC_32_PLT_PCREL;
862 }
863 break;
864
865 case pic_plt_off:
866 switch (size)
867 {
868 case 1:
869 return BFD_RELOC_8_PLTOFF;
870 case 2:
871 return BFD_RELOC_16_PLTOFF;
872 case 4:
873 return BFD_RELOC_32_PLTOFF;
874 }
875 break;
876
877 case pic_none:
878 if (pcrel)
879 {
880 switch (size)
881 {
882 case 1:
883 return BFD_RELOC_8_PCREL;
884 case 2:
885 return BFD_RELOC_16_PCREL;
886 case 4:
887 return BFD_RELOC_32_PCREL;
888 }
889 }
890 else
891 {
892 switch (size)
893 {
894 case 1:
895 return BFD_RELOC_8;
896 case 2:
897 return BFD_RELOC_16;
898 case 4:
899 return BFD_RELOC_32;
900 }
901 }
902 }
903
904 if (pcrel)
905 {
906 if (pic == pic_none)
907 as_bad (_("Can not do %d byte pc-relative relocation"), size);
908 else
909 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
910 }
911 else
912 {
913 if (pic == pic_none)
914 as_bad (_("Can not do %d byte relocation"), size);
915 else
916 as_bad (_("Can not do %d byte pic relocation"), size);
917 }
918
919 return BFD_RELOC_NONE;
920}
921
922/* Here we decide which fixups can be adjusted to make them relative
923 to the beginning of the section instead of the symbol. Basically
924 we need to make sure that the dynamic relocations are done
925 correctly, so in some cases we force the original symbol to be
926 used. */
927int
31302357 928tc_m68k_fix_adjustable (fixS *fixP)
252b5132 929{
36759679 930 /* Adjust_reloc_syms doesn't know about the GOT. */
252b5132
RH		 931 switch (fixP->fx_r_type)
932 {
933 case BFD_RELOC_8_GOT_PCREL:
934 case BFD_RELOC_16_GOT_PCREL:
935 case BFD_RELOC_32_GOT_PCREL:
936 case BFD_RELOC_8_GOTOFF:
937 case BFD_RELOC_16_GOTOFF:
938 case BFD_RELOC_32_GOTOFF:
939 case BFD_RELOC_8_PLT_PCREL:
940 case BFD_RELOC_16_PLT_PCREL:
941 case BFD_RELOC_32_PLT_PCREL:
942 case BFD_RELOC_8_PLTOFF:
943 case BFD_RELOC_16_PLTOFF:
944 case BFD_RELOC_32_PLTOFF:
945 return 0;
946
947 case BFD_RELOC_VTABLE_INHERIT:
948 case BFD_RELOC_VTABLE_ENTRY:
949 return 0;
950
951 default:
952 return 1;
953 }
954}
955
956#else /* !OBJ_ELF */
957
958#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
959
c801568a
AM		 960#define relaxable_symbol(symbol) 1
961
252b5132
RH		 962#endif /* OBJ_ELF */
963
252b5132 964arelent *
31302357 965tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
252b5132
RH		 966{
967 arelent *reloc;
968 bfd_reloc_code_real_type code;
969
8ec6253e
NC		 970 /* If the tcbit is set, then this was a fixup of a negative value
971 that was never resolved. We do not have a reloc to handle this,
972 so just return. We assume that other code will have detected this
973 situation and produced a helpful error message, so we just tell the
974 user that the reloc cannot be produced. */
252b5132 975 if (fixp->fx_tcbit)
8ec6253e
NC		 976 {
977 if (fixp->fx_addsy)
b091f402
AM		 978 as_bad_where (fixp->fx_file, fixp->fx_line,
979 _("Unable to produce reloc against symbol '%s'"),
980 S_GET_NAME (fixp->fx_addsy));
8ec6253e
NC		 981 return NULL;
982 }
252b5132
RH		 983
984 if (fixp->fx_r_type != BFD_RELOC_NONE)
985 {
986 code = fixp->fx_r_type;
987
988 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
989 that fixup_segment converted a non-PC relative reloc into a
990 PC relative reloc. In such a case, we need to convert the
991 reloc code. */
992 if (fixp->fx_pcrel)
993 {
994 switch (code)
995 {
996 case BFD_RELOC_8:
997 code = BFD_RELOC_8_PCREL;
998 break;
999 case BFD_RELOC_16:
1000 code = BFD_RELOC_16_PCREL;
1001 break;
1002 case BFD_RELOC_32:
1003 code = BFD_RELOC_32_PCREL;
1004 break;
1005 case BFD_RELOC_8_PCREL:
1006 case BFD_RELOC_16_PCREL:
1007 case BFD_RELOC_32_PCREL:
1008 case BFD_RELOC_8_GOT_PCREL:
1009 case BFD_RELOC_16_GOT_PCREL:
1010 case BFD_RELOC_32_GOT_PCREL:
1011 case BFD_RELOC_8_GOTOFF:
1012 case BFD_RELOC_16_GOTOFF:
1013 case BFD_RELOC_32_GOTOFF:
1014 case BFD_RELOC_8_PLT_PCREL:
1015 case BFD_RELOC_16_PLT_PCREL:
1016 case BFD_RELOC_32_PLT_PCREL:
1017 case BFD_RELOC_8_PLTOFF:
1018 case BFD_RELOC_16_PLTOFF:
1019 case BFD_RELOC_32_PLTOFF:
1020 break;
1021 default:
1022 as_bad_where (fixp->fx_file, fixp->fx_line,
1023 _("Cannot make %s relocation PC relative"),
1024 bfd_get_reloc_code_name (code));
1025 }
1026 }
1027 }
1028 else
1029 {
1030#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
1031 switch (F (fixp->fx_size, fixp->fx_pcrel))
1032 {
1033#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
1034 MAP (1, 0, BFD_RELOC_8);
1035 MAP (2, 0, BFD_RELOC_16);
1036 MAP (4, 0, BFD_RELOC_32);
1037 MAP (1, 1, BFD_RELOC_8_PCREL);
1038 MAP (2, 1, BFD_RELOC_16_PCREL);
1039 MAP (4, 1, BFD_RELOC_32_PCREL);
1040 default:
1041 abort ();
1042 }
1043 }
1044#undef F
1045#undef MAP
1046
1047 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 1048 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
1049 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 1050 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
1051#ifndef OBJ_ELF
1052 if (fixp->fx_pcrel)
1053 reloc->addend = fixp->fx_addnumber;
1054 else
1055 reloc->addend = 0;
1056#else
1057 if (!fixp->fx_pcrel)
1058 reloc->addend = fixp->fx_addnumber;
1059 else
1060 reloc->addend = (section->vma
8390138c
AS		 1061 /* Explicit sign extension in case char is
1062 unsigned. */
1063 + ((fixp->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80
252b5132
RH		 1064 + fixp->fx_addnumber
1065 + md_pcrel_from (fixp));
1066#endif
1067
1068 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
1069 assert (reloc->howto != 0);
1070
1071 return reloc;
1072}
1073
252b5132
RH		 1074/* Handle of the OPCODE hash table. NULL means any use before
1075 m68k_ip_begin() will crash. */
1076static struct hash_control *op_hash;
1077\f
1078/* Assemble an m68k instruction. */
1079
1080static void
31302357 1081m68k_ip (char *instring)
252b5132
RH		 1082{
1083 register char *p;
1084 register struct m68k_op *opP;
1085 register const struct m68k_incant *opcode;
1086 register const char *s;
1087 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1088 char *pdot, *pdotmove;
1089 enum m68k_size siz1, siz2;
1090 char c;
1091 int losing;
1092 int opsfound;
03b13e59 1093 struct m68k_op operands_backup[6];
252b5132
RH		 1094 LITTLENUM_TYPE words[6];
1095 LITTLENUM_TYPE *wordp;
1096 unsigned long ok_arch = 0;
1097
1098 if (*instring == ' ')
36759679 1099 instring++; /* Skip leading whitespace. */
252b5132
RH		 1100
1101 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1102 or exactly 1 space. */
252b5132
RH		 1103 pdot = 0;
1104 for (p = instring; *p != '\0'; p++)
1105 {
1106 if (*p == ' ')
1107 break;
1108 if (*p == '.')
1109 pdot = p;
1110 }
1111
1112 if (p == instring)
1113 {
1114 the_ins.error = _("No operator");
1115 return;
1116 }
1117
1118 /* p now points to the end of the opcode name, probably whitespace.
1119 Make sure the name is null terminated by clobbering the
1120 whitespace, look it up in the hash table, then fix it back.
1121 Remove a dot, first, since the opcode tables have none. */
1122 if (pdot != NULL)
1123 {
1124 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1125 *pdotmove = pdotmove[1];
1126 p--;
1127 }
1128
1129 c = *p;
1130 *p = '\0';
1131 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1132 *p = c;
1133
1134 if (pdot != NULL)
1135 {
1136 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1137 *pdotmove = pdotmove[-1];
1138 *pdot = '.';
1139 ++p;
1140 }
1141
1142 if (opcode == NULL)
1143 {
1144 the_ins.error = _("Unknown operator");
1145 return;
1146 }
1147
36759679 1148 /* Found a legitimate opcode, start matching operands. */
252b5132
RH		 1149 while (*p == ' ')
1150 ++p;
1151
1152 if (opcode->m_operands == 0)
1153 {
1154 char *old = input_line_pointer;
1155 *old = '\n';
1156 input_line_pointer = p;
36759679 1157 /* Ahh - it's a motorola style psuedo op. */
252b5132
RH		 1158 mote_pseudo_table[opcode->m_opnum].poc_handler
1159 (mote_pseudo_table[opcode->m_opnum].poc_val);
1160 input_line_pointer = old;
1161 *old = 0;
1162
1163 return;
1164 }
1165
1166 if (flag_mri && opcode->m_opnum == 0)
1167 {
1168 /* In MRI mode, random garbage is allowed after an instruction
1169 which accepts no operands. */
1170 the_ins.args = opcode->m_operands;
1171 the_ins.numargs = opcode->m_opnum;
1172 the_ins.numo = opcode->m_codenum;
1173 the_ins.opcode[0] = getone (opcode);
1174 the_ins.opcode[1] = gettwo (opcode);
1175 return;
1176 }
1177
1178 for (opP = &the_ins.operands[0]; *p; opP++)
1179 {
1180 p = crack_operand (p, opP);
1181
1182 if (opP->error)
1183 {
1184 the_ins.error = opP->error;
1185 return;
1186 }
1187 }
1188
1189 opsfound = opP - &the_ins.operands[0];
1190
1191 /* This ugly hack is to support the floating pt opcodes in their
1192 standard form. Essentially, we fake a first enty of type COP#1 */
1193 if (opcode->m_operands[0] == 'I')
1194 {
1195 int n;
1196
1197 for (n = opsfound; n > 0; --n)
1198 the_ins.operands[n] = the_ins.operands[n - 1];
1199
31302357 1200 memset (&the_ins.operands[0], '\0', sizeof (the_ins.operands[0]));
252b5132
RH		 1201 the_ins.operands[0].mode = CONTROL;
1202 the_ins.operands[0].reg = m68k_float_copnum;
1203 opsfound++;
1204 }
1205
36759679 1206 /* We've got the operands. Find an opcode that'll accept them. */
252b5132
RH		 1207 for (losing = 0;;)
1208 {
1209 /* If we didn't get the right number of ops, or we have no
92774660 1210 common model with this pattern then reject this pattern. */
252b5132
RH		 1211
1212 ok_arch |= opcode->m_arch;
1213 if (opsfound != opcode->m_opnum
1214 || ((opcode->m_arch & current_architecture) == 0))
1215 ++losing;
1216 else
1217 {
03b13e59
NC		 1218 int i;
1219
1220 /* Make a copy of the operands of this insn so that
1221 we can modify them safely, should we want to. */
1222 assert (opsfound <= (int) ARRAY_SIZE (operands_backup));
1223 for (i = 0; i < opsfound; i++)
1224 operands_backup[i] = the_ins.operands[i];
1225
1226 for (s = opcode->m_operands, opP = &operands_backup[0];
252b5132
RH		 1227 *s && !losing;
1228 s += 2, opP++)
1229 {
1230 /* Warning: this switch is huge! */
1231 /* I've tried to organize the cases into this order:
1232 non-alpha first, then alpha by letter. Lower-case
1233 goes directly before uppercase counterpart. */
1234 /* Code with multiple case ...: gets sorted by the lowest
1235 case ... it belongs to. I hope this makes sense. */
1236 switch (*s)
1237 {
1238 case '!':
1239 switch (opP->mode)
1240 {
1241 case IMMED:
1242 case DREG:
1243 case AREG:
1244 case FPREG:
1245 case CONTROL:
1246 case AINC:
1247 case ADEC:
1248 case REGLST:
1249 losing++;
1250 break;
1251 default:
1252 break;
1253 }
1254 break;
1255
1256 case '<':
1257 switch (opP->mode)
1258 {
1259 case DREG:
1260 case AREG:
1261 case FPREG:
1262 case CONTROL:
1263 case IMMED:
1264 case ADEC:
1265 case REGLST:
1266 losing++;
1267 break;
1268 default:
1269 break;
1270 }
1271 break;
1272
1273 case '>':
1274 switch (opP->mode)
1275 {
1276 case DREG:
1277 case AREG:
1278 case FPREG:
1279 case CONTROL:
1280 case IMMED:
1281 case AINC:
1282 case REGLST:
1283 losing++;
1284 break;
1285 case ABSL:
1286 break;
1287 default:
1288 if (opP->reg == PC
1289 || opP->reg == ZPC)
1290 losing++;
1291 break;
1292 }
1293 break;
1294
1295 case 'm':
1296 switch (opP->mode)
1297 {
1298 case DREG:
1299 case AREG:
1300 case AINDR:
1301 case AINC:
1302 case ADEC:
1303 break;
1304 default:
1305 losing++;
1306 }
8a104df9 1307 break;
252b5132
RH		 1308
1309 case 'n':
1310 switch (opP->mode)
1311 {
1312 case DISP:
1313 break;
1314 default:
1315 losing++;
1316 }
8a104df9 1317 break;
252b5132
RH		 1318
1319 case 'o':
1320 switch (opP->mode)
1321 {
1322 case BASE:
1323 case ABSL:
1324 case IMMED:
1325 break;
1326 default:
1327 losing++;
1328 }
8a104df9 1329 break;
252b5132
RH		 1330
1331 case 'p':
1332 switch (opP->mode)
1333 {
1334 case DREG:
1335 case AREG:
1336 case AINDR:
1337 case AINC:
1338 case ADEC:
1339 break;
1340 case DISP:
1341 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1342 losing++;
252b5132
RH		 1343 break;
1344 default:
1345 losing++;
1346 }
8a104df9 1347 break;
252b5132
RH		 1348
1349 case 'q':
1350 switch (opP->mode)
1351 {
1352 case DREG:
1353 case AINDR:
1354 case AINC:
1355 case ADEC:
1356 break;
1357 case DISP:
1358 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1359 losing++;
252b5132
RH		 1360 break;
1361 default:
1362 losing++;
1363 break;
1364 }
8a104df9 1365 break;
252b5132
RH		 1366
1367 case 'v':
1368 switch (opP->mode)
1369 {
1370 case DREG:
1371 case AINDR:
1372 case AINC:
1373 case ADEC:
1374 case ABSL:
1375 break;
1376 case DISP:
1377 if (opP->reg == PC || opP->reg == ZPC)
8a104df9 1378 losing++;
252b5132
RH		 1379 break;
1380 default:
1381 losing++;
1382 break;
1383 }
1384 break;
1385
1386 case '#':
1387 if (opP->mode != IMMED)
1388 losing++;
1389 else if (s[1] == 'b'
1390 && ! isvar (&opP->disp)
1391 && (opP->disp.exp.X_op != O_constant
1392 || ! isbyte (opP->disp.exp.X_add_number)))
1393 losing++;
1394 else if (s[1] == 'B'
1395 && ! isvar (&opP->disp)
1396 && (opP->disp.exp.X_op != O_constant
1397 || ! issbyte (opP->disp.exp.X_add_number)))
1398 losing++;
1399 else if (s[1] == 'w'
1400 && ! isvar (&opP->disp)
1401 && (opP->disp.exp.X_op != O_constant
1402 || ! isword (opP->disp.exp.X_add_number)))
1403 losing++;
1404 else if (s[1] == 'W'
1405 && ! isvar (&opP->disp)
1406 && (opP->disp.exp.X_op != O_constant
1407 || ! issword (opP->disp.exp.X_add_number)))
1408 losing++;
1409 break;
1410
1411 case '^':
1412 case 'T':
1413 if (opP->mode != IMMED)
1414 losing++;
1415 break;
1416
1417 case '$':
1418 if (opP->mode == AREG
1419 || opP->mode == CONTROL
1420 || opP->mode == FPREG
1421 || opP->mode == IMMED
1422 || opP->mode == REGLST
1423 || (opP->mode != ABSL
1424 && (opP->reg == PC
1425 || opP->reg == ZPC)))
1426 losing++;
1427 break;
1428
1429 case '%':
1430 if (opP->mode == CONTROL
1431 || opP->mode == FPREG
1432 || opP->mode == REGLST
1433 || opP->mode == IMMED
1434 || (opP->mode != ABSL
1435 && (opP->reg == PC
1436 || opP->reg == ZPC)))
1437 losing++;
1438 break;
1439
1440 case '&':
1441 switch (opP->mode)
1442 {
1443 case DREG:
1444 case AREG:
1445 case FPREG:
1446 case CONTROL:
1447 case IMMED:
1448 case AINC:
1449 case ADEC:
1450 case REGLST:
1451 losing++;
1452 break;
1453 case ABSL:
1454 break;
1455 default:
1456 if (opP->reg == PC
1457 || opP->reg == ZPC)
1458 losing++;
1459 break;
1460 }
1461 break;
1462
1463 case '*':
1464 if (opP->mode == CONTROL
1465 || opP->mode == FPREG
1466 || opP->mode == REGLST)
1467 losing++;
1468 break;
1469
1470 case '+':
1471 if (opP->mode != AINC)
1472 losing++;
1473 break;
1474
1475 case '-':
1476 if (opP->mode != ADEC)
1477 losing++;
1478 break;
1479
1480 case '/':
1481 switch (opP->mode)
1482 {
1483 case AREG:
1484 case CONTROL:
1485 case FPREG:
1486 case AINC:
1487 case ADEC:
1488 case IMMED:
1489 case REGLST:
1490 losing++;
1491 break;
1492 default:
1493 break;
1494 }
1495 break;
1496
1497 case ';':
1498 switch (opP->mode)
1499 {
1500 case AREG:
1501 case CONTROL:
1502 case FPREG:
1503 case REGLST:
1504 losing++;
1505 break;
1506 default:
1507 break;
1508 }
1509 break;
1510
1511 case '?':
1512 switch (opP->mode)
1513 {
1514 case AREG:
1515 case CONTROL:
1516 case FPREG:
1517 case AINC:
1518 case ADEC:
1519 case IMMED:
1520 case REGLST:
1521 losing++;
1522 break;
1523 case ABSL:
1524 break;
1525 default:
1526 if (opP->reg == PC || opP->reg == ZPC)
1527 losing++;
1528 break;
1529 }
1530 break;
1531
1532 case '@':
1533 switch (opP->mode)
1534 {
1535 case AREG:
1536 case CONTROL:
1537 case FPREG:
1538 case IMMED:
1539 case REGLST:
1540 losing++;
1541 break;
1542 default:
1543 break;
1544 }
1545 break;
1546
1547 case '~': /* For now! (JF FOO is this right?) */
1548 switch (opP->mode)
1549 {
1550 case DREG:
1551 case AREG:
1552 case CONTROL:
1553 case FPREG:
1554 case IMMED:
1555 case REGLST:
1556 losing++;
1557 break;
1558 case ABSL:
1559 break;
1560 default:
1561 if (opP->reg == PC
1562 || opP->reg == ZPC)
1563 losing++;
1564 break;
1565 }
1566 break;
1567
1568 case '3':
1569 if (opP->mode != CONTROL
1570 || (opP->reg != TT0 && opP->reg != TT1))
1571 losing++;
1572 break;
1573
1574 case 'A':
1575 if (opP->mode != AREG)
1576 losing++;
1577 break;
1578
1579 case 'a':
1580 if (opP->mode != AINDR)
1581 ++losing;
1582 break;
1583
fd99574b
NC		 1584 case '4':
1585 if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC
1586 && (opP->mode != DISP
1587 || opP->reg < ADDR0
1588 || opP->reg > ADDR7))
1589 ++losing;
1590 break;
1591
252b5132
RH		 1592 case 'B': /* FOO */
1593 if (opP->mode != ABSL
1594 || (flag_long_jumps
1595 && strncmp (instring, "jbsr", 4) == 0))
1596 losing++;
1597 break;
1598
3e602632
NC		 1599 case 'b':
1600 switch (opP->mode)
1601 {
1602 case IMMED:
1603 case ABSL:
1604 case AREG:
1605 case FPREG:
1606 case CONTROL:
1607 case POST:
1608 case PRE:
1609 case REGLST:
1610 losing++;
1611 break;
1612 default:
1613 break;
1614 }
1615 break;
1616
252b5132
RH		 1617 case 'C':
1618 if (opP->mode != CONTROL || opP->reg != CCR)
1619 losing++;
1620 break;
1621
1622 case 'd':
1623 if (opP->mode != DISP
1624 || opP->reg < ADDR0
1625 || opP->reg > ADDR7)
1626 losing++;
1627 break;
1628
1629 case 'D':
1630 if (opP->mode != DREG)
1631 losing++;
1632 break;
1633
6da466c7
ILT		 1634 case 'E':
1635 if (opP->reg != ACC)
1636 losing++;
1637 break;
1638
fd99574b
NC		 1639 case 'e':
1640 if (opP->reg != ACC && opP->reg != ACC1
1641 && opP->reg != ACC2 && opP->reg != ACC3)
1642 losing++;
1643 break;
1644
252b5132
RH		 1645 case 'F':
1646 if (opP->mode != FPREG)
1647 losing++;
1648 break;
1649
6da466c7
ILT		 1650 case 'G':
1651 if (opP->reg != MACSR)
1652 losing++;
1653 break;
1654
fd99574b
NC		 1655 case 'g':
1656 if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23)
1657 losing++;
1658 break;
1659
6da466c7
ILT		 1660 case 'H':
1661 if (opP->reg != MASK)
1662 losing++;
1663 break;
1664
252b5132
RH		 1665 case 'I':
1666 if (opP->mode != CONTROL
1667 || opP->reg < COP0
1668 || opP->reg > COP7)
1669 losing++;
1670 break;
1671
fd99574b
NC		 1672 case 'i':
1673 if (opP->mode != LSH && opP->mode != RSH)
1674 losing++;
1675 break;
1676
252b5132
RH		 1677 case 'J':
1678 if (opP->mode != CONTROL
1679 || opP->reg < USP
0b2e31dc
NS		 1680 || opP->reg > last_movec_reg
1681 || !control_regs)
252b5132
RH		 1682 losing++;
1683 else
1684 {
1685 const enum m68k_register *rp;
0b2e31dc 1686
252b5132
RH		 1687 for (rp = control_regs; *rp; rp++)
1688 if (*rp == opP->reg)
1689 break;
1690 if (*rp == 0)
1691 losing++;
1692 }
1693 break;
1694
1695 case 'k':
1696 if (opP->mode != IMMED)
1697 losing++;
1698 break;
1699
1700 case 'l':
1701 case 'L':
1702 if (opP->mode == DREG
1703 || opP->mode == AREG
1704 || opP->mode == FPREG)
1705 {
1706 if (s[1] == '8')
1707 losing++;
1708 else
1709 {
1710 switch (opP->mode)
1711 {
1712 case DREG:
1713 opP->mask = 1 << (opP->reg - DATA0);
1714 break;
1715 case AREG:
1716 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1717 break;
1718 case FPREG:
1719 opP->mask = 1 << (opP->reg - FP0 + 16);
1720 break;
1721 default:
1722 abort ();
1723 }
1724 opP->mode = REGLST;
1725 }
1726 }
1727 else if (opP->mode == CONTROL)
1728 {
1729 if (s[1] != '8')
1730 losing++;
1731 else
1732 {
1733 switch (opP->reg)
1734 {
1735 case FPI:
1736 opP->mask = 1 << 24;
1737 break;
1738 case FPS:
1739 opP->mask = 1 << 25;
1740 break;
1741 case FPC:
1742 opP->mask = 1 << 26;
1743 break;
1744 default:
1745 losing++;
1746 break;
1747 }
1748 opP->mode = REGLST;
1749 }
1750 }
1751 else if (opP->mode != REGLST)
1752 losing++;
1753 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1754 losing++;
1755 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1756 losing++;
1757 break;
1758
1759 case 'M':
1760 if (opP->mode != IMMED)
1761 losing++;
1762 else if (opP->disp.exp.X_op != O_constant
1763 || ! issbyte (opP->disp.exp.X_add_number))
1764 losing++;
1765 else if (! m68k_quick
1766 && instring[3] != 'q'
1767 && instring[4] != 'q')
1768 losing++;
1769 break;
1770
1771 case 'O':
1772 if (opP->mode != DREG
1773 && opP->mode != IMMED
1774 && opP->mode != ABSL)
1775 losing++;
1776 break;
1777
1778 case 'Q':
1779 if (opP->mode != IMMED)
1780 losing++;
1781 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1782 || TRUNC (opP->disp.exp.X_add_number) - 1 > 7)
252b5132
RH		 1783 losing++;
1784 else if (! m68k_quick
1785 && (strncmp (instring, "add", 3) == 0
1786 || strncmp (instring, "sub", 3) == 0)
1787 && instring[3] != 'q')
1788 losing++;
1789 break;
1790
1791 case 'R':
1792 if (opP->mode != DREG && opP->mode != AREG)
1793 losing++;
1794 break;
1795
1796 case 'r':
1797 if (opP->mode != AINDR
1798 && (opP->mode != BASE
1799 || (opP->reg != 0
1800 && opP->reg != ZADDR0)
1801 || opP->disp.exp.X_op != O_absent
1802 || ((opP->index.reg < DATA0
1803 || opP->index.reg > DATA7)
1804 && (opP->index.reg < ADDR0
1805 || opP->index.reg > ADDR7))
1806 || opP->index.size != SIZE_UNSPEC
1807 || opP->index.scale != 1))
1808 losing++;
1809 break;
1810
1811 case 's':
1812 if (opP->mode != CONTROL
1813 || ! (opP->reg == FPI
1814 || opP->reg == FPS
1815 || opP->reg == FPC))
1816 losing++;
1817 break;
1818
1819 case 'S':
1820 if (opP->mode != CONTROL || opP->reg != SR)
1821 losing++;
1822 break;
1823
1824 case 't':
1825 if (opP->mode != IMMED)
1826 losing++;
1827 else if (opP->disp.exp.X_op != O_constant
bd17c2c3 1828 || TRUNC (opP->disp.exp.X_add_number) > 7)
252b5132
RH		 1829 losing++;
1830 break;
1831
1832 case 'U':
1833 if (opP->mode != CONTROL || opP->reg != USP)
1834 losing++;
1835 break;
1836
3e602632
NC		 1837 case 'x':
1838 if (opP->mode != IMMED)
1839 losing++;
1840 else if (opP->disp.exp.X_op != O_constant
bd17c2c3
AM		 1841 || (TRUNC (opP->disp.exp.X_add_number) != 0xffffffff
1842 && TRUNC (opP->disp.exp.X_add_number) - 1 > 6))
3e602632
NC		 1843 losing++;
1844 break;
1845
252b5132
RH		 1846 /* JF these are out of order. We could put them
1847 in order if we were willing to put up with
1848 bunches of #ifdef m68851s in the code.
1849
1850 Don't forget that you need these operands
1851 to use 68030 MMU instructions. */
1852#ifndef NO_68851
36759679 1853 /* Memory addressing mode used by pflushr. */
252b5132
RH		 1854 case '|':
1855 if (opP->mode == CONTROL
1856 || opP->mode == FPREG
1857 || opP->mode == DREG
1858 || opP->mode == AREG
1859 || opP->mode == REGLST)
1860 losing++;
1861 /* We should accept immediate operands, but they
1862 supposedly have to be quad word, and we don't
1863 handle that. I would like to see what a Motorola
1864 assembler does before doing something here. */
1865 if (opP->mode == IMMED)
1866 losing++;
1867 break;
1868
1869 case 'f':
1870 if (opP->mode != CONTROL
1871 || (opP->reg != SFC && opP->reg != DFC))
1872 losing++;
1873 break;
1874
1875 case '0':
1876 if (opP->mode != CONTROL || opP->reg != TC)
1877 losing++;
1878 break;
1879
1880 case '1':
1881 if (opP->mode != CONTROL || opP->reg != AC)
1882 losing++;
1883 break;
1884
1885 case '2':
1886 if (opP->mode != CONTROL
1887 || (opP->reg != CAL
1888 && opP->reg != VAL
1889 && opP->reg != SCC))
1890 losing++;
1891 break;
1892
1893 case 'V':
1894 if (opP->mode != CONTROL
1895 || opP->reg != VAL)
1896 losing++;
1897 break;
1898
1899 case 'W':
1900 if (opP->mode != CONTROL
1901 || (opP->reg != DRP
1902 && opP->reg != SRP
1903 && opP->reg != CRP))
1904 losing++;
1905 break;
1906
3e602632
NC		 1907 case 'w':
1908 switch (opP->mode)
1909 {
1910 case IMMED:
1911 case ABSL:
1912 case AREG:
1913 case DREG:
1914 case FPREG:
1915 case CONTROL:
1916 case POST:
1917 case PRE:
1918 case REGLST:
1919 losing++;
1920 break;
1921 default:
1922 break;
1923 }
1924 break;
1925
252b5132
RH		 1926 case 'X':
1927 if (opP->mode != CONTROL
1928 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1929 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1930 losing++;
1931 break;
1932
1933 case 'Y':
1934 if (opP->mode != CONTROL || opP->reg != PSR)
1935 losing++;
1936 break;
1937
1938 case 'Z':
1939 if (opP->mode != CONTROL || opP->reg != PCSR)
1940 losing++;
1941 break;
1942#endif
1943 case 'c':
1944 if (opP->mode != CONTROL
1945 || (opP->reg != NC
1946 && opP->reg != IC
1947 && opP->reg != DC
1948 && opP->reg != BC))
36759679 1949 losing++;
252b5132
RH		 1950 break;
1951
1952 case '_':
1953 if (opP->mode != ABSL)
1954 ++losing;
1955 break;
1956
6da466c7
ILT		 1957 case 'u':
1958 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1959 losing++;
1960 /* FIXME: kludge instead of fixing parser:
1961 upper/lower registers are *not* CONTROL
92774660 1962 registers, but ordinary ones. */
6da466c7
ILT		 1963 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1964 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1965 opP->mode = DREG;
1966 else
1967 opP->mode = AREG;
1968 break;
1969
3e602632
NC		 1970 case 'y':
1971 if (!(opP->mode == AINDR
31302357
AS		 1972 || (opP->mode == DISP
1973 && !(opP->reg == PC || opP->reg == ZPC))))
3e602632
NC		 1974 losing++;
1975 break;
1976
1977 case 'z':
1978 if (!(opP->mode == AINDR || opP->mode == DISP))
1979 losing++;
1980 break;
1981
252b5132
RH		 1982 default:
1983 abort ();
36759679 1984 }
252b5132
RH		 1985
1986 if (losing)
1987 break;
36759679 1988 }
03b13e59
NC		 1989
1990 /* Since we have found the correct instruction, copy
1991 in the modifications that we may have made. */
1992 if (!losing)
1993 for (i = 0; i < opsfound; i++)
1994 the_ins.operands[i] = operands_backup[i];
36759679 1995 }
252b5132
RH		 1996
1997 if (!losing)
36759679 1998 break;
252b5132
RH		 1999
2000 opcode = opcode->m_next;
2001
2002 if (!opcode)
2003 {
2004 if (ok_arch
2005 && !(ok_arch & current_architecture))
2006 {
6d89cc8f
NS		 2007 const struct m68k_cpu *cpu;
2008 int any = 0;
2009 size_t space = 400;
2010 char *buf = xmalloc (space + 1);
2011 size_t len;
2012 int paren = 1;
2013
2014 the_ins.error = buf;
2015 /* Make sure there's a NUL at the end of the buffer -- strncpy
2016 won't write one when it runs out of buffer */
2017 buf[space] = 0;
2018#define APPEND(STRING) \
2019 (strncpy (buf, STRING, space), len = strlen (buf), buf += len, space -= len)
2020
2021 APPEND (_("invalid instruction for this architecture; needs "));
252b5132
RH		 2022 switch (ok_arch)
2023 {
6b6e92f4 2024 case mcfisa_a:
6d89cc8f 2025 APPEND (_("ColdFire ISA_A"));
6b6e92f4
NC		 2026 break;
2027 case mcfhwdiv:
6d89cc8f 2028 APPEND (_("ColdFire hardware divide"));
6b6e92f4
NC		 2029 break;
2030 case mcfisa_aa:
6d89cc8f 2031 APPEND (_("ColdFire ISA_A+"));
6b6e92f4
NC		 2032 break;
2033 case mcfisa_b:
6d89cc8f 2034 APPEND (_("ColdFire ISA_B"));
6b6e92f4 2035 break;
3e602632 2036 case cfloat:
6d89cc8f 2037 APPEND (_("ColdFire fpu"));
3e602632 2038 break;
252b5132 2039 case mfloat:
6d89cc8f 2040 APPEND (_("M68K fpu"));
252b5132
RH		 2041 break;
2042 case mmmu:
6d89cc8f 2043 APPEND (_("M68K mmu"));
252b5132
RH		 2044 break;
2045 case m68020up:
6d89cc8f 2046 APPEND (_("68020 or higher"));
252b5132
RH		 2047 break;
2048 case m68000up:
6d89cc8f 2049 APPEND (_("68000 or higher"));
252b5132
RH		 2050 break;
2051 case m68010up:
6d89cc8f 2052 APPEND (_("68010 or higher"));
252b5132
RH		 2053 break;
2054 default:
6d89cc8f
NS		 2055 paren = 0;
2056 }
2057 if (paren)
2058 APPEND (" (");
6b6e92f4 2059
6d89cc8f
NS		 2060 for (cpu = m68k_cpus; cpu->name; cpu++)
2061 if (!cpu->alias && (cpu->arch & ok_arch))
2062 {
2063 const struct m68k_cpu *alias;
869ddf2a
NS		 2064 int seen_master = 0;
2065
6d89cc8f
NS		 2066 if (any)
2067 APPEND (", ");
2068 any = 0;
2069 APPEND (cpu->name);
869ddf2a
NS		 2070 for (alias = cpu; alias != m68k_cpus; alias--)
2071 if (alias[-1].alias >= 0)
2072 break;
2073 for (; !seen_master || alias->alias > 0; alias++)
6d89cc8f 2074 {
869ddf2a
NS		 2075 if (!alias->alias)
2076 seen_master = 1;
2077 else
2078 {
2079 if (any)
2080 APPEND (", ");
2081 else
2082 APPEND (" [");
2083 APPEND (alias->name);
2084 any = 1;
2085 }
6d89cc8f 2086 }
869ddf2a
NS		 2087 if (any)
2088 APPEND ("]");
6d89cc8f 2089 any = 1;
252b5132 2090 }
6d89cc8f
NS		 2091 if (paren)
2092 APPEND (")");
2093#undef APPEND
2094 if (!space)
2095 {
2096 /* we ran out of space, so replace the end of the list
2097 with ellipsis. */
2098 buf -= 4;
2099 while (*buf != ' ')
2100 buf--;
2101 strcpy (buf, " ...");
252b5132 2102 }
252b5132
RH		 2103 }
2104 else
2105 the_ins.error = _("operands mismatch");
2106 return;
36759679 2107 }
252b5132
RH		 2108
2109 losing = 0;
2110 }
2111
36759679 2112 /* Now assemble it. */
252b5132
RH		 2113 the_ins.args = opcode->m_operands;
2114 the_ins.numargs = opcode->m_opnum;
2115 the_ins.numo = opcode->m_codenum;
2116 the_ins.opcode[0] = getone (opcode);
2117 the_ins.opcode[1] = gettwo (opcode);
2118
2119 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
2120 {
2121 /* This switch is a doozy.
31302357 2122 Watch the first step; its a big one! */
252b5132
RH		 2123 switch (s[0])
2124 {
2125
2126 case '*':
2127 case '~':
2128 case '%':
2129 case ';':
2130 case '@':
2131 case '!':
2132 case '&':
2133 case '$':
2134 case '?':
2135 case '/':
2136 case '<':
2137 case '>':
3e602632 2138 case 'b':
252b5132
RH		 2139 case 'm':
2140 case 'n':
2141 case 'o':
2142 case 'p':
2143 case 'q':
2144 case 'v':
3e602632
NC		 2145 case 'w':
2146 case 'y':
2147 case 'z':
fd99574b 2148 case '4':
252b5132
RH		 2149#ifndef NO_68851
2150 case '|':
2151#endif
2152 switch (opP->mode)
2153 {
2154 case IMMED:
2155 tmpreg = 0x3c; /* 7.4 */
2156 if (strchr ("bwl", s[1]))
3e602632 2157 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2158 else
2159 nextword = get_num (&opP->disp, 0);
2160 if (isvar (&opP->disp))
2161 add_fix (s[1], &opP->disp, 0, 0);
2162 switch (s[1])
2163 {
2164 case 'b':
2165 if (!isbyte (nextword))
2166 opP->error = _("operand out of range");
2167 addword (nextword);
2168 baseo = 0;
2169 break;
2170 case 'w':
2171 if (!isword (nextword))
2172 opP->error = _("operand out of range");
2173 addword (nextword);
2174 baseo = 0;
2175 break;
2176 case 'W':
2177 if (!issword (nextword))
2178 opP->error = _("operand out of range");
2179 addword (nextword);
2180 baseo = 0;
2181 break;
2182 case 'l':
2183 addword (nextword >> 16);
2184 addword (nextword);
2185 baseo = 0;
2186 break;
2187
2188 case 'f':
2189 baseo = 2;
2190 outro = 8;
2191 break;
2192 case 'F':
2193 baseo = 4;
2194 outro = 11;
2195 break;
2196 case 'x':
2197 baseo = 6;
2198 outro = 15;
2199 break;
2200 case 'p':
2201 baseo = 6;
2202 outro = -1;
2203 break;
2204 default:
2205 abort ();
2206 }
2207 if (!baseo)
2208 break;
2209
36759679 2210 /* We gotta put out some float. */
252b5132
RH		 2211 if (op (&opP->disp) != O_big)
2212 {
2213 valueT val;
2214 int gencnt;
2215
2216 /* Can other cases happen here? */
2217 if (op (&opP->disp) != O_constant)
2218 abort ();
2219
2220 val = (valueT) offs (&opP->disp);
2221 gencnt = 0;
2222 do
2223 {
2224 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2225 val >>= LITTLENUM_NUMBER_OF_BITS;
2226 ++gencnt;
2227 }
2228 while (val != 0);
2229 offs (&opP->disp) = gencnt;
2230 }
2231 if (offs (&opP->disp) > 0)
2232 {
2233 if (offs (&opP->disp) > baseo)
2234 {
2235 as_warn (_("Bignum too big for %c format; truncated"),
2236 s[1]);
2237 offs (&opP->disp) = baseo;
2238 }
2239 baseo -= offs (&opP->disp);
2240 while (baseo--)
2241 addword (0);
2242 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2243 offs (&opP->disp)--;
2244 --wordp)
2245 addword (*wordp);
2246 break;
2247 }
2248 gen_to_words (words, baseo, (long) outro);
2249 for (wordp = words; baseo--; wordp++)
2250 addword (*wordp);
2251 break;
2252 case DREG:
2253 tmpreg = opP->reg - DATA; /* 0.dreg */
2254 break;
2255 case AREG:
2256 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2257 break;
2258 case AINDR:
2259 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2260 break;
2261 case ADEC:
2262 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2263 break;
2264 case AINC:
2265 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2266 break;
2267 case DISP:
2268
3e602632 2269 nextword = get_num (&opP->disp, 90);
252b5132 2270
580b9172
NC		 2271 /* Convert mode 5 addressing with a zero offset into
2272 mode 2 addressing to reduce the instruction size by a
2273 word. */
2274 if (! isvar (&opP->disp)
2275 && (nextword == 0)
2276 && (opP->disp.size == SIZE_UNSPEC)
2277 && (opP->reg >= ADDR0)
2278 && (opP->reg <= ADDR7))
2279 {
2280 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2281 break;
2282 }
2283
252b5132
RH		 2284 if (opP->reg == PC
2285 && ! isvar (&opP->disp)
2286 && m68k_abspcadd)
2287 {
2288 opP->disp.exp.X_op = O_symbol;
252b5132
RH		 2289 opP->disp.exp.X_add_symbol =
2290 section_symbol (absolute_section);
252b5132
RH		 2291 }
2292
36759679 2293 /* Force into index mode. Hope this works. */
252b5132
RH		 2294
2295 /* We do the first bit for 32-bit displacements, and the
2296 second bit for 16 bit ones. It is possible that we
2297 should make the default be WORD instead of LONG, but
2298 I think that'd break GCC, so we put up with a little
2299 inefficiency for the sake of working output. */
2300
2301 if (!issword (nextword)
2302 || (isvar (&opP->disp)
2303 && ((opP->disp.size == SIZE_UNSPEC
2304 && flag_short_refs == 0
2305 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2306 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2307 || opP->disp.size == SIZE_LONG)))
2308 {
2309 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2310 || arch_coldfire_p (current_architecture))
252b5132
RH		 2311 opP->error =
2312 _("displacement too large for this architecture; needs 68020 or higher");
2313 if (opP->reg == PC)
2314 tmpreg = 0x3B; /* 7.3 */
2315 else
2316 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2317 if (isvar (&opP->disp))
2318 {
2319 if (opP->reg == PC)
2320 {
2321 if (opP->disp.size == SIZE_LONG
2322#ifdef OBJ_ELF
2323 /* If the displacement needs pic
2324 relocation it cannot be relaxed. */
2325 || opP->disp.pic_reloc != pic_none
2326#endif
2327 )
2328 {
2329 addword (0x0170);
2330 add_fix ('l', &opP->disp, 1, 2);
2331 }
2332 else
2333 {
2334 add_frag (adds (&opP->disp),
bd17c2c3 2335 SEXT (offs (&opP->disp)),
151337e8 2336 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2337 break;
2338 }
2339 }
2340 else
2341 {
2342 addword (0x0170);
2343 add_fix ('l', &opP->disp, 0, 0);
2344 }
2345 }
2346 else
2347 addword (0x0170);
2348 addword (nextword >> 16);
2349 }
2350 else
2351 {
2352 if (opP->reg == PC)
2353 tmpreg = 0x3A; /* 7.2 */
2354 else
2355 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2356
2357 if (isvar (&opP->disp))
2358 {
2359 if (opP->reg == PC)
2360 {
2361 add_fix ('w', &opP->disp, 1, 0);
2362 }
2363 else
2364 add_fix ('w', &opP->disp, 0, 0);
2365 }
2366 }
2367 addword (nextword);
2368 break;
2369
2370 case POST:
2371 case PRE:
2372 case BASE:
2373 nextword = 0;
3e602632 2374 baseo = get_num (&opP->disp, 90);
252b5132 2375 if (opP->mode == POST || opP->mode == PRE)
3e602632 2376 outro = get_num (&opP->odisp, 90);
252b5132
RH		 2377 /* Figure out the `addressing mode'.
2378 Also turn on the BASE_DISABLE bit, if needed. */
2379 if (opP->reg == PC || opP->reg == ZPC)
2380 {
2381 tmpreg = 0x3b; /* 7.3 */
2382 if (opP->reg == ZPC)
2383 nextword |= 0x80;
2384 }
2385 else if (opP->reg == 0)
2386 {
2387 nextword |= 0x80;
2388 tmpreg = 0x30; /* 6.garbage */
2389 }
2390 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2391 {
2392 nextword |= 0x80;
2393 tmpreg = 0x30 + opP->reg - ZADDR0;
2394 }
2395 else
2396 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2397
2398 siz1 = opP->disp.size;
2399 if (opP->mode == POST || opP->mode == PRE)
2400 siz2 = opP->odisp.size;
2401 else
2402 siz2 = SIZE_UNSPEC;
2403
36759679 2404 /* Index register stuff. */
252b5132
RH		 2405 if (opP->index.reg != 0
2406 && opP->index.reg >= DATA
2407 && opP->index.reg <= ADDR7)
2408 {
2409 nextword |= (opP->index.reg - DATA) << 12;
2410
2411 if (opP->index.size == SIZE_LONG
2412 || (opP->index.size == SIZE_UNSPEC
2413 && m68k_index_width_default == SIZE_LONG))
2414 nextword |= 0x800;
2415
92774660 2416 if ((opP->index.scale != 1
252b5132 2417 && cpu_of_arch (current_architecture) < m68020)
92774660 2418 || (opP->index.scale == 8
3e602632 2419 && (arch_coldfire_p (current_architecture)
6b6e92f4 2420 && !arch_coldfire_fpu (current_architecture))))
252b5132
RH		 2421 {
2422 opP->error =
2423 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2424 }
2425
6da466c7
ILT		 2426 if (arch_coldfire_p (current_architecture)
2427 && opP->index.size == SIZE_WORD)
2428 opP->error = _("invalid index size for coldfire");
2429
252b5132
RH		 2430 switch (opP->index.scale)
2431 {
2432 case 1:
2433 break;
2434 case 2:
2435 nextword |= 0x200;
2436 break;
2437 case 4:
2438 nextword |= 0x400;
2439 break;
2440 case 8:
2441 nextword |= 0x600;
2442 break;
2443 default:
2444 abort ();
2445 }
2446 /* IF its simple,
2447 GET US OUT OF HERE! */
2448
2449 /* Must be INDEX, with an index register. Address
2450 register cannot be ZERO-PC, and either :b was
2451 forced, or we know it will fit. For a 68000 or
2452 68010, force this mode anyways, because the
2453 larger modes aren't supported. */
2454 if (opP->mode == BASE
2455 && ((opP->reg >= ADDR0
2456 && opP->reg <= ADDR7)
2457 || opP->reg == PC))
2458 {
2459 if (siz1 == SIZE_BYTE
2460 || cpu_of_arch (current_architecture) < m68020
6da466c7 2461 || arch_coldfire_p (current_architecture)
252b5132
RH		 2462 || (siz1 == SIZE_UNSPEC
2463 && ! isvar (&opP->disp)
2464 && issbyte (baseo)))
2465 {
2466 nextword += baseo & 0xff;
2467 addword (nextword);
2468 if (isvar (&opP->disp))
2469 {
2470 /* Do a byte relocation. If it doesn't
2471 fit (possible on m68000) let the
2472 fixup processing complain later. */
2473 if (opP->reg == PC)
2474 add_fix ('B', &opP->disp, 1, 1);
2475 else
2476 add_fix ('B', &opP->disp, 0, 0);
2477 }
2478 else if (siz1 != SIZE_BYTE)
2479 {
2480 if (siz1 != SIZE_UNSPEC)
2481 as_warn (_("Forcing byte displacement"));
2482 if (! issbyte (baseo))
2483 opP->error = _("byte displacement out of range");
2484 }
2485
2486 break;
2487 }
2488 else if (siz1 == SIZE_UNSPEC
2489 && opP->reg == PC
2490 && isvar (&opP->disp)
2491 && subs (&opP->disp) == NULL
2492#ifdef OBJ_ELF
2493 /* If the displacement needs pic
2494 relocation it cannot be relaxed. */
2495 && opP->disp.pic_reloc == pic_none
2496#endif
2497 )
2498 {
2499 /* The code in md_convert_frag_1 needs to be
2500 able to adjust nextword. Call frag_grow
2501 to ensure that we have enough space in
2502 the frag obstack to make all the bytes
2503 contiguous. */
2504 frag_grow (14);
8a104df9
KH		 2505 nextword += baseo & 0xff;
2506 addword (nextword);
bd17c2c3
AM		 2507 add_frag (adds (&opP->disp),
2508 SEXT (offs (&opP->disp)),
8a104df9 2509 TAB (PCINDEX, SZ_UNDEF));
252b5132
RH		 2510
2511 break;
8a104df9 2512 }
252b5132
RH		 2513 }
2514 }
2515 else
2516 {
36759679 2517 nextword |= 0x40; /* No index reg. */
252b5132
RH		 2518 if (opP->index.reg >= ZDATA0
2519 && opP->index.reg <= ZDATA7)
2520 nextword |= (opP->index.reg - ZDATA0) << 12;
2521 else if (opP->index.reg >= ZADDR0
2522 || opP->index.reg <= ZADDR7)
2523 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2524 }
2525
2526 /* It isn't simple. */
2527
2528 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2529 || arch_coldfire_p (current_architecture))
252b5132
RH		 2530 opP->error =
2531 _("invalid operand mode for this architecture; needs 68020 or higher");
2532
2533 nextword |= 0x100;
2534 /* If the guy specified a width, we assume that it is
2535 wide enough. Maybe it isn't. If so, we lose. */
2536 switch (siz1)
2537 {
2538 case SIZE_UNSPEC:
2539 if (isvar (&opP->disp)
2540 ? m68k_rel32
2541 : ! issword (baseo))
2542 {
2543 siz1 = SIZE_LONG;
2544 nextword |= 0x30;
2545 }
2546 else if (! isvar (&opP->disp) && baseo == 0)
2547 nextword |= 0x10;
2548 else
2549 {
2550 nextword |= 0x20;
2551 siz1 = SIZE_WORD;
2552 }
2553 break;
2554 case SIZE_BYTE:
2555 as_warn (_(":b not permitted; defaulting to :w"));
2556 /* Fall through. */
2557 case SIZE_WORD:
2558 nextword |= 0x20;
2559 break;
2560 case SIZE_LONG:
2561 nextword |= 0x30;
2562 break;
2563 }
2564
67c1ffbe 2565 /* Figure out inner displacement stuff. */
252b5132
RH		 2566 if (opP->mode == POST || opP->mode == PRE)
2567 {
2568 if (cpu_of_arch (current_architecture) & cpu32)
2569 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2570 switch (siz2)
2571 {
2572 case SIZE_UNSPEC:
2573 if (isvar (&opP->odisp)
2574 ? m68k_rel32
2575 : ! issword (outro))
2576 {
2577 siz2 = SIZE_LONG;
2578 nextword |= 0x3;
2579 }
2580 else if (! isvar (&opP->odisp) && outro == 0)
2581 nextword |= 0x1;
2582 else
2583 {
2584 nextword |= 0x2;
2585 siz2 = SIZE_WORD;
2586 }
2587 break;
2588 case 1:
2589 as_warn (_(":b not permitted; defaulting to :w"));
2590 /* Fall through. */
2591 case 2:
2592 nextword |= 0x2;
2593 break;
2594 case 3:
2595 nextword |= 0x3;
2596 break;
2597 }
2598 if (opP->mode == POST
2599 && (nextword & 0x40) == 0)
2600 nextword |= 0x04;
2601 }
2602 addword (nextword);
2603
2604 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2605 {
2606 if (opP->reg == PC || opP->reg == ZPC)
2607 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2608 else
2609 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2610 }
2611 if (siz1 == SIZE_LONG)
2612 addword (baseo >> 16);
2613 if (siz1 != SIZE_UNSPEC)
2614 addword (baseo);
2615
2616 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2617 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2618 if (siz2 == SIZE_LONG)
2619 addword (outro >> 16);
2620 if (siz2 != SIZE_UNSPEC)
2621 addword (outro);
2622
2623 break;
2624
2625 case ABSL:
3e602632 2626 nextword = get_num (&opP->disp, 90);
252b5132
RH		 2627 switch (opP->disp.size)
2628 {
2629 default:
2630 abort ();
2631 case SIZE_UNSPEC:
2632 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2633 {
2634 tmpreg = 0x38; /* 7.0 */
2635 addword (nextword);
2636 break;
2637 }
252b5132
RH		 2638 if (isvar (&opP->disp)
2639 && !subs (&opP->disp)
2640 && adds (&opP->disp)
2641#ifdef OBJ_ELF
2642 /* If the displacement needs pic relocation it
2643 cannot be relaxed. */
2644 && opP->disp.pic_reloc == pic_none
2645#endif
252b5132
RH		 2646 && !flag_long_jumps
2647 && !strchr ("~%&$?", s[0]))
2648 {
2649 tmpreg = 0x3A; /* 7.2 */
2650 add_frag (adds (&opP->disp),
bd17c2c3 2651 SEXT (offs (&opP->disp)),
151337e8 2652 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2653 break;
2654 }
36759679 2655 /* Fall through into long. */
252b5132
RH		 2656 case SIZE_LONG:
2657 if (isvar (&opP->disp))
2658 add_fix ('l', &opP->disp, 0, 0);
2659
2660 tmpreg = 0x39;/* 7.1 mode */
2661 addword (nextword >> 16);
2662 addword (nextword);
2663 break;
2664
2665 case SIZE_BYTE:
2666 as_bad (_("unsupported byte value; use a different suffix"));
2667 /* Fall through. */
36759679
NC		 2668
2669 case SIZE_WORD:
252b5132
RH		 2670 if (isvar (&opP->disp))
2671 add_fix ('w', &opP->disp, 0, 0);
2672
2673 tmpreg = 0x38;/* 7.0 mode */
2674 addword (nextword);
2675 break;
2676 }
2677 break;
2678 case CONTROL:
2679 case FPREG:
2680 default:
2681 as_bad (_("unknown/incorrect operand"));
bc805888 2682 /* abort (); */
252b5132 2683 }
fd99574b
NC		 2684
2685 /* If s[0] is '4', then this is for the mac instructions
2686 that can have a trailing_ampersand set. If so, set 0x100
2687 bit on tmpreg so install_gen_operand can check for it and
2688 set the appropriate bit (word2, bit 5). */
2689 if (s[0] == '4')
2690 {
2691 if (opP->trailing_ampersand)
2692 tmpreg |= 0x100;
2693 }
252b5132
RH		 2694 install_gen_operand (s[1], tmpreg);
2695 break;
2696
2697 case '#':
2698 case '^':
2699 switch (s[1])
2700 { /* JF: I hate floating point! */
2701 case 'j':
2702 tmpreg = 70;
2703 break;
2704 case '8':
2705 tmpreg = 20;
2706 break;
2707 case 'C':
2708 tmpreg = 50;
2709 break;
2710 case '3':
2711 default:
3e602632 2712 tmpreg = 90;
252b5132
RH		 2713 break;
2714 }
2715 tmpreg = get_num (&opP->disp, tmpreg);
2716 if (isvar (&opP->disp))
2717 add_fix (s[1], &opP->disp, 0, 0);
2718 switch (s[1])
2719 {
2720 case 'b': /* Danger: These do no check for
2721 certain types of overflow.
2722 user beware! */
2723 if (!isbyte (tmpreg))
2724 opP->error = _("out of range");
2725 insop (tmpreg, opcode);
2726 if (isvar (&opP->disp))
2727 the_ins.reloc[the_ins.nrel - 1].n =
2728 (opcode->m_codenum) * 2 + 1;
2729 break;
2730 case 'B':
2731 if (!issbyte (tmpreg))
2732 opP->error = _("out of range");
2733 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2734 if (isvar (&opP->disp))
2735 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2736 break;
2737 case 'w':
2738 if (!isword (tmpreg))
2739 opP->error = _("out of range");
2740 insop (tmpreg, opcode);
2741 if (isvar (&opP->disp))
2742 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2743 break;
2744 case 'W':
2745 if (!issword (tmpreg))
2746 opP->error = _("out of range");
2747 insop (tmpreg, opcode);
2748 if (isvar (&opP->disp))
2749 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2750 break;
2751 case 'l':
2752 /* Because of the way insop works, we put these two out
2753 backwards. */
2754 insop (tmpreg, opcode);
2755 insop (tmpreg >> 16, opcode);
2756 if (isvar (&opP->disp))
2757 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2758 break;
2759 case '3':
2760 tmpreg &= 0xFF;
2761 case '8':
2762 case 'C':
2763 case 'j':
2764 install_operand (s[1], tmpreg);
2765 break;
2766 default:
2767 abort ();
2768 }
2769 break;
2770
2771 case '+':
2772 case '-':
2773 case 'A':
2774 case 'a':
2775 install_operand (s[1], opP->reg - ADDR);
2776 break;
2777
2778 case 'B':
3e602632 2779 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2780 switch (s[1])
2781 {
2782 case 'B':
8390138c 2783 add_fix ('B', &opP->disp, 1, -1);
252b5132
RH		 2784 break;
2785 case 'W':
2786 add_fix ('w', &opP->disp, 1, 0);
2787 addword (0);
2788 break;
2789 case 'L':
2790 long_branch:
151337e8 2791 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2792 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2793 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2794 add_fix ('l', &opP->disp, 1, 0);
2795 addword (0);
2796 addword (0);
2797 break;
2798 case 'g':
36759679 2799 if (subs (&opP->disp)) /* We can't relax it. */
252b5132
RH		 2800 goto long_branch;
2801
2802#ifdef OBJ_ELF
2803 /* If the displacement needs pic relocation it cannot be
2804 relaxed. */
2805 if (opP->disp.pic_reloc != pic_none)
2806 goto long_branch;
2807#endif
252b5132 2808 /* This could either be a symbol, or an absolute
151337e8
NC		 2809 address. If it's an absolute address, turn it into
2810 an absolute jump right here and keep it out of the
2811 relaxer. */
2812 if (adds (&opP->disp) == 0)
2813 {
2814 if (the_ins.opcode[0] == 0x6000) /* jbra */
18566f55 2815 the_ins.opcode[0] = 0x4EF9;
151337e8 2816 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
18566f55 2817 the_ins.opcode[0] = 0x4EB9;
151337e8
NC		 2818 else /* jCC */
2819 {
2820 the_ins.opcode[0] ^= 0x0100;
2821 the_ins.opcode[0] |= 0x0006;
18566f55 2822 addword (0x4EF9);
151337e8
NC		 2823 }
2824 add_fix ('l', &opP->disp, 0, 0);
2825 addword (0);
2826 addword (0);
2827 break;
2828 }
2829
2830 /* Now we know it's going into the relaxer. Now figure
2831 out which mode. We try in this order of preference:
2832 long branch, absolute jump, byte/word branches only. */
2833 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2834 add_frag (adds (&opP->disp),
2835 SEXT (offs (&opP->disp)),
151337e8
NC		 2836 TAB (BRANCHBWL, SZ_UNDEF));
2837 else if (! flag_keep_pcrel)
2838 {
2839 if ((the_ins.opcode[0] == 0x6000)
2840 || (the_ins.opcode[0] == 0x6100))
bd17c2c3
AM		 2841 add_frag (adds (&opP->disp),
2842 SEXT (offs (&opP->disp)),
151337e8
NC		 2843 TAB (BRABSJUNC, SZ_UNDEF));
2844 else
bd17c2c3
AM		 2845 add_frag (adds (&opP->disp),
2846 SEXT (offs (&opP->disp)),
151337e8
NC		 2847 TAB (BRABSJCOND, SZ_UNDEF));
2848 }
252b5132 2849 else
bd17c2c3
AM		 2850 add_frag (adds (&opP->disp),
2851 SEXT (offs (&opP->disp)),
151337e8 2852 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2853 break;
2854 case 'w':
2855 if (isvar (&opP->disp))
2856 {
151337e8
NC		 2857 /* Check for DBcc instructions. We can relax them,
2858 but only if we have long branches and/or absolute
2859 jumps. */
2860 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2861 && (HAVE_LONG_BRANCH (current_architecture)
2862 || (! flag_keep_pcrel)))
252b5132 2863 {
151337e8 2864 if (HAVE_LONG_BRANCH (current_architecture))
bd17c2c3
AM		 2865 add_frag (adds (&opP->disp),
2866 SEXT (offs (&opP->disp)),
151337e8
NC		 2867 TAB (DBCCLBR, SZ_UNDEF));
2868 else
bd17c2c3
AM		 2869 add_frag (adds (&opP->disp),
2870 SEXT (offs (&opP->disp)),
151337e8 2871 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2872 break;
2873 }
252b5132
RH		 2874 add_fix ('w', &opP->disp, 1, 0);
2875 }
2876 addword (0);
2877 break;
36759679 2878 case 'C': /* Fixed size LONG coproc branches. */
252b5132
RH		 2879 add_fix ('l', &opP->disp, 1, 0);
2880 addword (0);
2881 addword (0);
2882 break;
36759679 2883 case 'c': /* Var size Coprocesssor branches. */
151337e8 2884 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2885 {
252b5132
RH		 2886 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2887 add_fix ('l', &opP->disp, 1, 0);
2888 addword (0);
2889 addword (0);
2890 }
151337e8 2891 else
bd17c2c3
AM		 2892 add_frag (adds (&opP->disp),
2893 SEXT (offs (&opP->disp)),
151337e8 2894 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2895 break;
2896 default:
2897 abort ();
2898 }
2899 break;
2900
36759679 2901 case 'C': /* Ignore it. */
252b5132
RH		 2902 break;
2903
36759679 2904 case 'd': /* JF this is a kludge. */
252b5132 2905 install_operand ('s', opP->reg - ADDR);
3e602632 2906 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 2907 if (!issword (tmpreg))
2908 {
2909 as_warn (_("Expression out of range, using 0"));
2910 tmpreg = 0;
2911 }
2912 addword (tmpreg);
2913 break;
2914
2915 case 'D':
2916 install_operand (s[1], opP->reg - DATA);
2917 break;
2918
fd99574b
NC		 2919 case 'e': /* EMAC ACCx, reg/reg. */
2920 install_operand (s[1], opP->reg - ACC);
2921 break;
2922
36759679 2923 case 'E': /* Ignore it. */
6da466c7
ILT		 2924 break;
2925
252b5132
RH		 2926 case 'F':
2927 install_operand (s[1], opP->reg - FP0);
2928 break;
2929
fd99574b
NC		 2930 case 'g': /* EMAC ACCEXTx. */
2931 install_operand (s[1], opP->reg - ACCEXT01);
2932 break;
2933
36759679 2934 case 'G': /* Ignore it. */
6da466c7
ILT		 2935 case 'H':
2936 break;
2937
252b5132
RH		 2938 case 'I':
2939 tmpreg = opP->reg - COP0;
2940 install_operand (s[1], tmpreg);
2941 break;
2942
fd99574b
NC		 2943 case 'i': /* MAC/EMAC scale factor. */
2944 install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3);
2945 break;
2946
36759679 2947 case 'J': /* JF foo. */
252b5132
RH		 2948 switch (opP->reg)
2949 {
2950 case SFC:
2951 tmpreg = 0x000;
2952 break;
2953 case DFC:
2954 tmpreg = 0x001;
2955 break;
2956 case CACR:
2957 tmpreg = 0x002;
2958 break;
2959 case TC:
2960 tmpreg = 0x003;
2961 break;
3e602632 2962 case ACR0:
252b5132
RH		 2963 case ITT0:
2964 tmpreg = 0x004;
2965 break;
3e602632 2966 case ACR1:
252b5132
RH		 2967 case ITT1:
2968 tmpreg = 0x005;
2969 break;
3e602632 2970 case ACR2:
252b5132
RH		 2971 case DTT0:
2972 tmpreg = 0x006;
2973 break;
3e602632 2974 case ACR3:
252b5132
RH		 2975 case DTT1:
2976 tmpreg = 0x007;
2977 break;
2978 case BUSCR:
2979 tmpreg = 0x008;
2980 break;
2981
2982 case USP:
2983 tmpreg = 0x800;
2984 break;
2985 case VBR:
2986 tmpreg = 0x801;
2987 break;
2988 case CAAR:
2989 tmpreg = 0x802;
2990 break;
2991 case MSP:
2992 tmpreg = 0x803;
2993 break;
2994 case ISP:
2995 tmpreg = 0x804;
2996 break;
2997 case MMUSR:
2998 tmpreg = 0x805;
2999 break;
3000 case URP:
3001 tmpreg = 0x806;
3002 break;
3003 case SRP:
3004 tmpreg = 0x807;
3005 break;
3006 case PCR:
3007 tmpreg = 0x808;
3008 break;
3009 case ROMBAR:
3010 tmpreg = 0xC00;
3011 break;
3e602632
NC		 3012 case ROMBAR1:
3013 tmpreg = 0xC01;
3014 break;
3015 case FLASHBAR:
252b5132
RH		 3016 case RAMBAR0:
3017 tmpreg = 0xC04;
3018 break;
3e602632 3019 case RAMBAR:
252b5132
RH		 3020 case RAMBAR1:
3021 tmpreg = 0xC05;
3022 break;
3e602632
NC		 3023 case MPCR:
3024 tmpreg = 0xC0C;
3025 break;
3026 case EDRAMBAR:
3027 tmpreg = 0xC0D;
3028 break;
3029 case MBAR0:
e80e0390 3030 case MBAR2:
3e602632
NC		 3031 case SECMBAR:
3032 tmpreg = 0xC0E;
3033 break;
3034 case MBAR1:
252b5132
RH		 3035 case MBAR:
3036 tmpreg = 0xC0F;
3037 break;
3e602632
NC		 3038 case PCR1U0:
3039 tmpreg = 0xD02;
3040 break;
3041 case PCR1L0:
3042 tmpreg = 0xD03;
3043 break;
3044 case PCR2U0:
3045 tmpreg = 0xD04;
3046 break;
3047 case PCR2L0:
3048 tmpreg = 0xD05;
3049 break;
3050 case PCR3U0:
3051 tmpreg = 0xD06;
3052 break;
3053 case PCR3L0:
3054 tmpreg = 0xD07;
3055 break;
3056 case PCR1L1:
3057 tmpreg = 0xD0A;
3058 break;
3059 case PCR1U1:
3060 tmpreg = 0xD0B;
3061 break;
3062 case PCR2L1:
3063 tmpreg = 0xD0C;
3064 break;
3065 case PCR2U1:
3066 tmpreg = 0xD0D;
3067 break;
3068 case PCR3L1:
3069 tmpreg = 0xD0E;
3070 break;
3071 case PCR3U1:
3072 tmpreg = 0xD0F;
3073 break;
252b5132
RH		 3074 default:
3075 abort ();
3076 }
3077 install_operand (s[1], tmpreg);
3078 break;
3079
3080 case 'k':
3081 tmpreg = get_num (&opP->disp, 55);
3082 install_operand (s[1], tmpreg & 0x7f);
3083 break;
3084
3085 case 'l':
3086 tmpreg = opP->mask;
3087 if (s[1] == 'w')
3088 {
3089 if (tmpreg & 0x7FF0000)
3090 as_bad (_("Floating point register in register list"));
3091 insop (reverse_16_bits (tmpreg), opcode);
3092 }
3093 else
3094 {
3095 if (tmpreg & 0x700FFFF)
3096 as_bad (_("Wrong register in floating-point reglist"));
3097 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
3098 }
3099 break;
3100
3101 case 'L':
3102 tmpreg = opP->mask;
3103 if (s[1] == 'w')
3104 {
3105 if (tmpreg & 0x7FF0000)
3106 as_bad (_("Floating point register in register list"));
3107 insop (tmpreg, opcode);
3108 }
3109 else if (s[1] == '8')
3110 {
3111 if (tmpreg & 0x0FFFFFF)
3112 as_bad (_("incorrect register in reglist"));
3113 install_operand (s[1], tmpreg >> 24);
3114 }
3115 else
3116 {
3117 if (tmpreg & 0x700FFFF)
3118 as_bad (_("wrong register in floating-point reglist"));
3119 else
3120 install_operand (s[1], tmpreg >> 16);
3121 }
3122 break;
3123
3124 case 'M':
3125 install_operand (s[1], get_num (&opP->disp, 60));
3126 break;
3127
3128 case 'O':
3129 tmpreg = ((opP->mode == DREG)
8fce3f5e 3130 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 3131 : (get_num (&opP->disp, 40) & 0x1F));
3132 install_operand (s[1], tmpreg);
3133 break;
3134
3135 case 'Q':
3136 tmpreg = get_num (&opP->disp, 10);
3137 if (tmpreg == 8)
3138 tmpreg = 0;
3139 install_operand (s[1], tmpreg);
3140 break;
3141
3142 case 'R':
3143 /* This depends on the fact that ADDR registers are eight
3144 more than their corresponding DATA regs, so the result
36759679 3145 will have the ADDR_REG bit set. */
252b5132
RH		 3146 install_operand (s[1], opP->reg - DATA);
3147 break;
3148
3149 case 'r':
3150 if (opP->mode == AINDR)
3151 install_operand (s[1], opP->reg - DATA);
3152 else
3153 install_operand (s[1], opP->index.reg - DATA);
3154 break;
3155
3156 case 's':
3157 if (opP->reg == FPI)
3158 tmpreg = 0x1;
3159 else if (opP->reg == FPS)
3160 tmpreg = 0x2;
3161 else if (opP->reg == FPC)
3162 tmpreg = 0x4;
3163 else
3164 abort ();
3165 install_operand (s[1], tmpreg);
3166 break;
3167
36759679 3168 case 'S': /* Ignore it. */
252b5132
RH		 3169 break;
3170
3171 case 'T':
3172 install_operand (s[1], get_num (&opP->disp, 30));
3173 break;
3174
36759679 3175 case 'U': /* Ignore it. */
252b5132
RH		 3176 break;
3177
3178 case 'c':
3179 switch (opP->reg)
3180 {
3181 case NC:
3182 tmpreg = 0;
3183 break;
3184 case DC:
3185 tmpreg = 1;
3186 break;
3187 case IC:
3188 tmpreg = 2;
3189 break;
3190 case BC:
3191 tmpreg = 3;
3192 break;
3193 default:
3194 as_fatal (_("failed sanity check"));
36759679 3195 } /* switch on cache token. */
252b5132
RH		 3196 install_operand (s[1], tmpreg);
3197 break;
3198#ifndef NO_68851
92774660 3199 /* JF: These are out of order, I fear. */
252b5132
RH		 3200 case 'f':
3201 switch (opP->reg)
3202 {
3203 case SFC:
3204 tmpreg = 0;
3205 break;
3206 case DFC:
3207 tmpreg = 1;
3208 break;
3209 default:
3210 abort ();
3211 }
3212 install_operand (s[1], tmpreg);
3213 break;
3214
3215 case '0':
3216 case '1':
3217 case '2':
3218 switch (opP->reg)
3219 {
3220 case TC:
3221 tmpreg = 0;
3222 break;
3223 case CAL:
3224 tmpreg = 4;
3225 break;
3226 case VAL:
3227 tmpreg = 5;
3228 break;
3229 case SCC:
3230 tmpreg = 6;
3231 break;
3232 case AC:
3233 tmpreg = 7;
3234 break;
3235 default:
3236 abort ();
3237 }
3238 install_operand (s[1], tmpreg);
3239 break;
3240
3241 case 'V':
3242 if (opP->reg == VAL)
3243 break;
3244 abort ();
3245
3246 case 'W':
3247 switch (opP->reg)
3248 {
3249 case DRP:
3250 tmpreg = 1;
3251 break;
3252 case SRP:
3253 tmpreg = 2;
3254 break;
3255 case CRP:
3256 tmpreg = 3;
3257 break;
3258 default:
3259 abort ();
3260 }
3261 install_operand (s[1], tmpreg);
3262 break;
3263
3264 case 'X':
3265 switch (opP->reg)
3266 {
3267 case BAD:
3268 case BAD + 1:
3269 case BAD + 2:
3270 case BAD + 3:
3271 case BAD + 4:
3272 case BAD + 5:
3273 case BAD + 6:
3274 case BAD + 7:
3275 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
3276 break;
3277
3278 case BAC:
3279 case BAC + 1:
3280 case BAC + 2:
3281 case BAC + 3:
3282 case BAC + 4:
3283 case BAC + 5:
3284 case BAC + 6:
3285 case BAC + 7:
3286 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
3287 break;
3288
3289 default:
3290 abort ();
3291 }
3292 install_operand (s[1], tmpreg);
3293 break;
3294 case 'Y':
3295 know (opP->reg == PSR);
3296 break;
3297 case 'Z':
3298 know (opP->reg == PCSR);
3299 break;
3300#endif /* m68851 */
3301 case '3':
3302 switch (opP->reg)
3303 {
3304 case TT0:
3305 tmpreg = 2;
3306 break;
3307 case TT1:
3308 tmpreg = 3;
3309 break;
3310 default:
3311 abort ();
3312 }
3313 install_operand (s[1], tmpreg);
3314 break;
3315 case 't':
3316 tmpreg = get_num (&opP->disp, 20);
3317 install_operand (s[1], tmpreg);
3318 break;
36759679 3319 case '_': /* used only for move16 absolute 32-bit address. */
252b5132
RH		 3320 if (isvar (&opP->disp))
3321 add_fix ('l', &opP->disp, 0, 0);
3e602632 3322 tmpreg = get_num (&opP->disp, 90);
252b5132
RH		 3323 addword (tmpreg >> 16);
3324 addword (tmpreg & 0xFFFF);
3325 break;
6da466c7
ILT		 3326 case 'u':
3327 install_operand (s[1], opP->reg - DATA0L);
3328 opP->reg -= (DATA0L);
36759679 3329 opP->reg &= 0x0F; /* remove upper/lower bit. */
6da466c7 3330 break;
3e602632
NC		 3331 case 'x':
3332 tmpreg = get_num (&opP->disp, 80);
3333 if (tmpreg == -1)
3334 tmpreg = 0;
3335 install_operand (s[1], tmpreg);
3336 break;
252b5132
RH		 3337 default:
3338 abort ();
3339 }
3340 }
3341
3342 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3343 instruction, ready to be emitted. . . */
252b5132
RH		 3344}
3345
3346static int
31302357 3347reverse_16_bits (int in)
252b5132
RH		 3348{
3349 int out = 0;
3350 int n;
3351
3352 static int mask[16] =
3353 {
3354 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3355 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3356 };
3357 for (n = 0; n < 16; n++)
3358 {
3359 if (in & mask[n])
3360 out |= mask[15 - n];
3361 }
3362 return out;
3363} /* reverse_16_bits() */
3364
3365static int
31302357 3366reverse_8_bits (int in)
252b5132
RH		 3367{
3368 int out = 0;
3369 int n;
3370
3371 static int mask[8] =
3372 {
3373 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3374 };
3375
3376 for (n = 0; n < 8; n++)
3377 {
3378 if (in & mask[n])
3379 out |= mask[7 - n];
3380 }
3381 return out;
3382} /* reverse_8_bits() */
3383
3384/* Cause an extra frag to be generated here, inserting up to 10 bytes
3385 (that value is chosen in the frag_var call in md_assemble). TYPE
3386 is the subtype of the frag to be generated; its primary type is
3387 rs_machine_dependent.
3388
3389 The TYPE parameter is also used by md_convert_frag_1 and
3390 md_estimate_size_before_relax. The appropriate type of fixup will
3391 be emitted by md_convert_frag_1.
3392
3393 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3394static void
31302357 3395install_operand (int mode, int val)
252b5132
RH		 3396{
3397 switch (mode)
3398 {
3399 case 's':
36759679 3400 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */
252b5132
RH		 3401 break;
3402 case 'd':
3403 the_ins.opcode[0] |= val << 9;
3404 break;
3405 case '1':
3406 the_ins.opcode[1] |= val << 12;
3407 break;
3408 case '2':
3409 the_ins.opcode[1] |= val << 6;
3410 break;
3411 case '3':
3412 the_ins.opcode[1] |= val;
3413 break;
3414 case '4':
3415 the_ins.opcode[2] |= val << 12;
3416 break;
3417 case '5':
3418 the_ins.opcode[2] |= val << 6;
3419 break;
3420 case '6':
3421 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3422 three words long! */
3423 the_ins.numo++;
3424 the_ins.opcode[2] |= val;
3425 break;
3426 case '7':
3427 the_ins.opcode[1] |= val << 7;
3428 break;
3429 case '8':
3430 the_ins.opcode[1] |= val << 10;
3431 break;
3432#ifndef NO_68851
3433 case '9':
3434 the_ins.opcode[1] |= val << 5;
3435 break;
3436#endif
3437
3438 case 't':
3439 the_ins.opcode[1] |= (val << 10) | (val << 7);
3440 break;
3441 case 'D':
3442 the_ins.opcode[1] |= (val << 12) | val;
3443 break;
3444 case 'g':
3445 the_ins.opcode[0] |= val = 0xff;
3446 break;
3447 case 'i':
3448 the_ins.opcode[0] |= val << 9;
3449 break;
3450 case 'C':
3451 the_ins.opcode[1] |= val;
3452 break;
3453 case 'j':
3454 the_ins.opcode[1] |= val;
36759679 3455 the_ins.numo++; /* What a hack. */
252b5132
RH		 3456 break;
3457 case 'k':
3458 the_ins.opcode[1] |= val << 4;
3459 break;
3460 case 'b':
3461 case 'w':
3462 case 'W':
3463 case 'l':
3464 break;
3465 case 'e':
3466 the_ins.opcode[0] |= (val << 6);
3467 break;
3468 case 'L':
3469 the_ins.opcode[1] = (val >> 16);
3470 the_ins.opcode[2] = val & 0xffff;
3471 break;
6da466c7
ILT		 3472 case 'm':
3473 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3474 the_ins.opcode[0] |= ((val & 0x7) << 9);
3475 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3476 break;
fd99574b 3477 case 'n': /* MAC/EMAC Rx on !load. */
6da466c7
ILT		 3478 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3479 the_ins.opcode[0] |= ((val & 0x7) << 9);
fd99574b 3480 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
6da466c7 3481 break;
fd99574b 3482 case 'o': /* MAC/EMAC Rx on load. */
6da466c7
ILT		 3483 the_ins.opcode[1] |= val << 12;
3484 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3485 break;
fd99574b 3486 case 'M': /* MAC/EMAC Ry on !load. */
6da466c7
ILT		 3487 the_ins.opcode[0] |= (val & 0xF);
3488 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3489 break;
fd99574b 3490 case 'N': /* MAC/EMAC Ry on load. */
6da466c7
ILT		 3491 the_ins.opcode[1] |= (val & 0xF);
3492 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3493 break;
3494 case 'h':
3495 the_ins.opcode[1] |= ((val != 1) << 10);
3496 break;
fd99574b
NC		 3497 case 'F':
3498 the_ins.opcode[0] |= ((val & 0x3) << 9);
3499 break;
3500 case 'f':
3501 the_ins.opcode[0] |= ((val & 0x3) << 0);
3502 break;
be8c092b 3503 case 'G': /* EMAC accumulator in a EMAC load instruction. */
fd99574b
NC		 3504 the_ins.opcode[0] |= ((~val & 0x1) << 7);
3505 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3506 break;
be8c092b 3507 case 'H': /* EMAC accumulator in a EMAC non-load instruction. */
fd99574b
NC		 3508 the_ins.opcode[0] |= ((val & 0x1) << 7);
3509 the_ins.opcode[1] |= ((val & 0x2) << (4 - 1));
3510 break;
3511 case 'I':
3512 the_ins.opcode[1] |= ((val & 0x3) << 9);
3513 break;
3514 case ']':
3515 the_ins.opcode[0] |= (val & 0x1) <<10;
3516 break;
252b5132
RH		 3517 case 'c':
3518 default:
3519 as_fatal (_("failed sanity check."));
3520 }
6b6e92f4 3521}
252b5132
RH		 3522
3523static void
31302357 3524install_gen_operand (int mode, int val)
252b5132
RH		 3525{
3526 switch (mode)
3527 {
fd99574b
NC		 3528 case '/': /* Special for mask loads for mac/msac insns with
3529 possible mask; trailing_ampersend set in bit 8. */
3530 the_ins.opcode[0] |= (val & 0x3f);
3531 the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
3532 break;
252b5132
RH		 3533 case 's':
3534 the_ins.opcode[0] |= val;
3535 break;
3536 case 'd':
3537 /* This is a kludge!!! */
3538 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3539 break;
3540 case 'b':
3541 case 'w':
3542 case 'l':
3543 case 'f':
3544 case 'F':
3545 case 'x':
3546 case 'p':
3547 the_ins.opcode[0] |= val;
3548 break;
36759679 3549 /* more stuff goes here. */
252b5132
RH		 3550 default:
3551 as_fatal (_("failed sanity check."));
3552 }
6b6e92f4 3553}
252b5132 3554
6b6e92f4
NC		 3555/* Verify that we have some number of paren pairs, do m68k_ip_op(), and
3556 then deal with the bitfield hack. */
252b5132
RH		 3557
3558static char *
31302357 3559crack_operand (char *str, struct m68k_op *opP)
252b5132
RH		 3560{
3561 register int parens;
3562 register int c;
3563 register char *beg_str;
3564 int inquote = 0;
3565
3566 if (!str)
3567 {
3568 return str;
3569 }
3570 beg_str = str;
3571 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3572 {
3573 if (! inquote)
3574 {
3575 if (*str == '(')
3576 parens++;
3577 else if (*str == ')')
3578 {
3579 if (!parens)
36759679 3580 { /* ERROR. */
252b5132
RH		 3581 opP->error = _("Extra )");
3582 return str;
3583 }
3584 --parens;
3585 }
3586 }
3587 if (flag_mri && *str == '\'')
3588 inquote = ! inquote;
3589 }
3590 if (!*str && parens)
36759679 3591 { /* ERROR. */
252b5132
RH		 3592 opP->error = _("Missing )");
3593 return str;
3594 }
3595 c = *str;
3596 *str = '\0';
3597 if (m68k_ip_op (beg_str, opP) != 0)
3598 {
3599 *str = c;
3600 return str;
3601 }
3602 *str = c;
3603 if (c == '}')
36759679 3604 c = *++str; /* JF bitfield hack. */
252b5132
RH		 3605 if (c)
3606 {
3607 c = *++str;
3608 if (!c)
3609 as_bad (_("Missing operand"));
3610 }
3611
3612 /* Detect MRI REG symbols and convert them to REGLSTs. */
3613 if (opP->mode == CONTROL && (int)opP->reg < 0)
3614 {
3615 opP->mode = REGLST;
3616 opP->mask = ~(int)opP->reg;
3617 opP->reg = 0;
3618 }
3619
3620 return str;
3621}
3622
3623/* This is the guts of the machine-dependent assembler. STR points to a
3624 machine dependent instruction. This function is supposed to emit
3625 the frags/bytes it assembles to.
3626 */
3627
3628static void
31302357 3629insert_reg (const char *regname, int regnum)
252b5132
RH		 3630{
3631 char buf[100];
3632 int i;
3633
3634#ifdef REGISTER_PREFIX
3635 if (!flag_reg_prefix_optional)
3636 {
3637 buf[0] = REGISTER_PREFIX;
3638 strcpy (buf + 1, regname);
3639 regname = buf;
3640 }
3641#endif
3642
3643 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3644 &zero_address_frag));
3645
3646 for (i = 0; regname[i]; i++)
3882b010 3647 buf[i] = TOUPPER (regname[i]);
252b5132
RH		 3648 buf[i] = '\0';
3649
3650 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3651 &zero_address_frag));
3652}
3653
3654struct init_entry
3655 {
3656 const char *name;
3657 int number;
3658 };
3659
3660static const struct init_entry init_table[] =
3661{
3662 { "d0", DATA0 },
3663 { "d1", DATA1 },
3664 { "d2", DATA2 },
3665 { "d3", DATA3 },
3666 { "d4", DATA4 },
3667 { "d5", DATA5 },
3668 { "d6", DATA6 },
3669 { "d7", DATA7 },
3670 { "a0", ADDR0 },
3671 { "a1", ADDR1 },
3672 { "a2", ADDR2 },
3673 { "a3", ADDR3 },
3674 { "a4", ADDR4 },
3675 { "a5", ADDR5 },
3676 { "a6", ADDR6 },
3677 { "fp", ADDR6 },
3678 { "a7", ADDR7 },
3679 { "sp", ADDR7 },
3680 { "ssp", ADDR7 },
3681 { "fp0", FP0 },
3682 { "fp1", FP1 },
3683 { "fp2", FP2 },
3684 { "fp3", FP3 },
3685 { "fp4", FP4 },
3686 { "fp5", FP5 },
3687 { "fp6", FP6 },
3688 { "fp7", FP7 },
3689 { "fpi", FPI },
3690 { "fpiar", FPI },
3691 { "fpc", FPI },
3692 { "fps", FPS },
3693 { "fpsr", FPS },
3694 { "fpc", FPC },
3695 { "fpcr", FPC },
3696 { "control", FPC },
3697 { "status", FPS },
3698 { "iaddr", FPI },
3699
3700 { "cop0", COP0 },
3701 { "cop1", COP1 },
3702 { "cop2", COP2 },
3703 { "cop3", COP3 },
3704 { "cop4", COP4 },
3705 { "cop5", COP5 },
3706 { "cop6", COP6 },
3707 { "cop7", COP7 },
3708 { "pc", PC },
3709 { "zpc", ZPC },
3710 { "sr", SR },
3711
3712 { "ccr", CCR },
3713 { "cc", CCR },
3714
6da466c7 3715 { "acc", ACC },
fd99574b
NC		 3716 { "acc0", ACC },
3717 { "acc1", ACC1 },
3718 { "acc2", ACC2 },
3719 { "acc3", ACC3 },
3720 { "accext01", ACCEXT01 },
3721 { "accext23", ACCEXT23 },
6da466c7
ILT		 3722 { "macsr", MACSR },
3723 { "mask", MASK },
3724
36759679
NC		 3725 /* Control registers. */
3726 { "sfc", SFC }, /* Source Function Code. */
252b5132 3727 { "sfcr", SFC },
36759679 3728 { "dfc", DFC }, /* Destination Function Code. */
252b5132 3729 { "dfcr", DFC },
36759679
NC		 3730 { "cacr", CACR }, /* Cache Control Register. */
3731 { "caar", CAAR }, /* Cache Address Register. */
252b5132 3732
36759679
NC		 3733 { "usp", USP }, /* User Stack Pointer. */
3734 { "vbr", VBR }, /* Vector Base Register. */
3735 { "msp", MSP }, /* Master Stack Pointer. */
3736 { "isp", ISP }, /* Interrupt Stack Pointer. */
252b5132 3737
36759679
NC		 3738 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */
3739 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */
3740 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */
3741 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */
252b5132
RH		 3742
3743 /* 68ec040 versions of same */
36759679
NC		 3744 { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */
3745 { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */
3746 { "dacr0", DTT0 }, /* Data Access Control Register 0. */
3747 { "dacr1", DTT1 }, /* Data Access Control Register 0. */
252b5132
RH		 3748
3749 /* mcf5200 versions of same. The ColdFire programmer's reference
3750 manual indicated that the order is 2,3,0,1, but Ken Rose
3751 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3e602632
NC		 3752 { "acr0", ACR0 }, /* Access Control Unit 0. */
3753 { "acr1", ACR1 }, /* Access Control Unit 1. */
3754 { "acr2", ACR2 }, /* Access Control Unit 2. */
3755 { "acr3", ACR3 }, /* Access Control Unit 3. */
252b5132 3756
36759679 3757 { "tc", TC }, /* MMU Translation Control Register. */
252b5132
RH		 3758 { "tcr", TC },
3759
36759679
NC		 3760 { "mmusr", MMUSR }, /* MMU Status Register. */
3761 { "srp", SRP }, /* User Root Pointer. */
3762 { "urp", URP }, /* Supervisor Root Pointer. */
252b5132
RH		 3763
3764 { "buscr", BUSCR },
3765 { "pcr", PCR },
3766
36759679
NC		 3767 { "rombar", ROMBAR }, /* ROM Base Address Register. */
3768 { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */
3769 { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */
3770 { "mbar", MBAR }, /* Module Base Address Register. */
3e602632
NC		 3771
3772 { "mbar0", MBAR0 }, /* mcfv4e registers. */
3773 { "mbar1", MBAR1 }, /* mcfv4e registers. */
3774 { "rombar0", ROMBAR }, /* mcfv4e registers. */
3775 { "rombar1", ROMBAR1 }, /* mcfv4e registers. */
3776 { "mpcr", MPCR }, /* mcfv4e registers. */
3777 { "edrambar", EDRAMBAR }, /* mcfv4e registers. */
3778 { "secmbar", SECMBAR }, /* mcfv4e registers. */
3779 { "asid", TC }, /* mcfv4e registers. */
3780 { "mmubar", BUSCR }, /* mcfv4e registers. */
3781 { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */
3782 { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */
3783 { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */
3784 { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */
3785 { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */
3786 { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */
3787 { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */
3788 { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */
3789 { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */
3790 { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */
3791 { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */
3792 { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */
3793
3794 { "flashbar", FLASHBAR }, /* mcf528x registers. */
3795 { "rambar", RAMBAR }, /* mcf528x registers. */
e80e0390
NC		 3796
3797 { "mbar2", MBAR2 }, /* mcf5249 registers. */
36759679 3798 /* End of control registers. */
252b5132
RH		 3799
3800 { "ac", AC },
3801 { "bc", BC },
3802 { "cal", CAL },
3803 { "crp", CRP },
3804 { "drp", DRP },
3805 { "pcsr", PCSR },
3806 { "psr", PSR },
3807 { "scc", SCC },
3808 { "val", VAL },
3809 { "bad0", BAD0 },
3810 { "bad1", BAD1 },
3811 { "bad2", BAD2 },
3812 { "bad3", BAD3 },
3813 { "bad4", BAD4 },
3814 { "bad5", BAD5 },
3815 { "bad6", BAD6 },
3816 { "bad7", BAD7 },
3817 { "bac0", BAC0 },
3818 { "bac1", BAC1 },
3819 { "bac2", BAC2 },
3820 { "bac3", BAC3 },
3821 { "bac4", BAC4 },
3822 { "bac5", BAC5 },
3823 { "bac6", BAC6 },
3824 { "bac7", BAC7 },
3825
3826 { "ic", IC },
3827 { "dc", DC },
3828 { "nc", NC },
3829
3830 { "tt0", TT0 },
3831 { "tt1", TT1 },
36759679 3832 /* 68ec030 versions of same. */
252b5132
RH		 3833 { "ac0", TT0 },
3834 { "ac1", TT1 },
36759679 3835 /* 68ec030 access control unit, identical to 030 MMU status reg. */
252b5132
RH		 3836 { "acusr", PSR },
3837
3838 /* Suppressed data and address registers. */
3839 { "zd0", ZDATA0 },
3840 { "zd1", ZDATA1 },
3841 { "zd2", ZDATA2 },
3842 { "zd3", ZDATA3 },
3843 { "zd4", ZDATA4 },
3844 { "zd5", ZDATA5 },
3845 { "zd6", ZDATA6 },
3846 { "zd7", ZDATA7 },
3847 { "za0", ZADDR0 },
3848 { "za1", ZADDR1 },
3849 { "za2", ZADDR2 },
3850 { "za3", ZADDR3 },
3851 { "za4", ZADDR4 },
3852 { "za5", ZADDR5 },
3853 { "za6", ZADDR6 },
3854 { "za7", ZADDR7 },
3855
92774660 3856 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3857 { "d0l", DATA0L },
3858 { "d1l", DATA1L },
3859 { "d2l", DATA2L },
3860 { "d3l", DATA3L },
3861 { "d4l", DATA4L },
3862 { "d5l", DATA5L },
3863 { "d6l", DATA6L },
3864 { "d7l", DATA7L },
3865
3866 { "a0l", ADDR0L },
3867 { "a1l", ADDR1L },
3868 { "a2l", ADDR2L },
3869 { "a3l", ADDR3L },
3870 { "a4l", ADDR4L },
3871 { "a5l", ADDR5L },
3872 { "a6l", ADDR6L },
3873 { "a7l", ADDR7L },
3874
3875 { "d0u", DATA0U },
3876 { "d1u", DATA1U },
3877 { "d2u", DATA2U },
3878 { "d3u", DATA3U },
3879 { "d4u", DATA4U },
3880 { "d5u", DATA5U },
3881 { "d6u", DATA6U },
3882 { "d7u", DATA7U },
3883
3884 { "a0u", ADDR0U },
3885 { "a1u", ADDR1U },
3886 { "a2u", ADDR2U },
3887 { "a3u", ADDR3U },
3888 { "a4u", ADDR4U },
3889 { "a5u", ADDR5U },
3890 { "a6u", ADDR6U },
3891 { "a7u", ADDR7U },
3892
252b5132
RH		 3893 { 0, 0 }
3894};
3895
3896static void
31302357 3897init_regtable (void)
252b5132
RH		 3898{
3899 int i;
3900 for (i = 0; init_table[i].name; i++)
3901 insert_reg (init_table[i].name, init_table[i].number);
3902}
3903
252b5132 3904void
31302357 3905md_assemble (char *str)
252b5132
RH		 3906{
3907 const char *er;
3908 short *fromP;
3909 char *toP = NULL;
3910 int m, n = 0;
3911 char *to_beg_P;
3912 int shorts_this_frag;
3913 fixS *fixP;
3914
266abb8f
NS		 3915 if (!selected_cpu && !selected_arch)
3916 {
3917 /* We've not selected an architecture yet. Set the default
3918 now. We do this lazily so that an initial .cpu or .arch directive
3919 can specify. */
3920 if (!m68k_set_cpu (TARGET_CPU, 1, 1))
3921 as_bad (_("unrecognized default cpu `%s'"), TARGET_CPU);
3922 }
3923 if (!initialized)
3924 m68k_init_arch ();
3925
252b5132
RH		 3926 /* In MRI mode, the instruction and operands are separated by a
3927 space. Anything following the operands is a comment. The label
3928 has already been removed. */
3929 if (flag_mri)
3930 {
3931 char *s;
3932 int fields = 0;
3933 int infield = 0;
3934 int inquote = 0;
3935
3936 for (s = str; *s != '\0'; s++)
3937 {
3938 if ((*s == ' ' || *s == '\t') && ! inquote)
3939 {
3940 if (infield)
3941 {
3942 ++fields;
3943 if (fields >= 2)
3944 {
3945 *s = '\0';
3946 break;
3947 }
3948 infield = 0;
3949 }
3950 }
3951 else
3952 {
3953 if (! infield)
3954 infield = 1;
3955 if (*s == '\'')
3956 inquote = ! inquote;
3957 }
3958 }
3959 }
3960
31302357 3961 memset (&the_ins, '\0', sizeof (the_ins));
252b5132
RH		 3962 m68k_ip (str);
3963 er = the_ins.error;
3964 if (!er)
3965 {
3966 for (n = 0; n < the_ins.numargs; n++)
3967 if (the_ins.operands[n].error)
3968 {
3969 er = the_ins.operands[n].error;
3970 break;
3971 }
3972 }
3973 if (er)
3974 {
3975 as_bad (_("%s -- statement `%s' ignored"), er, str);
3976 return;
3977 }
3978
3979 /* If there is a current label, record that it marks an instruction. */
3980 if (current_label != NULL)
3981 {
3982 current_label->text = 1;
3983 current_label = NULL;
3984 }
3985
f27a3839
AS		 3986#ifdef OBJ_ELF
3987 /* Tie dwarf2 debug info to the address at the start of the insn. */
3988 dwarf2_emit_insn (0);
3989#endif
3990
252b5132
RH		 3991 if (the_ins.nfrag == 0)
3992 {
36759679 3993 /* No frag hacking involved; just put it out. */
252b5132
RH		 3994 toP = frag_more (2 * the_ins.numo);
3995 fromP = &the_ins.opcode[0];
3996 for (m = the_ins.numo; m; --m)
3997 {
3998 md_number_to_chars (toP, (long) (*fromP), 2);
3999 toP += 2;
4000 fromP++;
4001 }
36759679 4002 /* Put out symbol-dependent info. */
252b5132
RH		 4003 for (m = 0; m < the_ins.nrel; m++)
4004 {
4005 switch (the_ins.reloc[m].wid)
4006 {
4007 case 'B':
4008 n = 1;
4009 break;
4010 case 'b':
4011 n = 1;
4012 break;
4013 case '3':
4014 n = 1;
4015 break;
4016 case 'w':
4017 case 'W':
4018 n = 2;
4019 break;
4020 case 'l':
4021 n = 4;
4022 break;
4023 default:
4024 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
4025 the_ins.reloc[m].wid);
4026 }
4027
4028 fixP = fix_new_exp (frag_now,
4029 ((toP - frag_now->fr_literal)
4030 - the_ins.numo * 2 + the_ins.reloc[m].n),
4031 n,
4032 &the_ins.reloc[m].exp,
4033 the_ins.reloc[m].pcrel,
4034 get_reloc_code (n, the_ins.reloc[m].pcrel,
4035 the_ins.reloc[m].pic_reloc));
4036 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4037 if (the_ins.reloc[m].wid == 'B')
4038 fixP->fx_signed = 1;
4039 }
4040 return;
4041 }
4042
36759679 4043 /* There's some frag hacking. */
fbe572f9
AM		 4044 {
4045 /* Calculate the max frag size. */
4046 int wid;
4047
4048 wid = 2 * the_ins.fragb[0].fragoff;
4049 for (n = 1; n < the_ins.nfrag; n++)
4050 wid += 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4051 /* frag_var part. */
4052 wid += 10;
4053 /* Make sure the whole insn fits in one chunk, in particular that
4054 the var part is attached, as we access one byte before the
4055 variable frag for byte branches. */
4056 frag_grow (wid);
4057 }
4058
252b5132
RH		 4059 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
4060 {
4061 int wid;
4062
4063 if (n == 0)
4064 wid = 2 * the_ins.fragb[n].fragoff;
4065 else
4066 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4067 toP = frag_more (wid);
4068 to_beg_P = toP;
4069 shorts_this_frag = 0;
4070 for (m = wid / 2; m; --m)
4071 {
4072 md_number_to_chars (toP, (long) (*fromP), 2);
4073 toP += 2;
4074 fromP++;
4075 shorts_this_frag++;
4076 }
4077 for (m = 0; m < the_ins.nrel; m++)
4078 {
4079 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
4080 {
4081 the_ins.reloc[m].n -= 2 * shorts_this_frag;
4082 break;
4083 }
4084 wid = the_ins.reloc[m].wid;
4085 if (wid == 0)
4086 continue;
4087 the_ins.reloc[m].wid = 0;
4088 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4089
4090 fixP = fix_new_exp (frag_now,
4091 ((toP - frag_now->fr_literal)
4092 - the_ins.numo * 2 + the_ins.reloc[m].n),
4093 wid,
4094 &the_ins.reloc[m].exp,
4095 the_ins.reloc[m].pcrel,
4096 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4097 the_ins.reloc[m].pic_reloc));
4098 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4099 }
4100 (void) frag_var (rs_machine_dependent, 10, 0,
4101 (relax_substateT) (the_ins.fragb[n].fragty),
4102 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
4103 }
4104 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
4105 shorts_this_frag = 0;
4106 if (n)
4107 {
055d1eb0 4108 toP = frag_more (n * 2);
252b5132
RH		 4109 while (n--)
4110 {
4111 md_number_to_chars (toP, (long) (*fromP), 2);
4112 toP += 2;
4113 fromP++;
4114 shorts_this_frag++;
4115 }
4116 }
4117 for (m = 0; m < the_ins.nrel; m++)
4118 {
4119 int wid;
4120
4121 wid = the_ins.reloc[m].wid;
4122 if (wid == 0)
4123 continue;
4124 the_ins.reloc[m].wid = 0;
4125 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
4126
4127 fixP = fix_new_exp (frag_now,
4128 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
4129 - shorts_this_frag * 2),
4130 wid,
4131 &the_ins.reloc[m].exp,
4132 the_ins.reloc[m].pcrel,
4133 get_reloc_code (wid, the_ins.reloc[m].pcrel,
4134 the_ins.reloc[m].pic_reloc));
4135 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
4136 }
4137}
4138
60fed2d3
NC		 4139/* Comparison function used by qsort to rank the opcode entries by name. */
4140
4141static int
4142m68k_compare_opcode (const void * v1, const void * v2)
4143{
4144 struct m68k_opcode * op1, * op2;
4145 int ret;
4146
03b13e59
NC		 4147 if (v1 == v2)
4148 return 0;
4149
60fed2d3
NC		 4150 op1 = *(struct m68k_opcode **) v1;
4151 op2 = *(struct m68k_opcode **) v2;
4152
4153 /* Compare the two names. If different, return the comparison.
4154 If the same, return the order they are in the opcode table. */
4155 ret = strcmp (op1->name, op2->name);
4156 if (ret)
4157 return ret;
4158 if (op1 < op2)
4159 return -1;
03b13e59 4160 return 1;
60fed2d3
NC		 4161}
4162
252b5132 4163void
60fed2d3 4164md_begin (void)
252b5132 4165{
60fed2d3
NC		 4166 const struct m68k_opcode *ins;
4167 struct m68k_incant *hack, *slak;
4168 const char *retval = 0; /* Empty string, or error msg text. */
4169 int i;
4170
4171 /* Set up hash tables with 68000 instructions.
4172 similar to what the vax assembler does. */
252b5132
RH		 4173 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
4174 a copy of it at runtime, adding in the information we want but isn't
4175 there. I think it'd be better to have an awk script hack the table
4176 at compile time. Or even just xstr the table and use it as-is. But
4177 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
4178 names. */
4179
252b5132
RH		 4180 if (flag_mri)
4181 {
4182 flag_reg_prefix_optional = 1;
4183 m68k_abspcadd = 1;
4184 if (! m68k_rel32_from_cmdline)
4185 m68k_rel32 = 0;
4186 }
4187
60fed2d3
NC		 4188 /* First sort the opcode table into alphabetical order to seperate
4189 the order that the assembler wants to see the opcodes from the
4190 order that the disassembler wants to see them. */
4191 m68k_sorted_opcodes = xmalloc (m68k_numopcodes * sizeof (* m68k_sorted_opcodes));
4192 if (!m68k_sorted_opcodes)
4193 as_fatal (_("Internal Error: Can't allocate m68k_sorted_opcodes of size %d"),
045b540e 4194 m68k_numopcodes * ((int) sizeof (* m68k_sorted_opcodes)));
60fed2d3
NC		 4195
4196 for (i = m68k_numopcodes; i--;)
4197 m68k_sorted_opcodes[i] = m68k_opcodes + i;
4198
4199 qsort (m68k_sorted_opcodes, m68k_numopcodes,
4200 sizeof (m68k_sorted_opcodes[0]), m68k_compare_opcode);
4201
252b5132
RH		 4202 op_hash = hash_new ();
4203
4204 obstack_begin (&robyn, 4000);
4205 for (i = 0; i < m68k_numopcodes; i++)
4206 {
4207 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
4208 do
4209 {
60fed2d3
NC		 4210 ins = m68k_sorted_opcodes[i];
4211
4212 /* We *could* ignore insns that don't match our
4213 arch here by just leaving them out of the hash. */
252b5132
RH		 4214 slak->m_operands = ins->args;
4215 slak->m_opnum = strlen (slak->m_operands) / 2;
4216 slak->m_arch = ins->arch;
4217 slak->m_opcode = ins->opcode;
36759679 4218 /* This is kludgey. */
252b5132
RH		 4219 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
4220 if (i + 1 != m68k_numopcodes
60fed2d3 4221 && !strcmp (ins->name, m68k_sorted_opcodes[i + 1]->name))
252b5132 4222 {
60fed2d3 4223 slak->m_next = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4224 i++;
4225 }
4226 else
4227 slak->m_next = 0;
4228 slak = slak->m_next;
4229 }
4230 while (slak);
4231
4232 retval = hash_insert (op_hash, ins->name, (char *) hack);
4233 if (retval)
4234 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
4235 }
4236
4237 for (i = 0; i < m68k_numaliases; i++)
4238 {
4239 const char *name = m68k_opcode_aliases[i].primary;
4240 const char *alias = m68k_opcode_aliases[i].alias;
4241 PTR val = hash_find (op_hash, name);
60fed2d3 4242
252b5132
RH		 4243 if (!val)
4244 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4245 retval = hash_insert (op_hash, alias, val);
4246 if (retval)
4247 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4248 }
4249
4250 /* In MRI mode, all unsized branches are variable sized. Normally,
4251 they are word sized. */
4252 if (flag_mri)
4253 {
4254 static struct m68k_opcode_alias mri_aliases[] =
4255 {
4256 { "bhi", "jhi", },
4257 { "bls", "jls", },
4258 { "bcc", "jcc", },
4259 { "bcs", "jcs", },
4260 { "bne", "jne", },
4261 { "beq", "jeq", },
4262 { "bvc", "jvc", },
4263 { "bvs", "jvs", },
4264 { "bpl", "jpl", },
4265 { "bmi", "jmi", },
4266 { "bge", "jge", },
4267 { "blt", "jlt", },
4268 { "bgt", "jgt", },
4269 { "ble", "jle", },
4270 { "bra", "jra", },
4271 { "bsr", "jbsr", },
4272 };
4273
8fce3f5e
AM		 4274 for (i = 0;
4275 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
4276 i++)
252b5132
RH		 4277 {
4278 const char *name = mri_aliases[i].primary;
4279 const char *alias = mri_aliases[i].alias;
4280 PTR val = hash_find (op_hash, name);
60fed2d3 4281
252b5132
RH		 4282 if (!val)
4283 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
4284 retval = hash_jam (op_hash, alias, val);
4285 if (retval)
4286 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
4287 }
4288 }
4289
8fce3f5e 4290 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 4291 {
4292 notend_table[i] = 0;
4293 alt_notend_table[i] = 0;
4294 }
60fed2d3 4295
252b5132
RH		 4296 notend_table[','] = 1;
4297 notend_table['{'] = 1;
4298 notend_table['}'] = 1;
4299 alt_notend_table['a'] = 1;
4300 alt_notend_table['A'] = 1;
4301 alt_notend_table['d'] = 1;
4302 alt_notend_table['D'] = 1;
4303 alt_notend_table['#'] = 1;
4304 alt_notend_table['&'] = 1;
4305 alt_notend_table['f'] = 1;
4306 alt_notend_table['F'] = 1;
4307#ifdef REGISTER_PREFIX
4308 alt_notend_table[REGISTER_PREFIX] = 1;
4309#endif
4310
4311 /* We need to put '(' in alt_notend_table to handle
60fed2d3 4312 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1) */
252b5132
RH		 4313 alt_notend_table['('] = 1;
4314
4315 /* We need to put '@' in alt_notend_table to handle
60fed2d3 4316 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1) */
252b5132
RH		 4317 alt_notend_table['@'] = 1;
4318
4319 /* We need to put digits in alt_notend_table to handle
60fed2d3 4320 bfextu %d0{24:1},%d0 */
252b5132
RH		 4321 alt_notend_table['0'] = 1;
4322 alt_notend_table['1'] = 1;
4323 alt_notend_table['2'] = 1;
4324 alt_notend_table['3'] = 1;
4325 alt_notend_table['4'] = 1;
4326 alt_notend_table['5'] = 1;
4327 alt_notend_table['6'] = 1;
4328 alt_notend_table['7'] = 1;
4329 alt_notend_table['8'] = 1;
4330 alt_notend_table['9'] = 1;
4331
4332#ifndef MIT_SYNTAX_ONLY
4333 /* Insert pseudo ops, these have to go into the opcode table since
36759679 4334 gas expects pseudo ops to start with a dot. */
252b5132
RH		 4335 {
4336 int n = 0;
60fed2d3 4337
252b5132
RH		 4338 while (mote_pseudo_table[n].poc_name)
4339 {
60fed2d3 4340 hack = obstack_alloc (&robyn, sizeof (struct m68k_incant));
252b5132
RH		 4341 hash_insert (op_hash,
4342 mote_pseudo_table[n].poc_name, (char *) hack);
4343 hack->m_operands = 0;
4344 hack->m_opnum = n;
4345 n++;
4346 }
4347 }
4348#endif
4349
4350 init_regtable ();
4351
4352#ifdef OBJ_ELF
4353 record_alignment (text_section, 2);
4354 record_alignment (data_section, 2);
4355 record_alignment (bss_section, 2);
4356#endif
4357}
4358
252b5132
RH		 4359\f
4360/* This is called when a label is defined. */
4361
4362void
31302357 4363m68k_frob_label (symbolS *sym)
252b5132
RH		 4364{
4365 struct label_line *n;
4366
4367 n = (struct label_line *) xmalloc (sizeof *n);
4368 n->next = labels;
4369 n->label = sym;
4370 as_where (&n->file, &n->line);
4371 n->text = 0;
4372 labels = n;
4373 current_label = n;
07a53e5c
RH		 4374
4375#ifdef OBJ_ELF
4376 dwarf2_emit_label (sym);
4377#endif
252b5132
RH		 4378}
4379
4380/* This is called when a value that is not an instruction is emitted. */
4381
4382void
31302357 4383m68k_flush_pending_output (void)
252b5132
RH		 4384{
4385 current_label = NULL;
4386}
4387
4388/* This is called at the end of the assembly, when the final value of
4389 the label is known. We warn if this is a text symbol aligned at an
4390 odd location. */
4391
4392void
31302357 4393m68k_frob_symbol (symbolS *sym)
252b5132
RH		 4394{
4395 if (S_GET_SEGMENT (sym) == reg_section
4396 && (int) S_GET_VALUE (sym) < 0)
4397 {
4398 S_SET_SEGMENT (sym, absolute_section);
4399 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4400 }
4401 else if ((S_GET_VALUE (sym) & 1) != 0)
4402 {
4403 struct label_line *l;
4404
4405 for (l = labels; l != NULL; l = l->next)
4406 {
4407 if (l->label == sym)
4408 {
4409 if (l->text)
4410 as_warn_where (l->file, l->line,
4411 _("text label `%s' aligned to odd boundary"),
4412 S_GET_NAME (sym));
4413 break;
4414 }
4415 }
4416 }
4417}
4418\f
4419/* This is called if we go in or out of MRI mode because of the .mri
4420 pseudo-op. */
4421
4422void
31302357 4423m68k_mri_mode_change (int on)
252b5132
RH		 4424{
4425 if (on)
4426 {
4427 if (! flag_reg_prefix_optional)
4428 {
4429 flag_reg_prefix_optional = 1;
4430#ifdef REGISTER_PREFIX
4431 init_regtable ();
4432#endif
4433 }
4434 m68k_abspcadd = 1;
4435 if (! m68k_rel32_from_cmdline)
4436 m68k_rel32 = 0;
4437 }
4438 else
4439 {
4440 if (! reg_prefix_optional_seen)
4441 {
4442#ifdef REGISTER_PREFIX_OPTIONAL
4443 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4444#else
4445 flag_reg_prefix_optional = 0;
4446#endif
4447#ifdef REGISTER_PREFIX
4448 init_regtable ();
4449#endif
4450 }
4451 m68k_abspcadd = 0;
4452 if (! m68k_rel32_from_cmdline)
4453 m68k_rel32 = 1;
4454 }
4455}
4456
36759679 4457/* Equal to MAX_PRECISION in atof-ieee.c. */
252b5132
RH		 4458#define MAX_LITTLENUMS 6
4459
4460/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4461 of type TYPE, and store the appropriate bytes in *LITP. The number
4462 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4463 returned, or NULL on OK. */
4464
4465char *
31302357 4466md_atof (int type, char *litP, int *sizeP)
252b5132
RH		 4467{
4468 int prec;
4469 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4470 LITTLENUM_TYPE *wordP;
4471 char *t;
4472
4473 switch (type)
4474 {
4475 case 'f':
4476 case 'F':
4477 case 's':
4478 case 'S':
4479 prec = 2;
4480 break;
4481
4482 case 'd':
4483 case 'D':
4484 case 'r':
4485 case 'R':
4486 prec = 4;
4487 break;
4488
4489 case 'x':
4490 case 'X':
4491 prec = 6;
4492 break;
4493
4494 case 'p':
4495 case 'P':
4496 prec = 6;
4497 break;
4498
4499 default:
4500 *sizeP = 0;
4501 return _("Bad call to MD_ATOF()");
4502 }
4503 t = atof_ieee (input_line_pointer, type, words);
4504 if (t)
4505 input_line_pointer = t;
4506
4507 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4508 for (wordP = words; prec--;)
4509 {
4510 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4511 litP += sizeof (LITTLENUM_TYPE);
4512 }
4513 return 0;
4514}
4515
4516void
31302357 4517md_number_to_chars (char *buf, valueT val, int n)
252b5132
RH		 4518{
4519 number_to_chars_bigendian (buf, val, n);
4520}
4521
94f592af 4522void
55cf6793 4523md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
252b5132 4524{
bbe8ef22 4525 offsetT val = *valP;
252b5132
RH		 4526 addressT upper_limit;
4527 offsetT lower_limit;
4528
4529 /* This is unnecessary but it convinces the native rs6000 compiler
4530 to generate the code we want. */
4531 char *buf = fixP->fx_frag->fr_literal;
4532 buf += fixP->fx_where;
36759679 4533 /* End ibm compiler workaround. */
252b5132 4534
bd17c2c3 4535 val = SEXT (val);
252b5132 4536
94f592af
NC		 4537 if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0)
4538 fixP->fx_done = 1;
4539
252b5132
RH		 4540#ifdef OBJ_ELF
4541 if (fixP->fx_addsy)
4542 {
4543 memset (buf, 0, fixP->fx_size);
36759679 4544 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */
252b5132
RH		 4545
4546 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4547 && !S_IS_DEFINED (fixP->fx_addsy)
4548 && !S_IS_WEAK (fixP->fx_addsy))
4549 S_SET_WEAK (fixP->fx_addsy);
4550 return;
4551 }
4552#endif
4553
252b5132
RH		 4554 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4555 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4556 return;
252b5132
RH		 4557
4558 switch (fixP->fx_size)
4559 {
94f592af
NC		 4560 /* The cast to offsetT below are necessary to make code
4561 correct for machines where ints are smaller than offsetT. */
252b5132
RH		 4562 case 1:
4563 *buf++ = val;
4564 upper_limit = 0x7f;
4565 lower_limit = - (offsetT) 0x80;
4566 break;
4567 case 2:
4568 *buf++ = (val >> 8);
4569 *buf++ = val;
4570 upper_limit = 0x7fff;
4571 lower_limit = - (offsetT) 0x8000;
4572 break;
4573 case 4:
4574 *buf++ = (val >> 24);
4575 *buf++ = (val >> 16);
4576 *buf++ = (val >> 8);
4577 *buf++ = val;
4578 upper_limit = 0x7fffffff;
36759679 4579 lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */
252b5132
RH		 4580 break;
4581 default:
4582 BAD_CASE (fixP->fx_size);
4583 }
4584
4585 /* Fix up a negative reloc. */
4586 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4587 {
4588 fixP->fx_addsy = fixP->fx_subsy;
4589 fixP->fx_subsy = NULL;
4590 fixP->fx_tcbit = 1;
4591 }
4592
4593 /* For non-pc-relative values, it's conceivable we might get something
4594 like "0xff" for a byte field. So extend the upper part of the range
4595 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4596 so that we can do any range checking at all. */
4597 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4598 upper_limit = upper_limit * 2 + 1;
4599
4600 if ((addressT) val > upper_limit
4601 && (val > 0 || val < lower_limit))
4602 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4603
4604 /* A one byte PC-relative reloc means a short branch. We can't use
4605 a short branch with a value of 0 or -1, because those indicate
4606 different opcodes (branches with longer offsets). fixup_segment
4607 in write.c may have clobbered fx_pcrel, so we need to examine the
4608 reloc type. */
4609 if ((fixP->fx_pcrel
7be1c489 4610 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
252b5132
RH		 4611 && fixP->fx_size == 1
4612 && (fixP->fx_addsy == NULL
4613 || S_IS_DEFINED (fixP->fx_addsy))
4614 && (val == 0 || val == -1))
4615 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4616}
4617
252b5132
RH		 4618/* *fragP has been relaxed to its final size, and now needs to have
4619 the bytes inside it modified to conform to the new size There is UGLY
4620 MAGIC here. ..
4621 */
4622static void
31302357 4623md_convert_frag_1 (fragS *fragP)
252b5132
RH		 4624{
4625 long disp;
252b5132
RH		 4626 fixS *fixP;
4627
4628 /* Address in object code of the displacement. */
4629 register int object_address = fragP->fr_fix + fragP->fr_address;
4630
4631 /* Address in gas core of the place to store the displacement. */
4632 /* This convinces the native rs6000 compiler to generate the code we
92774660 4633 want. */
252b5132
RH		 4634 register char *buffer_address = fragP->fr_literal;
4635 buffer_address += fragP->fr_fix;
36759679 4636 /* End ibm compiler workaround. */
252b5132
RH		 4637
4638 /* The displacement of the address, from current location. */
4639 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4640 disp = (disp + fragP->fr_offset) - object_address;
4641
252b5132
RH		 4642 switch (fragP->fr_subtype)
4643 {
151337e8
NC		 4644 case TAB (BRANCHBWL, BYTE):
4645 case TAB (BRABSJUNC, BYTE):
4646 case TAB (BRABSJCOND, BYTE):
4647 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4648 know (issbyte (disp));
4649 if (disp == 0)
b091f402
AM		 4650 as_bad_where (fragP->fr_file, fragP->fr_line,
4651 _("short branch with zero offset: use :w"));
151337e8 4652 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4653 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4654 fixP->fx_pcrel_adjust = -1;
252b5132 4655 break;
151337e8
NC		 4656 case TAB (BRANCHBWL, SHORT):
4657 case TAB (BRABSJUNC, SHORT):
4658 case TAB (BRABSJCOND, SHORT):
4659 case TAB (BRANCHBW, SHORT):
252b5132 4660 fragP->fr_opcode[1] = 0x00;
151337e8 4661 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4662 1, RELAX_RELOC_PC16);
151337e8
NC		 4663 fragP->fr_fix += 2;
4664 break;
4665 case TAB (BRANCHBWL, LONG):
4666 fragP->fr_opcode[1] = (char) 0xFF;
4667 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4668 1, RELAX_RELOC_PC32);
151337e8 4669 fragP->fr_fix += 4;
252b5132 4670 break;
151337e8
NC		 4671 case TAB (BRABSJUNC, LONG):
4672 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4673 {
36759679 4674 if (flag_keep_pcrel)
6b6e92f4 4675 as_fatal (_("Tried to convert PC relative BSR to absolute JSR"));
151337e8 4676 fragP->fr_opcode[0] = 0x4E;
36759679 4677 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */
151337e8 4678 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4679 0, RELAX_RELOC_ABS32);
151337e8
NC		 4680 fragP->fr_fix += 4;
4681 }
4682 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4683 {
36759679 4684 if (flag_keep_pcrel)
6b6e92f4 4685 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
151337e8 4686 fragP->fr_opcode[0] = 0x4E;
36759679 4687 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */
151337e8 4688 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4689 0, RELAX_RELOC_ABS32);
151337e8 4690 fragP->fr_fix += 4;
252b5132
RH		 4691 }
4692 else
4693 {
151337e8
NC		 4694 /* This cannot happen, because jbsr and jbra are the only two
4695 unconditional branches. */
4696 abort ();
252b5132
RH		 4697 }
4698 break;
151337e8 4699 case TAB (BRABSJCOND, LONG):
36759679 4700 if (flag_keep_pcrel)
6b6e92f4 4701 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
92774660 4702
36759679
NC		 4703 /* Only Bcc 68000 instructions can come here
4704 Change bcc into b!cc/jmp absl long. */
4705 fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */
4706 fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
252b5132
RH		 4707
4708 /* JF: these used to be fr_opcode[2,3], but they may be in a
67c1ffbe 4709 different frag, in which case referring to them is a no-no.
92774660 4710 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4711 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4712 *buffer_address++ = (char) 0xf9;
36759679 4713 fragP->fr_fix += 2; /* Account for jmp instruction. */
252b5132 4714 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4715 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4716 fragP->fr_fix += 4;
4717 break;
4718 case TAB (FBRANCH, SHORT):
4719 know ((fragP->fr_opcode[1] & 0x40) == 0);
4720 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4721 1, RELAX_RELOC_PC16);
151337e8
NC		 4722 fragP->fr_fix += 2;
4723 break;
4724 case TAB (FBRANCH, LONG):
36759679 4725 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */
151337e8 4726 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4727 1, RELAX_RELOC_PC32);
252b5132 4728 fragP->fr_fix += 4;
252b5132 4729 break;
151337e8
NC		 4730 case TAB (DBCCLBR, SHORT):
4731 case TAB (DBCCABSJ, SHORT):
4732 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4733 1, RELAX_RELOC_PC16);
151337e8
NC		 4734 fragP->fr_fix += 2;
4735 break;
4736 case TAB (DBCCLBR, LONG):
36759679
NC		 4737 /* Only DBcc instructions can come here.
4738 Change dbcc into dbcc/bral.
4739 JF: these used to be fr_opcode[2-7], but that's wrong. */
4740 if (flag_keep_pcrel)
6b6e92f4 4741 as_fatal (_("Tried to convert DBcc to absolute jump"));
28e7409f 4742
36759679 4743 *buffer_address++ = 0x00; /* Branch offset = 4. */
252b5132 4744 *buffer_address++ = 0x04;
36759679 4745 *buffer_address++ = 0x60; /* Put in bra pc+6. */
252b5132 4746 *buffer_address++ = 0x06;
151337e8
NC		 4747 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4748 *buffer_address++ = (char) 0xff;
252b5132 4749
36759679 4750 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4751 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4752 RELAX_RELOC_PC32);
252b5132 4753 fragP->fr_fix += 4;
252b5132 4754 break;
151337e8 4755 case TAB (DBCCABSJ, LONG):
36759679
NC		 4756 /* Only DBcc instructions can come here.
4757 Change dbcc into dbcc/jmp.
4758 JF: these used to be fr_opcode[2-7], but that's wrong. */
4759 if (flag_keep_pcrel)
6b6e92f4 4760 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4761
36759679 4762 *buffer_address++ = 0x00; /* Branch offset = 4. */
151337e8 4763 *buffer_address++ = 0x04;
36759679 4764 *buffer_address++ = 0x60; /* Put in bra pc + 6. */
151337e8 4765 *buffer_address++ = 0x06;
36759679 4766 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
151337e8
NC		 4767 *buffer_address++ = (char) 0xf9;
4768
36759679 4769 fragP->fr_fix += 6; /* Account for bra/jmp instructions. */
151337e8 4770 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4771 RELAX_RELOC_ABS32);
252b5132 4772 fragP->fr_fix += 4;
252b5132 4773 break;
151337e8 4774 case TAB (PCREL1632, SHORT):
252b5132
RH		 4775 fragP->fr_opcode[1] &= ~0x3F;
4776 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4777 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4778 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4779 fragP->fr_fix += 2;
252b5132 4780 break;
151337e8 4781 case TAB (PCREL1632, LONG):
252b5132
RH		 4782 /* Already set to mode 7.3; this indicates: PC indirect with
4783 suppressed index, 32-bit displacement. */
4784 *buffer_address++ = 0x01;
4785 *buffer_address++ = 0x70;
4786 fragP->fr_fix += 2;
151337e8 4787 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4788 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4789 fixP->fx_pcrel_adjust = 2;
4790 fragP->fr_fix += 4;
252b5132 4791 break;
252b5132 4792 case TAB (PCINDEX, BYTE):
252b5132
RH		 4793 assert (fragP->fr_fix >= 2);
4794 buffer_address[-2] &= ~1;
151337e8 4795 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4796 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4797 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4798 break;
4799 case TAB (PCINDEX, SHORT):
252b5132
RH		 4800 assert (fragP->fr_fix >= 2);
4801 buffer_address[-2] |= 0x1;
4802 buffer_address[-1] = 0x20;
4803 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4804 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4805 fixP->fx_pcrel_adjust = 2;
151337e8 4806 fragP->fr_fix += 2;
252b5132
RH		 4807 break;
4808 case TAB (PCINDEX, LONG):
252b5132
RH		 4809 assert (fragP->fr_fix >= 2);
4810 buffer_address[-2] |= 0x1;
4811 buffer_address[-1] = 0x30;
151337e8 4812 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4813 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4814 fixP->fx_pcrel_adjust = 2;
4815 fragP->fr_fix += 4;
4816 break;
4817 case TAB (ABSTOPCREL, SHORT):
4818 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4819 1, RELAX_RELOC_PC16);
151337e8
NC		 4820 fragP->fr_fix += 2;
4821 break;
4822 case TAB (ABSTOPCREL, LONG):
36759679 4823 if (flag_keep_pcrel)
6b6e92f4 4824 as_fatal (_("Tried to convert PC relative conditional branch to absolute jump"));
151337e8 4825 /* The thing to do here is force it to ABSOLUTE LONG, since
36759679 4826 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */
151337e8
NC		 4827 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4828 abort ();
4829 fragP->fr_opcode[1] &= ~0x3F;
4830 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4831 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4832 0, RELAX_RELOC_ABS32);
151337e8 4833 fragP->fr_fix += 4;
252b5132 4834 break;
252b5132
RH		 4835 }
4836}
4837
252b5132 4838void
31302357
AS		 4839md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
4840 segT sec ATTRIBUTE_UNUSED,
4841 fragS *fragP)
252b5132
RH		 4842{
4843 md_convert_frag_1 (fragP);
4844}
252b5132
RH		 4845
4846/* Force truly undefined symbols to their maximum size, and generally set up
4847 the frag list to be relaxed
4848 */
4849int
31302357 4850md_estimate_size_before_relax (fragS *fragP, segT segment)
252b5132 4851{
151337e8 4852 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4853 switch (fragP->fr_subtype)
4854 {
151337e8
NC		 4855 case TAB (BRANCHBWL, SZ_UNDEF):
4856 case TAB (BRABSJUNC, SZ_UNDEF):
151337e8 4857 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4858 {
151337e8
NC		 4859 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4860 && relaxable_symbol (fragP->fr_symbol))
252b5132 4861 {
151337e8
NC		 4862 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4863 }
4864 else if (flag_short_refs)
4865 {
4866 /* Symbol is undefined and we want short ref. */
4867 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4868 }
4869 else
4870 {
151337e8
NC		 4871 /* Symbol is still undefined. Make it LONG. */
4872 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4873 }
4874 break;
151337e8 4875 }
252b5132 4876
151337e8 4877 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4878 {
151337e8
NC		 4879 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4880 && relaxable_symbol (fragP->fr_symbol))
252b5132 4881 {
151337e8 4882 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4883 }
4884 else
4885 {
151337e8
NC		 4886 /* Symbol is undefined and we don't have long branches. */
4887 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4888 }
4889 break;
151337e8 4890 }
252b5132 4891
151337e8 4892 case TAB (FBRANCH, SZ_UNDEF):
151337e8
NC		 4893 case TAB (DBCCLBR, SZ_UNDEF):
4894 case TAB (DBCCABSJ, SZ_UNDEF):
5c65dbc1 4895 case TAB (PCREL1632, SZ_UNDEF):
252b5132 4896 {
8ec6253e
NC		 4897 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4898 && relaxable_symbol (fragP->fr_symbol))
151337e8 4899 || flag_short_refs)
252b5132 4900 {
151337e8 4901 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4902 }
4903 else
4904 {
151337e8 4905 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
252b5132
RH		 4906 }
4907 break;
151337e8 4908 }
81d4177b 4909
252b5132
RH		 4910 case TAB (PCINDEX, SZ_UNDEF):
4911 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4912 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4913 {
4914 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4915 }
4916 else
4917 {
4918 fragP->fr_subtype = TAB (PCINDEX, LONG);
252b5132
RH		 4919 }
4920 break;
4921
151337e8
NC		 4922 case TAB (ABSTOPCREL, SZ_UNDEF):
4923 {
4924 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4925 && relaxable_symbol (fragP->fr_symbol)))
4926 {
4927 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
151337e8
NC		 4928 }
4929 else
4930 {
4931 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
151337e8
NC		 4932 }
4933 break;
4934 }
4935
252b5132
RH		 4936 default:
4937 break;
4938 }
4939
151337e8 4940 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4941 switch (fragP->fr_subtype)
4942 {
151337e8
NC		 4943 case TAB (BRANCHBWL, BYTE):
4944 case TAB (BRABSJUNC, BYTE):
4945 case TAB (BRABSJCOND, BYTE):
4946 case TAB (BRANCHBW, BYTE):
252b5132 4947 /* We can't do a short jump to the next instruction, so in that
ac62c346
AM		 4948 case we force word mode. If the symbol is at the start of a
4949 frag, and it is the next frag with any data in it (usually
4950 this is just the next frag, but assembler listings may
4951 introduce empty frags), we must use word mode. */
4952 if (fragP->fr_symbol)
252b5132 4953 {
ac62c346 4954 fragS *sym_frag;
252b5132 4955
ac62c346
AM		 4956 sym_frag = symbol_get_frag (fragP->fr_symbol);
4957 if (S_GET_VALUE (fragP->fr_symbol) == sym_frag->fr_address)
252b5132 4958 {
ac62c346
AM		 4959 fragS *l;
4960
23b7f870 4961 for (l = fragP->fr_next; l && l != sym_frag; l = l->fr_next)
ac62c346
AM		 4962 if (l->fr_fix != 0)
4963 break;
4964 if (l == sym_frag)
4965 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4966 }
4967 }
4968 break;
4969 default:
4970 break;
4971 }
ac62c346 4972 return md_relax_table[fragP->fr_subtype].rlx_length;
252b5132
RH		 4973}
4974
4975#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4976/* the bit-field entries in the relocation_info struct plays hell
4977 with the byte-order problems of cross-assembly. So as a hack,
4978 I added this mach. dependent ri twiddler. Ugly, but it gets
36759679 4979 you there. -KWK */
252b5132
RH		 4980/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4981 are symbolnum, most sig. byte first. Last byte is broken up with
4982 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4983 nibble as nuthin. (on Sun 3 at least) */
4984/* Translate the internal relocation information into target-specific
92774660 4985 format. */
252b5132
RH		 4986#ifdef comment
4987void
31302357 4988md_ri_to_chars (char *the_bytes, struct reloc_info_generic *ri)
252b5132 4989{
36759679 4990 /* This is easy. */
252b5132 4991 md_number_to_chars (the_bytes, ri->r_address, 4);
36759679 4992 /* Now the fun stuff. */
252b5132 4993 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
36759679
NC		 4994 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4995 the_bytes[6] = ri->r_symbolnum & 0x0ff;
31302357
AS		 4996 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80)
4997 | ((ri->r_length << 5) & 0x60)
4998 | ((ri->r_extern << 4) & 0x10));
252b5132
RH		 4999}
5000
36759679 5001#endif
252b5132 5002
252b5132
RH		 5003#endif /* OBJ_AOUT or OBJ_BOUT */
5004
5005#ifndef WORKING_DOT_WORD
2b4f075a
HPN		 5006int md_short_jump_size = 4;
5007int md_long_jump_size = 6;
252b5132
RH		 5008
5009void
31302357
AS		 5010md_create_short_jump (char *ptr, addressT from_addr, addressT to_addr,
5011 fragS *frag ATTRIBUTE_UNUSED,
5012 symbolS *to_symbol ATTRIBUTE_UNUSED)
252b5132
RH		 5013{
5014 valueT offset;
5015
5016 offset = to_addr - (from_addr + 2);
5017
5018 md_number_to_chars (ptr, (valueT) 0x6000, 2);
5019 md_number_to_chars (ptr + 2, (valueT) offset, 2);
5020}
5021
5022void
31302357
AS		 5023md_create_long_jump (char *ptr, addressT from_addr, addressT to_addr,
5024 fragS *frag, symbolS *to_symbol)
252b5132
RH		 5025{
5026 valueT offset;
5027
6b6e92f4 5028 if (!HAVE_LONG_BRANCH (current_architecture))
252b5132 5029 {
36759679 5030 if (flag_keep_pcrel)
6b6e92f4 5031 as_fatal (_("Tried to convert PC relative branch to absolute jump"));
252b5132
RH		 5032 offset = to_addr - S_GET_VALUE (to_symbol);
5033 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
5034 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5035 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
5036 0, NO_RELOC);
5037 }
5038 else
5039 {
5040 offset = to_addr - (from_addr + 2);
5041 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
5042 md_number_to_chars (ptr + 2, (valueT) offset, 4);
5043 }
5044}
5045
5046#endif
5047
5048/* Different values of OK tell what its OK to return. Things that
5049 aren't OK are an error (what a shock, no?)
5050
5051 0: Everything is OK
3e602632
NC		 5052 10: Absolute 1:8 only
5053 20: Absolute 0:7 only
5054 30: absolute 0:15 only
5055 40: Absolute 0:31 only
5056 50: absolute 0:127 only
252b5132 5057 55: absolute -64:63 only
3e602632
NC		 5058 60: absolute -128:127 only
5059 70: absolute 0:4095 only
5060 80: absolute -1, 1:7 only
5061 90: No bignums. */
252b5132
RH		 5062
5063static int
31302357 5064get_num (struct m68k_exp *exp, int ok)
252b5132
RH		 5065{
5066 if (exp->exp.X_op == O_absent)
5067 {
36759679 5068 /* Do the same thing the VAX asm does. */
252b5132
RH		 5069 op (exp) = O_constant;
5070 adds (exp) = 0;
5071 subs (exp) = 0;
5072 offs (exp) = 0;
5073 if (ok == 10)
5074 {
5075 as_warn (_("expression out of range: defaulting to 1"));
5076 offs (exp) = 1;
5077 }
5078 }
5079 else if (exp->exp.X_op == O_constant)
5080 {
5081 switch (ok)
5082 {
5083 case 10:
bd17c2c3 5084 if ((valueT) TRUNC (offs (exp)) - 1 > 7)
252b5132
RH		 5085 {
5086 as_warn (_("expression out of range: defaulting to 1"));
5087 offs (exp) = 1;
5088 }
5089 break;
5090 case 20:
bd17c2c3 5091 if ((valueT) TRUNC (offs (exp)) > 7)
252b5132
RH		 5092 goto outrange;
5093 break;
5094 case 30:
bd17c2c3 5095 if ((valueT) TRUNC (offs (exp)) > 15)
252b5132
RH		 5096 goto outrange;
5097 break;
5098 case 40:
bd17c2c3 5099 if ((valueT) TRUNC (offs (exp)) > 32)
252b5132
RH		 5100 goto outrange;
5101 break;
5102 case 50:
bd17c2c3 5103 if ((valueT) TRUNC (offs (exp)) > 127)
252b5132
RH		 5104 goto outrange;
5105 break;
5106 case 55:
bd17c2c3 5107 if ((valueT) SEXT (offs (exp)) + 64 > 127)
252b5132
RH		 5108 goto outrange;
5109 break;
5110 case 60:
bd17c2c3 5111 if ((valueT) SEXT (offs (exp)) + 128 > 255)
252b5132
RH		 5112 goto outrange;
5113 break;
5114 case 70:
bd17c2c3 5115 if ((valueT) TRUNC (offs (exp)) > 4095)
252b5132
RH		 5116 {
5117 outrange:
5118 as_warn (_("expression out of range: defaulting to 0"));
5119 offs (exp) = 0;
5120 }
5121 break;
3e602632 5122 case 80:
bd17c2c3
AM		 5123 if ((valueT) TRUNC (offs (exp)) != 0xffffffff
5124 && (valueT) TRUNC (offs (exp)) - 1 > 6)
3e602632
NC		 5125 {
5126 as_warn (_("expression out of range: defaulting to 1"));
5127 offs (exp) = 1;
5128 }
5129 break;
252b5132
RH		 5130 default:
5131 break;
5132 }
5133 }
5134 else if (exp->exp.X_op == O_big)
5135 {
36759679 5136 if (offs (exp) <= 0 /* flonum. */
3e602632 5137 && (ok == 90 /* no bignums */
36759679 5138 || (ok > 10 /* Small-int ranges including 0 ok. */
252b5132
RH		 5139 /* If we have a flonum zero, a zero integer should
5140 do as well (e.g., in moveq). */
5141 && generic_floating_point_number.exponent == 0
5142 && generic_floating_point_number.low[0] == 0)))
5143 {
36759679 5144 /* HACK! Turn it into a long. */
252b5132
RH		 5145 LITTLENUM_TYPE words[6];
5146
36759679 5147 gen_to_words (words, 2, 8L); /* These numbers are magic! */
252b5132
RH		 5148 op (exp) = O_constant;
5149 adds (exp) = 0;
5150 subs (exp) = 0;
5151 offs (exp) = words[1] | (words[0] << 16);
5152 }
5153 else if (ok != 0)
5154 {
5155 op (exp) = O_constant;
5156 adds (exp) = 0;
5157 subs (exp) = 0;
5158 offs (exp) = (ok == 10) ? 1 : 0;
5159 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5160 (long) offs (exp));
252b5132
RH		 5161 }
5162 }
5163 else
5164 {
3e602632 5165 if (ok >= 10 && ok <= 80)
252b5132
RH		 5166 {
5167 op (exp) = O_constant;
5168 adds (exp) = 0;
5169 subs (exp) = 0;
5170 offs (exp) = (ok == 10) ? 1 : 0;
5171 as_warn (_("Can't deal with expression; defaulting to %ld"),
045b540e 5172 (long) offs (exp));
252b5132
RH		 5173 }
5174 }
5175
5176 if (exp->size != SIZE_UNSPEC)
5177 {
5178 switch (exp->size)
5179 {
5180 case SIZE_UNSPEC:
5181 case SIZE_LONG:
5182 break;
5183 case SIZE_BYTE:
5184 if (!isbyte (offs (exp)))
5185 as_warn (_("expression doesn't fit in BYTE"));
5186 break;
5187 case SIZE_WORD:
5188 if (!isword (offs (exp)))
5189 as_warn (_("expression doesn't fit in WORD"));
5190 break;
5191 }
5192 }
5193
5194 return offs (exp);
5195}
5196
5197/* These are the back-ends for the various machine dependent pseudo-ops. */
5198
5199static void
31302357 5200s_data1 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5201{
5202 subseg_set (data_section, 1);
5203 demand_empty_rest_of_line ();
5204}
5205
5206static void
31302357 5207s_data2 (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5208{
5209 subseg_set (data_section, 2);
5210 demand_empty_rest_of_line ();
5211}
5212
5213static void
31302357 5214s_bss (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5215{
5216 /* We don't support putting frags in the BSS segment, we fake it
5217 by marking in_bss, then looking at s_skip for clues. */
5218
5219 subseg_set (bss_section, 0);
5220 demand_empty_rest_of_line ();
5221}
5222
5223static void
31302357 5224s_even (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5225{
5226 register int temp;
5227 register long temp_fill;
5228
5229 temp = 1; /* JF should be 2? */
5230 temp_fill = get_absolute_expression ();
92774660 5231 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5232 frag_align (temp, (int) temp_fill, 0);
5233 demand_empty_rest_of_line ();
5234 record_alignment (now_seg, temp);
5235}
5236
5237static void
31302357 5238s_proc (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5239{
5240 demand_empty_rest_of_line ();
5241}
5242\f
5243/* Pseudo-ops handled for MRI compatibility. */
5244
5245/* This function returns non-zero if the argument is a conditional
5246 pseudo-op. This is called when checking whether a pending
5247 alignment is needed. */
5248
5249int
31302357 5250m68k_conditional_pseudoop (pseudo_typeS *pop)
252b5132
RH		 5251{
5252 return (pop->poc_handler == s_mri_if
5253 || pop->poc_handler == s_mri_else);
5254}
5255
5256/* Handle an MRI style chip specification. */
5257
5258static void
31302357 5259mri_chip (void)
252b5132
RH		 5260{
5261 char *s;
5262 char c;
5263 int i;
5264
5265 s = input_line_pointer;
5266 /* We can't use get_symbol_end since the processor names are not proper
5267 symbols. */
5268 while (is_part_of_name (c = *input_line_pointer++))
5269 ;
5270 *--input_line_pointer = 0;
266abb8f
NS		 5271 for (i = 0; m68k_cpus[i].name; i++)
5272 if (strcasecmp (s, m68k_cpus[i].name) == 0)
252b5132 5273 break;
266abb8f 5274 if (!m68k_cpus[i].name)
252b5132
RH		 5275 {
5276 as_bad (_("%s: unrecognized processor name"), s);
5277 *input_line_pointer = c;
5278 ignore_rest_of_line ();
5279 return;
5280 }
5281 *input_line_pointer = c;
5282
5283 if (*input_line_pointer == '/')
5284 current_architecture = 0;
5285 else
5286 current_architecture &= m68881 | m68851;
266abb8f 5287 current_architecture |= m68k_cpus[i].arch & ~(m68881 | m68851);
2da12c60 5288 control_regs = m68k_cpus[i].control_regs;
252b5132
RH		 5289
5290 while (*input_line_pointer == '/')
5291 {
5292 ++input_line_pointer;
5293 s = input_line_pointer;
5294 /* We can't use get_symbol_end since the processor names are not
5295 proper symbols. */
5296 while (is_part_of_name (c = *input_line_pointer++))
5297 ;
5298 *--input_line_pointer = 0;
5299 if (strcmp (s, "68881") == 0)
5300 current_architecture |= m68881;
5301 else if (strcmp (s, "68851") == 0)
5302 current_architecture |= m68851;
5303 *input_line_pointer = c;
5304 }
252b5132
RH		 5305}
5306
5307/* The MRI CHIP pseudo-op. */
5308
5309static void
31302357 5310s_chip (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5311{
5312 char *stop = NULL;
5313 char stopc;
5314
5315 if (flag_mri)
5316 stop = mri_comment_field (&stopc);
5317 mri_chip ();
5318 if (flag_mri)
5319 mri_comment_end (stop, stopc);
5320 demand_empty_rest_of_line ();
5321}
5322
5323/* The MRI FOPT pseudo-op. */
5324
5325static void
31302357 5326s_fopt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5327{
5328 SKIP_WHITESPACE ();
5329
5330 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5331 {
5332 int temp;
5333
5334 input_line_pointer += 3;
5335 temp = get_absolute_expression ();
5336 if (temp < 0 || temp > 7)
5337 as_bad (_("bad coprocessor id"));
5338 else
5339 m68k_float_copnum = COP0 + temp;
5340 }
5341 else
5342 {
5343 as_bad (_("unrecognized fopt option"));
5344 ignore_rest_of_line ();
5345 return;
5346 }
5347
5348 demand_empty_rest_of_line ();
5349}
5350
5351/* The structure used to handle the MRI OPT pseudo-op. */
5352
5353struct opt_action
5354{
5355 /* The name of the option. */
5356 const char *name;
5357
5358 /* If this is not NULL, just call this function. The first argument
5359 is the ARG field of this structure, the second argument is
5360 whether the option was negated. */
31302357 5361 void (*pfn) (int arg, int on);
252b5132
RH		 5362
5363 /* If this is not NULL, and the PFN field is NULL, set the variable
5364 this points to. Set it to the ARG field if the option was not
5365 negated, and the NOTARG field otherwise. */
5366 int *pvar;
5367
5368 /* The value to pass to PFN or to assign to *PVAR. */
5369 int arg;
5370
5371 /* The value to assign to *PVAR if the option is negated. If PFN is
5372 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5373 the option may not be negated. */
5374 int notarg;
5375};
5376
5377/* The table used to handle the MRI OPT pseudo-op. */
5378
31302357
AS		 5379static void skip_to_comma (int, int);
5380static void opt_nest (int, int);
5381static void opt_chip (int, int);
5382static void opt_list (int, int);
5383static void opt_list_symbols (int, int);
252b5132
RH		 5384
5385static const struct opt_action opt_table[] =
5386{
5387 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5388
5389 /* We do relaxing, so there is little use for these options. */
5390 { "b", 0, 0, 0, 0 },
5391 { "brs", 0, 0, 0, 0 },
5392 { "brb", 0, 0, 0, 0 },
5393 { "brl", 0, 0, 0, 0 },
5394 { "brw", 0, 0, 0, 0 },
5395
5396 { "c", 0, 0, 0, 0 },
5397 { "cex", 0, 0, 0, 0 },
5398 { "case", 0, &symbols_case_sensitive, 1, 0 },
5399 { "cl", 0, 0, 0, 0 },
5400 { "cre", 0, 0, 0, 0 },
5401 { "d", 0, &flag_keep_locals, 1, 0 },
5402 { "e", 0, 0, 0, 0 },
5403 { "f", 0, &flag_short_refs, 1, 0 },
5404 { "frs", 0, &flag_short_refs, 1, 0 },
5405 { "frl", 0, &flag_short_refs, 0, 1 },
5406 { "g", 0, 0, 0, 0 },
5407 { "i", 0, 0, 0, 0 },
5408 { "m", 0, 0, 0, 0 },
5409 { "mex", 0, 0, 0, 0 },
5410 { "mc", 0, 0, 0, 0 },
5411 { "md", 0, 0, 0, 0 },
5412 { "nest", opt_nest, 0, 0, 0 },
5413 { "next", skip_to_comma, 0, 0, 0 },
5414 { "o", 0, 0, 0, 0 },
5415 { "old", 0, 0, 0, 0 },
5416 { "op", skip_to_comma, 0, 0, 0 },
5417 { "pco", 0, 0, 0, 0 },
5418 { "p", opt_chip, 0, 0, 0 },
5419 { "pcr", 0, 0, 0, 0 },
5420 { "pcs", 0, 0, 0, 0 },
5421 { "r", 0, 0, 0, 0 },
5422 { "quick", 0, &m68k_quick, 1, 0 },
5423 { "rel32", 0, &m68k_rel32, 1, 0 },
5424 { "s", opt_list, 0, 0, 0 },
5425 { "t", opt_list_symbols, 0, 0, 0 },
5426 { "w", 0, &flag_no_warnings, 0, 1 },
5427 { "x", 0, 0, 0, 0 }
5428};
5429
8fce3f5e 5430#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5431
5432/* The MRI OPT pseudo-op. */
5433
5434static void
31302357 5435s_opt (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5436{
5437 do
5438 {
5439 int t;
5440 char *s;
5441 char c;
5442 int i;
5443 const struct opt_action *o;
5444
5445 SKIP_WHITESPACE ();
5446
5447 t = 1;
5448 if (*input_line_pointer == '-')
5449 {
5450 ++input_line_pointer;
5451 t = 0;
5452 }
5453 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5454 {
5455 input_line_pointer += 2;
5456 t = 0;
5457 }
5458
5459 s = input_line_pointer;
5460 c = get_symbol_end ();
5461
5462 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5463 {
5464 if (strcasecmp (s, o->name) == 0)
5465 {
5466 if (o->pfn)
5467 {
5468 /* Restore input_line_pointer now in case the option
5469 takes arguments. */
5470 *input_line_pointer = c;
5471 (*o->pfn) (o->arg, t);
5472 }
5473 else if (o->pvar != NULL)
5474 {
5475 if (! t && o->arg == o->notarg)
5476 as_bad (_("option `%s' may not be negated"), s);
5477 *input_line_pointer = c;
5478 *o->pvar = t ? o->arg : o->notarg;
5479 }
5480 else
5481 *input_line_pointer = c;
5482 break;
5483 }
5484 }
5485 if (i >= OPTCOUNT)
5486 {
5487 as_bad (_("option `%s' not recognized"), s);
5488 *input_line_pointer = c;
5489 }
5490 }
5491 while (*input_line_pointer++ == ',');
5492
5493 /* Move back to terminating character. */
5494 --input_line_pointer;
5495 demand_empty_rest_of_line ();
5496}
5497
5498/* Skip ahead to a comma. This is used for OPT options which we do
67c1ffbe 5499 not support and which take arguments. */
252b5132
RH		 5500
5501static void
31302357 5502skip_to_comma (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5503{
5504 while (*input_line_pointer != ','
5505 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5506 ++input_line_pointer;
5507}
5508
5509/* Handle the OPT NEST=depth option. */
5510
5511static void
31302357 5512opt_nest (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5513{
5514 if (*input_line_pointer != '=')
5515 {
5516 as_bad (_("bad format of OPT NEST=depth"));
5517 return;
5518 }
5519
5520 ++input_line_pointer;
5521 max_macro_nest = get_absolute_expression ();
5522}
5523
5524/* Handle the OPT P=chip option. */
5525
5526static void
31302357 5527opt_chip (int arg ATTRIBUTE_UNUSED, int on ATTRIBUTE_UNUSED)
252b5132
RH		 5528{
5529 if (*input_line_pointer != '=')
5530 {
5531 /* This is just OPT P, which we do not support. */
5532 return;
5533 }
5534
5535 ++input_line_pointer;
5536 mri_chip ();
5537}
5538
5539/* Handle the OPT S option. */
5540
5541static void
31302357 5542opt_list (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5543{
5544 listing_list (on);
5545}
5546
5547/* Handle the OPT T option. */
5548
5549static void
31302357 5550opt_list_symbols (int arg ATTRIBUTE_UNUSED, int on)
252b5132
RH		 5551{
5552 if (on)
5553 listing |= LISTING_SYMBOLS;
5554 else
8a104df9 5555 listing &= ~LISTING_SYMBOLS;
252b5132
RH		 5556}
5557
5558/* Handle the MRI REG pseudo-op. */
5559
5560static void
31302357 5561s_reg (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5562{
5563 char *s;
5564 int c;
5565 struct m68k_op rop;
5566 int mask;
5567 char *stop = NULL;
5568 char stopc;
5569
5570 if (line_label == NULL)
5571 {
5572 as_bad (_("missing label"));
5573 ignore_rest_of_line ();
5574 return;
5575 }
5576
5577 if (flag_mri)
5578 stop = mri_comment_field (&stopc);
5579
5580 SKIP_WHITESPACE ();
5581
5582 s = input_line_pointer;
3882b010 5583 while (ISALNUM (*input_line_pointer)
252b5132
RH		 5584#ifdef REGISTER_PREFIX
5585 || *input_line_pointer == REGISTER_PREFIX
5586#endif
5587 || *input_line_pointer == '/'
5588 || *input_line_pointer == '-')
5589 ++input_line_pointer;
5590 c = *input_line_pointer;
5591 *input_line_pointer = '\0';
5592
5593 if (m68k_ip_op (s, &rop) != 0)
5594 {
5595 if (rop.error == NULL)
5596 as_bad (_("bad register list"));
5597 else
5598 as_bad (_("bad register list: %s"), rop.error);
5599 *input_line_pointer = c;
5600 ignore_rest_of_line ();
5601 return;
5602 }
5603
5604 *input_line_pointer = c;
5605
5606 if (rop.mode == REGLST)
5607 mask = rop.mask;
5608 else if (rop.mode == DREG)
5609 mask = 1 << (rop.reg - DATA0);
5610 else if (rop.mode == AREG)
5611 mask = 1 << (rop.reg - ADDR0 + 8);
5612 else if (rop.mode == FPREG)
5613 mask = 1 << (rop.reg - FP0 + 16);
5614 else if (rop.mode == CONTROL
5615 && rop.reg == FPI)
5616 mask = 1 << 24;
5617 else if (rop.mode == CONTROL
5618 && rop.reg == FPS)
5619 mask = 1 << 25;
5620 else if (rop.mode == CONTROL
5621 && rop.reg == FPC)
5622 mask = 1 << 26;
5623 else
5624 {
5625 as_bad (_("bad register list"));
5626 ignore_rest_of_line ();
5627 return;
5628 }
5629
5630 S_SET_SEGMENT (line_label, reg_section);
5631 S_SET_VALUE (line_label, ~mask);
49309057 5632 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5633
5634 if (flag_mri)
5635 mri_comment_end (stop, stopc);
5636
5637 demand_empty_rest_of_line ();
5638}
5639
5640/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5641
5642struct save_opts
5643{
5644 struct save_opts *next;
5645 int abspcadd;
5646 int symbols_case_sensitive;
5647 int keep_locals;
5648 int short_refs;
5649 int architecture;
2da12c60 5650 const enum m68k_register *control_regs;
252b5132
RH		 5651 int quick;
5652 int rel32;
5653 int listing;
5654 int no_warnings;
5655 /* FIXME: We don't save OPT S. */
5656};
5657
5658/* This variable holds the stack of saved options. */
5659
5660static struct save_opts *save_stack;
5661
5662/* The MRI SAVE pseudo-op. */
5663
5664static void
31302357 5665s_save (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5666{
5667 struct save_opts *s;
5668
5669 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5670 s->abspcadd = m68k_abspcadd;
5671 s->symbols_case_sensitive = symbols_case_sensitive;
5672 s->keep_locals = flag_keep_locals;
5673 s->short_refs = flag_short_refs;
5674 s->architecture = current_architecture;
2da12c60 5675 s->control_regs = control_regs;
252b5132
RH		 5676 s->quick = m68k_quick;
5677 s->rel32 = m68k_rel32;
5678 s->listing = listing;
5679 s->no_warnings = flag_no_warnings;
5680
5681 s->next = save_stack;
5682 save_stack = s;
5683
5684 demand_empty_rest_of_line ();
5685}
5686
5687/* The MRI RESTORE pseudo-op. */
5688
5689static void
31302357 5690s_restore (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 5691{
5692 struct save_opts *s;
5693
5694 if (save_stack == NULL)
5695 {
5696 as_bad (_("restore without save"));
5697 ignore_rest_of_line ();
5698 return;
5699 }
5700
5701 s = save_stack;
5702 save_stack = s->next;
5703
5704 m68k_abspcadd = s->abspcadd;
5705 symbols_case_sensitive = s->symbols_case_sensitive;
5706 flag_keep_locals = s->keep_locals;
5707 flag_short_refs = s->short_refs;
5708 current_architecture = s->architecture;
2da12c60 5709 control_regs = s->control_regs;
252b5132
RH		 5710 m68k_quick = s->quick;
5711 m68k_rel32 = s->rel32;
5712 listing = s->listing;
5713 flag_no_warnings = s->no_warnings;
5714
5715 free (s);
5716
5717 demand_empty_rest_of_line ();
5718}
5719
5720/* Types of MRI structured control directives. */
5721
5722enum mri_control_type
5723{
5724 mri_for,
5725 mri_if,
5726 mri_repeat,
5727 mri_while
5728};
5729
5730/* This structure is used to stack the MRI structured control
5731 directives. */
5732
5733struct mri_control_info
5734{
5735 /* The directive within which this one is enclosed. */
5736 struct mri_control_info *outer;
5737
5738 /* The type of directive. */
5739 enum mri_control_type type;
5740
5741 /* Whether an ELSE has been in an IF. */
5742 int else_seen;
5743
5744 /* The add or sub statement at the end of a FOR. */
5745 char *incr;
5746
5747 /* The label of the top of a FOR or REPEAT loop. */
5748 char *top;
5749
5750 /* The label to jump to for the next iteration, or the else
5751 expression of a conditional. */
5752 char *next;
5753
5754 /* The label to jump to to break out of the loop, or the label past
5755 the end of a conditional. */
5756 char *bottom;
5757};
5758
5759/* The stack of MRI structured control directives. */
5760
5761static struct mri_control_info *mri_control_stack;
5762
5763/* The current MRI structured control directive index number, used to
5764 generate label names. */
5765
5766static int mri_control_index;
5767
252b5132
RH		 5768/* Assemble an instruction for an MRI structured control directive. */
5769
5770static void
31302357 5771mri_assemble (char *str)
252b5132
RH		 5772{
5773 char *s;
5774
5775 /* md_assemble expects the opcode to be in lower case. */
5776 for (s = str; *s != ' ' && *s != '\0'; s++)
3882b010 5777 *s = TOLOWER (*s);
252b5132
RH		 5778
5779 md_assemble (str);
5780}
5781
5782/* Generate a new MRI label structured control directive label name. */
5783
5784static char *
31302357 5785mri_control_label (void)
252b5132
RH		 5786{
5787 char *n;
5788
5789 n = (char *) xmalloc (20);
5790 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5791 ++mri_control_index;
5792 return n;
5793}
5794
5795/* Create a new MRI structured control directive. */
5796
5797static struct mri_control_info *
31302357 5798push_mri_control (enum mri_control_type type)
252b5132
RH		 5799{
5800 struct mri_control_info *n;
5801
5802 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5803
5804 n->type = type;
5805 n->else_seen = 0;
5806 if (type == mri_if || type == mri_while)
5807 n->top = NULL;
5808 else
5809 n->top = mri_control_label ();
5810 n->next = mri_control_label ();
5811 n->bottom = mri_control_label ();
5812
5813 n->outer = mri_control_stack;
5814 mri_control_stack = n;
5815
5816 return n;
5817}
5818
5819/* Pop off the stack of MRI structured control directives. */
5820
5821static void
31302357 5822pop_mri_control (void)
252b5132
RH		 5823{
5824 struct mri_control_info *n;
5825
5826 n = mri_control_stack;
5827 mri_control_stack = n->outer;
5828 if (n->top != NULL)
5829 free (n->top);
5830 free (n->next);
5831 free (n->bottom);
5832 free (n);
5833}
5834
5835/* Recognize a condition code in an MRI structured control expression. */
5836
5837static int
31302357 5838parse_mri_condition (int *pcc)
252b5132
RH		 5839{
5840 char c1, c2;
5841
5842 know (*input_line_pointer == '<');
5843
5844 ++input_line_pointer;
5845 c1 = *input_line_pointer++;
5846 c2 = *input_line_pointer++;
5847
5848 if (*input_line_pointer != '>')
5849 {
5850 as_bad (_("syntax error in structured control directive"));
5851 return 0;
5852 }
5853
5854 ++input_line_pointer;
5855 SKIP_WHITESPACE ();
5856
3882b010
L		 5857 c1 = TOLOWER (c1);
5858 c2 = TOLOWER (c2);
252b5132
RH		 5859
5860 *pcc = (c1 << 8) | c2;
5861
5862 return 1;
5863}
5864
5865/* Parse a single operand in an MRI structured control expression. */
5866
5867static int
31302357
AS		 5868parse_mri_control_operand (int *pcc, char **leftstart, char **leftstop,
5869 char **rightstart, char **rightstop)
252b5132
RH		 5870{
5871 char *s;
5872
5873 SKIP_WHITESPACE ();
5874
5875 *pcc = -1;
5876 *leftstart = NULL;
5877 *leftstop = NULL;
5878 *rightstart = NULL;
5879 *rightstop = NULL;
5880
5881 if (*input_line_pointer == '<')
5882 {
5883 /* It's just a condition code. */
5884 return parse_mri_condition (pcc);
5885 }
5886
5887 /* Look ahead for the condition code. */
5888 for (s = input_line_pointer; *s != '\0'; ++s)
5889 {
5890 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5891 break;
5892 }
5893 if (*s == '\0')
5894 {
5895 as_bad (_("missing condition code in structured control directive"));
5896 return 0;
5897 }
5898
5899 *leftstart = input_line_pointer;
5900 *leftstop = s;
5901 if (*leftstop > *leftstart
5902 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5903 --*leftstop;
5904
5905 input_line_pointer = s;
5906 if (! parse_mri_condition (pcc))
5907 return 0;
5908
5909 /* Look ahead for AND or OR or end of line. */
5910 for (s = input_line_pointer; *s != '\0'; ++s)
5911 {
e1f44d10
NC		 5912 /* We must make sure we don't misinterpret AND/OR at the end of labels!
5913 if d0 <eq> #FOOAND and d1 <ne> #BAROR then
5914 ^^^ ^^ */
8a104df9
KH		 5915 if ((s == input_line_pointer
5916 || *(s-1) == ' '
5917 || *(s-1) == '\t')
5918 && ((strncasecmp (s, "AND", 3) == 0
5919 && (s[3] == '.' || ! is_part_of_name (s[3])))
5920 || (strncasecmp (s, "OR", 2) == 0
5921 && (s[2] == '.' || ! is_part_of_name (s[2])))))
5922 break;
252b5132
RH		 5923 }
5924
5925 *rightstart = input_line_pointer;
5926 *rightstop = s;
5927 if (*rightstop > *rightstart
5928 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5929 --*rightstop;
5930
5931 input_line_pointer = s;
5932
5933 return 1;
5934}
5935
5936#define MCC(b1, b2) (((b1) << 8) | (b2))
5937
5938/* Swap the sense of a condition. This changes the condition so that
5939 it generates the same result when the operands are swapped. */
5940
5941static int
31302357 5942swap_mri_condition (int cc)
252b5132
RH		 5943{
5944 switch (cc)
5945 {
5946 case MCC ('h', 'i'): return MCC ('c', 's');
5947 case MCC ('l', 's'): return MCC ('c', 'c');
36759679 5948 /* <HS> is an alias for <CC>. */
e1f44d10 5949 case MCC ('h', 's'):
252b5132 5950 case MCC ('c', 'c'): return MCC ('l', 's');
36759679 5951 /* <LO> is an alias for <CS>. */
e1f44d10 5952 case MCC ('l', 'o'):
252b5132
RH		 5953 case MCC ('c', 's'): return MCC ('h', 'i');
5954 case MCC ('p', 'l'): return MCC ('m', 'i');
5955 case MCC ('m', 'i'): return MCC ('p', 'l');
5956 case MCC ('g', 'e'): return MCC ('l', 'e');
5957 case MCC ('l', 't'): return MCC ('g', 't');
5958 case MCC ('g', 't'): return MCC ('l', 't');
5959 case MCC ('l', 'e'): return MCC ('g', 'e');
36759679 5960 /* Issue a warning for conditions we can not swap. */
e1f44d10
NC		 5961 case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here
5962 case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem
5963 case MCC ('v', 'c'):
5964 case MCC ('v', 's'):
5965 default :
5966 as_warn (_("Condition <%c%c> in structured control directive can not be encoded correctly"),
5967 (char) (cc >> 8), (char) (cc));
5968 break;
252b5132
RH		 5969 }
5970 return cc;
5971}
5972
5973/* Reverse the sense of a condition. */
5974
5975static int
31302357 5976reverse_mri_condition (int cc)
252b5132
RH		 5977{
5978 switch (cc)
5979 {
5980 case MCC ('h', 'i'): return MCC ('l', 's');
5981 case MCC ('l', 's'): return MCC ('h', 'i');
e1f44d10
NC		 5982 /* <HS> is an alias for <CC> */
5983 case MCC ('h', 's'): return MCC ('l', 'o');
252b5132 5984 case MCC ('c', 'c'): return MCC ('c', 's');
e1f44d10
NC		 5985 /* <LO> is an alias for <CS> */
5986 case MCC ('l', 'o'): return MCC ('h', 's');
252b5132
RH		 5987 case MCC ('c', 's'): return MCC ('c', 'c');
5988 case MCC ('n', 'e'): return MCC ('e', 'q');
5989 case MCC ('e', 'q'): return MCC ('n', 'e');
5990 case MCC ('v', 'c'): return MCC ('v', 's');
5991 case MCC ('v', 's'): return MCC ('v', 'c');
5992 case MCC ('p', 'l'): return MCC ('m', 'i');
5993 case MCC ('m', 'i'): return MCC ('p', 'l');
5994 case MCC ('g', 'e'): return MCC ('l', 't');
5995 case MCC ('l', 't'): return MCC ('g', 'e');
5996 case MCC ('g', 't'): return MCC ('l', 'e');
5997 case MCC ('l', 'e'): return MCC ('g', 't');
5998 }
5999 return cc;
6000}
6001
6002/* Build an MRI structured control expression. This generates test
6003 and branch instructions. It goes to TRUELAB if the condition is
6004 true, and to FALSELAB if the condition is false. Exactly one of
6005 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
6006 is the size qualifier for the expression. EXTENT is the size to
6007 use for the branch. */
6008
6009static void
31302357
AS		 6010build_mri_control_operand (int qual, int cc, char *leftstart, char *leftstop,
6011 char *rightstart, char *rightstop,
6012 const char *truelab, const char *falselab,
6013 int extent)
252b5132
RH		 6014{
6015 char *buf;
6016 char *s;
6017
6018 if (leftstart != NULL)
6019 {
6020 struct m68k_op leftop, rightop;
6021 char c;
6022
6023 /* Swap the compare operands, if necessary, to produce a legal
6024 m68k compare instruction. Comparing a register operand with
6025 a non-register operand requires the register to be on the
6026 right (cmp, cmpa). Comparing an immediate value with
6027 anything requires the immediate value to be on the left
6028 (cmpi). */
6029
6030 c = *leftstop;
6031 *leftstop = '\0';
6032 (void) m68k_ip_op (leftstart, &leftop);
6033 *leftstop = c;
6034
6035 c = *rightstop;
6036 *rightstop = '\0';
6037 (void) m68k_ip_op (rightstart, &rightop);
6038 *rightstop = c;
6039
6040 if (rightop.mode == IMMED
6041 || ((leftop.mode == DREG || leftop.mode == AREG)
6042 && (rightop.mode != DREG && rightop.mode != AREG)))
6043 {
6044 char *temp;
6045
31302357
AS		 6046 /* Correct conditional handling:
6047 if #1 <lt> d0 then ;means if (1 < d0)
6048 ...
6049 endi
e1f44d10 6050
31302357 6051 should assemble to:
e1f44d10 6052
31302357
AS		 6053 cmp #1,d0 if we do *not* swap the operands
6054 bgt true we need the swapped condition!
6055 ble false
6056 true:
6057 ...
6058 false:
6059 */
252b5132
RH		 6060 temp = leftstart;
6061 leftstart = rightstart;
6062 rightstart = temp;
6063 temp = leftstop;
6064 leftstop = rightstop;
6065 rightstop = temp;
8a104df9
KH		 6066 }
6067 else
6068 {
e1f44d10 6069 cc = swap_mri_condition (cc);
252b5132
RH		 6070 }
6071 }
6072
6073 if (truelab == NULL)
6074 {
6075 cc = reverse_mri_condition (cc);
6076 truelab = falselab;
6077 }
92774660 6078
252b5132
RH		 6079 if (leftstart != NULL)
6080 {
6081 buf = (char *) xmalloc (20
6082 + (leftstop - leftstart)
6083 + (rightstop - rightstart));
6084 s = buf;
6085 *s++ = 'c';
6086 *s++ = 'm';
6087 *s++ = 'p';
6088 if (qual != '\0')
3882b010 6089 *s++ = TOLOWER (qual);
252b5132
RH		 6090 *s++ = ' ';
6091 memcpy (s, leftstart, leftstop - leftstart);
6092 s += leftstop - leftstart;
6093 *s++ = ',';
6094 memcpy (s, rightstart, rightstop - rightstart);
6095 s += rightstop - rightstart;
6096 *s = '\0';
6097 mri_assemble (buf);
6098 free (buf);
6099 }
92774660 6100
252b5132
RH		 6101 buf = (char *) xmalloc (20 + strlen (truelab));
6102 s = buf;
6103 *s++ = 'b';
6104 *s++ = cc >> 8;
6105 *s++ = cc & 0xff;
6106 if (extent != '\0')
3882b010 6107 *s++ = TOLOWER (extent);
252b5132
RH		 6108 *s++ = ' ';
6109 strcpy (s, truelab);
6110 mri_assemble (buf);
6111 free (buf);
6112}
6113
6114/* Parse an MRI structured control expression. This generates test
6115 and branch instructions. STOP is where the expression ends. It
6116 goes to TRUELAB if the condition is true, and to FALSELAB if the
6117 condition is false. Exactly one of TRUELAB and FALSELAB will be
6118 NULL, meaning to fall through. QUAL is the size qualifier for the
6119 expression. EXTENT is the size to use for the branch. */
6120
6121static void
31302357
AS		 6122parse_mri_control_expression (char *stop, int qual, const char *truelab,
6123 const char *falselab, int extent)
252b5132
RH		 6124{
6125 int c;
6126 int cc;
6127 char *leftstart;
6128 char *leftstop;
6129 char *rightstart;
6130 char *rightstop;
6131
6132 c = *stop;
6133 *stop = '\0';
6134
6135 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6136 &rightstart, &rightstop))
6137 {
6138 *stop = c;
6139 return;
6140 }
6141
6142 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
6143 {
6144 const char *flab;
6145
6146 if (falselab != NULL)
6147 flab = falselab;
6148 else
6149 flab = mri_control_label ();
6150
6151 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6152 rightstop, (const char *) NULL, flab, extent);
6153
6154 input_line_pointer += 3;
6155 if (*input_line_pointer != '.'
6156 || input_line_pointer[1] == '\0')
6157 qual = '\0';
6158 else
6159 {
6160 qual = input_line_pointer[1];
6161 input_line_pointer += 2;
6162 }
6163
6164 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6165 &rightstart, &rightstop))
6166 {
6167 *stop = c;
6168 return;
6169 }
6170
6171 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6172 rightstop, truelab, falselab, extent);
6173
6174 if (falselab == NULL)
6175 colon (flab);
6176 }
6177 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6178 {
6179 const char *tlab;
6180
6181 if (truelab != NULL)
6182 tlab = truelab;
6183 else
6184 tlab = mri_control_label ();
6185
6186 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6187 rightstop, tlab, (const char *) NULL, extent);
6188
6189 input_line_pointer += 2;
6190 if (*input_line_pointer != '.'
6191 || input_line_pointer[1] == '\0')
6192 qual = '\0';
6193 else
6194 {
6195 qual = input_line_pointer[1];
6196 input_line_pointer += 2;
6197 }
6198
6199 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6200 &rightstart, &rightstop))
6201 {
6202 *stop = c;
6203 return;
6204 }
6205
6206 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6207 rightstop, truelab, falselab, extent);
6208
6209 if (truelab == NULL)
6210 colon (tlab);
6211 }
6212 else
6213 {
6214 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6215 rightstop, truelab, falselab, extent);
6216 }
6217
6218 *stop = c;
6219 if (input_line_pointer != stop)
6220 as_bad (_("syntax error in structured control directive"));
6221}
6222
6223/* Handle the MRI IF pseudo-op. This may be a structured control
6224 directive, or it may be a regular assembler conditional, depending
6225 on its operands. */
6226
6227static void
31302357 6228s_mri_if (int qual)
252b5132
RH		 6229{
6230 char *s;
6231 int c;
6232 struct mri_control_info *n;
6233
6234 /* A structured control directive must end with THEN with an
6235 optional qualifier. */
6236 s = input_line_pointer;
e1f44d10
NC		 6237 /* We only accept '*' as introduction of comments if preceded by white space
6238 or at first column of a line (I think this can't actually happen here?)
6239 This is important when assembling:
6240 if d0 <ne> 12(a0,d0*2) then
36759679 6241 if d0 <ne> #CONST*20 then. */
31302357
AS		 6242 while (! (is_end_of_line[(unsigned char) *s]
6243 || (flag_mri
6244 && *s == '*'
6245 && (s == input_line_pointer
6246 || *(s-1) == ' '
6247 || *(s-1) == '\t'))))
252b5132
RH		 6248 ++s;
6249 --s;
6250 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6251 --s;
6252
6253 if (s - input_line_pointer > 1
6254 && s[-1] == '.')
6255 s -= 2;
6256
6257 if (s - input_line_pointer < 3
6258 || strncasecmp (s - 3, "THEN", 4) != 0)
6259 {
6260 if (qual != '\0')
6261 {
6262 as_bad (_("missing then"));
6263 ignore_rest_of_line ();
6264 return;
6265 }
6266
6267 /* It's a conditional. */
6268 s_if (O_ne);
6269 return;
6270 }
6271
6272 /* Since this might be a conditional if, this pseudo-op will be
6273 called even if we are supported to be ignoring input. Double
6274 check now. Clobber *input_line_pointer so that ignore_input
6275 thinks that this is not a special pseudo-op. */
6276 c = *input_line_pointer;
6277 *input_line_pointer = 0;
6278 if (ignore_input ())
6279 {
6280 *input_line_pointer = c;
6281 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6282 ++input_line_pointer;
6283 demand_empty_rest_of_line ();
6284 return;
6285 }
6286 *input_line_pointer = c;
6287
6288 n = push_mri_control (mri_if);
6289
6290 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6291 n->next, s[1] == '.' ? s[2] : '\0');
6292
6293 if (s[1] == '.')
6294 input_line_pointer = s + 3;
6295 else
6296 input_line_pointer = s + 1;
6297
6298 if (flag_mri)
6299 {
6300 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6301 ++input_line_pointer;
6302 }
6303
6304 demand_empty_rest_of_line ();
6305}
6306
6307/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6308 structured IF, associate the ELSE with the IF. Otherwise, assume
6309 it is a conditional else. */
6310
6311static void
31302357 6312s_mri_else (int qual)
252b5132
RH		 6313{
6314 int c;
6315 char *buf;
6316 char q[2];
6317
6318 if (qual == '\0'
6319 && (mri_control_stack == NULL
6320 || mri_control_stack->type != mri_if
6321 || mri_control_stack->else_seen))
6322 {
6323 s_else (0);
6324 return;
6325 }
6326
6327 c = *input_line_pointer;
6328 *input_line_pointer = 0;
6329 if (ignore_input ())
6330 {
6331 *input_line_pointer = c;
6332 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6333 ++input_line_pointer;
6334 demand_empty_rest_of_line ();
6335 return;
6336 }
6337 *input_line_pointer = c;
6338
6339 if (mri_control_stack == NULL
6340 || mri_control_stack->type != mri_if
6341 || mri_control_stack->else_seen)
6342 {
6343 as_bad (_("else without matching if"));
6344 ignore_rest_of_line ();
6345 return;
6346 }
6347
6348 mri_control_stack->else_seen = 1;
6349
6350 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
3882b010 6351 q[0] = TOLOWER (qual);
252b5132
RH		 6352 q[1] = '\0';
6353 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6354 mri_assemble (buf);
6355 free (buf);
6356
6357 colon (mri_control_stack->next);
6358
6359 if (flag_mri)
6360 {
6361 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6362 ++input_line_pointer;
6363 }
6364
6365 demand_empty_rest_of_line ();
6366}
6367
6368/* Handle the MRI ENDI pseudo-op. */
6369
6370static void
31302357 6371s_mri_endi (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6372{
6373 if (mri_control_stack == NULL
6374 || mri_control_stack->type != mri_if)
6375 {
6376 as_bad (_("endi without matching if"));
6377 ignore_rest_of_line ();
6378 return;
6379 }
6380
6381 /* ignore_input will not return true for ENDI, so we don't need to
6382 worry about checking it again here. */
6383
6384 if (! mri_control_stack->else_seen)
6385 colon (mri_control_stack->next);
6386 colon (mri_control_stack->bottom);
6387
6388 pop_mri_control ();
6389
6390 if (flag_mri)
6391 {
6392 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6393 ++input_line_pointer;
6394 }
6395
6396 demand_empty_rest_of_line ();
6397}
6398
6399/* Handle the MRI BREAK pseudo-op. */
6400
6401static void
31302357 6402s_mri_break (int extent)
252b5132
RH		 6403{
6404 struct mri_control_info *n;
6405 char *buf;
6406 char ex[2];
6407
6408 n = mri_control_stack;
6409 while (n != NULL
6410 && n->type != mri_for
6411 && n->type != mri_repeat
6412 && n->type != mri_while)
6413 n = n->outer;
6414 if (n == NULL)
6415 {
6416 as_bad (_("break outside of structured loop"));
6417 ignore_rest_of_line ();
6418 return;
6419 }
6420
6421 buf = (char *) xmalloc (20 + strlen (n->bottom));
3882b010 6422 ex[0] = TOLOWER (extent);
252b5132
RH		 6423 ex[1] = '\0';
6424 sprintf (buf, "bra%s %s", ex, n->bottom);
6425 mri_assemble (buf);
6426 free (buf);
6427
6428 if (flag_mri)
6429 {
6430 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6431 ++input_line_pointer;
6432 }
6433
6434 demand_empty_rest_of_line ();
6435}
6436
6437/* Handle the MRI NEXT pseudo-op. */
6438
6439static void
31302357 6440s_mri_next (int extent)
252b5132
RH		 6441{
6442 struct mri_control_info *n;
6443 char *buf;
6444 char ex[2];
6445
6446 n = mri_control_stack;
6447 while (n != NULL
6448 && n->type != mri_for
6449 && n->type != mri_repeat
6450 && n->type != mri_while)
6451 n = n->outer;
6452 if (n == NULL)
6453 {
6454 as_bad (_("next outside of structured loop"));
6455 ignore_rest_of_line ();
6456 return;
6457 }
6458
6459 buf = (char *) xmalloc (20 + strlen (n->next));
3882b010 6460 ex[0] = TOLOWER (extent);
252b5132
RH		 6461 ex[1] = '\0';
6462 sprintf (buf, "bra%s %s", ex, n->next);
6463 mri_assemble (buf);
6464 free (buf);
6465
6466 if (flag_mri)
6467 {
6468 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6469 ++input_line_pointer;
6470 }
6471
6472 demand_empty_rest_of_line ();
6473}
6474
6475/* Handle the MRI FOR pseudo-op. */
6476
6477static void
31302357 6478s_mri_for (int qual)
252b5132
RH		 6479{
6480 const char *varstart, *varstop;
6481 const char *initstart, *initstop;
6482 const char *endstart, *endstop;
6483 const char *bystart, *bystop;
6484 int up;
6485 int by;
6486 int extent;
6487 struct mri_control_info *n;
6488 char *buf;
6489 char *s;
6490 char ex[2];
6491
6492 /* The syntax is
6493 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6494 */
6495
6496 SKIP_WHITESPACE ();
6497 varstart = input_line_pointer;
6498
6499 /* Look for the '='. */
6500 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6501 && *input_line_pointer != '=')
6502 ++input_line_pointer;
6503 if (*input_line_pointer != '=')
6504 {
6505 as_bad (_("missing ="));
6506 ignore_rest_of_line ();
6507 return;
6508 }
6509
6510 varstop = input_line_pointer;
6511 if (varstop > varstart
6512 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6513 --varstop;
6514
6515 ++input_line_pointer;
6516
6517 initstart = input_line_pointer;
6518
6519 /* Look for TO or DOWNTO. */
6520 up = 1;
6521 initstop = NULL;
6522 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6523 {
6524 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6525 && ! is_part_of_name (input_line_pointer[2]))
6526 {
6527 initstop = input_line_pointer;
6528 input_line_pointer += 2;
6529 break;
6530 }
6531 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6532 && ! is_part_of_name (input_line_pointer[6]))
6533 {
6534 initstop = input_line_pointer;
6535 up = 0;
6536 input_line_pointer += 6;
6537 break;
6538 }
6539 ++input_line_pointer;
6540 }
6541 if (initstop == NULL)
6542 {
6543 as_bad (_("missing to or downto"));
6544 ignore_rest_of_line ();
6545 return;
6546 }
6547 if (initstop > initstart
6548 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6549 --initstop;
6550
6551 SKIP_WHITESPACE ();
6552 endstart = input_line_pointer;
6553
6554 /* Look for BY or DO. */
6555 by = 0;
6556 endstop = NULL;
6557 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6558 {
6559 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6560 && ! is_part_of_name (input_line_pointer[2]))
6561 {
6562 endstop = input_line_pointer;
6563 by = 1;
6564 input_line_pointer += 2;
6565 break;
6566 }
6567 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6568 && (input_line_pointer[2] == '.'
6569 || ! is_part_of_name (input_line_pointer[2])))
6570 {
6571 endstop = input_line_pointer;
6572 input_line_pointer += 2;
6573 break;
6574 }
6575 ++input_line_pointer;
6576 }
6577 if (endstop == NULL)
6578 {
6579 as_bad (_("missing do"));
6580 ignore_rest_of_line ();
6581 return;
6582 }
6583 if (endstop > endstart
6584 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6585 --endstop;
6586
6587 if (! by)
6588 {
6589 bystart = "#1";
6590 bystop = bystart + 2;
6591 }
6592 else
6593 {
6594 SKIP_WHITESPACE ();
6595 bystart = input_line_pointer;
6596
6597 /* Look for DO. */
6598 bystop = NULL;
6599 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6600 {
6601 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6602 && (input_line_pointer[2] == '.'
6603 || ! is_part_of_name (input_line_pointer[2])))
6604 {
6605 bystop = input_line_pointer;
6606 input_line_pointer += 2;
6607 break;
6608 }
6609 ++input_line_pointer;
6610 }
6611 if (bystop == NULL)
6612 {
6613 as_bad (_("missing do"));
6614 ignore_rest_of_line ();
6615 return;
6616 }
6617 if (bystop > bystart
6618 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6619 --bystop;
6620 }
6621
6622 if (*input_line_pointer != '.')
6623 extent = '\0';
6624 else
6625 {
6626 extent = input_line_pointer[1];
6627 input_line_pointer += 2;
6628 }
6629
6630 /* We have fully parsed the FOR operands. Now build the loop. */
252b5132
RH		 6631 n = push_mri_control (mri_for);
6632
6633 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6634
36759679 6635 /* Move init,var. */
252b5132
RH		 6636 s = buf;
6637 *s++ = 'm';
6638 *s++ = 'o';
6639 *s++ = 'v';
6640 *s++ = 'e';
6641 if (qual != '\0')
3882b010 6642 *s++ = TOLOWER (qual);
252b5132
RH		 6643 *s++ = ' ';
6644 memcpy (s, initstart, initstop - initstart);
6645 s += initstop - initstart;
6646 *s++ = ',';
6647 memcpy (s, varstart, varstop - varstart);
6648 s += varstop - varstart;
6649 *s = '\0';
6650 mri_assemble (buf);
6651
6652 colon (n->top);
6653
36759679 6654 /* cmp end,var. */
252b5132
RH		 6655 s = buf;
6656 *s++ = 'c';
6657 *s++ = 'm';
6658 *s++ = 'p';
6659 if (qual != '\0')
3882b010 6660 *s++ = TOLOWER (qual);
252b5132
RH		 6661 *s++ = ' ';
6662 memcpy (s, endstart, endstop - endstart);
6663 s += endstop - endstart;
6664 *s++ = ',';
6665 memcpy (s, varstart, varstop - varstart);
6666 s += varstop - varstart;
6667 *s = '\0';
6668 mri_assemble (buf);
6669
36759679 6670 /* bcc bottom. */
3882b010 6671 ex[0] = TOLOWER (extent);
252b5132
RH		 6672 ex[1] = '\0';
6673 if (up)
6674 sprintf (buf, "blt%s %s", ex, n->bottom);
6675 else
6676 sprintf (buf, "bgt%s %s", ex, n->bottom);
6677 mri_assemble (buf);
6678
6679 /* Put together the add or sub instruction used by ENDF. */
6680 s = buf;
6681 if (up)
6682 strcpy (s, "add");
6683 else
6684 strcpy (s, "sub");
6685 s += 3;
6686 if (qual != '\0')
3882b010 6687 *s++ = TOLOWER (qual);
252b5132
RH		 6688 *s++ = ' ';
6689 memcpy (s, bystart, bystop - bystart);
6690 s += bystop - bystart;
6691 *s++ = ',';
6692 memcpy (s, varstart, varstop - varstart);
6693 s += varstop - varstart;
6694 *s = '\0';
6695 n->incr = buf;
6696
6697 if (flag_mri)
6698 {
6699 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6700 ++input_line_pointer;
6701 }
6702
6703 demand_empty_rest_of_line ();
6704}
6705
6706/* Handle the MRI ENDF pseudo-op. */
6707
6708static void
31302357 6709s_mri_endf (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6710{
6711 if (mri_control_stack == NULL
6712 || mri_control_stack->type != mri_for)
6713 {
6714 as_bad (_("endf without for"));
6715 ignore_rest_of_line ();
6716 return;
6717 }
6718
6719 colon (mri_control_stack->next);
6720
6721 mri_assemble (mri_control_stack->incr);
6722
6723 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6724 mri_assemble (mri_control_stack->incr);
6725
6726 free (mri_control_stack->incr);
6727
6728 colon (mri_control_stack->bottom);
6729
6730 pop_mri_control ();
6731
6732 if (flag_mri)
6733 {
6734 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6735 ++input_line_pointer;
6736 }
6737
6738 demand_empty_rest_of_line ();
6739}
6740
6741/* Handle the MRI REPEAT pseudo-op. */
6742
6743static void
31302357 6744s_mri_repeat (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6745{
6746 struct mri_control_info *n;
6747
6748 n = push_mri_control (mri_repeat);
6749 colon (n->top);
6750 if (flag_mri)
6751 {
6752 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6753 ++input_line_pointer;
6754 }
6755 demand_empty_rest_of_line ();
6756}
6757
6758/* Handle the MRI UNTIL pseudo-op. */
6759
6760static void
31302357 6761s_mri_until (int qual)
252b5132
RH		 6762{
6763 char *s;
6764
6765 if (mri_control_stack == NULL
6766 || mri_control_stack->type != mri_repeat)
6767 {
6768 as_bad (_("until without repeat"));
6769 ignore_rest_of_line ();
6770 return;
6771 }
6772
6773 colon (mri_control_stack->next);
6774
6775 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6776 ;
6777
6778 parse_mri_control_expression (s, qual, (const char *) NULL,
6779 mri_control_stack->top, '\0');
6780
6781 colon (mri_control_stack->bottom);
6782
6783 input_line_pointer = s;
6784
6785 pop_mri_control ();
6786
6787 if (flag_mri)
6788 {
6789 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6790 ++input_line_pointer;
6791 }
6792
6793 demand_empty_rest_of_line ();
6794}
6795
6796/* Handle the MRI WHILE pseudo-op. */
6797
6798static void
31302357 6799s_mri_while (int qual)
252b5132
RH		 6800{
6801 char *s;
6802
6803 struct mri_control_info *n;
6804
6805 s = input_line_pointer;
e1f44d10
NC		 6806 /* We only accept '*' as introduction of comments if preceded by white space
6807 or at first column of a line (I think this can't actually happen here?)
6808 This is important when assembling:
6809 while d0 <ne> 12(a0,d0*2) do
36759679 6810 while d0 <ne> #CONST*20 do. */
8a104df9
KH		 6811 while (! (is_end_of_line[(unsigned char) *s]
6812 || (flag_mri
6813 && *s == '*'
6814 && (s == input_line_pointer
6815 || *(s-1) == ' '
6816 || *(s-1) == '\t'))))
252b5132
RH		 6817 s++;
6818 --s;
6819 while (*s == ' ' || *s == '\t')
6820 --s;
6821 if (s - input_line_pointer > 1
6822 && s[-1] == '.')
6823 s -= 2;
6824 if (s - input_line_pointer < 2
6825 || strncasecmp (s - 1, "DO", 2) != 0)
6826 {
6827 as_bad (_("missing do"));
6828 ignore_rest_of_line ();
6829 return;
6830 }
6831
6832 n = push_mri_control (mri_while);
6833
6834 colon (n->next);
6835
6836 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6837 s[1] == '.' ? s[2] : '\0');
6838
6839 input_line_pointer = s + 1;
6840 if (*input_line_pointer == '.')
6841 input_line_pointer += 2;
6842
6843 if (flag_mri)
6844 {
6845 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6846 ++input_line_pointer;
6847 }
6848
6849 demand_empty_rest_of_line ();
6850}
6851
6852/* Handle the MRI ENDW pseudo-op. */
6853
6854static void
31302357 6855s_mri_endw (int ignore ATTRIBUTE_UNUSED)
252b5132
RH		 6856{
6857 char *buf;
6858
6859 if (mri_control_stack == NULL
6860 || mri_control_stack->type != mri_while)
6861 {
6862 as_bad (_("endw without while"));
6863 ignore_rest_of_line ();
6864 return;
6865 }
6866
6867 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6868 sprintf (buf, "bra %s", mri_control_stack->next);
6869 mri_assemble (buf);
6870 free (buf);
6871
6872 colon (mri_control_stack->bottom);
6873
6874 pop_mri_control ();
6875
6876 if (flag_mri)
6877 {
6878 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6879 ++input_line_pointer;
6880 }
6881
6882 demand_empty_rest_of_line ();
6883}
6884\f
266abb8f
NS		 6885/* Parse a .cpu directive. */
6886
6887static void
6888s_m68k_cpu (int ignored ATTRIBUTE_UNUSED)
6889{
6890 char saved_char;
6891 char *name;
6892
6893 if (initialized)
6894 {
6895 as_bad (_("already assembled instructions"));
6896 ignore_rest_of_line ();
6897 return;
6898 }
6899
6900 name = input_line_pointer;
6901 while (*input_line_pointer && !ISSPACE(*input_line_pointer))
6902 input_line_pointer++;
6903 saved_char = *input_line_pointer;
6904 *input_line_pointer = 0;
6905
6906 m68k_set_cpu (name, 1, 0);
6907
6908 *input_line_pointer = saved_char;
6909 demand_empty_rest_of_line ();
6910 return;
6911}
6912
6913/* Parse a .arch directive. */
6914
6915static void
6916s_m68k_arch (int ignored ATTRIBUTE_UNUSED)
6917{
6918 char saved_char;
6919 char *name;
6920
6921 if (initialized)
6922 {
6923 as_bad (_("already assembled instructions"));
6924 ignore_rest_of_line ();
6925 return;
6926 }
6927
6928 name = input_line_pointer;
6929 while (*input_line_pointer && *input_line_pointer != ','
6930 && !ISSPACE (*input_line_pointer))
6931 input_line_pointer++;
6932 saved_char = *input_line_pointer;
6933 *input_line_pointer = 0;
6934
6935 if (m68k_set_arch (name, 1, 0))
6936 {
6937 /* Scan extensions. */
6938 do
6939 {
6940 *input_line_pointer++ = saved_char;
6941 if (!*input_line_pointer || ISSPACE (*input_line_pointer))
6942 break;
6943 name = input_line_pointer;
6944 while (*input_line_pointer && *input_line_pointer != ','
6945 && !ISSPACE (*input_line_pointer))
6946 input_line_pointer++;
6947 saved_char = *input_line_pointer;
6948 *input_line_pointer = 0;
6949 }
6950 while (m68k_set_extension (name, 1, 0));
6951 }
6952
6953 *input_line_pointer = saved_char;
6954 demand_empty_rest_of_line ();
6955 return;
6956}
6957\f
6958/* Lookup a cpu name in TABLE and return the slot found. Return NULL
6959 if none is found, the caller is responsible for emitting an error
6960 message. If ALLOW_M is non-zero, we allow an initial 'm' on the
6961 cpu name, if it begins with a '6' (possibly skipping an intervening
6962 'c'. We also allow a 'c' in the same place. if NEGATED is
6963 non-zero, we accept a leading 'no-' and *NEGATED is set to true, if
6964 the option is indeed negated. */
6965
6966static const struct m68k_cpu *
6967m68k_lookup_cpu (const char *arg, const struct m68k_cpu *table,
6968 int allow_m, int *negated)
6969{
6970 /* allow negated value? */
6971 if (negated)
6972 {
6973 *negated = 0;
6974
6975 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6976 {
6977 arg += 3;
6978 *negated = 1;
6979 }
6980 }
6981
6982 /* Remove 'm' or 'mc' prefix from 68k variants. */
6983 if (allow_m)
6984 {
6985 if (arg[0] == 'm')
6986 {
6987 if (arg[1] == '6')
6988 arg += 1;
6989 else if (arg[1] == 'c' && arg[2] == '6')
6990 arg += 2;
6991 }
6992 }
6993 else if (arg[0] == 'c' && arg[1] == '6')
6994 arg += 1;
6995
6996 for (; table->name; table++)
6997 if (!strcmp (arg, table->name))
2da12c60
NS		 6998 {
6999 if (table->alias < -1 || table->alias > 1)
7000 as_bad (_("`%s' is deprecated, use `%s'"),
7001 table->name, table[table->alias < 0 ? 1 : -1].name);
7002 return table;
7003 }
266abb8f
NS		 7004 return 0;
7005}
7006
7007/* Set the cpu, issuing errors if it is unrecognized, or invalid */
7008
7009static int
7010m68k_set_cpu (char const *name, int allow_m, int silent)
7011{
7012 const struct m68k_cpu *cpu;
7013
7014 cpu = m68k_lookup_cpu (name, m68k_cpus, allow_m, NULL);
7015
7016 if (!cpu)
7017 {
7018 if (!silent)
7019 as_bad (_("cpu `%s' unrecognized"), name);
7020 return 0;
7021 }
7022
7023 if (selected_cpu && selected_cpu != cpu)
7024 {
7025 as_bad (_("already selected `%s' processor"),
7026 selected_cpu->name);
7027 return 0;
7028 }
7029 selected_cpu = cpu;
7030 return 1;
7031}
7032
7033/* Set the architecture, issuing errors if it is unrecognized, or invalid */
7034
7035static int
7036m68k_set_arch (char const *name, int allow_m, int silent)
7037{
7038 const struct m68k_cpu *arch;
7039
7040 arch = m68k_lookup_cpu (name, m68k_archs, allow_m, NULL);
7041
7042 if (!arch)
7043 {
7044 if (!silent)
7045 as_bad (_("architecture `%s' unrecognized"), name);
7046 return 0;
7047 }
7048
7049 if (selected_arch && selected_arch != arch)
7050 {
7051 as_bad (_("already selected `%s' architecture"),
7052 selected_arch->name);
7053 return 0;
7054 }
7055
7056 selected_arch = arch;
7057 return 1;
7058}
7059
7060/* Set the architecture extension, issuing errors if it is
7061 unrecognized, or invalid */
7062
7063static int
7064m68k_set_extension (char const *name, int allow_m, int silent)
7065{
7066 int negated;
7067 const struct m68k_cpu *ext;
7068
7069 ext = m68k_lookup_cpu (name, m68k_extensions, allow_m, &negated);
7070
7071 if (!ext)
7072 {
7073 if (!silent)
7074 as_bad (_("extension `%s' unrecognized"), name);
7075 return 0;
7076 }
7077
7078 if (negated)
7079 not_current_architecture |= ext->arch;
7080 else
7081 current_architecture |= ext->arch;
7082 return 1;
7083}
7084
31302357
AS		 7085/* md_parse_option
7086 Invocation line includes a switch not recognized by the base assembler.
266abb8f 7087 */
252b5132
RH		 7088
7089#ifdef OBJ_ELF
5a38dc70 7090const char *md_shortopts = "lSA:m:kQ:V";
252b5132 7091#else
5a38dc70 7092const char *md_shortopts = "lSA:m:k";
252b5132
RH		 7093#endif
7094
7095struct option md_longopts[] = {
7096#define OPTION_PIC (OPTION_MD_BASE)
7097 {"pic", no_argument, NULL, OPTION_PIC},
7098#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
7099 {"register-prefix-optional", no_argument, NULL,
7100 OPTION_REGISTER_PREFIX_OPTIONAL},
7101#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
7102 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
7103#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
7104 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
7105#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
7106 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
7107#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
7108 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
7109#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
7110 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 7111#define OPTION_PCREL (OPTION_MD_BASE + 7)
7112 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 7113 {NULL, no_argument, NULL, 0}
7114};
bc805888 7115size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 7116
7117int
31302357 7118md_parse_option (int c, char *arg)
252b5132
RH		 7119{
7120 switch (c)
7121 {
7122 case 'l': /* -l means keep external to 2 bit offset
36759679 7123 rather than 16 bit one. */
252b5132
RH		 7124 flag_short_refs = 1;
7125 break;
7126
7127 case 'S': /* -S means that jbsr's always turn into
7128 jsr's. */
7129 flag_long_jumps = 1;
7130 break;
7131
28e7409f
NC		 7132 case OPTION_PCREL: /* --pcrel means never turn PC-relative
7133 branches into absolute jumps. */
7134 flag_keep_pcrel = 1;
7135 break;
7136
252b5132
RH		 7137 case OPTION_PIC:
7138 case 'k':
7139 flag_want_pic = 1;
36759679 7140 break; /* -pic, Position Independent Code. */
252b5132
RH		 7141
7142 case OPTION_REGISTER_PREFIX_OPTIONAL:
7143 flag_reg_prefix_optional = 1;
7144 reg_prefix_optional_seen = 1;
7145 break;
7146
7147 /* -V: SVR4 argument to print version ID. */
7148 case 'V':
7149 print_version_id ();
7150 break;
7151
7152 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7153 should be emitted or not. FIXME: Not implemented. */
7154 case 'Q':
7155 break;
7156
7157 case OPTION_BITWISE_OR:
7158 {
7159 char *n, *t;
7160 const char *s;
7161
7162 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
7163 t = n;
7164 for (s = m68k_comment_chars; *s != '\0'; s++)
7165 if (*s != '|')
7166 *t++ = *s;
7167 *t = '\0';
7168 m68k_comment_chars = n;
7169 }
7170 break;
7171
7172 case OPTION_BASE_SIZE_DEFAULT_16:
7173 m68k_index_width_default = SIZE_WORD;
7174 break;
7175
7176 case OPTION_BASE_SIZE_DEFAULT_32:
7177 m68k_index_width_default = SIZE_LONG;
7178 break;
7179
7180 case OPTION_DISP_SIZE_DEFAULT_16:
7181 m68k_rel32 = 0;
7182 m68k_rel32_from_cmdline = 1;
7183 break;
7184
7185 case OPTION_DISP_SIZE_DEFAULT_32:
7186 m68k_rel32 = 1;
7187 m68k_rel32_from_cmdline = 1;
7188 break;
7189
266abb8f
NS		 7190 case 'A':
7191#if WARN_DEPRECATED
7192 as_tsktsk (_ ("option `-A%s' is deprecated: use `-%s'",
7193 arg, arg));
7194#endif
7195 /* Intentional fall-through. */
7196 case 'm':
7197 if (!strncmp (arg, "arch=", 5))
7198 m68k_set_arch (arg + 5, 1, 0);
7199 else if (!strncmp (arg, "cpu=", 4))
7200 m68k_set_cpu (arg + 4, 1, 0);
7201 else if (m68k_set_extension (arg, 0, 1))
7202 ;
0b2e31dc
NS		 7203 else if (m68k_set_arch (arg, 0, 1))
7204 ;
266abb8f
NS		 7205 else if (m68k_set_cpu (arg, 0, 1))
7206 ;
7207 else
7208 return 0;
7209 break;
7210
252b5132
RH		 7211 default:
7212 return 0;
7213 }
7214
7215 return 1;
7216}
7217
266abb8f
NS		 7218/* Setup tables from the selected arch and/or cpu */
7219
7220static void
7221m68k_init_arch (void)
7222{
266abb8f
NS		 7223 if (not_current_architecture & current_architecture)
7224 {
7225 as_bad (_("architecture features both enabled and disabled"));
7226 not_current_architecture &= ~current_architecture;
7227 }
7228 if (selected_arch)
2da12c60
NS		 7229 {
7230 current_architecture |= selected_arch->arch;
7231 control_regs = selected_arch->control_regs;
7232 }
0b2e31dc
NS		 7233 else
7234 current_architecture |= selected_cpu->arch;
0b2e31dc 7235
2da12c60
NS		 7236 current_architecture &= ~not_current_architecture;
7237
377260ba
NS		 7238 if ((current_architecture & (cfloat | m68881)) == (cfloat | m68881))
7239 {
7240 /* Determine which float is really meant. */
7241 if (current_architecture & (m68k_mask & ~m68881))
7242 current_architecture ^= cfloat;
7243 else
7244 current_architecture ^= m68881;
7245 }
7246
0b2e31dc 7247 if (selected_cpu)
266abb8f 7248 {
2da12c60 7249 control_regs = selected_cpu->control_regs;
0b2e31dc 7250 if (current_architecture & ~selected_cpu->arch)
266abb8f 7251 {
0b2e31dc
NS		 7252 as_bad (_("selected processor does not have all features of selected architecture"));
7253 current_architecture
7254 = selected_cpu->arch & ~not_current_architecture;
266abb8f
NS		 7255 }
7256 }
266abb8f 7257
266abb8f
NS		 7258 if ((current_architecture & m68k_mask)
7259 && (current_architecture & ~m68k_mask))
7260 {
7261 as_bad (_ ("m68k and cf features both selected"));
0b2e31dc 7262 if (current_architecture & m68k_mask)
266abb8f
NS		 7263 current_architecture &= m68k_mask;
7264 else
7265 current_architecture &= ~m68k_mask;
7266 }
7267
7268 /* Permit m68881 specification with all cpus; those that can't work
7269 with a coprocessor could be doing emulation. */
7270 if (current_architecture & m68851)
7271 {
7272 if (current_architecture & m68040)
7273 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
7274 }
7275 /* What other incompatibilities could we check for? */
7276
266abb8f
NS		 7277 if (cpu_of_arch (current_architecture) < m68020
7278 || arch_coldfire_p (current_architecture))
7279 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
7280
7281 initialized = 1;
7282}
7283
252b5132 7284void
31302357 7285md_show_usage (FILE *stream)
252b5132 7286{
76f57f3a 7287 const char *default_cpu = TARGET_CPU;
f1f5ef86
AM		 7288 int i;
7289 unsigned int default_arch;
76f57f3a 7290
8a104df9 7291 /* Get the canonical name for the default target CPU. */
76f57f3a
JT		 7292 if (*default_cpu == 'm')
7293 default_cpu++;
266abb8f 7294 for (i = 0; m68k_cpus[i].name; i++)
76f57f3a 7295 {
266abb8f 7296 if (strcasecmp (default_cpu, m68k_cpus[i].name) == 0)
76f57f3a 7297 {
266abb8f 7298 default_arch = m68k_cpus[i].arch;
2da12c60
NS		 7299 while (m68k_cpus[i].alias > 0)
7300 i--;
7301 while (m68k_cpus[i].alias < 0)
7302 i++;
7303 default_cpu = m68k_cpus[i].name;
76f57f3a
JT		 7304 }
7305 }
7306
bc805888 7307 fprintf (stream, _("\
266abb8f
NS		 7308-march=<arch> set architecture\n\
7309-mcpu=<cpu> set cpu [default %s]\n\
7310"), default_cpu);
7311 for (i = 0; m68k_extensions[i].name; i++)
7312 fprintf (stream, _("\
0b2e31dc
NS		 7313-m[no-]%-16s enable/disable%s architecture extension\n\
7314"), m68k_extensions[i].name,
7315 m68k_extensions[i].alias > 0 ? " ColdFire"
7316 : m68k_extensions[i].alias < 0 ? " m68k" : "");
266abb8f 7317
bc805888 7318 fprintf (stream, _("\
266abb8f 7319-l use 1 word for refs to undefined symbols [default 2]\n\
252b5132
RH		 7320-pic, -k generate position independent code\n\
7321-S turn jbsr into jsr\n\
28e7409f 7322--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 7323--register-prefix-optional\n\
7324 recognize register names without prefix character\n\
266abb8f 7325--bitwise-or do not treat `|' as a comment character\n\
252b5132
RH		 7326--base-size-default-16 base reg without size is 16 bits\n\
7327--base-size-default-32 base reg without size is 32 bits (default)\n\
7328--disp-size-default-16 displacement with unknown size is 16 bits\n\
266abb8f
NS		 7329--disp-size-default-32 displacement with unknown size is 32 bits (default)\n\
7330"));
7331
7332 fprintf (stream, _("Architecture variants are: "));
7333 for (i = 0; m68k_archs[i].name; i++)
7334 {
7335 if (i)
7336 fprintf (stream, " | ");
7337 fprintf (stream, m68k_archs[i].name);
7338 }
7339 fprintf (stream, "\n");
7340
7341 fprintf (stream, _("Processor variants are: "));
7342 for (i = 0; m68k_cpus[i].name; i++)
7343 {
7344 if (i)
7345 fprintf (stream, " | ");
7346 fprintf (stream, m68k_cpus[i].name);
7347 }
7348 fprintf (stream, _("\n"));
252b5132
RH		 7349}
7350\f
7351#ifdef TEST2
7352
7353/* TEST2: Test md_assemble() */
36759679
NC		 7354/* Warning, this routine probably doesn't work anymore. */
7355int
31302357 7356main (void)
252b5132
RH		 7357{
7358 struct m68k_it the_ins;
7359 char buf[120];
7360 char *cp;
7361 int n;
7362
7363 m68k_ip_begin ();
7364 for (;;)
7365 {
7366 if (!gets (buf) || !*buf)
7367 break;
7368 if (buf[0] == '|' || buf[1] == '.')
7369 continue;
7370 for (cp = buf; *cp; cp++)
7371 if (*cp == '\t')
7372 *cp = ' ';
7373 if (is_label (buf))
7374 continue;
7375 memset (&the_ins, '\0', sizeof (the_ins));
7376 m68k_ip (&the_ins, buf);
7377 if (the_ins.error)
7378 {
7379 printf (_("Error %s in %s\n"), the_ins.error, buf);
7380 }
7381 else
7382 {
7383 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7384 for (n = 0; n < the_ins.numo; n++)
7385 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7386 printf (" ");
7387 print_the_insn (&the_ins.opcode[0], stdout);
7388 (void) putchar ('\n');
7389 }
7390 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7391 {
7392 if (the_ins.operands[n].error)
7393 {
7394 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7395 continue;
7396 }
31302357
AS		 7397 printf ("mode %d, reg %d, ", the_ins.operands[n].mode,
7398 the_ins.operands[n].reg);
252b5132 7399 if (the_ins.operands[n].b_const)
31302357
AS		 7400 printf ("Constant: '%.*s', ",
7401 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const,
7402 the_ins.operands[n].b_const);
7403 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg,
7404 the_ins.operands[n].isiz, the_ins.operands[n].imul);
252b5132 7405 if (the_ins.operands[n].b_iadd)
31302357
AS		 7406 printf ("Iadd: '%.*s',",
7407 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd,
7408 the_ins.operands[n].b_iadd);
7409 putchar ('\n');
252b5132
RH		 7410 }
7411 }
7412 m68k_ip_end ();
7413 return 0;
7414}
7415
31302357
AS		 7416int
7417is_label (char *str)
252b5132
RH		 7418{
7419 while (*str == ' ')
7420 str++;
7421 while (*str && *str != ' ')
7422 str++;
7423 if (str[-1] == ':' || str[1] == '=')
7424 return 1;
7425 return 0;
7426}
7427
7428#endif
7429
7430/* Possible states for relaxation:
7431
7432 0 0 branch offset byte (bra, etc)
7433 0 1 word
7434 0 2 long
7435
7436 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7437 1 1 word
7438 1 2 long
7439
7440 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7441 2 1 word-long
7442 2 2 long-word
7443 2 3 long-long
7444
7445 */
7446
7447/* We have no need to default values of symbols. */
7448
252b5132 7449symbolS *
31302357 7450md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
252b5132
RH		 7451{
7452 return 0;
7453}
7454
7455/* Round up a section size to the appropriate boundary. */
7456valueT
31302357 7457md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
252b5132
RH		 7458{
7459#ifdef OBJ_AOUT
252b5132
RH		 7460 /* For a.out, force the section size to be aligned. If we don't do
7461 this, BFD will align it for us, but it will not write out the
7462 final bytes of the section. This may be a bug in BFD, but it is
7463 easier to fix it here since that is how the other a.out targets
7464 work. */
7465 int align;
7466
7467 align = bfd_get_section_alignment (stdoutput, segment);
7468 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
252b5132
RH		 7469#endif
7470
7471 return size;
7472}
7473
7474/* Exactly what point is a PC-relative offset relative TO?
7475 On the 68k, it is relative to the address of the first extension
7476 word. The difference between the addresses of the offset and the
92774660 7477 first extension word is stored in fx_pcrel_adjust. */
252b5132 7478long
31302357 7479md_pcrel_from (fixS *fixP)
252b5132
RH		 7480{
7481 int adjust;
7482
8390138c
AS		 7483 /* Because fx_pcrel_adjust is a char, and may be unsigned, we explicitly
7484 sign extend the value here. */
7485 adjust = ((fixP->fx_pcrel_adjust & 0xff) ^ 0x80) - 0x80;
252b5132
RH		 7486 if (adjust == 64)
7487 adjust = -1;
7488 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7489}
7490
0d96863f 7491#ifdef OBJ_ELF
8a104df9 7492void
31302357 7493m68k_elf_final_processing (void)
0d96863f 7494{
266abb8f
NS		 7495 unsigned flags = 0;
7496
238d258f 7497 if (arch_coldfire_fpu (current_architecture))
266abb8f
NS		 7498 flags |= EF_M68K_CFV4E;
7499 /* Set file-specific flags if this is a cpu32 processor. */
8a104df9 7500 if (cpu_of_arch (current_architecture) & cpu32)
266abb8f 7501 flags |= EF_M68K_CPU32;
8a104df9
KH		 7502 else if ((cpu_of_arch (current_architecture) & m68000up)
7503 && !(cpu_of_arch (current_architecture) & m68020up))
266abb8f
NS		 7504 flags |= EF_M68K_M68000;
7505
7506 if (current_architecture & mcfisa_a)
7507 {
0b2e31dc
NS		 7508 static const unsigned isa_features[][2] =
7509 {
c694fd50
KH		 7510 {EF_M68K_CF_ISA_A_NODIV, mcfisa_a},
7511 {EF_M68K_CF_ISA_A, mcfisa_a|mcfhwdiv},
7512 {EF_M68K_CF_ISA_A_PLUS,mcfisa_a|mcfisa_aa|mcfhwdiv|mcfusp},
7513 {EF_M68K_CF_ISA_B_NOUSP,mcfisa_a|mcfisa_b|mcfhwdiv},
7514 {EF_M68K_CF_ISA_B, mcfisa_a|mcfisa_b|mcfhwdiv|mcfusp},
0b2e31dc
NS		 7515 {0,0},
7516 };
7517 static const unsigned mac_features[][2] =
7518 {
c694fd50
KH		 7519 {EF_M68K_CF_MAC, mcfmac},
7520 {EF_M68K_CF_EMAC, mcfemac},
0b2e31dc
NS		 7521 {0,0},
7522 };
7523 unsigned ix;
7524 unsigned pattern;
266abb8f 7525
0b2e31dc
NS		 7526 pattern = (current_architecture
7527 & (mcfisa_a|mcfisa_aa|mcfisa_b|mcfhwdiv|mcfusp));
7528 for (ix = 0; isa_features[ix][1]; ix++)
7529 {
7530 if (pattern == isa_features[ix][1])
7531 {
7532 flags |= isa_features[ix][0];
7533 break;
7534 }
7535 }
7536 if (!isa_features[ix][1])
7537 {
7538 cf_bad:
7539 as_warn (_("Not a defined coldfire architecture"));
7540 }
7541 else
7542 {
7543 if (current_architecture & cfloat)
c694fd50 7544 flags |= EF_M68K_CF_FLOAT | EF_M68K_CFV4E;
266abb8f 7545
0b2e31dc
NS		 7546 pattern = current_architecture & (mcfmac|mcfemac);
7547 if (pattern)
7548 {
7549 for (ix = 0; mac_features[ix][1]; ix++)
7550 {
7551 if (pattern == mac_features[ix][1])
7552 {
7553 flags |= mac_features[ix][0];
7554 break;
7555 }
7556 }
7557 if (!mac_features[ix][1])
7558 goto cf_bad;
7559 }
7560 }
266abb8f
NS		 7561 }
7562 elf_elfheader (stdoutput)->e_flags |= flags;
0d96863f
CM		 7563}
7564#endif
c04898f8
AS		 7565
7566int
1df69f4f 7567tc_m68k_regname_to_dw2regnum (char *regname)
c04898f8
AS		 7568{
7569 unsigned int regnum;
7570 static const char *const regnames[] =
7571 {
7572 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
7573 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp",
7574 "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7",
7575 "pc"
7576 };
7577
7578 for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++)
7579 if (strcmp (regname, regnames[regnum]) == 0)
7580 return regnum;
7581
7582 return -1;
7583}
7584
7585void
7586tc_m68k_frame_initial_instructions (void)
7587{
7588 static int sp_regno = -1;
7589
7590 if (sp_regno < 0)
7591 sp_regno = tc_m68k_regname_to_dw2regnum ("sp");
7592
7593 cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT);
7594 cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT);
7595}
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