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252b5132 1/* tc-m68k.c -- Assemble for the m68k family
8fce3f5e 2 Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000
252b5132
RH		 3 Free Software Foundation, Inc.
4
5 This file is part of GAS, the GNU Assembler.
6
7 GAS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 GAS is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GAS; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
21
22#include <ctype.h>
23#include "as.h"
24#include "obstack.h"
25#include "subsegs.h"
26
27#include "opcode/m68k.h"
28#include "m68k-parse.h"
29
0d96863f
CM		 30#if defined (OBJ_ELF)
31#include "elf/m68k.h"
32#endif
33
252b5132
RH		 34/* This string holds the chars that always start a comment. If the
35 pre-processor is disabled, these aren't very useful. The macro
36 tc_comment_chars points to this. We use this, rather than the
37 usual comment_chars, so that the --bitwise-or option will work. */
38#if defined (TE_SVR4) || defined (TE_DELTA)
39const char *m68k_comment_chars = "|#";
40#else
41const char *m68k_comment_chars = "|";
42#endif
43
44/* This array holds the chars that only start a comment at the beginning of
45 a line. If the line seems to have the form '# 123 filename'
46 .line and .file directives will appear in the pre-processed output */
47/* Note that input_file.c hand checks for '#' at the beginning of the
48 first line of the input file. This is because the compiler outputs
92774660
KH		 49 #NO_APP at the beginning of its output. */
50/* Also note that comments like this one will always work. */
252b5132
RH		 51const char line_comment_chars[] = "#*";
52
63a0b638 53const char line_separator_chars[] = ";";
252b5132
RH		 54
55/* Chars that can be used to separate mant from exp in floating point nums */
56CONST char EXP_CHARS[] = "eE";
57
58/* Chars that mean this number is a floating point constant, as
59 in "0f12.456" or "0d1.2345e12". */
60
61CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP";
62
63/* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
64 changed in read.c . Ideally it shouldn't have to know about it at all,
65 but nothing is ideal around here. */
66
67const int md_reloc_size = 8; /* Size of relocation record */
68
69/* Are we trying to generate PIC code? If so, absolute references
70 ought to be made into linkage table references or pc-relative
92774660 71 references. Not implemented. For ELF there are other means
252b5132
RH		 72 to denote pic relocations. */
73int flag_want_pic;
74
75static int flag_short_refs; /* -l option */
76static int flag_long_jumps; /* -S option */
28e7409f 77static int flag_keep_pcrel; /* --pcrel option. */
252b5132
RH		 78
79#ifdef REGISTER_PREFIX_OPTIONAL
80int flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
81#else
82int flag_reg_prefix_optional;
83#endif
84
85/* Whether --register-prefix-optional was used on the command line. */
86static int reg_prefix_optional_seen;
87
88/* The floating point coprocessor to use by default. */
89static enum m68k_register m68k_float_copnum = COP1;
90
91/* If this is non-zero, then references to number(%pc) will be taken
92 to refer to number, rather than to %pc + number. */
93static int m68k_abspcadd;
94
95/* If this is non-zero, then the quick forms of the move, add, and sub
96 instructions are used when possible. */
97static int m68k_quick = 1;
98
99/* If this is non-zero, then if the size is not specified for a base
100 or outer displacement, the assembler assumes that the size should
101 be 32 bits. */
102static int m68k_rel32 = 1;
103
104/* This is non-zero if m68k_rel32 was set from the command line. */
105static int m68k_rel32_from_cmdline;
106
107/* The default width to use for an index register when using a base
108 displacement. */
109static enum m68k_size m68k_index_width_default = SIZE_LONG;
110
111/* We want to warn if any text labels are misaligned. In order to get
112 the right line number, we need to record the line number for each
113 label. */
114
115struct label_line
116{
117 struct label_line *next;
118 symbolS *label;
119 char *file;
120 unsigned int line;
121 int text;
122};
123
124/* The list of labels. */
125
126static struct label_line *labels;
127
128/* The current label. */
129
130static struct label_line *current_label;
131
132/* Its an arbitrary name: This means I don't approve of it */
133/* See flames below */
134static struct obstack robyn;
135
252b5132
RH		 136struct m68k_incant
137 {
138 const char *m_operands;
139 unsigned long m_opcode;
140 short m_opnum;
141 short m_codenum;
142 int m_arch;
143 struct m68k_incant *m_next;
144 };
145
146#define getone(x) ((((x)->m_opcode)>>16)&0xffff)
147#define gettwo(x) (((x)->m_opcode)&0xffff)
148
149static const enum m68k_register m68000_control_regs[] = { 0 };
150static const enum m68k_register m68010_control_regs[] = {
151 SFC, DFC, USP, VBR,
152 0
153};
154static const enum m68k_register m68020_control_regs[] = {
155 SFC, DFC, USP, VBR, CACR, CAAR, MSP, ISP,
156 0
157};
158static const enum m68k_register m68040_control_regs[] = {
159 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1,
160 USP, VBR, MSP, ISP, MMUSR, URP, SRP,
161 0
162};
163static const enum m68k_register m68060_control_regs[] = {
164 SFC, DFC, CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR,
165 USP, VBR, URP, SRP, PCR,
166 0
167};
6da466c7 168static const enum m68k_register mcf_control_regs[] = {
92774660 169 CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR,
252b5132
RH		 170 RAMBAR0, RAMBAR1, MBAR,
171 0
172};
173#define cpu32_control_regs m68010_control_regs
174
175static const enum m68k_register *control_regs;
176
177/* internal form of a 68020 instruction */
178struct m68k_it
179{
180 const char *error;
181 const char *args; /* list of opcode info */
182 int numargs;
183
184 int numo; /* Number of shorts in opcode */
185 short opcode[11];
186
187 struct m68k_op operands[6];
188
189 int nexp; /* number of exprs in use */
190 struct m68k_exp exprs[4];
191
192 int nfrag; /* Number of frags we have to produce */
193 struct
194 {
195 int fragoff; /* Where in the current opcode the frag ends */
196 symbolS *fadd;
197 offsetT foff;
198 int fragty;
199 }
200 fragb[4];
201
202 int nrel; /* Num of reloc strucs in use */
203 struct
204 {
205 int n;
206 expressionS exp;
207 char wid;
208 char pcrel;
209 /* In a pc relative address the difference between the address
210 of the offset and the address that the offset is relative
211 to. This depends on the addressing mode. Basically this
212 is the value to put in the offset field to address the
213 first byte of the offset, without regarding the special
214 significance of some values (in the branch instruction, for
215 example). */
216 int pcrel_fix;
217#ifdef OBJ_ELF
218 /* Whether this expression needs special pic relocation, and if
219 so, which. */
220 enum pic_relocation pic_reloc;
221#endif
222 }
223 reloc[5]; /* Five is enough??? */
224};
225
6da466c7 226#define cpu_of_arch(x) ((x) & (m68000up|mcf))
252b5132
RH		 227#define float_of_arch(x) ((x) & mfloat)
228#define mmu_of_arch(x) ((x) & mmmu)
6da466c7 229#define arch_coldfire_p(x) (((x) & mcf) != 0)
252b5132
RH		 230
231/* Macros for determining if cpu supports a specific addressing mode */
232#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32))
233
234static struct m68k_it the_ins; /* the instruction being assembled */
235
236#define op(ex) ((ex)->exp.X_op)
237#define adds(ex) ((ex)->exp.X_add_symbol)
238#define subs(ex) ((ex)->exp.X_op_symbol)
239#define offs(ex) ((ex)->exp.X_add_number)
240
241/* Macros for adding things to the m68k_it struct */
242
243#define addword(w) the_ins.opcode[the_ins.numo++]=(w)
244
245/* Static functions. */
246
247static void insop PARAMS ((int, const struct m68k_incant *));
248static void add_fix PARAMS ((int, struct m68k_exp *, int, int));
249static void add_frag PARAMS ((symbolS *, offsetT, int));
250
251/* Like addword, but goes BEFORE general operands */
252static void
253insop (w, opcode)
254 int w;
255 const struct m68k_incant *opcode;
256{
257 int z;
258 for(z=the_ins.numo;z>opcode->m_codenum;--z)
259 the_ins.opcode[z]=the_ins.opcode[z-1];
260 for(z=0;z<the_ins.nrel;z++)
261 the_ins.reloc[z].n+=2;
262 for (z = 0; z < the_ins.nfrag; z++)
263 the_ins.fragb[z].fragoff++;
264 the_ins.opcode[opcode->m_codenum]=w;
265 the_ins.numo++;
266}
267
268/* The numo+1 kludge is so we can hit the low order byte of the prev word.
269 Blecch. */
270static void
271add_fix (width, exp, pc_rel, pc_fix)
272 int width;
273 struct m68k_exp *exp;
274 int pc_rel;
275 int pc_fix;
276{
277 the_ins.reloc[the_ins.nrel].n = ((width == 'B' || width == '3')
278 ? (the_ins.numo*2-1)
279 : (((width)=='b')
280 ? (the_ins.numo*2+1)
281 : (the_ins.numo*2)));
282 the_ins.reloc[the_ins.nrel].exp = exp->exp;
283 the_ins.reloc[the_ins.nrel].wid = width;
284 the_ins.reloc[the_ins.nrel].pcrel_fix = pc_fix;
285#ifdef OBJ_ELF
286 the_ins.reloc[the_ins.nrel].pic_reloc = exp->pic_reloc;
287#endif
288 the_ins.reloc[the_ins.nrel++].pcrel = pc_rel;
289}
290
291/* Cause an extra frag to be generated here, inserting up to 10 bytes
292 (that value is chosen in the frag_var call in md_assemble). TYPE
293 is the subtype of the frag to be generated; its primary type is
294 rs_machine_dependent.
295
296 The TYPE parameter is also used by md_convert_frag_1 and
297 md_estimate_size_before_relax. The appropriate type of fixup will
298 be emitted by md_convert_frag_1.
299
300 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
301static void
302add_frag (add, off, type)
303 symbolS *add;
304 offsetT off;
305 int type;
306{
307 the_ins.fragb[the_ins.nfrag].fragoff=the_ins.numo;
308 the_ins.fragb[the_ins.nfrag].fadd=add;
309 the_ins.fragb[the_ins.nfrag].foff=off;
310 the_ins.fragb[the_ins.nfrag++].fragty=type;
311}
312
313#define isvar(ex) \
314 (op (ex) != O_constant && op (ex) != O_big)
315
316static char *crack_operand PARAMS ((char *str, struct m68k_op *opP));
317static int get_num PARAMS ((struct m68k_exp *exp, int ok));
318static void m68k_ip PARAMS ((char *));
319static void insert_reg PARAMS ((const char *, int));
320static void select_control_regs PARAMS ((void));
321static void init_regtable PARAMS ((void));
322static int reverse_16_bits PARAMS ((int in));
323static int reverse_8_bits PARAMS ((int in));
324static void install_gen_operand PARAMS ((int mode, int val));
325static void install_operand PARAMS ((int mode, int val));
326static void s_bss PARAMS ((int));
327static void s_data1 PARAMS ((int));
328static void s_data2 PARAMS ((int));
329static void s_even PARAMS ((int));
330static void s_proc PARAMS ((int));
331static void mri_chip PARAMS ((void));
332static void s_chip PARAMS ((int));
333static void s_fopt PARAMS ((int));
334static void s_opt PARAMS ((int));
335static void s_reg PARAMS ((int));
336static void s_restore PARAMS ((int));
337static void s_save PARAMS ((int));
338static void s_mri_if PARAMS ((int));
339static void s_mri_else PARAMS ((int));
340static void s_mri_endi PARAMS ((int));
341static void s_mri_break PARAMS ((int));
342static void s_mri_next PARAMS ((int));
343static void s_mri_for PARAMS ((int));
344static void s_mri_endf PARAMS ((int));
345static void s_mri_repeat PARAMS ((int));
346static void s_mri_until PARAMS ((int));
347static void s_mri_while PARAMS ((int));
348static void s_mri_endw PARAMS ((int));
349static void md_apply_fix_2 PARAMS ((fixS *, offsetT));
350static void md_convert_frag_1 PARAMS ((fragS *));
351
352static int current_architecture;
353
354struct m68k_cpu {
355 unsigned long arch;
356 const char *name;
357 int alias;
358};
359
360static const struct m68k_cpu archs[] = {
361 { m68000, "68000", 0 },
362 { m68010, "68010", 0 },
363 { m68020, "68020", 0 },
364 { m68030, "68030", 0 },
365 { m68040, "68040", 0 },
366 { m68060, "68060", 0 },
367 { cpu32, "cpu32", 0 },
368 { m68881, "68881", 0 },
369 { m68851, "68851", 0 },
370 { mcf5200, "5200", 0 },
6da466c7
ILT		 371 { mcf5206e, "5206e", 0 },
372 { mcf5307, "5307", 0},
252b5132
RH		 373 /* Aliases (effectively, so far as gas is concerned) for the above
374 cpus. */
375 { m68020, "68k", 1 },
376 { m68000, "68008", 1 },
377 { m68000, "68302", 1 },
378 { m68000, "68306", 1 },
379 { m68000, "68307", 1 },
380 { m68000, "68322", 1 },
381 { m68000, "68356", 1 },
382 { m68000, "68ec000", 1 },
383 { m68000, "68hc000", 1 },
384 { m68000, "68hc001", 1 },
385 { m68020, "68ec020", 1 },
386 { m68030, "68ec030", 1 },
387 { m68040, "68ec040", 1 },
388 { m68060, "68ec060", 1 },
389 { cpu32, "68330", 1 },
390 { cpu32, "68331", 1 },
391 { cpu32, "68332", 1 },
392 { cpu32, "68333", 1 },
393 { cpu32, "68334", 1 },
394 { cpu32, "68336", 1 },
395 { cpu32, "68340", 1 },
396 { cpu32, "68341", 1 },
397 { cpu32, "68349", 1 },
398 { cpu32, "68360", 1 },
399 { m68881, "68882", 1 },
6da466c7
ILT		 400 { mcf5200, "5202", 1 },
401 { mcf5200, "5204", 1 },
402 { mcf5200, "5206", 1 },
252b5132
RH		 403};
404
405static const int n_archs = sizeof (archs) / sizeof (archs[0]);
406
151337e8
NC		 407/* This is the assembler relaxation table for m68k. m68k is a rich CISC
408 architecture and we have a lot of relaxation modes. */
252b5132 409
151337e8
NC		 410/* Macros used in the relaxation code. */
411#define TAB(x,y) (((x) << 2) + (y))
412#define TABTYPE(x) ((x) >> 2)
413
414/* Relaxation states. */
415#define BYTE 0
416#define SHORT 1
417#define LONG 2
418#define SZ_UNDEF 3
419
420/* Here are all the relaxation modes we support. First we can relax ordinary
421 branches. On 68020 and higher and on CPU32 all branch instructions take
422 three forms, so on these CPUs all branches always remain as such. When we
423 have to expand to the LONG form on a 68000, though, we substitute an
424 absolute jump instead. This is a direct replacement for unconditional
425 branches and a branch over a jump for conditional branches. However, if the
426 user requires PIC and disables this with --pcrel, we can only relax between
427 BYTE and SHORT forms, punting if that isn't enough. This gives us four
428 different relaxation modes for branches: */
429
430#define BRANCHBWL 1 /* branch byte, word, or long */
431#define BRABSJUNC 2 /* absolute jump for LONG, unconditional */
432#define BRABSJCOND 3 /* absolute jump for LONG, conditional */
433#define BRANCHBW 4 /* branch byte or word */
434
435/* We also relax coprocessor branches and DBcc's. All CPUs that support
436 coprocessor branches support them in word and long forms, so we have only
437 one relaxation mode for them. DBcc's are word only on all CPUs. We can
438 relax them to the LONG form with a branch-around sequence. This sequence
439 can use a long branch (if available) or an absolute jump (if acceptable).
440 This gives us two relaxation modes. If long branches are not available and
441 absolute jumps are not acceptable, we don't relax DBcc's. */
442
443#define FBRANCH 5 /* coprocessor branch */
444#define DBCCLBR 6 /* DBcc relaxable with a long branch */
445#define DBCCABSJ 7 /* DBcc relaxable with an absolute jump */
446
447/* That's all for instruction relaxation. However, we also relax PC-relative
448 operands. Specifically, we have three operand relaxation modes. On the
449 68000 PC-relative operands can only be 16-bit, but on 68020 and higher and
450 on CPU32 they may be 16-bit or 32-bit. For the latter we relax between the
451 two. Also PC+displacement+index operands in their simple form (with a non-
452 suppressed index without memory indirection) are supported on all CPUs, but
453 on the 68000 the displacement can be 8-bit only, whereas on 68020 and higher
454 and on CPU32 we relax it to SHORT and LONG forms as well using the extended
455 form of the PC+displacement+index operand. Finally, some absolute operands
456 can be relaxed down to 16-bit PC-relative. */
457
458#define PCREL1632 8 /* 16-bit or 32-bit PC-relative */
459#define PCINDEX 9 /* PC+displacement+index */
460#define ABSTOPCREL 10 /* absolute relax down to 16-bit PC-relative */
252b5132
RH		 461
462/* Note that calls to frag_var need to specify the maximum expansion
463 needed; this is currently 10 bytes for DBCC. */
464
465/* The fields are:
466 How far Forward this mode will reach:
467 How far Backward this mode will reach:
468 How many bytes this mode will add to the size of the frag
469 Which mode to go to if the offset won't fit in this one
470 */
471relax_typeS md_relax_table[] =
472{
473 {1, 1, 0, 0}, /* First entries aren't used */
474 {1, 1, 0, 0}, /* For no good reason except */
475 {1, 1, 0, 0}, /* that the VAX doesn't either */
476 {1, 1, 0, 0},
477
151337e8
NC		 478 {(127), (-128), 0, TAB (BRANCHBWL, SHORT)},
479 {(32767), (-32768), 2, TAB (BRANCHBWL, LONG)},
252b5132
RH		 480 {0, 0, 4, 0},
481 {1, 1, 0, 0},
482
151337e8
NC		 483 {(127), (-128), 0, TAB (BRABSJUNC, SHORT)},
484 {(32767), (-32768), 2, TAB (BRABSJUNC, LONG)},
252b5132
RH		 485 {0, 0, 4, 0},
486 {1, 1, 0, 0},
487
151337e8
NC		 488 {(127), (-128), 0, TAB (BRABSJCOND, SHORT)},
489 {(32767), (-32768), 2, TAB (BRABSJCOND, LONG)},
490 {0, 0, 6, 0},
491 {1, 1, 0, 0},
492
493 {(127), (-128), 0, TAB (BRANCHBW, SHORT)},
494 {0, 0, 2, 0},
495 {1, 1, 0, 0},
496 {1, 1, 0, 0},
497
498 {1, 1, 0, 0}, /* FBRANCH doesn't come BYTE */
499 {(32767), (-32768), 2, TAB (FBRANCH, LONG)},
252b5132
RH		 500 {0, 0, 4, 0},
501 {1, 1, 0, 0},
502
151337e8
NC		 503 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
504 {(32767), (-32768), 2, TAB (DBCCLBR, LONG)},
505 {0, 0, 10, 0},
252b5132
RH		 506 {1, 1, 0, 0},
507
508 {1, 1, 0, 0}, /* DBCC doesn't come BYTE */
151337e8
NC		 509 {(32767), (-32768), 2, TAB (DBCCABSJ, LONG)},
510 {0, 0, 10, 0},
252b5132
RH		 511 {1, 1, 0, 0},
512
151337e8
NC		 513 {1, 1, 0, 0}, /* PCREL1632 doesn't come BYTE */
514 {32767, -32768, 2, TAB (PCREL1632, LONG)},
252b5132
RH		 515 {0, 0, 6, 0},
516 {1, 1, 0, 0},
517
252b5132
RH		 518 {125, -130, 0, TAB (PCINDEX, SHORT)},
519 {32765, -32770, 2, TAB (PCINDEX, LONG)},
520 {0, 0, 4, 0},
521 {1, 1, 0, 0},
151337e8
NC		 522
523 {1, 1, 0, 0}, /* ABSTOPCREL doesn't come BYTE */
524 {(32767), (-32768), 2, TAB (ABSTOPCREL, LONG)},
525 {0, 0, 4, 0},
526 {1, 1, 0, 0},
252b5132
RH		 527};
528
529/* These are the machine dependent pseudo-ops. These are included so
530 the assembler can work on the output from the SUN C compiler, which
531 generates these.
532 */
533
534/* This table describes all the machine specific pseudo-ops the assembler
535 has to support. The fields are:
536 pseudo-op name without dot
537 function to call to execute this pseudo-op
538 Integer arg to pass to the function
539 */
540const pseudo_typeS md_pseudo_table[] =
541{
542 {"data1", s_data1, 0},
543 {"data2", s_data2, 0},
544 {"bss", s_bss, 0},
545 {"even", s_even, 0},
546 {"skip", s_space, 0},
547 {"proc", s_proc, 0},
548#if defined (TE_SUN3) || defined (OBJ_ELF)
549 {"align", s_align_bytes, 0},
550#endif
551#ifdef OBJ_ELF
552 {"swbeg", s_ignore, 0},
553#endif
554 {"extend", float_cons, 'x'},
555 {"ldouble", float_cons, 'x'},
556
557 /* The following pseudo-ops are supported for MRI compatibility. */
558 {"chip", s_chip, 0},
559 {"comline", s_space, 1},
560 {"fopt", s_fopt, 0},
561 {"mask2", s_ignore, 0},
562 {"opt", s_opt, 0},
563 {"reg", s_reg, 0},
564 {"restore", s_restore, 0},
565 {"save", s_save, 0},
566
567 {"if", s_mri_if, 0},
568 {"if.b", s_mri_if, 'b'},
569 {"if.w", s_mri_if, 'w'},
570 {"if.l", s_mri_if, 'l'},
571 {"else", s_mri_else, 0},
572 {"else.s", s_mri_else, 's'},
573 {"else.l", s_mri_else, 'l'},
574 {"endi", s_mri_endi, 0},
575 {"break", s_mri_break, 0},
576 {"break.s", s_mri_break, 's'},
577 {"break.l", s_mri_break, 'l'},
578 {"next", s_mri_next, 0},
579 {"next.s", s_mri_next, 's'},
580 {"next.l", s_mri_next, 'l'},
581 {"for", s_mri_for, 0},
582 {"for.b", s_mri_for, 'b'},
583 {"for.w", s_mri_for, 'w'},
584 {"for.l", s_mri_for, 'l'},
585 {"endf", s_mri_endf, 0},
586 {"repeat", s_mri_repeat, 0},
587 {"until", s_mri_until, 0},
588 {"until.b", s_mri_until, 'b'},
589 {"until.w", s_mri_until, 'w'},
590 {"until.l", s_mri_until, 'l'},
591 {"while", s_mri_while, 0},
592 {"while.b", s_mri_while, 'b'},
593 {"while.w", s_mri_while, 'w'},
594 {"while.l", s_mri_while, 'l'},
595 {"endw", s_mri_endw, 0},
596
597 {0, 0, 0}
598};
599
252b5132
RH		 600/* The mote pseudo ops are put into the opcode table, since they
601 don't start with a . they look like opcodes to gas.
602 */
603
604#ifdef M68KCOFF
605extern void obj_coff_section PARAMS ((int));
606#endif
607
608CONST pseudo_typeS mote_pseudo_table[] =
609{
610
611 {"dcl", cons, 4},
612 {"dc", cons, 2},
613 {"dcw", cons, 2},
614 {"dcb", cons, 1},
615
616 {"dsl", s_space, 4},
617 {"ds", s_space, 2},
618 {"dsw", s_space, 2},
619 {"dsb", s_space, 1},
620
621 {"xdef", s_globl, 0},
622#ifdef OBJ_ELF
623 {"align", s_align_bytes, 0},
624#else
625 {"align", s_align_ptwo, 0},
626#endif
627#ifdef M68KCOFF
628 {"sect", obj_coff_section, 0},
629 {"section", obj_coff_section, 0},
630#endif
631 {0, 0, 0}
632};
633
634#define issbyte(x) ((x)>=-128 && (x)<=127)
635#define isubyte(x) ((x)>=0 && (x)<=255)
636#define issword(x) ((x)>=-32768 && (x)<=32767)
637#define isuword(x) ((x)>=0 && (x)<=65535)
638
639#define isbyte(x) ((x)>= -255 && (x)<=255)
640#define isword(x) ((x)>=-65536 && (x)<=65535)
641#define islong(x) (1)
642
643extern char *input_line_pointer;
644
645static char mklower_table[256];
bc805888 646#define mklower(c) (mklower_table[(unsigned char) (c)])
252b5132
RH		 647static char notend_table[256];
648static char alt_notend_table[256];
649#define notend(s) \
650 (! (notend_table[(unsigned char) *s] \
651 || (*s == ':' \
652 && alt_notend_table[(unsigned char) s[1]])))
653
654#if defined (M68KCOFF) && !defined (BFD_ASSEMBLER)
655
656#ifdef NO_PCREL_RELOCS
657
658int
659make_pcrel_absolute(fixP, add_number)
660 fixS *fixP;
661 long *add_number;
662{
663 register unsigned char *opcode = fixP->fx_frag->fr_opcode;
664
665 /* rewrite the PC relative instructions to absolute address ones.
666 * these are rumoured to be faster, and the apollo linker refuses
667 * to deal with the PC relative relocations.
668 */
669 if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */
670 {
671 opcode[0] = 0x4e;
672 opcode[1] = 0xf9;
673 }
674 else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */
675 {
676 opcode[0] = 0x4e;
677 opcode[1] = 0xb9;
678 }
679 else
680 as_fatal (_("Unknown PC relative instruction"));
681 *add_number -= 4;
682 return 0;
683}
684
685#endif /* NO_PCREL_RELOCS */
686
687short
688tc_coff_fix2rtype (fixP)
689 fixS *fixP;
690{
691 if (fixP->fx_tcbit && fixP->fx_size == 4)
692 return R_RELLONG_NEG;
693#ifdef NO_PCREL_RELOCS
694 know (fixP->fx_pcrel == 0);
695 return (fixP->fx_size == 1 ? R_RELBYTE
696 : fixP->fx_size == 2 ? R_DIR16
697 : R_DIR32);
698#else
699 return (fixP->fx_pcrel ?
700 (fixP->fx_size == 1 ? R_PCRBYTE :
701 fixP->fx_size == 2 ? R_PCRWORD :
702 R_PCRLONG) :
703 (fixP->fx_size == 1 ? R_RELBYTE :
704 fixP->fx_size == 2 ? R_RELWORD :
705 R_RELLONG));
706#endif
707}
708
709#endif
710
711#ifdef OBJ_ELF
712
713/* Compute the relocation code for a fixup of SIZE bytes, using pc
714 relative relocation if PCREL is non-zero. PIC says whether a special
715 pic relocation was requested. */
716
717static bfd_reloc_code_real_type get_reloc_code
718 PARAMS ((int, int, enum pic_relocation));
719
720static bfd_reloc_code_real_type
721get_reloc_code (size, pcrel, pic)
722 int size;
723 int pcrel;
724 enum pic_relocation pic;
725{
726 switch (pic)
727 {
728 case pic_got_pcrel:
729 switch (size)
730 {
731 case 1:
732 return BFD_RELOC_8_GOT_PCREL;
733 case 2:
734 return BFD_RELOC_16_GOT_PCREL;
735 case 4:
736 return BFD_RELOC_32_GOT_PCREL;
737 }
738 break;
739
740 case pic_got_off:
741 switch (size)
742 {
743 case 1:
744 return BFD_RELOC_8_GOTOFF;
745 case 2:
746 return BFD_RELOC_16_GOTOFF;
747 case 4:
748 return BFD_RELOC_32_GOTOFF;
749 }
750 break;
751
752 case pic_plt_pcrel:
753 switch (size)
754 {
755 case 1:
756 return BFD_RELOC_8_PLT_PCREL;
757 case 2:
758 return BFD_RELOC_16_PLT_PCREL;
759 case 4:
760 return BFD_RELOC_32_PLT_PCREL;
761 }
762 break;
763
764 case pic_plt_off:
765 switch (size)
766 {
767 case 1:
768 return BFD_RELOC_8_PLTOFF;
769 case 2:
770 return BFD_RELOC_16_PLTOFF;
771 case 4:
772 return BFD_RELOC_32_PLTOFF;
773 }
774 break;
775
776 case pic_none:
777 if (pcrel)
778 {
779 switch (size)
780 {
781 case 1:
782 return BFD_RELOC_8_PCREL;
783 case 2:
784 return BFD_RELOC_16_PCREL;
785 case 4:
786 return BFD_RELOC_32_PCREL;
787 }
788 }
789 else
790 {
791 switch (size)
792 {
793 case 1:
794 return BFD_RELOC_8;
795 case 2:
796 return BFD_RELOC_16;
797 case 4:
798 return BFD_RELOC_32;
799 }
800 }
801 }
802
803 if (pcrel)
804 {
805 if (pic == pic_none)
806 as_bad (_("Can not do %d byte pc-relative relocation"), size);
807 else
808 as_bad (_("Can not do %d byte pc-relative pic relocation"), size);
809 }
810 else
811 {
812 if (pic == pic_none)
813 as_bad (_("Can not do %d byte relocation"), size);
814 else
815 as_bad (_("Can not do %d byte pic relocation"), size);
816 }
817
818 return BFD_RELOC_NONE;
819}
820
821/* Here we decide which fixups can be adjusted to make them relative
822 to the beginning of the section instead of the symbol. Basically
823 we need to make sure that the dynamic relocations are done
824 correctly, so in some cases we force the original symbol to be
825 used. */
826int
827tc_m68k_fix_adjustable (fixP)
828 fixS *fixP;
829{
92774660 830 /* Prevent all adjustments to global symbols. */
252b5132
RH		 831 if (S_IS_EXTERNAL (fixP->fx_addsy)
832 || S_IS_WEAK (fixP->fx_addsy))
833 return 0;
834
835 /* adjust_reloc_syms doesn't know about the GOT */
836 switch (fixP->fx_r_type)
837 {
838 case BFD_RELOC_8_GOT_PCREL:
839 case BFD_RELOC_16_GOT_PCREL:
840 case BFD_RELOC_32_GOT_PCREL:
841 case BFD_RELOC_8_GOTOFF:
842 case BFD_RELOC_16_GOTOFF:
843 case BFD_RELOC_32_GOTOFF:
844 case BFD_RELOC_8_PLT_PCREL:
845 case BFD_RELOC_16_PLT_PCREL:
846 case BFD_RELOC_32_PLT_PCREL:
847 case BFD_RELOC_8_PLTOFF:
848 case BFD_RELOC_16_PLTOFF:
849 case BFD_RELOC_32_PLTOFF:
850 return 0;
851
852 case BFD_RELOC_VTABLE_INHERIT:
853 case BFD_RELOC_VTABLE_ENTRY:
854 return 0;
855
856 default:
857 return 1;
858 }
859}
860
861#else /* !OBJ_ELF */
862
863#define get_reloc_code(SIZE,PCREL,OTHER) NO_RELOC
864
865#endif /* OBJ_ELF */
866
867#ifdef BFD_ASSEMBLER
868
869arelent *
870tc_gen_reloc (section, fixp)
871 asection *section;
872 fixS *fixp;
873{
874 arelent *reloc;
875 bfd_reloc_code_real_type code;
876
8ec6253e
NC		 877 /* If the tcbit is set, then this was a fixup of a negative value
878 that was never resolved. We do not have a reloc to handle this,
879 so just return. We assume that other code will have detected this
880 situation and produced a helpful error message, so we just tell the
881 user that the reloc cannot be produced. */
252b5132 882 if (fixp->fx_tcbit)
8ec6253e
NC		 883 {
884 if (fixp->fx_addsy)
885 as_bad (_("Unable to produce reloc against symbol '%s'"),
886 S_GET_NAME (fixp->fx_addsy));
887 return NULL;
888 }
252b5132
RH		 889
890 if (fixp->fx_r_type != BFD_RELOC_NONE)
891 {
892 code = fixp->fx_r_type;
893
894 /* Since DIFF_EXPR_OK is defined in tc-m68k.h, it is possible
895 that fixup_segment converted a non-PC relative reloc into a
896 PC relative reloc. In such a case, we need to convert the
897 reloc code. */
898 if (fixp->fx_pcrel)
899 {
900 switch (code)
901 {
902 case BFD_RELOC_8:
903 code = BFD_RELOC_8_PCREL;
904 break;
905 case BFD_RELOC_16:
906 code = BFD_RELOC_16_PCREL;
907 break;
908 case BFD_RELOC_32:
909 code = BFD_RELOC_32_PCREL;
910 break;
911 case BFD_RELOC_8_PCREL:
912 case BFD_RELOC_16_PCREL:
913 case BFD_RELOC_32_PCREL:
914 case BFD_RELOC_8_GOT_PCREL:
915 case BFD_RELOC_16_GOT_PCREL:
916 case BFD_RELOC_32_GOT_PCREL:
917 case BFD_RELOC_8_GOTOFF:
918 case BFD_RELOC_16_GOTOFF:
919 case BFD_RELOC_32_GOTOFF:
920 case BFD_RELOC_8_PLT_PCREL:
921 case BFD_RELOC_16_PLT_PCREL:
922 case BFD_RELOC_32_PLT_PCREL:
923 case BFD_RELOC_8_PLTOFF:
924 case BFD_RELOC_16_PLTOFF:
925 case BFD_RELOC_32_PLTOFF:
926 break;
927 default:
928 as_bad_where (fixp->fx_file, fixp->fx_line,
929 _("Cannot make %s relocation PC relative"),
930 bfd_get_reloc_code_name (code));
931 }
932 }
933 }
934 else
935 {
936#define F(SZ,PCREL) (((SZ) << 1) + (PCREL))
937 switch (F (fixp->fx_size, fixp->fx_pcrel))
938 {
939#define MAP(SZ,PCREL,TYPE) case F(SZ,PCREL): code = (TYPE); break
940 MAP (1, 0, BFD_RELOC_8);
941 MAP (2, 0, BFD_RELOC_16);
942 MAP (4, 0, BFD_RELOC_32);
943 MAP (1, 1, BFD_RELOC_8_PCREL);
944 MAP (2, 1, BFD_RELOC_16_PCREL);
945 MAP (4, 1, BFD_RELOC_32_PCREL);
946 default:
947 abort ();
948 }
949 }
950#undef F
951#undef MAP
952
953 reloc = (arelent *) xmalloc (sizeof (arelent));
49309057
ILT		 954 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
955 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
252b5132
RH		 956 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
957#ifndef OBJ_ELF
958 if (fixp->fx_pcrel)
959 reloc->addend = fixp->fx_addnumber;
960 else
961 reloc->addend = 0;
962#else
963 if (!fixp->fx_pcrel)
964 reloc->addend = fixp->fx_addnumber;
965 else
966 reloc->addend = (section->vma
967 + (fixp->fx_pcrel_adjust == 64
968 ? -1 : fixp->fx_pcrel_adjust)
969 + fixp->fx_addnumber
970 + md_pcrel_from (fixp));
971#endif
972
973 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
974 assert (reloc->howto != 0);
975
976 return reloc;
977}
978
979#endif /* BFD_ASSEMBLER */
980
981/* Return zero if the reference to SYMBOL from within the same segment may
982 be relaxed. */
983#ifdef OBJ_ELF
984
985/* On an ELF system, we can't relax an externally visible symbol,
986 because it may be overridden by a shared library. However, if
987 TARGET_OS is "elf", then we presume that we are assembling for an
988 embedded system, in which case we don't have to worry about shared
989 libraries, and we can relax anything. */
990
991#define relaxable_symbol(symbol) \
992 (strcmp (TARGET_OS, "elf") == 0 \
993 || (! S_IS_EXTERNAL (symbol) \
994 && ! S_IS_WEAK (symbol)))
995
996#else
997
998#define relaxable_symbol(symbol) 1
999
1000#endif
92774660 1001
252b5132
RH		 1002/* Handle of the OPCODE hash table. NULL means any use before
1003 m68k_ip_begin() will crash. */
1004static struct hash_control *op_hash;
1005\f
1006/* Assemble an m68k instruction. */
1007
1008static void
1009m68k_ip (instring)
1010 char *instring;
1011{
1012 register char *p;
1013 register struct m68k_op *opP;
1014 register const struct m68k_incant *opcode;
1015 register const char *s;
1016 register int tmpreg = 0, baseo = 0, outro = 0, nextword;
1017 char *pdot, *pdotmove;
1018 enum m68k_size siz1, siz2;
1019 char c;
1020 int losing;
1021 int opsfound;
1022 LITTLENUM_TYPE words[6];
1023 LITTLENUM_TYPE *wordp;
1024 unsigned long ok_arch = 0;
1025
1026 if (*instring == ' ')
1027 instring++; /* skip leading whitespace */
1028
1029 /* Scan up to end of operation-code, which MUST end in end-of-string
92774660 1030 or exactly 1 space. */
252b5132
RH		 1031 pdot = 0;
1032 for (p = instring; *p != '\0'; p++)
1033 {
1034 if (*p == ' ')
1035 break;
1036 if (*p == '.')
1037 pdot = p;
1038 }
1039
1040 if (p == instring)
1041 {
1042 the_ins.error = _("No operator");
1043 return;
1044 }
1045
1046 /* p now points to the end of the opcode name, probably whitespace.
1047 Make sure the name is null terminated by clobbering the
1048 whitespace, look it up in the hash table, then fix it back.
1049 Remove a dot, first, since the opcode tables have none. */
1050 if (pdot != NULL)
1051 {
1052 for (pdotmove = pdot; pdotmove < p; pdotmove++)
1053 *pdotmove = pdotmove[1];
1054 p--;
1055 }
1056
1057 c = *p;
1058 *p = '\0';
1059 opcode = (const struct m68k_incant *) hash_find (op_hash, instring);
1060 *p = c;
1061
1062 if (pdot != NULL)
1063 {
1064 for (pdotmove = p; pdotmove > pdot; pdotmove--)
1065 *pdotmove = pdotmove[-1];
1066 *pdot = '.';
1067 ++p;
1068 }
1069
1070 if (opcode == NULL)
1071 {
1072 the_ins.error = _("Unknown operator");
1073 return;
1074 }
1075
1076 /* found a legitimate opcode, start matching operands */
1077 while (*p == ' ')
1078 ++p;
1079
1080 if (opcode->m_operands == 0)
1081 {
1082 char *old = input_line_pointer;
1083 *old = '\n';
1084 input_line_pointer = p;
1085 /* Ahh - it's a motorola style psuedo op */
1086 mote_pseudo_table[opcode->m_opnum].poc_handler
1087 (mote_pseudo_table[opcode->m_opnum].poc_val);
1088 input_line_pointer = old;
1089 *old = 0;
1090
1091 return;
1092 }
1093
1094 if (flag_mri && opcode->m_opnum == 0)
1095 {
1096 /* In MRI mode, random garbage is allowed after an instruction
1097 which accepts no operands. */
1098 the_ins.args = opcode->m_operands;
1099 the_ins.numargs = opcode->m_opnum;
1100 the_ins.numo = opcode->m_codenum;
1101 the_ins.opcode[0] = getone (opcode);
1102 the_ins.opcode[1] = gettwo (opcode);
1103 return;
1104 }
1105
1106 for (opP = &the_ins.operands[0]; *p; opP++)
1107 {
1108 p = crack_operand (p, opP);
1109
1110 if (opP->error)
1111 {
1112 the_ins.error = opP->error;
1113 return;
1114 }
1115 }
1116
1117 opsfound = opP - &the_ins.operands[0];
1118
1119 /* This ugly hack is to support the floating pt opcodes in their
1120 standard form. Essentially, we fake a first enty of type COP#1 */
1121 if (opcode->m_operands[0] == 'I')
1122 {
1123 int n;
1124
1125 for (n = opsfound; n > 0; --n)
1126 the_ins.operands[n] = the_ins.operands[n - 1];
1127
1128 memset ((char *) (&the_ins.operands[0]), '\0',
1129 sizeof (the_ins.operands[0]));
1130 the_ins.operands[0].mode = CONTROL;
1131 the_ins.operands[0].reg = m68k_float_copnum;
1132 opsfound++;
1133 }
1134
1135 /* We've got the operands. Find an opcode that'll accept them */
1136 for (losing = 0;;)
1137 {
1138 /* If we didn't get the right number of ops, or we have no
92774660 1139 common model with this pattern then reject this pattern. */
252b5132
RH		 1140
1141 ok_arch |= opcode->m_arch;
1142 if (opsfound != opcode->m_opnum
1143 || ((opcode->m_arch & current_architecture) == 0))
1144 ++losing;
1145 else
1146 {
1147 for (s = opcode->m_operands, opP = &the_ins.operands[0];
1148 *s && !losing;
1149 s += 2, opP++)
1150 {
1151 /* Warning: this switch is huge! */
1152 /* I've tried to organize the cases into this order:
1153 non-alpha first, then alpha by letter. Lower-case
1154 goes directly before uppercase counterpart. */
1155 /* Code with multiple case ...: gets sorted by the lowest
1156 case ... it belongs to. I hope this makes sense. */
1157 switch (*s)
1158 {
1159 case '!':
1160 switch (opP->mode)
1161 {
1162 case IMMED:
1163 case DREG:
1164 case AREG:
1165 case FPREG:
1166 case CONTROL:
1167 case AINC:
1168 case ADEC:
1169 case REGLST:
1170 losing++;
1171 break;
1172 default:
1173 break;
1174 }
1175 break;
1176
1177 case '<':
1178 switch (opP->mode)
1179 {
1180 case DREG:
1181 case AREG:
1182 case FPREG:
1183 case CONTROL:
1184 case IMMED:
1185 case ADEC:
1186 case REGLST:
1187 losing++;
1188 break;
1189 default:
1190 break;
1191 }
1192 break;
1193
1194 case '>':
1195 switch (opP->mode)
1196 {
1197 case DREG:
1198 case AREG:
1199 case FPREG:
1200 case CONTROL:
1201 case IMMED:
1202 case AINC:
1203 case REGLST:
1204 losing++;
1205 break;
1206 case ABSL:
1207 break;
1208 default:
1209 if (opP->reg == PC
1210 || opP->reg == ZPC)
1211 losing++;
1212 break;
1213 }
1214 break;
1215
1216 case 'm':
1217 switch (opP->mode)
1218 {
1219 case DREG:
1220 case AREG:
1221 case AINDR:
1222 case AINC:
1223 case ADEC:
1224 break;
1225 default:
1226 losing++;
1227 }
1228 break;
1229
1230 case 'n':
1231 switch (opP->mode)
1232 {
1233 case DISP:
1234 break;
1235 default:
1236 losing++;
1237 }
1238 break;
1239
1240 case 'o':
1241 switch (opP->mode)
1242 {
1243 case BASE:
1244 case ABSL:
1245 case IMMED:
1246 break;
1247 default:
1248 losing++;
1249 }
1250 break;
1251
1252 case 'p':
1253 switch (opP->mode)
1254 {
1255 case DREG:
1256 case AREG:
1257 case AINDR:
1258 case AINC:
1259 case ADEC:
1260 break;
1261 case DISP:
1262 if (opP->reg == PC || opP->reg == ZPC)
1263 losing++;
1264 break;
1265 default:
1266 losing++;
1267 }
1268 break;
1269
1270 case 'q':
1271 switch (opP->mode)
1272 {
1273 case DREG:
1274 case AINDR:
1275 case AINC:
1276 case ADEC:
1277 break;
1278 case DISP:
1279 if (opP->reg == PC || opP->reg == ZPC)
1280 losing++;
1281 break;
1282 default:
1283 losing++;
1284 break;
1285 }
1286 break;
1287
1288 case 'v':
1289 switch (opP->mode)
1290 {
1291 case DREG:
1292 case AINDR:
1293 case AINC:
1294 case ADEC:
1295 case ABSL:
1296 break;
1297 case DISP:
1298 if (opP->reg == PC || opP->reg == ZPC)
1299 losing++;
1300 break;
1301 default:
1302 losing++;
1303 break;
1304 }
1305 break;
1306
1307 case '#':
1308 if (opP->mode != IMMED)
1309 losing++;
1310 else if (s[1] == 'b'
1311 && ! isvar (&opP->disp)
1312 && (opP->disp.exp.X_op != O_constant
1313 || ! isbyte (opP->disp.exp.X_add_number)))
1314 losing++;
1315 else if (s[1] == 'B'
1316 && ! isvar (&opP->disp)
1317 && (opP->disp.exp.X_op != O_constant
1318 || ! issbyte (opP->disp.exp.X_add_number)))
1319 losing++;
1320 else if (s[1] == 'w'
1321 && ! isvar (&opP->disp)
1322 && (opP->disp.exp.X_op != O_constant
1323 || ! isword (opP->disp.exp.X_add_number)))
1324 losing++;
1325 else if (s[1] == 'W'
1326 && ! isvar (&opP->disp)
1327 && (opP->disp.exp.X_op != O_constant
1328 || ! issword (opP->disp.exp.X_add_number)))
1329 losing++;
1330 break;
1331
1332 case '^':
1333 case 'T':
1334 if (opP->mode != IMMED)
1335 losing++;
1336 break;
1337
1338 case '$':
1339 if (opP->mode == AREG
1340 || opP->mode == CONTROL
1341 || opP->mode == FPREG
1342 || opP->mode == IMMED
1343 || opP->mode == REGLST
1344 || (opP->mode != ABSL
1345 && (opP->reg == PC
1346 || opP->reg == ZPC)))
1347 losing++;
1348 break;
1349
1350 case '%':
1351 if (opP->mode == CONTROL
1352 || opP->mode == FPREG
1353 || opP->mode == REGLST
1354 || opP->mode == IMMED
1355 || (opP->mode != ABSL
1356 && (opP->reg == PC
1357 || opP->reg == ZPC)))
1358 losing++;
1359 break;
1360
1361 case '&':
1362 switch (opP->mode)
1363 {
1364 case DREG:
1365 case AREG:
1366 case FPREG:
1367 case CONTROL:
1368 case IMMED:
1369 case AINC:
1370 case ADEC:
1371 case REGLST:
1372 losing++;
1373 break;
1374 case ABSL:
1375 break;
1376 default:
1377 if (opP->reg == PC
1378 || opP->reg == ZPC)
1379 losing++;
1380 break;
1381 }
1382 break;
1383
1384 case '*':
1385 if (opP->mode == CONTROL
1386 || opP->mode == FPREG
1387 || opP->mode == REGLST)
1388 losing++;
1389 break;
1390
1391 case '+':
1392 if (opP->mode != AINC)
1393 losing++;
1394 break;
1395
1396 case '-':
1397 if (opP->mode != ADEC)
1398 losing++;
1399 break;
1400
1401 case '/':
1402 switch (opP->mode)
1403 {
1404 case AREG:
1405 case CONTROL:
1406 case FPREG:
1407 case AINC:
1408 case ADEC:
1409 case IMMED:
1410 case REGLST:
1411 losing++;
1412 break;
1413 default:
1414 break;
1415 }
1416 break;
1417
1418 case ';':
1419 switch (opP->mode)
1420 {
1421 case AREG:
1422 case CONTROL:
1423 case FPREG:
1424 case REGLST:
1425 losing++;
1426 break;
1427 default:
1428 break;
1429 }
1430 break;
1431
1432 case '?':
1433 switch (opP->mode)
1434 {
1435 case AREG:
1436 case CONTROL:
1437 case FPREG:
1438 case AINC:
1439 case ADEC:
1440 case IMMED:
1441 case REGLST:
1442 losing++;
1443 break;
1444 case ABSL:
1445 break;
1446 default:
1447 if (opP->reg == PC || opP->reg == ZPC)
1448 losing++;
1449 break;
1450 }
1451 break;
1452
1453 case '@':
1454 switch (opP->mode)
1455 {
1456 case AREG:
1457 case CONTROL:
1458 case FPREG:
1459 case IMMED:
1460 case REGLST:
1461 losing++;
1462 break;
1463 default:
1464 break;
1465 }
1466 break;
1467
1468 case '~': /* For now! (JF FOO is this right?) */
1469 switch (opP->mode)
1470 {
1471 case DREG:
1472 case AREG:
1473 case CONTROL:
1474 case FPREG:
1475 case IMMED:
1476 case REGLST:
1477 losing++;
1478 break;
1479 case ABSL:
1480 break;
1481 default:
1482 if (opP->reg == PC
1483 || opP->reg == ZPC)
1484 losing++;
1485 break;
1486 }
1487 break;
1488
1489 case '3':
1490 if (opP->mode != CONTROL
1491 || (opP->reg != TT0 && opP->reg != TT1))
1492 losing++;
1493 break;
1494
1495 case 'A':
1496 if (opP->mode != AREG)
1497 losing++;
1498 break;
1499
1500 case 'a':
1501 if (opP->mode != AINDR)
1502 ++losing;
1503 break;
1504
1505 case 'B': /* FOO */
1506 if (opP->mode != ABSL
1507 || (flag_long_jumps
1508 && strncmp (instring, "jbsr", 4) == 0))
1509 losing++;
1510 break;
1511
1512 case 'C':
1513 if (opP->mode != CONTROL || opP->reg != CCR)
1514 losing++;
1515 break;
1516
1517 case 'd':
1518 if (opP->mode != DISP
1519 || opP->reg < ADDR0
1520 || opP->reg > ADDR7)
1521 losing++;
1522 break;
1523
1524 case 'D':
1525 if (opP->mode != DREG)
1526 losing++;
1527 break;
1528
6da466c7
ILT		 1529 case 'E':
1530 if (opP->reg != ACC)
1531 losing++;
1532 break;
1533
252b5132
RH		 1534 case 'F':
1535 if (opP->mode != FPREG)
1536 losing++;
1537 break;
1538
6da466c7
ILT		 1539 case 'G':
1540 if (opP->reg != MACSR)
1541 losing++;
1542 break;
1543
1544 case 'H':
1545 if (opP->reg != MASK)
1546 losing++;
1547 break;
1548
252b5132
RH		 1549 case 'I':
1550 if (opP->mode != CONTROL
1551 || opP->reg < COP0
1552 || opP->reg > COP7)
1553 losing++;
1554 break;
1555
1556 case 'J':
1557 if (opP->mode != CONTROL
1558 || opP->reg < USP
1559 || opP->reg > last_movec_reg)
1560 losing++;
1561 else
1562 {
1563 const enum m68k_register *rp;
1564 for (rp = control_regs; *rp; rp++)
1565 if (*rp == opP->reg)
1566 break;
1567 if (*rp == 0)
1568 losing++;
1569 }
1570 break;
1571
1572 case 'k':
1573 if (opP->mode != IMMED)
1574 losing++;
1575 break;
1576
1577 case 'l':
1578 case 'L':
1579 if (opP->mode == DREG
1580 || opP->mode == AREG
1581 || opP->mode == FPREG)
1582 {
1583 if (s[1] == '8')
1584 losing++;
1585 else
1586 {
1587 switch (opP->mode)
1588 {
1589 case DREG:
1590 opP->mask = 1 << (opP->reg - DATA0);
1591 break;
1592 case AREG:
1593 opP->mask = 1 << (opP->reg - ADDR0 + 8);
1594 break;
1595 case FPREG:
1596 opP->mask = 1 << (opP->reg - FP0 + 16);
1597 break;
1598 default:
1599 abort ();
1600 }
1601 opP->mode = REGLST;
1602 }
1603 }
1604 else if (opP->mode == CONTROL)
1605 {
1606 if (s[1] != '8')
1607 losing++;
1608 else
1609 {
1610 switch (opP->reg)
1611 {
1612 case FPI:
1613 opP->mask = 1 << 24;
1614 break;
1615 case FPS:
1616 opP->mask = 1 << 25;
1617 break;
1618 case FPC:
1619 opP->mask = 1 << 26;
1620 break;
1621 default:
1622 losing++;
1623 break;
1624 }
1625 opP->mode = REGLST;
1626 }
1627 }
1628 else if (opP->mode != REGLST)
1629 losing++;
1630 else if (s[1] == '8' && (opP->mask & 0x0ffffff) != 0)
1631 losing++;
1632 else if (s[1] == '3' && (opP->mask & 0x7000000) != 0)
1633 losing++;
1634 break;
1635
1636 case 'M':
1637 if (opP->mode != IMMED)
1638 losing++;
1639 else if (opP->disp.exp.X_op != O_constant
1640 || ! issbyte (opP->disp.exp.X_add_number))
1641 losing++;
1642 else if (! m68k_quick
1643 && instring[3] != 'q'
1644 && instring[4] != 'q')
1645 losing++;
1646 break;
1647
1648 case 'O':
1649 if (opP->mode != DREG
1650 && opP->mode != IMMED
1651 && opP->mode != ABSL)
1652 losing++;
1653 break;
1654
1655 case 'Q':
1656 if (opP->mode != IMMED)
1657 losing++;
1658 else if (opP->disp.exp.X_op != O_constant
1659 || opP->disp.exp.X_add_number < 1
1660 || opP->disp.exp.X_add_number > 8)
1661 losing++;
1662 else if (! m68k_quick
1663 && (strncmp (instring, "add", 3) == 0
1664 || strncmp (instring, "sub", 3) == 0)
1665 && instring[3] != 'q')
1666 losing++;
1667 break;
1668
1669 case 'R':
1670 if (opP->mode != DREG && opP->mode != AREG)
1671 losing++;
1672 break;
1673
1674 case 'r':
1675 if (opP->mode != AINDR
1676 && (opP->mode != BASE
1677 || (opP->reg != 0
1678 && opP->reg != ZADDR0)
1679 || opP->disp.exp.X_op != O_absent
1680 || ((opP->index.reg < DATA0
1681 || opP->index.reg > DATA7)
1682 && (opP->index.reg < ADDR0
1683 || opP->index.reg > ADDR7))
1684 || opP->index.size != SIZE_UNSPEC
1685 || opP->index.scale != 1))
1686 losing++;
1687 break;
1688
1689 case 's':
1690 if (opP->mode != CONTROL
1691 || ! (opP->reg == FPI
1692 || opP->reg == FPS
1693 || opP->reg == FPC))
1694 losing++;
1695 break;
1696
1697 case 'S':
1698 if (opP->mode != CONTROL || opP->reg != SR)
1699 losing++;
1700 break;
1701
1702 case 't':
1703 if (opP->mode != IMMED)
1704 losing++;
1705 else if (opP->disp.exp.X_op != O_constant
1706 || opP->disp.exp.X_add_number < 0
1707 || opP->disp.exp.X_add_number > 7)
1708 losing++;
1709 break;
1710
1711 case 'U':
1712 if (opP->mode != CONTROL || opP->reg != USP)
1713 losing++;
1714 break;
1715
1716 /* JF these are out of order. We could put them
1717 in order if we were willing to put up with
1718 bunches of #ifdef m68851s in the code.
1719
1720 Don't forget that you need these operands
1721 to use 68030 MMU instructions. */
1722#ifndef NO_68851
1723 /* Memory addressing mode used by pflushr */
1724 case '|':
1725 if (opP->mode == CONTROL
1726 || opP->mode == FPREG
1727 || opP->mode == DREG
1728 || opP->mode == AREG
1729 || opP->mode == REGLST)
1730 losing++;
1731 /* We should accept immediate operands, but they
1732 supposedly have to be quad word, and we don't
1733 handle that. I would like to see what a Motorola
1734 assembler does before doing something here. */
1735 if (opP->mode == IMMED)
1736 losing++;
1737 break;
1738
1739 case 'f':
1740 if (opP->mode != CONTROL
1741 || (opP->reg != SFC && opP->reg != DFC))
1742 losing++;
1743 break;
1744
1745 case '0':
1746 if (opP->mode != CONTROL || opP->reg != TC)
1747 losing++;
1748 break;
1749
1750 case '1':
1751 if (opP->mode != CONTROL || opP->reg != AC)
1752 losing++;
1753 break;
1754
1755 case '2':
1756 if (opP->mode != CONTROL
1757 || (opP->reg != CAL
1758 && opP->reg != VAL
1759 && opP->reg != SCC))
1760 losing++;
1761 break;
1762
1763 case 'V':
1764 if (opP->mode != CONTROL
1765 || opP->reg != VAL)
1766 losing++;
1767 break;
1768
1769 case 'W':
1770 if (opP->mode != CONTROL
1771 || (opP->reg != DRP
1772 && opP->reg != SRP
1773 && opP->reg != CRP))
1774 losing++;
1775 break;
1776
1777 case 'X':
1778 if (opP->mode != CONTROL
1779 || (!(opP->reg >= BAD && opP->reg <= BAD + 7)
1780 && !(opP->reg >= BAC && opP->reg <= BAC + 7)))
1781 losing++;
1782 break;
1783
1784 case 'Y':
1785 if (opP->mode != CONTROL || opP->reg != PSR)
1786 losing++;
1787 break;
1788
1789 case 'Z':
1790 if (opP->mode != CONTROL || opP->reg != PCSR)
1791 losing++;
1792 break;
1793#endif
1794 case 'c':
1795 if (opP->mode != CONTROL
1796 || (opP->reg != NC
1797 && opP->reg != IC
1798 && opP->reg != DC
1799 && opP->reg != BC))
1800 {
1801 losing++;
92774660 1802 } /* not a cache specifier. */
252b5132
RH		 1803 break;
1804
1805 case '_':
1806 if (opP->mode != ABSL)
1807 ++losing;
1808 break;
1809
6da466c7
ILT		 1810 case 'u':
1811 if (opP->reg < DATA0L || opP->reg > ADDR7U)
1812 losing++;
1813 /* FIXME: kludge instead of fixing parser:
1814 upper/lower registers are *not* CONTROL
92774660 1815 registers, but ordinary ones. */
6da466c7
ILT		 1816 if ((opP->reg >= DATA0L && opP->reg <= DATA7L)
1817 || (opP->reg >= DATA0U && opP->reg <= DATA7U))
1818 opP->mode = DREG;
1819 else
1820 opP->mode = AREG;
1821 break;
1822
252b5132
RH		 1823 default:
1824 abort ();
1825 } /* switch on type of operand */
1826
1827 if (losing)
1828 break;
1829 } /* for each operand */
1830 } /* if immediately wrong */
1831
1832 if (!losing)
1833 {
1834 break;
92774660 1835 } /* got it. */
252b5132
RH		 1836
1837 opcode = opcode->m_next;
1838
1839 if (!opcode)
1840 {
1841 if (ok_arch
1842 && !(ok_arch & current_architecture))
1843 {
1844 char buf[200], *cp;
1845
1846 strcpy (buf,
1847 _("invalid instruction for this architecture; needs "));
1848 cp = buf + strlen (buf);
1849 switch (ok_arch)
1850 {
1851 case mfloat:
1852 strcpy (cp, _("fpu (68040, 68060 or 68881/68882)"));
1853 break;
1854 case mmmu:
1855 strcpy (cp, _("mmu (68030 or 68851)"));
1856 break;
1857 case m68020up:
1858 strcpy (cp, _("68020 or higher"));
1859 break;
1860 case m68000up:
1861 strcpy (cp, _("68000 or higher"));
1862 break;
1863 case m68010up:
1864 strcpy (cp, _("68010 or higher"));
1865 break;
1866 default:
1867 {
1868 int got_one = 0, idx;
8fce3f5e
AM		 1869 for (idx = 0;
1870 idx < (int) (sizeof (archs) / sizeof (archs[0]));
252b5132
RH		 1871 idx++)
1872 {
1873 if ((archs[idx].arch & ok_arch)
1874 && ! archs[idx].alias)
1875 {
1876 if (got_one)
1877 {
1878 strcpy (cp, " or ");
1879 cp += strlen (cp);
1880 }
1881 got_one = 1;
1882 strcpy (cp, archs[idx].name);
1883 cp += strlen (cp);
1884 }
1885 }
1886 }
1887 }
1888 cp = xmalloc (strlen (buf) + 1);
1889 strcpy (cp, buf);
1890 the_ins.error = cp;
1891 }
1892 else
1893 the_ins.error = _("operands mismatch");
1894 return;
1895 } /* Fell off the end */
1896
1897 losing = 0;
1898 }
1899
1900 /* now assemble it */
1901
1902 the_ins.args = opcode->m_operands;
1903 the_ins.numargs = opcode->m_opnum;
1904 the_ins.numo = opcode->m_codenum;
1905 the_ins.opcode[0] = getone (opcode);
1906 the_ins.opcode[1] = gettwo (opcode);
1907
1908 for (s = the_ins.args, opP = &the_ins.operands[0]; *s; s += 2, opP++)
1909 {
1910 /* This switch is a doozy.
1911 Watch the first step; its a big one! */
1912 switch (s[0])
1913 {
1914
1915 case '*':
1916 case '~':
1917 case '%':
1918 case ';':
1919 case '@':
1920 case '!':
1921 case '&':
1922 case '$':
1923 case '?':
1924 case '/':
1925 case '<':
1926 case '>':
1927 case 'm':
1928 case 'n':
1929 case 'o':
1930 case 'p':
1931 case 'q':
1932 case 'v':
1933#ifndef NO_68851
1934 case '|':
1935#endif
1936 switch (opP->mode)
1937 {
1938 case IMMED:
1939 tmpreg = 0x3c; /* 7.4 */
1940 if (strchr ("bwl", s[1]))
1941 nextword = get_num (&opP->disp, 80);
1942 else
1943 nextword = get_num (&opP->disp, 0);
1944 if (isvar (&opP->disp))
1945 add_fix (s[1], &opP->disp, 0, 0);
1946 switch (s[1])
1947 {
1948 case 'b':
1949 if (!isbyte (nextword))
1950 opP->error = _("operand out of range");
1951 addword (nextword);
1952 baseo = 0;
1953 break;
1954 case 'w':
1955 if (!isword (nextword))
1956 opP->error = _("operand out of range");
1957 addword (nextword);
1958 baseo = 0;
1959 break;
1960 case 'W':
1961 if (!issword (nextword))
1962 opP->error = _("operand out of range");
1963 addword (nextword);
1964 baseo = 0;
1965 break;
1966 case 'l':
1967 addword (nextword >> 16);
1968 addword (nextword);
1969 baseo = 0;
1970 break;
1971
1972 case 'f':
1973 baseo = 2;
1974 outro = 8;
1975 break;
1976 case 'F':
1977 baseo = 4;
1978 outro = 11;
1979 break;
1980 case 'x':
1981 baseo = 6;
1982 outro = 15;
1983 break;
1984 case 'p':
1985 baseo = 6;
1986 outro = -1;
1987 break;
1988 default:
1989 abort ();
1990 }
1991 if (!baseo)
1992 break;
1993
1994 /* We gotta put out some float */
1995 if (op (&opP->disp) != O_big)
1996 {
1997 valueT val;
1998 int gencnt;
1999
2000 /* Can other cases happen here? */
2001 if (op (&opP->disp) != O_constant)
2002 abort ();
2003
2004 val = (valueT) offs (&opP->disp);
2005 gencnt = 0;
2006 do
2007 {
2008 generic_bignum[gencnt] = (LITTLENUM_TYPE) val;
2009 val >>= LITTLENUM_NUMBER_OF_BITS;
2010 ++gencnt;
2011 }
2012 while (val != 0);
2013 offs (&opP->disp) = gencnt;
2014 }
2015 if (offs (&opP->disp) > 0)
2016 {
2017 if (offs (&opP->disp) > baseo)
2018 {
2019 as_warn (_("Bignum too big for %c format; truncated"),
2020 s[1]);
2021 offs (&opP->disp) = baseo;
2022 }
2023 baseo -= offs (&opP->disp);
2024 while (baseo--)
2025 addword (0);
2026 for (wordp = generic_bignum + offs (&opP->disp) - 1;
2027 offs (&opP->disp)--;
2028 --wordp)
2029 addword (*wordp);
2030 break;
2031 }
2032 gen_to_words (words, baseo, (long) outro);
2033 for (wordp = words; baseo--; wordp++)
2034 addword (*wordp);
2035 break;
2036 case DREG:
2037 tmpreg = opP->reg - DATA; /* 0.dreg */
2038 break;
2039 case AREG:
2040 tmpreg = 0x08 + opP->reg - ADDR; /* 1.areg */
2041 break;
2042 case AINDR:
2043 tmpreg = 0x10 + opP->reg - ADDR; /* 2.areg */
2044 break;
2045 case ADEC:
2046 tmpreg = 0x20 + opP->reg - ADDR; /* 4.areg */
2047 break;
2048 case AINC:
2049 tmpreg = 0x18 + opP->reg - ADDR; /* 3.areg */
2050 break;
2051 case DISP:
2052
2053 nextword = get_num (&opP->disp, 80);
2054
2055 if (opP->reg == PC
2056 && ! isvar (&opP->disp)
2057 && m68k_abspcadd)
2058 {
2059 opP->disp.exp.X_op = O_symbol;
2060#ifndef BFD_ASSEMBLER
2061 opP->disp.exp.X_add_symbol = &abs_symbol;
2062#else
2063 opP->disp.exp.X_add_symbol =
2064 section_symbol (absolute_section);
2065#endif
2066 }
2067
2068 /* Force into index mode. Hope this works */
2069
2070 /* We do the first bit for 32-bit displacements, and the
2071 second bit for 16 bit ones. It is possible that we
2072 should make the default be WORD instead of LONG, but
2073 I think that'd break GCC, so we put up with a little
2074 inefficiency for the sake of working output. */
2075
2076 if (!issword (nextword)
2077 || (isvar (&opP->disp)
2078 && ((opP->disp.size == SIZE_UNSPEC
2079 && flag_short_refs == 0
2080 && cpu_of_arch (current_architecture) >= m68020
6da466c7 2081 && ! arch_coldfire_p (current_architecture))
252b5132
RH		 2082 || opP->disp.size == SIZE_LONG)))
2083 {
2084 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2085 || arch_coldfire_p (current_architecture))
252b5132
RH		 2086 opP->error =
2087 _("displacement too large for this architecture; needs 68020 or higher");
2088 if (opP->reg == PC)
2089 tmpreg = 0x3B; /* 7.3 */
2090 else
2091 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2092 if (isvar (&opP->disp))
2093 {
2094 if (opP->reg == PC)
2095 {
2096 if (opP->disp.size == SIZE_LONG
2097#ifdef OBJ_ELF
2098 /* If the displacement needs pic
2099 relocation it cannot be relaxed. */
2100 || opP->disp.pic_reloc != pic_none
2101#endif
2102 )
2103 {
2104 addword (0x0170);
2105 add_fix ('l', &opP->disp, 1, 2);
2106 }
2107 else
2108 {
2109 add_frag (adds (&opP->disp),
2110 offs (&opP->disp),
151337e8 2111 TAB (PCREL1632, SZ_UNDEF));
252b5132
RH		 2112 break;
2113 }
2114 }
2115 else
2116 {
2117 addword (0x0170);
2118 add_fix ('l', &opP->disp, 0, 0);
2119 }
2120 }
2121 else
2122 addword (0x0170);
2123 addword (nextword >> 16);
2124 }
2125 else
2126 {
2127 if (opP->reg == PC)
2128 tmpreg = 0x3A; /* 7.2 */
2129 else
2130 tmpreg = 0x28 + opP->reg - ADDR; /* 5.areg */
2131
2132 if (isvar (&opP->disp))
2133 {
2134 if (opP->reg == PC)
2135 {
2136 add_fix ('w', &opP->disp, 1, 0);
2137 }
2138 else
2139 add_fix ('w', &opP->disp, 0, 0);
2140 }
2141 }
2142 addword (nextword);
2143 break;
2144
2145 case POST:
2146 case PRE:
2147 case BASE:
2148 nextword = 0;
2149 baseo = get_num (&opP->disp, 80);
2150 if (opP->mode == POST || opP->mode == PRE)
2151 outro = get_num (&opP->odisp, 80);
2152 /* Figure out the `addressing mode'.
2153 Also turn on the BASE_DISABLE bit, if needed. */
2154 if (opP->reg == PC || opP->reg == ZPC)
2155 {
2156 tmpreg = 0x3b; /* 7.3 */
2157 if (opP->reg == ZPC)
2158 nextword |= 0x80;
2159 }
2160 else if (opP->reg == 0)
2161 {
2162 nextword |= 0x80;
2163 tmpreg = 0x30; /* 6.garbage */
2164 }
2165 else if (opP->reg >= ZADDR0 && opP->reg <= ZADDR7)
2166 {
2167 nextword |= 0x80;
2168 tmpreg = 0x30 + opP->reg - ZADDR0;
2169 }
2170 else
2171 tmpreg = 0x30 + opP->reg - ADDR; /* 6.areg */
2172
2173 siz1 = opP->disp.size;
2174 if (opP->mode == POST || opP->mode == PRE)
2175 siz2 = opP->odisp.size;
2176 else
2177 siz2 = SIZE_UNSPEC;
2178
2179 /* Index register stuff */
2180 if (opP->index.reg != 0
2181 && opP->index.reg >= DATA
2182 && opP->index.reg <= ADDR7)
2183 {
2184 nextword |= (opP->index.reg - DATA) << 12;
2185
2186 if (opP->index.size == SIZE_LONG
2187 || (opP->index.size == SIZE_UNSPEC
2188 && m68k_index_width_default == SIZE_LONG))
2189 nextword |= 0x800;
2190
92774660 2191 if ((opP->index.scale != 1
252b5132 2192 && cpu_of_arch (current_architecture) < m68020)
92774660 2193 || (opP->index.scale == 8
6da466c7 2194 && arch_coldfire_p (current_architecture)))
252b5132
RH		 2195 {
2196 opP->error =
2197 _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher");
2198 }
2199
6da466c7
ILT		 2200 if (arch_coldfire_p (current_architecture)
2201 && opP->index.size == SIZE_WORD)
2202 opP->error = _("invalid index size for coldfire");
2203
252b5132
RH		 2204 switch (opP->index.scale)
2205 {
2206 case 1:
2207 break;
2208 case 2:
2209 nextword |= 0x200;
2210 break;
2211 case 4:
2212 nextword |= 0x400;
2213 break;
2214 case 8:
2215 nextword |= 0x600;
2216 break;
2217 default:
2218 abort ();
2219 }
2220 /* IF its simple,
2221 GET US OUT OF HERE! */
2222
2223 /* Must be INDEX, with an index register. Address
2224 register cannot be ZERO-PC, and either :b was
2225 forced, or we know it will fit. For a 68000 or
2226 68010, force this mode anyways, because the
2227 larger modes aren't supported. */
2228 if (opP->mode == BASE
2229 && ((opP->reg >= ADDR0
2230 && opP->reg <= ADDR7)
2231 || opP->reg == PC))
2232 {
2233 if (siz1 == SIZE_BYTE
2234 || cpu_of_arch (current_architecture) < m68020
6da466c7 2235 || arch_coldfire_p (current_architecture)
252b5132
RH		 2236 || (siz1 == SIZE_UNSPEC
2237 && ! isvar (&opP->disp)
2238 && issbyte (baseo)))
2239 {
2240 nextword += baseo & 0xff;
2241 addword (nextword);
2242 if (isvar (&opP->disp))
2243 {
2244 /* Do a byte relocation. If it doesn't
2245 fit (possible on m68000) let the
2246 fixup processing complain later. */
2247 if (opP->reg == PC)
2248 add_fix ('B', &opP->disp, 1, 1);
2249 else
2250 add_fix ('B', &opP->disp, 0, 0);
2251 }
2252 else if (siz1 != SIZE_BYTE)
2253 {
2254 if (siz1 != SIZE_UNSPEC)
2255 as_warn (_("Forcing byte displacement"));
2256 if (! issbyte (baseo))
2257 opP->error = _("byte displacement out of range");
2258 }
2259
2260 break;
2261 }
2262 else if (siz1 == SIZE_UNSPEC
2263 && opP->reg == PC
2264 && isvar (&opP->disp)
2265 && subs (&opP->disp) == NULL
2266#ifdef OBJ_ELF
2267 /* If the displacement needs pic
2268 relocation it cannot be relaxed. */
2269 && opP->disp.pic_reloc == pic_none
2270#endif
2271 )
2272 {
2273 /* The code in md_convert_frag_1 needs to be
2274 able to adjust nextword. Call frag_grow
2275 to ensure that we have enough space in
2276 the frag obstack to make all the bytes
2277 contiguous. */
2278 frag_grow (14);
2279 nextword += baseo & 0xff;
2280 addword (nextword);
2281 add_frag (adds (&opP->disp), offs (&opP->disp),
2282 TAB (PCINDEX, SZ_UNDEF));
2283
2284 break;
2285 }
2286 }
2287 }
2288 else
2289 {
2290 nextword |= 0x40; /* No index reg */
2291 if (opP->index.reg >= ZDATA0
2292 && opP->index.reg <= ZDATA7)
2293 nextword |= (opP->index.reg - ZDATA0) << 12;
2294 else if (opP->index.reg >= ZADDR0
2295 || opP->index.reg <= ZADDR7)
2296 nextword |= (opP->index.reg - ZADDR0 + 8) << 12;
2297 }
2298
2299 /* It isn't simple. */
2300
2301 if (cpu_of_arch (current_architecture) < m68020
6da466c7 2302 || arch_coldfire_p (current_architecture))
252b5132
RH		 2303 opP->error =
2304 _("invalid operand mode for this architecture; needs 68020 or higher");
2305
2306 nextword |= 0x100;
2307 /* If the guy specified a width, we assume that it is
2308 wide enough. Maybe it isn't. If so, we lose. */
2309 switch (siz1)
2310 {
2311 case SIZE_UNSPEC:
2312 if (isvar (&opP->disp)
2313 ? m68k_rel32
2314 : ! issword (baseo))
2315 {
2316 siz1 = SIZE_LONG;
2317 nextword |= 0x30;
2318 }
2319 else if (! isvar (&opP->disp) && baseo == 0)
2320 nextword |= 0x10;
2321 else
2322 {
2323 nextword |= 0x20;
2324 siz1 = SIZE_WORD;
2325 }
2326 break;
2327 case SIZE_BYTE:
2328 as_warn (_(":b not permitted; defaulting to :w"));
2329 /* Fall through. */
2330 case SIZE_WORD:
2331 nextword |= 0x20;
2332 break;
2333 case SIZE_LONG:
2334 nextword |= 0x30;
2335 break;
2336 }
2337
2338 /* Figure out innner displacement stuff */
2339 if (opP->mode == POST || opP->mode == PRE)
2340 {
2341 if (cpu_of_arch (current_architecture) & cpu32)
2342 opP->error = _("invalid operand mode for this architecture; needs 68020 or higher");
2343 switch (siz2)
2344 {
2345 case SIZE_UNSPEC:
2346 if (isvar (&opP->odisp)
2347 ? m68k_rel32
2348 : ! issword (outro))
2349 {
2350 siz2 = SIZE_LONG;
2351 nextword |= 0x3;
2352 }
2353 else if (! isvar (&opP->odisp) && outro == 0)
2354 nextword |= 0x1;
2355 else
2356 {
2357 nextword |= 0x2;
2358 siz2 = SIZE_WORD;
2359 }
2360 break;
2361 case 1:
2362 as_warn (_(":b not permitted; defaulting to :w"));
2363 /* Fall through. */
2364 case 2:
2365 nextword |= 0x2;
2366 break;
2367 case 3:
2368 nextword |= 0x3;
2369 break;
2370 }
2371 if (opP->mode == POST
2372 && (nextword & 0x40) == 0)
2373 nextword |= 0x04;
2374 }
2375 addword (nextword);
2376
2377 if (siz1 != SIZE_UNSPEC && isvar (&opP->disp))
2378 {
2379 if (opP->reg == PC || opP->reg == ZPC)
2380 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 1, 2);
2381 else
2382 add_fix (siz1 == SIZE_LONG ? 'l' : 'w', &opP->disp, 0, 0);
2383 }
2384 if (siz1 == SIZE_LONG)
2385 addword (baseo >> 16);
2386 if (siz1 != SIZE_UNSPEC)
2387 addword (baseo);
2388
2389 if (siz2 != SIZE_UNSPEC && isvar (&opP->odisp))
2390 add_fix (siz2 == SIZE_LONG ? 'l' : 'w', &opP->odisp, 0, 0);
2391 if (siz2 == SIZE_LONG)
2392 addword (outro >> 16);
2393 if (siz2 != SIZE_UNSPEC)
2394 addword (outro);
2395
2396 break;
2397
2398 case ABSL:
2399 nextword = get_num (&opP->disp, 80);
2400 switch (opP->disp.size)
2401 {
2402 default:
2403 abort ();
2404 case SIZE_UNSPEC:
2405 if (!isvar (&opP->disp) && issword (offs (&opP->disp)))
2406 {
2407 tmpreg = 0x38; /* 7.0 */
2408 addword (nextword);
2409 break;
2410 }
252b5132
RH		 2411 if (isvar (&opP->disp)
2412 && !subs (&opP->disp)
2413 && adds (&opP->disp)
2414#ifdef OBJ_ELF
2415 /* If the displacement needs pic relocation it
2416 cannot be relaxed. */
2417 && opP->disp.pic_reloc == pic_none
2418#endif
252b5132
RH		 2419 && !flag_long_jumps
2420 && !strchr ("~%&$?", s[0]))
2421 {
2422 tmpreg = 0x3A; /* 7.2 */
2423 add_frag (adds (&opP->disp),
2424 offs (&opP->disp),
151337e8 2425 TAB (ABSTOPCREL, SZ_UNDEF));
252b5132
RH		 2426 break;
2427 }
2428 /* Fall through into long */
2429 case SIZE_LONG:
2430 if (isvar (&opP->disp))
2431 add_fix ('l', &opP->disp, 0, 0);
2432
2433 tmpreg = 0x39;/* 7.1 mode */
2434 addword (nextword >> 16);
2435 addword (nextword);
2436 break;
2437
2438 case SIZE_BYTE:
2439 as_bad (_("unsupported byte value; use a different suffix"));
2440 /* Fall through. */
2441 case SIZE_WORD: /* Word */
2442 if (isvar (&opP->disp))
2443 add_fix ('w', &opP->disp, 0, 0);
2444
2445 tmpreg = 0x38;/* 7.0 mode */
2446 addword (nextword);
2447 break;
2448 }
2449 break;
2450 case CONTROL:
2451 case FPREG:
2452 default:
2453 as_bad (_("unknown/incorrect operand"));
bc805888 2454 /* abort (); */
252b5132
RH		 2455 }
2456 install_gen_operand (s[1], tmpreg);
2457 break;
2458
2459 case '#':
2460 case '^':
2461 switch (s[1])
2462 { /* JF: I hate floating point! */
2463 case 'j':
2464 tmpreg = 70;
2465 break;
2466 case '8':
2467 tmpreg = 20;
2468 break;
2469 case 'C':
2470 tmpreg = 50;
2471 break;
2472 case '3':
2473 default:
2474 tmpreg = 80;
2475 break;
2476 }
2477 tmpreg = get_num (&opP->disp, tmpreg);
2478 if (isvar (&opP->disp))
2479 add_fix (s[1], &opP->disp, 0, 0);
2480 switch (s[1])
2481 {
2482 case 'b': /* Danger: These do no check for
2483 certain types of overflow.
2484 user beware! */
2485 if (!isbyte (tmpreg))
2486 opP->error = _("out of range");
2487 insop (tmpreg, opcode);
2488 if (isvar (&opP->disp))
2489 the_ins.reloc[the_ins.nrel - 1].n =
2490 (opcode->m_codenum) * 2 + 1;
2491 break;
2492 case 'B':
2493 if (!issbyte (tmpreg))
2494 opP->error = _("out of range");
2495 the_ins.opcode[the_ins.numo - 1] |= tmpreg & 0xff;
2496 if (isvar (&opP->disp))
2497 the_ins.reloc[the_ins.nrel - 1].n = opcode->m_codenum * 2 - 1;
2498 break;
2499 case 'w':
2500 if (!isword (tmpreg))
2501 opP->error = _("out of range");
2502 insop (tmpreg, opcode);
2503 if (isvar (&opP->disp))
2504 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2505 break;
2506 case 'W':
2507 if (!issword (tmpreg))
2508 opP->error = _("out of range");
2509 insop (tmpreg, opcode);
2510 if (isvar (&opP->disp))
2511 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2512 break;
2513 case 'l':
2514 /* Because of the way insop works, we put these two out
2515 backwards. */
2516 insop (tmpreg, opcode);
2517 insop (tmpreg >> 16, opcode);
2518 if (isvar (&opP->disp))
2519 the_ins.reloc[the_ins.nrel - 1].n = (opcode->m_codenum) * 2;
2520 break;
2521 case '3':
2522 tmpreg &= 0xFF;
2523 case '8':
2524 case 'C':
2525 case 'j':
2526 install_operand (s[1], tmpreg);
2527 break;
2528 default:
2529 abort ();
2530 }
2531 break;
2532
2533 case '+':
2534 case '-':
2535 case 'A':
2536 case 'a':
2537 install_operand (s[1], opP->reg - ADDR);
2538 break;
2539
2540 case 'B':
2541 tmpreg = get_num (&opP->disp, 80);
2542 switch (s[1])
2543 {
2544 case 'B':
2545 /* The pc_fix argument winds up in fx_pcrel_adjust,
2546 which is a char, and may therefore be unsigned. We
2547 want to pass -1, but we pass 64 instead, and convert
2548 back in md_pcrel_from. */
2549 add_fix ('B', &opP->disp, 1, 64);
2550 break;
2551 case 'W':
2552 add_fix ('w', &opP->disp, 1, 0);
2553 addword (0);
2554 break;
2555 case 'L':
2556 long_branch:
151337e8 2557 if (! HAVE_LONG_BRANCH (current_architecture))
81d4177b 2558 as_warn (_("Can't use long branches on 68000/68010/5200"));
151337e8 2559 the_ins.opcode[0] |= 0xff;
252b5132
RH		 2560 add_fix ('l', &opP->disp, 1, 0);
2561 addword (0);
2562 addword (0);
2563 break;
2564 case 'g':
2565 if (subs (&opP->disp)) /* We can't relax it */
2566 goto long_branch;
2567
2568#ifdef OBJ_ELF
2569 /* If the displacement needs pic relocation it cannot be
2570 relaxed. */
2571 if (opP->disp.pic_reloc != pic_none)
2572 goto long_branch;
2573#endif
252b5132 2574 /* This could either be a symbol, or an absolute
151337e8
NC		 2575 address. If it's an absolute address, turn it into
2576 an absolute jump right here and keep it out of the
2577 relaxer. */
2578 if (adds (&opP->disp) == 0)
2579 {
2580 if (the_ins.opcode[0] == 0x6000) /* jbra */
2581 the_ins.opcode[0] = 0x4EF1;
2582 else if (the_ins.opcode[0] == 0x6100) /* jbsr */
2583 the_ins.opcode[0] = 0x4EB1;
2584 else /* jCC */
2585 {
2586 the_ins.opcode[0] ^= 0x0100;
2587 the_ins.opcode[0] |= 0x0006;
2588 addword (0x4EF1);
2589 }
2590 add_fix ('l', &opP->disp, 0, 0);
2591 addword (0);
2592 addword (0);
2593 break;
2594 }
2595
2596 /* Now we know it's going into the relaxer. Now figure
2597 out which mode. We try in this order of preference:
2598 long branch, absolute jump, byte/word branches only. */
2599 if (HAVE_LONG_BRANCH (current_architecture))
252b5132 2600 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8
NC		 2601 TAB (BRANCHBWL, SZ_UNDEF));
2602 else if (! flag_keep_pcrel)
2603 {
2604 if ((the_ins.opcode[0] == 0x6000)
2605 || (the_ins.opcode[0] == 0x6100))
2606 add_frag (adds (&opP->disp), offs (&opP->disp),
2607 TAB (BRABSJUNC, SZ_UNDEF));
2608 else
2609 add_frag (adds (&opP->disp), offs (&opP->disp),
2610 TAB (BRABSJCOND, SZ_UNDEF));
2611 }
252b5132
RH		 2612 else
2613 add_frag (adds (&opP->disp), offs (&opP->disp),
151337e8 2614 TAB (BRANCHBW, SZ_UNDEF));
252b5132
RH		 2615 break;
2616 case 'w':
2617 if (isvar (&opP->disp))
2618 {
151337e8
NC		 2619 /* Check for DBcc instructions. We can relax them,
2620 but only if we have long branches and/or absolute
2621 jumps. */
2622 if (((the_ins.opcode[0] & 0xf0f8) == 0x50c8)
2623 && (HAVE_LONG_BRANCH (current_architecture)
2624 || (! flag_keep_pcrel)))
252b5132 2625 {
151337e8
NC		 2626 if (HAVE_LONG_BRANCH (current_architecture))
2627 add_frag (adds (&opP->disp), offs (&opP->disp),
2628 TAB (DBCCLBR, SZ_UNDEF));
2629 else
2630 add_frag (adds (&opP->disp), offs (&opP->disp),
2631 TAB (DBCCABSJ, SZ_UNDEF));
252b5132
RH		 2632 break;
2633 }
252b5132
RH		 2634 add_fix ('w', &opP->disp, 1, 0);
2635 }
2636 addword (0);
2637 break;
2638 case 'C': /* Fixed size LONG coproc branches */
2639 add_fix ('l', &opP->disp, 1, 0);
2640 addword (0);
2641 addword (0);
2642 break;
2643 case 'c': /* Var size Coprocesssor branches */
151337e8 2644 if (subs (&opP->disp) || (adds (&opP->disp) == 0))
252b5132 2645 {
252b5132
RH		 2646 the_ins.opcode[the_ins.numo - 1] |= 0x40;
2647 add_fix ('l', &opP->disp, 1, 0);
2648 addword (0);
2649 addword (0);
2650 }
151337e8
NC		 2651 else
2652 add_frag (adds (&opP->disp), offs (&opP->disp),
2653 TAB (FBRANCH, SZ_UNDEF));
252b5132
RH		 2654 break;
2655 default:
2656 abort ();
2657 }
2658 break;
2659
2660 case 'C': /* Ignore it */
2661 break;
2662
2663 case 'd': /* JF this is a kludge */
2664 install_operand ('s', opP->reg - ADDR);
2665 tmpreg = get_num (&opP->disp, 80);
2666 if (!issword (tmpreg))
2667 {
2668 as_warn (_("Expression out of range, using 0"));
2669 tmpreg = 0;
2670 }
2671 addword (tmpreg);
2672 break;
2673
2674 case 'D':
2675 install_operand (s[1], opP->reg - DATA);
2676 break;
2677
6da466c7
ILT		 2678 case 'E': /* Ignore it */
2679 break;
2680
252b5132
RH		 2681 case 'F':
2682 install_operand (s[1], opP->reg - FP0);
2683 break;
2684
6da466c7
ILT		 2685 case 'G': /* Ignore it */
2686 case 'H':
2687 break;
2688
252b5132
RH		 2689 case 'I':
2690 tmpreg = opP->reg - COP0;
2691 install_operand (s[1], tmpreg);
2692 break;
2693
2694 case 'J': /* JF foo */
2695 switch (opP->reg)
2696 {
2697 case SFC:
2698 tmpreg = 0x000;
2699 break;
2700 case DFC:
2701 tmpreg = 0x001;
2702 break;
2703 case CACR:
2704 tmpreg = 0x002;
2705 break;
2706 case TC:
2707 tmpreg = 0x003;
2708 break;
2709 case ITT0:
2710 tmpreg = 0x004;
2711 break;
2712 case ITT1:
2713 tmpreg = 0x005;
2714 break;
2715 case DTT0:
2716 tmpreg = 0x006;
2717 break;
2718 case DTT1:
2719 tmpreg = 0x007;
2720 break;
2721 case BUSCR:
2722 tmpreg = 0x008;
2723 break;
2724
2725 case USP:
2726 tmpreg = 0x800;
2727 break;
2728 case VBR:
2729 tmpreg = 0x801;
2730 break;
2731 case CAAR:
2732 tmpreg = 0x802;
2733 break;
2734 case MSP:
2735 tmpreg = 0x803;
2736 break;
2737 case ISP:
2738 tmpreg = 0x804;
2739 break;
2740 case MMUSR:
2741 tmpreg = 0x805;
2742 break;
2743 case URP:
2744 tmpreg = 0x806;
2745 break;
2746 case SRP:
2747 tmpreg = 0x807;
2748 break;
2749 case PCR:
2750 tmpreg = 0x808;
2751 break;
2752 case ROMBAR:
2753 tmpreg = 0xC00;
2754 break;
2755 case RAMBAR0:
2756 tmpreg = 0xC04;
2757 break;
2758 case RAMBAR1:
2759 tmpreg = 0xC05;
2760 break;
2761 case MBAR:
2762 tmpreg = 0xC0F;
2763 break;
2764 default:
2765 abort ();
2766 }
2767 install_operand (s[1], tmpreg);
2768 break;
2769
2770 case 'k':
2771 tmpreg = get_num (&opP->disp, 55);
2772 install_operand (s[1], tmpreg & 0x7f);
2773 break;
2774
2775 case 'l':
2776 tmpreg = opP->mask;
2777 if (s[1] == 'w')
2778 {
2779 if (tmpreg & 0x7FF0000)
2780 as_bad (_("Floating point register in register list"));
2781 insop (reverse_16_bits (tmpreg), opcode);
2782 }
2783 else
2784 {
2785 if (tmpreg & 0x700FFFF)
2786 as_bad (_("Wrong register in floating-point reglist"));
2787 install_operand (s[1], reverse_8_bits (tmpreg >> 16));
2788 }
2789 break;
2790
2791 case 'L':
2792 tmpreg = opP->mask;
2793 if (s[1] == 'w')
2794 {
2795 if (tmpreg & 0x7FF0000)
2796 as_bad (_("Floating point register in register list"));
2797 insop (tmpreg, opcode);
2798 }
2799 else if (s[1] == '8')
2800 {
2801 if (tmpreg & 0x0FFFFFF)
2802 as_bad (_("incorrect register in reglist"));
2803 install_operand (s[1], tmpreg >> 24);
2804 }
2805 else
2806 {
2807 if (tmpreg & 0x700FFFF)
2808 as_bad (_("wrong register in floating-point reglist"));
2809 else
2810 install_operand (s[1], tmpreg >> 16);
2811 }
2812 break;
2813
2814 case 'M':
2815 install_operand (s[1], get_num (&opP->disp, 60));
2816 break;
2817
2818 case 'O':
2819 tmpreg = ((opP->mode == DREG)
8fce3f5e 2820 ? 0x20 + (int) (opP->reg - DATA)
252b5132
RH		 2821 : (get_num (&opP->disp, 40) & 0x1F));
2822 install_operand (s[1], tmpreg);
2823 break;
2824
2825 case 'Q':
2826 tmpreg = get_num (&opP->disp, 10);
2827 if (tmpreg == 8)
2828 tmpreg = 0;
2829 install_operand (s[1], tmpreg);
2830 break;
2831
2832 case 'R':
2833 /* This depends on the fact that ADDR registers are eight
2834 more than their corresponding DATA regs, so the result
2835 will have the ADDR_REG bit set */
2836 install_operand (s[1], opP->reg - DATA);
2837 break;
2838
2839 case 'r':
2840 if (opP->mode == AINDR)
2841 install_operand (s[1], opP->reg - DATA);
2842 else
2843 install_operand (s[1], opP->index.reg - DATA);
2844 break;
2845
2846 case 's':
2847 if (opP->reg == FPI)
2848 tmpreg = 0x1;
2849 else if (opP->reg == FPS)
2850 tmpreg = 0x2;
2851 else if (opP->reg == FPC)
2852 tmpreg = 0x4;
2853 else
2854 abort ();
2855 install_operand (s[1], tmpreg);
2856 break;
2857
2858 case 'S': /* Ignore it */
2859 break;
2860
2861 case 'T':
2862 install_operand (s[1], get_num (&opP->disp, 30));
2863 break;
2864
2865 case 'U': /* Ignore it */
2866 break;
2867
2868 case 'c':
2869 switch (opP->reg)
2870 {
2871 case NC:
2872 tmpreg = 0;
2873 break;
2874 case DC:
2875 tmpreg = 1;
2876 break;
2877 case IC:
2878 tmpreg = 2;
2879 break;
2880 case BC:
2881 tmpreg = 3;
2882 break;
2883 default:
2884 as_fatal (_("failed sanity check"));
2885 } /* switch on cache token */
2886 install_operand (s[1], tmpreg);
2887 break;
2888#ifndef NO_68851
92774660 2889 /* JF: These are out of order, I fear. */
252b5132
RH		 2890 case 'f':
2891 switch (opP->reg)
2892 {
2893 case SFC:
2894 tmpreg = 0;
2895 break;
2896 case DFC:
2897 tmpreg = 1;
2898 break;
2899 default:
2900 abort ();
2901 }
2902 install_operand (s[1], tmpreg);
2903 break;
2904
2905 case '0':
2906 case '1':
2907 case '2':
2908 switch (opP->reg)
2909 {
2910 case TC:
2911 tmpreg = 0;
2912 break;
2913 case CAL:
2914 tmpreg = 4;
2915 break;
2916 case VAL:
2917 tmpreg = 5;
2918 break;
2919 case SCC:
2920 tmpreg = 6;
2921 break;
2922 case AC:
2923 tmpreg = 7;
2924 break;
2925 default:
2926 abort ();
2927 }
2928 install_operand (s[1], tmpreg);
2929 break;
2930
2931 case 'V':
2932 if (opP->reg == VAL)
2933 break;
2934 abort ();
2935
2936 case 'W':
2937 switch (opP->reg)
2938 {
2939 case DRP:
2940 tmpreg = 1;
2941 break;
2942 case SRP:
2943 tmpreg = 2;
2944 break;
2945 case CRP:
2946 tmpreg = 3;
2947 break;
2948 default:
2949 abort ();
2950 }
2951 install_operand (s[1], tmpreg);
2952 break;
2953
2954 case 'X':
2955 switch (opP->reg)
2956 {
2957 case BAD:
2958 case BAD + 1:
2959 case BAD + 2:
2960 case BAD + 3:
2961 case BAD + 4:
2962 case BAD + 5:
2963 case BAD + 6:
2964 case BAD + 7:
2965 tmpreg = (4 << 10) | ((opP->reg - BAD) << 2);
2966 break;
2967
2968 case BAC:
2969 case BAC + 1:
2970 case BAC + 2:
2971 case BAC + 3:
2972 case BAC + 4:
2973 case BAC + 5:
2974 case BAC + 6:
2975 case BAC + 7:
2976 tmpreg = (5 << 10) | ((opP->reg - BAC) << 2);
2977 break;
2978
2979 default:
2980 abort ();
2981 }
2982 install_operand (s[1], tmpreg);
2983 break;
2984 case 'Y':
2985 know (opP->reg == PSR);
2986 break;
2987 case 'Z':
2988 know (opP->reg == PCSR);
2989 break;
2990#endif /* m68851 */
2991 case '3':
2992 switch (opP->reg)
2993 {
2994 case TT0:
2995 tmpreg = 2;
2996 break;
2997 case TT1:
2998 tmpreg = 3;
2999 break;
3000 default:
3001 abort ();
3002 }
3003 install_operand (s[1], tmpreg);
3004 break;
3005 case 't':
3006 tmpreg = get_num (&opP->disp, 20);
3007 install_operand (s[1], tmpreg);
3008 break;
3009 case '_': /* used only for move16 absolute 32-bit address */
3010 if (isvar (&opP->disp))
3011 add_fix ('l', &opP->disp, 0, 0);
3012 tmpreg = get_num (&opP->disp, 80);
3013 addword (tmpreg >> 16);
3014 addword (tmpreg & 0xFFFF);
3015 break;
6da466c7
ILT		 3016 case 'u':
3017 install_operand (s[1], opP->reg - DATA0L);
3018 opP->reg -= (DATA0L);
3019 opP->reg &= 0x0F; /* remove upper/lower bit */
3020 break;
252b5132
RH		 3021 default:
3022 abort ();
3023 }
3024 }
3025
3026 /* By the time whe get here (FINALLY) the_ins contains the complete
92774660 3027 instruction, ready to be emitted. . . */
252b5132
RH		 3028}
3029
3030static int
3031reverse_16_bits (in)
3032 int in;
3033{
3034 int out = 0;
3035 int n;
3036
3037 static int mask[16] =
3038 {
3039 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3040 0x0100, 0x0200, 0x0400, 0x0800, 0x1000, 0x2000, 0x4000, 0x8000
3041 };
3042 for (n = 0; n < 16; n++)
3043 {
3044 if (in & mask[n])
3045 out |= mask[15 - n];
3046 }
3047 return out;
3048} /* reverse_16_bits() */
3049
3050static int
3051reverse_8_bits (in)
3052 int in;
3053{
3054 int out = 0;
3055 int n;
3056
3057 static int mask[8] =
3058 {
3059 0x0001, 0x0002, 0x0004, 0x0008, 0x0010, 0x0020, 0x0040, 0x0080,
3060 };
3061
3062 for (n = 0; n < 8; n++)
3063 {
3064 if (in & mask[n])
3065 out |= mask[7 - n];
3066 }
3067 return out;
3068} /* reverse_8_bits() */
3069
3070/* Cause an extra frag to be generated here, inserting up to 10 bytes
3071 (that value is chosen in the frag_var call in md_assemble). TYPE
3072 is the subtype of the frag to be generated; its primary type is
3073 rs_machine_dependent.
3074
3075 The TYPE parameter is also used by md_convert_frag_1 and
3076 md_estimate_size_before_relax. The appropriate type of fixup will
3077 be emitted by md_convert_frag_1.
3078
3079 ADD becomes the FR_SYMBOL field of the frag, and OFF the FR_OFFSET. */
3080static void
3081install_operand (mode, val)
3082 int mode;
3083 int val;
3084{
3085 switch (mode)
3086 {
3087 case 's':
3088 the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */
3089 break;
3090 case 'd':
3091 the_ins.opcode[0] |= val << 9;
3092 break;
3093 case '1':
3094 the_ins.opcode[1] |= val << 12;
3095 break;
3096 case '2':
3097 the_ins.opcode[1] |= val << 6;
3098 break;
3099 case '3':
3100 the_ins.opcode[1] |= val;
3101 break;
3102 case '4':
3103 the_ins.opcode[2] |= val << 12;
3104 break;
3105 case '5':
3106 the_ins.opcode[2] |= val << 6;
3107 break;
3108 case '6':
3109 /* DANGER! This is a hack to force cas2l and cas2w cmds to be
3110 three words long! */
3111 the_ins.numo++;
3112 the_ins.opcode[2] |= val;
3113 break;
3114 case '7':
3115 the_ins.opcode[1] |= val << 7;
3116 break;
3117 case '8':
3118 the_ins.opcode[1] |= val << 10;
3119 break;
3120#ifndef NO_68851
3121 case '9':
3122 the_ins.opcode[1] |= val << 5;
3123 break;
3124#endif
3125
3126 case 't':
3127 the_ins.opcode[1] |= (val << 10) | (val << 7);
3128 break;
3129 case 'D':
3130 the_ins.opcode[1] |= (val << 12) | val;
3131 break;
3132 case 'g':
3133 the_ins.opcode[0] |= val = 0xff;
3134 break;
3135 case 'i':
3136 the_ins.opcode[0] |= val << 9;
3137 break;
3138 case 'C':
3139 the_ins.opcode[1] |= val;
3140 break;
3141 case 'j':
3142 the_ins.opcode[1] |= val;
3143 the_ins.numo++; /* What a hack */
3144 break;
3145 case 'k':
3146 the_ins.opcode[1] |= val << 4;
3147 break;
3148 case 'b':
3149 case 'w':
3150 case 'W':
3151 case 'l':
3152 break;
3153 case 'e':
3154 the_ins.opcode[0] |= (val << 6);
3155 break;
3156 case 'L':
3157 the_ins.opcode[1] = (val >> 16);
3158 the_ins.opcode[2] = val & 0xffff;
3159 break;
6da466c7
ILT		 3160 case 'm':
3161 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3162 the_ins.opcode[0] |= ((val & 0x7) << 9);
3163 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3164 break;
3165 case 'n':
3166 the_ins.opcode[0] |= ((val & 0x8) << (6 - 3));
3167 the_ins.opcode[0] |= ((val & 0x7) << 9);
3168 break;
3169 case 'o':
3170 the_ins.opcode[1] |= val << 12;
3171 the_ins.opcode[1] |= ((val & 0x10) << (7 - 4));
3172 break;
3173 case 'M':
3174 the_ins.opcode[0] |= (val & 0xF);
3175 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3176 break;
3177 case 'N':
3178 the_ins.opcode[1] |= (val & 0xF);
3179 the_ins.opcode[1] |= ((val & 0x10) << (6 - 4));
3180 break;
3181 case 'h':
3182 the_ins.opcode[1] |= ((val != 1) << 10);
3183 break;
252b5132
RH		 3184 case 'c':
3185 default:
3186 as_fatal (_("failed sanity check."));
3187 }
3188} /* install_operand() */
3189
3190static void
3191install_gen_operand (mode, val)
3192 int mode;
3193 int val;
3194{
3195 switch (mode)
3196 {
3197 case 's':
3198 the_ins.opcode[0] |= val;
3199 break;
3200 case 'd':
3201 /* This is a kludge!!! */
3202 the_ins.opcode[0] |= (val & 0x07) << 9 | (val & 0x38) << 3;
3203 break;
3204 case 'b':
3205 case 'w':
3206 case 'l':
3207 case 'f':
3208 case 'F':
3209 case 'x':
3210 case 'p':
3211 the_ins.opcode[0] |= val;
3212 break;
3213 /* more stuff goes here */
3214 default:
3215 as_fatal (_("failed sanity check."));
3216 }
3217} /* install_gen_operand() */
3218
3219/*
3220 * verify that we have some number of paren pairs, do m68k_ip_op(), and
3221 * then deal with the bitfield hack.
3222 */
3223
3224static char *
3225crack_operand (str, opP)
3226 register char *str;
3227 register struct m68k_op *opP;
3228{
3229 register int parens;
3230 register int c;
3231 register char *beg_str;
3232 int inquote = 0;
3233
3234 if (!str)
3235 {
3236 return str;
3237 }
3238 beg_str = str;
3239 for (parens = 0; *str && (parens > 0 || inquote || notend (str)); str++)
3240 {
3241 if (! inquote)
3242 {
3243 if (*str == '(')
3244 parens++;
3245 else if (*str == ')')
3246 {
3247 if (!parens)
3248 { /* ERROR */
3249 opP->error = _("Extra )");
3250 return str;
3251 }
3252 --parens;
3253 }
3254 }
3255 if (flag_mri && *str == '\'')
3256 inquote = ! inquote;
3257 }
3258 if (!*str && parens)
3259 { /* ERROR */
3260 opP->error = _("Missing )");
3261 return str;
3262 }
3263 c = *str;
3264 *str = '\0';
3265 if (m68k_ip_op (beg_str, opP) != 0)
3266 {
3267 *str = c;
3268 return str;
3269 }
3270 *str = c;
3271 if (c == '}')
3272 c = *++str; /* JF bitfield hack */
3273 if (c)
3274 {
3275 c = *++str;
3276 if (!c)
3277 as_bad (_("Missing operand"));
3278 }
3279
3280 /* Detect MRI REG symbols and convert them to REGLSTs. */
3281 if (opP->mode == CONTROL && (int)opP->reg < 0)
3282 {
3283 opP->mode = REGLST;
3284 opP->mask = ~(int)opP->reg;
3285 opP->reg = 0;
3286 }
3287
3288 return str;
3289}
3290
3291/* This is the guts of the machine-dependent assembler. STR points to a
3292 machine dependent instruction. This function is supposed to emit
3293 the frags/bytes it assembles to.
3294 */
3295
3296static void
3297insert_reg (regname, regnum)
3298 const char *regname;
3299 int regnum;
3300{
3301 char buf[100];
3302 int i;
3303
3304#ifdef REGISTER_PREFIX
3305 if (!flag_reg_prefix_optional)
3306 {
3307 buf[0] = REGISTER_PREFIX;
3308 strcpy (buf + 1, regname);
3309 regname = buf;
3310 }
3311#endif
3312
3313 symbol_table_insert (symbol_new (regname, reg_section, regnum,
3314 &zero_address_frag));
3315
3316 for (i = 0; regname[i]; i++)
3317 buf[i] = islower (regname[i]) ? toupper (regname[i]) : regname[i];
3318 buf[i] = '\0';
3319
3320 symbol_table_insert (symbol_new (buf, reg_section, regnum,
3321 &zero_address_frag));
3322}
3323
3324struct init_entry
3325 {
3326 const char *name;
3327 int number;
3328 };
3329
3330static const struct init_entry init_table[] =
3331{
3332 { "d0", DATA0 },
3333 { "d1", DATA1 },
3334 { "d2", DATA2 },
3335 { "d3", DATA3 },
3336 { "d4", DATA4 },
3337 { "d5", DATA5 },
3338 { "d6", DATA6 },
3339 { "d7", DATA7 },
3340 { "a0", ADDR0 },
3341 { "a1", ADDR1 },
3342 { "a2", ADDR2 },
3343 { "a3", ADDR3 },
3344 { "a4", ADDR4 },
3345 { "a5", ADDR5 },
3346 { "a6", ADDR6 },
3347 { "fp", ADDR6 },
3348 { "a7", ADDR7 },
3349 { "sp", ADDR7 },
3350 { "ssp", ADDR7 },
3351 { "fp0", FP0 },
3352 { "fp1", FP1 },
3353 { "fp2", FP2 },
3354 { "fp3", FP3 },
3355 { "fp4", FP4 },
3356 { "fp5", FP5 },
3357 { "fp6", FP6 },
3358 { "fp7", FP7 },
3359 { "fpi", FPI },
3360 { "fpiar", FPI },
3361 { "fpc", FPI },
3362 { "fps", FPS },
3363 { "fpsr", FPS },
3364 { "fpc", FPC },
3365 { "fpcr", FPC },
3366 { "control", FPC },
3367 { "status", FPS },
3368 { "iaddr", FPI },
3369
3370 { "cop0", COP0 },
3371 { "cop1", COP1 },
3372 { "cop2", COP2 },
3373 { "cop3", COP3 },
3374 { "cop4", COP4 },
3375 { "cop5", COP5 },
3376 { "cop6", COP6 },
3377 { "cop7", COP7 },
3378 { "pc", PC },
3379 { "zpc", ZPC },
3380 { "sr", SR },
3381
3382 { "ccr", CCR },
3383 { "cc", CCR },
3384
6da466c7
ILT		 3385 { "acc", ACC },
3386 { "macsr", MACSR },
3387 { "mask", MASK },
3388
252b5132
RH		 3389 /* control registers */
3390 { "sfc", SFC }, /* Source Function Code */
3391 { "sfcr", SFC },
3392 { "dfc", DFC }, /* Destination Function Code */
3393 { "dfcr", DFC },
3394 { "cacr", CACR }, /* Cache Control Register */
3395 { "caar", CAAR }, /* Cache Address Register */
3396
3397 { "usp", USP }, /* User Stack Pointer */
3398 { "vbr", VBR }, /* Vector Base Register */
3399 { "msp", MSP }, /* Master Stack Pointer */
3400 { "isp", ISP }, /* Interrupt Stack Pointer */
3401
3402 { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */
3403 { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */
3404 { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */
3405 { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */
3406
3407 /* 68ec040 versions of same */
3408 { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */
3409 { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */
3410 { "dacr0", DTT0 }, /* Data Access Control Register 0 */
3411 { "dacr1", DTT1 }, /* Data Access Control Register 0 */
3412
3413 /* mcf5200 versions of same. The ColdFire programmer's reference
3414 manual indicated that the order is 2,3,0,1, but Ken Rose
3415 <rose@netcom.com> says that 0,1,2,3 is the correct order. */
3416 { "acr0", ITT0 }, /* Access Control Unit 0 */
3417 { "acr1", ITT1 }, /* Access Control Unit 1 */
3418 { "acr2", DTT0 }, /* Access Control Unit 2 */
3419 { "acr3", DTT1 }, /* Access Control Unit 3 */
3420
3421 { "tc", TC }, /* MMU Translation Control Register */
3422 { "tcr", TC },
3423
3424 { "mmusr", MMUSR }, /* MMU Status Register */
3425 { "srp", SRP }, /* User Root Pointer */
3426 { "urp", URP }, /* Supervisor Root Pointer */
3427
3428 { "buscr", BUSCR },
3429 { "pcr", PCR },
3430
3431 { "rombar", ROMBAR }, /* ROM Base Address Register */
3432 { "rambar0", RAMBAR0 }, /* ROM Base Address Register */
3433 { "rambar1", RAMBAR1 }, /* ROM Base Address Register */
3434 { "mbar", MBAR }, /* Module Base Address Register */
3435 /* end of control registers */
3436
3437 { "ac", AC },
3438 { "bc", BC },
3439 { "cal", CAL },
3440 { "crp", CRP },
3441 { "drp", DRP },
3442 { "pcsr", PCSR },
3443 { "psr", PSR },
3444 { "scc", SCC },
3445 { "val", VAL },
3446 { "bad0", BAD0 },
3447 { "bad1", BAD1 },
3448 { "bad2", BAD2 },
3449 { "bad3", BAD3 },
3450 { "bad4", BAD4 },
3451 { "bad5", BAD5 },
3452 { "bad6", BAD6 },
3453 { "bad7", BAD7 },
3454 { "bac0", BAC0 },
3455 { "bac1", BAC1 },
3456 { "bac2", BAC2 },
3457 { "bac3", BAC3 },
3458 { "bac4", BAC4 },
3459 { "bac5", BAC5 },
3460 { "bac6", BAC6 },
3461 { "bac7", BAC7 },
3462
3463 { "ic", IC },
3464 { "dc", DC },
3465 { "nc", NC },
3466
3467 { "tt0", TT0 },
3468 { "tt1", TT1 },
3469 /* 68ec030 versions of same */
3470 { "ac0", TT0 },
3471 { "ac1", TT1 },
3472 /* 68ec030 access control unit, identical to 030 MMU status reg */
3473 { "acusr", PSR },
3474
3475 /* Suppressed data and address registers. */
3476 { "zd0", ZDATA0 },
3477 { "zd1", ZDATA1 },
3478 { "zd2", ZDATA2 },
3479 { "zd3", ZDATA3 },
3480 { "zd4", ZDATA4 },
3481 { "zd5", ZDATA5 },
3482 { "zd6", ZDATA6 },
3483 { "zd7", ZDATA7 },
3484 { "za0", ZADDR0 },
3485 { "za1", ZADDR1 },
3486 { "za2", ZADDR2 },
3487 { "za3", ZADDR3 },
3488 { "za4", ZADDR4 },
3489 { "za5", ZADDR5 },
3490 { "za6", ZADDR6 },
3491 { "za7", ZADDR7 },
3492
92774660 3493 /* Upper and lower data and address registers, used by macw and msacw. */
6da466c7
ILT		 3494 { "d0l", DATA0L },
3495 { "d1l", DATA1L },
3496 { "d2l", DATA2L },
3497 { "d3l", DATA3L },
3498 { "d4l", DATA4L },
3499 { "d5l", DATA5L },
3500 { "d6l", DATA6L },
3501 { "d7l", DATA7L },
3502
3503 { "a0l", ADDR0L },
3504 { "a1l", ADDR1L },
3505 { "a2l", ADDR2L },
3506 { "a3l", ADDR3L },
3507 { "a4l", ADDR4L },
3508 { "a5l", ADDR5L },
3509 { "a6l", ADDR6L },
3510 { "a7l", ADDR7L },
3511
3512 { "d0u", DATA0U },
3513 { "d1u", DATA1U },
3514 { "d2u", DATA2U },
3515 { "d3u", DATA3U },
3516 { "d4u", DATA4U },
3517 { "d5u", DATA5U },
3518 { "d6u", DATA6U },
3519 { "d7u", DATA7U },
3520
3521 { "a0u", ADDR0U },
3522 { "a1u", ADDR1U },
3523 { "a2u", ADDR2U },
3524 { "a3u", ADDR3U },
3525 { "a4u", ADDR4U },
3526 { "a5u", ADDR5U },
3527 { "a6u", ADDR6U },
3528 { "a7u", ADDR7U },
3529
252b5132
RH		 3530 { 0, 0 }
3531};
3532
3533static void
3534init_regtable ()
3535{
3536 int i;
3537 for (i = 0; init_table[i].name; i++)
3538 insert_reg (init_table[i].name, init_table[i].number);
3539}
3540
3541static int no_68851, no_68881;
3542
3543#ifdef OBJ_AOUT
3544/* a.out machine type. Default to 68020. */
3545int m68k_aout_machtype = 2;
3546#endif
3547
3548void
3549md_assemble (str)
3550 char *str;
3551{
3552 const char *er;
3553 short *fromP;
3554 char *toP = NULL;
3555 int m, n = 0;
3556 char *to_beg_P;
3557 int shorts_this_frag;
3558 fixS *fixP;
3559
3560 /* In MRI mode, the instruction and operands are separated by a
3561 space. Anything following the operands is a comment. The label
3562 has already been removed. */
3563 if (flag_mri)
3564 {
3565 char *s;
3566 int fields = 0;
3567 int infield = 0;
3568 int inquote = 0;
3569
3570 for (s = str; *s != '\0'; s++)
3571 {
3572 if ((*s == ' ' || *s == '\t') && ! inquote)
3573 {
3574 if (infield)
3575 {
3576 ++fields;
3577 if (fields >= 2)
3578 {
3579 *s = '\0';
3580 break;
3581 }
3582 infield = 0;
3583 }
3584 }
3585 else
3586 {
3587 if (! infield)
3588 infield = 1;
3589 if (*s == '\'')
3590 inquote = ! inquote;
3591 }
3592 }
3593 }
3594
3595 memset ((char *) (&the_ins), '\0', sizeof (the_ins));
3596 m68k_ip (str);
3597 er = the_ins.error;
3598 if (!er)
3599 {
3600 for (n = 0; n < the_ins.numargs; n++)
3601 if (the_ins.operands[n].error)
3602 {
3603 er = the_ins.operands[n].error;
3604 break;
3605 }
3606 }
3607 if (er)
3608 {
3609 as_bad (_("%s -- statement `%s' ignored"), er, str);
3610 return;
3611 }
3612
3613 /* If there is a current label, record that it marks an instruction. */
3614 if (current_label != NULL)
3615 {
3616 current_label->text = 1;
3617 current_label = NULL;
3618 }
3619
3620 if (the_ins.nfrag == 0)
3621 {
3622 /* No frag hacking involved; just put it out */
3623 toP = frag_more (2 * the_ins.numo);
3624 fromP = &the_ins.opcode[0];
3625 for (m = the_ins.numo; m; --m)
3626 {
3627 md_number_to_chars (toP, (long) (*fromP), 2);
3628 toP += 2;
3629 fromP++;
3630 }
3631 /* put out symbol-dependent info */
3632 for (m = 0; m < the_ins.nrel; m++)
3633 {
3634 switch (the_ins.reloc[m].wid)
3635 {
3636 case 'B':
3637 n = 1;
3638 break;
3639 case 'b':
3640 n = 1;
3641 break;
3642 case '3':
3643 n = 1;
3644 break;
3645 case 'w':
3646 case 'W':
3647 n = 2;
3648 break;
3649 case 'l':
3650 n = 4;
3651 break;
3652 default:
3653 as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
3654 the_ins.reloc[m].wid);
3655 }
3656
3657 fixP = fix_new_exp (frag_now,
3658 ((toP - frag_now->fr_literal)
3659 - the_ins.numo * 2 + the_ins.reloc[m].n),
3660 n,
3661 &the_ins.reloc[m].exp,
3662 the_ins.reloc[m].pcrel,
3663 get_reloc_code (n, the_ins.reloc[m].pcrel,
3664 the_ins.reloc[m].pic_reloc));
3665 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3666 if (the_ins.reloc[m].wid == 'B')
3667 fixP->fx_signed = 1;
3668 }
3669 return;
3670 }
3671
3672 /* There's some frag hacking */
3673 for (n = 0, fromP = &the_ins.opcode[0]; n < the_ins.nfrag; n++)
3674 {
3675 int wid;
3676
3677 if (n == 0)
3678 wid = 2 * the_ins.fragb[n].fragoff;
3679 else
3680 wid = 2 * (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3681 toP = frag_more (wid);
3682 to_beg_P = toP;
3683 shorts_this_frag = 0;
3684 for (m = wid / 2; m; --m)
3685 {
3686 md_number_to_chars (toP, (long) (*fromP), 2);
3687 toP += 2;
3688 fromP++;
3689 shorts_this_frag++;
3690 }
3691 for (m = 0; m < the_ins.nrel; m++)
3692 {
3693 if ((the_ins.reloc[m].n) >= 2 * shorts_this_frag)
3694 {
3695 the_ins.reloc[m].n -= 2 * shorts_this_frag;
3696 break;
3697 }
3698 wid = the_ins.reloc[m].wid;
3699 if (wid == 0)
3700 continue;
3701 the_ins.reloc[m].wid = 0;
3702 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3703
3704 fixP = fix_new_exp (frag_now,
3705 ((toP - frag_now->fr_literal)
3706 - the_ins.numo * 2 + the_ins.reloc[m].n),
3707 wid,
3708 &the_ins.reloc[m].exp,
3709 the_ins.reloc[m].pcrel,
3710 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3711 the_ins.reloc[m].pic_reloc));
3712 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3713 }
3714 (void) frag_var (rs_machine_dependent, 10, 0,
3715 (relax_substateT) (the_ins.fragb[n].fragty),
3716 the_ins.fragb[n].fadd, the_ins.fragb[n].foff, to_beg_P);
3717 }
3718 n = (the_ins.numo - the_ins.fragb[n - 1].fragoff);
3719 shorts_this_frag = 0;
3720 if (n)
3721 {
3722 toP = frag_more (n * sizeof (short));
3723 while (n--)
3724 {
3725 md_number_to_chars (toP, (long) (*fromP), 2);
3726 toP += 2;
3727 fromP++;
3728 shorts_this_frag++;
3729 }
3730 }
3731 for (m = 0; m < the_ins.nrel; m++)
3732 {
3733 int wid;
3734
3735 wid = the_ins.reloc[m].wid;
3736 if (wid == 0)
3737 continue;
3738 the_ins.reloc[m].wid = 0;
3739 wid = (wid == 'b') ? 1 : (wid == 'w') ? 2 : (wid == 'l') ? 4 : 4000;
3740
3741 fixP = fix_new_exp (frag_now,
3742 ((the_ins.reloc[m].n + toP - frag_now->fr_literal)
3743 - shorts_this_frag * 2),
3744 wid,
3745 &the_ins.reloc[m].exp,
3746 the_ins.reloc[m].pcrel,
3747 get_reloc_code (wid, the_ins.reloc[m].pcrel,
3748 the_ins.reloc[m].pic_reloc));
3749 fixP->fx_pcrel_adjust = the_ins.reloc[m].pcrel_fix;
3750 }
3751}
3752
3753void
3754md_begin ()
3755{
3756 /*
3757 * md_begin -- set up hash tables with 68000 instructions.
3758 * similar to what the vax assembler does. ---phr
3759 */
3760 /* RMS claims the thing to do is take the m68k-opcode.h table, and make
3761 a copy of it at runtime, adding in the information we want but isn't
3762 there. I think it'd be better to have an awk script hack the table
3763 at compile time. Or even just xstr the table and use it as-is. But
3764 my lord ghod hath spoken, so we do it this way. Excuse the ugly var
3765 names. */
3766
3767 register const struct m68k_opcode *ins;
3768 register struct m68k_incant *hack, *slak;
3769 register const char *retval = 0; /* empty string, or error msg text */
8fce3f5e 3770 register int i;
252b5132
RH		 3771 register char c;
3772
3773 if (flag_mri)
3774 {
3775 flag_reg_prefix_optional = 1;
3776 m68k_abspcadd = 1;
3777 if (! m68k_rel32_from_cmdline)
3778 m68k_rel32 = 0;
3779 }
3780
3781 op_hash = hash_new ();
3782
3783 obstack_begin (&robyn, 4000);
3784 for (i = 0; i < m68k_numopcodes; i++)
3785 {
3786 hack = slak = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3787 do
3788 {
3789 ins = &m68k_opcodes[i];
3790 /* We *could* ignore insns that don't match our arch here
92774660 3791 but just leaving them out of the hash. */
252b5132
RH		 3792 slak->m_operands = ins->args;
3793 slak->m_opnum = strlen (slak->m_operands) / 2;
3794 slak->m_arch = ins->arch;
3795 slak->m_opcode = ins->opcode;
3796 /* This is kludgey */
3797 slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1;
3798 if (i + 1 != m68k_numopcodes
3799 && !strcmp (ins->name, m68k_opcodes[i + 1].name))
3800 {
3801 slak->m_next = (struct m68k_incant *) obstack_alloc (&robyn, sizeof (struct m68k_incant));
3802 i++;
3803 }
3804 else
3805 slak->m_next = 0;
3806 slak = slak->m_next;
3807 }
3808 while (slak);
3809
3810 retval = hash_insert (op_hash, ins->name, (char *) hack);
3811 if (retval)
3812 as_fatal (_("Internal Error: Can't hash %s: %s"), ins->name, retval);
3813 }
3814
3815 for (i = 0; i < m68k_numaliases; i++)
3816 {
3817 const char *name = m68k_opcode_aliases[i].primary;
3818 const char *alias = m68k_opcode_aliases[i].alias;
3819 PTR val = hash_find (op_hash, name);
3820 if (!val)
3821 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3822 retval = hash_insert (op_hash, alias, val);
3823 if (retval)
3824 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3825 }
3826
3827 /* In MRI mode, all unsized branches are variable sized. Normally,
3828 they are word sized. */
3829 if (flag_mri)
3830 {
3831 static struct m68k_opcode_alias mri_aliases[] =
3832 {
3833 { "bhi", "jhi", },
3834 { "bls", "jls", },
3835 { "bcc", "jcc", },
3836 { "bcs", "jcs", },
3837 { "bne", "jne", },
3838 { "beq", "jeq", },
3839 { "bvc", "jvc", },
3840 { "bvs", "jvs", },
3841 { "bpl", "jpl", },
3842 { "bmi", "jmi", },
3843 { "bge", "jge", },
3844 { "blt", "jlt", },
3845 { "bgt", "jgt", },
3846 { "ble", "jle", },
3847 { "bra", "jra", },
3848 { "bsr", "jbsr", },
3849 };
3850
8fce3f5e
AM		 3851 for (i = 0;
3852 i < (int) (sizeof mri_aliases / sizeof mri_aliases[0]);
3853 i++)
252b5132
RH		 3854 {
3855 const char *name = mri_aliases[i].primary;
3856 const char *alias = mri_aliases[i].alias;
3857 PTR val = hash_find (op_hash, name);
3858 if (!val)
3859 as_fatal (_("Internal Error: Can't find %s in hash table"), name);
3860 retval = hash_jam (op_hash, alias, val);
3861 if (retval)
3862 as_fatal (_("Internal Error: Can't hash %s: %s"), alias, retval);
3863 }
3864 }
3865
8fce3f5e 3866 for (i = 0; i < (int) sizeof (mklower_table); i++)
252b5132
RH		 3867 mklower_table[i] = (isupper (c = (char) i)) ? tolower (c) : c;
3868
8fce3f5e 3869 for (i = 0; i < (int) sizeof (notend_table); i++)
252b5132
RH		 3870 {
3871 notend_table[i] = 0;
3872 alt_notend_table[i] = 0;
3873 }
3874 notend_table[','] = 1;
3875 notend_table['{'] = 1;
3876 notend_table['}'] = 1;
3877 alt_notend_table['a'] = 1;
3878 alt_notend_table['A'] = 1;
3879 alt_notend_table['d'] = 1;
3880 alt_notend_table['D'] = 1;
3881 alt_notend_table['#'] = 1;
3882 alt_notend_table['&'] = 1;
3883 alt_notend_table['f'] = 1;
3884 alt_notend_table['F'] = 1;
3885#ifdef REGISTER_PREFIX
3886 alt_notend_table[REGISTER_PREFIX] = 1;
3887#endif
3888
3889 /* We need to put '(' in alt_notend_table to handle
3890 cas2 %d0:%d2,%d3:%d4,(%a0):(%a1)
3891 */
3892 alt_notend_table['('] = 1;
3893
3894 /* We need to put '@' in alt_notend_table to handle
3895 cas2 %d0:%d2,%d3:%d4,@(%d0):@(%d1)
3896 */
3897 alt_notend_table['@'] = 1;
3898
3899 /* We need to put digits in alt_notend_table to handle
3900 bfextu %d0{24:1},%d0
3901 */
3902 alt_notend_table['0'] = 1;
3903 alt_notend_table['1'] = 1;
3904 alt_notend_table['2'] = 1;
3905 alt_notend_table['3'] = 1;
3906 alt_notend_table['4'] = 1;
3907 alt_notend_table['5'] = 1;
3908 alt_notend_table['6'] = 1;
3909 alt_notend_table['7'] = 1;
3910 alt_notend_table['8'] = 1;
3911 alt_notend_table['9'] = 1;
3912
3913#ifndef MIT_SYNTAX_ONLY
3914 /* Insert pseudo ops, these have to go into the opcode table since
3915 gas expects pseudo ops to start with a dot */
3916 {
3917 int n = 0;
3918 while (mote_pseudo_table[n].poc_name)
3919 {
3920 hack = (struct m68k_incant *)
3921 obstack_alloc (&robyn, sizeof (struct m68k_incant));
3922 hash_insert (op_hash,
3923 mote_pseudo_table[n].poc_name, (char *) hack);
3924 hack->m_operands = 0;
3925 hack->m_opnum = n;
3926 n++;
3927 }
3928 }
3929#endif
3930
3931 init_regtable ();
3932
3933#ifdef OBJ_ELF
3934 record_alignment (text_section, 2);
3935 record_alignment (data_section, 2);
3936 record_alignment (bss_section, 2);
3937#endif
3938}
3939
3940static void
3941select_control_regs ()
3942{
3943 /* Note which set of "movec" control registers is available. */
3944 switch (cpu_of_arch (current_architecture))
3945 {
3946 case m68000:
3947 control_regs = m68000_control_regs;
3948 break;
3949 case m68010:
3950 control_regs = m68010_control_regs;
3951 break;
3952 case m68020:
3953 case m68030:
3954 control_regs = m68020_control_regs;
3955 break;
3956 case m68040:
3957 control_regs = m68040_control_regs;
3958 break;
3959 case m68060:
3960 control_regs = m68060_control_regs;
3961 break;
3962 case cpu32:
3963 control_regs = cpu32_control_regs;
3964 break;
3965 case mcf5200:
6da466c7
ILT		 3966 case mcf5206e:
3967 case mcf5307:
3968 control_regs = mcf_control_regs;
252b5132
RH		 3969 break;
3970 default:
3971 abort ();
3972 }
3973}
3974
3975void
3976m68k_init_after_args ()
3977{
3978 if (cpu_of_arch (current_architecture) == 0)
3979 {
3980 int i;
3981 const char *default_cpu = TARGET_CPU;
3982
3983 if (*default_cpu == 'm')
3984 default_cpu++;
3985 for (i = 0; i < n_archs; i++)
3986 if (strcasecmp (default_cpu, archs[i].name) == 0)
3987 break;
3988 if (i == n_archs)
3989 {
3990 as_bad (_("unrecognized default cpu `%s' ???"), TARGET_CPU);
3991 current_architecture |= m68020;
3992 }
3993 else
3994 current_architecture |= archs[i].arch;
3995 }
3996 /* Permit m68881 specification with all cpus; those that can't work
3997 with a coprocessor could be doing emulation. */
3998 if (current_architecture & m68851)
3999 {
4000 if (current_architecture & m68040)
4001 {
4002 as_warn (_("68040 and 68851 specified; mmu instructions may assemble incorrectly"));
4003 }
4004 }
4005 /* What other incompatibilities could we check for? */
4006
4007 /* Toss in some default assumptions about coprocessors. */
4008 if (!no_68881
4009 && (cpu_of_arch (current_architecture)
4010 /* Can CPU32 have a 68881 coprocessor?? */
4011 & (m68020 | m68030 | cpu32)))
4012 {
4013 current_architecture |= m68881;
4014 }
4015 if (!no_68851
4016 && (cpu_of_arch (current_architecture) & m68020up) != 0
4017 && (cpu_of_arch (current_architecture) & m68040up) == 0)
4018 {
4019 current_architecture |= m68851;
4020 }
4021 if (no_68881 && (current_architecture & m68881))
4022 as_bad (_("options for 68881 and no-68881 both given"));
4023 if (no_68851 && (current_architecture & m68851))
4024 as_bad (_("options for 68851 and no-68851 both given"));
4025
4026#ifdef OBJ_AOUT
4027 /* Work out the magic number. This isn't very general. */
4028 if (current_architecture & m68000)
4029 m68k_aout_machtype = 0;
4030 else if (current_architecture & m68010)
4031 m68k_aout_machtype = 1;
4032 else if (current_architecture & m68020)
4033 m68k_aout_machtype = 2;
4034 else
4035 m68k_aout_machtype = 2;
4036#endif
4037
4038 /* Note which set of "movec" control registers is available. */
4039 select_control_regs ();
4040
4041 if (cpu_of_arch (current_architecture) < m68020
6da466c7 4042 || arch_coldfire_p (current_architecture))
252b5132
RH		 4043 md_relax_table[TAB (PCINDEX, BYTE)].rlx_more = 0;
4044}
4045\f
4046/* This is called when a label is defined. */
4047
4048void
4049m68k_frob_label (sym)
4050 symbolS *sym;
4051{
4052 struct label_line *n;
4053
4054 n = (struct label_line *) xmalloc (sizeof *n);
4055 n->next = labels;
4056 n->label = sym;
4057 as_where (&n->file, &n->line);
4058 n->text = 0;
4059 labels = n;
4060 current_label = n;
4061}
4062
4063/* This is called when a value that is not an instruction is emitted. */
4064
4065void
4066m68k_flush_pending_output ()
4067{
4068 current_label = NULL;
4069}
4070
4071/* This is called at the end of the assembly, when the final value of
4072 the label is known. We warn if this is a text symbol aligned at an
4073 odd location. */
4074
4075void
4076m68k_frob_symbol (sym)
4077 symbolS *sym;
4078{
4079 if (S_GET_SEGMENT (sym) == reg_section
4080 && (int) S_GET_VALUE (sym) < 0)
4081 {
4082 S_SET_SEGMENT (sym, absolute_section);
4083 S_SET_VALUE (sym, ~(int)S_GET_VALUE (sym));
4084 }
4085 else if ((S_GET_VALUE (sym) & 1) != 0)
4086 {
4087 struct label_line *l;
4088
4089 for (l = labels; l != NULL; l = l->next)
4090 {
4091 if (l->label == sym)
4092 {
4093 if (l->text)
4094 as_warn_where (l->file, l->line,
4095 _("text label `%s' aligned to odd boundary"),
4096 S_GET_NAME (sym));
4097 break;
4098 }
4099 }
4100 }
4101}
4102\f
4103/* This is called if we go in or out of MRI mode because of the .mri
4104 pseudo-op. */
4105
4106void
4107m68k_mri_mode_change (on)
4108 int on;
4109{
4110 if (on)
4111 {
4112 if (! flag_reg_prefix_optional)
4113 {
4114 flag_reg_prefix_optional = 1;
4115#ifdef REGISTER_PREFIX
4116 init_regtable ();
4117#endif
4118 }
4119 m68k_abspcadd = 1;
4120 if (! m68k_rel32_from_cmdline)
4121 m68k_rel32 = 0;
4122 }
4123 else
4124 {
4125 if (! reg_prefix_optional_seen)
4126 {
4127#ifdef REGISTER_PREFIX_OPTIONAL
4128 flag_reg_prefix_optional = REGISTER_PREFIX_OPTIONAL;
4129#else
4130 flag_reg_prefix_optional = 0;
4131#endif
4132#ifdef REGISTER_PREFIX
4133 init_regtable ();
4134#endif
4135 }
4136 m68k_abspcadd = 0;
4137 if (! m68k_rel32_from_cmdline)
4138 m68k_rel32 = 1;
4139 }
4140}
4141
4142/* Equal to MAX_PRECISION in atof-ieee.c */
4143#define MAX_LITTLENUMS 6
4144
4145/* Turn a string in input_line_pointer into a floating point constant
bc0d738a
NC		 4146 of type TYPE, and store the appropriate bytes in *LITP. The number
4147 of LITTLENUMS emitted is stored in *SIZEP. An error message is
252b5132
RH		 4148 returned, or NULL on OK. */
4149
4150char *
4151md_atof (type, litP, sizeP)
4152 char type;
4153 char *litP;
4154 int *sizeP;
4155{
4156 int prec;
4157 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4158 LITTLENUM_TYPE *wordP;
4159 char *t;
4160
4161 switch (type)
4162 {
4163 case 'f':
4164 case 'F':
4165 case 's':
4166 case 'S':
4167 prec = 2;
4168 break;
4169
4170 case 'd':
4171 case 'D':
4172 case 'r':
4173 case 'R':
4174 prec = 4;
4175 break;
4176
4177 case 'x':
4178 case 'X':
4179 prec = 6;
4180 break;
4181
4182 case 'p':
4183 case 'P':
4184 prec = 6;
4185 break;
4186
4187 default:
4188 *sizeP = 0;
4189 return _("Bad call to MD_ATOF()");
4190 }
4191 t = atof_ieee (input_line_pointer, type, words);
4192 if (t)
4193 input_line_pointer = t;
4194
4195 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4196 for (wordP = words; prec--;)
4197 {
4198 md_number_to_chars (litP, (long) (*wordP++), sizeof (LITTLENUM_TYPE));
4199 litP += sizeof (LITTLENUM_TYPE);
4200 }
4201 return 0;
4202}
4203
4204void
4205md_number_to_chars (buf, val, n)
4206 char *buf;
4207 valueT val;
4208 int n;
4209{
4210 number_to_chars_bigendian (buf, val, n);
4211}
4212
4213static void
4214md_apply_fix_2 (fixP, val)
4215 fixS *fixP;
4216 offsetT val;
4217{
4218 addressT upper_limit;
4219 offsetT lower_limit;
4220
4221 /* This is unnecessary but it convinces the native rs6000 compiler
4222 to generate the code we want. */
4223 char *buf = fixP->fx_frag->fr_literal;
4224 buf += fixP->fx_where;
4225 /* end ibm compiler workaround */
4226
4227 if (val & 0x80000000)
4228 val |= ~(addressT)0x7fffffff;
4229 else
4230 val &= 0x7fffffff;
4231
4232#ifdef OBJ_ELF
4233 if (fixP->fx_addsy)
4234 {
4235 memset (buf, 0, fixP->fx_size);
4236 fixP->fx_addnumber = val; /* Remember value for emit_reloc */
4237
4238 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4239 && !S_IS_DEFINED (fixP->fx_addsy)
4240 && !S_IS_WEAK (fixP->fx_addsy))
4241 S_SET_WEAK (fixP->fx_addsy);
4242 return;
4243 }
4244#endif
4245
4246#ifdef BFD_ASSEMBLER
4247 if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
4248 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
4249 return;
4250#endif
4251
4252 switch (fixP->fx_size)
4253 {
4254 /* The cast to offsetT below are necessary to make code correct for
4255 machines where ints are smaller than offsetT */
4256 case 1:
4257 *buf++ = val;
4258 upper_limit = 0x7f;
4259 lower_limit = - (offsetT) 0x80;
4260 break;
4261 case 2:
4262 *buf++ = (val >> 8);
4263 *buf++ = val;
4264 upper_limit = 0x7fff;
4265 lower_limit = - (offsetT) 0x8000;
4266 break;
4267 case 4:
4268 *buf++ = (val >> 24);
4269 *buf++ = (val >> 16);
4270 *buf++ = (val >> 8);
4271 *buf++ = val;
4272 upper_limit = 0x7fffffff;
4273 lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */
4274 break;
4275 default:
4276 BAD_CASE (fixP->fx_size);
4277 }
4278
4279 /* Fix up a negative reloc. */
4280 if (fixP->fx_addsy == NULL && fixP->fx_subsy != NULL)
4281 {
4282 fixP->fx_addsy = fixP->fx_subsy;
4283 fixP->fx_subsy = NULL;
4284 fixP->fx_tcbit = 1;
4285 }
4286
4287 /* For non-pc-relative values, it's conceivable we might get something
4288 like "0xff" for a byte field. So extend the upper part of the range
4289 to accept such numbers. We arbitrarily disallow "-0xff" or "0xff+0xff",
4290 so that we can do any range checking at all. */
4291 if (! fixP->fx_pcrel && ! fixP->fx_signed)
4292 upper_limit = upper_limit * 2 + 1;
4293
4294 if ((addressT) val > upper_limit
4295 && (val > 0 || val < lower_limit))
4296 as_bad_where (fixP->fx_file, fixP->fx_line, _("value out of range"));
4297
4298 /* A one byte PC-relative reloc means a short branch. We can't use
4299 a short branch with a value of 0 or -1, because those indicate
4300 different opcodes (branches with longer offsets). fixup_segment
4301 in write.c may have clobbered fx_pcrel, so we need to examine the
4302 reloc type. */
4303 if ((fixP->fx_pcrel
4304#ifdef BFD_ASSEMBLER
4305 || fixP->fx_r_type == BFD_RELOC_8_PCREL
4306#endif
4307 )
4308 && fixP->fx_size == 1
4309 && (fixP->fx_addsy == NULL
4310 || S_IS_DEFINED (fixP->fx_addsy))
4311 && (val == 0 || val == -1))
4312 as_bad_where (fixP->fx_file, fixP->fx_line, _("invalid byte branch offset"));
4313}
4314
4315#ifdef BFD_ASSEMBLER
4316int
4317md_apply_fix (fixP, valp)
4318 fixS *fixP;
4319 valueT *valp;
4320{
4321 md_apply_fix_2 (fixP, (addressT) *valp);
4322 return 1;
4323}
4324#else
4325void md_apply_fix (fixP, val)
4326 fixS *fixP;
4327 long val;
4328{
4329 md_apply_fix_2 (fixP, (addressT) val);
4330}
4331#endif
4332
4333/* *fragP has been relaxed to its final size, and now needs to have
4334 the bytes inside it modified to conform to the new size There is UGLY
4335 MAGIC here. ..
4336 */
4337static void
4338md_convert_frag_1 (fragP)
4339 register fragS *fragP;
4340{
4341 long disp;
252b5132
RH		 4342 fixS *fixP;
4343
4344 /* Address in object code of the displacement. */
4345 register int object_address = fragP->fr_fix + fragP->fr_address;
4346
4347 /* Address in gas core of the place to store the displacement. */
4348 /* This convinces the native rs6000 compiler to generate the code we
92774660 4349 want. */
252b5132
RH		 4350 register char *buffer_address = fragP->fr_literal;
4351 buffer_address += fragP->fr_fix;
4352 /* end ibm compiler workaround */
4353
4354 /* The displacement of the address, from current location. */
4355 disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0;
4356 disp = (disp + fragP->fr_offset) - object_address;
4357
4358#ifdef BFD_ASSEMBLER
49309057 4359 disp += symbol_get_frag (fragP->fr_symbol)->fr_address;
252b5132
RH		 4360#endif
4361
4362 switch (fragP->fr_subtype)
4363 {
151337e8
NC		 4364 case TAB (BRANCHBWL, BYTE):
4365 case TAB (BRABSJUNC, BYTE):
4366 case TAB (BRABSJCOND, BYTE):
4367 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4368 know (issbyte (disp));
4369 if (disp == 0)
4370 as_bad (_("short branch with zero offset: use :w"));
151337e8 4371 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4372 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4373 fixP->fx_pcrel_adjust = -1;
252b5132 4374 break;
151337e8
NC		 4375 case TAB (BRANCHBWL, SHORT):
4376 case TAB (BRABSJUNC, SHORT):
4377 case TAB (BRABSJCOND, SHORT):
4378 case TAB (BRANCHBW, SHORT):
252b5132 4379 fragP->fr_opcode[1] = 0x00;
151337e8 4380 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4381 1, RELAX_RELOC_PC16);
151337e8
NC		 4382 fragP->fr_fix += 2;
4383 break;
4384 case TAB (BRANCHBWL, LONG):
4385 fragP->fr_opcode[1] = (char) 0xFF;
4386 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4387 1, RELAX_RELOC_PC32);
151337e8 4388 fragP->fr_fix += 4;
252b5132 4389 break;
151337e8
NC		 4390 case TAB (BRABSJUNC, LONG):
4391 if (fragP->fr_opcode[0] == 0x61) /* jbsr */
252b5132 4392 {
151337e8
NC		 4393 fragP->fr_opcode[0] = 0x4E;
4394 fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */
4395 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
3ae647a0 4396 0, RELAX_RELOC_ABS32);
151337e8
NC		 4397 fragP->fr_fix += 4;
4398 }
4399 else if (fragP->fr_opcode[0] == 0x60) /* jbra */
4400 {
4401 fragP->fr_opcode[0] = 0x4E;
4402 fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */
4403 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4404 0, RELAX_RELOC_ABS32);
151337e8 4405 fragP->fr_fix += 4;
252b5132
RH		 4406 }
4407 else
4408 {
151337e8
NC		 4409 /* This cannot happen, because jbsr and jbra are the only two
4410 unconditional branches. */
4411 abort ();
252b5132
RH		 4412 }
4413 break;
151337e8
NC		 4414 case TAB (BRABSJCOND, LONG):
4415 /* Only Bcc 68000 instructions can come here. */
4416 /* Change bcc into b!cc/jmp absl long. */
92774660 4417
252b5132
RH		 4418 fragP->fr_opcode[0] ^= 0x01; /* invert bcc */
4419 fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */
4420
4421 /* JF: these used to be fr_opcode[2,3], but they may be in a
4422 different frag, in which case refering to them is a no-no.
92774660 4423 Only fr_opcode[0,1] are guaranteed to work. */
252b5132
RH		 4424 *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
4425 *buffer_address++ = (char) 0xf9;
4426 fragP->fr_fix += 2; /* account for jmp instruction */
4427 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol,
5cbdaa77 4428 fragP->fr_offset, 0, RELAX_RELOC_ABS32);
151337e8
NC		 4429 fragP->fr_fix += 4;
4430 break;
4431 case TAB (FBRANCH, SHORT):
4432 know ((fragP->fr_opcode[1] & 0x40) == 0);
4433 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4434 1, RELAX_RELOC_PC16);
151337e8
NC		 4435 fragP->fr_fix += 2;
4436 break;
4437 case TAB (FBRANCH, LONG):
4438 fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */
4439 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4440 1, RELAX_RELOC_PC32);
252b5132 4441 fragP->fr_fix += 4;
252b5132 4442 break;
151337e8
NC		 4443 case TAB (DBCCLBR, SHORT):
4444 case TAB (DBCCABSJ, SHORT):
4445 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4446 1, RELAX_RELOC_PC16);
151337e8
NC		 4447 fragP->fr_fix += 2;
4448 break;
4449 case TAB (DBCCLBR, LONG):
4450 /* only DBcc instructions can come here */
28e7409f 4451 /* Change dbcc into dbcc/bral. */
28e7409f 4452
252b5132
RH		 4453 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4454 *buffer_address++ = 0x00; /* branch offset = 4 */
4455 *buffer_address++ = 0x04;
4456 *buffer_address++ = 0x60; /* put in bra pc+6 */
4457 *buffer_address++ = 0x06;
151337e8
NC		 4458 *buffer_address++ = 0x60; /* Put in bral (0x60ff). */
4459 *buffer_address++ = (char) 0xff;
252b5132
RH		 4460
4461 fragP->fr_fix += 6; /* account for bra/jmp instructions */
151337e8 4462 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1,
5cbdaa77 4463 RELAX_RELOC_PC32);
252b5132 4464 fragP->fr_fix += 4;
252b5132 4465 break;
151337e8
NC		 4466 case TAB (DBCCABSJ, LONG):
4467 /* only DBcc instructions can come here */
4468 /* Change dbcc into dbcc/jmp. */
4469
4470 /* JF: these used to be fr_opcode[2-7], but that's wrong */
4471 *buffer_address++ = 0x00; /* branch offset = 4 */
4472 *buffer_address++ = 0x04;
4473 *buffer_address++ = 0x60; /* put in bra pc+6 */
4474 *buffer_address++ = 0x06;
4475 *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */
4476 *buffer_address++ = (char) 0xf9;
4477
4478 fragP->fr_fix += 6; /* account for bra/jmp instructions */
4479 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0,
5cbdaa77 4480 RELAX_RELOC_ABS32);
252b5132 4481 fragP->fr_fix += 4;
252b5132 4482 break;
151337e8 4483 case TAB (PCREL1632, SHORT):
252b5132
RH		 4484 fragP->fr_opcode[1] &= ~0x3F;
4485 fragP->fr_opcode[1] |= 0x3A; /* 072 - mode 7.2 */
151337e8 4486 fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4487 fragP->fr_offset, 1, RELAX_RELOC_PC16);
151337e8 4488 fragP->fr_fix += 2;
252b5132 4489 break;
151337e8 4490 case TAB (PCREL1632, LONG):
252b5132
RH		 4491 /* Already set to mode 7.3; this indicates: PC indirect with
4492 suppressed index, 32-bit displacement. */
4493 *buffer_address++ = 0x01;
4494 *buffer_address++ = 0x70;
4495 fragP->fr_fix += 2;
151337e8 4496 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4497 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4498 fixP->fx_pcrel_adjust = 2;
4499 fragP->fr_fix += 4;
252b5132 4500 break;
252b5132 4501 case TAB (PCINDEX, BYTE):
252b5132
RH		 4502 assert (fragP->fr_fix >= 2);
4503 buffer_address[-2] &= ~1;
151337e8 4504 fixP = fix_new (fragP, fragP->fr_fix - 1, 1, fragP->fr_symbol,
5cbdaa77 4505 fragP->fr_offset, 1, RELAX_RELOC_PC8);
151337e8 4506 fixP->fx_pcrel_adjust = 1;
252b5132
RH		 4507 break;
4508 case TAB (PCINDEX, SHORT):
252b5132
RH		 4509 assert (fragP->fr_fix >= 2);
4510 buffer_address[-2] |= 0x1;
4511 buffer_address[-1] = 0x20;
4512 fixP = fix_new (fragP, (int) (fragP->fr_fix), 2, fragP->fr_symbol,
5cbdaa77 4513 fragP->fr_offset, 1, RELAX_RELOC_PC16);
252b5132 4514 fixP->fx_pcrel_adjust = 2;
151337e8 4515 fragP->fr_fix += 2;
252b5132
RH		 4516 break;
4517 case TAB (PCINDEX, LONG):
252b5132
RH		 4518 assert (fragP->fr_fix >= 2);
4519 buffer_address[-2] |= 0x1;
4520 buffer_address[-1] = 0x30;
151337e8 4521 fixP = fix_new (fragP, (int) (fragP->fr_fix), 4, fragP->fr_symbol,
5cbdaa77 4522 fragP->fr_offset, 1, RELAX_RELOC_PC32);
151337e8
NC		 4523 fixP->fx_pcrel_adjust = 2;
4524 fragP->fr_fix += 4;
4525 break;
4526 case TAB (ABSTOPCREL, SHORT):
4527 fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4528 1, RELAX_RELOC_PC16);
151337e8
NC		 4529 fragP->fr_fix += 2;
4530 break;
4531 case TAB (ABSTOPCREL, LONG):
4532 /* The thing to do here is force it to ABSOLUTE LONG, since
4533 ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */
4534 if ((fragP->fr_opcode[1] & 0x3F) != 0x3A)
4535 abort ();
4536 fragP->fr_opcode[1] &= ~0x3F;
4537 fragP->fr_opcode[1] |= 0x39; /* Mode 7.1 */
4538 fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset,
5cbdaa77 4539 0, RELAX_RELOC_ABS32);
151337e8 4540 fragP->fr_fix += 4;
252b5132 4541 break;
252b5132
RH		 4542 }
4543}
4544
4545#ifndef BFD_ASSEMBLER
4546
4547void
4548md_convert_frag (headers, sec, fragP)
8fce3f5e
AM		 4549 object_headers *headers ATTRIBUTE_UNUSED;
4550 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4551 fragS *fragP;
4552{
4553 md_convert_frag_1 (fragP);
4554}
4555
4556#else
4557
4558void
4559md_convert_frag (abfd, sec, fragP)
36823076
AS		 4560 bfd *abfd ATTRIBUTE_UNUSED;
4561 segT sec ATTRIBUTE_UNUSED;
252b5132
RH		 4562 fragS *fragP;
4563{
4564 md_convert_frag_1 (fragP);
4565}
4566#endif
4567
4568/* Force truly undefined symbols to their maximum size, and generally set up
4569 the frag list to be relaxed
4570 */
4571int
4572md_estimate_size_before_relax (fragP, segment)
4573 register fragS *fragP;
4574 segT segment;
4575{
4576 int old_fix;
252b5132
RH		 4577
4578 old_fix = fragP->fr_fix;
4579
151337e8 4580 /* Handle SZ_UNDEF first, it can be changed to BYTE or SHORT. */
252b5132
RH		 4581 switch (fragP->fr_subtype)
4582 {
151337e8
NC		 4583 case TAB (BRANCHBWL, SZ_UNDEF):
4584 case TAB (BRABSJUNC, SZ_UNDEF):
252b5132 4585 {
151337e8 4586 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
252b5132
RH		 4587 && relaxable_symbol (fragP->fr_symbol))
4588 {
4589 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
8fce3f5e 4590 }
151337e8 4591 else if (flag_short_refs)
252b5132 4592 {
151337e8
NC		 4593 /* Symbol is undefined and we want short ref. */
4594 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4595 fragP->fr_var += 2;
252b5132
RH		 4596 }
4597 else
151337e8
NC		 4598 {
4599 /* Symbol is still undefined. Make it LONG. */
4600 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4601 fragP->fr_var += 4;
252b5132 4602 }
252b5132 4603 break;
151337e8 4604 }
252b5132 4605
151337e8 4606 case TAB (BRABSJCOND, SZ_UNDEF):
252b5132 4607 {
151337e8
NC		 4608 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4609 && relaxable_symbol (fragP->fr_symbol))
252b5132 4610 {
151337e8
NC		 4611 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
4612 }
4613 else if (flag_short_refs)
4614 {
4615 /* Symbol is undefined and we want short ref. */
4616 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132
RH		 4617 fragP->fr_var += 2;
4618 }
4619 else
4620 {
151337e8
NC		 4621 /* Symbol is still undefined. Make it LONG. */
4622 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4623 fragP->fr_var += 6;
252b5132
RH		 4624 }
4625 break;
151337e8 4626 }
252b5132 4627
151337e8 4628 case TAB (BRANCHBW, SZ_UNDEF):
252b5132 4629 {
151337e8
NC		 4630 if (S_GET_SEGMENT (fragP->fr_symbol) == segment
4631 && relaxable_symbol (fragP->fr_symbol))
252b5132 4632 {
151337e8 4633 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), BYTE);
252b5132
RH		 4634 }
4635 else
4636 {
151337e8
NC		 4637 /* Symbol is undefined and we don't have long branches. */
4638 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4639 fragP->fr_var += 2;
252b5132
RH		 4640 }
4641 break;
151337e8 4642 }
252b5132 4643
151337e8 4644 case TAB (FBRANCH, SZ_UNDEF):
252b5132 4645 {
151337e8
NC		 4646 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4647 && relaxable_symbol (fragP->fr_symbol))
4648 || flag_short_refs)
252b5132 4649 {
151337e8
NC		 4650 fragP->fr_subtype = TAB (FBRANCH, SHORT);
4651 fragP->fr_var += 2;
252b5132
RH		 4652 }
4653 else
4654 {
151337e8
NC		 4655 fragP->fr_subtype = TAB (FBRANCH, LONG);
4656 fragP->fr_var += 4;
252b5132 4657 }
252b5132 4658 break;
151337e8 4659 }
252b5132 4660
151337e8
NC		 4661 case TAB (DBCCLBR, SZ_UNDEF):
4662 case TAB (DBCCABSJ, SZ_UNDEF):
252b5132 4663 {
8ec6253e
NC		 4664 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4665 && relaxable_symbol (fragP->fr_symbol))
151337e8 4666 || flag_short_refs)
252b5132 4667 {
151337e8 4668 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
252b5132 4669 fragP->fr_var += 2;
252b5132
RH		 4670 }
4671 else
4672 {
151337e8
NC		 4673 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), LONG);
4674 fragP->fr_var += 10;
252b5132 4675 }
252b5132 4676 break;
151337e8 4677 }
252b5132 4678
151337e8 4679 case TAB (PCREL1632, SZ_UNDEF):
252b5132
RH		 4680 {
4681 if (((S_GET_SEGMENT (fragP->fr_symbol)) == segment
4682 && relaxable_symbol (fragP->fr_symbol))
151337e8 4683 || flag_short_refs)
252b5132 4684 {
151337e8 4685 fragP->fr_subtype = TAB (PCREL1632, SHORT);
252b5132
RH		 4686 fragP->fr_var += 2;
4687 }
4688 else
4689 {
151337e8 4690 fragP->fr_subtype = TAB (PCREL1632, LONG);
252b5132
RH		 4691 fragP->fr_var += 6;
4692 }
4693 break;
151337e8 4694 }
81d4177b 4695
252b5132
RH		 4696 case TAB (PCINDEX, SZ_UNDEF):
4697 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
151337e8 4698 && relaxable_symbol (fragP->fr_symbol)))
252b5132
RH		 4699 {
4700 fragP->fr_subtype = TAB (PCINDEX, BYTE);
4701 }
4702 else
4703 {
4704 fragP->fr_subtype = TAB (PCINDEX, LONG);
4705 fragP->fr_var += 4;
4706 }
4707 break;
4708
151337e8
NC		 4709 case TAB (ABSTOPCREL, SZ_UNDEF):
4710 {
4711 if ((S_GET_SEGMENT (fragP->fr_symbol) == segment
4712 && relaxable_symbol (fragP->fr_symbol)))
4713 {
4714 fragP->fr_subtype = TAB (ABSTOPCREL, SHORT);
4715 fragP->fr_var += 2;
4716 }
4717 else
4718 {
4719 fragP->fr_subtype = TAB (ABSTOPCREL, LONG);
4720 fragP->fr_var += 4;
4721 }
4722 break;
4723 }
4724
252b5132
RH		 4725 default:
4726 break;
4727 }
4728
151337e8 4729 /* Now that SZ_UNDEF are taken care of, check others. */
252b5132
RH		 4730 switch (fragP->fr_subtype)
4731 {
151337e8
NC		 4732 case TAB (BRANCHBWL, BYTE):
4733 case TAB (BRABSJUNC, BYTE):
4734 case TAB (BRABSJCOND, BYTE):
4735 case TAB (BRANCHBW, BYTE):
252b5132
RH		 4736 /* We can't do a short jump to the next instruction, so in that
4737 case we force word mode. At this point S_GET_VALUE should
4738 return the offset of the symbol within its frag. If the
4739 symbol is at the start of a frag, and it is the next frag
4740 with any data in it (usually this is just the next frag, but
4741 assembler listings may introduce empty frags), we must use
4742 word mode. */
4743 if (fragP->fr_symbol && S_GET_VALUE (fragP->fr_symbol) == 0)
4744 {
49309057 4745 fragS *stop;
252b5132
RH		 4746 fragS *l;
4747
49309057
ILT		 4748 stop = symbol_get_frag (fragP->fr_symbol);
4749 for (l = fragP->fr_next; l != stop; l = l->fr_next)
252b5132
RH		 4750 if (l->fr_fix + l->fr_var != 0)
4751 break;
49309057 4752 if (l == stop)
252b5132
RH		 4753 {
4754 fragP->fr_subtype = TAB (TABTYPE (fragP->fr_subtype), SHORT);
4755 fragP->fr_var += 2;
4756 }
4757 }
4758 break;
4759 default:
4760 break;
4761 }
4762 return fragP->fr_var + fragP->fr_fix - old_fix;
4763}
4764
4765#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
4766/* the bit-field entries in the relocation_info struct plays hell
4767 with the byte-order problems of cross-assembly. So as a hack,
4768 I added this mach. dependent ri twiddler. Ugly, but it gets
4769 you there. -KWK */
4770/* on m68k: first 4 bytes are normal unsigned long, next three bytes
4771 are symbolnum, most sig. byte first. Last byte is broken up with
4772 bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower
4773 nibble as nuthin. (on Sun 3 at least) */
4774/* Translate the internal relocation information into target-specific
92774660 4775 format. */
252b5132
RH		 4776#ifdef comment
4777void
4778md_ri_to_chars (the_bytes, ri)
4779 char *the_bytes;
4780 struct reloc_info_generic *ri;
4781{
4782 /* this is easy */
4783 md_number_to_chars (the_bytes, ri->r_address, 4);
4784 /* now the fun stuff */
4785 the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff;
4786 the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff;
4787 the_bytes[6] = ri->r_symbolnum & 0x0ff;
4788 the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) |
4789 ((ri->r_extern << 4) & 0x10));
4790}
4791
4792#endif /* comment */
4793
4794#ifndef BFD_ASSEMBLER
4795void
4796tc_aout_fix_to_chars (where, fixP, segment_address_in_file)
4797 char *where;
4798 fixS *fixP;
4799 relax_addressT segment_address_in_file;
4800{
4801 /*
4802 * In: length of relocation (or of address) in chars: 1, 2 or 4.
4803 * Out: GNU LD relocation length code: 0, 1, or 2.
4804 */
4805
4806 static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
4807 long r_symbolnum;
4808
4809 know (fixP->fx_addsy != NULL);
4810
4811 md_number_to_chars (where,
4812 fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file,
4813 4);
4814
4815 r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy)
4816 ? S_GET_TYPE (fixP->fx_addsy)
4817 : fixP->fx_addsy->sy_number);
4818
4819 where[4] = (r_symbolnum >> 16) & 0x0ff;
4820 where[5] = (r_symbolnum >> 8) & 0x0ff;
4821 where[6] = r_symbolnum & 0x0ff;
4822 where[7] = (((fixP->fx_pcrel << 7) & 0x80) | ((nbytes_r_length[fixP->fx_size] << 5) & 0x60) |
4823 (((!S_IS_DEFINED (fixP->fx_addsy)) << 4) & 0x10));
4824}
4825#endif
4826
4827#endif /* OBJ_AOUT or OBJ_BOUT */
4828
4829#ifndef WORKING_DOT_WORD
4830CONST int md_short_jump_size = 4;
4831CONST int md_long_jump_size = 6;
4832
4833void
4834md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4835 char *ptr;
4836 addressT from_addr, to_addr;
36823076
AS		 4837 fragS *frag ATTRIBUTE_UNUSED;
4838 symbolS *to_symbol ATTRIBUTE_UNUSED;
252b5132
RH		 4839{
4840 valueT offset;
4841
4842 offset = to_addr - (from_addr + 2);
4843
4844 md_number_to_chars (ptr, (valueT) 0x6000, 2);
4845 md_number_to_chars (ptr + 2, (valueT) offset, 2);
4846}
4847
4848void
4849md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4850 char *ptr;
4851 addressT from_addr, to_addr;
4852 fragS *frag;
4853 symbolS *to_symbol;
4854{
4855 valueT offset;
4856
4857 if (!HAVE_LONG_BRANCH(current_architecture))
4858 {
4859 offset = to_addr - S_GET_VALUE (to_symbol);
4860 md_number_to_chars (ptr, (valueT) 0x4EF9, 2);
4861 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4862 fix_new (frag, (ptr + 2) - frag->fr_literal, 4, to_symbol, (offsetT) 0,
4863 0, NO_RELOC);
4864 }
4865 else
4866 {
4867 offset = to_addr - (from_addr + 2);
4868 md_number_to_chars (ptr, (valueT) 0x60ff, 2);
4869 md_number_to_chars (ptr + 2, (valueT) offset, 4);
4870 }
4871}
4872
4873#endif
4874
4875/* Different values of OK tell what its OK to return. Things that
4876 aren't OK are an error (what a shock, no?)
4877
4878 0: Everything is OK
4879 10: Absolute 1:8 only
4880 20: Absolute 0:7 only
4881 30: absolute 0:15 only
4882 40: Absolute 0:31 only
4883 50: absolute 0:127 only
4884 55: absolute -64:63 only
4885 60: absolute -128:127 only
4886 70: absolute 0:4095 only
4887 80: No bignums
4888
4889 */
4890
4891static int
4892get_num (exp, ok)
4893 struct m68k_exp *exp;
4894 int ok;
4895{
4896 if (exp->exp.X_op == O_absent)
4897 {
4898 /* Do the same thing the VAX asm does */
4899 op (exp) = O_constant;
4900 adds (exp) = 0;
4901 subs (exp) = 0;
4902 offs (exp) = 0;
4903 if (ok == 10)
4904 {
4905 as_warn (_("expression out of range: defaulting to 1"));
4906 offs (exp) = 1;
4907 }
4908 }
4909 else if (exp->exp.X_op == O_constant)
4910 {
4911 switch (ok)
4912 {
4913 case 10:
4914 if (offs (exp) < 1 || offs (exp) > 8)
4915 {
4916 as_warn (_("expression out of range: defaulting to 1"));
4917 offs (exp) = 1;
4918 }
4919 break;
4920 case 20:
4921 if (offs (exp) < 0 || offs (exp) > 7)
4922 goto outrange;
4923 break;
4924 case 30:
4925 if (offs (exp) < 0 || offs (exp) > 15)
4926 goto outrange;
4927 break;
4928 case 40:
4929 if (offs (exp) < 0 || offs (exp) > 32)
4930 goto outrange;
4931 break;
4932 case 50:
4933 if (offs (exp) < 0 || offs (exp) > 127)
4934 goto outrange;
4935 break;
4936 case 55:
4937 if (offs (exp) < -64 || offs (exp) > 63)
4938 goto outrange;
4939 break;
4940 case 60:
4941 if (offs (exp) < -128 || offs (exp) > 127)
4942 goto outrange;
4943 break;
4944 case 70:
4945 if (offs (exp) < 0 || offs (exp) > 4095)
4946 {
4947 outrange:
4948 as_warn (_("expression out of range: defaulting to 0"));
4949 offs (exp) = 0;
4950 }
4951 break;
4952 default:
4953 break;
4954 }
4955 }
4956 else if (exp->exp.X_op == O_big)
4957 {
4958 if (offs (exp) <= 0 /* flonum */
4959 && (ok == 80 /* no bignums */
4960 || (ok > 10 /* small-int ranges including 0 ok */
4961 /* If we have a flonum zero, a zero integer should
4962 do as well (e.g., in moveq). */
4963 && generic_floating_point_number.exponent == 0
4964 && generic_floating_point_number.low[0] == 0)))
4965 {
4966 /* HACK! Turn it into a long */
4967 LITTLENUM_TYPE words[6];
4968
4969 gen_to_words (words, 2, 8L); /* These numbers are magic! */
4970 op (exp) = O_constant;
4971 adds (exp) = 0;
4972 subs (exp) = 0;
4973 offs (exp) = words[1] | (words[0] << 16);
4974 }
4975 else if (ok != 0)
4976 {
4977 op (exp) = O_constant;
4978 adds (exp) = 0;
4979 subs (exp) = 0;
4980 offs (exp) = (ok == 10) ? 1 : 0;
4981 as_warn (_("Can't deal with expression; defaulting to %ld"),
4982 offs (exp));
4983 }
4984 }
4985 else
4986 {
4987 if (ok >= 10 && ok <= 70)
4988 {
4989 op (exp) = O_constant;
4990 adds (exp) = 0;
4991 subs (exp) = 0;
4992 offs (exp) = (ok == 10) ? 1 : 0;
4993 as_warn (_("Can't deal with expression; defaulting to %ld"),
4994 offs (exp));
4995 }
4996 }
4997
4998 if (exp->size != SIZE_UNSPEC)
4999 {
5000 switch (exp->size)
5001 {
5002 case SIZE_UNSPEC:
5003 case SIZE_LONG:
5004 break;
5005 case SIZE_BYTE:
5006 if (!isbyte (offs (exp)))
5007 as_warn (_("expression doesn't fit in BYTE"));
5008 break;
5009 case SIZE_WORD:
5010 if (!isword (offs (exp)))
5011 as_warn (_("expression doesn't fit in WORD"));
5012 break;
5013 }
5014 }
5015
5016 return offs (exp);
5017}
5018
5019/* These are the back-ends for the various machine dependent pseudo-ops. */
5020
5021static void
5022s_data1 (ignore)
36823076 5023 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5024{
5025 subseg_set (data_section, 1);
5026 demand_empty_rest_of_line ();
5027}
5028
5029static void
5030s_data2 (ignore)
36823076 5031 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5032{
5033 subseg_set (data_section, 2);
5034 demand_empty_rest_of_line ();
5035}
5036
5037static void
5038s_bss (ignore)
36823076 5039 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5040{
5041 /* We don't support putting frags in the BSS segment, we fake it
5042 by marking in_bss, then looking at s_skip for clues. */
5043
5044 subseg_set (bss_section, 0);
5045 demand_empty_rest_of_line ();
5046}
5047
5048static void
5049s_even (ignore)
36823076 5050 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5051{
5052 register int temp;
5053 register long temp_fill;
5054
5055 temp = 1; /* JF should be 2? */
5056 temp_fill = get_absolute_expression ();
92774660 5057 if (!need_pass_2) /* Never make frag if expect extra pass. */
252b5132
RH		 5058 frag_align (temp, (int) temp_fill, 0);
5059 demand_empty_rest_of_line ();
5060 record_alignment (now_seg, temp);
5061}
5062
5063static void
5064s_proc (ignore)
36823076 5065 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5066{
5067 demand_empty_rest_of_line ();
5068}
5069\f
5070/* Pseudo-ops handled for MRI compatibility. */
5071
5072/* This function returns non-zero if the argument is a conditional
5073 pseudo-op. This is called when checking whether a pending
5074 alignment is needed. */
5075
5076int
5077m68k_conditional_pseudoop (pop)
5078 pseudo_typeS *pop;
5079{
5080 return (pop->poc_handler == s_mri_if
5081 || pop->poc_handler == s_mri_else);
5082}
5083
5084/* Handle an MRI style chip specification. */
5085
5086static void
5087mri_chip ()
5088{
5089 char *s;
5090 char c;
5091 int i;
5092
5093 s = input_line_pointer;
5094 /* We can't use get_symbol_end since the processor names are not proper
5095 symbols. */
5096 while (is_part_of_name (c = *input_line_pointer++))
5097 ;
5098 *--input_line_pointer = 0;
5099 for (i = 0; i < n_archs; i++)
5100 if (strcasecmp (s, archs[i].name) == 0)
5101 break;
5102 if (i >= n_archs)
5103 {
5104 as_bad (_("%s: unrecognized processor name"), s);
5105 *input_line_pointer = c;
5106 ignore_rest_of_line ();
5107 return;
5108 }
5109 *input_line_pointer = c;
5110
5111 if (*input_line_pointer == '/')
5112 current_architecture = 0;
5113 else
5114 current_architecture &= m68881 | m68851;
5115 current_architecture |= archs[i].arch;
5116
5117 while (*input_line_pointer == '/')
5118 {
5119 ++input_line_pointer;
5120 s = input_line_pointer;
5121 /* We can't use get_symbol_end since the processor names are not
5122 proper symbols. */
5123 while (is_part_of_name (c = *input_line_pointer++))
5124 ;
5125 *--input_line_pointer = 0;
5126 if (strcmp (s, "68881") == 0)
5127 current_architecture |= m68881;
5128 else if (strcmp (s, "68851") == 0)
5129 current_architecture |= m68851;
5130 *input_line_pointer = c;
5131 }
5132
5133 /* Update info about available control registers. */
5134 select_control_regs ();
5135}
5136
5137/* The MRI CHIP pseudo-op. */
5138
5139static void
5140s_chip (ignore)
36823076 5141 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5142{
5143 char *stop = NULL;
5144 char stopc;
5145
5146 if (flag_mri)
5147 stop = mri_comment_field (&stopc);
5148 mri_chip ();
5149 if (flag_mri)
5150 mri_comment_end (stop, stopc);
5151 demand_empty_rest_of_line ();
5152}
5153
5154/* The MRI FOPT pseudo-op. */
5155
5156static void
5157s_fopt (ignore)
36823076 5158 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5159{
5160 SKIP_WHITESPACE ();
5161
5162 if (strncasecmp (input_line_pointer, "ID=", 3) == 0)
5163 {
5164 int temp;
5165
5166 input_line_pointer += 3;
5167 temp = get_absolute_expression ();
5168 if (temp < 0 || temp > 7)
5169 as_bad (_("bad coprocessor id"));
5170 else
5171 m68k_float_copnum = COP0 + temp;
5172 }
5173 else
5174 {
5175 as_bad (_("unrecognized fopt option"));
5176 ignore_rest_of_line ();
5177 return;
5178 }
5179
5180 demand_empty_rest_of_line ();
5181}
5182
5183/* The structure used to handle the MRI OPT pseudo-op. */
5184
5185struct opt_action
5186{
5187 /* The name of the option. */
5188 const char *name;
5189
5190 /* If this is not NULL, just call this function. The first argument
5191 is the ARG field of this structure, the second argument is
5192 whether the option was negated. */
5193 void (*pfn) PARAMS ((int arg, int on));
5194
5195 /* If this is not NULL, and the PFN field is NULL, set the variable
5196 this points to. Set it to the ARG field if the option was not
5197 negated, and the NOTARG field otherwise. */
5198 int *pvar;
5199
5200 /* The value to pass to PFN or to assign to *PVAR. */
5201 int arg;
5202
5203 /* The value to assign to *PVAR if the option is negated. If PFN is
5204 NULL, and PVAR is not NULL, and ARG and NOTARG are the same, then
5205 the option may not be negated. */
5206 int notarg;
5207};
5208
5209/* The table used to handle the MRI OPT pseudo-op. */
5210
5211static void skip_to_comma PARAMS ((int, int));
5212static void opt_nest PARAMS ((int, int));
5213static void opt_chip PARAMS ((int, int));
5214static void opt_list PARAMS ((int, int));
5215static void opt_list_symbols PARAMS ((int, int));
5216
5217static const struct opt_action opt_table[] =
5218{
5219 { "abspcadd", 0, &m68k_abspcadd, 1, 0 },
5220
5221 /* We do relaxing, so there is little use for these options. */
5222 { "b", 0, 0, 0, 0 },
5223 { "brs", 0, 0, 0, 0 },
5224 { "brb", 0, 0, 0, 0 },
5225 { "brl", 0, 0, 0, 0 },
5226 { "brw", 0, 0, 0, 0 },
5227
5228 { "c", 0, 0, 0, 0 },
5229 { "cex", 0, 0, 0, 0 },
5230 { "case", 0, &symbols_case_sensitive, 1, 0 },
5231 { "cl", 0, 0, 0, 0 },
5232 { "cre", 0, 0, 0, 0 },
5233 { "d", 0, &flag_keep_locals, 1, 0 },
5234 { "e", 0, 0, 0, 0 },
5235 { "f", 0, &flag_short_refs, 1, 0 },
5236 { "frs", 0, &flag_short_refs, 1, 0 },
5237 { "frl", 0, &flag_short_refs, 0, 1 },
5238 { "g", 0, 0, 0, 0 },
5239 { "i", 0, 0, 0, 0 },
5240 { "m", 0, 0, 0, 0 },
5241 { "mex", 0, 0, 0, 0 },
5242 { "mc", 0, 0, 0, 0 },
5243 { "md", 0, 0, 0, 0 },
5244 { "nest", opt_nest, 0, 0, 0 },
5245 { "next", skip_to_comma, 0, 0, 0 },
5246 { "o", 0, 0, 0, 0 },
5247 { "old", 0, 0, 0, 0 },
5248 { "op", skip_to_comma, 0, 0, 0 },
5249 { "pco", 0, 0, 0, 0 },
5250 { "p", opt_chip, 0, 0, 0 },
5251 { "pcr", 0, 0, 0, 0 },
5252 { "pcs", 0, 0, 0, 0 },
5253 { "r", 0, 0, 0, 0 },
5254 { "quick", 0, &m68k_quick, 1, 0 },
5255 { "rel32", 0, &m68k_rel32, 1, 0 },
5256 { "s", opt_list, 0, 0, 0 },
5257 { "t", opt_list_symbols, 0, 0, 0 },
5258 { "w", 0, &flag_no_warnings, 0, 1 },
5259 { "x", 0, 0, 0, 0 }
5260};
5261
8fce3f5e 5262#define OPTCOUNT ((int) (sizeof opt_table / sizeof opt_table[0]))
252b5132
RH		 5263
5264/* The MRI OPT pseudo-op. */
5265
5266static void
5267s_opt (ignore)
36823076 5268 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5269{
5270 do
5271 {
5272 int t;
5273 char *s;
5274 char c;
5275 int i;
5276 const struct opt_action *o;
5277
5278 SKIP_WHITESPACE ();
5279
5280 t = 1;
5281 if (*input_line_pointer == '-')
5282 {
5283 ++input_line_pointer;
5284 t = 0;
5285 }
5286 else if (strncasecmp (input_line_pointer, "NO", 2) == 0)
5287 {
5288 input_line_pointer += 2;
5289 t = 0;
5290 }
5291
5292 s = input_line_pointer;
5293 c = get_symbol_end ();
5294
5295 for (i = 0, o = opt_table; i < OPTCOUNT; i++, o++)
5296 {
5297 if (strcasecmp (s, o->name) == 0)
5298 {
5299 if (o->pfn)
5300 {
5301 /* Restore input_line_pointer now in case the option
5302 takes arguments. */
5303 *input_line_pointer = c;
5304 (*o->pfn) (o->arg, t);
5305 }
5306 else if (o->pvar != NULL)
5307 {
5308 if (! t && o->arg == o->notarg)
5309 as_bad (_("option `%s' may not be negated"), s);
5310 *input_line_pointer = c;
5311 *o->pvar = t ? o->arg : o->notarg;
5312 }
5313 else
5314 *input_line_pointer = c;
5315 break;
5316 }
5317 }
5318 if (i >= OPTCOUNT)
5319 {
5320 as_bad (_("option `%s' not recognized"), s);
5321 *input_line_pointer = c;
5322 }
5323 }
5324 while (*input_line_pointer++ == ',');
5325
5326 /* Move back to terminating character. */
5327 --input_line_pointer;
5328 demand_empty_rest_of_line ();
5329}
5330
5331/* Skip ahead to a comma. This is used for OPT options which we do
5332 not suppor tand which take arguments. */
5333
5334static void
5335skip_to_comma (arg, on)
36823076
AS		 5336 int arg ATTRIBUTE_UNUSED;
5337 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5338{
5339 while (*input_line_pointer != ','
5340 && ! is_end_of_line[(unsigned char) *input_line_pointer])
5341 ++input_line_pointer;
5342}
5343
5344/* Handle the OPT NEST=depth option. */
5345
5346static void
5347opt_nest (arg, on)
36823076
AS		 5348 int arg ATTRIBUTE_UNUSED;
5349 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5350{
5351 if (*input_line_pointer != '=')
5352 {
5353 as_bad (_("bad format of OPT NEST=depth"));
5354 return;
5355 }
5356
5357 ++input_line_pointer;
5358 max_macro_nest = get_absolute_expression ();
5359}
5360
5361/* Handle the OPT P=chip option. */
5362
5363static void
5364opt_chip (arg, on)
36823076
AS		 5365 int arg ATTRIBUTE_UNUSED;
5366 int on ATTRIBUTE_UNUSED;
252b5132
RH		 5367{
5368 if (*input_line_pointer != '=')
5369 {
5370 /* This is just OPT P, which we do not support. */
5371 return;
5372 }
5373
5374 ++input_line_pointer;
5375 mri_chip ();
5376}
5377
5378/* Handle the OPT S option. */
5379
5380static void
5381opt_list (arg, on)
36823076 5382 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5383 int on;
5384{
5385 listing_list (on);
5386}
5387
5388/* Handle the OPT T option. */
5389
5390static void
5391opt_list_symbols (arg, on)
36823076 5392 int arg ATTRIBUTE_UNUSED;
252b5132
RH		 5393 int on;
5394{
5395 if (on)
5396 listing |= LISTING_SYMBOLS;
5397 else
5398 listing &=~ LISTING_SYMBOLS;
5399}
5400
5401/* Handle the MRI REG pseudo-op. */
5402
5403static void
5404s_reg (ignore)
36823076 5405 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5406{
5407 char *s;
5408 int c;
5409 struct m68k_op rop;
5410 int mask;
5411 char *stop = NULL;
5412 char stopc;
5413
5414 if (line_label == NULL)
5415 {
5416 as_bad (_("missing label"));
5417 ignore_rest_of_line ();
5418 return;
5419 }
5420
5421 if (flag_mri)
5422 stop = mri_comment_field (&stopc);
5423
5424 SKIP_WHITESPACE ();
5425
5426 s = input_line_pointer;
5427 while (isalnum ((unsigned char) *input_line_pointer)
5428#ifdef REGISTER_PREFIX
5429 || *input_line_pointer == REGISTER_PREFIX
5430#endif
5431 || *input_line_pointer == '/'
5432 || *input_line_pointer == '-')
5433 ++input_line_pointer;
5434 c = *input_line_pointer;
5435 *input_line_pointer = '\0';
5436
5437 if (m68k_ip_op (s, &rop) != 0)
5438 {
5439 if (rop.error == NULL)
5440 as_bad (_("bad register list"));
5441 else
5442 as_bad (_("bad register list: %s"), rop.error);
5443 *input_line_pointer = c;
5444 ignore_rest_of_line ();
5445 return;
5446 }
5447
5448 *input_line_pointer = c;
5449
5450 if (rop.mode == REGLST)
5451 mask = rop.mask;
5452 else if (rop.mode == DREG)
5453 mask = 1 << (rop.reg - DATA0);
5454 else if (rop.mode == AREG)
5455 mask = 1 << (rop.reg - ADDR0 + 8);
5456 else if (rop.mode == FPREG)
5457 mask = 1 << (rop.reg - FP0 + 16);
5458 else if (rop.mode == CONTROL
5459 && rop.reg == FPI)
5460 mask = 1 << 24;
5461 else if (rop.mode == CONTROL
5462 && rop.reg == FPS)
5463 mask = 1 << 25;
5464 else if (rop.mode == CONTROL
5465 && rop.reg == FPC)
5466 mask = 1 << 26;
5467 else
5468 {
5469 as_bad (_("bad register list"));
5470 ignore_rest_of_line ();
5471 return;
5472 }
5473
5474 S_SET_SEGMENT (line_label, reg_section);
5475 S_SET_VALUE (line_label, ~mask);
49309057 5476 symbol_set_frag (line_label, &zero_address_frag);
252b5132
RH		 5477
5478 if (flag_mri)
5479 mri_comment_end (stop, stopc);
5480
5481 demand_empty_rest_of_line ();
5482}
5483
5484/* This structure is used for the MRI SAVE and RESTORE pseudo-ops. */
5485
5486struct save_opts
5487{
5488 struct save_opts *next;
5489 int abspcadd;
5490 int symbols_case_sensitive;
5491 int keep_locals;
5492 int short_refs;
5493 int architecture;
5494 int quick;
5495 int rel32;
5496 int listing;
5497 int no_warnings;
5498 /* FIXME: We don't save OPT S. */
5499};
5500
5501/* This variable holds the stack of saved options. */
5502
5503static struct save_opts *save_stack;
5504
5505/* The MRI SAVE pseudo-op. */
5506
5507static void
5508s_save (ignore)
36823076 5509 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5510{
5511 struct save_opts *s;
5512
5513 s = (struct save_opts *) xmalloc (sizeof (struct save_opts));
5514 s->abspcadd = m68k_abspcadd;
5515 s->symbols_case_sensitive = symbols_case_sensitive;
5516 s->keep_locals = flag_keep_locals;
5517 s->short_refs = flag_short_refs;
5518 s->architecture = current_architecture;
5519 s->quick = m68k_quick;
5520 s->rel32 = m68k_rel32;
5521 s->listing = listing;
5522 s->no_warnings = flag_no_warnings;
5523
5524 s->next = save_stack;
5525 save_stack = s;
5526
5527 demand_empty_rest_of_line ();
5528}
5529
5530/* The MRI RESTORE pseudo-op. */
5531
5532static void
5533s_restore (ignore)
36823076 5534 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 5535{
5536 struct save_opts *s;
5537
5538 if (save_stack == NULL)
5539 {
5540 as_bad (_("restore without save"));
5541 ignore_rest_of_line ();
5542 return;
5543 }
5544
5545 s = save_stack;
5546 save_stack = s->next;
5547
5548 m68k_abspcadd = s->abspcadd;
5549 symbols_case_sensitive = s->symbols_case_sensitive;
5550 flag_keep_locals = s->keep_locals;
5551 flag_short_refs = s->short_refs;
5552 current_architecture = s->architecture;
5553 m68k_quick = s->quick;
5554 m68k_rel32 = s->rel32;
5555 listing = s->listing;
5556 flag_no_warnings = s->no_warnings;
5557
5558 free (s);
5559
5560 demand_empty_rest_of_line ();
5561}
5562
5563/* Types of MRI structured control directives. */
5564
5565enum mri_control_type
5566{
5567 mri_for,
5568 mri_if,
5569 mri_repeat,
5570 mri_while
5571};
5572
5573/* This structure is used to stack the MRI structured control
5574 directives. */
5575
5576struct mri_control_info
5577{
5578 /* The directive within which this one is enclosed. */
5579 struct mri_control_info *outer;
5580
5581 /* The type of directive. */
5582 enum mri_control_type type;
5583
5584 /* Whether an ELSE has been in an IF. */
5585 int else_seen;
5586
5587 /* The add or sub statement at the end of a FOR. */
5588 char *incr;
5589
5590 /* The label of the top of a FOR or REPEAT loop. */
5591 char *top;
5592
5593 /* The label to jump to for the next iteration, or the else
5594 expression of a conditional. */
5595 char *next;
5596
5597 /* The label to jump to to break out of the loop, or the label past
5598 the end of a conditional. */
5599 char *bottom;
5600};
5601
5602/* The stack of MRI structured control directives. */
5603
5604static struct mri_control_info *mri_control_stack;
5605
5606/* The current MRI structured control directive index number, used to
5607 generate label names. */
5608
5609static int mri_control_index;
5610
5611/* Some function prototypes. */
5612
5613static void mri_assemble PARAMS ((char *));
5614static char *mri_control_label PARAMS ((void));
5615static struct mri_control_info *push_mri_control
5616 PARAMS ((enum mri_control_type));
5617static void pop_mri_control PARAMS ((void));
5618static int parse_mri_condition PARAMS ((int *));
5619static int parse_mri_control_operand
5620 PARAMS ((int *, char **, char **, char **, char **));
5621static int swap_mri_condition PARAMS ((int));
5622static int reverse_mri_condition PARAMS ((int));
5623static void build_mri_control_operand
5624 PARAMS ((int, int, char *, char *, char *, char *, const char *,
5625 const char *, int));
5626static void parse_mri_control_expression
5627 PARAMS ((char *, int, const char *, const char *, int));
5628
5629/* Assemble an instruction for an MRI structured control directive. */
5630
5631static void
5632mri_assemble (str)
5633 char *str;
5634{
5635 char *s;
5636
5637 /* md_assemble expects the opcode to be in lower case. */
5638 for (s = str; *s != ' ' && *s != '\0'; s++)
5639 {
5640 if (isupper ((unsigned char) *s))
5641 *s = tolower ((unsigned char) *s);
5642 }
5643
5644 md_assemble (str);
5645}
5646
5647/* Generate a new MRI label structured control directive label name. */
5648
5649static char *
5650mri_control_label ()
5651{
5652 char *n;
5653
5654 n = (char *) xmalloc (20);
5655 sprintf (n, "%smc%d", FAKE_LABEL_NAME, mri_control_index);
5656 ++mri_control_index;
5657 return n;
5658}
5659
5660/* Create a new MRI structured control directive. */
5661
5662static struct mri_control_info *
5663push_mri_control (type)
5664 enum mri_control_type type;
5665{
5666 struct mri_control_info *n;
5667
5668 n = (struct mri_control_info *) xmalloc (sizeof (struct mri_control_info));
5669
5670 n->type = type;
5671 n->else_seen = 0;
5672 if (type == mri_if || type == mri_while)
5673 n->top = NULL;
5674 else
5675 n->top = mri_control_label ();
5676 n->next = mri_control_label ();
5677 n->bottom = mri_control_label ();
5678
5679 n->outer = mri_control_stack;
5680 mri_control_stack = n;
5681
5682 return n;
5683}
5684
5685/* Pop off the stack of MRI structured control directives. */
5686
5687static void
5688pop_mri_control ()
5689{
5690 struct mri_control_info *n;
5691
5692 n = mri_control_stack;
5693 mri_control_stack = n->outer;
5694 if (n->top != NULL)
5695 free (n->top);
5696 free (n->next);
5697 free (n->bottom);
5698 free (n);
5699}
5700
5701/* Recognize a condition code in an MRI structured control expression. */
5702
5703static int
5704parse_mri_condition (pcc)
5705 int *pcc;
5706{
5707 char c1, c2;
5708
5709 know (*input_line_pointer == '<');
5710
5711 ++input_line_pointer;
5712 c1 = *input_line_pointer++;
5713 c2 = *input_line_pointer++;
5714
5715 if (*input_line_pointer != '>')
5716 {
5717 as_bad (_("syntax error in structured control directive"));
5718 return 0;
5719 }
5720
5721 ++input_line_pointer;
5722 SKIP_WHITESPACE ();
5723
5724 if (isupper (c1))
5725 c1 = tolower (c1);
5726 if (isupper (c2))
5727 c2 = tolower (c2);
5728
5729 *pcc = (c1 << 8) | c2;
5730
5731 return 1;
5732}
5733
5734/* Parse a single operand in an MRI structured control expression. */
5735
5736static int
5737parse_mri_control_operand (pcc, leftstart, leftstop, rightstart, rightstop)
5738 int *pcc;
5739 char **leftstart;
5740 char **leftstop;
5741 char **rightstart;
5742 char **rightstop;
5743{
5744 char *s;
5745
5746 SKIP_WHITESPACE ();
5747
5748 *pcc = -1;
5749 *leftstart = NULL;
5750 *leftstop = NULL;
5751 *rightstart = NULL;
5752 *rightstop = NULL;
5753
5754 if (*input_line_pointer == '<')
5755 {
5756 /* It's just a condition code. */
5757 return parse_mri_condition (pcc);
5758 }
5759
5760 /* Look ahead for the condition code. */
5761 for (s = input_line_pointer; *s != '\0'; ++s)
5762 {
5763 if (*s == '<' && s[1] != '\0' && s[2] != '\0' && s[3] == '>')
5764 break;
5765 }
5766 if (*s == '\0')
5767 {
5768 as_bad (_("missing condition code in structured control directive"));
5769 return 0;
5770 }
5771
5772 *leftstart = input_line_pointer;
5773 *leftstop = s;
5774 if (*leftstop > *leftstart
5775 && ((*leftstop)[-1] == ' ' || (*leftstop)[-1] == '\t'))
5776 --*leftstop;
5777
5778 input_line_pointer = s;
5779 if (! parse_mri_condition (pcc))
5780 return 0;
5781
5782 /* Look ahead for AND or OR or end of line. */
5783 for (s = input_line_pointer; *s != '\0'; ++s)
5784 {
5785 if ((strncasecmp (s, "AND", 3) == 0
5786 && (s[3] == '.' || ! is_part_of_name (s[3])))
5787 || (strncasecmp (s, "OR", 2) == 0
5788 && (s[2] == '.' || ! is_part_of_name (s[2]))))
5789 break;
5790 }
5791
5792 *rightstart = input_line_pointer;
5793 *rightstop = s;
5794 if (*rightstop > *rightstart
5795 && ((*rightstop)[-1] == ' ' || (*rightstop)[-1] == '\t'))
5796 --*rightstop;
5797
5798 input_line_pointer = s;
5799
5800 return 1;
5801}
5802
5803#define MCC(b1, b2) (((b1) << 8) | (b2))
5804
5805/* Swap the sense of a condition. This changes the condition so that
5806 it generates the same result when the operands are swapped. */
5807
5808static int
5809swap_mri_condition (cc)
5810 int cc;
5811{
5812 switch (cc)
5813 {
5814 case MCC ('h', 'i'): return MCC ('c', 's');
5815 case MCC ('l', 's'): return MCC ('c', 'c');
5816 case MCC ('c', 'c'): return MCC ('l', 's');
5817 case MCC ('c', 's'): return MCC ('h', 'i');
5818 case MCC ('p', 'l'): return MCC ('m', 'i');
5819 case MCC ('m', 'i'): return MCC ('p', 'l');
5820 case MCC ('g', 'e'): return MCC ('l', 'e');
5821 case MCC ('l', 't'): return MCC ('g', 't');
5822 case MCC ('g', 't'): return MCC ('l', 't');
5823 case MCC ('l', 'e'): return MCC ('g', 'e');
5824 }
5825 return cc;
5826}
5827
5828/* Reverse the sense of a condition. */
5829
5830static int
5831reverse_mri_condition (cc)
5832 int cc;
5833{
5834 switch (cc)
5835 {
5836 case MCC ('h', 'i'): return MCC ('l', 's');
5837 case MCC ('l', 's'): return MCC ('h', 'i');
5838 case MCC ('c', 'c'): return MCC ('c', 's');
5839 case MCC ('c', 's'): return MCC ('c', 'c');
5840 case MCC ('n', 'e'): return MCC ('e', 'q');
5841 case MCC ('e', 'q'): return MCC ('n', 'e');
5842 case MCC ('v', 'c'): return MCC ('v', 's');
5843 case MCC ('v', 's'): return MCC ('v', 'c');
5844 case MCC ('p', 'l'): return MCC ('m', 'i');
5845 case MCC ('m', 'i'): return MCC ('p', 'l');
5846 case MCC ('g', 'e'): return MCC ('l', 't');
5847 case MCC ('l', 't'): return MCC ('g', 'e');
5848 case MCC ('g', 't'): return MCC ('l', 'e');
5849 case MCC ('l', 'e'): return MCC ('g', 't');
5850 }
5851 return cc;
5852}
5853
5854/* Build an MRI structured control expression. This generates test
5855 and branch instructions. It goes to TRUELAB if the condition is
5856 true, and to FALSELAB if the condition is false. Exactly one of
5857 TRUELAB and FALSELAB will be NULL, meaning to fall through. QUAL
5858 is the size qualifier for the expression. EXTENT is the size to
5859 use for the branch. */
5860
5861static void
5862build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5863 rightstop, truelab, falselab, extent)
5864 int qual;
5865 int cc;
5866 char *leftstart;
5867 char *leftstop;
5868 char *rightstart;
5869 char *rightstop;
5870 const char *truelab;
5871 const char *falselab;
5872 int extent;
5873{
5874 char *buf;
5875 char *s;
5876
5877 if (leftstart != NULL)
5878 {
5879 struct m68k_op leftop, rightop;
5880 char c;
5881
5882 /* Swap the compare operands, if necessary, to produce a legal
5883 m68k compare instruction. Comparing a register operand with
5884 a non-register operand requires the register to be on the
5885 right (cmp, cmpa). Comparing an immediate value with
5886 anything requires the immediate value to be on the left
5887 (cmpi). */
5888
5889 c = *leftstop;
5890 *leftstop = '\0';
5891 (void) m68k_ip_op (leftstart, &leftop);
5892 *leftstop = c;
5893
5894 c = *rightstop;
5895 *rightstop = '\0';
5896 (void) m68k_ip_op (rightstart, &rightop);
5897 *rightstop = c;
5898
5899 if (rightop.mode == IMMED
5900 || ((leftop.mode == DREG || leftop.mode == AREG)
5901 && (rightop.mode != DREG && rightop.mode != AREG)))
5902 {
5903 char *temp;
5904
5905 cc = swap_mri_condition (cc);
5906 temp = leftstart;
5907 leftstart = rightstart;
5908 rightstart = temp;
5909 temp = leftstop;
5910 leftstop = rightstop;
5911 rightstop = temp;
5912 }
5913 }
5914
5915 if (truelab == NULL)
5916 {
5917 cc = reverse_mri_condition (cc);
5918 truelab = falselab;
5919 }
92774660 5920
252b5132
RH		 5921 if (leftstart != NULL)
5922 {
5923 buf = (char *) xmalloc (20
5924 + (leftstop - leftstart)
5925 + (rightstop - rightstart));
5926 s = buf;
5927 *s++ = 'c';
5928 *s++ = 'm';
5929 *s++ = 'p';
5930 if (qual != '\0')
5931 *s++ = qual;
5932 *s++ = ' ';
5933 memcpy (s, leftstart, leftstop - leftstart);
5934 s += leftstop - leftstart;
5935 *s++ = ',';
5936 memcpy (s, rightstart, rightstop - rightstart);
5937 s += rightstop - rightstart;
5938 *s = '\0';
5939 mri_assemble (buf);
5940 free (buf);
5941 }
92774660 5942
252b5132
RH		 5943 buf = (char *) xmalloc (20 + strlen (truelab));
5944 s = buf;
5945 *s++ = 'b';
5946 *s++ = cc >> 8;
5947 *s++ = cc & 0xff;
5948 if (extent != '\0')
5949 *s++ = extent;
5950 *s++ = ' ';
5951 strcpy (s, truelab);
5952 mri_assemble (buf);
5953 free (buf);
5954}
5955
5956/* Parse an MRI structured control expression. This generates test
5957 and branch instructions. STOP is where the expression ends. It
5958 goes to TRUELAB if the condition is true, and to FALSELAB if the
5959 condition is false. Exactly one of TRUELAB and FALSELAB will be
5960 NULL, meaning to fall through. QUAL is the size qualifier for the
5961 expression. EXTENT is the size to use for the branch. */
5962
5963static void
5964parse_mri_control_expression (stop, qual, truelab, falselab, extent)
5965 char *stop;
5966 int qual;
5967 const char *truelab;
5968 const char *falselab;
5969 int extent;
5970{
5971 int c;
5972 int cc;
5973 char *leftstart;
5974 char *leftstop;
5975 char *rightstart;
5976 char *rightstop;
5977
5978 c = *stop;
5979 *stop = '\0';
5980
5981 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
5982 &rightstart, &rightstop))
5983 {
5984 *stop = c;
5985 return;
5986 }
5987
5988 if (strncasecmp (input_line_pointer, "AND", 3) == 0)
5989 {
5990 const char *flab;
5991
5992 if (falselab != NULL)
5993 flab = falselab;
5994 else
5995 flab = mri_control_label ();
5996
5997 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
5998 rightstop, (const char *) NULL, flab, extent);
5999
6000 input_line_pointer += 3;
6001 if (*input_line_pointer != '.'
6002 || input_line_pointer[1] == '\0')
6003 qual = '\0';
6004 else
6005 {
6006 qual = input_line_pointer[1];
6007 input_line_pointer += 2;
6008 }
6009
6010 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6011 &rightstart, &rightstop))
6012 {
6013 *stop = c;
6014 return;
6015 }
6016
6017 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6018 rightstop, truelab, falselab, extent);
6019
6020 if (falselab == NULL)
6021 colon (flab);
6022 }
6023 else if (strncasecmp (input_line_pointer, "OR", 2) == 0)
6024 {
6025 const char *tlab;
6026
6027 if (truelab != NULL)
6028 tlab = truelab;
6029 else
6030 tlab = mri_control_label ();
6031
6032 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6033 rightstop, tlab, (const char *) NULL, extent);
6034
6035 input_line_pointer += 2;
6036 if (*input_line_pointer != '.'
6037 || input_line_pointer[1] == '\0')
6038 qual = '\0';
6039 else
6040 {
6041 qual = input_line_pointer[1];
6042 input_line_pointer += 2;
6043 }
6044
6045 if (! parse_mri_control_operand (&cc, &leftstart, &leftstop,
6046 &rightstart, &rightstop))
6047 {
6048 *stop = c;
6049 return;
6050 }
6051
6052 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6053 rightstop, truelab, falselab, extent);
6054
6055 if (truelab == NULL)
6056 colon (tlab);
6057 }
6058 else
6059 {
6060 build_mri_control_operand (qual, cc, leftstart, leftstop, rightstart,
6061 rightstop, truelab, falselab, extent);
6062 }
6063
6064 *stop = c;
6065 if (input_line_pointer != stop)
6066 as_bad (_("syntax error in structured control directive"));
6067}
6068
6069/* Handle the MRI IF pseudo-op. This may be a structured control
6070 directive, or it may be a regular assembler conditional, depending
6071 on its operands. */
6072
6073static void
6074s_mri_if (qual)
6075 int qual;
6076{
6077 char *s;
6078 int c;
6079 struct mri_control_info *n;
6080
6081 /* A structured control directive must end with THEN with an
6082 optional qualifier. */
6083 s = input_line_pointer;
6084 while (! is_end_of_line[(unsigned char) *s]
6085 && (! flag_mri || *s != '*'))
6086 ++s;
6087 --s;
6088 while (s > input_line_pointer && (*s == ' ' || *s == '\t'))
6089 --s;
6090
6091 if (s - input_line_pointer > 1
6092 && s[-1] == '.')
6093 s -= 2;
6094
6095 if (s - input_line_pointer < 3
6096 || strncasecmp (s - 3, "THEN", 4) != 0)
6097 {
6098 if (qual != '\0')
6099 {
6100 as_bad (_("missing then"));
6101 ignore_rest_of_line ();
6102 return;
6103 }
6104
6105 /* It's a conditional. */
6106 s_if (O_ne);
6107 return;
6108 }
6109
6110 /* Since this might be a conditional if, this pseudo-op will be
6111 called even if we are supported to be ignoring input. Double
6112 check now. Clobber *input_line_pointer so that ignore_input
6113 thinks that this is not a special pseudo-op. */
6114 c = *input_line_pointer;
6115 *input_line_pointer = 0;
6116 if (ignore_input ())
6117 {
6118 *input_line_pointer = c;
6119 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6120 ++input_line_pointer;
6121 demand_empty_rest_of_line ();
6122 return;
6123 }
6124 *input_line_pointer = c;
6125
6126 n = push_mri_control (mri_if);
6127
6128 parse_mri_control_expression (s - 3, qual, (const char *) NULL,
6129 n->next, s[1] == '.' ? s[2] : '\0');
6130
6131 if (s[1] == '.')
6132 input_line_pointer = s + 3;
6133 else
6134 input_line_pointer = s + 1;
6135
6136 if (flag_mri)
6137 {
6138 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6139 ++input_line_pointer;
6140 }
6141
6142 demand_empty_rest_of_line ();
6143}
6144
6145/* Handle the MRI else pseudo-op. If we are currently doing an MRI
6146 structured IF, associate the ELSE with the IF. Otherwise, assume
6147 it is a conditional else. */
6148
6149static void
6150s_mri_else (qual)
6151 int qual;
6152{
6153 int c;
6154 char *buf;
6155 char q[2];
6156
6157 if (qual == '\0'
6158 && (mri_control_stack == NULL
6159 || mri_control_stack->type != mri_if
6160 || mri_control_stack->else_seen))
6161 {
6162 s_else (0);
6163 return;
6164 }
6165
6166 c = *input_line_pointer;
6167 *input_line_pointer = 0;
6168 if (ignore_input ())
6169 {
6170 *input_line_pointer = c;
6171 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6172 ++input_line_pointer;
6173 demand_empty_rest_of_line ();
6174 return;
6175 }
6176 *input_line_pointer = c;
6177
6178 if (mri_control_stack == NULL
6179 || mri_control_stack->type != mri_if
6180 || mri_control_stack->else_seen)
6181 {
6182 as_bad (_("else without matching if"));
6183 ignore_rest_of_line ();
6184 return;
6185 }
6186
6187 mri_control_stack->else_seen = 1;
6188
6189 buf = (char *) xmalloc (20 + strlen (mri_control_stack->bottom));
6190 q[0] = qual;
6191 q[1] = '\0';
6192 sprintf (buf, "bra%s %s", q, mri_control_stack->bottom);
6193 mri_assemble (buf);
6194 free (buf);
6195
6196 colon (mri_control_stack->next);
6197
6198 if (flag_mri)
6199 {
6200 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6201 ++input_line_pointer;
6202 }
6203
6204 demand_empty_rest_of_line ();
6205}
6206
6207/* Handle the MRI ENDI pseudo-op. */
6208
6209static void
6210s_mri_endi (ignore)
36823076 6211 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6212{
6213 if (mri_control_stack == NULL
6214 || mri_control_stack->type != mri_if)
6215 {
6216 as_bad (_("endi without matching if"));
6217 ignore_rest_of_line ();
6218 return;
6219 }
6220
6221 /* ignore_input will not return true for ENDI, so we don't need to
6222 worry about checking it again here. */
6223
6224 if (! mri_control_stack->else_seen)
6225 colon (mri_control_stack->next);
6226 colon (mri_control_stack->bottom);
6227
6228 pop_mri_control ();
6229
6230 if (flag_mri)
6231 {
6232 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6233 ++input_line_pointer;
6234 }
6235
6236 demand_empty_rest_of_line ();
6237}
6238
6239/* Handle the MRI BREAK pseudo-op. */
6240
6241static void
6242s_mri_break (extent)
6243 int extent;
6244{
6245 struct mri_control_info *n;
6246 char *buf;
6247 char ex[2];
6248
6249 n = mri_control_stack;
6250 while (n != NULL
6251 && n->type != mri_for
6252 && n->type != mri_repeat
6253 && n->type != mri_while)
6254 n = n->outer;
6255 if (n == NULL)
6256 {
6257 as_bad (_("break outside of structured loop"));
6258 ignore_rest_of_line ();
6259 return;
6260 }
6261
6262 buf = (char *) xmalloc (20 + strlen (n->bottom));
6263 ex[0] = extent;
6264 ex[1] = '\0';
6265 sprintf (buf, "bra%s %s", ex, n->bottom);
6266 mri_assemble (buf);
6267 free (buf);
6268
6269 if (flag_mri)
6270 {
6271 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6272 ++input_line_pointer;
6273 }
6274
6275 demand_empty_rest_of_line ();
6276}
6277
6278/* Handle the MRI NEXT pseudo-op. */
6279
6280static void
6281s_mri_next (extent)
6282 int extent;
6283{
6284 struct mri_control_info *n;
6285 char *buf;
6286 char ex[2];
6287
6288 n = mri_control_stack;
6289 while (n != NULL
6290 && n->type != mri_for
6291 && n->type != mri_repeat
6292 && n->type != mri_while)
6293 n = n->outer;
6294 if (n == NULL)
6295 {
6296 as_bad (_("next outside of structured loop"));
6297 ignore_rest_of_line ();
6298 return;
6299 }
6300
6301 buf = (char *) xmalloc (20 + strlen (n->next));
6302 ex[0] = extent;
6303 ex[1] = '\0';
6304 sprintf (buf, "bra%s %s", ex, n->next);
6305 mri_assemble (buf);
6306 free (buf);
6307
6308 if (flag_mri)
6309 {
6310 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6311 ++input_line_pointer;
6312 }
6313
6314 demand_empty_rest_of_line ();
6315}
6316
6317/* Handle the MRI FOR pseudo-op. */
6318
6319static void
6320s_mri_for (qual)
6321 int qual;
6322{
6323 const char *varstart, *varstop;
6324 const char *initstart, *initstop;
6325 const char *endstart, *endstop;
6326 const char *bystart, *bystop;
6327 int up;
6328 int by;
6329 int extent;
6330 struct mri_control_info *n;
6331 char *buf;
6332 char *s;
6333 char ex[2];
6334
6335 /* The syntax is
6336 FOR.q var = init { TO | DOWNTO } end [ BY by ] DO.e
6337 */
6338
6339 SKIP_WHITESPACE ();
6340 varstart = input_line_pointer;
6341
6342 /* Look for the '='. */
6343 while (! is_end_of_line[(unsigned char) *input_line_pointer]
6344 && *input_line_pointer != '=')
6345 ++input_line_pointer;
6346 if (*input_line_pointer != '=')
6347 {
6348 as_bad (_("missing ="));
6349 ignore_rest_of_line ();
6350 return;
6351 }
6352
6353 varstop = input_line_pointer;
6354 if (varstop > varstart
6355 && (varstop[-1] == ' ' || varstop[-1] == '\t'))
6356 --varstop;
6357
6358 ++input_line_pointer;
6359
6360 initstart = input_line_pointer;
6361
6362 /* Look for TO or DOWNTO. */
6363 up = 1;
6364 initstop = NULL;
6365 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6366 {
6367 if (strncasecmp (input_line_pointer, "TO", 2) == 0
6368 && ! is_part_of_name (input_line_pointer[2]))
6369 {
6370 initstop = input_line_pointer;
6371 input_line_pointer += 2;
6372 break;
6373 }
6374 if (strncasecmp (input_line_pointer, "DOWNTO", 6) == 0
6375 && ! is_part_of_name (input_line_pointer[6]))
6376 {
6377 initstop = input_line_pointer;
6378 up = 0;
6379 input_line_pointer += 6;
6380 break;
6381 }
6382 ++input_line_pointer;
6383 }
6384 if (initstop == NULL)
6385 {
6386 as_bad (_("missing to or downto"));
6387 ignore_rest_of_line ();
6388 return;
6389 }
6390 if (initstop > initstart
6391 && (initstop[-1] == ' ' || initstop[-1] == '\t'))
6392 --initstop;
6393
6394 SKIP_WHITESPACE ();
6395 endstart = input_line_pointer;
6396
6397 /* Look for BY or DO. */
6398 by = 0;
6399 endstop = NULL;
6400 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6401 {
6402 if (strncasecmp (input_line_pointer, "BY", 2) == 0
6403 && ! is_part_of_name (input_line_pointer[2]))
6404 {
6405 endstop = input_line_pointer;
6406 by = 1;
6407 input_line_pointer += 2;
6408 break;
6409 }
6410 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6411 && (input_line_pointer[2] == '.'
6412 || ! is_part_of_name (input_line_pointer[2])))
6413 {
6414 endstop = input_line_pointer;
6415 input_line_pointer += 2;
6416 break;
6417 }
6418 ++input_line_pointer;
6419 }
6420 if (endstop == NULL)
6421 {
6422 as_bad (_("missing do"));
6423 ignore_rest_of_line ();
6424 return;
6425 }
6426 if (endstop > endstart
6427 && (endstop[-1] == ' ' || endstop[-1] == '\t'))
6428 --endstop;
6429
6430 if (! by)
6431 {
6432 bystart = "#1";
6433 bystop = bystart + 2;
6434 }
6435 else
6436 {
6437 SKIP_WHITESPACE ();
6438 bystart = input_line_pointer;
6439
6440 /* Look for DO. */
6441 bystop = NULL;
6442 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6443 {
6444 if (strncasecmp (input_line_pointer, "DO", 2) == 0
6445 && (input_line_pointer[2] == '.'
6446 || ! is_part_of_name (input_line_pointer[2])))
6447 {
6448 bystop = input_line_pointer;
6449 input_line_pointer += 2;
6450 break;
6451 }
6452 ++input_line_pointer;
6453 }
6454 if (bystop == NULL)
6455 {
6456 as_bad (_("missing do"));
6457 ignore_rest_of_line ();
6458 return;
6459 }
6460 if (bystop > bystart
6461 && (bystop[-1] == ' ' || bystop[-1] == '\t'))
6462 --bystop;
6463 }
6464
6465 if (*input_line_pointer != '.')
6466 extent = '\0';
6467 else
6468 {
6469 extent = input_line_pointer[1];
6470 input_line_pointer += 2;
6471 }
6472
6473 /* We have fully parsed the FOR operands. Now build the loop. */
6474
6475 n = push_mri_control (mri_for);
6476
6477 buf = (char *) xmalloc (50 + (input_line_pointer - varstart));
6478
6479 /* move init,var */
6480 s = buf;
6481 *s++ = 'm';
6482 *s++ = 'o';
6483 *s++ = 'v';
6484 *s++ = 'e';
6485 if (qual != '\0')
6486 *s++ = qual;
6487 *s++ = ' ';
6488 memcpy (s, initstart, initstop - initstart);
6489 s += initstop - initstart;
6490 *s++ = ',';
6491 memcpy (s, varstart, varstop - varstart);
6492 s += varstop - varstart;
6493 *s = '\0';
6494 mri_assemble (buf);
6495
6496 colon (n->top);
6497
6498 /* cmp end,var */
6499 s = buf;
6500 *s++ = 'c';
6501 *s++ = 'm';
6502 *s++ = 'p';
6503 if (qual != '\0')
6504 *s++ = qual;
6505 *s++ = ' ';
6506 memcpy (s, endstart, endstop - endstart);
6507 s += endstop - endstart;
6508 *s++ = ',';
6509 memcpy (s, varstart, varstop - varstart);
6510 s += varstop - varstart;
6511 *s = '\0';
6512 mri_assemble (buf);
6513
6514 /* bcc bottom */
6515 ex[0] = extent;
6516 ex[1] = '\0';
6517 if (up)
6518 sprintf (buf, "blt%s %s", ex, n->bottom);
6519 else
6520 sprintf (buf, "bgt%s %s", ex, n->bottom);
6521 mri_assemble (buf);
6522
6523 /* Put together the add or sub instruction used by ENDF. */
6524 s = buf;
6525 if (up)
6526 strcpy (s, "add");
6527 else
6528 strcpy (s, "sub");
6529 s += 3;
6530 if (qual != '\0')
6531 *s++ = qual;
6532 *s++ = ' ';
6533 memcpy (s, bystart, bystop - bystart);
6534 s += bystop - bystart;
6535 *s++ = ',';
6536 memcpy (s, varstart, varstop - varstart);
6537 s += varstop - varstart;
6538 *s = '\0';
6539 n->incr = buf;
6540
6541 if (flag_mri)
6542 {
6543 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6544 ++input_line_pointer;
6545 }
6546
6547 demand_empty_rest_of_line ();
6548}
6549
6550/* Handle the MRI ENDF pseudo-op. */
6551
6552static void
6553s_mri_endf (ignore)
36823076 6554 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6555{
6556 if (mri_control_stack == NULL
6557 || mri_control_stack->type != mri_for)
6558 {
6559 as_bad (_("endf without for"));
6560 ignore_rest_of_line ();
6561 return;
6562 }
6563
6564 colon (mri_control_stack->next);
6565
6566 mri_assemble (mri_control_stack->incr);
6567
6568 sprintf (mri_control_stack->incr, "bra %s", mri_control_stack->top);
6569 mri_assemble (mri_control_stack->incr);
6570
6571 free (mri_control_stack->incr);
6572
6573 colon (mri_control_stack->bottom);
6574
6575 pop_mri_control ();
6576
6577 if (flag_mri)
6578 {
6579 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6580 ++input_line_pointer;
6581 }
6582
6583 demand_empty_rest_of_line ();
6584}
6585
6586/* Handle the MRI REPEAT pseudo-op. */
6587
6588static void
6589s_mri_repeat (ignore)
36823076 6590 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6591{
6592 struct mri_control_info *n;
6593
6594 n = push_mri_control (mri_repeat);
6595 colon (n->top);
6596 if (flag_mri)
6597 {
6598 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6599 ++input_line_pointer;
6600 }
6601 demand_empty_rest_of_line ();
6602}
6603
6604/* Handle the MRI UNTIL pseudo-op. */
6605
6606static void
6607s_mri_until (qual)
6608 int qual;
6609{
6610 char *s;
6611
6612 if (mri_control_stack == NULL
6613 || mri_control_stack->type != mri_repeat)
6614 {
6615 as_bad (_("until without repeat"));
6616 ignore_rest_of_line ();
6617 return;
6618 }
6619
6620 colon (mri_control_stack->next);
6621
6622 for (s = input_line_pointer; ! is_end_of_line[(unsigned char) *s]; s++)
6623 ;
6624
6625 parse_mri_control_expression (s, qual, (const char *) NULL,
6626 mri_control_stack->top, '\0');
6627
6628 colon (mri_control_stack->bottom);
6629
6630 input_line_pointer = s;
6631
6632 pop_mri_control ();
6633
6634 if (flag_mri)
6635 {
6636 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6637 ++input_line_pointer;
6638 }
6639
6640 demand_empty_rest_of_line ();
6641}
6642
6643/* Handle the MRI WHILE pseudo-op. */
6644
6645static void
6646s_mri_while (qual)
6647 int qual;
6648{
6649 char *s;
6650
6651 struct mri_control_info *n;
6652
6653 s = input_line_pointer;
6654 while (! is_end_of_line[(unsigned char) *s]
6655 && (! flag_mri || *s != '*'))
6656 s++;
6657 --s;
6658 while (*s == ' ' || *s == '\t')
6659 --s;
6660 if (s - input_line_pointer > 1
6661 && s[-1] == '.')
6662 s -= 2;
6663 if (s - input_line_pointer < 2
6664 || strncasecmp (s - 1, "DO", 2) != 0)
6665 {
6666 as_bad (_("missing do"));
6667 ignore_rest_of_line ();
6668 return;
6669 }
6670
6671 n = push_mri_control (mri_while);
6672
6673 colon (n->next);
6674
6675 parse_mri_control_expression (s - 1, qual, (const char *) NULL, n->bottom,
6676 s[1] == '.' ? s[2] : '\0');
6677
6678 input_line_pointer = s + 1;
6679 if (*input_line_pointer == '.')
6680 input_line_pointer += 2;
6681
6682 if (flag_mri)
6683 {
6684 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6685 ++input_line_pointer;
6686 }
6687
6688 demand_empty_rest_of_line ();
6689}
6690
6691/* Handle the MRI ENDW pseudo-op. */
6692
6693static void
6694s_mri_endw (ignore)
36823076 6695 int ignore ATTRIBUTE_UNUSED;
252b5132
RH		 6696{
6697 char *buf;
6698
6699 if (mri_control_stack == NULL
6700 || mri_control_stack->type != mri_while)
6701 {
6702 as_bad (_("endw without while"));
6703 ignore_rest_of_line ();
6704 return;
6705 }
6706
6707 buf = (char *) xmalloc (20 + strlen (mri_control_stack->next));
6708 sprintf (buf, "bra %s", mri_control_stack->next);
6709 mri_assemble (buf);
6710 free (buf);
6711
6712 colon (mri_control_stack->bottom);
6713
6714 pop_mri_control ();
6715
6716 if (flag_mri)
6717 {
6718 while (! is_end_of_line[(unsigned char) *input_line_pointer])
6719 ++input_line_pointer;
6720 }
6721
6722 demand_empty_rest_of_line ();
6723}
6724\f
6725/*
6726 * md_parse_option
6727 * Invocation line includes a switch not recognized by the base assembler.
6728 * See if it's a processor-specific option. These are:
6729 *
6730 * -[A]m[c]68000, -[A]m[c]68008, -[A]m[c]68010, -[A]m[c]68020, -[A]m[c]68030, -[A]m[c]68040
6731 * -[A]m[c]68881, -[A]m[c]68882, -[A]m[c]68851
6732 * Select the architecture. Instructions or features not
6733 * supported by the selected architecture cause fatal
6734 * errors. More than one may be specified. The default is
6735 * -m68020 -m68851 -m68881. Note that -m68008 is a synonym
6736 * for -m68000, and -m68882 is a synonym for -m68881.
6737 * -[A]m[c]no-68851, -[A]m[c]no-68881
6738 * Don't accept 688?1 instructions. (The "c" is kind of silly,
6739 * so don't use or document it, but that's the way the parsing
6740 * works).
6741 *
6742 * -pic Indicates PIC.
6743 * -k Indicates PIC. (Sun 3 only.)
28e7409f 6744 * --pcrel Never turn PC-relative branches into absolute jumps.
252b5132
RH		 6745 *
6746 * --bitwise-or
6747 * Permit `|' to be used in expressions.
6748 *
6749 */
6750
6751#ifdef OBJ_ELF
6752CONST char *md_shortopts = "lSA:m:kQ:V";
6753#else
6754CONST char *md_shortopts = "lSA:m:k";
6755#endif
6756
6757struct option md_longopts[] = {
6758#define OPTION_PIC (OPTION_MD_BASE)
6759 {"pic", no_argument, NULL, OPTION_PIC},
6760#define OPTION_REGISTER_PREFIX_OPTIONAL (OPTION_MD_BASE + 1)
6761 {"register-prefix-optional", no_argument, NULL,
6762 OPTION_REGISTER_PREFIX_OPTIONAL},
6763#define OPTION_BITWISE_OR (OPTION_MD_BASE + 2)
6764 {"bitwise-or", no_argument, NULL, OPTION_BITWISE_OR},
6765#define OPTION_BASE_SIZE_DEFAULT_16 (OPTION_MD_BASE + 3)
6766 {"base-size-default-16", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_16},
6767#define OPTION_BASE_SIZE_DEFAULT_32 (OPTION_MD_BASE + 4)
6768 {"base-size-default-32", no_argument, NULL, OPTION_BASE_SIZE_DEFAULT_32},
6769#define OPTION_DISP_SIZE_DEFAULT_16 (OPTION_MD_BASE + 5)
6770 {"disp-size-default-16", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_16},
6771#define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 6)
6772 {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32},
28e7409f
NC		 6773#define OPTION_PCREL (OPTION_MD_BASE + 7)
6774 {"pcrel", no_argument, NULL, OPTION_PCREL},
252b5132
RH		 6775 {NULL, no_argument, NULL, 0}
6776};
bc805888 6777size_t md_longopts_size = sizeof (md_longopts);
252b5132
RH		 6778
6779int
6780md_parse_option (c, arg)
6781 int c;
6782 char *arg;
6783{
6784 switch (c)
6785 {
6786 case 'l': /* -l means keep external to 2 bit offset
6787 rather than 16 bit one */
6788 flag_short_refs = 1;
6789 break;
6790
6791 case 'S': /* -S means that jbsr's always turn into
6792 jsr's. */
6793 flag_long_jumps = 1;
6794 break;
6795
28e7409f
NC		 6796 case OPTION_PCREL: /* --pcrel means never turn PC-relative
6797 branches into absolute jumps. */
6798 flag_keep_pcrel = 1;
6799 break;
6800
252b5132
RH		 6801 case 'A':
6802 if (*arg == 'm')
6803 arg++;
6804 /* intentional fall-through */
6805 case 'm':
6806
6807 if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-')
6808 {
6809 int i;
6810 unsigned long arch;
6811 const char *oarg = arg;
6812
6813 arg += 3;
6814 if (*arg == 'm')
6815 {
6816 arg++;
6817 if (arg[0] == 'c' && arg[1] == '6')
6818 arg++;
6819 }
6820 for (i = 0; i < n_archs; i++)
6821 if (!strcmp (arg, archs[i].name))
6822 break;
6823 if (i == n_archs)
6824 {
6825 unknown:
6826 as_bad (_("unrecognized option `%s'"), oarg);
6827 return 0;
6828 }
6829 arch = archs[i].arch;
6830 if (arch == m68881)
6831 no_68881 = 1;
6832 else if (arch == m68851)
6833 no_68851 = 1;
6834 else
6835 goto unknown;
6836 }
6837 else
6838 {
6839 int i;
6840
6841 if (arg[0] == 'c' && arg[1] == '6')
6842 arg++;
6843
6844 for (i = 0; i < n_archs; i++)
6845 if (!strcmp (arg, archs[i].name))
6846 {
6847 unsigned long arch = archs[i].arch;
6848 if (cpu_of_arch (arch))
6849 /* It's a cpu spec. */
6850 {
6851 current_architecture &= ~m68000up;
6852 current_architecture |= arch;
6853 }
6854 else if (arch == m68881)
6855 {
6856 current_architecture |= m68881;
6857 no_68881 = 0;
6858 }
6859 else if (arch == m68851)
6860 {
6861 current_architecture |= m68851;
6862 no_68851 = 0;
6863 }
6864 else
6865 /* ??? */
6866 abort ();
6867 break;
6868 }
6869 if (i == n_archs)
6870 {
6871 as_bad (_("unrecognized architecture specification `%s'"), arg);
6872 return 0;
6873 }
6874 }
6875 break;
6876
6877 case OPTION_PIC:
6878 case 'k':
6879 flag_want_pic = 1;
6880 break; /* -pic, Position Independent Code */
6881
6882 case OPTION_REGISTER_PREFIX_OPTIONAL:
6883 flag_reg_prefix_optional = 1;
6884 reg_prefix_optional_seen = 1;
6885 break;
6886
6887 /* -V: SVR4 argument to print version ID. */
6888 case 'V':
6889 print_version_id ();
6890 break;
6891
6892 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
6893 should be emitted or not. FIXME: Not implemented. */
6894 case 'Q':
6895 break;
6896
6897 case OPTION_BITWISE_OR:
6898 {
6899 char *n, *t;
6900 const char *s;
6901
6902 n = (char *) xmalloc (strlen (m68k_comment_chars) + 1);
6903 t = n;
6904 for (s = m68k_comment_chars; *s != '\0'; s++)
6905 if (*s != '|')
6906 *t++ = *s;
6907 *t = '\0';
6908 m68k_comment_chars = n;
6909 }
6910 break;
6911
6912 case OPTION_BASE_SIZE_DEFAULT_16:
6913 m68k_index_width_default = SIZE_WORD;
6914 break;
6915
6916 case OPTION_BASE_SIZE_DEFAULT_32:
6917 m68k_index_width_default = SIZE_LONG;
6918 break;
6919
6920 case OPTION_DISP_SIZE_DEFAULT_16:
6921 m68k_rel32 = 0;
6922 m68k_rel32_from_cmdline = 1;
6923 break;
6924
6925 case OPTION_DISP_SIZE_DEFAULT_32:
6926 m68k_rel32 = 1;
6927 m68k_rel32_from_cmdline = 1;
6928 break;
6929
6930 default:
6931 return 0;
6932 }
6933
6934 return 1;
6935}
6936
6937void
6938md_show_usage (stream)
6939 FILE *stream;
6940{
bc805888 6941 fprintf (stream, _("\
252b5132
RH		 6942680X0 options:\n\
6943-l use 1 word for refs to undefined symbols [default 2]\n\
6944-m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060\n\
6945 | -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360\n\
6946 | -mcpu32 | -m5200\n\
6947 specify variant of 680X0 architecture [default 68020]\n\
6948-m68881 | -m68882 | -mno-68881 | -mno-68882\n\
6949 target has/lacks floating-point coprocessor\n\
6950 [default yes for 68020, 68030, and cpu32]\n"));
bc805888 6951 fprintf (stream, _("\
252b5132
RH		 6952-m68851 | -mno-68851\n\
6953 target has/lacks memory-management unit coprocessor\n\
6954 [default yes for 68020 and up]\n\
6955-pic, -k generate position independent code\n\
6956-S turn jbsr into jsr\n\
28e7409f 6957--pcrel never turn PC-relative branches into absolute jumps\n\
252b5132
RH		 6958--register-prefix-optional\n\
6959 recognize register names without prefix character\n\
6960--bitwise-or do not treat `|' as a comment character\n"));
6961 fprintf (stream, _("\
6962--base-size-default-16 base reg without size is 16 bits\n\
6963--base-size-default-32 base reg without size is 32 bits (default)\n\
6964--disp-size-default-16 displacement with unknown size is 16 bits\n\
6965--disp-size-default-32 displacement with unknown size is 32 bits (default)\n"));
6966}
6967\f
6968#ifdef TEST2
6969
6970/* TEST2: Test md_assemble() */
6971/* Warning, this routine probably doesn't work anymore */
6972
6973main ()
6974{
6975 struct m68k_it the_ins;
6976 char buf[120];
6977 char *cp;
6978 int n;
6979
6980 m68k_ip_begin ();
6981 for (;;)
6982 {
6983 if (!gets (buf) || !*buf)
6984 break;
6985 if (buf[0] == '|' || buf[1] == '.')
6986 continue;
6987 for (cp = buf; *cp; cp++)
6988 if (*cp == '\t')
6989 *cp = ' ';
6990 if (is_label (buf))
6991 continue;
6992 memset (&the_ins, '\0', sizeof (the_ins));
6993 m68k_ip (&the_ins, buf);
6994 if (the_ins.error)
6995 {
6996 printf (_("Error %s in %s\n"), the_ins.error, buf);
6997 }
6998 else
6999 {
7000 printf (_("Opcode(%d.%s): "), the_ins.numo, the_ins.args);
7001 for (n = 0; n < the_ins.numo; n++)
7002 printf (" 0x%x", the_ins.opcode[n] & 0xffff);
7003 printf (" ");
7004 print_the_insn (&the_ins.opcode[0], stdout);
7005 (void) putchar ('\n');
7006 }
7007 for (n = 0; n < strlen (the_ins.args) / 2; n++)
7008 {
7009 if (the_ins.operands[n].error)
7010 {
7011 printf ("op%d Error %s in %s\n", n, the_ins.operands[n].error, buf);
7012 continue;
7013 }
7014 printf ("mode %d, reg %d, ", the_ins.operands[n].mode, the_ins.operands[n].reg);
7015 if (the_ins.operands[n].b_const)
7016 printf ("Constant: '%.*s', ", 1 + the_ins.operands[n].e_const - the_ins.operands[n].b_const, the_ins.operands[n].b_const);
7017 printf ("ireg %d, isiz %d, imul %d, ", the_ins.operands[n].ireg, the_ins.operands[n].isiz, the_ins.operands[n].imul);
7018 if (the_ins.operands[n].b_iadd)
7019 printf ("Iadd: '%.*s',", 1 + the_ins.operands[n].e_iadd - the_ins.operands[n].b_iadd, the_ins.operands[n].b_iadd);
7020 (void) putchar ('\n');
7021 }
7022 }
7023 m68k_ip_end ();
7024 return 0;
7025}
7026
7027is_label (str)
7028 char *str;
7029{
7030 while (*str == ' ')
7031 str++;
7032 while (*str && *str != ' ')
7033 str++;
7034 if (str[-1] == ':' || str[1] == '=')
7035 return 1;
7036 return 0;
7037}
7038
7039#endif
7040
7041/* Possible states for relaxation:
7042
7043 0 0 branch offset byte (bra, etc)
7044 0 1 word
7045 0 2 long
7046
7047 1 0 indexed offsets byte a0@(32,d4:w:1) etc
7048 1 1 word
7049 1 2 long
7050
7051 2 0 two-offset index word-word a0@(32,d4)@(45) etc
7052 2 1 word-long
7053 2 2 long-word
7054 2 3 long-long
7055
7056 */
7057
7058/* We have no need to default values of symbols. */
7059
252b5132
RH		 7060symbolS *
7061md_undefined_symbol (name)
36823076 7062 char *name ATTRIBUTE_UNUSED;
252b5132
RH		 7063{
7064 return 0;
7065}
7066
7067/* Round up a section size to the appropriate boundary. */
7068valueT
7069md_section_align (segment, size)
36823076 7070 segT segment ATTRIBUTE_UNUSED;
252b5132
RH		 7071 valueT size;
7072{
7073#ifdef OBJ_AOUT
7074#ifdef BFD_ASSEMBLER
7075 /* For a.out, force the section size to be aligned. If we don't do
7076 this, BFD will align it for us, but it will not write out the
7077 final bytes of the section. This may be a bug in BFD, but it is
7078 easier to fix it here since that is how the other a.out targets
7079 work. */
7080 int align;
7081
7082 align = bfd_get_section_alignment (stdoutput, segment);
7083 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
7084#endif
7085#endif
7086
7087 return size;
7088}
7089
7090/* Exactly what point is a PC-relative offset relative TO?
7091 On the 68k, it is relative to the address of the first extension
7092 word. The difference between the addresses of the offset and the
92774660 7093 first extension word is stored in fx_pcrel_adjust. */
252b5132
RH		 7094long
7095md_pcrel_from (fixP)
7096 fixS *fixP;
7097{
7098 int adjust;
7099
7100 /* Because fx_pcrel_adjust is a char, and may be unsigned, we store
7101 -1 as 64. */
7102 adjust = fixP->fx_pcrel_adjust;
7103 if (adjust == 64)
7104 adjust = -1;
7105 return fixP->fx_where + fixP->fx_frag->fr_address - adjust;
7106}
7107
7108#ifndef BFD_ASSEMBLER
7109#ifdef OBJ_COFF
7110
252b5132
RH		 7111void
7112tc_coff_symbol_emit_hook (ignore)
8fce3f5e 7113 symbolS *ignore ATTRIBUTE_UNUSED;
252b5132
RH		 7114{
7115}
7116
7117int
7118tc_coff_sizemachdep (frag)
7119 fragS *frag;
7120{
7121 switch (frag->fr_subtype & 0x3)
7122 {
7123 case BYTE:
7124 return 1;
7125 case SHORT:
7126 return 2;
7127 case LONG:
7128 return 4;
7129 default:
7130 abort ();
7131 return 0;
7132 }
7133}
7134
7135#endif
7136#endif
0d96863f
CM		 7137#ifdef OBJ_ELF
7138void m68k_elf_final_processing()
7139{
7140 /* Set file-specific flags if this is a cpu32 processor */
7141 if (cpu_of_arch (current_architecture) & cpu32)
7142 elf_elfheader (stdoutput)->e_flags |= EF_CPU32;
7143}
7144#endif
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