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252b5132 | 1 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) |
a2c58332 | 2 | Copyright (C) 1994-2022 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 | 24 | #include "subsegs.h" |
75e21f08 | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/ppc.h" | |
ee67d69a | 30 | #include "elf/ppc64.h" |
5d6f4f16 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
85645aed TG |
34 | #ifdef OBJ_XCOFF |
35 | #include "coff/xcoff.h" | |
36 | #include "libxcoff.h" | |
37 | #endif | |
38 | ||
252b5132 RH |
39 | /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ |
40 | ||
41 | /* Tell the main code what the endianness is. */ | |
42 | extern int target_big_endian; | |
43 | ||
44 | /* Whether or not, we've set target_big_endian. */ | |
45 | static int set_target_endian = 0; | |
46 | ||
47 | /* Whether to use user friendly register names. */ | |
48 | #ifndef TARGET_REG_NAMES_P | |
5b7c81bd | 49 | #define TARGET_REG_NAMES_P false |
252b5132 | 50 | #endif |
252b5132 | 51 | |
0baf16f2 AM |
52 | /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST, |
53 | HIGHESTA. */ | |
54 | ||
55 | /* #lo(value) denotes the least significant 16 bits of the indicated. */ | |
56 | #define PPC_LO(v) ((v) & 0xffff) | |
57 | ||
58 | /* #hi(value) denotes bits 16 through 31 of the indicated value. */ | |
59 | #define PPC_HI(v) (((v) >> 16) & 0xffff) | |
60 | ||
61 | /* #ha(value) denotes the high adjusted value: bits 16 through 31 of | |
62 | the indicated value, compensating for #lo() being treated as a | |
63 | signed number. */ | |
15c1449b | 64 | #define PPC_HA(v) PPC_HI ((v) + 0x8000) |
0baf16f2 AM |
65 | |
66 | /* #higher(value) denotes bits 32 through 47 of the indicated value. */ | |
2a98c3a6 | 67 | #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff) |
0baf16f2 AM |
68 | |
69 | /* #highera(value) denotes bits 32 through 47 of the indicated value, | |
70 | compensating for #lo() being treated as a signed number. */ | |
15c1449b | 71 | #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000) |
0baf16f2 AM |
72 | |
73 | /* #highest(value) denotes bits 48 through 63 of the indicated value. */ | |
2a98c3a6 | 74 | #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff) |
0baf16f2 AM |
75 | |
76 | /* #highesta(value) denotes bits 48 through 63 of the indicated value, | |
15c1449b AM |
77 | compensating for #lo being treated as a signed number. */ |
78 | #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000) | |
0baf16f2 | 79 | |
f9c6b907 AM |
80 | #define SEX16(val) (((val) ^ 0x8000) - 0x8000) |
81 | ||
82 | /* For the time being on ppc64, don't report overflow on @h and @ha | |
83 | applied to constants. */ | |
84 | #define REPORT_OVERFLOW_HI 0 | |
0baf16f2 | 85 | |
5b7c81bd | 86 | static bool reg_names_p = TARGET_REG_NAMES_P; |
252b5132 | 87 | |
98027b10 AM |
88 | static void ppc_macro (char *, const struct powerpc_macro *); |
89 | static void ppc_byte (int); | |
0baf16f2 AM |
90 | |
91 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) | |
98027b10 AM |
92 | static void ppc_tc (int); |
93 | static void ppc_machine (int); | |
0baf16f2 | 94 | #endif |
252b5132 RH |
95 | |
96 | #ifdef OBJ_XCOFF | |
98027b10 AM |
97 | static void ppc_comm (int); |
98 | static void ppc_bb (int); | |
99 | static void ppc_bc (int); | |
100 | static void ppc_bf (int); | |
101 | static void ppc_biei (int); | |
102 | static void ppc_bs (int); | |
103 | static void ppc_eb (int); | |
104 | static void ppc_ec (int); | |
105 | static void ppc_ef (int); | |
106 | static void ppc_es (int); | |
107 | static void ppc_csect (int); | |
85645aed | 108 | static void ppc_dwsect (int); |
98027b10 | 109 | static void ppc_change_csect (symbolS *, offsetT); |
e86fc4a5 | 110 | static void ppc_file (int); |
98027b10 AM |
111 | static void ppc_function (int); |
112 | static void ppc_extern (int); | |
113 | static void ppc_lglobl (int); | |
c865e45b | 114 | static void ppc_ref (int); |
98027b10 AM |
115 | static void ppc_section (int); |
116 | static void ppc_named_section (int); | |
117 | static void ppc_stabx (int); | |
118 | static void ppc_rename (int); | |
119 | static void ppc_toc (int); | |
120 | static void ppc_xcoff_cons (int); | |
121 | static void ppc_vbyte (int); | |
252b5132 RH |
122 | #endif |
123 | ||
124 | #ifdef OBJ_ELF | |
98027b10 AM |
125 | static void ppc_elf_rdata (int); |
126 | static void ppc_elf_lcomm (int); | |
6911b7dc | 127 | static void ppc_elf_localentry (int); |
ee67d69a | 128 | static void ppc_elf_abiversion (int); |
005d79fd | 129 | static void ppc_elf_gnu_attribute (int); |
252b5132 | 130 | #endif |
252b5132 RH |
131 | \f |
132 | /* Generic assembler global variables which must be defined by all | |
133 | targets. */ | |
134 | ||
135 | #ifdef OBJ_ELF | |
136 | /* This string holds the chars that always start a comment. If the | |
137 | pre-processor is disabled, these aren't very useful. The macro | |
138 | tc_comment_chars points to this. We use this, rather than the | |
139 | usual comment_chars, so that we can switch for Solaris conventions. */ | |
140 | static const char ppc_solaris_comment_chars[] = "#!"; | |
141 | static const char ppc_eabi_comment_chars[] = "#"; | |
142 | ||
143 | #ifdef TARGET_SOLARIS_COMMENT | |
144 | const char *ppc_comment_chars = ppc_solaris_comment_chars; | |
145 | #else | |
146 | const char *ppc_comment_chars = ppc_eabi_comment_chars; | |
147 | #endif | |
148 | #else | |
149 | const char comment_chars[] = "#"; | |
150 | #endif | |
151 | ||
152 | /* Characters which start a comment at the beginning of a line. */ | |
153 | const char line_comment_chars[] = "#"; | |
154 | ||
155 | /* Characters which may be used to separate multiple commands on a | |
156 | single line. */ | |
157 | const char line_separator_chars[] = ";"; | |
158 | ||
159 | /* Characters which are used to indicate an exponent in a floating | |
160 | point number. */ | |
161 | const char EXP_CHARS[] = "eE"; | |
162 | ||
163 | /* Characters which mean that a number is a floating point constant, | |
164 | as in 0d1.0. */ | |
165 | const char FLT_CHARS[] = "dD"; | |
5ce8663f | 166 | |
5e02f92e | 167 | /* Anything that can start an operand needs to be mentioned here, |
ac805826 | 168 | to stop the input scrubber eating whitespace. */ |
5e02f92e | 169 | const char ppc_symbol_chars[] = "%["; |
75e21f08 JJ |
170 | |
171 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
172 | int ppc_cie_data_alignment; | |
783de163 | 173 | |
8fbf7334 JL |
174 | /* The dwarf2 minimum instruction length. */ |
175 | int ppc_dwarf2_line_min_insn_length; | |
176 | ||
cef4f754 AM |
177 | /* More than this number of nops in an alignment op gets a branch |
178 | instead. */ | |
179 | unsigned long nop_limit = 4; | |
180 | ||
783de163 AM |
181 | /* The type of processor we are assembling for. This is one or more |
182 | of the PPC_OPCODE flags defined in opcode/ppc.h. */ | |
fa452fa6 | 183 | ppc_cpu_t ppc_cpu = 0; |
776fc418 | 184 | ppc_cpu_t sticky = 0; |
01efc3af | 185 | |
ee67d69a AM |
186 | /* Value for ELF e_flags EF_PPC64_ABI. */ |
187 | unsigned int ppc_abiversion = 0; | |
188 | ||
05f7541e | 189 | #ifdef OBJ_ELF |
01efc3af | 190 | /* Flags set on encountering toc relocs. */ |
4f2a7b51 | 191 | static enum { |
01efc3af AM |
192 | has_large_toc_reloc = 1, |
193 | has_small_toc_reloc = 2 | |
194 | } toc_reloc_types; | |
05f7541e | 195 | #endif |
bf7279d5 AM |
196 | |
197 | /* Warn on emitting data to code sections. */ | |
198 | int warn_476; | |
0f873fd5 | 199 | uint64_t last_insn; |
bf7279d5 AM |
200 | segT last_seg; |
201 | subsegT last_subseg; | |
252b5132 RH |
202 | \f |
203 | /* The target specific pseudo-ops which we support. */ | |
204 | ||
205 | const pseudo_typeS md_pseudo_table[] = | |
206 | { | |
207 | /* Pseudo-ops which must be overridden. */ | |
208 | { "byte", ppc_byte, 0 }, | |
209 | ||
210 | #ifdef OBJ_XCOFF | |
211 | /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these | |
212 | legitimately belong in the obj-*.c file. However, XCOFF is based | |
213 | on COFF, and is only implemented for the RS/6000. We just use | |
214 | obj-coff.c, and add what we need here. */ | |
215 | { "comm", ppc_comm, 0 }, | |
216 | { "lcomm", ppc_comm, 1 }, | |
217 | { "bb", ppc_bb, 0 }, | |
218 | { "bc", ppc_bc, 0 }, | |
219 | { "bf", ppc_bf, 0 }, | |
220 | { "bi", ppc_biei, 0 }, | |
221 | { "bs", ppc_bs, 0 }, | |
222 | { "csect", ppc_csect, 0 }, | |
85645aed | 223 | { "dwsect", ppc_dwsect, 0 }, |
252b5132 RH |
224 | { "data", ppc_section, 'd' }, |
225 | { "eb", ppc_eb, 0 }, | |
226 | { "ec", ppc_ec, 0 }, | |
227 | { "ef", ppc_ef, 0 }, | |
228 | { "ei", ppc_biei, 1 }, | |
229 | { "es", ppc_es, 0 }, | |
230 | { "extern", ppc_extern, 0 }, | |
e86fc4a5 | 231 | { "file", ppc_file, 0 }, |
252b5132 RH |
232 | { "function", ppc_function, 0 }, |
233 | { "lglobl", ppc_lglobl, 0 }, | |
c865e45b | 234 | { "ref", ppc_ref, 0 }, |
252b5132 RH |
235 | { "rename", ppc_rename, 0 }, |
236 | { "section", ppc_named_section, 0 }, | |
237 | { "stabx", ppc_stabx, 0 }, | |
238 | { "text", ppc_section, 't' }, | |
239 | { "toc", ppc_toc, 0 }, | |
240 | { "long", ppc_xcoff_cons, 2 }, | |
7f6d05e8 | 241 | { "llong", ppc_xcoff_cons, 3 }, |
252b5132 RH |
242 | { "word", ppc_xcoff_cons, 1 }, |
243 | { "short", ppc_xcoff_cons, 1 }, | |
244 | { "vbyte", ppc_vbyte, 0 }, | |
245 | #endif | |
246 | ||
247 | #ifdef OBJ_ELF | |
62ebcb5c | 248 | { "llong", cons, 8 }, |
252b5132 RH |
249 | { "rdata", ppc_elf_rdata, 0 }, |
250 | { "rodata", ppc_elf_rdata, 0 }, | |
251 | { "lcomm", ppc_elf_lcomm, 0 }, | |
6911b7dc | 252 | { "localentry", ppc_elf_localentry, 0 }, |
ee67d69a | 253 | { "abiversion", ppc_elf_abiversion, 0 }, |
005d79fd | 254 | { "gnu_attribute", ppc_elf_gnu_attribute, 0}, |
252b5132 RH |
255 | #endif |
256 | ||
0baf16f2 | 257 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 | 258 | { "tc", ppc_tc, 0 }, |
0baf16f2 AM |
259 | { "machine", ppc_machine, 0 }, |
260 | #endif | |
252b5132 RH |
261 | |
262 | { NULL, NULL, 0 } | |
263 | }; | |
264 | ||
265 | \f | |
99a814a1 AM |
266 | /* Predefined register names if -mregnames (or default for Windows NT). |
267 | In general, there are lots of them, in an attempt to be compatible | |
268 | with a number of other Windows NT assemblers. */ | |
252b5132 RH |
269 | |
270 | /* Structure to hold information about predefined registers. */ | |
271 | struct pd_reg | |
272 | { | |
e0471c16 | 273 | const char *name; |
7e0de605 AM |
274 | unsigned short value; |
275 | unsigned short flags; | |
252b5132 RH |
276 | }; |
277 | ||
278 | /* List of registers that are pre-defined: | |
279 | ||
280 | Each general register has predefined names of the form: | |
281 | 1. r<reg_num> which has the value <reg_num>. | |
282 | 2. r.<reg_num> which has the value <reg_num>. | |
283 | ||
252b5132 RH |
284 | Each floating point register has predefined names of the form: |
285 | 1. f<reg_num> which has the value <reg_num>. | |
286 | 2. f.<reg_num> which has the value <reg_num>. | |
287 | ||
7a899fff C |
288 | Each vector unit register has predefined names of the form: |
289 | 1. v<reg_num> which has the value <reg_num>. | |
290 | 2. v.<reg_num> which has the value <reg_num>. | |
291 | ||
252b5132 RH |
292 | Each condition register has predefined names of the form: |
293 | 1. cr<reg_num> which has the value <reg_num>. | |
294 | 2. cr.<reg_num> which has the value <reg_num>. | |
295 | ||
296 | There are individual registers as well: | |
297 | sp or r.sp has the value 1 | |
298 | rtoc or r.toc has the value 2 | |
252b5132 RH |
299 | xer has the value 1 |
300 | lr has the value 8 | |
301 | ctr has the value 9 | |
252b5132 RH |
302 | dar has the value 19 |
303 | dsisr has the value 18 | |
304 | dec has the value 22 | |
305 | sdr1 has the value 25 | |
306 | srr0 has the value 26 | |
307 | srr1 has the value 27 | |
308 | ||
81d4177b | 309 | The table is sorted. Suitable for searching by a binary search. */ |
252b5132 RH |
310 | |
311 | static const struct pd_reg pre_defined_registers[] = | |
312 | { | |
aa3c112f AM |
313 | /* VSX accumulators. */ |
314 | { "a0", 0, PPC_OPERAND_ACC }, | |
315 | { "a1", 1, PPC_OPERAND_ACC }, | |
316 | { "a2", 2, PPC_OPERAND_ACC }, | |
317 | { "a3", 3, PPC_OPERAND_ACC }, | |
318 | { "a4", 4, PPC_OPERAND_ACC }, | |
319 | { "a5", 5, PPC_OPERAND_ACC }, | |
320 | { "a6", 6, PPC_OPERAND_ACC }, | |
321 | { "a7", 7, PPC_OPERAND_ACC }, | |
322 | ||
7e0de605 AM |
323 | /* Condition Registers */ |
324 | { "cr.0", 0, PPC_OPERAND_CR_REG }, | |
325 | { "cr.1", 1, PPC_OPERAND_CR_REG }, | |
326 | { "cr.2", 2, PPC_OPERAND_CR_REG }, | |
327 | { "cr.3", 3, PPC_OPERAND_CR_REG }, | |
328 | { "cr.4", 4, PPC_OPERAND_CR_REG }, | |
329 | { "cr.5", 5, PPC_OPERAND_CR_REG }, | |
330 | { "cr.6", 6, PPC_OPERAND_CR_REG }, | |
331 | { "cr.7", 7, PPC_OPERAND_CR_REG }, | |
332 | ||
333 | { "cr0", 0, PPC_OPERAND_CR_REG }, | |
334 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
335 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
336 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
337 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
338 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
339 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
340 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
341 | ||
342 | { "ctr", 9, PPC_OPERAND_SPR }, | |
343 | { "dar", 19, PPC_OPERAND_SPR }, | |
344 | { "dec", 22, PPC_OPERAND_SPR }, | |
345 | { "dsisr", 18, PPC_OPERAND_SPR }, | |
346 | ||
347 | /* Floating point registers */ | |
348 | { "f.0", 0, PPC_OPERAND_FPR }, | |
349 | { "f.1", 1, PPC_OPERAND_FPR }, | |
350 | { "f.10", 10, PPC_OPERAND_FPR }, | |
351 | { "f.11", 11, PPC_OPERAND_FPR }, | |
352 | { "f.12", 12, PPC_OPERAND_FPR }, | |
353 | { "f.13", 13, PPC_OPERAND_FPR }, | |
354 | { "f.14", 14, PPC_OPERAND_FPR }, | |
355 | { "f.15", 15, PPC_OPERAND_FPR }, | |
356 | { "f.16", 16, PPC_OPERAND_FPR }, | |
357 | { "f.17", 17, PPC_OPERAND_FPR }, | |
358 | { "f.18", 18, PPC_OPERAND_FPR }, | |
359 | { "f.19", 19, PPC_OPERAND_FPR }, | |
360 | { "f.2", 2, PPC_OPERAND_FPR }, | |
361 | { "f.20", 20, PPC_OPERAND_FPR }, | |
362 | { "f.21", 21, PPC_OPERAND_FPR }, | |
363 | { "f.22", 22, PPC_OPERAND_FPR }, | |
364 | { "f.23", 23, PPC_OPERAND_FPR }, | |
365 | { "f.24", 24, PPC_OPERAND_FPR }, | |
366 | { "f.25", 25, PPC_OPERAND_FPR }, | |
367 | { "f.26", 26, PPC_OPERAND_FPR }, | |
368 | { "f.27", 27, PPC_OPERAND_FPR }, | |
369 | { "f.28", 28, PPC_OPERAND_FPR }, | |
370 | { "f.29", 29, PPC_OPERAND_FPR }, | |
371 | { "f.3", 3, PPC_OPERAND_FPR }, | |
372 | { "f.30", 30, PPC_OPERAND_FPR }, | |
373 | { "f.31", 31, PPC_OPERAND_FPR }, | |
374 | { "f.32", 32, PPC_OPERAND_VSR }, | |
375 | { "f.33", 33, PPC_OPERAND_VSR }, | |
376 | { "f.34", 34, PPC_OPERAND_VSR }, | |
377 | { "f.35", 35, PPC_OPERAND_VSR }, | |
378 | { "f.36", 36, PPC_OPERAND_VSR }, | |
379 | { "f.37", 37, PPC_OPERAND_VSR }, | |
380 | { "f.38", 38, PPC_OPERAND_VSR }, | |
381 | { "f.39", 39, PPC_OPERAND_VSR }, | |
382 | { "f.4", 4, PPC_OPERAND_FPR }, | |
383 | { "f.40", 40, PPC_OPERAND_VSR }, | |
384 | { "f.41", 41, PPC_OPERAND_VSR }, | |
385 | { "f.42", 42, PPC_OPERAND_VSR }, | |
386 | { "f.43", 43, PPC_OPERAND_VSR }, | |
387 | { "f.44", 44, PPC_OPERAND_VSR }, | |
388 | { "f.45", 45, PPC_OPERAND_VSR }, | |
389 | { "f.46", 46, PPC_OPERAND_VSR }, | |
390 | { "f.47", 47, PPC_OPERAND_VSR }, | |
391 | { "f.48", 48, PPC_OPERAND_VSR }, | |
392 | { "f.49", 49, PPC_OPERAND_VSR }, | |
393 | { "f.5", 5, PPC_OPERAND_FPR }, | |
394 | { "f.50", 50, PPC_OPERAND_VSR }, | |
395 | { "f.51", 51, PPC_OPERAND_VSR }, | |
396 | { "f.52", 52, PPC_OPERAND_VSR }, | |
397 | { "f.53", 53, PPC_OPERAND_VSR }, | |
398 | { "f.54", 54, PPC_OPERAND_VSR }, | |
399 | { "f.55", 55, PPC_OPERAND_VSR }, | |
400 | { "f.56", 56, PPC_OPERAND_VSR }, | |
401 | { "f.57", 57, PPC_OPERAND_VSR }, | |
402 | { "f.58", 58, PPC_OPERAND_VSR }, | |
403 | { "f.59", 59, PPC_OPERAND_VSR }, | |
404 | { "f.6", 6, PPC_OPERAND_FPR }, | |
405 | { "f.60", 60, PPC_OPERAND_VSR }, | |
406 | { "f.61", 61, PPC_OPERAND_VSR }, | |
407 | { "f.62", 62, PPC_OPERAND_VSR }, | |
408 | { "f.63", 63, PPC_OPERAND_VSR }, | |
409 | { "f.7", 7, PPC_OPERAND_FPR }, | |
410 | { "f.8", 8, PPC_OPERAND_FPR }, | |
411 | { "f.9", 9, PPC_OPERAND_FPR }, | |
412 | ||
413 | { "f0", 0, PPC_OPERAND_FPR }, | |
414 | { "f1", 1, PPC_OPERAND_FPR }, | |
415 | { "f10", 10, PPC_OPERAND_FPR }, | |
416 | { "f11", 11, PPC_OPERAND_FPR }, | |
417 | { "f12", 12, PPC_OPERAND_FPR }, | |
418 | { "f13", 13, PPC_OPERAND_FPR }, | |
419 | { "f14", 14, PPC_OPERAND_FPR }, | |
420 | { "f15", 15, PPC_OPERAND_FPR }, | |
421 | { "f16", 16, PPC_OPERAND_FPR }, | |
422 | { "f17", 17, PPC_OPERAND_FPR }, | |
423 | { "f18", 18, PPC_OPERAND_FPR }, | |
424 | { "f19", 19, PPC_OPERAND_FPR }, | |
425 | { "f2", 2, PPC_OPERAND_FPR }, | |
426 | { "f20", 20, PPC_OPERAND_FPR }, | |
427 | { "f21", 21, PPC_OPERAND_FPR }, | |
428 | { "f22", 22, PPC_OPERAND_FPR }, | |
429 | { "f23", 23, PPC_OPERAND_FPR }, | |
430 | { "f24", 24, PPC_OPERAND_FPR }, | |
431 | { "f25", 25, PPC_OPERAND_FPR }, | |
432 | { "f26", 26, PPC_OPERAND_FPR }, | |
433 | { "f27", 27, PPC_OPERAND_FPR }, | |
434 | { "f28", 28, PPC_OPERAND_FPR }, | |
435 | { "f29", 29, PPC_OPERAND_FPR }, | |
436 | { "f3", 3, PPC_OPERAND_FPR }, | |
437 | { "f30", 30, PPC_OPERAND_FPR }, | |
438 | { "f31", 31, PPC_OPERAND_FPR }, | |
439 | { "f32", 32, PPC_OPERAND_VSR }, | |
440 | { "f33", 33, PPC_OPERAND_VSR }, | |
441 | { "f34", 34, PPC_OPERAND_VSR }, | |
442 | { "f35", 35, PPC_OPERAND_VSR }, | |
443 | { "f36", 36, PPC_OPERAND_VSR }, | |
444 | { "f37", 37, PPC_OPERAND_VSR }, | |
445 | { "f38", 38, PPC_OPERAND_VSR }, | |
446 | { "f39", 39, PPC_OPERAND_VSR }, | |
447 | { "f4", 4, PPC_OPERAND_FPR }, | |
448 | { "f40", 40, PPC_OPERAND_VSR }, | |
449 | { "f41", 41, PPC_OPERAND_VSR }, | |
450 | { "f42", 42, PPC_OPERAND_VSR }, | |
451 | { "f43", 43, PPC_OPERAND_VSR }, | |
452 | { "f44", 44, PPC_OPERAND_VSR }, | |
453 | { "f45", 45, PPC_OPERAND_VSR }, | |
454 | { "f46", 46, PPC_OPERAND_VSR }, | |
455 | { "f47", 47, PPC_OPERAND_VSR }, | |
456 | { "f48", 48, PPC_OPERAND_VSR }, | |
457 | { "f49", 49, PPC_OPERAND_VSR }, | |
458 | { "f5", 5, PPC_OPERAND_FPR }, | |
459 | { "f50", 50, PPC_OPERAND_VSR }, | |
460 | { "f51", 51, PPC_OPERAND_VSR }, | |
461 | { "f52", 52, PPC_OPERAND_VSR }, | |
462 | { "f53", 53, PPC_OPERAND_VSR }, | |
463 | { "f54", 54, PPC_OPERAND_VSR }, | |
464 | { "f55", 55, PPC_OPERAND_VSR }, | |
465 | { "f56", 56, PPC_OPERAND_VSR }, | |
466 | { "f57", 57, PPC_OPERAND_VSR }, | |
467 | { "f58", 58, PPC_OPERAND_VSR }, | |
468 | { "f59", 59, PPC_OPERAND_VSR }, | |
469 | { "f6", 6, PPC_OPERAND_FPR }, | |
470 | { "f60", 60, PPC_OPERAND_VSR }, | |
471 | { "f61", 61, PPC_OPERAND_VSR }, | |
472 | { "f62", 62, PPC_OPERAND_VSR }, | |
473 | { "f63", 63, PPC_OPERAND_VSR }, | |
474 | { "f7", 7, PPC_OPERAND_FPR }, | |
475 | { "f8", 8, PPC_OPERAND_FPR }, | |
476 | { "f9", 9, PPC_OPERAND_FPR }, | |
252b5132 | 477 | |
c3d65c1c | 478 | /* Quantization registers used with pair single instructions. */ |
7e0de605 AM |
479 | { "gqr.0", 0, PPC_OPERAND_GQR }, |
480 | { "gqr.1", 1, PPC_OPERAND_GQR }, | |
481 | { "gqr.2", 2, PPC_OPERAND_GQR }, | |
482 | { "gqr.3", 3, PPC_OPERAND_GQR }, | |
483 | { "gqr.4", 4, PPC_OPERAND_GQR }, | |
484 | { "gqr.5", 5, PPC_OPERAND_GQR }, | |
485 | { "gqr.6", 6, PPC_OPERAND_GQR }, | |
486 | { "gqr.7", 7, PPC_OPERAND_GQR }, | |
487 | { "gqr0", 0, PPC_OPERAND_GQR }, | |
488 | { "gqr1", 1, PPC_OPERAND_GQR }, | |
489 | { "gqr2", 2, PPC_OPERAND_GQR }, | |
490 | { "gqr3", 3, PPC_OPERAND_GQR }, | |
491 | { "gqr4", 4, PPC_OPERAND_GQR }, | |
492 | { "gqr5", 5, PPC_OPERAND_GQR }, | |
493 | { "gqr6", 6, PPC_OPERAND_GQR }, | |
494 | { "gqr7", 7, PPC_OPERAND_GQR }, | |
495 | ||
496 | { "lr", 8, PPC_OPERAND_SPR }, | |
497 | ||
498 | /* General Purpose Registers */ | |
499 | { "r.0", 0, PPC_OPERAND_GPR }, | |
500 | { "r.1", 1, PPC_OPERAND_GPR }, | |
501 | { "r.10", 10, PPC_OPERAND_GPR }, | |
502 | { "r.11", 11, PPC_OPERAND_GPR }, | |
503 | { "r.12", 12, PPC_OPERAND_GPR }, | |
504 | { "r.13", 13, PPC_OPERAND_GPR }, | |
505 | { "r.14", 14, PPC_OPERAND_GPR }, | |
506 | { "r.15", 15, PPC_OPERAND_GPR }, | |
507 | { "r.16", 16, PPC_OPERAND_GPR }, | |
508 | { "r.17", 17, PPC_OPERAND_GPR }, | |
509 | { "r.18", 18, PPC_OPERAND_GPR }, | |
510 | { "r.19", 19, PPC_OPERAND_GPR }, | |
511 | { "r.2", 2, PPC_OPERAND_GPR }, | |
512 | { "r.20", 20, PPC_OPERAND_GPR }, | |
513 | { "r.21", 21, PPC_OPERAND_GPR }, | |
514 | { "r.22", 22, PPC_OPERAND_GPR }, | |
515 | { "r.23", 23, PPC_OPERAND_GPR }, | |
516 | { "r.24", 24, PPC_OPERAND_GPR }, | |
517 | { "r.25", 25, PPC_OPERAND_GPR }, | |
518 | { "r.26", 26, PPC_OPERAND_GPR }, | |
519 | { "r.27", 27, PPC_OPERAND_GPR }, | |
520 | { "r.28", 28, PPC_OPERAND_GPR }, | |
521 | { "r.29", 29, PPC_OPERAND_GPR }, | |
522 | { "r.3", 3, PPC_OPERAND_GPR }, | |
523 | { "r.30", 30, PPC_OPERAND_GPR }, | |
524 | { "r.31", 31, PPC_OPERAND_GPR }, | |
525 | { "r.4", 4, PPC_OPERAND_GPR }, | |
526 | { "r.5", 5, PPC_OPERAND_GPR }, | |
527 | { "r.6", 6, PPC_OPERAND_GPR }, | |
528 | { "r.7", 7, PPC_OPERAND_GPR }, | |
529 | { "r.8", 8, PPC_OPERAND_GPR }, | |
530 | { "r.9", 9, PPC_OPERAND_GPR }, | |
531 | ||
532 | { "r.sp", 1, PPC_OPERAND_GPR }, | |
533 | ||
534 | { "r.toc", 2, PPC_OPERAND_GPR }, | |
535 | ||
536 | { "r0", 0, PPC_OPERAND_GPR }, | |
537 | { "r1", 1, PPC_OPERAND_GPR }, | |
538 | { "r10", 10, PPC_OPERAND_GPR }, | |
539 | { "r11", 11, PPC_OPERAND_GPR }, | |
540 | { "r12", 12, PPC_OPERAND_GPR }, | |
541 | { "r13", 13, PPC_OPERAND_GPR }, | |
542 | { "r14", 14, PPC_OPERAND_GPR }, | |
543 | { "r15", 15, PPC_OPERAND_GPR }, | |
544 | { "r16", 16, PPC_OPERAND_GPR }, | |
545 | { "r17", 17, PPC_OPERAND_GPR }, | |
546 | { "r18", 18, PPC_OPERAND_GPR }, | |
547 | { "r19", 19, PPC_OPERAND_GPR }, | |
548 | { "r2", 2, PPC_OPERAND_GPR }, | |
549 | { "r20", 20, PPC_OPERAND_GPR }, | |
550 | { "r21", 21, PPC_OPERAND_GPR }, | |
551 | { "r22", 22, PPC_OPERAND_GPR }, | |
552 | { "r23", 23, PPC_OPERAND_GPR }, | |
553 | { "r24", 24, PPC_OPERAND_GPR }, | |
554 | { "r25", 25, PPC_OPERAND_GPR }, | |
555 | { "r26", 26, PPC_OPERAND_GPR }, | |
556 | { "r27", 27, PPC_OPERAND_GPR }, | |
557 | { "r28", 28, PPC_OPERAND_GPR }, | |
558 | { "r29", 29, PPC_OPERAND_GPR }, | |
559 | { "r3", 3, PPC_OPERAND_GPR }, | |
560 | { "r30", 30, PPC_OPERAND_GPR }, | |
561 | { "r31", 31, PPC_OPERAND_GPR }, | |
562 | { "r4", 4, PPC_OPERAND_GPR }, | |
563 | { "r5", 5, PPC_OPERAND_GPR }, | |
564 | { "r6", 6, PPC_OPERAND_GPR }, | |
565 | { "r7", 7, PPC_OPERAND_GPR }, | |
566 | { "r8", 8, PPC_OPERAND_GPR }, | |
567 | { "r9", 9, PPC_OPERAND_GPR }, | |
568 | ||
569 | { "rtoc", 2, PPC_OPERAND_GPR }, | |
570 | ||
571 | { "sdr1", 25, PPC_OPERAND_SPR }, | |
572 | ||
573 | { "sp", 1, PPC_OPERAND_GPR }, | |
574 | ||
575 | { "srr0", 26, PPC_OPERAND_SPR }, | |
576 | { "srr1", 27, PPC_OPERAND_SPR }, | |
577 | ||
578 | /* Vector (Altivec/VMX) registers */ | |
579 | { "v.0", 0, PPC_OPERAND_VR }, | |
580 | { "v.1", 1, PPC_OPERAND_VR }, | |
581 | { "v.10", 10, PPC_OPERAND_VR }, | |
582 | { "v.11", 11, PPC_OPERAND_VR }, | |
583 | { "v.12", 12, PPC_OPERAND_VR }, | |
584 | { "v.13", 13, PPC_OPERAND_VR }, | |
585 | { "v.14", 14, PPC_OPERAND_VR }, | |
586 | { "v.15", 15, PPC_OPERAND_VR }, | |
587 | { "v.16", 16, PPC_OPERAND_VR }, | |
588 | { "v.17", 17, PPC_OPERAND_VR }, | |
589 | { "v.18", 18, PPC_OPERAND_VR }, | |
590 | { "v.19", 19, PPC_OPERAND_VR }, | |
591 | { "v.2", 2, PPC_OPERAND_VR }, | |
592 | { "v.20", 20, PPC_OPERAND_VR }, | |
593 | { "v.21", 21, PPC_OPERAND_VR }, | |
594 | { "v.22", 22, PPC_OPERAND_VR }, | |
595 | { "v.23", 23, PPC_OPERAND_VR }, | |
596 | { "v.24", 24, PPC_OPERAND_VR }, | |
597 | { "v.25", 25, PPC_OPERAND_VR }, | |
598 | { "v.26", 26, PPC_OPERAND_VR }, | |
599 | { "v.27", 27, PPC_OPERAND_VR }, | |
600 | { "v.28", 28, PPC_OPERAND_VR }, | |
601 | { "v.29", 29, PPC_OPERAND_VR }, | |
602 | { "v.3", 3, PPC_OPERAND_VR }, | |
603 | { "v.30", 30, PPC_OPERAND_VR }, | |
604 | { "v.31", 31, PPC_OPERAND_VR }, | |
605 | { "v.4", 4, PPC_OPERAND_VR }, | |
606 | { "v.5", 5, PPC_OPERAND_VR }, | |
607 | { "v.6", 6, PPC_OPERAND_VR }, | |
608 | { "v.7", 7, PPC_OPERAND_VR }, | |
609 | { "v.8", 8, PPC_OPERAND_VR }, | |
610 | { "v.9", 9, PPC_OPERAND_VR }, | |
611 | ||
612 | { "v0", 0, PPC_OPERAND_VR }, | |
613 | { "v1", 1, PPC_OPERAND_VR }, | |
614 | { "v10", 10, PPC_OPERAND_VR }, | |
615 | { "v11", 11, PPC_OPERAND_VR }, | |
616 | { "v12", 12, PPC_OPERAND_VR }, | |
617 | { "v13", 13, PPC_OPERAND_VR }, | |
618 | { "v14", 14, PPC_OPERAND_VR }, | |
619 | { "v15", 15, PPC_OPERAND_VR }, | |
620 | { "v16", 16, PPC_OPERAND_VR }, | |
621 | { "v17", 17, PPC_OPERAND_VR }, | |
622 | { "v18", 18, PPC_OPERAND_VR }, | |
623 | { "v19", 19, PPC_OPERAND_VR }, | |
624 | { "v2", 2, PPC_OPERAND_VR }, | |
625 | { "v20", 20, PPC_OPERAND_VR }, | |
626 | { "v21", 21, PPC_OPERAND_VR }, | |
627 | { "v22", 22, PPC_OPERAND_VR }, | |
628 | { "v23", 23, PPC_OPERAND_VR }, | |
629 | { "v24", 24, PPC_OPERAND_VR }, | |
630 | { "v25", 25, PPC_OPERAND_VR }, | |
631 | { "v26", 26, PPC_OPERAND_VR }, | |
632 | { "v27", 27, PPC_OPERAND_VR }, | |
633 | { "v28", 28, PPC_OPERAND_VR }, | |
634 | { "v29", 29, PPC_OPERAND_VR }, | |
635 | { "v3", 3, PPC_OPERAND_VR }, | |
636 | { "v30", 30, PPC_OPERAND_VR }, | |
637 | { "v31", 31, PPC_OPERAND_VR }, | |
638 | { "v4", 4, PPC_OPERAND_VR }, | |
639 | { "v5", 5, PPC_OPERAND_VR }, | |
640 | { "v6", 6, PPC_OPERAND_VR }, | |
641 | { "v7", 7, PPC_OPERAND_VR }, | |
642 | { "v8", 8, PPC_OPERAND_VR }, | |
643 | { "v9", 9, PPC_OPERAND_VR }, | |
644 | ||
645 | /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
646 | { "vs.0", 0, PPC_OPERAND_VSR }, | |
647 | { "vs.1", 1, PPC_OPERAND_VSR }, | |
648 | { "vs.10", 10, PPC_OPERAND_VSR }, | |
649 | { "vs.11", 11, PPC_OPERAND_VSR }, | |
650 | { "vs.12", 12, PPC_OPERAND_VSR }, | |
651 | { "vs.13", 13, PPC_OPERAND_VSR }, | |
652 | { "vs.14", 14, PPC_OPERAND_VSR }, | |
653 | { "vs.15", 15, PPC_OPERAND_VSR }, | |
654 | { "vs.16", 16, PPC_OPERAND_VSR }, | |
655 | { "vs.17", 17, PPC_OPERAND_VSR }, | |
656 | { "vs.18", 18, PPC_OPERAND_VSR }, | |
657 | { "vs.19", 19, PPC_OPERAND_VSR }, | |
658 | { "vs.2", 2, PPC_OPERAND_VSR }, | |
659 | { "vs.20", 20, PPC_OPERAND_VSR }, | |
660 | { "vs.21", 21, PPC_OPERAND_VSR }, | |
661 | { "vs.22", 22, PPC_OPERAND_VSR }, | |
662 | { "vs.23", 23, PPC_OPERAND_VSR }, | |
663 | { "vs.24", 24, PPC_OPERAND_VSR }, | |
664 | { "vs.25", 25, PPC_OPERAND_VSR }, | |
665 | { "vs.26", 26, PPC_OPERAND_VSR }, | |
666 | { "vs.27", 27, PPC_OPERAND_VSR }, | |
667 | { "vs.28", 28, PPC_OPERAND_VSR }, | |
668 | { "vs.29", 29, PPC_OPERAND_VSR }, | |
669 | { "vs.3", 3, PPC_OPERAND_VSR }, | |
670 | { "vs.30", 30, PPC_OPERAND_VSR }, | |
671 | { "vs.31", 31, PPC_OPERAND_VSR }, | |
672 | { "vs.32", 32, PPC_OPERAND_VSR }, | |
673 | { "vs.33", 33, PPC_OPERAND_VSR }, | |
674 | { "vs.34", 34, PPC_OPERAND_VSR }, | |
675 | { "vs.35", 35, PPC_OPERAND_VSR }, | |
676 | { "vs.36", 36, PPC_OPERAND_VSR }, | |
677 | { "vs.37", 37, PPC_OPERAND_VSR }, | |
678 | { "vs.38", 38, PPC_OPERAND_VSR }, | |
679 | { "vs.39", 39, PPC_OPERAND_VSR }, | |
680 | { "vs.4", 4, PPC_OPERAND_VSR }, | |
681 | { "vs.40", 40, PPC_OPERAND_VSR }, | |
682 | { "vs.41", 41, PPC_OPERAND_VSR }, | |
683 | { "vs.42", 42, PPC_OPERAND_VSR }, | |
684 | { "vs.43", 43, PPC_OPERAND_VSR }, | |
685 | { "vs.44", 44, PPC_OPERAND_VSR }, | |
686 | { "vs.45", 45, PPC_OPERAND_VSR }, | |
687 | { "vs.46", 46, PPC_OPERAND_VSR }, | |
688 | { "vs.47", 47, PPC_OPERAND_VSR }, | |
689 | { "vs.48", 48, PPC_OPERAND_VSR }, | |
690 | { "vs.49", 49, PPC_OPERAND_VSR }, | |
691 | { "vs.5", 5, PPC_OPERAND_VSR }, | |
692 | { "vs.50", 50, PPC_OPERAND_VSR }, | |
693 | { "vs.51", 51, PPC_OPERAND_VSR }, | |
694 | { "vs.52", 52, PPC_OPERAND_VSR }, | |
695 | { "vs.53", 53, PPC_OPERAND_VSR }, | |
696 | { "vs.54", 54, PPC_OPERAND_VSR }, | |
697 | { "vs.55", 55, PPC_OPERAND_VSR }, | |
698 | { "vs.56", 56, PPC_OPERAND_VSR }, | |
699 | { "vs.57", 57, PPC_OPERAND_VSR }, | |
700 | { "vs.58", 58, PPC_OPERAND_VSR }, | |
701 | { "vs.59", 59, PPC_OPERAND_VSR }, | |
702 | { "vs.6", 6, PPC_OPERAND_VSR }, | |
703 | { "vs.60", 60, PPC_OPERAND_VSR }, | |
704 | { "vs.61", 61, PPC_OPERAND_VSR }, | |
705 | { "vs.62", 62, PPC_OPERAND_VSR }, | |
706 | { "vs.63", 63, PPC_OPERAND_VSR }, | |
707 | { "vs.7", 7, PPC_OPERAND_VSR }, | |
708 | { "vs.8", 8, PPC_OPERAND_VSR }, | |
709 | { "vs.9", 9, PPC_OPERAND_VSR }, | |
710 | ||
711 | { "vs0", 0, PPC_OPERAND_VSR }, | |
712 | { "vs1", 1, PPC_OPERAND_VSR }, | |
713 | { "vs10", 10, PPC_OPERAND_VSR }, | |
714 | { "vs11", 11, PPC_OPERAND_VSR }, | |
715 | { "vs12", 12, PPC_OPERAND_VSR }, | |
716 | { "vs13", 13, PPC_OPERAND_VSR }, | |
717 | { "vs14", 14, PPC_OPERAND_VSR }, | |
718 | { "vs15", 15, PPC_OPERAND_VSR }, | |
719 | { "vs16", 16, PPC_OPERAND_VSR }, | |
720 | { "vs17", 17, PPC_OPERAND_VSR }, | |
721 | { "vs18", 18, PPC_OPERAND_VSR }, | |
722 | { "vs19", 19, PPC_OPERAND_VSR }, | |
723 | { "vs2", 2, PPC_OPERAND_VSR }, | |
724 | { "vs20", 20, PPC_OPERAND_VSR }, | |
725 | { "vs21", 21, PPC_OPERAND_VSR }, | |
726 | { "vs22", 22, PPC_OPERAND_VSR }, | |
727 | { "vs23", 23, PPC_OPERAND_VSR }, | |
728 | { "vs24", 24, PPC_OPERAND_VSR }, | |
729 | { "vs25", 25, PPC_OPERAND_VSR }, | |
730 | { "vs26", 26, PPC_OPERAND_VSR }, | |
731 | { "vs27", 27, PPC_OPERAND_VSR }, | |
732 | { "vs28", 28, PPC_OPERAND_VSR }, | |
733 | { "vs29", 29, PPC_OPERAND_VSR }, | |
734 | { "vs3", 3, PPC_OPERAND_VSR }, | |
735 | { "vs30", 30, PPC_OPERAND_VSR }, | |
736 | { "vs31", 31, PPC_OPERAND_VSR }, | |
737 | { "vs32", 32, PPC_OPERAND_VSR }, | |
738 | { "vs33", 33, PPC_OPERAND_VSR }, | |
739 | { "vs34", 34, PPC_OPERAND_VSR }, | |
740 | { "vs35", 35, PPC_OPERAND_VSR }, | |
741 | { "vs36", 36, PPC_OPERAND_VSR }, | |
742 | { "vs37", 37, PPC_OPERAND_VSR }, | |
743 | { "vs38", 38, PPC_OPERAND_VSR }, | |
744 | { "vs39", 39, PPC_OPERAND_VSR }, | |
745 | { "vs4", 4, PPC_OPERAND_VSR }, | |
746 | { "vs40", 40, PPC_OPERAND_VSR }, | |
747 | { "vs41", 41, PPC_OPERAND_VSR }, | |
748 | { "vs42", 42, PPC_OPERAND_VSR }, | |
749 | { "vs43", 43, PPC_OPERAND_VSR }, | |
750 | { "vs44", 44, PPC_OPERAND_VSR }, | |
751 | { "vs45", 45, PPC_OPERAND_VSR }, | |
752 | { "vs46", 46, PPC_OPERAND_VSR }, | |
753 | { "vs47", 47, PPC_OPERAND_VSR }, | |
754 | { "vs48", 48, PPC_OPERAND_VSR }, | |
755 | { "vs49", 49, PPC_OPERAND_VSR }, | |
756 | { "vs5", 5, PPC_OPERAND_VSR }, | |
757 | { "vs50", 50, PPC_OPERAND_VSR }, | |
758 | { "vs51", 51, PPC_OPERAND_VSR }, | |
759 | { "vs52", 52, PPC_OPERAND_VSR }, | |
760 | { "vs53", 53, PPC_OPERAND_VSR }, | |
761 | { "vs54", 54, PPC_OPERAND_VSR }, | |
762 | { "vs55", 55, PPC_OPERAND_VSR }, | |
763 | { "vs56", 56, PPC_OPERAND_VSR }, | |
764 | { "vs57", 57, PPC_OPERAND_VSR }, | |
765 | { "vs58", 58, PPC_OPERAND_VSR }, | |
766 | { "vs59", 59, PPC_OPERAND_VSR }, | |
767 | { "vs6", 6, PPC_OPERAND_VSR }, | |
768 | { "vs60", 60, PPC_OPERAND_VSR }, | |
769 | { "vs61", 61, PPC_OPERAND_VSR }, | |
770 | { "vs62", 62, PPC_OPERAND_VSR }, | |
771 | { "vs63", 63, PPC_OPERAND_VSR }, | |
772 | { "vs7", 7, PPC_OPERAND_VSR }, | |
773 | { "vs8", 8, PPC_OPERAND_VSR }, | |
774 | { "vs9", 9, PPC_OPERAND_VSR }, | |
775 | ||
776 | { "xer", 1, PPC_OPERAND_SPR } | |
252b5132 RH |
777 | }; |
778 | ||
bc805888 | 779 | #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) |
252b5132 RH |
780 | |
781 | /* Given NAME, find the register number associated with that name, return | |
782 | the integer value associated with the given name or -1 on failure. */ | |
783 | ||
7e0de605 | 784 | static const struct pd_reg * |
98027b10 | 785 | reg_name_search (const struct pd_reg *regs, int regcount, const char *name) |
252b5132 RH |
786 | { |
787 | int middle, low, high; | |
788 | int cmp; | |
789 | ||
790 | low = 0; | |
791 | high = regcount - 1; | |
792 | ||
793 | do | |
794 | { | |
795 | middle = (low + high) / 2; | |
796 | cmp = strcasecmp (name, regs[middle].name); | |
797 | if (cmp < 0) | |
798 | high = middle - 1; | |
799 | else if (cmp > 0) | |
800 | low = middle + 1; | |
801 | else | |
7e0de605 | 802 | return ®s[middle]; |
252b5132 RH |
803 | } |
804 | while (low <= high); | |
805 | ||
7e0de605 | 806 | return NULL; |
252b5132 RH |
807 | } |
808 | ||
809 | /* | |
99a814a1 | 810 | * Summary of register_name. |
252b5132 RH |
811 | * |
812 | * in: Input_line_pointer points to 1st char of operand. | |
813 | * | |
814 | * out: A expressionS. | |
815 | * The operand may have been a register: in this case, X_op == O_register, | |
816 | * X_add_number is set to the register number, and truth is returned. | |
817 | * Input_line_pointer->(next non-blank) char after operand, or is in its | |
818 | * original state. | |
819 | */ | |
820 | ||
5b7c81bd | 821 | static bool |
98027b10 | 822 | register_name (expressionS *expressionP) |
252b5132 | 823 | { |
7e0de605 | 824 | const struct pd_reg *reg; |
252b5132 RH |
825 | char *name; |
826 | char *start; | |
827 | char c; | |
828 | ||
99a814a1 | 829 | /* Find the spelling of the operand. */ |
252b5132 | 830 | start = name = input_line_pointer; |
3882b010 | 831 | if (name[0] == '%' && ISALPHA (name[1])) |
252b5132 RH |
832 | name = ++input_line_pointer; |
833 | ||
3882b010 | 834 | else if (!reg_names_p || !ISALPHA (name[0])) |
5b7c81bd | 835 | return false; |
252b5132 | 836 | |
d02603dc | 837 | c = get_symbol_name (&name); |
7e0de605 | 838 | reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); |
252b5132 | 839 | |
468cced8 AM |
840 | /* Put back the delimiting char. */ |
841 | *input_line_pointer = c; | |
842 | ||
99a814a1 | 843 | /* Look to see if it's in the register table. */ |
7e0de605 | 844 | if (reg != NULL) |
252b5132 RH |
845 | { |
846 | expressionP->X_op = O_register; | |
7e0de605 AM |
847 | expressionP->X_add_number = reg->value; |
848 | expressionP->X_md = reg->flags; | |
81d4177b | 849 | |
99a814a1 | 850 | /* Make the rest nice. */ |
252b5132 RH |
851 | expressionP->X_add_symbol = NULL; |
852 | expressionP->X_op_symbol = NULL; | |
5b7c81bd | 853 | return true; |
252b5132 | 854 | } |
468cced8 AM |
855 | |
856 | /* Reset the line as if we had not done anything. */ | |
857 | input_line_pointer = start; | |
5b7c81bd | 858 | return false; |
252b5132 RH |
859 | } |
860 | \f | |
861 | /* This function is called for each symbol seen in an expression. It | |
862 | handles the special parsing which PowerPC assemblers are supposed | |
863 | to use for condition codes. */ | |
864 | ||
865 | /* Whether to do the special parsing. */ | |
5b7c81bd | 866 | static bool cr_operand; |
252b5132 RH |
867 | |
868 | /* Names to recognize in a condition code. This table is sorted. */ | |
869 | static const struct pd_reg cr_names[] = | |
870 | { | |
7e0de605 AM |
871 | { "cr0", 0, PPC_OPERAND_CR_REG }, |
872 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
873 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
874 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
875 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
876 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
877 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
878 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
879 | { "eq", 2, PPC_OPERAND_CR_BIT }, | |
880 | { "gt", 1, PPC_OPERAND_CR_BIT }, | |
881 | { "lt", 0, PPC_OPERAND_CR_BIT }, | |
882 | { "so", 3, PPC_OPERAND_CR_BIT }, | |
883 | { "un", 3, PPC_OPERAND_CR_BIT } | |
252b5132 RH |
884 | }; |
885 | ||
886 | /* Parsing function. This returns non-zero if it recognized an | |
887 | expression. */ | |
888 | ||
889 | int | |
91d6fa6a | 890 | ppc_parse_name (const char *name, expressionS *exp) |
252b5132 | 891 | { |
7e0de605 | 892 | const struct pd_reg *reg; |
252b5132 RH |
893 | |
894 | if (! cr_operand) | |
895 | return 0; | |
896 | ||
13abbae3 AM |
897 | if (*name == '%') |
898 | ++name; | |
7e0de605 | 899 | reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0], |
252b5132 | 900 | name); |
7e0de605 | 901 | if (reg == NULL) |
252b5132 RH |
902 | return 0; |
903 | ||
7e0de605 AM |
904 | exp->X_op = O_register; |
905 | exp->X_add_number = reg->value; | |
906 | exp->X_md = reg->flags; | |
252b5132 RH |
907 | |
908 | return 1; | |
909 | } | |
7e0de605 AM |
910 | |
911 | /* Propagate X_md and check register expressions. This is to support | |
912 | condition codes like 4*cr5+eq. */ | |
913 | ||
914 | int | |
915 | ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right) | |
916 | { | |
917 | /* Accept 4*cr<n> and cr<n>*4. */ | |
918 | if (op == O_multiply | |
919 | && ((right->X_op == O_register | |
920 | && right->X_md == PPC_OPERAND_CR_REG | |
921 | && left->X_op == O_constant | |
922 | && left->X_add_number == 4) | |
923 | || (left->X_op == O_register | |
924 | && left->X_md == PPC_OPERAND_CR_REG | |
925 | && right->X_op == O_constant | |
926 | && right->X_add_number == 4))) | |
927 | { | |
928 | left->X_op = O_register; | |
929 | left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT; | |
930 | left->X_add_number *= right->X_add_number; | |
931 | return 1; | |
932 | } | |
933 | ||
934 | /* Accept the above plus <cr bit>, and <cr bit> plus the above. */ | |
935 | if (right->X_op == O_register | |
936 | && left->X_op == O_register | |
937 | && op == O_add | |
938 | && ((right->X_md == PPC_OPERAND_CR_BIT | |
939 | && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)) | |
940 | || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT) | |
941 | && left->X_md == PPC_OPERAND_CR_BIT))) | |
942 | { | |
943 | left->X_md = PPC_OPERAND_CR_BIT; | |
944 | right->X_op = O_constant; | |
945 | return 0; | |
946 | } | |
947 | ||
948 | /* Accept reg +/- constant. */ | |
949 | if (left->X_op == O_register | |
950 | && !((op == O_add || op == O_subtract) && right->X_op == O_constant)) | |
ece5dcc1 | 951 | as_warn (_("invalid register expression")); |
7e0de605 AM |
952 | |
953 | /* Accept constant + reg. */ | |
954 | if (right->X_op == O_register) | |
955 | { | |
956 | if (op == O_add && left->X_op == O_constant) | |
957 | left->X_md = right->X_md; | |
958 | else | |
ece5dcc1 | 959 | as_warn (_("invalid register expression")); |
7e0de605 AM |
960 | } |
961 | ||
962 | return 0; | |
963 | } | |
252b5132 RH |
964 | \f |
965 | /* Local variables. */ | |
966 | ||
2b3c4602 AM |
967 | /* Whether to target xcoff64/elf64. */ |
968 | static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64; | |
7f6d05e8 | 969 | |
252b5132 | 970 | /* Opcode hash table. */ |
629310ab | 971 | static htab_t ppc_hash; |
252b5132 RH |
972 | |
973 | /* Macro hash table. */ | |
629310ab | 974 | static htab_t ppc_macro_hash; |
252b5132 RH |
975 | |
976 | #ifdef OBJ_ELF | |
99a814a1 | 977 | /* What type of shared library support to use. */ |
5d6f4f16 | 978 | static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE; |
252b5132 | 979 | |
99a814a1 | 980 | /* Flags to set in the elf header. */ |
252b5132 RH |
981 | static flagword ppc_flags = 0; |
982 | ||
983 | /* Whether this is Solaris or not. */ | |
984 | #ifdef TARGET_SOLARIS_COMMENT | |
5b7c81bd | 985 | #define SOLARIS_P true |
252b5132 | 986 | #else |
5b7c81bd | 987 | #define SOLARIS_P false |
252b5132 RH |
988 | #endif |
989 | ||
5b7c81bd | 990 | static bool msolaris = SOLARIS_P; |
252b5132 RH |
991 | #endif |
992 | ||
993 | #ifdef OBJ_XCOFF | |
994 | ||
995 | /* The RS/6000 assembler uses the .csect pseudo-op to generate code | |
996 | using a bunch of different sections. These assembler sections, | |
1b2cb8e2 CC |
997 | however, are all encompassed within the .text, .data or .bss sections |
998 | of the final output file. We handle this by using different | |
999 | subsegments within these main segments. | |
1000 | .tdata and .tbss sections only have one type of csects for now, | |
1001 | but it's better to follow the same construction like the others. */ | |
1002 | ||
1003 | struct ppc_xcoff_section ppc_xcoff_text_section; | |
1004 | struct ppc_xcoff_section ppc_xcoff_data_section; | |
1005 | struct ppc_xcoff_section ppc_xcoff_bss_section; | |
1006 | struct ppc_xcoff_section ppc_xcoff_tdata_section; | |
1007 | struct ppc_xcoff_section ppc_xcoff_tbss_section; | |
1008 | ||
1009 | /* Return true if the ppc_xcoff_section structure is already | |
1010 | initialized. */ | |
5b7c81bd | 1011 | static bool |
1b2cb8e2 CC |
1012 | ppc_xcoff_section_is_initialized (struct ppc_xcoff_section *section) |
1013 | { | |
1014 | return section->segment != NULL; | |
1015 | } | |
252b5132 | 1016 | |
1b2cb8e2 CC |
1017 | /* Initialize a ppc_xcoff_section. |
1018 | Dummy symbols are used to ensure the position of .text over .data | |
934cb849 CC |
1019 | and .tdata. Moreover, they allow all algorithms here to be sure that |
1020 | csects isn't NULL. These symbols won't be output. */ | |
1b2cb8e2 | 1021 | static void |
934cb849 | 1022 | ppc_init_xcoff_section (struct ppc_xcoff_section *s, segT seg) |
1b2cb8e2 CC |
1023 | { |
1024 | s->segment = seg; | |
1025 | s->next_subsegment = 2; | |
934cb849 CC |
1026 | s->csects = symbol_make ("dummy\001"); |
1027 | symbol_get_tc (s->csects)->within = s->csects; | |
1b2cb8e2 | 1028 | } |
252b5132 RH |
1029 | |
1030 | /* The current csect. */ | |
1031 | static symbolS *ppc_current_csect; | |
1032 | ||
1033 | /* The RS/6000 assembler uses a TOC which holds addresses of functions | |
1034 | and variables. Symbols are put in the TOC with the .tc pseudo-op. | |
1035 | A special relocation is used when accessing TOC entries. We handle | |
1036 | the TOC as a subsegment within the .data segment. We set it up if | |
1037 | we see a .toc pseudo-op, and save the csect symbol here. */ | |
1038 | static symbolS *ppc_toc_csect; | |
1039 | ||
1040 | /* The first frag in the TOC subsegment. */ | |
1041 | static fragS *ppc_toc_frag; | |
1042 | ||
1043 | /* The first frag in the first subsegment after the TOC in the .data | |
1044 | segment. NULL if there are no subsegments after the TOC. */ | |
1045 | static fragS *ppc_after_toc_frag; | |
1046 | ||
1047 | /* The current static block. */ | |
1048 | static symbolS *ppc_current_block; | |
1049 | ||
1050 | /* The COFF debugging section; set by md_begin. This is not the | |
1051 | .debug section, but is instead the secret BFD section which will | |
1052 | cause BFD to set the section number of a symbol to N_DEBUG. */ | |
1053 | static asection *ppc_coff_debug_section; | |
1054 | ||
85645aed TG |
1055 | /* Structure to set the length field of the dwarf sections. */ |
1056 | struct dw_subsection { | |
1057 | /* Subsections are simply linked. */ | |
1058 | struct dw_subsection *link; | |
1059 | ||
1060 | /* The subsection number. */ | |
1061 | subsegT subseg; | |
1062 | ||
1063 | /* Expression to compute the length of the section. */ | |
1064 | expressionS end_exp; | |
1065 | }; | |
1066 | ||
1067 | static struct dw_section { | |
1068 | /* Corresponding section. */ | |
1069 | segT sect; | |
1070 | ||
1071 | /* Simply linked list of subsections with a label. */ | |
1072 | struct dw_subsection *list_subseg; | |
1073 | ||
1074 | /* The anonymous subsection. */ | |
1075 | struct dw_subsection *anon_subseg; | |
1076 | } dw_sections[XCOFF_DWSECT_NBR_NAMES]; | |
252b5132 RH |
1077 | #endif /* OBJ_XCOFF */ |
1078 | ||
252b5132 RH |
1079 | #ifdef OBJ_ELF |
1080 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */ | |
6a0c61b7 EZ |
1081 | unsigned long *ppc_apuinfo_list; |
1082 | unsigned int ppc_apuinfo_num; | |
1083 | unsigned int ppc_apuinfo_num_alloc; | |
252b5132 RH |
1084 | #endif /* OBJ_ELF */ |
1085 | \f | |
1086 | #ifdef OBJ_ELF | |
15c1449b | 1087 | const char *const md_shortopts = "b:l:usm:K:VQ:"; |
252b5132 | 1088 | #else |
15c1449b | 1089 | const char *const md_shortopts = "um:"; |
252b5132 | 1090 | #endif |
cef4f754 | 1091 | #define OPTION_NOPS (OPTION_MD_BASE + 0) |
15c1449b | 1092 | const struct option md_longopts[] = { |
cef4f754 | 1093 | {"nops", required_argument, NULL, OPTION_NOPS}, |
bf7279d5 AM |
1094 | {"ppc476-workaround", no_argument, &warn_476, 1}, |
1095 | {"no-ppc476-workaround", no_argument, &warn_476, 0}, | |
252b5132 RH |
1096 | {NULL, no_argument, NULL, 0} |
1097 | }; | |
15c1449b | 1098 | const size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1099 | |
1100 | int | |
17b9d67d | 1101 | md_parse_option (int c, const char *arg) |
252b5132 | 1102 | { |
69fe9ce5 AM |
1103 | ppc_cpu_t new_cpu; |
1104 | ||
252b5132 RH |
1105 | switch (c) |
1106 | { | |
1107 | case 'u': | |
1108 | /* -u means that any undefined symbols should be treated as | |
1109 | external, which is the default for gas anyhow. */ | |
1110 | break; | |
1111 | ||
1112 | #ifdef OBJ_ELF | |
1113 | case 'l': | |
1114 | /* Solaris as takes -le (presumably for little endian). For completeness | |
99a814a1 | 1115 | sake, recognize -be also. */ |
252b5132 RH |
1116 | if (strcmp (arg, "e") == 0) |
1117 | { | |
1118 | target_big_endian = 0; | |
1119 | set_target_endian = 1; | |
b9c361e0 | 1120 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1121 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1122 | } |
1123 | else | |
1124 | return 0; | |
1125 | ||
1126 | break; | |
1127 | ||
1128 | case 'b': | |
1129 | if (strcmp (arg, "e") == 0) | |
1130 | { | |
1131 | target_big_endian = 1; | |
1132 | set_target_endian = 1; | |
1133 | } | |
1134 | else | |
1135 | return 0; | |
1136 | ||
1137 | break; | |
1138 | ||
1139 | case 'K': | |
99a814a1 | 1140 | /* Recognize -K PIC. */ |
252b5132 RH |
1141 | if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0) |
1142 | { | |
1143 | shlib = SHLIB_PIC; | |
1144 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; | |
1145 | } | |
1146 | else | |
1147 | return 0; | |
1148 | ||
1149 | break; | |
1150 | #endif | |
1151 | ||
7f6d05e8 CP |
1152 | /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */ |
1153 | case 'a': | |
1154 | if (strcmp (arg, "64") == 0) | |
2a98c3a6 AM |
1155 | { |
1156 | #ifdef BFD64 | |
1157 | ppc_obj64 = 1; | |
d6ed37ed AM |
1158 | if (ppc_cpu & PPC_OPCODE_VLE) |
1159 | as_bad (_("the use of -mvle requires -a32.")); | |
2a98c3a6 AM |
1160 | #else |
1161 | as_fatal (_("%s unsupported"), "-a64"); | |
1162 | #endif | |
1163 | } | |
7f6d05e8 | 1164 | else if (strcmp (arg, "32") == 0) |
2b3c4602 | 1165 | ppc_obj64 = 0; |
7f6d05e8 CP |
1166 | else |
1167 | return 0; | |
1168 | break; | |
81d4177b | 1169 | |
252b5132 | 1170 | case 'm': |
776fc418 | 1171 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg); |
52be03fd AM |
1172 | /* "raw" is only valid for the disassembler. */ |
1173 | if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0) | |
b9c361e0 JL |
1174 | { |
1175 | ppc_cpu = new_cpu; | |
d6ed37ed AM |
1176 | if (strcmp (arg, "vle") == 0) |
1177 | { | |
1178 | if (set_target_endian && target_big_endian == 0) | |
1179 | as_bad (_("the use of -mvle requires big endian.")); | |
1180 | if (ppc_obj64) | |
1181 | as_bad (_("the use of -mvle requires -a32.")); | |
1182 | } | |
b9c361e0 | 1183 | } |
252b5132 | 1184 | |
83eef883 AFB |
1185 | else if (strcmp (arg, "no-vle") == 0) |
1186 | { | |
1187 | sticky &= ~PPC_OPCODE_VLE; | |
1188 | ||
1189 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke"); | |
1190 | new_cpu &= ~PPC_OPCODE_VLE; | |
1191 | ||
1192 | ppc_cpu = new_cpu; | |
1193 | } | |
1194 | ||
252b5132 | 1195 | else if (strcmp (arg, "regnames") == 0) |
5b7c81bd | 1196 | reg_names_p = true; |
252b5132 RH |
1197 | |
1198 | else if (strcmp (arg, "no-regnames") == 0) | |
5b7c81bd | 1199 | reg_names_p = false; |
252b5132 RH |
1200 | |
1201 | #ifdef OBJ_ELF | |
99a814a1 AM |
1202 | /* -mrelocatable/-mrelocatable-lib -- warn about initializations |
1203 | that require relocation. */ | |
252b5132 RH |
1204 | else if (strcmp (arg, "relocatable") == 0) |
1205 | { | |
5d6f4f16 | 1206 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1207 | ppc_flags |= EF_PPC_RELOCATABLE; |
1208 | } | |
1209 | ||
1210 | else if (strcmp (arg, "relocatable-lib") == 0) | |
1211 | { | |
5d6f4f16 | 1212 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1213 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; |
1214 | } | |
1215 | ||
99a814a1 | 1216 | /* -memb, set embedded bit. */ |
252b5132 RH |
1217 | else if (strcmp (arg, "emb") == 0) |
1218 | ppc_flags |= EF_PPC_EMB; | |
1219 | ||
cc643b88 | 1220 | /* -mlittle/-mbig set the endianness. */ |
99a814a1 AM |
1221 | else if (strcmp (arg, "little") == 0 |
1222 | || strcmp (arg, "little-endian") == 0) | |
252b5132 RH |
1223 | { |
1224 | target_big_endian = 0; | |
1225 | set_target_endian = 1; | |
b9c361e0 | 1226 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1227 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1228 | } |
1229 | ||
1230 | else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0) | |
1231 | { | |
1232 | target_big_endian = 1; | |
1233 | set_target_endian = 1; | |
1234 | } | |
1235 | ||
1236 | else if (strcmp (arg, "solaris") == 0) | |
1237 | { | |
5b7c81bd | 1238 | msolaris = true; |
252b5132 RH |
1239 | ppc_comment_chars = ppc_solaris_comment_chars; |
1240 | } | |
1241 | ||
1242 | else if (strcmp (arg, "no-solaris") == 0) | |
1243 | { | |
5b7c81bd | 1244 | msolaris = false; |
252b5132 RH |
1245 | ppc_comment_chars = ppc_eabi_comment_chars; |
1246 | } | |
74081948 AF |
1247 | else if (strcmp (arg, "spe2") == 0) |
1248 | { | |
1249 | ppc_cpu |= PPC_OPCODE_SPE2; | |
1250 | } | |
252b5132 RH |
1251 | #endif |
1252 | else | |
1253 | { | |
1254 | as_bad (_("invalid switch -m%s"), arg); | |
1255 | return 0; | |
1256 | } | |
1257 | break; | |
1258 | ||
1259 | #ifdef OBJ_ELF | |
1260 | /* -V: SVR4 argument to print version ID. */ | |
1261 | case 'V': | |
1262 | print_version_id (); | |
1263 | break; | |
1264 | ||
1265 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
1266 | should be emitted or not. FIXME: Not implemented. */ | |
1267 | case 'Q': | |
1268 | break; | |
1269 | ||
1270 | /* Solaris takes -s to specify that .stabs go in a .stabs section, | |
1271 | rather than .stabs.excl, which is ignored by the linker. | |
1272 | FIXME: Not implemented. */ | |
1273 | case 's': | |
1274 | if (arg) | |
1275 | return 0; | |
1276 | ||
1277 | break; | |
1278 | #endif | |
1279 | ||
cef4f754 AM |
1280 | case OPTION_NOPS: |
1281 | { | |
1282 | char *end; | |
1283 | nop_limit = strtoul (optarg, &end, 0); | |
1284 | if (*end) | |
1285 | as_bad (_("--nops needs a numeric argument")); | |
1286 | } | |
1287 | break; | |
85645aed | 1288 | |
bf7279d5 AM |
1289 | case 0: |
1290 | break; | |
1291 | ||
252b5132 RH |
1292 | default: |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | return 1; | |
1297 | } | |
1298 | ||
5f63875b AM |
1299 | static int |
1300 | is_ppc64_target (const bfd_target *targ, void *data ATTRIBUTE_UNUSED) | |
1301 | { | |
1302 | switch (targ->flavour) | |
1303 | { | |
1304 | #ifdef OBJ_ELF | |
1305 | case bfd_target_elf_flavour: | |
d34049e8 | 1306 | return startswith (targ->name, "elf64-powerpc"); |
5f63875b AM |
1307 | #endif |
1308 | #ifdef OBJ_XCOFF | |
1309 | case bfd_target_xcoff_flavour: | |
1310 | return (strcmp (targ->name, "aixcoff64-rs6000") == 0 | |
1311 | || strcmp (targ->name, "aix5coff64-rs6000") == 0); | |
1312 | #endif | |
1313 | default: | |
1314 | return 0; | |
1315 | } | |
1316 | } | |
1317 | ||
252b5132 | 1318 | void |
98027b10 | 1319 | md_show_usage (FILE *stream) |
252b5132 | 1320 | { |
bc805888 | 1321 | fprintf (stream, _("\ |
5f63875b AM |
1322 | PowerPC options:\n")); |
1323 | fprintf (stream, _("\ | |
1324 | -a32 generate ELF32/XCOFF32\n")); | |
1325 | if (bfd_iterate_over_targets (is_ppc64_target, NULL)) | |
1326 | fprintf (stream, _("\ | |
1327 | -a64 generate ELF64/XCOFF64\n")); | |
1328 | fprintf (stream, _("\ | |
1329 | -u ignored\n")); | |
1330 | fprintf (stream, _("\ | |
1331 | -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n")); | |
1332 | fprintf (stream, _("\ | |
1333 | -mpwr generate code for POWER (RIOS1)\n")); | |
1334 | fprintf (stream, _("\ | |
1335 | -m601 generate code for PowerPC 601\n")); | |
1336 | fprintf (stream, _("\ | |
418c1742 | 1337 | -mppc, -mppc32, -m603, -m604\n\ |
5f63875b AM |
1338 | generate code for PowerPC 603/604\n")); |
1339 | fprintf (stream, _("\ | |
1340 | -m403 generate code for PowerPC 403\n")); | |
1341 | fprintf (stream, _("\ | |
1342 | -m405 generate code for PowerPC 405\n")); | |
1343 | fprintf (stream, _("\ | |
1344 | -m440 generate code for PowerPC 440\n")); | |
1345 | fprintf (stream, _("\ | |
1346 | -m464 generate code for PowerPC 464\n")); | |
1347 | fprintf (stream, _("\ | |
1348 | -m476 generate code for PowerPC 476\n")); | |
1349 | fprintf (stream, _("\ | |
f5c120c5 | 1350 | -m7400, -m7410, -m7450, -m7455\n\ |
5f63875b AM |
1351 | generate code for PowerPC 7400/7410/7450/7455\n")); |
1352 | fprintf (stream, _("\ | |
fa758a70 | 1353 | -m750cl, -mgekko, -mbroadway\n\ |
5f63875b AM |
1354 | generate code for PowerPC 750cl/Gekko/Broadway\n")); |
1355 | fprintf (stream, _("\ | |
ef5a96d5 | 1356 | -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); |
df12615d | 1357 | fprintf (stream, _("\ |
5f63875b AM |
1358 | -mppc64, -m620 generate code for PowerPC 620/625/630\n")); |
1359 | fprintf (stream, _("\ | |
1360 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n")); | |
1361 | fprintf (stream, _("\ | |
1362 | -mbooke generate code for 32-bit PowerPC BookE\n")); | |
1363 | fprintf (stream, _("\ | |
1364 | -ma2 generate code for A2 architecture\n")); | |
1365 | fprintf (stream, _("\ | |
1366 | -mpower4, -mpwr4 generate code for Power4 architecture\n")); | |
1367 | fprintf (stream, _("\ | |
cdc51b07 | 1368 | -mpower5, -mpwr5, -mpwr5x\n\ |
5f63875b AM |
1369 | generate code for Power5 architecture\n")); |
1370 | fprintf (stream, _("\ | |
1371 | -mpower6, -mpwr6 generate code for Power6 architecture\n")); | |
1372 | fprintf (stream, _("\ | |
1373 | -mpower7, -mpwr7 generate code for Power7 architecture\n")); | |
1374 | fprintf (stream, _("\ | |
1375 | -mpower8, -mpwr8 generate code for Power8 architecture\n")); | |
1376 | fprintf (stream, _("\ | |
1377 | -mpower9, -mpwr9 generate code for Power9 architecture\n")); | |
1378 | fprintf (stream, _("\ | |
1424c35d AM |
1379 | -mpower10, -mpwr10 generate code for Power10 architecture\n")); |
1380 | fprintf (stream, _("\ | |
5f63875b AM |
1381 | -mcell generate code for Cell Broadband Engine architecture\n")); |
1382 | fprintf (stream, _("\ | |
1383 | -mcom generate code for Power/PowerPC common instructions\n")); | |
1384 | fprintf (stream, _("\ | |
ce3d2015 | 1385 | -many generate code for any architecture (PWR/PWRX/PPC)\n")); |
6a0c61b7 | 1386 | fprintf (stream, _("\ |
5f63875b AM |
1387 | -maltivec generate code for AltiVec\n")); |
1388 | fprintf (stream, _("\ | |
1389 | -mvsx generate code for Vector-Scalar (VSX) instructions\n")); | |
1390 | fprintf (stream, _("\ | |
1391 | -me300 generate code for PowerPC e300 family\n")); | |
1392 | fprintf (stream, _("\ | |
1393 | -me500, -me500x2 generate code for Motorola e500 core complex\n")); | |
1394 | fprintf (stream, _("\ | |
1395 | -me500mc, generate code for Freescale e500mc core complex\n")); | |
1396 | fprintf (stream, _("\ | |
1397 | -me500mc64, generate code for Freescale e500mc64 core complex\n")); | |
1398 | fprintf (stream, _("\ | |
1399 | -me5500, generate code for Freescale e5500 core complex\n")); | |
1400 | fprintf (stream, _("\ | |
1401 | -me6500, generate code for Freescale e6500 core complex\n")); | |
1402 | fprintf (stream, _("\ | |
1403 | -mspe generate code for Motorola SPE instructions\n")); | |
1404 | fprintf (stream, _("\ | |
1405 | -mspe2 generate code for Freescale SPE2 instructions\n")); | |
1406 | fprintf (stream, _("\ | |
1407 | -mvle generate code for Freescale VLE instructions\n")); | |
1408 | fprintf (stream, _("\ | |
1409 | -mtitan generate code for AppliedMicro Titan core complex\n")); | |
1410 | fprintf (stream, _("\ | |
1411 | -mregnames Allow symbolic names for registers\n")); | |
1412 | fprintf (stream, _("\ | |
ce3d2015 | 1413 | -mno-regnames Do not allow symbolic names for registers\n")); |
252b5132 | 1414 | #ifdef OBJ_ELF |
bc805888 | 1415 | fprintf (stream, _("\ |
5f63875b AM |
1416 | -mrelocatable support for GCC's -mrelocatble option\n")); |
1417 | fprintf (stream, _("\ | |
1418 | -mrelocatable-lib support for GCC's -mrelocatble-lib option\n")); | |
1419 | fprintf (stream, _("\ | |
1420 | -memb set PPC_EMB bit in ELF flags\n")); | |
1421 | fprintf (stream, _("\ | |
b8b738ac | 1422 | -mlittle, -mlittle-endian, -le\n\ |
5f63875b AM |
1423 | generate code for a little endian machine\n")); |
1424 | fprintf (stream, _("\ | |
b8b738ac | 1425 | -mbig, -mbig-endian, -be\n\ |
5f63875b AM |
1426 | generate code for a big endian machine\n")); |
1427 | fprintf (stream, _("\ | |
1428 | -msolaris generate code for Solaris\n")); | |
1429 | fprintf (stream, _("\ | |
1430 | -mno-solaris do not generate code for Solaris\n")); | |
1431 | fprintf (stream, _("\ | |
1432 | -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n")); | |
1433 | fprintf (stream, _("\ | |
1434 | -V print assembler version number\n")); | |
1435 | fprintf (stream, _("\ | |
ce3d2015 | 1436 | -Qy, -Qn ignored\n")); |
252b5132 | 1437 | #endif |
cef4f754 | 1438 | fprintf (stream, _("\ |
5f63875b AM |
1439 | -nops=count when aligning, more than COUNT nops uses a branch\n")); |
1440 | fprintf (stream, _("\ | |
bf7279d5 | 1441 | -ppc476-workaround warn if emitting data to code sections\n")); |
252b5132 RH |
1442 | } |
1443 | \f | |
1444 | /* Set ppc_cpu if it is not already set. */ | |
1445 | ||
1446 | static void | |
98027b10 | 1447 | ppc_set_cpu (void) |
252b5132 RH |
1448 | { |
1449 | const char *default_os = TARGET_OS; | |
1450 | const char *default_cpu = TARGET_CPU; | |
1451 | ||
7102e95e | 1452 | if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0) |
252b5132 | 1453 | { |
2a98c3a6 | 1454 | if (ppc_obj64) |
f2ab4b42 PB |
1455 | if (target_big_endian) |
1456 | ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64; | |
1457 | else | |
1458 | /* The minimum supported cpu for 64-bit little-endian is power8. */ | |
1459 | ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8"); | |
d34049e8 | 1460 | else if (startswith (default_os, "aix") |
2a98c3a6 | 1461 | && default_os[3] >= '4' && default_os[3] <= '9') |
bdc70b4a | 1462 | ppc_cpu |= PPC_OPCODE_COMMON; |
d34049e8 | 1463 | else if (startswith (default_os, "aix3")) |
bdc70b4a | 1464 | ppc_cpu |= PPC_OPCODE_POWER; |
252b5132 | 1465 | else if (strcmp (default_cpu, "rs6000") == 0) |
bdc70b4a | 1466 | ppc_cpu |= PPC_OPCODE_POWER; |
d34049e8 | 1467 | else if (startswith (default_cpu, "powerpc")) |
bdc70b4a | 1468 | ppc_cpu |= PPC_OPCODE_PPC; |
252b5132 | 1469 | else |
d6ed37ed | 1470 | as_fatal (_("unknown default cpu = %s, os = %s"), |
99a814a1 | 1471 | default_cpu, default_os); |
252b5132 RH |
1472 | } |
1473 | } | |
1474 | ||
9232bbb0 AM |
1475 | /* Figure out the BFD architecture to use. This function and ppc_mach |
1476 | are called well before md_begin, when the output file is opened. */ | |
252b5132 RH |
1477 | |
1478 | enum bfd_architecture | |
98027b10 | 1479 | ppc_arch (void) |
252b5132 RH |
1480 | { |
1481 | const char *default_cpu = TARGET_CPU; | |
1482 | ppc_set_cpu (); | |
1483 | ||
1484 | if ((ppc_cpu & PPC_OPCODE_PPC) != 0) | |
1485 | return bfd_arch_powerpc; | |
b9c361e0 JL |
1486 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
1487 | return bfd_arch_powerpc; | |
1488 | if ((ppc_cpu & PPC_OPCODE_POWER) != 0) | |
252b5132 | 1489 | return bfd_arch_rs6000; |
b9c361e0 | 1490 | if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0) |
252b5132 RH |
1491 | { |
1492 | if (strcmp (default_cpu, "rs6000") == 0) | |
1493 | return bfd_arch_rs6000; | |
d34049e8 | 1494 | else if (startswith (default_cpu, "powerpc")) |
252b5132 RH |
1495 | return bfd_arch_powerpc; |
1496 | } | |
1497 | ||
d6ed37ed | 1498 | as_fatal (_("neither Power nor PowerPC opcodes were selected.")); |
252b5132 RH |
1499 | return bfd_arch_unknown; |
1500 | } | |
1501 | ||
7f6d05e8 | 1502 | unsigned long |
98027b10 | 1503 | ppc_mach (void) |
7f6d05e8 | 1504 | { |
2a98c3a6 AM |
1505 | if (ppc_obj64) |
1506 | return bfd_mach_ppc64; | |
1507 | else if (ppc_arch () == bfd_arch_rs6000) | |
1508 | return bfd_mach_rs6k; | |
ce3d2015 AM |
1509 | else if (ppc_cpu & PPC_OPCODE_TITAN) |
1510 | return bfd_mach_ppc_titan; | |
b9c361e0 JL |
1511 | else if (ppc_cpu & PPC_OPCODE_VLE) |
1512 | return bfd_mach_ppc_vle; | |
2a98c3a6 AM |
1513 | else |
1514 | return bfd_mach_ppc; | |
7f6d05e8 CP |
1515 | } |
1516 | ||
e0471c16 | 1517 | extern const char* |
98027b10 | 1518 | ppc_target_format (void) |
7f6d05e8 CP |
1519 | { |
1520 | #ifdef OBJ_COFF | |
fe49679d | 1521 | #if TE_POWERMAC |
0baf16f2 | 1522 | return "xcoff-powermac"; |
7f6d05e8 | 1523 | #else |
eb1e0e80 | 1524 | # ifdef TE_AIX5 |
edc1d652 | 1525 | return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1526 | # else |
edc1d652 | 1527 | return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1528 | # endif |
7f6d05e8 | 1529 | #endif |
7f6d05e8 CP |
1530 | #endif |
1531 | #ifdef OBJ_ELF | |
edc1d652 AM |
1532 | # ifdef TE_FreeBSD |
1533 | return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd"); | |
1534 | # elif defined (TE_VXWORKS) | |
9d8504b1 PB |
1535 | return "elf32-powerpc-vxworks"; |
1536 | # else | |
0baf16f2 | 1537 | return (target_big_endian |
2b3c4602 AM |
1538 | ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") |
1539 | : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); | |
9d8504b1 | 1540 | # endif |
7f6d05e8 CP |
1541 | #endif |
1542 | } | |
1543 | ||
b9c361e0 JL |
1544 | /* Validate one entry in powerpc_opcodes[] or vle_opcodes[]. |
1545 | Return TRUE if there's a problem, otherwise FALSE. */ | |
1546 | ||
5b7c81bd | 1547 | static bool |
b9c361e0 JL |
1548 | insn_validate (const struct powerpc_opcode *op) |
1549 | { | |
1550 | const unsigned char *o; | |
0f873fd5 | 1551 | uint64_t omask = op->mask; |
b9c361e0 JL |
1552 | |
1553 | /* The mask had better not trim off opcode bits. */ | |
1554 | if ((op->opcode & omask) != op->opcode) | |
1555 | { | |
1556 | as_bad (_("mask trims opcode bits for %s"), op->name); | |
5b7c81bd | 1557 | return true; |
b9c361e0 JL |
1558 | } |
1559 | ||
1560 | /* The operands must not overlap the opcode or each other. */ | |
1561 | for (o = op->operands; *o; ++o) | |
1562 | { | |
5b7c81bd | 1563 | bool optional = false; |
b9c361e0 JL |
1564 | if (*o >= num_powerpc_operands) |
1565 | { | |
1566 | as_bad (_("operand index error for %s"), op->name); | |
5b7c81bd | 1567 | return true; |
b9c361e0 JL |
1568 | } |
1569 | else | |
1570 | { | |
71553718 | 1571 | uint64_t mask; |
b9c361e0 | 1572 | const struct powerpc_operand *operand = &powerpc_operands[*o]; |
71553718 | 1573 | if (operand->shift == (int) PPC_OPSHIFT_INV) |
b9c361e0 | 1574 | { |
71553718 | 1575 | const char *errmsg; |
32d71569 | 1576 | uint64_t val; |
71553718 AM |
1577 | |
1578 | errmsg = NULL; | |
1579 | val = -1; | |
1580 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
1581 | val = -val; | |
1582 | else if ((operand->flags & PPC_OPERAND_PLUS1) != 0) | |
1583 | val += 1; | |
1584 | mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); | |
b9c361e0 | 1585 | } |
71553718 AM |
1586 | else if (operand->shift >= 0) |
1587 | mask = operand->bitm << operand->shift; | |
1588 | else | |
1589 | mask = operand->bitm >> -operand->shift; | |
1590 | if (omask & mask) | |
1591 | { | |
1592 | as_bad (_("operand %d overlap in %s"), | |
1593 | (int) (o - op->operands), op->name); | |
5b7c81bd | 1594 | return true; |
71553718 AM |
1595 | } |
1596 | omask |= mask; | |
2eac3da1 | 1597 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
5b7c81bd | 1598 | optional = true; |
2eac3da1 AM |
1599 | else if (optional) |
1600 | { | |
1601 | as_bad (_("non-optional operand %d follows optional operand in %s"), | |
1602 | (int) (o - op->operands), op->name); | |
5b7c81bd | 1603 | return true; |
2eac3da1 | 1604 | } |
b9c361e0 JL |
1605 | } |
1606 | } | |
5b7c81bd | 1607 | return false; |
b9c361e0 JL |
1608 | } |
1609 | ||
69c040df | 1610 | /* Insert opcodes and macros into hash tables. Called at startup and |
1fe532cf | 1611 | for .machine pseudo. */ |
252b5132 | 1612 | |
69c040df AM |
1613 | static void |
1614 | ppc_setup_opcodes (void) | |
252b5132 | 1615 | { |
98027b10 | 1616 | const struct powerpc_opcode *op; |
252b5132 RH |
1617 | const struct powerpc_opcode *op_end; |
1618 | const struct powerpc_macro *macro; | |
1619 | const struct powerpc_macro *macro_end; | |
5b7c81bd | 1620 | bool bad_insn = false; |
252b5132 | 1621 | |
69c040df | 1622 | if (ppc_hash != NULL) |
629310ab | 1623 | htab_delete (ppc_hash); |
69c040df | 1624 | if (ppc_macro_hash != NULL) |
629310ab | 1625 | htab_delete (ppc_macro_hash); |
252b5132 RH |
1626 | |
1627 | /* Insert the opcodes into a hash table. */ | |
629310ab | 1628 | ppc_hash = str_htab_create (); |
252b5132 | 1629 | |
c43a438d | 1630 | if (ENABLE_CHECKING) |
b84bf58a | 1631 | { |
c43a438d | 1632 | unsigned int i; |
b84bf58a | 1633 | |
3b8b57a9 AM |
1634 | /* An index into powerpc_operands is stored in struct fix |
1635 | fx_pcrel_adjust which is 8 bits wide. */ | |
1636 | gas_assert (num_powerpc_operands < 256); | |
1637 | ||
c43a438d AM |
1638 | /* Check operand masks. Code here and in the disassembler assumes |
1639 | all the 1's in the mask are contiguous. */ | |
1640 | for (i = 0; i < num_powerpc_operands; ++i) | |
b84bf58a | 1641 | { |
0f873fd5 PB |
1642 | uint64_t mask = powerpc_operands[i].bitm; |
1643 | uint64_t right_bit; | |
c43a438d AM |
1644 | unsigned int j; |
1645 | ||
1646 | right_bit = mask & -mask; | |
1647 | mask += right_bit; | |
1648 | right_bit = mask & -mask; | |
1649 | if (mask != right_bit) | |
1650 | { | |
1651 | as_bad (_("powerpc_operands[%d].bitm invalid"), i); | |
5b7c81bd | 1652 | bad_insn = true; |
c43a438d AM |
1653 | } |
1654 | for (j = i + 1; j < num_powerpc_operands; ++j) | |
1655 | if (memcmp (&powerpc_operands[i], &powerpc_operands[j], | |
1656 | sizeof (powerpc_operands[0])) == 0) | |
1657 | { | |
1658 | as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"), | |
1659 | j, i); | |
5b7c81bd | 1660 | bad_insn = true; |
c43a438d | 1661 | } |
b84bf58a AM |
1662 | } |
1663 | } | |
1664 | ||
252b5132 RH |
1665 | op_end = powerpc_opcodes + powerpc_num_opcodes; |
1666 | for (op = powerpc_opcodes; op < op_end; op++) | |
1667 | { | |
c43a438d | 1668 | if (ENABLE_CHECKING) |
b84bf58a | 1669 | { |
2ceb7719 | 1670 | unsigned int new_opcode = PPC_OP (op[0].opcode); |
b9c361e0 JL |
1671 | |
1672 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1673 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1674 | op->name, (unsigned int) (op - powerpc_opcodes), | |
1675 | new_opcode, (unsigned long long) op->opcode, | |
1676 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 JL |
1677 | #endif |
1678 | ||
2ceb7719 PB |
1679 | /* The major opcodes had better be sorted. Code in the disassembler |
1680 | assumes the insns are sorted according to major opcode. */ | |
1681 | if (op != powerpc_opcodes | |
1682 | && new_opcode < PPC_OP (op[-1].opcode)) | |
1683 | { | |
1684 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1685 | bad_insn = true; |
8dbcd839 | 1686 | } |
2ceb7719 | 1687 | |
14b57c7c AM |
1688 | if ((op->flags & PPC_OPCODE_VLE) != 0) |
1689 | { | |
1690 | as_bad (_("%s is enabled by vle flag"), op->name); | |
5b7c81bd | 1691 | bad_insn = true; |
14b57c7c AM |
1692 | } |
1693 | if (PPC_OP (op->opcode) != 4 | |
1694 | && PPC_OP (op->opcode) != 31 | |
1695 | && (op->deprecated & PPC_OPCODE_VLE) == 0) | |
1696 | { | |
1697 | as_bad (_("%s not disabled by vle flag"), op->name); | |
5b7c81bd | 1698 | bad_insn = true; |
14b57c7c | 1699 | } |
b9c361e0 JL |
1700 | bad_insn |= insn_validate (op); |
1701 | } | |
c43a438d | 1702 | |
b9c361e0 | 1703 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1704 | && !(ppc_cpu & op->deprecated) |
1705 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1706 | { | |
1707 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1708 | bad_insn = true; |
fe0e921f | 1709 | } |
b9c361e0 | 1710 | } |
c43a438d | 1711 | |
b9c361e0 JL |
1712 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) |
1713 | for (op = powerpc_opcodes; op < op_end; op++) | |
fe0e921f | 1714 | str_hash_insert (ppc_hash, op->name, op, 0); |
b9c361e0 | 1715 | |
dd7efa79 PB |
1716 | op_end = prefix_opcodes + prefix_num_opcodes; |
1717 | for (op = prefix_opcodes; op < op_end; op++) | |
1718 | { | |
1719 | if (ENABLE_CHECKING) | |
1720 | { | |
1721 | unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode); | |
1722 | ||
1723 | #ifdef PRINT_OPCODE_TABLE | |
1724 | printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", | |
1725 | op->name, (unsigned int) (op - prefix_opcodes), | |
1726 | new_opcode, (unsigned long long) op->opcode, | |
1727 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
1728 | #endif | |
1729 | ||
1730 | /* The major opcodes had better be sorted. Code in the disassembler | |
1731 | assumes the insns are sorted according to major opcode. */ | |
1732 | if (op != prefix_opcodes | |
1733 | && new_opcode < PPC_PREFIX_SEG (op[-1].opcode)) | |
1734 | { | |
1735 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1736 | bad_insn = true; |
dd7efa79 PB |
1737 | } |
1738 | bad_insn |= insn_validate (op); | |
1739 | } | |
1740 | ||
1741 | if ((ppc_cpu & op->flags) != 0 | |
fe0e921f AM |
1742 | && !(ppc_cpu & op->deprecated) |
1743 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1744 | { | |
1745 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1746 | bad_insn = true; |
fe0e921f | 1747 | } |
dd7efa79 PB |
1748 | } |
1749 | ||
1750 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1751 | for (op = prefix_opcodes; op < op_end; op++) | |
fe0e921f | 1752 | str_hash_insert (ppc_hash, op->name, op, 0); |
dd7efa79 | 1753 | |
b9c361e0 JL |
1754 | op_end = vle_opcodes + vle_num_opcodes; |
1755 | for (op = vle_opcodes; op < op_end; op++) | |
1756 | { | |
1757 | if (ENABLE_CHECKING) | |
1758 | { | |
2ceb7719 | 1759 | unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); |
b9c361e0 JL |
1760 | |
1761 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1762 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1763 | op->name, (unsigned int) (op - vle_opcodes), | |
1764 | (unsigned int) new_seg, (unsigned long long) op->opcode, | |
1765 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 | 1766 | #endif |
2ceb7719 PB |
1767 | |
1768 | /* The major opcodes had better be sorted. Code in the disassembler | |
1769 | assumes the insns are sorted according to major opcode. */ | |
1770 | if (op != vle_opcodes | |
1771 | && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) | |
1772 | { | |
1773 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1774 | bad_insn = true; |
b9c361e0 JL |
1775 | } |
1776 | ||
1777 | bad_insn |= insn_validate (op); | |
c43a438d | 1778 | } |
252b5132 | 1779 | |
bdc70b4a | 1780 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1781 | && !(ppc_cpu & op->deprecated) |
1782 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1783 | { | |
1784 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1785 | bad_insn = true; |
fe0e921f | 1786 | } |
252b5132 RH |
1787 | } |
1788 | ||
74081948 AF |
1789 | /* SPE2 instructions */ |
1790 | if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) | |
1791 | { | |
1792 | op_end = spe2_opcodes + spe2_num_opcodes; | |
1793 | for (op = spe2_opcodes; op < op_end; op++) | |
1794 | { | |
1795 | if (ENABLE_CHECKING) | |
1796 | { | |
1797 | if (op != spe2_opcodes) | |
1798 | { | |
1799 | unsigned old_seg, new_seg; | |
1800 | ||
1801 | old_seg = VLE_OP (op[-1].opcode, op[-1].mask); | |
1802 | old_seg = VLE_OP_TO_SEG (old_seg); | |
1803 | new_seg = VLE_OP (op[0].opcode, op[0].mask); | |
1804 | new_seg = VLE_OP_TO_SEG (new_seg); | |
1805 | ||
1806 | /* The major opcodes had better be sorted. Code in the | |
1807 | disassembler assumes the insns are sorted according to | |
1808 | major opcode. */ | |
1809 | if (new_seg < old_seg) | |
1810 | { | |
1811 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1812 | bad_insn = true; |
74081948 AF |
1813 | } |
1814 | } | |
1815 | ||
1816 | bad_insn |= insn_validate (op); | |
1817 | } | |
1818 | ||
fe0e921f AM |
1819 | if ((ppc_cpu & op->flags) != 0 |
1820 | && !(ppc_cpu & op->deprecated) | |
1821 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1822 | { | |
1823 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1824 | bad_insn = true; |
fe0e921f | 1825 | } |
74081948 AF |
1826 | } |
1827 | ||
1828 | for (op = spe2_opcodes; op < op_end; op++) | |
fe0e921f | 1829 | str_hash_insert (ppc_hash, op->name, op, 0); |
74081948 AF |
1830 | } |
1831 | ||
252b5132 | 1832 | /* Insert the macros into a hash table. */ |
629310ab | 1833 | ppc_macro_hash = str_htab_create (); |
252b5132 RH |
1834 | |
1835 | macro_end = powerpc_macros + powerpc_num_macros; | |
1836 | for (macro = powerpc_macros; macro < macro_end; macro++) | |
fe0e921f AM |
1837 | if (((macro->flags & ppc_cpu) != 0 |
1838 | || (ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1839 | && str_hash_insert (ppc_macro_hash, macro->name, macro, 0) != NULL) | |
1840 | { | |
1841 | as_bad (_("duplicate %s"), macro->name); | |
5b7c81bd | 1842 | bad_insn = true; |
fe0e921f | 1843 | } |
252b5132 | 1844 | |
b84bf58a | 1845 | if (bad_insn) |
252b5132 | 1846 | abort (); |
69c040df AM |
1847 | } |
1848 | ||
1849 | /* This function is called when the assembler starts up. It is called | |
1850 | after the options have been parsed and the output file has been | |
1851 | opened. */ | |
1852 | ||
1853 | void | |
98027b10 | 1854 | md_begin (void) |
69c040df AM |
1855 | { |
1856 | ppc_set_cpu (); | |
1857 | ||
1858 | ppc_cie_data_alignment = ppc_obj64 ? -8 : -4; | |
8fbf7334 | 1859 | ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4; |
69c040df AM |
1860 | |
1861 | #ifdef OBJ_ELF | |
1862 | /* Set the ELF flags if desired. */ | |
1863 | if (ppc_flags && !msolaris) | |
1864 | bfd_set_private_flags (stdoutput, ppc_flags); | |
1865 | #endif | |
1866 | ||
1867 | ppc_setup_opcodes (); | |
252b5132 | 1868 | |
67c1ffbe | 1869 | /* Tell the main code what the endianness is if it is not overridden |
99a814a1 | 1870 | by the user. */ |
252b5132 RH |
1871 | if (!set_target_endian) |
1872 | { | |
1873 | set_target_endian = 1; | |
1874 | target_big_endian = PPC_BIG_ENDIAN; | |
1875 | } | |
1876 | ||
1877 | #ifdef OBJ_XCOFF | |
1878 | ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG); | |
1879 | ||
1b2cb8e2 CC |
1880 | /* Create XCOFF sections with .text in first, as it's creating dummy symbols |
1881 | to serve as initial csects. This forces the text csects to precede the | |
1882 | data csects. These symbols will not be output. */ | |
934cb849 CC |
1883 | ppc_init_xcoff_section (&ppc_xcoff_text_section, text_section); |
1884 | ppc_init_xcoff_section (&ppc_xcoff_data_section, data_section); | |
1885 | ppc_init_xcoff_section (&ppc_xcoff_bss_section, bss_section); | |
252b5132 | 1886 | #endif |
252b5132 RH |
1887 | } |
1888 | ||
6a0c61b7 | 1889 | void |
98027b10 | 1890 | ppc_cleanup (void) |
6a0c61b7 | 1891 | { |
dc1d03fc | 1892 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
1893 | if (ppc_apuinfo_list == NULL) |
1894 | return; | |
1895 | ||
1896 | /* Ok, so write the section info out. We have this layout: | |
1897 | ||
1898 | byte data what | |
1899 | ---- ---- ---- | |
1900 | 0 8 length of "APUinfo\0" | |
1901 | 4 (n*4) number of APU's (4 bytes each) | |
1902 | 8 2 note type 2 | |
1903 | 12 "APUinfo\0" name | |
1904 | 20 APU#1 first APU's info | |
1905 | 24 APU#2 second APU's info | |
1906 | ... ... | |
1907 | */ | |
1908 | { | |
1909 | char *p; | |
1910 | asection *seg = now_seg; | |
1911 | subsegT subseg = now_subseg; | |
1912 | asection *apuinfo_secp = (asection *) NULL; | |
49181a6a | 1913 | unsigned int i; |
6a0c61b7 EZ |
1914 | |
1915 | /* Create the .PPC.EMB.apuinfo section. */ | |
14b57c7c | 1916 | apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0); |
fd361982 | 1917 | bfd_set_section_flags (apuinfo_secp, SEC_HAS_CONTENTS | SEC_READONLY); |
6a0c61b7 EZ |
1918 | |
1919 | p = frag_more (4); | |
1920 | md_number_to_chars (p, (valueT) 8, 4); | |
1921 | ||
1922 | p = frag_more (4); | |
e98d298c | 1923 | md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4); |
6a0c61b7 EZ |
1924 | |
1925 | p = frag_more (4); | |
1926 | md_number_to_chars (p, (valueT) 2, 4); | |
1927 | ||
1928 | p = frag_more (8); | |
14b57c7c | 1929 | strcpy (p, APUINFO_LABEL); |
6a0c61b7 EZ |
1930 | |
1931 | for (i = 0; i < ppc_apuinfo_num; i++) | |
1932 | { | |
b34976b6 AM |
1933 | p = frag_more (4); |
1934 | md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4); | |
6a0c61b7 EZ |
1935 | } |
1936 | ||
1937 | frag_align (2, 0, 0); | |
1938 | ||
1939 | /* We probably can't restore the current segment, for there likely | |
1940 | isn't one yet... */ | |
1941 | if (seg && subseg) | |
1942 | subseg_set (seg, subseg); | |
1943 | } | |
dc1d03fc | 1944 | #endif |
6a0c61b7 EZ |
1945 | } |
1946 | ||
252b5132 RH |
1947 | /* Insert an operand value into an instruction. */ |
1948 | ||
0f873fd5 PB |
1949 | static uint64_t |
1950 | ppc_insert_operand (uint64_t insn, | |
a1867a27 | 1951 | const struct powerpc_operand *operand, |
0f873fd5 | 1952 | int64_t val, |
91d6fa6a | 1953 | ppc_cpu_t cpu, |
3b4dbbbf | 1954 | const char *file, |
a1867a27 | 1955 | unsigned int line) |
252b5132 | 1956 | { |
0f873fd5 | 1957 | int64_t min, max, right; |
eb42fac1 | 1958 | |
b84bf58a AM |
1959 | max = operand->bitm; |
1960 | right = max & -max; | |
1961 | min = 0; | |
1962 | ||
a47622ac | 1963 | if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) |
252b5132 | 1964 | { |
a255f00a AM |
1965 | /* Extend the allowed range for addis to [-32768, 65535]. |
1966 | Similarly for cmpli and some VLE high part insns. For 64-bit | |
1967 | it would be good to disable this for signed fields since the | |
a47622ac AM |
1968 | value is sign extended into the high 32 bits of the register. |
1969 | If the value is, say, an address, then we might care about | |
1970 | the high bits. However, gcc as of 2014-06 uses unsigned | |
1971 | values when loading the high part of 64-bit constants using | |
a255f00a AM |
1972 | lis. */ |
1973 | min = ~(max >> 1) & -right; | |
a47622ac AM |
1974 | } |
1975 | else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
1976 | { | |
1977 | max = (max >> 1) & -right; | |
931774a9 | 1978 | min = ~max & -right; |
b84bf58a | 1979 | } |
252b5132 | 1980 | |
b84bf58a | 1981 | if ((operand->flags & PPC_OPERAND_PLUS1) != 0) |
3896c469 | 1982 | max++; |
252b5132 | 1983 | |
b84bf58a | 1984 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
a1867a27 | 1985 | { |
0f873fd5 | 1986 | int64_t tmp = min; |
a1867a27 AM |
1987 | min = -max; |
1988 | max = -tmp; | |
1989 | } | |
b84bf58a | 1990 | |
a1867a27 AM |
1991 | if (min <= max) |
1992 | { | |
1993 | /* Some people write constants with the sign extension done by | |
1994 | hand but only up to 32 bits. This shouldn't really be valid, | |
1995 | but, to permit this code to assemble on a 64-bit host, we | |
1996 | sign extend the 32-bit value to 64 bits if so doing makes the | |
8acf1435 PB |
1997 | value valid. We only do this for operands that are 32-bits or |
1998 | smaller. */ | |
a1867a27 | 1999 | if (val > max |
8acf1435 | 2000 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2001 | && (val - (1LL << 32)) >= min |
2002 | && (val - (1LL << 32)) <= max | |
2003 | && ((val - (1LL << 32)) & (right - 1)) == 0) | |
2004 | val = val - (1LL << 32); | |
a1867a27 AM |
2005 | |
2006 | /* Similarly, people write expressions like ~(1<<15), and expect | |
2007 | this to be OK for a 32-bit unsigned value. */ | |
2008 | else if (val < min | |
8acf1435 | 2009 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2010 | && (val + (1LL << 32)) >= min |
2011 | && (val + (1LL << 32)) <= max | |
2012 | && ((val + (1LL << 32)) & (right - 1)) == 0) | |
2013 | val = val + (1LL << 32); | |
a1867a27 AM |
2014 | |
2015 | else if (val < min | |
2016 | || val > max | |
2017 | || (val & (right - 1)) != 0) | |
2018 | as_bad_value_out_of_range (_("operand"), val, min, max, file, line); | |
2019 | } | |
b84bf58a | 2020 | |
252b5132 RH |
2021 | if (operand->insert) |
2022 | { | |
2023 | const char *errmsg; | |
2024 | ||
2025 | errmsg = NULL; | |
0f873fd5 | 2026 | insn = (*operand->insert) (insn, val, cpu, &errmsg); |
252b5132 | 2027 | if (errmsg != (const char *) NULL) |
ee2c9aa9 | 2028 | as_bad_where (file, line, "%s", errmsg); |
252b5132 | 2029 | } |
b9c361e0 | 2030 | else if (operand->shift >= 0) |
0f873fd5 | 2031 | insn |= (val & operand->bitm) << operand->shift; |
b9c361e0 | 2032 | else |
0f873fd5 | 2033 | insn |= (val & operand->bitm) >> -operand->shift; |
252b5132 RH |
2034 | |
2035 | return insn; | |
2036 | } | |
2037 | ||
2038 | \f | |
2039 | #ifdef OBJ_ELF | |
2040 | /* Parse @got, etc. and return the desired relocation. */ | |
2041 | static bfd_reloc_code_real_type | |
98027b10 | 2042 | ppc_elf_suffix (char **str_p, expressionS *exp_p) |
252b5132 RH |
2043 | { |
2044 | struct map_bfd { | |
e0471c16 | 2045 | const char *string; |
b7d7dc63 AM |
2046 | unsigned int length : 8; |
2047 | unsigned int valid32 : 1; | |
2048 | unsigned int valid64 : 1; | |
2049 | unsigned int reloc; | |
252b5132 RH |
2050 | }; |
2051 | ||
2052 | char ident[20]; | |
2053 | char *str = *str_p; | |
2054 | char *str2; | |
2055 | int ch; | |
2056 | int len; | |
15c1449b | 2057 | const struct map_bfd *ptr; |
252b5132 | 2058 | |
b7d7dc63 AM |
2059 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } |
2060 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2061 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
252b5132 | 2062 | |
15c1449b | 2063 | static const struct map_bfd mapping[] = { |
b7d7dc63 AM |
2064 | MAP ("l", BFD_RELOC_LO16), |
2065 | MAP ("h", BFD_RELOC_HI16), | |
2066 | MAP ("ha", BFD_RELOC_HI16_S), | |
2067 | MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN), | |
2068 | MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN), | |
2069 | MAP ("got", BFD_RELOC_16_GOTOFF), | |
2070 | MAP ("got@l", BFD_RELOC_LO16_GOTOFF), | |
2071 | MAP ("got@h", BFD_RELOC_HI16_GOTOFF), | |
2072 | MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), | |
2073 | MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), | |
2074 | MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), | |
2075 | MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), | |
2076 | MAP ("copy", BFD_RELOC_PPC_COPY), | |
2077 | MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), | |
2078 | MAP ("sectoff", BFD_RELOC_16_BASEREL), | |
2079 | MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), | |
2080 | MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), | |
2081 | MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), | |
2082 | MAP ("tls", BFD_RELOC_PPC_TLS), | |
2083 | MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD), | |
2084 | MAP ("dtprel", BFD_RELOC_PPC_DTPREL), | |
2085 | MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO), | |
2086 | MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI), | |
2087 | MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA), | |
2088 | MAP ("tprel", BFD_RELOC_PPC_TPREL), | |
2089 | MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO), | |
2090 | MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI), | |
2091 | MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA), | |
2092 | MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16), | |
2093 | MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO), | |
2094 | MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI), | |
2095 | MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA), | |
2096 | MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16), | |
2097 | MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO), | |
2098 | MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI), | |
2099 | MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA), | |
2100 | MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16), | |
2101 | MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO), | |
2102 | MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI), | |
2103 | MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA), | |
2104 | MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16), | |
2105 | MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO), | |
2106 | MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI), | |
2107 | MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA), | |
2108 | MAP32 ("fixup", BFD_RELOC_CTOR), | |
2109 | MAP32 ("plt", BFD_RELOC_24_PLT_PCREL), | |
2110 | MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL), | |
2111 | MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC), | |
2112 | MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC), | |
2113 | MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL), | |
2114 | MAP32 ("sdarel", BFD_RELOC_GPREL16), | |
b9c361e0 JL |
2115 | MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A), |
2116 | MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A), | |
2117 | MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A), | |
b7d7dc63 AM |
2118 | MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32), |
2119 | MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16), | |
2120 | MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO), | |
2121 | MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI), | |
2122 | MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA), | |
2123 | MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16), | |
2124 | MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL), | |
2125 | MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16), | |
2126 | MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21), | |
b9c361e0 | 2127 | MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO), |
b7d7dc63 AM |
2128 | MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF), |
2129 | MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16), | |
2130 | MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO), | |
2131 | MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI), | |
2132 | MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA), | |
2133 | MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD), | |
2134 | MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA), | |
2135 | MAP32 ("xgot", BFD_RELOC_PPC_TOC16), | |
f9c6b907 AM |
2136 | MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH), |
2137 | MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA), | |
b7d7dc63 AM |
2138 | MAP64 ("higher", BFD_RELOC_PPC64_HIGHER), |
2139 | MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S), | |
2140 | MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST), | |
2141 | MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), | |
2142 | MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), | |
2143 | MAP64 ("toc", BFD_RELOC_PPC_TOC16), | |
2144 | MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), | |
2145 | MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), | |
2146 | MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), | |
f9c6b907 AM |
2147 | MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH), |
2148 | MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA), | |
b7d7dc63 AM |
2149 | MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER), |
2150 | MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), | |
2151 | MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), | |
2152 | MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), | |
45965137 | 2153 | MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), |
f9c6b907 AM |
2154 | MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), |
2155 | MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), | |
b7d7dc63 AM |
2156 | MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), |
2157 | MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), | |
2158 | MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), | |
2159 | MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), | |
05d0e962 | 2160 | MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC), |
5663e321 AM |
2161 | MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34), |
2162 | MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34), | |
2163 | MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34), | |
c213164a | 2164 | MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL), |
87c69f97 AM |
2165 | MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34), |
2166 | MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34), | |
2167 | MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34), | |
2168 | MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34), | |
5663e321 AM |
2169 | MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34), |
2170 | MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34), | |
2171 | MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34), | |
2172 | MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34), | |
62ebcb5c | 2173 | { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } |
252b5132 RH |
2174 | }; |
2175 | ||
2176 | if (*str++ != '@') | |
62ebcb5c | 2177 | return BFD_RELOC_NONE; |
252b5132 RH |
2178 | |
2179 | for (ch = *str, str2 = ident; | |
2180 | (str2 < ident + sizeof (ident) - 1 | |
3882b010 | 2181 | && (ISALNUM (ch) || ch == '@')); |
252b5132 RH |
2182 | ch = *++str) |
2183 | { | |
3882b010 | 2184 | *str2++ = TOLOWER (ch); |
252b5132 RH |
2185 | } |
2186 | ||
2187 | *str2 = '\0'; | |
2188 | len = str2 - ident; | |
2189 | ||
2190 | ch = ident[0]; | |
2191 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2192 | if (ch == ptr->string[0] | |
2193 | && len == ptr->length | |
b7d7dc63 AM |
2194 | && memcmp (ident, ptr->string, ptr->length) == 0 |
2195 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
252b5132 | 2196 | { |
15c1449b AM |
2197 | int reloc = ptr->reloc; |
2198 | ||
32d71569 | 2199 | if (!ppc_obj64 && (exp_p->X_op == O_big || exp_p->X_add_number != 0)) |
727fc41e AM |
2200 | { |
2201 | switch (reloc) | |
2202 | { | |
2203 | case BFD_RELOC_16_GOTOFF: | |
2204 | case BFD_RELOC_LO16_GOTOFF: | |
2205 | case BFD_RELOC_HI16_GOTOFF: | |
2206 | case BFD_RELOC_HI16_S_GOTOFF: | |
e47d413a AM |
2207 | as_warn (_("symbol+offset@%s means symbol@%s+offset"), |
2208 | ptr->string, ptr->string); | |
727fc41e AM |
2209 | break; |
2210 | ||
2211 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2212 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2213 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2214 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2215 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2216 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2217 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2218 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2219 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2220 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2221 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2222 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2223 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2224 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2225 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2226 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
e47d413a | 2227 | as_bad (_("symbol+offset@%s not supported"), ptr->string); |
727fc41e AM |
2228 | break; |
2229 | } | |
2230 | } | |
5f6db75a AM |
2231 | |
2232 | /* Now check for identifier@suffix+constant. */ | |
2233 | if (*str == '-' || *str == '+') | |
252b5132 | 2234 | { |
5f6db75a AM |
2235 | char *orig_line = input_line_pointer; |
2236 | expressionS new_exp; | |
2237 | ||
2238 | input_line_pointer = str; | |
2239 | expression (&new_exp); | |
32d71569 | 2240 | if (new_exp.X_op == O_constant && exp_p->X_op != O_big) |
252b5132 | 2241 | { |
5f6db75a AM |
2242 | exp_p->X_add_number += new_exp.X_add_number; |
2243 | str = input_line_pointer; | |
252b5132 | 2244 | } |
32d71569 | 2245 | input_line_pointer = orig_line; |
252b5132 | 2246 | } |
252b5132 | 2247 | *str_p = str; |
0baf16f2 | 2248 | |
2b3c4602 | 2249 | if (reloc == (int) BFD_RELOC_PPC64_TOC |
9f2b53d7 AM |
2250 | && exp_p->X_op == O_symbol |
2251 | && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0) | |
0baf16f2 | 2252 | { |
9f2b53d7 AM |
2253 | /* Change the symbol so that the dummy .TOC. symbol can be |
2254 | omitted from the object file. */ | |
0baf16f2 AM |
2255 | exp_p->X_add_symbol = &abs_symbol; |
2256 | } | |
2257 | ||
7aba54da AM |
2258 | if (reloc == BFD_RELOC_PPC64_REL24_NOTOC |
2259 | && (ppc_cpu & PPC_OPCODE_POWER10) == 0) | |
2260 | reloc = BFD_RELOC_PPC64_REL24_P9NOTOC; | |
2261 | ||
15c1449b | 2262 | return (bfd_reloc_code_real_type) reloc; |
252b5132 RH |
2263 | } |
2264 | ||
62ebcb5c | 2265 | return BFD_RELOC_NONE; |
252b5132 RH |
2266 | } |
2267 | ||
62ebcb5c | 2268 | /* Support @got, etc. on constants emitted via .short, .int etc. */ |
99a814a1 | 2269 | |
62ebcb5c AM |
2270 | bfd_reloc_code_real_type |
2271 | ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) | |
2272 | { | |
2273 | expression (exp); | |
2274 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2275 | return ppc_elf_suffix (&input_line_pointer, exp); | |
2276 | return BFD_RELOC_NONE; | |
252b5132 RH |
2277 | } |
2278 | ||
bf7279d5 AM |
2279 | /* Warn when emitting data to code sections, unless we are emitting |
2280 | a relocation that ld --ppc476-workaround uses to recognise data | |
2281 | *and* there was an unconditional branch prior to the data. */ | |
2282 | ||
2283 | void | |
2284 | ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, | |
2285 | unsigned int nbytes, fixS *fix) | |
2286 | { | |
2287 | if (warn_476 | |
2288 | && (now_seg->flags & SEC_CODE) != 0 | |
2289 | && (nbytes != 4 | |
2290 | || fix == NULL | |
2291 | || !(fix->fx_r_type == BFD_RELOC_32 | |
2292 | || fix->fx_r_type == BFD_RELOC_CTOR | |
2293 | || fix->fx_r_type == BFD_RELOC_32_PCREL) | |
2294 | || !(last_seg == now_seg && last_subseg == now_subseg) | |
2295 | || !((last_insn & (0x3f << 26)) == (18u << 26) | |
2296 | || ((last_insn & (0x3f << 26)) == (16u << 26) | |
2297 | && (last_insn & (0x14 << 21)) == (0x14 << 21)) | |
2298 | || ((last_insn & (0x3f << 26)) == (19u << 26) | |
2299 | && (last_insn & (0x3ff << 1)) == (16u << 1) | |
2300 | && (last_insn & (0x14 << 21)) == (0x14 << 21))))) | |
2301 | { | |
2302 | /* Flag that we've warned. */ | |
2303 | if (fix != NULL) | |
2304 | fix->fx_tcbit = 1; | |
2305 | ||
2306 | as_warn (_("data in executable section")); | |
2307 | } | |
2308 | } | |
2309 | ||
252b5132 RH |
2310 | /* Solaris pseduo op to change to the .rodata section. */ |
2311 | static void | |
98027b10 | 2312 | ppc_elf_rdata (int xxx) |
252b5132 RH |
2313 | { |
2314 | char *save_line = input_line_pointer; | |
2315 | static char section[] = ".rodata\n"; | |
2316 | ||
99a814a1 | 2317 | /* Just pretend this is .section .rodata */ |
252b5132 RH |
2318 | input_line_pointer = section; |
2319 | obj_elf_section (xxx); | |
2320 | ||
2321 | input_line_pointer = save_line; | |
2322 | } | |
2323 | ||
99a814a1 | 2324 | /* Pseudo op to make file scope bss items. */ |
252b5132 | 2325 | static void |
98027b10 | 2326 | ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED) |
252b5132 | 2327 | { |
98027b10 AM |
2328 | char *name; |
2329 | char c; | |
2330 | char *p; | |
252b5132 | 2331 | offsetT size; |
98027b10 | 2332 | symbolS *symbolP; |
252b5132 RH |
2333 | offsetT align; |
2334 | segT old_sec; | |
2335 | int old_subsec; | |
2336 | char *pfrag; | |
2337 | int align2; | |
2338 | ||
d02603dc | 2339 | c = get_symbol_name (&name); |
252b5132 | 2340 | |
d02603dc | 2341 | /* Just after name is now '\0'. */ |
252b5132 RH |
2342 | p = input_line_pointer; |
2343 | *p = c; | |
d02603dc | 2344 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
2345 | if (*input_line_pointer != ',') |
2346 | { | |
d6ed37ed | 2347 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
2348 | ignore_rest_of_line (); |
2349 | return; | |
2350 | } | |
2351 | ||
2352 | input_line_pointer++; /* skip ',' */ | |
2353 | if ((size = get_absolute_expression ()) < 0) | |
2354 | { | |
2355 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); | |
2356 | ignore_rest_of_line (); | |
2357 | return; | |
2358 | } | |
2359 | ||
2360 | /* The third argument to .lcomm is the alignment. */ | |
2361 | if (*input_line_pointer != ',') | |
2362 | align = 8; | |
2363 | else | |
2364 | { | |
2365 | ++input_line_pointer; | |
2366 | align = get_absolute_expression (); | |
2367 | if (align <= 0) | |
2368 | { | |
2369 | as_warn (_("ignoring bad alignment")); | |
2370 | align = 8; | |
2371 | } | |
2372 | } | |
2373 | ||
2374 | *p = 0; | |
2375 | symbolP = symbol_find_or_make (name); | |
2376 | *p = c; | |
2377 | ||
2378 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
2379 | { | |
d6ed37ed | 2380 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
2381 | S_GET_NAME (symbolP)); |
2382 | ignore_rest_of_line (); | |
2383 | return; | |
2384 | } | |
2385 | ||
2386 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
2387 | { | |
d6ed37ed | 2388 | as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
2389 | S_GET_NAME (symbolP), |
2390 | (long) S_GET_VALUE (symbolP), | |
2391 | (long) size); | |
2392 | ||
2393 | ignore_rest_of_line (); | |
2394 | return; | |
2395 | } | |
2396 | ||
99a814a1 | 2397 | /* Allocate_bss. */ |
252b5132 RH |
2398 | old_sec = now_seg; |
2399 | old_subsec = now_subseg; | |
2400 | if (align) | |
2401 | { | |
99a814a1 | 2402 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
2403 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); |
2404 | if (align != 1) | |
2405 | { | |
d6ed37ed | 2406 | as_bad (_("common alignment not a power of 2")); |
252b5132 RH |
2407 | ignore_rest_of_line (); |
2408 | return; | |
2409 | } | |
2410 | } | |
2411 | else | |
2412 | align2 = 0; | |
2413 | ||
2414 | record_alignment (bss_section, align2); | |
cbe02d4f | 2415 | subseg_set (bss_section, 1); |
252b5132 RH |
2416 | if (align2) |
2417 | frag_align (align2, 0, 0); | |
2418 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
2419 | symbol_get_frag (symbolP)->fr_symbol = 0; |
2420 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
2421 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
2422 | (char *) 0); | |
2423 | *pfrag = 0; | |
2424 | S_SET_SIZE (symbolP, size); | |
2425 | S_SET_SEGMENT (symbolP, bss_section); | |
2426 | subseg_set (old_sec, old_subsec); | |
2427 | demand_empty_rest_of_line (); | |
2428 | } | |
2429 | ||
6911b7dc AM |
2430 | /* Pseudo op to set symbol local entry point. */ |
2431 | static void | |
2432 | ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED) | |
2433 | { | |
d02603dc NC |
2434 | char *name; |
2435 | char c = get_symbol_name (&name); | |
6911b7dc AM |
2436 | char *p; |
2437 | expressionS exp; | |
2438 | symbolS *sym; | |
2439 | asymbol *bfdsym; | |
2440 | elf_symbol_type *elfsym; | |
2441 | ||
2442 | p = input_line_pointer; | |
2443 | *p = c; | |
d02603dc | 2444 | SKIP_WHITESPACE_AFTER_NAME (); |
6911b7dc AM |
2445 | if (*input_line_pointer != ',') |
2446 | { | |
2447 | *p = 0; | |
2448 | as_bad (_("expected comma after name `%s' in .localentry directive"), | |
2449 | name); | |
2450 | *p = c; | |
2451 | ignore_rest_of_line (); | |
2452 | return; | |
2453 | } | |
2454 | input_line_pointer++; | |
2455 | expression (&exp); | |
2456 | if (exp.X_op == O_absent) | |
2457 | { | |
2458 | as_bad (_("missing expression in .localentry directive")); | |
2459 | exp.X_op = O_constant; | |
2460 | exp.X_add_number = 0; | |
2461 | } | |
2462 | *p = 0; | |
2463 | sym = symbol_find_or_make (name); | |
2464 | *p = c; | |
2465 | ||
2466 | if (resolve_expression (&exp) | |
2467 | && exp.X_op == O_constant) | |
2468 | { | |
33cb30a1 | 2469 | unsigned int encoded, ok; |
6911b7dc | 2470 | |
33cb30a1 AM |
2471 | ok = 1; |
2472 | if (exp.X_add_number == 1 || exp.X_add_number == 7) | |
2473 | encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT; | |
6911b7dc | 2474 | else |
33cb30a1 AM |
2475 | { |
2476 | encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number); | |
2477 | if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded)) | |
2478 | { | |
2479 | as_bad (_(".localentry expression for `%s' " | |
2480 | "is not a valid power of 2"), S_GET_NAME (sym)); | |
2481 | ok = 0; | |
2482 | } | |
2483 | } | |
2484 | if (ok) | |
6911b7dc AM |
2485 | { |
2486 | bfdsym = symbol_get_bfdsym (sym); | |
c1229f84 | 2487 | elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
2488 | gas_assert (elfsym); |
2489 | elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK; | |
2490 | elfsym->internal_elf_sym.st_other |= encoded; | |
2491 | if (ppc_abiversion == 0) | |
2492 | ppc_abiversion = 2; | |
2493 | } | |
2494 | } | |
2495 | else | |
2496 | as_bad (_(".localentry expression for `%s' " | |
2497 | "does not evaluate to a constant"), S_GET_NAME (sym)); | |
2498 | ||
2499 | demand_empty_rest_of_line (); | |
2500 | } | |
2501 | ||
ee67d69a AM |
2502 | /* Pseudo op to set ABI version. */ |
2503 | static void | |
2504 | ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED) | |
2505 | { | |
2506 | expressionS exp; | |
2507 | ||
2508 | expression (&exp); | |
2509 | if (exp.X_op == O_absent) | |
2510 | { | |
2511 | as_bad (_("missing expression in .abiversion directive")); | |
2512 | exp.X_op = O_constant; | |
2513 | exp.X_add_number = 0; | |
2514 | } | |
2515 | ||
2516 | if (resolve_expression (&exp) | |
2517 | && exp.X_op == O_constant) | |
2518 | ppc_abiversion = exp.X_add_number; | |
2519 | else | |
2520 | as_bad (_(".abiversion expression does not evaluate to a constant")); | |
2521 | demand_empty_rest_of_line (); | |
2522 | } | |
2523 | ||
005d79fd AM |
2524 | /* Parse a .gnu_attribute directive. */ |
2525 | static void | |
2526 | ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) | |
2527 | { | |
2528 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); | |
2529 | ||
2530 | /* Check validity of defined powerpc tags. */ | |
2531 | if (tag == Tag_GNU_Power_ABI_FP | |
2532 | || tag == Tag_GNU_Power_ABI_Vector | |
2533 | || tag == Tag_GNU_Power_ABI_Struct_Return) | |
2534 | { | |
2535 | unsigned int val; | |
2536 | ||
2537 | val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); | |
2538 | ||
2539 | if ((tag == Tag_GNU_Power_ABI_FP && val > 15) | |
2540 | || (tag == Tag_GNU_Power_ABI_Vector && val > 3) | |
2541 | || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2)) | |
2542 | as_warn (_("unknown .gnu_attribute value")); | |
2543 | } | |
2544 | } | |
2545 | ||
ee67d69a AM |
2546 | /* Set ABI version in output file. */ |
2547 | void | |
2548 | ppc_elf_end (void) | |
2549 | { | |
2550 | if (ppc_obj64 && ppc_abiversion != 0) | |
2551 | { | |
2552 | elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI; | |
2553 | elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI; | |
2554 | } | |
22f72c48 AM |
2555 | /* Any selection of opcodes based on ppc_cpu after gas has finished |
2556 | parsing the file is invalid. md_apply_fix and ppc_handle_align | |
2557 | must select opcodes based on the machine in force at the point | |
2558 | where the fixup or alignment frag was created, not the machine in | |
2559 | force at the end of file. */ | |
2560 | ppc_cpu = 0; | |
ee67d69a AM |
2561 | } |
2562 | ||
252b5132 RH |
2563 | /* Validate any relocations emitted for -mrelocatable, possibly adding |
2564 | fixups for word relocations in writable segments, so we can adjust | |
2565 | them at runtime. */ | |
2566 | static void | |
98027b10 | 2567 | ppc_elf_validate_fix (fixS *fixp, segT seg) |
252b5132 RH |
2568 | { |
2569 | if (fixp->fx_done || fixp->fx_pcrel) | |
2570 | return; | |
2571 | ||
2572 | switch (shlib) | |
2573 | { | |
2574 | case SHLIB_NONE: | |
2575 | case SHLIB_PIC: | |
2576 | return; | |
2577 | ||
5d6f4f16 | 2578 | case SHLIB_MRELOCATABLE: |
62ebcb5c | 2579 | if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF |
252b5132 RH |
2580 | && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF |
2581 | && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
2582 | && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
1cfc59d5 | 2583 | && fixp->fx_r_type != BFD_RELOC_16_BASEREL |
252b5132 RH |
2584 | && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL |
2585 | && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL | |
2586 | && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL | |
e138127a | 2587 | && (seg->flags & SEC_LOAD) != 0 |
252b5132 RH |
2588 | && strcmp (segment_name (seg), ".got2") != 0 |
2589 | && strcmp (segment_name (seg), ".dtors") != 0 | |
2590 | && strcmp (segment_name (seg), ".ctors") != 0 | |
2591 | && strcmp (segment_name (seg), ".fixup") != 0 | |
252b5132 RH |
2592 | && strcmp (segment_name (seg), ".gcc_except_table") != 0 |
2593 | && strcmp (segment_name (seg), ".eh_frame") != 0 | |
2594 | && strcmp (segment_name (seg), ".ex_shared") != 0) | |
2595 | { | |
2596 | if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0 | |
2597 | || fixp->fx_r_type != BFD_RELOC_CTOR) | |
2598 | { | |
2599 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d6ed37ed | 2600 | _("relocation cannot be done when using -mrelocatable")); |
252b5132 RH |
2601 | } |
2602 | } | |
2603 | return; | |
2604 | } | |
2605 | } | |
0baf16f2 | 2606 | |
7e8d4ab4 AM |
2607 | /* Prevent elf_frob_file_before_adjust removing a weak undefined |
2608 | function descriptor sym if the corresponding code sym is used. */ | |
2609 | ||
2610 | void | |
98027b10 | 2611 | ppc_frob_file_before_adjust (void) |
0baf16f2 | 2612 | { |
7e8d4ab4 | 2613 | symbolS *symp; |
9232bbb0 | 2614 | asection *toc; |
0baf16f2 | 2615 | |
7e8d4ab4 AM |
2616 | if (!ppc_obj64) |
2617 | return; | |
2618 | ||
2619 | for (symp = symbol_rootP; symp; symp = symbol_next (symp)) | |
0baf16f2 | 2620 | { |
7e8d4ab4 AM |
2621 | const char *name; |
2622 | char *dotname; | |
2623 | symbolS *dotsym; | |
7e8d4ab4 AM |
2624 | |
2625 | name = S_GET_NAME (symp); | |
2626 | if (name[0] == '.') | |
2627 | continue; | |
2628 | ||
2629 | if (! S_IS_WEAK (symp) | |
2630 | || S_IS_DEFINED (symp)) | |
2631 | continue; | |
2632 | ||
a44e2901 | 2633 | dotname = concat (".", name, (char *) NULL); |
461b725f | 2634 | dotsym = symbol_find_noref (dotname, 1); |
7e8d4ab4 AM |
2635 | free (dotname); |
2636 | if (dotsym != NULL && (symbol_used_p (dotsym) | |
2637 | || symbol_used_in_reloc_p (dotsym))) | |
670ec21d NC |
2638 | symbol_mark_used (symp); |
2639 | ||
0baf16f2 AM |
2640 | } |
2641 | ||
9232bbb0 AM |
2642 | toc = bfd_get_section_by_name (stdoutput, ".toc"); |
2643 | if (toc != NULL | |
01efc3af | 2644 | && toc_reloc_types != has_large_toc_reloc |
fd361982 | 2645 | && bfd_section_size (toc) > 0x10000) |
9232bbb0 | 2646 | as_warn (_("TOC section size exceeds 64k")); |
a38a07e0 AM |
2647 | } |
2648 | ||
2649 | /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be | |
2650 | emitted. Other uses of .TOC. will cause the symbol to be marked | |
2651 | with BSF_KEEP in md_apply_fix. */ | |
9232bbb0 | 2652 | |
a38a07e0 AM |
2653 | void |
2654 | ppc_elf_adjust_symtab (void) | |
2655 | { | |
2656 | if (ppc_obj64) | |
2657 | { | |
2658 | symbolS *symp; | |
2659 | symp = symbol_find (".TOC."); | |
2660 | if (symp != NULL) | |
2661 | { | |
2662 | asymbol *bsym = symbol_get_bfdsym (symp); | |
2663 | if ((bsym->flags & BSF_KEEP) == 0) | |
2664 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
a38a07e0 AM |
2665 | } |
2666 | } | |
0baf16f2 | 2667 | } |
252b5132 | 2668 | #endif /* OBJ_ELF */ |
4a403be0 CC |
2669 | |
2670 | #ifdef OBJ_XCOFF | |
2671 | /* Parse XCOFF relocations. */ | |
2672 | static bfd_reloc_code_real_type | |
2673 | ppc_xcoff_suffix (char **str_p) | |
2674 | { | |
2675 | struct map_bfd { | |
2676 | const char *string; | |
2677 | unsigned int length : 8; | |
2678 | unsigned int valid32 : 1; | |
2679 | unsigned int valid64 : 1; | |
2680 | unsigned int reloc; | |
2681 | }; | |
2682 | ||
2683 | char ident[20]; | |
2684 | char *str = *str_p; | |
2685 | char *str2; | |
2686 | int ch; | |
2687 | int len; | |
2688 | const struct map_bfd *ptr; | |
2689 | ||
2690 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } | |
2691 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2692 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
2693 | ||
2694 | static const struct map_bfd mapping[] = { | |
2695 | MAP ("l", BFD_RELOC_PPC_TOC16_LO), | |
2696 | MAP ("u", BFD_RELOC_PPC_TOC16_HI), | |
1b2cb8e2 CC |
2697 | MAP32 ("ie", BFD_RELOC_PPC_TLSIE), |
2698 | MAP32 ("ld", BFD_RELOC_PPC_TLSLD), | |
2699 | MAP32 ("le", BFD_RELOC_PPC_TLSLE), | |
2700 | MAP32 ("m", BFD_RELOC_PPC_TLSM), | |
2701 | MAP32 ("ml", BFD_RELOC_PPC_TLSML), | |
2702 | MAP64 ("ie", BFD_RELOC_PPC64_TLSIE), | |
2703 | MAP64 ("ld", BFD_RELOC_PPC64_TLSLD), | |
2704 | MAP64 ("le", BFD_RELOC_PPC64_TLSLE), | |
2705 | MAP64 ("m", BFD_RELOC_PPC64_TLSM), | |
2706 | MAP64 ("ml", BFD_RELOC_PPC64_TLSML), | |
4a403be0 CC |
2707 | }; |
2708 | ||
2709 | if (*str++ != '@') | |
2710 | return BFD_RELOC_NONE; | |
2711 | ||
2712 | for (ch = *str, str2 = ident; | |
2713 | (str2 < ident + sizeof (ident) - 1 | |
2714 | && (ISALNUM (ch) || ch == '@')); | |
2715 | ch = *++str) | |
2716 | { | |
2717 | *str2++ = TOLOWER (ch); | |
2718 | } | |
2719 | ||
2720 | *str2 = '\0'; | |
2721 | len = str2 - ident; | |
2722 | ||
2723 | ch = ident[0]; | |
2724 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2725 | if (ch == ptr->string[0] | |
2726 | && len == ptr->length | |
2727 | && memcmp (ident, ptr->string, ptr->length) == 0 | |
2728 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
2729 | { | |
2730 | *str_p = str; | |
2731 | return (bfd_reloc_code_real_type) ptr->reloc; | |
2732 | } | |
2733 | ||
2734 | return BFD_RELOC_NONE; | |
2735 | } | |
2736 | ||
2737 | /* Restore XCOFF addis instruction to ELF format. | |
2738 | AIX often generates addis instructions using "addis RT,D(RA)" | |
2739 | format instead of the ELF "addis RT,RA,SI" one. | |
2740 | On entry RT_E is at the comma after RT, D_E is at the open | |
2741 | parenthesis after D, and RA_E is at the close parenthesis after RA. */ | |
2742 | static void | |
2743 | ppc_xcoff_fixup_addis (char *rt_e, char *d_e, char *ra_e) | |
2744 | { | |
2745 | size_t ra_size = ra_e - d_e - 1; | |
2746 | char *save_ra = xmalloc (ra_size); | |
2747 | ||
2748 | /* Copy RA. */ | |
2749 | memcpy (save_ra, d_e + 1, ra_size); | |
2750 | /* Shuffle D to make room for RA, copying the comma too. */ | |
2751 | memmove (rt_e + ra_size + 1, rt_e, d_e - rt_e); | |
2752 | /* Erase the trailing ')', keeping any rubbish for potential errors. */ | |
2753 | memmove (ra_e, ra_e + 1, strlen (ra_e)); | |
2754 | /* Write RA back. */ | |
2755 | memcpy (rt_e + 1, save_ra, ra_size); | |
2756 | free (save_ra); | |
2757 | } | |
2758 | ||
1b2cb8e2 CC |
2759 | /* Support @ie, etc. on constants emitted via .short, .int etc. */ |
2760 | ||
2761 | bfd_reloc_code_real_type | |
2762 | ppc_xcoff_parse_cons (expressionS *exp, unsigned int nbytes) | |
2763 | { | |
2764 | expression (exp); | |
2765 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2766 | return ppc_xcoff_suffix (&input_line_pointer); | |
2767 | ||
2768 | /* There isn't any @ symbol for default TLS relocations (R_TLS). */ | |
2769 | if (exp->X_add_symbol != NULL | |
2770 | && (symbol_get_tc (exp->X_add_symbol)->symbol_class == XMC_TL | |
2771 | || symbol_get_tc (exp->X_add_symbol)->symbol_class == XMC_UL)) | |
2772 | return (ppc_obj64 ? BFD_RELOC_PPC64_TLSGD: BFD_RELOC_PPC_TLSGD); | |
2773 | ||
2774 | return BFD_RELOC_NONE; | |
2775 | } | |
2776 | ||
4a403be0 | 2777 | #endif /* OBJ_XCOFF */ |
252b5132 | 2778 | \f |
3e60bf4d | 2779 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
3b8b57a9 AM |
2780 | /* See whether a symbol is in the TOC section. */ |
2781 | ||
2782 | static int | |
2783 | ppc_is_toc_sym (symbolS *sym) | |
2784 | { | |
3e60bf4d | 2785 | #ifdef OBJ_XCOFF |
9f6e76f4 | 2786 | return (symbol_get_tc (sym)->symbol_class == XMC_TC |
4a403be0 | 2787 | || symbol_get_tc (sym)->symbol_class == XMC_TE |
9f6e76f4 | 2788 | || symbol_get_tc (sym)->symbol_class == XMC_TC0); |
f50c47f1 | 2789 | #endif |
3e60bf4d AM |
2790 | #ifdef OBJ_ELF |
2791 | const char *sname = segment_name (S_GET_SEGMENT (sym)); | |
2792 | if (ppc_obj64) | |
2793 | return strcmp (sname, ".toc") == 0; | |
2794 | else | |
2795 | return strcmp (sname, ".got") == 0; | |
2796 | #endif | |
2797 | } | |
2798 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ | |
252b5132 RH |
2799 | \f |
2800 | ||
dc1d03fc | 2801 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
2802 | #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff)) |
2803 | static void | |
98027b10 | 2804 | ppc_apuinfo_section_add (unsigned int apu, unsigned int version) |
6a0c61b7 EZ |
2805 | { |
2806 | unsigned int i; | |
2807 | ||
2808 | /* Check we don't already exist. */ | |
2809 | for (i = 0; i < ppc_apuinfo_num; i++) | |
dc1d03fc | 2810 | if (ppc_apuinfo_list[i] == APUID (apu, version)) |
6a0c61b7 | 2811 | return; |
b34976b6 | 2812 | |
6a0c61b7 EZ |
2813 | if (ppc_apuinfo_num == ppc_apuinfo_num_alloc) |
2814 | { | |
2815 | if (ppc_apuinfo_num_alloc == 0) | |
2816 | { | |
2817 | ppc_apuinfo_num_alloc = 4; | |
325801bd | 2818 | ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc); |
6a0c61b7 EZ |
2819 | } |
2820 | else | |
2821 | { | |
2822 | ppc_apuinfo_num_alloc += 4; | |
325801bd TS |
2823 | ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list, |
2824 | ppc_apuinfo_num_alloc); | |
6a0c61b7 EZ |
2825 | } |
2826 | } | |
dc1d03fc | 2827 | ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version); |
6a0c61b7 EZ |
2828 | } |
2829 | #undef APUID | |
dc1d03fc | 2830 | #endif |
6a0c61b7 | 2831 | \f |
dd7efa79 PB |
2832 | /* Various frobbings of labels and their addresses. */ |
2833 | ||
2834 | /* Symbols labelling the current insn. */ | |
2835 | struct insn_label_list | |
2836 | { | |
2837 | struct insn_label_list *next; | |
2838 | symbolS *label; | |
2839 | }; | |
2840 | ||
2841 | static struct insn_label_list *insn_labels; | |
2842 | static struct insn_label_list *free_insn_labels; | |
2843 | ||
2844 | static void | |
2845 | ppc_record_label (symbolS *sym) | |
2846 | { | |
2847 | struct insn_label_list *l; | |
2848 | ||
2849 | if (free_insn_labels == NULL) | |
2850 | l = XNEW (struct insn_label_list); | |
2851 | else | |
2852 | { | |
2853 | l = free_insn_labels; | |
2854 | free_insn_labels = l->next; | |
2855 | } | |
2856 | ||
2857 | l->label = sym; | |
2858 | l->next = insn_labels; | |
2859 | insn_labels = l; | |
2860 | } | |
2861 | ||
2862 | static void | |
2863 | ppc_clear_labels (void) | |
2864 | { | |
2865 | while (insn_labels != NULL) | |
2866 | { | |
2867 | struct insn_label_list *l = insn_labels; | |
2868 | insn_labels = l->next; | |
2869 | l->next = free_insn_labels; | |
2870 | free_insn_labels = l; | |
2871 | } | |
2872 | } | |
2873 | ||
2874 | void | |
2875 | ppc_start_line_hook (void) | |
2876 | { | |
2877 | ppc_clear_labels (); | |
2878 | } | |
2879 | ||
2880 | void | |
2881 | ppc_new_dot_label (symbolS *sym) | |
2882 | { | |
2883 | ppc_record_label (sym); | |
2884 | #ifdef OBJ_XCOFF | |
2885 | /* Anchor this label to the current csect for relocations. */ | |
2886 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2887 | #endif | |
2888 | } | |
2889 | ||
2890 | void | |
2891 | ppc_frob_label (symbolS *sym) | |
2892 | { | |
2893 | ppc_record_label (sym); | |
2894 | ||
2895 | #ifdef OBJ_XCOFF | |
2896 | /* Set the class of a label based on where it is defined. This handles | |
2897 | symbols without suffixes. Also, move the symbol so that it follows | |
2898 | the csect symbol. */ | |
2899 | if (ppc_current_csect != (symbolS *) NULL) | |
2900 | { | |
2901 | if (symbol_get_tc (sym)->symbol_class == -1) | |
2902 | symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class; | |
2903 | ||
2904 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
2905 | symbol_append (sym, symbol_get_tc (ppc_current_csect)->within, | |
2906 | &symbol_rootP, &symbol_lastP); | |
cd026728 | 2907 | /* Update last csect symbol. */ |
dd7efa79 | 2908 | symbol_get_tc (ppc_current_csect)->within = sym; |
cd026728 CC |
2909 | |
2910 | /* Some labels like .bs are using within differently. | |
2911 | So avoid changing it, if it's already set. */ | |
2912 | if (symbol_get_tc (sym)->within == NULL) | |
2913 | symbol_get_tc (sym)->within = ppc_current_csect; | |
dd7efa79 PB |
2914 | } |
2915 | #endif | |
2916 | ||
2917 | #ifdef OBJ_ELF | |
2918 | dwarf2_emit_label (sym); | |
2919 | #endif | |
2920 | } | |
6a0c61b7 | 2921 | |
252b5132 RH |
2922 | /* We need to keep a list of fixups. We can't simply generate them as |
2923 | we go, because that would require us to first create the frag, and | |
2924 | that would screw up references to ``.''. */ | |
2925 | ||
2926 | struct ppc_fixup | |
2927 | { | |
2928 | expressionS exp; | |
2929 | int opindex; | |
2930 | bfd_reloc_code_real_type reloc; | |
2931 | }; | |
2932 | ||
2933 | #define MAX_INSN_FIXUPS (5) | |
2934 | ||
0e2779e9 AM |
2935 | /* Return the field size operated on by RELOC, and whether it is |
2936 | pc-relative in PC_RELATIVE. */ | |
2937 | ||
2938 | static unsigned int | |
5b7c81bd | 2939 | fixup_size (bfd_reloc_code_real_type reloc, bool *pc_relative) |
0e2779e9 AM |
2940 | { |
2941 | unsigned int size = 0; | |
5b7c81bd | 2942 | bool pcrel = false; |
0e2779e9 AM |
2943 | |
2944 | switch (reloc) | |
2945 | { | |
2946 | /* This switch statement must handle all BFD_RELOC values | |
2947 | possible in instruction fixups. As is, it handles all | |
2948 | BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c, | |
fe49679d | 2949 | bfd/coff-rs6000.c and bfd/coff64-rs6000.c. |
0e2779e9 AM |
2950 | Overkill since data and marker relocs need not be handled |
2951 | here, but this way we can be sure a needed fixup reloc isn't | |
2952 | accidentally omitted. */ | |
2953 | case BFD_RELOC_PPC_EMB_MRKREF: | |
2954 | case BFD_RELOC_VTABLE_ENTRY: | |
2955 | case BFD_RELOC_VTABLE_INHERIT: | |
2956 | break; | |
2957 | ||
2958 | case BFD_RELOC_8: | |
2959 | size = 1; | |
2960 | break; | |
2961 | ||
2962 | case BFD_RELOC_16: | |
2963 | case BFD_RELOC_16_BASEREL: | |
2964 | case BFD_RELOC_16_GOTOFF: | |
2965 | case BFD_RELOC_GPREL16: | |
2966 | case BFD_RELOC_HI16: | |
2967 | case BFD_RELOC_HI16_BASEREL: | |
2968 | case BFD_RELOC_HI16_GOTOFF: | |
2969 | case BFD_RELOC_HI16_PLTOFF: | |
2970 | case BFD_RELOC_HI16_S: | |
2971 | case BFD_RELOC_HI16_S_BASEREL: | |
2972 | case BFD_RELOC_HI16_S_GOTOFF: | |
2973 | case BFD_RELOC_HI16_S_PLTOFF: | |
2974 | case BFD_RELOC_LO16: | |
2975 | case BFD_RELOC_LO16_BASEREL: | |
2976 | case BFD_RELOC_LO16_GOTOFF: | |
2977 | case BFD_RELOC_LO16_PLTOFF: | |
2978 | case BFD_RELOC_PPC64_ADDR16_DS: | |
2979 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
2980 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
5663e321 AM |
2981 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
2982 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
2983 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
2984 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
0e2779e9 AM |
2985 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
2986 | case BFD_RELOC_PPC64_DTPREL16_DS: | |
2987 | case BFD_RELOC_PPC64_DTPREL16_HIGH: | |
2988 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
2989 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
2990 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
2991 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
2992 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
2993 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
2994 | case BFD_RELOC_PPC64_GOT16_DS: | |
2995 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
2996 | case BFD_RELOC_PPC64_HIGHER: | |
2997 | case BFD_RELOC_PPC64_HIGHER_S: | |
2998 | case BFD_RELOC_PPC64_HIGHEST: | |
2999 | case BFD_RELOC_PPC64_HIGHEST_S: | |
3000 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
3001 | case BFD_RELOC_PPC64_PLTGOT16: | |
3002 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
3003 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
3004 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
3005 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
3006 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
3007 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
3008 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
3009 | case BFD_RELOC_PPC64_TOC16_DS: | |
3010 | case BFD_RELOC_PPC64_TOC16_HA: | |
3011 | case BFD_RELOC_PPC64_TOC16_HI: | |
3012 | case BFD_RELOC_PPC64_TOC16_LO: | |
3013 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
3014 | case BFD_RELOC_PPC64_TPREL16_DS: | |
3015 | case BFD_RELOC_PPC64_TPREL16_HIGH: | |
3016 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3017 | case BFD_RELOC_PPC64_TPREL16_HIGHER: | |
3018 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
3019 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
3020 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
3021 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
3022 | #ifdef OBJ_XCOFF | |
3023 | case BFD_RELOC_PPC_BA16: | |
3024 | #endif | |
3025 | case BFD_RELOC_PPC_DTPREL16: | |
3026 | case BFD_RELOC_PPC_DTPREL16_HA: | |
3027 | case BFD_RELOC_PPC_DTPREL16_HI: | |
3028 | case BFD_RELOC_PPC_DTPREL16_LO: | |
3029 | case BFD_RELOC_PPC_EMB_NADDR16: | |
3030 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
3031 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
3032 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
3033 | case BFD_RELOC_PPC_EMB_RELSDA: | |
3034 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
3035 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
3036 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
3037 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
3038 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
3039 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
3040 | case BFD_RELOC_PPC_EMB_SDAI16: | |
3041 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
3042 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
3043 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
3044 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3045 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
3046 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
3047 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
3048 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
3049 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
3050 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
3051 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
3052 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
3053 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3054 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
3055 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
3056 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3057 | case BFD_RELOC_PPC_TOC16: | |
4a403be0 CC |
3058 | case BFD_RELOC_PPC_TOC16_HI: |
3059 | case BFD_RELOC_PPC_TOC16_LO: | |
0e2779e9 AM |
3060 | case BFD_RELOC_PPC_TPREL16: |
3061 | case BFD_RELOC_PPC_TPREL16_HA: | |
3062 | case BFD_RELOC_PPC_TPREL16_HI: | |
3063 | case BFD_RELOC_PPC_TPREL16_LO: | |
3064 | size = 2; | |
3065 | break; | |
3066 | ||
3067 | case BFD_RELOC_16_PCREL: | |
3068 | case BFD_RELOC_HI16_PCREL: | |
3069 | case BFD_RELOC_HI16_S_PCREL: | |
3070 | case BFD_RELOC_LO16_PCREL: | |
3071 | case BFD_RELOC_PPC64_REL16_HIGH: | |
3072 | case BFD_RELOC_PPC64_REL16_HIGHA: | |
3073 | case BFD_RELOC_PPC64_REL16_HIGHER: | |
5663e321 | 3074 | case BFD_RELOC_PPC64_REL16_HIGHER34: |
0e2779e9 | 3075 | case BFD_RELOC_PPC64_REL16_HIGHERA: |
5663e321 | 3076 | case BFD_RELOC_PPC64_REL16_HIGHERA34: |
0e2779e9 | 3077 | case BFD_RELOC_PPC64_REL16_HIGHEST: |
5663e321 | 3078 | case BFD_RELOC_PPC64_REL16_HIGHEST34: |
0e2779e9 | 3079 | case BFD_RELOC_PPC64_REL16_HIGHESTA: |
5663e321 | 3080 | case BFD_RELOC_PPC64_REL16_HIGHESTA34: |
0e2779e9 AM |
3081 | #ifdef OBJ_XCOFF |
3082 | case BFD_RELOC_PPC_B16: | |
3083 | #endif | |
3084 | case BFD_RELOC_PPC_VLE_REL8: | |
3085 | size = 2; | |
5b7c81bd | 3086 | pcrel = true; |
0e2779e9 AM |
3087 | break; |
3088 | ||
0e2779e9 | 3089 | case BFD_RELOC_32: |
0e2779e9 AM |
3090 | case BFD_RELOC_32_PLTOFF: |
3091 | #ifdef OBJ_XCOFF | |
3092 | case BFD_RELOC_CTOR: | |
3093 | #endif | |
3094 | case BFD_RELOC_PPC64_ENTRY: | |
3095 | case BFD_RELOC_PPC_16DX_HA: | |
3096 | #ifndef OBJ_XCOFF | |
3097 | case BFD_RELOC_PPC_BA16: | |
3098 | #endif | |
3099 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
3100 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
3101 | case BFD_RELOC_PPC_BA26: | |
3102 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
3103 | case BFD_RELOC_PPC_EMB_NADDR32: | |
3104 | case BFD_RELOC_PPC_EMB_SDA21: | |
3105 | case BFD_RELOC_PPC_TLS: | |
3106 | case BFD_RELOC_PPC_TLSGD: | |
3107 | case BFD_RELOC_PPC_TLSLD: | |
1b2cb8e2 CC |
3108 | case BFD_RELOC_PPC_TLSLE: |
3109 | case BFD_RELOC_PPC_TLSIE: | |
3110 | case BFD_RELOC_PPC_TLSM: | |
3111 | case BFD_RELOC_PPC_TLSML: | |
0e2779e9 AM |
3112 | case BFD_RELOC_PPC_VLE_HA16A: |
3113 | case BFD_RELOC_PPC_VLE_HA16D: | |
3114 | case BFD_RELOC_PPC_VLE_HI16A: | |
3115 | case BFD_RELOC_PPC_VLE_HI16D: | |
3116 | case BFD_RELOC_PPC_VLE_LO16A: | |
3117 | case BFD_RELOC_PPC_VLE_LO16D: | |
3118 | case BFD_RELOC_PPC_VLE_SDA21: | |
3119 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
3120 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3121 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
3122 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3123 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
3124 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3125 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
c213164a | 3126 | case BFD_RELOC_PPC64_TLS_PCREL: |
0e2779e9 AM |
3127 | case BFD_RELOC_RVA: |
3128 | size = 4; | |
3129 | break; | |
3130 | ||
3131 | case BFD_RELOC_24_PLT_PCREL: | |
3132 | case BFD_RELOC_32_PCREL: | |
3133 | case BFD_RELOC_32_PLT_PCREL: | |
3134 | case BFD_RELOC_PPC64_REL24_NOTOC: | |
7aba54da | 3135 | case BFD_RELOC_PPC64_REL24_P9NOTOC: |
0e2779e9 AM |
3136 | #ifndef OBJ_XCOFF |
3137 | case BFD_RELOC_PPC_B16: | |
3138 | #endif | |
3139 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3140 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3141 | case BFD_RELOC_PPC_B26: | |
3142 | case BFD_RELOC_PPC_LOCAL24PC: | |
3143 | case BFD_RELOC_PPC_REL16DX_HA: | |
3144 | case BFD_RELOC_PPC_VLE_REL15: | |
3145 | case BFD_RELOC_PPC_VLE_REL24: | |
3146 | size = 4; | |
5b7c81bd | 3147 | pcrel = true; |
0e2779e9 AM |
3148 | break; |
3149 | ||
3150 | #ifndef OBJ_XCOFF | |
3151 | case BFD_RELOC_CTOR: | |
3152 | #endif | |
3153 | case BFD_RELOC_PPC_COPY: | |
3154 | case BFD_RELOC_PPC_DTPMOD: | |
3155 | case BFD_RELOC_PPC_DTPREL: | |
3156 | case BFD_RELOC_PPC_GLOB_DAT: | |
3157 | case BFD_RELOC_PPC_TPREL: | |
3158 | size = ppc_obj64 ? 8 : 4; | |
3159 | break; | |
3160 | ||
3161 | case BFD_RELOC_64: | |
3162 | case BFD_RELOC_64_PLTOFF: | |
3163 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
5663e321 AM |
3164 | case BFD_RELOC_PPC64_D28: |
3165 | case BFD_RELOC_PPC64_D34: | |
3166 | case BFD_RELOC_PPC64_D34_LO: | |
3167 | case BFD_RELOC_PPC64_D34_HI30: | |
3168 | case BFD_RELOC_PPC64_D34_HA30: | |
c213164a AM |
3169 | case BFD_RELOC_PPC64_TPREL34: |
3170 | case BFD_RELOC_PPC64_DTPREL34: | |
0e2779e9 | 3171 | case BFD_RELOC_PPC64_TOC: |
1b2cb8e2 CC |
3172 | case BFD_RELOC_PPC64_TLSGD: |
3173 | case BFD_RELOC_PPC64_TLSLD: | |
3174 | case BFD_RELOC_PPC64_TLSLE: | |
3175 | case BFD_RELOC_PPC64_TLSIE: | |
3176 | case BFD_RELOC_PPC64_TLSM: | |
3177 | case BFD_RELOC_PPC64_TLSML: | |
0e2779e9 AM |
3178 | size = 8; |
3179 | break; | |
3180 | ||
3181 | case BFD_RELOC_64_PCREL: | |
3182 | case BFD_RELOC_64_PLT_PCREL: | |
5663e321 | 3183 | case BFD_RELOC_PPC64_GOT_PCREL34: |
87c69f97 AM |
3184 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3185 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3186 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3187 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 AM |
3188 | case BFD_RELOC_PPC64_PCREL28: |
3189 | case BFD_RELOC_PPC64_PCREL34: | |
3190 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
0e2779e9 | 3191 | size = 8; |
5b7c81bd | 3192 | pcrel = true; |
0e2779e9 AM |
3193 | break; |
3194 | ||
3195 | default: | |
3196 | abort (); | |
3197 | } | |
3198 | ||
3199 | if (ENABLE_CHECKING) | |
3200 | { | |
3201 | reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
3202 | if (reloc_howto != NULL | |
3203 | && (size != bfd_get_reloc_size (reloc_howto) | |
3204 | || pcrel != reloc_howto->pc_relative)) | |
3205 | { | |
3206 | as_bad (_("%s howto doesn't match size/pcrel in gas"), | |
3207 | reloc_howto->name); | |
3208 | abort (); | |
3209 | } | |
3210 | } | |
3211 | *pc_relative = pcrel; | |
3212 | return size; | |
3213 | } | |
3214 | ||
a894d76a | 3215 | #ifdef OBJ_ELF |
160eba93 AM |
3216 | /* If we have parsed a call to __tls_get_addr, parse an argument like |
3217 | (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg | |
3218 | is successfully parsed, *STR is updated past the trailing | |
3219 | parenthesis and trailing white space, and *TLS_FIX contains the | |
3220 | reloc and arg expression. */ | |
3221 | ||
3222 | static int | |
3223 | parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix) | |
3224 | { | |
3225 | const char *sym_name = S_GET_NAME (exp->X_add_symbol); | |
3226 | if (sym_name[0] == '.') | |
3227 | ++sym_name; | |
3228 | ||
3229 | tls_fix->reloc = BFD_RELOC_NONE; | |
9e7028aa AM |
3230 | if (strncasecmp (sym_name, "__tls_get_addr", 14) == 0 |
3231 | && (sym_name[14] == 0 | |
3232 | || strcasecmp (sym_name + 14, "_desc") == 0 | |
3233 | || strcasecmp (sym_name + 14, "_opt") == 0)) | |
160eba93 AM |
3234 | { |
3235 | char *hold = input_line_pointer; | |
3236 | input_line_pointer = *str + 1; | |
3237 | expression (&tls_fix->exp); | |
3238 | if (tls_fix->exp.X_op == O_symbol) | |
3239 | { | |
3240 | if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) | |
3241 | tls_fix->reloc = BFD_RELOC_PPC_TLSGD; | |
3242 | else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0) | |
3243 | tls_fix->reloc = BFD_RELOC_PPC_TLSLD; | |
3244 | if (tls_fix->reloc != BFD_RELOC_NONE) | |
3245 | { | |
3246 | input_line_pointer += 7; | |
3247 | SKIP_WHITESPACE (); | |
3248 | *str = input_line_pointer; | |
3249 | } | |
3250 | } | |
3251 | input_line_pointer = hold; | |
3252 | } | |
3253 | return tls_fix->reloc != BFD_RELOC_NONE; | |
3254 | } | |
a894d76a | 3255 | #endif |
160eba93 | 3256 | |
252b5132 RH |
3257 | /* This routine is called for each instruction to be assembled. */ |
3258 | ||
3259 | void | |
98027b10 | 3260 | md_assemble (char *str) |
252b5132 RH |
3261 | { |
3262 | char *s; | |
3263 | const struct powerpc_opcode *opcode; | |
0f873fd5 | 3264 | uint64_t insn; |
252b5132 | 3265 | const unsigned char *opindex_ptr; |
252b5132 RH |
3266 | int need_paren; |
3267 | int next_opindex; | |
3268 | struct ppc_fixup fixups[MAX_INSN_FIXUPS]; | |
3269 | int fc; | |
3270 | char *f; | |
a9479dc0 | 3271 | int addr_mask; |
252b5132 | 3272 | int i; |
b9c361e0 | 3273 | unsigned int insn_length; |
252b5132 RH |
3274 | |
3275 | /* Get the opcode. */ | |
3882b010 | 3276 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 RH |
3277 | ; |
3278 | if (*s != '\0') | |
3279 | *s++ = '\0'; | |
3280 | ||
3281 | /* Look up the opcode in the hash table. */ | |
629310ab | 3282 | opcode = (const struct powerpc_opcode *) str_hash_find (ppc_hash, str); |
252b5132 RH |
3283 | if (opcode == (const struct powerpc_opcode *) NULL) |
3284 | { | |
3285 | const struct powerpc_macro *macro; | |
3286 | ||
fe0e921f AM |
3287 | macro = (const struct powerpc_macro *) str_hash_find (ppc_macro_hash, |
3288 | str); | |
252b5132 | 3289 | if (macro == (const struct powerpc_macro *) NULL) |
d6ed37ed | 3290 | as_bad (_("unrecognized opcode: `%s'"), str); |
252b5132 RH |
3291 | else |
3292 | ppc_macro (s, macro); | |
3293 | ||
dd7efa79 | 3294 | ppc_clear_labels (); |
252b5132 RH |
3295 | return; |
3296 | } | |
3297 | ||
3298 | insn = opcode->opcode; | |
86c0f617 AM |
3299 | if (!target_big_endian |
3300 | && ((insn & ~(1 << 26)) == 46u << 26 | |
3301 | || (insn & ~(0xc0 << 1)) == (31u << 26 | 533 << 1))) | |
3302 | { | |
3303 | /* lmw, stmw, lswi, lswx, stswi, stswx */ | |
3304 | as_bad (_("`%s' invalid when little-endian"), str); | |
3305 | ppc_clear_labels (); | |
3306 | return; | |
3307 | } | |
252b5132 RH |
3308 | |
3309 | str = s; | |
3882b010 | 3310 | while (ISSPACE (*str)) |
252b5132 RH |
3311 | ++str; |
3312 | ||
4a403be0 CC |
3313 | #ifdef OBJ_XCOFF |
3314 | /* AIX often generates addis instructions using "addis RT, D(RA)" | |
3315 | format instead of the classic "addis RT, RA, SI" one. | |
3316 | Restore it to the default format as it's the one encoded | |
3317 | in ppc opcodes. */ | |
3318 | if (!strcmp (opcode->name, "addis")) | |
3319 | { | |
3320 | char *rt_e = strchr (str, ','); | |
3321 | if (rt_e != NULL | |
3322 | && strchr (rt_e + 1, ',') == NULL) | |
3323 | { | |
3324 | char *d_e = strchr (rt_e + 1, '('); | |
3325 | if (d_e != NULL && d_e != rt_e + 1) | |
3326 | { | |
3327 | char *ra_e = strrchr (d_e + 1, ')'); | |
3328 | if (ra_e != NULL && ra_e != d_e + 1) | |
3329 | ppc_xcoff_fixup_addis (rt_e, d_e, ra_e); | |
3330 | } | |
3331 | } | |
3332 | } | |
3333 | #endif | |
3334 | ||
252b5132 | 3335 | /* PowerPC operands are just expressions. The only real issue is |
9cf7e568 AM |
3336 | that a few operand types are optional. If an instruction has |
3337 | multiple optional operands and one is omitted, then all optional | |
3338 | operands past the first omitted one must also be omitted. */ | |
3339 | int num_optional_operands = 0; | |
3340 | int num_optional_provided = 0; | |
252b5132 RH |
3341 | |
3342 | /* Gather the operands. */ | |
3343 | need_paren = 0; | |
3344 | next_opindex = 0; | |
3345 | fc = 0; | |
3346 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) | |
3347 | { | |
3348 | const struct powerpc_operand *operand; | |
3349 | const char *errmsg; | |
3350 | char *hold; | |
3351 | expressionS ex; | |
3352 | char endc; | |
3353 | ||
3354 | if (next_opindex == 0) | |
3355 | operand = &powerpc_operands[*opindex_ptr]; | |
3356 | else | |
3357 | { | |
3358 | operand = &powerpc_operands[next_opindex]; | |
3359 | next_opindex = 0; | |
3360 | } | |
252b5132 RH |
3361 | errmsg = NULL; |
3362 | ||
252b5132 | 3363 | /* If this is an optional operand, and we are skipping it, just |
9cf7e568 | 3364 | insert the default value, usually a zero. */ |
252b5132 | 3365 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
9cf7e568 | 3366 | && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)) |
252b5132 | 3367 | { |
9cf7e568 AM |
3368 | if (num_optional_operands == 0) |
3369 | { | |
3370 | const unsigned char *optr; | |
3371 | int total = 0; | |
3372 | int provided = 0; | |
3373 | int omitted; | |
3374 | ||
3375 | s = str; | |
3376 | for (optr = opindex_ptr; *optr != 0; optr++) | |
3377 | { | |
3378 | const struct powerpc_operand *op; | |
3379 | op = &powerpc_operands[*optr]; | |
3380 | ||
3381 | ++total; | |
3382 | ||
3383 | if ((op->flags & PPC_OPERAND_OPTIONAL) != 0 | |
3384 | && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0 | |
3385 | && ppc_obj64)) | |
3386 | ++num_optional_operands; | |
3387 | ||
3388 | if (s != NULL && *s != '\0') | |
3389 | { | |
3390 | ++provided; | |
3391 | ||
3392 | /* Look for the start of the next operand. */ | |
3393 | if ((op->flags & PPC_OPERAND_PARENS) != 0) | |
3394 | s = strpbrk (s, "(,"); | |
3395 | else | |
3396 | s = strchr (s, ','); | |
3397 | ||
3398 | if (s != NULL) | |
3399 | ++s; | |
3400 | } | |
3401 | } | |
3402 | omitted = total - provided; | |
3403 | num_optional_provided = num_optional_operands - omitted; | |
3404 | } | |
3405 | if (--num_optional_provided < 0) | |
252b5132 | 3406 | { |
32d71569 AM |
3407 | uint64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu, |
3408 | num_optional_provided); | |
9cf7e568 AM |
3409 | if (operand->insert) |
3410 | { | |
3411 | insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); | |
3412 | if (errmsg != (const char *) NULL) | |
3413 | as_bad ("%s", errmsg); | |
3414 | } | |
3415 | else if (operand->shift >= 0) | |
3416 | insn |= (val & operand->bitm) << operand->shift; | |
3417 | else | |
3418 | insn |= (val & operand->bitm) >> -operand->shift; | |
3419 | ||
3420 | if ((operand->flags & PPC_OPERAND_NEXT) != 0) | |
3421 | next_opindex = *opindex_ptr + 1; | |
3422 | continue; | |
252b5132 | 3423 | } |
252b5132 RH |
3424 | } |
3425 | ||
3426 | /* Gather the operand. */ | |
3427 | hold = input_line_pointer; | |
3428 | input_line_pointer = str; | |
3429 | ||
fe49679d AM |
3430 | if ((reg_names_p |
3431 | && (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
3432 | || ((operand->flags & PPC_OPERAND_CR_REG) != 0))) | |
3433 | || !register_name (&ex)) | |
252b5132 | 3434 | { |
fe49679d | 3435 | char save_lex = lex_type['%']; |
252b5132 | 3436 | |
fe49679d AM |
3437 | if (((operand->flags & PPC_OPERAND_CR_REG) != 0) |
3438 | || (operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
252b5132 | 3439 | { |
5b7c81bd | 3440 | cr_operand = true; |
fe49679d | 3441 | lex_type['%'] |= LEX_BEGIN_NAME; |
252b5132 | 3442 | } |
fe49679d | 3443 | expression (&ex); |
5b7c81bd | 3444 | cr_operand = false; |
fe49679d | 3445 | lex_type['%'] = save_lex; |
252b5132 RH |
3446 | } |
3447 | ||
3448 | str = input_line_pointer; | |
3449 | input_line_pointer = hold; | |
3450 | ||
3451 | if (ex.X_op == O_illegal) | |
3452 | as_bad (_("illegal operand")); | |
3453 | else if (ex.X_op == O_absent) | |
3454 | as_bad (_("missing operand")); | |
3455 | else if (ex.X_op == O_register) | |
3456 | { | |
7e0de605 AM |
3457 | if ((ex.X_md |
3458 | & ~operand->flags | |
3459 | & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR | |
3460 | | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG | |
aa3c112f | 3461 | | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0 |
7e0de605 AM |
3462 | && !((ex.X_md & PPC_OPERAND_GPR) != 0 |
3463 | && ex.X_add_number != 0 | |
3464 | && (operand->flags & PPC_OPERAND_GPR_0) != 0)) | |
ece5dcc1 | 3465 | as_warn (_("invalid register expression")); |
4b1c0f7e | 3466 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3467 | ppc_cpu, (char *) NULL, 0); |
252b5132 | 3468 | } |
32d71569 AM |
3469 | else if (ex.X_op == O_constant |
3470 | || (ex.X_op == O_big && ex.X_add_number > 0)) | |
252b5132 | 3471 | { |
32d71569 AM |
3472 | uint64_t val; |
3473 | if (ex.X_op == O_constant) | |
3474 | { | |
3475 | val = ex.X_add_number; | |
3476 | if (sizeof (ex.X_add_number) < sizeof (val) | |
3477 | && (ex.X_add_number < 0) != ex.X_extrabit) | |
3478 | val = val ^ ((addressT) -1 ^ (uint64_t) -1); | |
3479 | } | |
3480 | else | |
3481 | val = generic_bignum_to_int64 (); | |
252b5132 | 3482 | #ifdef OBJ_ELF |
81d4177b | 3483 | /* Allow @HA, @L, @H on constants. */ |
252b5132 | 3484 | char *orig_str = str; |
32d71569 | 3485 | bfd_reloc_code_real_type reloc = ppc_elf_suffix (&str, &ex); |
252b5132 | 3486 | |
32d71569 AM |
3487 | if (ex.X_op == O_constant) |
3488 | { | |
3489 | val = ex.X_add_number; | |
3490 | if (sizeof (ex.X_add_number) < sizeof (val) | |
3491 | && (ex.X_add_number < 0) != ex.X_extrabit) | |
3492 | val = val ^ ((addressT) -1 ^ (uint64_t) -1); | |
3493 | } | |
3494 | if (reloc != BFD_RELOC_NONE) | |
252b5132 RH |
3495 | switch (reloc) |
3496 | { | |
3497 | default: | |
3498 | str = orig_str; | |
3499 | break; | |
3500 | ||
3501 | case BFD_RELOC_LO16: | |
32d71569 | 3502 | val &= 0xffff; |
f9c6b907 | 3503 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3504 | val = SEX16 (val); |
252b5132 RH |
3505 | break; |
3506 | ||
3507 | case BFD_RELOC_HI16: | |
f9c6b907 AM |
3508 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3509 | { | |
3510 | /* PowerPC64 @h is tested for overflow. */ | |
32d71569 | 3511 | val = val >> 16; |
f9c6b907 AM |
3512 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
3513 | { | |
32d71569 AM |
3514 | uint64_t sign = (((uint64_t) -1 >> 16) + 1) >> 1; |
3515 | val = (val ^ sign) - sign; | |
f9c6b907 AM |
3516 | } |
3517 | break; | |
3518 | } | |
2b0f3761 | 3519 | /* Fallthru */ |
f9c6b907 AM |
3520 | |
3521 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
32d71569 | 3522 | val = PPC_HI (val); |
f9c6b907 | 3523 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3524 | val = SEX16 (val); |
252b5132 RH |
3525 | break; |
3526 | ||
3527 | case BFD_RELOC_HI16_S: | |
f9c6b907 AM |
3528 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3529 | { | |
3530 | /* PowerPC64 @ha is tested for overflow. */ | |
32d71569 | 3531 | val = (val + 0x8000) >> 16; |
f9c6b907 AM |
3532 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
3533 | { | |
32d71569 AM |
3534 | uint64_t sign = (((uint64_t) -1 >> 16) + 1) >> 1; |
3535 | val = (val ^ sign) - sign; | |
f9c6b907 AM |
3536 | } |
3537 | break; | |
3538 | } | |
2b0f3761 | 3539 | /* Fallthru */ |
f9c6b907 AM |
3540 | |
3541 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
32d71569 | 3542 | val = PPC_HA (val); |
f9c6b907 | 3543 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3544 | val = SEX16 (val); |
0baf16f2 AM |
3545 | break; |
3546 | ||
0baf16f2 | 3547 | case BFD_RELOC_PPC64_HIGHER: |
32d71569 | 3548 | val = PPC_HIGHER (val); |
f9c6b907 | 3549 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3550 | val = SEX16 (val); |
0baf16f2 AM |
3551 | break; |
3552 | ||
3553 | case BFD_RELOC_PPC64_HIGHER_S: | |
32d71569 | 3554 | val = PPC_HIGHERA (val); |
f9c6b907 | 3555 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3556 | val = SEX16 (val); |
252b5132 | 3557 | break; |
0baf16f2 AM |
3558 | |
3559 | case BFD_RELOC_PPC64_HIGHEST: | |
32d71569 | 3560 | val = PPC_HIGHEST (val); |
f9c6b907 | 3561 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3562 | val = SEX16 (val); |
0baf16f2 AM |
3563 | break; |
3564 | ||
3565 | case BFD_RELOC_PPC64_HIGHEST_S: | |
32d71569 | 3566 | val = PPC_HIGHESTA (val); |
f9c6b907 | 3567 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3568 | val = SEX16 (val); |
0baf16f2 | 3569 | break; |
252b5132 | 3570 | } |
0baf16f2 | 3571 | #endif /* OBJ_ELF */ |
32d71569 | 3572 | insn = ppc_insert_operand (insn, operand, val, ppc_cpu, NULL, 0); |
252b5132 | 3573 | } |
727fc41e | 3574 | else |
252b5132 | 3575 | { |
62ebcb5c | 3576 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
3b8b57a9 | 3577 | #ifdef OBJ_ELF |
160eba93 AM |
3578 | /* Look for a __tls_get_addr arg using the insane old syntax. */ |
3579 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3580 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
cdba85ec | 3581 | { |
160eba93 AM |
3582 | fixups[fc].opindex = *opindex_ptr; |
3583 | ++fc; | |
252b5132 RH |
3584 | } |
3585 | ||
62ebcb5c | 3586 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
0baf16f2 | 3587 | { |
b9c361e0 JL |
3588 | /* If VLE-mode convert LO/HI/HA relocations. */ |
3589 | if (opcode->flags & PPC_OPCODE_VLE) | |
3590 | { | |
0f873fd5 | 3591 | uint64_t tmp_insn = insn & opcode->mask; |
3739860c | 3592 | |
08dc996f | 3593 | int use_a_reloc = (tmp_insn == E_OR2I_INSN |
b9c361e0 JL |
3594 | || tmp_insn == E_AND2I_DOT_INSN |
3595 | || tmp_insn == E_OR2IS_INSN | |
bb6bf75e | 3596 | || tmp_insn == E_LI_INSN |
b9c361e0 JL |
3597 | || tmp_insn == E_LIS_INSN |
3598 | || tmp_insn == E_AND2IS_DOT_INSN); | |
3599 | ||
3600 | ||
08dc996f | 3601 | int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN |
b9c361e0 JL |
3602 | || tmp_insn == E_ADD2IS_INSN |
3603 | || tmp_insn == E_CMP16I_INSN | |
3604 | || tmp_insn == E_MULL2I_INSN | |
3605 | || tmp_insn == E_CMPL16I_INSN | |
3606 | || tmp_insn == E_CMPH16I_INSN | |
3607 | || tmp_insn == E_CMPHL16I_INSN); | |
3608 | ||
3609 | switch (reloc) | |
3610 | { | |
3611 | default: | |
3612 | break; | |
3613 | ||
3614 | case BFD_RELOC_PPC_EMB_SDA21: | |
3615 | reloc = BFD_RELOC_PPC_VLE_SDA21; | |
3616 | break; | |
3617 | ||
3618 | case BFD_RELOC_LO16: | |
3619 | if (use_d_reloc) | |
3620 | reloc = BFD_RELOC_PPC_VLE_LO16D; | |
3621 | else if (use_a_reloc) | |
3622 | reloc = BFD_RELOC_PPC_VLE_LO16A; | |
3623 | break; | |
3624 | ||
3625 | case BFD_RELOC_HI16: | |
3626 | if (use_d_reloc) | |
3627 | reloc = BFD_RELOC_PPC_VLE_HI16D; | |
3628 | else if (use_a_reloc) | |
3629 | reloc = BFD_RELOC_PPC_VLE_HI16A; | |
3630 | break; | |
3739860c | 3631 | |
b9c361e0 JL |
3632 | case BFD_RELOC_HI16_S: |
3633 | if (use_d_reloc) | |
3634 | reloc = BFD_RELOC_PPC_VLE_HA16D; | |
3635 | else if (use_a_reloc) | |
3636 | reloc = BFD_RELOC_PPC_VLE_HA16A; | |
3637 | break; | |
3638 | ||
3639 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3640 | if (use_d_reloc) | |
3641 | reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D; | |
3642 | break; | |
3643 | ||
3644 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3645 | if (use_d_reloc) | |
3646 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D; | |
3647 | break; | |
3648 | ||
3649 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3650 | if (use_d_reloc) | |
3651 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D; | |
3652 | break; | |
3653 | } | |
3654 | } | |
bb6bf75e AM |
3655 | |
3656 | /* TLS and other tweaks. */ | |
3657 | switch (reloc) | |
3658 | { | |
3659 | default: | |
3660 | break; | |
3661 | ||
3662 | case BFD_RELOC_PPC_TLS: | |
c213164a | 3663 | case BFD_RELOC_PPC64_TLS_PCREL: |
bb6bf75e AM |
3664 | if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0)) |
3665 | as_bad (_("@tls may not be used with \"%s\" operands"), | |
3666 | opcode->name); | |
3667 | else if (operand->shift != 11) | |
3668 | as_bad (_("@tls may only be used in last operand")); | |
3669 | else | |
3670 | insn = ppc_insert_operand (insn, operand, | |
3671 | ppc_obj64 ? 13 : 2, | |
3672 | ppc_cpu, (char *) NULL, 0); | |
3673 | break; | |
3674 | ||
3675 | /* We'll only use the 32 (or 64) bit form of these relocations | |
c213164a | 3676 | in constants. Instructions get the 16 or 34 bit form. */ |
bb6bf75e | 3677 | case BFD_RELOC_PPC_DTPREL: |
c213164a AM |
3678 | if (operand->bitm == 0x3ffffffffULL) |
3679 | reloc = BFD_RELOC_PPC64_DTPREL34; | |
3680 | else | |
3681 | reloc = BFD_RELOC_PPC_DTPREL16; | |
bb6bf75e AM |
3682 | break; |
3683 | ||
3684 | case BFD_RELOC_PPC_TPREL: | |
c213164a AM |
3685 | if (operand->bitm == 0x3ffffffffULL) |
3686 | reloc = BFD_RELOC_PPC64_TPREL34; | |
3687 | else | |
3688 | reloc = BFD_RELOC_PPC_TPREL16; | |
bb6bf75e AM |
3689 | break; |
3690 | ||
5663e321 AM |
3691 | case BFD_RELOC_PPC64_PCREL34: |
3692 | if (operand->bitm == 0xfffffffULL) | |
3693 | { | |
3694 | reloc = BFD_RELOC_PPC64_PCREL28; | |
3695 | break; | |
3696 | } | |
3697 | /* Fall through. */ | |
3698 | case BFD_RELOC_PPC64_GOT_PCREL34: | |
3699 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
87c69f97 AM |
3700 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3701 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3702 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3703 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 | 3704 | if (operand->bitm != 0x3ffffffffULL |
bb6bf75e | 3705 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
5663e321 AM |
3706 | as_warn (_("%s unsupported on this instruction"), "@pcrel"); |
3707 | break; | |
3708 | ||
3709 | case BFD_RELOC_LO16: | |
3710 | if (operand->bitm == 0x3ffffffffULL | |
3711 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3712 | reloc = BFD_RELOC_PPC64_D34_LO; | |
3713 | else if ((operand->bitm | 0xf) != 0xffff | |
3714 | || operand->shift != 0 | |
3715 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3716 | as_warn (_("%s unsupported on this instruction"), "@l"); |
3717 | break; | |
3718 | ||
3719 | case BFD_RELOC_HI16: | |
5663e321 AM |
3720 | if (operand->bitm == 0x3ffffffffULL |
3721 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3722 | reloc = BFD_RELOC_PPC64_D34_HI30; | |
3723 | else if (operand->bitm != 0xffff | |
3724 | || operand->shift != 0 | |
3725 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3726 | as_warn (_("%s unsupported on this instruction"), "@h"); |
3727 | break; | |
3728 | ||
3729 | case BFD_RELOC_HI16_S: | |
5663e321 AM |
3730 | if (operand->bitm == 0x3ffffffffULL |
3731 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3732 | reloc = BFD_RELOC_PPC64_D34_HA30; | |
3733 | else if (operand->bitm == 0xffff | |
3734 | && operand->shift == (int) PPC_OPSHIFT_INV | |
3735 | && opcode->opcode == (19 << 26) + (2 << 1)) | |
bb6bf75e AM |
3736 | /* addpcis. */ |
3737 | reloc = BFD_RELOC_PPC_16DX_HA; | |
3738 | else if (operand->bitm != 0xffff | |
3739 | || operand->shift != 0 | |
3740 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3741 | as_warn (_("%s unsupported on this instruction"), "@ha"); | |
3742 | } | |
0baf16f2 | 3743 | } |
3b8b57a9 | 3744 | #endif /* OBJ_ELF */ |
4a403be0 CC |
3745 | #ifdef OBJ_XCOFF |
3746 | reloc = ppc_xcoff_suffix (&str); | |
3747 | #endif /* OBJ_XCOFF */ | |
3b8b57a9 | 3748 | |
62ebcb5c | 3749 | if (reloc != BFD_RELOC_NONE) |
3b8b57a9 AM |
3750 | ; |
3751 | /* Determine a BFD reloc value based on the operand information. | |
3752 | We are only prepared to turn a few of the operands into | |
3753 | relocs. */ | |
a0593ad9 AM |
3754 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3755 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3756 | && operand->bitm == 0x3fffffc |
3757 | && operand->shift == 0) | |
3758 | reloc = BFD_RELOC_PPC_B26; | |
a0593ad9 AM |
3759 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3760 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3761 | && operand->bitm == 0xfffc |
3762 | && operand->shift == 0) | |
3763 | reloc = BFD_RELOC_PPC_B16; | |
3764 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3765 | && operand->bitm == 0x1fe | |
3766 | && operand->shift == -1) | |
3767 | reloc = BFD_RELOC_PPC_VLE_REL8; | |
3768 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3769 | && operand->bitm == 0xfffe | |
3770 | && operand->shift == 0) | |
3771 | reloc = BFD_RELOC_PPC_VLE_REL15; | |
3772 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3773 | && operand->bitm == 0x1fffffe | |
3774 | && operand->shift == 0) | |
3775 | reloc = BFD_RELOC_PPC_VLE_REL24; | |
a0593ad9 | 3776 | else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 |
3b8b57a9 AM |
3777 | && (operand->bitm & 0xfff0) == 0xfff0 |
3778 | && operand->shift == 0) | |
3779 | { | |
f50c47f1 | 3780 | reloc = BFD_RELOC_16; |
3e60bf4d | 3781 | #if defined OBJ_XCOFF || defined OBJ_ELF |
f50c47f1 | 3782 | /* Note: the symbol may be not yet defined. */ |
a0593ad9 AM |
3783 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
3784 | && ppc_is_toc_sym (ex.X_add_symbol)) | |
3e60bf4d AM |
3785 | { |
3786 | reloc = BFD_RELOC_PPC_TOC16; | |
3787 | #ifdef OBJ_ELF | |
3788 | as_warn (_("assuming %s on symbol"), | |
3789 | ppc_obj64 ? "@toc" : "@xgot"); | |
3790 | #endif | |
3791 | } | |
3b8b57a9 | 3792 | #endif |
3b8b57a9 | 3793 | } |
5663e321 AM |
3794 | else if (operand->bitm == 0x3ffffffffULL) |
3795 | reloc = BFD_RELOC_PPC64_D34; | |
3796 | else if (operand->bitm == 0xfffffffULL) | |
3797 | reloc = BFD_RELOC_PPC64_D28; | |
a0593ad9 AM |
3798 | |
3799 | /* For the absolute forms of branches, convert the PC | |
3800 | relative form back into the absolute. */ | |
3801 | if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
3802 | { | |
3803 | switch (reloc) | |
3804 | { | |
3805 | case BFD_RELOC_PPC_B26: | |
3806 | reloc = BFD_RELOC_PPC_BA26; | |
3807 | break; | |
3808 | case BFD_RELOC_PPC_B16: | |
3809 | reloc = BFD_RELOC_PPC_BA16; | |
3810 | break; | |
3811 | #ifdef OBJ_ELF | |
3812 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3813 | reloc = BFD_RELOC_PPC_BA16_BRTAKEN; | |
3814 | break; | |
3815 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3816 | reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; | |
3817 | break; | |
3818 | #endif | |
3819 | default: | |
3820 | break; | |
3821 | } | |
3822 | } | |
3823 | ||
3824 | #ifdef OBJ_ELF | |
3825 | switch (reloc) | |
3826 | { | |
3827 | case BFD_RELOC_PPC_TOC16: | |
3828 | toc_reloc_types |= has_small_toc_reloc; | |
3829 | break; | |
3830 | case BFD_RELOC_PPC64_TOC16_LO: | |
3831 | case BFD_RELOC_PPC64_TOC16_HI: | |
3832 | case BFD_RELOC_PPC64_TOC16_HA: | |
3833 | toc_reloc_types |= has_large_toc_reloc; | |
3834 | break; | |
3835 | default: | |
3836 | break; | |
3837 | } | |
3838 | ||
3839 | if (ppc_obj64 | |
3840 | && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) | |
3841 | { | |
3842 | switch (reloc) | |
3843 | { | |
3844 | case BFD_RELOC_16: | |
3845 | reloc = BFD_RELOC_PPC64_ADDR16_DS; | |
3846 | break; | |
5663e321 | 3847 | |
a0593ad9 AM |
3848 | case BFD_RELOC_LO16: |
3849 | reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; | |
3850 | break; | |
5663e321 | 3851 | |
a0593ad9 AM |
3852 | case BFD_RELOC_16_GOTOFF: |
3853 | reloc = BFD_RELOC_PPC64_GOT16_DS; | |
3854 | break; | |
5663e321 | 3855 | |
a0593ad9 AM |
3856 | case BFD_RELOC_LO16_GOTOFF: |
3857 | reloc = BFD_RELOC_PPC64_GOT16_LO_DS; | |
3858 | break; | |
5663e321 | 3859 | |
a0593ad9 AM |
3860 | case BFD_RELOC_LO16_PLTOFF: |
3861 | reloc = BFD_RELOC_PPC64_PLT16_LO_DS; | |
3862 | break; | |
5663e321 | 3863 | |
a0593ad9 AM |
3864 | case BFD_RELOC_16_BASEREL: |
3865 | reloc = BFD_RELOC_PPC64_SECTOFF_DS; | |
3866 | break; | |
5663e321 | 3867 | |
a0593ad9 AM |
3868 | case BFD_RELOC_LO16_BASEREL: |
3869 | reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; | |
3870 | break; | |
5663e321 | 3871 | |
a0593ad9 AM |
3872 | case BFD_RELOC_PPC_TOC16: |
3873 | reloc = BFD_RELOC_PPC64_TOC16_DS; | |
3874 | break; | |
5663e321 | 3875 | |
a0593ad9 AM |
3876 | case BFD_RELOC_PPC64_TOC16_LO: |
3877 | reloc = BFD_RELOC_PPC64_TOC16_LO_DS; | |
3878 | break; | |
5663e321 | 3879 | |
a0593ad9 AM |
3880 | case BFD_RELOC_PPC64_PLTGOT16: |
3881 | reloc = BFD_RELOC_PPC64_PLTGOT16_DS; | |
3882 | break; | |
5663e321 | 3883 | |
a0593ad9 AM |
3884 | case BFD_RELOC_PPC64_PLTGOT16_LO: |
3885 | reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; | |
3886 | break; | |
5663e321 | 3887 | |
a0593ad9 AM |
3888 | case BFD_RELOC_PPC_DTPREL16: |
3889 | reloc = BFD_RELOC_PPC64_DTPREL16_DS; | |
3890 | break; | |
5663e321 | 3891 | |
a0593ad9 AM |
3892 | case BFD_RELOC_PPC_DTPREL16_LO: |
3893 | reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; | |
3894 | break; | |
5663e321 | 3895 | |
a0593ad9 AM |
3896 | case BFD_RELOC_PPC_TPREL16: |
3897 | reloc = BFD_RELOC_PPC64_TPREL16_DS; | |
3898 | break; | |
5663e321 | 3899 | |
a0593ad9 AM |
3900 | case BFD_RELOC_PPC_TPREL16_LO: |
3901 | reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; | |
3902 | break; | |
5663e321 | 3903 | |
a0593ad9 AM |
3904 | case BFD_RELOC_PPC_GOT_DTPREL16: |
3905 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3906 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3907 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3908 | break; | |
5663e321 | 3909 | |
a0593ad9 AM |
3910 | default: |
3911 | as_bad (_("unsupported relocation for DS offset field")); | |
3912 | break; | |
3913 | } | |
3914 | } | |
160eba93 AM |
3915 | |
3916 | /* Look for a __tls_get_addr arg after any __tls_get_addr | |
3917 | modifiers like @plt. This fixup must be emitted before | |
3918 | the usual call fixup. */ | |
3919 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3920 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
3921 | { | |
3922 | fixups[fc].opindex = *opindex_ptr; | |
3923 | ++fc; | |
3924 | } | |
a0593ad9 | 3925 | #endif |
0baf16f2 | 3926 | |
252b5132 RH |
3927 | /* We need to generate a fixup for this expression. */ |
3928 | if (fc >= MAX_INSN_FIXUPS) | |
3929 | as_fatal (_("too many fixups")); | |
3930 | fixups[fc].exp = ex; | |
727fc41e | 3931 | fixups[fc].opindex = *opindex_ptr; |
252b5132 RH |
3932 | fixups[fc].reloc = reloc; |
3933 | ++fc; | |
3934 | } | |
252b5132 RH |
3935 | |
3936 | if (need_paren) | |
3937 | { | |
3938 | endc = ')'; | |
3939 | need_paren = 0; | |
c3d65c1c BE |
3940 | /* If expecting more operands, then we want to see "),". */ |
3941 | if (*str == endc && opindex_ptr[1] != 0) | |
3942 | { | |
3943 | do | |
3944 | ++str; | |
3945 | while (ISSPACE (*str)); | |
3946 | endc = ','; | |
3947 | } | |
252b5132 RH |
3948 | } |
3949 | else if ((operand->flags & PPC_OPERAND_PARENS) != 0) | |
9cf7e568 | 3950 | endc = '('; |
252b5132 RH |
3951 | else |
3952 | endc = ','; | |
3953 | ||
3954 | /* The call to expression should have advanced str past any | |
3955 | whitespace. */ | |
9cf7e568 | 3956 | if (*str == endc) |
252b5132 | 3957 | { |
9cf7e568 AM |
3958 | ++str; |
3959 | if (endc == '(') | |
3960 | need_paren = 1; | |
3961 | } | |
3962 | else if (*str != '\0') | |
3963 | { | |
3964 | as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc); | |
3965 | break; | |
3966 | } | |
3967 | else if (endc == ')') | |
3968 | { | |
3969 | as_bad (_("syntax error; end of line, expected `%c'"), endc); | |
252b5132 RH |
3970 | break; |
3971 | } | |
252b5132 RH |
3972 | } |
3973 | ||
3882b010 | 3974 | while (ISSPACE (*str)) |
252b5132 RH |
3975 | ++str; |
3976 | ||
3977 | if (*str != '\0') | |
3978 | as_bad (_("junk at end of line: `%s'"), str); | |
3979 | ||
dc1d03fc | 3980 | #ifdef OBJ_ELF |
b9c361e0 | 3981 | /* Do we need/want an APUinfo section? */ |
4faf939a JM |
3982 | if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0 |
3983 | && !ppc_obj64) | |
6a0c61b7 EZ |
3984 | { |
3985 | /* These are all version "1". */ | |
3986 | if (opcode->flags & PPC_OPCODE_SPE) | |
b34976b6 | 3987 | ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1); |
6a0c61b7 | 3988 | if (opcode->flags & PPC_OPCODE_ISEL) |
b34976b6 | 3989 | ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1); |
6a0c61b7 | 3990 | if (opcode->flags & PPC_OPCODE_EFS) |
b34976b6 | 3991 | ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1); |
6a0c61b7 | 3992 | if (opcode->flags & PPC_OPCODE_BRLOCK) |
b34976b6 | 3993 | ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1); |
6a0c61b7 | 3994 | if (opcode->flags & PPC_OPCODE_PMR) |
b34976b6 | 3995 | ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1); |
6a0c61b7 | 3996 | if (opcode->flags & PPC_OPCODE_CACHELCK) |
b34976b6 | 3997 | ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1); |
6a0c61b7 | 3998 | if (opcode->flags & PPC_OPCODE_RFMCI) |
b34976b6 | 3999 | ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1); |
fbd94057 MR |
4000 | /* Only set the VLE flag if the instruction has been pulled via |
4001 | the VLE instruction set. This way the flag is guaranteed to | |
4002 | be set for VLE-only instructions or for VLE-only processors, | |
4003 | however it'll remain clear for dual-mode instructions on | |
4004 | dual-mode and, more importantly, standard-mode processors. */ | |
4005 | if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) | |
f7d69005 AM |
4006 | { |
4007 | ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); | |
4008 | if (elf_section_data (now_seg) != NULL) | |
4009 | elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE; | |
4010 | } | |
6a0c61b7 | 4011 | } |
dc1d03fc | 4012 | #endif |
6a0c61b7 | 4013 | |
252b5132 | 4014 | /* Write out the instruction. */ |
a9479dc0 AM |
4015 | |
4016 | addr_mask = 3; | |
f7d69005 | 4017 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
a9479dc0 AM |
4018 | /* All instructions can start on a 2 byte boundary for VLE. */ |
4019 | addr_mask = 1; | |
4020 | ||
4021 | if (frag_now->insn_addr != addr_mask) | |
b9c361e0 | 4022 | { |
a9479dc0 AM |
4023 | /* Don't emit instructions to a frag started for data, or for a |
4024 | CPU differing in VLE mode. Data is allowed to be misaligned, | |
4025 | and it's possible to start a new frag in the middle of | |
4026 | misaligned data. */ | |
4027 | frag_wane (frag_now); | |
4028 | frag_new (0); | |
b9c361e0 | 4029 | } |
a9479dc0 AM |
4030 | |
4031 | /* Check that insns within the frag are aligned. ppc_frag_check | |
4032 | will ensure that the frag start address is aligned. */ | |
4033 | if ((frag_now_fix () & addr_mask) != 0) | |
4034 | as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1); | |
4035 | ||
dd7efa79 | 4036 | /* Differentiate between two, four, and eight byte insns. */ |
a9479dc0 AM |
4037 | insn_length = 4; |
4038 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn)) | |
4039 | insn_length = 2; | |
7c1f4227 | 4040 | else if ((opcode->flags & PPC_OPCODE_POWER10) != 0 |
dd7efa79 PB |
4041 | && PPC_PREFIX_P (insn)) |
4042 | { | |
4043 | struct insn_label_list *l; | |
4044 | ||
4045 | insn_length = 8; | |
4046 | ||
4047 | /* 8-byte prefix instructions are not allowed to cross 64-byte | |
4048 | boundaries. */ | |
4049 | frag_align_code (6, 4); | |
4050 | record_alignment (now_seg, 6); | |
1daf786b CC |
4051 | #ifdef OBJ_XCOFF |
4052 | /* Update alignment of the containing csect. */ | |
4053 | if (symbol_get_tc (ppc_current_csect)->align < 6) | |
4054 | symbol_get_tc (ppc_current_csect)->align = 6; | |
4055 | #endif | |
dd7efa79 PB |
4056 | |
4057 | /* Update "dot" in any expressions used by this instruction, and | |
4058 | a label attached to the instruction. By "attached" we mean | |
4059 | on the same source line as the instruction and without any | |
4060 | intervening semicolons. */ | |
4061 | dot_value = frag_now_fix (); | |
4062 | dot_frag = frag_now; | |
4063 | for (l = insn_labels; l != NULL; l = l->next) | |
4064 | { | |
4065 | symbol_set_frag (l->label, dot_frag); | |
4066 | S_SET_VALUE (l->label, dot_value); | |
4067 | } | |
4068 | } | |
4069 | ||
4070 | ppc_clear_labels (); | |
a9479dc0 | 4071 | |
b9c361e0 | 4072 | f = frag_more (insn_length); |
a9479dc0 | 4073 | frag_now->insn_addr = addr_mask; |
dd7efa79 PB |
4074 | |
4075 | /* The prefix part of an 8-byte instruction always occupies the lower | |
4076 | addressed word in a doubleword, regardless of endianness. */ | |
15a32af5 AM |
4077 | if (insn_length == 8 |
4078 | && (sizeof (insn) > sizeof (valueT) || !target_big_endian)) | |
dd7efa79 PB |
4079 | { |
4080 | md_number_to_chars (f, PPC_GET_PREFIX (insn), 4); | |
4081 | md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4); | |
4082 | } | |
4083 | else | |
4084 | md_number_to_chars (f, insn, insn_length); | |
4085 | ||
bf7279d5 AM |
4086 | last_insn = insn; |
4087 | last_seg = now_seg; | |
4088 | last_subseg = now_subseg; | |
252b5132 | 4089 | |
5d6f4f16 | 4090 | #ifdef OBJ_ELF |
b9c361e0 | 4091 | dwarf2_emit_insn (insn_length); |
5d6f4f16 GK |
4092 | #endif |
4093 | ||
3b8b57a9 | 4094 | /* Create any fixups. */ |
252b5132 RH |
4095 | for (i = 0; i < fc; i++) |
4096 | { | |
3b8b57a9 | 4097 | fixS *fixP; |
62ebcb5c | 4098 | if (fixups[i].reloc != BFD_RELOC_NONE) |
252b5132 | 4099 | { |
5b7c81bd | 4100 | bool pcrel; |
0e2779e9 AM |
4101 | unsigned int size = fixup_size (fixups[i].reloc, &pcrel); |
4102 | int offset = target_big_endian ? (insn_length - size) : 0; | |
252b5132 | 4103 | |
99a814a1 AM |
4104 | fixP = fix_new_exp (frag_now, |
4105 | f - frag_now->fr_literal + offset, | |
4106 | size, | |
4107 | &fixups[i].exp, | |
0e2779e9 | 4108 | pcrel, |
252b5132 | 4109 | fixups[i].reloc); |
252b5132 RH |
4110 | } |
4111 | else | |
727fc41e AM |
4112 | { |
4113 | const struct powerpc_operand *operand; | |
4114 | ||
4115 | operand = &powerpc_operands[fixups[i].opindex]; | |
3b8b57a9 AM |
4116 | fixP = fix_new_exp (frag_now, |
4117 | f - frag_now->fr_literal, | |
4118 | insn_length, | |
4119 | &fixups[i].exp, | |
4120 | (operand->flags & PPC_OPERAND_RELATIVE) != 0, | |
62ebcb5c | 4121 | BFD_RELOC_NONE); |
727fc41e | 4122 | } |
3b8b57a9 | 4123 | fixP->fx_pcrel_adjust = fixups[i].opindex; |
252b5132 RH |
4124 | } |
4125 | } | |
4126 | ||
4127 | /* Handle a macro. Gather all the operands, transform them as | |
4128 | described by the macro, and call md_assemble recursively. All the | |
4129 | operands are separated by commas; we don't accept parentheses | |
4130 | around operands here. */ | |
4131 | ||
4132 | static void | |
98027b10 | 4133 | ppc_macro (char *str, const struct powerpc_macro *macro) |
252b5132 RH |
4134 | { |
4135 | char *operands[10]; | |
4136 | unsigned int count; | |
4137 | char *s; | |
4138 | unsigned int len; | |
4139 | const char *format; | |
db557034 | 4140 | unsigned int arg; |
252b5132 RH |
4141 | char *send; |
4142 | char *complete; | |
4143 | ||
4144 | /* Gather the users operands into the operands array. */ | |
4145 | count = 0; | |
4146 | s = str; | |
4147 | while (1) | |
4148 | { | |
4149 | if (count >= sizeof operands / sizeof operands[0]) | |
4150 | break; | |
4151 | operands[count++] = s; | |
4152 | s = strchr (s, ','); | |
4153 | if (s == (char *) NULL) | |
4154 | break; | |
4155 | *s++ = '\0'; | |
81d4177b | 4156 | } |
252b5132 RH |
4157 | |
4158 | if (count != macro->operands) | |
4159 | { | |
4160 | as_bad (_("wrong number of operands")); | |
4161 | return; | |
4162 | } | |
4163 | ||
4164 | /* Work out how large the string must be (the size is unbounded | |
4165 | because it includes user input). */ | |
4166 | len = 0; | |
4167 | format = macro->format; | |
4168 | while (*format != '\0') | |
4169 | { | |
4170 | if (*format != '%') | |
4171 | { | |
4172 | ++len; | |
4173 | ++format; | |
4174 | } | |
4175 | else | |
4176 | { | |
4177 | arg = strtol (format + 1, &send, 10); | |
db557034 | 4178 | know (send != format && arg < count); |
252b5132 RH |
4179 | len += strlen (operands[arg]); |
4180 | format = send; | |
4181 | } | |
4182 | } | |
4183 | ||
4184 | /* Put the string together. */ | |
325801bd | 4185 | complete = s = XNEWVEC (char, len + 1); |
252b5132 RH |
4186 | format = macro->format; |
4187 | while (*format != '\0') | |
4188 | { | |
4189 | if (*format != '%') | |
4190 | *s++ = *format++; | |
4191 | else | |
4192 | { | |
4193 | arg = strtol (format + 1, &send, 10); | |
4194 | strcpy (s, operands[arg]); | |
4195 | s += strlen (s); | |
4196 | format = send; | |
4197 | } | |
4198 | } | |
4199 | *s = '\0'; | |
4200 | ||
4201 | /* Assemble the constructed instruction. */ | |
4202 | md_assemble (complete); | |
e1fa0163 | 4203 | free (complete); |
81d4177b | 4204 | } |
252b5132 RH |
4205 | \f |
4206 | #ifdef OBJ_ELF | |
18ae9cc1 | 4207 | /* For ELF, add support for SHT_ORDERED. */ |
252b5132 RH |
4208 | |
4209 | int | |
98027b10 | 4210 | ppc_section_type (char *str, size_t len) |
252b5132 | 4211 | { |
d34049e8 | 4212 | if (len == 7 && startswith (str, "ordered")) |
9de8d8f1 | 4213 | return SHT_ORDERED; |
252b5132 | 4214 | |
9de8d8f1 | 4215 | return -1; |
252b5132 RH |
4216 | } |
4217 | ||
4218 | int | |
1239de13 | 4219 | ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type) |
252b5132 RH |
4220 | { |
4221 | if (type == SHT_ORDERED) | |
4222 | flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES; | |
4223 | ||
252b5132 RH |
4224 | return flags; |
4225 | } | |
83eef883 AFB |
4226 | |
4227 | bfd_vma | |
4228 | ppc_elf_section_letter (int letter, const char **ptrmsg) | |
4229 | { | |
4230 | if (letter == 'v') | |
4231 | return SHF_PPC_VLE; | |
4232 | ||
4233 | *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string"); | |
4234 | return -1; | |
4235 | } | |
252b5132 RH |
4236 | #endif /* OBJ_ELF */ |
4237 | ||
4238 | \f | |
4239 | /* Pseudo-op handling. */ | |
4240 | ||
4241 | /* The .byte pseudo-op. This is similar to the normal .byte | |
4242 | pseudo-op, but it can also take a single ASCII string. */ | |
4243 | ||
4244 | static void | |
98027b10 | 4245 | ppc_byte (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 4246 | { |
bf7279d5 AM |
4247 | int count = 0; |
4248 | ||
252b5132 RH |
4249 | if (*input_line_pointer != '\"') |
4250 | { | |
4251 | cons (1); | |
4252 | return; | |
4253 | } | |
4254 | ||
4255 | /* Gather characters. A real double quote is doubled. Unusual | |
4256 | characters are not permitted. */ | |
4257 | ++input_line_pointer; | |
4258 | while (1) | |
4259 | { | |
4260 | char c; | |
4261 | ||
4262 | c = *input_line_pointer++; | |
4263 | ||
4264 | if (c == '\"') | |
4265 | { | |
4266 | if (*input_line_pointer != '\"') | |
4267 | break; | |
4268 | ++input_line_pointer; | |
4269 | } | |
4270 | ||
4271 | FRAG_APPEND_1_CHAR (c); | |
bf7279d5 | 4272 | ++count; |
252b5132 RH |
4273 | } |
4274 | ||
bf7279d5 AM |
4275 | if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) |
4276 | as_warn (_("data in executable section")); | |
252b5132 RH |
4277 | demand_empty_rest_of_line (); |
4278 | } | |
4279 | \f | |
4280 | #ifdef OBJ_XCOFF | |
4281 | ||
4282 | /* XCOFF specific pseudo-op handling. */ | |
4283 | ||
4284 | /* This is set if we are creating a .stabx symbol, since we don't want | |
4285 | to handle symbol suffixes for such symbols. */ | |
5b7c81bd | 4286 | static bool ppc_stab_symbol; |
252b5132 RH |
4287 | |
4288 | /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common | |
4289 | symbols in the .bss segment as though they were local common | |
67c1ffbe | 4290 | symbols, and uses a different smclas. The native Aix 4.3.3 assembler |
1b2cb8e2 CC |
4291 | aligns .comm and .lcomm to 4 bytes. |
4292 | Symbols having a XMC_UL storage class are uninialized thread-local | |
4293 | data. */ | |
252b5132 RH |
4294 | |
4295 | static void | |
98027b10 | 4296 | ppc_comm (int lcomm) |
252b5132 RH |
4297 | { |
4298 | asection *current_seg = now_seg; | |
4299 | subsegT current_subseg = now_subseg; | |
4300 | char *name; | |
4301 | char endc; | |
4302 | char *end_name; | |
4303 | offsetT size; | |
4304 | offsetT align; | |
4305 | symbolS *lcomm_sym = NULL; | |
4306 | symbolS *sym; | |
4307 | char *pfrag; | |
1b2cb8e2 | 4308 | struct ppc_xcoff_section *section; |
252b5132 | 4309 | |
d02603dc | 4310 | endc = get_symbol_name (&name); |
252b5132 | 4311 | end_name = input_line_pointer; |
d02603dc | 4312 | (void) restore_line_pointer (endc); |
252b5132 RH |
4313 | |
4314 | if (*input_line_pointer != ',') | |
4315 | { | |
4316 | as_bad (_("missing size")); | |
4317 | ignore_rest_of_line (); | |
4318 | return; | |
4319 | } | |
4320 | ++input_line_pointer; | |
4321 | ||
4322 | size = get_absolute_expression (); | |
4323 | if (size < 0) | |
4324 | { | |
4325 | as_bad (_("negative size")); | |
4326 | ignore_rest_of_line (); | |
4327 | return; | |
4328 | } | |
4329 | ||
4330 | if (! lcomm) | |
4331 | { | |
4332 | /* The third argument to .comm is the alignment. */ | |
4333 | if (*input_line_pointer != ',') | |
1ad63b2f | 4334 | align = 2; |
252b5132 RH |
4335 | else |
4336 | { | |
4337 | ++input_line_pointer; | |
4338 | align = get_absolute_expression (); | |
4339 | if (align <= 0) | |
4340 | { | |
4341 | as_warn (_("ignoring bad alignment")); | |
1ad63b2f | 4342 | align = 2; |
252b5132 RH |
4343 | } |
4344 | } | |
4345 | } | |
4346 | else | |
4347 | { | |
4348 | char *lcomm_name; | |
4349 | char lcomm_endc; | |
4350 | ||
252b5132 RH |
4351 | /* The third argument to .lcomm appears to be the real local |
4352 | common symbol to create. References to the symbol named in | |
4353 | the first argument are turned into references to the third | |
4354 | argument. */ | |
4355 | if (*input_line_pointer != ',') | |
4356 | { | |
4357 | as_bad (_("missing real symbol name")); | |
4358 | ignore_rest_of_line (); | |
4359 | return; | |
4360 | } | |
4361 | ++input_line_pointer; | |
4362 | ||
d02603dc | 4363 | lcomm_endc = get_symbol_name (&lcomm_name); |
81d4177b | 4364 | |
252b5132 RH |
4365 | lcomm_sym = symbol_find_or_make (lcomm_name); |
4366 | ||
d02603dc | 4367 | (void) restore_line_pointer (lcomm_endc); |
3c02c47f DE |
4368 | |
4369 | /* The fourth argument to .lcomm is the alignment. */ | |
4370 | if (*input_line_pointer != ',') | |
4371 | { | |
4372 | if (size <= 4) | |
4373 | align = 2; | |
4374 | else | |
4375 | align = 3; | |
4376 | } | |
4377 | else | |
4378 | { | |
4379 | ++input_line_pointer; | |
4380 | align = get_absolute_expression (); | |
4381 | if (align <= 0) | |
4382 | { | |
4383 | as_warn (_("ignoring bad alignment")); | |
4384 | align = 2; | |
4385 | } | |
4386 | } | |
252b5132 RH |
4387 | } |
4388 | ||
4389 | *end_name = '\0'; | |
4390 | sym = symbol_find_or_make (name); | |
4391 | *end_name = endc; | |
4392 | ||
4393 | if (S_IS_DEFINED (sym) | |
4394 | || S_GET_VALUE (sym) != 0) | |
4395 | { | |
4396 | as_bad (_("attempt to redefine symbol")); | |
4397 | ignore_rest_of_line (); | |
4398 | return; | |
4399 | } | |
81d4177b | 4400 | |
1b2cb8e2 CC |
4401 | if (symbol_get_tc (sym)->symbol_class == XMC_UL |
4402 | || (lcomm && symbol_get_tc (lcomm_sym)->symbol_class == XMC_UL)) | |
4403 | { | |
4404 | section = &ppc_xcoff_tbss_section; | |
4405 | if (!ppc_xcoff_section_is_initialized (section)) | |
4406 | { | |
934cb849 | 4407 | ppc_init_xcoff_section (section, subseg_new (".tbss", 0)); |
1b2cb8e2 CC |
4408 | bfd_set_section_flags (section->segment, |
4409 | SEC_ALLOC | SEC_THREAD_LOCAL); | |
4410 | seg_info (section->segment)->bss = 1; | |
4411 | } | |
4412 | } | |
4413 | else | |
4414 | section = &ppc_xcoff_bss_section; | |
4415 | ||
4416 | record_alignment (section->segment, align); | |
81d4177b | 4417 | |
252b5132 RH |
4418 | if (! lcomm |
4419 | || ! S_IS_DEFINED (lcomm_sym)) | |
4420 | { | |
4421 | symbolS *def_sym; | |
4422 | offsetT def_size; | |
4423 | ||
4424 | if (! lcomm) | |
4425 | { | |
4426 | def_sym = sym; | |
4427 | def_size = size; | |
4428 | S_SET_EXTERNAL (sym); | |
4429 | } | |
4430 | else | |
4431 | { | |
809ffe0d | 4432 | symbol_get_tc (lcomm_sym)->output = 1; |
252b5132 RH |
4433 | def_sym = lcomm_sym; |
4434 | def_size = 0; | |
4435 | } | |
4436 | ||
1b2cb8e2 | 4437 | subseg_set (section->segment, 1); |
252b5132 | 4438 | frag_align (align, 0, 0); |
81d4177b | 4439 | |
809ffe0d | 4440 | symbol_set_frag (def_sym, frag_now); |
252b5132 RH |
4441 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym, |
4442 | def_size, (char *) NULL); | |
4443 | *pfrag = 0; | |
1b2cb8e2 | 4444 | S_SET_SEGMENT (def_sym, section->segment); |
809ffe0d | 4445 | symbol_get_tc (def_sym)->align = align; |
252b5132 RH |
4446 | } |
4447 | else if (lcomm) | |
4448 | { | |
4449 | /* Align the size of lcomm_sym. */ | |
809ffe0d ILT |
4450 | symbol_get_frag (lcomm_sym)->fr_offset = |
4451 | ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1) | |
252b5132 | 4452 | &~ ((1 << align) - 1)); |
809ffe0d ILT |
4453 | if (align > symbol_get_tc (lcomm_sym)->align) |
4454 | symbol_get_tc (lcomm_sym)->align = align; | |
252b5132 RH |
4455 | } |
4456 | ||
4457 | if (lcomm) | |
4458 | { | |
4459 | /* Make sym an offset from lcomm_sym. */ | |
1b2cb8e2 | 4460 | S_SET_SEGMENT (sym, section->segment); |
809ffe0d ILT |
4461 | symbol_set_frag (sym, symbol_get_frag (lcomm_sym)); |
4462 | S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset); | |
4463 | symbol_get_frag (lcomm_sym)->fr_offset += size; | |
252b5132 RH |
4464 | } |
4465 | ||
4466 | subseg_set (current_seg, current_subseg); | |
4467 | ||
4468 | demand_empty_rest_of_line (); | |
4469 | } | |
4470 | ||
4471 | /* The .csect pseudo-op. This switches us into a different | |
4472 | subsegment. The first argument is a symbol whose value is the | |
4473 | start of the .csect. In COFF, csect symbols get special aux | |
4474 | entries defined by the x_csect field of union internal_auxent. The | |
4475 | optional second argument is the alignment (the default is 2). */ | |
4476 | ||
4477 | static void | |
98027b10 | 4478 | ppc_csect (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4479 | { |
4480 | char *name; | |
4481 | char endc; | |
4482 | symbolS *sym; | |
931e13a6 | 4483 | offsetT align; |
252b5132 | 4484 | |
d02603dc | 4485 | endc = get_symbol_name (&name); |
81d4177b | 4486 | |
252b5132 RH |
4487 | sym = symbol_find_or_make (name); |
4488 | ||
d02603dc | 4489 | (void) restore_line_pointer (endc); |
252b5132 RH |
4490 | |
4491 | if (S_GET_NAME (sym)[0] == '\0') | |
4492 | { | |
4493 | /* An unnamed csect is assumed to be [PR]. */ | |
96d56e9f | 4494 | symbol_get_tc (sym)->symbol_class = XMC_PR; |
252b5132 RH |
4495 | } |
4496 | ||
931e13a6 | 4497 | align = 2; |
252b5132 RH |
4498 | if (*input_line_pointer == ',') |
4499 | { | |
4500 | ++input_line_pointer; | |
931e13a6 | 4501 | align = get_absolute_expression (); |
252b5132 RH |
4502 | } |
4503 | ||
931e13a6 AM |
4504 | ppc_change_csect (sym, align); |
4505 | ||
252b5132 RH |
4506 | demand_empty_rest_of_line (); |
4507 | } | |
4508 | ||
4509 | /* Change to a different csect. */ | |
4510 | ||
4511 | static void | |
98027b10 | 4512 | ppc_change_csect (symbolS *sym, offsetT align) |
252b5132 RH |
4513 | { |
4514 | if (S_IS_DEFINED (sym)) | |
809ffe0d | 4515 | subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg); |
252b5132 RH |
4516 | else |
4517 | { | |
1b2cb8e2 | 4518 | struct ppc_xcoff_section *section; |
252b5132 RH |
4519 | int after_toc; |
4520 | int hold_chunksize; | |
4521 | symbolS *list; | |
931e13a6 AM |
4522 | int is_code; |
4523 | segT sec; | |
252b5132 RH |
4524 | |
4525 | /* This is a new csect. We need to look at the symbol class to | |
4526 | figure out whether it should go in the text section or the | |
4527 | data section. */ | |
4528 | after_toc = 0; | |
931e13a6 | 4529 | is_code = 0; |
96d56e9f | 4530 | switch (symbol_get_tc (sym)->symbol_class) |
252b5132 RH |
4531 | { |
4532 | case XMC_PR: | |
4533 | case XMC_RO: | |
4534 | case XMC_DB: | |
4535 | case XMC_GL: | |
4536 | case XMC_XO: | |
4537 | case XMC_SV: | |
4538 | case XMC_TI: | |
4539 | case XMC_TB: | |
1b2cb8e2 | 4540 | section = &ppc_xcoff_text_section; |
931e13a6 | 4541 | is_code = 1; |
252b5132 RH |
4542 | break; |
4543 | case XMC_RW: | |
4544 | case XMC_TC0: | |
4545 | case XMC_TC: | |
4a403be0 | 4546 | case XMC_TE: |
252b5132 RH |
4547 | case XMC_DS: |
4548 | case XMC_UA: | |
252b5132 | 4549 | case XMC_UC: |
1b2cb8e2 | 4550 | section = &ppc_xcoff_data_section; |
252b5132 | 4551 | if (ppc_toc_csect != NULL |
809ffe0d | 4552 | && (symbol_get_tc (ppc_toc_csect)->subseg + 1 |
1b2cb8e2 | 4553 | == section->next_subsegment)) |
252b5132 | 4554 | after_toc = 1; |
1b2cb8e2 CC |
4555 | break; |
4556 | case XMC_BS: | |
4557 | section = &ppc_xcoff_bss_section; | |
4558 | break; | |
4559 | case XMC_TL: | |
4560 | section = &ppc_xcoff_tdata_section; | |
4561 | /* Create .tdata section if not yet done. */ | |
4562 | if (!ppc_xcoff_section_is_initialized (section)) | |
4563 | { | |
934cb849 | 4564 | ppc_init_xcoff_section (section, subseg_new (".tdata", 0)); |
1b2cb8e2 CC |
4565 | bfd_set_section_flags (section->segment, SEC_ALLOC |
4566 | | SEC_LOAD | SEC_RELOC | SEC_DATA | |
4567 | | SEC_THREAD_LOCAL); | |
4568 | } | |
4569 | break; | |
4570 | case XMC_UL: | |
4571 | section = &ppc_xcoff_tbss_section; | |
4572 | /* Create .tbss section if not yet done. */ | |
4573 | if (!ppc_xcoff_section_is_initialized (section)) | |
4574 | { | |
934cb849 | 4575 | ppc_init_xcoff_section (section, subseg_new (".tbss", 0)); |
1b2cb8e2 CC |
4576 | bfd_set_section_flags (section->segment, SEC_ALLOC | |
4577 | SEC_THREAD_LOCAL); | |
4578 | seg_info (section->segment)->bss = 1; | |
4579 | } | |
252b5132 RH |
4580 | break; |
4581 | default: | |
4582 | abort (); | |
4583 | } | |
4584 | ||
1b2cb8e2 CC |
4585 | S_SET_SEGMENT (sym, section->segment); |
4586 | symbol_get_tc (sym)->subseg = section->next_subsegment; | |
4587 | ++section->next_subsegment; | |
4588 | ||
252b5132 | 4589 | /* We set the obstack chunk size to a small value before |
99a814a1 AM |
4590 | changing subsegments, so that we don't use a lot of memory |
4591 | space for what may be a small section. */ | |
252b5132 RH |
4592 | hold_chunksize = chunksize; |
4593 | chunksize = 64; | |
4594 | ||
931e13a6 AM |
4595 | sec = subseg_new (segment_name (S_GET_SEGMENT (sym)), |
4596 | symbol_get_tc (sym)->subseg); | |
252b5132 RH |
4597 | |
4598 | chunksize = hold_chunksize; | |
4599 | ||
4600 | if (after_toc) | |
4601 | ppc_after_toc_frag = frag_now; | |
4602 | ||
931e13a6 AM |
4603 | record_alignment (sec, align); |
4604 | if (is_code) | |
4605 | frag_align_code (align, 0); | |
4606 | else | |
4607 | frag_align (align, 0, 0); | |
4608 | ||
809ffe0d | 4609 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4610 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4611 | ||
931e13a6 | 4612 | symbol_get_tc (sym)->align = align; |
809ffe0d ILT |
4613 | symbol_get_tc (sym)->output = 1; |
4614 | symbol_get_tc (sym)->within = sym; | |
81d4177b | 4615 | |
1b2cb8e2 | 4616 | for (list = section->csects; |
809ffe0d ILT |
4617 | symbol_get_tc (list)->next != (symbolS *) NULL; |
4618 | list = symbol_get_tc (list)->next) | |
252b5132 | 4619 | ; |
809ffe0d | 4620 | symbol_get_tc (list)->next = sym; |
81d4177b | 4621 | |
252b5132 | 4622 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
809ffe0d ILT |
4623 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
4624 | &symbol_lastP); | |
252b5132 RH |
4625 | } |
4626 | ||
4627 | ppc_current_csect = sym; | |
4628 | } | |
4629 | ||
85645aed TG |
4630 | static void |
4631 | ppc_change_debug_section (unsigned int idx, subsegT subseg) | |
4632 | { | |
4633 | segT sec; | |
4634 | flagword oldflags; | |
4635 | const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx]; | |
4636 | ||
51d29b8c | 4637 | sec = subseg_new (dw->xcoff_name, subseg); |
fd361982 | 4638 | oldflags = bfd_section_flags (sec); |
85645aed TG |
4639 | if (oldflags == SEC_NO_FLAGS) |
4640 | { | |
4641 | /* Just created section. */ | |
4642 | gas_assert (dw_sections[idx].sect == NULL); | |
4643 | ||
fd361982 AM |
4644 | bfd_set_section_flags (sec, SEC_DEBUGGING); |
4645 | bfd_set_section_alignment (sec, 0); | |
85645aed TG |
4646 | dw_sections[idx].sect = sec; |
4647 | } | |
4648 | ||
4649 | /* Not anymore in a csect. */ | |
4650 | ppc_current_csect = NULL; | |
4651 | } | |
4652 | ||
4653 | /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is: | |
4654 | .dwsect flag [, opt-label ] | |
4655 | */ | |
4656 | ||
4657 | static void | |
4658 | ppc_dwsect (int ignore ATTRIBUTE_UNUSED) | |
4659 | { | |
16de26a6 | 4660 | valueT flag; |
85645aed TG |
4661 | symbolS *opt_label; |
4662 | const struct xcoff_dwsect_name *dw; | |
4663 | struct dw_subsection *subseg; | |
4664 | struct dw_section *dws; | |
4665 | int i; | |
4666 | ||
4667 | /* Find section. */ | |
4668 | flag = get_absolute_expression (); | |
4669 | dw = NULL; | |
4670 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
4671 | if (xcoff_dwsect_names[i].flag == flag) | |
4672 | { | |
4673 | dw = &xcoff_dwsect_names[i]; | |
4674 | break; | |
4675 | } | |
4676 | ||
4677 | /* Parse opt-label. */ | |
4678 | if (*input_line_pointer == ',') | |
4679 | { | |
d02603dc | 4680 | char *label; |
85645aed TG |
4681 | char c; |
4682 | ||
4683 | ++input_line_pointer; | |
4684 | ||
d02603dc | 4685 | c = get_symbol_name (&label); |
85645aed | 4686 | opt_label = symbol_find_or_make (label); |
d02603dc | 4687 | (void) restore_line_pointer (c); |
85645aed TG |
4688 | } |
4689 | else | |
4690 | opt_label = NULL; | |
4691 | ||
4692 | demand_empty_rest_of_line (); | |
4693 | ||
4694 | /* Return now in case of unknown subsection. */ | |
4695 | if (dw == NULL) | |
4696 | { | |
d6ed37ed | 4697 | as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"), |
85645aed TG |
4698 | (unsigned)flag); |
4699 | return; | |
4700 | } | |
4701 | ||
4702 | /* Find the subsection. */ | |
4703 | dws = &dw_sections[i]; | |
4704 | subseg = NULL; | |
4705 | if (opt_label != NULL && S_IS_DEFINED (opt_label)) | |
4706 | { | |
4707 | /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */ | |
4708 | if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect) | |
4709 | { | |
4710 | as_bad (_("label %s was not defined in this dwarf section"), | |
4711 | S_GET_NAME (opt_label)); | |
4712 | subseg = dws->anon_subseg; | |
4713 | opt_label = NULL; | |
4714 | } | |
4715 | else | |
4716 | subseg = symbol_get_tc (opt_label)->u.dw; | |
4717 | } | |
4718 | ||
4719 | if (subseg != NULL) | |
4720 | { | |
4721 | /* Switch to the subsection. */ | |
4722 | ppc_change_debug_section (i, subseg->subseg); | |
4723 | } | |
4724 | else | |
4725 | { | |
4726 | /* Create a new dw subsection. */ | |
f681e586 | 4727 | subseg = XCNEW (struct dw_subsection); |
85645aed TG |
4728 | |
4729 | if (opt_label == NULL) | |
4730 | { | |
4731 | /* The anonymous one. */ | |
4732 | subseg->subseg = 0; | |
4733 | subseg->link = NULL; | |
4734 | dws->anon_subseg = subseg; | |
4735 | } | |
4736 | else | |
4737 | { | |
4738 | /* A named one. */ | |
4739 | if (dws->list_subseg != NULL) | |
4740 | subseg->subseg = dws->list_subseg->subseg + 1; | |
4741 | else | |
4742 | subseg->subseg = 1; | |
4743 | ||
4744 | subseg->link = dws->list_subseg; | |
4745 | dws->list_subseg = subseg; | |
4746 | symbol_get_tc (opt_label)->u.dw = subseg; | |
4747 | } | |
4748 | ||
4749 | ppc_change_debug_section (i, subseg->subseg); | |
4750 | ||
4751 | if (dw->def_size) | |
4752 | { | |
4753 | /* Add the length field. */ | |
4754 | expressionS *exp = &subseg->end_exp; | |
4755 | int sz; | |
4756 | ||
4757 | if (opt_label != NULL) | |
4758 | symbol_set_value_now (opt_label); | |
4759 | ||
4760 | /* Add the length field. Note that according to the AIX assembler | |
4761 | manual, the size of the length field is 4 for powerpc32 but | |
4762 | 12 for powerpc64. */ | |
4763 | if (ppc_obj64) | |
4764 | { | |
4765 | /* Write the 64bit marker. */ | |
4766 | md_number_to_chars (frag_more (4), -1, 4); | |
4767 | } | |
4768 | ||
4769 | exp->X_op = O_subtract; | |
4770 | exp->X_op_symbol = symbol_temp_new_now (); | |
4771 | exp->X_add_symbol = symbol_temp_make (); | |
4772 | ||
4773 | sz = ppc_obj64 ? 8 : 4; | |
4774 | exp->X_add_number = -sz; | |
4775 | emit_expr (exp, sz); | |
4776 | } | |
4777 | } | |
4778 | } | |
4779 | ||
252b5132 RH |
4780 | /* This function handles the .text and .data pseudo-ops. These |
4781 | pseudo-ops aren't really used by XCOFF; we implement them for the | |
4782 | convenience of people who aren't used to XCOFF. */ | |
4783 | ||
4784 | static void | |
98027b10 | 4785 | ppc_section (int type) |
252b5132 RH |
4786 | { |
4787 | const char *name; | |
4788 | symbolS *sym; | |
4789 | ||
4790 | if (type == 't') | |
4791 | name = ".text[PR]"; | |
4792 | else if (type == 'd') | |
4793 | name = ".data[RW]"; | |
4794 | else | |
4795 | abort (); | |
4796 | ||
4797 | sym = symbol_find_or_make (name); | |
4798 | ||
931e13a6 | 4799 | ppc_change_csect (sym, 2); |
252b5132 RH |
4800 | |
4801 | demand_empty_rest_of_line (); | |
4802 | } | |
4803 | ||
4804 | /* This function handles the .section pseudo-op. This is mostly to | |
4805 | give an error, since XCOFF only supports .text, .data and .bss, but | |
4806 | we do permit the user to name the text or data section. */ | |
4807 | ||
4808 | static void | |
98027b10 | 4809 | ppc_named_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4810 | { |
4811 | char *user_name; | |
4812 | const char *real_name; | |
4813 | char c; | |
4814 | symbolS *sym; | |
4815 | ||
d02603dc | 4816 | c = get_symbol_name (&user_name); |
252b5132 RH |
4817 | |
4818 | if (strcmp (user_name, ".text") == 0) | |
4819 | real_name = ".text[PR]"; | |
4820 | else if (strcmp (user_name, ".data") == 0) | |
4821 | real_name = ".data[RW]"; | |
4822 | else | |
4823 | { | |
d6ed37ed | 4824 | as_bad (_("the XCOFF file format does not support arbitrary sections")); |
d02603dc | 4825 | (void) restore_line_pointer (c); |
252b5132 RH |
4826 | ignore_rest_of_line (); |
4827 | return; | |
4828 | } | |
4829 | ||
d02603dc | 4830 | (void) restore_line_pointer (c); |
252b5132 RH |
4831 | |
4832 | sym = symbol_find_or_make (real_name); | |
4833 | ||
931e13a6 | 4834 | ppc_change_csect (sym, 2); |
252b5132 RH |
4835 | |
4836 | demand_empty_rest_of_line (); | |
4837 | } | |
4838 | ||
4839 | /* The .extern pseudo-op. We create an undefined symbol. */ | |
4840 | ||
4841 | static void | |
98027b10 | 4842 | ppc_extern (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4843 | { |
4844 | char *name; | |
4845 | char endc; | |
4846 | ||
d02603dc | 4847 | endc = get_symbol_name (&name); |
252b5132 RH |
4848 | |
4849 | (void) symbol_find_or_make (name); | |
4850 | ||
d02603dc | 4851 | (void) restore_line_pointer (endc); |
252b5132 RH |
4852 | |
4853 | demand_empty_rest_of_line (); | |
4854 | } | |
4855 | ||
4856 | /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */ | |
4857 | ||
4858 | static void | |
98027b10 | 4859 | ppc_lglobl (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4860 | { |
4861 | char *name; | |
4862 | char endc; | |
4863 | symbolS *sym; | |
4864 | ||
d02603dc | 4865 | endc = get_symbol_name (&name); |
252b5132 RH |
4866 | |
4867 | sym = symbol_find_or_make (name); | |
4868 | ||
d02603dc | 4869 | (void) restore_line_pointer (endc); |
252b5132 | 4870 | |
809ffe0d | 4871 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4872 | |
4873 | demand_empty_rest_of_line (); | |
4874 | } | |
4875 | ||
c865e45b RS |
4876 | /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF |
4877 | relocations at the beginning of the current csect. | |
4878 | ||
4879 | (In principle, there's no reason why the relocations _have_ to be at | |
4880 | the beginning. Anywhere in the csect would do. However, inserting | |
33eaf5de | 4881 | at the beginning is what the native assembler does, and it helps to |
c865e45b RS |
4882 | deal with cases where the .ref statements follow the section contents.) |
4883 | ||
4884 | ??? .refs don't work for empty .csects. However, the native assembler | |
4885 | doesn't report an error in this case, and neither yet do we. */ | |
4886 | ||
4887 | static void | |
4888 | ppc_ref (int ignore ATTRIBUTE_UNUSED) | |
4889 | { | |
4890 | char *name; | |
4891 | char c; | |
4892 | ||
4893 | if (ppc_current_csect == NULL) | |
4894 | { | |
4895 | as_bad (_(".ref outside .csect")); | |
4896 | ignore_rest_of_line (); | |
4897 | return; | |
4898 | } | |
4899 | ||
4900 | do | |
4901 | { | |
d02603dc | 4902 | c = get_symbol_name (&name); |
c865e45b RS |
4903 | |
4904 | fix_at_start (symbol_get_frag (ppc_current_csect), 0, | |
5b7c81bd | 4905 | symbol_find_or_make (name), 0, false, BFD_RELOC_NONE); |
c865e45b RS |
4906 | |
4907 | *input_line_pointer = c; | |
d02603dc | 4908 | SKIP_WHITESPACE_AFTER_NAME (); |
c865e45b RS |
4909 | c = *input_line_pointer; |
4910 | if (c == ',') | |
4911 | { | |
4912 | input_line_pointer++; | |
4913 | SKIP_WHITESPACE (); | |
4914 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
4915 | { | |
4916 | as_bad (_("missing symbol name")); | |
4917 | ignore_rest_of_line (); | |
4918 | return; | |
4919 | } | |
4920 | } | |
4921 | } | |
4922 | while (c == ','); | |
4923 | ||
4924 | demand_empty_rest_of_line (); | |
4925 | } | |
4926 | ||
252b5132 RH |
4927 | /* The .rename pseudo-op. The RS/6000 assembler can rename symbols, |
4928 | although I don't know why it bothers. */ | |
4929 | ||
4930 | static void | |
98027b10 | 4931 | ppc_rename (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4932 | { |
4933 | char *name; | |
4934 | char endc; | |
4935 | symbolS *sym; | |
4936 | int len; | |
4937 | ||
d02603dc | 4938 | endc = get_symbol_name (&name); |
252b5132 RH |
4939 | |
4940 | sym = symbol_find_or_make (name); | |
4941 | ||
d02603dc | 4942 | (void) restore_line_pointer (endc); |
252b5132 RH |
4943 | |
4944 | if (*input_line_pointer != ',') | |
4945 | { | |
4946 | as_bad (_("missing rename string")); | |
4947 | ignore_rest_of_line (); | |
4948 | return; | |
4949 | } | |
4950 | ++input_line_pointer; | |
4951 | ||
809ffe0d | 4952 | symbol_get_tc (sym)->real_name = demand_copy_C_string (&len); |
252b5132 RH |
4953 | |
4954 | demand_empty_rest_of_line (); | |
4955 | } | |
4956 | ||
4957 | /* The .stabx pseudo-op. This is similar to a normal .stabs | |
4958 | pseudo-op, but slightly different. A sample is | |
4959 | .stabx "main:F-1",.main,142,0 | |
4960 | The first argument is the symbol name to create. The second is the | |
4961 | value, and the third is the storage class. The fourth seems to be | |
4962 | always zero, and I am assuming it is the type. */ | |
4963 | ||
4964 | static void | |
98027b10 | 4965 | ppc_stabx (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4966 | { |
4967 | char *name; | |
4968 | int len; | |
4969 | symbolS *sym; | |
4970 | expressionS exp; | |
4971 | ||
4972 | name = demand_copy_C_string (&len); | |
4973 | ||
4974 | if (*input_line_pointer != ',') | |
4975 | { | |
4976 | as_bad (_("missing value")); | |
4977 | return; | |
4978 | } | |
4979 | ++input_line_pointer; | |
4980 | ||
5b7c81bd | 4981 | ppc_stab_symbol = true; |
252b5132 | 4982 | sym = symbol_make (name); |
5b7c81bd | 4983 | ppc_stab_symbol = false; |
252b5132 | 4984 | |
809ffe0d | 4985 | symbol_get_tc (sym)->real_name = name; |
252b5132 RH |
4986 | |
4987 | (void) expression (&exp); | |
4988 | ||
4989 | switch (exp.X_op) | |
4990 | { | |
4991 | case O_illegal: | |
4992 | case O_absent: | |
4993 | case O_big: | |
4994 | as_bad (_("illegal .stabx expression; zero assumed")); | |
4995 | exp.X_add_number = 0; | |
4996 | /* Fall through. */ | |
4997 | case O_constant: | |
4998 | S_SET_VALUE (sym, (valueT) exp.X_add_number); | |
809ffe0d | 4999 | symbol_set_frag (sym, &zero_address_frag); |
252b5132 RH |
5000 | break; |
5001 | ||
5002 | case O_symbol: | |
5003 | if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section) | |
809ffe0d | 5004 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5005 | else |
5006 | { | |
5007 | S_SET_VALUE (sym, | |
5008 | exp.X_add_number + S_GET_VALUE (exp.X_add_symbol)); | |
809ffe0d | 5009 | symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol)); |
252b5132 RH |
5010 | } |
5011 | break; | |
5012 | ||
5013 | default: | |
5014 | /* The value is some complex expression. This will probably | |
99a814a1 AM |
5015 | fail at some later point, but this is probably the right |
5016 | thing to do here. */ | |
809ffe0d | 5017 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5018 | break; |
5019 | } | |
5020 | ||
5021 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5022 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5023 | |
5024 | if (*input_line_pointer != ',') | |
5025 | { | |
5026 | as_bad (_("missing class")); | |
5027 | return; | |
5028 | } | |
5029 | ++input_line_pointer; | |
5030 | ||
5031 | S_SET_STORAGE_CLASS (sym, get_absolute_expression ()); | |
5032 | ||
5033 | if (*input_line_pointer != ',') | |
5034 | { | |
5035 | as_bad (_("missing type")); | |
5036 | return; | |
5037 | } | |
5038 | ++input_line_pointer; | |
5039 | ||
5040 | S_SET_DATA_TYPE (sym, get_absolute_expression ()); | |
5041 | ||
809ffe0d | 5042 | symbol_get_tc (sym)->output = 1; |
252b5132 | 5043 | |
c734e7e3 TG |
5044 | if (S_GET_STORAGE_CLASS (sym) == C_STSYM) |
5045 | { | |
5046 | /* In this case : | |
252b5132 | 5047 | |
c734e7e3 TG |
5048 | .bs name |
5049 | .stabx "z",arrays_,133,0 | |
5050 | .es | |
99a814a1 | 5051 | |
c734e7e3 | 5052 | .comm arrays_,13768,3 |
99a814a1 | 5053 | |
c734e7e3 TG |
5054 | resolve_symbol_value will copy the exp's "within" into sym's when the |
5055 | offset is 0. Since this seems to be corner case problem, | |
5056 | only do the correction for storage class C_STSYM. A better solution | |
5057 | would be to have the tc field updated in ppc_symbol_new_hook. */ | |
99a814a1 | 5058 | |
c734e7e3 TG |
5059 | if (exp.X_op == O_symbol) |
5060 | { | |
5061 | if (ppc_current_block == NULL) | |
5062 | as_bad (_(".stabx of storage class stsym must be within .bs/.es")); | |
99a814a1 | 5063 | |
c734e7e3 | 5064 | symbol_get_tc (sym)->within = ppc_current_block; |
c734e7e3 TG |
5065 | } |
5066 | } | |
99a814a1 | 5067 | |
252b5132 RH |
5068 | if (exp.X_op != O_symbol |
5069 | || ! S_IS_EXTERNAL (exp.X_add_symbol) | |
5070 | || S_GET_SEGMENT (exp.X_add_symbol) != bss_section) | |
5071 | ppc_frob_label (sym); | |
5072 | else | |
5073 | { | |
5074 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5075 | symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5076 | if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol) |
5077 | symbol_get_tc (ppc_current_csect)->within = sym; | |
252b5132 RH |
5078 | } |
5079 | ||
5080 | demand_empty_rest_of_line (); | |
5081 | } | |
5082 | ||
e86fc4a5 CC |
5083 | /* The .file pseudo-op. On XCOFF, .file can have several parameters |
5084 | which are being added to the symbol table to provide additional | |
5085 | information. */ | |
5086 | ||
5087 | static void | |
5088 | ppc_file (int ignore ATTRIBUTE_UNUSED) | |
5089 | { | |
5090 | char *sfname, *s1 = NULL, *s2 = NULL, *s3 = NULL; | |
5091 | int length, auxnb = 1; | |
5092 | ||
5093 | /* Some assemblers tolerate immediately following '"'. */ | |
5094 | if ((sfname = demand_copy_string (&length)) != 0) | |
5095 | { | |
5096 | coff_symbol_type *coffsym; | |
5097 | if (*input_line_pointer == ',') | |
5098 | { | |
5099 | ++input_line_pointer; | |
5100 | s1 = demand_copy_string (&length); | |
5101 | auxnb++; | |
5102 | ||
5103 | if (*input_line_pointer == ',') | |
5104 | { | |
5105 | ++input_line_pointer; | |
5106 | s2 = demand_copy_string (&length); | |
5107 | auxnb++; | |
5108 | ||
5109 | if (*input_line_pointer == ',') | |
5110 | { | |
5111 | ++input_line_pointer; | |
5112 | s3 = demand_copy_string (&length); | |
5113 | auxnb++; | |
5114 | } | |
5115 | } | |
5116 | } | |
5117 | ||
5118 | /* Use coff dot_file creation and adjust auxiliary entries. */ | |
5119 | c_dot_file_symbol (sfname, 0); | |
5120 | S_SET_NUMBER_AUXILIARY (symbol_rootP, auxnb); | |
5121 | coffsym = coffsymbol (symbol_get_bfdsym (symbol_rootP)); | |
5122 | coffsym->native[1].u.auxent.x_file.x_ftype = XFT_FN; | |
5123 | ||
5124 | if (s1) | |
5125 | { | |
5126 | coffsym->native[2].u.auxent.x_file.x_ftype = XFT_CT; | |
5127 | coffsym->native[2].extrap = s1; | |
5128 | } | |
5129 | if (s2) | |
5130 | { | |
5131 | coffsym->native[3].u.auxent.x_file.x_ftype = XFT_CV; | |
5132 | coffsym->native[3].extrap = s2; | |
5133 | } | |
5134 | if (s3) | |
5135 | { | |
5136 | coffsym->native[4].u.auxent.x_file.x_ftype = XFT_CD; | |
5137 | coffsym->native[4].extrap = s3; | |
5138 | } | |
5139 | ||
5140 | demand_empty_rest_of_line (); | |
5141 | } | |
5142 | } | |
5143 | ||
252b5132 RH |
5144 | /* The .function pseudo-op. This takes several arguments. The first |
5145 | argument seems to be the external name of the symbol. The second | |
67c1ffbe | 5146 | argument seems to be the label for the start of the function. gcc |
252b5132 RH |
5147 | uses the same name for both. I have no idea what the third and |
5148 | fourth arguments are meant to be. The optional fifth argument is | |
5149 | an expression for the size of the function. In COFF this symbol | |
5150 | gets an aux entry like that used for a csect. */ | |
5151 | ||
5152 | static void | |
98027b10 | 5153 | ppc_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5154 | { |
5155 | char *name; | |
5156 | char endc; | |
5157 | char *s; | |
5158 | symbolS *ext_sym; | |
5159 | symbolS *lab_sym; | |
5160 | ||
d02603dc | 5161 | endc = get_symbol_name (&name); |
252b5132 RH |
5162 | |
5163 | /* Ignore any [PR] suffix. */ | |
5164 | name = ppc_canonicalize_symbol_name (name); | |
5165 | s = strchr (name, '['); | |
5166 | if (s != (char *) NULL | |
5167 | && strcmp (s + 1, "PR]") == 0) | |
5168 | *s = '\0'; | |
5169 | ||
5170 | ext_sym = symbol_find_or_make (name); | |
5171 | ||
d02603dc | 5172 | (void) restore_line_pointer (endc); |
252b5132 RH |
5173 | |
5174 | if (*input_line_pointer != ',') | |
5175 | { | |
5176 | as_bad (_("missing symbol name")); | |
5177 | ignore_rest_of_line (); | |
5178 | return; | |
5179 | } | |
5180 | ++input_line_pointer; | |
5181 | ||
d02603dc | 5182 | endc = get_symbol_name (&name); |
252b5132 RH |
5183 | |
5184 | lab_sym = symbol_find_or_make (name); | |
5185 | ||
d02603dc | 5186 | (void) restore_line_pointer (endc); |
252b5132 RH |
5187 | |
5188 | if (ext_sym != lab_sym) | |
5189 | { | |
809ffe0d ILT |
5190 | expressionS exp; |
5191 | ||
5192 | exp.X_op = O_symbol; | |
5193 | exp.X_add_symbol = lab_sym; | |
5194 | exp.X_op_symbol = NULL; | |
5195 | exp.X_add_number = 0; | |
5196 | exp.X_unsigned = 0; | |
5197 | symbol_set_value_expression (ext_sym, &exp); | |
252b5132 RH |
5198 | } |
5199 | ||
96d56e9f NC |
5200 | if (symbol_get_tc (ext_sym)->symbol_class == -1) |
5201 | symbol_get_tc (ext_sym)->symbol_class = XMC_PR; | |
809ffe0d | 5202 | symbol_get_tc (ext_sym)->output = 1; |
252b5132 RH |
5203 | |
5204 | if (*input_line_pointer == ',') | |
5205 | { | |
91d6fa6a | 5206 | expressionS exp; |
252b5132 RH |
5207 | |
5208 | /* Ignore the third argument. */ | |
5209 | ++input_line_pointer; | |
91d6fa6a | 5210 | expression (& exp); |
252b5132 RH |
5211 | if (*input_line_pointer == ',') |
5212 | { | |
5213 | /* Ignore the fourth argument. */ | |
5214 | ++input_line_pointer; | |
91d6fa6a | 5215 | expression (& exp); |
252b5132 RH |
5216 | if (*input_line_pointer == ',') |
5217 | { | |
97834047 CC |
5218 | /* The fifth argument is the function size. |
5219 | If it's omitted, the size will be the containing csect. | |
5220 | This will be donce during ppc_frob_symtab. */ | |
252b5132 | 5221 | ++input_line_pointer; |
e01e1cee AM |
5222 | symbol_get_tc (ext_sym)->u.size |
5223 | = symbol_new ("L0\001", absolute_section, | |
5224 | &zero_address_frag, 0); | |
85645aed | 5225 | pseudo_set (symbol_get_tc (ext_sym)->u.size); |
252b5132 RH |
5226 | } |
5227 | } | |
5228 | } | |
5229 | ||
5230 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
5231 | SF_SET_FUNCTION (ext_sym); | |
5232 | SF_SET_PROCESS (ext_sym); | |
5233 | coff_add_linesym (ext_sym); | |
5234 | ||
5235 | demand_empty_rest_of_line (); | |
5236 | } | |
5237 | ||
5238 | /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named | |
8642cce8 TR |
5239 | ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym |
5240 | with the correct line number */ | |
5d6255fe | 5241 | |
8642cce8 | 5242 | static symbolS *saved_bi_sym = 0; |
252b5132 RH |
5243 | |
5244 | static void | |
98027b10 | 5245 | ppc_bf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5246 | { |
5247 | symbolS *sym; | |
5248 | ||
5249 | sym = symbol_make (".bf"); | |
5250 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5251 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5252 | S_SET_VALUE (sym, frag_now_fix ()); |
5253 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5254 | ||
5255 | coff_line_base = get_absolute_expression (); | |
5256 | ||
5257 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5258 | SA_SET_SYM_LNNO (sym, coff_line_base); | |
5259 | ||
8642cce8 | 5260 | /* Line number for bi. */ |
5d6255fe | 5261 | if (saved_bi_sym) |
8642cce8 TR |
5262 | { |
5263 | S_SET_VALUE (saved_bi_sym, coff_n_line_nos); | |
5264 | saved_bi_sym = 0; | |
5265 | } | |
5d6255fe | 5266 | |
8642cce8 | 5267 | |
809ffe0d | 5268 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5269 | |
5270 | ppc_frob_label (sym); | |
5271 | ||
5272 | demand_empty_rest_of_line (); | |
5273 | } | |
5274 | ||
5275 | /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named | |
5276 | ".ef", except that the line number is absolute, not relative to the | |
5277 | most recent ".bf" symbol. */ | |
5278 | ||
5279 | static void | |
98027b10 | 5280 | ppc_ef (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5281 | { |
5282 | symbolS *sym; | |
5283 | ||
5284 | sym = symbol_make (".ef"); | |
5285 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5286 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5287 | S_SET_VALUE (sym, frag_now_fix ()); |
5288 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5289 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5290 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5291 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5292 | |
5293 | ppc_frob_label (sym); | |
5294 | ||
5295 | demand_empty_rest_of_line (); | |
5296 | } | |
5297 | ||
5298 | /* The .bi and .ei pseudo-ops. These take a string argument and | |
5299 | generates a C_BINCL or C_EINCL symbol, which goes at the start of | |
8642cce8 TR |
5300 | the symbol list. The value of .bi will be know when the next .bf |
5301 | is encountered. */ | |
252b5132 RH |
5302 | |
5303 | static void | |
98027b10 | 5304 | ppc_biei (int ei) |
252b5132 RH |
5305 | { |
5306 | static symbolS *last_biei; | |
5307 | ||
5308 | char *name; | |
5309 | int len; | |
5310 | symbolS *sym; | |
5311 | symbolS *look; | |
5312 | ||
5313 | name = demand_copy_C_string (&len); | |
5314 | ||
5315 | /* The value of these symbols is actually file offset. Here we set | |
5316 | the value to the index into the line number entries. In | |
5317 | ppc_frob_symbols we set the fix_line field, which will cause BFD | |
5318 | to do the right thing. */ | |
5319 | ||
5320 | sym = symbol_make (name); | |
5321 | /* obj-coff.c currently only handles line numbers correctly in the | |
5322 | .text section. */ | |
5323 | S_SET_SEGMENT (sym, text_section); | |
5324 | S_SET_VALUE (sym, coff_n_line_nos); | |
809ffe0d | 5325 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5326 | |
5327 | S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL); | |
809ffe0d | 5328 | symbol_get_tc (sym)->output = 1; |
81d4177b | 5329 | |
8642cce8 | 5330 | /* Save bi. */ |
5d6255fe | 5331 | if (ei) |
8642cce8 TR |
5332 | saved_bi_sym = 0; |
5333 | else | |
5334 | saved_bi_sym = sym; | |
5335 | ||
252b5132 RH |
5336 | for (look = last_biei ? last_biei : symbol_rootP; |
5337 | (look != (symbolS *) NULL | |
5338 | && (S_GET_STORAGE_CLASS (look) == C_FILE | |
5339 | || S_GET_STORAGE_CLASS (look) == C_BINCL | |
5340 | || S_GET_STORAGE_CLASS (look) == C_EINCL)); | |
5341 | look = symbol_next (look)) | |
5342 | ; | |
5343 | if (look != (symbolS *) NULL) | |
5344 | { | |
5345 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5346 | symbol_insert (sym, look, &symbol_rootP, &symbol_lastP); | |
5347 | last_biei = sym; | |
5348 | } | |
5349 | ||
5350 | demand_empty_rest_of_line (); | |
5351 | } | |
5352 | ||
5353 | /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs". | |
5354 | There is one argument, which is a csect symbol. The value of the | |
5355 | .bs symbol is the index of this csect symbol. */ | |
5356 | ||
5357 | static void | |
98027b10 | 5358 | ppc_bs (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5359 | { |
5360 | char *name; | |
5361 | char endc; | |
5362 | symbolS *csect; | |
5363 | symbolS *sym; | |
5364 | ||
5365 | if (ppc_current_block != NULL) | |
5366 | as_bad (_("nested .bs blocks")); | |
5367 | ||
d02603dc | 5368 | endc = get_symbol_name (&name); |
252b5132 RH |
5369 | |
5370 | csect = symbol_find_or_make (name); | |
5371 | ||
d02603dc | 5372 | (void) restore_line_pointer (endc); |
252b5132 RH |
5373 | |
5374 | sym = symbol_make (".bs"); | |
5375 | S_SET_SEGMENT (sym, now_seg); | |
5376 | S_SET_STORAGE_CLASS (sym, C_BSTAT); | |
809ffe0d ILT |
5377 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5378 | symbol_get_tc (sym)->output = 1; | |
252b5132 | 5379 | |
809ffe0d | 5380 | symbol_get_tc (sym)->within = csect; |
252b5132 RH |
5381 | |
5382 | ppc_frob_label (sym); | |
5383 | ||
5384 | ppc_current_block = sym; | |
5385 | ||
5386 | demand_empty_rest_of_line (); | |
5387 | } | |
5388 | ||
5389 | /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */ | |
5390 | ||
5391 | static void | |
98027b10 | 5392 | ppc_es (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5393 | { |
5394 | symbolS *sym; | |
5395 | ||
5396 | if (ppc_current_block == NULL) | |
5397 | as_bad (_(".es without preceding .bs")); | |
5398 | ||
5399 | sym = symbol_make (".es"); | |
5400 | S_SET_SEGMENT (sym, now_seg); | |
5401 | S_SET_STORAGE_CLASS (sym, C_ESTAT); | |
809ffe0d ILT |
5402 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5403 | symbol_get_tc (sym)->output = 1; | |
252b5132 RH |
5404 | |
5405 | ppc_frob_label (sym); | |
5406 | ||
5407 | ppc_current_block = NULL; | |
5408 | ||
5409 | demand_empty_rest_of_line (); | |
5410 | } | |
5411 | ||
5412 | /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a | |
5413 | line number. */ | |
5414 | ||
5415 | static void | |
98027b10 | 5416 | ppc_bb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5417 | { |
5418 | symbolS *sym; | |
5419 | ||
5420 | sym = symbol_make (".bb"); | |
5421 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5422 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5423 | S_SET_VALUE (sym, frag_now_fix ()); |
5424 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5425 | ||
5426 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5427 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
5428 | ||
809ffe0d | 5429 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5430 | |
5431 | SF_SET_PROCESS (sym); | |
5432 | ||
5433 | ppc_frob_label (sym); | |
5434 | ||
5435 | demand_empty_rest_of_line (); | |
5436 | } | |
5437 | ||
5438 | /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a | |
5439 | line number. */ | |
5440 | ||
5441 | static void | |
98027b10 | 5442 | ppc_eb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5443 | { |
5444 | symbolS *sym; | |
5445 | ||
5446 | sym = symbol_make (".eb"); | |
5447 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5448 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5449 | S_SET_VALUE (sym, frag_now_fix ()); |
5450 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5451 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5452 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5453 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5454 | |
5455 | SF_SET_PROCESS (sym); | |
5456 | ||
5457 | ppc_frob_label (sym); | |
5458 | ||
5459 | demand_empty_rest_of_line (); | |
5460 | } | |
5461 | ||
5462 | /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a | |
5463 | specified name. */ | |
5464 | ||
5465 | static void | |
98027b10 | 5466 | ppc_bc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5467 | { |
5468 | char *name; | |
5469 | int len; | |
5470 | symbolS *sym; | |
5471 | ||
5472 | name = demand_copy_C_string (&len); | |
5473 | sym = symbol_make (name); | |
5474 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5475 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5476 | S_SET_STORAGE_CLASS (sym, C_BCOMM); |
5477 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5478 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5479 | |
5480 | ppc_frob_label (sym); | |
5481 | ||
5482 | demand_empty_rest_of_line (); | |
5483 | } | |
5484 | ||
5485 | /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */ | |
5486 | ||
5487 | static void | |
98027b10 | 5488 | ppc_ec (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5489 | { |
5490 | symbolS *sym; | |
5491 | ||
5492 | sym = symbol_make (".ec"); | |
5493 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5494 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5495 | S_SET_STORAGE_CLASS (sym, C_ECOMM); |
5496 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5497 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5498 | |
5499 | ppc_frob_label (sym); | |
5500 | ||
5501 | demand_empty_rest_of_line (); | |
5502 | } | |
5503 | ||
5504 | /* The .toc pseudo-op. Switch to the .toc subsegment. */ | |
5505 | ||
5506 | static void | |
98027b10 | 5507 | ppc_toc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5508 | { |
5509 | if (ppc_toc_csect != (symbolS *) NULL) | |
809ffe0d | 5510 | subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg); |
252b5132 RH |
5511 | else |
5512 | { | |
5513 | subsegT subseg; | |
5514 | symbolS *sym; | |
5515 | symbolS *list; | |
81d4177b | 5516 | |
1b2cb8e2 CC |
5517 | subseg = ppc_xcoff_data_section.next_subsegment; |
5518 | ++ppc_xcoff_data_section.next_subsegment; | |
252b5132 RH |
5519 | |
5520 | subseg_new (segment_name (data_section), subseg); | |
5521 | ppc_toc_frag = frag_now; | |
5522 | ||
5523 | sym = symbol_find_or_make ("TOC[TC0]"); | |
809ffe0d | 5524 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5525 | S_SET_SEGMENT (sym, data_section); |
5526 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
809ffe0d ILT |
5527 | symbol_get_tc (sym)->subseg = subseg; |
5528 | symbol_get_tc (sym)->output = 1; | |
5529 | symbol_get_tc (sym)->within = sym; | |
252b5132 RH |
5530 | |
5531 | ppc_toc_csect = sym; | |
81d4177b | 5532 | |
1b2cb8e2 | 5533 | for (list = ppc_xcoff_data_section.csects; |
809ffe0d ILT |
5534 | symbol_get_tc (list)->next != (symbolS *) NULL; |
5535 | list = symbol_get_tc (list)->next) | |
252b5132 | 5536 | ; |
809ffe0d | 5537 | symbol_get_tc (list)->next = sym; |
252b5132 RH |
5538 | |
5539 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5540 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
5541 | &symbol_lastP); | |
252b5132 RH |
5542 | } |
5543 | ||
5544 | ppc_current_csect = ppc_toc_csect; | |
5545 | ||
5546 | demand_empty_rest_of_line (); | |
5547 | } | |
5548 | ||
5549 | /* The AIX assembler automatically aligns the operands of a .long or | |
5550 | .short pseudo-op, and we want to be compatible. */ | |
5551 | ||
5552 | static void | |
98027b10 | 5553 | ppc_xcoff_cons (int log_size) |
252b5132 RH |
5554 | { |
5555 | frag_align (log_size, 0, 0); | |
5556 | record_alignment (now_seg, log_size); | |
5557 | cons (1 << log_size); | |
5558 | } | |
5559 | ||
5560 | static void | |
98027b10 | 5561 | ppc_vbyte (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
5562 | { |
5563 | expressionS exp; | |
5564 | int byte_count; | |
5565 | ||
5566 | (void) expression (&exp); | |
5567 | ||
5568 | if (exp.X_op != O_constant) | |
5569 | { | |
5570 | as_bad (_("non-constant byte count")); | |
5571 | return; | |
5572 | } | |
5573 | ||
5574 | byte_count = exp.X_add_number; | |
5575 | ||
5576 | if (*input_line_pointer != ',') | |
5577 | { | |
5578 | as_bad (_("missing value")); | |
5579 | return; | |
5580 | } | |
5581 | ||
5582 | ++input_line_pointer; | |
5583 | cons (byte_count); | |
5584 | } | |
5585 | ||
85645aed TG |
5586 | void |
5587 | ppc_xcoff_end (void) | |
5588 | { | |
5589 | int i; | |
5590 | ||
5591 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
5592 | { | |
5593 | struct dw_section *dws = &dw_sections[i]; | |
5594 | struct dw_subsection *dwss; | |
5595 | ||
5596 | if (dws->anon_subseg) | |
5597 | { | |
5598 | dwss = dws->anon_subseg; | |
5599 | dwss->link = dws->list_subseg; | |
5600 | } | |
5601 | else | |
5602 | dwss = dws->list_subseg; | |
5603 | ||
5604 | for (; dwss != NULL; dwss = dwss->link) | |
5605 | if (dwss->end_exp.X_add_symbol != NULL) | |
5606 | { | |
5607 | subseg_set (dws->sect, dwss->subseg); | |
5608 | symbol_set_value_now (dwss->end_exp.X_add_symbol); | |
5609 | } | |
5610 | } | |
22f72c48 | 5611 | ppc_cpu = 0; |
85645aed TG |
5612 | } |
5613 | ||
252b5132 | 5614 | #endif /* OBJ_XCOFF */ |
0baf16f2 | 5615 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 RH |
5616 | \f |
5617 | /* The .tc pseudo-op. This is used when generating either XCOFF or | |
5618 | ELF. This takes two or more arguments. | |
5619 | ||
5620 | When generating XCOFF output, the first argument is the name to | |
5621 | give to this location in the toc; this will be a symbol with class | |
0baf16f2 | 5622 | TC. The rest of the arguments are N-byte values to actually put at |
252b5132 | 5623 | this location in the TOC; often there is just one more argument, a |
1049f94e | 5624 | relocatable symbol reference. The size of the value to store |
0baf16f2 AM |
5625 | depends on target word size. A 32-bit target uses 4-byte values, a |
5626 | 64-bit target uses 8-byte values. | |
252b5132 RH |
5627 | |
5628 | When not generating XCOFF output, the arguments are the same, but | |
5629 | the first argument is simply ignored. */ | |
5630 | ||
5631 | static void | |
98027b10 | 5632 | ppc_tc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5633 | { |
5634 | #ifdef OBJ_XCOFF | |
5635 | ||
5636 | /* Define the TOC symbol name. */ | |
5637 | { | |
5638 | char *name; | |
5639 | char endc; | |
5640 | symbolS *sym; | |
5641 | ||
5642 | if (ppc_toc_csect == (symbolS *) NULL | |
5643 | || ppc_toc_csect != ppc_current_csect) | |
5644 | { | |
5645 | as_bad (_(".tc not in .toc section")); | |
5646 | ignore_rest_of_line (); | |
5647 | return; | |
5648 | } | |
5649 | ||
d02603dc | 5650 | endc = get_symbol_name (&name); |
252b5132 RH |
5651 | |
5652 | sym = symbol_find_or_make (name); | |
5653 | ||
d02603dc | 5654 | (void) restore_line_pointer (endc); |
252b5132 RH |
5655 | |
5656 | if (S_IS_DEFINED (sym)) | |
5657 | { | |
5658 | symbolS *label; | |
5659 | ||
809ffe0d | 5660 | label = symbol_get_tc (ppc_current_csect)->within; |
96d56e9f | 5661 | if (symbol_get_tc (label)->symbol_class != XMC_TC0) |
252b5132 RH |
5662 | { |
5663 | as_bad (_(".tc with no label")); | |
5664 | ignore_rest_of_line (); | |
5665 | return; | |
5666 | } | |
5667 | ||
5668 | S_SET_SEGMENT (label, S_GET_SEGMENT (sym)); | |
809ffe0d | 5669 | symbol_set_frag (label, symbol_get_frag (sym)); |
252b5132 RH |
5670 | S_SET_VALUE (label, S_GET_VALUE (sym)); |
5671 | ||
5672 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5673 | ++input_line_pointer; | |
5674 | ||
5675 | return; | |
5676 | } | |
5677 | ||
5678 | S_SET_SEGMENT (sym, now_seg); | |
809ffe0d | 5679 | symbol_set_frag (sym, frag_now); |
252b5132 | 5680 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4a403be0 CC |
5681 | |
5682 | /* AIX assembler seems to allow any storage class to be set in .tc. | |
5683 | But for now, only XMC_TC and XMC_TE are supported by us. */ | |
5684 | switch (symbol_get_tc (sym)->symbol_class) | |
5685 | { | |
5686 | case XMC_TC: | |
5687 | case XMC_TE: | |
5688 | break; | |
5689 | ||
5690 | default: | |
5691 | as_bad (_(".tc with storage class %d not yet supported"), | |
5692 | symbol_get_tc (sym)->symbol_class); | |
5693 | ignore_rest_of_line (); | |
5694 | return; | |
5695 | } | |
809ffe0d | 5696 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5697 | |
5698 | ppc_frob_label (sym); | |
5699 | } | |
5700 | ||
0baf16f2 AM |
5701 | #endif /* OBJ_XCOFF */ |
5702 | #ifdef OBJ_ELF | |
9c7977b3 | 5703 | int align; |
252b5132 RH |
5704 | |
5705 | /* Skip the TOC symbol name. */ | |
5706 | while (is_part_of_name (*input_line_pointer) | |
d13d4015 | 5707 | || *input_line_pointer == ' ' |
252b5132 RH |
5708 | || *input_line_pointer == '[' |
5709 | || *input_line_pointer == ']' | |
5710 | || *input_line_pointer == '{' | |
5711 | || *input_line_pointer == '}') | |
5712 | ++input_line_pointer; | |
5713 | ||
0baf16f2 | 5714 | /* Align to a four/eight byte boundary. */ |
2b3c4602 | 5715 | align = ppc_obj64 ? 3 : 2; |
9c7977b3 AM |
5716 | frag_align (align, 0, 0); |
5717 | record_alignment (now_seg, align); | |
0baf16f2 | 5718 | #endif /* OBJ_ELF */ |
252b5132 RH |
5719 | |
5720 | if (*input_line_pointer != ',') | |
5721 | demand_empty_rest_of_line (); | |
5722 | else | |
5723 | { | |
5724 | ++input_line_pointer; | |
2b3c4602 | 5725 | cons (ppc_obj64 ? 8 : 4); |
252b5132 RH |
5726 | } |
5727 | } | |
0baf16f2 AM |
5728 | |
5729 | /* Pseudo-op .machine. */ | |
0baf16f2 AM |
5730 | |
5731 | static void | |
98027b10 | 5732 | ppc_machine (int ignore ATTRIBUTE_UNUSED) |
0baf16f2 | 5733 | { |
d02603dc | 5734 | char c; |
69c040df AM |
5735 | char *cpu_string; |
5736 | #define MAX_HISTORY 100 | |
fa452fa6 | 5737 | static ppc_cpu_t *cpu_history; |
69c040df AM |
5738 | static int curr_hist; |
5739 | ||
5740 | SKIP_WHITESPACE (); | |
5741 | ||
d02603dc NC |
5742 | c = get_symbol_name (&cpu_string); |
5743 | cpu_string = xstrdup (cpu_string); | |
5744 | (void) restore_line_pointer (c); | |
69c040df AM |
5745 | |
5746 | if (cpu_string != NULL) | |
5747 | { | |
fa452fa6 | 5748 | ppc_cpu_t old_cpu = ppc_cpu; |
69c040df AM |
5749 | char *p; |
5750 | ||
5751 | for (p = cpu_string; *p != 0; p++) | |
5752 | *p = TOLOWER (*p); | |
5753 | ||
5754 | if (strcmp (cpu_string, "push") == 0) | |
5755 | { | |
5756 | if (cpu_history == NULL) | |
325801bd | 5757 | cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY); |
69c040df AM |
5758 | |
5759 | if (curr_hist >= MAX_HISTORY) | |
5760 | as_bad (_(".machine stack overflow")); | |
5761 | else | |
5762 | cpu_history[curr_hist++] = ppc_cpu; | |
5763 | } | |
5764 | else if (strcmp (cpu_string, "pop") == 0) | |
5765 | { | |
5766 | if (curr_hist <= 0) | |
5767 | as_bad (_(".machine stack underflow")); | |
5768 | else | |
5769 | ppc_cpu = cpu_history[--curr_hist]; | |
5770 | } | |
69c040df | 5771 | else |
b25f942e AM |
5772 | { |
5773 | ppc_cpu_t new_cpu; | |
5774 | /* Not using the global "sticky" variable here results in | |
5775 | none of the extra functional unit command line options, | |
5776 | -many, -maltivec, -mspe, -mspe2, -mvle, -mvsx, being in | |
5777 | force after selecting a new cpu with .machine. | |
5778 | ".machine altivec" and other extra functional unit | |
5779 | options do not count as a new machine, instead they add | |
5780 | to currently selected opcodes. */ | |
5781 | ppc_cpu_t machine_sticky = 0; | |
5782 | new_cpu = ppc_parse_cpu (ppc_cpu, &machine_sticky, cpu_string); | |
5783 | if (new_cpu != 0) | |
5784 | ppc_cpu = new_cpu; | |
5785 | else | |
5786 | as_bad (_("invalid machine `%s'"), cpu_string); | |
5787 | } | |
69c040df AM |
5788 | |
5789 | if (ppc_cpu != old_cpu) | |
5790 | ppc_setup_opcodes (); | |
5791 | } | |
5792 | ||
5793 | demand_empty_rest_of_line (); | |
0baf16f2 | 5794 | } |
0baf16f2 | 5795 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ |
252b5132 | 5796 | \f |
252b5132 RH |
5797 | #ifdef OBJ_XCOFF |
5798 | ||
5799 | /* XCOFF specific symbol and file handling. */ | |
5800 | ||
5801 | /* Canonicalize the symbol name. We use the to force the suffix, if | |
5802 | any, to use square brackets, and to be in upper case. */ | |
5803 | ||
5804 | char * | |
98027b10 | 5805 | ppc_canonicalize_symbol_name (char *name) |
252b5132 RH |
5806 | { |
5807 | char *s; | |
5808 | ||
5809 | if (ppc_stab_symbol) | |
5810 | return name; | |
5811 | ||
5812 | for (s = name; *s != '\0' && *s != '{' && *s != '['; s++) | |
5813 | ; | |
5814 | if (*s != '\0') | |
5815 | { | |
5816 | char brac; | |
5817 | ||
5818 | if (*s == '[') | |
5819 | brac = ']'; | |
5820 | else | |
5821 | { | |
5822 | *s = '['; | |
5823 | brac = '}'; | |
5824 | } | |
5825 | ||
5826 | for (s++; *s != '\0' && *s != brac; s++) | |
3882b010 | 5827 | *s = TOUPPER (*s); |
252b5132 RH |
5828 | |
5829 | if (*s == '\0' || s[1] != '\0') | |
5830 | as_bad (_("bad symbol suffix")); | |
5831 | ||
5832 | *s = ']'; | |
5833 | } | |
5834 | ||
5835 | return name; | |
5836 | } | |
5837 | ||
5838 | /* Set the class of a symbol based on the suffix, if any. This is | |
5839 | called whenever a new symbol is created. */ | |
5840 | ||
5841 | void | |
98027b10 | 5842 | ppc_symbol_new_hook (symbolS *sym) |
252b5132 | 5843 | { |
809ffe0d | 5844 | struct ppc_tc_sy *tc; |
252b5132 RH |
5845 | const char *s; |
5846 | ||
809ffe0d ILT |
5847 | tc = symbol_get_tc (sym); |
5848 | tc->next = NULL; | |
5849 | tc->output = 0; | |
96d56e9f | 5850 | tc->symbol_class = -1; |
809ffe0d ILT |
5851 | tc->real_name = NULL; |
5852 | tc->subseg = 0; | |
5853 | tc->align = 0; | |
85645aed TG |
5854 | tc->u.size = NULL; |
5855 | tc->u.dw = NULL; | |
809ffe0d | 5856 | tc->within = NULL; |
252b5132 RH |
5857 | |
5858 | if (ppc_stab_symbol) | |
5859 | return; | |
5860 | ||
5861 | s = strchr (S_GET_NAME (sym), '['); | |
5862 | if (s == (const char *) NULL) | |
5863 | { | |
5864 | /* There is no suffix. */ | |
5865 | return; | |
5866 | } | |
5867 | ||
5868 | ++s; | |
5869 | ||
5870 | switch (s[0]) | |
5871 | { | |
5872 | case 'B': | |
5873 | if (strcmp (s, "BS]") == 0) | |
96d56e9f | 5874 | tc->symbol_class = XMC_BS; |
252b5132 RH |
5875 | break; |
5876 | case 'D': | |
5877 | if (strcmp (s, "DB]") == 0) | |
96d56e9f | 5878 | tc->symbol_class = XMC_DB; |
252b5132 | 5879 | else if (strcmp (s, "DS]") == 0) |
96d56e9f | 5880 | tc->symbol_class = XMC_DS; |
252b5132 RH |
5881 | break; |
5882 | case 'G': | |
5883 | if (strcmp (s, "GL]") == 0) | |
96d56e9f | 5884 | tc->symbol_class = XMC_GL; |
252b5132 RH |
5885 | break; |
5886 | case 'P': | |
5887 | if (strcmp (s, "PR]") == 0) | |
96d56e9f | 5888 | tc->symbol_class = XMC_PR; |
252b5132 RH |
5889 | break; |
5890 | case 'R': | |
5891 | if (strcmp (s, "RO]") == 0) | |
96d56e9f | 5892 | tc->symbol_class = XMC_RO; |
252b5132 | 5893 | else if (strcmp (s, "RW]") == 0) |
96d56e9f | 5894 | tc->symbol_class = XMC_RW; |
252b5132 RH |
5895 | break; |
5896 | case 'S': | |
5897 | if (strcmp (s, "SV]") == 0) | |
96d56e9f | 5898 | tc->symbol_class = XMC_SV; |
252b5132 RH |
5899 | break; |
5900 | case 'T': | |
5901 | if (strcmp (s, "TC]") == 0) | |
96d56e9f | 5902 | tc->symbol_class = XMC_TC; |
252b5132 | 5903 | else if (strcmp (s, "TI]") == 0) |
96d56e9f | 5904 | tc->symbol_class = XMC_TI; |
252b5132 | 5905 | else if (strcmp (s, "TB]") == 0) |
96d56e9f | 5906 | tc->symbol_class = XMC_TB; |
252b5132 | 5907 | else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0) |
96d56e9f | 5908 | tc->symbol_class = XMC_TC0; |
4a403be0 CC |
5909 | else if (strcmp (s, "TE]") == 0) |
5910 | tc->symbol_class = XMC_TE; | |
1b2cb8e2 CC |
5911 | else if (strcmp (s, "TL]") == 0) |
5912 | tc->symbol_class = XMC_TL; | |
252b5132 RH |
5913 | break; |
5914 | case 'U': | |
5915 | if (strcmp (s, "UA]") == 0) | |
96d56e9f | 5916 | tc->symbol_class = XMC_UA; |
252b5132 | 5917 | else if (strcmp (s, "UC]") == 0) |
96d56e9f | 5918 | tc->symbol_class = XMC_UC; |
1b2cb8e2 CC |
5919 | else if (strcmp (s, "UL]") == 0) |
5920 | tc->symbol_class = XMC_UL; | |
252b5132 RH |
5921 | break; |
5922 | case 'X': | |
5923 | if (strcmp (s, "XO]") == 0) | |
96d56e9f | 5924 | tc->symbol_class = XMC_XO; |
252b5132 RH |
5925 | break; |
5926 | } | |
5927 | ||
96d56e9f | 5928 | if (tc->symbol_class == -1) |
d6ed37ed | 5929 | as_bad (_("unrecognized symbol suffix")); |
252b5132 RH |
5930 | } |
5931 | ||
252b5132 RH |
5932 | /* This variable is set by ppc_frob_symbol if any absolute symbols are |
5933 | seen. It tells ppc_adjust_symtab whether it needs to look through | |
5934 | the symbols. */ | |
5935 | ||
5b7c81bd | 5936 | static bool ppc_saw_abs; |
252b5132 RH |
5937 | |
5938 | /* Change the name of a symbol just before writing it out. Set the | |
5939 | real name if the .rename pseudo-op was used. Otherwise, remove any | |
5940 | class suffix. Return 1 if the symbol should not be included in the | |
5941 | symbol table. */ | |
5942 | ||
5943 | int | |
98027b10 | 5944 | ppc_frob_symbol (symbolS *sym) |
252b5132 RH |
5945 | { |
5946 | static symbolS *ppc_last_function; | |
5947 | static symbolS *set_end; | |
5948 | ||
5949 | /* Discard symbols that should not be included in the output symbol | |
5950 | table. */ | |
809ffe0d | 5951 | if (! symbol_used_in_reloc_p (sym) |
97834047 | 5952 | && S_GET_STORAGE_CLASS (sym) != C_DWARF |
809ffe0d | 5953 | && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0 |
670ec21d | 5954 | || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 5955 | && ! symbol_get_tc (sym)->output |
252b5132 RH |
5956 | && S_GET_STORAGE_CLASS (sym) != C_FILE))) |
5957 | return 1; | |
5958 | ||
a161fe53 AM |
5959 | /* This one will disappear anyway. Don't make a csect sym for it. */ |
5960 | if (sym == abs_section_sym) | |
5961 | return 1; | |
5962 | ||
809ffe0d ILT |
5963 | if (symbol_get_tc (sym)->real_name != (char *) NULL) |
5964 | S_SET_NAME (sym, symbol_get_tc (sym)->real_name); | |
252b5132 RH |
5965 | else |
5966 | { | |
5967 | const char *name; | |
5968 | const char *s; | |
5969 | ||
5970 | name = S_GET_NAME (sym); | |
5971 | s = strchr (name, '['); | |
5972 | if (s != (char *) NULL) | |
5973 | { | |
5974 | unsigned int len; | |
5975 | char *snew; | |
5976 | ||
5977 | len = s - name; | |
a44e2901 | 5978 | snew = xstrndup (name, len); |
252b5132 RH |
5979 | |
5980 | S_SET_NAME (sym, snew); | |
5981 | } | |
5982 | } | |
5983 | ||
5984 | if (set_end != (symbolS *) NULL) | |
5985 | { | |
5986 | SA_SET_SYM_ENDNDX (set_end, sym); | |
5987 | set_end = NULL; | |
5988 | } | |
5989 | ||
5990 | if (SF_GET_FUNCTION (sym)) | |
5991 | { | |
97834047 CC |
5992 | /* Make sure coff_last_function is reset. Otherwise, we won't create |
5993 | the auxent for the next function. */ | |
5994 | coff_last_function = 0; | |
252b5132 | 5995 | ppc_last_function = sym; |
85645aed | 5996 | if (symbol_get_tc (sym)->u.size != (symbolS *) NULL) |
252b5132 | 5997 | { |
85645aed | 5998 | resolve_symbol_value (symbol_get_tc (sym)->u.size); |
809ffe0d | 5999 | SA_SET_SYM_FSIZE (sym, |
85645aed | 6000 | (long) S_GET_VALUE (symbol_get_tc (sym)->u.size)); |
252b5132 | 6001 | } |
97834047 CC |
6002 | else |
6003 | { | |
6004 | /* Size of containing csect. */ | |
6005 | symbolS* within = symbol_get_tc (sym)->within; | |
6006 | union internal_auxent *csectaux; | |
6007 | csectaux = &coffsymbol (symbol_get_bfdsym (within)) | |
6008 | ->native[S_GET_NUMBER_AUXILIARY(within)].u.auxent; | |
6009 | ||
6010 | SA_SET_SYM_FSIZE (sym, csectaux->x_csect.x_scnlen.l); | |
6011 | } | |
252b5132 RH |
6012 | } |
6013 | else if (S_GET_STORAGE_CLASS (sym) == C_FCN | |
6014 | && strcmp (S_GET_NAME (sym), ".ef") == 0) | |
6015 | { | |
6016 | if (ppc_last_function == (symbolS *) NULL) | |
6017 | as_bad (_(".ef with no preceding .function")); | |
6018 | else | |
6019 | { | |
6020 | set_end = ppc_last_function; | |
6021 | ppc_last_function = NULL; | |
6022 | ||
6023 | /* We don't have a C_EFCN symbol, but we need to force the | |
6024 | COFF backend to believe that it has seen one. */ | |
6025 | coff_last_function = NULL; | |
6026 | } | |
6027 | } | |
6028 | ||
670ec21d | 6029 | if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 6030 | && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0 |
252b5132 RH |
6031 | && S_GET_STORAGE_CLASS (sym) != C_FILE |
6032 | && S_GET_STORAGE_CLASS (sym) != C_FCN | |
6033 | && S_GET_STORAGE_CLASS (sym) != C_BLOCK | |
6034 | && S_GET_STORAGE_CLASS (sym) != C_BSTAT | |
6035 | && S_GET_STORAGE_CLASS (sym) != C_ESTAT | |
6036 | && S_GET_STORAGE_CLASS (sym) != C_BINCL | |
6037 | && S_GET_STORAGE_CLASS (sym) != C_EINCL | |
6038 | && S_GET_SEGMENT (sym) != ppc_coff_debug_section) | |
6039 | S_SET_STORAGE_CLASS (sym, C_HIDEXT); | |
6040 | ||
6041 | if (S_GET_STORAGE_CLASS (sym) == C_EXT | |
8602d4fe | 6042 | || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT |
252b5132 RH |
6043 | || S_GET_STORAGE_CLASS (sym) == C_HIDEXT) |
6044 | { | |
6045 | int i; | |
6046 | union internal_auxent *a; | |
6047 | ||
6048 | /* Create a csect aux. */ | |
6049 | i = S_GET_NUMBER_AUXILIARY (sym); | |
6050 | S_SET_NUMBER_AUXILIARY (sym, i + 1); | |
809ffe0d | 6051 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent; |
96d56e9f | 6052 | if (symbol_get_tc (sym)->symbol_class == XMC_TC0) |
252b5132 RH |
6053 | { |
6054 | /* This is the TOC table. */ | |
6055 | know (strcmp (S_GET_NAME (sym), "TOC") == 0); | |
6056 | a->x_csect.x_scnlen.l = 0; | |
6057 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6058 | } | |
809ffe0d | 6059 | else if (symbol_get_tc (sym)->subseg != 0) |
252b5132 RH |
6060 | { |
6061 | /* This is a csect symbol. x_scnlen is the size of the | |
6062 | csect. */ | |
809ffe0d | 6063 | if (symbol_get_tc (sym)->next == (symbolS *) NULL) |
fd361982 | 6064 | a->x_csect.x_scnlen.l = (bfd_section_size (S_GET_SEGMENT (sym)) |
252b5132 RH |
6065 | - S_GET_VALUE (sym)); |
6066 | else | |
6067 | { | |
6386f3a7 | 6068 | resolve_symbol_value (symbol_get_tc (sym)->next); |
809ffe0d | 6069 | a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next) |
252b5132 RH |
6070 | - S_GET_VALUE (sym)); |
6071 | } | |
a83ef1c7 CC |
6072 | if (symbol_get_tc (sym)->symbol_class == XMC_BS |
6073 | || symbol_get_tc (sym)->symbol_class == XMC_UL) | |
bcf84703 CC |
6074 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; |
6075 | else | |
6076 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD; | |
252b5132 | 6077 | } |
1b2cb8e2 CC |
6078 | else if (S_GET_SEGMENT (sym) == bss_section |
6079 | || S_GET_SEGMENT (sym) == ppc_xcoff_tbss_section.segment) | |
252b5132 RH |
6080 | { |
6081 | /* This is a common symbol. */ | |
809ffe0d ILT |
6082 | a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset; |
6083 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; | |
1b2cb8e2 CC |
6084 | if (S_GET_SEGMENT (sym) == ppc_xcoff_tbss_section.segment) |
6085 | symbol_get_tc (sym)->symbol_class = XMC_UL; | |
6086 | else if (S_IS_EXTERNAL (sym)) | |
96d56e9f | 6087 | symbol_get_tc (sym)->symbol_class = XMC_RW; |
252b5132 | 6088 | else |
96d56e9f | 6089 | symbol_get_tc (sym)->symbol_class = XMC_BS; |
252b5132 RH |
6090 | } |
6091 | else if (S_GET_SEGMENT (sym) == absolute_section) | |
6092 | { | |
6093 | /* This is an absolute symbol. The csect will be created by | |
99a814a1 | 6094 | ppc_adjust_symtab. */ |
5b7c81bd | 6095 | ppc_saw_abs = true; |
252b5132 | 6096 | a->x_csect.x_smtyp = XTY_LD; |
96d56e9f NC |
6097 | if (symbol_get_tc (sym)->symbol_class == -1) |
6098 | symbol_get_tc (sym)->symbol_class = XMC_XO; | |
252b5132 RH |
6099 | } |
6100 | else if (! S_IS_DEFINED (sym)) | |
6101 | { | |
6102 | /* This is an external symbol. */ | |
6103 | a->x_csect.x_scnlen.l = 0; | |
6104 | a->x_csect.x_smtyp = XTY_ER; | |
6105 | } | |
4a403be0 | 6106 | else if (ppc_is_toc_sym (sym)) |
252b5132 RH |
6107 | { |
6108 | symbolS *next; | |
6109 | ||
6110 | /* This is a TOC definition. x_scnlen is the size of the | |
6111 | TOC entry. */ | |
6112 | next = symbol_next (sym); | |
96d56e9f | 6113 | while (symbol_get_tc (next)->symbol_class == XMC_TC0) |
252b5132 RH |
6114 | next = symbol_next (next); |
6115 | if (next == (symbolS *) NULL | |
4a403be0 | 6116 | || (!ppc_is_toc_sym (next))) |
252b5132 RH |
6117 | { |
6118 | if (ppc_after_toc_frag == (fragS *) NULL) | |
fd361982 | 6119 | a->x_csect.x_scnlen.l = (bfd_section_size (data_section) |
252b5132 RH |
6120 | - S_GET_VALUE (sym)); |
6121 | else | |
6122 | a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address | |
6123 | - S_GET_VALUE (sym)); | |
6124 | } | |
6125 | else | |
6126 | { | |
6386f3a7 | 6127 | resolve_symbol_value (next); |
252b5132 RH |
6128 | a->x_csect.x_scnlen.l = (S_GET_VALUE (next) |
6129 | - S_GET_VALUE (sym)); | |
6130 | } | |
6131 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6132 | } | |
6133 | else | |
6134 | { | |
6135 | symbolS *csect; | |
6136 | ||
6137 | /* This is a normal symbol definition. x_scnlen is the | |
6138 | symbol index of the containing csect. */ | |
6139 | if (S_GET_SEGMENT (sym) == text_section) | |
1b2cb8e2 | 6140 | csect = ppc_xcoff_text_section.csects; |
252b5132 | 6141 | else if (S_GET_SEGMENT (sym) == data_section) |
1b2cb8e2 CC |
6142 | csect = ppc_xcoff_data_section.csects; |
6143 | else if (S_GET_SEGMENT (sym) == ppc_xcoff_tdata_section.segment) | |
6144 | csect = ppc_xcoff_tdata_section.csects; | |
252b5132 RH |
6145 | else |
6146 | abort (); | |
6147 | ||
6148 | /* Skip the initial dummy symbol. */ | |
809ffe0d | 6149 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6150 | |
6151 | if (csect == (symbolS *) NULL) | |
6152 | { | |
6153 | as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym)); | |
6154 | a->x_csect.x_scnlen.l = 0; | |
6155 | } | |
6156 | else | |
6157 | { | |
809ffe0d | 6158 | while (symbol_get_tc (csect)->next != (symbolS *) NULL) |
252b5132 | 6159 | { |
6386f3a7 | 6160 | resolve_symbol_value (symbol_get_tc (csect)->next); |
809ffe0d ILT |
6161 | if (S_GET_VALUE (symbol_get_tc (csect)->next) |
6162 | > S_GET_VALUE (sym)) | |
252b5132 | 6163 | break; |
809ffe0d | 6164 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6165 | } |
6166 | ||
809ffe0d ILT |
6167 | a->x_csect.x_scnlen.p = |
6168 | coffsymbol (symbol_get_bfdsym (csect))->native; | |
6169 | coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen = | |
6170 | 1; | |
252b5132 RH |
6171 | } |
6172 | a->x_csect.x_smtyp = XTY_LD; | |
6173 | } | |
81d4177b | 6174 | |
252b5132 RH |
6175 | a->x_csect.x_parmhash = 0; |
6176 | a->x_csect.x_snhash = 0; | |
96d56e9f | 6177 | if (symbol_get_tc (sym)->symbol_class == -1) |
252b5132 RH |
6178 | a->x_csect.x_smclas = XMC_PR; |
6179 | else | |
96d56e9f | 6180 | a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class; |
252b5132 RH |
6181 | a->x_csect.x_stab = 0; |
6182 | a->x_csect.x_snstab = 0; | |
6183 | ||
6184 | /* Don't let the COFF backend resort these symbols. */ | |
809ffe0d | 6185 | symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END; |
252b5132 RH |
6186 | } |
6187 | else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT) | |
6188 | { | |
6189 | /* We want the value to be the symbol index of the referenced | |
6190 | csect symbol. BFD will do that for us if we set the right | |
6191 | flags. */ | |
b782de16 AM |
6192 | asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within); |
6193 | combined_entry_type *c = coffsymbol (bsym)->native; | |
6194 | ||
6195 | S_SET_VALUE (sym, (valueT) (size_t) c); | |
809ffe0d | 6196 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1; |
252b5132 RH |
6197 | } |
6198 | else if (S_GET_STORAGE_CLASS (sym) == C_STSYM) | |
6199 | { | |
6200 | symbolS *block; | |
c734e7e3 | 6201 | valueT base; |
252b5132 | 6202 | |
809ffe0d | 6203 | block = symbol_get_tc (sym)->within; |
c734e7e3 TG |
6204 | if (block) |
6205 | { | |
6206 | /* The value is the offset from the enclosing csect. */ | |
6207 | symbolS *csect; | |
6208 | ||
6209 | csect = symbol_get_tc (block)->within; | |
6210 | resolve_symbol_value (csect); | |
6211 | base = S_GET_VALUE (csect); | |
6212 | } | |
6213 | else | |
6214 | base = 0; | |
6215 | ||
6216 | S_SET_VALUE (sym, S_GET_VALUE (sym) - base); | |
252b5132 RH |
6217 | } |
6218 | else if (S_GET_STORAGE_CLASS (sym) == C_BINCL | |
6219 | || S_GET_STORAGE_CLASS (sym) == C_EINCL) | |
6220 | { | |
6221 | /* We want the value to be a file offset into the line numbers. | |
99a814a1 AM |
6222 | BFD will do that for us if we set the right flags. We have |
6223 | already set the value correctly. */ | |
809ffe0d | 6224 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1; |
252b5132 RH |
6225 | } |
6226 | ||
6227 | return 0; | |
6228 | } | |
6229 | ||
97834047 | 6230 | /* Adjust the symbol table. */ |
252b5132 RH |
6231 | |
6232 | void | |
98027b10 | 6233 | ppc_adjust_symtab (void) |
252b5132 RH |
6234 | { |
6235 | symbolS *sym; | |
97834047 CC |
6236 | symbolS *anchorSym; |
6237 | ||
6238 | /* Make sure C_DWARF symbols come right after C_FILE. | |
6239 | As the C_FILE might not be defined yet and as C_DWARF | |
6240 | might already be ordered, we insert them before the | |
6241 | first symbol which isn't a C_FILE or a C_DWARF. */ | |
6242 | for (anchorSym = symbol_rootP; anchorSym != NULL; | |
6243 | anchorSym = symbol_next (anchorSym)) | |
6244 | { | |
6245 | if (S_GET_STORAGE_CLASS (anchorSym) != C_FILE | |
6246 | && S_GET_STORAGE_CLASS (anchorSym) != C_DWARF) | |
6247 | break; | |
6248 | } | |
6249 | ||
6250 | sym = anchorSym; | |
6251 | while (sym != NULL) | |
6252 | { | |
6253 | if (S_GET_STORAGE_CLASS (sym) != C_DWARF) | |
6254 | { | |
6255 | sym = symbol_next (sym); | |
6256 | continue; | |
6257 | } | |
6258 | ||
6259 | symbolS* tsym = sym; | |
6260 | sym = symbol_next (sym); | |
6261 | ||
6262 | symbol_remove (tsym, &symbol_rootP, &symbol_lastP); | |
6263 | symbol_insert (tsym, anchorSym, &symbol_rootP, &symbol_lastP); | |
6264 | } | |
6265 | ||
6266 | /* Create csect symbols for all absolute symbols. */ | |
252b5132 RH |
6267 | |
6268 | if (! ppc_saw_abs) | |
6269 | return; | |
6270 | ||
6271 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
6272 | { | |
6273 | symbolS *csect; | |
6274 | int i; | |
6275 | union internal_auxent *a; | |
6276 | ||
6277 | if (S_GET_SEGMENT (sym) != absolute_section) | |
6278 | continue; | |
6279 | ||
6280 | csect = symbol_create (".abs[XO]", absolute_section, | |
e01e1cee | 6281 | &zero_address_frag, S_GET_VALUE (sym)); |
809ffe0d | 6282 | symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym); |
252b5132 RH |
6283 | S_SET_STORAGE_CLASS (csect, C_HIDEXT); |
6284 | i = S_GET_NUMBER_AUXILIARY (csect); | |
6285 | S_SET_NUMBER_AUXILIARY (csect, i + 1); | |
809ffe0d | 6286 | a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent; |
252b5132 RH |
6287 | a->x_csect.x_scnlen.l = 0; |
6288 | a->x_csect.x_smtyp = XTY_SD; | |
6289 | a->x_csect.x_parmhash = 0; | |
6290 | a->x_csect.x_snhash = 0; | |
6291 | a->x_csect.x_smclas = XMC_XO; | |
6292 | a->x_csect.x_stab = 0; | |
6293 | a->x_csect.x_snstab = 0; | |
6294 | ||
6295 | symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP); | |
6296 | ||
6297 | i = S_GET_NUMBER_AUXILIARY (sym); | |
809ffe0d ILT |
6298 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent; |
6299 | a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native; | |
6300 | coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1; | |
252b5132 RH |
6301 | } |
6302 | ||
5b7c81bd | 6303 | ppc_saw_abs = false; |
252b5132 RH |
6304 | } |
6305 | ||
6306 | /* Set the VMA for a section. This is called on all the sections in | |
6307 | turn. */ | |
6308 | ||
6309 | void | |
98027b10 | 6310 | ppc_frob_section (asection *sec) |
252b5132 | 6311 | { |
931e13a6 | 6312 | static bfd_vma vma = 0; |
252b5132 | 6313 | |
85645aed | 6314 | /* Dwarf sections start at 0. */ |
fd361982 | 6315 | if (bfd_section_flags (sec) & SEC_DEBUGGING) |
85645aed TG |
6316 | return; |
6317 | ||
931e13a6 | 6318 | vma = md_section_align (sec, vma); |
fd361982 AM |
6319 | bfd_set_section_vma (sec, vma); |
6320 | vma += bfd_section_size (sec); | |
252b5132 RH |
6321 | } |
6322 | ||
6323 | #endif /* OBJ_XCOFF */ | |
6324 | \f | |
6d4af3c2 | 6325 | const char * |
98027b10 | 6326 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 6327 | { |
499ac353 | 6328 | return ieee_md_atof (type, litp, sizep, target_big_endian); |
252b5132 RH |
6329 | } |
6330 | ||
6331 | /* Write a value out to the object file, using the appropriate | |
6332 | endianness. */ | |
6333 | ||
6334 | void | |
98027b10 | 6335 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
6336 | { |
6337 | if (target_big_endian) | |
6338 | number_to_chars_bigendian (buf, val, n); | |
6339 | else | |
6340 | number_to_chars_littleendian (buf, val, n); | |
6341 | } | |
6342 | ||
6343 | /* Align a section (I don't know why this is machine dependent). */ | |
6344 | ||
6345 | valueT | |
3aeeedbb | 6346 | md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr) |
252b5132 | 6347 | { |
3aeeedbb AM |
6348 | #ifdef OBJ_ELF |
6349 | return addr; | |
6350 | #else | |
fd361982 | 6351 | int align = bfd_section_alignment (seg); |
252b5132 | 6352 | |
8d3842cd | 6353 | return ((addr + (1 << align) - 1) & -(1 << align)); |
3aeeedbb | 6354 | #endif |
252b5132 RH |
6355 | } |
6356 | ||
6357 | /* We don't have any form of relaxing. */ | |
6358 | ||
6359 | int | |
98027b10 AM |
6360 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
6361 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
6362 | { |
6363 | abort (); | |
6364 | return 0; | |
6365 | } | |
6366 | ||
6367 | /* Convert a machine dependent frag. We never generate these. */ | |
6368 | ||
6369 | void | |
98027b10 AM |
6370 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
6371 | asection *sec ATTRIBUTE_UNUSED, | |
6372 | fragS *fragp ATTRIBUTE_UNUSED) | |
252b5132 RH |
6373 | { |
6374 | abort (); | |
6375 | } | |
6376 | ||
6377 | /* We have no need to default values of symbols. */ | |
6378 | ||
252b5132 | 6379 | symbolS * |
98027b10 | 6380 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
6381 | { |
6382 | return 0; | |
6383 | } | |
6384 | \f | |
6385 | /* Functions concerning relocs. */ | |
6386 | ||
6387 | /* The location from which a PC relative jump should be calculated, | |
6388 | given a PC relative reloc. */ | |
6389 | ||
6390 | long | |
98027b10 | 6391 | md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
6392 | { |
6393 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
6394 | } | |
6395 | ||
6396 | #ifdef OBJ_XCOFF | |
6397 | ||
c5df7e44 CC |
6398 | /* Return the surrending csect for sym when possible. */ |
6399 | ||
6400 | static symbolS* | |
6401 | ppc_get_csect_to_adjust (symbolS *sym) | |
6402 | { | |
6403 | if (sym == NULL) | |
6404 | return NULL; | |
6405 | ||
6406 | valueT val = resolve_symbol_value (sym); | |
6407 | TC_SYMFIELD_TYPE *tc = symbol_get_tc (sym); | |
6408 | segT symseg = S_GET_SEGMENT (sym); | |
6409 | ||
6410 | if (tc->subseg == 0 | |
6411 | && tc->symbol_class != XMC_TC0 | |
6412 | && tc->symbol_class != XMC_TC | |
6413 | && tc->symbol_class != XMC_TE | |
6414 | && symseg != bss_section | |
6415 | && symseg != ppc_xcoff_tbss_section.segment | |
6416 | /* Don't adjust if this is a reloc in the toc section. */ | |
6417 | && (symseg != data_section | |
6418 | || ppc_toc_csect == NULL | |
6419 | || val < ppc_toc_frag->fr_address | |
6420 | || (ppc_after_toc_frag != NULL | |
6421 | && val >= ppc_after_toc_frag->fr_address))) | |
6422 | { | |
6423 | symbolS* csect = tc->within; | |
6424 | ||
6425 | /* If the symbol was not declared by a label (eg: a section symbol), | |
6426 | use the section instead of the csect. This doesn't happen in | |
6427 | normal AIX assembly code. */ | |
6428 | if (csect == NULL) | |
6429 | csect = seg_info (symseg)->sym; | |
6430 | ||
6431 | return csect; | |
6432 | } | |
6433 | ||
6434 | return NULL; | |
6435 | } | |
6436 | ||
252b5132 RH |
6437 | /* This is called to see whether a fixup should be adjusted to use a |
6438 | section symbol. We take the opportunity to change a fixup against | |
6439 | a symbol in the TOC subsegment into a reloc against the | |
6440 | corresponding .tc symbol. */ | |
6441 | ||
6442 | int | |
98027b10 | 6443 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6444 | { |
b782de16 AM |
6445 | valueT val = resolve_symbol_value (fix->fx_addsy); |
6446 | segT symseg = S_GET_SEGMENT (fix->fx_addsy); | |
c5df7e44 | 6447 | symbolS* csect; |
b782de16 AM |
6448 | |
6449 | if (symseg == absolute_section) | |
6450 | return 0; | |
252b5132 | 6451 | |
85645aed | 6452 | /* Always adjust symbols in debugging sections. */ |
fd361982 | 6453 | if (bfd_section_flags (symseg) & SEC_DEBUGGING) |
85645aed TG |
6454 | return 1; |
6455 | ||
252b5132 | 6456 | if (ppc_toc_csect != (symbolS *) NULL |
252b5132 | 6457 | && fix->fx_addsy != ppc_toc_csect |
b782de16 | 6458 | && symseg == data_section |
252b5132 RH |
6459 | && val >= ppc_toc_frag->fr_address |
6460 | && (ppc_after_toc_frag == (fragS *) NULL | |
6461 | || val < ppc_after_toc_frag->fr_address)) | |
6462 | { | |
6463 | symbolS *sy; | |
6464 | ||
6465 | for (sy = symbol_next (ppc_toc_csect); | |
6466 | sy != (symbolS *) NULL; | |
6467 | sy = symbol_next (sy)) | |
6468 | { | |
b782de16 AM |
6469 | TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy); |
6470 | ||
96d56e9f | 6471 | if (sy_tc->symbol_class == XMC_TC0) |
252b5132 | 6472 | continue; |
4a403be0 CC |
6473 | if (sy_tc->symbol_class != XMC_TC |
6474 | && sy_tc->symbol_class != XMC_TE) | |
252b5132 | 6475 | break; |
b782de16 | 6476 | if (val == resolve_symbol_value (sy)) |
252b5132 RH |
6477 | { |
6478 | fix->fx_addsy = sy; | |
6479 | fix->fx_addnumber = val - ppc_toc_frag->fr_address; | |
6480 | return 0; | |
6481 | } | |
6482 | } | |
6483 | ||
6484 | as_bad_where (fix->fx_file, fix->fx_line, | |
6485 | _("symbol in .toc does not match any .tc")); | |
6486 | } | |
6487 | ||
6488 | /* Possibly adjust the reloc to be against the csect. */ | |
c5df7e44 | 6489 | if ((csect = ppc_get_csect_to_adjust (fix->fx_addsy)) != NULL) |
252b5132 | 6490 | { |
2fb4b302 TG |
6491 | fix->fx_offset += val - symbol_get_frag (csect)->fr_address; |
6492 | fix->fx_addsy = csect; | |
c5df7e44 | 6493 | } |
252b5132 | 6494 | |
c5df7e44 CC |
6495 | if ((csect = ppc_get_csect_to_adjust (fix->fx_subsy)) != NULL) |
6496 | { | |
6497 | fix->fx_offset -= resolve_symbol_value (fix->fx_subsy) | |
6498 | - symbol_get_frag (csect)->fr_address; | |
6499 | fix->fx_subsy = csect; | |
252b5132 RH |
6500 | } |
6501 | ||
6502 | /* Adjust a reloc against a .lcomm symbol to be against the base | |
6503 | .lcomm. */ | |
b782de16 | 6504 | if (symseg == bss_section |
bcf84703 CC |
6505 | && ! S_IS_EXTERNAL (fix->fx_addsy) |
6506 | && symbol_get_tc (fix->fx_addsy)->subseg == 0) | |
252b5132 | 6507 | { |
b782de16 AM |
6508 | symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol; |
6509 | ||
6510 | fix->fx_offset += val - resolve_symbol_value (sy); | |
6511 | fix->fx_addsy = sy; | |
252b5132 RH |
6512 | } |
6513 | ||
6514 | return 0; | |
6515 | } | |
6516 | ||
6517 | /* A reloc from one csect to another must be kept. The assembler | |
6518 | will, of course, keep relocs between sections, and it will keep | |
6519 | absolute relocs, but we need to force it to keep PC relative relocs | |
6520 | between two csects in the same section. */ | |
6521 | ||
6522 | int | |
98027b10 | 6523 | ppc_force_relocation (fixS *fix) |
252b5132 RH |
6524 | { |
6525 | /* At this point fix->fx_addsy should already have been converted to | |
6526 | a csect symbol. If the csect does not include the fragment, then | |
6527 | we need to force the relocation. */ | |
6528 | if (fix->fx_pcrel | |
6529 | && fix->fx_addsy != NULL | |
809ffe0d ILT |
6530 | && symbol_get_tc (fix->fx_addsy)->subseg != 0 |
6531 | && ((symbol_get_frag (fix->fx_addsy)->fr_address | |
6532 | > fix->fx_frag->fr_address) | |
6533 | || (symbol_get_tc (fix->fx_addsy)->next != NULL | |
6534 | && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address | |
252b5132 RH |
6535 | <= fix->fx_frag->fr_address)))) |
6536 | return 1; | |
6537 | ||
ae6063d4 | 6538 | return generic_force_reloc (fix); |
252b5132 | 6539 | } |
252b5132 RH |
6540 | #endif /* OBJ_XCOFF */ |
6541 | ||
0baf16f2 | 6542 | #ifdef OBJ_ELF |
a161fe53 AM |
6543 | /* If this function returns non-zero, it guarantees that a relocation |
6544 | will be emitted for a fixup. */ | |
6545 | ||
6546 | int | |
98027b10 | 6547 | ppc_force_relocation (fixS *fix) |
a161fe53 AM |
6548 | { |
6549 | /* Branch prediction relocations must force a relocation, as must | |
6550 | the vtable description relocs. */ | |
6551 | switch (fix->fx_r_type) | |
6552 | { | |
6553 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6554 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6555 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6556 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
c744ecf2 | 6557 | case BFD_RELOC_24_PLT_PCREL: |
a161fe53 | 6558 | case BFD_RELOC_PPC64_TOC: |
a161fe53 | 6559 | return 1; |
6911b7dc AM |
6560 | case BFD_RELOC_PPC_B26: |
6561 | case BFD_RELOC_PPC_BA26: | |
6562 | case BFD_RELOC_PPC_B16: | |
6563 | case BFD_RELOC_PPC_BA16: | |
05d0e962 | 6564 | case BFD_RELOC_PPC64_REL24_NOTOC: |
7aba54da | 6565 | case BFD_RELOC_PPC64_REL24_P9NOTOC: |
6911b7dc AM |
6566 | /* All branch fixups targeting a localentry symbol must |
6567 | force a relocation. */ | |
6568 | if (fix->fx_addsy) | |
6569 | { | |
6570 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6571 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6572 | gas_assert (elfsym); |
6573 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6574 | return 1; | |
6575 | } | |
6576 | break; | |
a161fe53 AM |
6577 | default: |
6578 | break; | |
6579 | } | |
6580 | ||
cdba85ec | 6581 | if (fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6582 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL) |
cdba85ec AM |
6583 | return 1; |
6584 | ||
ae6063d4 | 6585 | return generic_force_reloc (fix); |
a161fe53 AM |
6586 | } |
6587 | ||
0baf16f2 | 6588 | int |
98027b10 | 6589 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6590 | { |
6911b7dc AM |
6591 | switch (fix->fx_r_type) |
6592 | { | |
6593 | /* All branch fixups targeting a localentry symbol must | |
6594 | continue using the symbol. */ | |
6595 | case BFD_RELOC_PPC_B26: | |
6596 | case BFD_RELOC_PPC_BA26: | |
6597 | case BFD_RELOC_PPC_B16: | |
6598 | case BFD_RELOC_PPC_BA16: | |
6599 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6600 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6601 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6602 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
05d0e962 | 6603 | case BFD_RELOC_PPC64_REL24_NOTOC: |
7aba54da | 6604 | case BFD_RELOC_PPC64_REL24_P9NOTOC: |
6911b7dc AM |
6605 | if (fix->fx_addsy) |
6606 | { | |
6607 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6608 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6609 | gas_assert (elfsym); |
6610 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6611 | return 0; | |
6612 | } | |
6613 | break; | |
6614 | default: | |
6615 | break; | |
6616 | } | |
6617 | ||
0baf16f2 AM |
6618 | return (fix->fx_r_type != BFD_RELOC_16_GOTOFF |
6619 | && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
6620 | && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF | |
6621 | && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
cc9edbf3 AM |
6622 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS |
6623 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS | |
5663e321 | 6624 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT_PCREL34 |
334d91b9 AM |
6625 | && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL |
6626 | && fix->fx_r_type != BFD_RELOC_32_PLTOFF | |
6627 | && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL | |
6628 | && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF | |
6629 | && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF | |
6630 | && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF | |
6631 | && fix->fx_r_type != BFD_RELOC_64_PLTOFF | |
6632 | && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL | |
6633 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS | |
5663e321 | 6634 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT_PCREL34 |
334d91b9 AM |
6635 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16 |
6636 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO | |
6637 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI | |
6638 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA | |
6639 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS | |
6640 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS | |
0baf16f2 | 6641 | && fix->fx_r_type != BFD_RELOC_GPREL16 |
334d91b9 AM |
6642 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A |
6643 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A | |
6644 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A | |
0baf16f2 AM |
6645 | && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT |
6646 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY | |
cdba85ec | 6647 | && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6648 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL)); |
252b5132 | 6649 | } |
0baf16f2 | 6650 | #endif |
252b5132 | 6651 | |
b9c361e0 JL |
6652 | void |
6653 | ppc_frag_check (struct frag *fragP) | |
6654 | { | |
a9479dc0 AM |
6655 | if ((fragP->fr_address & fragP->insn_addr) != 0) |
6656 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
6657 | _("instruction address is not a multiple of %d"), | |
6658 | fragP->insn_addr + 1); | |
b9c361e0 JL |
6659 | } |
6660 | ||
22f72c48 AM |
6661 | /* rs_align_code frag handling. */ |
6662 | ||
6663 | enum ppc_nop_encoding_for_rs_align_code | |
6664 | { | |
6665 | PPC_NOP_VANILLA, | |
6666 | PPC_NOP_VLE, | |
6667 | PPC_NOP_GROUP_P6, | |
6668 | PPC_NOP_GROUP_P7 | |
6669 | }; | |
6670 | ||
6671 | unsigned int | |
6672 | ppc_nop_select (void) | |
6673 | { | |
6674 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) | |
6675 | return PPC_NOP_VLE; | |
6676 | if ((ppc_cpu & (PPC_OPCODE_POWER9 | PPC_OPCODE_E500MC)) == 0) | |
6677 | { | |
6678 | if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) | |
6679 | return PPC_NOP_GROUP_P7; | |
6680 | if ((ppc_cpu & PPC_OPCODE_POWER6) != 0) | |
6681 | return PPC_NOP_GROUP_P6; | |
6682 | } | |
6683 | return PPC_NOP_VANILLA; | |
6684 | } | |
3aeeedbb AM |
6685 | |
6686 | void | |
6687 | ppc_handle_align (struct frag *fragP) | |
6688 | { | |
6689 | valueT count = (fragP->fr_next->fr_address | |
6690 | - (fragP->fr_address + fragP->fr_fix)); | |
22f72c48 AM |
6691 | char *dest = fragP->fr_literal + fragP->fr_fix; |
6692 | enum ppc_nop_encoding_for_rs_align_code nop_select = *dest & 0xff; | |
6693 | ||
6694 | /* Pad with zeros if not inserting a whole number of instructions. | |
6695 | We could pad with zeros up to an instruction boundary then follow | |
6696 | with nops but odd counts indicate data in an executable section | |
6697 | so padding with zeros is most appropriate. */ | |
6698 | if (count == 0 | |
de626965 | 6699 | || (nop_select == PPC_NOP_VLE ? (count & 1) != 0 : (count & 3) != 0)) |
22f72c48 AM |
6700 | { |
6701 | *dest = 0; | |
6702 | return; | |
6703 | } | |
3aeeedbb | 6704 | |
22f72c48 | 6705 | if (nop_select == PPC_NOP_VLE) |
b9c361e0 | 6706 | { |
b9c361e0 JL |
6707 | |
6708 | fragP->fr_var = 2; | |
6709 | md_number_to_chars (dest, 0x4400, 2); | |
6710 | } | |
22f72c48 | 6711 | else |
3aeeedbb | 6712 | { |
3aeeedbb | 6713 | fragP->fr_var = 4; |
cef4f754 AM |
6714 | |
6715 | if (count > 4 * nop_limit && count < 0x2000000) | |
6716 | { | |
6717 | struct frag *rest; | |
6718 | ||
6719 | /* Make a branch, then follow with nops. Insert another | |
6720 | frag to handle the nops. */ | |
6721 | md_number_to_chars (dest, 0x48000000 + count, 4); | |
6722 | count -= 4; | |
6723 | if (count == 0) | |
6724 | return; | |
6725 | ||
6726 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6727 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
6728 | fragP->fr_next = rest; | |
6729 | fragP = rest; | |
6730 | rest->fr_address += rest->fr_fix + 4; | |
6731 | rest->fr_fix = 0; | |
6732 | /* If we leave the next frag as rs_align_code we'll come here | |
6733 | again, resulting in a bunch of branches rather than a | |
6734 | branch followed by nops. */ | |
6735 | rest->fr_type = rs_align; | |
6736 | dest = rest->fr_literal; | |
6737 | } | |
6738 | ||
3aeeedbb AM |
6739 | md_number_to_chars (dest, 0x60000000, 4); |
6740 | ||
22f72c48 | 6741 | if (nop_select >= PPC_NOP_GROUP_P6) |
3aeeedbb | 6742 | { |
3fea0c3b AM |
6743 | /* For power6, power7, and power8, we want the last nop to |
6744 | be a group terminating one. Do this by inserting an | |
6745 | rs_fill frag immediately after this one, with its address | |
6746 | set to the last nop location. This will automatically | |
6747 | reduce the number of nops in the current frag by one. */ | |
3aeeedbb AM |
6748 | if (count > 4) |
6749 | { | |
6750 | struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6751 | ||
6752 | memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG); | |
6753 | group_nop->fr_address = group_nop->fr_next->fr_address - 4; | |
6754 | group_nop->fr_fix = 0; | |
6755 | group_nop->fr_offset = 1; | |
6756 | group_nop->fr_type = rs_fill; | |
6757 | fragP->fr_next = group_nop; | |
6758 | dest = group_nop->fr_literal; | |
6759 | } | |
6760 | ||
22f72c48 | 6761 | if (nop_select == PPC_NOP_GROUP_P6) |
42240548 PB |
6762 | /* power6 group terminating nop: "ori 1,1,0". */ |
6763 | md_number_to_chars (dest, 0x60210000, 4); | |
22f72c48 AM |
6764 | else |
6765 | /* power7/power8 group terminating nop: "ori 2,2,0". */ | |
6766 | md_number_to_chars (dest, 0x60420000, 4); | |
3aeeedbb AM |
6767 | } |
6768 | } | |
6769 | } | |
6770 | ||
252b5132 | 6771 | /* Apply a fixup to the object code. This is called for all the |
3b8b57a9 | 6772 | fixups we generated by the calls to fix_new_exp, above. */ |
252b5132 | 6773 | |
94f592af | 6774 | void |
62ebcb5c | 6775 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
252b5132 | 6776 | { |
94f592af | 6777 | valueT value = * valP; |
5656a981 AM |
6778 | offsetT fieldval; |
6779 | const struct powerpc_operand *operand; | |
252b5132 RH |
6780 | |
6781 | #ifdef OBJ_ELF | |
94f592af | 6782 | if (fixP->fx_addsy != NULL) |
252b5132 | 6783 | { |
a161fe53 | 6784 | /* Hack around bfd_install_relocation brain damage. */ |
94f592af NC |
6785 | if (fixP->fx_pcrel) |
6786 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
a680de9a PB |
6787 | |
6788 | if (fixP->fx_addsy == abs_section_sym) | |
6789 | fixP->fx_done = 1; | |
252b5132 RH |
6790 | } |
6791 | else | |
94f592af | 6792 | fixP->fx_done = 1; |
252b5132 | 6793 | #else |
a161fe53 | 6794 | /* FIXME FIXME FIXME: The value we are passed in *valP includes |
7be1c489 AM |
6795 | the symbol values. If we are doing this relocation the code in |
6796 | write.c is going to call bfd_install_relocation, which is also | |
6797 | going to use the symbol value. That means that if the reloc is | |
6798 | fully resolved we want to use *valP since bfd_install_relocation is | |
6799 | not being used. | |
9f0eb232 RS |
6800 | However, if the reloc is not fully resolved we do not want to |
6801 | use *valP, and must use fx_offset instead. If the relocation | |
6802 | is PC-relative, we then need to re-apply md_pcrel_from_section | |
6803 | to this new relocation value. */ | |
94f592af NC |
6804 | if (fixP->fx_addsy == (symbolS *) NULL) |
6805 | fixP->fx_done = 1; | |
6806 | ||
252b5132 | 6807 | else |
9f0eb232 RS |
6808 | { |
6809 | value = fixP->fx_offset; | |
6810 | if (fixP->fx_pcrel) | |
6811 | value -= md_pcrel_from_section (fixP, seg); | |
6812 | } | |
a161fe53 AM |
6813 | #endif |
6814 | ||
7ba71655 AM |
6815 | /* We are only able to convert some relocs to pc-relative. */ |
6816 | if (fixP->fx_pcrel) | |
6817 | { | |
6818 | switch (fixP->fx_r_type) | |
6819 | { | |
4a969973 AM |
6820 | case BFD_RELOC_64: |
6821 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
6822 | break; | |
6823 | ||
6824 | case BFD_RELOC_32: | |
6825 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
6826 | break; | |
6827 | ||
6828 | case BFD_RELOC_16: | |
6829 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
6830 | break; | |
6831 | ||
7ba71655 AM |
6832 | case BFD_RELOC_LO16: |
6833 | fixP->fx_r_type = BFD_RELOC_LO16_PCREL; | |
6834 | break; | |
6835 | ||
6836 | case BFD_RELOC_HI16: | |
6837 | fixP->fx_r_type = BFD_RELOC_HI16_PCREL; | |
6838 | break; | |
6839 | ||
6840 | case BFD_RELOC_HI16_S: | |
6841 | fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL; | |
6842 | break; | |
6843 | ||
4a969973 AM |
6844 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
6845 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH; | |
7ba71655 AM |
6846 | break; |
6847 | ||
4a969973 AM |
6848 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
6849 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA; | |
7ba71655 AM |
6850 | break; |
6851 | ||
4a969973 AM |
6852 | case BFD_RELOC_PPC64_HIGHER: |
6853 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER; | |
6854 | break; | |
6855 | ||
6856 | case BFD_RELOC_PPC64_HIGHER_S: | |
6857 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA; | |
6858 | break; | |
6859 | ||
6860 | case BFD_RELOC_PPC64_HIGHEST: | |
6861 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST; | |
6862 | break; | |
6863 | ||
6864 | case BFD_RELOC_PPC64_HIGHEST_S: | |
6865 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA; | |
7ba71655 AM |
6866 | break; |
6867 | ||
5663e321 AM |
6868 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
6869 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER34; | |
6870 | break; | |
6871 | ||
6872 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
6873 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA34; | |
6874 | break; | |
6875 | ||
6876 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
6877 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST34; | |
6878 | break; | |
6879 | ||
6880 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
6881 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA34; | |
6882 | break; | |
6883 | ||
7ba71655 AM |
6884 | case BFD_RELOC_PPC_16DX_HA: |
6885 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
6886 | break; | |
6887 | ||
5663e321 AM |
6888 | case BFD_RELOC_PPC64_D34: |
6889 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL34; | |
6890 | break; | |
6891 | ||
6892 | case BFD_RELOC_PPC64_D28: | |
6893 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL28; | |
6894 | break; | |
6895 | ||
7ba71655 AM |
6896 | default: |
6897 | break; | |
6898 | } | |
6899 | } | |
6900 | else if (!fixP->fx_done | |
6901 | && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA) | |
252b5132 | 6902 | { |
7ba71655 AM |
6903 | /* addpcis is relative to next insn address. */ |
6904 | value -= 4; | |
6905 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
6906 | fixP->fx_pcrel = 1; | |
252b5132 | 6907 | } |
252b5132 | 6908 | |
5656a981 | 6909 | operand = NULL; |
3b8b57a9 | 6910 | if (fixP->fx_pcrel_adjust != 0) |
252b5132 | 6911 | { |
5656a981 | 6912 | /* This is a fixup on an instruction. */ |
3b8b57a9 | 6913 | int opindex = fixP->fx_pcrel_adjust & 0xff; |
252b5132 | 6914 | |
5656a981 | 6915 | operand = &powerpc_operands[opindex]; |
252b5132 | 6916 | #ifdef OBJ_XCOFF |
0baf16f2 AM |
6917 | /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol |
6918 | does not generate a reloc. It uses the offset of `sym' within its | |
6919 | csect. Other usages, such as `.long sym', generate relocs. This | |
6920 | is the documented behaviour of non-TOC symbols. */ | |
252b5132 | 6921 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
b84bf58a | 6922 | && (operand->bitm & 0xfff0) == 0xfff0 |
252b5132 | 6923 | && operand->shift == 0 |
2b3c4602 | 6924 | && (operand->insert == NULL || ppc_obj64) |
94f592af NC |
6925 | && fixP->fx_addsy != NULL |
6926 | && symbol_get_tc (fixP->fx_addsy)->subseg != 0 | |
4a403be0 | 6927 | && !ppc_is_toc_sym (fixP->fx_addsy) |
94f592af | 6928 | && S_GET_SEGMENT (fixP->fx_addsy) != bss_section) |
252b5132 | 6929 | { |
94f592af NC |
6930 | value = fixP->fx_offset; |
6931 | fixP->fx_done = 1; | |
252b5132 | 6932 | } |
ac21e7da TG |
6933 | |
6934 | /* During parsing of instructions, a TOC16 reloc is generated for | |
6935 | instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined | |
6936 | in the toc. But at parse time, SYM may be not yet defined, so | |
6937 | check again here. */ | |
6938 | if (fixP->fx_r_type == BFD_RELOC_16 | |
6939 | && fixP->fx_addsy != NULL | |
6940 | && ppc_is_toc_sym (fixP->fx_addsy)) | |
4a403be0 | 6941 | fixP->fx_r_type = BFD_RELOC_PPC_TOC16; |
252b5132 | 6942 | #endif |
5656a981 AM |
6943 | } |
6944 | ||
6945 | /* Calculate value to be stored in field. */ | |
6946 | fieldval = value; | |
6947 | switch (fixP->fx_r_type) | |
6948 | { | |
1ec2d25e | 6949 | #ifdef OBJ_ELF |
5656a981 AM |
6950 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
6951 | case BFD_RELOC_PPC_VLE_LO16A: | |
6952 | case BFD_RELOC_PPC_VLE_LO16D: | |
1ec2d25e | 6953 | #endif |
5656a981 AM |
6954 | case BFD_RELOC_LO16: |
6955 | case BFD_RELOC_LO16_PCREL: | |
6956 | fieldval = value & 0xffff; | |
6957 | sign_extend_16: | |
6958 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
f9c6b907 | 6959 | fieldval = SEX16 (fieldval); |
5656a981 AM |
6960 | fixP->fx_no_overflow = 1; |
6961 | break; | |
3c9d25f4 | 6962 | |
f9c6b907 AM |
6963 | case BFD_RELOC_HI16: |
6964 | case BFD_RELOC_HI16_PCREL: | |
5656a981 | 6965 | #ifdef OBJ_ELF |
f9c6b907 AM |
6966 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
6967 | { | |
6968 | fieldval = value >> 16; | |
6969 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
6970 | { | |
6971 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
6972 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
6973 | } | |
6974 | break; | |
6975 | } | |
2b0f3761 | 6976 | /* Fallthru */ |
f9c6b907 | 6977 | |
5656a981 AM |
6978 | case BFD_RELOC_PPC_VLE_HI16A: |
6979 | case BFD_RELOC_PPC_VLE_HI16D: | |
f9c6b907 | 6980 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
5656a981 | 6981 | #endif |
5656a981 AM |
6982 | fieldval = PPC_HI (value); |
6983 | goto sign_extend_16; | |
0baf16f2 | 6984 | |
f9c6b907 AM |
6985 | case BFD_RELOC_HI16_S: |
6986 | case BFD_RELOC_HI16_S_PCREL: | |
7ba71655 | 6987 | case BFD_RELOC_PPC_16DX_HA: |
a680de9a | 6988 | case BFD_RELOC_PPC_REL16DX_HA: |
5656a981 | 6989 | #ifdef OBJ_ELF |
f9c6b907 AM |
6990 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
6991 | { | |
6992 | fieldval = (value + 0x8000) >> 16; | |
6993 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
6994 | { | |
6995 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
6996 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
6997 | } | |
6998 | break; | |
6999 | } | |
2b0f3761 | 7000 | /* Fallthru */ |
f9c6b907 | 7001 | |
5656a981 AM |
7002 | case BFD_RELOC_PPC_VLE_HA16A: |
7003 | case BFD_RELOC_PPC_VLE_HA16D: | |
f9c6b907 | 7004 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
5656a981 | 7005 | #endif |
5656a981 AM |
7006 | fieldval = PPC_HA (value); |
7007 | goto sign_extend_16; | |
0baf16f2 | 7008 | |
3b8b57a9 | 7009 | #ifdef OBJ_ELF |
5656a981 AM |
7010 | case BFD_RELOC_PPC64_HIGHER: |
7011 | fieldval = PPC_HIGHER (value); | |
7012 | goto sign_extend_16; | |
252b5132 | 7013 | |
5656a981 AM |
7014 | case BFD_RELOC_PPC64_HIGHER_S: |
7015 | fieldval = PPC_HIGHERA (value); | |
7016 | goto sign_extend_16; | |
0baf16f2 | 7017 | |
5656a981 AM |
7018 | case BFD_RELOC_PPC64_HIGHEST: |
7019 | fieldval = PPC_HIGHEST (value); | |
7020 | goto sign_extend_16; | |
0baf16f2 | 7021 | |
5656a981 AM |
7022 | case BFD_RELOC_PPC64_HIGHEST_S: |
7023 | fieldval = PPC_HIGHESTA (value); | |
7024 | goto sign_extend_16; | |
7025 | #endif | |
7026 | ||
7027 | default: | |
7028 | break; | |
7029 | } | |
7030 | ||
7031 | if (operand != NULL) | |
7032 | { | |
7033 | /* Handle relocs in an insn. */ | |
5656a981 AM |
7034 | switch (fixP->fx_r_type) |
7035 | { | |
7fa9fcb6 | 7036 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7037 | /* The following relocs can't be calculated by the assembler. |
7038 | Leave the field zero. */ | |
cdba85ec AM |
7039 | case BFD_RELOC_PPC_TPREL16: |
7040 | case BFD_RELOC_PPC_TPREL16_LO: | |
7041 | case BFD_RELOC_PPC_TPREL16_HI: | |
7042 | case BFD_RELOC_PPC_TPREL16_HA: | |
cdba85ec AM |
7043 | case BFD_RELOC_PPC_DTPREL16: |
7044 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7045 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7046 | case BFD_RELOC_PPC_DTPREL16_HA: | |
cdba85ec AM |
7047 | case BFD_RELOC_PPC_GOT_TLSGD16: |
7048 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7049 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7050 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7051 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7052 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7053 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7054 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7055 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7056 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7057 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7058 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7059 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7060 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7061 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7062 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7063 | case BFD_RELOC_PPC64_TPREL16_DS: | |
7064 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
f9c6b907 AM |
7065 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7066 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
cdba85ec AM |
7067 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7068 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7069 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7070 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
f9c6b907 AM |
7071 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7072 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
cdba85ec AM |
7073 | case BFD_RELOC_PPC64_DTPREL16_DS: |
7074 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
7075 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
7076 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7077 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7078 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
c213164a AM |
7079 | case BFD_RELOC_PPC64_TPREL34: |
7080 | case BFD_RELOC_PPC64_DTPREL34: | |
87c69f97 AM |
7081 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
7082 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
7083 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
7084 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
3b8b57a9 | 7085 | gas_assert (fixP->fx_addsy != NULL); |
7c1d0959 | 7086 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
3b8b57a9 | 7087 | fieldval = 0; |
cdba85ec | 7088 | break; |
3b8b57a9 AM |
7089 | |
7090 | /* These also should leave the field zero for the same | |
7091 | reason. Note that older versions of gas wrote values | |
7092 | here. If we want to go back to the old behaviour, then | |
7093 | all _LO and _LO_DS cases will need to be treated like | |
7094 | BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */ | |
7095 | case BFD_RELOC_16_GOTOFF: | |
7096 | case BFD_RELOC_LO16_GOTOFF: | |
7097 | case BFD_RELOC_HI16_GOTOFF: | |
7098 | case BFD_RELOC_HI16_S_GOTOFF: | |
7099 | case BFD_RELOC_LO16_PLTOFF: | |
7100 | case BFD_RELOC_HI16_PLTOFF: | |
7101 | case BFD_RELOC_HI16_S_PLTOFF: | |
7102 | case BFD_RELOC_GPREL16: | |
7103 | case BFD_RELOC_16_BASEREL: | |
7104 | case BFD_RELOC_LO16_BASEREL: | |
7105 | case BFD_RELOC_HI16_BASEREL: | |
7106 | case BFD_RELOC_HI16_S_BASEREL: | |
7107 | case BFD_RELOC_PPC_TOC16: | |
7108 | case BFD_RELOC_PPC64_TOC16_LO: | |
7109 | case BFD_RELOC_PPC64_TOC16_HI: | |
7110 | case BFD_RELOC_PPC64_TOC16_HA: | |
7111 | case BFD_RELOC_PPC64_PLTGOT16: | |
7112 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
7113 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
7114 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
7115 | case BFD_RELOC_PPC64_GOT16_DS: | |
7116 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
7117 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
7118 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
7119 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
7120 | case BFD_RELOC_PPC64_TOC16_DS: | |
7121 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
7122 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
7123 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
7124 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7125 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7126 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7127 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7128 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7129 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7130 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
252b5132 | 7131 | case BFD_RELOC_PPC_EMB_SDA21: |
3b8b57a9 AM |
7132 | case BFD_RELOC_PPC_EMB_MRKREF: |
7133 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7134 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7135 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7136 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7137 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7138 | case BFD_RELOC_PPC_EMB_RELSDA: | |
7139 | case BFD_RELOC_PPC_VLE_SDA21: | |
7140 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7141 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7142 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
7143 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7144 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
7145 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7146 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
5663e321 AM |
7147 | case BFD_RELOC_PPC64_GOT_PCREL34: |
7148 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
3b8b57a9 | 7149 | gas_assert (fixP->fx_addsy != NULL); |
2b0f3761 | 7150 | /* Fallthru */ |
3b8b57a9 AM |
7151 | |
7152 | case BFD_RELOC_PPC_TLS: | |
7153 | case BFD_RELOC_PPC_TLSGD: | |
7154 | case BFD_RELOC_PPC_TLSLD: | |
c213164a | 7155 | case BFD_RELOC_PPC64_TLS_PCREL: |
3b8b57a9 | 7156 | fieldval = 0; |
3b8b57a9 | 7157 | break; |
7fa9fcb6 TG |
7158 | #endif |
7159 | ||
7160 | #ifdef OBJ_XCOFF | |
7161 | case BFD_RELOC_PPC_B16: | |
7162 | /* Adjust the offset to the instruction boundary. */ | |
7163 | fieldval += 2; | |
7164 | break; | |
7165 | #endif | |
252b5132 | 7166 | |
f728387b AM |
7167 | case BFD_RELOC_VTABLE_INHERIT: |
7168 | case BFD_RELOC_VTABLE_ENTRY: | |
7169 | case BFD_RELOC_PPC_DTPMOD: | |
7170 | case BFD_RELOC_PPC_TPREL: | |
7171 | case BFD_RELOC_PPC_DTPREL: | |
7172 | case BFD_RELOC_PPC_COPY: | |
7173 | case BFD_RELOC_PPC_GLOB_DAT: | |
7174 | case BFD_RELOC_32_PLT_PCREL: | |
7175 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7176 | case BFD_RELOC_PPC64_TOC: | |
7177 | case BFD_RELOC_CTOR: | |
7178 | case BFD_RELOC_32: | |
7179 | case BFD_RELOC_32_PCREL: | |
7180 | case BFD_RELOC_RVA: | |
7181 | case BFD_RELOC_64: | |
7182 | case BFD_RELOC_64_PCREL: | |
7183 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
7184 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7185 | _("%s unsupported as instruction fixup"), | |
7186 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
7187 | fixP->fx_done = 1; | |
7188 | return; | |
7189 | ||
3b8b57a9 | 7190 | default: |
252b5132 | 7191 | break; |
3b8b57a9 | 7192 | } |
252b5132 | 7193 | |
3b8b57a9 AM |
7194 | #ifdef OBJ_ELF |
7195 | /* powerpc uses RELA style relocs, so if emitting a reloc the field | |
7196 | contents can stay at zero. */ | |
7197 | #define APPLY_RELOC fixP->fx_done | |
7198 | #else | |
7199 | #define APPLY_RELOC 1 | |
7200 | #endif | |
5663e321 AM |
7201 | /* We need to call the insert function even when fieldval is |
7202 | zero if the insert function would translate that zero to a | |
7203 | bit pattern other than all zeros. */ | |
3b8b57a9 AM |
7204 | if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL) |
7205 | { | |
5663e321 | 7206 | uint64_t insn; |
487b24d8 AM |
7207 | unsigned char *where; |
7208 | ||
3b8b57a9 AM |
7209 | /* Fetch the instruction, insert the fully resolved operand |
7210 | value, and stuff the instruction back again. */ | |
487b24d8 | 7211 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
3b8b57a9 | 7212 | if (target_big_endian) |
31a91399 | 7213 | { |
5663e321 | 7214 | if (fixP->fx_size < 4) |
487b24d8 | 7215 | insn = bfd_getb16 (where); |
5663e321 AM |
7216 | else |
7217 | { | |
7218 | insn = bfd_getb32 (where); | |
7219 | if (fixP->fx_size > 4) | |
7220 | insn = insn << 32 | bfd_getb32 (where + 4); | |
7221 | } | |
31a91399 NC |
7222 | } |
7223 | else | |
3b8b57a9 | 7224 | { |
5663e321 | 7225 | if (fixP->fx_size < 4) |
487b24d8 | 7226 | insn = bfd_getl16 (where); |
5663e321 AM |
7227 | else |
7228 | { | |
7229 | insn = bfd_getl32 (where); | |
7230 | if (fixP->fx_size > 4) | |
7231 | insn = insn << 32 | bfd_getl32 (where + 4); | |
7232 | } | |
3b8b57a9 AM |
7233 | } |
7234 | insn = ppc_insert_operand (insn, operand, fieldval, | |
7235 | fixP->tc_fix_data.ppc_cpu, | |
7236 | fixP->fx_file, fixP->fx_line); | |
7237 | if (target_big_endian) | |
7238 | { | |
5663e321 | 7239 | if (fixP->fx_size < 4) |
487b24d8 | 7240 | bfd_putb16 (insn, where); |
5663e321 AM |
7241 | else |
7242 | { | |
7243 | if (fixP->fx_size > 4) | |
7244 | { | |
7245 | bfd_putb32 (insn, where + 4); | |
7246 | insn >>= 32; | |
7247 | } | |
7248 | bfd_putb32 (insn, where); | |
7249 | } | |
3b8b57a9 AM |
7250 | } |
7251 | else | |
7252 | { | |
5663e321 | 7253 | if (fixP->fx_size < 4) |
487b24d8 | 7254 | bfd_putl16 (insn, where); |
5663e321 AM |
7255 | else |
7256 | { | |
7257 | if (fixP->fx_size > 4) | |
7258 | { | |
7259 | bfd_putl32 (insn, where + 4); | |
7260 | insn >>= 32; | |
7261 | } | |
7262 | bfd_putl32 (insn, where); | |
7263 | } | |
3b8b57a9 AM |
7264 | } |
7265 | } | |
7266 | ||
7267 | if (fixP->fx_done) | |
7268 | /* Nothing else to do here. */ | |
7269 | return; | |
7270 | ||
7271 | gas_assert (fixP->fx_addsy != NULL); | |
62ebcb5c | 7272 | if (fixP->fx_r_type == BFD_RELOC_NONE) |
3b8b57a9 | 7273 | { |
3b4dbbbf | 7274 | const char *sfile; |
3b8b57a9 AM |
7275 | unsigned int sline; |
7276 | ||
7277 | /* Use expr_symbol_where to see if this is an expression | |
7278 | symbol. */ | |
7279 | if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline)) | |
7280 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7281 | _("unresolved expression that must be resolved")); | |
7282 | else | |
7283 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7284 | _("unsupported relocation against %s"), | |
7285 | S_GET_NAME (fixP->fx_addsy)); | |
7286 | fixP->fx_done = 1; | |
7287 | return; | |
7288 | } | |
7289 | } | |
7290 | else | |
7291 | { | |
7292 | /* Handle relocs in data. */ | |
7293 | switch (fixP->fx_r_type) | |
7294 | { | |
252b5132 | 7295 | case BFD_RELOC_VTABLE_INHERIT: |
94f592af NC |
7296 | if (fixP->fx_addsy |
7297 | && !S_IS_DEFINED (fixP->fx_addsy) | |
7298 | && !S_IS_WEAK (fixP->fx_addsy)) | |
7299 | S_SET_WEAK (fixP->fx_addsy); | |
2b0f3761 | 7300 | /* Fallthru */ |
252b5132 RH |
7301 | |
7302 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af | 7303 | fixP->fx_done = 0; |
252b5132 RH |
7304 | break; |
7305 | ||
0baf16f2 | 7306 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7307 | /* These can appear with @l etc. in data. */ |
7308 | case BFD_RELOC_LO16: | |
3b8b57a9 | 7309 | case BFD_RELOC_LO16_PCREL: |
3b8b57a9 | 7310 | case BFD_RELOC_HI16: |
3b8b57a9 | 7311 | case BFD_RELOC_HI16_PCREL: |
3b8b57a9 | 7312 | case BFD_RELOC_HI16_S: |
3b8b57a9 | 7313 | case BFD_RELOC_HI16_S_PCREL: |
3b8b57a9 | 7314 | case BFD_RELOC_PPC64_HIGHER: |
3b8b57a9 | 7315 | case BFD_RELOC_PPC64_HIGHER_S: |
3b8b57a9 | 7316 | case BFD_RELOC_PPC64_HIGHEST: |
3b8b57a9 | 7317 | case BFD_RELOC_PPC64_HIGHEST_S: |
f9c6b907 AM |
7318 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7319 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
45965137 | 7320 | case BFD_RELOC_PPC64_ADDR64_LOCAL: |
3b8b57a9 AM |
7321 | break; |
7322 | ||
7323 | case BFD_RELOC_PPC_DTPMOD: | |
7324 | case BFD_RELOC_PPC_TPREL: | |
7325 | case BFD_RELOC_PPC_DTPREL: | |
7326 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7327 | break; | |
7328 | ||
7329 | /* Just punt all of these to the linker. */ | |
7330 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7331 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7332 | case BFD_RELOC_16_GOTOFF: | |
7333 | case BFD_RELOC_LO16_GOTOFF: | |
7334 | case BFD_RELOC_HI16_GOTOFF: | |
7335 | case BFD_RELOC_HI16_S_GOTOFF: | |
7336 | case BFD_RELOC_LO16_PLTOFF: | |
7337 | case BFD_RELOC_HI16_PLTOFF: | |
7338 | case BFD_RELOC_HI16_S_PLTOFF: | |
7339 | case BFD_RELOC_PPC_COPY: | |
7340 | case BFD_RELOC_PPC_GLOB_DAT: | |
7341 | case BFD_RELOC_16_BASEREL: | |
7342 | case BFD_RELOC_LO16_BASEREL: | |
7343 | case BFD_RELOC_HI16_BASEREL: | |
7344 | case BFD_RELOC_HI16_S_BASEREL: | |
7345 | case BFD_RELOC_PPC_TLS: | |
7346 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7347 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7348 | case BFD_RELOC_PPC_DTPREL16_HA: | |
7349 | case BFD_RELOC_PPC_TPREL16_LO: | |
7350 | case BFD_RELOC_PPC_TPREL16_HI: | |
7351 | case BFD_RELOC_PPC_TPREL16_HA: | |
7352 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
7353 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7354 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7355 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7356 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7357 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7358 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7359 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7360 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7361 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7362 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7363 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7364 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7365 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7366 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7367 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7368 | case BFD_RELOC_24_PLT_PCREL: | |
7369 | case BFD_RELOC_PPC_LOCAL24PC: | |
7370 | case BFD_RELOC_32_PLT_PCREL: | |
7371 | case BFD_RELOC_GPREL16: | |
7372 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7373 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7374 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7375 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7376 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7377 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7378 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7379 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7380 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7381 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
7382 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7383 | case BFD_RELOC_PPC_EMB_SDA21: | |
7384 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7385 | case BFD_RELOC_PPC_EMB_MRKREF: | |
7386 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7387 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7388 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7389 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7390 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7391 | case BFD_RELOC_PPC_EMB_RELSDA: | |
0baf16f2 | 7392 | case BFD_RELOC_PPC64_TOC: |
3b8b57a9 | 7393 | case BFD_RELOC_PPC_TOC16: |
4a403be0 CC |
7394 | case BFD_RELOC_PPC_TOC16_LO: |
7395 | case BFD_RELOC_PPC_TOC16_HI: | |
3b8b57a9 AM |
7396 | case BFD_RELOC_PPC64_TOC16_LO: |
7397 | case BFD_RELOC_PPC64_TOC16_HI: | |
7398 | case BFD_RELOC_PPC64_TOC16_HA: | |
f9c6b907 AM |
7399 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7400 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3b8b57a9 AM |
7401 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: |
7402 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7403 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7404 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
f9c6b907 AM |
7405 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7406 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3b8b57a9 AM |
7407 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7408 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7409 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7410 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
c213164a | 7411 | case BFD_RELOC_PPC64_TLS_PCREL: |
94f592af | 7412 | fixP->fx_done = 0; |
0baf16f2 | 7413 | break; |
0baf16f2 | 7414 | #endif |
3b8b57a9 AM |
7415 | |
7416 | #ifdef OBJ_XCOFF | |
1b2cb8e2 CC |
7417 | case BFD_RELOC_PPC_TLSGD: |
7418 | case BFD_RELOC_PPC_TLSLD: | |
7419 | case BFD_RELOC_PPC_TLSLE: | |
7420 | case BFD_RELOC_PPC_TLSIE: | |
7421 | case BFD_RELOC_PPC_TLSM: | |
7422 | case BFD_RELOC_PPC64_TLSGD: | |
7423 | case BFD_RELOC_PPC64_TLSLD: | |
7424 | case BFD_RELOC_PPC64_TLSLE: | |
7425 | case BFD_RELOC_PPC64_TLSIE: | |
7426 | case BFD_RELOC_PPC64_TLSM: | |
7427 | gas_assert (fixP->fx_addsy != NULL); | |
7428 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7429 | fieldval = 0; | |
7430 | break; | |
7431 | ||
7432 | /* TLSML relocations are targeting a XMC_TC symbol named | |
7433 | "_$TLSML". We can't check earlier because the relocation | |
7434 | can target any symbol name which will be latter .rename | |
7435 | to "_$TLSML". */ | |
7436 | case BFD_RELOC_PPC_TLSML: | |
7437 | case BFD_RELOC_PPC64_TLSML: | |
7438 | gas_assert (fixP->fx_addsy != NULL); | |
7439 | if (strcmp (symbol_get_tc (fixP->fx_addsy)->real_name, "_$TLSML") != 0) | |
7440 | { | |
7441 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7442 | _("R_TLSML relocation doesn't target a " | |
7443 | "symbol named \"_$TLSML\". %s"), S_GET_NAME(fixP->fx_addsy)); | |
7444 | } | |
7445 | fieldval = 0; | |
7446 | break; | |
7447 | ||
3b8b57a9 | 7448 | case BFD_RELOC_NONE: |
3b8b57a9 | 7449 | #endif |
5656a981 AM |
7450 | case BFD_RELOC_CTOR: |
7451 | case BFD_RELOC_32: | |
7452 | case BFD_RELOC_32_PCREL: | |
7453 | case BFD_RELOC_RVA: | |
7454 | case BFD_RELOC_64: | |
7455 | case BFD_RELOC_64_PCREL: | |
7456 | case BFD_RELOC_16: | |
7457 | case BFD_RELOC_16_PCREL: | |
7458 | case BFD_RELOC_8: | |
7459 | break; | |
3b8b57a9 | 7460 | |
252b5132 | 7461 | default: |
bc805888 | 7462 | fprintf (stderr, |
94f592af | 7463 | _("Gas failure, reloc value %d\n"), fixP->fx_r_type); |
99a814a1 | 7464 | fflush (stderr); |
252b5132 RH |
7465 | abort (); |
7466 | } | |
46b596ff | 7467 | |
5656a981 | 7468 | if (fixP->fx_size && APPLY_RELOC) |
46b596ff | 7469 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5656a981 | 7470 | fieldval, fixP->fx_size); |
bf7279d5 AM |
7471 | if (warn_476 |
7472 | && (seg->flags & SEC_CODE) != 0 | |
7473 | && fixP->fx_size == 4 | |
7474 | && fixP->fx_done | |
7475 | && !fixP->fx_tcbit | |
7476 | && (fixP->fx_r_type == BFD_RELOC_32 | |
7477 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
7478 | || fixP->fx_r_type == BFD_RELOC_32_PCREL)) | |
7479 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
7480 | _("data in executable section")); | |
5656a981 AM |
7481 | } |
7482 | ||
252b5132 | 7483 | #ifdef OBJ_ELF |
3b8b57a9 | 7484 | ppc_elf_validate_fix (fixP, seg); |
94f592af | 7485 | fixP->fx_addnumber = value; |
4e6935a6 AM |
7486 | |
7487 | /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately | |
7488 | from the section contents. If we are going to be emitting a reloc | |
7489 | then the section contents are immaterial, so don't warn if they | |
7490 | happen to overflow. Leave such warnings to ld. */ | |
7491 | if (!fixP->fx_done) | |
a38a07e0 AM |
7492 | { |
7493 | fixP->fx_no_overflow = 1; | |
7494 | ||
7495 | /* Arrange to emit .TOC. as a normal symbol if used in anything | |
7496 | but .TOC.@tocbase. */ | |
7497 | if (ppc_obj64 | |
7498 | && fixP->fx_r_type != BFD_RELOC_PPC64_TOC | |
7499 | && fixP->fx_addsy != NULL | |
7500 | && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0) | |
7501 | symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP; | |
7502 | } | |
252b5132 | 7503 | #else |
3478a63d CC |
7504 | if (fixP->fx_r_type == BFD_RELOC_PPC_TOC16 |
7505 | || fixP->fx_r_type == BFD_RELOC_PPC_TOC16_HI | |
7506 | || fixP->fx_r_type == BFD_RELOC_PPC_TOC16_LO) | |
252b5132 | 7507 | { |
8edcbfcd TG |
7508 | /* We want to use the offset within the toc, not the actual VMA |
7509 | of the symbol. */ | |
fd361982 AM |
7510 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) |
7511 | - S_GET_VALUE (ppc_toc_csect)); | |
4a403be0 CC |
7512 | |
7513 | /* The high bits must be adjusted for the low bits being signed. */ | |
7514 | if (fixP->fx_r_type == BFD_RELOC_PPC_TOC16_HI) { | |
7515 | fixP->fx_addnumber += 0x8000; | |
7516 | } | |
7517 | ||
ac21e7da TG |
7518 | /* Set *valP to avoid errors. */ |
7519 | *valP = value; | |
252b5132 | 7520 | } |
3478a63d CC |
7521 | else if (fixP->fx_r_type == BFD_RELOC_PPC_TLSM |
7522 | || fixP->fx_r_type == BFD_RELOC_PPC64_TLSM) | |
7523 | /* AIX ld expects the section contents for these relocations | |
7524 | to be zero. Arrange for that to occur when | |
7525 | bfd_install_relocation is called. */ | |
7526 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) | |
7527 | - S_GET_VALUE (fixP->fx_addsy)); | |
7528 | else | |
7529 | fixP->fx_addnumber = 0; | |
252b5132 | 7530 | #endif |
252b5132 RH |
7531 | } |
7532 | ||
7533 | /* Generate a reloc for a fixup. */ | |
7534 | ||
c5df7e44 | 7535 | arelent ** |
98027b10 | 7536 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 | 7537 | { |
c5df7e44 | 7538 | static arelent *relocs[3]; |
252b5132 RH |
7539 | arelent *reloc; |
7540 | ||
c5df7e44 CC |
7541 | relocs[0] = reloc = XNEW (arelent); |
7542 | relocs[1] = NULL; | |
252b5132 | 7543 | |
325801bd | 7544 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 7545 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 | 7546 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
c213164a AM |
7547 | /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */ |
7548 | if (fixp->fx_r_type == BFD_RELOC_PPC64_TLS_PCREL) | |
7549 | reloc->address++; | |
252b5132 RH |
7550 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
7551 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7552 | { | |
7553 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
99a814a1 AM |
7554 | _("reloc %d not supported by object file format"), |
7555 | (int) fixp->fx_r_type); | |
c5df7e44 | 7556 | relocs[0] = NULL; |
252b5132 RH |
7557 | } |
7558 | reloc->addend = fixp->fx_addnumber; | |
7559 | ||
4bf09429 | 7560 | if (fixp->fx_subsy != NULL) |
c5df7e44 CC |
7561 | { |
7562 | relocs[1] = reloc = XNEW (arelent); | |
7563 | relocs[2] = NULL; | |
7564 | ||
7565 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
7566 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_subsy); | |
7567 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
7568 | ||
7569 | reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_PPC_NEG); | |
7570 | reloc->addend = fixp->fx_addnumber; | |
7571 | ||
7572 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7573 | { | |
4bf09429 AM |
7574 | as_bad_subtract (fixp); |
7575 | free (relocs[1]->sym_ptr_ptr); | |
7576 | free (relocs[1]); | |
7577 | free (relocs[0]->sym_ptr_ptr); | |
7578 | free (relocs[0]); | |
c5df7e44 CC |
7579 | relocs[0] = NULL; |
7580 | } | |
7581 | } | |
7582 | ||
7583 | ||
7584 | return relocs; | |
252b5132 | 7585 | } |
75e21f08 JJ |
7586 | |
7587 | void | |
98027b10 | 7588 | ppc_cfi_frame_initial_instructions (void) |
75e21f08 JJ |
7589 | { |
7590 | cfi_add_CFA_def_cfa (1, 0); | |
7591 | } | |
7592 | ||
7593 | int | |
1df69f4f | 7594 | tc_ppc_regname_to_dw2regnum (char *regname) |
75e21f08 JJ |
7595 | { |
7596 | unsigned int regnum = -1; | |
7597 | unsigned int i; | |
7598 | const char *p; | |
7599 | char *q; | |
e0471c16 | 7600 | static struct { const char *name; int dw2regnum; } regnames[] = |
75e21f08 JJ |
7601 | { |
7602 | { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 }, | |
7603 | { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 }, | |
80f846b6 | 7604 | { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 }, |
75e21f08 JJ |
7605 | { "spe_acc", 111 }, { "spefscr", 112 } |
7606 | }; | |
7607 | ||
7608 | for (i = 0; i < ARRAY_SIZE (regnames); ++i) | |
7609 | if (strcmp (regnames[i].name, regname) == 0) | |
7610 | return regnames[i].dw2regnum; | |
7611 | ||
7612 | if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v') | |
7613 | { | |
7614 | p = regname + 1 + (regname[1] == '.'); | |
7615 | regnum = strtoul (p, &q, 10); | |
7616 | if (p == q || *q || regnum >= 32) | |
7617 | return -1; | |
7618 | if (regname[0] == 'f') | |
b7d7dc63 | 7619 | regnum += 32; |
75e21f08 | 7620 | else if (regname[0] == 'v') |
b7d7dc63 | 7621 | regnum += 77; |
75e21f08 JJ |
7622 | } |
7623 | else if (regname[0] == 'c' && regname[1] == 'r') | |
7624 | { | |
7625 | p = regname + 2 + (regname[2] == '.'); | |
7626 | if (p[0] < '0' || p[0] > '7' || p[1]) | |
b7d7dc63 | 7627 | return -1; |
75e21f08 JJ |
7628 | regnum = p[0] - '0' + 68; |
7629 | } | |
7630 | return regnum; | |
7631 | } |