]>
Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) |
250d07de | 2 | Copyright (C) 1994-2021 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support. |
4 | ||
5 | This file is part of GAS, the GNU Assembler. | |
6 | ||
7 | GAS is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 9 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
10 | any later version. |
11 | ||
12 | GAS is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
4b4da160 NC |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
20 | 02110-1301, USA. */ | |
252b5132 | 21 | |
252b5132 | 22 | #include "as.h" |
3882b010 | 23 | #include "safe-ctype.h" |
252b5132 | 24 | #include "subsegs.h" |
75e21f08 | 25 | #include "dw2gencfi.h" |
252b5132 RH |
26 | #include "opcode/ppc.h" |
27 | ||
28 | #ifdef OBJ_ELF | |
29 | #include "elf/ppc.h" | |
ee67d69a | 30 | #include "elf/ppc64.h" |
5d6f4f16 | 31 | #include "dwarf2dbg.h" |
252b5132 RH |
32 | #endif |
33 | ||
85645aed TG |
34 | #ifdef OBJ_XCOFF |
35 | #include "coff/xcoff.h" | |
36 | #include "libxcoff.h" | |
37 | #endif | |
38 | ||
252b5132 RH |
39 | /* This is the assembler for the PowerPC or POWER (RS/6000) chips. */ |
40 | ||
41 | /* Tell the main code what the endianness is. */ | |
42 | extern int target_big_endian; | |
43 | ||
44 | /* Whether or not, we've set target_big_endian. */ | |
45 | static int set_target_endian = 0; | |
46 | ||
47 | /* Whether to use user friendly register names. */ | |
48 | #ifndef TARGET_REG_NAMES_P | |
5b7c81bd | 49 | #define TARGET_REG_NAMES_P false |
252b5132 | 50 | #endif |
252b5132 | 51 | |
0baf16f2 AM |
52 | /* Macros for calculating LO, HI, HA, HIGHER, HIGHERA, HIGHEST, |
53 | HIGHESTA. */ | |
54 | ||
55 | /* #lo(value) denotes the least significant 16 bits of the indicated. */ | |
56 | #define PPC_LO(v) ((v) & 0xffff) | |
57 | ||
58 | /* #hi(value) denotes bits 16 through 31 of the indicated value. */ | |
59 | #define PPC_HI(v) (((v) >> 16) & 0xffff) | |
60 | ||
61 | /* #ha(value) denotes the high adjusted value: bits 16 through 31 of | |
62 | the indicated value, compensating for #lo() being treated as a | |
63 | signed number. */ | |
15c1449b | 64 | #define PPC_HA(v) PPC_HI ((v) + 0x8000) |
0baf16f2 AM |
65 | |
66 | /* #higher(value) denotes bits 32 through 47 of the indicated value. */ | |
2a98c3a6 | 67 | #define PPC_HIGHER(v) (((v) >> 16 >> 16) & 0xffff) |
0baf16f2 AM |
68 | |
69 | /* #highera(value) denotes bits 32 through 47 of the indicated value, | |
70 | compensating for #lo() being treated as a signed number. */ | |
15c1449b | 71 | #define PPC_HIGHERA(v) PPC_HIGHER ((v) + 0x8000) |
0baf16f2 AM |
72 | |
73 | /* #highest(value) denotes bits 48 through 63 of the indicated value. */ | |
2a98c3a6 | 74 | #define PPC_HIGHEST(v) (((v) >> 24 >> 24) & 0xffff) |
0baf16f2 AM |
75 | |
76 | /* #highesta(value) denotes bits 48 through 63 of the indicated value, | |
15c1449b AM |
77 | compensating for #lo being treated as a signed number. */ |
78 | #define PPC_HIGHESTA(v) PPC_HIGHEST ((v) + 0x8000) | |
0baf16f2 | 79 | |
f9c6b907 AM |
80 | #define SEX16(val) (((val) ^ 0x8000) - 0x8000) |
81 | ||
82 | /* For the time being on ppc64, don't report overflow on @h and @ha | |
83 | applied to constants. */ | |
84 | #define REPORT_OVERFLOW_HI 0 | |
0baf16f2 | 85 | |
5b7c81bd | 86 | static bool reg_names_p = TARGET_REG_NAMES_P; |
252b5132 | 87 | |
98027b10 AM |
88 | static void ppc_macro (char *, const struct powerpc_macro *); |
89 | static void ppc_byte (int); | |
0baf16f2 AM |
90 | |
91 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) | |
98027b10 AM |
92 | static void ppc_tc (int); |
93 | static void ppc_machine (int); | |
0baf16f2 | 94 | #endif |
252b5132 RH |
95 | |
96 | #ifdef OBJ_XCOFF | |
98027b10 AM |
97 | static void ppc_comm (int); |
98 | static void ppc_bb (int); | |
99 | static void ppc_bc (int); | |
100 | static void ppc_bf (int); | |
101 | static void ppc_biei (int); | |
102 | static void ppc_bs (int); | |
103 | static void ppc_eb (int); | |
104 | static void ppc_ec (int); | |
105 | static void ppc_ef (int); | |
106 | static void ppc_es (int); | |
107 | static void ppc_csect (int); | |
85645aed | 108 | static void ppc_dwsect (int); |
98027b10 AM |
109 | static void ppc_change_csect (symbolS *, offsetT); |
110 | static void ppc_function (int); | |
111 | static void ppc_extern (int); | |
112 | static void ppc_lglobl (int); | |
c865e45b | 113 | static void ppc_ref (int); |
98027b10 AM |
114 | static void ppc_section (int); |
115 | static void ppc_named_section (int); | |
116 | static void ppc_stabx (int); | |
117 | static void ppc_rename (int); | |
118 | static void ppc_toc (int); | |
119 | static void ppc_xcoff_cons (int); | |
120 | static void ppc_vbyte (int); | |
252b5132 RH |
121 | #endif |
122 | ||
123 | #ifdef OBJ_ELF | |
98027b10 AM |
124 | static void ppc_elf_rdata (int); |
125 | static void ppc_elf_lcomm (int); | |
6911b7dc | 126 | static void ppc_elf_localentry (int); |
ee67d69a | 127 | static void ppc_elf_abiversion (int); |
005d79fd | 128 | static void ppc_elf_gnu_attribute (int); |
252b5132 | 129 | #endif |
252b5132 RH |
130 | \f |
131 | /* Generic assembler global variables which must be defined by all | |
132 | targets. */ | |
133 | ||
134 | #ifdef OBJ_ELF | |
135 | /* This string holds the chars that always start a comment. If the | |
136 | pre-processor is disabled, these aren't very useful. The macro | |
137 | tc_comment_chars points to this. We use this, rather than the | |
138 | usual comment_chars, so that we can switch for Solaris conventions. */ | |
139 | static const char ppc_solaris_comment_chars[] = "#!"; | |
140 | static const char ppc_eabi_comment_chars[] = "#"; | |
141 | ||
142 | #ifdef TARGET_SOLARIS_COMMENT | |
143 | const char *ppc_comment_chars = ppc_solaris_comment_chars; | |
144 | #else | |
145 | const char *ppc_comment_chars = ppc_eabi_comment_chars; | |
146 | #endif | |
147 | #else | |
148 | const char comment_chars[] = "#"; | |
149 | #endif | |
150 | ||
151 | /* Characters which start a comment at the beginning of a line. */ | |
152 | const char line_comment_chars[] = "#"; | |
153 | ||
154 | /* Characters which may be used to separate multiple commands on a | |
155 | single line. */ | |
156 | const char line_separator_chars[] = ";"; | |
157 | ||
158 | /* Characters which are used to indicate an exponent in a floating | |
159 | point number. */ | |
160 | const char EXP_CHARS[] = "eE"; | |
161 | ||
162 | /* Characters which mean that a number is a floating point constant, | |
163 | as in 0d1.0. */ | |
164 | const char FLT_CHARS[] = "dD"; | |
5ce8663f | 165 | |
5e02f92e | 166 | /* Anything that can start an operand needs to be mentioned here, |
ac805826 | 167 | to stop the input scrubber eating whitespace. */ |
5e02f92e | 168 | const char ppc_symbol_chars[] = "%["; |
75e21f08 JJ |
169 | |
170 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ | |
171 | int ppc_cie_data_alignment; | |
783de163 | 172 | |
8fbf7334 JL |
173 | /* The dwarf2 minimum instruction length. */ |
174 | int ppc_dwarf2_line_min_insn_length; | |
175 | ||
cef4f754 AM |
176 | /* More than this number of nops in an alignment op gets a branch |
177 | instead. */ | |
178 | unsigned long nop_limit = 4; | |
179 | ||
783de163 AM |
180 | /* The type of processor we are assembling for. This is one or more |
181 | of the PPC_OPCODE flags defined in opcode/ppc.h. */ | |
fa452fa6 | 182 | ppc_cpu_t ppc_cpu = 0; |
776fc418 | 183 | ppc_cpu_t sticky = 0; |
01efc3af | 184 | |
ee67d69a AM |
185 | /* Value for ELF e_flags EF_PPC64_ABI. */ |
186 | unsigned int ppc_abiversion = 0; | |
187 | ||
05f7541e | 188 | #ifdef OBJ_ELF |
01efc3af | 189 | /* Flags set on encountering toc relocs. */ |
4f2a7b51 | 190 | static enum { |
01efc3af AM |
191 | has_large_toc_reloc = 1, |
192 | has_small_toc_reloc = 2 | |
193 | } toc_reloc_types; | |
05f7541e | 194 | #endif |
bf7279d5 AM |
195 | |
196 | /* Warn on emitting data to code sections. */ | |
197 | int warn_476; | |
0f873fd5 | 198 | uint64_t last_insn; |
bf7279d5 AM |
199 | segT last_seg; |
200 | subsegT last_subseg; | |
252b5132 RH |
201 | \f |
202 | /* The target specific pseudo-ops which we support. */ | |
203 | ||
204 | const pseudo_typeS md_pseudo_table[] = | |
205 | { | |
206 | /* Pseudo-ops which must be overridden. */ | |
207 | { "byte", ppc_byte, 0 }, | |
208 | ||
209 | #ifdef OBJ_XCOFF | |
210 | /* Pseudo-ops specific to the RS/6000 XCOFF format. Some of these | |
211 | legitimately belong in the obj-*.c file. However, XCOFF is based | |
212 | on COFF, and is only implemented for the RS/6000. We just use | |
213 | obj-coff.c, and add what we need here. */ | |
214 | { "comm", ppc_comm, 0 }, | |
215 | { "lcomm", ppc_comm, 1 }, | |
216 | { "bb", ppc_bb, 0 }, | |
217 | { "bc", ppc_bc, 0 }, | |
218 | { "bf", ppc_bf, 0 }, | |
219 | { "bi", ppc_biei, 0 }, | |
220 | { "bs", ppc_bs, 0 }, | |
221 | { "csect", ppc_csect, 0 }, | |
85645aed | 222 | { "dwsect", ppc_dwsect, 0 }, |
252b5132 RH |
223 | { "data", ppc_section, 'd' }, |
224 | { "eb", ppc_eb, 0 }, | |
225 | { "ec", ppc_ec, 0 }, | |
226 | { "ef", ppc_ef, 0 }, | |
227 | { "ei", ppc_biei, 1 }, | |
228 | { "es", ppc_es, 0 }, | |
229 | { "extern", ppc_extern, 0 }, | |
230 | { "function", ppc_function, 0 }, | |
231 | { "lglobl", ppc_lglobl, 0 }, | |
c865e45b | 232 | { "ref", ppc_ref, 0 }, |
252b5132 RH |
233 | { "rename", ppc_rename, 0 }, |
234 | { "section", ppc_named_section, 0 }, | |
235 | { "stabx", ppc_stabx, 0 }, | |
236 | { "text", ppc_section, 't' }, | |
237 | { "toc", ppc_toc, 0 }, | |
238 | { "long", ppc_xcoff_cons, 2 }, | |
7f6d05e8 | 239 | { "llong", ppc_xcoff_cons, 3 }, |
252b5132 RH |
240 | { "word", ppc_xcoff_cons, 1 }, |
241 | { "short", ppc_xcoff_cons, 1 }, | |
242 | { "vbyte", ppc_vbyte, 0 }, | |
243 | #endif | |
244 | ||
245 | #ifdef OBJ_ELF | |
62ebcb5c | 246 | { "llong", cons, 8 }, |
252b5132 RH |
247 | { "rdata", ppc_elf_rdata, 0 }, |
248 | { "rodata", ppc_elf_rdata, 0 }, | |
249 | { "lcomm", ppc_elf_lcomm, 0 }, | |
6911b7dc | 250 | { "localentry", ppc_elf_localentry, 0 }, |
ee67d69a | 251 | { "abiversion", ppc_elf_abiversion, 0 }, |
005d79fd | 252 | { "gnu_attribute", ppc_elf_gnu_attribute, 0}, |
252b5132 RH |
253 | #endif |
254 | ||
0baf16f2 | 255 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 | 256 | { "tc", ppc_tc, 0 }, |
0baf16f2 AM |
257 | { "machine", ppc_machine, 0 }, |
258 | #endif | |
252b5132 RH |
259 | |
260 | { NULL, NULL, 0 } | |
261 | }; | |
262 | ||
263 | \f | |
99a814a1 AM |
264 | /* Predefined register names if -mregnames (or default for Windows NT). |
265 | In general, there are lots of them, in an attempt to be compatible | |
266 | with a number of other Windows NT assemblers. */ | |
252b5132 RH |
267 | |
268 | /* Structure to hold information about predefined registers. */ | |
269 | struct pd_reg | |
270 | { | |
e0471c16 | 271 | const char *name; |
7e0de605 AM |
272 | unsigned short value; |
273 | unsigned short flags; | |
252b5132 RH |
274 | }; |
275 | ||
276 | /* List of registers that are pre-defined: | |
277 | ||
278 | Each general register has predefined names of the form: | |
279 | 1. r<reg_num> which has the value <reg_num>. | |
280 | 2. r.<reg_num> which has the value <reg_num>. | |
281 | ||
252b5132 RH |
282 | Each floating point register has predefined names of the form: |
283 | 1. f<reg_num> which has the value <reg_num>. | |
284 | 2. f.<reg_num> which has the value <reg_num>. | |
285 | ||
7a899fff C |
286 | Each vector unit register has predefined names of the form: |
287 | 1. v<reg_num> which has the value <reg_num>. | |
288 | 2. v.<reg_num> which has the value <reg_num>. | |
289 | ||
252b5132 RH |
290 | Each condition register has predefined names of the form: |
291 | 1. cr<reg_num> which has the value <reg_num>. | |
292 | 2. cr.<reg_num> which has the value <reg_num>. | |
293 | ||
294 | There are individual registers as well: | |
295 | sp or r.sp has the value 1 | |
296 | rtoc or r.toc has the value 2 | |
252b5132 RH |
297 | xer has the value 1 |
298 | lr has the value 8 | |
299 | ctr has the value 9 | |
252b5132 RH |
300 | dar has the value 19 |
301 | dsisr has the value 18 | |
302 | dec has the value 22 | |
303 | sdr1 has the value 25 | |
304 | srr0 has the value 26 | |
305 | srr1 has the value 27 | |
306 | ||
81d4177b | 307 | The table is sorted. Suitable for searching by a binary search. */ |
252b5132 RH |
308 | |
309 | static const struct pd_reg pre_defined_registers[] = | |
310 | { | |
aa3c112f AM |
311 | /* VSX accumulators. */ |
312 | { "a0", 0, PPC_OPERAND_ACC }, | |
313 | { "a1", 1, PPC_OPERAND_ACC }, | |
314 | { "a2", 2, PPC_OPERAND_ACC }, | |
315 | { "a3", 3, PPC_OPERAND_ACC }, | |
316 | { "a4", 4, PPC_OPERAND_ACC }, | |
317 | { "a5", 5, PPC_OPERAND_ACC }, | |
318 | { "a6", 6, PPC_OPERAND_ACC }, | |
319 | { "a7", 7, PPC_OPERAND_ACC }, | |
320 | ||
7e0de605 AM |
321 | /* Condition Registers */ |
322 | { "cr.0", 0, PPC_OPERAND_CR_REG }, | |
323 | { "cr.1", 1, PPC_OPERAND_CR_REG }, | |
324 | { "cr.2", 2, PPC_OPERAND_CR_REG }, | |
325 | { "cr.3", 3, PPC_OPERAND_CR_REG }, | |
326 | { "cr.4", 4, PPC_OPERAND_CR_REG }, | |
327 | { "cr.5", 5, PPC_OPERAND_CR_REG }, | |
328 | { "cr.6", 6, PPC_OPERAND_CR_REG }, | |
329 | { "cr.7", 7, PPC_OPERAND_CR_REG }, | |
330 | ||
331 | { "cr0", 0, PPC_OPERAND_CR_REG }, | |
332 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
333 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
334 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
335 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
336 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
337 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
338 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
339 | ||
340 | { "ctr", 9, PPC_OPERAND_SPR }, | |
341 | { "dar", 19, PPC_OPERAND_SPR }, | |
342 | { "dec", 22, PPC_OPERAND_SPR }, | |
343 | { "dsisr", 18, PPC_OPERAND_SPR }, | |
344 | ||
345 | /* Floating point registers */ | |
346 | { "f.0", 0, PPC_OPERAND_FPR }, | |
347 | { "f.1", 1, PPC_OPERAND_FPR }, | |
348 | { "f.10", 10, PPC_OPERAND_FPR }, | |
349 | { "f.11", 11, PPC_OPERAND_FPR }, | |
350 | { "f.12", 12, PPC_OPERAND_FPR }, | |
351 | { "f.13", 13, PPC_OPERAND_FPR }, | |
352 | { "f.14", 14, PPC_OPERAND_FPR }, | |
353 | { "f.15", 15, PPC_OPERAND_FPR }, | |
354 | { "f.16", 16, PPC_OPERAND_FPR }, | |
355 | { "f.17", 17, PPC_OPERAND_FPR }, | |
356 | { "f.18", 18, PPC_OPERAND_FPR }, | |
357 | { "f.19", 19, PPC_OPERAND_FPR }, | |
358 | { "f.2", 2, PPC_OPERAND_FPR }, | |
359 | { "f.20", 20, PPC_OPERAND_FPR }, | |
360 | { "f.21", 21, PPC_OPERAND_FPR }, | |
361 | { "f.22", 22, PPC_OPERAND_FPR }, | |
362 | { "f.23", 23, PPC_OPERAND_FPR }, | |
363 | { "f.24", 24, PPC_OPERAND_FPR }, | |
364 | { "f.25", 25, PPC_OPERAND_FPR }, | |
365 | { "f.26", 26, PPC_OPERAND_FPR }, | |
366 | { "f.27", 27, PPC_OPERAND_FPR }, | |
367 | { "f.28", 28, PPC_OPERAND_FPR }, | |
368 | { "f.29", 29, PPC_OPERAND_FPR }, | |
369 | { "f.3", 3, PPC_OPERAND_FPR }, | |
370 | { "f.30", 30, PPC_OPERAND_FPR }, | |
371 | { "f.31", 31, PPC_OPERAND_FPR }, | |
372 | { "f.32", 32, PPC_OPERAND_VSR }, | |
373 | { "f.33", 33, PPC_OPERAND_VSR }, | |
374 | { "f.34", 34, PPC_OPERAND_VSR }, | |
375 | { "f.35", 35, PPC_OPERAND_VSR }, | |
376 | { "f.36", 36, PPC_OPERAND_VSR }, | |
377 | { "f.37", 37, PPC_OPERAND_VSR }, | |
378 | { "f.38", 38, PPC_OPERAND_VSR }, | |
379 | { "f.39", 39, PPC_OPERAND_VSR }, | |
380 | { "f.4", 4, PPC_OPERAND_FPR }, | |
381 | { "f.40", 40, PPC_OPERAND_VSR }, | |
382 | { "f.41", 41, PPC_OPERAND_VSR }, | |
383 | { "f.42", 42, PPC_OPERAND_VSR }, | |
384 | { "f.43", 43, PPC_OPERAND_VSR }, | |
385 | { "f.44", 44, PPC_OPERAND_VSR }, | |
386 | { "f.45", 45, PPC_OPERAND_VSR }, | |
387 | { "f.46", 46, PPC_OPERAND_VSR }, | |
388 | { "f.47", 47, PPC_OPERAND_VSR }, | |
389 | { "f.48", 48, PPC_OPERAND_VSR }, | |
390 | { "f.49", 49, PPC_OPERAND_VSR }, | |
391 | { "f.5", 5, PPC_OPERAND_FPR }, | |
392 | { "f.50", 50, PPC_OPERAND_VSR }, | |
393 | { "f.51", 51, PPC_OPERAND_VSR }, | |
394 | { "f.52", 52, PPC_OPERAND_VSR }, | |
395 | { "f.53", 53, PPC_OPERAND_VSR }, | |
396 | { "f.54", 54, PPC_OPERAND_VSR }, | |
397 | { "f.55", 55, PPC_OPERAND_VSR }, | |
398 | { "f.56", 56, PPC_OPERAND_VSR }, | |
399 | { "f.57", 57, PPC_OPERAND_VSR }, | |
400 | { "f.58", 58, PPC_OPERAND_VSR }, | |
401 | { "f.59", 59, PPC_OPERAND_VSR }, | |
402 | { "f.6", 6, PPC_OPERAND_FPR }, | |
403 | { "f.60", 60, PPC_OPERAND_VSR }, | |
404 | { "f.61", 61, PPC_OPERAND_VSR }, | |
405 | { "f.62", 62, PPC_OPERAND_VSR }, | |
406 | { "f.63", 63, PPC_OPERAND_VSR }, | |
407 | { "f.7", 7, PPC_OPERAND_FPR }, | |
408 | { "f.8", 8, PPC_OPERAND_FPR }, | |
409 | { "f.9", 9, PPC_OPERAND_FPR }, | |
410 | ||
411 | { "f0", 0, PPC_OPERAND_FPR }, | |
412 | { "f1", 1, PPC_OPERAND_FPR }, | |
413 | { "f10", 10, PPC_OPERAND_FPR }, | |
414 | { "f11", 11, PPC_OPERAND_FPR }, | |
415 | { "f12", 12, PPC_OPERAND_FPR }, | |
416 | { "f13", 13, PPC_OPERAND_FPR }, | |
417 | { "f14", 14, PPC_OPERAND_FPR }, | |
418 | { "f15", 15, PPC_OPERAND_FPR }, | |
419 | { "f16", 16, PPC_OPERAND_FPR }, | |
420 | { "f17", 17, PPC_OPERAND_FPR }, | |
421 | { "f18", 18, PPC_OPERAND_FPR }, | |
422 | { "f19", 19, PPC_OPERAND_FPR }, | |
423 | { "f2", 2, PPC_OPERAND_FPR }, | |
424 | { "f20", 20, PPC_OPERAND_FPR }, | |
425 | { "f21", 21, PPC_OPERAND_FPR }, | |
426 | { "f22", 22, PPC_OPERAND_FPR }, | |
427 | { "f23", 23, PPC_OPERAND_FPR }, | |
428 | { "f24", 24, PPC_OPERAND_FPR }, | |
429 | { "f25", 25, PPC_OPERAND_FPR }, | |
430 | { "f26", 26, PPC_OPERAND_FPR }, | |
431 | { "f27", 27, PPC_OPERAND_FPR }, | |
432 | { "f28", 28, PPC_OPERAND_FPR }, | |
433 | { "f29", 29, PPC_OPERAND_FPR }, | |
434 | { "f3", 3, PPC_OPERAND_FPR }, | |
435 | { "f30", 30, PPC_OPERAND_FPR }, | |
436 | { "f31", 31, PPC_OPERAND_FPR }, | |
437 | { "f32", 32, PPC_OPERAND_VSR }, | |
438 | { "f33", 33, PPC_OPERAND_VSR }, | |
439 | { "f34", 34, PPC_OPERAND_VSR }, | |
440 | { "f35", 35, PPC_OPERAND_VSR }, | |
441 | { "f36", 36, PPC_OPERAND_VSR }, | |
442 | { "f37", 37, PPC_OPERAND_VSR }, | |
443 | { "f38", 38, PPC_OPERAND_VSR }, | |
444 | { "f39", 39, PPC_OPERAND_VSR }, | |
445 | { "f4", 4, PPC_OPERAND_FPR }, | |
446 | { "f40", 40, PPC_OPERAND_VSR }, | |
447 | { "f41", 41, PPC_OPERAND_VSR }, | |
448 | { "f42", 42, PPC_OPERAND_VSR }, | |
449 | { "f43", 43, PPC_OPERAND_VSR }, | |
450 | { "f44", 44, PPC_OPERAND_VSR }, | |
451 | { "f45", 45, PPC_OPERAND_VSR }, | |
452 | { "f46", 46, PPC_OPERAND_VSR }, | |
453 | { "f47", 47, PPC_OPERAND_VSR }, | |
454 | { "f48", 48, PPC_OPERAND_VSR }, | |
455 | { "f49", 49, PPC_OPERAND_VSR }, | |
456 | { "f5", 5, PPC_OPERAND_FPR }, | |
457 | { "f50", 50, PPC_OPERAND_VSR }, | |
458 | { "f51", 51, PPC_OPERAND_VSR }, | |
459 | { "f52", 52, PPC_OPERAND_VSR }, | |
460 | { "f53", 53, PPC_OPERAND_VSR }, | |
461 | { "f54", 54, PPC_OPERAND_VSR }, | |
462 | { "f55", 55, PPC_OPERAND_VSR }, | |
463 | { "f56", 56, PPC_OPERAND_VSR }, | |
464 | { "f57", 57, PPC_OPERAND_VSR }, | |
465 | { "f58", 58, PPC_OPERAND_VSR }, | |
466 | { "f59", 59, PPC_OPERAND_VSR }, | |
467 | { "f6", 6, PPC_OPERAND_FPR }, | |
468 | { "f60", 60, PPC_OPERAND_VSR }, | |
469 | { "f61", 61, PPC_OPERAND_VSR }, | |
470 | { "f62", 62, PPC_OPERAND_VSR }, | |
471 | { "f63", 63, PPC_OPERAND_VSR }, | |
472 | { "f7", 7, PPC_OPERAND_FPR }, | |
473 | { "f8", 8, PPC_OPERAND_FPR }, | |
474 | { "f9", 9, PPC_OPERAND_FPR }, | |
252b5132 | 475 | |
c3d65c1c | 476 | /* Quantization registers used with pair single instructions. */ |
7e0de605 AM |
477 | { "gqr.0", 0, PPC_OPERAND_GQR }, |
478 | { "gqr.1", 1, PPC_OPERAND_GQR }, | |
479 | { "gqr.2", 2, PPC_OPERAND_GQR }, | |
480 | { "gqr.3", 3, PPC_OPERAND_GQR }, | |
481 | { "gqr.4", 4, PPC_OPERAND_GQR }, | |
482 | { "gqr.5", 5, PPC_OPERAND_GQR }, | |
483 | { "gqr.6", 6, PPC_OPERAND_GQR }, | |
484 | { "gqr.7", 7, PPC_OPERAND_GQR }, | |
485 | { "gqr0", 0, PPC_OPERAND_GQR }, | |
486 | { "gqr1", 1, PPC_OPERAND_GQR }, | |
487 | { "gqr2", 2, PPC_OPERAND_GQR }, | |
488 | { "gqr3", 3, PPC_OPERAND_GQR }, | |
489 | { "gqr4", 4, PPC_OPERAND_GQR }, | |
490 | { "gqr5", 5, PPC_OPERAND_GQR }, | |
491 | { "gqr6", 6, PPC_OPERAND_GQR }, | |
492 | { "gqr7", 7, PPC_OPERAND_GQR }, | |
493 | ||
494 | { "lr", 8, PPC_OPERAND_SPR }, | |
495 | ||
496 | /* General Purpose Registers */ | |
497 | { "r.0", 0, PPC_OPERAND_GPR }, | |
498 | { "r.1", 1, PPC_OPERAND_GPR }, | |
499 | { "r.10", 10, PPC_OPERAND_GPR }, | |
500 | { "r.11", 11, PPC_OPERAND_GPR }, | |
501 | { "r.12", 12, PPC_OPERAND_GPR }, | |
502 | { "r.13", 13, PPC_OPERAND_GPR }, | |
503 | { "r.14", 14, PPC_OPERAND_GPR }, | |
504 | { "r.15", 15, PPC_OPERAND_GPR }, | |
505 | { "r.16", 16, PPC_OPERAND_GPR }, | |
506 | { "r.17", 17, PPC_OPERAND_GPR }, | |
507 | { "r.18", 18, PPC_OPERAND_GPR }, | |
508 | { "r.19", 19, PPC_OPERAND_GPR }, | |
509 | { "r.2", 2, PPC_OPERAND_GPR }, | |
510 | { "r.20", 20, PPC_OPERAND_GPR }, | |
511 | { "r.21", 21, PPC_OPERAND_GPR }, | |
512 | { "r.22", 22, PPC_OPERAND_GPR }, | |
513 | { "r.23", 23, PPC_OPERAND_GPR }, | |
514 | { "r.24", 24, PPC_OPERAND_GPR }, | |
515 | { "r.25", 25, PPC_OPERAND_GPR }, | |
516 | { "r.26", 26, PPC_OPERAND_GPR }, | |
517 | { "r.27", 27, PPC_OPERAND_GPR }, | |
518 | { "r.28", 28, PPC_OPERAND_GPR }, | |
519 | { "r.29", 29, PPC_OPERAND_GPR }, | |
520 | { "r.3", 3, PPC_OPERAND_GPR }, | |
521 | { "r.30", 30, PPC_OPERAND_GPR }, | |
522 | { "r.31", 31, PPC_OPERAND_GPR }, | |
523 | { "r.4", 4, PPC_OPERAND_GPR }, | |
524 | { "r.5", 5, PPC_OPERAND_GPR }, | |
525 | { "r.6", 6, PPC_OPERAND_GPR }, | |
526 | { "r.7", 7, PPC_OPERAND_GPR }, | |
527 | { "r.8", 8, PPC_OPERAND_GPR }, | |
528 | { "r.9", 9, PPC_OPERAND_GPR }, | |
529 | ||
530 | { "r.sp", 1, PPC_OPERAND_GPR }, | |
531 | ||
532 | { "r.toc", 2, PPC_OPERAND_GPR }, | |
533 | ||
534 | { "r0", 0, PPC_OPERAND_GPR }, | |
535 | { "r1", 1, PPC_OPERAND_GPR }, | |
536 | { "r10", 10, PPC_OPERAND_GPR }, | |
537 | { "r11", 11, PPC_OPERAND_GPR }, | |
538 | { "r12", 12, PPC_OPERAND_GPR }, | |
539 | { "r13", 13, PPC_OPERAND_GPR }, | |
540 | { "r14", 14, PPC_OPERAND_GPR }, | |
541 | { "r15", 15, PPC_OPERAND_GPR }, | |
542 | { "r16", 16, PPC_OPERAND_GPR }, | |
543 | { "r17", 17, PPC_OPERAND_GPR }, | |
544 | { "r18", 18, PPC_OPERAND_GPR }, | |
545 | { "r19", 19, PPC_OPERAND_GPR }, | |
546 | { "r2", 2, PPC_OPERAND_GPR }, | |
547 | { "r20", 20, PPC_OPERAND_GPR }, | |
548 | { "r21", 21, PPC_OPERAND_GPR }, | |
549 | { "r22", 22, PPC_OPERAND_GPR }, | |
550 | { "r23", 23, PPC_OPERAND_GPR }, | |
551 | { "r24", 24, PPC_OPERAND_GPR }, | |
552 | { "r25", 25, PPC_OPERAND_GPR }, | |
553 | { "r26", 26, PPC_OPERAND_GPR }, | |
554 | { "r27", 27, PPC_OPERAND_GPR }, | |
555 | { "r28", 28, PPC_OPERAND_GPR }, | |
556 | { "r29", 29, PPC_OPERAND_GPR }, | |
557 | { "r3", 3, PPC_OPERAND_GPR }, | |
558 | { "r30", 30, PPC_OPERAND_GPR }, | |
559 | { "r31", 31, PPC_OPERAND_GPR }, | |
560 | { "r4", 4, PPC_OPERAND_GPR }, | |
561 | { "r5", 5, PPC_OPERAND_GPR }, | |
562 | { "r6", 6, PPC_OPERAND_GPR }, | |
563 | { "r7", 7, PPC_OPERAND_GPR }, | |
564 | { "r8", 8, PPC_OPERAND_GPR }, | |
565 | { "r9", 9, PPC_OPERAND_GPR }, | |
566 | ||
567 | { "rtoc", 2, PPC_OPERAND_GPR }, | |
568 | ||
569 | { "sdr1", 25, PPC_OPERAND_SPR }, | |
570 | ||
571 | { "sp", 1, PPC_OPERAND_GPR }, | |
572 | ||
573 | { "srr0", 26, PPC_OPERAND_SPR }, | |
574 | { "srr1", 27, PPC_OPERAND_SPR }, | |
575 | ||
576 | /* Vector (Altivec/VMX) registers */ | |
577 | { "v.0", 0, PPC_OPERAND_VR }, | |
578 | { "v.1", 1, PPC_OPERAND_VR }, | |
579 | { "v.10", 10, PPC_OPERAND_VR }, | |
580 | { "v.11", 11, PPC_OPERAND_VR }, | |
581 | { "v.12", 12, PPC_OPERAND_VR }, | |
582 | { "v.13", 13, PPC_OPERAND_VR }, | |
583 | { "v.14", 14, PPC_OPERAND_VR }, | |
584 | { "v.15", 15, PPC_OPERAND_VR }, | |
585 | { "v.16", 16, PPC_OPERAND_VR }, | |
586 | { "v.17", 17, PPC_OPERAND_VR }, | |
587 | { "v.18", 18, PPC_OPERAND_VR }, | |
588 | { "v.19", 19, PPC_OPERAND_VR }, | |
589 | { "v.2", 2, PPC_OPERAND_VR }, | |
590 | { "v.20", 20, PPC_OPERAND_VR }, | |
591 | { "v.21", 21, PPC_OPERAND_VR }, | |
592 | { "v.22", 22, PPC_OPERAND_VR }, | |
593 | { "v.23", 23, PPC_OPERAND_VR }, | |
594 | { "v.24", 24, PPC_OPERAND_VR }, | |
595 | { "v.25", 25, PPC_OPERAND_VR }, | |
596 | { "v.26", 26, PPC_OPERAND_VR }, | |
597 | { "v.27", 27, PPC_OPERAND_VR }, | |
598 | { "v.28", 28, PPC_OPERAND_VR }, | |
599 | { "v.29", 29, PPC_OPERAND_VR }, | |
600 | { "v.3", 3, PPC_OPERAND_VR }, | |
601 | { "v.30", 30, PPC_OPERAND_VR }, | |
602 | { "v.31", 31, PPC_OPERAND_VR }, | |
603 | { "v.4", 4, PPC_OPERAND_VR }, | |
604 | { "v.5", 5, PPC_OPERAND_VR }, | |
605 | { "v.6", 6, PPC_OPERAND_VR }, | |
606 | { "v.7", 7, PPC_OPERAND_VR }, | |
607 | { "v.8", 8, PPC_OPERAND_VR }, | |
608 | { "v.9", 9, PPC_OPERAND_VR }, | |
609 | ||
610 | { "v0", 0, PPC_OPERAND_VR }, | |
611 | { "v1", 1, PPC_OPERAND_VR }, | |
612 | { "v10", 10, PPC_OPERAND_VR }, | |
613 | { "v11", 11, PPC_OPERAND_VR }, | |
614 | { "v12", 12, PPC_OPERAND_VR }, | |
615 | { "v13", 13, PPC_OPERAND_VR }, | |
616 | { "v14", 14, PPC_OPERAND_VR }, | |
617 | { "v15", 15, PPC_OPERAND_VR }, | |
618 | { "v16", 16, PPC_OPERAND_VR }, | |
619 | { "v17", 17, PPC_OPERAND_VR }, | |
620 | { "v18", 18, PPC_OPERAND_VR }, | |
621 | { "v19", 19, PPC_OPERAND_VR }, | |
622 | { "v2", 2, PPC_OPERAND_VR }, | |
623 | { "v20", 20, PPC_OPERAND_VR }, | |
624 | { "v21", 21, PPC_OPERAND_VR }, | |
625 | { "v22", 22, PPC_OPERAND_VR }, | |
626 | { "v23", 23, PPC_OPERAND_VR }, | |
627 | { "v24", 24, PPC_OPERAND_VR }, | |
628 | { "v25", 25, PPC_OPERAND_VR }, | |
629 | { "v26", 26, PPC_OPERAND_VR }, | |
630 | { "v27", 27, PPC_OPERAND_VR }, | |
631 | { "v28", 28, PPC_OPERAND_VR }, | |
632 | { "v29", 29, PPC_OPERAND_VR }, | |
633 | { "v3", 3, PPC_OPERAND_VR }, | |
634 | { "v30", 30, PPC_OPERAND_VR }, | |
635 | { "v31", 31, PPC_OPERAND_VR }, | |
636 | { "v4", 4, PPC_OPERAND_VR }, | |
637 | { "v5", 5, PPC_OPERAND_VR }, | |
638 | { "v6", 6, PPC_OPERAND_VR }, | |
639 | { "v7", 7, PPC_OPERAND_VR }, | |
640 | { "v8", 8, PPC_OPERAND_VR }, | |
641 | { "v9", 9, PPC_OPERAND_VR }, | |
642 | ||
643 | /* Vector Scalar (VSX) registers (ISA 2.06). */ | |
644 | { "vs.0", 0, PPC_OPERAND_VSR }, | |
645 | { "vs.1", 1, PPC_OPERAND_VSR }, | |
646 | { "vs.10", 10, PPC_OPERAND_VSR }, | |
647 | { "vs.11", 11, PPC_OPERAND_VSR }, | |
648 | { "vs.12", 12, PPC_OPERAND_VSR }, | |
649 | { "vs.13", 13, PPC_OPERAND_VSR }, | |
650 | { "vs.14", 14, PPC_OPERAND_VSR }, | |
651 | { "vs.15", 15, PPC_OPERAND_VSR }, | |
652 | { "vs.16", 16, PPC_OPERAND_VSR }, | |
653 | { "vs.17", 17, PPC_OPERAND_VSR }, | |
654 | { "vs.18", 18, PPC_OPERAND_VSR }, | |
655 | { "vs.19", 19, PPC_OPERAND_VSR }, | |
656 | { "vs.2", 2, PPC_OPERAND_VSR }, | |
657 | { "vs.20", 20, PPC_OPERAND_VSR }, | |
658 | { "vs.21", 21, PPC_OPERAND_VSR }, | |
659 | { "vs.22", 22, PPC_OPERAND_VSR }, | |
660 | { "vs.23", 23, PPC_OPERAND_VSR }, | |
661 | { "vs.24", 24, PPC_OPERAND_VSR }, | |
662 | { "vs.25", 25, PPC_OPERAND_VSR }, | |
663 | { "vs.26", 26, PPC_OPERAND_VSR }, | |
664 | { "vs.27", 27, PPC_OPERAND_VSR }, | |
665 | { "vs.28", 28, PPC_OPERAND_VSR }, | |
666 | { "vs.29", 29, PPC_OPERAND_VSR }, | |
667 | { "vs.3", 3, PPC_OPERAND_VSR }, | |
668 | { "vs.30", 30, PPC_OPERAND_VSR }, | |
669 | { "vs.31", 31, PPC_OPERAND_VSR }, | |
670 | { "vs.32", 32, PPC_OPERAND_VSR }, | |
671 | { "vs.33", 33, PPC_OPERAND_VSR }, | |
672 | { "vs.34", 34, PPC_OPERAND_VSR }, | |
673 | { "vs.35", 35, PPC_OPERAND_VSR }, | |
674 | { "vs.36", 36, PPC_OPERAND_VSR }, | |
675 | { "vs.37", 37, PPC_OPERAND_VSR }, | |
676 | { "vs.38", 38, PPC_OPERAND_VSR }, | |
677 | { "vs.39", 39, PPC_OPERAND_VSR }, | |
678 | { "vs.4", 4, PPC_OPERAND_VSR }, | |
679 | { "vs.40", 40, PPC_OPERAND_VSR }, | |
680 | { "vs.41", 41, PPC_OPERAND_VSR }, | |
681 | { "vs.42", 42, PPC_OPERAND_VSR }, | |
682 | { "vs.43", 43, PPC_OPERAND_VSR }, | |
683 | { "vs.44", 44, PPC_OPERAND_VSR }, | |
684 | { "vs.45", 45, PPC_OPERAND_VSR }, | |
685 | { "vs.46", 46, PPC_OPERAND_VSR }, | |
686 | { "vs.47", 47, PPC_OPERAND_VSR }, | |
687 | { "vs.48", 48, PPC_OPERAND_VSR }, | |
688 | { "vs.49", 49, PPC_OPERAND_VSR }, | |
689 | { "vs.5", 5, PPC_OPERAND_VSR }, | |
690 | { "vs.50", 50, PPC_OPERAND_VSR }, | |
691 | { "vs.51", 51, PPC_OPERAND_VSR }, | |
692 | { "vs.52", 52, PPC_OPERAND_VSR }, | |
693 | { "vs.53", 53, PPC_OPERAND_VSR }, | |
694 | { "vs.54", 54, PPC_OPERAND_VSR }, | |
695 | { "vs.55", 55, PPC_OPERAND_VSR }, | |
696 | { "vs.56", 56, PPC_OPERAND_VSR }, | |
697 | { "vs.57", 57, PPC_OPERAND_VSR }, | |
698 | { "vs.58", 58, PPC_OPERAND_VSR }, | |
699 | { "vs.59", 59, PPC_OPERAND_VSR }, | |
700 | { "vs.6", 6, PPC_OPERAND_VSR }, | |
701 | { "vs.60", 60, PPC_OPERAND_VSR }, | |
702 | { "vs.61", 61, PPC_OPERAND_VSR }, | |
703 | { "vs.62", 62, PPC_OPERAND_VSR }, | |
704 | { "vs.63", 63, PPC_OPERAND_VSR }, | |
705 | { "vs.7", 7, PPC_OPERAND_VSR }, | |
706 | { "vs.8", 8, PPC_OPERAND_VSR }, | |
707 | { "vs.9", 9, PPC_OPERAND_VSR }, | |
708 | ||
709 | { "vs0", 0, PPC_OPERAND_VSR }, | |
710 | { "vs1", 1, PPC_OPERAND_VSR }, | |
711 | { "vs10", 10, PPC_OPERAND_VSR }, | |
712 | { "vs11", 11, PPC_OPERAND_VSR }, | |
713 | { "vs12", 12, PPC_OPERAND_VSR }, | |
714 | { "vs13", 13, PPC_OPERAND_VSR }, | |
715 | { "vs14", 14, PPC_OPERAND_VSR }, | |
716 | { "vs15", 15, PPC_OPERAND_VSR }, | |
717 | { "vs16", 16, PPC_OPERAND_VSR }, | |
718 | { "vs17", 17, PPC_OPERAND_VSR }, | |
719 | { "vs18", 18, PPC_OPERAND_VSR }, | |
720 | { "vs19", 19, PPC_OPERAND_VSR }, | |
721 | { "vs2", 2, PPC_OPERAND_VSR }, | |
722 | { "vs20", 20, PPC_OPERAND_VSR }, | |
723 | { "vs21", 21, PPC_OPERAND_VSR }, | |
724 | { "vs22", 22, PPC_OPERAND_VSR }, | |
725 | { "vs23", 23, PPC_OPERAND_VSR }, | |
726 | { "vs24", 24, PPC_OPERAND_VSR }, | |
727 | { "vs25", 25, PPC_OPERAND_VSR }, | |
728 | { "vs26", 26, PPC_OPERAND_VSR }, | |
729 | { "vs27", 27, PPC_OPERAND_VSR }, | |
730 | { "vs28", 28, PPC_OPERAND_VSR }, | |
731 | { "vs29", 29, PPC_OPERAND_VSR }, | |
732 | { "vs3", 3, PPC_OPERAND_VSR }, | |
733 | { "vs30", 30, PPC_OPERAND_VSR }, | |
734 | { "vs31", 31, PPC_OPERAND_VSR }, | |
735 | { "vs32", 32, PPC_OPERAND_VSR }, | |
736 | { "vs33", 33, PPC_OPERAND_VSR }, | |
737 | { "vs34", 34, PPC_OPERAND_VSR }, | |
738 | { "vs35", 35, PPC_OPERAND_VSR }, | |
739 | { "vs36", 36, PPC_OPERAND_VSR }, | |
740 | { "vs37", 37, PPC_OPERAND_VSR }, | |
741 | { "vs38", 38, PPC_OPERAND_VSR }, | |
742 | { "vs39", 39, PPC_OPERAND_VSR }, | |
743 | { "vs4", 4, PPC_OPERAND_VSR }, | |
744 | { "vs40", 40, PPC_OPERAND_VSR }, | |
745 | { "vs41", 41, PPC_OPERAND_VSR }, | |
746 | { "vs42", 42, PPC_OPERAND_VSR }, | |
747 | { "vs43", 43, PPC_OPERAND_VSR }, | |
748 | { "vs44", 44, PPC_OPERAND_VSR }, | |
749 | { "vs45", 45, PPC_OPERAND_VSR }, | |
750 | { "vs46", 46, PPC_OPERAND_VSR }, | |
751 | { "vs47", 47, PPC_OPERAND_VSR }, | |
752 | { "vs48", 48, PPC_OPERAND_VSR }, | |
753 | { "vs49", 49, PPC_OPERAND_VSR }, | |
754 | { "vs5", 5, PPC_OPERAND_VSR }, | |
755 | { "vs50", 50, PPC_OPERAND_VSR }, | |
756 | { "vs51", 51, PPC_OPERAND_VSR }, | |
757 | { "vs52", 52, PPC_OPERAND_VSR }, | |
758 | { "vs53", 53, PPC_OPERAND_VSR }, | |
759 | { "vs54", 54, PPC_OPERAND_VSR }, | |
760 | { "vs55", 55, PPC_OPERAND_VSR }, | |
761 | { "vs56", 56, PPC_OPERAND_VSR }, | |
762 | { "vs57", 57, PPC_OPERAND_VSR }, | |
763 | { "vs58", 58, PPC_OPERAND_VSR }, | |
764 | { "vs59", 59, PPC_OPERAND_VSR }, | |
765 | { "vs6", 6, PPC_OPERAND_VSR }, | |
766 | { "vs60", 60, PPC_OPERAND_VSR }, | |
767 | { "vs61", 61, PPC_OPERAND_VSR }, | |
768 | { "vs62", 62, PPC_OPERAND_VSR }, | |
769 | { "vs63", 63, PPC_OPERAND_VSR }, | |
770 | { "vs7", 7, PPC_OPERAND_VSR }, | |
771 | { "vs8", 8, PPC_OPERAND_VSR }, | |
772 | { "vs9", 9, PPC_OPERAND_VSR }, | |
773 | ||
774 | { "xer", 1, PPC_OPERAND_SPR } | |
252b5132 RH |
775 | }; |
776 | ||
bc805888 | 777 | #define REG_NAME_CNT (sizeof (pre_defined_registers) / sizeof (struct pd_reg)) |
252b5132 RH |
778 | |
779 | /* Given NAME, find the register number associated with that name, return | |
780 | the integer value associated with the given name or -1 on failure. */ | |
781 | ||
7e0de605 | 782 | static const struct pd_reg * |
98027b10 | 783 | reg_name_search (const struct pd_reg *regs, int regcount, const char *name) |
252b5132 RH |
784 | { |
785 | int middle, low, high; | |
786 | int cmp; | |
787 | ||
788 | low = 0; | |
789 | high = regcount - 1; | |
790 | ||
791 | do | |
792 | { | |
793 | middle = (low + high) / 2; | |
794 | cmp = strcasecmp (name, regs[middle].name); | |
795 | if (cmp < 0) | |
796 | high = middle - 1; | |
797 | else if (cmp > 0) | |
798 | low = middle + 1; | |
799 | else | |
7e0de605 | 800 | return ®s[middle]; |
252b5132 RH |
801 | } |
802 | while (low <= high); | |
803 | ||
7e0de605 | 804 | return NULL; |
252b5132 RH |
805 | } |
806 | ||
807 | /* | |
99a814a1 | 808 | * Summary of register_name. |
252b5132 RH |
809 | * |
810 | * in: Input_line_pointer points to 1st char of operand. | |
811 | * | |
812 | * out: A expressionS. | |
813 | * The operand may have been a register: in this case, X_op == O_register, | |
814 | * X_add_number is set to the register number, and truth is returned. | |
815 | * Input_line_pointer->(next non-blank) char after operand, or is in its | |
816 | * original state. | |
817 | */ | |
818 | ||
5b7c81bd | 819 | static bool |
98027b10 | 820 | register_name (expressionS *expressionP) |
252b5132 | 821 | { |
7e0de605 | 822 | const struct pd_reg *reg; |
252b5132 RH |
823 | char *name; |
824 | char *start; | |
825 | char c; | |
826 | ||
99a814a1 | 827 | /* Find the spelling of the operand. */ |
252b5132 | 828 | start = name = input_line_pointer; |
3882b010 | 829 | if (name[0] == '%' && ISALPHA (name[1])) |
252b5132 RH |
830 | name = ++input_line_pointer; |
831 | ||
3882b010 | 832 | else if (!reg_names_p || !ISALPHA (name[0])) |
5b7c81bd | 833 | return false; |
252b5132 | 834 | |
d02603dc | 835 | c = get_symbol_name (&name); |
7e0de605 | 836 | reg = reg_name_search (pre_defined_registers, REG_NAME_CNT, name); |
252b5132 | 837 | |
468cced8 AM |
838 | /* Put back the delimiting char. */ |
839 | *input_line_pointer = c; | |
840 | ||
99a814a1 | 841 | /* Look to see if it's in the register table. */ |
7e0de605 | 842 | if (reg != NULL) |
252b5132 RH |
843 | { |
844 | expressionP->X_op = O_register; | |
7e0de605 AM |
845 | expressionP->X_add_number = reg->value; |
846 | expressionP->X_md = reg->flags; | |
81d4177b | 847 | |
99a814a1 | 848 | /* Make the rest nice. */ |
252b5132 RH |
849 | expressionP->X_add_symbol = NULL; |
850 | expressionP->X_op_symbol = NULL; | |
5b7c81bd | 851 | return true; |
252b5132 | 852 | } |
468cced8 AM |
853 | |
854 | /* Reset the line as if we had not done anything. */ | |
855 | input_line_pointer = start; | |
5b7c81bd | 856 | return false; |
252b5132 RH |
857 | } |
858 | \f | |
859 | /* This function is called for each symbol seen in an expression. It | |
860 | handles the special parsing which PowerPC assemblers are supposed | |
861 | to use for condition codes. */ | |
862 | ||
863 | /* Whether to do the special parsing. */ | |
5b7c81bd | 864 | static bool cr_operand; |
252b5132 RH |
865 | |
866 | /* Names to recognize in a condition code. This table is sorted. */ | |
867 | static const struct pd_reg cr_names[] = | |
868 | { | |
7e0de605 AM |
869 | { "cr0", 0, PPC_OPERAND_CR_REG }, |
870 | { "cr1", 1, PPC_OPERAND_CR_REG }, | |
871 | { "cr2", 2, PPC_OPERAND_CR_REG }, | |
872 | { "cr3", 3, PPC_OPERAND_CR_REG }, | |
873 | { "cr4", 4, PPC_OPERAND_CR_REG }, | |
874 | { "cr5", 5, PPC_OPERAND_CR_REG }, | |
875 | { "cr6", 6, PPC_OPERAND_CR_REG }, | |
876 | { "cr7", 7, PPC_OPERAND_CR_REG }, | |
877 | { "eq", 2, PPC_OPERAND_CR_BIT }, | |
878 | { "gt", 1, PPC_OPERAND_CR_BIT }, | |
879 | { "lt", 0, PPC_OPERAND_CR_BIT }, | |
880 | { "so", 3, PPC_OPERAND_CR_BIT }, | |
881 | { "un", 3, PPC_OPERAND_CR_BIT } | |
252b5132 RH |
882 | }; |
883 | ||
884 | /* Parsing function. This returns non-zero if it recognized an | |
885 | expression. */ | |
886 | ||
887 | int | |
91d6fa6a | 888 | ppc_parse_name (const char *name, expressionS *exp) |
252b5132 | 889 | { |
7e0de605 | 890 | const struct pd_reg *reg; |
252b5132 RH |
891 | |
892 | if (! cr_operand) | |
893 | return 0; | |
894 | ||
13abbae3 AM |
895 | if (*name == '%') |
896 | ++name; | |
7e0de605 | 897 | reg = reg_name_search (cr_names, sizeof cr_names / sizeof cr_names[0], |
252b5132 | 898 | name); |
7e0de605 | 899 | if (reg == NULL) |
252b5132 RH |
900 | return 0; |
901 | ||
7e0de605 AM |
902 | exp->X_op = O_register; |
903 | exp->X_add_number = reg->value; | |
904 | exp->X_md = reg->flags; | |
252b5132 RH |
905 | |
906 | return 1; | |
907 | } | |
7e0de605 AM |
908 | |
909 | /* Propagate X_md and check register expressions. This is to support | |
910 | condition codes like 4*cr5+eq. */ | |
911 | ||
912 | int | |
913 | ppc_optimize_expr (expressionS *left, operatorT op, expressionS *right) | |
914 | { | |
915 | /* Accept 4*cr<n> and cr<n>*4. */ | |
916 | if (op == O_multiply | |
917 | && ((right->X_op == O_register | |
918 | && right->X_md == PPC_OPERAND_CR_REG | |
919 | && left->X_op == O_constant | |
920 | && left->X_add_number == 4) | |
921 | || (left->X_op == O_register | |
922 | && left->X_md == PPC_OPERAND_CR_REG | |
923 | && right->X_op == O_constant | |
924 | && right->X_add_number == 4))) | |
925 | { | |
926 | left->X_op = O_register; | |
927 | left->X_md = PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT; | |
928 | left->X_add_number *= right->X_add_number; | |
929 | return 1; | |
930 | } | |
931 | ||
932 | /* Accept the above plus <cr bit>, and <cr bit> plus the above. */ | |
933 | if (right->X_op == O_register | |
934 | && left->X_op == O_register | |
935 | && op == O_add | |
936 | && ((right->X_md == PPC_OPERAND_CR_BIT | |
937 | && left->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT)) | |
938 | || (right->X_md == (PPC_OPERAND_CR_REG | PPC_OPERAND_CR_BIT) | |
939 | && left->X_md == PPC_OPERAND_CR_BIT))) | |
940 | { | |
941 | left->X_md = PPC_OPERAND_CR_BIT; | |
942 | right->X_op = O_constant; | |
943 | return 0; | |
944 | } | |
945 | ||
946 | /* Accept reg +/- constant. */ | |
947 | if (left->X_op == O_register | |
948 | && !((op == O_add || op == O_subtract) && right->X_op == O_constant)) | |
ece5dcc1 | 949 | as_warn (_("invalid register expression")); |
7e0de605 AM |
950 | |
951 | /* Accept constant + reg. */ | |
952 | if (right->X_op == O_register) | |
953 | { | |
954 | if (op == O_add && left->X_op == O_constant) | |
955 | left->X_md = right->X_md; | |
956 | else | |
ece5dcc1 | 957 | as_warn (_("invalid register expression")); |
7e0de605 AM |
958 | } |
959 | ||
960 | return 0; | |
961 | } | |
252b5132 RH |
962 | \f |
963 | /* Local variables. */ | |
964 | ||
2b3c4602 AM |
965 | /* Whether to target xcoff64/elf64. */ |
966 | static unsigned int ppc_obj64 = BFD_DEFAULT_TARGET_SIZE == 64; | |
7f6d05e8 | 967 | |
252b5132 | 968 | /* Opcode hash table. */ |
629310ab | 969 | static htab_t ppc_hash; |
252b5132 RH |
970 | |
971 | /* Macro hash table. */ | |
629310ab | 972 | static htab_t ppc_macro_hash; |
252b5132 RH |
973 | |
974 | #ifdef OBJ_ELF | |
99a814a1 | 975 | /* What type of shared library support to use. */ |
5d6f4f16 | 976 | static enum { SHLIB_NONE, SHLIB_PIC, SHLIB_MRELOCATABLE } shlib = SHLIB_NONE; |
252b5132 | 977 | |
99a814a1 | 978 | /* Flags to set in the elf header. */ |
252b5132 RH |
979 | static flagword ppc_flags = 0; |
980 | ||
981 | /* Whether this is Solaris or not. */ | |
982 | #ifdef TARGET_SOLARIS_COMMENT | |
5b7c81bd | 983 | #define SOLARIS_P true |
252b5132 | 984 | #else |
5b7c81bd | 985 | #define SOLARIS_P false |
252b5132 RH |
986 | #endif |
987 | ||
5b7c81bd | 988 | static bool msolaris = SOLARIS_P; |
252b5132 RH |
989 | #endif |
990 | ||
991 | #ifdef OBJ_XCOFF | |
992 | ||
993 | /* The RS/6000 assembler uses the .csect pseudo-op to generate code | |
994 | using a bunch of different sections. These assembler sections, | |
1b2cb8e2 CC |
995 | however, are all encompassed within the .text, .data or .bss sections |
996 | of the final output file. We handle this by using different | |
997 | subsegments within these main segments. | |
998 | .tdata and .tbss sections only have one type of csects for now, | |
999 | but it's better to follow the same construction like the others. */ | |
1000 | ||
1001 | struct ppc_xcoff_section ppc_xcoff_text_section; | |
1002 | struct ppc_xcoff_section ppc_xcoff_data_section; | |
1003 | struct ppc_xcoff_section ppc_xcoff_bss_section; | |
1004 | struct ppc_xcoff_section ppc_xcoff_tdata_section; | |
1005 | struct ppc_xcoff_section ppc_xcoff_tbss_section; | |
1006 | ||
1007 | /* Return true if the ppc_xcoff_section structure is already | |
1008 | initialized. */ | |
5b7c81bd | 1009 | static bool |
1b2cb8e2 CC |
1010 | ppc_xcoff_section_is_initialized (struct ppc_xcoff_section *section) |
1011 | { | |
1012 | return section->segment != NULL; | |
1013 | } | |
252b5132 | 1014 | |
1b2cb8e2 CC |
1015 | /* Initialize a ppc_xcoff_section. |
1016 | Dummy symbols are used to ensure the position of .text over .data | |
1017 | and .tdata. These symbols won't be output. */ | |
1018 | static void | |
1019 | ppc_init_xcoff_section (struct ppc_xcoff_section *s, segT seg, | |
5b7c81bd | 1020 | bool need_dummy) |
1b2cb8e2 CC |
1021 | { |
1022 | s->segment = seg; | |
1023 | s->next_subsegment = 2; | |
1024 | if (need_dummy) | |
1025 | { | |
1026 | s->csects = symbol_make ("dummy\001"); | |
1027 | symbol_get_tc (s->csects)->within = s->csects; | |
1028 | } | |
1029 | } | |
252b5132 RH |
1030 | |
1031 | /* The current csect. */ | |
1032 | static symbolS *ppc_current_csect; | |
1033 | ||
1034 | /* The RS/6000 assembler uses a TOC which holds addresses of functions | |
1035 | and variables. Symbols are put in the TOC with the .tc pseudo-op. | |
1036 | A special relocation is used when accessing TOC entries. We handle | |
1037 | the TOC as a subsegment within the .data segment. We set it up if | |
1038 | we see a .toc pseudo-op, and save the csect symbol here. */ | |
1039 | static symbolS *ppc_toc_csect; | |
1040 | ||
1041 | /* The first frag in the TOC subsegment. */ | |
1042 | static fragS *ppc_toc_frag; | |
1043 | ||
1044 | /* The first frag in the first subsegment after the TOC in the .data | |
1045 | segment. NULL if there are no subsegments after the TOC. */ | |
1046 | static fragS *ppc_after_toc_frag; | |
1047 | ||
1048 | /* The current static block. */ | |
1049 | static symbolS *ppc_current_block; | |
1050 | ||
1051 | /* The COFF debugging section; set by md_begin. This is not the | |
1052 | .debug section, but is instead the secret BFD section which will | |
1053 | cause BFD to set the section number of a symbol to N_DEBUG. */ | |
1054 | static asection *ppc_coff_debug_section; | |
1055 | ||
85645aed TG |
1056 | /* Structure to set the length field of the dwarf sections. */ |
1057 | struct dw_subsection { | |
1058 | /* Subsections are simply linked. */ | |
1059 | struct dw_subsection *link; | |
1060 | ||
1061 | /* The subsection number. */ | |
1062 | subsegT subseg; | |
1063 | ||
1064 | /* Expression to compute the length of the section. */ | |
1065 | expressionS end_exp; | |
1066 | }; | |
1067 | ||
1068 | static struct dw_section { | |
1069 | /* Corresponding section. */ | |
1070 | segT sect; | |
1071 | ||
1072 | /* Simply linked list of subsections with a label. */ | |
1073 | struct dw_subsection *list_subseg; | |
1074 | ||
1075 | /* The anonymous subsection. */ | |
1076 | struct dw_subsection *anon_subseg; | |
1077 | } dw_sections[XCOFF_DWSECT_NBR_NAMES]; | |
252b5132 RH |
1078 | #endif /* OBJ_XCOFF */ |
1079 | ||
252b5132 RH |
1080 | #ifdef OBJ_ELF |
1081 | symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE" */ | |
6a0c61b7 EZ |
1082 | unsigned long *ppc_apuinfo_list; |
1083 | unsigned int ppc_apuinfo_num; | |
1084 | unsigned int ppc_apuinfo_num_alloc; | |
252b5132 RH |
1085 | #endif /* OBJ_ELF */ |
1086 | \f | |
1087 | #ifdef OBJ_ELF | |
15c1449b | 1088 | const char *const md_shortopts = "b:l:usm:K:VQ:"; |
252b5132 | 1089 | #else |
15c1449b | 1090 | const char *const md_shortopts = "um:"; |
252b5132 | 1091 | #endif |
cef4f754 | 1092 | #define OPTION_NOPS (OPTION_MD_BASE + 0) |
15c1449b | 1093 | const struct option md_longopts[] = { |
cef4f754 | 1094 | {"nops", required_argument, NULL, OPTION_NOPS}, |
bf7279d5 AM |
1095 | {"ppc476-workaround", no_argument, &warn_476, 1}, |
1096 | {"no-ppc476-workaround", no_argument, &warn_476, 0}, | |
252b5132 RH |
1097 | {NULL, no_argument, NULL, 0} |
1098 | }; | |
15c1449b | 1099 | const size_t md_longopts_size = sizeof (md_longopts); |
252b5132 RH |
1100 | |
1101 | int | |
17b9d67d | 1102 | md_parse_option (int c, const char *arg) |
252b5132 | 1103 | { |
69fe9ce5 AM |
1104 | ppc_cpu_t new_cpu; |
1105 | ||
252b5132 RH |
1106 | switch (c) |
1107 | { | |
1108 | case 'u': | |
1109 | /* -u means that any undefined symbols should be treated as | |
1110 | external, which is the default for gas anyhow. */ | |
1111 | break; | |
1112 | ||
1113 | #ifdef OBJ_ELF | |
1114 | case 'l': | |
1115 | /* Solaris as takes -le (presumably for little endian). For completeness | |
99a814a1 | 1116 | sake, recognize -be also. */ |
252b5132 RH |
1117 | if (strcmp (arg, "e") == 0) |
1118 | { | |
1119 | target_big_endian = 0; | |
1120 | set_target_endian = 1; | |
b9c361e0 | 1121 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1122 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1123 | } |
1124 | else | |
1125 | return 0; | |
1126 | ||
1127 | break; | |
1128 | ||
1129 | case 'b': | |
1130 | if (strcmp (arg, "e") == 0) | |
1131 | { | |
1132 | target_big_endian = 1; | |
1133 | set_target_endian = 1; | |
1134 | } | |
1135 | else | |
1136 | return 0; | |
1137 | ||
1138 | break; | |
1139 | ||
1140 | case 'K': | |
99a814a1 | 1141 | /* Recognize -K PIC. */ |
252b5132 RH |
1142 | if (strcmp (arg, "PIC") == 0 || strcmp (arg, "pic") == 0) |
1143 | { | |
1144 | shlib = SHLIB_PIC; | |
1145 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; | |
1146 | } | |
1147 | else | |
1148 | return 0; | |
1149 | ||
1150 | break; | |
1151 | #endif | |
1152 | ||
7f6d05e8 CP |
1153 | /* a64 and a32 determine whether to use XCOFF64 or XCOFF32. */ |
1154 | case 'a': | |
1155 | if (strcmp (arg, "64") == 0) | |
2a98c3a6 AM |
1156 | { |
1157 | #ifdef BFD64 | |
1158 | ppc_obj64 = 1; | |
d6ed37ed AM |
1159 | if (ppc_cpu & PPC_OPCODE_VLE) |
1160 | as_bad (_("the use of -mvle requires -a32.")); | |
2a98c3a6 AM |
1161 | #else |
1162 | as_fatal (_("%s unsupported"), "-a64"); | |
1163 | #endif | |
1164 | } | |
7f6d05e8 | 1165 | else if (strcmp (arg, "32") == 0) |
2b3c4602 | 1166 | ppc_obj64 = 0; |
7f6d05e8 CP |
1167 | else |
1168 | return 0; | |
1169 | break; | |
81d4177b | 1170 | |
252b5132 | 1171 | case 'm': |
776fc418 | 1172 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, arg); |
52be03fd AM |
1173 | /* "raw" is only valid for the disassembler. */ |
1174 | if (new_cpu != 0 && (new_cpu & PPC_OPCODE_RAW) == 0) | |
b9c361e0 JL |
1175 | { |
1176 | ppc_cpu = new_cpu; | |
d6ed37ed AM |
1177 | if (strcmp (arg, "vle") == 0) |
1178 | { | |
1179 | if (set_target_endian && target_big_endian == 0) | |
1180 | as_bad (_("the use of -mvle requires big endian.")); | |
1181 | if (ppc_obj64) | |
1182 | as_bad (_("the use of -mvle requires -a32.")); | |
1183 | } | |
b9c361e0 | 1184 | } |
252b5132 | 1185 | |
83eef883 AFB |
1186 | else if (strcmp (arg, "no-vle") == 0) |
1187 | { | |
1188 | sticky &= ~PPC_OPCODE_VLE; | |
1189 | ||
1190 | new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, "booke"); | |
1191 | new_cpu &= ~PPC_OPCODE_VLE; | |
1192 | ||
1193 | ppc_cpu = new_cpu; | |
1194 | } | |
1195 | ||
252b5132 | 1196 | else if (strcmp (arg, "regnames") == 0) |
5b7c81bd | 1197 | reg_names_p = true; |
252b5132 RH |
1198 | |
1199 | else if (strcmp (arg, "no-regnames") == 0) | |
5b7c81bd | 1200 | reg_names_p = false; |
252b5132 RH |
1201 | |
1202 | #ifdef OBJ_ELF | |
99a814a1 AM |
1203 | /* -mrelocatable/-mrelocatable-lib -- warn about initializations |
1204 | that require relocation. */ | |
252b5132 RH |
1205 | else if (strcmp (arg, "relocatable") == 0) |
1206 | { | |
5d6f4f16 | 1207 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1208 | ppc_flags |= EF_PPC_RELOCATABLE; |
1209 | } | |
1210 | ||
1211 | else if (strcmp (arg, "relocatable-lib") == 0) | |
1212 | { | |
5d6f4f16 | 1213 | shlib = SHLIB_MRELOCATABLE; |
252b5132 RH |
1214 | ppc_flags |= EF_PPC_RELOCATABLE_LIB; |
1215 | } | |
1216 | ||
99a814a1 | 1217 | /* -memb, set embedded bit. */ |
252b5132 RH |
1218 | else if (strcmp (arg, "emb") == 0) |
1219 | ppc_flags |= EF_PPC_EMB; | |
1220 | ||
cc643b88 | 1221 | /* -mlittle/-mbig set the endianness. */ |
99a814a1 AM |
1222 | else if (strcmp (arg, "little") == 0 |
1223 | || strcmp (arg, "little-endian") == 0) | |
252b5132 RH |
1224 | { |
1225 | target_big_endian = 0; | |
1226 | set_target_endian = 1; | |
b9c361e0 | 1227 | if (ppc_cpu & PPC_OPCODE_VLE) |
d6ed37ed | 1228 | as_bad (_("the use of -mvle requires big endian.")); |
252b5132 RH |
1229 | } |
1230 | ||
1231 | else if (strcmp (arg, "big") == 0 || strcmp (arg, "big-endian") == 0) | |
1232 | { | |
1233 | target_big_endian = 1; | |
1234 | set_target_endian = 1; | |
1235 | } | |
1236 | ||
1237 | else if (strcmp (arg, "solaris") == 0) | |
1238 | { | |
5b7c81bd | 1239 | msolaris = true; |
252b5132 RH |
1240 | ppc_comment_chars = ppc_solaris_comment_chars; |
1241 | } | |
1242 | ||
1243 | else if (strcmp (arg, "no-solaris") == 0) | |
1244 | { | |
5b7c81bd | 1245 | msolaris = false; |
252b5132 RH |
1246 | ppc_comment_chars = ppc_eabi_comment_chars; |
1247 | } | |
74081948 AF |
1248 | else if (strcmp (arg, "spe2") == 0) |
1249 | { | |
1250 | ppc_cpu |= PPC_OPCODE_SPE2; | |
1251 | } | |
252b5132 RH |
1252 | #endif |
1253 | else | |
1254 | { | |
1255 | as_bad (_("invalid switch -m%s"), arg); | |
1256 | return 0; | |
1257 | } | |
1258 | break; | |
1259 | ||
1260 | #ifdef OBJ_ELF | |
1261 | /* -V: SVR4 argument to print version ID. */ | |
1262 | case 'V': | |
1263 | print_version_id (); | |
1264 | break; | |
1265 | ||
1266 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
1267 | should be emitted or not. FIXME: Not implemented. */ | |
1268 | case 'Q': | |
1269 | break; | |
1270 | ||
1271 | /* Solaris takes -s to specify that .stabs go in a .stabs section, | |
1272 | rather than .stabs.excl, which is ignored by the linker. | |
1273 | FIXME: Not implemented. */ | |
1274 | case 's': | |
1275 | if (arg) | |
1276 | return 0; | |
1277 | ||
1278 | break; | |
1279 | #endif | |
1280 | ||
cef4f754 AM |
1281 | case OPTION_NOPS: |
1282 | { | |
1283 | char *end; | |
1284 | nop_limit = strtoul (optarg, &end, 0); | |
1285 | if (*end) | |
1286 | as_bad (_("--nops needs a numeric argument")); | |
1287 | } | |
1288 | break; | |
85645aed | 1289 | |
bf7279d5 AM |
1290 | case 0: |
1291 | break; | |
1292 | ||
252b5132 RH |
1293 | default: |
1294 | return 0; | |
1295 | } | |
1296 | ||
1297 | return 1; | |
1298 | } | |
1299 | ||
5f63875b AM |
1300 | static int |
1301 | is_ppc64_target (const bfd_target *targ, void *data ATTRIBUTE_UNUSED) | |
1302 | { | |
1303 | switch (targ->flavour) | |
1304 | { | |
1305 | #ifdef OBJ_ELF | |
1306 | case bfd_target_elf_flavour: | |
d34049e8 | 1307 | return startswith (targ->name, "elf64-powerpc"); |
5f63875b AM |
1308 | #endif |
1309 | #ifdef OBJ_XCOFF | |
1310 | case bfd_target_xcoff_flavour: | |
1311 | return (strcmp (targ->name, "aixcoff64-rs6000") == 0 | |
1312 | || strcmp (targ->name, "aix5coff64-rs6000") == 0); | |
1313 | #endif | |
1314 | default: | |
1315 | return 0; | |
1316 | } | |
1317 | } | |
1318 | ||
252b5132 | 1319 | void |
98027b10 | 1320 | md_show_usage (FILE *stream) |
252b5132 | 1321 | { |
bc805888 | 1322 | fprintf (stream, _("\ |
5f63875b AM |
1323 | PowerPC options:\n")); |
1324 | fprintf (stream, _("\ | |
1325 | -a32 generate ELF32/XCOFF32\n")); | |
1326 | if (bfd_iterate_over_targets (is_ppc64_target, NULL)) | |
1327 | fprintf (stream, _("\ | |
1328 | -a64 generate ELF64/XCOFF64\n")); | |
1329 | fprintf (stream, _("\ | |
1330 | -u ignored\n")); | |
1331 | fprintf (stream, _("\ | |
1332 | -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2)\n")); | |
1333 | fprintf (stream, _("\ | |
1334 | -mpwr generate code for POWER (RIOS1)\n")); | |
1335 | fprintf (stream, _("\ | |
1336 | -m601 generate code for PowerPC 601\n")); | |
1337 | fprintf (stream, _("\ | |
418c1742 | 1338 | -mppc, -mppc32, -m603, -m604\n\ |
5f63875b AM |
1339 | generate code for PowerPC 603/604\n")); |
1340 | fprintf (stream, _("\ | |
1341 | -m403 generate code for PowerPC 403\n")); | |
1342 | fprintf (stream, _("\ | |
1343 | -m405 generate code for PowerPC 405\n")); | |
1344 | fprintf (stream, _("\ | |
1345 | -m440 generate code for PowerPC 440\n")); | |
1346 | fprintf (stream, _("\ | |
1347 | -m464 generate code for PowerPC 464\n")); | |
1348 | fprintf (stream, _("\ | |
1349 | -m476 generate code for PowerPC 476\n")); | |
1350 | fprintf (stream, _("\ | |
f5c120c5 | 1351 | -m7400, -m7410, -m7450, -m7455\n\ |
5f63875b AM |
1352 | generate code for PowerPC 7400/7410/7450/7455\n")); |
1353 | fprintf (stream, _("\ | |
fa758a70 | 1354 | -m750cl, -mgekko, -mbroadway\n\ |
5f63875b AM |
1355 | generate code for PowerPC 750cl/Gekko/Broadway\n")); |
1356 | fprintf (stream, _("\ | |
ef5a96d5 | 1357 | -m821, -m850, -m860 generate code for PowerPC 821/850/860\n")); |
df12615d | 1358 | fprintf (stream, _("\ |
5f63875b AM |
1359 | -mppc64, -m620 generate code for PowerPC 620/625/630\n")); |
1360 | fprintf (stream, _("\ | |
1361 | -mppc64bridge generate code for PowerPC 64, including bridge insns\n")); | |
1362 | fprintf (stream, _("\ | |
1363 | -mbooke generate code for 32-bit PowerPC BookE\n")); | |
1364 | fprintf (stream, _("\ | |
1365 | -ma2 generate code for A2 architecture\n")); | |
1366 | fprintf (stream, _("\ | |
1367 | -mpower4, -mpwr4 generate code for Power4 architecture\n")); | |
1368 | fprintf (stream, _("\ | |
cdc51b07 | 1369 | -mpower5, -mpwr5, -mpwr5x\n\ |
5f63875b AM |
1370 | generate code for Power5 architecture\n")); |
1371 | fprintf (stream, _("\ | |
1372 | -mpower6, -mpwr6 generate code for Power6 architecture\n")); | |
1373 | fprintf (stream, _("\ | |
1374 | -mpower7, -mpwr7 generate code for Power7 architecture\n")); | |
1375 | fprintf (stream, _("\ | |
1376 | -mpower8, -mpwr8 generate code for Power8 architecture\n")); | |
1377 | fprintf (stream, _("\ | |
1378 | -mpower9, -mpwr9 generate code for Power9 architecture\n")); | |
1379 | fprintf (stream, _("\ | |
1424c35d AM |
1380 | -mpower10, -mpwr10 generate code for Power10 architecture\n")); |
1381 | fprintf (stream, _("\ | |
5f63875b AM |
1382 | -mcell generate code for Cell Broadband Engine architecture\n")); |
1383 | fprintf (stream, _("\ | |
1384 | -mcom generate code for Power/PowerPC common instructions\n")); | |
1385 | fprintf (stream, _("\ | |
ce3d2015 | 1386 | -many generate code for any architecture (PWR/PWRX/PPC)\n")); |
6a0c61b7 | 1387 | fprintf (stream, _("\ |
5f63875b AM |
1388 | -maltivec generate code for AltiVec\n")); |
1389 | fprintf (stream, _("\ | |
1390 | -mvsx generate code for Vector-Scalar (VSX) instructions\n")); | |
1391 | fprintf (stream, _("\ | |
1392 | -me300 generate code for PowerPC e300 family\n")); | |
1393 | fprintf (stream, _("\ | |
1394 | -me500, -me500x2 generate code for Motorola e500 core complex\n")); | |
1395 | fprintf (stream, _("\ | |
1396 | -me500mc, generate code for Freescale e500mc core complex\n")); | |
1397 | fprintf (stream, _("\ | |
1398 | -me500mc64, generate code for Freescale e500mc64 core complex\n")); | |
1399 | fprintf (stream, _("\ | |
1400 | -me5500, generate code for Freescale e5500 core complex\n")); | |
1401 | fprintf (stream, _("\ | |
1402 | -me6500, generate code for Freescale e6500 core complex\n")); | |
1403 | fprintf (stream, _("\ | |
1404 | -mspe generate code for Motorola SPE instructions\n")); | |
1405 | fprintf (stream, _("\ | |
1406 | -mspe2 generate code for Freescale SPE2 instructions\n")); | |
1407 | fprintf (stream, _("\ | |
1408 | -mvle generate code for Freescale VLE instructions\n")); | |
1409 | fprintf (stream, _("\ | |
1410 | -mtitan generate code for AppliedMicro Titan core complex\n")); | |
1411 | fprintf (stream, _("\ | |
1412 | -mregnames Allow symbolic names for registers\n")); | |
1413 | fprintf (stream, _("\ | |
ce3d2015 | 1414 | -mno-regnames Do not allow symbolic names for registers\n")); |
252b5132 | 1415 | #ifdef OBJ_ELF |
bc805888 | 1416 | fprintf (stream, _("\ |
5f63875b AM |
1417 | -mrelocatable support for GCC's -mrelocatble option\n")); |
1418 | fprintf (stream, _("\ | |
1419 | -mrelocatable-lib support for GCC's -mrelocatble-lib option\n")); | |
1420 | fprintf (stream, _("\ | |
1421 | -memb set PPC_EMB bit in ELF flags\n")); | |
1422 | fprintf (stream, _("\ | |
b8b738ac | 1423 | -mlittle, -mlittle-endian, -le\n\ |
5f63875b AM |
1424 | generate code for a little endian machine\n")); |
1425 | fprintf (stream, _("\ | |
b8b738ac | 1426 | -mbig, -mbig-endian, -be\n\ |
5f63875b AM |
1427 | generate code for a big endian machine\n")); |
1428 | fprintf (stream, _("\ | |
1429 | -msolaris generate code for Solaris\n")); | |
1430 | fprintf (stream, _("\ | |
1431 | -mno-solaris do not generate code for Solaris\n")); | |
1432 | fprintf (stream, _("\ | |
1433 | -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags\n")); | |
1434 | fprintf (stream, _("\ | |
1435 | -V print assembler version number\n")); | |
1436 | fprintf (stream, _("\ | |
ce3d2015 | 1437 | -Qy, -Qn ignored\n")); |
252b5132 | 1438 | #endif |
cef4f754 | 1439 | fprintf (stream, _("\ |
5f63875b AM |
1440 | -nops=count when aligning, more than COUNT nops uses a branch\n")); |
1441 | fprintf (stream, _("\ | |
bf7279d5 | 1442 | -ppc476-workaround warn if emitting data to code sections\n")); |
252b5132 RH |
1443 | } |
1444 | \f | |
1445 | /* Set ppc_cpu if it is not already set. */ | |
1446 | ||
1447 | static void | |
98027b10 | 1448 | ppc_set_cpu (void) |
252b5132 RH |
1449 | { |
1450 | const char *default_os = TARGET_OS; | |
1451 | const char *default_cpu = TARGET_CPU; | |
1452 | ||
7102e95e | 1453 | if ((ppc_cpu & ~(ppc_cpu_t) PPC_OPCODE_ANY) == 0) |
252b5132 | 1454 | { |
2a98c3a6 | 1455 | if (ppc_obj64) |
f2ab4b42 PB |
1456 | if (target_big_endian) |
1457 | ppc_cpu |= PPC_OPCODE_PPC | PPC_OPCODE_64; | |
1458 | else | |
1459 | /* The minimum supported cpu for 64-bit little-endian is power8. */ | |
1460 | ppc_cpu |= ppc_parse_cpu (ppc_cpu, &sticky, "power8"); | |
d34049e8 | 1461 | else if (startswith (default_os, "aix") |
2a98c3a6 | 1462 | && default_os[3] >= '4' && default_os[3] <= '9') |
bdc70b4a | 1463 | ppc_cpu |= PPC_OPCODE_COMMON; |
d34049e8 | 1464 | else if (startswith (default_os, "aix3")) |
bdc70b4a | 1465 | ppc_cpu |= PPC_OPCODE_POWER; |
252b5132 | 1466 | else if (strcmp (default_cpu, "rs6000") == 0) |
bdc70b4a | 1467 | ppc_cpu |= PPC_OPCODE_POWER; |
d34049e8 | 1468 | else if (startswith (default_cpu, "powerpc")) |
bdc70b4a | 1469 | ppc_cpu |= PPC_OPCODE_PPC; |
252b5132 | 1470 | else |
d6ed37ed | 1471 | as_fatal (_("unknown default cpu = %s, os = %s"), |
99a814a1 | 1472 | default_cpu, default_os); |
252b5132 RH |
1473 | } |
1474 | } | |
1475 | ||
9232bbb0 AM |
1476 | /* Figure out the BFD architecture to use. This function and ppc_mach |
1477 | are called well before md_begin, when the output file is opened. */ | |
252b5132 RH |
1478 | |
1479 | enum bfd_architecture | |
98027b10 | 1480 | ppc_arch (void) |
252b5132 RH |
1481 | { |
1482 | const char *default_cpu = TARGET_CPU; | |
1483 | ppc_set_cpu (); | |
1484 | ||
1485 | if ((ppc_cpu & PPC_OPCODE_PPC) != 0) | |
1486 | return bfd_arch_powerpc; | |
b9c361e0 JL |
1487 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
1488 | return bfd_arch_powerpc; | |
1489 | if ((ppc_cpu & PPC_OPCODE_POWER) != 0) | |
252b5132 | 1490 | return bfd_arch_rs6000; |
b9c361e0 | 1491 | if ((ppc_cpu & (PPC_OPCODE_COMMON | PPC_OPCODE_ANY)) != 0) |
252b5132 RH |
1492 | { |
1493 | if (strcmp (default_cpu, "rs6000") == 0) | |
1494 | return bfd_arch_rs6000; | |
d34049e8 | 1495 | else if (startswith (default_cpu, "powerpc")) |
252b5132 RH |
1496 | return bfd_arch_powerpc; |
1497 | } | |
1498 | ||
d6ed37ed | 1499 | as_fatal (_("neither Power nor PowerPC opcodes were selected.")); |
252b5132 RH |
1500 | return bfd_arch_unknown; |
1501 | } | |
1502 | ||
7f6d05e8 | 1503 | unsigned long |
98027b10 | 1504 | ppc_mach (void) |
7f6d05e8 | 1505 | { |
2a98c3a6 AM |
1506 | if (ppc_obj64) |
1507 | return bfd_mach_ppc64; | |
1508 | else if (ppc_arch () == bfd_arch_rs6000) | |
1509 | return bfd_mach_rs6k; | |
ce3d2015 AM |
1510 | else if (ppc_cpu & PPC_OPCODE_TITAN) |
1511 | return bfd_mach_ppc_titan; | |
b9c361e0 JL |
1512 | else if (ppc_cpu & PPC_OPCODE_VLE) |
1513 | return bfd_mach_ppc_vle; | |
2a98c3a6 AM |
1514 | else |
1515 | return bfd_mach_ppc; | |
7f6d05e8 CP |
1516 | } |
1517 | ||
e0471c16 | 1518 | extern const char* |
98027b10 | 1519 | ppc_target_format (void) |
7f6d05e8 CP |
1520 | { |
1521 | #ifdef OBJ_COFF | |
fe49679d | 1522 | #if TE_POWERMAC |
0baf16f2 | 1523 | return "xcoff-powermac"; |
7f6d05e8 | 1524 | #else |
eb1e0e80 | 1525 | # ifdef TE_AIX5 |
edc1d652 | 1526 | return (ppc_obj64 ? "aix5coff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1527 | # else |
edc1d652 | 1528 | return (ppc_obj64 ? "aixcoff64-rs6000" : "aixcoff-rs6000"); |
eb1e0e80 | 1529 | # endif |
7f6d05e8 | 1530 | #endif |
7f6d05e8 CP |
1531 | #endif |
1532 | #ifdef OBJ_ELF | |
edc1d652 AM |
1533 | # ifdef TE_FreeBSD |
1534 | return (ppc_obj64 ? "elf64-powerpc-freebsd" : "elf32-powerpc-freebsd"); | |
1535 | # elif defined (TE_VXWORKS) | |
9d8504b1 PB |
1536 | return "elf32-powerpc-vxworks"; |
1537 | # else | |
0baf16f2 | 1538 | return (target_big_endian |
2b3c4602 AM |
1539 | ? (ppc_obj64 ? "elf64-powerpc" : "elf32-powerpc") |
1540 | : (ppc_obj64 ? "elf64-powerpcle" : "elf32-powerpcle")); | |
9d8504b1 | 1541 | # endif |
7f6d05e8 CP |
1542 | #endif |
1543 | } | |
1544 | ||
b9c361e0 JL |
1545 | /* Validate one entry in powerpc_opcodes[] or vle_opcodes[]. |
1546 | Return TRUE if there's a problem, otherwise FALSE. */ | |
1547 | ||
5b7c81bd | 1548 | static bool |
b9c361e0 JL |
1549 | insn_validate (const struct powerpc_opcode *op) |
1550 | { | |
1551 | const unsigned char *o; | |
0f873fd5 | 1552 | uint64_t omask = op->mask; |
b9c361e0 JL |
1553 | |
1554 | /* The mask had better not trim off opcode bits. */ | |
1555 | if ((op->opcode & omask) != op->opcode) | |
1556 | { | |
1557 | as_bad (_("mask trims opcode bits for %s"), op->name); | |
5b7c81bd | 1558 | return true; |
b9c361e0 JL |
1559 | } |
1560 | ||
1561 | /* The operands must not overlap the opcode or each other. */ | |
1562 | for (o = op->operands; *o; ++o) | |
1563 | { | |
5b7c81bd | 1564 | bool optional = false; |
b9c361e0 JL |
1565 | if (*o >= num_powerpc_operands) |
1566 | { | |
1567 | as_bad (_("operand index error for %s"), op->name); | |
5b7c81bd | 1568 | return true; |
b9c361e0 JL |
1569 | } |
1570 | else | |
1571 | { | |
71553718 | 1572 | uint64_t mask; |
b9c361e0 | 1573 | const struct powerpc_operand *operand = &powerpc_operands[*o]; |
71553718 | 1574 | if (operand->shift == (int) PPC_OPSHIFT_INV) |
b9c361e0 | 1575 | { |
71553718 | 1576 | const char *errmsg; |
32d71569 | 1577 | uint64_t val; |
71553718 AM |
1578 | |
1579 | errmsg = NULL; | |
1580 | val = -1; | |
1581 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
1582 | val = -val; | |
1583 | else if ((operand->flags & PPC_OPERAND_PLUS1) != 0) | |
1584 | val += 1; | |
1585 | mask = (*operand->insert) (0, val, ppc_cpu, &errmsg); | |
b9c361e0 | 1586 | } |
71553718 AM |
1587 | else if (operand->shift >= 0) |
1588 | mask = operand->bitm << operand->shift; | |
1589 | else | |
1590 | mask = operand->bitm >> -operand->shift; | |
1591 | if (omask & mask) | |
1592 | { | |
1593 | as_bad (_("operand %d overlap in %s"), | |
1594 | (int) (o - op->operands), op->name); | |
5b7c81bd | 1595 | return true; |
71553718 AM |
1596 | } |
1597 | omask |= mask; | |
2eac3da1 | 1598 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0) |
5b7c81bd | 1599 | optional = true; |
2eac3da1 AM |
1600 | else if (optional) |
1601 | { | |
1602 | as_bad (_("non-optional operand %d follows optional operand in %s"), | |
1603 | (int) (o - op->operands), op->name); | |
5b7c81bd | 1604 | return true; |
2eac3da1 | 1605 | } |
b9c361e0 JL |
1606 | } |
1607 | } | |
5b7c81bd | 1608 | return false; |
b9c361e0 JL |
1609 | } |
1610 | ||
69c040df | 1611 | /* Insert opcodes and macros into hash tables. Called at startup and |
1fe532cf | 1612 | for .machine pseudo. */ |
252b5132 | 1613 | |
69c040df AM |
1614 | static void |
1615 | ppc_setup_opcodes (void) | |
252b5132 | 1616 | { |
98027b10 | 1617 | const struct powerpc_opcode *op; |
252b5132 RH |
1618 | const struct powerpc_opcode *op_end; |
1619 | const struct powerpc_macro *macro; | |
1620 | const struct powerpc_macro *macro_end; | |
5b7c81bd | 1621 | bool bad_insn = false; |
252b5132 | 1622 | |
69c040df | 1623 | if (ppc_hash != NULL) |
629310ab | 1624 | htab_delete (ppc_hash); |
69c040df | 1625 | if (ppc_macro_hash != NULL) |
629310ab | 1626 | htab_delete (ppc_macro_hash); |
252b5132 RH |
1627 | |
1628 | /* Insert the opcodes into a hash table. */ | |
629310ab | 1629 | ppc_hash = str_htab_create (); |
252b5132 | 1630 | |
c43a438d | 1631 | if (ENABLE_CHECKING) |
b84bf58a | 1632 | { |
c43a438d | 1633 | unsigned int i; |
b84bf58a | 1634 | |
3b8b57a9 AM |
1635 | /* An index into powerpc_operands is stored in struct fix |
1636 | fx_pcrel_adjust which is 8 bits wide. */ | |
1637 | gas_assert (num_powerpc_operands < 256); | |
1638 | ||
c43a438d AM |
1639 | /* Check operand masks. Code here and in the disassembler assumes |
1640 | all the 1's in the mask are contiguous. */ | |
1641 | for (i = 0; i < num_powerpc_operands; ++i) | |
b84bf58a | 1642 | { |
0f873fd5 PB |
1643 | uint64_t mask = powerpc_operands[i].bitm; |
1644 | uint64_t right_bit; | |
c43a438d AM |
1645 | unsigned int j; |
1646 | ||
1647 | right_bit = mask & -mask; | |
1648 | mask += right_bit; | |
1649 | right_bit = mask & -mask; | |
1650 | if (mask != right_bit) | |
1651 | { | |
1652 | as_bad (_("powerpc_operands[%d].bitm invalid"), i); | |
5b7c81bd | 1653 | bad_insn = true; |
c43a438d AM |
1654 | } |
1655 | for (j = i + 1; j < num_powerpc_operands; ++j) | |
1656 | if (memcmp (&powerpc_operands[i], &powerpc_operands[j], | |
1657 | sizeof (powerpc_operands[0])) == 0) | |
1658 | { | |
1659 | as_bad (_("powerpc_operands[%d] duplicates powerpc_operands[%d]"), | |
1660 | j, i); | |
5b7c81bd | 1661 | bad_insn = true; |
c43a438d | 1662 | } |
b84bf58a AM |
1663 | } |
1664 | } | |
1665 | ||
252b5132 RH |
1666 | op_end = powerpc_opcodes + powerpc_num_opcodes; |
1667 | for (op = powerpc_opcodes; op < op_end; op++) | |
1668 | { | |
c43a438d | 1669 | if (ENABLE_CHECKING) |
b84bf58a | 1670 | { |
2ceb7719 | 1671 | unsigned int new_opcode = PPC_OP (op[0].opcode); |
b9c361e0 JL |
1672 | |
1673 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1674 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1675 | op->name, (unsigned int) (op - powerpc_opcodes), | |
1676 | new_opcode, (unsigned long long) op->opcode, | |
1677 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 JL |
1678 | #endif |
1679 | ||
2ceb7719 PB |
1680 | /* The major opcodes had better be sorted. Code in the disassembler |
1681 | assumes the insns are sorted according to major opcode. */ | |
1682 | if (op != powerpc_opcodes | |
1683 | && new_opcode < PPC_OP (op[-1].opcode)) | |
1684 | { | |
1685 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1686 | bad_insn = true; |
8dbcd839 | 1687 | } |
2ceb7719 | 1688 | |
14b57c7c AM |
1689 | if ((op->flags & PPC_OPCODE_VLE) != 0) |
1690 | { | |
1691 | as_bad (_("%s is enabled by vle flag"), op->name); | |
5b7c81bd | 1692 | bad_insn = true; |
14b57c7c AM |
1693 | } |
1694 | if (PPC_OP (op->opcode) != 4 | |
1695 | && PPC_OP (op->opcode) != 31 | |
1696 | && (op->deprecated & PPC_OPCODE_VLE) == 0) | |
1697 | { | |
1698 | as_bad (_("%s not disabled by vle flag"), op->name); | |
5b7c81bd | 1699 | bad_insn = true; |
14b57c7c | 1700 | } |
b9c361e0 JL |
1701 | bad_insn |= insn_validate (op); |
1702 | } | |
c43a438d | 1703 | |
b9c361e0 | 1704 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1705 | && !(ppc_cpu & op->deprecated) |
1706 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1707 | { | |
1708 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1709 | bad_insn = true; |
fe0e921f | 1710 | } |
b9c361e0 | 1711 | } |
c43a438d | 1712 | |
b9c361e0 JL |
1713 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) |
1714 | for (op = powerpc_opcodes; op < op_end; op++) | |
fe0e921f | 1715 | str_hash_insert (ppc_hash, op->name, op, 0); |
b9c361e0 | 1716 | |
dd7efa79 PB |
1717 | op_end = prefix_opcodes + prefix_num_opcodes; |
1718 | for (op = prefix_opcodes; op < op_end; op++) | |
1719 | { | |
1720 | if (ENABLE_CHECKING) | |
1721 | { | |
1722 | unsigned int new_opcode = PPC_PREFIX_SEG (op[0].opcode); | |
1723 | ||
1724 | #ifdef PRINT_OPCODE_TABLE | |
1725 | printf ("%-14s\t#%04u\tmajor op/2: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", | |
1726 | op->name, (unsigned int) (op - prefix_opcodes), | |
1727 | new_opcode, (unsigned long long) op->opcode, | |
1728 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
1729 | #endif | |
1730 | ||
1731 | /* The major opcodes had better be sorted. Code in the disassembler | |
1732 | assumes the insns are sorted according to major opcode. */ | |
1733 | if (op != prefix_opcodes | |
1734 | && new_opcode < PPC_PREFIX_SEG (op[-1].opcode)) | |
1735 | { | |
1736 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1737 | bad_insn = true; |
dd7efa79 PB |
1738 | } |
1739 | bad_insn |= insn_validate (op); | |
1740 | } | |
1741 | ||
1742 | if ((ppc_cpu & op->flags) != 0 | |
fe0e921f AM |
1743 | && !(ppc_cpu & op->deprecated) |
1744 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1745 | { | |
1746 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1747 | bad_insn = true; |
fe0e921f | 1748 | } |
dd7efa79 PB |
1749 | } |
1750 | ||
1751 | if ((ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1752 | for (op = prefix_opcodes; op < op_end; op++) | |
fe0e921f | 1753 | str_hash_insert (ppc_hash, op->name, op, 0); |
dd7efa79 | 1754 | |
b9c361e0 JL |
1755 | op_end = vle_opcodes + vle_num_opcodes; |
1756 | for (op = vle_opcodes; op < op_end; op++) | |
1757 | { | |
1758 | if (ENABLE_CHECKING) | |
1759 | { | |
2ceb7719 | 1760 | unsigned new_seg = VLE_OP_TO_SEG (VLE_OP (op[0].opcode, op[0].mask)); |
b9c361e0 JL |
1761 | |
1762 | #ifdef PRINT_OPCODE_TABLE | |
2ceb7719 PB |
1763 | printf ("%-14s\t#%04u\tmajor op: 0x%x\top: 0x%llx\tmask: 0x%llx\tflags: 0x%llx\n", |
1764 | op->name, (unsigned int) (op - vle_opcodes), | |
1765 | (unsigned int) new_seg, (unsigned long long) op->opcode, | |
1766 | (unsigned long long) op->mask, (unsigned long long) op->flags); | |
b9c361e0 | 1767 | #endif |
2ceb7719 PB |
1768 | |
1769 | /* The major opcodes had better be sorted. Code in the disassembler | |
1770 | assumes the insns are sorted according to major opcode. */ | |
1771 | if (op != vle_opcodes | |
1772 | && new_seg < VLE_OP_TO_SEG (VLE_OP (op[-1].opcode, op[-1].mask))) | |
1773 | { | |
1774 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1775 | bad_insn = true; |
b9c361e0 JL |
1776 | } |
1777 | ||
1778 | bad_insn |= insn_validate (op); | |
c43a438d | 1779 | } |
252b5132 | 1780 | |
bdc70b4a | 1781 | if ((ppc_cpu & op->flags) != 0 |
fe0e921f AM |
1782 | && !(ppc_cpu & op->deprecated) |
1783 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1784 | { | |
1785 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1786 | bad_insn = true; |
fe0e921f | 1787 | } |
252b5132 RH |
1788 | } |
1789 | ||
74081948 AF |
1790 | /* SPE2 instructions */ |
1791 | if ((ppc_cpu & PPC_OPCODE_SPE2) == PPC_OPCODE_SPE2) | |
1792 | { | |
1793 | op_end = spe2_opcodes + spe2_num_opcodes; | |
1794 | for (op = spe2_opcodes; op < op_end; op++) | |
1795 | { | |
1796 | if (ENABLE_CHECKING) | |
1797 | { | |
1798 | if (op != spe2_opcodes) | |
1799 | { | |
1800 | unsigned old_seg, new_seg; | |
1801 | ||
1802 | old_seg = VLE_OP (op[-1].opcode, op[-1].mask); | |
1803 | old_seg = VLE_OP_TO_SEG (old_seg); | |
1804 | new_seg = VLE_OP (op[0].opcode, op[0].mask); | |
1805 | new_seg = VLE_OP_TO_SEG (new_seg); | |
1806 | ||
1807 | /* The major opcodes had better be sorted. Code in the | |
1808 | disassembler assumes the insns are sorted according to | |
1809 | major opcode. */ | |
1810 | if (new_seg < old_seg) | |
1811 | { | |
1812 | as_bad (_("major opcode is not sorted for %s"), op->name); | |
5b7c81bd | 1813 | bad_insn = true; |
74081948 AF |
1814 | } |
1815 | } | |
1816 | ||
1817 | bad_insn |= insn_validate (op); | |
1818 | } | |
1819 | ||
fe0e921f AM |
1820 | if ((ppc_cpu & op->flags) != 0 |
1821 | && !(ppc_cpu & op->deprecated) | |
1822 | && str_hash_insert (ppc_hash, op->name, op, 0) != NULL) | |
1823 | { | |
1824 | as_bad (_("duplicate %s"), op->name); | |
5b7c81bd | 1825 | bad_insn = true; |
fe0e921f | 1826 | } |
74081948 AF |
1827 | } |
1828 | ||
1829 | for (op = spe2_opcodes; op < op_end; op++) | |
fe0e921f | 1830 | str_hash_insert (ppc_hash, op->name, op, 0); |
74081948 AF |
1831 | } |
1832 | ||
252b5132 | 1833 | /* Insert the macros into a hash table. */ |
629310ab | 1834 | ppc_macro_hash = str_htab_create (); |
252b5132 RH |
1835 | |
1836 | macro_end = powerpc_macros + powerpc_num_macros; | |
1837 | for (macro = powerpc_macros; macro < macro_end; macro++) | |
fe0e921f AM |
1838 | if (((macro->flags & ppc_cpu) != 0 |
1839 | || (ppc_cpu & PPC_OPCODE_ANY) != 0) | |
1840 | && str_hash_insert (ppc_macro_hash, macro->name, macro, 0) != NULL) | |
1841 | { | |
1842 | as_bad (_("duplicate %s"), macro->name); | |
5b7c81bd | 1843 | bad_insn = true; |
fe0e921f | 1844 | } |
252b5132 | 1845 | |
b84bf58a | 1846 | if (bad_insn) |
252b5132 | 1847 | abort (); |
69c040df AM |
1848 | } |
1849 | ||
1850 | /* This function is called when the assembler starts up. It is called | |
1851 | after the options have been parsed and the output file has been | |
1852 | opened. */ | |
1853 | ||
1854 | void | |
98027b10 | 1855 | md_begin (void) |
69c040df AM |
1856 | { |
1857 | ppc_set_cpu (); | |
1858 | ||
1859 | ppc_cie_data_alignment = ppc_obj64 ? -8 : -4; | |
8fbf7334 | 1860 | ppc_dwarf2_line_min_insn_length = (ppc_cpu & PPC_OPCODE_VLE) ? 2 : 4; |
69c040df AM |
1861 | |
1862 | #ifdef OBJ_ELF | |
1863 | /* Set the ELF flags if desired. */ | |
1864 | if (ppc_flags && !msolaris) | |
1865 | bfd_set_private_flags (stdoutput, ppc_flags); | |
1866 | #endif | |
1867 | ||
1868 | ppc_setup_opcodes (); | |
252b5132 | 1869 | |
67c1ffbe | 1870 | /* Tell the main code what the endianness is if it is not overridden |
99a814a1 | 1871 | by the user. */ |
252b5132 RH |
1872 | if (!set_target_endian) |
1873 | { | |
1874 | set_target_endian = 1; | |
1875 | target_big_endian = PPC_BIG_ENDIAN; | |
1876 | } | |
1877 | ||
1878 | #ifdef OBJ_XCOFF | |
1879 | ppc_coff_debug_section = coff_section_from_bfd_index (stdoutput, N_DEBUG); | |
1880 | ||
1b2cb8e2 CC |
1881 | /* Create XCOFF sections with .text in first, as it's creating dummy symbols |
1882 | to serve as initial csects. This forces the text csects to precede the | |
1883 | data csects. These symbols will not be output. */ | |
5b7c81bd AM |
1884 | ppc_init_xcoff_section (&ppc_xcoff_text_section, text_section, true); |
1885 | ppc_init_xcoff_section (&ppc_xcoff_data_section, data_section, true); | |
1886 | ppc_init_xcoff_section (&ppc_xcoff_bss_section, bss_section, false); | |
252b5132 | 1887 | #endif |
252b5132 RH |
1888 | } |
1889 | ||
6a0c61b7 | 1890 | void |
98027b10 | 1891 | ppc_cleanup (void) |
6a0c61b7 | 1892 | { |
dc1d03fc | 1893 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
1894 | if (ppc_apuinfo_list == NULL) |
1895 | return; | |
1896 | ||
1897 | /* Ok, so write the section info out. We have this layout: | |
1898 | ||
1899 | byte data what | |
1900 | ---- ---- ---- | |
1901 | 0 8 length of "APUinfo\0" | |
1902 | 4 (n*4) number of APU's (4 bytes each) | |
1903 | 8 2 note type 2 | |
1904 | 12 "APUinfo\0" name | |
1905 | 20 APU#1 first APU's info | |
1906 | 24 APU#2 second APU's info | |
1907 | ... ... | |
1908 | */ | |
1909 | { | |
1910 | char *p; | |
1911 | asection *seg = now_seg; | |
1912 | subsegT subseg = now_subseg; | |
1913 | asection *apuinfo_secp = (asection *) NULL; | |
49181a6a | 1914 | unsigned int i; |
6a0c61b7 EZ |
1915 | |
1916 | /* Create the .PPC.EMB.apuinfo section. */ | |
14b57c7c | 1917 | apuinfo_secp = subseg_new (APUINFO_SECTION_NAME, 0); |
fd361982 | 1918 | bfd_set_section_flags (apuinfo_secp, SEC_HAS_CONTENTS | SEC_READONLY); |
6a0c61b7 EZ |
1919 | |
1920 | p = frag_more (4); | |
1921 | md_number_to_chars (p, (valueT) 8, 4); | |
1922 | ||
1923 | p = frag_more (4); | |
e98d298c | 1924 | md_number_to_chars (p, (valueT) ppc_apuinfo_num * 4, 4); |
6a0c61b7 EZ |
1925 | |
1926 | p = frag_more (4); | |
1927 | md_number_to_chars (p, (valueT) 2, 4); | |
1928 | ||
1929 | p = frag_more (8); | |
14b57c7c | 1930 | strcpy (p, APUINFO_LABEL); |
6a0c61b7 EZ |
1931 | |
1932 | for (i = 0; i < ppc_apuinfo_num; i++) | |
1933 | { | |
b34976b6 AM |
1934 | p = frag_more (4); |
1935 | md_number_to_chars (p, (valueT) ppc_apuinfo_list[i], 4); | |
6a0c61b7 EZ |
1936 | } |
1937 | ||
1938 | frag_align (2, 0, 0); | |
1939 | ||
1940 | /* We probably can't restore the current segment, for there likely | |
1941 | isn't one yet... */ | |
1942 | if (seg && subseg) | |
1943 | subseg_set (seg, subseg); | |
1944 | } | |
dc1d03fc | 1945 | #endif |
6a0c61b7 EZ |
1946 | } |
1947 | ||
252b5132 RH |
1948 | /* Insert an operand value into an instruction. */ |
1949 | ||
0f873fd5 PB |
1950 | static uint64_t |
1951 | ppc_insert_operand (uint64_t insn, | |
a1867a27 | 1952 | const struct powerpc_operand *operand, |
0f873fd5 | 1953 | int64_t val, |
91d6fa6a | 1954 | ppc_cpu_t cpu, |
3b4dbbbf | 1955 | const char *file, |
a1867a27 | 1956 | unsigned int line) |
252b5132 | 1957 | { |
0f873fd5 | 1958 | int64_t min, max, right; |
eb42fac1 | 1959 | |
b84bf58a AM |
1960 | max = operand->bitm; |
1961 | right = max & -max; | |
1962 | min = 0; | |
1963 | ||
a47622ac | 1964 | if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) |
252b5132 | 1965 | { |
a255f00a AM |
1966 | /* Extend the allowed range for addis to [-32768, 65535]. |
1967 | Similarly for cmpli and some VLE high part insns. For 64-bit | |
1968 | it would be good to disable this for signed fields since the | |
a47622ac AM |
1969 | value is sign extended into the high 32 bits of the register. |
1970 | If the value is, say, an address, then we might care about | |
1971 | the high bits. However, gcc as of 2014-06 uses unsigned | |
1972 | values when loading the high part of 64-bit constants using | |
a255f00a AM |
1973 | lis. */ |
1974 | min = ~(max >> 1) & -right; | |
a47622ac AM |
1975 | } |
1976 | else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) | |
1977 | { | |
1978 | max = (max >> 1) & -right; | |
931774a9 | 1979 | min = ~max & -right; |
b84bf58a | 1980 | } |
252b5132 | 1981 | |
b84bf58a | 1982 | if ((operand->flags & PPC_OPERAND_PLUS1) != 0) |
3896c469 | 1983 | max++; |
252b5132 | 1984 | |
b84bf58a | 1985 | if ((operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
a1867a27 | 1986 | { |
0f873fd5 | 1987 | int64_t tmp = min; |
a1867a27 AM |
1988 | min = -max; |
1989 | max = -tmp; | |
1990 | } | |
b84bf58a | 1991 | |
a1867a27 AM |
1992 | if (min <= max) |
1993 | { | |
1994 | /* Some people write constants with the sign extension done by | |
1995 | hand but only up to 32 bits. This shouldn't really be valid, | |
1996 | but, to permit this code to assemble on a 64-bit host, we | |
1997 | sign extend the 32-bit value to 64 bits if so doing makes the | |
8acf1435 PB |
1998 | value valid. We only do this for operands that are 32-bits or |
1999 | smaller. */ | |
a1867a27 | 2000 | if (val > max |
8acf1435 | 2001 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2002 | && (val - (1LL << 32)) >= min |
2003 | && (val - (1LL << 32)) <= max | |
2004 | && ((val - (1LL << 32)) & (right - 1)) == 0) | |
2005 | val = val - (1LL << 32); | |
a1867a27 AM |
2006 | |
2007 | /* Similarly, people write expressions like ~(1<<15), and expect | |
2008 | this to be OK for a 32-bit unsigned value. */ | |
2009 | else if (val < min | |
8acf1435 | 2010 | && (operand->bitm & ~0xffffffffULL) == 0 |
0f873fd5 PB |
2011 | && (val + (1LL << 32)) >= min |
2012 | && (val + (1LL << 32)) <= max | |
2013 | && ((val + (1LL << 32)) & (right - 1)) == 0) | |
2014 | val = val + (1LL << 32); | |
a1867a27 AM |
2015 | |
2016 | else if (val < min | |
2017 | || val > max | |
2018 | || (val & (right - 1)) != 0) | |
2019 | as_bad_value_out_of_range (_("operand"), val, min, max, file, line); | |
2020 | } | |
b84bf58a | 2021 | |
252b5132 RH |
2022 | if (operand->insert) |
2023 | { | |
2024 | const char *errmsg; | |
2025 | ||
2026 | errmsg = NULL; | |
0f873fd5 | 2027 | insn = (*operand->insert) (insn, val, cpu, &errmsg); |
252b5132 | 2028 | if (errmsg != (const char *) NULL) |
ee2c9aa9 | 2029 | as_bad_where (file, line, "%s", errmsg); |
252b5132 | 2030 | } |
b9c361e0 | 2031 | else if (operand->shift >= 0) |
0f873fd5 | 2032 | insn |= (val & operand->bitm) << operand->shift; |
b9c361e0 | 2033 | else |
0f873fd5 | 2034 | insn |= (val & operand->bitm) >> -operand->shift; |
252b5132 RH |
2035 | |
2036 | return insn; | |
2037 | } | |
2038 | ||
2039 | \f | |
2040 | #ifdef OBJ_ELF | |
2041 | /* Parse @got, etc. and return the desired relocation. */ | |
2042 | static bfd_reloc_code_real_type | |
98027b10 | 2043 | ppc_elf_suffix (char **str_p, expressionS *exp_p) |
252b5132 RH |
2044 | { |
2045 | struct map_bfd { | |
e0471c16 | 2046 | const char *string; |
b7d7dc63 AM |
2047 | unsigned int length : 8; |
2048 | unsigned int valid32 : 1; | |
2049 | unsigned int valid64 : 1; | |
2050 | unsigned int reloc; | |
252b5132 RH |
2051 | }; |
2052 | ||
2053 | char ident[20]; | |
2054 | char *str = *str_p; | |
2055 | char *str2; | |
2056 | int ch; | |
2057 | int len; | |
15c1449b | 2058 | const struct map_bfd *ptr; |
252b5132 | 2059 | |
b7d7dc63 AM |
2060 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } |
2061 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2062 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
252b5132 | 2063 | |
15c1449b | 2064 | static const struct map_bfd mapping[] = { |
b7d7dc63 AM |
2065 | MAP ("l", BFD_RELOC_LO16), |
2066 | MAP ("h", BFD_RELOC_HI16), | |
2067 | MAP ("ha", BFD_RELOC_HI16_S), | |
2068 | MAP ("brtaken", BFD_RELOC_PPC_B16_BRTAKEN), | |
2069 | MAP ("brntaken", BFD_RELOC_PPC_B16_BRNTAKEN), | |
2070 | MAP ("got", BFD_RELOC_16_GOTOFF), | |
2071 | MAP ("got@l", BFD_RELOC_LO16_GOTOFF), | |
2072 | MAP ("got@h", BFD_RELOC_HI16_GOTOFF), | |
2073 | MAP ("got@ha", BFD_RELOC_HI16_S_GOTOFF), | |
2074 | MAP ("plt@l", BFD_RELOC_LO16_PLTOFF), | |
2075 | MAP ("plt@h", BFD_RELOC_HI16_PLTOFF), | |
2076 | MAP ("plt@ha", BFD_RELOC_HI16_S_PLTOFF), | |
2077 | MAP ("copy", BFD_RELOC_PPC_COPY), | |
2078 | MAP ("globdat", BFD_RELOC_PPC_GLOB_DAT), | |
2079 | MAP ("sectoff", BFD_RELOC_16_BASEREL), | |
2080 | MAP ("sectoff@l", BFD_RELOC_LO16_BASEREL), | |
2081 | MAP ("sectoff@h", BFD_RELOC_HI16_BASEREL), | |
2082 | MAP ("sectoff@ha", BFD_RELOC_HI16_S_BASEREL), | |
2083 | MAP ("tls", BFD_RELOC_PPC_TLS), | |
2084 | MAP ("dtpmod", BFD_RELOC_PPC_DTPMOD), | |
2085 | MAP ("dtprel", BFD_RELOC_PPC_DTPREL), | |
2086 | MAP ("dtprel@l", BFD_RELOC_PPC_DTPREL16_LO), | |
2087 | MAP ("dtprel@h", BFD_RELOC_PPC_DTPREL16_HI), | |
2088 | MAP ("dtprel@ha", BFD_RELOC_PPC_DTPREL16_HA), | |
2089 | MAP ("tprel", BFD_RELOC_PPC_TPREL), | |
2090 | MAP ("tprel@l", BFD_RELOC_PPC_TPREL16_LO), | |
2091 | MAP ("tprel@h", BFD_RELOC_PPC_TPREL16_HI), | |
2092 | MAP ("tprel@ha", BFD_RELOC_PPC_TPREL16_HA), | |
2093 | MAP ("got@tlsgd", BFD_RELOC_PPC_GOT_TLSGD16), | |
2094 | MAP ("got@tlsgd@l", BFD_RELOC_PPC_GOT_TLSGD16_LO), | |
2095 | MAP ("got@tlsgd@h", BFD_RELOC_PPC_GOT_TLSGD16_HI), | |
2096 | MAP ("got@tlsgd@ha", BFD_RELOC_PPC_GOT_TLSGD16_HA), | |
2097 | MAP ("got@tlsld", BFD_RELOC_PPC_GOT_TLSLD16), | |
2098 | MAP ("got@tlsld@l", BFD_RELOC_PPC_GOT_TLSLD16_LO), | |
2099 | MAP ("got@tlsld@h", BFD_RELOC_PPC_GOT_TLSLD16_HI), | |
2100 | MAP ("got@tlsld@ha", BFD_RELOC_PPC_GOT_TLSLD16_HA), | |
2101 | MAP ("got@dtprel", BFD_RELOC_PPC_GOT_DTPREL16), | |
2102 | MAP ("got@dtprel@l", BFD_RELOC_PPC_GOT_DTPREL16_LO), | |
2103 | MAP ("got@dtprel@h", BFD_RELOC_PPC_GOT_DTPREL16_HI), | |
2104 | MAP ("got@dtprel@ha", BFD_RELOC_PPC_GOT_DTPREL16_HA), | |
2105 | MAP ("got@tprel", BFD_RELOC_PPC_GOT_TPREL16), | |
2106 | MAP ("got@tprel@l", BFD_RELOC_PPC_GOT_TPREL16_LO), | |
2107 | MAP ("got@tprel@h", BFD_RELOC_PPC_GOT_TPREL16_HI), | |
2108 | MAP ("got@tprel@ha", BFD_RELOC_PPC_GOT_TPREL16_HA), | |
2109 | MAP32 ("fixup", BFD_RELOC_CTOR), | |
2110 | MAP32 ("plt", BFD_RELOC_24_PLT_PCREL), | |
2111 | MAP32 ("pltrel24", BFD_RELOC_24_PLT_PCREL), | |
2112 | MAP32 ("local24pc", BFD_RELOC_PPC_LOCAL24PC), | |
2113 | MAP32 ("local", BFD_RELOC_PPC_LOCAL24PC), | |
2114 | MAP32 ("pltrel", BFD_RELOC_32_PLT_PCREL), | |
2115 | MAP32 ("sdarel", BFD_RELOC_GPREL16), | |
b9c361e0 JL |
2116 | MAP32 ("sdarel@l", BFD_RELOC_PPC_VLE_SDAREL_LO16A), |
2117 | MAP32 ("sdarel@h", BFD_RELOC_PPC_VLE_SDAREL_HI16A), | |
2118 | MAP32 ("sdarel@ha", BFD_RELOC_PPC_VLE_SDAREL_HA16A), | |
b7d7dc63 AM |
2119 | MAP32 ("naddr", BFD_RELOC_PPC_EMB_NADDR32), |
2120 | MAP32 ("naddr16", BFD_RELOC_PPC_EMB_NADDR16), | |
2121 | MAP32 ("naddr@l", BFD_RELOC_PPC_EMB_NADDR16_LO), | |
2122 | MAP32 ("naddr@h", BFD_RELOC_PPC_EMB_NADDR16_HI), | |
2123 | MAP32 ("naddr@ha", BFD_RELOC_PPC_EMB_NADDR16_HA), | |
2124 | MAP32 ("sdai16", BFD_RELOC_PPC_EMB_SDAI16), | |
2125 | MAP32 ("sda2rel", BFD_RELOC_PPC_EMB_SDA2REL), | |
2126 | MAP32 ("sda2i16", BFD_RELOC_PPC_EMB_SDA2I16), | |
2127 | MAP32 ("sda21", BFD_RELOC_PPC_EMB_SDA21), | |
b9c361e0 | 2128 | MAP32 ("sda21@l", BFD_RELOC_PPC_VLE_SDA21_LO), |
b7d7dc63 AM |
2129 | MAP32 ("mrkref", BFD_RELOC_PPC_EMB_MRKREF), |
2130 | MAP32 ("relsect", BFD_RELOC_PPC_EMB_RELSEC16), | |
2131 | MAP32 ("relsect@l", BFD_RELOC_PPC_EMB_RELST_LO), | |
2132 | MAP32 ("relsect@h", BFD_RELOC_PPC_EMB_RELST_HI), | |
2133 | MAP32 ("relsect@ha", BFD_RELOC_PPC_EMB_RELST_HA), | |
2134 | MAP32 ("bitfld", BFD_RELOC_PPC_EMB_BIT_FLD), | |
2135 | MAP32 ("relsda", BFD_RELOC_PPC_EMB_RELSDA), | |
2136 | MAP32 ("xgot", BFD_RELOC_PPC_TOC16), | |
f9c6b907 AM |
2137 | MAP64 ("high", BFD_RELOC_PPC64_ADDR16_HIGH), |
2138 | MAP64 ("higha", BFD_RELOC_PPC64_ADDR16_HIGHA), | |
b7d7dc63 AM |
2139 | MAP64 ("higher", BFD_RELOC_PPC64_HIGHER), |
2140 | MAP64 ("highera", BFD_RELOC_PPC64_HIGHER_S), | |
2141 | MAP64 ("highest", BFD_RELOC_PPC64_HIGHEST), | |
2142 | MAP64 ("highesta", BFD_RELOC_PPC64_HIGHEST_S), | |
2143 | MAP64 ("tocbase", BFD_RELOC_PPC64_TOC), | |
2144 | MAP64 ("toc", BFD_RELOC_PPC_TOC16), | |
2145 | MAP64 ("toc@l", BFD_RELOC_PPC64_TOC16_LO), | |
2146 | MAP64 ("toc@h", BFD_RELOC_PPC64_TOC16_HI), | |
2147 | MAP64 ("toc@ha", BFD_RELOC_PPC64_TOC16_HA), | |
f9c6b907 AM |
2148 | MAP64 ("dtprel@high", BFD_RELOC_PPC64_DTPREL16_HIGH), |
2149 | MAP64 ("dtprel@higha", BFD_RELOC_PPC64_DTPREL16_HIGHA), | |
b7d7dc63 AM |
2150 | MAP64 ("dtprel@higher", BFD_RELOC_PPC64_DTPREL16_HIGHER), |
2151 | MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), | |
2152 | MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), | |
2153 | MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), | |
45965137 | 2154 | MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), |
f9c6b907 AM |
2155 | MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), |
2156 | MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), | |
b7d7dc63 AM |
2157 | MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), |
2158 | MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), | |
2159 | MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), | |
2160 | MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), | |
05d0e962 | 2161 | MAP64 ("notoc", BFD_RELOC_PPC64_REL24_NOTOC), |
5663e321 AM |
2162 | MAP64 ("pcrel", BFD_RELOC_PPC64_PCREL34), |
2163 | MAP64 ("got@pcrel", BFD_RELOC_PPC64_GOT_PCREL34), | |
2164 | MAP64 ("plt@pcrel", BFD_RELOC_PPC64_PLT_PCREL34), | |
c213164a | 2165 | MAP64 ("tls@pcrel", BFD_RELOC_PPC64_TLS_PCREL), |
87c69f97 AM |
2166 | MAP64 ("got@tlsgd@pcrel", BFD_RELOC_PPC64_GOT_TLSGD_PCREL34), |
2167 | MAP64 ("got@tlsld@pcrel", BFD_RELOC_PPC64_GOT_TLSLD_PCREL34), | |
2168 | MAP64 ("got@tprel@pcrel", BFD_RELOC_PPC64_GOT_TPREL_PCREL34), | |
2169 | MAP64 ("got@dtprel@pcrel", BFD_RELOC_PPC64_GOT_DTPREL_PCREL34), | |
5663e321 AM |
2170 | MAP64 ("higher34", BFD_RELOC_PPC64_ADDR16_HIGHER34), |
2171 | MAP64 ("highera34", BFD_RELOC_PPC64_ADDR16_HIGHERA34), | |
2172 | MAP64 ("highest34", BFD_RELOC_PPC64_ADDR16_HIGHEST34), | |
2173 | MAP64 ("highesta34", BFD_RELOC_PPC64_ADDR16_HIGHESTA34), | |
62ebcb5c | 2174 | { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } |
252b5132 RH |
2175 | }; |
2176 | ||
2177 | if (*str++ != '@') | |
62ebcb5c | 2178 | return BFD_RELOC_NONE; |
252b5132 RH |
2179 | |
2180 | for (ch = *str, str2 = ident; | |
2181 | (str2 < ident + sizeof (ident) - 1 | |
3882b010 | 2182 | && (ISALNUM (ch) || ch == '@')); |
252b5132 RH |
2183 | ch = *++str) |
2184 | { | |
3882b010 | 2185 | *str2++ = TOLOWER (ch); |
252b5132 RH |
2186 | } |
2187 | ||
2188 | *str2 = '\0'; | |
2189 | len = str2 - ident; | |
2190 | ||
2191 | ch = ident[0]; | |
2192 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2193 | if (ch == ptr->string[0] | |
2194 | && len == ptr->length | |
b7d7dc63 AM |
2195 | && memcmp (ident, ptr->string, ptr->length) == 0 |
2196 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
252b5132 | 2197 | { |
15c1449b AM |
2198 | int reloc = ptr->reloc; |
2199 | ||
32d71569 | 2200 | if (!ppc_obj64 && (exp_p->X_op == O_big || exp_p->X_add_number != 0)) |
727fc41e AM |
2201 | { |
2202 | switch (reloc) | |
2203 | { | |
2204 | case BFD_RELOC_16_GOTOFF: | |
2205 | case BFD_RELOC_LO16_GOTOFF: | |
2206 | case BFD_RELOC_HI16_GOTOFF: | |
2207 | case BFD_RELOC_HI16_S_GOTOFF: | |
e47d413a AM |
2208 | as_warn (_("symbol+offset@%s means symbol@%s+offset"), |
2209 | ptr->string, ptr->string); | |
727fc41e AM |
2210 | break; |
2211 | ||
2212 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
2213 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
2214 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
2215 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
2216 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
2217 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
2218 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
2219 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
2220 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
2221 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
2222 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
2223 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
2224 | case BFD_RELOC_PPC_GOT_TPREL16: | |
2225 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
2226 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
2227 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
e47d413a | 2228 | as_bad (_("symbol+offset@%s not supported"), ptr->string); |
727fc41e AM |
2229 | break; |
2230 | } | |
2231 | } | |
5f6db75a AM |
2232 | |
2233 | /* Now check for identifier@suffix+constant. */ | |
2234 | if (*str == '-' || *str == '+') | |
252b5132 | 2235 | { |
5f6db75a AM |
2236 | char *orig_line = input_line_pointer; |
2237 | expressionS new_exp; | |
2238 | ||
2239 | input_line_pointer = str; | |
2240 | expression (&new_exp); | |
32d71569 | 2241 | if (new_exp.X_op == O_constant && exp_p->X_op != O_big) |
252b5132 | 2242 | { |
5f6db75a AM |
2243 | exp_p->X_add_number += new_exp.X_add_number; |
2244 | str = input_line_pointer; | |
252b5132 | 2245 | } |
32d71569 | 2246 | input_line_pointer = orig_line; |
252b5132 | 2247 | } |
252b5132 | 2248 | *str_p = str; |
0baf16f2 | 2249 | |
2b3c4602 | 2250 | if (reloc == (int) BFD_RELOC_PPC64_TOC |
9f2b53d7 AM |
2251 | && exp_p->X_op == O_symbol |
2252 | && strcmp (S_GET_NAME (exp_p->X_add_symbol), ".TOC.") == 0) | |
0baf16f2 | 2253 | { |
9f2b53d7 AM |
2254 | /* Change the symbol so that the dummy .TOC. symbol can be |
2255 | omitted from the object file. */ | |
0baf16f2 AM |
2256 | exp_p->X_add_symbol = &abs_symbol; |
2257 | } | |
2258 | ||
15c1449b | 2259 | return (bfd_reloc_code_real_type) reloc; |
252b5132 RH |
2260 | } |
2261 | ||
62ebcb5c | 2262 | return BFD_RELOC_NONE; |
252b5132 RH |
2263 | } |
2264 | ||
62ebcb5c | 2265 | /* Support @got, etc. on constants emitted via .short, .int etc. */ |
99a814a1 | 2266 | |
62ebcb5c AM |
2267 | bfd_reloc_code_real_type |
2268 | ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) | |
2269 | { | |
2270 | expression (exp); | |
2271 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2272 | return ppc_elf_suffix (&input_line_pointer, exp); | |
2273 | return BFD_RELOC_NONE; | |
252b5132 RH |
2274 | } |
2275 | ||
bf7279d5 AM |
2276 | /* Warn when emitting data to code sections, unless we are emitting |
2277 | a relocation that ld --ppc476-workaround uses to recognise data | |
2278 | *and* there was an unconditional branch prior to the data. */ | |
2279 | ||
2280 | void | |
2281 | ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, | |
2282 | unsigned int nbytes, fixS *fix) | |
2283 | { | |
2284 | if (warn_476 | |
2285 | && (now_seg->flags & SEC_CODE) != 0 | |
2286 | && (nbytes != 4 | |
2287 | || fix == NULL | |
2288 | || !(fix->fx_r_type == BFD_RELOC_32 | |
2289 | || fix->fx_r_type == BFD_RELOC_CTOR | |
2290 | || fix->fx_r_type == BFD_RELOC_32_PCREL) | |
2291 | || !(last_seg == now_seg && last_subseg == now_subseg) | |
2292 | || !((last_insn & (0x3f << 26)) == (18u << 26) | |
2293 | || ((last_insn & (0x3f << 26)) == (16u << 26) | |
2294 | && (last_insn & (0x14 << 21)) == (0x14 << 21)) | |
2295 | || ((last_insn & (0x3f << 26)) == (19u << 26) | |
2296 | && (last_insn & (0x3ff << 1)) == (16u << 1) | |
2297 | && (last_insn & (0x14 << 21)) == (0x14 << 21))))) | |
2298 | { | |
2299 | /* Flag that we've warned. */ | |
2300 | if (fix != NULL) | |
2301 | fix->fx_tcbit = 1; | |
2302 | ||
2303 | as_warn (_("data in executable section")); | |
2304 | } | |
2305 | } | |
2306 | ||
252b5132 RH |
2307 | /* Solaris pseduo op to change to the .rodata section. */ |
2308 | static void | |
98027b10 | 2309 | ppc_elf_rdata (int xxx) |
252b5132 RH |
2310 | { |
2311 | char *save_line = input_line_pointer; | |
2312 | static char section[] = ".rodata\n"; | |
2313 | ||
99a814a1 | 2314 | /* Just pretend this is .section .rodata */ |
252b5132 RH |
2315 | input_line_pointer = section; |
2316 | obj_elf_section (xxx); | |
2317 | ||
2318 | input_line_pointer = save_line; | |
2319 | } | |
2320 | ||
99a814a1 | 2321 | /* Pseudo op to make file scope bss items. */ |
252b5132 | 2322 | static void |
98027b10 | 2323 | ppc_elf_lcomm (int xxx ATTRIBUTE_UNUSED) |
252b5132 | 2324 | { |
98027b10 AM |
2325 | char *name; |
2326 | char c; | |
2327 | char *p; | |
252b5132 | 2328 | offsetT size; |
98027b10 | 2329 | symbolS *symbolP; |
252b5132 RH |
2330 | offsetT align; |
2331 | segT old_sec; | |
2332 | int old_subsec; | |
2333 | char *pfrag; | |
2334 | int align2; | |
2335 | ||
d02603dc | 2336 | c = get_symbol_name (&name); |
252b5132 | 2337 | |
d02603dc | 2338 | /* Just after name is now '\0'. */ |
252b5132 RH |
2339 | p = input_line_pointer; |
2340 | *p = c; | |
d02603dc | 2341 | SKIP_WHITESPACE_AFTER_NAME (); |
252b5132 RH |
2342 | if (*input_line_pointer != ',') |
2343 | { | |
d6ed37ed | 2344 | as_bad (_("expected comma after symbol-name: rest of line ignored.")); |
252b5132 RH |
2345 | ignore_rest_of_line (); |
2346 | return; | |
2347 | } | |
2348 | ||
2349 | input_line_pointer++; /* skip ',' */ | |
2350 | if ((size = get_absolute_expression ()) < 0) | |
2351 | { | |
2352 | as_warn (_(".COMMon length (%ld.) <0! Ignored."), (long) size); | |
2353 | ignore_rest_of_line (); | |
2354 | return; | |
2355 | } | |
2356 | ||
2357 | /* The third argument to .lcomm is the alignment. */ | |
2358 | if (*input_line_pointer != ',') | |
2359 | align = 8; | |
2360 | else | |
2361 | { | |
2362 | ++input_line_pointer; | |
2363 | align = get_absolute_expression (); | |
2364 | if (align <= 0) | |
2365 | { | |
2366 | as_warn (_("ignoring bad alignment")); | |
2367 | align = 8; | |
2368 | } | |
2369 | } | |
2370 | ||
2371 | *p = 0; | |
2372 | symbolP = symbol_find_or_make (name); | |
2373 | *p = c; | |
2374 | ||
2375 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) | |
2376 | { | |
d6ed37ed | 2377 | as_bad (_("ignoring attempt to re-define symbol `%s'."), |
252b5132 RH |
2378 | S_GET_NAME (symbolP)); |
2379 | ignore_rest_of_line (); | |
2380 | return; | |
2381 | } | |
2382 | ||
2383 | if (S_GET_VALUE (symbolP) && S_GET_VALUE (symbolP) != (valueT) size) | |
2384 | { | |
d6ed37ed | 2385 | as_bad (_("length of .lcomm \"%s\" is already %ld. Not changed to %ld."), |
252b5132 RH |
2386 | S_GET_NAME (symbolP), |
2387 | (long) S_GET_VALUE (symbolP), | |
2388 | (long) size); | |
2389 | ||
2390 | ignore_rest_of_line (); | |
2391 | return; | |
2392 | } | |
2393 | ||
99a814a1 | 2394 | /* Allocate_bss. */ |
252b5132 RH |
2395 | old_sec = now_seg; |
2396 | old_subsec = now_subseg; | |
2397 | if (align) | |
2398 | { | |
99a814a1 | 2399 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
2400 | for (align2 = 0; (align & 1) == 0; align >>= 1, ++align2); |
2401 | if (align != 1) | |
2402 | { | |
d6ed37ed | 2403 | as_bad (_("common alignment not a power of 2")); |
252b5132 RH |
2404 | ignore_rest_of_line (); |
2405 | return; | |
2406 | } | |
2407 | } | |
2408 | else | |
2409 | align2 = 0; | |
2410 | ||
2411 | record_alignment (bss_section, align2); | |
cbe02d4f | 2412 | subseg_set (bss_section, 1); |
252b5132 RH |
2413 | if (align2) |
2414 | frag_align (align2, 0, 0); | |
2415 | if (S_GET_SEGMENT (symbolP) == bss_section) | |
49309057 ILT |
2416 | symbol_get_frag (symbolP)->fr_symbol = 0; |
2417 | symbol_set_frag (symbolP, frag_now); | |
252b5132 RH |
2418 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, size, |
2419 | (char *) 0); | |
2420 | *pfrag = 0; | |
2421 | S_SET_SIZE (symbolP, size); | |
2422 | S_SET_SEGMENT (symbolP, bss_section); | |
2423 | subseg_set (old_sec, old_subsec); | |
2424 | demand_empty_rest_of_line (); | |
2425 | } | |
2426 | ||
6911b7dc AM |
2427 | /* Pseudo op to set symbol local entry point. */ |
2428 | static void | |
2429 | ppc_elf_localentry (int ignore ATTRIBUTE_UNUSED) | |
2430 | { | |
d02603dc NC |
2431 | char *name; |
2432 | char c = get_symbol_name (&name); | |
6911b7dc AM |
2433 | char *p; |
2434 | expressionS exp; | |
2435 | symbolS *sym; | |
2436 | asymbol *bfdsym; | |
2437 | elf_symbol_type *elfsym; | |
2438 | ||
2439 | p = input_line_pointer; | |
2440 | *p = c; | |
d02603dc | 2441 | SKIP_WHITESPACE_AFTER_NAME (); |
6911b7dc AM |
2442 | if (*input_line_pointer != ',') |
2443 | { | |
2444 | *p = 0; | |
2445 | as_bad (_("expected comma after name `%s' in .localentry directive"), | |
2446 | name); | |
2447 | *p = c; | |
2448 | ignore_rest_of_line (); | |
2449 | return; | |
2450 | } | |
2451 | input_line_pointer++; | |
2452 | expression (&exp); | |
2453 | if (exp.X_op == O_absent) | |
2454 | { | |
2455 | as_bad (_("missing expression in .localentry directive")); | |
2456 | exp.X_op = O_constant; | |
2457 | exp.X_add_number = 0; | |
2458 | } | |
2459 | *p = 0; | |
2460 | sym = symbol_find_or_make (name); | |
2461 | *p = c; | |
2462 | ||
2463 | if (resolve_expression (&exp) | |
2464 | && exp.X_op == O_constant) | |
2465 | { | |
33cb30a1 | 2466 | unsigned int encoded, ok; |
6911b7dc | 2467 | |
33cb30a1 AM |
2468 | ok = 1; |
2469 | if (exp.X_add_number == 1 || exp.X_add_number == 7) | |
2470 | encoded = exp.X_add_number << STO_PPC64_LOCAL_BIT; | |
6911b7dc | 2471 | else |
33cb30a1 AM |
2472 | { |
2473 | encoded = PPC64_SET_LOCAL_ENTRY_OFFSET (exp.X_add_number); | |
2474 | if (exp.X_add_number != (offsetT) PPC64_LOCAL_ENTRY_OFFSET (encoded)) | |
2475 | { | |
2476 | as_bad (_(".localentry expression for `%s' " | |
2477 | "is not a valid power of 2"), S_GET_NAME (sym)); | |
2478 | ok = 0; | |
2479 | } | |
2480 | } | |
2481 | if (ok) | |
6911b7dc AM |
2482 | { |
2483 | bfdsym = symbol_get_bfdsym (sym); | |
c1229f84 | 2484 | elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
2485 | gas_assert (elfsym); |
2486 | elfsym->internal_elf_sym.st_other &= ~STO_PPC64_LOCAL_MASK; | |
2487 | elfsym->internal_elf_sym.st_other |= encoded; | |
2488 | if (ppc_abiversion == 0) | |
2489 | ppc_abiversion = 2; | |
2490 | } | |
2491 | } | |
2492 | else | |
2493 | as_bad (_(".localentry expression for `%s' " | |
2494 | "does not evaluate to a constant"), S_GET_NAME (sym)); | |
2495 | ||
2496 | demand_empty_rest_of_line (); | |
2497 | } | |
2498 | ||
ee67d69a AM |
2499 | /* Pseudo op to set ABI version. */ |
2500 | static void | |
2501 | ppc_elf_abiversion (int ignore ATTRIBUTE_UNUSED) | |
2502 | { | |
2503 | expressionS exp; | |
2504 | ||
2505 | expression (&exp); | |
2506 | if (exp.X_op == O_absent) | |
2507 | { | |
2508 | as_bad (_("missing expression in .abiversion directive")); | |
2509 | exp.X_op = O_constant; | |
2510 | exp.X_add_number = 0; | |
2511 | } | |
2512 | ||
2513 | if (resolve_expression (&exp) | |
2514 | && exp.X_op == O_constant) | |
2515 | ppc_abiversion = exp.X_add_number; | |
2516 | else | |
2517 | as_bad (_(".abiversion expression does not evaluate to a constant")); | |
2518 | demand_empty_rest_of_line (); | |
2519 | } | |
2520 | ||
005d79fd AM |
2521 | /* Parse a .gnu_attribute directive. */ |
2522 | static void | |
2523 | ppc_elf_gnu_attribute (int ignored ATTRIBUTE_UNUSED) | |
2524 | { | |
2525 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_GNU); | |
2526 | ||
2527 | /* Check validity of defined powerpc tags. */ | |
2528 | if (tag == Tag_GNU_Power_ABI_FP | |
2529 | || tag == Tag_GNU_Power_ABI_Vector | |
2530 | || tag == Tag_GNU_Power_ABI_Struct_Return) | |
2531 | { | |
2532 | unsigned int val; | |
2533 | ||
2534 | val = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, tag); | |
2535 | ||
2536 | if ((tag == Tag_GNU_Power_ABI_FP && val > 15) | |
2537 | || (tag == Tag_GNU_Power_ABI_Vector && val > 3) | |
2538 | || (tag == Tag_GNU_Power_ABI_Struct_Return && val > 2)) | |
2539 | as_warn (_("unknown .gnu_attribute value")); | |
2540 | } | |
2541 | } | |
2542 | ||
ee67d69a AM |
2543 | /* Set ABI version in output file. */ |
2544 | void | |
2545 | ppc_elf_end (void) | |
2546 | { | |
2547 | if (ppc_obj64 && ppc_abiversion != 0) | |
2548 | { | |
2549 | elf_elfheader (stdoutput)->e_flags &= ~EF_PPC64_ABI; | |
2550 | elf_elfheader (stdoutput)->e_flags |= ppc_abiversion & EF_PPC64_ABI; | |
2551 | } | |
22f72c48 AM |
2552 | /* Any selection of opcodes based on ppc_cpu after gas has finished |
2553 | parsing the file is invalid. md_apply_fix and ppc_handle_align | |
2554 | must select opcodes based on the machine in force at the point | |
2555 | where the fixup or alignment frag was created, not the machine in | |
2556 | force at the end of file. */ | |
2557 | ppc_cpu = 0; | |
ee67d69a AM |
2558 | } |
2559 | ||
252b5132 RH |
2560 | /* Validate any relocations emitted for -mrelocatable, possibly adding |
2561 | fixups for word relocations in writable segments, so we can adjust | |
2562 | them at runtime. */ | |
2563 | static void | |
98027b10 | 2564 | ppc_elf_validate_fix (fixS *fixp, segT seg) |
252b5132 RH |
2565 | { |
2566 | if (fixp->fx_done || fixp->fx_pcrel) | |
2567 | return; | |
2568 | ||
2569 | switch (shlib) | |
2570 | { | |
2571 | case SHLIB_NONE: | |
2572 | case SHLIB_PIC: | |
2573 | return; | |
2574 | ||
5d6f4f16 | 2575 | case SHLIB_MRELOCATABLE: |
62ebcb5c | 2576 | if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF |
252b5132 RH |
2577 | && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF |
2578 | && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
2579 | && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
1cfc59d5 | 2580 | && fixp->fx_r_type != BFD_RELOC_16_BASEREL |
252b5132 RH |
2581 | && fixp->fx_r_type != BFD_RELOC_LO16_BASEREL |
2582 | && fixp->fx_r_type != BFD_RELOC_HI16_BASEREL | |
2583 | && fixp->fx_r_type != BFD_RELOC_HI16_S_BASEREL | |
e138127a | 2584 | && (seg->flags & SEC_LOAD) != 0 |
252b5132 RH |
2585 | && strcmp (segment_name (seg), ".got2") != 0 |
2586 | && strcmp (segment_name (seg), ".dtors") != 0 | |
2587 | && strcmp (segment_name (seg), ".ctors") != 0 | |
2588 | && strcmp (segment_name (seg), ".fixup") != 0 | |
252b5132 RH |
2589 | && strcmp (segment_name (seg), ".gcc_except_table") != 0 |
2590 | && strcmp (segment_name (seg), ".eh_frame") != 0 | |
2591 | && strcmp (segment_name (seg), ".ex_shared") != 0) | |
2592 | { | |
2593 | if ((seg->flags & (SEC_READONLY | SEC_CODE)) != 0 | |
2594 | || fixp->fx_r_type != BFD_RELOC_CTOR) | |
2595 | { | |
2596 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
d6ed37ed | 2597 | _("relocation cannot be done when using -mrelocatable")); |
252b5132 RH |
2598 | } |
2599 | } | |
2600 | return; | |
2601 | } | |
2602 | } | |
0baf16f2 | 2603 | |
7e8d4ab4 AM |
2604 | /* Prevent elf_frob_file_before_adjust removing a weak undefined |
2605 | function descriptor sym if the corresponding code sym is used. */ | |
2606 | ||
2607 | void | |
98027b10 | 2608 | ppc_frob_file_before_adjust (void) |
0baf16f2 | 2609 | { |
7e8d4ab4 | 2610 | symbolS *symp; |
9232bbb0 | 2611 | asection *toc; |
0baf16f2 | 2612 | |
7e8d4ab4 AM |
2613 | if (!ppc_obj64) |
2614 | return; | |
2615 | ||
2616 | for (symp = symbol_rootP; symp; symp = symbol_next (symp)) | |
0baf16f2 | 2617 | { |
7e8d4ab4 AM |
2618 | const char *name; |
2619 | char *dotname; | |
2620 | symbolS *dotsym; | |
7e8d4ab4 AM |
2621 | |
2622 | name = S_GET_NAME (symp); | |
2623 | if (name[0] == '.') | |
2624 | continue; | |
2625 | ||
2626 | if (! S_IS_WEAK (symp) | |
2627 | || S_IS_DEFINED (symp)) | |
2628 | continue; | |
2629 | ||
a44e2901 | 2630 | dotname = concat (".", name, (char *) NULL); |
461b725f | 2631 | dotsym = symbol_find_noref (dotname, 1); |
7e8d4ab4 AM |
2632 | free (dotname); |
2633 | if (dotsym != NULL && (symbol_used_p (dotsym) | |
2634 | || symbol_used_in_reloc_p (dotsym))) | |
670ec21d NC |
2635 | symbol_mark_used (symp); |
2636 | ||
0baf16f2 AM |
2637 | } |
2638 | ||
9232bbb0 AM |
2639 | toc = bfd_get_section_by_name (stdoutput, ".toc"); |
2640 | if (toc != NULL | |
01efc3af | 2641 | && toc_reloc_types != has_large_toc_reloc |
fd361982 | 2642 | && bfd_section_size (toc) > 0x10000) |
9232bbb0 | 2643 | as_warn (_("TOC section size exceeds 64k")); |
a38a07e0 AM |
2644 | } |
2645 | ||
2646 | /* .TOC. used in an opd entry as .TOC.@tocbase doesn't need to be | |
2647 | emitted. Other uses of .TOC. will cause the symbol to be marked | |
2648 | with BSF_KEEP in md_apply_fix. */ | |
9232bbb0 | 2649 | |
a38a07e0 AM |
2650 | void |
2651 | ppc_elf_adjust_symtab (void) | |
2652 | { | |
2653 | if (ppc_obj64) | |
2654 | { | |
2655 | symbolS *symp; | |
2656 | symp = symbol_find (".TOC."); | |
2657 | if (symp != NULL) | |
2658 | { | |
2659 | asymbol *bsym = symbol_get_bfdsym (symp); | |
2660 | if ((bsym->flags & BSF_KEEP) == 0) | |
2661 | symbol_remove (symp, &symbol_rootP, &symbol_lastP); | |
a38a07e0 AM |
2662 | } |
2663 | } | |
0baf16f2 | 2664 | } |
252b5132 | 2665 | #endif /* OBJ_ELF */ |
4a403be0 CC |
2666 | |
2667 | #ifdef OBJ_XCOFF | |
2668 | /* Parse XCOFF relocations. */ | |
2669 | static bfd_reloc_code_real_type | |
2670 | ppc_xcoff_suffix (char **str_p) | |
2671 | { | |
2672 | struct map_bfd { | |
2673 | const char *string; | |
2674 | unsigned int length : 8; | |
2675 | unsigned int valid32 : 1; | |
2676 | unsigned int valid64 : 1; | |
2677 | unsigned int reloc; | |
2678 | }; | |
2679 | ||
2680 | char ident[20]; | |
2681 | char *str = *str_p; | |
2682 | char *str2; | |
2683 | int ch; | |
2684 | int len; | |
2685 | const struct map_bfd *ptr; | |
2686 | ||
2687 | #define MAP(str, reloc) { str, sizeof (str) - 1, 1, 1, reloc } | |
2688 | #define MAP32(str, reloc) { str, sizeof (str) - 1, 1, 0, reloc } | |
2689 | #define MAP64(str, reloc) { str, sizeof (str) - 1, 0, 1, reloc } | |
2690 | ||
2691 | static const struct map_bfd mapping[] = { | |
2692 | MAP ("l", BFD_RELOC_PPC_TOC16_LO), | |
2693 | MAP ("u", BFD_RELOC_PPC_TOC16_HI), | |
1b2cb8e2 CC |
2694 | MAP32 ("ie", BFD_RELOC_PPC_TLSIE), |
2695 | MAP32 ("ld", BFD_RELOC_PPC_TLSLD), | |
2696 | MAP32 ("le", BFD_RELOC_PPC_TLSLE), | |
2697 | MAP32 ("m", BFD_RELOC_PPC_TLSM), | |
2698 | MAP32 ("ml", BFD_RELOC_PPC_TLSML), | |
2699 | MAP64 ("ie", BFD_RELOC_PPC64_TLSIE), | |
2700 | MAP64 ("ld", BFD_RELOC_PPC64_TLSLD), | |
2701 | MAP64 ("le", BFD_RELOC_PPC64_TLSLE), | |
2702 | MAP64 ("m", BFD_RELOC_PPC64_TLSM), | |
2703 | MAP64 ("ml", BFD_RELOC_PPC64_TLSML), | |
4a403be0 CC |
2704 | }; |
2705 | ||
2706 | if (*str++ != '@') | |
2707 | return BFD_RELOC_NONE; | |
2708 | ||
2709 | for (ch = *str, str2 = ident; | |
2710 | (str2 < ident + sizeof (ident) - 1 | |
2711 | && (ISALNUM (ch) || ch == '@')); | |
2712 | ch = *++str) | |
2713 | { | |
2714 | *str2++ = TOLOWER (ch); | |
2715 | } | |
2716 | ||
2717 | *str2 = '\0'; | |
2718 | len = str2 - ident; | |
2719 | ||
2720 | ch = ident[0]; | |
2721 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
2722 | if (ch == ptr->string[0] | |
2723 | && len == ptr->length | |
2724 | && memcmp (ident, ptr->string, ptr->length) == 0 | |
2725 | && (ppc_obj64 ? ptr->valid64 : ptr->valid32)) | |
2726 | { | |
2727 | *str_p = str; | |
2728 | return (bfd_reloc_code_real_type) ptr->reloc; | |
2729 | } | |
2730 | ||
2731 | return BFD_RELOC_NONE; | |
2732 | } | |
2733 | ||
2734 | /* Restore XCOFF addis instruction to ELF format. | |
2735 | AIX often generates addis instructions using "addis RT,D(RA)" | |
2736 | format instead of the ELF "addis RT,RA,SI" one. | |
2737 | On entry RT_E is at the comma after RT, D_E is at the open | |
2738 | parenthesis after D, and RA_E is at the close parenthesis after RA. */ | |
2739 | static void | |
2740 | ppc_xcoff_fixup_addis (char *rt_e, char *d_e, char *ra_e) | |
2741 | { | |
2742 | size_t ra_size = ra_e - d_e - 1; | |
2743 | char *save_ra = xmalloc (ra_size); | |
2744 | ||
2745 | /* Copy RA. */ | |
2746 | memcpy (save_ra, d_e + 1, ra_size); | |
2747 | /* Shuffle D to make room for RA, copying the comma too. */ | |
2748 | memmove (rt_e + ra_size + 1, rt_e, d_e - rt_e); | |
2749 | /* Erase the trailing ')', keeping any rubbish for potential errors. */ | |
2750 | memmove (ra_e, ra_e + 1, strlen (ra_e)); | |
2751 | /* Write RA back. */ | |
2752 | memcpy (rt_e + 1, save_ra, ra_size); | |
2753 | free (save_ra); | |
2754 | } | |
2755 | ||
1b2cb8e2 CC |
2756 | /* Support @ie, etc. on constants emitted via .short, .int etc. */ |
2757 | ||
2758 | bfd_reloc_code_real_type | |
2759 | ppc_xcoff_parse_cons (expressionS *exp, unsigned int nbytes) | |
2760 | { | |
2761 | expression (exp); | |
2762 | if (nbytes >= 2 && *input_line_pointer == '@') | |
2763 | return ppc_xcoff_suffix (&input_line_pointer); | |
2764 | ||
2765 | /* There isn't any @ symbol for default TLS relocations (R_TLS). */ | |
2766 | if (exp->X_add_symbol != NULL | |
2767 | && (symbol_get_tc (exp->X_add_symbol)->symbol_class == XMC_TL | |
2768 | || symbol_get_tc (exp->X_add_symbol)->symbol_class == XMC_UL)) | |
2769 | return (ppc_obj64 ? BFD_RELOC_PPC64_TLSGD: BFD_RELOC_PPC_TLSGD); | |
2770 | ||
2771 | return BFD_RELOC_NONE; | |
2772 | } | |
2773 | ||
4a403be0 | 2774 | #endif /* OBJ_XCOFF */ |
252b5132 | 2775 | \f |
3e60bf4d | 2776 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
3b8b57a9 AM |
2777 | /* See whether a symbol is in the TOC section. */ |
2778 | ||
2779 | static int | |
2780 | ppc_is_toc_sym (symbolS *sym) | |
2781 | { | |
3e60bf4d | 2782 | #ifdef OBJ_XCOFF |
9f6e76f4 | 2783 | return (symbol_get_tc (sym)->symbol_class == XMC_TC |
4a403be0 | 2784 | || symbol_get_tc (sym)->symbol_class == XMC_TE |
9f6e76f4 | 2785 | || symbol_get_tc (sym)->symbol_class == XMC_TC0); |
f50c47f1 | 2786 | #endif |
3e60bf4d AM |
2787 | #ifdef OBJ_ELF |
2788 | const char *sname = segment_name (S_GET_SEGMENT (sym)); | |
2789 | if (ppc_obj64) | |
2790 | return strcmp (sname, ".toc") == 0; | |
2791 | else | |
2792 | return strcmp (sname, ".got") == 0; | |
2793 | #endif | |
2794 | } | |
2795 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ | |
252b5132 RH |
2796 | \f |
2797 | ||
dc1d03fc | 2798 | #ifdef OBJ_ELF |
6a0c61b7 EZ |
2799 | #define APUID(a,v) ((((a) & 0xffff) << 16) | ((v) & 0xffff)) |
2800 | static void | |
98027b10 | 2801 | ppc_apuinfo_section_add (unsigned int apu, unsigned int version) |
6a0c61b7 EZ |
2802 | { |
2803 | unsigned int i; | |
2804 | ||
2805 | /* Check we don't already exist. */ | |
2806 | for (i = 0; i < ppc_apuinfo_num; i++) | |
dc1d03fc | 2807 | if (ppc_apuinfo_list[i] == APUID (apu, version)) |
6a0c61b7 | 2808 | return; |
b34976b6 | 2809 | |
6a0c61b7 EZ |
2810 | if (ppc_apuinfo_num == ppc_apuinfo_num_alloc) |
2811 | { | |
2812 | if (ppc_apuinfo_num_alloc == 0) | |
2813 | { | |
2814 | ppc_apuinfo_num_alloc = 4; | |
325801bd | 2815 | ppc_apuinfo_list = XNEWVEC (unsigned long, ppc_apuinfo_num_alloc); |
6a0c61b7 EZ |
2816 | } |
2817 | else | |
2818 | { | |
2819 | ppc_apuinfo_num_alloc += 4; | |
325801bd TS |
2820 | ppc_apuinfo_list = XRESIZEVEC (unsigned long, ppc_apuinfo_list, |
2821 | ppc_apuinfo_num_alloc); | |
6a0c61b7 EZ |
2822 | } |
2823 | } | |
dc1d03fc | 2824 | ppc_apuinfo_list[ppc_apuinfo_num++] = APUID (apu, version); |
6a0c61b7 EZ |
2825 | } |
2826 | #undef APUID | |
dc1d03fc | 2827 | #endif |
6a0c61b7 | 2828 | \f |
dd7efa79 PB |
2829 | /* Various frobbings of labels and their addresses. */ |
2830 | ||
2831 | /* Symbols labelling the current insn. */ | |
2832 | struct insn_label_list | |
2833 | { | |
2834 | struct insn_label_list *next; | |
2835 | symbolS *label; | |
2836 | }; | |
2837 | ||
2838 | static struct insn_label_list *insn_labels; | |
2839 | static struct insn_label_list *free_insn_labels; | |
2840 | ||
2841 | static void | |
2842 | ppc_record_label (symbolS *sym) | |
2843 | { | |
2844 | struct insn_label_list *l; | |
2845 | ||
2846 | if (free_insn_labels == NULL) | |
2847 | l = XNEW (struct insn_label_list); | |
2848 | else | |
2849 | { | |
2850 | l = free_insn_labels; | |
2851 | free_insn_labels = l->next; | |
2852 | } | |
2853 | ||
2854 | l->label = sym; | |
2855 | l->next = insn_labels; | |
2856 | insn_labels = l; | |
2857 | } | |
2858 | ||
2859 | static void | |
2860 | ppc_clear_labels (void) | |
2861 | { | |
2862 | while (insn_labels != NULL) | |
2863 | { | |
2864 | struct insn_label_list *l = insn_labels; | |
2865 | insn_labels = l->next; | |
2866 | l->next = free_insn_labels; | |
2867 | free_insn_labels = l; | |
2868 | } | |
2869 | } | |
2870 | ||
2871 | void | |
2872 | ppc_start_line_hook (void) | |
2873 | { | |
2874 | ppc_clear_labels (); | |
2875 | } | |
2876 | ||
2877 | void | |
2878 | ppc_new_dot_label (symbolS *sym) | |
2879 | { | |
2880 | ppc_record_label (sym); | |
2881 | #ifdef OBJ_XCOFF | |
2882 | /* Anchor this label to the current csect for relocations. */ | |
2883 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2884 | #endif | |
2885 | } | |
2886 | ||
2887 | void | |
2888 | ppc_frob_label (symbolS *sym) | |
2889 | { | |
2890 | ppc_record_label (sym); | |
2891 | ||
2892 | #ifdef OBJ_XCOFF | |
2893 | /* Set the class of a label based on where it is defined. This handles | |
2894 | symbols without suffixes. Also, move the symbol so that it follows | |
2895 | the csect symbol. */ | |
2896 | if (ppc_current_csect != (symbolS *) NULL) | |
2897 | { | |
2898 | if (symbol_get_tc (sym)->symbol_class == -1) | |
2899 | symbol_get_tc (sym)->symbol_class = symbol_get_tc (ppc_current_csect)->symbol_class; | |
2900 | ||
2901 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
2902 | symbol_append (sym, symbol_get_tc (ppc_current_csect)->within, | |
2903 | &symbol_rootP, &symbol_lastP); | |
2904 | symbol_get_tc (ppc_current_csect)->within = sym; | |
2905 | symbol_get_tc (sym)->within = ppc_current_csect; | |
2906 | } | |
2907 | #endif | |
2908 | ||
2909 | #ifdef OBJ_ELF | |
2910 | dwarf2_emit_label (sym); | |
2911 | #endif | |
2912 | } | |
6a0c61b7 | 2913 | |
252b5132 RH |
2914 | /* We need to keep a list of fixups. We can't simply generate them as |
2915 | we go, because that would require us to first create the frag, and | |
2916 | that would screw up references to ``.''. */ | |
2917 | ||
2918 | struct ppc_fixup | |
2919 | { | |
2920 | expressionS exp; | |
2921 | int opindex; | |
2922 | bfd_reloc_code_real_type reloc; | |
2923 | }; | |
2924 | ||
2925 | #define MAX_INSN_FIXUPS (5) | |
2926 | ||
0e2779e9 AM |
2927 | /* Return the field size operated on by RELOC, and whether it is |
2928 | pc-relative in PC_RELATIVE. */ | |
2929 | ||
2930 | static unsigned int | |
5b7c81bd | 2931 | fixup_size (bfd_reloc_code_real_type reloc, bool *pc_relative) |
0e2779e9 AM |
2932 | { |
2933 | unsigned int size = 0; | |
5b7c81bd | 2934 | bool pcrel = false; |
0e2779e9 AM |
2935 | |
2936 | switch (reloc) | |
2937 | { | |
2938 | /* This switch statement must handle all BFD_RELOC values | |
2939 | possible in instruction fixups. As is, it handles all | |
2940 | BFD_RELOC values used in bfd/elf64-ppc.c, bfd/elf32-ppc.c, | |
fe49679d | 2941 | bfd/coff-rs6000.c and bfd/coff64-rs6000.c. |
0e2779e9 AM |
2942 | Overkill since data and marker relocs need not be handled |
2943 | here, but this way we can be sure a needed fixup reloc isn't | |
2944 | accidentally omitted. */ | |
2945 | case BFD_RELOC_PPC_EMB_MRKREF: | |
2946 | case BFD_RELOC_VTABLE_ENTRY: | |
2947 | case BFD_RELOC_VTABLE_INHERIT: | |
2948 | break; | |
2949 | ||
2950 | case BFD_RELOC_8: | |
2951 | size = 1; | |
2952 | break; | |
2953 | ||
2954 | case BFD_RELOC_16: | |
2955 | case BFD_RELOC_16_BASEREL: | |
2956 | case BFD_RELOC_16_GOTOFF: | |
2957 | case BFD_RELOC_GPREL16: | |
2958 | case BFD_RELOC_HI16: | |
2959 | case BFD_RELOC_HI16_BASEREL: | |
2960 | case BFD_RELOC_HI16_GOTOFF: | |
2961 | case BFD_RELOC_HI16_PLTOFF: | |
2962 | case BFD_RELOC_HI16_S: | |
2963 | case BFD_RELOC_HI16_S_BASEREL: | |
2964 | case BFD_RELOC_HI16_S_GOTOFF: | |
2965 | case BFD_RELOC_HI16_S_PLTOFF: | |
2966 | case BFD_RELOC_LO16: | |
2967 | case BFD_RELOC_LO16_BASEREL: | |
2968 | case BFD_RELOC_LO16_GOTOFF: | |
2969 | case BFD_RELOC_LO16_PLTOFF: | |
2970 | case BFD_RELOC_PPC64_ADDR16_DS: | |
2971 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
2972 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
5663e321 AM |
2973 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
2974 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
2975 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
2976 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
0e2779e9 AM |
2977 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
2978 | case BFD_RELOC_PPC64_DTPREL16_DS: | |
2979 | case BFD_RELOC_PPC64_DTPREL16_HIGH: | |
2980 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
2981 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
2982 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
2983 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
2984 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
2985 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
2986 | case BFD_RELOC_PPC64_GOT16_DS: | |
2987 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
2988 | case BFD_RELOC_PPC64_HIGHER: | |
2989 | case BFD_RELOC_PPC64_HIGHER_S: | |
2990 | case BFD_RELOC_PPC64_HIGHEST: | |
2991 | case BFD_RELOC_PPC64_HIGHEST_S: | |
2992 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
2993 | case BFD_RELOC_PPC64_PLTGOT16: | |
2994 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
2995 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
2996 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
2997 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
2998 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
2999 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
3000 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
3001 | case BFD_RELOC_PPC64_TOC16_DS: | |
3002 | case BFD_RELOC_PPC64_TOC16_HA: | |
3003 | case BFD_RELOC_PPC64_TOC16_HI: | |
3004 | case BFD_RELOC_PPC64_TOC16_LO: | |
3005 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
3006 | case BFD_RELOC_PPC64_TPREL16_DS: | |
3007 | case BFD_RELOC_PPC64_TPREL16_HIGH: | |
3008 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3009 | case BFD_RELOC_PPC64_TPREL16_HIGHER: | |
3010 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
3011 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
3012 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
3013 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
3014 | #ifdef OBJ_XCOFF | |
3015 | case BFD_RELOC_PPC_BA16: | |
3016 | #endif | |
3017 | case BFD_RELOC_PPC_DTPREL16: | |
3018 | case BFD_RELOC_PPC_DTPREL16_HA: | |
3019 | case BFD_RELOC_PPC_DTPREL16_HI: | |
3020 | case BFD_RELOC_PPC_DTPREL16_LO: | |
3021 | case BFD_RELOC_PPC_EMB_NADDR16: | |
3022 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
3023 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
3024 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
3025 | case BFD_RELOC_PPC_EMB_RELSDA: | |
3026 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
3027 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
3028 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
3029 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
3030 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
3031 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
3032 | case BFD_RELOC_PPC_EMB_SDAI16: | |
3033 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
3034 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
3035 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
3036 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3037 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
3038 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
3039 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
3040 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
3041 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
3042 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
3043 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
3044 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
3045 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3046 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
3047 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
3048 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3049 | case BFD_RELOC_PPC_TOC16: | |
4a403be0 CC |
3050 | case BFD_RELOC_PPC_TOC16_HI: |
3051 | case BFD_RELOC_PPC_TOC16_LO: | |
0e2779e9 AM |
3052 | case BFD_RELOC_PPC_TPREL16: |
3053 | case BFD_RELOC_PPC_TPREL16_HA: | |
3054 | case BFD_RELOC_PPC_TPREL16_HI: | |
3055 | case BFD_RELOC_PPC_TPREL16_LO: | |
3056 | size = 2; | |
3057 | break; | |
3058 | ||
3059 | case BFD_RELOC_16_PCREL: | |
3060 | case BFD_RELOC_HI16_PCREL: | |
3061 | case BFD_RELOC_HI16_S_PCREL: | |
3062 | case BFD_RELOC_LO16_PCREL: | |
3063 | case BFD_RELOC_PPC64_REL16_HIGH: | |
3064 | case BFD_RELOC_PPC64_REL16_HIGHA: | |
3065 | case BFD_RELOC_PPC64_REL16_HIGHER: | |
5663e321 | 3066 | case BFD_RELOC_PPC64_REL16_HIGHER34: |
0e2779e9 | 3067 | case BFD_RELOC_PPC64_REL16_HIGHERA: |
5663e321 | 3068 | case BFD_RELOC_PPC64_REL16_HIGHERA34: |
0e2779e9 | 3069 | case BFD_RELOC_PPC64_REL16_HIGHEST: |
5663e321 | 3070 | case BFD_RELOC_PPC64_REL16_HIGHEST34: |
0e2779e9 | 3071 | case BFD_RELOC_PPC64_REL16_HIGHESTA: |
5663e321 | 3072 | case BFD_RELOC_PPC64_REL16_HIGHESTA34: |
0e2779e9 AM |
3073 | #ifdef OBJ_XCOFF |
3074 | case BFD_RELOC_PPC_B16: | |
3075 | #endif | |
3076 | case BFD_RELOC_PPC_VLE_REL8: | |
3077 | size = 2; | |
5b7c81bd | 3078 | pcrel = true; |
0e2779e9 AM |
3079 | break; |
3080 | ||
0e2779e9 | 3081 | case BFD_RELOC_32: |
0e2779e9 AM |
3082 | case BFD_RELOC_32_PLTOFF: |
3083 | #ifdef OBJ_XCOFF | |
3084 | case BFD_RELOC_CTOR: | |
3085 | #endif | |
3086 | case BFD_RELOC_PPC64_ENTRY: | |
3087 | case BFD_RELOC_PPC_16DX_HA: | |
3088 | #ifndef OBJ_XCOFF | |
3089 | case BFD_RELOC_PPC_BA16: | |
3090 | #endif | |
3091 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
3092 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
3093 | case BFD_RELOC_PPC_BA26: | |
3094 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
3095 | case BFD_RELOC_PPC_EMB_NADDR32: | |
3096 | case BFD_RELOC_PPC_EMB_SDA21: | |
3097 | case BFD_RELOC_PPC_TLS: | |
3098 | case BFD_RELOC_PPC_TLSGD: | |
3099 | case BFD_RELOC_PPC_TLSLD: | |
1b2cb8e2 CC |
3100 | case BFD_RELOC_PPC_TLSLE: |
3101 | case BFD_RELOC_PPC_TLSIE: | |
3102 | case BFD_RELOC_PPC_TLSM: | |
3103 | case BFD_RELOC_PPC_TLSML: | |
0e2779e9 AM |
3104 | case BFD_RELOC_PPC_VLE_HA16A: |
3105 | case BFD_RELOC_PPC_VLE_HA16D: | |
3106 | case BFD_RELOC_PPC_VLE_HI16A: | |
3107 | case BFD_RELOC_PPC_VLE_HI16D: | |
3108 | case BFD_RELOC_PPC_VLE_LO16A: | |
3109 | case BFD_RELOC_PPC_VLE_LO16D: | |
3110 | case BFD_RELOC_PPC_VLE_SDA21: | |
3111 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
3112 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3113 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
3114 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3115 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
3116 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3117 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
c213164a | 3118 | case BFD_RELOC_PPC64_TLS_PCREL: |
0e2779e9 AM |
3119 | case BFD_RELOC_RVA: |
3120 | size = 4; | |
3121 | break; | |
3122 | ||
3123 | case BFD_RELOC_24_PLT_PCREL: | |
3124 | case BFD_RELOC_32_PCREL: | |
3125 | case BFD_RELOC_32_PLT_PCREL: | |
3126 | case BFD_RELOC_PPC64_REL24_NOTOC: | |
3127 | #ifndef OBJ_XCOFF | |
3128 | case BFD_RELOC_PPC_B16: | |
3129 | #endif | |
3130 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3131 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3132 | case BFD_RELOC_PPC_B26: | |
3133 | case BFD_RELOC_PPC_LOCAL24PC: | |
3134 | case BFD_RELOC_PPC_REL16DX_HA: | |
3135 | case BFD_RELOC_PPC_VLE_REL15: | |
3136 | case BFD_RELOC_PPC_VLE_REL24: | |
3137 | size = 4; | |
5b7c81bd | 3138 | pcrel = true; |
0e2779e9 AM |
3139 | break; |
3140 | ||
3141 | #ifndef OBJ_XCOFF | |
3142 | case BFD_RELOC_CTOR: | |
3143 | #endif | |
3144 | case BFD_RELOC_PPC_COPY: | |
3145 | case BFD_RELOC_PPC_DTPMOD: | |
3146 | case BFD_RELOC_PPC_DTPREL: | |
3147 | case BFD_RELOC_PPC_GLOB_DAT: | |
3148 | case BFD_RELOC_PPC_TPREL: | |
3149 | size = ppc_obj64 ? 8 : 4; | |
3150 | break; | |
3151 | ||
3152 | case BFD_RELOC_64: | |
3153 | case BFD_RELOC_64_PLTOFF: | |
3154 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
5663e321 AM |
3155 | case BFD_RELOC_PPC64_D28: |
3156 | case BFD_RELOC_PPC64_D34: | |
3157 | case BFD_RELOC_PPC64_D34_LO: | |
3158 | case BFD_RELOC_PPC64_D34_HI30: | |
3159 | case BFD_RELOC_PPC64_D34_HA30: | |
c213164a AM |
3160 | case BFD_RELOC_PPC64_TPREL34: |
3161 | case BFD_RELOC_PPC64_DTPREL34: | |
0e2779e9 | 3162 | case BFD_RELOC_PPC64_TOC: |
1b2cb8e2 CC |
3163 | case BFD_RELOC_PPC64_TLSGD: |
3164 | case BFD_RELOC_PPC64_TLSLD: | |
3165 | case BFD_RELOC_PPC64_TLSLE: | |
3166 | case BFD_RELOC_PPC64_TLSIE: | |
3167 | case BFD_RELOC_PPC64_TLSM: | |
3168 | case BFD_RELOC_PPC64_TLSML: | |
0e2779e9 AM |
3169 | size = 8; |
3170 | break; | |
3171 | ||
3172 | case BFD_RELOC_64_PCREL: | |
3173 | case BFD_RELOC_64_PLT_PCREL: | |
5663e321 | 3174 | case BFD_RELOC_PPC64_GOT_PCREL34: |
87c69f97 AM |
3175 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3176 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3177 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3178 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 AM |
3179 | case BFD_RELOC_PPC64_PCREL28: |
3180 | case BFD_RELOC_PPC64_PCREL34: | |
3181 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
0e2779e9 | 3182 | size = 8; |
5b7c81bd | 3183 | pcrel = true; |
0e2779e9 AM |
3184 | break; |
3185 | ||
3186 | default: | |
3187 | abort (); | |
3188 | } | |
3189 | ||
3190 | if (ENABLE_CHECKING) | |
3191 | { | |
3192 | reloc_howto_type *reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); | |
3193 | if (reloc_howto != NULL | |
3194 | && (size != bfd_get_reloc_size (reloc_howto) | |
3195 | || pcrel != reloc_howto->pc_relative)) | |
3196 | { | |
3197 | as_bad (_("%s howto doesn't match size/pcrel in gas"), | |
3198 | reloc_howto->name); | |
3199 | abort (); | |
3200 | } | |
3201 | } | |
3202 | *pc_relative = pcrel; | |
3203 | return size; | |
3204 | } | |
3205 | ||
a894d76a | 3206 | #ifdef OBJ_ELF |
160eba93 AM |
3207 | /* If we have parsed a call to __tls_get_addr, parse an argument like |
3208 | (gd0@tlsgd). *STR is the leading parenthesis on entry. If an arg | |
3209 | is successfully parsed, *STR is updated past the trailing | |
3210 | parenthesis and trailing white space, and *TLS_FIX contains the | |
3211 | reloc and arg expression. */ | |
3212 | ||
3213 | static int | |
3214 | parse_tls_arg (char **str, const expressionS *exp, struct ppc_fixup *tls_fix) | |
3215 | { | |
3216 | const char *sym_name = S_GET_NAME (exp->X_add_symbol); | |
3217 | if (sym_name[0] == '.') | |
3218 | ++sym_name; | |
3219 | ||
3220 | tls_fix->reloc = BFD_RELOC_NONE; | |
9e7028aa AM |
3221 | if (strncasecmp (sym_name, "__tls_get_addr", 14) == 0 |
3222 | && (sym_name[14] == 0 | |
3223 | || strcasecmp (sym_name + 14, "_desc") == 0 | |
3224 | || strcasecmp (sym_name + 14, "_opt") == 0)) | |
160eba93 AM |
3225 | { |
3226 | char *hold = input_line_pointer; | |
3227 | input_line_pointer = *str + 1; | |
3228 | expression (&tls_fix->exp); | |
3229 | if (tls_fix->exp.X_op == O_symbol) | |
3230 | { | |
3231 | if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) | |
3232 | tls_fix->reloc = BFD_RELOC_PPC_TLSGD; | |
3233 | else if (strncasecmp (input_line_pointer, "@tlsld)", 7) == 0) | |
3234 | tls_fix->reloc = BFD_RELOC_PPC_TLSLD; | |
3235 | if (tls_fix->reloc != BFD_RELOC_NONE) | |
3236 | { | |
3237 | input_line_pointer += 7; | |
3238 | SKIP_WHITESPACE (); | |
3239 | *str = input_line_pointer; | |
3240 | } | |
3241 | } | |
3242 | input_line_pointer = hold; | |
3243 | } | |
3244 | return tls_fix->reloc != BFD_RELOC_NONE; | |
3245 | } | |
a894d76a | 3246 | #endif |
160eba93 | 3247 | |
252b5132 RH |
3248 | /* This routine is called for each instruction to be assembled. */ |
3249 | ||
3250 | void | |
98027b10 | 3251 | md_assemble (char *str) |
252b5132 RH |
3252 | { |
3253 | char *s; | |
3254 | const struct powerpc_opcode *opcode; | |
0f873fd5 | 3255 | uint64_t insn; |
252b5132 | 3256 | const unsigned char *opindex_ptr; |
252b5132 RH |
3257 | int need_paren; |
3258 | int next_opindex; | |
3259 | struct ppc_fixup fixups[MAX_INSN_FIXUPS]; | |
3260 | int fc; | |
3261 | char *f; | |
a9479dc0 | 3262 | int addr_mask; |
252b5132 | 3263 | int i; |
b9c361e0 | 3264 | unsigned int insn_length; |
252b5132 RH |
3265 | |
3266 | /* Get the opcode. */ | |
3882b010 | 3267 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 RH |
3268 | ; |
3269 | if (*s != '\0') | |
3270 | *s++ = '\0'; | |
3271 | ||
3272 | /* Look up the opcode in the hash table. */ | |
629310ab | 3273 | opcode = (const struct powerpc_opcode *) str_hash_find (ppc_hash, str); |
252b5132 RH |
3274 | if (opcode == (const struct powerpc_opcode *) NULL) |
3275 | { | |
3276 | const struct powerpc_macro *macro; | |
3277 | ||
fe0e921f AM |
3278 | macro = (const struct powerpc_macro *) str_hash_find (ppc_macro_hash, |
3279 | str); | |
252b5132 | 3280 | if (macro == (const struct powerpc_macro *) NULL) |
d6ed37ed | 3281 | as_bad (_("unrecognized opcode: `%s'"), str); |
252b5132 RH |
3282 | else |
3283 | ppc_macro (s, macro); | |
3284 | ||
dd7efa79 | 3285 | ppc_clear_labels (); |
252b5132 RH |
3286 | return; |
3287 | } | |
3288 | ||
3289 | insn = opcode->opcode; | |
86c0f617 AM |
3290 | if (!target_big_endian |
3291 | && ((insn & ~(1 << 26)) == 46u << 26 | |
3292 | || (insn & ~(0xc0 << 1)) == (31u << 26 | 533 << 1))) | |
3293 | { | |
3294 | /* lmw, stmw, lswi, lswx, stswi, stswx */ | |
3295 | as_bad (_("`%s' invalid when little-endian"), str); | |
3296 | ppc_clear_labels (); | |
3297 | return; | |
3298 | } | |
252b5132 RH |
3299 | |
3300 | str = s; | |
3882b010 | 3301 | while (ISSPACE (*str)) |
252b5132 RH |
3302 | ++str; |
3303 | ||
4a403be0 CC |
3304 | #ifdef OBJ_XCOFF |
3305 | /* AIX often generates addis instructions using "addis RT, D(RA)" | |
3306 | format instead of the classic "addis RT, RA, SI" one. | |
3307 | Restore it to the default format as it's the one encoded | |
3308 | in ppc opcodes. */ | |
3309 | if (!strcmp (opcode->name, "addis")) | |
3310 | { | |
3311 | char *rt_e = strchr (str, ','); | |
3312 | if (rt_e != NULL | |
3313 | && strchr (rt_e + 1, ',') == NULL) | |
3314 | { | |
3315 | char *d_e = strchr (rt_e + 1, '('); | |
3316 | if (d_e != NULL && d_e != rt_e + 1) | |
3317 | { | |
3318 | char *ra_e = strrchr (d_e + 1, ')'); | |
3319 | if (ra_e != NULL && ra_e != d_e + 1) | |
3320 | ppc_xcoff_fixup_addis (rt_e, d_e, ra_e); | |
3321 | } | |
3322 | } | |
3323 | } | |
3324 | #endif | |
3325 | ||
252b5132 | 3326 | /* PowerPC operands are just expressions. The only real issue is |
9cf7e568 AM |
3327 | that a few operand types are optional. If an instruction has |
3328 | multiple optional operands and one is omitted, then all optional | |
3329 | operands past the first omitted one must also be omitted. */ | |
3330 | int num_optional_operands = 0; | |
3331 | int num_optional_provided = 0; | |
252b5132 RH |
3332 | |
3333 | /* Gather the operands. */ | |
3334 | need_paren = 0; | |
3335 | next_opindex = 0; | |
3336 | fc = 0; | |
3337 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) | |
3338 | { | |
3339 | const struct powerpc_operand *operand; | |
3340 | const char *errmsg; | |
3341 | char *hold; | |
3342 | expressionS ex; | |
3343 | char endc; | |
3344 | ||
3345 | if (next_opindex == 0) | |
3346 | operand = &powerpc_operands[*opindex_ptr]; | |
3347 | else | |
3348 | { | |
3349 | operand = &powerpc_operands[next_opindex]; | |
3350 | next_opindex = 0; | |
3351 | } | |
252b5132 RH |
3352 | errmsg = NULL; |
3353 | ||
252b5132 | 3354 | /* If this is an optional operand, and we are skipping it, just |
9cf7e568 | 3355 | insert the default value, usually a zero. */ |
252b5132 | 3356 | if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0 |
9cf7e568 | 3357 | && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)) |
252b5132 | 3358 | { |
9cf7e568 AM |
3359 | if (num_optional_operands == 0) |
3360 | { | |
3361 | const unsigned char *optr; | |
3362 | int total = 0; | |
3363 | int provided = 0; | |
3364 | int omitted; | |
3365 | ||
3366 | s = str; | |
3367 | for (optr = opindex_ptr; *optr != 0; optr++) | |
3368 | { | |
3369 | const struct powerpc_operand *op; | |
3370 | op = &powerpc_operands[*optr]; | |
3371 | ||
3372 | ++total; | |
3373 | ||
3374 | if ((op->flags & PPC_OPERAND_OPTIONAL) != 0 | |
3375 | && !((op->flags & PPC_OPERAND_OPTIONAL32) != 0 | |
3376 | && ppc_obj64)) | |
3377 | ++num_optional_operands; | |
3378 | ||
3379 | if (s != NULL && *s != '\0') | |
3380 | { | |
3381 | ++provided; | |
3382 | ||
3383 | /* Look for the start of the next operand. */ | |
3384 | if ((op->flags & PPC_OPERAND_PARENS) != 0) | |
3385 | s = strpbrk (s, "(,"); | |
3386 | else | |
3387 | s = strchr (s, ','); | |
3388 | ||
3389 | if (s != NULL) | |
3390 | ++s; | |
3391 | } | |
3392 | } | |
3393 | omitted = total - provided; | |
3394 | num_optional_provided = num_optional_operands - omitted; | |
3395 | } | |
3396 | if (--num_optional_provided < 0) | |
252b5132 | 3397 | { |
32d71569 AM |
3398 | uint64_t val = ppc_optional_operand_value (operand, insn, ppc_cpu, |
3399 | num_optional_provided); | |
9cf7e568 AM |
3400 | if (operand->insert) |
3401 | { | |
3402 | insn = (*operand->insert) (insn, val, ppc_cpu, &errmsg); | |
3403 | if (errmsg != (const char *) NULL) | |
3404 | as_bad ("%s", errmsg); | |
3405 | } | |
3406 | else if (operand->shift >= 0) | |
3407 | insn |= (val & operand->bitm) << operand->shift; | |
3408 | else | |
3409 | insn |= (val & operand->bitm) >> -operand->shift; | |
3410 | ||
3411 | if ((operand->flags & PPC_OPERAND_NEXT) != 0) | |
3412 | next_opindex = *opindex_ptr + 1; | |
3413 | continue; | |
252b5132 | 3414 | } |
252b5132 RH |
3415 | } |
3416 | ||
3417 | /* Gather the operand. */ | |
3418 | hold = input_line_pointer; | |
3419 | input_line_pointer = str; | |
3420 | ||
fe49679d AM |
3421 | if ((reg_names_p |
3422 | && (((operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
3423 | || ((operand->flags & PPC_OPERAND_CR_REG) != 0))) | |
3424 | || !register_name (&ex)) | |
252b5132 | 3425 | { |
fe49679d | 3426 | char save_lex = lex_type['%']; |
252b5132 | 3427 | |
fe49679d AM |
3428 | if (((operand->flags & PPC_OPERAND_CR_REG) != 0) |
3429 | || (operand->flags & PPC_OPERAND_CR_BIT) != 0) | |
252b5132 | 3430 | { |
5b7c81bd | 3431 | cr_operand = true; |
fe49679d | 3432 | lex_type['%'] |= LEX_BEGIN_NAME; |
252b5132 | 3433 | } |
fe49679d | 3434 | expression (&ex); |
5b7c81bd | 3435 | cr_operand = false; |
fe49679d | 3436 | lex_type['%'] = save_lex; |
252b5132 RH |
3437 | } |
3438 | ||
3439 | str = input_line_pointer; | |
3440 | input_line_pointer = hold; | |
3441 | ||
3442 | if (ex.X_op == O_illegal) | |
3443 | as_bad (_("illegal operand")); | |
3444 | else if (ex.X_op == O_absent) | |
3445 | as_bad (_("missing operand")); | |
3446 | else if (ex.X_op == O_register) | |
3447 | { | |
7e0de605 AM |
3448 | if ((ex.X_md |
3449 | & ~operand->flags | |
3450 | & (PPC_OPERAND_GPR | PPC_OPERAND_FPR | PPC_OPERAND_VR | |
3451 | | PPC_OPERAND_VSR | PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG | |
aa3c112f | 3452 | | PPC_OPERAND_SPR | PPC_OPERAND_GQR | PPC_OPERAND_ACC)) != 0 |
7e0de605 AM |
3453 | && !((ex.X_md & PPC_OPERAND_GPR) != 0 |
3454 | && ex.X_add_number != 0 | |
3455 | && (operand->flags & PPC_OPERAND_GPR_0) != 0)) | |
ece5dcc1 | 3456 | as_warn (_("invalid register expression")); |
4b1c0f7e | 3457 | insn = ppc_insert_operand (insn, operand, ex.X_add_number, |
783de163 | 3458 | ppc_cpu, (char *) NULL, 0); |
252b5132 | 3459 | } |
32d71569 AM |
3460 | else if (ex.X_op == O_constant |
3461 | || (ex.X_op == O_big && ex.X_add_number > 0)) | |
252b5132 | 3462 | { |
32d71569 AM |
3463 | uint64_t val; |
3464 | if (ex.X_op == O_constant) | |
3465 | { | |
3466 | val = ex.X_add_number; | |
3467 | if (sizeof (ex.X_add_number) < sizeof (val) | |
3468 | && (ex.X_add_number < 0) != ex.X_extrabit) | |
3469 | val = val ^ ((addressT) -1 ^ (uint64_t) -1); | |
3470 | } | |
3471 | else | |
3472 | val = generic_bignum_to_int64 (); | |
252b5132 | 3473 | #ifdef OBJ_ELF |
81d4177b | 3474 | /* Allow @HA, @L, @H on constants. */ |
252b5132 | 3475 | char *orig_str = str; |
32d71569 | 3476 | bfd_reloc_code_real_type reloc = ppc_elf_suffix (&str, &ex); |
252b5132 | 3477 | |
32d71569 AM |
3478 | if (ex.X_op == O_constant) |
3479 | { | |
3480 | val = ex.X_add_number; | |
3481 | if (sizeof (ex.X_add_number) < sizeof (val) | |
3482 | && (ex.X_add_number < 0) != ex.X_extrabit) | |
3483 | val = val ^ ((addressT) -1 ^ (uint64_t) -1); | |
3484 | } | |
3485 | if (reloc != BFD_RELOC_NONE) | |
252b5132 RH |
3486 | switch (reloc) |
3487 | { | |
3488 | default: | |
3489 | str = orig_str; | |
3490 | break; | |
3491 | ||
3492 | case BFD_RELOC_LO16: | |
32d71569 | 3493 | val &= 0xffff; |
f9c6b907 | 3494 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3495 | val = SEX16 (val); |
252b5132 RH |
3496 | break; |
3497 | ||
3498 | case BFD_RELOC_HI16: | |
f9c6b907 AM |
3499 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3500 | { | |
3501 | /* PowerPC64 @h is tested for overflow. */ | |
32d71569 | 3502 | val = val >> 16; |
f9c6b907 AM |
3503 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
3504 | { | |
32d71569 AM |
3505 | uint64_t sign = (((uint64_t) -1 >> 16) + 1) >> 1; |
3506 | val = (val ^ sign) - sign; | |
f9c6b907 AM |
3507 | } |
3508 | break; | |
3509 | } | |
2b0f3761 | 3510 | /* Fallthru */ |
f9c6b907 AM |
3511 | |
3512 | case BFD_RELOC_PPC64_ADDR16_HIGH: | |
32d71569 | 3513 | val = PPC_HI (val); |
f9c6b907 | 3514 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3515 | val = SEX16 (val); |
252b5132 RH |
3516 | break; |
3517 | ||
3518 | case BFD_RELOC_HI16_S: | |
f9c6b907 AM |
3519 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
3520 | { | |
3521 | /* PowerPC64 @ha is tested for overflow. */ | |
32d71569 | 3522 | val = (val + 0x8000) >> 16; |
f9c6b907 AM |
3523 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
3524 | { | |
32d71569 AM |
3525 | uint64_t sign = (((uint64_t) -1 >> 16) + 1) >> 1; |
3526 | val = (val ^ sign) - sign; | |
f9c6b907 AM |
3527 | } |
3528 | break; | |
3529 | } | |
2b0f3761 | 3530 | /* Fallthru */ |
f9c6b907 AM |
3531 | |
3532 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
32d71569 | 3533 | val = PPC_HA (val); |
f9c6b907 | 3534 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3535 | val = SEX16 (val); |
0baf16f2 AM |
3536 | break; |
3537 | ||
0baf16f2 | 3538 | case BFD_RELOC_PPC64_HIGHER: |
32d71569 | 3539 | val = PPC_HIGHER (val); |
f9c6b907 | 3540 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3541 | val = SEX16 (val); |
0baf16f2 AM |
3542 | break; |
3543 | ||
3544 | case BFD_RELOC_PPC64_HIGHER_S: | |
32d71569 | 3545 | val = PPC_HIGHERA (val); |
f9c6b907 | 3546 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3547 | val = SEX16 (val); |
252b5132 | 3548 | break; |
0baf16f2 AM |
3549 | |
3550 | case BFD_RELOC_PPC64_HIGHEST: | |
32d71569 | 3551 | val = PPC_HIGHEST (val); |
f9c6b907 | 3552 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3553 | val = SEX16 (val); |
0baf16f2 AM |
3554 | break; |
3555 | ||
3556 | case BFD_RELOC_PPC64_HIGHEST_S: | |
32d71569 | 3557 | val = PPC_HIGHESTA (val); |
f9c6b907 | 3558 | if ((operand->flags & PPC_OPERAND_SIGNED) != 0) |
32d71569 | 3559 | val = SEX16 (val); |
0baf16f2 | 3560 | break; |
252b5132 | 3561 | } |
0baf16f2 | 3562 | #endif /* OBJ_ELF */ |
32d71569 | 3563 | insn = ppc_insert_operand (insn, operand, val, ppc_cpu, NULL, 0); |
252b5132 | 3564 | } |
727fc41e | 3565 | else |
252b5132 | 3566 | { |
62ebcb5c | 3567 | bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; |
3b8b57a9 | 3568 | #ifdef OBJ_ELF |
160eba93 AM |
3569 | /* Look for a __tls_get_addr arg using the insane old syntax. */ |
3570 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3571 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
cdba85ec | 3572 | { |
160eba93 AM |
3573 | fixups[fc].opindex = *opindex_ptr; |
3574 | ++fc; | |
252b5132 RH |
3575 | } |
3576 | ||
62ebcb5c | 3577 | if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) |
0baf16f2 | 3578 | { |
b9c361e0 JL |
3579 | /* If VLE-mode convert LO/HI/HA relocations. */ |
3580 | if (opcode->flags & PPC_OPCODE_VLE) | |
3581 | { | |
0f873fd5 | 3582 | uint64_t tmp_insn = insn & opcode->mask; |
3739860c | 3583 | |
08dc996f | 3584 | int use_a_reloc = (tmp_insn == E_OR2I_INSN |
b9c361e0 JL |
3585 | || tmp_insn == E_AND2I_DOT_INSN |
3586 | || tmp_insn == E_OR2IS_INSN | |
bb6bf75e | 3587 | || tmp_insn == E_LI_INSN |
b9c361e0 JL |
3588 | || tmp_insn == E_LIS_INSN |
3589 | || tmp_insn == E_AND2IS_DOT_INSN); | |
3590 | ||
3591 | ||
08dc996f | 3592 | int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN |
b9c361e0 JL |
3593 | || tmp_insn == E_ADD2IS_INSN |
3594 | || tmp_insn == E_CMP16I_INSN | |
3595 | || tmp_insn == E_MULL2I_INSN | |
3596 | || tmp_insn == E_CMPL16I_INSN | |
3597 | || tmp_insn == E_CMPH16I_INSN | |
3598 | || tmp_insn == E_CMPHL16I_INSN); | |
3599 | ||
3600 | switch (reloc) | |
3601 | { | |
3602 | default: | |
3603 | break; | |
3604 | ||
3605 | case BFD_RELOC_PPC_EMB_SDA21: | |
3606 | reloc = BFD_RELOC_PPC_VLE_SDA21; | |
3607 | break; | |
3608 | ||
3609 | case BFD_RELOC_LO16: | |
3610 | if (use_d_reloc) | |
3611 | reloc = BFD_RELOC_PPC_VLE_LO16D; | |
3612 | else if (use_a_reloc) | |
3613 | reloc = BFD_RELOC_PPC_VLE_LO16A; | |
3614 | break; | |
3615 | ||
3616 | case BFD_RELOC_HI16: | |
3617 | if (use_d_reloc) | |
3618 | reloc = BFD_RELOC_PPC_VLE_HI16D; | |
3619 | else if (use_a_reloc) | |
3620 | reloc = BFD_RELOC_PPC_VLE_HI16A; | |
3621 | break; | |
3739860c | 3622 | |
b9c361e0 JL |
3623 | case BFD_RELOC_HI16_S: |
3624 | if (use_d_reloc) | |
3625 | reloc = BFD_RELOC_PPC_VLE_HA16D; | |
3626 | else if (use_a_reloc) | |
3627 | reloc = BFD_RELOC_PPC_VLE_HA16A; | |
3628 | break; | |
3629 | ||
3630 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
3631 | if (use_d_reloc) | |
3632 | reloc = BFD_RELOC_PPC_VLE_SDAREL_LO16D; | |
3633 | break; | |
3634 | ||
3635 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
3636 | if (use_d_reloc) | |
3637 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HI16D; | |
3638 | break; | |
3639 | ||
3640 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
3641 | if (use_d_reloc) | |
3642 | reloc = BFD_RELOC_PPC_VLE_SDAREL_HA16D; | |
3643 | break; | |
3644 | } | |
3645 | } | |
bb6bf75e AM |
3646 | |
3647 | /* TLS and other tweaks. */ | |
3648 | switch (reloc) | |
3649 | { | |
3650 | default: | |
3651 | break; | |
3652 | ||
3653 | case BFD_RELOC_PPC_TLS: | |
c213164a | 3654 | case BFD_RELOC_PPC64_TLS_PCREL: |
bb6bf75e AM |
3655 | if (!_bfd_elf_ppc_at_tls_transform (opcode->opcode, 0)) |
3656 | as_bad (_("@tls may not be used with \"%s\" operands"), | |
3657 | opcode->name); | |
3658 | else if (operand->shift != 11) | |
3659 | as_bad (_("@tls may only be used in last operand")); | |
3660 | else | |
3661 | insn = ppc_insert_operand (insn, operand, | |
3662 | ppc_obj64 ? 13 : 2, | |
3663 | ppc_cpu, (char *) NULL, 0); | |
3664 | break; | |
3665 | ||
3666 | /* We'll only use the 32 (or 64) bit form of these relocations | |
c213164a | 3667 | in constants. Instructions get the 16 or 34 bit form. */ |
bb6bf75e | 3668 | case BFD_RELOC_PPC_DTPREL: |
c213164a AM |
3669 | if (operand->bitm == 0x3ffffffffULL) |
3670 | reloc = BFD_RELOC_PPC64_DTPREL34; | |
3671 | else | |
3672 | reloc = BFD_RELOC_PPC_DTPREL16; | |
bb6bf75e AM |
3673 | break; |
3674 | ||
3675 | case BFD_RELOC_PPC_TPREL: | |
c213164a AM |
3676 | if (operand->bitm == 0x3ffffffffULL) |
3677 | reloc = BFD_RELOC_PPC64_TPREL34; | |
3678 | else | |
3679 | reloc = BFD_RELOC_PPC_TPREL16; | |
bb6bf75e AM |
3680 | break; |
3681 | ||
5663e321 AM |
3682 | case BFD_RELOC_PPC64_PCREL34: |
3683 | if (operand->bitm == 0xfffffffULL) | |
3684 | { | |
3685 | reloc = BFD_RELOC_PPC64_PCREL28; | |
3686 | break; | |
3687 | } | |
3688 | /* Fall through. */ | |
3689 | case BFD_RELOC_PPC64_GOT_PCREL34: | |
3690 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
87c69f97 AM |
3691 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
3692 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
3693 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
3694 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
5663e321 | 3695 | if (operand->bitm != 0x3ffffffffULL |
bb6bf75e | 3696 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) |
5663e321 AM |
3697 | as_warn (_("%s unsupported on this instruction"), "@pcrel"); |
3698 | break; | |
3699 | ||
3700 | case BFD_RELOC_LO16: | |
3701 | if (operand->bitm == 0x3ffffffffULL | |
3702 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3703 | reloc = BFD_RELOC_PPC64_D34_LO; | |
3704 | else if ((operand->bitm | 0xf) != 0xffff | |
3705 | || operand->shift != 0 | |
3706 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3707 | as_warn (_("%s unsupported on this instruction"), "@l"); |
3708 | break; | |
3709 | ||
3710 | case BFD_RELOC_HI16: | |
5663e321 AM |
3711 | if (operand->bitm == 0x3ffffffffULL |
3712 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3713 | reloc = BFD_RELOC_PPC64_D34_HI30; | |
3714 | else if (operand->bitm != 0xffff | |
3715 | || operand->shift != 0 | |
3716 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
bb6bf75e AM |
3717 | as_warn (_("%s unsupported on this instruction"), "@h"); |
3718 | break; | |
3719 | ||
3720 | case BFD_RELOC_HI16_S: | |
5663e321 AM |
3721 | if (operand->bitm == 0x3ffffffffULL |
3722 | && (operand->flags & PPC_OPERAND_NEGATIVE) == 0) | |
3723 | reloc = BFD_RELOC_PPC64_D34_HA30; | |
3724 | else if (operand->bitm == 0xffff | |
3725 | && operand->shift == (int) PPC_OPSHIFT_INV | |
3726 | && opcode->opcode == (19 << 26) + (2 << 1)) | |
bb6bf75e AM |
3727 | /* addpcis. */ |
3728 | reloc = BFD_RELOC_PPC_16DX_HA; | |
3729 | else if (operand->bitm != 0xffff | |
3730 | || operand->shift != 0 | |
3731 | || (operand->flags & PPC_OPERAND_NEGATIVE) != 0) | |
3732 | as_warn (_("%s unsupported on this instruction"), "@ha"); | |
3733 | } | |
0baf16f2 | 3734 | } |
3b8b57a9 | 3735 | #endif /* OBJ_ELF */ |
4a403be0 CC |
3736 | #ifdef OBJ_XCOFF |
3737 | reloc = ppc_xcoff_suffix (&str); | |
3738 | #endif /* OBJ_XCOFF */ | |
3b8b57a9 | 3739 | |
62ebcb5c | 3740 | if (reloc != BFD_RELOC_NONE) |
3b8b57a9 AM |
3741 | ; |
3742 | /* Determine a BFD reloc value based on the operand information. | |
3743 | We are only prepared to turn a few of the operands into | |
3744 | relocs. */ | |
a0593ad9 AM |
3745 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3746 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3747 | && operand->bitm == 0x3fffffc |
3748 | && operand->shift == 0) | |
3749 | reloc = BFD_RELOC_PPC_B26; | |
a0593ad9 AM |
3750 | else if ((operand->flags & (PPC_OPERAND_RELATIVE |
3751 | | PPC_OPERAND_ABSOLUTE)) != 0 | |
3b8b57a9 AM |
3752 | && operand->bitm == 0xfffc |
3753 | && operand->shift == 0) | |
3754 | reloc = BFD_RELOC_PPC_B16; | |
3755 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3756 | && operand->bitm == 0x1fe | |
3757 | && operand->shift == -1) | |
3758 | reloc = BFD_RELOC_PPC_VLE_REL8; | |
3759 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3760 | && operand->bitm == 0xfffe | |
3761 | && operand->shift == 0) | |
3762 | reloc = BFD_RELOC_PPC_VLE_REL15; | |
3763 | else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 | |
3764 | && operand->bitm == 0x1fffffe | |
3765 | && operand->shift == 0) | |
3766 | reloc = BFD_RELOC_PPC_VLE_REL24; | |
a0593ad9 | 3767 | else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 |
3b8b57a9 AM |
3768 | && (operand->bitm & 0xfff0) == 0xfff0 |
3769 | && operand->shift == 0) | |
3770 | { | |
f50c47f1 | 3771 | reloc = BFD_RELOC_16; |
3e60bf4d | 3772 | #if defined OBJ_XCOFF || defined OBJ_ELF |
f50c47f1 | 3773 | /* Note: the symbol may be not yet defined. */ |
a0593ad9 AM |
3774 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
3775 | && ppc_is_toc_sym (ex.X_add_symbol)) | |
3e60bf4d AM |
3776 | { |
3777 | reloc = BFD_RELOC_PPC_TOC16; | |
3778 | #ifdef OBJ_ELF | |
3779 | as_warn (_("assuming %s on symbol"), | |
3780 | ppc_obj64 ? "@toc" : "@xgot"); | |
3781 | #endif | |
3782 | } | |
3b8b57a9 | 3783 | #endif |
3b8b57a9 | 3784 | } |
5663e321 AM |
3785 | else if (operand->bitm == 0x3ffffffffULL) |
3786 | reloc = BFD_RELOC_PPC64_D34; | |
3787 | else if (operand->bitm == 0xfffffffULL) | |
3788 | reloc = BFD_RELOC_PPC64_D28; | |
a0593ad9 AM |
3789 | |
3790 | /* For the absolute forms of branches, convert the PC | |
3791 | relative form back into the absolute. */ | |
3792 | if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) | |
3793 | { | |
3794 | switch (reloc) | |
3795 | { | |
3796 | case BFD_RELOC_PPC_B26: | |
3797 | reloc = BFD_RELOC_PPC_BA26; | |
3798 | break; | |
3799 | case BFD_RELOC_PPC_B16: | |
3800 | reloc = BFD_RELOC_PPC_BA16; | |
3801 | break; | |
3802 | #ifdef OBJ_ELF | |
3803 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
3804 | reloc = BFD_RELOC_PPC_BA16_BRTAKEN; | |
3805 | break; | |
3806 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
3807 | reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; | |
3808 | break; | |
3809 | #endif | |
3810 | default: | |
3811 | break; | |
3812 | } | |
3813 | } | |
3814 | ||
3815 | #ifdef OBJ_ELF | |
3816 | switch (reloc) | |
3817 | { | |
3818 | case BFD_RELOC_PPC_TOC16: | |
3819 | toc_reloc_types |= has_small_toc_reloc; | |
3820 | break; | |
3821 | case BFD_RELOC_PPC64_TOC16_LO: | |
3822 | case BFD_RELOC_PPC64_TOC16_HI: | |
3823 | case BFD_RELOC_PPC64_TOC16_HA: | |
3824 | toc_reloc_types |= has_large_toc_reloc; | |
3825 | break; | |
3826 | default: | |
3827 | break; | |
3828 | } | |
3829 | ||
3830 | if (ppc_obj64 | |
3831 | && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) | |
3832 | { | |
3833 | switch (reloc) | |
3834 | { | |
3835 | case BFD_RELOC_16: | |
3836 | reloc = BFD_RELOC_PPC64_ADDR16_DS; | |
3837 | break; | |
5663e321 | 3838 | |
a0593ad9 AM |
3839 | case BFD_RELOC_LO16: |
3840 | reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; | |
3841 | break; | |
5663e321 | 3842 | |
a0593ad9 AM |
3843 | case BFD_RELOC_16_GOTOFF: |
3844 | reloc = BFD_RELOC_PPC64_GOT16_DS; | |
3845 | break; | |
5663e321 | 3846 | |
a0593ad9 AM |
3847 | case BFD_RELOC_LO16_GOTOFF: |
3848 | reloc = BFD_RELOC_PPC64_GOT16_LO_DS; | |
3849 | break; | |
5663e321 | 3850 | |
a0593ad9 AM |
3851 | case BFD_RELOC_LO16_PLTOFF: |
3852 | reloc = BFD_RELOC_PPC64_PLT16_LO_DS; | |
3853 | break; | |
5663e321 | 3854 | |
a0593ad9 AM |
3855 | case BFD_RELOC_16_BASEREL: |
3856 | reloc = BFD_RELOC_PPC64_SECTOFF_DS; | |
3857 | break; | |
5663e321 | 3858 | |
a0593ad9 AM |
3859 | case BFD_RELOC_LO16_BASEREL: |
3860 | reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; | |
3861 | break; | |
5663e321 | 3862 | |
a0593ad9 AM |
3863 | case BFD_RELOC_PPC_TOC16: |
3864 | reloc = BFD_RELOC_PPC64_TOC16_DS; | |
3865 | break; | |
5663e321 | 3866 | |
a0593ad9 AM |
3867 | case BFD_RELOC_PPC64_TOC16_LO: |
3868 | reloc = BFD_RELOC_PPC64_TOC16_LO_DS; | |
3869 | break; | |
5663e321 | 3870 | |
a0593ad9 AM |
3871 | case BFD_RELOC_PPC64_PLTGOT16: |
3872 | reloc = BFD_RELOC_PPC64_PLTGOT16_DS; | |
3873 | break; | |
5663e321 | 3874 | |
a0593ad9 AM |
3875 | case BFD_RELOC_PPC64_PLTGOT16_LO: |
3876 | reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; | |
3877 | break; | |
5663e321 | 3878 | |
a0593ad9 AM |
3879 | case BFD_RELOC_PPC_DTPREL16: |
3880 | reloc = BFD_RELOC_PPC64_DTPREL16_DS; | |
3881 | break; | |
5663e321 | 3882 | |
a0593ad9 AM |
3883 | case BFD_RELOC_PPC_DTPREL16_LO: |
3884 | reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; | |
3885 | break; | |
5663e321 | 3886 | |
a0593ad9 AM |
3887 | case BFD_RELOC_PPC_TPREL16: |
3888 | reloc = BFD_RELOC_PPC64_TPREL16_DS; | |
3889 | break; | |
5663e321 | 3890 | |
a0593ad9 AM |
3891 | case BFD_RELOC_PPC_TPREL16_LO: |
3892 | reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; | |
3893 | break; | |
5663e321 | 3894 | |
a0593ad9 AM |
3895 | case BFD_RELOC_PPC_GOT_DTPREL16: |
3896 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
3897 | case BFD_RELOC_PPC_GOT_TPREL16: | |
3898 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
3899 | break; | |
5663e321 | 3900 | |
a0593ad9 AM |
3901 | default: |
3902 | as_bad (_("unsupported relocation for DS offset field")); | |
3903 | break; | |
3904 | } | |
3905 | } | |
160eba93 AM |
3906 | |
3907 | /* Look for a __tls_get_addr arg after any __tls_get_addr | |
3908 | modifiers like @plt. This fixup must be emitted before | |
3909 | the usual call fixup. */ | |
3910 | if (ex.X_op == O_symbol && *str == '(' && fc < MAX_INSN_FIXUPS | |
3911 | && parse_tls_arg (&str, &ex, &fixups[fc])) | |
3912 | { | |
3913 | fixups[fc].opindex = *opindex_ptr; | |
3914 | ++fc; | |
3915 | } | |
a0593ad9 | 3916 | #endif |
0baf16f2 | 3917 | |
252b5132 RH |
3918 | /* We need to generate a fixup for this expression. */ |
3919 | if (fc >= MAX_INSN_FIXUPS) | |
3920 | as_fatal (_("too many fixups")); | |
3921 | fixups[fc].exp = ex; | |
727fc41e | 3922 | fixups[fc].opindex = *opindex_ptr; |
252b5132 RH |
3923 | fixups[fc].reloc = reloc; |
3924 | ++fc; | |
3925 | } | |
252b5132 RH |
3926 | |
3927 | if (need_paren) | |
3928 | { | |
3929 | endc = ')'; | |
3930 | need_paren = 0; | |
c3d65c1c BE |
3931 | /* If expecting more operands, then we want to see "),". */ |
3932 | if (*str == endc && opindex_ptr[1] != 0) | |
3933 | { | |
3934 | do | |
3935 | ++str; | |
3936 | while (ISSPACE (*str)); | |
3937 | endc = ','; | |
3938 | } | |
252b5132 RH |
3939 | } |
3940 | else if ((operand->flags & PPC_OPERAND_PARENS) != 0) | |
9cf7e568 | 3941 | endc = '('; |
252b5132 RH |
3942 | else |
3943 | endc = ','; | |
3944 | ||
3945 | /* The call to expression should have advanced str past any | |
3946 | whitespace. */ | |
9cf7e568 | 3947 | if (*str == endc) |
252b5132 | 3948 | { |
9cf7e568 AM |
3949 | ++str; |
3950 | if (endc == '(') | |
3951 | need_paren = 1; | |
3952 | } | |
3953 | else if (*str != '\0') | |
3954 | { | |
3955 | as_bad (_("syntax error; found `%c', expected `%c'"), *str, endc); | |
3956 | break; | |
3957 | } | |
3958 | else if (endc == ')') | |
3959 | { | |
3960 | as_bad (_("syntax error; end of line, expected `%c'"), endc); | |
252b5132 RH |
3961 | break; |
3962 | } | |
252b5132 RH |
3963 | } |
3964 | ||
3882b010 | 3965 | while (ISSPACE (*str)) |
252b5132 RH |
3966 | ++str; |
3967 | ||
3968 | if (*str != '\0') | |
3969 | as_bad (_("junk at end of line: `%s'"), str); | |
3970 | ||
dc1d03fc | 3971 | #ifdef OBJ_ELF |
b9c361e0 | 3972 | /* Do we need/want an APUinfo section? */ |
4faf939a JM |
3973 | if ((ppc_cpu & (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_VLE)) != 0 |
3974 | && !ppc_obj64) | |
6a0c61b7 EZ |
3975 | { |
3976 | /* These are all version "1". */ | |
3977 | if (opcode->flags & PPC_OPCODE_SPE) | |
b34976b6 | 3978 | ppc_apuinfo_section_add (PPC_APUINFO_SPE, 1); |
6a0c61b7 | 3979 | if (opcode->flags & PPC_OPCODE_ISEL) |
b34976b6 | 3980 | ppc_apuinfo_section_add (PPC_APUINFO_ISEL, 1); |
6a0c61b7 | 3981 | if (opcode->flags & PPC_OPCODE_EFS) |
b34976b6 | 3982 | ppc_apuinfo_section_add (PPC_APUINFO_EFS, 1); |
6a0c61b7 | 3983 | if (opcode->flags & PPC_OPCODE_BRLOCK) |
b34976b6 | 3984 | ppc_apuinfo_section_add (PPC_APUINFO_BRLOCK, 1); |
6a0c61b7 | 3985 | if (opcode->flags & PPC_OPCODE_PMR) |
b34976b6 | 3986 | ppc_apuinfo_section_add (PPC_APUINFO_PMR, 1); |
6a0c61b7 | 3987 | if (opcode->flags & PPC_OPCODE_CACHELCK) |
b34976b6 | 3988 | ppc_apuinfo_section_add (PPC_APUINFO_CACHELCK, 1); |
6a0c61b7 | 3989 | if (opcode->flags & PPC_OPCODE_RFMCI) |
b34976b6 | 3990 | ppc_apuinfo_section_add (PPC_APUINFO_RFMCI, 1); |
fbd94057 MR |
3991 | /* Only set the VLE flag if the instruction has been pulled via |
3992 | the VLE instruction set. This way the flag is guaranteed to | |
3993 | be set for VLE-only instructions or for VLE-only processors, | |
3994 | however it'll remain clear for dual-mode instructions on | |
3995 | dual-mode and, more importantly, standard-mode processors. */ | |
3996 | if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE) | |
f7d69005 AM |
3997 | { |
3998 | ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1); | |
3999 | if (elf_section_data (now_seg) != NULL) | |
4000 | elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE; | |
4001 | } | |
6a0c61b7 | 4002 | } |
dc1d03fc | 4003 | #endif |
6a0c61b7 | 4004 | |
252b5132 | 4005 | /* Write out the instruction. */ |
a9479dc0 AM |
4006 | |
4007 | addr_mask = 3; | |
f7d69005 | 4008 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) |
a9479dc0 AM |
4009 | /* All instructions can start on a 2 byte boundary for VLE. */ |
4010 | addr_mask = 1; | |
4011 | ||
4012 | if (frag_now->insn_addr != addr_mask) | |
b9c361e0 | 4013 | { |
a9479dc0 AM |
4014 | /* Don't emit instructions to a frag started for data, or for a |
4015 | CPU differing in VLE mode. Data is allowed to be misaligned, | |
4016 | and it's possible to start a new frag in the middle of | |
4017 | misaligned data. */ | |
4018 | frag_wane (frag_now); | |
4019 | frag_new (0); | |
b9c361e0 | 4020 | } |
a9479dc0 AM |
4021 | |
4022 | /* Check that insns within the frag are aligned. ppc_frag_check | |
4023 | will ensure that the frag start address is aligned. */ | |
4024 | if ((frag_now_fix () & addr_mask) != 0) | |
4025 | as_bad (_("instruction address is not a multiple of %d"), addr_mask + 1); | |
4026 | ||
dd7efa79 | 4027 | /* Differentiate between two, four, and eight byte insns. */ |
a9479dc0 AM |
4028 | insn_length = 4; |
4029 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && PPC_OP_SE_VLE (insn)) | |
4030 | insn_length = 2; | |
7c1f4227 | 4031 | else if ((opcode->flags & PPC_OPCODE_POWER10) != 0 |
dd7efa79 PB |
4032 | && PPC_PREFIX_P (insn)) |
4033 | { | |
4034 | struct insn_label_list *l; | |
4035 | ||
4036 | insn_length = 8; | |
4037 | ||
4038 | /* 8-byte prefix instructions are not allowed to cross 64-byte | |
4039 | boundaries. */ | |
4040 | frag_align_code (6, 4); | |
4041 | record_alignment (now_seg, 6); | |
4042 | ||
4043 | /* Update "dot" in any expressions used by this instruction, and | |
4044 | a label attached to the instruction. By "attached" we mean | |
4045 | on the same source line as the instruction and without any | |
4046 | intervening semicolons. */ | |
4047 | dot_value = frag_now_fix (); | |
4048 | dot_frag = frag_now; | |
4049 | for (l = insn_labels; l != NULL; l = l->next) | |
4050 | { | |
4051 | symbol_set_frag (l->label, dot_frag); | |
4052 | S_SET_VALUE (l->label, dot_value); | |
4053 | } | |
4054 | } | |
4055 | ||
4056 | ppc_clear_labels (); | |
a9479dc0 | 4057 | |
b9c361e0 | 4058 | f = frag_more (insn_length); |
a9479dc0 | 4059 | frag_now->insn_addr = addr_mask; |
dd7efa79 PB |
4060 | |
4061 | /* The prefix part of an 8-byte instruction always occupies the lower | |
4062 | addressed word in a doubleword, regardless of endianness. */ | |
15a32af5 AM |
4063 | if (insn_length == 8 |
4064 | && (sizeof (insn) > sizeof (valueT) || !target_big_endian)) | |
dd7efa79 PB |
4065 | { |
4066 | md_number_to_chars (f, PPC_GET_PREFIX (insn), 4); | |
4067 | md_number_to_chars (f + 4, PPC_GET_SUFFIX (insn), 4); | |
4068 | } | |
4069 | else | |
4070 | md_number_to_chars (f, insn, insn_length); | |
4071 | ||
bf7279d5 AM |
4072 | last_insn = insn; |
4073 | last_seg = now_seg; | |
4074 | last_subseg = now_subseg; | |
252b5132 | 4075 | |
5d6f4f16 | 4076 | #ifdef OBJ_ELF |
b9c361e0 | 4077 | dwarf2_emit_insn (insn_length); |
5d6f4f16 GK |
4078 | #endif |
4079 | ||
3b8b57a9 | 4080 | /* Create any fixups. */ |
252b5132 RH |
4081 | for (i = 0; i < fc; i++) |
4082 | { | |
3b8b57a9 | 4083 | fixS *fixP; |
62ebcb5c | 4084 | if (fixups[i].reloc != BFD_RELOC_NONE) |
252b5132 | 4085 | { |
5b7c81bd | 4086 | bool pcrel; |
0e2779e9 AM |
4087 | unsigned int size = fixup_size (fixups[i].reloc, &pcrel); |
4088 | int offset = target_big_endian ? (insn_length - size) : 0; | |
252b5132 | 4089 | |
99a814a1 AM |
4090 | fixP = fix_new_exp (frag_now, |
4091 | f - frag_now->fr_literal + offset, | |
4092 | size, | |
4093 | &fixups[i].exp, | |
0e2779e9 | 4094 | pcrel, |
252b5132 | 4095 | fixups[i].reloc); |
252b5132 RH |
4096 | } |
4097 | else | |
727fc41e AM |
4098 | { |
4099 | const struct powerpc_operand *operand; | |
4100 | ||
4101 | operand = &powerpc_operands[fixups[i].opindex]; | |
3b8b57a9 AM |
4102 | fixP = fix_new_exp (frag_now, |
4103 | f - frag_now->fr_literal, | |
4104 | insn_length, | |
4105 | &fixups[i].exp, | |
4106 | (operand->flags & PPC_OPERAND_RELATIVE) != 0, | |
62ebcb5c | 4107 | BFD_RELOC_NONE); |
727fc41e | 4108 | } |
3b8b57a9 | 4109 | fixP->fx_pcrel_adjust = fixups[i].opindex; |
252b5132 RH |
4110 | } |
4111 | } | |
4112 | ||
4113 | /* Handle a macro. Gather all the operands, transform them as | |
4114 | described by the macro, and call md_assemble recursively. All the | |
4115 | operands are separated by commas; we don't accept parentheses | |
4116 | around operands here. */ | |
4117 | ||
4118 | static void | |
98027b10 | 4119 | ppc_macro (char *str, const struct powerpc_macro *macro) |
252b5132 RH |
4120 | { |
4121 | char *operands[10]; | |
4122 | unsigned int count; | |
4123 | char *s; | |
4124 | unsigned int len; | |
4125 | const char *format; | |
db557034 | 4126 | unsigned int arg; |
252b5132 RH |
4127 | char *send; |
4128 | char *complete; | |
4129 | ||
4130 | /* Gather the users operands into the operands array. */ | |
4131 | count = 0; | |
4132 | s = str; | |
4133 | while (1) | |
4134 | { | |
4135 | if (count >= sizeof operands / sizeof operands[0]) | |
4136 | break; | |
4137 | operands[count++] = s; | |
4138 | s = strchr (s, ','); | |
4139 | if (s == (char *) NULL) | |
4140 | break; | |
4141 | *s++ = '\0'; | |
81d4177b | 4142 | } |
252b5132 RH |
4143 | |
4144 | if (count != macro->operands) | |
4145 | { | |
4146 | as_bad (_("wrong number of operands")); | |
4147 | return; | |
4148 | } | |
4149 | ||
4150 | /* Work out how large the string must be (the size is unbounded | |
4151 | because it includes user input). */ | |
4152 | len = 0; | |
4153 | format = macro->format; | |
4154 | while (*format != '\0') | |
4155 | { | |
4156 | if (*format != '%') | |
4157 | { | |
4158 | ++len; | |
4159 | ++format; | |
4160 | } | |
4161 | else | |
4162 | { | |
4163 | arg = strtol (format + 1, &send, 10); | |
db557034 | 4164 | know (send != format && arg < count); |
252b5132 RH |
4165 | len += strlen (operands[arg]); |
4166 | format = send; | |
4167 | } | |
4168 | } | |
4169 | ||
4170 | /* Put the string together. */ | |
325801bd | 4171 | complete = s = XNEWVEC (char, len + 1); |
252b5132 RH |
4172 | format = macro->format; |
4173 | while (*format != '\0') | |
4174 | { | |
4175 | if (*format != '%') | |
4176 | *s++ = *format++; | |
4177 | else | |
4178 | { | |
4179 | arg = strtol (format + 1, &send, 10); | |
4180 | strcpy (s, operands[arg]); | |
4181 | s += strlen (s); | |
4182 | format = send; | |
4183 | } | |
4184 | } | |
4185 | *s = '\0'; | |
4186 | ||
4187 | /* Assemble the constructed instruction. */ | |
4188 | md_assemble (complete); | |
e1fa0163 | 4189 | free (complete); |
81d4177b | 4190 | } |
252b5132 RH |
4191 | \f |
4192 | #ifdef OBJ_ELF | |
18ae9cc1 | 4193 | /* For ELF, add support for SHT_ORDERED. */ |
252b5132 RH |
4194 | |
4195 | int | |
98027b10 | 4196 | ppc_section_type (char *str, size_t len) |
252b5132 | 4197 | { |
d34049e8 | 4198 | if (len == 7 && startswith (str, "ordered")) |
9de8d8f1 | 4199 | return SHT_ORDERED; |
252b5132 | 4200 | |
9de8d8f1 | 4201 | return -1; |
252b5132 RH |
4202 | } |
4203 | ||
4204 | int | |
1239de13 | 4205 | ppc_section_flags (flagword flags, bfd_vma attr ATTRIBUTE_UNUSED, int type) |
252b5132 RH |
4206 | { |
4207 | if (type == SHT_ORDERED) | |
4208 | flags |= SEC_ALLOC | SEC_LOAD | SEC_SORT_ENTRIES; | |
4209 | ||
252b5132 RH |
4210 | return flags; |
4211 | } | |
83eef883 AFB |
4212 | |
4213 | bfd_vma | |
4214 | ppc_elf_section_letter (int letter, const char **ptrmsg) | |
4215 | { | |
4216 | if (letter == 'v') | |
4217 | return SHF_PPC_VLE; | |
4218 | ||
4219 | *ptrmsg = _("bad .section directive: want a,e,v,w,x,M,S,G,T in string"); | |
4220 | return -1; | |
4221 | } | |
252b5132 RH |
4222 | #endif /* OBJ_ELF */ |
4223 | ||
4224 | \f | |
4225 | /* Pseudo-op handling. */ | |
4226 | ||
4227 | /* The .byte pseudo-op. This is similar to the normal .byte | |
4228 | pseudo-op, but it can also take a single ASCII string. */ | |
4229 | ||
4230 | static void | |
98027b10 | 4231 | ppc_byte (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 4232 | { |
bf7279d5 AM |
4233 | int count = 0; |
4234 | ||
252b5132 RH |
4235 | if (*input_line_pointer != '\"') |
4236 | { | |
4237 | cons (1); | |
4238 | return; | |
4239 | } | |
4240 | ||
4241 | /* Gather characters. A real double quote is doubled. Unusual | |
4242 | characters are not permitted. */ | |
4243 | ++input_line_pointer; | |
4244 | while (1) | |
4245 | { | |
4246 | char c; | |
4247 | ||
4248 | c = *input_line_pointer++; | |
4249 | ||
4250 | if (c == '\"') | |
4251 | { | |
4252 | if (*input_line_pointer != '\"') | |
4253 | break; | |
4254 | ++input_line_pointer; | |
4255 | } | |
4256 | ||
4257 | FRAG_APPEND_1_CHAR (c); | |
bf7279d5 | 4258 | ++count; |
252b5132 RH |
4259 | } |
4260 | ||
bf7279d5 AM |
4261 | if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) |
4262 | as_warn (_("data in executable section")); | |
252b5132 RH |
4263 | demand_empty_rest_of_line (); |
4264 | } | |
4265 | \f | |
4266 | #ifdef OBJ_XCOFF | |
4267 | ||
4268 | /* XCOFF specific pseudo-op handling. */ | |
4269 | ||
4270 | /* This is set if we are creating a .stabx symbol, since we don't want | |
4271 | to handle symbol suffixes for such symbols. */ | |
5b7c81bd | 4272 | static bool ppc_stab_symbol; |
252b5132 RH |
4273 | |
4274 | /* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common | |
4275 | symbols in the .bss segment as though they were local common | |
67c1ffbe | 4276 | symbols, and uses a different smclas. The native Aix 4.3.3 assembler |
1b2cb8e2 CC |
4277 | aligns .comm and .lcomm to 4 bytes. |
4278 | Symbols having a XMC_UL storage class are uninialized thread-local | |
4279 | data. */ | |
252b5132 RH |
4280 | |
4281 | static void | |
98027b10 | 4282 | ppc_comm (int lcomm) |
252b5132 RH |
4283 | { |
4284 | asection *current_seg = now_seg; | |
4285 | subsegT current_subseg = now_subseg; | |
4286 | char *name; | |
4287 | char endc; | |
4288 | char *end_name; | |
4289 | offsetT size; | |
4290 | offsetT align; | |
4291 | symbolS *lcomm_sym = NULL; | |
4292 | symbolS *sym; | |
4293 | char *pfrag; | |
1b2cb8e2 | 4294 | struct ppc_xcoff_section *section; |
252b5132 | 4295 | |
d02603dc | 4296 | endc = get_symbol_name (&name); |
252b5132 | 4297 | end_name = input_line_pointer; |
d02603dc | 4298 | (void) restore_line_pointer (endc); |
252b5132 RH |
4299 | |
4300 | if (*input_line_pointer != ',') | |
4301 | { | |
4302 | as_bad (_("missing size")); | |
4303 | ignore_rest_of_line (); | |
4304 | return; | |
4305 | } | |
4306 | ++input_line_pointer; | |
4307 | ||
4308 | size = get_absolute_expression (); | |
4309 | if (size < 0) | |
4310 | { | |
4311 | as_bad (_("negative size")); | |
4312 | ignore_rest_of_line (); | |
4313 | return; | |
4314 | } | |
4315 | ||
4316 | if (! lcomm) | |
4317 | { | |
4318 | /* The third argument to .comm is the alignment. */ | |
4319 | if (*input_line_pointer != ',') | |
1ad63b2f | 4320 | align = 2; |
252b5132 RH |
4321 | else |
4322 | { | |
4323 | ++input_line_pointer; | |
4324 | align = get_absolute_expression (); | |
4325 | if (align <= 0) | |
4326 | { | |
4327 | as_warn (_("ignoring bad alignment")); | |
1ad63b2f | 4328 | align = 2; |
252b5132 RH |
4329 | } |
4330 | } | |
4331 | } | |
4332 | else | |
4333 | { | |
4334 | char *lcomm_name; | |
4335 | char lcomm_endc; | |
4336 | ||
252b5132 RH |
4337 | /* The third argument to .lcomm appears to be the real local |
4338 | common symbol to create. References to the symbol named in | |
4339 | the first argument are turned into references to the third | |
4340 | argument. */ | |
4341 | if (*input_line_pointer != ',') | |
4342 | { | |
4343 | as_bad (_("missing real symbol name")); | |
4344 | ignore_rest_of_line (); | |
4345 | return; | |
4346 | } | |
4347 | ++input_line_pointer; | |
4348 | ||
d02603dc | 4349 | lcomm_endc = get_symbol_name (&lcomm_name); |
81d4177b | 4350 | |
252b5132 RH |
4351 | lcomm_sym = symbol_find_or_make (lcomm_name); |
4352 | ||
d02603dc | 4353 | (void) restore_line_pointer (lcomm_endc); |
3c02c47f DE |
4354 | |
4355 | /* The fourth argument to .lcomm is the alignment. */ | |
4356 | if (*input_line_pointer != ',') | |
4357 | { | |
4358 | if (size <= 4) | |
4359 | align = 2; | |
4360 | else | |
4361 | align = 3; | |
4362 | } | |
4363 | else | |
4364 | { | |
4365 | ++input_line_pointer; | |
4366 | align = get_absolute_expression (); | |
4367 | if (align <= 0) | |
4368 | { | |
4369 | as_warn (_("ignoring bad alignment")); | |
4370 | align = 2; | |
4371 | } | |
4372 | } | |
252b5132 RH |
4373 | } |
4374 | ||
4375 | *end_name = '\0'; | |
4376 | sym = symbol_find_or_make (name); | |
4377 | *end_name = endc; | |
4378 | ||
4379 | if (S_IS_DEFINED (sym) | |
4380 | || S_GET_VALUE (sym) != 0) | |
4381 | { | |
4382 | as_bad (_("attempt to redefine symbol")); | |
4383 | ignore_rest_of_line (); | |
4384 | return; | |
4385 | } | |
81d4177b | 4386 | |
1b2cb8e2 CC |
4387 | if (symbol_get_tc (sym)->symbol_class == XMC_UL |
4388 | || (lcomm && symbol_get_tc (lcomm_sym)->symbol_class == XMC_UL)) | |
4389 | { | |
4390 | section = &ppc_xcoff_tbss_section; | |
4391 | if (!ppc_xcoff_section_is_initialized (section)) | |
4392 | { | |
4393 | ppc_init_xcoff_section (section, | |
5b7c81bd | 4394 | subseg_new (".tbss", 0), false); |
1b2cb8e2 CC |
4395 | bfd_set_section_flags (section->segment, |
4396 | SEC_ALLOC | SEC_THREAD_LOCAL); | |
4397 | seg_info (section->segment)->bss = 1; | |
4398 | } | |
4399 | } | |
4400 | else | |
4401 | section = &ppc_xcoff_bss_section; | |
4402 | ||
4403 | record_alignment (section->segment, align); | |
81d4177b | 4404 | |
252b5132 RH |
4405 | if (! lcomm |
4406 | || ! S_IS_DEFINED (lcomm_sym)) | |
4407 | { | |
4408 | symbolS *def_sym; | |
4409 | offsetT def_size; | |
4410 | ||
4411 | if (! lcomm) | |
4412 | { | |
4413 | def_sym = sym; | |
4414 | def_size = size; | |
4415 | S_SET_EXTERNAL (sym); | |
4416 | } | |
4417 | else | |
4418 | { | |
809ffe0d | 4419 | symbol_get_tc (lcomm_sym)->output = 1; |
252b5132 RH |
4420 | def_sym = lcomm_sym; |
4421 | def_size = 0; | |
4422 | } | |
4423 | ||
1b2cb8e2 | 4424 | subseg_set (section->segment, 1); |
252b5132 | 4425 | frag_align (align, 0, 0); |
81d4177b | 4426 | |
809ffe0d | 4427 | symbol_set_frag (def_sym, frag_now); |
252b5132 RH |
4428 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, def_sym, |
4429 | def_size, (char *) NULL); | |
4430 | *pfrag = 0; | |
1b2cb8e2 | 4431 | S_SET_SEGMENT (def_sym, section->segment); |
809ffe0d | 4432 | symbol_get_tc (def_sym)->align = align; |
252b5132 RH |
4433 | } |
4434 | else if (lcomm) | |
4435 | { | |
4436 | /* Align the size of lcomm_sym. */ | |
809ffe0d ILT |
4437 | symbol_get_frag (lcomm_sym)->fr_offset = |
4438 | ((symbol_get_frag (lcomm_sym)->fr_offset + (1 << align) - 1) | |
252b5132 | 4439 | &~ ((1 << align) - 1)); |
809ffe0d ILT |
4440 | if (align > symbol_get_tc (lcomm_sym)->align) |
4441 | symbol_get_tc (lcomm_sym)->align = align; | |
252b5132 RH |
4442 | } |
4443 | ||
4444 | if (lcomm) | |
4445 | { | |
4446 | /* Make sym an offset from lcomm_sym. */ | |
1b2cb8e2 | 4447 | S_SET_SEGMENT (sym, section->segment); |
809ffe0d ILT |
4448 | symbol_set_frag (sym, symbol_get_frag (lcomm_sym)); |
4449 | S_SET_VALUE (sym, symbol_get_frag (lcomm_sym)->fr_offset); | |
4450 | symbol_get_frag (lcomm_sym)->fr_offset += size; | |
252b5132 RH |
4451 | } |
4452 | ||
4453 | subseg_set (current_seg, current_subseg); | |
4454 | ||
4455 | demand_empty_rest_of_line (); | |
4456 | } | |
4457 | ||
4458 | /* The .csect pseudo-op. This switches us into a different | |
4459 | subsegment. The first argument is a symbol whose value is the | |
4460 | start of the .csect. In COFF, csect symbols get special aux | |
4461 | entries defined by the x_csect field of union internal_auxent. The | |
4462 | optional second argument is the alignment (the default is 2). */ | |
4463 | ||
4464 | static void | |
98027b10 | 4465 | ppc_csect (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4466 | { |
4467 | char *name; | |
4468 | char endc; | |
4469 | symbolS *sym; | |
931e13a6 | 4470 | offsetT align; |
252b5132 | 4471 | |
d02603dc | 4472 | endc = get_symbol_name (&name); |
81d4177b | 4473 | |
252b5132 RH |
4474 | sym = symbol_find_or_make (name); |
4475 | ||
d02603dc | 4476 | (void) restore_line_pointer (endc); |
252b5132 RH |
4477 | |
4478 | if (S_GET_NAME (sym)[0] == '\0') | |
4479 | { | |
4480 | /* An unnamed csect is assumed to be [PR]. */ | |
96d56e9f | 4481 | symbol_get_tc (sym)->symbol_class = XMC_PR; |
252b5132 RH |
4482 | } |
4483 | ||
931e13a6 | 4484 | align = 2; |
252b5132 RH |
4485 | if (*input_line_pointer == ',') |
4486 | { | |
4487 | ++input_line_pointer; | |
931e13a6 | 4488 | align = get_absolute_expression (); |
252b5132 RH |
4489 | } |
4490 | ||
931e13a6 AM |
4491 | ppc_change_csect (sym, align); |
4492 | ||
252b5132 RH |
4493 | demand_empty_rest_of_line (); |
4494 | } | |
4495 | ||
4496 | /* Change to a different csect. */ | |
4497 | ||
4498 | static void | |
98027b10 | 4499 | ppc_change_csect (symbolS *sym, offsetT align) |
252b5132 RH |
4500 | { |
4501 | if (S_IS_DEFINED (sym)) | |
809ffe0d | 4502 | subseg_set (S_GET_SEGMENT (sym), symbol_get_tc (sym)->subseg); |
252b5132 RH |
4503 | else |
4504 | { | |
1b2cb8e2 | 4505 | struct ppc_xcoff_section *section; |
252b5132 RH |
4506 | int after_toc; |
4507 | int hold_chunksize; | |
4508 | symbolS *list; | |
931e13a6 AM |
4509 | int is_code; |
4510 | segT sec; | |
252b5132 RH |
4511 | |
4512 | /* This is a new csect. We need to look at the symbol class to | |
4513 | figure out whether it should go in the text section or the | |
4514 | data section. */ | |
4515 | after_toc = 0; | |
931e13a6 | 4516 | is_code = 0; |
96d56e9f | 4517 | switch (symbol_get_tc (sym)->symbol_class) |
252b5132 RH |
4518 | { |
4519 | case XMC_PR: | |
4520 | case XMC_RO: | |
4521 | case XMC_DB: | |
4522 | case XMC_GL: | |
4523 | case XMC_XO: | |
4524 | case XMC_SV: | |
4525 | case XMC_TI: | |
4526 | case XMC_TB: | |
1b2cb8e2 | 4527 | section = &ppc_xcoff_text_section; |
931e13a6 | 4528 | is_code = 1; |
252b5132 RH |
4529 | break; |
4530 | case XMC_RW: | |
4531 | case XMC_TC0: | |
4532 | case XMC_TC: | |
4a403be0 | 4533 | case XMC_TE: |
252b5132 RH |
4534 | case XMC_DS: |
4535 | case XMC_UA: | |
252b5132 | 4536 | case XMC_UC: |
1b2cb8e2 | 4537 | section = &ppc_xcoff_data_section; |
252b5132 | 4538 | if (ppc_toc_csect != NULL |
809ffe0d | 4539 | && (symbol_get_tc (ppc_toc_csect)->subseg + 1 |
1b2cb8e2 | 4540 | == section->next_subsegment)) |
252b5132 | 4541 | after_toc = 1; |
1b2cb8e2 CC |
4542 | break; |
4543 | case XMC_BS: | |
4544 | section = &ppc_xcoff_bss_section; | |
4545 | break; | |
4546 | case XMC_TL: | |
4547 | section = &ppc_xcoff_tdata_section; | |
4548 | /* Create .tdata section if not yet done. */ | |
4549 | if (!ppc_xcoff_section_is_initialized (section)) | |
4550 | { | |
4551 | ppc_init_xcoff_section (section, subseg_new (".tdata", 0), | |
5b7c81bd | 4552 | true); |
1b2cb8e2 CC |
4553 | bfd_set_section_flags (section->segment, SEC_ALLOC |
4554 | | SEC_LOAD | SEC_RELOC | SEC_DATA | |
4555 | | SEC_THREAD_LOCAL); | |
4556 | } | |
4557 | break; | |
4558 | case XMC_UL: | |
4559 | section = &ppc_xcoff_tbss_section; | |
4560 | /* Create .tbss section if not yet done. */ | |
4561 | if (!ppc_xcoff_section_is_initialized (section)) | |
4562 | { | |
4563 | ppc_init_xcoff_section (section, subseg_new (".tbss", 0), | |
5b7c81bd | 4564 | false); |
1b2cb8e2 CC |
4565 | bfd_set_section_flags (section->segment, SEC_ALLOC | |
4566 | SEC_THREAD_LOCAL); | |
4567 | seg_info (section->segment)->bss = 1; | |
4568 | } | |
252b5132 RH |
4569 | break; |
4570 | default: | |
4571 | abort (); | |
4572 | } | |
4573 | ||
1b2cb8e2 CC |
4574 | S_SET_SEGMENT (sym, section->segment); |
4575 | symbol_get_tc (sym)->subseg = section->next_subsegment; | |
4576 | ++section->next_subsegment; | |
4577 | ||
252b5132 | 4578 | /* We set the obstack chunk size to a small value before |
99a814a1 AM |
4579 | changing subsegments, so that we don't use a lot of memory |
4580 | space for what may be a small section. */ | |
252b5132 RH |
4581 | hold_chunksize = chunksize; |
4582 | chunksize = 64; | |
4583 | ||
931e13a6 AM |
4584 | sec = subseg_new (segment_name (S_GET_SEGMENT (sym)), |
4585 | symbol_get_tc (sym)->subseg); | |
252b5132 RH |
4586 | |
4587 | chunksize = hold_chunksize; | |
4588 | ||
4589 | if (after_toc) | |
4590 | ppc_after_toc_frag = frag_now; | |
4591 | ||
931e13a6 AM |
4592 | record_alignment (sec, align); |
4593 | if (is_code) | |
4594 | frag_align_code (align, 0); | |
4595 | else | |
4596 | frag_align (align, 0, 0); | |
4597 | ||
809ffe0d | 4598 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
4599 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4600 | ||
931e13a6 | 4601 | symbol_get_tc (sym)->align = align; |
809ffe0d ILT |
4602 | symbol_get_tc (sym)->output = 1; |
4603 | symbol_get_tc (sym)->within = sym; | |
81d4177b | 4604 | |
1b2cb8e2 | 4605 | for (list = section->csects; |
809ffe0d ILT |
4606 | symbol_get_tc (list)->next != (symbolS *) NULL; |
4607 | list = symbol_get_tc (list)->next) | |
252b5132 | 4608 | ; |
809ffe0d | 4609 | symbol_get_tc (list)->next = sym; |
81d4177b | 4610 | |
252b5132 | 4611 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); |
809ffe0d ILT |
4612 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
4613 | &symbol_lastP); | |
252b5132 RH |
4614 | } |
4615 | ||
4616 | ppc_current_csect = sym; | |
4617 | } | |
4618 | ||
85645aed TG |
4619 | static void |
4620 | ppc_change_debug_section (unsigned int idx, subsegT subseg) | |
4621 | { | |
4622 | segT sec; | |
4623 | flagword oldflags; | |
4624 | const struct xcoff_dwsect_name *dw = &xcoff_dwsect_names[idx]; | |
4625 | ||
4626 | sec = subseg_new (dw->name, subseg); | |
fd361982 | 4627 | oldflags = bfd_section_flags (sec); |
85645aed TG |
4628 | if (oldflags == SEC_NO_FLAGS) |
4629 | { | |
4630 | /* Just created section. */ | |
4631 | gas_assert (dw_sections[idx].sect == NULL); | |
4632 | ||
fd361982 AM |
4633 | bfd_set_section_flags (sec, SEC_DEBUGGING); |
4634 | bfd_set_section_alignment (sec, 0); | |
85645aed TG |
4635 | dw_sections[idx].sect = sec; |
4636 | } | |
4637 | ||
4638 | /* Not anymore in a csect. */ | |
4639 | ppc_current_csect = NULL; | |
4640 | } | |
4641 | ||
4642 | /* The .dwsect pseudo-op. Defines a DWARF section. Syntax is: | |
4643 | .dwsect flag [, opt-label ] | |
4644 | */ | |
4645 | ||
4646 | static void | |
4647 | ppc_dwsect (int ignore ATTRIBUTE_UNUSED) | |
4648 | { | |
16de26a6 | 4649 | valueT flag; |
85645aed TG |
4650 | symbolS *opt_label; |
4651 | const struct xcoff_dwsect_name *dw; | |
4652 | struct dw_subsection *subseg; | |
4653 | struct dw_section *dws; | |
4654 | int i; | |
4655 | ||
4656 | /* Find section. */ | |
4657 | flag = get_absolute_expression (); | |
4658 | dw = NULL; | |
4659 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
4660 | if (xcoff_dwsect_names[i].flag == flag) | |
4661 | { | |
4662 | dw = &xcoff_dwsect_names[i]; | |
4663 | break; | |
4664 | } | |
4665 | ||
4666 | /* Parse opt-label. */ | |
4667 | if (*input_line_pointer == ',') | |
4668 | { | |
d02603dc | 4669 | char *label; |
85645aed TG |
4670 | char c; |
4671 | ||
4672 | ++input_line_pointer; | |
4673 | ||
d02603dc | 4674 | c = get_symbol_name (&label); |
85645aed | 4675 | opt_label = symbol_find_or_make (label); |
d02603dc | 4676 | (void) restore_line_pointer (c); |
85645aed TG |
4677 | } |
4678 | else | |
4679 | opt_label = NULL; | |
4680 | ||
4681 | demand_empty_rest_of_line (); | |
4682 | ||
4683 | /* Return now in case of unknown subsection. */ | |
4684 | if (dw == NULL) | |
4685 | { | |
d6ed37ed | 4686 | as_bad (_("no known dwarf XCOFF section for flag 0x%08x\n"), |
85645aed TG |
4687 | (unsigned)flag); |
4688 | return; | |
4689 | } | |
4690 | ||
4691 | /* Find the subsection. */ | |
4692 | dws = &dw_sections[i]; | |
4693 | subseg = NULL; | |
4694 | if (opt_label != NULL && S_IS_DEFINED (opt_label)) | |
4695 | { | |
4696 | /* Sanity check (note that in theory S_GET_SEGMENT mustn't be null). */ | |
4697 | if (dws->sect == NULL || S_GET_SEGMENT (opt_label) != dws->sect) | |
4698 | { | |
4699 | as_bad (_("label %s was not defined in this dwarf section"), | |
4700 | S_GET_NAME (opt_label)); | |
4701 | subseg = dws->anon_subseg; | |
4702 | opt_label = NULL; | |
4703 | } | |
4704 | else | |
4705 | subseg = symbol_get_tc (opt_label)->u.dw; | |
4706 | } | |
4707 | ||
4708 | if (subseg != NULL) | |
4709 | { | |
4710 | /* Switch to the subsection. */ | |
4711 | ppc_change_debug_section (i, subseg->subseg); | |
4712 | } | |
4713 | else | |
4714 | { | |
4715 | /* Create a new dw subsection. */ | |
325801bd | 4716 | subseg = XNEW (struct dw_subsection); |
85645aed TG |
4717 | |
4718 | if (opt_label == NULL) | |
4719 | { | |
4720 | /* The anonymous one. */ | |
4721 | subseg->subseg = 0; | |
4722 | subseg->link = NULL; | |
4723 | dws->anon_subseg = subseg; | |
4724 | } | |
4725 | else | |
4726 | { | |
4727 | /* A named one. */ | |
4728 | if (dws->list_subseg != NULL) | |
4729 | subseg->subseg = dws->list_subseg->subseg + 1; | |
4730 | else | |
4731 | subseg->subseg = 1; | |
4732 | ||
4733 | subseg->link = dws->list_subseg; | |
4734 | dws->list_subseg = subseg; | |
4735 | symbol_get_tc (opt_label)->u.dw = subseg; | |
4736 | } | |
4737 | ||
4738 | ppc_change_debug_section (i, subseg->subseg); | |
4739 | ||
4740 | if (dw->def_size) | |
4741 | { | |
4742 | /* Add the length field. */ | |
4743 | expressionS *exp = &subseg->end_exp; | |
4744 | int sz; | |
4745 | ||
4746 | if (opt_label != NULL) | |
4747 | symbol_set_value_now (opt_label); | |
4748 | ||
4749 | /* Add the length field. Note that according to the AIX assembler | |
4750 | manual, the size of the length field is 4 for powerpc32 but | |
4751 | 12 for powerpc64. */ | |
4752 | if (ppc_obj64) | |
4753 | { | |
4754 | /* Write the 64bit marker. */ | |
4755 | md_number_to_chars (frag_more (4), -1, 4); | |
4756 | } | |
4757 | ||
4758 | exp->X_op = O_subtract; | |
4759 | exp->X_op_symbol = symbol_temp_new_now (); | |
4760 | exp->X_add_symbol = symbol_temp_make (); | |
4761 | ||
4762 | sz = ppc_obj64 ? 8 : 4; | |
4763 | exp->X_add_number = -sz; | |
4764 | emit_expr (exp, sz); | |
4765 | } | |
4766 | } | |
4767 | } | |
4768 | ||
252b5132 RH |
4769 | /* This function handles the .text and .data pseudo-ops. These |
4770 | pseudo-ops aren't really used by XCOFF; we implement them for the | |
4771 | convenience of people who aren't used to XCOFF. */ | |
4772 | ||
4773 | static void | |
98027b10 | 4774 | ppc_section (int type) |
252b5132 RH |
4775 | { |
4776 | const char *name; | |
4777 | symbolS *sym; | |
4778 | ||
4779 | if (type == 't') | |
4780 | name = ".text[PR]"; | |
4781 | else if (type == 'd') | |
4782 | name = ".data[RW]"; | |
4783 | else | |
4784 | abort (); | |
4785 | ||
4786 | sym = symbol_find_or_make (name); | |
4787 | ||
931e13a6 | 4788 | ppc_change_csect (sym, 2); |
252b5132 RH |
4789 | |
4790 | demand_empty_rest_of_line (); | |
4791 | } | |
4792 | ||
4793 | /* This function handles the .section pseudo-op. This is mostly to | |
4794 | give an error, since XCOFF only supports .text, .data and .bss, but | |
4795 | we do permit the user to name the text or data section. */ | |
4796 | ||
4797 | static void | |
98027b10 | 4798 | ppc_named_section (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4799 | { |
4800 | char *user_name; | |
4801 | const char *real_name; | |
4802 | char c; | |
4803 | symbolS *sym; | |
4804 | ||
d02603dc | 4805 | c = get_symbol_name (&user_name); |
252b5132 RH |
4806 | |
4807 | if (strcmp (user_name, ".text") == 0) | |
4808 | real_name = ".text[PR]"; | |
4809 | else if (strcmp (user_name, ".data") == 0) | |
4810 | real_name = ".data[RW]"; | |
4811 | else | |
4812 | { | |
d6ed37ed | 4813 | as_bad (_("the XCOFF file format does not support arbitrary sections")); |
d02603dc | 4814 | (void) restore_line_pointer (c); |
252b5132 RH |
4815 | ignore_rest_of_line (); |
4816 | return; | |
4817 | } | |
4818 | ||
d02603dc | 4819 | (void) restore_line_pointer (c); |
252b5132 RH |
4820 | |
4821 | sym = symbol_find_or_make (real_name); | |
4822 | ||
931e13a6 | 4823 | ppc_change_csect (sym, 2); |
252b5132 RH |
4824 | |
4825 | demand_empty_rest_of_line (); | |
4826 | } | |
4827 | ||
4828 | /* The .extern pseudo-op. We create an undefined symbol. */ | |
4829 | ||
4830 | static void | |
98027b10 | 4831 | ppc_extern (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4832 | { |
4833 | char *name; | |
4834 | char endc; | |
4835 | ||
d02603dc | 4836 | endc = get_symbol_name (&name); |
252b5132 RH |
4837 | |
4838 | (void) symbol_find_or_make (name); | |
4839 | ||
d02603dc | 4840 | (void) restore_line_pointer (endc); |
252b5132 RH |
4841 | |
4842 | demand_empty_rest_of_line (); | |
4843 | } | |
4844 | ||
4845 | /* The .lglobl pseudo-op. Keep the symbol in the symbol table. */ | |
4846 | ||
4847 | static void | |
98027b10 | 4848 | ppc_lglobl (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4849 | { |
4850 | char *name; | |
4851 | char endc; | |
4852 | symbolS *sym; | |
4853 | ||
d02603dc | 4854 | endc = get_symbol_name (&name); |
252b5132 RH |
4855 | |
4856 | sym = symbol_find_or_make (name); | |
4857 | ||
d02603dc | 4858 | (void) restore_line_pointer (endc); |
252b5132 | 4859 | |
809ffe0d | 4860 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
4861 | |
4862 | demand_empty_rest_of_line (); | |
4863 | } | |
4864 | ||
c865e45b RS |
4865 | /* The .ref pseudo-op. It takes a list of symbol names and inserts R_REF |
4866 | relocations at the beginning of the current csect. | |
4867 | ||
4868 | (In principle, there's no reason why the relocations _have_ to be at | |
4869 | the beginning. Anywhere in the csect would do. However, inserting | |
33eaf5de | 4870 | at the beginning is what the native assembler does, and it helps to |
c865e45b RS |
4871 | deal with cases where the .ref statements follow the section contents.) |
4872 | ||
4873 | ??? .refs don't work for empty .csects. However, the native assembler | |
4874 | doesn't report an error in this case, and neither yet do we. */ | |
4875 | ||
4876 | static void | |
4877 | ppc_ref (int ignore ATTRIBUTE_UNUSED) | |
4878 | { | |
4879 | char *name; | |
4880 | char c; | |
4881 | ||
4882 | if (ppc_current_csect == NULL) | |
4883 | { | |
4884 | as_bad (_(".ref outside .csect")); | |
4885 | ignore_rest_of_line (); | |
4886 | return; | |
4887 | } | |
4888 | ||
4889 | do | |
4890 | { | |
d02603dc | 4891 | c = get_symbol_name (&name); |
c865e45b RS |
4892 | |
4893 | fix_at_start (symbol_get_frag (ppc_current_csect), 0, | |
5b7c81bd | 4894 | symbol_find_or_make (name), 0, false, BFD_RELOC_NONE); |
c865e45b RS |
4895 | |
4896 | *input_line_pointer = c; | |
d02603dc | 4897 | SKIP_WHITESPACE_AFTER_NAME (); |
c865e45b RS |
4898 | c = *input_line_pointer; |
4899 | if (c == ',') | |
4900 | { | |
4901 | input_line_pointer++; | |
4902 | SKIP_WHITESPACE (); | |
4903 | if (is_end_of_line[(unsigned char) *input_line_pointer]) | |
4904 | { | |
4905 | as_bad (_("missing symbol name")); | |
4906 | ignore_rest_of_line (); | |
4907 | return; | |
4908 | } | |
4909 | } | |
4910 | } | |
4911 | while (c == ','); | |
4912 | ||
4913 | demand_empty_rest_of_line (); | |
4914 | } | |
4915 | ||
252b5132 RH |
4916 | /* The .rename pseudo-op. The RS/6000 assembler can rename symbols, |
4917 | although I don't know why it bothers. */ | |
4918 | ||
4919 | static void | |
98027b10 | 4920 | ppc_rename (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4921 | { |
4922 | char *name; | |
4923 | char endc; | |
4924 | symbolS *sym; | |
4925 | int len; | |
4926 | ||
d02603dc | 4927 | endc = get_symbol_name (&name); |
252b5132 RH |
4928 | |
4929 | sym = symbol_find_or_make (name); | |
4930 | ||
d02603dc | 4931 | (void) restore_line_pointer (endc); |
252b5132 RH |
4932 | |
4933 | if (*input_line_pointer != ',') | |
4934 | { | |
4935 | as_bad (_("missing rename string")); | |
4936 | ignore_rest_of_line (); | |
4937 | return; | |
4938 | } | |
4939 | ++input_line_pointer; | |
4940 | ||
809ffe0d | 4941 | symbol_get_tc (sym)->real_name = demand_copy_C_string (&len); |
252b5132 RH |
4942 | |
4943 | demand_empty_rest_of_line (); | |
4944 | } | |
4945 | ||
4946 | /* The .stabx pseudo-op. This is similar to a normal .stabs | |
4947 | pseudo-op, but slightly different. A sample is | |
4948 | .stabx "main:F-1",.main,142,0 | |
4949 | The first argument is the symbol name to create. The second is the | |
4950 | value, and the third is the storage class. The fourth seems to be | |
4951 | always zero, and I am assuming it is the type. */ | |
4952 | ||
4953 | static void | |
98027b10 | 4954 | ppc_stabx (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
4955 | { |
4956 | char *name; | |
4957 | int len; | |
4958 | symbolS *sym; | |
4959 | expressionS exp; | |
4960 | ||
4961 | name = demand_copy_C_string (&len); | |
4962 | ||
4963 | if (*input_line_pointer != ',') | |
4964 | { | |
4965 | as_bad (_("missing value")); | |
4966 | return; | |
4967 | } | |
4968 | ++input_line_pointer; | |
4969 | ||
5b7c81bd | 4970 | ppc_stab_symbol = true; |
252b5132 | 4971 | sym = symbol_make (name); |
5b7c81bd | 4972 | ppc_stab_symbol = false; |
252b5132 | 4973 | |
809ffe0d | 4974 | symbol_get_tc (sym)->real_name = name; |
252b5132 RH |
4975 | |
4976 | (void) expression (&exp); | |
4977 | ||
4978 | switch (exp.X_op) | |
4979 | { | |
4980 | case O_illegal: | |
4981 | case O_absent: | |
4982 | case O_big: | |
4983 | as_bad (_("illegal .stabx expression; zero assumed")); | |
4984 | exp.X_add_number = 0; | |
4985 | /* Fall through. */ | |
4986 | case O_constant: | |
4987 | S_SET_VALUE (sym, (valueT) exp.X_add_number); | |
809ffe0d | 4988 | symbol_set_frag (sym, &zero_address_frag); |
252b5132 RH |
4989 | break; |
4990 | ||
4991 | case O_symbol: | |
4992 | if (S_GET_SEGMENT (exp.X_add_symbol) == undefined_section) | |
809ffe0d | 4993 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
4994 | else |
4995 | { | |
4996 | S_SET_VALUE (sym, | |
4997 | exp.X_add_number + S_GET_VALUE (exp.X_add_symbol)); | |
809ffe0d | 4998 | symbol_set_frag (sym, symbol_get_frag (exp.X_add_symbol)); |
252b5132 RH |
4999 | } |
5000 | break; | |
5001 | ||
5002 | default: | |
5003 | /* The value is some complex expression. This will probably | |
99a814a1 AM |
5004 | fail at some later point, but this is probably the right |
5005 | thing to do here. */ | |
809ffe0d | 5006 | symbol_set_value_expression (sym, &exp); |
252b5132 RH |
5007 | break; |
5008 | } | |
5009 | ||
5010 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5011 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5012 | |
5013 | if (*input_line_pointer != ',') | |
5014 | { | |
5015 | as_bad (_("missing class")); | |
5016 | return; | |
5017 | } | |
5018 | ++input_line_pointer; | |
5019 | ||
5020 | S_SET_STORAGE_CLASS (sym, get_absolute_expression ()); | |
5021 | ||
5022 | if (*input_line_pointer != ',') | |
5023 | { | |
5024 | as_bad (_("missing type")); | |
5025 | return; | |
5026 | } | |
5027 | ++input_line_pointer; | |
5028 | ||
5029 | S_SET_DATA_TYPE (sym, get_absolute_expression ()); | |
5030 | ||
809ffe0d | 5031 | symbol_get_tc (sym)->output = 1; |
252b5132 | 5032 | |
c734e7e3 TG |
5033 | if (S_GET_STORAGE_CLASS (sym) == C_STSYM) |
5034 | { | |
5035 | /* In this case : | |
252b5132 | 5036 | |
c734e7e3 TG |
5037 | .bs name |
5038 | .stabx "z",arrays_,133,0 | |
5039 | .es | |
99a814a1 | 5040 | |
c734e7e3 | 5041 | .comm arrays_,13768,3 |
99a814a1 | 5042 | |
c734e7e3 TG |
5043 | resolve_symbol_value will copy the exp's "within" into sym's when the |
5044 | offset is 0. Since this seems to be corner case problem, | |
5045 | only do the correction for storage class C_STSYM. A better solution | |
5046 | would be to have the tc field updated in ppc_symbol_new_hook. */ | |
99a814a1 | 5047 | |
c734e7e3 TG |
5048 | if (exp.X_op == O_symbol) |
5049 | { | |
5050 | if (ppc_current_block == NULL) | |
5051 | as_bad (_(".stabx of storage class stsym must be within .bs/.es")); | |
99a814a1 | 5052 | |
c734e7e3 TG |
5053 | symbol_get_tc (sym)->within = ppc_current_block; |
5054 | symbol_get_tc (exp.X_add_symbol)->within = ppc_current_block; | |
5055 | } | |
5056 | } | |
99a814a1 | 5057 | |
252b5132 RH |
5058 | if (exp.X_op != O_symbol |
5059 | || ! S_IS_EXTERNAL (exp.X_add_symbol) | |
5060 | || S_GET_SEGMENT (exp.X_add_symbol) != bss_section) | |
5061 | ppc_frob_label (sym); | |
5062 | else | |
5063 | { | |
5064 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5065 | symbol_append (sym, exp.X_add_symbol, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5066 | if (symbol_get_tc (ppc_current_csect)->within == exp.X_add_symbol) |
5067 | symbol_get_tc (ppc_current_csect)->within = sym; | |
252b5132 RH |
5068 | } |
5069 | ||
5070 | demand_empty_rest_of_line (); | |
5071 | } | |
5072 | ||
5073 | /* The .function pseudo-op. This takes several arguments. The first | |
5074 | argument seems to be the external name of the symbol. The second | |
67c1ffbe | 5075 | argument seems to be the label for the start of the function. gcc |
252b5132 RH |
5076 | uses the same name for both. I have no idea what the third and |
5077 | fourth arguments are meant to be. The optional fifth argument is | |
5078 | an expression for the size of the function. In COFF this symbol | |
5079 | gets an aux entry like that used for a csect. */ | |
5080 | ||
5081 | static void | |
98027b10 | 5082 | ppc_function (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5083 | { |
5084 | char *name; | |
5085 | char endc; | |
5086 | char *s; | |
5087 | symbolS *ext_sym; | |
5088 | symbolS *lab_sym; | |
5089 | ||
d02603dc | 5090 | endc = get_symbol_name (&name); |
252b5132 RH |
5091 | |
5092 | /* Ignore any [PR] suffix. */ | |
5093 | name = ppc_canonicalize_symbol_name (name); | |
5094 | s = strchr (name, '['); | |
5095 | if (s != (char *) NULL | |
5096 | && strcmp (s + 1, "PR]") == 0) | |
5097 | *s = '\0'; | |
5098 | ||
5099 | ext_sym = symbol_find_or_make (name); | |
5100 | ||
d02603dc | 5101 | (void) restore_line_pointer (endc); |
252b5132 RH |
5102 | |
5103 | if (*input_line_pointer != ',') | |
5104 | { | |
5105 | as_bad (_("missing symbol name")); | |
5106 | ignore_rest_of_line (); | |
5107 | return; | |
5108 | } | |
5109 | ++input_line_pointer; | |
5110 | ||
d02603dc | 5111 | endc = get_symbol_name (&name); |
252b5132 RH |
5112 | |
5113 | lab_sym = symbol_find_or_make (name); | |
5114 | ||
d02603dc | 5115 | (void) restore_line_pointer (endc); |
252b5132 RH |
5116 | |
5117 | if (ext_sym != lab_sym) | |
5118 | { | |
809ffe0d ILT |
5119 | expressionS exp; |
5120 | ||
5121 | exp.X_op = O_symbol; | |
5122 | exp.X_add_symbol = lab_sym; | |
5123 | exp.X_op_symbol = NULL; | |
5124 | exp.X_add_number = 0; | |
5125 | exp.X_unsigned = 0; | |
5126 | symbol_set_value_expression (ext_sym, &exp); | |
252b5132 RH |
5127 | } |
5128 | ||
96d56e9f NC |
5129 | if (symbol_get_tc (ext_sym)->symbol_class == -1) |
5130 | symbol_get_tc (ext_sym)->symbol_class = XMC_PR; | |
809ffe0d | 5131 | symbol_get_tc (ext_sym)->output = 1; |
252b5132 RH |
5132 | |
5133 | if (*input_line_pointer == ',') | |
5134 | { | |
91d6fa6a | 5135 | expressionS exp; |
252b5132 RH |
5136 | |
5137 | /* Ignore the third argument. */ | |
5138 | ++input_line_pointer; | |
91d6fa6a | 5139 | expression (& exp); |
252b5132 RH |
5140 | if (*input_line_pointer == ',') |
5141 | { | |
5142 | /* Ignore the fourth argument. */ | |
5143 | ++input_line_pointer; | |
91d6fa6a | 5144 | expression (& exp); |
252b5132 RH |
5145 | if (*input_line_pointer == ',') |
5146 | { | |
5147 | /* The fifth argument is the function size. */ | |
5148 | ++input_line_pointer; | |
e01e1cee AM |
5149 | symbol_get_tc (ext_sym)->u.size |
5150 | = symbol_new ("L0\001", absolute_section, | |
5151 | &zero_address_frag, 0); | |
85645aed | 5152 | pseudo_set (symbol_get_tc (ext_sym)->u.size); |
252b5132 RH |
5153 | } |
5154 | } | |
5155 | } | |
5156 | ||
5157 | S_SET_DATA_TYPE (ext_sym, DT_FCN << N_BTSHFT); | |
5158 | SF_SET_FUNCTION (ext_sym); | |
5159 | SF_SET_PROCESS (ext_sym); | |
5160 | coff_add_linesym (ext_sym); | |
5161 | ||
5162 | demand_empty_rest_of_line (); | |
5163 | } | |
5164 | ||
5165 | /* The .bf pseudo-op. This is just like a COFF C_FCN symbol named | |
8642cce8 TR |
5166 | ".bf". If the pseudo op .bi was seen before .bf, patch the .bi sym |
5167 | with the correct line number */ | |
5d6255fe | 5168 | |
8642cce8 | 5169 | static symbolS *saved_bi_sym = 0; |
252b5132 RH |
5170 | |
5171 | static void | |
98027b10 | 5172 | ppc_bf (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5173 | { |
5174 | symbolS *sym; | |
5175 | ||
5176 | sym = symbol_make (".bf"); | |
5177 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5178 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5179 | S_SET_VALUE (sym, frag_now_fix ()); |
5180 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5181 | ||
5182 | coff_line_base = get_absolute_expression (); | |
5183 | ||
5184 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5185 | SA_SET_SYM_LNNO (sym, coff_line_base); | |
5186 | ||
8642cce8 | 5187 | /* Line number for bi. */ |
5d6255fe | 5188 | if (saved_bi_sym) |
8642cce8 TR |
5189 | { |
5190 | S_SET_VALUE (saved_bi_sym, coff_n_line_nos); | |
5191 | saved_bi_sym = 0; | |
5192 | } | |
5d6255fe | 5193 | |
8642cce8 | 5194 | |
809ffe0d | 5195 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5196 | |
5197 | ppc_frob_label (sym); | |
5198 | ||
5199 | demand_empty_rest_of_line (); | |
5200 | } | |
5201 | ||
5202 | /* The .ef pseudo-op. This is just like a COFF C_FCN symbol named | |
5203 | ".ef", except that the line number is absolute, not relative to the | |
5204 | most recent ".bf" symbol. */ | |
5205 | ||
5206 | static void | |
98027b10 | 5207 | ppc_ef (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5208 | { |
5209 | symbolS *sym; | |
5210 | ||
5211 | sym = symbol_make (".ef"); | |
5212 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5213 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5214 | S_SET_VALUE (sym, frag_now_fix ()); |
5215 | S_SET_STORAGE_CLASS (sym, C_FCN); | |
5216 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5217 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5218 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5219 | |
5220 | ppc_frob_label (sym); | |
5221 | ||
5222 | demand_empty_rest_of_line (); | |
5223 | } | |
5224 | ||
5225 | /* The .bi and .ei pseudo-ops. These take a string argument and | |
5226 | generates a C_BINCL or C_EINCL symbol, which goes at the start of | |
8642cce8 TR |
5227 | the symbol list. The value of .bi will be know when the next .bf |
5228 | is encountered. */ | |
252b5132 RH |
5229 | |
5230 | static void | |
98027b10 | 5231 | ppc_biei (int ei) |
252b5132 RH |
5232 | { |
5233 | static symbolS *last_biei; | |
5234 | ||
5235 | char *name; | |
5236 | int len; | |
5237 | symbolS *sym; | |
5238 | symbolS *look; | |
5239 | ||
5240 | name = demand_copy_C_string (&len); | |
5241 | ||
5242 | /* The value of these symbols is actually file offset. Here we set | |
5243 | the value to the index into the line number entries. In | |
5244 | ppc_frob_symbols we set the fix_line field, which will cause BFD | |
5245 | to do the right thing. */ | |
5246 | ||
5247 | sym = symbol_make (name); | |
5248 | /* obj-coff.c currently only handles line numbers correctly in the | |
5249 | .text section. */ | |
5250 | S_SET_SEGMENT (sym, text_section); | |
5251 | S_SET_VALUE (sym, coff_n_line_nos); | |
809ffe0d | 5252 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5253 | |
5254 | S_SET_STORAGE_CLASS (sym, ei ? C_EINCL : C_BINCL); | |
809ffe0d | 5255 | symbol_get_tc (sym)->output = 1; |
81d4177b | 5256 | |
8642cce8 | 5257 | /* Save bi. */ |
5d6255fe | 5258 | if (ei) |
8642cce8 TR |
5259 | saved_bi_sym = 0; |
5260 | else | |
5261 | saved_bi_sym = sym; | |
5262 | ||
252b5132 RH |
5263 | for (look = last_biei ? last_biei : symbol_rootP; |
5264 | (look != (symbolS *) NULL | |
5265 | && (S_GET_STORAGE_CLASS (look) == C_FILE | |
5266 | || S_GET_STORAGE_CLASS (look) == C_BINCL | |
5267 | || S_GET_STORAGE_CLASS (look) == C_EINCL)); | |
5268 | look = symbol_next (look)) | |
5269 | ; | |
5270 | if (look != (symbolS *) NULL) | |
5271 | { | |
5272 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
5273 | symbol_insert (sym, look, &symbol_rootP, &symbol_lastP); | |
5274 | last_biei = sym; | |
5275 | } | |
5276 | ||
5277 | demand_empty_rest_of_line (); | |
5278 | } | |
5279 | ||
5280 | /* The .bs pseudo-op. This generates a C_BSTAT symbol named ".bs". | |
5281 | There is one argument, which is a csect symbol. The value of the | |
5282 | .bs symbol is the index of this csect symbol. */ | |
5283 | ||
5284 | static void | |
98027b10 | 5285 | ppc_bs (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5286 | { |
5287 | char *name; | |
5288 | char endc; | |
5289 | symbolS *csect; | |
5290 | symbolS *sym; | |
5291 | ||
5292 | if (ppc_current_block != NULL) | |
5293 | as_bad (_("nested .bs blocks")); | |
5294 | ||
d02603dc | 5295 | endc = get_symbol_name (&name); |
252b5132 RH |
5296 | |
5297 | csect = symbol_find_or_make (name); | |
5298 | ||
d02603dc | 5299 | (void) restore_line_pointer (endc); |
252b5132 RH |
5300 | |
5301 | sym = symbol_make (".bs"); | |
5302 | S_SET_SEGMENT (sym, now_seg); | |
5303 | S_SET_STORAGE_CLASS (sym, C_BSTAT); | |
809ffe0d ILT |
5304 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5305 | symbol_get_tc (sym)->output = 1; | |
252b5132 | 5306 | |
809ffe0d | 5307 | symbol_get_tc (sym)->within = csect; |
252b5132 RH |
5308 | |
5309 | ppc_frob_label (sym); | |
5310 | ||
5311 | ppc_current_block = sym; | |
5312 | ||
5313 | demand_empty_rest_of_line (); | |
5314 | } | |
5315 | ||
5316 | /* The .es pseudo-op. Generate a C_ESTART symbol named .es. */ | |
5317 | ||
5318 | static void | |
98027b10 | 5319 | ppc_es (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5320 | { |
5321 | symbolS *sym; | |
5322 | ||
5323 | if (ppc_current_block == NULL) | |
5324 | as_bad (_(".es without preceding .bs")); | |
5325 | ||
5326 | sym = symbol_make (".es"); | |
5327 | S_SET_SEGMENT (sym, now_seg); | |
5328 | S_SET_STORAGE_CLASS (sym, C_ESTAT); | |
809ffe0d ILT |
5329 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
5330 | symbol_get_tc (sym)->output = 1; | |
252b5132 RH |
5331 | |
5332 | ppc_frob_label (sym); | |
5333 | ||
5334 | ppc_current_block = NULL; | |
5335 | ||
5336 | demand_empty_rest_of_line (); | |
5337 | } | |
5338 | ||
5339 | /* The .bb pseudo-op. Generate a C_BLOCK symbol named .bb, with a | |
5340 | line number. */ | |
5341 | ||
5342 | static void | |
98027b10 | 5343 | ppc_bb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5344 | { |
5345 | symbolS *sym; | |
5346 | ||
5347 | sym = symbol_make (".bb"); | |
5348 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5349 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5350 | S_SET_VALUE (sym, frag_now_fix ()); |
5351 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5352 | ||
5353 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5354 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
5355 | ||
809ffe0d | 5356 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5357 | |
5358 | SF_SET_PROCESS (sym); | |
5359 | ||
5360 | ppc_frob_label (sym); | |
5361 | ||
5362 | demand_empty_rest_of_line (); | |
5363 | } | |
5364 | ||
5365 | /* The .eb pseudo-op. Generate a C_BLOCK symbol named .eb, with a | |
5366 | line number. */ | |
5367 | ||
5368 | static void | |
98027b10 | 5369 | ppc_eb (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5370 | { |
5371 | symbolS *sym; | |
5372 | ||
5373 | sym = symbol_make (".eb"); | |
5374 | S_SET_SEGMENT (sym, text_section); | |
809ffe0d | 5375 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5376 | S_SET_VALUE (sym, frag_now_fix ()); |
5377 | S_SET_STORAGE_CLASS (sym, C_BLOCK); | |
5378 | S_SET_NUMBER_AUXILIARY (sym, 1); | |
5379 | SA_SET_SYM_LNNO (sym, get_absolute_expression ()); | |
809ffe0d | 5380 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5381 | |
5382 | SF_SET_PROCESS (sym); | |
5383 | ||
5384 | ppc_frob_label (sym); | |
5385 | ||
5386 | demand_empty_rest_of_line (); | |
5387 | } | |
5388 | ||
5389 | /* The .bc pseudo-op. This just creates a C_BCOMM symbol with a | |
5390 | specified name. */ | |
5391 | ||
5392 | static void | |
98027b10 | 5393 | ppc_bc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5394 | { |
5395 | char *name; | |
5396 | int len; | |
5397 | symbolS *sym; | |
5398 | ||
5399 | name = demand_copy_C_string (&len); | |
5400 | sym = symbol_make (name); | |
5401 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5402 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5403 | S_SET_STORAGE_CLASS (sym, C_BCOMM); |
5404 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5405 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5406 | |
5407 | ppc_frob_label (sym); | |
5408 | ||
5409 | demand_empty_rest_of_line (); | |
5410 | } | |
5411 | ||
5412 | /* The .ec pseudo-op. This just creates a C_ECOMM symbol. */ | |
5413 | ||
5414 | static void | |
98027b10 | 5415 | ppc_ec (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5416 | { |
5417 | symbolS *sym; | |
5418 | ||
5419 | sym = symbol_make (".ec"); | |
5420 | S_SET_SEGMENT (sym, ppc_coff_debug_section); | |
809ffe0d | 5421 | symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING; |
252b5132 RH |
5422 | S_SET_STORAGE_CLASS (sym, C_ECOMM); |
5423 | S_SET_VALUE (sym, 0); | |
809ffe0d | 5424 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5425 | |
5426 | ppc_frob_label (sym); | |
5427 | ||
5428 | demand_empty_rest_of_line (); | |
5429 | } | |
5430 | ||
5431 | /* The .toc pseudo-op. Switch to the .toc subsegment. */ | |
5432 | ||
5433 | static void | |
98027b10 | 5434 | ppc_toc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5435 | { |
5436 | if (ppc_toc_csect != (symbolS *) NULL) | |
809ffe0d | 5437 | subseg_set (data_section, symbol_get_tc (ppc_toc_csect)->subseg); |
252b5132 RH |
5438 | else |
5439 | { | |
5440 | subsegT subseg; | |
5441 | symbolS *sym; | |
5442 | symbolS *list; | |
81d4177b | 5443 | |
1b2cb8e2 CC |
5444 | subseg = ppc_xcoff_data_section.next_subsegment; |
5445 | ++ppc_xcoff_data_section.next_subsegment; | |
252b5132 RH |
5446 | |
5447 | subseg_new (segment_name (data_section), subseg); | |
5448 | ppc_toc_frag = frag_now; | |
5449 | ||
5450 | sym = symbol_find_or_make ("TOC[TC0]"); | |
809ffe0d | 5451 | symbol_set_frag (sym, frag_now); |
252b5132 RH |
5452 | S_SET_SEGMENT (sym, data_section); |
5453 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
809ffe0d ILT |
5454 | symbol_get_tc (sym)->subseg = subseg; |
5455 | symbol_get_tc (sym)->output = 1; | |
5456 | symbol_get_tc (sym)->within = sym; | |
252b5132 RH |
5457 | |
5458 | ppc_toc_csect = sym; | |
81d4177b | 5459 | |
1b2cb8e2 | 5460 | for (list = ppc_xcoff_data_section.csects; |
809ffe0d ILT |
5461 | symbol_get_tc (list)->next != (symbolS *) NULL; |
5462 | list = symbol_get_tc (list)->next) | |
252b5132 | 5463 | ; |
809ffe0d | 5464 | symbol_get_tc (list)->next = sym; |
252b5132 RH |
5465 | |
5466 | symbol_remove (sym, &symbol_rootP, &symbol_lastP); | |
809ffe0d ILT |
5467 | symbol_append (sym, symbol_get_tc (list)->within, &symbol_rootP, |
5468 | &symbol_lastP); | |
252b5132 RH |
5469 | } |
5470 | ||
5471 | ppc_current_csect = ppc_toc_csect; | |
5472 | ||
5473 | demand_empty_rest_of_line (); | |
5474 | } | |
5475 | ||
5476 | /* The AIX assembler automatically aligns the operands of a .long or | |
5477 | .short pseudo-op, and we want to be compatible. */ | |
5478 | ||
5479 | static void | |
98027b10 | 5480 | ppc_xcoff_cons (int log_size) |
252b5132 RH |
5481 | { |
5482 | frag_align (log_size, 0, 0); | |
5483 | record_alignment (now_seg, log_size); | |
5484 | cons (1 << log_size); | |
5485 | } | |
5486 | ||
5487 | static void | |
98027b10 | 5488 | ppc_vbyte (int dummy ATTRIBUTE_UNUSED) |
252b5132 RH |
5489 | { |
5490 | expressionS exp; | |
5491 | int byte_count; | |
5492 | ||
5493 | (void) expression (&exp); | |
5494 | ||
5495 | if (exp.X_op != O_constant) | |
5496 | { | |
5497 | as_bad (_("non-constant byte count")); | |
5498 | return; | |
5499 | } | |
5500 | ||
5501 | byte_count = exp.X_add_number; | |
5502 | ||
5503 | if (*input_line_pointer != ',') | |
5504 | { | |
5505 | as_bad (_("missing value")); | |
5506 | return; | |
5507 | } | |
5508 | ||
5509 | ++input_line_pointer; | |
5510 | cons (byte_count); | |
5511 | } | |
5512 | ||
85645aed TG |
5513 | void |
5514 | ppc_xcoff_end (void) | |
5515 | { | |
5516 | int i; | |
5517 | ||
5518 | for (i = 0; i < XCOFF_DWSECT_NBR_NAMES; i++) | |
5519 | { | |
5520 | struct dw_section *dws = &dw_sections[i]; | |
5521 | struct dw_subsection *dwss; | |
5522 | ||
5523 | if (dws->anon_subseg) | |
5524 | { | |
5525 | dwss = dws->anon_subseg; | |
5526 | dwss->link = dws->list_subseg; | |
5527 | } | |
5528 | else | |
5529 | dwss = dws->list_subseg; | |
5530 | ||
5531 | for (; dwss != NULL; dwss = dwss->link) | |
5532 | if (dwss->end_exp.X_add_symbol != NULL) | |
5533 | { | |
5534 | subseg_set (dws->sect, dwss->subseg); | |
5535 | symbol_set_value_now (dwss->end_exp.X_add_symbol); | |
5536 | } | |
5537 | } | |
22f72c48 | 5538 | ppc_cpu = 0; |
85645aed TG |
5539 | } |
5540 | ||
252b5132 | 5541 | #endif /* OBJ_XCOFF */ |
0baf16f2 | 5542 | #if defined (OBJ_XCOFF) || defined (OBJ_ELF) |
252b5132 RH |
5543 | \f |
5544 | /* The .tc pseudo-op. This is used when generating either XCOFF or | |
5545 | ELF. This takes two or more arguments. | |
5546 | ||
5547 | When generating XCOFF output, the first argument is the name to | |
5548 | give to this location in the toc; this will be a symbol with class | |
0baf16f2 | 5549 | TC. The rest of the arguments are N-byte values to actually put at |
252b5132 | 5550 | this location in the TOC; often there is just one more argument, a |
1049f94e | 5551 | relocatable symbol reference. The size of the value to store |
0baf16f2 AM |
5552 | depends on target word size. A 32-bit target uses 4-byte values, a |
5553 | 64-bit target uses 8-byte values. | |
252b5132 RH |
5554 | |
5555 | When not generating XCOFF output, the arguments are the same, but | |
5556 | the first argument is simply ignored. */ | |
5557 | ||
5558 | static void | |
98027b10 | 5559 | ppc_tc (int ignore ATTRIBUTE_UNUSED) |
252b5132 RH |
5560 | { |
5561 | #ifdef OBJ_XCOFF | |
5562 | ||
5563 | /* Define the TOC symbol name. */ | |
5564 | { | |
5565 | char *name; | |
5566 | char endc; | |
5567 | symbolS *sym; | |
5568 | ||
5569 | if (ppc_toc_csect == (symbolS *) NULL | |
5570 | || ppc_toc_csect != ppc_current_csect) | |
5571 | { | |
5572 | as_bad (_(".tc not in .toc section")); | |
5573 | ignore_rest_of_line (); | |
5574 | return; | |
5575 | } | |
5576 | ||
d02603dc | 5577 | endc = get_symbol_name (&name); |
252b5132 RH |
5578 | |
5579 | sym = symbol_find_or_make (name); | |
5580 | ||
d02603dc | 5581 | (void) restore_line_pointer (endc); |
252b5132 RH |
5582 | |
5583 | if (S_IS_DEFINED (sym)) | |
5584 | { | |
5585 | symbolS *label; | |
5586 | ||
809ffe0d | 5587 | label = symbol_get_tc (ppc_current_csect)->within; |
96d56e9f | 5588 | if (symbol_get_tc (label)->symbol_class != XMC_TC0) |
252b5132 RH |
5589 | { |
5590 | as_bad (_(".tc with no label")); | |
5591 | ignore_rest_of_line (); | |
5592 | return; | |
5593 | } | |
5594 | ||
5595 | S_SET_SEGMENT (label, S_GET_SEGMENT (sym)); | |
809ffe0d | 5596 | symbol_set_frag (label, symbol_get_frag (sym)); |
252b5132 RH |
5597 | S_SET_VALUE (label, S_GET_VALUE (sym)); |
5598 | ||
5599 | while (! is_end_of_line[(unsigned char) *input_line_pointer]) | |
5600 | ++input_line_pointer; | |
5601 | ||
5602 | return; | |
5603 | } | |
5604 | ||
5605 | S_SET_SEGMENT (sym, now_seg); | |
809ffe0d | 5606 | symbol_set_frag (sym, frag_now); |
252b5132 | 5607 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); |
4a403be0 CC |
5608 | |
5609 | /* AIX assembler seems to allow any storage class to be set in .tc. | |
5610 | But for now, only XMC_TC and XMC_TE are supported by us. */ | |
5611 | switch (symbol_get_tc (sym)->symbol_class) | |
5612 | { | |
5613 | case XMC_TC: | |
5614 | case XMC_TE: | |
5615 | break; | |
5616 | ||
5617 | default: | |
5618 | as_bad (_(".tc with storage class %d not yet supported"), | |
5619 | symbol_get_tc (sym)->symbol_class); | |
5620 | ignore_rest_of_line (); | |
5621 | return; | |
5622 | } | |
809ffe0d | 5623 | symbol_get_tc (sym)->output = 1; |
252b5132 RH |
5624 | |
5625 | ppc_frob_label (sym); | |
5626 | } | |
5627 | ||
0baf16f2 AM |
5628 | #endif /* OBJ_XCOFF */ |
5629 | #ifdef OBJ_ELF | |
9c7977b3 | 5630 | int align; |
252b5132 RH |
5631 | |
5632 | /* Skip the TOC symbol name. */ | |
5633 | while (is_part_of_name (*input_line_pointer) | |
d13d4015 | 5634 | || *input_line_pointer == ' ' |
252b5132 RH |
5635 | || *input_line_pointer == '[' |
5636 | || *input_line_pointer == ']' | |
5637 | || *input_line_pointer == '{' | |
5638 | || *input_line_pointer == '}') | |
5639 | ++input_line_pointer; | |
5640 | ||
0baf16f2 | 5641 | /* Align to a four/eight byte boundary. */ |
2b3c4602 | 5642 | align = ppc_obj64 ? 3 : 2; |
9c7977b3 AM |
5643 | frag_align (align, 0, 0); |
5644 | record_alignment (now_seg, align); | |
0baf16f2 | 5645 | #endif /* OBJ_ELF */ |
252b5132 RH |
5646 | |
5647 | if (*input_line_pointer != ',') | |
5648 | demand_empty_rest_of_line (); | |
5649 | else | |
5650 | { | |
5651 | ++input_line_pointer; | |
2b3c4602 | 5652 | cons (ppc_obj64 ? 8 : 4); |
252b5132 RH |
5653 | } |
5654 | } | |
0baf16f2 AM |
5655 | |
5656 | /* Pseudo-op .machine. */ | |
0baf16f2 AM |
5657 | |
5658 | static void | |
98027b10 | 5659 | ppc_machine (int ignore ATTRIBUTE_UNUSED) |
0baf16f2 | 5660 | { |
d02603dc | 5661 | char c; |
69c040df AM |
5662 | char *cpu_string; |
5663 | #define MAX_HISTORY 100 | |
fa452fa6 | 5664 | static ppc_cpu_t *cpu_history; |
69c040df AM |
5665 | static int curr_hist; |
5666 | ||
5667 | SKIP_WHITESPACE (); | |
5668 | ||
d02603dc NC |
5669 | c = get_symbol_name (&cpu_string); |
5670 | cpu_string = xstrdup (cpu_string); | |
5671 | (void) restore_line_pointer (c); | |
69c040df AM |
5672 | |
5673 | if (cpu_string != NULL) | |
5674 | { | |
fa452fa6 | 5675 | ppc_cpu_t old_cpu = ppc_cpu; |
69fe9ce5 | 5676 | ppc_cpu_t new_cpu; |
69c040df AM |
5677 | char *p; |
5678 | ||
5679 | for (p = cpu_string; *p != 0; p++) | |
5680 | *p = TOLOWER (*p); | |
5681 | ||
5682 | if (strcmp (cpu_string, "push") == 0) | |
5683 | { | |
5684 | if (cpu_history == NULL) | |
325801bd | 5685 | cpu_history = XNEWVEC (ppc_cpu_t, MAX_HISTORY); |
69c040df AM |
5686 | |
5687 | if (curr_hist >= MAX_HISTORY) | |
5688 | as_bad (_(".machine stack overflow")); | |
5689 | else | |
5690 | cpu_history[curr_hist++] = ppc_cpu; | |
5691 | } | |
5692 | else if (strcmp (cpu_string, "pop") == 0) | |
5693 | { | |
5694 | if (curr_hist <= 0) | |
5695 | as_bad (_(".machine stack underflow")); | |
5696 | else | |
5697 | ppc_cpu = cpu_history[--curr_hist]; | |
5698 | } | |
776fc418 | 5699 | else if ((new_cpu = ppc_parse_cpu (ppc_cpu, &sticky, cpu_string)) != 0) |
69fe9ce5 | 5700 | ppc_cpu = new_cpu; |
69c040df AM |
5701 | else |
5702 | as_bad (_("invalid machine `%s'"), cpu_string); | |
5703 | ||
5704 | if (ppc_cpu != old_cpu) | |
5705 | ppc_setup_opcodes (); | |
5706 | } | |
5707 | ||
5708 | demand_empty_rest_of_line (); | |
0baf16f2 | 5709 | } |
0baf16f2 | 5710 | #endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ |
252b5132 | 5711 | \f |
252b5132 RH |
5712 | #ifdef OBJ_XCOFF |
5713 | ||
5714 | /* XCOFF specific symbol and file handling. */ | |
5715 | ||
5716 | /* Canonicalize the symbol name. We use the to force the suffix, if | |
5717 | any, to use square brackets, and to be in upper case. */ | |
5718 | ||
5719 | char * | |
98027b10 | 5720 | ppc_canonicalize_symbol_name (char *name) |
252b5132 RH |
5721 | { |
5722 | char *s; | |
5723 | ||
5724 | if (ppc_stab_symbol) | |
5725 | return name; | |
5726 | ||
5727 | for (s = name; *s != '\0' && *s != '{' && *s != '['; s++) | |
5728 | ; | |
5729 | if (*s != '\0') | |
5730 | { | |
5731 | char brac; | |
5732 | ||
5733 | if (*s == '[') | |
5734 | brac = ']'; | |
5735 | else | |
5736 | { | |
5737 | *s = '['; | |
5738 | brac = '}'; | |
5739 | } | |
5740 | ||
5741 | for (s++; *s != '\0' && *s != brac; s++) | |
3882b010 | 5742 | *s = TOUPPER (*s); |
252b5132 RH |
5743 | |
5744 | if (*s == '\0' || s[1] != '\0') | |
5745 | as_bad (_("bad symbol suffix")); | |
5746 | ||
5747 | *s = ']'; | |
5748 | } | |
5749 | ||
5750 | return name; | |
5751 | } | |
5752 | ||
5753 | /* Set the class of a symbol based on the suffix, if any. This is | |
5754 | called whenever a new symbol is created. */ | |
5755 | ||
5756 | void | |
98027b10 | 5757 | ppc_symbol_new_hook (symbolS *sym) |
252b5132 | 5758 | { |
809ffe0d | 5759 | struct ppc_tc_sy *tc; |
252b5132 RH |
5760 | const char *s; |
5761 | ||
809ffe0d ILT |
5762 | tc = symbol_get_tc (sym); |
5763 | tc->next = NULL; | |
5764 | tc->output = 0; | |
96d56e9f | 5765 | tc->symbol_class = -1; |
809ffe0d ILT |
5766 | tc->real_name = NULL; |
5767 | tc->subseg = 0; | |
5768 | tc->align = 0; | |
85645aed TG |
5769 | tc->u.size = NULL; |
5770 | tc->u.dw = NULL; | |
809ffe0d | 5771 | tc->within = NULL; |
252b5132 RH |
5772 | |
5773 | if (ppc_stab_symbol) | |
5774 | return; | |
5775 | ||
5776 | s = strchr (S_GET_NAME (sym), '['); | |
5777 | if (s == (const char *) NULL) | |
5778 | { | |
5779 | /* There is no suffix. */ | |
5780 | return; | |
5781 | } | |
5782 | ||
5783 | ++s; | |
5784 | ||
5785 | switch (s[0]) | |
5786 | { | |
5787 | case 'B': | |
5788 | if (strcmp (s, "BS]") == 0) | |
96d56e9f | 5789 | tc->symbol_class = XMC_BS; |
252b5132 RH |
5790 | break; |
5791 | case 'D': | |
5792 | if (strcmp (s, "DB]") == 0) | |
96d56e9f | 5793 | tc->symbol_class = XMC_DB; |
252b5132 | 5794 | else if (strcmp (s, "DS]") == 0) |
96d56e9f | 5795 | tc->symbol_class = XMC_DS; |
252b5132 RH |
5796 | break; |
5797 | case 'G': | |
5798 | if (strcmp (s, "GL]") == 0) | |
96d56e9f | 5799 | tc->symbol_class = XMC_GL; |
252b5132 RH |
5800 | break; |
5801 | case 'P': | |
5802 | if (strcmp (s, "PR]") == 0) | |
96d56e9f | 5803 | tc->symbol_class = XMC_PR; |
252b5132 RH |
5804 | break; |
5805 | case 'R': | |
5806 | if (strcmp (s, "RO]") == 0) | |
96d56e9f | 5807 | tc->symbol_class = XMC_RO; |
252b5132 | 5808 | else if (strcmp (s, "RW]") == 0) |
96d56e9f | 5809 | tc->symbol_class = XMC_RW; |
252b5132 RH |
5810 | break; |
5811 | case 'S': | |
5812 | if (strcmp (s, "SV]") == 0) | |
96d56e9f | 5813 | tc->symbol_class = XMC_SV; |
252b5132 RH |
5814 | break; |
5815 | case 'T': | |
5816 | if (strcmp (s, "TC]") == 0) | |
96d56e9f | 5817 | tc->symbol_class = XMC_TC; |
252b5132 | 5818 | else if (strcmp (s, "TI]") == 0) |
96d56e9f | 5819 | tc->symbol_class = XMC_TI; |
252b5132 | 5820 | else if (strcmp (s, "TB]") == 0) |
96d56e9f | 5821 | tc->symbol_class = XMC_TB; |
252b5132 | 5822 | else if (strcmp (s, "TC0]") == 0 || strcmp (s, "T0]") == 0) |
96d56e9f | 5823 | tc->symbol_class = XMC_TC0; |
4a403be0 CC |
5824 | else if (strcmp (s, "TE]") == 0) |
5825 | tc->symbol_class = XMC_TE; | |
1b2cb8e2 CC |
5826 | else if (strcmp (s, "TL]") == 0) |
5827 | tc->symbol_class = XMC_TL; | |
252b5132 RH |
5828 | break; |
5829 | case 'U': | |
5830 | if (strcmp (s, "UA]") == 0) | |
96d56e9f | 5831 | tc->symbol_class = XMC_UA; |
252b5132 | 5832 | else if (strcmp (s, "UC]") == 0) |
96d56e9f | 5833 | tc->symbol_class = XMC_UC; |
1b2cb8e2 CC |
5834 | else if (strcmp (s, "UL]") == 0) |
5835 | tc->symbol_class = XMC_UL; | |
252b5132 RH |
5836 | break; |
5837 | case 'X': | |
5838 | if (strcmp (s, "XO]") == 0) | |
96d56e9f | 5839 | tc->symbol_class = XMC_XO; |
252b5132 RH |
5840 | break; |
5841 | } | |
5842 | ||
96d56e9f | 5843 | if (tc->symbol_class == -1) |
d6ed37ed | 5844 | as_bad (_("unrecognized symbol suffix")); |
252b5132 RH |
5845 | } |
5846 | ||
252b5132 RH |
5847 | /* This variable is set by ppc_frob_symbol if any absolute symbols are |
5848 | seen. It tells ppc_adjust_symtab whether it needs to look through | |
5849 | the symbols. */ | |
5850 | ||
5b7c81bd | 5851 | static bool ppc_saw_abs; |
252b5132 RH |
5852 | |
5853 | /* Change the name of a symbol just before writing it out. Set the | |
5854 | real name if the .rename pseudo-op was used. Otherwise, remove any | |
5855 | class suffix. Return 1 if the symbol should not be included in the | |
5856 | symbol table. */ | |
5857 | ||
5858 | int | |
98027b10 | 5859 | ppc_frob_symbol (symbolS *sym) |
252b5132 RH |
5860 | { |
5861 | static symbolS *ppc_last_function; | |
5862 | static symbolS *set_end; | |
5863 | ||
5864 | /* Discard symbols that should not be included in the output symbol | |
5865 | table. */ | |
809ffe0d ILT |
5866 | if (! symbol_used_in_reloc_p (sym) |
5867 | && ((symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) != 0 | |
670ec21d | 5868 | || (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 5869 | && ! symbol_get_tc (sym)->output |
252b5132 RH |
5870 | && S_GET_STORAGE_CLASS (sym) != C_FILE))) |
5871 | return 1; | |
5872 | ||
a161fe53 AM |
5873 | /* This one will disappear anyway. Don't make a csect sym for it. */ |
5874 | if (sym == abs_section_sym) | |
5875 | return 1; | |
5876 | ||
809ffe0d ILT |
5877 | if (symbol_get_tc (sym)->real_name != (char *) NULL) |
5878 | S_SET_NAME (sym, symbol_get_tc (sym)->real_name); | |
252b5132 RH |
5879 | else |
5880 | { | |
5881 | const char *name; | |
5882 | const char *s; | |
5883 | ||
5884 | name = S_GET_NAME (sym); | |
5885 | s = strchr (name, '['); | |
5886 | if (s != (char *) NULL) | |
5887 | { | |
5888 | unsigned int len; | |
5889 | char *snew; | |
5890 | ||
5891 | len = s - name; | |
a44e2901 | 5892 | snew = xstrndup (name, len); |
252b5132 RH |
5893 | |
5894 | S_SET_NAME (sym, snew); | |
5895 | } | |
5896 | } | |
5897 | ||
5898 | if (set_end != (symbolS *) NULL) | |
5899 | { | |
5900 | SA_SET_SYM_ENDNDX (set_end, sym); | |
5901 | set_end = NULL; | |
5902 | } | |
5903 | ||
5904 | if (SF_GET_FUNCTION (sym)) | |
5905 | { | |
5906 | if (ppc_last_function != (symbolS *) NULL) | |
5907 | as_bad (_("two .function pseudo-ops with no intervening .ef")); | |
5908 | ppc_last_function = sym; | |
85645aed | 5909 | if (symbol_get_tc (sym)->u.size != (symbolS *) NULL) |
252b5132 | 5910 | { |
85645aed | 5911 | resolve_symbol_value (symbol_get_tc (sym)->u.size); |
809ffe0d | 5912 | SA_SET_SYM_FSIZE (sym, |
85645aed | 5913 | (long) S_GET_VALUE (symbol_get_tc (sym)->u.size)); |
252b5132 RH |
5914 | } |
5915 | } | |
5916 | else if (S_GET_STORAGE_CLASS (sym) == C_FCN | |
5917 | && strcmp (S_GET_NAME (sym), ".ef") == 0) | |
5918 | { | |
5919 | if (ppc_last_function == (symbolS *) NULL) | |
5920 | as_bad (_(".ef with no preceding .function")); | |
5921 | else | |
5922 | { | |
5923 | set_end = ppc_last_function; | |
5924 | ppc_last_function = NULL; | |
5925 | ||
5926 | /* We don't have a C_EFCN symbol, but we need to force the | |
5927 | COFF backend to believe that it has seen one. */ | |
5928 | coff_last_function = NULL; | |
5929 | } | |
5930 | } | |
5931 | ||
670ec21d | 5932 | if (! (S_IS_EXTERNAL (sym) || S_IS_WEAK (sym)) |
809ffe0d | 5933 | && (symbol_get_bfdsym (sym)->flags & BSF_SECTION_SYM) == 0 |
252b5132 RH |
5934 | && S_GET_STORAGE_CLASS (sym) != C_FILE |
5935 | && S_GET_STORAGE_CLASS (sym) != C_FCN | |
5936 | && S_GET_STORAGE_CLASS (sym) != C_BLOCK | |
5937 | && S_GET_STORAGE_CLASS (sym) != C_BSTAT | |
5938 | && S_GET_STORAGE_CLASS (sym) != C_ESTAT | |
5939 | && S_GET_STORAGE_CLASS (sym) != C_BINCL | |
5940 | && S_GET_STORAGE_CLASS (sym) != C_EINCL | |
5941 | && S_GET_SEGMENT (sym) != ppc_coff_debug_section) | |
5942 | S_SET_STORAGE_CLASS (sym, C_HIDEXT); | |
5943 | ||
5944 | if (S_GET_STORAGE_CLASS (sym) == C_EXT | |
8602d4fe | 5945 | || S_GET_STORAGE_CLASS (sym) == C_AIX_WEAKEXT |
252b5132 RH |
5946 | || S_GET_STORAGE_CLASS (sym) == C_HIDEXT) |
5947 | { | |
5948 | int i; | |
5949 | union internal_auxent *a; | |
5950 | ||
5951 | /* Create a csect aux. */ | |
5952 | i = S_GET_NUMBER_AUXILIARY (sym); | |
5953 | S_SET_NUMBER_AUXILIARY (sym, i + 1); | |
809ffe0d | 5954 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].u.auxent; |
96d56e9f | 5955 | if (symbol_get_tc (sym)->symbol_class == XMC_TC0) |
252b5132 RH |
5956 | { |
5957 | /* This is the TOC table. */ | |
5958 | know (strcmp (S_GET_NAME (sym), "TOC") == 0); | |
5959 | a->x_csect.x_scnlen.l = 0; | |
5960 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
5961 | } | |
809ffe0d | 5962 | else if (symbol_get_tc (sym)->subseg != 0) |
252b5132 RH |
5963 | { |
5964 | /* This is a csect symbol. x_scnlen is the size of the | |
5965 | csect. */ | |
809ffe0d | 5966 | if (symbol_get_tc (sym)->next == (symbolS *) NULL) |
fd361982 | 5967 | a->x_csect.x_scnlen.l = (bfd_section_size (S_GET_SEGMENT (sym)) |
252b5132 RH |
5968 | - S_GET_VALUE (sym)); |
5969 | else | |
5970 | { | |
6386f3a7 | 5971 | resolve_symbol_value (symbol_get_tc (sym)->next); |
809ffe0d | 5972 | a->x_csect.x_scnlen.l = (S_GET_VALUE (symbol_get_tc (sym)->next) |
252b5132 RH |
5973 | - S_GET_VALUE (sym)); |
5974 | } | |
809ffe0d | 5975 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_SD; |
252b5132 | 5976 | } |
1b2cb8e2 CC |
5977 | else if (S_GET_SEGMENT (sym) == bss_section |
5978 | || S_GET_SEGMENT (sym) == ppc_xcoff_tbss_section.segment) | |
252b5132 RH |
5979 | { |
5980 | /* This is a common symbol. */ | |
809ffe0d ILT |
5981 | a->x_csect.x_scnlen.l = symbol_get_frag (sym)->fr_offset; |
5982 | a->x_csect.x_smtyp = (symbol_get_tc (sym)->align << 3) | XTY_CM; | |
1b2cb8e2 CC |
5983 | if (S_GET_SEGMENT (sym) == ppc_xcoff_tbss_section.segment) |
5984 | symbol_get_tc (sym)->symbol_class = XMC_UL; | |
5985 | else if (S_IS_EXTERNAL (sym)) | |
96d56e9f | 5986 | symbol_get_tc (sym)->symbol_class = XMC_RW; |
252b5132 | 5987 | else |
96d56e9f | 5988 | symbol_get_tc (sym)->symbol_class = XMC_BS; |
252b5132 RH |
5989 | } |
5990 | else if (S_GET_SEGMENT (sym) == absolute_section) | |
5991 | { | |
5992 | /* This is an absolute symbol. The csect will be created by | |
99a814a1 | 5993 | ppc_adjust_symtab. */ |
5b7c81bd | 5994 | ppc_saw_abs = true; |
252b5132 | 5995 | a->x_csect.x_smtyp = XTY_LD; |
96d56e9f NC |
5996 | if (symbol_get_tc (sym)->symbol_class == -1) |
5997 | symbol_get_tc (sym)->symbol_class = XMC_XO; | |
252b5132 RH |
5998 | } |
5999 | else if (! S_IS_DEFINED (sym)) | |
6000 | { | |
6001 | /* This is an external symbol. */ | |
6002 | a->x_csect.x_scnlen.l = 0; | |
6003 | a->x_csect.x_smtyp = XTY_ER; | |
6004 | } | |
4a403be0 | 6005 | else if (ppc_is_toc_sym (sym)) |
252b5132 RH |
6006 | { |
6007 | symbolS *next; | |
6008 | ||
6009 | /* This is a TOC definition. x_scnlen is the size of the | |
6010 | TOC entry. */ | |
6011 | next = symbol_next (sym); | |
96d56e9f | 6012 | while (symbol_get_tc (next)->symbol_class == XMC_TC0) |
252b5132 RH |
6013 | next = symbol_next (next); |
6014 | if (next == (symbolS *) NULL | |
4a403be0 | 6015 | || (!ppc_is_toc_sym (next))) |
252b5132 RH |
6016 | { |
6017 | if (ppc_after_toc_frag == (fragS *) NULL) | |
fd361982 | 6018 | a->x_csect.x_scnlen.l = (bfd_section_size (data_section) |
252b5132 RH |
6019 | - S_GET_VALUE (sym)); |
6020 | else | |
6021 | a->x_csect.x_scnlen.l = (ppc_after_toc_frag->fr_address | |
6022 | - S_GET_VALUE (sym)); | |
6023 | } | |
6024 | else | |
6025 | { | |
6386f3a7 | 6026 | resolve_symbol_value (next); |
252b5132 RH |
6027 | a->x_csect.x_scnlen.l = (S_GET_VALUE (next) |
6028 | - S_GET_VALUE (sym)); | |
6029 | } | |
6030 | a->x_csect.x_smtyp = (2 << 3) | XTY_SD; | |
6031 | } | |
6032 | else | |
6033 | { | |
6034 | symbolS *csect; | |
6035 | ||
6036 | /* This is a normal symbol definition. x_scnlen is the | |
6037 | symbol index of the containing csect. */ | |
6038 | if (S_GET_SEGMENT (sym) == text_section) | |
1b2cb8e2 | 6039 | csect = ppc_xcoff_text_section.csects; |
252b5132 | 6040 | else if (S_GET_SEGMENT (sym) == data_section) |
1b2cb8e2 CC |
6041 | csect = ppc_xcoff_data_section.csects; |
6042 | else if (S_GET_SEGMENT (sym) == ppc_xcoff_tdata_section.segment) | |
6043 | csect = ppc_xcoff_tdata_section.csects; | |
252b5132 RH |
6044 | else |
6045 | abort (); | |
6046 | ||
6047 | /* Skip the initial dummy symbol. */ | |
809ffe0d | 6048 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6049 | |
6050 | if (csect == (symbolS *) NULL) | |
6051 | { | |
6052 | as_warn (_("warning: symbol %s has no csect"), S_GET_NAME (sym)); | |
6053 | a->x_csect.x_scnlen.l = 0; | |
6054 | } | |
6055 | else | |
6056 | { | |
809ffe0d | 6057 | while (symbol_get_tc (csect)->next != (symbolS *) NULL) |
252b5132 | 6058 | { |
6386f3a7 | 6059 | resolve_symbol_value (symbol_get_tc (csect)->next); |
809ffe0d ILT |
6060 | if (S_GET_VALUE (symbol_get_tc (csect)->next) |
6061 | > S_GET_VALUE (sym)) | |
252b5132 | 6062 | break; |
809ffe0d | 6063 | csect = symbol_get_tc (csect)->next; |
252b5132 RH |
6064 | } |
6065 | ||
809ffe0d ILT |
6066 | a->x_csect.x_scnlen.p = |
6067 | coffsymbol (symbol_get_bfdsym (csect))->native; | |
6068 | coffsymbol (symbol_get_bfdsym (sym))->native[i + 1].fix_scnlen = | |
6069 | 1; | |
252b5132 RH |
6070 | } |
6071 | a->x_csect.x_smtyp = XTY_LD; | |
6072 | } | |
81d4177b | 6073 | |
252b5132 RH |
6074 | a->x_csect.x_parmhash = 0; |
6075 | a->x_csect.x_snhash = 0; | |
96d56e9f | 6076 | if (symbol_get_tc (sym)->symbol_class == -1) |
252b5132 RH |
6077 | a->x_csect.x_smclas = XMC_PR; |
6078 | else | |
96d56e9f | 6079 | a->x_csect.x_smclas = symbol_get_tc (sym)->symbol_class; |
252b5132 RH |
6080 | a->x_csect.x_stab = 0; |
6081 | a->x_csect.x_snstab = 0; | |
6082 | ||
6083 | /* Don't let the COFF backend resort these symbols. */ | |
809ffe0d | 6084 | symbol_get_bfdsym (sym)->flags |= BSF_NOT_AT_END; |
252b5132 RH |
6085 | } |
6086 | else if (S_GET_STORAGE_CLASS (sym) == C_BSTAT) | |
6087 | { | |
6088 | /* We want the value to be the symbol index of the referenced | |
6089 | csect symbol. BFD will do that for us if we set the right | |
6090 | flags. */ | |
b782de16 AM |
6091 | asymbol *bsym = symbol_get_bfdsym (symbol_get_tc (sym)->within); |
6092 | combined_entry_type *c = coffsymbol (bsym)->native; | |
6093 | ||
6094 | S_SET_VALUE (sym, (valueT) (size_t) c); | |
809ffe0d | 6095 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_value = 1; |
252b5132 RH |
6096 | } |
6097 | else if (S_GET_STORAGE_CLASS (sym) == C_STSYM) | |
6098 | { | |
6099 | symbolS *block; | |
c734e7e3 | 6100 | valueT base; |
252b5132 | 6101 | |
809ffe0d | 6102 | block = symbol_get_tc (sym)->within; |
c734e7e3 TG |
6103 | if (block) |
6104 | { | |
6105 | /* The value is the offset from the enclosing csect. */ | |
6106 | symbolS *csect; | |
6107 | ||
6108 | csect = symbol_get_tc (block)->within; | |
6109 | resolve_symbol_value (csect); | |
6110 | base = S_GET_VALUE (csect); | |
6111 | } | |
6112 | else | |
6113 | base = 0; | |
6114 | ||
6115 | S_SET_VALUE (sym, S_GET_VALUE (sym) - base); | |
252b5132 RH |
6116 | } |
6117 | else if (S_GET_STORAGE_CLASS (sym) == C_BINCL | |
6118 | || S_GET_STORAGE_CLASS (sym) == C_EINCL) | |
6119 | { | |
6120 | /* We want the value to be a file offset into the line numbers. | |
99a814a1 AM |
6121 | BFD will do that for us if we set the right flags. We have |
6122 | already set the value correctly. */ | |
809ffe0d | 6123 | coffsymbol (symbol_get_bfdsym (sym))->native->fix_line = 1; |
252b5132 RH |
6124 | } |
6125 | ||
6126 | return 0; | |
6127 | } | |
6128 | ||
6129 | /* Adjust the symbol table. This creates csect symbols for all | |
6130 | absolute symbols. */ | |
6131 | ||
6132 | void | |
98027b10 | 6133 | ppc_adjust_symtab (void) |
252b5132 RH |
6134 | { |
6135 | symbolS *sym; | |
6136 | ||
6137 | if (! ppc_saw_abs) | |
6138 | return; | |
6139 | ||
6140 | for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) | |
6141 | { | |
6142 | symbolS *csect; | |
6143 | int i; | |
6144 | union internal_auxent *a; | |
6145 | ||
6146 | if (S_GET_SEGMENT (sym) != absolute_section) | |
6147 | continue; | |
6148 | ||
6149 | csect = symbol_create (".abs[XO]", absolute_section, | |
e01e1cee | 6150 | &zero_address_frag, S_GET_VALUE (sym)); |
809ffe0d | 6151 | symbol_get_bfdsym (csect)->value = S_GET_VALUE (sym); |
252b5132 RH |
6152 | S_SET_STORAGE_CLASS (csect, C_HIDEXT); |
6153 | i = S_GET_NUMBER_AUXILIARY (csect); | |
6154 | S_SET_NUMBER_AUXILIARY (csect, i + 1); | |
809ffe0d | 6155 | a = &coffsymbol (symbol_get_bfdsym (csect))->native[i + 1].u.auxent; |
252b5132 RH |
6156 | a->x_csect.x_scnlen.l = 0; |
6157 | a->x_csect.x_smtyp = XTY_SD; | |
6158 | a->x_csect.x_parmhash = 0; | |
6159 | a->x_csect.x_snhash = 0; | |
6160 | a->x_csect.x_smclas = XMC_XO; | |
6161 | a->x_csect.x_stab = 0; | |
6162 | a->x_csect.x_snstab = 0; | |
6163 | ||
6164 | symbol_insert (csect, sym, &symbol_rootP, &symbol_lastP); | |
6165 | ||
6166 | i = S_GET_NUMBER_AUXILIARY (sym); | |
809ffe0d ILT |
6167 | a = &coffsymbol (symbol_get_bfdsym (sym))->native[i].u.auxent; |
6168 | a->x_csect.x_scnlen.p = coffsymbol (symbol_get_bfdsym (csect))->native; | |
6169 | coffsymbol (symbol_get_bfdsym (sym))->native[i].fix_scnlen = 1; | |
252b5132 RH |
6170 | } |
6171 | ||
5b7c81bd | 6172 | ppc_saw_abs = false; |
252b5132 RH |
6173 | } |
6174 | ||
6175 | /* Set the VMA for a section. This is called on all the sections in | |
6176 | turn. */ | |
6177 | ||
6178 | void | |
98027b10 | 6179 | ppc_frob_section (asection *sec) |
252b5132 | 6180 | { |
931e13a6 | 6181 | static bfd_vma vma = 0; |
252b5132 | 6182 | |
85645aed | 6183 | /* Dwarf sections start at 0. */ |
fd361982 | 6184 | if (bfd_section_flags (sec) & SEC_DEBUGGING) |
85645aed TG |
6185 | return; |
6186 | ||
931e13a6 | 6187 | vma = md_section_align (sec, vma); |
fd361982 AM |
6188 | bfd_set_section_vma (sec, vma); |
6189 | vma += bfd_section_size (sec); | |
252b5132 RH |
6190 | } |
6191 | ||
6192 | #endif /* OBJ_XCOFF */ | |
6193 | \f | |
6d4af3c2 | 6194 | const char * |
98027b10 | 6195 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 6196 | { |
499ac353 | 6197 | return ieee_md_atof (type, litp, sizep, target_big_endian); |
252b5132 RH |
6198 | } |
6199 | ||
6200 | /* Write a value out to the object file, using the appropriate | |
6201 | endianness. */ | |
6202 | ||
6203 | void | |
98027b10 | 6204 | md_number_to_chars (char *buf, valueT val, int n) |
252b5132 RH |
6205 | { |
6206 | if (target_big_endian) | |
6207 | number_to_chars_bigendian (buf, val, n); | |
6208 | else | |
6209 | number_to_chars_littleendian (buf, val, n); | |
6210 | } | |
6211 | ||
6212 | /* Align a section (I don't know why this is machine dependent). */ | |
6213 | ||
6214 | valueT | |
3aeeedbb | 6215 | md_section_align (asection *seg ATTRIBUTE_UNUSED, valueT addr) |
252b5132 | 6216 | { |
3aeeedbb AM |
6217 | #ifdef OBJ_ELF |
6218 | return addr; | |
6219 | #else | |
fd361982 | 6220 | int align = bfd_section_alignment (seg); |
252b5132 | 6221 | |
8d3842cd | 6222 | return ((addr + (1 << align) - 1) & -(1 << align)); |
3aeeedbb | 6223 | #endif |
252b5132 RH |
6224 | } |
6225 | ||
6226 | /* We don't have any form of relaxing. */ | |
6227 | ||
6228 | int | |
98027b10 AM |
6229 | md_estimate_size_before_relax (fragS *fragp ATTRIBUTE_UNUSED, |
6230 | asection *seg ATTRIBUTE_UNUSED) | |
252b5132 RH |
6231 | { |
6232 | abort (); | |
6233 | return 0; | |
6234 | } | |
6235 | ||
6236 | /* Convert a machine dependent frag. We never generate these. */ | |
6237 | ||
6238 | void | |
98027b10 AM |
6239 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
6240 | asection *sec ATTRIBUTE_UNUSED, | |
6241 | fragS *fragp ATTRIBUTE_UNUSED) | |
252b5132 RH |
6242 | { |
6243 | abort (); | |
6244 | } | |
6245 | ||
6246 | /* We have no need to default values of symbols. */ | |
6247 | ||
252b5132 | 6248 | symbolS * |
98027b10 | 6249 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
6250 | { |
6251 | return 0; | |
6252 | } | |
6253 | \f | |
6254 | /* Functions concerning relocs. */ | |
6255 | ||
6256 | /* The location from which a PC relative jump should be calculated, | |
6257 | given a PC relative reloc. */ | |
6258 | ||
6259 | long | |
98027b10 | 6260 | md_pcrel_from_section (fixS *fixp, segT sec ATTRIBUTE_UNUSED) |
252b5132 RH |
6261 | { |
6262 | return fixp->fx_frag->fr_address + fixp->fx_where; | |
6263 | } | |
6264 | ||
6265 | #ifdef OBJ_XCOFF | |
6266 | ||
6267 | /* This is called to see whether a fixup should be adjusted to use a | |
6268 | section symbol. We take the opportunity to change a fixup against | |
6269 | a symbol in the TOC subsegment into a reloc against the | |
6270 | corresponding .tc symbol. */ | |
6271 | ||
6272 | int | |
98027b10 | 6273 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6274 | { |
b782de16 AM |
6275 | valueT val = resolve_symbol_value (fix->fx_addsy); |
6276 | segT symseg = S_GET_SEGMENT (fix->fx_addsy); | |
6277 | TC_SYMFIELD_TYPE *tc; | |
6278 | ||
6279 | if (symseg == absolute_section) | |
6280 | return 0; | |
252b5132 | 6281 | |
85645aed | 6282 | /* Always adjust symbols in debugging sections. */ |
fd361982 | 6283 | if (bfd_section_flags (symseg) & SEC_DEBUGGING) |
85645aed TG |
6284 | return 1; |
6285 | ||
252b5132 | 6286 | if (ppc_toc_csect != (symbolS *) NULL |
252b5132 | 6287 | && fix->fx_addsy != ppc_toc_csect |
b782de16 | 6288 | && symseg == data_section |
252b5132 RH |
6289 | && val >= ppc_toc_frag->fr_address |
6290 | && (ppc_after_toc_frag == (fragS *) NULL | |
6291 | || val < ppc_after_toc_frag->fr_address)) | |
6292 | { | |
6293 | symbolS *sy; | |
6294 | ||
6295 | for (sy = symbol_next (ppc_toc_csect); | |
6296 | sy != (symbolS *) NULL; | |
6297 | sy = symbol_next (sy)) | |
6298 | { | |
b782de16 AM |
6299 | TC_SYMFIELD_TYPE *sy_tc = symbol_get_tc (sy); |
6300 | ||
96d56e9f | 6301 | if (sy_tc->symbol_class == XMC_TC0) |
252b5132 | 6302 | continue; |
4a403be0 CC |
6303 | if (sy_tc->symbol_class != XMC_TC |
6304 | && sy_tc->symbol_class != XMC_TE) | |
252b5132 | 6305 | break; |
b782de16 | 6306 | if (val == resolve_symbol_value (sy)) |
252b5132 RH |
6307 | { |
6308 | fix->fx_addsy = sy; | |
6309 | fix->fx_addnumber = val - ppc_toc_frag->fr_address; | |
6310 | return 0; | |
6311 | } | |
6312 | } | |
6313 | ||
6314 | as_bad_where (fix->fx_file, fix->fx_line, | |
6315 | _("symbol in .toc does not match any .tc")); | |
6316 | } | |
6317 | ||
6318 | /* Possibly adjust the reloc to be against the csect. */ | |
b782de16 AM |
6319 | tc = symbol_get_tc (fix->fx_addsy); |
6320 | if (tc->subseg == 0 | |
96d56e9f NC |
6321 | && tc->symbol_class != XMC_TC0 |
6322 | && tc->symbol_class != XMC_TC | |
4a403be0 | 6323 | && tc->symbol_class != XMC_TE |
b782de16 | 6324 | && symseg != bss_section |
1b2cb8e2 | 6325 | && symseg != ppc_xcoff_tbss_section.segment |
252b5132 | 6326 | /* Don't adjust if this is a reloc in the toc section. */ |
b782de16 | 6327 | && (symseg != data_section |
252b5132 RH |
6328 | || ppc_toc_csect == NULL |
6329 | || val < ppc_toc_frag->fr_address | |
6330 | || (ppc_after_toc_frag != NULL | |
6331 | && val >= ppc_after_toc_frag->fr_address))) | |
6332 | { | |
2fb4b302 | 6333 | symbolS *csect = tc->within; |
252b5132 | 6334 | |
2fb4b302 TG |
6335 | /* If the symbol was not declared by a label (eg: a section symbol), |
6336 | use the section instead of the csect. This doesn't happen in | |
6337 | normal AIX assembly code. */ | |
6338 | if (csect == NULL) | |
6339 | csect = seg_info (symseg)->sym; | |
252b5132 | 6340 | |
2fb4b302 TG |
6341 | fix->fx_offset += val - symbol_get_frag (csect)->fr_address; |
6342 | fix->fx_addsy = csect; | |
252b5132 | 6343 | |
b782de16 | 6344 | return 0; |
252b5132 RH |
6345 | } |
6346 | ||
6347 | /* Adjust a reloc against a .lcomm symbol to be against the base | |
6348 | .lcomm. */ | |
b782de16 | 6349 | if (symseg == bss_section |
252b5132 RH |
6350 | && ! S_IS_EXTERNAL (fix->fx_addsy)) |
6351 | { | |
b782de16 AM |
6352 | symbolS *sy = symbol_get_frag (fix->fx_addsy)->fr_symbol; |
6353 | ||
6354 | fix->fx_offset += val - resolve_symbol_value (sy); | |
6355 | fix->fx_addsy = sy; | |
252b5132 RH |
6356 | } |
6357 | ||
6358 | return 0; | |
6359 | } | |
6360 | ||
6361 | /* A reloc from one csect to another must be kept. The assembler | |
6362 | will, of course, keep relocs between sections, and it will keep | |
6363 | absolute relocs, but we need to force it to keep PC relative relocs | |
6364 | between two csects in the same section. */ | |
6365 | ||
6366 | int | |
98027b10 | 6367 | ppc_force_relocation (fixS *fix) |
252b5132 RH |
6368 | { |
6369 | /* At this point fix->fx_addsy should already have been converted to | |
6370 | a csect symbol. If the csect does not include the fragment, then | |
6371 | we need to force the relocation. */ | |
6372 | if (fix->fx_pcrel | |
6373 | && fix->fx_addsy != NULL | |
809ffe0d ILT |
6374 | && symbol_get_tc (fix->fx_addsy)->subseg != 0 |
6375 | && ((symbol_get_frag (fix->fx_addsy)->fr_address | |
6376 | > fix->fx_frag->fr_address) | |
6377 | || (symbol_get_tc (fix->fx_addsy)->next != NULL | |
6378 | && (symbol_get_frag (symbol_get_tc (fix->fx_addsy)->next)->fr_address | |
252b5132 RH |
6379 | <= fix->fx_frag->fr_address)))) |
6380 | return 1; | |
6381 | ||
ae6063d4 | 6382 | return generic_force_reloc (fix); |
252b5132 | 6383 | } |
252b5132 RH |
6384 | #endif /* OBJ_XCOFF */ |
6385 | ||
0baf16f2 | 6386 | #ifdef OBJ_ELF |
a161fe53 AM |
6387 | /* If this function returns non-zero, it guarantees that a relocation |
6388 | will be emitted for a fixup. */ | |
6389 | ||
6390 | int | |
98027b10 | 6391 | ppc_force_relocation (fixS *fix) |
a161fe53 AM |
6392 | { |
6393 | /* Branch prediction relocations must force a relocation, as must | |
6394 | the vtable description relocs. */ | |
6395 | switch (fix->fx_r_type) | |
6396 | { | |
6397 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6398 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6399 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6400 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
c744ecf2 | 6401 | case BFD_RELOC_24_PLT_PCREL: |
a161fe53 | 6402 | case BFD_RELOC_PPC64_TOC: |
a161fe53 | 6403 | return 1; |
6911b7dc AM |
6404 | case BFD_RELOC_PPC_B26: |
6405 | case BFD_RELOC_PPC_BA26: | |
6406 | case BFD_RELOC_PPC_B16: | |
6407 | case BFD_RELOC_PPC_BA16: | |
05d0e962 | 6408 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
6409 | /* All branch fixups targeting a localentry symbol must |
6410 | force a relocation. */ | |
6411 | if (fix->fx_addsy) | |
6412 | { | |
6413 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6414 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6415 | gas_assert (elfsym); |
6416 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6417 | return 1; | |
6418 | } | |
6419 | break; | |
a161fe53 AM |
6420 | default: |
6421 | break; | |
6422 | } | |
6423 | ||
cdba85ec | 6424 | if (fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6425 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL) |
cdba85ec AM |
6426 | return 1; |
6427 | ||
ae6063d4 | 6428 | return generic_force_reloc (fix); |
a161fe53 AM |
6429 | } |
6430 | ||
0baf16f2 | 6431 | int |
98027b10 | 6432 | ppc_fix_adjustable (fixS *fix) |
252b5132 | 6433 | { |
6911b7dc AM |
6434 | switch (fix->fx_r_type) |
6435 | { | |
6436 | /* All branch fixups targeting a localentry symbol must | |
6437 | continue using the symbol. */ | |
6438 | case BFD_RELOC_PPC_B26: | |
6439 | case BFD_RELOC_PPC_BA26: | |
6440 | case BFD_RELOC_PPC_B16: | |
6441 | case BFD_RELOC_PPC_BA16: | |
6442 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
6443 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
6444 | case BFD_RELOC_PPC_BA16_BRTAKEN: | |
6445 | case BFD_RELOC_PPC_BA16_BRNTAKEN: | |
05d0e962 | 6446 | case BFD_RELOC_PPC64_REL24_NOTOC: |
6911b7dc AM |
6447 | if (fix->fx_addsy) |
6448 | { | |
6449 | asymbol *bfdsym = symbol_get_bfdsym (fix->fx_addsy); | |
c1229f84 | 6450 | elf_symbol_type *elfsym = elf_symbol_from (bfdsym); |
6911b7dc AM |
6451 | gas_assert (elfsym); |
6452 | if ((STO_PPC64_LOCAL_MASK & elfsym->internal_elf_sym.st_other) != 0) | |
6453 | return 0; | |
6454 | } | |
6455 | break; | |
6456 | default: | |
6457 | break; | |
6458 | } | |
6459 | ||
0baf16f2 AM |
6460 | return (fix->fx_r_type != BFD_RELOC_16_GOTOFF |
6461 | && fix->fx_r_type != BFD_RELOC_LO16_GOTOFF | |
6462 | && fix->fx_r_type != BFD_RELOC_HI16_GOTOFF | |
6463 | && fix->fx_r_type != BFD_RELOC_HI16_S_GOTOFF | |
cc9edbf3 AM |
6464 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_DS |
6465 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT16_LO_DS | |
5663e321 | 6466 | && fix->fx_r_type != BFD_RELOC_PPC64_GOT_PCREL34 |
334d91b9 AM |
6467 | && fix->fx_r_type != BFD_RELOC_24_PLT_PCREL |
6468 | && fix->fx_r_type != BFD_RELOC_32_PLTOFF | |
6469 | && fix->fx_r_type != BFD_RELOC_32_PLT_PCREL | |
6470 | && fix->fx_r_type != BFD_RELOC_LO16_PLTOFF | |
6471 | && fix->fx_r_type != BFD_RELOC_HI16_PLTOFF | |
6472 | && fix->fx_r_type != BFD_RELOC_HI16_S_PLTOFF | |
6473 | && fix->fx_r_type != BFD_RELOC_64_PLTOFF | |
6474 | && fix->fx_r_type != BFD_RELOC_64_PLT_PCREL | |
6475 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT16_LO_DS | |
5663e321 | 6476 | && fix->fx_r_type != BFD_RELOC_PPC64_PLT_PCREL34 |
334d91b9 AM |
6477 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16 |
6478 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO | |
6479 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HI | |
6480 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_HA | |
6481 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_DS | |
6482 | && fix->fx_r_type != BFD_RELOC_PPC64_PLTGOT16_LO_DS | |
0baf16f2 | 6483 | && fix->fx_r_type != BFD_RELOC_GPREL16 |
334d91b9 AM |
6484 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_LO16A |
6485 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HI16A | |
6486 | && fix->fx_r_type != BFD_RELOC_PPC_VLE_SDAREL_HA16A | |
0baf16f2 AM |
6487 | && fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT |
6488 | && fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY | |
cdba85ec | 6489 | && !(fix->fx_r_type >= BFD_RELOC_PPC_TLS |
c213164a | 6490 | && fix->fx_r_type <= BFD_RELOC_PPC64_TLS_PCREL)); |
252b5132 | 6491 | } |
0baf16f2 | 6492 | #endif |
252b5132 | 6493 | |
b9c361e0 JL |
6494 | void |
6495 | ppc_frag_check (struct frag *fragP) | |
6496 | { | |
a9479dc0 AM |
6497 | if ((fragP->fr_address & fragP->insn_addr) != 0) |
6498 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
6499 | _("instruction address is not a multiple of %d"), | |
6500 | fragP->insn_addr + 1); | |
b9c361e0 JL |
6501 | } |
6502 | ||
22f72c48 AM |
6503 | /* rs_align_code frag handling. */ |
6504 | ||
6505 | enum ppc_nop_encoding_for_rs_align_code | |
6506 | { | |
6507 | PPC_NOP_VANILLA, | |
6508 | PPC_NOP_VLE, | |
6509 | PPC_NOP_GROUP_P6, | |
6510 | PPC_NOP_GROUP_P7 | |
6511 | }; | |
6512 | ||
6513 | unsigned int | |
6514 | ppc_nop_select (void) | |
6515 | { | |
6516 | if ((ppc_cpu & PPC_OPCODE_VLE) != 0) | |
6517 | return PPC_NOP_VLE; | |
6518 | if ((ppc_cpu & (PPC_OPCODE_POWER9 | PPC_OPCODE_E500MC)) == 0) | |
6519 | { | |
6520 | if ((ppc_cpu & PPC_OPCODE_POWER7) != 0) | |
6521 | return PPC_NOP_GROUP_P7; | |
6522 | if ((ppc_cpu & PPC_OPCODE_POWER6) != 0) | |
6523 | return PPC_NOP_GROUP_P6; | |
6524 | } | |
6525 | return PPC_NOP_VANILLA; | |
6526 | } | |
3aeeedbb AM |
6527 | |
6528 | void | |
6529 | ppc_handle_align (struct frag *fragP) | |
6530 | { | |
6531 | valueT count = (fragP->fr_next->fr_address | |
6532 | - (fragP->fr_address + fragP->fr_fix)); | |
22f72c48 AM |
6533 | char *dest = fragP->fr_literal + fragP->fr_fix; |
6534 | enum ppc_nop_encoding_for_rs_align_code nop_select = *dest & 0xff; | |
6535 | ||
6536 | /* Pad with zeros if not inserting a whole number of instructions. | |
6537 | We could pad with zeros up to an instruction boundary then follow | |
6538 | with nops but odd counts indicate data in an executable section | |
6539 | so padding with zeros is most appropriate. */ | |
6540 | if (count == 0 | |
de626965 | 6541 | || (nop_select == PPC_NOP_VLE ? (count & 1) != 0 : (count & 3) != 0)) |
22f72c48 AM |
6542 | { |
6543 | *dest = 0; | |
6544 | return; | |
6545 | } | |
3aeeedbb | 6546 | |
22f72c48 | 6547 | if (nop_select == PPC_NOP_VLE) |
b9c361e0 | 6548 | { |
b9c361e0 JL |
6549 | |
6550 | fragP->fr_var = 2; | |
6551 | md_number_to_chars (dest, 0x4400, 2); | |
6552 | } | |
22f72c48 | 6553 | else |
3aeeedbb | 6554 | { |
3aeeedbb | 6555 | fragP->fr_var = 4; |
cef4f754 AM |
6556 | |
6557 | if (count > 4 * nop_limit && count < 0x2000000) | |
6558 | { | |
6559 | struct frag *rest; | |
6560 | ||
6561 | /* Make a branch, then follow with nops. Insert another | |
6562 | frag to handle the nops. */ | |
6563 | md_number_to_chars (dest, 0x48000000 + count, 4); | |
6564 | count -= 4; | |
6565 | if (count == 0) | |
6566 | return; | |
6567 | ||
6568 | rest = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6569 | memcpy (rest, fragP, SIZEOF_STRUCT_FRAG); | |
6570 | fragP->fr_next = rest; | |
6571 | fragP = rest; | |
6572 | rest->fr_address += rest->fr_fix + 4; | |
6573 | rest->fr_fix = 0; | |
6574 | /* If we leave the next frag as rs_align_code we'll come here | |
6575 | again, resulting in a bunch of branches rather than a | |
6576 | branch followed by nops. */ | |
6577 | rest->fr_type = rs_align; | |
6578 | dest = rest->fr_literal; | |
6579 | } | |
6580 | ||
3aeeedbb AM |
6581 | md_number_to_chars (dest, 0x60000000, 4); |
6582 | ||
22f72c48 | 6583 | if (nop_select >= PPC_NOP_GROUP_P6) |
3aeeedbb | 6584 | { |
3fea0c3b AM |
6585 | /* For power6, power7, and power8, we want the last nop to |
6586 | be a group terminating one. Do this by inserting an | |
6587 | rs_fill frag immediately after this one, with its address | |
6588 | set to the last nop location. This will automatically | |
6589 | reduce the number of nops in the current frag by one. */ | |
3aeeedbb AM |
6590 | if (count > 4) |
6591 | { | |
6592 | struct frag *group_nop = xmalloc (SIZEOF_STRUCT_FRAG + 4); | |
6593 | ||
6594 | memcpy (group_nop, fragP, SIZEOF_STRUCT_FRAG); | |
6595 | group_nop->fr_address = group_nop->fr_next->fr_address - 4; | |
6596 | group_nop->fr_fix = 0; | |
6597 | group_nop->fr_offset = 1; | |
6598 | group_nop->fr_type = rs_fill; | |
6599 | fragP->fr_next = group_nop; | |
6600 | dest = group_nop->fr_literal; | |
6601 | } | |
6602 | ||
22f72c48 | 6603 | if (nop_select == PPC_NOP_GROUP_P6) |
42240548 PB |
6604 | /* power6 group terminating nop: "ori 1,1,0". */ |
6605 | md_number_to_chars (dest, 0x60210000, 4); | |
22f72c48 AM |
6606 | else |
6607 | /* power7/power8 group terminating nop: "ori 2,2,0". */ | |
6608 | md_number_to_chars (dest, 0x60420000, 4); | |
3aeeedbb AM |
6609 | } |
6610 | } | |
6611 | } | |
6612 | ||
252b5132 | 6613 | /* Apply a fixup to the object code. This is called for all the |
3b8b57a9 | 6614 | fixups we generated by the calls to fix_new_exp, above. */ |
252b5132 | 6615 | |
94f592af | 6616 | void |
62ebcb5c | 6617 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
252b5132 | 6618 | { |
94f592af | 6619 | valueT value = * valP; |
5656a981 AM |
6620 | offsetT fieldval; |
6621 | const struct powerpc_operand *operand; | |
252b5132 RH |
6622 | |
6623 | #ifdef OBJ_ELF | |
94f592af | 6624 | if (fixP->fx_addsy != NULL) |
252b5132 | 6625 | { |
a161fe53 | 6626 | /* Hack around bfd_install_relocation brain damage. */ |
94f592af NC |
6627 | if (fixP->fx_pcrel) |
6628 | value += fixP->fx_frag->fr_address + fixP->fx_where; | |
a680de9a PB |
6629 | |
6630 | if (fixP->fx_addsy == abs_section_sym) | |
6631 | fixP->fx_done = 1; | |
252b5132 RH |
6632 | } |
6633 | else | |
94f592af | 6634 | fixP->fx_done = 1; |
252b5132 | 6635 | #else |
a161fe53 | 6636 | /* FIXME FIXME FIXME: The value we are passed in *valP includes |
7be1c489 AM |
6637 | the symbol values. If we are doing this relocation the code in |
6638 | write.c is going to call bfd_install_relocation, which is also | |
6639 | going to use the symbol value. That means that if the reloc is | |
6640 | fully resolved we want to use *valP since bfd_install_relocation is | |
6641 | not being used. | |
9f0eb232 RS |
6642 | However, if the reloc is not fully resolved we do not want to |
6643 | use *valP, and must use fx_offset instead. If the relocation | |
6644 | is PC-relative, we then need to re-apply md_pcrel_from_section | |
6645 | to this new relocation value. */ | |
94f592af NC |
6646 | if (fixP->fx_addsy == (symbolS *) NULL) |
6647 | fixP->fx_done = 1; | |
6648 | ||
252b5132 | 6649 | else |
9f0eb232 RS |
6650 | { |
6651 | value = fixP->fx_offset; | |
6652 | if (fixP->fx_pcrel) | |
6653 | value -= md_pcrel_from_section (fixP, seg); | |
6654 | } | |
a161fe53 AM |
6655 | #endif |
6656 | ||
7ba71655 AM |
6657 | /* We are only able to convert some relocs to pc-relative. */ |
6658 | if (fixP->fx_pcrel) | |
6659 | { | |
6660 | switch (fixP->fx_r_type) | |
6661 | { | |
4a969973 AM |
6662 | case BFD_RELOC_64: |
6663 | fixP->fx_r_type = BFD_RELOC_64_PCREL; | |
6664 | break; | |
6665 | ||
6666 | case BFD_RELOC_32: | |
6667 | fixP->fx_r_type = BFD_RELOC_32_PCREL; | |
6668 | break; | |
6669 | ||
6670 | case BFD_RELOC_16: | |
6671 | fixP->fx_r_type = BFD_RELOC_16_PCREL; | |
6672 | break; | |
6673 | ||
7ba71655 AM |
6674 | case BFD_RELOC_LO16: |
6675 | fixP->fx_r_type = BFD_RELOC_LO16_PCREL; | |
6676 | break; | |
6677 | ||
6678 | case BFD_RELOC_HI16: | |
6679 | fixP->fx_r_type = BFD_RELOC_HI16_PCREL; | |
6680 | break; | |
6681 | ||
6682 | case BFD_RELOC_HI16_S: | |
6683 | fixP->fx_r_type = BFD_RELOC_HI16_S_PCREL; | |
6684 | break; | |
6685 | ||
4a969973 AM |
6686 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
6687 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGH; | |
7ba71655 AM |
6688 | break; |
6689 | ||
4a969973 AM |
6690 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
6691 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHA; | |
7ba71655 AM |
6692 | break; |
6693 | ||
4a969973 AM |
6694 | case BFD_RELOC_PPC64_HIGHER: |
6695 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER; | |
6696 | break; | |
6697 | ||
6698 | case BFD_RELOC_PPC64_HIGHER_S: | |
6699 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA; | |
6700 | break; | |
6701 | ||
6702 | case BFD_RELOC_PPC64_HIGHEST: | |
6703 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST; | |
6704 | break; | |
6705 | ||
6706 | case BFD_RELOC_PPC64_HIGHEST_S: | |
6707 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA; | |
7ba71655 AM |
6708 | break; |
6709 | ||
5663e321 AM |
6710 | case BFD_RELOC_PPC64_ADDR16_HIGHER34: |
6711 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHER34; | |
6712 | break; | |
6713 | ||
6714 | case BFD_RELOC_PPC64_ADDR16_HIGHERA34: | |
6715 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHERA34; | |
6716 | break; | |
6717 | ||
6718 | case BFD_RELOC_PPC64_ADDR16_HIGHEST34: | |
6719 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHEST34; | |
6720 | break; | |
6721 | ||
6722 | case BFD_RELOC_PPC64_ADDR16_HIGHESTA34: | |
6723 | fixP->fx_r_type = BFD_RELOC_PPC64_REL16_HIGHESTA34; | |
6724 | break; | |
6725 | ||
7ba71655 AM |
6726 | case BFD_RELOC_PPC_16DX_HA: |
6727 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
6728 | break; | |
6729 | ||
5663e321 AM |
6730 | case BFD_RELOC_PPC64_D34: |
6731 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL34; | |
6732 | break; | |
6733 | ||
6734 | case BFD_RELOC_PPC64_D28: | |
6735 | fixP->fx_r_type = BFD_RELOC_PPC64_PCREL28; | |
6736 | break; | |
6737 | ||
7ba71655 AM |
6738 | default: |
6739 | break; | |
6740 | } | |
6741 | } | |
6742 | else if (!fixP->fx_done | |
6743 | && fixP->fx_r_type == BFD_RELOC_PPC_16DX_HA) | |
252b5132 | 6744 | { |
7ba71655 AM |
6745 | /* addpcis is relative to next insn address. */ |
6746 | value -= 4; | |
6747 | fixP->fx_r_type = BFD_RELOC_PPC_REL16DX_HA; | |
6748 | fixP->fx_pcrel = 1; | |
252b5132 | 6749 | } |
252b5132 | 6750 | |
5656a981 | 6751 | operand = NULL; |
3b8b57a9 | 6752 | if (fixP->fx_pcrel_adjust != 0) |
252b5132 | 6753 | { |
5656a981 | 6754 | /* This is a fixup on an instruction. */ |
3b8b57a9 | 6755 | int opindex = fixP->fx_pcrel_adjust & 0xff; |
252b5132 | 6756 | |
5656a981 | 6757 | operand = &powerpc_operands[opindex]; |
252b5132 | 6758 | #ifdef OBJ_XCOFF |
0baf16f2 AM |
6759 | /* An instruction like `lwz 9,sym(30)' when `sym' is not a TOC symbol |
6760 | does not generate a reloc. It uses the offset of `sym' within its | |
6761 | csect. Other usages, such as `.long sym', generate relocs. This | |
6762 | is the documented behaviour of non-TOC symbols. */ | |
252b5132 | 6763 | if ((operand->flags & PPC_OPERAND_PARENS) != 0 |
b84bf58a | 6764 | && (operand->bitm & 0xfff0) == 0xfff0 |
252b5132 | 6765 | && operand->shift == 0 |
2b3c4602 | 6766 | && (operand->insert == NULL || ppc_obj64) |
94f592af NC |
6767 | && fixP->fx_addsy != NULL |
6768 | && symbol_get_tc (fixP->fx_addsy)->subseg != 0 | |
4a403be0 | 6769 | && !ppc_is_toc_sym (fixP->fx_addsy) |
94f592af | 6770 | && S_GET_SEGMENT (fixP->fx_addsy) != bss_section) |
252b5132 | 6771 | { |
94f592af NC |
6772 | value = fixP->fx_offset; |
6773 | fixP->fx_done = 1; | |
252b5132 | 6774 | } |
ac21e7da TG |
6775 | |
6776 | /* During parsing of instructions, a TOC16 reloc is generated for | |
6777 | instructions such as 'lwz RT,SYM(RB)' if SYM is a symbol defined | |
6778 | in the toc. But at parse time, SYM may be not yet defined, so | |
6779 | check again here. */ | |
6780 | if (fixP->fx_r_type == BFD_RELOC_16 | |
6781 | && fixP->fx_addsy != NULL | |
6782 | && ppc_is_toc_sym (fixP->fx_addsy)) | |
4a403be0 | 6783 | fixP->fx_r_type = BFD_RELOC_PPC_TOC16; |
252b5132 | 6784 | #endif |
5656a981 AM |
6785 | } |
6786 | ||
6787 | /* Calculate value to be stored in field. */ | |
6788 | fieldval = value; | |
6789 | switch (fixP->fx_r_type) | |
6790 | { | |
1ec2d25e | 6791 | #ifdef OBJ_ELF |
5656a981 AM |
6792 | case BFD_RELOC_PPC64_ADDR16_LO_DS: |
6793 | case BFD_RELOC_PPC_VLE_LO16A: | |
6794 | case BFD_RELOC_PPC_VLE_LO16D: | |
1ec2d25e | 6795 | #endif |
5656a981 AM |
6796 | case BFD_RELOC_LO16: |
6797 | case BFD_RELOC_LO16_PCREL: | |
6798 | fieldval = value & 0xffff; | |
6799 | sign_extend_16: | |
6800 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
f9c6b907 | 6801 | fieldval = SEX16 (fieldval); |
5656a981 AM |
6802 | fixP->fx_no_overflow = 1; |
6803 | break; | |
3c9d25f4 | 6804 | |
f9c6b907 AM |
6805 | case BFD_RELOC_HI16: |
6806 | case BFD_RELOC_HI16_PCREL: | |
5656a981 | 6807 | #ifdef OBJ_ELF |
f9c6b907 AM |
6808 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
6809 | { | |
6810 | fieldval = value >> 16; | |
6811 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
6812 | { | |
6813 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
6814 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
6815 | } | |
6816 | break; | |
6817 | } | |
2b0f3761 | 6818 | /* Fallthru */ |
f9c6b907 | 6819 | |
5656a981 AM |
6820 | case BFD_RELOC_PPC_VLE_HI16A: |
6821 | case BFD_RELOC_PPC_VLE_HI16D: | |
f9c6b907 | 6822 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
5656a981 | 6823 | #endif |
5656a981 AM |
6824 | fieldval = PPC_HI (value); |
6825 | goto sign_extend_16; | |
0baf16f2 | 6826 | |
f9c6b907 AM |
6827 | case BFD_RELOC_HI16_S: |
6828 | case BFD_RELOC_HI16_S_PCREL: | |
7ba71655 | 6829 | case BFD_RELOC_PPC_16DX_HA: |
a680de9a | 6830 | case BFD_RELOC_PPC_REL16DX_HA: |
5656a981 | 6831 | #ifdef OBJ_ELF |
f9c6b907 AM |
6832 | if (REPORT_OVERFLOW_HI && ppc_obj64) |
6833 | { | |
6834 | fieldval = (value + 0x8000) >> 16; | |
6835 | if (operand != NULL && (operand->flags & PPC_OPERAND_SIGNED) != 0) | |
6836 | { | |
6837 | valueT sign = (((valueT) -1 >> 16) + 1) >> 1; | |
6838 | fieldval = ((valueT) fieldval ^ sign) - sign; | |
6839 | } | |
6840 | break; | |
6841 | } | |
2b0f3761 | 6842 | /* Fallthru */ |
f9c6b907 | 6843 | |
5656a981 AM |
6844 | case BFD_RELOC_PPC_VLE_HA16A: |
6845 | case BFD_RELOC_PPC_VLE_HA16D: | |
f9c6b907 | 6846 | case BFD_RELOC_PPC64_ADDR16_HIGHA: |
5656a981 | 6847 | #endif |
5656a981 AM |
6848 | fieldval = PPC_HA (value); |
6849 | goto sign_extend_16; | |
0baf16f2 | 6850 | |
3b8b57a9 | 6851 | #ifdef OBJ_ELF |
5656a981 AM |
6852 | case BFD_RELOC_PPC64_HIGHER: |
6853 | fieldval = PPC_HIGHER (value); | |
6854 | goto sign_extend_16; | |
252b5132 | 6855 | |
5656a981 AM |
6856 | case BFD_RELOC_PPC64_HIGHER_S: |
6857 | fieldval = PPC_HIGHERA (value); | |
6858 | goto sign_extend_16; | |
0baf16f2 | 6859 | |
5656a981 AM |
6860 | case BFD_RELOC_PPC64_HIGHEST: |
6861 | fieldval = PPC_HIGHEST (value); | |
6862 | goto sign_extend_16; | |
0baf16f2 | 6863 | |
5656a981 AM |
6864 | case BFD_RELOC_PPC64_HIGHEST_S: |
6865 | fieldval = PPC_HIGHESTA (value); | |
6866 | goto sign_extend_16; | |
6867 | #endif | |
6868 | ||
6869 | default: | |
6870 | break; | |
6871 | } | |
6872 | ||
6873 | if (operand != NULL) | |
6874 | { | |
6875 | /* Handle relocs in an insn. */ | |
5656a981 AM |
6876 | switch (fixP->fx_r_type) |
6877 | { | |
7fa9fcb6 | 6878 | #ifdef OBJ_ELF |
3b8b57a9 AM |
6879 | /* The following relocs can't be calculated by the assembler. |
6880 | Leave the field zero. */ | |
cdba85ec AM |
6881 | case BFD_RELOC_PPC_TPREL16: |
6882 | case BFD_RELOC_PPC_TPREL16_LO: | |
6883 | case BFD_RELOC_PPC_TPREL16_HI: | |
6884 | case BFD_RELOC_PPC_TPREL16_HA: | |
cdba85ec AM |
6885 | case BFD_RELOC_PPC_DTPREL16: |
6886 | case BFD_RELOC_PPC_DTPREL16_LO: | |
6887 | case BFD_RELOC_PPC_DTPREL16_HI: | |
6888 | case BFD_RELOC_PPC_DTPREL16_HA: | |
cdba85ec AM |
6889 | case BFD_RELOC_PPC_GOT_TLSGD16: |
6890 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
6891 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
6892 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
6893 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
6894 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
6895 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
6896 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
6897 | case BFD_RELOC_PPC_GOT_TPREL16: | |
6898 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
6899 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
6900 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
6901 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
6902 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
6903 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
6904 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
6905 | case BFD_RELOC_PPC64_TPREL16_DS: | |
6906 | case BFD_RELOC_PPC64_TPREL16_LO_DS: | |
f9c6b907 AM |
6907 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
6908 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
cdba85ec AM |
6909 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
6910 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
6911 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
6912 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
f9c6b907 AM |
6913 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
6914 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
cdba85ec AM |
6915 | case BFD_RELOC_PPC64_DTPREL16_DS: |
6916 | case BFD_RELOC_PPC64_DTPREL16_LO_DS: | |
6917 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: | |
6918 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
6919 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
6920 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
c213164a AM |
6921 | case BFD_RELOC_PPC64_TPREL34: |
6922 | case BFD_RELOC_PPC64_DTPREL34: | |
87c69f97 AM |
6923 | case BFD_RELOC_PPC64_GOT_TLSGD_PCREL34: |
6924 | case BFD_RELOC_PPC64_GOT_TLSLD_PCREL34: | |
6925 | case BFD_RELOC_PPC64_GOT_TPREL_PCREL34: | |
6926 | case BFD_RELOC_PPC64_GOT_DTPREL_PCREL34: | |
3b8b57a9 | 6927 | gas_assert (fixP->fx_addsy != NULL); |
7c1d0959 | 6928 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
3b8b57a9 | 6929 | fieldval = 0; |
cdba85ec | 6930 | break; |
3b8b57a9 AM |
6931 | |
6932 | /* These also should leave the field zero for the same | |
6933 | reason. Note that older versions of gas wrote values | |
6934 | here. If we want to go back to the old behaviour, then | |
6935 | all _LO and _LO_DS cases will need to be treated like | |
6936 | BFD_RELOC_LO16_PCREL above. Similarly for _HI etc. */ | |
6937 | case BFD_RELOC_16_GOTOFF: | |
6938 | case BFD_RELOC_LO16_GOTOFF: | |
6939 | case BFD_RELOC_HI16_GOTOFF: | |
6940 | case BFD_RELOC_HI16_S_GOTOFF: | |
6941 | case BFD_RELOC_LO16_PLTOFF: | |
6942 | case BFD_RELOC_HI16_PLTOFF: | |
6943 | case BFD_RELOC_HI16_S_PLTOFF: | |
6944 | case BFD_RELOC_GPREL16: | |
6945 | case BFD_RELOC_16_BASEREL: | |
6946 | case BFD_RELOC_LO16_BASEREL: | |
6947 | case BFD_RELOC_HI16_BASEREL: | |
6948 | case BFD_RELOC_HI16_S_BASEREL: | |
6949 | case BFD_RELOC_PPC_TOC16: | |
6950 | case BFD_RELOC_PPC64_TOC16_LO: | |
6951 | case BFD_RELOC_PPC64_TOC16_HI: | |
6952 | case BFD_RELOC_PPC64_TOC16_HA: | |
6953 | case BFD_RELOC_PPC64_PLTGOT16: | |
6954 | case BFD_RELOC_PPC64_PLTGOT16_LO: | |
6955 | case BFD_RELOC_PPC64_PLTGOT16_HI: | |
6956 | case BFD_RELOC_PPC64_PLTGOT16_HA: | |
6957 | case BFD_RELOC_PPC64_GOT16_DS: | |
6958 | case BFD_RELOC_PPC64_GOT16_LO_DS: | |
6959 | case BFD_RELOC_PPC64_PLT16_LO_DS: | |
6960 | case BFD_RELOC_PPC64_SECTOFF_DS: | |
6961 | case BFD_RELOC_PPC64_SECTOFF_LO_DS: | |
6962 | case BFD_RELOC_PPC64_TOC16_DS: | |
6963 | case BFD_RELOC_PPC64_TOC16_LO_DS: | |
6964 | case BFD_RELOC_PPC64_PLTGOT16_DS: | |
6965 | case BFD_RELOC_PPC64_PLTGOT16_LO_DS: | |
6966 | case BFD_RELOC_PPC_EMB_NADDR16: | |
6967 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
6968 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
6969 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
6970 | case BFD_RELOC_PPC_EMB_SDAI16: | |
6971 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
6972 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
252b5132 | 6973 | case BFD_RELOC_PPC_EMB_SDA21: |
3b8b57a9 AM |
6974 | case BFD_RELOC_PPC_EMB_MRKREF: |
6975 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
6976 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
6977 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
6978 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
6979 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
6980 | case BFD_RELOC_PPC_EMB_RELSDA: | |
6981 | case BFD_RELOC_PPC_VLE_SDA21: | |
6982 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
6983 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
6984 | case BFD_RELOC_PPC_VLE_SDAREL_LO16D: | |
6985 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
6986 | case BFD_RELOC_PPC_VLE_SDAREL_HI16D: | |
6987 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
6988 | case BFD_RELOC_PPC_VLE_SDAREL_HA16D: | |
5663e321 AM |
6989 | case BFD_RELOC_PPC64_GOT_PCREL34: |
6990 | case BFD_RELOC_PPC64_PLT_PCREL34: | |
3b8b57a9 | 6991 | gas_assert (fixP->fx_addsy != NULL); |
2b0f3761 | 6992 | /* Fallthru */ |
3b8b57a9 AM |
6993 | |
6994 | case BFD_RELOC_PPC_TLS: | |
6995 | case BFD_RELOC_PPC_TLSGD: | |
6996 | case BFD_RELOC_PPC_TLSLD: | |
c213164a | 6997 | case BFD_RELOC_PPC64_TLS_PCREL: |
3b8b57a9 | 6998 | fieldval = 0; |
3b8b57a9 | 6999 | break; |
7fa9fcb6 TG |
7000 | #endif |
7001 | ||
7002 | #ifdef OBJ_XCOFF | |
7003 | case BFD_RELOC_PPC_B16: | |
7004 | /* Adjust the offset to the instruction boundary. */ | |
7005 | fieldval += 2; | |
7006 | break; | |
7007 | #endif | |
252b5132 | 7008 | |
f728387b AM |
7009 | case BFD_RELOC_VTABLE_INHERIT: |
7010 | case BFD_RELOC_VTABLE_ENTRY: | |
7011 | case BFD_RELOC_PPC_DTPMOD: | |
7012 | case BFD_RELOC_PPC_TPREL: | |
7013 | case BFD_RELOC_PPC_DTPREL: | |
7014 | case BFD_RELOC_PPC_COPY: | |
7015 | case BFD_RELOC_PPC_GLOB_DAT: | |
7016 | case BFD_RELOC_32_PLT_PCREL: | |
7017 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7018 | case BFD_RELOC_PPC64_TOC: | |
7019 | case BFD_RELOC_CTOR: | |
7020 | case BFD_RELOC_32: | |
7021 | case BFD_RELOC_32_PCREL: | |
7022 | case BFD_RELOC_RVA: | |
7023 | case BFD_RELOC_64: | |
7024 | case BFD_RELOC_64_PCREL: | |
7025 | case BFD_RELOC_PPC64_ADDR64_LOCAL: | |
7026 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7027 | _("%s unsupported as instruction fixup"), | |
7028 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
7029 | fixP->fx_done = 1; | |
7030 | return; | |
7031 | ||
3b8b57a9 | 7032 | default: |
252b5132 | 7033 | break; |
3b8b57a9 | 7034 | } |
252b5132 | 7035 | |
3b8b57a9 AM |
7036 | #ifdef OBJ_ELF |
7037 | /* powerpc uses RELA style relocs, so if emitting a reloc the field | |
7038 | contents can stay at zero. */ | |
7039 | #define APPLY_RELOC fixP->fx_done | |
7040 | #else | |
7041 | #define APPLY_RELOC 1 | |
7042 | #endif | |
5663e321 AM |
7043 | /* We need to call the insert function even when fieldval is |
7044 | zero if the insert function would translate that zero to a | |
7045 | bit pattern other than all zeros. */ | |
3b8b57a9 AM |
7046 | if ((fieldval != 0 && APPLY_RELOC) || operand->insert != NULL) |
7047 | { | |
5663e321 | 7048 | uint64_t insn; |
487b24d8 AM |
7049 | unsigned char *where; |
7050 | ||
3b8b57a9 AM |
7051 | /* Fetch the instruction, insert the fully resolved operand |
7052 | value, and stuff the instruction back again. */ | |
487b24d8 | 7053 | where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; |
3b8b57a9 | 7054 | if (target_big_endian) |
31a91399 | 7055 | { |
5663e321 | 7056 | if (fixP->fx_size < 4) |
487b24d8 | 7057 | insn = bfd_getb16 (where); |
5663e321 AM |
7058 | else |
7059 | { | |
7060 | insn = bfd_getb32 (where); | |
7061 | if (fixP->fx_size > 4) | |
7062 | insn = insn << 32 | bfd_getb32 (where + 4); | |
7063 | } | |
31a91399 NC |
7064 | } |
7065 | else | |
3b8b57a9 | 7066 | { |
5663e321 | 7067 | if (fixP->fx_size < 4) |
487b24d8 | 7068 | insn = bfd_getl16 (where); |
5663e321 AM |
7069 | else |
7070 | { | |
7071 | insn = bfd_getl32 (where); | |
7072 | if (fixP->fx_size > 4) | |
7073 | insn = insn << 32 | bfd_getl32 (where + 4); | |
7074 | } | |
3b8b57a9 AM |
7075 | } |
7076 | insn = ppc_insert_operand (insn, operand, fieldval, | |
7077 | fixP->tc_fix_data.ppc_cpu, | |
7078 | fixP->fx_file, fixP->fx_line); | |
7079 | if (target_big_endian) | |
7080 | { | |
5663e321 | 7081 | if (fixP->fx_size < 4) |
487b24d8 | 7082 | bfd_putb16 (insn, where); |
5663e321 AM |
7083 | else |
7084 | { | |
7085 | if (fixP->fx_size > 4) | |
7086 | { | |
7087 | bfd_putb32 (insn, where + 4); | |
7088 | insn >>= 32; | |
7089 | } | |
7090 | bfd_putb32 (insn, where); | |
7091 | } | |
3b8b57a9 AM |
7092 | } |
7093 | else | |
7094 | { | |
5663e321 | 7095 | if (fixP->fx_size < 4) |
487b24d8 | 7096 | bfd_putl16 (insn, where); |
5663e321 AM |
7097 | else |
7098 | { | |
7099 | if (fixP->fx_size > 4) | |
7100 | { | |
7101 | bfd_putl32 (insn, where + 4); | |
7102 | insn >>= 32; | |
7103 | } | |
7104 | bfd_putl32 (insn, where); | |
7105 | } | |
3b8b57a9 AM |
7106 | } |
7107 | } | |
7108 | ||
7109 | if (fixP->fx_done) | |
7110 | /* Nothing else to do here. */ | |
7111 | return; | |
7112 | ||
7113 | gas_assert (fixP->fx_addsy != NULL); | |
62ebcb5c | 7114 | if (fixP->fx_r_type == BFD_RELOC_NONE) |
3b8b57a9 | 7115 | { |
3b4dbbbf | 7116 | const char *sfile; |
3b8b57a9 AM |
7117 | unsigned int sline; |
7118 | ||
7119 | /* Use expr_symbol_where to see if this is an expression | |
7120 | symbol. */ | |
7121 | if (expr_symbol_where (fixP->fx_addsy, &sfile, &sline)) | |
7122 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7123 | _("unresolved expression that must be resolved")); | |
7124 | else | |
7125 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7126 | _("unsupported relocation against %s"), | |
7127 | S_GET_NAME (fixP->fx_addsy)); | |
7128 | fixP->fx_done = 1; | |
7129 | return; | |
7130 | } | |
7131 | } | |
7132 | else | |
7133 | { | |
7134 | /* Handle relocs in data. */ | |
7135 | switch (fixP->fx_r_type) | |
7136 | { | |
252b5132 | 7137 | case BFD_RELOC_VTABLE_INHERIT: |
94f592af NC |
7138 | if (fixP->fx_addsy |
7139 | && !S_IS_DEFINED (fixP->fx_addsy) | |
7140 | && !S_IS_WEAK (fixP->fx_addsy)) | |
7141 | S_SET_WEAK (fixP->fx_addsy); | |
2b0f3761 | 7142 | /* Fallthru */ |
252b5132 RH |
7143 | |
7144 | case BFD_RELOC_VTABLE_ENTRY: | |
94f592af | 7145 | fixP->fx_done = 0; |
252b5132 RH |
7146 | break; |
7147 | ||
0baf16f2 | 7148 | #ifdef OBJ_ELF |
3b8b57a9 AM |
7149 | /* These can appear with @l etc. in data. */ |
7150 | case BFD_RELOC_LO16: | |
3b8b57a9 | 7151 | case BFD_RELOC_LO16_PCREL: |
3b8b57a9 | 7152 | case BFD_RELOC_HI16: |
3b8b57a9 | 7153 | case BFD_RELOC_HI16_PCREL: |
3b8b57a9 | 7154 | case BFD_RELOC_HI16_S: |
3b8b57a9 | 7155 | case BFD_RELOC_HI16_S_PCREL: |
3b8b57a9 | 7156 | case BFD_RELOC_PPC64_HIGHER: |
3b8b57a9 | 7157 | case BFD_RELOC_PPC64_HIGHER_S: |
3b8b57a9 | 7158 | case BFD_RELOC_PPC64_HIGHEST: |
3b8b57a9 | 7159 | case BFD_RELOC_PPC64_HIGHEST_S: |
f9c6b907 AM |
7160 | case BFD_RELOC_PPC64_ADDR16_HIGH: |
7161 | case BFD_RELOC_PPC64_ADDR16_HIGHA: | |
45965137 | 7162 | case BFD_RELOC_PPC64_ADDR64_LOCAL: |
3b8b57a9 AM |
7163 | break; |
7164 | ||
7165 | case BFD_RELOC_PPC_DTPMOD: | |
7166 | case BFD_RELOC_PPC_TPREL: | |
7167 | case BFD_RELOC_PPC_DTPREL: | |
7168 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7169 | break; | |
7170 | ||
7171 | /* Just punt all of these to the linker. */ | |
7172 | case BFD_RELOC_PPC_B16_BRTAKEN: | |
7173 | case BFD_RELOC_PPC_B16_BRNTAKEN: | |
7174 | case BFD_RELOC_16_GOTOFF: | |
7175 | case BFD_RELOC_LO16_GOTOFF: | |
7176 | case BFD_RELOC_HI16_GOTOFF: | |
7177 | case BFD_RELOC_HI16_S_GOTOFF: | |
7178 | case BFD_RELOC_LO16_PLTOFF: | |
7179 | case BFD_RELOC_HI16_PLTOFF: | |
7180 | case BFD_RELOC_HI16_S_PLTOFF: | |
7181 | case BFD_RELOC_PPC_COPY: | |
7182 | case BFD_RELOC_PPC_GLOB_DAT: | |
7183 | case BFD_RELOC_16_BASEREL: | |
7184 | case BFD_RELOC_LO16_BASEREL: | |
7185 | case BFD_RELOC_HI16_BASEREL: | |
7186 | case BFD_RELOC_HI16_S_BASEREL: | |
7187 | case BFD_RELOC_PPC_TLS: | |
7188 | case BFD_RELOC_PPC_DTPREL16_LO: | |
7189 | case BFD_RELOC_PPC_DTPREL16_HI: | |
7190 | case BFD_RELOC_PPC_DTPREL16_HA: | |
7191 | case BFD_RELOC_PPC_TPREL16_LO: | |
7192 | case BFD_RELOC_PPC_TPREL16_HI: | |
7193 | case BFD_RELOC_PPC_TPREL16_HA: | |
7194 | case BFD_RELOC_PPC_GOT_TLSGD16: | |
7195 | case BFD_RELOC_PPC_GOT_TLSGD16_LO: | |
7196 | case BFD_RELOC_PPC_GOT_TLSGD16_HI: | |
7197 | case BFD_RELOC_PPC_GOT_TLSGD16_HA: | |
7198 | case BFD_RELOC_PPC_GOT_TLSLD16: | |
7199 | case BFD_RELOC_PPC_GOT_TLSLD16_LO: | |
7200 | case BFD_RELOC_PPC_GOT_TLSLD16_HI: | |
7201 | case BFD_RELOC_PPC_GOT_TLSLD16_HA: | |
7202 | case BFD_RELOC_PPC_GOT_DTPREL16: | |
7203 | case BFD_RELOC_PPC_GOT_DTPREL16_LO: | |
7204 | case BFD_RELOC_PPC_GOT_DTPREL16_HI: | |
7205 | case BFD_RELOC_PPC_GOT_DTPREL16_HA: | |
7206 | case BFD_RELOC_PPC_GOT_TPREL16: | |
7207 | case BFD_RELOC_PPC_GOT_TPREL16_LO: | |
7208 | case BFD_RELOC_PPC_GOT_TPREL16_HI: | |
7209 | case BFD_RELOC_PPC_GOT_TPREL16_HA: | |
7210 | case BFD_RELOC_24_PLT_PCREL: | |
7211 | case BFD_RELOC_PPC_LOCAL24PC: | |
7212 | case BFD_RELOC_32_PLT_PCREL: | |
7213 | case BFD_RELOC_GPREL16: | |
7214 | case BFD_RELOC_PPC_VLE_SDAREL_LO16A: | |
7215 | case BFD_RELOC_PPC_VLE_SDAREL_HI16A: | |
7216 | case BFD_RELOC_PPC_VLE_SDAREL_HA16A: | |
7217 | case BFD_RELOC_PPC_EMB_NADDR32: | |
7218 | case BFD_RELOC_PPC_EMB_NADDR16: | |
7219 | case BFD_RELOC_PPC_EMB_NADDR16_LO: | |
7220 | case BFD_RELOC_PPC_EMB_NADDR16_HI: | |
7221 | case BFD_RELOC_PPC_EMB_NADDR16_HA: | |
7222 | case BFD_RELOC_PPC_EMB_SDAI16: | |
7223 | case BFD_RELOC_PPC_EMB_SDA2REL: | |
7224 | case BFD_RELOC_PPC_EMB_SDA2I16: | |
7225 | case BFD_RELOC_PPC_EMB_SDA21: | |
7226 | case BFD_RELOC_PPC_VLE_SDA21_LO: | |
7227 | case BFD_RELOC_PPC_EMB_MRKREF: | |
7228 | case BFD_RELOC_PPC_EMB_RELSEC16: | |
7229 | case BFD_RELOC_PPC_EMB_RELST_LO: | |
7230 | case BFD_RELOC_PPC_EMB_RELST_HI: | |
7231 | case BFD_RELOC_PPC_EMB_RELST_HA: | |
7232 | case BFD_RELOC_PPC_EMB_BIT_FLD: | |
7233 | case BFD_RELOC_PPC_EMB_RELSDA: | |
0baf16f2 | 7234 | case BFD_RELOC_PPC64_TOC: |
3b8b57a9 | 7235 | case BFD_RELOC_PPC_TOC16: |
4a403be0 CC |
7236 | case BFD_RELOC_PPC_TOC16_LO: |
7237 | case BFD_RELOC_PPC_TOC16_HI: | |
3b8b57a9 AM |
7238 | case BFD_RELOC_PPC64_TOC16_LO: |
7239 | case BFD_RELOC_PPC64_TOC16_HI: | |
7240 | case BFD_RELOC_PPC64_TOC16_HA: | |
f9c6b907 AM |
7241 | case BFD_RELOC_PPC64_DTPREL16_HIGH: |
7242 | case BFD_RELOC_PPC64_DTPREL16_HIGHA: | |
3b8b57a9 AM |
7243 | case BFD_RELOC_PPC64_DTPREL16_HIGHER: |
7244 | case BFD_RELOC_PPC64_DTPREL16_HIGHERA: | |
7245 | case BFD_RELOC_PPC64_DTPREL16_HIGHEST: | |
7246 | case BFD_RELOC_PPC64_DTPREL16_HIGHESTA: | |
f9c6b907 AM |
7247 | case BFD_RELOC_PPC64_TPREL16_HIGH: |
7248 | case BFD_RELOC_PPC64_TPREL16_HIGHA: | |
3b8b57a9 AM |
7249 | case BFD_RELOC_PPC64_TPREL16_HIGHER: |
7250 | case BFD_RELOC_PPC64_TPREL16_HIGHERA: | |
7251 | case BFD_RELOC_PPC64_TPREL16_HIGHEST: | |
7252 | case BFD_RELOC_PPC64_TPREL16_HIGHESTA: | |
c213164a | 7253 | case BFD_RELOC_PPC64_TLS_PCREL: |
94f592af | 7254 | fixP->fx_done = 0; |
0baf16f2 | 7255 | break; |
0baf16f2 | 7256 | #endif |
3b8b57a9 AM |
7257 | |
7258 | #ifdef OBJ_XCOFF | |
1b2cb8e2 CC |
7259 | case BFD_RELOC_PPC_TLSGD: |
7260 | case BFD_RELOC_PPC_TLSLD: | |
7261 | case BFD_RELOC_PPC_TLSLE: | |
7262 | case BFD_RELOC_PPC_TLSIE: | |
7263 | case BFD_RELOC_PPC_TLSM: | |
7264 | case BFD_RELOC_PPC64_TLSGD: | |
7265 | case BFD_RELOC_PPC64_TLSLD: | |
7266 | case BFD_RELOC_PPC64_TLSLE: | |
7267 | case BFD_RELOC_PPC64_TLSIE: | |
7268 | case BFD_RELOC_PPC64_TLSM: | |
7269 | gas_assert (fixP->fx_addsy != NULL); | |
7270 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
7271 | fieldval = 0; | |
7272 | break; | |
7273 | ||
7274 | /* TLSML relocations are targeting a XMC_TC symbol named | |
7275 | "_$TLSML". We can't check earlier because the relocation | |
7276 | can target any symbol name which will be latter .rename | |
7277 | to "_$TLSML". */ | |
7278 | case BFD_RELOC_PPC_TLSML: | |
7279 | case BFD_RELOC_PPC64_TLSML: | |
7280 | gas_assert (fixP->fx_addsy != NULL); | |
7281 | if (strcmp (symbol_get_tc (fixP->fx_addsy)->real_name, "_$TLSML") != 0) | |
7282 | { | |
7283 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
7284 | _("R_TLSML relocation doesn't target a " | |
7285 | "symbol named \"_$TLSML\". %s"), S_GET_NAME(fixP->fx_addsy)); | |
7286 | } | |
7287 | fieldval = 0; | |
7288 | break; | |
7289 | ||
3b8b57a9 | 7290 | case BFD_RELOC_NONE: |
3b8b57a9 | 7291 | #endif |
5656a981 AM |
7292 | case BFD_RELOC_CTOR: |
7293 | case BFD_RELOC_32: | |
7294 | case BFD_RELOC_32_PCREL: | |
7295 | case BFD_RELOC_RVA: | |
7296 | case BFD_RELOC_64: | |
7297 | case BFD_RELOC_64_PCREL: | |
7298 | case BFD_RELOC_16: | |
7299 | case BFD_RELOC_16_PCREL: | |
7300 | case BFD_RELOC_8: | |
7301 | break; | |
3b8b57a9 | 7302 | |
252b5132 | 7303 | default: |
bc805888 | 7304 | fprintf (stderr, |
94f592af | 7305 | _("Gas failure, reloc value %d\n"), fixP->fx_r_type); |
99a814a1 | 7306 | fflush (stderr); |
252b5132 RH |
7307 | abort (); |
7308 | } | |
46b596ff | 7309 | |
5656a981 | 7310 | if (fixP->fx_size && APPLY_RELOC) |
46b596ff | 7311 | md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, |
5656a981 | 7312 | fieldval, fixP->fx_size); |
bf7279d5 AM |
7313 | if (warn_476 |
7314 | && (seg->flags & SEC_CODE) != 0 | |
7315 | && fixP->fx_size == 4 | |
7316 | && fixP->fx_done | |
7317 | && !fixP->fx_tcbit | |
7318 | && (fixP->fx_r_type == BFD_RELOC_32 | |
7319 | || fixP->fx_r_type == BFD_RELOC_CTOR | |
7320 | || fixP->fx_r_type == BFD_RELOC_32_PCREL)) | |
7321 | as_warn_where (fixP->fx_file, fixP->fx_line, | |
7322 | _("data in executable section")); | |
5656a981 AM |
7323 | } |
7324 | ||
252b5132 | 7325 | #ifdef OBJ_ELF |
3b8b57a9 | 7326 | ppc_elf_validate_fix (fixP, seg); |
94f592af | 7327 | fixP->fx_addnumber = value; |
4e6935a6 AM |
7328 | |
7329 | /* PowerPC uses RELA relocs, ie. the reloc addend is stored separately | |
7330 | from the section contents. If we are going to be emitting a reloc | |
7331 | then the section contents are immaterial, so don't warn if they | |
7332 | happen to overflow. Leave such warnings to ld. */ | |
7333 | if (!fixP->fx_done) | |
a38a07e0 AM |
7334 | { |
7335 | fixP->fx_no_overflow = 1; | |
7336 | ||
7337 | /* Arrange to emit .TOC. as a normal symbol if used in anything | |
7338 | but .TOC.@tocbase. */ | |
7339 | if (ppc_obj64 | |
7340 | && fixP->fx_r_type != BFD_RELOC_PPC64_TOC | |
7341 | && fixP->fx_addsy != NULL | |
7342 | && strcmp (S_GET_NAME (fixP->fx_addsy), ".TOC.") == 0) | |
7343 | symbol_get_bfdsym (fixP->fx_addsy)->flags |= BSF_KEEP; | |
7344 | } | |
252b5132 | 7345 | #else |
4a403be0 CC |
7346 | if (fixP->fx_r_type != BFD_RELOC_PPC_TOC16 |
7347 | && fixP->fx_r_type != BFD_RELOC_PPC_TOC16_HI | |
7348 | && fixP->fx_r_type != BFD_RELOC_PPC_TOC16_LO) | |
94f592af | 7349 | fixP->fx_addnumber = 0; |
252b5132 RH |
7350 | else |
7351 | { | |
8edcbfcd TG |
7352 | /* We want to use the offset within the toc, not the actual VMA |
7353 | of the symbol. */ | |
fd361982 AM |
7354 | fixP->fx_addnumber = (- bfd_section_vma (S_GET_SEGMENT (fixP->fx_addsy)) |
7355 | - S_GET_VALUE (ppc_toc_csect)); | |
4a403be0 CC |
7356 | |
7357 | /* The high bits must be adjusted for the low bits being signed. */ | |
7358 | if (fixP->fx_r_type == BFD_RELOC_PPC_TOC16_HI) { | |
7359 | fixP->fx_addnumber += 0x8000; | |
7360 | } | |
7361 | ||
ac21e7da TG |
7362 | /* Set *valP to avoid errors. */ |
7363 | *valP = value; | |
252b5132 RH |
7364 | } |
7365 | #endif | |
252b5132 RH |
7366 | } |
7367 | ||
7368 | /* Generate a reloc for a fixup. */ | |
7369 | ||
7370 | arelent * | |
98027b10 | 7371 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 RH |
7372 | { |
7373 | arelent *reloc; | |
7374 | ||
325801bd | 7375 | reloc = XNEW (arelent); |
252b5132 | 7376 | |
325801bd | 7377 | reloc->sym_ptr_ptr = XNEW (asymbol *); |
49309057 | 7378 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
252b5132 | 7379 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; |
c213164a AM |
7380 | /* BFD_RELOC_PPC64_TLS_PCREL generates R_PPC64_TLS with an odd r_offset. */ |
7381 | if (fixp->fx_r_type == BFD_RELOC_PPC64_TLS_PCREL) | |
7382 | reloc->address++; | |
252b5132 RH |
7383 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
7384 | if (reloc->howto == (reloc_howto_type *) NULL) | |
7385 | { | |
7386 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
99a814a1 AM |
7387 | _("reloc %d not supported by object file format"), |
7388 | (int) fixp->fx_r_type); | |
252b5132 RH |
7389 | return NULL; |
7390 | } | |
7391 | reloc->addend = fixp->fx_addnumber; | |
7392 | ||
7393 | return reloc; | |
7394 | } | |
75e21f08 JJ |
7395 | |
7396 | void | |
98027b10 | 7397 | ppc_cfi_frame_initial_instructions (void) |
75e21f08 JJ |
7398 | { |
7399 | cfi_add_CFA_def_cfa (1, 0); | |
7400 | } | |
7401 | ||
7402 | int | |
1df69f4f | 7403 | tc_ppc_regname_to_dw2regnum (char *regname) |
75e21f08 JJ |
7404 | { |
7405 | unsigned int regnum = -1; | |
7406 | unsigned int i; | |
7407 | const char *p; | |
7408 | char *q; | |
e0471c16 | 7409 | static struct { const char *name; int dw2regnum; } regnames[] = |
75e21f08 JJ |
7410 | { |
7411 | { "sp", 1 }, { "r.sp", 1 }, { "rtoc", 2 }, { "r.toc", 2 }, | |
7412 | { "mq", 64 }, { "lr", 65 }, { "ctr", 66 }, { "ap", 67 }, | |
80f846b6 | 7413 | { "cr", 70 }, { "xer", 76 }, { "vrsave", 109 }, { "vscr", 110 }, |
75e21f08 JJ |
7414 | { "spe_acc", 111 }, { "spefscr", 112 } |
7415 | }; | |
7416 | ||
7417 | for (i = 0; i < ARRAY_SIZE (regnames); ++i) | |
7418 | if (strcmp (regnames[i].name, regname) == 0) | |
7419 | return regnames[i].dw2regnum; | |
7420 | ||
7421 | if (regname[0] == 'r' || regname[0] == 'f' || regname[0] == 'v') | |
7422 | { | |
7423 | p = regname + 1 + (regname[1] == '.'); | |
7424 | regnum = strtoul (p, &q, 10); | |
7425 | if (p == q || *q || regnum >= 32) | |
7426 | return -1; | |
7427 | if (regname[0] == 'f') | |
b7d7dc63 | 7428 | regnum += 32; |
75e21f08 | 7429 | else if (regname[0] == 'v') |
b7d7dc63 | 7430 | regnum += 77; |
75e21f08 JJ |
7431 | } |
7432 | else if (regname[0] == 'c' && regname[1] == 'r') | |
7433 | { | |
7434 | p = regname + 2 + (regname[2] == '.'); | |
7435 | if (p[0] < '0' || p[0] > '7' || p[1]) | |
b7d7dc63 | 7436 | return -1; |
75e21f08 JJ |
7437 | regnum = p[0] - '0' + 68; |
7438 | } | |
7439 | return regnum; | |
7440 | } |