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e23eba97 | 1 | /* tc-riscv.c -- RISC-V assembler |
d87bef3a | 2 | Copyright (C) 2011-2023 Free Software Foundation, Inc. |
e23eba97 NC |
3 | |
4 | Contributed by Andrew Waterman (andrew@sifive.com). | |
5 | Based on MIPS target. | |
6 | ||
7 | This file is part of GAS. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; see the file COPYING3. If not, | |
21 | see <http://www.gnu.org/licenses/>. */ | |
22 | ||
23 | #include "as.h" | |
24 | #include "config.h" | |
25 | #include "subsegs.h" | |
26 | #include "safe-ctype.h" | |
27 | ||
28 | #include "itbl-ops.h" | |
29 | #include "dwarf2dbg.h" | |
30 | #include "dw2gencfi.h" | |
31 | ||
1080bf78 | 32 | #include "bfd/elfxx-riscv.h" |
e23eba97 NC |
33 | #include "elf/riscv.h" |
34 | #include "opcode/riscv.h" | |
35 | ||
36 | #include <stdint.h> | |
37 | ||
38 | /* Information about an instruction, including its format, operands | |
39 | and fixups. */ | |
40 | struct riscv_cl_insn | |
41 | { | |
42 | /* The opcode's entry in riscv_opcodes. */ | |
43 | const struct riscv_opcode *insn_mo; | |
44 | ||
634001bb TO |
45 | /* The encoded instruction bits |
46 | (first bits enough to extract instruction length on a long opcode). */ | |
e23eba97 NC |
47 | insn_t insn_opcode; |
48 | ||
634001bb TO |
49 | /* The long encoded instruction bits ([0] is non-zero on a long opcode). */ |
50 | char insn_long_opcode[RISCV_MAX_INSN_LEN]; | |
51 | ||
e23eba97 NC |
52 | /* The frag that contains the instruction. */ |
53 | struct frag *frag; | |
54 | ||
55 | /* The offset into FRAG of the first instruction byte. */ | |
56 | long where; | |
57 | ||
58 | /* The relocs associated with the instruction, if any. */ | |
59 | fixS *fixp; | |
60 | }; | |
61 | ||
3d73d29e NC |
62 | /* All RISC-V CSR belong to one of these classes. */ |
63 | enum riscv_csr_class | |
64 | { | |
65 | CSR_CLASS_NONE, | |
66 | ||
67 | CSR_CLASS_I, | |
65e4a99a NC |
68 | CSR_CLASS_I_32, /* rv32 only */ |
69 | CSR_CLASS_F, /* f-ext only */ | |
70 | CSR_CLASS_ZKR, /* zkr only */ | |
71 | CSR_CLASS_V, /* rvv only */ | |
c625f4ed NC |
72 | CSR_CLASS_DEBUG, /* debug CSR */ |
73 | CSR_CLASS_H, /* hypervisor */ | |
74 | CSR_CLASS_H_32, /* hypervisor, rv32 only */ | |
ac8df5a1 CM |
75 | CSR_CLASS_SMAIA, /* Smaia */ |
76 | CSR_CLASS_SMAIA_32, /* Smaia, rv32 only */ | |
6af47b08 | 77 | CSR_CLASS_SMSTATEEN, /* Smstateen only */ |
6af47b08 | 78 | CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */ |
ac8df5a1 CM |
79 | CSR_CLASS_SSAIA, /* Ssaia */ |
80 | CSR_CLASS_SSAIA_AND_H, /* Ssaia with H */ | |
81 | CSR_CLASS_SSAIA_32, /* Ssaia, rv32 only */ | |
82 | CSR_CLASS_SSAIA_AND_H_32, /* Ssaia with H, rv32 only */ | |
15253318 TO |
83 | CSR_CLASS_SSSTATEEN, /* S[ms]stateen only */ |
84 | CSR_CLASS_SSSTATEEN_AND_H, /* S[ms]stateen only (with H) */ | |
85 | CSR_CLASS_SSSTATEEN_AND_H_32, /* S[ms]stateen RV32 only (with H) */ | |
713f3708 TO |
86 | CSR_CLASS_SSCOFPMF, /* Sscofpmf only */ |
87 | CSR_CLASS_SSCOFPMF_32, /* Sscofpmf RV32 only */ | |
766077c1 TO |
88 | CSR_CLASS_SSTC, /* Sstc only */ |
89 | CSR_CLASS_SSTC_AND_H, /* Sstc only (with H) */ | |
90 | CSR_CLASS_SSTC_32, /* Sstc RV32 only */ | |
91 | CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */ | |
3d73d29e NC |
92 | }; |
93 | ||
94 | /* This structure holds all restricted conditions for a CSR. */ | |
95 | struct riscv_csr_extra | |
96 | { | |
97 | /* Class to which this CSR belongs. Used to decide whether or | |
98 | not this CSR is legal in the current -march context. */ | |
99 | enum riscv_csr_class csr_class; | |
100 | ||
101 | /* CSR may have differnet numbers in the previous priv spec. */ | |
102 | unsigned address; | |
103 | ||
104 | /* Record the CSR is defined/valid in which versions. */ | |
105 | enum riscv_spec_class define_version; | |
106 | ||
107 | /* Record the CSR is aborted/invalid from which versions. If it isn't | |
a63375ac | 108 | aborted in the current version, then it should be PRIV_SPEC_CLASS_DRAFT. */ |
3d73d29e NC |
109 | enum riscv_spec_class abort_version; |
110 | ||
111 | /* The CSR may have more than one setting. */ | |
112 | struct riscv_csr_extra *next; | |
113 | }; | |
114 | ||
e4028336 PN |
115 | /* This structure contains information about errors that occur within the |
116 | riscv_ip function */ | |
117 | struct riscv_ip_error | |
118 | { | |
119 | /* General error message */ | |
120 | const char* msg; | |
121 | ||
122 | /* Statement that caused the error */ | |
123 | char* statement; | |
124 | ||
125 | /* Missing extension that needs to be enabled */ | |
126 | const char* missing_ext; | |
127 | }; | |
128 | ||
e23eba97 NC |
129 | #ifndef DEFAULT_ARCH |
130 | #define DEFAULT_ARCH "riscv64" | |
131 | #endif | |
132 | ||
2dc8dd17 JW |
133 | #ifndef DEFAULT_RISCV_ATTR |
134 | #define DEFAULT_RISCV_ATTR 0 | |
135 | #endif | |
136 | ||
8f595e9b | 137 | /* Let riscv_after_parse_args set the default value according to xlen. */ |
8f595e9b NC |
138 | #ifndef DEFAULT_RISCV_ARCH_WITH_EXT |
139 | #define DEFAULT_RISCV_ARCH_WITH_EXT NULL | |
140 | #endif | |
141 | ||
dcd709e0 | 142 | /* Need to sync the version with RISC-V compiler. */ |
8f595e9b | 143 | #ifndef DEFAULT_RISCV_ISA_SPEC |
aed44286 | 144 | #define DEFAULT_RISCV_ISA_SPEC "20191213" |
8f595e9b NC |
145 | #endif |
146 | ||
147 | #ifndef DEFAULT_RISCV_PRIV_SPEC | |
148 | #define DEFAULT_RISCV_PRIV_SPEC "1.11" | |
149 | #endif | |
150 | ||
e23eba97 | 151 | static const char default_arch[] = DEFAULT_ARCH; |
8f595e9b | 152 | static const char *default_arch_with_ext = DEFAULT_RISCV_ARCH_WITH_EXT; |
3d73d29e NC |
153 | static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_NONE; |
154 | static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; | |
e23eba97 | 155 | |
dcd709e0 NC |
156 | static unsigned xlen = 0; /* The width of an x-register. */ |
157 | static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */ | |
5b7c81bd | 158 | static bool rve_abi = false; |
1942a048 NC |
159 | enum float_abi |
160 | { | |
6e1605e4 NC |
161 | FLOAT_ABI_DEFAULT = -1, |
162 | FLOAT_ABI_SOFT, | |
163 | FLOAT_ABI_SINGLE, | |
164 | FLOAT_ABI_DOUBLE, | |
165 | FLOAT_ABI_QUAD | |
166 | }; | |
167 | static enum float_abi float_abi = FLOAT_ABI_DEFAULT; | |
e23eba97 | 168 | |
2922d21d | 169 | #define LOAD_ADDRESS_INSN (abi_xlen == 64 ? "ld" : "lw") |
e23eba97 NC |
170 | #define ADD32_INSN (xlen == 64 ? "addiw" : "addi") |
171 | ||
172 | static unsigned elf_flags = 0; | |
173 | ||
dcd709e0 NC |
174 | /* Set the default_isa_spec. Return 0 if the spec isn't supported. |
175 | Otherwise, return 1. */ | |
8f595e9b NC |
176 | |
177 | static int | |
178 | riscv_set_default_isa_spec (const char *s) | |
179 | { | |
3d73d29e NC |
180 | enum riscv_spec_class class = ISA_SPEC_CLASS_NONE; |
181 | RISCV_GET_ISA_SPEC_CLASS (s, class); | |
182 | if (class == ISA_SPEC_CLASS_NONE) | |
8f595e9b | 183 | { |
b800637e NC |
184 | as_bad ("unknown default ISA spec `%s' set by " |
185 | "-misa-spec or --with-isa-spec", s); | |
8f595e9b NC |
186 | return 0; |
187 | } | |
188 | else | |
189 | default_isa_spec = class; | |
190 | return 1; | |
191 | } | |
192 | ||
dcd709e0 NC |
193 | /* Set the default_priv_spec. Find the privileged elf attributes when |
194 | the input string is NULL. Return 0 if the spec isn't supported. | |
195 | Otherwise, return 1. */ | |
8f595e9b NC |
196 | |
197 | static int | |
198 | riscv_set_default_priv_spec (const char *s) | |
199 | { | |
3d73d29e | 200 | enum riscv_spec_class class = PRIV_SPEC_CLASS_NONE; |
8f595e9b NC |
201 | unsigned major, minor, revision; |
202 | obj_attribute *attr; | |
8f595e9b | 203 | |
3d73d29e NC |
204 | RISCV_GET_PRIV_SPEC_CLASS (s, class); |
205 | if (class != PRIV_SPEC_CLASS_NONE) | |
8f595e9b NC |
206 | { |
207 | default_priv_spec = class; | |
208 | return 1; | |
209 | } | |
210 | ||
211 | if (s != NULL) | |
212 | { | |
b800637e NC |
213 | as_bad (_("unknown default privileged spec `%s' set by " |
214 | "-mpriv-spec or --with-priv-spec"), s); | |
8f595e9b NC |
215 | return 0; |
216 | } | |
217 | ||
dcd709e0 | 218 | /* Set the default_priv_spec by the privileged elf attributes. */ |
8f595e9b NC |
219 | attr = elf_known_obj_attributes_proc (stdoutput); |
220 | major = (unsigned) attr[Tag_RISCV_priv_spec].i; | |
221 | minor = (unsigned) attr[Tag_RISCV_priv_spec_minor].i; | |
222 | revision = (unsigned) attr[Tag_RISCV_priv_spec_revision].i; | |
3d73d29e NC |
223 | /* Version 0.0.0 is the default value and meningless. */ |
224 | if (major == 0 && minor == 0 && revision == 0) | |
225 | return 1; | |
8f595e9b | 226 | |
3d73d29e NC |
227 | riscv_get_priv_spec_class_from_numbers (major, minor, revision, &class); |
228 | if (class != PRIV_SPEC_CLASS_NONE) | |
229 | { | |
8f595e9b | 230 | default_priv_spec = class; |
8f595e9b NC |
231 | return 1; |
232 | } | |
233 | ||
dcd709e0 | 234 | /* Still can not find the privileged spec class. */ |
b800637e NC |
235 | as_bad (_("unknown default privileged spec `%d.%d.%d' set by " |
236 | "privileged elf attributes"), major, minor, revision); | |
8f595e9b NC |
237 | return 0; |
238 | } | |
239 | ||
e23eba97 | 240 | /* This is the set of options which the .option pseudo-op may modify. */ |
e23eba97 NC |
241 | struct riscv_set_options |
242 | { | |
243 | int pic; /* Generate position-independent code. */ | |
244 | int rvc; /* Generate RVC code. */ | |
45f76423 | 245 | int relax; /* Emit relocs the linker is allowed to relax. */ |
dcd709e0 | 246 | int arch_attr; /* Emit architecture and privileged elf attributes. */ |
2ca89224 | 247 | int csr_check; /* Enable the CSR checking. */ |
e23eba97 NC |
248 | }; |
249 | ||
250 | static struct riscv_set_options riscv_opts = | |
251 | { | |
dcd709e0 NC |
252 | 0, /* pic */ |
253 | 0, /* rvc */ | |
dcd709e0 | 254 | 1, /* relax */ |
2dc8dd17 | 255 | DEFAULT_RISCV_ATTR, /* arch_attr */ |
dcd709e0 | 256 | 0, /* csr_check */ |
e23eba97 NC |
257 | }; |
258 | ||
437e2ff1 NC |
259 | /* Enable or disable the rvc flags for riscv_opts. Turn on the rvc flag |
260 | for elf_flags once we have enabled c extension. */ | |
261 | ||
e23eba97 | 262 | static void |
5b7c81bd | 263 | riscv_set_rvc (bool rvc_value) |
e23eba97 NC |
264 | { |
265 | if (rvc_value) | |
266 | elf_flags |= EF_RISCV_RVC; | |
267 | ||
268 | riscv_opts.rvc = rvc_value; | |
269 | } | |
270 | ||
96462b01 S |
271 | /* Turn on the tso flag for elf_flags once we have enabled ztso extension. */ |
272 | ||
273 | static void | |
0242db99 | 274 | riscv_set_tso (void) |
96462b01 S |
275 | { |
276 | elf_flags |= EF_RISCV_TSO; | |
277 | } | |
278 | ||
f5cb31a8 JB |
279 | /* The linked list hanging off of .subsets_list records all enabled extensions, |
280 | which are parsed from the architecture string. The architecture string can | |
281 | be set by the -march option, the elf architecture attributes, and the | |
282 | --with-arch configure option. */ | |
f786c359 | 283 | static riscv_parse_subset_t riscv_rps_as = |
43135d3b | 284 | { |
d3ffd7f7 NC |
285 | NULL, /* subset_list, we will set it later once |
286 | riscv_opts_stack is created or updated. */ | |
f786c359 NC |
287 | as_bad, /* error_handler. */ |
288 | &xlen, /* xlen. */ | |
289 | &default_isa_spec, /* isa_spec. */ | |
290 | true, /* check_unknown_prefixed_ext. */ | |
291 | }; | |
43135d3b | 292 | |
40f1a1a4 NC |
293 | /* Update the architecture string in the subset_list. */ |
294 | ||
295 | static void | |
296 | riscv_reset_subsets_list_arch_str (void) | |
297 | { | |
298 | riscv_subset_list_t *subsets = riscv_rps_as.subset_list; | |
299 | if (subsets->arch_str != NULL) | |
300 | free ((void *) subsets->arch_str); | |
301 | subsets->arch_str = riscv_arch_str (xlen, subsets); | |
302 | } | |
303 | ||
d3ffd7f7 NC |
304 | /* This structure is used to hold a stack of .option values. */ |
305 | struct riscv_option_stack | |
306 | { | |
307 | struct riscv_option_stack *next; | |
308 | struct riscv_set_options options; | |
309 | riscv_subset_list_t *subset_list; | |
310 | }; | |
311 | ||
312 | static struct riscv_option_stack *riscv_opts_stack = NULL; | |
313 | ||
2922d21d | 314 | /* Set which ISA and extensions are available. */ |
e23eba97 | 315 | |
e23eba97 | 316 | static void |
2922d21d | 317 | riscv_set_arch (const char *s) |
e23eba97 | 318 | { |
c9f27991 NC |
319 | if (s != NULL && strcmp (s, "") == 0) |
320 | { | |
321 | as_bad (_("the architecture string of -march and elf architecture " | |
322 | "attributes cannot be empty")); | |
323 | return; | |
324 | } | |
7f999549 | 325 | |
f5cb31a8 | 326 | if (riscv_rps_as.subset_list == NULL) |
d3ffd7f7 | 327 | { |
f5cb31a8 JB |
328 | riscv_rps_as.subset_list = XNEW (riscv_subset_list_t); |
329 | riscv_rps_as.subset_list->head = NULL; | |
330 | riscv_rps_as.subset_list->tail = NULL; | |
40f1a1a4 | 331 | riscv_rps_as.subset_list->arch_str = NULL; |
d3ffd7f7 | 332 | } |
f5cb31a8 | 333 | riscv_release_subset_list (riscv_rps_as.subset_list); |
f786c359 | 334 | riscv_parse_subset (&riscv_rps_as, s); |
40f1a1a4 | 335 | riscv_reset_subsets_list_arch_str (); |
28b2963f | 336 | |
28b2963f | 337 | riscv_set_rvc (false); |
f786c359 | 338 | if (riscv_subset_supports (&riscv_rps_as, "c")) |
28b2963f | 339 | riscv_set_rvc (true); |
96462b01 S |
340 | |
341 | if (riscv_subset_supports (&riscv_rps_as, "ztso")) | |
342 | riscv_set_tso (); | |
e23eba97 NC |
343 | } |
344 | ||
dcd709e0 | 345 | /* Indicate -mabi option is explictly set. */ |
5b7c81bd | 346 | static bool explicit_mabi = false; |
6e1605e4 | 347 | |
437e2ff1 NC |
348 | /* Set the abi information. */ |
349 | ||
6e1605e4 | 350 | static void |
5b7c81bd | 351 | riscv_set_abi (unsigned new_xlen, enum float_abi new_float_abi, bool rve) |
6e1605e4 NC |
352 | { |
353 | abi_xlen = new_xlen; | |
354 | float_abi = new_float_abi; | |
355 | rve_abi = rve; | |
356 | } | |
357 | ||
dcd709e0 NC |
358 | /* If the -mabi option isn't set, then set the abi according to the |
359 | ISA string. Otherwise, check if there is any conflict. */ | |
6e1605e4 NC |
360 | |
361 | static void | |
362 | riscv_set_abi_by_arch (void) | |
363 | { | |
364 | if (!explicit_mabi) | |
365 | { | |
f786c359 | 366 | if (riscv_subset_supports (&riscv_rps_as, "q")) |
5b7c81bd | 367 | riscv_set_abi (xlen, FLOAT_ABI_QUAD, false); |
f786c359 | 368 | else if (riscv_subset_supports (&riscv_rps_as, "d")) |
5b7c81bd | 369 | riscv_set_abi (xlen, FLOAT_ABI_DOUBLE, false); |
f786c359 | 370 | else if (riscv_subset_supports (&riscv_rps_as, "e")) |
5d0ed830 | 371 | riscv_set_abi (xlen, FLOAT_ABI_SOFT, true); |
6e1605e4 | 372 | else |
5b7c81bd | 373 | riscv_set_abi (xlen, FLOAT_ABI_SOFT, false); |
6e1605e4 NC |
374 | } |
375 | else | |
376 | { | |
377 | gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT); | |
378 | if (abi_xlen > xlen) | |
379 | as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); | |
380 | else if (abi_xlen < xlen) | |
381 | as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); | |
5d0ed830 | 382 | |
f786c359 | 383 | if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) |
5d0ed830 NC |
384 | as_bad ("only the ilp32e ABI is supported for e extension"); |
385 | ||
386 | if (float_abi == FLOAT_ABI_SINGLE | |
f786c359 | 387 | && !riscv_subset_supports (&riscv_rps_as, "f")) |
5d0ed830 NC |
388 | as_bad ("ilp32f/lp64f ABI can't be used when f extension " |
389 | "isn't supported"); | |
390 | else if (float_abi == FLOAT_ABI_DOUBLE | |
f786c359 | 391 | && !riscv_subset_supports (&riscv_rps_as, "d")) |
5d0ed830 NC |
392 | as_bad ("ilp32d/lp64d ABI can't be used when d extension " |
393 | "isn't supported"); | |
394 | else if (float_abi == FLOAT_ABI_QUAD | |
f786c359 | 395 | && !riscv_subset_supports (&riscv_rps_as, "q")) |
5d0ed830 NC |
396 | as_bad ("ilp32q/lp64q ABI can't be used when q extension " |
397 | "isn't supported"); | |
6e1605e4 NC |
398 | } |
399 | ||
400 | /* Update the EF_RISCV_FLOAT_ABI field of elf_flags. */ | |
401 | elf_flags &= ~EF_RISCV_FLOAT_ABI; | |
402 | elf_flags |= float_abi << 1; | |
403 | ||
404 | if (rve_abi) | |
405 | elf_flags |= EF_RISCV_RVE; | |
406 | } | |
407 | ||
e23eba97 | 408 | /* Handle of the OPCODE hash table. */ |
629310ab | 409 | static htab_t op_hash = NULL; |
e23eba97 | 410 | |
0e35537d | 411 | /* Handle of the type of .insn hash table. */ |
629310ab | 412 | static htab_t insn_type_hash = NULL; |
0e35537d | 413 | |
e23eba97 | 414 | /* This array holds the chars that always start a comment. If the |
dcd709e0 | 415 | pre-processor is disabled, these aren't very useful. */ |
e23eba97 NC |
416 | const char comment_chars[] = "#"; |
417 | ||
418 | /* This array holds the chars that only start a comment at the beginning of | |
419 | a line. If the line seems to have the form '# 123 filename' | |
dcd709e0 NC |
420 | .line and .file directives will appear in the pre-processed output |
421 | ||
422 | Note that input_file.c hand checks for '#' at the beginning of the | |
e23eba97 | 423 | first line of the input file. This is because the compiler outputs |
dcd709e0 NC |
424 | #NO_APP at the beginning of its output. |
425 | ||
426 | Also note that C style comments are always supported. */ | |
e23eba97 NC |
427 | const char line_comment_chars[] = "#"; |
428 | ||
429 | /* This array holds machine specific line separator characters. */ | |
430 | const char line_separator_chars[] = ";"; | |
431 | ||
dcd709e0 | 432 | /* Chars that can be used to separate mant from exp in floating point nums. */ |
e23eba97 NC |
433 | const char EXP_CHARS[] = "eE"; |
434 | ||
dcd709e0 NC |
435 | /* Chars that mean this number is a floating point constant. |
436 | As in 0f12.456 or 0d1.2345e12. */ | |
035784e3 | 437 | const char FLT_CHARS[] = "rRsSfFdDxXpPhH"; |
e23eba97 | 438 | |
2dc8dd17 | 439 | /* Indicate we are already assemble any instructions or not. */ |
5b7c81bd | 440 | static bool start_assemble = false; |
2dc8dd17 | 441 | |
f9a6a8f0 | 442 | /* Indicate ELF attributes are explicitly set. */ |
5b7c81bd | 443 | static bool explicit_attr = false; |
2dc8dd17 | 444 | |
f9a6a8f0 | 445 | /* Indicate CSR or priv instructions are explicitly used. */ |
5b7c81bd | 446 | static bool explicit_priv_attr = false; |
3fc6c3dc | 447 | |
6eb099ae | 448 | static char *expr_parse_end; |
437e2ff1 | 449 | |
e23eba97 NC |
450 | /* Macros for encoding relaxation state for RVC branches and far jumps. */ |
451 | #define RELAX_BRANCH_ENCODE(uncond, rvc, length) \ | |
452 | ((relax_substateT) \ | |
453 | (0xc0000000 \ | |
454 | | ((uncond) ? 1 : 0) \ | |
455 | | ((rvc) ? 2 : 0) \ | |
456 | | ((length) << 2))) | |
457 | #define RELAX_BRANCH_P(i) (((i) & 0xf0000000) == 0xc0000000) | |
458 | #define RELAX_BRANCH_LENGTH(i) (((i) >> 2) & 0xF) | |
459 | #define RELAX_BRANCH_RVC(i) (((i) & 2) != 0) | |
460 | #define RELAX_BRANCH_UNCOND(i) (((i) & 1) != 0) | |
461 | ||
462 | /* Is the given value a sign-extended 32-bit value? */ | |
463 | #define IS_SEXT_32BIT_NUM(x) \ | |
464 | (((x) &~ (offsetT) 0x7fffffff) == 0 \ | |
465 | || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff)) | |
466 | ||
467 | /* Is the given value a zero-extended 32-bit value? Or a negated one? */ | |
468 | #define IS_ZEXT_32BIT_NUM(x) \ | |
469 | (((x) &~ (offsetT) 0xffffffff) == 0 \ | |
470 | || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff)) | |
471 | ||
472 | /* Change INSN's opcode so that the operand given by FIELD has value VALUE. | |
473 | INSN is a riscv_cl_insn structure and VALUE is evaluated exactly once. */ | |
474 | #define INSERT_OPERAND(FIELD, INSN, VALUE) \ | |
475 | INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD) | |
476 | ||
8b7419c4 CM |
477 | #define INSERT_IMM(n, s, INSN, VALUE) \ |
478 | INSERT_BITS ((INSN).insn_opcode, VALUE, (1ULL<<n) - 1, s) | |
479 | ||
e23eba97 NC |
480 | /* Determine if an instruction matches an opcode. */ |
481 | #define OPCODE_MATCHES(OPCODE, OP) \ | |
482 | (((OPCODE) & MASK_##OP) == MATCH_##OP) | |
483 | ||
9b9b1092 NC |
484 | /* Create a new mapping symbol for the transition to STATE. */ |
485 | ||
486 | static void | |
487 | make_mapping_symbol (enum riscv_seg_mstate state, | |
488 | valueT value, | |
40f1a1a4 | 489 | fragS *frag, |
d918451a NC |
490 | const char *arch_str, |
491 | bool odd_data_padding) | |
9b9b1092 NC |
492 | { |
493 | const char *name; | |
615d4f41 | 494 | char *buff = NULL; |
9b9b1092 NC |
495 | switch (state) |
496 | { | |
497 | case MAP_DATA: | |
498 | name = "$d"; | |
499 | break; | |
500 | case MAP_INSN: | |
d918451a | 501 | if (arch_str != NULL) |
40f1a1a4 | 502 | { |
d918451a | 503 | size_t size = strlen (arch_str) + 3; /* "$x" + '\0' */ |
40f1a1a4 | 504 | buff = xmalloc (size); |
d918451a | 505 | snprintf (buff, size, "$x%s", arch_str); |
40f1a1a4 NC |
506 | name = buff; |
507 | } | |
508 | else | |
509 | name = "$x"; | |
9b9b1092 NC |
510 | break; |
511 | default: | |
512 | abort (); | |
513 | } | |
514 | ||
515 | symbolS *symbol = symbol_new (name, now_seg, frag, value); | |
516 | symbol_get_bfdsym (symbol)->flags |= (BSF_NO_FLAGS | BSF_LOCAL); | |
d918451a | 517 | if (arch_str != NULL) |
40f1a1a4 NC |
518 | { |
519 | /* Store current $x+arch into tc_segment_info. */ | |
520 | seg_info (now_seg)->tc_segment_info_data.arch_map_symbol = symbol; | |
521 | xfree ((void *) buff); | |
522 | } | |
9b9b1092 NC |
523 | |
524 | /* If .fill or other data filling directive generates zero sized data, | |
40f1a1a4 NC |
525 | then mapping symbol for the following code will have the same value. |
526 | ||
527 | Please see gas/testsuite/gas/riscv/mapping.s: .text.zero.fill.first | |
528 | and .text.zero.fill.last. */ | |
529 | symbolS *first = frag->tc_frag_data.first_map_symbol; | |
530 | symbolS *last = frag->tc_frag_data.last_map_symbol; | |
d918451a | 531 | symbolS *removed = NULL; |
9b9b1092 NC |
532 | if (value == 0) |
533 | { | |
40f1a1a4 | 534 | if (first != NULL) |
9b9b1092 | 535 | { |
40f1a1a4 NC |
536 | know (S_GET_VALUE (first) == S_GET_VALUE (symbol) |
537 | && first == last); | |
9b9b1092 | 538 | /* Remove the old one. */ |
d918451a | 539 | removed = first; |
9b9b1092 NC |
540 | } |
541 | frag->tc_frag_data.first_map_symbol = symbol; | |
542 | } | |
40f1a1a4 | 543 | else if (last != NULL) |
9b9b1092 NC |
544 | { |
545 | /* The mapping symbols should be added in offset order. */ | |
40f1a1a4 | 546 | know (S_GET_VALUE (last) <= S_GET_VALUE (symbol)); |
9b9b1092 | 547 | /* Remove the old one. */ |
40f1a1a4 | 548 | if (S_GET_VALUE (last) == S_GET_VALUE (symbol)) |
d918451a | 549 | removed = last; |
9b9b1092 NC |
550 | } |
551 | frag->tc_frag_data.last_map_symbol = symbol; | |
d918451a NC |
552 | |
553 | if (removed == NULL) | |
554 | return; | |
555 | ||
556 | if (odd_data_padding) | |
557 | { | |
558 | /* If the removed mapping symbol is $x+arch, then add it back to | |
559 | the next $x. */ | |
560 | const char *str = strncmp (S_GET_NAME (removed), "$xrv", 4) == 0 | |
561 | ? S_GET_NAME (removed) + 2 : NULL; | |
562 | make_mapping_symbol (MAP_INSN, frag->fr_fix + 1, frag, str, | |
563 | false/* odd_data_padding */); | |
564 | } | |
565 | symbol_remove (removed, &symbol_rootP, &symbol_lastP); | |
9b9b1092 NC |
566 | } |
567 | ||
568 | /* Set the mapping state for frag_now. */ | |
569 | ||
570 | void | |
571 | riscv_mapping_state (enum riscv_seg_mstate to_state, | |
40f1a1a4 | 572 | int max_chars, |
3190ebcb | 573 | bool fr_align_code) |
9b9b1092 NC |
574 | { |
575 | enum riscv_seg_mstate from_state = | |
576 | seg_info (now_seg)->tc_segment_info_data.map_state; | |
40f1a1a4 | 577 | bool reset_seg_arch_str = false; |
9b9b1092 NC |
578 | |
579 | if (!SEG_NORMAL (now_seg) | |
40f1a1a4 | 580 | /* For now we only add the mapping symbols to text sections. |
9b9b1092 NC |
581 | Therefore, the dis-assembler only show the actual contents |
582 | distribution for text. Other sections will be shown as | |
583 | data without the details. */ | |
584 | || !subseg_text_p (now_seg)) | |
585 | return; | |
586 | ||
587 | /* The mapping symbol should be emitted if not in the right | |
40f1a1a4 NC |
588 | mapping state. */ |
589 | symbolS *seg_arch_symbol = | |
590 | seg_info (now_seg)->tc_segment_info_data.arch_map_symbol; | |
591 | if (to_state == MAP_INSN && seg_arch_symbol == 0) | |
592 | { | |
593 | /* Always add $x+arch at the first instruction of section. */ | |
594 | reset_seg_arch_str = true; | |
595 | } | |
596 | else if (seg_arch_symbol != 0 | |
597 | && to_state == MAP_INSN | |
3190ebcb | 598 | && !fr_align_code |
40f1a1a4 NC |
599 | && strcmp (riscv_rps_as.subset_list->arch_str, |
600 | S_GET_NAME (seg_arch_symbol) + 2) != 0) | |
601 | { | |
602 | reset_seg_arch_str = true; | |
40f1a1a4 NC |
603 | } |
604 | else if (from_state == to_state) | |
9b9b1092 NC |
605 | return; |
606 | ||
607 | valueT value = (valueT) (frag_now_fix () - max_chars); | |
608 | seg_info (now_seg)->tc_segment_info_data.map_state = to_state; | |
d918451a NC |
609 | const char *arch_str = reset_seg_arch_str |
610 | ? riscv_rps_as.subset_list->arch_str : NULL; | |
611 | make_mapping_symbol (to_state, value, frag_now, arch_str, | |
612 | false/* odd_data_padding */); | |
9b9b1092 NC |
613 | } |
614 | ||
615 | /* Add the odd bytes of paddings for riscv_handle_align. */ | |
616 | ||
617 | static void | |
618 | riscv_add_odd_padding_symbol (fragS *frag) | |
619 | { | |
620 | /* If there was already a mapping symbol, it should be | |
40f1a1a4 NC |
621 | removed in the make_mapping_symbol. |
622 | ||
d918451a NC |
623 | Please see gas/testsuite/gas/riscv/mapping.s: .text.odd.align.*. */ |
624 | make_mapping_symbol (MAP_DATA, frag->fr_fix, frag, | |
625 | NULL/* arch_str */, true/* odd_data_padding */); | |
9b9b1092 NC |
626 | } |
627 | ||
628 | /* Remove any excess mapping symbols generated for alignment frags in | |
629 | SEC. We may have created a mapping symbol before a zero byte | |
630 | alignment; remove it if there's a mapping symbol after the | |
631 | alignment. */ | |
632 | ||
633 | static void | |
634 | riscv_check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, | |
635 | asection *sec, | |
636 | void *dummy ATTRIBUTE_UNUSED) | |
637 | { | |
638 | segment_info_type *seginfo = seg_info (sec); | |
639 | fragS *fragp; | |
640 | ||
641 | if (seginfo == NULL || seginfo->frchainP == NULL) | |
642 | return; | |
643 | ||
644 | for (fragp = seginfo->frchainP->frch_root; | |
645 | fragp != NULL; | |
646 | fragp = fragp->fr_next) | |
647 | { | |
648 | symbolS *last = fragp->tc_frag_data.last_map_symbol; | |
649 | fragS *next = fragp->fr_next; | |
650 | ||
651 | if (last == NULL || next == NULL) | |
652 | continue; | |
653 | ||
654 | /* Check the last mapping symbol if it is at the boundary of | |
655 | fragment. */ | |
656 | if (S_GET_VALUE (last) < next->fr_address) | |
657 | continue; | |
658 | know (S_GET_VALUE (last) == next->fr_address); | |
659 | ||
660 | do | |
661 | { | |
40f1a1a4 NC |
662 | symbolS *next_first = next->tc_frag_data.first_map_symbol; |
663 | if (next_first != NULL) | |
9b9b1092 NC |
664 | { |
665 | /* The last mapping symbol overlaps with another one | |
40f1a1a4 NC |
666 | which at the start of the next frag. |
667 | ||
668 | Please see the gas/testsuite/gas/riscv/mapping.s: | |
669 | .text.zero.fill.align.A and .text.zero.fill.align.B. */ | |
d918451a NC |
670 | know (S_GET_VALUE (last) == S_GET_VALUE (next_first)); |
671 | symbolS *removed = last; | |
672 | if (strncmp (S_GET_NAME (last), "$xrv", 4) == 0 | |
673 | && strcmp (S_GET_NAME (next_first), "$x") == 0) | |
674 | removed = next_first; | |
675 | symbol_remove (removed, &symbol_rootP, &symbol_lastP); | |
9b9b1092 NC |
676 | break; |
677 | } | |
678 | ||
679 | if (next->fr_next == NULL) | |
680 | { | |
40f1a1a4 NC |
681 | /* The last mapping symbol is at the end of the section. |
682 | ||
683 | Please see the gas/testsuite/gas/riscv/mapping.s: | |
684 | .text.last.section. */ | |
9b9b1092 NC |
685 | know (next->fr_fix == 0 && next->fr_var == 0); |
686 | symbol_remove (last, &symbol_rootP, &symbol_lastP); | |
687 | break; | |
688 | } | |
689 | ||
690 | /* Since we may have empty frags without any mapping symbols, | |
691 | keep looking until the non-empty frag. */ | |
692 | if (next->fr_address != next->fr_next->fr_address) | |
693 | break; | |
694 | ||
695 | next = next->fr_next; | |
696 | } | |
697 | while (next != NULL); | |
698 | } | |
699 | } | |
700 | ||
e23eba97 NC |
701 | /* The default target format to use. */ |
702 | ||
703 | const char * | |
704 | riscv_target_format (void) | |
705 | { | |
fbc09e7a MC |
706 | if (target_big_endian) |
707 | return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv"; | |
708 | else | |
709 | return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; | |
e23eba97 NC |
710 | } |
711 | ||
712 | /* Return the length of instruction INSN. */ | |
713 | ||
714 | static inline unsigned int | |
715 | insn_length (const struct riscv_cl_insn *insn) | |
716 | { | |
717 | return riscv_insn_length (insn->insn_opcode); | |
718 | } | |
719 | ||
720 | /* Initialise INSN from opcode entry MO. Leave its position unspecified. */ | |
721 | ||
722 | static void | |
723 | create_insn (struct riscv_cl_insn *insn, const struct riscv_opcode *mo) | |
724 | { | |
725 | insn->insn_mo = mo; | |
726 | insn->insn_opcode = mo->match; | |
634001bb | 727 | insn->insn_long_opcode[0] = 0; |
e23eba97 NC |
728 | insn->frag = NULL; |
729 | insn->where = 0; | |
730 | insn->fixp = NULL; | |
731 | } | |
732 | ||
733 | /* Install INSN at the location specified by its "frag" and "where" fields. */ | |
734 | ||
735 | static void | |
736 | install_insn (const struct riscv_cl_insn *insn) | |
737 | { | |
738 | char *f = insn->frag->fr_literal + insn->where; | |
634001bb TO |
739 | if (insn->insn_long_opcode[0] != 0) |
740 | memcpy (f, insn->insn_long_opcode, insn_length (insn)); | |
741 | else | |
742 | number_to_chars_littleendian (f, insn->insn_opcode, insn_length (insn)); | |
e23eba97 NC |
743 | } |
744 | ||
745 | /* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly | |
746 | and install the opcode in the new location. */ | |
747 | ||
748 | static void | |
749 | move_insn (struct riscv_cl_insn *insn, fragS *frag, long where) | |
750 | { | |
751 | insn->frag = frag; | |
752 | insn->where = where; | |
753 | if (insn->fixp != NULL) | |
754 | { | |
755 | insn->fixp->fx_frag = frag; | |
756 | insn->fixp->fx_where = where; | |
757 | } | |
758 | install_insn (insn); | |
759 | } | |
760 | ||
761 | /* Add INSN to the end of the output. */ | |
762 | ||
763 | static void | |
764 | add_fixed_insn (struct riscv_cl_insn *insn) | |
765 | { | |
766 | char *f = frag_more (insn_length (insn)); | |
767 | move_insn (insn, frag_now, f - frag_now->fr_literal); | |
768 | } | |
769 | ||
770 | static void | |
771 | add_relaxed_insn (struct riscv_cl_insn *insn, int max_chars, int var, | |
772 | relax_substateT subtype, symbolS *symbol, offsetT offset) | |
773 | { | |
774 | frag_grow (max_chars); | |
775 | move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal); | |
776 | frag_var (rs_machine_dependent, max_chars, var, | |
777 | subtype, symbol, offset, NULL); | |
778 | } | |
779 | ||
780 | /* Compute the length of a branch sequence, and adjust the stored length | |
781 | accordingly. If FRAGP is NULL, the worst-case length is returned. */ | |
782 | ||
783 | static unsigned | |
784 | relaxed_branch_length (fragS *fragp, asection *sec, int update) | |
785 | { | |
786 | int jump, rvc, length = 8; | |
787 | ||
788 | if (!fragp) | |
789 | return length; | |
790 | ||
791 | jump = RELAX_BRANCH_UNCOND (fragp->fr_subtype); | |
792 | rvc = RELAX_BRANCH_RVC (fragp->fr_subtype); | |
793 | length = RELAX_BRANCH_LENGTH (fragp->fr_subtype); | |
794 | ||
795 | /* Assume jumps are in range; the linker will catch any that aren't. */ | |
796 | length = jump ? 4 : 8; | |
797 | ||
798 | if (fragp->fr_symbol != NULL | |
799 | && S_IS_DEFINED (fragp->fr_symbol) | |
01156111 | 800 | && !S_IS_WEAK (fragp->fr_symbol) |
e23eba97 NC |
801 | && sec == S_GET_SEGMENT (fragp->fr_symbol)) |
802 | { | |
803 | offsetT val = S_GET_VALUE (fragp->fr_symbol) + fragp->fr_offset; | |
804 | bfd_vma rvc_range = jump ? RVC_JUMP_REACH : RVC_BRANCH_REACH; | |
805 | val -= fragp->fr_address + fragp->fr_fix; | |
806 | ||
807 | if (rvc && (bfd_vma)(val + rvc_range/2) < rvc_range) | |
808 | length = 2; | |
809 | else if ((bfd_vma)(val + RISCV_BRANCH_REACH/2) < RISCV_BRANCH_REACH) | |
810 | length = 4; | |
811 | else if (!jump && rvc) | |
812 | length = 6; | |
813 | } | |
814 | ||
815 | if (update) | |
816 | fragp->fr_subtype = RELAX_BRANCH_ENCODE (jump, rvc, length); | |
817 | ||
818 | return length; | |
819 | } | |
820 | ||
0e35537d JW |
821 | /* Information about an opcode name, mnemonics and its value. */ |
822 | struct opcode_name_t | |
823 | { | |
824 | const char *name; | |
825 | unsigned int val; | |
826 | }; | |
827 | ||
828 | /* List for all supported opcode name. */ | |
829 | static const struct opcode_name_t opcode_name_list[] = | |
830 | { | |
831 | {"C0", 0x0}, | |
832 | {"C1", 0x1}, | |
833 | {"C2", 0x2}, | |
834 | ||
835 | {"LOAD", 0x03}, | |
836 | {"LOAD_FP", 0x07}, | |
837 | {"CUSTOM_0", 0x0b}, | |
838 | {"MISC_MEM", 0x0f}, | |
839 | {"OP_IMM", 0x13}, | |
840 | {"AUIPC", 0x17}, | |
841 | {"OP_IMM_32", 0x1b}, | |
842 | /* 48b 0x1f. */ | |
843 | ||
844 | {"STORE", 0x23}, | |
845 | {"STORE_FP", 0x27}, | |
846 | {"CUSTOM_1", 0x2b}, | |
847 | {"AMO", 0x2f}, | |
848 | {"OP", 0x33}, | |
849 | {"LUI", 0x37}, | |
850 | {"OP_32", 0x3b}, | |
851 | /* 64b 0x3f. */ | |
852 | ||
853 | {"MADD", 0x43}, | |
854 | {"MSUB", 0x47}, | |
855 | {"NMADD", 0x4f}, | |
856 | {"NMSUB", 0x4b}, | |
857 | {"OP_FP", 0x53}, | |
f8ad70a1 | 858 | {"OP_V", 0x57}, |
0e35537d JW |
859 | {"CUSTOM_2", 0x5b}, |
860 | /* 48b 0x5f. */ | |
861 | ||
862 | {"BRANCH", 0x63}, | |
863 | {"JALR", 0x67}, | |
864 | /*reserved 0x5b. */ | |
865 | {"JAL", 0x6f}, | |
866 | {"SYSTEM", 0x73}, | |
867 | /*reserved 0x77. */ | |
868 | {"CUSTOM_3", 0x7b}, | |
869 | /* >80b 0x7f. */ | |
870 | ||
871 | {NULL, 0} | |
872 | }; | |
873 | ||
874 | /* Hash table for lookup opcode name. */ | |
629310ab | 875 | static htab_t opcode_names_hash = NULL; |
0e35537d JW |
876 | |
877 | /* Initialization for hash table of opcode name. */ | |
dcd709e0 | 878 | |
0e35537d JW |
879 | static void |
880 | init_opcode_names_hash (void) | |
881 | { | |
0e35537d JW |
882 | const struct opcode_name_t *opcode; |
883 | ||
884 | for (opcode = &opcode_name_list[0]; opcode->name != NULL; ++opcode) | |
fe0e921f | 885 | if (str_hash_insert (opcode_names_hash, opcode->name, opcode, 0) != NULL) |
b800637e | 886 | as_fatal (_("internal: duplicate %s"), opcode->name); |
0e35537d JW |
887 | } |
888 | ||
dcd709e0 NC |
889 | /* Find `s` is a valid opcode name or not, return the opcode name info |
890 | if found. */ | |
891 | ||
0e35537d JW |
892 | static const struct opcode_name_t * |
893 | opcode_name_lookup (char **s) | |
894 | { | |
895 | char *e; | |
896 | char save_c; | |
897 | struct opcode_name_t *o; | |
898 | ||
899 | /* Find end of name. */ | |
900 | e = *s; | |
901 | if (is_name_beginner (*e)) | |
902 | ++e; | |
903 | while (is_part_of_name (*e)) | |
904 | ++e; | |
905 | ||
906 | /* Terminate name. */ | |
907 | save_c = *e; | |
908 | *e = '\0'; | |
909 | ||
629310ab | 910 | o = (struct opcode_name_t *) str_hash_find (opcode_names_hash, *s); |
0e35537d JW |
911 | |
912 | /* Advance to next token if one was recognized. */ | |
913 | if (o) | |
914 | *s = e; | |
915 | ||
916 | *e = save_c; | |
6eb099ae | 917 | expr_parse_end = e; |
0e35537d JW |
918 | |
919 | return o; | |
920 | } | |
921 | ||
437e2ff1 | 922 | /* All RISC-V registers belong to one of these classes. */ |
e23eba97 NC |
923 | enum reg_class |
924 | { | |
925 | RCLASS_GPR, | |
926 | RCLASS_FPR, | |
65e4a99a NC |
927 | RCLASS_VECR, |
928 | RCLASS_VECM, | |
8f595e9b NC |
929 | RCLASS_MAX, |
930 | ||
931 | RCLASS_CSR | |
e23eba97 NC |
932 | }; |
933 | ||
629310ab ML |
934 | static htab_t reg_names_hash = NULL; |
935 | static htab_t csr_extra_hash = NULL; | |
e23eba97 NC |
936 | |
937 | #define ENCODE_REG_HASH(cls, n) \ | |
938 | ((void *)(uintptr_t)((n) * RCLASS_MAX + (cls) + 1)) | |
939 | #define DECODE_REG_CLASS(hash) (((uintptr_t)(hash) - 1) % RCLASS_MAX) | |
940 | #define DECODE_REG_NUM(hash) (((uintptr_t)(hash) - 1) / RCLASS_MAX) | |
941 | ||
942 | static void | |
943 | hash_reg_name (enum reg_class class, const char *name, unsigned n) | |
944 | { | |
945 | void *hash = ENCODE_REG_HASH (class, n); | |
fe0e921f | 946 | if (str_hash_insert (reg_names_hash, name, hash, 0) != NULL) |
b800637e | 947 | as_fatal (_("internal: duplicate %s"), name); |
e23eba97 NC |
948 | } |
949 | ||
950 | static void | |
951 | hash_reg_names (enum reg_class class, const char * const names[], unsigned n) | |
952 | { | |
953 | unsigned i; | |
954 | ||
955 | for (i = 0; i < n; i++) | |
956 | hash_reg_name (class, names[i], i); | |
957 | } | |
958 | ||
8f595e9b | 959 | /* Init hash table csr_extra_hash to handle CSR. */ |
dcd709e0 | 960 | |
8f595e9b NC |
961 | static void |
962 | riscv_init_csr_hash (const char *name, | |
3d73d29e NC |
963 | unsigned address, |
964 | enum riscv_csr_class class, | |
965 | enum riscv_spec_class define_version, | |
966 | enum riscv_spec_class abort_version) | |
8f595e9b NC |
967 | { |
968 | struct riscv_csr_extra *entry, *pre_entry; | |
5b7c81bd | 969 | bool need_enrty = true; |
8f595e9b NC |
970 | |
971 | pre_entry = NULL; | |
629310ab | 972 | entry = (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, name); |
8f595e9b NC |
973 | while (need_enrty && entry != NULL) |
974 | { | |
975 | if (entry->csr_class == class | |
1942a048 NC |
976 | && entry->address == address |
977 | && entry->define_version == define_version | |
978 | && entry->abort_version == abort_version) | |
5b7c81bd | 979 | need_enrty = false; |
8f595e9b NC |
980 | pre_entry = entry; |
981 | entry = entry->next; | |
982 | } | |
1942a048 | 983 | |
dcd709e0 | 984 | /* Duplicate CSR. */ |
8f595e9b NC |
985 | if (!need_enrty) |
986 | return; | |
bd0cf5a6 | 987 | |
7bfc4db2 | 988 | entry = notes_alloc (sizeof (*entry)); |
8f595e9b NC |
989 | entry->csr_class = class; |
990 | entry->address = address; | |
991 | entry->define_version = define_version; | |
992 | entry->abort_version = abort_version; | |
5c505568 | 993 | entry->next = NULL; |
8f595e9b | 994 | |
8f595e9b | 995 | if (pre_entry == NULL) |
fe0e921f | 996 | str_hash_insert (csr_extra_hash, name, entry, 0); |
8f595e9b NC |
997 | else |
998 | pre_entry->next = entry; | |
999 | } | |
bd0cf5a6 | 1000 | |
dcd709e0 NC |
1001 | /* Return the CSR address after checking the ISA dependency and |
1002 | the privileged spec version. | |
1003 | ||
1004 | There are one warning and two errors for CSR, | |
1005 | ||
1006 | Invalid CSR: the CSR was defined, but isn't allowed for the current ISA | |
1007 | or the privileged spec, report warning only if -mcsr-check is set. | |
1008 | Unknown CSR: the CSR has never been defined, report error. | |
1009 | Improper CSR: the CSR number over the range (> 0xfff), report error. */ | |
bd0cf5a6 | 1010 | |
08ccfccf NC |
1011 | static unsigned int |
1012 | riscv_csr_address (const char *csr_name, | |
1013 | struct riscv_csr_extra *entry) | |
bd0cf5a6 | 1014 | { |
08ccfccf NC |
1015 | struct riscv_csr_extra *saved_entry = entry; |
1016 | enum riscv_csr_class csr_class = entry->csr_class; | |
df0a549e | 1017 | bool need_check_version = false; |
39590abd TO |
1018 | bool is_rv32_only = false; |
1019 | bool is_h_required = false; | |
df0a549e | 1020 | const char* extension = NULL; |
8f595e9b | 1021 | |
8f595e9b | 1022 | switch (csr_class) |
bd0cf5a6 | 1023 | { |
08ccfccf | 1024 | case CSR_CLASS_I_32: |
39590abd | 1025 | is_rv32_only = true; |
df0a549e PN |
1026 | /* Fall through. */ |
1027 | case CSR_CLASS_I: | |
1028 | need_check_version = true; | |
1029 | extension = "i"; | |
08ccfccf | 1030 | break; |
c625f4ed | 1031 | case CSR_CLASS_H_32: |
39590abd | 1032 | is_rv32_only = true; |
c625f4ed NC |
1033 | /* Fall through. */ |
1034 | case CSR_CLASS_H: | |
1035 | extension = "h"; | |
1036 | break; | |
8f595e9b | 1037 | case CSR_CLASS_F: |
df0a549e | 1038 | extension = "f"; |
8f595e9b | 1039 | break; |
3d1cafa0 | 1040 | case CSR_CLASS_ZKR: |
df0a549e | 1041 | extension = "zkr"; |
3d1cafa0 | 1042 | break; |
65e4a99a | 1043 | case CSR_CLASS_V: |
1daabcc7 | 1044 | extension = "zve32x"; |
65e4a99a | 1045 | break; |
ac8df5a1 CM |
1046 | case CSR_CLASS_SMAIA_32: |
1047 | is_rv32_only = true; | |
1048 | /* Fall through. */ | |
1049 | case CSR_CLASS_SMAIA: | |
1050 | extension = "smaia"; | |
1051 | break; | |
6af47b08 | 1052 | case CSR_CLASS_SMSTATEEN_32: |
c509db05 TO |
1053 | is_rv32_only = true; |
1054 | /* Fall through. */ | |
1055 | case CSR_CLASS_SMSTATEEN: | |
6af47b08 TO |
1056 | extension = "smstateen"; |
1057 | break; | |
ac8df5a1 CM |
1058 | case CSR_CLASS_SSAIA: |
1059 | case CSR_CLASS_SSAIA_AND_H: | |
1060 | case CSR_CLASS_SSAIA_32: | |
1061 | case CSR_CLASS_SSAIA_AND_H_32: | |
1062 | is_rv32_only = (csr_class == CSR_CLASS_SSAIA_32 | |
1063 | || csr_class == CSR_CLASS_SSAIA_AND_H_32); | |
1064 | is_h_required = (csr_class == CSR_CLASS_SSAIA_AND_H | |
1065 | || csr_class == CSR_CLASS_SSAIA_AND_H_32); | |
1066 | extension = "ssaia"; | |
1067 | break; | |
15253318 | 1068 | case CSR_CLASS_SSSTATEEN_AND_H_32: |
c509db05 TO |
1069 | is_rv32_only = true; |
1070 | /* Fall through. */ | |
1071 | case CSR_CLASS_SSSTATEEN_AND_H: | |
1072 | is_h_required = true; | |
1073 | /* Fall through. */ | |
1074 | case CSR_CLASS_SSSTATEEN: | |
15253318 TO |
1075 | extension = "ssstateen"; |
1076 | break; | |
713f3708 TO |
1077 | case CSR_CLASS_SSCOFPMF_32: |
1078 | is_rv32_only = true; | |
1079 | /* Fall through. */ | |
1080 | case CSR_CLASS_SSCOFPMF: | |
1081 | extension = "sscofpmf"; | |
1082 | break; | |
766077c1 TO |
1083 | case CSR_CLASS_SSTC: |
1084 | case CSR_CLASS_SSTC_AND_H: | |
1085 | case CSR_CLASS_SSTC_32: | |
1086 | case CSR_CLASS_SSTC_AND_H_32: | |
1087 | is_rv32_only = (csr_class == CSR_CLASS_SSTC_32 | |
1088 | || csr_class == CSR_CLASS_SSTC_AND_H_32); | |
1089 | is_h_required = (csr_class == CSR_CLASS_SSTC_AND_H | |
1090 | || csr_class == CSR_CLASS_SSTC_AND_H_32); | |
1091 | extension = "sstc"; | |
1092 | break; | |
08ccfccf | 1093 | case CSR_CLASS_DEBUG: |
8f595e9b NC |
1094 | break; |
1095 | default: | |
1096 | as_bad (_("internal: bad RISC-V CSR class (0x%x)"), csr_class); | |
bd0cf5a6 NC |
1097 | } |
1098 | ||
df0a549e PN |
1099 | if (riscv_opts.csr_check) |
1100 | { | |
39590abd | 1101 | if (is_rv32_only && xlen != 32) |
df0a549e | 1102 | as_warn (_("invalid CSR `%s', needs rv32i extension"), csr_name); |
39590abd TO |
1103 | if (is_h_required && !riscv_subset_supports (&riscv_rps_as, "h")) |
1104 | as_warn (_("invalid CSR `%s', needs `h' extension"), csr_name); | |
df0a549e PN |
1105 | |
1106 | if (extension != NULL | |
1107 | && !riscv_subset_supports (&riscv_rps_as, extension)) | |
1108 | as_warn (_("invalid CSR `%s', needs `%s' extension"), | |
1109 | csr_name, extension); | |
1110 | } | |
8f595e9b NC |
1111 | |
1112 | while (entry != NULL) | |
bd0cf5a6 | 1113 | { |
08ccfccf NC |
1114 | if (!need_check_version |
1115 | || (default_priv_spec >= entry->define_version | |
1116 | && default_priv_spec < entry->abort_version)) | |
8f595e9b | 1117 | { |
dcd709e0 | 1118 | /* Find the CSR according to the specific version. */ |
08ccfccf | 1119 | return entry->address; |
8f595e9b NC |
1120 | } |
1121 | entry = entry->next; | |
1122 | } | |
bd0cf5a6 | 1123 | |
dcd709e0 NC |
1124 | /* Can not find the CSR address from the chosen privileged version, |
1125 | so use the newly defined value. */ | |
8f595e9b NC |
1126 | if (riscv_opts.csr_check) |
1127 | { | |
3d73d29e NC |
1128 | const char *priv_name = NULL; |
1129 | RISCV_GET_PRIV_SPEC_NAME (priv_name, default_priv_spec); | |
8f595e9b | 1130 | if (priv_name != NULL) |
b800637e | 1131 | as_warn (_("invalid CSR `%s' for the privileged spec `%s'"), |
8f595e9b | 1132 | csr_name, priv_name); |
bd0cf5a6 | 1133 | } |
08ccfccf NC |
1134 | |
1135 | return saved_entry->address; | |
bd0cf5a6 NC |
1136 | } |
1137 | ||
dcd709e0 NC |
1138 | /* Return -1 if the CSR has never been defined. Otherwise, return |
1139 | the address. */ | |
bd0cf5a6 | 1140 | |
8f595e9b | 1141 | static unsigned int |
bd0cf5a6 NC |
1142 | reg_csr_lookup_internal (const char *s) |
1143 | { | |
1144 | struct riscv_csr_extra *r = | |
629310ab | 1145 | (struct riscv_csr_extra *) str_hash_find (csr_extra_hash, s); |
bd0cf5a6 NC |
1146 | |
1147 | if (r == NULL) | |
8f595e9b | 1148 | return -1U; |
bd0cf5a6 | 1149 | |
08ccfccf | 1150 | return riscv_csr_address (s, r); |
bd0cf5a6 NC |
1151 | } |
1152 | ||
e23eba97 NC |
1153 | static unsigned int |
1154 | reg_lookup_internal (const char *s, enum reg_class class) | |
1155 | { | |
8f595e9b NC |
1156 | void *r; |
1157 | ||
1158 | if (class == RCLASS_CSR) | |
1159 | return reg_csr_lookup_internal (s); | |
e23eba97 | 1160 | |
629310ab | 1161 | r = str_hash_find (reg_names_hash, s); |
e23eba97 NC |
1162 | if (r == NULL || DECODE_REG_CLASS (r) != class) |
1163 | return -1; | |
7f999549 | 1164 | |
f786c359 | 1165 | if (riscv_subset_supports (&riscv_rps_as, "e") |
edc77c59 NC |
1166 | && class == RCLASS_GPR |
1167 | && DECODE_REG_NUM (r) > 15) | |
7f999549 JW |
1168 | return -1; |
1169 | ||
e23eba97 NC |
1170 | return DECODE_REG_NUM (r); |
1171 | } | |
1172 | ||
5b7c81bd | 1173 | static bool |
e23eba97 NC |
1174 | reg_lookup (char **s, enum reg_class class, unsigned int *regnop) |
1175 | { | |
1176 | char *e; | |
1177 | char save_c; | |
1178 | int reg = -1; | |
1179 | ||
1180 | /* Find end of name. */ | |
1181 | e = *s; | |
1182 | if (is_name_beginner (*e)) | |
1183 | ++e; | |
1184 | while (is_part_of_name (*e)) | |
1185 | ++e; | |
1186 | ||
1187 | /* Terminate name. */ | |
1188 | save_c = *e; | |
1189 | *e = '\0'; | |
1190 | ||
1191 | /* Look for the register. Advance to next token if one was recognized. */ | |
1192 | if ((reg = reg_lookup_internal (*s, class)) >= 0) | |
1193 | *s = e; | |
1194 | ||
1195 | *e = save_c; | |
1196 | if (regnop) | |
1197 | *regnop = reg; | |
1198 | return reg >= 0; | |
1199 | } | |
1200 | ||
5b7c81bd | 1201 | static bool |
e23eba97 NC |
1202 | arg_lookup (char **s, const char *const *array, size_t size, unsigned *regnop) |
1203 | { | |
1204 | const char *p = strchr (*s, ','); | |
1205 | size_t i, len = p ? (size_t)(p - *s) : strlen (*s); | |
1206 | ||
bfb218e3 | 1207 | if (len == 0) |
5b7c81bd | 1208 | return false; |
bfb218e3 | 1209 | |
e23eba97 | 1210 | for (i = 0; i < size; i++) |
207cc92d LX |
1211 | if (array[i] != NULL && strncmp (array[i], *s, len) == 0 |
1212 | && array[i][len] == '\0') | |
e23eba97 NC |
1213 | { |
1214 | *regnop = i; | |
1215 | *s += len; | |
5b7c81bd | 1216 | return true; |
e23eba97 NC |
1217 | } |
1218 | ||
5b7c81bd | 1219 | return false; |
e23eba97 NC |
1220 | } |
1221 | ||
437e2ff1 | 1222 | #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) |
8b7419c4 CM |
1223 | #define USE_IMM(n, s) \ |
1224 | (used_bits |= ((insn_t)((1ull<<n)-1) << (s))) | |
437e2ff1 | 1225 | |
e23eba97 NC |
1226 | /* For consistency checking, verify that all bits are specified either |
1227 | by the match/mask part of the instruction definition, or by the | |
83029f7f TO |
1228 | operand list. The `length` could be the actual instruction length or |
1229 | 0 for auto-detection. */ | |
0e35537d | 1230 | |
5b7c81bd | 1231 | static bool |
0e35537d | 1232 | validate_riscv_insn (const struct riscv_opcode *opc, int length) |
e23eba97 | 1233 | { |
437e2ff1 | 1234 | const char *oparg, *opargStart; |
e23eba97 | 1235 | insn_t used_bits = opc->mask; |
0e35537d JW |
1236 | int insn_width; |
1237 | insn_t required_bits; | |
1238 | ||
1239 | if (length == 0) | |
83029f7f TO |
1240 | length = riscv_insn_length (opc->match); |
1241 | /* We don't support instructions longer than 64-bits yet. */ | |
1242 | if (length > 8) | |
1243 | length = 8; | |
1244 | insn_width = 8 * length; | |
0e35537d | 1245 | |
83029f7f | 1246 | required_bits = ((insn_t)~0ULL) >> (64 - insn_width); |
e23eba97 NC |
1247 | |
1248 | if ((used_bits & opc->match) != (opc->match & required_bits)) | |
1249 | { | |
1250 | as_bad (_("internal: bad RISC-V opcode (mask error): %s %s"), | |
1251 | opc->name, opc->args); | |
5b7c81bd | 1252 | return false; |
e23eba97 NC |
1253 | } |
1254 | ||
437e2ff1 NC |
1255 | for (oparg = opc->args; *oparg; ++oparg) |
1256 | { | |
1257 | opargStart = oparg; | |
1258 | switch (*oparg) | |
1259 | { | |
1260 | case 'C': /* RVC */ | |
1261 | switch (*++oparg) | |
1262 | { | |
1263 | case 'U': break; /* CRS1, constrained to equal RD. */ | |
1264 | case 'c': break; /* CRS1, constrained to equal sp. */ | |
1265 | case 'T': /* CRS2, floating point. */ | |
1266 | case 'V': USE_BITS (OP_MASK_CRS2, OP_SH_CRS2); break; | |
1267 | case 'S': /* CRS1S, floating point. */ | |
1268 | case 's': USE_BITS (OP_MASK_CRS1S, OP_SH_CRS1S); break; | |
1269 | case 'w': break; /* CRS1S, constrained to equal RD. */ | |
1270 | case 'D': /* CRS2S, floating point. */ | |
1271 | case 't': USE_BITS (OP_MASK_CRS2S, OP_SH_CRS2S); break; | |
1272 | case 'x': break; /* CRS2S, constrained to equal RD. */ | |
1273 | case 'z': break; /* CRS2S, constrained to be x0. */ | |
1274 | case '>': /* CITYPE immediate, compressed shift. */ | |
1275 | case 'u': /* CITYPE immediate, compressed lui. */ | |
1276 | case 'v': /* CITYPE immediate, li to compressed lui. */ | |
1277 | case 'o': /* CITYPE immediate, allow zero. */ | |
1278 | case 'j': used_bits |= ENCODE_CITYPE_IMM (-1U); break; | |
1279 | case 'L': used_bits |= ENCODE_CITYPE_ADDI16SP_IMM (-1U); break; | |
1280 | case 'm': used_bits |= ENCODE_CITYPE_LWSP_IMM (-1U); break; | |
1281 | case 'n': used_bits |= ENCODE_CITYPE_LDSP_IMM (-1U); break; | |
1282 | case '6': used_bits |= ENCODE_CSSTYPE_IMM (-1U); break; | |
1283 | case 'M': used_bits |= ENCODE_CSSTYPE_SWSP_IMM (-1U); break; | |
1284 | case 'N': used_bits |= ENCODE_CSSTYPE_SDSP_IMM (-1U); break; | |
1285 | case '8': used_bits |= ENCODE_CIWTYPE_IMM (-1U); break; | |
1286 | case 'K': used_bits |= ENCODE_CIWTYPE_ADDI4SPN_IMM (-1U); break; | |
1287 | /* CLTYPE and CSTYPE have the same immediate encoding. */ | |
1288 | case '5': used_bits |= ENCODE_CLTYPE_IMM (-1U); break; | |
1289 | case 'k': used_bits |= ENCODE_CLTYPE_LW_IMM (-1U); break; | |
1290 | case 'l': used_bits |= ENCODE_CLTYPE_LD_IMM (-1U); break; | |
1291 | case 'p': used_bits |= ENCODE_CBTYPE_IMM (-1U); break; | |
1292 | case 'a': used_bits |= ENCODE_CJTYPE_IMM (-1U); break; | |
1293 | case 'F': /* Compressed funct for .insn directive. */ | |
1294 | switch (*++oparg) | |
1295 | { | |
65e4a99a NC |
1296 | case '6': USE_BITS (OP_MASK_CFUNCT6, OP_SH_CFUNCT6); break; |
1297 | case '4': USE_BITS (OP_MASK_CFUNCT4, OP_SH_CFUNCT4); break; | |
1298 | case '3': USE_BITS (OP_MASK_CFUNCT3, OP_SH_CFUNCT3); break; | |
1299 | case '2': USE_BITS (OP_MASK_CFUNCT2, OP_SH_CFUNCT2); break; | |
1300 | default: | |
1301 | goto unknown_validate_operand; | |
437e2ff1 NC |
1302 | } |
1303 | break; | |
0e35537d | 1304 | default: |
437e2ff1 NC |
1305 | goto unknown_validate_operand; |
1306 | } | |
a63375ac | 1307 | break; /* end RVC */ |
65e4a99a NC |
1308 | case 'V': /* RVV */ |
1309 | switch (*++oparg) | |
1310 | { | |
1311 | case 'd': | |
1312 | case 'f': USE_BITS (OP_MASK_VD, OP_SH_VD); break; | |
1313 | case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break; | |
1314 | case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break; | |
1315 | case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1316 | case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1); | |
1317 | USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1318 | case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD); | |
1319 | USE_BITS (OP_MASK_VS1, OP_SH_VS1); | |
1320 | USE_BITS (OP_MASK_VS2, OP_SH_VS2); break; | |
1321 | case '0': break; | |
1322 | case 'b': used_bits |= ENCODE_RVV_VB_IMM (-1U); break; | |
1323 | case 'c': used_bits |= ENCODE_RVV_VC_IMM (-1U); break; | |
1324 | case 'i': | |
1325 | case 'j': | |
1326 | case 'k': USE_BITS (OP_MASK_VIMM, OP_SH_VIMM); break; | |
1327 | case 'm': USE_BITS (OP_MASK_VMASK, OP_SH_VMASK); break; | |
c1ecdee7 TO |
1328 | case 'M': break; /* Macro operand, must be a mask register. */ |
1329 | case 'T': break; /* Macro operand, must be a vector register. */ | |
65e4a99a NC |
1330 | default: |
1331 | goto unknown_validate_operand; | |
1332 | } | |
a63375ac | 1333 | break; /* end RVV */ |
437e2ff1 NC |
1334 | case ',': break; |
1335 | case '(': break; | |
1336 | case ')': break; | |
1337 | case '<': USE_BITS (OP_MASK_SHAMTW, OP_SH_SHAMTW); break; | |
1338 | case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; | |
1339 | case 'A': break; /* Macro operand, must be symbol. */ | |
1340 | case 'B': break; /* Macro operand, must be symbol or constant. */ | |
c1ecdee7 | 1341 | case 'c': break; /* Macro operand, must be symbol or constant. */ |
437e2ff1 NC |
1342 | case 'I': break; /* Macro operand, must be constant. */ |
1343 | case 'D': /* RD, floating point. */ | |
1344 | case 'd': USE_BITS (OP_MASK_RD, OP_SH_RD); break; | |
3d1cafa0 | 1345 | case 'y': USE_BITS (OP_MASK_BS, OP_SH_BS); break; |
1346 | case 'Y': USE_BITS (OP_MASK_RNUM, OP_SH_RNUM); break; | |
437e2ff1 NC |
1347 | case 'Z': /* RS1, CSR number. */ |
1348 | case 'S': /* RS1, floating point. */ | |
1349 | case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; | |
1350 | case 'U': /* RS1 and RS2 are the same, floating point. */ | |
1351 | USE_BITS (OP_MASK_RS1, OP_SH_RS1); | |
1352 | /* Fall through. */ | |
1353 | case 'T': /* RS2, floating point. */ | |
1354 | case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break; | |
1355 | case 'R': /* RS3, floating point. */ | |
1356 | case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break; | |
1357 | case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break; | |
1358 | case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break; | |
1359 | case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break; | |
1360 | case 'Q': USE_BITS (OP_MASK_SUCC, OP_SH_SUCC); break; | |
1361 | case 'o': /* ITYPE immediate, load displacement. */ | |
1362 | case 'j': used_bits |= ENCODE_ITYPE_IMM (-1U); break; | |
1363 | case 'a': used_bits |= ENCODE_JTYPE_IMM (-1U); break; | |
1364 | case 'p': used_bits |= ENCODE_BTYPE_IMM (-1U); break; | |
3b374308 | 1365 | case 'f': /* Fall through. */ |
437e2ff1 NC |
1366 | case 'q': used_bits |= ENCODE_STYPE_IMM (-1U); break; |
1367 | case 'u': used_bits |= ENCODE_UTYPE_IMM (-1U); break; | |
1368 | case 'z': break; /* Zero immediate. */ | |
1369 | case '[': break; /* Unused operand. */ | |
1370 | case ']': break; /* Unused operand. */ | |
1371 | case '0': break; /* AMO displacement, must to zero. */ | |
1372 | case '1': break; /* Relaxation operand. */ | |
1373 | case 'F': /* Funct for .insn directive. */ | |
1374 | switch (*++oparg) | |
1375 | { | |
1376 | case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break; | |
1377 | case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break; | |
1378 | case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break; | |
1379 | default: | |
1380 | goto unknown_validate_operand; | |
1381 | } | |
1382 | break; | |
1383 | case 'O': /* Opcode for .insn directive. */ | |
1384 | switch (*++oparg) | |
1385 | { | |
1386 | case '4': USE_BITS (OP_MASK_OP, OP_SH_OP); break; | |
1387 | case '2': USE_BITS (OP_MASK_OP2, OP_SH_OP2); break; | |
1388 | default: | |
1389 | goto unknown_validate_operand; | |
1390 | } | |
1391 | break; | |
8b7419c4 CM |
1392 | case 'X': /* Integer immediate. */ |
1393 | { | |
1394 | size_t n; | |
1395 | size_t s; | |
1396 | ||
1397 | switch (*++oparg) | |
1398 | { | |
25236d63 CM |
1399 | case 'l': /* Literal. */ |
1400 | oparg += strcspn(oparg, ",") - 1; | |
1401 | break; | |
8b7419c4 CM |
1402 | case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ |
1403 | goto use_imm; | |
1404 | case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ | |
1405 | goto use_imm; | |
1406 | use_imm: | |
b0423163 | 1407 | n = strtol (oparg + 1, (char **)&oparg, 10); |
8b7419c4 CM |
1408 | if (*oparg != '@') |
1409 | goto unknown_validate_operand; | |
b0423163 | 1410 | s = strtol (oparg + 1, (char **)&oparg, 10); |
8b7419c4 CM |
1411 | oparg--; |
1412 | ||
1413 | USE_IMM (n, s); | |
1414 | break; | |
1415 | default: | |
1416 | goto unknown_validate_operand; | |
1417 | } | |
1418 | } | |
1419 | break; | |
437e2ff1 NC |
1420 | default: |
1421 | unknown_validate_operand: | |
1422 | as_bad (_("internal: bad RISC-V opcode " | |
1423 | "(unknown operand type `%s'): %s %s"), | |
1424 | opargStart, opc->name, opc->args); | |
1425 | return false; | |
1426 | } | |
1427 | } | |
1428 | ||
e23eba97 NC |
1429 | if (used_bits != required_bits) |
1430 | { | |
b800637e | 1431 | as_bad (_("internal: bad RISC-V opcode " |
6b84c098 TO |
1432 | "(bits %#llx undefined or invalid): %s %s"), |
1433 | (unsigned long long)(used_bits ^ required_bits), | |
e23eba97 | 1434 | opc->name, opc->args); |
5b7c81bd | 1435 | return false; |
e23eba97 | 1436 | } |
5b7c81bd | 1437 | return true; |
e23eba97 NC |
1438 | } |
1439 | ||
437e2ff1 NC |
1440 | #undef USE_BITS |
1441 | ||
e23eba97 NC |
1442 | struct percent_op_match |
1443 | { | |
1444 | const char *str; | |
1445 | bfd_reloc_code_real_type reloc; | |
1446 | }; | |
1447 | ||
dcd709e0 NC |
1448 | /* Common hash table initialization function for instruction and .insn |
1449 | directive. */ | |
1450 | ||
629310ab | 1451 | static htab_t |
0e35537d | 1452 | init_opcode_hash (const struct riscv_opcode *opcodes, |
5b7c81bd | 1453 | bool insn_directive_p) |
e23eba97 NC |
1454 | { |
1455 | int i = 0; | |
0e35537d | 1456 | int length; |
629310ab | 1457 | htab_t hash = str_htab_create (); |
0e35537d | 1458 | while (opcodes[i].name) |
e23eba97 | 1459 | { |
0e35537d | 1460 | const char *name = opcodes[i].name; |
fe0e921f | 1461 | if (str_hash_insert (hash, name, &opcodes[i], 0) != NULL) |
b800637e | 1462 | as_fatal (_("internal: duplicate %s"), name); |
e23eba97 NC |
1463 | |
1464 | do | |
1465 | { | |
0e35537d | 1466 | if (opcodes[i].pinfo != INSN_MACRO) |
e23eba97 | 1467 | { |
0e35537d JW |
1468 | if (insn_directive_p) |
1469 | length = ((name[0] == 'c') ? 2 : 4); | |
1470 | else | |
dcd709e0 | 1471 | length = 0; /* Let assembler determine the length. */ |
0e35537d | 1472 | if (!validate_riscv_insn (&opcodes[i], length)) |
b800637e NC |
1473 | as_fatal (_("internal: broken assembler. " |
1474 | "No assembly attempted")); | |
e23eba97 | 1475 | } |
0e35537d JW |
1476 | else |
1477 | gas_assert (!insn_directive_p); | |
e23eba97 NC |
1478 | ++i; |
1479 | } | |
0e35537d | 1480 | while (opcodes[i].name && !strcmp (opcodes[i].name, name)); |
e23eba97 NC |
1481 | } |
1482 | ||
0e35537d JW |
1483 | return hash; |
1484 | } | |
1485 | ||
1486 | /* This function is called once, at assembler startup time. It should set up | |
1487 | all the tables, etc. that the MD part of the assembler will need. */ | |
1488 | ||
1489 | void | |
1490 | md_begin (void) | |
1491 | { | |
1492 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
1493 | ||
1494 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
b800637e | 1495 | as_warn (_("could not set architecture and machine")); |
0e35537d | 1496 | |
5b7c81bd AM |
1497 | op_hash = init_opcode_hash (riscv_opcodes, false); |
1498 | insn_type_hash = init_opcode_hash (riscv_insn_types, true); | |
0e35537d | 1499 | |
629310ab | 1500 | reg_names_hash = str_htab_create (); |
e23eba97 NC |
1501 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_numeric, NGPR); |
1502 | hash_reg_names (RCLASS_GPR, riscv_gpr_names_abi, NGPR); | |
1503 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_numeric, NFPR); | |
1504 | hash_reg_names (RCLASS_FPR, riscv_fpr_names_abi, NFPR); | |
65e4a99a NC |
1505 | hash_reg_names (RCLASS_VECR, riscv_vecr_names_numeric, NVECR); |
1506 | hash_reg_names (RCLASS_VECM, riscv_vecm_names_numeric, NVECM); | |
b9c04e5a JW |
1507 | /* Add "fp" as an alias for "s0". */ |
1508 | hash_reg_name (RCLASS_GPR, "fp", 8); | |
1509 | ||
bd0cf5a6 | 1510 | /* Create and insert CSR hash tables. */ |
629310ab | 1511 | csr_extra_hash = str_htab_create (); |
8f595e9b NC |
1512 | #define DECLARE_CSR(name, num, class, define_version, abort_version) \ |
1513 | riscv_init_csr_hash (#name, num, class, define_version, abort_version); | |
1514 | #define DECLARE_CSR_ALIAS(name, num, class, define_version, abort_version) \ | |
1515 | DECLARE_CSR(name, num, class, define_version, abort_version); | |
e23eba97 NC |
1516 | #include "opcode/riscv-opc.h" |
1517 | #undef DECLARE_CSR | |
1518 | ||
629310ab | 1519 | opcode_names_hash = str_htab_create (); |
bd0cf5a6 NC |
1520 | init_opcode_names_hash (); |
1521 | ||
e23eba97 NC |
1522 | /* Set the default alignment for the text section. */ |
1523 | record_alignment (text_section, riscv_opts.rvc ? 1 : 2); | |
1524 | } | |
1525 | ||
45f76423 AW |
1526 | static insn_t |
1527 | riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value) | |
1528 | { | |
1529 | switch (reloc_type) | |
1530 | { | |
1531 | case BFD_RELOC_32: | |
1532 | return value; | |
1533 | ||
1534 | case BFD_RELOC_RISCV_HI20: | |
1535 | return ENCODE_UTYPE_IMM (RISCV_CONST_HIGH_PART (value)); | |
1536 | ||
1537 | case BFD_RELOC_RISCV_LO12_S: | |
1538 | return ENCODE_STYPE_IMM (value); | |
1539 | ||
1540 | case BFD_RELOC_RISCV_LO12_I: | |
1541 | return ENCODE_ITYPE_IMM (value); | |
1542 | ||
1543 | default: | |
1544 | abort (); | |
1545 | } | |
1546 | } | |
1547 | ||
e23eba97 NC |
1548 | /* Output an instruction. IP is the instruction information. |
1549 | ADDRESS_EXPR is an operand of the instruction to be used with | |
1550 | RELOC_TYPE. */ | |
1551 | ||
1552 | static void | |
1553 | append_insn (struct riscv_cl_insn *ip, expressionS *address_expr, | |
1554 | bfd_reloc_code_real_type reloc_type) | |
1555 | { | |
1556 | dwarf2_emit_insn (0); | |
1557 | ||
1558 | if (reloc_type != BFD_RELOC_UNUSED) | |
1559 | { | |
1560 | reloc_howto_type *howto; | |
1561 | ||
1d65abb5 | 1562 | gas_assert (address_expr); |
e23eba97 NC |
1563 | if (reloc_type == BFD_RELOC_12_PCREL |
1564 | || reloc_type == BFD_RELOC_RISCV_JMP) | |
1565 | { | |
1566 | int j = reloc_type == BFD_RELOC_RISCV_JMP; | |
8c07e983 | 1567 | int best_case = insn_length (ip); |
e23eba97 | 1568 | unsigned worst_case = relaxed_branch_length (NULL, NULL, 0); |
743f5cfc JW |
1569 | |
1570 | if (now_seg == absolute_section) | |
1571 | { | |
1572 | as_bad (_("relaxable branches not supported in absolute section")); | |
1573 | return; | |
1574 | } | |
1575 | ||
e23eba97 NC |
1576 | add_relaxed_insn (ip, worst_case, best_case, |
1577 | RELAX_BRANCH_ENCODE (j, best_case == 2, worst_case), | |
1578 | address_expr->X_add_symbol, | |
1579 | address_expr->X_add_number); | |
1580 | return; | |
1581 | } | |
45f76423 | 1582 | else |
e23eba97 | 1583 | { |
45f76423 AW |
1584 | howto = bfd_reloc_type_lookup (stdoutput, reloc_type); |
1585 | if (howto == NULL) | |
579f0281 | 1586 | as_bad (_("internal: unsupported RISC-V relocation number %d"), |
b800637e | 1587 | reloc_type); |
e23eba97 | 1588 | |
45f76423 AW |
1589 | ip->fixp = fix_new_exp (ip->frag, ip->where, |
1590 | bfd_get_reloc_size (howto), | |
5b7c81bd | 1591 | address_expr, false, reloc_type); |
e23eba97 | 1592 | |
45f76423 | 1593 | ip->fixp->fx_tcbit = riscv_opts.relax; |
e23eba97 | 1594 | } |
e23eba97 NC |
1595 | } |
1596 | ||
e23eba97 | 1597 | add_fixed_insn (ip); |
f77bb6c5 JW |
1598 | |
1599 | /* We need to start a new frag after any instruction that can be | |
1600 | optimized away or compressed by the linker during relaxation, to prevent | |
1601 | the assembler from computing static offsets across such an instruction. | |
1602 | This is necessary to get correct EH info. */ | |
b1b11e92 | 1603 | if (reloc_type == BFD_RELOC_RISCV_HI20 |
f77bb6c5 JW |
1604 | || reloc_type == BFD_RELOC_RISCV_PCREL_HI20 |
1605 | || reloc_type == BFD_RELOC_RISCV_TPREL_HI20 | |
1606 | || reloc_type == BFD_RELOC_RISCV_TPREL_ADD) | |
1607 | { | |
1608 | frag_wane (frag_now); | |
1609 | frag_new (0); | |
1610 | } | |
e23eba97 NC |
1611 | } |
1612 | ||
1613 | /* Build an instruction created by a macro expansion. This is passed | |
dcd709e0 NC |
1614 | a pointer to the count of instructions created so far, an expression, |
1615 | the name of the instruction to build, an operand format string, and | |
1616 | corresponding arguments. */ | |
e23eba97 NC |
1617 | |
1618 | static void | |
1619 | macro_build (expressionS *ep, const char *name, const char *fmt, ...) | |
1620 | { | |
1621 | const struct riscv_opcode *mo; | |
1622 | struct riscv_cl_insn insn; | |
1623 | bfd_reloc_code_real_type r; | |
1624 | va_list args; | |
437e2ff1 | 1625 | const char *fmtStart; |
e23eba97 NC |
1626 | |
1627 | va_start (args, fmt); | |
1628 | ||
1629 | r = BFD_RELOC_UNUSED; | |
629310ab | 1630 | mo = (struct riscv_opcode *) str_hash_find (op_hash, name); |
e23eba97 NC |
1631 | gas_assert (mo); |
1632 | ||
1633 | /* Find a non-RVC variant of the instruction. append_insn will compress | |
1634 | it if possible. */ | |
1635 | while (riscv_insn_length (mo->match) < 4) | |
1636 | mo++; | |
1637 | gas_assert (strcmp (name, mo->name) == 0); | |
1638 | ||
1639 | create_insn (&insn, mo); | |
437e2ff1 | 1640 | for (;; ++fmt) |
e23eba97 | 1641 | { |
437e2ff1 NC |
1642 | fmtStart = fmt; |
1643 | switch (*fmt) | |
e23eba97 | 1644 | { |
65e4a99a NC |
1645 | case 'V': /* RVV */ |
1646 | switch (*++fmt) | |
1647 | { | |
1648 | case 'd': | |
1649 | INSERT_OPERAND (VD, insn, va_arg (args, int)); | |
1650 | continue; | |
1651 | case 's': | |
1652 | INSERT_OPERAND (VS1, insn, va_arg (args, int)); | |
1653 | continue; | |
1654 | case 't': | |
1655 | INSERT_OPERAND (VS2, insn, va_arg (args, int)); | |
1656 | continue; | |
1657 | case 'm': | |
1658 | { | |
1659 | int reg = va_arg (args, int); | |
1660 | if (reg == -1) | |
1661 | { | |
1662 | INSERT_OPERAND (VMASK, insn, 1); | |
1663 | continue; | |
1664 | } | |
1665 | else if (reg == 0) | |
1666 | { | |
1667 | INSERT_OPERAND (VMASK, insn, 0); | |
1668 | continue; | |
1669 | } | |
1670 | else | |
1671 | goto unknown_macro_argument; | |
1672 | } | |
1673 | default: | |
1674 | goto unknown_macro_argument; | |
1675 | } | |
1676 | break; | |
1677 | ||
e23eba97 NC |
1678 | case 'd': |
1679 | INSERT_OPERAND (RD, insn, va_arg (args, int)); | |
1680 | continue; | |
e23eba97 NC |
1681 | case 's': |
1682 | INSERT_OPERAND (RS1, insn, va_arg (args, int)); | |
1683 | continue; | |
e23eba97 NC |
1684 | case 't': |
1685 | INSERT_OPERAND (RS2, insn, va_arg (args, int)); | |
1686 | continue; | |
1687 | ||
e23eba97 NC |
1688 | case 'j': |
1689 | case 'u': | |
1690 | case 'q': | |
1691 | gas_assert (ep != NULL); | |
1692 | r = va_arg (args, int); | |
1693 | continue; | |
1694 | ||
1695 | case '\0': | |
1696 | break; | |
1697 | case ',': | |
1698 | continue; | |
1699 | default: | |
65e4a99a | 1700 | unknown_macro_argument: |
437e2ff1 | 1701 | as_fatal (_("internal: invalid macro argument `%s'"), fmtStart); |
e23eba97 NC |
1702 | } |
1703 | break; | |
1704 | } | |
1705 | va_end (args); | |
1706 | gas_assert (r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL); | |
1707 | ||
1708 | append_insn (&insn, ep, r); | |
1709 | } | |
1710 | ||
db3b6ecc KC |
1711 | /* Build an instruction created by a macro expansion. Like md_assemble but |
1712 | accept a printf-style format string and arguments. */ | |
1713 | ||
1714 | static void | |
1715 | md_assemblef (const char *format, ...) | |
1716 | { | |
1717 | char *buf = NULL; | |
1718 | va_list ap; | |
1719 | int r; | |
1720 | ||
1721 | va_start (ap, format); | |
1722 | ||
1723 | r = vasprintf (&buf, format, ap); | |
1724 | ||
1725 | if (r < 0) | |
b800637e | 1726 | as_fatal (_("internal: vasprintf failed")); |
db3b6ecc KC |
1727 | |
1728 | md_assemble (buf); | |
1729 | free(buf); | |
1730 | ||
1731 | va_end (ap); | |
1732 | } | |
1733 | ||
e23eba97 NC |
1734 | /* Sign-extend 32-bit mode constants that have bit 31 set and all higher bits |
1735 | unset. */ | |
dcd709e0 | 1736 | |
e23eba97 NC |
1737 | static void |
1738 | normalize_constant_expr (expressionS *ex) | |
1739 | { | |
1740 | if (xlen > 32) | |
1741 | return; | |
1742 | if ((ex->X_op == O_constant || ex->X_op == O_symbol) | |
1743 | && IS_ZEXT_32BIT_NUM (ex->X_add_number)) | |
1744 | ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000) | |
1745 | - 0x80000000); | |
1746 | } | |
1747 | ||
ca2fd32c JW |
1748 | /* Fail if an expression EX is not a constant. IP is the instruction using EX. |
1749 | MAYBE_CSR is true if the symbol may be an unrecognized CSR name. */ | |
e23eba97 NC |
1750 | |
1751 | static void | |
ca2fd32c | 1752 | check_absolute_expr (struct riscv_cl_insn *ip, expressionS *ex, |
5b7c81bd | 1753 | bool maybe_csr) |
e23eba97 NC |
1754 | { |
1755 | if (ex->X_op == O_big) | |
1756 | as_bad (_("unsupported large constant")); | |
ca2fd32c JW |
1757 | else if (maybe_csr && ex->X_op == O_symbol) |
1758 | as_bad (_("unknown CSR `%s'"), | |
1759 | S_GET_NAME (ex->X_add_symbol)); | |
e23eba97 | 1760 | else if (ex->X_op != O_constant) |
b800637e | 1761 | as_bad (_("instruction %s requires absolute expression"), |
e23eba97 NC |
1762 | ip->insn_mo->name); |
1763 | normalize_constant_expr (ex); | |
1764 | } | |
1765 | ||
1766 | static symbolS * | |
1767 | make_internal_label (void) | |
1768 | { | |
e01e1cee AM |
1769 | return (symbolS *) local_symbol_make (FAKE_LABEL_NAME, now_seg, frag_now, |
1770 | frag_now_fix ()); | |
e23eba97 NC |
1771 | } |
1772 | ||
1773 | /* Load an entry from the GOT. */ | |
dcd709e0 | 1774 | |
e23eba97 NC |
1775 | static void |
1776 | pcrel_access (int destreg, int tempreg, expressionS *ep, | |
1777 | const char *lo_insn, const char *lo_pattern, | |
1778 | bfd_reloc_code_real_type hi_reloc, | |
1779 | bfd_reloc_code_real_type lo_reloc) | |
1780 | { | |
1781 | expressionS ep2; | |
1782 | ep2.X_op = O_symbol; | |
1783 | ep2.X_add_symbol = make_internal_label (); | |
1784 | ep2.X_add_number = 0; | |
1785 | ||
1786 | macro_build (ep, "auipc", "d,u", tempreg, hi_reloc); | |
1787 | macro_build (&ep2, lo_insn, lo_pattern, destreg, tempreg, lo_reloc); | |
1788 | } | |
1789 | ||
1790 | static void | |
1791 | pcrel_load (int destreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1792 | bfd_reloc_code_real_type hi_reloc, | |
1793 | bfd_reloc_code_real_type lo_reloc) | |
1794 | { | |
1795 | pcrel_access (destreg, tempreg, ep, lo_insn, "d,s,j", hi_reloc, lo_reloc); | |
1796 | } | |
1797 | ||
1798 | static void | |
1799 | pcrel_store (int srcreg, int tempreg, expressionS *ep, const char *lo_insn, | |
1800 | bfd_reloc_code_real_type hi_reloc, | |
1801 | bfd_reloc_code_real_type lo_reloc) | |
1802 | { | |
1803 | pcrel_access (srcreg, tempreg, ep, lo_insn, "t,s,q", hi_reloc, lo_reloc); | |
1804 | } | |
1805 | ||
1806 | /* PC-relative function call using AUIPC/JALR, relaxed to JAL. */ | |
dcd709e0 | 1807 | |
e23eba97 NC |
1808 | static void |
1809 | riscv_call (int destreg, int tempreg, expressionS *ep, | |
1810 | bfd_reloc_code_real_type reloc) | |
1811 | { | |
b1b11e92 AM |
1812 | /* Ensure the jalr is emitted to the same frag as the auipc. */ |
1813 | frag_grow (8); | |
e23eba97 NC |
1814 | macro_build (ep, "auipc", "d,u", tempreg, reloc); |
1815 | macro_build (NULL, "jalr", "d,s", destreg, tempreg); | |
b1b11e92 AM |
1816 | /* See comment at end of append_insn. */ |
1817 | frag_wane (frag_now); | |
1818 | frag_new (0); | |
e23eba97 NC |
1819 | } |
1820 | ||
1821 | /* Load an integer constant into a register. */ | |
1822 | ||
1823 | static void | |
1824 | load_const (int reg, expressionS *ep) | |
1825 | { | |
1826 | int shift = RISCV_IMM_BITS; | |
4f7cc141 | 1827 | bfd_vma upper_imm, sign = (bfd_vma) 1 << (RISCV_IMM_BITS - 1); |
e23eba97 | 1828 | expressionS upper = *ep, lower = *ep; |
4f7cc141 | 1829 | lower.X_add_number = ((ep->X_add_number & (sign + sign - 1)) ^ sign) - sign; |
e23eba97 NC |
1830 | upper.X_add_number -= lower.X_add_number; |
1831 | ||
1832 | if (ep->X_op != O_constant) | |
1833 | { | |
1834 | as_bad (_("unsupported large constant")); | |
1835 | return; | |
1836 | } | |
1837 | ||
1d65abb5 | 1838 | if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) |
e23eba97 NC |
1839 | { |
1840 | /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ | |
1841 | while (((upper.X_add_number >> shift) & 1) == 0) | |
1842 | shift++; | |
1843 | ||
1844 | upper.X_add_number = (int64_t) upper.X_add_number >> shift; | |
1d65abb5 | 1845 | load_const (reg, &upper); |
e23eba97 | 1846 | |
db3b6ecc | 1847 | md_assemblef ("slli x%d, x%d, 0x%x", reg, reg, shift); |
e23eba97 | 1848 | if (lower.X_add_number != 0) |
b8281767 AM |
1849 | md_assemblef ("addi x%d, x%d, %" PRId64, reg, reg, |
1850 | (int64_t) lower.X_add_number); | |
e23eba97 NC |
1851 | } |
1852 | else | |
1853 | { | |
1854 | /* Simply emit LUI and/or ADDI to build a 32-bit signed constant. */ | |
1855 | int hi_reg = 0; | |
1856 | ||
1857 | if (upper.X_add_number != 0) | |
1858 | { | |
db3b6ecc KC |
1859 | /* Discard low part and zero-extend upper immediate. */ |
1860 | upper_imm = ((uint32_t)upper.X_add_number >> shift); | |
1861 | ||
b8281767 | 1862 | md_assemblef ("lui x%d, 0x%" PRIx64, reg, (uint64_t) upper_imm); |
e23eba97 NC |
1863 | hi_reg = reg; |
1864 | } | |
1865 | ||
1866 | if (lower.X_add_number != 0 || hi_reg == 0) | |
b8281767 AM |
1867 | md_assemblef ("%s x%d, x%d, %" PRId64, ADD32_INSN, reg, hi_reg, |
1868 | (int64_t) lower.X_add_number); | |
e23eba97 NC |
1869 | } |
1870 | } | |
1871 | ||
c2137f55 NC |
1872 | /* Zero extend and sign extend byte/half-word/word. */ |
1873 | ||
1874 | static void | |
5b7c81bd | 1875 | riscv_ext (int destreg, int srcreg, unsigned shift, bool sign) |
c2137f55 NC |
1876 | { |
1877 | if (sign) | |
1878 | { | |
1879 | md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift); | |
1880 | md_assemblef ("srai x%d, x%d, 0x%x", destreg, destreg, shift); | |
1881 | } | |
1882 | else | |
1883 | { | |
1884 | md_assemblef ("slli x%d, x%d, 0x%x", destreg, srcreg, shift); | |
1885 | md_assemblef ("srli x%d, x%d, 0x%x", destreg, destreg, shift); | |
1886 | } | |
1887 | } | |
1888 | ||
65e4a99a NC |
1889 | /* Expand RISC-V Vector macros into one or more instructions. */ |
1890 | ||
1891 | static void | |
1892 | vector_macro (struct riscv_cl_insn *ip) | |
1893 | { | |
1894 | int vd = (ip->insn_opcode >> OP_SH_VD) & OP_MASK_VD; | |
1895 | int vs1 = (ip->insn_opcode >> OP_SH_VS1) & OP_MASK_VS1; | |
1896 | int vs2 = (ip->insn_opcode >> OP_SH_VS2) & OP_MASK_VS2; | |
1897 | int vm = (ip->insn_opcode >> OP_SH_VMASK) & OP_MASK_VMASK; | |
1898 | int vtemp = (ip->insn_opcode >> OP_SH_VFUNCT6) & OP_MASK_VFUNCT6; | |
1899 | int mask = ip->insn_mo->mask; | |
1900 | ||
1901 | switch (mask) | |
1902 | { | |
1903 | case M_VMSGE: | |
1904 | if (vm) | |
1905 | { | |
1906 | /* Unmasked. */ | |
1907 | macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1); | |
1908 | macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd); | |
1909 | break; | |
1910 | } | |
1911 | if (vtemp != 0) | |
1912 | { | |
1913 | /* Masked. Have vtemp to avoid overlap constraints. */ | |
1914 | if (vd == vm) | |
1915 | { | |
1916 | macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); | |
1917 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); | |
1918 | } | |
1919 | else | |
1920 | { | |
1921 | /* Preserve the value of vd if not updating by vm. */ | |
1922 | macro_build (NULL, "vmslt.vx", "Vd,Vt,s", vtemp, vs2, vs1); | |
1923 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); | |
1924 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); | |
1925 | macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); | |
1926 | } | |
1927 | } | |
1928 | else if (vd != vm) | |
1929 | { | |
1930 | /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */ | |
1931 | macro_build (NULL, "vmslt.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm); | |
1932 | macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm); | |
1933 | } | |
1934 | else | |
1935 | as_bad (_("must provide temp if destination overlaps mask")); | |
1936 | break; | |
1937 | ||
1938 | case M_VMSGEU: | |
1939 | if (vm) | |
1940 | { | |
1941 | /* Unmasked. */ | |
1942 | macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, -1); | |
1943 | macro_build (NULL, "vmnand.mm", "Vd,Vt,Vs", vd, vd, vd); | |
1944 | break; | |
1945 | } | |
1946 | if (vtemp != 0) | |
1947 | { | |
1948 | /* Masked. Have vtemp to avoid overlap constraints. */ | |
1949 | if (vd == vm) | |
1950 | { | |
1951 | macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); | |
1952 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vm, vtemp); | |
1953 | } | |
1954 | else | |
1955 | { | |
1956 | /* Preserve the value of vd if not updating by vm. */ | |
1957 | macro_build (NULL, "vmsltu.vx", "Vd,Vt,s", vtemp, vs2, vs1); | |
1958 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vtemp, vm, vtemp); | |
1959 | macro_build (NULL, "vmandnot.mm", "Vd,Vt,Vs", vd, vd, vm); | |
1960 | macro_build (NULL, "vmor.mm", "Vd,Vt,Vs", vd, vtemp, vd); | |
1961 | } | |
1962 | } | |
1963 | else if (vd != vm) | |
1964 | { | |
1965 | /* Masked. This may cause the vd overlaps vs2, when LMUL > 1. */ | |
1966 | macro_build (NULL, "vmsltu.vx", "Vd,Vt,sVm", vd, vs2, vs1, vm); | |
1967 | macro_build (NULL, "vmxor.mm", "Vd,Vt,Vs", vd, vd, vm); | |
1968 | } | |
1969 | else | |
1970 | as_bad (_("must provide temp if destination overlaps mask")); | |
1971 | break; | |
1972 | ||
1973 | default: | |
1974 | break; | |
1975 | } | |
1976 | } | |
1977 | ||
e23eba97 | 1978 | /* Expand RISC-V assembly macros into one or more instructions. */ |
2652cfad | 1979 | |
e23eba97 NC |
1980 | static void |
1981 | macro (struct riscv_cl_insn *ip, expressionS *imm_expr, | |
1982 | bfd_reloc_code_real_type *imm_reloc) | |
1983 | { | |
1984 | int rd = (ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD; | |
1985 | int rs1 = (ip->insn_opcode >> OP_SH_RS1) & OP_MASK_RS1; | |
1986 | int rs2 = (ip->insn_opcode >> OP_SH_RS2) & OP_MASK_RS2; | |
1987 | int mask = ip->insn_mo->mask; | |
1988 | ||
1989 | switch (mask) | |
1990 | { | |
1991 | case M_LI: | |
1992 | load_const (rd, imm_expr); | |
1993 | break; | |
1994 | ||
1995 | case M_LA: | |
1996 | case M_LLA: | |
1997 | /* Load the address of a symbol into a register. */ | |
1998 | if (!IS_SEXT_32BIT_NUM (imm_expr->X_add_number)) | |
1999 | as_bad (_("offset too large")); | |
2000 | ||
2001 | if (imm_expr->X_op == O_constant) | |
2002 | load_const (rd, imm_expr); | |
dcd709e0 | 2003 | else if (riscv_opts.pic && mask == M_LA) /* Global PIC symbol. */ |
e23eba97 NC |
2004 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, |
2005 | BFD_RELOC_RISCV_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
dcd709e0 | 2006 | else /* Local PIC symbol, or any non-PIC symbol. */ |
e23eba97 NC |
2007 | pcrel_load (rd, rd, imm_expr, "addi", |
2008 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2009 | break; | |
2010 | ||
2011 | case M_LA_TLS_GD: | |
2012 | pcrel_load (rd, rd, imm_expr, "addi", | |
2013 | BFD_RELOC_RISCV_TLS_GD_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2014 | break; | |
2015 | ||
2016 | case M_LA_TLS_IE: | |
2017 | pcrel_load (rd, rd, imm_expr, LOAD_ADDRESS_INSN, | |
2018 | BFD_RELOC_RISCV_TLS_GOT_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2019 | break; | |
2020 | ||
2021 | case M_LB: | |
2022 | pcrel_load (rd, rd, imm_expr, "lb", | |
2023 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2024 | break; | |
2025 | ||
2026 | case M_LBU: | |
2027 | pcrel_load (rd, rd, imm_expr, "lbu", | |
2028 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2029 | break; | |
2030 | ||
2031 | case M_LH: | |
2032 | pcrel_load (rd, rd, imm_expr, "lh", | |
2033 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2034 | break; | |
2035 | ||
2036 | case M_LHU: | |
2037 | pcrel_load (rd, rd, imm_expr, "lhu", | |
2038 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2039 | break; | |
2040 | ||
2041 | case M_LW: | |
2042 | pcrel_load (rd, rd, imm_expr, "lw", | |
2043 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2044 | break; | |
2045 | ||
2046 | case M_LWU: | |
2047 | pcrel_load (rd, rd, imm_expr, "lwu", | |
2048 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2049 | break; | |
2050 | ||
2051 | case M_LD: | |
2052 | pcrel_load (rd, rd, imm_expr, "ld", | |
2053 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2054 | break; | |
2055 | ||
2056 | case M_FLW: | |
2057 | pcrel_load (rd, rs1, imm_expr, "flw", | |
2058 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2059 | break; | |
2060 | ||
2061 | case M_FLD: | |
2062 | pcrel_load (rd, rs1, imm_expr, "fld", | |
2063 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2064 | break; | |
2065 | ||
2066 | case M_SB: | |
2067 | pcrel_store (rs2, rs1, imm_expr, "sb", | |
2068 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2069 | break; | |
2070 | ||
2071 | case M_SH: | |
2072 | pcrel_store (rs2, rs1, imm_expr, "sh", | |
2073 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2074 | break; | |
2075 | ||
2076 | case M_SW: | |
2077 | pcrel_store (rs2, rs1, imm_expr, "sw", | |
2078 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2079 | break; | |
2080 | ||
2081 | case M_SD: | |
2082 | pcrel_store (rs2, rs1, imm_expr, "sd", | |
2083 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2084 | break; | |
2085 | ||
2086 | case M_FSW: | |
2087 | pcrel_store (rs2, rs1, imm_expr, "fsw", | |
2088 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2089 | break; | |
2090 | ||
2091 | case M_FSD: | |
2092 | pcrel_store (rs2, rs1, imm_expr, "fsd", | |
2093 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2094 | break; | |
2095 | ||
2096 | case M_CALL: | |
2097 | riscv_call (rd, rs1, imm_expr, *imm_reloc); | |
2098 | break; | |
2099 | ||
c2137f55 | 2100 | case M_ZEXTH: |
5b7c81bd | 2101 | riscv_ext (rd, rs1, xlen - 16, false); |
c2137f55 NC |
2102 | break; |
2103 | ||
2104 | case M_ZEXTW: | |
5b7c81bd | 2105 | riscv_ext (rd, rs1, xlen - 32, false); |
c2137f55 NC |
2106 | break; |
2107 | ||
2108 | case M_SEXTB: | |
5b7c81bd | 2109 | riscv_ext (rd, rs1, xlen - 8, true); |
c2137f55 NC |
2110 | break; |
2111 | ||
2112 | case M_SEXTH: | |
5b7c81bd | 2113 | riscv_ext (rd, rs1, xlen - 16, true); |
c2137f55 NC |
2114 | break; |
2115 | ||
65e4a99a NC |
2116 | case M_VMSGE: |
2117 | case M_VMSGEU: | |
2118 | vector_macro (ip); | |
2119 | break; | |
2120 | ||
035784e3 NC |
2121 | case M_FLH: |
2122 | pcrel_load (rd, rs1, imm_expr, "flh", | |
2123 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_I); | |
2124 | break; | |
2125 | case M_FSH: | |
2126 | pcrel_store (rs2, rs1, imm_expr, "fsh", | |
2127 | BFD_RELOC_RISCV_PCREL_HI20, BFD_RELOC_RISCV_PCREL_LO12_S); | |
2128 | break; | |
2129 | ||
e23eba97 | 2130 | default: |
b800637e | 2131 | as_bad (_("internal: macro %s not implemented"), ip->insn_mo->name); |
e23eba97 NC |
2132 | break; |
2133 | } | |
2134 | } | |
2135 | ||
2136 | static const struct percent_op_match percent_op_utype[] = | |
2137 | { | |
2138 | {"%tprel_hi", BFD_RELOC_RISCV_TPREL_HI20}, | |
2139 | {"%pcrel_hi", BFD_RELOC_RISCV_PCREL_HI20}, | |
dee35d02 | 2140 | {"%got_pcrel_hi", BFD_RELOC_RISCV_GOT_HI20}, |
e23eba97 NC |
2141 | {"%tls_ie_pcrel_hi", BFD_RELOC_RISCV_TLS_GOT_HI20}, |
2142 | {"%tls_gd_pcrel_hi", BFD_RELOC_RISCV_TLS_GD_HI20}, | |
2143 | {"%hi", BFD_RELOC_RISCV_HI20}, | |
2144 | {0, 0} | |
2145 | }; | |
2146 | ||
2147 | static const struct percent_op_match percent_op_itype[] = | |
2148 | { | |
2149 | {"%lo", BFD_RELOC_RISCV_LO12_I}, | |
2150 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_I}, | |
2151 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_I}, | |
2152 | {0, 0} | |
2153 | }; | |
2154 | ||
2155 | static const struct percent_op_match percent_op_stype[] = | |
2156 | { | |
2157 | {"%lo", BFD_RELOC_RISCV_LO12_S}, | |
2158 | {"%tprel_lo", BFD_RELOC_RISCV_TPREL_LO12_S}, | |
2159 | {"%pcrel_lo", BFD_RELOC_RISCV_PCREL_LO12_S}, | |
2160 | {0, 0} | |
2161 | }; | |
2162 | ||
2163 | static const struct percent_op_match percent_op_rtype[] = | |
2164 | { | |
2165 | {"%tprel_add", BFD_RELOC_RISCV_TPREL_ADD}, | |
2166 | {0, 0} | |
2167 | }; | |
2168 | ||
f50fabe4 JW |
2169 | static const struct percent_op_match percent_op_null[] = |
2170 | { | |
2171 | {0, 0} | |
2172 | }; | |
2173 | ||
e23eba97 NC |
2174 | /* Return true if *STR points to a relocation operator. When returning true, |
2175 | move *STR over the operator and store its relocation code in *RELOC. | |
2176 | Leave both *STR and *RELOC alone when returning false. */ | |
2177 | ||
5b7c81bd | 2178 | static bool |
e23eba97 NC |
2179 | parse_relocation (char **str, bfd_reloc_code_real_type *reloc, |
2180 | const struct percent_op_match *percent_op) | |
2181 | { | |
2182 | for ( ; percent_op->str; percent_op++) | |
2183 | if (strncasecmp (*str, percent_op->str, strlen (percent_op->str)) == 0) | |
2184 | { | |
2185 | int len = strlen (percent_op->str); | |
2186 | ||
2187 | if (!ISSPACE ((*str)[len]) && (*str)[len] != '(') | |
2188 | continue; | |
2189 | ||
2190 | *str += strlen (percent_op->str); | |
2191 | *reloc = percent_op->reloc; | |
2192 | ||
2193 | /* Check whether the output BFD supports this relocation. | |
2194 | If not, issue an error and fall back on something safe. */ | |
45f76423 AW |
2195 | if (*reloc != BFD_RELOC_UNUSED |
2196 | && !bfd_reloc_type_lookup (stdoutput, *reloc)) | |
e23eba97 | 2197 | { |
b800637e NC |
2198 | as_bad ("internal: relocation %s isn't supported by the " |
2199 | "current ABI", percent_op->str); | |
e23eba97 NC |
2200 | *reloc = BFD_RELOC_UNUSED; |
2201 | } | |
5b7c81bd | 2202 | return true; |
e23eba97 | 2203 | } |
5b7c81bd | 2204 | return false; |
e23eba97 NC |
2205 | } |
2206 | ||
2207 | static void | |
2208 | my_getExpression (expressionS *ep, char *str) | |
2209 | { | |
2210 | char *save_in; | |
2211 | ||
2212 | save_in = input_line_pointer; | |
2213 | input_line_pointer = str; | |
2214 | expression (ep); | |
6eb099ae | 2215 | expr_parse_end = input_line_pointer; |
e23eba97 NC |
2216 | input_line_pointer = save_in; |
2217 | } | |
2218 | ||
2219 | /* Parse string STR as a 16-bit relocatable operand. Store the | |
2220 | expression in *EP and the relocation, if any, in RELOC. | |
2221 | Return the number of relocation operators used (0 or 1). | |
2222 | ||
6eb099ae AM |
2223 | On exit, EXPR_PARSE_END points to the first character after the |
2224 | expression. */ | |
e23eba97 NC |
2225 | |
2226 | static size_t | |
2227 | my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
2228 | char *str, const struct percent_op_match *percent_op) | |
2229 | { | |
2230 | size_t reloc_index; | |
2231 | unsigned crux_depth, str_depth, regno; | |
2232 | char *crux; | |
2233 | ||
8970c022 JW |
2234 | /* First, check for integer registers. No callers can accept a reg, but |
2235 | we need to avoid accidentally creating a useless undefined symbol below, | |
2236 | if this is an instruction pattern that can't match. A glibc build fails | |
2237 | if this is removed. */ | |
e23eba97 NC |
2238 | if (reg_lookup (&str, RCLASS_GPR, ®no)) |
2239 | { | |
2240 | ep->X_op = O_register; | |
2241 | ep->X_add_number = regno; | |
6eb099ae | 2242 | expr_parse_end = str; |
e23eba97 NC |
2243 | return 0; |
2244 | } | |
2245 | ||
2246 | /* Search for the start of the main expression. | |
dcd709e0 NC |
2247 | |
2248 | End the loop with CRUX pointing to the start of the main expression and | |
2249 | with CRUX_DEPTH containing the number of open brackets at that point. */ | |
e23eba97 NC |
2250 | reloc_index = -1; |
2251 | str_depth = 0; | |
2252 | do | |
2253 | { | |
2254 | reloc_index++; | |
2255 | crux = str; | |
2256 | crux_depth = str_depth; | |
2257 | ||
2258 | /* Skip over whitespace and brackets, keeping count of the number | |
2259 | of brackets. */ | |
2260 | while (*str == ' ' || *str == '\t' || *str == '(') | |
2261 | if (*str++ == '(') | |
2262 | str_depth++; | |
2263 | } | |
2264 | while (*str == '%' | |
2265 | && reloc_index < 1 | |
2266 | && parse_relocation (&str, reloc, percent_op)); | |
2267 | ||
2268 | my_getExpression (ep, crux); | |
6eb099ae | 2269 | str = expr_parse_end; |
e23eba97 NC |
2270 | |
2271 | /* Match every open bracket. */ | |
2272 | while (crux_depth > 0 && (*str == ')' || *str == ' ' || *str == '\t')) | |
2273 | if (*str++ == ')') | |
2274 | crux_depth--; | |
2275 | ||
2276 | if (crux_depth > 0) | |
2277 | as_bad ("unclosed '('"); | |
2278 | ||
6eb099ae | 2279 | expr_parse_end = str; |
e23eba97 NC |
2280 | |
2281 | return reloc_index; | |
2282 | } | |
2283 | ||
0e35537d | 2284 | /* Parse opcode name, could be an mnemonics or number. */ |
dcd709e0 | 2285 | |
0e35537d JW |
2286 | static size_t |
2287 | my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc, | |
2288 | char *str, const struct percent_op_match *percent_op) | |
2289 | { | |
2290 | const struct opcode_name_t *o = opcode_name_lookup (&str); | |
2291 | ||
2292 | if (o != NULL) | |
2293 | { | |
2294 | ep->X_op = O_constant; | |
2295 | ep->X_add_number = o->val; | |
2296 | return 0; | |
2297 | } | |
2298 | ||
2299 | return my_getSmallExpression (ep, reloc, str, percent_op); | |
2300 | } | |
2301 | ||
65e4a99a | 2302 | /* Parse string STR as a vsetvli operand. Store the expression in *EP. |
6eb099ae AM |
2303 | On exit, EXPR_PARSE_END points to the first character after the |
2304 | expression. */ | |
65e4a99a NC |
2305 | |
2306 | static void | |
2307 | my_getVsetvliExpression (expressionS *ep, char *str) | |
2308 | { | |
2309 | unsigned int vsew_value = 0, vlmul_value = 0; | |
2310 | unsigned int vta_value = 0, vma_value = 0; | |
2311 | bfd_boolean vsew_found = FALSE, vlmul_found = FALSE; | |
2312 | bfd_boolean vta_found = FALSE, vma_found = FALSE; | |
2313 | ||
2314 | if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value)) | |
2315 | { | |
2316 | if (*str == ',') | |
2317 | ++str; | |
2318 | if (vsew_found) | |
2319 | as_bad (_("multiple vsew constants")); | |
2320 | vsew_found = TRUE; | |
2321 | } | |
2322 | if (arg_lookup (&str, riscv_vlmul, ARRAY_SIZE (riscv_vlmul), &vlmul_value)) | |
2323 | { | |
2324 | if (*str == ',') | |
2325 | ++str; | |
2326 | if (vlmul_found) | |
2327 | as_bad (_("multiple vlmul constants")); | |
2328 | vlmul_found = TRUE; | |
2329 | } | |
2330 | if (arg_lookup (&str, riscv_vta, ARRAY_SIZE (riscv_vta), &vta_value)) | |
2331 | { | |
2332 | if (*str == ',') | |
2333 | ++str; | |
2334 | if (vta_found) | |
2335 | as_bad (_("multiple vta constants")); | |
2336 | vta_found = TRUE; | |
2337 | } | |
2338 | if (arg_lookup (&str, riscv_vma, ARRAY_SIZE (riscv_vma), &vma_value)) | |
2339 | { | |
2340 | if (*str == ',') | |
2341 | ++str; | |
2342 | if (vma_found) | |
2343 | as_bad (_("multiple vma constants")); | |
2344 | vma_found = TRUE; | |
2345 | } | |
2346 | ||
2347 | if (vsew_found || vlmul_found || vta_found || vma_found) | |
2348 | { | |
2349 | ep->X_op = O_constant; | |
2350 | ep->X_add_number = (vlmul_value << OP_SH_VLMUL) | |
2351 | | (vsew_value << OP_SH_VSEW) | |
2352 | | (vta_value << OP_SH_VTA) | |
2353 | | (vma_value << OP_SH_VMA); | |
6eb099ae | 2354 | expr_parse_end = str; |
65e4a99a NC |
2355 | } |
2356 | else | |
2357 | { | |
2358 | my_getExpression (ep, str); | |
6eb099ae | 2359 | str = expr_parse_end; |
65e4a99a NC |
2360 | } |
2361 | } | |
2362 | ||
f0531ed6 | 2363 | /* Detect and handle implicitly zero load-store offsets. For example, |
437e2ff1 | 2364 | "lw t0, (t1)" is shorthand for "lw t0, 0(t1)". Return true if such |
f0531ed6 JW |
2365 | an implicit offset was detected. */ |
2366 | ||
5b7c81bd | 2367 | static bool |
89424b1d | 2368 | riscv_handle_implicit_zero_offset (expressionS *ep, const char *s) |
f0531ed6 JW |
2369 | { |
2370 | /* Check whether there is only a single bracketed expression left. | |
2371 | If so, it must be the base register and the constant must be zero. */ | |
2372 | if (*s == '(' && strchr (s + 1, '(') == 0) | |
2373 | { | |
89424b1d MR |
2374 | ep->X_op = O_constant; |
2375 | ep->X_add_number = 0; | |
5b7c81bd | 2376 | return true; |
f0531ed6 JW |
2377 | } |
2378 | ||
5b7c81bd | 2379 | return false; |
f0531ed6 JW |
2380 | } |
2381 | ||
54b2aec1 | 2382 | /* All RISC-V CSR instructions belong to one of these classes. */ |
54b2aec1 NC |
2383 | enum csr_insn_type |
2384 | { | |
2385 | INSN_NOT_CSR, | |
2386 | INSN_CSRRW, | |
2387 | INSN_CSRRS, | |
2388 | INSN_CSRRC | |
2389 | }; | |
2390 | ||
2391 | /* Return which CSR instruction is checking. */ | |
2392 | ||
2393 | static enum csr_insn_type | |
2394 | riscv_csr_insn_type (insn_t insn) | |
2395 | { | |
2396 | if (((insn ^ MATCH_CSRRW) & MASK_CSRRW) == 0 | |
2397 | || ((insn ^ MATCH_CSRRWI) & MASK_CSRRWI) == 0) | |
2398 | return INSN_CSRRW; | |
2399 | else if (((insn ^ MATCH_CSRRS) & MASK_CSRRS) == 0 | |
2400 | || ((insn ^ MATCH_CSRRSI) & MASK_CSRRSI) == 0) | |
2401 | return INSN_CSRRS; | |
2402 | else if (((insn ^ MATCH_CSRRC) & MASK_CSRRC) == 0 | |
2403 | || ((insn ^ MATCH_CSRRCI) & MASK_CSRRCI) == 0) | |
2404 | return INSN_CSRRC; | |
2405 | else | |
2406 | return INSN_NOT_CSR; | |
2407 | } | |
2408 | ||
2409 | /* CSRRW and CSRRWI always write CSR. CSRRS, CSRRC, CSRRSI and CSRRCI write | |
2410 | CSR when RS1 isn't zero. The CSR is read only if the [11:10] bits of | |
2411 | CSR address is 0x3. */ | |
2412 | ||
5b7c81bd | 2413 | static bool |
54b2aec1 NC |
2414 | riscv_csr_read_only_check (insn_t insn) |
2415 | { | |
2416 | int csr = (insn & (OP_MASK_CSR << OP_SH_CSR)) >> OP_SH_CSR; | |
2417 | int rs1 = (insn & (OP_MASK_RS1 << OP_SH_RS1)) >> OP_SH_RS1; | |
2418 | int readonly = (((csr & (0x3 << 10)) >> 10) == 0x3); | |
2419 | enum csr_insn_type csr_insn = riscv_csr_insn_type (insn); | |
2420 | ||
2421 | if (readonly | |
2422 | && (((csr_insn == INSN_CSRRS | |
2423 | || csr_insn == INSN_CSRRC) | |
2424 | && rs1 != 0) | |
2425 | || csr_insn == INSN_CSRRW)) | |
5b7c81bd | 2426 | return false; |
54b2aec1 | 2427 | |
5b7c81bd | 2428 | return true; |
54b2aec1 NC |
2429 | } |
2430 | ||
437e2ff1 | 2431 | /* Return true if it is a privileged instruction. Otherwise, return false. |
1a79004f NC |
2432 | |
2433 | uret is actually a N-ext instruction. So it is better to regard it as | |
2434 | an user instruction rather than the priv instruction. | |
2435 | ||
2436 | hret is used to return from traps in H-mode. H-mode is removed since | |
2437 | the v1.10 priv spec, but probably be added in the new hypervisor spec. | |
2438 | Therefore, hret should be controlled by the hypervisor spec rather than | |
2439 | priv spec in the future. | |
2440 | ||
2441 | dret is defined in the debug spec, so it should be checked in the future, | |
2442 | too. */ | |
2443 | ||
5b7c81bd | 2444 | static bool |
1a79004f NC |
2445 | riscv_is_priv_insn (insn_t insn) |
2446 | { | |
2447 | return (((insn ^ MATCH_SRET) & MASK_SRET) == 0 | |
2448 | || ((insn ^ MATCH_MRET) & MASK_MRET) == 0 | |
2449 | || ((insn ^ MATCH_SFENCE_VMA) & MASK_SFENCE_VMA) == 0 | |
2450 | || ((insn ^ MATCH_WFI) & MASK_WFI) == 0 | |
2451 | /* The sfence.vm is dropped in the v1.10 priv specs, but we still need to | |
dcd709e0 | 2452 | check it here to keep the compatible. */ |
1a79004f NC |
2453 | || ((insn ^ MATCH_SFENCE_VM) & MASK_SFENCE_VM) == 0); |
2454 | } | |
2455 | ||
e23eba97 NC |
2456 | /* This routine assembles an instruction into its binary format. As a |
2457 | side effect, it sets the global variable imm_reloc to the type of | |
2458 | relocation to do if one of the operands is an address expression. */ | |
2459 | ||
e4028336 | 2460 | static struct riscv_ip_error |
e23eba97 | 2461 | riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, |
629310ab | 2462 | bfd_reloc_code_real_type *imm_reloc, htab_t hash) |
e23eba97 | 2463 | { |
437e2ff1 NC |
2464 | /* The operand string defined in the riscv_opcodes. */ |
2465 | const char *oparg, *opargStart; | |
2466 | /* The parsed operands from assembly. */ | |
2467 | char *asarg, *asargStart; | |
2468 | char save_c = 0; | |
e23eba97 | 2469 | struct riscv_opcode *insn; |
e23eba97 | 2470 | unsigned int regno; |
e23eba97 | 2471 | const struct percent_op_match *p; |
e4028336 PN |
2472 | struct riscv_ip_error error; |
2473 | error.msg = "unrecognized opcode"; | |
2474 | error.statement = str; | |
2475 | error.missing_ext = NULL; | |
54b2aec1 | 2476 | /* Indicate we are assembling instruction with CSR. */ |
5b7c81bd | 2477 | bool insn_with_csr = false; |
e23eba97 NC |
2478 | |
2479 | /* Parse the name of the instruction. Terminate the string if whitespace | |
629310ab | 2480 | is found so that str_hash_find only sees the name part of the string. */ |
437e2ff1 NC |
2481 | for (asarg = str; *asarg!= '\0'; ++asarg) |
2482 | if (ISSPACE (*asarg)) | |
e23eba97 | 2483 | { |
437e2ff1 NC |
2484 | save_c = *asarg; |
2485 | *asarg++ = '\0'; | |
e23eba97 NC |
2486 | break; |
2487 | } | |
2488 | ||
629310ab | 2489 | insn = (struct riscv_opcode *) str_hash_find (hash, str); |
e23eba97 | 2490 | |
437e2ff1 | 2491 | asargStart = asarg; |
e23eba97 NC |
2492 | for ( ; insn && insn->name && strcmp (insn->name, str) == 0; insn++) |
2493 | { | |
1080bf78 JW |
2494 | if ((insn->xlen_requirement != 0) && (xlen != insn->xlen_requirement)) |
2495 | continue; | |
2496 | ||
f786c359 | 2497 | if (!riscv_multi_subset_supports (&riscv_rps_as, insn->insn_class)) |
e4028336 PN |
2498 | { |
2499 | error.missing_ext = riscv_multi_subset_supports_ext (&riscv_rps_as, | |
2500 | insn->insn_class); | |
2501 | continue; | |
2502 | } | |
e23eba97 | 2503 | |
65e4a99a | 2504 | /* Reset error message of the previous round. */ |
e4028336 PN |
2505 | error.msg = _("illegal operands"); |
2506 | error.missing_ext = NULL; | |
e23eba97 | 2507 | create_insn (ip, insn); |
e23eba97 NC |
2508 | |
2509 | imm_expr->X_op = O_absent; | |
2510 | *imm_reloc = BFD_RELOC_UNUSED; | |
2511 | p = percent_op_itype; | |
2512 | ||
437e2ff1 | 2513 | for (oparg = insn->args;; ++oparg) |
e23eba97 | 2514 | { |
437e2ff1 NC |
2515 | opargStart = oparg; |
2516 | asarg += strspn (asarg, " \t"); | |
2517 | switch (*oparg) | |
e23eba97 | 2518 | { |
dcd709e0 | 2519 | case '\0': /* End of args. */ |
e23eba97 NC |
2520 | if (insn->pinfo != INSN_MACRO) |
2521 | { | |
2522 | if (!insn->match_func (insn, ip->insn_opcode)) | |
2523 | break; | |
0e35537d JW |
2524 | |
2525 | /* For .insn, insn->match and insn->mask are 0. */ | |
2526 | if (riscv_insn_length ((insn->match == 0 && insn->mask == 0) | |
2527 | ? ip->insn_opcode | |
2528 | : insn->match) == 2 | |
2529 | && !riscv_opts.rvc) | |
e23eba97 | 2530 | break; |
54b2aec1 | 2531 | |
1a79004f | 2532 | if (riscv_is_priv_insn (ip->insn_opcode)) |
5b7c81bd | 2533 | explicit_priv_attr = true; |
1a79004f | 2534 | |
54b2aec1 NC |
2535 | /* Check if we write a read-only CSR by the CSR |
2536 | instruction. */ | |
2537 | if (insn_with_csr | |
2538 | && riscv_opts.csr_check | |
2539 | && !riscv_csr_read_only_check (ip->insn_opcode)) | |
2540 | { | |
2541 | /* Restore the character in advance, since we want to | |
2542 | report the detailed warning message here. */ | |
2543 | if (save_c) | |
437e2ff1 | 2544 | *(asargStart - 1) = save_c; |
b800637e | 2545 | as_warn (_("read-only CSR is written `%s'"), str); |
5b7c81bd | 2546 | insn_with_csr = false; |
54b2aec1 | 2547 | } |
65e4a99a NC |
2548 | |
2549 | /* The (segmant) load and store with EEW 64 cannot be used | |
2550 | when zve32x is enabled. */ | |
2551 | if (ip->insn_mo->pinfo & INSN_V_EEW64 | |
2552 | && riscv_subset_supports (&riscv_rps_as, "zve32x") | |
2553 | && !riscv_subset_supports (&riscv_rps_as, "zve64x")) | |
2554 | { | |
e4028336 | 2555 | error.msg = _("illegal opcode for zve32x"); |
65e4a99a NC |
2556 | break; |
2557 | } | |
e23eba97 | 2558 | } |
437e2ff1 | 2559 | if (*asarg != '\0') |
e23eba97 NC |
2560 | break; |
2561 | /* Successful assembly. */ | |
e4028336 | 2562 | error.msg = NULL; |
5b7c81bd | 2563 | insn_with_csr = false; |
e23eba97 NC |
2564 | goto out; |
2565 | ||
2566 | case 'C': /* RVC */ | |
437e2ff1 | 2567 | switch (*++oparg) |
e23eba97 | 2568 | { |
dcd709e0 | 2569 | case 's': /* RS1 x8-x15. */ |
437e2ff1 | 2570 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2571 | || !(regno >= 8 && regno <= 15)) |
2572 | break; | |
2573 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
2574 | continue; | |
2575 | case 'w': /* RS1 x8-x15, constrained to equal RD x8-x15. */ | |
437e2ff1 | 2576 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2577 | || EXTRACT_OPERAND (CRS1S, ip->insn_opcode) + 8 != regno) |
2578 | break; | |
2579 | continue; | |
dcd709e0 | 2580 | case 't': /* RS2 x8-x15. */ |
437e2ff1 | 2581 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2582 | || !(regno >= 8 && regno <= 15)) |
2583 | break; | |
2584 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
2585 | continue; | |
2586 | case 'x': /* RS2 x8-x15, constrained to equal RD x8-x15. */ | |
437e2ff1 | 2587 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2588 | || EXTRACT_OPERAND (CRS2S, ip->insn_opcode) + 8 != regno) |
2589 | break; | |
2590 | continue; | |
2591 | case 'U': /* RS1, constrained to equal RD. */ | |
437e2ff1 | 2592 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2593 | || EXTRACT_OPERAND (RD, ip->insn_opcode) != regno) |
2594 | break; | |
2595 | continue; | |
2596 | case 'V': /* RS2 */ | |
437e2ff1 | 2597 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no)) |
e23eba97 NC |
2598 | break; |
2599 | INSERT_OPERAND (CRS2, *ip, regno); | |
2600 | continue; | |
2601 | case 'c': /* RS1, constrained to equal sp. */ | |
437e2ff1 | 2602 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
e23eba97 NC |
2603 | || regno != X_SP) |
2604 | break; | |
2605 | continue; | |
dcd709e0 | 2606 | case 'z': /* RS2, constrained to equal x0. */ |
437e2ff1 | 2607 | if (!reg_lookup (&asarg, RCLASS_GPR, ®no) |
ca0bc150 JW |
2608 | || regno != 0) |
2609 | break; | |
2610 | continue; | |
768589d1 | 2611 | case '>': /* Shift amount, 0 - (XLEN-1). */ |
437e2ff1 | 2612 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2613 | || imm_expr->X_op != O_constant |
768589d1 | 2614 | || (unsigned long) imm_expr->X_add_number >= xlen) |
e23eba97 | 2615 | break; |
5a9f5403 | 2616 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
dc1e8a47 | 2617 | rvc_imm_done: |
6eb099ae | 2618 | asarg = expr_parse_end; |
e23eba97 NC |
2619 | imm_expr->X_op = O_absent; |
2620 | continue; | |
5a9f5403 | 2621 | case '5': |
437e2ff1 | 2622 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2623 | || imm_expr->X_op != O_constant |
5a9f5403 | 2624 | || imm_expr->X_add_number < 0 |
169ec512 | 2625 | || imm_expr->X_add_number >= 32 |
5a9f5403 | 2626 | || !VALID_CLTYPE_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2627 | break; |
0257c2ff | 2628 | ip->insn_opcode |= ENCODE_CLTYPE_IMM (imm_expr->X_add_number); |
e23eba97 | 2629 | goto rvc_imm_done; |
5a9f5403 | 2630 | case '6': |
437e2ff1 | 2631 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d | 2632 | || imm_expr->X_op != O_constant |
0e35537d | 2633 | || imm_expr->X_add_number < 0 |
5a9f5403 NC |
2634 | || imm_expr->X_add_number >= 64 |
2635 | || !VALID_CSSTYPE_IMM ((valueT) imm_expr->X_add_number)) | |
0e35537d | 2636 | break; |
0257c2ff | 2637 | ip->insn_opcode |= ENCODE_CSSTYPE_IMM (imm_expr->X_add_number); |
0e35537d | 2638 | goto rvc_imm_done; |
5a9f5403 | 2639 | case '8': |
437e2ff1 | 2640 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2641 | || imm_expr->X_op != O_constant |
5a9f5403 NC |
2642 | || imm_expr->X_add_number < 0 |
2643 | || imm_expr->X_add_number >= 256 | |
2644 | || !VALID_CIWTYPE_IMM ((valueT) imm_expr->X_add_number)) | |
e23eba97 | 2645 | break; |
0257c2ff | 2646 | ip->insn_opcode |= ENCODE_CIWTYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2647 | goto rvc_imm_done; |
2648 | case 'j': | |
437e2ff1 | 2649 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 NC |
2650 | || imm_expr->X_op != O_constant |
2651 | || imm_expr->X_add_number == 0 | |
5a9f5403 | 2652 | || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2653 | break; |
5a9f5403 | 2654 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2655 | goto rvc_imm_done; |
2656 | case 'k': | |
437e2ff1 | 2657 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2658 | continue; |
437e2ff1 | 2659 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2660 | || imm_expr->X_op != O_constant |
5a9f5403 | 2661 | || !VALID_CLTYPE_LW_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2662 | break; |
5a9f5403 | 2663 | ip->insn_opcode |= ENCODE_CLTYPE_LW_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2664 | goto rvc_imm_done; |
2665 | case 'l': | |
437e2ff1 | 2666 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2667 | continue; |
437e2ff1 | 2668 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2669 | || imm_expr->X_op != O_constant |
5a9f5403 | 2670 | || !VALID_CLTYPE_LD_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 | 2671 | break; |
5a9f5403 | 2672 | ip->insn_opcode |= ENCODE_CLTYPE_LD_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2673 | goto rvc_imm_done; |
2674 | case 'm': | |
437e2ff1 | 2675 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2676 | continue; |
437e2ff1 | 2677 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2678 | || imm_expr->X_op != O_constant |
5a9f5403 | 2679 | || !VALID_CITYPE_LWSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2680 | break; |
2681 | ip->insn_opcode |= | |
5a9f5403 | 2682 | ENCODE_CITYPE_LWSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2683 | goto rvc_imm_done; |
2684 | case 'n': | |
437e2ff1 | 2685 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2686 | continue; |
437e2ff1 | 2687 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2688 | || imm_expr->X_op != O_constant |
5a9f5403 | 2689 | || !VALID_CITYPE_LDSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2690 | break; |
2691 | ip->insn_opcode |= | |
5a9f5403 | 2692 | ENCODE_CITYPE_LDSP_IMM (imm_expr->X_add_number); |
e23eba97 | 2693 | goto rvc_imm_done; |
b416fe87 | 2694 | case 'o': |
437e2ff1 | 2695 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
b416fe87 | 2696 | || imm_expr->X_op != O_constant |
21a186f2 JW |
2697 | /* C.addiw, c.li, and c.andi allow zero immediate. |
2698 | C.addi allows zero immediate as hint. Otherwise this | |
2699 | is same as 'j'. */ | |
5a9f5403 | 2700 | || !VALID_CITYPE_IMM ((valueT) imm_expr->X_add_number)) |
b416fe87 | 2701 | break; |
5a9f5403 | 2702 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
b416fe87 | 2703 | goto rvc_imm_done; |
e23eba97 | 2704 | case 'K': |
437e2ff1 | 2705 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2706 | || imm_expr->X_op != O_constant |
169ec512 | 2707 | || imm_expr->X_add_number == 0 |
5a9f5403 | 2708 | || !VALID_CIWTYPE_ADDI4SPN_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2709 | break; |
2710 | ip->insn_opcode |= | |
5a9f5403 | 2711 | ENCODE_CIWTYPE_ADDI4SPN_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2712 | goto rvc_imm_done; |
2713 | case 'L': | |
437e2ff1 | 2714 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2715 | || imm_expr->X_op != O_constant |
5a9f5403 | 2716 | || !VALID_CITYPE_ADDI16SP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2717 | break; |
2718 | ip->insn_opcode |= | |
5a9f5403 | 2719 | ENCODE_CITYPE_ADDI16SP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2720 | goto rvc_imm_done; |
2721 | case 'M': | |
437e2ff1 | 2722 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2723 | continue; |
437e2ff1 | 2724 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2725 | || imm_expr->X_op != O_constant |
5a9f5403 | 2726 | || !VALID_CSSTYPE_SWSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2727 | break; |
2728 | ip->insn_opcode |= | |
5a9f5403 | 2729 | ENCODE_CSSTYPE_SWSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2730 | goto rvc_imm_done; |
2731 | case 'N': | |
437e2ff1 | 2732 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
f0531ed6 | 2733 | continue; |
437e2ff1 | 2734 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 | 2735 | || imm_expr->X_op != O_constant |
5a9f5403 | 2736 | || !VALID_CSSTYPE_SDSP_IMM ((valueT) imm_expr->X_add_number)) |
e23eba97 NC |
2737 | break; |
2738 | ip->insn_opcode |= | |
5a9f5403 | 2739 | ENCODE_CSSTYPE_SDSP_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2740 | goto rvc_imm_done; |
2741 | case 'u': | |
2742 | p = percent_op_utype; | |
437e2ff1 | 2743 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 | 2744 | break; |
dc1e8a47 | 2745 | rvc_lui: |
e23eba97 NC |
2746 | if (imm_expr->X_op != O_constant |
2747 | || imm_expr->X_add_number <= 0 | |
2748 | || imm_expr->X_add_number >= RISCV_BIGIMM_REACH | |
2749 | || (imm_expr->X_add_number >= RISCV_RVC_IMM_REACH / 2 | |
2750 | && (imm_expr->X_add_number < | |
2751 | RISCV_BIGIMM_REACH - RISCV_RVC_IMM_REACH / 2))) | |
2752 | break; | |
5a9f5403 | 2753 | ip->insn_opcode |= ENCODE_CITYPE_IMM (imm_expr->X_add_number); |
e23eba97 NC |
2754 | goto rvc_imm_done; |
2755 | case 'v': | |
437e2ff1 | 2756 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e23eba97 NC |
2757 | || (imm_expr->X_add_number & (RISCV_IMM_REACH - 1)) |
2758 | || ((int32_t)imm_expr->X_add_number | |
2759 | != imm_expr->X_add_number)) | |
2760 | break; | |
2761 | imm_expr->X_add_number = | |
2762 | ((uint32_t) imm_expr->X_add_number) >> RISCV_IMM_BITS; | |
2763 | goto rvc_lui; | |
2764 | case 'p': | |
2765 | goto branch; | |
2766 | case 'a': | |
a3c2d248 JB |
2767 | if (oparg == insn->args + 1) |
2768 | goto jump_check_gpr; | |
e23eba97 | 2769 | goto jump; |
0e35537d | 2770 | case 'S': /* Floating-point RS1 x8-x15. */ |
437e2ff1 | 2771 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no) |
0e35537d JW |
2772 | || !(regno >= 8 && regno <= 15)) |
2773 | break; | |
2774 | INSERT_OPERAND (CRS1S, *ip, regno % 8); | |
2775 | continue; | |
e23eba97 | 2776 | case 'D': /* Floating-point RS2 x8-x15. */ |
437e2ff1 | 2777 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no) |
e23eba97 NC |
2778 | || !(regno >= 8 && regno <= 15)) |
2779 | break; | |
2780 | INSERT_OPERAND (CRS2S, *ip, regno % 8); | |
2781 | continue; | |
2782 | case 'T': /* Floating-point RS2. */ | |
437e2ff1 | 2783 | if (!reg_lookup (&asarg, RCLASS_FPR, ®no)) |
e23eba97 NC |
2784 | break; |
2785 | INSERT_OPERAND (CRS2, *ip, regno); | |
2786 | continue; | |
0e35537d | 2787 | case 'F': |
437e2ff1 | 2788 | switch (*++oparg) |
0e35537d | 2789 | { |
4765cd61 | 2790 | case '6': |
437e2ff1 | 2791 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
4765cd61 JW |
2792 | || imm_expr->X_op != O_constant |
2793 | || imm_expr->X_add_number < 0 | |
2794 | || imm_expr->X_add_number >= 64) | |
2795 | { | |
b800637e | 2796 | as_bad (_("bad value for compressed funct6 " |
b215cdf5 | 2797 | "field, value must be 0...63")); |
4765cd61 JW |
2798 | break; |
2799 | } | |
4765cd61 JW |
2800 | INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number); |
2801 | imm_expr->X_op = O_absent; | |
6eb099ae | 2802 | asarg = expr_parse_end; |
4765cd61 | 2803 | continue; |
1942a048 | 2804 | |
0e35537d | 2805 | case '4': |
437e2ff1 | 2806 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
2807 | || imm_expr->X_op != O_constant |
2808 | || imm_expr->X_add_number < 0 | |
2809 | || imm_expr->X_add_number >= 16) | |
2810 | { | |
b800637e NC |
2811 | as_bad (_("bad value for compressed funct4 " |
2812 | "field, value must be 0...15")); | |
0e35537d JW |
2813 | break; |
2814 | } | |
0e35537d JW |
2815 | INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number); |
2816 | imm_expr->X_op = O_absent; | |
6eb099ae | 2817 | asarg = expr_parse_end; |
0e35537d | 2818 | continue; |
1942a048 | 2819 | |
0e35537d | 2820 | case '3': |
437e2ff1 | 2821 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
2822 | || imm_expr->X_op != O_constant |
2823 | || imm_expr->X_add_number < 0 | |
2824 | || imm_expr->X_add_number >= 8) | |
2825 | { | |
b800637e NC |
2826 | as_bad (_("bad value for compressed funct3 " |
2827 | "field, value must be 0...7")); | |
0e35537d JW |
2828 | break; |
2829 | } | |
2830 | INSERT_OPERAND (CFUNCT3, *ip, imm_expr->X_add_number); | |
2831 | imm_expr->X_op = O_absent; | |
6eb099ae | 2832 | asarg = expr_parse_end; |
0e35537d | 2833 | continue; |
1942a048 | 2834 | |
4765cd61 | 2835 | case '2': |
437e2ff1 | 2836 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
4765cd61 JW |
2837 | || imm_expr->X_op != O_constant |
2838 | || imm_expr->X_add_number < 0 | |
2839 | || imm_expr->X_add_number >= 4) | |
2840 | { | |
b800637e NC |
2841 | as_bad (_("bad value for compressed funct2 " |
2842 | "field, value must be 0...3")); | |
4765cd61 JW |
2843 | break; |
2844 | } | |
2845 | INSERT_OPERAND (CFUNCT2, *ip, imm_expr->X_add_number); | |
2846 | imm_expr->X_op = O_absent; | |
6eb099ae | 2847 | asarg = expr_parse_end; |
4765cd61 | 2848 | continue; |
1942a048 | 2849 | |
0e35537d | 2850 | default: |
437e2ff1 | 2851 | goto unknown_riscv_ip_operand; |
0e35537d JW |
2852 | } |
2853 | break; | |
2854 | ||
e23eba97 | 2855 | default: |
437e2ff1 | 2856 | goto unknown_riscv_ip_operand; |
e23eba97 | 2857 | } |
a63375ac | 2858 | break; /* end RVC */ |
e23eba97 | 2859 | |
65e4a99a NC |
2860 | case 'V': /* RVV */ |
2861 | switch (*++oparg) | |
2862 | { | |
2863 | case 'd': /* VD */ | |
2864 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2865 | break; | |
2866 | INSERT_OPERAND (VD, *ip, regno); | |
2867 | continue; | |
2868 | ||
2869 | case 'e': /* AMO VD */ | |
2870 | if (reg_lookup (&asarg, RCLASS_GPR, ®no) && regno == 0) | |
2871 | INSERT_OPERAND (VWD, *ip, 0); | |
2872 | else if (reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2873 | { | |
2874 | INSERT_OPERAND (VWD, *ip, 1); | |
2875 | INSERT_OPERAND (VD, *ip, regno); | |
2876 | } | |
2877 | else | |
2878 | break; | |
2879 | continue; | |
2880 | ||
2881 | case 'f': /* AMO VS3 */ | |
2882 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2883 | break; | |
2884 | if (!EXTRACT_OPERAND (VWD, ip->insn_opcode)) | |
2885 | INSERT_OPERAND (VD, *ip, regno); | |
2886 | else | |
2887 | { | |
2888 | /* VS3 must match VD. */ | |
2889 | if (EXTRACT_OPERAND (VD, ip->insn_opcode) != regno) | |
2890 | break; | |
2891 | } | |
2892 | continue; | |
2893 | ||
2894 | case 's': /* VS1 */ | |
2895 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2896 | break; | |
2897 | INSERT_OPERAND (VS1, *ip, regno); | |
2898 | continue; | |
2899 | ||
2900 | case 't': /* VS2 */ | |
2901 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2902 | break; | |
2903 | INSERT_OPERAND (VS2, *ip, regno); | |
2904 | continue; | |
2905 | ||
2906 | case 'u': /* VS1 == VS2 */ | |
2907 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2908 | break; | |
2909 | INSERT_OPERAND (VS1, *ip, regno); | |
2910 | INSERT_OPERAND (VS2, *ip, regno); | |
2911 | continue; | |
2912 | ||
2913 | case 'v': /* VD == VS1 == VS2 */ | |
2914 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no)) | |
2915 | break; | |
2916 | INSERT_OPERAND (VD, *ip, regno); | |
2917 | INSERT_OPERAND (VS1, *ip, regno); | |
2918 | INSERT_OPERAND (VS2, *ip, regno); | |
2919 | continue; | |
2920 | ||
2921 | /* The `V0` is carry-in register for v[m]adc and v[m]sbc, | |
2922 | and is used to choose vs1/rs1/frs1/imm or vs2 for | |
2923 | v[f]merge. It use the same encoding as the vector mask | |
2924 | register. */ | |
2925 | case '0': | |
2926 | if (reg_lookup (&asarg, RCLASS_VECR, ®no) && regno == 0) | |
2927 | continue; | |
2928 | break; | |
2929 | ||
2930 | case 'b': /* vtypei for vsetivli */ | |
2931 | my_getVsetvliExpression (imm_expr, asarg); | |
2932 | check_absolute_expr (ip, imm_expr, FALSE); | |
2933 | if (!VALID_RVV_VB_IMM (imm_expr->X_add_number)) | |
2934 | as_bad (_("bad value for vsetivli immediate field, " | |
2935 | "value must be 0..1023")); | |
2936 | ip->insn_opcode | |
2937 | |= ENCODE_RVV_VB_IMM (imm_expr->X_add_number); | |
2938 | imm_expr->X_op = O_absent; | |
6eb099ae | 2939 | asarg = expr_parse_end; |
65e4a99a NC |
2940 | continue; |
2941 | ||
2942 | case 'c': /* vtypei for vsetvli */ | |
2943 | my_getVsetvliExpression (imm_expr, asarg); | |
2944 | check_absolute_expr (ip, imm_expr, FALSE); | |
2945 | if (!VALID_RVV_VC_IMM (imm_expr->X_add_number)) | |
2946 | as_bad (_("bad value for vsetvli immediate field, " | |
2947 | "value must be 0..2047")); | |
2948 | ip->insn_opcode | |
2949 | |= ENCODE_RVV_VC_IMM (imm_expr->X_add_number); | |
2950 | imm_expr->X_op = O_absent; | |
6eb099ae | 2951 | asarg = expr_parse_end; |
65e4a99a NC |
2952 | continue; |
2953 | ||
2954 | case 'i': /* vector arith signed immediate */ | |
2955 | my_getExpression (imm_expr, asarg); | |
2956 | check_absolute_expr (ip, imm_expr, FALSE); | |
2957 | if (imm_expr->X_add_number > 15 | |
2958 | || imm_expr->X_add_number < -16) | |
2959 | as_bad (_("bad value for vector immediate field, " | |
2960 | "value must be -16...15")); | |
2961 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); | |
2962 | imm_expr->X_op = O_absent; | |
6eb099ae | 2963 | asarg = expr_parse_end; |
65e4a99a NC |
2964 | continue; |
2965 | ||
2966 | case 'j': /* vector arith unsigned immediate */ | |
2967 | my_getExpression (imm_expr, asarg); | |
2968 | check_absolute_expr (ip, imm_expr, FALSE); | |
2969 | if (imm_expr->X_add_number < 0 | |
2970 | || imm_expr->X_add_number >= 32) | |
2971 | as_bad (_("bad value for vector immediate field, " | |
2972 | "value must be 0...31")); | |
2973 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number); | |
2974 | imm_expr->X_op = O_absent; | |
6eb099ae | 2975 | asarg = expr_parse_end; |
65e4a99a NC |
2976 | continue; |
2977 | ||
2978 | case 'k': /* vector arith signed immediate, minus 1 */ | |
2979 | my_getExpression (imm_expr, asarg); | |
2980 | check_absolute_expr (ip, imm_expr, FALSE); | |
2981 | if (imm_expr->X_add_number > 16 | |
2982 | || imm_expr->X_add_number < -15) | |
2983 | as_bad (_("bad value for vector immediate field, " | |
2984 | "value must be -15...16")); | |
2985 | INSERT_OPERAND (VIMM, *ip, imm_expr->X_add_number - 1); | |
2986 | imm_expr->X_op = O_absent; | |
6eb099ae | 2987 | asarg = expr_parse_end; |
65e4a99a NC |
2988 | continue; |
2989 | ||
2990 | case 'm': /* optional vector mask */ | |
2991 | if (*asarg == '\0') | |
2992 | { | |
2993 | INSERT_OPERAND (VMASK, *ip, 1); | |
2994 | continue; | |
2995 | } | |
2996 | else if (*asarg == ',' && asarg++ | |
2997 | && reg_lookup (&asarg, RCLASS_VECM, ®no) | |
2998 | && regno == 0) | |
2999 | { | |
3000 | INSERT_OPERAND (VMASK, *ip, 0); | |
3001 | continue; | |
3002 | } | |
3003 | break; | |
3004 | ||
3005 | case 'M': /* required vector mask */ | |
3006 | if (reg_lookup (&asarg, RCLASS_VECM, ®no) && regno == 0) | |
3007 | { | |
3008 | INSERT_OPERAND (VMASK, *ip, 0); | |
3009 | continue; | |
3010 | } | |
3011 | break; | |
3012 | ||
3013 | case 'T': /* vector macro temporary register */ | |
3014 | if (!reg_lookup (&asarg, RCLASS_VECR, ®no) || regno == 0) | |
3015 | break; | |
3016 | /* Store it in the FUNCT6 field as we don't have anyplace | |
3017 | else to store it. */ | |
3018 | INSERT_OPERAND (VFUNCT6, *ip, regno); | |
3019 | continue; | |
3020 | ||
3021 | default: | |
3022 | goto unknown_riscv_ip_operand; | |
3023 | } | |
a63375ac | 3024 | break; /* end RVV */ |
65e4a99a | 3025 | |
e23eba97 | 3026 | case ',': |
437e2ff1 | 3027 | if (*asarg++ == *oparg) |
e23eba97 | 3028 | continue; |
437e2ff1 | 3029 | asarg--; |
e23eba97 NC |
3030 | break; |
3031 | ||
3032 | case '(': | |
3033 | case ')': | |
3034 | case '[': | |
3035 | case ']': | |
437e2ff1 | 3036 | if (*asarg++ == *oparg) |
e23eba97 NC |
3037 | continue; |
3038 | break; | |
3039 | ||
dcd709e0 | 3040 | case '<': /* Shift amount, 0 - 31. */ |
437e2ff1 | 3041 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3042 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3043 | if ((unsigned long) imm_expr->X_add_number > 31) |
a6eeb20a CM |
3044 | as_bad (_("improper shift amount (%"PRIu64")"), |
3045 | imm_expr->X_add_number); | |
e23eba97 NC |
3046 | INSERT_OPERAND (SHAMTW, *ip, imm_expr->X_add_number); |
3047 | imm_expr->X_op = O_absent; | |
6eb099ae | 3048 | asarg = expr_parse_end; |
e23eba97 NC |
3049 | continue; |
3050 | ||
dcd709e0 | 3051 | case '>': /* Shift amount, 0 - (XLEN-1). */ |
437e2ff1 | 3052 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3053 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3054 | if ((unsigned long) imm_expr->X_add_number >= xlen) |
a6eeb20a CM |
3055 | as_bad (_("improper shift amount (%"PRIu64")"), |
3056 | imm_expr->X_add_number); | |
e23eba97 NC |
3057 | INSERT_OPERAND (SHAMT, *ip, imm_expr->X_add_number); |
3058 | imm_expr->X_op = O_absent; | |
6eb099ae | 3059 | asarg = expr_parse_end; |
e23eba97 NC |
3060 | continue; |
3061 | ||
dcd709e0 | 3062 | case 'Z': /* CSRRxI immediate. */ |
437e2ff1 | 3063 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3064 | check_absolute_expr (ip, imm_expr, false); |
e23eba97 | 3065 | if ((unsigned long) imm_expr->X_add_number > 31) |
a6eeb20a CM |
3066 | as_bad (_("improper CSRxI immediate (%"PRIu64")"), |
3067 | imm_expr->X_add_number); | |
e23eba97 NC |
3068 | INSERT_OPERAND (RS1, *ip, imm_expr->X_add_number); |
3069 | imm_expr->X_op = O_absent; | |
6eb099ae | 3070 | asarg = expr_parse_end; |
e23eba97 NC |
3071 | continue; |
3072 | ||
dcd709e0 | 3073 | case 'E': /* Control register. */ |
5b7c81bd AM |
3074 | insn_with_csr = true; |
3075 | explicit_priv_attr = true; | |
437e2ff1 | 3076 | if (reg_lookup (&asarg, RCLASS_CSR, ®no)) |
e23eba97 NC |
3077 | INSERT_OPERAND (CSR, *ip, regno); |
3078 | else | |
3079 | { | |
437e2ff1 | 3080 | my_getExpression (imm_expr, asarg); |
5b7c81bd | 3081 | check_absolute_expr (ip, imm_expr, true); |
e23eba97 | 3082 | if ((unsigned long) imm_expr->X_add_number > 0xfff) |
a6eeb20a CM |
3083 | as_bad (_("improper CSR address (%"PRIu64")"), |
3084 | imm_expr->X_add_number); | |
e23eba97 NC |
3085 | INSERT_OPERAND (CSR, *ip, imm_expr->X_add_number); |
3086 | imm_expr->X_op = O_absent; | |
6eb099ae | 3087 | asarg = expr_parse_end; |
e23eba97 NC |
3088 | } |
3089 | continue; | |
3090 | ||
dcd709e0 | 3091 | case 'm': /* Rounding mode. */ |
437e2ff1 NC |
3092 | if (arg_lookup (&asarg, riscv_rm, |
3093 | ARRAY_SIZE (riscv_rm), ®no)) | |
e23eba97 NC |
3094 | { |
3095 | INSERT_OPERAND (RM, *ip, regno); | |
3096 | continue; | |
3097 | } | |
3098 | break; | |
3099 | ||
3100 | case 'P': | |
dcd709e0 | 3101 | case 'Q': /* Fence predecessor/successor. */ |
437e2ff1 NC |
3102 | if (arg_lookup (&asarg, riscv_pred_succ, |
3103 | ARRAY_SIZE (riscv_pred_succ), ®no)) | |
e23eba97 | 3104 | { |
437e2ff1 | 3105 | if (*oparg == 'P') |
e23eba97 NC |
3106 | INSERT_OPERAND (PRED, *ip, regno); |
3107 | else | |
3108 | INSERT_OPERAND (SUCC, *ip, regno); | |
3109 | continue; | |
3110 | } | |
3111 | break; | |
3112 | ||
dcd709e0 NC |
3113 | case 'd': /* Destination register. */ |
3114 | case 's': /* Source register. */ | |
3115 | case 't': /* Target register. */ | |
3116 | case 'r': /* RS3 */ | |
437e2ff1 | 3117 | if (reg_lookup (&asarg, RCLASS_GPR, ®no)) |
e23eba97 | 3118 | { |
437e2ff1 NC |
3119 | char c = *oparg; |
3120 | if (*asarg == ' ') | |
3121 | ++asarg; | |
e23eba97 NC |
3122 | |
3123 | /* Now that we have assembled one operand, we use the args | |
3124 | string to figure out where it goes in the instruction. */ | |
3125 | switch (c) | |
3126 | { | |
3127 | case 's': | |
3128 | INSERT_OPERAND (RS1, *ip, regno); | |
3129 | break; | |
3130 | case 'd': | |
3131 | INSERT_OPERAND (RD, *ip, regno); | |
3132 | break; | |
3133 | case 't': | |
3134 | INSERT_OPERAND (RS2, *ip, regno); | |
3135 | break; | |
0e35537d JW |
3136 | case 'r': |
3137 | INSERT_OPERAND (RS3, *ip, regno); | |
3138 | break; | |
e23eba97 NC |
3139 | } |
3140 | continue; | |
3141 | } | |
3142 | break; | |
3143 | ||
dcd709e0 NC |
3144 | case 'D': /* Floating point RD. */ |
3145 | case 'S': /* Floating point RS1. */ | |
3146 | case 'T': /* Floating point RS2. */ | |
3147 | case 'U': /* Floating point RS1 and RS2. */ | |
3148 | case 'R': /* Floating point RS3. */ | |
de83e514 | 3149 | if (reg_lookup (&asarg, |
3150 | (riscv_subset_supports (&riscv_rps_as, "zfinx") | |
3151 | ? RCLASS_GPR : RCLASS_FPR), ®no)) | |
e23eba97 | 3152 | { |
437e2ff1 NC |
3153 | char c = *oparg; |
3154 | if (*asarg == ' ') | |
3155 | ++asarg; | |
e23eba97 NC |
3156 | switch (c) |
3157 | { | |
3158 | case 'D': | |
3159 | INSERT_OPERAND (RD, *ip, regno); | |
3160 | break; | |
3161 | case 'S': | |
3162 | INSERT_OPERAND (RS1, *ip, regno); | |
3163 | break; | |
3164 | case 'U': | |
3165 | INSERT_OPERAND (RS1, *ip, regno); | |
dcd709e0 | 3166 | /* Fall through. */ |
e23eba97 NC |
3167 | case 'T': |
3168 | INSERT_OPERAND (RS2, *ip, regno); | |
3169 | break; | |
3170 | case 'R': | |
3171 | INSERT_OPERAND (RS3, *ip, regno); | |
3172 | break; | |
3173 | } | |
3174 | continue; | |
3175 | } | |
e23eba97 NC |
3176 | break; |
3177 | ||
3178 | case 'I': | |
437e2ff1 | 3179 | my_getExpression (imm_expr, asarg); |
e23eba97 NC |
3180 | if (imm_expr->X_op != O_big |
3181 | && imm_expr->X_op != O_constant) | |
3182 | break; | |
3183 | normalize_constant_expr (imm_expr); | |
6eb099ae | 3184 | asarg = expr_parse_end; |
e23eba97 NC |
3185 | continue; |
3186 | ||
3187 | case 'A': | |
437e2ff1 | 3188 | my_getExpression (imm_expr, asarg); |
e23eba97 NC |
3189 | normalize_constant_expr (imm_expr); |
3190 | /* The 'A' format specifier must be a symbol. */ | |
3191 | if (imm_expr->X_op != O_symbol) | |
3192 | break; | |
3193 | *imm_reloc = BFD_RELOC_32; | |
6eb099ae | 3194 | asarg = expr_parse_end; |
e23eba97 NC |
3195 | continue; |
3196 | ||
160d1b3d | 3197 | case 'B': |
437e2ff1 | 3198 | my_getExpression (imm_expr, asarg); |
160d1b3d SH |
3199 | normalize_constant_expr (imm_expr); |
3200 | /* The 'B' format specifier must be a symbol or a constant. */ | |
3201 | if (imm_expr->X_op != O_symbol && imm_expr->X_op != O_constant) | |
3202 | break; | |
3203 | if (imm_expr->X_op == O_symbol) | |
3204 | *imm_reloc = BFD_RELOC_32; | |
6eb099ae | 3205 | asarg = expr_parse_end; |
160d1b3d SH |
3206 | continue; |
3207 | ||
e23eba97 | 3208 | case 'j': /* Sign-extended immediate. */ |
e23eba97 | 3209 | p = percent_op_itype; |
f50fabe4 | 3210 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; |
e23eba97 NC |
3211 | goto alu_op; |
3212 | case 'q': /* Store displacement. */ | |
3213 | p = percent_op_stype; | |
3214 | *imm_reloc = BFD_RELOC_RISCV_LO12_S; | |
3215 | goto load_store; | |
3216 | case 'o': /* Load displacement. */ | |
3217 | p = percent_op_itype; | |
3218 | *imm_reloc = BFD_RELOC_RISCV_LO12_I; | |
3219 | goto load_store; | |
dcd709e0 NC |
3220 | case '1': |
3221 | /* This is used for TLS, where the fourth operand is | |
3222 | %tprel_add, to get a relocation applied to an add | |
3223 | instruction, for relaxation to use. */ | |
e23eba97 | 3224 | p = percent_op_rtype; |
f50fabe4 | 3225 | goto alu_op; |
dcd709e0 | 3226 | case '0': /* AMO displacement, which must be zero. */ |
f50fabe4 | 3227 | p = percent_op_null; |
dc1e8a47 | 3228 | load_store: |
437e2ff1 | 3229 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) |
e23eba97 | 3230 | continue; |
dc1e8a47 | 3231 | alu_op: |
e23eba97 NC |
3232 | /* If this value won't fit into a 16 bit offset, then go |
3233 | find a macro that will generate the 32 bit offset | |
3234 | code pattern. */ | |
437e2ff1 | 3235 | if (!my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 NC |
3236 | { |
3237 | normalize_constant_expr (imm_expr); | |
3238 | if (imm_expr->X_op != O_constant | |
437e2ff1 NC |
3239 | || (*oparg == '0' && imm_expr->X_add_number != 0) |
3240 | || (*oparg == '1') | |
e23eba97 NC |
3241 | || imm_expr->X_add_number >= (signed)RISCV_IMM_REACH/2 |
3242 | || imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2) | |
3243 | break; | |
3244 | } | |
6eb099ae | 3245 | asarg = expr_parse_end; |
e23eba97 NC |
3246 | continue; |
3247 | ||
dcd709e0 | 3248 | case 'p': /* PC-relative offset. */ |
dc1e8a47 | 3249 | branch: |
e23eba97 | 3250 | *imm_reloc = BFD_RELOC_12_PCREL; |
437e2ff1 | 3251 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3252 | asarg = expr_parse_end; |
e23eba97 NC |
3253 | continue; |
3254 | ||
dcd709e0 | 3255 | case 'u': /* Upper 20 bits. */ |
e23eba97 | 3256 | p = percent_op_utype; |
437e2ff1 | 3257 | if (!my_getSmallExpression (imm_expr, imm_reloc, asarg, p)) |
e23eba97 | 3258 | { |
4288405d JW |
3259 | if (imm_expr->X_op != O_constant) |
3260 | break; | |
3261 | ||
e23eba97 NC |
3262 | if (imm_expr->X_add_number < 0 |
3263 | || imm_expr->X_add_number >= (signed)RISCV_BIGIMM_REACH) | |
3264 | as_bad (_("lui expression not in range 0..1048575")); | |
3265 | ||
3266 | *imm_reloc = BFD_RELOC_RISCV_HI20; | |
3267 | imm_expr->X_add_number <<= RISCV_IMM_BITS; | |
3268 | } | |
6eb099ae | 3269 | asarg = expr_parse_end; |
e23eba97 NC |
3270 | continue; |
3271 | ||
dcd709e0 | 3272 | case 'a': /* 20-bit PC-relative offset. */ |
f56532cc JB |
3273 | /* Like in my_getSmallExpression() we need to avoid emitting |
3274 | a stray undefined symbol if the 1st JAL entry doesn't match, | |
3275 | but the 2nd (with 2 operands) might. */ | |
3276 | if (oparg == insn->args) | |
3277 | { | |
a3c2d248 | 3278 | jump_check_gpr: |
f56532cc JB |
3279 | asargStart = asarg; |
3280 | if (reg_lookup (&asarg, RCLASS_GPR, NULL) | |
3281 | && (*asarg == ',' || (ISSPACE (*asarg) && asarg[1] == ','))) | |
3282 | break; | |
3283 | asarg = asargStart; | |
3284 | } | |
dc1e8a47 | 3285 | jump: |
437e2ff1 | 3286 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3287 | asarg = expr_parse_end; |
e23eba97 NC |
3288 | *imm_reloc = BFD_RELOC_RISCV_JMP; |
3289 | continue; | |
3290 | ||
3291 | case 'c': | |
437e2ff1 | 3292 | my_getExpression (imm_expr, asarg); |
6eb099ae | 3293 | asarg = expr_parse_end; |
437e2ff1 | 3294 | if (strcmp (asarg, "@plt") == 0) |
70f35d72 NC |
3295 | asarg += 4; |
3296 | *imm_reloc = BFD_RELOC_RISCV_CALL_PLT; | |
e23eba97 | 3297 | continue; |
1942a048 | 3298 | |
0e35537d | 3299 | case 'O': |
437e2ff1 | 3300 | switch (*++oparg) |
0e35537d JW |
3301 | { |
3302 | case '4': | |
437e2ff1 | 3303 | if (my_getOpcodeExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3304 | || imm_expr->X_op != O_constant |
3305 | || imm_expr->X_add_number < 0 | |
3306 | || imm_expr->X_add_number >= 128 | |
3307 | || (imm_expr->X_add_number & 0x3) != 3) | |
3308 | { | |
3309 | as_bad (_("bad value for opcode field, " | |
3310 | "value must be 0...127 and " | |
3311 | "lower 2 bits must be 0x3")); | |
3312 | break; | |
3313 | } | |
0e35537d JW |
3314 | INSERT_OPERAND (OP, *ip, imm_expr->X_add_number); |
3315 | imm_expr->X_op = O_absent; | |
6eb099ae | 3316 | asarg = expr_parse_end; |
0e35537d | 3317 | continue; |
1942a048 | 3318 | |
0e35537d | 3319 | case '2': |
437e2ff1 | 3320 | if (my_getOpcodeExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3321 | || imm_expr->X_op != O_constant |
3322 | || imm_expr->X_add_number < 0 | |
3323 | || imm_expr->X_add_number >= 3) | |
3324 | { | |
3325 | as_bad (_("bad value for opcode field, " | |
3326 | "value must be 0...2")); | |
3327 | break; | |
3328 | } | |
0e35537d JW |
3329 | INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number); |
3330 | imm_expr->X_op = O_absent; | |
6eb099ae | 3331 | asarg = expr_parse_end; |
0e35537d | 3332 | continue; |
1942a048 | 3333 | |
0e35537d | 3334 | default: |
437e2ff1 | 3335 | goto unknown_riscv_ip_operand; |
0e35537d JW |
3336 | } |
3337 | break; | |
3338 | ||
3339 | case 'F': | |
437e2ff1 | 3340 | switch (*++oparg) |
0e35537d JW |
3341 | { |
3342 | case '7': | |
437e2ff1 | 3343 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3344 | || imm_expr->X_op != O_constant |
3345 | || imm_expr->X_add_number < 0 | |
3346 | || imm_expr->X_add_number >= 128) | |
3347 | { | |
3348 | as_bad (_("bad value for funct7 field, " | |
3349 | "value must be 0...127")); | |
3350 | break; | |
3351 | } | |
0e35537d JW |
3352 | INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number); |
3353 | imm_expr->X_op = O_absent; | |
6eb099ae | 3354 | asarg = expr_parse_end; |
0e35537d | 3355 | continue; |
1942a048 | 3356 | |
0e35537d | 3357 | case '3': |
437e2ff1 | 3358 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3359 | || imm_expr->X_op != O_constant |
3360 | || imm_expr->X_add_number < 0 | |
3361 | || imm_expr->X_add_number >= 8) | |
3362 | { | |
3363 | as_bad (_("bad value for funct3 field, " | |
3364 | "value must be 0...7")); | |
3365 | break; | |
3366 | } | |
0e35537d JW |
3367 | INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number); |
3368 | imm_expr->X_op = O_absent; | |
6eb099ae | 3369 | asarg = expr_parse_end; |
0e35537d | 3370 | continue; |
1942a048 | 3371 | |
0e35537d | 3372 | case '2': |
437e2ff1 | 3373 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
0e35537d JW |
3374 | || imm_expr->X_op != O_constant |
3375 | || imm_expr->X_add_number < 0 | |
3376 | || imm_expr->X_add_number >= 4) | |
3377 | { | |
3378 | as_bad (_("bad value for funct2 field, " | |
3379 | "value must be 0...3")); | |
3380 | break; | |
3381 | } | |
0e35537d JW |
3382 | INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number); |
3383 | imm_expr->X_op = O_absent; | |
6eb099ae | 3384 | asarg = expr_parse_end; |
0e35537d JW |
3385 | continue; |
3386 | ||
3387 | default: | |
437e2ff1 | 3388 | goto unknown_riscv_ip_operand; |
0e35537d JW |
3389 | } |
3390 | break; | |
e23eba97 | 3391 | |
3d1cafa0 | 3392 | case 'y': /* bs immediate */ |
3393 | my_getExpression (imm_expr, asarg); | |
3394 | check_absolute_expr (ip, imm_expr, FALSE); | |
3395 | if ((unsigned long)imm_expr->X_add_number > 3) | |
3396 | as_bad(_("Improper bs immediate (%lu)"), | |
3397 | (unsigned long)imm_expr->X_add_number); | |
3398 | INSERT_OPERAND(BS, *ip, imm_expr->X_add_number); | |
3399 | imm_expr->X_op = O_absent; | |
6eb099ae | 3400 | asarg = expr_parse_end; |
3d1cafa0 | 3401 | continue; |
3402 | ||
3403 | case 'Y': /* rnum immediate */ | |
3404 | my_getExpression (imm_expr, asarg); | |
3405 | check_absolute_expr (ip, imm_expr, FALSE); | |
3406 | if ((unsigned long)imm_expr->X_add_number > 10) | |
3407 | as_bad(_("Improper rnum immediate (%lu)"), | |
3408 | (unsigned long)imm_expr->X_add_number); | |
3409 | INSERT_OPERAND(RNUM, *ip, imm_expr->X_add_number); | |
3410 | imm_expr->X_op = O_absent; | |
6eb099ae | 3411 | asarg = expr_parse_end; |
3d1cafa0 | 3412 | continue; |
3413 | ||
e925c834 | 3414 | case 'z': |
437e2ff1 | 3415 | if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) |
e925c834 JW |
3416 | || imm_expr->X_op != O_constant |
3417 | || imm_expr->X_add_number != 0) | |
3418 | break; | |
6eb099ae | 3419 | asarg = expr_parse_end; |
e925c834 JW |
3420 | imm_expr->X_op = O_absent; |
3421 | continue; | |
3422 | ||
3b374308 TO |
3423 | case 'f': /* Prefetch offset, pseudo S-type but lower 5-bits zero. */ |
3424 | if (riscv_handle_implicit_zero_offset (imm_expr, asarg)) | |
3425 | continue; | |
3426 | my_getExpression (imm_expr, asarg); | |
3427 | check_absolute_expr (ip, imm_expr, false); | |
3428 | if (((unsigned) (imm_expr->X_add_number) & 0x1fU) | |
3429 | || imm_expr->X_add_number >= (signed) RISCV_IMM_REACH / 2 | |
3430 | || imm_expr->X_add_number < -(signed) RISCV_IMM_REACH / 2) | |
3431 | as_bad (_("improper prefetch offset (%ld)"), | |
3432 | (long) imm_expr->X_add_number); | |
3433 | ip->insn_opcode |= | |
3434 | ENCODE_STYPE_IMM ((unsigned) (imm_expr->X_add_number) & | |
3435 | ~ 0x1fU); | |
3436 | imm_expr->X_op = O_absent; | |
6eb099ae | 3437 | asarg = expr_parse_end; |
3b374308 TO |
3438 | continue; |
3439 | ||
8b7419c4 CM |
3440 | case 'X': /* Integer immediate. */ |
3441 | { | |
3442 | size_t n; | |
3443 | size_t s; | |
3444 | bool sign; | |
3445 | ||
3446 | switch (*++oparg) | |
3447 | { | |
25236d63 CM |
3448 | case 'l': /* Literal. */ |
3449 | n = strcspn (++oparg, ","); | |
3450 | if (strncmp (oparg, asarg, n)) | |
3451 | as_bad (_("unexpected literal (%s)"), asarg); | |
3452 | oparg += n - 1; | |
3453 | asarg += n; | |
3454 | continue; | |
8b7419c4 CM |
3455 | case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ |
3456 | sign = true; | |
3457 | goto parse_imm; | |
3458 | case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ | |
3459 | sign = false; | |
3460 | goto parse_imm; | |
3461 | parse_imm: | |
b0423163 | 3462 | n = strtol (oparg + 1, (char **)&oparg, 10); |
8b7419c4 CM |
3463 | if (*oparg != '@') |
3464 | goto unknown_riscv_ip_operand; | |
b0423163 | 3465 | s = strtol (oparg + 1, (char **)&oparg, 10); |
8b7419c4 CM |
3466 | oparg--; |
3467 | ||
3468 | my_getExpression (imm_expr, asarg); | |
3469 | check_absolute_expr (ip, imm_expr, false); | |
3470 | if (!sign) | |
3471 | { | |
3472 | if (!VALIDATE_U_IMM (imm_expr->X_add_number, n)) | |
021205d0 JB |
3473 | as_bad (_("improper immediate value (%"PRIu64")"), |
3474 | imm_expr->X_add_number); | |
8b7419c4 CM |
3475 | } |
3476 | else | |
3477 | { | |
3478 | if (!VALIDATE_S_IMM (imm_expr->X_add_number, n)) | |
021205d0 JB |
3479 | as_bad (_("improper immediate value (%"PRIi64")"), |
3480 | imm_expr->X_add_number); | |
8b7419c4 CM |
3481 | } |
3482 | INSERT_IMM (n, s, *ip, imm_expr->X_add_number); | |
3483 | imm_expr->X_op = O_absent; | |
6eb099ae | 3484 | asarg = expr_parse_end; |
8b7419c4 CM |
3485 | continue; |
3486 | default: | |
3487 | goto unknown_riscv_ip_operand; | |
3488 | } | |
3489 | } | |
3490 | break; | |
e23eba97 | 3491 | default: |
437e2ff1 NC |
3492 | unknown_riscv_ip_operand: |
3493 | as_fatal (_("internal: unknown argument type `%s'"), | |
3494 | opargStart); | |
e23eba97 NC |
3495 | } |
3496 | break; | |
3497 | } | |
437e2ff1 | 3498 | asarg = asargStart; |
5b7c81bd | 3499 | insn_with_csr = false; |
e23eba97 NC |
3500 | } |
3501 | ||
dc1e8a47 | 3502 | out: |
e23eba97 NC |
3503 | /* Restore the character we might have clobbered above. */ |
3504 | if (save_c) | |
437e2ff1 | 3505 | *(asargStart - 1) = save_c; |
e23eba97 NC |
3506 | |
3507 | return error; | |
3508 | } | |
3509 | ||
a262b82f NC |
3510 | /* Similar to riscv_ip, but assembles an instruction according to the |
3511 | hardcode values of .insn directive. */ | |
3512 | ||
3513 | static const char * | |
3514 | riscv_ip_hardcode (char *str, | |
3515 | struct riscv_cl_insn *ip, | |
3516 | expressionS *imm_expr, | |
3517 | const char *error) | |
3518 | { | |
3519 | struct riscv_opcode *insn; | |
3520 | insn_t values[2] = {0, 0}; | |
3521 | unsigned int num = 0; | |
3522 | ||
3523 | input_line_pointer = str; | |
3524 | do | |
3525 | { | |
3526 | expression (imm_expr); | |
bb996692 | 3527 | switch (imm_expr->X_op) |
a262b82f | 3528 | { |
bb996692 JB |
3529 | case O_constant: |
3530 | values[num++] = (insn_t) imm_expr->X_add_number; | |
3531 | break; | |
3532 | case O_big: | |
634001bb TO |
3533 | /* Extract lower 32-bits of a big number. |
3534 | Assume that generic_bignum_to_int32 work on such number. */ | |
3535 | values[num++] = (insn_t) generic_bignum_to_int32 (); | |
bb996692 JB |
3536 | break; |
3537 | default: | |
a262b82f NC |
3538 | /* The first value isn't constant, so it should be |
3539 | .insn <type> <operands>. We have been parsed it | |
3540 | in the riscv_ip. */ | |
3541 | if (num == 0) | |
3542 | return error; | |
3543 | return _("values must be constant"); | |
3544 | } | |
a262b82f | 3545 | } |
bb996692 | 3546 | while (*input_line_pointer++ == ',' && num < 2 && imm_expr->X_op != O_big); |
a262b82f NC |
3547 | |
3548 | input_line_pointer--; | |
3549 | if (*input_line_pointer != '\0') | |
3550 | return _("unrecognized values"); | |
3551 | ||
3552 | insn = XNEW (struct riscv_opcode); | |
3553 | insn->match = values[num - 1]; | |
3554 | create_insn (ip, insn); | |
3555 | unsigned int bytes = riscv_insn_length (insn->match); | |
bb996692 JB |
3556 | |
3557 | if (num == 2 && values[0] != bytes) | |
3558 | return _("value conflicts with instruction length"); | |
3559 | ||
3560 | if (imm_expr->X_op == O_big) | |
3561 | { | |
634001bb TO |
3562 | unsigned int llen = 0; |
3563 | for (LITTLENUM_TYPE lval = generic_bignum[imm_expr->X_add_number - 1]; | |
3564 | lval != 0; llen++) | |
3565 | lval >>= BITS_PER_CHAR; | |
3566 | unsigned int repr_bytes | |
3567 | = (imm_expr->X_add_number - 1) * CHARS_PER_LITTLENUM + llen; | |
3568 | if (bytes < repr_bytes) | |
bb996692 | 3569 | return _("value conflicts with instruction length"); |
634001bb TO |
3570 | for (num = 0; num < imm_expr->X_add_number - 1; ++num) |
3571 | number_to_chars_littleendian ( | |
3572 | ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, | |
3573 | generic_bignum[num], | |
3574 | CHARS_PER_LITTLENUM); | |
3575 | if (llen != 0) | |
3576 | number_to_chars_littleendian ( | |
3577 | ip->insn_long_opcode + num * CHARS_PER_LITTLENUM, | |
3578 | generic_bignum[num], | |
3579 | llen); | |
3580 | memset(ip->insn_long_opcode + repr_bytes, 0, bytes - repr_bytes); | |
bb996692 JB |
3581 | return NULL; |
3582 | } | |
3583 | ||
3584 | if (bytes < sizeof(values[0]) && values[num - 1] >> (8 * bytes) != 0) | |
a262b82f NC |
3585 | return _("value conflicts with instruction length"); |
3586 | ||
3587 | return NULL; | |
3588 | } | |
3589 | ||
e23eba97 NC |
3590 | void |
3591 | md_assemble (char *str) | |
3592 | { | |
3593 | struct riscv_cl_insn insn; | |
3594 | expressionS imm_expr; | |
3595 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
3596 | ||
dcd709e0 NC |
3597 | /* The architecture and privileged elf attributes should be set |
3598 | before assembling. */ | |
8f595e9b NC |
3599 | if (!start_assemble) |
3600 | { | |
5b7c81bd | 3601 | start_assemble = true; |
e23eba97 | 3602 | |
dcd709e0 | 3603 | riscv_set_abi_by_arch (); |
8f595e9b NC |
3604 | if (!riscv_set_default_priv_spec (NULL)) |
3605 | return; | |
3606 | } | |
3607 | ||
3190ebcb | 3608 | riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); |
9b9b1092 | 3609 | |
e4028336 PN |
3610 | const struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr, |
3611 | &imm_reloc, op_hash); | |
2dc8dd17 | 3612 | |
e4028336 | 3613 | if (error.msg) |
e23eba97 | 3614 | { |
e4028336 PN |
3615 | if (error.missing_ext) |
3616 | as_bad ("%s `%s', extension `%s' required", error.msg, | |
3617 | error.statement, error.missing_ext); | |
3618 | else | |
3619 | as_bad ("%s `%s'", error.msg, error.statement); | |
e23eba97 NC |
3620 | return; |
3621 | } | |
3622 | ||
3623 | if (insn.insn_mo->pinfo == INSN_MACRO) | |
3624 | macro (&insn, &imm_expr, &imm_reloc); | |
3625 | else | |
3626 | append_insn (&insn, &imm_expr, imm_reloc); | |
3627 | } | |
3628 | ||
3629 | const char * | |
3630 | md_atof (int type, char *litP, int *sizeP) | |
3631 | { | |
3632 | return ieee_md_atof (type, litP, sizeP, TARGET_BYTES_BIG_ENDIAN); | |
3633 | } | |
3634 | ||
3635 | void | |
3636 | md_number_to_chars (char *buf, valueT val, int n) | |
3637 | { | |
fbc09e7a MC |
3638 | if (target_big_endian) |
3639 | number_to_chars_bigendian (buf, val, n); | |
3640 | else | |
3641 | number_to_chars_littleendian (buf, val, n); | |
e23eba97 NC |
3642 | } |
3643 | ||
3644 | const char *md_shortopts = "O::g::G:"; | |
3645 | ||
3646 | enum options | |
3647 | { | |
2922d21d | 3648 | OPTION_MARCH = OPTION_MD_BASE, |
e23eba97 NC |
3649 | OPTION_PIC, |
3650 | OPTION_NO_PIC, | |
2922d21d | 3651 | OPTION_MABI, |
71060565 JW |
3652 | OPTION_RELAX, |
3653 | OPTION_NO_RELAX, | |
2dc8dd17 JW |
3654 | OPTION_ARCH_ATTR, |
3655 | OPTION_NO_ARCH_ATTR, | |
2ca89224 NC |
3656 | OPTION_CSR_CHECK, |
3657 | OPTION_NO_CSR_CHECK, | |
8f595e9b NC |
3658 | OPTION_MISA_SPEC, |
3659 | OPTION_MPRIV_SPEC, | |
fbc09e7a MC |
3660 | OPTION_BIG_ENDIAN, |
3661 | OPTION_LITTLE_ENDIAN, | |
e23eba97 NC |
3662 | OPTION_END_OF_ENUM |
3663 | }; | |
3664 | ||
3665 | struct option md_longopts[] = | |
3666 | { | |
e23eba97 NC |
3667 | {"march", required_argument, NULL, OPTION_MARCH}, |
3668 | {"fPIC", no_argument, NULL, OPTION_PIC}, | |
3669 | {"fpic", no_argument, NULL, OPTION_PIC}, | |
3670 | {"fno-pic", no_argument, NULL, OPTION_NO_PIC}, | |
2922d21d | 3671 | {"mabi", required_argument, NULL, OPTION_MABI}, |
71060565 JW |
3672 | {"mrelax", no_argument, NULL, OPTION_RELAX}, |
3673 | {"mno-relax", no_argument, NULL, OPTION_NO_RELAX}, | |
2dc8dd17 JW |
3674 | {"march-attr", no_argument, NULL, OPTION_ARCH_ATTR}, |
3675 | {"mno-arch-attr", no_argument, NULL, OPTION_NO_ARCH_ATTR}, | |
2ca89224 NC |
3676 | {"mcsr-check", no_argument, NULL, OPTION_CSR_CHECK}, |
3677 | {"mno-csr-check", no_argument, NULL, OPTION_NO_CSR_CHECK}, | |
8f595e9b NC |
3678 | {"misa-spec", required_argument, NULL, OPTION_MISA_SPEC}, |
3679 | {"mpriv-spec", required_argument, NULL, OPTION_MPRIV_SPEC}, | |
fbc09e7a MC |
3680 | {"mbig-endian", no_argument, NULL, OPTION_BIG_ENDIAN}, |
3681 | {"mlittle-endian", no_argument, NULL, OPTION_LITTLE_ENDIAN}, | |
e23eba97 NC |
3682 | |
3683 | {NULL, no_argument, NULL, 0} | |
3684 | }; | |
3685 | size_t md_longopts_size = sizeof (md_longopts); | |
3686 | ||
e23eba97 NC |
3687 | int |
3688 | md_parse_option (int c, const char *arg) | |
3689 | { | |
3690 | switch (c) | |
3691 | { | |
e23eba97 | 3692 | case OPTION_MARCH: |
8f595e9b | 3693 | default_arch_with_ext = arg; |
e23eba97 NC |
3694 | break; |
3695 | ||
3696 | case OPTION_NO_PIC: | |
5b7c81bd | 3697 | riscv_opts.pic = false; |
e23eba97 NC |
3698 | break; |
3699 | ||
3700 | case OPTION_PIC: | |
5b7c81bd | 3701 | riscv_opts.pic = true; |
e23eba97 NC |
3702 | break; |
3703 | ||
2922d21d AW |
3704 | case OPTION_MABI: |
3705 | if (strcmp (arg, "ilp32") == 0) | |
5b7c81bd | 3706 | riscv_set_abi (32, FLOAT_ABI_SOFT, false); |
7f999549 | 3707 | else if (strcmp (arg, "ilp32e") == 0) |
5b7c81bd | 3708 | riscv_set_abi (32, FLOAT_ABI_SOFT, true); |
2922d21d | 3709 | else if (strcmp (arg, "ilp32f") == 0) |
5b7c81bd | 3710 | riscv_set_abi (32, FLOAT_ABI_SINGLE, false); |
2922d21d | 3711 | else if (strcmp (arg, "ilp32d") == 0) |
5b7c81bd | 3712 | riscv_set_abi (32, FLOAT_ABI_DOUBLE, false); |
2922d21d | 3713 | else if (strcmp (arg, "ilp32q") == 0) |
5b7c81bd | 3714 | riscv_set_abi (32, FLOAT_ABI_QUAD, false); |
2922d21d | 3715 | else if (strcmp (arg, "lp64") == 0) |
5b7c81bd | 3716 | riscv_set_abi (64, FLOAT_ABI_SOFT, false); |
2922d21d | 3717 | else if (strcmp (arg, "lp64f") == 0) |
5b7c81bd | 3718 | riscv_set_abi (64, FLOAT_ABI_SINGLE, false); |
2922d21d | 3719 | else if (strcmp (arg, "lp64d") == 0) |
5b7c81bd | 3720 | riscv_set_abi (64, FLOAT_ABI_DOUBLE, false); |
2922d21d | 3721 | else if (strcmp (arg, "lp64q") == 0) |
5b7c81bd | 3722 | riscv_set_abi (64, FLOAT_ABI_QUAD, false); |
2922d21d AW |
3723 | else |
3724 | return 0; | |
5b7c81bd | 3725 | explicit_mabi = true; |
2922d21d AW |
3726 | break; |
3727 | ||
71060565 | 3728 | case OPTION_RELAX: |
5b7c81bd | 3729 | riscv_opts.relax = true; |
71060565 JW |
3730 | break; |
3731 | ||
3732 | case OPTION_NO_RELAX: | |
5b7c81bd | 3733 | riscv_opts.relax = false; |
71060565 JW |
3734 | break; |
3735 | ||
2dc8dd17 | 3736 | case OPTION_ARCH_ATTR: |
5b7c81bd | 3737 | riscv_opts.arch_attr = true; |
2dc8dd17 JW |
3738 | break; |
3739 | ||
3740 | case OPTION_NO_ARCH_ATTR: | |
5b7c81bd | 3741 | riscv_opts.arch_attr = false; |
2dc8dd17 JW |
3742 | break; |
3743 | ||
2ca89224 | 3744 | case OPTION_CSR_CHECK: |
5b7c81bd | 3745 | riscv_opts.csr_check = true; |
2ca89224 NC |
3746 | break; |
3747 | ||
3748 | case OPTION_NO_CSR_CHECK: | |
5b7c81bd | 3749 | riscv_opts.csr_check = false; |
2ca89224 NC |
3750 | break; |
3751 | ||
8f595e9b NC |
3752 | case OPTION_MISA_SPEC: |
3753 | return riscv_set_default_isa_spec (arg); | |
3754 | ||
3755 | case OPTION_MPRIV_SPEC: | |
3756 | return riscv_set_default_priv_spec (arg); | |
3757 | ||
fbc09e7a MC |
3758 | case OPTION_BIG_ENDIAN: |
3759 | target_big_endian = 1; | |
3760 | break; | |
3761 | ||
3762 | case OPTION_LITTLE_ENDIAN: | |
3763 | target_big_endian = 0; | |
3764 | break; | |
3765 | ||
e23eba97 NC |
3766 | default: |
3767 | return 0; | |
3768 | } | |
3769 | ||
3770 | return 1; | |
3771 | } | |
3772 | ||
3773 | void | |
3774 | riscv_after_parse_args (void) | |
3775 | { | |
dcd709e0 NC |
3776 | /* The --with-arch is optional for now, so we still need to set the xlen |
3777 | according to the default_arch, which is set by the --target. */ | |
e23eba97 NC |
3778 | if (xlen == 0) |
3779 | { | |
3780 | if (strcmp (default_arch, "riscv32") == 0) | |
3781 | xlen = 32; | |
3782 | else if (strcmp (default_arch, "riscv64") == 0) | |
3783 | xlen = 64; | |
3784 | else | |
3785 | as_bad ("unknown default architecture `%s'", default_arch); | |
3786 | } | |
8f595e9b | 3787 | |
dcd709e0 | 3788 | /* Set default specs. */ |
8f595e9b NC |
3789 | if (default_isa_spec == ISA_SPEC_CLASS_NONE) |
3790 | riscv_set_default_isa_spec (DEFAULT_RISCV_ISA_SPEC); | |
dcd709e0 NC |
3791 | if (default_priv_spec == PRIV_SPEC_CLASS_NONE) |
3792 | riscv_set_default_priv_spec (DEFAULT_RISCV_PRIV_SPEC); | |
2922d21d | 3793 | |
8f595e9b | 3794 | riscv_set_arch (default_arch_with_ext); |
2922d21d | 3795 | |
0ac2b354 AB |
3796 | /* If the CIE to be produced has not been overridden on the command line, |
3797 | then produce version 3 by default. This allows us to use the full | |
3798 | range of registers in a .cfi_return_column directive. */ | |
3799 | if (flag_dwarf_cie_version == -1) | |
3800 | flag_dwarf_cie_version = 3; | |
e23eba97 NC |
3801 | } |
3802 | ||
3803 | long | |
3804 | md_pcrel_from (fixS *fixP) | |
3805 | { | |
3806 | return fixP->fx_where + fixP->fx_frag->fr_address; | |
3807 | } | |
3808 | ||
3809 | /* Apply a fixup to the object file. */ | |
3810 | ||
3811 | void | |
3812 | md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) | |
3813 | { | |
45f76423 | 3814 | unsigned int subtype; |
e23eba97 | 3815 | bfd_byte *buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where); |
5b7c81bd | 3816 | bool relaxable = false; |
c1b465c9 | 3817 | offsetT loc; |
a6cbf936 | 3818 | segT sub_segment; |
e23eba97 NC |
3819 | |
3820 | /* Remember value for tc_gen_reloc. */ | |
3821 | fixP->fx_addnumber = *valP; | |
3822 | ||
3823 | switch (fixP->fx_r_type) | |
3824 | { | |
e23eba97 NC |
3825 | case BFD_RELOC_RISCV_HI20: |
3826 | case BFD_RELOC_RISCV_LO12_I: | |
3827 | case BFD_RELOC_RISCV_LO12_S: | |
45f76423 AW |
3828 | bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP) |
3829 | | bfd_getl32 (buf), buf); | |
a5ec5e3f | 3830 | if (fixP->fx_addsy == NULL) |
5b7c81bd AM |
3831 | fixP->fx_done = true; |
3832 | relaxable = true; | |
45f76423 AW |
3833 | break; |
3834 | ||
3835 | case BFD_RELOC_RISCV_GOT_HI20: | |
e23eba97 NC |
3836 | case BFD_RELOC_RISCV_ADD8: |
3837 | case BFD_RELOC_RISCV_ADD16: | |
3838 | case BFD_RELOC_RISCV_ADD32: | |
3839 | case BFD_RELOC_RISCV_ADD64: | |
45f76423 | 3840 | case BFD_RELOC_RISCV_SUB6: |
e23eba97 NC |
3841 | case BFD_RELOC_RISCV_SUB8: |
3842 | case BFD_RELOC_RISCV_SUB16: | |
3843 | case BFD_RELOC_RISCV_SUB32: | |
3844 | case BFD_RELOC_RISCV_SUB64: | |
45f76423 AW |
3845 | case BFD_RELOC_RISCV_RELAX: |
3846 | break; | |
3847 | ||
3848 | case BFD_RELOC_RISCV_TPREL_HI20: | |
3849 | case BFD_RELOC_RISCV_TPREL_LO12_I: | |
3850 | case BFD_RELOC_RISCV_TPREL_LO12_S: | |
3851 | case BFD_RELOC_RISCV_TPREL_ADD: | |
5b7c81bd | 3852 | relaxable = true; |
45f76423 AW |
3853 | /* Fall through. */ |
3854 | ||
3855 | case BFD_RELOC_RISCV_TLS_GOT_HI20: | |
3856 | case BFD_RELOC_RISCV_TLS_GD_HI20: | |
3857 | case BFD_RELOC_RISCV_TLS_DTPREL32: | |
3858 | case BFD_RELOC_RISCV_TLS_DTPREL64: | |
e294484e AW |
3859 | if (fixP->fx_addsy != NULL) |
3860 | S_SET_THREAD_LOCAL (fixP->fx_addsy); | |
3861 | else | |
3862 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
3863 | _("TLS relocation against a constant")); | |
e23eba97 NC |
3864 | break; |
3865 | ||
e23eba97 | 3866 | case BFD_RELOC_32: |
a6cbf936 KLC |
3867 | /* Use pc-relative relocation for FDE initial location. |
3868 | The symbol address in .eh_frame may be adjusted in | |
3869 | _bfd_elf_discard_section_eh_frame, and the content of | |
3870 | .eh_frame will be adjusted in _bfd_elf_write_section_eh_frame. | |
3871 | Therefore, we cannot insert a relocation whose addend symbol is | |
dcd709e0 | 3872 | in .eh_frame. Othrewise, the value may be adjusted twice. */ |
a6cbf936 KLC |
3873 | if (fixP->fx_addsy && fixP->fx_subsy |
3874 | && (sub_segment = S_GET_SEGMENT (fixP->fx_subsy)) | |
3875 | && strcmp (sub_segment->name, ".eh_frame") == 0 | |
3876 | && S_GET_VALUE (fixP->fx_subsy) | |
3877 | == fixP->fx_frag->fr_address + fixP->fx_where) | |
3878 | { | |
3879 | fixP->fx_r_type = BFD_RELOC_RISCV_32_PCREL; | |
3880 | fixP->fx_subsy = NULL; | |
3881 | break; | |
3882 | } | |
3883 | /* Fall through. */ | |
3884 | case BFD_RELOC_64: | |
e23eba97 NC |
3885 | case BFD_RELOC_16: |
3886 | case BFD_RELOC_8: | |
45f76423 | 3887 | case BFD_RELOC_RISCV_CFA: |
e23eba97 NC |
3888 | if (fixP->fx_addsy && fixP->fx_subsy) |
3889 | { | |
3890 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
3891 | fixP->fx_next->fx_addsy = fixP->fx_subsy; | |
3892 | fixP->fx_next->fx_subsy = NULL; | |
3893 | fixP->fx_next->fx_offset = 0; | |
3894 | fixP->fx_subsy = NULL; | |
3895 | ||
3896 | switch (fixP->fx_r_type) | |
3897 | { | |
3898 | case BFD_RELOC_64: | |
3899 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD64; | |
3900 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB64; | |
3901 | break; | |
3902 | ||
3903 | case BFD_RELOC_32: | |
3904 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD32; | |
3905 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
3906 | break; | |
3907 | ||
3908 | case BFD_RELOC_16: | |
3909 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD16; | |
3910 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
3911 | break; | |
3912 | ||
3913 | case BFD_RELOC_8: | |
3914 | fixP->fx_r_type = BFD_RELOC_RISCV_ADD8; | |
3915 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
073808ed | 3916 | break; |
e23eba97 | 3917 | |
45f76423 AW |
3918 | case BFD_RELOC_RISCV_CFA: |
3919 | /* Load the byte to get the subtype. */ | |
c1b465c9 KLC |
3920 | subtype = bfd_get_8 (NULL, &((fragS *) (fixP->fx_frag->fr_opcode))->fr_literal[fixP->fx_where]); |
3921 | loc = fixP->fx_frag->fr_fix - (subtype & 7); | |
45f76423 AW |
3922 | switch (subtype) |
3923 | { | |
3924 | case DW_CFA_advance_loc1: | |
c1b465c9 KLC |
3925 | fixP->fx_where = loc + 1; |
3926 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
3927 | fixP->fx_r_type = BFD_RELOC_RISCV_SET8; |
3928 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB8; | |
3929 | break; | |
3930 | ||
3931 | case DW_CFA_advance_loc2: | |
3932 | fixP->fx_size = 2; | |
45f76423 | 3933 | fixP->fx_next->fx_size = 2; |
c1b465c9 KLC |
3934 | fixP->fx_where = loc + 1; |
3935 | fixP->fx_next->fx_where = loc + 1; | |
45f76423 AW |
3936 | fixP->fx_r_type = BFD_RELOC_RISCV_SET16; |
3937 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB16; | |
3938 | break; | |
3939 | ||
3940 | case DW_CFA_advance_loc4: | |
3941 | fixP->fx_size = 4; | |
45f76423 | 3942 | fixP->fx_next->fx_size = 4; |
c1b465c9 KLC |
3943 | fixP->fx_where = loc; |
3944 | fixP->fx_next->fx_where = loc; | |
45f76423 AW |
3945 | fixP->fx_r_type = BFD_RELOC_RISCV_SET32; |
3946 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB32; | |
3947 | break; | |
3948 | ||
3949 | default: | |
3950 | if (subtype < 0x80 && (subtype & 0x40)) | |
3951 | { | |
3952 | /* DW_CFA_advance_loc */ | |
2aece2ba KLC |
3953 | fixP->fx_frag = (fragS *) fixP->fx_frag->fr_opcode; |
3954 | fixP->fx_next->fx_frag = fixP->fx_frag; | |
45f76423 AW |
3955 | fixP->fx_r_type = BFD_RELOC_RISCV_SET6; |
3956 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_SUB6; | |
3957 | } | |
3958 | else | |
b800637e | 3959 | as_fatal (_("internal: bad CFA value #%d"), subtype); |
45f76423 AW |
3960 | break; |
3961 | } | |
3962 | break; | |
3963 | ||
e23eba97 NC |
3964 | default: |
3965 | /* This case is unreachable. */ | |
3966 | abort (); | |
3967 | } | |
3968 | } | |
3969 | /* Fall through. */ | |
3970 | ||
3971 | case BFD_RELOC_RVA: | |
3972 | /* If we are deleting this reloc entry, we must fill in the | |
3973 | value now. This can happen if we have a .word which is not | |
3974 | resolved when it appears but is later defined. */ | |
3975 | if (fixP->fx_addsy == NULL) | |
3976 | { | |
3977 | gas_assert (fixP->fx_size <= sizeof (valueT)); | |
3978 | md_number_to_chars ((char *) buf, *valP, fixP->fx_size); | |
3979 | fixP->fx_done = 1; | |
3980 | } | |
3981 | break; | |
3982 | ||
3983 | case BFD_RELOC_RISCV_JMP: | |
3984 | if (fixP->fx_addsy) | |
3985 | { | |
3986 | /* Fill in a tentative value to improve objdump readability. */ | |
3987 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
3988 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 3989 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_JTYPE_IMM (delta), buf); |
e23eba97 NC |
3990 | } |
3991 | break; | |
3992 | ||
3993 | case BFD_RELOC_12_PCREL: | |
3994 | if (fixP->fx_addsy) | |
3995 | { | |
3996 | /* Fill in a tentative value to improve objdump readability. */ | |
3997 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
3998 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 3999 | bfd_putl32 (bfd_getl32 (buf) | ENCODE_BTYPE_IMM (delta), buf); |
e23eba97 NC |
4000 | } |
4001 | break; | |
4002 | ||
4003 | case BFD_RELOC_RISCV_RVC_BRANCH: | |
4004 | if (fixP->fx_addsy) | |
4005 | { | |
4006 | /* Fill in a tentative value to improve objdump readability. */ | |
4007 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4008 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4009 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_CBTYPE_IMM (delta), buf); |
e23eba97 NC |
4010 | } |
4011 | break; | |
4012 | ||
4013 | case BFD_RELOC_RISCV_RVC_JUMP: | |
4014 | if (fixP->fx_addsy) | |
4015 | { | |
4016 | /* Fill in a tentative value to improve objdump readability. */ | |
4017 | bfd_vma target = S_GET_VALUE (fixP->fx_addsy) + *valP; | |
4018 | bfd_vma delta = target - md_pcrel_from (fixP); | |
5a9f5403 | 4019 | bfd_putl16 (bfd_getl16 (buf) | ENCODE_CJTYPE_IMM (delta), buf); |
e23eba97 NC |
4020 | } |
4021 | break; | |
4022 | ||
e23eba97 NC |
4023 | case BFD_RELOC_RISCV_CALL: |
4024 | case BFD_RELOC_RISCV_CALL_PLT: | |
5b7c81bd | 4025 | relaxable = true; |
45f76423 AW |
4026 | break; |
4027 | ||
9d06997a | 4028 | case BFD_RELOC_RISCV_PCREL_HI20: |
45f76423 AW |
4029 | case BFD_RELOC_RISCV_PCREL_LO12_S: |
4030 | case BFD_RELOC_RISCV_PCREL_LO12_I: | |
9d06997a PD |
4031 | relaxable = riscv_opts.relax; |
4032 | break; | |
4033 | ||
e23eba97 NC |
4034 | case BFD_RELOC_RISCV_ALIGN: |
4035 | break; | |
4036 | ||
4037 | default: | |
4038 | /* We ignore generic BFD relocations we don't know about. */ | |
4039 | if (bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type) != NULL) | |
b800637e | 4040 | as_fatal (_("internal: bad relocation #%d"), fixP->fx_r_type); |
e23eba97 | 4041 | } |
45f76423 | 4042 | |
e294484e | 4043 | if (fixP->fx_subsy != NULL) |
4bf09429 | 4044 | as_bad_subtract (fixP); |
e294484e | 4045 | |
45f76423 AW |
4046 | /* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */ |
4047 | if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL) | |
4048 | { | |
4049 | fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP)); | |
4050 | fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL; | |
4051 | fixP->fx_next->fx_r_type = BFD_RELOC_RISCV_RELAX; | |
b1b11e92 | 4052 | fixP->fx_next->fx_size = 0; |
45f76423 AW |
4053 | } |
4054 | } | |
4055 | ||
4056 | /* Because the value of .cfi_remember_state may changed after relaxation, | |
4057 | we insert a fix to relocate it again in link-time. */ | |
4058 | ||
4059 | void | |
4060 | riscv_pre_output_hook (void) | |
4061 | { | |
4062 | const frchainS *frch; | |
72393fd1 JW |
4063 | segT s; |
4064 | ||
4065 | /* Save the current segment info. */ | |
4066 | segT seg = now_seg; | |
4067 | subsegT subseg = now_subseg; | |
45f76423 AW |
4068 | |
4069 | for (s = stdoutput->sections; s; s = s->next) | |
4070 | for (frch = seg_info (s)->frchainP; frch; frch = frch->frch_next) | |
4071 | { | |
7cb7b948 | 4072 | fragS *frag; |
45f76423 AW |
4073 | |
4074 | for (frag = frch->frch_root; frag; frag = frag->fr_next) | |
4075 | { | |
4076 | if (frag->fr_type == rs_cfa) | |
4077 | { | |
45f76423 | 4078 | expressionS exp; |
8d1015a8 | 4079 | expressionS *symval; |
45f76423 | 4080 | |
8d1015a8 | 4081 | symval = symbol_get_value_expression (frag->fr_symbol); |
45f76423 | 4082 | exp.X_op = O_subtract; |
8d1015a8 | 4083 | exp.X_add_symbol = symval->X_add_symbol; |
45f76423 | 4084 | exp.X_add_number = 0; |
8d1015a8 | 4085 | exp.X_op_symbol = symval->X_op_symbol; |
45f76423 | 4086 | |
72393fd1 JW |
4087 | /* We must set the segment before creating a frag after all |
4088 | frag chains have been chained together. */ | |
4089 | subseg_set (s, frch->frch_subseg); | |
4090 | ||
c1b465c9 | 4091 | fix_new_exp (frag, (int) frag->fr_offset, 1, &exp, 0, |
45f76423 AW |
4092 | BFD_RELOC_RISCV_CFA); |
4093 | } | |
4094 | } | |
4095 | } | |
72393fd1 JW |
4096 | |
4097 | /* Restore the original segment info. */ | |
4098 | subseg_set (seg, subseg); | |
e23eba97 NC |
4099 | } |
4100 | ||
e23eba97 NC |
4101 | /* Handle the .option pseudo-op. */ |
4102 | ||
4103 | static void | |
4104 | s_riscv_option (int x ATTRIBUTE_UNUSED) | |
4105 | { | |
4106 | char *name = input_line_pointer, ch; | |
4107 | ||
4108 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4109 | ++input_line_pointer; | |
4110 | ch = *input_line_pointer; | |
4111 | *input_line_pointer = '\0'; | |
4112 | ||
4113 | if (strcmp (name, "rvc") == 0) | |
edc77c59 | 4114 | { |
d3ffd7f7 | 4115 | riscv_update_subset (&riscv_rps_as, "+c"); |
40f1a1a4 | 4116 | riscv_reset_subsets_list_arch_str (); |
edc77c59 NC |
4117 | riscv_set_rvc (true); |
4118 | } | |
e23eba97 | 4119 | else if (strcmp (name, "norvc") == 0) |
edc77c59 | 4120 | { |
d3ffd7f7 | 4121 | riscv_update_subset (&riscv_rps_as, "-c"); |
40f1a1a4 | 4122 | riscv_reset_subsets_list_arch_str (); |
edc77c59 NC |
4123 | riscv_set_rvc (false); |
4124 | } | |
e23eba97 | 4125 | else if (strcmp (name, "pic") == 0) |
5b7c81bd | 4126 | riscv_opts.pic = true; |
e23eba97 | 4127 | else if (strcmp (name, "nopic") == 0) |
5b7c81bd | 4128 | riscv_opts.pic = false; |
45f76423 | 4129 | else if (strcmp (name, "relax") == 0) |
5b7c81bd | 4130 | riscv_opts.relax = true; |
45f76423 | 4131 | else if (strcmp (name, "norelax") == 0) |
5b7c81bd | 4132 | riscv_opts.relax = false; |
2ca89224 | 4133 | else if (strcmp (name, "csr-check") == 0) |
5b7c81bd | 4134 | riscv_opts.csr_check = true; |
2ca89224 | 4135 | else if (strcmp (name, "no-csr-check") == 0) |
5b7c81bd | 4136 | riscv_opts.csr_check = false; |
d3ffd7f7 NC |
4137 | else if (strncmp (name, "arch,", 5) == 0) |
4138 | { | |
4139 | name += 5; | |
4140 | if (ISSPACE (*name) && *name != '\0') | |
4141 | name++; | |
4142 | riscv_update_subset (&riscv_rps_as, name); | |
40f1a1a4 | 4143 | riscv_reset_subsets_list_arch_str (); |
e7e599a1 NC |
4144 | |
4145 | riscv_set_rvc (false); | |
4146 | if (riscv_subset_supports (&riscv_rps_as, "c")) | |
4147 | riscv_set_rvc (true); | |
acab2a68 TO |
4148 | |
4149 | if (riscv_subset_supports (&riscv_rps_as, "ztso")) | |
4150 | riscv_set_tso (); | |
d3ffd7f7 | 4151 | } |
e23eba97 NC |
4152 | else if (strcmp (name, "push") == 0) |
4153 | { | |
4154 | struct riscv_option_stack *s; | |
4155 | ||
d3ffd7f7 | 4156 | s = XNEW (struct riscv_option_stack); |
e23eba97 NC |
4157 | s->next = riscv_opts_stack; |
4158 | s->options = riscv_opts; | |
f5cb31a8 | 4159 | s->subset_list = riscv_rps_as.subset_list; |
e23eba97 | 4160 | riscv_opts_stack = s; |
f5cb31a8 | 4161 | riscv_rps_as.subset_list = riscv_copy_subset_list (s->subset_list); |
e23eba97 NC |
4162 | } |
4163 | else if (strcmp (name, "pop") == 0) | |
4164 | { | |
4165 | struct riscv_option_stack *s; | |
4166 | ||
4167 | s = riscv_opts_stack; | |
4168 | if (s == NULL) | |
4169 | as_bad (_(".option pop with no .option push")); | |
4170 | else | |
4171 | { | |
f5cb31a8 | 4172 | riscv_subset_list_t *release_subsets = riscv_rps_as.subset_list; |
e23eba97 | 4173 | riscv_opts_stack = s->next; |
d3ffd7f7 | 4174 | riscv_opts = s->options; |
f5cb31a8 | 4175 | riscv_rps_as.subset_list = s->subset_list; |
d3ffd7f7 | 4176 | riscv_release_subset_list (release_subsets); |
e23eba97 NC |
4177 | free (s); |
4178 | } | |
4179 | } | |
4180 | else | |
4181 | { | |
c84b3d7e | 4182 | as_warn (_("unrecognized .option directive: %s"), name); |
e23eba97 NC |
4183 | } |
4184 | *input_line_pointer = ch; | |
4185 | demand_empty_rest_of_line (); | |
4186 | } | |
4187 | ||
4188 | /* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate | |
4189 | a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for | |
4190 | use in DWARF debug information. */ | |
4191 | ||
4192 | static void | |
4193 | s_dtprel (int bytes) | |
4194 | { | |
4195 | expressionS ex; | |
4196 | char *p; | |
4197 | ||
4198 | expression (&ex); | |
4199 | ||
4200 | if (ex.X_op != O_symbol) | |
4201 | { | |
b800637e | 4202 | as_bad (_("unsupported use of %s"), (bytes == 8 |
e23eba97 NC |
4203 | ? ".dtpreldword" |
4204 | : ".dtprelword")); | |
4205 | ignore_rest_of_line (); | |
4206 | } | |
4207 | ||
4208 | p = frag_more (bytes); | |
4209 | md_number_to_chars (p, 0, bytes); | |
5b7c81bd | 4210 | fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, false, |
e23eba97 NC |
4211 | (bytes == 8 |
4212 | ? BFD_RELOC_RISCV_TLS_DTPREL64 | |
4213 | : BFD_RELOC_RISCV_TLS_DTPREL32)); | |
4214 | ||
4215 | demand_empty_rest_of_line (); | |
4216 | } | |
4217 | ||
4218 | /* Handle the .bss pseudo-op. */ | |
4219 | ||
4220 | static void | |
4221 | s_bss (int ignore ATTRIBUTE_UNUSED) | |
4222 | { | |
4223 | subseg_set (bss_section, 0); | |
4224 | demand_empty_rest_of_line (); | |
4225 | } | |
4226 | ||
e23eba97 | 4227 | static void |
d115ab8e | 4228 | riscv_make_nops (char *buf, bfd_vma bytes) |
e23eba97 | 4229 | { |
d115ab8e | 4230 | bfd_vma i = 0; |
e23eba97 | 4231 | |
e5b737de AW |
4232 | /* RISC-V instructions cannot begin or end on odd addresses, so this case |
4233 | means we are not within a valid instruction sequence. It is thus safe | |
4234 | to use a zero byte, even though that is not a valid instruction. */ | |
4235 | if (bytes % 2 == 1) | |
4236 | buf[i++] = 0; | |
4237 | ||
4238 | /* Use at most one 2-byte NOP. */ | |
4239 | if ((bytes - i) % 4 == 2) | |
e23eba97 | 4240 | { |
fbc09e7a | 4241 | number_to_chars_littleendian (buf + i, RVC_NOP, 2); |
d115ab8e | 4242 | i += 2; |
e23eba97 NC |
4243 | } |
4244 | ||
e5b737de | 4245 | /* Fill the remainder with 4-byte NOPs. */ |
d115ab8e | 4246 | for ( ; i < bytes; i += 4) |
fbc09e7a | 4247 | number_to_chars_littleendian (buf + i, RISCV_NOP, 4); |
d115ab8e | 4248 | } |
e23eba97 | 4249 | |
d115ab8e AW |
4250 | /* Called from md_do_align. Used to create an alignment frag in a |
4251 | code section by emitting a worst-case NOP sequence that the linker | |
4252 | will later relax to the correct number of NOPs. We can't compute | |
4253 | the correct alignment now because of other linker relaxations. */ | |
4254 | ||
5b7c81bd | 4255 | bool |
d115ab8e AW |
4256 | riscv_frag_align_code (int n) |
4257 | { | |
e5b737de | 4258 | bfd_vma bytes = (bfd_vma) 1 << n; |
36877bfb JW |
4259 | bfd_vma insn_alignment = riscv_opts.rvc ? 2 : 4; |
4260 | bfd_vma worst_case_bytes = bytes - insn_alignment; | |
4261 | char *nops; | |
ed0816bd | 4262 | expressionS ex; |
d115ab8e | 4263 | |
36877bfb JW |
4264 | /* If we are moving to a smaller alignment than the instruction size, then no |
4265 | alignment is required. */ | |
4266 | if (bytes <= insn_alignment) | |
5b7c81bd | 4267 | return true; |
36877bfb | 4268 | |
d115ab8e AW |
4269 | /* When not relaxing, riscv_handle_align handles code alignment. */ |
4270 | if (!riscv_opts.relax) | |
5b7c81bd | 4271 | return false; |
e23eba97 | 4272 | |
40f1a1a4 NC |
4273 | /* Maybe we should use frag_var to create a new rs_align_code fragment, |
4274 | rather than just use frag_more to handle an alignment here? So that we | |
4275 | don't need to call riscv_mapping_state again later, and then only need | |
4276 | to check frag->fr_type to see if it is frag_align_code. */ | |
e80ae190 JW |
4277 | nops = frag_more (worst_case_bytes); |
4278 | ||
ed0816bd PD |
4279 | ex.X_op = O_constant; |
4280 | ex.X_add_number = worst_case_bytes; | |
d115ab8e | 4281 | |
ed0816bd | 4282 | riscv_make_nops (nops, worst_case_bytes); |
e23eba97 | 4283 | |
ed0816bd | 4284 | fix_new_exp (frag_now, nops - frag_now->fr_literal, 0, |
5b7c81bd | 4285 | &ex, false, BFD_RELOC_RISCV_ALIGN); |
e23eba97 | 4286 | |
3190ebcb | 4287 | riscv_mapping_state (MAP_INSN, worst_case_bytes, true/* fr_align_code */); |
9b9b1092 | 4288 | |
cb2562f5 LX |
4289 | /* We need to start a new frag after the alignment which may be removed by |
4290 | the linker, to prevent the assembler from computing static offsets. | |
4291 | This is necessary to get correct EH info. */ | |
4292 | frag_wane (frag_now); | |
4293 | frag_new (0); | |
4294 | ||
5b7c81bd | 4295 | return true; |
d115ab8e | 4296 | } |
e23eba97 | 4297 | |
d115ab8e AW |
4298 | /* Implement HANDLE_ALIGN. */ |
4299 | ||
4300 | void | |
4301 | riscv_handle_align (fragS *fragP) | |
4302 | { | |
4303 | switch (fragP->fr_type) | |
4304 | { | |
4305 | case rs_align_code: | |
4306 | /* When relaxing, riscv_frag_align_code handles code alignment. */ | |
4307 | if (!riscv_opts.relax) | |
4308 | { | |
e80ae190 JW |
4309 | bfd_signed_vma bytes = (fragP->fr_next->fr_address |
4310 | - fragP->fr_address - fragP->fr_fix); | |
4311 | /* We have 4 byte uncompressed nops. */ | |
4312 | bfd_signed_vma size = 4; | |
4313 | bfd_signed_vma excess = bytes % size; | |
9b9b1092 | 4314 | bfd_boolean odd_padding = (excess % 2 == 1); |
e80ae190 JW |
4315 | char *p = fragP->fr_literal + fragP->fr_fix; |
4316 | ||
4317 | if (bytes <= 0) | |
d115ab8e AW |
4318 | break; |
4319 | ||
e80ae190 JW |
4320 | /* Insert zeros or compressed nops to get 4 byte alignment. */ |
4321 | if (excess) | |
4322 | { | |
9b9b1092 NC |
4323 | if (odd_padding) |
4324 | riscv_add_odd_padding_symbol (fragP); | |
e80ae190 JW |
4325 | riscv_make_nops (p, excess); |
4326 | fragP->fr_fix += excess; | |
4327 | p += excess; | |
4328 | } | |
4329 | ||
9b9b1092 NC |
4330 | /* The frag will be changed to `rs_fill` later. The function |
4331 | `write_contents` will try to fill the remaining spaces | |
4332 | according to the patterns we give. In this case, we give | |
4333 | a 4 byte uncompressed nop as the pattern, and set the size | |
4334 | of the pattern into `fr_var`. The nop will be output to the | |
4335 | file `fr_offset` times. However, `fr_offset` could be zero | |
4336 | if we don't need to pad the boundary finally. */ | |
e80ae190 JW |
4337 | riscv_make_nops (p, size); |
4338 | fragP->fr_var = size; | |
d115ab8e AW |
4339 | } |
4340 | break; | |
4341 | ||
4342 | default: | |
4343 | break; | |
4344 | } | |
e23eba97 NC |
4345 | } |
4346 | ||
9b9b1092 NC |
4347 | /* This usually called from frag_var. */ |
4348 | ||
4349 | void | |
4350 | riscv_init_frag (fragS * fragP, int max_chars) | |
4351 | { | |
4352 | /* Do not add mapping symbol to debug sections. */ | |
4353 | if (bfd_section_flags (now_seg) & SEC_DEBUGGING) | |
4354 | return; | |
4355 | ||
4356 | switch (fragP->fr_type) | |
4357 | { | |
4358 | case rs_fill: | |
4359 | case rs_align: | |
4360 | case rs_align_test: | |
3190ebcb | 4361 | riscv_mapping_state (MAP_DATA, max_chars, false/* fr_align_code */); |
9b9b1092 NC |
4362 | break; |
4363 | case rs_align_code: | |
3190ebcb | 4364 | riscv_mapping_state (MAP_INSN, max_chars, true/* fr_align_code */); |
9b9b1092 NC |
4365 | break; |
4366 | default: | |
4367 | break; | |
4368 | } | |
4369 | } | |
4370 | ||
e23eba97 NC |
4371 | int |
4372 | md_estimate_size_before_relax (fragS *fragp, asection *segtype) | |
4373 | { | |
5b7c81bd | 4374 | return (fragp->fr_var = relaxed_branch_length (fragp, segtype, false)); |
e23eba97 NC |
4375 | } |
4376 | ||
4377 | /* Translate internal representation of relocation info to BFD target | |
4378 | format. */ | |
4379 | ||
4380 | arelent * | |
4381 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) | |
4382 | { | |
4383 | arelent *reloc = (arelent *) xmalloc (sizeof (arelent)); | |
4384 | ||
4385 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
4386 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
4387 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
4388 | reloc->addend = fixp->fx_addnumber; | |
4389 | ||
4390 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); | |
4391 | if (reloc->howto == NULL) | |
4392 | { | |
4393 | if ((fixp->fx_r_type == BFD_RELOC_16 || fixp->fx_r_type == BFD_RELOC_8) | |
4394 | && fixp->fx_addsy != NULL && fixp->fx_subsy != NULL) | |
4395 | { | |
4396 | /* We don't have R_RISCV_8/16, but for this special case, | |
4397 | we can use R_RISCV_ADD8/16 with R_RISCV_SUB8/16. */ | |
4398 | return reloc; | |
4399 | } | |
4400 | ||
4401 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
4402 | _("cannot represent %s relocation in object file"), | |
4403 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
4404 | return NULL; | |
4405 | } | |
4406 | ||
4407 | return reloc; | |
4408 | } | |
4409 | ||
4410 | int | |
4411 | riscv_relax_frag (asection *sec, fragS *fragp, long stretch ATTRIBUTE_UNUSED) | |
4412 | { | |
4413 | if (RELAX_BRANCH_P (fragp->fr_subtype)) | |
4414 | { | |
4415 | offsetT old_var = fragp->fr_var; | |
5b7c81bd | 4416 | fragp->fr_var = relaxed_branch_length (fragp, sec, true); |
e23eba97 NC |
4417 | return fragp->fr_var - old_var; |
4418 | } | |
4419 | ||
4420 | return 0; | |
4421 | } | |
4422 | ||
4423 | /* Expand far branches to multi-instruction sequences. */ | |
4424 | ||
4425 | static void | |
4426 | md_convert_frag_branch (fragS *fragp) | |
4427 | { | |
4428 | bfd_byte *buf; | |
4429 | expressionS exp; | |
4430 | fixS *fixp; | |
4431 | insn_t insn; | |
4432 | int rs1, reloc; | |
4433 | ||
4434 | buf = (bfd_byte *)fragp->fr_literal + fragp->fr_fix; | |
4435 | ||
4436 | exp.X_op = O_symbol; | |
4437 | exp.X_add_symbol = fragp->fr_symbol; | |
4438 | exp.X_add_number = fragp->fr_offset; | |
4439 | ||
4440 | gas_assert (fragp->fr_var == RELAX_BRANCH_LENGTH (fragp->fr_subtype)); | |
4441 | ||
4442 | if (RELAX_BRANCH_RVC (fragp->fr_subtype)) | |
4443 | { | |
4444 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
4445 | { | |
4446 | case 8: | |
4447 | case 4: | |
4448 | /* Expand the RVC branch into a RISC-V one. */ | |
4449 | insn = bfd_getl16 (buf); | |
4450 | rs1 = 8 + ((insn >> OP_SH_CRS1S) & OP_MASK_CRS1S); | |
4451 | if ((insn & MASK_C_J) == MATCH_C_J) | |
4452 | insn = MATCH_JAL; | |
4453 | else if ((insn & MASK_C_JAL) == MATCH_C_JAL) | |
4454 | insn = MATCH_JAL | (X_RA << OP_SH_RD); | |
4455 | else if ((insn & MASK_C_BEQZ) == MATCH_C_BEQZ) | |
4456 | insn = MATCH_BEQ | (rs1 << OP_SH_RS1); | |
4457 | else if ((insn & MASK_C_BNEZ) == MATCH_C_BNEZ) | |
4458 | insn = MATCH_BNE | (rs1 << OP_SH_RS1); | |
4459 | else | |
4460 | abort (); | |
4461 | bfd_putl32 (insn, buf); | |
4462 | break; | |
4463 | ||
4464 | case 6: | |
4465 | /* Invert the branch condition. Branch over the jump. */ | |
4466 | insn = bfd_getl16 (buf); | |
4467 | insn ^= MATCH_C_BEQZ ^ MATCH_C_BNEZ; | |
5a9f5403 | 4468 | insn |= ENCODE_CBTYPE_IMM (6); |
e23eba97 NC |
4469 | bfd_putl16 (insn, buf); |
4470 | buf += 2; | |
4471 | goto jump; | |
4472 | ||
4473 | case 2: | |
4474 | /* Just keep the RVC branch. */ | |
4475 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
4476 | ? BFD_RELOC_RISCV_RVC_JUMP : BFD_RELOC_RISCV_RVC_BRANCH; | |
4477 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4478 | 2, &exp, false, reloc); |
e23eba97 NC |
4479 | buf += 2; |
4480 | goto done; | |
4481 | ||
4482 | default: | |
1d65abb5 | 4483 | abort (); |
e23eba97 NC |
4484 | } |
4485 | } | |
4486 | ||
4487 | switch (RELAX_BRANCH_LENGTH (fragp->fr_subtype)) | |
4488 | { | |
4489 | case 8: | |
4490 | gas_assert (!RELAX_BRANCH_UNCOND (fragp->fr_subtype)); | |
4491 | ||
4492 | /* Invert the branch condition. Branch over the jump. */ | |
4493 | insn = bfd_getl32 (buf); | |
4494 | insn ^= MATCH_BEQ ^ MATCH_BNE; | |
5a9f5403 | 4495 | insn |= ENCODE_BTYPE_IMM (8); |
fbc09e7a | 4496 | bfd_putl32 (insn, buf); |
e23eba97 NC |
4497 | buf += 4; |
4498 | ||
dc1e8a47 | 4499 | jump: |
e23eba97 NC |
4500 | /* Jump to the target. */ |
4501 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4502 | 4, &exp, false, BFD_RELOC_RISCV_JMP); |
fbc09e7a | 4503 | bfd_putl32 (MATCH_JAL, buf); |
e23eba97 NC |
4504 | buf += 4; |
4505 | break; | |
4506 | ||
4507 | case 4: | |
4508 | reloc = RELAX_BRANCH_UNCOND (fragp->fr_subtype) | |
4509 | ? BFD_RELOC_RISCV_JMP : BFD_RELOC_12_PCREL; | |
4510 | fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal, | |
5b7c81bd | 4511 | 4, &exp, false, reloc); |
e23eba97 NC |
4512 | buf += 4; |
4513 | break; | |
4514 | ||
4515 | default: | |
4516 | abort (); | |
4517 | } | |
4518 | ||
dc1e8a47 | 4519 | done: |
e23eba97 NC |
4520 | fixp->fx_file = fragp->fr_file; |
4521 | fixp->fx_line = fragp->fr_line; | |
4522 | ||
4523 | gas_assert (buf == (bfd_byte *)fragp->fr_literal | |
4524 | + fragp->fr_fix + fragp->fr_var); | |
4525 | ||
4526 | fragp->fr_fix += fragp->fr_var; | |
4527 | } | |
4528 | ||
4529 | /* Relax a machine dependent frag. This returns the amount by which | |
4530 | the current size of the frag should change. */ | |
4531 | ||
4532 | void | |
4533 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec ATTRIBUTE_UNUSED, | |
4534 | fragS *fragp) | |
4535 | { | |
4536 | gas_assert (RELAX_BRANCH_P (fragp->fr_subtype)); | |
4537 | md_convert_frag_branch (fragp); | |
4538 | } | |
4539 | ||
4540 | void | |
4541 | md_show_usage (FILE *stream) | |
4542 | { | |
4543 | fprintf (stream, _("\ | |
4544 | RISC-V options:\n\ | |
437e2ff1 | 4545 | -fpic or -fPIC generate position-independent code\n\ |
8f595e9b NC |
4546 | -fno-pic don't generate position-independent code (default)\n\ |
4547 | -march=ISA set the RISC-V architecture\n\ | |
4548 | -misa-spec=ISAspec set the RISC-V ISA spec (2.2, 20190608, 20191213)\n\ | |
86d39e66 | 4549 | -mpriv-spec=PRIVspec set the RISC-V privilege spec (1.9.1, 1.10, 1.11, 1.12)\n\ |
8f595e9b NC |
4550 | -mabi=ABI set the RISC-V ABI\n\ |
4551 | -mrelax enable relax (default)\n\ | |
4552 | -mno-relax disable relax\n\ | |
4553 | -march-attr generate RISC-V arch attribute\n\ | |
4554 | -mno-arch-attr don't generate RISC-V arch attribute\n\ | |
437e2ff1 NC |
4555 | -mcsr-check enable the csr ISA and privilege spec version checks\n\ |
4556 | -mno-csr-check disable the csr ISA and privilege spec version checks (default)\n\ | |
4557 | -mbig-endian assemble for big-endian\n\ | |
4558 | -mlittle-endian assemble for little-endian\n\ | |
e23eba97 NC |
4559 | ")); |
4560 | } | |
4561 | ||
4562 | /* Standard calling conventions leave the CFA at SP on entry. */ | |
dcd709e0 | 4563 | |
e23eba97 NC |
4564 | void |
4565 | riscv_cfi_frame_initial_instructions (void) | |
4566 | { | |
4567 | cfi_add_CFA_def_cfa_register (X_SP); | |
4568 | } | |
4569 | ||
4570 | int | |
4571 | tc_riscv_regname_to_dw2regnum (char *regname) | |
4572 | { | |
4573 | int reg; | |
4574 | ||
4575 | if ((reg = reg_lookup_internal (regname, RCLASS_GPR)) >= 0) | |
4576 | return reg; | |
4577 | ||
4578 | if ((reg = reg_lookup_internal (regname, RCLASS_FPR)) >= 0) | |
4579 | return reg + 32; | |
4580 | ||
7b4f2407 TO |
4581 | if ((reg = reg_lookup_internal (regname, RCLASS_VECR)) >= 0) |
4582 | return reg + 96; | |
4583 | ||
4762fe62 AB |
4584 | /* CSRs are numbered 4096 -> 8191. */ |
4585 | if ((reg = reg_lookup_internal (regname, RCLASS_CSR)) >= 0) | |
4586 | return reg + 4096; | |
4587 | ||
e23eba97 NC |
4588 | as_bad (_("unknown register `%s'"), regname); |
4589 | return -1; | |
4590 | } | |
4591 | ||
4592 | void | |
4593 | riscv_elf_final_processing (void) | |
4594 | { | |
6e1605e4 | 4595 | riscv_set_abi_by_arch (); |
40f1a1a4 | 4596 | riscv_release_subset_list (riscv_rps_as.subset_list); |
e23eba97 | 4597 | elf_elfheader (stdoutput)->e_flags |= elf_flags; |
e23eba97 NC |
4598 | } |
4599 | ||
4600 | /* Parse the .sleb128 and .uleb128 pseudos. Only allow constant expressions, | |
4601 | since these directives break relaxation when used with symbol deltas. */ | |
4602 | ||
4603 | static void | |
4604 | s_riscv_leb128 (int sign) | |
4605 | { | |
4606 | expressionS exp; | |
4607 | char *save_in = input_line_pointer; | |
4608 | ||
4609 | expression (&exp); | |
4610 | if (exp.X_op != O_constant) | |
4611 | as_bad (_("non-constant .%cleb128 is not supported"), sign ? 's' : 'u'); | |
4612 | demand_empty_rest_of_line (); | |
4613 | ||
4614 | input_line_pointer = save_in; | |
4615 | return s_leb128 (sign); | |
4616 | } | |
4617 | ||
a262b82f NC |
4618 | /* Parse the .insn directive. There are three formats, |
4619 | Format 1: .insn <type> <operand1>, <operand2>, ... | |
4620 | Format 2: .insn <length>, <value> | |
4621 | Format 3: .insn <value>. */ | |
0e35537d JW |
4622 | |
4623 | static void | |
4624 | s_riscv_insn (int x ATTRIBUTE_UNUSED) | |
4625 | { | |
4626 | char *str = input_line_pointer; | |
4627 | struct riscv_cl_insn insn; | |
4628 | expressionS imm_expr; | |
4629 | bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED; | |
4630 | char save_c; | |
4631 | ||
4632 | while (!is_end_of_line[(unsigned char) *input_line_pointer]) | |
4633 | ++input_line_pointer; | |
4634 | ||
4635 | save_c = *input_line_pointer; | |
4636 | *input_line_pointer = '\0'; | |
4637 | ||
3190ebcb | 4638 | riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */); |
9b9b1092 | 4639 | |
e4028336 | 4640 | struct riscv_ip_error error = riscv_ip (str, &insn, &imm_expr, |
0e35537d | 4641 | &imm_reloc, insn_type_hash); |
e4028336 | 4642 | if (error.msg) |
0e35537d | 4643 | { |
a262b82f | 4644 | char *save_in = input_line_pointer; |
e4028336 | 4645 | error.msg = riscv_ip_hardcode (str, &insn, &imm_expr, error.msg); |
a262b82f | 4646 | input_line_pointer = save_in; |
0e35537d | 4647 | } |
a262b82f | 4648 | |
e4028336 PN |
4649 | if (error.msg) |
4650 | { | |
4651 | if (error.missing_ext) | |
4652 | as_bad ("%s `%s', extension `%s' required", error.msg, error.statement, | |
4653 | error.missing_ext); | |
4654 | else | |
4655 | as_bad ("%s `%s'", error.msg, error.statement); | |
4656 | } | |
634001bb | 4657 | else |
0e35537d JW |
4658 | { |
4659 | gas_assert (insn.insn_mo->pinfo != INSN_MACRO); | |
4660 | append_insn (&insn, &imm_expr, imm_reloc); | |
4661 | } | |
4662 | ||
4663 | *input_line_pointer = save_c; | |
4664 | demand_empty_rest_of_line (); | |
4665 | } | |
4666 | ||
dcd709e0 NC |
4667 | /* Update architecture and privileged elf attributes. If we don't set |
4668 | them, then try to output the default ones. */ | |
2dc8dd17 JW |
4669 | |
4670 | static void | |
8f595e9b | 4671 | riscv_write_out_attrs (void) |
2dc8dd17 | 4672 | { |
8f595e9b | 4673 | const char *arch_str, *priv_str, *p; |
dcd709e0 NC |
4674 | /* versions[0]: major version. |
4675 | versions[1]: minor version. | |
4676 | versions[2]: revision version. */ | |
8f595e9b NC |
4677 | unsigned versions[3] = {0}, number = 0; |
4678 | unsigned int i; | |
2dc8dd17 | 4679 | |
dcd709e0 | 4680 | /* Re-write architecture elf attribute. */ |
40f1a1a4 | 4681 | arch_str = riscv_rps_as.subset_list->arch_str; |
2dc8dd17 | 4682 | bfd_elf_add_proc_attr_string (stdoutput, Tag_RISCV_arch, arch_str); |
8f595e9b NC |
4683 | |
4684 | /* For the file without any instruction, we don't set the default_priv_spec | |
dcd709e0 NC |
4685 | according to the privileged elf attributes since the md_assemble isn't |
4686 | called. */ | |
8f595e9b NC |
4687 | if (!start_assemble |
4688 | && !riscv_set_default_priv_spec (NULL)) | |
4689 | return; | |
4690 | ||
dcd709e0 NC |
4691 | /* If we already have set privileged elf attributes, then no need to do |
4692 | anything. Otherwise, don't generate or update them when no CSR and | |
4693 | privileged instructions are used. */ | |
1a79004f | 4694 | if (!explicit_priv_attr) |
3fc6c3dc NC |
4695 | return; |
4696 | ||
3d73d29e | 4697 | RISCV_GET_PRIV_SPEC_NAME (priv_str, default_priv_spec); |
8f595e9b NC |
4698 | p = priv_str; |
4699 | for (i = 0; *p; ++p) | |
4700 | { | |
4701 | if (*p == '.' && i < 3) | |
4702 | { | |
4703 | versions[i++] = number; | |
4704 | number = 0; | |
4705 | } | |
4706 | else if (ISDIGIT (*p)) | |
4707 | number = (number * 10) + (*p - '0'); | |
4708 | else | |
4709 | { | |
b800637e | 4710 | as_bad (_("internal: bad RISC-V privileged spec (%s)"), priv_str); |
8f595e9b NC |
4711 | return; |
4712 | } | |
4713 | } | |
4714 | versions[i] = number; | |
4715 | ||
dcd709e0 | 4716 | /* Re-write privileged elf attributes. */ |
8f595e9b NC |
4717 | bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec, versions[0]); |
4718 | bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_minor, versions[1]); | |
4719 | bfd_elf_add_proc_attr_int (stdoutput, Tag_RISCV_priv_spec_revision, versions[2]); | |
2dc8dd17 JW |
4720 | } |
4721 | ||
dcd709e0 | 4722 | /* Add the default contents for the .riscv.attributes section. */ |
2dc8dd17 JW |
4723 | |
4724 | static void | |
4725 | riscv_set_public_attributes (void) | |
4726 | { | |
8f595e9b NC |
4727 | if (riscv_opts.arch_attr || explicit_attr) |
4728 | riscv_write_out_attrs (); | |
2dc8dd17 JW |
4729 | } |
4730 | ||
4731 | /* Called after all assembly has been done. */ | |
4732 | ||
4733 | void | |
ed2917de | 4734 | riscv_md_finish (void) |
2dc8dd17 JW |
4735 | { |
4736 | riscv_set_public_attributes (); | |
4737 | } | |
4738 | ||
9b9b1092 NC |
4739 | /* Adjust the symbol table. */ |
4740 | ||
4741 | void | |
4742 | riscv_adjust_symtab (void) | |
4743 | { | |
4744 | bfd_map_over_sections (stdoutput, riscv_check_mapping_symbols, (char *) 0); | |
4745 | elf_adjust_symtab (); | |
4746 | } | |
4747 | ||
2dc8dd17 JW |
4748 | /* Given a symbolic attribute NAME, return the proper integer value. |
4749 | Returns -1 if the attribute is not known. */ | |
4750 | ||
4751 | int | |
4752 | riscv_convert_symbolic_attribute (const char *name) | |
4753 | { | |
4754 | static const struct | |
4755 | { | |
1942a048 NC |
4756 | const char *name; |
4757 | const int tag; | |
2dc8dd17 JW |
4758 | } |
4759 | attribute_table[] = | |
1942a048 NC |
4760 | { |
4761 | /* When you modify this table you should | |
4762 | also modify the list in doc/c-riscv.texi. */ | |
4763 | #define T(tag) {#tag, Tag_RISCV_##tag}, {"Tag_RISCV_" #tag, Tag_RISCV_##tag} | |
4764 | T(arch), | |
4765 | T(priv_spec), | |
4766 | T(priv_spec_minor), | |
4767 | T(priv_spec_revision), | |
4768 | T(unaligned_access), | |
4769 | T(stack_align), | |
2dc8dd17 | 4770 | #undef T |
1942a048 | 4771 | }; |
2dc8dd17 JW |
4772 | |
4773 | if (name == NULL) | |
4774 | return -1; | |
4775 | ||
1942a048 | 4776 | unsigned int i; |
2dc8dd17 JW |
4777 | for (i = 0; i < ARRAY_SIZE (attribute_table); i++) |
4778 | if (strcmp (name, attribute_table[i].name) == 0) | |
4779 | return attribute_table[i].tag; | |
4780 | ||
4781 | return -1; | |
4782 | } | |
4783 | ||
4784 | /* Parse a .attribute directive. */ | |
4785 | ||
4786 | static void | |
4787 | s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) | |
4788 | { | |
4789 | int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC); | |
8f595e9b NC |
4790 | unsigned old_xlen; |
4791 | obj_attribute *attr; | |
2dc8dd17 | 4792 | |
5b7c81bd | 4793 | explicit_attr = true; |
8f595e9b | 4794 | switch (tag) |
2dc8dd17 | 4795 | { |
8f595e9b NC |
4796 | case Tag_RISCV_arch: |
4797 | old_xlen = xlen; | |
2dc8dd17 JW |
4798 | attr = elf_known_obj_attributes_proc (stdoutput); |
4799 | if (!start_assemble) | |
4800 | riscv_set_arch (attr[Tag_RISCV_arch].s); | |
4801 | else | |
b800637e NC |
4802 | as_fatal (_("architecture elf attributes must set before " |
4803 | "any instructions")); | |
2dc8dd17 JW |
4804 | |
4805 | if (old_xlen != xlen) | |
4806 | { | |
4807 | /* We must re-init bfd again if xlen is changed. */ | |
4808 | unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; | |
4809 | bfd_find_target (riscv_target_format (), stdoutput); | |
4810 | ||
4811 | if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) | |
b800637e | 4812 | as_warn (_("could not set architecture and machine")); |
2dc8dd17 | 4813 | } |
8f595e9b NC |
4814 | break; |
4815 | ||
4816 | case Tag_RISCV_priv_spec: | |
4817 | case Tag_RISCV_priv_spec_minor: | |
4818 | case Tag_RISCV_priv_spec_revision: | |
4819 | if (start_assemble) | |
b800637e NC |
4820 | as_fatal (_("privileged elf attributes must set before " |
4821 | "any instructions")); | |
8f595e9b NC |
4822 | break; |
4823 | ||
4824 | default: | |
4825 | break; | |
2dc8dd17 JW |
4826 | } |
4827 | } | |
4828 | ||
8155b853 NC |
4829 | /* Mark symbol that it follows a variant CC convention. */ |
4830 | ||
4831 | static void | |
4832 | s_variant_cc (int ignored ATTRIBUTE_UNUSED) | |
4833 | { | |
4834 | char *name; | |
4835 | char c; | |
4836 | symbolS *sym; | |
4837 | asymbol *bfdsym; | |
4838 | elf_symbol_type *elfsym; | |
4839 | ||
4840 | c = get_symbol_name (&name); | |
4841 | if (!*name) | |
4842 | as_bad (_("missing symbol name for .variant_cc directive")); | |
4843 | sym = symbol_find_or_make (name); | |
4844 | restore_line_pointer (c); | |
4845 | demand_empty_rest_of_line (); | |
4846 | ||
4847 | bfdsym = symbol_get_bfdsym (sym); | |
4848 | elfsym = elf_symbol_from (bfdsym); | |
4849 | gas_assert (elfsym); | |
4850 | elfsym->internal_elf_sym.st_other |= STO_RISCV_VARIANT_CC; | |
4851 | } | |
4852 | ||
4853 | /* Same as elf_copy_symbol_attributes, but without copying st_other. | |
4854 | This is needed so RISC-V specific st_other values can be independently | |
4855 | specified for an IFUNC resolver (that is called by the dynamic linker) | |
4856 | and the symbol it resolves (aliased to the resolver). In particular, | |
4857 | if a function symbol has special st_other value set via directives, | |
4858 | then attaching an IFUNC resolver to that symbol should not override | |
4859 | the st_other setting. Requiring the directive on the IFUNC resolver | |
4860 | symbol would be unexpected and problematic in C code, where the two | |
4861 | symbols appear as two independent function declarations. */ | |
4862 | ||
4863 | void | |
4864 | riscv_elf_copy_symbol_attributes (symbolS *dest, symbolS *src) | |
4865 | { | |
4866 | struct elf_obj_sy *srcelf = symbol_get_obj (src); | |
4867 | struct elf_obj_sy *destelf = symbol_get_obj (dest); | |
a3a7f5e1 FS |
4868 | /* If size is unset, copy size from src. Because we don't track whether |
4869 | .size has been used, we can't differentiate .size dest, 0 from the case | |
4870 | where dest's size is unset. */ | |
4871 | if (!destelf->size && S_GET_SIZE (dest) == 0) | |
8155b853 | 4872 | { |
a3a7f5e1 FS |
4873 | if (srcelf->size) |
4874 | { | |
4875 | destelf->size = XNEW (expressionS); | |
4876 | *destelf->size = *srcelf->size; | |
4877 | } | |
4878 | S_SET_SIZE (dest, S_GET_SIZE (src)); | |
8155b853 | 4879 | } |
8155b853 NC |
4880 | } |
4881 | ||
dcd709e0 | 4882 | /* RISC-V pseudo-ops table. */ |
e23eba97 NC |
4883 | static const pseudo_typeS riscv_pseudo_table[] = |
4884 | { | |
e23eba97 NC |
4885 | {"option", s_riscv_option, 0}, |
4886 | {"half", cons, 2}, | |
4887 | {"word", cons, 4}, | |
4888 | {"dword", cons, 8}, | |
4889 | {"dtprelword", s_dtprel, 4}, | |
4890 | {"dtpreldword", s_dtprel, 8}, | |
4891 | {"bss", s_bss, 0}, | |
e23eba97 NC |
4892 | {"uleb128", s_riscv_leb128, 0}, |
4893 | {"sleb128", s_riscv_leb128, 1}, | |
0e35537d | 4894 | {"insn", s_riscv_insn, 0}, |
2dc8dd17 | 4895 | {"attribute", s_riscv_attribute, 0}, |
8155b853 | 4896 | {"variant_cc", s_variant_cc, 0}, |
035784e3 | 4897 | {"float16", float_cons, 'h'}, |
e23eba97 NC |
4898 | |
4899 | { NULL, NULL, 0 }, | |
4900 | }; | |
4901 | ||
4902 | void | |
4903 | riscv_pop_insert (void) | |
4904 | { | |
4905 | extern void pop_insert (const pseudo_typeS *); | |
4906 | ||
4907 | pop_insert (riscv_pseudo_table); | |
4908 | } |