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252b5132 | 1 | /* tc-v850.c -- Assembler code for the NEC V850 |
d87bef3a | 2 | Copyright (C) 1996-2023 Free Software Foundation, Inc. |
252b5132 RH |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
ec2655a6 | 8 | the Free Software Foundation; either version 3, or (at your option) |
252b5132 RH |
9 | any later version. |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
19 | Boston, MA 02110-1301, USA. */ | |
252b5132 | 20 | |
252b5132 | 21 | #include "as.h" |
3882b010 | 22 | #include "safe-ctype.h" |
28e4f854 | 23 | #include "subsegs.h" |
252b5132 | 24 | #include "opcode/v850.h" |
a8761a19 | 25 | #include "dwarf2dbg.h" |
252b5132 | 26 | |
28e4f854 KH |
27 | /* Sign-extend a 16-bit number. */ |
28 | #define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) | |
252b5132 | 29 | |
252b5132 | 30 | /* Set to TRUE if we want to be pedantic about signed overflows. */ |
5b7c81bd AM |
31 | static bool warn_signed_overflows = false; |
32 | static bool warn_unsigned_overflows = false; | |
252b5132 | 33 | |
685080f2 NC |
34 | /* Non-zero if floating point insns are not being used. */ |
35 | static signed int soft_float = -1; | |
36 | ||
252b5132 | 37 | /* Indicates the target BFD machine number. */ |
28e4f854 | 38 | static int machine = -1; |
252b5132 | 39 | |
de863c74 | 40 | |
33eaf5de | 41 | /* Indicates the target BFD architecture. */ |
b42e9fa8 | 42 | enum bfd_architecture v850_target_arch = bfd_arch_v850_rh850; |
de863c74 NC |
43 | const char * v850_target_format = "elf32-v850-rh850"; |
44 | static flagword v850_e_flags = 0; | |
45 | ||
252b5132 | 46 | /* Indicates the target processor(s) for the assemble. */ |
1cd986c5 | 47 | static int processor_mask = 0; |
252b5132 RH |
48 | \f |
49 | /* Structure to hold information about predefined registers. */ | |
ea1562b3 NC |
50 | struct reg_name |
51 | { | |
28e4f854 KH |
52 | const char *name; |
53 | int value; | |
1cd986c5 | 54 | unsigned int processors; |
252b5132 RH |
55 | }; |
56 | ||
28e4f854 KH |
57 | /* Generic assembler global variables which must be defined by all |
58 | targets. */ | |
252b5132 | 59 | |
28e4f854 | 60 | /* Characters which always start a comment. */ |
252b5132 RH |
61 | const char comment_chars[] = "#"; |
62 | ||
63 | /* Characters which start a comment at the beginning of a line. */ | |
64 | const char line_comment_chars[] = ";#"; | |
65 | ||
28e4f854 | 66 | /* Characters which may be used to separate multiple commands on a |
252b5132 RH |
67 | single line. */ |
68 | const char line_separator_chars[] = ";"; | |
69 | ||
28e4f854 | 70 | /* Characters which are used to indicate an exponent in a floating |
252b5132 RH |
71 | point number. */ |
72 | const char EXP_CHARS[] = "eE"; | |
73 | ||
28e4f854 | 74 | /* Characters which mean that a number is a floating point constant, |
252b5132 RH |
75 | as in 0d1.0. */ |
76 | const char FLT_CHARS[] = "dD"; | |
77 | \f | |
ea1562b3 NC |
78 | const relax_typeS md_relax_table[] = |
79 | { | |
1cd986c5 NC |
80 | /* Conditional branches.(V850/V850E, max 22bit) */ |
81 | #define SUBYPTE_COND_9_22 0 | |
82 | {0xfe, -0x100, 2, SUBYPTE_COND_9_22 + 1}, | |
83 | {0x1ffffe + 2, -0x200000 + 2, 6, 0}, | |
84 | /* Conditional branches.(V850/V850E, max 22bit) */ | |
85 | #define SUBYPTE_SA_9_22 2 | |
86 | {0xfe, -0x100, 2, SUBYPTE_SA_9_22 + 1}, | |
87 | {0x1ffffe + 4, -0x200000 + 4, 8, 0}, | |
88 | /* Unconditional branches.(V850/V850E, max 22bit) */ | |
89 | #define SUBYPTE_UNCOND_9_22 4 | |
90 | {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22 + 1}, | |
91 | {0x1ffffe, -0x200000, 4, 0}, | |
92 | /* Conditional branches.(V850E2, max 32bit) */ | |
93 | #define SUBYPTE_COND_9_22_32 6 | |
94 | {0xfe, -0x100, 2, SUBYPTE_COND_9_22_32 + 1}, | |
95 | {0x1fffff + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_22_32 + 2}, | |
96 | {0x7ffffffe, -0x80000000, 8, 0}, | |
97 | /* Conditional branches.(V850E2, max 32bit) */ | |
98 | #define SUBYPTE_SA_9_22_32 9 | |
99 | {0xfe, -0x100, 2, SUBYPTE_SA_9_22_32 + 1}, | |
100 | {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_22_32 + 2}, | |
101 | {0x7ffffffe, -0x80000000, 10, 0}, | |
102 | /* Unconditional branches.(V850E2, max 32bit) */ | |
103 | #define SUBYPTE_UNCOND_9_22_32 12 | |
104 | {0xfe, -0x100, 2, SUBYPTE_UNCOND_9_22_32 + 1}, | |
105 | {0x1ffffe, -0x200000, 4, SUBYPTE_UNCOND_9_22_32 + 2}, | |
106 | {0x7ffffffe, -0x80000000, 6, 0}, | |
107 | /* Conditional branches.(V850E2R max 22bit) */ | |
108 | #define SUBYPTE_COND_9_17_22 15 | |
109 | {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22 + 1}, | |
110 | {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22 + 2}, | |
111 | {0x1ffffe + 2, -0x200000 + 2, 6, 0}, | |
112 | /* Conditional branches.(V850E2R max 22bit) */ | |
113 | #define SUBYPTE_SA_9_17_22 18 | |
114 | {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22 + 1}, | |
115 | {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22 + 2}, | |
116 | {0x1ffffe + 4, -0x200000 + 4, 8, 0}, | |
117 | /* Conditional branches.(V850E2R max 32bit) */ | |
118 | #define SUBYPTE_COND_9_17_22_32 21 | |
119 | {0xfe, -0x100, 2, SUBYPTE_COND_9_17_22_32 + 1}, | |
120 | {0xfffe, -0x10000, 4, SUBYPTE_COND_9_17_22_32 + 2}, | |
121 | {0x1ffffe + 2, -0x200000 + 2, 6, SUBYPTE_COND_9_17_22_32 + 3}, | |
122 | {0x7ffffffe, -0x80000000, 8, 0}, | |
123 | /* Conditional branches.(V850E2R max 32bit) */ | |
124 | #define SUBYPTE_SA_9_17_22_32 25 | |
125 | {0xfe, -0x100, 2, SUBYPTE_SA_9_17_22_32 + 1}, | |
126 | {0xfffe, -0x10000, 4, SUBYPTE_SA_9_17_22_32 + 2}, | |
127 | {0x1ffffe + 4, -0x200000 + 4, 8, SUBYPTE_SA_9_17_22_32 + 3}, | |
128 | {0x7ffffffe, -0x80000000, 10, 0}, | |
78c8d46c NC |
129 | /* Loop. (V850E2V4_UP, max 22-bit). */ |
130 | #define SUBYPTE_LOOP_16_22 29 | |
131 | {0x0, -0x0fffe, 4, SUBYPTE_LOOP_16_22 + 1}, | |
132 | {0x1ffffe + 2, -0x200000 + 2, 6, 0}, | |
252b5132 RH |
133 | }; |
134 | ||
1cd986c5 NC |
135 | static int v850_relax = 0; |
136 | ||
137 | /* Default branch disp size 22 or 32. */ | |
138 | static int default_disp_size = 22; | |
139 | ||
140 | /* Default no using bcond17. */ | |
141 | static int no_bcond17 = 0; | |
142 | ||
143 | /* Default no using ld/st 23bit offset. */ | |
144 | static int no_stld23 = 0; | |
86aba9db | 145 | |
28e4f854 | 146 | /* Fixups. */ |
ea1562b3 NC |
147 | #define MAX_INSN_FIXUPS 5 |
148 | ||
149 | struct v850_fixup | |
150 | { | |
28e4f854 KH |
151 | expressionS exp; |
152 | int opindex; | |
252b5132 RH |
153 | bfd_reloc_code_real_type reloc; |
154 | }; | |
155 | ||
28e4f854 | 156 | struct v850_fixup fixups[MAX_INSN_FIXUPS]; |
252b5132 | 157 | static int fc; |
252b5132 | 158 | |
9e0665bc | 159 | struct v850_seg_entry |
252b5132 | 160 | { |
9e0665bc AM |
161 | segT s; |
162 | const char *name; | |
163 | flagword flags; | |
164 | }; | |
252b5132 | 165 | |
9e0665bc | 166 | struct v850_seg_entry v850_seg_table[] = |
252b5132 | 167 | { |
9e0665bc AM |
168 | { NULL, ".sdata", |
169 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
170 | | SEC_SMALL_DATA }, | |
171 | { NULL, ".tdata", | |
172 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, | |
173 | { NULL, ".zdata", | |
174 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, | |
175 | { NULL, ".sbss", | |
176 | SEC_ALLOC | SEC_SMALL_DATA }, | |
177 | { NULL, ".tbss", | |
178 | SEC_ALLOC }, | |
179 | { NULL, ".zbss", | |
180 | SEC_ALLOC}, | |
181 | { NULL, ".rosdata", | |
182 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA | |
183 | | SEC_HAS_CONTENTS | SEC_SMALL_DATA }, | |
184 | { NULL, ".rozdata", | |
185 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_DATA | |
186 | | SEC_HAS_CONTENTS }, | |
187 | { NULL, ".scommon", | |
188 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
189 | | SEC_SMALL_DATA | SEC_IS_COMMON }, | |
190 | { NULL, ".tcommon", | |
191 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
192 | | SEC_IS_COMMON }, | |
193 | { NULL, ".zcommon", | |
194 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS | |
195 | | SEC_IS_COMMON }, | |
196 | { NULL, ".call_table_data", | |
197 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA | SEC_HAS_CONTENTS }, | |
198 | { NULL, ".call_table_text", | |
199 | SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_READONLY | SEC_CODE | |
200 | | SEC_HAS_CONTENTS}, | |
201 | { NULL, ".bss", | |
202 | SEC_ALLOC } | |
203 | }; | |
28e4f854 | 204 | |
9e0665bc AM |
205 | #define SDATA_SECTION 0 |
206 | #define TDATA_SECTION 1 | |
207 | #define ZDATA_SECTION 2 | |
208 | #define SBSS_SECTION 3 | |
209 | #define TBSS_SECTION 4 | |
210 | #define ZBSS_SECTION 5 | |
211 | #define ROSDATA_SECTION 6 | |
212 | #define ROZDATA_SECTION 7 | |
213 | #define SCOMMON_SECTION 8 | |
214 | #define TCOMMON_SECTION 9 | |
215 | #define ZCOMMON_SECTION 10 | |
216 | #define CALL_TABLE_DATA_SECTION 11 | |
217 | #define CALL_TABLE_TEXT_SECTION 12 | |
218 | #define BSS_SECTION 13 | |
219 | ||
9e0665bc | 220 | static void |
ea1562b3 | 221 | do_v850_seg (int i, subsegT sub) |
252b5132 | 222 | { |
9e0665bc | 223 | struct v850_seg_entry *seg = v850_seg_table + i; |
28e4f854 | 224 | |
28e4f854 | 225 | obj_elf_section_change_hook (); |
ea1562b3 | 226 | |
9e0665bc | 227 | if (seg->s != NULL) |
ea1562b3 | 228 | subseg_set (seg->s, sub); |
9e0665bc AM |
229 | else |
230 | { | |
231 | seg->s = subseg_new (seg->name, sub); | |
fd361982 | 232 | bfd_set_section_flags (seg->s, seg->flags); |
9e0665bc AM |
233 | if ((seg->flags & SEC_LOAD) == 0) |
234 | seg_info (seg->s)->bss = 1; | |
235 | } | |
252b5132 RH |
236 | } |
237 | ||
9e0665bc | 238 | static void |
ea1562b3 | 239 | v850_seg (int i) |
252b5132 | 240 | { |
9e0665bc | 241 | subsegT sub = get_absolute_expression (); |
28e4f854 | 242 | |
9e0665bc | 243 | do_v850_seg (i, sub); |
252b5132 RH |
244 | demand_empty_rest_of_line (); |
245 | } | |
246 | ||
9e0665bc | 247 | static void |
ea1562b3 | 248 | v850_offset (int ignore ATTRIBUTE_UNUSED) |
252b5132 | 249 | { |
825487fa | 250 | char *pfrag; |
252b5132 | 251 | int temp = get_absolute_expression (); |
685736be | 252 | |
825487fa | 253 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT)0, (symbolS *)0, |
ec178e1b | 254 | (offsetT) temp, (char *) 0); |
825487fa | 255 | *pfrag = 0; |
28e4f854 | 256 | |
252b5132 RH |
257 | demand_empty_rest_of_line (); |
258 | } | |
259 | ||
28e4f854 KH |
260 | /* Copied from obj_elf_common() in gas/config/obj-elf.c. */ |
261 | ||
252b5132 | 262 | static void |
ea1562b3 | 263 | v850_comm (int area) |
252b5132 | 264 | { |
28e4f854 KH |
265 | char *name; |
266 | char c; | |
267 | char *p; | |
268 | int temp; | |
269 | unsigned int size; | |
270 | symbolS *symbolP; | |
271 | int have_align; | |
252b5132 | 272 | |
d02603dc | 273 | c = get_symbol_name (&name); |
28e4f854 KH |
274 | |
275 | /* Just after name is now '\0'. */ | |
252b5132 RH |
276 | p = input_line_pointer; |
277 | *p = c; | |
28e4f854 | 278 | |
252b5132 | 279 | SKIP_WHITESPACE (); |
28e4f854 | 280 | |
252b5132 RH |
281 | if (*input_line_pointer != ',') |
282 | { | |
283 | as_bad (_("Expected comma after symbol-name")); | |
284 | ignore_rest_of_line (); | |
285 | return; | |
286 | } | |
28e4f854 KH |
287 | |
288 | /* Skip ','. */ | |
289 | input_line_pointer++; | |
290 | ||
252b5132 RH |
291 | if ((temp = get_absolute_expression ()) < 0) |
292 | { | |
28e4f854 | 293 | /* xgettext:c-format */ |
252b5132 RH |
294 | as_bad (_(".COMMon length (%d.) < 0! Ignored."), temp); |
295 | ignore_rest_of_line (); | |
296 | return; | |
297 | } | |
28e4f854 | 298 | |
252b5132 RH |
299 | size = temp; |
300 | *p = 0; | |
301 | symbolP = symbol_find_or_make (name); | |
302 | *p = c; | |
28e4f854 | 303 | |
252b5132 RH |
304 | if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) |
305 | { | |
306 | as_bad (_("Ignoring attempt to re-define symbol")); | |
307 | ignore_rest_of_line (); | |
308 | return; | |
309 | } | |
28e4f854 | 310 | |
252b5132 RH |
311 | if (S_GET_VALUE (symbolP) != 0) |
312 | { | |
313 | if (S_GET_VALUE (symbolP) != size) | |
ea1562b3 NC |
314 | /* xgettext:c-format */ |
315 | as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %d."), | |
316 | S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), size); | |
252b5132 | 317 | } |
28e4f854 KH |
318 | |
319 | know (symbol_get_frag (symbolP) == &zero_address_frag); | |
320 | ||
252b5132 RH |
321 | if (*input_line_pointer != ',') |
322 | have_align = 0; | |
323 | else | |
324 | { | |
325 | have_align = 1; | |
326 | input_line_pointer++; | |
327 | SKIP_WHITESPACE (); | |
328 | } | |
28e4f854 | 329 | |
252b5132 RH |
330 | if (! have_align || *input_line_pointer != '"') |
331 | { | |
332 | if (! have_align) | |
333 | temp = 0; | |
334 | else | |
335 | { | |
336 | temp = get_absolute_expression (); | |
28e4f854 | 337 | |
252b5132 RH |
338 | if (temp < 0) |
339 | { | |
340 | temp = 0; | |
341 | as_warn (_("Common alignment negative; 0 assumed")); | |
342 | } | |
343 | } | |
28e4f854 | 344 | |
cac58fa6 | 345 | if (symbol_get_obj (symbolP)->local) |
252b5132 | 346 | { |
28e4f854 KH |
347 | segT old_sec; |
348 | int old_subsec; | |
349 | char *pfrag; | |
350 | int align; | |
351 | flagword applicable; | |
252b5132 RH |
352 | |
353 | old_sec = now_seg; | |
354 | old_subsec = now_subseg; | |
28e4f854 | 355 | |
252b5132 | 356 | applicable = bfd_applicable_section_flags (stdoutput); |
28e4f854 | 357 | |
252b5132 | 358 | applicable &= SEC_ALLOC; |
28e4f854 | 359 | |
252b5132 RH |
360 | switch (area) |
361 | { | |
9e0665bc AM |
362 | case SCOMMON_SECTION: |
363 | do_v850_seg (SBSS_SECTION, 0); | |
252b5132 | 364 | break; |
28e4f854 | 365 | |
9e0665bc AM |
366 | case ZCOMMON_SECTION: |
367 | do_v850_seg (ZBSS_SECTION, 0); | |
252b5132 | 368 | break; |
28e4f854 | 369 | |
9e0665bc AM |
370 | case TCOMMON_SECTION: |
371 | do_v850_seg (TBSS_SECTION, 0); | |
252b5132 RH |
372 | break; |
373 | } | |
374 | ||
375 | if (temp) | |
376 | { | |
28e4f854 | 377 | /* Convert to a power of 2 alignment. */ |
252b5132 RH |
378 | for (align = 0; (temp & 1) == 0; temp >>= 1, ++align) |
379 | ; | |
28e4f854 | 380 | |
252b5132 RH |
381 | if (temp != 1) |
382 | { | |
383 | as_bad (_("Common alignment not a power of 2")); | |
384 | ignore_rest_of_line (); | |
385 | return; | |
386 | } | |
387 | } | |
388 | else | |
389 | align = 0; | |
28e4f854 | 390 | |
9e0665bc | 391 | record_alignment (now_seg, align); |
28e4f854 | 392 | |
252b5132 RH |
393 | if (align) |
394 | frag_align (align, 0, 0); | |
395 | ||
396 | switch (area) | |
397 | { | |
9e0665bc AM |
398 | case SCOMMON_SECTION: |
399 | if (S_GET_SEGMENT (symbolP) == v850_seg_table[SBSS_SECTION].s) | |
7dcc9865 | 400 | symbol_get_frag (symbolP)->fr_symbol = 0; |
252b5132 RH |
401 | break; |
402 | ||
9e0665bc AM |
403 | case ZCOMMON_SECTION: |
404 | if (S_GET_SEGMENT (symbolP) == v850_seg_table[ZBSS_SECTION].s) | |
7dcc9865 | 405 | symbol_get_frag (symbolP)->fr_symbol = 0; |
252b5132 RH |
406 | break; |
407 | ||
9e0665bc AM |
408 | case TCOMMON_SECTION: |
409 | if (S_GET_SEGMENT (symbolP) == v850_seg_table[TBSS_SECTION].s) | |
7dcc9865 | 410 | symbol_get_frag (symbolP)->fr_symbol = 0; |
252b5132 RH |
411 | break; |
412 | ||
413 | default: | |
cac58fa6 | 414 | abort (); |
252b5132 | 415 | } |
28e4f854 | 416 | |
7dcc9865 | 417 | symbol_set_frag (symbolP, frag_now); |
252b5132 RH |
418 | pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, |
419 | (offsetT) size, (char *) 0); | |
420 | *pfrag = 0; | |
421 | S_SET_SIZE (symbolP, size); | |
28e4f854 | 422 | |
252b5132 RH |
423 | switch (area) |
424 | { | |
9e0665bc AM |
425 | case SCOMMON_SECTION: |
426 | S_SET_SEGMENT (symbolP, v850_seg_table[SBSS_SECTION].s); | |
252b5132 | 427 | break; |
28e4f854 | 428 | |
9e0665bc AM |
429 | case ZCOMMON_SECTION: |
430 | S_SET_SEGMENT (symbolP, v850_seg_table[ZBSS_SECTION].s); | |
252b5132 | 431 | break; |
28e4f854 | 432 | |
9e0665bc AM |
433 | case TCOMMON_SECTION: |
434 | S_SET_SEGMENT (symbolP, v850_seg_table[TBSS_SECTION].s); | |
252b5132 | 435 | break; |
28e4f854 | 436 | |
252b5132 | 437 | default: |
28e4f854 | 438 | abort (); |
252b5132 | 439 | } |
28e4f854 | 440 | |
252b5132 | 441 | S_CLEAR_EXTERNAL (symbolP); |
28e4f854 | 442 | obj_elf_section_change_hook (); |
252b5132 RH |
443 | subseg_set (old_sec, old_subsec); |
444 | } | |
445 | else | |
446 | { | |
ec178e1b AM |
447 | segT old_sec; |
448 | int old_subsec; | |
86aba9db | 449 | |
252b5132 | 450 | allocate_common: |
ec178e1b AM |
451 | old_sec = now_seg; |
452 | old_subsec = now_subseg; | |
86aba9db | 453 | |
252b5132 RH |
454 | S_SET_VALUE (symbolP, (valueT) size); |
455 | S_SET_ALIGN (symbolP, temp); | |
456 | S_SET_EXTERNAL (symbolP); | |
28e4f854 | 457 | |
252b5132 RH |
458 | switch (area) |
459 | { | |
9e0665bc AM |
460 | case SCOMMON_SECTION: |
461 | case ZCOMMON_SECTION: | |
462 | case TCOMMON_SECTION: | |
463 | do_v850_seg (area, 0); | |
464 | S_SET_SEGMENT (symbolP, v850_seg_table[area].s); | |
252b5132 | 465 | break; |
28e4f854 | 466 | |
252b5132 | 467 | default: |
28e4f854 | 468 | abort (); |
252b5132 | 469 | } |
86aba9db NC |
470 | |
471 | obj_elf_section_change_hook (); | |
472 | subseg_set (old_sec, old_subsec); | |
252b5132 RH |
473 | } |
474 | } | |
475 | else | |
476 | { | |
477 | input_line_pointer++; | |
28e4f854 | 478 | |
252b5132 RH |
479 | /* @@ Some use the dot, some don't. Can we get some consistency?? */ |
480 | if (*input_line_pointer == '.') | |
481 | input_line_pointer++; | |
28e4f854 | 482 | |
252b5132 | 483 | /* @@ Some say data, some say bss. */ |
d34049e8 ML |
484 | if (!startswith (input_line_pointer, "bss\"") |
485 | && !startswith (input_line_pointer, "data\"")) | |
252b5132 RH |
486 | { |
487 | while (*--input_line_pointer != '"') | |
488 | ; | |
489 | input_line_pointer--; | |
490 | goto bad_common_segment; | |
491 | } | |
ea1562b3 | 492 | |
252b5132 RH |
493 | while (*input_line_pointer++ != '"') |
494 | ; | |
ea1562b3 | 495 | |
252b5132 RH |
496 | goto allocate_common; |
497 | } | |
498 | ||
fed9b18a | 499 | symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; |
252b5132 RH |
500 | |
501 | demand_empty_rest_of_line (); | |
502 | return; | |
503 | ||
504 | { | |
505 | bad_common_segment: | |
506 | p = input_line_pointer; | |
507 | while (*p && *p != '\n') | |
508 | p++; | |
509 | c = *p; | |
510 | *p = '\0'; | |
511 | as_bad (_("bad .common segment %s"), input_line_pointer + 1); | |
512 | *p = c; | |
513 | input_line_pointer = p; | |
514 | ignore_rest_of_line (); | |
515 | return; | |
516 | } | |
517 | } | |
518 | ||
9e0665bc | 519 | static void |
ea1562b3 | 520 | set_machine (int number) |
252b5132 RH |
521 | { |
522 | machine = number; | |
de863c74 | 523 | bfd_set_arch_mach (stdoutput, v850_target_arch, machine); |
252b5132 RH |
524 | |
525 | switch (machine) | |
526 | { | |
1cd986c5 NC |
527 | case 0: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; |
528 | case bfd_mach_v850: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); break; | |
529 | case bfd_mach_v850e: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; | |
530 | case bfd_mach_v850e1: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); break; | |
531 | case bfd_mach_v850e2: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); break; | |
532 | case bfd_mach_v850e2v3:SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); break; | |
78c8d46c | 533 | case bfd_mach_v850e3v5: SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); break; |
252b5132 RH |
534 | } |
535 | } | |
536 | ||
86aba9db | 537 | static void |
ea1562b3 | 538 | v850_longcode (int type) |
86aba9db NC |
539 | { |
540 | expressionS ex; | |
541 | ||
542 | if (! v850_relax) | |
543 | { | |
544 | if (type == 1) | |
20203fb9 | 545 | as_warn (_(".longcall pseudo-op seen when not relaxing")); |
86aba9db | 546 | else |
20203fb9 | 547 | as_warn (_(".longjump pseudo-op seen when not relaxing")); |
86aba9db NC |
548 | } |
549 | ||
550 | expression (&ex); | |
551 | ||
552 | if (ex.X_op != O_symbol || ex.X_add_number != 0) | |
553 | { | |
20203fb9 | 554 | as_bad (_("bad .longcall format")); |
86aba9db NC |
555 | ignore_rest_of_line (); |
556 | ||
557 | return; | |
558 | } | |
559 | ||
ec178e1b | 560 | if (type == 1) |
86aba9db NC |
561 | fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, |
562 | BFD_RELOC_V850_LONGCALL); | |
563 | else | |
564 | fix_new_exp (frag_now, frag_now_fix (), 4, & ex, 1, | |
565 | BFD_RELOC_V850_LONGJUMP); | |
566 | ||
567 | demand_empty_rest_of_line (); | |
568 | } | |
569 | ||
252b5132 | 570 | /* The target specific pseudo-ops which we support. */ |
77c6dd37 NC |
571 | const pseudo_typeS md_pseudo_table[] = |
572 | { | |
9e0665bc AM |
573 | { "sdata", v850_seg, SDATA_SECTION }, |
574 | { "tdata", v850_seg, TDATA_SECTION }, | |
575 | { "zdata", v850_seg, ZDATA_SECTION }, | |
576 | { "sbss", v850_seg, SBSS_SECTION }, | |
577 | { "tbss", v850_seg, TBSS_SECTION }, | |
578 | { "zbss", v850_seg, ZBSS_SECTION }, | |
579 | { "rosdata", v850_seg, ROSDATA_SECTION }, | |
580 | { "rozdata", v850_seg, ROZDATA_SECTION }, | |
581 | { "bss", v850_seg, BSS_SECTION }, | |
582 | { "offset", v850_offset, 0 }, | |
583 | { "word", cons, 4 }, | |
584 | { "zcomm", v850_comm, ZCOMMON_SECTION }, | |
585 | { "scomm", v850_comm, SCOMMON_SECTION }, | |
586 | { "tcomm", v850_comm, TCOMMON_SECTION }, | |
587 | { "v850", set_machine, 0 }, | |
588 | { "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION }, | |
589 | { "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION }, | |
590 | { "v850e", set_machine, bfd_mach_v850e }, | |
1cd986c5 NC |
591 | { "v850e1", set_machine, bfd_mach_v850e1 }, |
592 | { "v850e2", set_machine, bfd_mach_v850e2 }, | |
593 | { "v850e2v3", set_machine, bfd_mach_v850e2v3 }, | |
78c8d46c NC |
594 | { "v850e2v4", set_machine, bfd_mach_v850e3v5 }, |
595 | { "v850e3v5", set_machine, bfd_mach_v850e3v5 }, | |
ec178e1b AM |
596 | { "longcall", v850_longcode, 1 }, |
597 | { "longjump", v850_longcode, 2 }, | |
9e0665bc | 598 | { NULL, NULL, 0 } |
252b5132 RH |
599 | }; |
600 | ||
601 | /* Opcode hash table. */ | |
629310ab | 602 | static htab_t v850_hash; |
252b5132 | 603 | |
28e4f854 | 604 | /* This table is sorted. Suitable for searching by a binary search. */ |
77c6dd37 NC |
605 | static const struct reg_name pre_defined_registers[] = |
606 | { | |
1cd986c5 NC |
607 | { "ep", 30, PROCESSOR_ALL }, /* ep - element ptr. */ |
608 | { "gp", 4, PROCESSOR_ALL }, /* gp - global ptr. */ | |
609 | { "hp", 2, PROCESSOR_ALL }, /* hp - handler stack ptr. */ | |
610 | { "lp", 31, PROCESSOR_ALL }, /* lp - link ptr. */ | |
611 | { "r0", 0, PROCESSOR_ALL }, | |
612 | { "r1", 1, PROCESSOR_ALL }, | |
613 | { "r10", 10, PROCESSOR_ALL }, | |
614 | { "r11", 11, PROCESSOR_ALL }, | |
615 | { "r12", 12, PROCESSOR_ALL }, | |
616 | { "r13", 13, PROCESSOR_ALL }, | |
617 | { "r14", 14, PROCESSOR_ALL }, | |
618 | { "r15", 15, PROCESSOR_ALL }, | |
619 | { "r16", 16, PROCESSOR_ALL }, | |
620 | { "r17", 17, PROCESSOR_ALL }, | |
621 | { "r18", 18, PROCESSOR_ALL }, | |
622 | { "r19", 19, PROCESSOR_ALL }, | |
623 | { "r2", 2, PROCESSOR_ALL }, | |
624 | { "r20", 20, PROCESSOR_ALL }, | |
625 | { "r21", 21, PROCESSOR_ALL }, | |
626 | { "r22", 22, PROCESSOR_ALL }, | |
627 | { "r23", 23, PROCESSOR_ALL }, | |
628 | { "r24", 24, PROCESSOR_ALL }, | |
629 | { "r25", 25, PROCESSOR_ALL }, | |
630 | { "r26", 26, PROCESSOR_ALL }, | |
631 | { "r27", 27, PROCESSOR_ALL }, | |
632 | { "r28", 28, PROCESSOR_ALL }, | |
633 | { "r29", 29, PROCESSOR_ALL }, | |
634 | { "r3", 3, PROCESSOR_ALL }, | |
635 | { "r30", 30, PROCESSOR_ALL }, | |
636 | { "r31", 31, PROCESSOR_ALL }, | |
637 | { "r4", 4, PROCESSOR_ALL }, | |
638 | { "r5", 5, PROCESSOR_ALL }, | |
639 | { "r6", 6, PROCESSOR_ALL }, | |
640 | { "r7", 7, PROCESSOR_ALL }, | |
641 | { "r8", 8, PROCESSOR_ALL }, | |
642 | { "r9", 9, PROCESSOR_ALL }, | |
643 | { "sp", 3, PROCESSOR_ALL }, /* sp - stack ptr. */ | |
644 | { "tp", 5, PROCESSOR_ALL }, /* tp - text ptr. */ | |
645 | { "zero", 0, PROCESSOR_ALL }, | |
252b5132 | 646 | }; |
252b5132 | 647 | |
28e4f854 KH |
648 | #define REG_NAME_CNT \ |
649 | (sizeof (pre_defined_registers) / sizeof (struct reg_name)) | |
252b5132 | 650 | |
77c6dd37 NC |
651 | static const struct reg_name system_registers[] = |
652 | { | |
1cd986c5 NC |
653 | { "asid", 23, PROCESSOR_NOT_V850 }, |
654 | { "bpam", 25, PROCESSOR_NOT_V850 }, | |
655 | { "bpav", 24, PROCESSOR_NOT_V850 }, | |
656 | { "bpc", 22, PROCESSOR_NOT_V850 }, | |
657 | { "bpdm", 27, PROCESSOR_NOT_V850 }, | |
658 | { "bpdv", 26, PROCESSOR_NOT_V850 }, | |
78c8d46c NC |
659 | { "bsel", 31, PROCESSOR_V850E2_UP }, |
660 | { "cfg", 7, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 NC |
661 | { "ctbp", 20, PROCESSOR_NOT_V850 }, |
662 | { "ctpc", 16, PROCESSOR_NOT_V850 }, | |
663 | { "ctpsw", 17, PROCESSOR_NOT_V850 }, | |
78c8d46c | 664 | { "dbic", 15, PROCESSOR_V850E2_UP }, |
1cd986c5 NC |
665 | { "dbpc", 18, PROCESSOR_NOT_V850 }, |
666 | { "dbpsw", 19, PROCESSOR_NOT_V850 }, | |
78c8d46c | 667 | { "dbwr", 30, PROCESSOR_V850E2_UP }, |
1cd986c5 | 668 | { "dir", 21, PROCESSOR_NOT_V850 }, |
78c8d46c NC |
669 | { "dpa0l", 16, PROCESSOR_V850E2V3_UP }, |
670 | { "dpa0u", 17, PROCESSOR_V850E2V3_UP }, | |
671 | { "dpa1l", 18, PROCESSOR_V850E2V3_UP }, | |
672 | { "dpa1u", 19, PROCESSOR_V850E2V3_UP }, | |
673 | { "dpa2l", 20, PROCESSOR_V850E2V3_UP }, | |
674 | { "dpa2u", 21, PROCESSOR_V850E2V3_UP }, | |
675 | { "dpa3l", 22, PROCESSOR_V850E2V3_UP }, | |
676 | { "dpa3u", 23, PROCESSOR_V850E2V3_UP }, | |
677 | { "dpa4l", 24, PROCESSOR_V850E2V3_UP }, | |
678 | { "dpa4u", 25, PROCESSOR_V850E2V3_UP }, | |
679 | { "dpa5l", 26, PROCESSOR_V850E2V3_UP }, | |
680 | { "dpa5u", 27, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 | 681 | { "ecr", 4, PROCESSOR_ALL }, |
78c8d46c NC |
682 | { "eh_base", 3, PROCESSOR_V850E2V3_UP }, |
683 | { "eh_cfg", 1, PROCESSOR_V850E2V3_UP }, | |
684 | { "eh_reset", 2, PROCESSOR_V850E2V3_UP }, | |
685 | { "eiic", 13, PROCESSOR_V850E2_UP }, | |
1cd986c5 NC |
686 | { "eipc", 0, PROCESSOR_ALL }, |
687 | { "eipsw", 1, PROCESSOR_ALL }, | |
78c8d46c NC |
688 | { "eiwr", 28, PROCESSOR_V850E2_UP }, |
689 | { "feic", 14, PROCESSOR_V850E2_UP }, | |
1cd986c5 NC |
690 | { "fepc", 2, PROCESSOR_ALL }, |
691 | { "fepsw", 3, PROCESSOR_ALL }, | |
78c8d46c NC |
692 | { "fewr", 29, PROCESSOR_V850E2_UP }, |
693 | { "fpcc", 9, PROCESSOR_V850E2V3_UP }, | |
694 | { "fpcfg", 10, PROCESSOR_V850E2V3_UP }, | |
695 | { "fpec", 11, PROCESSOR_V850E2V3_UP }, | |
696 | { "fpepc", 7, PROCESSOR_V850E2V3_UP }, | |
697 | { "fpspc", 27, PROCESSOR_V850E2V3_UP }, | |
698 | { "fpsr", 6, PROCESSOR_V850E2V3_UP }, | |
699 | { "fpst", 8, PROCESSOR_V850E2V3_UP }, | |
700 | { "ipa0l", 6, PROCESSOR_V850E2V3_UP }, | |
701 | { "ipa0u", 7, PROCESSOR_V850E2V3_UP }, | |
702 | { "ipa1l", 8, PROCESSOR_V850E2V3_UP }, | |
703 | { "ipa1u", 9, PROCESSOR_V850E2V3_UP }, | |
704 | { "ipa2l", 10, PROCESSOR_V850E2V3_UP }, | |
705 | { "ipa2u", 11, PROCESSOR_V850E2V3_UP }, | |
706 | { "ipa3l", 12, PROCESSOR_V850E2V3_UP }, | |
707 | { "ipa3u", 13, PROCESSOR_V850E2V3_UP }, | |
708 | { "ipa4l", 14, PROCESSOR_V850E2V3_UP }, | |
709 | { "ipa4u", 15, PROCESSOR_V850E2V3_UP }, | |
710 | { "mca", 24, PROCESSOR_V850E2V3_UP }, | |
711 | { "mcc", 26, PROCESSOR_V850E2V3_UP }, | |
712 | { "mcr", 27, PROCESSOR_V850E2V3_UP }, | |
713 | { "mcs", 25, PROCESSOR_V850E2V3_UP }, | |
714 | { "mpc", 1, PROCESSOR_V850E2V3_UP }, | |
715 | { "mpm", 0, PROCESSOR_V850E2V3_UP }, | |
716 | { "mpu10_dpa0l", 16, PROCESSOR_V850E2V3_UP }, | |
717 | { "mpu10_dpa0u", 17, PROCESSOR_V850E2V3_UP }, | |
718 | { "mpu10_dpa1l", 18, PROCESSOR_V850E2V3_UP }, | |
719 | { "mpu10_dpa1u", 19, PROCESSOR_V850E2V3_UP }, | |
720 | { "mpu10_dpa2l", 20, PROCESSOR_V850E2V3_UP }, | |
721 | { "mpu10_dpa2u", 21, PROCESSOR_V850E2V3_UP }, | |
722 | { "mpu10_dpa3l", 22, PROCESSOR_V850E2V3_UP }, | |
723 | { "mpu10_dpa3u", 23, PROCESSOR_V850E2V3_UP }, | |
724 | { "mpu10_dpa4l", 24, PROCESSOR_V850E2V3_UP }, | |
725 | { "mpu10_dpa4u", 25, PROCESSOR_V850E2V3_UP }, | |
726 | { "mpu10_dpa5l", 26, PROCESSOR_V850E2V3_UP }, | |
727 | { "mpu10_dpa5u", 27, PROCESSOR_V850E2V3_UP }, | |
728 | { "mpu10_ipa0l", 6, PROCESSOR_V850E2V3_UP }, | |
729 | { "mpu10_ipa0u", 7, PROCESSOR_V850E2V3_UP }, | |
730 | { "mpu10_ipa1l", 8, PROCESSOR_V850E2V3_UP }, | |
731 | { "mpu10_ipa1u", 9, PROCESSOR_V850E2V3_UP }, | |
732 | { "mpu10_ipa2l", 10, PROCESSOR_V850E2V3_UP }, | |
733 | { "mpu10_ipa2u", 11, PROCESSOR_V850E2V3_UP }, | |
734 | { "mpu10_ipa3l", 12, PROCESSOR_V850E2V3_UP }, | |
735 | { "mpu10_ipa3u", 13, PROCESSOR_V850E2V3_UP }, | |
736 | { "mpu10_ipa4l", 14, PROCESSOR_V850E2V3_UP }, | |
737 | { "mpu10_ipa4u", 15, PROCESSOR_V850E2V3_UP }, | |
738 | { "mpu10_mpc", 1, PROCESSOR_V850E2V3_UP }, | |
739 | { "mpu10_mpm", 0, PROCESSOR_V850E2V3_UP }, | |
740 | { "mpu10_tid", 2, PROCESSOR_V850E2V3_UP }, | |
741 | { "mpu10_vmadr", 5, PROCESSOR_V850E2V3_UP }, | |
742 | { "mpu10_vmecr", 3, PROCESSOR_V850E2V3_UP }, | |
743 | { "mpu10_vmtid", 4, PROCESSOR_V850E2V3_UP }, | |
744 | { "pid", 6, PROCESSOR_V850E2V3_UP }, | |
745 | { "pmcr0", 4, PROCESSOR_V850E2V3_UP }, | |
746 | { "pmis2", 14, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 | 747 | { "psw", 5, PROCESSOR_ALL }, |
78c8d46c NC |
748 | { "scbp", 12, PROCESSOR_V850E2V3_UP }, |
749 | { "sccfg", 11, PROCESSOR_V850E2V3_UP }, | |
1cd986c5 NC |
750 | { "sr0", 0, PROCESSOR_ALL }, |
751 | { "sr1", 1, PROCESSOR_ALL }, | |
752 | { "sr10", 10, PROCESSOR_ALL }, | |
753 | { "sr11", 11, PROCESSOR_ALL }, | |
754 | { "sr12", 12, PROCESSOR_ALL }, | |
755 | { "sr13", 13, PROCESSOR_ALL }, | |
756 | { "sr14", 14, PROCESSOR_ALL }, | |
757 | { "sr15", 15, PROCESSOR_ALL }, | |
758 | { "sr16", 16, PROCESSOR_ALL }, | |
759 | { "sr17", 17, PROCESSOR_ALL }, | |
760 | { "sr18", 18, PROCESSOR_ALL }, | |
761 | { "sr19", 19, PROCESSOR_ALL }, | |
762 | { "sr2", 2, PROCESSOR_ALL }, | |
763 | { "sr20", 20, PROCESSOR_ALL }, | |
764 | { "sr21", 21, PROCESSOR_ALL }, | |
765 | { "sr22", 22, PROCESSOR_ALL }, | |
766 | { "sr23", 23, PROCESSOR_ALL }, | |
767 | { "sr24", 24, PROCESSOR_ALL }, | |
768 | { "sr25", 25, PROCESSOR_ALL }, | |
769 | { "sr26", 26, PROCESSOR_ALL }, | |
770 | { "sr27", 27, PROCESSOR_ALL }, | |
771 | { "sr28", 28, PROCESSOR_ALL }, | |
772 | { "sr29", 29, PROCESSOR_ALL }, | |
773 | { "sr3", 3, PROCESSOR_ALL }, | |
774 | { "sr30", 30, PROCESSOR_ALL }, | |
775 | { "sr31", 31, PROCESSOR_ALL }, | |
776 | { "sr4", 4, PROCESSOR_ALL }, | |
777 | { "sr5", 5, PROCESSOR_ALL }, | |
778 | { "sr6", 6, PROCESSOR_ALL }, | |
779 | { "sr7", 7, PROCESSOR_ALL }, | |
780 | { "sr8", 8, PROCESSOR_ALL }, | |
781 | { "sr9", 9, PROCESSOR_ALL }, | |
78c8d46c NC |
782 | { "sw_base", 3, PROCESSOR_V850E2V3_UP }, |
783 | { "sw_cfg", 1, PROCESSOR_V850E2V3_UP }, | |
784 | { "sw_ctl", 0, PROCESSOR_V850E2V3_UP }, | |
785 | { "tid", 2, PROCESSOR_V850E2V3_UP }, | |
786 | { "vmadr", 6, PROCESSOR_V850E2V3_UP }, | |
787 | { "vmecr", 4, PROCESSOR_V850E2V3_UP }, | |
788 | { "vmtid", 5, PROCESSOR_V850E2V3_UP }, | |
789 | { "vsadr", 2, PROCESSOR_V850E2V3_UP }, | |
790 | { "vsecr", 0, PROCESSOR_V850E2V3_UP }, | |
791 | { "vstid", 1, PROCESSOR_V850E2V3_UP }, | |
252b5132 | 792 | }; |
28e4f854 KH |
793 | |
794 | #define SYSREG_NAME_CNT \ | |
795 | (sizeof (system_registers) / sizeof (struct reg_name)) | |
252b5132 | 796 | |
252b5132 | 797 | |
77c6dd37 NC |
798 | static const struct reg_name cc_names[] = |
799 | { | |
1cd986c5 NC |
800 | { "c", 0x1, PROCESSOR_ALL }, |
801 | { "e", 0x2, PROCESSOR_ALL }, | |
802 | { "ge", 0xe, PROCESSOR_ALL }, | |
803 | { "gt", 0xf, PROCESSOR_ALL }, | |
804 | { "h", 0xb, PROCESSOR_ALL }, | |
805 | { "l", 0x1, PROCESSOR_ALL }, | |
806 | { "le", 0x7, PROCESSOR_ALL }, | |
807 | { "lt", 0x6, PROCESSOR_ALL }, | |
808 | { "n", 0x4, PROCESSOR_ALL }, | |
809 | { "nc", 0x9, PROCESSOR_ALL }, | |
810 | { "ne", 0xa, PROCESSOR_ALL }, | |
811 | { "nh", 0x3, PROCESSOR_ALL }, | |
812 | { "nl", 0x9, PROCESSOR_ALL }, | |
813 | { "ns", 0xc, PROCESSOR_ALL }, | |
814 | { "nv", 0x8, PROCESSOR_ALL }, | |
815 | { "nz", 0xa, PROCESSOR_ALL }, | |
816 | { "p", 0xc, PROCESSOR_ALL }, | |
817 | { "s", 0x4, PROCESSOR_ALL }, | |
818 | #define COND_SA_NUM 0xd | |
819 | { "sa", COND_SA_NUM, PROCESSOR_ALL }, | |
820 | { "t", 0x5, PROCESSOR_ALL }, | |
821 | { "v", 0x0, PROCESSOR_ALL }, | |
822 | { "z", 0x2, PROCESSOR_ALL }, | |
252b5132 | 823 | }; |
252b5132 | 824 | |
28e4f854 KH |
825 | #define CC_NAME_CNT \ |
826 | (sizeof (cc_names) / sizeof (struct reg_name)) | |
827 | ||
1cd986c5 NC |
828 | static const struct reg_name float_cc_names[] = |
829 | { | |
78c8d46c NC |
830 | { "eq", 0x2, PROCESSOR_V850E2V3_UP }, /* true. */ |
831 | { "f", 0x0, PROCESSOR_V850E2V3_UP }, /* true. */ | |
832 | { "ge", 0xd, PROCESSOR_V850E2V3_UP }, /* false. */ | |
833 | { "gl", 0xb, PROCESSOR_V850E2V3_UP }, /* false. */ | |
834 | { "gle", 0x9, PROCESSOR_V850E2V3_UP }, /* false. */ | |
835 | { "gt", 0xf, PROCESSOR_V850E2V3_UP }, /* false. */ | |
836 | { "le", 0xe, PROCESSOR_V850E2V3_UP }, /* true. */ | |
837 | { "lt", 0xc, PROCESSOR_V850E2V3_UP }, /* true. */ | |
838 | { "neq", 0x2, PROCESSOR_V850E2V3_UP }, /* false. */ | |
839 | { "nge", 0xd, PROCESSOR_V850E2V3_UP }, /* true. */ | |
840 | { "ngl", 0xb, PROCESSOR_V850E2V3_UP }, /* true. */ | |
841 | { "ngle",0x9, PROCESSOR_V850E2V3_UP }, /* true. */ | |
842 | { "ngt", 0xf, PROCESSOR_V850E2V3_UP }, /* true. */ | |
843 | { "nle", 0xe, PROCESSOR_V850E2V3_UP }, /* false. */ | |
844 | { "nlt", 0xc, PROCESSOR_V850E2V3_UP }, /* false. */ | |
845 | { "oge", 0x5, PROCESSOR_V850E2V3_UP }, /* false. */ | |
846 | { "ogl", 0x3, PROCESSOR_V850E2V3_UP }, /* false. */ | |
847 | { "ogt", 0x7, PROCESSOR_V850E2V3_UP }, /* false. */ | |
848 | { "ole", 0x6, PROCESSOR_V850E2V3_UP }, /* true. */ | |
849 | { "olt", 0x4, PROCESSOR_V850E2V3_UP }, /* true. */ | |
850 | { "or", 0x1, PROCESSOR_V850E2V3_UP }, /* false. */ | |
851 | { "seq", 0xa, PROCESSOR_V850E2V3_UP }, /* true. */ | |
852 | { "sf", 0x8, PROCESSOR_V850E2V3_UP }, /* true. */ | |
853 | { "sne", 0xa, PROCESSOR_V850E2V3_UP }, /* false. */ | |
854 | { "st", 0x8, PROCESSOR_V850E2V3_UP }, /* false. */ | |
855 | { "t", 0x0, PROCESSOR_V850E2V3_UP }, /* false. */ | |
856 | { "ueq", 0x3, PROCESSOR_V850E2V3_UP }, /* true. */ | |
857 | { "uge", 0x4, PROCESSOR_V850E2V3_UP }, /* false. */ | |
858 | { "ugt", 0x6, PROCESSOR_V850E2V3_UP }, /* false. */ | |
859 | { "ule", 0x7, PROCESSOR_V850E2V3_UP }, /* true. */ | |
860 | { "ult", 0x5, PROCESSOR_V850E2V3_UP }, /* true. */ | |
861 | { "un", 0x1, PROCESSOR_V850E2V3_UP }, /* true. */ | |
1cd986c5 NC |
862 | }; |
863 | ||
864 | #define FLOAT_CC_NAME_CNT \ | |
865 | (sizeof (float_cc_names) / sizeof (struct reg_name)) | |
866 | ||
78c8d46c NC |
867 | |
868 | static const struct reg_name cacheop_names[] = | |
869 | { | |
870 | { "cfald", 0x44, PROCESSOR_V850E3V5_UP }, | |
871 | { "cfali", 0x40, PROCESSOR_V850E3V5_UP }, | |
872 | { "chbid", 0x04, PROCESSOR_V850E3V5_UP }, | |
873 | { "chbii", 0x00, PROCESSOR_V850E3V5_UP }, | |
874 | { "chbiwbd", 0x06, PROCESSOR_V850E3V5_UP }, | |
875 | { "chbwbd", 0x07, PROCESSOR_V850E3V5_UP }, | |
876 | { "cibid", 0x24, PROCESSOR_V850E3V5_UP }, | |
877 | { "cibii", 0x20, PROCESSOR_V850E3V5_UP }, | |
878 | { "cibiwbd", 0x26, PROCESSOR_V850E3V5_UP }, | |
879 | { "cibwbd", 0x27, PROCESSOR_V850E3V5_UP }, | |
880 | { "cildd", 0x65, PROCESSOR_V850E3V5_UP }, | |
881 | { "cildi", 0x61, PROCESSOR_V850E3V5_UP }, | |
882 | { "cistd", 0x64, PROCESSOR_V850E3V5_UP }, | |
883 | { "cisti", 0x60, PROCESSOR_V850E3V5_UP }, | |
884 | }; | |
885 | ||
886 | #define CACHEOP_NAME_CNT \ | |
887 | (sizeof (cacheop_names) / sizeof (struct reg_name)) | |
888 | ||
889 | static const struct reg_name prefop_names[] = | |
890 | { | |
891 | { "prefd", 0x04, PROCESSOR_V850E3V5_UP }, | |
892 | { "prefi", 0x00, PROCESSOR_V850E3V5_UP }, | |
893 | }; | |
894 | ||
895 | #define PREFOP_NAME_CNT \ | |
896 | (sizeof (prefop_names) / sizeof (struct reg_name)) | |
897 | ||
898 | static const struct reg_name vector_registers[] = | |
899 | { | |
900 | { "vr0", 0, PROCESSOR_V850E3V5_UP }, | |
901 | { "vr1", 1, PROCESSOR_V850E3V5_UP }, | |
902 | { "vr10", 10, PROCESSOR_V850E3V5_UP }, | |
903 | { "vr11", 11, PROCESSOR_V850E3V5_UP }, | |
904 | { "vr12", 12, PROCESSOR_V850E3V5_UP }, | |
905 | { "vr13", 13, PROCESSOR_V850E3V5_UP }, | |
906 | { "vr14", 14, PROCESSOR_V850E3V5_UP }, | |
907 | { "vr15", 15, PROCESSOR_V850E3V5_UP }, | |
908 | { "vr16", 16, PROCESSOR_V850E3V5_UP }, | |
909 | { "vr17", 17, PROCESSOR_V850E3V5_UP }, | |
910 | { "vr18", 18, PROCESSOR_V850E3V5_UP }, | |
911 | { "vr19", 19, PROCESSOR_V850E3V5_UP }, | |
912 | { "vr2", 2, PROCESSOR_V850E3V5_UP }, | |
913 | { "vr20", 20, PROCESSOR_V850E3V5_UP }, | |
914 | { "vr21", 21, PROCESSOR_V850E3V5_UP }, | |
915 | { "vr22", 22, PROCESSOR_V850E3V5_UP }, | |
916 | { "vr23", 23, PROCESSOR_V850E3V5_UP }, | |
917 | { "vr24", 24, PROCESSOR_V850E3V5_UP }, | |
918 | { "vr25", 25, PROCESSOR_V850E3V5_UP }, | |
919 | { "vr26", 26, PROCESSOR_V850E3V5_UP }, | |
920 | { "vr27", 27, PROCESSOR_V850E3V5_UP }, | |
921 | { "vr28", 28, PROCESSOR_V850E3V5_UP }, | |
922 | { "vr29", 29, PROCESSOR_V850E3V5_UP }, | |
923 | { "vr3", 3, PROCESSOR_V850E3V5_UP }, | |
924 | { "vr30", 30, PROCESSOR_V850E3V5_UP }, | |
925 | { "vr31", 31, PROCESSOR_V850E3V5_UP }, | |
926 | { "vr4", 4, PROCESSOR_V850E3V5_UP }, | |
927 | { "vr5", 5, PROCESSOR_V850E3V5_UP }, | |
928 | { "vr6", 6, PROCESSOR_V850E3V5_UP }, | |
929 | { "vr7", 7, PROCESSOR_V850E3V5_UP }, | |
930 | { "vr8", 8, PROCESSOR_V850E3V5_UP }, | |
931 | { "vr9", 9, PROCESSOR_V850E3V5_UP }, | |
932 | }; | |
933 | ||
934 | #define VREG_NAME_CNT \ | |
935 | (sizeof (vector_registers) / sizeof (struct reg_name)) | |
936 | ||
28e4f854 | 937 | /* Do a binary search of the given register table to see if NAME is a |
33eaf5de | 938 | valid register name. Return the register number from the array on |
28e4f854 | 939 | success, or -1 on failure. */ |
252b5132 RH |
940 | |
941 | static int | |
ea1562b3 NC |
942 | reg_name_search (const struct reg_name *regs, |
943 | int regcount, | |
944 | const char *name, | |
5b7c81bd | 945 | bool accept_numbers) |
252b5132 RH |
946 | { |
947 | int middle, low, high; | |
948 | int cmp; | |
28e4f854 | 949 | symbolS *symbolP; |
252b5132 RH |
950 | |
951 | /* If the register name is a symbol, then evaluate it. */ | |
952 | if ((symbolP = symbol_find (name)) != NULL) | |
953 | { | |
954 | /* If the symbol is an alias for another name then use that. | |
955 | If the symbol is an alias for a number, then return the number. */ | |
a77f5182 | 956 | if (symbol_equated_p (symbolP)) |
ea1562b3 NC |
957 | name |
958 | = S_GET_NAME (symbol_get_value_expression (symbolP)->X_add_symbol); | |
252b5132 RH |
959 | else if (accept_numbers) |
960 | { | |
961 | int reg = S_GET_VALUE (symbolP); | |
1cd986c5 | 962 | return reg; |
252b5132 RH |
963 | } |
964 | ||
965 | /* Otherwise drop through and try parsing name normally. */ | |
966 | } | |
28e4f854 | 967 | |
252b5132 RH |
968 | low = 0; |
969 | high = regcount - 1; | |
970 | ||
971 | do | |
972 | { | |
973 | middle = (low + high) / 2; | |
974 | cmp = strcasecmp (name, regs[middle].name); | |
975 | if (cmp < 0) | |
976 | high = middle - 1; | |
977 | else if (cmp > 0) | |
978 | low = middle + 1; | |
979 | else | |
1cd986c5 NC |
980 | return ((regs[middle].processors & processor_mask) |
981 | ? regs[middle].value | |
982 | : -1); | |
252b5132 RH |
983 | } |
984 | while (low <= high); | |
985 | return -1; | |
986 | } | |
987 | ||
252b5132 | 988 | /* Summary of register_name(). |
ec178e1b | 989 | |
77c6dd37 | 990 | in: Input_line_pointer points to 1st char of operand. |
ec178e1b | 991 | |
77c6dd37 NC |
992 | out: An expressionS. |
993 | The operand may have been a register: in this case, X_op == O_register, | |
994 | X_add_number is set to the register number, and truth is returned. | |
995 | Input_line_pointer->(next non-blank) char after operand, or is in | |
996 | its original state. */ | |
28e4f854 | 997 | |
5b7c81bd | 998 | static bool |
ea1562b3 | 999 | register_name (expressionS *expressionP) |
252b5132 | 1000 | { |
28e4f854 KH |
1001 | int reg_number; |
1002 | char *name; | |
1003 | char *start; | |
1004 | char c; | |
252b5132 | 1005 | |
28e4f854 | 1006 | /* Find the spelling of the operand. */ |
d02603dc NC |
1007 | start = input_line_pointer; |
1008 | c = get_symbol_name (&name); | |
252b5132 RH |
1009 | |
1010 | reg_number = reg_name_search (pre_defined_registers, REG_NAME_CNT, | |
5b7c81bd | 1011 | name, false); |
252b5132 | 1012 | |
28e4f854 | 1013 | /* Put back the delimiting char. */ |
d02603dc | 1014 | (void) restore_line_pointer (c); |
28e4f854 | 1015 | |
1cd986c5 NC |
1016 | expressionP->X_add_symbol = NULL; |
1017 | expressionP->X_op_symbol = NULL; | |
1018 | ||
28e4f854 KH |
1019 | /* Look to see if it's in the register table. */ |
1020 | if (reg_number >= 0) | |
252b5132 | 1021 | { |
ec178e1b | 1022 | expressionP->X_op = O_register; |
252b5132 RH |
1023 | expressionP->X_add_number = reg_number; |
1024 | ||
5b7c81bd | 1025 | return true; |
252b5132 | 1026 | } |
28e4f854 | 1027 | |
1cd986c5 NC |
1028 | /* Reset the line as if we had not done anything. */ |
1029 | input_line_pointer = start; | |
1030 | ||
1031 | expressionP->X_op = O_illegal; | |
1032 | ||
5b7c81bd | 1033 | return false; |
252b5132 RH |
1034 | } |
1035 | ||
1036 | /* Summary of system_register_name(). | |
ec178e1b | 1037 | |
77c6dd37 | 1038 | in: INPUT_LINE_POINTER points to 1st char of operand. |
ec178e1b AM |
1039 | EXPRESSIONP points to an expression structure to be filled in. |
1040 | ACCEPT_NUMBERS is true iff numerical register names may be used. | |
ec178e1b | 1041 | |
77c6dd37 NC |
1042 | out: An expressionS structure in expressionP. |
1043 | The operand may have been a register: in this case, X_op == O_register, | |
1044 | X_add_number is set to the register number, and truth is returned. | |
1045 | Input_line_pointer->(next non-blank) char after operand, or is in | |
1046 | its original state. */ | |
28e4f854 | 1047 | |
5b7c81bd | 1048 | static bool |
ea1562b3 | 1049 | system_register_name (expressionS *expressionP, |
5b7c81bd | 1050 | bool accept_numbers) |
252b5132 | 1051 | { |
28e4f854 KH |
1052 | int reg_number; |
1053 | char *name; | |
1054 | char *start; | |
1055 | char c; | |
252b5132 | 1056 | |
28e4f854 | 1057 | /* Find the spelling of the operand. */ |
d02603dc NC |
1058 | start = input_line_pointer; |
1059 | c = get_symbol_name (&name); | |
252b5132 RH |
1060 | reg_number = reg_name_search (system_registers, SYSREG_NAME_CNT, name, |
1061 | accept_numbers); | |
1062 | ||
28e4f854 | 1063 | /* Put back the delimiting char. */ |
d02603dc | 1064 | (void) restore_line_pointer (c); |
28e4f854 | 1065 | |
252b5132 RH |
1066 | if (reg_number < 0 |
1067 | && accept_numbers) | |
1068 | { | |
28e4f854 KH |
1069 | /* Reset input_line pointer. */ |
1070 | input_line_pointer = start; | |
252b5132 | 1071 | |
3882b010 | 1072 | if (ISDIGIT (*input_line_pointer)) |
252b5132 | 1073 | { |
1cd986c5 | 1074 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); |
252b5132 RH |
1075 | } |
1076 | } | |
28e4f854 | 1077 | |
1cd986c5 NC |
1078 | expressionP->X_add_symbol = NULL; |
1079 | expressionP->X_op_symbol = NULL; | |
1080 | ||
28e4f854 KH |
1081 | /* Look to see if it's in the register table. */ |
1082 | if (reg_number >= 0) | |
252b5132 | 1083 | { |
ec178e1b | 1084 | expressionP->X_op = O_register; |
252b5132 RH |
1085 | expressionP->X_add_number = reg_number; |
1086 | ||
5b7c81bd | 1087 | return true; |
252b5132 | 1088 | } |
28e4f854 | 1089 | |
1cd986c5 NC |
1090 | /* Reset the line as if we had not done anything. */ |
1091 | input_line_pointer = start; | |
1092 | ||
1093 | expressionP->X_op = O_illegal; | |
1094 | ||
5b7c81bd | 1095 | return false; |
252b5132 RH |
1096 | } |
1097 | ||
1098 | /* Summary of cc_name(). | |
ec178e1b | 1099 | |
77c6dd37 | 1100 | in: INPUT_LINE_POINTER points to 1st char of operand. |
ec178e1b | 1101 | |
77c6dd37 NC |
1102 | out: An expressionS. |
1103 | The operand may have been a register: in this case, X_op == O_register, | |
1104 | X_add_number is set to the register number, and truth is returned. | |
1105 | Input_line_pointer->(next non-blank) char after operand, or is in | |
1106 | its original state. */ | |
28e4f854 | 1107 | |
5b7c81bd | 1108 | static bool |
1cd986c5 | 1109 | cc_name (expressionS *expressionP, |
5b7c81bd | 1110 | bool accept_numbers) |
252b5132 | 1111 | { |
28e4f854 KH |
1112 | int reg_number; |
1113 | char *name; | |
1114 | char *start; | |
1115 | char c; | |
252b5132 | 1116 | |
28e4f854 | 1117 | /* Find the spelling of the operand. */ |
d02603dc NC |
1118 | start = input_line_pointer; |
1119 | c = get_symbol_name (&name); | |
1cd986c5 | 1120 | reg_number = reg_name_search (cc_names, CC_NAME_CNT, name, accept_numbers); |
252b5132 | 1121 | |
28e4f854 | 1122 | /* Put back the delimiting char. */ |
d02603dc | 1123 | (void) restore_line_pointer (c); |
28e4f854 | 1124 | |
1cd986c5 NC |
1125 | if (reg_number < 0 |
1126 | && accept_numbers) | |
1127 | { | |
1128 | /* Reset input_line pointer. */ | |
1129 | input_line_pointer = start; | |
1130 | ||
1131 | if (ISDIGIT (*input_line_pointer)) | |
1132 | { | |
1133 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | expressionP->X_add_symbol = NULL; | |
1138 | expressionP->X_op_symbol = NULL; | |
1139 | ||
28e4f854 KH |
1140 | /* Look to see if it's in the register table. */ |
1141 | if (reg_number >= 0) | |
252b5132 | 1142 | { |
ec178e1b | 1143 | expressionP->X_op = O_constant; |
252b5132 RH |
1144 | expressionP->X_add_number = reg_number; |
1145 | ||
5b7c81bd | 1146 | return true; |
252b5132 | 1147 | } |
1cd986c5 NC |
1148 | |
1149 | /* Reset the line as if we had not done anything. */ | |
1150 | input_line_pointer = start; | |
1151 | ||
1152 | expressionP->X_op = O_illegal; | |
1153 | expressionP->X_add_number = 0; | |
1154 | ||
5b7c81bd | 1155 | return false; |
1cd986c5 NC |
1156 | } |
1157 | ||
5b7c81bd | 1158 | static bool |
1cd986c5 | 1159 | float_cc_name (expressionS *expressionP, |
5b7c81bd | 1160 | bool accept_numbers) |
1cd986c5 NC |
1161 | { |
1162 | int reg_number; | |
1163 | char *name; | |
1164 | char *start; | |
1165 | char c; | |
1166 | ||
1167 | /* Find the spelling of the operand. */ | |
d02603dc NC |
1168 | start = input_line_pointer; |
1169 | c = get_symbol_name (&name); | |
1cd986c5 NC |
1170 | reg_number = reg_name_search (float_cc_names, FLOAT_CC_NAME_CNT, name, accept_numbers); |
1171 | ||
1172 | /* Put back the delimiting char. */ | |
d02603dc | 1173 | (void) restore_line_pointer (c); |
1cd986c5 NC |
1174 | |
1175 | if (reg_number < 0 | |
1176 | && accept_numbers) | |
252b5132 | 1177 | { |
1cd986c5 | 1178 | /* Reset input_line pointer. */ |
252b5132 | 1179 | input_line_pointer = start; |
28e4f854 | 1180 | |
1cd986c5 NC |
1181 | if (ISDIGIT (*input_line_pointer)) |
1182 | { | |
1183 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | expressionP->X_add_symbol = NULL; | |
1188 | expressionP->X_op_symbol = NULL; | |
1189 | ||
1190 | /* Look to see if it's in the register table. */ | |
1191 | if (reg_number >= 0) | |
1192 | { | |
1193 | expressionP->X_op = O_constant; | |
1194 | expressionP->X_add_number = reg_number; | |
1195 | ||
5b7c81bd | 1196 | return true; |
252b5132 | 1197 | } |
1cd986c5 NC |
1198 | |
1199 | /* Reset the line as if we had not done anything. */ | |
1200 | input_line_pointer = start; | |
1201 | ||
1202 | expressionP->X_op = O_illegal; | |
1203 | expressionP->X_add_number = 0; | |
1204 | ||
5b7c81bd | 1205 | return false; |
252b5132 RH |
1206 | } |
1207 | ||
5b7c81bd | 1208 | static bool |
78c8d46c | 1209 | cacheop_name (expressionS * expressionP, |
5b7c81bd | 1210 | bool accept_numbers) |
78c8d46c NC |
1211 | { |
1212 | int reg_number; | |
1213 | char *name; | |
1214 | char *start; | |
1215 | char c; | |
1216 | ||
1217 | /* Find the spelling of the operand. */ | |
d02603dc NC |
1218 | start = input_line_pointer; |
1219 | c = get_symbol_name (&name); | |
78c8d46c NC |
1220 | reg_number = reg_name_search (cacheop_names, CACHEOP_NAME_CNT, name, accept_numbers); |
1221 | ||
1222 | /* Put back the delimiting char. */ | |
d02603dc | 1223 | (void) restore_line_pointer (c); |
78c8d46c NC |
1224 | |
1225 | if (reg_number < 0 | |
1226 | && accept_numbers) | |
1227 | { | |
1228 | /* Reset input_line pointer. */ | |
1229 | input_line_pointer = start; | |
1230 | ||
1231 | if (ISDIGIT (*input_line_pointer)) | |
1232 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); | |
1233 | } | |
1234 | ||
1235 | expressionP->X_add_symbol = NULL; | |
1236 | expressionP->X_op_symbol = NULL; | |
1237 | ||
1238 | /* Look to see if it's in the register table. */ | |
1239 | if (reg_number >= 0) | |
1240 | { | |
1241 | expressionP->X_op = O_constant; | |
1242 | expressionP->X_add_number = reg_number; | |
1243 | ||
5b7c81bd | 1244 | return true; |
78c8d46c NC |
1245 | } |
1246 | ||
1247 | /* Reset the line as if we had not done anything. */ | |
1248 | input_line_pointer = start; | |
1249 | ||
1250 | expressionP->X_op = O_illegal; | |
1251 | expressionP->X_add_number = 0; | |
1252 | ||
5b7c81bd | 1253 | return false; |
78c8d46c NC |
1254 | } |
1255 | ||
5b7c81bd | 1256 | static bool |
78c8d46c | 1257 | prefop_name (expressionS * expressionP, |
5b7c81bd | 1258 | bool accept_numbers) |
78c8d46c NC |
1259 | { |
1260 | int reg_number; | |
1261 | char *name; | |
1262 | char *start; | |
1263 | char c; | |
1264 | ||
1265 | /* Find the spelling of the operand. */ | |
d02603dc NC |
1266 | start = input_line_pointer; |
1267 | c = get_symbol_name (&name); | |
78c8d46c NC |
1268 | reg_number = reg_name_search (prefop_names, PREFOP_NAME_CNT, name, accept_numbers); |
1269 | ||
1270 | /* Put back the delimiting char. */ | |
d02603dc | 1271 | (void) restore_line_pointer (c); |
78c8d46c NC |
1272 | |
1273 | if (reg_number < 0 | |
1274 | && accept_numbers) | |
1275 | { | |
1276 | /* Reset input_line pointer. */ | |
1277 | input_line_pointer = start; | |
1278 | ||
1279 | if (ISDIGIT (*input_line_pointer)) | |
1280 | reg_number = strtol (input_line_pointer, &input_line_pointer, 0); | |
1281 | } | |
1282 | ||
1283 | expressionP->X_add_symbol = NULL; | |
1284 | expressionP->X_op_symbol = NULL; | |
1285 | ||
1286 | /* Look to see if it's in the register table. */ | |
1287 | if (reg_number >= 0) | |
1288 | { | |
1289 | expressionP->X_op = O_constant; | |
1290 | expressionP->X_add_number = reg_number; | |
1291 | ||
5b7c81bd | 1292 | return true; |
78c8d46c NC |
1293 | } |
1294 | ||
1295 | /* Reset the line as if we had not done anything. */ | |
1296 | input_line_pointer = start; | |
1297 | ||
1298 | expressionP->X_op = O_illegal; | |
1299 | expressionP->X_add_number = 0; | |
1300 | ||
5b7c81bd | 1301 | return false; |
78c8d46c NC |
1302 | } |
1303 | ||
5b7c81bd | 1304 | static bool |
78c8d46c NC |
1305 | vector_register_name (expressionS *expressionP) |
1306 | { | |
1307 | int reg_number; | |
1308 | char *name; | |
1309 | char *start; | |
1310 | char c; | |
1311 | ||
1312 | /* Find the spelling of the operand. */ | |
d02603dc NC |
1313 | start = input_line_pointer; |
1314 | c = get_symbol_name (&name); | |
78c8d46c NC |
1315 | |
1316 | reg_number = reg_name_search (vector_registers, VREG_NAME_CNT, | |
5b7c81bd | 1317 | name, false); |
78c8d46c NC |
1318 | |
1319 | /* Put back the delimiting char. */ | |
d02603dc | 1320 | (void) restore_line_pointer (c); |
78c8d46c NC |
1321 | |
1322 | expressionP->X_add_symbol = NULL; | |
1323 | expressionP->X_op_symbol = NULL; | |
1324 | ||
1325 | /* Look to see if it's in the register table. */ | |
1326 | if (reg_number >= 0) | |
1327 | { | |
1328 | expressionP->X_op = O_register; | |
1329 | expressionP->X_add_number = reg_number; | |
1330 | ||
5b7c81bd | 1331 | return true; |
78c8d46c NC |
1332 | } |
1333 | ||
1334 | /* Reset the line as if we had not done anything. */ | |
1335 | input_line_pointer = start; | |
1336 | ||
1337 | expressionP->X_op = O_illegal; | |
1338 | ||
5b7c81bd | 1339 | return false; |
78c8d46c NC |
1340 | } |
1341 | ||
252b5132 | 1342 | static void |
ea1562b3 | 1343 | skip_white_space (void) |
252b5132 | 1344 | { |
28e4f854 KH |
1345 | while (*input_line_pointer == ' ' |
1346 | || *input_line_pointer == '\t') | |
1347 | ++input_line_pointer; | |
252b5132 RH |
1348 | } |
1349 | ||
1350 | /* Summary of parse_register_list (). | |
ec178e1b | 1351 | |
77c6dd37 | 1352 | in: INPUT_LINE_POINTER points to 1st char of a list of registers. |
ec178e1b AM |
1353 | INSN is the partially constructed instruction. |
1354 | OPERAND is the operand being inserted. | |
1355 | ||
77c6dd37 | 1356 | out: NULL if the parse completed successfully, otherwise a |
ec178e1b AM |
1357 | pointer to an error message is returned. If the parse |
1358 | completes the correct bit fields in the instruction | |
1359 | will be filled in. | |
1360 | ||
77c6dd37 | 1361 | Parses register lists with the syntax: |
ec178e1b | 1362 | |
77c6dd37 NC |
1363 | { rX } |
1364 | { rX, rY } | |
1365 | { rX - rY } | |
1366 | { rX - rY, rZ } | |
1367 | etc | |
ec178e1b | 1368 | |
33eaf5de | 1369 | and also parses constant expressions whose bits indicate the |
77c6dd37 | 1370 | registers in the lists. The LSB in the expression refers to |
33b7f697 | 1371 | the lowest numbered permissible register in the register list, |
77c6dd37 NC |
1372 | and so on upwards. System registers are considered to be very |
1373 | high numbers. */ | |
28e4f854 | 1374 | |
6d4af3c2 | 1375 | static const char * |
ea1562b3 NC |
1376 | parse_register_list (unsigned long *insn, |
1377 | const struct v850_operand *operand) | |
252b5132 | 1378 | { |
ea1562b3 NC |
1379 | static int type1_regs[32] = |
1380 | { | |
28e4f854 KH |
1381 | 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
1382 | 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 | |
1383 | }; | |
1cd986c5 | 1384 | |
28e4f854 | 1385 | int *regs; |
252b5132 RH |
1386 | expressionS exp; |
1387 | ||
28e4f854 | 1388 | /* Select a register array to parse. */ |
252b5132 RH |
1389 | switch (operand->shift) |
1390 | { | |
1391 | case 0xffe00001: regs = type1_regs; break; | |
252b5132 RH |
1392 | default: |
1393 | as_bad (_("unknown operand shift: %x\n"), operand->shift); | |
1394 | return _("internal failure in parse_register_list"); | |
1395 | } | |
1396 | ||
1397 | skip_white_space (); | |
1398 | ||
1399 | /* If the expression starts with a curly brace it is a register list. | |
33eaf5de | 1400 | Otherwise it is a constant expression, whose bits indicate which |
252b5132 | 1401 | registers are to be included in the list. */ |
28e4f854 | 1402 | if (*input_line_pointer != '{') |
252b5132 | 1403 | { |
252b5132 RH |
1404 | int reg; |
1405 | int i; | |
28e4f854 KH |
1406 | |
1407 | expression (&exp); | |
1408 | ||
252b5132 RH |
1409 | if (exp.X_op != O_constant) |
1410 | return _("constant expression or register list expected"); | |
1411 | ||
1412 | if (regs == type1_regs) | |
1413 | { | |
1414 | if (exp.X_add_number & 0xFFFFF000) | |
1415 | return _("high bits set in register list expression"); | |
28e4f854 KH |
1416 | |
1417 | for (reg = 20; reg < 32; reg++) | |
252b5132 RH |
1418 | if (exp.X_add_number & (1 << (reg - 20))) |
1419 | { | |
1420 | for (i = 0; i < 32; i++) | |
1421 | if (regs[i] == reg) | |
28e4f854 | 1422 | *insn |= (1 << i); |
252b5132 RH |
1423 | } |
1424 | } | |
252b5132 RH |
1425 | |
1426 | return NULL; | |
1427 | } | |
1428 | ||
28e4f854 | 1429 | input_line_pointer++; |
252b5132 RH |
1430 | |
1431 | /* Parse the register list until a terminator (closing curly brace or | |
1432 | new-line) is found. */ | |
1433 | for (;;) | |
1434 | { | |
1cd986c5 NC |
1435 | skip_white_space (); |
1436 | ||
28e4f854 | 1437 | if (register_name (&exp)) |
252b5132 | 1438 | { |
28e4f854 KH |
1439 | int i; |
1440 | ||
252b5132 RH |
1441 | /* Locate the given register in the list, and if it is there, |
1442 | insert the corresponding bit into the instruction. */ | |
1443 | for (i = 0; i < 32; i++) | |
1444 | { | |
28e4f854 | 1445 | if (regs[i] == exp.X_add_number) |
252b5132 | 1446 | { |
8e822017 | 1447 | *insn |= 1u << i; |
252b5132 RH |
1448 | break; |
1449 | } | |
1450 | } | |
1451 | ||
1452 | if (i == 32) | |
77c6dd37 | 1453 | return _("illegal register included in list"); |
252b5132 | 1454 | } |
5b7c81bd | 1455 | else if (system_register_name (&exp, true)) |
252b5132 RH |
1456 | { |
1457 | if (regs == type1_regs) | |
1458 | { | |
1459 | return _("system registers cannot be included in list"); | |
1460 | } | |
252b5132 | 1461 | } |
1cd986c5 NC |
1462 | |
1463 | if (*input_line_pointer == '}') | |
252b5132 | 1464 | { |
28e4f854 | 1465 | input_line_pointer++; |
252b5132 RH |
1466 | break; |
1467 | } | |
28e4f854 | 1468 | else if (*input_line_pointer == ',') |
252b5132 | 1469 | { |
28e4f854 | 1470 | input_line_pointer++; |
252b5132 RH |
1471 | continue; |
1472 | } | |
28e4f854 | 1473 | else if (*input_line_pointer == '-') |
252b5132 | 1474 | { |
28e4f854 KH |
1475 | /* We have encountered a range of registers: rX - rY. */ |
1476 | int j; | |
252b5132 RH |
1477 | expressionS exp2; |
1478 | ||
1479 | /* Skip the dash. */ | |
28e4f854 | 1480 | ++input_line_pointer; |
252b5132 RH |
1481 | |
1482 | /* Get the second register in the range. */ | |
28e4f854 | 1483 | if (! register_name (&exp2)) |
252b5132 RH |
1484 | { |
1485 | return _("second register should follow dash in register list"); | |
1cd986c5 NC |
1486 | } |
1487 | ||
1488 | if (exp.X_add_number > exp2.X_add_number) | |
1489 | { | |
5648d7c7 | 1490 | return _("second register should be greater than first register"); |
252b5132 RH |
1491 | } |
1492 | ||
1493 | /* Add the rest of the registers in the range. */ | |
1494 | for (j = exp.X_add_number + 1; j <= exp2.X_add_number; j++) | |
1495 | { | |
28e4f854 KH |
1496 | int i; |
1497 | ||
252b5132 RH |
1498 | /* Locate the given register in the list, and if it is there, |
1499 | insert the corresponding bit into the instruction. */ | |
1500 | for (i = 0; i < 32; i++) | |
1501 | { | |
28e4f854 | 1502 | if (regs[i] == j) |
252b5132 | 1503 | { |
28e4f854 | 1504 | *insn |= (1 << i); |
252b5132 RH |
1505 | break; |
1506 | } | |
1507 | } | |
1508 | ||
1509 | if (i == 32) | |
1510 | return _("illegal register included in list"); | |
1511 | } | |
1cd986c5 NC |
1512 | |
1513 | exp = exp2; | |
252b5132 RH |
1514 | } |
1515 | else | |
77c6dd37 | 1516 | break; |
252b5132 RH |
1517 | } |
1518 | ||
1519 | return NULL; | |
1520 | } | |
1521 | ||
5a38dc70 | 1522 | const char *md_shortopts = "m:"; |
252b5132 | 1523 | |
ea1562b3 NC |
1524 | struct option md_longopts[] = |
1525 | { | |
1cd986c5 NC |
1526 | #define OPTION_DISP_SIZE_DEFAULT_22 (OPTION_MD_BASE) |
1527 | {"disp-size-default-22", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_22}, | |
1528 | #define OPTION_DISP_SIZE_DEFAULT_32 (OPTION_MD_BASE + 1) | |
1529 | {"disp-size-default-32", no_argument, NULL, OPTION_DISP_SIZE_DEFAULT_32}, | |
252b5132 RH |
1530 | {NULL, no_argument, NULL, 0} |
1531 | }; | |
252b5132 | 1532 | |
28e4f854 | 1533 | size_t md_longopts_size = sizeof (md_longopts); |
252b5132 | 1534 | |
5b7c81bd | 1535 | static bool v850_data_8 = false; |
685080f2 | 1536 | |
252b5132 | 1537 | void |
ea1562b3 | 1538 | md_show_usage (FILE *stream) |
252b5132 RH |
1539 | { |
1540 | fprintf (stream, _(" V850 options:\n")); | |
1541 | fprintf (stream, _(" -mwarn-signed-overflow Warn if signed immediate values overflow\n")); | |
1542 | fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n")); | |
1543 | fprintf (stream, _(" -mv850 The code is targeted at the v850\n")); | |
1544 | fprintf (stream, _(" -mv850e The code is targeted at the v850e\n")); | |
8ad30312 | 1545 | fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n")); |
1cd986c5 NC |
1546 | fprintf (stream, _(" -mv850e2 The code is targeted at the v850e2\n")); |
1547 | fprintf (stream, _(" -mv850e2v3 The code is targeted at the v850e2v3\n")); | |
78c8d46c NC |
1548 | fprintf (stream, _(" -mv850e2v4 Alias for -mv850e3v5\n")); |
1549 | fprintf (stream, _(" -mv850e3v5 The code is targeted at the v850e3v5\n")); | |
86aba9db | 1550 | fprintf (stream, _(" -mrelax Enable relaxation\n")); |
1cd986c5 NC |
1551 | fprintf (stream, _(" --disp-size-default-22 branch displacement with unknown size is 22 bits (default)\n")); |
1552 | fprintf (stream, _(" --disp-size-default-32 branch displacement with unknown size is 32 bits\n")); | |
1553 | fprintf (stream, _(" -mextension enable extension opcode support\n")); | |
1554 | fprintf (stream, _(" -mno-bcond17 disable b<cond> disp17 instruction\n")); | |
1555 | fprintf (stream, _(" -mno-stld23 disable st/ld offset23 instruction\n")); | |
de863c74 NC |
1556 | fprintf (stream, _(" -mgcc-abi Mark the binary as using the old GCC ABI\n")); |
1557 | fprintf (stream, _(" -mrh850-abi Mark the binary as using the RH850 ABI (default)\n")); | |
1558 | fprintf (stream, _(" -m8byte-align Mark the binary as using 64-bit alignment\n")); | |
1559 | fprintf (stream, _(" -m4byte-align Mark the binary as using 32-bit alignment (default)\n")); | |
685080f2 NC |
1560 | fprintf (stream, _(" -msoft-float Mark the binary as not using FP insns (default for pre e2v3)\n")); |
1561 | fprintf (stream, _(" -mhard-float Mark the binary as using FP insns (default for e2v3 and up)\n")); | |
252b5132 RH |
1562 | } |
1563 | ||
1564 | int | |
17b9d67d | 1565 | md_parse_option (int c, const char *arg) |
252b5132 RH |
1566 | { |
1567 | if (c != 'm') | |
1cd986c5 NC |
1568 | { |
1569 | switch (c) | |
1570 | { | |
1571 | case OPTION_DISP_SIZE_DEFAULT_22: | |
1572 | default_disp_size = 22; | |
1573 | return 1; | |
1574 | ||
1575 | case OPTION_DISP_SIZE_DEFAULT_32: | |
1576 | default_disp_size = 32; | |
1577 | return 1; | |
1578 | } | |
1579 | return 0; | |
1580 | } | |
252b5132 RH |
1581 | |
1582 | if (strcmp (arg, "warn-signed-overflow") == 0) | |
5b7c81bd | 1583 | warn_signed_overflows = true; |
329e276d | 1584 | |
252b5132 | 1585 | else if (strcmp (arg, "warn-unsigned-overflow") == 0) |
5b7c81bd | 1586 | warn_unsigned_overflows = true; |
329e276d | 1587 | |
252b5132 RH |
1588 | else if (strcmp (arg, "v850") == 0) |
1589 | { | |
1590 | machine = 0; | |
1cd986c5 | 1591 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); |
252b5132 RH |
1592 | } |
1593 | else if (strcmp (arg, "v850e") == 0) | |
1594 | { | |
1595 | machine = bfd_mach_v850e; | |
1cd986c5 | 1596 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); |
252b5132 | 1597 | } |
8ad30312 NC |
1598 | else if (strcmp (arg, "v850e1") == 0) |
1599 | { | |
1600 | machine = bfd_mach_v850e1; | |
1cd986c5 | 1601 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); |
8ad30312 | 1602 | } |
1cd986c5 | 1603 | else if (strcmp (arg, "v850e2") == 0) |
252b5132 | 1604 | { |
1cd986c5 NC |
1605 | machine = bfd_mach_v850e2; |
1606 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); | |
1607 | } | |
1608 | else if (strcmp (arg, "v850e2v3") == 0) | |
1609 | { | |
1610 | machine = bfd_mach_v850e2v3; | |
1611 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); | |
1612 | } | |
78c8d46c NC |
1613 | else if (strcmp (arg, "v850e2v4") == 0) |
1614 | { | |
1615 | machine = bfd_mach_v850e3v5; | |
1616 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); | |
1617 | } | |
1618 | else if (strcmp (arg, "v850e3v5") == 0) | |
1619 | { | |
1620 | machine = bfd_mach_v850e3v5; | |
1621 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); | |
1622 | } | |
1cd986c5 NC |
1623 | else if (strcmp (arg, "extension") == 0) |
1624 | { | |
5bb3703f | 1625 | processor_mask |= PROCESSOR_OPTION_EXTENSION | PROCESSOR_OPTION_ALIAS; |
1cd986c5 NC |
1626 | } |
1627 | else if (strcmp (arg, "no-bcond17") == 0) | |
1628 | { | |
1629 | no_bcond17 = 1; | |
1630 | } | |
1631 | else if (strcmp (arg, "no-stld23") == 0) | |
1632 | { | |
1633 | no_stld23 = 1; | |
252b5132 | 1634 | } |
86aba9db NC |
1635 | else if (strcmp (arg, "relax") == 0) |
1636 | v850_relax = 1; | |
de863c74 NC |
1637 | else if (strcmp (arg, "gcc-abi") == 0) |
1638 | { | |
1639 | v850_target_arch = bfd_arch_v850; | |
1640 | v850_target_format = "elf32-v850"; | |
1641 | } | |
1642 | else if (strcmp (arg, "rh850-abi") == 0) | |
1643 | { | |
1644 | v850_target_arch = bfd_arch_v850_rh850; | |
1645 | v850_target_format = "elf32-v850-rh850"; | |
1646 | } | |
685080f2 | 1647 | else if (strcmp (arg, "8byte-align") == 0) |
a26de52c | 1648 | { |
5b7c81bd | 1649 | v850_data_8 = true; |
a26de52c NC |
1650 | v850_e_flags |= EF_RH850_DATA_ALIGN8; |
1651 | } | |
685080f2 | 1652 | else if (strcmp (arg, "4byte-align") == 0) |
a26de52c | 1653 | { |
5b7c81bd | 1654 | v850_data_8 = false; |
a26de52c NC |
1655 | v850_e_flags &= ~ EF_RH850_DATA_ALIGN8; |
1656 | } | |
685080f2 NC |
1657 | else if (strcmp (arg, "soft-float") == 0) |
1658 | soft_float = 1; | |
1659 | else if (strcmp (arg, "hard-float") == 0) | |
1660 | soft_float = 0; | |
252b5132 | 1661 | else |
329e276d | 1662 | return 0; |
28e4f854 | 1663 | |
252b5132 RH |
1664 | return 1; |
1665 | } | |
1666 | ||
1667 | symbolS * | |
ea1562b3 | 1668 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
252b5132 RH |
1669 | { |
1670 | return 0; | |
1671 | } | |
1672 | ||
6d4af3c2 | 1673 | const char * |
ea1562b3 | 1674 | md_atof (int type, char *litp, int *sizep) |
252b5132 | 1675 | { |
5b7c81bd | 1676 | return ieee_md_atof (type, litp, sizep, false); |
252b5132 RH |
1677 | } |
1678 | ||
252b5132 | 1679 | /* Very gross. */ |
28e4f854 | 1680 | |
252b5132 | 1681 | void |
ea1562b3 NC |
1682 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, |
1683 | asection *sec, | |
1684 | fragS *fragP) | |
252b5132 | 1685 | { |
8ad7c533 NC |
1686 | union u |
1687 | { | |
1688 | bfd_reloc_code_real_type fx_r_type; | |
1689 | char * fr_opcode; | |
1690 | } | |
1691 | opcode_converter; | |
252b5132 | 1692 | subseg_change (sec, 0); |
28e4f854 | 1693 | |
8ad7c533 | 1694 | opcode_converter.fr_opcode = fragP->fr_opcode; |
1cd986c5 NC |
1695 | |
1696 | subseg_change (sec, 0); | |
1697 | ||
78c8d46c NC |
1698 | if (fragP->fr_subtype == SUBYPTE_LOOP_16_22) |
1699 | { | |
1700 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
1701 | fragP->fr_offset, 1, | |
1702 | BFD_RELOC_UNUSED + opcode_converter.fx_r_type); | |
1703 | fragP->fr_fix += 4; | |
1704 | } | |
1705 | else if (fragP->fr_subtype == SUBYPTE_LOOP_16_22 + 1) | |
1706 | { | |
1707 | unsigned char * buffer = | |
70b1b570 | 1708 | (unsigned char *) (fragP->fr_fix + &fragP->fr_literal[0]); |
78c8d46c NC |
1709 | int loop_reg = (buffer[0] & 0x1f); |
1710 | ||
1711 | /* Add -1.reg. */ | |
1712 | md_number_to_chars ((char *) buffer, 0x025f | (loop_reg << 11), 2); | |
1713 | /* Now create the conditional branch + fixup to the final target. */ | |
1714 | /* 0x000107ea = bne LBL(disp17). */ | |
1715 | md_number_to_chars ((char *) buffer + 2, 0x000107ea, 4); | |
718aefcf | 1716 | fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, |
78c8d46c NC |
1717 | fragP->fr_offset, 1, |
1718 | BFD_RELOC_V850_17_PCREL); | |
1719 | fragP->fr_fix += 6; | |
1720 | } | |
252b5132 | 1721 | /* In range conditional or unconditional branch. */ |
78c8d46c | 1722 | else if (fragP->fr_subtype == SUBYPTE_COND_9_22 |
1cd986c5 NC |
1723 | || fragP->fr_subtype == SUBYPTE_UNCOND_9_22 |
1724 | || fragP->fr_subtype == SUBYPTE_COND_9_22_32 | |
1725 | || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 | |
1726 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22 | |
1727 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 | |
1728 | || fragP->fr_subtype == SUBYPTE_SA_9_22 | |
1729 | || fragP->fr_subtype == SUBYPTE_SA_9_22_32 | |
1730 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22 | |
1731 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32) | |
1732 | ||
252b5132 RH |
1733 | { |
1734 | fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, | |
8ad7c533 NC |
1735 | fragP->fr_offset, 1, |
1736 | BFD_RELOC_UNUSED + opcode_converter.fx_r_type); | |
252b5132 RH |
1737 | fragP->fr_fix += 2; |
1738 | } | |
1cd986c5 NC |
1739 | /* V850e2r-v3 17bit conditional branch. */ |
1740 | else if (fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 1 | |
1741 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 1 | |
1742 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 1 | |
1743 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 1) | |
1744 | { | |
1745 | unsigned char *buffer = | |
70b1b570 | 1746 | (unsigned char *) (fragP->fr_fix + &fragP->fr_literal[0]); |
1cd986c5 NC |
1747 | |
1748 | buffer[0] &= 0x0f; /* Use condition. */ | |
1749 | buffer[0] |= 0xe0; | |
1750 | buffer[1] = 0x07; | |
1751 | ||
1752 | /* Now create the unconditional branch + fixup to the final | |
1753 | target. */ | |
1754 | md_number_to_chars ((char *) buffer + 2, 0x0001, 2); | |
1755 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
1756 | fragP->fr_offset, 1, BFD_RELOC_V850_17_PCREL); | |
1757 | fragP->fr_fix += 4; | |
1758 | } | |
1759 | /* Out of range conditional branch. Emit a branch around a 22bit jump. */ | |
1760 | else if (fragP->fr_subtype == SUBYPTE_COND_9_22 + 1 | |
1761 | || fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 1 | |
3739860c | 1762 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22 + 2 |
1cd986c5 | 1763 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 2) |
252b5132 | 1764 | { |
28e4f854 | 1765 | unsigned char *buffer = |
252b5132 RH |
1766 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); |
1767 | ||
1768 | /* Reverse the condition of the first branch. */ | |
1769 | buffer[0] ^= 0x08; | |
1770 | /* Mask off all the displacement bits. */ | |
1771 | buffer[0] &= 0x8f; | |
1772 | buffer[1] &= 0x07; | |
1773 | /* Now set the displacement bits so that we branch | |
1774 | around the unconditional branch. */ | |
1775 | buffer[0] |= 0x30; | |
1776 | ||
1777 | /* Now create the unconditional branch + fixup to the final | |
1778 | target. */ | |
2132e3a3 | 1779 | md_number_to_chars ((char *) buffer + 2, 0x00000780, 4); |
252b5132 | 1780 | fix_new (fragP, fragP->fr_fix + 2, 4, fragP->fr_symbol, |
1cd986c5 | 1781 | fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); |
252b5132 RH |
1782 | fragP->fr_fix += 6; |
1783 | } | |
1cd986c5 NC |
1784 | /* Out of range conditional branch. Emit a branch around a 32bit jump. */ |
1785 | else if (fragP->fr_subtype == SUBYPTE_COND_9_22_32 + 2 | |
1786 | || fragP->fr_subtype == SUBYPTE_COND_9_17_22_32 + 3) | |
1787 | { | |
1788 | unsigned char *buffer = | |
1789 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); | |
1790 | ||
1791 | /* Reverse the condition of the first branch. */ | |
1792 | buffer[0] ^= 0x08; | |
1793 | /* Mask off all the displacement bits. */ | |
1794 | buffer[0] &= 0x8f; | |
1795 | buffer[1] &= 0x07; | |
1796 | /* Now set the displacement bits so that we branch | |
1797 | around the unconditional branch. */ | |
1798 | buffer[0] |= 0x40; | |
1799 | ||
1800 | /* Now create the unconditional branch + fixup to the final | |
1801 | target. */ | |
1802 | md_number_to_chars ((char *) buffer + 2, 0x02e0, 2); | |
1803 | fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, | |
1804 | fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); | |
1805 | fragP->fr_fix += 8; | |
1806 | } | |
1807 | /* Out of range unconditional branch. Emit a 22bit jump. */ | |
1808 | else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22 + 1 | |
1809 | || fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 1) | |
252b5132 RH |
1810 | { |
1811 | md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x00000780, 4); | |
1812 | fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, | |
1cd986c5 | 1813 | fragP->fr_offset, 1, BFD_RELOC_V850_22_PCREL); |
252b5132 RH |
1814 | fragP->fr_fix += 4; |
1815 | } | |
1cd986c5 NC |
1816 | /* Out of range unconditional branch. Emit a 32bit jump. */ |
1817 | else if (fragP->fr_subtype == SUBYPTE_UNCOND_9_22_32 + 2) | |
1818 | { | |
1819 | md_number_to_chars (fragP->fr_fix + fragP->fr_literal, 0x02e0, 2); | |
1820 | fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, | |
1821 | fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); | |
1822 | fragP->fr_fix += 6; | |
1823 | } | |
1824 | /* Out of range SA conditional branch. Emit a branch to a 22bit jump. */ | |
1825 | else if (fragP->fr_subtype == SUBYPTE_SA_9_22 + 1 | |
1826 | || fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 1 | |
1827 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22 + 2 | |
1828 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 2) | |
1829 | { | |
1830 | unsigned char *buffer = | |
1831 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); | |
1832 | ||
1833 | /* bsa .+4 */ | |
1834 | buffer[0] &= 0x8f; | |
1835 | buffer[0] |= 0x20; | |
1836 | buffer[1] &= 0x07; | |
1837 | ||
1838 | /* br .+6 */ | |
1839 | md_number_to_chars ((char *) buffer + 2, 0x05b5, 2); | |
1840 | ||
1841 | /* Now create the unconditional branch + fixup to the final | |
1842 | target. */ | |
1843 | /* jr SYM */ | |
1844 | md_number_to_chars ((char *) buffer + 4, 0x00000780, 4); | |
1845 | fix_new (fragP, fragP->fr_fix + 4, 4, fragP->fr_symbol, | |
1846 | fragP->fr_offset, 1, | |
1847 | BFD_RELOC_V850_22_PCREL); | |
1848 | fragP->fr_fix += 8; | |
1849 | } | |
1850 | /* Out of range SA conditional branch. Emit a branch around a 32bit jump. */ | |
1851 | else if (fragP->fr_subtype == SUBYPTE_SA_9_22_32 + 2 | |
1852 | || fragP->fr_subtype == SUBYPTE_SA_9_17_22_32 + 3) | |
1853 | { | |
1854 | unsigned char *buffer = | |
1855 | (unsigned char *) (fragP->fr_fix + fragP->fr_literal); | |
1856 | ||
1857 | /* bsa .+2 */ | |
1858 | buffer[0] &= 0x8f; | |
1859 | buffer[0] |= 0x20; | |
1860 | buffer[1] &= 0x07; | |
1861 | ||
1862 | /* br .+8 */ | |
1863 | md_number_to_chars ((char *) buffer + 2, 0x05c5, 2); | |
1864 | ||
1865 | /* Now create the unconditional branch + fixup to the final | |
1866 | target. */ | |
1867 | /* jr SYM */ | |
1868 | md_number_to_chars ((char *) buffer + 4, 0x02e0, 2); | |
1869 | fix_new (fragP, fragP->fr_fix + 6, 4, fragP->fr_symbol, | |
1870 | fragP->fr_offset + 2, 1, BFD_RELOC_V850_32_PCREL); | |
1871 | ||
1872 | fragP->fr_fix += 10; | |
1873 | } | |
252b5132 RH |
1874 | else |
1875 | abort (); | |
1876 | } | |
1877 | ||
1878 | valueT | |
ea1562b3 | 1879 | md_section_align (asection *seg, valueT addr) |
252b5132 | 1880 | { |
fd361982 | 1881 | int align = bfd_section_alignment (seg); |
8d3842cd | 1882 | return ((addr + (1 << align) - 1) & -(1 << align)); |
252b5132 RH |
1883 | } |
1884 | ||
1885 | void | |
ea1562b3 | 1886 | md_begin (void) |
252b5132 | 1887 | { |
e0471c16 | 1888 | const char *prev_name = ""; |
86aba9db | 1889 | const struct v850_opcode *op; |
28e4f854 | 1890 | |
d34049e8 | 1891 | if (startswith (TARGET_CPU, "v850e3v5")) |
78c8d46c NC |
1892 | { |
1893 | if (machine == -1) | |
1894 | machine = bfd_mach_v850e3v5; | |
1895 | ||
1896 | if (!processor_mask) | |
1897 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); | |
1898 | } | |
d34049e8 | 1899 | else if (startswith (TARGET_CPU, "v850e2v4")) |
78c8d46c NC |
1900 | { |
1901 | if (machine == -1) | |
1902 | machine = bfd_mach_v850e3v5; | |
1903 | ||
1904 | if (!processor_mask) | |
1905 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E3V5); | |
1906 | } | |
d34049e8 | 1907 | else if (startswith (TARGET_CPU, "v850e2v3")) |
1cd986c5 NC |
1908 | { |
1909 | if (machine == -1) | |
1910 | machine = bfd_mach_v850e2v3; | |
1911 | ||
1912 | if (!processor_mask) | |
1913 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2V3); | |
1914 | } | |
d34049e8 | 1915 | else if (startswith (TARGET_CPU, "v850e2")) |
1cd986c5 NC |
1916 | { |
1917 | if (machine == -1) | |
1918 | machine = bfd_mach_v850e2; | |
1919 | ||
1920 | if (!processor_mask) | |
1921 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E2); | |
1922 | } | |
d34049e8 | 1923 | else if (startswith (TARGET_CPU, "v850e1")) |
8ad30312 NC |
1924 | { |
1925 | if (machine == -1) | |
1cd986c5 | 1926 | machine = bfd_mach_v850e1; |
8ad30312 | 1927 | |
1cd986c5 NC |
1928 | if (!processor_mask) |
1929 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E1); | |
8ad30312 | 1930 | } |
d34049e8 | 1931 | else if (startswith (TARGET_CPU, "v850e")) |
252b5132 RH |
1932 | { |
1933 | if (machine == -1) | |
28e4f854 KH |
1934 | machine = bfd_mach_v850e; |
1935 | ||
1cd986c5 NC |
1936 | if (!processor_mask) |
1937 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850E); | |
252b5132 | 1938 | } |
d34049e8 | 1939 | else if (startswith (TARGET_CPU, "v850")) |
252b5132 RH |
1940 | { |
1941 | if (machine == -1) | |
28e4f854 KH |
1942 | machine = 0; |
1943 | ||
1cd986c5 NC |
1944 | if (!processor_mask) |
1945 | SET_PROCESSOR_MASK (processor_mask, PROCESSOR_V850); | |
252b5132 RH |
1946 | } |
1947 | else | |
28e4f854 KH |
1948 | /* xgettext:c-format */ |
1949 | as_bad (_("Unable to determine default target processor from string: %s"), | |
ec178e1b | 1950 | TARGET_CPU); |
252b5132 | 1951 | |
685080f2 NC |
1952 | if (soft_float == -1) |
1953 | soft_float = machine < bfd_mach_v850e2v3; | |
1954 | ||
629310ab | 1955 | v850_hash = str_htab_create (); |
252b5132 RH |
1956 | |
1957 | /* Insert unique names into hash table. The V850 instruction set | |
1958 | has many identical opcode names that have different opcodes based | |
1959 | on the operands. This hash table then provides a quick index to | |
1960 | the first opcode with a particular name in the opcode table. */ | |
252b5132 RH |
1961 | op = v850_opcodes; |
1962 | while (op->name) | |
1963 | { | |
28e4f854 | 1964 | if (strcmp (prev_name, op->name)) |
252b5132 RH |
1965 | { |
1966 | prev_name = (char *) op->name; | |
fe0e921f | 1967 | str_hash_insert (v850_hash, op->name, op, 0); |
252b5132 RH |
1968 | } |
1969 | op++; | |
1970 | } | |
1971 | ||
9e0665bc | 1972 | v850_seg_table[BSS_SECTION].s = bss_section; |
de863c74 NC |
1973 | bfd_set_arch_mach (stdoutput, v850_target_arch, machine); |
1974 | bfd_set_private_flags (stdoutput, v850_e_flags); | |
252b5132 RH |
1975 | } |
1976 | ||
1cd986c5 | 1977 | |
1e50d24d | 1978 | static bfd_reloc_code_real_type |
1cd986c5 | 1979 | handle_hi016 (const struct v850_operand *operand, const char **errmsg) |
1e50d24d | 1980 | { |
1cd986c5 NC |
1981 | if (operand == NULL) |
1982 | return BFD_RELOC_HI16; | |
1e50d24d | 1983 | |
1cd986c5 NC |
1984 | if (operand->default_reloc == BFD_RELOC_HI16) |
1985 | return BFD_RELOC_HI16; | |
1986 | ||
1987 | if (operand->default_reloc == BFD_RELOC_HI16_S) | |
1988 | return BFD_RELOC_HI16; | |
1989 | ||
1990 | if (operand->default_reloc == BFD_RELOC_16) | |
1991 | return BFD_RELOC_HI16; | |
1992 | ||
1993 | *errmsg = _("hi0() relocation used on an instruction which does " | |
1994 | "not support it"); | |
1995 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
1e50d24d RS |
1996 | } |
1997 | ||
252b5132 | 1998 | static bfd_reloc_code_real_type |
1cd986c5 | 1999 | handle_hi16 (const struct v850_operand *operand, const char **errmsg) |
252b5132 RH |
2000 | { |
2001 | if (operand == NULL) | |
1cd986c5 | 2002 | return BFD_RELOC_HI16_S; |
252b5132 | 2003 | |
1cd986c5 NC |
2004 | if (operand->default_reloc == BFD_RELOC_HI16_S) |
2005 | return BFD_RELOC_HI16_S; | |
2006 | ||
2007 | if (operand->default_reloc == BFD_RELOC_HI16) | |
2008 | return BFD_RELOC_HI16_S; | |
2009 | ||
2010 | if (operand->default_reloc == BFD_RELOC_16) | |
2011 | return BFD_RELOC_HI16_S; | |
28e4f854 | 2012 | |
1cd986c5 NC |
2013 | *errmsg = _("hi() relocation used on an instruction which does " |
2014 | "not support it"); | |
2015 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
252b5132 RH |
2016 | } |
2017 | ||
2018 | static bfd_reloc_code_real_type | |
1cd986c5 | 2019 | handle_lo16 (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 2020 | { |
28e4f854 | 2021 | if (operand == NULL) |
1cd986c5 | 2022 | return BFD_RELOC_LO16; |
718aefcf NC |
2023 | |
2024 | switch (operand->default_reloc) | |
2025 | { | |
2026 | case BFD_RELOC_LO16: return BFD_RELOC_LO16; | |
2027 | case BFD_RELOC_V850_LO16_SPLIT_OFFSET: return BFD_RELOC_V850_LO16_SPLIT_OFFSET; | |
2028 | case BFD_RELOC_V850_16_SPLIT_OFFSET: return BFD_RELOC_V850_LO16_SPLIT_OFFSET; | |
2029 | case BFD_RELOC_V850_16_S1: return BFD_RELOC_V850_LO16_S1; | |
2030 | case BFD_RELOC_16: return BFD_RELOC_LO16; | |
2031 | default: | |
2032 | *errmsg = _("lo() relocation used on an instruction which does " | |
2033 | "not support it"); | |
2034 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
2035 | } | |
252b5132 RH |
2036 | } |
2037 | ||
2038 | static bfd_reloc_code_real_type | |
1cd986c5 | 2039 | handle_ctoff (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 2040 | { |
77f730a2 NC |
2041 | if (v850_target_arch == bfd_arch_v850_rh850) |
2042 | { | |
2043 | *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead"); | |
2044 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
2045 | } | |
2046 | ||
28e4f854 | 2047 | if (operand == NULL) |
1cd986c5 | 2048 | return BFD_RELOC_V850_CALLT_16_16_OFFSET; |
28e4f854 | 2049 | |
1cd986c5 NC |
2050 | if (operand->default_reloc == BFD_RELOC_V850_CALLT_6_7_OFFSET) |
2051 | return operand->default_reloc; | |
252b5132 | 2052 | |
1cd986c5 NC |
2053 | if (operand->default_reloc == BFD_RELOC_V850_16_S1) |
2054 | return BFD_RELOC_V850_CALLT_15_16_OFFSET; | |
28e4f854 | 2055 | |
1cd986c5 NC |
2056 | if (operand->default_reloc == BFD_RELOC_16) |
2057 | return BFD_RELOC_V850_CALLT_16_16_OFFSET; | |
28e4f854 | 2058 | |
1cd986c5 NC |
2059 | *errmsg = _("ctoff() relocation used on an instruction which does not support it"); |
2060 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
252b5132 RH |
2061 | } |
2062 | ||
2063 | static bfd_reloc_code_real_type | |
1cd986c5 | 2064 | handle_sdaoff (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 2065 | { |
28e4f854 | 2066 | if (operand == NULL) |
1cd986c5 | 2067 | return BFD_RELOC_V850_SDA_16_16_OFFSET; |
28e4f854 | 2068 | |
1cd986c5 NC |
2069 | if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) |
2070 | return BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET; | |
28e4f854 | 2071 | |
1cd986c5 NC |
2072 | if (operand->default_reloc == BFD_RELOC_16) |
2073 | return BFD_RELOC_V850_SDA_16_16_OFFSET; | |
28e4f854 | 2074 | |
1cd986c5 NC |
2075 | if (operand->default_reloc == BFD_RELOC_V850_16_S1) |
2076 | return BFD_RELOC_V850_SDA_15_16_OFFSET; | |
28e4f854 | 2077 | |
1cd986c5 NC |
2078 | *errmsg = _("sdaoff() relocation used on an instruction which does not support it"); |
2079 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
252b5132 RH |
2080 | } |
2081 | ||
252b5132 | 2082 | static bfd_reloc_code_real_type |
1cd986c5 | 2083 | handle_zdaoff (const struct v850_operand *operand, const char **errmsg) |
252b5132 | 2084 | { |
1cd986c5 NC |
2085 | if (operand == NULL) |
2086 | return BFD_RELOC_V850_ZDA_16_16_OFFSET; | |
252b5132 | 2087 | |
1cd986c5 NC |
2088 | if (operand->default_reloc == BFD_RELOC_V850_16_SPLIT_OFFSET) |
2089 | return BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET; | |
252b5132 | 2090 | |
1cd986c5 NC |
2091 | if (operand->default_reloc == BFD_RELOC_16) |
2092 | return BFD_RELOC_V850_ZDA_16_16_OFFSET; | |
2093 | ||
2094 | if (operand->default_reloc == BFD_RELOC_V850_16_S1) | |
2095 | return BFD_RELOC_V850_ZDA_15_16_OFFSET; | |
2096 | ||
2097 | *errmsg = _("zdaoff() relocation used on an instruction which does not support it"); | |
2098 | return BFD_RELOC_64; /* Used to indicate an error condition. */ | |
2099 | } | |
2100 | ||
2101 | static bfd_reloc_code_real_type | |
2102 | handle_tdaoff (const struct v850_operand *operand, const char **errmsg) | |
2103 | { | |
2104 | if (operand == NULL) | |
2105 | /* Data item, not an instruction. */ | |
2106 | return BFD_RELOC_V850_TDA_16_16_OFFSET; | |
2107 | ||
2108 | switch (operand->default_reloc) | |
2109 | { | |
2110 | /* sld.hu, operand: D5-4. */ | |
2111 | case BFD_RELOC_V850_TDA_4_5_OFFSET: | |
2112 | /* sld.bu, operand: D4. */ | |
2113 | case BFD_RELOC_V850_TDA_4_4_OFFSET: | |
2114 | /* sld.w/sst.w, operand: D8_6. */ | |
2115 | case BFD_RELOC_V850_TDA_6_8_OFFSET: | |
2116 | /* sld.h/sst.h, operand: D8_7. */ | |
2117 | case BFD_RELOC_V850_TDA_7_8_OFFSET: | |
2118 | /* sld.b/sst.b, operand: D7. */ | |
2119 | case BFD_RELOC_V850_TDA_7_7_OFFSET: | |
2120 | return operand->default_reloc; | |
2121 | default: | |
2122 | break; | |
2123 | } | |
2124 | ||
2125 | if (operand->default_reloc == BFD_RELOC_16 && operand->shift == 16) | |
2126 | /* set1 & chums, operands: D16. */ | |
2127 | return BFD_RELOC_V850_TDA_16_16_OFFSET; | |
2128 | ||
2129 | *errmsg = _("tdaoff() relocation used on an instruction which does not support it"); | |
2130 | /* Used to indicate an error condition. */ | |
2131 | return BFD_RELOC_64; | |
2132 | } | |
2133 | ||
2134 | /* Warning: The code in this function relies upon the definitions | |
2135 | in the v850_operands[] array (defined in opcodes/v850-opc.c) | |
2136 | matching the hard coded values contained herein. */ | |
2137 | ||
2138 | static bfd_reloc_code_real_type | |
2139 | v850_reloc_prefix (const struct v850_operand *operand, const char **errmsg) | |
2140 | { | |
5b7c81bd | 2141 | bool paren_skipped = false; |
1cd986c5 NC |
2142 | |
2143 | /* Skip leading opening parenthesis. */ | |
2144 | if (*input_line_pointer == '(') | |
2145 | { | |
2146 | ++input_line_pointer; | |
5b7c81bd | 2147 | paren_skipped = true; |
1cd986c5 NC |
2148 | } |
2149 | ||
2150 | #define CHECK_(name, reloc) \ | |
ec266e19 | 2151 | if (strncmp (input_line_pointer, name "(", strlen (name) + 1) == 0) \ |
252b5132 RH |
2152 | { \ |
2153 | input_line_pointer += strlen (name); \ | |
2154 | return reloc; \ | |
2155 | } | |
28e4f854 | 2156 | |
718aefcf NC |
2157 | CHECK_ ("hi0", handle_hi016 (operand, errmsg)); |
2158 | CHECK_ ("hi", handle_hi16 (operand, errmsg)); | |
2159 | CHECK_ ("lo", handle_lo16 (operand, errmsg)); | |
1cd986c5 NC |
2160 | CHECK_ ("sdaoff", handle_sdaoff (operand, errmsg)); |
2161 | CHECK_ ("zdaoff", handle_zdaoff (operand, errmsg)); | |
2162 | CHECK_ ("tdaoff", handle_tdaoff (operand, errmsg)); | |
2163 | CHECK_ ("hilo", BFD_RELOC_32); | |
2164 | CHECK_ ("lo23", BFD_RELOC_V850_23); | |
718aefcf | 2165 | CHECK_ ("ctoff", handle_ctoff (operand, errmsg)); |
28e4f854 | 2166 | |
252b5132 RH |
2167 | /* Restore skipped parenthesis. */ |
2168 | if (paren_skipped) | |
28e4f854 KH |
2169 | --input_line_pointer; |
2170 | ||
62ebcb5c | 2171 | return BFD_RELOC_NONE; |
252b5132 RH |
2172 | } |
2173 | ||
2174 | /* Insert an operand value into an instruction. */ | |
2175 | ||
2176 | static unsigned long | |
ea1562b3 NC |
2177 | v850_insert_operand (unsigned long insn, |
2178 | const struct v850_operand *operand, | |
2179 | offsetT val, | |
1cd986c5 | 2180 | const char **errmsg) |
252b5132 RH |
2181 | { |
2182 | if (operand->insert) | |
2183 | { | |
28e4f854 KH |
2184 | const char *message = NULL; |
2185 | ||
2186 | insn = operand->insert (insn, val, &message); | |
252b5132 RH |
2187 | if (message != NULL) |
2188 | { | |
2189 | if ((operand->flags & V850_OPERAND_SIGNED) | |
2190 | && ! warn_signed_overflows | |
1cd986c5 | 2191 | && v850_msg_is_out_of_range (message)) |
252b5132 | 2192 | { |
28e4f854 | 2193 | /* Skip warning... */ |
252b5132 RH |
2194 | } |
2195 | else if ((operand->flags & V850_OPERAND_SIGNED) == 0 | |
2196 | && ! warn_unsigned_overflows | |
1cd986c5 | 2197 | && v850_msg_is_out_of_range (message)) |
252b5132 | 2198 | { |
28e4f854 | 2199 | /* Skip warning... */ |
252b5132 | 2200 | } |
252b5132 RH |
2201 | else |
2202 | { | |
1cd986c5 NC |
2203 | if (errmsg != NULL) |
2204 | *errmsg = message; | |
252b5132 RH |
2205 | } |
2206 | } | |
2207 | } | |
1cd986c5 NC |
2208 | else if (operand->bits == -1 |
2209 | || operand->flags & V850E_IMMEDIATE16 | |
2210 | || operand->flags & V850E_IMMEDIATE23 | |
2211 | || operand->flags & V850E_IMMEDIATE32) | |
2212 | { | |
2213 | abort (); | |
2214 | } | |
252b5132 RH |
2215 | else |
2216 | { | |
1cd986c5 | 2217 | if (operand->bits < 32) |
252b5132 | 2218 | { |
28e4f854 | 2219 | long min, max; |
252b5132 RH |
2220 | |
2221 | if ((operand->flags & V850_OPERAND_SIGNED) != 0) | |
2222 | { | |
2223 | if (! warn_signed_overflows) | |
2224 | max = (1 << operand->bits) - 1; | |
2225 | else | |
2226 | max = (1 << (operand->bits - 1)) - 1; | |
28e4f854 KH |
2227 | |
2228 | min = -(1 << (operand->bits - 1)); | |
252b5132 RH |
2229 | } |
2230 | else | |
2231 | { | |
2232 | max = (1 << operand->bits) - 1; | |
28e4f854 | 2233 | |
252b5132 | 2234 | if (! warn_unsigned_overflows) |
28e4f854 | 2235 | min = -(1 << (operand->bits - 1)); |
252b5132 RH |
2236 | else |
2237 | min = 0; | |
2238 | } | |
28e4f854 | 2239 | |
dc86b458 SB |
2240 | /* Some people write constants with the sign extension done by |
2241 | hand but only up to 32 bits. This shouldn't really be valid, | |
2242 | but, to permit this code to assemble on a 64-bit host, we | |
2243 | sign extend the 32-bit value to 64 bits if so doing makes the | |
2244 | value valid. */ | |
2245 | if (val > max | |
2246 | && (offsetT) (val - 0x80000000 - 0x80000000) >= min | |
2247 | && (offsetT) (val - 0x80000000 - 0x80000000) <= max) | |
2248 | val = val - 0x80000000 - 0x80000000; | |
2249 | ||
2250 | /* Similarly, people write expressions like ~(1<<15), and expect | |
2251 | this to be OK for a 32-bit unsigned value. */ | |
2252 | else if (val < min | |
2253 | && (offsetT) (val + 0x80000000 + 0x80000000) >= min | |
2254 | && (offsetT) (val + 0x80000000 + 0x80000000) <= max) | |
2255 | val = val + 0x80000000 + 0x80000000; | |
2256 | ||
2257 | else if (val < (offsetT) min || val > (offsetT) max) | |
252b5132 | 2258 | { |
04ee5257 | 2259 | static char buf [128]; |
28e4f854 | 2260 | |
252b5132 RH |
2261 | /* Restore min and mix to expected values for decimal ranges. */ |
2262 | if ((operand->flags & V850_OPERAND_SIGNED) | |
2263 | && ! warn_signed_overflows) | |
2264 | max = (1 << (operand->bits - 1)) - 1; | |
2265 | ||
2266 | if (! (operand->flags & V850_OPERAND_SIGNED) | |
2267 | && ! warn_unsigned_overflows) | |
2268 | min = 0; | |
2269 | ||
1cd986c5 NC |
2270 | sprintf (buf, _("operand out of range (%d is not between %d and %d)"), |
2271 | (int) val, (int) min, (int) max); | |
2272 | *errmsg = buf; | |
252b5132 | 2273 | } |
252b5132 | 2274 | |
1cd986c5 NC |
2275 | insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift); |
2276 | } | |
2277 | else | |
2278 | { | |
2279 | insn |= (((long) val) << operand->shift); | |
2280 | } | |
252b5132 | 2281 | } |
28e4f854 | 2282 | |
252b5132 RH |
2283 | return insn; |
2284 | } | |
252b5132 | 2285 | \f |
28e4f854 | 2286 | static char copy_of_instruction[128]; |
252b5132 RH |
2287 | |
2288 | void | |
ea1562b3 | 2289 | md_assemble (char *str) |
252b5132 | 2290 | { |
28e4f854 KH |
2291 | char *s; |
2292 | char *start_of_operands; | |
2293 | struct v850_opcode *opcode; | |
2294 | struct v850_opcode *next_opcode; | |
2295 | const unsigned char *opindex_ptr; | |
2296 | int next_opindex; | |
2297 | int relaxable = 0; | |
0bae9e9e | 2298 | unsigned long insn = 0; |
28e4f854 | 2299 | unsigned long insn_size; |
de863c74 | 2300 | char *f = NULL; |
28e4f854 KH |
2301 | int i; |
2302 | int match; | |
5b7c81bd | 2303 | bool extra_data_after_insn = false; |
28e4f854 KH |
2304 | unsigned extra_data_len = 0; |
2305 | unsigned long extra_data = 0; | |
2306 | char *saved_input_line_pointer; | |
1cd986c5 NC |
2307 | char most_match_errmsg[1024]; |
2308 | int most_match_count = -1; | |
28e4f854 | 2309 | |
252b5132 | 2310 | strncpy (copy_of_instruction, str, sizeof (copy_of_instruction) - 1); |
1cd986c5 | 2311 | most_match_errmsg[0] = 0; |
28e4f854 | 2312 | |
252b5132 | 2313 | /* Get the opcode. */ |
3882b010 | 2314 | for (s = str; *s != '\0' && ! ISSPACE (*s); s++) |
252b5132 | 2315 | continue; |
28e4f854 | 2316 | |
252b5132 RH |
2317 | if (*s != '\0') |
2318 | *s++ = '\0'; | |
2319 | ||
28e4f854 | 2320 | /* Find the first opcode with the proper name. */ |
629310ab | 2321 | opcode = (struct v850_opcode *) str_hash_find (v850_hash, str); |
252b5132 RH |
2322 | if (opcode == NULL) |
2323 | { | |
28e4f854 | 2324 | /* xgettext:c-format */ |
252b5132 RH |
2325 | as_bad (_("Unrecognized opcode: `%s'"), str); |
2326 | ignore_rest_of_line (); | |
2327 | return; | |
2328 | } | |
2329 | ||
2330 | str = s; | |
3882b010 | 2331 | while (ISSPACE (*str)) |
28e4f854 | 2332 | ++str; |
252b5132 RH |
2333 | |
2334 | start_of_operands = str; | |
2335 | ||
2336 | saved_input_line_pointer = input_line_pointer; | |
28e4f854 | 2337 | |
252b5132 RH |
2338 | for (;;) |
2339 | { | |
28e4f854 | 2340 | const char *errmsg = NULL; |
1cd986c5 | 2341 | const char *warningmsg = NULL; |
252b5132 RH |
2342 | |
2343 | match = 0; | |
1cd986c5 | 2344 | opindex_ptr = opcode->operands; |
28e4f854 | 2345 | |
1cd986c5 NC |
2346 | if (no_stld23) |
2347 | { | |
d34049e8 | 2348 | if ((startswith (opcode->name, "st.") |
1cd986c5 | 2349 | && v850_operands[opcode->operands[1]].bits == 23) |
d34049e8 | 2350 | || (startswith (opcode->name, "ld.") |
1cd986c5 NC |
2351 | && v850_operands[opcode->operands[0]].bits == 23)) |
2352 | { | |
2353 | errmsg = _("st/ld offset 23 instruction was disabled ."); | |
2354 | goto error; | |
2355 | } | |
2356 | } | |
2357 | ||
2358 | if ((opcode->processors & processor_mask & PROCESSOR_MASK) == 0 | |
2359 | || (((opcode->processors & ~PROCESSOR_MASK) != 0) | |
2360 | && ((opcode->processors & processor_mask & ~PROCESSOR_MASK) == 0))) | |
252b5132 RH |
2361 | { |
2362 | errmsg = _("Target processor does not support this instruction."); | |
2363 | goto error; | |
2364 | } | |
28e4f854 | 2365 | |
252b5132 RH |
2366 | relaxable = 0; |
2367 | fc = 0; | |
2368 | next_opindex = 0; | |
2369 | insn = opcode->opcode; | |
1cd986c5 | 2370 | extra_data_len = 0; |
5b7c81bd | 2371 | extra_data_after_insn = false; |
252b5132 RH |
2372 | |
2373 | input_line_pointer = str = start_of_operands; | |
2374 | ||
28e4f854 | 2375 | for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++) |
252b5132 | 2376 | { |
28e4f854 KH |
2377 | const struct v850_operand *operand; |
2378 | char *hold; | |
2379 | expressionS ex; | |
2380 | bfd_reloc_code_real_type reloc; | |
252b5132 RH |
2381 | |
2382 | if (next_opindex == 0) | |
ea1562b3 | 2383 | operand = &v850_operands[*opindex_ptr]; |
252b5132 RH |
2384 | else |
2385 | { | |
28e4f854 | 2386 | operand = &v850_operands[next_opindex]; |
252b5132 RH |
2387 | next_opindex = 0; |
2388 | } | |
2389 | ||
2390 | errmsg = NULL; | |
2391 | ||
1cd986c5 NC |
2392 | while (*str == ' ') |
2393 | ++str; | |
2394 | ||
2395 | if (operand->flags & V850_OPERAND_BANG | |
2396 | && *str == '!') | |
2397 | ++str; | |
2398 | else if (operand->flags & V850_OPERAND_PERCENT | |
2399 | && *str == '%') | |
2400 | ++str; | |
2401 | ||
2402 | if (*str == ',' || *str == '[' || *str == ']') | |
2403 | ++str; | |
2404 | ||
2405 | while (*str == ' ') | |
28e4f854 | 2406 | ++str; |
252b5132 | 2407 | |
78c8d46c NC |
2408 | if ( (strcmp (opcode->name, "pushsp") == 0 |
2409 | || strcmp (opcode->name, "popsp") == 0 | |
2410 | || strcmp (opcode->name, "dbpush") == 0) | |
2411 | && (*str == '-')) | |
2412 | ++str; | |
2413 | ||
252b5132 RH |
2414 | if (operand->flags & V850_OPERAND_RELAX) |
2415 | relaxable = 1; | |
2416 | ||
28e4f854 | 2417 | /* Gather the operand. */ |
252b5132 RH |
2418 | hold = input_line_pointer; |
2419 | input_line_pointer = str; | |
28e4f854 KH |
2420 | |
2421 | /* lo(), hi(), hi0(), etc... */ | |
62ebcb5c | 2422 | if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE) |
252b5132 RH |
2423 | { |
2424 | /* This is a fake reloc, used to indicate an error condition. */ | |
2425 | if (reloc == BFD_RELOC_64) | |
2426 | { | |
1cd986c5 | 2427 | /* match = 1; */ |
252b5132 RH |
2428 | goto error; |
2429 | } | |
28e4f854 KH |
2430 | |
2431 | expression (&ex); | |
252b5132 RH |
2432 | |
2433 | if (ex.X_op == O_constant) | |
2434 | { | |
2435 | switch (reloc) | |
2436 | { | |
2437 | case BFD_RELOC_V850_ZDA_16_16_OFFSET: | |
1cd986c5 NC |
2438 | case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: |
2439 | case BFD_RELOC_V850_ZDA_15_16_OFFSET: | |
252b5132 RH |
2440 | /* To cope with "not1 7, zdaoff(0xfffff006)[r0]" |
2441 | and the like. */ | |
2442 | /* Fall through. */ | |
28e4f854 | 2443 | |
252b5132 | 2444 | case BFD_RELOC_LO16: |
1cd986c5 | 2445 | case BFD_RELOC_V850_LO16_S1: |
1e50d24d | 2446 | case BFD_RELOC_V850_LO16_SPLIT_OFFSET: |
252b5132 RH |
2447 | { |
2448 | /* Truncate, then sign extend the value. */ | |
2449 | ex.X_add_number = SEXT16 (ex.X_add_number); | |
2450 | break; | |
2451 | } | |
2452 | ||
2453 | case BFD_RELOC_HI16: | |
2454 | { | |
2455 | /* Truncate, then sign extend the value. */ | |
2456 | ex.X_add_number = SEXT16 (ex.X_add_number >> 16); | |
2457 | break; | |
2458 | } | |
2459 | ||
2460 | case BFD_RELOC_HI16_S: | |
2461 | { | |
2462 | /* Truncate, then sign extend the value. */ | |
28e4f854 | 2463 | int temp = (ex.X_add_number >> 16) & 0xffff; |
252b5132 RH |
2464 | |
2465 | temp += (ex.X_add_number >> 15) & 1; | |
2466 | ||
2467 | ex.X_add_number = SEXT16 (temp); | |
2468 | break; | |
2469 | } | |
28e4f854 | 2470 | |
1cd986c5 NC |
2471 | case BFD_RELOC_V850_23: |
2472 | if ((operand->flags & V850E_IMMEDIATE23) == 0) | |
2473 | { | |
2474 | errmsg = _("immediate operand is too large"); | |
2475 | goto error; | |
2476 | } | |
2477 | break; | |
2478 | ||
252b5132 | 2479 | case BFD_RELOC_32: |
1cd986c5 NC |
2480 | case BFD_RELOC_V850_32_ABS: |
2481 | case BFD_RELOC_V850_32_PCREL: | |
252b5132 RH |
2482 | if ((operand->flags & V850E_IMMEDIATE32) == 0) |
2483 | { | |
2484 | errmsg = _("immediate operand is too large"); | |
2485 | goto error; | |
2486 | } | |
28e4f854 | 2487 | |
252b5132 | 2488 | break; |
28e4f854 | 2489 | |
252b5132 | 2490 | default: |
78c8d46c | 2491 | as_bad (_("AAARG -> unhandled constant reloc: %d"), reloc); |
252b5132 RH |
2492 | break; |
2493 | } | |
2494 | ||
1cd986c5 NC |
2495 | if (operand->flags & V850E_IMMEDIATE32) |
2496 | { | |
5b7c81bd | 2497 | extra_data_after_insn = true; |
1cd986c5 NC |
2498 | extra_data_len = 4; |
2499 | extra_data = 0; | |
2500 | } | |
2501 | else if (operand->flags & V850E_IMMEDIATE23) | |
2502 | { | |
2503 | if (reloc != BFD_RELOC_V850_23) | |
2504 | { | |
2505 | errmsg = _("immediate operand is too large"); | |
2506 | goto error; | |
2507 | } | |
5b7c81bd | 2508 | extra_data_after_insn = true; |
1cd986c5 NC |
2509 | extra_data_len = 2; |
2510 | extra_data = 0; | |
2511 | } | |
2512 | else if ((operand->flags & V850E_IMMEDIATE16) | |
2513 | || (operand->flags & V850E_IMMEDIATE16HI)) | |
2514 | { | |
2515 | if (operand->flags & V850E_IMMEDIATE16HI | |
2516 | && reloc != BFD_RELOC_HI16 | |
2517 | && reloc != BFD_RELOC_HI16_S) | |
2518 | { | |
2519 | errmsg = _("immediate operand is too large"); | |
2520 | goto error; | |
2521 | } | |
2522 | else if (operand->flags & V850E_IMMEDIATE16 | |
2523 | && reloc != BFD_RELOC_LO16) | |
2524 | { | |
2525 | errmsg = _("immediate operand is too large"); | |
2526 | goto error; | |
2527 | } | |
2528 | ||
5b7c81bd | 2529 | extra_data_after_insn = true; |
1cd986c5 NC |
2530 | extra_data_len = 2; |
2531 | extra_data = 0; | |
2532 | } | |
2533 | ||
252b5132 RH |
2534 | if (fc > MAX_INSN_FIXUPS) |
2535 | as_fatal (_("too many fixups")); | |
28e4f854 KH |
2536 | |
2537 | fixups[fc].exp = ex; | |
2538 | fixups[fc].opindex = *opindex_ptr; | |
2539 | fixups[fc].reloc = reloc; | |
252b5132 RH |
2540 | fc++; |
2541 | } | |
1cd986c5 | 2542 | else /* ex.X_op != O_constant. */ |
252b5132 | 2543 | { |
1cd986c5 NC |
2544 | if ((reloc == BFD_RELOC_32 |
2545 | || reloc == BFD_RELOC_V850_32_ABS | |
2546 | || reloc == BFD_RELOC_V850_32_PCREL) | |
2547 | && operand->bits < 32) | |
252b5132 | 2548 | { |
1cd986c5 NC |
2549 | errmsg = _("immediate operand is too large"); |
2550 | goto error; | |
2551 | } | |
2552 | else if (reloc == BFD_RELOC_V850_23 | |
2553 | && (operand->flags & V850E_IMMEDIATE23) == 0) | |
2554 | { | |
2555 | errmsg = _("immediate operand is too large"); | |
2556 | goto error; | |
2557 | } | |
2558 | else if ((reloc == BFD_RELOC_HI16 | |
2559 | || reloc == BFD_RELOC_HI16_S) | |
2560 | && operand->bits < 16) | |
2561 | { | |
2562 | errmsg = _("immediate operand is too large"); | |
2563 | goto error; | |
2564 | } | |
2565 | ||
2566 | if (operand->flags & V850E_IMMEDIATE32) | |
2567 | { | |
5b7c81bd | 2568 | extra_data_after_insn = true; |
1cd986c5 NC |
2569 | extra_data_len = 4; |
2570 | extra_data = 0; | |
2571 | } | |
2572 | else if (operand->flags & V850E_IMMEDIATE23) | |
2573 | { | |
2574 | if (reloc != BFD_RELOC_V850_23) | |
2575 | { | |
2576 | errmsg = _("immediate operand is too large"); | |
2577 | goto error; | |
2578 | } | |
5b7c81bd | 2579 | extra_data_after_insn = true; |
1cd986c5 NC |
2580 | extra_data_len = 2; |
2581 | extra_data = 0; | |
2582 | } | |
2583 | else if ((operand->flags & V850E_IMMEDIATE16) | |
2584 | || (operand->flags & V850E_IMMEDIATE16HI)) | |
2585 | { | |
2586 | if (operand->flags & V850E_IMMEDIATE16HI | |
2587 | && reloc != BFD_RELOC_HI16 | |
2588 | && reloc != BFD_RELOC_HI16_S) | |
2589 | { | |
2590 | errmsg = _("immediate operand is too large"); | |
2591 | goto error; | |
2592 | } | |
2593 | else if (operand->flags & V850E_IMMEDIATE16 | |
2594 | && reloc != BFD_RELOC_LO16) | |
252b5132 RH |
2595 | { |
2596 | errmsg = _("immediate operand is too large"); | |
2597 | goto error; | |
2598 | } | |
28e4f854 | 2599 | |
5b7c81bd | 2600 | extra_data_after_insn = true; |
1cd986c5 NC |
2601 | extra_data_len = 2; |
2602 | extra_data = 0; | |
252b5132 | 2603 | } |
28e4f854 | 2604 | |
252b5132 RH |
2605 | if (fc > MAX_INSN_FIXUPS) |
2606 | as_fatal (_("too many fixups")); | |
2607 | ||
28e4f854 KH |
2608 | fixups[fc].exp = ex; |
2609 | fixups[fc].opindex = *opindex_ptr; | |
2610 | fixups[fc].reloc = reloc; | |
252b5132 RH |
2611 | fc++; |
2612 | } | |
2613 | } | |
1cd986c5 NC |
2614 | else if (operand->flags & V850E_IMMEDIATE16 |
2615 | || operand->flags & V850E_IMMEDIATE16HI) | |
2616 | { | |
2617 | expression (&ex); | |
2618 | ||
2619 | switch (ex.X_op) | |
2620 | { | |
2621 | case O_constant: | |
2622 | if (operand->flags & V850E_IMMEDIATE16HI) | |
2623 | { | |
2624 | if (ex.X_add_number & 0xffff) | |
2625 | { | |
2626 | errmsg = _("constant too big to fit into instruction"); | |
2627 | goto error; | |
2628 | } | |
2629 | ||
2630 | ex.X_add_number >>= 16; | |
2631 | } | |
2632 | if (operand->flags & V850E_IMMEDIATE16) | |
2633 | { | |
78c8d46c NC |
2634 | if ((ex.X_add_number & 0xffff8000) |
2635 | && ((ex.X_add_number & 0xffff8000) != 0xffff8000)) | |
1cd986c5 NC |
2636 | { |
2637 | errmsg = _("constant too big to fit into instruction"); | |
2638 | goto error; | |
2639 | } | |
2640 | } | |
2641 | break; | |
2642 | ||
2643 | case O_illegal: | |
2644 | errmsg = _("illegal operand"); | |
2645 | goto error; | |
2646 | ||
2647 | case O_absent: | |
2648 | errmsg = _("missing operand"); | |
2649 | goto error; | |
2650 | ||
2651 | default: | |
2652 | if (fc >= MAX_INSN_FIXUPS) | |
2653 | as_fatal (_("too many fixups")); | |
2654 | ||
2655 | fixups[fc].exp = ex; | |
2656 | fixups[fc].opindex = *opindex_ptr; | |
2657 | fixups[fc].reloc = operand->default_reloc; | |
2658 | ++fc; | |
2659 | ||
2660 | ex.X_add_number = 0; | |
2661 | break; | |
2662 | } | |
2663 | ||
5b7c81bd | 2664 | extra_data_after_insn = true; |
1cd986c5 NC |
2665 | extra_data_len = 2; |
2666 | extra_data = ex.X_add_number; | |
2667 | } | |
2668 | else if (operand->flags & V850E_IMMEDIATE23) | |
2669 | { | |
2670 | expression (&ex); | |
2671 | ||
2672 | switch (ex.X_op) | |
2673 | { | |
2674 | case O_constant: | |
2675 | break; | |
2676 | ||
2677 | case O_illegal: | |
2678 | errmsg = _("illegal operand"); | |
2679 | goto error; | |
2680 | ||
2681 | case O_absent: | |
2682 | errmsg = _("missing operand"); | |
2683 | goto error; | |
2684 | ||
2685 | default: | |
2686 | break; | |
2687 | } | |
2688 | ||
2689 | if (fc >= MAX_INSN_FIXUPS) | |
2690 | as_fatal (_("too many fixups")); | |
2691 | ||
2692 | fixups[fc].exp = ex; | |
2693 | fixups[fc].opindex = *opindex_ptr; | |
2694 | fixups[fc].reloc = operand->default_reloc; | |
2695 | ++fc; | |
2696 | ||
5b7c81bd | 2697 | extra_data_after_insn = true; |
1cd986c5 NC |
2698 | extra_data_len = 2; |
2699 | extra_data = 0; | |
2700 | } | |
2701 | else if (operand->flags & V850E_IMMEDIATE32) | |
2702 | { | |
2703 | expression (&ex); | |
2704 | ||
2705 | switch (ex.X_op) | |
2706 | { | |
2707 | case O_constant: | |
2708 | if ((operand->default_reloc == BFD_RELOC_V850_32_ABS | |
2709 | || operand->default_reloc == BFD_RELOC_V850_32_PCREL) | |
2710 | && (ex.X_add_number & 1)) | |
2711 | { | |
2712 | errmsg = _("odd number cannot be used here"); | |
2713 | goto error; | |
2714 | } | |
2715 | break; | |
2716 | ||
2717 | case O_illegal: | |
2718 | errmsg = _("illegal operand"); | |
2719 | goto error; | |
2720 | ||
2721 | case O_absent: | |
2722 | errmsg = _("missing operand"); | |
2723 | goto error; | |
2724 | ||
2725 | default: | |
2726 | if (fc >= MAX_INSN_FIXUPS) | |
2727 | as_fatal (_("too many fixups")); | |
2728 | ||
2729 | fixups[fc].exp = ex; | |
2730 | fixups[fc].opindex = *opindex_ptr; | |
2731 | fixups[fc].reloc = operand->default_reloc; | |
2732 | ++fc; | |
2733 | ||
2734 | ex.X_add_number = 0; | |
2735 | break; | |
2736 | } | |
2737 | ||
5b7c81bd | 2738 | extra_data_after_insn = true; |
1cd986c5 NC |
2739 | extra_data_len = 4; |
2740 | extra_data = ex.X_add_number; | |
2741 | } | |
2742 | else if (operand->flags & V850E_OPERAND_REG_LIST) | |
2743 | { | |
2744 | errmsg = parse_register_list (&insn, operand); | |
2745 | ||
2746 | if (errmsg) | |
2747 | goto error; | |
2748 | } | |
252b5132 RH |
2749 | else |
2750 | { | |
2751 | errmsg = NULL; | |
28e4f854 KH |
2752 | |
2753 | if ((operand->flags & V850_OPERAND_REG) != 0) | |
252b5132 | 2754 | { |
28e4f854 | 2755 | if (!register_name (&ex)) |
1cd986c5 NC |
2756 | { |
2757 | errmsg = _("invalid register name"); | |
2758 | } | |
2759 | ||
2760 | if ((operand->flags & V850_NOT_R0) | |
28e4f854 | 2761 | && ex.X_add_number == 0) |
252b5132 RH |
2762 | { |
2763 | errmsg = _("register r0 cannot be used here"); | |
1cd986c5 | 2764 | } |
28e4f854 | 2765 | |
1cd986c5 NC |
2766 | if (operand->flags & V850_REG_EVEN) |
2767 | { | |
2768 | if (ex.X_add_number % 2) | |
2769 | errmsg = _("odd register cannot be used here"); | |
2770 | ex.X_add_number = ex.X_add_number / 2; | |
252b5132 | 2771 | } |
1cd986c5 | 2772 | |
252b5132 | 2773 | } |
28e4f854 | 2774 | else if ((operand->flags & V850_OPERAND_SRG) != 0) |
252b5132 | 2775 | { |
5b7c81bd | 2776 | if (!system_register_name (&ex, true)) |
1cd986c5 NC |
2777 | { |
2778 | errmsg = _("invalid system register name"); | |
2779 | } | |
252b5132 RH |
2780 | } |
2781 | else if ((operand->flags & V850_OPERAND_EP) != 0) | |
2782 | { | |
28e4f854 | 2783 | char *start = input_line_pointer; |
d02603dc NC |
2784 | char *name; |
2785 | char c = get_symbol_name (&name); | |
28e4f854 | 2786 | |
d02603dc | 2787 | if (strcmp (name, "ep") != 0 && strcmp (name, "r30") != 0) |
252b5132 RH |
2788 | { |
2789 | /* Put things back the way we found them. */ | |
d02603dc | 2790 | (void) restore_line_pointer (c); |
252b5132 RH |
2791 | input_line_pointer = start; |
2792 | errmsg = _("expected EP register"); | |
2793 | goto error; | |
2794 | } | |
28e4f854 | 2795 | |
d02603dc | 2796 | (void) restore_line_pointer (c); |
252b5132 RH |
2797 | str = input_line_pointer; |
2798 | input_line_pointer = hold; | |
28e4f854 KH |
2799 | |
2800 | while (*str == ' ' || *str == ',' | |
2801 | || *str == '[' || *str == ']') | |
2802 | ++str; | |
252b5132 RH |
2803 | continue; |
2804 | } | |
28e4f854 | 2805 | else if ((operand->flags & V850_OPERAND_CC) != 0) |
252b5132 | 2806 | { |
5b7c81bd | 2807 | if (!cc_name (&ex, true)) |
252b5132 | 2808 | { |
1cd986c5 | 2809 | errmsg = _("invalid condition code name"); |
252b5132 | 2810 | } |
28e4f854 | 2811 | |
1cd986c5 NC |
2812 | if ((operand->flags & V850_NOT_SA) |
2813 | && ex.X_add_number == COND_SA_NUM) | |
2814 | { | |
2815 | errmsg = _("condition sa cannot be used here"); | |
2816 | } | |
252b5132 | 2817 | } |
1cd986c5 | 2818 | else if ((operand->flags & V850_OPERAND_FLOAT_CC) != 0) |
252b5132 | 2819 | { |
5b7c81bd | 2820 | if (!float_cc_name (&ex, true)) |
1cd986c5 NC |
2821 | { |
2822 | errmsg = _("invalid condition code name"); | |
2823 | } | |
252b5132 | 2824 | } |
78c8d46c NC |
2825 | else if ((operand->flags & V850_OPERAND_CACHEOP) != 0) |
2826 | { | |
5b7c81bd | 2827 | if (!cacheop_name (&ex, true)) |
33eaf5de | 2828 | errmsg = _("invalid cache operation name"); |
78c8d46c NC |
2829 | } |
2830 | else if ((operand->flags & V850_OPERAND_PREFOP) != 0) | |
2831 | { | |
5b7c81bd | 2832 | if (!prefop_name (&ex, true)) |
33eaf5de | 2833 | errmsg = _("invalid pref operation name"); |
78c8d46c NC |
2834 | } |
2835 | else if ((operand->flags & V850_OPERAND_VREG) != 0) | |
2836 | { | |
2837 | if (!vector_register_name (&ex)) | |
2838 | errmsg = _("invalid vector register name"); | |
2839 | } | |
1cd986c5 NC |
2840 | else if ((register_name (&ex) |
2841 | && (operand->flags & V850_OPERAND_REG) == 0)) | |
252b5132 | 2842 | { |
d02603dc | 2843 | char *name; |
252b5132 | 2844 | char c; |
28e4f854 KH |
2845 | int exists = 0; |
2846 | ||
252b5132 RH |
2847 | /* It is possible that an alias has been defined that |
2848 | matches a register name. For example the code may | |
2849 | include a ".set ZERO, 0" directive, which matches | |
2850 | the register name "zero". Attempt to reparse the | |
2851 | field as an expression, and only complain if we | |
2852 | cannot generate a constant. */ | |
2853 | ||
2854 | input_line_pointer = str; | |
2855 | ||
d02603dc | 2856 | c = get_symbol_name (&name); |
28e4f854 | 2857 | |
d02603dc | 2858 | if (symbol_find (name) != NULL) |
252b5132 | 2859 | exists = 1; |
28e4f854 | 2860 | |
d02603dc | 2861 | (void) restore_line_pointer (c); |
252b5132 | 2862 | input_line_pointer = str; |
28e4f854 KH |
2863 | |
2864 | expression (&ex); | |
252b5132 RH |
2865 | |
2866 | if (ex.X_op != O_constant) | |
2867 | { | |
33b7f697 | 2868 | /* If this register is actually occurring too early on |
252b5132 RH |
2869 | the parsing of the instruction, (because another |
2870 | field is missing) then report this. */ | |
2871 | if (opindex_ptr[1] != 0 | |
1cd986c5 NC |
2872 | && ((v850_operands[opindex_ptr[1]].flags |
2873 | & V850_OPERAND_REG) | |
2874 | ||(v850_operands[opindex_ptr[1]].flags | |
2875 | & V850_OPERAND_VREG))) | |
252b5132 RH |
2876 | errmsg = _("syntax error: value is missing before the register name"); |
2877 | else | |
2878 | errmsg = _("syntax error: register not expected"); | |
2879 | ||
28e4f854 KH |
2880 | /* If we created a symbol in the process of this |
2881 | test then delete it now, so that it will not | |
2882 | be output with the real symbols... */ | |
252b5132 RH |
2883 | if (exists == 0 |
2884 | && ex.X_op == O_symbol) | |
2885 | symbol_remove (ex.X_add_symbol, | |
28e4f854 | 2886 | &symbol_rootP, &symbol_lastP); |
252b5132 RH |
2887 | } |
2888 | } | |
5b7c81bd | 2889 | else if (system_register_name (&ex, false) |
252b5132 | 2890 | && (operand->flags & V850_OPERAND_SRG) == 0) |
1cd986c5 NC |
2891 | { |
2892 | errmsg = _("syntax error: system register not expected"); | |
2893 | } | |
5b7c81bd | 2894 | else if (cc_name (&ex, false) |
252b5132 | 2895 | && (operand->flags & V850_OPERAND_CC) == 0) |
1cd986c5 NC |
2896 | { |
2897 | errmsg = _("syntax error: condition code not expected"); | |
2898 | } | |
5b7c81bd | 2899 | else if (float_cc_name (&ex, false) |
1cd986c5 NC |
2900 | && (operand->flags & V850_OPERAND_FLOAT_CC) == 0) |
2901 | { | |
2902 | errmsg = _("syntax error: condition code not expected"); | |
2903 | } | |
78c8d46c NC |
2904 | else if (vector_register_name (&ex) |
2905 | && (operand->flags & V850_OPERAND_VREG) == 0) | |
2906 | { | |
2907 | errmsg = _("syntax error: vector register not expected"); | |
2908 | } | |
252b5132 RH |
2909 | else |
2910 | { | |
28e4f854 | 2911 | expression (&ex); |
d50c498a | 2912 | resolve_register (&ex); |
1cd986c5 NC |
2913 | |
2914 | if ((operand->flags & V850_NOT_IMM0) | |
2915 | && ex.X_op == O_constant | |
2916 | && ex.X_add_number == 0) | |
2917 | { | |
2918 | errmsg = _("immediate 0 cannot be used here"); | |
2919 | } | |
2920 | ||
252b5132 | 2921 | /* Special case: |
1cd986c5 | 2922 | If we are assembling a MOV/JARL/JR instruction and the immediate |
50b15da2 | 2923 | value does not fit into the bits available then create a |
1cd986c5 | 2924 | fake error so that the next MOV/JARL/JR instruction will be |
50b15da2 | 2925 | selected. This one has a 32 bit immediate field. */ |
252b5132 | 2926 | |
1cd986c5 NC |
2927 | if ((strcmp (opcode->name, "mov") == 0 |
2928 | || strcmp (opcode->name, "jarl") == 0 | |
2929 | || strcmp (opcode->name, "jr") == 0) | |
252b5132 | 2930 | && ex.X_op == O_constant |
28e4f854 | 2931 | && (ex.X_add_number < (-(1 << (operand->bits - 1))) |
03223580 | 2932 | || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) |
1cd986c5 NC |
2933 | { |
2934 | errmsg = _("immediate operand is too large"); | |
2935 | } | |
2936 | ||
2937 | if ((strcmp (opcode->name, "jarl") == 0 | |
2938 | || strcmp (opcode->name, "jr") == 0) | |
2939 | && ex.X_op != O_constant | |
2940 | && operand->bits != default_disp_size) | |
2941 | { | |
2942 | errmsg = _("immediate operand is not match"); | |
2943 | } | |
78c8d46c NC |
2944 | |
2945 | /* Special case2 : | |
2946 | If we are assembling a ld/st instruction and the immediate | |
2947 | value does not fit into the bits available then create a | |
2948 | fake error so that the next ld/st instruction will be | |
2949 | selected. */ | |
d34049e8 ML |
2950 | if ( ( (startswith (opcode->name, "st.")) |
2951 | || (startswith (opcode->name, "ld."))) | |
78c8d46c NC |
2952 | && ex.X_op == O_constant |
2953 | && (ex.X_add_number < (-(1 << (operand->bits - 1))) | |
2954 | || ex.X_add_number > ((1 << (operand->bits - 1)) - 1))) | |
2955 | errmsg = _("displacement is too large"); | |
252b5132 RH |
2956 | } |
2957 | ||
2958 | if (errmsg) | |
2959 | goto error; | |
252b5132 | 2960 | |
28e4f854 | 2961 | switch (ex.X_op) |
252b5132 RH |
2962 | { |
2963 | case O_illegal: | |
2964 | errmsg = _("illegal operand"); | |
2965 | goto error; | |
2966 | case O_absent: | |
2967 | errmsg = _("missing operand"); | |
2968 | goto error; | |
2969 | case O_register: | |
28e4f854 | 2970 | if ((operand->flags |
1cd986c5 | 2971 | & (V850_OPERAND_REG | V850_OPERAND_SRG | V850_OPERAND_VREG)) == 0) |
252b5132 RH |
2972 | { |
2973 | errmsg = _("invalid operand"); | |
2974 | goto error; | |
2975 | } | |
1cd986c5 NC |
2976 | |
2977 | insn = v850_insert_operand (insn, operand, | |
2978 | ex.X_add_number, | |
2979 | &warningmsg); | |
2980 | ||
252b5132 RH |
2981 | break; |
2982 | ||
2983 | case O_constant: | |
2984 | insn = v850_insert_operand (insn, operand, ex.X_add_number, | |
1cd986c5 | 2985 | &warningmsg); |
252b5132 RH |
2986 | break; |
2987 | ||
2988 | default: | |
2989 | /* We need to generate a fixup for this expression. */ | |
2990 | if (fc >= MAX_INSN_FIXUPS) | |
2991 | as_fatal (_("too many fixups")); | |
2992 | ||
28e4f854 KH |
2993 | fixups[fc].exp = ex; |
2994 | fixups[fc].opindex = *opindex_ptr; | |
62ebcb5c | 2995 | fixups[fc].reloc = BFD_RELOC_NONE; |
252b5132 RH |
2996 | ++fc; |
2997 | break; | |
2998 | } | |
2999 | } | |
3000 | ||
3001 | str = input_line_pointer; | |
3002 | input_line_pointer = hold; | |
3003 | ||
3004 | while (*str == ' ' || *str == ',' || *str == '[' || *str == ']' | |
3005 | || *str == ')') | |
3006 | ++str; | |
3007 | } | |
1cd986c5 NC |
3008 | |
3009 | while (ISSPACE (*str)) | |
3010 | ++str; | |
3011 | ||
3012 | if (*str == '\0') | |
3013 | match = 1; | |
252b5132 RH |
3014 | |
3015 | error: | |
3016 | if (match == 0) | |
28e4f854 | 3017 | { |
1cd986c5 NC |
3018 | if ((opindex_ptr - opcode->operands) >= most_match_count) |
3019 | { | |
3020 | most_match_count = opindex_ptr - opcode->operands; | |
3021 | if (errmsg != NULL) | |
3022 | strncpy (most_match_errmsg, errmsg, sizeof (most_match_errmsg)-1); | |
3023 | } | |
3024 | ||
252b5132 RH |
3025 | next_opcode = opcode + 1; |
3026 | if (next_opcode->name != NULL | |
3027 | && strcmp (next_opcode->name, opcode->name) == 0) | |
3028 | { | |
3029 | opcode = next_opcode; | |
3030 | ||
3031 | /* Skip versions that are not supported by the target | |
3032 | processor. */ | |
3033 | if ((opcode->processors & processor_mask) == 0) | |
3034 | goto error; | |
28e4f854 | 3035 | |
252b5132 RH |
3036 | continue; |
3037 | } | |
28e4f854 | 3038 | |
1cd986c5 NC |
3039 | if (most_match_errmsg[0] == 0) |
3040 | /* xgettext:c-format. */ | |
3041 | as_bad (_("junk at end of line: `%s'"), str); | |
3042 | else | |
3043 | as_bad ("%s: %s", copy_of_instruction, most_match_errmsg); | |
28e4f854 KH |
3044 | |
3045 | if (*input_line_pointer == ']') | |
3046 | ++input_line_pointer; | |
3047 | ||
252b5132 RH |
3048 | ignore_rest_of_line (); |
3049 | input_line_pointer = saved_input_line_pointer; | |
3050 | return; | |
28e4f854 | 3051 | } |
1cd986c5 NC |
3052 | |
3053 | if (warningmsg != NULL) | |
cd94c7fb | 3054 | as_warn ("%s", warningmsg); |
252b5132 RH |
3055 | break; |
3056 | } | |
28e4f854 | 3057 | |
252b5132 RH |
3058 | input_line_pointer = str; |
3059 | ||
9fcc94b6 AM |
3060 | /* Tie dwarf2 debug info to the address at the start of the insn. |
3061 | We can't do this after the insn has been output as the current | |
3062 | frag may have been closed off. eg. by frag_var. */ | |
3063 | dwarf2_emit_insn (0); | |
3064 | ||
28e4f854 | 3065 | /* Write out the instruction. */ |
252b5132 RH |
3066 | if (relaxable && fc > 0) |
3067 | { | |
3068 | insn_size = 2; | |
3069 | fc = 0; | |
3070 | ||
78c8d46c NC |
3071 | if (strcmp (opcode->name, "loop") == 0) |
3072 | { | |
3073 | if (((processor_mask & PROCESSOR_V850E3V5_UP) == 0) || default_disp_size == 22) | |
3074 | { | |
3075 | insn_size = 4; | |
3076 | f = frag_var (rs_machine_dependent, 6, 2, SUBYPTE_LOOP_16_22, | |
3077 | fixups[0].exp.X_add_symbol, | |
3078 | fixups[0].exp.X_add_number, | |
3079 | (char *)(size_t) fixups[0].opindex); | |
3080 | md_number_to_chars (f, insn, insn_size); | |
3081 | md_number_to_chars (f+4, 0, 4); | |
3082 | } | |
3083 | else | |
3084 | { | |
3085 | as_bad (_("loop: 32-bit displacement not supported")); | |
3086 | } | |
3087 | } | |
3088 | else if (strcmp (opcode->name, "br") == 0 | |
3089 | || strcmp (opcode->name, "jbr") == 0) | |
252b5132 | 3090 | { |
78c8d46c | 3091 | if ((processor_mask & PROCESSOR_V850E2_UP) == 0 || default_disp_size == 22) |
1cd986c5 NC |
3092 | { |
3093 | f = frag_var (rs_machine_dependent, 4, 2, SUBYPTE_UNCOND_9_22, | |
3094 | fixups[0].exp.X_add_symbol, | |
3095 | fixups[0].exp.X_add_number, | |
3096 | (char *)(size_t) fixups[0].opindex); | |
3097 | md_number_to_chars (f, insn, insn_size); | |
3098 | md_number_to_chars (f + 2, 0, 2); | |
3099 | } | |
3100 | else | |
3101 | { | |
3102 | f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_UNCOND_9_22_32, | |
3103 | fixups[0].exp.X_add_symbol, | |
3104 | fixups[0].exp.X_add_number, | |
3105 | (char *)(size_t) fixups[0].opindex); | |
3106 | md_number_to_chars (f, insn, insn_size); | |
3107 | md_number_to_chars (f + 2, 0, 4); | |
3108 | } | |
252b5132 | 3109 | } |
1cd986c5 | 3110 | else /* b<cond>, j<cond>. */ |
252b5132 | 3111 | { |
1cd986c5 | 3112 | if (default_disp_size == 22 |
78c8d46c | 3113 | || (processor_mask & PROCESSOR_V850E2_UP) == 0) |
1cd986c5 | 3114 | { |
78c8d46c | 3115 | if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) |
1cd986c5 NC |
3116 | { |
3117 | if (strcmp (opcode->name, "bsa") == 0) | |
3118 | { | |
3119 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_17_22, | |
3120 | fixups[0].exp.X_add_symbol, | |
3121 | fixups[0].exp.X_add_number, | |
3122 | (char *)(size_t) fixups[0].opindex); | |
3123 | md_number_to_chars (f, insn, insn_size); | |
3124 | md_number_to_chars (f + 2, 0, 6); | |
3125 | } | |
3126 | else | |
3127 | { | |
3128 | f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_17_22, | |
3129 | fixups[0].exp.X_add_symbol, | |
3130 | fixups[0].exp.X_add_number, | |
3131 | (char *)(size_t) fixups[0].opindex); | |
3132 | md_number_to_chars (f, insn, insn_size); | |
3133 | md_number_to_chars (f + 2, 0, 4); | |
3134 | } | |
3135 | } | |
3136 | else | |
3137 | { | |
3138 | if (strcmp (opcode->name, "bsa") == 0) | |
3139 | { | |
3140 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_SA_9_22, | |
3141 | fixups[0].exp.X_add_symbol, | |
3142 | fixups[0].exp.X_add_number, | |
3143 | (char *)(size_t) fixups[0].opindex); | |
3144 | md_number_to_chars (f, insn, insn_size); | |
3145 | md_number_to_chars (f + 2, 0, 6); | |
3146 | } | |
3147 | else | |
3148 | { | |
3149 | f = frag_var (rs_machine_dependent, 6, 4, SUBYPTE_COND_9_22, | |
3150 | fixups[0].exp.X_add_symbol, | |
3151 | fixups[0].exp.X_add_number, | |
3152 | (char *)(size_t) fixups[0].opindex); | |
3153 | md_number_to_chars (f, insn, insn_size); | |
3154 | md_number_to_chars (f + 2, 0, 4); | |
3155 | } | |
3156 | } | |
3157 | } | |
3158 | else | |
3159 | { | |
78c8d46c | 3160 | if (processor_mask & PROCESSOR_V850E2V3_UP && !no_bcond17) |
1cd986c5 NC |
3161 | { |
3162 | if (strcmp (opcode->name, "bsa") == 0) | |
3163 | { | |
3164 | f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_17_22_32, | |
3165 | fixups[0].exp.X_add_symbol, | |
3166 | fixups[0].exp.X_add_number, | |
3167 | (char *)(size_t) fixups[0].opindex); | |
3168 | md_number_to_chars (f, insn, insn_size); | |
3169 | md_number_to_chars (f + 2, 0, 8); | |
3170 | } | |
3171 | else | |
3172 | { | |
3173 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_17_22_32, | |
3174 | fixups[0].exp.X_add_symbol, | |
3175 | fixups[0].exp.X_add_number, | |
3176 | (char *)(size_t) fixups[0].opindex); | |
3177 | md_number_to_chars (f, insn, insn_size); | |
3178 | md_number_to_chars (f + 2, 0, 6); | |
3179 | } | |
3180 | } | |
3181 | else | |
3182 | { | |
3183 | if (strcmp (opcode->name, "bsa") == 0) | |
3184 | { | |
3185 | f = frag_var (rs_machine_dependent, 10, 8, SUBYPTE_SA_9_22_32, | |
3186 | fixups[0].exp.X_add_symbol, | |
3187 | fixups[0].exp.X_add_number, | |
3188 | (char *)(size_t) fixups[0].opindex); | |
3189 | md_number_to_chars (f, insn, insn_size); | |
3190 | md_number_to_chars (f + 2, 0, 8); | |
3191 | } | |
3192 | else | |
3193 | { | |
3194 | f = frag_var (rs_machine_dependent, 8, 6, SUBYPTE_COND_9_22_32, | |
3195 | fixups[0].exp.X_add_symbol, | |
3196 | fixups[0].exp.X_add_number, | |
3197 | (char *)(size_t) fixups[0].opindex); | |
3198 | md_number_to_chars (f, insn, insn_size); | |
3199 | md_number_to_chars (f + 2, 0, 6); | |
3200 | } | |
3201 | } | |
3202 | } | |
252b5132 RH |
3203 | } |
3204 | } | |
28e4f854 | 3205 | else |
252b5132 RH |
3206 | { |
3207 | /* Four byte insns have an opcode with the two high bits on. */ | |
3208 | if ((insn & 0x0600) == 0x0600) | |
3209 | insn_size = 4; | |
3210 | else | |
3211 | insn_size = 2; | |
3212 | ||
28e4f854 | 3213 | /* Special case: 32 bit MOV. */ |
252b5132 RH |
3214 | if ((insn & 0xffe0) == 0x0620) |
3215 | insn_size = 2; | |
28e4f854 | 3216 | |
1cd986c5 NC |
3217 | /* Special case: 32 bit JARL,JMP,JR. */ |
3218 | if ((insn & 0x1ffe0) == 0x2e0 /* JARL. */ | |
3219 | || (insn & 0x1ffe0) == 0x6e0 /* JMP. */ | |
3220 | || (insn & 0x1ffff) == 0x2e0) /* JR. */ | |
3221 | insn_size = 2; | |
3222 | ||
78c8d46c NC |
3223 | if (obstack_room (& frchain_now->frch_obstack) < (insn_size + extra_data_len)) |
3224 | { | |
3225 | frag_wane (frag_now); | |
3226 | frag_new (0); | |
3227 | } | |
3228 | ||
252b5132 | 3229 | f = frag_more (insn_size); |
252b5132 RH |
3230 | md_number_to_chars (f, insn, insn_size); |
3231 | ||
3232 | if (extra_data_after_insn) | |
3233 | { | |
3234 | f = frag_more (extra_data_len); | |
252b5132 RH |
3235 | md_number_to_chars (f, extra_data, extra_data_len); |
3236 | ||
5b7c81bd | 3237 | extra_data_after_insn = false; |
252b5132 RH |
3238 | } |
3239 | } | |
3240 | ||
3241 | /* Create any fixups. At this point we do not use a | |
3242 | bfd_reloc_code_real_type, but instead just use the | |
3243 | BFD_RELOC_UNUSED plus the operand index. This lets us easily | |
3244 | handle fixups for any operand type, although that is admittedly | |
3245 | not a very exciting feature. We pick a BFD reloc type in | |
55cf6793 | 3246 | md_apply_fix. */ |
252b5132 RH |
3247 | for (i = 0; i < fc; i++) |
3248 | { | |
28e4f854 KH |
3249 | const struct v850_operand *operand; |
3250 | bfd_reloc_code_real_type reloc; | |
3251 | ||
3252 | operand = &v850_operands[fixups[i].opindex]; | |
252b5132 RH |
3253 | |
3254 | reloc = fixups[i].reloc; | |
28e4f854 | 3255 | |
62ebcb5c | 3256 | if (reloc != BFD_RELOC_NONE) |
252b5132 | 3257 | { |
28e4f854 KH |
3258 | reloc_howto_type *reloc_howto = |
3259 | bfd_reloc_type_lookup (stdoutput, reloc); | |
3260 | int size; | |
3261 | int address; | |
3262 | fixS *fixP; | |
252b5132 RH |
3263 | |
3264 | if (!reloc_howto) | |
28e4f854 KH |
3265 | abort (); |
3266 | ||
252b5132 RH |
3267 | size = bfd_get_reloc_size (reloc_howto); |
3268 | ||
3269 | /* XXX This will abort on an R_V850_8 reloc - | |
28e4f854 KH |
3270 | is this reloc actually used? */ |
3271 | if (size != 2 && size != 4) | |
252b5132 RH |
3272 | abort (); |
3273 | ||
1cd986c5 NC |
3274 | if (extra_data_len == 0) |
3275 | { | |
3276 | address = (f - frag_now->fr_literal) + insn_size - size; | |
3277 | } | |
3278 | else | |
3279 | { | |
3280 | address = (f - frag_now->fr_literal) + extra_data_len - size; | |
3281 | } | |
252b5132 | 3282 | |
1cd986c5 NC |
3283 | if ((operand->flags & V850E_IMMEDIATE32) && (operand->flags & V850_PCREL)) |
3284 | { | |
3285 | fixups[i].exp.X_add_number += 2; | |
3286 | } | |
3287 | else if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) | |
3288 | { | |
3289 | fixups[i].exp.X_add_number += 2; | |
3290 | address += 2; | |
3291 | } | |
28e4f854 | 3292 | |
1cd986c5 | 3293 | /* fprintf (stderr, "0x%x %d %ld\n", address, size, fixups[i].exp.X_add_number); */ |
252b5132 | 3294 | fixP = fix_new_exp (frag_now, address, size, |
28e4f854 | 3295 | &fixups[i].exp, |
252b5132 RH |
3296 | reloc_howto->pc_relative, |
3297 | reloc); | |
3298 | ||
2d034539 NC |
3299 | fixP->tc_fix_data = (void *) operand; |
3300 | ||
252b5132 RH |
3301 | switch (reloc) |
3302 | { | |
3303 | case BFD_RELOC_LO16: | |
1cd986c5 | 3304 | case BFD_RELOC_V850_LO16_S1: |
1e50d24d | 3305 | case BFD_RELOC_V850_LO16_SPLIT_OFFSET: |
252b5132 RH |
3306 | case BFD_RELOC_HI16: |
3307 | case BFD_RELOC_HI16_S: | |
3308 | fixP->fx_no_overflow = 1; | |
3309 | break; | |
5480ccf3 NC |
3310 | default: |
3311 | break; | |
252b5132 RH |
3312 | } |
3313 | } | |
3314 | else | |
3315 | { | |
78c8d46c | 3316 | gas_assert (f != NULL); |
28e4f854 | 3317 | fix_new_exp (frag_now, |
252b5132 RH |
3318 | f - frag_now->fr_literal, 4, |
3319 | & fixups[i].exp, | |
1cd986c5 | 3320 | (operand->flags & V850_PCREL) != 0, |
252b5132 | 3321 | (bfd_reloc_code_real_type) (fixups[i].opindex |
28e4f854 | 3322 | + (int) BFD_RELOC_UNUSED)); |
252b5132 RH |
3323 | } |
3324 | } | |
3325 | ||
3326 | input_line_pointer = saved_input_line_pointer; | |
3327 | } | |
3328 | ||
28e4f854 KH |
3329 | /* If while processing a fixup, a reloc really needs to be created |
3330 | then it is done here. */ | |
252b5132 | 3331 | |
252b5132 | 3332 | arelent * |
ea1562b3 | 3333 | tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) |
252b5132 | 3334 | { |
28e4f854 KH |
3335 | arelent *reloc; |
3336 | ||
add39d23 TS |
3337 | reloc = XNEW (arelent); |
3338 | reloc->sym_ptr_ptr = XNEW (asymbol *); | |
28e4f854 KH |
3339 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
3340 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
e30ddb24 NC |
3341 | |
3342 | if ( fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY | |
3343 | || fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
3344 | || fixp->fx_r_type == BFD_RELOC_V850_LONGCALL | |
3345 | || fixp->fx_r_type == BFD_RELOC_V850_LONGJUMP | |
3346 | || fixp->fx_r_type == BFD_RELOC_V850_ALIGN) | |
3347 | reloc->addend = fixp->fx_offset; | |
3348 | else | |
3349 | { | |
1cd986c5 | 3350 | #if 0 |
e30ddb24 NC |
3351 | if (fixp->fx_r_type == BFD_RELOC_32 |
3352 | && fixp->fx_pcrel) | |
3353 | fixp->fx_r_type = BFD_RELOC_32_PCREL; | |
1cd986c5 | 3354 | #endif |
e30ddb24 NC |
3355 | |
3356 | reloc->addend = fixp->fx_addnumber; | |
3357 | } | |
3358 | ||
ec178e1b | 3359 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
252b5132 | 3360 | |
ea1562b3 | 3361 | if (reloc->howto == NULL) |
252b5132 RH |
3362 | { |
3363 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
28e4f854 KH |
3364 | /* xgettext:c-format */ |
3365 | _("reloc %d not supported by object file format"), | |
252b5132 RH |
3366 | (int) fixp->fx_r_type); |
3367 | ||
3368 | xfree (reloc); | |
28e4f854 | 3369 | |
252b5132 RH |
3370 | return NULL; |
3371 | } | |
28e4f854 | 3372 | |
252b5132 RH |
3373 | return reloc; |
3374 | } | |
3375 | ||
86aba9db | 3376 | void |
ea1562b3 | 3377 | v850_handle_align (fragS * frag) |
86aba9db NC |
3378 | { |
3379 | if (v850_relax | |
3380 | && frag->fr_type == rs_align | |
3381 | && frag->fr_address + frag->fr_fix > 0 | |
3382 | && frag->fr_offset > 1 | |
3383 | && now_seg != bss_section | |
3384 | && now_seg != v850_seg_table[SBSS_SECTION].s | |
3385 | && now_seg != v850_seg_table[TBSS_SECTION].s | |
3386 | && now_seg != v850_seg_table[ZBSS_SECTION].s) | |
3387 | fix_new (frag, frag->fr_fix, 2, & abs_symbol, frag->fr_offset, 0, | |
ec178e1b | 3388 | BFD_RELOC_V850_ALIGN); |
86aba9db NC |
3389 | } |
3390 | ||
606ab118 | 3391 | /* Return current size of variable part of frag. */ |
28e4f854 | 3392 | |
252b5132 | 3393 | int |
ea1562b3 | 3394 | md_estimate_size_before_relax (fragS *fragp, asection *seg ATTRIBUTE_UNUSED) |
252b5132 | 3395 | { |
606ab118 | 3396 | if (fragp->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) |
252b5132 | 3397 | abort (); |
606ab118 AM |
3398 | |
3399 | return md_relax_table[fragp->fr_subtype].rlx_length; | |
28e4f854 | 3400 | } |
252b5132 RH |
3401 | |
3402 | long | |
ea1562b3 | 3403 | v850_pcrel_from_section (fixS *fixp, segT section) |
252b5132 RH |
3404 | { |
3405 | /* If the symbol is undefined, or in a section other than our own, | |
d6c497c7 | 3406 | or it is weak (in which case it may well be in another section, |
252b5132 RH |
3407 | then let the linker figure it out. */ |
3408 | if (fixp->fx_addsy != (symbolS *) NULL | |
3409 | && (! S_IS_DEFINED (fixp->fx_addsy) | |
d6c497c7 | 3410 | || S_IS_WEAK (fixp->fx_addsy) |
252b5132 | 3411 | || (S_GET_SEGMENT (fixp->fx_addsy) != section))) |
d6c497c7 | 3412 | return 0; |
28e4f854 | 3413 | |
252b5132 RH |
3414 | return fixp->fx_frag->fr_address + fixp->fx_where; |
3415 | } | |
3416 | ||
94f592af | 3417 | void |
55cf6793 | 3418 | md_apply_fix (fixS *fixP, valueT *valueP, segT seg ATTRIBUTE_UNUSED) |
252b5132 | 3419 | { |
94f592af | 3420 | valueT value = * valueP; |
28e4f854 | 3421 | char *where; |
252b5132 | 3422 | |
94f592af | 3423 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
86aba9db NC |
3424 | || fixP->fx_r_type == BFD_RELOC_V850_LONGCALL |
3425 | || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP | |
94f592af | 3426 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
252b5132 | 3427 | { |
94f592af NC |
3428 | fixP->fx_done = 0; |
3429 | return; | |
252b5132 RH |
3430 | } |
3431 | ||
94f592af | 3432 | if (fixP->fx_addsy == (symbolS *) NULL) |
86aba9db | 3433 | fixP->fx_addnumber = value, |
94f592af NC |
3434 | fixP->fx_done = 1; |
3435 | ||
3436 | else if (fixP->fx_pcrel) | |
86aba9db | 3437 | fixP->fx_addnumber = fixP->fx_offset; |
94f592af | 3438 | |
252b5132 RH |
3439 | else |
3440 | { | |
94f592af NC |
3441 | value = fixP->fx_offset; |
3442 | if (fixP->fx_subsy != (symbolS *) NULL) | |
252b5132 | 3443 | { |
94f592af NC |
3444 | if (S_GET_SEGMENT (fixP->fx_subsy) == absolute_section) |
3445 | value -= S_GET_VALUE (fixP->fx_subsy); | |
252b5132 | 3446 | else |
ea1562b3 | 3447 | /* We don't actually support subtracting a symbol. */ |
4bf09429 | 3448 | as_bad_subtract (fixP); |
252b5132 | 3449 | } |
86aba9db | 3450 | fixP->fx_addnumber = value; |
252b5132 RH |
3451 | } |
3452 | ||
94f592af | 3453 | if ((int) fixP->fx_r_type >= (int) BFD_RELOC_UNUSED) |
252b5132 | 3454 | { |
28e4f854 KH |
3455 | int opindex; |
3456 | const struct v850_operand *operand; | |
3457 | unsigned long insn; | |
1cd986c5 | 3458 | const char *errmsg = NULL; |
252b5132 | 3459 | |
94f592af | 3460 | opindex = (int) fixP->fx_r_type - (int) BFD_RELOC_UNUSED; |
28e4f854 | 3461 | operand = &v850_operands[opindex]; |
252b5132 RH |
3462 | |
3463 | /* Fetch the instruction, insert the fully resolved operand | |
ec178e1b | 3464 | value, and stuff the instruction back again. |
252b5132 RH |
3465 | |
3466 | Note the instruction has been stored in little endian | |
3467 | format! */ | |
94f592af | 3468 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 3469 | |
1cd986c5 NC |
3470 | if (fixP->fx_size > 2) |
3471 | insn = bfd_getl32 ((unsigned char *) where); | |
3472 | else | |
3473 | insn = bfd_getl16 ((unsigned char *) where); | |
3474 | ||
33eaf5de | 3475 | /* When inserting loop offsets a backwards displacement |
86d27af6 NC |
3476 | is encoded as a positive value. */ |
3477 | if (operand->flags & V850_INVERSE_PCREL) | |
3478 | value = - value; | |
3479 | ||
252b5132 | 3480 | insn = v850_insert_operand (insn, operand, (offsetT) value, |
1cd986c5 NC |
3481 | &errmsg); |
3482 | if (errmsg) | |
cd94c7fb | 3483 | as_warn_where (fixP->fx_file, fixP->fx_line, "%s", errmsg); |
1cd986c5 NC |
3484 | |
3485 | if (fixP->fx_size > 2) | |
3486 | bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); | |
3487 | else | |
3488 | bfd_putl16 ((bfd_vma) insn, (unsigned char *) where); | |
252b5132 | 3489 | |
94f592af NC |
3490 | if (fixP->fx_done) |
3491 | /* Nothing else to do here. */ | |
3492 | return; | |
252b5132 | 3493 | |
28e4f854 KH |
3494 | /* Determine a BFD reloc value based on the operand information. |
3495 | We are only prepared to turn a few of the operands into relocs. */ | |
252b5132 | 3496 | |
1cd986c5 | 3497 | if (operand->default_reloc == BFD_RELOC_NONE) |
252b5132 | 3498 | { |
94f592af | 3499 | as_bad_where (fixP->fx_file, fixP->fx_line, |
28e4f854 | 3500 | _("unresolved expression that must be resolved")); |
94f592af NC |
3501 | fixP->fx_done = 1; |
3502 | return; | |
252b5132 | 3503 | } |
1cd986c5 NC |
3504 | |
3505 | { | |
3506 | fixP->fx_r_type = operand->default_reloc; | |
3507 | if (operand->default_reloc == BFD_RELOC_V850_16_PCREL) | |
3508 | { | |
3509 | fixP->fx_where += 2; | |
3510 | fixP->fx_size = 2; | |
3511 | fixP->fx_addnumber += 2; | |
3512 | } | |
3513 | } | |
252b5132 | 3514 | } |
94f592af | 3515 | else if (fixP->fx_done) |
252b5132 RH |
3516 | { |
3517 | /* We still have to insert the value into memory! */ | |
94f592af | 3518 | where = fixP->fx_frag->fr_literal + fixP->fx_where; |
252b5132 | 3519 | |
a0ef61f7 | 3520 | if (fixP->tc_fix_data != NULL |
1cd986c5 NC |
3521 | && ((struct v850_operand *) fixP->tc_fix_data)->insert != NULL) |
3522 | { | |
3523 | const char * message = NULL; | |
3524 | struct v850_operand * operand = (struct v850_operand *) fixP->tc_fix_data; | |
3525 | unsigned long insn; | |
3526 | ||
3527 | /* The variable "where" currently points at the exact point inside | |
3528 | the insn where we need to insert the value. But we need to | |
3529 | extract the entire insn so we probably need to move "where" | |
3530 | back a few bytes. */ | |
3531 | ||
3532 | if (fixP->fx_size == 2) | |
3533 | where -= 2; | |
3534 | else if (fixP->fx_size == 1) | |
3535 | where -= 3; | |
3536 | ||
3537 | insn = bfd_getl32 ((unsigned char *) where); | |
3538 | ||
3539 | /* Use the operand's insertion procedure, if present, in order to | |
3540 | make sure that the value is correctly stored in the insn. */ | |
3541 | insn = operand->insert (insn, (offsetT) value, & message); | |
3542 | /* Ignore message even if it is set. */ | |
3543 | ||
3544 | bfd_putl32 ((bfd_vma) insn, (unsigned char *) where); | |
3545 | } | |
2d034539 | 3546 | else |
1cd986c5 NC |
3547 | { |
3548 | switch (fixP->fx_r_type) | |
3549 | { | |
3550 | case BFD_RELOC_V850_32_ABS: | |
3551 | case BFD_RELOC_V850_32_PCREL: | |
3552 | bfd_putl32 (value & 0xfffffffe, (unsigned char *) where); | |
3553 | break; | |
3554 | ||
3555 | case BFD_RELOC_32: | |
3556 | bfd_putl32 (value, (unsigned char *) where); | |
3557 | break; | |
3558 | ||
3559 | case BFD_RELOC_V850_23: | |
3560 | bfd_putl32 (((value & 0x7f) << 4) | ((value & 0x7fff80) << (16-7)) | |
3561 | | (bfd_getl32 (where) & ~((0x7f << 4) | (0xffff << 16))), | |
3562 | (unsigned char *) where); | |
3563 | break; | |
3564 | ||
3565 | case BFD_RELOC_16: | |
3566 | case BFD_RELOC_HI16: | |
3567 | case BFD_RELOC_HI16_S: | |
3568 | case BFD_RELOC_LO16: | |
3569 | case BFD_RELOC_V850_ZDA_16_16_OFFSET: | |
3570 | case BFD_RELOC_V850_SDA_16_16_OFFSET: | |
3571 | case BFD_RELOC_V850_TDA_16_16_OFFSET: | |
3572 | case BFD_RELOC_V850_CALLT_16_16_OFFSET: | |
3573 | bfd_putl16 (value & 0xffff, (unsigned char *) where); | |
3574 | break; | |
3575 | ||
3576 | case BFD_RELOC_8: | |
3577 | *where = value & 0xff; | |
3578 | break; | |
3579 | ||
3580 | case BFD_RELOC_V850_9_PCREL: | |
3581 | bfd_putl16 (((value & 0x1f0) << 7) | ((value & 0x0e) << 3) | |
3582 | | (bfd_getl16 (where) & ~((0x1f0 << 7) | (0x0e << 3))), where); | |
3583 | break; | |
3584 | ||
3585 | case BFD_RELOC_V850_17_PCREL: | |
3586 | bfd_putl32 (((value & 0x10000) >> (16 - 4)) | ((value & 0xfffe) << 16) | |
3587 | | (bfd_getl32 (where) & ~((0x10000 >> (16 - 4)) | (0xfffe << 16))), where); | |
3588 | break; | |
3589 | ||
3590 | case BFD_RELOC_V850_16_PCREL: | |
de863c74 NC |
3591 | bfd_putl16 ((-value & 0xfffe) | (bfd_getl16 (where + 2) & 0x0001), |
3592 | (unsigned char *) (where + 2)); | |
1cd986c5 NC |
3593 | break; |
3594 | ||
3595 | case BFD_RELOC_V850_22_PCREL: | |
3596 | bfd_putl32 (((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16) | |
3597 | | (bfd_getl32 (where) & ~((0xfffe << 16) | (0x3f0000 >> 16))), where); | |
3598 | break; | |
3599 | ||
3600 | case BFD_RELOC_V850_16_S1: | |
3601 | case BFD_RELOC_V850_LO16_S1: | |
3602 | case BFD_RELOC_V850_ZDA_15_16_OFFSET: | |
3603 | case BFD_RELOC_V850_SDA_15_16_OFFSET: | |
3604 | bfd_putl16 (value & 0xfffe, (unsigned char *) where); | |
3605 | break; | |
3606 | ||
3607 | case BFD_RELOC_V850_16_SPLIT_OFFSET: | |
3608 | case BFD_RELOC_V850_LO16_SPLIT_OFFSET: | |
3609 | case BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET: | |
3610 | case BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET: | |
3611 | bfd_putl32 (((value << 16) & 0xfffe0000) | |
3612 | | ((value << 5) & 0x20) | |
3613 | | (bfd_getl32 (where) & ~0xfffe0020), where); | |
3614 | break; | |
3615 | ||
3616 | case BFD_RELOC_V850_TDA_6_8_OFFSET: | |
3617 | *where = (*where & ~0x7e) | ((value >> 1) & 0x7e); | |
3618 | break; | |
3619 | ||
3620 | case BFD_RELOC_V850_TDA_7_8_OFFSET: | |
3621 | *where = (*where & ~0x7f) | ((value >> 1) & 0x7f); | |
3622 | break; | |
3623 | ||
3624 | case BFD_RELOC_V850_TDA_7_7_OFFSET: | |
3625 | *where = (*where & ~0x7f) | (value & 0x7f); | |
3626 | break; | |
3627 | ||
3628 | case BFD_RELOC_V850_TDA_4_5_OFFSET: | |
3629 | *where = (*where & ~0xf) | ((value >> 1) & 0xf); | |
3630 | break; | |
3631 | ||
3632 | case BFD_RELOC_V850_TDA_4_4_OFFSET: | |
3633 | *where = (*where & ~0xf) | (value & 0xf); | |
3634 | break; | |
3635 | ||
3636 | case BFD_RELOC_V850_CALLT_6_7_OFFSET: | |
3637 | *where = (*where & ~0x3f) | (value & 0x3f); | |
3638 | break; | |
3639 | ||
3640 | default: | |
3641 | abort (); | |
3642 | } | |
3643 | } | |
252b5132 | 3644 | } |
252b5132 | 3645 | } |
1cd986c5 | 3646 | |
252b5132 RH |
3647 | /* Parse a cons expression. We have to handle hi(), lo(), etc |
3648 | on the v850. */ | |
28e4f854 | 3649 | |
62ebcb5c | 3650 | bfd_reloc_code_real_type |
ea1562b3 | 3651 | parse_cons_expression_v850 (expressionS *exp) |
252b5132 | 3652 | { |
1cd986c5 | 3653 | const char *errmsg; |
62ebcb5c AM |
3654 | bfd_reloc_code_real_type r; |
3655 | ||
252b5132 | 3656 | /* See if there's a reloc prefix like hi() we have to handle. */ |
62ebcb5c | 3657 | r = v850_reloc_prefix (NULL, &errmsg); |
252b5132 RH |
3658 | |
3659 | /* Do normal expression parsing. */ | |
3660 | expression (exp); | |
62ebcb5c | 3661 | return r; |
252b5132 RH |
3662 | } |
3663 | ||
3664 | /* Create a fixup for a cons expression. If parse_cons_expression_v850 | |
3665 | found a reloc prefix, then we use that reloc, else we choose an | |
3666 | appropriate one based on the size of the expression. */ | |
28e4f854 | 3667 | |
252b5132 | 3668 | void |
ea1562b3 NC |
3669 | cons_fix_new_v850 (fragS *frag, |
3670 | int where, | |
3671 | int size, | |
62ebcb5c AM |
3672 | expressionS *exp, |
3673 | bfd_reloc_code_real_type r) | |
252b5132 | 3674 | { |
62ebcb5c | 3675 | if (r == BFD_RELOC_NONE) |
252b5132 RH |
3676 | { |
3677 | if (size == 4) | |
62ebcb5c | 3678 | r = BFD_RELOC_32; |
252b5132 | 3679 | if (size == 2) |
62ebcb5c | 3680 | r = BFD_RELOC_16; |
252b5132 | 3681 | if (size == 1) |
62ebcb5c | 3682 | r = BFD_RELOC_8; |
252b5132 RH |
3683 | } |
3684 | ||
3685 | if (exp != NULL) | |
62ebcb5c | 3686 | fix_new_exp (frag, where, size, exp, 0, r); |
252b5132 | 3687 | else |
62ebcb5c | 3688 | fix_new (frag, where, size, NULL, 0, 0, r); |
252b5132 | 3689 | } |
d6c497c7 | 3690 | |
5b7c81bd | 3691 | bool |
ea1562b3 | 3692 | v850_fix_adjustable (fixS *fixP) |
252b5132 | 3693 | { |
252b5132 RH |
3694 | if (fixP->fx_addsy == NULL) |
3695 | return 1; | |
28e4f854 | 3696 | |
28e4f854 | 3697 | /* Don't adjust function names. */ |
252b5132 RH |
3698 | if (S_IS_FUNCTION (fixP->fx_addsy)) |
3699 | return 0; | |
3700 | ||
28e4f854 KH |
3701 | /* We need the symbol name for the VTABLE entries. */ |
3702 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
252b5132 RH |
3703 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
3704 | return 0; | |
28e4f854 | 3705 | |
252b5132 RH |
3706 | return 1; |
3707 | } | |
28e4f854 | 3708 | |
252b5132 | 3709 | int |
ea1562b3 | 3710 | v850_force_relocation (struct fix *fixP) |
252b5132 | 3711 | { |
a161fe53 | 3712 | if (fixP->fx_r_type == BFD_RELOC_V850_LONGCALL |
86aba9db NC |
3713 | || fixP->fx_r_type == BFD_RELOC_V850_LONGJUMP) |
3714 | return 1; | |
3715 | ||
3716 | if (v850_relax | |
3717 | && (fixP->fx_pcrel | |
a161fe53 | 3718 | || fixP->fx_r_type == BFD_RELOC_V850_ALIGN |
a161fe53 | 3719 | || fixP->fx_r_type == BFD_RELOC_V850_9_PCREL |
1cd986c5 NC |
3720 | || fixP->fx_r_type == BFD_RELOC_V850_16_PCREL |
3721 | || fixP->fx_r_type == BFD_RELOC_V850_17_PCREL | |
3722 | || fixP->fx_r_type == BFD_RELOC_V850_22_PCREL | |
3723 | || fixP->fx_r_type == BFD_RELOC_V850_32_PCREL | |
a161fe53 | 3724 | || fixP->fx_r_type >= BFD_RELOC_UNUSED)) |
86aba9db NC |
3725 | return 1; |
3726 | ||
ae6063d4 | 3727 | return generic_force_reloc (fixP); |
252b5132 | 3728 | } |
685080f2 NC |
3729 | |
3730 | /* Create a v850 note section. */ | |
3731 | void | |
ed2917de | 3732 | v850_md_finish (void) |
685080f2 NC |
3733 | { |
3734 | segT note_sec; | |
3735 | segT orig_seg = now_seg; | |
3736 | subsegT orig_subseg = now_subseg; | |
3737 | enum v850_notes id; | |
3738 | ||
3739 | note_sec = subseg_new (V850_NOTE_SECNAME, 0); | |
fd361982 AM |
3740 | bfd_set_section_flags (note_sec, SEC_HAS_CONTENTS | SEC_READONLY | SEC_MERGE); |
3741 | bfd_set_section_alignment (note_sec, 2); | |
685080f2 NC |
3742 | |
3743 | /* Provide default values for all of the notes. */ | |
3744 | for (id = V850_NOTE_ALIGNMENT; id <= NUM_V850_NOTES; id++) | |
3745 | { | |
3746 | int val = 0; | |
3747 | char * p; | |
3748 | ||
3749 | /* Follow the standard note section layout: | |
3750 | First write the length of the name string. */ | |
3751 | p = frag_more (4); | |
3752 | md_number_to_chars (p, 4, 4); | |
3753 | ||
3754 | /* Next comes the length of the "descriptor", i.e., the actual data. */ | |
3755 | p = frag_more (4); | |
3756 | md_number_to_chars (p, 4, 4); | |
3757 | ||
3758 | /* Write the note type. */ | |
3759 | p = frag_more (4); | |
3760 | md_number_to_chars (p, (valueT) id, 4); | |
3761 | ||
3762 | /* Write the name field. */ | |
3763 | p = frag_more (4); | |
3764 | memcpy (p, V850_NOTE_NAME, 4); | |
3765 | ||
3766 | /* Finally, write the descriptor. */ | |
3767 | p = frag_more (4); | |
3768 | switch (id) | |
3769 | { | |
3770 | case V850_NOTE_ALIGNMENT: | |
3771 | val = v850_data_8 ? EF_RH850_DATA_ALIGN8 : EF_RH850_DATA_ALIGN4; | |
3772 | break; | |
3773 | ||
3774 | case V850_NOTE_DATA_SIZE: | |
3775 | /* GCC does not currently support an option | |
3776 | for 32-bit doubles with the V850 backend. */ | |
3777 | val = EF_RH850_DOUBLE64; | |
3778 | break; | |
3779 | ||
3780 | case V850_NOTE_FPU_INFO: | |
3781 | if (! soft_float) | |
3782 | switch (machine) | |
3783 | { | |
3784 | case bfd_mach_v850e3v5: val = EF_RH850_FPU30; break; | |
3785 | case bfd_mach_v850e2v3: val = EF_RH850_FPU20; break; | |
3786 | default: break; | |
3787 | } | |
3788 | break; | |
3789 | ||
3790 | default: | |
3791 | break; | |
3792 | } | |
3793 | md_number_to_chars (p, val, 4); | |
3794 | } | |
3795 | ||
3796 | /* Paranoia - we probably do not need this. */ | |
3797 | subseg_set (orig_seg, orig_subseg); | |
3798 | } |