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e0001a05 | 1 | /* tc-xtensa.c -- Assemble Xtensa instructions. |
d47d412e | 2 | Copyright 2003, 2004, 2005, 2006 Free Software Foundation, Inc. |
e0001a05 NC |
3 | |
4 | This file is part of GAS, the GNU Assembler. | |
5 | ||
6 | GAS is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GAS is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to | |
4b4da160 NC |
18 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
e0001a05 | 20 | |
43cd72b9 | 21 | #include <limits.h> |
e0001a05 NC |
22 | #include "as.h" |
23 | #include "sb.h" | |
24 | #include "safe-ctype.h" | |
25 | #include "tc-xtensa.h" | |
e0001a05 NC |
26 | #include "subsegs.h" |
27 | #include "xtensa-relax.h" | |
28 | #include "xtensa-istack.h" | |
cda2eb9e | 29 | #include "dwarf2dbg.h" |
e0001a05 NC |
30 | #include "struc-symbol.h" |
31 | #include "xtensa-config.h" | |
32 | ||
33 | #ifndef uint32 | |
34 | #define uint32 unsigned int | |
35 | #endif | |
36 | #ifndef int32 | |
37 | #define int32 signed int | |
38 | #endif | |
39 | ||
40 | /* Notes: | |
41 | ||
e0001a05 NC |
42 | Naming conventions (used somewhat inconsistently): |
43 | The xtensa_ functions are exported | |
44 | The xg_ functions are internal | |
45 | ||
46 | We also have a couple of different extensibility mechanisms. | |
47 | 1) The idiom replacement: | |
48 | This is used when a line is first parsed to | |
49 | replace an instruction pattern with another instruction | |
50 | It is currently limited to replacements of instructions | |
51 | with constant operands. | |
52 | 2) The xtensa-relax.c mechanism that has stronger instruction | |
53 | replacement patterns. When an instruction's immediate field | |
54 | does not fit the next instruction sequence is attempted. | |
55 | In addition, "narrow" opcodes are supported this way. */ | |
56 | ||
57 | ||
58 | /* Define characters with special meanings to GAS. */ | |
59 | const char comment_chars[] = "#"; | |
60 | const char line_comment_chars[] = "#"; | |
61 | const char line_separator_chars[] = ";"; | |
62 | const char EXP_CHARS[] = "eE"; | |
63 | const char FLT_CHARS[] = "rRsSfFdDxXpP"; | |
64 | ||
65 | ||
43cd72b9 BW |
66 | /* Flags to indicate whether the hardware supports the density and |
67 | absolute literals options. */ | |
e0001a05 | 68 | |
e0001a05 | 69 | bfd_boolean density_supported = XCHAL_HAVE_DENSITY; |
43cd72b9 BW |
70 | bfd_boolean absolute_literals_supported = XSHAL_USE_ABSOLUTE_LITERALS; |
71 | ||
72 | /* Maximum width we would pad an unreachable frag to get alignment. */ | |
73 | #define UNREACHABLE_MAX_WIDTH 8 | |
e0001a05 | 74 | |
43cd72b9 BW |
75 | static vliw_insn cur_vinsn; |
76 | ||
d77b99c9 | 77 | unsigned xtensa_fetch_width = XCHAL_INST_FETCH_WIDTH; |
43cd72b9 BW |
78 | |
79 | static enum debug_info_type xt_saved_debug_type = DEBUG_NONE; | |
80 | ||
81 | /* Some functions are only valid in the front end. This variable | |
c138bc38 | 82 | allows us to assert that we haven't crossed over into the |
43cd72b9 BW |
83 | back end. */ |
84 | static bfd_boolean past_xtensa_end = FALSE; | |
e0001a05 NC |
85 | |
86 | /* Flags for properties of the last instruction in a segment. */ | |
87 | #define FLAG_IS_A0_WRITER 0x1 | |
88 | #define FLAG_IS_BAD_LOOPEND 0x2 | |
89 | ||
90 | ||
91 | /* We define a special segment names ".literal" to place literals | |
92 | into. The .fini and .init sections are special because they | |
93 | contain code that is moved together by the linker. We give them | |
94 | their own special .fini.literal and .init.literal sections. */ | |
95 | ||
96 | #define LITERAL_SECTION_NAME xtensa_section_rename (".literal") | |
43cd72b9 | 97 | #define LIT4_SECTION_NAME xtensa_section_rename (".lit4") |
e0001a05 NC |
98 | #define FINI_SECTION_NAME xtensa_section_rename (".fini") |
99 | #define INIT_SECTION_NAME xtensa_section_rename (".init") | |
100 | #define FINI_LITERAL_SECTION_NAME xtensa_section_rename (".fini.literal") | |
101 | #define INIT_LITERAL_SECTION_NAME xtensa_section_rename (".init.literal") | |
102 | ||
103 | ||
43cd72b9 | 104 | /* This type is used for the directive_stack to keep track of the |
e0001a05 NC |
105 | state of the literal collection pools. */ |
106 | ||
107 | typedef struct lit_state_struct | |
108 | { | |
109 | const char *lit_seg_name; | |
43cd72b9 | 110 | const char *lit4_seg_name; |
e0001a05 NC |
111 | const char *init_lit_seg_name; |
112 | const char *fini_lit_seg_name; | |
113 | segT lit_seg; | |
43cd72b9 | 114 | segT lit4_seg; |
e0001a05 NC |
115 | segT init_lit_seg; |
116 | segT fini_lit_seg; | |
117 | } lit_state; | |
118 | ||
119 | static lit_state default_lit_sections; | |
120 | ||
121 | ||
122 | /* We keep lists of literal segments. The seg_list type is the node | |
123 | for such a list. The *_literal_head locals are the heads of the | |
124 | various lists. All of these lists have a dummy node at the start. */ | |
125 | ||
126 | typedef struct seg_list_struct | |
127 | { | |
128 | struct seg_list_struct *next; | |
129 | segT seg; | |
130 | } seg_list; | |
131 | ||
132 | static seg_list literal_head_h; | |
133 | static seg_list *literal_head = &literal_head_h; | |
134 | static seg_list init_literal_head_h; | |
135 | static seg_list *init_literal_head = &init_literal_head_h; | |
136 | static seg_list fini_literal_head_h; | |
137 | static seg_list *fini_literal_head = &fini_literal_head_h; | |
138 | ||
139 | ||
82e7541d BW |
140 | /* Lists of symbols. We keep a list of symbols that label the current |
141 | instruction, so that we can adjust the symbols when inserting alignment | |
142 | for various instructions. We also keep a list of all the symbols on | |
143 | literals, so that we can fix up those symbols when the literals are | |
144 | later moved into the text sections. */ | |
145 | ||
146 | typedef struct sym_list_struct | |
147 | { | |
148 | struct sym_list_struct *next; | |
149 | symbolS *sym; | |
150 | } sym_list; | |
151 | ||
152 | static sym_list *insn_labels = NULL; | |
153 | static sym_list *free_insn_labels = NULL; | |
154 | static sym_list *saved_insn_labels = NULL; | |
155 | ||
156 | static sym_list *literal_syms; | |
157 | ||
158 | ||
43cd72b9 BW |
159 | /* Flags to determine whether to prefer const16 or l32r |
160 | if both options are available. */ | |
161 | int prefer_const16 = 0; | |
162 | int prefer_l32r = 0; | |
163 | ||
e0001a05 NC |
164 | /* Global flag to indicate when we are emitting literals. */ |
165 | int generating_literals = 0; | |
166 | ||
43cd72b9 BW |
167 | /* The following PROPERTY table definitions are copied from |
168 | <elf/xtensa.h> and must be kept in sync with the code there. */ | |
169 | ||
170 | /* Flags in the property tables to specify whether blocks of memory | |
171 | are literals, instructions, data, or unreachable. For | |
172 | instructions, blocks that begin loop targets and branch targets are | |
173 | designated. Blocks that do not allow density, instruction | |
174 | reordering or transformation are also specified. Finally, for | |
175 | branch targets, branch target alignment priority is included. | |
176 | Alignment of the next block is specified in the current block | |
177 | and the size of the current block does not include any fill required | |
178 | to align to the next block. */ | |
179 | ||
180 | #define XTENSA_PROP_LITERAL 0x00000001 | |
181 | #define XTENSA_PROP_INSN 0x00000002 | |
182 | #define XTENSA_PROP_DATA 0x00000004 | |
183 | #define XTENSA_PROP_UNREACHABLE 0x00000008 | |
184 | /* Instruction only properties at beginning of code. */ | |
185 | #define XTENSA_PROP_INSN_LOOP_TARGET 0x00000010 | |
186 | #define XTENSA_PROP_INSN_BRANCH_TARGET 0x00000020 | |
187 | /* Instruction only properties about code. */ | |
188 | #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 | |
189 | #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 | |
190 | #define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100 | |
191 | ||
192 | /* Branch target alignment information. This transmits information | |
193 | to the linker optimization about the priority of aligning a | |
194 | particular block for branch target alignment: None, low priority, | |
195 | high priority, or required. These only need to be checked in | |
196 | instruction blocks marked as XTENSA_PROP_INSN_BRANCH_TARGET. | |
197 | Common usage is | |
198 | ||
199 | switch (GET_XTENSA_PROP_BT_ALIGN (flags)) | |
200 | case XTENSA_PROP_BT_ALIGN_NONE: | |
201 | case XTENSA_PROP_BT_ALIGN_LOW: | |
202 | case XTENSA_PROP_BT_ALIGN_HIGH: | |
203 | case XTENSA_PROP_BT_ALIGN_REQUIRE: | |
204 | */ | |
205 | #define XTENSA_PROP_BT_ALIGN_MASK 0x00000600 | |
206 | ||
207 | /* No branch target alignment. */ | |
208 | #define XTENSA_PROP_BT_ALIGN_NONE 0x0 | |
209 | /* Low priority branch target alignment. */ | |
210 | #define XTENSA_PROP_BT_ALIGN_LOW 0x1 | |
211 | /* High priority branch target alignment. */ | |
212 | #define XTENSA_PROP_BT_ALIGN_HIGH 0x2 | |
213 | /* Required branch target alignment. */ | |
214 | #define XTENSA_PROP_BT_ALIGN_REQUIRE 0x3 | |
215 | ||
216 | #define GET_XTENSA_PROP_BT_ALIGN(flag) \ | |
217 | (((unsigned) ((flag) & (XTENSA_PROP_BT_ALIGN_MASK))) >> 9) | |
218 | #define SET_XTENSA_PROP_BT_ALIGN(flag, align) \ | |
219 | (((flag) & (~XTENSA_PROP_BT_ALIGN_MASK)) | \ | |
220 | (((align) << 9) & XTENSA_PROP_BT_ALIGN_MASK)) | |
221 | ||
222 | ||
223 | /* Alignment is specified in the block BEFORE the one that needs | |
224 | alignment. Up to 5 bits. Use GET_XTENSA_PROP_ALIGNMENT(flags) to | |
225 | get the required alignment specified as a power of 2. Use | |
226 | SET_XTENSA_PROP_ALIGNMENT(flags, pow2) to set the required | |
227 | alignment. Be careful of side effects since the SET will evaluate | |
228 | flags twice. Also, note that the SIZE of a block in the property | |
229 | table does not include the alignment size, so the alignment fill | |
230 | must be calculated to determine if two blocks are contiguous. | |
231 | TEXT_ALIGN is not currently implemented but is a placeholder for a | |
232 | possible future implementation. */ | |
233 | ||
234 | #define XTENSA_PROP_ALIGN 0x00000800 | |
235 | ||
236 | #define XTENSA_PROP_ALIGNMENT_MASK 0x0001f000 | |
237 | ||
238 | #define GET_XTENSA_PROP_ALIGNMENT(flag) \ | |
239 | (((unsigned) ((flag) & (XTENSA_PROP_ALIGNMENT_MASK))) >> 12) | |
240 | #define SET_XTENSA_PROP_ALIGNMENT(flag, align) \ | |
241 | (((flag) & (~XTENSA_PROP_ALIGNMENT_MASK)) | \ | |
242 | (((align) << 12) & XTENSA_PROP_ALIGNMENT_MASK)) | |
243 | ||
244 | #define XTENSA_PROP_INSN_ABSLIT 0x00020000 | |
245 | ||
246 | ||
247 | /* Structure for saving instruction and alignment per-fragment data | |
248 | that will be written to the object file. This structure is | |
249 | equivalent to the actual data that will be written out to the file | |
250 | but is easier to use. We provide a conversion to file flags | |
251 | in frag_flags_to_number. */ | |
252 | ||
253 | typedef struct frag_flags_struct frag_flags; | |
254 | ||
255 | struct frag_flags_struct | |
256 | { | |
257 | /* is_literal should only be used after xtensa_move_literals. | |
258 | If you need to check if you are generating a literal fragment, | |
259 | then use the generating_literals global. */ | |
260 | ||
261 | unsigned is_literal : 1; | |
262 | unsigned is_insn : 1; | |
263 | unsigned is_data : 1; | |
264 | unsigned is_unreachable : 1; | |
265 | ||
266 | struct | |
267 | { | |
268 | unsigned is_loop_target : 1; | |
269 | unsigned is_branch_target : 1; /* Branch targets have a priority. */ | |
270 | unsigned bt_align_priority : 2; | |
271 | ||
272 | unsigned is_no_density : 1; | |
273 | /* no_longcalls flag does not need to be placed in the object file. */ | |
274 | /* is_specific_opcode implies no_transform. */ | |
275 | unsigned is_no_transform : 1; | |
276 | ||
277 | unsigned is_no_reorder : 1; | |
278 | ||
279 | /* Uses absolute literal addressing for l32r. */ | |
280 | unsigned is_abslit : 1; | |
281 | } insn; | |
282 | unsigned is_align : 1; | |
283 | unsigned alignment : 5; | |
284 | }; | |
285 | ||
286 | ||
287 | /* Structure for saving information about a block of property data | |
288 | for frags that have the same flags. */ | |
289 | struct xtensa_block_info_struct | |
290 | { | |
291 | segT sec; | |
292 | bfd_vma offset; | |
293 | size_t size; | |
294 | frag_flags flags; | |
295 | struct xtensa_block_info_struct *next; | |
296 | }; | |
297 | ||
e0001a05 NC |
298 | |
299 | /* Structure for saving the current state before emitting literals. */ | |
300 | typedef struct emit_state_struct | |
301 | { | |
302 | const char *name; | |
303 | segT now_seg; | |
304 | subsegT now_subseg; | |
305 | int generating_literals; | |
306 | } emit_state; | |
307 | ||
308 | ||
43cd72b9 BW |
309 | /* Opcode placement information */ |
310 | ||
311 | typedef unsigned long long bitfield; | |
312 | #define bit_is_set(bit, bf) ((bf) & (0x01ll << (bit))) | |
313 | #define set_bit(bit, bf) ((bf) |= (0x01ll << (bit))) | |
314 | #define clear_bit(bit, bf) ((bf) &= ~(0x01ll << (bit))) | |
315 | ||
316 | #define MAX_FORMATS 32 | |
317 | ||
318 | typedef struct op_placement_info_struct | |
319 | { | |
320 | int num_formats; | |
321 | /* A number describing how restrictive the issue is for this | |
322 | opcode. For example, an opcode that fits lots of different | |
c138bc38 | 323 | formats has a high freedom, as does an opcode that fits |
43cd72b9 | 324 | only one format but many slots in that format. The most |
c138bc38 | 325 | restrictive is the opcode that fits only one slot in one |
43cd72b9 BW |
326 | format. */ |
327 | int issuef; | |
43cd72b9 | 328 | xtensa_format narrowest; |
43cd72b9 | 329 | char narrowest_size; |
b2d179be | 330 | char narrowest_slot; |
43cd72b9 BW |
331 | |
332 | /* formats is a bitfield with the Nth bit set | |
333 | if the opcode fits in the Nth xtensa_format. */ | |
334 | bitfield formats; | |
335 | ||
336 | /* slots[N]'s Mth bit is set if the op fits in the | |
337 | Mth slot of the Nth xtensa_format. */ | |
338 | bitfield slots[MAX_FORMATS]; | |
339 | ||
340 | /* A count of the number of slots in a given format | |
341 | an op can fit (i.e., the bitcount of the slot field above). */ | |
342 | char slots_in_format[MAX_FORMATS]; | |
343 | ||
344 | } op_placement_info, *op_placement_info_table; | |
345 | ||
346 | op_placement_info_table op_placement_table; | |
347 | ||
348 | ||
349 | /* Extra expression types. */ | |
350 | ||
351 | #define O_pltrel O_md1 /* like O_symbol but use a PLT reloc */ | |
352 | #define O_hi16 O_md2 /* use high 16 bits of symbolic value */ | |
353 | #define O_lo16 O_md3 /* use low 16 bits of symbolic value */ | |
354 | ||
355 | ||
e0001a05 NC |
356 | /* Directives. */ |
357 | ||
358 | typedef enum | |
359 | { | |
360 | directive_none = 0, | |
361 | directive_literal, | |
362 | directive_density, | |
43cd72b9 | 363 | directive_transform, |
e0001a05 NC |
364 | directive_freeregs, |
365 | directive_longcalls, | |
43cd72b9 BW |
366 | directive_literal_prefix, |
367 | directive_schedule, | |
368 | directive_absolute_literals, | |
369 | directive_last_directive | |
e0001a05 NC |
370 | } directiveE; |
371 | ||
372 | typedef struct | |
373 | { | |
374 | const char *name; | |
375 | bfd_boolean can_be_negated; | |
376 | } directive_infoS; | |
377 | ||
378 | const directive_infoS directive_info[] = | |
379 | { | |
43cd72b9 BW |
380 | { "none", FALSE }, |
381 | { "literal", FALSE }, | |
382 | { "density", TRUE }, | |
383 | { "transform", TRUE }, | |
384 | { "freeregs", FALSE }, | |
385 | { "longcalls", TRUE }, | |
386 | { "literal_prefix", FALSE }, | |
387 | { "schedule", TRUE }, | |
388 | { "absolute-literals", TRUE } | |
e0001a05 NC |
389 | }; |
390 | ||
391 | bfd_boolean directive_state[] = | |
392 | { | |
393 | FALSE, /* none */ | |
394 | FALSE, /* literal */ | |
43cd72b9 | 395 | #if !XCHAL_HAVE_DENSITY |
e0001a05 NC |
396 | FALSE, /* density */ |
397 | #else | |
398 | TRUE, /* density */ | |
399 | #endif | |
43cd72b9 | 400 | TRUE, /* transform */ |
e0001a05 NC |
401 | FALSE, /* freeregs */ |
402 | FALSE, /* longcalls */ | |
43cd72b9 BW |
403 | FALSE, /* literal_prefix */ |
404 | TRUE, /* schedule */ | |
405 | #if XSHAL_USE_ABSOLUTE_LITERALS | |
406 | TRUE /* absolute_literals */ | |
407 | #else | |
408 | FALSE /* absolute_literals */ | |
409 | #endif | |
e0001a05 NC |
410 | }; |
411 | ||
e0001a05 NC |
412 | |
413 | /* Directive functions. */ | |
414 | ||
7fa3d080 BW |
415 | static void xtensa_begin_directive (int); |
416 | static void xtensa_end_directive (int); | |
7fa3d080 BW |
417 | static void xtensa_literal_prefix (char const *, int); |
418 | static void xtensa_literal_position (int); | |
419 | static void xtensa_literal_pseudo (int); | |
420 | static void xtensa_frequency_pseudo (int); | |
421 | static void xtensa_elf_cons (int); | |
e0001a05 | 422 | |
7fa3d080 | 423 | /* Parsing and Idiom Translation. */ |
e0001a05 | 424 | |
7fa3d080 | 425 | static bfd_reloc_code_real_type xtensa_elf_suffix (char **, expressionS *); |
e0001a05 | 426 | |
e0001a05 NC |
427 | /* Various Other Internal Functions. */ |
428 | ||
84b08ed9 BW |
429 | extern bfd_boolean xg_is_single_relaxable_insn (TInsn *, TInsn *, bfd_boolean); |
430 | static bfd_boolean xg_build_to_insn (TInsn *, TInsn *, BuildInstr *); | |
7fa3d080 BW |
431 | static void xtensa_mark_literal_pool_location (void); |
432 | static addressT get_expanded_loop_offset (xtensa_opcode); | |
433 | static fragS *get_literal_pool_location (segT); | |
434 | static void set_literal_pool_location (segT, fragS *); | |
435 | static void xtensa_set_frag_assembly_state (fragS *); | |
436 | static void finish_vinsn (vliw_insn *); | |
437 | static bfd_boolean emit_single_op (TInsn *); | |
34e41783 | 438 | static int total_frag_text_expansion (fragS *); |
e0001a05 NC |
439 | |
440 | /* Alignment Functions. */ | |
441 | ||
d77b99c9 BW |
442 | static int get_text_align_power (unsigned); |
443 | static int get_text_align_max_fill_size (int, bfd_boolean, bfd_boolean); | |
664df4e4 | 444 | static int branch_align_power (segT); |
e0001a05 NC |
445 | |
446 | /* Helpers for xtensa_relax_frag(). */ | |
447 | ||
7fa3d080 | 448 | static long relax_frag_add_nop (fragS *); |
e0001a05 | 449 | |
b08b5071 | 450 | /* Accessors for additional per-subsegment information. */ |
e0001a05 | 451 | |
7fa3d080 BW |
452 | static unsigned get_last_insn_flags (segT, subsegT); |
453 | static void set_last_insn_flags (segT, subsegT, unsigned, bfd_boolean); | |
b08b5071 BW |
454 | static float get_subseg_total_freq (segT, subsegT); |
455 | static float get_subseg_target_freq (segT, subsegT); | |
456 | static void set_subseg_freq (segT, subsegT, float, float); | |
e0001a05 NC |
457 | |
458 | /* Segment list functions. */ | |
459 | ||
7fa3d080 BW |
460 | static void xtensa_move_literals (void); |
461 | static void xtensa_reorder_segments (void); | |
462 | static void xtensa_switch_to_literal_fragment (emit_state *); | |
463 | static void xtensa_switch_to_non_abs_literal_fragment (emit_state *); | |
464 | static void xtensa_switch_section_emit_state (emit_state *, segT, subsegT); | |
465 | static void xtensa_restore_emit_state (emit_state *); | |
e0001a05 | 466 | static void cache_literal_section |
7fa3d080 | 467 | (seg_list *, const char *, segT *, bfd_boolean); |
e0001a05 | 468 | |
e0001a05 | 469 | /* Import from elf32-xtensa.c in BFD library. */ |
43cd72b9 | 470 | |
7fa3d080 | 471 | extern char *xtensa_get_property_section_name (asection *, const char *); |
e0001a05 | 472 | |
43cd72b9 BW |
473 | /* op_placement_info functions. */ |
474 | ||
7fa3d080 BW |
475 | static void init_op_placement_info_table (void); |
476 | extern bfd_boolean opcode_fits_format_slot (xtensa_opcode, xtensa_format, int); | |
477 | static int xg_get_single_size (xtensa_opcode); | |
478 | static xtensa_format xg_get_single_format (xtensa_opcode); | |
b2d179be | 479 | static int xg_get_single_slot (xtensa_opcode); |
43cd72b9 | 480 | |
e0001a05 | 481 | /* TInsn and IStack functions. */ |
43cd72b9 | 482 | |
7fa3d080 BW |
483 | static bfd_boolean tinsn_has_symbolic_operands (const TInsn *); |
484 | static bfd_boolean tinsn_has_invalid_symbolic_operands (const TInsn *); | |
485 | static bfd_boolean tinsn_has_complex_operands (const TInsn *); | |
486 | static bfd_boolean tinsn_to_insnbuf (TInsn *, xtensa_insnbuf); | |
487 | static bfd_boolean tinsn_check_arguments (const TInsn *); | |
488 | static void tinsn_from_chars (TInsn *, char *, int); | |
489 | static void tinsn_immed_from_frag (TInsn *, fragS *, int); | |
490 | static int get_num_stack_text_bytes (IStack *); | |
491 | static int get_num_stack_literal_bytes (IStack *); | |
e0001a05 | 492 | |
43cd72b9 BW |
493 | /* vliw_insn functions. */ |
494 | ||
7fa3d080 BW |
495 | static void xg_init_vinsn (vliw_insn *); |
496 | static void xg_clear_vinsn (vliw_insn *); | |
497 | static bfd_boolean vinsn_has_specific_opcodes (vliw_insn *); | |
498 | static void xg_free_vinsn (vliw_insn *); | |
43cd72b9 | 499 | static bfd_boolean vinsn_to_insnbuf |
7fa3d080 BW |
500 | (vliw_insn *, char *, fragS *, bfd_boolean); |
501 | static void vinsn_from_chars (vliw_insn *, char *); | |
43cd72b9 | 502 | |
e0001a05 | 503 | /* Expression Utilities. */ |
43cd72b9 | 504 | |
7fa3d080 BW |
505 | bfd_boolean expr_is_const (const expressionS *); |
506 | offsetT get_expr_const (const expressionS *); | |
507 | void set_expr_const (expressionS *, offsetT); | |
508 | bfd_boolean expr_is_register (const expressionS *); | |
509 | offsetT get_expr_register (const expressionS *); | |
510 | void set_expr_symbol_offset (expressionS *, symbolS *, offsetT); | |
7fa3d080 BW |
511 | bfd_boolean expr_is_equal (expressionS *, expressionS *); |
512 | static void copy_expr (expressionS *, const expressionS *); | |
e0001a05 | 513 | |
9456465c BW |
514 | /* Section renaming. */ |
515 | ||
7fa3d080 | 516 | static void build_section_rename (const char *); |
e0001a05 | 517 | |
e0001a05 NC |
518 | |
519 | /* ISA imported from bfd. */ | |
520 | extern xtensa_isa xtensa_default_isa; | |
521 | ||
522 | extern int target_big_endian; | |
523 | ||
524 | static xtensa_opcode xtensa_addi_opcode; | |
525 | static xtensa_opcode xtensa_addmi_opcode; | |
526 | static xtensa_opcode xtensa_call0_opcode; | |
527 | static xtensa_opcode xtensa_call4_opcode; | |
528 | static xtensa_opcode xtensa_call8_opcode; | |
529 | static xtensa_opcode xtensa_call12_opcode; | |
530 | static xtensa_opcode xtensa_callx0_opcode; | |
531 | static xtensa_opcode xtensa_callx4_opcode; | |
532 | static xtensa_opcode xtensa_callx8_opcode; | |
533 | static xtensa_opcode xtensa_callx12_opcode; | |
43cd72b9 | 534 | static xtensa_opcode xtensa_const16_opcode; |
e0001a05 | 535 | static xtensa_opcode xtensa_entry_opcode; |
43cd72b9 BW |
536 | static xtensa_opcode xtensa_movi_opcode; |
537 | static xtensa_opcode xtensa_movi_n_opcode; | |
e0001a05 | 538 | static xtensa_opcode xtensa_isync_opcode; |
e0001a05 | 539 | static xtensa_opcode xtensa_jx_opcode; |
43cd72b9 | 540 | static xtensa_opcode xtensa_l32r_opcode; |
e0001a05 NC |
541 | static xtensa_opcode xtensa_loop_opcode; |
542 | static xtensa_opcode xtensa_loopnez_opcode; | |
543 | static xtensa_opcode xtensa_loopgtz_opcode; | |
43cd72b9 | 544 | static xtensa_opcode xtensa_nop_opcode; |
e0001a05 NC |
545 | static xtensa_opcode xtensa_nop_n_opcode; |
546 | static xtensa_opcode xtensa_or_opcode; | |
547 | static xtensa_opcode xtensa_ret_opcode; | |
548 | static xtensa_opcode xtensa_ret_n_opcode; | |
549 | static xtensa_opcode xtensa_retw_opcode; | |
550 | static xtensa_opcode xtensa_retw_n_opcode; | |
43cd72b9 | 551 | static xtensa_opcode xtensa_rsr_lcount_opcode; |
e0001a05 NC |
552 | static xtensa_opcode xtensa_waiti_opcode; |
553 | ||
554 | \f | |
555 | /* Command-line Options. */ | |
556 | ||
557 | bfd_boolean use_literal_section = TRUE; | |
558 | static bfd_boolean align_targets = TRUE; | |
43cd72b9 | 559 | static bfd_boolean warn_unaligned_branch_targets = FALSE; |
e0001a05 | 560 | static bfd_boolean has_a0_b_retw = FALSE; |
43cd72b9 BW |
561 | static bfd_boolean workaround_a0_b_retw = FALSE; |
562 | static bfd_boolean workaround_b_j_loop_end = FALSE; | |
563 | static bfd_boolean workaround_short_loop = FALSE; | |
e0001a05 | 564 | static bfd_boolean maybe_has_short_loop = FALSE; |
43cd72b9 | 565 | static bfd_boolean workaround_close_loop_end = FALSE; |
e0001a05 | 566 | static bfd_boolean maybe_has_close_loop_end = FALSE; |
03aaa593 | 567 | static bfd_boolean enforce_three_byte_loop_align = FALSE; |
e0001a05 | 568 | |
43cd72b9 BW |
569 | /* When workaround_short_loops is TRUE, all loops with early exits must |
570 | have at least 3 instructions. workaround_all_short_loops is a modifier | |
571 | to the workaround_short_loop flag. In addition to the | |
572 | workaround_short_loop actions, all straightline loopgtz and loopnez | |
573 | must have at least 3 instructions. */ | |
e0001a05 | 574 | |
43cd72b9 | 575 | static bfd_boolean workaround_all_short_loops = FALSE; |
e0001a05 | 576 | |
7fa3d080 BW |
577 | |
578 | static void | |
579 | xtensa_setup_hw_workarounds (int earliest, int latest) | |
580 | { | |
581 | if (earliest > latest) | |
582 | as_fatal (_("illegal range of target hardware versions")); | |
583 | ||
584 | /* Enable all workarounds for pre-T1050.0 hardware. */ | |
585 | if (earliest < 105000 || latest < 105000) | |
586 | { | |
587 | workaround_a0_b_retw |= TRUE; | |
588 | workaround_b_j_loop_end |= TRUE; | |
589 | workaround_short_loop |= TRUE; | |
590 | workaround_close_loop_end |= TRUE; | |
591 | workaround_all_short_loops |= TRUE; | |
03aaa593 | 592 | enforce_three_byte_loop_align = TRUE; |
7fa3d080 BW |
593 | } |
594 | } | |
595 | ||
596 | ||
e0001a05 NC |
597 | enum |
598 | { | |
599 | option_density = OPTION_MD_BASE, | |
600 | option_no_density, | |
601 | ||
602 | option_relax, | |
603 | option_no_relax, | |
604 | ||
43cd72b9 BW |
605 | option_link_relax, |
606 | option_no_link_relax, | |
607 | ||
e0001a05 NC |
608 | option_generics, |
609 | option_no_generics, | |
610 | ||
43cd72b9 BW |
611 | option_transform, |
612 | option_no_transform, | |
613 | ||
e0001a05 NC |
614 | option_text_section_literals, |
615 | option_no_text_section_literals, | |
616 | ||
43cd72b9 BW |
617 | option_absolute_literals, |
618 | option_no_absolute_literals, | |
619 | ||
e0001a05 NC |
620 | option_align_targets, |
621 | option_no_align_targets, | |
622 | ||
43cd72b9 | 623 | option_warn_unaligned_targets, |
e0001a05 NC |
624 | |
625 | option_longcalls, | |
626 | option_no_longcalls, | |
627 | ||
628 | option_workaround_a0_b_retw, | |
629 | option_no_workaround_a0_b_retw, | |
630 | ||
631 | option_workaround_b_j_loop_end, | |
632 | option_no_workaround_b_j_loop_end, | |
633 | ||
634 | option_workaround_short_loop, | |
635 | option_no_workaround_short_loop, | |
636 | ||
637 | option_workaround_all_short_loops, | |
638 | option_no_workaround_all_short_loops, | |
639 | ||
640 | option_workaround_close_loop_end, | |
641 | option_no_workaround_close_loop_end, | |
642 | ||
643 | option_no_workarounds, | |
644 | ||
e0001a05 | 645 | option_rename_section_name, |
e0001a05 | 646 | |
43cd72b9 BW |
647 | option_prefer_l32r, |
648 | option_prefer_const16, | |
649 | ||
650 | option_target_hardware | |
e0001a05 NC |
651 | }; |
652 | ||
653 | const char *md_shortopts = ""; | |
654 | ||
655 | struct option md_longopts[] = | |
656 | { | |
43cd72b9 BW |
657 | { "density", no_argument, NULL, option_density }, |
658 | { "no-density", no_argument, NULL, option_no_density }, | |
659 | ||
660 | /* Both "relax" and "generics" are deprecated and treated as equivalent | |
661 | to the "transform" option. */ | |
662 | { "relax", no_argument, NULL, option_relax }, | |
663 | { "no-relax", no_argument, NULL, option_no_relax }, | |
664 | { "generics", no_argument, NULL, option_generics }, | |
665 | { "no-generics", no_argument, NULL, option_no_generics }, | |
666 | ||
667 | { "transform", no_argument, NULL, option_transform }, | |
668 | { "no-transform", no_argument, NULL, option_no_transform }, | |
669 | { "text-section-literals", no_argument, NULL, option_text_section_literals }, | |
670 | { "no-text-section-literals", no_argument, NULL, | |
671 | option_no_text_section_literals }, | |
672 | { "absolute-literals", no_argument, NULL, option_absolute_literals }, | |
673 | { "no-absolute-literals", no_argument, NULL, option_no_absolute_literals }, | |
e0001a05 NC |
674 | /* This option was changed from -align-target to -target-align |
675 | because it conflicted with the "-al" option. */ | |
43cd72b9 | 676 | { "target-align", no_argument, NULL, option_align_targets }, |
7fa3d080 BW |
677 | { "no-target-align", no_argument, NULL, option_no_align_targets }, |
678 | { "warn-unaligned-targets", no_argument, NULL, | |
679 | option_warn_unaligned_targets }, | |
43cd72b9 BW |
680 | { "longcalls", no_argument, NULL, option_longcalls }, |
681 | { "no-longcalls", no_argument, NULL, option_no_longcalls }, | |
682 | ||
683 | { "no-workaround-a0-b-retw", no_argument, NULL, | |
684 | option_no_workaround_a0_b_retw }, | |
685 | { "workaround-a0-b-retw", no_argument, NULL, option_workaround_a0_b_retw }, | |
e0001a05 | 686 | |
43cd72b9 BW |
687 | { "no-workaround-b-j-loop-end", no_argument, NULL, |
688 | option_no_workaround_b_j_loop_end }, | |
689 | { "workaround-b-j-loop-end", no_argument, NULL, | |
690 | option_workaround_b_j_loop_end }, | |
e0001a05 | 691 | |
43cd72b9 BW |
692 | { "no-workaround-short-loops", no_argument, NULL, |
693 | option_no_workaround_short_loop }, | |
7fa3d080 BW |
694 | { "workaround-short-loops", no_argument, NULL, |
695 | option_workaround_short_loop }, | |
e0001a05 | 696 | |
43cd72b9 BW |
697 | { "no-workaround-all-short-loops", no_argument, NULL, |
698 | option_no_workaround_all_short_loops }, | |
699 | { "workaround-all-short-loop", no_argument, NULL, | |
700 | option_workaround_all_short_loops }, | |
701 | ||
702 | { "prefer-l32r", no_argument, NULL, option_prefer_l32r }, | |
703 | { "prefer-const16", no_argument, NULL, option_prefer_const16 }, | |
704 | ||
705 | { "no-workarounds", no_argument, NULL, option_no_workarounds }, | |
706 | ||
707 | { "no-workaround-close-loop-end", no_argument, NULL, | |
708 | option_no_workaround_close_loop_end }, | |
709 | { "workaround-close-loop-end", no_argument, NULL, | |
710 | option_workaround_close_loop_end }, | |
e0001a05 | 711 | |
7fa3d080 | 712 | { "rename-section", required_argument, NULL, option_rename_section_name }, |
e0001a05 | 713 | |
43cd72b9 BW |
714 | { "link-relax", no_argument, NULL, option_link_relax }, |
715 | { "no-link-relax", no_argument, NULL, option_no_link_relax }, | |
716 | ||
717 | { "target-hardware", required_argument, NULL, option_target_hardware }, | |
718 | ||
719 | { NULL, no_argument, NULL, 0 } | |
e0001a05 NC |
720 | }; |
721 | ||
722 | size_t md_longopts_size = sizeof md_longopts; | |
723 | ||
724 | ||
725 | int | |
7fa3d080 | 726 | md_parse_option (int c, char *arg) |
e0001a05 NC |
727 | { |
728 | switch (c) | |
729 | { | |
730 | case option_density: | |
43cd72b9 | 731 | as_warn (_("--density option is ignored")); |
e0001a05 NC |
732 | return 1; |
733 | case option_no_density: | |
43cd72b9 | 734 | as_warn (_("--no-density option is ignored")); |
e0001a05 | 735 | return 1; |
43cd72b9 BW |
736 | case option_link_relax: |
737 | linkrelax = 1; | |
e0001a05 | 738 | return 1; |
43cd72b9 BW |
739 | case option_no_link_relax: |
740 | linkrelax = 0; | |
e0001a05 | 741 | return 1; |
43cd72b9 BW |
742 | case option_generics: |
743 | as_warn (_("--generics is deprecated; use --transform instead")); | |
744 | return md_parse_option (option_transform, arg); | |
745 | case option_no_generics: | |
746 | as_warn (_("--no-generics is deprecated; use --no-transform instead")); | |
747 | return md_parse_option (option_no_transform, arg); | |
748 | case option_relax: | |
749 | as_warn (_("--relax is deprecated; use --transform instead")); | |
750 | return md_parse_option (option_transform, arg); | |
751 | case option_no_relax: | |
752 | as_warn (_("--no-relax is deprecated; use --no-transform instead")); | |
753 | return md_parse_option (option_no_transform, arg); | |
e0001a05 NC |
754 | case option_longcalls: |
755 | directive_state[directive_longcalls] = TRUE; | |
756 | return 1; | |
757 | case option_no_longcalls: | |
758 | directive_state[directive_longcalls] = FALSE; | |
759 | return 1; | |
760 | case option_text_section_literals: | |
761 | use_literal_section = FALSE; | |
762 | return 1; | |
763 | case option_no_text_section_literals: | |
764 | use_literal_section = TRUE; | |
765 | return 1; | |
43cd72b9 BW |
766 | case option_absolute_literals: |
767 | if (!absolute_literals_supported) | |
768 | { | |
769 | as_fatal (_("--absolute-literals option not supported in this Xtensa configuration")); | |
770 | return 0; | |
771 | } | |
772 | directive_state[directive_absolute_literals] = TRUE; | |
773 | return 1; | |
774 | case option_no_absolute_literals: | |
775 | directive_state[directive_absolute_literals] = FALSE; | |
776 | return 1; | |
777 | ||
e0001a05 NC |
778 | case option_workaround_a0_b_retw: |
779 | workaround_a0_b_retw = TRUE; | |
e0001a05 NC |
780 | return 1; |
781 | case option_no_workaround_a0_b_retw: | |
782 | workaround_a0_b_retw = FALSE; | |
e0001a05 NC |
783 | return 1; |
784 | case option_workaround_b_j_loop_end: | |
785 | workaround_b_j_loop_end = TRUE; | |
e0001a05 NC |
786 | return 1; |
787 | case option_no_workaround_b_j_loop_end: | |
788 | workaround_b_j_loop_end = FALSE; | |
e0001a05 NC |
789 | return 1; |
790 | ||
791 | case option_workaround_short_loop: | |
792 | workaround_short_loop = TRUE; | |
e0001a05 NC |
793 | return 1; |
794 | case option_no_workaround_short_loop: | |
795 | workaround_short_loop = FALSE; | |
e0001a05 NC |
796 | return 1; |
797 | ||
798 | case option_workaround_all_short_loops: | |
799 | workaround_all_short_loops = TRUE; | |
e0001a05 NC |
800 | return 1; |
801 | case option_no_workaround_all_short_loops: | |
802 | workaround_all_short_loops = FALSE; | |
e0001a05 NC |
803 | return 1; |
804 | ||
805 | case option_workaround_close_loop_end: | |
806 | workaround_close_loop_end = TRUE; | |
e0001a05 NC |
807 | return 1; |
808 | case option_no_workaround_close_loop_end: | |
809 | workaround_close_loop_end = FALSE; | |
e0001a05 NC |
810 | return 1; |
811 | ||
812 | case option_no_workarounds: | |
813 | workaround_a0_b_retw = FALSE; | |
e0001a05 | 814 | workaround_b_j_loop_end = FALSE; |
e0001a05 | 815 | workaround_short_loop = FALSE; |
e0001a05 | 816 | workaround_all_short_loops = FALSE; |
e0001a05 | 817 | workaround_close_loop_end = FALSE; |
e0001a05 | 818 | return 1; |
43cd72b9 | 819 | |
e0001a05 NC |
820 | case option_align_targets: |
821 | align_targets = TRUE; | |
822 | return 1; | |
823 | case option_no_align_targets: | |
824 | align_targets = FALSE; | |
825 | return 1; | |
826 | ||
43cd72b9 BW |
827 | case option_warn_unaligned_targets: |
828 | warn_unaligned_branch_targets = TRUE; | |
e0001a05 NC |
829 | return 1; |
830 | ||
e0001a05 NC |
831 | case option_rename_section_name: |
832 | build_section_rename (arg); | |
833 | return 1; | |
e0001a05 NC |
834 | |
835 | case 'Q': | |
836 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section | |
837 | should be emitted or not. FIXME: Not implemented. */ | |
838 | return 1; | |
c138bc38 | 839 | |
43cd72b9 BW |
840 | case option_prefer_l32r: |
841 | if (prefer_const16) | |
842 | as_fatal (_("prefer-l32r conflicts with prefer-const16")); | |
843 | prefer_l32r = 1; | |
844 | return 1; | |
845 | ||
846 | case option_prefer_const16: | |
847 | if (prefer_l32r) | |
848 | as_fatal (_("prefer-const16 conflicts with prefer-l32r")); | |
849 | prefer_const16 = 1; | |
850 | return 1; | |
851 | ||
c138bc38 | 852 | case option_target_hardware: |
43cd72b9 BW |
853 | { |
854 | int earliest, latest = 0; | |
855 | if (*arg == 0 || *arg == '-') | |
856 | as_fatal (_("invalid target hardware version")); | |
857 | ||
858 | earliest = strtol (arg, &arg, 0); | |
859 | ||
860 | if (*arg == 0) | |
861 | latest = earliest; | |
862 | else if (*arg == '-') | |
863 | { | |
864 | if (*++arg == 0) | |
865 | as_fatal (_("invalid target hardware version")); | |
866 | latest = strtol (arg, &arg, 0); | |
867 | } | |
868 | if (*arg != 0) | |
869 | as_fatal (_("invalid target hardware version")); | |
870 | ||
871 | xtensa_setup_hw_workarounds (earliest, latest); | |
872 | return 1; | |
873 | } | |
874 | ||
875 | case option_transform: | |
876 | /* This option has no affect other than to use the defaults, | |
877 | which are already set. */ | |
878 | return 1; | |
879 | ||
880 | case option_no_transform: | |
881 | /* This option turns off all transformations of any kind. | |
882 | However, because we want to preserve the state of other | |
883 | directives, we only change its own field. Thus, before | |
884 | you perform any transformation, always check if transform | |
885 | is available. If you use the functions we provide for this | |
886 | purpose, you will be ok. */ | |
887 | directive_state[directive_transform] = FALSE; | |
888 | return 1; | |
889 | ||
e0001a05 NC |
890 | default: |
891 | return 0; | |
892 | } | |
893 | } | |
894 | ||
895 | ||
896 | void | |
7fa3d080 | 897 | md_show_usage (FILE *stream) |
e0001a05 | 898 | { |
43cd72b9 BW |
899 | fputs ("\n\ |
900 | Xtensa options:\n\ | |
9456465c BW |
901 | --[no-]text-section-literals\n\ |
902 | [Do not] put literals in the text section\n\ | |
903 | --[no-]absolute-literals\n\ | |
904 | [Do not] default to use non-PC-relative literals\n\ | |
905 | --[no-]target-align [Do not] try to align branch targets\n\ | |
906 | --[no-]longcalls [Do not] emit 32-bit call sequences\n\ | |
907 | --[no-]transform [Do not] transform instructions\n\ | |
908 | --rename-section old=new Rename section 'old' to 'new'\n", stream); | |
e0001a05 NC |
909 | } |
910 | ||
7fa3d080 BW |
911 | \f |
912 | /* Functions related to the list of current label symbols. */ | |
43cd72b9 BW |
913 | |
914 | static void | |
7fa3d080 | 915 | xtensa_add_insn_label (symbolS *sym) |
43cd72b9 | 916 | { |
7fa3d080 | 917 | sym_list *l; |
43cd72b9 | 918 | |
7fa3d080 BW |
919 | if (!free_insn_labels) |
920 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
921 | else | |
43cd72b9 | 922 | { |
7fa3d080 BW |
923 | l = free_insn_labels; |
924 | free_insn_labels = l->next; | |
925 | } | |
926 | ||
927 | l->sym = sym; | |
928 | l->next = insn_labels; | |
929 | insn_labels = l; | |
930 | } | |
931 | ||
932 | ||
933 | static void | |
934 | xtensa_clear_insn_labels (void) | |
935 | { | |
936 | sym_list **pl; | |
937 | ||
938 | for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next) | |
939 | ; | |
940 | *pl = insn_labels; | |
941 | insn_labels = NULL; | |
942 | } | |
943 | ||
944 | ||
c138bc38 BW |
945 | /* The "loops_ok" argument is provided to allow ignoring labels that |
946 | define loop ends. This fixes a bug where the NOPs to align a | |
7fa3d080 BW |
947 | loop opcode were included in a previous zero-cost loop: |
948 | ||
949 | loop a0, loopend | |
950 | <loop1 body> | |
951 | loopend: | |
952 | ||
953 | loop a2, loopend2 | |
954 | <loop2 body> | |
955 | ||
956 | would become: | |
957 | ||
958 | loop a0, loopend | |
959 | <loop1 body> | |
960 | nop.n <===== bad! | |
961 | loopend: | |
962 | ||
963 | loop a2, loopend2 | |
964 | <loop2 body> | |
965 | ||
966 | This argument is used to prevent moving the NOP to before the | |
967 | loop-end label, which is what you want in this special case. */ | |
968 | ||
969 | static void | |
970 | xtensa_move_labels (fragS *new_frag, valueT new_offset, bfd_boolean loops_ok) | |
971 | { | |
972 | sym_list *lit; | |
973 | ||
974 | for (lit = insn_labels; lit; lit = lit->next) | |
975 | { | |
976 | symbolS *lit_sym = lit->sym; | |
977 | if (loops_ok || ! symbol_get_tc (lit_sym)->is_loop_target) | |
978 | { | |
979 | S_SET_VALUE (lit_sym, new_offset); | |
980 | symbol_set_frag (lit_sym, new_frag); | |
981 | } | |
43cd72b9 BW |
982 | } |
983 | } | |
984 | ||
e0001a05 NC |
985 | \f |
986 | /* Directive data and functions. */ | |
987 | ||
988 | typedef struct state_stackS_struct | |
989 | { | |
990 | directiveE directive; | |
991 | bfd_boolean negated; | |
992 | bfd_boolean old_state; | |
993 | const char *file; | |
994 | unsigned int line; | |
995 | const void *datum; | |
996 | struct state_stackS_struct *prev; | |
997 | } state_stackS; | |
998 | ||
999 | state_stackS *directive_state_stack; | |
1000 | ||
1001 | const pseudo_typeS md_pseudo_table[] = | |
1002 | { | |
43cd72b9 BW |
1003 | { "align", s_align_bytes, 0 }, /* Defaulting is invalid (0). */ |
1004 | { "literal_position", xtensa_literal_position, 0 }, | |
1005 | { "frame", s_ignore, 0 }, /* Formerly used for STABS debugging. */ | |
1006 | { "long", xtensa_elf_cons, 4 }, | |
1007 | { "word", xtensa_elf_cons, 4 }, | |
1008 | { "short", xtensa_elf_cons, 2 }, | |
1009 | { "begin", xtensa_begin_directive, 0 }, | |
1010 | { "end", xtensa_end_directive, 0 }, | |
43cd72b9 BW |
1011 | { "literal", xtensa_literal_pseudo, 0 }, |
1012 | { "frequency", xtensa_frequency_pseudo, 0 }, | |
1013 | { NULL, 0, 0 }, | |
e0001a05 NC |
1014 | }; |
1015 | ||
1016 | ||
7fa3d080 BW |
1017 | static bfd_boolean |
1018 | use_transform (void) | |
e0001a05 | 1019 | { |
43cd72b9 BW |
1020 | /* After md_end, you should be checking frag by frag, rather |
1021 | than state directives. */ | |
1022 | assert (!past_xtensa_end); | |
1023 | return directive_state[directive_transform]; | |
e0001a05 NC |
1024 | } |
1025 | ||
1026 | ||
7fa3d080 BW |
1027 | static bfd_boolean |
1028 | do_align_targets (void) | |
e0001a05 | 1029 | { |
7b1cc377 BW |
1030 | /* Do not use this function after md_end; just look at align_targets |
1031 | instead. There is no target-align directive, so alignment is either | |
1032 | enabled for all frags or not done at all. */ | |
43cd72b9 BW |
1033 | assert (!past_xtensa_end); |
1034 | return align_targets && use_transform (); | |
e0001a05 NC |
1035 | } |
1036 | ||
1037 | ||
1038 | static void | |
7fa3d080 | 1039 | directive_push (directiveE directive, bfd_boolean negated, const void *datum) |
e0001a05 NC |
1040 | { |
1041 | char *file; | |
1042 | unsigned int line; | |
1043 | state_stackS *stack = (state_stackS *) xmalloc (sizeof (state_stackS)); | |
1044 | ||
1045 | as_where (&file, &line); | |
1046 | ||
1047 | stack->directive = directive; | |
1048 | stack->negated = negated; | |
1049 | stack->old_state = directive_state[directive]; | |
1050 | stack->file = file; | |
1051 | stack->line = line; | |
1052 | stack->datum = datum; | |
1053 | stack->prev = directive_state_stack; | |
1054 | directive_state_stack = stack; | |
1055 | ||
1056 | directive_state[directive] = !negated; | |
1057 | } | |
1058 | ||
7fa3d080 | 1059 | |
e0001a05 | 1060 | static void |
7fa3d080 BW |
1061 | directive_pop (directiveE *directive, |
1062 | bfd_boolean *negated, | |
1063 | const char **file, | |
1064 | unsigned int *line, | |
1065 | const void **datum) | |
e0001a05 NC |
1066 | { |
1067 | state_stackS *top = directive_state_stack; | |
1068 | ||
1069 | if (!directive_state_stack) | |
1070 | { | |
1071 | as_bad (_("unmatched end directive")); | |
1072 | *directive = directive_none; | |
1073 | return; | |
1074 | } | |
1075 | ||
1076 | directive_state[directive_state_stack->directive] = top->old_state; | |
1077 | *directive = top->directive; | |
1078 | *negated = top->negated; | |
1079 | *file = top->file; | |
1080 | *line = top->line; | |
1081 | *datum = top->datum; | |
1082 | directive_state_stack = top->prev; | |
1083 | free (top); | |
1084 | } | |
1085 | ||
1086 | ||
1087 | static void | |
7fa3d080 | 1088 | directive_balance (void) |
e0001a05 NC |
1089 | { |
1090 | while (directive_state_stack) | |
1091 | { | |
1092 | directiveE directive; | |
1093 | bfd_boolean negated; | |
1094 | const char *file; | |
1095 | unsigned int line; | |
1096 | const void *datum; | |
1097 | ||
1098 | directive_pop (&directive, &negated, &file, &line, &datum); | |
1099 | as_warn_where ((char *) file, line, | |
1100 | _(".begin directive with no matching .end directive")); | |
1101 | } | |
1102 | } | |
1103 | ||
1104 | ||
1105 | static bfd_boolean | |
7fa3d080 | 1106 | inside_directive (directiveE dir) |
e0001a05 NC |
1107 | { |
1108 | state_stackS *top = directive_state_stack; | |
1109 | ||
1110 | while (top && top->directive != dir) | |
1111 | top = top->prev; | |
1112 | ||
1113 | return (top != NULL); | |
1114 | } | |
1115 | ||
1116 | ||
1117 | static void | |
7fa3d080 | 1118 | get_directive (directiveE *directive, bfd_boolean *negated) |
e0001a05 NC |
1119 | { |
1120 | int len; | |
1121 | unsigned i; | |
43cd72b9 | 1122 | char *directive_string; |
e0001a05 NC |
1123 | |
1124 | if (strncmp (input_line_pointer, "no-", 3) != 0) | |
1125 | *negated = FALSE; | |
1126 | else | |
1127 | { | |
1128 | *negated = TRUE; | |
1129 | input_line_pointer += 3; | |
1130 | } | |
1131 | ||
1132 | len = strspn (input_line_pointer, | |
43cd72b9 BW |
1133 | "abcdefghijklmnopqrstuvwxyz_-/0123456789."); |
1134 | ||
1135 | /* This code is a hack to make .begin [no-][generics|relax] exactly | |
1136 | equivalent to .begin [no-]transform. We should remove it when | |
1137 | we stop accepting those options. */ | |
c138bc38 | 1138 | |
43cd72b9 BW |
1139 | if (strncmp (input_line_pointer, "generics", strlen ("generics")) == 0) |
1140 | { | |
1141 | as_warn (_("[no-]generics is deprecated; use [no-]transform instead")); | |
1142 | directive_string = "transform"; | |
1143 | } | |
1144 | else if (strncmp (input_line_pointer, "relax", strlen ("relax")) == 0) | |
1145 | { | |
1146 | as_warn (_("[no-]relax is deprecated; use [no-]transform instead")); | |
1147 | directive_string = "transform"; | |
c138bc38 | 1148 | } |
43cd72b9 BW |
1149 | else |
1150 | directive_string = input_line_pointer; | |
e0001a05 NC |
1151 | |
1152 | for (i = 0; i < sizeof (directive_info) / sizeof (*directive_info); ++i) | |
1153 | { | |
43cd72b9 | 1154 | if (strncmp (directive_string, directive_info[i].name, len) == 0) |
e0001a05 NC |
1155 | { |
1156 | input_line_pointer += len; | |
1157 | *directive = (directiveE) i; | |
1158 | if (*negated && !directive_info[i].can_be_negated) | |
43cd72b9 | 1159 | as_bad (_("directive %s cannot be negated"), |
e0001a05 NC |
1160 | directive_info[i].name); |
1161 | return; | |
1162 | } | |
1163 | } | |
1164 | ||
1165 | as_bad (_("unknown directive")); | |
1166 | *directive = (directiveE) XTENSA_UNDEFINED; | |
1167 | } | |
1168 | ||
1169 | ||
1170 | static void | |
7fa3d080 | 1171 | xtensa_begin_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1172 | { |
1173 | directiveE directive; | |
1174 | bfd_boolean negated; | |
1175 | emit_state *state; | |
1176 | int len; | |
1177 | lit_state *ls; | |
1178 | ||
1179 | get_directive (&directive, &negated); | |
1180 | if (directive == (directiveE) XTENSA_UNDEFINED) | |
1181 | { | |
1182 | discard_rest_of_line (); | |
1183 | return; | |
1184 | } | |
1185 | ||
43cd72b9 BW |
1186 | if (cur_vinsn.inside_bundle) |
1187 | as_bad (_("directives are not valid inside bundles")); | |
1188 | ||
e0001a05 NC |
1189 | switch (directive) |
1190 | { | |
1191 | case directive_literal: | |
82e7541d BW |
1192 | if (!inside_directive (directive_literal)) |
1193 | { | |
1194 | /* Previous labels go with whatever follows this directive, not with | |
1195 | the literal, so save them now. */ | |
1196 | saved_insn_labels = insn_labels; | |
1197 | insn_labels = NULL; | |
1198 | } | |
43cd72b9 | 1199 | as_warn (_(".begin literal is deprecated; use .literal instead")); |
e0001a05 NC |
1200 | state = (emit_state *) xmalloc (sizeof (emit_state)); |
1201 | xtensa_switch_to_literal_fragment (state); | |
1202 | directive_push (directive_literal, negated, state); | |
1203 | break; | |
1204 | ||
1205 | case directive_literal_prefix: | |
c138bc38 | 1206 | /* Have to flush pending output because a movi relaxed to an l32r |
43cd72b9 BW |
1207 | might produce a literal. */ |
1208 | md_flush_pending_output (); | |
e0001a05 NC |
1209 | /* Check to see if the current fragment is a literal |
1210 | fragment. If it is, then this operation is not allowed. */ | |
43cd72b9 | 1211 | if (generating_literals) |
e0001a05 NC |
1212 | { |
1213 | as_bad (_("cannot set literal_prefix inside literal fragment")); | |
1214 | return; | |
1215 | } | |
1216 | ||
1217 | /* Allocate the literal state for this section and push | |
1218 | onto the directive stack. */ | |
1219 | ls = xmalloc (sizeof (lit_state)); | |
1220 | assert (ls); | |
1221 | ||
1222 | *ls = default_lit_sections; | |
1223 | ||
1224 | directive_push (directive_literal_prefix, negated, ls); | |
1225 | ||
1226 | /* Parse the new prefix from the input_line_pointer. */ | |
1227 | SKIP_WHITESPACE (); | |
1228 | len = strspn (input_line_pointer, | |
1229 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" | |
1230 | "abcdefghijklmnopqrstuvwxyz_/0123456789.$"); | |
1231 | ||
1232 | /* Process the new prefix. */ | |
1233 | xtensa_literal_prefix (input_line_pointer, len); | |
1234 | ||
1235 | /* Skip the name in the input line. */ | |
1236 | input_line_pointer += len; | |
1237 | break; | |
1238 | ||
1239 | case directive_freeregs: | |
1240 | /* This information is currently unused, but we'll accept the statement | |
1241 | and just discard the rest of the line. This won't check the syntax, | |
1242 | but it will accept every correct freeregs directive. */ | |
1243 | input_line_pointer += strcspn (input_line_pointer, "\n"); | |
1244 | directive_push (directive_freeregs, negated, 0); | |
1245 | break; | |
1246 | ||
43cd72b9 BW |
1247 | case directive_schedule: |
1248 | md_flush_pending_output (); | |
1249 | frag_var (rs_fill, 0, 0, frag_now->fr_subtype, | |
1250 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
1251 | directive_push (directive_schedule, negated, 0); | |
1252 | xtensa_set_frag_assembly_state (frag_now); | |
1253 | break; | |
1254 | ||
e0001a05 | 1255 | case directive_density: |
43cd72b9 BW |
1256 | as_warn (_(".begin [no-]density is ignored")); |
1257 | break; | |
1258 | ||
1259 | case directive_absolute_literals: | |
1260 | md_flush_pending_output (); | |
1261 | if (!absolute_literals_supported && !negated) | |
e0001a05 | 1262 | { |
43cd72b9 | 1263 | as_warn (_("Xtensa absolute literals option not supported; ignored")); |
e0001a05 NC |
1264 | break; |
1265 | } | |
43cd72b9 BW |
1266 | xtensa_set_frag_assembly_state (frag_now); |
1267 | directive_push (directive, negated, 0); | |
1268 | break; | |
e0001a05 NC |
1269 | |
1270 | default: | |
43cd72b9 BW |
1271 | md_flush_pending_output (); |
1272 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
1273 | directive_push (directive, negated, 0); |
1274 | break; | |
1275 | } | |
1276 | ||
1277 | demand_empty_rest_of_line (); | |
1278 | } | |
1279 | ||
1280 | ||
1281 | static void | |
7fa3d080 | 1282 | xtensa_end_directive (int ignore ATTRIBUTE_UNUSED) |
e0001a05 NC |
1283 | { |
1284 | directiveE begin_directive, end_directive; | |
1285 | bfd_boolean begin_negated, end_negated; | |
1286 | const char *file; | |
1287 | unsigned int line; | |
1288 | emit_state *state; | |
43cd72b9 | 1289 | emit_state **state_ptr; |
e0001a05 NC |
1290 | lit_state *s; |
1291 | ||
43cd72b9 BW |
1292 | if (cur_vinsn.inside_bundle) |
1293 | as_bad (_("directives are not valid inside bundles")); | |
82e7541d | 1294 | |
e0001a05 | 1295 | get_directive (&end_directive, &end_negated); |
43cd72b9 BW |
1296 | |
1297 | md_flush_pending_output (); | |
1298 | ||
1299 | switch (end_directive) | |
e0001a05 | 1300 | { |
43cd72b9 | 1301 | case (directiveE) XTENSA_UNDEFINED: |
e0001a05 NC |
1302 | discard_rest_of_line (); |
1303 | return; | |
e0001a05 | 1304 | |
43cd72b9 BW |
1305 | case directive_density: |
1306 | as_warn (_(".end [no-]density is ignored")); | |
e0001a05 | 1307 | demand_empty_rest_of_line (); |
43cd72b9 BW |
1308 | break; |
1309 | ||
1310 | case directive_absolute_literals: | |
1311 | if (!absolute_literals_supported && !end_negated) | |
1312 | { | |
1313 | as_warn (_("Xtensa absolute literals option not supported; ignored")); | |
1314 | demand_empty_rest_of_line (); | |
1315 | return; | |
1316 | } | |
1317 | break; | |
1318 | ||
1319 | default: | |
1320 | break; | |
e0001a05 NC |
1321 | } |
1322 | ||
43cd72b9 | 1323 | state_ptr = &state; /* use state_ptr to avoid type-punning warning */ |
e0001a05 | 1324 | directive_pop (&begin_directive, &begin_negated, &file, &line, |
43cd72b9 | 1325 | (const void **) state_ptr); |
e0001a05 NC |
1326 | |
1327 | if (begin_directive != directive_none) | |
1328 | { | |
1329 | if (begin_directive != end_directive || begin_negated != end_negated) | |
1330 | { | |
1331 | as_bad (_("does not match begin %s%s at %s:%d"), | |
1332 | begin_negated ? "no-" : "", | |
1333 | directive_info[begin_directive].name, file, line); | |
1334 | } | |
1335 | else | |
1336 | { | |
1337 | switch (end_directive) | |
1338 | { | |
1339 | case directive_literal: | |
1340 | frag_var (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
1341 | xtensa_restore_emit_state (state); | |
43cd72b9 | 1342 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 1343 | free (state); |
82e7541d BW |
1344 | if (!inside_directive (directive_literal)) |
1345 | { | |
1346 | /* Restore the list of current labels. */ | |
1347 | xtensa_clear_insn_labels (); | |
1348 | insn_labels = saved_insn_labels; | |
1349 | } | |
e0001a05 NC |
1350 | break; |
1351 | ||
e0001a05 NC |
1352 | case directive_literal_prefix: |
1353 | /* Restore the default collection sections from saved state. */ | |
1354 | s = (lit_state *) state; | |
1355 | assert (s); | |
1356 | ||
e8247da7 | 1357 | default_lit_sections = *s; |
e0001a05 NC |
1358 | |
1359 | /* free the state storage */ | |
1360 | free (s); | |
1361 | break; | |
1362 | ||
43cd72b9 BW |
1363 | case directive_schedule: |
1364 | case directive_freeregs: | |
1365 | break; | |
1366 | ||
e0001a05 | 1367 | default: |
43cd72b9 | 1368 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
1369 | break; |
1370 | } | |
1371 | } | |
1372 | } | |
1373 | ||
1374 | demand_empty_rest_of_line (); | |
1375 | } | |
1376 | ||
1377 | ||
1378 | /* Place an aligned literal fragment at the current location. */ | |
1379 | ||
1380 | static void | |
7fa3d080 | 1381 | xtensa_literal_position (int ignore ATTRIBUTE_UNUSED) |
e0001a05 | 1382 | { |
43cd72b9 BW |
1383 | md_flush_pending_output (); |
1384 | ||
e0001a05 NC |
1385 | if (inside_directive (directive_literal)) |
1386 | as_warn (_(".literal_position inside literal directive; ignoring")); | |
43cd72b9 | 1387 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
1388 | |
1389 | demand_empty_rest_of_line (); | |
82e7541d | 1390 | xtensa_clear_insn_labels (); |
e0001a05 NC |
1391 | } |
1392 | ||
1393 | ||
43cd72b9 | 1394 | /* Support .literal label, expr, ... */ |
e0001a05 NC |
1395 | |
1396 | static void | |
7fa3d080 | 1397 | xtensa_literal_pseudo (int ignored ATTRIBUTE_UNUSED) |
e0001a05 NC |
1398 | { |
1399 | emit_state state; | |
1745fcba | 1400 | char *p, *base_name; |
e0001a05 | 1401 | char c; |
e0001a05 NC |
1402 | segT dest_seg; |
1403 | ||
82e7541d BW |
1404 | if (inside_directive (directive_literal)) |
1405 | { | |
1406 | as_bad (_(".literal not allowed inside .begin literal region")); | |
1407 | ignore_rest_of_line (); | |
1408 | return; | |
1409 | } | |
1410 | ||
43cd72b9 BW |
1411 | md_flush_pending_output (); |
1412 | ||
82e7541d BW |
1413 | /* Previous labels go with whatever follows this directive, not with |
1414 | the literal, so save them now. */ | |
1415 | saved_insn_labels = insn_labels; | |
1416 | insn_labels = NULL; | |
1417 | ||
e0001a05 NC |
1418 | /* If we are using text-section literals, then this is the right value... */ |
1419 | dest_seg = now_seg; | |
1420 | ||
1421 | base_name = input_line_pointer; | |
1422 | ||
1423 | xtensa_switch_to_literal_fragment (&state); | |
1424 | ||
43cd72b9 | 1425 | /* ...but if we aren't using text-section-literals, then we |
e0001a05 | 1426 | need to put them in the section we just switched to. */ |
43cd72b9 | 1427 | if (use_literal_section || directive_state[directive_absolute_literals]) |
e0001a05 NC |
1428 | dest_seg = now_seg; |
1429 | ||
43cd72b9 BW |
1430 | /* All literals are aligned to four-byte boundaries. */ |
1431 | frag_align (2, 0, 0); | |
1432 | record_alignment (now_seg, 2); | |
e0001a05 NC |
1433 | |
1434 | c = get_symbol_end (); | |
1435 | /* Just after name is now '\0'. */ | |
1436 | p = input_line_pointer; | |
1437 | *p = c; | |
1438 | SKIP_WHITESPACE (); | |
1439 | ||
1440 | if (*input_line_pointer != ',' && *input_line_pointer != ':') | |
1441 | { | |
1442 | as_bad (_("expected comma or colon after symbol name; " | |
1443 | "rest of line ignored")); | |
1444 | ignore_rest_of_line (); | |
1445 | xtensa_restore_emit_state (&state); | |
1446 | return; | |
1447 | } | |
1448 | *p = 0; | |
1449 | ||
e0001a05 | 1450 | colon (base_name); |
e0001a05 | 1451 | |
e0001a05 | 1452 | *p = c; |
43cd72b9 | 1453 | input_line_pointer++; /* skip ',' or ':' */ |
e0001a05 | 1454 | |
43cd72b9 | 1455 | xtensa_elf_cons (4); |
e0001a05 NC |
1456 | |
1457 | xtensa_restore_emit_state (&state); | |
82e7541d BW |
1458 | |
1459 | /* Restore the list of current labels. */ | |
1460 | xtensa_clear_insn_labels (); | |
1461 | insn_labels = saved_insn_labels; | |
e0001a05 NC |
1462 | } |
1463 | ||
1464 | ||
1465 | static void | |
7fa3d080 | 1466 | xtensa_literal_prefix (char const *start, int len) |
e0001a05 | 1467 | { |
43cd72b9 BW |
1468 | char *name, *linkonce_suffix; |
1469 | char *newname, *newname4; | |
1470 | size_t linkonce_len; | |
e0001a05 NC |
1471 | |
1472 | /* Get a null-terminated copy of the name. */ | |
1473 | name = xmalloc (len + 1); | |
1474 | assert (name); | |
1475 | ||
1476 | strncpy (name, start, len); | |
1477 | name[len] = 0; | |
1478 | ||
1479 | /* Allocate the sections (interesting note: the memory pointing to | |
1480 | the name is actually used for the name by the new section). */ | |
43cd72b9 | 1481 | |
e0001a05 | 1482 | newname = xmalloc (len + strlen (".literal") + 1); |
43cd72b9 | 1483 | newname4 = xmalloc (len + strlen (".lit4") + 1); |
e0001a05 | 1484 | |
43cd72b9 BW |
1485 | linkonce_len = sizeof (".gnu.linkonce.") - 1; |
1486 | if (strncmp (name, ".gnu.linkonce.", linkonce_len) == 0 | |
1487 | && (linkonce_suffix = strchr (name + linkonce_len, '.')) != 0) | |
1488 | { | |
1489 | strcpy (newname, ".gnu.linkonce.literal"); | |
1490 | strcpy (newname4, ".gnu.linkonce.lit4"); | |
e0001a05 | 1491 | |
43cd72b9 BW |
1492 | strcat (newname, linkonce_suffix); |
1493 | strcat (newname4, linkonce_suffix); | |
1494 | } | |
1495 | else | |
1496 | { | |
1497 | int suffix_pos = len; | |
1498 | ||
1499 | /* If the section name ends with ".text", then replace that suffix | |
1500 | instead of appending an additional suffix. */ | |
1501 | if (len >= 5 && strcmp (name + len - 5, ".text") == 0) | |
1502 | suffix_pos -= 5; | |
1503 | ||
1504 | strcpy (newname, name); | |
1505 | strcpy (newname4, name); | |
1506 | ||
1507 | strcpy (newname + suffix_pos, ".literal"); | |
1508 | strcpy (newname4 + suffix_pos, ".lit4"); | |
1509 | } | |
1510 | ||
b08b5071 | 1511 | /* Note that cache_literal_section does not create a segment if |
43cd72b9 BW |
1512 | it already exists. */ |
1513 | default_lit_sections.lit_seg = NULL; | |
1514 | default_lit_sections.lit4_seg = NULL; | |
1515 | ||
1516 | /* Canonicalizing section names allows renaming literal | |
e0001a05 | 1517 | sections to occur correctly. */ |
43cd72b9 BW |
1518 | default_lit_sections.lit_seg_name = tc_canonicalize_symbol_name (newname); |
1519 | default_lit_sections.lit4_seg_name = tc_canonicalize_symbol_name (newname4); | |
e0001a05 NC |
1520 | |
1521 | free (name); | |
43cd72b9 BW |
1522 | } |
1523 | ||
1524 | ||
1525 | /* Support ".frequency branch_target_frequency fall_through_frequency". */ | |
1526 | ||
1527 | static void | |
7fa3d080 | 1528 | xtensa_frequency_pseudo (int ignored ATTRIBUTE_UNUSED) |
43cd72b9 BW |
1529 | { |
1530 | float fall_through_f, target_f; | |
43cd72b9 BW |
1531 | |
1532 | fall_through_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1533 | if (fall_through_f < 0) | |
1534 | { | |
1535 | as_bad (_("fall through frequency must be greater than 0")); | |
1536 | ignore_rest_of_line (); | |
1537 | return; | |
1538 | } | |
1539 | ||
1540 | target_f = (float) strtod (input_line_pointer, &input_line_pointer); | |
1541 | if (target_f < 0) | |
1542 | { | |
1543 | as_bad (_("branch target frequency must be greater than 0")); | |
1544 | ignore_rest_of_line (); | |
1545 | return; | |
1546 | } | |
1547 | ||
b08b5071 | 1548 | set_subseg_freq (now_seg, now_subseg, target_f + fall_through_f, target_f); |
43cd72b9 BW |
1549 | |
1550 | demand_empty_rest_of_line (); | |
1551 | } | |
1552 | ||
1553 | ||
1554 | /* Like normal .long/.short/.word, except support @plt, etc. | |
1555 | Clobbers input_line_pointer, checks end-of-line. */ | |
1556 | ||
1557 | static void | |
7fa3d080 | 1558 | xtensa_elf_cons (int nbytes) |
43cd72b9 BW |
1559 | { |
1560 | expressionS exp; | |
1561 | bfd_reloc_code_real_type reloc; | |
1562 | ||
1563 | md_flush_pending_output (); | |
1564 | ||
1565 | if (cur_vinsn.inside_bundle) | |
1566 | as_bad (_("directives are not valid inside bundles")); | |
1567 | ||
1568 | if (is_it_end_of_statement ()) | |
1569 | { | |
1570 | demand_empty_rest_of_line (); | |
1571 | return; | |
1572 | } | |
1573 | ||
1574 | do | |
1575 | { | |
1576 | expression (&exp); | |
1577 | if (exp.X_op == O_symbol | |
1578 | && *input_line_pointer == '@' | |
1579 | && ((reloc = xtensa_elf_suffix (&input_line_pointer, &exp)) | |
1580 | != BFD_RELOC_NONE)) | |
1581 | { | |
1582 | reloc_howto_type *reloc_howto = | |
1583 | bfd_reloc_type_lookup (stdoutput, reloc); | |
1584 | ||
1585 | if (reloc == BFD_RELOC_UNUSED || !reloc_howto) | |
1586 | as_bad (_("unsupported relocation")); | |
1587 | else if ((reloc >= BFD_RELOC_XTENSA_SLOT0_OP | |
1588 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
1589 | || (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT | |
1590 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT)) | |
1591 | as_bad (_("opcode-specific %s relocation used outside " | |
1592 | "an instruction"), reloc_howto->name); | |
1593 | else if (nbytes != (int) bfd_get_reloc_size (reloc_howto)) | |
1594 | as_bad (_("%s relocations do not fit in %d bytes"), | |
1595 | reloc_howto->name, nbytes); | |
1596 | else | |
1597 | { | |
1598 | char *p = frag_more ((int) nbytes); | |
1599 | xtensa_set_frag_assembly_state (frag_now); | |
1600 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
1601 | nbytes, &exp, 0, reloc); | |
1602 | } | |
1603 | } | |
1604 | else | |
1605 | emit_expr (&exp, (unsigned int) nbytes); | |
1606 | } | |
1607 | while (*input_line_pointer++ == ','); | |
1608 | ||
1609 | input_line_pointer--; /* Put terminator back into stream. */ | |
1610 | demand_empty_rest_of_line (); | |
1611 | } | |
1612 | ||
7fa3d080 BW |
1613 | \f |
1614 | /* Parsing and Idiom Translation. */ | |
43cd72b9 BW |
1615 | |
1616 | /* Parse @plt, etc. and return the desired relocation. */ | |
1617 | static bfd_reloc_code_real_type | |
7fa3d080 | 1618 | xtensa_elf_suffix (char **str_p, expressionS *exp_p) |
43cd72b9 BW |
1619 | { |
1620 | struct map_bfd | |
1621 | { | |
1622 | char *string; | |
1623 | int length; | |
1624 | bfd_reloc_code_real_type reloc; | |
1625 | }; | |
1626 | ||
1627 | char ident[20]; | |
1628 | char *str = *str_p; | |
1629 | char *str2; | |
1630 | int ch; | |
1631 | int len; | |
1632 | struct map_bfd *ptr; | |
1633 | ||
1634 | #define MAP(str,reloc) { str, sizeof (str) - 1, reloc } | |
e0001a05 | 1635 | |
43cd72b9 BW |
1636 | static struct map_bfd mapping[] = |
1637 | { | |
1638 | MAP ("l", BFD_RELOC_LO16), | |
1639 | MAP ("h", BFD_RELOC_HI16), | |
1640 | MAP ("plt", BFD_RELOC_XTENSA_PLT), | |
1641 | { (char *) 0, 0, BFD_RELOC_UNUSED } | |
1642 | }; | |
1643 | ||
1644 | if (*str++ != '@') | |
1645 | return BFD_RELOC_NONE; | |
1646 | ||
1647 | for (ch = *str, str2 = ident; | |
1648 | (str2 < ident + sizeof (ident) - 1 | |
1649 | && (ISALNUM (ch) || ch == '@')); | |
1650 | ch = *++str) | |
1651 | { | |
1652 | *str2++ = (ISLOWER (ch)) ? ch : TOLOWER (ch); | |
1653 | } | |
1654 | ||
1655 | *str2 = '\0'; | |
1656 | len = str2 - ident; | |
1657 | ||
1658 | ch = ident[0]; | |
1659 | for (ptr = &mapping[0]; ptr->length > 0; ptr++) | |
1660 | if (ch == ptr->string[0] | |
1661 | && len == ptr->length | |
1662 | && memcmp (ident, ptr->string, ptr->length) == 0) | |
1663 | { | |
1664 | /* Now check for "identifier@suffix+constant". */ | |
1665 | if (*str == '-' || *str == '+') | |
1666 | { | |
1667 | char *orig_line = input_line_pointer; | |
1668 | expressionS new_exp; | |
1669 | ||
1670 | input_line_pointer = str; | |
1671 | expression (&new_exp); | |
1672 | if (new_exp.X_op == O_constant) | |
1673 | { | |
1674 | exp_p->X_add_number += new_exp.X_add_number; | |
1675 | str = input_line_pointer; | |
1676 | } | |
1677 | ||
1678 | if (&input_line_pointer != str_p) | |
1679 | input_line_pointer = orig_line; | |
1680 | } | |
1681 | ||
1682 | *str_p = str; | |
1683 | return ptr->reloc; | |
1684 | } | |
1685 | ||
1686 | return BFD_RELOC_UNUSED; | |
e0001a05 NC |
1687 | } |
1688 | ||
e0001a05 NC |
1689 | |
1690 | static const char * | |
7fa3d080 | 1691 | expression_end (const char *name) |
e0001a05 NC |
1692 | { |
1693 | while (1) | |
1694 | { | |
1695 | switch (*name) | |
1696 | { | |
43cd72b9 | 1697 | case '}': |
e0001a05 NC |
1698 | case ';': |
1699 | case '\0': | |
1700 | case ',': | |
43cd72b9 | 1701 | case ':': |
e0001a05 NC |
1702 | return name; |
1703 | case ' ': | |
1704 | case '\t': | |
1705 | ++name; | |
1706 | continue; | |
1707 | default: | |
1708 | return 0; | |
1709 | } | |
1710 | } | |
1711 | } | |
1712 | ||
1713 | ||
1714 | #define ERROR_REG_NUM ((unsigned) -1) | |
1715 | ||
1716 | static unsigned | |
7fa3d080 | 1717 | tc_get_register (const char *prefix) |
e0001a05 NC |
1718 | { |
1719 | unsigned reg; | |
1720 | const char *next_expr; | |
1721 | const char *old_line_pointer; | |
1722 | ||
1723 | SKIP_WHITESPACE (); | |
1724 | old_line_pointer = input_line_pointer; | |
1725 | ||
1726 | if (*input_line_pointer == '$') | |
1727 | ++input_line_pointer; | |
1728 | ||
1729 | /* Accept "sp" as a synonym for "a1". */ | |
1730 | if (input_line_pointer[0] == 's' && input_line_pointer[1] == 'p' | |
1731 | && expression_end (input_line_pointer + 2)) | |
1732 | { | |
1733 | input_line_pointer += 2; | |
1734 | return 1; /* AR[1] */ | |
1735 | } | |
1736 | ||
1737 | while (*input_line_pointer++ == *prefix++) | |
1738 | ; | |
1739 | --input_line_pointer; | |
1740 | --prefix; | |
1741 | ||
1742 | if (*prefix) | |
1743 | { | |
1744 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1745 | return ERROR_REG_NUM; | |
1746 | } | |
1747 | ||
1748 | if (!ISDIGIT ((unsigned char) *input_line_pointer)) | |
1749 | { | |
1750 | as_bad (_("bad register number: %s"), input_line_pointer); | |
1751 | return ERROR_REG_NUM; | |
1752 | } | |
1753 | ||
1754 | reg = 0; | |
1755 | ||
1756 | while (ISDIGIT ((int) *input_line_pointer)) | |
1757 | reg = reg * 10 + *input_line_pointer++ - '0'; | |
1758 | ||
1759 | if (!(next_expr = expression_end (input_line_pointer))) | |
1760 | { | |
1761 | as_bad (_("bad register name: %s"), old_line_pointer); | |
1762 | return ERROR_REG_NUM; | |
1763 | } | |
1764 | ||
1765 | input_line_pointer = (char *) next_expr; | |
1766 | ||
1767 | return reg; | |
1768 | } | |
1769 | ||
1770 | ||
e0001a05 | 1771 | static void |
7fa3d080 | 1772 | expression_maybe_register (xtensa_opcode opc, int opnd, expressionS *tok) |
e0001a05 | 1773 | { |
43cd72b9 | 1774 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 | 1775 | |
43cd72b9 BW |
1776 | /* Check if this is an immediate operand. */ |
1777 | if (xtensa_operand_is_register (isa, opc, opnd) == 0) | |
e0001a05 | 1778 | { |
43cd72b9 | 1779 | bfd_reloc_code_real_type reloc; |
e0001a05 | 1780 | segT t = expression (tok); |
43cd72b9 BW |
1781 | if (t == absolute_section |
1782 | && xtensa_operand_is_PCrelative (isa, opc, opnd) == 1) | |
e0001a05 NC |
1783 | { |
1784 | assert (tok->X_op == O_constant); | |
1785 | tok->X_op = O_symbol; | |
1786 | tok->X_add_symbol = &abs_symbol; | |
1787 | } | |
43cd72b9 BW |
1788 | |
1789 | if ((tok->X_op == O_constant || tok->X_op == O_symbol) | |
1790 | && (reloc = xtensa_elf_suffix (&input_line_pointer, tok)) | |
1791 | && (reloc != BFD_RELOC_NONE)) | |
e0001a05 | 1792 | { |
43cd72b9 BW |
1793 | switch (reloc) |
1794 | { | |
1795 | default: | |
1796 | case BFD_RELOC_UNUSED: | |
1797 | as_bad (_("unsupported relocation")); | |
1798 | break; | |
1799 | ||
1800 | case BFD_RELOC_XTENSA_PLT: | |
1801 | tok->X_op = O_pltrel; | |
1802 | break; | |
1803 | ||
1804 | case BFD_RELOC_LO16: | |
1805 | if (tok->X_op == O_constant) | |
1806 | tok->X_add_number &= 0xffff; | |
1807 | else | |
1808 | tok->X_op = O_lo16; | |
1809 | break; | |
1810 | ||
1811 | case BFD_RELOC_HI16: | |
1812 | if (tok->X_op == O_constant) | |
1813 | tok->X_add_number = ((unsigned) tok->X_add_number) >> 16; | |
1814 | else | |
1815 | tok->X_op = O_hi16; | |
1816 | break; | |
1817 | } | |
e0001a05 | 1818 | } |
e0001a05 NC |
1819 | } |
1820 | else | |
1821 | { | |
43cd72b9 BW |
1822 | xtensa_regfile opnd_rf = xtensa_operand_regfile (isa, opc, opnd); |
1823 | unsigned reg = tc_get_register (xtensa_regfile_shortname (isa, opnd_rf)); | |
e0001a05 NC |
1824 | |
1825 | if (reg != ERROR_REG_NUM) /* Already errored */ | |
1826 | { | |
1827 | uint32 buf = reg; | |
43cd72b9 | 1828 | if (xtensa_operand_encode (isa, opc, opnd, &buf)) |
e0001a05 NC |
1829 | as_bad (_("register number out of range")); |
1830 | } | |
1831 | ||
1832 | tok->X_op = O_register; | |
1833 | tok->X_add_symbol = 0; | |
1834 | tok->X_add_number = reg; | |
1835 | } | |
1836 | } | |
1837 | ||
1838 | ||
1839 | /* Split up the arguments for an opcode or pseudo-op. */ | |
1840 | ||
1841 | static int | |
7fa3d080 | 1842 | tokenize_arguments (char **args, char *str) |
e0001a05 NC |
1843 | { |
1844 | char *old_input_line_pointer; | |
1845 | bfd_boolean saw_comma = FALSE; | |
1846 | bfd_boolean saw_arg = FALSE; | |
43cd72b9 | 1847 | bfd_boolean saw_colon = FALSE; |
e0001a05 NC |
1848 | int num_args = 0; |
1849 | char *arg_end, *arg; | |
1850 | int arg_len; | |
43cd72b9 BW |
1851 | |
1852 | /* Save and restore input_line_pointer around this function. */ | |
e0001a05 NC |
1853 | old_input_line_pointer = input_line_pointer; |
1854 | input_line_pointer = str; | |
1855 | ||
1856 | while (*input_line_pointer) | |
1857 | { | |
1858 | SKIP_WHITESPACE (); | |
1859 | switch (*input_line_pointer) | |
1860 | { | |
1861 | case '\0': | |
43cd72b9 | 1862 | case '}': |
e0001a05 NC |
1863 | goto fini; |
1864 | ||
43cd72b9 BW |
1865 | case ':': |
1866 | input_line_pointer++; | |
1867 | if (saw_comma || saw_colon || !saw_arg) | |
1868 | goto err; | |
1869 | saw_colon = TRUE; | |
1870 | break; | |
1871 | ||
e0001a05 NC |
1872 | case ',': |
1873 | input_line_pointer++; | |
43cd72b9 | 1874 | if (saw_comma || saw_colon || !saw_arg) |
e0001a05 NC |
1875 | goto err; |
1876 | saw_comma = TRUE; | |
1877 | break; | |
1878 | ||
1879 | default: | |
43cd72b9 | 1880 | if (!saw_comma && !saw_colon && saw_arg) |
e0001a05 NC |
1881 | goto err; |
1882 | ||
1883 | arg_end = input_line_pointer + 1; | |
1884 | while (!expression_end (arg_end)) | |
1885 | arg_end += 1; | |
43cd72b9 | 1886 | |
e0001a05 | 1887 | arg_len = arg_end - input_line_pointer; |
43cd72b9 | 1888 | arg = (char *) xmalloc ((saw_colon ? 1 : 0) + arg_len + 1); |
e0001a05 NC |
1889 | args[num_args] = arg; |
1890 | ||
43cd72b9 BW |
1891 | if (saw_colon) |
1892 | *arg++ = ':'; | |
e0001a05 NC |
1893 | strncpy (arg, input_line_pointer, arg_len); |
1894 | arg[arg_len] = '\0'; | |
43cd72b9 | 1895 | |
e0001a05 NC |
1896 | input_line_pointer = arg_end; |
1897 | num_args += 1; | |
c138bc38 | 1898 | saw_comma = FALSE; |
43cd72b9 | 1899 | saw_colon = FALSE; |
c138bc38 | 1900 | saw_arg = TRUE; |
e0001a05 NC |
1901 | break; |
1902 | } | |
1903 | } | |
1904 | ||
1905 | fini: | |
43cd72b9 | 1906 | if (saw_comma || saw_colon) |
e0001a05 NC |
1907 | goto err; |
1908 | input_line_pointer = old_input_line_pointer; | |
1909 | return num_args; | |
1910 | ||
1911 | err: | |
43cd72b9 BW |
1912 | if (saw_comma) |
1913 | as_bad (_("extra comma")); | |
1914 | else if (saw_colon) | |
1915 | as_bad (_("extra colon")); | |
1916 | else if (!saw_arg) | |
c138bc38 | 1917 | as_bad (_("missing argument")); |
43cd72b9 BW |
1918 | else |
1919 | as_bad (_("missing comma or colon")); | |
e0001a05 NC |
1920 | input_line_pointer = old_input_line_pointer; |
1921 | return -1; | |
1922 | } | |
1923 | ||
1924 | ||
43cd72b9 | 1925 | /* Parse the arguments to an opcode. Return TRUE on error. */ |
e0001a05 NC |
1926 | |
1927 | static bfd_boolean | |
7fa3d080 | 1928 | parse_arguments (TInsn *insn, int num_args, char **arg_strings) |
e0001a05 | 1929 | { |
43cd72b9 | 1930 | expressionS *tok, *last_tok; |
e0001a05 NC |
1931 | xtensa_opcode opcode = insn->opcode; |
1932 | bfd_boolean had_error = TRUE; | |
43cd72b9 BW |
1933 | xtensa_isa isa = xtensa_default_isa; |
1934 | int n, num_regs = 0; | |
e0001a05 | 1935 | int opcode_operand_count; |
43cd72b9 BW |
1936 | int opnd_cnt, last_opnd_cnt; |
1937 | unsigned int next_reg = 0; | |
e0001a05 NC |
1938 | char *old_input_line_pointer; |
1939 | ||
1940 | if (insn->insn_type == ITYPE_LITERAL) | |
1941 | opcode_operand_count = 1; | |
1942 | else | |
43cd72b9 | 1943 | opcode_operand_count = xtensa_opcode_num_operands (isa, opcode); |
e0001a05 | 1944 | |
43cd72b9 | 1945 | tok = insn->tok; |
e0001a05 NC |
1946 | memset (tok, 0, sizeof (*tok) * MAX_INSN_ARGS); |
1947 | ||
1948 | /* Save and restore input_line_pointer around this function. */ | |
43cd72b9 BW |
1949 | old_input_line_pointer = input_line_pointer; |
1950 | ||
1951 | last_tok = 0; | |
1952 | last_opnd_cnt = -1; | |
1953 | opnd_cnt = 0; | |
1954 | ||
1955 | /* Skip invisible operands. */ | |
1956 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0) | |
1957 | { | |
1958 | opnd_cnt += 1; | |
1959 | tok++; | |
1960 | } | |
e0001a05 NC |
1961 | |
1962 | for (n = 0; n < num_args; n++) | |
43cd72b9 | 1963 | { |
e0001a05 | 1964 | input_line_pointer = arg_strings[n]; |
43cd72b9 BW |
1965 | if (*input_line_pointer == ':') |
1966 | { | |
1967 | xtensa_regfile opnd_rf; | |
1968 | input_line_pointer++; | |
1969 | if (num_regs == 0) | |
1970 | goto err; | |
1971 | assert (opnd_cnt > 0); | |
1972 | num_regs--; | |
1973 | opnd_rf = xtensa_operand_regfile (isa, opcode, last_opnd_cnt); | |
1974 | if (next_reg | |
1975 | != tc_get_register (xtensa_regfile_shortname (isa, opnd_rf))) | |
1976 | as_warn (_("incorrect register number, ignoring")); | |
1977 | next_reg++; | |
1978 | } | |
1979 | else | |
1980 | { | |
1981 | if (opnd_cnt >= opcode_operand_count) | |
1982 | { | |
1983 | as_warn (_("too many arguments")); | |
1984 | goto err; | |
1985 | } | |
1986 | assert (opnd_cnt < MAX_INSN_ARGS); | |
1987 | ||
1988 | expression_maybe_register (opcode, opnd_cnt, tok); | |
1989 | next_reg = tok->X_add_number + 1; | |
1990 | ||
1991 | if (tok->X_op == O_illegal || tok->X_op == O_absent) | |
1992 | goto err; | |
1993 | if (xtensa_operand_is_register (isa, opcode, opnd_cnt) == 1) | |
1994 | { | |
1995 | num_regs = xtensa_operand_num_regs (isa, opcode, opnd_cnt) - 1; | |
1996 | /* minus 1 because we are seeing one right now */ | |
1997 | } | |
1998 | else | |
1999 | num_regs = 0; | |
e0001a05 | 2000 | |
43cd72b9 BW |
2001 | last_tok = tok; |
2002 | last_opnd_cnt = opnd_cnt; | |
e0001a05 | 2003 | |
43cd72b9 BW |
2004 | do |
2005 | { | |
2006 | opnd_cnt += 1; | |
2007 | tok++; | |
2008 | } | |
2009 | while (xtensa_operand_is_visible (isa, opcode, opnd_cnt) == 0); | |
2010 | } | |
2011 | } | |
e0001a05 | 2012 | |
43cd72b9 BW |
2013 | if (num_regs > 0 && ((int) next_reg != last_tok->X_add_number + 1)) |
2014 | goto err; | |
e0001a05 NC |
2015 | |
2016 | insn->ntok = tok - insn->tok; | |
c138bc38 | 2017 | had_error = FALSE; |
e0001a05 NC |
2018 | |
2019 | err: | |
43cd72b9 | 2020 | input_line_pointer = old_input_line_pointer; |
e0001a05 NC |
2021 | return had_error; |
2022 | } | |
2023 | ||
2024 | ||
43cd72b9 | 2025 | static int |
7fa3d080 | 2026 | get_invisible_operands (TInsn *insn) |
43cd72b9 BW |
2027 | { |
2028 | xtensa_isa isa = xtensa_default_isa; | |
2029 | static xtensa_insnbuf slotbuf = NULL; | |
2030 | xtensa_format fmt; | |
2031 | xtensa_opcode opc = insn->opcode; | |
2032 | int slot, opnd, fmt_found; | |
2033 | unsigned val; | |
2034 | ||
2035 | if (!slotbuf) | |
2036 | slotbuf = xtensa_insnbuf_alloc (isa); | |
2037 | ||
2038 | /* Find format/slot where this can be encoded. */ | |
2039 | fmt_found = 0; | |
2040 | slot = 0; | |
2041 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
2042 | { | |
2043 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
2044 | { | |
2045 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opc) == 0) | |
2046 | { | |
2047 | fmt_found = 1; | |
2048 | break; | |
2049 | } | |
2050 | } | |
2051 | if (fmt_found) break; | |
2052 | } | |
2053 | ||
2054 | if (!fmt_found) | |
2055 | { | |
2056 | as_bad (_("cannot encode opcode \"%s\""), xtensa_opcode_name (isa, opc)); | |
2057 | return -1; | |
2058 | } | |
2059 | ||
2060 | /* First encode all the visible operands | |
2061 | (to deal with shared field operands). */ | |
2062 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2063 | { | |
2064 | if (xtensa_operand_is_visible (isa, opc, opnd) == 1 | |
2065 | && (insn->tok[opnd].X_op == O_register | |
2066 | || insn->tok[opnd].X_op == O_constant)) | |
2067 | { | |
2068 | val = insn->tok[opnd].X_add_number; | |
2069 | xtensa_operand_encode (isa, opc, opnd, &val); | |
2070 | xtensa_operand_set_field (isa, opc, opnd, fmt, slot, slotbuf, val); | |
2071 | } | |
2072 | } | |
2073 | ||
2074 | /* Then pull out the values for the invisible ones. */ | |
2075 | for (opnd = 0; opnd < insn->ntok; opnd++) | |
2076 | { | |
2077 | if (xtensa_operand_is_visible (isa, opc, opnd) == 0) | |
2078 | { | |
2079 | xtensa_operand_get_field (isa, opc, opnd, fmt, slot, slotbuf, &val); | |
2080 | xtensa_operand_decode (isa, opc, opnd, &val); | |
2081 | insn->tok[opnd].X_add_number = val; | |
2082 | if (xtensa_operand_is_register (isa, opc, opnd) == 1) | |
2083 | insn->tok[opnd].X_op = O_register; | |
2084 | else | |
2085 | insn->tok[opnd].X_op = O_constant; | |
2086 | } | |
2087 | } | |
2088 | ||
2089 | return 0; | |
2090 | } | |
2091 | ||
2092 | ||
e0001a05 | 2093 | static void |
7fa3d080 | 2094 | xg_reverse_shift_count (char **cnt_argp) |
e0001a05 NC |
2095 | { |
2096 | char *cnt_arg, *new_arg; | |
2097 | cnt_arg = *cnt_argp; | |
2098 | ||
2099 | /* replace the argument with "31-(argument)" */ | |
2100 | new_arg = (char *) xmalloc (strlen (cnt_arg) + 6); | |
2101 | sprintf (new_arg, "31-(%s)", cnt_arg); | |
2102 | ||
2103 | free (cnt_arg); | |
2104 | *cnt_argp = new_arg; | |
2105 | } | |
2106 | ||
2107 | ||
2108 | /* If "arg" is a constant expression, return non-zero with the value | |
2109 | in *valp. */ | |
2110 | ||
2111 | static int | |
7fa3d080 | 2112 | xg_arg_is_constant (char *arg, offsetT *valp) |
e0001a05 NC |
2113 | { |
2114 | expressionS exp; | |
2115 | char *save_ptr = input_line_pointer; | |
2116 | ||
2117 | input_line_pointer = arg; | |
2118 | expression (&exp); | |
2119 | input_line_pointer = save_ptr; | |
2120 | ||
2121 | if (exp.X_op == O_constant) | |
2122 | { | |
2123 | *valp = exp.X_add_number; | |
2124 | return 1; | |
2125 | } | |
2126 | ||
2127 | return 0; | |
2128 | } | |
2129 | ||
2130 | ||
2131 | static void | |
7fa3d080 | 2132 | xg_replace_opname (char **popname, char *newop) |
e0001a05 NC |
2133 | { |
2134 | free (*popname); | |
2135 | *popname = (char *) xmalloc (strlen (newop) + 1); | |
2136 | strcpy (*popname, newop); | |
2137 | } | |
2138 | ||
2139 | ||
2140 | static int | |
7fa3d080 BW |
2141 | xg_check_num_args (int *pnum_args, |
2142 | int expected_num, | |
2143 | char *opname, | |
2144 | char **arg_strings) | |
e0001a05 NC |
2145 | { |
2146 | int num_args = *pnum_args; | |
2147 | ||
43cd72b9 | 2148 | if (num_args < expected_num) |
e0001a05 NC |
2149 | { |
2150 | as_bad (_("not enough operands (%d) for '%s'; expected %d"), | |
2151 | num_args, opname, expected_num); | |
2152 | return -1; | |
2153 | } | |
2154 | ||
2155 | if (num_args > expected_num) | |
2156 | { | |
2157 | as_warn (_("too many operands (%d) for '%s'; expected %d"), | |
2158 | num_args, opname, expected_num); | |
2159 | while (num_args-- > expected_num) | |
2160 | { | |
2161 | free (arg_strings[num_args]); | |
2162 | arg_strings[num_args] = 0; | |
2163 | } | |
2164 | *pnum_args = expected_num; | |
2165 | return -1; | |
2166 | } | |
2167 | ||
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | ||
43cd72b9 BW |
2172 | /* If the register is not specified as part of the opcode, |
2173 | then get it from the operand and move it to the opcode. */ | |
2174 | ||
e0001a05 | 2175 | static int |
7fa3d080 | 2176 | xg_translate_sysreg_op (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 | 2177 | { |
43cd72b9 BW |
2178 | xtensa_isa isa = xtensa_default_isa; |
2179 | xtensa_sysreg sr; | |
e0001a05 | 2180 | char *opname, *new_opname; |
43cd72b9 BW |
2181 | const char *sr_name; |
2182 | int is_user, is_write; | |
e0001a05 NC |
2183 | |
2184 | opname = *popname; | |
2185 | if (*opname == '_') | |
80ca4e2c | 2186 | opname += 1; |
43cd72b9 BW |
2187 | is_user = (opname[1] == 'u'); |
2188 | is_write = (opname[0] == 'w'); | |
e0001a05 | 2189 | |
43cd72b9 | 2190 | /* Opname == [rw]ur or [rwx]sr... */ |
e0001a05 | 2191 | |
43cd72b9 BW |
2192 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) |
2193 | return -1; | |
e0001a05 | 2194 | |
43cd72b9 BW |
2195 | /* Check if the argument is a symbolic register name. */ |
2196 | sr = xtensa_sysreg_lookup_name (isa, arg_strings[1]); | |
2197 | /* Handle WSR to "INTSET" as a special case. */ | |
2198 | if (sr == XTENSA_UNDEFINED && is_write && !is_user | |
2199 | && !strcasecmp (arg_strings[1], "intset")) | |
2200 | sr = xtensa_sysreg_lookup_name (isa, "interrupt"); | |
2201 | if (sr == XTENSA_UNDEFINED | |
2202 | || (xtensa_sysreg_is_user (isa, sr) == 1) != is_user) | |
2203 | { | |
2204 | /* Maybe it's a register number.... */ | |
2205 | offsetT val; | |
e0001a05 NC |
2206 | if (!xg_arg_is_constant (arg_strings[1], &val)) |
2207 | { | |
43cd72b9 BW |
2208 | as_bad (_("invalid register '%s' for '%s' instruction"), |
2209 | arg_strings[1], opname); | |
e0001a05 NC |
2210 | return -1; |
2211 | } | |
43cd72b9 BW |
2212 | sr = xtensa_sysreg_lookup (isa, val, is_user); |
2213 | if (sr == XTENSA_UNDEFINED) | |
e0001a05 | 2214 | { |
43cd72b9 | 2215 | as_bad (_("invalid register number (%ld) for '%s' instruction"), |
dd49a749 | 2216 | (long) val, opname); |
e0001a05 NC |
2217 | return -1; |
2218 | } | |
43cd72b9 | 2219 | } |
e0001a05 | 2220 | |
43cd72b9 BW |
2221 | /* Remove the last argument, which is now part of the opcode. */ |
2222 | free (arg_strings[1]); | |
2223 | arg_strings[1] = 0; | |
2224 | *pnum_args = 1; | |
2225 | ||
2226 | /* Translate the opcode. */ | |
2227 | sr_name = xtensa_sysreg_name (isa, sr); | |
2228 | /* Another special case for "WSR.INTSET".... */ | |
2229 | if (is_write && !is_user && !strcasecmp ("interrupt", sr_name)) | |
2230 | sr_name = "intset"; | |
2231 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
80ca4e2c | 2232 | sprintf (new_opname, "%s.%s", *popname, sr_name); |
43cd72b9 BW |
2233 | free (*popname); |
2234 | *popname = new_opname; | |
2235 | ||
2236 | return 0; | |
2237 | } | |
2238 | ||
2239 | ||
2240 | static int | |
7fa3d080 | 2241 | xtensa_translate_old_userreg_ops (char **popname) |
43cd72b9 BW |
2242 | { |
2243 | xtensa_isa isa = xtensa_default_isa; | |
2244 | xtensa_sysreg sr; | |
2245 | char *opname, *new_opname; | |
2246 | const char *sr_name; | |
2247 | bfd_boolean has_underbar = FALSE; | |
2248 | ||
2249 | opname = *popname; | |
2250 | if (opname[0] == '_') | |
2251 | { | |
2252 | has_underbar = TRUE; | |
2253 | opname += 1; | |
2254 | } | |
2255 | ||
2256 | sr = xtensa_sysreg_lookup_name (isa, opname + 1); | |
2257 | if (sr != XTENSA_UNDEFINED) | |
2258 | { | |
2259 | /* The new default name ("nnn") is different from the old default | |
2260 | name ("URnnn"). The old default is handled below, and we don't | |
2261 | want to recognize [RW]nnn, so do nothing if the name is the (new) | |
2262 | default. */ | |
2263 | static char namebuf[10]; | |
2264 | sprintf (namebuf, "%d", xtensa_sysreg_number (isa, sr)); | |
2265 | if (strcmp (namebuf, opname + 1) == 0) | |
2266 | return 0; | |
2267 | } | |
2268 | else | |
2269 | { | |
2270 | offsetT val; | |
2271 | char *end; | |
2272 | ||
2273 | /* Only continue if the reg name is "URnnn". */ | |
2274 | if (opname[1] != 'u' || opname[2] != 'r') | |
2275 | return 0; | |
2276 | val = strtoul (opname + 3, &end, 10); | |
2277 | if (*end != '\0') | |
2278 | return 0; | |
2279 | ||
2280 | sr = xtensa_sysreg_lookup (isa, val, 1); | |
2281 | if (sr == XTENSA_UNDEFINED) | |
2282 | { | |
2283 | as_bad (_("invalid register number (%ld) for '%s'"), | |
dd49a749 | 2284 | (long) val, opname); |
43cd72b9 BW |
2285 | return -1; |
2286 | } | |
2287 | } | |
2288 | ||
2289 | /* Translate the opcode. */ | |
2290 | sr_name = xtensa_sysreg_name (isa, sr); | |
2291 | new_opname = (char *) xmalloc (strlen (sr_name) + 6); | |
2292 | sprintf (new_opname, "%s%cur.%s", (has_underbar ? "_" : ""), | |
2293 | opname[0], sr_name); | |
2294 | free (*popname); | |
2295 | *popname = new_opname; | |
2296 | ||
2297 | return 0; | |
2298 | } | |
2299 | ||
2300 | ||
2301 | static int | |
7fa3d080 BW |
2302 | xtensa_translate_zero_immed (char *old_op, |
2303 | char *new_op, | |
2304 | char **popname, | |
2305 | int *pnum_args, | |
2306 | char **arg_strings) | |
43cd72b9 BW |
2307 | { |
2308 | char *opname; | |
2309 | offsetT val; | |
2310 | ||
2311 | opname = *popname; | |
2312 | assert (opname[0] != '_'); | |
2313 | ||
2314 | if (strcmp (opname, old_op) != 0) | |
2315 | return 0; | |
e0001a05 | 2316 | |
43cd72b9 BW |
2317 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) |
2318 | return -1; | |
2319 | if (xg_arg_is_constant (arg_strings[1], &val) && val == 0) | |
2320 | { | |
2321 | xg_replace_opname (popname, new_op); | |
2322 | free (arg_strings[1]); | |
2323 | arg_strings[1] = arg_strings[2]; | |
2324 | arg_strings[2] = 0; | |
2325 | *pnum_args = 2; | |
e0001a05 NC |
2326 | } |
2327 | ||
2328 | return 0; | |
2329 | } | |
2330 | ||
2331 | ||
2332 | /* If the instruction is an idiom (i.e., a built-in macro), translate it. | |
2333 | Returns non-zero if an error was found. */ | |
2334 | ||
2335 | static int | |
7fa3d080 | 2336 | xg_translate_idioms (char **popname, int *pnum_args, char **arg_strings) |
e0001a05 NC |
2337 | { |
2338 | char *opname = *popname; | |
2339 | bfd_boolean has_underbar = FALSE; | |
2340 | ||
43cd72b9 BW |
2341 | if (cur_vinsn.inside_bundle) |
2342 | return 0; | |
2343 | ||
e0001a05 NC |
2344 | if (*opname == '_') |
2345 | { | |
2346 | has_underbar = TRUE; | |
2347 | opname += 1; | |
2348 | } | |
2349 | ||
2350 | if (strcmp (opname, "mov") == 0) | |
2351 | { | |
43cd72b9 | 2352 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2353 | xg_replace_opname (popname, "mov.n"); |
2354 | else | |
2355 | { | |
2356 | if (xg_check_num_args (pnum_args, 2, opname, arg_strings)) | |
2357 | return -1; | |
2358 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2359 | arg_strings[2] = (char *) xmalloc (strlen (arg_strings[1]) + 1); | |
2360 | strcpy (arg_strings[2], arg_strings[1]); | |
2361 | *pnum_args = 3; | |
2362 | } | |
2363 | return 0; | |
2364 | } | |
2365 | ||
2366 | if (strcmp (opname, "bbsi.l") == 0) | |
2367 | { | |
2368 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2369 | return -1; | |
2370 | xg_replace_opname (popname, (has_underbar ? "_bbsi" : "bbsi")); | |
2371 | if (target_big_endian) | |
2372 | xg_reverse_shift_count (&arg_strings[1]); | |
2373 | return 0; | |
2374 | } | |
2375 | ||
2376 | if (strcmp (opname, "bbci.l") == 0) | |
2377 | { | |
2378 | if (xg_check_num_args (pnum_args, 3, opname, arg_strings)) | |
2379 | return -1; | |
2380 | xg_replace_opname (popname, (has_underbar ? "_bbci" : "bbci")); | |
2381 | if (target_big_endian) | |
2382 | xg_reverse_shift_count (&arg_strings[1]); | |
2383 | return 0; | |
2384 | } | |
2385 | ||
43cd72b9 BW |
2386 | if (xtensa_nop_opcode == XTENSA_UNDEFINED |
2387 | && strcmp (opname, "nop") == 0) | |
e0001a05 | 2388 | { |
43cd72b9 | 2389 | if (use_transform () && !has_underbar && density_supported) |
e0001a05 NC |
2390 | xg_replace_opname (popname, "nop.n"); |
2391 | else | |
2392 | { | |
2393 | if (xg_check_num_args (pnum_args, 0, opname, arg_strings)) | |
2394 | return -1; | |
2395 | xg_replace_opname (popname, (has_underbar ? "_or" : "or")); | |
2396 | arg_strings[0] = (char *) xmalloc (3); | |
2397 | arg_strings[1] = (char *) xmalloc (3); | |
2398 | arg_strings[2] = (char *) xmalloc (3); | |
2399 | strcpy (arg_strings[0], "a1"); | |
2400 | strcpy (arg_strings[1], "a1"); | |
2401 | strcpy (arg_strings[2], "a1"); | |
2402 | *pnum_args = 3; | |
2403 | } | |
2404 | return 0; | |
2405 | } | |
2406 | ||
43cd72b9 BW |
2407 | /* Recognize [RW]UR and [RWX]SR. */ |
2408 | if ((((opname[0] == 'r' || opname[0] == 'w') | |
2409 | && (opname[1] == 'u' || opname[1] == 's')) | |
2410 | || (opname[0] == 'x' && opname[1] == 's')) | |
2411 | && opname[2] == 'r' | |
2412 | && opname[3] == '\0') | |
e0001a05 NC |
2413 | return xg_translate_sysreg_op (popname, pnum_args, arg_strings); |
2414 | ||
43cd72b9 BW |
2415 | /* Backward compatibility for RUR and WUR: Recognize [RW]UR<nnn> and |
2416 | [RW]<name> if <name> is the non-default name of a user register. */ | |
2417 | if ((opname[0] == 'r' || opname[0] == 'w') | |
2418 | && xtensa_opcode_lookup (xtensa_default_isa, opname) == XTENSA_UNDEFINED) | |
2419 | return xtensa_translate_old_userreg_ops (popname); | |
e0001a05 | 2420 | |
43cd72b9 BW |
2421 | /* Relax branches that don't allow comparisons against an immediate value |
2422 | of zero to the corresponding branches with implicit zero immediates. */ | |
2423 | if (!has_underbar && use_transform ()) | |
2424 | { | |
2425 | if (xtensa_translate_zero_immed ("bnei", "bnez", popname, | |
2426 | pnum_args, arg_strings)) | |
2427 | return -1; | |
e0001a05 | 2428 | |
43cd72b9 BW |
2429 | if (xtensa_translate_zero_immed ("beqi", "beqz", popname, |
2430 | pnum_args, arg_strings)) | |
2431 | return -1; | |
e0001a05 | 2432 | |
43cd72b9 BW |
2433 | if (xtensa_translate_zero_immed ("bgei", "bgez", popname, |
2434 | pnum_args, arg_strings)) | |
2435 | return -1; | |
e0001a05 | 2436 | |
43cd72b9 BW |
2437 | if (xtensa_translate_zero_immed ("blti", "bltz", popname, |
2438 | pnum_args, arg_strings)) | |
2439 | return -1; | |
2440 | } | |
e0001a05 | 2441 | |
43cd72b9 BW |
2442 | return 0; |
2443 | } | |
e0001a05 | 2444 | |
43cd72b9 BW |
2445 | \f |
2446 | /* Functions for dealing with the Xtensa ISA. */ | |
e0001a05 | 2447 | |
43cd72b9 BW |
2448 | /* Currently the assembler only allows us to use a single target per |
2449 | fragment. Because of this, only one operand for a given | |
2450 | instruction may be symbolic. If there is a PC-relative operand, | |
2451 | the last one is chosen. Otherwise, the result is the number of the | |
2452 | last immediate operand, and if there are none of those, we fail and | |
2453 | return -1. */ | |
e0001a05 | 2454 | |
7fa3d080 BW |
2455 | static int |
2456 | get_relaxable_immed (xtensa_opcode opcode) | |
43cd72b9 BW |
2457 | { |
2458 | int last_immed = -1; | |
2459 | int noperands, opi; | |
e0001a05 | 2460 | |
43cd72b9 BW |
2461 | if (opcode == XTENSA_UNDEFINED) |
2462 | return -1; | |
e0001a05 | 2463 | |
43cd72b9 BW |
2464 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, opcode); |
2465 | for (opi = noperands - 1; opi >= 0; opi--) | |
2466 | { | |
2467 | if (xtensa_operand_is_visible (xtensa_default_isa, opcode, opi) == 0) | |
2468 | continue; | |
2469 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, opi) == 1) | |
2470 | return opi; | |
2471 | if (last_immed == -1 | |
2472 | && xtensa_operand_is_register (xtensa_default_isa, opcode, opi) == 0) | |
2473 | last_immed = opi; | |
e0001a05 | 2474 | } |
43cd72b9 | 2475 | return last_immed; |
e0001a05 NC |
2476 | } |
2477 | ||
e0001a05 | 2478 | |
43cd72b9 | 2479 | static xtensa_opcode |
7fa3d080 | 2480 | get_opcode_from_buf (const char *buf, int slot) |
e0001a05 | 2481 | { |
43cd72b9 BW |
2482 | static xtensa_insnbuf insnbuf = NULL; |
2483 | static xtensa_insnbuf slotbuf = NULL; | |
2484 | xtensa_isa isa = xtensa_default_isa; | |
2485 | xtensa_format fmt; | |
2486 | ||
2487 | if (!insnbuf) | |
e0001a05 | 2488 | { |
43cd72b9 BW |
2489 | insnbuf = xtensa_insnbuf_alloc (isa); |
2490 | slotbuf = xtensa_insnbuf_alloc (isa); | |
e0001a05 | 2491 | } |
e0001a05 | 2492 | |
d77b99c9 | 2493 | xtensa_insnbuf_from_chars (isa, insnbuf, (const unsigned char *) buf, 0); |
43cd72b9 BW |
2494 | fmt = xtensa_format_decode (isa, insnbuf); |
2495 | if (fmt == XTENSA_UNDEFINED) | |
2496 | return XTENSA_UNDEFINED; | |
e0001a05 | 2497 | |
43cd72b9 BW |
2498 | if (slot >= xtensa_format_num_slots (isa, fmt)) |
2499 | return XTENSA_UNDEFINED; | |
e0001a05 | 2500 | |
43cd72b9 BW |
2501 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); |
2502 | return xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
e0001a05 NC |
2503 | } |
2504 | ||
2505 | ||
43cd72b9 | 2506 | #ifdef TENSILICA_DEBUG |
e0001a05 | 2507 | |
43cd72b9 | 2508 | /* For debugging, print out the mapping of opcode numbers to opcodes. */ |
e0001a05 | 2509 | |
7fa3d080 BW |
2510 | static void |
2511 | xtensa_print_insn_table (void) | |
43cd72b9 BW |
2512 | { |
2513 | int num_opcodes, num_operands; | |
2514 | xtensa_opcode opcode; | |
2515 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 | 2516 | |
43cd72b9 BW |
2517 | num_opcodes = xtensa_isa_num_opcodes (xtensa_default_isa); |
2518 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
e0001a05 | 2519 | { |
43cd72b9 BW |
2520 | int opn; |
2521 | fprintf (stderr, "%d: %s: ", opcode, xtensa_opcode_name (isa, opcode)); | |
2522 | num_operands = xtensa_opcode_num_operands (isa, opcode); | |
2523 | for (opn = 0; opn < num_operands; opn++) | |
2524 | { | |
2525 | if (xtensa_operand_is_visible (isa, opcode, opn) == 0) | |
2526 | continue; | |
2527 | if (xtensa_operand_is_register (isa, opcode, opn) == 1) | |
2528 | { | |
2529 | xtensa_regfile opnd_rf = | |
2530 | xtensa_operand_regfile (isa, opcode, opn); | |
2531 | fprintf (stderr, "%s ", xtensa_regfile_shortname (isa, opnd_rf)); | |
2532 | } | |
2533 | else if (xtensa_operand_is_PCrelative (isa, opcode, opn) == 1) | |
2534 | fputs ("[lLr] ", stderr); | |
2535 | else | |
2536 | fputs ("i ", stderr); | |
2537 | } | |
2538 | fprintf (stderr, "\n"); | |
e0001a05 | 2539 | } |
e0001a05 NC |
2540 | } |
2541 | ||
2542 | ||
43cd72b9 | 2543 | static void |
7fa3d080 | 2544 | print_vliw_insn (xtensa_insnbuf vbuf) |
e0001a05 | 2545 | { |
e0001a05 | 2546 | xtensa_isa isa = xtensa_default_isa; |
43cd72b9 BW |
2547 | xtensa_format f = xtensa_format_decode (isa, vbuf); |
2548 | xtensa_insnbuf sbuf = xtensa_insnbuf_alloc (isa); | |
2549 | int op; | |
e0001a05 | 2550 | |
43cd72b9 | 2551 | fprintf (stderr, "format = %d\n", f); |
e0001a05 | 2552 | |
43cd72b9 BW |
2553 | for (op = 0; op < xtensa_format_num_slots (isa, f); op++) |
2554 | { | |
2555 | xtensa_opcode opcode; | |
2556 | const char *opname; | |
2557 | int operands; | |
2558 | ||
2559 | xtensa_format_get_slot (isa, f, op, vbuf, sbuf); | |
2560 | opcode = xtensa_opcode_decode (isa, f, op, sbuf); | |
2561 | opname = xtensa_opcode_name (isa, opcode); | |
2562 | ||
2563 | fprintf (stderr, "op in slot %i is %s;\n", op, opname); | |
2564 | fprintf (stderr, " operands = "); | |
2565 | for (operands = 0; | |
2566 | operands < xtensa_opcode_num_operands (isa, opcode); | |
2567 | operands++) | |
2568 | { | |
2569 | unsigned int val; | |
2570 | if (xtensa_operand_is_visible (isa, opcode, operands) == 0) | |
2571 | continue; | |
2572 | xtensa_operand_get_field (isa, opcode, operands, f, op, sbuf, &val); | |
2573 | xtensa_operand_decode (isa, opcode, operands, &val); | |
2574 | fprintf (stderr, "%d ", val); | |
2575 | } | |
2576 | fprintf (stderr, "\n"); | |
2577 | } | |
2578 | xtensa_insnbuf_free (isa, sbuf); | |
e0001a05 NC |
2579 | } |
2580 | ||
43cd72b9 BW |
2581 | #endif /* TENSILICA_DEBUG */ |
2582 | ||
e0001a05 NC |
2583 | |
2584 | static bfd_boolean | |
7fa3d080 | 2585 | is_direct_call_opcode (xtensa_opcode opcode) |
e0001a05 | 2586 | { |
43cd72b9 BW |
2587 | xtensa_isa isa = xtensa_default_isa; |
2588 | int n, num_operands; | |
e0001a05 | 2589 | |
64b607e6 | 2590 | if (xtensa_opcode_is_call (isa, opcode) != 1) |
e0001a05 NC |
2591 | return FALSE; |
2592 | ||
43cd72b9 BW |
2593 | num_operands = xtensa_opcode_num_operands (isa, opcode); |
2594 | for (n = 0; n < num_operands; n++) | |
2595 | { | |
2596 | if (xtensa_operand_is_register (isa, opcode, n) == 0 | |
2597 | && xtensa_operand_is_PCrelative (isa, opcode, n) == 1) | |
2598 | return TRUE; | |
2599 | } | |
2600 | return FALSE; | |
e0001a05 NC |
2601 | } |
2602 | ||
2603 | ||
43cd72b9 BW |
2604 | /* Convert from BFD relocation type code to slot and operand number. |
2605 | Returns non-zero on failure. */ | |
e0001a05 | 2606 | |
43cd72b9 | 2607 | static int |
7fa3d080 | 2608 | decode_reloc (bfd_reloc_code_real_type reloc, int *slot, bfd_boolean *is_alt) |
e0001a05 | 2609 | { |
43cd72b9 BW |
2610 | if (reloc >= BFD_RELOC_XTENSA_SLOT0_OP |
2611 | && reloc <= BFD_RELOC_XTENSA_SLOT14_OP) | |
e0001a05 | 2612 | { |
43cd72b9 BW |
2613 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_OP; |
2614 | *is_alt = FALSE; | |
e0001a05 | 2615 | } |
43cd72b9 BW |
2616 | else if (reloc >= BFD_RELOC_XTENSA_SLOT0_ALT |
2617 | && reloc <= BFD_RELOC_XTENSA_SLOT14_ALT) | |
e0001a05 | 2618 | { |
43cd72b9 BW |
2619 | *slot = reloc - BFD_RELOC_XTENSA_SLOT0_ALT; |
2620 | *is_alt = TRUE; | |
e0001a05 | 2621 | } |
43cd72b9 BW |
2622 | else |
2623 | return -1; | |
2624 | ||
2625 | return 0; | |
e0001a05 NC |
2626 | } |
2627 | ||
2628 | ||
43cd72b9 BW |
2629 | /* Convert from slot number to BFD relocation type code for the |
2630 | standard PC-relative relocations. Return BFD_RELOC_NONE on | |
2631 | failure. */ | |
e0001a05 | 2632 | |
43cd72b9 | 2633 | static bfd_reloc_code_real_type |
7fa3d080 | 2634 | encode_reloc (int slot) |
e0001a05 | 2635 | { |
43cd72b9 BW |
2636 | if (slot < 0 || slot > 14) |
2637 | return BFD_RELOC_NONE; | |
2638 | ||
2639 | return BFD_RELOC_XTENSA_SLOT0_OP + slot; | |
e0001a05 NC |
2640 | } |
2641 | ||
2642 | ||
43cd72b9 BW |
2643 | /* Convert from slot numbers to BFD relocation type code for the |
2644 | "alternate" relocations. Return BFD_RELOC_NONE on failure. */ | |
e0001a05 | 2645 | |
43cd72b9 | 2646 | static bfd_reloc_code_real_type |
7fa3d080 | 2647 | encode_alt_reloc (int slot) |
e0001a05 | 2648 | { |
43cd72b9 BW |
2649 | if (slot < 0 || slot > 14) |
2650 | return BFD_RELOC_NONE; | |
2651 | ||
2652 | return BFD_RELOC_XTENSA_SLOT0_ALT + slot; | |
e0001a05 NC |
2653 | } |
2654 | ||
2655 | ||
2656 | static void | |
7fa3d080 BW |
2657 | xtensa_insnbuf_set_operand (xtensa_insnbuf slotbuf, |
2658 | xtensa_format fmt, | |
2659 | int slot, | |
2660 | xtensa_opcode opcode, | |
2661 | int operand, | |
2662 | uint32 value, | |
2663 | const char *file, | |
2664 | unsigned int line) | |
e0001a05 | 2665 | { |
e0001a05 NC |
2666 | uint32 valbuf = value; |
2667 | ||
43cd72b9 | 2668 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) |
e0001a05 | 2669 | { |
43cd72b9 BW |
2670 | if (xtensa_operand_is_PCrelative (xtensa_default_isa, opcode, operand) |
2671 | == 1) | |
2672 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2673 | _("operand %d of '%s' has out of range value '%u'"), |
2674 | operand + 1, | |
2675 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2676 | value); | |
43cd72b9 BW |
2677 | else |
2678 | as_bad_where ((char *) file, line, | |
d7c531cd BW |
2679 | _("operand %d of '%s' has invalid value '%u'"), |
2680 | operand + 1, | |
2681 | xtensa_opcode_name (xtensa_default_isa, opcode), | |
2682 | value); | |
43cd72b9 | 2683 | return; |
e0001a05 NC |
2684 | } |
2685 | ||
43cd72b9 BW |
2686 | xtensa_operand_set_field (xtensa_default_isa, opcode, operand, fmt, slot, |
2687 | slotbuf, valbuf); | |
e0001a05 NC |
2688 | } |
2689 | ||
2690 | ||
2691 | static uint32 | |
7fa3d080 BW |
2692 | xtensa_insnbuf_get_operand (xtensa_insnbuf slotbuf, |
2693 | xtensa_format fmt, | |
2694 | int slot, | |
2695 | xtensa_opcode opcode, | |
2696 | int opnum) | |
e0001a05 | 2697 | { |
43cd72b9 BW |
2698 | uint32 val = 0; |
2699 | (void) xtensa_operand_get_field (xtensa_default_isa, opcode, opnum, | |
2700 | fmt, slot, slotbuf, &val); | |
2701 | (void) xtensa_operand_decode (xtensa_default_isa, opcode, opnum, &val); | |
2702 | return val; | |
e0001a05 NC |
2703 | } |
2704 | ||
e0001a05 | 2705 | \f |
7fa3d080 | 2706 | /* Checks for rules from xtensa-relax tables. */ |
e0001a05 | 2707 | |
7fa3d080 BW |
2708 | /* The routine xg_instruction_matches_option_term must return TRUE |
2709 | when a given option term is true. The meaning of all of the option | |
2710 | terms is given interpretation by this function. This is needed when | |
2711 | an option depends on the state of a directive, but there are no such | |
2712 | options in use right now. */ | |
e0001a05 | 2713 | |
7fa3d080 BW |
2714 | static bfd_boolean |
2715 | xg_instruction_matches_option_term (TInsn *insn ATTRIBUTE_UNUSED, | |
2716 | const ReqOrOption *option) | |
e0001a05 | 2717 | { |
7fa3d080 BW |
2718 | if (strcmp (option->option_name, "realnop") == 0 |
2719 | || strncmp (option->option_name, "IsaUse", 6) == 0) | |
2720 | { | |
2721 | /* These conditions were evaluated statically when building the | |
2722 | relaxation table. There's no need to reevaluate them now. */ | |
2723 | return TRUE; | |
2724 | } | |
2725 | else | |
2726 | { | |
2727 | as_fatal (_("internal error: unknown option name '%s'"), | |
2728 | option->option_name); | |
2729 | } | |
e0001a05 NC |
2730 | } |
2731 | ||
2732 | ||
7fa3d080 BW |
2733 | static bfd_boolean |
2734 | xg_instruction_matches_or_options (TInsn *insn, | |
2735 | const ReqOrOptionList *or_option) | |
e0001a05 | 2736 | { |
7fa3d080 BW |
2737 | const ReqOrOption *option; |
2738 | /* Must match each of the AND terms. */ | |
2739 | for (option = or_option; option != NULL; option = option->next) | |
e0001a05 | 2740 | { |
7fa3d080 BW |
2741 | if (xg_instruction_matches_option_term (insn, option)) |
2742 | return TRUE; | |
e0001a05 | 2743 | } |
7fa3d080 | 2744 | return FALSE; |
e0001a05 NC |
2745 | } |
2746 | ||
2747 | ||
7fa3d080 BW |
2748 | static bfd_boolean |
2749 | xg_instruction_matches_options (TInsn *insn, const ReqOptionList *options) | |
e0001a05 | 2750 | { |
7fa3d080 BW |
2751 | const ReqOption *req_options; |
2752 | /* Must match each of the AND terms. */ | |
2753 | for (req_options = options; | |
2754 | req_options != NULL; | |
2755 | req_options = req_options->next) | |
e0001a05 | 2756 | { |
7fa3d080 BW |
2757 | /* Must match one of the OR clauses. */ |
2758 | if (!xg_instruction_matches_or_options (insn, | |
2759 | req_options->or_option_terms)) | |
2760 | return FALSE; | |
e0001a05 | 2761 | } |
7fa3d080 | 2762 | return TRUE; |
e0001a05 NC |
2763 | } |
2764 | ||
2765 | ||
7fa3d080 | 2766 | /* Return the transition rule that matches or NULL if none matches. */ |
e0001a05 | 2767 | |
7fa3d080 BW |
2768 | static bfd_boolean |
2769 | xg_instruction_matches_rule (TInsn *insn, TransitionRule *rule) | |
e0001a05 | 2770 | { |
7fa3d080 | 2771 | PreconditionList *condition_l; |
e0001a05 | 2772 | |
7fa3d080 BW |
2773 | if (rule->opcode != insn->opcode) |
2774 | return FALSE; | |
e0001a05 | 2775 | |
7fa3d080 BW |
2776 | for (condition_l = rule->conditions; |
2777 | condition_l != NULL; | |
2778 | condition_l = condition_l->next) | |
e0001a05 | 2779 | { |
7fa3d080 BW |
2780 | expressionS *exp1; |
2781 | expressionS *exp2; | |
2782 | Precondition *cond = condition_l->precond; | |
e0001a05 | 2783 | |
7fa3d080 | 2784 | switch (cond->typ) |
e0001a05 | 2785 | { |
7fa3d080 BW |
2786 | case OP_CONSTANT: |
2787 | /* The expression must be the constant. */ | |
2788 | assert (cond->op_num < insn->ntok); | |
2789 | exp1 = &insn->tok[cond->op_num]; | |
2790 | if (expr_is_const (exp1)) | |
2791 | { | |
2792 | switch (cond->cmp) | |
2793 | { | |
2794 | case OP_EQUAL: | |
2795 | if (get_expr_const (exp1) != cond->op_data) | |
2796 | return FALSE; | |
2797 | break; | |
2798 | case OP_NOTEQUAL: | |
2799 | if (get_expr_const (exp1) == cond->op_data) | |
2800 | return FALSE; | |
2801 | break; | |
2802 | default: | |
2803 | return FALSE; | |
2804 | } | |
2805 | } | |
2806 | else if (expr_is_register (exp1)) | |
2807 | { | |
2808 | switch (cond->cmp) | |
2809 | { | |
2810 | case OP_EQUAL: | |
2811 | if (get_expr_register (exp1) != cond->op_data) | |
2812 | return FALSE; | |
2813 | break; | |
2814 | case OP_NOTEQUAL: | |
2815 | if (get_expr_register (exp1) == cond->op_data) | |
2816 | return FALSE; | |
2817 | break; | |
2818 | default: | |
2819 | return FALSE; | |
2820 | } | |
2821 | } | |
2822 | else | |
2823 | return FALSE; | |
2824 | break; | |
2825 | ||
2826 | case OP_OPERAND: | |
2827 | assert (cond->op_num < insn->ntok); | |
2828 | assert (cond->op_data < insn->ntok); | |
2829 | exp1 = &insn->tok[cond->op_num]; | |
2830 | exp2 = &insn->tok[cond->op_data]; | |
2831 | ||
2832 | switch (cond->cmp) | |
2833 | { | |
2834 | case OP_EQUAL: | |
2835 | if (!expr_is_equal (exp1, exp2)) | |
2836 | return FALSE; | |
2837 | break; | |
2838 | case OP_NOTEQUAL: | |
2839 | if (expr_is_equal (exp1, exp2)) | |
2840 | return FALSE; | |
2841 | break; | |
2842 | } | |
2843 | break; | |
2844 | ||
2845 | case OP_LITERAL: | |
2846 | case OP_LABEL: | |
2847 | default: | |
2848 | return FALSE; | |
2849 | } | |
2850 | } | |
2851 | if (!xg_instruction_matches_options (insn, rule->options)) | |
2852 | return FALSE; | |
2853 | ||
2854 | return TRUE; | |
2855 | } | |
2856 | ||
2857 | ||
2858 | static int | |
2859 | transition_rule_cmp (const TransitionRule *a, const TransitionRule *b) | |
2860 | { | |
2861 | bfd_boolean a_greater = FALSE; | |
2862 | bfd_boolean b_greater = FALSE; | |
2863 | ||
2864 | ReqOptionList *l_a = a->options; | |
2865 | ReqOptionList *l_b = b->options; | |
2866 | ||
2867 | /* We only care if they both are the same except for | |
2868 | a const16 vs. an l32r. */ | |
2869 | ||
2870 | while (l_a && l_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2871 | { | |
2872 | ReqOrOptionList *l_or_a = l_a->or_option_terms; | |
2873 | ReqOrOptionList *l_or_b = l_b->or_option_terms; | |
2874 | while (l_or_a && l_or_b && ((l_a->next == NULL) == (l_b->next == NULL))) | |
2875 | { | |
2876 | if (l_or_a->is_true != l_or_b->is_true) | |
2877 | return 0; | |
2878 | if (strcmp (l_or_a->option_name, l_or_b->option_name) != 0) | |
2879 | { | |
2880 | /* This is the case we care about. */ | |
2881 | if (strcmp (l_or_a->option_name, "IsaUseConst16") == 0 | |
2882 | && strcmp (l_or_b->option_name, "IsaUseL32R") == 0) | |
2883 | { | |
2884 | if (prefer_const16) | |
2885 | a_greater = TRUE; | |
2886 | else | |
2887 | b_greater = TRUE; | |
2888 | } | |
2889 | else if (strcmp (l_or_a->option_name, "IsaUseL32R") == 0 | |
2890 | && strcmp (l_or_b->option_name, "IsaUseConst16") == 0) | |
2891 | { | |
2892 | if (prefer_const16) | |
2893 | b_greater = TRUE; | |
2894 | else | |
2895 | a_greater = TRUE; | |
2896 | } | |
2897 | else | |
2898 | return 0; | |
2899 | } | |
2900 | l_or_a = l_or_a->next; | |
2901 | l_or_b = l_or_b->next; | |
2902 | } | |
2903 | if (l_or_a || l_or_b) | |
2904 | return 0; | |
2905 | ||
2906 | l_a = l_a->next; | |
2907 | l_b = l_b->next; | |
2908 | } | |
2909 | if (l_a || l_b) | |
2910 | return 0; | |
2911 | ||
2912 | /* Incomparable if the substitution was used differently in two cases. */ | |
2913 | if (a_greater && b_greater) | |
2914 | return 0; | |
2915 | ||
2916 | if (b_greater) | |
2917 | return 1; | |
2918 | if (a_greater) | |
2919 | return -1; | |
2920 | ||
2921 | return 0; | |
2922 | } | |
2923 | ||
2924 | ||
2925 | static TransitionRule * | |
2926 | xg_instruction_match (TInsn *insn) | |
2927 | { | |
2928 | TransitionTable *table = xg_build_simplify_table (&transition_rule_cmp); | |
2929 | TransitionList *l; | |
2930 | assert (insn->opcode < table->num_opcodes); | |
2931 | ||
2932 | /* Walk through all of the possible transitions. */ | |
2933 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2934 | { | |
2935 | TransitionRule *rule = l->rule; | |
2936 | if (xg_instruction_matches_rule (insn, rule)) | |
2937 | return rule; | |
2938 | } | |
2939 | return NULL; | |
2940 | } | |
2941 | ||
2942 | \f | |
2943 | /* Various Other Internal Functions. */ | |
2944 | ||
2945 | static bfd_boolean | |
2946 | is_unique_insn_expansion (TransitionRule *r) | |
2947 | { | |
2948 | if (!r->to_instr || r->to_instr->next != NULL) | |
2949 | return FALSE; | |
2950 | if (r->to_instr->typ != INSTR_INSTR) | |
2951 | return FALSE; | |
2952 | return TRUE; | |
2953 | } | |
2954 | ||
2955 | ||
84b08ed9 BW |
2956 | /* Check if there is exactly one relaxation for INSN that converts it to |
2957 | another instruction of equal or larger size. If so, and if TARG is | |
2958 | non-null, go ahead and generate the relaxed instruction into TARG. If | |
2959 | NARROW_ONLY is true, then only consider relaxations that widen a narrow | |
2960 | instruction, i.e., ignore relaxations that convert to an instruction of | |
2961 | equal size. In some contexts where this function is used, only | |
c138bc38 | 2962 | a single widening is allowed and the NARROW_ONLY argument is used to |
84b08ed9 BW |
2963 | exclude cases like ADDI being "widened" to an ADDMI, which may |
2964 | later be relaxed to an ADDMI/ADDI pair. */ | |
7fa3d080 | 2965 | |
84b08ed9 BW |
2966 | bfd_boolean |
2967 | xg_is_single_relaxable_insn (TInsn *insn, TInsn *targ, bfd_boolean narrow_only) | |
7fa3d080 BW |
2968 | { |
2969 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
2970 | TransitionList *l; | |
84b08ed9 | 2971 | TransitionRule *match = 0; |
7fa3d080 | 2972 | |
7fa3d080 BW |
2973 | assert (insn->insn_type == ITYPE_INSN); |
2974 | assert (insn->opcode < table->num_opcodes); | |
2975 | ||
2976 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
2977 | { | |
2978 | TransitionRule *rule = l->rule; | |
2979 | ||
2980 | if (xg_instruction_matches_rule (insn, rule) | |
84b08ed9 BW |
2981 | && is_unique_insn_expansion (rule) |
2982 | && (xg_get_single_size (insn->opcode) + (narrow_only ? 1 : 0) | |
2983 | <= xg_get_single_size (rule->to_instr->opcode))) | |
7fa3d080 | 2984 | { |
84b08ed9 BW |
2985 | if (match) |
2986 | return FALSE; | |
2987 | match = rule; | |
7fa3d080 BW |
2988 | } |
2989 | } | |
84b08ed9 BW |
2990 | if (!match) |
2991 | return FALSE; | |
2992 | ||
2993 | if (targ) | |
2994 | xg_build_to_insn (targ, insn, match->to_instr); | |
2995 | return TRUE; | |
7fa3d080 BW |
2996 | } |
2997 | ||
2998 | ||
2999 | /* Return the maximum number of bytes this opcode can expand to. */ | |
3000 | ||
3001 | static int | |
3002 | xg_get_max_insn_widen_size (xtensa_opcode opcode) | |
3003 | { | |
3004 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3005 | TransitionList *l; | |
3006 | int max_size = xg_get_single_size (opcode); | |
3007 | ||
3008 | assert (opcode < table->num_opcodes); | |
3009 | ||
3010 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3011 | { | |
3012 | TransitionRule *rule = l->rule; | |
3013 | BuildInstr *build_list; | |
3014 | int this_size = 0; | |
3015 | ||
3016 | if (!rule) | |
3017 | continue; | |
3018 | build_list = rule->to_instr; | |
3019 | if (is_unique_insn_expansion (rule)) | |
3020 | { | |
3021 | assert (build_list->typ == INSTR_INSTR); | |
3022 | this_size = xg_get_max_insn_widen_size (build_list->opcode); | |
3023 | } | |
3024 | else | |
3025 | for (; build_list != NULL; build_list = build_list->next) | |
3026 | { | |
3027 | switch (build_list->typ) | |
3028 | { | |
3029 | case INSTR_INSTR: | |
3030 | this_size += xg_get_single_size (build_list->opcode); | |
3031 | break; | |
3032 | case INSTR_LITERAL_DEF: | |
3033 | case INSTR_LABEL_DEF: | |
e0001a05 NC |
3034 | default: |
3035 | break; | |
3036 | } | |
3037 | } | |
3038 | if (this_size > max_size) | |
3039 | max_size = this_size; | |
3040 | } | |
3041 | return max_size; | |
3042 | } | |
3043 | ||
3044 | ||
3045 | /* Return the maximum number of literal bytes this opcode can generate. */ | |
3046 | ||
7fa3d080 BW |
3047 | static int |
3048 | xg_get_max_insn_widen_literal_size (xtensa_opcode opcode) | |
e0001a05 | 3049 | { |
43cd72b9 | 3050 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3051 | TransitionList *l; |
3052 | int max_size = 0; | |
3053 | ||
3054 | assert (opcode < table->num_opcodes); | |
3055 | ||
3056 | for (l = table->table[opcode]; l != NULL; l = l->next) | |
3057 | { | |
3058 | TransitionRule *rule = l->rule; | |
3059 | BuildInstr *build_list; | |
3060 | int this_size = 0; | |
3061 | ||
3062 | if (!rule) | |
3063 | continue; | |
3064 | build_list = rule->to_instr; | |
3065 | if (is_unique_insn_expansion (rule)) | |
3066 | { | |
3067 | assert (build_list->typ == INSTR_INSTR); | |
3068 | this_size = xg_get_max_insn_widen_literal_size (build_list->opcode); | |
3069 | } | |
3070 | else | |
3071 | for (; build_list != NULL; build_list = build_list->next) | |
3072 | { | |
3073 | switch (build_list->typ) | |
3074 | { | |
3075 | case INSTR_LITERAL_DEF: | |
43cd72b9 | 3076 | /* Hard-coded 4-byte literal. */ |
e0001a05 NC |
3077 | this_size += 4; |
3078 | break; | |
3079 | case INSTR_INSTR: | |
3080 | case INSTR_LABEL_DEF: | |
3081 | default: | |
3082 | break; | |
3083 | } | |
3084 | } | |
3085 | if (this_size > max_size) | |
3086 | max_size = this_size; | |
3087 | } | |
3088 | return max_size; | |
3089 | } | |
3090 | ||
3091 | ||
7fa3d080 BW |
3092 | static bfd_boolean |
3093 | xg_is_relaxable_insn (TInsn *insn, int lateral_steps) | |
3094 | { | |
3095 | int steps_taken = 0; | |
3096 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); | |
3097 | TransitionList *l; | |
3098 | ||
3099 | assert (insn->insn_type == ITYPE_INSN); | |
3100 | assert (insn->opcode < table->num_opcodes); | |
3101 | ||
3102 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3103 | { | |
3104 | TransitionRule *rule = l->rule; | |
3105 | ||
3106 | if (xg_instruction_matches_rule (insn, rule)) | |
3107 | { | |
3108 | if (steps_taken == lateral_steps) | |
3109 | return TRUE; | |
3110 | steps_taken++; | |
3111 | } | |
3112 | } | |
3113 | return FALSE; | |
3114 | } | |
3115 | ||
3116 | ||
3117 | static symbolS * | |
3118 | get_special_literal_symbol (void) | |
3119 | { | |
3120 | static symbolS *sym = NULL; | |
3121 | ||
3122 | if (sym == NULL) | |
3123 | sym = symbol_find_or_make ("SPECIAL_LITERAL0\001"); | |
3124 | return sym; | |
3125 | } | |
3126 | ||
3127 | ||
3128 | static symbolS * | |
3129 | get_special_label_symbol (void) | |
3130 | { | |
3131 | static symbolS *sym = NULL; | |
3132 | ||
3133 | if (sym == NULL) | |
3134 | sym = symbol_find_or_make ("SPECIAL_LABEL0\001"); | |
3135 | return sym; | |
3136 | } | |
3137 | ||
3138 | ||
3139 | static bfd_boolean | |
3140 | xg_valid_literal_expression (const expressionS *exp) | |
3141 | { | |
3142 | switch (exp->X_op) | |
3143 | { | |
3144 | case O_constant: | |
3145 | case O_symbol: | |
3146 | case O_big: | |
3147 | case O_uminus: | |
3148 | case O_subtract: | |
3149 | case O_pltrel: | |
3150 | return TRUE; | |
3151 | default: | |
3152 | return FALSE; | |
3153 | } | |
3154 | } | |
3155 | ||
3156 | ||
3157 | /* This will check to see if the value can be converted into the | |
3158 | operand type. It will return TRUE if it does not fit. */ | |
3159 | ||
3160 | static bfd_boolean | |
3161 | xg_check_operand (int32 value, xtensa_opcode opcode, int operand) | |
3162 | { | |
3163 | uint32 valbuf = value; | |
3164 | if (xtensa_operand_encode (xtensa_default_isa, opcode, operand, &valbuf)) | |
3165 | return TRUE; | |
3166 | return FALSE; | |
3167 | } | |
3168 | ||
3169 | ||
3170 | /* Assumes: All immeds are constants. Check that all constants fit | |
3171 | into their immeds; return FALSE if not. */ | |
3172 | ||
3173 | static bfd_boolean | |
3174 | xg_immeds_fit (const TInsn *insn) | |
3175 | { | |
3176 | xtensa_isa isa = xtensa_default_isa; | |
3177 | int i; | |
3178 | ||
3179 | int n = insn->ntok; | |
3180 | assert (insn->insn_type == ITYPE_INSN); | |
3181 | for (i = 0; i < n; ++i) | |
3182 | { | |
3183 | const expressionS *expr = &insn->tok[i]; | |
3184 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3185 | continue; | |
3186 | ||
3187 | switch (expr->X_op) | |
3188 | { | |
3189 | case O_register: | |
3190 | case O_constant: | |
3191 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3192 | return FALSE; | |
3193 | break; | |
3194 | ||
3195 | default: | |
3196 | /* The symbol should have a fixup associated with it. */ | |
3197 | assert (FALSE); | |
3198 | break; | |
3199 | } | |
3200 | } | |
3201 | return TRUE; | |
3202 | } | |
3203 | ||
3204 | ||
3205 | /* This should only be called after we have an initial | |
3206 | estimate of the addresses. */ | |
3207 | ||
3208 | static bfd_boolean | |
3209 | xg_symbolic_immeds_fit (const TInsn *insn, | |
3210 | segT pc_seg, | |
3211 | fragS *pc_frag, | |
3212 | offsetT pc_offset, | |
3213 | long stretch) | |
e0001a05 | 3214 | { |
7fa3d080 BW |
3215 | xtensa_isa isa = xtensa_default_isa; |
3216 | symbolS *symbolP; | |
3217 | fragS *sym_frag; | |
3218 | offsetT target, pc; | |
3219 | uint32 new_offset; | |
3220 | int i; | |
3221 | int n = insn->ntok; | |
e0001a05 NC |
3222 | |
3223 | assert (insn->insn_type == ITYPE_INSN); | |
e0001a05 | 3224 | |
7fa3d080 | 3225 | for (i = 0; i < n; ++i) |
e0001a05 | 3226 | { |
7fa3d080 BW |
3227 | const expressionS *expr = &insn->tok[i]; |
3228 | if (xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
3229 | continue; | |
e0001a05 | 3230 | |
7fa3d080 | 3231 | switch (expr->X_op) |
e0001a05 | 3232 | { |
7fa3d080 BW |
3233 | case O_register: |
3234 | case O_constant: | |
3235 | if (xg_check_operand (expr->X_add_number, insn->opcode, i)) | |
3236 | return FALSE; | |
3237 | break; | |
e0001a05 | 3238 | |
7fa3d080 BW |
3239 | case O_lo16: |
3240 | case O_hi16: | |
3241 | /* Check for the worst case. */ | |
3242 | if (xg_check_operand (0xffff, insn->opcode, i)) | |
3243 | return FALSE; | |
3244 | break; | |
e0001a05 | 3245 | |
7fa3d080 | 3246 | case O_symbol: |
7c834684 | 3247 | /* We only allow symbols for PC-relative references. |
7fa3d080 | 3248 | If pc_frag == 0, then we don't have frag locations yet. */ |
7c834684 BW |
3249 | if (pc_frag == 0 |
3250 | || xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 0) | |
7fa3d080 | 3251 | return FALSE; |
e0001a05 | 3252 | |
7c834684 BW |
3253 | /* If it is a weak symbol, then assume it won't reach. */ |
3254 | if (S_IS_WEAK (expr->X_add_symbol)) | |
7fa3d080 | 3255 | return FALSE; |
e0001a05 | 3256 | |
7c834684 BW |
3257 | if (is_direct_call_opcode (insn->opcode) |
3258 | && ! pc_frag->tc_frag_data.use_longcalls) | |
3259 | { | |
3260 | /* If callee is undefined or in a different segment, be | |
3261 | optimistic and assume it will be in range. */ | |
3262 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
3263 | return TRUE; | |
3264 | } | |
3265 | ||
3266 | /* Only references within a segment can be known to fit in the | |
3267 | operands at assembly time. */ | |
3268 | if (S_GET_SEGMENT (expr->X_add_symbol) != pc_seg) | |
7fa3d080 | 3269 | return FALSE; |
e0001a05 | 3270 | |
7fa3d080 BW |
3271 | symbolP = expr->X_add_symbol; |
3272 | sym_frag = symbol_get_frag (symbolP); | |
3273 | target = S_GET_VALUE (symbolP) + expr->X_add_number; | |
3274 | pc = pc_frag->fr_address + pc_offset; | |
e0001a05 | 3275 | |
7fa3d080 BW |
3276 | /* If frag has yet to be reached on this pass, assume it |
3277 | will move by STRETCH just as we did. If this is not so, | |
3278 | it will be because some frag between grows, and that will | |
3279 | force another pass. Beware zero-length frags. There | |
3280 | should be a faster way to do this. */ | |
3281 | ||
3282 | if (stretch != 0 | |
3283 | && sym_frag->relax_marker != pc_frag->relax_marker | |
3284 | && S_GET_SEGMENT (symbolP) == pc_seg) | |
3285 | { | |
3286 | target += stretch; | |
3287 | } | |
c138bc38 | 3288 | |
7fa3d080 BW |
3289 | new_offset = target; |
3290 | xtensa_operand_do_reloc (isa, insn->opcode, i, &new_offset, pc); | |
3291 | if (xg_check_operand (new_offset, insn->opcode, i)) | |
3292 | return FALSE; | |
3293 | break; | |
3294 | ||
3295 | default: | |
3296 | /* The symbol should have a fixup associated with it. */ | |
3297 | return FALSE; | |
3298 | } | |
3299 | } | |
3300 | ||
3301 | return TRUE; | |
e0001a05 NC |
3302 | } |
3303 | ||
3304 | ||
43cd72b9 | 3305 | /* Return TRUE on success. */ |
e0001a05 | 3306 | |
7fa3d080 BW |
3307 | static bfd_boolean |
3308 | xg_build_to_insn (TInsn *targ, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3309 | { |
3310 | BuildOp *op; | |
3311 | symbolS *sym; | |
3312 | ||
3313 | memset (targ, 0, sizeof (TInsn)); | |
7c430684 | 3314 | targ->linenum = insn->linenum; |
e0001a05 NC |
3315 | switch (bi->typ) |
3316 | { | |
3317 | case INSTR_INSTR: | |
3318 | op = bi->ops; | |
3319 | targ->opcode = bi->opcode; | |
3320 | targ->insn_type = ITYPE_INSN; | |
3321 | targ->is_specific_opcode = FALSE; | |
3322 | ||
3323 | for (; op != NULL; op = op->next) | |
3324 | { | |
3325 | int op_num = op->op_num; | |
3326 | int op_data = op->op_data; | |
3327 | ||
3328 | assert (op->op_num < MAX_INSN_ARGS); | |
3329 | ||
3330 | if (targ->ntok <= op_num) | |
3331 | targ->ntok = op_num + 1; | |
3332 | ||
3333 | switch (op->typ) | |
3334 | { | |
3335 | case OP_CONSTANT: | |
3336 | set_expr_const (&targ->tok[op_num], op_data); | |
3337 | break; | |
3338 | case OP_OPERAND: | |
3339 | assert (op_data < insn->ntok); | |
3340 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3341 | break; | |
3342 | case OP_LITERAL: | |
3343 | sym = get_special_literal_symbol (); | |
3344 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3345 | break; | |
3346 | case OP_LABEL: | |
3347 | sym = get_special_label_symbol (); | |
3348 | set_expr_symbol_offset (&targ->tok[op_num], sym, 0); | |
3349 | break; | |
43cd72b9 BW |
3350 | case OP_OPERAND_HI16U: |
3351 | case OP_OPERAND_LOW16U: | |
3352 | assert (op_data < insn->ntok); | |
3353 | if (expr_is_const (&insn->tok[op_data])) | |
3354 | { | |
3355 | long val; | |
3356 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3357 | val = xg_apply_userdef_op_fn (op->typ, | |
3358 | targ->tok[op_num]. | |
3359 | X_add_number); | |
3360 | targ->tok[op_num].X_add_number = val; | |
3361 | } | |
3362 | else | |
3363 | { | |
3364 | /* For const16 we can create relocations for these. */ | |
3365 | if (targ->opcode == XTENSA_UNDEFINED | |
3366 | || (targ->opcode != xtensa_const16_opcode)) | |
3367 | return FALSE; | |
3368 | assert (op_data < insn->ntok); | |
3369 | /* Need to build a O_lo16 or O_hi16. */ | |
3370 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3371 | if (targ->tok[op_num].X_op == O_symbol) | |
3372 | { | |
3373 | if (op->typ == OP_OPERAND_HI16U) | |
3374 | targ->tok[op_num].X_op = O_hi16; | |
3375 | else if (op->typ == OP_OPERAND_LOW16U) | |
3376 | targ->tok[op_num].X_op = O_lo16; | |
3377 | else | |
3378 | return FALSE; | |
3379 | } | |
3380 | } | |
3381 | break; | |
e0001a05 NC |
3382 | default: |
3383 | /* currently handles: | |
3384 | OP_OPERAND_LOW8 | |
3385 | OP_OPERAND_HI24S | |
3386 | OP_OPERAND_F32MINUS */ | |
3387 | if (xg_has_userdef_op_fn (op->typ)) | |
3388 | { | |
3389 | assert (op_data < insn->ntok); | |
3390 | if (expr_is_const (&insn->tok[op_data])) | |
3391 | { | |
3392 | long val; | |
3393 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); | |
3394 | val = xg_apply_userdef_op_fn (op->typ, | |
3395 | targ->tok[op_num]. | |
3396 | X_add_number); | |
3397 | targ->tok[op_num].X_add_number = val; | |
3398 | } | |
3399 | else | |
3400 | return FALSE; /* We cannot use a relocation for this. */ | |
3401 | break; | |
3402 | } | |
3403 | assert (0); | |
3404 | break; | |
3405 | } | |
3406 | } | |
3407 | break; | |
3408 | ||
3409 | case INSTR_LITERAL_DEF: | |
3410 | op = bi->ops; | |
3411 | targ->opcode = XTENSA_UNDEFINED; | |
3412 | targ->insn_type = ITYPE_LITERAL; | |
3413 | targ->is_specific_opcode = FALSE; | |
3414 | for (; op != NULL; op = op->next) | |
3415 | { | |
3416 | int op_num = op->op_num; | |
3417 | int op_data = op->op_data; | |
3418 | assert (op->op_num < MAX_INSN_ARGS); | |
3419 | ||
3420 | if (targ->ntok <= op_num) | |
3421 | targ->ntok = op_num + 1; | |
3422 | ||
3423 | switch (op->typ) | |
3424 | { | |
3425 | case OP_OPERAND: | |
3426 | assert (op_data < insn->ntok); | |
43cd72b9 BW |
3427 | /* We can only pass resolvable literals through. */ |
3428 | if (!xg_valid_literal_expression (&insn->tok[op_data])) | |
3429 | return FALSE; | |
e0001a05 NC |
3430 | copy_expr (&targ->tok[op_num], &insn->tok[op_data]); |
3431 | break; | |
3432 | case OP_LITERAL: | |
3433 | case OP_CONSTANT: | |
3434 | case OP_LABEL: | |
3435 | default: | |
3436 | assert (0); | |
3437 | break; | |
3438 | } | |
3439 | } | |
3440 | break; | |
3441 | ||
3442 | case INSTR_LABEL_DEF: | |
3443 | op = bi->ops; | |
3444 | targ->opcode = XTENSA_UNDEFINED; | |
3445 | targ->insn_type = ITYPE_LABEL; | |
3446 | targ->is_specific_opcode = FALSE; | |
43cd72b9 | 3447 | /* Literal with no ops is a label? */ |
e0001a05 NC |
3448 | assert (op == NULL); |
3449 | break; | |
3450 | ||
3451 | default: | |
3452 | assert (0); | |
3453 | } | |
3454 | ||
3455 | return TRUE; | |
3456 | } | |
3457 | ||
3458 | ||
43cd72b9 | 3459 | /* Return TRUE on success. */ |
e0001a05 | 3460 | |
7fa3d080 BW |
3461 | static bfd_boolean |
3462 | xg_build_to_stack (IStack *istack, TInsn *insn, BuildInstr *bi) | |
e0001a05 NC |
3463 | { |
3464 | for (; bi != NULL; bi = bi->next) | |
3465 | { | |
3466 | TInsn *next_insn = istack_push_space (istack); | |
3467 | ||
3468 | if (!xg_build_to_insn (next_insn, insn, bi)) | |
3469 | return FALSE; | |
3470 | } | |
3471 | return TRUE; | |
3472 | } | |
3473 | ||
3474 | ||
43cd72b9 | 3475 | /* Return TRUE on valid expansion. */ |
e0001a05 | 3476 | |
7fa3d080 BW |
3477 | static bfd_boolean |
3478 | xg_expand_to_stack (IStack *istack, TInsn *insn, int lateral_steps) | |
e0001a05 NC |
3479 | { |
3480 | int stack_size = istack->ninsn; | |
3481 | int steps_taken = 0; | |
43cd72b9 | 3482 | TransitionTable *table = xg_build_widen_table (&transition_rule_cmp); |
e0001a05 NC |
3483 | TransitionList *l; |
3484 | ||
3485 | assert (insn->insn_type == ITYPE_INSN); | |
3486 | assert (insn->opcode < table->num_opcodes); | |
3487 | ||
3488 | for (l = table->table[insn->opcode]; l != NULL; l = l->next) | |
3489 | { | |
3490 | TransitionRule *rule = l->rule; | |
3491 | ||
3492 | if (xg_instruction_matches_rule (insn, rule)) | |
3493 | { | |
3494 | if (lateral_steps == steps_taken) | |
3495 | { | |
3496 | int i; | |
3497 | ||
3498 | /* This is it. Expand the rule to the stack. */ | |
3499 | if (!xg_build_to_stack (istack, insn, rule->to_instr)) | |
3500 | return FALSE; | |
3501 | ||
3502 | /* Check to see if it fits. */ | |
3503 | for (i = stack_size; i < istack->ninsn; i++) | |
3504 | { | |
3505 | TInsn *insn = &istack->insn[i]; | |
3506 | ||
3507 | if (insn->insn_type == ITYPE_INSN | |
3508 | && !tinsn_has_symbolic_operands (insn) | |
3509 | && !xg_immeds_fit (insn)) | |
3510 | { | |
3511 | istack->ninsn = stack_size; | |
3512 | return FALSE; | |
3513 | } | |
3514 | } | |
3515 | return TRUE; | |
3516 | } | |
3517 | steps_taken++; | |
3518 | } | |
3519 | } | |
3520 | return FALSE; | |
3521 | } | |
3522 | ||
43cd72b9 | 3523 | \f |
43cd72b9 BW |
3524 | /* Relax the assembly instruction at least "min_steps". |
3525 | Return the number of steps taken. */ | |
e0001a05 | 3526 | |
7fa3d080 BW |
3527 | static int |
3528 | xg_assembly_relax (IStack *istack, | |
3529 | TInsn *insn, | |
3530 | segT pc_seg, | |
3531 | fragS *pc_frag, /* if pc_frag == 0, not pc-relative */ | |
3532 | offsetT pc_offset, /* offset in fragment */ | |
3533 | int min_steps, /* minimum conversion steps */ | |
3534 | long stretch) /* number of bytes stretched so far */ | |
e0001a05 NC |
3535 | { |
3536 | int steps_taken = 0; | |
3537 | ||
3538 | /* assert (has no symbolic operands) | |
3539 | Some of its immeds don't fit. | |
3540 | Try to build a relaxed version. | |
3541 | This may go through a couple of stages | |
3542 | of single instruction transformations before | |
3543 | we get there. */ | |
3544 | ||
3545 | TInsn single_target; | |
3546 | TInsn current_insn; | |
3547 | int lateral_steps = 0; | |
3548 | int istack_size = istack->ninsn; | |
3549 | ||
3550 | if (xg_symbolic_immeds_fit (insn, pc_seg, pc_frag, pc_offset, stretch) | |
3551 | && steps_taken >= min_steps) | |
3552 | { | |
3553 | istack_push (istack, insn); | |
3554 | return steps_taken; | |
3555 | } | |
43cd72b9 | 3556 | current_insn = *insn; |
e0001a05 | 3557 | |
7c834684 | 3558 | /* Walk through all of the single instruction expansions. */ |
84b08ed9 | 3559 | while (xg_is_single_relaxable_insn (¤t_insn, &single_target, FALSE)) |
e0001a05 | 3560 | { |
21af2bbd | 3561 | steps_taken++; |
e0001a05 NC |
3562 | if (xg_symbolic_immeds_fit (&single_target, pc_seg, pc_frag, pc_offset, |
3563 | stretch)) | |
3564 | { | |
e0001a05 NC |
3565 | if (steps_taken >= min_steps) |
3566 | { | |
3567 | istack_push (istack, &single_target); | |
3568 | return steps_taken; | |
3569 | } | |
3570 | } | |
43cd72b9 | 3571 | current_insn = single_target; |
e0001a05 NC |
3572 | } |
3573 | ||
3574 | /* Now check for a multi-instruction expansion. */ | |
3575 | while (xg_is_relaxable_insn (¤t_insn, lateral_steps)) | |
3576 | { | |
3577 | if (xg_symbolic_immeds_fit (¤t_insn, pc_seg, pc_frag, pc_offset, | |
3578 | stretch)) | |
3579 | { | |
3580 | if (steps_taken >= min_steps) | |
3581 | { | |
3582 | istack_push (istack, ¤t_insn); | |
3583 | return steps_taken; | |
3584 | } | |
3585 | } | |
3586 | steps_taken++; | |
3587 | if (xg_expand_to_stack (istack, ¤t_insn, lateral_steps)) | |
3588 | { | |
3589 | if (steps_taken >= min_steps) | |
3590 | return steps_taken; | |
3591 | } | |
3592 | lateral_steps++; | |
3593 | istack->ninsn = istack_size; | |
3594 | } | |
3595 | ||
3596 | /* It's not going to work -- use the original. */ | |
3597 | istack_push (istack, insn); | |
3598 | return steps_taken; | |
3599 | } | |
3600 | ||
3601 | ||
3602 | static void | |
7fa3d080 | 3603 | xg_force_frag_space (int size) |
e0001a05 NC |
3604 | { |
3605 | /* This may have the side effect of creating a new fragment for the | |
3606 | space to go into. I just do not like the name of the "frag" | |
3607 | functions. */ | |
3608 | frag_grow (size); | |
3609 | } | |
3610 | ||
3611 | ||
7fa3d080 BW |
3612 | static void |
3613 | xg_finish_frag (char *last_insn, | |
3614 | enum xtensa_relax_statesE frag_state, | |
3615 | enum xtensa_relax_statesE slot0_state, | |
3616 | int max_growth, | |
3617 | bfd_boolean is_insn) | |
e0001a05 NC |
3618 | { |
3619 | /* Finish off this fragment so that it has at LEAST the desired | |
3620 | max_growth. If it doesn't fit in this fragment, close this one | |
3621 | and start a new one. In either case, return a pointer to the | |
3622 | beginning of the growth area. */ | |
3623 | ||
3624 | fragS *old_frag; | |
43cd72b9 | 3625 | |
e0001a05 NC |
3626 | xg_force_frag_space (max_growth); |
3627 | ||
3628 | old_frag = frag_now; | |
3629 | ||
3630 | frag_now->fr_opcode = last_insn; | |
3631 | if (is_insn) | |
3632 | frag_now->tc_frag_data.is_insn = TRUE; | |
3633 | ||
3634 | frag_var (rs_machine_dependent, max_growth, max_growth, | |
43cd72b9 BW |
3635 | frag_state, frag_now->fr_symbol, frag_now->fr_offset, last_insn); |
3636 | ||
3637 | old_frag->tc_frag_data.slot_subtypes[0] = slot0_state; | |
3638 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
3639 | |
3640 | /* Just to make sure that we did not split it up. */ | |
3641 | assert (old_frag->fr_next == frag_now); | |
3642 | } | |
3643 | ||
3644 | ||
7fa3d080 BW |
3645 | /* Return TRUE if the target frag is one of the next non-empty frags. */ |
3646 | ||
3647 | static bfd_boolean | |
3648 | is_next_frag_target (const fragS *fragP, const fragS *target) | |
3649 | { | |
3650 | if (fragP == NULL) | |
3651 | return FALSE; | |
3652 | ||
3653 | for (; fragP; fragP = fragP->fr_next) | |
3654 | { | |
3655 | if (fragP == target) | |
3656 | return TRUE; | |
3657 | if (fragP->fr_fix != 0) | |
3658 | return FALSE; | |
3659 | if (fragP->fr_type == rs_fill && fragP->fr_offset != 0) | |
3660 | return FALSE; | |
3661 | if ((fragP->fr_type == rs_align || fragP->fr_type == rs_align_code) | |
3662 | && ((fragP->fr_address % (1 << fragP->fr_offset)) != 0)) | |
3663 | return FALSE; | |
3664 | if (fragP->fr_type == rs_space) | |
3665 | return FALSE; | |
3666 | } | |
3667 | return FALSE; | |
3668 | } | |
3669 | ||
3670 | ||
e0001a05 | 3671 | static bfd_boolean |
7fa3d080 | 3672 | is_branch_jmp_to_next (TInsn *insn, fragS *fragP) |
e0001a05 NC |
3673 | { |
3674 | xtensa_isa isa = xtensa_default_isa; | |
3675 | int i; | |
43cd72b9 | 3676 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
3677 | int target_op = -1; |
3678 | symbolS *sym; | |
3679 | fragS *target_frag; | |
3680 | ||
64b607e6 BW |
3681 | if (xtensa_opcode_is_branch (isa, insn->opcode) != 1 |
3682 | && xtensa_opcode_is_jump (isa, insn->opcode) != 1) | |
e0001a05 NC |
3683 | return FALSE; |
3684 | ||
3685 | for (i = 0; i < num_ops; i++) | |
3686 | { | |
43cd72b9 | 3687 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1) |
e0001a05 NC |
3688 | { |
3689 | target_op = i; | |
3690 | break; | |
3691 | } | |
3692 | } | |
3693 | if (target_op == -1) | |
3694 | return FALSE; | |
3695 | ||
3696 | if (insn->ntok <= target_op) | |
3697 | return FALSE; | |
3698 | ||
3699 | if (insn->tok[target_op].X_op != O_symbol) | |
3700 | return FALSE; | |
3701 | ||
3702 | sym = insn->tok[target_op].X_add_symbol; | |
3703 | if (sym == NULL) | |
3704 | return FALSE; | |
3705 | ||
3706 | if (insn->tok[target_op].X_add_number != 0) | |
3707 | return FALSE; | |
3708 | ||
3709 | target_frag = symbol_get_frag (sym); | |
3710 | if (target_frag == NULL) | |
3711 | return FALSE; | |
3712 | ||
c138bc38 | 3713 | if (is_next_frag_target (fragP->fr_next, target_frag) |
e0001a05 NC |
3714 | && S_GET_VALUE (sym) == target_frag->fr_address) |
3715 | return TRUE; | |
3716 | ||
3717 | return FALSE; | |
3718 | } | |
3719 | ||
3720 | ||
3721 | static void | |
7fa3d080 | 3722 | xg_add_branch_and_loop_targets (TInsn *insn) |
e0001a05 NC |
3723 | { |
3724 | xtensa_isa isa = xtensa_default_isa; | |
7fa3d080 | 3725 | int num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
43cd72b9 | 3726 | |
7fa3d080 BW |
3727 | if (xtensa_opcode_is_loop (isa, insn->opcode) == 1) |
3728 | { | |
3729 | int i = 1; | |
3730 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3731 | && insn->tok[i].X_op == O_symbol) | |
3732 | symbol_get_tc (insn->tok[i].X_add_symbol)->is_loop_target = TRUE; | |
3733 | return; | |
3734 | } | |
e0001a05 | 3735 | |
7fa3d080 BW |
3736 | if (xtensa_opcode_is_branch (isa, insn->opcode) == 1 |
3737 | || xtensa_opcode_is_loop (isa, insn->opcode) == 1) | |
e0001a05 | 3738 | { |
7fa3d080 BW |
3739 | int i; |
3740 | ||
3741 | for (i = 0; i < insn->ntok && i < num_ops; i++) | |
3742 | { | |
3743 | if (xtensa_operand_is_PCrelative (isa, insn->opcode, i) == 1 | |
3744 | && insn->tok[i].X_op == O_symbol) | |
3745 | { | |
3746 | symbolS *sym = insn->tok[i].X_add_symbol; | |
3747 | symbol_get_tc (sym)->is_branch_target = TRUE; | |
3748 | if (S_IS_DEFINED (sym)) | |
3749 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
3750 | } | |
3751 | } | |
e0001a05 | 3752 | } |
e0001a05 NC |
3753 | } |
3754 | ||
3755 | ||
43cd72b9 | 3756 | /* Return FALSE if no error. */ |
e0001a05 | 3757 | |
7fa3d080 BW |
3758 | static bfd_boolean |
3759 | xg_build_token_insn (BuildInstr *instr_spec, TInsn *old_insn, TInsn *new_insn) | |
e0001a05 NC |
3760 | { |
3761 | int num_ops = 0; | |
3762 | BuildOp *b_op; | |
3763 | ||
3764 | switch (instr_spec->typ) | |
3765 | { | |
3766 | case INSTR_INSTR: | |
3767 | new_insn->insn_type = ITYPE_INSN; | |
3768 | new_insn->opcode = instr_spec->opcode; | |
3769 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3770 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3771 | break; |
3772 | case INSTR_LITERAL_DEF: | |
3773 | new_insn->insn_type = ITYPE_LITERAL; | |
3774 | new_insn->opcode = XTENSA_UNDEFINED; | |
3775 | new_insn->is_specific_opcode = FALSE; | |
7c430684 | 3776 | new_insn->linenum = old_insn->linenum; |
e0001a05 NC |
3777 | break; |
3778 | case INSTR_LABEL_DEF: | |
3779 | as_bad (_("INSTR_LABEL_DEF not supported yet")); | |
3780 | break; | |
3781 | } | |
3782 | ||
3783 | for (b_op = instr_spec->ops; b_op != NULL; b_op = b_op->next) | |
3784 | { | |
3785 | expressionS *exp; | |
3786 | const expressionS *src_exp; | |
3787 | ||
3788 | num_ops++; | |
3789 | switch (b_op->typ) | |
3790 | { | |
3791 | case OP_CONSTANT: | |
3792 | /* The expression must be the constant. */ | |
3793 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3794 | exp = &new_insn->tok[b_op->op_num]; | |
3795 | set_expr_const (exp, b_op->op_data); | |
3796 | break; | |
3797 | ||
3798 | case OP_OPERAND: | |
3799 | assert (b_op->op_num < MAX_INSN_ARGS); | |
3800 | assert (b_op->op_data < (unsigned) old_insn->ntok); | |
3801 | src_exp = &old_insn->tok[b_op->op_data]; | |
3802 | exp = &new_insn->tok[b_op->op_num]; | |
3803 | copy_expr (exp, src_exp); | |
3804 | break; | |
3805 | ||
3806 | case OP_LITERAL: | |
3807 | case OP_LABEL: | |
3808 | as_bad (_("can't handle generation of literal/labels yet")); | |
3809 | assert (0); | |
3810 | ||
3811 | default: | |
3812 | as_bad (_("can't handle undefined OP TYPE")); | |
3813 | assert (0); | |
3814 | } | |
3815 | } | |
3816 | ||
3817 | new_insn->ntok = num_ops; | |
3818 | return FALSE; | |
3819 | } | |
3820 | ||
3821 | ||
43cd72b9 | 3822 | /* Return TRUE if it was simplified. */ |
e0001a05 | 3823 | |
7fa3d080 BW |
3824 | static bfd_boolean |
3825 | xg_simplify_insn (TInsn *old_insn, TInsn *new_insn) | |
e0001a05 | 3826 | { |
43cd72b9 | 3827 | TransitionRule *rule; |
e0001a05 | 3828 | BuildInstr *insn_spec; |
43cd72b9 BW |
3829 | |
3830 | if (old_insn->is_specific_opcode || !density_supported) | |
3831 | return FALSE; | |
3832 | ||
3833 | rule = xg_instruction_match (old_insn); | |
e0001a05 NC |
3834 | if (rule == NULL) |
3835 | return FALSE; | |
3836 | ||
3837 | insn_spec = rule->to_instr; | |
3838 | /* There should only be one. */ | |
3839 | assert (insn_spec != NULL); | |
3840 | assert (insn_spec->next == NULL); | |
3841 | if (insn_spec->next != NULL) | |
3842 | return FALSE; | |
3843 | ||
3844 | xg_build_token_insn (insn_spec, old_insn, new_insn); | |
3845 | ||
3846 | return TRUE; | |
3847 | } | |
3848 | ||
3849 | ||
3850 | /* xg_expand_assembly_insn: (1) Simplify the instruction, i.e., l32i -> | |
3851 | l32i.n. (2) Check the number of operands. (3) Place the instruction | |
7c834684 BW |
3852 | tokens into the stack or relax it and place multiple |
3853 | instructions/literals onto the stack. Return FALSE if no error. */ | |
e0001a05 NC |
3854 | |
3855 | static bfd_boolean | |
7fa3d080 | 3856 | xg_expand_assembly_insn (IStack *istack, TInsn *orig_insn) |
e0001a05 NC |
3857 | { |
3858 | int noperands; | |
3859 | TInsn new_insn; | |
7c834684 BW |
3860 | bfd_boolean do_expand; |
3861 | ||
e0001a05 NC |
3862 | memset (&new_insn, 0, sizeof (TInsn)); |
3863 | ||
43cd72b9 BW |
3864 | /* Narrow it if we can. xg_simplify_insn now does all the |
3865 | appropriate checking (e.g., for the density option). */ | |
3866 | if (xg_simplify_insn (orig_insn, &new_insn)) | |
3867 | orig_insn = &new_insn; | |
e0001a05 | 3868 | |
43cd72b9 BW |
3869 | noperands = xtensa_opcode_num_operands (xtensa_default_isa, |
3870 | orig_insn->opcode); | |
e0001a05 NC |
3871 | if (orig_insn->ntok < noperands) |
3872 | { | |
3873 | as_bad (_("found %d operands for '%s': Expected %d"), | |
3874 | orig_insn->ntok, | |
3875 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3876 | noperands); | |
3877 | return TRUE; | |
3878 | } | |
3879 | if (orig_insn->ntok > noperands) | |
3880 | as_warn (_("found too many (%d) operands for '%s': Expected %d"), | |
3881 | orig_insn->ntok, | |
3882 | xtensa_opcode_name (xtensa_default_isa, orig_insn->opcode), | |
3883 | noperands); | |
3884 | ||
43cd72b9 | 3885 | /* If there are not enough operands, we will assert above. If there |
e0001a05 | 3886 | are too many, just cut out the extras here. */ |
e0001a05 NC |
3887 | orig_insn->ntok = noperands; |
3888 | ||
e0001a05 NC |
3889 | if (tinsn_has_invalid_symbolic_operands (orig_insn)) |
3890 | return TRUE; | |
3891 | ||
7c834684 BW |
3892 | /* If the instruction will definitely need to be relaxed, it is better |
3893 | to expand it now for better scheduling. Decide whether to expand | |
3894 | now.... */ | |
3895 | do_expand = (!orig_insn->is_specific_opcode && use_transform ()); | |
3896 | ||
3897 | /* Calls should be expanded to longcalls only in the backend relaxation | |
3898 | so that the assembly scheduler will keep the L32R/CALLX instructions | |
3899 | adjacent. */ | |
3900 | if (is_direct_call_opcode (orig_insn->opcode)) | |
3901 | do_expand = FALSE; | |
e0001a05 NC |
3902 | |
3903 | if (tinsn_has_symbolic_operands (orig_insn)) | |
3904 | { | |
7c834684 BW |
3905 | /* The values of symbolic operands are not known yet, so only expand |
3906 | now if an operand is "complex" (e.g., difference of symbols) and | |
3907 | will have to be stored as a literal regardless of the value. */ | |
3908 | if (!tinsn_has_complex_operands (orig_insn)) | |
3909 | do_expand = FALSE; | |
e0001a05 | 3910 | } |
7c834684 BW |
3911 | else if (xg_immeds_fit (orig_insn)) |
3912 | do_expand = FALSE; | |
3913 | ||
3914 | if (do_expand) | |
3915 | xg_assembly_relax (istack, orig_insn, 0, 0, 0, 0, 0); | |
e0001a05 | 3916 | else |
7c834684 | 3917 | istack_push (istack, orig_insn); |
e0001a05 | 3918 | |
e0001a05 NC |
3919 | return FALSE; |
3920 | } | |
3921 | ||
3922 | ||
7fa3d080 BW |
3923 | /* Return TRUE if the section flags are marked linkonce |
3924 | or the name is .gnu.linkonce*. */ | |
3925 | ||
3926 | static bfd_boolean | |
3927 | get_is_linkonce_section (bfd *abfd ATTRIBUTE_UNUSED, segT sec) | |
3928 | { | |
3929 | flagword flags, link_once_flags; | |
3930 | ||
3931 | flags = bfd_get_section_flags (abfd, sec); | |
3932 | link_once_flags = (flags & SEC_LINK_ONCE); | |
3933 | ||
3934 | /* Flags might not be set yet. */ | |
3935 | if (!link_once_flags) | |
3936 | { | |
3937 | static size_t len = sizeof ".gnu.linkonce.t."; | |
3938 | ||
3939 | if (strncmp (segment_name (sec), ".gnu.linkonce.t.", len - 1) == 0) | |
3940 | link_once_flags = SEC_LINK_ONCE; | |
3941 | } | |
3942 | return (link_once_flags != 0); | |
3943 | } | |
3944 | ||
3945 | ||
3946 | static void | |
3947 | xtensa_add_literal_sym (symbolS *sym) | |
3948 | { | |
3949 | sym_list *l; | |
3950 | ||
3951 | l = (sym_list *) xmalloc (sizeof (sym_list)); | |
3952 | l->sym = sym; | |
3953 | l->next = literal_syms; | |
3954 | literal_syms = l; | |
3955 | } | |
3956 | ||
3957 | ||
3958 | static symbolS * | |
3959 | xtensa_create_literal_symbol (segT sec, fragS *frag) | |
3960 | { | |
3961 | static int lit_num = 0; | |
3962 | static char name[256]; | |
3963 | symbolS *symbolP; | |
3964 | ||
3965 | sprintf (name, ".L_lit_sym%d", lit_num); | |
3966 | ||
3967 | /* Create a local symbol. If it is in a linkonce section, we have to | |
3968 | be careful to make sure that if it is used in a relocation that the | |
3969 | symbol will be in the output file. */ | |
3970 | if (get_is_linkonce_section (stdoutput, sec)) | |
3971 | { | |
3972 | symbolP = symbol_new (name, sec, 0, frag); | |
3973 | S_CLEAR_EXTERNAL (symbolP); | |
3974 | /* symbolP->local = 1; */ | |
3975 | } | |
3976 | else | |
3977 | symbolP = symbol_new (name, sec, 0, frag); | |
3978 | ||
3979 | xtensa_add_literal_sym (symbolP); | |
3980 | ||
7fa3d080 BW |
3981 | lit_num++; |
3982 | return symbolP; | |
3983 | } | |
3984 | ||
3985 | ||
e0001a05 NC |
3986 | /* Currently all literals that are generated here are 32-bit L32R targets. */ |
3987 | ||
7fa3d080 BW |
3988 | static symbolS * |
3989 | xg_assemble_literal (/* const */ TInsn *insn) | |
e0001a05 NC |
3990 | { |
3991 | emit_state state; | |
3992 | symbolS *lit_sym = NULL; | |
3993 | ||
3994 | /* size = 4 for L32R. It could easily be larger when we move to | |
3995 | larger constants. Add a parameter later. */ | |
3996 | offsetT litsize = 4; | |
3997 | offsetT litalign = 2; /* 2^2 = 4 */ | |
3998 | expressionS saved_loc; | |
43cd72b9 BW |
3999 | expressionS * emit_val; |
4000 | ||
e0001a05 NC |
4001 | set_expr_symbol_offset (&saved_loc, frag_now->fr_symbol, frag_now_fix ()); |
4002 | ||
4003 | assert (insn->insn_type == ITYPE_LITERAL); | |
77cd6497 | 4004 | assert (insn->ntok == 1); /* must be only one token here */ |
e0001a05 NC |
4005 | |
4006 | xtensa_switch_to_literal_fragment (&state); | |
4007 | ||
43cd72b9 BW |
4008 | emit_val = &insn->tok[0]; |
4009 | if (emit_val->X_op == O_big) | |
4010 | { | |
4011 | int size = emit_val->X_add_number * CHARS_PER_LITTLENUM; | |
4012 | if (size > litsize) | |
4013 | { | |
4014 | /* This happens when someone writes a "movi a2, big_number". */ | |
c138bc38 | 4015 | as_bad_where (frag_now->fr_file, frag_now->fr_line, |
43cd72b9 BW |
4016 | _("invalid immediate")); |
4017 | xtensa_restore_emit_state (&state); | |
4018 | return NULL; | |
4019 | } | |
4020 | } | |
4021 | ||
e0001a05 NC |
4022 | /* Force a 4-byte align here. Note that this opens a new frag, so all |
4023 | literals done with this function have a frag to themselves. That's | |
4024 | important for the way text section literals work. */ | |
4025 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4026 | record_alignment (now_seg, litalign); |
e0001a05 | 4027 | |
43cd72b9 BW |
4028 | if (emit_val->X_op == O_pltrel) |
4029 | { | |
4030 | char *p = frag_more (litsize); | |
4031 | xtensa_set_frag_assembly_state (frag_now); | |
4032 | if (emit_val->X_add_symbol) | |
4033 | emit_val->X_op = O_symbol; | |
4034 | else | |
4035 | emit_val->X_op = O_constant; | |
4036 | fix_new_exp (frag_now, p - frag_now->fr_literal, | |
4037 | litsize, emit_val, 0, BFD_RELOC_XTENSA_PLT); | |
4038 | } | |
4039 | else | |
4040 | emit_expr (emit_val, litsize); | |
e0001a05 NC |
4041 | |
4042 | assert (frag_now->tc_frag_data.literal_frag == NULL); | |
4043 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
4044 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); | |
4045 | lit_sym = frag_now->fr_symbol; | |
e0001a05 NC |
4046 | |
4047 | /* Go back. */ | |
4048 | xtensa_restore_emit_state (&state); | |
4049 | return lit_sym; | |
4050 | } | |
4051 | ||
4052 | ||
4053 | static void | |
7fa3d080 | 4054 | xg_assemble_literal_space (/* const */ int size, int slot) |
e0001a05 NC |
4055 | { |
4056 | emit_state state; | |
43cd72b9 | 4057 | /* We might have to do something about this alignment. It only |
e0001a05 NC |
4058 | takes effect if something is placed here. */ |
4059 | offsetT litalign = 2; /* 2^2 = 4 */ | |
4060 | fragS *lit_saved_frag; | |
4061 | ||
e0001a05 | 4062 | assert (size % 4 == 0); |
e0001a05 NC |
4063 | |
4064 | xtensa_switch_to_literal_fragment (&state); | |
4065 | ||
4066 | /* Force a 4-byte align here. */ | |
4067 | frag_align (litalign, 0, 0); | |
43cd72b9 | 4068 | record_alignment (now_seg, litalign); |
e0001a05 NC |
4069 | |
4070 | xg_force_frag_space (size); | |
4071 | ||
4072 | lit_saved_frag = frag_now; | |
4073 | frag_now->tc_frag_data.literal_frag = get_literal_pool_location (now_seg); | |
e0001a05 | 4074 | frag_now->fr_symbol = xtensa_create_literal_symbol (now_seg, frag_now); |
43cd72b9 | 4075 | xg_finish_frag (0, RELAX_LITERAL, 0, size, FALSE); |
e0001a05 NC |
4076 | |
4077 | /* Go back. */ | |
4078 | xtensa_restore_emit_state (&state); | |
43cd72b9 | 4079 | frag_now->tc_frag_data.literal_frags[slot] = lit_saved_frag; |
e0001a05 NC |
4080 | } |
4081 | ||
4082 | ||
e0001a05 | 4083 | /* Put in a fixup record based on the opcode. |
43cd72b9 | 4084 | Return TRUE on success. */ |
e0001a05 | 4085 | |
7fa3d080 BW |
4086 | static bfd_boolean |
4087 | xg_add_opcode_fix (TInsn *tinsn, | |
4088 | int opnum, | |
4089 | xtensa_format fmt, | |
4090 | int slot, | |
4091 | expressionS *expr, | |
4092 | fragS *fragP, | |
4093 | offsetT offset) | |
43cd72b9 BW |
4094 | { |
4095 | xtensa_opcode opcode = tinsn->opcode; | |
4096 | bfd_reloc_code_real_type reloc; | |
4097 | reloc_howto_type *howto; | |
4098 | int fmt_length; | |
e0001a05 NC |
4099 | fixS *the_fix; |
4100 | ||
43cd72b9 BW |
4101 | reloc = BFD_RELOC_NONE; |
4102 | ||
4103 | /* First try the special cases for "alternate" relocs. */ | |
4104 | if (opcode == xtensa_l32r_opcode) | |
4105 | { | |
4106 | if (fragP->tc_frag_data.use_absolute_literals) | |
4107 | reloc = encode_alt_reloc (slot); | |
4108 | } | |
4109 | else if (opcode == xtensa_const16_opcode) | |
4110 | { | |
4111 | if (expr->X_op == O_lo16) | |
4112 | { | |
4113 | reloc = encode_reloc (slot); | |
4114 | expr->X_op = O_symbol; | |
4115 | } | |
4116 | else if (expr->X_op == O_hi16) | |
4117 | { | |
4118 | reloc = encode_alt_reloc (slot); | |
4119 | expr->X_op = O_symbol; | |
4120 | } | |
4121 | } | |
4122 | ||
4123 | if (opnum != get_relaxable_immed (opcode)) | |
e0001a05 | 4124 | { |
43cd72b9 | 4125 | as_bad (_("invalid relocation for operand %i of '%s'"), |
431ad2d0 | 4126 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
e0001a05 NC |
4127 | return FALSE; |
4128 | } | |
4129 | ||
43cd72b9 BW |
4130 | /* Handle erroneous "@h" and "@l" expressions here before they propagate |
4131 | into the symbol table where the generic portions of the assembler | |
4132 | won't know what to do with them. */ | |
4133 | if (expr->X_op == O_lo16 || expr->X_op == O_hi16) | |
4134 | { | |
4135 | as_bad (_("invalid expression for operand %i of '%s'"), | |
431ad2d0 | 4136 | opnum + 1, xtensa_opcode_name (xtensa_default_isa, opcode)); |
43cd72b9 BW |
4137 | return FALSE; |
4138 | } | |
4139 | ||
4140 | /* Next try the generic relocs. */ | |
4141 | if (reloc == BFD_RELOC_NONE) | |
4142 | reloc = encode_reloc (slot); | |
4143 | if (reloc == BFD_RELOC_NONE) | |
4144 | { | |
4145 | as_bad (_("invalid relocation in instruction slot %i"), slot); | |
4146 | return FALSE; | |
4147 | } | |
e0001a05 | 4148 | |
43cd72b9 | 4149 | howto = bfd_reloc_type_lookup (stdoutput, reloc); |
e0001a05 NC |
4150 | if (!howto) |
4151 | { | |
43cd72b9 | 4152 | as_bad (_("undefined symbol for opcode \"%s\""), |
e0001a05 NC |
4153 | xtensa_opcode_name (xtensa_default_isa, opcode)); |
4154 | return FALSE; | |
4155 | } | |
4156 | ||
43cd72b9 BW |
4157 | fmt_length = xtensa_format_length (xtensa_default_isa, fmt); |
4158 | the_fix = fix_new_exp (fragP, offset, fmt_length, expr, | |
e0001a05 | 4159 | howto->pc_relative, reloc); |
d9740523 | 4160 | the_fix->fx_no_overflow = 1; |
e0001a05 | 4161 | |
7fa3d080 BW |
4162 | if (expr->X_add_symbol |
4163 | && (S_IS_EXTERNAL (expr->X_add_symbol) | |
4164 | || S_IS_WEAK (expr->X_add_symbol))) | |
4165 | the_fix->fx_plt = TRUE; | |
4166 | ||
4167 | the_fix->tc_fix_data.X_add_symbol = expr->X_add_symbol; | |
4168 | the_fix->tc_fix_data.X_add_number = expr->X_add_number; | |
4169 | the_fix->tc_fix_data.slot = slot; | |
c138bc38 | 4170 | |
7fa3d080 BW |
4171 | return TRUE; |
4172 | } | |
4173 | ||
4174 | ||
4175 | static bfd_boolean | |
4176 | xg_emit_insn_to_buf (TInsn *tinsn, | |
7fa3d080 BW |
4177 | char *buf, |
4178 | fragS *fragP, | |
4179 | offsetT offset, | |
4180 | bfd_boolean build_fix) | |
4181 | { | |
4182 | static xtensa_insnbuf insnbuf = NULL; | |
4183 | bfd_boolean has_symbolic_immed = FALSE; | |
4184 | bfd_boolean ok = TRUE; | |
b2d179be | 4185 | |
7fa3d080 BW |
4186 | if (!insnbuf) |
4187 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
4188 | ||
4189 | has_symbolic_immed = tinsn_to_insnbuf (tinsn, insnbuf); | |
4190 | if (has_symbolic_immed && build_fix) | |
4191 | { | |
4192 | /* Add a fixup. */ | |
b2d179be BW |
4193 | xtensa_format fmt = xg_get_single_format (tinsn->opcode); |
4194 | int slot = xg_get_single_slot (tinsn->opcode); | |
7fa3d080 BW |
4195 | int opnum = get_relaxable_immed (tinsn->opcode); |
4196 | expressionS *exp = &tinsn->tok[opnum]; | |
43cd72b9 | 4197 | |
b2d179be | 4198 | if (!xg_add_opcode_fix (tinsn, opnum, fmt, slot, exp, fragP, offset)) |
7fa3d080 BW |
4199 | ok = FALSE; |
4200 | } | |
4201 | fragP->tc_frag_data.is_insn = TRUE; | |
d77b99c9 BW |
4202 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4203 | (unsigned char *) buf, 0); | |
7fa3d080 | 4204 | return ok; |
e0001a05 NC |
4205 | } |
4206 | ||
4207 | ||
7fa3d080 BW |
4208 | static void |
4209 | xg_resolve_literals (TInsn *insn, symbolS *lit_sym) | |
e0001a05 NC |
4210 | { |
4211 | symbolS *sym = get_special_literal_symbol (); | |
4212 | int i; | |
4213 | if (lit_sym == 0) | |
4214 | return; | |
4215 | assert (insn->insn_type == ITYPE_INSN); | |
4216 | for (i = 0; i < insn->ntok; i++) | |
4217 | if (insn->tok[i].X_add_symbol == sym) | |
4218 | insn->tok[i].X_add_symbol = lit_sym; | |
4219 | ||
4220 | } | |
4221 | ||
4222 | ||
7fa3d080 BW |
4223 | static void |
4224 | xg_resolve_labels (TInsn *insn, symbolS *label_sym) | |
e0001a05 NC |
4225 | { |
4226 | symbolS *sym = get_special_label_symbol (); | |
4227 | int i; | |
e0001a05 NC |
4228 | for (i = 0; i < insn->ntok; i++) |
4229 | if (insn->tok[i].X_add_symbol == sym) | |
4230 | insn->tok[i].X_add_symbol = label_sym; | |
4231 | ||
4232 | } | |
4233 | ||
4234 | ||
43cd72b9 | 4235 | /* Return TRUE if the instruction can write to the specified |
e0001a05 NC |
4236 | integer register. */ |
4237 | ||
4238 | static bfd_boolean | |
7fa3d080 | 4239 | is_register_writer (const TInsn *insn, const char *regset, int regnum) |
e0001a05 NC |
4240 | { |
4241 | int i; | |
4242 | int num_ops; | |
4243 | xtensa_isa isa = xtensa_default_isa; | |
4244 | ||
43cd72b9 | 4245 | num_ops = xtensa_opcode_num_operands (isa, insn->opcode); |
e0001a05 NC |
4246 | |
4247 | for (i = 0; i < num_ops; i++) | |
4248 | { | |
43cd72b9 BW |
4249 | char inout; |
4250 | inout = xtensa_operand_inout (isa, insn->opcode, i); | |
4251 | if ((inout == 'o' || inout == 'm') | |
4252 | && xtensa_operand_is_register (isa, insn->opcode, i) == 1) | |
e0001a05 | 4253 | { |
43cd72b9 BW |
4254 | xtensa_regfile opnd_rf = |
4255 | xtensa_operand_regfile (isa, insn->opcode, i); | |
4256 | if (!strcmp (xtensa_regfile_shortname (isa, opnd_rf), regset)) | |
e0001a05 NC |
4257 | { |
4258 | if ((insn->tok[i].X_op == O_register) | |
4259 | && (insn->tok[i].X_add_number == regnum)) | |
4260 | return TRUE; | |
4261 | } | |
4262 | } | |
4263 | } | |
4264 | return FALSE; | |
4265 | } | |
4266 | ||
4267 | ||
4268 | static bfd_boolean | |
7fa3d080 | 4269 | is_bad_loopend_opcode (const TInsn *tinsn) |
e0001a05 NC |
4270 | { |
4271 | xtensa_opcode opcode = tinsn->opcode; | |
4272 | ||
4273 | if (opcode == XTENSA_UNDEFINED) | |
4274 | return FALSE; | |
4275 | ||
4276 | if (opcode == xtensa_call0_opcode | |
4277 | || opcode == xtensa_callx0_opcode | |
4278 | || opcode == xtensa_call4_opcode | |
4279 | || opcode == xtensa_callx4_opcode | |
4280 | || opcode == xtensa_call8_opcode | |
4281 | || opcode == xtensa_callx8_opcode | |
4282 | || opcode == xtensa_call12_opcode | |
4283 | || opcode == xtensa_callx12_opcode | |
4284 | || opcode == xtensa_isync_opcode | |
4285 | || opcode == xtensa_ret_opcode | |
4286 | || opcode == xtensa_ret_n_opcode | |
4287 | || opcode == xtensa_retw_opcode | |
4288 | || opcode == xtensa_retw_n_opcode | |
43cd72b9 BW |
4289 | || opcode == xtensa_waiti_opcode |
4290 | || opcode == xtensa_rsr_lcount_opcode) | |
e0001a05 | 4291 | return TRUE; |
c138bc38 | 4292 | |
e0001a05 NC |
4293 | return FALSE; |
4294 | } | |
4295 | ||
4296 | ||
4297 | /* Labels that begin with ".Ln" or ".LM" are unaligned. | |
4298 | This allows the debugger to add unaligned labels. | |
4299 | Also, the assembler generates stabs labels that need | |
4300 | not be aligned: FAKE_LABEL_NAME . {"F", "L", "endfunc"}. */ | |
4301 | ||
7fa3d080 BW |
4302 | static bfd_boolean |
4303 | is_unaligned_label (symbolS *sym) | |
e0001a05 NC |
4304 | { |
4305 | const char *name = S_GET_NAME (sym); | |
4306 | static size_t fake_size = 0; | |
4307 | ||
4308 | if (name | |
4309 | && name[0] == '.' | |
4310 | && name[1] == 'L' && (name[2] == 'n' || name[2] == 'M')) | |
4311 | return TRUE; | |
4312 | ||
4313 | /* FAKE_LABEL_NAME followed by "F", "L" or "endfunc" */ | |
4314 | if (fake_size == 0) | |
4315 | fake_size = strlen (FAKE_LABEL_NAME); | |
4316 | ||
43cd72b9 | 4317 | if (name |
e0001a05 NC |
4318 | && strncmp (FAKE_LABEL_NAME, name, fake_size) == 0 |
4319 | && (name[fake_size] == 'F' | |
4320 | || name[fake_size] == 'L' | |
4321 | || (name[fake_size] == 'e' | |
4322 | && strncmp ("endfunc", name+fake_size, 7) == 0))) | |
4323 | return TRUE; | |
4324 | ||
4325 | return FALSE; | |
4326 | } | |
4327 | ||
4328 | ||
7fa3d080 BW |
4329 | static fragS * |
4330 | next_non_empty_frag (const fragS *fragP) | |
e0001a05 NC |
4331 | { |
4332 | fragS *next_fragP = fragP->fr_next; | |
4333 | ||
c138bc38 | 4334 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4335 | So we have to skip until we find something legit. */ |
4336 | while (next_fragP && next_fragP->fr_fix == 0) | |
4337 | next_fragP = next_fragP->fr_next; | |
4338 | ||
4339 | if (next_fragP == NULL || next_fragP->fr_fix == 0) | |
4340 | return NULL; | |
4341 | ||
4342 | return next_fragP; | |
4343 | } | |
4344 | ||
4345 | ||
43cd72b9 | 4346 | static bfd_boolean |
7fa3d080 | 4347 | next_frag_opcode_is_loop (const fragS *fragP, xtensa_opcode *opcode) |
43cd72b9 BW |
4348 | { |
4349 | xtensa_opcode out_opcode; | |
4350 | const fragS *next_fragP = next_non_empty_frag (fragP); | |
4351 | ||
4352 | if (next_fragP == NULL) | |
4353 | return FALSE; | |
4354 | ||
4355 | out_opcode = get_opcode_from_buf (next_fragP->fr_literal, 0); | |
4356 | if (xtensa_opcode_is_loop (xtensa_default_isa, out_opcode) == 1) | |
4357 | { | |
4358 | *opcode = out_opcode; | |
4359 | return TRUE; | |
4360 | } | |
4361 | return FALSE; | |
4362 | } | |
4363 | ||
4364 | ||
4365 | static int | |
7fa3d080 | 4366 | frag_format_size (const fragS *fragP) |
43cd72b9 | 4367 | { |
e0001a05 NC |
4368 | static xtensa_insnbuf insnbuf = NULL; |
4369 | xtensa_isa isa = xtensa_default_isa; | |
43cd72b9 | 4370 | xtensa_format fmt; |
c138bc38 | 4371 | int fmt_size; |
e0001a05 NC |
4372 | |
4373 | if (!insnbuf) | |
4374 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4375 | ||
43cd72b9 BW |
4376 | if (fragP == NULL) |
4377 | return XTENSA_UNDEFINED; | |
4378 | ||
d77b99c9 BW |
4379 | xtensa_insnbuf_from_chars (isa, insnbuf, |
4380 | (unsigned char *) fragP->fr_literal, 0); | |
43cd72b9 BW |
4381 | |
4382 | fmt = xtensa_format_decode (isa, insnbuf); | |
4383 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 | 4384 | return XTENSA_UNDEFINED; |
43cd72b9 BW |
4385 | fmt_size = xtensa_format_length (isa, fmt); |
4386 | ||
4387 | /* If the next format won't be changing due to relaxation, just | |
4388 | return the length of the first format. */ | |
4389 | if (fragP->fr_opcode != fragP->fr_literal) | |
4390 | return fmt_size; | |
4391 | ||
c138bc38 | 4392 | /* If during relaxation we have to pull an instruction out of a |
43cd72b9 BW |
4393 | multi-slot instruction, we will return the more conservative |
4394 | number. This works because alignment on bigger instructions | |
4395 | is more restrictive than alignment on smaller instructions. | |
4396 | This is more conservative than we would like, but it happens | |
4397 | infrequently. */ | |
4398 | ||
4399 | if (xtensa_format_num_slots (xtensa_default_isa, fmt) > 1) | |
4400 | return fmt_size; | |
4401 | ||
4402 | /* If we aren't doing one of our own relaxations or it isn't | |
4403 | slot-based, then the insn size won't change. */ | |
4404 | if (fragP->fr_type != rs_machine_dependent) | |
4405 | return fmt_size; | |
4406 | if (fragP->fr_subtype != RELAX_SLOTS) | |
4407 | return fmt_size; | |
4408 | ||
4409 | /* If an instruction is about to grow, return the longer size. */ | |
4410 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP1 | |
4411 | || fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED_STEP2) | |
4412 | return 3; | |
c138bc38 | 4413 | |
43cd72b9 BW |
4414 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) |
4415 | return 2 + fragP->tc_frag_data.text_expansion[0]; | |
e0001a05 | 4416 | |
43cd72b9 | 4417 | return fmt_size; |
e0001a05 NC |
4418 | } |
4419 | ||
4420 | ||
7fa3d080 BW |
4421 | static int |
4422 | next_frag_format_size (const fragS *fragP) | |
e0001a05 | 4423 | { |
7fa3d080 BW |
4424 | const fragS *next_fragP = next_non_empty_frag (fragP); |
4425 | return frag_format_size (next_fragP); | |
e0001a05 NC |
4426 | } |
4427 | ||
4428 | ||
03aaa593 BW |
4429 | /* In early Xtensa Processors, for reasons that are unclear, the ISA |
4430 | required two-byte instructions to be treated as three-byte instructions | |
4431 | for loop instruction alignment. This restriction was removed beginning | |
4432 | with Xtensa LX. Now the only requirement on loop instruction alignment | |
4433 | is that the first instruction of the loop must appear at an address that | |
4434 | does not cross a fetch boundary. */ | |
4435 | ||
4436 | static int | |
4437 | get_loop_align_size (int insn_size) | |
4438 | { | |
4439 | if (insn_size == XTENSA_UNDEFINED) | |
4440 | return xtensa_fetch_width; | |
4441 | ||
4442 | if (enforce_three_byte_loop_align && insn_size == 2) | |
4443 | return 3; | |
4444 | ||
4445 | return insn_size; | |
4446 | } | |
4447 | ||
4448 | ||
e0001a05 NC |
4449 | /* If the next legit fragment is an end-of-loop marker, |
4450 | switch its state so it will instantiate a NOP. */ | |
4451 | ||
4452 | static void | |
1d19a770 | 4453 | update_next_frag_state (fragS *fragP) |
e0001a05 NC |
4454 | { |
4455 | fragS *next_fragP = fragP->fr_next; | |
43cd72b9 | 4456 | fragS *new_target = NULL; |
e0001a05 | 4457 | |
7b1cc377 | 4458 | if (align_targets) |
43cd72b9 BW |
4459 | { |
4460 | /* We are guaranteed there will be one of these... */ | |
4461 | while (!(next_fragP->fr_type == rs_machine_dependent | |
4462 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4463 | || next_fragP->fr_subtype == RELAX_UNREACHABLE))) | |
4464 | next_fragP = next_fragP->fr_next; | |
4465 | ||
4466 | assert (next_fragP->fr_type == rs_machine_dependent | |
4467 | && (next_fragP->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
4468 | || next_fragP->fr_subtype == RELAX_UNREACHABLE)); | |
4469 | ||
4470 | /* ...and one of these. */ | |
4471 | new_target = next_fragP->fr_next; | |
4472 | while (!(new_target->fr_type == rs_machine_dependent | |
4473 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4474 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN))) | |
4475 | new_target = new_target->fr_next; | |
4476 | ||
4477 | assert (new_target->fr_type == rs_machine_dependent | |
4478 | && (new_target->fr_subtype == RELAX_MAYBE_DESIRE_ALIGN | |
4479 | || new_target->fr_subtype == RELAX_DESIRE_ALIGN)); | |
4480 | } | |
43cd72b9 | 4481 | |
1d19a770 | 4482 | while (next_fragP && next_fragP->fr_fix == 0) |
43cd72b9 | 4483 | { |
1d19a770 BW |
4484 | if (next_fragP->fr_type == rs_machine_dependent |
4485 | && next_fragP->fr_subtype == RELAX_LOOP_END) | |
43cd72b9 | 4486 | { |
1d19a770 BW |
4487 | next_fragP->fr_subtype = RELAX_LOOP_END_ADD_NOP; |
4488 | return; | |
e0001a05 | 4489 | } |
1d19a770 BW |
4490 | |
4491 | next_fragP = next_fragP->fr_next; | |
e0001a05 NC |
4492 | } |
4493 | } | |
4494 | ||
4495 | ||
4496 | static bfd_boolean | |
7fa3d080 | 4497 | next_frag_is_branch_target (const fragS *fragP) |
e0001a05 | 4498 | { |
43cd72b9 | 4499 | /* Sometimes an empty will end up here due to storage allocation issues, |
e0001a05 NC |
4500 | so we have to skip until we find something legit. */ |
4501 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4502 | { | |
4503 | if (fragP->tc_frag_data.is_branch_target) | |
4504 | return TRUE; | |
4505 | if (fragP->fr_fix != 0) | |
4506 | break; | |
4507 | } | |
4508 | return FALSE; | |
4509 | } | |
4510 | ||
4511 | ||
4512 | static bfd_boolean | |
7fa3d080 | 4513 | next_frag_is_loop_target (const fragS *fragP) |
e0001a05 | 4514 | { |
c138bc38 | 4515 | /* Sometimes an empty will end up here due storage allocation issues. |
e0001a05 NC |
4516 | So we have to skip until we find something legit. */ |
4517 | for (fragP = fragP->fr_next; fragP; fragP = fragP->fr_next) | |
4518 | { | |
4519 | if (fragP->tc_frag_data.is_loop_target) | |
4520 | return TRUE; | |
4521 | if (fragP->fr_fix != 0) | |
4522 | break; | |
4523 | } | |
4524 | return FALSE; | |
4525 | } | |
4526 | ||
4527 | ||
4528 | static addressT | |
7fa3d080 | 4529 | next_frag_pre_opcode_bytes (const fragS *fragp) |
e0001a05 NC |
4530 | { |
4531 | const fragS *next_fragp = fragp->fr_next; | |
43cd72b9 | 4532 | xtensa_opcode next_opcode; |
e0001a05 | 4533 | |
43cd72b9 | 4534 | if (!next_frag_opcode_is_loop (fragp, &next_opcode)) |
e0001a05 NC |
4535 | return 0; |
4536 | ||
43cd72b9 BW |
4537 | /* Sometimes an empty will end up here due to storage allocation issues, |
4538 | so we have to skip until we find something legit. */ | |
e0001a05 NC |
4539 | while (next_fragp->fr_fix == 0) |
4540 | next_fragp = next_fragp->fr_next; | |
4541 | ||
4542 | if (next_fragp->fr_type != rs_machine_dependent) | |
4543 | return 0; | |
4544 | ||
4545 | /* There is some implicit knowledge encoded in here. | |
4546 | The LOOP instructions that are NOT RELAX_IMMED have | |
43cd72b9 BW |
4547 | been relaxed. Note that we can assume that the LOOP |
4548 | instruction is in slot 0 because loops aren't bundleable. */ | |
4549 | if (next_fragp->tc_frag_data.slot_subtypes[0] > RELAX_IMMED) | |
e0001a05 NC |
4550 | return get_expanded_loop_offset (next_opcode); |
4551 | ||
4552 | return 0; | |
4553 | } | |
4554 | ||
4555 | ||
4556 | /* Mark a location where we can later insert literal frags. Update | |
4557 | the section's literal_pool_loc, so subsequent literals can be | |
4558 | placed nearest to their use. */ | |
4559 | ||
4560 | static void | |
7fa3d080 | 4561 | xtensa_mark_literal_pool_location (void) |
e0001a05 NC |
4562 | { |
4563 | /* Any labels pointing to the current location need | |
4564 | to be adjusted to after the literal pool. */ | |
4565 | emit_state s; | |
e0001a05 | 4566 | fragS *pool_location; |
e0001a05 | 4567 | |
43cd72b9 BW |
4568 | if (use_literal_section && !directive_state[directive_absolute_literals]) |
4569 | return; | |
4570 | ||
e0001a05 | 4571 | frag_align (2, 0, 0); |
43cd72b9 | 4572 | record_alignment (now_seg, 2); |
e0001a05 | 4573 | |
dd49a749 BW |
4574 | /* We stash info in these frags so we can later move the literal's |
4575 | fixes into this frchain's fix list. */ | |
e0001a05 | 4576 | pool_location = frag_now; |
dd49a749 BW |
4577 | frag_now->tc_frag_data.lit_frchain = frchain_now; |
4578 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4579 | RELAX_LITERAL_POOL_BEGIN, NULL, 0, NULL); |
43cd72b9 | 4580 | xtensa_set_frag_assembly_state (frag_now); |
dd49a749 BW |
4581 | frag_now->tc_frag_data.lit_seg = now_seg; |
4582 | frag_variant (rs_machine_dependent, 0, 0, | |
e0001a05 | 4583 | RELAX_LITERAL_POOL_END, NULL, 0, NULL); |
43cd72b9 | 4584 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4585 | |
4586 | /* Now put a frag into the literal pool that points to this location. */ | |
4587 | set_literal_pool_location (now_seg, pool_location); | |
43cd72b9 BW |
4588 | xtensa_switch_to_non_abs_literal_fragment (&s); |
4589 | frag_align (2, 0, 0); | |
4590 | record_alignment (now_seg, 2); | |
e0001a05 NC |
4591 | |
4592 | /* Close whatever frag is there. */ | |
4593 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 4594 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4595 | frag_now->tc_frag_data.literal_frag = pool_location; |
4596 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
4597 | xtensa_restore_emit_state (&s); | |
43cd72b9 | 4598 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
4599 | } |
4600 | ||
4601 | ||
43cd72b9 BW |
4602 | /* Build a nop of the correct size into tinsn. */ |
4603 | ||
4604 | static void | |
7fa3d080 | 4605 | build_nop (TInsn *tinsn, int size) |
43cd72b9 BW |
4606 | { |
4607 | tinsn_init (tinsn); | |
4608 | switch (size) | |
4609 | { | |
4610 | case 2: | |
4611 | tinsn->opcode = xtensa_nop_n_opcode; | |
4612 | tinsn->ntok = 0; | |
4613 | if (tinsn->opcode == XTENSA_UNDEFINED) | |
4614 | as_fatal (_("opcode 'NOP.N' unavailable in this configuration")); | |
4615 | break; | |
4616 | ||
4617 | case 3: | |
4618 | if (xtensa_nop_opcode == XTENSA_UNDEFINED) | |
4619 | { | |
4620 | tinsn->opcode = xtensa_or_opcode; | |
4621 | set_expr_const (&tinsn->tok[0], 1); | |
4622 | set_expr_const (&tinsn->tok[1], 1); | |
4623 | set_expr_const (&tinsn->tok[2], 1); | |
4624 | tinsn->ntok = 3; | |
4625 | } | |
4626 | else | |
4627 | tinsn->opcode = xtensa_nop_opcode; | |
4628 | ||
4629 | assert (tinsn->opcode != XTENSA_UNDEFINED); | |
4630 | } | |
4631 | } | |
4632 | ||
4633 | ||
e0001a05 NC |
4634 | /* Assemble a NOP of the requested size in the buffer. User must have |
4635 | allocated "buf" with at least "size" bytes. */ | |
4636 | ||
7fa3d080 | 4637 | static void |
d77b99c9 | 4638 | assemble_nop (int size, char *buf) |
e0001a05 NC |
4639 | { |
4640 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 4641 | TInsn tinsn; |
e0001a05 | 4642 | |
43cd72b9 | 4643 | build_nop (&tinsn, size); |
e0001a05 | 4644 | |
43cd72b9 BW |
4645 | if (!insnbuf) |
4646 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
e0001a05 | 4647 | |
43cd72b9 | 4648 | tinsn_to_insnbuf (&tinsn, insnbuf); |
d77b99c9 BW |
4649 | xtensa_insnbuf_to_chars (xtensa_default_isa, insnbuf, |
4650 | (unsigned char *) buf, 0); | |
e0001a05 NC |
4651 | } |
4652 | ||
4653 | ||
4654 | /* Return the number of bytes for the offset of the expanded loop | |
4655 | instruction. This should be incorporated into the relaxation | |
4656 | specification but is hard-coded here. This is used to auto-align | |
4657 | the loop instruction. It is invalid to call this function if the | |
4658 | configuration does not have loops or if the opcode is not a loop | |
4659 | opcode. */ | |
4660 | ||
4661 | static addressT | |
7fa3d080 | 4662 | get_expanded_loop_offset (xtensa_opcode opcode) |
e0001a05 NC |
4663 | { |
4664 | /* This is the OFFSET of the loop instruction in the expanded loop. | |
4665 | This MUST correspond directly to the specification of the loop | |
4666 | expansion. It will be validated on fragment conversion. */ | |
43cd72b9 | 4667 | assert (opcode != XTENSA_UNDEFINED); |
e0001a05 NC |
4668 | if (opcode == xtensa_loop_opcode) |
4669 | return 0; | |
4670 | if (opcode == xtensa_loopnez_opcode) | |
4671 | return 3; | |
4672 | if (opcode == xtensa_loopgtz_opcode) | |
4673 | return 6; | |
4674 | as_fatal (_("get_expanded_loop_offset: invalid opcode")); | |
4675 | return 0; | |
4676 | } | |
4677 | ||
4678 | ||
7fa3d080 BW |
4679 | static fragS * |
4680 | get_literal_pool_location (segT seg) | |
e0001a05 NC |
4681 | { |
4682 | return seg_info (seg)->tc_segment_info_data.literal_pool_loc; | |
4683 | } | |
4684 | ||
4685 | ||
4686 | static void | |
7fa3d080 | 4687 | set_literal_pool_location (segT seg, fragS *literal_pool_loc) |
e0001a05 NC |
4688 | { |
4689 | seg_info (seg)->tc_segment_info_data.literal_pool_loc = literal_pool_loc; | |
4690 | } | |
4691 | ||
43cd72b9 BW |
4692 | |
4693 | /* Set frag assembly state should be called when a new frag is | |
4694 | opened and after a frag has been closed. */ | |
4695 | ||
7fa3d080 BW |
4696 | static void |
4697 | xtensa_set_frag_assembly_state (fragS *fragP) | |
43cd72b9 BW |
4698 | { |
4699 | if (!density_supported) | |
4700 | fragP->tc_frag_data.is_no_density = TRUE; | |
4701 | ||
4702 | /* This function is called from subsegs_finish, which is called | |
c138bc38 | 4703 | after xtensa_end, so we can't use "use_transform" or |
43cd72b9 BW |
4704 | "use_schedule" here. */ |
4705 | if (!directive_state[directive_transform]) | |
4706 | fragP->tc_frag_data.is_no_transform = TRUE; | |
7c834684 BW |
4707 | if (directive_state[directive_longcalls]) |
4708 | fragP->tc_frag_data.use_longcalls = TRUE; | |
43cd72b9 BW |
4709 | fragP->tc_frag_data.use_absolute_literals = |
4710 | directive_state[directive_absolute_literals]; | |
4711 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4712 | } | |
4713 | ||
4714 | ||
7fa3d080 BW |
4715 | static bfd_boolean |
4716 | relaxable_section (asection *sec) | |
43cd72b9 BW |
4717 | { |
4718 | return (sec->flags & SEC_DEBUGGING) == 0; | |
4719 | } | |
4720 | ||
4721 | ||
4722 | static void | |
7fa3d080 | 4723 | xtensa_find_unmarked_state_frags (void) |
43cd72b9 BW |
4724 | { |
4725 | segT *seclist; | |
4726 | ||
4727 | /* Walk over each fragment of all of the current segments. For each | |
4728 | unmarked fragment, mark it with the same info as the previous | |
4729 | fragment. */ | |
4730 | for (seclist = &stdoutput->sections; | |
4731 | seclist && *seclist; | |
4732 | seclist = &(*seclist)->next) | |
4733 | { | |
4734 | segT sec = *seclist; | |
4735 | segment_info_type *seginfo; | |
4736 | fragS *fragP; | |
4737 | flagword flags; | |
4738 | flags = bfd_get_section_flags (stdoutput, sec); | |
4739 | if (flags & SEC_DEBUGGING) | |
4740 | continue; | |
4741 | if (!(flags & SEC_ALLOC)) | |
4742 | continue; | |
4743 | ||
4744 | seginfo = seg_info (sec); | |
4745 | if (seginfo && seginfo->frchainP) | |
4746 | { | |
4747 | fragS *last_fragP = 0; | |
4748 | for (fragP = seginfo->frchainP->frch_root; fragP; | |
4749 | fragP = fragP->fr_next) | |
4750 | { | |
4751 | if (fragP->fr_fix != 0 | |
4752 | && !fragP->tc_frag_data.is_assembly_state_set) | |
4753 | { | |
4754 | if (last_fragP == 0) | |
4755 | { | |
4756 | as_warn_where (fragP->fr_file, fragP->fr_line, | |
4757 | _("assembly state not set for first frag in section %s"), | |
4758 | sec->name); | |
4759 | } | |
4760 | else | |
4761 | { | |
4762 | fragP->tc_frag_data.is_assembly_state_set = TRUE; | |
4763 | fragP->tc_frag_data.is_no_density = | |
4764 | last_fragP->tc_frag_data.is_no_density; | |
4765 | fragP->tc_frag_data.is_no_transform = | |
4766 | last_fragP->tc_frag_data.is_no_transform; | |
7c834684 BW |
4767 | fragP->tc_frag_data.use_longcalls = |
4768 | last_fragP->tc_frag_data.use_longcalls; | |
43cd72b9 BW |
4769 | fragP->tc_frag_data.use_absolute_literals = |
4770 | last_fragP->tc_frag_data.use_absolute_literals; | |
4771 | } | |
4772 | } | |
4773 | if (fragP->tc_frag_data.is_assembly_state_set) | |
4774 | last_fragP = fragP; | |
4775 | } | |
4776 | } | |
4777 | } | |
4778 | } | |
4779 | ||
4780 | ||
4781 | static void | |
7fa3d080 BW |
4782 | xtensa_find_unaligned_branch_targets (bfd *abfd ATTRIBUTE_UNUSED, |
4783 | asection *sec, | |
4784 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4785 | { |
4786 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4787 | segment_info_type *seginfo = seg_info (sec); | |
4788 | fragS *frag = seginfo->frchainP->frch_root; | |
c138bc38 | 4789 | |
43cd72b9 | 4790 | if (flags & SEC_CODE) |
c138bc38 | 4791 | { |
43cd72b9 BW |
4792 | xtensa_isa isa = xtensa_default_isa; |
4793 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); | |
4794 | while (frag != NULL) | |
4795 | { | |
4796 | if (frag->tc_frag_data.is_branch_target) | |
4797 | { | |
4798 | int op_size; | |
664df4e4 | 4799 | addressT branch_align, frag_addr; |
43cd72b9 BW |
4800 | xtensa_format fmt; |
4801 | ||
d77b99c9 BW |
4802 | xtensa_insnbuf_from_chars |
4803 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4804 | fmt = xtensa_format_decode (isa, insnbuf); |
4805 | op_size = xtensa_format_length (isa, fmt); | |
664df4e4 BW |
4806 | branch_align = 1 << branch_align_power (sec); |
4807 | frag_addr = frag->fr_address % branch_align; | |
4808 | if (frag_addr + op_size > branch_align) | |
43cd72b9 BW |
4809 | as_warn_where (frag->fr_file, frag->fr_line, |
4810 | _("unaligned branch target: %d bytes at 0x%lx"), | |
dd49a749 | 4811 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4812 | } |
4813 | frag = frag->fr_next; | |
4814 | } | |
4815 | xtensa_insnbuf_free (isa, insnbuf); | |
4816 | } | |
4817 | } | |
4818 | ||
4819 | ||
4820 | static void | |
7fa3d080 BW |
4821 | xtensa_find_unaligned_loops (bfd *abfd ATTRIBUTE_UNUSED, |
4822 | asection *sec, | |
4823 | void *unused ATTRIBUTE_UNUSED) | |
43cd72b9 BW |
4824 | { |
4825 | flagword flags = bfd_get_section_flags (abfd, sec); | |
4826 | segment_info_type *seginfo = seg_info (sec); | |
4827 | fragS *frag = seginfo->frchainP->frch_root; | |
4828 | xtensa_isa isa = xtensa_default_isa; | |
c138bc38 | 4829 | |
43cd72b9 | 4830 | if (flags & SEC_CODE) |
c138bc38 | 4831 | { |
43cd72b9 BW |
4832 | xtensa_insnbuf insnbuf = xtensa_insnbuf_alloc (isa); |
4833 | while (frag != NULL) | |
4834 | { | |
4835 | if (frag->tc_frag_data.is_first_loop_insn) | |
4836 | { | |
4837 | int op_size; | |
d77b99c9 | 4838 | addressT frag_addr; |
43cd72b9 BW |
4839 | xtensa_format fmt; |
4840 | ||
d77b99c9 BW |
4841 | xtensa_insnbuf_from_chars |
4842 | (isa, insnbuf, (unsigned char *) frag->fr_literal, 0); | |
43cd72b9 BW |
4843 | fmt = xtensa_format_decode (isa, insnbuf); |
4844 | op_size = xtensa_format_length (isa, fmt); | |
4845 | frag_addr = frag->fr_address % xtensa_fetch_width; | |
4846 | ||
d77b99c9 | 4847 | if (frag_addr + op_size > xtensa_fetch_width) |
43cd72b9 BW |
4848 | as_warn_where (frag->fr_file, frag->fr_line, |
4849 | _("unaligned loop: %d bytes at 0x%lx"), | |
dd49a749 | 4850 | op_size, (long) frag->fr_address); |
43cd72b9 BW |
4851 | } |
4852 | frag = frag->fr_next; | |
4853 | } | |
4854 | xtensa_insnbuf_free (isa, insnbuf); | |
4855 | } | |
4856 | } | |
4857 | ||
4858 | ||
30f725a1 BW |
4859 | static int |
4860 | xg_apply_fix_value (fixS *fixP, valueT val) | |
43cd72b9 BW |
4861 | { |
4862 | xtensa_isa isa = xtensa_default_isa; | |
4863 | static xtensa_insnbuf insnbuf = NULL; | |
4864 | static xtensa_insnbuf slotbuf = NULL; | |
4865 | xtensa_format fmt; | |
4866 | int slot; | |
4867 | bfd_boolean alt_reloc; | |
4868 | xtensa_opcode opcode; | |
4869 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; | |
4870 | ||
4871 | (void) decode_reloc (fixP->fx_r_type, &slot, &alt_reloc); | |
4872 | if (alt_reloc) | |
4873 | as_fatal (_("unexpected fix")); | |
4874 | ||
4875 | if (!insnbuf) | |
4876 | { | |
4877 | insnbuf = xtensa_insnbuf_alloc (isa); | |
4878 | slotbuf = xtensa_insnbuf_alloc (isa); | |
4879 | } | |
4880 | ||
d77b99c9 | 4881 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
43cd72b9 BW |
4882 | fmt = xtensa_format_decode (isa, insnbuf); |
4883 | if (fmt == XTENSA_UNDEFINED) | |
4884 | as_fatal (_("undecodable fix")); | |
4885 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
4886 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
4887 | if (opcode == XTENSA_UNDEFINED) | |
4888 | as_fatal (_("undecodable fix")); | |
4889 | ||
4890 | /* CONST16 immediates are not PC-relative, despite the fact that we | |
4891 | reuse the normal PC-relative operand relocations for the low part | |
30f725a1 | 4892 | of a CONST16 operand. */ |
43cd72b9 | 4893 | if (opcode == xtensa_const16_opcode) |
30f725a1 | 4894 | return 0; |
43cd72b9 BW |
4895 | |
4896 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, | |
4897 | get_relaxable_immed (opcode), val, | |
4898 | fixP->fx_file, fixP->fx_line); | |
4899 | ||
4900 | xtensa_format_set_slot (isa, fmt, slot, insnbuf, slotbuf); | |
d77b99c9 | 4901 | xtensa_insnbuf_to_chars (isa, insnbuf, (unsigned char *) fixpos, 0); |
30f725a1 BW |
4902 | |
4903 | return 1; | |
43cd72b9 BW |
4904 | } |
4905 | ||
e0001a05 NC |
4906 | \f |
4907 | /* External Functions and Other GAS Hooks. */ | |
4908 | ||
4909 | const char * | |
7fa3d080 | 4910 | xtensa_target_format (void) |
e0001a05 NC |
4911 | { |
4912 | return (target_big_endian ? "elf32-xtensa-be" : "elf32-xtensa-le"); | |
4913 | } | |
4914 | ||
4915 | ||
4916 | void | |
7fa3d080 | 4917 | xtensa_file_arch_init (bfd *abfd) |
e0001a05 NC |
4918 | { |
4919 | bfd_set_private_flags (abfd, 0x100 | 0x200); | |
4920 | } | |
4921 | ||
4922 | ||
4923 | void | |
7fa3d080 | 4924 | md_number_to_chars (char *buf, valueT val, int n) |
e0001a05 NC |
4925 | { |
4926 | if (target_big_endian) | |
4927 | number_to_chars_bigendian (buf, val, n); | |
4928 | else | |
4929 | number_to_chars_littleendian (buf, val, n); | |
4930 | } | |
4931 | ||
4932 | ||
4933 | /* This function is called once, at assembler startup time. It should | |
4934 | set up all the tables, etc. that the MD part of the assembler will | |
4935 | need. */ | |
4936 | ||
4937 | void | |
7fa3d080 | 4938 | md_begin (void) |
e0001a05 NC |
4939 | { |
4940 | segT current_section = now_seg; | |
4941 | int current_subsec = now_subseg; | |
4942 | xtensa_isa isa; | |
4943 | ||
43cd72b9 | 4944 | xtensa_default_isa = xtensa_isa_init (0, 0); |
e0001a05 | 4945 | isa = xtensa_default_isa; |
e0001a05 | 4946 | |
43cd72b9 BW |
4947 | linkrelax = 1; |
4948 | ||
4949 | /* Set up the .literal, .fini.literal and .init.literal sections. */ | |
e0001a05 NC |
4950 | memset (&default_lit_sections, 0, sizeof (default_lit_sections)); |
4951 | default_lit_sections.init_lit_seg_name = INIT_LITERAL_SECTION_NAME; | |
4952 | default_lit_sections.fini_lit_seg_name = FINI_LITERAL_SECTION_NAME; | |
4953 | default_lit_sections.lit_seg_name = LITERAL_SECTION_NAME; | |
43cd72b9 | 4954 | default_lit_sections.lit4_seg_name = LIT4_SECTION_NAME; |
e0001a05 NC |
4955 | |
4956 | subseg_set (current_section, current_subsec); | |
4957 | ||
43cd72b9 BW |
4958 | xg_init_vinsn (&cur_vinsn); |
4959 | ||
e0001a05 NC |
4960 | xtensa_addi_opcode = xtensa_opcode_lookup (isa, "addi"); |
4961 | xtensa_addmi_opcode = xtensa_opcode_lookup (isa, "addmi"); | |
4962 | xtensa_call0_opcode = xtensa_opcode_lookup (isa, "call0"); | |
4963 | xtensa_call4_opcode = xtensa_opcode_lookup (isa, "call4"); | |
4964 | xtensa_call8_opcode = xtensa_opcode_lookup (isa, "call8"); | |
4965 | xtensa_call12_opcode = xtensa_opcode_lookup (isa, "call12"); | |
4966 | xtensa_callx0_opcode = xtensa_opcode_lookup (isa, "callx0"); | |
4967 | xtensa_callx4_opcode = xtensa_opcode_lookup (isa, "callx4"); | |
4968 | xtensa_callx8_opcode = xtensa_opcode_lookup (isa, "callx8"); | |
4969 | xtensa_callx12_opcode = xtensa_opcode_lookup (isa, "callx12"); | |
43cd72b9 | 4970 | xtensa_const16_opcode = xtensa_opcode_lookup (isa, "const16"); |
e0001a05 | 4971 | xtensa_entry_opcode = xtensa_opcode_lookup (isa, "entry"); |
43cd72b9 BW |
4972 | xtensa_movi_opcode = xtensa_opcode_lookup (isa, "movi"); |
4973 | xtensa_movi_n_opcode = xtensa_opcode_lookup (isa, "movi.n"); | |
e0001a05 | 4974 | xtensa_isync_opcode = xtensa_opcode_lookup (isa, "isync"); |
e0001a05 | 4975 | xtensa_jx_opcode = xtensa_opcode_lookup (isa, "jx"); |
43cd72b9 | 4976 | xtensa_l32r_opcode = xtensa_opcode_lookup (isa, "l32r"); |
e0001a05 NC |
4977 | xtensa_loop_opcode = xtensa_opcode_lookup (isa, "loop"); |
4978 | xtensa_loopnez_opcode = xtensa_opcode_lookup (isa, "loopnez"); | |
4979 | xtensa_loopgtz_opcode = xtensa_opcode_lookup (isa, "loopgtz"); | |
43cd72b9 | 4980 | xtensa_nop_opcode = xtensa_opcode_lookup (isa, "nop"); |
e0001a05 NC |
4981 | xtensa_nop_n_opcode = xtensa_opcode_lookup (isa, "nop.n"); |
4982 | xtensa_or_opcode = xtensa_opcode_lookup (isa, "or"); | |
4983 | xtensa_ret_opcode = xtensa_opcode_lookup (isa, "ret"); | |
4984 | xtensa_ret_n_opcode = xtensa_opcode_lookup (isa, "ret.n"); | |
4985 | xtensa_retw_opcode = xtensa_opcode_lookup (isa, "retw"); | |
4986 | xtensa_retw_n_opcode = xtensa_opcode_lookup (isa, "retw.n"); | |
43cd72b9 | 4987 | xtensa_rsr_lcount_opcode = xtensa_opcode_lookup (isa, "rsr.lcount"); |
e0001a05 | 4988 | xtensa_waiti_opcode = xtensa_opcode_lookup (isa, "waiti"); |
43cd72b9 BW |
4989 | |
4990 | init_op_placement_info_table (); | |
4991 | ||
4992 | /* Set up the assembly state. */ | |
4993 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
4994 | xtensa_set_frag_assembly_state (frag_now); | |
4995 | } | |
4996 | ||
4997 | ||
4998 | /* TC_INIT_FIX_DATA hook */ | |
4999 | ||
5000 | void | |
7fa3d080 | 5001 | xtensa_init_fix_data (fixS *x) |
43cd72b9 BW |
5002 | { |
5003 | x->tc_fix_data.slot = 0; | |
5004 | x->tc_fix_data.X_add_symbol = NULL; | |
5005 | x->tc_fix_data.X_add_number = 0; | |
e0001a05 NC |
5006 | } |
5007 | ||
5008 | ||
5009 | /* tc_frob_label hook */ | |
5010 | ||
5011 | void | |
7fa3d080 | 5012 | xtensa_frob_label (symbolS *sym) |
e0001a05 | 5013 | { |
3ea38ac2 BW |
5014 | float freq; |
5015 | ||
5016 | if (cur_vinsn.inside_bundle) | |
5017 | { | |
5018 | as_bad (_("labels are not valid inside bundles")); | |
5019 | return; | |
5020 | } | |
5021 | ||
5022 | freq = get_subseg_target_freq (now_seg, now_subseg); | |
7b1cc377 | 5023 | |
43cd72b9 BW |
5024 | /* Since the label was already attached to a frag associated with the |
5025 | previous basic block, it now needs to be reset to the current frag. */ | |
5026 | symbol_set_frag (sym, frag_now); | |
5027 | S_SET_VALUE (sym, (valueT) frag_now_fix ()); | |
5028 | ||
82e7541d BW |
5029 | if (generating_literals) |
5030 | xtensa_add_literal_sym (sym); | |
5031 | else | |
5032 | xtensa_add_insn_label (sym); | |
5033 | ||
7b1cc377 BW |
5034 | if (symbol_get_tc (sym)->is_loop_target) |
5035 | { | |
5036 | if ((get_last_insn_flags (now_seg, now_subseg) | |
e0001a05 | 5037 | & FLAG_IS_BAD_LOOPEND) != 0) |
7b1cc377 BW |
5038 | as_bad (_("invalid last instruction for a zero-overhead loop")); |
5039 | ||
5040 | xtensa_set_frag_assembly_state (frag_now); | |
5041 | frag_var (rs_machine_dependent, 4, 4, RELAX_LOOP_END, | |
5042 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
5043 | ||
5044 | xtensa_set_frag_assembly_state (frag_now); | |
5045 | xtensa_move_labels (frag_now, 0, TRUE); | |
07a53e5c | 5046 | } |
e0001a05 NC |
5047 | |
5048 | /* No target aligning in the absolute section. */ | |
61846f28 | 5049 | if (now_seg != absolute_section |
43cd72b9 | 5050 | && do_align_targets () |
61846f28 | 5051 | && !is_unaligned_label (sym) |
43cd72b9 BW |
5052 | && !generating_literals) |
5053 | { | |
43cd72b9 BW |
5054 | xtensa_set_frag_assembly_state (frag_now); |
5055 | ||
43cd72b9 | 5056 | frag_var (rs_machine_dependent, |
7b1cc377 | 5057 | 0, (int) freq, |
e0001a05 NC |
5058 | RELAX_DESIRE_ALIGN_IF_TARGET, |
5059 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
43cd72b9 | 5060 | xtensa_set_frag_assembly_state (frag_now); |
82e7541d | 5061 | xtensa_move_labels (frag_now, 0, TRUE); |
43cd72b9 BW |
5062 | } |
5063 | ||
5064 | /* We need to mark the following properties even if we aren't aligning. */ | |
5065 | ||
5066 | /* If the label is already known to be a branch target, i.e., a | |
5067 | forward branch, mark the frag accordingly. Backward branches | |
5068 | are handled by xg_add_branch_and_loop_targets. */ | |
5069 | if (symbol_get_tc (sym)->is_branch_target) | |
5070 | symbol_get_frag (sym)->tc_frag_data.is_branch_target = TRUE; | |
5071 | ||
5072 | /* Loops only go forward, so they can be identified here. */ | |
5073 | if (symbol_get_tc (sym)->is_loop_target) | |
5074 | symbol_get_frag (sym)->tc_frag_data.is_loop_target = TRUE; | |
07a53e5c RH |
5075 | |
5076 | dwarf2_emit_label (sym); | |
43cd72b9 BW |
5077 | } |
5078 | ||
5079 | ||
5080 | /* tc_unrecognized_line hook */ | |
5081 | ||
5082 | int | |
7fa3d080 | 5083 | xtensa_unrecognized_line (int ch) |
43cd72b9 BW |
5084 | { |
5085 | switch (ch) | |
5086 | { | |
5087 | case '{' : | |
5088 | if (cur_vinsn.inside_bundle == 0) | |
5089 | { | |
5090 | /* PR8110: Cannot emit line number info inside a FLIX bundle | |
5091 | when using --gstabs. Temporarily disable debug info. */ | |
5092 | generate_lineno_debug (); | |
5093 | if (debug_type == DEBUG_STABS) | |
5094 | { | |
5095 | xt_saved_debug_type = debug_type; | |
5096 | debug_type = DEBUG_NONE; | |
5097 | } | |
82e7541d | 5098 | |
43cd72b9 BW |
5099 | cur_vinsn.inside_bundle = 1; |
5100 | } | |
5101 | else | |
5102 | { | |
5103 | as_bad (_("extra opening brace")); | |
5104 | return 0; | |
5105 | } | |
5106 | break; | |
82e7541d | 5107 | |
43cd72b9 BW |
5108 | case '}' : |
5109 | if (cur_vinsn.inside_bundle) | |
5110 | finish_vinsn (&cur_vinsn); | |
5111 | else | |
5112 | { | |
5113 | as_bad (_("extra closing brace")); | |
5114 | return 0; | |
5115 | } | |
5116 | break; | |
5117 | default: | |
5118 | as_bad (_("syntax error")); | |
5119 | return 0; | |
e0001a05 | 5120 | } |
43cd72b9 | 5121 | return 1; |
e0001a05 NC |
5122 | } |
5123 | ||
5124 | ||
5125 | /* md_flush_pending_output hook */ | |
5126 | ||
5127 | void | |
7fa3d080 | 5128 | xtensa_flush_pending_output (void) |
e0001a05 | 5129 | { |
43cd72b9 BW |
5130 | if (cur_vinsn.inside_bundle) |
5131 | as_bad (_("missing closing brace")); | |
5132 | ||
e0001a05 NC |
5133 | /* If there is a non-zero instruction fragment, close it. */ |
5134 | if (frag_now_fix () != 0 && frag_now->tc_frag_data.is_insn) | |
5135 | { | |
5136 | frag_wane (frag_now); | |
5137 | frag_new (0); | |
43cd72b9 | 5138 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
5139 | } |
5140 | frag_now->tc_frag_data.is_insn = FALSE; | |
82e7541d BW |
5141 | |
5142 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5143 | } |
5144 | ||
5145 | ||
43cd72b9 BW |
5146 | /* We had an error while parsing an instruction. The string might look |
5147 | like this: "insn arg1, arg2 }". If so, we need to see the closing | |
5148 | brace and reset some fields. Otherwise, the vinsn never gets closed | |
5149 | and the num_slots field will grow past the end of the array of slots, | |
5150 | and bad things happen. */ | |
5151 | ||
5152 | static void | |
7fa3d080 | 5153 | error_reset_cur_vinsn (void) |
43cd72b9 BW |
5154 | { |
5155 | if (cur_vinsn.inside_bundle) | |
5156 | { | |
5157 | if (*input_line_pointer == '}' | |
5158 | || *(input_line_pointer - 1) == '}' | |
5159 | || *(input_line_pointer - 2) == '}') | |
5160 | xg_clear_vinsn (&cur_vinsn); | |
5161 | } | |
5162 | } | |
5163 | ||
5164 | ||
e0001a05 | 5165 | void |
7fa3d080 | 5166 | md_assemble (char *str) |
e0001a05 NC |
5167 | { |
5168 | xtensa_isa isa = xtensa_default_isa; | |
7c430684 | 5169 | char *opname, *file_name; |
e0001a05 NC |
5170 | unsigned opnamelen; |
5171 | bfd_boolean has_underbar = FALSE; | |
43cd72b9 | 5172 | char *arg_strings[MAX_INSN_ARGS]; |
e0001a05 | 5173 | int num_args; |
e0001a05 | 5174 | TInsn orig_insn; /* Original instruction from the input. */ |
e0001a05 | 5175 | |
e0001a05 NC |
5176 | tinsn_init (&orig_insn); |
5177 | ||
5178 | /* Split off the opcode. */ | |
5179 | opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_/0123456789."); | |
5180 | opname = xmalloc (opnamelen + 1); | |
5181 | memcpy (opname, str, opnamelen); | |
5182 | opname[opnamelen] = '\0'; | |
5183 | ||
5184 | num_args = tokenize_arguments (arg_strings, str + opnamelen); | |
5185 | if (num_args == -1) | |
5186 | { | |
5187 | as_bad (_("syntax error")); | |
5188 | return; | |
5189 | } | |
5190 | ||
5191 | if (xg_translate_idioms (&opname, &num_args, arg_strings)) | |
5192 | return; | |
5193 | ||
5194 | /* Check for an underbar prefix. */ | |
5195 | if (*opname == '_') | |
5196 | { | |
5197 | has_underbar = TRUE; | |
5198 | opname += 1; | |
5199 | } | |
5200 | ||
5201 | orig_insn.insn_type = ITYPE_INSN; | |
5202 | orig_insn.ntok = 0; | |
43cd72b9 | 5203 | orig_insn.is_specific_opcode = (has_underbar || !use_transform ()); |
e0001a05 NC |
5204 | |
5205 | orig_insn.opcode = xtensa_opcode_lookup (isa, opname); | |
5206 | if (orig_insn.opcode == XTENSA_UNDEFINED) | |
5207 | { | |
43cd72b9 BW |
5208 | xtensa_format fmt = xtensa_format_lookup (isa, opname); |
5209 | if (fmt == XTENSA_UNDEFINED) | |
5210 | { | |
5211 | as_bad (_("unknown opcode or format name '%s'"), opname); | |
5212 | error_reset_cur_vinsn (); | |
5213 | return; | |
5214 | } | |
5215 | if (!cur_vinsn.inside_bundle) | |
5216 | { | |
5217 | as_bad (_("format names only valid inside bundles")); | |
5218 | error_reset_cur_vinsn (); | |
5219 | return; | |
5220 | } | |
5221 | if (cur_vinsn.format != XTENSA_UNDEFINED) | |
5222 | as_warn (_("multiple formats specified for one bundle; using '%s'"), | |
5223 | opname); | |
5224 | cur_vinsn.format = fmt; | |
5225 | free (has_underbar ? opname - 1 : opname); | |
5226 | error_reset_cur_vinsn (); | |
e0001a05 NC |
5227 | return; |
5228 | } | |
5229 | ||
e0001a05 NC |
5230 | /* Parse the arguments. */ |
5231 | if (parse_arguments (&orig_insn, num_args, arg_strings)) | |
5232 | { | |
5233 | as_bad (_("syntax error")); | |
43cd72b9 | 5234 | error_reset_cur_vinsn (); |
e0001a05 NC |
5235 | return; |
5236 | } | |
5237 | ||
5238 | /* Free the opcode and argument strings, now that they've been parsed. */ | |
5239 | free (has_underbar ? opname - 1 : opname); | |
5240 | opname = 0; | |
5241 | while (num_args-- > 0) | |
5242 | free (arg_strings[num_args]); | |
5243 | ||
43cd72b9 BW |
5244 | /* Get expressions for invisible operands. */ |
5245 | if (get_invisible_operands (&orig_insn)) | |
5246 | { | |
5247 | error_reset_cur_vinsn (); | |
5248 | return; | |
5249 | } | |
5250 | ||
e0001a05 NC |
5251 | /* Check for the right number and type of arguments. */ |
5252 | if (tinsn_check_arguments (&orig_insn)) | |
e0001a05 | 5253 | { |
43cd72b9 BW |
5254 | error_reset_cur_vinsn (); |
5255 | return; | |
e0001a05 NC |
5256 | } |
5257 | ||
7c430684 BW |
5258 | /* A FLIX bundle may be spread across multiple input lines. We want to |
5259 | report the first such line in the debug information. Record the line | |
5260 | number for each TInsn (assume the file name doesn't change), so the | |
5261 | first line can be found later. */ | |
5262 | as_where (&file_name, &orig_insn.linenum); | |
c138bc38 | 5263 | |
43cd72b9 BW |
5264 | xg_add_branch_and_loop_targets (&orig_insn); |
5265 | ||
431ad2d0 BW |
5266 | /* Check that immediate value for ENTRY is >= 16. */ |
5267 | if (orig_insn.opcode == xtensa_entry_opcode && orig_insn.ntok >= 3) | |
e0001a05 | 5268 | { |
431ad2d0 BW |
5269 | expressionS *exp = &orig_insn.tok[2]; |
5270 | if (exp->X_op == O_constant && exp->X_add_number < 16) | |
5271 | as_warn (_("entry instruction with stack decrement < 16")); | |
e0001a05 NC |
5272 | } |
5273 | ||
e0001a05 | 5274 | /* Finish it off: |
43cd72b9 BW |
5275 | assemble_tokens (opcode, tok, ntok); |
5276 | expand the tokens from the orig_insn into the | |
5277 | stack of instructions that will not expand | |
e0001a05 | 5278 | unless required at relaxation time. */ |
e0001a05 | 5279 | |
43cd72b9 BW |
5280 | if (!cur_vinsn.inside_bundle) |
5281 | emit_single_op (&orig_insn); | |
5282 | else /* We are inside a bundle. */ | |
e0001a05 | 5283 | { |
43cd72b9 BW |
5284 | cur_vinsn.slots[cur_vinsn.num_slots] = orig_insn; |
5285 | cur_vinsn.num_slots++; | |
5286 | if (*input_line_pointer == '}' | |
5287 | || *(input_line_pointer - 1) == '}' | |
5288 | || *(input_line_pointer - 2) == '}') | |
5289 | finish_vinsn (&cur_vinsn); | |
e0001a05 NC |
5290 | } |
5291 | ||
43cd72b9 BW |
5292 | /* We've just emitted a new instruction so clear the list of labels. */ |
5293 | xtensa_clear_insn_labels (); | |
e0001a05 NC |
5294 | } |
5295 | ||
5296 | ||
43cd72b9 | 5297 | /* HANDLE_ALIGN hook */ |
e0001a05 | 5298 | |
43cd72b9 BW |
5299 | /* For a .align directive, we mark the previous block with the alignment |
5300 | information. This will be placed in the object file in the | |
5301 | property section corresponding to this section. */ | |
e0001a05 | 5302 | |
43cd72b9 | 5303 | void |
7fa3d080 | 5304 | xtensa_handle_align (fragS *fragP) |
43cd72b9 BW |
5305 | { |
5306 | if (linkrelax | |
b08b5071 | 5307 | && ! fragP->tc_frag_data.is_literal |
43cd72b9 BW |
5308 | && (fragP->fr_type == rs_align |
5309 | || fragP->fr_type == rs_align_code) | |
5310 | && fragP->fr_address + fragP->fr_fix > 0 | |
5311 | && fragP->fr_offset > 0 | |
5312 | && now_seg != bss_section) | |
e0001a05 | 5313 | { |
43cd72b9 BW |
5314 | fragP->tc_frag_data.is_align = TRUE; |
5315 | fragP->tc_frag_data.alignment = fragP->fr_offset; | |
e0001a05 NC |
5316 | } |
5317 | ||
43cd72b9 | 5318 | if (fragP->fr_type == rs_align_test) |
e0001a05 | 5319 | { |
43cd72b9 BW |
5320 | int count; |
5321 | count = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix; | |
5322 | if (count != 0) | |
c138bc38 | 5323 | as_bad_where (fragP->fr_file, fragP->fr_line, |
43cd72b9 | 5324 | _("unaligned entry instruction")); |
e0001a05 | 5325 | } |
e0001a05 | 5326 | } |
43cd72b9 | 5327 | |
e0001a05 NC |
5328 | |
5329 | /* TC_FRAG_INIT hook */ | |
5330 | ||
5331 | void | |
7fa3d080 | 5332 | xtensa_frag_init (fragS *frag) |
e0001a05 | 5333 | { |
43cd72b9 | 5334 | xtensa_set_frag_assembly_state (frag); |
e0001a05 NC |
5335 | } |
5336 | ||
5337 | ||
5338 | symbolS * | |
7fa3d080 | 5339 | md_undefined_symbol (char *name ATTRIBUTE_UNUSED) |
e0001a05 NC |
5340 | { |
5341 | return NULL; | |
5342 | } | |
5343 | ||
5344 | ||
5345 | /* Round up a section size to the appropriate boundary. */ | |
5346 | ||
5347 | valueT | |
7fa3d080 | 5348 | md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) |
e0001a05 NC |
5349 | { |
5350 | return size; /* Byte alignment is fine. */ | |
5351 | } | |
5352 | ||
5353 | ||
5354 | long | |
7fa3d080 | 5355 | md_pcrel_from (fixS *fixP) |
e0001a05 NC |
5356 | { |
5357 | char *insn_p; | |
5358 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 5359 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 | 5360 | int opnum; |
43cd72b9 | 5361 | uint32 opnd_value; |
e0001a05 | 5362 | xtensa_opcode opcode; |
43cd72b9 BW |
5363 | xtensa_format fmt; |
5364 | int slot; | |
e0001a05 NC |
5365 | xtensa_isa isa = xtensa_default_isa; |
5366 | valueT addr = fixP->fx_where + fixP->fx_frag->fr_address; | |
43cd72b9 | 5367 | bfd_boolean alt_reloc; |
e0001a05 | 5368 | |
e0001a05 | 5369 | if (fixP->fx_r_type == BFD_RELOC_XTENSA_ASM_EXPAND) |
30f725a1 | 5370 | return 0; |
e0001a05 NC |
5371 | |
5372 | if (!insnbuf) | |
43cd72b9 BW |
5373 | { |
5374 | insnbuf = xtensa_insnbuf_alloc (isa); | |
5375 | slotbuf = xtensa_insnbuf_alloc (isa); | |
5376 | } | |
e0001a05 NC |
5377 | |
5378 | insn_p = &fixP->fx_frag->fr_literal[fixP->fx_where]; | |
d77b99c9 | 5379 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) insn_p, 0); |
43cd72b9 BW |
5380 | fmt = xtensa_format_decode (isa, insnbuf); |
5381 | ||
5382 | if (fmt == XTENSA_UNDEFINED) | |
5383 | as_fatal (_("bad instruction format")); | |
5384 | ||
5385 | if (decode_reloc (fixP->fx_r_type, &slot, &alt_reloc) != 0) | |
5386 | as_fatal (_("invalid relocation")); | |
5387 | ||
5388 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
5389 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
5390 | ||
30f725a1 BW |
5391 | /* Check for "alternate" relocations (operand not specified). None |
5392 | of the current uses for these are really PC-relative. */ | |
43cd72b9 BW |
5393 | if (alt_reloc || opcode == xtensa_const16_opcode) |
5394 | { | |
5395 | if (opcode != xtensa_l32r_opcode | |
5396 | && opcode != xtensa_const16_opcode) | |
5397 | as_fatal (_("invalid relocation for '%s' instruction"), | |
5398 | xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5399 | return 0; |
e0001a05 NC |
5400 | } |
5401 | ||
43cd72b9 BW |
5402 | opnum = get_relaxable_immed (opcode); |
5403 | opnd_value = 0; | |
5404 | if (xtensa_operand_is_PCrelative (isa, opcode, opnum) != 1 | |
5405 | || xtensa_operand_do_reloc (isa, opcode, opnum, &opnd_value, addr)) | |
e0001a05 NC |
5406 | { |
5407 | as_bad_where (fixP->fx_file, | |
5408 | fixP->fx_line, | |
5409 | _("invalid relocation for operand %d of '%s'"), | |
5410 | opnum, xtensa_opcode_name (isa, opcode)); | |
30f725a1 | 5411 | return 0; |
e0001a05 | 5412 | } |
43cd72b9 BW |
5413 | return 0 - opnd_value; |
5414 | } | |
5415 | ||
5416 | ||
5417 | /* TC_FORCE_RELOCATION hook */ | |
5418 | ||
5419 | int | |
7fa3d080 | 5420 | xtensa_force_relocation (fixS *fix) |
43cd72b9 BW |
5421 | { |
5422 | switch (fix->fx_r_type) | |
30f725a1 BW |
5423 | { |
5424 | case BFD_RELOC_XTENSA_ASM_EXPAND: | |
43cd72b9 BW |
5425 | case BFD_RELOC_XTENSA_SLOT0_ALT: |
5426 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5427 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5428 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5429 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5430 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5431 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5432 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5433 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5434 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5435 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5436 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5437 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5438 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5439 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
43cd72b9 BW |
5440 | return 1; |
5441 | default: | |
5442 | break; | |
e0001a05 NC |
5443 | } |
5444 | ||
43cd72b9 BW |
5445 | if (linkrelax && fix->fx_addsy |
5446 | && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) | |
5447 | return 1; | |
5448 | ||
5449 | return generic_force_reloc (fix); | |
5450 | } | |
5451 | ||
5452 | ||
30f725a1 BW |
5453 | /* TC_VALIDATE_FIX_SUB hook */ |
5454 | ||
5455 | int | |
5456 | xtensa_validate_fix_sub (fixS *fix) | |
5457 | { | |
5458 | segT add_symbol_segment, sub_symbol_segment; | |
5459 | ||
5460 | /* The difference of two symbols should be resolved by the assembler when | |
5461 | linkrelax is not set. If the linker may relax the section containing | |
5462 | the symbols, then an Xtensa DIFF relocation must be generated so that | |
5463 | the linker knows to adjust the difference value. */ | |
5464 | if (!linkrelax || fix->fx_addsy == NULL) | |
5465 | return 0; | |
5466 | ||
5467 | /* Make sure both symbols are in the same segment, and that segment is | |
5468 | "normal" and relaxable. If the segment is not "normal", then the | |
5469 | fix is not valid. If the segment is not "relaxable", then the fix | |
5470 | should have been handled earlier. */ | |
5471 | add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); | |
5472 | if (! SEG_NORMAL (add_symbol_segment) || | |
5473 | ! relaxable_section (add_symbol_segment)) | |
5474 | return 0; | |
5475 | sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); | |
5476 | return (sub_symbol_segment == add_symbol_segment); | |
5477 | } | |
5478 | ||
5479 | ||
43cd72b9 BW |
5480 | /* NO_PSEUDO_DOT hook */ |
5481 | ||
5482 | /* This function has nothing to do with pseudo dots, but this is the | |
5483 | nearest macro to where the check needs to take place. FIXME: This | |
5484 | seems wrong. */ | |
5485 | ||
5486 | bfd_boolean | |
7fa3d080 | 5487 | xtensa_check_inside_bundle (void) |
43cd72b9 BW |
5488 | { |
5489 | if (cur_vinsn.inside_bundle && input_line_pointer[-1] == '.') | |
5490 | as_bad (_("directives are not valid inside bundles")); | |
5491 | ||
5492 | /* This function must always return FALSE because it is called via a | |
5493 | macro that has nothing to do with bundling. */ | |
5494 | return FALSE; | |
e0001a05 NC |
5495 | } |
5496 | ||
5497 | ||
43cd72b9 | 5498 | /* md_elf_section_change_hook */ |
e0001a05 NC |
5499 | |
5500 | void | |
7fa3d080 | 5501 | xtensa_elf_section_change_hook (void) |
e0001a05 | 5502 | { |
43cd72b9 BW |
5503 | /* Set up the assembly state. */ |
5504 | if (!frag_now->tc_frag_data.is_assembly_state_set) | |
5505 | xtensa_set_frag_assembly_state (frag_now); | |
e0001a05 NC |
5506 | } |
5507 | ||
5508 | ||
5509 | /* tc_fix_adjustable hook */ | |
5510 | ||
5511 | bfd_boolean | |
7fa3d080 | 5512 | xtensa_fix_adjustable (fixS *fixP) |
e0001a05 | 5513 | { |
43cd72b9 BW |
5514 | /* An offset is not allowed in combination with the difference of two |
5515 | symbols, but that cannot be easily detected after a local symbol | |
5516 | has been adjusted to a (section+offset) form. Return 0 so that such | |
5517 | an fix will not be adjusted. */ | |
5518 | if (fixP->fx_subsy && fixP->fx_addsy && fixP->fx_offset | |
5519 | && relaxable_section (S_GET_SEGMENT (fixP->fx_subsy))) | |
5520 | return 0; | |
5521 | ||
e0001a05 NC |
5522 | /* We need the symbol name for the VTABLE entries. */ |
5523 | if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT | |
5524 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) | |
5525 | return 0; | |
5526 | ||
5527 | return 1; | |
5528 | } | |
5529 | ||
5530 | ||
5531 | void | |
55cf6793 | 5532 | md_apply_fix (fixS *fixP, valueT *valP, segT seg) |
e0001a05 | 5533 | { |
30f725a1 | 5534 | char *const fixpos = fixP->fx_frag->fr_literal + fixP->fx_where; |
d47d412e | 5535 | valueT val = 0; |
30f725a1 | 5536 | |
e7da6241 BW |
5537 | /* Subtracted symbols are only allowed for a few relocation types, and |
5538 | unless linkrelax is enabled, they should not make it to this point. */ | |
5539 | if (fixP->fx_subsy && !(linkrelax && (fixP->fx_r_type == BFD_RELOC_32 | |
5540 | || fixP->fx_r_type == BFD_RELOC_16 | |
5541 | || fixP->fx_r_type == BFD_RELOC_8))) | |
5542 | as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); | |
5543 | ||
30f725a1 | 5544 | switch (fixP->fx_r_type) |
e0001a05 | 5545 | { |
30f725a1 BW |
5546 | case BFD_RELOC_32: |
5547 | case BFD_RELOC_16: | |
5548 | case BFD_RELOC_8: | |
e7da6241 | 5549 | if (fixP->fx_subsy) |
30f725a1 BW |
5550 | { |
5551 | switch (fixP->fx_r_type) | |
5552 | { | |
5553 | case BFD_RELOC_8: | |
5554 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; | |
5555 | break; | |
5556 | case BFD_RELOC_16: | |
5557 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; | |
5558 | break; | |
5559 | case BFD_RELOC_32: | |
5560 | fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; | |
5561 | break; | |
5562 | default: | |
5563 | break; | |
5564 | } | |
e0001a05 | 5565 | |
30f725a1 BW |
5566 | /* An offset is only allowed when it results from adjusting a |
5567 | local symbol into a section-relative offset. If the offset | |
5568 | came from the original expression, tc_fix_adjustable will have | |
5569 | prevented the fix from being converted to a section-relative | |
5570 | form so that we can flag the error here. */ | |
5571 | if (fixP->fx_offset != 0 && !symbol_section_p (fixP->fx_addsy)) | |
5572 | as_bad_where (fixP->fx_file, fixP->fx_line, | |
5573 | _("cannot represent subtraction with an offset")); | |
5574 | ||
5575 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5576 | - S_GET_VALUE (fixP->fx_subsy)); | |
5577 | ||
5578 | /* The difference value gets written out, and the DIFF reloc | |
5579 | identifies the address of the subtracted symbol (i.e., the one | |
5580 | with the lowest address). */ | |
5581 | *valP = val; | |
5582 | fixP->fx_offset -= val; | |
5583 | fixP->fx_subsy = NULL; | |
5584 | } | |
5585 | else if (! fixP->fx_addsy) | |
e0001a05 | 5586 | { |
30f725a1 | 5587 | val = *valP; |
e0001a05 | 5588 | fixP->fx_done = 1; |
30f725a1 | 5589 | } |
d47d412e BW |
5590 | /* fall through */ |
5591 | ||
5592 | case BFD_RELOC_XTENSA_PLT: | |
30f725a1 BW |
5593 | md_number_to_chars (fixpos, val, fixP->fx_size); |
5594 | fixP->fx_no_overflow = 0; /* Use the standard overflow check. */ | |
5595 | break; | |
e0001a05 | 5596 | |
30f725a1 BW |
5597 | case BFD_RELOC_XTENSA_SLOT0_OP: |
5598 | case BFD_RELOC_XTENSA_SLOT1_OP: | |
5599 | case BFD_RELOC_XTENSA_SLOT2_OP: | |
5600 | case BFD_RELOC_XTENSA_SLOT3_OP: | |
5601 | case BFD_RELOC_XTENSA_SLOT4_OP: | |
5602 | case BFD_RELOC_XTENSA_SLOT5_OP: | |
5603 | case BFD_RELOC_XTENSA_SLOT6_OP: | |
5604 | case BFD_RELOC_XTENSA_SLOT7_OP: | |
5605 | case BFD_RELOC_XTENSA_SLOT8_OP: | |
5606 | case BFD_RELOC_XTENSA_SLOT9_OP: | |
5607 | case BFD_RELOC_XTENSA_SLOT10_OP: | |
5608 | case BFD_RELOC_XTENSA_SLOT11_OP: | |
5609 | case BFD_RELOC_XTENSA_SLOT12_OP: | |
5610 | case BFD_RELOC_XTENSA_SLOT13_OP: | |
5611 | case BFD_RELOC_XTENSA_SLOT14_OP: | |
5612 | if (linkrelax) | |
5613 | { | |
5614 | /* Write the tentative value of a PC-relative relocation to a | |
5615 | local symbol into the instruction. The value will be ignored | |
5616 | by the linker, and it makes the object file disassembly | |
5617 | readable when all branch targets are encoded in relocations. */ | |
5618 | ||
5619 | assert (fixP->fx_addsy); | |
5620 | if (S_GET_SEGMENT (fixP->fx_addsy) == seg && !fixP->fx_plt | |
5621 | && !S_FORCE_RELOC (fixP->fx_addsy, 1)) | |
5622 | { | |
5623 | val = (S_GET_VALUE (fixP->fx_addsy) + fixP->fx_offset | |
5624 | - md_pcrel_from (fixP)); | |
5625 | (void) xg_apply_fix_value (fixP, val); | |
5626 | } | |
5627 | } | |
5628 | else if (! fixP->fx_addsy) | |
5629 | { | |
5630 | val = *valP; | |
5631 | if (xg_apply_fix_value (fixP, val)) | |
5632 | fixP->fx_done = 1; | |
5633 | } | |
5634 | break; | |
e0001a05 | 5635 | |
30f725a1 BW |
5636 | case BFD_RELOC_XTENSA_ASM_EXPAND: |
5637 | case BFD_RELOC_XTENSA_SLOT0_ALT: | |
5638 | case BFD_RELOC_XTENSA_SLOT1_ALT: | |
5639 | case BFD_RELOC_XTENSA_SLOT2_ALT: | |
5640 | case BFD_RELOC_XTENSA_SLOT3_ALT: | |
5641 | case BFD_RELOC_XTENSA_SLOT4_ALT: | |
5642 | case BFD_RELOC_XTENSA_SLOT5_ALT: | |
5643 | case BFD_RELOC_XTENSA_SLOT6_ALT: | |
5644 | case BFD_RELOC_XTENSA_SLOT7_ALT: | |
5645 | case BFD_RELOC_XTENSA_SLOT8_ALT: | |
5646 | case BFD_RELOC_XTENSA_SLOT9_ALT: | |
5647 | case BFD_RELOC_XTENSA_SLOT10_ALT: | |
5648 | case BFD_RELOC_XTENSA_SLOT11_ALT: | |
5649 | case BFD_RELOC_XTENSA_SLOT12_ALT: | |
5650 | case BFD_RELOC_XTENSA_SLOT13_ALT: | |
5651 | case BFD_RELOC_XTENSA_SLOT14_ALT: | |
5652 | /* These all need to be resolved at link-time. Do nothing now. */ | |
5653 | break; | |
e0001a05 | 5654 | |
30f725a1 BW |
5655 | case BFD_RELOC_VTABLE_INHERIT: |
5656 | case BFD_RELOC_VTABLE_ENTRY: | |
5657 | fixP->fx_done = 0; | |
5658 | break; | |
e0001a05 | 5659 | |
30f725a1 BW |
5660 | default: |
5661 | as_bad (_("unhandled local relocation fix %s"), | |
5662 | bfd_get_reloc_code_name (fixP->fx_r_type)); | |
e0001a05 NC |
5663 | } |
5664 | } | |
5665 | ||
5666 | ||
5667 | char * | |
7fa3d080 | 5668 | md_atof (int type, char *litP, int *sizeP) |
e0001a05 NC |
5669 | { |
5670 | int prec; | |
5671 | LITTLENUM_TYPE words[4]; | |
5672 | char *t; | |
5673 | int i; | |
5674 | ||
5675 | switch (type) | |
5676 | { | |
5677 | case 'f': | |
5678 | prec = 2; | |
5679 | break; | |
5680 | ||
5681 | case 'd': | |
5682 | prec = 4; | |
5683 | break; | |
5684 | ||
5685 | default: | |
5686 | *sizeP = 0; | |
5687 | return "bad call to md_atof"; | |
5688 | } | |
5689 | ||
5690 | t = atof_ieee (input_line_pointer, type, words); | |
5691 | if (t) | |
5692 | input_line_pointer = t; | |
5693 | ||
5694 | *sizeP = prec * 2; | |
5695 | ||
5696 | for (i = prec - 1; i >= 0; i--) | |
5697 | { | |
5698 | int idx = i; | |
5699 | if (target_big_endian) | |
5700 | idx = (prec - 1 - i); | |
5701 | ||
5702 | md_number_to_chars (litP, (valueT) words[idx], 2); | |
5703 | litP += 2; | |
5704 | } | |
5705 | ||
5706 | return NULL; | |
5707 | } | |
5708 | ||
5709 | ||
5710 | int | |
7fa3d080 | 5711 | md_estimate_size_before_relax (fragS *fragP, segT seg ATTRIBUTE_UNUSED) |
e0001a05 | 5712 | { |
34e41783 | 5713 | return total_frag_text_expansion (fragP); |
e0001a05 NC |
5714 | } |
5715 | ||
5716 | ||
5717 | /* Translate internal representation of relocation info to BFD target | |
5718 | format. */ | |
5719 | ||
5720 | arelent * | |
30f725a1 | 5721 | tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp) |
e0001a05 NC |
5722 | { |
5723 | arelent *reloc; | |
5724 | ||
5725 | reloc = (arelent *) xmalloc (sizeof (arelent)); | |
5726 | reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); | |
5727 | *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); | |
5728 | reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; | |
5729 | ||
5730 | /* Make sure none of our internal relocations make it this far. | |
5731 | They'd better have been fully resolved by this point. */ | |
5732 | assert ((int) fixp->fx_r_type > 0); | |
5733 | ||
30f725a1 | 5734 | reloc->addend = fixp->fx_offset; |
43cd72b9 | 5735 | |
e0001a05 NC |
5736 | reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); |
5737 | if (reloc->howto == NULL) | |
5738 | { | |
5739 | as_bad_where (fixp->fx_file, fixp->fx_line, | |
5740 | _("cannot represent `%s' relocation in object file"), | |
5741 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
43cd72b9 BW |
5742 | free (reloc->sym_ptr_ptr); |
5743 | free (reloc); | |
e0001a05 NC |
5744 | return NULL; |
5745 | } | |
5746 | ||
5747 | if (!fixp->fx_pcrel != !reloc->howto->pc_relative) | |
43cd72b9 BW |
5748 | as_fatal (_("internal error? cannot generate `%s' relocation"), |
5749 | bfd_get_reloc_code_name (fixp->fx_r_type)); | |
e0001a05 | 5750 | |
e0001a05 NC |
5751 | return reloc; |
5752 | } | |
5753 | ||
7fa3d080 BW |
5754 | \f |
5755 | /* Checks for resource conflicts between instructions. */ | |
5756 | ||
c138bc38 BW |
5757 | /* The func unit stuff could be implemented as bit-vectors rather |
5758 | than the iterative approach here. If it ends up being too | |
7fa3d080 BW |
5759 | slow, we will switch it. */ |
5760 | ||
c138bc38 | 5761 | resource_table * |
7fa3d080 BW |
5762 | new_resource_table (void *data, |
5763 | int cycles, | |
5764 | int nu, | |
5765 | unit_num_copies_func uncf, | |
5766 | opcode_num_units_func onuf, | |
5767 | opcode_funcUnit_use_unit_func ouuf, | |
5768 | opcode_funcUnit_use_stage_func ousf) | |
5769 | { | |
5770 | int i; | |
5771 | resource_table *rt = (resource_table *) xmalloc (sizeof (resource_table)); | |
5772 | rt->data = data; | |
5773 | rt->cycles = cycles; | |
5774 | rt->allocated_cycles = cycles; | |
5775 | rt->num_units = nu; | |
5776 | rt->unit_num_copies = uncf; | |
5777 | rt->opcode_num_units = onuf; | |
5778 | rt->opcode_unit_use = ouuf; | |
5779 | rt->opcode_unit_stage = ousf; | |
5780 | ||
0bf60745 | 5781 | rt->units = (unsigned char **) xcalloc (cycles, sizeof (unsigned char *)); |
7fa3d080 | 5782 | for (i = 0; i < cycles; i++) |
0bf60745 | 5783 | rt->units[i] = (unsigned char *) xcalloc (nu, sizeof (unsigned char)); |
7fa3d080 BW |
5784 | |
5785 | return rt; | |
5786 | } | |
5787 | ||
5788 | ||
c138bc38 | 5789 | void |
7fa3d080 BW |
5790 | clear_resource_table (resource_table *rt) |
5791 | { | |
5792 | int i, j; | |
5793 | for (i = 0; i < rt->allocated_cycles; i++) | |
5794 | for (j = 0; j < rt->num_units; j++) | |
5795 | rt->units[i][j] = 0; | |
5796 | } | |
5797 | ||
5798 | ||
5799 | /* We never shrink it, just fake it into thinking so. */ | |
5800 | ||
c138bc38 | 5801 | void |
7fa3d080 BW |
5802 | resize_resource_table (resource_table *rt, int cycles) |
5803 | { | |
5804 | int i, old_cycles; | |
5805 | ||
5806 | rt->cycles = cycles; | |
5807 | if (cycles <= rt->allocated_cycles) | |
5808 | return; | |
5809 | ||
5810 | old_cycles = rt->allocated_cycles; | |
5811 | rt->allocated_cycles = cycles; | |
5812 | ||
0bf60745 BW |
5813 | rt->units = xrealloc (rt->units, |
5814 | rt->allocated_cycles * sizeof (unsigned char *)); | |
7fa3d080 | 5815 | for (i = 0; i < old_cycles; i++) |
0bf60745 BW |
5816 | rt->units[i] = xrealloc (rt->units[i], |
5817 | rt->num_units * sizeof (unsigned char)); | |
7fa3d080 | 5818 | for (i = old_cycles; i < cycles; i++) |
0bf60745 | 5819 | rt->units[i] = xcalloc (rt->num_units, sizeof (unsigned char)); |
7fa3d080 BW |
5820 | } |
5821 | ||
5822 | ||
c138bc38 | 5823 | bfd_boolean |
7fa3d080 BW |
5824 | resources_available (resource_table *rt, xtensa_opcode opcode, int cycle) |
5825 | { | |
5826 | int i; | |
5827 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5828 | ||
c138bc38 | 5829 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5830 | { |
5831 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5832 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
5833 | int copies_in_use = rt->units[stage + cycle][unit]; | |
5834 | int copies = (rt->unit_num_copies) (rt->data, unit); | |
5835 | if (copies_in_use >= copies) | |
5836 | return FALSE; | |
5837 | } | |
5838 | return TRUE; | |
5839 | } | |
7fa3d080 | 5840 | |
c138bc38 BW |
5841 | |
5842 | void | |
7fa3d080 BW |
5843 | reserve_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5844 | { | |
5845 | int i; | |
5846 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5847 | ||
c138bc38 | 5848 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5849 | { |
5850 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5851 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
c138bc38 BW |
5852 | /* Note that this allows resources to be oversubscribed. That's |
5853 | essential to the way the optional scheduler works. | |
7fa3d080 BW |
5854 | resources_available reports when a resource is over-subscribed, |
5855 | so it's easy to tell. */ | |
5856 | rt->units[stage + cycle][unit]++; | |
5857 | } | |
5858 | } | |
5859 | ||
5860 | ||
c138bc38 | 5861 | void |
7fa3d080 BW |
5862 | release_resources (resource_table *rt, xtensa_opcode opcode, int cycle) |
5863 | { | |
5864 | int i; | |
5865 | int uses = (rt->opcode_num_units) (rt->data, opcode); | |
5866 | ||
c138bc38 | 5867 | for (i = 0; i < uses; i++) |
7fa3d080 BW |
5868 | { |
5869 | xtensa_funcUnit unit = (rt->opcode_unit_use) (rt->data, opcode, i); | |
5870 | int stage = (rt->opcode_unit_stage) (rt->data, opcode, i); | |
0bf60745 | 5871 | assert (rt->units[stage + cycle][unit] > 0); |
7fa3d080 | 5872 | rt->units[stage + cycle][unit]--; |
7fa3d080 BW |
5873 | } |
5874 | } | |
c138bc38 | 5875 | |
7fa3d080 BW |
5876 | |
5877 | /* Wrapper functions make parameterized resource reservation | |
5878 | more convenient. */ | |
5879 | ||
c138bc38 | 5880 | int |
7fa3d080 BW |
5881 | opcode_funcUnit_use_unit (void *data, xtensa_opcode opcode, int idx) |
5882 | { | |
5883 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
c138bc38 | 5884 | return use->unit; |
7fa3d080 BW |
5885 | } |
5886 | ||
5887 | ||
c138bc38 | 5888 | int |
7fa3d080 BW |
5889 | opcode_funcUnit_use_stage (void *data, xtensa_opcode opcode, int idx) |
5890 | { | |
5891 | xtensa_funcUnit_use *use = xtensa_opcode_funcUnit_use (data, opcode, idx); | |
5892 | return use->stage; | |
5893 | } | |
5894 | ||
5895 | ||
5896 | /* Note that this function does not check issue constraints, but | |
5897 | solely whether the hardware is available to execute the given | |
c138bc38 | 5898 | instructions together. It also doesn't check if the tinsns |
7fa3d080 | 5899 | write the same state, or access the same tieports. That is |
a1ace8d8 | 5900 | checked by check_t1_t2_reads_and_writes. */ |
7fa3d080 BW |
5901 | |
5902 | static bfd_boolean | |
5903 | resources_conflict (vliw_insn *vinsn) | |
5904 | { | |
5905 | int i; | |
5906 | static resource_table *rt = NULL; | |
5907 | ||
5908 | /* This is the most common case by far. Optimize it. */ | |
5909 | if (vinsn->num_slots == 1) | |
5910 | return FALSE; | |
43cd72b9 | 5911 | |
c138bc38 | 5912 | if (rt == NULL) |
7fa3d080 BW |
5913 | { |
5914 | xtensa_isa isa = xtensa_default_isa; | |
5915 | rt = new_resource_table | |
5916 | (isa, xtensa_isa_num_pipe_stages (isa), | |
5917 | xtensa_isa_num_funcUnits (isa), | |
5918 | (unit_num_copies_func) xtensa_funcUnit_num_copies, | |
5919 | (opcode_num_units_func) xtensa_opcode_num_funcUnit_uses, | |
5920 | opcode_funcUnit_use_unit, | |
5921 | opcode_funcUnit_use_stage); | |
5922 | } | |
43cd72b9 | 5923 | |
7fa3d080 | 5924 | clear_resource_table (rt); |
43cd72b9 | 5925 | |
7fa3d080 BW |
5926 | for (i = 0; i < vinsn->num_slots; i++) |
5927 | { | |
5928 | if (!resources_available (rt, vinsn->slots[i].opcode, 0)) | |
5929 | return TRUE; | |
5930 | reserve_resources (rt, vinsn->slots[i].opcode, 0); | |
5931 | } | |
e0001a05 | 5932 | |
7fa3d080 BW |
5933 | return FALSE; |
5934 | } | |
e0001a05 | 5935 | |
7fa3d080 BW |
5936 | \f |
5937 | /* finish_vinsn, emit_single_op and helper functions. */ | |
e0001a05 | 5938 | |
7fa3d080 BW |
5939 | static bfd_boolean find_vinsn_conflicts (vliw_insn *); |
5940 | static xtensa_format xg_find_narrowest_format (vliw_insn *); | |
7fa3d080 | 5941 | static void xg_assemble_vliw_tokens (vliw_insn *); |
e0001a05 NC |
5942 | |
5943 | ||
43cd72b9 BW |
5944 | /* We have reached the end of a bundle; emit into the frag. */ |
5945 | ||
e0001a05 | 5946 | static void |
7fa3d080 | 5947 | finish_vinsn (vliw_insn *vinsn) |
e0001a05 | 5948 | { |
43cd72b9 BW |
5949 | IStack slotstack; |
5950 | int i; | |
5951 | char *file_name; | |
d77b99c9 | 5952 | unsigned line; |
e0001a05 | 5953 | |
43cd72b9 | 5954 | if (find_vinsn_conflicts (vinsn)) |
a1ace8d8 BW |
5955 | { |
5956 | xg_clear_vinsn (vinsn); | |
5957 | return; | |
5958 | } | |
43cd72b9 BW |
5959 | |
5960 | /* First, find a format that works. */ | |
5961 | if (vinsn->format == XTENSA_UNDEFINED) | |
5962 | vinsn->format = xg_find_narrowest_format (vinsn); | |
5963 | ||
5964 | if (vinsn->format == XTENSA_UNDEFINED) | |
5965 | { | |
5966 | as_where (&file_name, &line); | |
5967 | as_bad_where (file_name, line, | |
5968 | _("couldn't find a valid instruction format")); | |
5969 | fprintf (stderr, _(" ops were: ")); | |
5970 | for (i = 0; i < vinsn->num_slots; i++) | |
5971 | fprintf (stderr, _(" %s;"), | |
5972 | xtensa_opcode_name (xtensa_default_isa, | |
5973 | vinsn->slots[i].opcode)); | |
5974 | fprintf (stderr, _("\n")); | |
5975 | xg_clear_vinsn (vinsn); | |
5976 | return; | |
5977 | } | |
5978 | ||
5979 | if (vinsn->num_slots | |
5980 | != xtensa_format_num_slots (xtensa_default_isa, vinsn->format)) | |
e0001a05 | 5981 | { |
43cd72b9 BW |
5982 | as_bad (_("format '%s' allows %d slots, but there are %d opcodes"), |
5983 | xtensa_format_name (xtensa_default_isa, vinsn->format), | |
5984 | xtensa_format_num_slots (xtensa_default_isa, vinsn->format), | |
5985 | vinsn->num_slots); | |
5986 | xg_clear_vinsn (vinsn); | |
5987 | return; | |
5988 | } | |
e0001a05 | 5989 | |
c138bc38 | 5990 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
5991 | { |
5992 | as_where (&file_name, &line); | |
5993 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
5994 | fprintf (stderr, " ops were: "); | |
5995 | for (i = 0; i < vinsn->num_slots; i++) | |
5996 | fprintf (stderr, " %s;", | |
5997 | xtensa_opcode_name (xtensa_default_isa, | |
5998 | vinsn->slots[i].opcode)); | |
5999 | fprintf (stderr, "\n"); | |
6000 | xg_clear_vinsn (vinsn); | |
6001 | return; | |
6002 | } | |
6003 | ||
6004 | for (i = 0; i < vinsn->num_slots; i++) | |
6005 | { | |
6006 | if (vinsn->slots[i].opcode != XTENSA_UNDEFINED) | |
e0001a05 | 6007 | { |
43cd72b9 BW |
6008 | symbolS *lit_sym = NULL; |
6009 | int j; | |
6010 | bfd_boolean e = FALSE; | |
6011 | bfd_boolean saved_density = density_supported; | |
6012 | ||
6013 | /* We don't want to narrow ops inside multi-slot bundles. */ | |
6014 | if (vinsn->num_slots > 1) | |
6015 | density_supported = FALSE; | |
6016 | ||
6017 | istack_init (&slotstack); | |
6018 | if (vinsn->slots[i].opcode == xtensa_nop_opcode) | |
e0001a05 | 6019 | { |
43cd72b9 BW |
6020 | vinsn->slots[i].opcode = |
6021 | xtensa_format_slot_nop_opcode (xtensa_default_isa, | |
6022 | vinsn->format, i); | |
6023 | vinsn->slots[i].ntok = 0; | |
6024 | } | |
e0001a05 | 6025 | |
43cd72b9 BW |
6026 | if (xg_expand_assembly_insn (&slotstack, &vinsn->slots[i])) |
6027 | { | |
6028 | e = TRUE; | |
6029 | continue; | |
e0001a05 | 6030 | } |
e0001a05 | 6031 | |
43cd72b9 | 6032 | density_supported = saved_density; |
e0001a05 | 6033 | |
43cd72b9 BW |
6034 | if (e) |
6035 | { | |
6036 | xg_clear_vinsn (vinsn); | |
6037 | return; | |
6038 | } | |
e0001a05 | 6039 | |
0fa77c95 | 6040 | for (j = 0; j < slotstack.ninsn; j++) |
43cd72b9 BW |
6041 | { |
6042 | TInsn *insn = &slotstack.insn[j]; | |
6043 | if (insn->insn_type == ITYPE_LITERAL) | |
6044 | { | |
6045 | assert (lit_sym == NULL); | |
6046 | lit_sym = xg_assemble_literal (insn); | |
6047 | } | |
6048 | else | |
6049 | { | |
0fa77c95 | 6050 | assert (insn->insn_type == ITYPE_INSN); |
43cd72b9 BW |
6051 | if (lit_sym) |
6052 | xg_resolve_literals (insn, lit_sym); | |
0fa77c95 BW |
6053 | if (j != slotstack.ninsn - 1) |
6054 | emit_single_op (insn); | |
43cd72b9 BW |
6055 | } |
6056 | } | |
6057 | ||
6058 | if (vinsn->num_slots > 1) | |
6059 | { | |
6060 | if (opcode_fits_format_slot | |
6061 | (slotstack.insn[slotstack.ninsn - 1].opcode, | |
6062 | vinsn->format, i)) | |
6063 | { | |
6064 | vinsn->slots[i] = slotstack.insn[slotstack.ninsn - 1]; | |
6065 | } | |
6066 | else | |
6067 | { | |
b2d179be | 6068 | emit_single_op (&slotstack.insn[slotstack.ninsn - 1]); |
43cd72b9 BW |
6069 | if (vinsn->format == XTENSA_UNDEFINED) |
6070 | vinsn->slots[i].opcode = xtensa_nop_opcode; | |
6071 | else | |
c138bc38 | 6072 | vinsn->slots[i].opcode |
43cd72b9 BW |
6073 | = xtensa_format_slot_nop_opcode (xtensa_default_isa, |
6074 | vinsn->format, i); | |
6075 | ||
6076 | vinsn->slots[i].ntok = 0; | |
6077 | } | |
6078 | } | |
6079 | else | |
6080 | { | |
6081 | vinsn->slots[0] = slotstack.insn[slotstack.ninsn - 1]; | |
6082 | vinsn->format = XTENSA_UNDEFINED; | |
6083 | } | |
6084 | } | |
6085 | } | |
6086 | ||
6087 | /* Now check resource conflicts on the modified bundle. */ | |
c138bc38 | 6088 | if (resources_conflict (vinsn)) |
43cd72b9 BW |
6089 | { |
6090 | as_where (&file_name, &line); | |
6091 | as_bad_where (file_name, line, _("illegal resource usage in bundle")); | |
6092 | fprintf (stderr, " ops were: "); | |
6093 | for (i = 0; i < vinsn->num_slots; i++) | |
6094 | fprintf (stderr, " %s;", | |
6095 | xtensa_opcode_name (xtensa_default_isa, | |
6096 | vinsn->slots[i].opcode)); | |
6097 | fprintf (stderr, "\n"); | |
6098 | xg_clear_vinsn (vinsn); | |
6099 | return; | |
6100 | } | |
6101 | ||
6102 | /* First, find a format that works. */ | |
6103 | if (vinsn->format == XTENSA_UNDEFINED) | |
6104 | vinsn->format = xg_find_narrowest_format (vinsn); | |
6105 | ||
6106 | xg_assemble_vliw_tokens (vinsn); | |
6107 | ||
6108 | xg_clear_vinsn (vinsn); | |
6109 | } | |
6110 | ||
6111 | ||
6112 | /* Given an vliw instruction, what conflicts are there in register | |
6113 | usage and in writes to states and queues? | |
6114 | ||
6115 | This function does two things: | |
6116 | 1. Reports an error when a vinsn contains illegal combinations | |
6117 | of writes to registers states or queues. | |
6118 | 2. Marks individual tinsns as not relaxable if the combination | |
6119 | contains antidependencies. | |
6120 | ||
6121 | Job 2 handles things like swap semantics in instructions that need | |
6122 | to be relaxed. For example, | |
6123 | ||
6124 | addi a0, a1, 100000 | |
6125 | ||
6126 | normally would be relaxed to | |
6127 | ||
6128 | l32r a0, some_label | |
6129 | add a0, a1, a0 | |
6130 | ||
6131 | _but_, if the above instruction is bundled with an a0 reader, e.g., | |
6132 | ||
6133 | { addi a0, a1, 10000 ; add a2, a0, a4 ; } | |
6134 | ||
6135 | then we can't relax it into | |
6136 | ||
6137 | l32r a0, some_label | |
6138 | { add a0, a1, a0 ; add a2, a0, a4 ; } | |
6139 | ||
6140 | because the value of a0 is trashed before the second add can read it. */ | |
6141 | ||
7fa3d080 BW |
6142 | static char check_t1_t2_reads_and_writes (TInsn *, TInsn *); |
6143 | ||
43cd72b9 | 6144 | static bfd_boolean |
7fa3d080 | 6145 | find_vinsn_conflicts (vliw_insn *vinsn) |
43cd72b9 BW |
6146 | { |
6147 | int i, j; | |
6148 | int branches = 0; | |
6149 | xtensa_isa isa = xtensa_default_isa; | |
6150 | ||
6151 | assert (!past_xtensa_end); | |
6152 | ||
6153 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6154 | { | |
6155 | TInsn *op1 = &vinsn->slots[i]; | |
6156 | if (op1->is_specific_opcode) | |
6157 | op1->keep_wide = TRUE; | |
6158 | else | |
6159 | op1->keep_wide = FALSE; | |
6160 | } | |
6161 | ||
6162 | for (i = 0 ; i < vinsn->num_slots; i++) | |
6163 | { | |
6164 | TInsn *op1 = &vinsn->slots[i]; | |
6165 | ||
6166 | if (xtensa_opcode_is_branch (isa, op1->opcode) == 1) | |
6167 | branches++; | |
6168 | ||
6169 | for (j = 0; j < vinsn->num_slots; j++) | |
6170 | { | |
6171 | if (i != j) | |
6172 | { | |
6173 | TInsn *op2 = &vinsn->slots[j]; | |
6174 | char conflict_type = check_t1_t2_reads_and_writes (op1, op2); | |
6175 | switch (conflict_type) | |
6176 | { | |
6177 | case 'c': | |
6178 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same register"), | |
6179 | xtensa_opcode_name (isa, op1->opcode), i, | |
6180 | xtensa_opcode_name (isa, op2->opcode), j); | |
6181 | return TRUE; | |
6182 | case 'd': | |
6183 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same state"), | |
6184 | xtensa_opcode_name (isa, op1->opcode), i, | |
6185 | xtensa_opcode_name (isa, op2->opcode), j); | |
6186 | return TRUE; | |
6187 | case 'e': | |
53dfbcc7 | 6188 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) write the same port"), |
43cd72b9 BW |
6189 | xtensa_opcode_name (isa, op1->opcode), i, |
6190 | xtensa_opcode_name (isa, op2->opcode), j); | |
6191 | return TRUE; | |
6192 | case 'f': | |
53dfbcc7 | 6193 | as_bad (_("opcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accesses"), |
43cd72b9 BW |
6194 | xtensa_opcode_name (isa, op1->opcode), i, |
6195 | xtensa_opcode_name (isa, op2->opcode), j); | |
6196 | return TRUE; | |
6197 | default: | |
6198 | /* Everything is OK. */ | |
6199 | break; | |
6200 | } | |
6201 | op2->is_specific_opcode = (op2->is_specific_opcode | |
6202 | || conflict_type == 'a'); | |
6203 | } | |
6204 | } | |
6205 | } | |
6206 | ||
6207 | if (branches > 1) | |
6208 | { | |
6209 | as_bad (_("multiple branches or jumps in the same bundle")); | |
6210 | return TRUE; | |
6211 | } | |
6212 | ||
6213 | return FALSE; | |
6214 | } | |
6215 | ||
6216 | ||
a1ace8d8 | 6217 | /* Check how the state used by t1 and t2 relate. |
43cd72b9 BW |
6218 | Cases found are: |
6219 | ||
6220 | case A: t1 reads a register t2 writes (an antidependency within a bundle) | |
6221 | case B: no relationship between what is read and written (both could | |
6222 | read the same reg though) | |
c138bc38 | 6223 | case C: t1 writes a register t2 writes (a register conflict within a |
43cd72b9 BW |
6224 | bundle) |
6225 | case D: t1 writes a state that t2 also writes | |
6226 | case E: t1 writes a tie queue that t2 also writes | |
a1ace8d8 | 6227 | case F: two volatile queue accesses |
43cd72b9 BW |
6228 | */ |
6229 | ||
6230 | static char | |
7fa3d080 | 6231 | check_t1_t2_reads_and_writes (TInsn *t1, TInsn *t2) |
43cd72b9 BW |
6232 | { |
6233 | xtensa_isa isa = xtensa_default_isa; | |
6234 | xtensa_regfile t1_regfile, t2_regfile; | |
6235 | int t1_reg, t2_reg; | |
6236 | int t1_base_reg, t1_last_reg; | |
6237 | int t2_base_reg, t2_last_reg; | |
6238 | char t1_inout, t2_inout; | |
6239 | int i, j; | |
6240 | char conflict = 'b'; | |
6241 | int t1_states; | |
6242 | int t2_states; | |
6243 | int t1_interfaces; | |
6244 | int t2_interfaces; | |
6245 | bfd_boolean t1_volatile = FALSE; | |
6246 | bfd_boolean t2_volatile = FALSE; | |
6247 | ||
6248 | /* Check registers. */ | |
6249 | for (j = 0; j < t2->ntok; j++) | |
6250 | { | |
6251 | if (xtensa_operand_is_register (isa, t2->opcode, j) != 1) | |
6252 | continue; | |
6253 | ||
6254 | t2_regfile = xtensa_operand_regfile (isa, t2->opcode, j); | |
6255 | t2_base_reg = t2->tok[j].X_add_number; | |
6256 | t2_last_reg = t2_base_reg + xtensa_operand_num_regs (isa, t2->opcode, j); | |
6257 | ||
6258 | for (i = 0; i < t1->ntok; i++) | |
6259 | { | |
6260 | if (xtensa_operand_is_register (isa, t1->opcode, i) != 1) | |
6261 | continue; | |
6262 | ||
6263 | t1_regfile = xtensa_operand_regfile (isa, t1->opcode, i); | |
6264 | ||
6265 | if (t1_regfile != t2_regfile) | |
6266 | continue; | |
6267 | ||
6268 | t1_inout = xtensa_operand_inout (isa, t1->opcode, i); | |
6269 | t2_inout = xtensa_operand_inout (isa, t2->opcode, j); | |
6270 | ||
6271 | if (xtensa_operand_is_known_reg (isa, t1->opcode, i) == 0 | |
6272 | || xtensa_operand_is_known_reg (isa, t2->opcode, j) == 0) | |
6273 | { | |
6274 | if (t1_inout == 'm' || t1_inout == 'o' | |
6275 | || t2_inout == 'm' || t2_inout == 'o') | |
6276 | { | |
6277 | conflict = 'a'; | |
6278 | continue; | |
6279 | } | |
6280 | } | |
6281 | ||
6282 | t1_base_reg = t1->tok[i].X_add_number; | |
6283 | t1_last_reg = (t1_base_reg | |
6284 | + xtensa_operand_num_regs (isa, t1->opcode, i)); | |
6285 | ||
6286 | for (t1_reg = t1_base_reg; t1_reg < t1_last_reg; t1_reg++) | |
6287 | { | |
6288 | for (t2_reg = t2_base_reg; t2_reg < t2_last_reg; t2_reg++) | |
6289 | { | |
6290 | if (t1_reg != t2_reg) | |
6291 | continue; | |
6292 | ||
6293 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) | |
7fa3d080 BW |
6294 | { |
6295 | conflict = 'a'; | |
6296 | continue; | |
6297 | } | |
43cd72b9 | 6298 | |
7fa3d080 BW |
6299 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6300 | { | |
6301 | conflict = 'a'; | |
6302 | continue; | |
6303 | } | |
43cd72b9 | 6304 | |
7fa3d080 BW |
6305 | if (t1_inout != 'i' && t2_inout != 'i') |
6306 | return 'c'; | |
6307 | } | |
6308 | } | |
6309 | } | |
6310 | } | |
43cd72b9 | 6311 | |
7fa3d080 BW |
6312 | /* Check states. */ |
6313 | t1_states = xtensa_opcode_num_stateOperands (isa, t1->opcode); | |
6314 | t2_states = xtensa_opcode_num_stateOperands (isa, t2->opcode); | |
6315 | for (j = 0; j < t2_states; j++) | |
43cd72b9 | 6316 | { |
7fa3d080 BW |
6317 | xtensa_state t2_so = xtensa_stateOperand_state (isa, t2->opcode, j); |
6318 | t2_inout = xtensa_stateOperand_inout (isa, t2->opcode, j); | |
6319 | for (i = 0; i < t1_states; i++) | |
6320 | { | |
6321 | xtensa_state t1_so = xtensa_stateOperand_state (isa, t1->opcode, i); | |
6322 | t1_inout = xtensa_stateOperand_inout (isa, t1->opcode, i); | |
c138bc38 | 6323 | if (t1_so != t2_so) |
7fa3d080 | 6324 | continue; |
43cd72b9 | 6325 | |
7fa3d080 BW |
6326 | if (t2_inout == 'i' && (t1_inout == 'm' || t1_inout == 'o')) |
6327 | { | |
6328 | conflict = 'a'; | |
6329 | continue; | |
6330 | } | |
c138bc38 | 6331 | |
7fa3d080 BW |
6332 | if (t1_inout == 'i' && (t2_inout == 'm' || t2_inout == 'o')) |
6333 | { | |
6334 | conflict = 'a'; | |
6335 | continue; | |
6336 | } | |
c138bc38 | 6337 | |
7fa3d080 BW |
6338 | if (t1_inout != 'i' && t2_inout != 'i') |
6339 | return 'd'; | |
c138bc38 | 6340 | } |
7fa3d080 | 6341 | } |
43cd72b9 | 6342 | |
7fa3d080 BW |
6343 | /* Check tieports. */ |
6344 | t1_interfaces = xtensa_opcode_num_interfaceOperands (isa, t1->opcode); | |
6345 | t2_interfaces = xtensa_opcode_num_interfaceOperands (isa, t2->opcode); | |
c138bc38 | 6346 | for (j = 0; j < t2_interfaces; j++) |
43cd72b9 | 6347 | { |
7fa3d080 BW |
6348 | xtensa_interface t2_int |
6349 | = xtensa_interfaceOperand_interface (isa, t2->opcode, j); | |
a1ace8d8 BW |
6350 | int t2_class = xtensa_interface_class_id (isa, t2_int); |
6351 | ||
53dfbcc7 | 6352 | t2_inout = xtensa_interface_inout (isa, t2_int); |
a1ace8d8 | 6353 | if (xtensa_interface_has_side_effect (isa, t2_int) == 1) |
7fa3d080 | 6354 | t2_volatile = TRUE; |
a1ace8d8 | 6355 | |
7fa3d080 BW |
6356 | for (i = 0; i < t1_interfaces; i++) |
6357 | { | |
6358 | xtensa_interface t1_int | |
6359 | = xtensa_interfaceOperand_interface (isa, t1->opcode, j); | |
2eccd1b4 | 6360 | int t1_class = xtensa_interface_class_id (isa, t1_int); |
a1ace8d8 | 6361 | |
53dfbcc7 | 6362 | t1_inout = xtensa_interface_inout (isa, t1_int); |
a1ace8d8 | 6363 | if (xtensa_interface_has_side_effect (isa, t1_int) == 1) |
7fa3d080 | 6364 | t1_volatile = TRUE; |
a1ace8d8 BW |
6365 | |
6366 | if (t1_volatile && t2_volatile && (t1_class == t2_class)) | |
6367 | return 'f'; | |
c138bc38 | 6368 | |
7fa3d080 BW |
6369 | if (t1_int != t2_int) |
6370 | continue; | |
c138bc38 | 6371 | |
7fa3d080 BW |
6372 | if (t2_inout == 'i' && t1_inout == 'o') |
6373 | { | |
6374 | conflict = 'a'; | |
6375 | continue; | |
6376 | } | |
c138bc38 | 6377 | |
7fa3d080 BW |
6378 | if (t1_inout == 'i' && t2_inout == 'o') |
6379 | { | |
6380 | conflict = 'a'; | |
6381 | continue; | |
6382 | } | |
c138bc38 | 6383 | |
7fa3d080 BW |
6384 | if (t1_inout != 'i' && t2_inout != 'i') |
6385 | return 'e'; | |
6386 | } | |
43cd72b9 | 6387 | } |
c138bc38 | 6388 | |
7fa3d080 | 6389 | return conflict; |
43cd72b9 BW |
6390 | } |
6391 | ||
6392 | ||
6393 | static xtensa_format | |
7fa3d080 | 6394 | xg_find_narrowest_format (vliw_insn *vinsn) |
43cd72b9 BW |
6395 | { |
6396 | /* Right now we assume that the ops within the vinsn are properly | |
6397 | ordered for the slots that the programmer wanted them in. In | |
6398 | other words, we don't rearrange the ops in hopes of finding a | |
6399 | better format. The scheduler handles that. */ | |
6400 | ||
6401 | xtensa_isa isa = xtensa_default_isa; | |
6402 | xtensa_format format; | |
6403 | vliw_insn v_copy = *vinsn; | |
6404 | xtensa_opcode nop_opcode = xtensa_nop_opcode; | |
6405 | ||
65738a7d BW |
6406 | if (vinsn->num_slots == 1) |
6407 | return xg_get_single_format (vinsn->slots[0].opcode); | |
6408 | ||
43cd72b9 BW |
6409 | for (format = 0; format < xtensa_isa_num_formats (isa); format++) |
6410 | { | |
6411 | v_copy = *vinsn; | |
6412 | if (xtensa_format_num_slots (isa, format) == v_copy.num_slots) | |
6413 | { | |
6414 | int slot; | |
6415 | int fit = 0; | |
6416 | for (slot = 0; slot < v_copy.num_slots; slot++) | |
6417 | { | |
6418 | if (v_copy.slots[slot].opcode == nop_opcode) | |
6419 | { | |
6420 | v_copy.slots[slot].opcode = | |
6421 | xtensa_format_slot_nop_opcode (isa, format, slot); | |
6422 | v_copy.slots[slot].ntok = 0; | |
6423 | } | |
6424 | ||
6425 | if (opcode_fits_format_slot (v_copy.slots[slot].opcode, | |
6426 | format, slot)) | |
6427 | fit++; | |
7fa3d080 | 6428 | else if (v_copy.num_slots > 1) |
43cd72b9 | 6429 | { |
7fa3d080 BW |
6430 | TInsn widened; |
6431 | /* Try the widened version. */ | |
6432 | if (!v_copy.slots[slot].keep_wide | |
6433 | && !v_copy.slots[slot].is_specific_opcode | |
84b08ed9 BW |
6434 | && xg_is_single_relaxable_insn (&v_copy.slots[slot], |
6435 | &widened, TRUE) | |
7fa3d080 BW |
6436 | && opcode_fits_format_slot (widened.opcode, |
6437 | format, slot)) | |
43cd72b9 | 6438 | { |
7fa3d080 BW |
6439 | v_copy.slots[slot] = widened; |
6440 | fit++; | |
43cd72b9 BW |
6441 | } |
6442 | } | |
6443 | } | |
6444 | if (fit == v_copy.num_slots) | |
6445 | { | |
6446 | *vinsn = v_copy; | |
6447 | xtensa_format_encode (isa, format, vinsn->insnbuf); | |
6448 | vinsn->format = format; | |
6449 | break; | |
6450 | } | |
6451 | } | |
6452 | } | |
6453 | ||
6454 | if (format == xtensa_isa_num_formats (isa)) | |
6455 | return XTENSA_UNDEFINED; | |
6456 | ||
6457 | return format; | |
6458 | } | |
6459 | ||
6460 | ||
6461 | /* Return the additional space needed in a frag | |
6462 | for possible relaxations of any ops in a VLIW insn. | |
6463 | Also fill out the relaxations that might be required of | |
6464 | each tinsn in the vinsn. */ | |
6465 | ||
6466 | static int | |
e7da6241 | 6467 | relaxation_requirements (vliw_insn *vinsn, bfd_boolean *pfinish_frag) |
43cd72b9 | 6468 | { |
e7da6241 | 6469 | bfd_boolean finish_frag = FALSE; |
43cd72b9 BW |
6470 | int extra_space = 0; |
6471 | int slot; | |
6472 | ||
6473 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6474 | { | |
6475 | TInsn *tinsn = &vinsn->slots[slot]; | |
6476 | if (!tinsn_has_symbolic_operands (tinsn)) | |
6477 | { | |
6478 | /* A narrow instruction could be widened later to help | |
6479 | alignment issues. */ | |
84b08ed9 | 6480 | if (xg_is_single_relaxable_insn (tinsn, 0, TRUE) |
43cd72b9 BW |
6481 | && !tinsn->is_specific_opcode |
6482 | && vinsn->num_slots == 1) | |
6483 | { | |
6484 | /* Difference in bytes between narrow and wide insns... */ | |
6485 | extra_space += 1; | |
6486 | tinsn->subtype = RELAX_NARROW; | |
43cd72b9 BW |
6487 | } |
6488 | } | |
6489 | else | |
6490 | { | |
b08b5071 BW |
6491 | if (workaround_b_j_loop_end |
6492 | && tinsn->opcode == xtensa_jx_opcode | |
43cd72b9 BW |
6493 | && use_transform ()) |
6494 | { | |
6495 | /* Add 2 of these. */ | |
6496 | extra_space += 3; /* for the nop size */ | |
6497 | tinsn->subtype = RELAX_ADD_NOP_IF_PRE_LOOP_END; | |
6498 | } | |
c138bc38 | 6499 | |
43cd72b9 BW |
6500 | /* Need to assemble it with space for the relocation. */ |
6501 | if (xg_is_relaxable_insn (tinsn, 0) | |
6502 | && !tinsn->is_specific_opcode) | |
6503 | { | |
6504 | int max_size = xg_get_max_insn_widen_size (tinsn->opcode); | |
6505 | int max_literal_size = | |
6506 | xg_get_max_insn_widen_literal_size (tinsn->opcode); | |
c138bc38 | 6507 | |
43cd72b9 | 6508 | tinsn->literal_space = max_literal_size; |
c138bc38 | 6509 | |
43cd72b9 | 6510 | tinsn->subtype = RELAX_IMMED; |
43cd72b9 BW |
6511 | extra_space += max_size; |
6512 | } | |
6513 | else | |
6514 | { | |
e7da6241 BW |
6515 | /* A fix record will be added for this instruction prior |
6516 | to relaxation, so make it end the frag. */ | |
6517 | finish_frag = TRUE; | |
43cd72b9 BW |
6518 | } |
6519 | } | |
6520 | } | |
e7da6241 | 6521 | *pfinish_frag = finish_frag; |
43cd72b9 BW |
6522 | return extra_space; |
6523 | } | |
6524 | ||
6525 | ||
6526 | static void | |
b2d179be | 6527 | bundle_tinsn (TInsn *tinsn, vliw_insn *vinsn) |
43cd72b9 BW |
6528 | { |
6529 | xtensa_isa isa = xtensa_default_isa; | |
b2d179be | 6530 | int slot, chosen_slot; |
43cd72b9 | 6531 | |
b2d179be BW |
6532 | vinsn->format = xg_get_single_format (tinsn->opcode); |
6533 | assert (vinsn->format != XTENSA_UNDEFINED); | |
6534 | vinsn->num_slots = xtensa_format_num_slots (isa, vinsn->format); | |
43cd72b9 | 6535 | |
b2d179be BW |
6536 | chosen_slot = xg_get_single_slot (tinsn->opcode); |
6537 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
43cd72b9 | 6538 | { |
b2d179be BW |
6539 | if (slot == chosen_slot) |
6540 | vinsn->slots[slot] = *tinsn; | |
6541 | else | |
6542 | { | |
6543 | vinsn->slots[slot].opcode = | |
6544 | xtensa_format_slot_nop_opcode (isa, vinsn->format, slot); | |
6545 | vinsn->slots[slot].ntok = 0; | |
6546 | vinsn->slots[slot].insn_type = ITYPE_INSN; | |
6547 | } | |
43cd72b9 | 6548 | } |
43cd72b9 BW |
6549 | } |
6550 | ||
6551 | ||
6552 | static bfd_boolean | |
7fa3d080 | 6553 | emit_single_op (TInsn *orig_insn) |
43cd72b9 BW |
6554 | { |
6555 | int i; | |
6556 | IStack istack; /* put instructions into here */ | |
6557 | symbolS *lit_sym = NULL; | |
6558 | symbolS *label_sym = NULL; | |
6559 | ||
6560 | istack_init (&istack); | |
6561 | ||
6562 | /* Special-case for "movi aX, foo" which is guaranteed to need relaxing. | |
c138bc38 BW |
6563 | Because the scheduling and bundling characteristics of movi and |
6564 | l32r or const16 are so different, we can do much better if we relax | |
43cd72b9 | 6565 | it prior to scheduling and bundling, rather than after. */ |
c138bc38 | 6566 | if ((orig_insn->opcode == xtensa_movi_opcode |
b08b5071 BW |
6567 | || orig_insn->opcode == xtensa_movi_n_opcode) |
6568 | && !cur_vinsn.inside_bundle | |
43cd72b9 | 6569 | && (orig_insn->tok[1].X_op == O_symbol |
482fd9f9 BW |
6570 | || orig_insn->tok[1].X_op == O_pltrel) |
6571 | && !orig_insn->is_specific_opcode && use_transform ()) | |
43cd72b9 BW |
6572 | xg_assembly_relax (&istack, orig_insn, now_seg, frag_now, 0, 1, 0); |
6573 | else | |
6574 | if (xg_expand_assembly_insn (&istack, orig_insn)) | |
6575 | return TRUE; | |
6576 | ||
6577 | for (i = 0; i < istack.ninsn; i++) | |
6578 | { | |
6579 | TInsn *insn = &istack.insn[i]; | |
c138bc38 | 6580 | switch (insn->insn_type) |
43cd72b9 BW |
6581 | { |
6582 | case ITYPE_LITERAL: | |
6583 | assert (lit_sym == NULL); | |
6584 | lit_sym = xg_assemble_literal (insn); | |
6585 | break; | |
6586 | case ITYPE_LABEL: | |
6587 | { | |
6588 | static int relaxed_sym_idx = 0; | |
6589 | char *label = xmalloc (strlen (FAKE_LABEL_NAME) + 12); | |
6590 | sprintf (label, "%s_rl_%x", FAKE_LABEL_NAME, relaxed_sym_idx++); | |
6591 | colon (label); | |
6592 | assert (label_sym == NULL); | |
6593 | label_sym = symbol_find_or_make (label); | |
6594 | assert (label_sym); | |
6595 | free (label); | |
6596 | } | |
6597 | break; | |
6598 | case ITYPE_INSN: | |
b2d179be BW |
6599 | { |
6600 | vliw_insn v; | |
6601 | if (lit_sym) | |
6602 | xg_resolve_literals (insn, lit_sym); | |
6603 | if (label_sym) | |
6604 | xg_resolve_labels (insn, label_sym); | |
6605 | xg_init_vinsn (&v); | |
6606 | bundle_tinsn (insn, &v); | |
6607 | finish_vinsn (&v); | |
6608 | xg_free_vinsn (&v); | |
6609 | } | |
43cd72b9 BW |
6610 | break; |
6611 | default: | |
6612 | assert (0); | |
6613 | break; | |
6614 | } | |
6615 | } | |
6616 | return FALSE; | |
6617 | } | |
6618 | ||
6619 | ||
34e41783 BW |
6620 | static int |
6621 | total_frag_text_expansion (fragS *fragP) | |
6622 | { | |
6623 | int slot; | |
6624 | int total_expansion = 0; | |
6625 | ||
6626 | for (slot = 0; slot < MAX_SLOTS; slot++) | |
6627 | total_expansion += fragP->tc_frag_data.text_expansion[slot]; | |
6628 | ||
6629 | return total_expansion; | |
6630 | } | |
6631 | ||
6632 | ||
43cd72b9 BW |
6633 | /* Emit a vliw instruction to the current fragment. */ |
6634 | ||
7fa3d080 BW |
6635 | static void |
6636 | xg_assemble_vliw_tokens (vliw_insn *vinsn) | |
43cd72b9 | 6637 | { |
e7da6241 | 6638 | bfd_boolean finish_frag; |
43cd72b9 BW |
6639 | bfd_boolean is_jump = FALSE; |
6640 | bfd_boolean is_branch = FALSE; | |
6641 | xtensa_isa isa = xtensa_default_isa; | |
6642 | int i; | |
6643 | int insn_size; | |
6644 | int extra_space; | |
6645 | char *f = NULL; | |
6646 | int slot; | |
7c430684 BW |
6647 | unsigned current_line, best_linenum; |
6648 | char *current_file; | |
43cd72b9 | 6649 | |
7c430684 | 6650 | best_linenum = UINT_MAX; |
43cd72b9 BW |
6651 | |
6652 | if (generating_literals) | |
6653 | { | |
6654 | static int reported = 0; | |
6655 | if (reported < 4) | |
6656 | as_bad_where (frag_now->fr_file, frag_now->fr_line, | |
6657 | _("cannot assemble into a literal fragment")); | |
6658 | if (reported == 3) | |
6659 | as_bad (_("...")); | |
6660 | reported++; | |
6661 | return; | |
6662 | } | |
6663 | ||
6664 | if (frag_now_fix () != 0 | |
b08b5071 | 6665 | && (! frag_now->tc_frag_data.is_insn |
43cd72b9 | 6666 | || (vinsn_has_specific_opcodes (vinsn) && use_transform ()) |
b08b5071 | 6667 | || !use_transform () != frag_now->tc_frag_data.is_no_transform |
7c834684 BW |
6668 | || (directive_state[directive_longcalls] |
6669 | != frag_now->tc_frag_data.use_longcalls) | |
43cd72b9 BW |
6670 | || (directive_state[directive_absolute_literals] |
6671 | != frag_now->tc_frag_data.use_absolute_literals))) | |
6672 | { | |
6673 | frag_wane (frag_now); | |
6674 | frag_new (0); | |
6675 | xtensa_set_frag_assembly_state (frag_now); | |
6676 | } | |
6677 | ||
6678 | if (workaround_a0_b_retw | |
6679 | && vinsn->num_slots == 1 | |
6680 | && (get_last_insn_flags (now_seg, now_subseg) & FLAG_IS_A0_WRITER) != 0 | |
6681 | && xtensa_opcode_is_branch (isa, vinsn->slots[0].opcode) == 1 | |
6682 | && use_transform ()) | |
6683 | { | |
6684 | has_a0_b_retw = TRUE; | |
6685 | ||
6686 | /* Mark this fragment with the special RELAX_ADD_NOP_IF_A0_B_RETW. | |
6687 | After the first assembly pass we will check all of them and | |
6688 | add a nop if needed. */ | |
6689 | frag_now->tc_frag_data.is_insn = TRUE; | |
6690 | frag_var (rs_machine_dependent, 4, 4, | |
6691 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6692 | frag_now->fr_symbol, | |
6693 | frag_now->fr_offset, | |
6694 | NULL); | |
6695 | xtensa_set_frag_assembly_state (frag_now); | |
6696 | frag_now->tc_frag_data.is_insn = TRUE; | |
6697 | frag_var (rs_machine_dependent, 4, 4, | |
6698 | RELAX_ADD_NOP_IF_A0_B_RETW, | |
6699 | frag_now->fr_symbol, | |
6700 | frag_now->fr_offset, | |
6701 | NULL); | |
6702 | xtensa_set_frag_assembly_state (frag_now); | |
6703 | } | |
6704 | ||
6705 | for (i = 0; i < vinsn->num_slots; i++) | |
6706 | { | |
6707 | /* See if the instruction implies an aligned section. */ | |
6708 | if (xtensa_opcode_is_loop (isa, vinsn->slots[i].opcode) == 1) | |
6709 | record_alignment (now_seg, 2); | |
c138bc38 | 6710 | |
43cd72b9 | 6711 | /* Also determine the best line number for debug info. */ |
7c430684 BW |
6712 | best_linenum = vinsn->slots[i].linenum < best_linenum |
6713 | ? vinsn->slots[i].linenum : best_linenum; | |
43cd72b9 BW |
6714 | } |
6715 | ||
6716 | /* Special cases for instructions that force an alignment... */ | |
6717 | /* None of these opcodes are bundle-able. */ | |
6718 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1) | |
6719 | { | |
d77b99c9 | 6720 | int max_fill; |
c138bc38 | 6721 | |
05d58145 BW |
6722 | /* Remember the symbol that marks the end of the loop in the frag |
6723 | that marks the start of the loop. This way we can easily find | |
6724 | the end of the loop at the beginning, without adding special code | |
6725 | to mark the loop instructions themselves. */ | |
6726 | symbolS *target_sym = NULL; | |
6727 | if (vinsn->slots[0].tok[1].X_op == O_symbol) | |
6728 | target_sym = vinsn->slots[0].tok[1].X_add_symbol; | |
6729 | ||
43cd72b9 BW |
6730 | xtensa_set_frag_assembly_state (frag_now); |
6731 | frag_now->tc_frag_data.is_insn = TRUE; | |
c138bc38 | 6732 | |
43cd72b9 BW |
6733 | max_fill = get_text_align_max_fill_size |
6734 | (get_text_align_power (xtensa_fetch_width), | |
6735 | TRUE, frag_now->tc_frag_data.is_no_density); | |
6736 | ||
6737 | if (use_transform ()) | |
6738 | frag_var (rs_machine_dependent, max_fill, max_fill, | |
05d58145 | 6739 | RELAX_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6740 | else |
c138bc38 | 6741 | frag_var (rs_machine_dependent, 0, 0, |
05d58145 | 6742 | RELAX_CHECK_ALIGN_NEXT_OPCODE, target_sym, 0, NULL); |
43cd72b9 | 6743 | xtensa_set_frag_assembly_state (frag_now); |
c138bc38 | 6744 | |
43cd72b9 BW |
6745 | xtensa_move_labels (frag_now, 0, FALSE); |
6746 | } | |
6747 | ||
b08b5071 | 6748 | if (vinsn->slots[0].opcode == xtensa_entry_opcode |
43cd72b9 BW |
6749 | && !vinsn->slots[0].is_specific_opcode) |
6750 | { | |
6751 | xtensa_mark_literal_pool_location (); | |
6752 | xtensa_move_labels (frag_now, 0, TRUE); | |
6753 | frag_var (rs_align_test, 1, 1, 0, NULL, 2, NULL); | |
6754 | } | |
6755 | ||
6756 | if (vinsn->num_slots == 1) | |
6757 | { | |
6758 | if (workaround_a0_b_retw && use_transform ()) | |
6759 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_A0_WRITER, | |
6760 | is_register_writer (&vinsn->slots[0], "a", 0)); | |
6761 | ||
6762 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, | |
6763 | is_bad_loopend_opcode (&vinsn->slots[0])); | |
6764 | } | |
6765 | else | |
6766 | set_last_insn_flags (now_seg, now_subseg, FLAG_IS_BAD_LOOPEND, FALSE); | |
6767 | ||
6768 | insn_size = xtensa_format_length (isa, vinsn->format); | |
6769 | ||
e7da6241 | 6770 | extra_space = relaxation_requirements (vinsn, &finish_frag); |
43cd72b9 BW |
6771 | |
6772 | /* vinsn_to_insnbuf will produce the error. */ | |
6773 | if (vinsn->format != XTENSA_UNDEFINED) | |
6774 | { | |
d77b99c9 | 6775 | f = frag_more (insn_size + extra_space); |
43cd72b9 BW |
6776 | xtensa_set_frag_assembly_state (frag_now); |
6777 | frag_now->tc_frag_data.is_insn = TRUE; | |
6778 | } | |
6779 | ||
e7da6241 | 6780 | vinsn_to_insnbuf (vinsn, f, frag_now, FALSE); |
43cd72b9 BW |
6781 | if (vinsn->format == XTENSA_UNDEFINED) |
6782 | return; | |
6783 | ||
d77b99c9 | 6784 | xtensa_insnbuf_to_chars (isa, vinsn->insnbuf, (unsigned char *) f, 0); |
c138bc38 | 6785 | |
7c430684 BW |
6786 | /* Temporarily set the logical line number to the one we want to appear |
6787 | in the debug information. */ | |
6788 | as_where (¤t_file, ¤t_line); | |
6789 | new_logical_line (current_file, best_linenum); | |
6790 | dwarf2_emit_insn (insn_size + extra_space); | |
6791 | new_logical_line (current_file, current_line); | |
43cd72b9 BW |
6792 | |
6793 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
6794 | { | |
6795 | TInsn *tinsn = &vinsn->slots[slot]; | |
6796 | frag_now->tc_frag_data.slot_subtypes[slot] = tinsn->subtype; | |
7c834684 | 6797 | frag_now->tc_frag_data.slot_symbols[slot] = tinsn->symbol; |
7c834684 | 6798 | frag_now->tc_frag_data.slot_offsets[slot] = tinsn->offset; |
43cd72b9 BW |
6799 | frag_now->tc_frag_data.literal_frags[slot] = tinsn->literal_frag; |
6800 | if (tinsn->literal_space != 0) | |
6801 | xg_assemble_literal_space (tinsn->literal_space, slot); | |
6802 | ||
6803 | if (tinsn->subtype == RELAX_NARROW) | |
6804 | assert (vinsn->num_slots == 1); | |
6805 | if (xtensa_opcode_is_jump (isa, tinsn->opcode) == 1) | |
6806 | is_jump = TRUE; | |
6807 | if (xtensa_opcode_is_branch (isa, tinsn->opcode) == 1) | |
6808 | is_branch = TRUE; | |
6809 | ||
e7da6241 BW |
6810 | if (tinsn->subtype || tinsn->symbol || tinsn->offset |
6811 | || tinsn->literal_frag || is_jump || is_branch) | |
43cd72b9 BW |
6812 | finish_frag = TRUE; |
6813 | } | |
6814 | ||
6815 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
b08b5071 | 6816 | frag_now->tc_frag_data.is_specific_opcode = TRUE; |
43cd72b9 BW |
6817 | |
6818 | if (finish_frag) | |
6819 | { | |
6820 | frag_variant (rs_machine_dependent, | |
6821 | extra_space, extra_space, RELAX_SLOTS, | |
6822 | frag_now->fr_symbol, frag_now->fr_offset, f); | |
6823 | xtensa_set_frag_assembly_state (frag_now); | |
6824 | } | |
6825 | ||
6826 | /* Special cases for loops: | |
6827 | close_loop_end should be inserted AFTER short_loop. | |
6828 | Make sure that CLOSE loops are processed BEFORE short_loops | |
6829 | when converting them. */ | |
6830 | ||
6831 | /* "short_loop": Add a NOP if the loop is < 4 bytes. */ | |
64b607e6 | 6832 | if (xtensa_opcode_is_loop (isa, vinsn->slots[0].opcode) == 1 |
43cd72b9 BW |
6833 | && !vinsn->slots[0].is_specific_opcode) |
6834 | { | |
6835 | if (workaround_short_loop && use_transform ()) | |
6836 | { | |
6837 | maybe_has_short_loop = TRUE; | |
6838 | frag_now->tc_frag_data.is_insn = TRUE; | |
6839 | frag_var (rs_machine_dependent, 4, 4, | |
6840 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6841 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6842 | frag_now->tc_frag_data.is_insn = TRUE; | |
6843 | frag_var (rs_machine_dependent, 4, 4, | |
6844 | RELAX_ADD_NOP_IF_SHORT_LOOP, | |
6845 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6846 | } | |
6847 | ||
6848 | /* "close_loop_end": Add up to 12 bytes of NOPs to keep a | |
6849 | loop at least 12 bytes away from another loop's end. */ | |
6850 | if (workaround_close_loop_end && use_transform ()) | |
6851 | { | |
6852 | maybe_has_close_loop_end = TRUE; | |
6853 | frag_now->tc_frag_data.is_insn = TRUE; | |
6854 | frag_var (rs_machine_dependent, 12, 12, | |
6855 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END, | |
6856 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6857 | } | |
6858 | } | |
6859 | ||
6860 | if (use_transform ()) | |
6861 | { | |
6862 | if (is_jump) | |
6863 | { | |
6864 | assert (finish_frag); | |
6865 | frag_var (rs_machine_dependent, | |
6866 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6867 | RELAX_UNREACHABLE, | |
6868 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6869 | xtensa_set_frag_assembly_state (frag_now); | |
6870 | } | |
7b1cc377 | 6871 | else if (is_branch && do_align_targets ()) |
43cd72b9 BW |
6872 | { |
6873 | assert (finish_frag); | |
6874 | frag_var (rs_machine_dependent, | |
6875 | UNREACHABLE_MAX_WIDTH, UNREACHABLE_MAX_WIDTH, | |
6876 | RELAX_MAYBE_UNREACHABLE, | |
6877 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6878 | xtensa_set_frag_assembly_state (frag_now); | |
6879 | frag_var (rs_machine_dependent, | |
6880 | 0, 0, | |
6881 | RELAX_MAYBE_DESIRE_ALIGN, | |
6882 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6883 | xtensa_set_frag_assembly_state (frag_now); | |
6884 | } | |
6885 | } | |
6886 | ||
6887 | /* Now, if the original opcode was a call... */ | |
6888 | if (do_align_targets () | |
6889 | && xtensa_opcode_is_call (isa, vinsn->slots[0].opcode) == 1) | |
6890 | { | |
b08b5071 | 6891 | float freq = get_subseg_total_freq (now_seg, now_subseg); |
43cd72b9 BW |
6892 | frag_now->tc_frag_data.is_insn = TRUE; |
6893 | frag_var (rs_machine_dependent, 4, (int) freq, RELAX_DESIRE_ALIGN, | |
6894 | frag_now->fr_symbol, frag_now->fr_offset, NULL); | |
6895 | xtensa_set_frag_assembly_state (frag_now); | |
6896 | } | |
6897 | ||
6898 | if (vinsn_has_specific_opcodes (vinsn) && use_transform ()) | |
6899 | { | |
6900 | frag_wane (frag_now); | |
6901 | frag_new (0); | |
6902 | xtensa_set_frag_assembly_state (frag_now); | |
6903 | } | |
6904 | } | |
6905 | ||
6906 | \f | |
7fa3d080 BW |
6907 | /* xtensa_end and helper functions. */ |
6908 | ||
6909 | static void xtensa_cleanup_align_frags (void); | |
6910 | static void xtensa_fix_target_frags (void); | |
6911 | static void xtensa_mark_narrow_branches (void); | |
6912 | static void xtensa_mark_zcl_first_insns (void); | |
6913 | static void xtensa_fix_a0_b_retw_frags (void); | |
6914 | static void xtensa_fix_b_j_loop_end_frags (void); | |
6915 | static void xtensa_fix_close_loop_end_frags (void); | |
6916 | static void xtensa_fix_short_loop_frags (void); | |
6917 | static void xtensa_sanity_check (void); | |
6918 | ||
43cd72b9 | 6919 | void |
7fa3d080 | 6920 | xtensa_end (void) |
43cd72b9 BW |
6921 | { |
6922 | directive_balance (); | |
6923 | xtensa_flush_pending_output (); | |
6924 | ||
6925 | past_xtensa_end = TRUE; | |
6926 | ||
6927 | xtensa_move_literals (); | |
6928 | ||
6929 | xtensa_reorder_segments (); | |
6930 | xtensa_cleanup_align_frags (); | |
6931 | xtensa_fix_target_frags (); | |
6932 | if (workaround_a0_b_retw && has_a0_b_retw) | |
6933 | xtensa_fix_a0_b_retw_frags (); | |
6934 | if (workaround_b_j_loop_end) | |
6935 | xtensa_fix_b_j_loop_end_frags (); | |
6936 | ||
6937 | /* "close_loop_end" should be processed BEFORE "short_loop". */ | |
6938 | if (workaround_close_loop_end && maybe_has_close_loop_end) | |
6939 | xtensa_fix_close_loop_end_frags (); | |
6940 | ||
6941 | if (workaround_short_loop && maybe_has_short_loop) | |
6942 | xtensa_fix_short_loop_frags (); | |
03aaa593 BW |
6943 | if (align_targets) |
6944 | xtensa_mark_narrow_branches (); | |
43cd72b9 BW |
6945 | xtensa_mark_zcl_first_insns (); |
6946 | ||
6947 | xtensa_sanity_check (); | |
6948 | } | |
6949 | ||
6950 | ||
6951 | static void | |
7fa3d080 | 6952 | xtensa_cleanup_align_frags (void) |
43cd72b9 BW |
6953 | { |
6954 | frchainS *frchP; | |
c9049d30 | 6955 | asection *s; |
43cd72b9 | 6956 | |
c9049d30 AM |
6957 | for (s = stdoutput->sections; s; s = s->next) |
6958 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
6959 | { | |
6960 | fragS *fragP; | |
6961 | /* Walk over all of the fragments in a subsection. */ | |
6962 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
6963 | { | |
6964 | if ((fragP->fr_type == rs_align | |
6965 | || fragP->fr_type == rs_align_code | |
6966 | || (fragP->fr_type == rs_machine_dependent | |
6967 | && (fragP->fr_subtype == RELAX_DESIRE_ALIGN | |
6968 | || fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET))) | |
6969 | && fragP->fr_fix == 0) | |
6970 | { | |
6971 | fragS *next = fragP->fr_next; | |
6972 | ||
6973 | while (next | |
6974 | && next->fr_fix == 0 | |
6975 | && next->fr_type == rs_machine_dependent | |
6976 | && next->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
6977 | { | |
6978 | frag_wane (next); | |
6979 | next = next->fr_next; | |
6980 | } | |
6981 | } | |
6982 | /* If we don't widen branch targets, then they | |
6983 | will be easier to align. */ | |
6984 | if (fragP->tc_frag_data.is_branch_target | |
6985 | && fragP->fr_opcode == fragP->fr_literal | |
6986 | && fragP->fr_type == rs_machine_dependent | |
6987 | && fragP->fr_subtype == RELAX_SLOTS | |
6988 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
6989 | frag_wane (fragP); | |
6990 | if (fragP->fr_type == rs_machine_dependent | |
6991 | && fragP->fr_subtype == RELAX_UNREACHABLE) | |
6992 | fragP->tc_frag_data.is_unreachable = TRUE; | |
6993 | } | |
6994 | } | |
43cd72b9 BW |
6995 | } |
6996 | ||
6997 | ||
6998 | /* Re-process all of the fragments looking to convert all of the | |
6999 | RELAX_DESIRE_ALIGN_IF_TARGET fragments. If there is a branch | |
7000 | target in the next fragment, convert this to RELAX_DESIRE_ALIGN. | |
7b1cc377 | 7001 | Otherwise, convert to a .fill 0. */ |
7fa3d080 | 7002 | |
43cd72b9 | 7003 | static void |
7fa3d080 | 7004 | xtensa_fix_target_frags (void) |
e0001a05 NC |
7005 | { |
7006 | frchainS *frchP; | |
c9049d30 | 7007 | asection *s; |
e0001a05 NC |
7008 | |
7009 | /* When this routine is called, all of the subsections are still intact | |
7010 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7011 | for (s = stdoutput->sections; s; s = s->next) |
7012 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7013 | { | |
7014 | fragS *fragP; | |
e0001a05 | 7015 | |
c9049d30 AM |
7016 | /* Walk over all of the fragments in a subsection. */ |
7017 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7018 | { | |
7019 | if (fragP->fr_type == rs_machine_dependent | |
7020 | && fragP->fr_subtype == RELAX_DESIRE_ALIGN_IF_TARGET) | |
7021 | { | |
7022 | if (next_frag_is_branch_target (fragP)) | |
7023 | fragP->fr_subtype = RELAX_DESIRE_ALIGN; | |
7024 | else | |
7025 | frag_wane (fragP); | |
7026 | } | |
7027 | } | |
7028 | } | |
e0001a05 NC |
7029 | } |
7030 | ||
7031 | ||
7fa3d080 BW |
7032 | static bfd_boolean is_narrow_branch_guaranteed_in_range (fragS *, TInsn *); |
7033 | ||
43cd72b9 | 7034 | static void |
7fa3d080 | 7035 | xtensa_mark_narrow_branches (void) |
43cd72b9 BW |
7036 | { |
7037 | frchainS *frchP; | |
c9049d30 | 7038 | asection *s; |
43cd72b9 | 7039 | |
c9049d30 AM |
7040 | for (s = stdoutput->sections; s; s = s->next) |
7041 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7042 | { | |
7043 | fragS *fragP; | |
7044 | /* Walk over all of the fragments in a subsection. */ | |
7045 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7046 | { | |
7047 | if (fragP->fr_type == rs_machine_dependent | |
7048 | && fragP->fr_subtype == RELAX_SLOTS | |
7049 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_IMMED) | |
7050 | { | |
7051 | vliw_insn vinsn; | |
7052 | ||
7053 | vinsn_from_chars (&vinsn, fragP->fr_opcode); | |
7054 | tinsn_immed_from_frag (&vinsn.slots[0], fragP, 0); | |
7055 | ||
7056 | if (vinsn.num_slots == 1 | |
7057 | && xtensa_opcode_is_branch (xtensa_default_isa, | |
64b607e6 | 7058 | vinsn.slots[0].opcode) == 1 |
c9049d30 AM |
7059 | && xg_get_single_size (vinsn.slots[0].opcode) == 2 |
7060 | && is_narrow_branch_guaranteed_in_range (fragP, | |
7061 | &vinsn.slots[0])) | |
7062 | { | |
7063 | fragP->fr_subtype = RELAX_SLOTS; | |
7064 | fragP->tc_frag_data.slot_subtypes[0] = RELAX_NARROW; | |
7065 | fragP->tc_frag_data.is_aligning_branch = 1; | |
7066 | } | |
7067 | } | |
7068 | } | |
7069 | } | |
43cd72b9 BW |
7070 | } |
7071 | ||
7072 | ||
7073 | /* A branch is typically widened only when its target is out of | |
7074 | range. However, we would like to widen them to align a subsequent | |
7075 | branch target when possible. | |
7076 | ||
7077 | Because the branch relaxation code is so convoluted, the optimal solution | |
7078 | (combining the two cases) is difficult to get right in all circumstances. | |
7079 | We therefore go with an "almost as good" solution, where we only | |
7080 | use for alignment narrow branches that definitely will not expand to a | |
7081 | jump and a branch. These functions find and mark these cases. */ | |
7082 | ||
a67517f4 BW |
7083 | /* The range in bytes of BNEZ.N and BEQZ.N. The target operand is encoded |
7084 | as PC + 4 + imm6, where imm6 is a 6-bit immediate ranging from 0 to 63. | |
7085 | We start counting beginning with the frag after the 2-byte branch, so the | |
7086 | maximum offset is (4 - 2) + 63 = 65. */ | |
7087 | #define MAX_IMMED6 65 | |
43cd72b9 | 7088 | |
d77b99c9 | 7089 | static offsetT unrelaxed_frag_max_size (fragS *); |
7fa3d080 | 7090 | |
43cd72b9 | 7091 | static bfd_boolean |
7fa3d080 | 7092 | is_narrow_branch_guaranteed_in_range (fragS *fragP, TInsn *tinsn) |
43cd72b9 BW |
7093 | { |
7094 | const expressionS *expr = &tinsn->tok[1]; | |
7095 | symbolS *symbolP = expr->X_add_symbol; | |
d77b99c9 | 7096 | offsetT max_distance = expr->X_add_number; |
e7da6241 BW |
7097 | fragS *target_frag; |
7098 | ||
7099 | if (expr->X_op != O_symbol) | |
7100 | return FALSE; | |
7101 | ||
7102 | target_frag = symbol_get_frag (symbolP); | |
7103 | ||
43cd72b9 BW |
7104 | max_distance += (S_GET_VALUE (symbolP) - target_frag->fr_address); |
7105 | if (is_branch_jmp_to_next (tinsn, fragP)) | |
7106 | return FALSE; | |
7107 | ||
7108 | /* The branch doesn't branch over it's own frag, | |
7109 | but over the subsequent ones. */ | |
7110 | fragP = fragP->fr_next; | |
7111 | while (fragP != NULL && fragP != target_frag && max_distance <= MAX_IMMED6) | |
7112 | { | |
7113 | max_distance += unrelaxed_frag_max_size (fragP); | |
7114 | fragP = fragP->fr_next; | |
7115 | } | |
7116 | if (max_distance <= MAX_IMMED6 && fragP == target_frag) | |
7117 | return TRUE; | |
e0001a05 NC |
7118 | return FALSE; |
7119 | } | |
7120 | ||
7121 | ||
43cd72b9 | 7122 | static void |
7fa3d080 | 7123 | xtensa_mark_zcl_first_insns (void) |
43cd72b9 BW |
7124 | { |
7125 | frchainS *frchP; | |
c9049d30 | 7126 | asection *s; |
43cd72b9 | 7127 | |
c9049d30 AM |
7128 | for (s = stdoutput->sections; s; s = s->next) |
7129 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7130 | { | |
7131 | fragS *fragP; | |
7132 | /* Walk over all of the fragments in a subsection. */ | |
7133 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7134 | { | |
7135 | if (fragP->fr_type == rs_machine_dependent | |
7136 | && (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE | |
7137 | || fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE)) | |
7138 | { | |
7139 | /* Find the loop frag. */ | |
7140 | fragS *targ_frag = next_non_empty_frag (fragP); | |
7141 | /* Find the first insn frag. */ | |
7142 | targ_frag = next_non_empty_frag (targ_frag); | |
7143 | ||
7144 | /* Of course, sometimes (mostly for toy test cases) a | |
7145 | zero-cost loop instruction is the last in a section. */ | |
7146 | if (targ_frag) | |
7147 | { | |
7148 | targ_frag->tc_frag_data.is_first_loop_insn = TRUE; | |
7149 | /* Do not widen a frag that is the first instruction of a | |
7150 | zero-cost loop. It makes that loop harder to align. */ | |
7151 | if (targ_frag->fr_type == rs_machine_dependent | |
7152 | && targ_frag->fr_subtype == RELAX_SLOTS | |
7153 | && (targ_frag->tc_frag_data.slot_subtypes[0] | |
7154 | == RELAX_NARROW)) | |
7155 | { | |
7156 | if (targ_frag->tc_frag_data.is_aligning_branch) | |
7157 | targ_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
7158 | else | |
7159 | { | |
7160 | frag_wane (targ_frag); | |
7161 | targ_frag->tc_frag_data.slot_subtypes[0] = 0; | |
7162 | } | |
7163 | } | |
7164 | } | |
7165 | if (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE) | |
7166 | frag_wane (fragP); | |
7167 | } | |
7168 | } | |
7169 | } | |
43cd72b9 BW |
7170 | } |
7171 | ||
7172 | ||
e0001a05 NC |
7173 | /* Re-process all of the fragments looking to convert all of the |
7174 | RELAX_ADD_NOP_IF_A0_B_RETW. If the next instruction is a | |
7175 | conditional branch or a retw/retw.n, convert this frag to one that | |
7176 | will generate a NOP. In any case close it off with a .fill 0. */ | |
7177 | ||
7fa3d080 BW |
7178 | static bfd_boolean next_instrs_are_b_retw (fragS *); |
7179 | ||
e0001a05 | 7180 | static void |
7fa3d080 | 7181 | xtensa_fix_a0_b_retw_frags (void) |
e0001a05 NC |
7182 | { |
7183 | frchainS *frchP; | |
c9049d30 | 7184 | asection *s; |
e0001a05 NC |
7185 | |
7186 | /* When this routine is called, all of the subsections are still intact | |
7187 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7188 | for (s = stdoutput->sections; s; s = s->next) |
7189 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7190 | { | |
7191 | fragS *fragP; | |
e0001a05 | 7192 | |
c9049d30 AM |
7193 | /* Walk over all of the fragments in a subsection. */ |
7194 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7195 | { | |
7196 | if (fragP->fr_type == rs_machine_dependent | |
7197 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_A0_B_RETW) | |
7198 | { | |
7199 | if (next_instrs_are_b_retw (fragP)) | |
7200 | { | |
7201 | if (fragP->tc_frag_data.is_no_transform) | |
7202 | as_bad (_("instruction sequence (write a0, branch, retw) may trigger hardware errata")); | |
7203 | else | |
7204 | relax_frag_add_nop (fragP); | |
7205 | } | |
7206 | frag_wane (fragP); | |
7207 | } | |
7208 | } | |
7209 | } | |
e0001a05 NC |
7210 | } |
7211 | ||
7212 | ||
7fa3d080 BW |
7213 | static bfd_boolean |
7214 | next_instrs_are_b_retw (fragS *fragP) | |
e0001a05 NC |
7215 | { |
7216 | xtensa_opcode opcode; | |
43cd72b9 | 7217 | xtensa_format fmt; |
e0001a05 NC |
7218 | const fragS *next_fragP = next_non_empty_frag (fragP); |
7219 | static xtensa_insnbuf insnbuf = NULL; | |
43cd72b9 | 7220 | static xtensa_insnbuf slotbuf = NULL; |
e0001a05 NC |
7221 | xtensa_isa isa = xtensa_default_isa; |
7222 | int offset = 0; | |
43cd72b9 BW |
7223 | int slot; |
7224 | bfd_boolean branch_seen = FALSE; | |
e0001a05 NC |
7225 | |
7226 | if (!insnbuf) | |
43cd72b9 BW |
7227 | { |
7228 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7229 | slotbuf = xtensa_insnbuf_alloc (isa); | |
7230 | } | |
e0001a05 NC |
7231 | |
7232 | if (next_fragP == NULL) | |
7233 | return FALSE; | |
7234 | ||
7235 | /* Check for the conditional branch. */ | |
d77b99c9 BW |
7236 | xtensa_insnbuf_from_chars |
7237 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7238 | fmt = xtensa_format_decode (isa, insnbuf); |
7239 | if (fmt == XTENSA_UNDEFINED) | |
7240 | return FALSE; | |
7241 | ||
7242 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
7243 | { | |
7244 | xtensa_format_get_slot (isa, fmt, slot, insnbuf, slotbuf); | |
7245 | opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
7246 | ||
7247 | branch_seen = (branch_seen | |
7248 | || xtensa_opcode_is_branch (isa, opcode) == 1); | |
7249 | } | |
e0001a05 | 7250 | |
43cd72b9 | 7251 | if (!branch_seen) |
e0001a05 NC |
7252 | return FALSE; |
7253 | ||
43cd72b9 | 7254 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7255 | if (offset == next_fragP->fr_fix) |
7256 | { | |
7257 | next_fragP = next_non_empty_frag (next_fragP); | |
7258 | offset = 0; | |
7259 | } | |
43cd72b9 | 7260 | |
e0001a05 NC |
7261 | if (next_fragP == NULL) |
7262 | return FALSE; | |
7263 | ||
7264 | /* Check for the retw/retw.n. */ | |
d77b99c9 BW |
7265 | xtensa_insnbuf_from_chars |
7266 | (isa, insnbuf, (unsigned char *) &next_fragP->fr_literal[offset], 0); | |
43cd72b9 BW |
7267 | fmt = xtensa_format_decode (isa, insnbuf); |
7268 | ||
7269 | /* Because RETW[.N] is not bundleable, a VLIW bundle here means that we | |
7270 | have no problems. */ | |
7271 | if (fmt == XTENSA_UNDEFINED | |
7272 | || xtensa_format_num_slots (isa, fmt) != 1) | |
7273 | return FALSE; | |
7274 | ||
7275 | xtensa_format_get_slot (isa, fmt, 0, insnbuf, slotbuf); | |
7276 | opcode = xtensa_opcode_decode (isa, fmt, 0, slotbuf); | |
e0001a05 | 7277 | |
b08b5071 | 7278 | if (opcode == xtensa_retw_opcode || opcode == xtensa_retw_n_opcode) |
e0001a05 | 7279 | return TRUE; |
43cd72b9 | 7280 | |
e0001a05 NC |
7281 | return FALSE; |
7282 | } | |
7283 | ||
7284 | ||
7285 | /* Re-process all of the fragments looking to convert all of the | |
7286 | RELAX_ADD_NOP_IF_PRE_LOOP_END. If there is one instruction and a | |
7287 | loop end label, convert this frag to one that will generate a NOP. | |
7288 | In any case close it off with a .fill 0. */ | |
7289 | ||
7fa3d080 BW |
7290 | static bfd_boolean next_instr_is_loop_end (fragS *); |
7291 | ||
e0001a05 | 7292 | static void |
7fa3d080 | 7293 | xtensa_fix_b_j_loop_end_frags (void) |
e0001a05 NC |
7294 | { |
7295 | frchainS *frchP; | |
c9049d30 | 7296 | asection *s; |
e0001a05 NC |
7297 | |
7298 | /* When this routine is called, all of the subsections are still intact | |
7299 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7300 | for (s = stdoutput->sections; s; s = s->next) |
7301 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7302 | { | |
7303 | fragS *fragP; | |
e0001a05 | 7304 | |
c9049d30 AM |
7305 | /* Walk over all of the fragments in a subsection. */ |
7306 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7307 | { | |
7308 | if (fragP->fr_type == rs_machine_dependent | |
7309 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_PRE_LOOP_END) | |
7310 | { | |
7311 | if (next_instr_is_loop_end (fragP)) | |
7312 | { | |
7313 | if (fragP->tc_frag_data.is_no_transform) | |
7314 | as_bad (_("branching or jumping to a loop end may trigger hardware errata")); | |
7315 | else | |
7316 | relax_frag_add_nop (fragP); | |
7317 | } | |
7318 | frag_wane (fragP); | |
7319 | } | |
7320 | } | |
7321 | } | |
e0001a05 NC |
7322 | } |
7323 | ||
7324 | ||
7fa3d080 BW |
7325 | static bfd_boolean |
7326 | next_instr_is_loop_end (fragS *fragP) | |
e0001a05 NC |
7327 | { |
7328 | const fragS *next_fragP; | |
7329 | ||
7330 | if (next_frag_is_loop_target (fragP)) | |
7331 | return FALSE; | |
7332 | ||
7333 | next_fragP = next_non_empty_frag (fragP); | |
7334 | if (next_fragP == NULL) | |
7335 | return FALSE; | |
7336 | ||
7337 | if (!next_frag_is_loop_target (next_fragP)) | |
7338 | return FALSE; | |
7339 | ||
7340 | /* If the size is >= 3 then there is more than one instruction here. | |
7341 | The hardware bug will not fire. */ | |
7342 | if (next_fragP->fr_fix > 3) | |
7343 | return FALSE; | |
7344 | ||
7345 | return TRUE; | |
7346 | } | |
7347 | ||
7348 | ||
7349 | /* Re-process all of the fragments looking to convert all of the | |
7350 | RELAX_ADD_NOP_IF_CLOSE_LOOP_END. If there is an loop end that is | |
7351 | not MY loop's loop end within 12 bytes, add enough nops here to | |
7352 | make it at least 12 bytes away. In any case close it off with a | |
7353 | .fill 0. */ | |
7354 | ||
d77b99c9 | 7355 | static offsetT min_bytes_to_other_loop_end |
05d58145 | 7356 | (fragS *, fragS *, offsetT); |
7fa3d080 | 7357 | |
e0001a05 | 7358 | static void |
7fa3d080 | 7359 | xtensa_fix_close_loop_end_frags (void) |
e0001a05 NC |
7360 | { |
7361 | frchainS *frchP; | |
c9049d30 | 7362 | asection *s; |
e0001a05 NC |
7363 | |
7364 | /* When this routine is called, all of the subsections are still intact | |
7365 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7366 | for (s = stdoutput->sections; s; s = s->next) |
7367 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7368 | { | |
7369 | fragS *fragP; | |
e0001a05 | 7370 | |
c9049d30 | 7371 | fragS *current_target = NULL; |
e0001a05 | 7372 | |
c9049d30 AM |
7373 | /* Walk over all of the fragments in a subsection. */ |
7374 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7375 | { | |
7376 | if (fragP->fr_type == rs_machine_dependent | |
7377 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7378 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
05d58145 | 7379 | current_target = symbol_get_frag (fragP->fr_symbol); |
e0001a05 | 7380 | |
c9049d30 AM |
7381 | if (current_target |
7382 | && fragP->fr_type == rs_machine_dependent | |
7383 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_CLOSE_LOOP_END) | |
7384 | { | |
7385 | offsetT min_bytes; | |
7386 | int bytes_added = 0; | |
e0001a05 NC |
7387 | |
7388 | #define REQUIRED_LOOP_DIVIDING_BYTES 12 | |
c9049d30 AM |
7389 | /* Max out at 12. */ |
7390 | min_bytes = min_bytes_to_other_loop_end | |
7391 | (fragP->fr_next, current_target, REQUIRED_LOOP_DIVIDING_BYTES); | |
7392 | ||
7393 | if (min_bytes < REQUIRED_LOOP_DIVIDING_BYTES) | |
7394 | { | |
7395 | if (fragP->tc_frag_data.is_no_transform) | |
7396 | as_bad (_("loop end too close to another loop end may trigger hardware errata")); | |
7397 | else | |
7398 | { | |
7399 | while (min_bytes + bytes_added | |
7400 | < REQUIRED_LOOP_DIVIDING_BYTES) | |
7401 | { | |
7402 | int length = 3; | |
7403 | ||
7404 | if (fragP->fr_var < length) | |
7405 | as_fatal (_("fr_var %lu < length %d"), | |
7406 | (long) fragP->fr_var, length); | |
7407 | else | |
7408 | { | |
7409 | assemble_nop (length, | |
7410 | fragP->fr_literal + fragP->fr_fix); | |
7411 | fragP->fr_fix += length; | |
7412 | fragP->fr_var -= length; | |
7413 | } | |
7414 | bytes_added += length; | |
7415 | } | |
7416 | } | |
7417 | } | |
7418 | frag_wane (fragP); | |
7419 | } | |
7420 | assert (fragP->fr_type != rs_machine_dependent | |
7421 | || fragP->fr_subtype != RELAX_ADD_NOP_IF_CLOSE_LOOP_END); | |
7422 | } | |
7423 | } | |
e0001a05 NC |
7424 | } |
7425 | ||
7426 | ||
d77b99c9 | 7427 | static offsetT unrelaxed_frag_min_size (fragS *); |
7fa3d080 | 7428 | |
d77b99c9 | 7429 | static offsetT |
7fa3d080 BW |
7430 | min_bytes_to_other_loop_end (fragS *fragP, |
7431 | fragS *current_target, | |
d77b99c9 | 7432 | offsetT max_size) |
e0001a05 | 7433 | { |
d77b99c9 | 7434 | offsetT offset = 0; |
e0001a05 NC |
7435 | fragS *current_fragP; |
7436 | ||
7437 | for (current_fragP = fragP; | |
7438 | current_fragP; | |
7439 | current_fragP = current_fragP->fr_next) | |
7440 | { | |
7441 | if (current_fragP->tc_frag_data.is_loop_target | |
7442 | && current_fragP != current_target) | |
05d58145 | 7443 | return offset; |
e0001a05 NC |
7444 | |
7445 | offset += unrelaxed_frag_min_size (current_fragP); | |
7446 | ||
05d58145 | 7447 | if (offset >= max_size) |
e0001a05 NC |
7448 | return max_size; |
7449 | } | |
7450 | return max_size; | |
7451 | } | |
7452 | ||
7453 | ||
d77b99c9 | 7454 | static offsetT |
7fa3d080 | 7455 | unrelaxed_frag_min_size (fragS *fragP) |
e0001a05 | 7456 | { |
d77b99c9 | 7457 | offsetT size = fragP->fr_fix; |
e0001a05 | 7458 | |
d77b99c9 | 7459 | /* Add fill size. */ |
e0001a05 NC |
7460 | if (fragP->fr_type == rs_fill) |
7461 | size += fragP->fr_offset; | |
7462 | ||
7463 | return size; | |
7464 | } | |
7465 | ||
7466 | ||
d77b99c9 | 7467 | static offsetT |
7fa3d080 | 7468 | unrelaxed_frag_max_size (fragS *fragP) |
43cd72b9 | 7469 | { |
d77b99c9 | 7470 | offsetT size = fragP->fr_fix; |
43cd72b9 BW |
7471 | switch (fragP->fr_type) |
7472 | { | |
7473 | case 0: | |
c138bc38 | 7474 | /* Empty frags created by the obstack allocation scheme |
43cd72b9 BW |
7475 | end up with type 0. */ |
7476 | break; | |
7477 | case rs_fill: | |
7478 | case rs_org: | |
7479 | case rs_space: | |
7480 | size += fragP->fr_offset; | |
7481 | break; | |
7482 | case rs_align: | |
7483 | case rs_align_code: | |
7484 | case rs_align_test: | |
7485 | case rs_leb128: | |
7486 | case rs_cfa: | |
7487 | case rs_dwarf2dbg: | |
7488 | /* No further adjustments needed. */ | |
7489 | break; | |
7490 | case rs_machine_dependent: | |
7491 | if (fragP->fr_subtype != RELAX_DESIRE_ALIGN) | |
7492 | size += fragP->fr_var; | |
7493 | break; | |
7494 | default: | |
7495 | /* We had darn well better know how big it is. */ | |
7496 | assert (0); | |
7497 | break; | |
7498 | } | |
7499 | ||
7500 | return size; | |
7501 | } | |
7502 | ||
7503 | ||
e0001a05 NC |
7504 | /* Re-process all of the fragments looking to convert all |
7505 | of the RELAX_ADD_NOP_IF_SHORT_LOOP. If: | |
7506 | ||
7507 | A) | |
7508 | 1) the instruction size count to the loop end label | |
7509 | is too short (<= 2 instructions), | |
7510 | 2) loop has a jump or branch in it | |
7511 | ||
7512 | or B) | |
43cd72b9 | 7513 | 1) workaround_all_short_loops is TRUE |
e0001a05 NC |
7514 | 2) The generating loop was a 'loopgtz' or 'loopnez' |
7515 | 3) the instruction size count to the loop end label is too short | |
7516 | (<= 2 instructions) | |
7517 | then convert this frag (and maybe the next one) to generate a NOP. | |
7518 | In any case close it off with a .fill 0. */ | |
7519 | ||
d77b99c9 | 7520 | static int count_insns_to_loop_end (fragS *, bfd_boolean, int); |
7fa3d080 BW |
7521 | static bfd_boolean branch_before_loop_end (fragS *); |
7522 | ||
e0001a05 | 7523 | static void |
7fa3d080 | 7524 | xtensa_fix_short_loop_frags (void) |
e0001a05 NC |
7525 | { |
7526 | frchainS *frchP; | |
c9049d30 | 7527 | asection *s; |
e0001a05 NC |
7528 | |
7529 | /* When this routine is called, all of the subsections are still intact | |
7530 | so we walk over subsections instead of sections. */ | |
c9049d30 AM |
7531 | for (s = stdoutput->sections; s; s = s->next) |
7532 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7533 | { | |
7534 | fragS *fragP; | |
7535 | fragS *current_target = NULL; | |
7536 | xtensa_opcode current_opcode = XTENSA_UNDEFINED; | |
e0001a05 | 7537 | |
c9049d30 AM |
7538 | /* Walk over all of the fragments in a subsection. */ |
7539 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7540 | { | |
7541 | if (fragP->fr_type == rs_machine_dependent | |
7542 | && ((fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE) | |
7543 | || (fragP->fr_subtype == RELAX_CHECK_ALIGN_NEXT_OPCODE))) | |
7544 | { | |
7545 | TInsn t_insn; | |
7546 | fragS *loop_frag = next_non_empty_frag (fragP); | |
7547 | tinsn_from_chars (&t_insn, loop_frag->fr_opcode, 0); | |
7548 | current_target = symbol_get_frag (fragP->fr_symbol); | |
7549 | current_opcode = t_insn.opcode; | |
7550 | assert (xtensa_opcode_is_loop (xtensa_default_isa, | |
64b607e6 | 7551 | current_opcode) == 1); |
c9049d30 | 7552 | } |
e0001a05 | 7553 | |
c9049d30 AM |
7554 | if (fragP->fr_type == rs_machine_dependent |
7555 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7556 | { | |
7557 | if (count_insns_to_loop_end (fragP->fr_next, TRUE, 3) < 3 | |
7558 | && (branch_before_loop_end (fragP->fr_next) | |
7559 | || (workaround_all_short_loops | |
7560 | && current_opcode != XTENSA_UNDEFINED | |
7561 | && current_opcode != xtensa_loop_opcode))) | |
7562 | { | |
7563 | if (fragP->tc_frag_data.is_no_transform) | |
7564 | as_bad (_("loop containing less than three instructions may trigger hardware errata")); | |
7565 | else | |
7566 | relax_frag_add_nop (fragP); | |
7567 | } | |
7568 | frag_wane (fragP); | |
7569 | } | |
7570 | } | |
7571 | } | |
e0001a05 NC |
7572 | } |
7573 | ||
7574 | ||
d77b99c9 | 7575 | static int unrelaxed_frag_min_insn_count (fragS *); |
7fa3d080 | 7576 | |
d77b99c9 | 7577 | static int |
7fa3d080 BW |
7578 | count_insns_to_loop_end (fragS *base_fragP, |
7579 | bfd_boolean count_relax_add, | |
d77b99c9 | 7580 | int max_count) |
e0001a05 NC |
7581 | { |
7582 | fragS *fragP = NULL; | |
d77b99c9 | 7583 | int insn_count = 0; |
e0001a05 NC |
7584 | |
7585 | fragP = base_fragP; | |
7586 | ||
7587 | for (; fragP && !fragP->tc_frag_data.is_loop_target; fragP = fragP->fr_next) | |
7588 | { | |
7589 | insn_count += unrelaxed_frag_min_insn_count (fragP); | |
7590 | if (insn_count >= max_count) | |
7591 | return max_count; | |
7592 | ||
7593 | if (count_relax_add) | |
7594 | { | |
7595 | if (fragP->fr_type == rs_machine_dependent | |
7596 | && fragP->fr_subtype == RELAX_ADD_NOP_IF_SHORT_LOOP) | |
7597 | { | |
7598 | /* In order to add the appropriate number of | |
7599 | NOPs, we count an instruction for downstream | |
7600 | occurrences. */ | |
7601 | insn_count++; | |
7602 | if (insn_count >= max_count) | |
7603 | return max_count; | |
7604 | } | |
7605 | } | |
7606 | } | |
7607 | return insn_count; | |
7608 | } | |
7609 | ||
7610 | ||
d77b99c9 | 7611 | static int |
7fa3d080 | 7612 | unrelaxed_frag_min_insn_count (fragS *fragP) |
e0001a05 | 7613 | { |
43cd72b9 BW |
7614 | xtensa_isa isa = xtensa_default_isa; |
7615 | static xtensa_insnbuf insnbuf = NULL; | |
d77b99c9 | 7616 | int insn_count = 0; |
e0001a05 NC |
7617 | int offset = 0; |
7618 | ||
7619 | if (!fragP->tc_frag_data.is_insn) | |
7620 | return insn_count; | |
7621 | ||
43cd72b9 BW |
7622 | if (!insnbuf) |
7623 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7624 | ||
e0001a05 NC |
7625 | /* Decode the fixed instructions. */ |
7626 | while (offset < fragP->fr_fix) | |
7627 | { | |
43cd72b9 BW |
7628 | xtensa_format fmt; |
7629 | ||
d77b99c9 BW |
7630 | xtensa_insnbuf_from_chars |
7631 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7632 | fmt = xtensa_format_decode (isa, insnbuf); |
7633 | ||
7634 | if (fmt == XTENSA_UNDEFINED) | |
e0001a05 NC |
7635 | { |
7636 | as_fatal (_("undecodable instruction in instruction frag")); | |
7637 | return insn_count; | |
7638 | } | |
43cd72b9 | 7639 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7640 | insn_count++; |
7641 | } | |
7642 | ||
7643 | return insn_count; | |
7644 | } | |
7645 | ||
7646 | ||
7fa3d080 BW |
7647 | static bfd_boolean unrelaxed_frag_has_b_j (fragS *); |
7648 | ||
43cd72b9 | 7649 | static bfd_boolean |
7fa3d080 | 7650 | branch_before_loop_end (fragS *base_fragP) |
e0001a05 NC |
7651 | { |
7652 | fragS *fragP; | |
7653 | ||
7654 | for (fragP = base_fragP; | |
7655 | fragP && !fragP->tc_frag_data.is_loop_target; | |
7656 | fragP = fragP->fr_next) | |
7657 | { | |
7658 | if (unrelaxed_frag_has_b_j (fragP)) | |
7659 | return TRUE; | |
7660 | } | |
7661 | return FALSE; | |
7662 | } | |
7663 | ||
7664 | ||
43cd72b9 | 7665 | static bfd_boolean |
7fa3d080 | 7666 | unrelaxed_frag_has_b_j (fragS *fragP) |
e0001a05 | 7667 | { |
43cd72b9 BW |
7668 | static xtensa_insnbuf insnbuf = NULL; |
7669 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
7670 | int offset = 0; |
7671 | ||
7672 | if (!fragP->tc_frag_data.is_insn) | |
7673 | return FALSE; | |
7674 | ||
43cd72b9 BW |
7675 | if (!insnbuf) |
7676 | insnbuf = xtensa_insnbuf_alloc (isa); | |
7677 | ||
e0001a05 NC |
7678 | /* Decode the fixed instructions. */ |
7679 | while (offset < fragP->fr_fix) | |
7680 | { | |
43cd72b9 BW |
7681 | xtensa_format fmt; |
7682 | int slot; | |
7683 | ||
d77b99c9 BW |
7684 | xtensa_insnbuf_from_chars |
7685 | (isa, insnbuf, (unsigned char *) fragP->fr_literal + offset, 0); | |
43cd72b9 BW |
7686 | fmt = xtensa_format_decode (isa, insnbuf); |
7687 | if (fmt == XTENSA_UNDEFINED) | |
7688 | return FALSE; | |
7689 | ||
7690 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
e0001a05 | 7691 | { |
43cd72b9 BW |
7692 | xtensa_opcode opcode = |
7693 | get_opcode_from_buf (fragP->fr_literal + offset, slot); | |
7694 | if (xtensa_opcode_is_branch (isa, opcode) == 1 | |
7695 | || xtensa_opcode_is_jump (isa, opcode) == 1) | |
7696 | return TRUE; | |
e0001a05 | 7697 | } |
43cd72b9 | 7698 | offset += xtensa_format_length (isa, fmt); |
e0001a05 NC |
7699 | } |
7700 | return FALSE; | |
7701 | } | |
7702 | ||
7703 | ||
7704 | /* Checks to be made after initial assembly but before relaxation. */ | |
7705 | ||
7fa3d080 BW |
7706 | static bfd_boolean is_empty_loop (const TInsn *, fragS *); |
7707 | static bfd_boolean is_local_forward_loop (const TInsn *, fragS *); | |
7708 | ||
e0001a05 | 7709 | static void |
7fa3d080 | 7710 | xtensa_sanity_check (void) |
e0001a05 NC |
7711 | { |
7712 | char *file_name; | |
d77b99c9 | 7713 | unsigned line; |
e0001a05 | 7714 | frchainS *frchP; |
c9049d30 | 7715 | asection *s; |
e0001a05 NC |
7716 | |
7717 | as_where (&file_name, &line); | |
c9049d30 AM |
7718 | for (s = stdoutput->sections; s; s = s->next) |
7719 | for (frchP = seg_info (s)->frchainP; frchP; frchP = frchP->frch_next) | |
7720 | { | |
7721 | fragS *fragP; | |
e0001a05 | 7722 | |
c9049d30 AM |
7723 | /* Walk over all of the fragments in a subsection. */ |
7724 | for (fragP = frchP->frch_root; fragP; fragP = fragP->fr_next) | |
7725 | { | |
7726 | /* Currently we only check for empty loops here. */ | |
7727 | if (fragP->fr_type == rs_machine_dependent | |
7728 | && fragP->fr_subtype == RELAX_IMMED) | |
7729 | { | |
7730 | static xtensa_insnbuf insnbuf = NULL; | |
7731 | TInsn t_insn; | |
7732 | ||
7733 | if (fragP->fr_opcode != NULL) | |
7734 | { | |
7735 | if (!insnbuf) | |
7736 | insnbuf = xtensa_insnbuf_alloc (xtensa_default_isa); | |
7737 | tinsn_from_chars (&t_insn, fragP->fr_opcode, 0); | |
7738 | tinsn_immed_from_frag (&t_insn, fragP, 0); | |
7739 | ||
7740 | if (xtensa_opcode_is_loop (xtensa_default_isa, | |
7741 | t_insn.opcode) == 1) | |
7742 | { | |
7743 | if (is_empty_loop (&t_insn, fragP)) | |
7744 | { | |
7745 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7746 | as_bad (_("invalid empty loop")); | |
7747 | } | |
7748 | if (!is_local_forward_loop (&t_insn, fragP)) | |
7749 | { | |
7750 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
7751 | as_bad (_("loop target does not follow " | |
7752 | "loop instruction in section")); | |
7753 | } | |
7754 | } | |
7755 | } | |
7756 | } | |
7757 | } | |
7758 | } | |
e0001a05 NC |
7759 | new_logical_line (file_name, line); |
7760 | } | |
7761 | ||
7762 | ||
7763 | #define LOOP_IMMED_OPN 1 | |
7764 | ||
43cd72b9 | 7765 | /* Return TRUE if the loop target is the next non-zero fragment. */ |
e0001a05 | 7766 | |
7fa3d080 BW |
7767 | static bfd_boolean |
7768 | is_empty_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7769 | { |
7770 | const expressionS *expr; | |
7771 | symbolS *symbolP; | |
7772 | fragS *next_fragP; | |
7773 | ||
7774 | if (insn->insn_type != ITYPE_INSN) | |
7775 | return FALSE; | |
7776 | ||
43cd72b9 | 7777 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7778 | return FALSE; |
7779 | ||
7780 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7781 | return FALSE; | |
7782 | ||
7783 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7784 | ||
7785 | if (expr->X_op != O_symbol) | |
7786 | return FALSE; | |
7787 | ||
7788 | symbolP = expr->X_add_symbol; | |
7789 | if (!symbolP) | |
7790 | return FALSE; | |
7791 | ||
7792 | if (symbol_get_frag (symbolP) == NULL) | |
7793 | return FALSE; | |
7794 | ||
7795 | if (S_GET_VALUE (symbolP) != 0) | |
7796 | return FALSE; | |
7797 | ||
7798 | /* Walk through the zero-size fragments from this one. If we find | |
7799 | the target fragment, then this is a zero-size loop. */ | |
43cd72b9 | 7800 | |
e0001a05 NC |
7801 | for (next_fragP = fragP->fr_next; |
7802 | next_fragP != NULL; | |
7803 | next_fragP = next_fragP->fr_next) | |
7804 | { | |
7805 | if (next_fragP == symbol_get_frag (symbolP)) | |
7806 | return TRUE; | |
7807 | if (next_fragP->fr_fix != 0) | |
7808 | return FALSE; | |
7809 | } | |
7810 | return FALSE; | |
7811 | } | |
7812 | ||
7813 | ||
7fa3d080 BW |
7814 | static bfd_boolean |
7815 | is_local_forward_loop (const TInsn *insn, fragS *fragP) | |
e0001a05 NC |
7816 | { |
7817 | const expressionS *expr; | |
7818 | symbolS *symbolP; | |
7819 | fragS *next_fragP; | |
7820 | ||
7821 | if (insn->insn_type != ITYPE_INSN) | |
7822 | return FALSE; | |
7823 | ||
64b607e6 | 7824 | if (xtensa_opcode_is_loop (xtensa_default_isa, insn->opcode) != 1) |
e0001a05 NC |
7825 | return FALSE; |
7826 | ||
7827 | if (insn->ntok <= LOOP_IMMED_OPN) | |
7828 | return FALSE; | |
7829 | ||
7830 | expr = &insn->tok[LOOP_IMMED_OPN]; | |
7831 | ||
7832 | if (expr->X_op != O_symbol) | |
7833 | return FALSE; | |
7834 | ||
7835 | symbolP = expr->X_add_symbol; | |
7836 | if (!symbolP) | |
7837 | return FALSE; | |
7838 | ||
7839 | if (symbol_get_frag (symbolP) == NULL) | |
7840 | return FALSE; | |
7841 | ||
7842 | /* Walk through fragments until we find the target. | |
7843 | If we do not find the target, then this is an invalid loop. */ | |
43cd72b9 | 7844 | |
e0001a05 NC |
7845 | for (next_fragP = fragP->fr_next; |
7846 | next_fragP != NULL; | |
7847 | next_fragP = next_fragP->fr_next) | |
43cd72b9 BW |
7848 | { |
7849 | if (next_fragP == symbol_get_frag (symbolP)) | |
7850 | return TRUE; | |
7851 | } | |
e0001a05 NC |
7852 | |
7853 | return FALSE; | |
7854 | } | |
7855 | ||
7856 | \f | |
7857 | /* Alignment Functions. */ | |
7858 | ||
d77b99c9 BW |
7859 | static int |
7860 | get_text_align_power (unsigned target_size) | |
e0001a05 | 7861 | { |
03aaa593 BW |
7862 | if (target_size <= 4) |
7863 | return 2; | |
7864 | assert (target_size == 8); | |
7865 | return 3; | |
e0001a05 NC |
7866 | } |
7867 | ||
7868 | ||
d77b99c9 | 7869 | static int |
7fa3d080 BW |
7870 | get_text_align_max_fill_size (int align_pow, |
7871 | bfd_boolean use_nops, | |
7872 | bfd_boolean use_no_density) | |
e0001a05 NC |
7873 | { |
7874 | if (!use_nops) | |
7875 | return (1 << align_pow); | |
7876 | if (use_no_density) | |
7877 | return 3 * (1 << align_pow); | |
7878 | ||
7879 | return 1 + (1 << align_pow); | |
7880 | } | |
7881 | ||
7882 | ||
d77b99c9 BW |
7883 | /* Calculate the minimum bytes of fill needed at "address" to align a |
7884 | target instruction of size "target_size" so that it does not cross a | |
7885 | power-of-two boundary specified by "align_pow". If "use_nops" is FALSE, | |
7886 | the fill can be an arbitrary number of bytes. Otherwise, the space must | |
7887 | be filled by NOP instructions. */ | |
e0001a05 | 7888 | |
d77b99c9 | 7889 | static int |
7fa3d080 BW |
7890 | get_text_align_fill_size (addressT address, |
7891 | int align_pow, | |
7892 | int target_size, | |
7893 | bfd_boolean use_nops, | |
7894 | bfd_boolean use_no_density) | |
e0001a05 | 7895 | { |
d77b99c9 BW |
7896 | addressT alignment, fill, fill_limit, fill_step; |
7897 | bfd_boolean skip_one = FALSE; | |
e0001a05 | 7898 | |
d77b99c9 BW |
7899 | alignment = (1 << align_pow); |
7900 | assert (target_size > 0 && alignment >= (addressT) target_size); | |
c138bc38 | 7901 | |
e0001a05 NC |
7902 | if (!use_nops) |
7903 | { | |
d77b99c9 BW |
7904 | fill_limit = alignment; |
7905 | fill_step = 1; | |
e0001a05 | 7906 | } |
d77b99c9 | 7907 | else if (!use_no_density) |
e0001a05 | 7908 | { |
d77b99c9 BW |
7909 | /* Combine 2- and 3-byte NOPs to fill anything larger than one. */ |
7910 | fill_limit = alignment * 2; | |
7911 | fill_step = 1; | |
7912 | skip_one = TRUE; | |
e0001a05 NC |
7913 | } |
7914 | else | |
7915 | { | |
d77b99c9 BW |
7916 | /* Fill with 3-byte NOPs -- can only fill multiples of 3. */ |
7917 | fill_limit = alignment * 3; | |
7918 | fill_step = 3; | |
7919 | } | |
e0001a05 | 7920 | |
d77b99c9 BW |
7921 | /* Try all fill sizes until finding one that works. */ |
7922 | for (fill = 0; fill < fill_limit; fill += fill_step) | |
7923 | { | |
7924 | if (skip_one && fill == 1) | |
7925 | continue; | |
7926 | if ((address + fill) >> align_pow | |
7927 | == (address + fill + target_size - 1) >> align_pow) | |
7928 | return fill; | |
e0001a05 NC |
7929 | } |
7930 | assert (0); | |
7931 | return 0; | |
7932 | } | |
7933 | ||
7934 | ||
664df4e4 BW |
7935 | static int |
7936 | branch_align_power (segT sec) | |
7937 | { | |
7938 | /* If the Xtensa processor has a fetch width of 8 bytes, and the section | |
7939 | is aligned to at least an 8-byte boundary, then a branch target need | |
7940 | only fit within an 8-byte aligned block of memory to avoid a stall. | |
7941 | Otherwise, try to fit branch targets within 4-byte aligned blocks | |
7942 | (which may be insufficient, e.g., if the section has no alignment, but | |
7943 | it's good enough). */ | |
7944 | if (xtensa_fetch_width == 8) | |
7945 | { | |
7946 | if (get_recorded_alignment (sec) >= 3) | |
7947 | return 3; | |
7948 | } | |
7949 | else | |
7950 | assert (xtensa_fetch_width == 4); | |
7951 | ||
7952 | return 2; | |
7953 | } | |
7954 | ||
7955 | ||
e0001a05 NC |
7956 | /* This will assert if it is not possible. */ |
7957 | ||
d77b99c9 BW |
7958 | static int |
7959 | get_text_align_nop_count (offsetT fill_size, bfd_boolean use_no_density) | |
e0001a05 | 7960 | { |
d77b99c9 BW |
7961 | int count = 0; |
7962 | ||
e0001a05 NC |
7963 | if (use_no_density) |
7964 | { | |
7965 | assert (fill_size % 3 == 0); | |
7966 | return (fill_size / 3); | |
7967 | } | |
7968 | ||
7969 | assert (fill_size != 1); /* Bad argument. */ | |
7970 | ||
7971 | while (fill_size > 1) | |
7972 | { | |
d77b99c9 | 7973 | int insn_size = 3; |
e0001a05 NC |
7974 | if (fill_size == 2 || fill_size == 4) |
7975 | insn_size = 2; | |
7976 | fill_size -= insn_size; | |
7977 | count++; | |
7978 | } | |
7979 | assert (fill_size != 1); /* Bad algorithm. */ | |
7980 | return count; | |
7981 | } | |
7982 | ||
7983 | ||
d77b99c9 BW |
7984 | static int |
7985 | get_text_align_nth_nop_size (offsetT fill_size, | |
7986 | int n, | |
7fa3d080 | 7987 | bfd_boolean use_no_density) |
e0001a05 | 7988 | { |
d77b99c9 | 7989 | int count = 0; |
e0001a05 NC |
7990 | |
7991 | if (use_no_density) | |
7992 | return 3; | |
7993 | ||
d77b99c9 BW |
7994 | assert (fill_size != 1); /* Bad argument. */ |
7995 | ||
e0001a05 NC |
7996 | while (fill_size > 1) |
7997 | { | |
d77b99c9 | 7998 | int insn_size = 3; |
e0001a05 NC |
7999 | if (fill_size == 2 || fill_size == 4) |
8000 | insn_size = 2; | |
8001 | fill_size -= insn_size; | |
8002 | count++; | |
8003 | if (n + 1 == count) | |
8004 | return insn_size; | |
8005 | } | |
8006 | assert (0); | |
8007 | return 0; | |
8008 | } | |
8009 | ||
8010 | ||
8011 | /* For the given fragment, find the appropriate address | |
8012 | for it to begin at if we are using NOPs to align it. */ | |
8013 | ||
8014 | static addressT | |
7fa3d080 | 8015 | get_noop_aligned_address (fragS *fragP, addressT address) |
e0001a05 | 8016 | { |
43cd72b9 BW |
8017 | /* The rule is: get next fragment's FIRST instruction. Find |
8018 | the smallest number of bytes that need to be added to | |
8019 | ensure that the next fragment's FIRST instruction will fit | |
8020 | in a single word. | |
c138bc38 | 8021 | |
43cd72b9 BW |
8022 | E.G., 2 bytes : 0, 1, 2 mod 4 |
8023 | 3 bytes: 0, 1 mod 4 | |
c138bc38 | 8024 | |
43cd72b9 BW |
8025 | If the FIRST instruction MIGHT be relaxed, |
8026 | assume that it will become a 3-byte instruction. | |
c138bc38 | 8027 | |
43cd72b9 BW |
8028 | Note again here that LOOP instructions are not bundleable, |
8029 | and this relaxation only applies to LOOP opcodes. */ | |
c138bc38 | 8030 | |
d77b99c9 | 8031 | int fill_size = 0; |
43cd72b9 BW |
8032 | int first_insn_size; |
8033 | int loop_insn_size; | |
8034 | addressT pre_opcode_bytes; | |
d77b99c9 | 8035 | int align_power; |
43cd72b9 BW |
8036 | fragS *first_insn; |
8037 | xtensa_opcode opcode; | |
8038 | bfd_boolean is_loop; | |
e0001a05 | 8039 | |
43cd72b9 BW |
8040 | assert (fragP->fr_type == rs_machine_dependent); |
8041 | assert (fragP->fr_subtype == RELAX_ALIGN_NEXT_OPCODE); | |
e0001a05 | 8042 | |
43cd72b9 BW |
8043 | /* Find the loop frag. */ |
8044 | first_insn = next_non_empty_frag (fragP); | |
8045 | /* Now find the first insn frag. */ | |
8046 | first_insn = next_non_empty_frag (first_insn); | |
e0001a05 | 8047 | |
43cd72b9 BW |
8048 | is_loop = next_frag_opcode_is_loop (fragP, &opcode); |
8049 | assert (is_loop); | |
8050 | loop_insn_size = xg_get_single_size (opcode); | |
e0001a05 | 8051 | |
43cd72b9 BW |
8052 | pre_opcode_bytes = next_frag_pre_opcode_bytes (fragP); |
8053 | pre_opcode_bytes += loop_insn_size; | |
e0001a05 | 8054 | |
43cd72b9 BW |
8055 | /* For loops, the alignment depends on the size of the |
8056 | instruction following the loop, not the LOOP instruction. */ | |
e0001a05 | 8057 | |
43cd72b9 | 8058 | if (first_insn == NULL) |
03aaa593 BW |
8059 | first_insn_size = xtensa_fetch_width; |
8060 | else | |
8061 | first_insn_size = get_loop_align_size (frag_format_size (first_insn)); | |
e0001a05 | 8062 | |
43cd72b9 | 8063 | /* If it was 8, then we'll need a larger alignment for the section. */ |
d77b99c9 BW |
8064 | align_power = get_text_align_power (first_insn_size); |
8065 | record_alignment (now_seg, align_power); | |
c138bc38 | 8066 | |
43cd72b9 | 8067 | fill_size = get_text_align_fill_size |
d77b99c9 BW |
8068 | (address + pre_opcode_bytes, align_power, first_insn_size, TRUE, |
8069 | fragP->tc_frag_data.is_no_density); | |
e0001a05 NC |
8070 | |
8071 | return address + fill_size; | |
8072 | } | |
8073 | ||
8074 | ||
43cd72b9 BW |
8075 | /* 3 mechanisms for relaxing an alignment: |
8076 | ||
8077 | Align to a power of 2. | |
8078 | Align so the next fragment's instruction does not cross a word boundary. | |
8079 | Align the current instruction so that if the next instruction | |
8080 | were 3 bytes, it would not cross a word boundary. | |
8081 | ||
e0001a05 NC |
8082 | We can align with: |
8083 | ||
43cd72b9 BW |
8084 | zeros - This is easy; always insert zeros. |
8085 | nops - 3-byte and 2-byte instructions | |
8086 | 2 - 2-byte nop | |
8087 | 3 - 3-byte nop | |
8088 | 4 - 2 2-byte nops | |
8089 | >=5 : 3-byte instruction + fn (n-3) | |
e0001a05 NC |
8090 | widening - widen previous instructions. */ |
8091 | ||
d77b99c9 BW |
8092 | static offsetT |
8093 | get_aligned_diff (fragS *fragP, addressT address, offsetT *max_diff) | |
e0001a05 | 8094 | { |
43cd72b9 BW |
8095 | addressT target_address, loop_insn_offset; |
8096 | int target_size; | |
8097 | xtensa_opcode loop_opcode; | |
8098 | bfd_boolean is_loop; | |
d77b99c9 BW |
8099 | int align_power; |
8100 | offsetT opt_diff; | |
5f9084e9 | 8101 | offsetT branch_align; |
e0001a05 | 8102 | |
43cd72b9 BW |
8103 | assert (fragP->fr_type == rs_machine_dependent); |
8104 | switch (fragP->fr_subtype) | |
e0001a05 | 8105 | { |
43cd72b9 BW |
8106 | case RELAX_DESIRE_ALIGN: |
8107 | target_size = next_frag_format_size (fragP); | |
8108 | if (target_size == XTENSA_UNDEFINED) | |
8109 | target_size = 3; | |
664df4e4 BW |
8110 | align_power = branch_align_power (now_seg); |
8111 | branch_align = 1 << align_power; | |
0e5cd789 BW |
8112 | /* Don't count on the section alignment being as large as the target. */ |
8113 | if (target_size > branch_align) | |
8114 | target_size = branch_align; | |
d77b99c9 | 8115 | opt_diff = get_text_align_fill_size (address, align_power, |
43cd72b9 BW |
8116 | target_size, FALSE, FALSE); |
8117 | ||
664df4e4 BW |
8118 | *max_diff = (opt_diff + branch_align |
8119 | - (target_size + ((address + opt_diff) % branch_align))); | |
43cd72b9 BW |
8120 | assert (*max_diff >= opt_diff); |
8121 | return opt_diff; | |
e0001a05 | 8122 | |
43cd72b9 | 8123 | case RELAX_ALIGN_NEXT_OPCODE: |
03aaa593 | 8124 | target_size = get_loop_align_size (next_frag_format_size (fragP)); |
43cd72b9 BW |
8125 | loop_insn_offset = 0; |
8126 | is_loop = next_frag_opcode_is_loop (fragP, &loop_opcode); | |
8127 | assert (is_loop); | |
8128 | ||
8129 | /* If the loop has been expanded then the LOOP instruction | |
8130 | could be at an offset from this fragment. */ | |
8131 | if (next_non_empty_frag(fragP)->tc_frag_data.slot_subtypes[0] | |
8132 | != RELAX_IMMED) | |
8133 | loop_insn_offset = get_expanded_loop_offset (loop_opcode); | |
8134 | ||
43cd72b9 BW |
8135 | /* In an ideal world, which is what we are shooting for here, |
8136 | we wouldn't need to use any NOPs immediately prior to the | |
8137 | LOOP instruction. If this approach fails, relax_frag_loop_align | |
8138 | will call get_noop_aligned_address. */ | |
8139 | target_address = | |
8140 | address + loop_insn_offset + xg_get_single_size (loop_opcode); | |
d77b99c9 BW |
8141 | align_power = get_text_align_power (target_size), |
8142 | opt_diff = get_text_align_fill_size (target_address, align_power, | |
43cd72b9 BW |
8143 | target_size, FALSE, FALSE); |
8144 | ||
8145 | *max_diff = xtensa_fetch_width | |
8146 | - ((target_address + opt_diff) % xtensa_fetch_width) | |
8147 | - target_size + opt_diff; | |
8148 | assert (*max_diff >= opt_diff); | |
8149 | return opt_diff; | |
e0001a05 | 8150 | |
43cd72b9 BW |
8151 | default: |
8152 | break; | |
e0001a05 | 8153 | } |
43cd72b9 BW |
8154 | assert (0); |
8155 | return 0; | |
e0001a05 NC |
8156 | } |
8157 | ||
8158 | \f | |
8159 | /* md_relax_frag Hook and Helper Functions. */ | |
8160 | ||
7fa3d080 BW |
8161 | static long relax_frag_loop_align (fragS *, long); |
8162 | static long relax_frag_for_align (fragS *, long); | |
8163 | static long relax_frag_immed | |
8164 | (segT, fragS *, long, int, xtensa_format, int, int *, bfd_boolean); | |
8165 | ||
8166 | ||
e0001a05 NC |
8167 | /* Return the number of bytes added to this fragment, given that the |
8168 | input has been stretched already by "stretch". */ | |
8169 | ||
8170 | long | |
7fa3d080 | 8171 | xtensa_relax_frag (fragS *fragP, long stretch, int *stretched_p) |
e0001a05 | 8172 | { |
43cd72b9 | 8173 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
8174 | int unreported = fragP->tc_frag_data.unreported_expansion; |
8175 | long new_stretch = 0; | |
8176 | char *file_name; | |
d77b99c9 BW |
8177 | unsigned line; |
8178 | int lit_size; | |
43cd72b9 BW |
8179 | static xtensa_insnbuf vbuf = NULL; |
8180 | int slot, num_slots; | |
8181 | xtensa_format fmt; | |
e0001a05 NC |
8182 | |
8183 | as_where (&file_name, &line); | |
8184 | new_logical_line (fragP->fr_file, fragP->fr_line); | |
8185 | ||
8186 | fragP->tc_frag_data.unreported_expansion = 0; | |
8187 | ||
8188 | switch (fragP->fr_subtype) | |
8189 | { | |
8190 | case RELAX_ALIGN_NEXT_OPCODE: | |
8191 | /* Always convert. */ | |
43cd72b9 BW |
8192 | if (fragP->tc_frag_data.relax_seen) |
8193 | new_stretch = relax_frag_loop_align (fragP, stretch); | |
e0001a05 NC |
8194 | break; |
8195 | ||
8196 | case RELAX_LOOP_END: | |
8197 | /* Do nothing. */ | |
8198 | break; | |
8199 | ||
8200 | case RELAX_LOOP_END_ADD_NOP: | |
8201 | /* Add a NOP and switch to .fill 0. */ | |
8202 | new_stretch = relax_frag_add_nop (fragP); | |
43cd72b9 | 8203 | frag_wane (fragP); |
e0001a05 NC |
8204 | break; |
8205 | ||
8206 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 | 8207 | /* Do nothing. The narrowing before this frag will either align |
e0001a05 NC |
8208 | it or not. */ |
8209 | break; | |
8210 | ||
8211 | case RELAX_LITERAL: | |
8212 | case RELAX_LITERAL_FINAL: | |
8213 | return 0; | |
8214 | ||
8215 | case RELAX_LITERAL_NR: | |
8216 | lit_size = 4; | |
8217 | fragP->fr_subtype = RELAX_LITERAL_FINAL; | |
8218 | assert (unreported == lit_size); | |
8219 | memset (&fragP->fr_literal[fragP->fr_fix], 0, 4); | |
8220 | fragP->fr_var -= lit_size; | |
8221 | fragP->fr_fix += lit_size; | |
8222 | new_stretch = 4; | |
8223 | break; | |
8224 | ||
43cd72b9 BW |
8225 | case RELAX_SLOTS: |
8226 | if (vbuf == NULL) | |
8227 | vbuf = xtensa_insnbuf_alloc (isa); | |
8228 | ||
d77b99c9 BW |
8229 | xtensa_insnbuf_from_chars |
8230 | (isa, vbuf, (unsigned char *) fragP->fr_opcode, 0); | |
43cd72b9 BW |
8231 | fmt = xtensa_format_decode (isa, vbuf); |
8232 | num_slots = xtensa_format_num_slots (isa, fmt); | |
e0001a05 | 8233 | |
43cd72b9 BW |
8234 | for (slot = 0; slot < num_slots; slot++) |
8235 | { | |
8236 | switch (fragP->tc_frag_data.slot_subtypes[slot]) | |
8237 | { | |
8238 | case RELAX_NARROW: | |
8239 | if (fragP->tc_frag_data.relax_seen) | |
8240 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8241 | break; | |
8242 | ||
8243 | case RELAX_IMMED: | |
8244 | case RELAX_IMMED_STEP1: | |
8245 | case RELAX_IMMED_STEP2: | |
8246 | /* Place the immediate. */ | |
8247 | new_stretch += relax_frag_immed | |
8248 | (now_seg, fragP, stretch, | |
8249 | fragP->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8250 | fmt, slot, stretched_p, FALSE); | |
8251 | break; | |
8252 | ||
8253 | default: | |
8254 | /* This is OK; see the note in xg_assemble_vliw_tokens. */ | |
8255 | break; | |
8256 | } | |
8257 | } | |
e0001a05 NC |
8258 | break; |
8259 | ||
8260 | case RELAX_LITERAL_POOL_BEGIN: | |
8261 | case RELAX_LITERAL_POOL_END: | |
43cd72b9 BW |
8262 | case RELAX_MAYBE_UNREACHABLE: |
8263 | case RELAX_MAYBE_DESIRE_ALIGN: | |
e0001a05 NC |
8264 | /* No relaxation required. */ |
8265 | break; | |
8266 | ||
43cd72b9 BW |
8267 | case RELAX_FILL_NOP: |
8268 | case RELAX_UNREACHABLE: | |
8269 | if (fragP->tc_frag_data.relax_seen) | |
8270 | new_stretch += relax_frag_for_align (fragP, stretch); | |
8271 | break; | |
8272 | ||
e0001a05 NC |
8273 | default: |
8274 | as_bad (_("bad relaxation state")); | |
8275 | } | |
8276 | ||
43cd72b9 | 8277 | /* Tell gas we need another relaxation pass. */ |
c138bc38 | 8278 | if (! fragP->tc_frag_data.relax_seen) |
43cd72b9 BW |
8279 | { |
8280 | fragP->tc_frag_data.relax_seen = TRUE; | |
8281 | *stretched_p = 1; | |
8282 | } | |
8283 | ||
e0001a05 NC |
8284 | new_logical_line (file_name, line); |
8285 | return new_stretch; | |
8286 | } | |
8287 | ||
8288 | ||
8289 | static long | |
7fa3d080 | 8290 | relax_frag_loop_align (fragS *fragP, long stretch) |
e0001a05 NC |
8291 | { |
8292 | addressT old_address, old_next_address, old_size; | |
8293 | addressT new_address, new_next_address, new_size; | |
8294 | addressT growth; | |
8295 | ||
43cd72b9 BW |
8296 | /* All the frags with relax_frag_for_alignment prior to this one in the |
8297 | section have been done, hopefully eliminating the need for a NOP here. | |
8298 | But, this will put it in if necessary. */ | |
e0001a05 NC |
8299 | |
8300 | /* Calculate the old address of this fragment and the next fragment. */ | |
8301 | old_address = fragP->fr_address - stretch; | |
8302 | old_next_address = (fragP->fr_address - stretch + fragP->fr_fix + | |
43cd72b9 | 8303 | fragP->tc_frag_data.text_expansion[0]); |
e0001a05 NC |
8304 | old_size = old_next_address - old_address; |
8305 | ||
8306 | /* Calculate the new address of this fragment and the next fragment. */ | |
8307 | new_address = fragP->fr_address; | |
8308 | new_next_address = | |
8309 | get_noop_aligned_address (fragP, fragP->fr_address + fragP->fr_fix); | |
8310 | new_size = new_next_address - new_address; | |
8311 | ||
8312 | growth = new_size - old_size; | |
8313 | ||
8314 | /* Fix up the text_expansion field and return the new growth. */ | |
43cd72b9 | 8315 | fragP->tc_frag_data.text_expansion[0] += growth; |
e0001a05 NC |
8316 | return growth; |
8317 | } | |
8318 | ||
8319 | ||
43cd72b9 | 8320 | /* Add a NOP instruction. */ |
e0001a05 NC |
8321 | |
8322 | static long | |
7fa3d080 | 8323 | relax_frag_add_nop (fragS *fragP) |
e0001a05 | 8324 | { |
e0001a05 | 8325 | char *nop_buf = fragP->fr_literal + fragP->fr_fix; |
43cd72b9 BW |
8326 | int length = fragP->tc_frag_data.is_no_density ? 3 : 2; |
8327 | assemble_nop (length, nop_buf); | |
e0001a05 | 8328 | fragP->tc_frag_data.is_insn = TRUE; |
e0001a05 | 8329 | |
e0001a05 NC |
8330 | if (fragP->fr_var < length) |
8331 | { | |
dd49a749 | 8332 | as_fatal (_("fr_var (%ld) < length (%d)"), (long) fragP->fr_var, length); |
e0001a05 NC |
8333 | return 0; |
8334 | } | |
8335 | ||
8336 | fragP->fr_fix += length; | |
8337 | fragP->fr_var -= length; | |
e0001a05 NC |
8338 | return length; |
8339 | } | |
8340 | ||
8341 | ||
7fa3d080 BW |
8342 | static long future_alignment_required (fragS *, long); |
8343 | ||
e0001a05 | 8344 | static long |
7fa3d080 | 8345 | relax_frag_for_align (fragS *fragP, long stretch) |
e0001a05 | 8346 | { |
43cd72b9 BW |
8347 | /* Overview of the relaxation procedure for alignment: |
8348 | We can widen with NOPs or by widening instructions or by filling | |
8349 | bytes after jump instructions. Find the opportune places and widen | |
8350 | them if necessary. */ | |
8351 | ||
8352 | long stretch_me; | |
8353 | long diff; | |
e0001a05 | 8354 | |
43cd72b9 BW |
8355 | assert (fragP->fr_subtype == RELAX_FILL_NOP |
8356 | || fragP->fr_subtype == RELAX_UNREACHABLE | |
8357 | || (fragP->fr_subtype == RELAX_SLOTS | |
8358 | && fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW)); | |
8359 | ||
8360 | stretch_me = future_alignment_required (fragP, stretch); | |
8361 | diff = stretch_me - fragP->tc_frag_data.text_expansion[0]; | |
8362 | if (diff == 0) | |
8363 | return 0; | |
e0001a05 | 8364 | |
43cd72b9 | 8365 | if (diff < 0) |
e0001a05 | 8366 | { |
43cd72b9 BW |
8367 | /* We expanded on a previous pass. Can we shrink now? */ |
8368 | long shrink = fragP->tc_frag_data.text_expansion[0] - stretch_me; | |
8369 | if (shrink <= stretch && stretch > 0) | |
e0001a05 | 8370 | { |
43cd72b9 BW |
8371 | fragP->tc_frag_data.text_expansion[0] = stretch_me; |
8372 | return -shrink; | |
e0001a05 NC |
8373 | } |
8374 | return 0; | |
8375 | } | |
8376 | ||
43cd72b9 BW |
8377 | /* Below here, diff > 0. */ |
8378 | fragP->tc_frag_data.text_expansion[0] = stretch_me; | |
e0001a05 | 8379 | |
43cd72b9 | 8380 | return diff; |
e0001a05 NC |
8381 | } |
8382 | ||
8383 | ||
43cd72b9 BW |
8384 | /* Return the address of the next frag that should be aligned. |
8385 | ||
8386 | By "address" we mean the address it _would_ be at if there | |
8387 | is no action taken to align it between here and the target frag. | |
8388 | In other words, if no narrows and no fill nops are used between | |
8389 | here and the frag to align, _even_if_ some of the frags we use | |
8390 | to align targets have already expanded on a previous relaxation | |
8391 | pass. | |
8392 | ||
8393 | Also, count each frag that may be used to help align the target. | |
8394 | ||
8395 | Return 0 if there are no frags left in the chain that need to be | |
8396 | aligned. */ | |
8397 | ||
8398 | static addressT | |
7fa3d080 BW |
8399 | find_address_of_next_align_frag (fragS **fragPP, |
8400 | int *wide_nops, | |
8401 | int *narrow_nops, | |
8402 | int *widens, | |
8403 | bfd_boolean *paddable) | |
e0001a05 | 8404 | { |
43cd72b9 BW |
8405 | fragS *fragP = *fragPP; |
8406 | addressT address = fragP->fr_address; | |
8407 | ||
8408 | /* Do not reset the counts to 0. */ | |
e0001a05 NC |
8409 | |
8410 | while (fragP) | |
8411 | { | |
8412 | /* Limit this to a small search. */ | |
b5e4a23d | 8413 | if (*widens >= (int) xtensa_fetch_width) |
43cd72b9 BW |
8414 | { |
8415 | *fragPP = fragP; | |
8416 | return 0; | |
8417 | } | |
e0001a05 NC |
8418 | address += fragP->fr_fix; |
8419 | ||
43cd72b9 BW |
8420 | if (fragP->fr_type == rs_fill) |
8421 | address += fragP->fr_offset * fragP->fr_var; | |
8422 | else if (fragP->fr_type == rs_machine_dependent) | |
e0001a05 | 8423 | { |
e0001a05 NC |
8424 | switch (fragP->fr_subtype) |
8425 | { | |
43cd72b9 BW |
8426 | case RELAX_UNREACHABLE: |
8427 | *paddable = TRUE; | |
8428 | break; | |
8429 | ||
8430 | case RELAX_FILL_NOP: | |
8431 | (*wide_nops)++; | |
8432 | if (!fragP->tc_frag_data.is_no_density) | |
8433 | (*narrow_nops)++; | |
8434 | break; | |
8435 | ||
8436 | case RELAX_SLOTS: | |
8437 | if (fragP->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8438 | { | |
8439 | (*widens)++; | |
8440 | break; | |
8441 | } | |
34e41783 | 8442 | address += total_frag_text_expansion (fragP);; |
e0001a05 NC |
8443 | break; |
8444 | ||
8445 | case RELAX_IMMED: | |
43cd72b9 | 8446 | address += fragP->tc_frag_data.text_expansion[0]; |
e0001a05 NC |
8447 | break; |
8448 | ||
8449 | case RELAX_ALIGN_NEXT_OPCODE: | |
8450 | case RELAX_DESIRE_ALIGN: | |
43cd72b9 BW |
8451 | *fragPP = fragP; |
8452 | return address; | |
8453 | ||
8454 | case RELAX_MAYBE_UNREACHABLE: | |
8455 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8456 | /* Do nothing. */ | |
e0001a05 NC |
8457 | break; |
8458 | ||
8459 | default: | |
43cd72b9 BW |
8460 | /* Just punt if we don't know the type. */ |
8461 | *fragPP = fragP; | |
8462 | return 0; | |
e0001a05 | 8463 | } |
43cd72b9 | 8464 | } |
c138bc38 | 8465 | else |
43cd72b9 BW |
8466 | { |
8467 | /* Just punt if we don't know the type. */ | |
8468 | *fragPP = fragP; | |
8469 | return 0; | |
8470 | } | |
8471 | fragP = fragP->fr_next; | |
8472 | } | |
8473 | ||
8474 | *fragPP = fragP; | |
8475 | return 0; | |
8476 | } | |
8477 | ||
8478 | ||
7fa3d080 BW |
8479 | static long bytes_to_stretch (fragS *, int, int, int, int); |
8480 | ||
43cd72b9 | 8481 | static long |
7fa3d080 | 8482 | future_alignment_required (fragS *fragP, long stretch ATTRIBUTE_UNUSED) |
43cd72b9 BW |
8483 | { |
8484 | fragS *this_frag = fragP; | |
8485 | long address; | |
8486 | int num_widens = 0; | |
8487 | int wide_nops = 0; | |
8488 | int narrow_nops = 0; | |
8489 | bfd_boolean paddable = FALSE; | |
8490 | offsetT local_opt_diff; | |
8491 | offsetT opt_diff; | |
8492 | offsetT max_diff; | |
8493 | int stretch_amount = 0; | |
8494 | int local_stretch_amount; | |
8495 | int global_stretch_amount; | |
8496 | ||
7fa3d080 BW |
8497 | address = find_address_of_next_align_frag |
8498 | (&fragP, &wide_nops, &narrow_nops, &num_widens, &paddable); | |
43cd72b9 | 8499 | |
b5e4a23d BW |
8500 | if (!address) |
8501 | { | |
8502 | if (this_frag->tc_frag_data.is_aligning_branch) | |
8503 | this_frag->tc_frag_data.slot_subtypes[0] = RELAX_IMMED; | |
8504 | else | |
8505 | frag_wane (this_frag); | |
8506 | } | |
8507 | else | |
43cd72b9 BW |
8508 | { |
8509 | local_opt_diff = get_aligned_diff (fragP, address, &max_diff); | |
8510 | opt_diff = local_opt_diff; | |
8511 | assert (opt_diff >= 0); | |
8512 | assert (max_diff >= opt_diff); | |
c138bc38 | 8513 | if (max_diff == 0) |
43cd72b9 | 8514 | return 0; |
d2a033cd | 8515 | |
43cd72b9 BW |
8516 | if (fragP) |
8517 | fragP = fragP->fr_next; | |
8518 | ||
8519 | while (fragP && opt_diff < max_diff && address) | |
8520 | { | |
8521 | /* We only use these to determine if we can exit early | |
c138bc38 | 8522 | because there will be plenty of ways to align future |
43cd72b9 | 8523 | align frags. */ |
d77b99c9 | 8524 | int glob_widens = 0; |
43cd72b9 BW |
8525 | int dnn = 0; |
8526 | int dw = 0; | |
8527 | bfd_boolean glob_pad = 0; | |
7fa3d080 BW |
8528 | address = find_address_of_next_align_frag |
8529 | (&fragP, &glob_widens, &dnn, &dw, &glob_pad); | |
43cd72b9 | 8530 | /* If there is a padable portion, then skip. */ |
664df4e4 | 8531 | if (glob_pad || glob_widens >= (1 << branch_align_power (now_seg))) |
b5e4a23d | 8532 | address = 0; |
43cd72b9 | 8533 | |
c138bc38 | 8534 | if (address) |
43cd72b9 BW |
8535 | { |
8536 | offsetT next_m_diff; | |
8537 | offsetT next_o_diff; | |
8538 | ||
8539 | /* Downrange frags haven't had stretch added to them yet. */ | |
8540 | address += stretch; | |
8541 | ||
8542 | /* The address also includes any text expansion from this | |
8543 | frag in a previous pass, but we don't want that. */ | |
8544 | address -= this_frag->tc_frag_data.text_expansion[0]; | |
8545 | ||
8546 | /* Assume we are going to move at least opt_diff. In | |
8547 | reality, we might not be able to, but assuming that | |
8548 | we will helps catch cases where moving opt_diff pushes | |
8549 | the next target from aligned to unaligned. */ | |
8550 | address += opt_diff; | |
8551 | ||
8552 | next_o_diff = get_aligned_diff (fragP, address, &next_m_diff); | |
8553 | ||
8554 | /* Now cleanup for the adjustments to address. */ | |
8555 | next_o_diff += opt_diff; | |
8556 | next_m_diff += opt_diff; | |
8557 | if (next_o_diff <= max_diff && next_o_diff > opt_diff) | |
8558 | opt_diff = next_o_diff; | |
8559 | if (next_m_diff < max_diff) | |
8560 | max_diff = next_m_diff; | |
8561 | fragP = fragP->fr_next; | |
8562 | } | |
8563 | } | |
d2a033cd | 8564 | |
43cd72b9 BW |
8565 | /* If there are enough wideners in between, do it. */ |
8566 | if (paddable) | |
8567 | { | |
8568 | if (this_frag->fr_subtype == RELAX_UNREACHABLE) | |
8569 | { | |
8570 | assert (opt_diff <= UNREACHABLE_MAX_WIDTH); | |
8571 | return opt_diff; | |
8572 | } | |
8573 | return 0; | |
8574 | } | |
c138bc38 | 8575 | local_stretch_amount |
43cd72b9 BW |
8576 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, |
8577 | num_widens, local_opt_diff); | |
c138bc38 BW |
8578 | global_stretch_amount |
8579 | = bytes_to_stretch (this_frag, wide_nops, narrow_nops, | |
43cd72b9 | 8580 | num_widens, opt_diff); |
c138bc38 BW |
8581 | /* If the condition below is true, then the frag couldn't |
8582 | stretch the correct amount for the global case, so we just | |
8583 | optimize locally. We'll rely on the subsequent frags to get | |
43cd72b9 BW |
8584 | the correct alignment in the global case. */ |
8585 | if (global_stretch_amount < local_stretch_amount) | |
8586 | stretch_amount = local_stretch_amount; | |
8587 | else | |
8588 | stretch_amount = global_stretch_amount; | |
d2a033cd | 8589 | |
43cd72b9 BW |
8590 | if (this_frag->fr_subtype == RELAX_SLOTS |
8591 | && this_frag->tc_frag_data.slot_subtypes[0] == RELAX_NARROW) | |
8592 | assert (stretch_amount <= 1); | |
8593 | else if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8594 | { | |
8595 | if (this_frag->tc_frag_data.is_no_density) | |
8596 | assert (stretch_amount == 3 || stretch_amount == 0); | |
8597 | else | |
8598 | assert (stretch_amount <= 3); | |
8599 | } | |
8600 | } | |
8601 | return stretch_amount; | |
8602 | } | |
8603 | ||
8604 | ||
8605 | /* The idea: widen everything you can to get a target or loop aligned, | |
8606 | then start using NOPs. | |
8607 | ||
8608 | When we must have a NOP, here is a table of how we decide | |
8609 | (so you don't have to fight through the control flow below): | |
8610 | ||
8611 | wide_nops = the number of wide NOPs available for aligning | |
8612 | narrow_nops = the number of narrow NOPs available for aligning | |
8613 | (a subset of wide_nops) | |
8614 | widens = the number of narrow instructions that should be widened | |
8615 | ||
8616 | Desired wide narrow | |
8617 | Diff nop nop widens | |
8618 | 1 0 0 1 | |
8619 | 2 0 1 0 | |
8620 | 3a 1 0 0 | |
8621 | b 0 1 1 (case 3a makes this case unnecessary) | |
8622 | 4a 1 0 1 | |
8623 | b 0 2 0 | |
8624 | c 0 1 2 (case 4a makes this case unnecessary) | |
8625 | 5a 1 0 2 | |
8626 | b 1 1 0 | |
8627 | c 0 2 1 (case 5b makes this case unnecessary) | |
8628 | 6a 2 0 0 | |
8629 | b 1 0 3 | |
708587a4 | 8630 | c 0 1 4 (case 6b makes this case unnecessary) |
43cd72b9 BW |
8631 | d 1 1 1 (case 6a makes this case unnecessary) |
8632 | e 0 2 2 (case 6a makes this case unnecessary) | |
8633 | f 0 3 0 (case 6a makes this case unnecessary) | |
8634 | 7a 1 0 4 | |
8635 | b 2 0 1 | |
8636 | c 1 1 2 (case 7b makes this case unnecessary) | |
8637 | d 0 1 5 (case 7a makes this case unnecessary) | |
8638 | e 0 2 3 (case 7b makes this case unnecessary) | |
8639 | f 0 3 1 (case 7b makes this case unnecessary) | |
8640 | g 1 2 1 (case 7b makes this case unnecessary) | |
8641 | */ | |
8642 | ||
8643 | static long | |
7fa3d080 BW |
8644 | bytes_to_stretch (fragS *this_frag, |
8645 | int wide_nops, | |
8646 | int narrow_nops, | |
8647 | int num_widens, | |
8648 | int desired_diff) | |
43cd72b9 BW |
8649 | { |
8650 | int bytes_short = desired_diff - num_widens; | |
8651 | ||
8652 | assert (desired_diff >= 0 && desired_diff < 8); | |
8653 | if (desired_diff == 0) | |
8654 | return 0; | |
c138bc38 | 8655 | |
43cd72b9 | 8656 | assert (wide_nops > 0 || num_widens > 0); |
e0001a05 | 8657 | |
43cd72b9 BW |
8658 | /* Always prefer widening to NOP-filling. */ |
8659 | if (bytes_short < 0) | |
8660 | { | |
8661 | /* There are enough RELAX_NARROW frags after this one | |
8662 | to align the target without widening this frag in any way. */ | |
8663 | return 0; | |
8664 | } | |
c138bc38 | 8665 | |
43cd72b9 BW |
8666 | if (bytes_short == 0) |
8667 | { | |
8668 | /* Widen every narrow between here and the align target | |
8669 | and the align target will be properly aligned. */ | |
8670 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8671 | return 0; | |
8672 | else | |
8673 | return 1; | |
8674 | } | |
c138bc38 | 8675 | |
43cd72b9 BW |
8676 | /* From here we will need at least one NOP to get an alignment. |
8677 | However, we may not be able to align at all, in which case, | |
8678 | don't widen. */ | |
8679 | if (this_frag->fr_subtype == RELAX_FILL_NOP) | |
8680 | { | |
8681 | switch (desired_diff) | |
8682 | { | |
8683 | case 1: | |
8684 | return 0; | |
8685 | case 2: | |
8686 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 1) | |
8687 | return 2; /* case 2 */ | |
8688 | return 0; | |
c138bc38 | 8689 | case 3: |
43cd72b9 BW |
8690 | if (wide_nops > 1) |
8691 | return 0; | |
8692 | else | |
8693 | return 3; /* case 3a */ | |
8694 | case 4: | |
8695 | if (num_widens >= 1 && wide_nops == 1) | |
8696 | return 3; /* case 4a */ | |
8697 | if (!this_frag->tc_frag_data.is_no_density && narrow_nops == 2) | |
8698 | return 2; /* case 4b */ | |
8699 | return 0; | |
8700 | case 5: | |
8701 | if (num_widens >= 2 && wide_nops == 1) | |
8702 | return 3; /* case 5a */ | |
c138bc38 | 8703 | /* We will need two nops. Are there enough nops |
43cd72b9 BW |
8704 | between here and the align target? */ |
8705 | if (wide_nops < 2 || narrow_nops == 0) | |
8706 | return 0; | |
8707 | /* Are there other nops closer that can serve instead? */ | |
8708 | if (wide_nops > 2 && narrow_nops > 1) | |
8709 | return 0; | |
8710 | /* Take the density one first, because there might not be | |
8711 | another density one available. */ | |
8712 | if (!this_frag->tc_frag_data.is_no_density) | |
8713 | return 2; /* case 5b narrow */ | |
8714 | else | |
8715 | return 3; /* case 5b wide */ | |
8716 | return 0; | |
8717 | case 6: | |
8718 | if (wide_nops == 2) | |
8719 | return 3; /* case 6a */ | |
8720 | else if (num_widens >= 3 && wide_nops == 1) | |
8721 | return 3; /* case 6b */ | |
8722 | return 0; | |
8723 | case 7: | |
8724 | if (wide_nops == 1 && num_widens >= 4) | |
8725 | return 3; /* case 7a */ | |
8726 | else if (wide_nops == 2 && num_widens >= 1) | |
8727 | return 3; /* case 7b */ | |
8728 | return 0; | |
e0001a05 | 8729 | default: |
43cd72b9 | 8730 | assert (0); |
e0001a05 | 8731 | } |
e0001a05 | 8732 | } |
43cd72b9 BW |
8733 | else |
8734 | { | |
c138bc38 | 8735 | /* We will need a NOP no matter what, but should we widen |
43cd72b9 | 8736 | this instruction to help? |
e0001a05 | 8737 | |
03aaa593 | 8738 | This is a RELAX_NARROW frag. */ |
43cd72b9 BW |
8739 | switch (desired_diff) |
8740 | { | |
8741 | case 1: | |
8742 | assert (0); | |
8743 | return 0; | |
8744 | case 2: | |
8745 | case 3: | |
8746 | return 0; | |
8747 | case 4: | |
8748 | if (wide_nops >= 1 && num_widens == 1) | |
8749 | return 1; /* case 4a */ | |
8750 | return 0; | |
8751 | case 5: | |
8752 | if (wide_nops >= 1 && num_widens == 2) | |
8753 | return 1; /* case 5a */ | |
8754 | return 0; | |
8755 | case 6: | |
8756 | if (wide_nops >= 2) | |
8757 | return 0; /* case 6a */ | |
8758 | else if (wide_nops >= 1 && num_widens == 3) | |
8759 | return 1; /* case 6b */ | |
8760 | return 0; | |
8761 | case 7: | |
8762 | if (wide_nops >= 1 && num_widens == 4) | |
8763 | return 1; /* case 7a */ | |
8764 | else if (wide_nops >= 2 && num_widens == 1) | |
8765 | return 1; /* case 7b */ | |
8766 | return 0; | |
8767 | default: | |
8768 | assert (0); | |
8769 | return 0; | |
8770 | } | |
8771 | } | |
8772 | assert (0); | |
8773 | return 0; | |
e0001a05 NC |
8774 | } |
8775 | ||
8776 | ||
8777 | static long | |
7fa3d080 BW |
8778 | relax_frag_immed (segT segP, |
8779 | fragS *fragP, | |
8780 | long stretch, | |
8781 | int min_steps, | |
8782 | xtensa_format fmt, | |
8783 | int slot, | |
8784 | int *stretched_p, | |
8785 | bfd_boolean estimate_only) | |
e0001a05 | 8786 | { |
43cd72b9 | 8787 | TInsn tinsn; |
e0001a05 NC |
8788 | int old_size; |
8789 | bfd_boolean negatable_branch = FALSE; | |
8790 | bfd_boolean branch_jmp_to_next = FALSE; | |
43cd72b9 BW |
8791 | bfd_boolean wide_insn = FALSE; |
8792 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
8793 | IStack istack; |
8794 | offsetT frag_offset; | |
8795 | int num_steps; | |
8796 | fragS *lit_fragP; | |
8797 | int num_text_bytes, num_literal_bytes; | |
43cd72b9 | 8798 | int literal_diff, total_text_diff, this_text_diff, first; |
e0001a05 NC |
8799 | |
8800 | assert (fragP->fr_opcode != NULL); | |
8801 | ||
b5e4a23d BW |
8802 | xg_clear_vinsn (&cur_vinsn); |
8803 | vinsn_from_chars (&cur_vinsn, fragP->fr_opcode); | |
b2d179be | 8804 | if (cur_vinsn.num_slots > 1) |
43cd72b9 BW |
8805 | wide_insn = TRUE; |
8806 | ||
b5e4a23d | 8807 | tinsn = cur_vinsn.slots[slot]; |
43cd72b9 | 8808 | tinsn_immed_from_frag (&tinsn, fragP, slot); |
e0001a05 | 8809 | |
64b607e6 | 8810 | if (estimate_only && xtensa_opcode_is_loop (isa, tinsn.opcode) == 1) |
43cd72b9 | 8811 | return 0; |
e0001a05 | 8812 | |
b08b5071 | 8813 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 8814 | branch_jmp_to_next = is_branch_jmp_to_next (&tinsn, fragP); |
e0001a05 | 8815 | |
43cd72b9 | 8816 | negatable_branch = (xtensa_opcode_is_branch (isa, tinsn.opcode) == 1); |
e0001a05 | 8817 | |
43cd72b9 | 8818 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
8819 | |
8820 | /* Special case: replace a branch to the next instruction with a NOP. | |
8821 | This is required to work around a hardware bug in T1040.0 and also | |
8822 | serves as an optimization. */ | |
8823 | ||
8824 | if (branch_jmp_to_next | |
8825 | && ((old_size == 2) || (old_size == 3)) | |
8826 | && !next_frag_is_loop_target (fragP)) | |
8827 | return 0; | |
8828 | ||
8829 | /* Here is the fun stuff: Get the immediate field from this | |
8830 | instruction. If it fits, we are done. If not, find the next | |
8831 | instruction sequence that fits. */ | |
8832 | ||
8833 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
8834 | istack_init (&istack); | |
43cd72b9 | 8835 | num_steps = xg_assembly_relax (&istack, &tinsn, segP, fragP, frag_offset, |
e0001a05 NC |
8836 | min_steps, stretch); |
8837 | if (num_steps < min_steps) | |
8838 | { | |
8839 | as_fatal (_("internal error: relaxation failed")); | |
8840 | return 0; | |
8841 | } | |
8842 | ||
8843 | if (num_steps > RELAX_IMMED_MAXSTEPS) | |
8844 | { | |
8845 | as_fatal (_("internal error: relaxation requires too many steps")); | |
8846 | return 0; | |
8847 | } | |
8848 | ||
43cd72b9 | 8849 | fragP->tc_frag_data.slot_subtypes[slot] = (int) RELAX_IMMED + num_steps; |
e0001a05 NC |
8850 | |
8851 | /* Figure out the number of bytes needed. */ | |
8852 | lit_fragP = 0; | |
e0001a05 | 8853 | num_literal_bytes = get_num_stack_literal_bytes (&istack); |
43cd72b9 BW |
8854 | literal_diff = |
8855 | num_literal_bytes - fragP->tc_frag_data.literal_expansion[slot]; | |
8856 | first = 0; | |
8857 | while (istack.insn[first].opcode == XTENSA_UNDEFINED) | |
8858 | first++; | |
8859 | num_text_bytes = get_num_stack_text_bytes (&istack); | |
8860 | if (wide_insn) | |
8861 | { | |
8862 | num_text_bytes += old_size; | |
8863 | if (opcode_fits_format_slot (istack.insn[first].opcode, fmt, slot)) | |
8864 | num_text_bytes -= xg_get_single_size (istack.insn[first].opcode); | |
8865 | } | |
8866 | total_text_diff = num_text_bytes - old_size; | |
8867 | this_text_diff = total_text_diff - fragP->tc_frag_data.text_expansion[slot]; | |
e0001a05 NC |
8868 | |
8869 | /* It MUST get larger. If not, we could get an infinite loop. */ | |
43cd72b9 BW |
8870 | assert (num_text_bytes >= 0); |
8871 | assert (literal_diff >= 0); | |
8872 | assert (total_text_diff >= 0); | |
e0001a05 | 8873 | |
43cd72b9 BW |
8874 | fragP->tc_frag_data.text_expansion[slot] = total_text_diff; |
8875 | fragP->tc_frag_data.literal_expansion[slot] = num_literal_bytes; | |
8876 | assert (fragP->tc_frag_data.text_expansion[slot] >= 0); | |
8877 | assert (fragP->tc_frag_data.literal_expansion[slot] >= 0); | |
e0001a05 NC |
8878 | |
8879 | /* Find the associated expandable literal for this. */ | |
8880 | if (literal_diff != 0) | |
8881 | { | |
43cd72b9 | 8882 | lit_fragP = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
8883 | if (lit_fragP) |
8884 | { | |
8885 | assert (literal_diff == 4); | |
8886 | lit_fragP->tc_frag_data.unreported_expansion += literal_diff; | |
8887 | ||
8888 | /* We expect that the literal section state has NOT been | |
8889 | modified yet. */ | |
8890 | assert (lit_fragP->fr_type == rs_machine_dependent | |
8891 | && lit_fragP->fr_subtype == RELAX_LITERAL); | |
8892 | lit_fragP->fr_subtype = RELAX_LITERAL_NR; | |
8893 | ||
8894 | /* We need to mark this section for another iteration | |
8895 | of relaxation. */ | |
8896 | (*stretched_p)++; | |
8897 | } | |
8898 | } | |
8899 | ||
43cd72b9 | 8900 | if (negatable_branch && istack.ninsn > 1) |
1d19a770 | 8901 | update_next_frag_state (fragP); |
e0001a05 | 8902 | |
43cd72b9 | 8903 | return this_text_diff; |
e0001a05 NC |
8904 | } |
8905 | ||
8906 | \f | |
8907 | /* md_convert_frag Hook and Helper Functions. */ | |
8908 | ||
7fa3d080 BW |
8909 | static void convert_frag_align_next_opcode (fragS *); |
8910 | static void convert_frag_narrow (segT, fragS *, xtensa_format, int); | |
8911 | static void convert_frag_fill_nop (fragS *); | |
8912 | static void convert_frag_immed (segT, fragS *, int, xtensa_format, int); | |
8913 | ||
e0001a05 | 8914 | void |
7fa3d080 | 8915 | md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragp) |
e0001a05 | 8916 | { |
43cd72b9 BW |
8917 | static xtensa_insnbuf vbuf = NULL; |
8918 | xtensa_isa isa = xtensa_default_isa; | |
8919 | int slot; | |
8920 | int num_slots; | |
8921 | xtensa_format fmt; | |
e0001a05 | 8922 | char *file_name; |
d77b99c9 | 8923 | unsigned line; |
e0001a05 NC |
8924 | |
8925 | as_where (&file_name, &line); | |
8926 | new_logical_line (fragp->fr_file, fragp->fr_line); | |
8927 | ||
8928 | switch (fragp->fr_subtype) | |
8929 | { | |
8930 | case RELAX_ALIGN_NEXT_OPCODE: | |
8931 | /* Always convert. */ | |
8932 | convert_frag_align_next_opcode (fragp); | |
8933 | break; | |
8934 | ||
8935 | case RELAX_DESIRE_ALIGN: | |
8936 | /* Do nothing. If not aligned already, too bad. */ | |
8937 | break; | |
8938 | ||
43cd72b9 BW |
8939 | case RELAX_LITERAL: |
8940 | case RELAX_LITERAL_FINAL: | |
8941 | break; | |
8942 | ||
8943 | case RELAX_SLOTS: | |
8944 | if (vbuf == NULL) | |
8945 | vbuf = xtensa_insnbuf_alloc (isa); | |
8946 | ||
d77b99c9 BW |
8947 | xtensa_insnbuf_from_chars |
8948 | (isa, vbuf, (unsigned char *) fragp->fr_opcode, 0); | |
43cd72b9 BW |
8949 | fmt = xtensa_format_decode (isa, vbuf); |
8950 | num_slots = xtensa_format_num_slots (isa, fmt); | |
8951 | ||
8952 | for (slot = 0; slot < num_slots; slot++) | |
8953 | { | |
8954 | switch (fragp->tc_frag_data.slot_subtypes[slot]) | |
8955 | { | |
8956 | case RELAX_NARROW: | |
8957 | convert_frag_narrow (sec, fragp, fmt, slot); | |
8958 | break; | |
8959 | ||
8960 | case RELAX_IMMED: | |
8961 | case RELAX_IMMED_STEP1: | |
8962 | case RELAX_IMMED_STEP2: | |
8963 | /* Place the immediate. */ | |
8964 | convert_frag_immed | |
8965 | (sec, fragp, | |
8966 | fragp->tc_frag_data.slot_subtypes[slot] - RELAX_IMMED, | |
8967 | fmt, slot); | |
8968 | break; | |
8969 | ||
8970 | default: | |
8971 | /* This is OK because some slots could have | |
8972 | relaxations and others have none. */ | |
8973 | break; | |
8974 | } | |
8975 | } | |
8976 | break; | |
8977 | ||
8978 | case RELAX_UNREACHABLE: | |
8979 | memset (&fragp->fr_literal[fragp->fr_fix], 0, fragp->fr_var); | |
8980 | fragp->fr_fix += fragp->tc_frag_data.text_expansion[0]; | |
8981 | fragp->fr_var -= fragp->tc_frag_data.text_expansion[0]; | |
8982 | frag_wane (fragp); | |
e0001a05 NC |
8983 | break; |
8984 | ||
43cd72b9 BW |
8985 | case RELAX_MAYBE_UNREACHABLE: |
8986 | case RELAX_MAYBE_DESIRE_ALIGN: | |
8987 | frag_wane (fragp); | |
e0001a05 NC |
8988 | break; |
8989 | ||
43cd72b9 BW |
8990 | case RELAX_FILL_NOP: |
8991 | convert_frag_fill_nop (fragp); | |
e0001a05 NC |
8992 | break; |
8993 | ||
8994 | case RELAX_LITERAL_NR: | |
8995 | if (use_literal_section) | |
8996 | { | |
8997 | /* This should have been handled during relaxation. When | |
8998 | relaxing a code segment, literals sometimes need to be | |
8999 | added to the corresponding literal segment. If that | |
9000 | literal segment has already been relaxed, then we end up | |
9001 | in this situation. Marking the literal segments as data | |
9002 | would make this happen less often (since GAS always relaxes | |
9003 | code before data), but we could still get into trouble if | |
9004 | there are instructions in a segment that is not marked as | |
9005 | containing code. Until we can implement a better solution, | |
9006 | cheat and adjust the addresses of all the following frags. | |
9007 | This could break subsequent alignments, but the linker's | |
9008 | literal coalescing will do that anyway. */ | |
9009 | ||
9010 | fragS *f; | |
9011 | fragp->fr_subtype = RELAX_LITERAL_FINAL; | |
9012 | assert (fragp->tc_frag_data.unreported_expansion == 4); | |
9013 | memset (&fragp->fr_literal[fragp->fr_fix], 0, 4); | |
9014 | fragp->fr_var -= 4; | |
9015 | fragp->fr_fix += 4; | |
9016 | for (f = fragp->fr_next; f; f = f->fr_next) | |
9017 | f->fr_address += 4; | |
9018 | } | |
9019 | else | |
9020 | as_bad (_("invalid relaxation fragment result")); | |
9021 | break; | |
9022 | } | |
9023 | ||
9024 | fragp->fr_var = 0; | |
9025 | new_logical_line (file_name, line); | |
9026 | } | |
9027 | ||
9028 | ||
7fa3d080 BW |
9029 | static void |
9030 | convert_frag_align_next_opcode (fragS *fragp) | |
e0001a05 NC |
9031 | { |
9032 | char *nop_buf; /* Location for Writing. */ | |
e0001a05 NC |
9033 | bfd_boolean use_no_density = fragp->tc_frag_data.is_no_density; |
9034 | addressT aligned_address; | |
d77b99c9 BW |
9035 | offsetT fill_size; |
9036 | int nop, nop_count; | |
e0001a05 NC |
9037 | |
9038 | aligned_address = get_noop_aligned_address (fragp, fragp->fr_address + | |
9039 | fragp->fr_fix); | |
9040 | fill_size = aligned_address - (fragp->fr_address + fragp->fr_fix); | |
9041 | nop_count = get_text_align_nop_count (fill_size, use_no_density); | |
9042 | nop_buf = fragp->fr_literal + fragp->fr_fix; | |
9043 | ||
d77b99c9 | 9044 | for (nop = 0; nop < nop_count; nop++) |
e0001a05 | 9045 | { |
d77b99c9 BW |
9046 | int nop_size; |
9047 | nop_size = get_text_align_nth_nop_size (fill_size, nop, use_no_density); | |
e0001a05 NC |
9048 | |
9049 | assemble_nop (nop_size, nop_buf); | |
9050 | nop_buf += nop_size; | |
9051 | } | |
9052 | ||
9053 | fragp->fr_fix += fill_size; | |
9054 | fragp->fr_var -= fill_size; | |
9055 | } | |
9056 | ||
9057 | ||
9058 | static void | |
7fa3d080 | 9059 | convert_frag_narrow (segT segP, fragS *fragP, xtensa_format fmt, int slot) |
e0001a05 | 9060 | { |
43cd72b9 | 9061 | TInsn tinsn, single_target; |
84b08ed9 | 9062 | int size, old_size, diff; |
e0001a05 NC |
9063 | offsetT frag_offset; |
9064 | ||
43cd72b9 BW |
9065 | assert (slot == 0); |
9066 | tinsn_from_chars (&tinsn, fragP->fr_opcode, 0); | |
9067 | ||
b5e4a23d | 9068 | if (fragP->tc_frag_data.is_aligning_branch == 1) |
43cd72b9 BW |
9069 | { |
9070 | assert (fragP->tc_frag_data.text_expansion[0] == 1 | |
9071 | || fragP->tc_frag_data.text_expansion[0] == 0); | |
9072 | convert_frag_immed (segP, fragP, fragP->tc_frag_data.text_expansion[0], | |
9073 | fmt, slot); | |
9074 | return; | |
9075 | } | |
9076 | ||
9077 | if (fragP->tc_frag_data.text_expansion[0] == 0) | |
e0001a05 NC |
9078 | { |
9079 | /* No conversion. */ | |
9080 | fragP->fr_var = 0; | |
9081 | return; | |
9082 | } | |
9083 | ||
9084 | assert (fragP->fr_opcode != NULL); | |
9085 | ||
43cd72b9 BW |
9086 | /* Frags in this relaxation state should only contain |
9087 | single instruction bundles. */ | |
9088 | tinsn_immed_from_frag (&tinsn, fragP, 0); | |
e0001a05 NC |
9089 | |
9090 | /* Just convert it to a wide form.... */ | |
9091 | size = 0; | |
43cd72b9 | 9092 | old_size = xg_get_single_size (tinsn.opcode); |
e0001a05 NC |
9093 | |
9094 | tinsn_init (&single_target); | |
9095 | frag_offset = fragP->fr_opcode - fragP->fr_literal; | |
9096 | ||
84b08ed9 | 9097 | if (! xg_is_single_relaxable_insn (&tinsn, &single_target, FALSE)) |
43cd72b9 BW |
9098 | { |
9099 | as_bad (_("unable to widen instruction")); | |
9100 | return; | |
9101 | } | |
9102 | ||
9103 | size = xg_get_single_size (single_target.opcode); | |
b2d179be BW |
9104 | xg_emit_insn_to_buf (&single_target, fragP->fr_opcode, fragP, |
9105 | frag_offset, TRUE); | |
e0001a05 NC |
9106 | |
9107 | diff = size - old_size; | |
9108 | assert (diff >= 0); | |
9109 | assert (diff <= fragP->fr_var); | |
9110 | fragP->fr_var -= diff; | |
9111 | fragP->fr_fix += diff; | |
9112 | ||
9113 | /* clean it up */ | |
9114 | fragP->fr_var = 0; | |
9115 | } | |
9116 | ||
9117 | ||
9118 | static void | |
7fa3d080 | 9119 | convert_frag_fill_nop (fragS *fragP) |
43cd72b9 BW |
9120 | { |
9121 | char *loc = &fragP->fr_literal[fragP->fr_fix]; | |
9122 | int size = fragP->tc_frag_data.text_expansion[0]; | |
9123 | assert ((unsigned) size == (fragP->fr_next->fr_address | |
9124 | - fragP->fr_address - fragP->fr_fix)); | |
9125 | if (size == 0) | |
9126 | { | |
9127 | /* No conversion. */ | |
9128 | fragP->fr_var = 0; | |
9129 | return; | |
9130 | } | |
9131 | assemble_nop (size, loc); | |
9132 | fragP->tc_frag_data.is_insn = TRUE; | |
9133 | fragP->fr_var -= size; | |
9134 | fragP->fr_fix += size; | |
9135 | frag_wane (fragP); | |
9136 | } | |
9137 | ||
9138 | ||
7fa3d080 BW |
9139 | static fixS *fix_new_exp_in_seg |
9140 | (segT, subsegT, fragS *, int, int, expressionS *, int, | |
9141 | bfd_reloc_code_real_type); | |
9142 | static void convert_frag_immed_finish_loop (segT, fragS *, TInsn *); | |
9143 | ||
43cd72b9 | 9144 | static void |
7fa3d080 BW |
9145 | convert_frag_immed (segT segP, |
9146 | fragS *fragP, | |
9147 | int min_steps, | |
9148 | xtensa_format fmt, | |
9149 | int slot) | |
e0001a05 NC |
9150 | { |
9151 | char *immed_instr = fragP->fr_opcode; | |
43cd72b9 | 9152 | TInsn orig_tinsn; |
e0001a05 | 9153 | bfd_boolean expanded = FALSE; |
e0001a05 | 9154 | bfd_boolean branch_jmp_to_next = FALSE; |
43cd72b9 | 9155 | char *fr_opcode = fragP->fr_opcode; |
43cd72b9 BW |
9156 | xtensa_isa isa = xtensa_default_isa; |
9157 | bfd_boolean wide_insn = FALSE; | |
9158 | int bytes; | |
9159 | bfd_boolean is_loop; | |
e0001a05 | 9160 | |
43cd72b9 | 9161 | assert (fr_opcode != NULL); |
e0001a05 | 9162 | |
b5e4a23d | 9163 | xg_clear_vinsn (&cur_vinsn); |
e0001a05 | 9164 | |
b5e4a23d | 9165 | vinsn_from_chars (&cur_vinsn, fr_opcode); |
b2d179be | 9166 | if (cur_vinsn.num_slots > 1) |
43cd72b9 | 9167 | wide_insn = TRUE; |
e0001a05 | 9168 | |
b5e4a23d | 9169 | orig_tinsn = cur_vinsn.slots[slot]; |
43cd72b9 BW |
9170 | tinsn_immed_from_frag (&orig_tinsn, fragP, slot); |
9171 | ||
9172 | is_loop = xtensa_opcode_is_loop (xtensa_default_isa, orig_tinsn.opcode) == 1; | |
e0001a05 | 9173 | |
b08b5071 | 9174 | if (workaround_b_j_loop_end && ! fragP->tc_frag_data.is_no_transform) |
43cd72b9 | 9175 | branch_jmp_to_next = is_branch_jmp_to_next (&orig_tinsn, fragP); |
e0001a05 NC |
9176 | |
9177 | if (branch_jmp_to_next && !next_frag_is_loop_target (fragP)) | |
9178 | { | |
9179 | /* Conversion just inserts a NOP and marks the fix as completed. */ | |
43cd72b9 BW |
9180 | bytes = xtensa_format_length (isa, fmt); |
9181 | if (bytes >= 4) | |
9182 | { | |
b5e4a23d BW |
9183 | cur_vinsn.slots[slot].opcode = |
9184 | xtensa_format_slot_nop_opcode (isa, cur_vinsn.format, slot); | |
9185 | cur_vinsn.slots[slot].ntok = 0; | |
43cd72b9 BW |
9186 | } |
9187 | else | |
9188 | { | |
9189 | bytes += fragP->tc_frag_data.text_expansion[0]; | |
9190 | assert (bytes == 2 || bytes == 3); | |
b5e4a23d | 9191 | build_nop (&cur_vinsn.slots[0], bytes); |
43cd72b9 BW |
9192 | fragP->fr_fix += fragP->tc_frag_data.text_expansion[0]; |
9193 | } | |
e7da6241 | 9194 | vinsn_to_insnbuf (&cur_vinsn, fr_opcode, frag_now, TRUE); |
d77b99c9 | 9195 | xtensa_insnbuf_to_chars |
b5e4a23d | 9196 | (isa, cur_vinsn.insnbuf, (unsigned char *) fr_opcode, 0); |
e0001a05 NC |
9197 | fragP->fr_var = 0; |
9198 | } | |
7c834684 | 9199 | else |
e0001a05 | 9200 | { |
43cd72b9 BW |
9201 | /* Here is the fun stuff: Get the immediate field from this |
9202 | instruction. If it fits, we're done. If not, find the next | |
9203 | instruction sequence that fits. */ | |
9204 | ||
e0001a05 NC |
9205 | IStack istack; |
9206 | int i; | |
9207 | symbolS *lit_sym = NULL; | |
9208 | int total_size = 0; | |
43cd72b9 | 9209 | int target_offset = 0; |
e0001a05 NC |
9210 | int old_size; |
9211 | int diff; | |
9212 | symbolS *gen_label = NULL; | |
9213 | offsetT frag_offset; | |
43cd72b9 BW |
9214 | bfd_boolean first = TRUE; |
9215 | bfd_boolean last_is_jump; | |
e0001a05 | 9216 | |
43cd72b9 | 9217 | /* It does not fit. Find something that does and |
e0001a05 | 9218 | convert immediately. */ |
43cd72b9 | 9219 | frag_offset = fr_opcode - fragP->fr_literal; |
e0001a05 | 9220 | istack_init (&istack); |
43cd72b9 | 9221 | xg_assembly_relax (&istack, &orig_tinsn, |
e0001a05 NC |
9222 | segP, fragP, frag_offset, min_steps, 0); |
9223 | ||
43cd72b9 | 9224 | old_size = xtensa_format_length (isa, fmt); |
e0001a05 NC |
9225 | |
9226 | /* Assemble this right inline. */ | |
9227 | ||
9228 | /* First, create the mapping from a label name to the REAL label. */ | |
43cd72b9 | 9229 | target_offset = 0; |
e0001a05 NC |
9230 | for (i = 0; i < istack.ninsn; i++) |
9231 | { | |
43cd72b9 | 9232 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9233 | fragS *lit_frag; |
9234 | ||
43cd72b9 | 9235 | switch (tinsn->insn_type) |
e0001a05 NC |
9236 | { |
9237 | case ITYPE_LITERAL: | |
9238 | if (lit_sym != NULL) | |
9239 | as_bad (_("multiple literals in expansion")); | |
9240 | /* First find the appropriate space in the literal pool. */ | |
43cd72b9 | 9241 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
e0001a05 NC |
9242 | if (lit_frag == NULL) |
9243 | as_bad (_("no registered fragment for literal")); | |
43cd72b9 | 9244 | if (tinsn->ntok != 1) |
e0001a05 NC |
9245 | as_bad (_("number of literal tokens != 1")); |
9246 | ||
9247 | /* Set the literal symbol and add a fixup. */ | |
9248 | lit_sym = lit_frag->fr_symbol; | |
9249 | break; | |
9250 | ||
9251 | case ITYPE_LABEL: | |
43cd72b9 BW |
9252 | if (align_targets && !is_loop) |
9253 | { | |
9254 | fragS *unreach = fragP->fr_next; | |
9255 | while (!(unreach->fr_type == rs_machine_dependent | |
9256 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9257 | || unreach->fr_subtype == RELAX_UNREACHABLE))) | |
9258 | { | |
9259 | unreach = unreach->fr_next; | |
9260 | } | |
9261 | ||
9262 | assert (unreach->fr_type == rs_machine_dependent | |
9263 | && (unreach->fr_subtype == RELAX_MAYBE_UNREACHABLE | |
9264 | || unreach->fr_subtype == RELAX_UNREACHABLE)); | |
9265 | ||
9266 | target_offset += unreach->tc_frag_data.text_expansion[0]; | |
9267 | } | |
e0001a05 NC |
9268 | assert (gen_label == NULL); |
9269 | gen_label = symbol_new (FAKE_LABEL_NAME, now_seg, | |
43cd72b9 BW |
9270 | fr_opcode - fragP->fr_literal |
9271 | + target_offset, fragP); | |
e0001a05 NC |
9272 | break; |
9273 | ||
9274 | case ITYPE_INSN: | |
43cd72b9 BW |
9275 | if (first && wide_insn) |
9276 | { | |
9277 | target_offset += xtensa_format_length (isa, fmt); | |
9278 | first = FALSE; | |
9279 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9280 | target_offset += xg_get_single_size (tinsn->opcode); | |
9281 | } | |
9282 | else | |
9283 | target_offset += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
9284 | break; |
9285 | } | |
9286 | } | |
9287 | ||
9288 | total_size = 0; | |
43cd72b9 BW |
9289 | first = TRUE; |
9290 | last_is_jump = FALSE; | |
e0001a05 NC |
9291 | for (i = 0; i < istack.ninsn; i++) |
9292 | { | |
43cd72b9 | 9293 | TInsn *tinsn = &istack.insn[i]; |
e0001a05 NC |
9294 | fragS *lit_frag; |
9295 | int size; | |
9296 | segT target_seg; | |
43cd72b9 | 9297 | bfd_reloc_code_real_type reloc_type; |
e0001a05 | 9298 | |
43cd72b9 | 9299 | switch (tinsn->insn_type) |
e0001a05 NC |
9300 | { |
9301 | case ITYPE_LITERAL: | |
43cd72b9 BW |
9302 | lit_frag = fragP->tc_frag_data.literal_frags[slot]; |
9303 | /* Already checked. */ | |
e0001a05 NC |
9304 | assert (lit_frag != NULL); |
9305 | assert (lit_sym != NULL); | |
43cd72b9 BW |
9306 | assert (tinsn->ntok == 1); |
9307 | /* Add a fixup. */ | |
e0001a05 NC |
9308 | target_seg = S_GET_SEGMENT (lit_sym); |
9309 | assert (target_seg); | |
43cd72b9 BW |
9310 | if (tinsn->tok[0].X_op == O_pltrel) |
9311 | reloc_type = BFD_RELOC_XTENSA_PLT; | |
9312 | else | |
9313 | reloc_type = BFD_RELOC_32; | |
e0001a05 | 9314 | fix_new_exp_in_seg (target_seg, 0, lit_frag, 0, 4, |
43cd72b9 | 9315 | &tinsn->tok[0], FALSE, reloc_type); |
e0001a05 NC |
9316 | break; |
9317 | ||
9318 | case ITYPE_LABEL: | |
9319 | break; | |
9320 | ||
9321 | case ITYPE_INSN: | |
43cd72b9 BW |
9322 | xg_resolve_labels (tinsn, gen_label); |
9323 | xg_resolve_literals (tinsn, lit_sym); | |
9324 | if (wide_insn && first) | |
9325 | { | |
9326 | first = FALSE; | |
9327 | if (opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9328 | { | |
b5e4a23d | 9329 | cur_vinsn.slots[slot] = *tinsn; |
43cd72b9 BW |
9330 | } |
9331 | else | |
9332 | { | |
b5e4a23d | 9333 | cur_vinsn.slots[slot].opcode = |
43cd72b9 | 9334 | xtensa_format_slot_nop_opcode (isa, fmt, slot); |
b5e4a23d | 9335 | cur_vinsn.slots[slot].ntok = 0; |
43cd72b9 | 9336 | } |
b5e4a23d BW |
9337 | vinsn_to_insnbuf (&cur_vinsn, immed_instr, fragP, TRUE); |
9338 | xtensa_insnbuf_to_chars (isa, cur_vinsn.insnbuf, | |
d77b99c9 | 9339 | (unsigned char *) immed_instr, 0); |
43cd72b9 BW |
9340 | fragP->tc_frag_data.is_insn = TRUE; |
9341 | size = xtensa_format_length (isa, fmt); | |
9342 | if (!opcode_fits_format_slot (tinsn->opcode, fmt, slot)) | |
9343 | { | |
43cd72b9 | 9344 | xg_emit_insn_to_buf |
b2d179be | 9345 | (tinsn, immed_instr + size, fragP, |
43cd72b9 BW |
9346 | immed_instr - fragP->fr_literal + size, TRUE); |
9347 | size += xg_get_single_size (tinsn->opcode); | |
9348 | } | |
9349 | } | |
9350 | else | |
9351 | { | |
43cd72b9 | 9352 | size = xg_get_single_size (tinsn->opcode); |
b2d179be | 9353 | xg_emit_insn_to_buf (tinsn, immed_instr, fragP, |
43cd72b9 | 9354 | immed_instr - fragP->fr_literal, TRUE); |
43cd72b9 | 9355 | } |
e0001a05 | 9356 | immed_instr += size; |
43cd72b9 | 9357 | total_size += size; |
e0001a05 NC |
9358 | break; |
9359 | } | |
9360 | } | |
9361 | ||
9362 | diff = total_size - old_size; | |
9363 | assert (diff >= 0); | |
9364 | if (diff != 0) | |
9365 | expanded = TRUE; | |
9366 | assert (diff <= fragP->fr_var); | |
9367 | fragP->fr_var -= diff; | |
9368 | fragP->fr_fix += diff; | |
9369 | } | |
9370 | ||
e0001a05 | 9371 | /* Check for undefined immediates in LOOP instructions. */ |
43cd72b9 | 9372 | if (is_loop) |
e0001a05 NC |
9373 | { |
9374 | symbolS *sym; | |
43cd72b9 | 9375 | sym = orig_tinsn.tok[1].X_add_symbol; |
e0001a05 NC |
9376 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9377 | { | |
9378 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9379 | return; | |
9380 | } | |
43cd72b9 | 9381 | sym = orig_tinsn.tok[1].X_op_symbol; |
e0001a05 NC |
9382 | if (sym != NULL && !S_IS_DEFINED (sym)) |
9383 | { | |
9384 | as_bad (_("unresolved loop target symbol: %s"), S_GET_NAME (sym)); | |
9385 | return; | |
9386 | } | |
9387 | } | |
9388 | ||
43cd72b9 BW |
9389 | if (expanded && xtensa_opcode_is_loop (isa, orig_tinsn.opcode) == 1) |
9390 | convert_frag_immed_finish_loop (segP, fragP, &orig_tinsn); | |
e0001a05 | 9391 | |
43cd72b9 | 9392 | if (expanded && is_direct_call_opcode (orig_tinsn.opcode)) |
e0001a05 NC |
9393 | { |
9394 | /* Add an expansion note on the expanded instruction. */ | |
9395 | fix_new_exp_in_seg (now_seg, 0, fragP, fr_opcode - fragP->fr_literal, 4, | |
43cd72b9 | 9396 | &orig_tinsn.tok[0], TRUE, |
e0001a05 | 9397 | BFD_RELOC_XTENSA_ASM_EXPAND); |
e0001a05 NC |
9398 | } |
9399 | } | |
9400 | ||
9401 | ||
9402 | /* Add a new fix expression into the desired segment. We have to | |
9403 | switch to that segment to do this. */ | |
9404 | ||
9405 | static fixS * | |
7fa3d080 BW |
9406 | fix_new_exp_in_seg (segT new_seg, |
9407 | subsegT new_subseg, | |
9408 | fragS *frag, | |
9409 | int where, | |
9410 | int size, | |
9411 | expressionS *exp, | |
9412 | int pcrel, | |
9413 | bfd_reloc_code_real_type r_type) | |
e0001a05 NC |
9414 | { |
9415 | fixS *new_fix; | |
9416 | segT seg = now_seg; | |
9417 | subsegT subseg = now_subseg; | |
43cd72b9 | 9418 | |
e0001a05 NC |
9419 | assert (new_seg != 0); |
9420 | subseg_set (new_seg, new_subseg); | |
9421 | ||
e0001a05 NC |
9422 | new_fix = fix_new_exp (frag, where, size, exp, pcrel, r_type); |
9423 | subseg_set (seg, subseg); | |
9424 | return new_fix; | |
9425 | } | |
9426 | ||
9427 | ||
43cd72b9 BW |
9428 | /* Relax a loop instruction so that it can span loop >256 bytes. |
9429 | ||
9430 | loop as, .L1 | |
9431 | .L0: | |
9432 | rsr as, LEND | |
9433 | wsr as, LBEG | |
9434 | addi as, as, lo8 (label-.L1) | |
9435 | addmi as, as, mid8 (label-.L1) | |
9436 | wsr as, LEND | |
9437 | isync | |
9438 | rsr as, LCOUNT | |
9439 | addi as, as, 1 | |
9440 | .L1: | |
9441 | <<body>> | |
9442 | label: | |
9443 | */ | |
e0001a05 NC |
9444 | |
9445 | static void | |
7fa3d080 | 9446 | convert_frag_immed_finish_loop (segT segP, fragS *fragP, TInsn *tinsn) |
e0001a05 NC |
9447 | { |
9448 | TInsn loop_insn; | |
9449 | TInsn addi_insn; | |
9450 | TInsn addmi_insn; | |
9451 | unsigned long target; | |
9452 | static xtensa_insnbuf insnbuf = NULL; | |
9453 | unsigned int loop_length, loop_length_hi, loop_length_lo; | |
9454 | xtensa_isa isa = xtensa_default_isa; | |
9455 | addressT loop_offset; | |
9456 | addressT addi_offset = 9; | |
9457 | addressT addmi_offset = 12; | |
43cd72b9 | 9458 | fragS *next_fragP; |
d77b99c9 | 9459 | int target_count; |
e0001a05 NC |
9460 | |
9461 | if (!insnbuf) | |
9462 | insnbuf = xtensa_insnbuf_alloc (isa); | |
9463 | ||
9464 | /* Get the loop offset. */ | |
43cd72b9 | 9465 | loop_offset = get_expanded_loop_offset (tinsn->opcode); |
e0001a05 | 9466 | |
43cd72b9 BW |
9467 | /* Validate that there really is a LOOP at the loop_offset. Because |
9468 | loops are not bundleable, we can assume that the instruction will be | |
9469 | in slot 0. */ | |
9470 | tinsn_from_chars (&loop_insn, fragP->fr_opcode + loop_offset, 0); | |
9471 | tinsn_immed_from_frag (&loop_insn, fragP, 0); | |
9472 | ||
9473 | assert (xtensa_opcode_is_loop (isa, loop_insn.opcode) == 1); | |
e0001a05 NC |
9474 | addi_offset += loop_offset; |
9475 | addmi_offset += loop_offset; | |
9476 | ||
43cd72b9 | 9477 | assert (tinsn->ntok == 2); |
b08b5071 BW |
9478 | if (tinsn->tok[1].X_op == O_constant) |
9479 | target = tinsn->tok[1].X_add_number; | |
9480 | else if (tinsn->tok[1].X_op == O_symbol) | |
9481 | { | |
9482 | /* Find the fragment. */ | |
9483 | symbolS *sym = tinsn->tok[1].X_add_symbol; | |
9484 | assert (S_GET_SEGMENT (sym) == segP | |
9485 | || S_GET_SEGMENT (sym) == absolute_section); | |
9486 | target = (S_GET_VALUE (sym) + tinsn->tok[1].X_add_number); | |
9487 | } | |
9488 | else | |
9489 | { | |
9490 | as_bad (_("invalid expression evaluation type %d"), tinsn->tok[1].X_op); | |
9491 | target = 0; | |
9492 | } | |
e0001a05 NC |
9493 | |
9494 | know (symbolP); | |
9495 | know (symbolP->sy_frag); | |
9496 | know (!(S_GET_SEGMENT (symbolP) == absolute_section) | |
9497 | || symbol_get_frag (symbolP) == &zero_address_frag); | |
9498 | ||
9499 | loop_length = target - (fragP->fr_address + fragP->fr_fix); | |
9500 | loop_length_hi = loop_length & ~0x0ff; | |
9501 | loop_length_lo = loop_length & 0x0ff; | |
9502 | if (loop_length_lo >= 128) | |
9503 | { | |
9504 | loop_length_lo -= 256; | |
9505 | loop_length_hi += 256; | |
9506 | } | |
9507 | ||
43cd72b9 | 9508 | /* Because addmi sign-extends the immediate, 'loop_length_hi' can be at most |
e0001a05 NC |
9509 | 32512. If the loop is larger than that, then we just fail. */ |
9510 | if (loop_length_hi > 32512) | |
9511 | as_bad_where (fragP->fr_file, fragP->fr_line, | |
9512 | _("loop too long for LOOP instruction")); | |
9513 | ||
43cd72b9 | 9514 | tinsn_from_chars (&addi_insn, fragP->fr_opcode + addi_offset, 0); |
e0001a05 NC |
9515 | assert (addi_insn.opcode == xtensa_addi_opcode); |
9516 | ||
43cd72b9 | 9517 | tinsn_from_chars (&addmi_insn, fragP->fr_opcode + addmi_offset, 0); |
e0001a05 NC |
9518 | assert (addmi_insn.opcode == xtensa_addmi_opcode); |
9519 | ||
9520 | set_expr_const (&addi_insn.tok[2], loop_length_lo); | |
9521 | tinsn_to_insnbuf (&addi_insn, insnbuf); | |
43cd72b9 | 9522 | |
e0001a05 | 9523 | fragP->tc_frag_data.is_insn = TRUE; |
d77b99c9 BW |
9524 | xtensa_insnbuf_to_chars |
9525 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addi_offset, 0); | |
e0001a05 NC |
9526 | |
9527 | set_expr_const (&addmi_insn.tok[2], loop_length_hi); | |
9528 | tinsn_to_insnbuf (&addmi_insn, insnbuf); | |
d77b99c9 BW |
9529 | xtensa_insnbuf_to_chars |
9530 | (isa, insnbuf, (unsigned char *) fragP->fr_opcode + addmi_offset, 0); | |
43cd72b9 BW |
9531 | |
9532 | /* Walk through all of the frags from here to the loop end | |
9533 | and mark them as no_transform to keep them from being modified | |
9534 | by the linker. If we ever have a relocation for the | |
9535 | addi/addmi of the difference of two symbols we can remove this. */ | |
9536 | ||
9537 | target_count = 0; | |
9538 | for (next_fragP = fragP; next_fragP != NULL; | |
9539 | next_fragP = next_fragP->fr_next) | |
9540 | { | |
b08b5071 | 9541 | next_fragP->tc_frag_data.is_no_transform = TRUE; |
43cd72b9 BW |
9542 | if (next_fragP->tc_frag_data.is_loop_target) |
9543 | target_count++; | |
9544 | if (target_count == 2) | |
9545 | break; | |
9546 | } | |
e0001a05 NC |
9547 | } |
9548 | ||
b08b5071 BW |
9549 | \f |
9550 | /* A map that keeps information on a per-subsegment basis. This is | |
9551 | maintained during initial assembly, but is invalid once the | |
9552 | subsegments are smashed together. I.E., it cannot be used during | |
9553 | the relaxation. */ | |
e0001a05 | 9554 | |
b08b5071 | 9555 | typedef struct subseg_map_struct |
e0001a05 | 9556 | { |
b08b5071 BW |
9557 | /* the key */ |
9558 | segT seg; | |
9559 | subsegT subseg; | |
e0001a05 | 9560 | |
b08b5071 BW |
9561 | /* the data */ |
9562 | unsigned flags; | |
9563 | float total_freq; /* fall-through + branch target frequency */ | |
9564 | float target_freq; /* branch target frequency alone */ | |
9565 | ||
9566 | struct subseg_map_struct *next; | |
9567 | } subseg_map; | |
e0001a05 | 9568 | |
e0001a05 | 9569 | |
e0001a05 NC |
9570 | static subseg_map *sseg_map = NULL; |
9571 | ||
43cd72b9 | 9572 | static subseg_map * |
7fa3d080 | 9573 | get_subseg_info (segT seg, subsegT subseg) |
e0001a05 NC |
9574 | { |
9575 | subseg_map *subseg_e; | |
9576 | ||
9577 | for (subseg_e = sseg_map; subseg_e; subseg_e = subseg_e->next) | |
e0001a05 | 9578 | { |
43cd72b9 | 9579 | if (seg == subseg_e->seg && subseg == subseg_e->subseg) |
b08b5071 | 9580 | break; |
e0001a05 | 9581 | } |
b08b5071 BW |
9582 | return subseg_e; |
9583 | } | |
9584 | ||
9585 | ||
9586 | static subseg_map * | |
9587 | add_subseg_info (segT seg, subsegT subseg) | |
9588 | { | |
9589 | subseg_map *subseg_e = (subseg_map *) xmalloc (sizeof (subseg_map)); | |
43cd72b9 BW |
9590 | memset (subseg_e, 0, sizeof (subseg_map)); |
9591 | subseg_e->seg = seg; | |
9592 | subseg_e->subseg = subseg; | |
9593 | subseg_e->flags = 0; | |
9594 | /* Start off considering every branch target very important. */ | |
b08b5071 BW |
9595 | subseg_e->target_freq = 1.0; |
9596 | subseg_e->total_freq = 1.0; | |
43cd72b9 BW |
9597 | subseg_e->next = sseg_map; |
9598 | sseg_map = subseg_e; | |
43cd72b9 BW |
9599 | return subseg_e; |
9600 | } | |
e0001a05 | 9601 | |
7fa3d080 BW |
9602 | |
9603 | static unsigned | |
9604 | get_last_insn_flags (segT seg, subsegT subseg) | |
9605 | { | |
9606 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9607 | if (subseg_e) |
9608 | return subseg_e->flags; | |
9609 | return 0; | |
7fa3d080 BW |
9610 | } |
9611 | ||
9612 | ||
43cd72b9 | 9613 | static void |
7fa3d080 BW |
9614 | set_last_insn_flags (segT seg, |
9615 | subsegT subseg, | |
9616 | unsigned fl, | |
9617 | bfd_boolean val) | |
43cd72b9 BW |
9618 | { |
9619 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
b08b5071 BW |
9620 | if (! subseg_e) |
9621 | subseg_e = add_subseg_info (seg, subseg); | |
e0001a05 NC |
9622 | if (val) |
9623 | subseg_e->flags |= fl; | |
9624 | else | |
9625 | subseg_e->flags &= ~fl; | |
9626 | } | |
9627 | ||
b08b5071 BW |
9628 | |
9629 | static float | |
9630 | get_subseg_total_freq (segT seg, subsegT subseg) | |
9631 | { | |
9632 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9633 | if (subseg_e) | |
9634 | return subseg_e->total_freq; | |
9635 | return 1.0; | |
9636 | } | |
9637 | ||
9638 | ||
9639 | static float | |
9640 | get_subseg_target_freq (segT seg, subsegT subseg) | |
9641 | { | |
9642 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9643 | if (subseg_e) | |
9644 | return subseg_e->target_freq; | |
9645 | return 1.0; | |
9646 | } | |
9647 | ||
9648 | ||
9649 | static void | |
9650 | set_subseg_freq (segT seg, subsegT subseg, float total_f, float target_f) | |
9651 | { | |
9652 | subseg_map *subseg_e = get_subseg_info (seg, subseg); | |
9653 | if (! subseg_e) | |
9654 | subseg_e = add_subseg_info (seg, subseg); | |
9655 | subseg_e->total_freq = total_f; | |
9656 | subseg_e->target_freq = target_f; | |
9657 | } | |
9658 | ||
e0001a05 NC |
9659 | \f |
9660 | /* Segment Lists and emit_state Stuff. */ | |
9661 | ||
e0001a05 | 9662 | static void |
7fa3d080 | 9663 | xtensa_move_seg_list_to_beginning (seg_list *head) |
e0001a05 NC |
9664 | { |
9665 | head = head->next; | |
9666 | while (head) | |
9667 | { | |
9668 | segT literal_section = head->seg; | |
9669 | ||
9670 | /* Move the literal section to the front of the section list. */ | |
9671 | assert (literal_section); | |
69852798 AM |
9672 | if (literal_section != stdoutput->sections) |
9673 | { | |
9674 | bfd_section_list_remove (stdoutput, literal_section); | |
9675 | bfd_section_list_prepend (stdoutput, literal_section); | |
9676 | } | |
e0001a05 NC |
9677 | head = head->next; |
9678 | } | |
9679 | } | |
9680 | ||
9681 | ||
7fa3d080 BW |
9682 | static void mark_literal_frags (seg_list *); |
9683 | ||
9684 | static void | |
9685 | xtensa_move_literals (void) | |
e0001a05 NC |
9686 | { |
9687 | seg_list *segment; | |
9688 | frchainS *frchain_from, *frchain_to; | |
9689 | fragS *search_frag, *next_frag, *last_frag, *literal_pool, *insert_after; | |
9690 | fragS **frag_splice; | |
9691 | emit_state state; | |
9692 | segT dest_seg; | |
9693 | fixS *fix, *next_fix, **fix_splice; | |
82e7541d | 9694 | sym_list *lit; |
e0001a05 | 9695 | |
a7877748 BW |
9696 | mark_literal_frags (literal_head->next); |
9697 | mark_literal_frags (init_literal_head->next); | |
9698 | mark_literal_frags (fini_literal_head->next); | |
e0001a05 NC |
9699 | |
9700 | if (use_literal_section) | |
9701 | return; | |
9702 | ||
9703 | segment = literal_head->next; | |
9704 | while (segment) | |
9705 | { | |
9706 | frchain_from = seg_info (segment->seg)->frchainP; | |
9707 | search_frag = frchain_from->frch_root; | |
9708 | literal_pool = NULL; | |
9709 | frchain_to = NULL; | |
9710 | frag_splice = &(frchain_from->frch_root); | |
9711 | ||
9712 | while (!search_frag->tc_frag_data.literal_frag) | |
9713 | { | |
9714 | assert (search_frag->fr_fix == 0 | |
9715 | || search_frag->fr_type == rs_align); | |
9716 | search_frag = search_frag->fr_next; | |
9717 | } | |
9718 | ||
9719 | assert (search_frag->tc_frag_data.literal_frag->fr_subtype | |
9720 | == RELAX_LITERAL_POOL_BEGIN); | |
9721 | xtensa_switch_section_emit_state (&state, segment->seg, 0); | |
9722 | ||
9723 | /* Make sure that all the frags in this series are closed, and | |
9724 | that there is at least one left over of zero-size. This | |
9725 | prevents us from making a segment with an frchain without any | |
9726 | frags in it. */ | |
9727 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9728 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9729 | last_frag = frag_now; |
9730 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9731 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9732 | |
43cd72b9 | 9733 | while (search_frag != frag_now) |
e0001a05 NC |
9734 | { |
9735 | next_frag = search_frag->fr_next; | |
9736 | ||
43cd72b9 | 9737 | /* First, move the frag out of the literal section and |
e0001a05 NC |
9738 | to the appropriate place. */ |
9739 | if (search_frag->tc_frag_data.literal_frag) | |
9740 | { | |
9741 | literal_pool = search_frag->tc_frag_data.literal_frag; | |
9742 | assert (literal_pool->fr_subtype == RELAX_LITERAL_POOL_BEGIN); | |
dd49a749 BW |
9743 | frchain_to = literal_pool->tc_frag_data.lit_frchain; |
9744 | assert (frchain_to); | |
e0001a05 NC |
9745 | } |
9746 | insert_after = literal_pool; | |
43cd72b9 | 9747 | |
e0001a05 NC |
9748 | while (insert_after->fr_next->fr_subtype != RELAX_LITERAL_POOL_END) |
9749 | insert_after = insert_after->fr_next; | |
9750 | ||
dd49a749 | 9751 | dest_seg = insert_after->fr_next->tc_frag_data.lit_seg; |
43cd72b9 | 9752 | |
e0001a05 NC |
9753 | *frag_splice = next_frag; |
9754 | search_frag->fr_next = insert_after->fr_next; | |
9755 | insert_after->fr_next = search_frag; | |
9756 | search_frag->tc_frag_data.lit_seg = dest_seg; | |
9757 | ||
9758 | /* Now move any fixups associated with this frag to the | |
9759 | right section. */ | |
9760 | fix = frchain_from->fix_root; | |
9761 | fix_splice = &(frchain_from->fix_root); | |
9762 | while (fix) | |
9763 | { | |
9764 | next_fix = fix->fx_next; | |
9765 | if (fix->fx_frag == search_frag) | |
9766 | { | |
9767 | *fix_splice = next_fix; | |
9768 | fix->fx_next = frchain_to->fix_root; | |
9769 | frchain_to->fix_root = fix; | |
9770 | if (frchain_to->fix_tail == NULL) | |
9771 | frchain_to->fix_tail = fix; | |
9772 | } | |
9773 | else | |
9774 | fix_splice = &(fix->fx_next); | |
9775 | fix = next_fix; | |
9776 | } | |
9777 | search_frag = next_frag; | |
9778 | } | |
9779 | ||
9780 | if (frchain_from->fix_root != NULL) | |
9781 | { | |
9782 | frchain_from = seg_info (segment->seg)->frchainP; | |
9783 | as_warn (_("fixes not all moved from %s"), segment->seg->name); | |
9784 | ||
9785 | assert (frchain_from->fix_root == NULL); | |
9786 | } | |
9787 | frchain_from->fix_tail = NULL; | |
9788 | xtensa_restore_emit_state (&state); | |
9789 | segment = segment->next; | |
9790 | } | |
9791 | ||
82e7541d BW |
9792 | /* Now fix up the SEGMENT value for all the literal symbols. */ |
9793 | for (lit = literal_syms; lit; lit = lit->next) | |
9794 | { | |
9795 | symbolS *lit_sym = lit->sym; | |
9796 | segT dest_seg = symbol_get_frag (lit_sym)->tc_frag_data.lit_seg; | |
43cd72b9 BW |
9797 | if (dest_seg) |
9798 | S_SET_SEGMENT (lit_sym, dest_seg); | |
82e7541d | 9799 | } |
e0001a05 NC |
9800 | } |
9801 | ||
9802 | ||
a7877748 BW |
9803 | /* Walk over all the frags for segments in a list and mark them as |
9804 | containing literals. As clunky as this is, we can't rely on frag_var | |
9805 | and frag_variant to get called in all situations. */ | |
9806 | ||
9807 | static void | |
7fa3d080 | 9808 | mark_literal_frags (seg_list *segment) |
a7877748 BW |
9809 | { |
9810 | frchainS *frchain_from; | |
9811 | fragS *search_frag; | |
9812 | ||
9813 | while (segment) | |
9814 | { | |
9815 | frchain_from = seg_info (segment->seg)->frchainP; | |
9816 | search_frag = frchain_from->frch_root; | |
c138bc38 | 9817 | while (search_frag) |
a7877748 BW |
9818 | { |
9819 | search_frag->tc_frag_data.is_literal = TRUE; | |
9820 | search_frag = search_frag->fr_next; | |
9821 | } | |
9822 | segment = segment->next; | |
9823 | } | |
9824 | } | |
9825 | ||
9826 | ||
e0001a05 | 9827 | static void |
7fa3d080 | 9828 | xtensa_reorder_seg_list (seg_list *head, segT after) |
e0001a05 NC |
9829 | { |
9830 | /* Move all of the sections in the section list to come | |
9831 | after "after" in the gnu segment list. */ | |
9832 | ||
9833 | head = head->next; | |
9834 | while (head) | |
9835 | { | |
9836 | segT literal_section = head->seg; | |
9837 | ||
9838 | /* Move the literal section after "after". */ | |
9839 | assert (literal_section); | |
9840 | if (literal_section != after) | |
9841 | { | |
69852798 AM |
9842 | bfd_section_list_remove (stdoutput, literal_section); |
9843 | bfd_section_list_insert_after (stdoutput, after, literal_section); | |
e0001a05 NC |
9844 | } |
9845 | ||
9846 | head = head->next; | |
9847 | } | |
9848 | } | |
9849 | ||
9850 | ||
9851 | /* Push all the literal segments to the end of the gnu list. */ | |
9852 | ||
7fa3d080 BW |
9853 | static void |
9854 | xtensa_reorder_segments (void) | |
e0001a05 NC |
9855 | { |
9856 | segT sec; | |
b08b5071 | 9857 | segT last_sec = 0; |
e0001a05 NC |
9858 | int old_count = 0; |
9859 | int new_count = 0; | |
9860 | ||
9861 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
b08b5071 BW |
9862 | { |
9863 | last_sec = sec; | |
9864 | old_count++; | |
9865 | } | |
e0001a05 NC |
9866 | |
9867 | /* Now that we have the last section, push all the literal | |
9868 | sections to the end. */ | |
e0001a05 NC |
9869 | xtensa_reorder_seg_list (literal_head, last_sec); |
9870 | xtensa_reorder_seg_list (init_literal_head, last_sec); | |
9871 | xtensa_reorder_seg_list (fini_literal_head, last_sec); | |
9872 | ||
9873 | /* Now perform the final error check. */ | |
9874 | for (sec = stdoutput->sections; sec != NULL; sec = sec->next) | |
9875 | new_count++; | |
9876 | assert (new_count == old_count); | |
9877 | } | |
9878 | ||
9879 | ||
e0001a05 NC |
9880 | /* Change the emit state (seg, subseg, and frag related stuff) to the |
9881 | correct location. Return a emit_state which can be passed to | |
9882 | xtensa_restore_emit_state to return to current fragment. */ | |
9883 | ||
7fa3d080 BW |
9884 | static void |
9885 | xtensa_switch_to_literal_fragment (emit_state *result) | |
43cd72b9 BW |
9886 | { |
9887 | if (directive_state[directive_absolute_literals]) | |
9888 | { | |
9889 | cache_literal_section (0, default_lit_sections.lit4_seg_name, | |
9890 | &default_lit_sections.lit4_seg, FALSE); | |
9891 | xtensa_switch_section_emit_state (result, | |
9892 | default_lit_sections.lit4_seg, 0); | |
9893 | } | |
9894 | else | |
9895 | xtensa_switch_to_non_abs_literal_fragment (result); | |
9896 | ||
9897 | /* Do a 4-byte align here. */ | |
9898 | frag_align (2, 0, 0); | |
9899 | record_alignment (now_seg, 2); | |
9900 | } | |
9901 | ||
9902 | ||
7fa3d080 BW |
9903 | static void |
9904 | xtensa_switch_to_non_abs_literal_fragment (emit_state *result) | |
e0001a05 NC |
9905 | { |
9906 | /* When we mark a literal pool location, we want to put a frag in | |
9907 | the literal pool that points to it. But to do that, we want to | |
9908 | switch_to_literal_fragment. But literal sections don't have | |
9909 | literal pools, so their location is always null, so we would | |
9910 | recurse forever. This is kind of hacky, but it works. */ | |
9911 | ||
9912 | static bfd_boolean recursive = FALSE; | |
9913 | fragS *pool_location = get_literal_pool_location (now_seg); | |
c138bc38 | 9914 | bfd_boolean is_init = |
e0001a05 NC |
9915 | (now_seg && !strcmp (segment_name (now_seg), INIT_SECTION_NAME)); |
9916 | ||
c138bc38 | 9917 | bfd_boolean is_fini = |
e0001a05 | 9918 | (now_seg && !strcmp (segment_name (now_seg), FINI_SECTION_NAME)); |
e0001a05 | 9919 | |
43cd72b9 BW |
9920 | if (pool_location == NULL |
9921 | && !use_literal_section | |
e0001a05 NC |
9922 | && !recursive |
9923 | && !is_init && ! is_fini) | |
9924 | { | |
43cd72b9 | 9925 | as_bad (_("literal pool location required for text-section-literals; specify with .literal_position")); |
e0001a05 | 9926 | recursive = TRUE; |
61846f28 | 9927 | xtensa_mark_literal_pool_location (); |
e0001a05 NC |
9928 | recursive = FALSE; |
9929 | } | |
9930 | ||
9931 | /* Special case: If we are in the ".fini" or ".init" section, then | |
9932 | we will ALWAYS be generating to the ".fini.literal" and | |
9933 | ".init.literal" sections. */ | |
9934 | ||
9935 | if (is_init) | |
9936 | { | |
9937 | cache_literal_section (init_literal_head, | |
9938 | default_lit_sections.init_lit_seg_name, | |
43cd72b9 | 9939 | &default_lit_sections.init_lit_seg, TRUE); |
e0001a05 NC |
9940 | xtensa_switch_section_emit_state (result, |
9941 | default_lit_sections.init_lit_seg, 0); | |
9942 | } | |
9943 | else if (is_fini) | |
9944 | { | |
9945 | cache_literal_section (fini_literal_head, | |
9946 | default_lit_sections.fini_lit_seg_name, | |
43cd72b9 | 9947 | &default_lit_sections.fini_lit_seg, TRUE); |
e0001a05 NC |
9948 | xtensa_switch_section_emit_state (result, |
9949 | default_lit_sections.fini_lit_seg, 0); | |
9950 | } | |
43cd72b9 | 9951 | else |
e0001a05 NC |
9952 | { |
9953 | cache_literal_section (literal_head, | |
9954 | default_lit_sections.lit_seg_name, | |
43cd72b9 | 9955 | &default_lit_sections.lit_seg, TRUE); |
e0001a05 NC |
9956 | xtensa_switch_section_emit_state (result, |
9957 | default_lit_sections.lit_seg, 0); | |
9958 | } | |
9959 | ||
43cd72b9 BW |
9960 | if (!use_literal_section |
9961 | && !is_init && !is_fini | |
9962 | && get_literal_pool_location (now_seg) != pool_location) | |
e0001a05 NC |
9963 | { |
9964 | /* Close whatever frag is there. */ | |
9965 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9966 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 NC |
9967 | frag_now->tc_frag_data.literal_frag = pool_location; |
9968 | frag_variant (rs_fill, 0, 0, 0, NULL, 0, NULL); | |
43cd72b9 | 9969 | xtensa_set_frag_assembly_state (frag_now); |
e0001a05 | 9970 | } |
e0001a05 NC |
9971 | } |
9972 | ||
9973 | ||
9974 | /* Call this function before emitting data into the literal section. | |
9975 | This is a helper function for xtensa_switch_to_literal_fragment. | |
9976 | This is similar to a .section new_now_seg subseg. */ | |
9977 | ||
7fa3d080 BW |
9978 | static void |
9979 | xtensa_switch_section_emit_state (emit_state *state, | |
9980 | segT new_now_seg, | |
9981 | subsegT new_now_subseg) | |
e0001a05 NC |
9982 | { |
9983 | state->name = now_seg->name; | |
9984 | state->now_seg = now_seg; | |
9985 | state->now_subseg = now_subseg; | |
9986 | state->generating_literals = generating_literals; | |
9987 | generating_literals++; | |
2b0210eb | 9988 | subseg_set (new_now_seg, new_now_subseg); |
e0001a05 NC |
9989 | } |
9990 | ||
9991 | ||
9992 | /* Use to restore the emitting into the normal place. */ | |
9993 | ||
7fa3d080 BW |
9994 | static void |
9995 | xtensa_restore_emit_state (emit_state *state) | |
e0001a05 NC |
9996 | { |
9997 | generating_literals = state->generating_literals; | |
2b0210eb | 9998 | subseg_set (state->now_seg, state->now_subseg); |
e0001a05 NC |
9999 | } |
10000 | ||
10001 | ||
10002 | /* Get a segment of a given name. If the segment is already | |
10003 | present, return it; otherwise, create a new one. */ | |
10004 | ||
10005 | static void | |
7fa3d080 BW |
10006 | cache_literal_section (seg_list *head, |
10007 | const char *name, | |
b08b5071 | 10008 | segT *pseg, |
7fa3d080 | 10009 | bfd_boolean is_code) |
e0001a05 NC |
10010 | { |
10011 | segT current_section = now_seg; | |
10012 | int current_subsec = now_subseg; | |
b08b5071 | 10013 | segT seg; |
e0001a05 | 10014 | |
b08b5071 | 10015 | if (*pseg != 0) |
e0001a05 | 10016 | return; |
e0001a05 | 10017 | |
b08b5071 BW |
10018 | /* Check if the named section exists. */ |
10019 | for (seg = stdoutput->sections; seg; seg = seg->next) | |
10020 | { | |
10021 | if (!strcmp (segment_name (seg), name)) | |
10022 | break; | |
10023 | } | |
e0001a05 | 10024 | |
b08b5071 | 10025 | if (!seg) |
e0001a05 | 10026 | { |
b08b5071 BW |
10027 | /* Create a new literal section. */ |
10028 | seg = subseg_new (name, (subsegT) 0); | |
43cd72b9 | 10029 | if (head) |
b08b5071 BW |
10030 | { |
10031 | /* Add the newly created literal segment to the specified list. */ | |
10032 | seg_list *n = (seg_list *) xmalloc (sizeof (seg_list)); | |
10033 | n->seg = seg; | |
10034 | n->next = head->next; | |
10035 | head->next = n; | |
10036 | } | |
10037 | bfd_set_section_flags (stdoutput, seg, SEC_HAS_CONTENTS | | |
43cd72b9 BW |
10038 | SEC_READONLY | SEC_ALLOC | SEC_LOAD |
10039 | | (is_code ? SEC_CODE : SEC_DATA)); | |
b08b5071 | 10040 | bfd_set_section_alignment (stdoutput, seg, 2); |
e0001a05 NC |
10041 | } |
10042 | ||
b08b5071 BW |
10043 | *pseg = seg; |
10044 | subseg_set (current_section, current_subsec); | |
e0001a05 NC |
10045 | } |
10046 | ||
43cd72b9 BW |
10047 | \f |
10048 | /* Property Tables Stuff. */ | |
10049 | ||
7fa3d080 BW |
10050 | #define XTENSA_INSN_SEC_NAME ".xt.insn" |
10051 | #define XTENSA_LIT_SEC_NAME ".xt.lit" | |
10052 | #define XTENSA_PROP_SEC_NAME ".xt.prop" | |
10053 | ||
10054 | typedef bfd_boolean (*frag_predicate) (const fragS *); | |
10055 | typedef void (*frag_flags_fn) (const fragS *, frag_flags *); | |
10056 | ||
b08b5071 | 10057 | static bfd_boolean get_frag_is_literal (const fragS *); |
7fa3d080 BW |
10058 | static void xtensa_create_property_segments |
10059 | (frag_predicate, frag_predicate, const char *, xt_section_type); | |
10060 | static void xtensa_create_xproperty_segments | |
10061 | (frag_flags_fn, const char *, xt_section_type); | |
10062 | static segment_info_type *retrieve_segment_info (segT); | |
10063 | static segT retrieve_xtensa_section (char *); | |
10064 | static bfd_boolean section_has_property (segT, frag_predicate); | |
10065 | static bfd_boolean section_has_xproperty (segT, frag_flags_fn); | |
10066 | static void add_xt_block_frags | |
10067 | (segT, segT, xtensa_block_info **, frag_predicate, frag_predicate); | |
10068 | static bfd_boolean xtensa_frag_flags_is_empty (const frag_flags *); | |
10069 | static void xtensa_frag_flags_init (frag_flags *); | |
10070 | static void get_frag_property_flags (const fragS *, frag_flags *); | |
10071 | static bfd_vma frag_flags_to_number (const frag_flags *); | |
10072 | static void add_xt_prop_frags | |
10073 | (segT, segT, xtensa_block_info **, frag_flags_fn); | |
10074 | ||
10075 | /* Set up property tables after relaxation. */ | |
10076 | ||
10077 | void | |
10078 | xtensa_post_relax_hook (void) | |
10079 | { | |
10080 | xtensa_move_seg_list_to_beginning (literal_head); | |
10081 | xtensa_move_seg_list_to_beginning (init_literal_head); | |
10082 | xtensa_move_seg_list_to_beginning (fini_literal_head); | |
10083 | ||
10084 | xtensa_find_unmarked_state_frags (); | |
10085 | ||
b29757dc BW |
10086 | xtensa_create_property_segments (get_frag_is_literal, |
10087 | NULL, | |
10088 | XTENSA_LIT_SEC_NAME, | |
10089 | xt_literal_sec); | |
7fa3d080 BW |
10090 | xtensa_create_xproperty_segments (get_frag_property_flags, |
10091 | XTENSA_PROP_SEC_NAME, | |
10092 | xt_prop_sec); | |
10093 | ||
10094 | if (warn_unaligned_branch_targets) | |
10095 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_branch_targets, 0); | |
10096 | bfd_map_over_sections (stdoutput, xtensa_find_unaligned_loops, 0); | |
10097 | } | |
10098 | ||
10099 | ||
43cd72b9 BW |
10100 | /* This function is only meaningful after xtensa_move_literals. */ |
10101 | ||
10102 | static bfd_boolean | |
7fa3d080 | 10103 | get_frag_is_literal (const fragS *fragP) |
43cd72b9 BW |
10104 | { |
10105 | assert (fragP != NULL); | |
10106 | return fragP->tc_frag_data.is_literal; | |
10107 | } | |
10108 | ||
10109 | ||
43cd72b9 | 10110 | static void |
7fa3d080 BW |
10111 | xtensa_create_property_segments (frag_predicate property_function, |
10112 | frag_predicate end_property_function, | |
10113 | const char *section_name_base, | |
10114 | xt_section_type sec_type) | |
43cd72b9 BW |
10115 | { |
10116 | segT *seclist; | |
10117 | ||
10118 | /* Walk over all of the current segments. | |
10119 | Walk over each fragment | |
10120 | For each non-empty fragment, | |
10121 | Build a property record (append where possible). */ | |
10122 | ||
10123 | for (seclist = &stdoutput->sections; | |
10124 | seclist && *seclist; | |
10125 | seclist = &(*seclist)->next) | |
10126 | { | |
10127 | segT sec = *seclist; | |
10128 | flagword flags; | |
10129 | ||
10130 | flags = bfd_get_section_flags (stdoutput, sec); | |
10131 | if (flags & SEC_DEBUGGING) | |
10132 | continue; | |
10133 | if (!(flags & SEC_ALLOC)) | |
10134 | continue; | |
10135 | ||
10136 | if (section_has_property (sec, property_function)) | |
10137 | { | |
10138 | char *property_section_name = | |
10139 | xtensa_get_property_section_name (sec, section_name_base); | |
10140 | segT insn_sec = retrieve_xtensa_section (property_section_name); | |
10141 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); | |
10142 | xtensa_block_info **xt_blocks = | |
10143 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; | |
10144 | /* Walk over all of the frchains here and add new sections. */ | |
10145 | add_xt_block_frags (sec, insn_sec, xt_blocks, property_function, | |
10146 | end_property_function); | |
10147 | } | |
10148 | } | |
10149 | ||
10150 | /* Now we fill them out.... */ | |
10151 | ||
10152 | for (seclist = &stdoutput->sections; | |
10153 | seclist && *seclist; | |
10154 | seclist = &(*seclist)->next) | |
10155 | { | |
10156 | segment_info_type *seginfo; | |
10157 | xtensa_block_info *block; | |
10158 | segT sec = *seclist; | |
10159 | ||
10160 | seginfo = seg_info (sec); | |
10161 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10162 | ||
10163 | if (block) | |
10164 | { | |
10165 | xtensa_block_info *cur_block; | |
10166 | /* This is a section with some data. */ | |
10167 | int num_recs = 0; | |
d77b99c9 | 10168 | bfd_size_type rec_size; |
43cd72b9 BW |
10169 | |
10170 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10171 | num_recs++; | |
10172 | ||
10173 | rec_size = num_recs * 8; | |
10174 | bfd_set_section_size (stdoutput, sec, rec_size); | |
10175 | ||
10176 | /* In order to make this work with the assembler, we have to | |
10177 | build some frags and then build the "fixups" for it. It | |
10178 | would be easier to just set the contents then set the | |
10179 | arlents. */ | |
10180 | ||
10181 | if (num_recs) | |
10182 | { | |
10183 | /* Allocate a fragment and leak it. */ | |
10184 | fragS *fragP; | |
d77b99c9 | 10185 | bfd_size_type frag_size; |
43cd72b9 BW |
10186 | fixS *fixes; |
10187 | frchainS *frchainP; | |
10188 | int i; | |
10189 | char *frag_data; | |
10190 | ||
10191 | frag_size = sizeof (fragS) + rec_size; | |
10192 | fragP = (fragS *) xmalloc (frag_size); | |
e0001a05 | 10193 | |
43cd72b9 BW |
10194 | memset (fragP, 0, frag_size); |
10195 | fragP->fr_address = 0; | |
10196 | fragP->fr_next = NULL; | |
10197 | fragP->fr_fix = rec_size; | |
10198 | fragP->fr_var = 0; | |
10199 | fragP->fr_type = rs_fill; | |
10200 | /* The rest are zeros. */ | |
e0001a05 | 10201 | |
43cd72b9 BW |
10202 | frchainP = seginfo->frchainP; |
10203 | frchainP->frch_root = fragP; | |
10204 | frchainP->frch_last = fragP; | |
e0001a05 | 10205 | |
43cd72b9 BW |
10206 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); |
10207 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
e0001a05 | 10208 | |
43cd72b9 BW |
10209 | seginfo->fix_root = fixes; |
10210 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10211 | cur_block = block; | |
10212 | frag_data = &fragP->fr_literal[0]; | |
10213 | for (i = 0; i < num_recs; i++) | |
10214 | { | |
10215 | fixS *fix = &fixes[i]; | |
10216 | assert (cur_block); | |
e0001a05 | 10217 | |
43cd72b9 BW |
10218 | /* Write the fixup. */ |
10219 | if (i != num_recs - 1) | |
10220 | fix->fx_next = &fixes[i + 1]; | |
10221 | else | |
10222 | fix->fx_next = NULL; | |
10223 | fix->fx_size = 4; | |
10224 | fix->fx_done = 0; | |
10225 | fix->fx_frag = fragP; | |
10226 | fix->fx_where = i * 8; | |
10227 | fix->fx_addsy = section_symbol (cur_block->sec); | |
10228 | fix->fx_offset = cur_block->offset; | |
10229 | fix->fx_r_type = BFD_RELOC_32; | |
10230 | fix->fx_file = "Internal Assembly"; | |
10231 | fix->fx_line = 0; | |
e0001a05 | 10232 | |
43cd72b9 BW |
10233 | /* Write the length. */ |
10234 | md_number_to_chars (&frag_data[4 + 8 * i], | |
10235 | cur_block->size, 4); | |
10236 | cur_block = cur_block->next; | |
10237 | } | |
10238 | } | |
10239 | } | |
10240 | } | |
e0001a05 NC |
10241 | } |
10242 | ||
10243 | ||
7fa3d080 BW |
10244 | static void |
10245 | xtensa_create_xproperty_segments (frag_flags_fn flag_fn, | |
10246 | const char *section_name_base, | |
10247 | xt_section_type sec_type) | |
e0001a05 NC |
10248 | { |
10249 | segT *seclist; | |
10250 | ||
10251 | /* Walk over all of the current segments. | |
43cd72b9 BW |
10252 | Walk over each fragment. |
10253 | For each fragment that has instructions, | |
10254 | build an instruction record (append where possible). */ | |
e0001a05 NC |
10255 | |
10256 | for (seclist = &stdoutput->sections; | |
10257 | seclist && *seclist; | |
10258 | seclist = &(*seclist)->next) | |
10259 | { | |
10260 | segT sec = *seclist; | |
43cd72b9 BW |
10261 | flagword flags; |
10262 | ||
10263 | flags = bfd_get_section_flags (stdoutput, sec); | |
6624cbde BW |
10264 | if ((flags & SEC_DEBUGGING) |
10265 | || !(flags & SEC_ALLOC) | |
10266 | || (flags & SEC_MERGE)) | |
43cd72b9 BW |
10267 | continue; |
10268 | ||
10269 | if (section_has_xproperty (sec, flag_fn)) | |
e0001a05 | 10270 | { |
b614a702 BW |
10271 | char *property_section_name = |
10272 | xtensa_get_property_section_name (sec, section_name_base); | |
e0001a05 NC |
10273 | segT insn_sec = retrieve_xtensa_section (property_section_name); |
10274 | segment_info_type *xt_seg_info = retrieve_segment_info (insn_sec); | |
43cd72b9 | 10275 | xtensa_block_info **xt_blocks = |
e0001a05 NC |
10276 | &xt_seg_info->tc_segment_info_data.blocks[sec_type]; |
10277 | /* Walk over all of the frchains here and add new sections. */ | |
43cd72b9 | 10278 | add_xt_prop_frags (sec, insn_sec, xt_blocks, flag_fn); |
e0001a05 NC |
10279 | } |
10280 | } | |
10281 | ||
10282 | /* Now we fill them out.... */ | |
10283 | ||
10284 | for (seclist = &stdoutput->sections; | |
10285 | seclist && *seclist; | |
10286 | seclist = &(*seclist)->next) | |
10287 | { | |
10288 | segment_info_type *seginfo; | |
10289 | xtensa_block_info *block; | |
10290 | segT sec = *seclist; | |
43cd72b9 | 10291 | |
e0001a05 NC |
10292 | seginfo = seg_info (sec); |
10293 | block = seginfo->tc_segment_info_data.blocks[sec_type]; | |
10294 | ||
10295 | if (block) | |
10296 | { | |
10297 | xtensa_block_info *cur_block; | |
10298 | /* This is a section with some data. */ | |
43cd72b9 | 10299 | int num_recs = 0; |
d77b99c9 | 10300 | bfd_size_type rec_size; |
e0001a05 NC |
10301 | |
10302 | for (cur_block = block; cur_block; cur_block = cur_block->next) | |
10303 | num_recs++; | |
10304 | ||
43cd72b9 | 10305 | rec_size = num_recs * (8 + 4); |
e0001a05 NC |
10306 | bfd_set_section_size (stdoutput, sec, rec_size); |
10307 | ||
43cd72b9 BW |
10308 | /* elf_section_data (sec)->this_hdr.sh_entsize = 12; */ |
10309 | ||
10310 | /* In order to make this work with the assembler, we have to build | |
10311 | some frags then build the "fixups" for it. It would be easier to | |
10312 | just set the contents then set the arlents. */ | |
e0001a05 NC |
10313 | |
10314 | if (num_recs) | |
10315 | { | |
43cd72b9 | 10316 | /* Allocate a fragment and (unfortunately) leak it. */ |
e0001a05 | 10317 | fragS *fragP; |
d77b99c9 | 10318 | bfd_size_type frag_size; |
e0001a05 NC |
10319 | fixS *fixes; |
10320 | frchainS *frchainP; | |
43cd72b9 | 10321 | int i; |
e0001a05 NC |
10322 | char *frag_data; |
10323 | ||
10324 | frag_size = sizeof (fragS) + rec_size; | |
10325 | fragP = (fragS *) xmalloc (frag_size); | |
10326 | ||
10327 | memset (fragP, 0, frag_size); | |
10328 | fragP->fr_address = 0; | |
10329 | fragP->fr_next = NULL; | |
10330 | fragP->fr_fix = rec_size; | |
10331 | fragP->fr_var = 0; | |
10332 | fragP->fr_type = rs_fill; | |
43cd72b9 | 10333 | /* The rest are zeros. */ |
e0001a05 NC |
10334 | |
10335 | frchainP = seginfo->frchainP; | |
10336 | frchainP->frch_root = fragP; | |
10337 | frchainP->frch_last = fragP; | |
10338 | ||
10339 | fixes = (fixS *) xmalloc (sizeof (fixS) * num_recs); | |
10340 | memset (fixes, 0, sizeof (fixS) * num_recs); | |
10341 | ||
10342 | seginfo->fix_root = fixes; | |
10343 | seginfo->fix_tail = &fixes[num_recs - 1]; | |
10344 | cur_block = block; | |
10345 | frag_data = &fragP->fr_literal[0]; | |
10346 | for (i = 0; i < num_recs; i++) | |
10347 | { | |
10348 | fixS *fix = &fixes[i]; | |
10349 | assert (cur_block); | |
10350 | ||
10351 | /* Write the fixup. */ | |
10352 | if (i != num_recs - 1) | |
10353 | fix->fx_next = &fixes[i + 1]; | |
10354 | else | |
10355 | fix->fx_next = NULL; | |
10356 | fix->fx_size = 4; | |
10357 | fix->fx_done = 0; | |
10358 | fix->fx_frag = fragP; | |
43cd72b9 | 10359 | fix->fx_where = i * (8 + 4); |
e0001a05 NC |
10360 | fix->fx_addsy = section_symbol (cur_block->sec); |
10361 | fix->fx_offset = cur_block->offset; | |
10362 | fix->fx_r_type = BFD_RELOC_32; | |
10363 | fix->fx_file = "Internal Assembly"; | |
10364 | fix->fx_line = 0; | |
10365 | ||
10366 | /* Write the length. */ | |
43cd72b9 | 10367 | md_number_to_chars (&frag_data[4 + (8+4) * i], |
e0001a05 | 10368 | cur_block->size, 4); |
43cd72b9 BW |
10369 | md_number_to_chars (&frag_data[8 + (8+4) * i], |
10370 | frag_flags_to_number (&cur_block->flags), | |
10371 | 4); | |
e0001a05 NC |
10372 | cur_block = cur_block->next; |
10373 | } | |
10374 | } | |
10375 | } | |
10376 | } | |
10377 | } | |
10378 | ||
10379 | ||
7fa3d080 BW |
10380 | static segment_info_type * |
10381 | retrieve_segment_info (segT seg) | |
e0001a05 NC |
10382 | { |
10383 | segment_info_type *seginfo; | |
10384 | seginfo = (segment_info_type *) bfd_get_section_userdata (stdoutput, seg); | |
10385 | if (!seginfo) | |
10386 | { | |
10387 | frchainS *frchainP; | |
10388 | ||
10389 | seginfo = (segment_info_type *) xmalloc (sizeof (*seginfo)); | |
7fa3d080 | 10390 | memset ((void *) seginfo, 0, sizeof (*seginfo)); |
e0001a05 NC |
10391 | seginfo->fix_root = NULL; |
10392 | seginfo->fix_tail = NULL; | |
10393 | seginfo->bfd_section = seg; | |
10394 | seginfo->sym = 0; | |
10395 | /* We will not be dealing with these, only our special ones. */ | |
65ec77d2 | 10396 | bfd_set_section_userdata (stdoutput, seg, (void *) seginfo); |
e0001a05 NC |
10397 | |
10398 | frchainP = (frchainS *) xmalloc (sizeof (frchainS)); | |
10399 | frchainP->frch_root = NULL; | |
10400 | frchainP->frch_last = NULL; | |
10401 | frchainP->frch_next = NULL; | |
e0001a05 NC |
10402 | frchainP->frch_subseg = 0; |
10403 | frchainP->fix_root = NULL; | |
10404 | frchainP->fix_tail = NULL; | |
10405 | /* Do not init the objstack. */ | |
10406 | /* obstack_begin (&frchainP->frch_obstack, chunksize); */ | |
10407 | /* frchainP->frch_frag_now = fragP; */ | |
10408 | frchainP->frch_frag_now = NULL; | |
10409 | ||
10410 | seginfo->frchainP = frchainP; | |
10411 | } | |
10412 | ||
10413 | return seginfo; | |
10414 | } | |
10415 | ||
10416 | ||
7fa3d080 BW |
10417 | static segT |
10418 | retrieve_xtensa_section (char *sec_name) | |
e0001a05 NC |
10419 | { |
10420 | bfd *abfd = stdoutput; | |
10421 | flagword flags, out_flags, link_once_flags; | |
10422 | segT s; | |
10423 | ||
10424 | flags = bfd_get_section_flags (abfd, now_seg); | |
10425 | link_once_flags = (flags & SEC_LINK_ONCE); | |
10426 | if (link_once_flags) | |
10427 | link_once_flags |= (flags & SEC_LINK_DUPLICATES); | |
10428 | out_flags = (SEC_RELOC | SEC_HAS_CONTENTS | SEC_READONLY | link_once_flags); | |
10429 | ||
10430 | s = bfd_make_section_old_way (abfd, sec_name); | |
10431 | if (s == NULL) | |
10432 | as_bad (_("could not create section %s"), sec_name); | |
10433 | if (!bfd_set_section_flags (abfd, s, out_flags)) | |
10434 | as_bad (_("invalid flag combination on section %s"), sec_name); | |
10435 | ||
10436 | return s; | |
10437 | } | |
10438 | ||
10439 | ||
7fa3d080 BW |
10440 | static bfd_boolean |
10441 | section_has_property (segT sec, frag_predicate property_function) | |
e0001a05 NC |
10442 | { |
10443 | segment_info_type *seginfo = seg_info (sec); | |
10444 | fragS *fragP; | |
10445 | ||
10446 | if (seginfo && seginfo->frchainP) | |
10447 | { | |
10448 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10449 | { | |
10450 | if (property_function (fragP) | |
10451 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10452 | return TRUE; | |
10453 | } | |
10454 | } | |
10455 | return FALSE; | |
10456 | } | |
10457 | ||
10458 | ||
7fa3d080 BW |
10459 | static bfd_boolean |
10460 | section_has_xproperty (segT sec, frag_flags_fn property_function) | |
43cd72b9 BW |
10461 | { |
10462 | segment_info_type *seginfo = seg_info (sec); | |
10463 | fragS *fragP; | |
10464 | ||
10465 | if (seginfo && seginfo->frchainP) | |
10466 | { | |
10467 | for (fragP = seginfo->frchainP->frch_root; fragP; fragP = fragP->fr_next) | |
10468 | { | |
10469 | frag_flags prop_flags; | |
10470 | property_function (fragP, &prop_flags); | |
10471 | if (!xtensa_frag_flags_is_empty (&prop_flags)) | |
10472 | return TRUE; | |
10473 | } | |
10474 | } | |
10475 | return FALSE; | |
10476 | } | |
10477 | ||
10478 | ||
e0001a05 NC |
10479 | /* Two types of block sections exist right now: literal and insns. */ |
10480 | ||
7fa3d080 BW |
10481 | static void |
10482 | add_xt_block_frags (segT sec, | |
10483 | segT xt_block_sec, | |
10484 | xtensa_block_info **xt_block, | |
10485 | frag_predicate property_function, | |
10486 | frag_predicate end_property_function) | |
e0001a05 NC |
10487 | { |
10488 | segment_info_type *seg_info; | |
10489 | segment_info_type *xt_seg_info; | |
10490 | bfd_vma seg_offset; | |
10491 | fragS *fragP; | |
10492 | ||
10493 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10494 | seg_info = retrieve_segment_info (sec); | |
10495 | ||
10496 | /* Build it if needed. */ | |
10497 | while (*xt_block != NULL) | |
10498 | xt_block = &(*xt_block)->next; | |
10499 | /* We are either at NULL at the beginning or at the end. */ | |
10500 | ||
10501 | /* Walk through the frags. */ | |
10502 | seg_offset = 0; | |
10503 | ||
10504 | if (seg_info->frchainP) | |
10505 | { | |
10506 | for (fragP = seg_info->frchainP->frch_root; | |
10507 | fragP; | |
10508 | fragP = fragP->fr_next) | |
10509 | { | |
10510 | if (property_function (fragP) | |
10511 | && (fragP->fr_type != rs_fill || fragP->fr_fix != 0)) | |
10512 | { | |
10513 | if (*xt_block != NULL) | |
10514 | { | |
10515 | if ((*xt_block)->offset + (*xt_block)->size | |
10516 | == fragP->fr_address) | |
10517 | (*xt_block)->size += fragP->fr_fix; | |
10518 | else | |
10519 | xt_block = &((*xt_block)->next); | |
10520 | } | |
10521 | if (*xt_block == NULL) | |
10522 | { | |
43cd72b9 BW |
10523 | xtensa_block_info *new_block = (xtensa_block_info *) |
10524 | xmalloc (sizeof (xtensa_block_info)); | |
10525 | new_block->sec = sec; | |
10526 | new_block->offset = fragP->fr_address; | |
10527 | new_block->size = fragP->fr_fix; | |
10528 | new_block->next = NULL; | |
10529 | xtensa_frag_flags_init (&new_block->flags); | |
10530 | *xt_block = new_block; | |
10531 | } | |
10532 | if (end_property_function | |
10533 | && end_property_function (fragP)) | |
10534 | { | |
10535 | xt_block = &((*xt_block)->next); | |
10536 | } | |
10537 | } | |
10538 | } | |
10539 | } | |
10540 | } | |
10541 | ||
10542 | ||
10543 | /* Break the encapsulation of add_xt_prop_frags here. */ | |
10544 | ||
7fa3d080 BW |
10545 | static bfd_boolean |
10546 | xtensa_frag_flags_is_empty (const frag_flags *prop_flags) | |
43cd72b9 BW |
10547 | { |
10548 | if (prop_flags->is_literal | |
10549 | || prop_flags->is_insn | |
10550 | || prop_flags->is_data | |
10551 | || prop_flags->is_unreachable) | |
10552 | return FALSE; | |
10553 | return TRUE; | |
10554 | } | |
10555 | ||
10556 | ||
7fa3d080 BW |
10557 | static void |
10558 | xtensa_frag_flags_init (frag_flags *prop_flags) | |
43cd72b9 BW |
10559 | { |
10560 | memset (prop_flags, 0, sizeof (frag_flags)); | |
10561 | } | |
10562 | ||
10563 | ||
7fa3d080 BW |
10564 | static void |
10565 | get_frag_property_flags (const fragS *fragP, frag_flags *prop_flags) | |
43cd72b9 BW |
10566 | { |
10567 | xtensa_frag_flags_init (prop_flags); | |
10568 | if (fragP->tc_frag_data.is_literal) | |
10569 | prop_flags->is_literal = TRUE; | |
10570 | if (fragP->tc_frag_data.is_unreachable) | |
7fa3d080 | 10571 | prop_flags->is_unreachable = TRUE; |
43cd72b9 BW |
10572 | else if (fragP->tc_frag_data.is_insn) |
10573 | { | |
10574 | prop_flags->is_insn = TRUE; | |
10575 | if (fragP->tc_frag_data.is_loop_target) | |
10576 | prop_flags->insn.is_loop_target = TRUE; | |
10577 | if (fragP->tc_frag_data.is_branch_target) | |
10578 | prop_flags->insn.is_branch_target = TRUE; | |
10579 | if (fragP->tc_frag_data.is_specific_opcode | |
10580 | || fragP->tc_frag_data.is_no_transform) | |
10581 | prop_flags->insn.is_no_transform = TRUE; | |
10582 | if (fragP->tc_frag_data.is_no_density) | |
10583 | prop_flags->insn.is_no_density = TRUE; | |
10584 | if (fragP->tc_frag_data.use_absolute_literals) | |
10585 | prop_flags->insn.is_abslit = TRUE; | |
10586 | } | |
10587 | if (fragP->tc_frag_data.is_align) | |
10588 | { | |
10589 | prop_flags->is_align = TRUE; | |
10590 | prop_flags->alignment = fragP->tc_frag_data.alignment; | |
10591 | if (xtensa_frag_flags_is_empty (prop_flags)) | |
10592 | prop_flags->is_data = TRUE; | |
10593 | } | |
10594 | } | |
10595 | ||
10596 | ||
7fa3d080 BW |
10597 | static bfd_vma |
10598 | frag_flags_to_number (const frag_flags *prop_flags) | |
43cd72b9 BW |
10599 | { |
10600 | bfd_vma num = 0; | |
10601 | if (prop_flags->is_literal) | |
10602 | num |= XTENSA_PROP_LITERAL; | |
10603 | if (prop_flags->is_insn) | |
10604 | num |= XTENSA_PROP_INSN; | |
10605 | if (prop_flags->is_data) | |
10606 | num |= XTENSA_PROP_DATA; | |
10607 | if (prop_flags->is_unreachable) | |
10608 | num |= XTENSA_PROP_UNREACHABLE; | |
10609 | if (prop_flags->insn.is_loop_target) | |
10610 | num |= XTENSA_PROP_INSN_LOOP_TARGET; | |
10611 | if (prop_flags->insn.is_branch_target) | |
10612 | { | |
10613 | num |= XTENSA_PROP_INSN_BRANCH_TARGET; | |
10614 | num = SET_XTENSA_PROP_BT_ALIGN (num, prop_flags->insn.bt_align_priority); | |
10615 | } | |
10616 | ||
10617 | if (prop_flags->insn.is_no_density) | |
10618 | num |= XTENSA_PROP_INSN_NO_DENSITY; | |
10619 | if (prop_flags->insn.is_no_transform) | |
10620 | num |= XTENSA_PROP_INSN_NO_TRANSFORM; | |
10621 | if (prop_flags->insn.is_no_reorder) | |
10622 | num |= XTENSA_PROP_INSN_NO_REORDER; | |
10623 | if (prop_flags->insn.is_abslit) | |
10624 | num |= XTENSA_PROP_INSN_ABSLIT; | |
10625 | ||
10626 | if (prop_flags->is_align) | |
10627 | { | |
10628 | num |= XTENSA_PROP_ALIGN; | |
10629 | num = SET_XTENSA_PROP_ALIGNMENT (num, prop_flags->alignment); | |
10630 | } | |
10631 | ||
10632 | return num; | |
10633 | } | |
10634 | ||
10635 | ||
10636 | static bfd_boolean | |
7fa3d080 BW |
10637 | xtensa_frag_flags_combinable (const frag_flags *prop_flags_1, |
10638 | const frag_flags *prop_flags_2) | |
43cd72b9 BW |
10639 | { |
10640 | /* Cannot combine with an end marker. */ | |
10641 | ||
10642 | if (prop_flags_1->is_literal != prop_flags_2->is_literal) | |
10643 | return FALSE; | |
10644 | if (prop_flags_1->is_insn != prop_flags_2->is_insn) | |
10645 | return FALSE; | |
10646 | if (prop_flags_1->is_data != prop_flags_2->is_data) | |
10647 | return FALSE; | |
10648 | ||
10649 | if (prop_flags_1->is_insn) | |
10650 | { | |
10651 | /* Properties of the beginning of the frag. */ | |
10652 | if (prop_flags_2->insn.is_loop_target) | |
10653 | return FALSE; | |
10654 | if (prop_flags_2->insn.is_branch_target) | |
10655 | return FALSE; | |
10656 | if (prop_flags_1->insn.is_no_density != | |
10657 | prop_flags_2->insn.is_no_density) | |
10658 | return FALSE; | |
10659 | if (prop_flags_1->insn.is_no_transform != | |
10660 | prop_flags_2->insn.is_no_transform) | |
10661 | return FALSE; | |
10662 | if (prop_flags_1->insn.is_no_reorder != | |
10663 | prop_flags_2->insn.is_no_reorder) | |
10664 | return FALSE; | |
10665 | if (prop_flags_1->insn.is_abslit != | |
10666 | prop_flags_2->insn.is_abslit) | |
10667 | return FALSE; | |
10668 | } | |
10669 | ||
10670 | if (prop_flags_1->is_align) | |
10671 | return FALSE; | |
10672 | ||
10673 | return TRUE; | |
10674 | } | |
10675 | ||
10676 | ||
7fa3d080 BW |
10677 | static bfd_vma |
10678 | xt_block_aligned_size (const xtensa_block_info *xt_block) | |
43cd72b9 BW |
10679 | { |
10680 | bfd_vma end_addr; | |
d77b99c9 | 10681 | unsigned align_bits; |
43cd72b9 BW |
10682 | |
10683 | if (!xt_block->flags.is_align) | |
10684 | return xt_block->size; | |
10685 | ||
10686 | end_addr = xt_block->offset + xt_block->size; | |
10687 | align_bits = xt_block->flags.alignment; | |
10688 | end_addr = ((end_addr + ((1 << align_bits) -1)) >> align_bits) << align_bits; | |
10689 | return end_addr - xt_block->offset; | |
10690 | } | |
10691 | ||
10692 | ||
10693 | static bfd_boolean | |
7fa3d080 BW |
10694 | xtensa_xt_block_combine (xtensa_block_info *xt_block, |
10695 | const xtensa_block_info *xt_block_2) | |
43cd72b9 BW |
10696 | { |
10697 | if (xt_block->sec != xt_block_2->sec) | |
10698 | return FALSE; | |
10699 | if (xt_block->offset + xt_block_aligned_size (xt_block) | |
10700 | != xt_block_2->offset) | |
10701 | return FALSE; | |
10702 | ||
10703 | if (xt_block_2->size == 0 | |
10704 | && (!xt_block_2->flags.is_unreachable | |
10705 | || xt_block->flags.is_unreachable)) | |
10706 | { | |
10707 | if (xt_block_2->flags.is_align | |
10708 | && xt_block->flags.is_align) | |
10709 | { | |
10710 | /* Nothing needed. */ | |
10711 | if (xt_block->flags.alignment >= xt_block_2->flags.alignment) | |
10712 | return TRUE; | |
10713 | } | |
10714 | else | |
10715 | { | |
10716 | if (xt_block_2->flags.is_align) | |
10717 | { | |
10718 | /* Push alignment to previous entry. */ | |
10719 | xt_block->flags.is_align = xt_block_2->flags.is_align; | |
10720 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10721 | } | |
10722 | return TRUE; | |
10723 | } | |
10724 | } | |
10725 | if (!xtensa_frag_flags_combinable (&xt_block->flags, | |
10726 | &xt_block_2->flags)) | |
10727 | return FALSE; | |
10728 | ||
10729 | xt_block->size += xt_block_2->size; | |
10730 | ||
10731 | if (xt_block_2->flags.is_align) | |
10732 | { | |
10733 | xt_block->flags.is_align = TRUE; | |
10734 | xt_block->flags.alignment = xt_block_2->flags.alignment; | |
10735 | } | |
10736 | ||
10737 | return TRUE; | |
10738 | } | |
10739 | ||
10740 | ||
7fa3d080 BW |
10741 | static void |
10742 | add_xt_prop_frags (segT sec, | |
10743 | segT xt_block_sec, | |
10744 | xtensa_block_info **xt_block, | |
10745 | frag_flags_fn property_function) | |
43cd72b9 BW |
10746 | { |
10747 | segment_info_type *seg_info; | |
10748 | segment_info_type *xt_seg_info; | |
10749 | bfd_vma seg_offset; | |
10750 | fragS *fragP; | |
10751 | ||
10752 | xt_seg_info = retrieve_segment_info (xt_block_sec); | |
10753 | seg_info = retrieve_segment_info (sec); | |
10754 | /* Build it if needed. */ | |
10755 | while (*xt_block != NULL) | |
10756 | { | |
10757 | xt_block = &(*xt_block)->next; | |
10758 | } | |
10759 | /* We are either at NULL at the beginning or at the end. */ | |
10760 | ||
10761 | /* Walk through the frags. */ | |
10762 | seg_offset = 0; | |
10763 | ||
10764 | if (seg_info->frchainP) | |
10765 | { | |
10766 | for (fragP = seg_info->frchainP->frch_root; fragP; | |
10767 | fragP = fragP->fr_next) | |
10768 | { | |
10769 | xtensa_block_info tmp_block; | |
10770 | tmp_block.sec = sec; | |
10771 | tmp_block.offset = fragP->fr_address; | |
10772 | tmp_block.size = fragP->fr_fix; | |
10773 | tmp_block.next = NULL; | |
10774 | property_function (fragP, &tmp_block.flags); | |
10775 | ||
10776 | if (!xtensa_frag_flags_is_empty (&tmp_block.flags)) | |
10777 | /* && fragP->fr_fix != 0) */ | |
10778 | { | |
10779 | if ((*xt_block) == NULL | |
10780 | || !xtensa_xt_block_combine (*xt_block, &tmp_block)) | |
10781 | { | |
10782 | xtensa_block_info *new_block; | |
10783 | if ((*xt_block) != NULL) | |
10784 | xt_block = &(*xt_block)->next; | |
10785 | new_block = (xtensa_block_info *) | |
10786 | xmalloc (sizeof (xtensa_block_info)); | |
10787 | *new_block = tmp_block; | |
10788 | *xt_block = new_block; | |
10789 | } | |
10790 | } | |
10791 | } | |
10792 | } | |
10793 | } | |
10794 | ||
10795 | \f | |
10796 | /* op_placement_info_table */ | |
10797 | ||
10798 | /* op_placement_info makes it easier to determine which | |
10799 | ops can go in which slots. */ | |
10800 | ||
10801 | static void | |
7fa3d080 | 10802 | init_op_placement_info_table (void) |
43cd72b9 BW |
10803 | { |
10804 | xtensa_isa isa = xtensa_default_isa; | |
10805 | xtensa_insnbuf ibuf = xtensa_insnbuf_alloc (isa); | |
10806 | xtensa_opcode opcode; | |
10807 | xtensa_format fmt; | |
10808 | int slot; | |
10809 | int num_opcodes = xtensa_isa_num_opcodes (isa); | |
10810 | ||
10811 | op_placement_table = (op_placement_info_table) | |
10812 | xmalloc (sizeof (op_placement_info) * num_opcodes); | |
10813 | assert (xtensa_isa_num_formats (isa) < MAX_FORMATS); | |
10814 | ||
10815 | for (opcode = 0; opcode < num_opcodes; opcode++) | |
10816 | { | |
10817 | op_placement_info *opi = &op_placement_table[opcode]; | |
10818 | /* FIXME: Make tinsn allocation dynamic. */ | |
10819 | if (xtensa_opcode_num_operands (isa, opcode) >= MAX_INSN_ARGS) | |
10820 | as_fatal (_("too many operands in instruction")); | |
43cd72b9 BW |
10821 | opi->narrowest = XTENSA_UNDEFINED; |
10822 | opi->narrowest_size = 0x7F; | |
b2d179be | 10823 | opi->narrowest_slot = 0; |
43cd72b9 BW |
10824 | opi->formats = 0; |
10825 | opi->num_formats = 0; | |
10826 | opi->issuef = 0; | |
10827 | for (fmt = 0; fmt < xtensa_isa_num_formats (isa); fmt++) | |
10828 | { | |
10829 | opi->slots[fmt] = 0; | |
10830 | for (slot = 0; slot < xtensa_format_num_slots (isa, fmt); slot++) | |
10831 | { | |
10832 | if (xtensa_opcode_encode (isa, fmt, slot, ibuf, opcode) == 0) | |
10833 | { | |
10834 | int fmt_length = xtensa_format_length (isa, fmt); | |
10835 | opi->issuef++; | |
10836 | set_bit (fmt, opi->formats); | |
10837 | set_bit (slot, opi->slots[fmt]); | |
a02728c8 BW |
10838 | if (fmt_length < opi->narrowest_size |
10839 | || (fmt_length == opi->narrowest_size | |
10840 | && (xtensa_format_num_slots (isa, fmt) | |
10841 | < xtensa_format_num_slots (isa, | |
10842 | opi->narrowest)))) | |
43cd72b9 BW |
10843 | { |
10844 | opi->narrowest = fmt; | |
10845 | opi->narrowest_size = fmt_length; | |
b2d179be | 10846 | opi->narrowest_slot = slot; |
43cd72b9 | 10847 | } |
e0001a05 NC |
10848 | } |
10849 | } | |
43cd72b9 BW |
10850 | if (opi->formats) |
10851 | opi->num_formats++; | |
e0001a05 NC |
10852 | } |
10853 | } | |
43cd72b9 BW |
10854 | xtensa_insnbuf_free (isa, ibuf); |
10855 | } | |
10856 | ||
10857 | ||
10858 | bfd_boolean | |
7fa3d080 | 10859 | opcode_fits_format_slot (xtensa_opcode opcode, xtensa_format fmt, int slot) |
43cd72b9 BW |
10860 | { |
10861 | return bit_is_set (slot, op_placement_table[opcode].slots[fmt]); | |
10862 | } | |
10863 | ||
10864 | ||
10865 | /* If the opcode is available in a single slot format, return its size. */ | |
10866 | ||
7fa3d080 BW |
10867 | static int |
10868 | xg_get_single_size (xtensa_opcode opcode) | |
43cd72b9 | 10869 | { |
b2d179be | 10870 | return op_placement_table[opcode].narrowest_size; |
43cd72b9 BW |
10871 | } |
10872 | ||
10873 | ||
7fa3d080 BW |
10874 | static xtensa_format |
10875 | xg_get_single_format (xtensa_opcode opcode) | |
43cd72b9 | 10876 | { |
b2d179be BW |
10877 | return op_placement_table[opcode].narrowest; |
10878 | } | |
10879 | ||
10880 | ||
10881 | static int | |
10882 | xg_get_single_slot (xtensa_opcode opcode) | |
10883 | { | |
10884 | return op_placement_table[opcode].narrowest_slot; | |
e0001a05 NC |
10885 | } |
10886 | ||
10887 | \f | |
10888 | /* Instruction Stack Functions (from "xtensa-istack.h"). */ | |
10889 | ||
10890 | void | |
7fa3d080 | 10891 | istack_init (IStack *stack) |
e0001a05 NC |
10892 | { |
10893 | memset (stack, 0, sizeof (IStack)); | |
10894 | stack->ninsn = 0; | |
10895 | } | |
10896 | ||
10897 | ||
10898 | bfd_boolean | |
7fa3d080 | 10899 | istack_empty (IStack *stack) |
e0001a05 NC |
10900 | { |
10901 | return (stack->ninsn == 0); | |
10902 | } | |
10903 | ||
10904 | ||
10905 | bfd_boolean | |
7fa3d080 | 10906 | istack_full (IStack *stack) |
e0001a05 NC |
10907 | { |
10908 | return (stack->ninsn == MAX_ISTACK); | |
10909 | } | |
10910 | ||
10911 | ||
10912 | /* Return a pointer to the top IStack entry. | |
43cd72b9 | 10913 | It is an error to call this if istack_empty () is TRUE. */ |
e0001a05 NC |
10914 | |
10915 | TInsn * | |
7fa3d080 | 10916 | istack_top (IStack *stack) |
e0001a05 NC |
10917 | { |
10918 | int rec = stack->ninsn - 1; | |
10919 | assert (!istack_empty (stack)); | |
10920 | return &stack->insn[rec]; | |
10921 | } | |
10922 | ||
10923 | ||
10924 | /* Add a new TInsn to an IStack. | |
43cd72b9 | 10925 | It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10926 | |
10927 | void | |
7fa3d080 | 10928 | istack_push (IStack *stack, TInsn *insn) |
e0001a05 NC |
10929 | { |
10930 | int rec = stack->ninsn; | |
10931 | assert (!istack_full (stack)); | |
43cd72b9 | 10932 | stack->insn[rec] = *insn; |
e0001a05 NC |
10933 | stack->ninsn++; |
10934 | } | |
10935 | ||
10936 | ||
10937 | /* Clear space for the next TInsn on the IStack and return a pointer | |
43cd72b9 | 10938 | to it. It is an error to call this if istack_full () is TRUE. */ |
e0001a05 NC |
10939 | |
10940 | TInsn * | |
7fa3d080 | 10941 | istack_push_space (IStack *stack) |
e0001a05 NC |
10942 | { |
10943 | int rec = stack->ninsn; | |
10944 | TInsn *insn; | |
10945 | assert (!istack_full (stack)); | |
10946 | insn = &stack->insn[rec]; | |
10947 | memset (insn, 0, sizeof (TInsn)); | |
10948 | stack->ninsn++; | |
10949 | return insn; | |
10950 | } | |
10951 | ||
10952 | ||
10953 | /* Remove the last pushed instruction. It is an error to call this if | |
43cd72b9 | 10954 | istack_empty () returns TRUE. */ |
e0001a05 NC |
10955 | |
10956 | void | |
7fa3d080 | 10957 | istack_pop (IStack *stack) |
e0001a05 NC |
10958 | { |
10959 | int rec = stack->ninsn - 1; | |
10960 | assert (!istack_empty (stack)); | |
10961 | stack->ninsn--; | |
10962 | memset (&stack->insn[rec], 0, sizeof (TInsn)); | |
10963 | } | |
10964 | ||
10965 | \f | |
10966 | /* TInsn functions. */ | |
10967 | ||
10968 | void | |
7fa3d080 | 10969 | tinsn_init (TInsn *dst) |
e0001a05 NC |
10970 | { |
10971 | memset (dst, 0, sizeof (TInsn)); | |
10972 | } | |
10973 | ||
10974 | ||
e0001a05 NC |
10975 | /* Get the ``num''th token of the TInsn. |
10976 | It is illegal to call this if num > insn->ntoks. */ | |
10977 | ||
10978 | expressionS * | |
7fa3d080 | 10979 | tinsn_get_tok (TInsn *insn, int num) |
e0001a05 NC |
10980 | { |
10981 | assert (num < insn->ntok); | |
10982 | return &insn->tok[num]; | |
10983 | } | |
10984 | ||
10985 | ||
43cd72b9 | 10986 | /* Return TRUE if ANY of the operands in the insn are symbolic. */ |
e0001a05 NC |
10987 | |
10988 | static bfd_boolean | |
7fa3d080 | 10989 | tinsn_has_symbolic_operands (const TInsn *insn) |
e0001a05 NC |
10990 | { |
10991 | int i; | |
10992 | int n = insn->ntok; | |
10993 | ||
10994 | assert (insn->insn_type == ITYPE_INSN); | |
10995 | ||
10996 | for (i = 0; i < n; ++i) | |
10997 | { | |
10998 | switch (insn->tok[i].X_op) | |
10999 | { | |
11000 | case O_register: | |
11001 | case O_constant: | |
11002 | break; | |
11003 | default: | |
11004 | return TRUE; | |
11005 | } | |
11006 | } | |
11007 | return FALSE; | |
11008 | } | |
11009 | ||
11010 | ||
11011 | bfd_boolean | |
7fa3d080 | 11012 | tinsn_has_invalid_symbolic_operands (const TInsn *insn) |
e0001a05 | 11013 | { |
43cd72b9 | 11014 | xtensa_isa isa = xtensa_default_isa; |
e0001a05 NC |
11015 | int i; |
11016 | int n = insn->ntok; | |
11017 | ||
11018 | assert (insn->insn_type == ITYPE_INSN); | |
11019 | ||
11020 | for (i = 0; i < n; ++i) | |
11021 | { | |
11022 | switch (insn->tok[i].X_op) | |
11023 | { | |
11024 | case O_register: | |
11025 | case O_constant: | |
11026 | break; | |
43cd72b9 BW |
11027 | case O_big: |
11028 | case O_illegal: | |
11029 | case O_absent: | |
11030 | /* Errors for these types are caught later. */ | |
11031 | break; | |
11032 | case O_hi16: | |
11033 | case O_lo16: | |
e0001a05 | 11034 | default: |
43cd72b9 BW |
11035 | /* Symbolic immediates are only allowed on the last immediate |
11036 | operand. At this time, CONST16 is the only opcode where we | |
e7da6241 | 11037 | support non-PC-relative relocations. */ |
43cd72b9 BW |
11038 | if (i != get_relaxable_immed (insn->opcode) |
11039 | || (xtensa_operand_is_PCrelative (isa, insn->opcode, i) != 1 | |
11040 | && insn->opcode != xtensa_const16_opcode)) | |
11041 | { | |
431ad2d0 | 11042 | as_bad (_("invalid symbolic operand")); |
43cd72b9 BW |
11043 | return TRUE; |
11044 | } | |
e0001a05 NC |
11045 | } |
11046 | } | |
11047 | return FALSE; | |
11048 | } | |
11049 | ||
11050 | ||
11051 | /* For assembly code with complex expressions (e.g. subtraction), | |
11052 | we have to build them in the literal pool so that | |
11053 | their results are calculated correctly after relaxation. | |
11054 | The relaxation only handles expressions that | |
11055 | boil down to SYMBOL + OFFSET. */ | |
11056 | ||
11057 | static bfd_boolean | |
7fa3d080 | 11058 | tinsn_has_complex_operands (const TInsn *insn) |
e0001a05 NC |
11059 | { |
11060 | int i; | |
11061 | int n = insn->ntok; | |
11062 | assert (insn->insn_type == ITYPE_INSN); | |
11063 | for (i = 0; i < n; ++i) | |
11064 | { | |
11065 | switch (insn->tok[i].X_op) | |
11066 | { | |
11067 | case O_register: | |
11068 | case O_constant: | |
11069 | case O_symbol: | |
43cd72b9 BW |
11070 | case O_lo16: |
11071 | case O_hi16: | |
e0001a05 NC |
11072 | break; |
11073 | default: | |
11074 | return TRUE; | |
11075 | } | |
11076 | } | |
11077 | return FALSE; | |
11078 | } | |
11079 | ||
11080 | ||
b2d179be BW |
11081 | /* Encode a TInsn opcode and its constant operands into slotbuf. |
11082 | Return TRUE if there is a symbol in the immediate field. This | |
11083 | function assumes that: | |
11084 | 1) The number of operands are correct. | |
11085 | 2) The insn_type is ITYPE_INSN. | |
11086 | 3) The opcode can be encoded in the specified format and slot. | |
11087 | 4) Operands are either O_constant or O_symbol, and all constants fit. */ | |
43cd72b9 BW |
11088 | |
11089 | static bfd_boolean | |
7fa3d080 BW |
11090 | tinsn_to_slotbuf (xtensa_format fmt, |
11091 | int slot, | |
11092 | TInsn *tinsn, | |
11093 | xtensa_insnbuf slotbuf) | |
43cd72b9 BW |
11094 | { |
11095 | xtensa_isa isa = xtensa_default_isa; | |
11096 | xtensa_opcode opcode = tinsn->opcode; | |
11097 | bfd_boolean has_fixup = FALSE; | |
11098 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11099 | int i; | |
11100 | ||
43cd72b9 BW |
11101 | assert (tinsn->insn_type == ITYPE_INSN); |
11102 | if (noperands != tinsn->ntok) | |
11103 | as_fatal (_("operand number mismatch")); | |
11104 | ||
11105 | if (xtensa_opcode_encode (isa, fmt, slot, slotbuf, opcode)) | |
11106 | { | |
11107 | as_bad (_("cannot encode opcode \"%s\" in the given format \"%s\""), | |
11108 | xtensa_opcode_name (isa, opcode), xtensa_format_name (isa, fmt)); | |
11109 | return FALSE; | |
11110 | } | |
11111 | ||
11112 | for (i = 0; i < noperands; i++) | |
11113 | { | |
11114 | expressionS *expr = &tinsn->tok[i]; | |
d77b99c9 BW |
11115 | int rc; |
11116 | unsigned line; | |
43cd72b9 BW |
11117 | char *file_name; |
11118 | uint32 opnd_value; | |
11119 | ||
11120 | switch (expr->X_op) | |
11121 | { | |
11122 | case O_register: | |
11123 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11124 | break; | |
11125 | /* The register number has already been checked in | |
11126 | expression_maybe_register, so we don't need to check here. */ | |
11127 | opnd_value = expr->X_add_number; | |
11128 | (void) xtensa_operand_encode (isa, opcode, i, &opnd_value); | |
11129 | rc = xtensa_operand_set_field (isa, opcode, i, fmt, slot, slotbuf, | |
11130 | opnd_value); | |
11131 | if (rc != 0) | |
11132 | as_warn (_("xtensa-isa failure: %s"), xtensa_isa_error_msg (isa)); | |
11133 | break; | |
11134 | ||
11135 | case O_constant: | |
11136 | if (xtensa_operand_is_visible (isa, opcode, i) == 0) | |
11137 | break; | |
11138 | as_where (&file_name, &line); | |
11139 | /* It is a constant and we called this function | |
11140 | then we have to try to fit it. */ | |
11141 | xtensa_insnbuf_set_operand (slotbuf, fmt, slot, opcode, i, | |
e0001a05 NC |
11142 | expr->X_add_number, file_name, line); |
11143 | break; | |
11144 | ||
e0001a05 NC |
11145 | default: |
11146 | has_fixup = TRUE; | |
11147 | break; | |
11148 | } | |
11149 | } | |
43cd72b9 | 11150 | |
e0001a05 NC |
11151 | return has_fixup; |
11152 | } | |
11153 | ||
11154 | ||
b2d179be BW |
11155 | /* Encode a single TInsn into an insnbuf. If the opcode can only be encoded |
11156 | into a multi-slot instruction, fill the other slots with NOPs. | |
11157 | Return TRUE if there is a symbol in the immediate field. See also the | |
11158 | assumptions listed for tinsn_to_slotbuf. */ | |
11159 | ||
11160 | static bfd_boolean | |
11161 | tinsn_to_insnbuf (TInsn *tinsn, xtensa_insnbuf insnbuf) | |
11162 | { | |
11163 | static xtensa_insnbuf slotbuf = 0; | |
11164 | static vliw_insn vinsn; | |
11165 | xtensa_isa isa = xtensa_default_isa; | |
11166 | bfd_boolean has_fixup = FALSE; | |
11167 | int i; | |
11168 | ||
11169 | if (!slotbuf) | |
11170 | { | |
11171 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11172 | xg_init_vinsn (&vinsn); | |
11173 | } | |
11174 | ||
11175 | xg_clear_vinsn (&vinsn); | |
11176 | ||
11177 | bundle_tinsn (tinsn, &vinsn); | |
11178 | ||
11179 | xtensa_format_encode (isa, vinsn.format, insnbuf); | |
11180 | ||
11181 | for (i = 0; i < vinsn.num_slots; i++) | |
11182 | { | |
11183 | /* Only one slot may have a fix-up because the rest contains NOPs. */ | |
11184 | has_fixup |= | |
11185 | tinsn_to_slotbuf (vinsn.format, i, &vinsn.slots[i], vinsn.slotbuf[i]); | |
11186 | xtensa_format_set_slot (isa, vinsn.format, i, insnbuf, vinsn.slotbuf[i]); | |
11187 | } | |
11188 | ||
11189 | return has_fixup; | |
11190 | } | |
11191 | ||
11192 | ||
43cd72b9 | 11193 | /* Check the instruction arguments. Return TRUE on failure. */ |
e0001a05 | 11194 | |
7fa3d080 BW |
11195 | static bfd_boolean |
11196 | tinsn_check_arguments (const TInsn *insn) | |
e0001a05 NC |
11197 | { |
11198 | xtensa_isa isa = xtensa_default_isa; | |
11199 | xtensa_opcode opcode = insn->opcode; | |
11200 | ||
11201 | if (opcode == XTENSA_UNDEFINED) | |
11202 | { | |
11203 | as_bad (_("invalid opcode")); | |
11204 | return TRUE; | |
11205 | } | |
11206 | ||
43cd72b9 | 11207 | if (xtensa_opcode_num_operands (isa, opcode) > insn->ntok) |
e0001a05 NC |
11208 | { |
11209 | as_bad (_("too few operands")); | |
11210 | return TRUE; | |
11211 | } | |
11212 | ||
43cd72b9 | 11213 | if (xtensa_opcode_num_operands (isa, opcode) < insn->ntok) |
e0001a05 NC |
11214 | { |
11215 | as_bad (_("too many operands")); | |
11216 | return TRUE; | |
11217 | } | |
11218 | return FALSE; | |
11219 | } | |
11220 | ||
11221 | ||
11222 | /* Load an instruction from its encoded form. */ | |
11223 | ||
11224 | static void | |
7fa3d080 | 11225 | tinsn_from_chars (TInsn *tinsn, char *f, int slot) |
e0001a05 | 11226 | { |
43cd72b9 | 11227 | vliw_insn vinsn; |
e0001a05 | 11228 | |
43cd72b9 BW |
11229 | xg_init_vinsn (&vinsn); |
11230 | vinsn_from_chars (&vinsn, f); | |
11231 | ||
11232 | *tinsn = vinsn.slots[slot]; | |
11233 | xg_free_vinsn (&vinsn); | |
11234 | } | |
e0001a05 | 11235 | |
43cd72b9 BW |
11236 | |
11237 | static void | |
7fa3d080 BW |
11238 | tinsn_from_insnbuf (TInsn *tinsn, |
11239 | xtensa_insnbuf slotbuf, | |
11240 | xtensa_format fmt, | |
11241 | int slot) | |
43cd72b9 BW |
11242 | { |
11243 | int i; | |
11244 | xtensa_isa isa = xtensa_default_isa; | |
e0001a05 NC |
11245 | |
11246 | /* Find the immed. */ | |
43cd72b9 BW |
11247 | tinsn_init (tinsn); |
11248 | tinsn->insn_type = ITYPE_INSN; | |
11249 | tinsn->is_specific_opcode = FALSE; /* must not be specific */ | |
11250 | tinsn->opcode = xtensa_opcode_decode (isa, fmt, slot, slotbuf); | |
11251 | tinsn->ntok = xtensa_opcode_num_operands (isa, tinsn->opcode); | |
11252 | for (i = 0; i < tinsn->ntok; i++) | |
e0001a05 | 11253 | { |
43cd72b9 BW |
11254 | set_expr_const (&tinsn->tok[i], |
11255 | xtensa_insnbuf_get_operand (slotbuf, fmt, slot, | |
11256 | tinsn->opcode, i)); | |
e0001a05 NC |
11257 | } |
11258 | } | |
11259 | ||
11260 | ||
11261 | /* Read the value of the relaxable immed from the fr_symbol and fr_offset. */ | |
11262 | ||
11263 | static void | |
7fa3d080 | 11264 | tinsn_immed_from_frag (TInsn *tinsn, fragS *fragP, int slot) |
e0001a05 | 11265 | { |
43cd72b9 | 11266 | xtensa_opcode opcode = tinsn->opcode; |
e0001a05 NC |
11267 | int opnum; |
11268 | ||
43cd72b9 | 11269 | if (fragP->tc_frag_data.slot_symbols[slot]) |
e0001a05 NC |
11270 | { |
11271 | opnum = get_relaxable_immed (opcode); | |
43cd72b9 | 11272 | assert (opnum >= 0); |
e7da6241 BW |
11273 | set_expr_symbol_offset (&tinsn->tok[opnum], |
11274 | fragP->tc_frag_data.slot_symbols[slot], | |
11275 | fragP->tc_frag_data.slot_offsets[slot]); | |
e0001a05 NC |
11276 | } |
11277 | } | |
11278 | ||
11279 | ||
11280 | static int | |
7fa3d080 | 11281 | get_num_stack_text_bytes (IStack *istack) |
e0001a05 NC |
11282 | { |
11283 | int i; | |
11284 | int text_bytes = 0; | |
11285 | ||
11286 | for (i = 0; i < istack->ninsn; i++) | |
11287 | { | |
43cd72b9 BW |
11288 | TInsn *tinsn = &istack->insn[i]; |
11289 | if (tinsn->insn_type == ITYPE_INSN) | |
11290 | text_bytes += xg_get_single_size (tinsn->opcode); | |
e0001a05 NC |
11291 | } |
11292 | return text_bytes; | |
11293 | } | |
11294 | ||
11295 | ||
11296 | static int | |
7fa3d080 | 11297 | get_num_stack_literal_bytes (IStack *istack) |
e0001a05 NC |
11298 | { |
11299 | int i; | |
11300 | int lit_bytes = 0; | |
11301 | ||
11302 | for (i = 0; i < istack->ninsn; i++) | |
11303 | { | |
43cd72b9 BW |
11304 | TInsn *tinsn = &istack->insn[i]; |
11305 | if (tinsn->insn_type == ITYPE_LITERAL && tinsn->ntok == 1) | |
e0001a05 NC |
11306 | lit_bytes += 4; |
11307 | } | |
11308 | return lit_bytes; | |
11309 | } | |
11310 | ||
43cd72b9 BW |
11311 | \f |
11312 | /* vliw_insn functions. */ | |
11313 | ||
7fa3d080 BW |
11314 | static void |
11315 | xg_init_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11316 | { |
11317 | int i; | |
11318 | xtensa_isa isa = xtensa_default_isa; | |
11319 | ||
11320 | xg_clear_vinsn (v); | |
11321 | ||
11322 | v->insnbuf = xtensa_insnbuf_alloc (isa); | |
11323 | if (v->insnbuf == NULL) | |
11324 | as_fatal (_("out of memory")); | |
11325 | ||
11326 | for (i = 0; i < MAX_SLOTS; i++) | |
11327 | { | |
43cd72b9 BW |
11328 | v->slotbuf[i] = xtensa_insnbuf_alloc (isa); |
11329 | if (v->slotbuf[i] == NULL) | |
11330 | as_fatal (_("out of memory")); | |
11331 | } | |
11332 | } | |
11333 | ||
11334 | ||
7fa3d080 BW |
11335 | static void |
11336 | xg_clear_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11337 | { |
11338 | int i; | |
65738a7d BW |
11339 | |
11340 | memset (v, 0, offsetof (vliw_insn, insnbuf)); | |
11341 | ||
43cd72b9 BW |
11342 | v->format = XTENSA_UNDEFINED; |
11343 | v->num_slots = 0; | |
11344 | v->inside_bundle = FALSE; | |
11345 | ||
11346 | if (xt_saved_debug_type != DEBUG_NONE) | |
11347 | debug_type = xt_saved_debug_type; | |
11348 | ||
11349 | for (i = 0; i < MAX_SLOTS; i++) | |
65738a7d | 11350 | v->slots[i].opcode = XTENSA_UNDEFINED; |
43cd72b9 BW |
11351 | } |
11352 | ||
11353 | ||
7fa3d080 BW |
11354 | static bfd_boolean |
11355 | vinsn_has_specific_opcodes (vliw_insn *v) | |
43cd72b9 BW |
11356 | { |
11357 | int i; | |
c138bc38 | 11358 | |
43cd72b9 BW |
11359 | for (i = 0; i < v->num_slots; i++) |
11360 | { | |
11361 | if (v->slots[i].is_specific_opcode) | |
11362 | return TRUE; | |
11363 | } | |
11364 | return FALSE; | |
11365 | } | |
11366 | ||
11367 | ||
7fa3d080 BW |
11368 | static void |
11369 | xg_free_vinsn (vliw_insn *v) | |
43cd72b9 BW |
11370 | { |
11371 | int i; | |
11372 | xtensa_insnbuf_free (xtensa_default_isa, v->insnbuf); | |
11373 | for (i = 0; i < MAX_SLOTS; i++) | |
11374 | xtensa_insnbuf_free (xtensa_default_isa, v->slotbuf[i]); | |
11375 | } | |
11376 | ||
11377 | ||
e7da6241 BW |
11378 | /* Encode a vliw_insn into an insnbuf. Return TRUE if there are any symbolic |
11379 | operands. See also the assumptions listed for tinsn_to_slotbuf. */ | |
43cd72b9 BW |
11380 | |
11381 | static bfd_boolean | |
7fa3d080 BW |
11382 | vinsn_to_insnbuf (vliw_insn *vinsn, |
11383 | char *frag_offset, | |
11384 | fragS *fragP, | |
11385 | bfd_boolean record_fixup) | |
43cd72b9 BW |
11386 | { |
11387 | xtensa_isa isa = xtensa_default_isa; | |
11388 | xtensa_format fmt = vinsn->format; | |
11389 | xtensa_insnbuf insnbuf = vinsn->insnbuf; | |
11390 | int slot; | |
11391 | bfd_boolean has_fixup = FALSE; | |
11392 | ||
11393 | xtensa_format_encode (isa, fmt, insnbuf); | |
11394 | ||
11395 | for (slot = 0; slot < vinsn->num_slots; slot++) | |
11396 | { | |
11397 | TInsn *tinsn = &vinsn->slots[slot]; | |
11398 | bfd_boolean tinsn_has_fixup = | |
11399 | tinsn_to_slotbuf (vinsn->format, slot, tinsn, | |
11400 | vinsn->slotbuf[slot]); | |
11401 | ||
11402 | xtensa_format_set_slot (isa, fmt, slot, | |
11403 | insnbuf, vinsn->slotbuf[slot]); | |
e7da6241 | 11404 | if (tinsn_has_fixup) |
43cd72b9 BW |
11405 | { |
11406 | int i; | |
11407 | xtensa_opcode opcode = tinsn->opcode; | |
11408 | int noperands = xtensa_opcode_num_operands (isa, opcode); | |
11409 | has_fixup = TRUE; | |
11410 | ||
11411 | for (i = 0; i < noperands; i++) | |
11412 | { | |
11413 | expressionS* expr = &tinsn->tok[i]; | |
11414 | switch (expr->X_op) | |
11415 | { | |
11416 | case O_symbol: | |
11417 | case O_lo16: | |
11418 | case O_hi16: | |
11419 | if (get_relaxable_immed (opcode) == i) | |
11420 | { | |
e7da6241 BW |
11421 | /* Add a fix record for the instruction, except if this |
11422 | function is being called prior to relaxation, i.e., | |
11423 | if record_fixup is false, and the instruction might | |
11424 | be relaxed later. */ | |
11425 | if (record_fixup | |
11426 | || tinsn->is_specific_opcode | |
11427 | || !xg_is_relaxable_insn (tinsn, 0)) | |
43cd72b9 | 11428 | { |
e7da6241 BW |
11429 | xg_add_opcode_fix (tinsn, i, fmt, slot, expr, fragP, |
11430 | frag_offset - fragP->fr_literal); | |
43cd72b9 BW |
11431 | } |
11432 | else | |
11433 | { | |
e7da6241 BW |
11434 | if (expr->X_op != O_symbol) |
11435 | as_bad (_("invalid operand")); | |
43cd72b9 BW |
11436 | tinsn->symbol = expr->X_add_symbol; |
11437 | tinsn->offset = expr->X_add_number; | |
11438 | } | |
11439 | } | |
11440 | else | |
e7da6241 | 11441 | as_bad (_("symbolic operand not allowed")); |
43cd72b9 BW |
11442 | break; |
11443 | ||
11444 | case O_constant: | |
11445 | case O_register: | |
11446 | break; | |
11447 | ||
43cd72b9 | 11448 | default: |
e7da6241 | 11449 | as_bad (_("expression too complex")); |
43cd72b9 BW |
11450 | break; |
11451 | } | |
11452 | } | |
11453 | } | |
11454 | } | |
11455 | ||
11456 | return has_fixup; | |
11457 | } | |
11458 | ||
11459 | ||
11460 | static void | |
7fa3d080 | 11461 | vinsn_from_chars (vliw_insn *vinsn, char *f) |
43cd72b9 BW |
11462 | { |
11463 | static xtensa_insnbuf insnbuf = NULL; | |
11464 | static xtensa_insnbuf slotbuf = NULL; | |
11465 | int i; | |
11466 | xtensa_format fmt; | |
11467 | xtensa_isa isa = xtensa_default_isa; | |
11468 | ||
11469 | if (!insnbuf) | |
11470 | { | |
11471 | insnbuf = xtensa_insnbuf_alloc (isa); | |
11472 | slotbuf = xtensa_insnbuf_alloc (isa); | |
11473 | } | |
11474 | ||
d77b99c9 | 11475 | xtensa_insnbuf_from_chars (isa, insnbuf, (unsigned char *) f, 0); |
43cd72b9 BW |
11476 | fmt = xtensa_format_decode (isa, insnbuf); |
11477 | if (fmt == XTENSA_UNDEFINED) | |
11478 | as_fatal (_("cannot decode instruction format")); | |
11479 | vinsn->format = fmt; | |
11480 | vinsn->num_slots = xtensa_format_num_slots (isa, fmt); | |
11481 | ||
11482 | for (i = 0; i < vinsn->num_slots; i++) | |
11483 | { | |
11484 | TInsn *tinsn = &vinsn->slots[i]; | |
11485 | xtensa_format_get_slot (isa, fmt, i, insnbuf, slotbuf); | |
11486 | tinsn_from_insnbuf (tinsn, slotbuf, fmt, i); | |
11487 | } | |
11488 | } | |
11489 | ||
e0001a05 NC |
11490 | \f |
11491 | /* Expression utilities. */ | |
11492 | ||
43cd72b9 | 11493 | /* Return TRUE if the expression is an integer constant. */ |
e0001a05 NC |
11494 | |
11495 | bfd_boolean | |
7fa3d080 | 11496 | expr_is_const (const expressionS *s) |
e0001a05 NC |
11497 | { |
11498 | return (s->X_op == O_constant); | |
11499 | } | |
11500 | ||
11501 | ||
11502 | /* Get the expression constant. | |
43cd72b9 | 11503 | Calling this is illegal if expr_is_const () returns TRUE. */ |
e0001a05 NC |
11504 | |
11505 | offsetT | |
7fa3d080 | 11506 | get_expr_const (const expressionS *s) |
e0001a05 NC |
11507 | { |
11508 | assert (expr_is_const (s)); | |
11509 | return s->X_add_number; | |
11510 | } | |
11511 | ||
11512 | ||
11513 | /* Set the expression to a constant value. */ | |
11514 | ||
11515 | void | |
7fa3d080 | 11516 | set_expr_const (expressionS *s, offsetT val) |
e0001a05 NC |
11517 | { |
11518 | s->X_op = O_constant; | |
11519 | s->X_add_number = val; | |
11520 | s->X_add_symbol = NULL; | |
11521 | s->X_op_symbol = NULL; | |
11522 | } | |
11523 | ||
11524 | ||
43cd72b9 | 11525 | bfd_boolean |
7fa3d080 | 11526 | expr_is_register (const expressionS *s) |
43cd72b9 BW |
11527 | { |
11528 | return (s->X_op == O_register); | |
11529 | } | |
11530 | ||
11531 | ||
11532 | /* Get the expression constant. | |
11533 | Calling this is illegal if expr_is_const () returns TRUE. */ | |
11534 | ||
11535 | offsetT | |
7fa3d080 | 11536 | get_expr_register (const expressionS *s) |
43cd72b9 BW |
11537 | { |
11538 | assert (expr_is_register (s)); | |
11539 | return s->X_add_number; | |
11540 | } | |
11541 | ||
11542 | ||
e0001a05 NC |
11543 | /* Set the expression to a symbol + constant offset. */ |
11544 | ||
11545 | void | |
7fa3d080 | 11546 | set_expr_symbol_offset (expressionS *s, symbolS *sym, offsetT offset) |
e0001a05 NC |
11547 | { |
11548 | s->X_op = O_symbol; | |
11549 | s->X_add_symbol = sym; | |
11550 | s->X_op_symbol = NULL; /* unused */ | |
11551 | s->X_add_number = offset; | |
11552 | } | |
11553 | ||
11554 | ||
43cd72b9 BW |
11555 | /* Return TRUE if the two expressions are equal. */ |
11556 | ||
e0001a05 | 11557 | bfd_boolean |
7fa3d080 | 11558 | expr_is_equal (expressionS *s1, expressionS *s2) |
e0001a05 NC |
11559 | { |
11560 | if (s1->X_op != s2->X_op) | |
11561 | return FALSE; | |
11562 | if (s1->X_add_symbol != s2->X_add_symbol) | |
11563 | return FALSE; | |
11564 | if (s1->X_op_symbol != s2->X_op_symbol) | |
11565 | return FALSE; | |
11566 | if (s1->X_add_number != s2->X_add_number) | |
11567 | return FALSE; | |
11568 | return TRUE; | |
11569 | } | |
11570 | ||
11571 | ||
11572 | static void | |
7fa3d080 | 11573 | copy_expr (expressionS *dst, const expressionS *src) |
e0001a05 NC |
11574 | { |
11575 | memcpy (dst, src, sizeof (expressionS)); | |
11576 | } | |
11577 | ||
11578 | \f | |
9456465c | 11579 | /* Support for the "--rename-section" option. */ |
e0001a05 NC |
11580 | |
11581 | struct rename_section_struct | |
11582 | { | |
11583 | char *old_name; | |
11584 | char *new_name; | |
11585 | struct rename_section_struct *next; | |
11586 | }; | |
11587 | ||
11588 | static struct rename_section_struct *section_rename; | |
11589 | ||
11590 | ||
9456465c BW |
11591 | /* Parse the string "oldname=new_name(:oldname2=new_name2)*" and add |
11592 | entries to the section_rename list. Note: Specifying multiple | |
11593 | renamings separated by colons is not documented and is retained only | |
11594 | for backward compatibility. */ | |
e0001a05 | 11595 | |
7fa3d080 BW |
11596 | static void |
11597 | build_section_rename (const char *arg) | |
e0001a05 | 11598 | { |
9456465c | 11599 | struct rename_section_struct *r; |
e0001a05 NC |
11600 | char *this_arg = NULL; |
11601 | char *next_arg = NULL; | |
11602 | ||
9456465c | 11603 | for (this_arg = xstrdup (arg); this_arg != NULL; this_arg = next_arg) |
e0001a05 | 11604 | { |
9456465c BW |
11605 | char *old_name, *new_name; |
11606 | ||
e0001a05 NC |
11607 | if (this_arg) |
11608 | { | |
11609 | next_arg = strchr (this_arg, ':'); | |
11610 | if (next_arg) | |
11611 | { | |
11612 | *next_arg = '\0'; | |
11613 | next_arg++; | |
11614 | } | |
11615 | } | |
e0001a05 | 11616 | |
9456465c BW |
11617 | old_name = this_arg; |
11618 | new_name = strchr (this_arg, '='); | |
e0001a05 | 11619 | |
9456465c BW |
11620 | if (*old_name == '\0') |
11621 | { | |
11622 | as_warn (_("ignoring extra '-rename-section' delimiter ':'")); | |
11623 | continue; | |
11624 | } | |
11625 | if (!new_name || new_name[1] == '\0') | |
11626 | { | |
11627 | as_warn (_("ignoring invalid '-rename-section' specification: '%s'"), | |
11628 | old_name); | |
11629 | continue; | |
11630 | } | |
11631 | *new_name = '\0'; | |
11632 | new_name++; | |
e0001a05 | 11633 | |
9456465c BW |
11634 | /* Check for invalid section renaming. */ |
11635 | for (r = section_rename; r != NULL; r = r->next) | |
11636 | { | |
11637 | if (strcmp (r->old_name, old_name) == 0) | |
11638 | as_bad (_("section %s renamed multiple times"), old_name); | |
11639 | if (strcmp (r->new_name, new_name) == 0) | |
11640 | as_bad (_("multiple sections remapped to output section %s"), | |
11641 | new_name); | |
11642 | } | |
e0001a05 | 11643 | |
9456465c BW |
11644 | /* Now add it. */ |
11645 | r = (struct rename_section_struct *) | |
11646 | xmalloc (sizeof (struct rename_section_struct)); | |
11647 | r->old_name = xstrdup (old_name); | |
11648 | r->new_name = xstrdup (new_name); | |
11649 | r->next = section_rename; | |
11650 | section_rename = r; | |
e0001a05 | 11651 | } |
e0001a05 NC |
11652 | } |
11653 | ||
11654 | ||
9456465c BW |
11655 | char * |
11656 | xtensa_section_rename (char *name) | |
e0001a05 NC |
11657 | { |
11658 | struct rename_section_struct *r = section_rename; | |
11659 | ||
11660 | for (r = section_rename; r != NULL; r = r->next) | |
43cd72b9 BW |
11661 | { |
11662 | if (strcmp (r->old_name, name) == 0) | |
11663 | return r->new_name; | |
11664 | } | |
e0001a05 NC |
11665 | |
11666 | return name; | |
11667 | } |