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4b95cf5c | 1 | @c Copyright (C) 1991-2014 Free Software Foundation, Inc. |
252b5132 RH |
2 | @c This is part of the GAS manual. |
3 | @c For copying conditions, see the file as.texinfo. | |
4 | @ifset GENERIC | |
5 | @page | |
6 | @node MIPS-Dependent | |
7 | @chapter MIPS Dependent Features | |
8 | @end ifset | |
9 | @ifclear GENERIC | |
10 | @node Machine Dependencies | |
11 | @chapter MIPS Dependent Features | |
12 | @end ifclear | |
13 | ||
14 | @cindex MIPS processor | |
98508b2a RS |
15 | @sc{gnu} @code{@value{AS}} for MIPS architectures supports several |
16 | different MIPS processors, and MIPS ISA levels I through V, MIPS32, | |
17 | and MIPS64. For information about the MIPS instruction set, see | |
584da044 | 18 | @cite{MIPS RISC Architecture}, by Kane and Heindrich (Prentice-Hall). |
98508b2a | 19 | For an overview of MIPS assembly conventions, see ``Appendix D: |
584da044 | 20 | Assembly Language Programming'' in the same work. |
252b5132 RH |
21 | |
22 | @menu | |
98508b2a | 23 | * MIPS Options:: Assembler options |
fc16f8cc | 24 | * MIPS Macros:: High-level assembly macros |
5a7560b5 | 25 | * MIPS Symbol Sizes:: Directives to override the size of symbols |
fc16f8cc | 26 | * MIPS Small Data:: Controlling the use of small data accesses |
252b5132 | 27 | * MIPS ISA:: Directives to override the ISA level |
833794fc | 28 | * MIPS assembly options:: Directives to control code generation |
252b5132 RH |
29 | * MIPS autoextend:: Directives for extending MIPS 16 bit instructions |
30 | * MIPS insn:: Directive to mark data as an instruction | |
ba92f887 | 31 | * MIPS NaN Encodings:: Directives to record which NaN encoding is being used |
98508b2a RS |
32 | * MIPS Option Stack:: Directives to save and restore options |
33 | * MIPS ASE Instruction Generation Overrides:: Directives to control | |
0eb7102d | 34 | generation of MIPS ASE instructions |
98508b2a | 35 | * MIPS Floating-Point:: Directives to override floating-point options |
7c31ae13 | 36 | * MIPS Syntax:: MIPS specific syntactical considerations |
252b5132 RH |
37 | @end menu |
38 | ||
98508b2a | 39 | @node MIPS Options |
252b5132 RH |
40 | @section Assembler options |
41 | ||
98508b2a | 42 | The MIPS configurations of @sc{gnu} @code{@value{AS}} support these |
252b5132 RH |
43 | special options: |
44 | ||
45 | @table @code | |
46 | @cindex @code{-G} option (MIPS) | |
47 | @item -G @var{num} | |
fc16f8cc RS |
48 | Set the ``small data'' limit to @var{n} bytes. The default limit is 8 bytes. |
49 | @xref{MIPS Small Data,, Controlling the use of small data accesses}. | |
252b5132 RH |
50 | |
51 | @cindex @code{-EB} option (MIPS) | |
52 | @cindex @code{-EL} option (MIPS) | |
53 | @cindex MIPS big-endian output | |
54 | @cindex MIPS little-endian output | |
55 | @cindex big-endian output, MIPS | |
56 | @cindex little-endian output, MIPS | |
57 | @item -EB | |
58 | @itemx -EL | |
98508b2a | 59 | Any MIPS configuration of @code{@value{AS}} can select big-endian or |
252b5132 RH |
60 | little-endian output at run time (unlike the other @sc{gnu} development |
61 | tools, which must be configured for one or the other). Use @samp{-EB} | |
62 | to select big-endian output, and @samp{-EL} for little-endian. | |
63 | ||
0c000745 RS |
64 | @item -KPIC |
65 | @cindex PIC selection, MIPS | |
66 | @cindex @option{-KPIC} option, MIPS | |
67 | Generate SVR4-style PIC. This option tells the assembler to generate | |
68 | SVR4-style position-independent macro expansions. It also tells the | |
69 | assembler to mark the output file as PIC. | |
70 | ||
71 | @item -mvxworks-pic | |
72 | @cindex @option{-mvxworks-pic} option, MIPS | |
73 | Generate VxWorks PIC. This option tells the assembler to generate | |
74 | VxWorks-style position-independent macro expansions. | |
75 | ||
252b5132 RH |
76 | @cindex MIPS architecture options |
77 | @item -mips1 | |
78 | @itemx -mips2 | |
79 | @itemx -mips3 | |
80 | @itemx -mips4 | |
b1929900 | 81 | @itemx -mips5 |
e7af610e | 82 | @itemx -mips32 |
af7ee8bf | 83 | @itemx -mips32r2 |
84ea6cf2 | 84 | @itemx -mips64 |
5f74bc13 | 85 | @itemx -mips64r2 |
252b5132 | 86 | Generate code for a particular MIPS Instruction Set Architecture level. |
98508b2a RS |
87 | @samp{-mips1} corresponds to the R2000 and R3000 processors, |
88 | @samp{-mips2} to the R6000 processor, @samp{-mips3} to the | |
81566a9b MR |
89 | R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. |
90 | @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and | |
91 | @samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, | |
92 | MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also | |
93 | switch instruction sets during the assembly; see @ref{MIPS ISA, | |
94 | Directives to override the ISA level}. | |
252b5132 | 95 | |
6349b5f4 | 96 | @item -mgp32 |
ca4e0257 RS |
97 | @itemx -mfp32 |
98 | Some macros have different expansions for 32-bit and 64-bit registers. | |
99 | The register sizes are normally inferred from the ISA and ABI, but these | |
100 | flags force a certain group of registers to be treated as 32 bits wide at | |
101 | all times. @samp{-mgp32} controls the size of general-purpose registers | |
102 | and @samp{-mfp32} controls the size of floating-point registers. | |
103 | ||
ad3fea08 TS |
104 | The @code{.set gp=32} and @code{.set fp=32} directives allow the size |
105 | of registers to be changed for parts of an object. The default value is | |
106 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
107 | ||
ca4e0257 RS |
108 | On some MIPS variants there is a 32-bit mode flag; when this flag is |
109 | set, 64-bit instructions generate a trap. Also, some 32-bit OSes only | |
110 | save the 32-bit registers on a context switch, so it is essential never | |
111 | to use the 64-bit registers. | |
6349b5f4 AH |
112 | |
113 | @item -mgp64 | |
ad3fea08 TS |
114 | @itemx -mfp64 |
115 | Assume that 64-bit registers are available. This is provided in the | |
116 | interests of symmetry with @samp{-mgp32} and @samp{-mfp32}. | |
117 | ||
118 | The @code{.set gp=64} and @code{.set fp=64} directives allow the size | |
119 | of registers to be changed for parts of an object. The default value is | |
120 | restored by @code{.set gp=default} and @code{.set fp=default}. | |
6349b5f4 | 121 | |
252b5132 RH |
122 | @item -mips16 |
123 | @itemx -no-mips16 | |
124 | Generate code for the MIPS 16 processor. This is equivalent to putting | |
ad3fea08 | 125 | @code{.set mips16} at the start of the assembly file. @samp{-no-mips16} |
252b5132 RH |
126 | turns off this option. |
127 | ||
df58fc94 RS |
128 | @item -mmicromips |
129 | @itemx -mno-micromips | |
130 | Generate code for the microMIPS processor. This is equivalent to putting | |
131 | @code{.set micromips} at the start of the assembly file. @samp{-mno-micromips} | |
132 | turns off this option. This is equivalent to putting @code{.set nomicromips} | |
133 | at the start of the assembly file. | |
134 | ||
e16bfa71 TS |
135 | @item -msmartmips |
136 | @itemx -mno-smartmips | |
137 | Enables the SmartMIPS extensions to the MIPS32 instruction set, which | |
138 | provides a number of new instructions which target smartcard and | |
139 | cryptographic applications. This is equivalent to putting | |
ad3fea08 | 140 | @code{.set smartmips} at the start of the assembly file. |
e16bfa71 TS |
141 | @samp{-mno-smartmips} turns off this option. |
142 | ||
1f25f5d3 CD |
143 | @item -mips3d |
144 | @itemx -no-mips3d | |
145 | Generate code for the MIPS-3D Application Specific Extension. | |
146 | This tells the assembler to accept MIPS-3D instructions. | |
147 | @samp{-no-mips3d} turns off this option. | |
148 | ||
deec1734 CD |
149 | @item -mdmx |
150 | @itemx -no-mdmx | |
151 | Generate code for the MDMX Application Specific Extension. | |
152 | This tells the assembler to accept MDMX instructions. | |
153 | @samp{-no-mdmx} turns off this option. | |
154 | ||
2ef2b9ae CF |
155 | @item -mdsp |
156 | @itemx -mno-dsp | |
8b082fb1 TS |
157 | Generate code for the DSP Release 1 Application Specific Extension. |
158 | This tells the assembler to accept DSP Release 1 instructions. | |
2ef2b9ae CF |
159 | @samp{-mno-dsp} turns off this option. |
160 | ||
8b082fb1 TS |
161 | @item -mdspr2 |
162 | @itemx -mno-dspr2 | |
163 | Generate code for the DSP Release 2 Application Specific Extension. | |
164 | This option implies -mdsp. | |
165 | This tells the assembler to accept DSP Release 2 instructions. | |
166 | @samp{-mno-dspr2} turns off this option. | |
167 | ||
ef2e4d86 CF |
168 | @item -mmt |
169 | @itemx -mno-mt | |
170 | Generate code for the MT Application Specific Extension. | |
171 | This tells the assembler to accept MT instructions. | |
172 | @samp{-mno-mt} turns off this option. | |
173 | ||
dec0624d MR |
174 | @item -mmcu |
175 | @itemx -mno-mcu | |
176 | Generate code for the MCU Application Specific Extension. | |
177 | This tells the assembler to accept MCU instructions. | |
178 | @samp{-mno-mcu} turns off this option. | |
179 | ||
56d438b1 CF |
180 | @item -mmsa |
181 | @itemx -mno-msa | |
182 | Generate code for the MIPS SIMD Architecture Extension. | |
183 | This tells the assembler to accept MSA instructions. | |
184 | @samp{-mno-msa} turns off this option. | |
185 | ||
7d64c587 AB |
186 | @item -mxpa |
187 | @itemx -mno-xpa | |
188 | Generate code for the MIPS eXtended Physical Address (XPA) Extension. | |
189 | This tells the assembler to accept XPA instructions. | |
190 | @samp{-mno-xpa} turns off this option. | |
191 | ||
b015e599 AP |
192 | @item -mvirt |
193 | @itemx -mno-virt | |
194 | Generate code for the Virtualization Application Specific Extension. | |
195 | This tells the assembler to accept Virtualization instructions. | |
196 | @samp{-mno-virt} turns off this option. | |
197 | ||
833794fc MR |
198 | @item -minsn32 |
199 | @itemx -mno-insn32 | |
200 | Only use 32-bit instruction encodings when generating code for the | |
201 | microMIPS processor. This option inhibits the use of any 16-bit | |
202 | instructions. This is equivalent to putting @code{.set insn32} at | |
203 | the start of the assembly file. @samp{-mno-insn32} turns off this | |
204 | option. This is equivalent to putting @code{.set noinsn32} at the | |
205 | start of the assembly file. By default @samp{-mno-insn32} is | |
206 | selected, allowing all instructions to be used. | |
207 | ||
6b76fefe | 208 | @item -mfix7000 |
9ee72ff1 | 209 | @itemx -mno-fix7000 |
6b76fefe CM |
210 | Cause nops to be inserted if the read of the destination register |
211 | of an mfhi or mflo instruction occurs in the following two instructions. | |
212 | ||
a8d14a88 CM |
213 | @item -mfix-rm7000 |
214 | @itemx -mno-fix-rm7000 | |
215 | Cause nops to be inserted if a dmult or dmultu instruction is | |
216 | followed by a load instruction. | |
217 | ||
c67a084a NC |
218 | @item -mfix-loongson2f-jump |
219 | @itemx -mno-fix-loongson2f-jump | |
220 | Eliminate instruction fetch from outside 256M region to work around the | |
221 | Loongson2F @samp{jump} instructions. Without it, under extreme cases, | |
222 | the kernel may crash. The issue has been solved in latest processor | |
223 | batches, but this fix has no side effect to them. | |
224 | ||
225 | @item -mfix-loongson2f-nop | |
226 | @itemx -mno-fix-loongson2f-nop | |
227 | Replace nops by @code{or at,at,zero} to work around the Loongson2F | |
98508b2a RS |
228 | @samp{nop} errata. Without it, under extreme cases, the CPU might |
229 | deadlock. The issue has been solved in later Loongson2F batches, but | |
c67a084a NC |
230 | this fix has no side effect to them. |
231 | ||
d766e8ec | 232 | @item -mfix-vr4120 |
2babba43 | 233 | @itemx -mno-fix-vr4120 |
d766e8ec RS |
234 | Insert nops to work around certain VR4120 errata. This option is |
235 | intended to be used on GCC-generated code: it is not designed to catch | |
236 | all problems in hand-written assembler code. | |
60b63b72 | 237 | |
11db99f8 | 238 | @item -mfix-vr4130 |
2babba43 | 239 | @itemx -mno-fix-vr4130 |
11db99f8 RS |
240 | Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. |
241 | ||
6a32d874 | 242 | @item -mfix-24k |
45e279f5 | 243 | @itemx -mno-fix-24k |
6a32d874 CM |
244 | Insert nops to work around the 24K @samp{eret}/@samp{deret} errata. |
245 | ||
d954098f DD |
246 | @item -mfix-cn63xxp1 |
247 | @itemx -mno-fix-cn63xxp1 | |
248 | Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around | |
249 | certain CN63XXP1 errata. | |
250 | ||
252b5132 RH |
251 | @item -m4010 |
252 | @itemx -no-m4010 | |
98508b2a RS |
253 | Generate code for the LSI R4010 chip. This tells the assembler to |
254 | accept the R4010-specific instructions (@samp{addciu}, @samp{ffc}, | |
252b5132 RH |
255 | etc.), and to not schedule @samp{nop} instructions around accesses to |
256 | the @samp{HI} and @samp{LO} registers. @samp{-no-m4010} turns off this | |
257 | option. | |
258 | ||
259 | @item -m4650 | |
260 | @itemx -no-m4650 | |
98508b2a | 261 | Generate code for the MIPS R4650 chip. This tells the assembler to accept |
252b5132 RH |
262 | the @samp{mad} and @samp{madu} instruction, and to not schedule @samp{nop} |
263 | instructions around accesses to the @samp{HI} and @samp{LO} registers. | |
264 | @samp{-no-m4650} turns off this option. | |
265 | ||
a4ac1c42 | 266 | @item -m3900 |
252b5132 RH |
267 | @itemx -no-m3900 |
268 | @itemx -m4100 | |
269 | @itemx -no-m4100 | |
270 | For each option @samp{-m@var{nnnn}}, generate code for the MIPS | |
98508b2a | 271 | R@var{nnnn} chip. This tells the assembler to accept instructions |
252b5132 RH |
272 | specific to that chip, and to schedule for that chip's hazards. |
273 | ||
ec68c924 | 274 | @item -march=@var{cpu} |
98508b2a | 275 | Generate code for a particular MIPS CPU. It is exactly equivalent to |
252b5132 RH |
276 | @samp{-m@var{cpu}}, except that there are more value of @var{cpu} |
277 | understood. Valid @var{cpu} value are: | |
278 | ||
279 | @quotation | |
280 | 2000, | |
281 | 3000, | |
282 | 3900, | |
283 | 4000, | |
284 | 4010, | |
285 | 4100, | |
286 | 4111, | |
60b63b72 RS |
287 | vr4120, |
288 | vr4130, | |
289 | vr4181, | |
252b5132 RH |
290 | 4300, |
291 | 4400, | |
292 | 4600, | |
293 | 4650, | |
294 | 5000, | |
b946ec34 NC |
295 | rm5200, |
296 | rm5230, | |
297 | rm5231, | |
298 | rm5261, | |
299 | rm5721, | |
60b63b72 RS |
300 | vr5400, |
301 | vr5500, | |
252b5132 | 302 | 6000, |
b946ec34 | 303 | rm7000, |
252b5132 | 304 | 8000, |
963ac363 | 305 | rm9000, |
e7af610e | 306 | 10000, |
18ae5d72 | 307 | 12000, |
3aa3176b TS |
308 | 14000, |
309 | 16000, | |
ad3fea08 TS |
310 | 4kc, |
311 | 4km, | |
312 | 4kp, | |
313 | 4ksc, | |
314 | 4kec, | |
315 | 4kem, | |
316 | 4kep, | |
317 | 4ksd, | |
318 | m4k, | |
319 | m4kp, | |
b5503c7b MR |
320 | m14k, |
321 | m14kc, | |
7a795ef4 MR |
322 | m14ke, |
323 | m14kec, | |
ad3fea08 | 324 | 24kc, |
0fdf1951 | 325 | 24kf2_1, |
ad3fea08 | 326 | 24kf, |
0fdf1951 | 327 | 24kf1_1, |
ad3fea08 | 328 | 24kec, |
0fdf1951 | 329 | 24kef2_1, |
ad3fea08 | 330 | 24kef, |
0fdf1951 | 331 | 24kef1_1, |
ad3fea08 | 332 | 34kc, |
0fdf1951 | 333 | 34kf2_1, |
ad3fea08 | 334 | 34kf, |
0fdf1951 | 335 | 34kf1_1, |
711eefe4 | 336 | 34kn, |
f281862d | 337 | 74kc, |
0fdf1951 | 338 | 74kf2_1, |
f281862d | 339 | 74kf, |
0fdf1951 RS |
340 | 74kf1_1, |
341 | 74kf3_2, | |
30f8113a SL |
342 | 1004kc, |
343 | 1004kf2_1, | |
344 | 1004kf, | |
345 | 1004kf1_1, | |
bbaa46c0 | 346 | p5600, |
ad3fea08 TS |
347 | 5kc, |
348 | 5kf, | |
349 | 20kc, | |
350 | 25kf, | |
82100185 | 351 | sb1, |
350cc38d MS |
352 | sb1a, |
353 | loongson2e, | |
037b32b9 | 354 | loongson2f, |
fd503541 | 355 | loongson3a, |
52b6b6b9 | 356 | octeon, |
dd6a37e7 | 357 | octeon+, |
432233b3 | 358 | octeon2, |
55a36193 MK |
359 | xlr, |
360 | xlp | |
252b5132 RH |
361 | @end quotation |
362 | ||
0fdf1951 RS |
363 | For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are |
364 | accepted as synonyms for @samp{@var{n}f1_1}. These values are | |
365 | deprecated. | |
366 | ||
ec68c924 | 367 | @item -mtune=@var{cpu} |
98508b2a | 368 | Schedule and tune for a particular MIPS CPU. Valid @var{cpu} values are |
ec68c924 EC |
369 | identical to @samp{-march=@var{cpu}}. |
370 | ||
316f5878 RS |
371 | @item -mabi=@var{abi} |
372 | Record which ABI the source code uses. The recognized arguments | |
373 | are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. | |
252b5132 | 374 | |
aed1a261 RS |
375 | @item -msym32 |
376 | @itemx -mno-sym32 | |
377 | @cindex -msym32 | |
378 | @cindex -mno-sym32 | |
379 | Equivalent to adding @code{.set sym32} or @code{.set nosym32} to | |
5a7560b5 | 380 | the beginning of the assembler input. @xref{MIPS Symbol Sizes}. |
aed1a261 | 381 | |
252b5132 RH |
382 | @cindex @code{-nocpp} ignored (MIPS) |
383 | @item -nocpp | |
384 | This option is ignored. It is accepted for command-line compatibility with | |
385 | other assemblers, which use it to turn off C style preprocessing. With | |
386 | @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the | |
387 | @sc{gnu} assembler itself never runs the C preprocessor. | |
388 | ||
037b32b9 AN |
389 | @item -msoft-float |
390 | @itemx -mhard-float | |
391 | Disable or enable floating-point instructions. Note that by default | |
392 | floating-point instructions are always allowed even with CPU targets | |
393 | that don't have support for these instructions. | |
394 | ||
395 | @item -msingle-float | |
396 | @itemx -mdouble-float | |
397 | Disable or enable double-precision floating-point operations. Note | |
398 | that by default double-precision floating-point operations are always | |
399 | allowed even with CPU targets that don't have support for these | |
400 | operations. | |
401 | ||
119d663a NC |
402 | @item --construct-floats |
403 | @itemx --no-construct-floats | |
119d663a NC |
404 | The @code{--no-construct-floats} option disables the construction of |
405 | double width floating point constants by loading the two halves of the | |
406 | value into the two single width floating point registers that make up | |
407 | the double width register. This feature is useful if the processor | |
408 | support the FR bit in its status register, and this bit is known (by | |
409 | the programmer) to be set. This bit prevents the aliasing of the double | |
410 | width register by the single width registers. | |
411 | ||
63bf5651 | 412 | By default @code{--construct-floats} is selected, allowing construction |
119d663a NC |
413 | of these floating point constants. |
414 | ||
3bf0dbfb MR |
415 | @item --relax-branch |
416 | @itemx --no-relax-branch | |
417 | The @samp{--relax-branch} option enables the relaxation of out-of-range | |
418 | branches. Any branches whose target cannot be reached directly are | |
419 | converted to a small instruction sequence including an inverse-condition | |
420 | branch to the physically next instruction, and a jump to the original | |
421 | target is inserted between the two instructions. In PIC code the jump | |
422 | will involve further instructions for address calculation. | |
423 | ||
424 | The @code{BC1ANY2F}, @code{BC1ANY2T}, @code{BC1ANY4F}, @code{BC1ANY4T}, | |
425 | @code{BPOSGE32} and @code{BPOSGE64} instructions are excluded from | |
426 | relaxation, because they have no complementing counterparts. They could | |
427 | be relaxed with the use of a longer sequence involving another branch, | |
428 | however this has not been implemented and if their target turns out of | |
429 | reach, they produce an error even if branch relaxation is enabled. | |
430 | ||
81566a9b | 431 | Also no MIPS16 branches are ever relaxed. |
3bf0dbfb MR |
432 | |
433 | By default @samp{--no-relax-branch} is selected, causing any out-of-range | |
434 | branches to produce an error. | |
435 | ||
ba92f887 MR |
436 | @cindex @option{-mnan=} command line option, MIPS |
437 | @item -mnan=@var{encoding} | |
438 | This option indicates whether the source code uses the IEEE 2008 | |
439 | NaN encoding (@option{-mnan=2008}) or the original MIPS encoding | |
440 | (@option{-mnan=legacy}). It is equivalent to adding a @code{.nan} | |
441 | directive to the beginning of the source file. @xref{MIPS NaN Encodings}. | |
442 | ||
443 | @option{-mnan=legacy} is the default if no @option{-mnan} option or | |
444 | @code{.nan} directive is used. | |
445 | ||
252b5132 RH |
446 | @item --trap |
447 | @itemx --no-break | |
448 | @c FIXME! (1) reflect these options (next item too) in option summaries; | |
449 | @c (2) stop teasing, say _which_ instructions expanded _how_. | |
450 | @code{@value{AS}} automatically macro expands certain division and | |
451 | multiplication instructions to check for overflow and division by zero. This | |
452 | option causes @code{@value{AS}} to generate code to take a trap exception | |
453 | rather than a break exception when an error is detected. The trap instructions | |
454 | are only supported at Instruction Set Architecture level 2 and higher. | |
455 | ||
456 | @item --break | |
457 | @itemx --no-trap | |
458 | Generate code to take a break exception rather than a trap exception when an | |
459 | error is detected. This is the default. | |
63486801 | 460 | |
dcd410fe RO |
461 | @item -mpdr |
462 | @itemx -mno-pdr | |
463 | Control generation of @code{.pdr} sections. Off by default on IRIX, on | |
464 | elsewhere. | |
aa6975fb ILT |
465 | |
466 | @item -mshared | |
467 | @itemx -mno-shared | |
468 | When generating code using the Unix calling conventions (selected by | |
469 | @samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code | |
470 | which can go into a shared library. The @samp{-mno-shared} option | |
471 | tells gas to generate code which uses the calling convention, but can | |
472 | not go into a shared library. The resulting code is slightly more | |
473 | efficient. This option only affects the handling of the | |
474 | @samp{.cpload} and @samp{.cpsetup} pseudo-ops. | |
252b5132 RH |
475 | @end table |
476 | ||
fc16f8cc RS |
477 | @node MIPS Macros |
478 | @section High-level assembly macros | |
479 | ||
480 | MIPS assemblers have traditionally provided a wider range of | |
481 | instructions than the MIPS architecture itself. These extra | |
482 | instructions are usually referred to as ``macro'' instructions | |
483 | @footnote{The term ``macro'' is somewhat overloaded here, since | |
484 | these macros have no relation to those defined by @code{.macro}, | |
485 | @pxref{Macro,, @code{.macro}}.}. | |
486 | ||
487 | Some MIPS macro instructions extend an underlying architectural instruction | |
488 | while others are entirely new. An example of the former type is @code{and}, | |
489 | which allows the third operand to be either a register or an arbitrary | |
490 | immediate value. Examples of the latter type include @code{bgt}, which | |
491 | branches to the third operand when the first operand is greater than | |
492 | the second operand, and @code{ulh}, which implements an unaligned | |
493 | 2-byte load. | |
494 | ||
495 | One of the most common extensions provided by macros is to expand | |
496 | memory offsets to the full address range (32 or 64 bits) and to allow | |
497 | symbolic offsets such as @samp{my_data + 4} to be used in place of | |
498 | integer constants. For example, the architectural instruction | |
499 | @code{lbu} allows only a signed 16-bit offset, whereas the macro | |
500 | @code{lbu} allows code such as @samp{lbu $4,array+32769($5)}. | |
501 | The implementation of these symbolic offsets depends on several factors, | |
98508b2a RS |
502 | such as whether the assembler is generating SVR4-style PIC (selected by |
503 | @option{-KPIC}, @pxref{MIPS Options,, Assembler options}), the size of symbols | |
fc16f8cc RS |
504 | (@pxref{MIPS Symbol Sizes,, Directives to override the size of symbols}), |
505 | and the small data limit (@pxref{MIPS Small Data,, Controlling the use | |
506 | of small data accesses}). | |
507 | ||
508 | @kindex @code{.set macro} | |
509 | @kindex @code{.set nomacro} | |
510 | Sometimes it is undesirable to have one assembly instruction expand | |
511 | to several machine instructions. The directive @code{.set nomacro} | |
512 | tells the assembler to warn when this happens. @code{.set macro} | |
513 | restores the default behavior. | |
514 | ||
515 | @cindex @code{at} register, MIPS | |
516 | @kindex @code{.set at=@var{reg}} | |
517 | Some macro instructions need a temporary register to store intermediate | |
518 | results. This register is usually @code{$1}, also known as @code{$at}, | |
519 | but it can be changed to any core register @var{reg} using | |
520 | @code{.set at=@var{reg}}. Note that @code{$at} always refers | |
521 | to @code{$1} regardless of which register is being used as the | |
522 | temporary register. | |
523 | ||
524 | @kindex @code{.set at} | |
525 | @kindex @code{.set noat} | |
526 | Implicit uses of the temporary register in macros could interfere with | |
527 | explicit uses in the assembly code. The assembler therefore warns | |
528 | whenever it sees an explicit use of the temporary register. The directive | |
529 | @code{.set noat} silences this warning while @code{.set at} restores | |
530 | the default behavior. It is safe to use @code{.set noat} while | |
531 | @code{.set nomacro} is in effect since single-instruction macros | |
532 | never need a temporary register. | |
533 | ||
534 | Note that while the @sc{gnu} assembler provides these macros for compatibility, | |
535 | it does not make any attempt to optimize them with the surrounding code. | |
536 | ||
5a7560b5 | 537 | @node MIPS Symbol Sizes |
aed1a261 RS |
538 | @section Directives to override the size of symbols |
539 | ||
5a7560b5 RS |
540 | @kindex @code{.set sym32} |
541 | @kindex @code{.set nosym32} | |
aed1a261 RS |
542 | The n64 ABI allows symbols to have any 64-bit value. Although this |
543 | provides a great deal of flexibility, it means that some macros have | |
544 | much longer expansions than their 32-bit counterparts. For example, | |
545 | the non-PIC expansion of @samp{dla $4,sym} is usually: | |
546 | ||
547 | @smallexample | |
548 | lui $4,%highest(sym) | |
549 | lui $1,%hi(sym) | |
550 | daddiu $4,$4,%higher(sym) | |
551 | daddiu $1,$1,%lo(sym) | |
552 | dsll32 $4,$4,0 | |
553 | daddu $4,$4,$1 | |
554 | @end smallexample | |
555 | ||
556 | whereas the 32-bit expansion is simply: | |
557 | ||
558 | @smallexample | |
559 | lui $4,%hi(sym) | |
560 | daddiu $4,$4,%lo(sym) | |
561 | @end smallexample | |
562 | ||
563 | n64 code is sometimes constructed in such a way that all symbolic | |
564 | constants are known to have 32-bit values, and in such cases, it's | |
565 | preferable to use the 32-bit expansion instead of the 64-bit | |
566 | expansion. | |
567 | ||
568 | You can use the @code{.set sym32} directive to tell the assembler | |
569 | that, from this point on, all expressions of the form | |
570 | @samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} | |
571 | have 32-bit values. For example: | |
572 | ||
573 | @smallexample | |
574 | .set sym32 | |
575 | dla $4,sym | |
576 | lw $4,sym+16 | |
577 | sw $4,sym+0x8000($4) | |
578 | @end smallexample | |
579 | ||
580 | will cause the assembler to treat @samp{sym}, @code{sym+16} and | |
581 | @code{sym+0x8000} as 32-bit values. The handling of non-symbolic | |
582 | addresses is not affected. | |
583 | ||
584 | The directive @code{.set nosym32} ends a @code{.set sym32} block and | |
585 | reverts to the normal behavior. It is also possible to change the | |
586 | symbol size using the command-line options @option{-msym32} and | |
587 | @option{-mno-sym32}. | |
588 | ||
589 | These options and directives are always accepted, but at present, | |
590 | they have no effect for anything other than n64. | |
591 | ||
fc16f8cc RS |
592 | @node MIPS Small Data |
593 | @section Controlling the use of small data accesses | |
5a7560b5 | 594 | |
fc16f8cc RS |
595 | @c This section deliberately glosses over the possibility of using -G |
596 | @c in SVR4-style PIC, as could be done on IRIX. We don't support that. | |
597 | @cindex small data, MIPS | |
5a7560b5 | 598 | @cindex @code{gp} register, MIPS |
fc16f8cc RS |
599 | It often takes several instructions to load the address of a symbol. |
600 | For example, when @samp{addr} is a 32-bit symbol, the non-PIC expansion | |
601 | of @samp{dla $4,addr} is usually: | |
602 | ||
603 | @smallexample | |
604 | lui $4,%hi(addr) | |
605 | daddiu $4,$4,%lo(addr) | |
606 | @end smallexample | |
607 | ||
608 | The sequence is much longer when @samp{addr} is a 64-bit symbol. | |
609 | @xref{MIPS Symbol Sizes,, Directives to override the size of symbols}. | |
610 | ||
611 | In order to cut down on this overhead, most embedded MIPS systems | |
612 | set aside a 64-kilobyte ``small data'' area and guarantee that all | |
613 | data of size @var{n} and smaller will be placed in that area. | |
614 | The limit @var{n} is passed to both the assembler and the linker | |
98508b2a | 615 | using the command-line option @option{-G @var{n}}, @pxref{MIPS Options,, |
fc16f8cc RS |
616 | Assembler options}. Note that the same value of @var{n} must be used |
617 | when linking and when assembling all input files to the link; any | |
618 | inconsistency could cause a relocation overflow error. | |
619 | ||
620 | The size of an object in the @code{.bss} section is set by the | |
621 | @code{.comm} or @code{.lcomm} directive that defines it. The size of | |
622 | an external object may be set with the @code{.extern} directive. For | |
623 | example, @samp{.extern sym,4} declares that the object at @code{sym} | |
624 | is 4 bytes in length, while leaving @code{sym} otherwise undefined. | |
625 | ||
626 | When no @option{-G} option is given, the default limit is 8 bytes. | |
627 | The option @option{-G 0} prevents any data from being automatically | |
628 | classified as small. | |
629 | ||
630 | It is also possible to mark specific objects as small by putting them | |
631 | in the special sections @code{.sdata} and @code{.sbss}, which are | |
632 | ``small'' counterparts of @code{.data} and @code{.bss} respectively. | |
633 | The toolchain will treat such data as small regardless of the | |
634 | @option{-G} setting. | |
635 | ||
636 | On startup, systems that support a small data area are expected to | |
637 | initialize register @code{$28}, also known as @code{$gp}, in such a | |
638 | way that small data can be accessed using a 16-bit offset from that | |
639 | register. For example, when @samp{addr} is small data, | |
640 | the @samp{dla $4,addr} instruction above is equivalent to: | |
641 | ||
642 | @smallexample | |
643 | daddiu $4,$28,%gp_rel(addr) | |
644 | @end smallexample | |
645 | ||
646 | Small data is not supported for SVR4-style PIC. | |
5a7560b5 | 647 | |
252b5132 RH |
648 | @node MIPS ISA |
649 | @section Directives to override the ISA level | |
650 | ||
651 | @cindex MIPS ISA override | |
652 | @kindex @code{.set mips@var{n}} | |
653 | @sc{gnu} @code{@value{AS}} supports an additional directive to change | |
98508b2a | 654 | the MIPS Instruction Set Architecture level on the fly: @code{.set |
5f74bc13 CD |
655 | mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 |
656 | or 64r2. | |
071742cf | 657 | The values other than 0 make the assembler accept instructions |
e335d9cb | 658 | for the corresponding ISA level, from that point on in the |
584da044 NC |
659 | assembly. @code{.set mips@var{n}} affects not only which instructions |
660 | are permitted, but also how certain macros are expanded. @code{.set | |
e335d9cb | 661 | mips0} restores the ISA level to its original level: either the |
584da044 | 662 | level you selected with command line options, or the default for your |
81566a9b | 663 | configuration. You can use this feature to permit specific MIPS III |
584da044 | 664 | instructions while assembling in 32 bit mode. Use this directive with |
ec68c924 | 665 | care! |
252b5132 | 666 | |
ad3fea08 TS |
667 | @cindex MIPS CPU override |
668 | @kindex @code{.set arch=@var{cpu}} | |
669 | The @code{.set arch=@var{cpu}} directive provides even finer control. | |
670 | It changes the effective CPU target and allows the assembler to use | |
671 | instructions specific to a particular CPU. All CPUs supported by the | |
672 | @samp{-march} command line option are also selectable by this directive. | |
673 | The original value is restored by @code{.set arch=default}. | |
252b5132 | 674 | |
ad3fea08 TS |
675 | The directive @code{.set mips16} puts the assembler into MIPS 16 mode, |
676 | in which it will assemble instructions for the MIPS 16 processor. Use | |
677 | @code{.set nomips16} to return to normal 32 bit mode. | |
e16bfa71 | 678 | |
98508b2a | 679 | Traditional MIPS assemblers do not support this directive. |
252b5132 | 680 | |
df58fc94 RS |
681 | The directive @code{.set micromips} puts the assembler into microMIPS mode, |
682 | in which it will assemble instructions for the microMIPS processor. Use | |
683 | @code{.set nomicromips} to return to normal 32 bit mode. | |
684 | ||
98508b2a | 685 | Traditional MIPS assemblers do not support this directive. |
df58fc94 | 686 | |
833794fc MR |
687 | @node MIPS assembly options |
688 | @section Directives to control code generation | |
689 | ||
690 | @cindex MIPS 32-bit microMIPS instruction generation override | |
691 | @kindex @code{.set insn32} | |
692 | @kindex @code{.set noinsn32} | |
693 | The directive @code{.set insn32} makes the assembler only use 32-bit | |
694 | instruction encodings when generating code for the microMIPS processor. | |
695 | This directive inhibits the use of any 16-bit instructions from that | |
696 | point on in the assembly. The @code{.set noinsn32} directive allows | |
697 | 16-bit instructions to be accepted. | |
698 | ||
699 | Traditional MIPS assemblers do not support this directive. | |
700 | ||
252b5132 RH |
701 | @node MIPS autoextend |
702 | @section Directives for extending MIPS 16 bit instructions | |
703 | ||
704 | @kindex @code{.set autoextend} | |
705 | @kindex @code{.set noautoextend} | |
706 | By default, MIPS 16 instructions are automatically extended to 32 bits | |
ad3fea08 TS |
707 | when necessary. The directive @code{.set noautoextend} will turn this |
708 | off. When @code{.set noautoextend} is in effect, any 32 bit instruction | |
709 | must be explicitly extended with the @code{.e} modifier (e.g., | |
710 | @code{li.e $4,1000}). The directive @code{.set autoextend} may be used | |
252b5132 RH |
711 | to once again automatically extend instructions when necessary. |
712 | ||
713 | This directive is only meaningful when in MIPS 16 mode. Traditional | |
98508b2a | 714 | MIPS assemblers do not support this directive. |
252b5132 RH |
715 | |
716 | @node MIPS insn | |
717 | @section Directive to mark data as an instruction | |
718 | ||
719 | @kindex @code{.insn} | |
720 | The @code{.insn} directive tells @code{@value{AS}} that the following | |
df58fc94 RS |
721 | data is actually instructions. This makes a difference in MIPS 16 and |
722 | microMIPS modes: when loading the address of a label which precedes | |
723 | instructions, @code{@value{AS}} automatically adds 1 to the value, so | |
724 | that jumping to the loaded address will do the right thing. | |
252b5132 | 725 | |
a946d7e3 NC |
726 | @kindex @code{.global} |
727 | The @code{.global} and @code{.globl} directives supported by | |
728 | @code{@value{AS}} will by default mark the symbol as pointing to a | |
729 | region of data not code. This means that, for example, any | |
730 | instructions following such a symbol will not be disassembled by | |
f746e6b9 | 731 | @code{objdump} as it will regard them as data. To change this |
a946d7e3 NC |
732 | behaviour an optional section name can be placed after the symbol name |
733 | in the @code{.global} directive. If this section exists and is known | |
734 | to be a code section, then the symbol will be marked as poiting at | |
735 | code not data. Ie the syntax for the directive is: | |
736 | ||
737 | @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...}, | |
738 | ||
739 | Here is a short example: | |
740 | ||
741 | @example | |
742 | .global foo .text, bar, baz .data | |
743 | foo: | |
744 | nop | |
745 | bar: | |
746 | .word 0x0 | |
747 | baz: | |
748 | .word 0x1 | |
34bca508 | 749 | |
a946d7e3 NC |
750 | @end example |
751 | ||
ba92f887 MR |
752 | @node MIPS NaN Encodings |
753 | @section Directives to record which NaN encoding is being used | |
754 | ||
755 | @cindex MIPS IEEE 754 NaN data encoding selection | |
756 | @cindex @code{.nan} directive, MIPS | |
757 | The IEEE 754 floating-point standard defines two types of not-a-number | |
758 | (NaN) data: ``signalling'' NaNs and ``quiet'' NaNs. The original version | |
759 | of the standard did not specify how these two types should be | |
760 | distinguished. Most implementations followed the i387 model, in which | |
761 | the first bit of the significand is set for quiet NaNs and clear for | |
762 | signalling NaNs. However, the original MIPS implementation assigned the | |
763 | opposite meaning to the bit, so that it was set for signalling NaNs and | |
764 | clear for quiet NaNs. | |
765 | ||
766 | The 2008 revision of the standard formally suggested the i387 choice | |
767 | and as from Sep 2012 the current release of the MIPS architecture | |
768 | therefore optionally supports that form. Code that uses one NaN encoding | |
769 | would usually be incompatible with code that uses the other NaN encoding, | |
770 | so MIPS ELF objects have a flag (@code{EF_MIPS_NAN2008}) to record which | |
771 | encoding is being used. | |
772 | ||
773 | Assembly files can use the @code{.nan} directive to select between the | |
774 | two encodings. @samp{.nan 2008} says that the assembly file uses the | |
775 | IEEE 754-2008 encoding while @samp{.nan legacy} says that the file uses | |
776 | the original MIPS encoding. If several @code{.nan} directives are given, | |
777 | the final setting is the one that is used. | |
778 | ||
779 | The command-line options @option{-mnan=legacy} and @option{-mnan=2008} | |
780 | can be used instead of @samp{.nan legacy} and @samp{.nan 2008} | |
781 | respectively. However, any @code{.nan} directive overrides the | |
782 | command-line setting. | |
783 | ||
784 | @samp{.nan legacy} is the default if no @code{.nan} directive or | |
785 | @option{-mnan} option is given. | |
786 | ||
787 | Note that @sc{gnu} @code{@value{AS}} does not produce NaNs itself and | |
788 | therefore these directives do not affect code generation. They simply | |
789 | control the setting of the @code{EF_MIPS_NAN2008} flag. | |
790 | ||
791 | Traditional MIPS assemblers do not support these directives. | |
792 | ||
98508b2a | 793 | @node MIPS Option Stack |
252b5132 RH |
794 | @section Directives to save and restore options |
795 | ||
796 | @cindex MIPS option stack | |
797 | @kindex @code{.set push} | |
798 | @kindex @code{.set pop} | |
799 | The directives @code{.set push} and @code{.set pop} may be used to save | |
800 | and restore the current settings for all the options which are | |
801 | controlled by @code{.set}. The @code{.set push} directive saves the | |
802 | current settings on a stack. The @code{.set pop} directive pops the | |
803 | stack and restores the settings. | |
804 | ||
805 | These directives can be useful inside an macro which must change an | |
806 | option such as the ISA level or instruction reordering but does not want | |
807 | to change the state of the code which invoked the macro. | |
808 | ||
98508b2a | 809 | Traditional MIPS assemblers do not support these directives. |
1f25f5d3 | 810 | |
98508b2a | 811 | @node MIPS ASE Instruction Generation Overrides |
1f25f5d3 CD |
812 | @section Directives to control generation of MIPS ASE instructions |
813 | ||
814 | @cindex MIPS MIPS-3D instruction generation override | |
815 | @kindex @code{.set mips3d} | |
816 | @kindex @code{.set nomips3d} | |
817 | The directive @code{.set mips3d} makes the assembler accept instructions | |
818 | from the MIPS-3D Application Specific Extension from that point on | |
819 | in the assembly. The @code{.set nomips3d} directive prevents MIPS-3D | |
820 | instructions from being accepted. | |
821 | ||
ad3fea08 TS |
822 | @cindex SmartMIPS instruction generation override |
823 | @kindex @code{.set smartmips} | |
824 | @kindex @code{.set nosmartmips} | |
825 | The directive @code{.set smartmips} makes the assembler accept | |
826 | instructions from the SmartMIPS Application Specific Extension to the | |
e335d9cb | 827 | MIPS32 ISA from that point on in the assembly. The |
ad3fea08 TS |
828 | @code{.set nosmartmips} directive prevents SmartMIPS instructions from |
829 | being accepted. | |
830 | ||
deec1734 CD |
831 | @cindex MIPS MDMX instruction generation override |
832 | @kindex @code{.set mdmx} | |
833 | @kindex @code{.set nomdmx} | |
834 | The directive @code{.set mdmx} makes the assembler accept instructions | |
835 | from the MDMX Application Specific Extension from that point on | |
836 | in the assembly. The @code{.set nomdmx} directive prevents MDMX | |
837 | instructions from being accepted. | |
838 | ||
8b082fb1 | 839 | @cindex MIPS DSP Release 1 instruction generation override |
2ef2b9ae CF |
840 | @kindex @code{.set dsp} |
841 | @kindex @code{.set nodsp} | |
842 | The directive @code{.set dsp} makes the assembler accept instructions | |
8b082fb1 TS |
843 | from the DSP Release 1 Application Specific Extension from that point |
844 | on in the assembly. The @code{.set nodsp} directive prevents DSP | |
845 | Release 1 instructions from being accepted. | |
846 | ||
847 | @cindex MIPS DSP Release 2 instruction generation override | |
848 | @kindex @code{.set dspr2} | |
849 | @kindex @code{.set nodspr2} | |
850 | The directive @code{.set dspr2} makes the assembler accept instructions | |
851 | from the DSP Release 2 Application Specific Extension from that point | |
852 | on in the assembly. This dirctive implies @code{.set dsp}. The | |
853 | @code{.set nodspr2} directive prevents DSP Release 2 instructions from | |
854 | being accepted. | |
2ef2b9ae | 855 | |
ef2e4d86 CF |
856 | @cindex MIPS MT instruction generation override |
857 | @kindex @code{.set mt} | |
858 | @kindex @code{.set nomt} | |
859 | The directive @code{.set mt} makes the assembler accept instructions | |
860 | from the MT Application Specific Extension from that point on | |
861 | in the assembly. The @code{.set nomt} directive prevents MT | |
862 | instructions from being accepted. | |
863 | ||
dec0624d MR |
864 | @cindex MIPS MCU instruction generation override |
865 | @kindex @code{.set mcu} | |
866 | @kindex @code{.set nomcu} | |
867 | The directive @code{.set mcu} makes the assembler accept instructions | |
868 | from the MCU Application Specific Extension from that point on | |
869 | in the assembly. The @code{.set nomcu} directive prevents MCU | |
870 | instructions from being accepted. | |
871 | ||
56d438b1 CF |
872 | @cindex MIPS SIMD Architecture instruction generation override |
873 | @kindex @code{.set msa} | |
874 | @kindex @code{.set nomsa} | |
875 | The directive @code{.set msa} makes the assembler accept instructions | |
876 | from the MIPS SIMD Architecture Extension from that point on | |
877 | in the assembly. The @code{.set nomsa} directive prevents MSA | |
878 | instructions from being accepted. | |
879 | ||
b015e599 AP |
880 | @cindex Virtualization instruction generation override |
881 | @kindex @code{.set virt} | |
882 | @kindex @code{.set novirt} | |
883 | The directive @code{.set virt} makes the assembler accept instructions | |
884 | from the Virtualization Application Specific Extension from that point | |
885 | on in the assembly. The @code{.set novirt} directive prevents Virtualization | |
886 | instructions from being accepted. | |
887 | ||
7d64c587 AB |
888 | @cindex MIPS eXtended Physical Address (XPA) instruction generation override |
889 | @kindex @code{.set xpa} | |
890 | @kindex @code{.set noxpa} | |
891 | The directive @code{.set xpa} makes the assembler accept instructions | |
892 | from the XPA Extension from that point on in the assembly. The | |
893 | @code{.set noxpa} directive prevents XPA instructions from being accepted. | |
894 | ||
98508b2a | 895 | Traditional MIPS assemblers do not support these directives. |
037b32b9 | 896 | |
98508b2a | 897 | @node MIPS Floating-Point |
037b32b9 AN |
898 | @section Directives to override floating-point options |
899 | ||
900 | @cindex Disable floating-point instructions | |
901 | @kindex @code{.set softfloat} | |
902 | @kindex @code{.set hardfloat} | |
903 | The directives @code{.set softfloat} and @code{.set hardfloat} provide | |
904 | finer control of disabling and enabling float-point instructions. | |
905 | These directives always override the default (that hard-float | |
906 | instructions are accepted) or the command-line options | |
907 | (@samp{-msoft-float} and @samp{-mhard-float}). | |
908 | ||
909 | @cindex Disable single-precision floating-point operations | |
605b1dd4 NH |
910 | @kindex @code{.set singlefloat} |
911 | @kindex @code{.set doublefloat} | |
037b32b9 AN |
912 | The directives @code{.set singlefloat} and @code{.set doublefloat} |
913 | provide finer control of disabling and enabling double-precision | |
914 | float-point operations. These directives always override the default | |
915 | (that double-precision operations are accepted) or the command-line | |
916 | options (@samp{-msingle-float} and @samp{-mdouble-float}). | |
917 | ||
98508b2a | 918 | Traditional MIPS assemblers do not support these directives. |
7c31ae13 NC |
919 | |
920 | @node MIPS Syntax | |
921 | @section Syntactical considerations for the MIPS assembler | |
922 | @menu | |
923 | * MIPS-Chars:: Special Characters | |
924 | @end menu | |
925 | ||
926 | @node MIPS-Chars | |
927 | @subsection Special Characters | |
928 | ||
929 | @cindex line comment character, MIPS | |
930 | @cindex MIPS line comment character | |
931 | The presence of a @samp{#} on a line indicates the start of a comment | |
932 | that extends to the end of the current line. | |
933 | ||
934 | If a @samp{#} appears as the first character of a line, the whole line | |
935 | is treated as a comment, but in this case the line can also be a | |
936 | logical line number directive (@pxref{Comments}) or a | |
937 | preprocessor control command (@pxref{Preprocessing}). | |
938 | ||
939 | @cindex line separator, MIPS | |
940 | @cindex statement separator, MIPS | |
941 | @cindex MIPS line separator | |
942 | The @samp{;} character can be used to separate statements on the same | |
943 | line. |