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Commit | Line | Data |
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252b5132 RH |
1 | .SPACE $PRIVATE$ |
2 | .SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31 | |
3 | .SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82 | |
4 | .SPACE $TEXT$ | |
5 | .SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44 | |
6 | .SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY | |
7 | ||
8 | .SPACE $TEXT$ | |
9 | .SUBSPA $CODE$ | |
10 | ||
11 | .align 4 | |
12 | ; Basic immediate instruction tests. | |
13 | ; | |
14 | ; We could/should test some of the corner cases for register and | |
15 | ; immediate fields. We should also check the assorted field | |
16 | ; selectors to make sure they're handled correctly. | |
17 | fcnvff,sgl,sgl %fr5,%fr10 | |
18 | fcnvff,sgl,dbl %fr5,%fr10 | |
19 | fcnvff,sgl,quad %fr5,%fr10 | |
20 | fcnvff,dbl,sgl %fr5,%fr10 | |
21 | fcnvff,dbl,dbl %fr5,%fr10 | |
22 | fcnvff,dbl,quad %fr5,%fr10 | |
23 | fcnvff,quad,sgl %fr5,%fr10 | |
24 | fcnvff,quad,dbl %fr5,%fr10 | |
25 | fcnvff,quad,quad %fr5,%fr10 | |
26 | fcnvff,sgl,sgl %fr20,%fr24 | |
27 | fcnvff,sgl,dbl %fr20,%fr24 | |
28 | fcnvff,sgl,quad %fr20,%fr24 | |
29 | fcnvff,dbl,sgl %fr20,%fr24 | |
30 | fcnvff,dbl,dbl %fr20,%fr24 | |
31 | fcnvff,dbl,quad %fr20,%fr24 | |
32 | fcnvff,quad,sgl %fr20,%fr24 | |
33 | fcnvff,quad,dbl %fr20,%fr24 | |
34 | fcnvff,quad,quad %fr20,%fr24 | |
35 | ||
36 | fcnvxf,sgl,sgl %fr5,%fr10 | |
37 | fcnvxf,sgl,dbl %fr5,%fr10 | |
38 | fcnvxf,sgl,quad %fr5,%fr10 | |
39 | fcnvxf,dbl,sgl %fr5,%fr10 | |
40 | fcnvxf,dbl,dbl %fr5,%fr10 | |
41 | fcnvxf,dbl,quad %fr5,%fr10 | |
42 | fcnvxf,quad,sgl %fr5,%fr10 | |
43 | fcnvxf,quad,dbl %fr5,%fr10 | |
44 | fcnvxf,quad,quad %fr5,%fr10 | |
45 | fcnvxf,sgl,sgl %fr20,%fr24 | |
46 | fcnvxf,sgl,dbl %fr20,%fr24 | |
47 | fcnvxf,sgl,quad %fr20,%fr24 | |
48 | fcnvxf,dbl,sgl %fr20,%fr24 | |
49 | fcnvxf,dbl,dbl %fr20,%fr24 | |
50 | fcnvxf,dbl,quad %fr20,%fr24 | |
51 | fcnvxf,quad,sgl %fr20,%fr24 | |
52 | fcnvxf,quad,dbl %fr20,%fr24 | |
53 | fcnvxf,quad,quad %fr20,%fr24 | |
54 | ||
55 | fcnvfx,sgl,sgl %fr5,%fr10 | |
56 | fcnvfx,sgl,dbl %fr5,%fr10 | |
57 | fcnvfx,sgl,quad %fr5,%fr10 | |
58 | fcnvfx,dbl,sgl %fr5,%fr10 | |
59 | fcnvfx,dbl,dbl %fr5,%fr10 | |
60 | fcnvfx,dbl,quad %fr5,%fr10 | |
61 | fcnvfx,quad,sgl %fr5,%fr10 | |
62 | fcnvfx,quad,dbl %fr5,%fr10 | |
63 | fcnvfx,quad,quad %fr5,%fr10 | |
64 | fcnvfx,sgl,sgl %fr20,%fr24 | |
65 | fcnvfx,sgl,dbl %fr20,%fr24 | |
66 | fcnvfx,sgl,quad %fr20,%fr24 | |
67 | fcnvfx,dbl,sgl %fr20,%fr24 | |
68 | fcnvfx,dbl,dbl %fr20,%fr24 | |
69 | fcnvfx,dbl,quad %fr20,%fr24 | |
70 | fcnvfx,quad,sgl %fr20,%fr24 | |
71 | fcnvfx,quad,dbl %fr20,%fr24 | |
72 | fcnvfx,quad,quad %fr20,%fr24 | |
73 | ||
74 | fcnvfxt,sgl,sgl %fr5,%fr10 | |
75 | fcnvfxt,sgl,dbl %fr5,%fr10 | |
76 | fcnvfxt,sgl,quad %fr5,%fr10 | |
77 | fcnvfxt,dbl,sgl %fr5,%fr10 | |
78 | fcnvfxt,dbl,dbl %fr5,%fr10 | |
79 | fcnvfxt,dbl,quad %fr5,%fr10 | |
80 | fcnvfxt,quad,sgl %fr5,%fr10 | |
81 | fcnvfxt,quad,dbl %fr5,%fr10 | |
82 | fcnvfxt,quad,quad %fr5,%fr10 | |
83 | fcnvfxt,sgl,sgl %fr20,%fr24 | |
84 | fcnvfxt,sgl,dbl %fr20,%fr24 | |
85 | fcnvfxt,sgl,quad %fr20,%fr24 | |
86 | fcnvfxt,dbl,sgl %fr20,%fr24 | |
87 | fcnvfxt,dbl,dbl %fr20,%fr24 | |
88 | fcnvfxt,dbl,quad %fr20,%fr24 | |
89 | fcnvfxt,quad,sgl %fr20,%fr24 | |
90 | fcnvfxt,quad,dbl %fr20,%fr24 | |
91 | fcnvfxt,quad,quad %fr20,%fr24 | |
92 |