[thirdparty/binutils-gdb.git] / gas / testsuite / gas / ia64 / dv-raw-err.s

//	
// Detect RAW violations.  Cases taken from DV tables.
// This test is by no means complete but tries to hit the things that are 
// likely to be missed.
//	
.text
	.explicit
// AR[BSP]
	mov	ar.bspstore = r0
	mov	r1 = ar.bsp
	;;

// AR[BSPSTORE]	
	mov	ar.bspstore = r2
	mov	r3 = ar.bspstore
	;;
	
// AR[CCV]
	mov	ar.ccv = r4
	cmpxchg8.acq r5 = [r6],r7,ar.ccv
	;;
	
// AR[EC]	
	br.wtop.sptk	L
	mov	r8 = ar.ec
	;;

// AR[FPSR].sf0.controls 
	fsetc.s0	0x7f, 0x0f
	fpcmp.eq.s0	f2 = f3, f4
	;;

// AR[FPSR].sf1.controls
	fsetc.s1	0x7f, 0x0f
	fpcmp.eq.s1	f2 = f3, f4
	;;

// AR[FPSR].sf2.controls
	fsetc.s2	0x7f, 0x0f
	fpcmp.eq.s2	f2 = f3, f4
	;;

// AR[FPSR].sf3.controls
	fsetc.s3	0x7f, 0x0f
	fpcmp.eq.s3	f2 = f3, f4
	;;

// AR[FPSR].sf0.flags
	fpcmp.eq.s0	f2 = f3, f4
	fchkf.s0	L
	;;

// AR[FPSR].sf1.flags
	fpcmp.eq.s1	f2 = f3, f4
	fchkf.s1	L
	;;

// AR[FPSR].sf2.flags
	fpcmp.eq.s2	f2 = f3, f4
	fchkf.s2	L
	;;

// AR[FPSR].sf3.flags
	fpcmp.eq.s3	f2 = f3, f4
	fchkf.s3	L
	;;

// AR[FPSR].traps/rv
	mov	ar.fpsr = r0
	fcmp.eq.s3	p1, p2 = f5, f6
	;;

// AR[ITC]
	mov	ar.itc = r1
	mov	r2 = ar.itc
	;;

// AR[RUC]
	mov	ar.ruc = r1
	mov	r2 = ar.ruc
	;;

// AR[K]
	mov	ar.k1 = r3
	br.ia.sptk	b0
	;;
	
// AR[LC]
	br.cloop.sptk	L
	mov	r4 = ar.lc
	;;
	
// AR[PFS]
	mov	ar.pfs = r5
	epc

// AR[RNAT]	
	mov	ar.bspstore = r8
	mov	r9 = ar.rnat	
	;;
	
// AR[RSC]
	mov	ar.rsc = r10
	mov	r11 = ar.rnat
	;;	
	
// AR[UNAT]	
	mov	ar.unat = r12
	ld8.fill r13 = [r14]
	;;
	
// AR%

// BR%
	mov	b0 = r0
	mov	r2 = b0
	;;
	
// CFM	
	br.wtop.sptk	L
	fadd	f2 = f1, f32	// read from rotating register region
	;;
	
// CR[CMCV]
	mov	cr.cmcv = r1
	mov	r2 = cr.cmcv	
	;;

// CR[DCR]
	mov	cr.dcr = r3
	ld8.s	r4 = [r5]
	;;

// CR[EOI]
	
// CR[GPTA]
	mov	cr.gpta = r6
	thash	r7 = r8
	;;
	srlz.d

// CR[IFA]
	mov	cr.ifa = r9
	itc.i	r10
	;;

// CR[IFS]
	mov	cr.ifs = r11
	mov	r12 = cr.ifs
	;;

// CR[IHA]
	mov	cr.iha = r13
	mov	r14 = cr.iha
	;;

// CR[IIB%]
	mov	cr.iib0 = r15
	mov	r16 = cr.iib0
	;;

	mov	cr.iib1 = r15
	mov	r16 = cr.iib1
	;;

// CR[IIM]
	mov	cr.iim = r15
	mov	r16 = cr.iim
	;;

// CR[IIP] 
	mov	cr.iip = r17
	rfi
	;;

// CR[IIPA]
	mov	cr.iipa = r19
	mov	r20 = cr.iipa
	;;

// CR[IPSR]
	mov	cr.ipsr = r21
	rfi
	;;

// CR[IRR%]
	mov	r22 = cr.ivr
	mov	r23 = cr.irr0
	;;
	
// CR[ISR]
	mov	cr.isr = r24
	mov	r25 = cr.isr
	;;	
	
// CR[ITIR]
	mov	cr.itir = r26
	itc.d	r27
	;;	
	
// CR[ITM]
	mov	cr.itm = r28
	mov	r29 = cr.itm
	;;	
	
// CR[ITV]
	mov	cr.itv = r0
	mov	r1 = cr.itv
	;;	
	
// CR[IVR] (all writes are implicit in other resource usage)
	
// CR[IVA]
	mov	cr.iva = r0
	mov	r1 = cr.iva
	;;	
	
// CR[LID]
	mov	cr.lid = r0
	mov	r1 = cr.lid
	;;	
	srlz.d
	
// CR[LRR%]
	mov	cr.lrr0 = r0
	mov	r1 = cr.lrr0
	;;
	
// CR[PMV]
	mov	cr.pmv = r0
	mov	r1 = cr.pmv
	;;
	
// CR[PTA]
	mov	cr.pta = r0
	thash	r1 = r2
	;;
	
// CR[TPR]
	mov	cr.tpr = r0
	mov	r1 = cr.ivr	// data
	;;
	srlz.d
	mov	cr.tpr = r2
	mov	psr.l = r3	// other
	;;
	srlz.d
	
// DBR# 
	mov	dbr[r0] = r1
	mov	r2 = dbr[r3]
	;;	
	srlz.d
	mov	dbr[r4] = r5
	probe.r	r6 = r7, r8
	;;
	srlz.d
	
// DTC
	ptc.e	r0
	fc	r1
	;;
	srlz.d
	itr.i	itr[r2] = r3
	ptc.e	r4
	;;
	
// DTC_LIMIT/ITC_LIMIT 
	ptc.g	r0, r1		// NOTE: GAS automatically emits stops after 
	ptc.ga	r2, r3		//  ptc.g/ptc.ga, so this conflict is no     
	;;			//  longer possible in GAS-generated assembly
	srlz.d

// DTR
	itr.d	dtr[r0] = r1
	tak	r2 = r3
	;;
	srlz.d
	ptr.d	r4, r5
	tpa	r6 = r7
	;;
	srlz.d
	
// FR%
	ldfs.c.clr	f2 = [r1]
	mov		f3 = f2		// no DV here
	;;
	mov		f4 = f5
	mov		f6 = f4
	;;

// GR%
	ld8.c.clr	r1 = [r1]	// no DV here
	mov		r2 = r0		
	;;
	mov		r3 = r4
	mov		r5 = r3
	;;

// IBR#
	mov	ibr[r0] = r1
	mov	r2 = ibr[r3]
	;;

// InService		
	mov	cr.eoi = r0
	mov	r1 = cr.ivr
	;;
	srlz.d
	mov	r2 = cr.ivr
	mov	r3 = cr.ivr	// several DVs
	;;
	mov	cr.eoi = r4
	mov	cr.eoi = r5
	;;
	
// ITC		
	ptc.e	r0
	epc
	;;
	srlz.i
	;;
	
// ITC_LIMIT (see DTC_LIMIT)
	
// ITR	
	itr.i	itr[r0] = r1
	epc
	;;
	srlz.i
	;;
	
// PKR#
	mov	pkr[r0] = r1
	probe.r	r2 = r3, r4
	;;
	srlz.d
	mov	pkr[r5] = r6
	mov	r7 = pkr[r8]
	;;
	srlz.d
	
// PMC#
	mov	pmc[r0] = r1
	mov	r2 = pmc[r3]
	;;
	srlz.d
	mov	pmc[r4] = r5
	mov	r6 = pmd[r7]
	;;
	srlz.d
	
// PMD#
	mov	pmd[r0] = r1
	mov	r2 = pmd[r3]
	;;
	
// PR%, 1 - 15
	cmp.eq	p1, p2 = r0, r1	// pr-writer/pr-reader-nobr-nomovpr
(p1)	add	r2 = r3, r4	
	;;
	mov	pr = r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
(p2)	add	r6 = r7, r8	
	;;
	fcmp.eq p5, p6 = f2, f3 // pr-writer-fp/pr-reader-br
(p5)	br.cond.sptk	b0
	;;
	cmp.eq	p7, p8 = r11, r12
(p7)	br.cond.sptk	b1	// no DV here
	;;
	
// PR63
	br.wtop.sptk	L
(p63)	add	r3 = r1, r2
	;;
	fcmp.eq p62, p63 = f2, f3
(p63)	add	r3 = r4, r5	
	;;
	cmp.eq p62, p63 = r6, r7 // no DV here
(p63)	br.cond.sptk	b0
	;;	

// PSR.ac
	rum	(1<<3)
	ld8	r2 = [r1]
	;;

// PSR.be
	rum	(1<<1)
	ld8	r2 = [r1]
	;;
	
// PSR.bn
	bsw.0
	mov	r1 = r15	// no DV here, since gr < 16
	;;
	bsw.1			// GAS automatically emits a stop after bsw.n
	mov	r1 = r16	// so this conflict is avoided               
	;;
	
// PSR.cpl
	epc
	st8	[r0] = r1
	;;
	epc
	mov	r2 = ar.itc
	;;
	epc
	mov	ar.itc = r3
	;;
	epc
	mov	r2 = ar.ruc
	;;
	epc
	mov	ar.ruc = r3
	;;
	epc
	mov	ar.rsc = r4
	;;
	epc
	mov	ar.k0 = r5
	;;
	epc
	mov	r6 = pmd[r7]
	;;
	epc
	mov	ar.bsp = r8	// no DV here
	;;
	epc
	mov	r9 = ar.bsp	// no DV here
	;;
	epc
	mov	cr.ifa = r10	// any mov-to/from-cr is a DV
	;;
	epc
	mov	r11 = cr.eoi	// any mov-to/from-cr is a DV
	;;

// PSR.da (rfi is the only writer)
// PSR.db (also ac,be,dt,pk)
	mov	psr.l = r0
	ld8	r1 = [r2]
	;;
	srlz.d

// PSR.dd (rfi is the only writer)
	
// PSR.dfh
	mov	psr.l = r0
	mov	f64 = f65
	;;
	srlz.d

// PSR.dfl
	mov	psr.l = r0
	mov	f3 = f4	
	;;
	srlz.d
	
// PSR.di
	rsm	(1<<22)
	mov	r1 = psr
	;;

// PSR.dt
	rsm	(1<<17)
	ld8	r1 = [r1]
	;;
	
// PSR.ed (rfi is the only writer)
// PSR.i
	ssm	(1<<14)
	mov	r1 = psr
	;;
	
// PSR.ia (no DV semantics)
// PSR.ic
	ssm	(1<<13)
	mov	r1 = psr
	;;
	srlz.d
	rsm	(1<<13)
	mov	r1 = cr.itir
	;;
	srlz.d
	rsm	(1<<13)
	mov	r1 = cr.irr0	// no DV here
	;;
	srlz.d

// PSR.id (rfi is the only writer)
// PSR.is (br.ia and rfi are the only writers)
// PSR.it (rfi is the only writer)
// PSR.lp
	mov	psr.l = r0
	br.ret.sptk	b0
	;;

// PSR.mc (rfi is the only writer)
// PSR.mfh
	mov	f32 = f33
	mov	r1 = psr
	;;

// PSR.mfl
	mov	f2 = f3
	mov	r1 = psr
	;;

// PSR.pk
	rsm	(1<<15)
	ld8	r1 = [r1]
	;;
	rsm	(1<<15)
	mov	r2 = psr
	;;

// PSR.pp
	rsm	(1<<21)
	mov	r1 = psr
	;;

// PSR.ri (no DV semantics)
// PSR.rt
	mov	psr.l = r0
	flushrs
	;;
	srlz.d

// PSR.si
	rsm	(1<<23)
	mov	r1 = ar.itc
	;;
	rsm	(1<<23)
	mov	r1 = ar.ruc
	;;
	ssm	(1<<23)
	mov	r1 = ar.ec	// no DV here
	;;

// PSR.sp
	ssm	(1<<20)
	mov	r1 = pmd[r1]
	;;
	ssm	(1<<20)
	rum	0xff
	;;
	ssm	(1<<20)
	mov	r1 = rr[r1]
	;;

// PSR.ss (rfi is the only writer)
// PSR.tb
	mov	psr.l = r0
	chk.s	r0, L
	;;

// PSR.up
	rsm	(1<<2)
	mov	r1 = psr.um
	;;
	srlz.d

// RR#
	mov	rr[r0] = r1
	ld8	r2 = [r0]	// data
	;;
	mov	rr[r4] = r5
	mov	r6 = rr[r7]	// impliedf
	;;
	srlz.d
	;;
// RSE
	
// GR%, additional cases
// addl
	mov	r2 = r32
	addl	r3 = 12345, r2	// impliedf, IA64_OPND_R3_2
	;;
// postinc
	ld8	r2 = [r32], 8
	mov	r8 = r32	// impliedf
	;;

// PR%, 16 - 62
	cmp.eq	p21, p22 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
(p21)	add	r2 = r3, r4	
	;;
	mov	pr = r5, 0x1ffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
(p22)	add	r6 = r7, r8	
	;;
	mov	pr.rot = 0xffff0000 // mov-to-pr-rotreg/pr-reader-nobr-nomovpr
(p23)	add	r9 = r10, r11
	;;
	fcmp.eq p25, p26 = f2, f3 // pr-writer-fp/pr-reader-br
(p25)	br.cond.sptk	b0
	;;
	cmp.eq	p27, p28 = r11, r12
(p27)	br.cond.sptk	b1	// no DV here
	;;
	
// postinc
	st8	[r6] = r8, 16
	add	r7 = 8, r6	// impliedf
	;;
	ldfd	f14 = [r6], 16
	add	r7 = 8, r6	// impliedf
	;;
	stfd	[r6] = f14, 16
	add	r7 = r8, r6
	;;
	add	r6 = 8, r7
	ld8	r8 = [r6], 16	// impliedf, WAW
	;;
	add	r6 = 8, r7
	ldfd	f14 = [r6], 16	// impliedf, WAW
	;;

L:
	br.ret.sptk     rp

// PSR.vm. New in SDM 2.2
	vmsw.0
	ld8	r2 = [r1]
	;;
Commit	Line	Data
800eeca4 JW	1	//
	2	// Detect RAW violations. Cases taken from DV tables.
	3	// This test is by no means complete but tries to hit the things that are
	4	// likely to be missed.
	5	//
	6	.text
	7	.explicit
	8	// AR[BSP]
4b09e828 JB	9	mov ar.bspstore = r0
4b09e828 JB	10	mov r1 = ar.bsp
800eeca4 JW	11	;;
	12
	13	// AR[BSPSTORE]
	14	mov ar.bspstore = r2
	15	mov r3 = ar.bspstore
	16	;;
	17
	18	// AR[CCV]
	19	mov ar.ccv = r4
	20	cmpxchg8.acq r5 = [r6],r7,ar.ccv
	21	;;
	22
	23	// AR[EC]
	24	br.wtop.sptk L
	25	mov r8 = ar.ec
	26	;;
	27
	28	// AR[FPSR].sf0.controls
	29	fsetc.s0 0x7f, 0x0f
	30	fpcmp.eq.s0 f2 = f3, f4
	31	;;
	32
	33	// AR[FPSR].sf1.controls
	34	fsetc.s1 0x7f, 0x0f
	35	fpcmp.eq.s1 f2 = f3, f4
	36	;;
	37
	38	// AR[FPSR].sf2.controls
	39	fsetc.s2 0x7f, 0x0f
	40	fpcmp.eq.s2 f2 = f3, f4
	41	;;
	42
	43	// AR[FPSR].sf3.controls
	44	fsetc.s3 0x7f, 0x0f
	45	fpcmp.eq.s3 f2 = f3, f4
	46	;;
	47
	48	// AR[FPSR].sf0.flags
	49	fpcmp.eq.s0 f2 = f3, f4
	50	fchkf.s0 L
	51	;;
	52
	53	// AR[FPSR].sf1.flags
	54	fpcmp.eq.s1 f2 = f3, f4
	55	fchkf.s1 L
	56	;;
	57
	58	// AR[FPSR].sf2.flags
	59	fpcmp.eq.s2 f2 = f3, f4
	60	fchkf.s2 L
	61	;;
	62
	63	// AR[FPSR].sf3.flags
	64	fpcmp.eq.s3 f2 = f3, f4
	65	fchkf.s3 L
	66	;;
	67
	68	// AR[FPSR].traps/rv
	69	mov ar.fpsr = r0
	70	fcmp.eq.s3 p1, p2 = f5, f6
	71	;;
	72
	73	// AR[ITC]
	74	mov ar.itc = r1
75	mov r2 = ar.itc
76	;;
77
4f8631b1 L	78	// AR[RUC]
	79	mov ar.ruc = r1
	80	mov r2 = ar.ruc
	81	;;
	82
800eeca4 JW	83	// AR[K]
	84	mov ar.k1 = r3
	85	br.ia.sptk b0
	86	;;
	87
	88	// AR[LC]
	89	br.cloop.sptk L
	90	mov r4 = ar.lc
	91	;;
	92
	93	// AR[PFS]
	94	mov ar.pfs = r5
	95	epc
	96
	97	// AR[RNAT]
	98	mov ar.bspstore = r8
	99	mov r9 = ar.rnat
	100	;;
	101
	102	// AR[RSC]
	103	mov ar.rsc = r10
	104	mov r11 = ar.rnat
	105	;;
	106
	107	// AR[UNAT]
	108	mov ar.unat = r12
	109	ld8.fill r13 = [r14]
	110	;;
	111
	112	// AR%
	113
	114	// BR%
	115	mov b0 = r0
4b09e828	116	mov r2 = b0
800eeca4 JW	117	;;
	118
	119	// CFM
	120	br.wtop.sptk L
4b09e828	121	fadd f2 = f1, f32 // read from rotating register region
800eeca4 JW	122	;;
	123
	124	// CR[CMCV]
	125	mov cr.cmcv = r1
	126	mov r2 = cr.cmcv
	127	;;
	128
	129	// CR[DCR]
	130	mov cr.dcr = r3
	131	ld8.s r4 = [r5]
	132	;;
	133
	134	// CR[EOI]
	135
	136	// CR[GPTA]
	137	mov cr.gpta = r6
	138	thash r7 = r8
	139	;;
	140	srlz.d
	141
	142	// CR[IFA]
	143	mov cr.ifa = r9
	144	itc.i r10
	145	;;
	146
	147	// CR[IFS]
	148	mov cr.ifs = r11
	149	mov r12 = cr.ifs
	150	;;
	151
	152	// CR[IHA]
	153	mov cr.iha = r13
	154	mov r14 = cr.iha
	155	;;
	156
1ca35711 L	157	// CR[IIB%]
	158	mov cr.iib0 = r15
	159	mov r16 = cr.iib0
	160	;;
	161
	162	mov cr.iib1 = r15
	163	mov r16 = cr.iib1
	164	;;
	165
800eeca4 JW	166	// CR[IIM]
	167	mov cr.iim = r15
	168	mov r16 = cr.iim
	169	;;
	170
	171	// CR[IIP]
	172	mov cr.iip = r17
	173	rfi
	174	;;
	175
	176	// CR[IIPA]
	177	mov cr.iipa = r19
	178	mov r20 = cr.iipa
	179	;;
	180
	181	// CR[IPSR]
	182	mov cr.ipsr = r21
	183	rfi
	184	;;
	185
	186	// CR[IRR%]
	187	mov r22 = cr.ivr
	188	mov r23 = cr.irr0
	189	;;
	190
	191	// CR[ISR]
	192	mov cr.isr = r24
	193	mov r25 = cr.isr
	194	;;
	195
	196	// CR[ITIR]
	197	mov cr.itir = r26
	198	itc.d r27
	199	;;
	200
	201	// CR[ITM]
	202	mov cr.itm = r28
	203	mov r29 = cr.itm
	204	;;
	205
	206	// CR[ITV]
	207	mov cr.itv = r0
	208	mov r1 = cr.itv
	209	;;
	210
	211	// CR[IVR] (all writes are implicit in other resource usage)
	212
	213	// CR[IVA]
	214	mov cr.iva = r0
	215	mov r1 = cr.iva
	216	;;
	217
	218	// CR[LID]
	219	mov cr.lid = r0
	220	mov r1 = cr.lid
	221	;;
	222	srlz.d
	223
	224	// CR[LRR%]
	225	mov cr.lrr0 = r0
	226	mov r1 = cr.lrr0
	227	;;
	228
	229	// CR[PMV]
230	mov cr.pmv = r0
231	mov r1 = cr.pmv
232	;;
233
234	// CR[PTA]
235	mov cr.pta = r0
236	thash r1 = r2
237	;;
238
239	// CR[TPR]
240	mov cr.tpr = r0
241	mov r1 = cr.ivr // data
242	;;
243	srlz.d
244	mov cr.tpr = r2
245	mov psr.l = r3 // other
246	;;
247	srlz.d
248
249	// DBR#
250	mov dbr[r0] = r1
251	mov r2 = dbr[r3]
252	;;
253	srlz.d
254	mov dbr[r4] = r5
255	probe.r r6 = r7, r8
256	;;
257	srlz.d
258
259	// DTC
260	ptc.e r0
261	fc r1
262	;;
263	srlz.d
264	itr.i itr[r2] = r3
265	ptc.e r4
266	;;
267
268	// DTC_LIMIT/ITC_LIMIT
269	ptc.g r0, r1 // NOTE: GAS automatically emits stops after
270	ptc.ga r2, r3 // ptc.g/ptc.ga, so this conflict is no
271	;; // longer possible in GAS-generated assembly
272	srlz.d
273
274	// DTR
275	itr.d dtr[r0] = r1
276	tak r2 = r3
277	;;
278	srlz.d
279	ptr.d r4, r5
280	tpa r6 = r7
281	;;
282	srlz.d
283
284	// FR%
285	ldfs.c.clr f2 = [r1]
286	mov f3 = f2 // no DV here
287	;;
288	mov f4 = f5
289	mov f6 = f4
290	;;
291
292	// GR%
4b09e828	293	ld8.c.clr r1 = [r1] // no DV here
800eeca4 JW	294	mov r2 = r0
	295	;;
	296	mov r3 = r4
	297	mov r5 = r3
	298	;;
	299
	300	// IBR#
	301	mov ibr[r0] = r1
	302	mov r2 = ibr[r3]
	303	;;
	304
	305	// InService
	306	mov cr.eoi = r0
	307	mov r1 = cr.ivr
	308	;;
	309	srlz.d
	310	mov r2 = cr.ivr
	311	mov r3 = cr.ivr // several DVs
	312	;;
	313	mov cr.eoi = r4
	314	mov cr.eoi = r5
	315	;;
	316
	317	// ITC
	318	ptc.e r0
	319	epc
	320	;;
	321	srlz.i
	322	;;
	323
	324	// ITC_LIMIT (see DTC_LIMIT)
	325
	326	// ITR
	327	itr.i itr[r0] = r1
	328	epc
	329	;;
	330	srlz.i
	331	;;
	332
	333	// PKR#
	334	mov pkr[r0] = r1
	335	probe.r r2 = r3, r4
	336	;;
	337	srlz.d
	338	mov pkr[r5] = r6
	339	mov r7 = pkr[r8]
	340	;;
	341	srlz.d
	342
	343	// PMC#
	344	mov pmc[r0] = r1
	345	mov r2 = pmc[r3]
	346	;;
	347	srlz.d
	348	mov pmc[r4] = r5
	349	mov r6 = pmd[r7]
	350	;;
	351	srlz.d
	352
	353	// PMD#
	354	mov pmd[r0] = r1
	355	mov r2 = pmd[r3]
	356	;;
	357
139368c9	358	// PR%, 1 - 15
800eeca4 JW	359	cmp.eq p1, p2 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
	360	(p1) add r2 = r3, r4
	361	;;
	362	mov pr = r5, 0xffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
	363	(p2) add r6 = r7, r8
	364	;;
	365	fcmp.eq p5, p6 = f2, f3 // pr-writer-fp/pr-reader-br
	366	(p5) br.cond.sptk b0
	367	;;
	368	cmp.eq p7, p8 = r11, r12
	369	(p7) br.cond.sptk b1 // no DV here
	370	;;
	371
	372	// PR63
	373	br.wtop.sptk L
4b09e828	374	(p63) add r3 = r1, r2
800eeca4 JW	375	;;
	376	fcmp.eq p62, p63 = f2, f3
	377	(p63) add r3 = r4, r5
	378	;;
	379	cmp.eq p62, p63 = r6, r7 // no DV here
	380	(p63) br.cond.sptk b0
	381	;;
	382
	383	// PSR.ac
	384	rum (1<<3)
4b09e828	385	ld8 r2 = [r1]
800eeca4 JW	386	;;
	387
	388	// PSR.be
	389	rum (1<<1)
4b09e828	390	ld8 r2 = [r1]
800eeca4 JW	391	;;
	392
	393	// PSR.bn
	394	bsw.0
4b09e828	395	mov r1 = r15 // no DV here, since gr < 16
800eeca4 JW	396	;;
	397	bsw.1 // GAS automatically emits a stop after bsw.n
	398	mov r1 = r16 // so this conflict is avoided
	399	;;
	400
	401	// PSR.cpl
	402	epc
	403	st8 [r0] = r1
	404	;;
	405	epc
	406	mov r2 = ar.itc
	407	;;
	408	epc
	409	mov ar.itc = r3
	410	;;
	411	epc
4f8631b1 L	412	mov r2 = ar.ruc
	413	;;
	414	epc
	415	mov ar.ruc = r3
	416	;;
	417	epc
800eeca4 JW	418	mov ar.rsc = r4
	419	;;
	420	epc
	421	mov ar.k0 = r5
	422	;;
	423	epc
	424	mov r6 = pmd[r7]
	425	;;
	426	epc
	427	mov ar.bsp = r8 // no DV here
	428	;;
	429	epc
	430	mov r9 = ar.bsp // no DV here
	431	;;
	432	epc
	433	mov cr.ifa = r10 // any mov-to/from-cr is a DV
	434	;;
	435	epc
	436	mov r11 = cr.eoi // any mov-to/from-cr is a DV
	437	;;
	438
	439	// PSR.da (rfi is the only writer)
	440	// PSR.db (also ac,be,dt,pk)
	441	mov psr.l = r0
	442	ld8 r1 = [r2]
	443	;;
	444	srlz.d
	445
	446	// PSR.dd (rfi is the only writer)
	447
	448	// PSR.dfh
	449	mov psr.l = r0
	450	mov f64 = f65
	451	;;
	452	srlz.d
	453
	454	// PSR.dfl
	455	mov psr.l = r0
	456	mov f3 = f4
	457	;;
	458	srlz.d
	459
	460	// PSR.di
	461	rsm (1<<22)
4b09e828	462	mov r1 = psr
800eeca4 JW	463	;;
	464
	465	// PSR.dt
	466	rsm (1<<17)
4b09e828	467	ld8 r1 = [r1]
800eeca4 JW	468	;;
	469
	470	// PSR.ed (rfi is the only writer)
	471	// PSR.i
	472	ssm (1<<14)
4b09e828	473	mov r1 = psr
800eeca4 JW	474	;;
	475
	476	// PSR.ia (no DV semantics)
	477	// PSR.ic
	478	ssm (1<<13)
4b09e828	479	mov r1 = psr
800eeca4 JW	480	;;
	481	srlz.d
	482	rsm (1<<13)
	483	mov r1 = cr.itir
	484	;;
	485	srlz.d
	486	rsm (1<<13)
	487	mov r1 = cr.irr0 // no DV here
	488	;;
	489	srlz.d
	490
	491	// PSR.id (rfi is the only writer)
	492	// PSR.is (br.ia and rfi are the only writers)
	493	// PSR.it (rfi is the only writer)
	494	// PSR.lp
	495	mov psr.l = r0
	496	br.ret.sptk b0
	497	;;
	498
	499	// PSR.mc (rfi is the only writer)
	500	// PSR.mfh
	501	mov f32 = f33
4b09e828	502	mov r1 = psr
800eeca4 JW	503	;;
	504
	505	// PSR.mfl
	506	mov f2 = f3
4b09e828	507	mov r1 = psr
800eeca4 JW	508	;;
	509
	510	// PSR.pk
	511	rsm (1<<15)
4b09e828	512	ld8 r1 = [r1]
800eeca4 JW	513	;;
	514	rsm (1<<15)
	515	mov r2 = psr
	516	;;
	517
	518	// PSR.pp
	519	rsm (1<<21)
4b09e828	520	mov r1 = psr
800eeca4 JW	521	;;
	522
	523	// PSR.ri (no DV semantics)
	524	// PSR.rt
	525	mov psr.l = r0
	526	flushrs
	527	;;
	528	srlz.d
	529
	530	// PSR.si
	531	rsm (1<<23)
4b09e828	532	mov r1 = ar.itc
800eeca4	533	;;
4f8631b1 L	534	rsm (1<<23)
	535	mov r1 = ar.ruc
	536	;;
800eeca4 JW	537	ssm (1<<23)
	538	mov r1 = ar.ec // no DV here
	539	;;
	540
	541	// PSR.sp
	542	ssm (1<<20)
4b09e828	543	mov r1 = pmd[r1]
800eeca4 JW	544	;;
	545	ssm (1<<20)
	546	rum 0xff
	547	;;
	548	ssm (1<<20)
4b09e828	549	mov r1 = rr[r1]
800eeca4 JW	550	;;
	551
	552	// PSR.ss (rfi is the only writer)
	553	// PSR.tb
	554	mov psr.l = r0
	555	chk.s r0, L
	556	;;
	557
	558	// PSR.up
	559	rsm (1<<2)
4b09e828	560	mov r1 = psr.um
800eeca4 JW	561	;;
	562	srlz.d
	563
	564	// RR#
	565	mov rr[r0] = r1
	566	ld8 r2 = [r0] // data
	567	;;
	568	mov rr[r4] = r5
	569	mov r6 = rr[r7] // impliedf
	570	;;
50b81f19 JW	571	srlz.d
50b81f19 JW	572	;;
800eeca4	573	// RSE
50b81f19 JW	574
	575	// GR%, additional cases
	576	// addl
	577	mov r2 = r32
	578	addl r3 = 12345, r2 // impliedf, IA64_OPND_R3_2
	579	;;
	580	// postinc
	581	ld8 r2 = [r32], 8
	582	mov r8 = r32 // impliedf
	583	;;
139368c9 JW	584
	585	// PR%, 16 - 62
	586	cmp.eq p21, p22 = r0, r1 // pr-writer/pr-reader-nobr-nomovpr
	587	(p21) add r2 = r3, r4
	588	;;
	589	mov pr = r5, 0x1ffff // mov-to-pr-allreg/pr-reader-nobr-nomovpr
	590	(p22) add r6 = r7, r8
	591	;;
	592	mov pr.rot = 0xffff0000 // mov-to-pr-rotreg/pr-reader-nobr-nomovpr
	593	(p23) add r9 = r10, r11
	594	;;
	595	fcmp.eq p25, p26 = f2, f3 // pr-writer-fp/pr-reader-br
	596	(p25) br.cond.sptk b0
	597	;;
	598	cmp.eq p27, p28 = r11, r12
	599	(p27) br.cond.sptk b1 // no DV here
	600	;;
	601
bad9ceea JJ	602	// postinc
	603	st8 [r6] = r8, 16
	604	add r7 = 8, r6 // impliedf
	605	;;
	606	ldfd f14 = [r6], 16
	607	add r7 = 8, r6 // impliedf
	608	;;
	609	stfd [r6] = f14, 16
	610	add r7 = r8, r6
	611	;;
	612	add r6 = 8, r7
	613	ld8 r8 = [r6], 16 // impliedf, WAW
	614	;;
	615	add r6 = 8, r7
	616	ldfd f14 = [r6], 16 // impliedf, WAW
	617	;;
	618
	619	L:
7f3dfb9c L	620	br.ret.sptk rp
	621
	622	// PSR.vm. New in SDM 2.2
	623	vmsw.0
	624	ld8 r2 = [r1]
	625	;;