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9d19df75 MS |
1 | /* Native-dependent code for GNU/Linux AArch64. |
2 | ||
e2882c85 | 3 | Copyright (C) 2011-2018 Free Software Foundation, Inc. |
9d19df75 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "inferior.h" | |
24 | #include "gdbcore.h" | |
25 | #include "regcache.h" | |
26 | #include "linux-nat.h" | |
27 | #include "target-descriptions.h" | |
28 | #include "auxv.h" | |
29 | #include "gdbcmd.h" | |
30 | #include "aarch64-tdep.h" | |
31 | #include "aarch64-linux-tdep.h" | |
607685ec | 32 | #include "aarch32-linux-nat.h" |
db3cb7cb | 33 | #include "nat/aarch64-linux.h" |
554717a3 | 34 | #include "nat/aarch64-linux-hw-point.h" |
ba2d2bb2 | 35 | #include "nat/aarch64-sve-linux-ptrace.h" |
607685ec YQ |
36 | |
37 | #include "elf/external.h" | |
9d19df75 MS |
38 | #include "elf/common.h" |
39 | ||
5826e159 | 40 | #include "nat/gdb_ptrace.h" |
9d19df75 | 41 | #include <sys/utsname.h> |
036cd381 | 42 | #include <asm/ptrace.h> |
9d19df75 MS |
43 | |
44 | #include "gregset.h" | |
45 | ||
9d19df75 MS |
46 | /* Defines ps_err_e, struct ps_prochandle. */ |
47 | #include "gdb_proc_service.h" | |
48 | ||
49 | #ifndef TRAP_HWBKPT | |
50 | #define TRAP_HWBKPT 0x0004 | |
51 | #endif | |
52 | ||
f6ac5f3d PA |
53 | class aarch64_linux_nat_target final : public linux_nat_target |
54 | { | |
55 | public: | |
56 | /* Add our register access methods. */ | |
57 | void fetch_registers (struct regcache *, int) override; | |
58 | void store_registers (struct regcache *, int) override; | |
59 | ||
60 | const struct target_desc *read_description () override; | |
61 | ||
62 | /* Add our hardware breakpoint and watchpoint implementation. */ | |
63 | int can_use_hw_breakpoint (enum bptype, int, int) override; | |
64 | int insert_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
65 | int remove_hw_breakpoint (struct gdbarch *, struct bp_target_info *) override; | |
66 | int region_ok_for_hw_watchpoint (CORE_ADDR, int) override; | |
67 | int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
68 | struct expression *) override; | |
69 | int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type, | |
70 | struct expression *) override; | |
57810aa7 PA |
71 | bool stopped_by_watchpoint () override; |
72 | bool stopped_data_address (CORE_ADDR *) override; | |
73 | bool watchpoint_addr_within_range (CORE_ADDR, CORE_ADDR, int) override; | |
f6ac5f3d PA |
74 | |
75 | int can_do_single_step () override; | |
76 | ||
77 | /* Override the GNU/Linux inferior startup hook. */ | |
78 | void post_startup_inferior (ptid_t) override; | |
135340af PA |
79 | |
80 | /* These three defer to common nat/ code. */ | |
81 | void low_new_thread (struct lwp_info *lp) override | |
82 | { aarch64_linux_new_thread (lp); } | |
83 | void low_delete_thread (struct arch_lwp_info *lp) override | |
84 | { aarch64_linux_delete_thread (lp); } | |
85 | void low_prepare_to_resume (struct lwp_info *lp) override | |
86 | { aarch64_linux_prepare_to_resume (lp); } | |
87 | ||
88 | void low_new_fork (struct lwp_info *parent, pid_t child_pid) override; | |
89 | void low_forget_process (pid_t pid) override; | |
90 | ||
91 | /* Add our siginfo layout converter. */ | |
92 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
93 | override; | |
f6ac5f3d PA |
94 | }; |
95 | ||
96 | static aarch64_linux_nat_target the_aarch64_linux_nat_target; | |
97 | ||
d6c44983 YZ |
98 | /* Per-process data. We don't bind this to a per-inferior registry |
99 | because of targets like x86 GNU/Linux that need to keep track of | |
100 | processes that aren't bound to any inferior (e.g., fork children, | |
101 | checkpoints). */ | |
9d19df75 | 102 | |
d6c44983 | 103 | struct aarch64_process_info |
9d19df75 | 104 | { |
d6c44983 YZ |
105 | /* Linked list. */ |
106 | struct aarch64_process_info *next; | |
9d19df75 | 107 | |
d6c44983 YZ |
108 | /* The process identifier. */ |
109 | pid_t pid; | |
9d19df75 | 110 | |
d6c44983 YZ |
111 | /* Copy of aarch64 hardware debug registers. */ |
112 | struct aarch64_debug_reg_state state; | |
113 | }; | |
114 | ||
115 | static struct aarch64_process_info *aarch64_process_list = NULL; | |
116 | ||
117 | /* Find process data for process PID. */ | |
118 | ||
119 | static struct aarch64_process_info * | |
120 | aarch64_find_process_pid (pid_t pid) | |
121 | { | |
122 | struct aarch64_process_info *proc; | |
123 | ||
124 | for (proc = aarch64_process_list; proc; proc = proc->next) | |
125 | if (proc->pid == pid) | |
126 | return proc; | |
127 | ||
128 | return NULL; | |
9d19df75 MS |
129 | } |
130 | ||
d6c44983 YZ |
131 | /* Add process data for process PID. Returns newly allocated info |
132 | object. */ | |
9d19df75 | 133 | |
d6c44983 YZ |
134 | static struct aarch64_process_info * |
135 | aarch64_add_process (pid_t pid) | |
9d19df75 | 136 | { |
d6c44983 | 137 | struct aarch64_process_info *proc; |
9d19df75 | 138 | |
8d749320 | 139 | proc = XCNEW (struct aarch64_process_info); |
d6c44983 | 140 | proc->pid = pid; |
9d19df75 | 141 | |
d6c44983 YZ |
142 | proc->next = aarch64_process_list; |
143 | aarch64_process_list = proc; | |
144 | ||
145 | return proc; | |
146 | } | |
147 | ||
148 | /* Get data specific info for process PID, creating it if necessary. | |
149 | Never returns NULL. */ | |
150 | ||
151 | static struct aarch64_process_info * | |
152 | aarch64_process_info_get (pid_t pid) | |
9d19df75 | 153 | { |
d6c44983 YZ |
154 | struct aarch64_process_info *proc; |
155 | ||
156 | proc = aarch64_find_process_pid (pid); | |
157 | if (proc == NULL) | |
158 | proc = aarch64_add_process (pid); | |
9d19df75 | 159 | |
d6c44983 | 160 | return proc; |
9d19df75 MS |
161 | } |
162 | ||
d6c44983 YZ |
163 | /* Called whenever GDB is no longer debugging process PID. It deletes |
164 | data structures that keep track of debug register state. */ | |
9d19df75 | 165 | |
135340af PA |
166 | void |
167 | aarch64_linux_nat_target::low_forget_process (pid_t pid) | |
9d19df75 | 168 | { |
d6c44983 | 169 | struct aarch64_process_info *proc, **proc_link; |
9d19df75 | 170 | |
d6c44983 YZ |
171 | proc = aarch64_process_list; |
172 | proc_link = &aarch64_process_list; | |
173 | ||
174 | while (proc != NULL) | |
9d19df75 | 175 | { |
d6c44983 YZ |
176 | if (proc->pid == pid) |
177 | { | |
178 | *proc_link = proc->next; | |
9d19df75 | 179 | |
d6c44983 YZ |
180 | xfree (proc); |
181 | return; | |
182 | } | |
183 | ||
184 | proc_link = &proc->next; | |
185 | proc = *proc_link; | |
186 | } | |
9d19df75 MS |
187 | } |
188 | ||
d6c44983 | 189 | /* Get debug registers state for process PID. */ |
9d19df75 | 190 | |
db3cb7cb | 191 | struct aarch64_debug_reg_state * |
d6c44983 | 192 | aarch64_get_debug_reg_state (pid_t pid) |
9d19df75 | 193 | { |
d6c44983 | 194 | return &aarch64_process_info_get (pid)->state; |
9d19df75 MS |
195 | } |
196 | ||
9d19df75 MS |
197 | /* Fill GDB's register array with the general-purpose register values |
198 | from the current thread. */ | |
199 | ||
200 | static void | |
201 | fetch_gregs_from_thread (struct regcache *regcache) | |
202 | { | |
607685ec | 203 | int ret, tid; |
ac7936df | 204 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 MS |
205 | elf_gregset_t regs; |
206 | struct iovec iovec; | |
207 | ||
607685ec YQ |
208 | /* Make sure REGS can hold all registers contents on both aarch64 |
209 | and arm. */ | |
210 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
211 | ||
222312d3 | 212 | tid = ptid_get_lwp (regcache->ptid ()); |
9d19df75 MS |
213 | |
214 | iovec.iov_base = ®s; | |
607685ec YQ |
215 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
216 | iovec.iov_len = 18 * 4; | |
217 | else | |
218 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
219 | |
220 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
221 | if (ret < 0) | |
222 | perror_with_name (_("Unable to fetch general registers.")); | |
223 | ||
607685ec YQ |
224 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
225 | aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1); | |
226 | else | |
227 | { | |
228 | int regno; | |
229 | ||
230 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
73e1c03f | 231 | regcache->raw_supply (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 232 | } |
9d19df75 MS |
233 | } |
234 | ||
235 | /* Store to the current thread the valid general-purpose register | |
236 | values in the GDB's register array. */ | |
237 | ||
238 | static void | |
239 | store_gregs_to_thread (const struct regcache *regcache) | |
240 | { | |
607685ec | 241 | int ret, tid; |
9d19df75 MS |
242 | elf_gregset_t regs; |
243 | struct iovec iovec; | |
ac7936df | 244 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 245 | |
607685ec YQ |
246 | /* Make sure REGS can hold all registers contents on both aarch64 |
247 | and arm. */ | |
248 | gdb_static_assert (sizeof (regs) >= 18 * 4); | |
222312d3 | 249 | tid = ptid_get_lwp (regcache->ptid ()); |
9d19df75 MS |
250 | |
251 | iovec.iov_base = ®s; | |
607685ec YQ |
252 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
253 | iovec.iov_len = 18 * 4; | |
254 | else | |
255 | iovec.iov_len = sizeof (regs); | |
9d19df75 MS |
256 | |
257 | ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec); | |
258 | if (ret < 0) | |
259 | perror_with_name (_("Unable to fetch general registers.")); | |
260 | ||
607685ec YQ |
261 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
262 | aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1); | |
263 | else | |
264 | { | |
265 | int regno; | |
266 | ||
267 | for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++) | |
0ec9f114 | 268 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 | 269 | regcache->raw_collect (regno, ®s[regno - AARCH64_X0_REGNUM]); |
607685ec | 270 | } |
9d19df75 MS |
271 | |
272 | ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec); | |
273 | if (ret < 0) | |
274 | perror_with_name (_("Unable to store general registers.")); | |
275 | } | |
276 | ||
277 | /* Fill GDB's register array with the fp/simd register values | |
278 | from the current thread. */ | |
279 | ||
280 | static void | |
281 | fetch_fpregs_from_thread (struct regcache *regcache) | |
282 | { | |
607685ec | 283 | int ret, tid; |
9d19df75 MS |
284 | elf_fpregset_t regs; |
285 | struct iovec iovec; | |
ac7936df | 286 | struct gdbarch *gdbarch = regcache->arch (); |
607685ec YQ |
287 | |
288 | /* Make sure REGS can hold all VFP registers contents on both aarch64 | |
289 | and arm. */ | |
290 | gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); | |
9d19df75 | 291 | |
222312d3 | 292 | tid = ptid_get_lwp (regcache->ptid ()); |
9d19df75 MS |
293 | |
294 | iovec.iov_base = ®s; | |
9d19df75 | 295 | |
607685ec YQ |
296 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
297 | { | |
298 | iovec.iov_len = VFP_REGS_SIZE; | |
299 | ||
300 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); | |
301 | if (ret < 0) | |
302 | perror_with_name (_("Unable to fetch VFP registers.")); | |
303 | ||
304 | aarch32_vfp_regcache_supply (regcache, (gdb_byte *) ®s, 32); | |
305 | } | |
306 | else | |
307 | { | |
308 | int regno; | |
309 | ||
310 | iovec.iov_len = sizeof (regs); | |
9d19df75 | 311 | |
607685ec YQ |
312 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); |
313 | if (ret < 0) | |
314 | perror_with_name (_("Unable to fetch vFP/SIMD registers.")); | |
9d19df75 | 315 | |
607685ec | 316 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) |
73e1c03f | 317 | regcache->raw_supply (regno, ®s.vregs[regno - AARCH64_V0_REGNUM]); |
607685ec | 318 | |
73e1c03f SM |
319 | regcache->raw_supply (AARCH64_FPSR_REGNUM, ®s.fpsr); |
320 | regcache->raw_supply (AARCH64_FPCR_REGNUM, ®s.fpcr); | |
607685ec | 321 | } |
9d19df75 MS |
322 | } |
323 | ||
324 | /* Store to the current thread the valid fp/simd register | |
325 | values in the GDB's register array. */ | |
326 | ||
327 | static void | |
328 | store_fpregs_to_thread (const struct regcache *regcache) | |
329 | { | |
607685ec | 330 | int ret, tid; |
9d19df75 MS |
331 | elf_fpregset_t regs; |
332 | struct iovec iovec; | |
ac7936df | 333 | struct gdbarch *gdbarch = regcache->arch (); |
9d19df75 | 334 | |
607685ec YQ |
335 | /* Make sure REGS can hold all VFP registers contents on both aarch64 |
336 | and arm. */ | |
337 | gdb_static_assert (sizeof regs >= VFP_REGS_SIZE); | |
222312d3 | 338 | tid = ptid_get_lwp (regcache->ptid ()); |
9d19df75 MS |
339 | |
340 | iovec.iov_base = ®s; | |
9d19df75 | 341 | |
607685ec YQ |
342 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
343 | { | |
344 | iovec.iov_len = VFP_REGS_SIZE; | |
9d19df75 | 345 | |
607685ec YQ |
346 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
347 | if (ret < 0) | |
348 | perror_with_name (_("Unable to fetch VFP registers.")); | |
9d19df75 | 349 | |
607685ec YQ |
350 | aarch32_vfp_regcache_collect (regcache, (gdb_byte *) ®s, 32); |
351 | } | |
352 | else | |
353 | { | |
354 | int regno; | |
9d19df75 | 355 | |
607685ec YQ |
356 | iovec.iov_len = sizeof (regs); |
357 | ||
358 | ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec); | |
359 | if (ret < 0) | |
360 | perror_with_name (_("Unable to fetch FP/SIMD registers.")); | |
361 | ||
362 | for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++) | |
0ec9f114 | 363 | if (REG_VALID == regcache->get_register_status (regno)) |
34a79281 SM |
364 | regcache->raw_collect |
365 | (regno, (char *) ®s.vregs[regno - AARCH64_V0_REGNUM]); | |
607685ec | 366 | |
0ec9f114 | 367 | if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM)) |
34a79281 | 368 | regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) ®s.fpsr); |
0ec9f114 | 369 | if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM)) |
34a79281 | 370 | regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) ®s.fpcr); |
607685ec YQ |
371 | } |
372 | ||
373 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
374 | { | |
375 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec); | |
376 | if (ret < 0) | |
377 | perror_with_name (_("Unable to store VFP registers.")); | |
378 | } | |
379 | else | |
380 | { | |
381 | ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec); | |
382 | if (ret < 0) | |
383 | perror_with_name (_("Unable to store FP/SIMD registers.")); | |
384 | } | |
9d19df75 MS |
385 | } |
386 | ||
e9902bfc AH |
387 | /* Fill GDB's register array with the sve register values |
388 | from the current thread. */ | |
389 | ||
390 | static void | |
391 | fetch_sveregs_from_thread (struct regcache *regcache) | |
392 | { | |
393 | std::unique_ptr<gdb_byte[]> base | |
394 | = aarch64_sve_get_sveregs (ptid_get_lwp (regcache->ptid ())); | |
395 | aarch64_sve_regs_copy_to_reg_buf (regcache, base.get ()); | |
396 | } | |
397 | ||
398 | /* Store to the current thread the valid sve register | |
399 | values in the GDB's register array. */ | |
400 | ||
401 | static void | |
402 | store_sveregs_to_thread (struct regcache *regcache) | |
403 | { | |
404 | int ret; | |
405 | struct iovec iovec; | |
406 | int tid = ptid_get_lwp (regcache->ptid ()); | |
407 | ||
408 | /* Obtain a dump of SVE registers from ptrace. */ | |
409 | std::unique_ptr<gdb_byte[]> base = aarch64_sve_get_sveregs (tid); | |
410 | ||
411 | /* Overwrite with regcache state. */ | |
412 | aarch64_sve_regs_copy_from_reg_buf (regcache, base.get ()); | |
413 | ||
414 | /* Write back to the kernel. */ | |
415 | iovec.iov_base = base.get (); | |
416 | iovec.iov_len = ((struct user_sve_header *) base.get ())->size; | |
417 | ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_SVE, &iovec); | |
418 | ||
419 | if (ret < 0) | |
420 | perror_with_name (_("Unable to store sve registers")); | |
421 | } | |
422 | ||
f6ac5f3d | 423 | /* Implement the "fetch_registers" target_ops method. */ |
9d19df75 | 424 | |
f6ac5f3d PA |
425 | void |
426 | aarch64_linux_nat_target::fetch_registers (struct regcache *regcache, | |
427 | int regno) | |
9d19df75 | 428 | { |
e9902bfc AH |
429 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
430 | ||
9d19df75 MS |
431 | if (regno == -1) |
432 | { | |
433 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
434 | if (tdep->has_sve ()) |
435 | fetch_sveregs_from_thread (regcache); | |
436 | else | |
437 | fetch_fpregs_from_thread (regcache); | |
9d19df75 MS |
438 | } |
439 | else if (regno < AARCH64_V0_REGNUM) | |
440 | fetch_gregs_from_thread (regcache); | |
e9902bfc AH |
441 | else if (tdep->has_sve ()) |
442 | fetch_sveregs_from_thread (regcache); | |
9d19df75 MS |
443 | else |
444 | fetch_fpregs_from_thread (regcache); | |
445 | } | |
446 | ||
f6ac5f3d | 447 | /* Implement the "store_registers" target_ops method. */ |
9d19df75 | 448 | |
f6ac5f3d PA |
449 | void |
450 | aarch64_linux_nat_target::store_registers (struct regcache *regcache, | |
451 | int regno) | |
9d19df75 | 452 | { |
e9902bfc AH |
453 | struct gdbarch_tdep *tdep = gdbarch_tdep (regcache->arch ()); |
454 | ||
9d19df75 MS |
455 | if (regno == -1) |
456 | { | |
457 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
458 | if (tdep->has_sve ()) |
459 | store_sveregs_to_thread (regcache); | |
460 | else | |
461 | store_fpregs_to_thread (regcache); | |
9d19df75 MS |
462 | } |
463 | else if (regno < AARCH64_V0_REGNUM) | |
464 | store_gregs_to_thread (regcache); | |
e9902bfc AH |
465 | else if (tdep->has_sve ()) |
466 | store_sveregs_to_thread (regcache); | |
9d19df75 MS |
467 | else |
468 | store_fpregs_to_thread (regcache); | |
469 | } | |
470 | ||
471 | /* Fill register REGNO (if it is a general-purpose register) in | |
472 | *GREGSETPS with the value in GDB's register array. If REGNO is -1, | |
473 | do this for all registers. */ | |
474 | ||
475 | void | |
476 | fill_gregset (const struct regcache *regcache, | |
477 | gdb_gregset_t *gregsetp, int regno) | |
478 | { | |
d4d793bf AA |
479 | regcache_collect_regset (&aarch64_linux_gregset, regcache, |
480 | regno, (gdb_byte *) gregsetp, | |
481 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
482 | } |
483 | ||
484 | /* Fill GDB's register array with the general-purpose register values | |
485 | in *GREGSETP. */ | |
486 | ||
487 | void | |
488 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) | |
489 | { | |
d4d793bf AA |
490 | regcache_supply_regset (&aarch64_linux_gregset, regcache, -1, |
491 | (const gdb_byte *) gregsetp, | |
492 | AARCH64_LINUX_SIZEOF_GREGSET); | |
9d19df75 MS |
493 | } |
494 | ||
495 | /* Fill register REGNO (if it is a floating-point register) in | |
496 | *FPREGSETP with the value in GDB's register array. If REGNO is -1, | |
497 | do this for all registers. */ | |
498 | ||
499 | void | |
500 | fill_fpregset (const struct regcache *regcache, | |
501 | gdb_fpregset_t *fpregsetp, int regno) | |
502 | { | |
d4d793bf AA |
503 | regcache_collect_regset (&aarch64_linux_fpregset, regcache, |
504 | regno, (gdb_byte *) fpregsetp, | |
505 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
506 | } |
507 | ||
508 | /* Fill GDB's register array with the floating-point register values | |
509 | in *FPREGSETP. */ | |
510 | ||
511 | void | |
512 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) | |
513 | { | |
d4d793bf AA |
514 | regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1, |
515 | (const gdb_byte *) fpregsetp, | |
516 | AARCH64_LINUX_SIZEOF_FPREGSET); | |
9d19df75 MS |
517 | } |
518 | ||
d6c44983 YZ |
519 | /* linux_nat_new_fork hook. */ |
520 | ||
135340af PA |
521 | void |
522 | aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent, | |
523 | pid_t child_pid) | |
d6c44983 YZ |
524 | { |
525 | pid_t parent_pid; | |
526 | struct aarch64_debug_reg_state *parent_state; | |
527 | struct aarch64_debug_reg_state *child_state; | |
528 | ||
529 | /* NULL means no watchpoint has ever been set in the parent. In | |
530 | that case, there's nothing to do. */ | |
531 | if (parent->arch_private == NULL) | |
532 | return; | |
533 | ||
534 | /* GDB core assumes the child inherits the watchpoints/hw | |
535 | breakpoints of the parent, and will remove them all from the | |
536 | forked off process. Copy the debug registers mirrors into the | |
537 | new process so that all breakpoints and watchpoints can be | |
538 | removed together. */ | |
539 | ||
540 | parent_pid = ptid_get_pid (parent->ptid); | |
541 | parent_state = aarch64_get_debug_reg_state (parent_pid); | |
542 | child_state = aarch64_get_debug_reg_state (child_pid); | |
543 | *child_state = *parent_state; | |
544 | } | |
9d19df75 MS |
545 | \f |
546 | ||
547 | /* Called by libthread_db. Returns a pointer to the thread local | |
548 | storage (or its descriptor). */ | |
549 | ||
550 | ps_err_e | |
754653a7 | 551 | ps_get_thread_area (struct ps_prochandle *ph, |
9d19df75 MS |
552 | lwpid_t lwpid, int idx, void **base) |
553 | { | |
a0cc84cd YQ |
554 | int is_64bit_p |
555 | = (gdbarch_bfd_arch_info (target_gdbarch ())->bits_per_word == 64); | |
9d19df75 | 556 | |
a0cc84cd | 557 | return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p); |
9d19df75 MS |
558 | } |
559 | \f | |
560 | ||
f6ac5f3d | 561 | /* Implement the "post_startup_inferior" target_ops method. */ |
9d19df75 | 562 | |
f6ac5f3d PA |
563 | void |
564 | aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid) | |
9d19df75 | 565 | { |
135340af | 566 | low_forget_process (ptid_get_pid (ptid)); |
af1b22f3 | 567 | aarch64_linux_get_debug_reg_capacity (ptid_get_pid (ptid)); |
f6ac5f3d | 568 | linux_nat_target::post_startup_inferior (ptid); |
9d19df75 MS |
569 | } |
570 | ||
607685ec YQ |
571 | extern struct target_desc *tdesc_arm_with_neon; |
572 | ||
f6ac5f3d | 573 | /* Implement the "read_description" target_ops method. */ |
9d19df75 | 574 | |
f6ac5f3d PA |
575 | const struct target_desc * |
576 | aarch64_linux_nat_target::read_description () | |
9d19df75 | 577 | { |
6f67973b YQ |
578 | int ret, tid; |
579 | gdb_byte regbuf[VFP_REGS_SIZE]; | |
580 | struct iovec iovec; | |
607685ec | 581 | |
6f67973b | 582 | tid = ptid_get_lwp (inferior_ptid); |
607685ec | 583 | |
6f67973b YQ |
584 | iovec.iov_base = regbuf; |
585 | iovec.iov_len = VFP_REGS_SIZE; | |
607685ec | 586 | |
6f67973b YQ |
587 | ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec); |
588 | if (ret == 0) | |
589 | return tdesc_arm_with_neon; | |
590 | else | |
ba2d2bb2 | 591 | return aarch64_read_description (aarch64_sve_get_vq (tid)); |
9d19df75 MS |
592 | } |
593 | ||
ade90bde YQ |
594 | /* Convert a native/host siginfo object, into/from the siginfo in the |
595 | layout of the inferiors' architecture. Returns true if any | |
596 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
597 | from INF to NATIVE. If DIRECTION is 0, copy from NATIVE to | |
598 | INF. */ | |
599 | ||
135340af PA |
600 | bool |
601 | aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, | |
602 | int direction) | |
ade90bde YQ |
603 | { |
604 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); | |
605 | ||
606 | /* Is the inferior 32-bit? If so, then do fixup the siginfo | |
607 | object. */ | |
608 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
609 | { | |
610 | if (direction == 0) | |
611 | aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf, | |
612 | native); | |
613 | else | |
614 | aarch64_siginfo_from_compat_siginfo (native, | |
615 | (struct compat_siginfo *) inf); | |
616 | ||
135340af | 617 | return true; |
ade90bde YQ |
618 | } |
619 | ||
135340af | 620 | return false; |
ade90bde YQ |
621 | } |
622 | ||
9d19df75 MS |
623 | /* Returns the number of hardware watchpoints of type TYPE that we can |
624 | set. Value is positive if we can set CNT watchpoints, zero if | |
625 | setting watchpoints of type TYPE is not supported, and negative if | |
626 | CNT is more than the maximum number of watchpoints of type TYPE | |
627 | that we can support. TYPE is one of bp_hardware_watchpoint, | |
628 | bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint. | |
629 | CNT is the number of such watchpoints used so far (including this | |
630 | one). OTHERTYPE is non-zero if other types of watchpoints are | |
c2fbdc59 | 631 | currently enabled. */ |
9d19df75 | 632 | |
f6ac5f3d PA |
633 | int |
634 | aarch64_linux_nat_target::can_use_hw_breakpoint (enum bptype type, | |
635 | int cnt, int othertype) | |
9d19df75 | 636 | { |
c2fbdc59 YQ |
637 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint |
638 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
639 | { | |
640 | if (aarch64_num_wp_regs == 0) | |
641 | return 0; | |
642 | } | |
643 | else if (type == bp_hardware_breakpoint) | |
644 | { | |
645 | if (aarch64_num_bp_regs == 0) | |
646 | return 0; | |
647 | } | |
648 | else | |
649 | gdb_assert_not_reached ("unexpected breakpoint type"); | |
650 | ||
651 | /* We always return 1 here because we don't have enough information | |
652 | about possible overlap of addresses that they want to watch. As an | |
653 | extreme example, consider the case where all the watchpoints watch | |
654 | the same address and the same region length: then we can handle a | |
655 | virtually unlimited number of watchpoints, due to debug register | |
656 | sharing implemented via reference counts. */ | |
9d19df75 MS |
657 | return 1; |
658 | } | |
659 | ||
0d5ed153 | 660 | /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address. |
9d19df75 MS |
661 | Return 0 on success, -1 on failure. */ |
662 | ||
f6ac5f3d PA |
663 | int |
664 | aarch64_linux_nat_target::insert_hw_breakpoint (struct gdbarch *gdbarch, | |
665 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
666 | { |
667 | int ret; | |
0d5ed153 | 668 | CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address; |
8d689ee5 | 669 | int len; |
2ecd81c2 | 670 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de YQ |
671 | struct aarch64_debug_reg_state *state |
672 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 | 673 | |
8d689ee5 YQ |
674 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
675 | ||
c5e92cca | 676 | if (show_debug_regs) |
9d19df75 MS |
677 | fprintf_unfiltered |
678 | (gdb_stdlog, | |
679 | "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
680 | (unsigned long) addr, len); | |
681 | ||
c67ca4de | 682 | ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 683 | |
c5e92cca | 684 | if (show_debug_regs) |
d6c44983 | 685 | { |
d6c44983 | 686 | aarch64_show_debug_reg_state (state, |
2fd0f80d | 687 | "insert_hw_breakpoint", addr, len, type); |
d6c44983 | 688 | } |
9d19df75 MS |
689 | |
690 | return ret; | |
691 | } | |
692 | ||
693 | /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address. | |
694 | Return 0 on success, -1 on failure. */ | |
695 | ||
f6ac5f3d PA |
696 | int |
697 | aarch64_linux_nat_target::remove_hw_breakpoint (struct gdbarch *gdbarch, | |
698 | struct bp_target_info *bp_tgt) | |
9d19df75 MS |
699 | { |
700 | int ret; | |
701 | CORE_ADDR addr = bp_tgt->placed_address; | |
8d689ee5 | 702 | int len = 4; |
2ecd81c2 | 703 | const enum target_hw_bp_type type = hw_execute; |
c67ca4de YQ |
704 | struct aarch64_debug_reg_state *state |
705 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 | 706 | |
8d689ee5 YQ |
707 | gdbarch_breakpoint_from_pc (gdbarch, &addr, &len); |
708 | ||
c5e92cca | 709 | if (show_debug_regs) |
9d19df75 MS |
710 | fprintf_unfiltered |
711 | (gdb_stdlog, "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n", | |
712 | (unsigned long) addr, len); | |
713 | ||
c67ca4de | 714 | ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 715 | |
c5e92cca | 716 | if (show_debug_regs) |
d6c44983 | 717 | { |
d6c44983 YZ |
718 | aarch64_show_debug_reg_state (state, |
719 | "remove_hw_watchpoint", addr, len, type); | |
720 | } | |
9d19df75 MS |
721 | |
722 | return ret; | |
723 | } | |
724 | ||
f6ac5f3d | 725 | /* Implement the "insert_watchpoint" target_ops method. |
9d19df75 MS |
726 | |
727 | Insert a watchpoint to watch a memory region which starts at | |
728 | address ADDR and whose length is LEN bytes. Watch memory accesses | |
729 | of the type TYPE. Return 0 on success, -1 on failure. */ | |
730 | ||
f6ac5f3d PA |
731 | int |
732 | aarch64_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len, | |
733 | enum target_hw_bp_type type, | |
734 | struct expression *cond) | |
9d19df75 MS |
735 | { |
736 | int ret; | |
c67ca4de YQ |
737 | struct aarch64_debug_reg_state *state |
738 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 | 739 | |
c5e92cca | 740 | if (show_debug_regs) |
9d19df75 MS |
741 | fprintf_unfiltered (gdb_stdlog, |
742 | "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
743 | (unsigned long) addr, len); | |
744 | ||
745 | gdb_assert (type != hw_execute); | |
746 | ||
c67ca4de | 747 | ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */, state); |
9d19df75 | 748 | |
c5e92cca | 749 | if (show_debug_regs) |
d6c44983 | 750 | { |
d6c44983 YZ |
751 | aarch64_show_debug_reg_state (state, |
752 | "insert_watchpoint", addr, len, type); | |
753 | } | |
9d19df75 MS |
754 | |
755 | return ret; | |
756 | } | |
757 | ||
f6ac5f3d | 758 | /* Implement the "remove_watchpoint" target_ops method. |
9d19df75 MS |
759 | Remove a watchpoint that watched the memory region which starts at |
760 | address ADDR, whose length is LEN bytes, and for accesses of the | |
761 | type TYPE. Return 0 on success, -1 on failure. */ | |
762 | ||
f6ac5f3d PA |
763 | int |
764 | aarch64_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len, | |
765 | enum target_hw_bp_type type, | |
766 | struct expression *cond) | |
9d19df75 MS |
767 | { |
768 | int ret; | |
c67ca4de YQ |
769 | struct aarch64_debug_reg_state *state |
770 | = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); | |
9d19df75 | 771 | |
c5e92cca | 772 | if (show_debug_regs) |
9d19df75 MS |
773 | fprintf_unfiltered (gdb_stdlog, |
774 | "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n", | |
775 | (unsigned long) addr, len); | |
776 | ||
777 | gdb_assert (type != hw_execute); | |
778 | ||
c67ca4de | 779 | ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */, state); |
9d19df75 | 780 | |
c5e92cca | 781 | if (show_debug_regs) |
d6c44983 | 782 | { |
d6c44983 YZ |
783 | aarch64_show_debug_reg_state (state, |
784 | "remove_watchpoint", addr, len, type); | |
785 | } | |
9d19df75 MS |
786 | |
787 | return ret; | |
788 | } | |
789 | ||
f6ac5f3d | 790 | /* Implement the "region_ok_for_hw_watchpoint" target_ops method. */ |
9d19df75 | 791 | |
f6ac5f3d PA |
792 | int |
793 | aarch64_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len) | |
9d19df75 | 794 | { |
39edd165 | 795 | return aarch64_linux_region_ok_for_watchpoint (addr, len); |
9d19df75 MS |
796 | } |
797 | ||
f6ac5f3d | 798 | /* Implement the "stopped_data_address" target_ops method. */ |
9d19df75 | 799 | |
57810aa7 | 800 | bool |
f6ac5f3d | 801 | aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p) |
9d19df75 MS |
802 | { |
803 | siginfo_t siginfo; | |
804 | int i, tid; | |
805 | struct aarch64_debug_reg_state *state; | |
806 | ||
807 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
57810aa7 | 808 | return false; |
9d19df75 MS |
809 | |
810 | /* This must be a hardware breakpoint. */ | |
811 | if (siginfo.si_signo != SIGTRAP | |
812 | || (siginfo.si_code & 0xffff) != TRAP_HWBKPT) | |
57810aa7 | 813 | return false; |
9d19df75 MS |
814 | |
815 | /* Check if the address matches any watched address. */ | |
d6c44983 | 816 | state = aarch64_get_debug_reg_state (ptid_get_pid (inferior_ptid)); |
9d19df75 MS |
817 | for (i = aarch64_num_wp_regs - 1; i >= 0; --i) |
818 | { | |
a3b60e45 JK |
819 | const unsigned int offset |
820 | = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]); | |
9d19df75 MS |
821 | const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]); |
822 | const CORE_ADDR addr_trap = (CORE_ADDR) siginfo.si_addr; | |
a3b60e45 JK |
823 | const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset; |
824 | const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8); | |
825 | const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i]; | |
9d19df75 MS |
826 | |
827 | if (state->dr_ref_count_wp[i] | |
828 | && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i]) | |
a3b60e45 | 829 | && addr_trap >= addr_watch_aligned |
9d19df75 MS |
830 | && addr_trap < addr_watch + len) |
831 | { | |
a3b60e45 JK |
832 | /* ADDR_TRAP reports the first address of the memory range |
833 | accessed by the CPU, regardless of what was the memory | |
834 | range watched. Thus, a large CPU access that straddles | |
835 | the ADDR_WATCH..ADDR_WATCH+LEN range may result in an | |
836 | ADDR_TRAP that is lower than the | |
837 | ADDR_WATCH..ADDR_WATCH+LEN range. E.g.: | |
838 | ||
839 | addr: | 4 | 5 | 6 | 7 | 8 | | |
840 | |---- range watched ----| | |
841 | |----------- range accessed ------------| | |
842 | ||
843 | In this case, ADDR_TRAP will be 4. | |
844 | ||
845 | To match a watchpoint known to GDB core, we must never | |
846 | report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN | |
847 | range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false | |
848 | positive on kernels older than 4.10. See PR | |
849 | external/20207. */ | |
850 | *addr_p = addr_orig; | |
57810aa7 | 851 | return true; |
9d19df75 MS |
852 | } |
853 | } | |
854 | ||
57810aa7 | 855 | return false; |
9d19df75 MS |
856 | } |
857 | ||
f6ac5f3d | 858 | /* Implement the "stopped_by_watchpoint" target_ops method. */ |
9d19df75 | 859 | |
57810aa7 | 860 | bool |
f6ac5f3d | 861 | aarch64_linux_nat_target::stopped_by_watchpoint () |
9d19df75 MS |
862 | { |
863 | CORE_ADDR addr; | |
864 | ||
f6ac5f3d | 865 | return stopped_data_address (&addr); |
9d19df75 MS |
866 | } |
867 | ||
f6ac5f3d | 868 | /* Implement the "watchpoint_addr_within_range" target_ops method. */ |
9d19df75 | 869 | |
57810aa7 | 870 | bool |
f6ac5f3d PA |
871 | aarch64_linux_nat_target::watchpoint_addr_within_range (CORE_ADDR addr, |
872 | CORE_ADDR start, int length) | |
9d19df75 MS |
873 | { |
874 | return start <= addr && start + length - 1 >= addr; | |
875 | } | |
876 | ||
f6ac5f3d | 877 | /* Implement the "can_do_single_step" target_ops method. */ |
750ce8d1 | 878 | |
f6ac5f3d PA |
879 | int |
880 | aarch64_linux_nat_target::can_do_single_step () | |
750ce8d1 YQ |
881 | { |
882 | return 1; | |
883 | } | |
884 | ||
9d19df75 MS |
885 | /* Define AArch64 maintenance commands. */ |
886 | ||
887 | static void | |
888 | add_show_debug_regs_command (void) | |
889 | { | |
890 | /* A maintenance command to enable printing the internal DRi mirror | |
891 | variables. */ | |
892 | add_setshow_boolean_cmd ("show-debug-regs", class_maintenance, | |
c5e92cca | 893 | &show_debug_regs, _("\ |
9d19df75 MS |
894 | Set whether to show variables that mirror the AArch64 debug registers."), _("\ |
895 | Show whether to show variables that mirror the AArch64 debug registers."), _("\ | |
896 | Use \"on\" to enable, \"off\" to disable.\n\ | |
897 | If enabled, the debug registers values are shown when GDB inserts\n\ | |
898 | or removes a hardware breakpoint or watchpoint, and when the inferior\n\ | |
899 | triggers a breakpoint or watchpoint."), | |
900 | NULL, | |
901 | NULL, | |
902 | &maintenance_set_cmdlist, | |
903 | &maintenance_show_cmdlist); | |
904 | } | |
905 | ||
9d19df75 MS |
906 | void |
907 | _initialize_aarch64_linux_nat (void) | |
908 | { | |
9d19df75 MS |
909 | add_show_debug_regs_command (); |
910 | ||
9d19df75 | 911 | /* Register the target. */ |
f6ac5f3d | 912 | linux_target = &the_aarch64_linux_nat_target; |
d9f719f1 | 913 | add_inf_child_target (&the_aarch64_linux_nat_target); |
9d19df75 | 914 | } |