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e8bf1ce4 JB |
1 | /* Ravenscar Aarch64 target support. |
2 | ||
1d506c26 | 3 | Copyright (C) 2017-2024 Free Software Foundation, Inc. |
e8bf1ce4 JB |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #include "defs.h" | |
d55e5aa6 | 21 | #include "gdbcore.h" |
4de283e4 TT |
22 | #include "regcache.h" |
23 | #include "aarch64-tdep.h" | |
e8bf1ce4 JB |
24 | #include "inferior.h" |
25 | #include "ravenscar-thread.h" | |
4de283e4 | 26 | #include "aarch64-ravenscar-thread.h" |
0d12e84c | 27 | #include "gdbarch.h" |
e8bf1ce4 JB |
28 | |
29 | #define NO_OFFSET -1 | |
30 | ||
31 | /* See aarch64-tdep.h for register numbers. */ | |
32 | ||
33 | static const int aarch64_context_offsets[] = | |
34 | { | |
35 | /* X0 - X28 */ | |
36 | NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, | |
37 | NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, | |
38 | NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, | |
39 | NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET, | |
40 | NO_OFFSET, NO_OFFSET, NO_OFFSET, 0, | |
41 | 8, 16, 24, 32, | |
42 | 40, 48, 56, 64, | |
43 | 72, | |
44 | ||
45 | /* FP, LR, SP, PC, CPSR */ | |
46 | /* Note that as task switch is synchronous, PC is in fact the LR here */ | |
47 | 80, 88, 96, 88, | |
48 | NO_OFFSET, | |
49 | ||
2808125f TT |
50 | /* V0 - V31 */ |
51 | 128, 144, 160, 176, | |
52 | 192, 208, 224, 240, | |
53 | 256, 272, 288, 304, | |
54 | 320, 336, 352, 368, | |
55 | 384, 400, 416, 432, | |
56 | 448, 464, 480, 496, | |
57 | 512, 528, 544, 560, | |
58 | 576, 592, 608, 624, | |
e8bf1ce4 JB |
59 | |
60 | /* FPSR, FPCR */ | |
2808125f | 61 | 112, 116, |
e8bf1ce4 JB |
62 | }; |
63 | ||
965b71a7 TT |
64 | #define V_INIT_OFFSET 640 |
65 | ||
e8bf1ce4 JB |
66 | /* The ravenscar_arch_ops vector for most Aarch64 targets. */ |
67 | ||
e73434e3 | 68 | static struct ravenscar_arch_ops aarch64_ravenscar_ops |
965b71a7 TT |
69 | (aarch64_context_offsets, |
70 | -1, -1, | |
71 | V_INIT_OFFSET, | |
72 | /* The FPU context buffer starts with the FPSR register. */ | |
73 | aarch64_context_offsets[AARCH64_FPSR_REGNUM], | |
74 | AARCH64_V0_REGNUM, AARCH64_FPCR_REGNUM); | |
e8bf1ce4 JB |
75 | |
76 | /* Register aarch64_ravenscar_ops in GDBARCH. */ | |
77 | ||
78 | void | |
79 | register_aarch64_ravenscar_ops (struct gdbarch *gdbarch) | |
80 | { | |
81 | set_gdbarch_ravenscar_ops (gdbarch, &aarch64_ravenscar_ops); | |
82 | } |