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07b287a0 MS |
1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
213516ef | 3 | Copyright (C) 2009-2023 Free Software Foundation, Inc. |
07b287a0 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "frame.h" | |
83b6e1f1 | 24 | #include "language.h" |
07b287a0 MS |
25 | #include "gdbcmd.h" |
26 | #include "gdbcore.h" | |
4de283e4 | 27 | #include "dis-asm.h" |
d55e5aa6 TT |
28 | #include "regcache.h" |
29 | #include "reggroups.h" | |
4de283e4 TT |
30 | #include "value.h" |
31 | #include "arch-utils.h" | |
32 | #include "osabi.h" | |
33 | #include "frame-unwind.h" | |
34 | #include "frame-base.h" | |
d55e5aa6 | 35 | #include "trad-frame.h" |
4de283e4 TT |
36 | #include "objfiles.h" |
37 | #include "dwarf2.h" | |
82ca8957 | 38 | #include "dwarf2/frame.h" |
4de283e4 TT |
39 | #include "gdbtypes.h" |
40 | #include "prologue-value.h" | |
41 | #include "target-descriptions.h" | |
07b287a0 | 42 | #include "user-regs.h" |
4de283e4 | 43 | #include "ax-gdb.h" |
268a13a5 | 44 | #include "gdbsupport/selftest.h" |
4de283e4 TT |
45 | |
46 | #include "aarch64-tdep.h" | |
47 | #include "aarch64-ravenscar-thread.h" | |
48 | ||
4de283e4 TT |
49 | #include "record.h" |
50 | #include "record-full.h" | |
51 | #include "arch/aarch64-insn.h" | |
0d12e84c | 52 | #include "gdbarch.h" |
4de283e4 TT |
53 | |
54 | #include "opcode/aarch64.h" | |
55 | #include <algorithm> | |
0ee6b1c5 | 56 | #include <unordered_map> |
f77ee802 | 57 | |
ef139898 LM |
58 | /* For inferior_ptid and current_inferior (). */ |
59 | #include "inferior.h" | |
60 | ||
ea92689a AH |
61 | /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most |
62 | four members. */ | |
63 | #define HA_MAX_NUM_FLDS 4 | |
64 | ||
95228a0d | 65 | /* All possible aarch64 target descriptors. */ |
0ee6b1c5 | 66 | static std::unordered_map <aarch64_features, target_desc *> tdesc_aarch64_map; |
95228a0d | 67 | |
ea2f6fad TV |
68 | /* The standard register names, and all the valid aliases for them. |
69 | We're not adding fp here, that name is already taken, see | |
70 | _initialize_frame_reg. */ | |
07b287a0 MS |
71 | static const struct |
72 | { | |
73 | const char *const name; | |
74 | int regnum; | |
75 | } aarch64_register_aliases[] = | |
76 | { | |
ea2f6fad | 77 | /* Link register alias for x30. */ |
07b287a0 | 78 | {"lr", AARCH64_LR_REGNUM}, |
ea2f6fad TV |
79 | /* SP is the canonical name for x31 according to aarch64_r_register_names, |
80 | so we're adding an x31 alias for sp. */ | |
81 | {"x31", AARCH64_SP_REGNUM}, | |
07b287a0 MS |
82 | /* specials */ |
83 | {"ip0", AARCH64_X0_REGNUM + 16}, | |
84 | {"ip1", AARCH64_X0_REGNUM + 17} | |
85 | }; | |
86 | ||
87 | /* The required core 'R' registers. */ | |
88 | static const char *const aarch64_r_register_names[] = | |
89 | { | |
90 | /* These registers must appear in consecutive RAW register number | |
91 | order and they must begin with AARCH64_X0_REGNUM! */ | |
92 | "x0", "x1", "x2", "x3", | |
93 | "x4", "x5", "x6", "x7", | |
94 | "x8", "x9", "x10", "x11", | |
95 | "x12", "x13", "x14", "x15", | |
96 | "x16", "x17", "x18", "x19", | |
97 | "x20", "x21", "x22", "x23", | |
98 | "x24", "x25", "x26", "x27", | |
99 | "x28", "x29", "x30", "sp", | |
100 | "pc", "cpsr" | |
101 | }; | |
102 | ||
103 | /* The FP/SIMD 'V' registers. */ | |
104 | static const char *const aarch64_v_register_names[] = | |
105 | { | |
106 | /* These registers must appear in consecutive RAW register number | |
107 | order and they must begin with AARCH64_V0_REGNUM! */ | |
108 | "v0", "v1", "v2", "v3", | |
109 | "v4", "v5", "v6", "v7", | |
110 | "v8", "v9", "v10", "v11", | |
111 | "v12", "v13", "v14", "v15", | |
112 | "v16", "v17", "v18", "v19", | |
113 | "v20", "v21", "v22", "v23", | |
114 | "v24", "v25", "v26", "v27", | |
115 | "v28", "v29", "v30", "v31", | |
116 | "fpsr", | |
117 | "fpcr" | |
118 | }; | |
119 | ||
739e8682 AH |
120 | /* The SVE 'Z' and 'P' registers. */ |
121 | static const char *const aarch64_sve_register_names[] = | |
122 | { | |
123 | /* These registers must appear in consecutive RAW register number | |
124 | order and they must begin with AARCH64_SVE_Z0_REGNUM! */ | |
125 | "z0", "z1", "z2", "z3", | |
126 | "z4", "z5", "z6", "z7", | |
127 | "z8", "z9", "z10", "z11", | |
128 | "z12", "z13", "z14", "z15", | |
129 | "z16", "z17", "z18", "z19", | |
130 | "z20", "z21", "z22", "z23", | |
131 | "z24", "z25", "z26", "z27", | |
132 | "z28", "z29", "z30", "z31", | |
133 | "fpsr", "fpcr", | |
134 | "p0", "p1", "p2", "p3", | |
135 | "p4", "p5", "p6", "p7", | |
136 | "p8", "p9", "p10", "p11", | |
137 | "p12", "p13", "p14", "p15", | |
138 | "ffr", "vg" | |
139 | }; | |
140 | ||
76bed0fd AH |
141 | static const char *const aarch64_pauth_register_names[] = |
142 | { | |
6d002087 | 143 | /* Authentication mask for data pointer, low half/user pointers. */ |
76bed0fd | 144 | "pauth_dmask", |
6d002087 LM |
145 | /* Authentication mask for code pointer, low half/user pointers. */ |
146 | "pauth_cmask", | |
147 | /* Authentication mask for data pointer, high half / kernel pointers. */ | |
148 | "pauth_dmask_high", | |
149 | /* Authentication mask for code pointer, high half / kernel pointers. */ | |
150 | "pauth_cmask_high" | |
76bed0fd AH |
151 | }; |
152 | ||
5e984dbf LM |
153 | static const char *const aarch64_mte_register_names[] = |
154 | { | |
155 | /* Tag Control Register. */ | |
156 | "tag_ctl" | |
157 | }; | |
158 | ||
29e09a42 TV |
159 | static int aarch64_stack_frame_destroyed_p (struct gdbarch *, CORE_ADDR); |
160 | ||
07b287a0 MS |
161 | /* AArch64 prologue cache structure. */ |
162 | struct aarch64_prologue_cache | |
163 | { | |
db634143 PL |
164 | /* The program counter at the start of the function. It is used to |
165 | identify this frame as a prologue frame. */ | |
166 | CORE_ADDR func; | |
167 | ||
168 | /* The program counter at the time this frame was created; i.e. where | |
169 | this function was called from. It is used to identify this frame as a | |
170 | stub frame. */ | |
171 | CORE_ADDR prev_pc; | |
172 | ||
07b287a0 MS |
173 | /* The stack pointer at the time this frame was created; i.e. the |
174 | caller's stack pointer when this function was called. It is used | |
175 | to identify this frame. */ | |
176 | CORE_ADDR prev_sp; | |
177 | ||
7dfa3edc PL |
178 | /* Is the target available to read from? */ |
179 | int available_p; | |
180 | ||
07b287a0 MS |
181 | /* The frame base for this frame is just prev_sp - frame size. |
182 | FRAMESIZE is the distance from the frame pointer to the | |
183 | initial stack pointer. */ | |
184 | int framesize; | |
185 | ||
186 | /* The register used to hold the frame pointer for this frame. */ | |
187 | int framereg; | |
188 | ||
189 | /* Saved register offsets. */ | |
098caef4 | 190 | trad_frame_saved_reg *saved_regs; |
07b287a0 MS |
191 | }; |
192 | ||
07b287a0 MS |
193 | static void |
194 | show_aarch64_debug (struct ui_file *file, int from_tty, | |
dda83cd7 | 195 | struct cmd_list_element *c, const char *value) |
07b287a0 | 196 | { |
6cb06a8c | 197 | gdb_printf (file, _("AArch64 debugging is %s.\n"), value); |
07b287a0 MS |
198 | } |
199 | ||
ffdbe864 YQ |
200 | namespace { |
201 | ||
4d9a9006 YQ |
202 | /* Abstract instruction reader. */ |
203 | ||
204 | class abstract_instruction_reader | |
205 | { | |
206 | public: | |
207 | /* Read in one instruction. */ | |
208 | virtual ULONGEST read (CORE_ADDR memaddr, int len, | |
209 | enum bfd_endian byte_order) = 0; | |
210 | }; | |
211 | ||
212 | /* Instruction reader from real target. */ | |
213 | ||
214 | class instruction_reader : public abstract_instruction_reader | |
215 | { | |
216 | public: | |
217 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
632e107b | 218 | override |
4d9a9006 | 219 | { |
fc2f703e | 220 | return read_code_unsigned_integer (memaddr, len, byte_order); |
4d9a9006 YQ |
221 | } |
222 | }; | |
223 | ||
ffdbe864 YQ |
224 | } // namespace |
225 | ||
3d31bc39 AH |
226 | /* If address signing is enabled, mask off the signature bits from the link |
227 | register, which is passed by value in ADDR, using the register values in | |
228 | THIS_FRAME. */ | |
11e1b75f AH |
229 | |
230 | static CORE_ADDR | |
345bd07c | 231 | aarch64_frame_unmask_lr (aarch64_gdbarch_tdep *tdep, |
bd2b40ac | 232 | frame_info_ptr this_frame, CORE_ADDR addr) |
11e1b75f AH |
233 | { |
234 | if (tdep->has_pauth () | |
235 | && frame_unwind_register_unsigned (this_frame, | |
c9cd8ca4 | 236 | tdep->ra_sign_state_regnum)) |
11e1b75f | 237 | { |
6d002087 LM |
238 | /* VA range select (bit 55) tells us whether to use the low half masks |
239 | or the high half masks. */ | |
240 | int cmask_num; | |
241 | if (tdep->pauth_reg_count > 2 && addr & VA_RANGE_SELECT_BIT_MASK) | |
242 | cmask_num = AARCH64_PAUTH_CMASK_HIGH_REGNUM (tdep->pauth_reg_base); | |
243 | else | |
244 | cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base); | |
245 | ||
246 | /* By default, we assume TBI and discard the top 8 bits plus the VA range | |
247 | select bit (55). */ | |
248 | CORE_ADDR mask = AARCH64_TOP_BITS_MASK; | |
249 | mask |= frame_unwind_register_unsigned (this_frame, cmask_num); | |
250 | addr = aarch64_remove_top_bits (addr, mask); | |
3d31bc39 AH |
251 | |
252 | /* Record in the frame that the link register required unmasking. */ | |
253 | set_frame_previous_pc_masked (this_frame); | |
11e1b75f AH |
254 | } |
255 | ||
256 | return addr; | |
257 | } | |
258 | ||
aa7ca1bb AH |
259 | /* Implement the "get_pc_address_flags" gdbarch method. */ |
260 | ||
261 | static std::string | |
bd2b40ac | 262 | aarch64_get_pc_address_flags (frame_info_ptr frame, CORE_ADDR pc) |
aa7ca1bb AH |
263 | { |
264 | if (pc != 0 && get_frame_pc_masked (frame)) | |
265 | return "PAC"; | |
266 | ||
267 | return ""; | |
268 | } | |
269 | ||
07b287a0 MS |
270 | /* Analyze a prologue, looking for a recognizable stack frame |
271 | and frame pointer. Scan until we encounter a store that could | |
272 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
273 | ||
274 | static CORE_ADDR | |
275 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
276 | CORE_ADDR start, CORE_ADDR limit, | |
4d9a9006 YQ |
277 | struct aarch64_prologue_cache *cache, |
278 | abstract_instruction_reader& reader) | |
07b287a0 MS |
279 | { |
280 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
281 | int i; | |
f8e3fe0d LM |
282 | |
283 | /* Whether the stack has been set. This should be true when we notice a SP | |
284 | to FP move or if we are using the SP as the base register for storing | |
33b5899f | 285 | data, in case the FP is omitted. */ |
f8e3fe0d LM |
286 | bool seen_stack_set = false; |
287 | ||
187f5d00 YQ |
288 | /* Track X registers and D registers in prologue. */ |
289 | pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT]; | |
07b287a0 | 290 | |
187f5d00 | 291 | for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++) |
07b287a0 | 292 | regs[i] = pv_register (i, 0); |
f7b7ed97 | 293 | pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
07b287a0 MS |
294 | |
295 | for (; start < limit; start += 4) | |
296 | { | |
297 | uint32_t insn; | |
d9ebcbce | 298 | aarch64_inst inst; |
07b287a0 | 299 | |
4d9a9006 | 300 | insn = reader.read (start, 4, byte_order_for_code); |
07b287a0 | 301 | |
561a72d4 | 302 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
d9ebcbce YQ |
303 | break; |
304 | ||
305 | if (inst.opcode->iclass == addsub_imm | |
306 | && (inst.opcode->op == OP_ADD | |
307 | || strcmp ("sub", inst.opcode->name) == 0)) | |
07b287a0 | 308 | { |
d9ebcbce YQ |
309 | unsigned rd = inst.operands[0].reg.regno; |
310 | unsigned rn = inst.operands[1].reg.regno; | |
311 | ||
312 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 3); | |
313 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP); | |
314 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP); | |
315 | gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM); | |
316 | ||
317 | if (inst.opcode->op == OP_ADD) | |
318 | { | |
319 | regs[rd] = pv_add_constant (regs[rn], | |
320 | inst.operands[2].imm.value); | |
321 | } | |
322 | else | |
323 | { | |
324 | regs[rd] = pv_add_constant (regs[rn], | |
325 | -inst.operands[2].imm.value); | |
326 | } | |
f8e3fe0d LM |
327 | |
328 | /* Did we move SP to FP? */ | |
329 | if (rn == AARCH64_SP_REGNUM && rd == AARCH64_FP_REGNUM) | |
330 | seen_stack_set = true; | |
d9ebcbce | 331 | } |
60adf22c TV |
332 | else if (inst.opcode->iclass == addsub_ext |
333 | && strcmp ("sub", inst.opcode->name) == 0) | |
334 | { | |
335 | unsigned rd = inst.operands[0].reg.regno; | |
336 | unsigned rn = inst.operands[1].reg.regno; | |
337 | unsigned rm = inst.operands[2].reg.regno; | |
338 | ||
339 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 3); | |
340 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP); | |
341 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP); | |
342 | gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_EXT); | |
343 | ||
344 | regs[rd] = pv_subtract (regs[rn], regs[rm]); | |
345 | } | |
d9ebcbce | 346 | else if (inst.opcode->iclass == branch_imm) |
07b287a0 MS |
347 | { |
348 | /* Stop analysis on branch. */ | |
349 | break; | |
350 | } | |
d9ebcbce | 351 | else if (inst.opcode->iclass == condbranch) |
07b287a0 MS |
352 | { |
353 | /* Stop analysis on branch. */ | |
354 | break; | |
355 | } | |
d9ebcbce | 356 | else if (inst.opcode->iclass == branch_reg) |
07b287a0 MS |
357 | { |
358 | /* Stop analysis on branch. */ | |
359 | break; | |
360 | } | |
d9ebcbce | 361 | else if (inst.opcode->iclass == compbranch) |
07b287a0 MS |
362 | { |
363 | /* Stop analysis on branch. */ | |
364 | break; | |
365 | } | |
d9ebcbce YQ |
366 | else if (inst.opcode->op == OP_MOVZ) |
367 | { | |
60adf22c TV |
368 | unsigned rd = inst.operands[0].reg.regno; |
369 | ||
370 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
d9ebcbce | 371 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); |
60adf22c TV |
372 | gdb_assert (inst.operands[1].type == AARCH64_OPND_HALF); |
373 | gdb_assert (inst.operands[1].shifter.kind == AARCH64_MOD_LSL); | |
f8e3fe0d LM |
374 | |
375 | /* If this shows up before we set the stack, keep going. Otherwise | |
376 | stop the analysis. */ | |
377 | if (seen_stack_set) | |
378 | break; | |
379 | ||
60adf22c TV |
380 | regs[rd] = pv_constant (inst.operands[1].imm.value |
381 | << inst.operands[1].shifter.amount); | |
d9ebcbce YQ |
382 | } |
383 | else if (inst.opcode->iclass == log_shift | |
384 | && strcmp (inst.opcode->name, "orr") == 0) | |
07b287a0 | 385 | { |
d9ebcbce YQ |
386 | unsigned rd = inst.operands[0].reg.regno; |
387 | unsigned rn = inst.operands[1].reg.regno; | |
388 | unsigned rm = inst.operands[2].reg.regno; | |
389 | ||
390 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
391 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn); | |
392 | gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT); | |
393 | ||
394 | if (inst.operands[2].shifter.amount == 0 | |
395 | && rn == AARCH64_SP_REGNUM) | |
07b287a0 MS |
396 | regs[rd] = regs[rm]; |
397 | else | |
398 | { | |
c6185dce SM |
399 | aarch64_debug_printf ("prologue analysis gave up " |
400 | "addr=%s opcode=0x%x (orr x register)", | |
401 | core_addr_to_string_nz (start), insn); | |
402 | ||
07b287a0 MS |
403 | break; |
404 | } | |
405 | } | |
d9ebcbce | 406 | else if (inst.opcode->op == OP_STUR) |
07b287a0 | 407 | { |
d9ebcbce YQ |
408 | unsigned rt = inst.operands[0].reg.regno; |
409 | unsigned rn = inst.operands[1].addr.base_regno; | |
75faf5c4 | 410 | int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); |
d9ebcbce YQ |
411 | |
412 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
413 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt); | |
414 | gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9); | |
415 | gdb_assert (!inst.operands[1].addr.offset.is_reg); | |
416 | ||
75faf5c4 AH |
417 | stack.store |
418 | (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), | |
419 | size, regs[rt]); | |
f8e3fe0d LM |
420 | |
421 | /* Are we storing with SP as a base? */ | |
422 | if (rn == AARCH64_SP_REGNUM) | |
423 | seen_stack_set = true; | |
07b287a0 | 424 | } |
d9ebcbce | 425 | else if ((inst.opcode->iclass == ldstpair_off |
03bcd739 YQ |
426 | || (inst.opcode->iclass == ldstpair_indexed |
427 | && inst.operands[2].addr.preind)) | |
d9ebcbce | 428 | && strcmp ("stp", inst.opcode->name) == 0) |
07b287a0 | 429 | { |
03bcd739 | 430 | /* STP with addressing mode Pre-indexed and Base register. */ |
187f5d00 YQ |
431 | unsigned rt1; |
432 | unsigned rt2; | |
d9ebcbce YQ |
433 | unsigned rn = inst.operands[2].addr.base_regno; |
434 | int32_t imm = inst.operands[2].addr.offset.imm; | |
75faf5c4 | 435 | int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); |
d9ebcbce | 436 | |
187f5d00 YQ |
437 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt |
438 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
439 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2 | |
440 | || inst.operands[1].type == AARCH64_OPND_Ft2); | |
d9ebcbce YQ |
441 | gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7); |
442 | gdb_assert (!inst.operands[2].addr.offset.is_reg); | |
443 | ||
07b287a0 MS |
444 | /* If recording this store would invalidate the store area |
445 | (perhaps because rn is not known) then we should abandon | |
446 | further prologue analysis. */ | |
f7b7ed97 | 447 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm))) |
07b287a0 MS |
448 | break; |
449 | ||
f7b7ed97 | 450 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8))) |
07b287a0 MS |
451 | break; |
452 | ||
187f5d00 YQ |
453 | rt1 = inst.operands[0].reg.regno; |
454 | rt2 = inst.operands[1].reg.regno; | |
455 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
456 | { | |
187f5d00 YQ |
457 | rt1 += AARCH64_X_REGISTER_COUNT; |
458 | rt2 += AARCH64_X_REGISTER_COUNT; | |
459 | } | |
460 | ||
75faf5c4 AH |
461 | stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]); |
462 | stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]); | |
14ac654f | 463 | |
d9ebcbce | 464 | if (inst.operands[2].addr.writeback) |
93d96012 | 465 | regs[rn] = pv_add_constant (regs[rn], imm); |
07b287a0 | 466 | |
f8e3fe0d LM |
467 | /* Ignore the instruction that allocates stack space and sets |
468 | the SP. */ | |
469 | if (rn == AARCH64_SP_REGNUM && !inst.operands[2].addr.writeback) | |
470 | seen_stack_set = true; | |
07b287a0 | 471 | } |
432ec081 YQ |
472 | else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ |
473 | || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ | |
474 | && (inst.opcode->op == OP_STR_POS | |
475 | || inst.opcode->op == OP_STRF_POS))) | |
476 | && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM | |
477 | && strcmp ("str", inst.opcode->name) == 0) | |
478 | { | |
479 | /* STR (immediate) */ | |
480 | unsigned int rt = inst.operands[0].reg.regno; | |
481 | int32_t imm = inst.operands[1].addr.offset.imm; | |
482 | unsigned int rn = inst.operands[1].addr.base_regno; | |
75faf5c4 | 483 | int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); |
432ec081 YQ |
484 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt |
485 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
486 | ||
487 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
75faf5c4 | 488 | rt += AARCH64_X_REGISTER_COUNT; |
432ec081 | 489 | |
75faf5c4 | 490 | stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]); |
432ec081 YQ |
491 | if (inst.operands[1].addr.writeback) |
492 | regs[rn] = pv_add_constant (regs[rn], imm); | |
f8e3fe0d LM |
493 | |
494 | /* Are we storing with SP as a base? */ | |
495 | if (rn == AARCH64_SP_REGNUM) | |
496 | seen_stack_set = true; | |
432ec081 | 497 | } |
d9ebcbce | 498 | else if (inst.opcode->iclass == testbranch) |
07b287a0 MS |
499 | { |
500 | /* Stop analysis on branch. */ | |
501 | break; | |
502 | } | |
17e116a7 AH |
503 | else if (inst.opcode->iclass == ic_system) |
504 | { | |
345bd07c | 505 | aarch64_gdbarch_tdep *tdep |
08106042 | 506 | = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
17e116a7 AH |
507 | int ra_state_val = 0; |
508 | ||
509 | if (insn == 0xd503233f /* paciasp. */ | |
510 | || insn == 0xd503237f /* pacibsp. */) | |
511 | { | |
512 | /* Return addresses are mangled. */ | |
513 | ra_state_val = 1; | |
514 | } | |
515 | else if (insn == 0xd50323bf /* autiasp. */ | |
516 | || insn == 0xd50323ff /* autibsp. */) | |
517 | { | |
518 | /* Return addresses are not mangled. */ | |
519 | ra_state_val = 0; | |
520 | } | |
37989733 LM |
521 | else if (IS_BTI (insn)) |
522 | /* We don't need to do anything special for a BTI instruction. */ | |
523 | continue; | |
17e116a7 AH |
524 | else |
525 | { | |
c6185dce SM |
526 | aarch64_debug_printf ("prologue analysis gave up addr=%s" |
527 | " opcode=0x%x (iclass)", | |
528 | core_addr_to_string_nz (start), insn); | |
17e116a7 AH |
529 | break; |
530 | } | |
531 | ||
532 | if (tdep->has_pauth () && cache != nullptr) | |
a9a87d35 | 533 | { |
c9cd8ca4 | 534 | int regnum = tdep->ra_sign_state_regnum; |
a9a87d35 LM |
535 | cache->saved_regs[regnum].set_value (ra_state_val); |
536 | } | |
17e116a7 | 537 | } |
07b287a0 MS |
538 | else |
539 | { | |
c6185dce SM |
540 | aarch64_debug_printf ("prologue analysis gave up addr=%s" |
541 | " opcode=0x%x", | |
542 | core_addr_to_string_nz (start), insn); | |
543 | ||
07b287a0 MS |
544 | break; |
545 | } | |
546 | } | |
547 | ||
548 | if (cache == NULL) | |
f7b7ed97 | 549 | return start; |
07b287a0 MS |
550 | |
551 | if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM)) | |
552 | { | |
553 | /* Frame pointer is fp. Frame size is constant. */ | |
554 | cache->framereg = AARCH64_FP_REGNUM; | |
555 | cache->framesize = -regs[AARCH64_FP_REGNUM].k; | |
556 | } | |
557 | else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM)) | |
558 | { | |
559 | /* Try the stack pointer. */ | |
560 | cache->framesize = -regs[AARCH64_SP_REGNUM].k; | |
561 | cache->framereg = AARCH64_SP_REGNUM; | |
562 | } | |
563 | else | |
564 | { | |
565 | /* We're just out of luck. We don't know where the frame is. */ | |
566 | cache->framereg = -1; | |
567 | cache->framesize = 0; | |
568 | } | |
569 | ||
570 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
571 | { | |
572 | CORE_ADDR offset; | |
573 | ||
f7b7ed97 | 574 | if (stack.find_reg (gdbarch, i, &offset)) |
098caef4 | 575 | cache->saved_regs[i].set_addr (offset); |
07b287a0 MS |
576 | } |
577 | ||
187f5d00 YQ |
578 | for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++) |
579 | { | |
580 | int regnum = gdbarch_num_regs (gdbarch); | |
581 | CORE_ADDR offset; | |
582 | ||
f7b7ed97 TT |
583 | if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT, |
584 | &offset)) | |
098caef4 | 585 | cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].set_addr (offset); |
187f5d00 YQ |
586 | } |
587 | ||
07b287a0 MS |
588 | return start; |
589 | } | |
590 | ||
4d9a9006 YQ |
591 | static CORE_ADDR |
592 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
593 | CORE_ADDR start, CORE_ADDR limit, | |
594 | struct aarch64_prologue_cache *cache) | |
595 | { | |
596 | instruction_reader reader; | |
597 | ||
598 | return aarch64_analyze_prologue (gdbarch, start, limit, cache, | |
599 | reader); | |
600 | } | |
601 | ||
602 | #if GDB_SELF_TEST | |
603 | ||
604 | namespace selftests { | |
605 | ||
606 | /* Instruction reader from manually cooked instruction sequences. */ | |
607 | ||
608 | class instruction_reader_test : public abstract_instruction_reader | |
609 | { | |
610 | public: | |
611 | template<size_t SIZE> | |
612 | explicit instruction_reader_test (const uint32_t (&insns)[SIZE]) | |
613 | : m_insns (insns), m_insns_size (SIZE) | |
614 | {} | |
615 | ||
616 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
632e107b | 617 | override |
4d9a9006 YQ |
618 | { |
619 | SELF_CHECK (len == 4); | |
620 | SELF_CHECK (memaddr % 4 == 0); | |
621 | SELF_CHECK (memaddr / 4 < m_insns_size); | |
622 | ||
623 | return m_insns[memaddr / 4]; | |
624 | } | |
625 | ||
626 | private: | |
627 | const uint32_t *m_insns; | |
628 | size_t m_insns_size; | |
629 | }; | |
630 | ||
631 | static void | |
632 | aarch64_analyze_prologue_test (void) | |
633 | { | |
634 | struct gdbarch_info info; | |
635 | ||
4d9a9006 YQ |
636 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); |
637 | ||
638 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
639 | SELF_CHECK (gdbarch != NULL); | |
640 | ||
17e116a7 AH |
641 | struct aarch64_prologue_cache cache; |
642 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
643 | ||
08106042 | 644 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
17e116a7 | 645 | |
4d9a9006 YQ |
646 | /* Test the simple prologue in which frame pointer is used. */ |
647 | { | |
4d9a9006 YQ |
648 | static const uint32_t insns[] = { |
649 | 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */ | |
650 | 0x910003fd, /* mov x29, sp */ | |
651 | 0x97ffffe6, /* bl 0x400580 */ | |
652 | }; | |
653 | instruction_reader_test reader (insns); | |
654 | ||
655 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
656 | SELF_CHECK (end == 4 * 2); | |
657 | ||
658 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
659 | SELF_CHECK (cache.framesize == 272); | |
660 | ||
661 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
662 | { | |
663 | if (i == AARCH64_FP_REGNUM) | |
098caef4 | 664 | SELF_CHECK (cache.saved_regs[i].addr () == -272); |
4d9a9006 | 665 | else if (i == AARCH64_LR_REGNUM) |
098caef4 | 666 | SELF_CHECK (cache.saved_regs[i].addr () == -264); |
4d9a9006 | 667 | else |
a9a87d35 LM |
668 | SELF_CHECK (cache.saved_regs[i].is_realreg () |
669 | && cache.saved_regs[i].realreg () == i); | |
4d9a9006 YQ |
670 | } |
671 | ||
672 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
673 | { | |
a9a87d35 LM |
674 | int num_regs = gdbarch_num_regs (gdbarch); |
675 | int regnum = i + num_regs + AARCH64_D0_REGNUM; | |
4d9a9006 | 676 | |
a9a87d35 LM |
677 | SELF_CHECK (cache.saved_regs[regnum].is_realreg () |
678 | && cache.saved_regs[regnum].realreg () == regnum); | |
4d9a9006 YQ |
679 | } |
680 | } | |
432ec081 YQ |
681 | |
682 | /* Test a prologue in which STR is used and frame pointer is not | |
683 | used. */ | |
684 | { | |
432ec081 YQ |
685 | static const uint32_t insns[] = { |
686 | 0xf81d0ff3, /* str x19, [sp, #-48]! */ | |
687 | 0xb9002fe0, /* str w0, [sp, #44] */ | |
688 | 0xf90013e1, /* str x1, [sp, #32]*/ | |
689 | 0xfd000fe0, /* str d0, [sp, #24] */ | |
690 | 0xaa0203f3, /* mov x19, x2 */ | |
691 | 0xf94013e0, /* ldr x0, [sp, #32] */ | |
692 | }; | |
693 | instruction_reader_test reader (insns); | |
694 | ||
68811f8f | 695 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); |
432ec081 YQ |
696 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); |
697 | ||
698 | SELF_CHECK (end == 4 * 5); | |
699 | ||
700 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
701 | SELF_CHECK (cache.framesize == 48); | |
702 | ||
703 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
704 | { | |
705 | if (i == 1) | |
098caef4 | 706 | SELF_CHECK (cache.saved_regs[i].addr () == -16); |
432ec081 | 707 | else if (i == 19) |
098caef4 | 708 | SELF_CHECK (cache.saved_regs[i].addr () == -48); |
432ec081 | 709 | else |
a9a87d35 LM |
710 | SELF_CHECK (cache.saved_regs[i].is_realreg () |
711 | && cache.saved_regs[i].realreg () == i); | |
432ec081 YQ |
712 | } |
713 | ||
714 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
715 | { | |
a9a87d35 LM |
716 | int num_regs = gdbarch_num_regs (gdbarch); |
717 | int regnum = i + num_regs + AARCH64_D0_REGNUM; | |
718 | ||
432ec081 YQ |
719 | |
720 | if (i == 0) | |
a9a87d35 | 721 | SELF_CHECK (cache.saved_regs[regnum].addr () == -24); |
432ec081 | 722 | else |
a9a87d35 LM |
723 | SELF_CHECK (cache.saved_regs[regnum].is_realreg () |
724 | && cache.saved_regs[regnum].realreg () == regnum); | |
432ec081 YQ |
725 | } |
726 | } | |
17e116a7 | 727 | |
f8e3fe0d LM |
728 | /* Test handling of movz before setting the frame pointer. */ |
729 | { | |
730 | static const uint32_t insns[] = { | |
731 | 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */ | |
732 | 0x52800020, /* mov w0, #0x1 */ | |
733 | 0x910003fd, /* mov x29, sp */ | |
734 | 0x528000a2, /* mov w2, #0x5 */ | |
735 | 0x97fffff8, /* bl 6e4 */ | |
736 | }; | |
737 | ||
738 | instruction_reader_test reader (insns); | |
739 | ||
740 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
741 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
742 | ||
743 | /* We should stop at the 4th instruction. */ | |
744 | SELF_CHECK (end == (4 - 1) * 4); | |
745 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
746 | SELF_CHECK (cache.framesize == 16); | |
747 | } | |
748 | ||
749 | /* Test handling of movz/stp when using the stack pointer as frame | |
750 | pointer. */ | |
751 | { | |
752 | static const uint32_t insns[] = { | |
753 | 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */ | |
754 | 0x52800020, /* mov w0, #0x1 */ | |
755 | 0x290207e0, /* stp w0, w1, [sp, #16] */ | |
756 | 0xa9018fe2, /* stp x2, x3, [sp, #24] */ | |
757 | 0x528000a2, /* mov w2, #0x5 */ | |
758 | 0x97fffff8, /* bl 6e4 */ | |
759 | }; | |
760 | ||
761 | instruction_reader_test reader (insns); | |
762 | ||
763 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
764 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
765 | ||
766 | /* We should stop at the 5th instruction. */ | |
767 | SELF_CHECK (end == (5 - 1) * 4); | |
768 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
769 | SELF_CHECK (cache.framesize == 64); | |
770 | } | |
771 | ||
772 | /* Test handling of movz/str when using the stack pointer as frame | |
773 | pointer */ | |
774 | { | |
775 | static const uint32_t insns[] = { | |
776 | 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */ | |
777 | 0x52800020, /* mov w0, #0x1 */ | |
778 | 0xb9002be4, /* str w4, [sp, #40] */ | |
779 | 0xf9001be5, /* str x5, [sp, #48] */ | |
780 | 0x528000a2, /* mov w2, #0x5 */ | |
781 | 0x97fffff8, /* bl 6e4 */ | |
782 | }; | |
783 | ||
784 | instruction_reader_test reader (insns); | |
785 | ||
786 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
787 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
788 | ||
789 | /* We should stop at the 5th instruction. */ | |
790 | SELF_CHECK (end == (5 - 1) * 4); | |
791 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
792 | SELF_CHECK (cache.framesize == 64); | |
793 | } | |
794 | ||
795 | /* Test handling of movz/stur when using the stack pointer as frame | |
796 | pointer. */ | |
797 | { | |
798 | static const uint32_t insns[] = { | |
799 | 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */ | |
800 | 0x52800020, /* mov w0, #0x1 */ | |
801 | 0xb80343e6, /* stur w6, [sp, #52] */ | |
802 | 0xf80383e7, /* stur x7, [sp, #56] */ | |
803 | 0x528000a2, /* mov w2, #0x5 */ | |
804 | 0x97fffff8, /* bl 6e4 */ | |
805 | }; | |
806 | ||
807 | instruction_reader_test reader (insns); | |
808 | ||
809 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
810 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
811 | ||
812 | /* We should stop at the 5th instruction. */ | |
813 | SELF_CHECK (end == (5 - 1) * 4); | |
814 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
815 | SELF_CHECK (cache.framesize == 64); | |
816 | } | |
817 | ||
818 | /* Test handling of movz when there is no frame pointer set or no stack | |
819 | pointer used. */ | |
820 | { | |
821 | static const uint32_t insns[] = { | |
822 | 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */ | |
823 | 0x52800020, /* mov w0, #0x1 */ | |
824 | 0x528000a2, /* mov w2, #0x5 */ | |
825 | 0x97fffff8, /* bl 6e4 */ | |
826 | }; | |
827 | ||
828 | instruction_reader_test reader (insns); | |
829 | ||
830 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
831 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
832 | ||
833 | /* We should stop at the 4th instruction. */ | |
834 | SELF_CHECK (end == (4 - 1) * 4); | |
835 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
836 | SELF_CHECK (cache.framesize == 16); | |
837 | } | |
838 | ||
17e116a7 AH |
839 | /* Test a prologue in which there is a return address signing instruction. */ |
840 | if (tdep->has_pauth ()) | |
841 | { | |
842 | static const uint32_t insns[] = { | |
843 | 0xd503233f, /* paciasp */ | |
844 | 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */ | |
845 | 0x910003fd, /* mov x29, sp */ | |
846 | 0xf801c3f3, /* str x19, [sp, #28] */ | |
847 | 0xb9401fa0, /* ldr x19, [x29, #28] */ | |
848 | }; | |
849 | instruction_reader_test reader (insns); | |
850 | ||
68811f8f | 851 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); |
17e116a7 AH |
852 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, |
853 | reader); | |
854 | ||
855 | SELF_CHECK (end == 4 * 4); | |
856 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
857 | SELF_CHECK (cache.framesize == 48); | |
858 | ||
859 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
860 | { | |
861 | if (i == 19) | |
098caef4 | 862 | SELF_CHECK (cache.saved_regs[i].addr () == -20); |
17e116a7 | 863 | else if (i == AARCH64_FP_REGNUM) |
098caef4 | 864 | SELF_CHECK (cache.saved_regs[i].addr () == -48); |
17e116a7 | 865 | else if (i == AARCH64_LR_REGNUM) |
098caef4 | 866 | SELF_CHECK (cache.saved_regs[i].addr () == -40); |
17e116a7 | 867 | else |
a9a87d35 LM |
868 | SELF_CHECK (cache.saved_regs[i].is_realreg () |
869 | && cache.saved_regs[i].realreg () == i); | |
17e116a7 AH |
870 | } |
871 | ||
872 | if (tdep->has_pauth ()) | |
873 | { | |
c9cd8ca4 | 874 | int regnum = tdep->ra_sign_state_regnum; |
a9a87d35 | 875 | SELF_CHECK (cache.saved_regs[regnum].is_value ()); |
17e116a7 AH |
876 | } |
877 | } | |
37989733 LM |
878 | |
879 | /* Test a prologue with a BTI instruction. */ | |
880 | { | |
881 | static const uint32_t insns[] = { | |
882 | 0xd503245f, /* bti */ | |
883 | 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */ | |
884 | 0x910003fd, /* mov x29, sp */ | |
885 | 0xf801c3f3, /* str x19, [sp, #28] */ | |
886 | 0xb9401fa0, /* ldr x19, [x29, #28] */ | |
887 | }; | |
888 | instruction_reader_test reader (insns); | |
889 | ||
890 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
891 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, | |
892 | reader); | |
893 | ||
894 | SELF_CHECK (end == 4 * 4); | |
895 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
896 | SELF_CHECK (cache.framesize == 48); | |
897 | ||
898 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
899 | { | |
900 | if (i == 19) | |
901 | SELF_CHECK (cache.saved_regs[i].addr () == -20); | |
902 | else if (i == AARCH64_FP_REGNUM) | |
903 | SELF_CHECK (cache.saved_regs[i].addr () == -48); | |
904 | else if (i == AARCH64_LR_REGNUM) | |
905 | SELF_CHECK (cache.saved_regs[i].addr () == -40); | |
906 | else | |
907 | SELF_CHECK (cache.saved_regs[i].is_realreg () | |
908 | && cache.saved_regs[i].realreg () == i); | |
909 | } | |
910 | } | |
4d9a9006 YQ |
911 | } |
912 | } // namespace selftests | |
913 | #endif /* GDB_SELF_TEST */ | |
914 | ||
07b287a0 MS |
915 | /* Implement the "skip_prologue" gdbarch method. */ |
916 | ||
917 | static CORE_ADDR | |
918 | aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
919 | { | |
22f2cf64 | 920 | CORE_ADDR func_addr, func_end_addr, limit_pc; |
07b287a0 MS |
921 | |
922 | /* See if we can determine the end of the prologue via the symbol | |
923 | table. If so, then return either PC, or the PC after the | |
924 | prologue, whichever is greater. */ | |
22f2cf64 TV |
925 | bool func_addr_found |
926 | = find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr); | |
927 | ||
928 | if (func_addr_found) | |
07b287a0 MS |
929 | { |
930 | CORE_ADDR post_prologue_pc | |
931 | = skip_prologue_using_sal (gdbarch, func_addr); | |
932 | ||
933 | if (post_prologue_pc != 0) | |
325fac50 | 934 | return std::max (pc, post_prologue_pc); |
07b287a0 MS |
935 | } |
936 | ||
937 | /* Can't determine prologue from the symbol table, need to examine | |
938 | instructions. */ | |
939 | ||
940 | /* Find an upper limit on the function prologue using the debug | |
941 | information. If the debug information could not be used to | |
942 | provide that bound, then use an arbitrary large number as the | |
943 | upper bound. */ | |
944 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
945 | if (limit_pc == 0) | |
946 | limit_pc = pc + 128; /* Magic. */ | |
947 | ||
22f2cf64 | 948 | limit_pc |
05d63baf | 949 | = func_end_addr == 0 ? limit_pc : std::min (limit_pc, func_end_addr - 4); |
22f2cf64 | 950 | |
07b287a0 MS |
951 | /* Try disassembling prologue. */ |
952 | return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
953 | } | |
954 | ||
955 | /* Scan the function prologue for THIS_FRAME and populate the prologue | |
956 | cache CACHE. */ | |
957 | ||
958 | static void | |
bd2b40ac | 959 | aarch64_scan_prologue (frame_info_ptr this_frame, |
07b287a0 MS |
960 | struct aarch64_prologue_cache *cache) |
961 | { | |
962 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
963 | CORE_ADDR prologue_start; | |
964 | CORE_ADDR prologue_end; | |
965 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
966 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
967 | ||
db634143 PL |
968 | cache->prev_pc = prev_pc; |
969 | ||
07b287a0 MS |
970 | /* Assume we do not find a frame. */ |
971 | cache->framereg = -1; | |
972 | cache->framesize = 0; | |
973 | ||
974 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
975 | &prologue_end)) | |
976 | { | |
977 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
978 | ||
979 | if (sal.line == 0) | |
980 | { | |
981 | /* No line info so use the current PC. */ | |
982 | prologue_end = prev_pc; | |
983 | } | |
984 | else if (sal.end < prologue_end) | |
985 | { | |
986 | /* The next line begins after the function end. */ | |
987 | prologue_end = sal.end; | |
988 | } | |
989 | ||
325fac50 | 990 | prologue_end = std::min (prologue_end, prev_pc); |
07b287a0 MS |
991 | aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
992 | } | |
993 | else | |
994 | { | |
995 | CORE_ADDR frame_loc; | |
07b287a0 MS |
996 | |
997 | frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM); | |
998 | if (frame_loc == 0) | |
999 | return; | |
1000 | ||
1001 | cache->framereg = AARCH64_FP_REGNUM; | |
1002 | cache->framesize = 16; | |
098caef4 LM |
1003 | cache->saved_regs[29].set_addr (0); |
1004 | cache->saved_regs[30].set_addr (8); | |
07b287a0 MS |
1005 | } |
1006 | } | |
1007 | ||
7dfa3edc PL |
1008 | /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This |
1009 | function may throw an exception if the inferior's registers or memory is | |
1010 | not available. */ | |
07b287a0 | 1011 | |
7dfa3edc | 1012 | static void |
bd2b40ac | 1013 | aarch64_make_prologue_cache_1 (frame_info_ptr this_frame, |
7dfa3edc | 1014 | struct aarch64_prologue_cache *cache) |
07b287a0 | 1015 | { |
07b287a0 MS |
1016 | CORE_ADDR unwound_fp; |
1017 | int reg; | |
1018 | ||
07b287a0 MS |
1019 | aarch64_scan_prologue (this_frame, cache); |
1020 | ||
1021 | if (cache->framereg == -1) | |
7dfa3edc | 1022 | return; |
07b287a0 MS |
1023 | |
1024 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); | |
1025 | if (unwound_fp == 0) | |
7dfa3edc | 1026 | return; |
07b287a0 | 1027 | |
29e09a42 TV |
1028 | cache->prev_sp = unwound_fp; |
1029 | if (!aarch64_stack_frame_destroyed_p (get_frame_arch (this_frame), | |
1030 | cache->prev_pc)) | |
1031 | cache->prev_sp += cache->framesize; | |
07b287a0 MS |
1032 | |
1033 | /* Calculate actual addresses of saved registers using offsets | |
1034 | determined by aarch64_analyze_prologue. */ | |
1035 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
a9a87d35 | 1036 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 LM |
1037 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
1038 | + cache->prev_sp); | |
07b287a0 | 1039 | |
db634143 PL |
1040 | cache->func = get_frame_func (this_frame); |
1041 | ||
7dfa3edc PL |
1042 | cache->available_p = 1; |
1043 | } | |
1044 | ||
1045 | /* Allocate and fill in *THIS_CACHE with information about the prologue of | |
1046 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
1047 | Return a pointer to the current aarch64_prologue_cache in | |
1048 | *THIS_CACHE. */ | |
1049 | ||
1050 | static struct aarch64_prologue_cache * | |
bd2b40ac | 1051 | aarch64_make_prologue_cache (frame_info_ptr this_frame, void **this_cache) |
7dfa3edc PL |
1052 | { |
1053 | struct aarch64_prologue_cache *cache; | |
1054 | ||
1055 | if (*this_cache != NULL) | |
9a3c8263 | 1056 | return (struct aarch64_prologue_cache *) *this_cache; |
7dfa3edc PL |
1057 | |
1058 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
1059 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
1060 | *this_cache = cache; | |
1061 | ||
a70b8144 | 1062 | try |
7dfa3edc PL |
1063 | { |
1064 | aarch64_make_prologue_cache_1 (this_frame, cache); | |
1065 | } | |
230d2906 | 1066 | catch (const gdb_exception_error &ex) |
7dfa3edc PL |
1067 | { |
1068 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 1069 | throw; |
7dfa3edc | 1070 | } |
7dfa3edc | 1071 | |
07b287a0 MS |
1072 | return cache; |
1073 | } | |
1074 | ||
7dfa3edc PL |
1075 | /* Implement the "stop_reason" frame_unwind method. */ |
1076 | ||
1077 | static enum unwind_stop_reason | |
bd2b40ac | 1078 | aarch64_prologue_frame_unwind_stop_reason (frame_info_ptr this_frame, |
7dfa3edc PL |
1079 | void **this_cache) |
1080 | { | |
1081 | struct aarch64_prologue_cache *cache | |
1082 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
1083 | ||
1084 | if (!cache->available_p) | |
1085 | return UNWIND_UNAVAILABLE; | |
1086 | ||
1087 | /* Halt the backtrace at "_start". */ | |
345bd07c | 1088 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 1089 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (arch); |
345bd07c | 1090 | if (cache->prev_pc <= tdep->lowest_pc) |
7dfa3edc PL |
1091 | return UNWIND_OUTERMOST; |
1092 | ||
1093 | /* We've hit a wall, stop. */ | |
1094 | if (cache->prev_sp == 0) | |
1095 | return UNWIND_OUTERMOST; | |
1096 | ||
1097 | return UNWIND_NO_REASON; | |
1098 | } | |
1099 | ||
07b287a0 MS |
1100 | /* Our frame ID for a normal frame is the current function's starting |
1101 | PC and the caller's SP when we were called. */ | |
1102 | ||
1103 | static void | |
bd2b40ac | 1104 | aarch64_prologue_this_id (frame_info_ptr this_frame, |
07b287a0 MS |
1105 | void **this_cache, struct frame_id *this_id) |
1106 | { | |
7c8edfae PL |
1107 | struct aarch64_prologue_cache *cache |
1108 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 | 1109 | |
7dfa3edc PL |
1110 | if (!cache->available_p) |
1111 | *this_id = frame_id_build_unavailable_stack (cache->func); | |
1112 | else | |
1113 | *this_id = frame_id_build (cache->prev_sp, cache->func); | |
07b287a0 MS |
1114 | } |
1115 | ||
1116 | /* Implement the "prev_register" frame_unwind method. */ | |
1117 | ||
1118 | static struct value * | |
bd2b40ac | 1119 | aarch64_prologue_prev_register (frame_info_ptr this_frame, |
07b287a0 MS |
1120 | void **this_cache, int prev_regnum) |
1121 | { | |
7c8edfae PL |
1122 | struct aarch64_prologue_cache *cache |
1123 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
1124 | |
1125 | /* If we are asked to unwind the PC, then we need to return the LR | |
1126 | instead. The prologue may save PC, but it will point into this | |
1127 | frame's prologue, not the next frame's resume location. */ | |
1128 | if (prev_regnum == AARCH64_PC_REGNUM) | |
1129 | { | |
1130 | CORE_ADDR lr; | |
17e116a7 | 1131 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
345bd07c | 1132 | aarch64_gdbarch_tdep *tdep |
08106042 | 1133 | = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
1134 | |
1135 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
17e116a7 AH |
1136 | |
1137 | if (tdep->has_pauth () | |
c9cd8ca4 | 1138 | && cache->saved_regs[tdep->ra_sign_state_regnum].is_value ()) |
3d31bc39 | 1139 | lr = aarch64_frame_unmask_lr (tdep, this_frame, lr); |
17e116a7 | 1140 | |
07b287a0 MS |
1141 | return frame_unwind_got_constant (this_frame, prev_regnum, lr); |
1142 | } | |
1143 | ||
1144 | /* SP is generally not saved to the stack, but this frame is | |
1145 | identified by the next frame's stack pointer at the time of the | |
1146 | call. The value was already reconstructed into PREV_SP. */ | |
1147 | /* | |
dda83cd7 SM |
1148 | +----------+ ^ |
1149 | | saved lr | | | |
07b287a0 MS |
1150 | +->| saved fp |--+ |
1151 | | | | | |
1152 | | | | <- Previous SP | |
1153 | | +----------+ | |
1154 | | | saved lr | | |
1155 | +--| saved fp |<- FP | |
dda83cd7 SM |
1156 | | | |
1157 | | |<- SP | |
1158 | +----------+ */ | |
07b287a0 MS |
1159 | if (prev_regnum == AARCH64_SP_REGNUM) |
1160 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
1161 | cache->prev_sp); | |
1162 | ||
1163 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
1164 | prev_regnum); | |
1165 | } | |
1166 | ||
1167 | /* AArch64 prologue unwinder. */ | |
6bd434d6 | 1168 | static frame_unwind aarch64_prologue_unwind = |
07b287a0 | 1169 | { |
a154d838 | 1170 | "aarch64 prologue", |
07b287a0 | 1171 | NORMAL_FRAME, |
7dfa3edc | 1172 | aarch64_prologue_frame_unwind_stop_reason, |
07b287a0 MS |
1173 | aarch64_prologue_this_id, |
1174 | aarch64_prologue_prev_register, | |
1175 | NULL, | |
1176 | default_frame_sniffer | |
1177 | }; | |
1178 | ||
8b61f75d PL |
1179 | /* Allocate and fill in *THIS_CACHE with information about the prologue of |
1180 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
1181 | Return a pointer to the current aarch64_prologue_cache in | |
1182 | *THIS_CACHE. */ | |
07b287a0 MS |
1183 | |
1184 | static struct aarch64_prologue_cache * | |
bd2b40ac | 1185 | aarch64_make_stub_cache (frame_info_ptr this_frame, void **this_cache) |
07b287a0 | 1186 | { |
07b287a0 | 1187 | struct aarch64_prologue_cache *cache; |
8b61f75d PL |
1188 | |
1189 | if (*this_cache != NULL) | |
9a3c8263 | 1190 | return (struct aarch64_prologue_cache *) *this_cache; |
07b287a0 MS |
1191 | |
1192 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
1193 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
8b61f75d | 1194 | *this_cache = cache; |
07b287a0 | 1195 | |
a70b8144 | 1196 | try |
02a2a705 PL |
1197 | { |
1198 | cache->prev_sp = get_frame_register_unsigned (this_frame, | |
1199 | AARCH64_SP_REGNUM); | |
1200 | cache->prev_pc = get_frame_pc (this_frame); | |
1201 | cache->available_p = 1; | |
1202 | } | |
230d2906 | 1203 | catch (const gdb_exception_error &ex) |
02a2a705 PL |
1204 | { |
1205 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 1206 | throw; |
02a2a705 | 1207 | } |
07b287a0 MS |
1208 | |
1209 | return cache; | |
1210 | } | |
1211 | ||
02a2a705 PL |
1212 | /* Implement the "stop_reason" frame_unwind method. */ |
1213 | ||
1214 | static enum unwind_stop_reason | |
bd2b40ac | 1215 | aarch64_stub_frame_unwind_stop_reason (frame_info_ptr this_frame, |
02a2a705 PL |
1216 | void **this_cache) |
1217 | { | |
1218 | struct aarch64_prologue_cache *cache | |
1219 | = aarch64_make_stub_cache (this_frame, this_cache); | |
1220 | ||
1221 | if (!cache->available_p) | |
1222 | return UNWIND_UNAVAILABLE; | |
1223 | ||
1224 | return UNWIND_NO_REASON; | |
1225 | } | |
1226 | ||
07b287a0 MS |
1227 | /* Our frame ID for a stub frame is the current SP and LR. */ |
1228 | ||
1229 | static void | |
bd2b40ac | 1230 | aarch64_stub_this_id (frame_info_ptr this_frame, |
07b287a0 MS |
1231 | void **this_cache, struct frame_id *this_id) |
1232 | { | |
8b61f75d PL |
1233 | struct aarch64_prologue_cache *cache |
1234 | = aarch64_make_stub_cache (this_frame, this_cache); | |
07b287a0 | 1235 | |
02a2a705 PL |
1236 | if (cache->available_p) |
1237 | *this_id = frame_id_build (cache->prev_sp, cache->prev_pc); | |
1238 | else | |
1239 | *this_id = frame_id_build_unavailable_stack (cache->prev_pc); | |
07b287a0 MS |
1240 | } |
1241 | ||
1242 | /* Implement the "sniffer" frame_unwind method. */ | |
1243 | ||
1244 | static int | |
1245 | aarch64_stub_unwind_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 1246 | frame_info_ptr this_frame, |
07b287a0 MS |
1247 | void **this_prologue_cache) |
1248 | { | |
1249 | CORE_ADDR addr_in_block; | |
1250 | gdb_byte dummy[4]; | |
1251 | ||
1252 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 1253 | if (in_plt_section (addr_in_block) |
07b287a0 MS |
1254 | /* We also use the stub winder if the target memory is unreadable |
1255 | to avoid having the prologue unwinder trying to read it. */ | |
1256 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
1257 | return 1; | |
1258 | ||
1259 | return 0; | |
1260 | } | |
1261 | ||
1262 | /* AArch64 stub unwinder. */ | |
6bd434d6 | 1263 | static frame_unwind aarch64_stub_unwind = |
07b287a0 | 1264 | { |
a154d838 | 1265 | "aarch64 stub", |
07b287a0 | 1266 | NORMAL_FRAME, |
02a2a705 | 1267 | aarch64_stub_frame_unwind_stop_reason, |
07b287a0 MS |
1268 | aarch64_stub_this_id, |
1269 | aarch64_prologue_prev_register, | |
1270 | NULL, | |
1271 | aarch64_stub_unwind_sniffer | |
1272 | }; | |
1273 | ||
1274 | /* Return the frame base address of *THIS_FRAME. */ | |
1275 | ||
1276 | static CORE_ADDR | |
bd2b40ac | 1277 | aarch64_normal_frame_base (frame_info_ptr this_frame, void **this_cache) |
07b287a0 | 1278 | { |
7c8edfae PL |
1279 | struct aarch64_prologue_cache *cache |
1280 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
1281 | |
1282 | return cache->prev_sp - cache->framesize; | |
1283 | } | |
1284 | ||
1285 | /* AArch64 default frame base information. */ | |
6bd434d6 | 1286 | static frame_base aarch64_normal_base = |
07b287a0 MS |
1287 | { |
1288 | &aarch64_prologue_unwind, | |
1289 | aarch64_normal_frame_base, | |
1290 | aarch64_normal_frame_base, | |
1291 | aarch64_normal_frame_base | |
1292 | }; | |
1293 | ||
07b287a0 MS |
1294 | /* Return the value of the REGNUM register in the previous frame of |
1295 | *THIS_FRAME. */ | |
1296 | ||
1297 | static struct value * | |
bd2b40ac | 1298 | aarch64_dwarf2_prev_register (frame_info_ptr this_frame, |
07b287a0 MS |
1299 | void **this_cache, int regnum) |
1300 | { | |
345bd07c | 1301 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 1302 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (arch); |
07b287a0 MS |
1303 | CORE_ADDR lr; |
1304 | ||
1305 | switch (regnum) | |
1306 | { | |
1307 | case AARCH64_PC_REGNUM: | |
1308 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
3d31bc39 | 1309 | lr = aarch64_frame_unmask_lr (tdep, this_frame, lr); |
07b287a0 MS |
1310 | return frame_unwind_got_constant (this_frame, regnum, lr); |
1311 | ||
1312 | default: | |
f34652de | 1313 | internal_error (_("Unexpected register %d"), regnum); |
07b287a0 MS |
1314 | } |
1315 | } | |
1316 | ||
11e1b75f AH |
1317 | static const unsigned char op_lit0 = DW_OP_lit0; |
1318 | static const unsigned char op_lit1 = DW_OP_lit1; | |
1319 | ||
07b287a0 MS |
1320 | /* Implement the "init_reg" dwarf2_frame_ops method. */ |
1321 | ||
1322 | static void | |
1323 | aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1324 | struct dwarf2_frame_state_reg *reg, | |
bd2b40ac | 1325 | frame_info_ptr this_frame) |
07b287a0 | 1326 | { |
08106042 | 1327 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
11e1b75f | 1328 | |
07b287a0 MS |
1329 | switch (regnum) |
1330 | { | |
1331 | case AARCH64_PC_REGNUM: | |
1332 | reg->how = DWARF2_FRAME_REG_FN; | |
1333 | reg->loc.fn = aarch64_dwarf2_prev_register; | |
11e1b75f AH |
1334 | return; |
1335 | ||
07b287a0 MS |
1336 | case AARCH64_SP_REGNUM: |
1337 | reg->how = DWARF2_FRAME_REG_CFA; | |
11e1b75f AH |
1338 | return; |
1339 | } | |
1340 | ||
1341 | /* Init pauth registers. */ | |
1342 | if (tdep->has_pauth ()) | |
1343 | { | |
c9cd8ca4 | 1344 | if (regnum == tdep->ra_sign_state_regnum) |
11e1b75f AH |
1345 | { |
1346 | /* Initialize RA_STATE to zero. */ | |
1347 | reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; | |
1348 | reg->loc.exp.start = &op_lit0; | |
1349 | reg->loc.exp.len = 1; | |
1350 | return; | |
1351 | } | |
6d002087 LM |
1352 | else if (regnum >= tdep->pauth_reg_base |
1353 | && regnum < tdep->pauth_reg_base + tdep->pauth_reg_count) | |
11e1b75f AH |
1354 | { |
1355 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1356 | return; | |
1357 | } | |
07b287a0 MS |
1358 | } |
1359 | } | |
1360 | ||
11e1b75f AH |
1361 | /* Implement the execute_dwarf_cfa_vendor_op method. */ |
1362 | ||
1363 | static bool | |
1364 | aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, | |
1365 | struct dwarf2_frame_state *fs) | |
1366 | { | |
08106042 | 1367 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
11e1b75f AH |
1368 | struct dwarf2_frame_state_reg *ra_state; |
1369 | ||
8fca4da0 | 1370 | if (op == DW_CFA_AARCH64_negate_ra_state) |
11e1b75f | 1371 | { |
8fca4da0 AH |
1372 | /* On systems without pauth, treat as a nop. */ |
1373 | if (!tdep->has_pauth ()) | |
1374 | return true; | |
1375 | ||
11e1b75f | 1376 | /* Allocate RA_STATE column if it's not allocated yet. */ |
c9cd8ca4 | 1377 | fs->regs.alloc_regs (AARCH64_DWARF_RA_SIGN_STATE + 1); |
11e1b75f AH |
1378 | |
1379 | /* Toggle the status of RA_STATE between 0 and 1. */ | |
c9cd8ca4 | 1380 | ra_state = &(fs->regs.reg[AARCH64_DWARF_RA_SIGN_STATE]); |
11e1b75f AH |
1381 | ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; |
1382 | ||
1383 | if (ra_state->loc.exp.start == nullptr | |
1384 | || ra_state->loc.exp.start == &op_lit0) | |
1385 | ra_state->loc.exp.start = &op_lit1; | |
1386 | else | |
1387 | ra_state->loc.exp.start = &op_lit0; | |
1388 | ||
1389 | ra_state->loc.exp.len = 1; | |
1390 | ||
1391 | return true; | |
1392 | } | |
1393 | ||
1394 | return false; | |
1395 | } | |
1396 | ||
5133a315 LM |
1397 | /* Used for matching BRK instructions for AArch64. */ |
1398 | static constexpr uint32_t BRK_INSN_MASK = 0xffe0001f; | |
1399 | static constexpr uint32_t BRK_INSN_BASE = 0xd4200000; | |
1400 | ||
1401 | /* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */ | |
1402 | ||
1403 | static bool | |
1404 | aarch64_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address) | |
1405 | { | |
1406 | const uint32_t insn_len = 4; | |
1407 | gdb_byte target_mem[4]; | |
1408 | ||
1409 | /* Enable the automatic memory restoration from breakpoints while | |
1410 | we read the memory. Otherwise we may find temporary breakpoints, ones | |
1411 | inserted by GDB, and flag them as permanent breakpoints. */ | |
1412 | scoped_restore restore_memory | |
1413 | = make_scoped_restore_show_memory_breakpoints (0); | |
1414 | ||
1415 | if (target_read_memory (address, target_mem, insn_len) == 0) | |
1416 | { | |
1417 | uint32_t insn = | |
1418 | (uint32_t) extract_unsigned_integer (target_mem, insn_len, | |
1419 | gdbarch_byte_order_for_code (gdbarch)); | |
1420 | ||
1421 | /* Check if INSN is a BRK instruction pattern. There are multiple choices | |
1422 | of such instructions with different immediate values. Different OS' | |
1423 | may use a different variation, but they have the same outcome. */ | |
1424 | return ((insn & BRK_INSN_MASK) == BRK_INSN_BASE); | |
1425 | } | |
1426 | ||
1427 | return false; | |
1428 | } | |
1429 | ||
07b287a0 MS |
1430 | /* When arguments must be pushed onto the stack, they go on in reverse |
1431 | order. The code below implements a FILO (stack) to do this. */ | |
1432 | ||
89055eaa | 1433 | struct stack_item_t |
07b287a0 | 1434 | { |
c3c87445 YQ |
1435 | /* Value to pass on stack. It can be NULL if this item is for stack |
1436 | padding. */ | |
7c543f7b | 1437 | const gdb_byte *data; |
07b287a0 MS |
1438 | |
1439 | /* Size in bytes of value to pass on stack. */ | |
1440 | int len; | |
89055eaa | 1441 | }; |
07b287a0 | 1442 | |
b907456c AB |
1443 | /* Implement the gdbarch type alignment method, overrides the generic |
1444 | alignment algorithm for anything that is aarch64 specific. */ | |
07b287a0 | 1445 | |
b907456c AB |
1446 | static ULONGEST |
1447 | aarch64_type_align (gdbarch *gdbarch, struct type *t) | |
07b287a0 | 1448 | { |
07b287a0 | 1449 | t = check_typedef (t); |
bd63c870 | 1450 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
07b287a0 | 1451 | { |
b907456c AB |
1452 | /* Use the natural alignment for vector types (the same for |
1453 | scalar type), but the maximum alignment is 128-bit. */ | |
df86565b | 1454 | if (t->length () > 16) |
b907456c | 1455 | return 16; |
238f2452 | 1456 | else |
df86565b | 1457 | return t->length (); |
07b287a0 | 1458 | } |
b907456c AB |
1459 | |
1460 | /* Allow the common code to calculate the alignment. */ | |
1461 | return 0; | |
07b287a0 MS |
1462 | } |
1463 | ||
ea92689a AH |
1464 | /* Worker function for aapcs_is_vfp_call_or_return_candidate. |
1465 | ||
1466 | Return the number of register required, or -1 on failure. | |
1467 | ||
1468 | When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it | |
1469 | to the element, else fail if the type of this element does not match the | |
1470 | existing value. */ | |
1471 | ||
1472 | static int | |
1473 | aapcs_is_vfp_call_or_return_candidate_1 (struct type *type, | |
1474 | struct type **fundamental_type) | |
1475 | { | |
1476 | if (type == nullptr) | |
1477 | return -1; | |
1478 | ||
78134374 | 1479 | switch (type->code ()) |
ea92689a AH |
1480 | { |
1481 | case TYPE_CODE_FLT: | |
81657e58 | 1482 | case TYPE_CODE_DECFLOAT: |
df86565b | 1483 | if (type->length () > 16) |
ea92689a AH |
1484 | return -1; |
1485 | ||
1486 | if (*fundamental_type == nullptr) | |
1487 | *fundamental_type = type; | |
df86565b | 1488 | else if (type->length () != (*fundamental_type)->length () |
78134374 | 1489 | || type->code () != (*fundamental_type)->code ()) |
ea92689a AH |
1490 | return -1; |
1491 | ||
1492 | return 1; | |
1493 | ||
1494 | case TYPE_CODE_COMPLEX: | |
1495 | { | |
27710edb | 1496 | struct type *target_type = check_typedef (type->target_type ()); |
df86565b | 1497 | if (target_type->length () > 16) |
ea92689a AH |
1498 | return -1; |
1499 | ||
1500 | if (*fundamental_type == nullptr) | |
1501 | *fundamental_type = target_type; | |
df86565b | 1502 | else if (target_type->length () != (*fundamental_type)->length () |
78134374 | 1503 | || target_type->code () != (*fundamental_type)->code ()) |
ea92689a AH |
1504 | return -1; |
1505 | ||
1506 | return 2; | |
1507 | } | |
1508 | ||
1509 | case TYPE_CODE_ARRAY: | |
1510 | { | |
bd63c870 | 1511 | if (type->is_vector ()) |
ea92689a | 1512 | { |
df86565b | 1513 | if (type->length () != 8 && type->length () != 16) |
ea92689a AH |
1514 | return -1; |
1515 | ||
1516 | if (*fundamental_type == nullptr) | |
1517 | *fundamental_type = type; | |
df86565b | 1518 | else if (type->length () != (*fundamental_type)->length () |
78134374 | 1519 | || type->code () != (*fundamental_type)->code ()) |
ea92689a AH |
1520 | return -1; |
1521 | ||
1522 | return 1; | |
1523 | } | |
1524 | else | |
1525 | { | |
27710edb | 1526 | struct type *target_type = type->target_type (); |
ea92689a AH |
1527 | int count = aapcs_is_vfp_call_or_return_candidate_1 |
1528 | (target_type, fundamental_type); | |
1529 | ||
1530 | if (count == -1) | |
1531 | return count; | |
1532 | ||
df86565b | 1533 | count *= (type->length () / target_type->length ()); |
ea92689a AH |
1534 | return count; |
1535 | } | |
1536 | } | |
1537 | ||
1538 | case TYPE_CODE_STRUCT: | |
1539 | case TYPE_CODE_UNION: | |
1540 | { | |
1541 | int count = 0; | |
1542 | ||
1f704f76 | 1543 | for (int i = 0; i < type->num_fields (); i++) |
ea92689a | 1544 | { |
353229bf | 1545 | /* Ignore any static fields. */ |
c819a338 | 1546 | if (type->field (i).is_static ()) |
353229bf AH |
1547 | continue; |
1548 | ||
940da03e | 1549 | struct type *member = check_typedef (type->field (i).type ()); |
ea92689a AH |
1550 | |
1551 | int sub_count = aapcs_is_vfp_call_or_return_candidate_1 | |
1552 | (member, fundamental_type); | |
1553 | if (sub_count == -1) | |
1554 | return -1; | |
1555 | count += sub_count; | |
1556 | } | |
73021deb AH |
1557 | |
1558 | /* Ensure there is no padding between the fields (allowing for empty | |
1559 | zero length structs) */ | |
1560 | int ftype_length = (*fundamental_type == nullptr) | |
df86565b SM |
1561 | ? 0 : (*fundamental_type)->length (); |
1562 | if (count * ftype_length != type->length ()) | |
73021deb AH |
1563 | return -1; |
1564 | ||
ea92689a AH |
1565 | return count; |
1566 | } | |
1567 | ||
1568 | default: | |
1569 | break; | |
1570 | } | |
1571 | ||
1572 | return -1; | |
1573 | } | |
1574 | ||
1575 | /* Return true if an argument, whose type is described by TYPE, can be passed or | |
1576 | returned in simd/fp registers, providing enough parameter passing registers | |
1577 | are available. This is as described in the AAPCS64. | |
1578 | ||
1579 | Upon successful return, *COUNT returns the number of needed registers, | |
1580 | *FUNDAMENTAL_TYPE contains the type of those registers. | |
1581 | ||
1582 | Candidate as per the AAPCS64 5.4.2.C is either a: | |
1583 | - float. | |
1584 | - short-vector. | |
1585 | - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where | |
1586 | all the members are floats and has at most 4 members. | |
1587 | - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where | |
1588 | all the members are short vectors and has at most 4 members. | |
1589 | - Complex (7.1.1) | |
1590 | ||
1591 | Note that HFAs and HVAs can include nested structures and arrays. */ | |
1592 | ||
0e745c60 | 1593 | static bool |
ea92689a AH |
1594 | aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count, |
1595 | struct type **fundamental_type) | |
1596 | { | |
1597 | if (type == nullptr) | |
1598 | return false; | |
1599 | ||
1600 | *fundamental_type = nullptr; | |
1601 | ||
1602 | int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type, | |
1603 | fundamental_type); | |
1604 | ||
1605 | if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS) | |
1606 | { | |
1607 | *count = ag_count; | |
1608 | return true; | |
1609 | } | |
1610 | else | |
1611 | return false; | |
1612 | } | |
1613 | ||
07b287a0 MS |
1614 | /* AArch64 function call information structure. */ |
1615 | struct aarch64_call_info | |
1616 | { | |
1617 | /* the current argument number. */ | |
89055eaa | 1618 | unsigned argnum = 0; |
07b287a0 MS |
1619 | |
1620 | /* The next general purpose register number, equivalent to NGRN as | |
1621 | described in the AArch64 Procedure Call Standard. */ | |
89055eaa | 1622 | unsigned ngrn = 0; |
07b287a0 MS |
1623 | |
1624 | /* The next SIMD and floating point register number, equivalent to | |
1625 | NSRN as described in the AArch64 Procedure Call Standard. */ | |
89055eaa | 1626 | unsigned nsrn = 0; |
07b287a0 MS |
1627 | |
1628 | /* The next stacked argument address, equivalent to NSAA as | |
1629 | described in the AArch64 Procedure Call Standard. */ | |
89055eaa | 1630 | unsigned nsaa = 0; |
07b287a0 MS |
1631 | |
1632 | /* Stack item vector. */ | |
89055eaa | 1633 | std::vector<stack_item_t> si; |
07b287a0 MS |
1634 | }; |
1635 | ||
1636 | /* Pass a value in a sequence of consecutive X registers. The caller | |
30baf67b | 1637 | is responsible for ensuring sufficient registers are available. */ |
07b287a0 MS |
1638 | |
1639 | static void | |
1640 | pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache, | |
1641 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1642 | struct value *arg) |
07b287a0 MS |
1643 | { |
1644 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
df86565b | 1645 | int len = type->length (); |
78134374 | 1646 | enum type_code typecode = type->code (); |
07b287a0 | 1647 | int regnum = AARCH64_X0_REGNUM + info->ngrn; |
efaf1ae0 | 1648 | const bfd_byte *buf = arg->contents ().data (); |
07b287a0 MS |
1649 | |
1650 | info->argnum++; | |
1651 | ||
1652 | while (len > 0) | |
1653 | { | |
1654 | int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE; | |
1655 | CORE_ADDR regval = extract_unsigned_integer (buf, partial_len, | |
1656 | byte_order); | |
1657 | ||
1658 | ||
1659 | /* Adjust sub-word struct/union args when big-endian. */ | |
1660 | if (byte_order == BFD_ENDIAN_BIG | |
1661 | && partial_len < X_REGISTER_SIZE | |
1662 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
1663 | regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT); | |
1664 | ||
c6185dce SM |
1665 | aarch64_debug_printf ("arg %d in %s = 0x%s", info->argnum, |
1666 | gdbarch_register_name (gdbarch, regnum), | |
1667 | phex (regval, X_REGISTER_SIZE)); | |
1668 | ||
07b287a0 MS |
1669 | regcache_cooked_write_unsigned (regcache, regnum, regval); |
1670 | len -= partial_len; | |
1671 | buf += partial_len; | |
1672 | regnum++; | |
1673 | } | |
1674 | } | |
1675 | ||
1676 | /* Attempt to marshall a value in a V register. Return 1 if | |
1677 | successful, or 0 if insufficient registers are available. This | |
1678 | function, unlike the equivalent pass_in_x() function does not | |
1679 | handle arguments spread across multiple registers. */ | |
1680 | ||
1681 | static int | |
1682 | pass_in_v (struct gdbarch *gdbarch, | |
1683 | struct regcache *regcache, | |
1684 | struct aarch64_call_info *info, | |
0735fddd | 1685 | int len, const bfd_byte *buf) |
07b287a0 MS |
1686 | { |
1687 | if (info->nsrn < 8) | |
1688 | { | |
07b287a0 | 1689 | int regnum = AARCH64_V0_REGNUM + info->nsrn; |
3ff2c72e AH |
1690 | /* Enough space for a full vector register. */ |
1691 | gdb_byte reg[register_size (gdbarch, regnum)]; | |
1692 | gdb_assert (len <= sizeof (reg)); | |
07b287a0 MS |
1693 | |
1694 | info->argnum++; | |
1695 | info->nsrn++; | |
1696 | ||
0735fddd YQ |
1697 | memset (reg, 0, sizeof (reg)); |
1698 | /* PCS C.1, the argument is allocated to the least significant | |
1699 | bits of V register. */ | |
1700 | memcpy (reg, buf, len); | |
b66f5587 | 1701 | regcache->cooked_write (regnum, reg); |
0735fddd | 1702 | |
c6185dce SM |
1703 | aarch64_debug_printf ("arg %d in %s", info->argnum, |
1704 | gdbarch_register_name (gdbarch, regnum)); | |
1705 | ||
07b287a0 MS |
1706 | return 1; |
1707 | } | |
1708 | info->nsrn = 8; | |
1709 | return 0; | |
1710 | } | |
1711 | ||
1712 | /* Marshall an argument onto the stack. */ | |
1713 | ||
1714 | static void | |
1715 | pass_on_stack (struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1716 | struct value *arg) |
07b287a0 | 1717 | { |
efaf1ae0 | 1718 | const bfd_byte *buf = arg->contents ().data (); |
df86565b | 1719 | int len = type->length (); |
07b287a0 MS |
1720 | int align; |
1721 | stack_item_t item; | |
1722 | ||
1723 | info->argnum++; | |
1724 | ||
b907456c | 1725 | align = type_align (type); |
07b287a0 MS |
1726 | |
1727 | /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the | |
1728 | Natural alignment of the argument's type. */ | |
1729 | align = align_up (align, 8); | |
1730 | ||
1731 | /* The AArch64 PCS requires at most doubleword alignment. */ | |
1732 | if (align > 16) | |
1733 | align = 16; | |
1734 | ||
c6185dce SM |
1735 | aarch64_debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len, |
1736 | info->nsaa); | |
07b287a0 MS |
1737 | |
1738 | item.len = len; | |
1739 | item.data = buf; | |
89055eaa | 1740 | info->si.push_back (item); |
07b287a0 MS |
1741 | |
1742 | info->nsaa += len; | |
1743 | if (info->nsaa & (align - 1)) | |
1744 | { | |
1745 | /* Push stack alignment padding. */ | |
1746 | int pad = align - (info->nsaa & (align - 1)); | |
1747 | ||
1748 | item.len = pad; | |
c3c87445 | 1749 | item.data = NULL; |
07b287a0 | 1750 | |
89055eaa | 1751 | info->si.push_back (item); |
07b287a0 MS |
1752 | info->nsaa += pad; |
1753 | } | |
1754 | } | |
1755 | ||
1756 | /* Marshall an argument into a sequence of one or more consecutive X | |
1757 | registers or, if insufficient X registers are available then onto | |
1758 | the stack. */ | |
1759 | ||
1760 | static void | |
1761 | pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache, | |
1762 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1763 | struct value *arg) |
07b287a0 | 1764 | { |
df86565b | 1765 | int len = type->length (); |
07b287a0 MS |
1766 | int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE; |
1767 | ||
1768 | /* PCS C.13 - Pass in registers if we have enough spare */ | |
1769 | if (info->ngrn + nregs <= 8) | |
1770 | { | |
8e80f9d1 | 1771 | pass_in_x (gdbarch, regcache, info, type, arg); |
07b287a0 MS |
1772 | info->ngrn += nregs; |
1773 | } | |
1774 | else | |
1775 | { | |
1776 | info->ngrn = 8; | |
8e80f9d1 | 1777 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1778 | } |
1779 | } | |
1780 | ||
0e745c60 AH |
1781 | /* Pass a value, which is of type arg_type, in a V register. Assumes value is a |
1782 | aapcs_is_vfp_call_or_return_candidate and there are enough spare V | |
1783 | registers. A return value of false is an error state as the value will have | |
1784 | been partially passed to the stack. */ | |
1785 | static bool | |
1786 | pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache, | |
1787 | struct aarch64_call_info *info, struct type *arg_type, | |
1788 | struct value *arg) | |
07b287a0 | 1789 | { |
78134374 | 1790 | switch (arg_type->code ()) |
0e745c60 AH |
1791 | { |
1792 | case TYPE_CODE_FLT: | |
81657e58 | 1793 | case TYPE_CODE_DECFLOAT: |
df86565b | 1794 | return pass_in_v (gdbarch, regcache, info, arg_type->length (), |
efaf1ae0 | 1795 | arg->contents ().data ()); |
0e745c60 AH |
1796 | break; |
1797 | ||
1798 | case TYPE_CODE_COMPLEX: | |
1799 | { | |
efaf1ae0 | 1800 | const bfd_byte *buf = arg->contents ().data (); |
27710edb | 1801 | struct type *target_type = check_typedef (arg_type->target_type ()); |
0e745c60 | 1802 | |
df86565b | 1803 | if (!pass_in_v (gdbarch, regcache, info, target_type->length (), |
0e745c60 AH |
1804 | buf)) |
1805 | return false; | |
1806 | ||
df86565b SM |
1807 | return pass_in_v (gdbarch, regcache, info, target_type->length (), |
1808 | buf + target_type->length ()); | |
0e745c60 AH |
1809 | } |
1810 | ||
1811 | case TYPE_CODE_ARRAY: | |
bd63c870 | 1812 | if (arg_type->is_vector ()) |
df86565b | 1813 | return pass_in_v (gdbarch, regcache, info, arg_type->length (), |
efaf1ae0 | 1814 | arg->contents ().data ()); |
0e745c60 AH |
1815 | /* fall through. */ |
1816 | ||
1817 | case TYPE_CODE_STRUCT: | |
1818 | case TYPE_CODE_UNION: | |
1f704f76 | 1819 | for (int i = 0; i < arg_type->num_fields (); i++) |
0e745c60 | 1820 | { |
353229bf | 1821 | /* Don't include static fields. */ |
c819a338 | 1822 | if (arg_type->field (i).is_static ()) |
353229bf AH |
1823 | continue; |
1824 | ||
6c49729e | 1825 | struct value *field = arg->primitive_field (0, i, arg_type); |
d0c97917 | 1826 | struct type *field_type = check_typedef (field->type ()); |
0e745c60 AH |
1827 | |
1828 | if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type, | |
1829 | field)) | |
1830 | return false; | |
1831 | } | |
1832 | return true; | |
1833 | ||
1834 | default: | |
1835 | return false; | |
1836 | } | |
07b287a0 MS |
1837 | } |
1838 | ||
1839 | /* Implement the "push_dummy_call" gdbarch method. */ | |
1840 | ||
1841 | static CORE_ADDR | |
1842 | aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1843 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1844 | int nargs, | |
cf84fa6b AH |
1845 | struct value **args, CORE_ADDR sp, |
1846 | function_call_return_method return_method, | |
07b287a0 MS |
1847 | CORE_ADDR struct_addr) |
1848 | { | |
07b287a0 | 1849 | int argnum; |
07b287a0 | 1850 | struct aarch64_call_info info; |
07b287a0 | 1851 | |
07b287a0 MS |
1852 | /* We need to know what the type of the called function is in order |
1853 | to determine the number of named/anonymous arguments for the | |
1854 | actual argument placement, and the return type in order to handle | |
1855 | return value correctly. | |
1856 | ||
1857 | The generic code above us views the decision of return in memory | |
1858 | or return in registers as a two stage processes. The language | |
1859 | handler is consulted first and may decide to return in memory (eg | |
1860 | class with copy constructor returned by value), this will cause | |
1861 | the generic code to allocate space AND insert an initial leading | |
1862 | argument. | |
1863 | ||
1864 | If the language code does not decide to pass in memory then the | |
1865 | target code is consulted. | |
1866 | ||
1867 | If the language code decides to pass in memory we want to move | |
1868 | the pointer inserted as the initial argument from the argument | |
1869 | list and into X8, the conventional AArch64 struct return pointer | |
38a72da0 | 1870 | register. */ |
07b287a0 MS |
1871 | |
1872 | /* Set the return address. For the AArch64, the return breakpoint | |
1873 | is always at BP_ADDR. */ | |
1874 | regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr); | |
1875 | ||
38a72da0 AH |
1876 | /* If we were given an initial argument for the return slot, lose it. */ |
1877 | if (return_method == return_method_hidden_param) | |
07b287a0 MS |
1878 | { |
1879 | args++; | |
1880 | nargs--; | |
1881 | } | |
1882 | ||
1883 | /* The struct_return pointer occupies X8. */ | |
38a72da0 | 1884 | if (return_method != return_method_normal) |
07b287a0 | 1885 | { |
c6185dce SM |
1886 | aarch64_debug_printf ("struct return in %s = 0x%s", |
1887 | gdbarch_register_name | |
1888 | (gdbarch, AARCH64_STRUCT_RETURN_REGNUM), | |
1889 | paddress (gdbarch, struct_addr)); | |
1890 | ||
07b287a0 MS |
1891 | regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM, |
1892 | struct_addr); | |
1893 | } | |
1894 | ||
1895 | for (argnum = 0; argnum < nargs; argnum++) | |
1896 | { | |
1897 | struct value *arg = args[argnum]; | |
0e745c60 AH |
1898 | struct type *arg_type, *fundamental_type; |
1899 | int len, elements; | |
07b287a0 | 1900 | |
d0c97917 | 1901 | arg_type = check_typedef (arg->type ()); |
df86565b | 1902 | len = arg_type->length (); |
07b287a0 | 1903 | |
0e745c60 AH |
1904 | /* If arg can be passed in v registers as per the AAPCS64, then do so if |
1905 | if there are enough spare registers. */ | |
1906 | if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements, | |
1907 | &fundamental_type)) | |
1908 | { | |
1909 | if (info.nsrn + elements <= 8) | |
1910 | { | |
1911 | /* We know that we have sufficient registers available therefore | |
1912 | this will never need to fallback to the stack. */ | |
1913 | if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type, | |
1914 | arg)) | |
1915 | gdb_assert_not_reached ("Failed to push args"); | |
1916 | } | |
1917 | else | |
1918 | { | |
1919 | info.nsrn = 8; | |
1920 | pass_on_stack (&info, arg_type, arg); | |
1921 | } | |
1922 | continue; | |
1923 | } | |
1924 | ||
78134374 | 1925 | switch (arg_type->code ()) |
07b287a0 MS |
1926 | { |
1927 | case TYPE_CODE_INT: | |
1928 | case TYPE_CODE_BOOL: | |
1929 | case TYPE_CODE_CHAR: | |
1930 | case TYPE_CODE_RANGE: | |
1931 | case TYPE_CODE_ENUM: | |
28397ae7 | 1932 | if (len < 4 && !is_fixed_point_type (arg_type)) |
07b287a0 MS |
1933 | { |
1934 | /* Promote to 32 bit integer. */ | |
c6d940a9 | 1935 | if (arg_type->is_unsigned ()) |
07b287a0 MS |
1936 | arg_type = builtin_type (gdbarch)->builtin_uint32; |
1937 | else | |
1938 | arg_type = builtin_type (gdbarch)->builtin_int32; | |
1939 | arg = value_cast (arg_type, arg); | |
1940 | } | |
8e80f9d1 | 1941 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1942 | break; |
1943 | ||
07b287a0 MS |
1944 | case TYPE_CODE_STRUCT: |
1945 | case TYPE_CODE_ARRAY: | |
1946 | case TYPE_CODE_UNION: | |
0e745c60 | 1947 | if (len > 16) |
07b287a0 MS |
1948 | { |
1949 | /* PCS B.7 Aggregates larger than 16 bytes are passed by | |
1950 | invisible reference. */ | |
1951 | ||
1952 | /* Allocate aligned storage. */ | |
1953 | sp = align_down (sp - len, 16); | |
1954 | ||
1955 | /* Write the real data into the stack. */ | |
efaf1ae0 | 1956 | write_memory (sp, arg->contents ().data (), len); |
07b287a0 MS |
1957 | |
1958 | /* Construct the indirection. */ | |
1959 | arg_type = lookup_pointer_type (arg_type); | |
1960 | arg = value_from_pointer (arg_type, sp); | |
8e80f9d1 | 1961 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1962 | } |
1963 | else | |
1964 | /* PCS C.15 / C.18 multiple values pass. */ | |
8e80f9d1 | 1965 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1966 | break; |
1967 | ||
1968 | default: | |
8e80f9d1 | 1969 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1970 | break; |
1971 | } | |
1972 | } | |
1973 | ||
1974 | /* Make sure stack retains 16 byte alignment. */ | |
1975 | if (info.nsaa & 15) | |
1976 | sp -= 16 - (info.nsaa & 15); | |
1977 | ||
89055eaa | 1978 | while (!info.si.empty ()) |
07b287a0 | 1979 | { |
89055eaa | 1980 | const stack_item_t &si = info.si.back (); |
07b287a0 | 1981 | |
89055eaa TT |
1982 | sp -= si.len; |
1983 | if (si.data != NULL) | |
1984 | write_memory (sp, si.data, si.len); | |
1985 | info.si.pop_back (); | |
07b287a0 MS |
1986 | } |
1987 | ||
07b287a0 MS |
1988 | /* Finally, update the SP register. */ |
1989 | regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp); | |
1990 | ||
1991 | return sp; | |
1992 | } | |
1993 | ||
1994 | /* Implement the "frame_align" gdbarch method. */ | |
1995 | ||
1996 | static CORE_ADDR | |
1997 | aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
1998 | { | |
1999 | /* Align the stack to sixteen bytes. */ | |
2000 | return sp & ~(CORE_ADDR) 15; | |
2001 | } | |
2002 | ||
2003 | /* Return the type for an AdvSISD Q register. */ | |
2004 | ||
2005 | static struct type * | |
2006 | aarch64_vnq_type (struct gdbarch *gdbarch) | |
2007 | { | |
08106042 | 2008 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2009 | |
2010 | if (tdep->vnq_type == NULL) | |
2011 | { | |
2012 | struct type *t; | |
2013 | struct type *elem; | |
2014 | ||
2015 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
2016 | TYPE_CODE_UNION); | |
2017 | ||
2018 | elem = builtin_type (gdbarch)->builtin_uint128; | |
2019 | append_composite_type_field (t, "u", elem); | |
2020 | ||
2021 | elem = builtin_type (gdbarch)->builtin_int128; | |
2022 | append_composite_type_field (t, "s", elem); | |
2023 | ||
2024 | tdep->vnq_type = t; | |
2025 | } | |
2026 | ||
2027 | return tdep->vnq_type; | |
2028 | } | |
2029 | ||
2030 | /* Return the type for an AdvSISD D register. */ | |
2031 | ||
2032 | static struct type * | |
2033 | aarch64_vnd_type (struct gdbarch *gdbarch) | |
2034 | { | |
08106042 | 2035 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2036 | |
2037 | if (tdep->vnd_type == NULL) | |
2038 | { | |
2039 | struct type *t; | |
2040 | struct type *elem; | |
2041 | ||
2042 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", | |
2043 | TYPE_CODE_UNION); | |
2044 | ||
2045 | elem = builtin_type (gdbarch)->builtin_double; | |
2046 | append_composite_type_field (t, "f", elem); | |
2047 | ||
2048 | elem = builtin_type (gdbarch)->builtin_uint64; | |
2049 | append_composite_type_field (t, "u", elem); | |
2050 | ||
2051 | elem = builtin_type (gdbarch)->builtin_int64; | |
2052 | append_composite_type_field (t, "s", elem); | |
2053 | ||
2054 | tdep->vnd_type = t; | |
2055 | } | |
2056 | ||
2057 | return tdep->vnd_type; | |
2058 | } | |
2059 | ||
2060 | /* Return the type for an AdvSISD S register. */ | |
2061 | ||
2062 | static struct type * | |
2063 | aarch64_vns_type (struct gdbarch *gdbarch) | |
2064 | { | |
08106042 | 2065 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2066 | |
2067 | if (tdep->vns_type == NULL) | |
2068 | { | |
2069 | struct type *t; | |
2070 | struct type *elem; | |
2071 | ||
2072 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
2073 | TYPE_CODE_UNION); | |
2074 | ||
2075 | elem = builtin_type (gdbarch)->builtin_float; | |
2076 | append_composite_type_field (t, "f", elem); | |
2077 | ||
2078 | elem = builtin_type (gdbarch)->builtin_uint32; | |
2079 | append_composite_type_field (t, "u", elem); | |
2080 | ||
2081 | elem = builtin_type (gdbarch)->builtin_int32; | |
2082 | append_composite_type_field (t, "s", elem); | |
2083 | ||
2084 | tdep->vns_type = t; | |
2085 | } | |
2086 | ||
2087 | return tdep->vns_type; | |
2088 | } | |
2089 | ||
2090 | /* Return the type for an AdvSISD H register. */ | |
2091 | ||
2092 | static struct type * | |
2093 | aarch64_vnh_type (struct gdbarch *gdbarch) | |
2094 | { | |
08106042 | 2095 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2096 | |
2097 | if (tdep->vnh_type == NULL) | |
2098 | { | |
2099 | struct type *t; | |
2100 | struct type *elem; | |
2101 | ||
2102 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
2103 | TYPE_CODE_UNION); | |
2104 | ||
5291fe3c SP |
2105 | elem = builtin_type (gdbarch)->builtin_bfloat16; |
2106 | append_composite_type_field (t, "bf", elem); | |
2107 | ||
a6d0f249 AH |
2108 | elem = builtin_type (gdbarch)->builtin_half; |
2109 | append_composite_type_field (t, "f", elem); | |
2110 | ||
07b287a0 MS |
2111 | elem = builtin_type (gdbarch)->builtin_uint16; |
2112 | append_composite_type_field (t, "u", elem); | |
2113 | ||
2114 | elem = builtin_type (gdbarch)->builtin_int16; | |
2115 | append_composite_type_field (t, "s", elem); | |
2116 | ||
2117 | tdep->vnh_type = t; | |
2118 | } | |
2119 | ||
2120 | return tdep->vnh_type; | |
2121 | } | |
2122 | ||
2123 | /* Return the type for an AdvSISD B register. */ | |
2124 | ||
2125 | static struct type * | |
2126 | aarch64_vnb_type (struct gdbarch *gdbarch) | |
2127 | { | |
08106042 | 2128 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2129 | |
2130 | if (tdep->vnb_type == NULL) | |
2131 | { | |
2132 | struct type *t; | |
2133 | struct type *elem; | |
2134 | ||
2135 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
2136 | TYPE_CODE_UNION); | |
2137 | ||
2138 | elem = builtin_type (gdbarch)->builtin_uint8; | |
2139 | append_composite_type_field (t, "u", elem); | |
2140 | ||
2141 | elem = builtin_type (gdbarch)->builtin_int8; | |
2142 | append_composite_type_field (t, "s", elem); | |
2143 | ||
2144 | tdep->vnb_type = t; | |
2145 | } | |
2146 | ||
2147 | return tdep->vnb_type; | |
2148 | } | |
2149 | ||
63bad7b6 AH |
2150 | /* Return the type for an AdvSISD V register. */ |
2151 | ||
2152 | static struct type * | |
2153 | aarch64_vnv_type (struct gdbarch *gdbarch) | |
2154 | { | |
08106042 | 2155 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 AH |
2156 | |
2157 | if (tdep->vnv_type == NULL) | |
2158 | { | |
09624f1f | 2159 | /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value |
bffa1015 AH |
2160 | slice from the non-pseudo vector registers. However NEON V registers |
2161 | are always vector registers, and need constructing as such. */ | |
2162 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2163 | ||
63bad7b6 AH |
2164 | struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv", |
2165 | TYPE_CODE_UNION); | |
2166 | ||
bffa1015 AH |
2167 | struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", |
2168 | TYPE_CODE_UNION); | |
2169 | append_composite_type_field (sub, "f", | |
2170 | init_vector_type (bt->builtin_double, 2)); | |
2171 | append_composite_type_field (sub, "u", | |
2172 | init_vector_type (bt->builtin_uint64, 2)); | |
2173 | append_composite_type_field (sub, "s", | |
2174 | init_vector_type (bt->builtin_int64, 2)); | |
2175 | append_composite_type_field (t, "d", sub); | |
2176 | ||
2177 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
2178 | TYPE_CODE_UNION); | |
2179 | append_composite_type_field (sub, "f", | |
2180 | init_vector_type (bt->builtin_float, 4)); | |
2181 | append_composite_type_field (sub, "u", | |
2182 | init_vector_type (bt->builtin_uint32, 4)); | |
2183 | append_composite_type_field (sub, "s", | |
2184 | init_vector_type (bt->builtin_int32, 4)); | |
2185 | append_composite_type_field (t, "s", sub); | |
2186 | ||
2187 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
2188 | TYPE_CODE_UNION); | |
5291fe3c SP |
2189 | append_composite_type_field (sub, "bf", |
2190 | init_vector_type (bt->builtin_bfloat16, 8)); | |
a6d0f249 AH |
2191 | append_composite_type_field (sub, "f", |
2192 | init_vector_type (bt->builtin_half, 8)); | |
bffa1015 AH |
2193 | append_composite_type_field (sub, "u", |
2194 | init_vector_type (bt->builtin_uint16, 8)); | |
2195 | append_composite_type_field (sub, "s", | |
2196 | init_vector_type (bt->builtin_int16, 8)); | |
2197 | append_composite_type_field (t, "h", sub); | |
2198 | ||
2199 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
2200 | TYPE_CODE_UNION); | |
2201 | append_composite_type_field (sub, "u", | |
2202 | init_vector_type (bt->builtin_uint8, 16)); | |
2203 | append_composite_type_field (sub, "s", | |
2204 | init_vector_type (bt->builtin_int8, 16)); | |
2205 | append_composite_type_field (t, "b", sub); | |
2206 | ||
2207 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
2208 | TYPE_CODE_UNION); | |
2209 | append_composite_type_field (sub, "u", | |
2210 | init_vector_type (bt->builtin_uint128, 1)); | |
2211 | append_composite_type_field (sub, "s", | |
2212 | init_vector_type (bt->builtin_int128, 1)); | |
2213 | append_composite_type_field (t, "q", sub); | |
63bad7b6 AH |
2214 | |
2215 | tdep->vnv_type = t; | |
2216 | } | |
2217 | ||
2218 | return tdep->vnv_type; | |
2219 | } | |
2220 | ||
07b287a0 MS |
2221 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ |
2222 | ||
2223 | static int | |
2224 | aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
2225 | { | |
08106042 | 2226 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
34dcc7cf | 2227 | |
07b287a0 MS |
2228 | if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30) |
2229 | return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0; | |
2230 | ||
2231 | if (reg == AARCH64_DWARF_SP) | |
2232 | return AARCH64_SP_REGNUM; | |
2233 | ||
1fe84861 YY |
2234 | if (reg == AARCH64_DWARF_PC) |
2235 | return AARCH64_PC_REGNUM; | |
2236 | ||
07b287a0 MS |
2237 | if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31) |
2238 | return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0; | |
2239 | ||
65d4cada AH |
2240 | if (reg == AARCH64_DWARF_SVE_VG) |
2241 | return AARCH64_SVE_VG_REGNUM; | |
2242 | ||
2243 | if (reg == AARCH64_DWARF_SVE_FFR) | |
2244 | return AARCH64_SVE_FFR_REGNUM; | |
2245 | ||
2246 | if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15) | |
2247 | return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0; | |
2248 | ||
2249 | if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15) | |
2250 | return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0; | |
2251 | ||
34dcc7cf AH |
2252 | if (tdep->has_pauth ()) |
2253 | { | |
c9cd8ca4 LM |
2254 | if (reg == AARCH64_DWARF_RA_SIGN_STATE) |
2255 | return tdep->ra_sign_state_regnum; | |
34dcc7cf AH |
2256 | } |
2257 | ||
07b287a0 MS |
2258 | return -1; |
2259 | } | |
07b287a0 MS |
2260 | |
2261 | /* Implement the "print_insn" gdbarch method. */ | |
2262 | ||
2263 | static int | |
2264 | aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info) | |
2265 | { | |
2266 | info->symbols = NULL; | |
6394c606 | 2267 | return default_print_insn (memaddr, info); |
07b287a0 MS |
2268 | } |
2269 | ||
2270 | /* AArch64 BRK software debug mode instruction. | |
2271 | Note that AArch64 code is always little-endian. | |
2272 | 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */ | |
04180708 | 2273 | constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; |
07b287a0 | 2274 | |
04180708 | 2275 | typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint; |
07b287a0 MS |
2276 | |
2277 | /* Extract from an array REGS containing the (raw) register state a | |
2278 | function return value of type TYPE, and copy that, in virtual | |
2279 | format, into VALBUF. */ | |
2280 | ||
2281 | static void | |
2282 | aarch64_extract_return_value (struct type *type, struct regcache *regs, | |
2283 | gdb_byte *valbuf) | |
2284 | { | |
ac7936df | 2285 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 | 2286 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4f4aedeb AH |
2287 | int elements; |
2288 | struct type *fundamental_type; | |
07b287a0 | 2289 | |
4f4aedeb AH |
2290 | if (aapcs_is_vfp_call_or_return_candidate (type, &elements, |
2291 | &fundamental_type)) | |
07b287a0 | 2292 | { |
df86565b | 2293 | int len = fundamental_type->length (); |
4f4aedeb AH |
2294 | |
2295 | for (int i = 0; i < elements; i++) | |
2296 | { | |
2297 | int regno = AARCH64_V0_REGNUM + i; | |
3ff2c72e AH |
2298 | /* Enough space for a full vector register. */ |
2299 | gdb_byte buf[register_size (gdbarch, regno)]; | |
2300 | gdb_assert (len <= sizeof (buf)); | |
4f4aedeb | 2301 | |
c6185dce SM |
2302 | aarch64_debug_printf |
2303 | ("read HFA or HVA return value element %d from %s", | |
2304 | i + 1, gdbarch_register_name (gdbarch, regno)); | |
2305 | ||
4f4aedeb | 2306 | regs->cooked_read (regno, buf); |
07b287a0 | 2307 | |
4f4aedeb AH |
2308 | memcpy (valbuf, buf, len); |
2309 | valbuf += len; | |
2310 | } | |
07b287a0 | 2311 | } |
78134374 SM |
2312 | else if (type->code () == TYPE_CODE_INT |
2313 | || type->code () == TYPE_CODE_CHAR | |
2314 | || type->code () == TYPE_CODE_BOOL | |
2315 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 2316 | || TYPE_IS_REFERENCE (type) |
78134374 | 2317 | || type->code () == TYPE_CODE_ENUM) |
07b287a0 | 2318 | { |
6471e7d2 | 2319 | /* If the type is a plain integer, then the access is |
07b287a0 MS |
2320 | straight-forward. Otherwise we have to play around a bit |
2321 | more. */ | |
df86565b | 2322 | int len = type->length (); |
07b287a0 MS |
2323 | int regno = AARCH64_X0_REGNUM; |
2324 | ULONGEST tmp; | |
2325 | ||
2326 | while (len > 0) | |
2327 | { | |
2328 | /* By using store_unsigned_integer we avoid having to do | |
2329 | anything special for small big-endian values. */ | |
2330 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2331 | store_unsigned_integer (valbuf, | |
2332 | (len > X_REGISTER_SIZE | |
2333 | ? X_REGISTER_SIZE : len), byte_order, tmp); | |
2334 | len -= X_REGISTER_SIZE; | |
2335 | valbuf += X_REGISTER_SIZE; | |
2336 | } | |
2337 | } | |
07b287a0 MS |
2338 | else |
2339 | { | |
2340 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
2341 | been stored to word-aligned memory and then loaded into |
2342 | registers with 64-bit load instruction(s). */ | |
df86565b | 2343 | int len = type->length (); |
07b287a0 MS |
2344 | int regno = AARCH64_X0_REGNUM; |
2345 | bfd_byte buf[X_REGISTER_SIZE]; | |
2346 | ||
2347 | while (len > 0) | |
2348 | { | |
dca08e1f | 2349 | regs->cooked_read (regno++, buf); |
07b287a0 MS |
2350 | memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); |
2351 | len -= X_REGISTER_SIZE; | |
2352 | valbuf += X_REGISTER_SIZE; | |
2353 | } | |
2354 | } | |
2355 | } | |
2356 | ||
2357 | ||
2358 | /* Will a function return an aggregate type in memory or in a | |
2359 | register? Return 0 if an aggregate type can be returned in a | |
2360 | register, 1 if it must be returned in memory. */ | |
2361 | ||
2362 | static int | |
2363 | aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
2364 | { | |
f168693b | 2365 | type = check_typedef (type); |
4f4aedeb AH |
2366 | int elements; |
2367 | struct type *fundamental_type; | |
07b287a0 | 2368 | |
911627e7 TT |
2369 | if (TYPE_HAS_DYNAMIC_LENGTH (type)) |
2370 | return 1; | |
2371 | ||
4f4aedeb AH |
2372 | if (aapcs_is_vfp_call_or_return_candidate (type, &elements, |
2373 | &fundamental_type)) | |
07b287a0 | 2374 | { |
cd635f74 YQ |
2375 | /* v0-v7 are used to return values and one register is allocated |
2376 | for one member. However, HFA or HVA has at most four members. */ | |
07b287a0 MS |
2377 | return 0; |
2378 | } | |
2379 | ||
df86565b | 2380 | if (type->length () > 16 |
bab22d06 | 2381 | || !language_pass_by_reference (type).trivially_copyable) |
07b287a0 MS |
2382 | { |
2383 | /* PCS B.6 Aggregates larger than 16 bytes are passed by | |
dda83cd7 | 2384 | invisible reference. */ |
07b287a0 MS |
2385 | |
2386 | return 1; | |
2387 | } | |
2388 | ||
2389 | return 0; | |
2390 | } | |
2391 | ||
2392 | /* Write into appropriate registers a function return value of type | |
2393 | TYPE, given in virtual format. */ | |
2394 | ||
2395 | static void | |
2396 | aarch64_store_return_value (struct type *type, struct regcache *regs, | |
2397 | const gdb_byte *valbuf) | |
2398 | { | |
ac7936df | 2399 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 | 2400 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4f4aedeb AH |
2401 | int elements; |
2402 | struct type *fundamental_type; | |
07b287a0 | 2403 | |
4f4aedeb AH |
2404 | if (aapcs_is_vfp_call_or_return_candidate (type, &elements, |
2405 | &fundamental_type)) | |
07b287a0 | 2406 | { |
df86565b | 2407 | int len = fundamental_type->length (); |
4f4aedeb AH |
2408 | |
2409 | for (int i = 0; i < elements; i++) | |
2410 | { | |
2411 | int regno = AARCH64_V0_REGNUM + i; | |
3ff2c72e AH |
2412 | /* Enough space for a full vector register. */ |
2413 | gdb_byte tmpbuf[register_size (gdbarch, regno)]; | |
2414 | gdb_assert (len <= sizeof (tmpbuf)); | |
4f4aedeb | 2415 | |
c6185dce SM |
2416 | aarch64_debug_printf |
2417 | ("write HFA or HVA return value element %d to %s", | |
2418 | i + 1, gdbarch_register_name (gdbarch, regno)); | |
07b287a0 | 2419 | |
4f4aedeb AH |
2420 | memcpy (tmpbuf, valbuf, |
2421 | len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len); | |
2422 | regs->cooked_write (regno, tmpbuf); | |
2423 | valbuf += len; | |
2424 | } | |
07b287a0 | 2425 | } |
78134374 SM |
2426 | else if (type->code () == TYPE_CODE_INT |
2427 | || type->code () == TYPE_CODE_CHAR | |
2428 | || type->code () == TYPE_CODE_BOOL | |
2429 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 2430 | || TYPE_IS_REFERENCE (type) |
78134374 | 2431 | || type->code () == TYPE_CODE_ENUM) |
07b287a0 | 2432 | { |
df86565b | 2433 | if (type->length () <= X_REGISTER_SIZE) |
07b287a0 MS |
2434 | { |
2435 | /* Values of one word or less are zero/sign-extended and | |
2436 | returned in r0. */ | |
2437 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2438 | LONGEST val = unpack_long (type, valbuf); | |
2439 | ||
2440 | store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val); | |
b66f5587 | 2441 | regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf); |
07b287a0 MS |
2442 | } |
2443 | else | |
2444 | { | |
2445 | /* Integral values greater than one word are stored in | |
2446 | consecutive registers starting with r0. This will always | |
2447 | be a multiple of the regiser size. */ | |
df86565b | 2448 | int len = type->length (); |
07b287a0 MS |
2449 | int regno = AARCH64_X0_REGNUM; |
2450 | ||
2451 | while (len > 0) | |
2452 | { | |
b66f5587 | 2453 | regs->cooked_write (regno++, valbuf); |
07b287a0 MS |
2454 | len -= X_REGISTER_SIZE; |
2455 | valbuf += X_REGISTER_SIZE; | |
2456 | } | |
2457 | } | |
2458 | } | |
07b287a0 MS |
2459 | else |
2460 | { | |
2461 | /* For a structure or union the behaviour is as if the value had | |
2462 | been stored to word-aligned memory and then loaded into | |
2463 | registers with 64-bit load instruction(s). */ | |
df86565b | 2464 | int len = type->length (); |
07b287a0 MS |
2465 | int regno = AARCH64_X0_REGNUM; |
2466 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2467 | ||
2468 | while (len > 0) | |
2469 | { | |
2470 | memcpy (tmpbuf, valbuf, | |
2471 | len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
b66f5587 | 2472 | regs->cooked_write (regno++, tmpbuf); |
07b287a0 MS |
2473 | len -= X_REGISTER_SIZE; |
2474 | valbuf += X_REGISTER_SIZE; | |
2475 | } | |
2476 | } | |
2477 | } | |
2478 | ||
2479 | /* Implement the "return_value" gdbarch method. */ | |
2480 | ||
2481 | static enum return_value_convention | |
2482 | aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value, | |
2483 | struct type *valtype, struct regcache *regcache, | |
5cb0f2d5 | 2484 | struct value **read_value, const gdb_byte *writebuf) |
07b287a0 | 2485 | { |
78134374 SM |
2486 | if (valtype->code () == TYPE_CODE_STRUCT |
2487 | || valtype->code () == TYPE_CODE_UNION | |
2488 | || valtype->code () == TYPE_CODE_ARRAY) | |
07b287a0 MS |
2489 | { |
2490 | if (aarch64_return_in_memory (gdbarch, valtype)) | |
2491 | { | |
bab22d06 LM |
2492 | /* From the AAPCS64's Result Return section: |
2493 | ||
2494 | "Otherwise, the caller shall reserve a block of memory of | |
2495 | sufficient size and alignment to hold the result. The address | |
2496 | of the memory block shall be passed as an additional argument to | |
2497 | the function in x8. */ | |
2498 | ||
c6185dce | 2499 | aarch64_debug_printf ("return value in memory"); |
bab22d06 | 2500 | |
911627e7 | 2501 | if (read_value != nullptr) |
bab22d06 LM |
2502 | { |
2503 | CORE_ADDR addr; | |
2504 | ||
2505 | regcache->cooked_read (AARCH64_STRUCT_RETURN_REGNUM, &addr); | |
911627e7 | 2506 | *read_value = value_at_non_lval (valtype, addr); |
bab22d06 LM |
2507 | } |
2508 | ||
2509 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
07b287a0 MS |
2510 | } |
2511 | } | |
2512 | ||
2513 | if (writebuf) | |
2514 | aarch64_store_return_value (valtype, regcache, writebuf); | |
2515 | ||
911627e7 TT |
2516 | if (read_value) |
2517 | { | |
317c3ed9 | 2518 | *read_value = value::allocate (valtype); |
911627e7 | 2519 | aarch64_extract_return_value (valtype, regcache, |
bbe912ba | 2520 | (*read_value)->contents_raw ().data ()); |
911627e7 | 2521 | } |
07b287a0 | 2522 | |
c6185dce | 2523 | aarch64_debug_printf ("return value in registers"); |
07b287a0 MS |
2524 | |
2525 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2526 | } | |
2527 | ||
2528 | /* Implement the "get_longjmp_target" gdbarch method. */ | |
2529 | ||
2530 | static int | |
bd2b40ac | 2531 | aarch64_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
07b287a0 MS |
2532 | { |
2533 | CORE_ADDR jb_addr; | |
2534 | gdb_byte buf[X_REGISTER_SIZE]; | |
2535 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
08106042 | 2536 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2537 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2538 | ||
2539 | jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM); | |
2540 | ||
2541 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2542 | X_REGISTER_SIZE)) | |
2543 | return 0; | |
2544 | ||
2545 | *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order); | |
2546 | return 1; | |
2547 | } | |
ea873d8e PL |
2548 | |
2549 | /* Implement the "gen_return_address" gdbarch method. */ | |
2550 | ||
2551 | static void | |
2552 | aarch64_gen_return_address (struct gdbarch *gdbarch, | |
2553 | struct agent_expr *ax, struct axs_value *value, | |
2554 | CORE_ADDR scope) | |
2555 | { | |
2556 | value->type = register_type (gdbarch, AARCH64_LR_REGNUM); | |
2557 | value->kind = axs_lvalue_register; | |
2558 | value->u.reg = AARCH64_LR_REGNUM; | |
2559 | } | |
07b287a0 MS |
2560 | \f |
2561 | ||
e63ae49b LM |
2562 | /* Return TRUE if REGNUM is a W pseudo-register number. Return FALSE |
2563 | otherwise. */ | |
2564 | ||
2565 | static bool | |
2566 | is_w_pseudo_register (struct gdbarch *gdbarch, int regnum) | |
2567 | { | |
2568 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); | |
2569 | ||
2570 | if (tdep->w_pseudo_base <= regnum | |
2571 | && regnum < tdep->w_pseudo_base + tdep->w_pseudo_count) | |
2572 | return true; | |
2573 | ||
2574 | return false; | |
2575 | } | |
2576 | ||
07b287a0 MS |
2577 | /* Return the pseudo register name corresponding to register regnum. */ |
2578 | ||
2579 | static const char * | |
2580 | aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
2581 | { | |
08106042 | 2582 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 | 2583 | |
e63ae49b LM |
2584 | /* W pseudo-registers. Bottom halves of the X registers. */ |
2585 | static const char *const w_name[] = | |
2586 | { | |
2587 | "w0", "w1", "w2", "w3", | |
2588 | "w4", "w5", "w6", "w7", | |
2589 | "w8", "w9", "w10", "w11", | |
2590 | "w12", "w13", "w14", "w15", | |
2591 | "w16", "w17", "w18", "w19", | |
2592 | "w20", "w21", "w22", "w23", | |
2593 | "w24", "w25", "w26", "w27", | |
2594 | "w28", "w29", "w30", | |
2595 | }; | |
2596 | ||
07b287a0 MS |
2597 | static const char *const q_name[] = |
2598 | { | |
2599 | "q0", "q1", "q2", "q3", | |
2600 | "q4", "q5", "q6", "q7", | |
2601 | "q8", "q9", "q10", "q11", | |
2602 | "q12", "q13", "q14", "q15", | |
2603 | "q16", "q17", "q18", "q19", | |
2604 | "q20", "q21", "q22", "q23", | |
2605 | "q24", "q25", "q26", "q27", | |
2606 | "q28", "q29", "q30", "q31", | |
2607 | }; | |
2608 | ||
2609 | static const char *const d_name[] = | |
2610 | { | |
2611 | "d0", "d1", "d2", "d3", | |
2612 | "d4", "d5", "d6", "d7", | |
2613 | "d8", "d9", "d10", "d11", | |
2614 | "d12", "d13", "d14", "d15", | |
2615 | "d16", "d17", "d18", "d19", | |
2616 | "d20", "d21", "d22", "d23", | |
2617 | "d24", "d25", "d26", "d27", | |
2618 | "d28", "d29", "d30", "d31", | |
2619 | }; | |
2620 | ||
2621 | static const char *const s_name[] = | |
2622 | { | |
2623 | "s0", "s1", "s2", "s3", | |
2624 | "s4", "s5", "s6", "s7", | |
2625 | "s8", "s9", "s10", "s11", | |
2626 | "s12", "s13", "s14", "s15", | |
2627 | "s16", "s17", "s18", "s19", | |
2628 | "s20", "s21", "s22", "s23", | |
2629 | "s24", "s25", "s26", "s27", | |
2630 | "s28", "s29", "s30", "s31", | |
2631 | }; | |
2632 | ||
2633 | static const char *const h_name[] = | |
2634 | { | |
2635 | "h0", "h1", "h2", "h3", | |
2636 | "h4", "h5", "h6", "h7", | |
2637 | "h8", "h9", "h10", "h11", | |
2638 | "h12", "h13", "h14", "h15", | |
2639 | "h16", "h17", "h18", "h19", | |
2640 | "h20", "h21", "h22", "h23", | |
2641 | "h24", "h25", "h26", "h27", | |
2642 | "h28", "h29", "h30", "h31", | |
2643 | }; | |
2644 | ||
2645 | static const char *const b_name[] = | |
2646 | { | |
2647 | "b0", "b1", "b2", "b3", | |
2648 | "b4", "b5", "b6", "b7", | |
2649 | "b8", "b9", "b10", "b11", | |
2650 | "b12", "b13", "b14", "b15", | |
2651 | "b16", "b17", "b18", "b19", | |
2652 | "b20", "b21", "b22", "b23", | |
2653 | "b24", "b25", "b26", "b27", | |
2654 | "b28", "b29", "b30", "b31", | |
2655 | }; | |
2656 | ||
34dcc7cf | 2657 | int p_regnum = regnum - gdbarch_num_regs (gdbarch); |
07b287a0 | 2658 | |
34dcc7cf AH |
2659 | if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32) |
2660 | return q_name[p_regnum - AARCH64_Q0_REGNUM]; | |
07b287a0 | 2661 | |
34dcc7cf AH |
2662 | if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32) |
2663 | return d_name[p_regnum - AARCH64_D0_REGNUM]; | |
07b287a0 | 2664 | |
34dcc7cf AH |
2665 | if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32) |
2666 | return s_name[p_regnum - AARCH64_S0_REGNUM]; | |
07b287a0 | 2667 | |
34dcc7cf AH |
2668 | if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32) |
2669 | return h_name[p_regnum - AARCH64_H0_REGNUM]; | |
07b287a0 | 2670 | |
34dcc7cf AH |
2671 | if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32) |
2672 | return b_name[p_regnum - AARCH64_B0_REGNUM]; | |
07b287a0 | 2673 | |
e63ae49b LM |
2674 | /* W pseudo-registers? */ |
2675 | if (is_w_pseudo_register (gdbarch, regnum)) | |
2676 | return w_name[regnum - tdep->w_pseudo_base]; | |
2677 | ||
63bad7b6 AH |
2678 | if (tdep->has_sve ()) |
2679 | { | |
2680 | static const char *const sve_v_name[] = | |
2681 | { | |
2682 | "v0", "v1", "v2", "v3", | |
2683 | "v4", "v5", "v6", "v7", | |
2684 | "v8", "v9", "v10", "v11", | |
2685 | "v12", "v13", "v14", "v15", | |
2686 | "v16", "v17", "v18", "v19", | |
2687 | "v20", "v21", "v22", "v23", | |
2688 | "v24", "v25", "v26", "v27", | |
2689 | "v28", "v29", "v30", "v31", | |
2690 | }; | |
2691 | ||
34dcc7cf AH |
2692 | if (p_regnum >= AARCH64_SVE_V0_REGNUM |
2693 | && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
2694 | return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM]; | |
63bad7b6 AH |
2695 | } |
2696 | ||
34dcc7cf AH |
2697 | /* RA_STATE is used for unwinding only. Do not assign it a name - this |
2698 | prevents it from being read by methods such as | |
2699 | mi_cmd_trace_frame_collected. */ | |
c9cd8ca4 | 2700 | if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum) |
34dcc7cf AH |
2701 | return ""; |
2702 | ||
f34652de | 2703 | internal_error (_("aarch64_pseudo_register_name: bad register number %d"), |
34dcc7cf | 2704 | p_regnum); |
07b287a0 MS |
2705 | } |
2706 | ||
2707 | /* Implement the "pseudo_register_type" tdesc_arch_data method. */ | |
2708 | ||
2709 | static struct type * | |
2710 | aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2711 | { | |
08106042 | 2712 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 | 2713 | |
34dcc7cf | 2714 | int p_regnum = regnum - gdbarch_num_regs (gdbarch); |
07b287a0 | 2715 | |
34dcc7cf | 2716 | if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32) |
07b287a0 MS |
2717 | return aarch64_vnq_type (gdbarch); |
2718 | ||
34dcc7cf | 2719 | if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32) |
07b287a0 MS |
2720 | return aarch64_vnd_type (gdbarch); |
2721 | ||
34dcc7cf | 2722 | if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32) |
07b287a0 MS |
2723 | return aarch64_vns_type (gdbarch); |
2724 | ||
34dcc7cf | 2725 | if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32) |
07b287a0 MS |
2726 | return aarch64_vnh_type (gdbarch); |
2727 | ||
34dcc7cf | 2728 | if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32) |
07b287a0 MS |
2729 | return aarch64_vnb_type (gdbarch); |
2730 | ||
34dcc7cf AH |
2731 | if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM |
2732 | && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
63bad7b6 AH |
2733 | return aarch64_vnv_type (gdbarch); |
2734 | ||
e63ae49b LM |
2735 | /* W pseudo-registers are 32-bit. */ |
2736 | if (is_w_pseudo_register (gdbarch, regnum)) | |
2737 | return builtin_type (gdbarch)->builtin_uint32; | |
2738 | ||
c9cd8ca4 | 2739 | if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum) |
34dcc7cf AH |
2740 | return builtin_type (gdbarch)->builtin_uint64; |
2741 | ||
f34652de | 2742 | internal_error (_("aarch64_pseudo_register_type: bad register number %d"), |
34dcc7cf | 2743 | p_regnum); |
07b287a0 MS |
2744 | } |
2745 | ||
2746 | /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */ | |
2747 | ||
2748 | static int | |
2749 | aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 2750 | const struct reggroup *group) |
07b287a0 | 2751 | { |
08106042 | 2752 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 | 2753 | |
34dcc7cf | 2754 | int p_regnum = regnum - gdbarch_num_regs (gdbarch); |
07b287a0 | 2755 | |
34dcc7cf | 2756 | if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32) |
07b287a0 | 2757 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf | 2758 | else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32) |
07b287a0 MS |
2759 | return (group == all_reggroup || group == vector_reggroup |
2760 | || group == float_reggroup); | |
34dcc7cf | 2761 | else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32) |
07b287a0 MS |
2762 | return (group == all_reggroup || group == vector_reggroup |
2763 | || group == float_reggroup); | |
34dcc7cf | 2764 | else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32) |
07b287a0 | 2765 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf | 2766 | else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32) |
07b287a0 | 2767 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf AH |
2768 | else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM |
2769 | && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
63bad7b6 | 2770 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf | 2771 | /* RA_STATE is used for unwinding only. Do not assign it to any groups. */ |
c9cd8ca4 | 2772 | if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum) |
34dcc7cf | 2773 | return 0; |
07b287a0 MS |
2774 | |
2775 | return group == all_reggroup; | |
2776 | } | |
2777 | ||
3c5cd5c3 AH |
2778 | /* Helper for aarch64_pseudo_read_value. */ |
2779 | ||
2780 | static struct value * | |
63bad7b6 AH |
2781 | aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch, |
2782 | readable_regcache *regcache, int regnum_offset, | |
3c5cd5c3 AH |
2783 | int regsize, struct value *result_value) |
2784 | { | |
3c5cd5c3 AH |
2785 | unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset; |
2786 | ||
63bad7b6 AH |
2787 | /* Enough space for a full vector register. */ |
2788 | gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)]; | |
2789 | gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM); | |
2790 | ||
3c5cd5c3 | 2791 | if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID) |
d00664db TT |
2792 | result_value->mark_bytes_unavailable (0, |
2793 | result_value->type ()->length ()); | |
3c5cd5c3 | 2794 | else |
bbe912ba | 2795 | memcpy (result_value->contents_raw ().data (), reg_buf, regsize); |
63bad7b6 | 2796 | |
3c5cd5c3 AH |
2797 | return result_value; |
2798 | } | |
2799 | ||
07b287a0 MS |
2800 | /* Implement the "pseudo_register_read_value" gdbarch method. */ |
2801 | ||
2802 | static struct value * | |
3c5cd5c3 | 2803 | aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache, |
07b287a0 MS |
2804 | int regnum) |
2805 | { | |
08106042 | 2806 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
317c3ed9 | 2807 | struct value *result_value = value::allocate (register_type (gdbarch, regnum)); |
07b287a0 | 2808 | |
6f9c9d71 | 2809 | result_value->set_lval (lval_register); |
07b287a0 | 2810 | VALUE_REGNUM (result_value) = regnum; |
07b287a0 | 2811 | |
e63ae49b LM |
2812 | if (is_w_pseudo_register (gdbarch, regnum)) |
2813 | { | |
2814 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2815 | /* Default offset for little endian. */ | |
2816 | int offset = 0; | |
2817 | ||
2818 | if (byte_order == BFD_ENDIAN_BIG) | |
2819 | offset = 4; | |
2820 | ||
2821 | /* Find the correct X register to extract the data from. */ | |
2822 | int x_regnum = AARCH64_X0_REGNUM + (regnum - tdep->w_pseudo_base); | |
2823 | gdb_byte data[4]; | |
2824 | ||
2825 | /* Read the bottom 4 bytes of X. */ | |
2826 | if (regcache->raw_read_part (x_regnum, offset, 4, data) != REG_VALID) | |
d00664db | 2827 | result_value->mark_bytes_unavailable (0, 4); |
e63ae49b | 2828 | else |
bbe912ba | 2829 | memcpy (result_value->contents_raw ().data (), data, 4); |
e63ae49b LM |
2830 | |
2831 | return result_value; | |
2832 | } | |
2833 | ||
07b287a0 MS |
2834 | regnum -= gdbarch_num_regs (gdbarch); |
2835 | ||
2836 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
63bad7b6 AH |
2837 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2838 | regnum - AARCH64_Q0_REGNUM, | |
3c5cd5c3 | 2839 | Q_REGISTER_SIZE, result_value); |
07b287a0 MS |
2840 | |
2841 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
63bad7b6 AH |
2842 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2843 | regnum - AARCH64_D0_REGNUM, | |
3c5cd5c3 | 2844 | D_REGISTER_SIZE, result_value); |
07b287a0 MS |
2845 | |
2846 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
63bad7b6 AH |
2847 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2848 | regnum - AARCH64_S0_REGNUM, | |
3c5cd5c3 | 2849 | S_REGISTER_SIZE, result_value); |
07b287a0 MS |
2850 | |
2851 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
63bad7b6 AH |
2852 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2853 | regnum - AARCH64_H0_REGNUM, | |
3c5cd5c3 | 2854 | H_REGISTER_SIZE, result_value); |
07b287a0 MS |
2855 | |
2856 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
63bad7b6 AH |
2857 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2858 | regnum - AARCH64_B0_REGNUM, | |
3c5cd5c3 | 2859 | B_REGISTER_SIZE, result_value); |
07b287a0 | 2860 | |
63bad7b6 AH |
2861 | if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM |
2862 | && regnum < AARCH64_SVE_V0_REGNUM + 32) | |
2863 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, | |
2864 | regnum - AARCH64_SVE_V0_REGNUM, | |
2865 | V_REGISTER_SIZE, result_value); | |
2866 | ||
07b287a0 MS |
2867 | gdb_assert_not_reached ("regnum out of bound"); |
2868 | } | |
2869 | ||
3c5cd5c3 | 2870 | /* Helper for aarch64_pseudo_write. */ |
07b287a0 MS |
2871 | |
2872 | static void | |
63bad7b6 AH |
2873 | aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache, |
2874 | int regnum_offset, int regsize, const gdb_byte *buf) | |
07b287a0 | 2875 | { |
3c5cd5c3 | 2876 | unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset; |
07b287a0 | 2877 | |
63bad7b6 AH |
2878 | /* Enough space for a full vector register. */ |
2879 | gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)]; | |
2880 | gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM); | |
2881 | ||
07b287a0 MS |
2882 | /* Ensure the register buffer is zero, we want gdb writes of the |
2883 | various 'scalar' pseudo registers to behavior like architectural | |
2884 | writes, register width bytes are written the remainder are set to | |
2885 | zero. */ | |
63bad7b6 | 2886 | memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM)); |
07b287a0 | 2887 | |
3c5cd5c3 AH |
2888 | memcpy (reg_buf, buf, regsize); |
2889 | regcache->raw_write (v_regnum, reg_buf); | |
2890 | } | |
2891 | ||
2892 | /* Implement the "pseudo_register_write" gdbarch method. */ | |
2893 | ||
2894 | static void | |
2895 | aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2896 | int regnum, const gdb_byte *buf) | |
2897 | { | |
08106042 | 2898 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
e63ae49b LM |
2899 | |
2900 | if (is_w_pseudo_register (gdbarch, regnum)) | |
2901 | { | |
2902 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
2903 | /* Default offset for little endian. */ | |
2904 | int offset = 0; | |
2905 | ||
2906 | if (byte_order == BFD_ENDIAN_BIG) | |
2907 | offset = 4; | |
2908 | ||
2909 | /* Find the correct X register to extract the data from. */ | |
2910 | int x_regnum = AARCH64_X0_REGNUM + (regnum - tdep->w_pseudo_base); | |
2911 | ||
2912 | /* First zero-out the contents of X. */ | |
2913 | ULONGEST zero = 0; | |
2914 | regcache->raw_write (x_regnum, zero); | |
2915 | /* Write to the bottom 4 bytes of X. */ | |
2916 | regcache->raw_write_part (x_regnum, offset, 4, buf); | |
2917 | return; | |
2918 | } | |
2919 | ||
07b287a0 MS |
2920 | regnum -= gdbarch_num_regs (gdbarch); |
2921 | ||
2922 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
63bad7b6 AH |
2923 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2924 | regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE, | |
2925 | buf); | |
07b287a0 MS |
2926 | |
2927 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
63bad7b6 AH |
2928 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2929 | regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE, | |
2930 | buf); | |
07b287a0 MS |
2931 | |
2932 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
63bad7b6 AH |
2933 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2934 | regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE, | |
2935 | buf); | |
07b287a0 MS |
2936 | |
2937 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
63bad7b6 AH |
2938 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2939 | regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE, | |
2940 | buf); | |
07b287a0 MS |
2941 | |
2942 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
63bad7b6 AH |
2943 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2944 | regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE, | |
2945 | buf); | |
2946 | ||
2947 | if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM | |
2948 | && regnum < AARCH64_SVE_V0_REGNUM + 32) | |
2949 | return aarch64_pseudo_write_1 (gdbarch, regcache, | |
2950 | regnum - AARCH64_SVE_V0_REGNUM, | |
2951 | V_REGISTER_SIZE, buf); | |
07b287a0 MS |
2952 | |
2953 | gdb_assert_not_reached ("regnum out of bound"); | |
2954 | } | |
2955 | ||
07b287a0 MS |
2956 | /* Callback function for user_reg_add. */ |
2957 | ||
2958 | static struct value * | |
bd2b40ac | 2959 | value_of_aarch64_user_reg (frame_info_ptr frame, const void *baton) |
07b287a0 | 2960 | { |
9a3c8263 | 2961 | const int *reg_p = (const int *) baton; |
07b287a0 MS |
2962 | |
2963 | return value_of_register (*reg_p, frame); | |
2964 | } | |
2965 | \f | |
2966 | ||
9404b58f KM |
2967 | /* Implement the "software_single_step" gdbarch method, needed to |
2968 | single step through atomic sequences on AArch64. */ | |
2969 | ||
a0ff9e1a | 2970 | static std::vector<CORE_ADDR> |
f5ea389a | 2971 | aarch64_software_single_step (struct regcache *regcache) |
9404b58f | 2972 | { |
ac7936df | 2973 | struct gdbarch *gdbarch = regcache->arch (); |
9404b58f KM |
2974 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
2975 | const int insn_size = 4; | |
2976 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
0187a92f | 2977 | CORE_ADDR pc = regcache_read_pc (regcache); |
70ab8ccd | 2978 | CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX }; |
9404b58f KM |
2979 | CORE_ADDR loc = pc; |
2980 | CORE_ADDR closing_insn = 0; | |
94355de7 LM |
2981 | |
2982 | ULONGEST insn_from_memory; | |
2983 | if (!safe_read_memory_unsigned_integer (loc, insn_size, | |
2984 | byte_order_for_code, | |
2985 | &insn_from_memory)) | |
2986 | { | |
2987 | /* Assume we don't have a atomic sequence, as we couldn't read the | |
2988 | instruction in this location. */ | |
2989 | return {}; | |
2990 | } | |
2991 | ||
2992 | uint32_t insn = insn_from_memory; | |
9404b58f KM |
2993 | int index; |
2994 | int insn_count; | |
2995 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
2996 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
f77ee802 YQ |
2997 | aarch64_inst inst; |
2998 | ||
561a72d4 | 2999 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
a0ff9e1a | 3000 | return {}; |
9404b58f KM |
3001 | |
3002 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
f77ee802 | 3003 | if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) |
a0ff9e1a | 3004 | return {}; |
9404b58f KM |
3005 | |
3006 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
3007 | { | |
9404b58f | 3008 | loc += insn_size; |
9404b58f | 3009 | |
94355de7 LM |
3010 | if (!safe_read_memory_unsigned_integer (loc, insn_size, |
3011 | byte_order_for_code, | |
3012 | &insn_from_memory)) | |
3013 | { | |
3014 | /* Assume we don't have a atomic sequence, as we couldn't read the | |
3015 | instruction in this location. */ | |
3016 | return {}; | |
3017 | } | |
3018 | ||
3019 | insn = insn_from_memory; | |
561a72d4 | 3020 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
a0ff9e1a | 3021 | return {}; |
9404b58f | 3022 | /* Check if the instruction is a conditional branch. */ |
f77ee802 | 3023 | if (inst.opcode->iclass == condbranch) |
9404b58f | 3024 | { |
f77ee802 YQ |
3025 | gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); |
3026 | ||
9404b58f | 3027 | if (bc_insn_count >= 1) |
a0ff9e1a | 3028 | return {}; |
9404b58f KM |
3029 | |
3030 | /* It is, so we'll try to set a breakpoint at the destination. */ | |
f77ee802 | 3031 | breaks[1] = loc + inst.operands[0].imm.value; |
9404b58f KM |
3032 | |
3033 | bc_insn_count++; | |
3034 | last_breakpoint++; | |
3035 | } | |
3036 | ||
3037 | /* Look for the Store Exclusive which closes the atomic sequence. */ | |
f77ee802 | 3038 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0) |
9404b58f KM |
3039 | { |
3040 | closing_insn = loc; | |
3041 | break; | |
3042 | } | |
3043 | } | |
3044 | ||
3045 | /* We didn't find a closing Store Exclusive instruction, fall back. */ | |
3046 | if (!closing_insn) | |
a0ff9e1a | 3047 | return {}; |
9404b58f KM |
3048 | |
3049 | /* Insert breakpoint after the end of the atomic sequence. */ | |
3050 | breaks[0] = loc + insn_size; | |
3051 | ||
3052 | /* Check for duplicated breakpoints, and also check that the second | |
3053 | breakpoint is not within the atomic sequence. */ | |
3054 | if (last_breakpoint | |
3055 | && (breaks[1] == breaks[0] | |
3056 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
3057 | last_breakpoint = 0; | |
3058 | ||
a0ff9e1a SM |
3059 | std::vector<CORE_ADDR> next_pcs; |
3060 | ||
9404b58f KM |
3061 | /* Insert the breakpoint at the end of the sequence, and one at the |
3062 | destination of the conditional branch, if it exists. */ | |
3063 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 3064 | next_pcs.push_back (breaks[index]); |
9404b58f | 3065 | |
93f9a11f | 3066 | return next_pcs; |
9404b58f KM |
3067 | } |
3068 | ||
1152d984 SM |
3069 | struct aarch64_displaced_step_copy_insn_closure |
3070 | : public displaced_step_copy_insn_closure | |
b6542f81 YQ |
3071 | { |
3072 | /* It is true when condition instruction, such as B.CON, TBZ, etc, | |
3073 | is being displaced stepping. */ | |
f0c702d4 | 3074 | bool cond = false; |
b6542f81 | 3075 | |
0c271889 LM |
3076 | /* PC adjustment offset after displaced stepping. If 0, then we don't |
3077 | write the PC back, assuming the PC is already the right address. */ | |
cfba9872 | 3078 | int32_t pc_adjust = 0; |
b6542f81 YQ |
3079 | }; |
3080 | ||
3081 | /* Data when visiting instructions for displaced stepping. */ | |
3082 | ||
3083 | struct aarch64_displaced_step_data | |
3084 | { | |
3085 | struct aarch64_insn_data base; | |
3086 | ||
3087 | /* The address where the instruction will be executed at. */ | |
3088 | CORE_ADDR new_addr; | |
3089 | /* Buffer of instructions to be copied to NEW_ADDR to execute. */ | |
e935475c | 3090 | uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS]; |
b6542f81 YQ |
3091 | /* Number of instructions in INSN_BUF. */ |
3092 | unsigned insn_count; | |
3093 | /* Registers when doing displaced stepping. */ | |
3094 | struct regcache *regs; | |
3095 | ||
1152d984 | 3096 | aarch64_displaced_step_copy_insn_closure *dsc; |
b6542f81 YQ |
3097 | }; |
3098 | ||
3099 | /* Implementation of aarch64_insn_visitor method "b". */ | |
3100 | ||
3101 | static void | |
3102 | aarch64_displaced_step_b (const int is_bl, const int32_t offset, | |
3103 | struct aarch64_insn_data *data) | |
3104 | { | |
3105 | struct aarch64_displaced_step_data *dsd | |
3106 | = (struct aarch64_displaced_step_data *) data; | |
2ac09a5b | 3107 | int64_t new_offset = data->insn_addr - dsd->new_addr + offset; |
b6542f81 YQ |
3108 | |
3109 | if (can_encode_int32 (new_offset, 28)) | |
3110 | { | |
3111 | /* Emit B rather than BL, because executing BL on a new address | |
3112 | will get the wrong address into LR. In order to avoid this, | |
3113 | we emit B, and update LR if the instruction is BL. */ | |
3114 | emit_b (dsd->insn_buf, 0, new_offset); | |
3115 | dsd->insn_count++; | |
3116 | } | |
3117 | else | |
3118 | { | |
3119 | /* Write NOP. */ | |
3120 | emit_nop (dsd->insn_buf); | |
3121 | dsd->insn_count++; | |
3122 | dsd->dsc->pc_adjust = offset; | |
3123 | } | |
3124 | ||
3125 | if (is_bl) | |
3126 | { | |
3127 | /* Update LR. */ | |
3128 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, | |
3129 | data->insn_addr + 4); | |
3130 | } | |
3131 | } | |
3132 | ||
3133 | /* Implementation of aarch64_insn_visitor method "b_cond". */ | |
3134 | ||
3135 | static void | |
3136 | aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset, | |
3137 | struct aarch64_insn_data *data) | |
3138 | { | |
3139 | struct aarch64_displaced_step_data *dsd | |
3140 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
3141 | |
3142 | /* GDB has to fix up PC after displaced step this instruction | |
3143 | differently according to the condition is true or false. Instead | |
3144 | of checking COND against conditional flags, we can use | |
3145 | the following instructions, and GDB can tell how to fix up PC | |
3146 | according to the PC value. | |
3147 | ||
3148 | B.COND TAKEN ; If cond is true, then jump to TAKEN. | |
3149 | INSN1 ; | |
3150 | TAKEN: | |
3151 | INSN2 | |
3152 | */ | |
3153 | ||
3154 | emit_bcond (dsd->insn_buf, cond, 8); | |
f0c702d4 | 3155 | dsd->dsc->cond = true; |
b6542f81 YQ |
3156 | dsd->dsc->pc_adjust = offset; |
3157 | dsd->insn_count = 1; | |
3158 | } | |
3159 | ||
3160 | /* Dynamically allocate a new register. If we know the register | |
3161 | statically, we should make it a global as above instead of using this | |
3162 | helper function. */ | |
3163 | ||
3164 | static struct aarch64_register | |
3165 | aarch64_register (unsigned num, int is64) | |
3166 | { | |
3167 | return (struct aarch64_register) { num, is64 }; | |
3168 | } | |
3169 | ||
3170 | /* Implementation of aarch64_insn_visitor method "cb". */ | |
3171 | ||
3172 | static void | |
3173 | aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz, | |
3174 | const unsigned rn, int is64, | |
3175 | struct aarch64_insn_data *data) | |
3176 | { | |
3177 | struct aarch64_displaced_step_data *dsd | |
3178 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
3179 | |
3180 | /* The offset is out of range for a compare and branch | |
3181 | instruction. We can use the following instructions instead: | |
3182 | ||
3183 | CBZ xn, TAKEN ; xn == 0, then jump to TAKEN. | |
3184 | INSN1 ; | |
3185 | TAKEN: | |
3186 | INSN2 | |
3187 | */ | |
3188 | emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8); | |
3189 | dsd->insn_count = 1; | |
f0c702d4 | 3190 | dsd->dsc->cond = true; |
b6542f81 YQ |
3191 | dsd->dsc->pc_adjust = offset; |
3192 | } | |
3193 | ||
3194 | /* Implementation of aarch64_insn_visitor method "tb". */ | |
3195 | ||
3196 | static void | |
3197 | aarch64_displaced_step_tb (const int32_t offset, int is_tbnz, | |
3198 | const unsigned rt, unsigned bit, | |
3199 | struct aarch64_insn_data *data) | |
3200 | { | |
3201 | struct aarch64_displaced_step_data *dsd | |
3202 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
3203 | |
3204 | /* The offset is out of range for a test bit and branch | |
3205 | instruction We can use the following instructions instead: | |
3206 | ||
3207 | TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN. | |
3208 | INSN1 ; | |
3209 | TAKEN: | |
3210 | INSN2 | |
3211 | ||
3212 | */ | |
3213 | emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8); | |
3214 | dsd->insn_count = 1; | |
f0c702d4 | 3215 | dsd->dsc->cond = true; |
b6542f81 YQ |
3216 | dsd->dsc->pc_adjust = offset; |
3217 | } | |
3218 | ||
3219 | /* Implementation of aarch64_insn_visitor method "adr". */ | |
3220 | ||
3221 | static void | |
3222 | aarch64_displaced_step_adr (const int32_t offset, const unsigned rd, | |
3223 | const int is_adrp, struct aarch64_insn_data *data) | |
3224 | { | |
3225 | struct aarch64_displaced_step_data *dsd | |
3226 | = (struct aarch64_displaced_step_data *) data; | |
3227 | /* We know exactly the address the ADR{P,} instruction will compute. | |
3228 | We can just write it to the destination register. */ | |
3229 | CORE_ADDR address = data->insn_addr + offset; | |
3230 | ||
3231 | if (is_adrp) | |
3232 | { | |
3233 | /* Clear the lower 12 bits of the offset to get the 4K page. */ | |
3234 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
3235 | address & ~0xfff); | |
3236 | } | |
3237 | else | |
3238 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
3239 | address); | |
3240 | ||
3241 | dsd->dsc->pc_adjust = 4; | |
3242 | emit_nop (dsd->insn_buf); | |
3243 | dsd->insn_count = 1; | |
3244 | } | |
3245 | ||
3246 | /* Implementation of aarch64_insn_visitor method "ldr_literal". */ | |
3247 | ||
3248 | static void | |
3249 | aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw, | |
3250 | const unsigned rt, const int is64, | |
3251 | struct aarch64_insn_data *data) | |
3252 | { | |
3253 | struct aarch64_displaced_step_data *dsd | |
3254 | = (struct aarch64_displaced_step_data *) data; | |
3255 | CORE_ADDR address = data->insn_addr + offset; | |
3256 | struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 }; | |
3257 | ||
3258 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt, | |
3259 | address); | |
3260 | ||
3261 | if (is_sw) | |
3262 | dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1), | |
3263 | aarch64_register (rt, 1), zero); | |
3264 | else | |
3265 | dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64), | |
3266 | aarch64_register (rt, 1), zero); | |
3267 | ||
3268 | dsd->dsc->pc_adjust = 4; | |
3269 | } | |
3270 | ||
3271 | /* Implementation of aarch64_insn_visitor method "others". */ | |
3272 | ||
3273 | static void | |
3274 | aarch64_displaced_step_others (const uint32_t insn, | |
3275 | struct aarch64_insn_data *data) | |
3276 | { | |
3277 | struct aarch64_displaced_step_data *dsd | |
3278 | = (struct aarch64_displaced_step_data *) data; | |
3279 | ||
807f647c MM |
3280 | uint32_t masked_insn = (insn & CLEAR_Rn_MASK); |
3281 | if (masked_insn == BLR) | |
b6542f81 | 3282 | { |
807f647c MM |
3283 | /* Emit a BR to the same register and then update LR to the original |
3284 | address (similar to aarch64_displaced_step_b). */ | |
3285 | aarch64_emit_insn (dsd->insn_buf, insn & 0xffdfffff); | |
3286 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, | |
3287 | data->insn_addr + 4); | |
b6542f81 | 3288 | } |
807f647c MM |
3289 | else |
3290 | aarch64_emit_insn (dsd->insn_buf, insn); | |
3291 | dsd->insn_count = 1; | |
3292 | ||
3293 | if (masked_insn == RET || masked_insn == BR || masked_insn == BLR) | |
3294 | dsd->dsc->pc_adjust = 0; | |
b6542f81 YQ |
3295 | else |
3296 | dsd->dsc->pc_adjust = 4; | |
3297 | } | |
3298 | ||
3299 | static const struct aarch64_insn_visitor visitor = | |
3300 | { | |
3301 | aarch64_displaced_step_b, | |
3302 | aarch64_displaced_step_b_cond, | |
3303 | aarch64_displaced_step_cb, | |
3304 | aarch64_displaced_step_tb, | |
3305 | aarch64_displaced_step_adr, | |
3306 | aarch64_displaced_step_ldr_literal, | |
3307 | aarch64_displaced_step_others, | |
3308 | }; | |
3309 | ||
3310 | /* Implement the "displaced_step_copy_insn" gdbarch method. */ | |
3311 | ||
1152d984 | 3312 | displaced_step_copy_insn_closure_up |
b6542f81 YQ |
3313 | aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, |
3314 | CORE_ADDR from, CORE_ADDR to, | |
3315 | struct regcache *regs) | |
3316 | { | |
b6542f81 | 3317 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
b6542f81 | 3318 | struct aarch64_displaced_step_data dsd; |
c86a40c6 | 3319 | aarch64_inst inst; |
94355de7 LM |
3320 | ULONGEST insn_from_memory; |
3321 | ||
3322 | if (!safe_read_memory_unsigned_integer (from, 4, byte_order_for_code, | |
3323 | &insn_from_memory)) | |
3324 | return nullptr; | |
3325 | ||
3326 | uint32_t insn = insn_from_memory; | |
c86a40c6 | 3327 | |
561a72d4 | 3328 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
c86a40c6 | 3329 | return NULL; |
b6542f81 YQ |
3330 | |
3331 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
c86a40c6 | 3332 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22)) |
b6542f81 YQ |
3333 | { |
3334 | /* We can't displaced step atomic sequences. */ | |
3335 | return NULL; | |
3336 | } | |
3337 | ||
1152d984 SM |
3338 | std::unique_ptr<aarch64_displaced_step_copy_insn_closure> dsc |
3339 | (new aarch64_displaced_step_copy_insn_closure); | |
b6542f81 YQ |
3340 | dsd.base.insn_addr = from; |
3341 | dsd.new_addr = to; | |
3342 | dsd.regs = regs; | |
cfba9872 | 3343 | dsd.dsc = dsc.get (); |
034f1a81 | 3344 | dsd.insn_count = 0; |
b6542f81 YQ |
3345 | aarch64_relocate_instruction (insn, &visitor, |
3346 | (struct aarch64_insn_data *) &dsd); | |
e935475c | 3347 | gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS); |
b6542f81 YQ |
3348 | |
3349 | if (dsd.insn_count != 0) | |
3350 | { | |
3351 | int i; | |
3352 | ||
3353 | /* Instruction can be relocated to scratch pad. Copy | |
3354 | relocated instruction(s) there. */ | |
3355 | for (i = 0; i < dsd.insn_count; i++) | |
3356 | { | |
136821d9 SM |
3357 | displaced_debug_printf ("writing insn %.8x at %s", |
3358 | dsd.insn_buf[i], | |
3359 | paddress (gdbarch, to + i * 4)); | |
3360 | ||
b6542f81 YQ |
3361 | write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code, |
3362 | (ULONGEST) dsd.insn_buf[i]); | |
3363 | } | |
3364 | } | |
3365 | else | |
3366 | { | |
b6542f81 YQ |
3367 | dsc = NULL; |
3368 | } | |
3369 | ||
6d0cf446 | 3370 | /* This is a work around for a problem with g++ 4.8. */ |
1152d984 | 3371 | return displaced_step_copy_insn_closure_up (dsc.release ()); |
b6542f81 YQ |
3372 | } |
3373 | ||
3374 | /* Implement the "displaced_step_fixup" gdbarch method. */ | |
3375 | ||
3376 | void | |
3377 | aarch64_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 3378 | struct displaced_step_copy_insn_closure *dsc_, |
b6542f81 | 3379 | CORE_ADDR from, CORE_ADDR to, |
cf141dd8 | 3380 | struct regcache *regs, bool completed_p) |
b6542f81 | 3381 | { |
cf141dd8 | 3382 | CORE_ADDR pc = regcache_read_pc (regs); |
cfba9872 | 3383 | |
cf141dd8 AB |
3384 | /* If the displaced instruction didn't complete successfully then all we |
3385 | need to do is restore the program counter. */ | |
3386 | if (!completed_p) | |
3387 | { | |
3388 | pc = from + (pc - to); | |
3389 | regcache_write_pc (regs, pc); | |
3390 | return; | |
3391 | } | |
0c271889 | 3392 | |
cf141dd8 AB |
3393 | aarch64_displaced_step_copy_insn_closure *dsc |
3394 | = (aarch64_displaced_step_copy_insn_closure *) dsc_; | |
0c271889 | 3395 | |
136821d9 SM |
3396 | displaced_debug_printf ("PC after stepping: %s (was %s).", |
3397 | paddress (gdbarch, pc), paddress (gdbarch, to)); | |
1ab139e5 | 3398 | |
b6542f81 YQ |
3399 | if (dsc->cond) |
3400 | { | |
136821d9 SM |
3401 | displaced_debug_printf ("[Conditional] pc_adjust before: %d", |
3402 | dsc->pc_adjust); | |
1ab139e5 | 3403 | |
b6542f81 YQ |
3404 | if (pc - to == 8) |
3405 | { | |
3406 | /* Condition is true. */ | |
3407 | } | |
3408 | else if (pc - to == 4) | |
3409 | { | |
3410 | /* Condition is false. */ | |
3411 | dsc->pc_adjust = 4; | |
3412 | } | |
3413 | else | |
3414 | gdb_assert_not_reached ("Unexpected PC value after displaced stepping"); | |
1ab139e5 | 3415 | |
136821d9 SM |
3416 | displaced_debug_printf ("[Conditional] pc_adjust after: %d", |
3417 | dsc->pc_adjust); | |
b6542f81 YQ |
3418 | } |
3419 | ||
136821d9 SM |
3420 | displaced_debug_printf ("%s PC by %d", |
3421 | dsc->pc_adjust ? "adjusting" : "not adjusting", | |
3422 | dsc->pc_adjust); | |
1ab139e5 | 3423 | |
b6542f81 YQ |
3424 | if (dsc->pc_adjust != 0) |
3425 | { | |
0c271889 LM |
3426 | /* Make sure the previous instruction was executed (that is, the PC |
3427 | has changed). If the PC didn't change, then discard the adjustment | |
3428 | offset. Otherwise we may skip an instruction before its execution | |
3429 | took place. */ | |
3430 | if ((pc - to) == 0) | |
1ab139e5 | 3431 | { |
136821d9 | 3432 | displaced_debug_printf ("PC did not move. Discarding PC adjustment."); |
1ab139e5 LM |
3433 | dsc->pc_adjust = 0; |
3434 | } | |
0c271889 | 3435 | |
136821d9 SM |
3436 | displaced_debug_printf ("fixup: set PC to %s:%d", |
3437 | paddress (gdbarch, from), dsc->pc_adjust); | |
3438 | ||
b6542f81 YQ |
3439 | regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM, |
3440 | from + dsc->pc_adjust); | |
3441 | } | |
3442 | } | |
3443 | ||
3444 | /* Implement the "displaced_step_hw_singlestep" gdbarch method. */ | |
3445 | ||
07fbbd01 | 3446 | bool |
40a53766 | 3447 | aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch) |
b6542f81 | 3448 | { |
07fbbd01 | 3449 | return true; |
b6542f81 YQ |
3450 | } |
3451 | ||
95228a0d AH |
3452 | /* Get the correct target description for the given VQ value. |
3453 | If VQ is zero then it is assumed SVE is not supported. | |
c1bd443b LM |
3454 | (It is not possible to set VQ to zero on an SVE system). |
3455 | ||
414d5848 JB |
3456 | MTE_P indicates the presence of the Memory Tagging Extension feature. |
3457 | ||
3458 | TLS_P indicates the presence of the Thread Local Storage feature. */ | |
da434ccb AH |
3459 | |
3460 | const target_desc * | |
0ee6b1c5 | 3461 | aarch64_read_description (const aarch64_features &features) |
da434ccb | 3462 | { |
0ee6b1c5 JB |
3463 | if (features.vq > AARCH64_MAX_SVE_VQ) |
3464 | error (_("VQ is %" PRIu64 ", maximum supported value is %d"), features.vq, | |
95228a0d AH |
3465 | AARCH64_MAX_SVE_VQ); |
3466 | ||
0ee6b1c5 | 3467 | struct target_desc *tdesc = tdesc_aarch64_map[features]; |
da434ccb | 3468 | |
95228a0d AH |
3469 | if (tdesc == NULL) |
3470 | { | |
0ee6b1c5 JB |
3471 | tdesc = aarch64_create_target_description (features); |
3472 | tdesc_aarch64_map[features] = tdesc; | |
95228a0d | 3473 | } |
da434ccb | 3474 | |
95228a0d | 3475 | return tdesc; |
da434ccb AH |
3476 | } |
3477 | ||
ba2d2bb2 AH |
3478 | /* Return the VQ used when creating the target description TDESC. */ |
3479 | ||
1332a140 | 3480 | static uint64_t |
ba2d2bb2 AH |
3481 | aarch64_get_tdesc_vq (const struct target_desc *tdesc) |
3482 | { | |
3483 | const struct tdesc_feature *feature_sve; | |
3484 | ||
3485 | if (!tdesc_has_registers (tdesc)) | |
3486 | return 0; | |
3487 | ||
3488 | feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); | |
3489 | ||
3490 | if (feature_sve == nullptr) | |
3491 | return 0; | |
3492 | ||
12863263 AH |
3493 | uint64_t vl = tdesc_register_bitsize (feature_sve, |
3494 | aarch64_sve_register_names[0]) / 8; | |
ba2d2bb2 AH |
3495 | return sve_vq_from_vl (vl); |
3496 | } | |
3497 | ||
4f3681cc TJB |
3498 | /* Get the AArch64 features present in the given target description. */ |
3499 | ||
3500 | aarch64_features | |
3501 | aarch64_features_from_target_desc (const struct target_desc *tdesc) | |
3502 | { | |
3503 | aarch64_features features; | |
3504 | ||
3505 | if (tdesc == nullptr) | |
3506 | return features; | |
3507 | ||
3508 | features.vq = aarch64_get_tdesc_vq (tdesc); | |
acdf6071 LM |
3509 | |
3510 | /* We need to look for a couple pauth feature name variations. */ | |
4f3681cc TJB |
3511 | features.pauth |
3512 | = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth") != nullptr); | |
acdf6071 LM |
3513 | |
3514 | if (!features.pauth) | |
3515 | features.pauth = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth_v2") | |
3516 | != nullptr); | |
3517 | ||
4f3681cc TJB |
3518 | features.mte |
3519 | = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.mte") != nullptr); | |
ba60b963 LM |
3520 | |
3521 | const struct tdesc_feature *tls_feature | |
3522 | = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.tls"); | |
3523 | ||
3524 | if (tls_feature != nullptr) | |
3525 | { | |
3526 | /* We have TLS registers. Find out how many. */ | |
3527 | if (tdesc_unnumbered_register (tls_feature, "tpidr2")) | |
3528 | features.tls = 2; | |
3529 | else | |
3530 | features.tls = 1; | |
3531 | } | |
4f3681cc TJB |
3532 | |
3533 | return features; | |
3534 | } | |
3535 | ||
76bed0fd AH |
3536 | /* Implement the "cannot_store_register" gdbarch method. */ |
3537 | ||
3538 | static int | |
3539 | aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum) | |
3540 | { | |
08106042 | 3541 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
76bed0fd AH |
3542 | |
3543 | if (!tdep->has_pauth ()) | |
3544 | return 0; | |
3545 | ||
3546 | /* Pointer authentication registers are read-only. */ | |
6d002087 LM |
3547 | return (regnum >= tdep->pauth_reg_base |
3548 | && regnum < tdep->pauth_reg_base + tdep->pauth_reg_count); | |
76bed0fd AH |
3549 | } |
3550 | ||
da729c5c TT |
3551 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
3552 | ||
3553 | static int | |
3554 | aarch64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3555 | { | |
3556 | CORE_ADDR func_start, func_end; | |
3557 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3558 | return 0; | |
3559 | ||
3560 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
94355de7 LM |
3561 | |
3562 | ULONGEST insn_from_memory; | |
3563 | if (!safe_read_memory_unsigned_integer (pc, 4, byte_order_for_code, | |
3564 | &insn_from_memory)) | |
3565 | return 0; | |
3566 | ||
3567 | uint32_t insn = insn_from_memory; | |
da729c5c TT |
3568 | |
3569 | aarch64_inst inst; | |
3570 | if (aarch64_decode_insn (insn, &inst, 1, nullptr) != 0) | |
3571 | return 0; | |
3572 | ||
3573 | return streq (inst.opcode->name, "ret"); | |
3574 | } | |
3575 | ||
6d002087 LM |
3576 | /* AArch64 implementation of the remove_non_address_bits gdbarch hook. Remove |
3577 | non address bits from a pointer value. */ | |
3578 | ||
3579 | static CORE_ADDR | |
3580 | aarch64_remove_non_address_bits (struct gdbarch *gdbarch, CORE_ADDR pointer) | |
3581 | { | |
6d002087 | 3582 | /* By default, we assume TBI and discard the top 8 bits plus the VA range |
ef139898 LM |
3583 | select bit (55). Below we try to fetch information about pointer |
3584 | authentication masks in order to make non-address removal more | |
3585 | precise. */ | |
6d002087 LM |
3586 | CORE_ADDR mask = AARCH64_TOP_BITS_MASK; |
3587 | ||
ef139898 LM |
3588 | /* Check if we have an inferior first. If not, just use the default |
3589 | mask. | |
6d002087 | 3590 | |
ef139898 LM |
3591 | We use the inferior_ptid here because the pointer authentication masks |
3592 | should be the same across threads of a process. Since we may not have | |
3593 | access to the current thread (gdb may have switched to no inferiors | |
3594 | momentarily), we use the inferior ptid. */ | |
3595 | if (inferior_ptid != null_ptid) | |
3596 | { | |
3597 | /* If we do have an inferior, attempt to fetch its thread's thread_info | |
3598 | struct. */ | |
9213a6d7 | 3599 | thread_info *thread = current_inferior ()->find_thread (inferior_ptid); |
6d002087 | 3600 | |
ef139898 LM |
3601 | /* If the thread is running, we will not be able to fetch the mask |
3602 | registers. */ | |
3603 | if (thread != nullptr && thread->state != THREAD_RUNNING) | |
6d002087 | 3604 | { |
ef139898 LM |
3605 | /* Otherwise, fetch the register cache and the masks. */ |
3606 | struct regcache *regs | |
3607 | = get_thread_regcache (current_inferior ()->process_target (), | |
3608 | inferior_ptid); | |
3609 | ||
3610 | /* Use the gdbarch from the register cache to check for pointer | |
3611 | authentication support, as it matches the features found in | |
3612 | that particular thread. */ | |
3613 | aarch64_gdbarch_tdep *tdep | |
3614 | = gdbarch_tdep<aarch64_gdbarch_tdep> (regs->arch ()); | |
6d002087 | 3615 | |
ef139898 LM |
3616 | /* Is there pointer authentication support? */ |
3617 | if (tdep->has_pauth ()) | |
3618 | { | |
3619 | CORE_ADDR cmask, dmask; | |
3620 | int dmask_regnum | |
3621 | = AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base); | |
3622 | int cmask_regnum | |
3623 | = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base); | |
3624 | ||
3625 | /* If we have a kernel address and we have kernel-mode address | |
3626 | mask registers, use those instead. */ | |
3627 | if (tdep->pauth_reg_count > 2 | |
3628 | && pointer & VA_RANGE_SELECT_BIT_MASK) | |
3629 | { | |
3630 | dmask_regnum | |
3631 | = AARCH64_PAUTH_DMASK_HIGH_REGNUM (tdep->pauth_reg_base); | |
3632 | cmask_regnum | |
3633 | = AARCH64_PAUTH_CMASK_HIGH_REGNUM (tdep->pauth_reg_base); | |
3634 | } | |
3635 | ||
3636 | /* We have both a code mask and a data mask. For now they are | |
3637 | the same, but this may change in the future. */ | |
3638 | if (regs->cooked_read (dmask_regnum, &dmask) != REG_VALID) | |
3639 | dmask = mask; | |
3640 | ||
3641 | if (regs->cooked_read (cmask_regnum, &cmask) != REG_VALID) | |
3642 | cmask = mask; | |
3643 | ||
3644 | mask |= aarch64_mask_from_pac_registers (cmask, dmask); | |
3645 | } | |
3646 | } | |
6d002087 LM |
3647 | } |
3648 | ||
3649 | return aarch64_remove_top_bits (pointer, mask); | |
3650 | } | |
3651 | ||
07b287a0 MS |
3652 | /* Initialize the current architecture based on INFO. If possible, |
3653 | re-use an architecture from ARCHES, which is a list of | |
3654 | architectures already created during this debugging session. | |
3655 | ||
3656 | Called e.g. at program startup, when reading a core file, and when | |
3657 | reading a binary file. */ | |
3658 | ||
3659 | static struct gdbarch * | |
3660 | aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3661 | { | |
ccb8d7e8 | 3662 | const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve; |
76bed0fd | 3663 | const struct tdesc_feature *feature_pauth; |
ccb8d7e8 AH |
3664 | bool valid_p = true; |
3665 | int i, num_regs = 0, num_pseudo_regs = 0; | |
c9cd8ca4 | 3666 | int first_pauth_regnum = -1, ra_sign_state_offset = -1; |
ba60b963 | 3667 | int first_mte_regnum = -1, first_tls_regnum = -1; |
4f3681cc | 3668 | uint64_t vq = aarch64_get_tdesc_vq (info.target_desc); |
4da037ef AH |
3669 | |
3670 | if (vq > AARCH64_MAX_SVE_VQ) | |
f34652de | 3671 | internal_error (_("VQ out of bounds: %s (max %d)"), |
596179f7 | 3672 | pulongest (vq), AARCH64_MAX_SVE_VQ); |
4da037ef | 3673 | |
ccb8d7e8 AH |
3674 | /* If there is already a candidate, use it. */ |
3675 | for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
3676 | best_arch != nullptr; | |
3677 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
3678 | { | |
345bd07c | 3679 | aarch64_gdbarch_tdep *tdep |
08106042 | 3680 | = gdbarch_tdep<aarch64_gdbarch_tdep> (best_arch->gdbarch); |
4da037ef | 3681 | if (tdep && tdep->vq == vq) |
ccb8d7e8 AH |
3682 | return best_arch->gdbarch; |
3683 | } | |
07b287a0 | 3684 | |
4da037ef AH |
3685 | /* Ensure we always have a target descriptor, and that it is for the given VQ |
3686 | value. */ | |
ccb8d7e8 | 3687 | const struct target_desc *tdesc = info.target_desc; |
4f3681cc TJB |
3688 | if (!tdesc_has_registers (tdesc)) |
3689 | tdesc = aarch64_read_description ({}); | |
07b287a0 MS |
3690 | gdb_assert (tdesc); |
3691 | ||
ccb8d7e8 | 3692 | feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core"); |
ba2d2bb2 AH |
3693 | feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); |
3694 | feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); | |
5e984dbf LM |
3695 | const struct tdesc_feature *feature_mte |
3696 | = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.mte"); | |
414d5848 JB |
3697 | const struct tdesc_feature *feature_tls |
3698 | = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.tls"); | |
07b287a0 | 3699 | |
ccb8d7e8 AH |
3700 | if (feature_core == nullptr) |
3701 | return nullptr; | |
07b287a0 | 3702 | |
c1e1314d | 3703 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
07b287a0 | 3704 | |
ba2d2bb2 | 3705 | /* Validate the description provides the mandatory core R registers |
07b287a0 MS |
3706 | and allocate their numbers. */ |
3707 | for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++) | |
c1e1314d | 3708 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data.get (), |
ba2d2bb2 AH |
3709 | AARCH64_X0_REGNUM + i, |
3710 | aarch64_r_register_names[i]); | |
07b287a0 MS |
3711 | |
3712 | num_regs = AARCH64_X0_REGNUM + i; | |
3713 | ||
ba2d2bb2 | 3714 | /* Add the V registers. */ |
ccb8d7e8 | 3715 | if (feature_fpu != nullptr) |
07b287a0 | 3716 | { |
ccb8d7e8 | 3717 | if (feature_sve != nullptr) |
ba2d2bb2 AH |
3718 | error (_("Program contains both fpu and SVE features.")); |
3719 | ||
3720 | /* Validate the description provides the mandatory V registers | |
3721 | and allocate their numbers. */ | |
07b287a0 | 3722 | for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++) |
c1e1314d | 3723 | valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data.get (), |
ba2d2bb2 AH |
3724 | AARCH64_V0_REGNUM + i, |
3725 | aarch64_v_register_names[i]); | |
07b287a0 MS |
3726 | |
3727 | num_regs = AARCH64_V0_REGNUM + i; | |
ba2d2bb2 | 3728 | } |
07b287a0 | 3729 | |
ba2d2bb2 | 3730 | /* Add the SVE registers. */ |
ccb8d7e8 | 3731 | if (feature_sve != nullptr) |
ba2d2bb2 AH |
3732 | { |
3733 | /* Validate the description provides the mandatory SVE registers | |
3734 | and allocate their numbers. */ | |
3735 | for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++) | |
c1e1314d | 3736 | valid_p &= tdesc_numbered_register (feature_sve, tdesc_data.get (), |
ba2d2bb2 AH |
3737 | AARCH64_SVE_Z0_REGNUM + i, |
3738 | aarch64_sve_register_names[i]); | |
3739 | ||
3740 | num_regs = AARCH64_SVE_Z0_REGNUM + i; | |
3741 | num_pseudo_regs += 32; /* add the Vn register pseudos. */ | |
3742 | } | |
3743 | ||
ccb8d7e8 | 3744 | if (feature_fpu != nullptr || feature_sve != nullptr) |
ba2d2bb2 | 3745 | { |
07b287a0 MS |
3746 | num_pseudo_regs += 32; /* add the Qn scalar register pseudos */ |
3747 | num_pseudo_regs += 32; /* add the Dn scalar register pseudos */ | |
3748 | num_pseudo_regs += 32; /* add the Sn scalar register pseudos */ | |
3749 | num_pseudo_regs += 32; /* add the Hn scalar register pseudos */ | |
3750 | num_pseudo_regs += 32; /* add the Bn scalar register pseudos */ | |
3751 | } | |
3752 | ||
414d5848 | 3753 | /* Add the TLS register. */ |
ba60b963 | 3754 | int tls_register_count = 0; |
414d5848 JB |
3755 | if (feature_tls != nullptr) |
3756 | { | |
ba60b963 | 3757 | first_tls_regnum = num_regs; |
414d5848 | 3758 | |
ba60b963 LM |
3759 | /* Look for the TLS registers. tpidr is required, but tpidr2 is |
3760 | optional. */ | |
3761 | valid_p | |
3762 | = tdesc_numbered_register (feature_tls, tdesc_data.get (), | |
3763 | first_tls_regnum, "tpidr"); | |
3764 | ||
3765 | if (valid_p) | |
3766 | { | |
3767 | tls_register_count++; | |
3768 | ||
3769 | bool has_tpidr2 | |
3770 | = tdesc_numbered_register (feature_tls, tdesc_data.get (), | |
3771 | first_tls_regnum + tls_register_count, | |
3772 | "tpidr2"); | |
3773 | ||
3774 | /* Figure out how many TLS registers we have. */ | |
3775 | if (has_tpidr2) | |
3776 | tls_register_count++; | |
3777 | ||
3778 | num_regs += tls_register_count; | |
3779 | } | |
3780 | else | |
3781 | { | |
3782 | warning (_("Provided TLS register feature doesn't contain " | |
3783 | "required tpidr register.")); | |
3784 | return nullptr; | |
3785 | } | |
414d5848 JB |
3786 | } |
3787 | ||
acdf6071 LM |
3788 | /* We have two versions of the pauth target description due to a past bug |
3789 | where GDB would crash when seeing the first version of the pauth target | |
3790 | description. */ | |
3791 | feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth"); | |
3792 | if (feature_pauth == nullptr) | |
3793 | feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth_v2"); | |
3794 | ||
76bed0fd | 3795 | /* Add the pauth registers. */ |
6d002087 | 3796 | int pauth_masks = 0; |
76bed0fd AH |
3797 | if (feature_pauth != NULL) |
3798 | { | |
3799 | first_pauth_regnum = num_regs; | |
c9cd8ca4 | 3800 | ra_sign_state_offset = num_pseudo_regs; |
6d002087 LM |
3801 | |
3802 | /* Size of the expected register set with all 4 masks. */ | |
3803 | int set_size = ARRAY_SIZE (aarch64_pauth_register_names); | |
3804 | ||
3805 | /* QEMU exposes a couple additional masks for the high half of the | |
3806 | address. We should either have 2 registers or 4 registers. */ | |
3807 | if (tdesc_unnumbered_register (feature_pauth, | |
3808 | "pauth_dmask_high") == 0) | |
3809 | { | |
3810 | /* We did not find pauth_dmask_high, assume we only have | |
3811 | 2 masks. We are not dealing with QEMU/Emulators then. */ | |
3812 | set_size -= 2; | |
3813 | } | |
3814 | ||
76bed0fd AH |
3815 | /* Validate the descriptor provides the mandatory PAUTH registers and |
3816 | allocate their numbers. */ | |
6d002087 | 3817 | for (i = 0; i < set_size; i++) |
c1e1314d | 3818 | valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data.get (), |
76bed0fd AH |
3819 | first_pauth_regnum + i, |
3820 | aarch64_pauth_register_names[i]); | |
3821 | ||
3822 | num_regs += i; | |
34dcc7cf | 3823 | num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */ |
6d002087 | 3824 | pauth_masks = set_size; |
76bed0fd AH |
3825 | } |
3826 | ||
5e984dbf LM |
3827 | /* Add the MTE registers. */ |
3828 | if (feature_mte != NULL) | |
3829 | { | |
3830 | first_mte_regnum = num_regs; | |
3831 | /* Validate the descriptor provides the mandatory MTE registers and | |
3832 | allocate their numbers. */ | |
3833 | for (i = 0; i < ARRAY_SIZE (aarch64_mte_register_names); i++) | |
3834 | valid_p &= tdesc_numbered_register (feature_mte, tdesc_data.get (), | |
3835 | first_mte_regnum + i, | |
3836 | aarch64_mte_register_names[i]); | |
3837 | ||
3838 | num_regs += i; | |
3839 | } | |
e63ae49b LM |
3840 | /* W pseudo-registers */ |
3841 | int first_w_regnum = num_pseudo_regs; | |
3842 | num_pseudo_regs += 31; | |
5e984dbf | 3843 | |
07b287a0 | 3844 | if (!valid_p) |
c1e1314d | 3845 | return nullptr; |
07b287a0 MS |
3846 | |
3847 | /* AArch64 code is always little-endian. */ | |
3848 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
3849 | ||
2b16913c SM |
3850 | gdbarch *gdbarch |
3851 | = gdbarch_alloc (&info, gdbarch_tdep_up (new aarch64_gdbarch_tdep)); | |
3852 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); | |
07b287a0 MS |
3853 | |
3854 | /* This should be low enough for everything. */ | |
3855 | tdep->lowest_pc = 0x20; | |
3856 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ | |
3857 | tdep->jb_elt_size = 8; | |
4da037ef | 3858 | tdep->vq = vq; |
76bed0fd | 3859 | tdep->pauth_reg_base = first_pauth_regnum; |
6d002087 | 3860 | tdep->pauth_reg_count = pauth_masks; |
1ba3a322 | 3861 | tdep->ra_sign_state_regnum = -1; |
5e984dbf | 3862 | tdep->mte_reg_base = first_mte_regnum; |
ba60b963 LM |
3863 | tdep->tls_regnum_base = first_tls_regnum; |
3864 | tdep->tls_register_count = tls_register_count; | |
34dcc7cf | 3865 | |
07b287a0 MS |
3866 | set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); |
3867 | set_gdbarch_frame_align (gdbarch, aarch64_frame_align); | |
3868 | ||
07b287a0 MS |
3869 | /* Advance PC across function entry code. */ |
3870 | set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue); | |
3871 | ||
3872 | /* The stack grows downward. */ | |
3873 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3874 | ||
3875 | /* Breakpoint manipulation. */ | |
04180708 YQ |
3876 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
3877 | aarch64_breakpoint::kind_from_pc); | |
3878 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
3879 | aarch64_breakpoint::bp_from_kind); | |
07b287a0 | 3880 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
9404b58f | 3881 | set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step); |
07b287a0 MS |
3882 | |
3883 | /* Information about registers, etc. */ | |
3884 | set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM); | |
3885 | set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM); | |
3886 | set_gdbarch_num_regs (gdbarch, num_regs); | |
3887 | ||
3888 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs); | |
3889 | set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value); | |
3890 | set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write); | |
3891 | set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name); | |
3892 | set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type); | |
3893 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
3894 | aarch64_pseudo_register_reggroup_p); | |
76bed0fd | 3895 | set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register); |
07b287a0 MS |
3896 | |
3897 | /* ABI */ | |
3898 | set_gdbarch_short_bit (gdbarch, 16); | |
3899 | set_gdbarch_int_bit (gdbarch, 32); | |
3900 | set_gdbarch_float_bit (gdbarch, 32); | |
3901 | set_gdbarch_double_bit (gdbarch, 64); | |
3902 | set_gdbarch_long_double_bit (gdbarch, 128); | |
3903 | set_gdbarch_long_bit (gdbarch, 64); | |
3904 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3905 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3906 | set_gdbarch_char_signed (gdbarch, 0); | |
53375380 | 3907 | set_gdbarch_wchar_signed (gdbarch, 0); |
07b287a0 MS |
3908 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
3909 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
552f1157 | 3910 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad); |
b907456c | 3911 | set_gdbarch_type_align (gdbarch, aarch64_type_align); |
07b287a0 | 3912 | |
da729c5c TT |
3913 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
3914 | set_gdbarch_stack_frame_destroyed_p (gdbarch, aarch64_stack_frame_destroyed_p); | |
3915 | ||
07b287a0 MS |
3916 | /* Internal <-> external register number maps. */ |
3917 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum); | |
3918 | ||
3919 | /* Returning results. */ | |
5cb0f2d5 | 3920 | set_gdbarch_return_value_as_value (gdbarch, aarch64_return_value); |
07b287a0 MS |
3921 | |
3922 | /* Disassembly. */ | |
3923 | set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn); | |
3924 | ||
3925 | /* Virtual tables. */ | |
3926 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
3927 | ||
3928 | /* Hook in the ABI-specific overrides, if they have been registered. */ | |
3929 | info.target_desc = tdesc; | |
c1e1314d | 3930 | info.tdesc_data = tdesc_data.get (); |
07b287a0 MS |
3931 | gdbarch_init_osabi (info, gdbarch); |
3932 | ||
3933 | dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg); | |
11e1b75f AH |
3934 | /* Register DWARF CFA vendor handler. */ |
3935 | set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, | |
3936 | aarch64_execute_dwarf_cfa_vendor_op); | |
07b287a0 | 3937 | |
5133a315 LM |
3938 | /* Permanent/Program breakpoint handling. */ |
3939 | set_gdbarch_program_breakpoint_here_p (gdbarch, | |
3940 | aarch64_program_breakpoint_here_p); | |
3941 | ||
07b287a0 MS |
3942 | /* Add some default predicates. */ |
3943 | frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind); | |
3944 | dwarf2_append_unwinders (gdbarch); | |
3945 | frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind); | |
3946 | ||
3947 | frame_base_set_default (gdbarch, &aarch64_normal_base); | |
3948 | ||
3949 | /* Now we have tuned the configuration, set a few final things, | |
3950 | based on what the OS ABI has told us. */ | |
3951 | ||
3952 | if (tdep->jb_pc >= 0) | |
3953 | set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target); | |
3954 | ||
ea873d8e PL |
3955 | set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address); |
3956 | ||
aa7ca1bb AH |
3957 | set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags); |
3958 | ||
c1e1314d | 3959 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
07b287a0 | 3960 | |
1ba3a322 LM |
3961 | /* Fetch the updated number of registers after we're done adding all |
3962 | entries from features we don't explicitly care about. This is the case | |
3963 | for bare metal debugging stubs that include a lot of system registers. */ | |
3964 | num_regs = gdbarch_num_regs (gdbarch); | |
3965 | ||
3966 | /* With the number of real registers updated, setup the pseudo-registers and | |
3967 | record their numbers. */ | |
3968 | ||
e63ae49b LM |
3969 | /* Setup W pseudo-register numbers. */ |
3970 | tdep->w_pseudo_base = first_w_regnum + num_regs; | |
3971 | tdep->w_pseudo_count = 31; | |
3972 | ||
1ba3a322 LM |
3973 | /* Pointer authentication pseudo-registers. */ |
3974 | if (tdep->has_pauth ()) | |
3975 | tdep->ra_sign_state_regnum = ra_sign_state_offset + num_regs; | |
3976 | ||
6d002087 LM |
3977 | /* Architecture hook to remove bits of a pointer that are not part of the |
3978 | address, like memory tags (MTE) and pointer authentication signatures. */ | |
3979 | set_gdbarch_remove_non_address_bits (gdbarch, | |
3980 | aarch64_remove_non_address_bits); | |
3981 | ||
07b287a0 MS |
3982 | /* Add standard register aliases. */ |
3983 | for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++) | |
3984 | user_reg_add (gdbarch, aarch64_register_aliases[i].name, | |
3985 | value_of_aarch64_user_reg, | |
3986 | &aarch64_register_aliases[i].regnum); | |
3987 | ||
e8bf1ce4 JB |
3988 | register_aarch64_ravenscar_ops (gdbarch); |
3989 | ||
07b287a0 MS |
3990 | return gdbarch; |
3991 | } | |
3992 | ||
3993 | static void | |
3994 | aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3995 | { | |
08106042 | 3996 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
3997 | |
3998 | if (tdep == NULL) | |
3999 | return; | |
4000 | ||
09a5d200 | 4001 | gdb_printf (file, _("aarch64_dump_tdep: Lowest pc = 0x%s\n"), |
6cb06a8c | 4002 | paddress (gdbarch, tdep->lowest_pc)); |
07b287a0 MS |
4003 | } |
4004 | ||
0d4c07af | 4005 | #if GDB_SELF_TEST |
1e2b521d YQ |
4006 | namespace selftests |
4007 | { | |
4008 | static void aarch64_process_record_test (void); | |
4009 | } | |
0d4c07af | 4010 | #endif |
1e2b521d | 4011 | |
6c265988 | 4012 | void _initialize_aarch64_tdep (); |
07b287a0 | 4013 | void |
6c265988 | 4014 | _initialize_aarch64_tdep () |
07b287a0 MS |
4015 | { |
4016 | gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init, | |
4017 | aarch64_dump_tdep); | |
4018 | ||
07b287a0 MS |
4019 | /* Debug this file's internals. */ |
4020 | add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\ | |
4021 | Set AArch64 debugging."), _("\ | |
4022 | Show AArch64 debugging."), _("\ | |
4023 | When on, AArch64 specific debugging is enabled."), | |
4024 | NULL, | |
4025 | show_aarch64_debug, | |
4026 | &setdebuglist, &showdebuglist); | |
4d9a9006 YQ |
4027 | |
4028 | #if GDB_SELF_TEST | |
1526853e SM |
4029 | selftests::register_test ("aarch64-analyze-prologue", |
4030 | selftests::aarch64_analyze_prologue_test); | |
4031 | selftests::register_test ("aarch64-process-record", | |
4032 | selftests::aarch64_process_record_test); | |
4d9a9006 | 4033 | #endif |
07b287a0 | 4034 | } |
99afc88b OJ |
4035 | |
4036 | /* AArch64 process record-replay related structures, defines etc. */ | |
4037 | ||
99afc88b | 4038 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ |
dda83cd7 SM |
4039 | do \ |
4040 | { \ | |
4041 | unsigned int reg_len = LENGTH; \ | |
4042 | if (reg_len) \ | |
4043 | { \ | |
4044 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
4045 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
4046 | } \ | |
4047 | } \ | |
4048 | while (0) | |
99afc88b OJ |
4049 | |
4050 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
4051 | do \ |
4052 | { \ | |
4053 | unsigned int mem_len = LENGTH; \ | |
4054 | if (mem_len) \ | |
01add95b SM |
4055 | { \ |
4056 | MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \ | |
91ddba83 | 4057 | memcpy(MEMS, &RECORD_BUF[0], \ |
01add95b SM |
4058 | sizeof(struct aarch64_mem_r) * LENGTH); \ |
4059 | } \ | |
dda83cd7 SM |
4060 | } \ |
4061 | while (0) | |
99afc88b OJ |
4062 | |
4063 | /* AArch64 record/replay structures and enumerations. */ | |
4064 | ||
4065 | struct aarch64_mem_r | |
4066 | { | |
4067 | uint64_t len; /* Record length. */ | |
4068 | uint64_t addr; /* Memory address. */ | |
4069 | }; | |
4070 | ||
4071 | enum aarch64_record_result | |
4072 | { | |
4073 | AARCH64_RECORD_SUCCESS, | |
99afc88b OJ |
4074 | AARCH64_RECORD_UNSUPPORTED, |
4075 | AARCH64_RECORD_UNKNOWN | |
4076 | }; | |
4077 | ||
4748a9be | 4078 | struct aarch64_insn_decode_record |
99afc88b OJ |
4079 | { |
4080 | struct gdbarch *gdbarch; | |
4081 | struct regcache *regcache; | |
4082 | CORE_ADDR this_addr; /* Address of insn to be recorded. */ | |
4083 | uint32_t aarch64_insn; /* Insn to be recorded. */ | |
4084 | uint32_t mem_rec_count; /* Count of memory records. */ | |
4085 | uint32_t reg_rec_count; /* Count of register records. */ | |
4086 | uint32_t *aarch64_regs; /* Registers to be recorded. */ | |
4087 | struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */ | |
4748a9be | 4088 | }; |
99afc88b OJ |
4089 | |
4090 | /* Record handler for data processing - register instructions. */ | |
4091 | ||
4092 | static unsigned int | |
4748a9be | 4093 | aarch64_record_data_proc_reg (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4094 | { |
4095 | uint8_t reg_rd, insn_bits24_27, insn_bits21_23; | |
4096 | uint32_t record_buf[4]; | |
4097 | ||
4098 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4099 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
4100 | insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23); | |
4101 | ||
4102 | if (!bit (aarch64_insn_r->aarch64_insn, 28)) | |
4103 | { | |
4104 | uint8_t setflags; | |
4105 | ||
4106 | /* Logical (shifted register). */ | |
4107 | if (insn_bits24_27 == 0x0a) | |
4108 | setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03); | |
4109 | /* Add/subtract. */ | |
4110 | else if (insn_bits24_27 == 0x0b) | |
4111 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
4112 | else | |
4113 | return AARCH64_RECORD_UNKNOWN; | |
4114 | ||
4115 | record_buf[0] = reg_rd; | |
4116 | aarch64_insn_r->reg_rec_count = 1; | |
4117 | if (setflags) | |
4118 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
4119 | } | |
4120 | else | |
4121 | { | |
4122 | if (insn_bits24_27 == 0x0b) | |
4123 | { | |
4124 | /* Data-processing (3 source). */ | |
4125 | record_buf[0] = reg_rd; | |
4126 | aarch64_insn_r->reg_rec_count = 1; | |
4127 | } | |
4128 | else if (insn_bits24_27 == 0x0a) | |
4129 | { | |
4130 | if (insn_bits21_23 == 0x00) | |
4131 | { | |
4132 | /* Add/subtract (with carry). */ | |
4133 | record_buf[0] = reg_rd; | |
4134 | aarch64_insn_r->reg_rec_count = 1; | |
4135 | if (bit (aarch64_insn_r->aarch64_insn, 29)) | |
4136 | { | |
4137 | record_buf[1] = AARCH64_CPSR_REGNUM; | |
4138 | aarch64_insn_r->reg_rec_count = 2; | |
4139 | } | |
4140 | } | |
4141 | else if (insn_bits21_23 == 0x02) | |
4142 | { | |
4143 | /* Conditional compare (register) and conditional compare | |
4144 | (immediate) instructions. */ | |
4145 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
4146 | aarch64_insn_r->reg_rec_count = 1; | |
4147 | } | |
4148 | else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06) | |
4149 | { | |
85102364 | 4150 | /* Conditional select. */ |
99afc88b OJ |
4151 | /* Data-processing (2 source). */ |
4152 | /* Data-processing (1 source). */ | |
4153 | record_buf[0] = reg_rd; | |
4154 | aarch64_insn_r->reg_rec_count = 1; | |
4155 | } | |
4156 | else | |
4157 | return AARCH64_RECORD_UNKNOWN; | |
4158 | } | |
4159 | } | |
4160 | ||
4161 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
4162 | record_buf); | |
4163 | return AARCH64_RECORD_SUCCESS; | |
4164 | } | |
4165 | ||
4166 | /* Record handler for data processing - immediate instructions. */ | |
4167 | ||
4168 | static unsigned int | |
4748a9be | 4169 | aarch64_record_data_proc_imm (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b | 4170 | { |
78cc6c2d | 4171 | uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags; |
99afc88b OJ |
4172 | uint32_t record_buf[4]; |
4173 | ||
4174 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
99afc88b OJ |
4175 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); |
4176 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
4177 | ||
4178 | if (insn_bits24_27 == 0x00 /* PC rel addressing. */ | |
4179 | || insn_bits24_27 == 0x03 /* Bitfield and Extract. */ | |
4180 | || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */ | |
4181 | { | |
4182 | record_buf[0] = reg_rd; | |
4183 | aarch64_insn_r->reg_rec_count = 1; | |
4184 | } | |
4185 | else if (insn_bits24_27 == 0x01) | |
4186 | { | |
4187 | /* Add/Subtract (immediate). */ | |
4188 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
4189 | record_buf[0] = reg_rd; | |
4190 | aarch64_insn_r->reg_rec_count = 1; | |
4191 | if (setflags) | |
4192 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
4193 | } | |
4194 | else if (insn_bits24_27 == 0x02 && !insn_bit23) | |
4195 | { | |
4196 | /* Logical (immediate). */ | |
4197 | setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03; | |
4198 | record_buf[0] = reg_rd; | |
4199 | aarch64_insn_r->reg_rec_count = 1; | |
4200 | if (setflags) | |
4201 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
4202 | } | |
4203 | else | |
4204 | return AARCH64_RECORD_UNKNOWN; | |
4205 | ||
4206 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
4207 | record_buf); | |
4208 | return AARCH64_RECORD_SUCCESS; | |
4209 | } | |
4210 | ||
4211 | /* Record handler for branch, exception generation and system instructions. */ | |
4212 | ||
4213 | static unsigned int | |
4748a9be | 4214 | aarch64_record_branch_except_sys (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b | 4215 | { |
345bd07c SM |
4216 | |
4217 | aarch64_gdbarch_tdep *tdep | |
08106042 | 4218 | = gdbarch_tdep<aarch64_gdbarch_tdep> (aarch64_insn_r->gdbarch); |
99afc88b OJ |
4219 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23; |
4220 | uint32_t record_buf[4]; | |
4221 | ||
4222 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
4223 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
4224 | insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
4225 | ||
4226 | if (insn_bits28_31 == 0x0d) | |
4227 | { | |
4228 | /* Exception generation instructions. */ | |
4229 | if (insn_bits24_27 == 0x04) | |
4230 | { | |
5d98d3cd YQ |
4231 | if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) |
4232 | && !bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
4233 | && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01) | |
99afc88b OJ |
4234 | { |
4235 | ULONGEST svc_number; | |
4236 | ||
4237 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8, | |
4238 | &svc_number); | |
4239 | return tdep->aarch64_syscall_record (aarch64_insn_r->regcache, | |
4240 | svc_number); | |
4241 | } | |
4242 | else | |
4243 | return AARCH64_RECORD_UNSUPPORTED; | |
4244 | } | |
4245 | /* System instructions. */ | |
4246 | else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00) | |
4247 | { | |
4248 | uint32_t reg_rt, reg_crn; | |
4249 | ||
4250 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4251 | reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
4252 | ||
4253 | /* Record rt in case of sysl and mrs instructions. */ | |
4254 | if (bit (aarch64_insn_r->aarch64_insn, 21)) | |
4255 | { | |
4256 | record_buf[0] = reg_rt; | |
4257 | aarch64_insn_r->reg_rec_count = 1; | |
4258 | } | |
4259 | /* Record cpsr for hint and msr(immediate) instructions. */ | |
4260 | else if (reg_crn == 0x02 || reg_crn == 0x04) | |
4261 | { | |
4262 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
4263 | aarch64_insn_r->reg_rec_count = 1; | |
4264 | } | |
4265 | } | |
4266 | /* Unconditional branch (register). */ | |
4267 | else if((insn_bits24_27 & 0x0e) == 0x06) | |
4268 | { | |
4269 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
4270 | if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01) | |
4271 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
4272 | } | |
4273 | else | |
4274 | return AARCH64_RECORD_UNKNOWN; | |
4275 | } | |
4276 | /* Unconditional branch (immediate). */ | |
4277 | else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04) | |
4278 | { | |
4279 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
4280 | if (bit (aarch64_insn_r->aarch64_insn, 31)) | |
4281 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
4282 | } | |
4283 | else | |
4284 | /* Compare & branch (immediate), Test & branch (immediate) and | |
4285 | Conditional branch (immediate). */ | |
4286 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
4287 | ||
4288 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
4289 | record_buf); | |
4290 | return AARCH64_RECORD_SUCCESS; | |
4291 | } | |
4292 | ||
4293 | /* Record handler for advanced SIMD load and store instructions. */ | |
4294 | ||
4295 | static unsigned int | |
4748a9be | 4296 | aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4297 | { |
4298 | CORE_ADDR address; | |
4299 | uint64_t addr_offset = 0; | |
4300 | uint32_t record_buf[24]; | |
4301 | uint64_t record_buf_mem[24]; | |
4302 | uint32_t reg_rn, reg_rt; | |
4303 | uint32_t reg_index = 0, mem_index = 0; | |
4304 | uint8_t opcode_bits, size_bits; | |
4305 | ||
4306 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4307 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
4308 | size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
4309 | opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
4310 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address); | |
4311 | ||
4312 | if (record_debug) | |
b277c936 | 4313 | debug_printf ("Process record: Advanced SIMD load/store\n"); |
99afc88b OJ |
4314 | |
4315 | /* Load/store single structure. */ | |
4316 | if (bit (aarch64_insn_r->aarch64_insn, 24)) | |
4317 | { | |
4318 | uint8_t sindex, scale, selem, esize, replicate = 0; | |
4319 | scale = opcode_bits >> 2; | |
4320 | selem = ((opcode_bits & 0x02) | | |
dda83cd7 | 4321 | bit (aarch64_insn_r->aarch64_insn, 21)) + 1; |
99afc88b | 4322 | switch (scale) |
dda83cd7 SM |
4323 | { |
4324 | case 1: | |
4325 | if (size_bits & 0x01) | |
4326 | return AARCH64_RECORD_UNKNOWN; | |
4327 | break; | |
4328 | case 2: | |
4329 | if ((size_bits >> 1) & 0x01) | |
4330 | return AARCH64_RECORD_UNKNOWN; | |
4331 | if (size_bits & 0x01) | |
4332 | { | |
4333 | if (!((opcode_bits >> 1) & 0x01)) | |
4334 | scale = 3; | |
4335 | else | |
4336 | return AARCH64_RECORD_UNKNOWN; | |
4337 | } | |
4338 | break; | |
4339 | case 3: | |
4340 | if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01)) | |
4341 | { | |
4342 | scale = size_bits; | |
4343 | replicate = 1; | |
4344 | break; | |
4345 | } | |
4346 | else | |
4347 | return AARCH64_RECORD_UNKNOWN; | |
4348 | default: | |
4349 | break; | |
4350 | } | |
99afc88b OJ |
4351 | esize = 8 << scale; |
4352 | if (replicate) | |
dda83cd7 SM |
4353 | for (sindex = 0; sindex < selem; sindex++) |
4354 | { | |
4355 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
4356 | reg_rt = (reg_rt + 1) % 32; | |
4357 | } | |
99afc88b | 4358 | else |
dda83cd7 SM |
4359 | { |
4360 | for (sindex = 0; sindex < selem; sindex++) | |
a2e3e93f SM |
4361 | { |
4362 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
4363 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
4364 | else | |
4365 | { | |
4366 | record_buf_mem[mem_index++] = esize / 8; | |
4367 | record_buf_mem[mem_index++] = address + addr_offset; | |
4368 | } | |
4369 | addr_offset = addr_offset + (esize / 8); | |
4370 | reg_rt = (reg_rt + 1) % 32; | |
4371 | } | |
dda83cd7 | 4372 | } |
99afc88b OJ |
4373 | } |
4374 | /* Load/store multiple structure. */ | |
4375 | else | |
4376 | { | |
4377 | uint8_t selem, esize, rpt, elements; | |
4378 | uint8_t eindex, rindex; | |
4379 | ||
4380 | esize = 8 << size_bits; | |
4381 | if (bit (aarch64_insn_r->aarch64_insn, 30)) | |
dda83cd7 | 4382 | elements = 128 / esize; |
99afc88b | 4383 | else |
dda83cd7 | 4384 | elements = 64 / esize; |
99afc88b OJ |
4385 | |
4386 | switch (opcode_bits) | |
dda83cd7 SM |
4387 | { |
4388 | /*LD/ST4 (4 Registers). */ | |
4389 | case 0: | |
4390 | rpt = 1; | |
4391 | selem = 4; | |
4392 | break; | |
4393 | /*LD/ST1 (4 Registers). */ | |
4394 | case 2: | |
4395 | rpt = 4; | |
4396 | selem = 1; | |
4397 | break; | |
4398 | /*LD/ST3 (3 Registers). */ | |
4399 | case 4: | |
4400 | rpt = 1; | |
4401 | selem = 3; | |
4402 | break; | |
4403 | /*LD/ST1 (3 Registers). */ | |
4404 | case 6: | |
4405 | rpt = 3; | |
4406 | selem = 1; | |
4407 | break; | |
4408 | /*LD/ST1 (1 Register). */ | |
4409 | case 7: | |
4410 | rpt = 1; | |
4411 | selem = 1; | |
4412 | break; | |
4413 | /*LD/ST2 (2 Registers). */ | |
4414 | case 8: | |
4415 | rpt = 1; | |
4416 | selem = 2; | |
4417 | break; | |
4418 | /*LD/ST1 (2 Registers). */ | |
4419 | case 10: | |
4420 | rpt = 2; | |
4421 | selem = 1; | |
4422 | break; | |
4423 | default: | |
4424 | return AARCH64_RECORD_UNSUPPORTED; | |
4425 | break; | |
4426 | } | |
99afc88b | 4427 | for (rindex = 0; rindex < rpt; rindex++) |
dda83cd7 SM |
4428 | for (eindex = 0; eindex < elements; eindex++) |
4429 | { | |
4430 | uint8_t reg_tt, sindex; | |
4431 | reg_tt = (reg_rt + rindex) % 32; | |
4432 | for (sindex = 0; sindex < selem; sindex++) | |
4433 | { | |
4434 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
4435 | record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM; | |
4436 | else | |
4437 | { | |
4438 | record_buf_mem[mem_index++] = esize / 8; | |
4439 | record_buf_mem[mem_index++] = address + addr_offset; | |
4440 | } | |
4441 | addr_offset = addr_offset + (esize / 8); | |
4442 | reg_tt = (reg_tt + 1) % 32; | |
4443 | } | |
4444 | } | |
99afc88b OJ |
4445 | } |
4446 | ||
4447 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
4448 | record_buf[reg_index++] = reg_rn; | |
4449 | ||
4450 | aarch64_insn_r->reg_rec_count = reg_index; | |
4451 | aarch64_insn_r->mem_rec_count = mem_index / 2; | |
4452 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
dda83cd7 | 4453 | record_buf_mem); |
99afc88b | 4454 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, |
dda83cd7 | 4455 | record_buf); |
99afc88b OJ |
4456 | return AARCH64_RECORD_SUCCESS; |
4457 | } | |
4458 | ||
4459 | /* Record handler for load and store instructions. */ | |
4460 | ||
4461 | static unsigned int | |
4748a9be | 4462 | aarch64_record_load_store (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4463 | { |
4464 | uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11; | |
4465 | uint8_t insn_bit23, insn_bit21; | |
4466 | uint8_t opc, size_bits, ld_flag, vector_flag; | |
4467 | uint32_t reg_rn, reg_rt, reg_rt2; | |
4468 | uint64_t datasize, offset; | |
4469 | uint32_t record_buf[8]; | |
4470 | uint64_t record_buf_mem[8]; | |
4471 | CORE_ADDR address; | |
4472 | ||
4473 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
4474 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
4475 | insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29); | |
4476 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
4477 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); | |
4478 | ld_flag = bit (aarch64_insn_r->aarch64_insn, 22); | |
4479 | vector_flag = bit (aarch64_insn_r->aarch64_insn, 26); | |
4480 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4481 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
4482 | reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14); | |
4483 | size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31); | |
4484 | ||
4485 | /* Load/store exclusive. */ | |
4486 | if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00) | |
4487 | { | |
4488 | if (record_debug) | |
b277c936 | 4489 | debug_printf ("Process record: load/store exclusive\n"); |
99afc88b OJ |
4490 | |
4491 | if (ld_flag) | |
4492 | { | |
4493 | record_buf[0] = reg_rt; | |
4494 | aarch64_insn_r->reg_rec_count = 1; | |
4495 | if (insn_bit21) | |
4496 | { | |
4497 | record_buf[1] = reg_rt2; | |
4498 | aarch64_insn_r->reg_rec_count = 2; | |
4499 | } | |
4500 | } | |
4501 | else | |
4502 | { | |
4503 | if (insn_bit21) | |
4504 | datasize = (8 << size_bits) * 2; | |
4505 | else | |
4506 | datasize = (8 << size_bits); | |
4507 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4508 | &address); | |
4509 | record_buf_mem[0] = datasize / 8; | |
4510 | record_buf_mem[1] = address; | |
4511 | aarch64_insn_r->mem_rec_count = 1; | |
4512 | if (!insn_bit23) | |
4513 | { | |
4514 | /* Save register rs. */ | |
4515 | record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20); | |
4516 | aarch64_insn_r->reg_rec_count = 1; | |
4517 | } | |
4518 | } | |
4519 | } | |
4520 | /* Load register (literal) instructions decoding. */ | |
4521 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01) | |
4522 | { | |
4523 | if (record_debug) | |
b277c936 | 4524 | debug_printf ("Process record: load register (literal)\n"); |
99afc88b | 4525 | if (vector_flag) |
dda83cd7 | 4526 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; |
99afc88b | 4527 | else |
dda83cd7 | 4528 | record_buf[0] = reg_rt; |
99afc88b OJ |
4529 | aarch64_insn_r->reg_rec_count = 1; |
4530 | } | |
4531 | /* All types of load/store pair instructions decoding. */ | |
4532 | else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02) | |
4533 | { | |
4534 | if (record_debug) | |
b277c936 | 4535 | debug_printf ("Process record: load/store pair\n"); |
99afc88b OJ |
4536 | |
4537 | if (ld_flag) | |
dda83cd7 SM |
4538 | { |
4539 | if (vector_flag) | |
4540 | { | |
4541 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4542 | record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM; | |
4543 | } | |
4544 | else | |
4545 | { | |
4546 | record_buf[0] = reg_rt; | |
4547 | record_buf[1] = reg_rt2; | |
4548 | } | |
4549 | aarch64_insn_r->reg_rec_count = 2; | |
4550 | } | |
99afc88b | 4551 | else |
dda83cd7 SM |
4552 | { |
4553 | uint16_t imm7_off; | |
4554 | imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21); | |
4555 | if (!vector_flag) | |
4556 | size_bits = size_bits >> 1; | |
4557 | datasize = 8 << (2 + size_bits); | |
4558 | offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off; | |
4559 | offset = offset << (2 + size_bits); | |
4560 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4561 | &address); | |
4562 | if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23)) | |
4563 | { | |
4564 | if (imm7_off & 0x40) | |
4565 | address = address - offset; | |
4566 | else | |
4567 | address = address + offset; | |
4568 | } | |
4569 | ||
4570 | record_buf_mem[0] = datasize / 8; | |
4571 | record_buf_mem[1] = address; | |
4572 | record_buf_mem[2] = datasize / 8; | |
4573 | record_buf_mem[3] = address + (datasize / 8); | |
4574 | aarch64_insn_r->mem_rec_count = 2; | |
4575 | } | |
99afc88b | 4576 | if (bit (aarch64_insn_r->aarch64_insn, 23)) |
dda83cd7 | 4577 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; |
99afc88b OJ |
4578 | } |
4579 | /* Load/store register (unsigned immediate) instructions. */ | |
4580 | else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03) | |
4581 | { | |
4582 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
4583 | if (!(opc >> 1)) | |
33877125 YQ |
4584 | { |
4585 | if (opc & 0x01) | |
4586 | ld_flag = 0x01; | |
4587 | else | |
4588 | ld_flag = 0x0; | |
4589 | } | |
99afc88b | 4590 | else |
33877125 | 4591 | { |
1e2b521d YQ |
4592 | if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2) |
4593 | { | |
4594 | /* PRFM (immediate) */ | |
4595 | return AARCH64_RECORD_SUCCESS; | |
4596 | } | |
4597 | else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2) | |
4598 | { | |
4599 | /* LDRSW (immediate) */ | |
4600 | ld_flag = 0x1; | |
4601 | } | |
33877125 | 4602 | else |
1e2b521d YQ |
4603 | { |
4604 | if (opc & 0x01) | |
4605 | ld_flag = 0x01; | |
4606 | else | |
4607 | ld_flag = 0x0; | |
4608 | } | |
33877125 | 4609 | } |
99afc88b OJ |
4610 | |
4611 | if (record_debug) | |
4612 | { | |
b277c936 PL |
4613 | debug_printf ("Process record: load/store (unsigned immediate):" |
4614 | " size %x V %d opc %x\n", size_bits, vector_flag, | |
4615 | opc); | |
99afc88b OJ |
4616 | } |
4617 | ||
4618 | if (!ld_flag) | |
dda83cd7 SM |
4619 | { |
4620 | offset = bits (aarch64_insn_r->aarch64_insn, 10, 21); | |
4621 | datasize = 8 << size_bits; | |
4622 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4623 | &address); | |
4624 | offset = offset << size_bits; | |
4625 | address = address + offset; | |
4626 | ||
4627 | record_buf_mem[0] = datasize >> 3; | |
4628 | record_buf_mem[1] = address; | |
4629 | aarch64_insn_r->mem_rec_count = 1; | |
4630 | } | |
99afc88b | 4631 | else |
dda83cd7 SM |
4632 | { |
4633 | if (vector_flag) | |
4634 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4635 | else | |
4636 | record_buf[0] = reg_rt; | |
4637 | aarch64_insn_r->reg_rec_count = 1; | |
4638 | } | |
99afc88b OJ |
4639 | } |
4640 | /* Load/store register (register offset) instructions. */ | |
5d98d3cd YQ |
4641 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
4642 | && insn_bits10_11 == 0x02 && insn_bit21) | |
99afc88b OJ |
4643 | { |
4644 | if (record_debug) | |
b277c936 | 4645 | debug_printf ("Process record: load/store (register offset)\n"); |
99afc88b OJ |
4646 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); |
4647 | if (!(opc >> 1)) | |
dda83cd7 SM |
4648 | if (opc & 0x01) |
4649 | ld_flag = 0x01; | |
4650 | else | |
4651 | ld_flag = 0x0; | |
99afc88b | 4652 | else |
dda83cd7 SM |
4653 | if (size_bits != 0x03) |
4654 | ld_flag = 0x01; | |
4655 | else | |
4656 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
4657 | |
4658 | if (!ld_flag) | |
dda83cd7 SM |
4659 | { |
4660 | ULONGEST reg_rm_val; | |
4661 | ||
4662 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, | |
4663 | bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val); | |
4664 | if (bit (aarch64_insn_r->aarch64_insn, 12)) | |
4665 | offset = reg_rm_val << size_bits; | |
4666 | else | |
4667 | offset = reg_rm_val; | |
4668 | datasize = 8 << size_bits; | |
4669 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4670 | &address); | |
4671 | address = address + offset; | |
4672 | record_buf_mem[0] = datasize >> 3; | |
4673 | record_buf_mem[1] = address; | |
4674 | aarch64_insn_r->mem_rec_count = 1; | |
4675 | } | |
99afc88b | 4676 | else |
dda83cd7 SM |
4677 | { |
4678 | if (vector_flag) | |
4679 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4680 | else | |
4681 | record_buf[0] = reg_rt; | |
4682 | aarch64_insn_r->reg_rec_count = 1; | |
4683 | } | |
99afc88b OJ |
4684 | } |
4685 | /* Load/store register (immediate and unprivileged) instructions. */ | |
5d98d3cd YQ |
4686 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
4687 | && !insn_bit21) | |
99afc88b OJ |
4688 | { |
4689 | if (record_debug) | |
4690 | { | |
b277c936 PL |
4691 | debug_printf ("Process record: load/store " |
4692 | "(immediate and unprivileged)\n"); | |
99afc88b OJ |
4693 | } |
4694 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
4695 | if (!(opc >> 1)) | |
dda83cd7 SM |
4696 | if (opc & 0x01) |
4697 | ld_flag = 0x01; | |
4698 | else | |
4699 | ld_flag = 0x0; | |
99afc88b | 4700 | else |
dda83cd7 SM |
4701 | if (size_bits != 0x03) |
4702 | ld_flag = 0x01; | |
4703 | else | |
4704 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
4705 | |
4706 | if (!ld_flag) | |
dda83cd7 SM |
4707 | { |
4708 | uint16_t imm9_off; | |
4709 | imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20); | |
4710 | offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off; | |
4711 | datasize = 8 << size_bits; | |
4712 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4713 | &address); | |
4714 | if (insn_bits10_11 != 0x01) | |
4715 | { | |
4716 | if (imm9_off & 0x0100) | |
4717 | address = address - offset; | |
4718 | else | |
4719 | address = address + offset; | |
4720 | } | |
4721 | record_buf_mem[0] = datasize >> 3; | |
4722 | record_buf_mem[1] = address; | |
4723 | aarch64_insn_r->mem_rec_count = 1; | |
4724 | } | |
99afc88b | 4725 | else |
dda83cd7 SM |
4726 | { |
4727 | if (vector_flag) | |
4728 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4729 | else | |
4730 | record_buf[0] = reg_rt; | |
4731 | aarch64_insn_r->reg_rec_count = 1; | |
4732 | } | |
99afc88b | 4733 | if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03) |
dda83cd7 | 4734 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; |
99afc88b OJ |
4735 | } |
4736 | /* Advanced SIMD load/store instructions. */ | |
4737 | else | |
4738 | return aarch64_record_asimd_load_store (aarch64_insn_r); | |
4739 | ||
4740 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
dda83cd7 | 4741 | record_buf_mem); |
99afc88b | 4742 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, |
dda83cd7 | 4743 | record_buf); |
99afc88b OJ |
4744 | return AARCH64_RECORD_SUCCESS; |
4745 | } | |
4746 | ||
4747 | /* Record handler for data processing SIMD and floating point instructions. */ | |
4748 | ||
4749 | static unsigned int | |
4748a9be | 4750 | aarch64_record_data_proc_simd_fp (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4751 | { |
4752 | uint8_t insn_bit21, opcode, rmode, reg_rd; | |
4753 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15; | |
4754 | uint8_t insn_bits11_14; | |
4755 | uint32_t record_buf[2]; | |
4756 | ||
4757 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
4758 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
4759 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
4760 | insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
4761 | insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14); | |
4762 | opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18); | |
4763 | rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20); | |
4764 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4765 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
4766 | ||
4767 | if (record_debug) | |
b277c936 | 4768 | debug_printf ("Process record: data processing SIMD/FP: "); |
99afc88b OJ |
4769 | |
4770 | if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e) | |
4771 | { | |
4772 | /* Floating point - fixed point conversion instructions. */ | |
4773 | if (!insn_bit21) | |
4774 | { | |
4775 | if (record_debug) | |
b277c936 | 4776 | debug_printf ("FP - fixed point conversion"); |
99afc88b OJ |
4777 | |
4778 | if ((opcode >> 1) == 0x0 && rmode == 0x03) | |
4779 | record_buf[0] = reg_rd; | |
4780 | else | |
4781 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4782 | } | |
4783 | /* Floating point - conditional compare instructions. */ | |
4784 | else if (insn_bits10_11 == 0x01) | |
4785 | { | |
4786 | if (record_debug) | |
b277c936 | 4787 | debug_printf ("FP - conditional compare"); |
99afc88b OJ |
4788 | |
4789 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
4790 | } | |
4791 | /* Floating point - data processing (2-source) and | |
dda83cd7 | 4792 | conditional select instructions. */ |
99afc88b OJ |
4793 | else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03) |
4794 | { | |
4795 | if (record_debug) | |
b277c936 | 4796 | debug_printf ("FP - DP (2-source)"); |
99afc88b OJ |
4797 | |
4798 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4799 | } | |
4800 | else if (insn_bits10_11 == 0x00) | |
4801 | { | |
4802 | /* Floating point - immediate instructions. */ | |
4803 | if ((insn_bits12_15 & 0x01) == 0x01 | |
4804 | || (insn_bits12_15 & 0x07) == 0x04) | |
4805 | { | |
4806 | if (record_debug) | |
b277c936 | 4807 | debug_printf ("FP - immediate"); |
99afc88b OJ |
4808 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; |
4809 | } | |
4810 | /* Floating point - compare instructions. */ | |
4811 | else if ((insn_bits12_15 & 0x03) == 0x02) | |
4812 | { | |
4813 | if (record_debug) | |
b277c936 | 4814 | debug_printf ("FP - immediate"); |
99afc88b OJ |
4815 | record_buf[0] = AARCH64_CPSR_REGNUM; |
4816 | } | |
4817 | /* Floating point - integer conversions instructions. */ | |
f62fce35 | 4818 | else if (insn_bits12_15 == 0x00) |
99afc88b OJ |
4819 | { |
4820 | /* Convert float to integer instruction. */ | |
4821 | if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode)) | |
4822 | { | |
4823 | if (record_debug) | |
b277c936 | 4824 | debug_printf ("float to int conversion"); |
99afc88b OJ |
4825 | |
4826 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
4827 | } | |
4828 | /* Convert integer to float instruction. */ | |
4829 | else if ((opcode >> 1) == 0x01 && !rmode) | |
4830 | { | |
4831 | if (record_debug) | |
b277c936 | 4832 | debug_printf ("int to float conversion"); |
99afc88b OJ |
4833 | |
4834 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4835 | } | |
4836 | /* Move float to integer instruction. */ | |
4837 | else if ((opcode >> 1) == 0x03) | |
4838 | { | |
4839 | if (record_debug) | |
b277c936 | 4840 | debug_printf ("move float to int"); |
99afc88b OJ |
4841 | |
4842 | if (!(opcode & 0x01)) | |
4843 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
4844 | else | |
4845 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4846 | } | |
f62fce35 YQ |
4847 | else |
4848 | return AARCH64_RECORD_UNKNOWN; | |
dda83cd7 | 4849 | } |
f62fce35 YQ |
4850 | else |
4851 | return AARCH64_RECORD_UNKNOWN; | |
dda83cd7 | 4852 | } |
f62fce35 YQ |
4853 | else |
4854 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
4855 | } |
4856 | else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e) | |
4857 | { | |
4858 | if (record_debug) | |
b277c936 | 4859 | debug_printf ("SIMD copy"); |
99afc88b OJ |
4860 | |
4861 | /* Advanced SIMD copy instructions. */ | |
4862 | if (!bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
4863 | && !bit (aarch64_insn_r->aarch64_insn, 15) | |
4864 | && bit (aarch64_insn_r->aarch64_insn, 10)) | |
4865 | { | |
4866 | if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07) | |
4867 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
4868 | else | |
4869 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4870 | } | |
4871 | else | |
4872 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4873 | } | |
4874 | /* All remaining floating point or advanced SIMD instructions. */ | |
4875 | else | |
4876 | { | |
4877 | if (record_debug) | |
b277c936 | 4878 | debug_printf ("all remain"); |
99afc88b OJ |
4879 | |
4880 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4881 | } | |
4882 | ||
4883 | if (record_debug) | |
b277c936 | 4884 | debug_printf ("\n"); |
99afc88b | 4885 | |
bfbe4b84 | 4886 | /* Record the V/X register. */ |
99afc88b | 4887 | aarch64_insn_r->reg_rec_count++; |
bfbe4b84 LM |
4888 | |
4889 | /* Some of these instructions may set bits in the FPSR, so record it | |
4890 | too. */ | |
4891 | record_buf[1] = AARCH64_FPSR_REGNUM; | |
4892 | aarch64_insn_r->reg_rec_count++; | |
4893 | ||
4894 | gdb_assert (aarch64_insn_r->reg_rec_count == 2); | |
99afc88b OJ |
4895 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, |
4896 | record_buf); | |
4897 | return AARCH64_RECORD_SUCCESS; | |
4898 | } | |
4899 | ||
4900 | /* Decodes insns type and invokes its record handler. */ | |
4901 | ||
4902 | static unsigned int | |
4748a9be | 4903 | aarch64_record_decode_insn_handler (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4904 | { |
4905 | uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28; | |
4906 | ||
4907 | ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25); | |
4908 | ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26); | |
4909 | ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27); | |
4910 | ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28); | |
4911 | ||
4912 | /* Data processing - immediate instructions. */ | |
4913 | if (!ins_bit26 && !ins_bit27 && ins_bit28) | |
4914 | return aarch64_record_data_proc_imm (aarch64_insn_r); | |
4915 | ||
4916 | /* Branch, exception generation and system instructions. */ | |
4917 | if (ins_bit26 && !ins_bit27 && ins_bit28) | |
4918 | return aarch64_record_branch_except_sys (aarch64_insn_r); | |
4919 | ||
4920 | /* Load and store instructions. */ | |
4921 | if (!ins_bit25 && ins_bit27) | |
4922 | return aarch64_record_load_store (aarch64_insn_r); | |
4923 | ||
4924 | /* Data processing - register instructions. */ | |
4925 | if (ins_bit25 && !ins_bit26 && ins_bit27) | |
4926 | return aarch64_record_data_proc_reg (aarch64_insn_r); | |
4927 | ||
4928 | /* Data processing - SIMD and floating point instructions. */ | |
4929 | if (ins_bit25 && ins_bit26 && ins_bit27) | |
4930 | return aarch64_record_data_proc_simd_fp (aarch64_insn_r); | |
4931 | ||
4932 | return AARCH64_RECORD_UNSUPPORTED; | |
4933 | } | |
4934 | ||
4935 | /* Cleans up local record registers and memory allocations. */ | |
4936 | ||
4937 | static void | |
4748a9be | 4938 | deallocate_reg_mem (aarch64_insn_decode_record *record) |
99afc88b OJ |
4939 | { |
4940 | xfree (record->aarch64_regs); | |
4941 | xfree (record->aarch64_mems); | |
4942 | } | |
4943 | ||
1e2b521d YQ |
4944 | #if GDB_SELF_TEST |
4945 | namespace selftests { | |
4946 | ||
4947 | static void | |
4948 | aarch64_process_record_test (void) | |
4949 | { | |
4950 | struct gdbarch_info info; | |
4951 | uint32_t ret; | |
4952 | ||
1e2b521d YQ |
4953 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); |
4954 | ||
4955 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
4956 | SELF_CHECK (gdbarch != NULL); | |
4957 | ||
4748a9be | 4958 | aarch64_insn_decode_record aarch64_record; |
1e2b521d | 4959 | |
4748a9be | 4960 | memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record)); |
1e2b521d YQ |
4961 | aarch64_record.regcache = NULL; |
4962 | aarch64_record.this_addr = 0; | |
4963 | aarch64_record.gdbarch = gdbarch; | |
4964 | ||
4965 | /* 20 00 80 f9 prfm pldl1keep, [x1] */ | |
4966 | aarch64_record.aarch64_insn = 0xf9800020; | |
4967 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
4968 | SELF_CHECK (ret == AARCH64_RECORD_SUCCESS); | |
4969 | SELF_CHECK (aarch64_record.reg_rec_count == 0); | |
4970 | SELF_CHECK (aarch64_record.mem_rec_count == 0); | |
4971 | ||
4972 | deallocate_reg_mem (&aarch64_record); | |
4973 | } | |
4974 | ||
4975 | } // namespace selftests | |
4976 | #endif /* GDB_SELF_TEST */ | |
4977 | ||
99afc88b OJ |
4978 | /* Parse the current instruction and record the values of the registers and |
4979 | memory that will be changed in current instruction to record_arch_list | |
4980 | return -1 if something is wrong. */ | |
4981 | ||
4982 | int | |
4983 | aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
4984 | CORE_ADDR insn_addr) | |
4985 | { | |
4986 | uint32_t rec_no = 0; | |
4987 | uint8_t insn_size = 4; | |
4988 | uint32_t ret = 0; | |
99afc88b | 4989 | gdb_byte buf[insn_size]; |
4748a9be | 4990 | aarch64_insn_decode_record aarch64_record; |
99afc88b OJ |
4991 | |
4992 | memset (&buf[0], 0, insn_size); | |
4748a9be | 4993 | memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record)); |
99afc88b OJ |
4994 | target_read_memory (insn_addr, &buf[0], insn_size); |
4995 | aarch64_record.aarch64_insn | |
4996 | = (uint32_t) extract_unsigned_integer (&buf[0], | |
4997 | insn_size, | |
4998 | gdbarch_byte_order (gdbarch)); | |
4999 | aarch64_record.regcache = regcache; | |
5000 | aarch64_record.this_addr = insn_addr; | |
5001 | aarch64_record.gdbarch = gdbarch; | |
5002 | ||
5003 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
5004 | if (ret == AARCH64_RECORD_UNSUPPORTED) | |
5005 | { | |
6cb06a8c TT |
5006 | gdb_printf (gdb_stderr, |
5007 | _("Process record does not support instruction " | |
5008 | "0x%0x at address %s.\n"), | |
5009 | aarch64_record.aarch64_insn, | |
5010 | paddress (gdbarch, insn_addr)); | |
99afc88b OJ |
5011 | ret = -1; |
5012 | } | |
5013 | ||
5014 | if (0 == ret) | |
5015 | { | |
5016 | /* Record registers. */ | |
5017 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
5018 | AARCH64_PC_REGNUM); | |
5019 | /* Always record register CPSR. */ | |
5020 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
5021 | AARCH64_CPSR_REGNUM); | |
5022 | if (aarch64_record.aarch64_regs) | |
5023 | for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++) | |
5024 | if (record_full_arch_list_add_reg (aarch64_record.regcache, | |
5025 | aarch64_record.aarch64_regs[rec_no])) | |
5026 | ret = -1; | |
5027 | ||
5028 | /* Record memories. */ | |
5029 | if (aarch64_record.aarch64_mems) | |
5030 | for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++) | |
5031 | if (record_full_arch_list_add_mem | |
5032 | ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr, | |
5033 | aarch64_record.aarch64_mems[rec_no].len)) | |
5034 | ret = -1; | |
5035 | ||
5036 | if (record_full_arch_list_add_end ()) | |
5037 | ret = -1; | |
5038 | } | |
5039 | ||
5040 | deallocate_reg_mem (&aarch64_record); | |
5041 | return ret; | |
5042 | } |