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07b287a0 MS |
1 | /* Common target dependent code for GDB on AArch64 systems. |
2 | ||
4a94e368 | 3 | Copyright (C) 2009-2022 Free Software Foundation, Inc. |
07b287a0 MS |
4 | Contributed by ARM Ltd. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | ||
23 | #include "frame.h" | |
07b287a0 MS |
24 | #include "gdbcmd.h" |
25 | #include "gdbcore.h" | |
4de283e4 | 26 | #include "dis-asm.h" |
d55e5aa6 TT |
27 | #include "regcache.h" |
28 | #include "reggroups.h" | |
4de283e4 TT |
29 | #include "value.h" |
30 | #include "arch-utils.h" | |
31 | #include "osabi.h" | |
32 | #include "frame-unwind.h" | |
33 | #include "frame-base.h" | |
d55e5aa6 | 34 | #include "trad-frame.h" |
4de283e4 TT |
35 | #include "objfiles.h" |
36 | #include "dwarf2.h" | |
82ca8957 | 37 | #include "dwarf2/frame.h" |
4de283e4 TT |
38 | #include "gdbtypes.h" |
39 | #include "prologue-value.h" | |
40 | #include "target-descriptions.h" | |
07b287a0 | 41 | #include "user-regs.h" |
4de283e4 | 42 | #include "ax-gdb.h" |
268a13a5 | 43 | #include "gdbsupport/selftest.h" |
4de283e4 TT |
44 | |
45 | #include "aarch64-tdep.h" | |
46 | #include "aarch64-ravenscar-thread.h" | |
47 | ||
4de283e4 TT |
48 | #include "record.h" |
49 | #include "record-full.h" | |
50 | #include "arch/aarch64-insn.h" | |
0d12e84c | 51 | #include "gdbarch.h" |
4de283e4 TT |
52 | |
53 | #include "opcode/aarch64.h" | |
54 | #include <algorithm> | |
0ee6b1c5 | 55 | #include <unordered_map> |
f77ee802 | 56 | |
ea92689a AH |
57 | /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most |
58 | four members. */ | |
59 | #define HA_MAX_NUM_FLDS 4 | |
60 | ||
95228a0d | 61 | /* All possible aarch64 target descriptors. */ |
0ee6b1c5 | 62 | static std::unordered_map <aarch64_features, target_desc *> tdesc_aarch64_map; |
95228a0d | 63 | |
07b287a0 MS |
64 | /* The standard register names, and all the valid aliases for them. */ |
65 | static const struct | |
66 | { | |
67 | const char *const name; | |
68 | int regnum; | |
69 | } aarch64_register_aliases[] = | |
70 | { | |
71 | /* 64-bit register names. */ | |
72 | {"fp", AARCH64_FP_REGNUM}, | |
73 | {"lr", AARCH64_LR_REGNUM}, | |
74 | {"sp", AARCH64_SP_REGNUM}, | |
75 | ||
76 | /* 32-bit register names. */ | |
77 | {"w0", AARCH64_X0_REGNUM + 0}, | |
78 | {"w1", AARCH64_X0_REGNUM + 1}, | |
79 | {"w2", AARCH64_X0_REGNUM + 2}, | |
80 | {"w3", AARCH64_X0_REGNUM + 3}, | |
81 | {"w4", AARCH64_X0_REGNUM + 4}, | |
82 | {"w5", AARCH64_X0_REGNUM + 5}, | |
83 | {"w6", AARCH64_X0_REGNUM + 6}, | |
84 | {"w7", AARCH64_X0_REGNUM + 7}, | |
85 | {"w8", AARCH64_X0_REGNUM + 8}, | |
86 | {"w9", AARCH64_X0_REGNUM + 9}, | |
87 | {"w10", AARCH64_X0_REGNUM + 10}, | |
88 | {"w11", AARCH64_X0_REGNUM + 11}, | |
89 | {"w12", AARCH64_X0_REGNUM + 12}, | |
90 | {"w13", AARCH64_X0_REGNUM + 13}, | |
91 | {"w14", AARCH64_X0_REGNUM + 14}, | |
92 | {"w15", AARCH64_X0_REGNUM + 15}, | |
93 | {"w16", AARCH64_X0_REGNUM + 16}, | |
94 | {"w17", AARCH64_X0_REGNUM + 17}, | |
95 | {"w18", AARCH64_X0_REGNUM + 18}, | |
96 | {"w19", AARCH64_X0_REGNUM + 19}, | |
97 | {"w20", AARCH64_X0_REGNUM + 20}, | |
98 | {"w21", AARCH64_X0_REGNUM + 21}, | |
99 | {"w22", AARCH64_X0_REGNUM + 22}, | |
100 | {"w23", AARCH64_X0_REGNUM + 23}, | |
101 | {"w24", AARCH64_X0_REGNUM + 24}, | |
102 | {"w25", AARCH64_X0_REGNUM + 25}, | |
103 | {"w26", AARCH64_X0_REGNUM + 26}, | |
104 | {"w27", AARCH64_X0_REGNUM + 27}, | |
105 | {"w28", AARCH64_X0_REGNUM + 28}, | |
106 | {"w29", AARCH64_X0_REGNUM + 29}, | |
107 | {"w30", AARCH64_X0_REGNUM + 30}, | |
108 | ||
109 | /* specials */ | |
110 | {"ip0", AARCH64_X0_REGNUM + 16}, | |
111 | {"ip1", AARCH64_X0_REGNUM + 17} | |
112 | }; | |
113 | ||
114 | /* The required core 'R' registers. */ | |
115 | static const char *const aarch64_r_register_names[] = | |
116 | { | |
117 | /* These registers must appear in consecutive RAW register number | |
118 | order and they must begin with AARCH64_X0_REGNUM! */ | |
119 | "x0", "x1", "x2", "x3", | |
120 | "x4", "x5", "x6", "x7", | |
121 | "x8", "x9", "x10", "x11", | |
122 | "x12", "x13", "x14", "x15", | |
123 | "x16", "x17", "x18", "x19", | |
124 | "x20", "x21", "x22", "x23", | |
125 | "x24", "x25", "x26", "x27", | |
126 | "x28", "x29", "x30", "sp", | |
127 | "pc", "cpsr" | |
128 | }; | |
129 | ||
130 | /* The FP/SIMD 'V' registers. */ | |
131 | static const char *const aarch64_v_register_names[] = | |
132 | { | |
133 | /* These registers must appear in consecutive RAW register number | |
134 | order and they must begin with AARCH64_V0_REGNUM! */ | |
135 | "v0", "v1", "v2", "v3", | |
136 | "v4", "v5", "v6", "v7", | |
137 | "v8", "v9", "v10", "v11", | |
138 | "v12", "v13", "v14", "v15", | |
139 | "v16", "v17", "v18", "v19", | |
140 | "v20", "v21", "v22", "v23", | |
141 | "v24", "v25", "v26", "v27", | |
142 | "v28", "v29", "v30", "v31", | |
143 | "fpsr", | |
144 | "fpcr" | |
145 | }; | |
146 | ||
739e8682 AH |
147 | /* The SVE 'Z' and 'P' registers. */ |
148 | static const char *const aarch64_sve_register_names[] = | |
149 | { | |
150 | /* These registers must appear in consecutive RAW register number | |
151 | order and they must begin with AARCH64_SVE_Z0_REGNUM! */ | |
152 | "z0", "z1", "z2", "z3", | |
153 | "z4", "z5", "z6", "z7", | |
154 | "z8", "z9", "z10", "z11", | |
155 | "z12", "z13", "z14", "z15", | |
156 | "z16", "z17", "z18", "z19", | |
157 | "z20", "z21", "z22", "z23", | |
158 | "z24", "z25", "z26", "z27", | |
159 | "z28", "z29", "z30", "z31", | |
160 | "fpsr", "fpcr", | |
161 | "p0", "p1", "p2", "p3", | |
162 | "p4", "p5", "p6", "p7", | |
163 | "p8", "p9", "p10", "p11", | |
164 | "p12", "p13", "p14", "p15", | |
165 | "ffr", "vg" | |
166 | }; | |
167 | ||
76bed0fd AH |
168 | static const char *const aarch64_pauth_register_names[] = |
169 | { | |
170 | /* Authentication mask for data pointer. */ | |
171 | "pauth_dmask", | |
172 | /* Authentication mask for code pointer. */ | |
173 | "pauth_cmask" | |
174 | }; | |
175 | ||
5e984dbf LM |
176 | static const char *const aarch64_mte_register_names[] = |
177 | { | |
178 | /* Tag Control Register. */ | |
179 | "tag_ctl" | |
180 | }; | |
181 | ||
07b287a0 MS |
182 | /* AArch64 prologue cache structure. */ |
183 | struct aarch64_prologue_cache | |
184 | { | |
db634143 PL |
185 | /* The program counter at the start of the function. It is used to |
186 | identify this frame as a prologue frame. */ | |
187 | CORE_ADDR func; | |
188 | ||
189 | /* The program counter at the time this frame was created; i.e. where | |
190 | this function was called from. It is used to identify this frame as a | |
191 | stub frame. */ | |
192 | CORE_ADDR prev_pc; | |
193 | ||
07b287a0 MS |
194 | /* The stack pointer at the time this frame was created; i.e. the |
195 | caller's stack pointer when this function was called. It is used | |
196 | to identify this frame. */ | |
197 | CORE_ADDR prev_sp; | |
198 | ||
7dfa3edc PL |
199 | /* Is the target available to read from? */ |
200 | int available_p; | |
201 | ||
07b287a0 MS |
202 | /* The frame base for this frame is just prev_sp - frame size. |
203 | FRAMESIZE is the distance from the frame pointer to the | |
204 | initial stack pointer. */ | |
205 | int framesize; | |
206 | ||
207 | /* The register used to hold the frame pointer for this frame. */ | |
208 | int framereg; | |
209 | ||
210 | /* Saved register offsets. */ | |
098caef4 | 211 | trad_frame_saved_reg *saved_regs; |
07b287a0 MS |
212 | }; |
213 | ||
07b287a0 MS |
214 | static void |
215 | show_aarch64_debug (struct ui_file *file, int from_tty, | |
dda83cd7 | 216 | struct cmd_list_element *c, const char *value) |
07b287a0 | 217 | { |
6cb06a8c | 218 | gdb_printf (file, _("AArch64 debugging is %s.\n"), value); |
07b287a0 MS |
219 | } |
220 | ||
ffdbe864 YQ |
221 | namespace { |
222 | ||
4d9a9006 YQ |
223 | /* Abstract instruction reader. */ |
224 | ||
225 | class abstract_instruction_reader | |
226 | { | |
227 | public: | |
228 | /* Read in one instruction. */ | |
229 | virtual ULONGEST read (CORE_ADDR memaddr, int len, | |
230 | enum bfd_endian byte_order) = 0; | |
231 | }; | |
232 | ||
233 | /* Instruction reader from real target. */ | |
234 | ||
235 | class instruction_reader : public abstract_instruction_reader | |
236 | { | |
237 | public: | |
238 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
632e107b | 239 | override |
4d9a9006 | 240 | { |
fc2f703e | 241 | return read_code_unsigned_integer (memaddr, len, byte_order); |
4d9a9006 YQ |
242 | } |
243 | }; | |
244 | ||
ffdbe864 YQ |
245 | } // namespace |
246 | ||
3d31bc39 AH |
247 | /* If address signing is enabled, mask off the signature bits from the link |
248 | register, which is passed by value in ADDR, using the register values in | |
249 | THIS_FRAME. */ | |
11e1b75f AH |
250 | |
251 | static CORE_ADDR | |
345bd07c | 252 | aarch64_frame_unmask_lr (aarch64_gdbarch_tdep *tdep, |
3d31bc39 | 253 | struct frame_info *this_frame, CORE_ADDR addr) |
11e1b75f AH |
254 | { |
255 | if (tdep->has_pauth () | |
256 | && frame_unwind_register_unsigned (this_frame, | |
c9cd8ca4 | 257 | tdep->ra_sign_state_regnum)) |
11e1b75f AH |
258 | { |
259 | int cmask_num = AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base); | |
260 | CORE_ADDR cmask = frame_unwind_register_unsigned (this_frame, cmask_num); | |
261 | addr = addr & ~cmask; | |
3d31bc39 AH |
262 | |
263 | /* Record in the frame that the link register required unmasking. */ | |
264 | set_frame_previous_pc_masked (this_frame); | |
11e1b75f AH |
265 | } |
266 | ||
267 | return addr; | |
268 | } | |
269 | ||
aa7ca1bb AH |
270 | /* Implement the "get_pc_address_flags" gdbarch method. */ |
271 | ||
272 | static std::string | |
273 | aarch64_get_pc_address_flags (frame_info *frame, CORE_ADDR pc) | |
274 | { | |
275 | if (pc != 0 && get_frame_pc_masked (frame)) | |
276 | return "PAC"; | |
277 | ||
278 | return ""; | |
279 | } | |
280 | ||
07b287a0 MS |
281 | /* Analyze a prologue, looking for a recognizable stack frame |
282 | and frame pointer. Scan until we encounter a store that could | |
283 | clobber the stack frame unexpectedly, or an unknown instruction. */ | |
284 | ||
285 | static CORE_ADDR | |
286 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
287 | CORE_ADDR start, CORE_ADDR limit, | |
4d9a9006 YQ |
288 | struct aarch64_prologue_cache *cache, |
289 | abstract_instruction_reader& reader) | |
07b287a0 MS |
290 | { |
291 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
292 | int i; | |
f8e3fe0d LM |
293 | |
294 | /* Whether the stack has been set. This should be true when we notice a SP | |
295 | to FP move or if we are using the SP as the base register for storing | |
296 | data, in case the FP is ommitted. */ | |
297 | bool seen_stack_set = false; | |
298 | ||
187f5d00 YQ |
299 | /* Track X registers and D registers in prologue. */ |
300 | pv_t regs[AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT]; | |
07b287a0 | 301 | |
187f5d00 | 302 | for (i = 0; i < AARCH64_X_REGISTER_COUNT + AARCH64_D_REGISTER_COUNT; i++) |
07b287a0 | 303 | regs[i] = pv_register (i, 0); |
f7b7ed97 | 304 | pv_area stack (AARCH64_SP_REGNUM, gdbarch_addr_bit (gdbarch)); |
07b287a0 MS |
305 | |
306 | for (; start < limit; start += 4) | |
307 | { | |
308 | uint32_t insn; | |
d9ebcbce | 309 | aarch64_inst inst; |
07b287a0 | 310 | |
4d9a9006 | 311 | insn = reader.read (start, 4, byte_order_for_code); |
07b287a0 | 312 | |
561a72d4 | 313 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
d9ebcbce YQ |
314 | break; |
315 | ||
316 | if (inst.opcode->iclass == addsub_imm | |
317 | && (inst.opcode->op == OP_ADD | |
318 | || strcmp ("sub", inst.opcode->name) == 0)) | |
07b287a0 | 319 | { |
d9ebcbce YQ |
320 | unsigned rd = inst.operands[0].reg.regno; |
321 | unsigned rn = inst.operands[1].reg.regno; | |
322 | ||
323 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 3); | |
324 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP); | |
325 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP); | |
326 | gdb_assert (inst.operands[2].type == AARCH64_OPND_AIMM); | |
327 | ||
328 | if (inst.opcode->op == OP_ADD) | |
329 | { | |
330 | regs[rd] = pv_add_constant (regs[rn], | |
331 | inst.operands[2].imm.value); | |
332 | } | |
333 | else | |
334 | { | |
335 | regs[rd] = pv_add_constant (regs[rn], | |
336 | -inst.operands[2].imm.value); | |
337 | } | |
f8e3fe0d LM |
338 | |
339 | /* Did we move SP to FP? */ | |
340 | if (rn == AARCH64_SP_REGNUM && rd == AARCH64_FP_REGNUM) | |
341 | seen_stack_set = true; | |
d9ebcbce | 342 | } |
60adf22c TV |
343 | else if (inst.opcode->iclass == addsub_ext |
344 | && strcmp ("sub", inst.opcode->name) == 0) | |
345 | { | |
346 | unsigned rd = inst.operands[0].reg.regno; | |
347 | unsigned rn = inst.operands[1].reg.regno; | |
348 | unsigned rm = inst.operands[2].reg.regno; | |
349 | ||
350 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 3); | |
351 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd_SP); | |
352 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn_SP); | |
353 | gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_EXT); | |
354 | ||
355 | regs[rd] = pv_subtract (regs[rn], regs[rm]); | |
356 | } | |
d9ebcbce | 357 | else if (inst.opcode->iclass == branch_imm) |
07b287a0 MS |
358 | { |
359 | /* Stop analysis on branch. */ | |
360 | break; | |
361 | } | |
d9ebcbce | 362 | else if (inst.opcode->iclass == condbranch) |
07b287a0 MS |
363 | { |
364 | /* Stop analysis on branch. */ | |
365 | break; | |
366 | } | |
d9ebcbce | 367 | else if (inst.opcode->iclass == branch_reg) |
07b287a0 MS |
368 | { |
369 | /* Stop analysis on branch. */ | |
370 | break; | |
371 | } | |
d9ebcbce | 372 | else if (inst.opcode->iclass == compbranch) |
07b287a0 MS |
373 | { |
374 | /* Stop analysis on branch. */ | |
375 | break; | |
376 | } | |
d9ebcbce YQ |
377 | else if (inst.opcode->op == OP_MOVZ) |
378 | { | |
60adf22c TV |
379 | unsigned rd = inst.operands[0].reg.regno; |
380 | ||
381 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
d9ebcbce | 382 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); |
60adf22c TV |
383 | gdb_assert (inst.operands[1].type == AARCH64_OPND_HALF); |
384 | gdb_assert (inst.operands[1].shifter.kind == AARCH64_MOD_LSL); | |
f8e3fe0d LM |
385 | |
386 | /* If this shows up before we set the stack, keep going. Otherwise | |
387 | stop the analysis. */ | |
388 | if (seen_stack_set) | |
389 | break; | |
390 | ||
60adf22c TV |
391 | regs[rd] = pv_constant (inst.operands[1].imm.value |
392 | << inst.operands[1].shifter.amount); | |
d9ebcbce YQ |
393 | } |
394 | else if (inst.opcode->iclass == log_shift | |
395 | && strcmp (inst.opcode->name, "orr") == 0) | |
07b287a0 | 396 | { |
d9ebcbce YQ |
397 | unsigned rd = inst.operands[0].reg.regno; |
398 | unsigned rn = inst.operands[1].reg.regno; | |
399 | unsigned rm = inst.operands[2].reg.regno; | |
400 | ||
401 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rd); | |
402 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rn); | |
403 | gdb_assert (inst.operands[2].type == AARCH64_OPND_Rm_SFT); | |
404 | ||
405 | if (inst.operands[2].shifter.amount == 0 | |
406 | && rn == AARCH64_SP_REGNUM) | |
07b287a0 MS |
407 | regs[rd] = regs[rm]; |
408 | else | |
409 | { | |
c6185dce SM |
410 | aarch64_debug_printf ("prologue analysis gave up " |
411 | "addr=%s opcode=0x%x (orr x register)", | |
412 | core_addr_to_string_nz (start), insn); | |
413 | ||
07b287a0 MS |
414 | break; |
415 | } | |
416 | } | |
d9ebcbce | 417 | else if (inst.opcode->op == OP_STUR) |
07b287a0 | 418 | { |
d9ebcbce YQ |
419 | unsigned rt = inst.operands[0].reg.regno; |
420 | unsigned rn = inst.operands[1].addr.base_regno; | |
75faf5c4 | 421 | int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); |
d9ebcbce YQ |
422 | |
423 | gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); | |
424 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt); | |
425 | gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9); | |
426 | gdb_assert (!inst.operands[1].addr.offset.is_reg); | |
427 | ||
75faf5c4 AH |
428 | stack.store |
429 | (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), | |
430 | size, regs[rt]); | |
f8e3fe0d LM |
431 | |
432 | /* Are we storing with SP as a base? */ | |
433 | if (rn == AARCH64_SP_REGNUM) | |
434 | seen_stack_set = true; | |
07b287a0 | 435 | } |
d9ebcbce | 436 | else if ((inst.opcode->iclass == ldstpair_off |
03bcd739 YQ |
437 | || (inst.opcode->iclass == ldstpair_indexed |
438 | && inst.operands[2].addr.preind)) | |
d9ebcbce | 439 | && strcmp ("stp", inst.opcode->name) == 0) |
07b287a0 | 440 | { |
03bcd739 | 441 | /* STP with addressing mode Pre-indexed and Base register. */ |
187f5d00 YQ |
442 | unsigned rt1; |
443 | unsigned rt2; | |
d9ebcbce YQ |
444 | unsigned rn = inst.operands[2].addr.base_regno; |
445 | int32_t imm = inst.operands[2].addr.offset.imm; | |
75faf5c4 | 446 | int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); |
d9ebcbce | 447 | |
187f5d00 YQ |
448 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt |
449 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
450 | gdb_assert (inst.operands[1].type == AARCH64_OPND_Rt2 | |
451 | || inst.operands[1].type == AARCH64_OPND_Ft2); | |
d9ebcbce YQ |
452 | gdb_assert (inst.operands[2].type == AARCH64_OPND_ADDR_SIMM7); |
453 | gdb_assert (!inst.operands[2].addr.offset.is_reg); | |
454 | ||
07b287a0 MS |
455 | /* If recording this store would invalidate the store area |
456 | (perhaps because rn is not known) then we should abandon | |
457 | further prologue analysis. */ | |
f7b7ed97 | 458 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm))) |
07b287a0 MS |
459 | break; |
460 | ||
f7b7ed97 | 461 | if (stack.store_would_trash (pv_add_constant (regs[rn], imm + 8))) |
07b287a0 MS |
462 | break; |
463 | ||
187f5d00 YQ |
464 | rt1 = inst.operands[0].reg.regno; |
465 | rt2 = inst.operands[1].reg.regno; | |
466 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
467 | { | |
187f5d00 YQ |
468 | rt1 += AARCH64_X_REGISTER_COUNT; |
469 | rt2 += AARCH64_X_REGISTER_COUNT; | |
470 | } | |
471 | ||
75faf5c4 AH |
472 | stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]); |
473 | stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]); | |
14ac654f | 474 | |
d9ebcbce | 475 | if (inst.operands[2].addr.writeback) |
93d96012 | 476 | regs[rn] = pv_add_constant (regs[rn], imm); |
07b287a0 | 477 | |
f8e3fe0d LM |
478 | /* Ignore the instruction that allocates stack space and sets |
479 | the SP. */ | |
480 | if (rn == AARCH64_SP_REGNUM && !inst.operands[2].addr.writeback) | |
481 | seen_stack_set = true; | |
07b287a0 | 482 | } |
432ec081 YQ |
483 | else if ((inst.opcode->iclass == ldst_imm9 /* Signed immediate. */ |
484 | || (inst.opcode->iclass == ldst_pos /* Unsigned immediate. */ | |
485 | && (inst.opcode->op == OP_STR_POS | |
486 | || inst.opcode->op == OP_STRF_POS))) | |
487 | && inst.operands[1].addr.base_regno == AARCH64_SP_REGNUM | |
488 | && strcmp ("str", inst.opcode->name) == 0) | |
489 | { | |
490 | /* STR (immediate) */ | |
491 | unsigned int rt = inst.operands[0].reg.regno; | |
492 | int32_t imm = inst.operands[1].addr.offset.imm; | |
493 | unsigned int rn = inst.operands[1].addr.base_regno; | |
75faf5c4 | 494 | int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); |
432ec081 YQ |
495 | gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt |
496 | || inst.operands[0].type == AARCH64_OPND_Ft); | |
497 | ||
498 | if (inst.operands[0].type == AARCH64_OPND_Ft) | |
75faf5c4 | 499 | rt += AARCH64_X_REGISTER_COUNT; |
432ec081 | 500 | |
75faf5c4 | 501 | stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]); |
432ec081 YQ |
502 | if (inst.operands[1].addr.writeback) |
503 | regs[rn] = pv_add_constant (regs[rn], imm); | |
f8e3fe0d LM |
504 | |
505 | /* Are we storing with SP as a base? */ | |
506 | if (rn == AARCH64_SP_REGNUM) | |
507 | seen_stack_set = true; | |
432ec081 | 508 | } |
d9ebcbce | 509 | else if (inst.opcode->iclass == testbranch) |
07b287a0 MS |
510 | { |
511 | /* Stop analysis on branch. */ | |
512 | break; | |
513 | } | |
17e116a7 AH |
514 | else if (inst.opcode->iclass == ic_system) |
515 | { | |
345bd07c | 516 | aarch64_gdbarch_tdep *tdep |
08106042 | 517 | = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
17e116a7 AH |
518 | int ra_state_val = 0; |
519 | ||
520 | if (insn == 0xd503233f /* paciasp. */ | |
521 | || insn == 0xd503237f /* pacibsp. */) | |
522 | { | |
523 | /* Return addresses are mangled. */ | |
524 | ra_state_val = 1; | |
525 | } | |
526 | else if (insn == 0xd50323bf /* autiasp. */ | |
527 | || insn == 0xd50323ff /* autibsp. */) | |
528 | { | |
529 | /* Return addresses are not mangled. */ | |
530 | ra_state_val = 0; | |
531 | } | |
37989733 LM |
532 | else if (IS_BTI (insn)) |
533 | /* We don't need to do anything special for a BTI instruction. */ | |
534 | continue; | |
17e116a7 AH |
535 | else |
536 | { | |
c6185dce SM |
537 | aarch64_debug_printf ("prologue analysis gave up addr=%s" |
538 | " opcode=0x%x (iclass)", | |
539 | core_addr_to_string_nz (start), insn); | |
17e116a7 AH |
540 | break; |
541 | } | |
542 | ||
543 | if (tdep->has_pauth () && cache != nullptr) | |
a9a87d35 | 544 | { |
c9cd8ca4 | 545 | int regnum = tdep->ra_sign_state_regnum; |
a9a87d35 LM |
546 | cache->saved_regs[regnum].set_value (ra_state_val); |
547 | } | |
17e116a7 | 548 | } |
07b287a0 MS |
549 | else |
550 | { | |
c6185dce SM |
551 | aarch64_debug_printf ("prologue analysis gave up addr=%s" |
552 | " opcode=0x%x", | |
553 | core_addr_to_string_nz (start), insn); | |
554 | ||
07b287a0 MS |
555 | break; |
556 | } | |
557 | } | |
558 | ||
559 | if (cache == NULL) | |
f7b7ed97 | 560 | return start; |
07b287a0 MS |
561 | |
562 | if (pv_is_register (regs[AARCH64_FP_REGNUM], AARCH64_SP_REGNUM)) | |
563 | { | |
564 | /* Frame pointer is fp. Frame size is constant. */ | |
565 | cache->framereg = AARCH64_FP_REGNUM; | |
566 | cache->framesize = -regs[AARCH64_FP_REGNUM].k; | |
567 | } | |
568 | else if (pv_is_register (regs[AARCH64_SP_REGNUM], AARCH64_SP_REGNUM)) | |
569 | { | |
570 | /* Try the stack pointer. */ | |
571 | cache->framesize = -regs[AARCH64_SP_REGNUM].k; | |
572 | cache->framereg = AARCH64_SP_REGNUM; | |
573 | } | |
574 | else | |
575 | { | |
576 | /* We're just out of luck. We don't know where the frame is. */ | |
577 | cache->framereg = -1; | |
578 | cache->framesize = 0; | |
579 | } | |
580 | ||
581 | for (i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
582 | { | |
583 | CORE_ADDR offset; | |
584 | ||
f7b7ed97 | 585 | if (stack.find_reg (gdbarch, i, &offset)) |
098caef4 | 586 | cache->saved_regs[i].set_addr (offset); |
07b287a0 MS |
587 | } |
588 | ||
187f5d00 YQ |
589 | for (i = 0; i < AARCH64_D_REGISTER_COUNT; i++) |
590 | { | |
591 | int regnum = gdbarch_num_regs (gdbarch); | |
592 | CORE_ADDR offset; | |
593 | ||
f7b7ed97 TT |
594 | if (stack.find_reg (gdbarch, i + AARCH64_X_REGISTER_COUNT, |
595 | &offset)) | |
098caef4 | 596 | cache->saved_regs[i + regnum + AARCH64_D0_REGNUM].set_addr (offset); |
187f5d00 YQ |
597 | } |
598 | ||
07b287a0 MS |
599 | return start; |
600 | } | |
601 | ||
4d9a9006 YQ |
602 | static CORE_ADDR |
603 | aarch64_analyze_prologue (struct gdbarch *gdbarch, | |
604 | CORE_ADDR start, CORE_ADDR limit, | |
605 | struct aarch64_prologue_cache *cache) | |
606 | { | |
607 | instruction_reader reader; | |
608 | ||
609 | return aarch64_analyze_prologue (gdbarch, start, limit, cache, | |
610 | reader); | |
611 | } | |
612 | ||
613 | #if GDB_SELF_TEST | |
614 | ||
615 | namespace selftests { | |
616 | ||
617 | /* Instruction reader from manually cooked instruction sequences. */ | |
618 | ||
619 | class instruction_reader_test : public abstract_instruction_reader | |
620 | { | |
621 | public: | |
622 | template<size_t SIZE> | |
623 | explicit instruction_reader_test (const uint32_t (&insns)[SIZE]) | |
624 | : m_insns (insns), m_insns_size (SIZE) | |
625 | {} | |
626 | ||
627 | ULONGEST read (CORE_ADDR memaddr, int len, enum bfd_endian byte_order) | |
632e107b | 628 | override |
4d9a9006 YQ |
629 | { |
630 | SELF_CHECK (len == 4); | |
631 | SELF_CHECK (memaddr % 4 == 0); | |
632 | SELF_CHECK (memaddr / 4 < m_insns_size); | |
633 | ||
634 | return m_insns[memaddr / 4]; | |
635 | } | |
636 | ||
637 | private: | |
638 | const uint32_t *m_insns; | |
639 | size_t m_insns_size; | |
640 | }; | |
641 | ||
642 | static void | |
643 | aarch64_analyze_prologue_test (void) | |
644 | { | |
645 | struct gdbarch_info info; | |
646 | ||
4d9a9006 YQ |
647 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); |
648 | ||
649 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
650 | SELF_CHECK (gdbarch != NULL); | |
651 | ||
17e116a7 AH |
652 | struct aarch64_prologue_cache cache; |
653 | cache.saved_regs = trad_frame_alloc_saved_regs (gdbarch); | |
654 | ||
08106042 | 655 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
17e116a7 | 656 | |
4d9a9006 YQ |
657 | /* Test the simple prologue in which frame pointer is used. */ |
658 | { | |
4d9a9006 YQ |
659 | static const uint32_t insns[] = { |
660 | 0xa9af7bfd, /* stp x29, x30, [sp,#-272]! */ | |
661 | 0x910003fd, /* mov x29, sp */ | |
662 | 0x97ffffe6, /* bl 0x400580 */ | |
663 | }; | |
664 | instruction_reader_test reader (insns); | |
665 | ||
666 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
667 | SELF_CHECK (end == 4 * 2); | |
668 | ||
669 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
670 | SELF_CHECK (cache.framesize == 272); | |
671 | ||
672 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
673 | { | |
674 | if (i == AARCH64_FP_REGNUM) | |
098caef4 | 675 | SELF_CHECK (cache.saved_regs[i].addr () == -272); |
4d9a9006 | 676 | else if (i == AARCH64_LR_REGNUM) |
098caef4 | 677 | SELF_CHECK (cache.saved_regs[i].addr () == -264); |
4d9a9006 | 678 | else |
a9a87d35 LM |
679 | SELF_CHECK (cache.saved_regs[i].is_realreg () |
680 | && cache.saved_regs[i].realreg () == i); | |
4d9a9006 YQ |
681 | } |
682 | ||
683 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
684 | { | |
a9a87d35 LM |
685 | int num_regs = gdbarch_num_regs (gdbarch); |
686 | int regnum = i + num_regs + AARCH64_D0_REGNUM; | |
4d9a9006 | 687 | |
a9a87d35 LM |
688 | SELF_CHECK (cache.saved_regs[regnum].is_realreg () |
689 | && cache.saved_regs[regnum].realreg () == regnum); | |
4d9a9006 YQ |
690 | } |
691 | } | |
432ec081 YQ |
692 | |
693 | /* Test a prologue in which STR is used and frame pointer is not | |
694 | used. */ | |
695 | { | |
432ec081 YQ |
696 | static const uint32_t insns[] = { |
697 | 0xf81d0ff3, /* str x19, [sp, #-48]! */ | |
698 | 0xb9002fe0, /* str w0, [sp, #44] */ | |
699 | 0xf90013e1, /* str x1, [sp, #32]*/ | |
700 | 0xfd000fe0, /* str d0, [sp, #24] */ | |
701 | 0xaa0203f3, /* mov x19, x2 */ | |
702 | 0xf94013e0, /* ldr x0, [sp, #32] */ | |
703 | }; | |
704 | instruction_reader_test reader (insns); | |
705 | ||
68811f8f | 706 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); |
432ec081 YQ |
707 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); |
708 | ||
709 | SELF_CHECK (end == 4 * 5); | |
710 | ||
711 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
712 | SELF_CHECK (cache.framesize == 48); | |
713 | ||
714 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
715 | { | |
716 | if (i == 1) | |
098caef4 | 717 | SELF_CHECK (cache.saved_regs[i].addr () == -16); |
432ec081 | 718 | else if (i == 19) |
098caef4 | 719 | SELF_CHECK (cache.saved_regs[i].addr () == -48); |
432ec081 | 720 | else |
a9a87d35 LM |
721 | SELF_CHECK (cache.saved_regs[i].is_realreg () |
722 | && cache.saved_regs[i].realreg () == i); | |
432ec081 YQ |
723 | } |
724 | ||
725 | for (int i = 0; i < AARCH64_D_REGISTER_COUNT; i++) | |
726 | { | |
a9a87d35 LM |
727 | int num_regs = gdbarch_num_regs (gdbarch); |
728 | int regnum = i + num_regs + AARCH64_D0_REGNUM; | |
729 | ||
432ec081 YQ |
730 | |
731 | if (i == 0) | |
a9a87d35 | 732 | SELF_CHECK (cache.saved_regs[regnum].addr () == -24); |
432ec081 | 733 | else |
a9a87d35 LM |
734 | SELF_CHECK (cache.saved_regs[regnum].is_realreg () |
735 | && cache.saved_regs[regnum].realreg () == regnum); | |
432ec081 YQ |
736 | } |
737 | } | |
17e116a7 | 738 | |
f8e3fe0d LM |
739 | /* Test handling of movz before setting the frame pointer. */ |
740 | { | |
741 | static const uint32_t insns[] = { | |
742 | 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */ | |
743 | 0x52800020, /* mov w0, #0x1 */ | |
744 | 0x910003fd, /* mov x29, sp */ | |
745 | 0x528000a2, /* mov w2, #0x5 */ | |
746 | 0x97fffff8, /* bl 6e4 */ | |
747 | }; | |
748 | ||
749 | instruction_reader_test reader (insns); | |
750 | ||
751 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
752 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
753 | ||
754 | /* We should stop at the 4th instruction. */ | |
755 | SELF_CHECK (end == (4 - 1) * 4); | |
756 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
757 | SELF_CHECK (cache.framesize == 16); | |
758 | } | |
759 | ||
760 | /* Test handling of movz/stp when using the stack pointer as frame | |
761 | pointer. */ | |
762 | { | |
763 | static const uint32_t insns[] = { | |
764 | 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */ | |
765 | 0x52800020, /* mov w0, #0x1 */ | |
766 | 0x290207e0, /* stp w0, w1, [sp, #16] */ | |
767 | 0xa9018fe2, /* stp x2, x3, [sp, #24] */ | |
768 | 0x528000a2, /* mov w2, #0x5 */ | |
769 | 0x97fffff8, /* bl 6e4 */ | |
770 | }; | |
771 | ||
772 | instruction_reader_test reader (insns); | |
773 | ||
774 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
775 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
776 | ||
777 | /* We should stop at the 5th instruction. */ | |
778 | SELF_CHECK (end == (5 - 1) * 4); | |
779 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
780 | SELF_CHECK (cache.framesize == 64); | |
781 | } | |
782 | ||
783 | /* Test handling of movz/str when using the stack pointer as frame | |
784 | pointer */ | |
785 | { | |
786 | static const uint32_t insns[] = { | |
787 | 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */ | |
788 | 0x52800020, /* mov w0, #0x1 */ | |
789 | 0xb9002be4, /* str w4, [sp, #40] */ | |
790 | 0xf9001be5, /* str x5, [sp, #48] */ | |
791 | 0x528000a2, /* mov w2, #0x5 */ | |
792 | 0x97fffff8, /* bl 6e4 */ | |
793 | }; | |
794 | ||
795 | instruction_reader_test reader (insns); | |
796 | ||
797 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
798 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
799 | ||
800 | /* We should stop at the 5th instruction. */ | |
801 | SELF_CHECK (end == (5 - 1) * 4); | |
802 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
803 | SELF_CHECK (cache.framesize == 64); | |
804 | } | |
805 | ||
806 | /* Test handling of movz/stur when using the stack pointer as frame | |
807 | pointer. */ | |
808 | { | |
809 | static const uint32_t insns[] = { | |
810 | 0xa9bc7bfd, /* stp x29, x30, [sp, #-64]! */ | |
811 | 0x52800020, /* mov w0, #0x1 */ | |
812 | 0xb80343e6, /* stur w6, [sp, #52] */ | |
813 | 0xf80383e7, /* stur x7, [sp, #56] */ | |
814 | 0x528000a2, /* mov w2, #0x5 */ | |
815 | 0x97fffff8, /* bl 6e4 */ | |
816 | }; | |
817 | ||
818 | instruction_reader_test reader (insns); | |
819 | ||
820 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
821 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
822 | ||
823 | /* We should stop at the 5th instruction. */ | |
824 | SELF_CHECK (end == (5 - 1) * 4); | |
825 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
826 | SELF_CHECK (cache.framesize == 64); | |
827 | } | |
828 | ||
829 | /* Test handling of movz when there is no frame pointer set or no stack | |
830 | pointer used. */ | |
831 | { | |
832 | static const uint32_t insns[] = { | |
833 | 0xa9bf7bfd, /* stp x29, x30, [sp, #-16]! */ | |
834 | 0x52800020, /* mov w0, #0x1 */ | |
835 | 0x528000a2, /* mov w2, #0x5 */ | |
836 | 0x97fffff8, /* bl 6e4 */ | |
837 | }; | |
838 | ||
839 | instruction_reader_test reader (insns); | |
840 | ||
841 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
842 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, reader); | |
843 | ||
844 | /* We should stop at the 4th instruction. */ | |
845 | SELF_CHECK (end == (4 - 1) * 4); | |
846 | SELF_CHECK (cache.framereg == AARCH64_SP_REGNUM); | |
847 | SELF_CHECK (cache.framesize == 16); | |
848 | } | |
849 | ||
17e116a7 AH |
850 | /* Test a prologue in which there is a return address signing instruction. */ |
851 | if (tdep->has_pauth ()) | |
852 | { | |
853 | static const uint32_t insns[] = { | |
854 | 0xd503233f, /* paciasp */ | |
855 | 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */ | |
856 | 0x910003fd, /* mov x29, sp */ | |
857 | 0xf801c3f3, /* str x19, [sp, #28] */ | |
858 | 0xb9401fa0, /* ldr x19, [x29, #28] */ | |
859 | }; | |
860 | instruction_reader_test reader (insns); | |
861 | ||
68811f8f | 862 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); |
17e116a7 AH |
863 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, |
864 | reader); | |
865 | ||
866 | SELF_CHECK (end == 4 * 4); | |
867 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
868 | SELF_CHECK (cache.framesize == 48); | |
869 | ||
870 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
871 | { | |
872 | if (i == 19) | |
098caef4 | 873 | SELF_CHECK (cache.saved_regs[i].addr () == -20); |
17e116a7 | 874 | else if (i == AARCH64_FP_REGNUM) |
098caef4 | 875 | SELF_CHECK (cache.saved_regs[i].addr () == -48); |
17e116a7 | 876 | else if (i == AARCH64_LR_REGNUM) |
098caef4 | 877 | SELF_CHECK (cache.saved_regs[i].addr () == -40); |
17e116a7 | 878 | else |
a9a87d35 LM |
879 | SELF_CHECK (cache.saved_regs[i].is_realreg () |
880 | && cache.saved_regs[i].realreg () == i); | |
17e116a7 AH |
881 | } |
882 | ||
883 | if (tdep->has_pauth ()) | |
884 | { | |
c9cd8ca4 | 885 | int regnum = tdep->ra_sign_state_regnum; |
a9a87d35 | 886 | SELF_CHECK (cache.saved_regs[regnum].is_value ()); |
17e116a7 AH |
887 | } |
888 | } | |
37989733 LM |
889 | |
890 | /* Test a prologue with a BTI instruction. */ | |
891 | { | |
892 | static const uint32_t insns[] = { | |
893 | 0xd503245f, /* bti */ | |
894 | 0xa9bd7bfd, /* stp x29, x30, [sp, #-48]! */ | |
895 | 0x910003fd, /* mov x29, sp */ | |
896 | 0xf801c3f3, /* str x19, [sp, #28] */ | |
897 | 0xb9401fa0, /* ldr x19, [x29, #28] */ | |
898 | }; | |
899 | instruction_reader_test reader (insns); | |
900 | ||
901 | trad_frame_reset_saved_regs (gdbarch, cache.saved_regs); | |
902 | CORE_ADDR end = aarch64_analyze_prologue (gdbarch, 0, 128, &cache, | |
903 | reader); | |
904 | ||
905 | SELF_CHECK (end == 4 * 4); | |
906 | SELF_CHECK (cache.framereg == AARCH64_FP_REGNUM); | |
907 | SELF_CHECK (cache.framesize == 48); | |
908 | ||
909 | for (int i = 0; i < AARCH64_X_REGISTER_COUNT; i++) | |
910 | { | |
911 | if (i == 19) | |
912 | SELF_CHECK (cache.saved_regs[i].addr () == -20); | |
913 | else if (i == AARCH64_FP_REGNUM) | |
914 | SELF_CHECK (cache.saved_regs[i].addr () == -48); | |
915 | else if (i == AARCH64_LR_REGNUM) | |
916 | SELF_CHECK (cache.saved_regs[i].addr () == -40); | |
917 | else | |
918 | SELF_CHECK (cache.saved_regs[i].is_realreg () | |
919 | && cache.saved_regs[i].realreg () == i); | |
920 | } | |
921 | } | |
4d9a9006 YQ |
922 | } |
923 | } // namespace selftests | |
924 | #endif /* GDB_SELF_TEST */ | |
925 | ||
07b287a0 MS |
926 | /* Implement the "skip_prologue" gdbarch method. */ |
927 | ||
928 | static CORE_ADDR | |
929 | aarch64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
930 | { | |
07b287a0 | 931 | CORE_ADDR func_addr, limit_pc; |
07b287a0 MS |
932 | |
933 | /* See if we can determine the end of the prologue via the symbol | |
934 | table. If so, then return either PC, or the PC after the | |
935 | prologue, whichever is greater. */ | |
936 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
937 | { | |
938 | CORE_ADDR post_prologue_pc | |
939 | = skip_prologue_using_sal (gdbarch, func_addr); | |
940 | ||
941 | if (post_prologue_pc != 0) | |
325fac50 | 942 | return std::max (pc, post_prologue_pc); |
07b287a0 MS |
943 | } |
944 | ||
945 | /* Can't determine prologue from the symbol table, need to examine | |
946 | instructions. */ | |
947 | ||
948 | /* Find an upper limit on the function prologue using the debug | |
949 | information. If the debug information could not be used to | |
950 | provide that bound, then use an arbitrary large number as the | |
951 | upper bound. */ | |
952 | limit_pc = skip_prologue_using_sal (gdbarch, pc); | |
953 | if (limit_pc == 0) | |
954 | limit_pc = pc + 128; /* Magic. */ | |
955 | ||
956 | /* Try disassembling prologue. */ | |
957 | return aarch64_analyze_prologue (gdbarch, pc, limit_pc, NULL); | |
958 | } | |
959 | ||
960 | /* Scan the function prologue for THIS_FRAME and populate the prologue | |
961 | cache CACHE. */ | |
962 | ||
963 | static void | |
964 | aarch64_scan_prologue (struct frame_info *this_frame, | |
965 | struct aarch64_prologue_cache *cache) | |
966 | { | |
967 | CORE_ADDR block_addr = get_frame_address_in_block (this_frame); | |
968 | CORE_ADDR prologue_start; | |
969 | CORE_ADDR prologue_end; | |
970 | CORE_ADDR prev_pc = get_frame_pc (this_frame); | |
971 | struct gdbarch *gdbarch = get_frame_arch (this_frame); | |
972 | ||
db634143 PL |
973 | cache->prev_pc = prev_pc; |
974 | ||
07b287a0 MS |
975 | /* Assume we do not find a frame. */ |
976 | cache->framereg = -1; | |
977 | cache->framesize = 0; | |
978 | ||
979 | if (find_pc_partial_function (block_addr, NULL, &prologue_start, | |
980 | &prologue_end)) | |
981 | { | |
982 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
983 | ||
984 | if (sal.line == 0) | |
985 | { | |
986 | /* No line info so use the current PC. */ | |
987 | prologue_end = prev_pc; | |
988 | } | |
989 | else if (sal.end < prologue_end) | |
990 | { | |
991 | /* The next line begins after the function end. */ | |
992 | prologue_end = sal.end; | |
993 | } | |
994 | ||
325fac50 | 995 | prologue_end = std::min (prologue_end, prev_pc); |
07b287a0 MS |
996 | aarch64_analyze_prologue (gdbarch, prologue_start, prologue_end, cache); |
997 | } | |
998 | else | |
999 | { | |
1000 | CORE_ADDR frame_loc; | |
07b287a0 MS |
1001 | |
1002 | frame_loc = get_frame_register_unsigned (this_frame, AARCH64_FP_REGNUM); | |
1003 | if (frame_loc == 0) | |
1004 | return; | |
1005 | ||
1006 | cache->framereg = AARCH64_FP_REGNUM; | |
1007 | cache->framesize = 16; | |
098caef4 LM |
1008 | cache->saved_regs[29].set_addr (0); |
1009 | cache->saved_regs[30].set_addr (8); | |
07b287a0 MS |
1010 | } |
1011 | } | |
1012 | ||
7dfa3edc PL |
1013 | /* Fill in *CACHE with information about the prologue of *THIS_FRAME. This |
1014 | function may throw an exception if the inferior's registers or memory is | |
1015 | not available. */ | |
07b287a0 | 1016 | |
7dfa3edc PL |
1017 | static void |
1018 | aarch64_make_prologue_cache_1 (struct frame_info *this_frame, | |
1019 | struct aarch64_prologue_cache *cache) | |
07b287a0 | 1020 | { |
07b287a0 MS |
1021 | CORE_ADDR unwound_fp; |
1022 | int reg; | |
1023 | ||
07b287a0 MS |
1024 | aarch64_scan_prologue (this_frame, cache); |
1025 | ||
1026 | if (cache->framereg == -1) | |
7dfa3edc | 1027 | return; |
07b287a0 MS |
1028 | |
1029 | unwound_fp = get_frame_register_unsigned (this_frame, cache->framereg); | |
1030 | if (unwound_fp == 0) | |
7dfa3edc | 1031 | return; |
07b287a0 MS |
1032 | |
1033 | cache->prev_sp = unwound_fp + cache->framesize; | |
1034 | ||
1035 | /* Calculate actual addresses of saved registers using offsets | |
1036 | determined by aarch64_analyze_prologue. */ | |
1037 | for (reg = 0; reg < gdbarch_num_regs (get_frame_arch (this_frame)); reg++) | |
a9a87d35 | 1038 | if (cache->saved_regs[reg].is_addr ()) |
098caef4 LM |
1039 | cache->saved_regs[reg].set_addr (cache->saved_regs[reg].addr () |
1040 | + cache->prev_sp); | |
07b287a0 | 1041 | |
db634143 PL |
1042 | cache->func = get_frame_func (this_frame); |
1043 | ||
7dfa3edc PL |
1044 | cache->available_p = 1; |
1045 | } | |
1046 | ||
1047 | /* Allocate and fill in *THIS_CACHE with information about the prologue of | |
1048 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
1049 | Return a pointer to the current aarch64_prologue_cache in | |
1050 | *THIS_CACHE. */ | |
1051 | ||
1052 | static struct aarch64_prologue_cache * | |
1053 | aarch64_make_prologue_cache (struct frame_info *this_frame, void **this_cache) | |
1054 | { | |
1055 | struct aarch64_prologue_cache *cache; | |
1056 | ||
1057 | if (*this_cache != NULL) | |
9a3c8263 | 1058 | return (struct aarch64_prologue_cache *) *this_cache; |
7dfa3edc PL |
1059 | |
1060 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
1061 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
1062 | *this_cache = cache; | |
1063 | ||
a70b8144 | 1064 | try |
7dfa3edc PL |
1065 | { |
1066 | aarch64_make_prologue_cache_1 (this_frame, cache); | |
1067 | } | |
230d2906 | 1068 | catch (const gdb_exception_error &ex) |
7dfa3edc PL |
1069 | { |
1070 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 1071 | throw; |
7dfa3edc | 1072 | } |
7dfa3edc | 1073 | |
07b287a0 MS |
1074 | return cache; |
1075 | } | |
1076 | ||
7dfa3edc PL |
1077 | /* Implement the "stop_reason" frame_unwind method. */ |
1078 | ||
1079 | static enum unwind_stop_reason | |
1080 | aarch64_prologue_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1081 | void **this_cache) | |
1082 | { | |
1083 | struct aarch64_prologue_cache *cache | |
1084 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
1085 | ||
1086 | if (!cache->available_p) | |
1087 | return UNWIND_UNAVAILABLE; | |
1088 | ||
1089 | /* Halt the backtrace at "_start". */ | |
345bd07c | 1090 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 1091 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (arch); |
345bd07c | 1092 | if (cache->prev_pc <= tdep->lowest_pc) |
7dfa3edc PL |
1093 | return UNWIND_OUTERMOST; |
1094 | ||
1095 | /* We've hit a wall, stop. */ | |
1096 | if (cache->prev_sp == 0) | |
1097 | return UNWIND_OUTERMOST; | |
1098 | ||
1099 | return UNWIND_NO_REASON; | |
1100 | } | |
1101 | ||
07b287a0 MS |
1102 | /* Our frame ID for a normal frame is the current function's starting |
1103 | PC and the caller's SP when we were called. */ | |
1104 | ||
1105 | static void | |
1106 | aarch64_prologue_this_id (struct frame_info *this_frame, | |
1107 | void **this_cache, struct frame_id *this_id) | |
1108 | { | |
7c8edfae PL |
1109 | struct aarch64_prologue_cache *cache |
1110 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 | 1111 | |
7dfa3edc PL |
1112 | if (!cache->available_p) |
1113 | *this_id = frame_id_build_unavailable_stack (cache->func); | |
1114 | else | |
1115 | *this_id = frame_id_build (cache->prev_sp, cache->func); | |
07b287a0 MS |
1116 | } |
1117 | ||
1118 | /* Implement the "prev_register" frame_unwind method. */ | |
1119 | ||
1120 | static struct value * | |
1121 | aarch64_prologue_prev_register (struct frame_info *this_frame, | |
1122 | void **this_cache, int prev_regnum) | |
1123 | { | |
7c8edfae PL |
1124 | struct aarch64_prologue_cache *cache |
1125 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
1126 | |
1127 | /* If we are asked to unwind the PC, then we need to return the LR | |
1128 | instead. The prologue may save PC, but it will point into this | |
1129 | frame's prologue, not the next frame's resume location. */ | |
1130 | if (prev_regnum == AARCH64_PC_REGNUM) | |
1131 | { | |
1132 | CORE_ADDR lr; | |
17e116a7 | 1133 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
345bd07c | 1134 | aarch64_gdbarch_tdep *tdep |
08106042 | 1135 | = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
1136 | |
1137 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
17e116a7 AH |
1138 | |
1139 | if (tdep->has_pauth () | |
c9cd8ca4 | 1140 | && cache->saved_regs[tdep->ra_sign_state_regnum].is_value ()) |
3d31bc39 | 1141 | lr = aarch64_frame_unmask_lr (tdep, this_frame, lr); |
17e116a7 | 1142 | |
07b287a0 MS |
1143 | return frame_unwind_got_constant (this_frame, prev_regnum, lr); |
1144 | } | |
1145 | ||
1146 | /* SP is generally not saved to the stack, but this frame is | |
1147 | identified by the next frame's stack pointer at the time of the | |
1148 | call. The value was already reconstructed into PREV_SP. */ | |
1149 | /* | |
dda83cd7 SM |
1150 | +----------+ ^ |
1151 | | saved lr | | | |
07b287a0 MS |
1152 | +->| saved fp |--+ |
1153 | | | | | |
1154 | | | | <- Previous SP | |
1155 | | +----------+ | |
1156 | | | saved lr | | |
1157 | +--| saved fp |<- FP | |
dda83cd7 SM |
1158 | | | |
1159 | | |<- SP | |
1160 | +----------+ */ | |
07b287a0 MS |
1161 | if (prev_regnum == AARCH64_SP_REGNUM) |
1162 | return frame_unwind_got_constant (this_frame, prev_regnum, | |
1163 | cache->prev_sp); | |
1164 | ||
1165 | return trad_frame_get_prev_register (this_frame, cache->saved_regs, | |
1166 | prev_regnum); | |
1167 | } | |
1168 | ||
1169 | /* AArch64 prologue unwinder. */ | |
6bd434d6 | 1170 | static frame_unwind aarch64_prologue_unwind = |
07b287a0 | 1171 | { |
a154d838 | 1172 | "aarch64 prologue", |
07b287a0 | 1173 | NORMAL_FRAME, |
7dfa3edc | 1174 | aarch64_prologue_frame_unwind_stop_reason, |
07b287a0 MS |
1175 | aarch64_prologue_this_id, |
1176 | aarch64_prologue_prev_register, | |
1177 | NULL, | |
1178 | default_frame_sniffer | |
1179 | }; | |
1180 | ||
8b61f75d PL |
1181 | /* Allocate and fill in *THIS_CACHE with information about the prologue of |
1182 | *THIS_FRAME. Do not do this is if *THIS_CACHE was already allocated. | |
1183 | Return a pointer to the current aarch64_prologue_cache in | |
1184 | *THIS_CACHE. */ | |
07b287a0 MS |
1185 | |
1186 | static struct aarch64_prologue_cache * | |
8b61f75d | 1187 | aarch64_make_stub_cache (struct frame_info *this_frame, void **this_cache) |
07b287a0 | 1188 | { |
07b287a0 | 1189 | struct aarch64_prologue_cache *cache; |
8b61f75d PL |
1190 | |
1191 | if (*this_cache != NULL) | |
9a3c8263 | 1192 | return (struct aarch64_prologue_cache *) *this_cache; |
07b287a0 MS |
1193 | |
1194 | cache = FRAME_OBSTACK_ZALLOC (struct aarch64_prologue_cache); | |
1195 | cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
8b61f75d | 1196 | *this_cache = cache; |
07b287a0 | 1197 | |
a70b8144 | 1198 | try |
02a2a705 PL |
1199 | { |
1200 | cache->prev_sp = get_frame_register_unsigned (this_frame, | |
1201 | AARCH64_SP_REGNUM); | |
1202 | cache->prev_pc = get_frame_pc (this_frame); | |
1203 | cache->available_p = 1; | |
1204 | } | |
230d2906 | 1205 | catch (const gdb_exception_error &ex) |
02a2a705 PL |
1206 | { |
1207 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 1208 | throw; |
02a2a705 | 1209 | } |
07b287a0 MS |
1210 | |
1211 | return cache; | |
1212 | } | |
1213 | ||
02a2a705 PL |
1214 | /* Implement the "stop_reason" frame_unwind method. */ |
1215 | ||
1216 | static enum unwind_stop_reason | |
1217 | aarch64_stub_frame_unwind_stop_reason (struct frame_info *this_frame, | |
1218 | void **this_cache) | |
1219 | { | |
1220 | struct aarch64_prologue_cache *cache | |
1221 | = aarch64_make_stub_cache (this_frame, this_cache); | |
1222 | ||
1223 | if (!cache->available_p) | |
1224 | return UNWIND_UNAVAILABLE; | |
1225 | ||
1226 | return UNWIND_NO_REASON; | |
1227 | } | |
1228 | ||
07b287a0 MS |
1229 | /* Our frame ID for a stub frame is the current SP and LR. */ |
1230 | ||
1231 | static void | |
1232 | aarch64_stub_this_id (struct frame_info *this_frame, | |
1233 | void **this_cache, struct frame_id *this_id) | |
1234 | { | |
8b61f75d PL |
1235 | struct aarch64_prologue_cache *cache |
1236 | = aarch64_make_stub_cache (this_frame, this_cache); | |
07b287a0 | 1237 | |
02a2a705 PL |
1238 | if (cache->available_p) |
1239 | *this_id = frame_id_build (cache->prev_sp, cache->prev_pc); | |
1240 | else | |
1241 | *this_id = frame_id_build_unavailable_stack (cache->prev_pc); | |
07b287a0 MS |
1242 | } |
1243 | ||
1244 | /* Implement the "sniffer" frame_unwind method. */ | |
1245 | ||
1246 | static int | |
1247 | aarch64_stub_unwind_sniffer (const struct frame_unwind *self, | |
1248 | struct frame_info *this_frame, | |
1249 | void **this_prologue_cache) | |
1250 | { | |
1251 | CORE_ADDR addr_in_block; | |
1252 | gdb_byte dummy[4]; | |
1253 | ||
1254 | addr_in_block = get_frame_address_in_block (this_frame); | |
3e5d3a5a | 1255 | if (in_plt_section (addr_in_block) |
07b287a0 MS |
1256 | /* We also use the stub winder if the target memory is unreadable |
1257 | to avoid having the prologue unwinder trying to read it. */ | |
1258 | || target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) | |
1259 | return 1; | |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | /* AArch64 stub unwinder. */ | |
6bd434d6 | 1265 | static frame_unwind aarch64_stub_unwind = |
07b287a0 | 1266 | { |
a154d838 | 1267 | "aarch64 stub", |
07b287a0 | 1268 | NORMAL_FRAME, |
02a2a705 | 1269 | aarch64_stub_frame_unwind_stop_reason, |
07b287a0 MS |
1270 | aarch64_stub_this_id, |
1271 | aarch64_prologue_prev_register, | |
1272 | NULL, | |
1273 | aarch64_stub_unwind_sniffer | |
1274 | }; | |
1275 | ||
1276 | /* Return the frame base address of *THIS_FRAME. */ | |
1277 | ||
1278 | static CORE_ADDR | |
1279 | aarch64_normal_frame_base (struct frame_info *this_frame, void **this_cache) | |
1280 | { | |
7c8edfae PL |
1281 | struct aarch64_prologue_cache *cache |
1282 | = aarch64_make_prologue_cache (this_frame, this_cache); | |
07b287a0 MS |
1283 | |
1284 | return cache->prev_sp - cache->framesize; | |
1285 | } | |
1286 | ||
1287 | /* AArch64 default frame base information. */ | |
6bd434d6 | 1288 | static frame_base aarch64_normal_base = |
07b287a0 MS |
1289 | { |
1290 | &aarch64_prologue_unwind, | |
1291 | aarch64_normal_frame_base, | |
1292 | aarch64_normal_frame_base, | |
1293 | aarch64_normal_frame_base | |
1294 | }; | |
1295 | ||
07b287a0 MS |
1296 | /* Return the value of the REGNUM register in the previous frame of |
1297 | *THIS_FRAME. */ | |
1298 | ||
1299 | static struct value * | |
1300 | aarch64_dwarf2_prev_register (struct frame_info *this_frame, | |
1301 | void **this_cache, int regnum) | |
1302 | { | |
345bd07c | 1303 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 1304 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (arch); |
07b287a0 MS |
1305 | CORE_ADDR lr; |
1306 | ||
1307 | switch (regnum) | |
1308 | { | |
1309 | case AARCH64_PC_REGNUM: | |
1310 | lr = frame_unwind_register_unsigned (this_frame, AARCH64_LR_REGNUM); | |
3d31bc39 | 1311 | lr = aarch64_frame_unmask_lr (tdep, this_frame, lr); |
07b287a0 MS |
1312 | return frame_unwind_got_constant (this_frame, regnum, lr); |
1313 | ||
1314 | default: | |
1315 | internal_error (__FILE__, __LINE__, | |
1316 | _("Unexpected register %d"), regnum); | |
1317 | } | |
1318 | } | |
1319 | ||
11e1b75f AH |
1320 | static const unsigned char op_lit0 = DW_OP_lit0; |
1321 | static const unsigned char op_lit1 = DW_OP_lit1; | |
1322 | ||
07b287a0 MS |
1323 | /* Implement the "init_reg" dwarf2_frame_ops method. */ |
1324 | ||
1325 | static void | |
1326 | aarch64_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
1327 | struct dwarf2_frame_state_reg *reg, | |
1328 | struct frame_info *this_frame) | |
1329 | { | |
08106042 | 1330 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
11e1b75f | 1331 | |
07b287a0 MS |
1332 | switch (regnum) |
1333 | { | |
1334 | case AARCH64_PC_REGNUM: | |
1335 | reg->how = DWARF2_FRAME_REG_FN; | |
1336 | reg->loc.fn = aarch64_dwarf2_prev_register; | |
11e1b75f AH |
1337 | return; |
1338 | ||
07b287a0 MS |
1339 | case AARCH64_SP_REGNUM: |
1340 | reg->how = DWARF2_FRAME_REG_CFA; | |
11e1b75f AH |
1341 | return; |
1342 | } | |
1343 | ||
1344 | /* Init pauth registers. */ | |
1345 | if (tdep->has_pauth ()) | |
1346 | { | |
c9cd8ca4 | 1347 | if (regnum == tdep->ra_sign_state_regnum) |
11e1b75f AH |
1348 | { |
1349 | /* Initialize RA_STATE to zero. */ | |
1350 | reg->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; | |
1351 | reg->loc.exp.start = &op_lit0; | |
1352 | reg->loc.exp.len = 1; | |
1353 | return; | |
1354 | } | |
1355 | else if (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) | |
1356 | || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)) | |
1357 | { | |
1358 | reg->how = DWARF2_FRAME_REG_SAME_VALUE; | |
1359 | return; | |
1360 | } | |
07b287a0 MS |
1361 | } |
1362 | } | |
1363 | ||
11e1b75f AH |
1364 | /* Implement the execute_dwarf_cfa_vendor_op method. */ |
1365 | ||
1366 | static bool | |
1367 | aarch64_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, | |
1368 | struct dwarf2_frame_state *fs) | |
1369 | { | |
08106042 | 1370 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
11e1b75f AH |
1371 | struct dwarf2_frame_state_reg *ra_state; |
1372 | ||
8fca4da0 | 1373 | if (op == DW_CFA_AARCH64_negate_ra_state) |
11e1b75f | 1374 | { |
8fca4da0 AH |
1375 | /* On systems without pauth, treat as a nop. */ |
1376 | if (!tdep->has_pauth ()) | |
1377 | return true; | |
1378 | ||
11e1b75f | 1379 | /* Allocate RA_STATE column if it's not allocated yet. */ |
c9cd8ca4 | 1380 | fs->regs.alloc_regs (AARCH64_DWARF_RA_SIGN_STATE + 1); |
11e1b75f AH |
1381 | |
1382 | /* Toggle the status of RA_STATE between 0 and 1. */ | |
c9cd8ca4 | 1383 | ra_state = &(fs->regs.reg[AARCH64_DWARF_RA_SIGN_STATE]); |
11e1b75f AH |
1384 | ra_state->how = DWARF2_FRAME_REG_SAVED_VAL_EXP; |
1385 | ||
1386 | if (ra_state->loc.exp.start == nullptr | |
1387 | || ra_state->loc.exp.start == &op_lit0) | |
1388 | ra_state->loc.exp.start = &op_lit1; | |
1389 | else | |
1390 | ra_state->loc.exp.start = &op_lit0; | |
1391 | ||
1392 | ra_state->loc.exp.len = 1; | |
1393 | ||
1394 | return true; | |
1395 | } | |
1396 | ||
1397 | return false; | |
1398 | } | |
1399 | ||
5133a315 LM |
1400 | /* Used for matching BRK instructions for AArch64. */ |
1401 | static constexpr uint32_t BRK_INSN_MASK = 0xffe0001f; | |
1402 | static constexpr uint32_t BRK_INSN_BASE = 0xd4200000; | |
1403 | ||
1404 | /* Implementation of gdbarch_program_breakpoint_here_p for aarch64. */ | |
1405 | ||
1406 | static bool | |
1407 | aarch64_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address) | |
1408 | { | |
1409 | const uint32_t insn_len = 4; | |
1410 | gdb_byte target_mem[4]; | |
1411 | ||
1412 | /* Enable the automatic memory restoration from breakpoints while | |
1413 | we read the memory. Otherwise we may find temporary breakpoints, ones | |
1414 | inserted by GDB, and flag them as permanent breakpoints. */ | |
1415 | scoped_restore restore_memory | |
1416 | = make_scoped_restore_show_memory_breakpoints (0); | |
1417 | ||
1418 | if (target_read_memory (address, target_mem, insn_len) == 0) | |
1419 | { | |
1420 | uint32_t insn = | |
1421 | (uint32_t) extract_unsigned_integer (target_mem, insn_len, | |
1422 | gdbarch_byte_order_for_code (gdbarch)); | |
1423 | ||
1424 | /* Check if INSN is a BRK instruction pattern. There are multiple choices | |
1425 | of such instructions with different immediate values. Different OS' | |
1426 | may use a different variation, but they have the same outcome. */ | |
1427 | return ((insn & BRK_INSN_MASK) == BRK_INSN_BASE); | |
1428 | } | |
1429 | ||
1430 | return false; | |
1431 | } | |
1432 | ||
07b287a0 MS |
1433 | /* When arguments must be pushed onto the stack, they go on in reverse |
1434 | order. The code below implements a FILO (stack) to do this. */ | |
1435 | ||
89055eaa | 1436 | struct stack_item_t |
07b287a0 | 1437 | { |
c3c87445 YQ |
1438 | /* Value to pass on stack. It can be NULL if this item is for stack |
1439 | padding. */ | |
7c543f7b | 1440 | const gdb_byte *data; |
07b287a0 MS |
1441 | |
1442 | /* Size in bytes of value to pass on stack. */ | |
1443 | int len; | |
89055eaa | 1444 | }; |
07b287a0 | 1445 | |
b907456c AB |
1446 | /* Implement the gdbarch type alignment method, overrides the generic |
1447 | alignment algorithm for anything that is aarch64 specific. */ | |
07b287a0 | 1448 | |
b907456c AB |
1449 | static ULONGEST |
1450 | aarch64_type_align (gdbarch *gdbarch, struct type *t) | |
07b287a0 | 1451 | { |
07b287a0 | 1452 | t = check_typedef (t); |
bd63c870 | 1453 | if (t->code () == TYPE_CODE_ARRAY && t->is_vector ()) |
07b287a0 | 1454 | { |
b907456c AB |
1455 | /* Use the natural alignment for vector types (the same for |
1456 | scalar type), but the maximum alignment is 128-bit. */ | |
1457 | if (TYPE_LENGTH (t) > 16) | |
1458 | return 16; | |
238f2452 | 1459 | else |
b907456c | 1460 | return TYPE_LENGTH (t); |
07b287a0 | 1461 | } |
b907456c AB |
1462 | |
1463 | /* Allow the common code to calculate the alignment. */ | |
1464 | return 0; | |
07b287a0 MS |
1465 | } |
1466 | ||
ea92689a AH |
1467 | /* Worker function for aapcs_is_vfp_call_or_return_candidate. |
1468 | ||
1469 | Return the number of register required, or -1 on failure. | |
1470 | ||
1471 | When encountering a base element, if FUNDAMENTAL_TYPE is not set then set it | |
1472 | to the element, else fail if the type of this element does not match the | |
1473 | existing value. */ | |
1474 | ||
1475 | static int | |
1476 | aapcs_is_vfp_call_or_return_candidate_1 (struct type *type, | |
1477 | struct type **fundamental_type) | |
1478 | { | |
1479 | if (type == nullptr) | |
1480 | return -1; | |
1481 | ||
78134374 | 1482 | switch (type->code ()) |
ea92689a AH |
1483 | { |
1484 | case TYPE_CODE_FLT: | |
81657e58 | 1485 | case TYPE_CODE_DECFLOAT: |
ea92689a AH |
1486 | if (TYPE_LENGTH (type) > 16) |
1487 | return -1; | |
1488 | ||
1489 | if (*fundamental_type == nullptr) | |
1490 | *fundamental_type = type; | |
1491 | else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type) | |
78134374 | 1492 | || type->code () != (*fundamental_type)->code ()) |
ea92689a AH |
1493 | return -1; |
1494 | ||
1495 | return 1; | |
1496 | ||
1497 | case TYPE_CODE_COMPLEX: | |
1498 | { | |
1499 | struct type *target_type = check_typedef (TYPE_TARGET_TYPE (type)); | |
1500 | if (TYPE_LENGTH (target_type) > 16) | |
1501 | return -1; | |
1502 | ||
1503 | if (*fundamental_type == nullptr) | |
1504 | *fundamental_type = target_type; | |
1505 | else if (TYPE_LENGTH (target_type) != TYPE_LENGTH (*fundamental_type) | |
78134374 | 1506 | || target_type->code () != (*fundamental_type)->code ()) |
ea92689a AH |
1507 | return -1; |
1508 | ||
1509 | return 2; | |
1510 | } | |
1511 | ||
1512 | case TYPE_CODE_ARRAY: | |
1513 | { | |
bd63c870 | 1514 | if (type->is_vector ()) |
ea92689a AH |
1515 | { |
1516 | if (TYPE_LENGTH (type) != 8 && TYPE_LENGTH (type) != 16) | |
1517 | return -1; | |
1518 | ||
1519 | if (*fundamental_type == nullptr) | |
1520 | *fundamental_type = type; | |
1521 | else if (TYPE_LENGTH (type) != TYPE_LENGTH (*fundamental_type) | |
78134374 | 1522 | || type->code () != (*fundamental_type)->code ()) |
ea92689a AH |
1523 | return -1; |
1524 | ||
1525 | return 1; | |
1526 | } | |
1527 | else | |
1528 | { | |
1529 | struct type *target_type = TYPE_TARGET_TYPE (type); | |
1530 | int count = aapcs_is_vfp_call_or_return_candidate_1 | |
1531 | (target_type, fundamental_type); | |
1532 | ||
1533 | if (count == -1) | |
1534 | return count; | |
1535 | ||
d4718d5c | 1536 | count *= (TYPE_LENGTH (type) / TYPE_LENGTH (target_type)); |
ea92689a AH |
1537 | return count; |
1538 | } | |
1539 | } | |
1540 | ||
1541 | case TYPE_CODE_STRUCT: | |
1542 | case TYPE_CODE_UNION: | |
1543 | { | |
1544 | int count = 0; | |
1545 | ||
1f704f76 | 1546 | for (int i = 0; i < type->num_fields (); i++) |
ea92689a | 1547 | { |
353229bf | 1548 | /* Ignore any static fields. */ |
ceacbf6e | 1549 | if (field_is_static (&type->field (i))) |
353229bf AH |
1550 | continue; |
1551 | ||
940da03e | 1552 | struct type *member = check_typedef (type->field (i).type ()); |
ea92689a AH |
1553 | |
1554 | int sub_count = aapcs_is_vfp_call_or_return_candidate_1 | |
1555 | (member, fundamental_type); | |
1556 | if (sub_count == -1) | |
1557 | return -1; | |
1558 | count += sub_count; | |
1559 | } | |
73021deb AH |
1560 | |
1561 | /* Ensure there is no padding between the fields (allowing for empty | |
1562 | zero length structs) */ | |
1563 | int ftype_length = (*fundamental_type == nullptr) | |
1564 | ? 0 : TYPE_LENGTH (*fundamental_type); | |
1565 | if (count * ftype_length != TYPE_LENGTH (type)) | |
1566 | return -1; | |
1567 | ||
ea92689a AH |
1568 | return count; |
1569 | } | |
1570 | ||
1571 | default: | |
1572 | break; | |
1573 | } | |
1574 | ||
1575 | return -1; | |
1576 | } | |
1577 | ||
1578 | /* Return true if an argument, whose type is described by TYPE, can be passed or | |
1579 | returned in simd/fp registers, providing enough parameter passing registers | |
1580 | are available. This is as described in the AAPCS64. | |
1581 | ||
1582 | Upon successful return, *COUNT returns the number of needed registers, | |
1583 | *FUNDAMENTAL_TYPE contains the type of those registers. | |
1584 | ||
1585 | Candidate as per the AAPCS64 5.4.2.C is either a: | |
1586 | - float. | |
1587 | - short-vector. | |
1588 | - HFA (Homogeneous Floating-point Aggregate, 4.3.5.1). A Composite type where | |
1589 | all the members are floats and has at most 4 members. | |
1590 | - HVA (Homogeneous Short-vector Aggregate, 4.3.5.2). A Composite type where | |
1591 | all the members are short vectors and has at most 4 members. | |
1592 | - Complex (7.1.1) | |
1593 | ||
1594 | Note that HFAs and HVAs can include nested structures and arrays. */ | |
1595 | ||
0e745c60 | 1596 | static bool |
ea92689a AH |
1597 | aapcs_is_vfp_call_or_return_candidate (struct type *type, int *count, |
1598 | struct type **fundamental_type) | |
1599 | { | |
1600 | if (type == nullptr) | |
1601 | return false; | |
1602 | ||
1603 | *fundamental_type = nullptr; | |
1604 | ||
1605 | int ag_count = aapcs_is_vfp_call_or_return_candidate_1 (type, | |
1606 | fundamental_type); | |
1607 | ||
1608 | if (ag_count > 0 && ag_count <= HA_MAX_NUM_FLDS) | |
1609 | { | |
1610 | *count = ag_count; | |
1611 | return true; | |
1612 | } | |
1613 | else | |
1614 | return false; | |
1615 | } | |
1616 | ||
07b287a0 MS |
1617 | /* AArch64 function call information structure. */ |
1618 | struct aarch64_call_info | |
1619 | { | |
1620 | /* the current argument number. */ | |
89055eaa | 1621 | unsigned argnum = 0; |
07b287a0 MS |
1622 | |
1623 | /* The next general purpose register number, equivalent to NGRN as | |
1624 | described in the AArch64 Procedure Call Standard. */ | |
89055eaa | 1625 | unsigned ngrn = 0; |
07b287a0 MS |
1626 | |
1627 | /* The next SIMD and floating point register number, equivalent to | |
1628 | NSRN as described in the AArch64 Procedure Call Standard. */ | |
89055eaa | 1629 | unsigned nsrn = 0; |
07b287a0 MS |
1630 | |
1631 | /* The next stacked argument address, equivalent to NSAA as | |
1632 | described in the AArch64 Procedure Call Standard. */ | |
89055eaa | 1633 | unsigned nsaa = 0; |
07b287a0 MS |
1634 | |
1635 | /* Stack item vector. */ | |
89055eaa | 1636 | std::vector<stack_item_t> si; |
07b287a0 MS |
1637 | }; |
1638 | ||
1639 | /* Pass a value in a sequence of consecutive X registers. The caller | |
30baf67b | 1640 | is responsible for ensuring sufficient registers are available. */ |
07b287a0 MS |
1641 | |
1642 | static void | |
1643 | pass_in_x (struct gdbarch *gdbarch, struct regcache *regcache, | |
1644 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1645 | struct value *arg) |
07b287a0 MS |
1646 | { |
1647 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
1648 | int len = TYPE_LENGTH (type); | |
78134374 | 1649 | enum type_code typecode = type->code (); |
07b287a0 | 1650 | int regnum = AARCH64_X0_REGNUM + info->ngrn; |
50888e42 | 1651 | const bfd_byte *buf = value_contents (arg).data (); |
07b287a0 MS |
1652 | |
1653 | info->argnum++; | |
1654 | ||
1655 | while (len > 0) | |
1656 | { | |
1657 | int partial_len = len < X_REGISTER_SIZE ? len : X_REGISTER_SIZE; | |
1658 | CORE_ADDR regval = extract_unsigned_integer (buf, partial_len, | |
1659 | byte_order); | |
1660 | ||
1661 | ||
1662 | /* Adjust sub-word struct/union args when big-endian. */ | |
1663 | if (byte_order == BFD_ENDIAN_BIG | |
1664 | && partial_len < X_REGISTER_SIZE | |
1665 | && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) | |
1666 | regval <<= ((X_REGISTER_SIZE - partial_len) * TARGET_CHAR_BIT); | |
1667 | ||
c6185dce SM |
1668 | aarch64_debug_printf ("arg %d in %s = 0x%s", info->argnum, |
1669 | gdbarch_register_name (gdbarch, regnum), | |
1670 | phex (regval, X_REGISTER_SIZE)); | |
1671 | ||
07b287a0 MS |
1672 | regcache_cooked_write_unsigned (regcache, regnum, regval); |
1673 | len -= partial_len; | |
1674 | buf += partial_len; | |
1675 | regnum++; | |
1676 | } | |
1677 | } | |
1678 | ||
1679 | /* Attempt to marshall a value in a V register. Return 1 if | |
1680 | successful, or 0 if insufficient registers are available. This | |
1681 | function, unlike the equivalent pass_in_x() function does not | |
1682 | handle arguments spread across multiple registers. */ | |
1683 | ||
1684 | static int | |
1685 | pass_in_v (struct gdbarch *gdbarch, | |
1686 | struct regcache *regcache, | |
1687 | struct aarch64_call_info *info, | |
0735fddd | 1688 | int len, const bfd_byte *buf) |
07b287a0 MS |
1689 | { |
1690 | if (info->nsrn < 8) | |
1691 | { | |
07b287a0 | 1692 | int regnum = AARCH64_V0_REGNUM + info->nsrn; |
3ff2c72e AH |
1693 | /* Enough space for a full vector register. */ |
1694 | gdb_byte reg[register_size (gdbarch, regnum)]; | |
1695 | gdb_assert (len <= sizeof (reg)); | |
07b287a0 MS |
1696 | |
1697 | info->argnum++; | |
1698 | info->nsrn++; | |
1699 | ||
0735fddd YQ |
1700 | memset (reg, 0, sizeof (reg)); |
1701 | /* PCS C.1, the argument is allocated to the least significant | |
1702 | bits of V register. */ | |
1703 | memcpy (reg, buf, len); | |
b66f5587 | 1704 | regcache->cooked_write (regnum, reg); |
0735fddd | 1705 | |
c6185dce SM |
1706 | aarch64_debug_printf ("arg %d in %s", info->argnum, |
1707 | gdbarch_register_name (gdbarch, regnum)); | |
1708 | ||
07b287a0 MS |
1709 | return 1; |
1710 | } | |
1711 | info->nsrn = 8; | |
1712 | return 0; | |
1713 | } | |
1714 | ||
1715 | /* Marshall an argument onto the stack. */ | |
1716 | ||
1717 | static void | |
1718 | pass_on_stack (struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1719 | struct value *arg) |
07b287a0 | 1720 | { |
50888e42 | 1721 | const bfd_byte *buf = value_contents (arg).data (); |
07b287a0 MS |
1722 | int len = TYPE_LENGTH (type); |
1723 | int align; | |
1724 | stack_item_t item; | |
1725 | ||
1726 | info->argnum++; | |
1727 | ||
b907456c | 1728 | align = type_align (type); |
07b287a0 MS |
1729 | |
1730 | /* PCS C.17 Stack should be aligned to the larger of 8 bytes or the | |
1731 | Natural alignment of the argument's type. */ | |
1732 | align = align_up (align, 8); | |
1733 | ||
1734 | /* The AArch64 PCS requires at most doubleword alignment. */ | |
1735 | if (align > 16) | |
1736 | align = 16; | |
1737 | ||
c6185dce SM |
1738 | aarch64_debug_printf ("arg %d len=%d @ sp + %d\n", info->argnum, len, |
1739 | info->nsaa); | |
07b287a0 MS |
1740 | |
1741 | item.len = len; | |
1742 | item.data = buf; | |
89055eaa | 1743 | info->si.push_back (item); |
07b287a0 MS |
1744 | |
1745 | info->nsaa += len; | |
1746 | if (info->nsaa & (align - 1)) | |
1747 | { | |
1748 | /* Push stack alignment padding. */ | |
1749 | int pad = align - (info->nsaa & (align - 1)); | |
1750 | ||
1751 | item.len = pad; | |
c3c87445 | 1752 | item.data = NULL; |
07b287a0 | 1753 | |
89055eaa | 1754 | info->si.push_back (item); |
07b287a0 MS |
1755 | info->nsaa += pad; |
1756 | } | |
1757 | } | |
1758 | ||
1759 | /* Marshall an argument into a sequence of one or more consecutive X | |
1760 | registers or, if insufficient X registers are available then onto | |
1761 | the stack. */ | |
1762 | ||
1763 | static void | |
1764 | pass_in_x_or_stack (struct gdbarch *gdbarch, struct regcache *regcache, | |
1765 | struct aarch64_call_info *info, struct type *type, | |
8e80f9d1 | 1766 | struct value *arg) |
07b287a0 MS |
1767 | { |
1768 | int len = TYPE_LENGTH (type); | |
1769 | int nregs = (len + X_REGISTER_SIZE - 1) / X_REGISTER_SIZE; | |
1770 | ||
1771 | /* PCS C.13 - Pass in registers if we have enough spare */ | |
1772 | if (info->ngrn + nregs <= 8) | |
1773 | { | |
8e80f9d1 | 1774 | pass_in_x (gdbarch, regcache, info, type, arg); |
07b287a0 MS |
1775 | info->ngrn += nregs; |
1776 | } | |
1777 | else | |
1778 | { | |
1779 | info->ngrn = 8; | |
8e80f9d1 | 1780 | pass_on_stack (info, type, arg); |
07b287a0 MS |
1781 | } |
1782 | } | |
1783 | ||
0e745c60 AH |
1784 | /* Pass a value, which is of type arg_type, in a V register. Assumes value is a |
1785 | aapcs_is_vfp_call_or_return_candidate and there are enough spare V | |
1786 | registers. A return value of false is an error state as the value will have | |
1787 | been partially passed to the stack. */ | |
1788 | static bool | |
1789 | pass_in_v_vfp_candidate (struct gdbarch *gdbarch, struct regcache *regcache, | |
1790 | struct aarch64_call_info *info, struct type *arg_type, | |
1791 | struct value *arg) | |
07b287a0 | 1792 | { |
78134374 | 1793 | switch (arg_type->code ()) |
0e745c60 AH |
1794 | { |
1795 | case TYPE_CODE_FLT: | |
81657e58 | 1796 | case TYPE_CODE_DECFLOAT: |
0e745c60 | 1797 | return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type), |
50888e42 | 1798 | value_contents (arg).data ()); |
0e745c60 AH |
1799 | break; |
1800 | ||
1801 | case TYPE_CODE_COMPLEX: | |
1802 | { | |
50888e42 | 1803 | const bfd_byte *buf = value_contents (arg).data (); |
0e745c60 AH |
1804 | struct type *target_type = check_typedef (TYPE_TARGET_TYPE (arg_type)); |
1805 | ||
1806 | if (!pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type), | |
1807 | buf)) | |
1808 | return false; | |
1809 | ||
1810 | return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (target_type), | |
1811 | buf + TYPE_LENGTH (target_type)); | |
1812 | } | |
1813 | ||
1814 | case TYPE_CODE_ARRAY: | |
bd63c870 | 1815 | if (arg_type->is_vector ()) |
0e745c60 | 1816 | return pass_in_v (gdbarch, regcache, info, TYPE_LENGTH (arg_type), |
50888e42 | 1817 | value_contents (arg).data ()); |
0e745c60 AH |
1818 | /* fall through. */ |
1819 | ||
1820 | case TYPE_CODE_STRUCT: | |
1821 | case TYPE_CODE_UNION: | |
1f704f76 | 1822 | for (int i = 0; i < arg_type->num_fields (); i++) |
0e745c60 | 1823 | { |
353229bf | 1824 | /* Don't include static fields. */ |
ceacbf6e | 1825 | if (field_is_static (&arg_type->field (i))) |
353229bf AH |
1826 | continue; |
1827 | ||
0e745c60 AH |
1828 | struct value *field = value_primitive_field (arg, 0, i, arg_type); |
1829 | struct type *field_type = check_typedef (value_type (field)); | |
1830 | ||
1831 | if (!pass_in_v_vfp_candidate (gdbarch, regcache, info, field_type, | |
1832 | field)) | |
1833 | return false; | |
1834 | } | |
1835 | return true; | |
1836 | ||
1837 | default: | |
1838 | return false; | |
1839 | } | |
07b287a0 MS |
1840 | } |
1841 | ||
1842 | /* Implement the "push_dummy_call" gdbarch method. */ | |
1843 | ||
1844 | static CORE_ADDR | |
1845 | aarch64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
1846 | struct regcache *regcache, CORE_ADDR bp_addr, | |
1847 | int nargs, | |
cf84fa6b AH |
1848 | struct value **args, CORE_ADDR sp, |
1849 | function_call_return_method return_method, | |
07b287a0 MS |
1850 | CORE_ADDR struct_addr) |
1851 | { | |
07b287a0 | 1852 | int argnum; |
07b287a0 | 1853 | struct aarch64_call_info info; |
07b287a0 | 1854 | |
07b287a0 MS |
1855 | /* We need to know what the type of the called function is in order |
1856 | to determine the number of named/anonymous arguments for the | |
1857 | actual argument placement, and the return type in order to handle | |
1858 | return value correctly. | |
1859 | ||
1860 | The generic code above us views the decision of return in memory | |
1861 | or return in registers as a two stage processes. The language | |
1862 | handler is consulted first and may decide to return in memory (eg | |
1863 | class with copy constructor returned by value), this will cause | |
1864 | the generic code to allocate space AND insert an initial leading | |
1865 | argument. | |
1866 | ||
1867 | If the language code does not decide to pass in memory then the | |
1868 | target code is consulted. | |
1869 | ||
1870 | If the language code decides to pass in memory we want to move | |
1871 | the pointer inserted as the initial argument from the argument | |
1872 | list and into X8, the conventional AArch64 struct return pointer | |
38a72da0 | 1873 | register. */ |
07b287a0 MS |
1874 | |
1875 | /* Set the return address. For the AArch64, the return breakpoint | |
1876 | is always at BP_ADDR. */ | |
1877 | regcache_cooked_write_unsigned (regcache, AARCH64_LR_REGNUM, bp_addr); | |
1878 | ||
38a72da0 AH |
1879 | /* If we were given an initial argument for the return slot, lose it. */ |
1880 | if (return_method == return_method_hidden_param) | |
07b287a0 MS |
1881 | { |
1882 | args++; | |
1883 | nargs--; | |
1884 | } | |
1885 | ||
1886 | /* The struct_return pointer occupies X8. */ | |
38a72da0 | 1887 | if (return_method != return_method_normal) |
07b287a0 | 1888 | { |
c6185dce SM |
1889 | aarch64_debug_printf ("struct return in %s = 0x%s", |
1890 | gdbarch_register_name | |
1891 | (gdbarch, AARCH64_STRUCT_RETURN_REGNUM), | |
1892 | paddress (gdbarch, struct_addr)); | |
1893 | ||
07b287a0 MS |
1894 | regcache_cooked_write_unsigned (regcache, AARCH64_STRUCT_RETURN_REGNUM, |
1895 | struct_addr); | |
1896 | } | |
1897 | ||
1898 | for (argnum = 0; argnum < nargs; argnum++) | |
1899 | { | |
1900 | struct value *arg = args[argnum]; | |
0e745c60 AH |
1901 | struct type *arg_type, *fundamental_type; |
1902 | int len, elements; | |
07b287a0 MS |
1903 | |
1904 | arg_type = check_typedef (value_type (arg)); | |
1905 | len = TYPE_LENGTH (arg_type); | |
1906 | ||
0e745c60 AH |
1907 | /* If arg can be passed in v registers as per the AAPCS64, then do so if |
1908 | if there are enough spare registers. */ | |
1909 | if (aapcs_is_vfp_call_or_return_candidate (arg_type, &elements, | |
1910 | &fundamental_type)) | |
1911 | { | |
1912 | if (info.nsrn + elements <= 8) | |
1913 | { | |
1914 | /* We know that we have sufficient registers available therefore | |
1915 | this will never need to fallback to the stack. */ | |
1916 | if (!pass_in_v_vfp_candidate (gdbarch, regcache, &info, arg_type, | |
1917 | arg)) | |
1918 | gdb_assert_not_reached ("Failed to push args"); | |
1919 | } | |
1920 | else | |
1921 | { | |
1922 | info.nsrn = 8; | |
1923 | pass_on_stack (&info, arg_type, arg); | |
1924 | } | |
1925 | continue; | |
1926 | } | |
1927 | ||
78134374 | 1928 | switch (arg_type->code ()) |
07b287a0 MS |
1929 | { |
1930 | case TYPE_CODE_INT: | |
1931 | case TYPE_CODE_BOOL: | |
1932 | case TYPE_CODE_CHAR: | |
1933 | case TYPE_CODE_RANGE: | |
1934 | case TYPE_CODE_ENUM: | |
28397ae7 | 1935 | if (len < 4 && !is_fixed_point_type (arg_type)) |
07b287a0 MS |
1936 | { |
1937 | /* Promote to 32 bit integer. */ | |
c6d940a9 | 1938 | if (arg_type->is_unsigned ()) |
07b287a0 MS |
1939 | arg_type = builtin_type (gdbarch)->builtin_uint32; |
1940 | else | |
1941 | arg_type = builtin_type (gdbarch)->builtin_int32; | |
1942 | arg = value_cast (arg_type, arg); | |
1943 | } | |
8e80f9d1 | 1944 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1945 | break; |
1946 | ||
07b287a0 MS |
1947 | case TYPE_CODE_STRUCT: |
1948 | case TYPE_CODE_ARRAY: | |
1949 | case TYPE_CODE_UNION: | |
0e745c60 | 1950 | if (len > 16) |
07b287a0 MS |
1951 | { |
1952 | /* PCS B.7 Aggregates larger than 16 bytes are passed by | |
1953 | invisible reference. */ | |
1954 | ||
1955 | /* Allocate aligned storage. */ | |
1956 | sp = align_down (sp - len, 16); | |
1957 | ||
1958 | /* Write the real data into the stack. */ | |
50888e42 | 1959 | write_memory (sp, value_contents (arg).data (), len); |
07b287a0 MS |
1960 | |
1961 | /* Construct the indirection. */ | |
1962 | arg_type = lookup_pointer_type (arg_type); | |
1963 | arg = value_from_pointer (arg_type, sp); | |
8e80f9d1 | 1964 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1965 | } |
1966 | else | |
1967 | /* PCS C.15 / C.18 multiple values pass. */ | |
8e80f9d1 | 1968 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1969 | break; |
1970 | ||
1971 | default: | |
8e80f9d1 | 1972 | pass_in_x_or_stack (gdbarch, regcache, &info, arg_type, arg); |
07b287a0 MS |
1973 | break; |
1974 | } | |
1975 | } | |
1976 | ||
1977 | /* Make sure stack retains 16 byte alignment. */ | |
1978 | if (info.nsaa & 15) | |
1979 | sp -= 16 - (info.nsaa & 15); | |
1980 | ||
89055eaa | 1981 | while (!info.si.empty ()) |
07b287a0 | 1982 | { |
89055eaa | 1983 | const stack_item_t &si = info.si.back (); |
07b287a0 | 1984 | |
89055eaa TT |
1985 | sp -= si.len; |
1986 | if (si.data != NULL) | |
1987 | write_memory (sp, si.data, si.len); | |
1988 | info.si.pop_back (); | |
07b287a0 MS |
1989 | } |
1990 | ||
07b287a0 MS |
1991 | /* Finally, update the SP register. */ |
1992 | regcache_cooked_write_unsigned (regcache, AARCH64_SP_REGNUM, sp); | |
1993 | ||
1994 | return sp; | |
1995 | } | |
1996 | ||
1997 | /* Implement the "frame_align" gdbarch method. */ | |
1998 | ||
1999 | static CORE_ADDR | |
2000 | aarch64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2001 | { | |
2002 | /* Align the stack to sixteen bytes. */ | |
2003 | return sp & ~(CORE_ADDR) 15; | |
2004 | } | |
2005 | ||
2006 | /* Return the type for an AdvSISD Q register. */ | |
2007 | ||
2008 | static struct type * | |
2009 | aarch64_vnq_type (struct gdbarch *gdbarch) | |
2010 | { | |
08106042 | 2011 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2012 | |
2013 | if (tdep->vnq_type == NULL) | |
2014 | { | |
2015 | struct type *t; | |
2016 | struct type *elem; | |
2017 | ||
2018 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
2019 | TYPE_CODE_UNION); | |
2020 | ||
2021 | elem = builtin_type (gdbarch)->builtin_uint128; | |
2022 | append_composite_type_field (t, "u", elem); | |
2023 | ||
2024 | elem = builtin_type (gdbarch)->builtin_int128; | |
2025 | append_composite_type_field (t, "s", elem); | |
2026 | ||
2027 | tdep->vnq_type = t; | |
2028 | } | |
2029 | ||
2030 | return tdep->vnq_type; | |
2031 | } | |
2032 | ||
2033 | /* Return the type for an AdvSISD D register. */ | |
2034 | ||
2035 | static struct type * | |
2036 | aarch64_vnd_type (struct gdbarch *gdbarch) | |
2037 | { | |
08106042 | 2038 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2039 | |
2040 | if (tdep->vnd_type == NULL) | |
2041 | { | |
2042 | struct type *t; | |
2043 | struct type *elem; | |
2044 | ||
2045 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", | |
2046 | TYPE_CODE_UNION); | |
2047 | ||
2048 | elem = builtin_type (gdbarch)->builtin_double; | |
2049 | append_composite_type_field (t, "f", elem); | |
2050 | ||
2051 | elem = builtin_type (gdbarch)->builtin_uint64; | |
2052 | append_composite_type_field (t, "u", elem); | |
2053 | ||
2054 | elem = builtin_type (gdbarch)->builtin_int64; | |
2055 | append_composite_type_field (t, "s", elem); | |
2056 | ||
2057 | tdep->vnd_type = t; | |
2058 | } | |
2059 | ||
2060 | return tdep->vnd_type; | |
2061 | } | |
2062 | ||
2063 | /* Return the type for an AdvSISD S register. */ | |
2064 | ||
2065 | static struct type * | |
2066 | aarch64_vns_type (struct gdbarch *gdbarch) | |
2067 | { | |
08106042 | 2068 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2069 | |
2070 | if (tdep->vns_type == NULL) | |
2071 | { | |
2072 | struct type *t; | |
2073 | struct type *elem; | |
2074 | ||
2075 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
2076 | TYPE_CODE_UNION); | |
2077 | ||
2078 | elem = builtin_type (gdbarch)->builtin_float; | |
2079 | append_composite_type_field (t, "f", elem); | |
2080 | ||
2081 | elem = builtin_type (gdbarch)->builtin_uint32; | |
2082 | append_composite_type_field (t, "u", elem); | |
2083 | ||
2084 | elem = builtin_type (gdbarch)->builtin_int32; | |
2085 | append_composite_type_field (t, "s", elem); | |
2086 | ||
2087 | tdep->vns_type = t; | |
2088 | } | |
2089 | ||
2090 | return tdep->vns_type; | |
2091 | } | |
2092 | ||
2093 | /* Return the type for an AdvSISD H register. */ | |
2094 | ||
2095 | static struct type * | |
2096 | aarch64_vnh_type (struct gdbarch *gdbarch) | |
2097 | { | |
08106042 | 2098 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2099 | |
2100 | if (tdep->vnh_type == NULL) | |
2101 | { | |
2102 | struct type *t; | |
2103 | struct type *elem; | |
2104 | ||
2105 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
2106 | TYPE_CODE_UNION); | |
2107 | ||
5291fe3c SP |
2108 | elem = builtin_type (gdbarch)->builtin_bfloat16; |
2109 | append_composite_type_field (t, "bf", elem); | |
2110 | ||
a6d0f249 AH |
2111 | elem = builtin_type (gdbarch)->builtin_half; |
2112 | append_composite_type_field (t, "f", elem); | |
2113 | ||
07b287a0 MS |
2114 | elem = builtin_type (gdbarch)->builtin_uint16; |
2115 | append_composite_type_field (t, "u", elem); | |
2116 | ||
2117 | elem = builtin_type (gdbarch)->builtin_int16; | |
2118 | append_composite_type_field (t, "s", elem); | |
2119 | ||
2120 | tdep->vnh_type = t; | |
2121 | } | |
2122 | ||
2123 | return tdep->vnh_type; | |
2124 | } | |
2125 | ||
2126 | /* Return the type for an AdvSISD B register. */ | |
2127 | ||
2128 | static struct type * | |
2129 | aarch64_vnb_type (struct gdbarch *gdbarch) | |
2130 | { | |
08106042 | 2131 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2132 | |
2133 | if (tdep->vnb_type == NULL) | |
2134 | { | |
2135 | struct type *t; | |
2136 | struct type *elem; | |
2137 | ||
2138 | t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
2139 | TYPE_CODE_UNION); | |
2140 | ||
2141 | elem = builtin_type (gdbarch)->builtin_uint8; | |
2142 | append_composite_type_field (t, "u", elem); | |
2143 | ||
2144 | elem = builtin_type (gdbarch)->builtin_int8; | |
2145 | append_composite_type_field (t, "s", elem); | |
2146 | ||
2147 | tdep->vnb_type = t; | |
2148 | } | |
2149 | ||
2150 | return tdep->vnb_type; | |
2151 | } | |
2152 | ||
63bad7b6 AH |
2153 | /* Return the type for an AdvSISD V register. */ |
2154 | ||
2155 | static struct type * | |
2156 | aarch64_vnv_type (struct gdbarch *gdbarch) | |
2157 | { | |
08106042 | 2158 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 AH |
2159 | |
2160 | if (tdep->vnv_type == NULL) | |
2161 | { | |
09624f1f | 2162 | /* The other AArch64 pseudo registers (Q,D,H,S,B) refer to a single value |
bffa1015 AH |
2163 | slice from the non-pseudo vector registers. However NEON V registers |
2164 | are always vector registers, and need constructing as such. */ | |
2165 | const struct builtin_type *bt = builtin_type (gdbarch); | |
2166 | ||
63bad7b6 AH |
2167 | struct type *t = arch_composite_type (gdbarch, "__gdb_builtin_type_vnv", |
2168 | TYPE_CODE_UNION); | |
2169 | ||
bffa1015 AH |
2170 | struct type *sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnd", |
2171 | TYPE_CODE_UNION); | |
2172 | append_composite_type_field (sub, "f", | |
2173 | init_vector_type (bt->builtin_double, 2)); | |
2174 | append_composite_type_field (sub, "u", | |
2175 | init_vector_type (bt->builtin_uint64, 2)); | |
2176 | append_composite_type_field (sub, "s", | |
2177 | init_vector_type (bt->builtin_int64, 2)); | |
2178 | append_composite_type_field (t, "d", sub); | |
2179 | ||
2180 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vns", | |
2181 | TYPE_CODE_UNION); | |
2182 | append_composite_type_field (sub, "f", | |
2183 | init_vector_type (bt->builtin_float, 4)); | |
2184 | append_composite_type_field (sub, "u", | |
2185 | init_vector_type (bt->builtin_uint32, 4)); | |
2186 | append_composite_type_field (sub, "s", | |
2187 | init_vector_type (bt->builtin_int32, 4)); | |
2188 | append_composite_type_field (t, "s", sub); | |
2189 | ||
2190 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnh", | |
2191 | TYPE_CODE_UNION); | |
5291fe3c SP |
2192 | append_composite_type_field (sub, "bf", |
2193 | init_vector_type (bt->builtin_bfloat16, 8)); | |
a6d0f249 AH |
2194 | append_composite_type_field (sub, "f", |
2195 | init_vector_type (bt->builtin_half, 8)); | |
bffa1015 AH |
2196 | append_composite_type_field (sub, "u", |
2197 | init_vector_type (bt->builtin_uint16, 8)); | |
2198 | append_composite_type_field (sub, "s", | |
2199 | init_vector_type (bt->builtin_int16, 8)); | |
2200 | append_composite_type_field (t, "h", sub); | |
2201 | ||
2202 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnb", | |
2203 | TYPE_CODE_UNION); | |
2204 | append_composite_type_field (sub, "u", | |
2205 | init_vector_type (bt->builtin_uint8, 16)); | |
2206 | append_composite_type_field (sub, "s", | |
2207 | init_vector_type (bt->builtin_int8, 16)); | |
2208 | append_composite_type_field (t, "b", sub); | |
2209 | ||
2210 | sub = arch_composite_type (gdbarch, "__gdb_builtin_type_vnq", | |
2211 | TYPE_CODE_UNION); | |
2212 | append_composite_type_field (sub, "u", | |
2213 | init_vector_type (bt->builtin_uint128, 1)); | |
2214 | append_composite_type_field (sub, "s", | |
2215 | init_vector_type (bt->builtin_int128, 1)); | |
2216 | append_composite_type_field (t, "q", sub); | |
63bad7b6 AH |
2217 | |
2218 | tdep->vnv_type = t; | |
2219 | } | |
2220 | ||
2221 | return tdep->vnv_type; | |
2222 | } | |
2223 | ||
07b287a0 MS |
2224 | /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */ |
2225 | ||
2226 | static int | |
2227 | aarch64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) | |
2228 | { | |
08106042 | 2229 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
34dcc7cf | 2230 | |
07b287a0 MS |
2231 | if (reg >= AARCH64_DWARF_X0 && reg <= AARCH64_DWARF_X0 + 30) |
2232 | return AARCH64_X0_REGNUM + reg - AARCH64_DWARF_X0; | |
2233 | ||
2234 | if (reg == AARCH64_DWARF_SP) | |
2235 | return AARCH64_SP_REGNUM; | |
2236 | ||
1fe84861 YY |
2237 | if (reg == AARCH64_DWARF_PC) |
2238 | return AARCH64_PC_REGNUM; | |
2239 | ||
07b287a0 MS |
2240 | if (reg >= AARCH64_DWARF_V0 && reg <= AARCH64_DWARF_V0 + 31) |
2241 | return AARCH64_V0_REGNUM + reg - AARCH64_DWARF_V0; | |
2242 | ||
65d4cada AH |
2243 | if (reg == AARCH64_DWARF_SVE_VG) |
2244 | return AARCH64_SVE_VG_REGNUM; | |
2245 | ||
2246 | if (reg == AARCH64_DWARF_SVE_FFR) | |
2247 | return AARCH64_SVE_FFR_REGNUM; | |
2248 | ||
2249 | if (reg >= AARCH64_DWARF_SVE_P0 && reg <= AARCH64_DWARF_SVE_P0 + 15) | |
2250 | return AARCH64_SVE_P0_REGNUM + reg - AARCH64_DWARF_SVE_P0; | |
2251 | ||
2252 | if (reg >= AARCH64_DWARF_SVE_Z0 && reg <= AARCH64_DWARF_SVE_Z0 + 15) | |
2253 | return AARCH64_SVE_Z0_REGNUM + reg - AARCH64_DWARF_SVE_Z0; | |
2254 | ||
34dcc7cf AH |
2255 | if (tdep->has_pauth ()) |
2256 | { | |
c9cd8ca4 LM |
2257 | if (reg == AARCH64_DWARF_RA_SIGN_STATE) |
2258 | return tdep->ra_sign_state_regnum; | |
34dcc7cf AH |
2259 | } |
2260 | ||
07b287a0 MS |
2261 | return -1; |
2262 | } | |
07b287a0 MS |
2263 | |
2264 | /* Implement the "print_insn" gdbarch method. */ | |
2265 | ||
2266 | static int | |
2267 | aarch64_gdb_print_insn (bfd_vma memaddr, disassemble_info *info) | |
2268 | { | |
2269 | info->symbols = NULL; | |
6394c606 | 2270 | return default_print_insn (memaddr, info); |
07b287a0 MS |
2271 | } |
2272 | ||
2273 | /* AArch64 BRK software debug mode instruction. | |
2274 | Note that AArch64 code is always little-endian. | |
2275 | 1101.0100.0010.0000.0000.0000.0000.0000 = 0xd4200000. */ | |
04180708 | 2276 | constexpr gdb_byte aarch64_default_breakpoint[] = {0x00, 0x00, 0x20, 0xd4}; |
07b287a0 | 2277 | |
04180708 | 2278 | typedef BP_MANIPULATION (aarch64_default_breakpoint) aarch64_breakpoint; |
07b287a0 MS |
2279 | |
2280 | /* Extract from an array REGS containing the (raw) register state a | |
2281 | function return value of type TYPE, and copy that, in virtual | |
2282 | format, into VALBUF. */ | |
2283 | ||
2284 | static void | |
2285 | aarch64_extract_return_value (struct type *type, struct regcache *regs, | |
2286 | gdb_byte *valbuf) | |
2287 | { | |
ac7936df | 2288 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 | 2289 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4f4aedeb AH |
2290 | int elements; |
2291 | struct type *fundamental_type; | |
07b287a0 | 2292 | |
4f4aedeb AH |
2293 | if (aapcs_is_vfp_call_or_return_candidate (type, &elements, |
2294 | &fundamental_type)) | |
07b287a0 | 2295 | { |
4f4aedeb AH |
2296 | int len = TYPE_LENGTH (fundamental_type); |
2297 | ||
2298 | for (int i = 0; i < elements; i++) | |
2299 | { | |
2300 | int regno = AARCH64_V0_REGNUM + i; | |
3ff2c72e AH |
2301 | /* Enough space for a full vector register. */ |
2302 | gdb_byte buf[register_size (gdbarch, regno)]; | |
2303 | gdb_assert (len <= sizeof (buf)); | |
4f4aedeb | 2304 | |
c6185dce SM |
2305 | aarch64_debug_printf |
2306 | ("read HFA or HVA return value element %d from %s", | |
2307 | i + 1, gdbarch_register_name (gdbarch, regno)); | |
2308 | ||
4f4aedeb | 2309 | regs->cooked_read (regno, buf); |
07b287a0 | 2310 | |
4f4aedeb AH |
2311 | memcpy (valbuf, buf, len); |
2312 | valbuf += len; | |
2313 | } | |
07b287a0 | 2314 | } |
78134374 SM |
2315 | else if (type->code () == TYPE_CODE_INT |
2316 | || type->code () == TYPE_CODE_CHAR | |
2317 | || type->code () == TYPE_CODE_BOOL | |
2318 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 2319 | || TYPE_IS_REFERENCE (type) |
78134374 | 2320 | || type->code () == TYPE_CODE_ENUM) |
07b287a0 | 2321 | { |
6471e7d2 | 2322 | /* If the type is a plain integer, then the access is |
07b287a0 MS |
2323 | straight-forward. Otherwise we have to play around a bit |
2324 | more. */ | |
2325 | int len = TYPE_LENGTH (type); | |
2326 | int regno = AARCH64_X0_REGNUM; | |
2327 | ULONGEST tmp; | |
2328 | ||
2329 | while (len > 0) | |
2330 | { | |
2331 | /* By using store_unsigned_integer we avoid having to do | |
2332 | anything special for small big-endian values. */ | |
2333 | regcache_cooked_read_unsigned (regs, regno++, &tmp); | |
2334 | store_unsigned_integer (valbuf, | |
2335 | (len > X_REGISTER_SIZE | |
2336 | ? X_REGISTER_SIZE : len), byte_order, tmp); | |
2337 | len -= X_REGISTER_SIZE; | |
2338 | valbuf += X_REGISTER_SIZE; | |
2339 | } | |
2340 | } | |
07b287a0 MS |
2341 | else |
2342 | { | |
2343 | /* For a structure or union the behaviour is as if the value had | |
dda83cd7 SM |
2344 | been stored to word-aligned memory and then loaded into |
2345 | registers with 64-bit load instruction(s). */ | |
07b287a0 MS |
2346 | int len = TYPE_LENGTH (type); |
2347 | int regno = AARCH64_X0_REGNUM; | |
2348 | bfd_byte buf[X_REGISTER_SIZE]; | |
2349 | ||
2350 | while (len > 0) | |
2351 | { | |
dca08e1f | 2352 | regs->cooked_read (regno++, buf); |
07b287a0 MS |
2353 | memcpy (valbuf, buf, len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); |
2354 | len -= X_REGISTER_SIZE; | |
2355 | valbuf += X_REGISTER_SIZE; | |
2356 | } | |
2357 | } | |
2358 | } | |
2359 | ||
2360 | ||
2361 | /* Will a function return an aggregate type in memory or in a | |
2362 | register? Return 0 if an aggregate type can be returned in a | |
2363 | register, 1 if it must be returned in memory. */ | |
2364 | ||
2365 | static int | |
2366 | aarch64_return_in_memory (struct gdbarch *gdbarch, struct type *type) | |
2367 | { | |
f168693b | 2368 | type = check_typedef (type); |
4f4aedeb AH |
2369 | int elements; |
2370 | struct type *fundamental_type; | |
07b287a0 | 2371 | |
4f4aedeb AH |
2372 | if (aapcs_is_vfp_call_or_return_candidate (type, &elements, |
2373 | &fundamental_type)) | |
07b287a0 | 2374 | { |
cd635f74 YQ |
2375 | /* v0-v7 are used to return values and one register is allocated |
2376 | for one member. However, HFA or HVA has at most four members. */ | |
07b287a0 MS |
2377 | return 0; |
2378 | } | |
2379 | ||
bab22d06 LM |
2380 | if (TYPE_LENGTH (type) > 16 |
2381 | || !language_pass_by_reference (type).trivially_copyable) | |
07b287a0 MS |
2382 | { |
2383 | /* PCS B.6 Aggregates larger than 16 bytes are passed by | |
dda83cd7 | 2384 | invisible reference. */ |
07b287a0 MS |
2385 | |
2386 | return 1; | |
2387 | } | |
2388 | ||
2389 | return 0; | |
2390 | } | |
2391 | ||
2392 | /* Write into appropriate registers a function return value of type | |
2393 | TYPE, given in virtual format. */ | |
2394 | ||
2395 | static void | |
2396 | aarch64_store_return_value (struct type *type, struct regcache *regs, | |
2397 | const gdb_byte *valbuf) | |
2398 | { | |
ac7936df | 2399 | struct gdbarch *gdbarch = regs->arch (); |
07b287a0 | 2400 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4f4aedeb AH |
2401 | int elements; |
2402 | struct type *fundamental_type; | |
07b287a0 | 2403 | |
4f4aedeb AH |
2404 | if (aapcs_is_vfp_call_or_return_candidate (type, &elements, |
2405 | &fundamental_type)) | |
07b287a0 | 2406 | { |
4f4aedeb AH |
2407 | int len = TYPE_LENGTH (fundamental_type); |
2408 | ||
2409 | for (int i = 0; i < elements; i++) | |
2410 | { | |
2411 | int regno = AARCH64_V0_REGNUM + i; | |
3ff2c72e AH |
2412 | /* Enough space for a full vector register. */ |
2413 | gdb_byte tmpbuf[register_size (gdbarch, regno)]; | |
2414 | gdb_assert (len <= sizeof (tmpbuf)); | |
4f4aedeb | 2415 | |
c6185dce SM |
2416 | aarch64_debug_printf |
2417 | ("write HFA or HVA return value element %d to %s", | |
2418 | i + 1, gdbarch_register_name (gdbarch, regno)); | |
07b287a0 | 2419 | |
4f4aedeb AH |
2420 | memcpy (tmpbuf, valbuf, |
2421 | len > V_REGISTER_SIZE ? V_REGISTER_SIZE : len); | |
2422 | regs->cooked_write (regno, tmpbuf); | |
2423 | valbuf += len; | |
2424 | } | |
07b287a0 | 2425 | } |
78134374 SM |
2426 | else if (type->code () == TYPE_CODE_INT |
2427 | || type->code () == TYPE_CODE_CHAR | |
2428 | || type->code () == TYPE_CODE_BOOL | |
2429 | || type->code () == TYPE_CODE_PTR | |
aa006118 | 2430 | || TYPE_IS_REFERENCE (type) |
78134374 | 2431 | || type->code () == TYPE_CODE_ENUM) |
07b287a0 MS |
2432 | { |
2433 | if (TYPE_LENGTH (type) <= X_REGISTER_SIZE) | |
2434 | { | |
2435 | /* Values of one word or less are zero/sign-extended and | |
2436 | returned in r0. */ | |
2437 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2438 | LONGEST val = unpack_long (type, valbuf); | |
2439 | ||
2440 | store_signed_integer (tmpbuf, X_REGISTER_SIZE, byte_order, val); | |
b66f5587 | 2441 | regs->cooked_write (AARCH64_X0_REGNUM, tmpbuf); |
07b287a0 MS |
2442 | } |
2443 | else | |
2444 | { | |
2445 | /* Integral values greater than one word are stored in | |
2446 | consecutive registers starting with r0. This will always | |
2447 | be a multiple of the regiser size. */ | |
2448 | int len = TYPE_LENGTH (type); | |
2449 | int regno = AARCH64_X0_REGNUM; | |
2450 | ||
2451 | while (len > 0) | |
2452 | { | |
b66f5587 | 2453 | regs->cooked_write (regno++, valbuf); |
07b287a0 MS |
2454 | len -= X_REGISTER_SIZE; |
2455 | valbuf += X_REGISTER_SIZE; | |
2456 | } | |
2457 | } | |
2458 | } | |
07b287a0 MS |
2459 | else |
2460 | { | |
2461 | /* For a structure or union the behaviour is as if the value had | |
2462 | been stored to word-aligned memory and then loaded into | |
2463 | registers with 64-bit load instruction(s). */ | |
2464 | int len = TYPE_LENGTH (type); | |
2465 | int regno = AARCH64_X0_REGNUM; | |
2466 | bfd_byte tmpbuf[X_REGISTER_SIZE]; | |
2467 | ||
2468 | while (len > 0) | |
2469 | { | |
2470 | memcpy (tmpbuf, valbuf, | |
2471 | len > X_REGISTER_SIZE ? X_REGISTER_SIZE : len); | |
b66f5587 | 2472 | regs->cooked_write (regno++, tmpbuf); |
07b287a0 MS |
2473 | len -= X_REGISTER_SIZE; |
2474 | valbuf += X_REGISTER_SIZE; | |
2475 | } | |
2476 | } | |
2477 | } | |
2478 | ||
2479 | /* Implement the "return_value" gdbarch method. */ | |
2480 | ||
2481 | static enum return_value_convention | |
2482 | aarch64_return_value (struct gdbarch *gdbarch, struct value *func_value, | |
2483 | struct type *valtype, struct regcache *regcache, | |
2484 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
2485 | { | |
07b287a0 | 2486 | |
78134374 SM |
2487 | if (valtype->code () == TYPE_CODE_STRUCT |
2488 | || valtype->code () == TYPE_CODE_UNION | |
2489 | || valtype->code () == TYPE_CODE_ARRAY) | |
07b287a0 MS |
2490 | { |
2491 | if (aarch64_return_in_memory (gdbarch, valtype)) | |
2492 | { | |
bab22d06 LM |
2493 | /* From the AAPCS64's Result Return section: |
2494 | ||
2495 | "Otherwise, the caller shall reserve a block of memory of | |
2496 | sufficient size and alignment to hold the result. The address | |
2497 | of the memory block shall be passed as an additional argument to | |
2498 | the function in x8. */ | |
2499 | ||
c6185dce | 2500 | aarch64_debug_printf ("return value in memory"); |
bab22d06 LM |
2501 | |
2502 | if (readbuf) | |
2503 | { | |
2504 | CORE_ADDR addr; | |
2505 | ||
2506 | regcache->cooked_read (AARCH64_STRUCT_RETURN_REGNUM, &addr); | |
2507 | read_memory (addr, readbuf, TYPE_LENGTH (valtype)); | |
2508 | } | |
2509 | ||
2510 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
07b287a0 MS |
2511 | } |
2512 | } | |
2513 | ||
2514 | if (writebuf) | |
2515 | aarch64_store_return_value (valtype, regcache, writebuf); | |
2516 | ||
2517 | if (readbuf) | |
2518 | aarch64_extract_return_value (valtype, regcache, readbuf); | |
2519 | ||
c6185dce | 2520 | aarch64_debug_printf ("return value in registers"); |
07b287a0 MS |
2521 | |
2522 | return RETURN_VALUE_REGISTER_CONVENTION; | |
2523 | } | |
2524 | ||
2525 | /* Implement the "get_longjmp_target" gdbarch method. */ | |
2526 | ||
2527 | static int | |
2528 | aarch64_get_longjmp_target (struct frame_info *frame, CORE_ADDR *pc) | |
2529 | { | |
2530 | CORE_ADDR jb_addr; | |
2531 | gdb_byte buf[X_REGISTER_SIZE]; | |
2532 | struct gdbarch *gdbarch = get_frame_arch (frame); | |
08106042 | 2533 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2534 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2535 | ||
2536 | jb_addr = get_frame_register_unsigned (frame, AARCH64_X0_REGNUM); | |
2537 | ||
2538 | if (target_read_memory (jb_addr + tdep->jb_pc * tdep->jb_elt_size, buf, | |
2539 | X_REGISTER_SIZE)) | |
2540 | return 0; | |
2541 | ||
2542 | *pc = extract_unsigned_integer (buf, X_REGISTER_SIZE, byte_order); | |
2543 | return 1; | |
2544 | } | |
ea873d8e PL |
2545 | |
2546 | /* Implement the "gen_return_address" gdbarch method. */ | |
2547 | ||
2548 | static void | |
2549 | aarch64_gen_return_address (struct gdbarch *gdbarch, | |
2550 | struct agent_expr *ax, struct axs_value *value, | |
2551 | CORE_ADDR scope) | |
2552 | { | |
2553 | value->type = register_type (gdbarch, AARCH64_LR_REGNUM); | |
2554 | value->kind = axs_lvalue_register; | |
2555 | value->u.reg = AARCH64_LR_REGNUM; | |
2556 | } | |
07b287a0 MS |
2557 | \f |
2558 | ||
2559 | /* Return the pseudo register name corresponding to register regnum. */ | |
2560 | ||
2561 | static const char * | |
2562 | aarch64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) | |
2563 | { | |
08106042 | 2564 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 | 2565 | |
07b287a0 MS |
2566 | static const char *const q_name[] = |
2567 | { | |
2568 | "q0", "q1", "q2", "q3", | |
2569 | "q4", "q5", "q6", "q7", | |
2570 | "q8", "q9", "q10", "q11", | |
2571 | "q12", "q13", "q14", "q15", | |
2572 | "q16", "q17", "q18", "q19", | |
2573 | "q20", "q21", "q22", "q23", | |
2574 | "q24", "q25", "q26", "q27", | |
2575 | "q28", "q29", "q30", "q31", | |
2576 | }; | |
2577 | ||
2578 | static const char *const d_name[] = | |
2579 | { | |
2580 | "d0", "d1", "d2", "d3", | |
2581 | "d4", "d5", "d6", "d7", | |
2582 | "d8", "d9", "d10", "d11", | |
2583 | "d12", "d13", "d14", "d15", | |
2584 | "d16", "d17", "d18", "d19", | |
2585 | "d20", "d21", "d22", "d23", | |
2586 | "d24", "d25", "d26", "d27", | |
2587 | "d28", "d29", "d30", "d31", | |
2588 | }; | |
2589 | ||
2590 | static const char *const s_name[] = | |
2591 | { | |
2592 | "s0", "s1", "s2", "s3", | |
2593 | "s4", "s5", "s6", "s7", | |
2594 | "s8", "s9", "s10", "s11", | |
2595 | "s12", "s13", "s14", "s15", | |
2596 | "s16", "s17", "s18", "s19", | |
2597 | "s20", "s21", "s22", "s23", | |
2598 | "s24", "s25", "s26", "s27", | |
2599 | "s28", "s29", "s30", "s31", | |
2600 | }; | |
2601 | ||
2602 | static const char *const h_name[] = | |
2603 | { | |
2604 | "h0", "h1", "h2", "h3", | |
2605 | "h4", "h5", "h6", "h7", | |
2606 | "h8", "h9", "h10", "h11", | |
2607 | "h12", "h13", "h14", "h15", | |
2608 | "h16", "h17", "h18", "h19", | |
2609 | "h20", "h21", "h22", "h23", | |
2610 | "h24", "h25", "h26", "h27", | |
2611 | "h28", "h29", "h30", "h31", | |
2612 | }; | |
2613 | ||
2614 | static const char *const b_name[] = | |
2615 | { | |
2616 | "b0", "b1", "b2", "b3", | |
2617 | "b4", "b5", "b6", "b7", | |
2618 | "b8", "b9", "b10", "b11", | |
2619 | "b12", "b13", "b14", "b15", | |
2620 | "b16", "b17", "b18", "b19", | |
2621 | "b20", "b21", "b22", "b23", | |
2622 | "b24", "b25", "b26", "b27", | |
2623 | "b28", "b29", "b30", "b31", | |
2624 | }; | |
2625 | ||
34dcc7cf | 2626 | int p_regnum = regnum - gdbarch_num_regs (gdbarch); |
07b287a0 | 2627 | |
34dcc7cf AH |
2628 | if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32) |
2629 | return q_name[p_regnum - AARCH64_Q0_REGNUM]; | |
07b287a0 | 2630 | |
34dcc7cf AH |
2631 | if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32) |
2632 | return d_name[p_regnum - AARCH64_D0_REGNUM]; | |
07b287a0 | 2633 | |
34dcc7cf AH |
2634 | if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32) |
2635 | return s_name[p_regnum - AARCH64_S0_REGNUM]; | |
07b287a0 | 2636 | |
34dcc7cf AH |
2637 | if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32) |
2638 | return h_name[p_regnum - AARCH64_H0_REGNUM]; | |
07b287a0 | 2639 | |
34dcc7cf AH |
2640 | if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32) |
2641 | return b_name[p_regnum - AARCH64_B0_REGNUM]; | |
07b287a0 | 2642 | |
63bad7b6 AH |
2643 | if (tdep->has_sve ()) |
2644 | { | |
2645 | static const char *const sve_v_name[] = | |
2646 | { | |
2647 | "v0", "v1", "v2", "v3", | |
2648 | "v4", "v5", "v6", "v7", | |
2649 | "v8", "v9", "v10", "v11", | |
2650 | "v12", "v13", "v14", "v15", | |
2651 | "v16", "v17", "v18", "v19", | |
2652 | "v20", "v21", "v22", "v23", | |
2653 | "v24", "v25", "v26", "v27", | |
2654 | "v28", "v29", "v30", "v31", | |
2655 | }; | |
2656 | ||
34dcc7cf AH |
2657 | if (p_regnum >= AARCH64_SVE_V0_REGNUM |
2658 | && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
2659 | return sve_v_name[p_regnum - AARCH64_SVE_V0_REGNUM]; | |
63bad7b6 AH |
2660 | } |
2661 | ||
34dcc7cf AH |
2662 | /* RA_STATE is used for unwinding only. Do not assign it a name - this |
2663 | prevents it from being read by methods such as | |
2664 | mi_cmd_trace_frame_collected. */ | |
c9cd8ca4 | 2665 | if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum) |
34dcc7cf AH |
2666 | return ""; |
2667 | ||
07b287a0 MS |
2668 | internal_error (__FILE__, __LINE__, |
2669 | _("aarch64_pseudo_register_name: bad register number %d"), | |
34dcc7cf | 2670 | p_regnum); |
07b287a0 MS |
2671 | } |
2672 | ||
2673 | /* Implement the "pseudo_register_type" tdesc_arch_data method. */ | |
2674 | ||
2675 | static struct type * | |
2676 | aarch64_pseudo_register_type (struct gdbarch *gdbarch, int regnum) | |
2677 | { | |
08106042 | 2678 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 | 2679 | |
34dcc7cf | 2680 | int p_regnum = regnum - gdbarch_num_regs (gdbarch); |
07b287a0 | 2681 | |
34dcc7cf | 2682 | if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32) |
07b287a0 MS |
2683 | return aarch64_vnq_type (gdbarch); |
2684 | ||
34dcc7cf | 2685 | if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32) |
07b287a0 MS |
2686 | return aarch64_vnd_type (gdbarch); |
2687 | ||
34dcc7cf | 2688 | if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32) |
07b287a0 MS |
2689 | return aarch64_vns_type (gdbarch); |
2690 | ||
34dcc7cf | 2691 | if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32) |
07b287a0 MS |
2692 | return aarch64_vnh_type (gdbarch); |
2693 | ||
34dcc7cf | 2694 | if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32) |
07b287a0 MS |
2695 | return aarch64_vnb_type (gdbarch); |
2696 | ||
34dcc7cf AH |
2697 | if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM |
2698 | && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
63bad7b6 AH |
2699 | return aarch64_vnv_type (gdbarch); |
2700 | ||
c9cd8ca4 | 2701 | if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum) |
34dcc7cf AH |
2702 | return builtin_type (gdbarch)->builtin_uint64; |
2703 | ||
07b287a0 MS |
2704 | internal_error (__FILE__, __LINE__, |
2705 | _("aarch64_pseudo_register_type: bad register number %d"), | |
34dcc7cf | 2706 | p_regnum); |
07b287a0 MS |
2707 | } |
2708 | ||
2709 | /* Implement the "pseudo_register_reggroup_p" tdesc_arch_data method. */ | |
2710 | ||
2711 | static int | |
2712 | aarch64_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 2713 | const struct reggroup *group) |
07b287a0 | 2714 | { |
08106042 | 2715 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
63bad7b6 | 2716 | |
34dcc7cf | 2717 | int p_regnum = regnum - gdbarch_num_regs (gdbarch); |
07b287a0 | 2718 | |
34dcc7cf | 2719 | if (p_regnum >= AARCH64_Q0_REGNUM && p_regnum < AARCH64_Q0_REGNUM + 32) |
07b287a0 | 2720 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf | 2721 | else if (p_regnum >= AARCH64_D0_REGNUM && p_regnum < AARCH64_D0_REGNUM + 32) |
07b287a0 MS |
2722 | return (group == all_reggroup || group == vector_reggroup |
2723 | || group == float_reggroup); | |
34dcc7cf | 2724 | else if (p_regnum >= AARCH64_S0_REGNUM && p_regnum < AARCH64_S0_REGNUM + 32) |
07b287a0 MS |
2725 | return (group == all_reggroup || group == vector_reggroup |
2726 | || group == float_reggroup); | |
34dcc7cf | 2727 | else if (p_regnum >= AARCH64_H0_REGNUM && p_regnum < AARCH64_H0_REGNUM + 32) |
07b287a0 | 2728 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf | 2729 | else if (p_regnum >= AARCH64_B0_REGNUM && p_regnum < AARCH64_B0_REGNUM + 32) |
07b287a0 | 2730 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf AH |
2731 | else if (tdep->has_sve () && p_regnum >= AARCH64_SVE_V0_REGNUM |
2732 | && p_regnum < AARCH64_SVE_V0_REGNUM + AARCH64_V_REGS_NUM) | |
63bad7b6 | 2733 | return group == all_reggroup || group == vector_reggroup; |
34dcc7cf | 2734 | /* RA_STATE is used for unwinding only. Do not assign it to any groups. */ |
c9cd8ca4 | 2735 | if (tdep->has_pauth () && regnum == tdep->ra_sign_state_regnum) |
34dcc7cf | 2736 | return 0; |
07b287a0 MS |
2737 | |
2738 | return group == all_reggroup; | |
2739 | } | |
2740 | ||
3c5cd5c3 AH |
2741 | /* Helper for aarch64_pseudo_read_value. */ |
2742 | ||
2743 | static struct value * | |
63bad7b6 AH |
2744 | aarch64_pseudo_read_value_1 (struct gdbarch *gdbarch, |
2745 | readable_regcache *regcache, int regnum_offset, | |
3c5cd5c3 AH |
2746 | int regsize, struct value *result_value) |
2747 | { | |
3c5cd5c3 AH |
2748 | unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset; |
2749 | ||
63bad7b6 AH |
2750 | /* Enough space for a full vector register. */ |
2751 | gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)]; | |
2752 | gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM); | |
2753 | ||
3c5cd5c3 AH |
2754 | if (regcache->raw_read (v_regnum, reg_buf) != REG_VALID) |
2755 | mark_value_bytes_unavailable (result_value, 0, | |
2756 | TYPE_LENGTH (value_type (result_value))); | |
2757 | else | |
50888e42 | 2758 | memcpy (value_contents_raw (result_value).data (), reg_buf, regsize); |
63bad7b6 | 2759 | |
3c5cd5c3 AH |
2760 | return result_value; |
2761 | } | |
2762 | ||
07b287a0 MS |
2763 | /* Implement the "pseudo_register_read_value" gdbarch method. */ |
2764 | ||
2765 | static struct value * | |
3c5cd5c3 | 2766 | aarch64_pseudo_read_value (struct gdbarch *gdbarch, readable_regcache *regcache, |
07b287a0 MS |
2767 | int regnum) |
2768 | { | |
08106042 | 2769 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
3c5cd5c3 | 2770 | struct value *result_value = allocate_value (register_type (gdbarch, regnum)); |
07b287a0 | 2771 | |
07b287a0 MS |
2772 | VALUE_LVAL (result_value) = lval_register; |
2773 | VALUE_REGNUM (result_value) = regnum; | |
07b287a0 MS |
2774 | |
2775 | regnum -= gdbarch_num_regs (gdbarch); | |
2776 | ||
2777 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
63bad7b6 AH |
2778 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2779 | regnum - AARCH64_Q0_REGNUM, | |
3c5cd5c3 | 2780 | Q_REGISTER_SIZE, result_value); |
07b287a0 MS |
2781 | |
2782 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
63bad7b6 AH |
2783 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2784 | regnum - AARCH64_D0_REGNUM, | |
3c5cd5c3 | 2785 | D_REGISTER_SIZE, result_value); |
07b287a0 MS |
2786 | |
2787 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
63bad7b6 AH |
2788 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2789 | regnum - AARCH64_S0_REGNUM, | |
3c5cd5c3 | 2790 | S_REGISTER_SIZE, result_value); |
07b287a0 MS |
2791 | |
2792 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
63bad7b6 AH |
2793 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2794 | regnum - AARCH64_H0_REGNUM, | |
3c5cd5c3 | 2795 | H_REGISTER_SIZE, result_value); |
07b287a0 MS |
2796 | |
2797 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
63bad7b6 AH |
2798 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, |
2799 | regnum - AARCH64_B0_REGNUM, | |
3c5cd5c3 | 2800 | B_REGISTER_SIZE, result_value); |
07b287a0 | 2801 | |
63bad7b6 AH |
2802 | if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM |
2803 | && regnum < AARCH64_SVE_V0_REGNUM + 32) | |
2804 | return aarch64_pseudo_read_value_1 (gdbarch, regcache, | |
2805 | regnum - AARCH64_SVE_V0_REGNUM, | |
2806 | V_REGISTER_SIZE, result_value); | |
2807 | ||
07b287a0 MS |
2808 | gdb_assert_not_reached ("regnum out of bound"); |
2809 | } | |
2810 | ||
3c5cd5c3 | 2811 | /* Helper for aarch64_pseudo_write. */ |
07b287a0 MS |
2812 | |
2813 | static void | |
63bad7b6 AH |
2814 | aarch64_pseudo_write_1 (struct gdbarch *gdbarch, struct regcache *regcache, |
2815 | int regnum_offset, int regsize, const gdb_byte *buf) | |
07b287a0 | 2816 | { |
3c5cd5c3 | 2817 | unsigned v_regnum = AARCH64_V0_REGNUM + regnum_offset; |
07b287a0 | 2818 | |
63bad7b6 AH |
2819 | /* Enough space for a full vector register. */ |
2820 | gdb_byte reg_buf[register_size (gdbarch, AARCH64_V0_REGNUM)]; | |
2821 | gdb_static_assert (AARCH64_V0_REGNUM == AARCH64_SVE_Z0_REGNUM); | |
2822 | ||
07b287a0 MS |
2823 | /* Ensure the register buffer is zero, we want gdb writes of the |
2824 | various 'scalar' pseudo registers to behavior like architectural | |
2825 | writes, register width bytes are written the remainder are set to | |
2826 | zero. */ | |
63bad7b6 | 2827 | memset (reg_buf, 0, register_size (gdbarch, AARCH64_V0_REGNUM)); |
07b287a0 | 2828 | |
3c5cd5c3 AH |
2829 | memcpy (reg_buf, buf, regsize); |
2830 | regcache->raw_write (v_regnum, reg_buf); | |
2831 | } | |
2832 | ||
2833 | /* Implement the "pseudo_register_write" gdbarch method. */ | |
2834 | ||
2835 | static void | |
2836 | aarch64_pseudo_write (struct gdbarch *gdbarch, struct regcache *regcache, | |
2837 | int regnum, const gdb_byte *buf) | |
2838 | { | |
08106042 | 2839 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
2840 | regnum -= gdbarch_num_regs (gdbarch); |
2841 | ||
2842 | if (regnum >= AARCH64_Q0_REGNUM && regnum < AARCH64_Q0_REGNUM + 32) | |
63bad7b6 AH |
2843 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2844 | regnum - AARCH64_Q0_REGNUM, Q_REGISTER_SIZE, | |
2845 | buf); | |
07b287a0 MS |
2846 | |
2847 | if (regnum >= AARCH64_D0_REGNUM && regnum < AARCH64_D0_REGNUM + 32) | |
63bad7b6 AH |
2848 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2849 | regnum - AARCH64_D0_REGNUM, D_REGISTER_SIZE, | |
2850 | buf); | |
07b287a0 MS |
2851 | |
2852 | if (regnum >= AARCH64_S0_REGNUM && regnum < AARCH64_S0_REGNUM + 32) | |
63bad7b6 AH |
2853 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2854 | regnum - AARCH64_S0_REGNUM, S_REGISTER_SIZE, | |
2855 | buf); | |
07b287a0 MS |
2856 | |
2857 | if (regnum >= AARCH64_H0_REGNUM && regnum < AARCH64_H0_REGNUM + 32) | |
63bad7b6 AH |
2858 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2859 | regnum - AARCH64_H0_REGNUM, H_REGISTER_SIZE, | |
2860 | buf); | |
07b287a0 MS |
2861 | |
2862 | if (regnum >= AARCH64_B0_REGNUM && regnum < AARCH64_B0_REGNUM + 32) | |
63bad7b6 AH |
2863 | return aarch64_pseudo_write_1 (gdbarch, regcache, |
2864 | regnum - AARCH64_B0_REGNUM, B_REGISTER_SIZE, | |
2865 | buf); | |
2866 | ||
2867 | if (tdep->has_sve () && regnum >= AARCH64_SVE_V0_REGNUM | |
2868 | && regnum < AARCH64_SVE_V0_REGNUM + 32) | |
2869 | return aarch64_pseudo_write_1 (gdbarch, regcache, | |
2870 | regnum - AARCH64_SVE_V0_REGNUM, | |
2871 | V_REGISTER_SIZE, buf); | |
07b287a0 MS |
2872 | |
2873 | gdb_assert_not_reached ("regnum out of bound"); | |
2874 | } | |
2875 | ||
07b287a0 MS |
2876 | /* Callback function for user_reg_add. */ |
2877 | ||
2878 | static struct value * | |
2879 | value_of_aarch64_user_reg (struct frame_info *frame, const void *baton) | |
2880 | { | |
9a3c8263 | 2881 | const int *reg_p = (const int *) baton; |
07b287a0 MS |
2882 | |
2883 | return value_of_register (*reg_p, frame); | |
2884 | } | |
2885 | \f | |
2886 | ||
9404b58f KM |
2887 | /* Implement the "software_single_step" gdbarch method, needed to |
2888 | single step through atomic sequences on AArch64. */ | |
2889 | ||
a0ff9e1a | 2890 | static std::vector<CORE_ADDR> |
f5ea389a | 2891 | aarch64_software_single_step (struct regcache *regcache) |
9404b58f | 2892 | { |
ac7936df | 2893 | struct gdbarch *gdbarch = regcache->arch (); |
9404b58f KM |
2894 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
2895 | const int insn_size = 4; | |
2896 | const int atomic_sequence_length = 16; /* Instruction sequence length. */ | |
0187a92f | 2897 | CORE_ADDR pc = regcache_read_pc (regcache); |
70ab8ccd | 2898 | CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX }; |
9404b58f KM |
2899 | CORE_ADDR loc = pc; |
2900 | CORE_ADDR closing_insn = 0; | |
2901 | uint32_t insn = read_memory_unsigned_integer (loc, insn_size, | |
2902 | byte_order_for_code); | |
2903 | int index; | |
2904 | int insn_count; | |
2905 | int bc_insn_count = 0; /* Conditional branch instruction count. */ | |
2906 | int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ | |
f77ee802 YQ |
2907 | aarch64_inst inst; |
2908 | ||
561a72d4 | 2909 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
a0ff9e1a | 2910 | return {}; |
9404b58f KM |
2911 | |
2912 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
f77ee802 | 2913 | if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0) |
a0ff9e1a | 2914 | return {}; |
9404b58f KM |
2915 | |
2916 | for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) | |
2917 | { | |
9404b58f KM |
2918 | loc += insn_size; |
2919 | insn = read_memory_unsigned_integer (loc, insn_size, | |
2920 | byte_order_for_code); | |
2921 | ||
561a72d4 | 2922 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
a0ff9e1a | 2923 | return {}; |
9404b58f | 2924 | /* Check if the instruction is a conditional branch. */ |
f77ee802 | 2925 | if (inst.opcode->iclass == condbranch) |
9404b58f | 2926 | { |
f77ee802 YQ |
2927 | gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19); |
2928 | ||
9404b58f | 2929 | if (bc_insn_count >= 1) |
a0ff9e1a | 2930 | return {}; |
9404b58f KM |
2931 | |
2932 | /* It is, so we'll try to set a breakpoint at the destination. */ | |
f77ee802 | 2933 | breaks[1] = loc + inst.operands[0].imm.value; |
9404b58f KM |
2934 | |
2935 | bc_insn_count++; | |
2936 | last_breakpoint++; | |
2937 | } | |
2938 | ||
2939 | /* Look for the Store Exclusive which closes the atomic sequence. */ | |
f77ee802 | 2940 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22) == 0) |
9404b58f KM |
2941 | { |
2942 | closing_insn = loc; | |
2943 | break; | |
2944 | } | |
2945 | } | |
2946 | ||
2947 | /* We didn't find a closing Store Exclusive instruction, fall back. */ | |
2948 | if (!closing_insn) | |
a0ff9e1a | 2949 | return {}; |
9404b58f KM |
2950 | |
2951 | /* Insert breakpoint after the end of the atomic sequence. */ | |
2952 | breaks[0] = loc + insn_size; | |
2953 | ||
2954 | /* Check for duplicated breakpoints, and also check that the second | |
2955 | breakpoint is not within the atomic sequence. */ | |
2956 | if (last_breakpoint | |
2957 | && (breaks[1] == breaks[0] | |
2958 | || (breaks[1] >= pc && breaks[1] <= closing_insn))) | |
2959 | last_breakpoint = 0; | |
2960 | ||
a0ff9e1a SM |
2961 | std::vector<CORE_ADDR> next_pcs; |
2962 | ||
9404b58f KM |
2963 | /* Insert the breakpoint at the end of the sequence, and one at the |
2964 | destination of the conditional branch, if it exists. */ | |
2965 | for (index = 0; index <= last_breakpoint; index++) | |
a0ff9e1a | 2966 | next_pcs.push_back (breaks[index]); |
9404b58f | 2967 | |
93f9a11f | 2968 | return next_pcs; |
9404b58f KM |
2969 | } |
2970 | ||
1152d984 SM |
2971 | struct aarch64_displaced_step_copy_insn_closure |
2972 | : public displaced_step_copy_insn_closure | |
b6542f81 YQ |
2973 | { |
2974 | /* It is true when condition instruction, such as B.CON, TBZ, etc, | |
2975 | is being displaced stepping. */ | |
f0c702d4 | 2976 | bool cond = false; |
b6542f81 | 2977 | |
0c271889 LM |
2978 | /* PC adjustment offset after displaced stepping. If 0, then we don't |
2979 | write the PC back, assuming the PC is already the right address. */ | |
cfba9872 | 2980 | int32_t pc_adjust = 0; |
b6542f81 YQ |
2981 | }; |
2982 | ||
2983 | /* Data when visiting instructions for displaced stepping. */ | |
2984 | ||
2985 | struct aarch64_displaced_step_data | |
2986 | { | |
2987 | struct aarch64_insn_data base; | |
2988 | ||
2989 | /* The address where the instruction will be executed at. */ | |
2990 | CORE_ADDR new_addr; | |
2991 | /* Buffer of instructions to be copied to NEW_ADDR to execute. */ | |
e935475c | 2992 | uint32_t insn_buf[AARCH64_DISPLACED_MODIFIED_INSNS]; |
b6542f81 YQ |
2993 | /* Number of instructions in INSN_BUF. */ |
2994 | unsigned insn_count; | |
2995 | /* Registers when doing displaced stepping. */ | |
2996 | struct regcache *regs; | |
2997 | ||
1152d984 | 2998 | aarch64_displaced_step_copy_insn_closure *dsc; |
b6542f81 YQ |
2999 | }; |
3000 | ||
3001 | /* Implementation of aarch64_insn_visitor method "b". */ | |
3002 | ||
3003 | static void | |
3004 | aarch64_displaced_step_b (const int is_bl, const int32_t offset, | |
3005 | struct aarch64_insn_data *data) | |
3006 | { | |
3007 | struct aarch64_displaced_step_data *dsd | |
3008 | = (struct aarch64_displaced_step_data *) data; | |
2ac09a5b | 3009 | int64_t new_offset = data->insn_addr - dsd->new_addr + offset; |
b6542f81 YQ |
3010 | |
3011 | if (can_encode_int32 (new_offset, 28)) | |
3012 | { | |
3013 | /* Emit B rather than BL, because executing BL on a new address | |
3014 | will get the wrong address into LR. In order to avoid this, | |
3015 | we emit B, and update LR if the instruction is BL. */ | |
3016 | emit_b (dsd->insn_buf, 0, new_offset); | |
3017 | dsd->insn_count++; | |
3018 | } | |
3019 | else | |
3020 | { | |
3021 | /* Write NOP. */ | |
3022 | emit_nop (dsd->insn_buf); | |
3023 | dsd->insn_count++; | |
3024 | dsd->dsc->pc_adjust = offset; | |
3025 | } | |
3026 | ||
3027 | if (is_bl) | |
3028 | { | |
3029 | /* Update LR. */ | |
3030 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, | |
3031 | data->insn_addr + 4); | |
3032 | } | |
3033 | } | |
3034 | ||
3035 | /* Implementation of aarch64_insn_visitor method "b_cond". */ | |
3036 | ||
3037 | static void | |
3038 | aarch64_displaced_step_b_cond (const unsigned cond, const int32_t offset, | |
3039 | struct aarch64_insn_data *data) | |
3040 | { | |
3041 | struct aarch64_displaced_step_data *dsd | |
3042 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
3043 | |
3044 | /* GDB has to fix up PC after displaced step this instruction | |
3045 | differently according to the condition is true or false. Instead | |
3046 | of checking COND against conditional flags, we can use | |
3047 | the following instructions, and GDB can tell how to fix up PC | |
3048 | according to the PC value. | |
3049 | ||
3050 | B.COND TAKEN ; If cond is true, then jump to TAKEN. | |
3051 | INSN1 ; | |
3052 | TAKEN: | |
3053 | INSN2 | |
3054 | */ | |
3055 | ||
3056 | emit_bcond (dsd->insn_buf, cond, 8); | |
f0c702d4 | 3057 | dsd->dsc->cond = true; |
b6542f81 YQ |
3058 | dsd->dsc->pc_adjust = offset; |
3059 | dsd->insn_count = 1; | |
3060 | } | |
3061 | ||
3062 | /* Dynamically allocate a new register. If we know the register | |
3063 | statically, we should make it a global as above instead of using this | |
3064 | helper function. */ | |
3065 | ||
3066 | static struct aarch64_register | |
3067 | aarch64_register (unsigned num, int is64) | |
3068 | { | |
3069 | return (struct aarch64_register) { num, is64 }; | |
3070 | } | |
3071 | ||
3072 | /* Implementation of aarch64_insn_visitor method "cb". */ | |
3073 | ||
3074 | static void | |
3075 | aarch64_displaced_step_cb (const int32_t offset, const int is_cbnz, | |
3076 | const unsigned rn, int is64, | |
3077 | struct aarch64_insn_data *data) | |
3078 | { | |
3079 | struct aarch64_displaced_step_data *dsd | |
3080 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
3081 | |
3082 | /* The offset is out of range for a compare and branch | |
3083 | instruction. We can use the following instructions instead: | |
3084 | ||
3085 | CBZ xn, TAKEN ; xn == 0, then jump to TAKEN. | |
3086 | INSN1 ; | |
3087 | TAKEN: | |
3088 | INSN2 | |
3089 | */ | |
3090 | emit_cb (dsd->insn_buf, is_cbnz, aarch64_register (rn, is64), 8); | |
3091 | dsd->insn_count = 1; | |
f0c702d4 | 3092 | dsd->dsc->cond = true; |
b6542f81 YQ |
3093 | dsd->dsc->pc_adjust = offset; |
3094 | } | |
3095 | ||
3096 | /* Implementation of aarch64_insn_visitor method "tb". */ | |
3097 | ||
3098 | static void | |
3099 | aarch64_displaced_step_tb (const int32_t offset, int is_tbnz, | |
3100 | const unsigned rt, unsigned bit, | |
3101 | struct aarch64_insn_data *data) | |
3102 | { | |
3103 | struct aarch64_displaced_step_data *dsd | |
3104 | = (struct aarch64_displaced_step_data *) data; | |
b6542f81 YQ |
3105 | |
3106 | /* The offset is out of range for a test bit and branch | |
3107 | instruction We can use the following instructions instead: | |
3108 | ||
3109 | TBZ xn, #bit, TAKEN ; xn[bit] == 0, then jump to TAKEN. | |
3110 | INSN1 ; | |
3111 | TAKEN: | |
3112 | INSN2 | |
3113 | ||
3114 | */ | |
3115 | emit_tb (dsd->insn_buf, is_tbnz, bit, aarch64_register (rt, 1), 8); | |
3116 | dsd->insn_count = 1; | |
f0c702d4 | 3117 | dsd->dsc->cond = true; |
b6542f81 YQ |
3118 | dsd->dsc->pc_adjust = offset; |
3119 | } | |
3120 | ||
3121 | /* Implementation of aarch64_insn_visitor method "adr". */ | |
3122 | ||
3123 | static void | |
3124 | aarch64_displaced_step_adr (const int32_t offset, const unsigned rd, | |
3125 | const int is_adrp, struct aarch64_insn_data *data) | |
3126 | { | |
3127 | struct aarch64_displaced_step_data *dsd | |
3128 | = (struct aarch64_displaced_step_data *) data; | |
3129 | /* We know exactly the address the ADR{P,} instruction will compute. | |
3130 | We can just write it to the destination register. */ | |
3131 | CORE_ADDR address = data->insn_addr + offset; | |
3132 | ||
3133 | if (is_adrp) | |
3134 | { | |
3135 | /* Clear the lower 12 bits of the offset to get the 4K page. */ | |
3136 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
3137 | address & ~0xfff); | |
3138 | } | |
3139 | else | |
3140 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rd, | |
3141 | address); | |
3142 | ||
3143 | dsd->dsc->pc_adjust = 4; | |
3144 | emit_nop (dsd->insn_buf); | |
3145 | dsd->insn_count = 1; | |
3146 | } | |
3147 | ||
3148 | /* Implementation of aarch64_insn_visitor method "ldr_literal". */ | |
3149 | ||
3150 | static void | |
3151 | aarch64_displaced_step_ldr_literal (const int32_t offset, const int is_sw, | |
3152 | const unsigned rt, const int is64, | |
3153 | struct aarch64_insn_data *data) | |
3154 | { | |
3155 | struct aarch64_displaced_step_data *dsd | |
3156 | = (struct aarch64_displaced_step_data *) data; | |
3157 | CORE_ADDR address = data->insn_addr + offset; | |
3158 | struct aarch64_memory_operand zero = { MEMORY_OPERAND_OFFSET, 0 }; | |
3159 | ||
3160 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_X0_REGNUM + rt, | |
3161 | address); | |
3162 | ||
3163 | if (is_sw) | |
3164 | dsd->insn_count = emit_ldrsw (dsd->insn_buf, aarch64_register (rt, 1), | |
3165 | aarch64_register (rt, 1), zero); | |
3166 | else | |
3167 | dsd->insn_count = emit_ldr (dsd->insn_buf, aarch64_register (rt, is64), | |
3168 | aarch64_register (rt, 1), zero); | |
3169 | ||
3170 | dsd->dsc->pc_adjust = 4; | |
3171 | } | |
3172 | ||
3173 | /* Implementation of aarch64_insn_visitor method "others". */ | |
3174 | ||
3175 | static void | |
3176 | aarch64_displaced_step_others (const uint32_t insn, | |
3177 | struct aarch64_insn_data *data) | |
3178 | { | |
3179 | struct aarch64_displaced_step_data *dsd | |
3180 | = (struct aarch64_displaced_step_data *) data; | |
3181 | ||
807f647c MM |
3182 | uint32_t masked_insn = (insn & CLEAR_Rn_MASK); |
3183 | if (masked_insn == BLR) | |
b6542f81 | 3184 | { |
807f647c MM |
3185 | /* Emit a BR to the same register and then update LR to the original |
3186 | address (similar to aarch64_displaced_step_b). */ | |
3187 | aarch64_emit_insn (dsd->insn_buf, insn & 0xffdfffff); | |
3188 | regcache_cooked_write_unsigned (dsd->regs, AARCH64_LR_REGNUM, | |
3189 | data->insn_addr + 4); | |
b6542f81 | 3190 | } |
807f647c MM |
3191 | else |
3192 | aarch64_emit_insn (dsd->insn_buf, insn); | |
3193 | dsd->insn_count = 1; | |
3194 | ||
3195 | if (masked_insn == RET || masked_insn == BR || masked_insn == BLR) | |
3196 | dsd->dsc->pc_adjust = 0; | |
b6542f81 YQ |
3197 | else |
3198 | dsd->dsc->pc_adjust = 4; | |
3199 | } | |
3200 | ||
3201 | static const struct aarch64_insn_visitor visitor = | |
3202 | { | |
3203 | aarch64_displaced_step_b, | |
3204 | aarch64_displaced_step_b_cond, | |
3205 | aarch64_displaced_step_cb, | |
3206 | aarch64_displaced_step_tb, | |
3207 | aarch64_displaced_step_adr, | |
3208 | aarch64_displaced_step_ldr_literal, | |
3209 | aarch64_displaced_step_others, | |
3210 | }; | |
3211 | ||
3212 | /* Implement the "displaced_step_copy_insn" gdbarch method. */ | |
3213 | ||
1152d984 | 3214 | displaced_step_copy_insn_closure_up |
b6542f81 YQ |
3215 | aarch64_displaced_step_copy_insn (struct gdbarch *gdbarch, |
3216 | CORE_ADDR from, CORE_ADDR to, | |
3217 | struct regcache *regs) | |
3218 | { | |
b6542f81 YQ |
3219 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); |
3220 | uint32_t insn = read_memory_unsigned_integer (from, 4, byte_order_for_code); | |
3221 | struct aarch64_displaced_step_data dsd; | |
c86a40c6 YQ |
3222 | aarch64_inst inst; |
3223 | ||
561a72d4 | 3224 | if (aarch64_decode_insn (insn, &inst, 1, NULL) != 0) |
c86a40c6 | 3225 | return NULL; |
b6542f81 YQ |
3226 | |
3227 | /* Look for a Load Exclusive instruction which begins the sequence. */ | |
c86a40c6 | 3228 | if (inst.opcode->iclass == ldstexcl && bit (insn, 22)) |
b6542f81 YQ |
3229 | { |
3230 | /* We can't displaced step atomic sequences. */ | |
3231 | return NULL; | |
3232 | } | |
3233 | ||
1152d984 SM |
3234 | std::unique_ptr<aarch64_displaced_step_copy_insn_closure> dsc |
3235 | (new aarch64_displaced_step_copy_insn_closure); | |
b6542f81 YQ |
3236 | dsd.base.insn_addr = from; |
3237 | dsd.new_addr = to; | |
3238 | dsd.regs = regs; | |
cfba9872 | 3239 | dsd.dsc = dsc.get (); |
034f1a81 | 3240 | dsd.insn_count = 0; |
b6542f81 YQ |
3241 | aarch64_relocate_instruction (insn, &visitor, |
3242 | (struct aarch64_insn_data *) &dsd); | |
e935475c | 3243 | gdb_assert (dsd.insn_count <= AARCH64_DISPLACED_MODIFIED_INSNS); |
b6542f81 YQ |
3244 | |
3245 | if (dsd.insn_count != 0) | |
3246 | { | |
3247 | int i; | |
3248 | ||
3249 | /* Instruction can be relocated to scratch pad. Copy | |
3250 | relocated instruction(s) there. */ | |
3251 | for (i = 0; i < dsd.insn_count; i++) | |
3252 | { | |
136821d9 SM |
3253 | displaced_debug_printf ("writing insn %.8x at %s", |
3254 | dsd.insn_buf[i], | |
3255 | paddress (gdbarch, to + i * 4)); | |
3256 | ||
b6542f81 YQ |
3257 | write_memory_unsigned_integer (to + i * 4, 4, byte_order_for_code, |
3258 | (ULONGEST) dsd.insn_buf[i]); | |
3259 | } | |
3260 | } | |
3261 | else | |
3262 | { | |
b6542f81 YQ |
3263 | dsc = NULL; |
3264 | } | |
3265 | ||
6d0cf446 | 3266 | /* This is a work around for a problem with g++ 4.8. */ |
1152d984 | 3267 | return displaced_step_copy_insn_closure_up (dsc.release ()); |
b6542f81 YQ |
3268 | } |
3269 | ||
3270 | /* Implement the "displaced_step_fixup" gdbarch method. */ | |
3271 | ||
3272 | void | |
3273 | aarch64_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 3274 | struct displaced_step_copy_insn_closure *dsc_, |
b6542f81 YQ |
3275 | CORE_ADDR from, CORE_ADDR to, |
3276 | struct regcache *regs) | |
3277 | { | |
1152d984 SM |
3278 | aarch64_displaced_step_copy_insn_closure *dsc |
3279 | = (aarch64_displaced_step_copy_insn_closure *) dsc_; | |
cfba9872 | 3280 | |
0c271889 LM |
3281 | ULONGEST pc; |
3282 | ||
3283 | regcache_cooked_read_unsigned (regs, AARCH64_PC_REGNUM, &pc); | |
3284 | ||
136821d9 SM |
3285 | displaced_debug_printf ("PC after stepping: %s (was %s).", |
3286 | paddress (gdbarch, pc), paddress (gdbarch, to)); | |
1ab139e5 | 3287 | |
b6542f81 YQ |
3288 | if (dsc->cond) |
3289 | { | |
136821d9 SM |
3290 | displaced_debug_printf ("[Conditional] pc_adjust before: %d", |
3291 | dsc->pc_adjust); | |
1ab139e5 | 3292 | |
b6542f81 YQ |
3293 | if (pc - to == 8) |
3294 | { | |
3295 | /* Condition is true. */ | |
3296 | } | |
3297 | else if (pc - to == 4) | |
3298 | { | |
3299 | /* Condition is false. */ | |
3300 | dsc->pc_adjust = 4; | |
3301 | } | |
3302 | else | |
3303 | gdb_assert_not_reached ("Unexpected PC value after displaced stepping"); | |
1ab139e5 | 3304 | |
136821d9 SM |
3305 | displaced_debug_printf ("[Conditional] pc_adjust after: %d", |
3306 | dsc->pc_adjust); | |
b6542f81 YQ |
3307 | } |
3308 | ||
136821d9 SM |
3309 | displaced_debug_printf ("%s PC by %d", |
3310 | dsc->pc_adjust ? "adjusting" : "not adjusting", | |
3311 | dsc->pc_adjust); | |
1ab139e5 | 3312 | |
b6542f81 YQ |
3313 | if (dsc->pc_adjust != 0) |
3314 | { | |
0c271889 LM |
3315 | /* Make sure the previous instruction was executed (that is, the PC |
3316 | has changed). If the PC didn't change, then discard the adjustment | |
3317 | offset. Otherwise we may skip an instruction before its execution | |
3318 | took place. */ | |
3319 | if ((pc - to) == 0) | |
1ab139e5 | 3320 | { |
136821d9 | 3321 | displaced_debug_printf ("PC did not move. Discarding PC adjustment."); |
1ab139e5 LM |
3322 | dsc->pc_adjust = 0; |
3323 | } | |
0c271889 | 3324 | |
136821d9 SM |
3325 | displaced_debug_printf ("fixup: set PC to %s:%d", |
3326 | paddress (gdbarch, from), dsc->pc_adjust); | |
3327 | ||
b6542f81 YQ |
3328 | regcache_cooked_write_unsigned (regs, AARCH64_PC_REGNUM, |
3329 | from + dsc->pc_adjust); | |
3330 | } | |
3331 | } | |
3332 | ||
3333 | /* Implement the "displaced_step_hw_singlestep" gdbarch method. */ | |
3334 | ||
07fbbd01 | 3335 | bool |
40a53766 | 3336 | aarch64_displaced_step_hw_singlestep (struct gdbarch *gdbarch) |
b6542f81 | 3337 | { |
07fbbd01 | 3338 | return true; |
b6542f81 YQ |
3339 | } |
3340 | ||
95228a0d AH |
3341 | /* Get the correct target description for the given VQ value. |
3342 | If VQ is zero then it is assumed SVE is not supported. | |
c1bd443b LM |
3343 | (It is not possible to set VQ to zero on an SVE system). |
3344 | ||
414d5848 JB |
3345 | MTE_P indicates the presence of the Memory Tagging Extension feature. |
3346 | ||
3347 | TLS_P indicates the presence of the Thread Local Storage feature. */ | |
da434ccb AH |
3348 | |
3349 | const target_desc * | |
0ee6b1c5 | 3350 | aarch64_read_description (const aarch64_features &features) |
da434ccb | 3351 | { |
0ee6b1c5 JB |
3352 | if (features.vq > AARCH64_MAX_SVE_VQ) |
3353 | error (_("VQ is %" PRIu64 ", maximum supported value is %d"), features.vq, | |
95228a0d AH |
3354 | AARCH64_MAX_SVE_VQ); |
3355 | ||
0ee6b1c5 | 3356 | struct target_desc *tdesc = tdesc_aarch64_map[features]; |
da434ccb | 3357 | |
95228a0d AH |
3358 | if (tdesc == NULL) |
3359 | { | |
0ee6b1c5 JB |
3360 | tdesc = aarch64_create_target_description (features); |
3361 | tdesc_aarch64_map[features] = tdesc; | |
95228a0d | 3362 | } |
da434ccb | 3363 | |
95228a0d | 3364 | return tdesc; |
da434ccb AH |
3365 | } |
3366 | ||
ba2d2bb2 AH |
3367 | /* Return the VQ used when creating the target description TDESC. */ |
3368 | ||
1332a140 | 3369 | static uint64_t |
ba2d2bb2 AH |
3370 | aarch64_get_tdesc_vq (const struct target_desc *tdesc) |
3371 | { | |
3372 | const struct tdesc_feature *feature_sve; | |
3373 | ||
3374 | if (!tdesc_has_registers (tdesc)) | |
3375 | return 0; | |
3376 | ||
3377 | feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); | |
3378 | ||
3379 | if (feature_sve == nullptr) | |
3380 | return 0; | |
3381 | ||
12863263 AH |
3382 | uint64_t vl = tdesc_register_bitsize (feature_sve, |
3383 | aarch64_sve_register_names[0]) / 8; | |
ba2d2bb2 AH |
3384 | return sve_vq_from_vl (vl); |
3385 | } | |
3386 | ||
4f3681cc TJB |
3387 | /* Get the AArch64 features present in the given target description. */ |
3388 | ||
3389 | aarch64_features | |
3390 | aarch64_features_from_target_desc (const struct target_desc *tdesc) | |
3391 | { | |
3392 | aarch64_features features; | |
3393 | ||
3394 | if (tdesc == nullptr) | |
3395 | return features; | |
3396 | ||
3397 | features.vq = aarch64_get_tdesc_vq (tdesc); | |
3398 | features.pauth | |
3399 | = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth") != nullptr); | |
3400 | features.mte | |
3401 | = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.mte") != nullptr); | |
3402 | features.tls | |
3403 | = (tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.tls") != nullptr); | |
3404 | ||
3405 | return features; | |
3406 | } | |
3407 | ||
76bed0fd AH |
3408 | /* Implement the "cannot_store_register" gdbarch method. */ |
3409 | ||
3410 | static int | |
3411 | aarch64_cannot_store_register (struct gdbarch *gdbarch, int regnum) | |
3412 | { | |
08106042 | 3413 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
76bed0fd AH |
3414 | |
3415 | if (!tdep->has_pauth ()) | |
3416 | return 0; | |
3417 | ||
3418 | /* Pointer authentication registers are read-only. */ | |
3419 | return (regnum == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base) | |
3420 | || regnum == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)); | |
3421 | } | |
3422 | ||
da729c5c TT |
3423 | /* Implement the stack_frame_destroyed_p gdbarch method. */ |
3424 | ||
3425 | static int | |
3426 | aarch64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) | |
3427 | { | |
3428 | CORE_ADDR func_start, func_end; | |
3429 | if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) | |
3430 | return 0; | |
3431 | ||
3432 | enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); | |
3433 | uint32_t insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); | |
3434 | ||
3435 | aarch64_inst inst; | |
3436 | if (aarch64_decode_insn (insn, &inst, 1, nullptr) != 0) | |
3437 | return 0; | |
3438 | ||
3439 | return streq (inst.opcode->name, "ret"); | |
3440 | } | |
3441 | ||
07b287a0 MS |
3442 | /* Initialize the current architecture based on INFO. If possible, |
3443 | re-use an architecture from ARCHES, which is a list of | |
3444 | architectures already created during this debugging session. | |
3445 | ||
3446 | Called e.g. at program startup, when reading a core file, and when | |
3447 | reading a binary file. */ | |
3448 | ||
3449 | static struct gdbarch * | |
3450 | aarch64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3451 | { | |
ccb8d7e8 | 3452 | const struct tdesc_feature *feature_core, *feature_fpu, *feature_sve; |
76bed0fd | 3453 | const struct tdesc_feature *feature_pauth; |
ccb8d7e8 AH |
3454 | bool valid_p = true; |
3455 | int i, num_regs = 0, num_pseudo_regs = 0; | |
c9cd8ca4 | 3456 | int first_pauth_regnum = -1, ra_sign_state_offset = -1; |
414d5848 | 3457 | int first_mte_regnum = -1, tls_regnum = -1; |
4f3681cc | 3458 | uint64_t vq = aarch64_get_tdesc_vq (info.target_desc); |
4da037ef AH |
3459 | |
3460 | if (vq > AARCH64_MAX_SVE_VQ) | |
596179f7 SDJ |
3461 | internal_error (__FILE__, __LINE__, _("VQ out of bounds: %s (max %d)"), |
3462 | pulongest (vq), AARCH64_MAX_SVE_VQ); | |
4da037ef | 3463 | |
ccb8d7e8 AH |
3464 | /* If there is already a candidate, use it. */ |
3465 | for (gdbarch_list *best_arch = gdbarch_list_lookup_by_info (arches, &info); | |
3466 | best_arch != nullptr; | |
3467 | best_arch = gdbarch_list_lookup_by_info (best_arch->next, &info)) | |
3468 | { | |
345bd07c | 3469 | aarch64_gdbarch_tdep *tdep |
08106042 | 3470 | = gdbarch_tdep<aarch64_gdbarch_tdep> (best_arch->gdbarch); |
4da037ef | 3471 | if (tdep && tdep->vq == vq) |
ccb8d7e8 AH |
3472 | return best_arch->gdbarch; |
3473 | } | |
07b287a0 | 3474 | |
4da037ef AH |
3475 | /* Ensure we always have a target descriptor, and that it is for the given VQ |
3476 | value. */ | |
ccb8d7e8 | 3477 | const struct target_desc *tdesc = info.target_desc; |
4f3681cc TJB |
3478 | if (!tdesc_has_registers (tdesc)) |
3479 | tdesc = aarch64_read_description ({}); | |
07b287a0 MS |
3480 | gdb_assert (tdesc); |
3481 | ||
ccb8d7e8 | 3482 | feature_core = tdesc_find_feature (tdesc,"org.gnu.gdb.aarch64.core"); |
ba2d2bb2 AH |
3483 | feature_fpu = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.fpu"); |
3484 | feature_sve = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.sve"); | |
76bed0fd | 3485 | feature_pauth = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.pauth"); |
5e984dbf LM |
3486 | const struct tdesc_feature *feature_mte |
3487 | = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.mte"); | |
414d5848 JB |
3488 | const struct tdesc_feature *feature_tls |
3489 | = tdesc_find_feature (tdesc, "org.gnu.gdb.aarch64.tls"); | |
07b287a0 | 3490 | |
ccb8d7e8 AH |
3491 | if (feature_core == nullptr) |
3492 | return nullptr; | |
07b287a0 | 3493 | |
c1e1314d | 3494 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
07b287a0 | 3495 | |
ba2d2bb2 | 3496 | /* Validate the description provides the mandatory core R registers |
07b287a0 MS |
3497 | and allocate their numbers. */ |
3498 | for (i = 0; i < ARRAY_SIZE (aarch64_r_register_names); i++) | |
c1e1314d | 3499 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data.get (), |
ba2d2bb2 AH |
3500 | AARCH64_X0_REGNUM + i, |
3501 | aarch64_r_register_names[i]); | |
07b287a0 MS |
3502 | |
3503 | num_regs = AARCH64_X0_REGNUM + i; | |
3504 | ||
ba2d2bb2 | 3505 | /* Add the V registers. */ |
ccb8d7e8 | 3506 | if (feature_fpu != nullptr) |
07b287a0 | 3507 | { |
ccb8d7e8 | 3508 | if (feature_sve != nullptr) |
ba2d2bb2 AH |
3509 | error (_("Program contains both fpu and SVE features.")); |
3510 | ||
3511 | /* Validate the description provides the mandatory V registers | |
3512 | and allocate their numbers. */ | |
07b287a0 | 3513 | for (i = 0; i < ARRAY_SIZE (aarch64_v_register_names); i++) |
c1e1314d | 3514 | valid_p &= tdesc_numbered_register (feature_fpu, tdesc_data.get (), |
ba2d2bb2 AH |
3515 | AARCH64_V0_REGNUM + i, |
3516 | aarch64_v_register_names[i]); | |
07b287a0 MS |
3517 | |
3518 | num_regs = AARCH64_V0_REGNUM + i; | |
ba2d2bb2 | 3519 | } |
07b287a0 | 3520 | |
ba2d2bb2 | 3521 | /* Add the SVE registers. */ |
ccb8d7e8 | 3522 | if (feature_sve != nullptr) |
ba2d2bb2 AH |
3523 | { |
3524 | /* Validate the description provides the mandatory SVE registers | |
3525 | and allocate their numbers. */ | |
3526 | for (i = 0; i < ARRAY_SIZE (aarch64_sve_register_names); i++) | |
c1e1314d | 3527 | valid_p &= tdesc_numbered_register (feature_sve, tdesc_data.get (), |
ba2d2bb2 AH |
3528 | AARCH64_SVE_Z0_REGNUM + i, |
3529 | aarch64_sve_register_names[i]); | |
3530 | ||
3531 | num_regs = AARCH64_SVE_Z0_REGNUM + i; | |
3532 | num_pseudo_regs += 32; /* add the Vn register pseudos. */ | |
3533 | } | |
3534 | ||
ccb8d7e8 | 3535 | if (feature_fpu != nullptr || feature_sve != nullptr) |
ba2d2bb2 | 3536 | { |
07b287a0 MS |
3537 | num_pseudo_regs += 32; /* add the Qn scalar register pseudos */ |
3538 | num_pseudo_regs += 32; /* add the Dn scalar register pseudos */ | |
3539 | num_pseudo_regs += 32; /* add the Sn scalar register pseudos */ | |
3540 | num_pseudo_regs += 32; /* add the Hn scalar register pseudos */ | |
3541 | num_pseudo_regs += 32; /* add the Bn scalar register pseudos */ | |
3542 | } | |
3543 | ||
414d5848 JB |
3544 | /* Add the TLS register. */ |
3545 | if (feature_tls != nullptr) | |
3546 | { | |
3547 | tls_regnum = num_regs; | |
3548 | /* Validate the descriptor provides the mandatory TLS register | |
3549 | and allocate its number. */ | |
3550 | valid_p = tdesc_numbered_register (feature_tls, tdesc_data.get (), | |
3551 | tls_regnum, "tpidr"); | |
3552 | ||
3553 | num_regs++; | |
3554 | } | |
3555 | ||
76bed0fd AH |
3556 | /* Add the pauth registers. */ |
3557 | if (feature_pauth != NULL) | |
3558 | { | |
3559 | first_pauth_regnum = num_regs; | |
c9cd8ca4 | 3560 | ra_sign_state_offset = num_pseudo_regs; |
76bed0fd AH |
3561 | /* Validate the descriptor provides the mandatory PAUTH registers and |
3562 | allocate their numbers. */ | |
3563 | for (i = 0; i < ARRAY_SIZE (aarch64_pauth_register_names); i++) | |
c1e1314d | 3564 | valid_p &= tdesc_numbered_register (feature_pauth, tdesc_data.get (), |
76bed0fd AH |
3565 | first_pauth_regnum + i, |
3566 | aarch64_pauth_register_names[i]); | |
3567 | ||
3568 | num_regs += i; | |
34dcc7cf | 3569 | num_pseudo_regs += 1; /* Count RA_STATE pseudo register. */ |
76bed0fd AH |
3570 | } |
3571 | ||
5e984dbf LM |
3572 | /* Add the MTE registers. */ |
3573 | if (feature_mte != NULL) | |
3574 | { | |
3575 | first_mte_regnum = num_regs; | |
3576 | /* Validate the descriptor provides the mandatory MTE registers and | |
3577 | allocate their numbers. */ | |
3578 | for (i = 0; i < ARRAY_SIZE (aarch64_mte_register_names); i++) | |
3579 | valid_p &= tdesc_numbered_register (feature_mte, tdesc_data.get (), | |
3580 | first_mte_regnum + i, | |
3581 | aarch64_mte_register_names[i]); | |
3582 | ||
3583 | num_regs += i; | |
3584 | } | |
3585 | ||
07b287a0 | 3586 | if (!valid_p) |
c1e1314d | 3587 | return nullptr; |
07b287a0 MS |
3588 | |
3589 | /* AArch64 code is always little-endian. */ | |
3590 | info.byte_order_for_code = BFD_ENDIAN_LITTLE; | |
3591 | ||
345bd07c | 3592 | aarch64_gdbarch_tdep *tdep = new aarch64_gdbarch_tdep; |
ccb8d7e8 | 3593 | struct gdbarch *gdbarch = gdbarch_alloc (&info, tdep); |
07b287a0 MS |
3594 | |
3595 | /* This should be low enough for everything. */ | |
3596 | tdep->lowest_pc = 0x20; | |
3597 | tdep->jb_pc = -1; /* Longjump support not enabled by default. */ | |
3598 | tdep->jb_elt_size = 8; | |
4da037ef | 3599 | tdep->vq = vq; |
76bed0fd | 3600 | tdep->pauth_reg_base = first_pauth_regnum; |
c9cd8ca4 LM |
3601 | tdep->ra_sign_state_regnum = (feature_pauth == NULL) ? -1 |
3602 | : ra_sign_state_offset + num_regs; | |
5e984dbf | 3603 | tdep->mte_reg_base = first_mte_regnum; |
414d5848 | 3604 | tdep->tls_regnum = tls_regnum; |
34dcc7cf | 3605 | |
07b287a0 MS |
3606 | set_gdbarch_push_dummy_call (gdbarch, aarch64_push_dummy_call); |
3607 | set_gdbarch_frame_align (gdbarch, aarch64_frame_align); | |
3608 | ||
07b287a0 MS |
3609 | /* Advance PC across function entry code. */ |
3610 | set_gdbarch_skip_prologue (gdbarch, aarch64_skip_prologue); | |
3611 | ||
3612 | /* The stack grows downward. */ | |
3613 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
3614 | ||
3615 | /* Breakpoint manipulation. */ | |
04180708 YQ |
3616 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
3617 | aarch64_breakpoint::kind_from_pc); | |
3618 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
3619 | aarch64_breakpoint::bp_from_kind); | |
07b287a0 | 3620 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
9404b58f | 3621 | set_gdbarch_software_single_step (gdbarch, aarch64_software_single_step); |
07b287a0 MS |
3622 | |
3623 | /* Information about registers, etc. */ | |
3624 | set_gdbarch_sp_regnum (gdbarch, AARCH64_SP_REGNUM); | |
3625 | set_gdbarch_pc_regnum (gdbarch, AARCH64_PC_REGNUM); | |
3626 | set_gdbarch_num_regs (gdbarch, num_regs); | |
3627 | ||
3628 | set_gdbarch_num_pseudo_regs (gdbarch, num_pseudo_regs); | |
3629 | set_gdbarch_pseudo_register_read_value (gdbarch, aarch64_pseudo_read_value); | |
3630 | set_gdbarch_pseudo_register_write (gdbarch, aarch64_pseudo_write); | |
3631 | set_tdesc_pseudo_register_name (gdbarch, aarch64_pseudo_register_name); | |
3632 | set_tdesc_pseudo_register_type (gdbarch, aarch64_pseudo_register_type); | |
3633 | set_tdesc_pseudo_register_reggroup_p (gdbarch, | |
3634 | aarch64_pseudo_register_reggroup_p); | |
76bed0fd | 3635 | set_gdbarch_cannot_store_register (gdbarch, aarch64_cannot_store_register); |
07b287a0 MS |
3636 | |
3637 | /* ABI */ | |
3638 | set_gdbarch_short_bit (gdbarch, 16); | |
3639 | set_gdbarch_int_bit (gdbarch, 32); | |
3640 | set_gdbarch_float_bit (gdbarch, 32); | |
3641 | set_gdbarch_double_bit (gdbarch, 64); | |
3642 | set_gdbarch_long_double_bit (gdbarch, 128); | |
3643 | set_gdbarch_long_bit (gdbarch, 64); | |
3644 | set_gdbarch_long_long_bit (gdbarch, 64); | |
3645 | set_gdbarch_ptr_bit (gdbarch, 64); | |
3646 | set_gdbarch_char_signed (gdbarch, 0); | |
53375380 | 3647 | set_gdbarch_wchar_signed (gdbarch, 0); |
07b287a0 MS |
3648 | set_gdbarch_float_format (gdbarch, floatformats_ieee_single); |
3649 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
552f1157 | 3650 | set_gdbarch_long_double_format (gdbarch, floatformats_ieee_quad); |
b907456c | 3651 | set_gdbarch_type_align (gdbarch, aarch64_type_align); |
07b287a0 | 3652 | |
da729c5c TT |
3653 | /* Detect whether PC is at a point where the stack has been destroyed. */ |
3654 | set_gdbarch_stack_frame_destroyed_p (gdbarch, aarch64_stack_frame_destroyed_p); | |
3655 | ||
07b287a0 MS |
3656 | /* Internal <-> external register number maps. */ |
3657 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, aarch64_dwarf_reg_to_regnum); | |
3658 | ||
3659 | /* Returning results. */ | |
3660 | set_gdbarch_return_value (gdbarch, aarch64_return_value); | |
3661 | ||
3662 | /* Disassembly. */ | |
3663 | set_gdbarch_print_insn (gdbarch, aarch64_gdb_print_insn); | |
3664 | ||
3665 | /* Virtual tables. */ | |
3666 | set_gdbarch_vbit_in_delta (gdbarch, 1); | |
3667 | ||
3668 | /* Hook in the ABI-specific overrides, if they have been registered. */ | |
3669 | info.target_desc = tdesc; | |
c1e1314d | 3670 | info.tdesc_data = tdesc_data.get (); |
07b287a0 MS |
3671 | gdbarch_init_osabi (info, gdbarch); |
3672 | ||
3673 | dwarf2_frame_set_init_reg (gdbarch, aarch64_dwarf2_frame_init_reg); | |
11e1b75f AH |
3674 | /* Register DWARF CFA vendor handler. */ |
3675 | set_gdbarch_execute_dwarf_cfa_vendor_op (gdbarch, | |
3676 | aarch64_execute_dwarf_cfa_vendor_op); | |
07b287a0 | 3677 | |
5133a315 LM |
3678 | /* Permanent/Program breakpoint handling. */ |
3679 | set_gdbarch_program_breakpoint_here_p (gdbarch, | |
3680 | aarch64_program_breakpoint_here_p); | |
3681 | ||
07b287a0 MS |
3682 | /* Add some default predicates. */ |
3683 | frame_unwind_append_unwinder (gdbarch, &aarch64_stub_unwind); | |
3684 | dwarf2_append_unwinders (gdbarch); | |
3685 | frame_unwind_append_unwinder (gdbarch, &aarch64_prologue_unwind); | |
3686 | ||
3687 | frame_base_set_default (gdbarch, &aarch64_normal_base); | |
3688 | ||
3689 | /* Now we have tuned the configuration, set a few final things, | |
3690 | based on what the OS ABI has told us. */ | |
3691 | ||
3692 | if (tdep->jb_pc >= 0) | |
3693 | set_gdbarch_get_longjmp_target (gdbarch, aarch64_get_longjmp_target); | |
3694 | ||
ea873d8e PL |
3695 | set_gdbarch_gen_return_address (gdbarch, aarch64_gen_return_address); |
3696 | ||
aa7ca1bb AH |
3697 | set_gdbarch_get_pc_address_flags (gdbarch, aarch64_get_pc_address_flags); |
3698 | ||
c1e1314d | 3699 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
07b287a0 MS |
3700 | |
3701 | /* Add standard register aliases. */ | |
3702 | for (i = 0; i < ARRAY_SIZE (aarch64_register_aliases); i++) | |
3703 | user_reg_add (gdbarch, aarch64_register_aliases[i].name, | |
3704 | value_of_aarch64_user_reg, | |
3705 | &aarch64_register_aliases[i].regnum); | |
3706 | ||
e8bf1ce4 JB |
3707 | register_aarch64_ravenscar_ops (gdbarch); |
3708 | ||
07b287a0 MS |
3709 | return gdbarch; |
3710 | } | |
3711 | ||
3712 | static void | |
3713 | aarch64_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3714 | { | |
08106042 | 3715 | aarch64_gdbarch_tdep *tdep = gdbarch_tdep<aarch64_gdbarch_tdep> (gdbarch); |
07b287a0 MS |
3716 | |
3717 | if (tdep == NULL) | |
3718 | return; | |
3719 | ||
6cb06a8c TT |
3720 | gdb_printf (file, _("aarch64_dump_tdep: Lowest pc = 0x%s"), |
3721 | paddress (gdbarch, tdep->lowest_pc)); | |
07b287a0 MS |
3722 | } |
3723 | ||
0d4c07af | 3724 | #if GDB_SELF_TEST |
1e2b521d YQ |
3725 | namespace selftests |
3726 | { | |
3727 | static void aarch64_process_record_test (void); | |
3728 | } | |
0d4c07af | 3729 | #endif |
1e2b521d | 3730 | |
6c265988 | 3731 | void _initialize_aarch64_tdep (); |
07b287a0 | 3732 | void |
6c265988 | 3733 | _initialize_aarch64_tdep () |
07b287a0 MS |
3734 | { |
3735 | gdbarch_register (bfd_arch_aarch64, aarch64_gdbarch_init, | |
3736 | aarch64_dump_tdep); | |
3737 | ||
07b287a0 MS |
3738 | /* Debug this file's internals. */ |
3739 | add_setshow_boolean_cmd ("aarch64", class_maintenance, &aarch64_debug, _("\ | |
3740 | Set AArch64 debugging."), _("\ | |
3741 | Show AArch64 debugging."), _("\ | |
3742 | When on, AArch64 specific debugging is enabled."), | |
3743 | NULL, | |
3744 | show_aarch64_debug, | |
3745 | &setdebuglist, &showdebuglist); | |
4d9a9006 YQ |
3746 | |
3747 | #if GDB_SELF_TEST | |
1526853e SM |
3748 | selftests::register_test ("aarch64-analyze-prologue", |
3749 | selftests::aarch64_analyze_prologue_test); | |
3750 | selftests::register_test ("aarch64-process-record", | |
3751 | selftests::aarch64_process_record_test); | |
4d9a9006 | 3752 | #endif |
07b287a0 | 3753 | } |
99afc88b OJ |
3754 | |
3755 | /* AArch64 process record-replay related structures, defines etc. */ | |
3756 | ||
99afc88b | 3757 | #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ |
dda83cd7 SM |
3758 | do \ |
3759 | { \ | |
3760 | unsigned int reg_len = LENGTH; \ | |
3761 | if (reg_len) \ | |
3762 | { \ | |
3763 | REGS = XNEWVEC (uint32_t, reg_len); \ | |
3764 | memcpy(®S[0], &RECORD_BUF[0], sizeof(uint32_t)*LENGTH); \ | |
3765 | } \ | |
3766 | } \ | |
3767 | while (0) | |
99afc88b OJ |
3768 | |
3769 | #define MEM_ALLOC(MEMS, LENGTH, RECORD_BUF) \ | |
dda83cd7 SM |
3770 | do \ |
3771 | { \ | |
3772 | unsigned int mem_len = LENGTH; \ | |
3773 | if (mem_len) \ | |
01add95b SM |
3774 | { \ |
3775 | MEMS = XNEWVEC (struct aarch64_mem_r, mem_len); \ | |
91ddba83 | 3776 | memcpy(MEMS, &RECORD_BUF[0], \ |
01add95b SM |
3777 | sizeof(struct aarch64_mem_r) * LENGTH); \ |
3778 | } \ | |
dda83cd7 SM |
3779 | } \ |
3780 | while (0) | |
99afc88b OJ |
3781 | |
3782 | /* AArch64 record/replay structures and enumerations. */ | |
3783 | ||
3784 | struct aarch64_mem_r | |
3785 | { | |
3786 | uint64_t len; /* Record length. */ | |
3787 | uint64_t addr; /* Memory address. */ | |
3788 | }; | |
3789 | ||
3790 | enum aarch64_record_result | |
3791 | { | |
3792 | AARCH64_RECORD_SUCCESS, | |
99afc88b OJ |
3793 | AARCH64_RECORD_UNSUPPORTED, |
3794 | AARCH64_RECORD_UNKNOWN | |
3795 | }; | |
3796 | ||
4748a9be | 3797 | struct aarch64_insn_decode_record |
99afc88b OJ |
3798 | { |
3799 | struct gdbarch *gdbarch; | |
3800 | struct regcache *regcache; | |
3801 | CORE_ADDR this_addr; /* Address of insn to be recorded. */ | |
3802 | uint32_t aarch64_insn; /* Insn to be recorded. */ | |
3803 | uint32_t mem_rec_count; /* Count of memory records. */ | |
3804 | uint32_t reg_rec_count; /* Count of register records. */ | |
3805 | uint32_t *aarch64_regs; /* Registers to be recorded. */ | |
3806 | struct aarch64_mem_r *aarch64_mems; /* Memory locations to be recorded. */ | |
4748a9be | 3807 | }; |
99afc88b OJ |
3808 | |
3809 | /* Record handler for data processing - register instructions. */ | |
3810 | ||
3811 | static unsigned int | |
4748a9be | 3812 | aarch64_record_data_proc_reg (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
3813 | { |
3814 | uint8_t reg_rd, insn_bits24_27, insn_bits21_23; | |
3815 | uint32_t record_buf[4]; | |
3816 | ||
3817 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3818 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3819 | insn_bits21_23 = bits (aarch64_insn_r->aarch64_insn, 21, 23); | |
3820 | ||
3821 | if (!bit (aarch64_insn_r->aarch64_insn, 28)) | |
3822 | { | |
3823 | uint8_t setflags; | |
3824 | ||
3825 | /* Logical (shifted register). */ | |
3826 | if (insn_bits24_27 == 0x0a) | |
3827 | setflags = (bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03); | |
3828 | /* Add/subtract. */ | |
3829 | else if (insn_bits24_27 == 0x0b) | |
3830 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3831 | else | |
3832 | return AARCH64_RECORD_UNKNOWN; | |
3833 | ||
3834 | record_buf[0] = reg_rd; | |
3835 | aarch64_insn_r->reg_rec_count = 1; | |
3836 | if (setflags) | |
3837 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3838 | } | |
3839 | else | |
3840 | { | |
3841 | if (insn_bits24_27 == 0x0b) | |
3842 | { | |
3843 | /* Data-processing (3 source). */ | |
3844 | record_buf[0] = reg_rd; | |
3845 | aarch64_insn_r->reg_rec_count = 1; | |
3846 | } | |
3847 | else if (insn_bits24_27 == 0x0a) | |
3848 | { | |
3849 | if (insn_bits21_23 == 0x00) | |
3850 | { | |
3851 | /* Add/subtract (with carry). */ | |
3852 | record_buf[0] = reg_rd; | |
3853 | aarch64_insn_r->reg_rec_count = 1; | |
3854 | if (bit (aarch64_insn_r->aarch64_insn, 29)) | |
3855 | { | |
3856 | record_buf[1] = AARCH64_CPSR_REGNUM; | |
3857 | aarch64_insn_r->reg_rec_count = 2; | |
3858 | } | |
3859 | } | |
3860 | else if (insn_bits21_23 == 0x02) | |
3861 | { | |
3862 | /* Conditional compare (register) and conditional compare | |
3863 | (immediate) instructions. */ | |
3864 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3865 | aarch64_insn_r->reg_rec_count = 1; | |
3866 | } | |
3867 | else if (insn_bits21_23 == 0x04 || insn_bits21_23 == 0x06) | |
3868 | { | |
85102364 | 3869 | /* Conditional select. */ |
99afc88b OJ |
3870 | /* Data-processing (2 source). */ |
3871 | /* Data-processing (1 source). */ | |
3872 | record_buf[0] = reg_rd; | |
3873 | aarch64_insn_r->reg_rec_count = 1; | |
3874 | } | |
3875 | else | |
3876 | return AARCH64_RECORD_UNKNOWN; | |
3877 | } | |
3878 | } | |
3879 | ||
3880 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3881 | record_buf); | |
3882 | return AARCH64_RECORD_SUCCESS; | |
3883 | } | |
3884 | ||
3885 | /* Record handler for data processing - immediate instructions. */ | |
3886 | ||
3887 | static unsigned int | |
4748a9be | 3888 | aarch64_record_data_proc_imm (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b | 3889 | { |
78cc6c2d | 3890 | uint8_t reg_rd, insn_bit23, insn_bits24_27, setflags; |
99afc88b OJ |
3891 | uint32_t record_buf[4]; |
3892 | ||
3893 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
99afc88b OJ |
3894 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); |
3895 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3896 | ||
3897 | if (insn_bits24_27 == 0x00 /* PC rel addressing. */ | |
3898 | || insn_bits24_27 == 0x03 /* Bitfield and Extract. */ | |
3899 | || (insn_bits24_27 == 0x02 && insn_bit23)) /* Move wide (immediate). */ | |
3900 | { | |
3901 | record_buf[0] = reg_rd; | |
3902 | aarch64_insn_r->reg_rec_count = 1; | |
3903 | } | |
3904 | else if (insn_bits24_27 == 0x01) | |
3905 | { | |
3906 | /* Add/Subtract (immediate). */ | |
3907 | setflags = bit (aarch64_insn_r->aarch64_insn, 29); | |
3908 | record_buf[0] = reg_rd; | |
3909 | aarch64_insn_r->reg_rec_count = 1; | |
3910 | if (setflags) | |
3911 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3912 | } | |
3913 | else if (insn_bits24_27 == 0x02 && !insn_bit23) | |
3914 | { | |
3915 | /* Logical (immediate). */ | |
3916 | setflags = bits (aarch64_insn_r->aarch64_insn, 29, 30) == 0x03; | |
3917 | record_buf[0] = reg_rd; | |
3918 | aarch64_insn_r->reg_rec_count = 1; | |
3919 | if (setflags) | |
3920 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_CPSR_REGNUM; | |
3921 | } | |
3922 | else | |
3923 | return AARCH64_RECORD_UNKNOWN; | |
3924 | ||
3925 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
3926 | record_buf); | |
3927 | return AARCH64_RECORD_SUCCESS; | |
3928 | } | |
3929 | ||
3930 | /* Record handler for branch, exception generation and system instructions. */ | |
3931 | ||
3932 | static unsigned int | |
4748a9be | 3933 | aarch64_record_branch_except_sys (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b | 3934 | { |
345bd07c SM |
3935 | |
3936 | aarch64_gdbarch_tdep *tdep | |
08106042 | 3937 | = gdbarch_tdep<aarch64_gdbarch_tdep> (aarch64_insn_r->gdbarch); |
99afc88b OJ |
3938 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits22_23; |
3939 | uint32_t record_buf[4]; | |
3940 | ||
3941 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
3942 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
3943 | insn_bits22_23 = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
3944 | ||
3945 | if (insn_bits28_31 == 0x0d) | |
3946 | { | |
3947 | /* Exception generation instructions. */ | |
3948 | if (insn_bits24_27 == 0x04) | |
3949 | { | |
5d98d3cd YQ |
3950 | if (!bits (aarch64_insn_r->aarch64_insn, 2, 4) |
3951 | && !bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
3952 | && bits (aarch64_insn_r->aarch64_insn, 0, 1) == 0x01) | |
99afc88b OJ |
3953 | { |
3954 | ULONGEST svc_number; | |
3955 | ||
3956 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, 8, | |
3957 | &svc_number); | |
3958 | return tdep->aarch64_syscall_record (aarch64_insn_r->regcache, | |
3959 | svc_number); | |
3960 | } | |
3961 | else | |
3962 | return AARCH64_RECORD_UNSUPPORTED; | |
3963 | } | |
3964 | /* System instructions. */ | |
3965 | else if (insn_bits24_27 == 0x05 && insn_bits22_23 == 0x00) | |
3966 | { | |
3967 | uint32_t reg_rt, reg_crn; | |
3968 | ||
3969 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
3970 | reg_crn = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
3971 | ||
3972 | /* Record rt in case of sysl and mrs instructions. */ | |
3973 | if (bit (aarch64_insn_r->aarch64_insn, 21)) | |
3974 | { | |
3975 | record_buf[0] = reg_rt; | |
3976 | aarch64_insn_r->reg_rec_count = 1; | |
3977 | } | |
3978 | /* Record cpsr for hint and msr(immediate) instructions. */ | |
3979 | else if (reg_crn == 0x02 || reg_crn == 0x04) | |
3980 | { | |
3981 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
3982 | aarch64_insn_r->reg_rec_count = 1; | |
3983 | } | |
3984 | } | |
3985 | /* Unconditional branch (register). */ | |
3986 | else if((insn_bits24_27 & 0x0e) == 0x06) | |
3987 | { | |
3988 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3989 | if (bits (aarch64_insn_r->aarch64_insn, 21, 22) == 0x01) | |
3990 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
3991 | } | |
3992 | else | |
3993 | return AARCH64_RECORD_UNKNOWN; | |
3994 | } | |
3995 | /* Unconditional branch (immediate). */ | |
3996 | else if ((insn_bits28_31 & 0x07) == 0x01 && (insn_bits24_27 & 0x0c) == 0x04) | |
3997 | { | |
3998 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
3999 | if (bit (aarch64_insn_r->aarch64_insn, 31)) | |
4000 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_LR_REGNUM; | |
4001 | } | |
4002 | else | |
4003 | /* Compare & branch (immediate), Test & branch (immediate) and | |
4004 | Conditional branch (immediate). */ | |
4005 | record_buf[aarch64_insn_r->reg_rec_count++] = AARCH64_PC_REGNUM; | |
4006 | ||
4007 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, | |
4008 | record_buf); | |
4009 | return AARCH64_RECORD_SUCCESS; | |
4010 | } | |
4011 | ||
4012 | /* Record handler for advanced SIMD load and store instructions. */ | |
4013 | ||
4014 | static unsigned int | |
4748a9be | 4015 | aarch64_record_asimd_load_store (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4016 | { |
4017 | CORE_ADDR address; | |
4018 | uint64_t addr_offset = 0; | |
4019 | uint32_t record_buf[24]; | |
4020 | uint64_t record_buf_mem[24]; | |
4021 | uint32_t reg_rn, reg_rt; | |
4022 | uint32_t reg_index = 0, mem_index = 0; | |
4023 | uint8_t opcode_bits, size_bits; | |
4024 | ||
4025 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4026 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
4027 | size_bits = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
4028 | opcode_bits = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
4029 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, &address); | |
4030 | ||
4031 | if (record_debug) | |
b277c936 | 4032 | debug_printf ("Process record: Advanced SIMD load/store\n"); |
99afc88b OJ |
4033 | |
4034 | /* Load/store single structure. */ | |
4035 | if (bit (aarch64_insn_r->aarch64_insn, 24)) | |
4036 | { | |
4037 | uint8_t sindex, scale, selem, esize, replicate = 0; | |
4038 | scale = opcode_bits >> 2; | |
4039 | selem = ((opcode_bits & 0x02) | | |
dda83cd7 | 4040 | bit (aarch64_insn_r->aarch64_insn, 21)) + 1; |
99afc88b | 4041 | switch (scale) |
dda83cd7 SM |
4042 | { |
4043 | case 1: | |
4044 | if (size_bits & 0x01) | |
4045 | return AARCH64_RECORD_UNKNOWN; | |
4046 | break; | |
4047 | case 2: | |
4048 | if ((size_bits >> 1) & 0x01) | |
4049 | return AARCH64_RECORD_UNKNOWN; | |
4050 | if (size_bits & 0x01) | |
4051 | { | |
4052 | if (!((opcode_bits >> 1) & 0x01)) | |
4053 | scale = 3; | |
4054 | else | |
4055 | return AARCH64_RECORD_UNKNOWN; | |
4056 | } | |
4057 | break; | |
4058 | case 3: | |
4059 | if (bit (aarch64_insn_r->aarch64_insn, 22) && !(opcode_bits & 0x01)) | |
4060 | { | |
4061 | scale = size_bits; | |
4062 | replicate = 1; | |
4063 | break; | |
4064 | } | |
4065 | else | |
4066 | return AARCH64_RECORD_UNKNOWN; | |
4067 | default: | |
4068 | break; | |
4069 | } | |
99afc88b OJ |
4070 | esize = 8 << scale; |
4071 | if (replicate) | |
dda83cd7 SM |
4072 | for (sindex = 0; sindex < selem; sindex++) |
4073 | { | |
4074 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
4075 | reg_rt = (reg_rt + 1) % 32; | |
4076 | } | |
99afc88b | 4077 | else |
dda83cd7 SM |
4078 | { |
4079 | for (sindex = 0; sindex < selem; sindex++) | |
a2e3e93f SM |
4080 | { |
4081 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
4082 | record_buf[reg_index++] = reg_rt + AARCH64_V0_REGNUM; | |
4083 | else | |
4084 | { | |
4085 | record_buf_mem[mem_index++] = esize / 8; | |
4086 | record_buf_mem[mem_index++] = address + addr_offset; | |
4087 | } | |
4088 | addr_offset = addr_offset + (esize / 8); | |
4089 | reg_rt = (reg_rt + 1) % 32; | |
4090 | } | |
dda83cd7 | 4091 | } |
99afc88b OJ |
4092 | } |
4093 | /* Load/store multiple structure. */ | |
4094 | else | |
4095 | { | |
4096 | uint8_t selem, esize, rpt, elements; | |
4097 | uint8_t eindex, rindex; | |
4098 | ||
4099 | esize = 8 << size_bits; | |
4100 | if (bit (aarch64_insn_r->aarch64_insn, 30)) | |
dda83cd7 | 4101 | elements = 128 / esize; |
99afc88b | 4102 | else |
dda83cd7 | 4103 | elements = 64 / esize; |
99afc88b OJ |
4104 | |
4105 | switch (opcode_bits) | |
dda83cd7 SM |
4106 | { |
4107 | /*LD/ST4 (4 Registers). */ | |
4108 | case 0: | |
4109 | rpt = 1; | |
4110 | selem = 4; | |
4111 | break; | |
4112 | /*LD/ST1 (4 Registers). */ | |
4113 | case 2: | |
4114 | rpt = 4; | |
4115 | selem = 1; | |
4116 | break; | |
4117 | /*LD/ST3 (3 Registers). */ | |
4118 | case 4: | |
4119 | rpt = 1; | |
4120 | selem = 3; | |
4121 | break; | |
4122 | /*LD/ST1 (3 Registers). */ | |
4123 | case 6: | |
4124 | rpt = 3; | |
4125 | selem = 1; | |
4126 | break; | |
4127 | /*LD/ST1 (1 Register). */ | |
4128 | case 7: | |
4129 | rpt = 1; | |
4130 | selem = 1; | |
4131 | break; | |
4132 | /*LD/ST2 (2 Registers). */ | |
4133 | case 8: | |
4134 | rpt = 1; | |
4135 | selem = 2; | |
4136 | break; | |
4137 | /*LD/ST1 (2 Registers). */ | |
4138 | case 10: | |
4139 | rpt = 2; | |
4140 | selem = 1; | |
4141 | break; | |
4142 | default: | |
4143 | return AARCH64_RECORD_UNSUPPORTED; | |
4144 | break; | |
4145 | } | |
99afc88b | 4146 | for (rindex = 0; rindex < rpt; rindex++) |
dda83cd7 SM |
4147 | for (eindex = 0; eindex < elements; eindex++) |
4148 | { | |
4149 | uint8_t reg_tt, sindex; | |
4150 | reg_tt = (reg_rt + rindex) % 32; | |
4151 | for (sindex = 0; sindex < selem; sindex++) | |
4152 | { | |
4153 | if (bit (aarch64_insn_r->aarch64_insn, 22)) | |
4154 | record_buf[reg_index++] = reg_tt + AARCH64_V0_REGNUM; | |
4155 | else | |
4156 | { | |
4157 | record_buf_mem[mem_index++] = esize / 8; | |
4158 | record_buf_mem[mem_index++] = address + addr_offset; | |
4159 | } | |
4160 | addr_offset = addr_offset + (esize / 8); | |
4161 | reg_tt = (reg_tt + 1) % 32; | |
4162 | } | |
4163 | } | |
99afc88b OJ |
4164 | } |
4165 | ||
4166 | if (bit (aarch64_insn_r->aarch64_insn, 23)) | |
4167 | record_buf[reg_index++] = reg_rn; | |
4168 | ||
4169 | aarch64_insn_r->reg_rec_count = reg_index; | |
4170 | aarch64_insn_r->mem_rec_count = mem_index / 2; | |
4171 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
dda83cd7 | 4172 | record_buf_mem); |
99afc88b | 4173 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, |
dda83cd7 | 4174 | record_buf); |
99afc88b OJ |
4175 | return AARCH64_RECORD_SUCCESS; |
4176 | } | |
4177 | ||
4178 | /* Record handler for load and store instructions. */ | |
4179 | ||
4180 | static unsigned int | |
4748a9be | 4181 | aarch64_record_load_store (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4182 | { |
4183 | uint8_t insn_bits24_27, insn_bits28_29, insn_bits10_11; | |
4184 | uint8_t insn_bit23, insn_bit21; | |
4185 | uint8_t opc, size_bits, ld_flag, vector_flag; | |
4186 | uint32_t reg_rn, reg_rt, reg_rt2; | |
4187 | uint64_t datasize, offset; | |
4188 | uint32_t record_buf[8]; | |
4189 | uint64_t record_buf_mem[8]; | |
4190 | CORE_ADDR address; | |
4191 | ||
4192 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
4193 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
4194 | insn_bits28_29 = bits (aarch64_insn_r->aarch64_insn, 28, 29); | |
4195 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
4196 | insn_bit23 = bit (aarch64_insn_r->aarch64_insn, 23); | |
4197 | ld_flag = bit (aarch64_insn_r->aarch64_insn, 22); | |
4198 | vector_flag = bit (aarch64_insn_r->aarch64_insn, 26); | |
4199 | reg_rt = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4200 | reg_rn = bits (aarch64_insn_r->aarch64_insn, 5, 9); | |
4201 | reg_rt2 = bits (aarch64_insn_r->aarch64_insn, 10, 14); | |
4202 | size_bits = bits (aarch64_insn_r->aarch64_insn, 30, 31); | |
4203 | ||
4204 | /* Load/store exclusive. */ | |
4205 | if (insn_bits24_27 == 0x08 && insn_bits28_29 == 0x00) | |
4206 | { | |
4207 | if (record_debug) | |
b277c936 | 4208 | debug_printf ("Process record: load/store exclusive\n"); |
99afc88b OJ |
4209 | |
4210 | if (ld_flag) | |
4211 | { | |
4212 | record_buf[0] = reg_rt; | |
4213 | aarch64_insn_r->reg_rec_count = 1; | |
4214 | if (insn_bit21) | |
4215 | { | |
4216 | record_buf[1] = reg_rt2; | |
4217 | aarch64_insn_r->reg_rec_count = 2; | |
4218 | } | |
4219 | } | |
4220 | else | |
4221 | { | |
4222 | if (insn_bit21) | |
4223 | datasize = (8 << size_bits) * 2; | |
4224 | else | |
4225 | datasize = (8 << size_bits); | |
4226 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4227 | &address); | |
4228 | record_buf_mem[0] = datasize / 8; | |
4229 | record_buf_mem[1] = address; | |
4230 | aarch64_insn_r->mem_rec_count = 1; | |
4231 | if (!insn_bit23) | |
4232 | { | |
4233 | /* Save register rs. */ | |
4234 | record_buf[0] = bits (aarch64_insn_r->aarch64_insn, 16, 20); | |
4235 | aarch64_insn_r->reg_rec_count = 1; | |
4236 | } | |
4237 | } | |
4238 | } | |
4239 | /* Load register (literal) instructions decoding. */ | |
4240 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x01) | |
4241 | { | |
4242 | if (record_debug) | |
b277c936 | 4243 | debug_printf ("Process record: load register (literal)\n"); |
99afc88b | 4244 | if (vector_flag) |
dda83cd7 | 4245 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; |
99afc88b | 4246 | else |
dda83cd7 | 4247 | record_buf[0] = reg_rt; |
99afc88b OJ |
4248 | aarch64_insn_r->reg_rec_count = 1; |
4249 | } | |
4250 | /* All types of load/store pair instructions decoding. */ | |
4251 | else if ((insn_bits24_27 & 0x0a) == 0x08 && insn_bits28_29 == 0x02) | |
4252 | { | |
4253 | if (record_debug) | |
b277c936 | 4254 | debug_printf ("Process record: load/store pair\n"); |
99afc88b OJ |
4255 | |
4256 | if (ld_flag) | |
dda83cd7 SM |
4257 | { |
4258 | if (vector_flag) | |
4259 | { | |
4260 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4261 | record_buf[1] = reg_rt2 + AARCH64_V0_REGNUM; | |
4262 | } | |
4263 | else | |
4264 | { | |
4265 | record_buf[0] = reg_rt; | |
4266 | record_buf[1] = reg_rt2; | |
4267 | } | |
4268 | aarch64_insn_r->reg_rec_count = 2; | |
4269 | } | |
99afc88b | 4270 | else |
dda83cd7 SM |
4271 | { |
4272 | uint16_t imm7_off; | |
4273 | imm7_off = bits (aarch64_insn_r->aarch64_insn, 15, 21); | |
4274 | if (!vector_flag) | |
4275 | size_bits = size_bits >> 1; | |
4276 | datasize = 8 << (2 + size_bits); | |
4277 | offset = (imm7_off & 0x40) ? (~imm7_off & 0x007f) + 1 : imm7_off; | |
4278 | offset = offset << (2 + size_bits); | |
4279 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4280 | &address); | |
4281 | if (!((insn_bits24_27 & 0x0b) == 0x08 && insn_bit23)) | |
4282 | { | |
4283 | if (imm7_off & 0x40) | |
4284 | address = address - offset; | |
4285 | else | |
4286 | address = address + offset; | |
4287 | } | |
4288 | ||
4289 | record_buf_mem[0] = datasize / 8; | |
4290 | record_buf_mem[1] = address; | |
4291 | record_buf_mem[2] = datasize / 8; | |
4292 | record_buf_mem[3] = address + (datasize / 8); | |
4293 | aarch64_insn_r->mem_rec_count = 2; | |
4294 | } | |
99afc88b | 4295 | if (bit (aarch64_insn_r->aarch64_insn, 23)) |
dda83cd7 | 4296 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; |
99afc88b OJ |
4297 | } |
4298 | /* Load/store register (unsigned immediate) instructions. */ | |
4299 | else if ((insn_bits24_27 & 0x0b) == 0x09 && insn_bits28_29 == 0x03) | |
4300 | { | |
4301 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
4302 | if (!(opc >> 1)) | |
33877125 YQ |
4303 | { |
4304 | if (opc & 0x01) | |
4305 | ld_flag = 0x01; | |
4306 | else | |
4307 | ld_flag = 0x0; | |
4308 | } | |
99afc88b | 4309 | else |
33877125 | 4310 | { |
1e2b521d YQ |
4311 | if (size_bits == 0x3 && vector_flag == 0x0 && opc == 0x2) |
4312 | { | |
4313 | /* PRFM (immediate) */ | |
4314 | return AARCH64_RECORD_SUCCESS; | |
4315 | } | |
4316 | else if (size_bits == 0x2 && vector_flag == 0x0 && opc == 0x2) | |
4317 | { | |
4318 | /* LDRSW (immediate) */ | |
4319 | ld_flag = 0x1; | |
4320 | } | |
33877125 | 4321 | else |
1e2b521d YQ |
4322 | { |
4323 | if (opc & 0x01) | |
4324 | ld_flag = 0x01; | |
4325 | else | |
4326 | ld_flag = 0x0; | |
4327 | } | |
33877125 | 4328 | } |
99afc88b OJ |
4329 | |
4330 | if (record_debug) | |
4331 | { | |
b277c936 PL |
4332 | debug_printf ("Process record: load/store (unsigned immediate):" |
4333 | " size %x V %d opc %x\n", size_bits, vector_flag, | |
4334 | opc); | |
99afc88b OJ |
4335 | } |
4336 | ||
4337 | if (!ld_flag) | |
dda83cd7 SM |
4338 | { |
4339 | offset = bits (aarch64_insn_r->aarch64_insn, 10, 21); | |
4340 | datasize = 8 << size_bits; | |
4341 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4342 | &address); | |
4343 | offset = offset << size_bits; | |
4344 | address = address + offset; | |
4345 | ||
4346 | record_buf_mem[0] = datasize >> 3; | |
4347 | record_buf_mem[1] = address; | |
4348 | aarch64_insn_r->mem_rec_count = 1; | |
4349 | } | |
99afc88b | 4350 | else |
dda83cd7 SM |
4351 | { |
4352 | if (vector_flag) | |
4353 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4354 | else | |
4355 | record_buf[0] = reg_rt; | |
4356 | aarch64_insn_r->reg_rec_count = 1; | |
4357 | } | |
99afc88b OJ |
4358 | } |
4359 | /* Load/store register (register offset) instructions. */ | |
5d98d3cd YQ |
4360 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
4361 | && insn_bits10_11 == 0x02 && insn_bit21) | |
99afc88b OJ |
4362 | { |
4363 | if (record_debug) | |
b277c936 | 4364 | debug_printf ("Process record: load/store (register offset)\n"); |
99afc88b OJ |
4365 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); |
4366 | if (!(opc >> 1)) | |
dda83cd7 SM |
4367 | if (opc & 0x01) |
4368 | ld_flag = 0x01; | |
4369 | else | |
4370 | ld_flag = 0x0; | |
99afc88b | 4371 | else |
dda83cd7 SM |
4372 | if (size_bits != 0x03) |
4373 | ld_flag = 0x01; | |
4374 | else | |
4375 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
4376 | |
4377 | if (!ld_flag) | |
dda83cd7 SM |
4378 | { |
4379 | ULONGEST reg_rm_val; | |
4380 | ||
4381 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, | |
4382 | bits (aarch64_insn_r->aarch64_insn, 16, 20), ®_rm_val); | |
4383 | if (bit (aarch64_insn_r->aarch64_insn, 12)) | |
4384 | offset = reg_rm_val << size_bits; | |
4385 | else | |
4386 | offset = reg_rm_val; | |
4387 | datasize = 8 << size_bits; | |
4388 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4389 | &address); | |
4390 | address = address + offset; | |
4391 | record_buf_mem[0] = datasize >> 3; | |
4392 | record_buf_mem[1] = address; | |
4393 | aarch64_insn_r->mem_rec_count = 1; | |
4394 | } | |
99afc88b | 4395 | else |
dda83cd7 SM |
4396 | { |
4397 | if (vector_flag) | |
4398 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4399 | else | |
4400 | record_buf[0] = reg_rt; | |
4401 | aarch64_insn_r->reg_rec_count = 1; | |
4402 | } | |
99afc88b OJ |
4403 | } |
4404 | /* Load/store register (immediate and unprivileged) instructions. */ | |
5d98d3cd YQ |
4405 | else if ((insn_bits24_27 & 0x0b) == 0x08 && insn_bits28_29 == 0x03 |
4406 | && !insn_bit21) | |
99afc88b OJ |
4407 | { |
4408 | if (record_debug) | |
4409 | { | |
b277c936 PL |
4410 | debug_printf ("Process record: load/store " |
4411 | "(immediate and unprivileged)\n"); | |
99afc88b OJ |
4412 | } |
4413 | opc = bits (aarch64_insn_r->aarch64_insn, 22, 23); | |
4414 | if (!(opc >> 1)) | |
dda83cd7 SM |
4415 | if (opc & 0x01) |
4416 | ld_flag = 0x01; | |
4417 | else | |
4418 | ld_flag = 0x0; | |
99afc88b | 4419 | else |
dda83cd7 SM |
4420 | if (size_bits != 0x03) |
4421 | ld_flag = 0x01; | |
4422 | else | |
4423 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
4424 | |
4425 | if (!ld_flag) | |
dda83cd7 SM |
4426 | { |
4427 | uint16_t imm9_off; | |
4428 | imm9_off = bits (aarch64_insn_r->aarch64_insn, 12, 20); | |
4429 | offset = (imm9_off & 0x0100) ? (((~imm9_off) & 0x01ff) + 1) : imm9_off; | |
4430 | datasize = 8 << size_bits; | |
4431 | regcache_raw_read_unsigned (aarch64_insn_r->regcache, reg_rn, | |
4432 | &address); | |
4433 | if (insn_bits10_11 != 0x01) | |
4434 | { | |
4435 | if (imm9_off & 0x0100) | |
4436 | address = address - offset; | |
4437 | else | |
4438 | address = address + offset; | |
4439 | } | |
4440 | record_buf_mem[0] = datasize >> 3; | |
4441 | record_buf_mem[1] = address; | |
4442 | aarch64_insn_r->mem_rec_count = 1; | |
4443 | } | |
99afc88b | 4444 | else |
dda83cd7 SM |
4445 | { |
4446 | if (vector_flag) | |
4447 | record_buf[0] = reg_rt + AARCH64_V0_REGNUM; | |
4448 | else | |
4449 | record_buf[0] = reg_rt; | |
4450 | aarch64_insn_r->reg_rec_count = 1; | |
4451 | } | |
99afc88b | 4452 | if (insn_bits10_11 == 0x01 || insn_bits10_11 == 0x03) |
dda83cd7 | 4453 | record_buf[aarch64_insn_r->reg_rec_count++] = reg_rn; |
99afc88b OJ |
4454 | } |
4455 | /* Advanced SIMD load/store instructions. */ | |
4456 | else | |
4457 | return aarch64_record_asimd_load_store (aarch64_insn_r); | |
4458 | ||
4459 | MEM_ALLOC (aarch64_insn_r->aarch64_mems, aarch64_insn_r->mem_rec_count, | |
dda83cd7 | 4460 | record_buf_mem); |
99afc88b | 4461 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, |
dda83cd7 | 4462 | record_buf); |
99afc88b OJ |
4463 | return AARCH64_RECORD_SUCCESS; |
4464 | } | |
4465 | ||
4466 | /* Record handler for data processing SIMD and floating point instructions. */ | |
4467 | ||
4468 | static unsigned int | |
4748a9be | 4469 | aarch64_record_data_proc_simd_fp (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4470 | { |
4471 | uint8_t insn_bit21, opcode, rmode, reg_rd; | |
4472 | uint8_t insn_bits24_27, insn_bits28_31, insn_bits10_11, insn_bits12_15; | |
4473 | uint8_t insn_bits11_14; | |
4474 | uint32_t record_buf[2]; | |
4475 | ||
4476 | insn_bits24_27 = bits (aarch64_insn_r->aarch64_insn, 24, 27); | |
4477 | insn_bits28_31 = bits (aarch64_insn_r->aarch64_insn, 28, 31); | |
4478 | insn_bits10_11 = bits (aarch64_insn_r->aarch64_insn, 10, 11); | |
4479 | insn_bits12_15 = bits (aarch64_insn_r->aarch64_insn, 12, 15); | |
4480 | insn_bits11_14 = bits (aarch64_insn_r->aarch64_insn, 11, 14); | |
4481 | opcode = bits (aarch64_insn_r->aarch64_insn, 16, 18); | |
4482 | rmode = bits (aarch64_insn_r->aarch64_insn, 19, 20); | |
4483 | reg_rd = bits (aarch64_insn_r->aarch64_insn, 0, 4); | |
4484 | insn_bit21 = bit (aarch64_insn_r->aarch64_insn, 21); | |
4485 | ||
4486 | if (record_debug) | |
b277c936 | 4487 | debug_printf ("Process record: data processing SIMD/FP: "); |
99afc88b OJ |
4488 | |
4489 | if ((insn_bits28_31 & 0x05) == 0x01 && insn_bits24_27 == 0x0e) | |
4490 | { | |
4491 | /* Floating point - fixed point conversion instructions. */ | |
4492 | if (!insn_bit21) | |
4493 | { | |
4494 | if (record_debug) | |
b277c936 | 4495 | debug_printf ("FP - fixed point conversion"); |
99afc88b OJ |
4496 | |
4497 | if ((opcode >> 1) == 0x0 && rmode == 0x03) | |
4498 | record_buf[0] = reg_rd; | |
4499 | else | |
4500 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4501 | } | |
4502 | /* Floating point - conditional compare instructions. */ | |
4503 | else if (insn_bits10_11 == 0x01) | |
4504 | { | |
4505 | if (record_debug) | |
b277c936 | 4506 | debug_printf ("FP - conditional compare"); |
99afc88b OJ |
4507 | |
4508 | record_buf[0] = AARCH64_CPSR_REGNUM; | |
4509 | } | |
4510 | /* Floating point - data processing (2-source) and | |
dda83cd7 | 4511 | conditional select instructions. */ |
99afc88b OJ |
4512 | else if (insn_bits10_11 == 0x02 || insn_bits10_11 == 0x03) |
4513 | { | |
4514 | if (record_debug) | |
b277c936 | 4515 | debug_printf ("FP - DP (2-source)"); |
99afc88b OJ |
4516 | |
4517 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4518 | } | |
4519 | else if (insn_bits10_11 == 0x00) | |
4520 | { | |
4521 | /* Floating point - immediate instructions. */ | |
4522 | if ((insn_bits12_15 & 0x01) == 0x01 | |
4523 | || (insn_bits12_15 & 0x07) == 0x04) | |
4524 | { | |
4525 | if (record_debug) | |
b277c936 | 4526 | debug_printf ("FP - immediate"); |
99afc88b OJ |
4527 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; |
4528 | } | |
4529 | /* Floating point - compare instructions. */ | |
4530 | else if ((insn_bits12_15 & 0x03) == 0x02) | |
4531 | { | |
4532 | if (record_debug) | |
b277c936 | 4533 | debug_printf ("FP - immediate"); |
99afc88b OJ |
4534 | record_buf[0] = AARCH64_CPSR_REGNUM; |
4535 | } | |
4536 | /* Floating point - integer conversions instructions. */ | |
f62fce35 | 4537 | else if (insn_bits12_15 == 0x00) |
99afc88b OJ |
4538 | { |
4539 | /* Convert float to integer instruction. */ | |
4540 | if (!(opcode >> 1) || ((opcode >> 1) == 0x02 && !rmode)) | |
4541 | { | |
4542 | if (record_debug) | |
b277c936 | 4543 | debug_printf ("float to int conversion"); |
99afc88b OJ |
4544 | |
4545 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
4546 | } | |
4547 | /* Convert integer to float instruction. */ | |
4548 | else if ((opcode >> 1) == 0x01 && !rmode) | |
4549 | { | |
4550 | if (record_debug) | |
b277c936 | 4551 | debug_printf ("int to float conversion"); |
99afc88b OJ |
4552 | |
4553 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4554 | } | |
4555 | /* Move float to integer instruction. */ | |
4556 | else if ((opcode >> 1) == 0x03) | |
4557 | { | |
4558 | if (record_debug) | |
b277c936 | 4559 | debug_printf ("move float to int"); |
99afc88b OJ |
4560 | |
4561 | if (!(opcode & 0x01)) | |
4562 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
4563 | else | |
4564 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4565 | } | |
f62fce35 YQ |
4566 | else |
4567 | return AARCH64_RECORD_UNKNOWN; | |
dda83cd7 | 4568 | } |
f62fce35 YQ |
4569 | else |
4570 | return AARCH64_RECORD_UNKNOWN; | |
dda83cd7 | 4571 | } |
f62fce35 YQ |
4572 | else |
4573 | return AARCH64_RECORD_UNKNOWN; | |
99afc88b OJ |
4574 | } |
4575 | else if ((insn_bits28_31 & 0x09) == 0x00 && insn_bits24_27 == 0x0e) | |
4576 | { | |
4577 | if (record_debug) | |
b277c936 | 4578 | debug_printf ("SIMD copy"); |
99afc88b OJ |
4579 | |
4580 | /* Advanced SIMD copy instructions. */ | |
4581 | if (!bits (aarch64_insn_r->aarch64_insn, 21, 23) | |
4582 | && !bit (aarch64_insn_r->aarch64_insn, 15) | |
4583 | && bit (aarch64_insn_r->aarch64_insn, 10)) | |
4584 | { | |
4585 | if (insn_bits11_14 == 0x05 || insn_bits11_14 == 0x07) | |
4586 | record_buf[0] = reg_rd + AARCH64_X0_REGNUM; | |
4587 | else | |
4588 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4589 | } | |
4590 | else | |
4591 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4592 | } | |
4593 | /* All remaining floating point or advanced SIMD instructions. */ | |
4594 | else | |
4595 | { | |
4596 | if (record_debug) | |
b277c936 | 4597 | debug_printf ("all remain"); |
99afc88b OJ |
4598 | |
4599 | record_buf[0] = reg_rd + AARCH64_V0_REGNUM; | |
4600 | } | |
4601 | ||
4602 | if (record_debug) | |
b277c936 | 4603 | debug_printf ("\n"); |
99afc88b | 4604 | |
bfbe4b84 | 4605 | /* Record the V/X register. */ |
99afc88b | 4606 | aarch64_insn_r->reg_rec_count++; |
bfbe4b84 LM |
4607 | |
4608 | /* Some of these instructions may set bits in the FPSR, so record it | |
4609 | too. */ | |
4610 | record_buf[1] = AARCH64_FPSR_REGNUM; | |
4611 | aarch64_insn_r->reg_rec_count++; | |
4612 | ||
4613 | gdb_assert (aarch64_insn_r->reg_rec_count == 2); | |
99afc88b OJ |
4614 | REG_ALLOC (aarch64_insn_r->aarch64_regs, aarch64_insn_r->reg_rec_count, |
4615 | record_buf); | |
4616 | return AARCH64_RECORD_SUCCESS; | |
4617 | } | |
4618 | ||
4619 | /* Decodes insns type and invokes its record handler. */ | |
4620 | ||
4621 | static unsigned int | |
4748a9be | 4622 | aarch64_record_decode_insn_handler (aarch64_insn_decode_record *aarch64_insn_r) |
99afc88b OJ |
4623 | { |
4624 | uint32_t ins_bit25, ins_bit26, ins_bit27, ins_bit28; | |
4625 | ||
4626 | ins_bit25 = bit (aarch64_insn_r->aarch64_insn, 25); | |
4627 | ins_bit26 = bit (aarch64_insn_r->aarch64_insn, 26); | |
4628 | ins_bit27 = bit (aarch64_insn_r->aarch64_insn, 27); | |
4629 | ins_bit28 = bit (aarch64_insn_r->aarch64_insn, 28); | |
4630 | ||
4631 | /* Data processing - immediate instructions. */ | |
4632 | if (!ins_bit26 && !ins_bit27 && ins_bit28) | |
4633 | return aarch64_record_data_proc_imm (aarch64_insn_r); | |
4634 | ||
4635 | /* Branch, exception generation and system instructions. */ | |
4636 | if (ins_bit26 && !ins_bit27 && ins_bit28) | |
4637 | return aarch64_record_branch_except_sys (aarch64_insn_r); | |
4638 | ||
4639 | /* Load and store instructions. */ | |
4640 | if (!ins_bit25 && ins_bit27) | |
4641 | return aarch64_record_load_store (aarch64_insn_r); | |
4642 | ||
4643 | /* Data processing - register instructions. */ | |
4644 | if (ins_bit25 && !ins_bit26 && ins_bit27) | |
4645 | return aarch64_record_data_proc_reg (aarch64_insn_r); | |
4646 | ||
4647 | /* Data processing - SIMD and floating point instructions. */ | |
4648 | if (ins_bit25 && ins_bit26 && ins_bit27) | |
4649 | return aarch64_record_data_proc_simd_fp (aarch64_insn_r); | |
4650 | ||
4651 | return AARCH64_RECORD_UNSUPPORTED; | |
4652 | } | |
4653 | ||
4654 | /* Cleans up local record registers and memory allocations. */ | |
4655 | ||
4656 | static void | |
4748a9be | 4657 | deallocate_reg_mem (aarch64_insn_decode_record *record) |
99afc88b OJ |
4658 | { |
4659 | xfree (record->aarch64_regs); | |
4660 | xfree (record->aarch64_mems); | |
4661 | } | |
4662 | ||
1e2b521d YQ |
4663 | #if GDB_SELF_TEST |
4664 | namespace selftests { | |
4665 | ||
4666 | static void | |
4667 | aarch64_process_record_test (void) | |
4668 | { | |
4669 | struct gdbarch_info info; | |
4670 | uint32_t ret; | |
4671 | ||
1e2b521d YQ |
4672 | info.bfd_arch_info = bfd_scan_arch ("aarch64"); |
4673 | ||
4674 | struct gdbarch *gdbarch = gdbarch_find_by_info (info); | |
4675 | SELF_CHECK (gdbarch != NULL); | |
4676 | ||
4748a9be | 4677 | aarch64_insn_decode_record aarch64_record; |
1e2b521d | 4678 | |
4748a9be | 4679 | memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record)); |
1e2b521d YQ |
4680 | aarch64_record.regcache = NULL; |
4681 | aarch64_record.this_addr = 0; | |
4682 | aarch64_record.gdbarch = gdbarch; | |
4683 | ||
4684 | /* 20 00 80 f9 prfm pldl1keep, [x1] */ | |
4685 | aarch64_record.aarch64_insn = 0xf9800020; | |
4686 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
4687 | SELF_CHECK (ret == AARCH64_RECORD_SUCCESS); | |
4688 | SELF_CHECK (aarch64_record.reg_rec_count == 0); | |
4689 | SELF_CHECK (aarch64_record.mem_rec_count == 0); | |
4690 | ||
4691 | deallocate_reg_mem (&aarch64_record); | |
4692 | } | |
4693 | ||
4694 | } // namespace selftests | |
4695 | #endif /* GDB_SELF_TEST */ | |
4696 | ||
99afc88b OJ |
4697 | /* Parse the current instruction and record the values of the registers and |
4698 | memory that will be changed in current instruction to record_arch_list | |
4699 | return -1 if something is wrong. */ | |
4700 | ||
4701 | int | |
4702 | aarch64_process_record (struct gdbarch *gdbarch, struct regcache *regcache, | |
4703 | CORE_ADDR insn_addr) | |
4704 | { | |
4705 | uint32_t rec_no = 0; | |
4706 | uint8_t insn_size = 4; | |
4707 | uint32_t ret = 0; | |
99afc88b | 4708 | gdb_byte buf[insn_size]; |
4748a9be | 4709 | aarch64_insn_decode_record aarch64_record; |
99afc88b OJ |
4710 | |
4711 | memset (&buf[0], 0, insn_size); | |
4748a9be | 4712 | memset (&aarch64_record, 0, sizeof (aarch64_insn_decode_record)); |
99afc88b OJ |
4713 | target_read_memory (insn_addr, &buf[0], insn_size); |
4714 | aarch64_record.aarch64_insn | |
4715 | = (uint32_t) extract_unsigned_integer (&buf[0], | |
4716 | insn_size, | |
4717 | gdbarch_byte_order (gdbarch)); | |
4718 | aarch64_record.regcache = regcache; | |
4719 | aarch64_record.this_addr = insn_addr; | |
4720 | aarch64_record.gdbarch = gdbarch; | |
4721 | ||
4722 | ret = aarch64_record_decode_insn_handler (&aarch64_record); | |
4723 | if (ret == AARCH64_RECORD_UNSUPPORTED) | |
4724 | { | |
6cb06a8c TT |
4725 | gdb_printf (gdb_stderr, |
4726 | _("Process record does not support instruction " | |
4727 | "0x%0x at address %s.\n"), | |
4728 | aarch64_record.aarch64_insn, | |
4729 | paddress (gdbarch, insn_addr)); | |
99afc88b OJ |
4730 | ret = -1; |
4731 | } | |
4732 | ||
4733 | if (0 == ret) | |
4734 | { | |
4735 | /* Record registers. */ | |
4736 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4737 | AARCH64_PC_REGNUM); | |
4738 | /* Always record register CPSR. */ | |
4739 | record_full_arch_list_add_reg (aarch64_record.regcache, | |
4740 | AARCH64_CPSR_REGNUM); | |
4741 | if (aarch64_record.aarch64_regs) | |
4742 | for (rec_no = 0; rec_no < aarch64_record.reg_rec_count; rec_no++) | |
4743 | if (record_full_arch_list_add_reg (aarch64_record.regcache, | |
4744 | aarch64_record.aarch64_regs[rec_no])) | |
4745 | ret = -1; | |
4746 | ||
4747 | /* Record memories. */ | |
4748 | if (aarch64_record.aarch64_mems) | |
4749 | for (rec_no = 0; rec_no < aarch64_record.mem_rec_count; rec_no++) | |
4750 | if (record_full_arch_list_add_mem | |
4751 | ((CORE_ADDR)aarch64_record.aarch64_mems[rec_no].addr, | |
4752 | aarch64_record.aarch64_mems[rec_no].len)) | |
4753 | ret = -1; | |
4754 | ||
4755 | if (record_full_arch_list_add_end ()) | |
4756 | ret = -1; | |
4757 | } | |
4758 | ||
4759 | deallocate_reg_mem (&aarch64_record); | |
4760 | return ret; | |
4761 | } |