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a4b6fc86 | 1 | /* Native-dependent code for GNU/Linux x86-64. |
0a65a603 | 2 | |
d01e8234 | 3 | Copyright (C) 2001-2025 Free Software Foundation, Inc. |
53e95fcf JS |
4 | Contributed by Jiri Smid, SuSE Labs. |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 10 | the Free Software Foundation; either version 3 of the License, or |
53e95fcf JS |
11 | (at your option) any later version. |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
53e95fcf | 20 | |
4de283e4 TT |
21 | #include "inferior.h" |
22 | #include "regcache.h" | |
23 | #include "elf/common.h" | |
24 | #include <sys/uio.h> | |
25 | #include "nat/gdb_ptrace.h" | |
c43af07c | 26 | #include <asm/prctl.h> |
33a0a2ac | 27 | #include <sys/reg.h> |
4de283e4 TT |
28 | #include "gregset.h" |
29 | #include "gdb_proc_service.h" | |
c4f35dd8 | 30 | |
3116063b | 31 | #include "amd64-nat.h" |
9c1488cb | 32 | #include "amd64-tdep.h" |
4de283e4 | 33 | #include "amd64-linux-tdep.h" |
d55e5aa6 | 34 | #include "i386-linux-tdep.h" |
268a13a5 | 35 | #include "gdbsupport/x86-xstate.h" |
4de283e4 | 36 | |
d55e5aa6 | 37 | #include "x86-linux-nat.h" |
4de283e4 TT |
38 | #include "nat/linux-ptrace.h" |
39 | #include "nat/amd64-linux-siginfo.h" | |
60fac5b8 | 40 | |
2735833d WT |
41 | /* This definition comes from prctl.h. Kernels older than 2.5.64 |
42 | do not have it. */ | |
43 | #ifndef PTRACE_ARCH_PRCTL | |
44 | #define PTRACE_ARCH_PRCTL 30 | |
45 | #endif | |
46 | ||
f6ac5f3d PA |
47 | struct amd64_linux_nat_target final : public x86_linux_nat_target |
48 | { | |
49 | /* Add our register access methods. */ | |
50 | void fetch_registers (struct regcache *, int) override; | |
51 | void store_registers (struct regcache *, int) override; | |
135340af PA |
52 | |
53 | bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) | |
54 | override; | |
f6ac5f3d PA |
55 | }; |
56 | ||
57 | static amd64_linux_nat_target the_amd64_linux_nat_target; | |
58 | ||
60fac5b8 MK |
59 | /* Mapping between the general-purpose registers in GNU/Linux x86-64 |
60 | `struct user' format and GDB's register cache layout for GNU/Linux | |
61 | i386. | |
62 | ||
63 | Note that most GNU/Linux x86-64 registers are 64-bit, while the | |
64 | GNU/Linux i386 registers are all 32-bit, but since we're | |
65 | little-endian we get away with that. */ | |
66 | ||
67 | /* From <sys/reg.h> on GNU/Linux i386. */ | |
430eaf2e | 68 | static int amd64_linux_gregset32_reg_offset[] = |
60fac5b8 | 69 | { |
f5859b4d MK |
70 | RAX * 8, RCX * 8, /* %eax, %ecx */ |
71 | RDX * 8, RBX * 8, /* %edx, %ebx */ | |
72 | RSP * 8, RBP * 8, /* %esp, %ebp */ | |
73 | RSI * 8, RDI * 8, /* %esi, %edi */ | |
74 | RIP * 8, EFLAGS * 8, /* %eip, %eflags */ | |
75 | CS * 8, SS * 8, /* %cs, %ss */ | |
76 | DS * 8, ES * 8, /* %ds, %es */ | |
77 | FS * 8, GS * 8, /* %fs, %gs */ | |
60fac5b8 MK |
78 | -1, -1, -1, -1, -1, -1, -1, -1, |
79 | -1, -1, -1, -1, -1, -1, -1, -1, | |
80 | -1, -1, -1, -1, -1, -1, -1, -1, -1, | |
a055a187 | 81 | -1, -1, -1, -1, -1, -1, -1, -1, |
fc143432 SC |
82 | /* MPX is deprecated. Yet we keep this to not give the registers below |
83 | a new number. That could break older gdbservers. */ | |
01f9f808 MS |
84 | -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */ |
85 | -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */ | |
86 | -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */ | |
87 | -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm7 (AVX512) */ | |
51547df6 | 88 | -1, /* PKEYS register PKRU */ |
01f9f808 | 89 | ORIG_RAX * 8 /* "orig_eax" */ |
60fac5b8 | 90 | }; |
53e95fcf JS |
91 | \f |
92 | ||
5cb0406b | 93 | /* Transferring the general-purpose registers between GDB, inferiors |
53e95fcf JS |
94 | and core files. */ |
95 | ||
3f52fdbc KB |
96 | /* See amd64_collect_native_gregset. This linux specific version handles |
97 | issues with negative EAX values not being restored correctly upon syscall | |
98 | return when debugging 32-bit targets. It has no effect on 64-bit | |
99 | targets. */ | |
100 | ||
101 | static void | |
102 | amd64_linux_collect_native_gregset (const struct regcache *regcache, | |
dda83cd7 | 103 | void *gregs, int regnum) |
3f52fdbc KB |
104 | { |
105 | amd64_collect_native_gregset (regcache, gregs, regnum); | |
106 | ||
107 | struct gdbarch *gdbarch = regcache->arch (); | |
108 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) | |
109 | { | |
110 | /* Sign extend EAX value to avoid potential syscall restart | |
111 | problems. | |
112 | ||
113 | On Linux, when a syscall is interrupted by a signal, the | |
114 | (kernel function implementing the) syscall may return | |
115 | -ERESTARTSYS when a signal occurs. Doing so indicates that | |
116 | the syscall is restartable. Then, depending on settings | |
117 | associated with the signal handler, and after the signal | |
118 | handler is called, the kernel can then either return -EINTR | |
119 | or it can cause the syscall to be restarted. We are | |
120 | concerned with the latter case here. | |
121 | ||
122 | On (32-bit) i386, the status (-ERESTARTSYS) is placed in the | |
123 | EAX register. When debugging a 32-bit process from a 64-bit | |
124 | (amd64) GDB, the debugger fetches 64-bit registers even | |
125 | though the process being debugged is only 32-bit. The | |
126 | register cache is only 32 bits wide though; GDB discards the | |
127 | high 32 bits when placing 64-bit values in the 32-bit | |
128 | regcache. Normally, this is not a problem since the 32-bit | |
129 | process should only care about the lower 32-bit portions of | |
130 | these registers. That said, it can happen that the 64-bit | |
131 | value being restored will be different from the 64-bit value | |
132 | that was originally retrieved from the kernel. The one place | |
133 | (that we know of) where it does matter is in the kernel's | |
134 | syscall restart code. The kernel's code for restarting a | |
135 | syscall after a signal expects to see a negative value | |
136 | (specifically -ERESTARTSYS) in the 64-bit RAX register in | |
137 | order to correctly cause a syscall to be restarted. | |
138 | ||
139 | The call to amd64_collect_native_gregset, above, is setting | |
140 | the high 32 bits of RAX (and other registers too) to 0. For | |
141 | syscall restart, we need to sign extend EAX so that RAX will | |
142 | appear as a negative value when EAX is set to -ERESTARTSYS. | |
143 | This in turn will cause the signal handling code in the | |
144 | kernel to recognize -ERESTARTSYS which will in turn cause the | |
145 | syscall to be restarted. | |
146 | ||
147 | The test case gdb.base/interrupt.exp tests for this problem. | |
148 | Without this sign extension code in place, it'll show | |
149 | a number of failures when testing against unix/-m32. */ | |
150 | ||
151 | if (regnum == -1 || regnum == I386_EAX_REGNUM) | |
152 | { | |
153 | void *ptr = ((gdb_byte *) gregs | |
154 | + amd64_linux_gregset32_reg_offset[I386_EAX_REGNUM]); | |
155 | ||
156 | *(int64_t *) ptr = *(int32_t *) ptr; | |
157 | } | |
158 | } | |
159 | } | |
160 | ||
60fac5b8 | 161 | /* Fill GDB's register cache with the general-purpose register values |
53e95fcf JS |
162 | in *GREGSETP. */ |
163 | ||
164 | void | |
7f7fe91e | 165 | supply_gregset (struct regcache *regcache, const elf_gregset_t *gregsetp) |
53e95fcf | 166 | { |
7f7fe91e | 167 | amd64_supply_native_gregset (regcache, gregsetp, -1); |
53e95fcf JS |
168 | } |
169 | ||
60fac5b8 MK |
170 | /* Fill register REGNUM (if it is a general-purpose register) in |
171 | *GREGSETP with the value in GDB's register cache. If REGNUM is -1, | |
53e95fcf JS |
172 | do this for all registers. */ |
173 | ||
174 | void | |
7f7fe91e UW |
175 | fill_gregset (const struct regcache *regcache, |
176 | elf_gregset_t *gregsetp, int regnum) | |
53e95fcf | 177 | { |
3f52fdbc | 178 | amd64_linux_collect_native_gregset (regcache, gregsetp, regnum); |
53e95fcf JS |
179 | } |
180 | ||
5cb0406b | 181 | /* Transferring floating-point registers between GDB, inferiors and cores. */ |
53e95fcf | 182 | |
60fac5b8 | 183 | /* Fill GDB's register cache with the floating-point and SSE register |
c4f35dd8 | 184 | values in *FPREGSETP. */ |
53e95fcf JS |
185 | |
186 | void | |
7f7fe91e | 187 | supply_fpregset (struct regcache *regcache, const elf_fpregset_t *fpregsetp) |
53e95fcf | 188 | { |
7f7fe91e | 189 | amd64_supply_fxsave (regcache, -1, fpregsetp); |
53e95fcf JS |
190 | } |
191 | ||
8dda9770 | 192 | /* Fill register REGNUM (if it is a floating-point or SSE register) in |
60fac5b8 | 193 | *FPREGSETP with the value in GDB's register cache. If REGNUM is |
c4f35dd8 | 194 | -1, do this for all registers. */ |
53e95fcf JS |
195 | |
196 | void | |
7f7fe91e UW |
197 | fill_fpregset (const struct regcache *regcache, |
198 | elf_fpregset_t *fpregsetp, int regnum) | |
53e95fcf | 199 | { |
7f7fe91e | 200 | amd64_collect_fxsave (regcache, regnum, fpregsetp); |
53e95fcf | 201 | } |
53e95fcf JS |
202 | \f |
203 | ||
204 | /* Transferring arbitrary registers between GDB and inferior. */ | |
205 | ||
60fac5b8 | 206 | /* Fetch register REGNUM from the child process. If REGNUM is -1, do |
53e95fcf JS |
207 | this for all registers (including the floating point and SSE |
208 | registers). */ | |
209 | ||
f6ac5f3d PA |
210 | void |
211 | amd64_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum) | |
53e95fcf | 212 | { |
ac7936df | 213 | struct gdbarch *gdbarch = regcache->arch (); |
9848bf83 | 214 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
53e95fcf JS |
215 | int tid; |
216 | ||
a4b6fc86 | 217 | /* GNU/Linux LWP ID's are process ID's. */ |
e38504b3 | 218 | tid = regcache->ptid ().lwp (); |
c4f35dd8 | 219 | if (tid == 0) |
e99b03dc | 220 | tid = regcache->ptid ().pid (); /* Not a threaded program. */ |
53e95fcf | 221 | |
f8028488 | 222 | if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 223 | { |
99679982 MK |
224 | elf_gregset_t regs; |
225 | ||
226 | if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 227 | perror_with_name (_("Couldn't get registers")); |
99679982 | 228 | |
56be3814 | 229 | amd64_supply_native_gregset (regcache, ®s, -1); |
60fac5b8 MK |
230 | if (regnum != -1) |
231 | return; | |
53e95fcf JS |
232 | } |
233 | ||
f8028488 | 234 | if (regnum == -1 || !amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 235 | { |
99679982 | 236 | elf_fpregset_t fpregs; |
53e95fcf | 237 | |
0bdb2f78 | 238 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
a055a187 | 239 | { |
3d435220 TV |
240 | /* Pre-4.14 kernels have a bug (fixed by commit 0852b374173b |
241 | "x86/fpu: Add FPU state copying quirk to handle XRSTOR failure on | |
242 | Intel Skylake CPUs") that sometimes causes the mxcsr location in | |
243 | xstateregs not to be copied by PTRACE_GETREGSET. Make sure that | |
244 | the location is at least initialized with a defined value. */ | |
d724d71a SM |
245 | gdb::byte_vector xstateregs (tdep->xsave_layout.sizeof_xsave, 0); |
246 | struct iovec iov; | |
247 | ||
248 | iov.iov_base = xstateregs.data (); | |
249 | iov.iov_len = xstateregs.size (); | |
a055a187 L |
250 | if (ptrace (PTRACE_GETREGSET, tid, |
251 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
252 | perror_with_name (_("Couldn't get extended state status")); | |
99679982 | 253 | |
d724d71a | 254 | amd64_supply_xsave (regcache, -1, xstateregs.data ()); |
a055a187 L |
255 | } |
256 | else | |
257 | { | |
258 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (long) &fpregs) < 0) | |
259 | perror_with_name (_("Couldn't get floating point status")); | |
260 | ||
261 | amd64_supply_fxsave (regcache, -1, &fpregs); | |
262 | } | |
99679982 | 263 | } |
53e95fcf JS |
264 | } |
265 | ||
60fac5b8 MK |
266 | /* Store register REGNUM back into the child process. If REGNUM is |
267 | -1, do this for all registers (including the floating-point and SSE | |
53e95fcf | 268 | registers). */ |
c4f35dd8 | 269 | |
f6ac5f3d PA |
270 | void |
271 | amd64_linux_nat_target::store_registers (struct regcache *regcache, int regnum) | |
53e95fcf | 272 | { |
ac7936df | 273 | struct gdbarch *gdbarch = regcache->arch (); |
9848bf83 | 274 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
53e95fcf JS |
275 | int tid; |
276 | ||
a4b6fc86 | 277 | /* GNU/Linux LWP ID's are process ID's. */ |
e38504b3 | 278 | tid = regcache->ptid ().lwp (); |
c4f35dd8 | 279 | if (tid == 0) |
e99b03dc | 280 | tid = regcache->ptid ().pid (); /* Not a threaded program. */ |
53e95fcf | 281 | |
f8028488 | 282 | if (regnum == -1 || amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 283 | { |
99679982 MK |
284 | elf_gregset_t regs; |
285 | ||
286 | if (ptrace (PTRACE_GETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 287 | perror_with_name (_("Couldn't get registers")); |
99679982 | 288 | |
3f52fdbc | 289 | amd64_linux_collect_native_gregset (regcache, ®s, regnum); |
99679982 MK |
290 | |
291 | if (ptrace (PTRACE_SETREGS, tid, 0, (long) ®s) < 0) | |
edefbb7c | 292 | perror_with_name (_("Couldn't write registers")); |
99679982 | 293 | |
60fac5b8 MK |
294 | if (regnum != -1) |
295 | return; | |
53e95fcf JS |
296 | } |
297 | ||
f8028488 | 298 | if (regnum == -1 || !amd64_native_gregset_supplies_p (gdbarch, regnum)) |
53e95fcf | 299 | { |
99679982 MK |
300 | elf_fpregset_t fpregs; |
301 | ||
0bdb2f78 | 302 | if (have_ptrace_getregset == TRIBOOL_TRUE) |
a055a187 | 303 | { |
d724d71a | 304 | gdb::byte_vector xstateregs (tdep->xsave_layout.sizeof_xsave); |
a055a187 L |
305 | struct iovec iov; |
306 | ||
d724d71a SM |
307 | iov.iov_base = xstateregs.data (); |
308 | iov.iov_len = xstateregs.size (); | |
a055a187 L |
309 | if (ptrace (PTRACE_GETREGSET, tid, |
310 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
311 | perror_with_name (_("Couldn't get extended state status")); | |
99679982 | 312 | |
d724d71a | 313 | amd64_collect_xsave (regcache, regnum, xstateregs.data (), 0); |
a055a187 L |
314 | |
315 | if (ptrace (PTRACE_SETREGSET, tid, | |
316 | (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) | |
317 | perror_with_name (_("Couldn't write extended state status")); | |
318 | } | |
319 | else | |
320 | { | |
321 | if (ptrace (PTRACE_GETFPREGS, tid, 0, (long) &fpregs) < 0) | |
322 | perror_with_name (_("Couldn't get floating point status")); | |
99679982 | 323 | |
a055a187 | 324 | amd64_collect_fxsave (regcache, regnum, &fpregs); |
99679982 | 325 | |
a055a187 L |
326 | if (ptrace (PTRACE_SETFPREGS, tid, 0, (long) &fpregs) < 0) |
327 | perror_with_name (_("Couldn't write floating point status")); | |
328 | } | |
53e95fcf | 329 | } |
53e95fcf JS |
330 | } |
331 | \f | |
1aa7e42c | 332 | |
50d71875 AC |
333 | /* This function is called by libthread_db as part of its handling of |
334 | a request for a thread's local storage address. */ | |
335 | ||
5bca7895 | 336 | ps_err_e |
754653a7 | 337 | ps_get_thread_area (struct ps_prochandle *ph, |
dda83cd7 | 338 | lwpid_t lwpid, int idx, void **base) |
c43af07c | 339 | { |
27b1f19f | 340 | if (gdbarch_bfd_arch_info (ph->thread->inf->arch ())->bits_per_word == 32) |
50d71875 | 341 | { |
8c420b8d GB |
342 | unsigned int base_addr; |
343 | ps_err_e result; | |
344 | ||
345 | result = x86_linux_get_thread_area (lwpid, (void *) (long) idx, | |
346 | &base_addr); | |
347 | if (result == PS_OK) | |
348 | { | |
349 | /* Extend the value to 64 bits. Here it's assumed that | |
350 | a "long" and a "void *" are the same. */ | |
351 | (*base) = (void *) (long) base_addr; | |
352 | } | |
353 | return result; | |
50d71875 AC |
354 | } |
355 | else | |
356 | { | |
2735833d | 357 | |
50d71875 AC |
358 | /* FIXME: ezannoni-2003-07-09 see comment above about include |
359 | file order. We could be getting bogus values for these two. */ | |
360 | gdb_assert (FS < ELF_NGREG); | |
361 | gdb_assert (GS < ELF_NGREG); | |
362 | switch (idx) | |
363 | { | |
364 | case FS: | |
6fea9e18 | 365 | { |
6fea9e18 L |
366 | unsigned long fs; |
367 | errno = 0; | |
368 | fs = ptrace (PTRACE_PEEKUSER, lwpid, | |
369 | offsetof (struct user_regs_struct, fs_base), 0); | |
370 | if (errno == 0) | |
371 | { | |
372 | *base = (void *) fs; | |
373 | return PS_OK; | |
374 | } | |
375 | } | |
1eb39914 | 376 | |
50d71875 | 377 | break; |
1eb39914 | 378 | |
50d71875 | 379 | case GS: |
6fea9e18 L |
380 | { |
381 | unsigned long gs; | |
382 | errno = 0; | |
383 | gs = ptrace (PTRACE_PEEKUSER, lwpid, | |
384 | offsetof (struct user_regs_struct, gs_base), 0); | |
385 | if (errno == 0) | |
386 | { | |
387 | *base = (void *) gs; | |
388 | return PS_OK; | |
389 | } | |
390 | } | |
50d71875 | 391 | break; |
1eb39914 | 392 | |
50d71875 AC |
393 | default: /* Should not happen. */ |
394 | return PS_BADADDR; | |
395 | } | |
c43af07c | 396 | } |
b6d42148 | 397 | return PS_ERR; /* ptrace failed. */ |
c43af07c | 398 | } |
5bca7895 | 399 | \f |
c43af07c | 400 | |
9cf12d57 | 401 | /* Convert a ptrace/host siginfo object, into/from the siginfo in the |
5b009018 PA |
402 | layout of the inferiors' architecture. Returns true if any |
403 | conversion was done; false otherwise. If DIRECTION is 1, then copy | |
9cf12d57 | 404 | from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to |
5b009018 PA |
405 | INF. */ |
406 | ||
135340af PA |
407 | bool |
408 | amd64_linux_nat_target::low_siginfo_fixup (siginfo_t *ptrace, | |
409 | gdb_byte *inf, | |
410 | int direction) | |
5b009018 | 411 | { |
ba224c70 L |
412 | struct gdbarch *gdbarch = get_frame_arch (get_current_frame ()); |
413 | ||
5b009018 PA |
414 | /* Is the inferior 32-bit? If so, then do fixup the siginfo |
415 | object. */ | |
ba224c70 | 416 | if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32) |
135340af PA |
417 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
418 | FIXUP_32); | |
ba224c70 L |
419 | /* No fixup for native x32 GDB. */ |
420 | else if (gdbarch_addr_bit (gdbarch) == 32 && sizeof (void *) == 8) | |
135340af PA |
421 | return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, |
422 | FIXUP_X32); | |
5b009018 | 423 | else |
135340af | 424 | return false; |
5b009018 | 425 | } |
c1e246a0 | 426 | |
5fe70629 | 427 | INIT_GDB_FILE (amd64_linux_nat) |
c1e246a0 | 428 | { |
c1e246a0 GB |
429 | amd64_native_gregset32_reg_offset = amd64_linux_gregset32_reg_offset; |
430 | amd64_native_gregset32_num_regs = I386_LINUX_NUM_REGS; | |
431 | amd64_native_gregset64_reg_offset = amd64_linux_gregset_reg_offset; | |
432 | amd64_native_gregset64_num_regs = AMD64_LINUX_NUM_REGS; | |
433 | ||
434 | gdb_assert (ARRAY_SIZE (amd64_linux_gregset32_reg_offset) | |
435 | == amd64_native_gregset32_num_regs); | |
436 | ||
f6ac5f3d | 437 | linux_target = &the_amd64_linux_nat_target; |
c1e246a0 GB |
438 | |
439 | /* Add the target. */ | |
d9f719f1 | 440 | add_inf_child_target (linux_target); |
c1e246a0 | 441 | } |