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cc628f3d AH |
1 | /* Common target-dependent functionality for AArch64. |
2 | ||
213516ef | 3 | Copyright (C) 2017-2023 Free Software Foundation, Inc. |
cc628f3d AH |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifndef ARCH_AARCH64_H | |
21 | #define ARCH_AARCH64_H | |
22 | ||
268a13a5 | 23 | #include "gdbsupport/tdesc.h" |
da434ccb | 24 | |
7fd85468 LM |
25 | /* Holds information on what architectural features are available. This is |
26 | used to select register sets. */ | |
27 | struct aarch64_features | |
28 | { | |
0ee6b1c5 | 29 | /* A non zero VQ value indicates both the presence of SVE and the |
ca65640f LM |
30 | Vector Quotient - the number of 128-bit chunks in an SVE Z |
31 | register. | |
0ee6b1c5 | 32 | |
ca65640f LM |
33 | The maximum value for VQ is 16 (5 bits). */ |
34 | uint64_t vq = 0; | |
7fd85468 LM |
35 | bool pauth = false; |
36 | bool mte = false; | |
ba60b963 LM |
37 | |
38 | /* A positive TLS value indicates the number of TLS registers available. */ | |
39 | uint8_t tls = 0; | |
ca65640f LM |
40 | /* The allowed values for SVQ are the following: |
41 | ||
42 | 0 - SME is not supported/available. | |
43 | 1 - SME is available, SVL is 16 bytes / 128-bit. | |
44 | 2 - SME is available, SVL is 32 bytes / 256-bit. | |
45 | 4 - SME is available, SVL is 64 bytes / 512-bit. | |
46 | 8 - SME is available, SVL is 128 bytes / 1024-bit. | |
47 | 16 - SME is available, SVL is 256 bytes / 2048-bit. | |
48 | ||
49 | These use at most 5 bits to represent. */ | |
50 | uint8_t svq = 0; | |
7fd85468 LM |
51 | }; |
52 | ||
0ee6b1c5 JB |
53 | inline bool operator==(const aarch64_features &lhs, const aarch64_features &rhs) |
54 | { | |
55 | return lhs.vq == rhs.vq | |
56 | && lhs.pauth == rhs.pauth | |
57 | && lhs.mte == rhs.mte | |
ca65640f LM |
58 | && lhs.tls == rhs.tls |
59 | && lhs.svq == rhs.svq; | |
0ee6b1c5 | 60 | } |
95228a0d | 61 | |
e8123c84 | 62 | namespace std |
0ee6b1c5 | 63 | { |
e8123c84 JB |
64 | template<> |
65 | struct hash<aarch64_features> | |
0ee6b1c5 | 66 | { |
e8123c84 JB |
67 | std::size_t operator()(const aarch64_features &features) const noexcept |
68 | { | |
69 | std::size_t h; | |
0ee6b1c5 | 70 | |
e8123c84 JB |
71 | h = features.vq; |
72 | h = h << 1 | features.pauth; | |
73 | h = h << 1 | features.mte; | |
ba60b963 LM |
74 | /* Shift by two bits for now. We may need to increase this in the future |
75 | if more TLS registers get added. */ | |
76 | h = h << 2 | features.tls; | |
ca65640f LM |
77 | |
78 | /* Make sure the SVQ values are within the limits. */ | |
79 | gdb_assert (features.svq >= 0); | |
80 | gdb_assert (features.svq <= 16); | |
81 | h = h << 5 | (features.svq & 0x5); | |
e8123c84 JB |
82 | return h; |
83 | } | |
84 | }; | |
85 | } | |
414d5848 | 86 | |
0ee6b1c5 | 87 | /* Create the aarch64 target description. */ |
c1bd443b | 88 | |
0ee6b1c5 JB |
89 | target_desc * |
90 | aarch64_create_target_description (const aarch64_features &features); | |
da434ccb | 91 | |
d88cb738 LM |
92 | /* Given a pointer value POINTER and a MASK of non-address bits, remove the |
93 | non-address bits from the pointer and sign-extend the result if required. | |
94 | The sign-extension is required so we can handle kernel addresses | |
95 | correctly. */ | |
96 | CORE_ADDR aarch64_remove_top_bits (CORE_ADDR pointer, CORE_ADDR mask); | |
97 | ||
98 | /* Given CMASK and DMASK the two PAC mask registers, return the correct PAC | |
99 | mask to use for removing non-address bits from a pointer. */ | |
100 | CORE_ADDR | |
101 | aarch64_mask_from_pac_registers (const CORE_ADDR cmask, const CORE_ADDR dmask); | |
102 | ||
739e8682 AH |
103 | /* Register numbers of various important registers. |
104 | Note that on SVE, the Z registers reuse the V register numbers and the V | |
105 | registers become pseudo registers. */ | |
cc628f3d AH |
106 | enum aarch64_regnum |
107 | { | |
108 | AARCH64_X0_REGNUM, /* First integer register. */ | |
109 | AARCH64_FP_REGNUM = AARCH64_X0_REGNUM + 29, /* Frame register, if used. */ | |
110 | AARCH64_LR_REGNUM = AARCH64_X0_REGNUM + 30, /* Return address. */ | |
111 | AARCH64_SP_REGNUM, /* Stack pointer. */ | |
112 | AARCH64_PC_REGNUM, /* Program counter. */ | |
113 | AARCH64_CPSR_REGNUM, /* Current Program Status Register. */ | |
114 | AARCH64_V0_REGNUM, /* First fp/vec register. */ | |
115 | AARCH64_V31_REGNUM = AARCH64_V0_REGNUM + 31, /* Last fp/vec register. */ | |
739e8682 AH |
116 | AARCH64_SVE_Z0_REGNUM = AARCH64_V0_REGNUM, /* First SVE Z register. */ |
117 | AARCH64_SVE_Z31_REGNUM = AARCH64_V31_REGNUM, /* Last SVE Z register. */ | |
cc628f3d AH |
118 | AARCH64_FPSR_REGNUM, /* Floating Point Status Register. */ |
119 | AARCH64_FPCR_REGNUM, /* Floating Point Control Register. */ | |
739e8682 AH |
120 | AARCH64_SVE_P0_REGNUM, /* First SVE predicate register. */ |
121 | AARCH64_SVE_P15_REGNUM = AARCH64_SVE_P0_REGNUM + 15, /* Last SVE predicate | |
122 | register. */ | |
123 | AARCH64_SVE_FFR_REGNUM, /* SVE First Fault Register. */ | |
9758a8f8 | 124 | AARCH64_SVE_VG_REGNUM, /* SVE Vector Granule. */ |
cc628f3d AH |
125 | |
126 | /* Other useful registers. */ | |
127 | AARCH64_LAST_X_ARG_REGNUM = AARCH64_X0_REGNUM + 7, | |
128 | AARCH64_STRUCT_RETURN_REGNUM = AARCH64_X0_REGNUM + 8, | |
129 | AARCH64_LAST_V_ARG_REGNUM = AARCH64_V0_REGNUM + 7 | |
130 | }; | |
131 | ||
ba60b963 LM |
132 | /* Sizes of various AArch64 registers. */ |
133 | #define AARCH64_TLS_REGISTER_SIZE 8 | |
134 | #define V_REGISTER_SIZE 16 | |
6afcd2d4 | 135 | |
d88cb738 LM |
136 | /* PAC-related constants. */ |
137 | /* Bit 55 is used to select between a kernel-space and user-space address. */ | |
138 | #define VA_RANGE_SELECT_BIT_MASK 0x80000000000000ULL | |
139 | /* Mask with 1's in bits 55~63, used to remove the top byte of pointers | |
140 | (Top Byte Ignore). */ | |
141 | #define AARCH64_TOP_BITS_MASK 0xff80000000000000ULL | |
142 | ||
c74e7cb9 AH |
143 | /* Pseudo register base numbers. */ |
144 | #define AARCH64_Q0_REGNUM 0 | |
145 | #define AARCH64_D0_REGNUM (AARCH64_Q0_REGNUM + AARCH64_D_REGISTER_COUNT) | |
146 | #define AARCH64_S0_REGNUM (AARCH64_D0_REGNUM + 32) | |
147 | #define AARCH64_H0_REGNUM (AARCH64_S0_REGNUM + 32) | |
148 | #define AARCH64_B0_REGNUM (AARCH64_H0_REGNUM + 32) | |
149 | #define AARCH64_SVE_V0_REGNUM (AARCH64_B0_REGNUM + 32) | |
150 | ||
76bed0fd AH |
151 | #define AARCH64_PAUTH_DMASK_REGNUM(pauth_reg_base) (pauth_reg_base) |
152 | #define AARCH64_PAUTH_CMASK_REGNUM(pauth_reg_base) (pauth_reg_base + 1) | |
6d002087 LM |
153 | /* The high versions of these masks are used for bare metal/kernel-mode pointer |
154 | authentication support. */ | |
155 | #define AARCH64_PAUTH_DMASK_HIGH_REGNUM(pauth_reg_base) (pauth_reg_base + 2) | |
156 | #define AARCH64_PAUTH_CMASK_HIGH_REGNUM(pauth_reg_base) (pauth_reg_base + 3) | |
157 | ||
158 | /* This size is only meant for Linux, not bare metal. QEMU exposes 4 masks. */ | |
1ef53e6b | 159 | #define AARCH64_PAUTH_REGS_SIZE (16) |
76bed0fd | 160 | |
cc628f3d AH |
161 | #define AARCH64_X_REGS_NUM 31 |
162 | #define AARCH64_V_REGS_NUM 32 | |
739e8682 AH |
163 | #define AARCH64_SVE_Z_REGS_NUM AARCH64_V_REGS_NUM |
164 | #define AARCH64_SVE_P_REGS_NUM 16 | |
cc628f3d | 165 | #define AARCH64_NUM_REGS AARCH64_FPCR_REGNUM + 1 |
739e8682 AH |
166 | #define AARCH64_SVE_NUM_REGS AARCH64_SVE_VG_REGNUM + 1 |
167 | ||
122394f1 AH |
168 | /* There are a number of ways of expressing the current SVE vector size: |
169 | ||
170 | VL : Vector Length. | |
171 | The number of bytes in an SVE Z register. | |
172 | VQ : Vector Quotient. | |
173 | The number of 128bit chunks in an SVE Z register. | |
9758a8f8 | 174 | VG : Vector Granule. |
122394f1 AH |
175 | The number of 64bit chunks in an SVE Z register. */ |
176 | ||
177 | #define sve_vg_from_vl(vl) ((vl) / 8) | |
178 | #define sve_vl_from_vg(vg) ((vg) * 8) | |
e5a77256 | 179 | #ifndef sve_vq_from_vl |
122394f1 | 180 | #define sve_vq_from_vl(vl) ((vl) / 0x10) |
e5a77256 SDJ |
181 | #endif |
182 | #ifndef sve_vl_from_vq | |
122394f1 | 183 | #define sve_vl_from_vq(vq) ((vq) * 0x10) |
e5a77256 | 184 | #endif |
122394f1 AH |
185 | #define sve_vq_from_vg(vg) (sve_vq_from_vl (sve_vl_from_vg (vg))) |
186 | #define sve_vg_from_vq(vq) (sve_vg_from_vl (sve_vl_from_vq (vq))) | |
187 | ||
188 | ||
95228a0d AH |
189 | /* Maximum supported VQ value. Increase if required. */ |
190 | #define AARCH64_MAX_SVE_VQ 16 | |
191 | ||
ca65640f LM |
192 | /* SME definitions |
193 | ||
194 | Some of these definitions are not found in the Architecture Reference | |
195 | Manual, but we use them so we can keep a similar standard compared to the | |
196 | SVE definitions that the Linux Kernel uses. Otherwise it can get | |
197 | confusing. | |
198 | ||
199 | SVL : Streaming Vector Length. | |
200 | Although the documentation handles SVL in bits, we do it in | |
201 | bytes to match what we do for SVE. | |
202 | ||
203 | The streaming vector length dictates the size of the ZA register and | |
204 | the size of the SVE registers when in streaming mode. | |
205 | ||
206 | SVQ : Streaming Vector Quotient. | |
207 | The number of 128-bit chunks in an SVE Z register or the size of | |
208 | each dimension of the SME ZA matrix. | |
209 | ||
210 | SVG : Streaming Vector Granule. | |
211 | The number of 64-bit chunks in an SVE Z register or the size of | |
212 | half a SME ZA matrix dimension. The SVG definition was added so | |
213 | we keep a familiar definition when dealing with SVE registers in | |
214 | streaming mode. */ | |
215 | ||
216 | /* The total number of tiles. This is always fixed regardless of the | |
217 | streaming vector length (svl). */ | |
218 | #define AARCH64_ZA_TILES_NUM 31 | |
219 | /* svl limits for SME. */ | |
220 | #define AARCH64_SME_MIN_SVL 128 | |
221 | #define AARCH64_SME_MAX_SVL 2048 | |
222 | ||
cc628f3d | 223 | #endif /* ARCH_AARCH64_H */ |