]>
Commit | Line | Data |
---|---|---|
ed9a39eb | 1 | /* GNU/Linux on ARM native support. |
32d0add0 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
ed9a39eb JM |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
ed9a39eb JM |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
ed9a39eb JM |
18 | |
19 | #include "defs.h" | |
20 | #include "inferior.h" | |
21 | #include "gdbcore.h" | |
4e052eda | 22 | #include "regcache.h" |
10d6c8cd DJ |
23 | #include "target.h" |
24 | #include "linux-nat.h" | |
05a4558a | 25 | #include "target-descriptions.h" |
3b273a55 | 26 | #include "auxv.h" |
e3039479 UW |
27 | #include "observer.h" |
28 | #include "gdbthread.h" | |
ed9a39eb | 29 | |
aeb98c60 | 30 | #include "arm-tdep.h" |
cb587d83 | 31 | #include "arm-linux-tdep.h" |
aeb98c60 | 32 | |
3b273a55 | 33 | #include <elf/common.h> |
ed9a39eb JM |
34 | #include <sys/user.h> |
35 | #include <sys/ptrace.h> | |
36 | #include <sys/utsname.h> | |
41c49b06 | 37 | #include <sys/procfs.h> |
ed9a39eb | 38 | |
0963b4bd | 39 | /* Prototypes for supply_gregset etc. */ |
c60c0f5f MS |
40 | #include "gregset.h" |
41 | ||
9308fc88 DJ |
42 | /* Defines ps_err_e, struct ps_prochandle. */ |
43 | #include "gdb_proc_service.h" | |
44 | ||
45 | #ifndef PTRACE_GET_THREAD_AREA | |
46 | #define PTRACE_GET_THREAD_AREA 22 | |
47 | #endif | |
48 | ||
05a4558a DJ |
49 | #ifndef PTRACE_GETWMMXREGS |
50 | #define PTRACE_GETWMMXREGS 18 | |
51 | #define PTRACE_SETWMMXREGS 19 | |
52 | #endif | |
53 | ||
3b273a55 RE |
54 | #ifndef PTRACE_GETVFPREGS |
55 | #define PTRACE_GETVFPREGS 27 | |
56 | #define PTRACE_SETVFPREGS 28 | |
57 | #endif | |
58 | ||
e3039479 UW |
59 | #ifndef PTRACE_GETHBPREGS |
60 | #define PTRACE_GETHBPREGS 29 | |
61 | #define PTRACE_SETHBPREGS 30 | |
62 | #endif | |
63 | ||
ed9a39eb JM |
64 | extern int arm_apcs_32; |
65 | ||
fdf39c9a | 66 | /* On GNU/Linux, threads are implemented as pseudo-processes, in which |
41c49b06 | 67 | case we may be tracing more than one process at a time. In that |
39f77062 | 68 | case, inferior_ptid will contain the main process ID and the |
fdf39c9a RE |
69 | individual thread (process) ID. get_thread_id () is used to get |
70 | the thread id if it's available, and the process id otherwise. */ | |
41c49b06 | 71 | |
4e841acf | 72 | static int |
39f77062 | 73 | get_thread_id (ptid_t ptid) |
41c49b06 | 74 | { |
dfd4cc63 | 75 | int tid = ptid_get_lwp (ptid); |
39f77062 | 76 | if (0 == tid) |
dfd4cc63 | 77 | tid = ptid_get_pid (ptid); |
41c49b06 SB |
78 | return tid; |
79 | } | |
3b273a55 | 80 | |
05a4558a | 81 | #define GET_THREAD_ID(PTID) get_thread_id (PTID) |
41c49b06 | 82 | |
41c49b06 | 83 | /* Get the value of a particular register from the floating point |
c6b92abd | 84 | state of the process and store it into regcache. */ |
41c49b06 SB |
85 | |
86 | static void | |
56be3814 | 87 | fetch_fpregister (struct regcache *regcache, int regno) |
41c49b06 SB |
88 | { |
89 | int ret, tid; | |
cb587d83 | 90 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
41c49b06 SB |
91 | |
92 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 93 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
94 | |
95 | /* Read the floating point state. */ | |
cb587d83 | 96 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
97 | if (ret < 0) |
98 | { | |
edefbb7c | 99 | warning (_("Unable to fetch floating point register.")); |
41c49b06 SB |
100 | return; |
101 | } | |
102 | ||
103 | /* Fetch fpsr. */ | |
34e8f22d | 104 | if (ARM_FPS_REGNUM == regno) |
56be3814 | 105 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 106 | fp + NWFPE_FPSR_OFFSET); |
41c49b06 SB |
107 | |
108 | /* Fetch the floating point register. */ | |
34e8f22d | 109 | if (regno >= ARM_F0_REGNUM && regno <= ARM_F7_REGNUM) |
56be3814 | 110 | supply_nwfpe_register (regcache, regno, fp); |
41c49b06 SB |
111 | } |
112 | ||
113 | /* Get the whole floating point state of the process and store it | |
c6b92abd | 114 | into regcache. */ |
ed9a39eb JM |
115 | |
116 | static void | |
56be3814 | 117 | fetch_fpregs (struct regcache *regcache) |
ed9a39eb | 118 | { |
41c49b06 | 119 | int ret, regno, tid; |
cb587d83 | 120 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 121 | |
41c49b06 | 122 | /* Get the thread id for the ptrace call. */ |
39f77062 | 123 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 | 124 | |
ed9a39eb | 125 | /* Read the floating point state. */ |
cb587d83 | 126 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
ed9a39eb JM |
127 | if (ret < 0) |
128 | { | |
edefbb7c | 129 | warning (_("Unable to fetch the floating point registers.")); |
ed9a39eb JM |
130 | return; |
131 | } | |
132 | ||
133 | /* Fetch fpsr. */ | |
56be3814 | 134 | regcache_raw_supply (regcache, ARM_FPS_REGNUM, |
cb587d83 | 135 | fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
136 | |
137 | /* Fetch the floating point registers. */ | |
34e8f22d | 138 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
56be3814 | 139 | supply_nwfpe_register (regcache, regno, fp); |
ed9a39eb JM |
140 | } |
141 | ||
41c49b06 | 142 | /* Save a particular register into the floating point state of the |
c6b92abd | 143 | process using the contents from regcache. */ |
41c49b06 SB |
144 | |
145 | static void | |
56be3814 | 146 | store_fpregister (const struct regcache *regcache, int regno) |
41c49b06 SB |
147 | { |
148 | int ret, tid; | |
cb587d83 | 149 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
41c49b06 SB |
150 | |
151 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 152 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
153 | |
154 | /* Read the floating point state. */ | |
cb587d83 | 155 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
156 | if (ret < 0) |
157 | { | |
edefbb7c | 158 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
159 | return; |
160 | } | |
161 | ||
162 | /* Store fpsr. */ | |
672c9795 YQ |
163 | if (ARM_FPS_REGNUM == regno |
164 | && REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) | |
56be3814 | 165 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
41c49b06 SB |
166 | |
167 | /* Store the floating point register. */ | |
34e8f22d | 168 | if (regno >= ARM_F0_REGNUM && regno <= ARM_F7_REGNUM) |
56be3814 | 169 | collect_nwfpe_register (regcache, regno, fp); |
41c49b06 | 170 | |
cb587d83 | 171 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); |
41c49b06 SB |
172 | if (ret < 0) |
173 | { | |
edefbb7c | 174 | warning (_("Unable to store floating point register.")); |
41c49b06 SB |
175 | return; |
176 | } | |
177 | } | |
178 | ||
ed9a39eb | 179 | /* Save the whole floating point state of the process using |
c6b92abd | 180 | the contents from regcache. */ |
ed9a39eb JM |
181 | |
182 | static void | |
56be3814 | 183 | store_fpregs (const struct regcache *regcache) |
ed9a39eb | 184 | { |
41c49b06 | 185 | int ret, regno, tid; |
cb587d83 | 186 | gdb_byte fp[ARM_LINUX_SIZEOF_NWFPE]; |
ed9a39eb | 187 | |
41c49b06 | 188 | /* Get the thread id for the ptrace call. */ |
39f77062 | 189 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
190 | |
191 | /* Read the floating point state. */ | |
cb587d83 | 192 | ret = ptrace (PT_GETFPREGS, tid, 0, fp); |
41c49b06 SB |
193 | if (ret < 0) |
194 | { | |
edefbb7c | 195 | warning (_("Unable to fetch the floating point registers.")); |
41c49b06 SB |
196 | return; |
197 | } | |
198 | ||
ed9a39eb | 199 | /* Store fpsr. */ |
672c9795 | 200 | if (REG_VALID == regcache_register_status (regcache, ARM_FPS_REGNUM)) |
56be3814 | 201 | regcache_raw_collect (regcache, ARM_FPS_REGNUM, fp + NWFPE_FPSR_OFFSET); |
ed9a39eb JM |
202 | |
203 | /* Store the floating point registers. */ | |
34e8f22d | 204 | for (regno = ARM_F0_REGNUM; regno <= ARM_F7_REGNUM; regno++) |
672c9795 | 205 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 206 | collect_nwfpe_register (regcache, regno, fp); |
ed9a39eb | 207 | |
cb587d83 | 208 | ret = ptrace (PTRACE_SETFPREGS, tid, 0, fp); |
ed9a39eb JM |
209 | if (ret < 0) |
210 | { | |
edefbb7c | 211 | warning (_("Unable to store floating point registers.")); |
ed9a39eb JM |
212 | return; |
213 | } | |
214 | } | |
215 | ||
41c49b06 | 216 | /* Fetch a general register of the process and store into |
c6b92abd | 217 | regcache. */ |
41c49b06 SB |
218 | |
219 | static void | |
56be3814 | 220 | fetch_register (struct regcache *regcache, int regno) |
41c49b06 SB |
221 | { |
222 | int ret, tid; | |
c2152441 | 223 | elf_gregset_t regs; |
41c49b06 SB |
224 | |
225 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 226 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
227 | |
228 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
229 | if (ret < 0) | |
230 | { | |
edefbb7c | 231 | warning (_("Unable to fetch general register.")); |
41c49b06 SB |
232 | return; |
233 | } | |
234 | ||
34e8f22d | 235 | if (regno >= ARM_A1_REGNUM && regno < ARM_PC_REGNUM) |
56be3814 | 236 | regcache_raw_supply (regcache, regno, (char *) ®s[regno]); |
41c49b06 | 237 | |
34e8f22d | 238 | if (ARM_PS_REGNUM == regno) |
41c49b06 SB |
239 | { |
240 | if (arm_apcs_32) | |
56be3814 | 241 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
17c12639 | 242 | (char *) ®s[ARM_CPSR_GREGNUM]); |
41c49b06 | 243 | else |
56be3814 | 244 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 245 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
246 | } |
247 | ||
34e8f22d | 248 | if (ARM_PC_REGNUM == regno) |
41c49b06 | 249 | { |
bf6ae464 | 250 | regs[ARM_PC_REGNUM] = gdbarch_addr_bits_remove |
08790784 UW |
251 | (get_regcache_arch (regcache), |
252 | regs[ARM_PC_REGNUM]); | |
56be3814 | 253 | regcache_raw_supply (regcache, ARM_PC_REGNUM, |
23a6d369 | 254 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
255 | } |
256 | } | |
257 | ||
ed9a39eb | 258 | /* Fetch all general registers of the process and store into |
c6b92abd | 259 | regcache. */ |
ed9a39eb JM |
260 | |
261 | static void | |
56be3814 | 262 | fetch_regs (struct regcache *regcache) |
ed9a39eb | 263 | { |
41c49b06 | 264 | int ret, regno, tid; |
c2152441 | 265 | elf_gregset_t regs; |
ed9a39eb | 266 | |
41c49b06 | 267 | /* Get the thread id for the ptrace call. */ |
39f77062 | 268 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
269 | |
270 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
ed9a39eb JM |
271 | if (ret < 0) |
272 | { | |
edefbb7c | 273 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
274 | return; |
275 | } | |
276 | ||
34e8f22d | 277 | for (regno = ARM_A1_REGNUM; regno < ARM_PC_REGNUM; regno++) |
56be3814 | 278 | regcache_raw_supply (regcache, regno, (char *) ®s[regno]); |
ed9a39eb JM |
279 | |
280 | if (arm_apcs_32) | |
56be3814 | 281 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
17c12639 | 282 | (char *) ®s[ARM_CPSR_GREGNUM]); |
ed9a39eb | 283 | else |
56be3814 | 284 | regcache_raw_supply (regcache, ARM_PS_REGNUM, |
23a6d369 | 285 | (char *) ®s[ARM_PC_REGNUM]); |
ed9a39eb | 286 | |
bf6ae464 | 287 | regs[ARM_PC_REGNUM] = gdbarch_addr_bits_remove |
08790784 | 288 | (get_regcache_arch (regcache), regs[ARM_PC_REGNUM]); |
56be3814 | 289 | regcache_raw_supply (regcache, ARM_PC_REGNUM, |
23a6d369 | 290 | (char *) ®s[ARM_PC_REGNUM]); |
ed9a39eb JM |
291 | } |
292 | ||
293 | /* Store all general registers of the process from the values in | |
c6b92abd | 294 | regcache. */ |
ed9a39eb | 295 | |
41c49b06 | 296 | static void |
56be3814 | 297 | store_register (const struct regcache *regcache, int regno) |
41c49b06 SB |
298 | { |
299 | int ret, tid; | |
c2152441 | 300 | elf_gregset_t regs; |
41c49b06 | 301 | |
672c9795 | 302 | if (REG_VALID != regcache_register_status (regcache, regno)) |
41c49b06 SB |
303 | return; |
304 | ||
305 | /* Get the thread id for the ptrace call. */ | |
39f77062 | 306 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
307 | |
308 | /* Get the general registers from the process. */ | |
309 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
310 | if (ret < 0) | |
311 | { | |
edefbb7c | 312 | warning (_("Unable to fetch general registers.")); |
41c49b06 SB |
313 | return; |
314 | } | |
315 | ||
34e8f22d | 316 | if (regno >= ARM_A1_REGNUM && regno <= ARM_PC_REGNUM) |
56be3814 | 317 | regcache_raw_collect (regcache, regno, (char *) ®s[regno]); |
adb8a87c | 318 | else if (arm_apcs_32 && regno == ARM_PS_REGNUM) |
56be3814 | 319 | regcache_raw_collect (regcache, regno, |
17c12639 | 320 | (char *) ®s[ARM_CPSR_GREGNUM]); |
adb8a87c | 321 | else if (!arm_apcs_32 && regno == ARM_PS_REGNUM) |
56be3814 | 322 | regcache_raw_collect (regcache, ARM_PC_REGNUM, |
adb8a87c | 323 | (char *) ®s[ARM_PC_REGNUM]); |
41c49b06 SB |
324 | |
325 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); | |
326 | if (ret < 0) | |
327 | { | |
edefbb7c | 328 | warning (_("Unable to store general register.")); |
41c49b06 SB |
329 | return; |
330 | } | |
331 | } | |
332 | ||
ed9a39eb | 333 | static void |
56be3814 | 334 | store_regs (const struct regcache *regcache) |
ed9a39eb | 335 | { |
41c49b06 | 336 | int ret, regno, tid; |
c2152441 | 337 | elf_gregset_t regs; |
ed9a39eb | 338 | |
41c49b06 | 339 | /* Get the thread id for the ptrace call. */ |
39f77062 | 340 | tid = GET_THREAD_ID (inferior_ptid); |
41c49b06 SB |
341 | |
342 | /* Fetch the general registers. */ | |
343 | ret = ptrace (PTRACE_GETREGS, tid, 0, ®s); | |
ed9a39eb JM |
344 | if (ret < 0) |
345 | { | |
edefbb7c | 346 | warning (_("Unable to fetch general registers.")); |
ed9a39eb JM |
347 | return; |
348 | } | |
349 | ||
34e8f22d | 350 | for (regno = ARM_A1_REGNUM; regno <= ARM_PC_REGNUM; regno++) |
ed9a39eb | 351 | { |
672c9795 | 352 | if (REG_VALID == regcache_register_status (regcache, regno)) |
56be3814 | 353 | regcache_raw_collect (regcache, regno, (char *) ®s[regno]); |
ed9a39eb JM |
354 | } |
355 | ||
672c9795 | 356 | if (arm_apcs_32 && REG_VALID == regcache_register_status (regcache, ARM_PS_REGNUM)) |
56be3814 | 357 | regcache_raw_collect (regcache, ARM_PS_REGNUM, |
17c12639 | 358 | (char *) ®s[ARM_CPSR_GREGNUM]); |
adb8a87c | 359 | |
41c49b06 | 360 | ret = ptrace (PTRACE_SETREGS, tid, 0, ®s); |
ed9a39eb JM |
361 | |
362 | if (ret < 0) | |
363 | { | |
edefbb7c | 364 | warning (_("Unable to store general registers.")); |
ed9a39eb JM |
365 | return; |
366 | } | |
367 | } | |
368 | ||
05a4558a DJ |
369 | /* Fetch all WMMX registers of the process and store into |
370 | regcache. */ | |
371 | ||
372 | #define IWMMXT_REGS_SIZE (16 * 8 + 6 * 4) | |
373 | ||
374 | static void | |
56be3814 | 375 | fetch_wmmx_regs (struct regcache *regcache) |
05a4558a DJ |
376 | { |
377 | char regbuf[IWMMXT_REGS_SIZE]; | |
378 | int ret, regno, tid; | |
379 | ||
380 | /* Get the thread id for the ptrace call. */ | |
381 | tid = GET_THREAD_ID (inferior_ptid); | |
382 | ||
383 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
384 | if (ret < 0) | |
385 | { | |
386 | warning (_("Unable to fetch WMMX registers.")); | |
387 | return; | |
388 | } | |
389 | ||
390 | for (regno = 0; regno < 16; regno++) | |
56be3814 | 391 | regcache_raw_supply (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
392 | ®buf[regno * 8]); |
393 | ||
394 | for (regno = 0; regno < 2; regno++) | |
56be3814 | 395 | regcache_raw_supply (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
396 | ®buf[16 * 8 + regno * 4]); |
397 | ||
398 | for (regno = 0; regno < 4; regno++) | |
56be3814 | 399 | regcache_raw_supply (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
400 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
401 | } | |
402 | ||
403 | static void | |
56be3814 | 404 | store_wmmx_regs (const struct regcache *regcache) |
05a4558a DJ |
405 | { |
406 | char regbuf[IWMMXT_REGS_SIZE]; | |
407 | int ret, regno, tid; | |
408 | ||
409 | /* Get the thread id for the ptrace call. */ | |
410 | tid = GET_THREAD_ID (inferior_ptid); | |
411 | ||
412 | ret = ptrace (PTRACE_GETWMMXREGS, tid, 0, regbuf); | |
413 | if (ret < 0) | |
414 | { | |
415 | warning (_("Unable to fetch WMMX registers.")); | |
416 | return; | |
417 | } | |
418 | ||
419 | for (regno = 0; regno < 16; regno++) | |
672c9795 YQ |
420 | if (REG_VALID == regcache_register_status (regcache, |
421 | regno + ARM_WR0_REGNUM)) | |
56be3814 | 422 | regcache_raw_collect (regcache, regno + ARM_WR0_REGNUM, |
05a4558a DJ |
423 | ®buf[regno * 8]); |
424 | ||
425 | for (regno = 0; regno < 2; regno++) | |
672c9795 YQ |
426 | if (REG_VALID == regcache_register_status (regcache, |
427 | regno + ARM_WCSSF_REGNUM)) | |
56be3814 | 428 | regcache_raw_collect (regcache, regno + ARM_WCSSF_REGNUM, |
05a4558a DJ |
429 | ®buf[16 * 8 + regno * 4]); |
430 | ||
431 | for (regno = 0; regno < 4; regno++) | |
672c9795 YQ |
432 | if (REG_VALID == regcache_register_status (regcache, |
433 | regno + ARM_WCGR0_REGNUM)) | |
56be3814 | 434 | regcache_raw_collect (regcache, regno + ARM_WCGR0_REGNUM, |
05a4558a DJ |
435 | ®buf[16 * 8 + 2 * 4 + regno * 4]); |
436 | ||
437 | ret = ptrace (PTRACE_SETWMMXREGS, tid, 0, regbuf); | |
438 | ||
439 | if (ret < 0) | |
440 | { | |
441 | warning (_("Unable to store WMMX registers.")); | |
442 | return; | |
443 | } | |
444 | } | |
445 | ||
3b273a55 RE |
446 | /* Fetch and store VFP Registers. The kernel object has space for 32 |
447 | 64-bit registers, and the FPSCR. This is even when on a VFPv2 or | |
448 | VFPv3D16 target. */ | |
449 | #define VFP_REGS_SIZE (32 * 8 + 4) | |
450 | ||
451 | static void | |
452 | fetch_vfp_regs (struct regcache *regcache) | |
453 | { | |
454 | char regbuf[VFP_REGS_SIZE]; | |
455 | int ret, regno, tid; | |
330c6ca9 YQ |
456 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
457 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
458 | |
459 | /* Get the thread id for the ptrace call. */ | |
460 | tid = GET_THREAD_ID (inferior_ptid); | |
461 | ||
462 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
463 | if (ret < 0) | |
464 | { | |
465 | warning (_("Unable to fetch VFP registers.")); | |
466 | return; | |
467 | } | |
468 | ||
330c6ca9 | 469 | for (regno = 0; regno < tdep->vfp_register_count; regno++) |
3b273a55 RE |
470 | regcache_raw_supply (regcache, regno + ARM_D0_REGNUM, |
471 | (char *) regbuf + regno * 8); | |
472 | ||
473 | regcache_raw_supply (regcache, ARM_FPSCR_REGNUM, | |
474 | (char *) regbuf + 32 * 8); | |
475 | } | |
476 | ||
477 | static void | |
478 | store_vfp_regs (const struct regcache *regcache) | |
479 | { | |
480 | char regbuf[VFP_REGS_SIZE]; | |
481 | int ret, regno, tid; | |
330c6ca9 YQ |
482 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
483 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
3b273a55 RE |
484 | |
485 | /* Get the thread id for the ptrace call. */ | |
486 | tid = GET_THREAD_ID (inferior_ptid); | |
487 | ||
488 | ret = ptrace (PTRACE_GETVFPREGS, tid, 0, regbuf); | |
489 | if (ret < 0) | |
490 | { | |
491 | warning (_("Unable to fetch VFP registers (for update).")); | |
492 | return; | |
493 | } | |
494 | ||
330c6ca9 | 495 | for (regno = 0; regno < tdep->vfp_register_count; regno++) |
3b273a55 RE |
496 | regcache_raw_collect (regcache, regno + ARM_D0_REGNUM, |
497 | (char *) regbuf + regno * 8); | |
498 | ||
499 | regcache_raw_collect (regcache, ARM_FPSCR_REGNUM, | |
500 | (char *) regbuf + 32 * 8); | |
501 | ||
502 | ret = ptrace (PTRACE_SETVFPREGS, tid, 0, regbuf); | |
503 | ||
504 | if (ret < 0) | |
505 | { | |
506 | warning (_("Unable to store VFP registers.")); | |
507 | return; | |
508 | } | |
509 | } | |
510 | ||
ed9a39eb JM |
511 | /* Fetch registers from the child process. Fetch all registers if |
512 | regno == -1, otherwise fetch all general registers or all floating | |
513 | point registers depending upon the value of regno. */ | |
514 | ||
10d6c8cd | 515 | static void |
28439f5e PA |
516 | arm_linux_fetch_inferior_registers (struct target_ops *ops, |
517 | struct regcache *regcache, int regno) | |
ed9a39eb | 518 | { |
330c6ca9 YQ |
519 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
520 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
521 | ||
41c49b06 SB |
522 | if (-1 == regno) |
523 | { | |
56be3814 UW |
524 | fetch_regs (regcache); |
525 | fetch_fpregs (regcache); | |
a56cc1ce | 526 | if (tdep->have_wmmx_registers) |
56be3814 | 527 | fetch_wmmx_regs (regcache); |
330c6ca9 | 528 | if (tdep->vfp_register_count > 0) |
3b273a55 | 529 | fetch_vfp_regs (regcache); |
41c49b06 SB |
530 | } |
531 | else | |
532 | { | |
05a4558a | 533 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
56be3814 | 534 | fetch_register (regcache, regno); |
05a4558a | 535 | else if (regno >= ARM_F0_REGNUM && regno <= ARM_FPS_REGNUM) |
56be3814 | 536 | fetch_fpregister (regcache, regno); |
a56cc1ce | 537 | else if (tdep->have_wmmx_registers |
05a4558a | 538 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 539 | fetch_wmmx_regs (regcache); |
330c6ca9 | 540 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 541 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 542 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 543 | fetch_vfp_regs (regcache); |
41c49b06 | 544 | } |
ed9a39eb JM |
545 | } |
546 | ||
547 | /* Store registers back into the inferior. Store all registers if | |
548 | regno == -1, otherwise store all general registers or all floating | |
549 | point registers depending upon the value of regno. */ | |
550 | ||
10d6c8cd | 551 | static void |
28439f5e PA |
552 | arm_linux_store_inferior_registers (struct target_ops *ops, |
553 | struct regcache *regcache, int regno) | |
ed9a39eb | 554 | { |
330c6ca9 YQ |
555 | struct gdbarch *gdbarch = get_regcache_arch (regcache); |
556 | struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); | |
557 | ||
41c49b06 SB |
558 | if (-1 == regno) |
559 | { | |
56be3814 UW |
560 | store_regs (regcache); |
561 | store_fpregs (regcache); | |
a56cc1ce | 562 | if (tdep->have_wmmx_registers) |
56be3814 | 563 | store_wmmx_regs (regcache); |
330c6ca9 | 564 | if (tdep->vfp_register_count > 0) |
3b273a55 | 565 | store_vfp_regs (regcache); |
41c49b06 SB |
566 | } |
567 | else | |
568 | { | |
05a4558a | 569 | if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM) |
56be3814 | 570 | store_register (regcache, regno); |
05a4558a | 571 | else if ((regno >= ARM_F0_REGNUM) && (regno <= ARM_FPS_REGNUM)) |
56be3814 | 572 | store_fpregister (regcache, regno); |
a56cc1ce | 573 | else if (tdep->have_wmmx_registers |
05a4558a | 574 | && regno >= ARM_WR0_REGNUM && regno <= ARM_WCGR7_REGNUM) |
56be3814 | 575 | store_wmmx_regs (regcache); |
330c6ca9 | 576 | else if (tdep->vfp_register_count > 0 |
3b273a55 | 577 | && regno >= ARM_D0_REGNUM |
330c6ca9 | 578 | && regno <= ARM_D0_REGNUM + tdep->vfp_register_count) |
3b273a55 | 579 | store_vfp_regs (regcache); |
41c49b06 | 580 | } |
ed9a39eb JM |
581 | } |
582 | ||
cb587d83 DJ |
583 | /* Wrapper functions for the standard regset handling, used by |
584 | thread debugging. */ | |
41c49b06 SB |
585 | |
586 | void | |
7f7fe91e UW |
587 | fill_gregset (const struct regcache *regcache, |
588 | gdb_gregset_t *gregsetp, int regno) | |
41c49b06 | 589 | { |
7f7fe91e | 590 | arm_linux_collect_gregset (NULL, regcache, regno, gregsetp, 0); |
41c49b06 SB |
591 | } |
592 | ||
41c49b06 | 593 | void |
7f7fe91e | 594 | supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp) |
41c49b06 | 595 | { |
7f7fe91e | 596 | arm_linux_supply_gregset (NULL, regcache, -1, gregsetp, 0); |
41c49b06 SB |
597 | } |
598 | ||
41c49b06 | 599 | void |
7f7fe91e UW |
600 | fill_fpregset (const struct regcache *regcache, |
601 | gdb_fpregset_t *fpregsetp, int regno) | |
41c49b06 | 602 | { |
7f7fe91e | 603 | arm_linux_collect_nwfpe (NULL, regcache, regno, fpregsetp, 0); |
41c49b06 SB |
604 | } |
605 | ||
606 | /* Fill GDB's register array with the floating-point register values | |
607 | in *fpregsetp. */ | |
608 | ||
609 | void | |
7f7fe91e | 610 | supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp) |
ed9a39eb | 611 | { |
7f7fe91e | 612 | arm_linux_supply_nwfpe (NULL, regcache, -1, fpregsetp, 0); |
ed9a39eb JM |
613 | } |
614 | ||
9308fc88 DJ |
615 | /* Fetch the thread-local storage pointer for libthread_db. */ |
616 | ||
617 | ps_err_e | |
618 | ps_get_thread_area (const struct ps_prochandle *ph, | |
619 | lwpid_t lwpid, int idx, void **base) | |
620 | { | |
621 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
622 | return PS_ERR; | |
623 | ||
624 | /* IDX is the bias from the thread pointer to the beginning of the | |
625 | thread descriptor. It has to be subtracted due to implementation | |
626 | quirks in libthread_db. */ | |
627 | *base = (void *) ((char *)*base - idx); | |
628 | ||
629 | return PS_OK; | |
630 | } | |
631 | ||
81adfced DJ |
632 | static const struct target_desc * |
633 | arm_linux_read_description (struct target_ops *ops) | |
05a4558a | 634 | { |
3b273a55 | 635 | CORE_ADDR arm_hwcap = 0; |
05a4558a | 636 | |
3b273a55 RE |
637 | if (target_auxv_search (ops, AT_HWCAP, &arm_hwcap) != 1) |
638 | { | |
2117c711 | 639 | return ops->beneath->to_read_description (ops->beneath); |
3b273a55 | 640 | } |
81adfced | 641 | |
3b273a55 | 642 | if (arm_hwcap & HWCAP_IWMMXT) |
a56cc1ce | 643 | return tdesc_arm_with_iwmmxt; |
3b273a55 RE |
644 | |
645 | if (arm_hwcap & HWCAP_VFP) | |
646 | { | |
647 | int pid; | |
648 | char *buf; | |
649 | const struct target_desc * result = NULL; | |
650 | ||
651 | /* NEON implies VFPv3-D32 or no-VFP unit. Say that we only support | |
652 | Neon with VFPv3-D32. */ | |
653 | if (arm_hwcap & HWCAP_NEON) | |
330c6ca9 | 654 | result = tdesc_arm_with_neon; |
3b273a55 | 655 | else if ((arm_hwcap & (HWCAP_VFPv3 | HWCAP_VFPv3D16)) == HWCAP_VFPv3) |
330c6ca9 | 656 | result = tdesc_arm_with_vfpv3; |
3b273a55 | 657 | else |
330c6ca9 | 658 | result = tdesc_arm_with_vfpv2; |
3b273a55 RE |
659 | |
660 | /* Now make sure that the kernel supports reading these | |
661 | registers. Support was added in 2.6.30. */ | |
dfd4cc63 | 662 | pid = ptid_get_lwp (inferior_ptid); |
3b273a55 RE |
663 | errno = 0; |
664 | buf = alloca (VFP_REGS_SIZE); | |
665 | if (ptrace (PTRACE_GETVFPREGS, pid, 0, buf) < 0 | |
666 | && errno == EIO) | |
667 | result = NULL; | |
668 | ||
669 | return result; | |
670 | } | |
671 | ||
2117c711 | 672 | return ops->beneath->to_read_description (ops->beneath); |
05a4558a DJ |
673 | } |
674 | ||
e3039479 UW |
675 | /* Information describing the hardware breakpoint capabilities. */ |
676 | struct arm_linux_hwbp_cap | |
677 | { | |
678 | gdb_byte arch; | |
679 | gdb_byte max_wp_length; | |
680 | gdb_byte wp_count; | |
681 | gdb_byte bp_count; | |
682 | }; | |
683 | ||
638c5f49 OJ |
684 | /* Since we cannot dynamically allocate subfields of arm_linux_process_info, |
685 | assume a maximum number of supported break-/watchpoints. */ | |
686 | #define MAX_BPTS 16 | |
687 | #define MAX_WPTS 16 | |
688 | ||
e3039479 UW |
689 | /* Get hold of the Hardware Breakpoint information for the target we are |
690 | attached to. Returns NULL if the kernel doesn't support Hardware | |
691 | breakpoints at all, or a pointer to the information structure. */ | |
692 | static const struct arm_linux_hwbp_cap * | |
693 | arm_linux_get_hwbp_cap (void) | |
694 | { | |
695 | /* The info structure we return. */ | |
696 | static struct arm_linux_hwbp_cap info; | |
697 | ||
698 | /* Is INFO in a good state? -1 means that no attempt has been made to | |
699 | initialize INFO; 0 means an attempt has been made, but it failed; 1 | |
700 | means INFO is in an initialized state. */ | |
701 | static int available = -1; | |
702 | ||
703 | if (available == -1) | |
704 | { | |
705 | int tid; | |
706 | unsigned int val; | |
707 | ||
708 | tid = GET_THREAD_ID (inferior_ptid); | |
709 | if (ptrace (PTRACE_GETHBPREGS, tid, 0, &val) < 0) | |
710 | available = 0; | |
711 | else | |
712 | { | |
713 | info.arch = (gdb_byte)((val >> 24) & 0xff); | |
714 | info.max_wp_length = (gdb_byte)((val >> 16) & 0xff); | |
715 | info.wp_count = (gdb_byte)((val >> 8) & 0xff); | |
716 | info.bp_count = (gdb_byte)(val & 0xff); | |
638c5f49 OJ |
717 | |
718 | if (info.wp_count > MAX_WPTS) | |
719 | { | |
720 | warning (_("arm-linux-gdb supports %d hardware watchpoints but target \ | |
721 | supports %d"), MAX_WPTS, info.wp_count); | |
722 | info.wp_count = MAX_WPTS; | |
723 | } | |
724 | ||
725 | if (info.bp_count > MAX_BPTS) | |
726 | { | |
727 | warning (_("arm-linux-gdb supports %d hardware breakpoints but target \ | |
728 | supports %d"), MAX_BPTS, info.bp_count); | |
729 | info.bp_count = MAX_BPTS; | |
730 | } | |
e3039479 UW |
731 | available = (info.arch != 0); |
732 | } | |
733 | } | |
734 | ||
735 | return available == 1 ? &info : NULL; | |
736 | } | |
737 | ||
738 | /* How many hardware breakpoints are available? */ | |
739 | static int | |
740 | arm_linux_get_hw_breakpoint_count (void) | |
741 | { | |
742 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
743 | return cap != NULL ? cap->bp_count : 0; | |
744 | } | |
745 | ||
746 | /* How many hardware watchpoints are available? */ | |
747 | static int | |
748 | arm_linux_get_hw_watchpoint_count (void) | |
749 | { | |
750 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
751 | return cap != NULL ? cap->wp_count : 0; | |
752 | } | |
753 | ||
754 | /* Have we got a free break-/watch-point available for use? Returns -1 if | |
755 | there is not an appropriate resource available, otherwise returns 1. */ | |
756 | static int | |
5461485a TT |
757 | arm_linux_can_use_hw_breakpoint (struct target_ops *self, |
758 | int type, int cnt, int ot) | |
e3039479 UW |
759 | { |
760 | if (type == bp_hardware_watchpoint || type == bp_read_watchpoint | |
761 | || type == bp_access_watchpoint || type == bp_watchpoint) | |
762 | { | |
dbbf180a YQ |
763 | int count = arm_linux_get_hw_watchpoint_count (); |
764 | ||
765 | if (count == 0) | |
766 | return 0; | |
767 | else if (cnt + ot > count) | |
e3039479 UW |
768 | return -1; |
769 | } | |
770 | else if (type == bp_hardware_breakpoint) | |
771 | { | |
dbbf180a YQ |
772 | int count = arm_linux_get_hw_breakpoint_count (); |
773 | ||
774 | if (count == 0) | |
775 | return 0; | |
776 | else if (cnt > count) | |
e3039479 UW |
777 | return -1; |
778 | } | |
779 | else | |
780 | gdb_assert (FALSE); | |
781 | ||
782 | return 1; | |
783 | } | |
784 | ||
785 | /* Enum describing the different types of ARM hardware break-/watch-points. */ | |
786 | typedef enum | |
787 | { | |
788 | arm_hwbp_break = 0, | |
789 | arm_hwbp_load = 1, | |
790 | arm_hwbp_store = 2, | |
791 | arm_hwbp_access = 3 | |
792 | } arm_hwbp_type; | |
793 | ||
794 | /* Type describing an ARM Hardware Breakpoint Control register value. */ | |
795 | typedef unsigned int arm_hwbp_control_t; | |
796 | ||
797 | /* Structure used to keep track of hardware break-/watch-points. */ | |
798 | struct arm_linux_hw_breakpoint | |
799 | { | |
800 | /* Address to break on, or being watched. */ | |
801 | unsigned int address; | |
802 | /* Control register for break-/watch- point. */ | |
803 | arm_hwbp_control_t control; | |
804 | }; | |
805 | ||
638c5f49 OJ |
806 | /* Structure containing arrays of per process hardware break-/watchpoints |
807 | for caching address and control information. | |
e3039479 UW |
808 | |
809 | The Linux ptrace interface to hardware break-/watch-points presents the | |
810 | values in a vector centred around 0 (which is used fo generic information). | |
811 | Positive indicies refer to breakpoint addresses/control registers, negative | |
812 | indices to watchpoint addresses/control registers. | |
813 | ||
814 | The Linux vector is indexed as follows: | |
815 | -((i << 1) + 2): Control register for watchpoint i. | |
816 | -((i << 1) + 1): Address register for watchpoint i. | |
817 | 0: Information register. | |
818 | ((i << 1) + 1): Address register for breakpoint i. | |
819 | ((i << 1) + 2): Control register for breakpoint i. | |
820 | ||
821 | This structure is used as a per-thread cache of the state stored by the | |
822 | kernel, so that we don't need to keep calling into the kernel to find a | |
823 | free breakpoint. | |
824 | ||
825 | We treat break-/watch-points with their enable bit clear as being deleted. | |
826 | */ | |
638c5f49 | 827 | struct arm_linux_debug_reg_state |
e3039479 | 828 | { |
638c5f49 OJ |
829 | /* Hardware breakpoints for this process. */ |
830 | struct arm_linux_hw_breakpoint bpts[MAX_BPTS]; | |
831 | /* Hardware watchpoints for this process. */ | |
832 | struct arm_linux_hw_breakpoint wpts[MAX_WPTS]; | |
833 | }; | |
834 | ||
835 | /* Per-process arch-specific data we want to keep. */ | |
836 | struct arm_linux_process_info | |
e3039479 | 837 | { |
638c5f49 OJ |
838 | /* Linked list. */ |
839 | struct arm_linux_process_info *next; | |
840 | /* The process identifier. */ | |
841 | pid_t pid; | |
842 | /* Hardware break-/watchpoints state information. */ | |
843 | struct arm_linux_debug_reg_state state; | |
e3039479 | 844 | |
638c5f49 OJ |
845 | }; |
846 | ||
847 | /* Per-thread arch-specific data we want to keep. */ | |
848 | struct arch_lwp_info | |
849 | { | |
850 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
851 | char bpts_changed[MAX_BPTS]; | |
852 | char wpts_changed[MAX_WPTS]; | |
853 | }; | |
854 | ||
855 | static struct arm_linux_process_info *arm_linux_process_list = NULL; | |
856 | ||
857 | /* Find process data for process PID. */ | |
858 | ||
859 | static struct arm_linux_process_info * | |
860 | arm_linux_find_process_pid (pid_t pid) | |
861 | { | |
862 | struct arm_linux_process_info *proc; | |
863 | ||
864 | for (proc = arm_linux_process_list; proc; proc = proc->next) | |
865 | if (proc->pid == pid) | |
866 | return proc; | |
867 | ||
868 | return NULL; | |
869 | } | |
870 | ||
871 | /* Add process data for process PID. Returns newly allocated info | |
872 | object. */ | |
873 | ||
874 | static struct arm_linux_process_info * | |
875 | arm_linux_add_process (pid_t pid) | |
876 | { | |
877 | struct arm_linux_process_info *proc; | |
e3039479 | 878 | |
638c5f49 OJ |
879 | proc = xcalloc (1, sizeof (*proc)); |
880 | proc->pid = pid; | |
e3039479 | 881 | |
638c5f49 OJ |
882 | proc->next = arm_linux_process_list; |
883 | arm_linux_process_list = proc; | |
884 | ||
885 | return proc; | |
886 | } | |
887 | ||
888 | /* Get data specific info for process PID, creating it if necessary. | |
889 | Never returns NULL. */ | |
890 | ||
891 | static struct arm_linux_process_info * | |
892 | arm_linux_process_info_get (pid_t pid) | |
893 | { | |
894 | struct arm_linux_process_info *proc; | |
895 | ||
896 | proc = arm_linux_find_process_pid (pid); | |
897 | if (proc == NULL) | |
898 | proc = arm_linux_add_process (pid); | |
899 | ||
900 | return proc; | |
901 | } | |
902 | ||
903 | /* Called whenever GDB is no longer debugging process PID. It deletes | |
904 | data structures that keep track of debug register state. */ | |
905 | ||
906 | static void | |
907 | arm_linux_forget_process (pid_t pid) | |
908 | { | |
909 | struct arm_linux_process_info *proc, **proc_link; | |
910 | ||
911 | proc = arm_linux_process_list; | |
912 | proc_link = &arm_linux_process_list; | |
913 | ||
914 | while (proc != NULL) | |
915 | { | |
916 | if (proc->pid == pid) | |
e3039479 | 917 | { |
638c5f49 OJ |
918 | *proc_link = proc->next; |
919 | ||
920 | xfree (proc); | |
921 | return; | |
e3039479 UW |
922 | } |
923 | ||
638c5f49 OJ |
924 | proc_link = &proc->next; |
925 | proc = *proc_link; | |
926 | } | |
927 | } | |
928 | ||
929 | /* Get hardware break-/watchpoint state for process PID. */ | |
930 | ||
931 | static struct arm_linux_debug_reg_state * | |
932 | arm_linux_get_debug_reg_state (pid_t pid) | |
933 | { | |
934 | return &arm_linux_process_info_get (pid)->state; | |
e3039479 UW |
935 | } |
936 | ||
937 | /* Initialize an ARM hardware break-/watch-point control register value. | |
938 | BYTE_ADDRESS_SELECT is the mask of bytes to trigger on; HWBP_TYPE is the | |
939 | type of break-/watch-point; ENABLE indicates whether the point is enabled. | |
940 | */ | |
941 | static arm_hwbp_control_t | |
942 | arm_hwbp_control_initialize (unsigned byte_address_select, | |
943 | arm_hwbp_type hwbp_type, | |
944 | int enable) | |
945 | { | |
946 | gdb_assert ((byte_address_select & ~0xffU) == 0); | |
947 | gdb_assert (hwbp_type != arm_hwbp_break | |
948 | || ((byte_address_select & 0xfU) != 0)); | |
949 | ||
950 | return (byte_address_select << 5) | (hwbp_type << 3) | (3 << 1) | enable; | |
951 | } | |
952 | ||
953 | /* Does the breakpoint control value CONTROL have the enable bit set? */ | |
954 | static int | |
955 | arm_hwbp_control_is_enabled (arm_hwbp_control_t control) | |
956 | { | |
957 | return control & 0x1; | |
958 | } | |
959 | ||
960 | /* Change a breakpoint control word so that it is in the disabled state. */ | |
961 | static arm_hwbp_control_t | |
962 | arm_hwbp_control_disable (arm_hwbp_control_t control) | |
963 | { | |
964 | return control & ~0x1; | |
965 | } | |
966 | ||
967 | /* Initialise the hardware breakpoint structure P. The breakpoint will be | |
968 | enabled, and will point to the placed address of BP_TGT. */ | |
969 | static void | |
970 | arm_linux_hw_breakpoint_initialize (struct gdbarch *gdbarch, | |
971 | struct bp_target_info *bp_tgt, | |
972 | struct arm_linux_hw_breakpoint *p) | |
973 | { | |
974 | unsigned mask; | |
0d5ed153 | 975 | CORE_ADDR address = bp_tgt->placed_address = bp_tgt->reqstd_address; |
e3039479 UW |
976 | |
977 | /* We have to create a mask for the control register which says which bits | |
978 | of the word pointed to by address to break on. */ | |
979 | if (arm_pc_is_thumb (gdbarch, address)) | |
fcf303ab UW |
980 | { |
981 | mask = 0x3; | |
982 | address &= ~1; | |
983 | } | |
e3039479 | 984 | else |
fcf303ab UW |
985 | { |
986 | mask = 0xf; | |
987 | address &= ~3; | |
988 | } | |
e3039479 | 989 | |
fcf303ab | 990 | p->address = (unsigned int) address; |
e3039479 UW |
991 | p->control = arm_hwbp_control_initialize (mask, arm_hwbp_break, 1); |
992 | } | |
993 | ||
994 | /* Get the ARM hardware breakpoint type from the RW value we're given when | |
995 | asked to set a watchpoint. */ | |
996 | static arm_hwbp_type | |
997 | arm_linux_get_hwbp_type (int rw) | |
998 | { | |
999 | if (rw == hw_read) | |
1000 | return arm_hwbp_load; | |
1001 | else if (rw == hw_write) | |
1002 | return arm_hwbp_store; | |
1003 | else | |
1004 | return arm_hwbp_access; | |
1005 | } | |
1006 | ||
1007 | /* Initialize the hardware breakpoint structure P for a watchpoint at ADDR | |
1008 | to LEN. The type of watchpoint is given in RW. */ | |
1009 | static void | |
1010 | arm_linux_hw_watchpoint_initialize (CORE_ADDR addr, int len, int rw, | |
1011 | struct arm_linux_hw_breakpoint *p) | |
1012 | { | |
1013 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1014 | unsigned mask; | |
1015 | ||
1016 | gdb_assert (cap != NULL); | |
1017 | gdb_assert (cap->max_wp_length != 0); | |
1018 | ||
1019 | mask = (1 << len) - 1; | |
1020 | ||
1021 | p->address = (unsigned int) addr; | |
1022 | p->control = arm_hwbp_control_initialize (mask, | |
1023 | arm_linux_get_hwbp_type (rw), 1); | |
1024 | } | |
1025 | ||
1026 | /* Are two break-/watch-points equal? */ | |
1027 | static int | |
1028 | arm_linux_hw_breakpoint_equal (const struct arm_linux_hw_breakpoint *p1, | |
1029 | const struct arm_linux_hw_breakpoint *p2) | |
1030 | { | |
1031 | return p1->address == p2->address && p1->control == p2->control; | |
1032 | } | |
1033 | ||
638c5f49 OJ |
1034 | /* Callback to mark a watch-/breakpoint to be updated in all threads of |
1035 | the current process. */ | |
1036 | ||
1037 | struct update_registers_data | |
1038 | { | |
1039 | int watch; | |
1040 | int index; | |
1041 | }; | |
1042 | ||
1043 | static int | |
1044 | update_registers_callback (struct lwp_info *lwp, void *arg) | |
1045 | { | |
1046 | struct update_registers_data *data = (struct update_registers_data *) arg; | |
1047 | ||
1048 | if (lwp->arch_private == NULL) | |
1049 | lwp->arch_private = XCNEW (struct arch_lwp_info); | |
1050 | ||
1051 | /* The actual update is done later just before resuming the lwp, | |
1052 | we just mark that the registers need updating. */ | |
1053 | if (data->watch) | |
1054 | lwp->arch_private->wpts_changed[data->index] = 1; | |
1055 | else | |
1056 | lwp->arch_private->bpts_changed[data->index] = 1; | |
1057 | ||
1058 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
1059 | we can update its breakpoint registers. */ | |
1060 | if (!lwp->stopped) | |
1061 | linux_stop_lwp (lwp); | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
e3039479 UW |
1066 | /* Insert the hardware breakpoint (WATCHPOINT = 0) or watchpoint (WATCHPOINT |
1067 | =1) BPT for thread TID. */ | |
1068 | static void | |
1069 | arm_linux_insert_hw_breakpoint1 (const struct arm_linux_hw_breakpoint* bpt, | |
638c5f49 | 1070 | int watchpoint) |
e3039479 | 1071 | { |
638c5f49 OJ |
1072 | int pid; |
1073 | ptid_t pid_ptid; | |
e3039479 UW |
1074 | gdb_byte count, i; |
1075 | struct arm_linux_hw_breakpoint* bpts; | |
638c5f49 | 1076 | struct update_registers_data data; |
e3039479 | 1077 | |
638c5f49 OJ |
1078 | pid = ptid_get_pid (inferior_ptid); |
1079 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1080 | |
1081 | if (watchpoint) | |
1082 | { | |
1083 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1084 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1085 | } |
1086 | else | |
1087 | { | |
1088 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1089 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1090 | } |
1091 | ||
1092 | for (i = 0; i < count; ++i) | |
1093 | if (!arm_hwbp_control_is_enabled (bpts[i].control)) | |
1094 | { | |
638c5f49 OJ |
1095 | data.watch = watchpoint; |
1096 | data.index = i; | |
1097 | bpts[i] = *bpt; | |
1098 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1099 | break; | |
e3039479 UW |
1100 | } |
1101 | ||
1102 | gdb_assert (i != count); | |
1103 | } | |
1104 | ||
1105 | /* Remove the hardware breakpoint (WATCHPOINT = 0) or watchpoint | |
1106 | (WATCHPOINT = 1) BPT for thread TID. */ | |
1107 | static void | |
1108 | arm_linux_remove_hw_breakpoint1 (const struct arm_linux_hw_breakpoint *bpt, | |
638c5f49 | 1109 | int watchpoint) |
e3039479 | 1110 | { |
638c5f49 | 1111 | int pid; |
e3039479 | 1112 | gdb_byte count, i; |
638c5f49 OJ |
1113 | ptid_t pid_ptid; |
1114 | struct arm_linux_hw_breakpoint* bpts; | |
1115 | struct update_registers_data data; | |
e3039479 | 1116 | |
638c5f49 OJ |
1117 | pid = ptid_get_pid (inferior_ptid); |
1118 | pid_ptid = pid_to_ptid (pid); | |
e3039479 UW |
1119 | |
1120 | if (watchpoint) | |
1121 | { | |
1122 | count = arm_linux_get_hw_watchpoint_count (); | |
638c5f49 | 1123 | bpts = arm_linux_get_debug_reg_state (pid)->wpts; |
e3039479 UW |
1124 | } |
1125 | else | |
1126 | { | |
1127 | count = arm_linux_get_hw_breakpoint_count (); | |
638c5f49 | 1128 | bpts = arm_linux_get_debug_reg_state (pid)->bpts; |
e3039479 UW |
1129 | } |
1130 | ||
1131 | for (i = 0; i < count; ++i) | |
1132 | if (arm_linux_hw_breakpoint_equal (bpt, bpts + i)) | |
1133 | { | |
638c5f49 OJ |
1134 | data.watch = watchpoint; |
1135 | data.index = i; | |
1136 | bpts[i].control = arm_hwbp_control_disable (bpts[i].control); | |
1137 | iterate_over_lwps (pid_ptid, update_registers_callback, &data); | |
1138 | break; | |
e3039479 UW |
1139 | } |
1140 | ||
1141 | gdb_assert (i != count); | |
1142 | } | |
1143 | ||
1144 | /* Insert a Hardware breakpoint. */ | |
1145 | static int | |
23a26771 TT |
1146 | arm_linux_insert_hw_breakpoint (struct target_ops *self, |
1147 | struct gdbarch *gdbarch, | |
e3039479 UW |
1148 | struct bp_target_info *bp_tgt) |
1149 | { | |
e3039479 UW |
1150 | struct lwp_info *lp; |
1151 | struct arm_linux_hw_breakpoint p; | |
1152 | ||
1153 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1154 | return -1; | |
1155 | ||
1156 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1157 | |
1158 | arm_linux_insert_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1159 | |
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | /* Remove a hardware breakpoint. */ | |
1164 | static int | |
a64dc96c TT |
1165 | arm_linux_remove_hw_breakpoint (struct target_ops *self, |
1166 | struct gdbarch *gdbarch, | |
e3039479 UW |
1167 | struct bp_target_info *bp_tgt) |
1168 | { | |
e3039479 UW |
1169 | struct lwp_info *lp; |
1170 | struct arm_linux_hw_breakpoint p; | |
1171 | ||
1172 | if (arm_linux_get_hw_breakpoint_count () == 0) | |
1173 | return -1; | |
1174 | ||
1175 | arm_linux_hw_breakpoint_initialize (gdbarch, bp_tgt, &p); | |
638c5f49 OJ |
1176 | |
1177 | arm_linux_remove_hw_breakpoint1 (&p, 0); | |
e3039479 UW |
1178 | |
1179 | return 0; | |
1180 | } | |
1181 | ||
1182 | /* Are we able to use a hardware watchpoint for the LEN bytes starting at | |
1183 | ADDR? */ | |
1184 | static int | |
31568a15 TT |
1185 | arm_linux_region_ok_for_hw_watchpoint (struct target_ops *self, |
1186 | CORE_ADDR addr, int len) | |
e3039479 UW |
1187 | { |
1188 | const struct arm_linux_hwbp_cap *cap = arm_linux_get_hwbp_cap (); | |
1189 | CORE_ADDR max_wp_length, aligned_addr; | |
1190 | ||
1191 | /* Can not set watchpoints for zero or negative lengths. */ | |
1192 | if (len <= 0) | |
1193 | return 0; | |
1194 | ||
1195 | /* Need to be able to use the ptrace interface. */ | |
1196 | if (cap == NULL || cap->wp_count == 0) | |
1197 | return 0; | |
1198 | ||
1199 | /* Test that the range [ADDR, ADDR + LEN) fits into the largest address | |
1200 | range covered by a watchpoint. */ | |
1201 | max_wp_length = (CORE_ADDR)cap->max_wp_length; | |
1202 | aligned_addr = addr & ~(max_wp_length - 1); | |
1203 | ||
1204 | if (aligned_addr + max_wp_length < addr + len) | |
1205 | return 0; | |
1206 | ||
1207 | /* The current ptrace interface can only handle watchpoints that are a | |
1208 | power of 2. */ | |
1209 | if ((len & (len - 1)) != 0) | |
1210 | return 0; | |
1211 | ||
1212 | /* All tests passed so we must be able to set a watchpoint. */ | |
1213 | return 1; | |
1214 | } | |
1215 | ||
1216 | /* Insert a Hardware breakpoint. */ | |
1217 | static int | |
7bb99c53 TT |
1218 | arm_linux_insert_watchpoint (struct target_ops *self, |
1219 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1220 | struct expression *cond) |
1221 | { | |
e3039479 UW |
1222 | struct lwp_info *lp; |
1223 | struct arm_linux_hw_breakpoint p; | |
1224 | ||
1225 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1226 | return -1; | |
1227 | ||
1228 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1229 | |
1230 | arm_linux_insert_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1231 | |
1232 | return 0; | |
1233 | } | |
1234 | ||
1235 | /* Remove a hardware breakpoint. */ | |
1236 | static int | |
11b5219a TT |
1237 | arm_linux_remove_watchpoint (struct target_ops *self, |
1238 | CORE_ADDR addr, int len, int rw, | |
e3039479 UW |
1239 | struct expression *cond) |
1240 | { | |
e3039479 UW |
1241 | struct lwp_info *lp; |
1242 | struct arm_linux_hw_breakpoint p; | |
1243 | ||
1244 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1245 | return -1; | |
1246 | ||
1247 | arm_linux_hw_watchpoint_initialize (addr, len, rw, &p); | |
638c5f49 OJ |
1248 | |
1249 | arm_linux_remove_hw_breakpoint1 (&p, 1); | |
e3039479 UW |
1250 | |
1251 | return 0; | |
1252 | } | |
1253 | ||
1254 | /* What was the data address the target was stopped on accessing. */ | |
1255 | static int | |
1256 | arm_linux_stopped_data_address (struct target_ops *target, CORE_ADDR *addr_p) | |
1257 | { | |
f865ee35 JK |
1258 | siginfo_t siginfo; |
1259 | int slot; | |
1260 | ||
1261 | if (!linux_nat_get_siginfo (inferior_ptid, &siginfo)) | |
1262 | return 0; | |
e3039479 UW |
1263 | |
1264 | /* This must be a hardware breakpoint. */ | |
f865ee35 JK |
1265 | if (siginfo.si_signo != SIGTRAP |
1266 | || (siginfo.si_code & 0xffff) != 0x0004 /* TRAP_HWBKPT */) | |
e3039479 UW |
1267 | return 0; |
1268 | ||
1269 | /* We must be able to set hardware watchpoints. */ | |
1270 | if (arm_linux_get_hw_watchpoint_count () == 0) | |
1271 | return 0; | |
1272 | ||
f865ee35 JK |
1273 | slot = siginfo.si_errno; |
1274 | ||
e3039479 UW |
1275 | /* If we are in a positive slot then we're looking at a breakpoint and not |
1276 | a watchpoint. */ | |
1277 | if (slot >= 0) | |
1278 | return 0; | |
1279 | ||
f865ee35 | 1280 | *addr_p = (CORE_ADDR) (uintptr_t) siginfo.si_addr; |
e3039479 UW |
1281 | return 1; |
1282 | } | |
1283 | ||
1284 | /* Has the target been stopped by hitting a watchpoint? */ | |
1285 | static int | |
6a109b6b | 1286 | arm_linux_stopped_by_watchpoint (struct target_ops *ops) |
e3039479 UW |
1287 | { |
1288 | CORE_ADDR addr; | |
6a109b6b | 1289 | return arm_linux_stopped_data_address (ops, &addr); |
e3039479 UW |
1290 | } |
1291 | ||
1292 | static int | |
1293 | arm_linux_watchpoint_addr_within_range (struct target_ops *target, | |
1294 | CORE_ADDR addr, | |
1295 | CORE_ADDR start, int length) | |
1296 | { | |
1297 | return start <= addr && start + length - 1 >= addr; | |
1298 | } | |
1299 | ||
1300 | /* Handle thread creation. We need to copy the breakpoints and watchpoints | |
1301 | in the parent thread to the child thread. */ | |
1302 | static void | |
7b50312a | 1303 | arm_linux_new_thread (struct lwp_info *lp) |
e3039479 | 1304 | { |
638c5f49 OJ |
1305 | int i; |
1306 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); | |
1307 | ||
1308 | /* Mark that all the hardware breakpoint/watchpoint register pairs | |
1309 | for this thread need to be initialized. */ | |
e3039479 | 1310 | |
638c5f49 | 1311 | for (i = 0; i < MAX_BPTS; i++) |
e3039479 | 1312 | { |
638c5f49 OJ |
1313 | info->bpts_changed[i] = 1; |
1314 | info->wpts_changed[i] = 1; | |
e3039479 | 1315 | } |
638c5f49 OJ |
1316 | |
1317 | lp->arch_private = info; | |
e3039479 UW |
1318 | } |
1319 | ||
638c5f49 OJ |
1320 | /* Called when resuming a thread. |
1321 | The hardware debug registers are updated when there is any change. */ | |
1322 | ||
e3039479 | 1323 | static void |
638c5f49 | 1324 | arm_linux_prepare_to_resume (struct lwp_info *lwp) |
e3039479 | 1325 | { |
638c5f49 OJ |
1326 | int pid, i; |
1327 | struct arm_linux_hw_breakpoint *bpts, *wpts; | |
1328 | struct arch_lwp_info *arm_lwp_info = lwp->arch_private; | |
1329 | ||
1330 | pid = ptid_get_lwp (lwp->ptid); | |
1331 | bpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->bpts; | |
1332 | wpts = arm_linux_get_debug_reg_state (ptid_get_pid (lwp->ptid))->wpts; | |
1333 | ||
1334 | /* NULL means this is the main thread still going through the shell, | |
1335 | or, no watchpoint has been set yet. In that case, there's | |
1336 | nothing to do. */ | |
1337 | if (arm_lwp_info == NULL) | |
1338 | return; | |
e3039479 | 1339 | |
638c5f49 OJ |
1340 | for (i = 0; i < arm_linux_get_hw_breakpoint_count (); i++) |
1341 | if (arm_lwp_info->bpts_changed[i]) | |
1342 | { | |
1343 | errno = 0; | |
1344 | if (arm_hwbp_control_is_enabled (bpts[i].control)) | |
1345 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1346 | (PTRACE_TYPE_ARG3) ((i << 1) + 1), &bpts[i].address) < 0) | |
1347 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1348 | ||
1349 | if (bpts[i].control != 0) | |
1350 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1351 | (PTRACE_TYPE_ARG3) ((i << 1) + 2), &bpts[i].control) < 0) | |
1352 | perror_with_name (_("Unexpected error setting breakpoint")); | |
1353 | ||
1354 | arm_lwp_info->bpts_changed[i] = 0; | |
1355 | } | |
e3039479 | 1356 | |
638c5f49 OJ |
1357 | for (i = 0; i < arm_linux_get_hw_watchpoint_count (); i++) |
1358 | if (arm_lwp_info->wpts_changed[i]) | |
1359 | { | |
1360 | errno = 0; | |
1361 | if (arm_hwbp_control_is_enabled (wpts[i].control)) | |
1362 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1363 | (PTRACE_TYPE_ARG3) -((i << 1) + 1), &wpts[i].address) < 0) | |
1364 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1365 | ||
1366 | if (wpts[i].control != 0) | |
1367 | if (ptrace (PTRACE_SETHBPREGS, pid, | |
1368 | (PTRACE_TYPE_ARG3) -((i << 1) + 2), &wpts[i].control) < 0) | |
1369 | perror_with_name (_("Unexpected error setting watchpoint")); | |
1370 | ||
1371 | arm_lwp_info->wpts_changed[i] = 0; | |
1372 | } | |
1373 | } | |
1374 | ||
1375 | /* linux_nat_new_fork hook. */ | |
1376 | ||
1377 | static void | |
1378 | arm_linux_new_fork (struct lwp_info *parent, pid_t child_pid) | |
1379 | { | |
1380 | pid_t parent_pid; | |
1381 | struct arm_linux_debug_reg_state *parent_state; | |
1382 | struct arm_linux_debug_reg_state *child_state; | |
e3039479 | 1383 | |
638c5f49 OJ |
1384 | /* NULL means no watchpoint has ever been set in the parent. In |
1385 | that case, there's nothing to do. */ | |
1386 | if (parent->arch_private == NULL) | |
1387 | return; | |
e3039479 | 1388 | |
638c5f49 OJ |
1389 | /* GDB core assumes the child inherits the watchpoints/hw |
1390 | breakpoints of the parent, and will remove them all from the | |
1391 | forked off process. Copy the debug registers mirrors into the | |
1392 | new process so that all breakpoints and watchpoints can be | |
1393 | removed together. */ | |
e3039479 | 1394 | |
638c5f49 OJ |
1395 | parent_pid = ptid_get_pid (parent->ptid); |
1396 | parent_state = arm_linux_get_debug_reg_state (parent_pid); | |
1397 | child_state = arm_linux_get_debug_reg_state (child_pid); | |
1398 | *child_state = *parent_state; | |
e3039479 UW |
1399 | } |
1400 | ||
10d6c8cd DJ |
1401 | void _initialize_arm_linux_nat (void); |
1402 | ||
ed9a39eb JM |
1403 | void |
1404 | _initialize_arm_linux_nat (void) | |
1405 | { | |
10d6c8cd DJ |
1406 | struct target_ops *t; |
1407 | ||
10d6c8cd DJ |
1408 | /* Fill in the generic GNU/Linux methods. */ |
1409 | t = linux_target (); | |
1410 | ||
1411 | /* Add our register access methods. */ | |
1412 | t->to_fetch_registers = arm_linux_fetch_inferior_registers; | |
1413 | t->to_store_registers = arm_linux_store_inferior_registers; | |
1414 | ||
e3039479 UW |
1415 | /* Add our hardware breakpoint and watchpoint implementation. */ |
1416 | t->to_can_use_hw_breakpoint = arm_linux_can_use_hw_breakpoint; | |
1417 | t->to_insert_hw_breakpoint = arm_linux_insert_hw_breakpoint; | |
1418 | t->to_remove_hw_breakpoint = arm_linux_remove_hw_breakpoint; | |
1419 | t->to_region_ok_for_hw_watchpoint = arm_linux_region_ok_for_hw_watchpoint; | |
1420 | t->to_insert_watchpoint = arm_linux_insert_watchpoint; | |
1421 | t->to_remove_watchpoint = arm_linux_remove_watchpoint; | |
1422 | t->to_stopped_by_watchpoint = arm_linux_stopped_by_watchpoint; | |
1423 | t->to_stopped_data_address = arm_linux_stopped_data_address; | |
1424 | t->to_watchpoint_addr_within_range = arm_linux_watchpoint_addr_within_range; | |
1425 | ||
81adfced | 1426 | t->to_read_description = arm_linux_read_description; |
05a4558a | 1427 | |
10d6c8cd | 1428 | /* Register the target. */ |
f973ed9c | 1429 | linux_nat_add_target (t); |
e3039479 | 1430 | |
638c5f49 | 1431 | /* Handle thread creation and exit. */ |
e3039479 | 1432 | linux_nat_set_new_thread (t, arm_linux_new_thread); |
638c5f49 OJ |
1433 | linux_nat_set_prepare_to_resume (t, arm_linux_prepare_to_resume); |
1434 | ||
1435 | /* Handle process creation and exit. */ | |
1436 | linux_nat_set_new_fork (t, arm_linux_new_fork); | |
1437 | linux_nat_set_forget_process (t, arm_linux_forget_process); | |
ed9a39eb | 1438 | } |