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ed9a39eb JM |
1 | /* Common target dependent code for GDB on ARM systems. |
2 | Copyright 1988, 1989, 1991, 1992, 1993, 1995-1999 | |
c906108c SS |
3 | Free Software Foundation, Inc. |
4 | ||
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2 of the License, or | |
10 | (at your option) any later version. | |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b JM |
17 | You should have received a copy of the GNU General Public License |
18 | along with this program; if not, write to the Free Software | |
19 | Foundation, Inc., 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
c906108c SS |
21 | |
22 | #include "defs.h" | |
23 | #include "frame.h" | |
24 | #include "inferior.h" | |
25 | #include "gdbcmd.h" | |
26 | #include "gdbcore.h" | |
27 | #include "symfile.h" | |
28 | #include "gdb_string.h" | |
29 | #include "coff/internal.h" /* Internal format of COFF symbols in BFD */ | |
30 | ||
ed9a39eb JM |
31 | extern void _initialize_arm_tdep (void); |
32 | ||
c906108c | 33 | /* |
c5aa993b JM |
34 | The following macros are actually wrong. Neither arm nor thumb can |
35 | or should set the lsb on addr. | |
36 | The thumb addresses are mod 2, so (addr & 2) would be a good heuristic | |
37 | to use when checking for thumb (see arm_pc_is_thumb() below). | |
38 | Unfortunately, something else depends on these (incorrect) macros, so | |
39 | fixing them actually breaks gdb. I didn't have time to investigate. Z.R. | |
40 | */ | |
c906108c SS |
41 | /* Thumb function addresses are odd (bit 0 is set). Here are some |
42 | macros to test, set, or clear bit 0 of addresses. */ | |
43 | #define IS_THUMB_ADDR(addr) ((addr) & 1) | |
44 | #define MAKE_THUMB_ADDR(addr) ((addr) | 1) | |
45 | #define UNMAKE_THUMB_ADDR(addr) ((addr) & ~1) | |
46 | ||
ed9a39eb | 47 | /* Default register names as specified by APCS. */ |
96baa820 | 48 | static char *apcs_register_names[] = |
ed9a39eb JM |
49 | {"a1", "a2", "a3", "a4", /* 0 1 2 3 */ |
50 | "v1", "v2", "v3", "v4", /* 4 5 6 7 */ | |
51 | "v5", "v6", "sl", "fp", /* 8 9 10 11 */ | |
52 | "ip", "sp", "lr", "pc", /* 12 13 14 15 */ | |
53 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
54 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
55 | "fps", "ps"} /* 24 25 */ ; | |
56 | ||
57 | /* Alternate set of registers names used by GCC. */ | |
085dd6e6 | 58 | static char *additional_register_names[] = |
ed9a39eb JM |
59 | {"r0", "r1", "r2", "r3", /* 0 1 2 3 */ |
60 | "r4", "r5", "r6", "r7", /* 4 5 6 7 */ | |
61 | "r8", "r9", "r10", "r11", /* 8 9 10 11 */ | |
62 | "r12", "r13", "r14", "pc", /* 12 13 14 15 */ | |
63 | "f0", "f1", "f2", "f3", /* 16 17 18 19 */ | |
64 | "f4", "f5", "f6", "f7", /* 20 21 22 23 */ | |
65 | "fps", "ps"} /* 24 25 */ ; | |
66 | ||
67 | /* This is the variable that is set with "set disassembly-flavor". | |
68 | By default use the APCS registers names. */ | |
96baa820 | 69 | char **arm_register_names = apcs_register_names; |
ed9a39eb JM |
70 | |
71 | /* Valid register name flavours. */ | |
96baa820 JM |
72 | static char apcs_flavor[] = "apcs"; |
73 | static char r_prefix_flavor[] = "r-prefix"; | |
ed9a39eb JM |
74 | static char *valid_flavors[] = |
75 | { | |
96baa820 JM |
76 | apcs_flavor, |
77 | r_prefix_flavor, | |
78 | NULL | |
79 | }; | |
ed9a39eb JM |
80 | |
81 | /* Disassembly flavor to use. */ | |
96baa820 JM |
82 | static char *disassembly_flavor = apcs_flavor; |
83 | ||
ed9a39eb JM |
84 | /* This is used to keep the bfd arch_info in sync with the disassembly |
85 | flavor. */ | |
86 | static void set_disassembly_flavor_sfunc(char *, int, | |
87 | struct cmd_list_element *); | |
88 | static void set_disassembly_flavor (void); | |
89 | ||
90 | static void convert_from_extended (void *ptr, void *dbl); | |
91 | ||
92 | /* Define other aspects of the stack frame. We keep the offsets of | |
93 | all saved registers, 'cause we need 'em a lot! We also keep the | |
94 | current size of the stack frame, and the offset of the frame | |
95 | pointer from the stack pointer (for frameless functions, and when | |
96 | we're still in the prologue of a function with a frame) */ | |
97 | ||
98 | struct frame_extra_info | |
99 | { | |
100 | struct frame_saved_regs fsr; | |
101 | int framesize; | |
102 | int frameoffset; | |
103 | int framereg; | |
104 | }; | |
105 | ||
106 | /* Will a function return an aggregate type in memory or in a | |
107 | register? Return 0 if an aggregate type can be returned in a | |
108 | register, 1 if it must be returned in memory. */ | |
085dd6e6 | 109 | |
c906108c | 110 | int |
ed9a39eb | 111 | arm_use_struct_convention (int gcc_p, struct type *type) |
c906108c | 112 | { |
ed9a39eb JM |
113 | int nRc; |
114 | register enum type_code code; | |
115 | ||
116 | /* In the ARM ABI, "integer" like aggregate types are returned in | |
117 | registers. For an aggregate type to be integer like, its size | |
118 | must be less than or equal to REGISTER_SIZE and the offset of | |
119 | each addressable subfield must be zero. Note that bit fields are | |
120 | not addressable, and all addressable subfields of unions always | |
121 | start at offset zero. | |
122 | ||
123 | This function is based on the behaviour of GCC 2.95.1. | |
124 | See: gcc/arm.c: arm_return_in_memory() for details. | |
125 | ||
126 | Note: All versions of GCC before GCC 2.95.2 do not set up the | |
127 | parameters correctly for a function returning the following | |
128 | structure: struct { float f;}; This should be returned in memory, | |
129 | not a register. Richard Earnshaw sent me a patch, but I do not | |
130 | know of any way to detect if a function like the above has been | |
131 | compiled with the correct calling convention. */ | |
132 | ||
133 | /* All aggregate types that won't fit in a register must be returned | |
134 | in memory. */ | |
135 | if (TYPE_LENGTH (type) > REGISTER_SIZE) | |
136 | { | |
137 | return 1; | |
138 | } | |
139 | ||
140 | /* The only aggregate types that can be returned in a register are | |
141 | structs and unions. Arrays must be returned in memory. */ | |
142 | code = TYPE_CODE (type); | |
143 | if ((TYPE_CODE_STRUCT != code) && (TYPE_CODE_UNION != code)) | |
144 | { | |
145 | return 1; | |
146 | } | |
147 | ||
148 | /* Assume all other aggregate types can be returned in a register. | |
149 | Run a check for structures, unions and arrays. */ | |
150 | nRc = 0; | |
151 | ||
152 | if ((TYPE_CODE_STRUCT == code) || (TYPE_CODE_UNION == code)) | |
153 | { | |
154 | int i; | |
155 | /* Need to check if this struct/union is "integer" like. For | |
156 | this to be true, its size must be less than or equal to | |
157 | REGISTER_SIZE and the offset of each addressable subfield | |
158 | must be zero. Note that bit fields are not addressable, and | |
159 | unions always start at offset zero. If any of the subfields | |
160 | is a floating point type, the struct/union cannot be an | |
161 | integer type. */ | |
162 | ||
163 | /* For each field in the object, check: | |
164 | 1) Is it FP? --> yes, nRc = 1; | |
165 | 2) Is it addressable (bitpos != 0) and | |
166 | not packed (bitsize == 0)? | |
167 | --> yes, nRc = 1 | |
168 | */ | |
169 | ||
170 | for (i = 0; i < TYPE_NFIELDS (type); i++) | |
171 | { | |
172 | enum type_code field_type_code; | |
173 | field_type_code = TYPE_CODE (TYPE_FIELD_TYPE (type, i)); | |
174 | ||
175 | /* Is it a floating point type field? */ | |
176 | if (field_type_code == TYPE_CODE_FLT) | |
177 | { | |
178 | nRc = 1; | |
179 | break; | |
180 | } | |
181 | ||
182 | /* If bitpos != 0, then we have to care about it. */ | |
183 | if (TYPE_FIELD_BITPOS (type, i) != 0) | |
184 | { | |
185 | /* Bitfields are not addressable. If the field bitsize is | |
186 | zero, then the field is not packed. Hence it cannot be | |
187 | a bitfield or any other packed type. */ | |
188 | if (TYPE_FIELD_BITSIZE (type, i) == 0) | |
189 | { | |
190 | nRc = 1; | |
191 | break; | |
192 | } | |
193 | } | |
194 | } | |
195 | } | |
196 | ||
197 | return nRc; | |
c906108c SS |
198 | } |
199 | ||
200 | int | |
ed9a39eb | 201 | arm_frame_chain_valid (CORE_ADDR chain, struct frame_info *thisframe) |
c906108c | 202 | { |
c906108c SS |
203 | return (chain != 0 && (FRAME_SAVED_PC (thisframe) >= LOWEST_PC)); |
204 | } | |
205 | ||
206 | /* Set to true if the 32-bit mode is in use. */ | |
207 | ||
208 | int arm_apcs_32 = 1; | |
209 | ||
ed9a39eb JM |
210 | /* Flag set by arm_fix_call_dummy that tells whether the target |
211 | function is a Thumb function. This flag is checked by | |
212 | arm_push_arguments. FIXME: Change the PUSH_ARGUMENTS macro (and | |
213 | its use in valops.c) to pass the function address as an additional | |
214 | parameter. */ | |
c906108c SS |
215 | |
216 | static int target_is_thumb; | |
217 | ||
ed9a39eb JM |
218 | /* Flag set by arm_fix_call_dummy that tells whether the calling |
219 | function is a Thumb function. This flag is checked by | |
220 | arm_pc_is_thumb and arm_call_dummy_breakpoint_offset. */ | |
c906108c SS |
221 | |
222 | static int caller_is_thumb; | |
223 | ||
ed9a39eb JM |
224 | /* Determine if the program counter specified in MEMADDR is in a Thumb |
225 | function. */ | |
c906108c SS |
226 | |
227 | int | |
ed9a39eb | 228 | arm_pc_is_thumb (bfd_vma memaddr) |
c906108c | 229 | { |
c5aa993b | 230 | struct minimal_symbol *sym; |
c906108c | 231 | |
ed9a39eb | 232 | /* If bit 0 of the address is set, assume this is a Thumb address. */ |
c906108c SS |
233 | if (IS_THUMB_ADDR (memaddr)) |
234 | return 1; | |
235 | ||
ed9a39eb | 236 | /* Thumb functions have a "special" bit set in minimal symbols. */ |
c906108c SS |
237 | sym = lookup_minimal_symbol_by_pc (memaddr); |
238 | if (sym) | |
239 | { | |
c5aa993b | 240 | return (MSYMBOL_IS_SPECIAL (sym)); |
c906108c SS |
241 | } |
242 | else | |
ed9a39eb JM |
243 | { |
244 | return 0; | |
245 | } | |
c906108c SS |
246 | } |
247 | ||
ed9a39eb JM |
248 | /* Determine if the program counter specified in MEMADDR is in a call |
249 | dummy being called from a Thumb function. */ | |
c906108c SS |
250 | |
251 | int | |
ed9a39eb | 252 | arm_pc_is_thumb_dummy (bfd_vma memaddr) |
c906108c | 253 | { |
c5aa993b | 254 | CORE_ADDR sp = read_sp (); |
c906108c | 255 | |
c5aa993b | 256 | if (PC_IN_CALL_DUMMY (memaddr, sp, sp + 64)) |
c906108c SS |
257 | return caller_is_thumb; |
258 | else | |
259 | return 0; | |
260 | } | |
261 | ||
262 | CORE_ADDR | |
ed9a39eb | 263 | arm_addr_bits_remove (CORE_ADDR val) |
c906108c SS |
264 | { |
265 | if (arm_pc_is_thumb (val)) | |
266 | return (val & (arm_apcs_32 ? 0xfffffffe : 0x03fffffe)); | |
267 | else | |
268 | return (val & (arm_apcs_32 ? 0xfffffffc : 0x03fffffc)); | |
269 | } | |
270 | ||
271 | CORE_ADDR | |
ed9a39eb | 272 | arm_saved_pc_after_call (struct frame_info *frame) |
c906108c SS |
273 | { |
274 | return ADDR_BITS_REMOVE (read_register (LR_REGNUM)); | |
275 | } | |
276 | ||
392a587b | 277 | int |
ed9a39eb | 278 | arm_frameless_function_invocation (struct frame_info *fi) |
392a587b | 279 | { |
392a587b | 280 | CORE_ADDR func_start, after_prologue; |
96baa820 | 281 | int frameless; |
ed9a39eb | 282 | |
392a587b | 283 | func_start = (get_pc_function_start ((fi)->pc) + FUNCTION_START_OFFSET); |
7be570e7 | 284 | after_prologue = SKIP_PROLOGUE (func_start); |
ed9a39eb | 285 | |
96baa820 | 286 | /* There are some frameless functions whose first two instructions |
ed9a39eb JM |
287 | follow the standard APCS form, in which case after_prologue will |
288 | be func_start + 8. */ | |
289 | ||
96baa820 | 290 | frameless = (after_prologue < func_start + 12); |
392a587b JM |
291 | return frameless; |
292 | } | |
293 | ||
c906108c | 294 | /* A typical Thumb prologue looks like this: |
c5aa993b JM |
295 | push {r7, lr} |
296 | add sp, sp, #-28 | |
297 | add r7, sp, #12 | |
c906108c | 298 | Sometimes the latter instruction may be replaced by: |
c5aa993b | 299 | mov r7, sp |
ed9a39eb | 300 | */ |
c906108c SS |
301 | |
302 | static CORE_ADDR | |
ed9a39eb | 303 | thumb_skip_prologue (CORE_ADDR pc) |
c906108c SS |
304 | { |
305 | CORE_ADDR current_pc; | |
306 | ||
307 | for (current_pc = pc; current_pc < pc + 20; current_pc += 2) | |
308 | { | |
309 | unsigned short insn = read_memory_unsigned_integer (current_pc, 2); | |
310 | ||
ed9a39eb JM |
311 | if ((insn & 0xfe00) != 0xb400 /* push {..., r7, lr} */ |
312 | && (insn & 0xff00) != 0xb000 /* add sp, #simm */ | |
313 | && (insn & 0xff00) != 0xaf00 /* add r7, sp, #imm */ | |
314 | && insn != 0x466f /* mov r7, sp */ | |
315 | && (insn & 0xffc0) != 0x4640) /* mov r0-r7, r8-r15 */ | |
c906108c SS |
316 | break; |
317 | } | |
318 | ||
319 | return current_pc; | |
320 | } | |
321 | ||
ed9a39eb JM |
322 | /* The APCS (ARM Procedure Call Standard) defines the following |
323 | prologue: | |
c906108c | 324 | |
c5aa993b JM |
325 | mov ip, sp |
326 | [stmfd sp!, {a1,a2,a3,a4}] | |
327 | stmfd sp!, {...,fp,ip,lr,pc} | |
ed9a39eb JM |
328 | [stfe f7, [sp, #-12]!] |
329 | [stfe f6, [sp, #-12]!] | |
330 | [stfe f5, [sp, #-12]!] | |
331 | [stfe f4, [sp, #-12]!] | |
332 | sub fp, ip, #nn @@ nn == 20 or 4 depending on second insn */ | |
c906108c SS |
333 | |
334 | CORE_ADDR | |
ed9a39eb | 335 | arm_skip_prologue (CORE_ADDR pc) |
c906108c SS |
336 | { |
337 | unsigned long inst; | |
338 | CORE_ADDR skip_pc; | |
339 | CORE_ADDR func_addr, func_end; | |
340 | struct symtab_and_line sal; | |
341 | ||
96baa820 | 342 | /* See what the symbol table says. */ |
ed9a39eb | 343 | |
c5aa993b | 344 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) |
c906108c SS |
345 | { |
346 | sal = find_pc_line (func_addr, 0); | |
96baa820 | 347 | if ((sal.line != 0) && (sal.end < func_end)) |
c906108c SS |
348 | return sal.end; |
349 | } | |
350 | ||
351 | /* Check if this is Thumb code. */ | |
352 | if (arm_pc_is_thumb (pc)) | |
353 | return thumb_skip_prologue (pc); | |
354 | ||
355 | /* Can't find the prologue end in the symbol table, try it the hard way | |
356 | by disassembling the instructions. */ | |
357 | skip_pc = pc; | |
358 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 359 | if (inst != 0xe1a0c00d) /* mov ip, sp */ |
c906108c SS |
360 | return pc; |
361 | ||
362 | skip_pc += 4; | |
363 | inst = read_memory_integer (skip_pc, 4); | |
c5aa993b | 364 | if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ |
c906108c SS |
365 | { |
366 | skip_pc += 4; | |
367 | inst = read_memory_integer (skip_pc, 4); | |
368 | } | |
369 | ||
c5aa993b | 370 | if ((inst & 0xfffff800) != 0xe92dd800) /* stmfd sp!,{...,fp,ip,lr,pc} */ |
c906108c SS |
371 | return pc; |
372 | ||
373 | skip_pc += 4; | |
374 | inst = read_memory_integer (skip_pc, 4); | |
375 | ||
376 | /* Any insns after this point may float into the code, if it makes | |
ed9a39eb JM |
377 | for better instruction scheduling, so we skip them only if we |
378 | find them, but still consdier the function to be frame-ful. */ | |
c906108c | 379 | |
ed9a39eb JM |
380 | /* We may have either one sfmfd instruction here, or several stfe |
381 | insns, depending on the version of floating point code we | |
382 | support. */ | |
c5aa993b | 383 | if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, <cnt>, [sp]! */ |
c906108c SS |
384 | { |
385 | skip_pc += 4; | |
386 | inst = read_memory_integer (skip_pc, 4); | |
387 | } | |
388 | else | |
389 | { | |
c5aa993b JM |
390 | while ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ |
391 | { | |
392 | skip_pc += 4; | |
393 | inst = read_memory_integer (skip_pc, 4); | |
394 | } | |
c906108c SS |
395 | } |
396 | ||
c5aa993b | 397 | if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ |
c906108c SS |
398 | skip_pc += 4; |
399 | ||
400 | return skip_pc; | |
401 | } | |
c5aa993b | 402 | /* *INDENT-OFF* */ |
c906108c SS |
403 | /* Function: thumb_scan_prologue (helper function for arm_scan_prologue) |
404 | This function decodes a Thumb function prologue to determine: | |
405 | 1) the size of the stack frame | |
406 | 2) which registers are saved on it | |
407 | 3) the offsets of saved regs | |
408 | 4) the offset from the stack pointer to the frame pointer | |
409 | This information is stored in the "extra" fields of the frame_info. | |
410 | ||
411 | A typical Thumb function prologue might look like this: | |
412 | push {r7, lr} | |
413 | sub sp, #28, | |
414 | add r7, sp, #12 | |
415 | Which would create this stack frame (offsets relative to FP) | |
416 | old SP -> 24 stack parameters | |
417 | 20 LR | |
418 | 16 R7 | |
419 | R7 -> 0 local variables (16 bytes) | |
420 | SP -> -12 additional stack space (12 bytes) | |
421 | The frame size would thus be 36 bytes, and the frame offset would be | |
422 | 12 bytes. The frame register is R7. */ | |
c5aa993b JM |
423 | /* *INDENT-ON* */ |
424 | ||
c906108c | 425 | static void |
ed9a39eb | 426 | thumb_scan_prologue (struct frame_info *fi) |
c906108c SS |
427 | { |
428 | CORE_ADDR prologue_start; | |
429 | CORE_ADDR prologue_end; | |
430 | CORE_ADDR current_pc; | |
c5aa993b JM |
431 | int saved_reg[16]; /* which register has been copied to register n? */ |
432 | int i; | |
c906108c | 433 | |
c5aa993b | 434 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) |
c906108c SS |
435 | { |
436 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
437 | ||
c5aa993b | 438 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
439 | prologue_end = fi->pc; |
440 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 441 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
442 | } |
443 | else | |
c5aa993b JM |
444 | prologue_end = prologue_start + 40; /* We're in the boondocks: allow for */ |
445 | /* 16 pushes, an add, and "mv fp,sp" */ | |
c906108c SS |
446 | |
447 | prologue_end = min (prologue_end, fi->pc); | |
448 | ||
449 | /* Initialize the saved register map. When register H is copied to | |
450 | register L, we will put H in saved_reg[L]. */ | |
451 | for (i = 0; i < 16; i++) | |
452 | saved_reg[i] = i; | |
453 | ||
454 | /* Search the prologue looking for instructions that set up the | |
455 | frame pointer, adjust the stack pointer, and save registers. */ | |
456 | ||
457 | fi->framesize = 0; | |
458 | for (current_pc = prologue_start; current_pc < prologue_end; current_pc += 2) | |
459 | { | |
460 | unsigned short insn; | |
461 | int regno; | |
462 | int offset; | |
463 | ||
464 | insn = read_memory_unsigned_integer (current_pc, 2); | |
465 | ||
c5aa993b | 466 | if ((insn & 0xfe00) == 0xb400) /* push { rlist } */ |
c906108c SS |
467 | { |
468 | /* Bits 0-7 contain a mask for registers R0-R7. Bit 8 says | |
469 | whether to save LR (R14). */ | |
470 | int mask = (insn & 0xff) | ((insn & 0x100) << 6); | |
471 | ||
472 | /* Calculate offsets of saved R0-R7 and LR. */ | |
473 | for (regno = LR_REGNUM; regno >= 0; regno--) | |
474 | if (mask & (1 << regno)) | |
c5aa993b | 475 | { |
c906108c SS |
476 | fi->framesize += 4; |
477 | fi->fsr.regs[saved_reg[regno]] = -(fi->framesize); | |
478 | saved_reg[regno] = regno; /* reset saved register map */ | |
479 | } | |
480 | } | |
481 | else if ((insn & 0xff00) == 0xb000) /* add sp, #simm */ | |
482 | { | |
c5aa993b JM |
483 | offset = (insn & 0x7f) << 2; /* get scaled offset */ |
484 | if (insn & 0x80) /* is it signed? */ | |
485 | offset = -offset; | |
c906108c SS |
486 | fi->framesize -= offset; |
487 | } | |
488 | else if ((insn & 0xff00) == 0xaf00) /* add r7, sp, #imm */ | |
489 | { | |
490 | fi->framereg = THUMB_FP_REGNUM; | |
c5aa993b | 491 | fi->frameoffset = (insn & 0xff) << 2; /* get scaled offset */ |
c906108c | 492 | } |
c5aa993b | 493 | else if (insn == 0x466f) /* mov r7, sp */ |
c906108c SS |
494 | { |
495 | fi->framereg = THUMB_FP_REGNUM; | |
496 | fi->frameoffset = 0; | |
497 | saved_reg[THUMB_FP_REGNUM] = SP_REGNUM; | |
498 | } | |
499 | else if ((insn & 0xffc0) == 0x4640) /* mov r0-r7, r8-r15 */ | |
500 | { | |
c5aa993b | 501 | int lo_reg = insn & 7; /* dest. register (r0-r7) */ |
c906108c | 502 | int hi_reg = ((insn >> 3) & 7) + 8; /* source register (r8-15) */ |
c5aa993b | 503 | saved_reg[lo_reg] = hi_reg; /* remember hi reg was saved */ |
c906108c SS |
504 | } |
505 | else | |
c5aa993b | 506 | break; /* anything else isn't prologue */ |
c906108c SS |
507 | } |
508 | } | |
509 | ||
ed9a39eb JM |
510 | /* Check if prologue for this frame's PC has already been scanned. If |
511 | it has, copy the relevant information about that prologue and | |
c906108c SS |
512 | return non-zero. Otherwise do not copy anything and return zero. |
513 | ||
514 | The information saved in the cache includes: | |
c5aa993b JM |
515 | * the frame register number; |
516 | * the size of the stack frame; | |
517 | * the offsets of saved regs (relative to the old SP); and | |
518 | * the offset from the stack pointer to the frame pointer | |
c906108c | 519 | |
ed9a39eb JM |
520 | The cache contains only one entry, since this is adequate for the |
521 | typical sequence of prologue scan requests we get. When performing | |
522 | a backtrace, GDB will usually ask to scan the same function twice | |
523 | in a row (once to get the frame chain, and once to fill in the | |
524 | extra frame information). */ | |
c906108c SS |
525 | |
526 | static struct frame_info prologue_cache; | |
527 | ||
528 | static int | |
ed9a39eb | 529 | check_prologue_cache (struct frame_info *fi) |
c906108c SS |
530 | { |
531 | int i; | |
532 | ||
533 | if (fi->pc == prologue_cache.pc) | |
534 | { | |
535 | fi->framereg = prologue_cache.framereg; | |
536 | fi->framesize = prologue_cache.framesize; | |
537 | fi->frameoffset = prologue_cache.frameoffset; | |
538 | for (i = 0; i <= NUM_REGS; i++) | |
539 | fi->fsr.regs[i] = prologue_cache.fsr.regs[i]; | |
540 | return 1; | |
541 | } | |
542 | else | |
543 | return 0; | |
544 | } | |
545 | ||
546 | ||
ed9a39eb | 547 | /* Copy the prologue information from fi to the prologue cache. */ |
c906108c SS |
548 | |
549 | static void | |
ed9a39eb | 550 | save_prologue_cache (struct frame_info *fi) |
c906108c SS |
551 | { |
552 | int i; | |
553 | ||
c5aa993b JM |
554 | prologue_cache.pc = fi->pc; |
555 | prologue_cache.framereg = fi->framereg; | |
556 | prologue_cache.framesize = fi->framesize; | |
c906108c | 557 | prologue_cache.frameoffset = fi->frameoffset; |
c5aa993b | 558 | |
c906108c SS |
559 | for (i = 0; i <= NUM_REGS; i++) |
560 | prologue_cache.fsr.regs[i] = fi->fsr.regs[i]; | |
561 | } | |
562 | ||
563 | ||
ed9a39eb | 564 | /* This function decodes an ARM function prologue to determine: |
c5aa993b JM |
565 | 1) the size of the stack frame |
566 | 2) which registers are saved on it | |
567 | 3) the offsets of saved regs | |
568 | 4) the offset from the stack pointer to the frame pointer | |
c906108c SS |
569 | This information is stored in the "extra" fields of the frame_info. |
570 | ||
96baa820 JM |
571 | There are two basic forms for the ARM prologue. The fixed argument |
572 | function call will look like: | |
ed9a39eb JM |
573 | |
574 | mov ip, sp | |
575 | stmfd sp!, {fp, ip, lr, pc} | |
576 | sub fp, ip, #4 | |
577 | [sub sp, sp, #4] | |
96baa820 | 578 | |
c906108c | 579 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
580 | IP -> 4 (caller's stack) |
581 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
582 | -4 LR (return address in caller) | |
583 | -8 IP (copy of caller's SP) | |
584 | -12 FP (caller's FP) | |
585 | SP -> -28 Local variables | |
586 | ||
c906108c | 587 | The frame size would thus be 32 bytes, and the frame offset would be |
96baa820 JM |
588 | 28 bytes. The stmfd call can also save any of the vN registers it |
589 | plans to use, which increases the frame size accordingly. | |
590 | ||
591 | Note: The stored PC is 8 off of the STMFD instruction that stored it | |
592 | because the ARM Store instructions always store PC + 8 when you read | |
593 | the PC register. | |
ed9a39eb | 594 | |
96baa820 JM |
595 | A variable argument function call will look like: |
596 | ||
ed9a39eb JM |
597 | mov ip, sp |
598 | stmfd sp!, {a1, a2, a3, a4} | |
599 | stmfd sp!, {fp, ip, lr, pc} | |
600 | sub fp, ip, #20 | |
601 | ||
96baa820 | 602 | Which would create this stack frame (offsets relative to FP): |
ed9a39eb JM |
603 | IP -> 20 (caller's stack) |
604 | 16 A4 | |
605 | 12 A3 | |
606 | 8 A2 | |
607 | 4 A1 | |
608 | FP -> 0 PC (points to address of stmfd instruction + 8 in callee) | |
609 | -4 LR (return address in caller) | |
610 | -8 IP (copy of caller's SP) | |
611 | -12 FP (caller's FP) | |
612 | SP -> -28 Local variables | |
96baa820 JM |
613 | |
614 | The frame size would thus be 48 bytes, and the frame offset would be | |
615 | 28 bytes. | |
616 | ||
617 | There is another potential complication, which is that the optimizer | |
618 | will try to separate the store of fp in the "stmfd" instruction from | |
619 | the "sub fp, ip, #NN" instruction. Almost anything can be there, so | |
620 | we just key on the stmfd, and then scan for the "sub fp, ip, #NN"... | |
621 | ||
622 | Also, note, the original version of the ARM toolchain claimed that there | |
623 | should be an | |
624 | ||
625 | instruction at the end of the prologue. I have never seen GCC produce | |
626 | this, and the ARM docs don't mention it. We still test for it below in | |
627 | case it happens... | |
ed9a39eb JM |
628 | |
629 | */ | |
c906108c SS |
630 | |
631 | static void | |
ed9a39eb | 632 | arm_scan_prologue (struct frame_info *fi) |
c906108c SS |
633 | { |
634 | int regno, sp_offset, fp_offset; | |
635 | CORE_ADDR prologue_start, prologue_end, current_pc; | |
636 | ||
637 | /* Check if this function is already in the cache of frame information. */ | |
638 | if (check_prologue_cache (fi)) | |
639 | return; | |
640 | ||
641 | /* Assume there is no frame until proven otherwise. */ | |
c5aa993b JM |
642 | fi->framereg = SP_REGNUM; |
643 | fi->framesize = 0; | |
c906108c SS |
644 | fi->frameoffset = 0; |
645 | ||
646 | /* Check for Thumb prologue. */ | |
647 | if (arm_pc_is_thumb (fi->pc)) | |
648 | { | |
649 | thumb_scan_prologue (fi); | |
650 | save_prologue_cache (fi); | |
651 | return; | |
652 | } | |
653 | ||
654 | /* Find the function prologue. If we can't find the function in | |
655 | the symbol table, peek in the stack frame to find the PC. */ | |
656 | if (find_pc_partial_function (fi->pc, NULL, &prologue_start, &prologue_end)) | |
657 | { | |
658 | /* Assume the prologue is everything between the first instruction | |
659 | in the function and the first source line. */ | |
660 | struct symtab_and_line sal = find_pc_line (prologue_start, 0); | |
661 | ||
c5aa993b | 662 | if (sal.line == 0) /* no line info, use current PC */ |
c906108c SS |
663 | prologue_end = fi->pc; |
664 | else if (sal.end < prologue_end) /* next line begins after fn end */ | |
c5aa993b | 665 | prologue_end = sal.end; /* (probably means no prologue) */ |
c906108c SS |
666 | } |
667 | else | |
668 | { | |
669 | /* Get address of the stmfd in the prologue of the callee; the saved | |
96baa820 | 670 | PC is the address of the stmfd + 8. */ |
ed9a39eb | 671 | prologue_start = ADDR_BITS_REMOVE (read_memory_integer (fi->frame, 4)) |
96baa820 | 672 | - 8; |
ed9a39eb JM |
673 | prologue_end = prologue_start + 64; /* This is all the insn's |
674 | that could be in the prologue, | |
675 | plus room for 5 insn's inserted | |
676 | by the scheduler. */ | |
c906108c SS |
677 | } |
678 | ||
679 | /* Now search the prologue looking for instructions that set up the | |
96baa820 | 680 | frame pointer, adjust the stack pointer, and save registers. |
ed9a39eb | 681 | |
96baa820 JM |
682 | Be careful, however, and if it doesn't look like a prologue, |
683 | don't try to scan it. If, for instance, a frameless function | |
684 | begins with stmfd sp!, then we will tell ourselves there is | |
685 | a frame, which will confuse stack traceback, as well ad"finish" | |
686 | and other operations that rely on a knowledge of the stack | |
687 | traceback. | |
688 | ||
689 | In the APCS, the prologue should start with "mov ip, sp" so | |
690 | if we don't see this as the first insn, we will stop. */ | |
c906108c SS |
691 | |
692 | sp_offset = fp_offset = 0; | |
c906108c | 693 | |
ed9a39eb JM |
694 | if (read_memory_unsigned_integer (prologue_start, 4) |
695 | == 0xe1a0c00d) /* mov ip, sp */ | |
96baa820 | 696 | { |
ed9a39eb | 697 | for (current_pc = prologue_start + 4; current_pc < prologue_end; |
96baa820 | 698 | current_pc += 4) |
c906108c | 699 | { |
96baa820 | 700 | unsigned int insn = read_memory_unsigned_integer (current_pc, 4); |
ed9a39eb | 701 | |
96baa820 JM |
702 | if ((insn & 0xffff0000) == 0xe92d0000) |
703 | /* stmfd sp!, {..., fp, ip, lr, pc} | |
704 | or | |
705 | stmfd sp!, {a1, a2, a3, a4} */ | |
706 | { | |
707 | int mask = insn & 0xffff; | |
ed9a39eb | 708 | |
96baa820 JM |
709 | /* Calculate offsets of saved registers. */ |
710 | for (regno = PC_REGNUM; regno >= 0; regno--) | |
711 | if (mask & (1 << regno)) | |
712 | { | |
713 | sp_offset -= 4; | |
714 | fi->fsr.regs[regno] = sp_offset; | |
715 | } | |
716 | } | |
ed9a39eb | 717 | else if ((insn & 0xfffff000) == 0xe24cb000) /* sub fp, ip #n */ |
96baa820 | 718 | { |
ed9a39eb JM |
719 | unsigned imm = insn & 0xff; /* immediate value */ |
720 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
721 | imm = (imm >> rot) | (imm << (32 - rot)); | |
96baa820 JM |
722 | fp_offset = -imm; |
723 | fi->framereg = FP_REGNUM; | |
724 | } | |
ed9a39eb | 725 | else if ((insn & 0xfffff000) == 0xe24dd000) /* sub sp, sp #n */ |
96baa820 | 726 | { |
ed9a39eb JM |
727 | unsigned imm = insn & 0xff; /* immediate value */ |
728 | unsigned rot = (insn & 0xf00) >> 7; /* rotate amount */ | |
729 | imm = (imm >> rot) | (imm << (32 - rot)); | |
96baa820 JM |
730 | sp_offset -= imm; |
731 | } | |
ed9a39eb | 732 | else if ((insn & 0xffff7fff) == 0xed6d0103) /* stfe f?, [sp, -#c]! */ |
96baa820 JM |
733 | { |
734 | sp_offset -= 12; | |
735 | regno = F0_REGNUM + ((insn >> 12) & 0x07); | |
736 | fi->fsr.regs[regno] = sp_offset; | |
737 | } | |
ed9a39eb | 738 | else if ((insn & 0xffbf0fff) == 0xec2d0200) /* sfmfd f0, 4, [sp!] */ |
96baa820 | 739 | { |
ed9a39eb | 740 | int n_saved_fp_regs; |
96baa820 | 741 | unsigned int fp_start_reg, fp_bound_reg; |
ed9a39eb JM |
742 | |
743 | if ((insn & 0x800) == 0x800) /* N0 is set */ | |
744 | { | |
745 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ | |
96baa820 JM |
746 | n_saved_fp_regs = 3; |
747 | else | |
748 | n_saved_fp_regs = 1; | |
749 | } | |
750 | else | |
ed9a39eb JM |
751 | { |
752 | if ((insn & 0x40000) == 0x40000) /* N1 is set */ | |
96baa820 JM |
753 | n_saved_fp_regs = 2; |
754 | else | |
755 | n_saved_fp_regs = 4; | |
756 | } | |
ed9a39eb | 757 | |
96baa820 JM |
758 | fp_start_reg = F0_REGNUM + ((insn >> 12) & 0x7); |
759 | fp_bound_reg = fp_start_reg + n_saved_fp_regs; | |
760 | for (; fp_start_reg < fp_bound_reg; fp_start_reg++) | |
761 | { | |
762 | sp_offset -= 12; | |
763 | fi->fsr.regs[fp_start_reg++] = sp_offset; | |
764 | } | |
765 | } | |
766 | else | |
ed9a39eb JM |
767 | /* The optimizer might shove anything into the prologue, |
768 | so we just skip what we don't recognize. */ | |
769 | continue; | |
c906108c | 770 | } |
c906108c SS |
771 | } |
772 | ||
773 | /* The frame size is just the negative of the offset (from the original SP) | |
774 | of the last thing thing we pushed on the stack. The frame offset is | |
775 | [new FP] - [new SP]. */ | |
776 | fi->framesize = -sp_offset; | |
777 | fi->frameoffset = fp_offset - sp_offset; | |
ed9a39eb | 778 | |
c906108c SS |
779 | save_prologue_cache (fi); |
780 | } | |
781 | ||
ed9a39eb JM |
782 | /* Find REGNUM on the stack. Otherwise, it's in an active register. |
783 | One thing we might want to do here is to check REGNUM against the | |
784 | clobber mask, and somehow flag it as invalid if it isn't saved on | |
785 | the stack somewhere. This would provide a graceful failure mode | |
786 | when trying to get the value of caller-saves registers for an inner | |
787 | frame. */ | |
c906108c SS |
788 | |
789 | static CORE_ADDR | |
ed9a39eb | 790 | arm_find_callers_reg (struct frame_info *fi, int regnum) |
c906108c SS |
791 | { |
792 | for (; fi; fi = fi->next) | |
c5aa993b JM |
793 | |
794 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ | |
c906108c SS |
795 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
796 | return generic_read_register_dummy (fi->pc, fi->frame, regnum); | |
797 | else | |
798 | #endif | |
c5aa993b JM |
799 | if (fi->fsr.regs[regnum] != 0) |
800 | return read_memory_integer (fi->fsr.regs[regnum], | |
801 | REGISTER_RAW_SIZE (regnum)); | |
c906108c SS |
802 | return read_register (regnum); |
803 | } | |
c5aa993b | 804 | /* *INDENT-OFF* */ |
c906108c SS |
805 | /* Function: frame_chain |
806 | Given a GDB frame, determine the address of the calling function's frame. | |
807 | This will be used to create a new GDB frame struct, and then | |
808 | INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. | |
809 | For ARM, we save the frame size when we initialize the frame_info. | |
810 | ||
811 | The original definition of this function was a macro in tm-arm.h: | |
812 | { In the case of the ARM, the frame's nominal address is the FP value, | |
813 | and 12 bytes before comes the saved previous FP value as a 4-byte word. } | |
814 | ||
815 | #define FRAME_CHAIN(thisframe) \ | |
816 | ((thisframe)->pc >= LOWEST_PC ? \ | |
817 | read_memory_integer ((thisframe)->frame - 12, 4) :\ | |
818 | 0) | |
819 | */ | |
c5aa993b JM |
820 | /* *INDENT-ON* */ |
821 | ||
c906108c | 822 | CORE_ADDR |
ed9a39eb | 823 | arm_frame_chain (struct frame_info *fi) |
c906108c | 824 | { |
c5aa993b | 825 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
826 | CORE_ADDR fn_start, callers_pc, fp; |
827 | ||
828 | /* is this a dummy frame? */ | |
829 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) | |
c5aa993b | 830 | return fi->frame; /* dummy frame same as caller's frame */ |
c906108c SS |
831 | |
832 | /* is caller-of-this a dummy frame? */ | |
c5aa993b | 833 | callers_pc = FRAME_SAVED_PC (fi); /* find out who called us: */ |
c906108c | 834 | fp = arm_find_callers_reg (fi, FP_REGNUM); |
c5aa993b JM |
835 | if (PC_IN_CALL_DUMMY (callers_pc, fp, fp)) |
836 | return fp; /* dummy frame's frame may bear no relation to ours */ | |
c906108c SS |
837 | |
838 | if (find_pc_partial_function (fi->pc, 0, &fn_start, 0)) | |
839 | if (fn_start == entry_point_address ()) | |
c5aa993b | 840 | return 0; /* in _start fn, don't chain further */ |
c906108c SS |
841 | #endif |
842 | CORE_ADDR caller_pc, fn_start; | |
843 | struct frame_info caller_fi; | |
844 | int framereg = fi->framereg; | |
845 | ||
846 | if (fi->pc < LOWEST_PC) | |
847 | return 0; | |
848 | ||
849 | /* If the caller is the startup code, we're at the end of the chain. */ | |
850 | caller_pc = FRAME_SAVED_PC (fi); | |
851 | if (find_pc_partial_function (caller_pc, 0, &fn_start, 0)) | |
852 | if (fn_start == entry_point_address ()) | |
853 | return 0; | |
854 | ||
855 | /* If the caller is Thumb and the caller is ARM, or vice versa, | |
856 | the frame register of the caller is different from ours. | |
857 | So we must scan the prologue of the caller to determine its | |
858 | frame register number. */ | |
859 | if (arm_pc_is_thumb (caller_pc) != arm_pc_is_thumb (fi->pc)) | |
860 | { | |
c5aa993b | 861 | memset (&caller_fi, 0, sizeof (caller_fi)); |
c906108c | 862 | caller_fi.pc = caller_pc; |
c5aa993b | 863 | arm_scan_prologue (&caller_fi); |
c906108c SS |
864 | framereg = caller_fi.framereg; |
865 | } | |
866 | ||
867 | /* If the caller used a frame register, return its value. | |
868 | Otherwise, return the caller's stack pointer. */ | |
869 | if (framereg == FP_REGNUM || framereg == THUMB_FP_REGNUM) | |
870 | return arm_find_callers_reg (fi, framereg); | |
871 | else | |
872 | return fi->frame + fi->framesize; | |
873 | } | |
874 | ||
ed9a39eb JM |
875 | /* This function actually figures out the frame address for a given pc |
876 | and sp. This is tricky because we sometimes don't use an explicit | |
877 | frame pointer, and the previous stack pointer isn't necessarily | |
878 | recorded on the stack. The only reliable way to get this info is | |
879 | to examine the prologue. FROMLEAF is a little confusing, it means | |
880 | this is the next frame up the chain AFTER a frameless function. If | |
881 | this is true, then the frame value for this frame is still in the | |
882 | fp register. */ | |
c906108c SS |
883 | |
884 | void | |
ed9a39eb | 885 | arm_init_extra_frame_info (int fromleaf, struct frame_info *fi) |
c906108c SS |
886 | { |
887 | int reg; | |
888 | ||
889 | if (fi->next) | |
890 | fi->pc = FRAME_SAVED_PC (fi->next); | |
891 | ||
892 | memset (fi->fsr.regs, '\000', sizeof fi->fsr.regs); | |
893 | ||
c5aa993b | 894 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
895 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
896 | { | |
897 | /* We need to setup fi->frame here because run_stack_dummy gets it wrong | |
c5aa993b JM |
898 | by assuming it's always FP. */ |
899 | fi->frame = generic_read_register_dummy (fi->pc, fi->frame, SP_REGNUM); | |
900 | fi->framesize = 0; | |
c906108c SS |
901 | fi->frameoffset = 0; |
902 | return; | |
903 | } | |
c5aa993b | 904 | else |
c906108c SS |
905 | #endif |
906 | { | |
907 | arm_scan_prologue (fi); | |
908 | ||
104c1213 JM |
909 | if (!fi->next) |
910 | /* this is the innermost frame? */ | |
c906108c | 911 | fi->frame = read_register (fi->framereg); |
ed9a39eb JM |
912 | else if (fi->framereg == FP_REGNUM || fi->framereg == THUMB_FP_REGNUM) |
913 | { | |
914 | /* not the innermost frame */ | |
915 | /* If we have an FP, the callee saved it. */ | |
916 | if (fi->next->fsr.regs[fi->framereg] != 0) | |
917 | fi->frame = | |
918 | read_memory_integer (fi->next->fsr.regs[fi->framereg], 4); | |
919 | else if (fromleaf) | |
920 | /* If we were called by a frameless fn. then our frame is | |
921 | still in the frame pointer register on the board... */ | |
922 | fi->frame = read_fp (); | |
923 | } | |
c906108c | 924 | |
ed9a39eb JM |
925 | /* Calculate actual addresses of saved registers using offsets |
926 | determined by arm_scan_prologue. */ | |
c906108c SS |
927 | for (reg = 0; reg < NUM_REGS; reg++) |
928 | if (fi->fsr.regs[reg] != 0) | |
929 | fi->fsr.regs[reg] += fi->frame + fi->framesize - fi->frameoffset; | |
930 | } | |
931 | } | |
932 | ||
933 | ||
ed9a39eb JM |
934 | /* Find the caller of this frame. We do this by seeing if LR_REGNUM |
935 | is saved in the stack anywhere, otherwise we get it from the | |
936 | registers. | |
c906108c SS |
937 | |
938 | The old definition of this function was a macro: | |
c5aa993b | 939 | #define FRAME_SAVED_PC(FRAME) \ |
ed9a39eb | 940 | ADDR_BITS_REMOVE (read_memory_integer ((FRAME)->frame - 4, 4)) */ |
c906108c SS |
941 | |
942 | CORE_ADDR | |
ed9a39eb | 943 | arm_frame_saved_pc (struct frame_info *fi) |
c906108c | 944 | { |
c5aa993b | 945 | #if 0 /* FIXME: enable this code if we convert to new call dummy scheme. */ |
c906108c SS |
946 | if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) |
947 | return generic_read_register_dummy (fi->pc, fi->frame, PC_REGNUM); | |
948 | else | |
949 | #endif | |
950 | { | |
951 | CORE_ADDR pc = arm_find_callers_reg (fi, LR_REGNUM); | |
952 | return IS_THUMB_ADDR (pc) ? UNMAKE_THUMB_ADDR (pc) : pc; | |
953 | } | |
954 | } | |
955 | ||
c906108c SS |
956 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. |
957 | Examine the Program Status Register to decide which state we're in. */ | |
958 | ||
959 | CORE_ADDR | |
ed9a39eb | 960 | arm_target_read_fp (void) |
c906108c SS |
961 | { |
962 | if (read_register (PS_REGNUM) & 0x20) /* Bit 5 is Thumb state bit */ | |
963 | return read_register (THUMB_FP_REGNUM); /* R7 if Thumb */ | |
964 | else | |
c5aa993b | 965 | return read_register (FP_REGNUM); /* R11 if ARM */ |
c906108c SS |
966 | } |
967 | ||
ed9a39eb | 968 | /* Calculate the frame offsets of the saved registers (ARM version). */ |
c906108c | 969 | |
c906108c | 970 | void |
ed9a39eb JM |
971 | arm_frame_find_saved_regs (struct frame_info *fi, |
972 | struct frame_saved_regs *regaddr) | |
c906108c SS |
973 | { |
974 | memcpy (regaddr, &fi->fsr, sizeof (struct frame_saved_regs)); | |
975 | } | |
976 | ||
c906108c | 977 | void |
ed9a39eb | 978 | arm_push_dummy_frame (void) |
c906108c SS |
979 | { |
980 | CORE_ADDR old_sp = read_register (SP_REGNUM); | |
981 | CORE_ADDR sp = old_sp; | |
982 | CORE_ADDR fp, prologue_start; | |
983 | int regnum; | |
984 | ||
985 | /* Push the two dummy prologue instructions in reverse order, | |
986 | so that they'll be in the correct low-to-high order in memory. */ | |
987 | /* sub fp, ip, #4 */ | |
988 | sp = push_word (sp, 0xe24cb004); | |
989 | /* stmdb sp!, {r0-r10, fp, ip, lr, pc} */ | |
990 | prologue_start = sp = push_word (sp, 0xe92ddfff); | |
991 | ||
ed9a39eb JM |
992 | /* Push a pointer to the dummy prologue + 12, because when stm |
993 | instruction stores the PC, it stores the address of the stm | |
c906108c SS |
994 | instruction itself plus 12. */ |
995 | fp = sp = push_word (sp, prologue_start + 12); | |
c5aa993b | 996 | sp = push_word (sp, read_register (PC_REGNUM)); /* FIXME: was PS_REGNUM */ |
c906108c SS |
997 | sp = push_word (sp, old_sp); |
998 | sp = push_word (sp, read_register (FP_REGNUM)); | |
c5aa993b JM |
999 | |
1000 | for (regnum = 10; regnum >= 0; regnum--) | |
c906108c | 1001 | sp = push_word (sp, read_register (regnum)); |
c5aa993b | 1002 | |
c906108c SS |
1003 | write_register (FP_REGNUM, fp); |
1004 | write_register (THUMB_FP_REGNUM, fp); | |
1005 | write_register (SP_REGNUM, sp); | |
1006 | } | |
1007 | ||
1008 | /* Fix up the call dummy, based on whether the processor is currently | |
ed9a39eb JM |
1009 | in Thumb or ARM mode, and whether the target function is Thumb or |
1010 | ARM. There are three different situations requiring three | |
c906108c SS |
1011 | different dummies: |
1012 | ||
1013 | * ARM calling ARM: uses the call dummy in tm-arm.h, which has already | |
c5aa993b | 1014 | been copied into the dummy parameter to this function. |
c906108c | 1015 | * ARM calling Thumb: uses the call dummy in tm-arm.h, but with the |
c5aa993b | 1016 | "mov pc,r4" instruction patched to be a "bx r4" instead. |
c906108c | 1017 | * Thumb calling anything: uses the Thumb dummy defined below, which |
c5aa993b | 1018 | works for calling both ARM and Thumb functions. |
c906108c | 1019 | |
ed9a39eb JM |
1020 | All three call dummies expect to receive the target function |
1021 | address in R4, with the low bit set if it's a Thumb function. */ | |
c906108c SS |
1022 | |
1023 | void | |
ed9a39eb JM |
1024 | arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs, |
1025 | value_ptr *args, struct type *type, int gcc_p) | |
c906108c SS |
1026 | { |
1027 | static short thumb_dummy[4] = | |
1028 | { | |
c5aa993b JM |
1029 | 0xf000, 0xf801, /* bl label */ |
1030 | 0xdf18, /* swi 24 */ | |
1031 | 0x4720, /* label: bx r4 */ | |
c906108c SS |
1032 | }; |
1033 | static unsigned long arm_bx_r4 = 0xe12fff14; /* bx r4 instruction */ | |
1034 | ||
1035 | /* Set flag indicating whether the current PC is in a Thumb function. */ | |
c5aa993b | 1036 | caller_is_thumb = arm_pc_is_thumb (read_pc ()); |
c906108c | 1037 | |
ed9a39eb JM |
1038 | /* If the target function is Thumb, set the low bit of the function |
1039 | address. And if the CPU is currently in ARM mode, patch the | |
1040 | second instruction of call dummy to use a BX instruction to | |
1041 | switch to Thumb mode. */ | |
c906108c SS |
1042 | target_is_thumb = arm_pc_is_thumb (fun); |
1043 | if (target_is_thumb) | |
1044 | { | |
1045 | fun |= 1; | |
1046 | if (!caller_is_thumb) | |
1047 | store_unsigned_integer (dummy + 4, sizeof (arm_bx_r4), arm_bx_r4); | |
1048 | } | |
1049 | ||
1050 | /* If the CPU is currently in Thumb mode, use the Thumb call dummy | |
1051 | instead of the ARM one that's already been copied. This will | |
1052 | work for both Thumb and ARM target functions. */ | |
1053 | if (caller_is_thumb) | |
1054 | { | |
1055 | int i; | |
1056 | char *p = dummy; | |
1057 | int len = sizeof (thumb_dummy) / sizeof (thumb_dummy[0]); | |
1058 | ||
1059 | for (i = 0; i < len; i++) | |
1060 | { | |
1061 | store_unsigned_integer (p, sizeof (thumb_dummy[0]), thumb_dummy[i]); | |
1062 | p += sizeof (thumb_dummy[0]); | |
1063 | } | |
1064 | } | |
1065 | ||
ed9a39eb JM |
1066 | /* Put the target address in r4; the call dummy will copy this to |
1067 | the PC. */ | |
c906108c SS |
1068 | write_register (4, fun); |
1069 | } | |
1070 | ||
c906108c | 1071 | /* Return the offset in the call dummy of the instruction that needs |
ed9a39eb JM |
1072 | to have a breakpoint placed on it. This is the offset of the 'swi |
1073 | 24' instruction, which is no longer actually used, but simply acts | |
c906108c SS |
1074 | as a place-holder now. |
1075 | ||
ed9a39eb | 1076 | This implements the CALL_DUMMY_BREAK_OFFSET macro. */ |
c906108c SS |
1077 | |
1078 | int | |
ed9a39eb | 1079 | arm_call_dummy_breakpoint_offset (void) |
c906108c SS |
1080 | { |
1081 | if (caller_is_thumb) | |
1082 | return 4; | |
1083 | else | |
1084 | return 8; | |
1085 | } | |
1086 | ||
ed9a39eb JM |
1087 | /* Note: ScottB |
1088 | ||
1089 | This function does not support passing parameters using the FPA | |
1090 | variant of the APCS. It passes any floating point arguments in the | |
1091 | general registers and/or on the stack. */ | |
c906108c SS |
1092 | |
1093 | CORE_ADDR | |
ed9a39eb JM |
1094 | arm_push_arguments (int nargs, value_ptr * args, CORE_ADDR sp, |
1095 | int struct_return, CORE_ADDR struct_addr) | |
c906108c | 1096 | { |
ed9a39eb JM |
1097 | char *fp; |
1098 | int argnum, argreg, nstack_size; | |
1099 | ||
1100 | /* Walk through the list of args and determine how large a temporary | |
1101 | stack is required. Need to take care here as structs may be | |
1102 | passed on the stack, and we have to to push them. */ | |
1103 | nstack_size = -4 * REGISTER_SIZE; /* Some arguments go into A1-A4. */ | |
1104 | if (struct_return) /* The struct address goes in A1. */ | |
1105 | nstack_size += REGISTER_SIZE; | |
1106 | ||
1107 | /* Walk through the arguments and add their size to nstack_size. */ | |
1108 | for (argnum = 0; argnum < nargs; argnum++) | |
c5aa993b | 1109 | { |
c906108c | 1110 | int len; |
ed9a39eb JM |
1111 | struct type *arg_type; |
1112 | ||
1113 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1114 | len = TYPE_LENGTH (arg_type); | |
c906108c | 1115 | |
ed9a39eb JM |
1116 | /* ANSI C code passes float arguments as integers, K&R code |
1117 | passes float arguments as doubles. Correct for this here. */ | |
1118 | if (TYPE_CODE_FLT == TYPE_CODE (arg_type) && REGISTER_SIZE == len) | |
1119 | nstack_size += FP_REGISTER_VIRTUAL_SIZE; | |
1120 | else | |
1121 | nstack_size += len; | |
1122 | } | |
c906108c | 1123 | |
ed9a39eb JM |
1124 | /* Allocate room on the stack, and initialize our stack frame |
1125 | pointer. */ | |
1126 | fp = NULL; | |
1127 | if (nstack_size > 0) | |
1128 | { | |
1129 | sp -= nstack_size; | |
1130 | fp = (char *) sp; | |
1131 | } | |
1132 | ||
1133 | /* Initialize the integer argument register pointer. */ | |
c906108c | 1134 | argreg = A1_REGNUM; |
c906108c | 1135 | |
ed9a39eb JM |
1136 | /* The struct_return pointer occupies the first parameter passing |
1137 | register. */ | |
c906108c | 1138 | if (struct_return) |
c5aa993b | 1139 | write_register (argreg++, struct_addr); |
c906108c | 1140 | |
ed9a39eb JM |
1141 | /* Process arguments from left to right. Store as many as allowed |
1142 | in the parameter passing registers (A1-A4), and save the rest on | |
1143 | the temporary stack. */ | |
c5aa993b | 1144 | for (argnum = 0; argnum < nargs; argnum++) |
c906108c | 1145 | { |
ed9a39eb | 1146 | int len; |
c5aa993b | 1147 | char *val; |
ed9a39eb | 1148 | double dbl_arg; |
c5aa993b | 1149 | CORE_ADDR regval; |
ed9a39eb JM |
1150 | enum type_code typecode; |
1151 | struct type *arg_type, *target_type; | |
1152 | ||
1153 | arg_type = check_typedef (VALUE_TYPE (args[argnum])); | |
1154 | target_type = TYPE_TARGET_TYPE (arg_type); | |
1155 | len = TYPE_LENGTH (arg_type); | |
1156 | typecode = TYPE_CODE (arg_type); | |
1157 | val = (char *) VALUE_CONTENTS (args[argnum]); | |
1158 | ||
1159 | /* ANSI C code passes float arguments as integers, K&R code | |
1160 | passes float arguments as doubles. The .stabs record for | |
1161 | for ANSI prototype floating point arguments records the | |
1162 | type as FP_INTEGER, while a K&R style (no prototype) | |
1163 | .stabs records the type as FP_FLOAT. In this latter case | |
1164 | the compiler converts the float arguments to double before | |
1165 | calling the function. */ | |
1166 | if (TYPE_CODE_FLT == typecode && REGISTER_SIZE == len) | |
1167 | { | |
1168 | float f = *(float *) val; | |
1169 | dbl_arg = f; | |
1170 | val = (char *) &dbl_arg; | |
1171 | len = sizeof (double); | |
1172 | } | |
1173 | #if 0 | |
1174 | /* If the argument is a pointer to a function, and it is a Thumb | |
c906108c | 1175 | function, set the low bit of the pointer. */ |
ed9a39eb JM |
1176 | if (TYPE_CODE_PTR == typecode |
1177 | && NULL != target_type | |
1178 | && TYPE_CODE_FUNC == TYPE_CODE (target_type)) | |
c906108c | 1179 | { |
ed9a39eb | 1180 | CORE_ADDR regval = extract_address (val, len); |
c906108c SS |
1181 | if (arm_pc_is_thumb (regval)) |
1182 | store_address (val, len, MAKE_THUMB_ADDR (regval)); | |
1183 | } | |
c906108c | 1184 | #endif |
ed9a39eb JM |
1185 | /* Copy the argument to general registers or the stack in |
1186 | register-sized pieces. Large arguments are split between | |
1187 | registers and stack. */ | |
1188 | while (len > 0) | |
c906108c | 1189 | { |
ed9a39eb JM |
1190 | int partial_len = len < REGISTER_SIZE ? len : REGISTER_SIZE; |
1191 | ||
1192 | if (argreg <= ARM_LAST_ARG_REGNUM) | |
c906108c | 1193 | { |
ed9a39eb JM |
1194 | /* It's an argument being passed in a general register. */ |
1195 | regval = extract_address (val, partial_len); | |
1196 | write_register (argreg++, regval); | |
c906108c | 1197 | } |
ed9a39eb JM |
1198 | else |
1199 | { | |
1200 | /* Push the arguments onto the stack. */ | |
1201 | write_memory ((CORE_ADDR) fp, val, REGISTER_SIZE); | |
1202 | fp += REGISTER_SIZE; | |
1203 | } | |
1204 | ||
1205 | len -= partial_len; | |
1206 | val += partial_len; | |
c906108c SS |
1207 | } |
1208 | } | |
c906108c SS |
1209 | |
1210 | /* Return adjusted stack pointer. */ | |
1211 | return sp; | |
1212 | } | |
1213 | ||
1214 | void | |
ed9a39eb | 1215 | arm_pop_frame (void) |
c906108c | 1216 | { |
c5aa993b | 1217 | struct frame_info *frame = get_current_frame (); |
c906108c | 1218 | int regnum; |
7a292a7a | 1219 | CORE_ADDR old_SP; |
c906108c | 1220 | |
7a292a7a | 1221 | old_SP = read_register (frame->framereg); |
c906108c SS |
1222 | for (regnum = 0; regnum < NUM_REGS; regnum++) |
1223 | if (frame->fsr.regs[regnum] != 0) | |
c5aa993b | 1224 | write_register (regnum, |
c906108c SS |
1225 | read_memory_integer (frame->fsr.regs[regnum], 4)); |
1226 | ||
1227 | write_register (PC_REGNUM, FRAME_SAVED_PC (frame)); | |
7a292a7a | 1228 | write_register (SP_REGNUM, old_SP); |
c906108c SS |
1229 | |
1230 | flush_cached_frames (); | |
1231 | } | |
1232 | ||
1233 | static void | |
ed9a39eb | 1234 | print_fpu_flags (int flags) |
c906108c | 1235 | { |
c5aa993b JM |
1236 | if (flags & (1 << 0)) |
1237 | fputs ("IVO ", stdout); | |
1238 | if (flags & (1 << 1)) | |
1239 | fputs ("DVZ ", stdout); | |
1240 | if (flags & (1 << 2)) | |
1241 | fputs ("OFL ", stdout); | |
1242 | if (flags & (1 << 3)) | |
1243 | fputs ("UFL ", stdout); | |
1244 | if (flags & (1 << 4)) | |
1245 | fputs ("INX ", stdout); | |
1246 | putchar ('\n'); | |
c906108c SS |
1247 | } |
1248 | ||
1249 | void | |
ed9a39eb | 1250 | arm_float_info (void) |
c906108c | 1251 | { |
c5aa993b JM |
1252 | register unsigned long status = read_register (FPS_REGNUM); |
1253 | int type; | |
1254 | ||
1255 | type = (status >> 24) & 127; | |
1256 | printf ("%s FPU type %d\n", | |
ed9a39eb | 1257 | (status & (1 << 31)) ? "Hardware" : "Software", |
c5aa993b JM |
1258 | type); |
1259 | fputs ("mask: ", stdout); | |
1260 | print_fpu_flags (status >> 16); | |
1261 | fputs ("flags: ", stdout); | |
1262 | print_fpu_flags (status); | |
c906108c SS |
1263 | } |
1264 | ||
96baa820 JM |
1265 | /* If the disassembly mode is APCS, we have to also switch the |
1266 | bfd mach_type. This function is run in the set disassembly_flavor | |
1267 | command, and does that. */ | |
1268 | ||
c906108c | 1269 | static void |
ed9a39eb JM |
1270 | set_disassembly_flavor_sfunc (char *args, int from_tty, |
1271 | struct cmd_list_element *c) | |
c906108c | 1272 | { |
96baa820 | 1273 | set_disassembly_flavor (); |
96baa820 | 1274 | } |
085dd6e6 | 1275 | |
96baa820 | 1276 | static void |
ed9a39eb | 1277 | set_disassembly_flavor (void) |
96baa820 JM |
1278 | { |
1279 | if (disassembly_flavor == apcs_flavor) | |
c5aa993b | 1280 | { |
96baa820 JM |
1281 | if (arm_toggle_regnames () == 0) |
1282 | arm_toggle_regnames (); | |
1283 | arm_register_names = apcs_register_names; | |
1284 | } | |
1285 | else if (disassembly_flavor == r_prefix_flavor) | |
1286 | { | |
1287 | if (arm_toggle_regnames () == 1) | |
1288 | arm_toggle_regnames (); | |
ed9a39eb JM |
1289 | arm_register_names = additional_register_names; |
1290 | } | |
96baa820 JM |
1291 | } |
1292 | ||
ed9a39eb JM |
1293 | /* arm_othernames implements the "othernames" command. This is kind |
1294 | of hacky, and I prefer the set-show disassembly-flavor which is | |
1295 | also used for the x86 gdb. I will keep this around, however, in | |
1296 | case anyone is actually using it. */ | |
96baa820 JM |
1297 | |
1298 | static void | |
ed9a39eb | 1299 | arm_othernames (char *names, int n) |
96baa820 JM |
1300 | { |
1301 | if (disassembly_flavor == r_prefix_flavor) | |
1302 | { | |
1303 | disassembly_flavor = apcs_flavor; | |
1304 | set_disassembly_flavor (); | |
c5aa993b JM |
1305 | } |
1306 | else | |
1307 | { | |
96baa820 JM |
1308 | disassembly_flavor = r_prefix_flavor; |
1309 | set_disassembly_flavor (); | |
c5aa993b | 1310 | } |
c906108c SS |
1311 | } |
1312 | ||
ed9a39eb JM |
1313 | #if 0 |
1314 | /* FIXME: The generated assembler works but sucks. Instead of using | |
1315 | r0, r1 it pushes them on the stack, then loads them into r3, r4 and | |
1316 | uses those registers. I must be missing something. ScottB */ | |
c906108c | 1317 | |
c5aa993b | 1318 | void |
ed9a39eb JM |
1319 | convert_from_extended (void *ptr, void *dbl) |
1320 | { | |
1321 | __asm__ (" | |
1322 | ldfe f0,[%0] | |
1323 | stfd f0,[%1] " | |
1324 | : /* no output */ | |
1325 | : "r" (ptr), "r" (dbl)); | |
1326 | } | |
1327 | ||
1328 | void | |
1329 | convert_to_extended (void *dbl, void *ptr) | |
1330 | { | |
1331 | __asm__ (" | |
1332 | ldfd f0,[%0] | |
1333 | stfe f0,[%1] " | |
1334 | : /* no output */ | |
1335 | : "r" (dbl), "r" (ptr)); | |
1336 | } | |
1337 | #else | |
1338 | static void | |
1339 | convert_from_extended (void *ptr, void *dbl) | |
c906108c | 1340 | { |
104c1213 | 1341 | *(double *) dbl = *(double *) ptr; |
c906108c SS |
1342 | } |
1343 | ||
c5aa993b | 1344 | void |
ed9a39eb | 1345 | convert_to_extended (void *dbl, void *ptr) |
c906108c | 1346 | { |
104c1213 | 1347 | *(double *) ptr = *(double *) dbl; |
c906108c | 1348 | } |
ed9a39eb JM |
1349 | #endif |
1350 | ||
1351 | /* Nonzero if register N requires conversion from raw format to | |
1352 | virtual format. */ | |
1353 | ||
1354 | int | |
1355 | arm_register_convertible (unsigned int regnum) | |
1356 | { | |
1357 | return ((regnum - F0_REGNUM) < 8); | |
1358 | } | |
1359 | ||
1360 | /* Convert data from raw format for register REGNUM in buffer FROM to | |
1361 | virtual format with type TYPE in buffer TO. */ | |
1362 | ||
1363 | void | |
1364 | arm_register_convert_to_virtual (unsigned int regnum, struct type *type, | |
1365 | void *from, void *to) | |
1366 | { | |
1367 | double val; | |
1368 | ||
1369 | convert_from_extended (from, &val); | |
1370 | store_floating (to, TYPE_LENGTH (type), val); | |
1371 | } | |
1372 | ||
1373 | /* Convert data from virtual format with type TYPE in buffer FROM to | |
1374 | raw format for register REGNUM in buffer TO. */ | |
1375 | ||
1376 | void | |
1377 | arm_register_convert_to_raw (unsigned int regnum, struct type *type, | |
1378 | void *from, void *to) | |
1379 | { | |
1380 | double val = extract_floating (from, TYPE_LENGTH (type)); | |
1381 | ||
1382 | convert_to_extended (&val, to); | |
1383 | } | |
c906108c SS |
1384 | |
1385 | static int | |
ed9a39eb | 1386 | condition_true (unsigned long cond, unsigned long status_reg) |
c906108c SS |
1387 | { |
1388 | if (cond == INST_AL || cond == INST_NV) | |
1389 | return 1; | |
1390 | ||
1391 | switch (cond) | |
1392 | { | |
1393 | case INST_EQ: | |
1394 | return ((status_reg & FLAG_Z) != 0); | |
1395 | case INST_NE: | |
1396 | return ((status_reg & FLAG_Z) == 0); | |
1397 | case INST_CS: | |
1398 | return ((status_reg & FLAG_C) != 0); | |
1399 | case INST_CC: | |
1400 | return ((status_reg & FLAG_C) == 0); | |
1401 | case INST_MI: | |
1402 | return ((status_reg & FLAG_N) != 0); | |
1403 | case INST_PL: | |
1404 | return ((status_reg & FLAG_N) == 0); | |
1405 | case INST_VS: | |
1406 | return ((status_reg & FLAG_V) != 0); | |
1407 | case INST_VC: | |
1408 | return ((status_reg & FLAG_V) == 0); | |
1409 | case INST_HI: | |
1410 | return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C); | |
1411 | case INST_LS: | |
1412 | return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C); | |
1413 | case INST_GE: | |
1414 | return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0)); | |
1415 | case INST_LT: | |
1416 | return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0)); | |
1417 | case INST_GT: | |
1418 | return (((status_reg & FLAG_Z) == 0) && | |
ed9a39eb | 1419 | (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1420 | case INST_LE: |
1421 | return (((status_reg & FLAG_Z) != 0) || | |
ed9a39eb | 1422 | (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0))); |
c906108c SS |
1423 | } |
1424 | return 1; | |
1425 | } | |
1426 | ||
1427 | #define submask(x) ((1L << ((x) + 1)) - 1) | |
1428 | #define bit(obj,st) (((obj) >> (st)) & 1) | |
1429 | #define bits(obj,st,fn) (((obj) >> (st)) & submask ((fn) - (st))) | |
1430 | #define sbits(obj,st,fn) \ | |
1431 | ((long) (bits(obj,st,fn) | ((long) bit(obj,fn) * ~ submask (fn - st)))) | |
1432 | #define BranchDest(addr,instr) \ | |
1433 | ((CORE_ADDR) (((long) (addr)) + 8 + (sbits (instr, 0, 23) << 2))) | |
1434 | #define ARM_PC_32 1 | |
1435 | ||
1436 | static unsigned long | |
ed9a39eb JM |
1437 | shifted_reg_val (unsigned long inst, int carry, unsigned long pc_val, |
1438 | unsigned long status_reg) | |
c906108c SS |
1439 | { |
1440 | unsigned long res, shift; | |
1441 | int rm = bits (inst, 0, 3); | |
1442 | unsigned long shifttype = bits (inst, 5, 6); | |
c5aa993b JM |
1443 | |
1444 | if (bit (inst, 4)) | |
c906108c SS |
1445 | { |
1446 | int rs = bits (inst, 8, 11); | |
1447 | shift = (rs == 15 ? pc_val + 8 : read_register (rs)) & 0xFF; | |
1448 | } | |
1449 | else | |
1450 | shift = bits (inst, 7, 11); | |
c5aa993b JM |
1451 | |
1452 | res = (rm == 15 | |
c906108c | 1453 | ? ((pc_val | (ARM_PC_32 ? 0 : status_reg)) |
c5aa993b | 1454 | + (bit (inst, 4) ? 12 : 8)) |
c906108c SS |
1455 | : read_register (rm)); |
1456 | ||
1457 | switch (shifttype) | |
1458 | { | |
c5aa993b | 1459 | case 0: /* LSL */ |
c906108c SS |
1460 | res = shift >= 32 ? 0 : res << shift; |
1461 | break; | |
c5aa993b JM |
1462 | |
1463 | case 1: /* LSR */ | |
c906108c SS |
1464 | res = shift >= 32 ? 0 : res >> shift; |
1465 | break; | |
1466 | ||
c5aa993b JM |
1467 | case 2: /* ASR */ |
1468 | if (shift >= 32) | |
1469 | shift = 31; | |
c906108c SS |
1470 | res = ((res & 0x80000000L) |
1471 | ? ~((~res) >> shift) : res >> shift); | |
1472 | break; | |
1473 | ||
c5aa993b | 1474 | case 3: /* ROR/RRX */ |
c906108c SS |
1475 | shift &= 31; |
1476 | if (shift == 0) | |
1477 | res = (res >> 1) | (carry ? 0x80000000L : 0); | |
1478 | else | |
c5aa993b | 1479 | res = (res >> shift) | (res << (32 - shift)); |
c906108c SS |
1480 | break; |
1481 | } | |
1482 | ||
1483 | return res & 0xffffffff; | |
1484 | } | |
1485 | ||
c906108c SS |
1486 | /* Return number of 1-bits in VAL. */ |
1487 | ||
1488 | static int | |
ed9a39eb | 1489 | bitcount (unsigned long val) |
c906108c SS |
1490 | { |
1491 | int nbits; | |
1492 | for (nbits = 0; val != 0; nbits++) | |
c5aa993b | 1493 | val &= val - 1; /* delete rightmost 1-bit in val */ |
c906108c SS |
1494 | return nbits; |
1495 | } | |
1496 | ||
c906108c | 1497 | static CORE_ADDR |
ed9a39eb | 1498 | thumb_get_next_pc (CORE_ADDR pc) |
c906108c | 1499 | { |
c5aa993b | 1500 | unsigned long pc_val = ((unsigned long) pc) + 4; /* PC after prefetch */ |
c906108c | 1501 | unsigned short inst1 = read_memory_integer (pc, 2); |
c5aa993b | 1502 | CORE_ADDR nextpc = pc + 2; /* default is next instruction */ |
c906108c SS |
1503 | unsigned long offset; |
1504 | ||
1505 | if ((inst1 & 0xff00) == 0xbd00) /* pop {rlist, pc} */ | |
1506 | { | |
1507 | CORE_ADDR sp; | |
1508 | ||
1509 | /* Fetch the saved PC from the stack. It's stored above | |
1510 | all of the other registers. */ | |
1511 | offset = bitcount (bits (inst1, 0, 7)) * REGISTER_SIZE; | |
1512 | sp = read_register (SP_REGNUM); | |
1513 | nextpc = (CORE_ADDR) read_memory_integer (sp + offset, 4); | |
1514 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1515 | if (nextpc == pc) | |
1516 | error ("Infinite loop detected"); | |
1517 | } | |
1518 | else if ((inst1 & 0xf000) == 0xd000) /* conditional branch */ | |
1519 | { | |
1520 | unsigned long status = read_register (PS_REGNUM); | |
c5aa993b | 1521 | unsigned long cond = bits (inst1, 8, 11); |
c906108c SS |
1522 | if (cond != 0x0f && condition_true (cond, status)) /* 0x0f = SWI */ |
1523 | nextpc = pc_val + (sbits (inst1, 0, 7) << 1); | |
1524 | } | |
1525 | else if ((inst1 & 0xf800) == 0xe000) /* unconditional branch */ | |
1526 | { | |
1527 | nextpc = pc_val + (sbits (inst1, 0, 10) << 1); | |
1528 | } | |
1529 | else if ((inst1 & 0xf800) == 0xf000) /* long branch with link */ | |
1530 | { | |
1531 | unsigned short inst2 = read_memory_integer (pc + 2, 2); | |
c5aa993b | 1532 | offset = (sbits (inst1, 0, 10) << 12) + (bits (inst2, 0, 10) << 1); |
c906108c SS |
1533 | nextpc = pc_val + offset; |
1534 | } | |
1535 | ||
1536 | return nextpc; | |
1537 | } | |
1538 | ||
c906108c | 1539 | CORE_ADDR |
ed9a39eb | 1540 | arm_get_next_pc (CORE_ADDR pc) |
c906108c SS |
1541 | { |
1542 | unsigned long pc_val; | |
1543 | unsigned long this_instr; | |
1544 | unsigned long status; | |
1545 | CORE_ADDR nextpc; | |
1546 | ||
1547 | if (arm_pc_is_thumb (pc)) | |
1548 | return thumb_get_next_pc (pc); | |
1549 | ||
1550 | pc_val = (unsigned long) pc; | |
1551 | this_instr = read_memory_integer (pc, 4); | |
1552 | status = read_register (PS_REGNUM); | |
c5aa993b | 1553 | nextpc = (CORE_ADDR) (pc_val + 4); /* Default case */ |
c906108c SS |
1554 | |
1555 | if (condition_true (bits (this_instr, 28, 31), status)) | |
1556 | { | |
1557 | switch (bits (this_instr, 24, 27)) | |
1558 | { | |
c5aa993b JM |
1559 | case 0x0: |
1560 | case 0x1: /* data processing */ | |
1561 | case 0x2: | |
1562 | case 0x3: | |
c906108c SS |
1563 | { |
1564 | unsigned long operand1, operand2, result = 0; | |
1565 | unsigned long rn; | |
1566 | int c; | |
c5aa993b | 1567 | |
c906108c SS |
1568 | if (bits (this_instr, 12, 15) != 15) |
1569 | break; | |
1570 | ||
1571 | if (bits (this_instr, 22, 25) == 0 | |
c5aa993b | 1572 | && bits (this_instr, 4, 7) == 9) /* multiply */ |
c906108c SS |
1573 | error ("Illegal update to pc in instruction"); |
1574 | ||
1575 | /* Multiply into PC */ | |
1576 | c = (status & FLAG_C) ? 1 : 0; | |
1577 | rn = bits (this_instr, 16, 19); | |
1578 | operand1 = (rn == 15) ? pc_val + 8 : read_register (rn); | |
c5aa993b | 1579 | |
c906108c SS |
1580 | if (bit (this_instr, 25)) |
1581 | { | |
1582 | unsigned long immval = bits (this_instr, 0, 7); | |
1583 | unsigned long rotate = 2 * bits (this_instr, 8, 11); | |
c5aa993b JM |
1584 | operand2 = ((immval >> rotate) | (immval << (32 - rotate))) |
1585 | & 0xffffffff; | |
c906108c | 1586 | } |
c5aa993b | 1587 | else /* operand 2 is a shifted register */ |
c906108c | 1588 | operand2 = shifted_reg_val (this_instr, c, pc_val, status); |
c5aa993b | 1589 | |
c906108c SS |
1590 | switch (bits (this_instr, 21, 24)) |
1591 | { | |
c5aa993b | 1592 | case 0x0: /*and */ |
c906108c SS |
1593 | result = operand1 & operand2; |
1594 | break; | |
1595 | ||
c5aa993b | 1596 | case 0x1: /*eor */ |
c906108c SS |
1597 | result = operand1 ^ operand2; |
1598 | break; | |
1599 | ||
c5aa993b | 1600 | case 0x2: /*sub */ |
c906108c SS |
1601 | result = operand1 - operand2; |
1602 | break; | |
1603 | ||
c5aa993b | 1604 | case 0x3: /*rsb */ |
c906108c SS |
1605 | result = operand2 - operand1; |
1606 | break; | |
1607 | ||
c5aa993b | 1608 | case 0x4: /*add */ |
c906108c SS |
1609 | result = operand1 + operand2; |
1610 | break; | |
1611 | ||
c5aa993b | 1612 | case 0x5: /*adc */ |
c906108c SS |
1613 | result = operand1 + operand2 + c; |
1614 | break; | |
1615 | ||
c5aa993b | 1616 | case 0x6: /*sbc */ |
c906108c SS |
1617 | result = operand1 - operand2 + c; |
1618 | break; | |
1619 | ||
c5aa993b | 1620 | case 0x7: /*rsc */ |
c906108c SS |
1621 | result = operand2 - operand1 + c; |
1622 | break; | |
1623 | ||
c5aa993b JM |
1624 | case 0x8: |
1625 | case 0x9: | |
1626 | case 0xa: | |
1627 | case 0xb: /* tst, teq, cmp, cmn */ | |
c906108c SS |
1628 | result = (unsigned long) nextpc; |
1629 | break; | |
1630 | ||
c5aa993b | 1631 | case 0xc: /*orr */ |
c906108c SS |
1632 | result = operand1 | operand2; |
1633 | break; | |
1634 | ||
c5aa993b | 1635 | case 0xd: /*mov */ |
c906108c SS |
1636 | /* Always step into a function. */ |
1637 | result = operand2; | |
c5aa993b | 1638 | break; |
c906108c | 1639 | |
c5aa993b | 1640 | case 0xe: /*bic */ |
c906108c SS |
1641 | result = operand1 & ~operand2; |
1642 | break; | |
1643 | ||
c5aa993b | 1644 | case 0xf: /*mvn */ |
c906108c SS |
1645 | result = ~operand2; |
1646 | break; | |
1647 | } | |
1648 | nextpc = (CORE_ADDR) ADDR_BITS_REMOVE (result); | |
1649 | ||
1650 | if (nextpc == pc) | |
1651 | error ("Infinite loop detected"); | |
1652 | break; | |
1653 | } | |
c5aa993b JM |
1654 | |
1655 | case 0x4: | |
1656 | case 0x5: /* data transfer */ | |
1657 | case 0x6: | |
1658 | case 0x7: | |
c906108c SS |
1659 | if (bit (this_instr, 20)) |
1660 | { | |
1661 | /* load */ | |
1662 | if (bits (this_instr, 12, 15) == 15) | |
1663 | { | |
1664 | /* rd == pc */ | |
c5aa993b | 1665 | unsigned long rn; |
c906108c | 1666 | unsigned long base; |
c5aa993b | 1667 | |
c906108c SS |
1668 | if (bit (this_instr, 22)) |
1669 | error ("Illegal update to pc in instruction"); | |
1670 | ||
1671 | /* byte write to PC */ | |
1672 | rn = bits (this_instr, 16, 19); | |
1673 | base = (rn == 15) ? pc_val + 8 : read_register (rn); | |
1674 | if (bit (this_instr, 24)) | |
1675 | { | |
1676 | /* pre-indexed */ | |
1677 | int c = (status & FLAG_C) ? 1 : 0; | |
1678 | unsigned long offset = | |
c5aa993b | 1679 | (bit (this_instr, 25) |
ed9a39eb | 1680 | ? shifted_reg_val (this_instr, c, pc_val, status) |
c5aa993b | 1681 | : bits (this_instr, 0, 11)); |
c906108c SS |
1682 | |
1683 | if (bit (this_instr, 23)) | |
1684 | base += offset; | |
1685 | else | |
1686 | base -= offset; | |
1687 | } | |
c5aa993b | 1688 | nextpc = (CORE_ADDR) read_memory_integer ((CORE_ADDR) base, |
c906108c | 1689 | 4); |
c5aa993b | 1690 | |
c906108c SS |
1691 | nextpc = ADDR_BITS_REMOVE (nextpc); |
1692 | ||
1693 | if (nextpc == pc) | |
1694 | error ("Infinite loop detected"); | |
1695 | } | |
1696 | } | |
1697 | break; | |
c5aa993b JM |
1698 | |
1699 | case 0x8: | |
1700 | case 0x9: /* block transfer */ | |
c906108c SS |
1701 | if (bit (this_instr, 20)) |
1702 | { | |
1703 | /* LDM */ | |
1704 | if (bit (this_instr, 15)) | |
1705 | { | |
1706 | /* loading pc */ | |
1707 | int offset = 0; | |
1708 | ||
1709 | if (bit (this_instr, 23)) | |
1710 | { | |
1711 | /* up */ | |
1712 | unsigned long reglist = bits (this_instr, 0, 14); | |
1713 | offset = bitcount (reglist) * 4; | |
c5aa993b | 1714 | if (bit (this_instr, 24)) /* pre */ |
c906108c SS |
1715 | offset += 4; |
1716 | } | |
1717 | else if (bit (this_instr, 24)) | |
1718 | offset = -4; | |
c5aa993b | 1719 | |
c906108c | 1720 | { |
c5aa993b JM |
1721 | unsigned long rn_val = |
1722 | read_register (bits (this_instr, 16, 19)); | |
c906108c SS |
1723 | nextpc = |
1724 | (CORE_ADDR) read_memory_integer ((CORE_ADDR) (rn_val | |
c5aa993b | 1725 | + offset), |
c906108c SS |
1726 | 4); |
1727 | } | |
1728 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1729 | if (nextpc == pc) | |
1730 | error ("Infinite loop detected"); | |
1731 | } | |
1732 | } | |
1733 | break; | |
c5aa993b JM |
1734 | |
1735 | case 0xb: /* branch & link */ | |
1736 | case 0xa: /* branch */ | |
c906108c SS |
1737 | { |
1738 | nextpc = BranchDest (pc, this_instr); | |
1739 | ||
1740 | nextpc = ADDR_BITS_REMOVE (nextpc); | |
1741 | if (nextpc == pc) | |
1742 | error ("Infinite loop detected"); | |
1743 | break; | |
1744 | } | |
c5aa993b JM |
1745 | |
1746 | case 0xc: | |
1747 | case 0xd: | |
1748 | case 0xe: /* coproc ops */ | |
1749 | case 0xf: /* SWI */ | |
c906108c SS |
1750 | break; |
1751 | ||
1752 | default: | |
1753 | fprintf (stderr, "Bad bit-field extraction\n"); | |
1754 | return (pc); | |
1755 | } | |
1756 | } | |
1757 | ||
1758 | return nextpc; | |
1759 | } | |
1760 | ||
1761 | #include "bfd-in2.h" | |
1762 | #include "libcoff.h" | |
1763 | ||
1764 | static int | |
ed9a39eb | 1765 | gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) |
c906108c SS |
1766 | { |
1767 | if (arm_pc_is_thumb (memaddr)) | |
1768 | { | |
c5aa993b JM |
1769 | static asymbol *asym; |
1770 | static combined_entry_type ce; | |
1771 | static struct coff_symbol_struct csym; | |
1772 | static struct _bfd fake_bfd; | |
1773 | static bfd_target fake_target; | |
c906108c SS |
1774 | |
1775 | if (csym.native == NULL) | |
1776 | { | |
1777 | /* Create a fake symbol vector containing a Thumb symbol. This is | |
1778 | solely so that the code in print_insn_little_arm() and | |
1779 | print_insn_big_arm() in opcodes/arm-dis.c will detect the presence | |
1780 | of a Thumb symbol and switch to decoding Thumb instructions. */ | |
c5aa993b JM |
1781 | |
1782 | fake_target.flavour = bfd_target_coff_flavour; | |
1783 | fake_bfd.xvec = &fake_target; | |
c906108c | 1784 | ce.u.syment.n_sclass = C_THUMBEXTFUNC; |
c5aa993b JM |
1785 | csym.native = &ce; |
1786 | csym.symbol.the_bfd = &fake_bfd; | |
1787 | csym.symbol.name = "fake"; | |
1788 | asym = (asymbol *) & csym; | |
c906108c | 1789 | } |
c5aa993b | 1790 | |
c906108c | 1791 | memaddr = UNMAKE_THUMB_ADDR (memaddr); |
c5aa993b | 1792 | info->symbols = &asym; |
c906108c SS |
1793 | } |
1794 | else | |
1795 | info->symbols = NULL; | |
c5aa993b | 1796 | |
c906108c SS |
1797 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) |
1798 | return print_insn_big_arm (memaddr, info); | |
1799 | else | |
1800 | return print_insn_little_arm (memaddr, info); | |
1801 | } | |
1802 | ||
ed9a39eb JM |
1803 | /* This function implements the BREAKPOINT_FROM_PC macro. It uses the |
1804 | program counter value to determine whether a 16-bit or 32-bit | |
1805 | breakpoint should be used. It returns a pointer to a string of | |
1806 | bytes that encode a breakpoint instruction, stores the length of | |
1807 | the string to *lenptr, and adjusts the program counter (if | |
1808 | necessary) to point to the actual memory location where the | |
c906108c SS |
1809 | breakpoint should be inserted. */ |
1810 | ||
1811 | unsigned char * | |
ed9a39eb | 1812 | arm_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) |
c906108c SS |
1813 | { |
1814 | if (arm_pc_is_thumb (*pcptr) || arm_pc_is_thumb_dummy (*pcptr)) | |
1815 | { | |
1816 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b JM |
1817 | { |
1818 | static char thumb_breakpoint[] = THUMB_BE_BREAKPOINT; | |
1819 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1820 | *lenptr = sizeof (thumb_breakpoint); | |
1821 | return thumb_breakpoint; | |
1822 | } | |
c906108c | 1823 | else |
c5aa993b JM |
1824 | { |
1825 | static char thumb_breakpoint[] = THUMB_LE_BREAKPOINT; | |
1826 | *pcptr = UNMAKE_THUMB_ADDR (*pcptr); | |
1827 | *lenptr = sizeof (thumb_breakpoint); | |
1828 | return thumb_breakpoint; | |
1829 | } | |
c906108c SS |
1830 | } |
1831 | else | |
1832 | { | |
1833 | if (TARGET_BYTE_ORDER == BIG_ENDIAN) | |
c5aa993b JM |
1834 | { |
1835 | static char arm_breakpoint[] = ARM_BE_BREAKPOINT; | |
1836 | *lenptr = sizeof (arm_breakpoint); | |
1837 | return arm_breakpoint; | |
1838 | } | |
c906108c | 1839 | else |
c5aa993b JM |
1840 | { |
1841 | static char arm_breakpoint[] = ARM_LE_BREAKPOINT; | |
1842 | *lenptr = sizeof (arm_breakpoint); | |
1843 | return arm_breakpoint; | |
1844 | } | |
c906108c SS |
1845 | } |
1846 | } | |
ed9a39eb JM |
1847 | |
1848 | /* Extract from an array REGBUF containing the (raw) register state a | |
1849 | function return value of type TYPE, and copy that, in virtual | |
1850 | format, into VALBUF. */ | |
1851 | ||
1852 | void | |
1853 | arm_extract_return_value (struct type *type, | |
1854 | char regbuf[REGISTER_BYTES], | |
1855 | char *valbuf) | |
1856 | { | |
1857 | if (TYPE_CODE_FLT == TYPE_CODE (type)) | |
1858 | convert_from_extended (®buf[REGISTER_BYTE (F0_REGNUM)], valbuf); | |
1859 | else | |
1860 | memcpy (valbuf, ®buf[REGISTER_BYTE (A1_REGNUM)], TYPE_LENGTH (type)); | |
1861 | } | |
1862 | ||
1863 | /* Return non-zero if the PC is inside a thumb call thunk. */ | |
c906108c SS |
1864 | |
1865 | int | |
ed9a39eb | 1866 | arm_in_call_stub (CORE_ADDR pc, char *name) |
c906108c SS |
1867 | { |
1868 | CORE_ADDR start_addr; | |
1869 | ||
ed9a39eb JM |
1870 | /* Find the starting address of the function containing the PC. If |
1871 | the caller didn't give us a name, look it up at the same time. */ | |
c906108c SS |
1872 | if (find_pc_partial_function (pc, name ? NULL : &name, &start_addr, NULL) == 0) |
1873 | return 0; | |
1874 | ||
1875 | return strncmp (name, "_call_via_r", 11) == 0; | |
1876 | } | |
1877 | ||
ed9a39eb JM |
1878 | /* If PC is in a Thumb call or return stub, return the address of the |
1879 | target PC, which is in a register. The thunk functions are called | |
1880 | _called_via_xx, where x is the register name. The possible names | |
1881 | are r0-r9, sl, fp, ip, sp, and lr. */ | |
c906108c SS |
1882 | |
1883 | CORE_ADDR | |
ed9a39eb | 1884 | arm_skip_stub (CORE_ADDR pc) |
c906108c | 1885 | { |
c5aa993b | 1886 | char *name; |
c906108c SS |
1887 | CORE_ADDR start_addr; |
1888 | ||
1889 | /* Find the starting address and name of the function containing the PC. */ | |
1890 | if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) | |
1891 | return 0; | |
1892 | ||
1893 | /* Call thunks always start with "_call_via_". */ | |
1894 | if (strncmp (name, "_call_via_", 10) == 0) | |
1895 | { | |
ed9a39eb JM |
1896 | /* Use the name suffix to determine which register contains the |
1897 | target PC. */ | |
c5aa993b JM |
1898 | static char *table[15] = |
1899 | {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
1900 | "r8", "r9", "sl", "fp", "ip", "sp", "lr" | |
1901 | }; | |
c906108c SS |
1902 | int regno; |
1903 | ||
1904 | for (regno = 0; regno <= 14; regno++) | |
1905 | if (strcmp (&name[10], table[regno]) == 0) | |
1906 | return read_register (regno); | |
1907 | } | |
ed9a39eb | 1908 | |
c5aa993b | 1909 | return 0; /* not a stub */ |
c906108c SS |
1910 | } |
1911 | ||
c906108c | 1912 | void |
ed9a39eb | 1913 | _initialize_arm_tdep (void) |
c906108c | 1914 | { |
96baa820 | 1915 | struct cmd_list_element *new_cmd; |
085dd6e6 | 1916 | |
c906108c | 1917 | tm_print_insn = gdb_print_insn_arm; |
ed9a39eb | 1918 | |
085dd6e6 | 1919 | /* Sync the opcode insn printer with our register viewer: */ |
c906108c | 1920 | |
96baa820 | 1921 | if (arm_toggle_regnames () != 1) |
085dd6e6 | 1922 | arm_toggle_regnames (); |
c5aa993b | 1923 | |
96baa820 | 1924 | /* Add the deprecated "othernames" command */ |
ed9a39eb | 1925 | |
c906108c SS |
1926 | add_com ("othernames", class_obscure, arm_othernames, |
1927 | "Switch to the other set of register names."); | |
1928 | ||
96baa820 | 1929 | /* Add the disassembly-flavor command */ |
ed9a39eb | 1930 | |
96baa820 | 1931 | new_cmd = add_set_enum_cmd ("disassembly-flavor", no_class, |
ed9a39eb JM |
1932 | valid_flavors, |
1933 | (char *) &disassembly_flavor, | |
1934 | "Set the disassembly flavor, \ | |
96baa820 JM |
1935 | the valid values are \"apcs\" and \"r-prefix\", \ |
1936 | and the default value is \"apcs\".", | |
ed9a39eb | 1937 | &setlist); |
96baa820 | 1938 | new_cmd->function.sfunc = set_disassembly_flavor_sfunc; |
ed9a39eb JM |
1939 | add_show_from_set (new_cmd, &showlist); |
1940 | ||
c906108c SS |
1941 | /* ??? Maybe this should be a boolean. */ |
1942 | add_show_from_set (add_set_cmd ("apcs32", no_class, | |
ed9a39eb | 1943 | var_zinteger, (char *) &arm_apcs_32, |
96baa820 | 1944 | "Set usage of ARM 32-bit mode.\n", &setlist), |
ed9a39eb | 1945 | &showlist); |
c906108c SS |
1946 | |
1947 | } | |
1948 | ||
ed9a39eb JM |
1949 | /* Test whether the coff symbol specific value corresponds to a Thumb |
1950 | function. */ | |
1951 | ||
c906108c | 1952 | int |
c5aa993b | 1953 | coff_sym_is_thumb (int val) |
c906108c | 1954 | { |
c5aa993b JM |
1955 | return (val == C_THUMBEXT || |
1956 | val == C_THUMBSTAT || | |
1957 | val == C_THUMBEXTFUNC || | |
1958 | val == C_THUMBSTATFUNC || | |
1959 | val == C_THUMBLABEL); | |
c906108c | 1960 | } |