[thirdparty/binutils-gdb.git] / gdb / arm-tdep.h

/* Common target dependent code for GDB on ARM systems.
   Copyright (C) 2002-2023 Free Software Foundation, Inc.

   This file is part of GDB.

   This program is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3 of the License, or
   (at your option) any later version.

   This program is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */

#ifndef ARM_TDEP_H
#define ARM_TDEP_H

/* Forward declarations.  */
struct regset;
struct address_space;
struct get_next_pcs;
struct arm_get_next_pcs;
struct gdb_get_next_pcs;

/* Set to true if the 32-bit mode is in use.  */

extern bool arm_apcs_32;

#include "gdbarch.h"
#include "arch/arm.h"
#include "infrun.h"

#include <vector>

/* Number of machine registers.  The only define actually required 
   is gdbarch_num_regs.  The other definitions are used for documentation
   purposes and code readability.  */
/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
   (and called PS for processor status) so the status bits can be cleared
   from the PC (register 15).  For 32 bit ARM code, a copy of CPSR is placed
   in PS.  */
#define NUM_FREGS	8	/* Number of floating point registers.  */
#define NUM_SREGS	2	/* Number of status registers.  */
#define NUM_GREGS	16	/* Number of general purpose registers.  */


/* Type of floating-point code in use by inferior.  There are really 3 models
   that are traditionally supported (plus the endianness issue), but gcc can
   only generate 2 of those.  The third is APCS_FLOAT, where arguments to
   functions are passed in floating-point registers.  

   In addition to the traditional models, VFP adds two more. 

   If you update this enum, don't forget to update fp_model_strings in 
   arm-tdep.c.  */

enum arm_float_model
{
  ARM_FLOAT_AUTO,	/* Automatic detection.  Do not set in tdep.  */
  ARM_FLOAT_SOFT_FPA,	/* Traditional soft-float (mixed-endian on LE ARM).  */
  ARM_FLOAT_FPA,	/* FPA co-processor.  GCC calling convention.  */
  ARM_FLOAT_SOFT_VFP,	/* Soft-float with pure-endian doubles.  */
  ARM_FLOAT_VFP,	/* Full VFP calling convention.  */
  ARM_FLOAT_LAST	/* Keep at end.  */
};

/* ABI used by the inferior.  */
enum arm_abi_kind
{
  ARM_ABI_AUTO,
  ARM_ABI_APCS,
  ARM_ABI_AAPCS,
  ARM_ABI_LAST
};

/* Convention for returning structures.  */

enum struct_return
{
  pcc_struct_return,		/* Return "short" structures in memory.  */
  reg_struct_return		/* Return "short" structures in registers.  */
};

/* Target-dependent structure in gdbarch.  */
struct arm_gdbarch_tdep : gdbarch_tdep_base
{
  /* The ABI for this architecture.  It should never be set to
     ARM_ABI_AUTO.  */
  enum arm_abi_kind arm_abi {};

  enum arm_float_model fp_model {}; /* Floating point calling conventions.  */

  bool have_fpa_registers = false;	/* Does the target report the FPA registers?  */
  bool have_wmmx_registers = false;	/* Does the target report the WMMX registers?  */
  /* The number of VFP registers reported by the target.  It is zero
     if VFP registers are not supported.  */
  int vfp_register_count = 0;
  bool have_s_pseudos = false;	/* Are we synthesizing the single precision
				   VFP registers?  */
  int s_pseudo_base = 0;	/* Register number for the first S pseudo
				   register.  */
  int s_pseudo_count = 0;	/* Number of S pseudo registers.  */
  bool have_q_pseudos = false;	/* Are we synthesizing the quad precision
				   Q (NEON or MVE) registers?  Requires
				   have_s_pseudos.  */
  int q_pseudo_base = 0;	/* Register number for the first quad
				   precision pseudo register.  */
  int q_pseudo_count = 0;	/* Number of quad precision pseudo
				   registers.  */
  bool have_neon = false;	/* Do we have a NEON unit?  */

  bool have_mve = false;	/* Do we have a MVE extension?  */
  int mve_vpr_regnum = 0;	/* MVE VPR register number.  */
  int mve_pseudo_base = 0;	/* Number of the first MVE pseudo register.  */
  int mve_pseudo_count = 0;	/* Total number of MVE pseudo registers.  */

  bool have_pacbti = false;	/* True if we have the ARMv8.1-m PACBTI
				   extensions.  */
  int pacbti_pseudo_base = 0;	/* Number of the first PACBTI pseudo
				   register.  */
  int pacbti_pseudo_count = 0;	/* Total number of PACBTI pseudo registers.  */

  int m_profile_msp_regnum = ARM_SP_REGNUM;	/* M-profile MSP register number.  */
  int m_profile_psp_regnum = ARM_SP_REGNUM;	/* M-profile PSP register number.  */

  /* Secure and Non-secure stack pointers with security extension.  */
  int m_profile_msp_ns_regnum = ARM_SP_REGNUM;	/* M-profile MSP_NS register number.  */
  int m_profile_psp_ns_regnum = ARM_SP_REGNUM;	/* M-profile PSP_NS register number.  */
  int m_profile_msp_s_regnum = ARM_SP_REGNUM;	/* M-profile MSP_S register number.  */
  int m_profile_psp_s_regnum = ARM_SP_REGNUM;	/* M-profile PSP_S register number.  */

  int tls_regnum = 0;		/* Number of the tpidruro register.  */

  bool is_m = false;		/* Does the target follow the "M" profile.  */
  bool have_sec_ext = false;	/* Do we have security extensions?  */
  CORE_ADDR lowest_pc = 0;	/* Lowest address at which instructions
				   will appear.  */

  const gdb_byte *arm_breakpoint = nullptr;	/* Breakpoint pattern for an ARM insn.  */
  int arm_breakpoint_size = 0;	/* And its size.  */
  const gdb_byte *thumb_breakpoint = nullptr;	/* Breakpoint pattern for a Thumb insn.  */
  int thumb_breakpoint_size = 0;	/* And its size.  */

  /* If the Thumb breakpoint is an undefined instruction (which is
     affected by IT blocks) rather than a BKPT instruction (which is
     not), then we need a 32-bit Thumb breakpoint to preserve the
     instruction count in IT blocks.  */
  const gdb_byte *thumb2_breakpoint = nullptr;
  int thumb2_breakpoint_size = 0;

  int jb_pc = 0;			/* Offset to PC value in jump buffer.
				   If this is negative, longjmp support
				   will be disabled.  */
  size_t jb_elt_size = 0;		/* And the size of each entry in the buf.  */

  /* Convention for returning structures.  */
  enum struct_return struct_return {};

  /* ISA-specific data types.  */
  struct type *arm_ext_type = nullptr;
  struct type *neon_double_type = nullptr;
  struct type *neon_quad_type = nullptr;

   /* syscall record.  */
  int (*arm_syscall_record) (struct regcache *regcache,
			     unsigned long svc_number) = nullptr;
};

/* Structures used for displaced stepping.  */

/* The maximum number of temporaries available for displaced instructions.  */
#define DISPLACED_TEMPS			16
/* The maximum number of modified instructions generated for one single-stepped
   instruction, including the breakpoint (usually at the end of the instruction
   sequence) and any scratch words, etc.  */
#define ARM_DISPLACED_MODIFIED_INSNS	8

struct arm_displaced_step_copy_insn_closure
  : public displaced_step_copy_insn_closure
{
  ULONGEST tmp[DISPLACED_TEMPS];
  int rd;
  int wrote_to_pc;
  union
  {
    struct
    {
      int xfersize;
      int rn;			   /* Writeback register.  */
      unsigned int immed : 1;      /* Offset is immediate.  */
      unsigned int writeback : 1;  /* Perform base-register writeback.  */
      unsigned int restore_r4 : 1; /* Used r4 as scratch.  */
    } ldst;

    struct
    {
      unsigned long dest;
      unsigned int link : 1;
      unsigned int exchange : 1;
      unsigned int cond : 4;
    } branch;

    struct
    {
      unsigned int regmask;
      int rn;
      CORE_ADDR xfer_addr;
      unsigned int load : 1;
      unsigned int user : 1;
      unsigned int increment : 1;
      unsigned int before : 1;
      unsigned int writeback : 1;
      unsigned int cond : 4;
    } block;

    struct
    {
      unsigned int immed : 1;
    } preload;

    struct
    {
      /* If non-NULL, override generic SVC handling (e.g. for a particular
	 OS).  */
      int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs,
			  arm_displaced_step_copy_insn_closure *dsc);
    } svc;
  } u;

  /* The size of original instruction, 2 or 4.  */
  unsigned int insn_size;
  /* True if the original insn (and thus all replacement insns) are Thumb
     instead of ARM.   */
  unsigned int is_thumb;

  /* The slots in the array is used in this way below,
     - ARM instruction occupies one slot,
     - Thumb 16 bit instruction occupies one slot,
     - Thumb 32-bit instruction occupies *two* slots, one part for each.  */
  unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
  int numinsns;
  CORE_ADDR insn_addr;
  CORE_ADDR scratch_base;
  void (*cleanup) (struct gdbarch *, struct regcache *,
		   arm_displaced_step_copy_insn_closure *);
};

/* Values for the WRITE_PC argument to displaced_write_reg.  If the register
   write may write to the PC, specifies the way the CPSR T bit, etc. is
   modified by the instruction.  */

enum pc_write_style
{
  BRANCH_WRITE_PC,
  BX_WRITE_PC,
  LOAD_WRITE_PC,
  ALU_WRITE_PC,
  CANNOT_WRITE_PC
};

extern void
  arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to, struct regcache *regs,
			      arm_displaced_step_copy_insn_closure *dsc);
extern void
  arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
			      CORE_ADDR to,
			      arm_displaced_step_copy_insn_closure *dsc);
extern ULONGEST
  displaced_read_reg (regcache *regs, arm_displaced_step_copy_insn_closure *dsc,
		      int regno);
extern void
  displaced_write_reg (struct regcache *regs,
		       arm_displaced_step_copy_insn_closure *dsc, int regno,
		       ULONGEST val, enum pc_write_style write_pc);

CORE_ADDR arm_skip_stub (frame_info_ptr, CORE_ADDR);

ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
							int len,
							int byte_order);

CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
					     CORE_ADDR val);

int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);

std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
int arm_is_thumb (struct regcache *regcache);
int arm_frame_is_thumb (frame_info_ptr frame);

extern void arm_displaced_step_fixup (struct gdbarch *,
				      displaced_step_copy_insn_closure *,
				      CORE_ADDR, CORE_ADDR,
				      struct regcache *, bool);

/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode.  */
extern int arm_psr_thumb_bit (struct gdbarch *);

/* Is the instruction at the given memory address a Thumb or ARM
   instruction?  */
extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);

extern int arm_process_record (struct gdbarch *gdbarch, 
			       struct regcache *regcache, CORE_ADDR addr);
/* Functions exported from arm-bsd-tdep.h.  */

/* Return the appropriate register set for the core section identified
   by SECT_NAME and SECT_SIZE.  */

extern void
  armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
				       iterate_over_regset_sections_cb *cb,
				       void *cb_data,
				       const struct regcache *regcache);

/* Get the correct Arm target description with given FP hardware type.  */
const target_desc *arm_read_description (arm_fp_type fp_type, bool tls);

/* Get the correct Arm M-Profile target description with given hardware
   type.  */
const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);

#endif /* arm-tdep.h */
Commit	Line	Data
34e8f22d	1	/* Common target dependent code for GDB on ARM systems.
213516ef	2	Copyright (C) 2002-2023 Free Software Foundation, Inc.
34e8f22d RE	3
	4	This file is part of GDB.
	5
	6	This program is free software; you can redistribute it and/or modify
	7	it under the terms of the GNU General Public License as published by
a9762ec7	8	the Free Software Foundation; either version 3 of the License, or
34e8f22d RE	9	(at your option) any later version.
	10
	11	This program is distributed in the hope that it will be useful,
	12	but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	GNU General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
a9762ec7	17	along with this program. If not, see <http://www.gnu.org/licenses/>. */
34e8f22d	18
47ccd048 MK	19	#ifndef ARM_TDEP_H
	20	#define ARM_TDEP_H
	21
cb587d83 DJ	22	/* Forward declarations. */
cb587d83 DJ	23	struct regset;
3352110b	24	struct address_space;
d9311bfa AT	25	struct get_next_pcs;
	26	struct arm_get_next_pcs;
	27	struct gdb_get_next_pcs;
cb587d83	28
c7ae7675 CB	29	/* Set to true if the 32-bit mode is in use. */
	30
	31	extern bool arm_apcs_32;
	32
0d12e84c	33	#include "gdbarch.h"
ec741292	34	#include "arch/arm.h"
cfba9872	35	#include "infrun.h"
34e8f22d	36
a0ff9e1a SM	37	#include <vector>
a0ff9e1a SM	38
34e8f22d	39	/* Number of machine registers. The only define actually required
f57d151a	40	is gdbarch_num_regs. The other definitions are used for documentation
34e8f22d RE	41	purposes and code readability. */
	42	/* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS)
	43	(and called PS for processor status) so the status bits can be cleared
	44	from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed
	45	in PS. */
	46	#define NUM_FREGS 8 /* Number of floating point registers. */
	47	#define NUM_SREGS 2 /* Number of status registers. */
	48	#define NUM_GREGS 16 /* Number of general purpose registers. */
	49
	50
9779414d	51
08216dd7 RE	52	/* Type of floating-point code in use by inferior. There are really 3 models
	53	that are traditionally supported (plus the endianness issue), but gcc can
	54	only generate 2 of those. The third is APCS_FLOAT, where arguments to
	55	functions are passed in floating-point registers.
	56
fd50bc42 RE	57	In addition to the traditional models, VFP adds two more.
	58
	59	If you update this enum, don't forget to update fp_model_strings in
	60	arm-tdep.c. */
08216dd7 RE	61
	62	enum arm_float_model
	63	{
fd50bc42 RE	64	ARM_FLOAT_AUTO, /* Automatic detection. Do not set in tdep. */
	65	ARM_FLOAT_SOFT_FPA, /* Traditional soft-float (mixed-endian on LE ARM). */
	66	ARM_FLOAT_FPA, /* FPA co-processor. GCC calling convention. */
	67	ARM_FLOAT_SOFT_VFP, /* Soft-float with pure-endian doubles. */
	68	ARM_FLOAT_VFP, /* Full VFP calling convention. */
	69	ARM_FLOAT_LAST /* Keep at end. */
08216dd7 RE	70	};
08216dd7 RE	71
28e97307 DJ	72	/* ABI used by the inferior. */
	73	enum arm_abi_kind
	74	{
	75	ARM_ABI_AUTO,
	76	ARM_ABI_APCS,
	77	ARM_ABI_AAPCS,
	78	ARM_ABI_LAST
	79	};
fd50bc42	80
7c00367c MK	81	/* Convention for returning structures. */
	82
	83	enum struct_return
	84	{
	85	pcc_struct_return, /* Return "short" structures in memory. */
	86	reg_struct_return /* Return "short" structures in registers. */
	87	};
	88
97e03143	89	/* Target-dependent structure in gdbarch. */
ab25d9bb	90	struct arm_gdbarch_tdep : gdbarch_tdep_base
97e03143	91	{
28e97307 DJ	92	/* The ABI for this architecture. It should never be set to
28e97307 DJ	93	ARM_ABI_AUTO. */
345bd07c	94	enum arm_abi_kind arm_abi {};
28e97307	95
345bd07c	96	enum arm_float_model fp_model {}; /* Floating point calling conventions. */
08216dd7	97
345bd07c SM	98	bool have_fpa_registers = false; /* Does the target report the FPA registers? */
345bd07c SM	99	bool have_wmmx_registers = false; /* Does the target report the WMMX registers? */
330c6ca9 YQ	100	/* The number of VFP registers reported by the target. It is zero
330c6ca9 YQ	101	if VFP registers are not supported. */
345bd07c SM	102	int vfp_register_count = 0;
345bd07c SM	103	bool have_s_pseudos = false; /* Are we synthesizing the single precision
58d6951d	104	VFP registers? */
345bd07c	105	int s_pseudo_base = 0; /* Register number for the first S pseudo
ecbf5d4f	106	register. */
345bd07c SM	107	int s_pseudo_count = 0; /* Number of S pseudo registers. */
345bd07c SM	108	bool have_q_pseudos = false; /* Are we synthesizing the quad precision
ecbf5d4f LM	109	Q (NEON or MVE) registers? Requires
ecbf5d4f LM	110	have_s_pseudos. */
345bd07c	111	int q_pseudo_base = 0; /* Register number for the first quad
ecbf5d4f	112	precision pseudo register. */
345bd07c	113	int q_pseudo_count = 0; /* Number of quad precision pseudo
ecbf5d4f	114	registers. */
345bd07c	115	bool have_neon = false; /* Do we have a NEON unit? */
ff6f572f	116
345bd07c SM	117	bool have_mve = false; /* Do we have a MVE extension? */
	118	int mve_vpr_regnum = 0; /* MVE VPR register number. */
	119	int mve_pseudo_base = 0; /* Number of the first MVE pseudo register. */
	120	int mve_pseudo_count = 0; /* Total number of MVE pseudo registers. */
ae66a8f1	121
a01567f4 LM	122	bool have_pacbti = false; /* True if we have the ARMv8.1-m PACBTI
	123	extensions. */
	124	int pacbti_pseudo_base = 0; /* Number of the first PACBTI pseudo
	125	register. */
	126	int pacbti_pseudo_count = 0; /* Total number of PACBTI pseudo registers. */
	127
ae7e2f45 CL	128	int m_profile_msp_regnum = ARM_SP_REGNUM; /* M-profile MSP register number. */
	129	int m_profile_psp_regnum = ARM_SP_REGNUM; /* M-profile PSP register number. */
	130
	131	/* Secure and Non-secure stack pointers with security extension. */
	132	int m_profile_msp_ns_regnum = ARM_SP_REGNUM; /* M-profile MSP_NS register number. */
	133	int m_profile_psp_ns_regnum = ARM_SP_REGNUM; /* M-profile PSP_NS register number. */
	134	int m_profile_msp_s_regnum = ARM_SP_REGNUM; /* M-profile MSP_S register number. */
	135	int m_profile_psp_s_regnum = ARM_SP_REGNUM; /* M-profile PSP_S register number. */
9074667a	136
92d48a1e JB	137	int tls_regnum = 0; /* Number of the tpidruro register. */
92d48a1e JB	138
345bd07c	139	bool is_m = false; /* Does the target follow the "M" profile. */
ae7e2f45	140	bool have_sec_ext = false; /* Do we have security extensions? */
345bd07c	141	CORE_ADDR lowest_pc = 0; /* Lowest address at which instructions
97e03143	142	will appear. */
9df628e0	143
345bd07c SM	144	const gdb_byte arm_breakpoint = nullptr; / Breakpoint pattern for an ARM insn. */
	145	int arm_breakpoint_size = 0; /* And its size. */
	146	const gdb_byte thumb_breakpoint = nullptr; / Breakpoint pattern for a Thumb insn. */
	147	int thumb_breakpoint_size = 0; /* And its size. */
9df628e0	148
177321bd DJ	149	/* If the Thumb breakpoint is an undefined instruction (which is
	150	affected by IT blocks) rather than a BKPT instruction (which is
	151	not), then we need a 32-bit Thumb breakpoint to preserve the
	152	instruction count in IT blocks. */
345bd07c SM	153	const gdb_byte *thumb2_breakpoint = nullptr;
345bd07c SM	154	int thumb2_breakpoint_size = 0;
177321bd	155
345bd07c	156	int jb_pc = 0; /* Offset to PC value in jump buffer.
9df628e0 RE	157	If this is negative, longjmp support
9df628e0 RE	158	will be disabled. */
345bd07c	159	size_t jb_elt_size = 0; /* And the size of each entry in the buf. */
cb587d83	160
7c00367c	161	/* Convention for returning structures. */
345bd07c	162	enum struct_return struct_return {};
7c00367c	163
27067745	164	/* ISA-specific data types. */
345bd07c SM	165	struct type *arm_ext_type = nullptr;
	166	struct type *neon_double_type = nullptr;
	167	struct type *neon_quad_type = nullptr;
25b41d01	168
97dfe206	169	/* syscall record. */
345bd07c SM	170	int (arm_syscall_record) (struct regcache regcache,
345bd07c SM	171	unsigned long svc_number) = nullptr;
97e03143 RE	172	};
97e03143 RE	173
cca44b1b JB	174	/* Structures used for displaced stepping. */
	175
	176	/* The maximum number of temporaries available for displaced instructions. */
	177	#define DISPLACED_TEMPS 16
	178	/* The maximum number of modified instructions generated for one single-stepped
	179	instruction, including the breakpoint (usually at the end of the instruction
	180	sequence) and any scratch words, etc. */
e935475c	181	#define ARM_DISPLACED_MODIFIED_INSNS 8
cca44b1b	182
1152d984 SM	183	struct arm_displaced_step_copy_insn_closure
1152d984 SM	184	: public displaced_step_copy_insn_closure
cca44b1b JB	185	{
	186	ULONGEST tmp[DISPLACED_TEMPS];
	187	int rd;
	188	int wrote_to_pc;
	189	union
	190	{
	191	struct
	192	{
	193	int xfersize;
	194	int rn; /* Writeback register. */
	195	unsigned int immed : 1; /* Offset is immediate. */
	196	unsigned int writeback : 1; /* Perform base-register writeback. */
	197	unsigned int restore_r4 : 1; /* Used r4 as scratch. */
	198	} ldst;
	199
	200	struct
	201	{
	202	unsigned long dest;
	203	unsigned int link : 1;
	204	unsigned int exchange : 1;
	205	unsigned int cond : 4;
	206	} branch;
	207
	208	struct
	209	{
	210	unsigned int regmask;
	211	int rn;
	212	CORE_ADDR xfer_addr;
	213	unsigned int load : 1;
	214	unsigned int user : 1;
	215	unsigned int increment : 1;
	216	unsigned int before : 1;
	217	unsigned int writeback : 1;
	218	unsigned int cond : 4;
	219	} block;
	220
	221	struct
	222	{
	223	unsigned int immed : 1;
	224	} preload;
	225
	226	struct
	227	{
	228	/* If non-NULL, override generic SVC handling (e.g. for a particular
dda83cd7	229	OS). */
bd18283a	230	int (copy_svc_os) (struct gdbarch gdbarch, struct regcache *regs,
1152d984	231	arm_displaced_step_copy_insn_closure *dsc);
cca44b1b JB	232	} svc;
cca44b1b JB	233	} u;
4db71c0b YQ	234
	235	/* The size of original instruction, 2 or 4. */
	236	unsigned int insn_size;
	237	/* True if the original insn (and thus all replacement insns) are Thumb
	238	instead of ARM. */
	239	unsigned int is_thumb;
	240
	241	/* The slots in the array is used in this way below,
	242	- ARM instruction occupies one slot,
	243	- Thumb 16 bit instruction occupies one slot,
	244	- Thumb 32-bit instruction occupies two slots, one part for each. */
e935475c	245	unsigned long modinsn[ARM_DISPLACED_MODIFIED_INSNS];
cca44b1b JB	246	int numinsns;
	247	CORE_ADDR insn_addr;
	248	CORE_ADDR scratch_base;
	249	void (cleanup) (struct gdbarch , struct regcache *,
1152d984	250	arm_displaced_step_copy_insn_closure *);
cca44b1b JB	251	};
	252
	253	/* Values for the WRITE_PC argument to displaced_write_reg. If the register
	254	write may write to the PC, specifies the way the CPSR T bit, etc. is
	255	modified by the instruction. */
	256
	257	enum pc_write_style
	258	{
	259	BRANCH_WRITE_PC,
	260	BX_WRITE_PC,
	261	LOAD_WRITE_PC,
	262	ALU_WRITE_PC,
	263	CANNOT_WRITE_PC
	264	};
	265
	266	extern void
b434a28f YQ	267	arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from,
b434a28f YQ	268	CORE_ADDR to, struct regcache *regs,
1152d984	269	arm_displaced_step_copy_insn_closure *dsc);
cca44b1b JB	270	extern void
cca44b1b JB	271	arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from,
1152d984 SM	272	CORE_ADDR to,
1152d984 SM	273	arm_displaced_step_copy_insn_closure *dsc);
cca44b1b	274	extern ULONGEST
1152d984	275	displaced_read_reg (regcache regs, arm_displaced_step_copy_insn_closure dsc,
36073a92	276	int regno);
cca44b1b JB	277	extern void
cca44b1b JB	278	displaced_write_reg (struct regcache *regs,
1152d984	279	arm_displaced_step_copy_insn_closure *dsc, int regno,
cca44b1b	280	ULONGEST val, enum pc_write_style write_pc);
7c00367c	281
9efe17a3	282	CORE_ADDR arm_skip_stub (frame_info_ptr, CORE_ADDR);
d9311bfa AT	283
	284	ULONGEST arm_get_next_pcs_read_memory_unsigned_integer (CORE_ADDR memaddr,
	285	int len,
	286	int byte_order);
	287
	288	CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
	289	CORE_ADDR val);
	290
d9311bfa AT	291	int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
d9311bfa AT	292
a0ff9e1a	293	std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
d0e59a68	294	int arm_is_thumb (struct regcache *regcache);
bd2b40ac	295	int arm_frame_is_thumb (frame_info_ptr frame);
190dce09	296
cca44b1b	297	extern void arm_displaced_step_fixup (struct gdbarch *,
1152d984	298	displaced_step_copy_insn_closure *,
cf141dd8 AB	299	CORE_ADDR, CORE_ADDR,
cf141dd8 AB	300	struct regcache *, bool);
cca44b1b	301
478fd957 UW	302	/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */
	303	extern int arm_psr_thumb_bit (struct gdbarch *);
	304
e3039479 UW	305	/* Is the instruction at the given memory address a Thumb or ARM
	306	instruction? */
	307	extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR);
	308
72508ac0	309	extern int arm_process_record (struct gdbarch *gdbarch,
dda83cd7	310	struct regcache *regcache, CORE_ADDR addr);
03b62bbb	311	/* Functions exported from arm-bsd-tdep.h. */
47ccd048 MK	312
	313	/* Return the appropriate register set for the core section identified
	314	by SECT_NAME and SECT_SIZE. */
	315
ed09174e AA	316	extern void
	317	armbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
	318	iterate_over_regset_sections_cb *cb,
	319	void *cb_data,
	320	const struct regcache *regcache);
47ccd048	321
d105cce5	322	/* Get the correct Arm target description with given FP hardware type. */
92d48a1e	323	const target_desc *arm_read_description (arm_fp_type fp_type, bool tls);
d105cce5 AH	324
	325	/* Get the correct Arm M-Profile target description with given hardware
	326	type. */
	327	const target_desc *arm_read_mprofile_description (arm_m_profile_type m_type);
ef7e8358	328
47ccd048	329	#endif /* arm-tdep.h */