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ed9a39eb | 1 | /* Definitions to target GDB to ARM targets. |
dfcd3bfb | 2 | Copyright 1986, 1987, 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. |
c906108c | 3 | |
c5aa993b | 4 | This file is part of GDB. |
c906108c | 5 | |
c5aa993b JM |
6 | This program is free software; you can redistribute it and/or modify |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
c906108c | 10 | |
c5aa993b JM |
11 | This program is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
c906108c | 15 | |
c5aa993b JM |
16 | You should have received a copy of the GNU General Public License |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 59 Temple Place - Suite 330, | |
19 | Boston, MA 02111-1307, USA. */ | |
c906108c | 20 | |
ed9a39eb JM |
21 | #ifndef TM_ARM_H |
22 | #define TM_ARM_H | |
23 | ||
24 | /* Forward declarations for prototypes. */ | |
c906108c SS |
25 | struct type; |
26 | struct value; | |
c906108c SS |
27 | |
28 | #define TARGET_BYTE_ORDER_SELECTABLE | |
29 | ||
ed9a39eb JM |
30 | /* Target byte order on ARM defaults to selectable, and defaults to |
31 | little endian. */ | |
32 | #define TARGET_BYTE_ORDER_SELECTABLE_P 1 | |
33 | #define TARGET_BYTE_ORDER_DEFAULT LITTLE_ENDIAN | |
c906108c | 34 | |
ed9a39eb | 35 | /* IEEE format floating point. */ |
c906108c | 36 | #define IEEE_FLOAT |
ed9a39eb JM |
37 | #define TARGET_DOUBLE_FORMAT (target_byte_order == BIG_ENDIAN \ |
38 | ? &floatformat_ieee_double_big \ | |
39 | : &floatformat_ieee_double_littlebyte_bigword) | |
c906108c | 40 | |
ed9a39eb JM |
41 | /* When reading symbols, we need to zap the low bit of the address, |
42 | which may be set to 1 for Thumb functions. */ | |
c906108c SS |
43 | |
44 | #define SMASH_TEXT_ADDRESS(addr) ((addr) &= ~0x1) | |
45 | ||
46 | /* Remove useless bits from addresses in a running program. */ | |
47 | ||
ed9a39eb | 48 | CORE_ADDR arm_addr_bits_remove (CORE_ADDR); |
c906108c | 49 | |
ed9a39eb | 50 | #define ADDR_BITS_REMOVE(val) (arm_addr_bits_remove (val)) |
c906108c | 51 | |
ed9a39eb JM |
52 | /* Offset from address of function to start of its code. Zero on most |
53 | machines. */ | |
c906108c | 54 | |
ed9a39eb | 55 | #define FUNCTION_START_OFFSET 0 |
c906108c | 56 | |
ed9a39eb JM |
57 | /* Advance PC across any function entry prologue instructions to reach |
58 | some "real" code. */ | |
c906108c | 59 | |
ed9a39eb | 60 | extern CORE_ADDR arm_skip_prologue (CORE_ADDR pc); |
c906108c | 61 | |
ed9a39eb | 62 | #define SKIP_PROLOGUE(pc) (arm_skip_prologue (pc)) |
c906108c | 63 | |
ed9a39eb JM |
64 | /* Immediately after a function call, return the saved pc. Can't |
65 | always go through the frames for this because on some machines the | |
66 | new frame is not set up until the new function executes some | |
67 | instructions. */ | |
c906108c | 68 | |
ed9a39eb | 69 | #define SAVED_PC_AFTER_CALL(frame) arm_saved_pc_after_call (frame) |
c906108c | 70 | struct frame_info; |
ed9a39eb JM |
71 | extern CORE_ADDR arm_saved_pc_after_call (struct frame_info *); |
72 | ||
73 | /* The following define instruction sequences that will cause ARM | |
74 | cpu's to take an undefined instruction trap. These are used to | |
75 | signal a breakpoint to GDB. | |
76 | ||
77 | The newer ARMv4T cpu's are capable of operating in ARM or Thumb | |
78 | modes. A different instruction is required for each mode. The ARM | |
79 | cpu's can also be big or little endian. Thus four different | |
80 | instructions are needed to support all cases. | |
81 | ||
82 | Note: ARMv4 defines several new instructions that will take the | |
83 | undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does | |
84 | not in fact add the new instructions. The new undefined | |
85 | instructions in ARMv4 are all instructions that had no defined | |
86 | behaviour in earlier chips. There is no guarantee that they will | |
87 | raise an exception, but may be treated as NOP's. In practice, it | |
88 | may only safe to rely on instructions matching: | |
89 | ||
90 | 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 | |
91 | 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 | |
92 | C C C C 0 1 1 x x x x x x x x x x x x x x x x x x x x 1 x x x x | |
93 | ||
94 | Even this may only true if the condition predicate is true. The | |
95 | following use a condition predicate of ALWAYS so it is always TRUE. | |
96 | ||
97 | There are other ways of forcing a breakpoint. ARM Linux, RisciX, | |
98 | and I suspect NetBSD will all use a software interrupt rather than | |
99 | an undefined instruction to force a trap. This can be handled by | |
100 | redefining some or all of the following in a target dependent | |
101 | fashion. */ | |
102 | ||
103 | #define ARM_LE_BREAKPOINT {0xFE,0xDE,0xFF,0xE7} | |
104 | #define ARM_BE_BREAKPOINT {0xE7,0xFF,0xDE,0xFE} | |
105 | #define THUMB_LE_BREAKPOINT {0xfe,0xdf} | |
106 | #define THUMB_BE_BREAKPOINT {0xdf,0xfe} | |
c906108c SS |
107 | |
108 | /* Stack grows downward. */ | |
109 | ||
110 | #define INNER_THAN(lhs,rhs) ((lhs) < (rhs)) | |
111 | ||
ed9a39eb JM |
112 | /* !!!! if we're using RDP, then we're inserting breakpoints and |
113 | storing their handles instread of what was in memory. It is nice | |
114 | that this is the same size as a handle - otherwise remote-rdp will | |
c906108c SS |
115 | have to change. */ |
116 | ||
ed9a39eb JM |
117 | /* BREAKPOINT_FROM_PC uses the program counter value to determine |
118 | whether a 16- or 32-bit breakpoint should be used. It returns a | |
119 | pointer to a string of bytes that encode a breakpoint instruction, | |
120 | stores the length of the string to *lenptr, and adjusts the pc (if | |
121 | necessary) to point to the actual memory location where the | |
122 | breakpoint should be inserted. */ | |
c906108c SS |
123 | |
124 | extern breakpoint_from_pc_fn arm_breakpoint_from_pc; | |
125 | #define BREAKPOINT_FROM_PC(pcptr, lenptr) arm_breakpoint_from_pc (pcptr, lenptr) | |
126 | ||
ed9a39eb JM |
127 | /* Amount PC must be decremented by after a breakpoint. This is often |
128 | the number of bytes in BREAKPOINT but not always. */ | |
c906108c SS |
129 | |
130 | #define DECR_PC_AFTER_BREAK 0 | |
131 | ||
ed9a39eb JM |
132 | /* Code to execute to print interesting information about the floating |
133 | point processor (if any) or emulator. No need to define if there | |
134 | is nothing to do. */ | |
104c1213 JM |
135 | extern void arm_float_info (void); |
136 | ||
ed9a39eb | 137 | #define FLOAT_INFO { arm_float_info (); } |
c906108c SS |
138 | |
139 | /* Say how long (ordinary) registers are. This is a piece of bogosity | |
140 | used in push_word and a few other places; REGISTER_RAW_SIZE is the | |
141 | real way to know how big a register is. */ | |
142 | ||
ed9a39eb JM |
143 | #define REGISTER_SIZE 4 |
144 | ||
145 | /* Say how long FP registers are. Used for documentation purposes and | |
146 | code readability in this header. IEEE extended doubles are 80 | |
147 | bits. DWORD aligned they use 96 bits. */ | |
148 | #define FP_REGISTER_RAW_SIZE 12 | |
149 | ||
150 | /* GCC doesn't support long doubles (extended IEEE values). The FP | |
151 | register virtual size is therefore 64 bits. Used for documentation | |
152 | purposes and code readability in this header. */ | |
153 | #define FP_REGISTER_VIRTUAL_SIZE 8 | |
154 | ||
155 | /* Status registers are the same size as general purpose registers. | |
156 | Used for documentation purposes and code readability in this | |
157 | header. */ | |
158 | #define STATUS_REGISTER_SIZE REGISTER_SIZE | |
159 | ||
160 | /* Number of machine registers. The only define actually required | |
161 | is NUM_REGS. The other definitions are used for documentation | |
162 | purposes and code readability. */ | |
163 | /* For 26 bit ARM code, a fake copy of the PC is placed in register 25 (PS) | |
164 | (and called PS for processor status) so the status bits can be cleared | |
165 | from the PC (register 15). For 32 bit ARM code, a copy of CPSR is placed | |
166 | in PS. */ | |
167 | #define NUM_FREGS 8 /* Number of floating point registers. */ | |
168 | #define NUM_SREGS 2 /* Number of status registers. */ | |
169 | #define NUM_GREGS 16 /* Number of general purpose registers. */ | |
170 | #define NUM_REGS (NUM_GREGS + NUM_FREGS + NUM_SREGS) | |
c906108c SS |
171 | |
172 | /* An array of names of registers. */ | |
c906108c | 173 | extern char **arm_register_names; |
ed9a39eb | 174 | |
c906108c SS |
175 | #define REGISTER_NAME(i) arm_register_names[i] |
176 | ||
ed9a39eb JM |
177 | /* Register numbers of various important registers. Note that some of |
178 | these values are "real" register numbers, and correspond to the | |
179 | general registers of the machine, and some are "phony" register | |
180 | numbers which are too large to be actual register numbers as far as | |
181 | the user is concerned but do serve to get the desired values when | |
182 | passed to read_register. */ | |
c906108c SS |
183 | |
184 | #define A1_REGNUM 0 /* first integer-like argument */ | |
185 | #define A4_REGNUM 3 /* last integer-like argument */ | |
186 | #define AP_REGNUM 11 | |
187 | #define FP_REGNUM 11 /* Contains address of executing stack frame */ | |
188 | #define SP_REGNUM 13 /* Contains address of top of stack */ | |
189 | #define LR_REGNUM 14 /* address to return to from a function call */ | |
190 | #define PC_REGNUM 15 /* Contains program counter */ | |
191 | #define F0_REGNUM 16 /* first floating point register */ | |
192 | #define F3_REGNUM 19 /* last floating point argument register */ | |
193 | #define F7_REGNUM 23 /* last floating point register */ | |
194 | #define FPS_REGNUM 24 /* floating point status register */ | |
195 | #define PS_REGNUM 25 /* Contains processor status */ | |
196 | ||
197 | #define THUMB_FP_REGNUM 7 /* R7 is frame register on Thumb */ | |
198 | ||
199 | #define ARM_NUM_ARG_REGS 4 | |
200 | #define ARM_LAST_ARG_REGNUM A4_REGNUM | |
201 | #define ARM_NUM_FP_ARG_REGS 4 | |
202 | #define ARM_LAST_FP_ARG_REGNUM F3_REGNUM | |
203 | ||
204 | /* Instruction condition field values. */ | |
205 | #define INST_EQ 0x0 | |
206 | #define INST_NE 0x1 | |
207 | #define INST_CS 0x2 | |
208 | #define INST_CC 0x3 | |
209 | #define INST_MI 0x4 | |
210 | #define INST_PL 0x5 | |
211 | #define INST_VS 0x6 | |
212 | #define INST_VC 0x7 | |
213 | #define INST_HI 0x8 | |
214 | #define INST_LS 0x9 | |
215 | #define INST_GE 0xa | |
216 | #define INST_LT 0xb | |
217 | #define INST_GT 0xc | |
218 | #define INST_LE 0xd | |
219 | #define INST_AL 0xe | |
220 | #define INST_NV 0xf | |
221 | ||
222 | #define FLAG_N 0x80000000 | |
223 | #define FLAG_Z 0x40000000 | |
224 | #define FLAG_C 0x20000000 | |
225 | #define FLAG_V 0x10000000 | |
226 | ||
227 | ||
228 | ||
229 | /* Total amount of space needed to store our copies of the machine's | |
230 | register state, the array `registers'. */ | |
ed9a39eb JM |
231 | |
232 | #define REGISTER_BYTES ((NUM_GREGS * REGISTER_SIZE) + \ | |
233 | (NUM_FREGS * FP_REGISTER_RAW_SIZE) + \ | |
234 | (NUM_SREGS * STATUS_REGISTER_SIZE)) | |
c906108c SS |
235 | |
236 | /* Index within `registers' of the first byte of the space for | |
237 | register N. */ | |
238 | ||
ed9a39eb JM |
239 | #define REGISTER_BYTE(N) \ |
240 | ((N) < F0_REGNUM \ | |
241 | ? (N) * REGISTER_SIZE \ | |
242 | : ((N) < PS_REGNUM \ | |
243 | ? (NUM_GREGS * REGISTER_SIZE + \ | |
244 | ((N) - F0_REGNUM) * FP_REGISTER_RAW_SIZE) \ | |
245 | : (NUM_GREGS * REGISTER_SIZE + \ | |
246 | NUM_FREGS * FP_REGISTER_RAW_SIZE + \ | |
247 | ((N) - FPS_REGNUM) * STATUS_REGISTER_SIZE))) | |
248 | ||
249 | /* Number of bytes of storage in the actual machine representation for | |
250 | register N. All registers are 4 bytes, except fp0 - fp7, which are | |
251 | 12 bytes in length. */ | |
252 | #define REGISTER_RAW_SIZE(N) \ | |
253 | ((N) < F0_REGNUM ? REGISTER_SIZE : \ | |
254 | (N) < FPS_REGNUM ? FP_REGISTER_RAW_SIZE : STATUS_REGISTER_SIZE) | |
255 | ||
256 | /* Number of bytes of storage in a program's representation | |
257 | for register N. */ | |
258 | #define REGISTER_VIRTUAL_SIZE(N) \ | |
259 | ((N) < F0_REGNUM ? REGISTER_SIZE : \ | |
260 | (N) < FPS_REGNUM ? FP_REGISTER_VIRTUAL_SIZE : STATUS_REGISTER_SIZE) | |
c906108c SS |
261 | |
262 | /* Largest value REGISTER_RAW_SIZE can have. */ | |
263 | ||
ed9a39eb | 264 | #define MAX_REGISTER_RAW_SIZE FP_REGISTER_RAW_SIZE |
c906108c SS |
265 | |
266 | /* Largest value REGISTER_VIRTUAL_SIZE can have. */ | |
ed9a39eb | 267 | #define MAX_REGISTER_VIRTUAL_SIZE FP_REGISTER_VIRTUAL_SIZE |
c906108c | 268 | |
ed9a39eb JM |
269 | /* Nonzero if register N requires conversion from raw format to |
270 | virtual format. */ | |
271 | extern int arm_register_convertible (unsigned int); | |
272 | #define REGISTER_CONVERTIBLE(REGNUM) (arm_register_convertible (REGNUM)) | |
c906108c | 273 | |
ed9a39eb JM |
274 | /* Convert data from raw format for register REGNUM in buffer FROM to |
275 | virtual format with type TYPE in buffer TO. */ | |
104c1213 | 276 | |
ed9a39eb JM |
277 | extern void arm_register_convert_to_virtual (unsigned int regnum, |
278 | struct type *type, | |
279 | void *from, void *to); | |
c906108c | 280 | #define REGISTER_CONVERT_TO_VIRTUAL(REGNUM,TYPE,FROM,TO) \ |
ed9a39eb | 281 | arm_register_convert_to_virtual (REGNUM, TYPE, FROM, TO) |
c906108c | 282 | |
ed9a39eb JM |
283 | /* Convert data from virtual format with type TYPE in buffer FROM to |
284 | raw format for register REGNUM in buffer TO. */ | |
c906108c | 285 | |
ed9a39eb JM |
286 | extern void arm_register_convert_to_raw (unsigned int regnum, |
287 | struct type *type, | |
288 | void *from, void *to); | |
289 | #define REGISTER_CONVERT_TO_RAW(TYPE,REGNUM,FROM,TO) \ | |
290 | arm_register_convert_to_raw (REGNUM, TYPE, FROM, TO) | |
104c1213 | 291 | |
ed9a39eb JM |
292 | /* Return the GDB type object for the "standard" data type of data in |
293 | register N. */ | |
c906108c SS |
294 | |
295 | #define REGISTER_VIRTUAL_TYPE(N) \ | |
ed9a39eb JM |
296 | (((unsigned)(N) - F0_REGNUM) < NUM_FREGS \ |
297 | ? builtin_type_double : builtin_type_int) | |
298 | ||
c906108c SS |
299 | /* The system C compiler uses a similar structure return convention to gcc */ |
300 | extern use_struct_convention_fn arm_use_struct_convention; | |
ed9a39eb JM |
301 | #define USE_STRUCT_CONVENTION(gcc_p, type) \ |
302 | arm_use_struct_convention (gcc_p, type) | |
c906108c SS |
303 | |
304 | /* Store the address of the place in which to copy the structure the | |
305 | subroutine will return. This is called from call_function. */ | |
306 | ||
307 | #define STORE_STRUCT_RETURN(ADDR, SP) \ | |
ed9a39eb | 308 | write_register (A1_REGNUM, (ADDR)) |
c906108c | 309 | |
ed9a39eb JM |
310 | /* Extract from an array REGBUF containing the (raw) register state a |
311 | function return value of type TYPE, and copy that, in virtual | |
312 | format, into VALBUF. */ | |
c906108c | 313 | |
ed9a39eb | 314 | extern void arm_extract_return_value (struct type *, char[], char *); |
c906108c | 315 | #define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \ |
ed9a39eb | 316 | arm_extract_return_value ((TYPE), (REGBUF), (VALBUF)) |
c906108c | 317 | |
ed9a39eb JM |
318 | /* Write into appropriate registers a function return value of type |
319 | TYPE, given in virtual format. */ | |
c906108c | 320 | |
ed9a39eb | 321 | extern void convert_to_extended (void *dbl, void *ptr); |
c906108c SS |
322 | #define STORE_RETURN_VALUE(TYPE,VALBUF) \ |
323 | if (TYPE_CODE (TYPE) == TYPE_CODE_FLT) { \ | |
324 | char _buf[MAX_REGISTER_RAW_SIZE]; \ | |
325 | convert_to_extended (VALBUF, _buf); \ | |
326 | write_register_bytes (REGISTER_BYTE (F0_REGNUM), _buf, MAX_REGISTER_RAW_SIZE); \ | |
327 | } else \ | |
328 | write_register_bytes (0, VALBUF, TYPE_LENGTH (TYPE)) | |
329 | ||
330 | /* Extract from an array REGBUF containing the (raw) register state | |
331 | the address in which a function should return its structure value, | |
332 | as a CORE_ADDR (or an expression that can be used as one). */ | |
333 | ||
7a292a7a | 334 | #define EXTRACT_STRUCT_VALUE_ADDRESS(REGBUF) \ |
ed9a39eb | 335 | (extract_address ((PTR)(REGBUF), REGISTER_RAW_SIZE(0))) |
c906108c SS |
336 | |
337 | /* Specify that for the native compiler variables for a particular | |
338 | lexical context are listed after the beginning LBRAC instead of | |
339 | before in the executables list of symbols. */ | |
340 | #define VARIABLES_INSIDE_BLOCK(desc, gcc_p) (!(gcc_p)) | |
c906108c | 341 | \f |
c5aa993b | 342 | |
ed9a39eb JM |
343 | /* Define other aspects of the stack frame. We keep the offsets of |
344 | all saved registers, 'cause we need 'em a lot! We also keep the | |
345 | current size of the stack frame, and the offset of the frame | |
346 | pointer from the stack pointer (for frameless functions, and when | |
347 | we're still in the prologue of a function with a frame) */ | |
c906108c SS |
348 | |
349 | #define EXTRA_FRAME_INFO \ | |
350 | struct frame_saved_regs fsr; \ | |
351 | int framesize; \ | |
352 | int frameoffset; \ | |
353 | int framereg; | |
354 | ||
ed9a39eb | 355 | extern void arm_init_extra_frame_info (int fromleaf, struct frame_info * fi); |
96baa820 | 356 | #define INIT_EXTRA_FRAME_INFO(fromleaf, fi) \ |
ed9a39eb | 357 | arm_init_extra_frame_info ((fromleaf), (fi)) |
c906108c SS |
358 | |
359 | /* Return the frame address. On ARM, it is R11; on Thumb it is R7. */ | |
ed9a39eb | 360 | CORE_ADDR arm_target_read_fp (void); |
c906108c SS |
361 | #define TARGET_READ_FP() arm_target_read_fp () |
362 | ||
ed9a39eb JM |
363 | /* Describe the pointer in each stack frame to the previous stack |
364 | frame (its caller). */ | |
c906108c | 365 | |
ed9a39eb JM |
366 | /* FRAME_CHAIN takes a frame's nominal address and produces the |
367 | frame's chain-pointer. | |
c906108c SS |
368 | |
369 | However, if FRAME_CHAIN_VALID returns zero, | |
370 | it means the given frame is the outermost one and has no caller. */ | |
371 | ||
ed9a39eb JM |
372 | #define FRAME_CHAIN(thisframe) arm_frame_chain (thisframe) |
373 | extern CORE_ADDR arm_frame_chain (struct frame_info *); | |
c906108c | 374 | |
ed9a39eb JM |
375 | extern int arm_frame_chain_valid (CORE_ADDR, struct frame_info *); |
376 | #define FRAME_CHAIN_VALID(chain, thisframe) \ | |
377 | arm_frame_chain_valid (chain, thisframe) | |
c906108c SS |
378 | |
379 | /* Define other aspects of the stack frame. */ | |
380 | ||
96baa820 JM |
381 | /* A macro that tells us whether the function invocation represented |
382 | by FI does not have a frame on the stack associated with it. If it | |
383 | does not, FRAMELESS is set to 1, else 0. | |
384 | ||
ed9a39eb JM |
385 | Sometimes we have functions that do a little setup (like saving the |
386 | vN registers with the stmdb instruction, but DO NOT set up a frame. | |
96baa820 | 387 | The symbol table will report this as a prologue. However, it is |
ed9a39eb | 388 | important not to try to parse these partial frames as frames, or we |
96baa820 JM |
389 | will get really confused. |
390 | ||
ed9a39eb JM |
391 | So I will demand 3 instructions between the start & end of the |
392 | prologue before I call it a real prologue, i.e. at least | |
96baa820 JM |
393 | mov ip, sp, |
394 | stmdb sp!, {} | |
395 | sub sp, ip, #4. */ | |
396 | ||
104c1213 | 397 | extern int arm_frameless_function_invocation (struct frame_info *fi); |
96baa820 JM |
398 | #define FRAMELESS_FUNCTION_INVOCATION(FI) \ |
399 | (arm_frameless_function_invocation (FI)) | |
ed9a39eb | 400 | |
c906108c SS |
401 | /* Saved Pc. */ |
402 | ||
403 | #define FRAME_SAVED_PC(FRAME) arm_frame_saved_pc (FRAME) | |
ed9a39eb | 404 | extern CORE_ADDR arm_frame_saved_pc (struct frame_info *); |
c906108c SS |
405 | |
406 | #define FRAME_ARGS_ADDRESS(fi) (fi->frame) | |
407 | ||
408 | #define FRAME_LOCALS_ADDRESS(fi) ((fi)->frame) | |
409 | ||
410 | /* Return number of args passed to a frame. | |
411 | Can return -1, meaning no way to tell. */ | |
412 | ||
392a587b | 413 | #define FRAME_NUM_ARGS(fi) (-1) |
c906108c | 414 | |
ed9a39eb | 415 | /* Return number of bytes at start of arglist that are not really args. */ |
c906108c SS |
416 | |
417 | #define FRAME_ARGS_SKIP 0 | |
418 | ||
ed9a39eb JM |
419 | /* Put here the code to store, into a struct frame_saved_regs, the |
420 | addresses of the saved registers of frame described by FRAME_INFO. | |
c906108c | 421 | This includes special registers such as pc and fp saved in special |
ed9a39eb JM |
422 | ways in the stack frame. sp is even more special: the address we |
423 | return for it IS the sp for the next frame. */ | |
c906108c SS |
424 | |
425 | struct frame_saved_regs; | |
426 | struct frame_info; | |
104c1213 JM |
427 | void arm_frame_find_saved_regs (struct frame_info * fi, |
428 | struct frame_saved_regs * fsr); | |
c906108c SS |
429 | |
430 | #define FRAME_FIND_SAVED_REGS(frame_info, frame_saved_regs) \ | |
ed9a39eb | 431 | arm_frame_find_saved_regs (frame_info, &(frame_saved_regs)); |
c5aa993b | 432 | |
c906108c SS |
433 | /* Things needed for making the inferior call functions. */ |
434 | ||
435 | #define PUSH_ARGUMENTS(nargs, args, sp, struct_return, struct_addr) \ | |
ed9a39eb JM |
436 | sp = arm_push_arguments ((nargs), (args), (sp), (struct_return), (struct_addr)) |
437 | extern CORE_ADDR arm_push_arguments (int, struct value **, CORE_ADDR, int, | |
438 | CORE_ADDR); | |
c906108c SS |
439 | |
440 | /* Push an empty stack frame, to record the current PC, etc. */ | |
441 | ||
ed9a39eb | 442 | void arm_push_dummy_frame (void); |
c906108c SS |
443 | |
444 | #define PUSH_DUMMY_FRAME arm_push_dummy_frame () | |
445 | ||
446 | /* Discard from the stack the innermost frame, restoring all registers. */ | |
447 | ||
ed9a39eb | 448 | void arm_pop_frame (void); |
c906108c SS |
449 | |
450 | #define POP_FRAME arm_pop_frame () | |
451 | ||
452 | /* This sequence of words is the instructions | |
453 | ||
c5aa993b JM |
454 | mov lr,pc |
455 | mov pc,r4 | |
456 | illegal | |
c906108c SS |
457 | |
458 | Note this is 12 bytes. */ | |
459 | ||
ed9a39eb JM |
460 | #define CALL_DUMMY {0xe1a0e00f, 0xe1a0f004, 0xe7ffdefe} |
461 | #define CALL_DUMMY_START_OFFSET 0 /* Start execution at beginning of dummy */ | |
c906108c SS |
462 | |
463 | #define CALL_DUMMY_BREAKPOINT_OFFSET arm_call_dummy_breakpoint_offset() | |
ed9a39eb | 464 | extern int arm_call_dummy_breakpoint_offset (void); |
c906108c | 465 | |
ed9a39eb JM |
466 | /* Insert the specified number of args and function address into a |
467 | call sequence of the above form stored at DUMMYNAME. */ | |
c906108c SS |
468 | |
469 | #define FIX_CALL_DUMMY(dummyname, pc, fun, nargs, args, type, gcc_p) \ | |
ed9a39eb | 470 | arm_fix_call_dummy ((dummyname), (pc), (fun), (nargs), (args), (type), (gcc_p)) |
c906108c | 471 | |
ed9a39eb JM |
472 | void arm_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, |
473 | int nargs, struct value ** args, | |
474 | struct type * type, int gcc_p); | |
c906108c | 475 | |
ed9a39eb | 476 | CORE_ADDR arm_get_next_pc (CORE_ADDR pc); |
c906108c | 477 | |
ed9a39eb JM |
478 | /* Macros for setting and testing a bit in a minimal symbol that marks |
479 | it as Thumb function. The MSB of the minimal symbol's "info" field | |
480 | is used for this purpose. This field is already being used to store | |
481 | the symbol size, so the assumption is that the symbol size cannot | |
482 | exceed 2^31. | |
c5aa993b | 483 | |
c906108c | 484 | COFF_MAKE_MSYMBOL_SPECIAL |
ed9a39eb JM |
485 | ELF_MAKE_MSYMBOL_SPECIAL |
486 | ||
487 | These macros test whether the COFF or ELF symbol corresponds to a | |
488 | thumb function, and set a "special" bit in a minimal symbol to | |
489 | indicate that it does. | |
490 | ||
491 | MSYMBOL_SET_SPECIAL Actually sets the "special" bit. | |
492 | MSYMBOL_IS_SPECIAL Tests the "special" bit in a minimal symbol. | |
493 | MSYMBOL_SIZE Returns the size of the minimal symbol, | |
494 | i.e. the "info" field with the "special" bit | |
495 | masked out | |
496 | */ | |
c5aa993b JM |
497 | |
498 | extern int coff_sym_is_thumb (int val); | |
ed9a39eb | 499 | |
c906108c | 500 | #define MSYMBOL_SET_SPECIAL(msym) \ |
ed9a39eb | 501 | MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000) |
c906108c SS |
502 | #define MSYMBOL_IS_SPECIAL(msym) \ |
503 | (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0) | |
504 | #define MSYMBOL_SIZE(msym) \ | |
505 | ((long) MSYMBOL_INFO (msym) & 0x7fffffff) | |
506 | ||
ed9a39eb | 507 | /* Thumb symbols are of type STT_LOPROC, (synonymous with STT_ARM_TFUNC) */ |
c906108c | 508 | #define ELF_MAKE_MSYMBOL_SPECIAL(sym,msym) \ |
ed9a39eb JM |
509 | { if(ELF_ST_TYPE(((elf_symbol_type *)(sym))->internal_elf_sym.st_info) == STT_LOPROC) \ |
510 | MSYMBOL_SET_SPECIAL(msym); } | |
c5aa993b | 511 | |
c906108c SS |
512 | #define COFF_MAKE_MSYMBOL_SPECIAL(val,msym) \ |
513 | { if(coff_sym_is_thumb(val)) MSYMBOL_SET_SPECIAL(msym); } | |
514 | ||
dfcd3bfb JM |
515 | /* The first 0x20 bytes are the trap vectors. */ |
516 | #define LOWEST_PC 0x20 | |
517 | ||
ed9a39eb | 518 | #endif /* TM_ARM_H */ |