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29134980 | 1 | /* Target dependent code for CRIS, for GDB, the GNU debugger. |
6b4d5c91 | 2 | |
213516ef | 3 | Copyright (C) 2001-2023 Free Software Foundation, Inc. |
6b4d5c91 | 4 | |
29134980 OF |
5 | Contributed by Axis Communications AB. |
6 | Written by Hendrik Ruijter, Stefan Andersson, and Orjan Friberg. | |
7 | ||
a9762ec7 | 8 | This file is part of GDB. |
29134980 | 9 | |
a9762ec7 JB |
10 | This program is free software; you can redistribute it and/or modify |
11 | it under the terms of the GNU General Public License as published by | |
12 | the Free Software Foundation; either version 3 of the License, or | |
13 | (at your option) any later version. | |
29134980 | 14 | |
a9762ec7 JB |
15 | This program is distributed in the hope that it will be useful, |
16 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | GNU General Public License for more details. | |
29134980 | 19 | |
a9762ec7 JB |
20 | You should have received a copy of the GNU General Public License |
21 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
29134980 OF |
22 | |
23 | #include "defs.h" | |
d55e5aa6 | 24 | #include "frame.h" |
4de283e4 TT |
25 | #include "frame-unwind.h" |
26 | #include "frame-base.h" | |
27 | #include "trad-frame.h" | |
82ca8957 | 28 | #include "dwarf2/frame.h" |
4de283e4 | 29 | #include "symtab.h" |
d55e5aa6 | 30 | #include "inferior.h" |
4de283e4 TT |
31 | #include "gdbtypes.h" |
32 | #include "gdbcore.h" | |
33 | #include "gdbcmd.h" | |
34 | #include "target.h" | |
35 | #include "value.h" | |
29134980 | 36 | #include "opcode/cris.h" |
749c8b38 | 37 | #include "osabi.h" |
4de283e4 | 38 | #include "arch-utils.h" |
29134980 | 39 | #include "regcache.h" |
69ed9b74 | 40 | #include "regset.h" |
4de283e4 TT |
41 | |
42 | #include "objfiles.h" | |
43 | ||
44 | #include "solib.h" /* Support for shared libraries. */ | |
76a9d10f | 45 | #include "solib-svr4.h" |
4de283e4 TT |
46 | #include "dis-asm.h" |
47 | ||
48 | #include "cris-tdep.h" | |
749c8b38 | 49 | |
29134980 OF |
50 | enum cris_num_regs |
51 | { | |
52 | /* There are no floating point registers. Used in gdbserver low-linux.c. */ | |
53 | NUM_FREGS = 0, | |
54 | ||
55 | /* There are 16 general registers. */ | |
56 | NUM_GENREGS = 16, | |
57 | ||
58 | /* There are 16 special registers. */ | |
c600d464 OF |
59 | NUM_SPECREGS = 16, |
60 | ||
61 | /* CRISv32 has a pseudo PC register, not noted here. */ | |
62 | ||
63 | /* CRISv32 has 16 support registers. */ | |
64 | NUM_SUPPREGS = 16 | |
29134980 OF |
65 | }; |
66 | ||
67 | /* Register numbers of various important registers. | |
2e4b5889 | 68 | CRIS_FP_REGNUM Contains address of executing stack frame. |
29134980 OF |
69 | STR_REGNUM Contains the address of structure return values. |
70 | RET_REGNUM Contains the return value when shorter than or equal to 32 bits | |
71 | ARG1_REGNUM Contains the first parameter to a function. | |
72 | ARG2_REGNUM Contains the second parameter to a function. | |
73 | ARG3_REGNUM Contains the third parameter to a function. | |
0963b4bd | 74 | ARG4_REGNUM Contains the fourth parameter to a function. Rest on stack. |
3e8c568d UW |
75 | gdbarch_sp_regnum Contains address of top of stack. |
76 | gdbarch_pc_regnum Contains address of next instruction. | |
29134980 OF |
77 | SRP_REGNUM Subroutine return pointer register. |
78 | BRP_REGNUM Breakpoint return pointer register. */ | |
79 | ||
29134980 OF |
80 | enum cris_regnums |
81 | { | |
82 | /* Enums with respect to the general registers, valid for all | |
c600d464 | 83 | CRIS versions. The frame pointer is always in R8. */ |
2e4b5889 | 84 | CRIS_FP_REGNUM = 8, |
c600d464 | 85 | /* ABI related registers. */ |
29134980 OF |
86 | STR_REGNUM = 9, |
87 | RET_REGNUM = 10, | |
88 | ARG1_REGNUM = 10, | |
89 | ARG2_REGNUM = 11, | |
90 | ARG3_REGNUM = 12, | |
91 | ARG4_REGNUM = 13, | |
92 | ||
c600d464 | 93 | /* Registers which happen to be common. */ |
29134980 | 94 | VR_REGNUM = 17, |
c600d464 OF |
95 | MOF_REGNUM = 23, |
96 | SRP_REGNUM = 27, | |
97 | ||
0963b4bd | 98 | /* CRISv10 et al. specific registers. */ |
c600d464 | 99 | P0_REGNUM = 16, |
29134980 OF |
100 | P4_REGNUM = 20, |
101 | CCR_REGNUM = 21, | |
29134980 OF |
102 | P8_REGNUM = 24, |
103 | IBR_REGNUM = 25, | |
104 | IRP_REGNUM = 26, | |
29134980 | 105 | BAR_REGNUM = 28, |
2a9ecef2 | 106 | DCCR_REGNUM = 29, |
29134980 | 107 | BRP_REGNUM = 30, |
c600d464 OF |
108 | USP_REGNUM = 31, |
109 | ||
110 | /* CRISv32 specific registers. */ | |
111 | ACR_REGNUM = 15, | |
112 | BZ_REGNUM = 16, | |
113 | PID_REGNUM = 18, | |
114 | SRS_REGNUM = 19, | |
115 | WZ_REGNUM = 20, | |
116 | EXS_REGNUM = 21, | |
117 | EDA_REGNUM = 22, | |
118 | DZ_REGNUM = 24, | |
119 | EBP_REGNUM = 25, | |
120 | ERP_REGNUM = 26, | |
121 | NRP_REGNUM = 28, | |
122 | CCS_REGNUM = 29, | |
123 | CRISV32USP_REGNUM = 30, /* Shares name but not number with CRISv10. */ | |
124 | SPC_REGNUM = 31, | |
125 | CRISV32PC_REGNUM = 32, /* Shares name but not number with CRISv10. */ | |
126 | ||
127 | S0_REGNUM = 33, | |
128 | S1_REGNUM = 34, | |
129 | S2_REGNUM = 35, | |
130 | S3_REGNUM = 36, | |
131 | S4_REGNUM = 37, | |
132 | S5_REGNUM = 38, | |
133 | S6_REGNUM = 39, | |
134 | S7_REGNUM = 40, | |
135 | S8_REGNUM = 41, | |
136 | S9_REGNUM = 42, | |
137 | S10_REGNUM = 43, | |
138 | S11_REGNUM = 44, | |
139 | S12_REGNUM = 45, | |
140 | S13_REGNUM = 46, | |
141 | S14_REGNUM = 47, | |
142 | S15_REGNUM = 48, | |
29134980 OF |
143 | }; |
144 | ||
145 | extern const struct cris_spec_reg cris_spec_regs[]; | |
146 | ||
147 | /* CRIS version, set via the user command 'set cris-version'. Affects | |
0e6bdb31 | 148 | register names and sizes. */ |
e4286e57 | 149 | static unsigned int usr_cmd_cris_version; |
29134980 OF |
150 | |
151 | /* Indicates whether to trust the above variable. */ | |
491144b5 | 152 | static bool usr_cmd_cris_version_valid = false; |
29134980 | 153 | |
41922353 OF |
154 | static const char cris_mode_normal[] = "normal"; |
155 | static const char cris_mode_guru[] = "guru"; | |
40478521 | 156 | static const char *const cris_modes[] = { |
0e6bdb31 OF |
157 | cris_mode_normal, |
158 | cris_mode_guru, | |
159 | 0 | |
160 | }; | |
161 | ||
162 | /* CRIS mode, set via the user command 'set cris-mode'. Affects | |
163 | type of break instruction among other things. */ | |
164 | static const char *usr_cmd_cris_mode = cris_mode_normal; | |
165 | ||
a5f6c8f5 | 166 | /* Whether to make use of Dwarf-2 CFI (default on). */ |
491144b5 | 167 | static bool usr_cmd_cris_dwarf2_cfi = true; |
29134980 | 168 | |
a5f6c8f5 OF |
169 | /* Sigtramp identification code copied from i386-linux-tdep.c. */ |
170 | ||
171 | #define SIGTRAMP_INSN0 0x9c5f /* movu.w 0xXX, $r9 */ | |
172 | #define SIGTRAMP_OFFSET0 0 | |
173 | #define SIGTRAMP_INSN1 0xe93d /* break 13 */ | |
174 | #define SIGTRAMP_OFFSET1 4 | |
175 | ||
176 | static const unsigned short sigtramp_code[] = | |
177 | { | |
178 | SIGTRAMP_INSN0, 0x0077, /* movu.w $0x77, $r9 */ | |
179 | SIGTRAMP_INSN1 /* break 13 */ | |
180 | }; | |
181 | ||
182 | #define SIGTRAMP_LEN (sizeof sigtramp_code) | |
183 | ||
184 | /* Note: same length as normal sigtramp code. */ | |
185 | ||
186 | static const unsigned short rt_sigtramp_code[] = | |
29134980 | 187 | { |
a5f6c8f5 OF |
188 | SIGTRAMP_INSN0, 0x00ad, /* movu.w $0xad, $r9 */ |
189 | SIGTRAMP_INSN1 /* break 13 */ | |
190 | }; | |
191 | ||
192 | /* If PC is in a sigtramp routine, return the address of the start of | |
193 | the routine. Otherwise, return 0. */ | |
194 | ||
195 | static CORE_ADDR | |
bd2b40ac | 196 | cris_sigtramp_start (frame_info_ptr this_frame) |
a5f6c8f5 | 197 | { |
94afd7a6 | 198 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 199 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 200 | |
bdec2917 | 201 | if (!safe_frame_unwind_memory (this_frame, pc, buf)) |
a5f6c8f5 OF |
202 | return 0; |
203 | ||
e2a2a3e8 | 204 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 205 | { |
e2a2a3e8 | 206 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
207 | return 0; |
208 | ||
209 | pc -= SIGTRAMP_OFFSET1; | |
bdec2917 | 210 | if (!safe_frame_unwind_memory (this_frame, pc, buf)) |
a5f6c8f5 OF |
211 | return 0; |
212 | } | |
213 | ||
214 | if (memcmp (buf, sigtramp_code, SIGTRAMP_LEN) != 0) | |
215 | return 0; | |
216 | ||
217 | return pc; | |
218 | } | |
219 | ||
220 | /* If PC is in a RT sigtramp routine, return the address of the start of | |
221 | the routine. Otherwise, return 0. */ | |
222 | ||
223 | static CORE_ADDR | |
bd2b40ac | 224 | cris_rt_sigtramp_start (frame_info_ptr this_frame) |
a5f6c8f5 | 225 | { |
94afd7a6 | 226 | CORE_ADDR pc = get_frame_pc (this_frame); |
e2a2a3e8 | 227 | gdb_byte buf[SIGTRAMP_LEN]; |
a5f6c8f5 | 228 | |
bdec2917 | 229 | if (!safe_frame_unwind_memory (this_frame, pc, buf)) |
a5f6c8f5 OF |
230 | return 0; |
231 | ||
e2a2a3e8 | 232 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN0) |
a5f6c8f5 | 233 | { |
e2a2a3e8 | 234 | if (((buf[1] << 8) + buf[0]) != SIGTRAMP_INSN1) |
a5f6c8f5 OF |
235 | return 0; |
236 | ||
237 | pc -= SIGTRAMP_OFFSET1; | |
bdec2917 | 238 | if (!safe_frame_unwind_memory (this_frame, pc, buf)) |
a5f6c8f5 OF |
239 | return 0; |
240 | } | |
241 | ||
242 | if (memcmp (buf, rt_sigtramp_code, SIGTRAMP_LEN) != 0) | |
243 | return 0; | |
244 | ||
245 | return pc; | |
246 | } | |
247 | ||
94afd7a6 UW |
248 | /* Assuming THIS_FRAME is a frame for a GNU/Linux sigtramp routine, |
249 | return the address of the associated sigcontext structure. */ | |
a5f6c8f5 OF |
250 | |
251 | static CORE_ADDR | |
bd2b40ac | 252 | cris_sigcontext_addr (frame_info_ptr this_frame) |
a5f6c8f5 | 253 | { |
e17a4113 UW |
254 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
255 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
a5f6c8f5 OF |
256 | CORE_ADDR pc; |
257 | CORE_ADDR sp; | |
e362b510 | 258 | gdb_byte buf[4]; |
a5f6c8f5 | 259 | |
e17a4113 UW |
260 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
261 | sp = extract_unsigned_integer (buf, 4, byte_order); | |
a5f6c8f5 OF |
262 | |
263 | /* Look for normal sigtramp frame first. */ | |
94afd7a6 | 264 | pc = cris_sigtramp_start (this_frame); |
a5f6c8f5 OF |
265 | if (pc) |
266 | { | |
267 | /* struct signal_frame (arch/cris/kernel/signal.c) contains | |
268 | struct sigcontext as its first member, meaning the SP points to | |
269 | it already. */ | |
270 | return sp; | |
271 | } | |
272 | ||
94afd7a6 | 273 | pc = cris_rt_sigtramp_start (this_frame); |
a5f6c8f5 OF |
274 | if (pc) |
275 | { | |
276 | /* struct rt_signal_frame (arch/cris/kernel/signal.c) contains | |
277 | a struct ucontext, which in turn contains a struct sigcontext. | |
278 | Magic digging: | |
279 | 4 + 4 + 128 to struct ucontext, then | |
280 | 4 + 4 + 12 to struct sigcontext. */ | |
281 | return (sp + 156); | |
282 | } | |
283 | ||
8a3fe4f8 | 284 | error (_("Couldn't recognize signal trampoline.")); |
a5f6c8f5 | 285 | return 0; |
29134980 OF |
286 | } |
287 | ||
2e4b5889 | 288 | struct cris_unwind_cache |
29134980 | 289 | { |
2e4b5889 OF |
290 | /* The previous frame's inner most stack address. Used as this |
291 | frame ID's stack_addr. */ | |
292 | CORE_ADDR prev_sp; | |
293 | /* The frame's base, optionally used by the high-level debug info. */ | |
294 | CORE_ADDR base; | |
295 | int size; | |
296 | /* How far the SP and r8 (FP) have been offset from the start of | |
297 | the stack frame (as defined by the previous frame's stack | |
298 | pointer). */ | |
299 | LONGEST sp_offset; | |
300 | LONGEST r8_offset; | |
301 | int uses_frame; | |
302 | ||
303 | /* From old frame_extra_info struct. */ | |
29134980 OF |
304 | CORE_ADDR return_pc; |
305 | int leaf_function; | |
2e4b5889 OF |
306 | |
307 | /* Table indicating the location of each and every register. */ | |
098caef4 | 308 | trad_frame_saved_reg *saved_regs; |
29134980 OF |
309 | }; |
310 | ||
a5f6c8f5 | 311 | static struct cris_unwind_cache * |
bd2b40ac | 312 | cris_sigtramp_frame_unwind_cache (frame_info_ptr this_frame, |
a5f6c8f5 OF |
313 | void **this_cache) |
314 | { | |
94afd7a6 | 315 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
08106042 | 316 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
e17a4113 | 317 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
a5f6c8f5 | 318 | struct cris_unwind_cache *info; |
a5f6c8f5 | 319 | CORE_ADDR addr; |
e362b510 | 320 | gdb_byte buf[4]; |
a5f6c8f5 OF |
321 | int i; |
322 | ||
323 | if ((*this_cache)) | |
9a3c8263 | 324 | return (struct cris_unwind_cache *) (*this_cache); |
a5f6c8f5 OF |
325 | |
326 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
327 | (*this_cache) = info; | |
94afd7a6 | 328 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
a5f6c8f5 OF |
329 | |
330 | /* Zero all fields. */ | |
331 | info->prev_sp = 0; | |
332 | info->base = 0; | |
333 | info->size = 0; | |
334 | info->sp_offset = 0; | |
335 | info->r8_offset = 0; | |
336 | info->uses_frame = 0; | |
337 | info->return_pc = 0; | |
338 | info->leaf_function = 0; | |
339 | ||
94afd7a6 | 340 | get_frame_register (this_frame, gdbarch_sp_regnum (gdbarch), buf); |
e17a4113 | 341 | info->base = extract_unsigned_integer (buf, 4, byte_order); |
a5f6c8f5 | 342 | |
94afd7a6 | 343 | addr = cris_sigcontext_addr (this_frame); |
a5f6c8f5 OF |
344 | |
345 | /* Layout of the sigcontext struct: | |
346 | struct sigcontext { | |
347 | struct pt_regs regs; | |
348 | unsigned long oldmask; | |
349 | unsigned long usp; | |
350 | }; */ | |
351 | ||
c600d464 OF |
352 | if (tdep->cris_version == 10) |
353 | { | |
354 | /* R0 to R13 are stored in reverse order at offset (2 * 4) in | |
355 | struct pt_regs. */ | |
356 | for (i = 0; i <= 13; i++) | |
098caef4 | 357 | info->saved_regs[i].set_addr (addr + ((15 - i) * 4)); |
c600d464 | 358 | |
098caef4 LM |
359 | info->saved_regs[MOF_REGNUM].set_addr (addr + (16 * 4)); |
360 | info->saved_regs[DCCR_REGNUM].set_addr (addr + (17 * 4)); | |
361 | info->saved_regs[SRP_REGNUM].set_addr (addr + (18 * 4)); | |
c600d464 OF |
362 | /* Note: IRP is off by 2 at this point. There's no point in correcting |
363 | it though since that will mean that the backtrace will show a PC | |
364 | different from what is shown when stopped. */ | |
098caef4 | 365 | info->saved_regs[IRP_REGNUM].set_addr (addr + (19 * 4)); |
7fbe2eba | 366 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 367 | = info->saved_regs[IRP_REGNUM]; |
098caef4 | 368 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].set_addr (addr + (24 * 4)); |
c600d464 OF |
369 | } |
370 | else | |
371 | { | |
372 | /* CRISv32. */ | |
373 | /* R0 to R13 are stored in order at offset (1 * 4) in | |
374 | struct pt_regs. */ | |
375 | for (i = 0; i <= 13; i++) | |
098caef4 LM |
376 | info->saved_regs[i].set_addr (addr + ((i + 1) * 4)); |
377 | ||
378 | info->saved_regs[ACR_REGNUM].set_addr (addr + (15 * 4)); | |
379 | info->saved_regs[SRS_REGNUM].set_addr (addr + (16 * 4)); | |
380 | info->saved_regs[MOF_REGNUM].set_addr (addr + (17 * 4)); | |
381 | info->saved_regs[SPC_REGNUM].set_addr (addr + (18 * 4)); | |
382 | info->saved_regs[CCS_REGNUM].set_addr (addr + (19 * 4)); | |
383 | info->saved_regs[SRP_REGNUM].set_addr (addr + (20 * 4)); | |
384 | info->saved_regs[ERP_REGNUM].set_addr (addr + (21 * 4)); | |
385 | info->saved_regs[EXS_REGNUM].set_addr (addr + (22 * 4)); | |
386 | info->saved_regs[EDA_REGNUM].set_addr (addr + (23 * 4)); | |
c600d464 OF |
387 | |
388 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
389 | be wrong at this point. This problem manifests itself in the | |
390 | sigaltstack.exp test case, which occasionally generates FAILs when | |
0963b4bd | 391 | the signal is received while in a delay slot. |
c600d464 OF |
392 | |
393 | This could be solved by a couple of read_memory_unsigned_integer and a | |
394 | trad_frame_set_value. */ | |
7fbe2eba | 395 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 396 | = info->saved_regs[ERP_REGNUM]; |
c600d464 | 397 | |
098caef4 | 398 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].set_addr (addr + (25 * 4)); |
c600d464 | 399 | } |
a5f6c8f5 OF |
400 | |
401 | return info; | |
402 | } | |
403 | ||
404 | static void | |
bd2b40ac | 405 | cris_sigtramp_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
dda83cd7 | 406 | struct frame_id *this_id) |
a5f6c8f5 OF |
407 | { |
408 | struct cris_unwind_cache *cache = | |
94afd7a6 UW |
409 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
410 | (*this_id) = frame_id_build (cache->base, get_frame_pc (this_frame)); | |
a5f6c8f5 OF |
411 | } |
412 | ||
413 | /* Forward declaration. */ | |
414 | ||
bd2b40ac | 415 | static struct value *cris_frame_prev_register (frame_info_ptr this_frame, |
94afd7a6 UW |
416 | void **this_cache, int regnum); |
417 | static struct value * | |
bd2b40ac | 418 | cris_sigtramp_frame_prev_register (frame_info_ptr this_frame, |
dda83cd7 | 419 | void **this_cache, int regnum) |
a5f6c8f5 OF |
420 | { |
421 | /* Make sure we've initialized the cache. */ | |
94afd7a6 UW |
422 | cris_sigtramp_frame_unwind_cache (this_frame, this_cache); |
423 | return cris_frame_prev_register (this_frame, this_cache, regnum); | |
424 | } | |
425 | ||
426 | static int | |
427 | cris_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 428 | frame_info_ptr this_frame, |
94afd7a6 UW |
429 | void **this_cache) |
430 | { | |
431 | if (cris_sigtramp_start (this_frame) | |
432 | || cris_rt_sigtramp_start (this_frame)) | |
433 | return 1; | |
434 | ||
435 | return 0; | |
a5f6c8f5 OF |
436 | } |
437 | ||
438 | static const struct frame_unwind cris_sigtramp_frame_unwind = | |
439 | { | |
a154d838 | 440 | "cris sigtramp", |
a5f6c8f5 | 441 | SIGTRAMP_FRAME, |
8fbca658 | 442 | default_frame_unwind_stop_reason, |
a5f6c8f5 | 443 | cris_sigtramp_frame_this_id, |
94afd7a6 UW |
444 | cris_sigtramp_frame_prev_register, |
445 | NULL, | |
446 | cris_sigtramp_frame_sniffer | |
a5f6c8f5 OF |
447 | }; |
448 | ||
63807e1d | 449 | static int |
c600d464 | 450 | crisv32_single_step_through_delay (struct gdbarch *gdbarch, |
bd2b40ac | 451 | frame_info_ptr this_frame) |
c600d464 | 452 | { |
08106042 | 453 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
c600d464 OF |
454 | ULONGEST erp; |
455 | int ret = 0; | |
c600d464 | 456 | |
35488783 | 457 | if (tdep->cris_mode == cris_mode_guru) |
395f2fc2 | 458 | erp = get_frame_register_unsigned (this_frame, NRP_REGNUM); |
0e6bdb31 | 459 | else |
395f2fc2 | 460 | erp = get_frame_register_unsigned (this_frame, ERP_REGNUM); |
c600d464 OF |
461 | |
462 | if (erp & 0x1) | |
463 | { | |
464 | /* In delay slot - check if there's a breakpoint at the preceding | |
465 | instruction. */ | |
6c95b8df | 466 | if (breakpoint_here_p (get_frame_address_space (this_frame), erp & ~0x1)) |
c600d464 OF |
467 | ret = 1; |
468 | } | |
469 | return ret; | |
470 | } | |
471 | ||
29134980 | 472 | /* The instruction environment needed to find single-step breakpoints. */ |
c600d464 | 473 | |
29134980 OF |
474 | typedef |
475 | struct instruction_environment | |
476 | { | |
477 | unsigned long reg[NUM_GENREGS]; | |
478 | unsigned long preg[NUM_SPECREGS]; | |
479 | unsigned long branch_break_address; | |
480 | unsigned long delay_slot_pc; | |
481 | unsigned long prefix_value; | |
482 | int branch_found; | |
483 | int prefix_found; | |
484 | int invalid; | |
485 | int slot_needed; | |
486 | int delay_slot_pc_active; | |
487 | int xflag_found; | |
488 | int disable_interrupt; | |
78c5b882 | 489 | enum bfd_endian byte_order; |
29134980 OF |
490 | } inst_env_type; |
491 | ||
29134980 OF |
492 | /* Machine-dependencies in CRIS for opcodes. */ |
493 | ||
494 | /* Instruction sizes. */ | |
495 | enum cris_instruction_sizes | |
496 | { | |
497 | INST_BYTE_SIZE = 0, | |
498 | INST_WORD_SIZE = 1, | |
499 | INST_DWORD_SIZE = 2 | |
500 | }; | |
501 | ||
502 | /* Addressing modes. */ | |
503 | enum cris_addressing_modes | |
504 | { | |
505 | REGISTER_MODE = 1, | |
506 | INDIRECT_MODE = 2, | |
507 | AUTOINC_MODE = 3 | |
508 | }; | |
509 | ||
510 | /* Prefix addressing modes. */ | |
511 | enum cris_prefix_addressing_modes | |
512 | { | |
513 | PREFIX_INDEX_MODE = 2, | |
514 | PREFIX_ASSIGN_MODE = 3, | |
515 | ||
516 | /* Handle immediate byte offset addressing mode prefix format. */ | |
517 | PREFIX_OFFSET_MODE = 2 | |
518 | }; | |
519 | ||
520 | /* Masks for opcodes. */ | |
521 | enum cris_opcode_masks | |
522 | { | |
523 | BRANCH_SIGNED_SHORT_OFFSET_MASK = 0x1, | |
524 | SIGNED_EXTEND_BIT_MASK = 0x2, | |
525 | SIGNED_BYTE_MASK = 0x80, | |
526 | SIGNED_BYTE_EXTEND_MASK = 0xFFFFFF00, | |
527 | SIGNED_WORD_MASK = 0x8000, | |
528 | SIGNED_WORD_EXTEND_MASK = 0xFFFF0000, | |
529 | SIGNED_DWORD_MASK = 0x80000000, | |
530 | SIGNED_QUICK_VALUE_MASK = 0x20, | |
531 | SIGNED_QUICK_VALUE_EXTEND_MASK = 0xFFFFFFC0 | |
532 | }; | |
533 | ||
534 | /* Functions for opcodes. The general form of the ETRAX 16-bit instruction: | |
535 | Bit 15 - 12 Operand2 | |
536 | 11 - 10 Mode | |
dda83cd7 SM |
537 | 9 - 6 Opcode |
538 | 5 - 4 Size | |
539 | 3 - 0 Operand1 */ | |
29134980 OF |
540 | |
541 | static int | |
542 | cris_get_operand2 (unsigned short insn) | |
543 | { | |
544 | return ((insn & 0xF000) >> 12); | |
545 | } | |
546 | ||
547 | static int | |
548 | cris_get_mode (unsigned short insn) | |
549 | { | |
550 | return ((insn & 0x0C00) >> 10); | |
551 | } | |
552 | ||
553 | static int | |
554 | cris_get_opcode (unsigned short insn) | |
555 | { | |
556 | return ((insn & 0x03C0) >> 6); | |
557 | } | |
558 | ||
559 | static int | |
560 | cris_get_size (unsigned short insn) | |
561 | { | |
562 | return ((insn & 0x0030) >> 4); | |
563 | } | |
564 | ||
565 | static int | |
566 | cris_get_operand1 (unsigned short insn) | |
567 | { | |
568 | return (insn & 0x000F); | |
569 | } | |
570 | ||
571 | /* Additional functions in order to handle opcodes. */ | |
572 | ||
29134980 OF |
573 | static int |
574 | cris_get_quick_value (unsigned short insn) | |
575 | { | |
576 | return (insn & 0x003F); | |
577 | } | |
578 | ||
579 | static int | |
580 | cris_get_bdap_quick_offset (unsigned short insn) | |
581 | { | |
582 | return (insn & 0x00FF); | |
583 | } | |
584 | ||
585 | static int | |
586 | cris_get_branch_short_offset (unsigned short insn) | |
587 | { | |
588 | return (insn & 0x00FF); | |
589 | } | |
590 | ||
591 | static int | |
592 | cris_get_asr_shift_steps (unsigned long value) | |
593 | { | |
594 | return (value & 0x3F); | |
595 | } | |
596 | ||
29134980 OF |
597 | static int |
598 | cris_get_clear_size (unsigned short insn) | |
599 | { | |
600 | return ((insn) & 0xC000); | |
601 | } | |
602 | ||
603 | static int | |
604 | cris_is_signed_extend_bit_on (unsigned short insn) | |
605 | { | |
606 | return (((insn) & 0x20) == 0x20); | |
607 | } | |
608 | ||
609 | static int | |
610 | cris_is_xflag_bit_on (unsigned short insn) | |
611 | { | |
612 | return (((insn) & 0x1000) == 0x1000); | |
613 | } | |
614 | ||
615 | static void | |
616 | cris_set_size_to_dword (unsigned short *insn) | |
617 | { | |
618 | *insn &= 0xFFCF; | |
619 | *insn |= 0x20; | |
620 | } | |
621 | ||
8535cb38 | 622 | static signed char |
29134980 OF |
623 | cris_get_signed_offset (unsigned short insn) |
624 | { | |
8535cb38 | 625 | return ((signed char) (insn & 0x00FF)); |
29134980 OF |
626 | } |
627 | ||
628 | /* Calls an op function given the op-type, working on the insn and the | |
629 | inst_env. */ | |
be8626e0 MD |
630 | static void cris_gdb_func (struct gdbarch *, enum cris_op_type, unsigned short, |
631 | inst_env_type *); | |
29134980 | 632 | |
29134980 | 633 | static struct gdbarch *cris_gdbarch_init (struct gdbarch_info, |
dda83cd7 | 634 | struct gdbarch_list *); |
29134980 | 635 | |
29134980 OF |
636 | static void cris_dump_tdep (struct gdbarch *, struct ui_file *); |
637 | ||
eb4c3f4a | 638 | static void set_cris_version (const char *ignore_args, int from_tty, |
a5f6c8f5 | 639 | struct cmd_list_element *c); |
29134980 | 640 | |
eb4c3f4a | 641 | static void set_cris_mode (const char *ignore_args, int from_tty, |
0e6bdb31 OF |
642 | struct cmd_list_element *c); |
643 | ||
eb4c3f4a | 644 | static void set_cris_dwarf2_cfi (const char *ignore_args, int from_tty, |
a5f6c8f5 | 645 | struct cmd_list_element *c); |
29134980 | 646 | |
2e4b5889 | 647 | static CORE_ADDR cris_scan_prologue (CORE_ADDR pc, |
bd2b40ac | 648 | frame_info_ptr this_frame, |
2e4b5889 OF |
649 | struct cris_unwind_cache *info); |
650 | ||
5114e29d | 651 | static CORE_ADDR crisv32_scan_prologue (CORE_ADDR pc, |
bd2b40ac | 652 | frame_info_ptr this_frame, |
5114e29d OF |
653 | struct cris_unwind_cache *info); |
654 | ||
2e4b5889 | 655 | /* When arguments must be pushed onto the stack, they go on in reverse |
0963b4bd | 656 | order. The below implements a FILO (stack) to do this. |
a5f6c8f5 | 657 | Copied from d10v-tdep.c. */ |
2e4b5889 | 658 | |
0fecb1a7 | 659 | struct cris_stack_item |
2e4b5889 OF |
660 | { |
661 | int len; | |
0fecb1a7 | 662 | struct cris_stack_item *prev; |
7c543f7b | 663 | gdb_byte *data; |
2e4b5889 OF |
664 | }; |
665 | ||
0fecb1a7 TT |
666 | static struct cris_stack_item * |
667 | push_stack_item (struct cris_stack_item *prev, const gdb_byte *contents, | |
668 | int len) | |
2e4b5889 | 669 | { |
0fecb1a7 | 670 | struct cris_stack_item *si = XNEW (struct cris_stack_item); |
7c543f7b | 671 | si->data = (gdb_byte *) xmalloc (len); |
2e4b5889 OF |
672 | si->len = len; |
673 | si->prev = prev; | |
674 | memcpy (si->data, contents, len); | |
675 | return si; | |
676 | } | |
677 | ||
0fecb1a7 TT |
678 | static struct cris_stack_item * |
679 | pop_stack_item (struct cris_stack_item *si) | |
2e4b5889 | 680 | { |
0fecb1a7 | 681 | struct cris_stack_item *dead = si; |
2e4b5889 OF |
682 | si = si->prev; |
683 | xfree (dead->data); | |
684 | xfree (dead); | |
685 | return si; | |
686 | } | |
687 | ||
688 | /* Put here the code to store, into fi->saved_regs, the addresses of | |
689 | the saved registers of frame described by FRAME_INFO. This | |
690 | includes special registers such as pc and fp saved in special ways | |
691 | in the stack frame. sp is even more special: the address we return | |
a5f6c8f5 | 692 | for it IS the sp for the next frame. */ |
2e4b5889 | 693 | |
63807e1d | 694 | static struct cris_unwind_cache * |
bd2b40ac | 695 | cris_frame_unwind_cache (frame_info_ptr this_frame, |
2e4b5889 OF |
696 | void **this_prologue_cache) |
697 | { | |
35488783 | 698 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
08106042 | 699 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
2e4b5889 | 700 | struct cris_unwind_cache *info; |
2e4b5889 OF |
701 | |
702 | if ((*this_prologue_cache)) | |
9a3c8263 | 703 | return (struct cris_unwind_cache *) (*this_prologue_cache); |
2e4b5889 OF |
704 | |
705 | info = FRAME_OBSTACK_ZALLOC (struct cris_unwind_cache); | |
706 | (*this_prologue_cache) = info; | |
94afd7a6 | 707 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
2e4b5889 OF |
708 | |
709 | /* Zero all fields. */ | |
710 | info->prev_sp = 0; | |
711 | info->base = 0; | |
712 | info->size = 0; | |
713 | info->sp_offset = 0; | |
714 | info->r8_offset = 0; | |
715 | info->uses_frame = 0; | |
716 | info->return_pc = 0; | |
717 | info->leaf_function = 0; | |
718 | ||
719 | /* Prologue analysis does the rest... */ | |
35488783 | 720 | if (tdep->cris_version == 32) |
94afd7a6 | 721 | crisv32_scan_prologue (get_frame_func (this_frame), this_frame, info); |
5114e29d | 722 | else |
94afd7a6 | 723 | cris_scan_prologue (get_frame_func (this_frame), this_frame, info); |
2e4b5889 OF |
724 | |
725 | return info; | |
726 | } | |
727 | ||
728 | /* Given a GDB frame, determine the address of the calling function's | |
729 | frame. This will be used to create a new GDB frame struct. */ | |
730 | ||
731 | static void | |
bd2b40ac | 732 | cris_frame_this_id (frame_info_ptr this_frame, |
2e4b5889 OF |
733 | void **this_prologue_cache, |
734 | struct frame_id *this_id) | |
735 | { | |
736 | struct cris_unwind_cache *info | |
94afd7a6 | 737 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
2e4b5889 OF |
738 | CORE_ADDR base; |
739 | CORE_ADDR func; | |
740 | struct frame_id id; | |
741 | ||
742 | /* The FUNC is easy. */ | |
94afd7a6 | 743 | func = get_frame_func (this_frame); |
2e4b5889 OF |
744 | |
745 | /* Hopefully the prologue analysis either correctly determined the | |
746 | frame's base (which is the SP from the previous frame), or set | |
747 | that base to "NULL". */ | |
748 | base = info->prev_sp; | |
749 | if (base == 0) | |
750 | return; | |
751 | ||
752 | id = frame_id_build (base, func); | |
753 | ||
754 | (*this_id) = id; | |
755 | } | |
756 | ||
94afd7a6 | 757 | static struct value * |
bd2b40ac | 758 | cris_frame_prev_register (frame_info_ptr this_frame, |
94afd7a6 | 759 | void **this_prologue_cache, int regnum) |
2e4b5889 OF |
760 | { |
761 | struct cris_unwind_cache *info | |
94afd7a6 UW |
762 | = cris_frame_unwind_cache (this_frame, this_prologue_cache); |
763 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
2e4b5889 OF |
764 | } |
765 | ||
2e4b5889 OF |
766 | static CORE_ADDR |
767 | cris_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
768 | { | |
769 | /* Align to the size of an instruction (so that they can safely be | |
770 | pushed onto the stack). */ | |
771 | return sp & ~3; | |
772 | } | |
773 | ||
774 | static CORE_ADDR | |
775 | cris_push_dummy_code (struct gdbarch *gdbarch, | |
dda83cd7 SM |
776 | CORE_ADDR sp, CORE_ADDR funaddr, |
777 | struct value **args, int nargs, | |
778 | struct type *value_type, | |
779 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
e4fd649a | 780 | struct regcache *regcache) |
2e4b5889 OF |
781 | { |
782 | /* Allocate space sufficient for a breakpoint. */ | |
783 | sp = (sp - 4) & ~3; | |
784 | /* Store the address of that breakpoint */ | |
785 | *bp_addr = sp; | |
786 | /* CRIS always starts the call at the callee's entry point. */ | |
787 | *real_pc = funaddr; | |
788 | return sp; | |
789 | } | |
790 | ||
791 | static CORE_ADDR | |
7d9b040b | 792 | cris_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
2e4b5889 OF |
793 | struct regcache *regcache, CORE_ADDR bp_addr, |
794 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
795 | function_call_return_method return_method, |
796 | CORE_ADDR struct_addr) | |
2e4b5889 | 797 | { |
e17a4113 | 798 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 OF |
799 | int argreg; |
800 | int argnum; | |
801 | ||
0fecb1a7 | 802 | struct cris_stack_item *si = NULL; |
2e4b5889 | 803 | |
a5f6c8f5 | 804 | /* Push the return address. */ |
2e4b5889 OF |
805 | regcache_cooked_write_unsigned (regcache, SRP_REGNUM, bp_addr); |
806 | ||
807 | /* Are we returning a value using a structure return or a normal value | |
808 | return? struct_addr is the address of the reserved space for the return | |
809 | structure to be written on the stack. */ | |
cf84fa6b AH |
810 | if (return_method == return_method_struct) |
811 | regcache_cooked_write_unsigned (regcache, STR_REGNUM, struct_addr); | |
2e4b5889 OF |
812 | |
813 | /* Now load as many as possible of the first arguments into registers, | |
814 | and push the rest onto the stack. */ | |
815 | argreg = ARG1_REGNUM; | |
2e4b5889 OF |
816 | |
817 | for (argnum = 0; argnum < nargs; argnum++) | |
818 | { | |
819 | int len; | |
948f8e3d | 820 | const gdb_byte *val; |
2e4b5889 OF |
821 | int reg_demand; |
822 | int i; | |
823 | ||
df86565b | 824 | len = value_type (args[argnum])->length (); |
50888e42 | 825 | val = value_contents (args[argnum]).data (); |
2e4b5889 OF |
826 | |
827 | /* How may registers worth of storage do we need for this argument? */ | |
828 | reg_demand = (len / 4) + (len % 4 != 0 ? 1 : 0); | |
dda83cd7 | 829 | |
2e4b5889 | 830 | if (len <= (2 * 4) && (argreg + reg_demand - 1 <= ARG4_REGNUM)) |
dda83cd7 SM |
831 | { |
832 | /* Data passed by value. Fits in available register(s). */ | |
833 | for (i = 0; i < reg_demand; i++) | |
834 | { | |
835 | regcache->cooked_write (argreg, val); | |
836 | argreg++; | |
837 | val += 4; | |
838 | } | |
839 | } | |
2e4b5889 | 840 | else if (len <= (2 * 4) && argreg <= ARG4_REGNUM) |
dda83cd7 SM |
841 | { |
842 | /* Data passed by value. Does not fit in available register(s). | |
843 | Use the register(s) first, then the stack. */ | |
844 | for (i = 0; i < reg_demand; i++) | |
845 | { | |
846 | if (argreg <= ARG4_REGNUM) | |
847 | { | |
848 | regcache->cooked_write (argreg, val); | |
849 | argreg++; | |
850 | val += 4; | |
851 | } | |
852 | else | |
853 | { | |
2e4b5889 OF |
854 | /* Push item for later so that pushed arguments |
855 | come in the right order. */ | |
856 | si = push_stack_item (si, val, 4); | |
dda83cd7 SM |
857 | val += 4; |
858 | } | |
859 | } | |
860 | } | |
2e4b5889 | 861 | else if (len > (2 * 4)) |
dda83cd7 | 862 | { |
f6e56ab3 UW |
863 | /* Data passed by reference. Push copy of data onto stack |
864 | and pass pointer to this copy as argument. */ | |
865 | sp = (sp - len) & ~3; | |
866 | write_memory (sp, val, len); | |
867 | ||
868 | if (argreg <= ARG4_REGNUM) | |
869 | { | |
870 | regcache_cooked_write_unsigned (regcache, argreg, sp); | |
871 | argreg++; | |
872 | } | |
873 | else | |
874 | { | |
875 | gdb_byte buf[4]; | |
e17a4113 | 876 | store_unsigned_integer (buf, 4, byte_order, sp); |
f6e56ab3 UW |
877 | si = push_stack_item (si, buf, 4); |
878 | } | |
dda83cd7 | 879 | } |
2e4b5889 | 880 | else |
dda83cd7 SM |
881 | { |
882 | /* Data passed by value. No available registers. Put it on | |
883 | the stack. */ | |
2e4b5889 | 884 | si = push_stack_item (si, val, len); |
dda83cd7 | 885 | } |
2e4b5889 OF |
886 | } |
887 | ||
888 | while (si) | |
889 | { | |
890 | /* fp_arg must be word-aligned (i.e., don't += len) to match | |
891 | the function prologue. */ | |
892 | sp = (sp - si->len) & ~3; | |
893 | write_memory (sp, si->data, si->len); | |
894 | si = pop_stack_item (si); | |
895 | } | |
896 | ||
897 | /* Finally, update the SP register. */ | |
7fbe2eba | 898 | regcache_cooked_write_unsigned (regcache, gdbarch_sp_regnum (gdbarch), sp); |
2e4b5889 OF |
899 | |
900 | return sp; | |
901 | } | |
902 | ||
e2a2a3e8 OF |
903 | static const struct frame_unwind cris_frame_unwind = |
904 | { | |
a154d838 | 905 | "cris prologue", |
2e4b5889 | 906 | NORMAL_FRAME, |
8fbca658 | 907 | default_frame_unwind_stop_reason, |
2e4b5889 | 908 | cris_frame_this_id, |
94afd7a6 UW |
909 | cris_frame_prev_register, |
910 | NULL, | |
911 | default_frame_sniffer | |
2e4b5889 OF |
912 | }; |
913 | ||
2e4b5889 | 914 | static CORE_ADDR |
bd2b40ac | 915 | cris_frame_base_address (frame_info_ptr this_frame, void **this_cache) |
2e4b5889 OF |
916 | { |
917 | struct cris_unwind_cache *info | |
94afd7a6 | 918 | = cris_frame_unwind_cache (this_frame, this_cache); |
2e4b5889 OF |
919 | return info->base; |
920 | } | |
921 | ||
e2a2a3e8 OF |
922 | static const struct frame_base cris_frame_base = |
923 | { | |
2e4b5889 OF |
924 | &cris_frame_unwind, |
925 | cris_frame_base_address, | |
926 | cris_frame_base_address, | |
927 | cris_frame_base_address | |
928 | }; | |
929 | ||
29134980 OF |
930 | /* Frames information. The definition of the struct frame_info is |
931 | ||
932 | CORE_ADDR frame | |
933 | CORE_ADDR pc | |
5a203e44 | 934 | enum frame_type type; |
29134980 OF |
935 | CORE_ADDR return_pc |
936 | int leaf_function | |
937 | ||
938 | If the compilation option -fno-omit-frame-pointer is present the | |
939 | variable frame will be set to the content of R8 which is the frame | |
940 | pointer register. | |
941 | ||
942 | The variable pc contains the address where execution is performed | |
943 | in the present frame. The innermost frame contains the current content | |
944 | of the register PC. All other frames contain the content of the | |
945 | register PC in the next frame. | |
946 | ||
5a203e44 AC |
947 | The variable `type' indicates the frame's type: normal, SIGTRAMP |
948 | (associated with a signal handler), dummy (associated with a dummy | |
949 | frame). | |
29134980 OF |
950 | |
951 | The variable return_pc contains the address where execution should be | |
952 | resumed when the present frame has finished, the return address. | |
953 | ||
954 | The variable leaf_function is 1 if the return address is in the register | |
955 | SRP, and 0 if it is on the stack. | |
956 | ||
957 | Prologue instructions C-code. | |
958 | The prologue may consist of (-fno-omit-frame-pointer) | |
959 | 1) 2) | |
960 | push srp | |
961 | push r8 push r8 | |
962 | move.d sp,r8 move.d sp,r8 | |
963 | subq X,sp subq X,sp | |
964 | movem rY,[sp] movem rY,[sp] | |
965 | move.S rZ,[r8-U] move.S rZ,[r8-U] | |
966 | ||
967 | where 1 is a non-terminal function, and 2 is a leaf-function. | |
968 | ||
969 | Note that this assumption is extremely brittle, and will break at the | |
970 | slightest change in GCC's prologue. | |
971 | ||
972 | If local variables are declared or register contents are saved on stack | |
973 | the subq-instruction will be present with X as the number of bytes | |
974 | needed for storage. The reshuffle with respect to r8 may be performed | |
975 | with any size S (b, w, d) and any of the general registers Z={0..13}. | |
0963b4bd | 976 | The offset U should be representable by a signed 8-bit value in all cases. |
29134980 OF |
977 | Thus, the prefix word is assumed to be immediate byte offset mode followed |
978 | by another word containing the instruction. | |
979 | ||
980 | Degenerate cases: | |
981 | 3) | |
982 | push r8 | |
983 | move.d sp,r8 | |
984 | move.d r8,sp | |
985 | pop r8 | |
986 | ||
987 | Prologue instructions C++-code. | |
988 | Case 1) and 2) in the C-code may be followed by | |
989 | ||
990 | move.d r10,rS ; this | |
991 | move.d r11,rT ; P1 | |
992 | move.d r12,rU ; P2 | |
993 | move.d r13,rV ; P3 | |
994 | move.S [r8+U],rZ ; P4 | |
995 | ||
0963b4bd | 996 | if any of the call parameters are stored. The host expects these |
29134980 OF |
997 | instructions to be executed in order to get the call parameters right. */ |
998 | ||
999 | /* Examine the prologue of a function. The variable ip is the address of | |
1000 | the first instruction of the prologue. The variable limit is the address | |
1001 | of the first instruction after the prologue. The variable fi contains the | |
1002 | information in struct frame_info. The variable frameless_p controls whether | |
1003 | the entire prologue is examined (0) or just enough instructions to | |
1004 | determine that it is a prologue (1). */ | |
1005 | ||
a78f21af | 1006 | static CORE_ADDR |
bd2b40ac | 1007 | cris_scan_prologue (CORE_ADDR pc, frame_info_ptr this_frame, |
2e4b5889 | 1008 | struct cris_unwind_cache *info) |
29134980 | 1009 | { |
94afd7a6 | 1010 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
e17a4113 UW |
1011 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1012 | ||
29134980 OF |
1013 | /* Present instruction. */ |
1014 | unsigned short insn; | |
1015 | ||
1016 | /* Next instruction, lookahead. */ | |
1017 | unsigned short insn_next; | |
1018 | int regno; | |
1019 | ||
29134980 OF |
1020 | /* Number of byte on stack used for local variables and movem. */ |
1021 | int val; | |
1022 | ||
1023 | /* Highest register number in a movem. */ | |
1024 | int regsave; | |
1025 | ||
1026 | /* move.d r<source_register>,rS */ | |
1027 | short source_register; | |
1028 | ||
2e4b5889 OF |
1029 | /* Scan limit. */ |
1030 | int limit; | |
29134980 | 1031 | |
2e4b5889 OF |
1032 | /* This frame is with respect to a leaf until a push srp is found. */ |
1033 | if (info) | |
1034 | { | |
1035 | info->leaf_function = 1; | |
1036 | } | |
29134980 OF |
1037 | |
1038 | /* Assume nothing on stack. */ | |
1039 | val = 0; | |
1040 | regsave = -1; | |
1041 | ||
94afd7a6 | 1042 | /* If we were called without a this_frame, that means we were called |
2e4b5889 OF |
1043 | from cris_skip_prologue which already tried to find the end of the |
1044 | prologue through the symbol information. 64 instructions past current | |
1045 | pc is arbitrarily chosen, but at least it means we'll stop eventually. */ | |
94afd7a6 | 1046 | limit = this_frame ? get_frame_pc (this_frame) : pc + 64; |
29134980 | 1047 | |
29134980 | 1048 | /* Find the prologue instructions. */ |
a5f6c8f5 | 1049 | while (pc > 0 && pc < limit) |
29134980 | 1050 | { |
e17a4113 | 1051 | insn = read_memory_unsigned_integer (pc, 2, byte_order); |
2e4b5889 | 1052 | pc += 2; |
29134980 | 1053 | if (insn == 0xE1FC) |
dda83cd7 SM |
1054 | { |
1055 | /* push <reg> 32 bit instruction. */ | |
1056 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); | |
1057 | pc += 2; | |
1058 | regno = cris_get_operand2 (insn_next); | |
2e4b5889 OF |
1059 | if (info) |
1060 | { | |
1061 | info->sp_offset += 4; | |
1062 | } | |
dda83cd7 SM |
1063 | /* This check, meant to recognize srp, used to be regno == |
1064 | (SRP_REGNUM - NUM_GENREGS), but that covers r11 also. */ | |
1065 | if (insn_next == 0xBE7E) | |
1066 | { | |
2e4b5889 OF |
1067 | if (info) |
1068 | { | |
1069 | info->leaf_function = 0; | |
1070 | } | |
dda83cd7 | 1071 | } |
b4206d25 | 1072 | else if (insn_next == 0x8FEE) |
dda83cd7 | 1073 | { |
b4206d25 OF |
1074 | /* push $r8 */ |
1075 | if (info) | |
1076 | { | |
1077 | info->r8_offset = info->sp_offset; | |
1078 | } | |
dda83cd7 SM |
1079 | } |
1080 | } | |
29134980 | 1081 | else if (insn == 0x866E) |
dda83cd7 SM |
1082 | { |
1083 | /* move.d sp,r8 */ | |
2e4b5889 OF |
1084 | if (info) |
1085 | { | |
1086 | info->uses_frame = 1; | |
2e4b5889 | 1087 | } |
dda83cd7 SM |
1088 | continue; |
1089 | } | |
7fbe2eba | 1090 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
dda83cd7 SM |
1091 | && cris_get_mode (insn) == 0x0000 |
1092 | && cris_get_opcode (insn) == 0x000A) | |
1093 | { | |
1094 | /* subq <val>,sp */ | |
2e4b5889 OF |
1095 | if (info) |
1096 | { | |
1097 | info->sp_offset += cris_get_quick_value (insn); | |
1098 | } | |
dda83cd7 | 1099 | } |
29134980 | 1100 | else if (cris_get_mode (insn) == 0x0002 |
dda83cd7 SM |
1101 | && cris_get_opcode (insn) == 0x000F |
1102 | && cris_get_size (insn) == 0x0003 | |
1103 | && cris_get_operand1 (insn) == gdbarch_sp_regnum (gdbarch)) | |
1104 | { | |
1105 | /* movem r<regsave>,[sp] */ | |
1106 | regsave = cris_get_operand2 (insn); | |
1107 | } | |
7fbe2eba | 1108 | else if (cris_get_operand2 (insn) == gdbarch_sp_regnum (gdbarch) |
dda83cd7 SM |
1109 | && ((insn & 0x0F00) >> 8) == 0x0001 |
1110 | && (cris_get_signed_offset (insn) < 0)) | |
1111 | { | |
1112 | /* Immediate byte offset addressing prefix word with sp as base | |
1113 | register. Used for CRIS v8 i.e. ETRAX 100 and newer if <val> | |
1114 | is between 64 and 128. | |
1115 | movem r<regsave>,[sp=sp-<val>] */ | |
2e4b5889 OF |
1116 | if (info) |
1117 | { | |
1118 | info->sp_offset += -cris_get_signed_offset (insn); | |
1119 | } | |
e17a4113 | 1120 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
dda83cd7 SM |
1121 | pc += 2; |
1122 | if (cris_get_mode (insn_next) == PREFIX_ASSIGN_MODE | |
1123 | && cris_get_opcode (insn_next) == 0x000F | |
1124 | && cris_get_size (insn_next) == 0x0003 | |
1125 | && cris_get_operand1 (insn_next) == gdbarch_sp_regnum | |
7fbe2eba | 1126 | (gdbarch)) |
dda83cd7 SM |
1127 | { |
1128 | regsave = cris_get_operand2 (insn_next); | |
1129 | } | |
1130 | else | |
1131 | { | |
1132 | /* The prologue ended before the limit was reached. */ | |
1133 | pc -= 4; | |
1134 | break; | |
1135 | } | |
1136 | } | |
29134980 | 1137 | else if (cris_get_mode (insn) == 0x0001 |
dda83cd7 SM |
1138 | && cris_get_opcode (insn) == 0x0009 |
1139 | && cris_get_size (insn) == 0x0002) | |
1140 | { | |
1141 | /* move.d r<10..13>,r<0..15> */ | |
1142 | source_register = cris_get_operand1 (insn); | |
1143 | ||
1144 | /* FIXME? In the glibc solibs, the prologue might contain something | |
1145 | like (this example taken from relocate_doit): | |
1146 | move.d $pc,$r0 | |
1147 | sub.d 0xfffef426,$r0 | |
1148 | which isn't covered by the source_register check below. Question | |
1149 | is whether to add a check for this combo, or make better use of | |
1150 | the limit variable instead. */ | |
1151 | if (source_register < ARG1_REGNUM || source_register > ARG4_REGNUM) | |
1152 | { | |
1153 | /* The prologue ended before the limit was reached. */ | |
1154 | pc -= 2; | |
1155 | break; | |
1156 | } | |
1157 | } | |
2e4b5889 | 1158 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
dda83cd7 SM |
1159 | /* The size is a fixed-size. */ |
1160 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1161 | /* A negative offset. */ | |
1162 | && (cris_get_signed_offset (insn) < 0)) | |
1163 | { | |
1164 | /* move.S rZ,[r8-U] (?) */ | |
1165 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); | |
1166 | pc += 2; | |
1167 | regno = cris_get_operand2 (insn_next); | |
1168 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) | |
1169 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1170 | && cris_get_opcode (insn_next) == 0x000F) | |
1171 | { | |
1172 | /* move.S rZ,[r8-U] */ | |
1173 | continue; | |
1174 | } | |
1175 | else | |
1176 | { | |
1177 | /* The prologue ended before the limit was reached. */ | |
1178 | pc -= 4; | |
1179 | break; | |
1180 | } | |
1181 | } | |
2e4b5889 | 1182 | else if (cris_get_operand2 (insn) == CRIS_FP_REGNUM |
dda83cd7 SM |
1183 | /* The size is a fixed-size. */ |
1184 | && ((insn & 0x0F00) >> 8) == 0x0001 | |
1185 | /* A positive offset. */ | |
1186 | && (cris_get_signed_offset (insn) > 0)) | |
1187 | { | |
1188 | /* move.S [r8+U],rZ (?) */ | |
e17a4113 | 1189 | insn_next = read_memory_unsigned_integer (pc, 2, byte_order); |
dda83cd7 SM |
1190 | pc += 2; |
1191 | regno = cris_get_operand2 (insn_next); | |
1192 | if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) | |
1193 | && cris_get_mode (insn_next) == PREFIX_OFFSET_MODE | |
1194 | && cris_get_opcode (insn_next) == 0x0009 | |
1195 | && cris_get_operand1 (insn_next) == regno) | |
1196 | { | |
1197 | /* move.S [r8+U],rZ */ | |
1198 | continue; | |
1199 | } | |
1200 | else | |
1201 | { | |
1202 | /* The prologue ended before the limit was reached. */ | |
1203 | pc -= 4; | |
1204 | break; | |
1205 | } | |
1206 | } | |
29134980 | 1207 | else |
dda83cd7 SM |
1208 | { |
1209 | /* The prologue ended before the limit was reached. */ | |
1210 | pc -= 2; | |
1211 | break; | |
1212 | } | |
29134980 | 1213 | } |
29134980 | 1214 | |
94afd7a6 | 1215 | /* We only want to know the end of the prologue when this_frame and info |
2e4b5889 | 1216 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1217 | if (this_frame == NULL && info == NULL) |
2e4b5889 OF |
1218 | { |
1219 | return pc; | |
1220 | } | |
29134980 | 1221 | |
2e4b5889 OF |
1222 | info->size = info->sp_offset; |
1223 | ||
1224 | /* Compute the previous frame's stack pointer (which is also the | |
1225 | frame's ID's stack address), and this frame's base pointer. */ | |
1226 | if (info->uses_frame) | |
29134980 | 1227 | { |
2e4b5889 OF |
1228 | ULONGEST this_base; |
1229 | /* The SP was moved to the FP. This indicates that a new frame | |
dda83cd7 SM |
1230 | was created. Get THIS frame's FP value by unwinding it from |
1231 | the next frame. */ | |
94afd7a6 | 1232 | this_base = get_frame_register_unsigned (this_frame, CRIS_FP_REGNUM); |
2e4b5889 | 1233 | info->base = this_base; |
098caef4 | 1234 | info->saved_regs[CRIS_FP_REGNUM].set_addr (info->base); |
b4206d25 | 1235 | |
2e4b5889 | 1236 | /* The FP points at the last saved register. Adjust the FP back |
dda83cd7 | 1237 | to before the first saved register giving the SP. */ |
2e4b5889 OF |
1238 | info->prev_sp = info->base + info->r8_offset; |
1239 | } | |
1240 | else | |
1241 | { | |
1242 | ULONGEST this_base; | |
1243 | /* Assume that the FP is this frame's SP but with that pushed | |
dda83cd7 | 1244 | stack space added back. */ |
94afd7a6 UW |
1245 | this_base = get_frame_register_unsigned (this_frame, |
1246 | gdbarch_sp_regnum (gdbarch)); | |
2e4b5889 OF |
1247 | info->base = this_base; |
1248 | info->prev_sp = info->base + info->size; | |
1249 | } | |
29134980 | 1250 | |
2e4b5889 OF |
1251 | /* Calculate the addresses for the saved registers on the stack. */ |
1252 | /* FIXME: The address calculation should really be done on the fly while | |
1253 | we're analyzing the prologue (we only hold one regsave value as it is | |
1254 | now). */ | |
1255 | val = info->sp_offset; | |
1256 | ||
1257 | for (regno = regsave; regno >= 0; regno--) | |
1258 | { | |
098caef4 | 1259 | info->saved_regs[regno].set_addr (info->base + info->r8_offset - val); |
2e4b5889 OF |
1260 | val -= 4; |
1261 | } | |
1262 | ||
1263 | /* The previous frame's SP needed to be computed. Save the computed | |
1264 | value. */ | |
a9a87d35 | 1265 | info->saved_regs[gdbarch_sp_regnum (gdbarch)].set_value (info->prev_sp); |
2e4b5889 OF |
1266 | |
1267 | if (!info->leaf_function) | |
1268 | { | |
b4206d25 OF |
1269 | /* SRP saved on the stack. But where? */ |
1270 | if (info->r8_offset == 0) | |
1271 | { | |
1272 | /* R8 not pushed yet. */ | |
098caef4 | 1273 | info->saved_regs[SRP_REGNUM].set_addr (info->base); |
b4206d25 OF |
1274 | } |
1275 | else | |
1276 | { | |
1277 | /* R8 pushed, but SP may or may not be moved to R8 yet. */ | |
098caef4 | 1278 | info->saved_regs[SRP_REGNUM].set_addr (info->base + 4); |
b4206d25 | 1279 | } |
29134980 | 1280 | } |
2e4b5889 OF |
1281 | |
1282 | /* The PC is found in SRP (the actual register or located on the stack). */ | |
7fbe2eba | 1283 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1284 | = info->saved_regs[SRP_REGNUM]; |
2e4b5889 OF |
1285 | |
1286 | return pc; | |
29134980 OF |
1287 | } |
1288 | ||
5114e29d | 1289 | static CORE_ADDR |
bd2b40ac | 1290 | crisv32_scan_prologue (CORE_ADDR pc, frame_info_ptr this_frame, |
5114e29d OF |
1291 | struct cris_unwind_cache *info) |
1292 | { | |
94afd7a6 | 1293 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
5114e29d OF |
1294 | ULONGEST this_base; |
1295 | ||
1296 | /* Unlike the CRISv10 prologue scanner (cris_scan_prologue), this is not | |
1297 | meant to be a full-fledged prologue scanner. It is only needed for | |
1298 | the cases where we end up in code always lacking DWARF-2 CFI, notably: | |
1299 | ||
1300 | * PLT stubs (library calls) | |
1301 | * call dummys | |
1302 | * signal trampolines | |
1303 | ||
1304 | For those cases, it is assumed that there is no actual prologue; that | |
1305 | the stack pointer is not adjusted, and (as a consequence) the return | |
1306 | address is not pushed onto the stack. */ | |
1307 | ||
94afd7a6 | 1308 | /* We only want to know the end of the prologue when this_frame and info |
5114e29d | 1309 | are NULL (called from cris_skip_prologue i.e.). */ |
94afd7a6 | 1310 | if (this_frame == NULL && info == NULL) |
5114e29d OF |
1311 | { |
1312 | return pc; | |
1313 | } | |
1314 | ||
1315 | /* The SP is assumed to be unaltered. */ | |
94afd7a6 UW |
1316 | this_base = get_frame_register_unsigned (this_frame, |
1317 | gdbarch_sp_regnum (gdbarch)); | |
5114e29d OF |
1318 | info->base = this_base; |
1319 | info->prev_sp = this_base; | |
1320 | ||
1321 | /* The PC is assumed to be found in SRP. */ | |
7fbe2eba | 1322 | info->saved_regs[gdbarch_pc_regnum (gdbarch)] |
3e8c568d | 1323 | = info->saved_regs[SRP_REGNUM]; |
5114e29d OF |
1324 | |
1325 | return pc; | |
1326 | } | |
1327 | ||
29134980 OF |
1328 | /* Advance pc beyond any function entry prologue instructions at pc |
1329 | to reach some "real" code. */ | |
1330 | ||
29134980 OF |
1331 | /* Given a PC value corresponding to the start of a function, return the PC |
1332 | of the first instruction after the function prologue. */ | |
1333 | ||
a78f21af | 1334 | static CORE_ADDR |
6093d2eb | 1335 | cris_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
29134980 | 1336 | { |
08106042 | 1337 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
2e4b5889 OF |
1338 | CORE_ADDR func_addr, func_end; |
1339 | struct symtab_and_line sal; | |
29134980 OF |
1340 | CORE_ADDR pc_after_prologue; |
1341 | ||
2e4b5889 OF |
1342 | /* If we have line debugging information, then the end of the prologue |
1343 | should the first assembly instruction of the first source line. */ | |
1344 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
1345 | { | |
1346 | sal = find_pc_line (func_addr, 0); | |
1347 | if (sal.end > 0 && sal.end < func_end) | |
1348 | return sal.end; | |
1349 | } | |
29134980 | 1350 | |
35488783 | 1351 | if (tdep->cris_version == 32) |
5114e29d OF |
1352 | pc_after_prologue = crisv32_scan_prologue (pc, NULL, NULL); |
1353 | else | |
1354 | pc_after_prologue = cris_scan_prologue (pc, NULL, NULL); | |
1355 | ||
29134980 OF |
1356 | return pc_after_prologue; |
1357 | } | |
1358 | ||
cd6c3b4f YQ |
1359 | /* Implement the breakpoint_kind_from_pc gdbarch method. */ |
1360 | ||
d19280ad YQ |
1361 | static int |
1362 | cris_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) | |
1363 | { | |
1364 | return 2; | |
1365 | } | |
29134980 | 1366 | |
cd6c3b4f YQ |
1367 | /* Implement the sw_breakpoint_from_kind gdbarch method. */ |
1368 | ||
d19280ad YQ |
1369 | static const gdb_byte * |
1370 | cris_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) | |
29134980 | 1371 | { |
08106042 | 1372 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
0e6bdb31 OF |
1373 | static unsigned char break8_insn[] = {0x38, 0xe9}; |
1374 | static unsigned char break15_insn[] = {0x3f, 0xe9}; | |
d19280ad YQ |
1375 | |
1376 | *size = kind; | |
29134980 | 1377 | |
35488783 | 1378 | if (tdep->cris_mode == cris_mode_guru) |
0e6bdb31 OF |
1379 | return break15_insn; |
1380 | else | |
1381 | return break8_insn; | |
29134980 OF |
1382 | } |
1383 | ||
29134980 OF |
1384 | /* Returns 1 if spec_reg is applicable to the current gdbarch's CRIS version, |
1385 | 0 otherwise. */ | |
1386 | ||
a78f21af | 1387 | static int |
35488783 UW |
1388 | cris_spec_reg_applicable (struct gdbarch *gdbarch, |
1389 | struct cris_spec_reg spec_reg) | |
29134980 | 1390 | { |
08106042 | 1391 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
e4286e57 | 1392 | unsigned int version = tdep->cris_version; |
29134980 OF |
1393 | |
1394 | switch (spec_reg.applicable_version) | |
1395 | { | |
1396 | case cris_ver_version_all: | |
1397 | return 1; | |
1398 | case cris_ver_warning: | |
1399 | /* Indeterminate/obsolete. */ | |
1400 | return 0; | |
29134980 | 1401 | case cris_ver_v0_3: |
b020ff80 | 1402 | return in_inclusive_range (version, 0U, 3U); |
29134980 OF |
1403 | case cris_ver_v3p: |
1404 | return (version >= 3); | |
1405 | case cris_ver_v8: | |
b020ff80 | 1406 | return in_inclusive_range (version, 8U, 9U); |
29134980 OF |
1407 | case cris_ver_v8p: |
1408 | return (version >= 8); | |
c600d464 | 1409 | case cris_ver_v0_10: |
b020ff80 | 1410 | return in_inclusive_range (version, 0U, 10U); |
c600d464 | 1411 | case cris_ver_v3_10: |
b020ff80 | 1412 | return in_inclusive_range (version, 3U, 10U); |
c600d464 | 1413 | case cris_ver_v8_10: |
b020ff80 | 1414 | return in_inclusive_range (version, 8U, 10U); |
c600d464 OF |
1415 | case cris_ver_v10: |
1416 | return (version == 10); | |
29134980 OF |
1417 | case cris_ver_v10p: |
1418 | return (version >= 10); | |
c600d464 OF |
1419 | case cris_ver_v32p: |
1420 | return (version >= 32); | |
29134980 OF |
1421 | default: |
1422 | /* Invalid cris version. */ | |
1423 | return 0; | |
1424 | } | |
1425 | } | |
1426 | ||
1d94326f AC |
1427 | /* Returns the register size in unit byte. Returns 0 for an unimplemented |
1428 | register, -1 for an invalid register. */ | |
1429 | ||
1430 | static int | |
be8626e0 | 1431 | cris_register_size (struct gdbarch *gdbarch, int regno) |
1d94326f AC |
1432 | { |
1433 | int i; | |
1434 | int spec_regno; | |
1435 | ||
1436 | if (regno >= 0 && regno < NUM_GENREGS) | |
1437 | { | |
1438 | /* General registers (R0 - R15) are 32 bits. */ | |
1439 | return 4; | |
1440 | } | |
c600d464 | 1441 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) |
1d94326f AC |
1442 | { |
1443 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
dda83cd7 | 1444 | Adjust regno accordingly. */ |
1d94326f AC |
1445 | spec_regno = regno - NUM_GENREGS; |
1446 | ||
c600d464 | 1447 | for (i = 0; cris_spec_regs[i].name != NULL; i++) |
dda83cd7 SM |
1448 | { |
1449 | if (cris_spec_regs[i].number == spec_regno | |
1450 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) | |
1451 | /* Go with the first applicable register. */ | |
1452 | return cris_spec_regs[i].reg_size; | |
1453 | } | |
1d94326f AC |
1454 | /* Special register not applicable to this CRIS version. */ |
1455 | return 0; | |
1456 | } | |
be8626e0 MD |
1457 | else if (regno >= gdbarch_pc_regnum (gdbarch) |
1458 | && regno < gdbarch_num_regs (gdbarch)) | |
1d94326f | 1459 | { |
c600d464 OF |
1460 | /* This will apply to CRISv32 only where there are additional registers |
1461 | after the special registers (pseudo PC and support registers). */ | |
1462 | return 4; | |
1d94326f | 1463 | } |
c600d464 OF |
1464 | |
1465 | ||
1466 | return -1; | |
1d94326f AC |
1467 | } |
1468 | ||
29134980 OF |
1469 | /* Nonzero if regno should not be fetched from the target. This is the case |
1470 | for unimplemented (size 0) and non-existant registers. */ | |
1471 | ||
a78f21af | 1472 | static int |
64a3914f | 1473 | cris_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
29134980 | 1474 | { |
64a3914f | 1475 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda83cd7 | 1476 | || (cris_register_size (gdbarch, regno) == 0)); |
29134980 OF |
1477 | } |
1478 | ||
1479 | /* Nonzero if regno should not be written to the target, for various | |
1480 | reasons. */ | |
1481 | ||
a78f21af | 1482 | static int |
64a3914f | 1483 | cris_cannot_store_register (struct gdbarch *gdbarch, int regno) |
29134980 OF |
1484 | { |
1485 | /* There are three kinds of registers we refuse to write to. | |
1486 | 1. Those that not implemented. | |
1487 | 2. Those that are read-only (depends on the processor mode). | |
0963b4bd | 1488 | 3. Those registers to which a write has no effect. */ |
29134980 | 1489 | |
f57d151a | 1490 | if (regno < 0 |
64a3914f | 1491 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1492 | || cris_register_size (gdbarch, regno) == 0) |
29134980 OF |
1493 | /* Not implemented. */ |
1494 | return 1; | |
1495 | ||
1496 | else if (regno == VR_REGNUM) | |
1497 | /* Read-only. */ | |
1498 | return 1; | |
1499 | ||
1500 | else if (regno == P0_REGNUM || regno == P4_REGNUM || regno == P8_REGNUM) | |
1501 | /* Writing has no effect. */ | |
1502 | return 1; | |
1503 | ||
a5f6c8f5 OF |
1504 | /* IBR, BAR, BRP and IRP are read-only in user mode. Let the debug |
1505 | agent decide whether they are writable. */ | |
29134980 OF |
1506 | |
1507 | return 0; | |
1508 | } | |
1509 | ||
c600d464 OF |
1510 | /* Nonzero if regno should not be fetched from the target. This is the case |
1511 | for unimplemented (size 0) and non-existant registers. */ | |
1512 | ||
1513 | static int | |
64a3914f | 1514 | crisv32_cannot_fetch_register (struct gdbarch *gdbarch, int regno) |
c600d464 | 1515 | { |
64a3914f | 1516 | return ((regno < 0 || regno >= gdbarch_num_regs (gdbarch)) |
dda83cd7 | 1517 | || (cris_register_size (gdbarch, regno) == 0)); |
c600d464 OF |
1518 | } |
1519 | ||
1520 | /* Nonzero if regno should not be written to the target, for various | |
1521 | reasons. */ | |
1522 | ||
1523 | static int | |
64a3914f | 1524 | crisv32_cannot_store_register (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1525 | { |
1526 | /* There are three kinds of registers we refuse to write to. | |
1527 | 1. Those that not implemented. | |
1528 | 2. Those that are read-only (depends on the processor mode). | |
0963b4bd | 1529 | 3. Those registers to which a write has no effect. */ |
c600d464 | 1530 | |
f57d151a | 1531 | if (regno < 0 |
64a3914f | 1532 | || regno >= gdbarch_num_regs (gdbarch) |
be8626e0 | 1533 | || cris_register_size (gdbarch, regno) == 0) |
c600d464 OF |
1534 | /* Not implemented. */ |
1535 | return 1; | |
1536 | ||
1537 | else if (regno == VR_REGNUM) | |
1538 | /* Read-only. */ | |
1539 | return 1; | |
1540 | ||
1541 | else if (regno == BZ_REGNUM || regno == WZ_REGNUM || regno == DZ_REGNUM) | |
1542 | /* Writing has no effect. */ | |
1543 | return 1; | |
1544 | ||
1545 | /* Many special registers are read-only in user mode. Let the debug | |
1546 | agent decide whether they are writable. */ | |
1547 | ||
1548 | return 0; | |
1549 | } | |
1550 | ||
29134980 OF |
1551 | /* Return the GDB type (defined in gdbtypes.c) for the "standard" data type |
1552 | of data in register regno. */ | |
1553 | ||
a78f21af | 1554 | static struct type * |
c1d546cd | 1555 | cris_register_type (struct gdbarch *gdbarch, int regno) |
29134980 | 1556 | { |
7fbe2eba | 1557 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1558 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1559 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1560 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1561 | return builtin_type (gdbarch)->builtin_data_ptr; |
7fbe2eba | 1562 | else if ((regno >= 0 && regno < gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 OF |
1563 | || (regno >= MOF_REGNUM && regno <= USP_REGNUM)) |
1564 | /* Note: R8 taken care of previous clause. */ | |
df4df182 | 1565 | return builtin_type (gdbarch)->builtin_uint32; |
a5f6c8f5 | 1566 | else if (regno >= P4_REGNUM && regno <= CCR_REGNUM) |
df4df182 | 1567 | return builtin_type (gdbarch)->builtin_uint16; |
a5f6c8f5 | 1568 | else if (regno >= P0_REGNUM && regno <= VR_REGNUM) |
df4df182 | 1569 | return builtin_type (gdbarch)->builtin_uint8; |
29134980 | 1570 | else |
a5f6c8f5 | 1571 | /* Invalid (unimplemented) register. */ |
df4df182 | 1572 | return builtin_type (gdbarch)->builtin_int0; |
29134980 OF |
1573 | } |
1574 | ||
c600d464 OF |
1575 | static struct type * |
1576 | crisv32_register_type (struct gdbarch *gdbarch, int regno) | |
1577 | { | |
7fbe2eba | 1578 | if (regno == gdbarch_pc_regnum (gdbarch)) |
0dfff4cb | 1579 | return builtin_type (gdbarch)->builtin_func_ptr; |
7fbe2eba | 1580 | else if (regno == gdbarch_sp_regnum (gdbarch) |
3e8c568d | 1581 | || regno == CRIS_FP_REGNUM) |
0dfff4cb | 1582 | return builtin_type (gdbarch)->builtin_data_ptr; |
c600d464 OF |
1583 | else if ((regno >= 0 && regno <= ACR_REGNUM) |
1584 | || (regno >= EXS_REGNUM && regno <= SPC_REGNUM) | |
1585 | || (regno == PID_REGNUM) | |
1586 | || (regno >= S0_REGNUM && regno <= S15_REGNUM)) | |
1587 | /* Note: R8 and SP taken care of by previous clause. */ | |
df4df182 | 1588 | return builtin_type (gdbarch)->builtin_uint32; |
c600d464 | 1589 | else if (regno == WZ_REGNUM) |
df4df182 | 1590 | return builtin_type (gdbarch)->builtin_uint16; |
c600d464 | 1591 | else if (regno == BZ_REGNUM || regno == VR_REGNUM || regno == SRS_REGNUM) |
df4df182 | 1592 | return builtin_type (gdbarch)->builtin_uint8; |
c600d464 OF |
1593 | else |
1594 | { | |
1595 | /* Invalid (unimplemented) register. Should not happen as there are | |
1596 | no unimplemented CRISv32 registers. */ | |
8a3fe4f8 | 1597 | warning (_("crisv32_register_type: unknown regno %d"), regno); |
df4df182 | 1598 | return builtin_type (gdbarch)->builtin_int0; |
c600d464 OF |
1599 | } |
1600 | } | |
1601 | ||
2e4b5889 OF |
1602 | /* Stores a function return value of type type, where valbuf is the address |
1603 | of the value to be stored. */ | |
29134980 | 1604 | |
2e4b5889 | 1605 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ |
29134980 | 1606 | |
2e4b5889 OF |
1607 | static void |
1608 | cris_store_return_value (struct type *type, struct regcache *regcache, | |
948f8e3d | 1609 | const gdb_byte *valbuf) |
29134980 | 1610 | { |
ac7936df | 1611 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1612 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 | 1613 | ULONGEST val; |
df86565b | 1614 | int len = type->length (); |
29134980 | 1615 | |
bad43aa5 | 1616 | if (len <= 4) |
29134980 | 1617 | { |
2e4b5889 | 1618 | /* Put the return value in R10. */ |
bad43aa5 | 1619 | val = extract_unsigned_integer (valbuf, len, byte_order); |
2e4b5889 | 1620 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
29134980 | 1621 | } |
bad43aa5 | 1622 | else if (len <= 8) |
29134980 | 1623 | { |
2e4b5889 | 1624 | /* Put the return value in R10 and R11. */ |
e17a4113 | 1625 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
2e4b5889 | 1626 | regcache_cooked_write_unsigned (regcache, ARG1_REGNUM, val); |
948f8e3d | 1627 | val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
2e4b5889 | 1628 | regcache_cooked_write_unsigned (regcache, ARG2_REGNUM, val); |
29134980 | 1629 | } |
2e4b5889 | 1630 | else |
8a3fe4f8 | 1631 | error (_("cris_store_return_value: type length too large.")); |
29134980 OF |
1632 | } |
1633 | ||
0963b4bd MS |
1634 | /* Return the name of register regno as a string. Return NULL for an |
1635 | invalid or unimplemented register. */ | |
29134980 | 1636 | |
c600d464 | 1637 | static const char * |
35488783 | 1638 | cris_special_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 OF |
1639 | { |
1640 | int spec_regno; | |
1641 | int i; | |
1642 | ||
1643 | /* Special register (R16 - R31). cris_spec_regs is zero-based. | |
1644 | Adjust regno accordingly. */ | |
1645 | spec_regno = regno - NUM_GENREGS; | |
1646 | ||
1647 | /* Assume nothing about the layout of the cris_spec_regs struct | |
1648 | when searching. */ | |
1649 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1650 | { | |
1651 | if (cris_spec_regs[i].number == spec_regno | |
35488783 | 1652 | && cris_spec_reg_applicable (gdbarch, cris_spec_regs[i])) |
c600d464 OF |
1653 | /* Go with the first applicable register. */ |
1654 | return cris_spec_regs[i].name; | |
1655 | } | |
1656 | /* Special register not applicable to this CRIS version. */ | |
9a972b54 | 1657 | return ""; |
c600d464 OF |
1658 | } |
1659 | ||
2e4b5889 | 1660 | static const char * |
d93859e2 | 1661 | cris_register_name (struct gdbarch *gdbarch, int regno) |
2e4b5889 | 1662 | { |
a121b7c1 | 1663 | static const char *cris_genreg_names[] = |
2e4b5889 OF |
1664 | { "r0", "r1", "r2", "r3", \ |
1665 | "r4", "r5", "r6", "r7", \ | |
1666 | "r8", "r9", "r10", "r11", \ | |
1667 | "r12", "r13", "sp", "pc" }; | |
29134980 | 1668 | |
9b9e61c7 | 1669 | if (regno < NUM_GENREGS) |
29134980 | 1670 | { |
2e4b5889 | 1671 | /* General register. */ |
9b9e61c7 | 1672 | gdb_static_assert (ARRAY_SIZE (cris_genreg_names) == NUM_GENREGS); |
2e4b5889 | 1673 | return cris_genreg_names[regno]; |
29134980 | 1674 | } |
d93859e2 | 1675 | else if (regno >= NUM_GENREGS && regno < gdbarch_num_regs (gdbarch)) |
29134980 | 1676 | { |
35488783 | 1677 | return cris_special_register_name (gdbarch, regno); |
c600d464 OF |
1678 | } |
1679 | else | |
1680 | { | |
1681 | /* Invalid register. */ | |
9a972b54 | 1682 | return ""; |
2e4b5889 | 1683 | } |
c600d464 OF |
1684 | } |
1685 | ||
1686 | static const char * | |
d93859e2 | 1687 | crisv32_register_name (struct gdbarch *gdbarch, int regno) |
c600d464 | 1688 | { |
a121b7c1 | 1689 | static const char *crisv32_genreg_names[] = |
c600d464 OF |
1690 | { "r0", "r1", "r2", "r3", \ |
1691 | "r4", "r5", "r6", "r7", \ | |
1692 | "r8", "r9", "r10", "r11", \ | |
1693 | "r12", "r13", "sp", "acr" | |
1694 | }; | |
1695 | ||
a121b7c1 | 1696 | static const char *crisv32_sreg_names[] = |
c600d464 OF |
1697 | { "s0", "s1", "s2", "s3", \ |
1698 | "s4", "s5", "s6", "s7", \ | |
1699 | "s8", "s9", "s10", "s11", \ | |
1700 | "s12", "s13", "s14", "s15" | |
1701 | }; | |
1702 | ||
1703 | if (regno >= 0 && regno < NUM_GENREGS) | |
1704 | { | |
1705 | /* General register. */ | |
1706 | return crisv32_genreg_names[regno]; | |
1707 | } | |
1708 | else if (regno >= NUM_GENREGS && regno < (NUM_GENREGS + NUM_SPECREGS)) | |
1709 | { | |
35488783 | 1710 | return cris_special_register_name (gdbarch, regno); |
c600d464 | 1711 | } |
d93859e2 | 1712 | else if (regno == gdbarch_pc_regnum (gdbarch)) |
c600d464 OF |
1713 | { |
1714 | return "pc"; | |
1715 | } | |
1716 | else if (regno >= S0_REGNUM && regno <= S15_REGNUM) | |
1717 | { | |
1718 | return crisv32_sreg_names[regno - S0_REGNUM]; | |
1719 | } | |
2e4b5889 OF |
1720 | else |
1721 | { | |
1722 | /* Invalid register. */ | |
1723 | return NULL; | |
29134980 | 1724 | } |
29134980 OF |
1725 | } |
1726 | ||
a5f6c8f5 OF |
1727 | /* Convert DWARF register number REG to the appropriate register |
1728 | number used by GDB. */ | |
1729 | ||
2e4b5889 | 1730 | static int |
d3f73121 | 1731 | cris_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
29134980 | 1732 | { |
a5f6c8f5 OF |
1733 | /* We need to re-map a couple of registers (SRP is 16 in Dwarf-2 register |
1734 | numbering, MOF is 18). | |
1735 | Adapted from gcc/config/cris/cris.h. */ | |
1736 | static int cris_dwarf_regmap[] = { | |
1737 | 0, 1, 2, 3, | |
1738 | 4, 5, 6, 7, | |
1739 | 8, 9, 10, 11, | |
1740 | 12, 13, 14, 15, | |
1741 | 27, -1, -1, -1, | |
1742 | -1, -1, -1, 23, | |
1743 | -1, -1, -1, 27, | |
1744 | -1, -1, -1, -1 | |
1745 | }; | |
1746 | int regnum = -1; | |
1747 | ||
1748 | if (reg >= 0 && reg < ARRAY_SIZE (cris_dwarf_regmap)) | |
1749 | regnum = cris_dwarf_regmap[reg]; | |
1750 | ||
a5f6c8f5 OF |
1751 | return regnum; |
1752 | } | |
1753 | ||
1754 | /* DWARF-2 frame support. */ | |
1755 | ||
1756 | static void | |
1757 | cris_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, | |
dda83cd7 | 1758 | struct dwarf2_frame_state_reg *reg, |
bd2b40ac | 1759 | frame_info_ptr this_frame) |
a5f6c8f5 OF |
1760 | { |
1761 | /* The return address column. */ | |
7fbe2eba | 1762 | if (regnum == gdbarch_pc_regnum (gdbarch)) |
a5f6c8f5 OF |
1763 | reg->how = DWARF2_FRAME_REG_RA; |
1764 | ||
1765 | /* The call frame address. */ | |
7fbe2eba | 1766 | else if (regnum == gdbarch_sp_regnum (gdbarch)) |
a5f6c8f5 | 1767 | reg->how = DWARF2_FRAME_REG_CFA; |
29134980 OF |
1768 | } |
1769 | ||
2e4b5889 OF |
1770 | /* Extract from an array regbuf containing the raw register state a function |
1771 | return value of type type, and copy that, in virtual format, into | |
1772 | valbuf. */ | |
1773 | ||
1774 | /* In the CRIS ABI, R10 and R11 are used to store return values. */ | |
29134980 | 1775 | |
2e4b5889 OF |
1776 | static void |
1777 | cris_extract_return_value (struct type *type, struct regcache *regcache, | |
948f8e3d | 1778 | gdb_byte *valbuf) |
29134980 | 1779 | { |
ac7936df | 1780 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1781 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
2e4b5889 | 1782 | ULONGEST val; |
df86565b | 1783 | int len = type->length (); |
29134980 | 1784 | |
bad43aa5 | 1785 | if (len <= 4) |
29134980 | 1786 | { |
2e4b5889 OF |
1787 | /* Get the return value from R10. */ |
1788 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
bad43aa5 | 1789 | store_unsigned_integer (valbuf, len, byte_order, val); |
29134980 | 1790 | } |
bad43aa5 | 1791 | else if (len <= 8) |
29134980 | 1792 | { |
2e4b5889 OF |
1793 | /* Get the return value from R10 and R11. */ |
1794 | regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &val); | |
e17a4113 | 1795 | store_unsigned_integer (valbuf, 4, byte_order, val); |
2e4b5889 | 1796 | regcache_cooked_read_unsigned (regcache, ARG2_REGNUM, &val); |
948f8e3d | 1797 | store_unsigned_integer (valbuf + 4, len - 4, byte_order, val); |
29134980 | 1798 | } |
2e4b5889 | 1799 | else |
8a3fe4f8 | 1800 | error (_("cris_extract_return_value: type length too large")); |
2e4b5889 OF |
1801 | } |
1802 | ||
b4206d25 OF |
1803 | /* Handle the CRIS return value convention. */ |
1804 | ||
1805 | static enum return_value_convention | |
6a3a010b | 1806 | cris_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1807 | struct type *type, struct regcache *regcache, |
1808 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
b4206d25 | 1809 | { |
78134374 SM |
1810 | if (type->code () == TYPE_CODE_STRUCT |
1811 | || type->code () == TYPE_CODE_UNION | |
df86565b | 1812 | || type->length () > 8) |
b4206d25 OF |
1813 | /* Structs, unions, and anything larger than 8 bytes (2 registers) |
1814 | goes on the stack. */ | |
1815 | return RETURN_VALUE_STRUCT_CONVENTION; | |
1816 | ||
1817 | if (readbuf) | |
1818 | cris_extract_return_value (type, regcache, readbuf); | |
1819 | if (writebuf) | |
1820 | cris_store_return_value (type, regcache, writebuf); | |
1821 | ||
1822 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1823 | } | |
1824 | ||
29134980 OF |
1825 | /* Calculates a value that measures how good inst_args constraints an |
1826 | instruction. It stems from cris_constraint, found in cris-dis.c. */ | |
1827 | ||
1828 | static int | |
948f8e3d | 1829 | constraint (unsigned int insn, const char *inst_args, |
dda83cd7 | 1830 | inst_env_type *inst_env) |
29134980 OF |
1831 | { |
1832 | int retval = 0; | |
1833 | int tmp, i; | |
1834 | ||
948f8e3d | 1835 | const gdb_byte *s = (const gdb_byte *) inst_args; |
29134980 OF |
1836 | |
1837 | for (; *s; s++) | |
1838 | switch (*s) | |
1839 | { | |
1840 | case 'm': | |
dda83cd7 SM |
1841 | if ((insn & 0x30) == 0x30) |
1842 | return -1; | |
1843 | break; | |
1844 | ||
29134980 | 1845 | case 'S': |
dda83cd7 SM |
1846 | /* A prefix operand. */ |
1847 | if (inst_env->prefix_found) | |
1848 | break; | |
1849 | else | |
1850 | return -1; | |
29134980 OF |
1851 | |
1852 | case 'B': | |
dda83cd7 SM |
1853 | /* A "push" prefix. (This check was REMOVED by san 970921.) Check for |
1854 | valid "push" size. In case of special register, it may be != 4. */ | |
1855 | if (inst_env->prefix_found) | |
1856 | break; | |
1857 | else | |
1858 | return -1; | |
29134980 OF |
1859 | |
1860 | case 'D': | |
dda83cd7 SM |
1861 | retval = (((insn >> 0xC) & 0xF) == (insn & 0xF)); |
1862 | if (!retval) | |
1863 | return -1; | |
1864 | else | |
1865 | retval += 4; | |
1866 | break; | |
29134980 OF |
1867 | |
1868 | case 'P': | |
dda83cd7 SM |
1869 | tmp = (insn >> 0xC) & 0xF; |
1870 | ||
1871 | for (i = 0; cris_spec_regs[i].name != NULL; i++) | |
1872 | { | |
1873 | /* Since we match four bits, we will give a value of | |
1874 | 4 - 1 = 3 in a match. If there is a corresponding | |
1875 | exact match of a special register in another pattern, it | |
1876 | will get a value of 4, which will be higher. This should | |
1877 | be correct in that an exact pattern would match better that | |
1878 | a general pattern. | |
1879 | Note that there is a reason for not returning zero; the | |
1880 | pattern for "clear" is partly matched in the bit-pattern | |
1881 | (the two lower bits must be zero), while the bit-pattern | |
1882 | for a move from a special register is matched in the | |
1883 | register constraint. | |
1884 | This also means we will will have a race condition if | |
1885 | there is a partly match in three bits in the bit pattern. */ | |
1886 | if (tmp == cris_spec_regs[i].number) | |
1887 | { | |
1888 | retval += 3; | |
1889 | break; | |
1890 | } | |
1891 | } | |
1892 | ||
1893 | if (cris_spec_regs[i].name == NULL) | |
1894 | return -1; | |
1895 | break; | |
29134980 OF |
1896 | } |
1897 | return retval; | |
1898 | } | |
1899 | ||
1900 | /* Returns the number of bits set in the variable value. */ | |
1901 | ||
1902 | static int | |
1903 | number_of_bits (unsigned int value) | |
1904 | { | |
1905 | int number_of_bits = 0; | |
1906 | ||
1907 | while (value != 0) | |
1908 | { | |
1909 | number_of_bits += 1; | |
1910 | value &= (value - 1); | |
1911 | } | |
1912 | return number_of_bits; | |
1913 | } | |
1914 | ||
1915 | /* Finds the address that should contain the single step breakpoint(s). | |
1916 | It stems from code in cris-dis.c. */ | |
1917 | ||
1918 | static int | |
1919 | find_cris_op (unsigned short insn, inst_env_type *inst_env) | |
1920 | { | |
1921 | int i; | |
1922 | int max_level_of_match = -1; | |
1923 | int max_matched = -1; | |
1924 | int level_of_match; | |
1925 | ||
1926 | for (i = 0; cris_opcodes[i].name != NULL; i++) | |
1927 | { | |
1928 | if (((cris_opcodes[i].match & insn) == cris_opcodes[i].match) | |
dda83cd7 | 1929 | && ((cris_opcodes[i].lose & insn) == 0) |
c600d464 OF |
1930 | /* Only CRISv10 instructions, please. */ |
1931 | && (cris_opcodes[i].applicable_version != cris_ver_v32p)) | |
dda83cd7 SM |
1932 | { |
1933 | level_of_match = constraint (insn, cris_opcodes[i].args, inst_env); | |
1934 | if (level_of_match >= 0) | |
1935 | { | |
1936 | level_of_match += | |
1937 | number_of_bits (cris_opcodes[i].match | cris_opcodes[i].lose); | |
1938 | if (level_of_match > max_level_of_match) | |
1939 | { | |
1940 | max_matched = i; | |
1941 | max_level_of_match = level_of_match; | |
1942 | if (level_of_match == 16) | |
1943 | { | |
1944 | /* All bits matched, cannot find better. */ | |
1945 | break; | |
1946 | } | |
1947 | } | |
1948 | } | |
1949 | } | |
29134980 OF |
1950 | } |
1951 | return max_matched; | |
1952 | } | |
1953 | ||
1954 | /* Attempts to find single-step breakpoints. Returns -1 on failure which is | |
1955 | actually an internal error. */ | |
1956 | ||
1957 | static int | |
5b6e2eee | 1958 | find_step_target (struct regcache *regcache, inst_env_type *inst_env) |
29134980 OF |
1959 | { |
1960 | int i; | |
1961 | int offset; | |
1962 | unsigned short insn; | |
ac7936df | 1963 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 1964 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
29134980 OF |
1965 | |
1966 | /* Create a local register image and set the initial state. */ | |
1967 | for (i = 0; i < NUM_GENREGS; i++) | |
1968 | { | |
0b1b3e42 | 1969 | inst_env->reg[i] = |
5b6e2eee | 1970 | (unsigned long) regcache_raw_get_unsigned (regcache, i); |
29134980 OF |
1971 | } |
1972 | offset = NUM_GENREGS; | |
1973 | for (i = 0; i < NUM_SPECREGS; i++) | |
1974 | { | |
0b1b3e42 | 1975 | inst_env->preg[i] = |
5b6e2eee | 1976 | (unsigned long) regcache_raw_get_unsigned (regcache, offset + i); |
29134980 OF |
1977 | } |
1978 | inst_env->branch_found = 0; | |
1979 | inst_env->slot_needed = 0; | |
1980 | inst_env->delay_slot_pc_active = 0; | |
1981 | inst_env->prefix_found = 0; | |
1982 | inst_env->invalid = 0; | |
1983 | inst_env->xflag_found = 0; | |
1984 | inst_env->disable_interrupt = 0; | |
e17a4113 | 1985 | inst_env->byte_order = byte_order; |
29134980 OF |
1986 | |
1987 | /* Look for a step target. */ | |
1988 | do | |
1989 | { | |
1990 | /* Read an instruction from the client. */ | |
3e8c568d | 1991 | insn = read_memory_unsigned_integer |
e17a4113 | 1992 | (inst_env->reg[gdbarch_pc_regnum (gdbarch)], 2, byte_order); |
29134980 OF |
1993 | |
1994 | /* If the instruction is not in a delay slot the new content of the | |
dda83cd7 SM |
1995 | PC is [PC] + 2. If the instruction is in a delay slot it is not |
1996 | that simple. Since a instruction in a delay slot cannot change | |
1997 | the content of the PC, it does not matter what value PC will have. | |
1998 | Just make sure it is a valid instruction. */ | |
29134980 | 1999 | if (!inst_env->delay_slot_pc_active) |
dda83cd7 SM |
2000 | { |
2001 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] += 2; | |
2002 | } | |
29134980 | 2003 | else |
dda83cd7 SM |
2004 | { |
2005 | inst_env->delay_slot_pc_active = 0; | |
2006 | inst_env->reg[gdbarch_pc_regnum (gdbarch)] | |
3e8c568d | 2007 | = inst_env->delay_slot_pc; |
dda83cd7 | 2008 | } |
29134980 OF |
2009 | /* Analyse the present instruction. */ |
2010 | i = find_cris_op (insn, inst_env); | |
2011 | if (i == -1) | |
dda83cd7 SM |
2012 | { |
2013 | inst_env->invalid = 1; | |
2014 | } | |
29134980 | 2015 | else |
dda83cd7 SM |
2016 | { |
2017 | cris_gdb_func (gdbarch, cris_opcodes[i].op, insn, inst_env); | |
2018 | } | |
29134980 | 2019 | } while (!inst_env->invalid |
dda83cd7 SM |
2020 | && (inst_env->prefix_found || inst_env->xflag_found |
2021 | || inst_env->slot_needed)); | |
29134980 OF |
2022 | return i; |
2023 | } | |
2024 | ||
2025 | /* There is no hardware single-step support. The function find_step_target | |
0963b4bd | 2026 | digs through the opcodes in order to find all possible targets. |
29134980 OF |
2027 | Either one ordinary target or two targets for branches may be found. */ |
2028 | ||
a0ff9e1a | 2029 | static std::vector<CORE_ADDR> |
f5ea389a | 2030 | cris_software_single_step (struct regcache *regcache) |
29134980 | 2031 | { |
ac7936df | 2032 | struct gdbarch *gdbarch = regcache->arch (); |
29134980 | 2033 | inst_env_type inst_env; |
a0ff9e1a | 2034 | std::vector<CORE_ADDR> next_pcs; |
8181d85f | 2035 | |
e0cd558a UW |
2036 | /* Analyse the present instruction environment and insert |
2037 | breakpoints. */ | |
5b6e2eee | 2038 | int status = find_step_target (regcache, &inst_env); |
e0cd558a | 2039 | if (status == -1) |
29134980 | 2040 | { |
e0cd558a UW |
2041 | /* Could not find a target. Things are likely to go downhill |
2042 | from here. */ | |
2043 | warning (_("CRIS software single step could not find a step target.")); | |
29134980 OF |
2044 | } |
2045 | else | |
e0cd558a UW |
2046 | { |
2047 | /* Insert at most two breakpoints. One for the next PC content | |
dda83cd7 | 2048 | and possibly another one for a branch, jump, etc. */ |
a6d9a66e UW |
2049 | CORE_ADDR next_pc |
2050 | = (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)]; | |
93f9a11f | 2051 | |
a0ff9e1a | 2052 | next_pcs.push_back (next_pc); |
e0cd558a UW |
2053 | if (inst_env.branch_found |
2054 | && (CORE_ADDR) inst_env.branch_break_address != next_pc) | |
2055 | { | |
2056 | CORE_ADDR branch_target_address | |
2057 | = (CORE_ADDR) inst_env.branch_break_address; | |
93f9a11f | 2058 | |
a0ff9e1a | 2059 | next_pcs.push_back (branch_target_address); |
e0cd558a UW |
2060 | } |
2061 | } | |
e6590a1b | 2062 | |
93f9a11f | 2063 | return next_pcs; |
29134980 OF |
2064 | } |
2065 | ||
2066 | /* Calculates the prefix value for quick offset addressing mode. */ | |
2067 | ||
a78f21af | 2068 | static void |
29134980 OF |
2069 | quick_mode_bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2070 | { | |
2071 | /* It's invalid to be in a delay slot. You can't have a prefix to this | |
2072 | instruction (not 100% sure). */ | |
2073 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2074 | { | |
2075 | inst_env->invalid = 1; | |
2076 | return; | |
2077 | } | |
2078 | ||
2079 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; | |
2080 | inst_env->prefix_value += cris_get_bdap_quick_offset (inst); | |
2081 | ||
2082 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2083 | need updating. */ | |
2084 | inst_env->slot_needed = 0; | |
2085 | inst_env->prefix_found = 1; | |
2086 | } | |
2087 | ||
2088 | /* Updates the autoincrement register. The size of the increment is derived | |
2089 | from the size of the operation. The PC is always kept aligned on even | |
2090 | word addresses. */ | |
2091 | ||
a78f21af | 2092 | static void |
29134980 OF |
2093 | process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env) |
2094 | { | |
2095 | if (size == INST_BYTE_SIZE) | |
2096 | { | |
2097 | inst_env->reg[cris_get_operand1 (inst)] += 1; | |
2098 | ||
2099 | /* The PC must be word aligned, so increase the PC with one | |
dda83cd7 | 2100 | word even if the size is byte. */ |
29134980 | 2101 | if (cris_get_operand1 (inst) == REG_PC) |
dda83cd7 SM |
2102 | { |
2103 | inst_env->reg[REG_PC] += 1; | |
2104 | } | |
29134980 OF |
2105 | } |
2106 | else if (size == INST_WORD_SIZE) | |
2107 | { | |
2108 | inst_env->reg[cris_get_operand1 (inst)] += 2; | |
2109 | } | |
2110 | else if (size == INST_DWORD_SIZE) | |
2111 | { | |
2112 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2113 | } | |
2114 | else | |
2115 | { | |
2116 | /* Invalid size. */ | |
2117 | inst_env->invalid = 1; | |
2118 | } | |
2119 | } | |
2120 | ||
2a9ecef2 OF |
2121 | /* Just a forward declaration. */ |
2122 | ||
a78f21af | 2123 | static unsigned long get_data_from_address (unsigned short *inst, |
e17a4113 UW |
2124 | CORE_ADDR address, |
2125 | enum bfd_endian byte_order); | |
2a9ecef2 | 2126 | |
29134980 OF |
2127 | /* Calculates the prefix value for the general case of offset addressing |
2128 | mode. */ | |
2129 | ||
a78f21af | 2130 | static void |
29134980 OF |
2131 | bdap_prefix (unsigned short inst, inst_env_type *inst_env) |
2132 | { | |
29134980 OF |
2133 | /* It's invalid to be in a delay slot. */ |
2134 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2135 | { | |
2136 | inst_env->invalid = 1; | |
2137 | return; | |
2138 | } | |
2139 | ||
fa4e4598 OF |
2140 | /* The calculation of prefix_value used to be after process_autoincrement, |
2141 | but that fails for an instruction such as jsr [$r0+12] which is encoded | |
2142 | as 5f0d 0c00 30b9 when compiled with -fpic. Since PC is operand1 it | |
2143 | mustn't be incremented until we have read it and what it points at. */ | |
29134980 OF |
2144 | inst_env->prefix_value = inst_env->reg[cris_get_operand2 (inst)]; |
2145 | ||
2146 | /* The offset is an indirection of the contents of the operand1 register. */ | |
2147 | inst_env->prefix_value += | |
e17a4113 UW |
2148 | get_data_from_address (&inst, inst_env->reg[cris_get_operand1 (inst)], |
2149 | inst_env->byte_order); | |
2a9ecef2 | 2150 | |
fa4e4598 OF |
2151 | if (cris_get_mode (inst) == AUTOINC_MODE) |
2152 | { | |
2153 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2154 | } | |
2155 | ||
29134980 OF |
2156 | /* A prefix doesn't change the xflag_found. But the rest of the flags |
2157 | need updating. */ | |
2158 | inst_env->slot_needed = 0; | |
2159 | inst_env->prefix_found = 1; | |
2160 | } | |
2161 | ||
2162 | /* Calculates the prefix value for the index addressing mode. */ | |
2163 | ||
a78f21af | 2164 | static void |
29134980 OF |
2165 | biap_prefix (unsigned short inst, inst_env_type *inst_env) |
2166 | { | |
2167 | /* It's invalid to be in a delay slot. I can't see that it's possible to | |
2168 | have a prefix to this instruction. So I will treat this as invalid. */ | |
2169 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2170 | { | |
2171 | inst_env->invalid = 1; | |
2172 | return; | |
2173 | } | |
2174 | ||
2175 | inst_env->prefix_value = inst_env->reg[cris_get_operand1 (inst)]; | |
2176 | ||
2177 | /* The offset is the operand2 value shifted the size of the instruction | |
2178 | to the left. */ | |
2179 | inst_env->prefix_value += | |
2180 | inst_env->reg[cris_get_operand2 (inst)] << cris_get_size (inst); | |
2181 | ||
2182 | /* If the PC is operand1 (base) the address used is the address after | |
2183 | the main instruction, i.e. address + 2 (the PC is already compensated | |
2184 | for the prefix operation). */ | |
2185 | if (cris_get_operand1 (inst) == REG_PC) | |
2186 | { | |
2187 | inst_env->prefix_value += 2; | |
2188 | } | |
2189 | ||
2190 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2191 | need updating. */ | |
2192 | inst_env->slot_needed = 0; | |
2193 | inst_env->xflag_found = 0; | |
2194 | inst_env->prefix_found = 1; | |
2195 | } | |
2196 | ||
2197 | /* Calculates the prefix value for the double indirect addressing mode. */ | |
2198 | ||
a78f21af | 2199 | static void |
29134980 OF |
2200 | dip_prefix (unsigned short inst, inst_env_type *inst_env) |
2201 | { | |
2202 | ||
2203 | CORE_ADDR address; | |
2204 | ||
2205 | /* It's invalid to be in a delay slot. */ | |
2206 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2207 | { | |
2208 | inst_env->invalid = 1; | |
2209 | return; | |
2210 | } | |
2211 | ||
2212 | /* The prefix value is one dereference of the contents of the operand1 | |
2213 | register. */ | |
2214 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 UW |
2215 | inst_env->prefix_value |
2216 | = read_memory_unsigned_integer (address, 4, inst_env->byte_order); | |
29134980 OF |
2217 | |
2218 | /* Check if the mode is autoincrement. */ | |
2219 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2220 | { | |
2221 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2222 | } | |
2223 | ||
2224 | /* A prefix doesn't change the xflag_found. But the rest of the flags | |
2225 | need updating. */ | |
2226 | inst_env->slot_needed = 0; | |
2227 | inst_env->xflag_found = 0; | |
2228 | inst_env->prefix_found = 1; | |
2229 | } | |
2230 | ||
2231 | /* Finds the destination for a branch with 8-bits offset. */ | |
2232 | ||
a78f21af | 2233 | static void |
29134980 OF |
2234 | eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2235 | { | |
2236 | ||
2237 | short offset; | |
2238 | ||
2239 | /* If we have a prefix or are in a delay slot it's bad. */ | |
2240 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2241 | { | |
2242 | inst_env->invalid = 1; | |
2243 | return; | |
2244 | } | |
2245 | ||
2246 | /* We have a branch, find out where the branch will land. */ | |
2247 | offset = cris_get_branch_short_offset (inst); | |
2248 | ||
2249 | /* Check if the offset is signed. */ | |
2250 | if (offset & BRANCH_SIGNED_SHORT_OFFSET_MASK) | |
2251 | { | |
2252 | offset |= 0xFF00; | |
2253 | } | |
2254 | ||
2255 | /* The offset ends with the sign bit, set it to zero. The address | |
2256 | should always be word aligned. */ | |
2257 | offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK; | |
2258 | ||
2259 | inst_env->branch_found = 1; | |
2260 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2261 | ||
2262 | inst_env->slot_needed = 1; | |
2263 | inst_env->prefix_found = 0; | |
2264 | inst_env->xflag_found = 0; | |
2265 | inst_env->disable_interrupt = 1; | |
2266 | } | |
2267 | ||
2268 | /* Finds the destination for a branch with 16-bits offset. */ | |
2269 | ||
a78f21af | 2270 | static void |
29134980 OF |
2271 | sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env) |
2272 | { | |
2273 | short offset; | |
2274 | ||
2275 | /* If we have a prefix or is in a delay slot it's bad. */ | |
2276 | if (inst_env->slot_needed || inst_env->prefix_found) | |
2277 | { | |
2278 | inst_env->invalid = 1; | |
2279 | return; | |
2280 | } | |
2281 | ||
2282 | /* We have a branch, find out the offset for the branch. */ | |
0963b4bd MS |
2283 | offset = read_memory_integer (inst_env->reg[REG_PC], 2, |
2284 | inst_env->byte_order); | |
29134980 OF |
2285 | |
2286 | /* The instruction is one word longer than normal, so add one word | |
2287 | to the PC. */ | |
2288 | inst_env->reg[REG_PC] += 2; | |
2289 | ||
2290 | inst_env->branch_found = 1; | |
2291 | inst_env->branch_break_address = inst_env->reg[REG_PC] + offset; | |
2292 | ||
2293 | ||
2294 | inst_env->slot_needed = 1; | |
2295 | inst_env->prefix_found = 0; | |
2296 | inst_env->xflag_found = 0; | |
2297 | inst_env->disable_interrupt = 1; | |
2298 | } | |
2299 | ||
2300 | /* Handles the ABS instruction. */ | |
2301 | ||
a78f21af | 2302 | static void |
29134980 OF |
2303 | abs_op (unsigned short inst, inst_env_type *inst_env) |
2304 | { | |
2305 | ||
2306 | long value; | |
2307 | ||
2308 | /* ABS can't have a prefix, so it's bad if it does. */ | |
2309 | if (inst_env->prefix_found) | |
2310 | { | |
2311 | inst_env->invalid = 1; | |
2312 | return; | |
2313 | } | |
2314 | ||
2315 | /* Check if the operation affects the PC. */ | |
2316 | if (cris_get_operand2 (inst) == REG_PC) | |
2317 | { | |
2318 | ||
2319 | /* It's invalid to change to the PC if we are in a delay slot. */ | |
2320 | if (inst_env->slot_needed) | |
dda83cd7 SM |
2321 | { |
2322 | inst_env->invalid = 1; | |
2323 | return; | |
2324 | } | |
29134980 OF |
2325 | |
2326 | value = (long) inst_env->reg[REG_PC]; | |
2327 | ||
2328 | /* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */ | |
2329 | if (value != SIGNED_DWORD_MASK) | |
dda83cd7 SM |
2330 | { |
2331 | value = -value; | |
2332 | inst_env->reg[REG_PC] = (long) value; | |
2333 | } | |
29134980 OF |
2334 | } |
2335 | ||
2336 | inst_env->slot_needed = 0; | |
2337 | inst_env->prefix_found = 0; | |
2338 | inst_env->xflag_found = 0; | |
2339 | inst_env->disable_interrupt = 0; | |
2340 | } | |
2341 | ||
2342 | /* Handles the ADDI instruction. */ | |
2343 | ||
a78f21af | 2344 | static void |
29134980 OF |
2345 | addi_op (unsigned short inst, inst_env_type *inst_env) |
2346 | { | |
2347 | /* It's invalid to have the PC as base register. And ADDI can't have | |
2348 | a prefix. */ | |
2349 | if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC)) | |
2350 | { | |
2351 | inst_env->invalid = 1; | |
2352 | return; | |
2353 | } | |
2354 | ||
2355 | inst_env->slot_needed = 0; | |
2356 | inst_env->prefix_found = 0; | |
2357 | inst_env->xflag_found = 0; | |
2358 | inst_env->disable_interrupt = 0; | |
2359 | } | |
2360 | ||
2361 | /* Handles the ASR instruction. */ | |
2362 | ||
a78f21af | 2363 | static void |
29134980 OF |
2364 | asr_op (unsigned short inst, inst_env_type *inst_env) |
2365 | { | |
2366 | int shift_steps; | |
2367 | unsigned long value; | |
2368 | unsigned long signed_extend_mask = 0; | |
2369 | ||
2370 | /* ASR can't have a prefix, so check that it doesn't. */ | |
2371 | if (inst_env->prefix_found) | |
2372 | { | |
2373 | inst_env->invalid = 1; | |
2374 | return; | |
2375 | } | |
2376 | ||
2377 | /* Check if the PC is the target register. */ | |
2378 | if (cris_get_operand2 (inst) == REG_PC) | |
2379 | { | |
2380 | /* It's invalid to change the PC in a delay slot. */ | |
2381 | if (inst_env->slot_needed) | |
dda83cd7 SM |
2382 | { |
2383 | inst_env->invalid = 1; | |
2384 | return; | |
2385 | } | |
29134980 | 2386 | /* Get the number of bits to shift. */ |
0963b4bd MS |
2387 | shift_steps |
2388 | = cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]); | |
29134980 OF |
2389 | value = inst_env->reg[REG_PC]; |
2390 | ||
2391 | /* Find out how many bits the operation should apply to. */ | |
2392 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
dda83cd7 SM |
2393 | { |
2394 | if (value & SIGNED_BYTE_MASK) | |
2395 | { | |
2396 | signed_extend_mask = 0xFF; | |
2397 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2398 | signed_extend_mask = ~signed_extend_mask; | |
2399 | } | |
2400 | value = value >> shift_steps; | |
2401 | value |= signed_extend_mask; | |
2402 | value &= 0xFF; | |
2403 | inst_env->reg[REG_PC] &= 0xFFFFFF00; | |
2404 | inst_env->reg[REG_PC] |= value; | |
2405 | } | |
29134980 | 2406 | else if (cris_get_size (inst) == INST_WORD_SIZE) |
dda83cd7 SM |
2407 | { |
2408 | if (value & SIGNED_WORD_MASK) | |
2409 | { | |
2410 | signed_extend_mask = 0xFFFF; | |
2411 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2412 | signed_extend_mask = ~signed_extend_mask; | |
2413 | } | |
2414 | value = value >> shift_steps; | |
2415 | value |= signed_extend_mask; | |
2416 | value &= 0xFFFF; | |
2417 | inst_env->reg[REG_PC] &= 0xFFFF0000; | |
2418 | inst_env->reg[REG_PC] |= value; | |
2419 | } | |
29134980 | 2420 | else if (cris_get_size (inst) == INST_DWORD_SIZE) |
dda83cd7 SM |
2421 | { |
2422 | if (value & SIGNED_DWORD_MASK) | |
2423 | { | |
2424 | signed_extend_mask = 0xFFFFFFFF; | |
2425 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2426 | signed_extend_mask = ~signed_extend_mask; | |
2427 | } | |
2428 | value = value >> shift_steps; | |
2429 | value |= signed_extend_mask; | |
2430 | inst_env->reg[REG_PC] = value; | |
2431 | } | |
29134980 OF |
2432 | } |
2433 | inst_env->slot_needed = 0; | |
2434 | inst_env->prefix_found = 0; | |
2435 | inst_env->xflag_found = 0; | |
2436 | inst_env->disable_interrupt = 0; | |
2437 | } | |
2438 | ||
2439 | /* Handles the ASRQ instruction. */ | |
2440 | ||
a78f21af | 2441 | static void |
29134980 OF |
2442 | asrq_op (unsigned short inst, inst_env_type *inst_env) |
2443 | { | |
2444 | ||
2445 | int shift_steps; | |
2446 | unsigned long value; | |
2447 | unsigned long signed_extend_mask = 0; | |
2448 | ||
2449 | /* ASRQ can't have a prefix, so check that it doesn't. */ | |
2450 | if (inst_env->prefix_found) | |
2451 | { | |
2452 | inst_env->invalid = 1; | |
2453 | return; | |
2454 | } | |
2455 | ||
2456 | /* Check if the PC is the target register. */ | |
2457 | if (cris_get_operand2 (inst) == REG_PC) | |
2458 | { | |
2459 | ||
2460 | /* It's invalid to change the PC in a delay slot. */ | |
2461 | if (inst_env->slot_needed) | |
dda83cd7 SM |
2462 | { |
2463 | inst_env->invalid = 1; | |
2464 | return; | |
2465 | } | |
29134980 | 2466 | /* The shift size is given as a 5 bit quick value, i.e. we don't |
dda83cd7 | 2467 | want the sign bit of the quick value. */ |
29134980 OF |
2468 | shift_steps = cris_get_asr_shift_steps (inst); |
2469 | value = inst_env->reg[REG_PC]; | |
2470 | if (value & SIGNED_DWORD_MASK) | |
dda83cd7 SM |
2471 | { |
2472 | signed_extend_mask = 0xFFFFFFFF; | |
2473 | signed_extend_mask = signed_extend_mask >> shift_steps; | |
2474 | signed_extend_mask = ~signed_extend_mask; | |
2475 | } | |
29134980 OF |
2476 | value = value >> shift_steps; |
2477 | value |= signed_extend_mask; | |
2478 | inst_env->reg[REG_PC] = value; | |
2479 | } | |
2480 | inst_env->slot_needed = 0; | |
2481 | inst_env->prefix_found = 0; | |
2482 | inst_env->xflag_found = 0; | |
2483 | inst_env->disable_interrupt = 0; | |
2484 | } | |
2485 | ||
2486 | /* Handles the AX, EI and SETF instruction. */ | |
2487 | ||
a78f21af | 2488 | static void |
29134980 OF |
2489 | ax_ei_setf_op (unsigned short inst, inst_env_type *inst_env) |
2490 | { | |
2491 | if (inst_env->prefix_found) | |
2492 | { | |
2493 | inst_env->invalid = 1; | |
2494 | return; | |
2495 | } | |
2496 | /* Check if the instruction is setting the X flag. */ | |
2497 | if (cris_is_xflag_bit_on (inst)) | |
2498 | { | |
2499 | inst_env->xflag_found = 1; | |
2500 | } | |
2501 | else | |
2502 | { | |
2503 | inst_env->xflag_found = 0; | |
2504 | } | |
2505 | inst_env->slot_needed = 0; | |
2506 | inst_env->prefix_found = 0; | |
2507 | inst_env->disable_interrupt = 1; | |
2508 | } | |
2509 | ||
2510 | /* Checks if the instruction is in assign mode. If so, it updates the assign | |
2511 | register. Note that check_assign assumes that the caller has checked that | |
2512 | there is a prefix to this instruction. The mode check depends on this. */ | |
2513 | ||
a78f21af | 2514 | static void |
29134980 OF |
2515 | check_assign (unsigned short inst, inst_env_type *inst_env) |
2516 | { | |
2517 | /* Check if it's an assign addressing mode. */ | |
2518 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) | |
2519 | { | |
2520 | /* Assign the prefix value to operand 1. */ | |
2521 | inst_env->reg[cris_get_operand1 (inst)] = inst_env->prefix_value; | |
2522 | } | |
2523 | } | |
2524 | ||
2525 | /* Handles the 2-operand BOUND instruction. */ | |
2526 | ||
a78f21af | 2527 | static void |
29134980 OF |
2528 | two_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2529 | { | |
2530 | /* It's invalid to have the PC as the index operand. */ | |
2531 | if (cris_get_operand2 (inst) == REG_PC) | |
2532 | { | |
2533 | inst_env->invalid = 1; | |
2534 | return; | |
2535 | } | |
2536 | /* Check if we have a prefix. */ | |
2537 | if (inst_env->prefix_found) | |
2538 | { | |
2539 | check_assign (inst, inst_env); | |
2540 | } | |
2541 | /* Check if this is an autoincrement mode. */ | |
2542 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2543 | { | |
2544 | /* It's invalid to change the PC in a delay slot. */ | |
2545 | if (inst_env->slot_needed) | |
dda83cd7 SM |
2546 | { |
2547 | inst_env->invalid = 1; | |
2548 | return; | |
2549 | } | |
29134980 OF |
2550 | process_autoincrement (cris_get_size (inst), inst, inst_env); |
2551 | } | |
2552 | inst_env->slot_needed = 0; | |
2553 | inst_env->prefix_found = 0; | |
2554 | inst_env->xflag_found = 0; | |
2555 | inst_env->disable_interrupt = 0; | |
2556 | } | |
2557 | ||
2558 | /* Handles the 3-operand BOUND instruction. */ | |
2559 | ||
a78f21af | 2560 | static void |
29134980 OF |
2561 | three_operand_bound_op (unsigned short inst, inst_env_type *inst_env) |
2562 | { | |
2563 | /* It's an error if we haven't got a prefix. And it's also an error | |
2564 | if the PC is the destination register. */ | |
2565 | if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC)) | |
2566 | { | |
2567 | inst_env->invalid = 1; | |
2568 | return; | |
2569 | } | |
2570 | inst_env->slot_needed = 0; | |
2571 | inst_env->prefix_found = 0; | |
2572 | inst_env->xflag_found = 0; | |
2573 | inst_env->disable_interrupt = 0; | |
2574 | } | |
2575 | ||
2576 | /* Clears the status flags in inst_env. */ | |
2577 | ||
a78f21af | 2578 | static void |
29134980 OF |
2579 | btst_nop_op (unsigned short inst, inst_env_type *inst_env) |
2580 | { | |
2581 | /* It's an error if we have got a prefix. */ | |
2582 | if (inst_env->prefix_found) | |
2583 | { | |
2584 | inst_env->invalid = 1; | |
2585 | return; | |
2586 | } | |
2587 | ||
2588 | inst_env->slot_needed = 0; | |
2589 | inst_env->prefix_found = 0; | |
2590 | inst_env->xflag_found = 0; | |
2591 | inst_env->disable_interrupt = 0; | |
2592 | } | |
2593 | ||
2594 | /* Clears the status flags in inst_env. */ | |
2595 | ||
a78f21af | 2596 | static void |
29134980 OF |
2597 | clearf_di_op (unsigned short inst, inst_env_type *inst_env) |
2598 | { | |
2599 | /* It's an error if we have got a prefix. */ | |
2600 | if (inst_env->prefix_found) | |
2601 | { | |
2602 | inst_env->invalid = 1; | |
2603 | return; | |
2604 | } | |
2605 | ||
2606 | inst_env->slot_needed = 0; | |
2607 | inst_env->prefix_found = 0; | |
2608 | inst_env->xflag_found = 0; | |
2609 | inst_env->disable_interrupt = 1; | |
2610 | } | |
2611 | ||
2612 | /* Handles the CLEAR instruction if it's in register mode. */ | |
2613 | ||
a78f21af | 2614 | static void |
29134980 OF |
2615 | reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env) |
2616 | { | |
2617 | /* Check if the target is the PC. */ | |
2618 | if (cris_get_operand2 (inst) == REG_PC) | |
2619 | { | |
2620 | /* The instruction will clear the instruction's size bits. */ | |
2621 | int clear_size = cris_get_clear_size (inst); | |
2622 | if (clear_size == INST_BYTE_SIZE) | |
dda83cd7 SM |
2623 | { |
2624 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00; | |
2625 | } | |
29134980 | 2626 | if (clear_size == INST_WORD_SIZE) |
dda83cd7 SM |
2627 | { |
2628 | inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000; | |
2629 | } | |
29134980 | 2630 | if (clear_size == INST_DWORD_SIZE) |
dda83cd7 SM |
2631 | { |
2632 | inst_env->delay_slot_pc = 0x0; | |
2633 | } | |
29134980 | 2634 | /* The jump will be delayed with one delay slot. So we need a delay |
dda83cd7 | 2635 | slot. */ |
29134980 OF |
2636 | inst_env->slot_needed = 1; |
2637 | inst_env->delay_slot_pc_active = 1; | |
2638 | } | |
2639 | else | |
2640 | { | |
2641 | /* The PC will not change => no delay slot. */ | |
2642 | inst_env->slot_needed = 0; | |
2643 | } | |
2644 | inst_env->prefix_found = 0; | |
2645 | inst_env->xflag_found = 0; | |
2646 | inst_env->disable_interrupt = 0; | |
2647 | } | |
2648 | ||
2649 | /* Handles the TEST instruction if it's in register mode. */ | |
2650 | ||
a78f21af | 2651 | static void |
29134980 OF |
2652 | reg_mode_test_op (unsigned short inst, inst_env_type *inst_env) |
2653 | { | |
2654 | /* It's an error if we have got a prefix. */ | |
2655 | if (inst_env->prefix_found) | |
2656 | { | |
2657 | inst_env->invalid = 1; | |
2658 | return; | |
2659 | } | |
2660 | inst_env->slot_needed = 0; | |
2661 | inst_env->prefix_found = 0; | |
2662 | inst_env->xflag_found = 0; | |
2663 | inst_env->disable_interrupt = 0; | |
2664 | ||
2665 | } | |
2666 | ||
2667 | /* Handles the CLEAR and TEST instruction if the instruction isn't | |
2668 | in register mode. */ | |
2669 | ||
a78f21af | 2670 | static void |
29134980 OF |
2671 | none_reg_mode_clear_test_op (unsigned short inst, inst_env_type *inst_env) |
2672 | { | |
2673 | /* Check if we are in a prefix mode. */ | |
2674 | if (inst_env->prefix_found) | |
2675 | { | |
2676 | /* The only way the PC can change is if this instruction is in | |
dda83cd7 | 2677 | assign addressing mode. */ |
29134980 OF |
2678 | check_assign (inst, inst_env); |
2679 | } | |
2680 | /* Indirect mode can't change the PC so just check if the mode is | |
2681 | autoincrement. */ | |
2682 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2683 | { | |
2684 | process_autoincrement (cris_get_size (inst), inst, inst_env); | |
2685 | } | |
2686 | inst_env->slot_needed = 0; | |
2687 | inst_env->prefix_found = 0; | |
2688 | inst_env->xflag_found = 0; | |
2689 | inst_env->disable_interrupt = 0; | |
2690 | } | |
2691 | ||
2692 | /* Checks that the PC isn't the destination register or the instructions has | |
2693 | a prefix. */ | |
2694 | ||
a78f21af | 2695 | static void |
29134980 OF |
2696 | dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env) |
2697 | { | |
2698 | /* It's invalid to have the PC as the destination. The instruction can't | |
2699 | have a prefix. */ | |
2700 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2701 | { | |
2702 | inst_env->invalid = 1; | |
2703 | return; | |
2704 | } | |
2705 | ||
2706 | inst_env->slot_needed = 0; | |
2707 | inst_env->prefix_found = 0; | |
2708 | inst_env->xflag_found = 0; | |
2709 | inst_env->disable_interrupt = 0; | |
2710 | } | |
2711 | ||
2712 | /* Checks that the instruction doesn't have a prefix. */ | |
2713 | ||
a78f21af | 2714 | static void |
29134980 OF |
2715 | break_op (unsigned short inst, inst_env_type *inst_env) |
2716 | { | |
2717 | /* The instruction can't have a prefix. */ | |
2718 | if (inst_env->prefix_found) | |
2719 | { | |
2720 | inst_env->invalid = 1; | |
2721 | return; | |
2722 | } | |
2723 | ||
2724 | inst_env->slot_needed = 0; | |
2725 | inst_env->prefix_found = 0; | |
2726 | inst_env->xflag_found = 0; | |
2727 | inst_env->disable_interrupt = 1; | |
2728 | } | |
2729 | ||
2730 | /* Checks that the PC isn't the destination register and that the instruction | |
2731 | doesn't have a prefix. */ | |
2732 | ||
a78f21af | 2733 | static void |
29134980 OF |
2734 | scc_op (unsigned short inst, inst_env_type *inst_env) |
2735 | { | |
2736 | /* It's invalid to have the PC as the destination. The instruction can't | |
2737 | have a prefix. */ | |
2738 | if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found) | |
2739 | { | |
2740 | inst_env->invalid = 1; | |
2741 | return; | |
2742 | } | |
2743 | ||
2744 | inst_env->slot_needed = 0; | |
2745 | inst_env->prefix_found = 0; | |
2746 | inst_env->xflag_found = 0; | |
2747 | inst_env->disable_interrupt = 1; | |
2748 | } | |
2749 | ||
2750 | /* Handles the register mode JUMP instruction. */ | |
2751 | ||
a78f21af | 2752 | static void |
29134980 OF |
2753 | reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) |
2754 | { | |
2755 | /* It's invalid to do a JUMP in a delay slot. The mode is register, so | |
2756 | you can't have a prefix. */ | |
2757 | if ((inst_env->slot_needed) || (inst_env->prefix_found)) | |
2758 | { | |
2759 | inst_env->invalid = 1; | |
2760 | return; | |
2761 | } | |
2762 | ||
2763 | /* Just change the PC. */ | |
2764 | inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)]; | |
2765 | inst_env->slot_needed = 0; | |
2766 | inst_env->prefix_found = 0; | |
2767 | inst_env->xflag_found = 0; | |
2768 | inst_env->disable_interrupt = 1; | |
2769 | } | |
2770 | ||
2771 | /* Handles the JUMP instruction for all modes except register. */ | |
2772 | ||
a78f21af AC |
2773 | static void |
2774 | none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
2775 | { |
2776 | unsigned long newpc; | |
2777 | CORE_ADDR address; | |
2778 | ||
2779 | /* It's invalid to do a JUMP in a delay slot. */ | |
2780 | if (inst_env->slot_needed) | |
2781 | { | |
2782 | inst_env->invalid = 1; | |
2783 | } | |
2784 | else | |
2785 | { | |
2786 | /* Check if we have a prefix. */ | |
2787 | if (inst_env->prefix_found) | |
dda83cd7 SM |
2788 | { |
2789 | check_assign (inst, inst_env); | |
2790 | ||
2791 | /* Get the new value for the PC. */ | |
2792 | newpc = | |
2793 | read_memory_unsigned_integer ((CORE_ADDR) inst_env->prefix_value, | |
2794 | 4, inst_env->byte_order); | |
2795 | } | |
29134980 | 2796 | else |
dda83cd7 SM |
2797 | { |
2798 | /* Get the new value for the PC. */ | |
2799 | address = (CORE_ADDR) inst_env->reg[cris_get_operand1 (inst)]; | |
2800 | newpc = read_memory_unsigned_integer (address, | |
e17a4113 | 2801 | 4, inst_env->byte_order); |
29134980 | 2802 | |
dda83cd7 SM |
2803 | /* Check if we should increment a register. */ |
2804 | if (cris_get_mode (inst) == AUTOINC_MODE) | |
2805 | { | |
2806 | inst_env->reg[cris_get_operand1 (inst)] += 4; | |
2807 | } | |
2808 | } | |
29134980 OF |
2809 | inst_env->reg[REG_PC] = newpc; |
2810 | } | |
2811 | inst_env->slot_needed = 0; | |
2812 | inst_env->prefix_found = 0; | |
2813 | inst_env->xflag_found = 0; | |
2814 | inst_env->disable_interrupt = 1; | |
2815 | } | |
2816 | ||
2817 | /* Handles moves to special registers (aka P-register) for all modes. */ | |
2818 | ||
a78f21af | 2819 | static void |
be8626e0 MD |
2820 | move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2821 | inst_env_type *inst_env) | |
29134980 OF |
2822 | { |
2823 | if (inst_env->prefix_found) | |
2824 | { | |
2825 | /* The instruction has a prefix that means we are only interested if | |
dda83cd7 | 2826 | the instruction is in assign mode. */ |
29134980 | 2827 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
dda83cd7 SM |
2828 | { |
2829 | /* The prefix handles the problem if we are in a delay slot. */ | |
2830 | if (cris_get_operand1 (inst) == REG_PC) | |
2831 | { | |
2832 | /* Just take care of the assign. */ | |
2833 | check_assign (inst, inst_env); | |
2834 | } | |
2835 | } | |
29134980 OF |
2836 | } |
2837 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2838 | { | |
2839 | /* The instruction doesn't have a prefix, the only case left that we | |
dda83cd7 | 2840 | are interested in is the autoincrement mode. */ |
29134980 | 2841 | if (cris_get_operand1 (inst) == REG_PC) |
dda83cd7 SM |
2842 | { |
2843 | /* If the PC is to be incremented it's invalid to be in a | |
2844 | delay slot. */ | |
2845 | if (inst_env->slot_needed) | |
2846 | { | |
2847 | inst_env->invalid = 1; | |
2848 | return; | |
2849 | } | |
2850 | ||
2851 | /* The increment depends on the size of the special register. */ | |
2852 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) | |
2853 | { | |
2854 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2855 | } | |
2856 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) | |
2857 | { | |
2858 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2859 | } | |
2860 | else | |
2861 | { | |
2862 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2863 | } | |
2864 | } | |
29134980 OF |
2865 | } |
2866 | inst_env->slot_needed = 0; | |
2867 | inst_env->prefix_found = 0; | |
2868 | inst_env->xflag_found = 0; | |
2869 | inst_env->disable_interrupt = 1; | |
2870 | } | |
2871 | ||
2872 | /* Handles moves from special registers (aka P-register) for all modes | |
2873 | except register. */ | |
2874 | ||
a78f21af | 2875 | static void |
be8626e0 MD |
2876 | none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst, |
2877 | inst_env_type *inst_env) | |
29134980 OF |
2878 | { |
2879 | if (inst_env->prefix_found) | |
2880 | { | |
2881 | /* The instruction has a prefix that means we are only interested if | |
dda83cd7 | 2882 | the instruction is in assign mode. */ |
29134980 | 2883 | if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
dda83cd7 SM |
2884 | { |
2885 | /* The prefix handles the problem if we are in a delay slot. */ | |
2886 | if (cris_get_operand1 (inst) == REG_PC) | |
2887 | { | |
2888 | /* Just take care of the assign. */ | |
2889 | check_assign (inst, inst_env); | |
2890 | } | |
2891 | } | |
29134980 OF |
2892 | } |
2893 | /* The instruction doesn't have a prefix, the only case left that we | |
2894 | are interested in is the autoincrement mode. */ | |
2895 | else if (cris_get_mode (inst) == AUTOINC_MODE) | |
2896 | { | |
2897 | if (cris_get_operand1 (inst) == REG_PC) | |
dda83cd7 SM |
2898 | { |
2899 | /* If the PC is to be incremented it's invalid to be in a | |
2900 | delay slot. */ | |
2901 | if (inst_env->slot_needed) | |
2902 | { | |
2903 | inst_env->invalid = 1; | |
2904 | return; | |
2905 | } | |
2906 | ||
2907 | /* The increment depends on the size of the special register. */ | |
2908 | if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 1) | |
2909 | { | |
2910 | process_autoincrement (INST_BYTE_SIZE, inst, inst_env); | |
2911 | } | |
2912 | else if (cris_register_size (gdbarch, cris_get_operand2 (inst)) == 2) | |
2913 | { | |
2914 | process_autoincrement (INST_WORD_SIZE, inst, inst_env); | |
2915 | } | |
2916 | else | |
2917 | { | |
2918 | process_autoincrement (INST_DWORD_SIZE, inst, inst_env); | |
2919 | } | |
2920 | } | |
29134980 OF |
2921 | } |
2922 | inst_env->slot_needed = 0; | |
2923 | inst_env->prefix_found = 0; | |
2924 | inst_env->xflag_found = 0; | |
2925 | inst_env->disable_interrupt = 1; | |
2926 | } | |
2927 | ||
2928 | /* Handles moves from special registers (aka P-register) when the mode | |
2929 | is register. */ | |
2930 | ||
a78f21af | 2931 | static void |
29134980 OF |
2932 | reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env) |
2933 | { | |
2934 | /* Register mode move from special register can't have a prefix. */ | |
2935 | if (inst_env->prefix_found) | |
2936 | { | |
2937 | inst_env->invalid = 1; | |
2938 | return; | |
2939 | } | |
2940 | ||
2941 | if (cris_get_operand1 (inst) == REG_PC) | |
2942 | { | |
2943 | /* It's invalid to change the PC in a delay slot. */ | |
2944 | if (inst_env->slot_needed) | |
dda83cd7 SM |
2945 | { |
2946 | inst_env->invalid = 1; | |
2947 | return; | |
2948 | } | |
29134980 OF |
2949 | /* The destination is the PC, the jump will have a delay slot. */ |
2950 | inst_env->delay_slot_pc = inst_env->preg[cris_get_operand2 (inst)]; | |
2951 | inst_env->slot_needed = 1; | |
2952 | inst_env->delay_slot_pc_active = 1; | |
2953 | } | |
2954 | else | |
2955 | { | |
2956 | /* If the destination isn't PC, there will be no jump. */ | |
2957 | inst_env->slot_needed = 0; | |
2958 | } | |
2959 | inst_env->prefix_found = 0; | |
2960 | inst_env->xflag_found = 0; | |
2961 | inst_env->disable_interrupt = 1; | |
2962 | } | |
2963 | ||
2964 | /* Handles the MOVEM from memory to general register instruction. */ | |
2965 | ||
a78f21af | 2966 | static void |
29134980 OF |
2967 | move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env) |
2968 | { | |
2969 | if (inst_env->prefix_found) | |
2970 | { | |
2971 | /* The prefix handles the problem if we are in a delay slot. Is the | |
dda83cd7 | 2972 | MOVEM instruction going to change the PC? */ |
29134980 | 2973 | if (cris_get_operand2 (inst) >= REG_PC) |
dda83cd7 SM |
2974 | { |
2975 | inst_env->reg[REG_PC] = | |
2976 | read_memory_unsigned_integer (inst_env->prefix_value, | |
e17a4113 | 2977 | 4, inst_env->byte_order); |
dda83cd7 | 2978 | } |
29134980 | 2979 | /* The assign value is the value after the increment. Normally, the |
dda83cd7 | 2980 | assign value is the value before the increment. */ |
29134980 | 2981 | if ((cris_get_operand1 (inst) == REG_PC) |
dda83cd7 SM |
2982 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
2983 | { | |
2984 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
2985 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
2986 | } | |
29134980 OF |
2987 | } |
2988 | else | |
2989 | { | |
2990 | /* Is the MOVEM instruction going to change the PC? */ | |
2991 | if (cris_get_operand2 (inst) == REG_PC) | |
dda83cd7 SM |
2992 | { |
2993 | /* It's invalid to change the PC in a delay slot. */ | |
2994 | if (inst_env->slot_needed) | |
2995 | { | |
2996 | inst_env->invalid = 1; | |
2997 | return; | |
2998 | } | |
2999 | inst_env->reg[REG_PC] = | |
3000 | read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)], | |
3001 | 4, inst_env->byte_order); | |
3002 | } | |
29134980 | 3003 | /* The increment is not depending on the size, instead it's depending |
dda83cd7 | 3004 | on the number of registers loaded from memory. */ |
0963b4bd MS |
3005 | if ((cris_get_operand1 (inst) == REG_PC) |
3006 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
dda83cd7 SM |
3007 | { |
3008 | /* It's invalid to change the PC in a delay slot. */ | |
3009 | if (inst_env->slot_needed) | |
3010 | { | |
3011 | inst_env->invalid = 1; | |
3012 | return; | |
3013 | } | |
3014 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3015 | } | |
29134980 OF |
3016 | } |
3017 | inst_env->slot_needed = 0; | |
3018 | inst_env->prefix_found = 0; | |
3019 | inst_env->xflag_found = 0; | |
3020 | inst_env->disable_interrupt = 0; | |
3021 | } | |
3022 | ||
3023 | /* Handles the MOVEM to memory from general register instruction. */ | |
3024 | ||
a78f21af | 3025 | static void |
29134980 OF |
3026 | move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env) |
3027 | { | |
3028 | if (inst_env->prefix_found) | |
3029 | { | |
3030 | /* The assign value is the value after the increment. Normally, the | |
dda83cd7 | 3031 | assign value is the value before the increment. */ |
5aafa1cc | 3032 | if ((cris_get_operand1 (inst) == REG_PC) |
dda83cd7 SM |
3033 | && (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)) |
3034 | { | |
3035 | /* The prefix handles the problem if we are in a delay slot. */ | |
3036 | inst_env->reg[REG_PC] = inst_env->prefix_value; | |
3037 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3038 | } | |
29134980 OF |
3039 | } |
3040 | else | |
3041 | { | |
3042 | /* The increment is not depending on the size, instead it's depending | |
dda83cd7 | 3043 | on the number of registers loaded to memory. */ |
0963b4bd MS |
3044 | if ((cris_get_operand1 (inst) == REG_PC) |
3045 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
dda83cd7 SM |
3046 | { |
3047 | /* It's invalid to change the PC in a delay slot. */ | |
3048 | if (inst_env->slot_needed) | |
3049 | { | |
3050 | inst_env->invalid = 1; | |
3051 | return; | |
3052 | } | |
3053 | inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1); | |
3054 | } | |
29134980 OF |
3055 | } |
3056 | inst_env->slot_needed = 0; | |
3057 | inst_env->prefix_found = 0; | |
3058 | inst_env->xflag_found = 0; | |
3059 | inst_env->disable_interrupt = 0; | |
3060 | } | |
3061 | ||
85102364 | 3062 | /* Handles the instructions that's not yet implemented, by setting |
29134980 OF |
3063 | inst_env->invalid to true. */ |
3064 | ||
a78f21af | 3065 | static void |
29134980 OF |
3066 | not_implemented_op (unsigned short inst, inst_env_type *inst_env) |
3067 | { | |
3068 | inst_env->invalid = 1; | |
3069 | } | |
3070 | ||
3071 | /* Handles the XOR instruction. */ | |
3072 | ||
a78f21af | 3073 | static void |
29134980 OF |
3074 | xor_op (unsigned short inst, inst_env_type *inst_env) |
3075 | { | |
3076 | /* XOR can't have a prefix. */ | |
3077 | if (inst_env->prefix_found) | |
3078 | { | |
3079 | inst_env->invalid = 1; | |
3080 | return; | |
3081 | } | |
3082 | ||
3083 | /* Check if the PC is the target. */ | |
3084 | if (cris_get_operand2 (inst) == REG_PC) | |
3085 | { | |
3086 | /* It's invalid to change the PC in a delay slot. */ | |
3087 | if (inst_env->slot_needed) | |
dda83cd7 SM |
3088 | { |
3089 | inst_env->invalid = 1; | |
3090 | return; | |
3091 | } | |
29134980 OF |
3092 | inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)]; |
3093 | } | |
3094 | inst_env->slot_needed = 0; | |
3095 | inst_env->prefix_found = 0; | |
3096 | inst_env->xflag_found = 0; | |
3097 | inst_env->disable_interrupt = 0; | |
3098 | } | |
3099 | ||
3100 | /* Handles the MULS instruction. */ | |
3101 | ||
a78f21af | 3102 | static void |
29134980 OF |
3103 | muls_op (unsigned short inst, inst_env_type *inst_env) |
3104 | { | |
3105 | /* MULS/U can't have a prefix. */ | |
3106 | if (inst_env->prefix_found) | |
3107 | { | |
3108 | inst_env->invalid = 1; | |
3109 | return; | |
3110 | } | |
3111 | ||
3112 | /* Consider it invalid if the PC is the target. */ | |
3113 | if (cris_get_operand2 (inst) == REG_PC) | |
3114 | { | |
3115 | inst_env->invalid = 1; | |
3116 | return; | |
3117 | } | |
3118 | inst_env->slot_needed = 0; | |
3119 | inst_env->prefix_found = 0; | |
3120 | inst_env->xflag_found = 0; | |
3121 | inst_env->disable_interrupt = 0; | |
3122 | } | |
3123 | ||
3124 | /* Handles the MULU instruction. */ | |
3125 | ||
a78f21af | 3126 | static void |
29134980 OF |
3127 | mulu_op (unsigned short inst, inst_env_type *inst_env) |
3128 | { | |
3129 | /* MULS/U can't have a prefix. */ | |
3130 | if (inst_env->prefix_found) | |
3131 | { | |
3132 | inst_env->invalid = 1; | |
3133 | return; | |
3134 | } | |
3135 | ||
3136 | /* Consider it invalid if the PC is the target. */ | |
3137 | if (cris_get_operand2 (inst) == REG_PC) | |
3138 | { | |
3139 | inst_env->invalid = 1; | |
3140 | return; | |
3141 | } | |
3142 | inst_env->slot_needed = 0; | |
3143 | inst_env->prefix_found = 0; | |
3144 | inst_env->xflag_found = 0; | |
3145 | inst_env->disable_interrupt = 0; | |
3146 | } | |
3147 | ||
0963b4bd | 3148 | /* Calculate the result of the instruction for ADD, SUB, CMP AND, OR and MOVE. |
29134980 OF |
3149 | The MOVE instruction is the move from source to register. */ |
3150 | ||
a78f21af | 3151 | static void |
29134980 | 3152 | add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env, |
dda83cd7 | 3153 | unsigned long source1, unsigned long source2) |
29134980 OF |
3154 | { |
3155 | unsigned long pc_mask; | |
3156 | unsigned long operation_mask; | |
3157 | ||
3158 | /* Find out how many bits the operation should apply to. */ | |
3159 | if (cris_get_size (inst) == INST_BYTE_SIZE) | |
3160 | { | |
3161 | pc_mask = 0xFFFFFF00; | |
3162 | operation_mask = 0xFF; | |
3163 | } | |
3164 | else if (cris_get_size (inst) == INST_WORD_SIZE) | |
3165 | { | |
3166 | pc_mask = 0xFFFF0000; | |
3167 | operation_mask = 0xFFFF; | |
3168 | } | |
3169 | else if (cris_get_size (inst) == INST_DWORD_SIZE) | |
3170 | { | |
3171 | pc_mask = 0x0; | |
3172 | operation_mask = 0xFFFFFFFF; | |
3173 | } | |
3174 | else | |
3175 | { | |
3176 | /* The size is out of range. */ | |
3177 | inst_env->invalid = 1; | |
3178 | return; | |
3179 | } | |
3180 | ||
3181 | /* The instruction just works on uw_operation_mask bits. */ | |
3182 | source2 &= operation_mask; | |
3183 | source1 &= operation_mask; | |
3184 | ||
3185 | /* Now calculate the result. The opcode's 3 first bits separates | |
3186 | the different actions. */ | |
3187 | switch (cris_get_opcode (inst) & 7) | |
3188 | { | |
3189 | case 0: /* add */ | |
3190 | source1 += source2; | |
3191 | break; | |
3192 | ||
3193 | case 1: /* move */ | |
3194 | source1 = source2; | |
3195 | break; | |
3196 | ||
3197 | case 2: /* subtract */ | |
3198 | source1 -= source2; | |
3199 | break; | |
3200 | ||
3201 | case 3: /* compare */ | |
3202 | break; | |
3203 | ||
3204 | case 4: /* and */ | |
3205 | source1 &= source2; | |
3206 | break; | |
3207 | ||
3208 | case 5: /* or */ | |
3209 | source1 |= source2; | |
3210 | break; | |
3211 | ||
3212 | default: | |
3213 | inst_env->invalid = 1; | |
3214 | return; | |
3215 | ||
3216 | break; | |
3217 | } | |
3218 | ||
3219 | /* Make sure that the result doesn't contain more than the instruction | |
3220 | size bits. */ | |
3221 | source2 &= operation_mask; | |
3222 | ||
3223 | /* Calculate the new breakpoint address. */ | |
3224 | inst_env->reg[REG_PC] &= pc_mask; | |
3225 | inst_env->reg[REG_PC] |= source1; | |
3226 | ||
3227 | } | |
3228 | ||
3229 | /* Extends the value from either byte or word size to a dword. If the mode | |
3230 | is zero extend then the value is extended with zero. If instead the mode | |
3231 | is signed extend the sign bit of the value is taken into consideration. */ | |
3232 | ||
a78f21af | 3233 | static unsigned long |
29134980 OF |
3234 | do_sign_or_zero_extend (unsigned long value, unsigned short *inst) |
3235 | { | |
3236 | /* The size can be either byte or word, check which one it is. | |
3237 | Don't check the highest bit, it's indicating if it's a zero | |
3238 | or sign extend. */ | |
3239 | if (cris_get_size (*inst) & INST_WORD_SIZE) | |
3240 | { | |
3241 | /* Word size. */ | |
3242 | value &= 0xFFFF; | |
3243 | ||
3244 | /* Check if the instruction is signed extend. If so, check if value has | |
dda83cd7 | 3245 | the sign bit on. */ |
29134980 | 3246 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_WORD_MASK)) |
dda83cd7 SM |
3247 | { |
3248 | value |= SIGNED_WORD_EXTEND_MASK; | |
3249 | } | |
29134980 OF |
3250 | } |
3251 | else | |
3252 | { | |
3253 | /* Byte size. */ | |
3254 | value &= 0xFF; | |
3255 | ||
3256 | /* Check if the instruction is signed extend. If so, check if value has | |
dda83cd7 | 3257 | the sign bit on. */ |
29134980 | 3258 | if (cris_is_signed_extend_bit_on (*inst) && (value & SIGNED_BYTE_MASK)) |
dda83cd7 SM |
3259 | { |
3260 | value |= SIGNED_BYTE_EXTEND_MASK; | |
3261 | } | |
29134980 OF |
3262 | } |
3263 | /* The size should now be dword. */ | |
3264 | cris_set_size_to_dword (inst); | |
3265 | return value; | |
3266 | } | |
3267 | ||
3268 | /* Handles the register mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3269 | instruction. The MOVE instruction is the move from source to register. */ | |
3270 | ||
a78f21af | 3271 | static void |
29134980 | 3272 | reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
dda83cd7 | 3273 | inst_env_type *inst_env) |
29134980 OF |
3274 | { |
3275 | unsigned long operand1; | |
3276 | unsigned long operand2; | |
3277 | ||
3278 | /* It's invalid to have a prefix to the instruction. This is a register | |
3279 | mode instruction and can't have a prefix. */ | |
3280 | if (inst_env->prefix_found) | |
3281 | { | |
3282 | inst_env->invalid = 1; | |
3283 | return; | |
3284 | } | |
3285 | /* Check if the instruction has PC as its target. */ | |
3286 | if (cris_get_operand2 (inst) == REG_PC) | |
3287 | { | |
3288 | if (inst_env->slot_needed) | |
dda83cd7 SM |
3289 | { |
3290 | inst_env->invalid = 1; | |
3291 | return; | |
3292 | } | |
29134980 | 3293 | /* The instruction has the PC as its target register. */ |
7ab98e9e | 3294 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; |
29134980 OF |
3295 | operand2 = inst_env->reg[REG_PC]; |
3296 | ||
3297 | /* Check if it's a extend, signed or zero instruction. */ | |
3298 | if (cris_get_opcode (inst) < 4) | |
dda83cd7 SM |
3299 | { |
3300 | operand1 = do_sign_or_zero_extend (operand1, &inst); | |
3301 | } | |
29134980 | 3302 | /* Calculate the PC value after the instruction, i.e. where the |
dda83cd7 | 3303 | breakpoint should be. The order of the udw_operands is vital. */ |
29134980 OF |
3304 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
3305 | } | |
3306 | inst_env->slot_needed = 0; | |
3307 | inst_env->prefix_found = 0; | |
3308 | inst_env->xflag_found = 0; | |
3309 | inst_env->disable_interrupt = 0; | |
3310 | } | |
3311 | ||
3312 | /* Returns the data contained at address. The size of the data is derived from | |
3313 | the size of the operation. If the instruction is a zero or signed | |
3314 | extend instruction, the size field is changed in instruction. */ | |
3315 | ||
a78f21af | 3316 | static unsigned long |
0963b4bd MS |
3317 | get_data_from_address (unsigned short *inst, CORE_ADDR address, |
3318 | enum bfd_endian byte_order) | |
29134980 OF |
3319 | { |
3320 | int size = cris_get_size (*inst); | |
3321 | unsigned long value; | |
3322 | ||
3323 | /* If it's an extend instruction we don't want the signed extend bit, | |
3324 | because it influences the size. */ | |
3325 | if (cris_get_opcode (*inst) < 4) | |
3326 | { | |
3327 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3328 | } | |
3329 | /* Is there a need for checking the size? Size should contain the number of | |
3330 | bytes to read. */ | |
3331 | size = 1 << size; | |
e17a4113 | 3332 | value = read_memory_unsigned_integer (address, size, byte_order); |
29134980 OF |
3333 | |
3334 | /* Check if it's an extend, signed or zero instruction. */ | |
3335 | if (cris_get_opcode (*inst) < 4) | |
3336 | { | |
3337 | value = do_sign_or_zero_extend (value, inst); | |
3338 | } | |
3339 | return value; | |
3340 | } | |
3341 | ||
3342 | /* Handles the assign addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3343 | instructions. The MOVE instruction is the move from source to register. */ | |
3344 | ||
a78f21af | 3345 | static void |
29134980 | 3346 | handle_prefix_assign_mode_for_aritm_op (unsigned short inst, |
dda83cd7 | 3347 | inst_env_type *inst_env) |
29134980 OF |
3348 | { |
3349 | unsigned long operand2; | |
3350 | unsigned long operand3; | |
3351 | ||
3352 | check_assign (inst, inst_env); | |
3353 | if (cris_get_operand2 (inst) == REG_PC) | |
3354 | { | |
3355 | operand2 = inst_env->reg[REG_PC]; | |
3356 | ||
3357 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3358 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3359 | inst_env->byte_order); | |
29134980 OF |
3360 | |
3361 | /* Calculate the PC value after the instruction, i.e. where the | |
dda83cd7 | 3362 | breakpoint should be. The order of the udw_operands is vital. */ |
29134980 OF |
3363 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
3364 | } | |
3365 | inst_env->slot_needed = 0; | |
3366 | inst_env->prefix_found = 0; | |
3367 | inst_env->xflag_found = 0; | |
3368 | inst_env->disable_interrupt = 0; | |
3369 | } | |
3370 | ||
3371 | /* Handles the three-operand addressing mode for the ADD, SUB, CMP, AND and | |
3372 | OR instructions. Note that for this to work as expected, the calling | |
3373 | function must have made sure that there is a prefix to this instruction. */ | |
3374 | ||
a78f21af | 3375 | static void |
29134980 | 3376 | three_operand_add_sub_cmp_and_or_op (unsigned short inst, |
dda83cd7 | 3377 | inst_env_type *inst_env) |
29134980 OF |
3378 | { |
3379 | unsigned long operand2; | |
3380 | unsigned long operand3; | |
3381 | ||
3382 | if (cris_get_operand1 (inst) == REG_PC) | |
3383 | { | |
3384 | /* The PC will be changed by the instruction. */ | |
3385 | operand2 = inst_env->reg[cris_get_operand2 (inst)]; | |
3386 | ||
3387 | /* Get the value of the third operand. */ | |
e17a4113 UW |
3388 | operand3 = get_data_from_address (&inst, inst_env->prefix_value, |
3389 | inst_env->byte_order); | |
29134980 OF |
3390 | |
3391 | /* Calculate the PC value after the instruction, i.e. where the | |
dda83cd7 | 3392 | breakpoint should be. */ |
29134980 OF |
3393 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
3394 | } | |
3395 | inst_env->slot_needed = 0; | |
3396 | inst_env->prefix_found = 0; | |
3397 | inst_env->xflag_found = 0; | |
3398 | inst_env->disable_interrupt = 0; | |
3399 | } | |
3400 | ||
3401 | /* Handles the index addresing mode for the ADD, SUB, CMP, AND, OR and MOVE | |
3402 | instructions. The MOVE instruction is the move from source to register. */ | |
3403 | ||
a78f21af | 3404 | static void |
29134980 | 3405 | handle_prefix_index_mode_for_aritm_op (unsigned short inst, |
dda83cd7 | 3406 | inst_env_type *inst_env) |
29134980 OF |
3407 | { |
3408 | if (cris_get_operand1 (inst) != cris_get_operand2 (inst)) | |
3409 | { | |
3410 | /* If the instruction is MOVE it's invalid. If the instruction is ADD, | |
dda83cd7 SM |
3411 | SUB, AND or OR something weird is going on (if everything works these |
3412 | instructions should end up in the three operand version). */ | |
29134980 OF |
3413 | inst_env->invalid = 1; |
3414 | return; | |
3415 | } | |
3416 | else | |
3417 | { | |
3418 | /* three_operand_add_sub_cmp_and_or does the same as we should do here | |
dda83cd7 | 3419 | so use it. */ |
29134980 OF |
3420 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); |
3421 | } | |
3422 | inst_env->slot_needed = 0; | |
3423 | inst_env->prefix_found = 0; | |
3424 | inst_env->xflag_found = 0; | |
3425 | inst_env->disable_interrupt = 0; | |
3426 | } | |
3427 | ||
3428 | /* Handles the autoincrement and indirect addresing mode for the ADD, SUB, | |
3429 | CMP, AND OR and MOVE instruction. The MOVE instruction is the move from | |
3430 | source to register. */ | |
3431 | ||
a78f21af | 3432 | static void |
29134980 | 3433 | handle_inc_and_index_mode_for_aritm_op (unsigned short inst, |
dda83cd7 | 3434 | inst_env_type *inst_env) |
29134980 OF |
3435 | { |
3436 | unsigned long operand1; | |
3437 | unsigned long operand2; | |
3438 | unsigned long operand3; | |
3439 | int size; | |
3440 | ||
0963b4bd | 3441 | /* The instruction is either an indirect or autoincrement addressing mode. |
29134980 OF |
3442 | Check if the destination register is the PC. */ |
3443 | if (cris_get_operand2 (inst) == REG_PC) | |
3444 | { | |
3445 | /* Must be done here, get_data_from_address may change the size | |
dda83cd7 | 3446 | field. */ |
29134980 OF |
3447 | size = cris_get_size (inst); |
3448 | operand2 = inst_env->reg[REG_PC]; | |
3449 | ||
3450 | /* Get the value of the third operand, i.e. the indirect operand. */ | |
3451 | operand1 = inst_env->reg[cris_get_operand1 (inst)]; | |
e17a4113 | 3452 | operand3 = get_data_from_address (&inst, operand1, inst_env->byte_order); |
29134980 OF |
3453 | |
3454 | /* Calculate the PC value after the instruction, i.e. where the | |
dda83cd7 | 3455 | breakpoint should be. The order of the udw_operands is vital. */ |
29134980 OF |
3456 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand3); |
3457 | } | |
3458 | /* If this is an autoincrement addressing mode, check if the increment | |
3459 | changes the PC. */ | |
0963b4bd MS |
3460 | if ((cris_get_operand1 (inst) == REG_PC) |
3461 | && (cris_get_mode (inst) == AUTOINC_MODE)) | |
29134980 OF |
3462 | { |
3463 | /* Get the size field. */ | |
3464 | size = cris_get_size (inst); | |
3465 | ||
3466 | /* If it's an extend instruction we don't want the signed extend bit, | |
dda83cd7 | 3467 | because it influences the size. */ |
29134980 | 3468 | if (cris_get_opcode (inst) < 4) |
dda83cd7 SM |
3469 | { |
3470 | size &= ~SIGNED_EXTEND_BIT_MASK; | |
3471 | } | |
29134980 OF |
3472 | process_autoincrement (size, inst, inst_env); |
3473 | } | |
3474 | inst_env->slot_needed = 0; | |
3475 | inst_env->prefix_found = 0; | |
3476 | inst_env->xflag_found = 0; | |
3477 | inst_env->disable_interrupt = 0; | |
3478 | } | |
3479 | ||
3480 | /* Handles the two-operand addressing mode, all modes except register, for | |
3481 | the ADD, SUB CMP, AND and OR instruction. */ | |
3482 | ||
a78f21af | 3483 | static void |
29134980 | 3484 | none_reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst, |
dda83cd7 | 3485 | inst_env_type *inst_env) |
29134980 OF |
3486 | { |
3487 | if (inst_env->prefix_found) | |
3488 | { | |
3489 | if (cris_get_mode (inst) == PREFIX_INDEX_MODE) | |
dda83cd7 SM |
3490 | { |
3491 | handle_prefix_index_mode_for_aritm_op (inst, inst_env); | |
3492 | } | |
29134980 | 3493 | else if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE) |
dda83cd7 SM |
3494 | { |
3495 | handle_prefix_assign_mode_for_aritm_op (inst, inst_env); | |
3496 | } | |
29134980 | 3497 | else |
dda83cd7 SM |
3498 | { |
3499 | /* The mode is invalid for a prefixed base instruction. */ | |
3500 | inst_env->invalid = 1; | |
3501 | return; | |
3502 | } | |
29134980 OF |
3503 | } |
3504 | else | |
3505 | { | |
3506 | handle_inc_and_index_mode_for_aritm_op (inst, inst_env); | |
3507 | } | |
3508 | } | |
3509 | ||
3510 | /* Handles the quick addressing mode for the ADD and SUB instruction. */ | |
3511 | ||
a78f21af | 3512 | static void |
29134980 OF |
3513 | quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env) |
3514 | { | |
3515 | unsigned long operand1; | |
3516 | unsigned long operand2; | |
3517 | ||
3518 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3519 | instruction and can't have a prefix. */ | |
3520 | if (inst_env->prefix_found) | |
3521 | { | |
3522 | inst_env->invalid = 1; | |
3523 | return; | |
3524 | } | |
3525 | ||
3526 | /* Check if the instruction has PC as its target. */ | |
3527 | if (cris_get_operand2 (inst) == REG_PC) | |
3528 | { | |
3529 | if (inst_env->slot_needed) | |
dda83cd7 SM |
3530 | { |
3531 | inst_env->invalid = 1; | |
3532 | return; | |
3533 | } | |
29134980 OF |
3534 | operand1 = cris_get_quick_value (inst); |
3535 | operand2 = inst_env->reg[REG_PC]; | |
3536 | ||
3537 | /* The size should now be dword. */ | |
3538 | cris_set_size_to_dword (&inst); | |
3539 | ||
3540 | /* Calculate the PC value after the instruction, i.e. where the | |
dda83cd7 | 3541 | breakpoint should be. */ |
29134980 OF |
3542 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
3543 | } | |
3544 | inst_env->slot_needed = 0; | |
3545 | inst_env->prefix_found = 0; | |
3546 | inst_env->xflag_found = 0; | |
3547 | inst_env->disable_interrupt = 0; | |
3548 | } | |
3549 | ||
3550 | /* Handles the quick addressing mode for the CMP, AND and OR instruction. */ | |
3551 | ||
a78f21af | 3552 | static void |
29134980 OF |
3553 | quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env) |
3554 | { | |
3555 | unsigned long operand1; | |
3556 | unsigned long operand2; | |
3557 | ||
3558 | /* It's a bad idea to be in a prefix instruction now. This is a quick mode | |
3559 | instruction and can't have a prefix. */ | |
3560 | if (inst_env->prefix_found) | |
3561 | { | |
3562 | inst_env->invalid = 1; | |
3563 | return; | |
3564 | } | |
3565 | /* Check if the instruction has PC as its target. */ | |
3566 | if (cris_get_operand2 (inst) == REG_PC) | |
3567 | { | |
3568 | if (inst_env->slot_needed) | |
dda83cd7 SM |
3569 | { |
3570 | inst_env->invalid = 1; | |
3571 | return; | |
3572 | } | |
29134980 OF |
3573 | /* The instruction has the PC as its target register. */ |
3574 | operand1 = cris_get_quick_value (inst); | |
3575 | operand2 = inst_env->reg[REG_PC]; | |
3576 | ||
3577 | /* The quick value is signed, so check if we must do a signed extend. */ | |
3578 | if (operand1 & SIGNED_QUICK_VALUE_MASK) | |
dda83cd7 SM |
3579 | { |
3580 | /* sign extend */ | |
3581 | operand1 |= SIGNED_QUICK_VALUE_EXTEND_MASK; | |
3582 | } | |
29134980 OF |
3583 | /* The size should now be dword. */ |
3584 | cris_set_size_to_dword (&inst); | |
3585 | ||
3586 | /* Calculate the PC value after the instruction, i.e. where the | |
dda83cd7 | 3587 | breakpoint should be. */ |
29134980 OF |
3588 | add_sub_cmp_and_or_move_action (inst, inst_env, operand2, operand1); |
3589 | } | |
3590 | inst_env->slot_needed = 0; | |
3591 | inst_env->prefix_found = 0; | |
3592 | inst_env->xflag_found = 0; | |
3593 | inst_env->disable_interrupt = 0; | |
3594 | } | |
3595 | ||
3596 | /* Translate op_type to a function and call it. */ | |
3597 | ||
a78f21af | 3598 | static void |
be8626e0 MD |
3599 | cris_gdb_func (struct gdbarch *gdbarch, enum cris_op_type op_type, |
3600 | unsigned short inst, inst_env_type *inst_env) | |
29134980 OF |
3601 | { |
3602 | switch (op_type) | |
3603 | { | |
3604 | case cris_not_implemented_op: | |
3605 | not_implemented_op (inst, inst_env); | |
3606 | break; | |
3607 | ||
3608 | case cris_abs_op: | |
3609 | abs_op (inst, inst_env); | |
3610 | break; | |
3611 | ||
3612 | case cris_addi_op: | |
3613 | addi_op (inst, inst_env); | |
3614 | break; | |
3615 | ||
3616 | case cris_asr_op: | |
3617 | asr_op (inst, inst_env); | |
3618 | break; | |
3619 | ||
3620 | case cris_asrq_op: | |
3621 | asrq_op (inst, inst_env); | |
3622 | break; | |
3623 | ||
3624 | case cris_ax_ei_setf_op: | |
3625 | ax_ei_setf_op (inst, inst_env); | |
3626 | break; | |
3627 | ||
3628 | case cris_bdap_prefix: | |
3629 | bdap_prefix (inst, inst_env); | |
3630 | break; | |
3631 | ||
3632 | case cris_biap_prefix: | |
3633 | biap_prefix (inst, inst_env); | |
3634 | break; | |
3635 | ||
3636 | case cris_break_op: | |
3637 | break_op (inst, inst_env); | |
3638 | break; | |
3639 | ||
3640 | case cris_btst_nop_op: | |
3641 | btst_nop_op (inst, inst_env); | |
3642 | break; | |
3643 | ||
3644 | case cris_clearf_di_op: | |
3645 | clearf_di_op (inst, inst_env); | |
3646 | break; | |
3647 | ||
3648 | case cris_dip_prefix: | |
3649 | dip_prefix (inst, inst_env); | |
3650 | break; | |
3651 | ||
3652 | case cris_dstep_logshift_mstep_neg_not_op: | |
3653 | dstep_logshift_mstep_neg_not_op (inst, inst_env); | |
3654 | break; | |
3655 | ||
3656 | case cris_eight_bit_offset_branch_op: | |
3657 | eight_bit_offset_branch_op (inst, inst_env); | |
3658 | break; | |
3659 | ||
3660 | case cris_move_mem_to_reg_movem_op: | |
3661 | move_mem_to_reg_movem_op (inst, inst_env); | |
3662 | break; | |
3663 | ||
3664 | case cris_move_reg_to_mem_movem_op: | |
3665 | move_reg_to_mem_movem_op (inst, inst_env); | |
3666 | break; | |
3667 | ||
3668 | case cris_move_to_preg_op: | |
be8626e0 | 3669 | move_to_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3670 | break; |
3671 | ||
3672 | case cris_muls_op: | |
3673 | muls_op (inst, inst_env); | |
3674 | break; | |
3675 | ||
3676 | case cris_mulu_op: | |
3677 | mulu_op (inst, inst_env); | |
3678 | break; | |
3679 | ||
3680 | case cris_none_reg_mode_add_sub_cmp_and_or_move_op: | |
3681 | none_reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3682 | break; | |
3683 | ||
3684 | case cris_none_reg_mode_clear_test_op: | |
3685 | none_reg_mode_clear_test_op (inst, inst_env); | |
3686 | break; | |
3687 | ||
3688 | case cris_none_reg_mode_jump_op: | |
3689 | none_reg_mode_jump_op (inst, inst_env); | |
3690 | break; | |
3691 | ||
3692 | case cris_none_reg_mode_move_from_preg_op: | |
be8626e0 | 3693 | none_reg_mode_move_from_preg_op (gdbarch, inst, inst_env); |
29134980 OF |
3694 | break; |
3695 | ||
3696 | case cris_quick_mode_add_sub_op: | |
3697 | quick_mode_add_sub_op (inst, inst_env); | |
3698 | break; | |
3699 | ||
3700 | case cris_quick_mode_and_cmp_move_or_op: | |
3701 | quick_mode_and_cmp_move_or_op (inst, inst_env); | |
3702 | break; | |
3703 | ||
3704 | case cris_quick_mode_bdap_prefix: | |
3705 | quick_mode_bdap_prefix (inst, inst_env); | |
3706 | break; | |
3707 | ||
3708 | case cris_reg_mode_add_sub_cmp_and_or_move_op: | |
3709 | reg_mode_add_sub_cmp_and_or_move_op (inst, inst_env); | |
3710 | break; | |
3711 | ||
3712 | case cris_reg_mode_clear_op: | |
3713 | reg_mode_clear_op (inst, inst_env); | |
3714 | break; | |
3715 | ||
3716 | case cris_reg_mode_jump_op: | |
3717 | reg_mode_jump_op (inst, inst_env); | |
3718 | break; | |
3719 | ||
3720 | case cris_reg_mode_move_from_preg_op: | |
3721 | reg_mode_move_from_preg_op (inst, inst_env); | |
3722 | break; | |
3723 | ||
3724 | case cris_reg_mode_test_op: | |
3725 | reg_mode_test_op (inst, inst_env); | |
3726 | break; | |
3727 | ||
3728 | case cris_scc_op: | |
3729 | scc_op (inst, inst_env); | |
3730 | break; | |
3731 | ||
3732 | case cris_sixteen_bit_offset_branch_op: | |
3733 | sixteen_bit_offset_branch_op (inst, inst_env); | |
3734 | break; | |
3735 | ||
3736 | case cris_three_operand_add_sub_cmp_and_or_op: | |
3737 | three_operand_add_sub_cmp_and_or_op (inst, inst_env); | |
3738 | break; | |
3739 | ||
3740 | case cris_three_operand_bound_op: | |
3741 | three_operand_bound_op (inst, inst_env); | |
3742 | break; | |
3743 | ||
3744 | case cris_two_operand_bound_op: | |
3745 | two_operand_bound_op (inst, inst_env); | |
3746 | break; | |
3747 | ||
3748 | case cris_xor_op: | |
3749 | xor_op (inst, inst_env); | |
3750 | break; | |
3751 | } | |
3752 | } | |
3753 | ||
18b3c2f5 RW |
3754 | /* Originally from <asm/elf.h>. */ |
3755 | typedef unsigned char cris_elf_greg_t[4]; | |
dbbff683 OF |
3756 | |
3757 | /* Same as user_regs_struct struct in <asm/user.h>. */ | |
c600d464 | 3758 | #define CRISV10_ELF_NGREG 35 |
18b3c2f5 | 3759 | typedef cris_elf_greg_t cris_elf_gregset_t[CRISV10_ELF_NGREG]; |
c600d464 OF |
3760 | |
3761 | #define CRISV32_ELF_NGREG 32 | |
18b3c2f5 | 3762 | typedef cris_elf_greg_t crisv32_elf_gregset_t[CRISV32_ELF_NGREG]; |
dbbff683 | 3763 | |
18b3c2f5 | 3764 | /* Unpack a cris_elf_gregset_t into GDB's register cache. */ |
dbbff683 | 3765 | |
a78f21af | 3766 | static void |
69ed9b74 CB |
3767 | cris_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3768 | int regnum, const void *gregs, size_t len) | |
dbbff683 | 3769 | { |
ac7936df | 3770 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3771 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
dbbff683 | 3772 | int i; |
69ed9b74 CB |
3773 | const cris_elf_greg_t *regp = static_cast<const cris_elf_greg_t *>(gregs); |
3774 | ||
3775 | if (len != sizeof (cris_elf_gregset_t) | |
3776 | && len != sizeof (crisv32_elf_gregset_t)) | |
3777 | warning (_("wrong size gregset struct in core file")); | |
3778 | gdb_assert (len >= sizeof (crisv32_elf_gregset_t)); | |
dbbff683 OF |
3779 | |
3780 | /* The kernel dumps all 32 registers as unsigned longs, but supply_register | |
3781 | knows about the actual size of each register so that's no problem. */ | |
3782 | for (i = 0; i < NUM_GENREGS + NUM_SPECREGS; i++) | |
3783 | { | |
69ed9b74 CB |
3784 | if (regnum == -1 || regnum == i) |
3785 | regcache->raw_supply (i, (char *)®p[i]); | |
dbbff683 | 3786 | } |
c600d464 | 3787 | |
69ed9b74 | 3788 | if (tdep->cris_version == 32 && (regnum == -1 || regnum == ERP_REGNUM)) |
c600d464 OF |
3789 | { |
3790 | /* Needed to set pseudo-register PC for CRISv32. */ | |
3791 | /* FIXME: If ERP is in a delay slot at this point then the PC will | |
3792 | be wrong. Issue a warning to alert the user. */ | |
73e1c03f SM |
3793 | regcache->raw_supply (gdbarch_pc_regnum (gdbarch), |
3794 | (char *)®p[ERP_REGNUM]); | |
c600d464 OF |
3795 | |
3796 | if (*(char *)®p[ERP_REGNUM] & 0x1) | |
6cb06a8c | 3797 | gdb_printf (gdb_stderr, "Warning: PC in delay slot\n"); |
c600d464 | 3798 | } |
dbbff683 OF |
3799 | } |
3800 | ||
69ed9b74 CB |
3801 | static const struct regset cris_regset = { |
3802 | nullptr, | |
3803 | cris_supply_gregset, | |
3804 | /* We don't need a collect function because we only use this for core files | |
3805 | (via iterate_over_regset_sections). */ | |
3806 | nullptr, | |
3807 | REGSET_VARIABLE_SIZE | |
3808 | }; | |
dbbff683 | 3809 | |
69ed9b74 CB |
3810 | static void cris_iterate_over_regset_sections (struct gdbarch *gdbarch, |
3811 | iterate_over_regset_sections_cb *cb, | |
3812 | void *cb_data, | |
3813 | const struct regcache *regcache) | |
dbbff683 | 3814 | { |
69ed9b74 CB |
3815 | cb (".reg", sizeof (crisv32_elf_gregset_t), sizeof (crisv32_elf_gregset_t), |
3816 | &cris_regset, NULL, cb_data); | |
dbbff683 OF |
3817 | } |
3818 | ||
6c265988 | 3819 | void _initialize_cris_tdep (); |
29134980 | 3820 | void |
6c265988 | 3821 | _initialize_cris_tdep () |
29134980 | 3822 | { |
29134980 OF |
3823 | gdbarch_register (bfd_arch_cris, cris_gdbarch_init, cris_dump_tdep); |
3824 | ||
29134980 | 3825 | /* CRIS-specific user-commands. */ |
addb4faf PA |
3826 | add_setshow_zuinteger_cmd ("cris-version", class_support, |
3827 | &usr_cmd_cris_version, | |
3828 | _("Set the current CRIS version."), | |
3829 | _("Show the current CRIS version."), | |
3830 | _("\ | |
bdd56253 OF |
3831 | Set to 10 for CRISv10 or 32 for CRISv32 if autodetection fails.\n\ |
3832 | Defaults to 10. "), | |
addb4faf PA |
3833 | set_cris_version, |
3834 | NULL, /* FIXME: i18n: Current CRIS version | |
3835 | is %s. */ | |
3836 | &setlist, &showlist); | |
0e6bdb31 OF |
3837 | |
3838 | add_setshow_enum_cmd ("cris-mode", class_support, | |
3839 | cris_modes, &usr_cmd_cris_mode, | |
3840 | _("Set the current CRIS mode."), | |
3841 | _("Show the current CRIS mode."), | |
bdd56253 OF |
3842 | _("\ |
3843 | Set to CRIS_MODE_GURU when debugging in guru mode.\n\ | |
3844 | Makes GDB use the NRP register instead of the ERP register in certain cases."), | |
0e6bdb31 OF |
3845 | set_cris_mode, |
3846 | NULL, /* FIXME: i18n: Current CRIS version is %s. */ | |
3847 | &setlist, &showlist); | |
dbbff683 | 3848 | |
a5f6c8f5 OF |
3849 | add_setshow_boolean_cmd ("cris-dwarf2-cfi", class_support, |
3850 | &usr_cmd_cris_dwarf2_cfi, | |
7915a72c AC |
3851 | _("Set the usage of Dwarf-2 CFI for CRIS."), |
3852 | _("Show the usage of Dwarf-2 CFI for CRIS."), | |
bdd56253 | 3853 | _("Set this to \"off\" if using gcc-cris < R59."), |
2c5b56ce | 3854 | set_cris_dwarf2_cfi, |
0963b4bd MS |
3855 | NULL, /* FIXME: i18n: Usage of Dwarf-2 CFI |
3856 | for CRIS is %d. */ | |
a5f6c8f5 | 3857 | &setlist, &showlist); |
29134980 OF |
3858 | } |
3859 | ||
3860 | /* Prints out all target specific values. */ | |
3861 | ||
3862 | static void | |
3863 | cris_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) | |
3864 | { | |
08106042 | 3865 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); |
29134980 OF |
3866 | if (tdep != NULL) |
3867 | { | |
6cb06a8c TT |
3868 | gdb_printf (file, "cris_dump_tdep: tdep->cris_version = %i\n", |
3869 | tdep->cris_version); | |
3870 | gdb_printf (file, "cris_dump_tdep: tdep->cris_mode = %s\n", | |
3871 | tdep->cris_mode); | |
3872 | gdb_printf (file, "cris_dump_tdep: tdep->cris_dwarf2_cfi = %i\n", | |
3873 | tdep->cris_dwarf2_cfi); | |
29134980 OF |
3874 | } |
3875 | } | |
3876 | ||
3877 | static void | |
eb4c3f4a | 3878 | set_cris_version (const char *ignore_args, int from_tty, |
a5f6c8f5 | 3879 | struct cmd_list_element *c) |
29134980 OF |
3880 | { |
3881 | struct gdbarch_info info; | |
3882 | ||
a5f6c8f5 | 3883 | usr_cmd_cris_version_valid = 1; |
29134980 | 3884 | |
a5f6c8f5 | 3885 | /* Update the current architecture, if needed. */ |
a5f6c8f5 | 3886 | if (!gdbarch_update_p (info)) |
f34652de | 3887 | internal_error (_("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
3888 | } |
3889 | ||
0e6bdb31 | 3890 | static void |
eb4c3f4a | 3891 | set_cris_mode (const char *ignore_args, int from_tty, |
0e6bdb31 OF |
3892 | struct cmd_list_element *c) |
3893 | { | |
3894 | struct gdbarch_info info; | |
3895 | ||
3896 | /* Update the current architecture, if needed. */ | |
0e6bdb31 | 3897 | if (!gdbarch_update_p (info)) |
f34652de | 3898 | internal_error ("cris_gdbarch_update: failed to update architecture."); |
0e6bdb31 OF |
3899 | } |
3900 | ||
29134980 | 3901 | static void |
eb4c3f4a | 3902 | set_cris_dwarf2_cfi (const char *ignore_args, int from_tty, |
a5f6c8f5 | 3903 | struct cmd_list_element *c) |
29134980 OF |
3904 | { |
3905 | struct gdbarch_info info; | |
a5f6c8f5 OF |
3906 | |
3907 | /* Update the current architecture, if needed. */ | |
a5f6c8f5 | 3908 | if (!gdbarch_update_p (info)) |
f34652de | 3909 | internal_error (_("cris_gdbarch_update: failed to update architecture.")); |
29134980 OF |
3910 | } |
3911 | ||
29134980 OF |
3912 | static struct gdbarch * |
3913 | cris_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
3914 | { | |
e4286e57 | 3915 | unsigned int cris_version; |
29134980 OF |
3916 | |
3917 | if (usr_cmd_cris_version_valid) | |
3918 | { | |
3919 | /* Trust the user's CRIS version setting. */ | |
3920 | cris_version = usr_cmd_cris_version; | |
3921 | } | |
c600d464 OF |
3922 | else if (info.abfd && bfd_get_mach (info.abfd) == bfd_mach_cris_v32) |
3923 | { | |
3924 | cris_version = 32; | |
3925 | } | |
29134980 OF |
3926 | else |
3927 | { | |
3928 | /* Assume it's CRIS version 10. */ | |
3929 | cris_version = 10; | |
3930 | } | |
3931 | ||
29134980 OF |
3932 | /* Make the current settings visible to the user. */ |
3933 | usr_cmd_cris_version = cris_version; | |
29134980 | 3934 | |
0e6bdb31 | 3935 | /* Find a candidate among the list of pre-declared architectures. */ |
29134980 OF |
3936 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
3937 | arches != NULL; | |
3938 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
3939 | { | |
345bd07c | 3940 | cris_gdbarch_tdep *tdep |
08106042 | 3941 | = gdbarch_tdep<cris_gdbarch_tdep> (arches->gdbarch); |
345bd07c SM |
3942 | |
3943 | if (tdep->cris_version == usr_cmd_cris_version | |
3944 | && tdep->cris_mode == usr_cmd_cris_mode | |
3945 | && tdep->cris_dwarf2_cfi == usr_cmd_cris_dwarf2_cfi) | |
dda83cd7 | 3946 | return arches->gdbarch; |
29134980 OF |
3947 | } |
3948 | ||
3949 | /* No matching architecture was found. Create a new one. */ | |
7cf1de6c | 3950 | info.byte_order = BFD_ENDIAN_LITTLE; |
2b16913c SM |
3951 | gdbarch *gdbarch |
3952 | = gdbarch_alloc (&info, gdbarch_tdep_up (new cris_gdbarch_tdep)); | |
3953 | cris_gdbarch_tdep *tdep = gdbarch_tdep<cris_gdbarch_tdep> (gdbarch); | |
29134980 | 3954 | |
a5f6c8f5 | 3955 | tdep->cris_version = usr_cmd_cris_version; |
0e6bdb31 | 3956 | tdep->cris_mode = usr_cmd_cris_mode; |
a5f6c8f5 | 3957 | tdep->cris_dwarf2_cfi = usr_cmd_cris_dwarf2_cfi; |
29134980 | 3958 | |
b4206d25 | 3959 | set_gdbarch_return_value (gdbarch, cris_return_value); |
29134980 | 3960 | set_gdbarch_sp_regnum (gdbarch, 14); |
c600d464 OF |
3961 | |
3962 | /* Length of ordinary registers used in push_word and a few other | |
3963 | places. register_size() is the real way to know how big a | |
3964 | register is. */ | |
a5f6c8f5 | 3965 | |
2e4b5889 | 3966 | set_gdbarch_double_bit (gdbarch, 64); |
ea06eb3d | 3967 | /* The default definition of a long double is 2 * gdbarch_double_bit, |
2e4b5889 | 3968 | which means we have to set this explicitly. */ |
c600d464 | 3969 | set_gdbarch_long_double_bit (gdbarch, 64); |
29134980 | 3970 | |
29134980 OF |
3971 | /* The total amount of space needed to store (in an array called registers) |
3972 | GDB's copy of the machine's register state. Note: We can not use | |
d93859e2 | 3973 | cris_register_size at this point, since it relies on gdbarch |
29134980 OF |
3974 | being set. */ |
3975 | switch (tdep->cris_version) | |
3976 | { | |
3977 | case 0: | |
3978 | case 1: | |
3979 | case 2: | |
3980 | case 3: | |
29134980 OF |
3981 | case 8: |
3982 | case 9: | |
a5f6c8f5 | 3983 | /* Old versions; not supported. */ |
114d7832 | 3984 | return 0; |
29134980 OF |
3985 | |
3986 | case 10: | |
3987 | case 11: | |
3988 | /* CRIS v10 and v11, a.k.a. ETRAX 100LX. In addition to ETRAX 100, | |
dda83cd7 | 3989 | P7 (32 bits), and P15 (32 bits) have been implemented. */ |
c600d464 OF |
3990 | set_gdbarch_pc_regnum (gdbarch, 15); |
3991 | set_gdbarch_register_type (gdbarch, cris_register_type); | |
3992 | /* There are 32 registers (some of which may not be implemented). */ | |
3993 | set_gdbarch_num_regs (gdbarch, 32); | |
3994 | set_gdbarch_register_name (gdbarch, cris_register_name); | |
3995 | set_gdbarch_cannot_store_register (gdbarch, cris_cannot_store_register); | |
3996 | set_gdbarch_cannot_fetch_register (gdbarch, cris_cannot_fetch_register); | |
3997 | ||
3998 | set_gdbarch_software_single_step (gdbarch, cris_software_single_step); | |
3999 | break; | |
4000 | ||
4001 | case 32: | |
4002 | /* CRIS v32. General registers R0 - R15 (32 bits), special registers | |
4003 | P0 - P15 (32 bits) except P0, P1, P3 (8 bits) and P4 (16 bits) | |
4004 | and pseudo-register PC (32 bits). */ | |
4005 | set_gdbarch_pc_regnum (gdbarch, 32); | |
4006 | set_gdbarch_register_type (gdbarch, crisv32_register_type); | |
4007 | /* 32 registers + pseudo-register PC + 16 support registers. */ | |
4008 | set_gdbarch_num_regs (gdbarch, 32 + 1 + 16); | |
4009 | set_gdbarch_register_name (gdbarch, crisv32_register_name); | |
4010 | ||
4011 | set_gdbarch_cannot_store_register | |
4012 | (gdbarch, crisv32_cannot_store_register); | |
4013 | set_gdbarch_cannot_fetch_register | |
4014 | (gdbarch, crisv32_cannot_fetch_register); | |
4015 | ||
4016 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); | |
4017 | ||
4018 | set_gdbarch_single_step_through_delay | |
4019 | (gdbarch, crisv32_single_step_through_delay); | |
4020 | ||
29134980 OF |
4021 | break; |
4022 | ||
4023 | default: | |
114d7832 PA |
4024 | /* Unknown version. */ |
4025 | return 0; | |
29134980 OF |
4026 | } |
4027 | ||
c600d464 OF |
4028 | /* Dummy frame functions (shared between CRISv10 and CRISv32 since they |
4029 | have the same ABI). */ | |
2e4b5889 OF |
4030 | set_gdbarch_push_dummy_code (gdbarch, cris_push_dummy_code); |
4031 | set_gdbarch_push_dummy_call (gdbarch, cris_push_dummy_call); | |
4032 | set_gdbarch_frame_align (gdbarch, cris_frame_align); | |
29134980 | 4033 | set_gdbarch_skip_prologue (gdbarch, cris_skip_prologue); |
29134980 OF |
4034 | |
4035 | /* The stack grows downward. */ | |
4036 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
4037 | ||
04180708 YQ |
4038 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, cris_breakpoint_kind_from_pc); |
4039 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, cris_sw_breakpoint_from_kind); | |
69ed9b74 | 4040 | set_gdbarch_iterate_over_regset_sections (gdbarch, cris_iterate_over_regset_sections); |
29134980 | 4041 | |
a5f6c8f5 OF |
4042 | if (tdep->cris_dwarf2_cfi == 1) |
4043 | { | |
4044 | /* Hook in the Dwarf-2 frame sniffer. */ | |
4045 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, cris_dwarf2_reg_to_regnum); | |
4046 | dwarf2_frame_set_init_reg (gdbarch, cris_dwarf2_frame_init_reg); | |
94afd7a6 | 4047 | dwarf2_append_unwinders (gdbarch); |
a5f6c8f5 OF |
4048 | } |
4049 | ||
0e6bdb31 OF |
4050 | if (tdep->cris_mode != cris_mode_guru) |
4051 | { | |
94afd7a6 | 4052 | frame_unwind_append_unwinder (gdbarch, &cris_sigtramp_frame_unwind); |
0e6bdb31 | 4053 | } |
a5f6c8f5 | 4054 | |
94afd7a6 | 4055 | frame_unwind_append_unwinder (gdbarch, &cris_frame_unwind); |
2e4b5889 | 4056 | frame_base_set_default (gdbarch, &cris_frame_base); |
6c0e89ed | 4057 | |
749c8b38 RW |
4058 | /* Hook in ABI-specific overrides, if they have been registered. */ |
4059 | gdbarch_init_osabi (info, gdbarch); | |
4060 | ||
29134980 OF |
4061 | return gdbarch; |
4062 | } |