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9d24df82 HAQ |
1 | /* Target-dependent code for the CSKY architecture, for GDB. |
2 | ||
1d506c26 | 3 | Copyright (C) 2010-2024 Free Software Foundation, Inc. |
9d24df82 HAQ |
4 | |
5 | This file is part of GDB. | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3 of the License, or | |
10 | (at your option) any later version. | |
11 | ||
12 | This program is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
19 | ||
20 | #ifndef CSKY_TDEP_H | |
21 | #define CSKY_TDEP_H | |
22 | ||
76eb8ef1 SM |
23 | #include "gdbarch.h" |
24 | ||
9d24df82 HAQ |
25 | /* How to interpret the contents of the link register. */ |
26 | enum lr_type_t | |
27 | { | |
28 | LR_TYPE_R15, | |
29 | LR_TYPE_EPC, | |
30 | LR_TYPE_FPC | |
31 | }; | |
32 | ||
33 | /* Target-dependent structure in gdbarch. */ | |
ab25d9bb | 34 | struct csky_gdbarch_tdep : gdbarch_tdep_base |
9d24df82 | 35 | { |
68538bbe JL |
36 | /* Save FPU, VDSP ABI. */ |
37 | unsigned int fpu_abi; | |
38 | unsigned int fpu_hardfp; | |
39 | unsigned int vdsp_version; | |
e3940312 JL |
40 | |
41 | /* Save fv_pseudo_registers_count. */ | |
42 | unsigned int has_vr0; | |
43 | unsigned int fv_pseudo_registers_count; | |
9d24df82 HAQ |
44 | }; |
45 | ||
46 | /* Instruction sizes. */ | |
47 | enum csky_insn_size_t | |
48 | { | |
49 | CSKY_INSN_SIZE16 = 2, | |
50 | CSKY_INSN_SIZE32 = 4 | |
51 | }; | |
52 | ||
53 | /* CSKY register numbers. */ | |
54 | enum csky_regnum | |
55 | { | |
56 | CSKY_R0_REGNUM = 0, /* General registers. */ | |
57 | CSKY_R15_REGNUM = 15, | |
afd53c3c JL |
58 | CSKY_HI_REGNUM = 36, |
59 | CSKY_LO_REGNUM = 37, | |
9d24df82 | 60 | CSKY_PC_REGNUM = 72, |
afd53c3c | 61 | CSKY_AR0_REGNUM = 73, |
9d24df82 HAQ |
62 | CSKY_CR0_REGNUM = 89, |
63 | CSKY_VBR_REGNUM = CSKY_CR0_REGNUM + 1, | |
64 | CSKY_EPSR_REGNUM = CSKY_CR0_REGNUM + 2, | |
65 | CSKY_FPSR_REGNUM = CSKY_CR0_REGNUM + 3, | |
66 | CSKY_EPC_REGNUM = CSKY_CR0_REGNUM + 4, | |
67 | CSKY_FPC_REGNUM = CSKY_CR0_REGNUM + 5, | |
68 | ||
69 | /* Float register 0. */ | |
70 | CSKY_FR0_REGNUM = 40, | |
afd53c3c JL |
71 | CSKY_FR16_REGNUM = 1172, |
72 | CSKY_FCR_REGNUM = 121, | |
9d24df82 HAQ |
73 | CSKY_MMU_REGNUM = 128, |
74 | CSKY_PROFCR_REGNUM = 140, | |
75 | CSKY_PROFGR_REGNUM = 144, | |
76 | CSKY_FP_REGNUM = 8, | |
77 | ||
78 | /* Vector register 0. */ | |
79 | CSKY_VR0_REGNUM = 56, | |
80 | ||
81 | /* m32r calling convention. */ | |
82 | CSKY_SP_REGNUM = CSKY_R0_REGNUM + 14, | |
83 | CSKY_RET_REGNUM = CSKY_R0_REGNUM, | |
84 | ||
85 | /* Argument registers. */ | |
86 | CSKY_ABI_A0_REGNUM = 0, | |
87 | CSKY_ABI_LAST_ARG_REGNUM = 3, | |
88 | ||
89 | /* Link register, r15. */ | |
90 | CSKY_LR_REGNUM = CSKY_R15_REGNUM, | |
91 | ||
92 | /* Processor status register, cr0. */ | |
93 | CSKY_PSR_REGNUM = CSKY_CR0_REGNUM, | |
94 | ||
95 | CSKY_MAX_REGISTER_SIZE = 16, | |
0d3c3667 JL |
96 | |
97 | /* Actually, the max regs number should be 1187. But if the | |
98 | gdb stub does not send a tdesc-xml file to gdb, 253 works. */ | |
9d24df82 HAQ |
99 | CSKY_MAX_REGS = 253 |
100 | }; | |
101 | ||
102 | /* ICE registers. */ | |
103 | #define CSKY_CRBANK_NUM_REGS 32 | |
104 | ||
afd53c3c JL |
105 | /* Tdesc registers essential check. */ |
106 | #define CSKY_TDESC_REGS_PC_NUMBERED (1 << 0) | |
107 | #define CSKY_TDESC_REGS_SP_NUMBERED (1 << 1) | |
108 | #define CSKY_TDESC_REGS_LR_NUMBERED (1 << 2) | |
109 | #define CSKY_TDESC_REGS_ESSENTIAL_VALUE (7) | |
110 | ||
e3940312 JL |
111 | /* For fr0~fr15, fr16~fr31, vr0~vr15 check. */ |
112 | #define CSKY_FULL16_ONEHOT_VALUE 0xffff | |
113 | ||
d5ffc11f JL |
114 | /* Define for CSKY FV pseudo regs for dwarf regs. */ |
115 | #define FV_PSEUDO_REGNO_FIRST 74 | |
116 | #define FV_PSEUDO_REGNO_LAST 201 | |
117 | ||
9d24df82 HAQ |
118 | /* Number of processor registers w/o ICE registers. */ |
119 | #define CSKY_NUM_REGS (CSKY_MAX_REGS - CSKY_CRBANK_NUM_REGS) | |
120 | ||
121 | /* size. */ | |
122 | #define CSKY_16_ST_SIZE(insn) (1 << ((insn & 0x1800) >> 11)) | |
123 | /* rx. */ | |
124 | #define CSKY_16_ST_ADDR_REGNUM(insn) ((insn & 0x700) >> 8) | |
125 | /* disp. */ | |
126 | #define CSKY_16_ST_OFFSET(insn) ((insn & 0x1f) << ((insn & 0x1800) >> 11)) | |
127 | /* ry. */ | |
128 | #define CSKY_16_ST_VAL_REGNUM(insn) ((insn & 0xe0) >> 5) | |
129 | ||
130 | /* st16.w rz, (sp, disp). */ | |
131 | #define CSKY_16_IS_STWx0(insn) ((insn & 0xf800) == 0xb800) | |
132 | #define CSKY_16_STWx0_VAL_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn) | |
133 | ||
134 | /* disp. */ | |
135 | #define CSKY_16_STWx0_OFFSET(insn) \ | |
136 | ((((insn & 0x700) >> 3) + (insn & 0x1f)) << 2) | |
137 | ||
138 | /* Check ld16 but not ld16 sp. */ | |
139 | #define CSKY_16_IS_LD(insn) \ | |
140 | (((insn & 0xe000) == 0x8000) && (insn & 0x1800) != 0x1800) | |
141 | /* size. */ | |
142 | #define CSKY_16_LD_SIZE(insn) CSKY_16_ST_SIZE (insn) | |
143 | /* rx. */ | |
144 | #define CSKY_16_LD_ADDR_REGNUM(insn) CSKY_16_ST_ADDR_REGNUM (insn) | |
145 | /* disp. */ | |
146 | #define CSKY_16_LD_OFFSET(insn) CSKY_16_ST_OFFSET (insn) | |
147 | ||
148 | /* ld16.w rz,(sp,disp). */ | |
149 | #define CSKY_16_IS_LDWx0(insn) ((insn & 0xf800) == 0x9800) | |
150 | /*disp. */ | |
151 | #define CSKY_16_LDWx0_OFFSET(insn) CSKY_16_STWx0_OFFSET (insn) | |
152 | ||
153 | /* st32.b/h/w/d. */ | |
154 | #define CSKY_32_IS_ST(insn) ((insn & 0xfc00c000) == 0xdc000000) | |
155 | ||
156 | /* size: b/h/w/d. */ | |
157 | #define CSKY_32_ST_SIZE(insn) (1 << ((insn & 0x3000) >> 12)) | |
158 | /* rx. */ | |
159 | #define CSKY_32_ST_ADDR_REGNUM(insn) ((insn & 0x001f0000) >> 16) | |
160 | /* disp. */ | |
161 | #define CSKY_32_ST_OFFSET(insn) ((insn & 0xfff) << ((insn & 0x3000) >> 12)) | |
162 | /* ry. */ | |
163 | #define CSKY_32_ST_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21) | |
164 | ||
165 | /* stw ry, (sp, disp). */ | |
166 | #define CSKY_32_IS_STWx0(insn) ((insn & 0xfc1ff000) == 0xdc0e2000) | |
167 | ||
168 | /* stm32 ry-rz, (rx). */ | |
169 | #define CSKY_32_IS_STM(insn) ((insn & 0xfc00ffe0) == 0xd4001c20) | |
170 | /* rx. */ | |
171 | #define CSKY_32_STM_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn) | |
172 | /* Count of registers. */ | |
173 | #define CSKY_32_STM_SIZE(insn) (insn & 0x1f) | |
174 | /* ry. */ | |
175 | #define CSKY_32_STM_VAL_REGNUM(insn) ((insn & 0x03e00000) >> 21) | |
176 | /* stm32 ry-rz, (sp). */ | |
177 | #define CSKY_32_IS_STMx0(insn) ((insn & 0xfc1fffe0) == 0xd40e1c20) | |
178 | ||
179 | /* str32.b/h/w rz, (rx, ry << offset). */ | |
180 | #define CSKY_32_IS_STR(insn) \ | |
181 | (((insn & 0xfc000000) == 0xd4000000) && !(CSKY_32_IS_STM (insn))) | |
182 | /* rx. */ | |
183 | #define CSKY_32_STR_X_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn) | |
184 | /* ry. */ | |
185 | #define CSKY_32_STR_Y_REGNUM(insn) ((insn >> 21) & 0x1f) | |
186 | /* size: b/h/w. */ | |
187 | #define CSKY_32_STR_SIZE(insn) (1 << ((insn & 0x0c00) >> 10)) | |
188 | /* imm (for rx + ry * imm). */ | |
189 | #define CSKY_32_STR_OFFSET(insn) ((insn & 0x000003e0) >> 5) | |
190 | ||
191 | /* stex32.w rz, (rx, disp). */ | |
192 | #define CSKY_32_IS_STEX(insn) ((insn & 0xfc00f000) == 0xdc007000) | |
193 | /* rx. */ | |
194 | #define CSKY_32_STEX_ADDR_REGNUM(insn) ((insn & 0x1f0000) >> 16) | |
195 | /* disp. */ | |
196 | #define CSKY_32_STEX_OFFSET(insn) ((insn & 0x0fff) << 2) | |
197 | ||
198 | /* ld.b/h/w. */ | |
199 | #define CSKY_32_IS_LD(insn) ((insn & 0xfc00c000) == 0xd8000000) | |
200 | /* size. */ | |
201 | #define CSKY_32_LD_SIZE(insn) CSKY_32_ST_SIZE (insn) | |
202 | /* rx. */ | |
203 | #define CSKY_32_LD_ADDR_REGNUM(insn) CSKY_32_ST_ADDR_REGNUM (insn) | |
204 | /* disp. */ | |
205 | #define CSKY_32_LD_OFFSET(insn) CSKY_32_ST_OFFSET (insn) | |
206 | #define CSKY_32_IS_LDM(insn) ((insn & 0xfc00ffe0) == 0xd0001c20) | |
207 | /* rx. */ | |
208 | #define CSKY_32_LDM_ADDR_REGNUM(insn) CSKY_32_STM_ADDR_REGNUM (insn) | |
209 | /* Count of registers. */ | |
210 | #define CSKY_32_LDM_SIZE(insn) CSKY_32_STM_SIZE (insn) | |
211 | ||
212 | /* ldr32.b/h/w rz, (rx, ry << offset). */ | |
213 | #define CSKY_32_IS_LDR(insn) \ | |
214 | (((insn & 0xfc00fe00) == 0xd0000000) && !(CSKY_32_IS_LDM (insn))) | |
215 | /* rx. */ | |
216 | #define CSKY_32_LDR_X_REGNUM(insn) CSKY_32_STR_X_REGNUM (insn) | |
217 | /* ry. */ | |
218 | #define CSKY_32_LDR_Y_REGNUM(insn) CSKY_32_STR_Y_REGNUM (insn) | |
219 | /* size: b/h/w. */ | |
220 | #define CSKY_32_LDR_SIZE(insn) CSKY_32_STR_SIZE (insn) | |
221 | /* imm (for rx + ry*imm). */ | |
222 | #define CSKY_32_LDR_OFFSET(insn) CSKY_32_STR_OFFSET (insn) | |
223 | ||
224 | #define CSKY_32_IS_LDEX(insn) ((insn & 0xfc00f000) == 0xd8007000) | |
225 | /* rx. */ | |
226 | #define CSKY_32_LDEX_ADDR_REGNUM(insn) CSKY_32_STEX_ADDR_REGNUM (insn) | |
227 | /* disp. */ | |
228 | #define CSKY_32_LDEX_OFFSET(insn) CSKY_32_STEX_OFFSET (insn) | |
229 | ||
230 | /* subi.sp sp, disp. */ | |
231 | #define CSKY_16_IS_SUBI0(insn) ((insn & 0xfce0) == 0x1420) | |
232 | /* disp. */ | |
233 | #define CSKY_16_SUBI_IMM(insn) ((((insn & 0x300) >> 3) + (insn & 0x1f)) << 2) | |
234 | ||
235 | /* subi32 sp,sp,oimm12. */ | |
236 | #define CSKY_32_IS_SUBI0(insn) ((insn & 0xfffff000) == 0xe5ce1000) | |
237 | /* oimm12. */ | |
238 | #define CSKY_32_SUBI_IMM(insn) ((insn & 0xfff) + 1) | |
239 | ||
240 | /* push16. */ | |
241 | #define CSKY_16_IS_PUSH(insn) ((insn & 0xffe0) == 0x14c0) | |
242 | #define CSKY_16_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10) | |
243 | #define CSKY_16_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */ | |
244 | ||
245 | /* pop16. */ | |
246 | #define CSKY_16_IS_POP(insn) ((insn & 0xffe0) == 0x1480) | |
247 | #define CSKY_16_IS_POP_R15(insn) CSKY_16_IS_PUSH_R15 (insn) | |
248 | #define CSKY_16_POP_LIST1(insn) CSKY_16_PUSH_LIST1 (insn) /* r4 - r11. */ | |
249 | ||
250 | /* push32. */ | |
251 | #define CSKY_32_IS_PUSH(insn) ((insn & 0xfffffe00) == 0xebe00000) | |
252 | #define CSKY_32_IS_PUSH_R29(insn) ((insn & 0x100) == 0x100) | |
253 | #define CSKY_32_IS_PUSH_R15(insn) ((insn & 0x10) == 0x10) | |
254 | #define CSKY_32_PUSH_LIST1(insn) (insn & 0xf) /* r4 - r11. */ | |
255 | #define CSKY_32_PUSH_LIST2(insn) ((insn & 0xe0) >> 5) /* r16 - r17. */ | |
256 | ||
257 | /* pop32. */ | |
258 | #define CSKY_32_IS_POP(insn) ((insn & 0xfffffe00) == 0xebc00000) | |
259 | #define CSKY_32_IS_POP_R29(insn) CSKY_32_IS_PUSH_R29 (insn) | |
260 | #define CSKY_32_IS_POP_R15(insn) CSKY_32_IS_PUSH_R15 (insn) | |
261 | #define CSKY_32_POP_LIST1(insn) CSKY_32_PUSH_LIST1 (insn) /* r4 - r11. */ | |
262 | #define CSKY_32_POP_LIST2(insn) CSKY_32_PUSH_LIST2 (insn) /* r16 - r17. */ | |
263 | ||
264 | /* Adjust sp by r4(l0). */ | |
265 | /* lrw r4, literal. */ | |
266 | #define CSKY_16_IS_LRW4(x) (((x) &0xfce0) == 0x1080) | |
267 | /* movi r4, imm8. */ | |
268 | #define CSKY_16_IS_MOVI4(x) (((x) &0xff00) == 0x3400) | |
269 | ||
270 | /* addi r4, oimm8. */ | |
271 | #define CSKY_16_IS_ADDI4(x) (((x) &0xff00) == 0x2400) | |
272 | /* subi r4, oimm8. */ | |
273 | #define CSKY_16_IS_SUBI4(x) (((x) &0xff00) == 0x2c00) | |
274 | ||
275 | /* nor16 r4, r4. */ | |
276 | #define CSKY_16_IS_NOR4(x) ((x) == 0x6d12) | |
277 | ||
278 | /* lsli r4, r4, imm5. */ | |
279 | #define CSKY_16_IS_LSLI4(x) (((x) &0xffe0) == 0x4480) | |
280 | /* bseti r4, imm5. */ | |
281 | #define CSKY_16_IS_BSETI4(x) (((x) &0xffe0) == 0x3ca0) | |
282 | /* bclri r4, imm5. */ | |
283 | #define CSKY_16_IS_BCLRI4(x) (((x) &0xffe0) == 0x3c80) | |
284 | ||
285 | /* subu sp, r4. */ | |
286 | #define CSKY_16_IS_SUBU4(x) ((x) == 0x6392) | |
287 | ||
288 | #define CSKY_16_IS_R4_ADJUSTER(x) \ | |
289 | (CSKY_16_IS_ADDI4 (x) || CSKY_16_IS_SUBI4 (x) || CSKY_16_IS_BSETI4 (x) \ | |
290 | || CSKY_16_IS_BCLRI4 (x) || CSKY_16_IS_NOR4 (x) || CSKY_16_IS_LSLI4 (x)) | |
291 | ||
292 | /* lrw r4, literal. */ | |
293 | #define CSKY_32_IS_LRW4(x) (((x) &0xffff0000) == 0xea840000) | |
294 | /* movi r4, imm16. */ | |
295 | #define CSKY_32_IS_MOVI4(x) (((x) &0xffff0000) == 0xea040000) | |
296 | /* movih r4, imm16. */ | |
297 | #define CSKY_32_IS_MOVIH4(x) (((x) &0xffff0000) == 0xea240000) | |
298 | /* bmaski r4, oimm5. */ | |
299 | #define CSKY_32_IS_BMASKI4(x) (((x) &0xfc1fffff) == 0xc4005024) | |
300 | /* addi r4, r4, oimm12. */ | |
301 | #define CSKY_32_IS_ADDI4(x) (((x) &0xfffff000) == 0xe4840000) | |
302 | /* subi r4, r4, oimm12. */ | |
303 | #define CSKY_32_IS_SUBI4(x) (((x) &0xfffff000) == 0xe4810000) | |
304 | ||
305 | /* nor32 r4, r4, r4. */ | |
306 | #define CSKY_32_IS_NOR4(x) ((x) == 0xc4842484) | |
307 | /* rotli r4, r4, imm5. */ | |
308 | #define CSKY_32_IS_ROTLI4(x) (((x) &0xfc1fffff) == 0xc4044904) | |
309 | /* lsli r4, r4, imm5. */ | |
310 | #define CSKY_32_IS_LISI4(x) (((x) &0xfc1fffff) == 0xc4044824) | |
311 | /* bseti32 r4, r4, imm5. */ | |
312 | #define CSKY_32_IS_BSETI4(x) (((x) &0xfc1fffff) == 0xc4042844) | |
313 | /* bclri32 r4, r4, imm5. */ | |
314 | #define CSKY_32_IS_BCLRI4(x) (((x) &0xfc1fffff) == 0xc4042824) | |
315 | /* ixh r4, r4, r4. */ | |
316 | #define CSKY_32_IS_IXH4(x) ((x) == 0xc4840824) | |
317 | /* ixw r4, r4, r4. */ | |
318 | #define CSKY_32_IS_IXW4(x) ((x) == 0xc4840844) | |
319 | /* subu32 sp, sp, r4. */ | |
320 | #define CSKY_32_IS_SUBU4(x) ((x) == 0xc48e008e) | |
321 | ||
322 | #define CSKY_32_IS_R4_ADJUSTER(x) \ | |
323 | (CSKY_32_IS_ADDI4 (x) || CSKY_32_IS_SUBI4 (x) || CSKY_32_IS_ROTLI4 (x) \ | |
324 | || CSKY_32_IS_IXH4 (x) || CSKY_32_IS_IXW4 (x) || CSKY_32_IS_NOR4 (x) \ | |
325 | || CSKY_32_IS_BSETI4 (x) || CSKY_32_IS_BCLRI4 (x) || CSKY_32_IS_LISI4 (x)) | |
326 | ||
327 | #define CSKY_IS_R4_ADJUSTER(x) \ | |
328 | (CSKY_32_IS_R4_ADJUSTER (x) || CSKY_16_IS_R4_ADJUSTER (x)) | |
329 | #define CSKY_IS_SUBU4(x) (CSKY_32_IS_SUBU4 (x) || CSKY_16_IS_SUBU4 (x)) | |
330 | ||
331 | /* mfcr rz, epsr. */ | |
332 | #define CSKY_32_IS_MFCR_EPSR(insn) ((insn & 0xffffffe0) == 0xc0026020) | |
333 | /* mfcr rz, fpsr. */ | |
334 | #define CSKY_32_IS_MFCR_FPSR(insn) ((insn & 0xffffffe0) == 0xc0036020) | |
335 | /* mfcr rz, epc. */ | |
336 | #define CSKY_32_IS_MFCR_EPC(insn) ((insn & 0xffffffe0) == 0xc0046020) | |
337 | /* mfcr rz, fpc. */ | |
338 | #define CSKY_32_IS_MFCR_FPC(insn) ((insn & 0xffffffe0) == 0xc0056020) | |
339 | ||
340 | #define CSKY_32_IS_RTE(insn) (insn == 0xc0004020) | |
341 | #define CSKY_32_IS_RFI(insn) (insn == 0xc0004420) | |
342 | #define CSKY_32_IS_JMP(insn) ((insn & 0xffe0ffff) == 0xe8c00000) | |
343 | #define CSKY_16_IS_JMP(insn) ((insn & 0xffc3) == 0x7800) | |
344 | #define CSKY_32_IS_JMPI(insn) ((insn & 0xffff0000) == 0xeac00000) | |
345 | #define CSKY_32_IS_JMPIX(insn) ((insn & 0xffe0fffc) == 0xe9e00000) | |
346 | #define CSKY_16_IS_JMPIX(insn) ((insn & 0xf8fc) == 0x38e0) | |
347 | ||
348 | #define CSKY_16_IS_BR(insn) ((insn & 0xfc00) == 0x0400) | |
349 | #define CSKY_32_IS_BR(insn) ((insn & 0xffff0000) == 0xe8000000) | |
350 | #define CSKY_16_IS_MOV_FP_SP(insn) (insn == 0x6e3b) /* mov r8, r14. */ | |
351 | #define CSKY_32_IS_MOV_FP_SP(insn) (insn == 0xc40e4828) /* mov r8, r14. */ | |
352 | #define CSKY_16_IS_MOV_SP_FP(insn) (insn == 0x6fa3) /* mov r14, r8. */ | |
353 | #define CSKY_32_INSN_MASK 0xc000 | |
354 | #define CSKY_BKPT_INSN 0x0 | |
355 | #define CSKY_NUM_GREGS 32 | |
356 | /* 32 general regs + 4. */ | |
357 | #define CSKY_NUM_GREGS_SAVED_GREGS (CSKY_NUM_GREGS + 4) | |
358 | ||
359 | /* CSKY software bkpt write-mode. */ | |
360 | #define CSKY_WR_BKPT_MODE 4 | |
361 | ||
362 | /* Define insns for parse rt_sigframe. */ | |
363 | /* There are three words(sig, pinfo, puc) before siginfo. */ | |
364 | #define CSKY_SIGINFO_OFFSET 0xc | |
365 | ||
366 | /* Size of struct siginfo. */ | |
367 | #define CSKY_SIGINFO_SIZE 0x80 | |
368 | ||
369 | /* There are five words(uc_flags, uc_link, and three for uc_stack) | |
370 | in struct ucontext before sigcontext. */ | |
371 | #define CSKY_UCONTEXT_SIGCONTEXT 0x14 | |
372 | ||
373 | /* There is a word(sc_mask) before sc_usp. */ | |
374 | #define CSKY_SIGCONTEXT_SC_USP 0x4 | |
375 | ||
376 | /* There is a word(sc_usp) before sc_a0. */ | |
377 | #define CSKY_SIGCONTEXT_SC_A0 0x4 | |
378 | ||
379 | #define CSKY_MOVI_R7_173 0x00adea07 | |
380 | #define CSKY_TRAP_0 0x2020c000 | |
381 | ||
105afa7f JL |
382 | /* Sizeof (tls) */ |
383 | #define CSKY_SIGCONTEXT_PT_REGS_TLS 4 | |
384 | ||
385 | /* Macro for kernel 4.x */ | |
386 | #define CSKY_MOVI_R7_139 0x008bea07 | |
387 | ||
d354e0c8 JL |
388 | /* Macro for check long branch. */ |
389 | #define CSKY_JMPI_PC_4 0x1eac0 | |
390 | #define CSKY_LRW_T1_PC_8 0x2ea8d | |
391 | #define CSKY_JMP_T1_VS_NOP 0x6c037834 | |
392 | ||
9d24df82 | 393 | #endif |