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0a30fbc4 | 1 | /* GNU/Linux/MIPS specific low level interface, for the remote server for GDB. |
61baf725 | 2 | Copyright (C) 1995-2017 Free Software Foundation, Inc. |
0a30fbc4 DJ |
3 | |
4 | This file is part of GDB. | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 8 | the Free Software Foundation; either version 3 of the License, or |
0a30fbc4 DJ |
9 | (at your option) any later version. |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
a9762ec7 | 17 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
0a30fbc4 DJ |
18 | |
19 | #include "server.h" | |
58caa3dc | 20 | #include "linux-low.h" |
0a30fbc4 | 21 | |
5826e159 | 22 | #include "nat/gdb_ptrace.h" |
186947f7 | 23 | #include <endian.h> |
21b0f40c | 24 | |
125f8a3d | 25 | #include "nat/mips-linux-watch.h" |
21b0f40c DJ |
26 | #include "gdb_proc_service.h" |
27 | ||
d05b4ac3 UW |
28 | /* Defined in auto-generated file mips-linux.c. */ |
29 | void init_registers_mips_linux (void); | |
3aee8918 PA |
30 | extern const struct target_desc *tdesc_mips_linux; |
31 | ||
1faeff08 MR |
32 | /* Defined in auto-generated file mips-dsp-linux.c. */ |
33 | void init_registers_mips_dsp_linux (void); | |
3aee8918 PA |
34 | extern const struct target_desc *tdesc_mips_dsp_linux; |
35 | ||
d05b4ac3 UW |
36 | /* Defined in auto-generated file mips64-linux.c. */ |
37 | void init_registers_mips64_linux (void); | |
3aee8918 PA |
38 | extern const struct target_desc *tdesc_mips64_linux; |
39 | ||
1faeff08 MR |
40 | /* Defined in auto-generated file mips64-dsp-linux.c. */ |
41 | void init_registers_mips64_dsp_linux (void); | |
3aee8918 | 42 | extern const struct target_desc *tdesc_mips64_dsp_linux; |
1faeff08 MR |
43 | |
44 | #ifdef __mips64 | |
3aee8918 PA |
45 | #define tdesc_mips_linux tdesc_mips64_linux |
46 | #define tdesc_mips_dsp_linux tdesc_mips64_dsp_linux | |
1faeff08 | 47 | #endif |
d05b4ac3 | 48 | |
21b0f40c DJ |
49 | #ifndef PTRACE_GET_THREAD_AREA |
50 | #define PTRACE_GET_THREAD_AREA 25 | |
51 | #endif | |
52 | ||
0a30fbc4 DJ |
53 | #ifdef HAVE_SYS_REG_H |
54 | #include <sys/reg.h> | |
55 | #endif | |
56 | ||
117ce543 | 57 | #define mips_num_regs 73 |
1faeff08 | 58 | #define mips_dsp_num_regs 80 |
0a30fbc4 DJ |
59 | |
60 | #include <asm/ptrace.h> | |
61 | ||
1faeff08 MR |
62 | #ifndef DSP_BASE |
63 | #define DSP_BASE 71 | |
64 | #define DSP_CONTROL 77 | |
65 | #endif | |
66 | ||
186947f7 DJ |
67 | union mips_register |
68 | { | |
69 | unsigned char buf[8]; | |
70 | ||
71 | /* Deliberately signed, for proper sign extension. */ | |
72 | int reg32; | |
73 | long long reg64; | |
74 | }; | |
75 | ||
0a30fbc4 DJ |
76 | /* Return the ptrace ``address'' of register REGNO. */ |
77 | ||
1faeff08 MR |
78 | #define mips_base_regs \ |
79 | -1, 1, 2, 3, 4, 5, 6, 7, \ | |
80 | 8, 9, 10, 11, 12, 13, 14, 15, \ | |
81 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
82 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
83 | \ | |
84 | -1, MMLO, MMHI, BADVADDR, CAUSE, PC, \ | |
85 | \ | |
86 | FPR_BASE, FPR_BASE + 1, FPR_BASE + 2, FPR_BASE + 3, \ | |
87 | FPR_BASE + 4, FPR_BASE + 5, FPR_BASE + 6, FPR_BASE + 7, \ | |
88 | FPR_BASE + 8, FPR_BASE + 9, FPR_BASE + 10, FPR_BASE + 11, \ | |
89 | FPR_BASE + 12, FPR_BASE + 13, FPR_BASE + 14, FPR_BASE + 15, \ | |
90 | FPR_BASE + 16, FPR_BASE + 17, FPR_BASE + 18, FPR_BASE + 19, \ | |
91 | FPR_BASE + 20, FPR_BASE + 21, FPR_BASE + 22, FPR_BASE + 23, \ | |
92 | FPR_BASE + 24, FPR_BASE + 25, FPR_BASE + 26, FPR_BASE + 27, \ | |
93 | FPR_BASE + 28, FPR_BASE + 29, FPR_BASE + 30, FPR_BASE + 31, \ | |
94 | FPC_CSR, FPC_EIR | |
95 | ||
96 | #define mips_dsp_regs \ | |
97 | DSP_BASE, DSP_BASE + 1, DSP_BASE + 2, DSP_BASE + 3, \ | |
98 | DSP_BASE + 4, DSP_BASE + 5, \ | |
99 | DSP_CONTROL | |
100 | ||
101 | static int mips_regmap[mips_num_regs] = { | |
102 | mips_base_regs, | |
103 | 0 | |
104 | }; | |
0a30fbc4 | 105 | |
1faeff08 MR |
106 | static int mips_dsp_regmap[mips_dsp_num_regs] = { |
107 | mips_base_regs, | |
108 | mips_dsp_regs, | |
109 | 0 | |
110 | }; | |
0a30fbc4 | 111 | |
1faeff08 MR |
112 | /* DSP registers are not in any regset and can only be accessed |
113 | individually. */ | |
0a30fbc4 | 114 | |
1faeff08 MR |
115 | static unsigned char mips_dsp_regset_bitmap[(mips_dsp_num_regs + 7) / 8] = { |
116 | 0xfe, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0x80 | |
0a30fbc4 DJ |
117 | }; |
118 | ||
3aee8918 PA |
119 | static int have_dsp = -1; |
120 | ||
1faeff08 MR |
121 | /* Try peeking at an arbitrarily chosen DSP register and pick the available |
122 | user register set accordingly. */ | |
123 | ||
3aee8918 PA |
124 | static const struct target_desc * |
125 | mips_read_description (void) | |
1faeff08 | 126 | { |
3aee8918 | 127 | if (have_dsp < 0) |
1faeff08 | 128 | { |
0bfdf32f | 129 | int pid = lwpid_of (current_thread); |
1faeff08 | 130 | |
ac740bc7 | 131 | errno = 0; |
1faeff08 MR |
132 | ptrace (PTRACE_PEEKUSER, pid, DSP_CONTROL, 0); |
133 | switch (errno) | |
134 | { | |
135 | case 0: | |
3aee8918 | 136 | have_dsp = 1; |
1faeff08 MR |
137 | break; |
138 | case EIO: | |
3aee8918 | 139 | have_dsp = 0; |
1faeff08 MR |
140 | break; |
141 | default: | |
142 | perror_with_name ("ptrace"); | |
143 | break; | |
144 | } | |
145 | } | |
3aee8918 PA |
146 | |
147 | return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux; | |
148 | } | |
149 | ||
150 | static void | |
151 | mips_arch_setup (void) | |
152 | { | |
153 | current_process ()->tdesc = mips_read_description (); | |
154 | } | |
155 | ||
156 | static struct usrregs_info * | |
157 | get_usrregs_info (void) | |
158 | { | |
159 | const struct regs_info *regs_info = the_low_target.regs_info (); | |
160 | ||
161 | return regs_info->usrregs; | |
1faeff08 MR |
162 | } |
163 | ||
7a60ad40 YQ |
164 | /* Per-process arch-specific data we want to keep. */ |
165 | ||
166 | struct arch_process_info | |
167 | { | |
168 | /* -1 if the kernel and/or CPU do not support watch registers. | |
169 | 1 if watch_readback is valid and we can read style, num_valid | |
170 | and the masks. | |
171 | 0 if we need to read the watch_readback. */ | |
172 | ||
173 | int watch_readback_valid; | |
174 | ||
175 | /* Cached watch register read values. */ | |
176 | ||
177 | struct pt_watch_regs watch_readback; | |
178 | ||
179 | /* Current watchpoint requests for this process. */ | |
180 | ||
181 | struct mips_watchpoint *current_watches; | |
182 | ||
183 | /* The current set of watch register values for writing the | |
184 | registers. */ | |
185 | ||
186 | struct pt_watch_regs watch_mirror; | |
187 | }; | |
188 | ||
189 | /* Per-thread arch-specific data we want to keep. */ | |
190 | ||
191 | struct arch_lwp_info | |
192 | { | |
193 | /* Non-zero if our copy differs from what's recorded in the thread. */ | |
194 | int watch_registers_changed; | |
195 | }; | |
196 | ||
0a30fbc4 DJ |
197 | /* From mips-linux-nat.c. */ |
198 | ||
199 | /* Pseudo registers can not be read. ptrace does not provide a way to | |
200 | read (or set) PS_REGNUM, and there's no point in reading or setting | |
201 | ZERO_REGNUM. We also can not set BADVADDR, CAUSE, or FCRIR via | |
202 | ptrace(). */ | |
203 | ||
2ec06d2e DJ |
204 | static int |
205 | mips_cannot_fetch_register (int regno) | |
0a30fbc4 | 206 | { |
3aee8918 PA |
207 | const struct target_desc *tdesc; |
208 | ||
209 | if (get_usrregs_info ()->regmap[regno] == -1) | |
0a30fbc4 DJ |
210 | return 1; |
211 | ||
3aee8918 PA |
212 | tdesc = current_process ()->tdesc; |
213 | ||
214 | if (find_regno (tdesc, "r0") == regno) | |
0a30fbc4 DJ |
215 | return 1; |
216 | ||
217 | return 0; | |
218 | } | |
219 | ||
2ec06d2e DJ |
220 | static int |
221 | mips_cannot_store_register (int regno) | |
0a30fbc4 | 222 | { |
3aee8918 PA |
223 | const struct target_desc *tdesc; |
224 | ||
225 | if (get_usrregs_info ()->regmap[regno] == -1) | |
0a30fbc4 DJ |
226 | return 1; |
227 | ||
3aee8918 PA |
228 | tdesc = current_process ()->tdesc; |
229 | ||
230 | if (find_regno (tdesc, "r0") == regno) | |
0a30fbc4 DJ |
231 | return 1; |
232 | ||
3aee8918 | 233 | if (find_regno (tdesc, "cause") == regno) |
0a30fbc4 DJ |
234 | return 1; |
235 | ||
3aee8918 | 236 | if (find_regno (tdesc, "badvaddr") == regno) |
0a30fbc4 DJ |
237 | return 1; |
238 | ||
3aee8918 | 239 | if (find_regno (tdesc, "fir") == regno) |
0a30fbc4 DJ |
240 | return 1; |
241 | ||
242 | return 0; | |
243 | } | |
2ec06d2e | 244 | |
0d62e5e8 | 245 | static CORE_ADDR |
442ea881 | 246 | mips_get_pc (struct regcache *regcache) |
0d62e5e8 | 247 | { |
186947f7 | 248 | union mips_register pc; |
442ea881 | 249 | collect_register_by_name (regcache, "pc", pc.buf); |
3aee8918 | 250 | return register_size (regcache->tdesc, 0) == 4 ? pc.reg32 : pc.reg64; |
0d62e5e8 DJ |
251 | } |
252 | ||
253 | static void | |
442ea881 | 254 | mips_set_pc (struct regcache *regcache, CORE_ADDR pc) |
0d62e5e8 | 255 | { |
186947f7 | 256 | union mips_register newpc; |
3aee8918 | 257 | if (register_size (regcache->tdesc, 0) == 4) |
186947f7 DJ |
258 | newpc.reg32 = pc; |
259 | else | |
260 | newpc.reg64 = pc; | |
261 | ||
442ea881 | 262 | supply_register_by_name (regcache, "pc", newpc.buf); |
0d62e5e8 DJ |
263 | } |
264 | ||
265 | /* Correct in either endianness. */ | |
186947f7 | 266 | static const unsigned int mips_breakpoint = 0x0005000d; |
0d62e5e8 DJ |
267 | #define mips_breakpoint_len 4 |
268 | ||
dd373349 AT |
269 | /* Implementation of linux_target_ops method "sw_breakpoint_from_kind". */ |
270 | ||
271 | static const gdb_byte * | |
272 | mips_sw_breakpoint_from_kind (int kind, int *size) | |
273 | { | |
274 | *size = mips_breakpoint_len; | |
275 | return (const gdb_byte *) &mips_breakpoint; | |
276 | } | |
277 | ||
0d62e5e8 DJ |
278 | static int |
279 | mips_breakpoint_at (CORE_ADDR where) | |
280 | { | |
186947f7 | 281 | unsigned int insn; |
0d62e5e8 | 282 | |
f450004a | 283 | (*the_target->read_memory) (where, (unsigned char *) &insn, 4); |
0d62e5e8 DJ |
284 | if (insn == mips_breakpoint) |
285 | return 1; | |
286 | ||
287 | /* If necessary, recognize more trap instructions here. GDB only uses the | |
288 | one. */ | |
289 | return 0; | |
290 | } | |
291 | ||
7a60ad40 YQ |
292 | /* Mark the watch registers of lwp, represented by ENTRY, as changed, |
293 | if the lwp's process id is *PID_P. */ | |
294 | ||
295 | static int | |
9c80ecd6 | 296 | update_watch_registers_callback (thread_info *thread, void *pid_p) |
7a60ad40 | 297 | { |
d86d4aaf | 298 | struct lwp_info *lwp = get_thread_lwp (thread); |
7a60ad40 YQ |
299 | int pid = *(int *) pid_p; |
300 | ||
301 | /* Only update the threads of this process. */ | |
d86d4aaf | 302 | if (pid_of (thread) == pid) |
7a60ad40 YQ |
303 | { |
304 | /* The actual update is done later just before resuming the lwp, | |
305 | we just mark that the registers need updating. */ | |
306 | lwp->arch_private->watch_registers_changed = 1; | |
307 | ||
308 | /* If the lwp isn't stopped, force it to momentarily pause, so | |
309 | we can update its watch registers. */ | |
310 | if (!lwp->stopped) | |
311 | linux_stop_lwp (lwp); | |
312 | } | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | /* This is the implementation of linux_target_ops method | |
318 | new_process. */ | |
319 | ||
320 | static struct arch_process_info * | |
321 | mips_linux_new_process (void) | |
322 | { | |
8d749320 | 323 | struct arch_process_info *info = XCNEW (struct arch_process_info); |
7a60ad40 YQ |
324 | |
325 | return info; | |
326 | } | |
327 | ||
04ec7890 SM |
328 | /* This is the implementation of linux_target_ops method |
329 | delete_process. */ | |
330 | ||
331 | static void | |
332 | mips_linux_delete_process (struct arch_process_info *info) | |
333 | { | |
334 | xfree (info); | |
335 | } | |
336 | ||
7a60ad40 YQ |
337 | /* This is the implementation of linux_target_ops method new_thread. |
338 | Mark the watch registers as changed, so the threads' copies will | |
339 | be updated. */ | |
340 | ||
34c703da GB |
341 | static void |
342 | mips_linux_new_thread (struct lwp_info *lwp) | |
7a60ad40 | 343 | { |
8d749320 | 344 | struct arch_lwp_info *info = XCNEW (struct arch_lwp_info); |
7a60ad40 YQ |
345 | |
346 | info->watch_registers_changed = 1; | |
347 | ||
34c703da | 348 | lwp->arch_private = info; |
7a60ad40 YQ |
349 | } |
350 | ||
466eecee SM |
351 | /* Function to call when a thread is being deleted. */ |
352 | ||
353 | static void | |
354 | mips_linux_delete_thread (struct arch_lwp_info *arch_lwp) | |
355 | { | |
356 | xfree (arch_lwp); | |
357 | } | |
358 | ||
3a8a0396 DB |
359 | /* Create a new mips_watchpoint and add it to the list. */ |
360 | ||
361 | static void | |
cbec665b | 362 | mips_add_watchpoint (struct arch_process_info *priv, CORE_ADDR addr, int len, |
eb3e3c67 | 363 | enum target_hw_bp_type watch_type) |
3a8a0396 DB |
364 | { |
365 | struct mips_watchpoint *new_watch; | |
366 | struct mips_watchpoint **pw; | |
367 | ||
8d749320 | 368 | new_watch = XNEW (struct mips_watchpoint); |
3a8a0396 DB |
369 | new_watch->addr = addr; |
370 | new_watch->len = len; | |
371 | new_watch->type = watch_type; | |
372 | new_watch->next = NULL; | |
373 | ||
cbec665b | 374 | pw = &priv->current_watches; |
3a8a0396 DB |
375 | while (*pw != NULL) |
376 | pw = &(*pw)->next; | |
377 | *pw = new_watch; | |
378 | } | |
379 | ||
380 | /* Hook to call when a new fork is attached. */ | |
381 | ||
382 | static void | |
383 | mips_linux_new_fork (struct process_info *parent, | |
384 | struct process_info *child) | |
385 | { | |
386 | struct arch_process_info *parent_private; | |
387 | struct arch_process_info *child_private; | |
388 | struct mips_watchpoint *wp; | |
389 | ||
390 | /* These are allocated by linux_add_process. */ | |
61a7418c DB |
391 | gdb_assert (parent->priv != NULL |
392 | && parent->priv->arch_private != NULL); | |
393 | gdb_assert (child->priv != NULL | |
394 | && child->priv->arch_private != NULL); | |
3a8a0396 DB |
395 | |
396 | /* Linux kernel before 2.6.33 commit | |
397 | 72f674d203cd230426437cdcf7dd6f681dad8b0d | |
398 | will inherit hardware debug registers from parent | |
399 | on fork/vfork/clone. Newer Linux kernels create such tasks with | |
400 | zeroed debug registers. | |
401 | ||
402 | GDB core assumes the child inherits the watchpoints/hw | |
403 | breakpoints of the parent, and will remove them all from the | |
404 | forked off process. Copy the debug registers mirrors into the | |
405 | new process so that all breakpoints and watchpoints can be | |
406 | removed together. The debug registers mirror will become zeroed | |
407 | in the end before detaching the forked off process, thus making | |
408 | this compatible with older Linux kernels too. */ | |
409 | ||
61a7418c DB |
410 | parent_private = parent->priv->arch_private; |
411 | child_private = child->priv->arch_private; | |
3a8a0396 DB |
412 | |
413 | child_private->watch_readback_valid = parent_private->watch_readback_valid; | |
414 | child_private->watch_readback = parent_private->watch_readback; | |
415 | ||
416 | for (wp = parent_private->current_watches; wp != NULL; wp = wp->next) | |
417 | mips_add_watchpoint (child_private, wp->addr, wp->len, wp->type); | |
418 | ||
419 | child_private->watch_mirror = parent_private->watch_mirror; | |
420 | } | |
7a60ad40 YQ |
421 | /* This is the implementation of linux_target_ops method |
422 | prepare_to_resume. If the watch regs have changed, update the | |
423 | thread's copies. */ | |
424 | ||
425 | static void | |
426 | mips_linux_prepare_to_resume (struct lwp_info *lwp) | |
427 | { | |
d86d4aaf | 428 | ptid_t ptid = ptid_of (get_lwp_thread (lwp)); |
7a60ad40 | 429 | struct process_info *proc = find_process_pid (ptid_get_pid (ptid)); |
fe978cb0 | 430 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
431 | |
432 | if (lwp->arch_private->watch_registers_changed) | |
433 | { | |
434 | /* Only update the watch registers if we have set or unset a | |
435 | watchpoint already. */ | |
fe978cb0 | 436 | if (mips_linux_watch_get_num_valid (&priv->watch_mirror) > 0) |
7a60ad40 YQ |
437 | { |
438 | /* Write the mirrored watch register values. */ | |
439 | int tid = ptid_get_lwp (ptid); | |
440 | ||
441 | if (-1 == ptrace (PTRACE_SET_WATCH_REGS, tid, | |
aa58a496 | 442 | &priv->watch_mirror, NULL)) |
7a60ad40 YQ |
443 | perror_with_name ("Couldn't write watch register"); |
444 | } | |
445 | ||
446 | lwp->arch_private->watch_registers_changed = 0; | |
447 | } | |
448 | } | |
449 | ||
802e8e6d PA |
450 | static int |
451 | mips_supports_z_point_type (char z_type) | |
452 | { | |
453 | switch (z_type) | |
454 | { | |
455 | case Z_PACKET_WRITE_WP: | |
456 | case Z_PACKET_READ_WP: | |
457 | case Z_PACKET_ACCESS_WP: | |
458 | return 1; | |
459 | default: | |
460 | return 0; | |
461 | } | |
462 | } | |
463 | ||
7a60ad40 YQ |
464 | /* This is the implementation of linux_target_ops method |
465 | insert_point. */ | |
466 | ||
467 | static int | |
802e8e6d PA |
468 | mips_insert_point (enum raw_bkpt_type type, CORE_ADDR addr, |
469 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
470 | { |
471 | struct process_info *proc = current_process (); | |
fe978cb0 | 472 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 | 473 | struct pt_watch_regs regs; |
7a60ad40 YQ |
474 | int pid; |
475 | long lwpid; | |
476 | enum target_hw_bp_type watch_type; | |
477 | uint32_t irw; | |
478 | ||
0bfdf32f | 479 | lwpid = lwpid_of (current_thread); |
7a60ad40 | 480 | if (!mips_linux_read_watch_registers (lwpid, |
fe978cb0 PA |
481 | &priv->watch_readback, |
482 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
483 | 0)) |
484 | return -1; | |
485 | ||
486 | if (len <= 0) | |
487 | return -1; | |
488 | ||
fe978cb0 | 489 | regs = priv->watch_readback; |
7a60ad40 | 490 | /* Add the current watches. */ |
fe978cb0 | 491 | mips_linux_watch_populate_regs (priv->current_watches, ®s); |
7a60ad40 YQ |
492 | |
493 | /* Now try to add the new watch. */ | |
802e8e6d | 494 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 YQ |
495 | irw = mips_linux_watch_type_to_irw (watch_type); |
496 | if (!mips_linux_watch_try_one_watch (®s, addr, len, irw)) | |
497 | return -1; | |
498 | ||
499 | /* It fit. Stick it on the end of the list. */ | |
3a8a0396 | 500 | mips_add_watchpoint (priv, addr, len, watch_type); |
7a60ad40 | 501 | |
fe978cb0 | 502 | priv->watch_mirror = regs; |
7a60ad40 YQ |
503 | |
504 | /* Only update the threads of this process. */ | |
505 | pid = pid_of (proc); | |
d86d4aaf | 506 | find_inferior (&all_threads, update_watch_registers_callback, &pid); |
7a60ad40 YQ |
507 | |
508 | return 0; | |
509 | } | |
510 | ||
511 | /* This is the implementation of linux_target_ops method | |
512 | remove_point. */ | |
513 | ||
514 | static int | |
802e8e6d PA |
515 | mips_remove_point (enum raw_bkpt_type type, CORE_ADDR addr, |
516 | int len, struct raw_breakpoint *bp) | |
7a60ad40 YQ |
517 | { |
518 | struct process_info *proc = current_process (); | |
fe978cb0 | 519 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
520 | |
521 | int deleted_one; | |
522 | int pid; | |
523 | enum target_hw_bp_type watch_type; | |
524 | ||
525 | struct mips_watchpoint **pw; | |
526 | struct mips_watchpoint *w; | |
527 | ||
7a60ad40 | 528 | /* Search for a known watch that matches. Then unlink and free it. */ |
802e8e6d | 529 | watch_type = raw_bkpt_type_to_target_hw_bp_type (type); |
7a60ad40 | 530 | deleted_one = 0; |
fe978cb0 | 531 | pw = &priv->current_watches; |
7a60ad40 YQ |
532 | while ((w = *pw)) |
533 | { | |
534 | if (w->addr == addr && w->len == len && w->type == watch_type) | |
535 | { | |
536 | *pw = w->next; | |
537 | free (w); | |
538 | deleted_one = 1; | |
539 | break; | |
540 | } | |
541 | pw = &(w->next); | |
542 | } | |
543 | ||
544 | if (!deleted_one) | |
545 | return -1; /* We don't know about it, fail doing nothing. */ | |
546 | ||
547 | /* At this point watch_readback is known to be valid because we | |
548 | could not have added the watch without reading it. */ | |
fe978cb0 | 549 | gdb_assert (priv->watch_readback_valid == 1); |
7a60ad40 | 550 | |
fe978cb0 PA |
551 | priv->watch_mirror = priv->watch_readback; |
552 | mips_linux_watch_populate_regs (priv->current_watches, | |
553 | &priv->watch_mirror); | |
7a60ad40 YQ |
554 | |
555 | /* Only update the threads of this process. */ | |
556 | pid = pid_of (proc); | |
d86d4aaf | 557 | find_inferior (&all_threads, update_watch_registers_callback, &pid); |
7a60ad40 YQ |
558 | return 0; |
559 | } | |
560 | ||
561 | /* This is the implementation of linux_target_ops method | |
562 | stopped_by_watchpoint. The watchhi R and W bits indicate | |
563 | the watch register triggered. */ | |
564 | ||
565 | static int | |
566 | mips_stopped_by_watchpoint (void) | |
567 | { | |
568 | struct process_info *proc = current_process (); | |
fe978cb0 | 569 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
570 | int n; |
571 | int num_valid; | |
0bfdf32f | 572 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
573 | |
574 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
575 | &priv->watch_readback, |
576 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
577 | 1)) |
578 | return 0; | |
579 | ||
fe978cb0 | 580 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
581 | |
582 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 583 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
584 | & (R_MASK | W_MASK)) |
585 | return 1; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | /* This is the implementation of linux_target_ops method | |
591 | stopped_data_address. */ | |
592 | ||
593 | static CORE_ADDR | |
594 | mips_stopped_data_address (void) | |
595 | { | |
596 | struct process_info *proc = current_process (); | |
fe978cb0 | 597 | struct arch_process_info *priv = proc->priv->arch_private; |
7a60ad40 YQ |
598 | int n; |
599 | int num_valid; | |
0bfdf32f | 600 | long lwpid = lwpid_of (current_thread); |
7a60ad40 YQ |
601 | |
602 | /* On MIPS we don't know the low order 3 bits of the data address. | |
603 | GDB does not support remote targets that can't report the | |
604 | watchpoint address. So, make our best guess; return the starting | |
605 | address of a watchpoint request which overlaps the one that | |
606 | triggered. */ | |
607 | ||
608 | if (!mips_linux_read_watch_registers (lwpid, | |
fe978cb0 PA |
609 | &priv->watch_readback, |
610 | &priv->watch_readback_valid, | |
7a60ad40 YQ |
611 | 0)) |
612 | return 0; | |
613 | ||
fe978cb0 | 614 | num_valid = mips_linux_watch_get_num_valid (&priv->watch_readback); |
7a60ad40 YQ |
615 | |
616 | for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++) | |
fe978cb0 | 617 | if (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
618 | & (R_MASK | W_MASK)) |
619 | { | |
620 | CORE_ADDR t_low, t_hi; | |
621 | int t_irw; | |
622 | struct mips_watchpoint *watch; | |
623 | ||
fe978cb0 | 624 | t_low = mips_linux_watch_get_watchlo (&priv->watch_readback, n); |
7a60ad40 | 625 | t_irw = t_low & IRW_MASK; |
fe978cb0 | 626 | t_hi = (mips_linux_watch_get_watchhi (&priv->watch_readback, n) |
7a60ad40 YQ |
627 | | IRW_MASK); |
628 | t_low &= ~(CORE_ADDR)t_hi; | |
629 | ||
fe978cb0 | 630 | for (watch = priv->current_watches; |
7a60ad40 YQ |
631 | watch != NULL; |
632 | watch = watch->next) | |
633 | { | |
634 | CORE_ADDR addr = watch->addr; | |
635 | CORE_ADDR last_byte = addr + watch->len - 1; | |
636 | ||
637 | if ((t_irw & mips_linux_watch_type_to_irw (watch->type)) == 0) | |
638 | { | |
639 | /* Different type. */ | |
640 | continue; | |
641 | } | |
642 | /* Check for overlap of even a single byte. */ | |
643 | if (last_byte >= t_low && addr <= t_low + t_hi) | |
644 | return addr; | |
645 | } | |
646 | } | |
647 | ||
648 | /* Shouldn't happen. */ | |
649 | return 0; | |
650 | } | |
651 | ||
21b0f40c DJ |
652 | /* Fetch the thread-local storage pointer for libthread_db. */ |
653 | ||
654 | ps_err_e | |
754653a7 | 655 | ps_get_thread_area (struct ps_prochandle *ph, |
1b3f6016 | 656 | lwpid_t lwpid, int idx, void **base) |
21b0f40c DJ |
657 | { |
658 | if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0) | |
659 | return PS_ERR; | |
660 | ||
661 | /* IDX is the bias from the thread pointer to the beginning of the | |
662 | thread descriptor. It has to be subtracted due to implementation | |
663 | quirks in libthread_db. */ | |
664 | *base = (void *) ((char *)*base - idx); | |
665 | ||
666 | return PS_OK; | |
667 | } | |
668 | ||
186947f7 DJ |
669 | #ifdef HAVE_PTRACE_GETREGS |
670 | ||
671 | static void | |
442ea881 PA |
672 | mips_collect_register (struct regcache *regcache, |
673 | int use_64bit, int regno, union mips_register *reg) | |
186947f7 DJ |
674 | { |
675 | union mips_register tmp_reg; | |
676 | ||
677 | if (use_64bit) | |
678 | { | |
442ea881 | 679 | collect_register (regcache, regno, &tmp_reg.reg64); |
186947f7 DJ |
680 | *reg = tmp_reg; |
681 | } | |
682 | else | |
683 | { | |
442ea881 | 684 | collect_register (regcache, regno, &tmp_reg.reg32); |
186947f7 DJ |
685 | reg->reg64 = tmp_reg.reg32; |
686 | } | |
687 | } | |
688 | ||
689 | static void | |
442ea881 PA |
690 | mips_supply_register (struct regcache *regcache, |
691 | int use_64bit, int regno, const union mips_register *reg) | |
186947f7 DJ |
692 | { |
693 | int offset = 0; | |
694 | ||
695 | /* For big-endian 32-bit targets, ignore the high four bytes of each | |
696 | eight-byte slot. */ | |
697 | if (__BYTE_ORDER == __BIG_ENDIAN && !use_64bit) | |
698 | offset = 4; | |
699 | ||
442ea881 | 700 | supply_register (regcache, regno, reg->buf + offset); |
186947f7 DJ |
701 | } |
702 | ||
703 | static void | |
442ea881 PA |
704 | mips_collect_register_32bit (struct regcache *regcache, |
705 | int use_64bit, int regno, unsigned char *buf) | |
186947f7 DJ |
706 | { |
707 | union mips_register tmp_reg; | |
708 | int reg32; | |
709 | ||
442ea881 | 710 | mips_collect_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
711 | reg32 = tmp_reg.reg64; |
712 | memcpy (buf, ®32, 4); | |
713 | } | |
714 | ||
715 | static void | |
442ea881 PA |
716 | mips_supply_register_32bit (struct regcache *regcache, |
717 | int use_64bit, int regno, const unsigned char *buf) | |
186947f7 DJ |
718 | { |
719 | union mips_register tmp_reg; | |
720 | int reg32; | |
721 | ||
722 | memcpy (®32, buf, 4); | |
723 | tmp_reg.reg64 = reg32; | |
442ea881 | 724 | mips_supply_register (regcache, use_64bit, regno, &tmp_reg); |
186947f7 DJ |
725 | } |
726 | ||
727 | static void | |
442ea881 | 728 | mips_fill_gregset (struct regcache *regcache, void *buf) |
186947f7 | 729 | { |
1996e237 | 730 | union mips_register *regset = (union mips_register *) buf; |
186947f7 | 731 | int i, use_64bit; |
3aee8918 | 732 | const struct target_desc *tdesc = regcache->tdesc; |
186947f7 | 733 | |
3aee8918 | 734 | use_64bit = (register_size (tdesc, 0) == 8); |
186947f7 | 735 | |
117ce543 | 736 | for (i = 1; i < 32; i++) |
442ea881 PA |
737 | mips_collect_register (regcache, use_64bit, i, regset + i); |
738 | ||
739 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 740 | find_regno (tdesc, "lo"), regset + 32); |
442ea881 | 741 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 742 | find_regno (tdesc, "hi"), regset + 33); |
442ea881 | 743 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 744 | find_regno (tdesc, "pc"), regset + 34); |
442ea881 | 745 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 746 | find_regno (tdesc, "badvaddr"), regset + 35); |
442ea881 | 747 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 748 | find_regno (tdesc, "status"), regset + 36); |
442ea881 | 749 | mips_collect_register (regcache, use_64bit, |
3aee8918 | 750 | find_regno (tdesc, "cause"), regset + 37); |
442ea881 PA |
751 | |
752 | mips_collect_register (regcache, use_64bit, | |
3aee8918 | 753 | find_regno (tdesc, "restart"), regset + 0); |
186947f7 DJ |
754 | } |
755 | ||
756 | static void | |
442ea881 | 757 | mips_store_gregset (struct regcache *regcache, const void *buf) |
186947f7 | 758 | { |
1996e237 | 759 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
760 | int i, use_64bit; |
761 | ||
3aee8918 | 762 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
186947f7 DJ |
763 | |
764 | for (i = 0; i < 32; i++) | |
442ea881 PA |
765 | mips_supply_register (regcache, use_64bit, i, regset + i); |
766 | ||
442ea881 | 767 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
768 | find_regno (regcache->tdesc, "lo"), regset + 32); |
769 | mips_supply_register (regcache, use_64bit, | |
770 | find_regno (regcache->tdesc, "hi"), regset + 33); | |
442ea881 | 771 | mips_supply_register (regcache, use_64bit, |
3aee8918 | 772 | find_regno (regcache->tdesc, "pc"), regset + 34); |
442ea881 | 773 | mips_supply_register (regcache, use_64bit, |
3aee8918 PA |
774 | find_regno (regcache->tdesc, "badvaddr"), regset + 35); |
775 | mips_supply_register (regcache, use_64bit, | |
776 | find_regno (regcache->tdesc, "status"), regset + 36); | |
777 | mips_supply_register (regcache, use_64bit, | |
778 | find_regno (regcache->tdesc, "cause"), regset + 37); | |
442ea881 PA |
779 | |
780 | mips_supply_register (regcache, use_64bit, | |
3aee8918 | 781 | find_regno (regcache->tdesc, "restart"), regset + 0); |
186947f7 DJ |
782 | } |
783 | ||
784 | static void | |
442ea881 | 785 | mips_fill_fpregset (struct regcache *regcache, void *buf) |
186947f7 | 786 | { |
1996e237 | 787 | union mips_register *regset = (union mips_register *) buf; |
186947f7 DJ |
788 | int i, use_64bit, first_fp, big_endian; |
789 | ||
3aee8918 PA |
790 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
791 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
792 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
793 | ||
794 | /* See GDB for a discussion of this peculiar layout. */ | |
795 | for (i = 0; i < 32; i++) | |
796 | if (use_64bit) | |
442ea881 | 797 | collect_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 798 | else |
442ea881 | 799 | collect_register (regcache, first_fp + i, |
186947f7 DJ |
800 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
801 | ||
442ea881 | 802 | mips_collect_register_32bit (regcache, use_64bit, |
3aee8918 PA |
803 | find_regno (regcache->tdesc, "fcsr"), regset[32].buf); |
804 | mips_collect_register_32bit (regcache, use_64bit, | |
805 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
806 | regset[32].buf + 4); |
807 | } | |
808 | ||
809 | static void | |
442ea881 | 810 | mips_store_fpregset (struct regcache *regcache, const void *buf) |
186947f7 | 811 | { |
1996e237 | 812 | const union mips_register *regset = (const union mips_register *) buf; |
186947f7 DJ |
813 | int i, use_64bit, first_fp, big_endian; |
814 | ||
3aee8918 PA |
815 | use_64bit = (register_size (regcache->tdesc, 0) == 8); |
816 | first_fp = find_regno (regcache->tdesc, "f0"); | |
186947f7 DJ |
817 | big_endian = (__BYTE_ORDER == __BIG_ENDIAN); |
818 | ||
819 | /* See GDB for a discussion of this peculiar layout. */ | |
820 | for (i = 0; i < 32; i++) | |
821 | if (use_64bit) | |
442ea881 | 822 | supply_register (regcache, first_fp + i, regset[i].buf); |
186947f7 | 823 | else |
442ea881 | 824 | supply_register (regcache, first_fp + i, |
186947f7 DJ |
825 | regset[i & ~1].buf + 4 * (big_endian != (i & 1))); |
826 | ||
442ea881 | 827 | mips_supply_register_32bit (regcache, use_64bit, |
3aee8918 PA |
828 | find_regno (regcache->tdesc, "fcsr"), |
829 | regset[32].buf); | |
830 | mips_supply_register_32bit (regcache, use_64bit, | |
831 | find_regno (regcache->tdesc, "fir"), | |
186947f7 DJ |
832 | regset[32].buf + 4); |
833 | } | |
834 | #endif /* HAVE_PTRACE_GETREGS */ | |
835 | ||
3aee8918 | 836 | static struct regset_info mips_regsets[] = { |
186947f7 | 837 | #ifdef HAVE_PTRACE_GETREGS |
1570b33e | 838 | { PTRACE_GETREGS, PTRACE_SETREGS, 0, 38 * 8, GENERAL_REGS, |
186947f7 | 839 | mips_fill_gregset, mips_store_gregset }, |
1570b33e | 840 | { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, 33 * 8, FP_REGS, |
186947f7 DJ |
841 | mips_fill_fpregset, mips_store_fpregset }, |
842 | #endif /* HAVE_PTRACE_GETREGS */ | |
50bc912a | 843 | NULL_REGSET |
186947f7 DJ |
844 | }; |
845 | ||
3aee8918 PA |
846 | static struct regsets_info mips_regsets_info = |
847 | { | |
848 | mips_regsets, /* regsets */ | |
849 | 0, /* num_regsets */ | |
850 | NULL, /* disabled_regsets */ | |
851 | }; | |
852 | ||
853 | static struct usrregs_info mips_dsp_usrregs_info = | |
854 | { | |
855 | mips_dsp_num_regs, | |
856 | mips_dsp_regmap, | |
857 | }; | |
858 | ||
859 | static struct usrregs_info mips_usrregs_info = | |
860 | { | |
861 | mips_num_regs, | |
862 | mips_regmap, | |
863 | }; | |
864 | ||
865 | static struct regs_info dsp_regs_info = | |
866 | { | |
867 | mips_dsp_regset_bitmap, | |
868 | &mips_dsp_usrregs_info, | |
869 | &mips_regsets_info | |
870 | }; | |
871 | ||
872 | static struct regs_info regs_info = | |
873 | { | |
874 | NULL, /* regset_bitmap */ | |
875 | &mips_usrregs_info, | |
876 | &mips_regsets_info | |
877 | }; | |
878 | ||
879 | static const struct regs_info * | |
880 | mips_regs_info (void) | |
881 | { | |
882 | if (have_dsp) | |
883 | return &dsp_regs_info; | |
884 | else | |
885 | return ®s_info; | |
886 | } | |
887 | ||
2ec06d2e | 888 | struct linux_target_ops the_low_target = { |
1faeff08 | 889 | mips_arch_setup, |
3aee8918 | 890 | mips_regs_info, |
2ec06d2e DJ |
891 | mips_cannot_fetch_register, |
892 | mips_cannot_store_register, | |
c14dfd32 | 893 | NULL, /* fetch_register */ |
0d62e5e8 DJ |
894 | mips_get_pc, |
895 | mips_set_pc, | |
dd373349 AT |
896 | NULL, /* breakpoint_kind_from_pc */ |
897 | mips_sw_breakpoint_from_kind, | |
fa5308bd | 898 | NULL, /* get_next_pcs */ |
0d62e5e8 DJ |
899 | 0, |
900 | mips_breakpoint_at, | |
802e8e6d | 901 | mips_supports_z_point_type, |
7a60ad40 YQ |
902 | mips_insert_point, |
903 | mips_remove_point, | |
904 | mips_stopped_by_watchpoint, | |
905 | mips_stopped_data_address, | |
906 | NULL, | |
907 | NULL, | |
908 | NULL, /* siginfo_fixup */ | |
909 | mips_linux_new_process, | |
04ec7890 | 910 | mips_linux_delete_process, |
7a60ad40 | 911 | mips_linux_new_thread, |
466eecee | 912 | mips_linux_delete_thread, |
3a8a0396 | 913 | mips_linux_new_fork, |
7a60ad40 | 914 | mips_linux_prepare_to_resume |
2ec06d2e | 915 | }; |
3aee8918 PA |
916 | |
917 | void | |
918 | initialize_low_arch (void) | |
919 | { | |
920 | /* Initialize the Linux target descriptions. */ | |
921 | init_registers_mips_linux (); | |
922 | init_registers_mips_dsp_linux (); | |
923 | init_registers_mips64_linux (); | |
924 | init_registers_mips64_dsp_linux (); | |
925 | ||
926 | initialize_regsets_info (&mips_regsets_info); | |
927 | } |