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a80b95ba | 1 | /* Darwin support for GDB, the GNU debugger. |
1d506c26 | 2 | Copyright (C) 1997-2024 Free Software Foundation, Inc. |
a80b95ba TG |
3 | |
4 | Contributed by Apple Computer, Inc. | |
5 | ||
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
21 | #include "defs.h" | |
22 | #include "frame.h" | |
23 | #include "inferior.h" | |
24 | #include "target.h" | |
25 | #include "symfile.h" | |
26 | #include "symtab.h" | |
27 | #include "objfiles.h" | |
28 | #include "gdbcmd.h" | |
29 | #include "regcache.h" | |
a80b95ba | 30 | #include "i386-tdep.h" |
a80b95ba TG |
31 | #include "i387-tdep.h" |
32 | #include "gdbarch.h" | |
33 | #include "arch-utils.h" | |
acdb24a9 | 34 | #include "gdbcore.h" |
a80b95ba | 35 | |
df7e5265 | 36 | #include "x86-nat.h" |
a80b95ba TG |
37 | #include "darwin-nat.h" |
38 | #include "i386-darwin-tdep.h" | |
39 | ||
5cd226f2 TG |
40 | #ifdef BFD64 |
41 | #include "amd64-nat.h" | |
46187dff | 42 | #include "amd64-tdep.h" |
5cd226f2 TG |
43 | #include "amd64-darwin-tdep.h" |
44 | #endif | |
45 | ||
f6ac5f3d PA |
46 | struct i386_darwin_nat_target final : public x86_nat_target<darwin_nat_target> |
47 | { | |
48 | /* Add our register access methods. */ | |
49 | void fetch_registers (struct regcache *, int) override; | |
50 | void store_registers (struct regcache *, int) override; | |
51 | }; | |
52 | ||
53 | static struct i386_darwin_nat_target darwin_target; | |
54 | ||
a80b95ba TG |
55 | /* Read register values from the inferior process. |
56 | If REGNO is -1, do this for all registers. | |
57 | Otherwise, REGNO specifies which register (so we can save time). */ | |
f6ac5f3d PA |
58 | |
59 | void | |
60 | i386_darwin_nat_target::fetch_registers (struct regcache *regcache, int regno) | |
a80b95ba | 61 | { |
cc6bcb54 | 62 | thread_t current_thread = regcache->ptid ().tid (); |
a80b95ba | 63 | int fetched = 0; |
ac7936df | 64 | struct gdbarch *gdbarch = regcache->arch (); |
a80b95ba | 65 | |
5cd226f2 | 66 | #ifdef BFD64 |
a80b95ba TG |
67 | if (gdbarch_ptr_bit (gdbarch) == 64) |
68 | { | |
69 | if (regno == -1 || amd64_native_gregset_supplies_p (gdbarch, regno)) | |
dda83cd7 SM |
70 | { |
71 | x86_thread_state_t gp_regs; | |
72 | unsigned int gp_count = x86_THREAD_STATE_COUNT; | |
73 | kern_return_t ret; | |
a80b95ba TG |
74 | |
75 | ret = thread_get_state | |
dda83cd7 SM |
76 | (current_thread, x86_THREAD_STATE, (thread_state_t) & gp_regs, |
77 | &gp_count); | |
a80b95ba TG |
78 | if (ret != KERN_SUCCESS) |
79 | { | |
a42a7433 TT |
80 | warning (_("Error calling thread_get_state for " |
81 | "GP registers for thread 0x%lx\n"), | |
82 | (unsigned long) current_thread); | |
a80b95ba TG |
83 | MACH_CHECK_ERROR (ret); |
84 | } | |
89c7137f TG |
85 | |
86 | /* Some kernels don't sanitize the values. */ | |
87 | gp_regs.uts.ts64.__fs &= 0xffff; | |
88 | gp_regs.uts.ts64.__gs &= 0xffff; | |
89 | ||
a80b95ba | 90 | amd64_supply_native_gregset (regcache, &gp_regs.uts, -1); |
dda83cd7 SM |
91 | fetched++; |
92 | } | |
a80b95ba TG |
93 | |
94 | if (regno == -1 || !amd64_native_gregset_supplies_p (gdbarch, regno)) | |
dda83cd7 SM |
95 | { |
96 | x86_float_state_t fp_regs; | |
97 | unsigned int fp_count = x86_FLOAT_STATE_COUNT; | |
98 | kern_return_t ret; | |
a80b95ba TG |
99 | |
100 | ret = thread_get_state | |
dda83cd7 SM |
101 | (current_thread, x86_FLOAT_STATE, (thread_state_t) & fp_regs, |
102 | &fp_count); | |
a80b95ba TG |
103 | if (ret != KERN_SUCCESS) |
104 | { | |
a42a7433 TT |
105 | warning (_("Error calling thread_get_state for " |
106 | "float registers for thread 0x%lx\n"), | |
107 | (unsigned long) current_thread); | |
a80b95ba TG |
108 | MACH_CHECK_ERROR (ret); |
109 | } | |
dda83cd7 SM |
110 | amd64_supply_fxsave (regcache, -1, &fp_regs.ufs.fs64.__fpu_fcw); |
111 | fetched++; | |
112 | } | |
a80b95ba TG |
113 | } |
114 | else | |
5cd226f2 | 115 | #endif |
a80b95ba TG |
116 | { |
117 | if (regno == -1 || regno < I386_NUM_GREGS) | |
dda83cd7 SM |
118 | { |
119 | x86_thread_state32_t gp_regs; | |
120 | unsigned int gp_count = x86_THREAD_STATE32_COUNT; | |
121 | kern_return_t ret; | |
a80b95ba TG |
122 | int i; |
123 | ||
124 | ret = thread_get_state | |
dda83cd7 SM |
125 | (current_thread, x86_THREAD_STATE32, (thread_state_t) &gp_regs, |
126 | &gp_count); | |
a80b95ba TG |
127 | if (ret != KERN_SUCCESS) |
128 | { | |
a42a7433 TT |
129 | warning (_("Error calling thread_get_state for " |
130 | "GP registers for thread 0x%lx\n"), | |
131 | (unsigned long) current_thread); | |
a80b95ba TG |
132 | MACH_CHECK_ERROR (ret); |
133 | } | |
134 | for (i = 0; i < I386_NUM_GREGS; i++) | |
73e1c03f SM |
135 | regcache->raw_supply |
136 | (i, (char *) &gp_regs + i386_darwin_thread_state_reg_offset[i]); | |
a80b95ba | 137 | |
dda83cd7 SM |
138 | fetched++; |
139 | } | |
a80b95ba TG |
140 | |
141 | if (regno == -1 | |
142 | || (regno >= I386_ST0_REGNUM && regno < I386_SSE_NUM_REGS)) | |
dda83cd7 SM |
143 | { |
144 | x86_float_state32_t fp_regs; | |
145 | unsigned int fp_count = x86_FLOAT_STATE32_COUNT; | |
146 | kern_return_t ret; | |
a80b95ba TG |
147 | |
148 | ret = thread_get_state | |
dda83cd7 SM |
149 | (current_thread, x86_FLOAT_STATE32, (thread_state_t) &fp_regs, |
150 | &fp_count); | |
a80b95ba TG |
151 | if (ret != KERN_SUCCESS) |
152 | { | |
a42a7433 TT |
153 | warning (_("Error calling thread_get_state for " |
154 | "float registers for thread 0x%lx\n"), | |
155 | (unsigned long) current_thread); | |
a80b95ba TG |
156 | MACH_CHECK_ERROR (ret); |
157 | } | |
dda83cd7 SM |
158 | i387_supply_fxsave (regcache, -1, &fp_regs.__fpu_fcw); |
159 | fetched++; | |
160 | } | |
a80b95ba TG |
161 | } |
162 | ||
163 | if (! fetched) | |
164 | { | |
165 | warning (_("unknown register %d"), regno); | |
73e1c03f | 166 | regcache->raw_supply (regno, NULL); |
a80b95ba TG |
167 | } |
168 | } | |
169 | ||
170 | /* Store our register values back into the inferior. | |
171 | If REGNO is -1, do this for all registers. | |
172 | Otherwise, REGNO specifies which register (so we can save time). */ | |
173 | ||
f6ac5f3d PA |
174 | void |
175 | i386_darwin_nat_target::store_registers (struct regcache *regcache, | |
176 | int regno) | |
a80b95ba | 177 | { |
cc6bcb54 | 178 | thread_t current_thread = regcache->ptid ().tid (); |
ac7936df | 179 | struct gdbarch *gdbarch = regcache->arch (); |
a80b95ba | 180 | |
5cd226f2 | 181 | #ifdef BFD64 |
a80b95ba TG |
182 | if (gdbarch_ptr_bit (gdbarch) == 64) |
183 | { | |
184 | if (regno == -1 || amd64_native_gregset_supplies_p (gdbarch, regno)) | |
dda83cd7 SM |
185 | { |
186 | x86_thread_state_t gp_regs; | |
187 | kern_return_t ret; | |
a80b95ba TG |
188 | unsigned int gp_count = x86_THREAD_STATE_COUNT; |
189 | ||
190 | ret = thread_get_state | |
191 | (current_thread, x86_THREAD_STATE, (thread_state_t) &gp_regs, | |
192 | &gp_count); | |
dda83cd7 | 193 | MACH_CHECK_ERROR (ret); |
a80b95ba | 194 | gdb_assert (gp_regs.tsh.flavor == x86_THREAD_STATE64); |
dda83cd7 | 195 | gdb_assert (gp_regs.tsh.count == x86_THREAD_STATE64_COUNT); |
a80b95ba TG |
196 | |
197 | amd64_collect_native_gregset (regcache, &gp_regs.uts, regno); | |
198 | ||
89c7137f TG |
199 | /* Some kernels don't sanitize the values. */ |
200 | gp_regs.uts.ts64.__fs &= 0xffff; | |
201 | gp_regs.uts.ts64.__gs &= 0xffff; | |
202 | ||
dda83cd7 SM |
203 | ret = thread_set_state (current_thread, x86_THREAD_STATE, |
204 | (thread_state_t) &gp_regs, | |
205 | x86_THREAD_STATE_COUNT); | |
206 | MACH_CHECK_ERROR (ret); | |
207 | } | |
a80b95ba TG |
208 | |
209 | if (regno == -1 || !amd64_native_gregset_supplies_p (gdbarch, regno)) | |
dda83cd7 SM |
210 | { |
211 | x86_float_state_t fp_regs; | |
212 | kern_return_t ret; | |
a80b95ba TG |
213 | unsigned int fp_count = x86_FLOAT_STATE_COUNT; |
214 | ||
215 | ret = thread_get_state | |
216 | (current_thread, x86_FLOAT_STATE, (thread_state_t) & fp_regs, | |
217 | &fp_count); | |
dda83cd7 SM |
218 | MACH_CHECK_ERROR (ret); |
219 | gdb_assert (fp_regs.fsh.flavor == x86_FLOAT_STATE64); | |
220 | gdb_assert (fp_regs.fsh.count == x86_FLOAT_STATE64_COUNT); | |
a80b95ba | 221 | |
46187dff | 222 | amd64_collect_fxsave (regcache, regno, &fp_regs.ufs.fs64.__fpu_fcw); |
a80b95ba TG |
223 | |
224 | ret = thread_set_state (current_thread, x86_FLOAT_STATE, | |
225 | (thread_state_t) & fp_regs, | |
226 | x86_FLOAT_STATE_COUNT); | |
227 | MACH_CHECK_ERROR (ret); | |
dda83cd7 | 228 | } |
a80b95ba TG |
229 | } |
230 | else | |
5cd226f2 | 231 | #endif |
a80b95ba TG |
232 | { |
233 | if (regno == -1 || regno < I386_NUM_GREGS) | |
dda83cd7 SM |
234 | { |
235 | x86_thread_state32_t gp_regs; | |
236 | kern_return_t ret; | |
237 | unsigned int gp_count = x86_THREAD_STATE32_COUNT; | |
a80b95ba TG |
238 | int i; |
239 | ||
dda83cd7 SM |
240 | ret = thread_get_state |
241 | (current_thread, x86_THREAD_STATE32, (thread_state_t) &gp_regs, | |
242 | &gp_count); | |
a80b95ba TG |
243 | MACH_CHECK_ERROR (ret); |
244 | ||
245 | for (i = 0; i < I386_NUM_GREGS; i++) | |
246 | if (regno == -1 || regno == i) | |
34a79281 SM |
247 | regcache->raw_collect |
248 | (i, (char *) &gp_regs + i386_darwin_thread_state_reg_offset[i]); | |
a80b95ba | 249 | |
dda83cd7 SM |
250 | ret = thread_set_state (current_thread, x86_THREAD_STATE32, |
251 | (thread_state_t) &gp_regs, | |
252 | x86_THREAD_STATE32_COUNT); | |
253 | MACH_CHECK_ERROR (ret); | |
254 | } | |
a80b95ba TG |
255 | |
256 | if (regno == -1 | |
257 | || (regno >= I386_ST0_REGNUM && regno < I386_SSE_NUM_REGS)) | |
dda83cd7 SM |
258 | { |
259 | x86_float_state32_t fp_regs; | |
260 | unsigned int fp_count = x86_FLOAT_STATE32_COUNT; | |
261 | kern_return_t ret; | |
a80b95ba TG |
262 | |
263 | ret = thread_get_state | |
dda83cd7 SM |
264 | (current_thread, x86_FLOAT_STATE32, (thread_state_t) & fp_regs, |
265 | &fp_count); | |
a80b95ba TG |
266 | MACH_CHECK_ERROR (ret); |
267 | ||
268 | i387_collect_fxsave (regcache, regno, &fp_regs.__fpu_fcw); | |
269 | ||
cf9bb588 TG |
270 | ret = thread_set_state (current_thread, x86_FLOAT_STATE32, |
271 | (thread_state_t) &fp_regs, | |
272 | x86_FLOAT_STATE32_COUNT); | |
a80b95ba | 273 | MACH_CHECK_ERROR (ret); |
dda83cd7 | 274 | } |
a80b95ba TG |
275 | } |
276 | } | |
277 | ||
a80b95ba TG |
278 | /* Support for debug registers, boosted mostly from i386-linux-nat.c. */ |
279 | ||
a80b95ba | 280 | static void |
b1328b1b | 281 | i386_darwin_dr_set (int regnum, CORE_ADDR value) |
a80b95ba | 282 | { |
a80b95ba TG |
283 | thread_t current_thread; |
284 | x86_debug_state_t dr_regs; | |
285 | kern_return_t ret; | |
61d82a0d | 286 | unsigned int dr_count; |
a80b95ba TG |
287 | |
288 | gdb_assert (regnum >= 0 && regnum <= DR_CONTROL); | |
289 | ||
cc6bcb54 | 290 | current_thread = inferior_ptid.tid (); |
a80b95ba | 291 | |
61d82a0d TG |
292 | dr_regs.dsh.flavor = x86_DEBUG_STATE; |
293 | dr_regs.dsh.count = x86_DEBUG_STATE_COUNT; | |
a80b95ba | 294 | dr_count = x86_DEBUG_STATE_COUNT; |
61d82a0d | 295 | ret = thread_get_state (current_thread, x86_DEBUG_STATE, |
dda83cd7 | 296 | (thread_state_t) &dr_regs, &dr_count); |
b1328b1b | 297 | MACH_CHECK_ERROR (ret); |
a80b95ba | 298 | |
61d82a0d | 299 | switch (dr_regs.dsh.flavor) |
a80b95ba | 300 | { |
61d82a0d TG |
301 | case x86_DEBUG_STATE32: |
302 | switch (regnum) | |
303 | { | |
304 | case 0: | |
305 | dr_regs.uds.ds32.__dr0 = value; | |
306 | break; | |
307 | case 1: | |
308 | dr_regs.uds.ds32.__dr1 = value; | |
309 | break; | |
310 | case 2: | |
311 | dr_regs.uds.ds32.__dr2 = value; | |
312 | break; | |
313 | case 3: | |
314 | dr_regs.uds.ds32.__dr3 = value; | |
315 | break; | |
316 | case 4: | |
317 | dr_regs.uds.ds32.__dr4 = value; | |
318 | break; | |
319 | case 5: | |
320 | dr_regs.uds.ds32.__dr5 = value; | |
321 | break; | |
322 | case 6: | |
323 | dr_regs.uds.ds32.__dr6 = value; | |
324 | break; | |
325 | case 7: | |
326 | dr_regs.uds.ds32.__dr7 = value; | |
327 | break; | |
328 | } | |
329 | break; | |
330 | #ifdef BFD64 | |
331 | case x86_DEBUG_STATE64: | |
332 | switch (regnum) | |
333 | { | |
334 | case 0: | |
335 | dr_regs.uds.ds64.__dr0 = value; | |
336 | break; | |
337 | case 1: | |
338 | dr_regs.uds.ds64.__dr1 = value; | |
339 | break; | |
340 | case 2: | |
341 | dr_regs.uds.ds64.__dr2 = value; | |
342 | break; | |
343 | case 3: | |
344 | dr_regs.uds.ds64.__dr3 = value; | |
345 | break; | |
346 | case 4: | |
347 | dr_regs.uds.ds64.__dr4 = value; | |
348 | break; | |
349 | case 5: | |
350 | dr_regs.uds.ds64.__dr5 = value; | |
351 | break; | |
352 | case 6: | |
353 | dr_regs.uds.ds64.__dr6 = value; | |
354 | break; | |
355 | case 7: | |
356 | dr_regs.uds.ds64.__dr7 = value; | |
357 | break; | |
358 | } | |
359 | break; | |
360 | #endif | |
a80b95ba TG |
361 | } |
362 | ||
b1328b1b | 363 | ret = thread_set_state (current_thread, dr_regs.dsh.flavor, |
dda83cd7 | 364 | (thread_state_t) &dr_regs.uds, dr_count); |
a80b95ba | 365 | |
b1328b1b | 366 | MACH_CHECK_ERROR (ret); |
a80b95ba TG |
367 | } |
368 | ||
b1328b1b | 369 | static CORE_ADDR |
a80b95ba TG |
370 | i386_darwin_dr_get (int regnum) |
371 | { | |
372 | thread_t current_thread; | |
373 | x86_debug_state_t dr_regs; | |
374 | kern_return_t ret; | |
61d82a0d | 375 | unsigned int dr_count; |
a80b95ba TG |
376 | |
377 | gdb_assert (regnum >= 0 && regnum <= DR_CONTROL); | |
378 | ||
cc6bcb54 | 379 | current_thread = inferior_ptid.tid (); |
a80b95ba | 380 | |
61d82a0d TG |
381 | dr_regs.dsh.flavor = x86_DEBUG_STATE; |
382 | dr_regs.dsh.count = x86_DEBUG_STATE_COUNT; | |
a80b95ba | 383 | dr_count = x86_DEBUG_STATE_COUNT; |
61d82a0d | 384 | ret = thread_get_state (current_thread, x86_DEBUG_STATE, |
dda83cd7 | 385 | (thread_state_t) &dr_regs, &dr_count); |
b1328b1b | 386 | MACH_CHECK_ERROR (ret); |
a80b95ba | 387 | |
61d82a0d | 388 | switch (dr_regs.dsh.flavor) |
a80b95ba | 389 | { |
61d82a0d TG |
390 | case x86_DEBUG_STATE32: |
391 | switch (regnum) | |
392 | { | |
393 | case 0: | |
394 | return dr_regs.uds.ds32.__dr0; | |
395 | case 1: | |
396 | return dr_regs.uds.ds32.__dr1; | |
397 | case 2: | |
398 | return dr_regs.uds.ds32.__dr2; | |
399 | case 3: | |
400 | return dr_regs.uds.ds32.__dr3; | |
401 | case 4: | |
402 | return dr_regs.uds.ds32.__dr4; | |
403 | case 5: | |
404 | return dr_regs.uds.ds32.__dr5; | |
405 | case 6: | |
406 | return dr_regs.uds.ds32.__dr6; | |
407 | case 7: | |
408 | return dr_regs.uds.ds32.__dr7; | |
409 | default: | |
410 | return -1; | |
411 | } | |
412 | break; | |
413 | #ifdef BFD64 | |
414 | case x86_DEBUG_STATE64: | |
415 | switch (regnum) | |
416 | { | |
417 | case 0: | |
418 | return dr_regs.uds.ds64.__dr0; | |
419 | case 1: | |
420 | return dr_regs.uds.ds64.__dr1; | |
421 | case 2: | |
422 | return dr_regs.uds.ds64.__dr2; | |
423 | case 3: | |
424 | return dr_regs.uds.ds64.__dr3; | |
425 | case 4: | |
426 | return dr_regs.uds.ds64.__dr4; | |
427 | case 5: | |
428 | return dr_regs.uds.ds64.__dr5; | |
429 | case 6: | |
430 | return dr_regs.uds.ds64.__dr6; | |
431 | case 7: | |
432 | return dr_regs.uds.ds64.__dr7; | |
433 | default: | |
434 | return -1; | |
435 | } | |
436 | break; | |
437 | #endif | |
438 | default: | |
439 | return -1; | |
a80b95ba TG |
440 | } |
441 | } | |
442 | ||
61d82a0d | 443 | static void |
a80b95ba TG |
444 | i386_darwin_dr_set_control (unsigned long control) |
445 | { | |
446 | i386_darwin_dr_set (DR_CONTROL, control); | |
447 | } | |
448 | ||
61d82a0d | 449 | static void |
a80b95ba TG |
450 | i386_darwin_dr_set_addr (int regnum, CORE_ADDR addr) |
451 | { | |
452 | gdb_assert (regnum >= 0 && regnum <= DR_LASTADDR - DR_FIRSTADDR); | |
453 | ||
454 | i386_darwin_dr_set (DR_FIRSTADDR + regnum, addr); | |
455 | } | |
456 | ||
61d82a0d | 457 | static CORE_ADDR |
7b50312a | 458 | i386_darwin_dr_get_addr (int regnum) |
a80b95ba | 459 | { |
7b50312a | 460 | return i386_darwin_dr_get (regnum); |
a80b95ba TG |
461 | } |
462 | ||
61d82a0d | 463 | static unsigned long |
a80b95ba TG |
464 | i386_darwin_dr_get_status (void) |
465 | { | |
466 | return i386_darwin_dr_get (DR_STATUS); | |
467 | } | |
468 | ||
61d82a0d | 469 | static unsigned long |
7b50312a PA |
470 | i386_darwin_dr_get_control (void) |
471 | { | |
472 | return i386_darwin_dr_get (DR_CONTROL); | |
473 | } | |
474 | ||
a80b95ba TG |
475 | void |
476 | darwin_check_osabi (darwin_inferior *inf, thread_t thread) | |
477 | { | |
99d9c3b9 | 478 | if (gdbarch_osabi (current_inferior ()->arch ()) == GDB_OSABI_UNKNOWN) |
a80b95ba TG |
479 | { |
480 | /* Attaching to a process. Let's figure out what kind it is. */ | |
481 | x86_thread_state_t gp_regs; | |
a80b95ba TG |
482 | unsigned int gp_count = x86_THREAD_STATE_COUNT; |
483 | kern_return_t ret; | |
484 | ||
485 | ret = thread_get_state (thread, x86_THREAD_STATE, | |
486 | (thread_state_t) &gp_regs, &gp_count); | |
487 | if (ret != KERN_SUCCESS) | |
488 | { | |
489 | MACH_CHECK_ERROR (ret); | |
490 | return; | |
491 | } | |
492 | ||
b447dd03 | 493 | gdbarch_info info; |
a80b95ba | 494 | gdbarch_info_fill (&info); |
99d9c3b9 | 495 | info.byte_order = gdbarch_byte_order (current_inferior ()->arch ()); |
a80b95ba TG |
496 | info.osabi = GDB_OSABI_DARWIN; |
497 | if (gp_regs.tsh.flavor == x86_THREAD_STATE64) | |
498 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_i386, | |
499 | bfd_mach_x86_64); | |
500 | else | |
61d82a0d | 501 | info.bfd_arch_info = bfd_lookup_arch (bfd_arch_i386, |
a80b95ba TG |
502 | bfd_mach_i386_i386); |
503 | gdbarch_update_p (info); | |
504 | } | |
505 | } | |
506 | ||
507 | #define X86_EFLAGS_T 0x100UL | |
508 | ||
acdb24a9 TG |
509 | /* Returning from a signal trampoline is done by calling a |
510 | special system call (sigreturn). This system call | |
511 | restores the registers that were saved when the signal was | |
512 | raised, including %eflags/%rflags. That means that single-stepping | |
513 | won't work. Instead, we'll have to modify the signal context | |
514 | that's about to be restored, and set the trace flag there. */ | |
515 | ||
516 | static int | |
517 | i386_darwin_sstep_at_sigreturn (x86_thread_state_t *regs) | |
518 | { | |
99d9c3b9 | 519 | bfd_endian byte_order = gdbarch_byte_order (current_inferior ()->arch ()); |
acdb24a9 TG |
520 | static const gdb_byte darwin_syscall[] = { 0xcd, 0x80 }; /* int 0x80 */ |
521 | gdb_byte buf[sizeof (darwin_syscall)]; | |
522 | ||
523 | /* Check if PC is at a sigreturn system call. */ | |
524 | if (target_read_memory (regs->uts.ts32.__eip, buf, sizeof (buf)) == 0 | |
525 | && memcmp (buf, darwin_syscall, sizeof (darwin_syscall)) == 0 | |
526 | && regs->uts.ts32.__eax == 0xb8 /* SYS_sigreturn */) | |
527 | { | |
528 | ULONGEST uctx_addr; | |
529 | ULONGEST mctx_addr; | |
530 | ULONGEST flags_addr; | |
531 | unsigned int eflags; | |
532 | ||
e17a4113 UW |
533 | uctx_addr = read_memory_unsigned_integer |
534 | (regs->uts.ts32.__esp + 4, 4, byte_order); | |
535 | mctx_addr = read_memory_unsigned_integer | |
536 | (uctx_addr + 28, 4, byte_order); | |
acdb24a9 TG |
537 | |
538 | flags_addr = mctx_addr + 12 + 9 * 4; | |
539 | read_memory (flags_addr, (gdb_byte *) &eflags, 4); | |
540 | eflags |= X86_EFLAGS_T; | |
541 | write_memory (flags_addr, (gdb_byte *) &eflags, 4); | |
542 | ||
543 | return 1; | |
544 | } | |
545 | return 0; | |
546 | } | |
547 | ||
5cd226f2 | 548 | #ifdef BFD64 |
acdb24a9 TG |
549 | static int |
550 | amd64_darwin_sstep_at_sigreturn (x86_thread_state_t *regs) | |
551 | { | |
99d9c3b9 | 552 | bfd_endian byte_order = gdbarch_byte_order (current_inferior ()->arch ()); |
acdb24a9 TG |
553 | static const gdb_byte darwin_syscall[] = { 0x0f, 0x05 }; /* syscall */ |
554 | gdb_byte buf[sizeof (darwin_syscall)]; | |
555 | ||
556 | /* Check if PC is at a sigreturn system call. */ | |
557 | if (target_read_memory (regs->uts.ts64.__rip, buf, sizeof (buf)) == 0 | |
558 | && memcmp (buf, darwin_syscall, sizeof (darwin_syscall)) == 0 | |
559 | && (regs->uts.ts64.__rax & 0xffffffff) == 0x20000b8 /* SYS_sigreturn */) | |
560 | { | |
561 | ULONGEST mctx_addr; | |
562 | ULONGEST flags_addr; | |
563 | unsigned int rflags; | |
564 | ||
e17a4113 UW |
565 | mctx_addr = read_memory_unsigned_integer |
566 | (regs->uts.ts64.__rdi + 48, 8, byte_order); | |
acdb24a9 TG |
567 | flags_addr = mctx_addr + 16 + 17 * 8; |
568 | ||
569 | /* AMD64 is little endian. */ | |
570 | read_memory (flags_addr, (gdb_byte *) &rflags, 4); | |
571 | rflags |= X86_EFLAGS_T; | |
572 | write_memory (flags_addr, (gdb_byte *) &rflags, 4); | |
573 | ||
574 | return 1; | |
575 | } | |
576 | return 0; | |
577 | } | |
5cd226f2 | 578 | #endif |
acdb24a9 | 579 | |
a80b95ba TG |
580 | void |
581 | darwin_set_sstep (thread_t thread, int enable) | |
582 | { | |
583 | x86_thread_state_t regs; | |
584 | unsigned int count = x86_THREAD_STATE_COUNT; | |
585 | kern_return_t kret; | |
586 | ||
587 | kret = thread_get_state (thread, x86_THREAD_STATE, | |
588 | (thread_state_t) ®s, &count); | |
589 | if (kret != KERN_SUCCESS) | |
590 | { | |
a42a7433 TT |
591 | warning (_("darwin_set_sstep: error %x, thread=%x\n"), |
592 | kret, thread); | |
a80b95ba TG |
593 | return; |
594 | } | |
acdb24a9 | 595 | |
a80b95ba TG |
596 | switch (regs.tsh.flavor) |
597 | { | |
598 | case x86_THREAD_STATE32: | |
599 | { | |
600 | __uint32_t bit = enable ? X86_EFLAGS_T : 0; | |
b1328b1b | 601 | |
acdb24a9 TG |
602 | if (enable && i386_darwin_sstep_at_sigreturn (®s)) |
603 | return; | |
a80b95ba TG |
604 | if ((regs.uts.ts32.__eflags & X86_EFLAGS_T) == bit) |
605 | return; | |
1777feb0 MS |
606 | regs.uts.ts32.__eflags |
607 | = (regs.uts.ts32.__eflags & ~X86_EFLAGS_T) | bit; | |
b1328b1b | 608 | kret = thread_set_state (thread, x86_THREAD_STATE, |
a80b95ba TG |
609 | (thread_state_t) ®s, count); |
610 | MACH_CHECK_ERROR (kret); | |
611 | } | |
612 | break; | |
5cd226f2 | 613 | #ifdef BFD64 |
a80b95ba TG |
614 | case x86_THREAD_STATE64: |
615 | { | |
616 | __uint64_t bit = enable ? X86_EFLAGS_T : 0; | |
617 | ||
acdb24a9 TG |
618 | if (enable && amd64_darwin_sstep_at_sigreturn (®s)) |
619 | return; | |
a80b95ba TG |
620 | if ((regs.uts.ts64.__rflags & X86_EFLAGS_T) == bit) |
621 | return; | |
1777feb0 MS |
622 | regs.uts.ts64.__rflags |
623 | = (regs.uts.ts64.__rflags & ~X86_EFLAGS_T) | bit; | |
b1328b1b | 624 | kret = thread_set_state (thread, x86_THREAD_STATE, |
a80b95ba TG |
625 | (thread_state_t) ®s, count); |
626 | MACH_CHECK_ERROR (kret); | |
627 | } | |
628 | break; | |
5cd226f2 | 629 | #endif |
a80b95ba | 630 | default: |
b37520b6 | 631 | error (_("darwin_set_sstep: unknown flavour: %d"), regs.tsh.flavor); |
a80b95ba TG |
632 | } |
633 | } | |
634 | ||
6c265988 | 635 | void _initialize_i386_darwin_nat (); |
a80b95ba | 636 | void |
6c265988 | 637 | _initialize_i386_darwin_nat () |
a80b95ba | 638 | { |
5cd226f2 | 639 | #ifdef BFD64 |
a80b95ba TG |
640 | amd64_native_gregset64_reg_offset = amd64_darwin_thread_state_reg_offset; |
641 | amd64_native_gregset64_num_regs = amd64_darwin_thread_state_num_regs; | |
642 | amd64_native_gregset32_reg_offset = i386_darwin_thread_state_reg_offset; | |
643 | amd64_native_gregset32_num_regs = i386_darwin_thread_state_num_regs; | |
5cd226f2 | 644 | #endif |
a80b95ba | 645 | |
df7e5265 GB |
646 | x86_dr_low.set_control = i386_darwin_dr_set_control; |
647 | x86_dr_low.set_addr = i386_darwin_dr_set_addr; | |
648 | x86_dr_low.get_addr = i386_darwin_dr_get_addr; | |
649 | x86_dr_low.get_status = i386_darwin_dr_get_status; | |
650 | x86_dr_low.get_control = i386_darwin_dr_get_control; | |
61d82a0d TG |
651 | |
652 | /* Let's assume that the kernel is 64 bits iff the executable is. */ | |
653 | #ifdef __x86_64__ | |
df7e5265 | 654 | x86_set_debug_register_length (8); |
61d82a0d | 655 | #else |
df7e5265 | 656 | x86_set_debug_register_length (4); |
61d82a0d TG |
657 | #endif |
658 | ||
d9f719f1 | 659 | add_inf_child_target (&darwin_target); |
a80b95ba | 660 | } |