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c906108c | 1 | /* Intel 386 target-dependent stuff. |
349c5d5f | 2 | |
213516ef | 3 | Copyright (C) 1988-2023 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
1903f0e6 | 21 | #include "opcode/i386.h" |
acd5c798 MK |
22 | #include "arch-utils.h" |
23 | #include "command.h" | |
24 | #include "dummy-frame.h" | |
82ca8957 | 25 | #include "dwarf2/frame.h" |
c906108c | 26 | #include "frame.h" |
acd5c798 MK |
27 | #include "frame-base.h" |
28 | #include "frame-unwind.h" | |
c906108c | 29 | #include "inferior.h" |
45741a9c | 30 | #include "infrun.h" |
acd5c798 | 31 | #include "gdbcmd.h" |
c906108c | 32 | #include "gdbcore.h" |
e6bb342a | 33 | #include "gdbtypes.h" |
dfe01d39 | 34 | #include "objfiles.h" |
acd5c798 MK |
35 | #include "osabi.h" |
36 | #include "regcache.h" | |
37 | #include "reggroups.h" | |
473f17b0 | 38 | #include "regset.h" |
c0d1d883 | 39 | #include "symfile.h" |
c906108c | 40 | #include "symtab.h" |
acd5c798 | 41 | #include "target.h" |
3b2ca824 | 42 | #include "target-float.h" |
fd0407d6 | 43 | #include "value.h" |
a89aa300 | 44 | #include "dis-asm.h" |
7a697b8d | 45 | #include "disasm.h" |
c8d5aac9 | 46 | #include "remote.h" |
d2a7c97a | 47 | #include "i386-tdep.h" |
61113f8b | 48 | #include "i387-tdep.h" |
268a13a5 | 49 | #include "gdbsupport/x86-xstate.h" |
1d509aa6 | 50 | #include "x86-tdep.h" |
4c5e7a93 | 51 | #include "expop.h" |
d2a7c97a | 52 | |
7ad10968 | 53 | #include "record.h" |
d02ed0bb | 54 | #include "record-full.h" |
22916b07 YQ |
55 | #include "target-descriptions.h" |
56 | #include "arch/i386.h" | |
90884b2b | 57 | |
6710bf39 SS |
58 | #include "ax.h" |
59 | #include "ax-gdb.h" | |
60 | ||
55aa24fb SDJ |
61 | #include "stap-probe.h" |
62 | #include "user-regs.h" | |
63 | #include "cli/cli-utils.h" | |
64 | #include "expression.h" | |
65 | #include "parser-defs.h" | |
66 | #include <ctype.h> | |
325fac50 | 67 | #include <algorithm> |
7d7571f0 | 68 | #include <unordered_set> |
c2fd7fae | 69 | #include "producer.h" |
545e49f5 TV |
70 | #include "infcall.h" |
71 | #include "maint.h" | |
55aa24fb | 72 | |
c4fc7f1b | 73 | /* Register names. */ |
c40e1eab | 74 | |
27087b7f | 75 | static const char * const i386_register_names[] = |
fc633446 MK |
76 | { |
77 | "eax", "ecx", "edx", "ebx", | |
78 | "esp", "ebp", "esi", "edi", | |
79 | "eip", "eflags", "cs", "ss", | |
80 | "ds", "es", "fs", "gs", | |
81 | "st0", "st1", "st2", "st3", | |
82 | "st4", "st5", "st6", "st7", | |
83 | "fctrl", "fstat", "ftag", "fiseg", | |
84 | "fioff", "foseg", "fooff", "fop", | |
85 | "xmm0", "xmm1", "xmm2", "xmm3", | |
86 | "xmm4", "xmm5", "xmm6", "xmm7", | |
87 | "mxcsr" | |
88 | }; | |
89 | ||
27087b7f | 90 | static const char * const i386_zmm_names[] = |
01f9f808 MS |
91 | { |
92 | "zmm0", "zmm1", "zmm2", "zmm3", | |
93 | "zmm4", "zmm5", "zmm6", "zmm7" | |
94 | }; | |
95 | ||
27087b7f | 96 | static const char * const i386_zmmh_names[] = |
01f9f808 MS |
97 | { |
98 | "zmm0h", "zmm1h", "zmm2h", "zmm3h", | |
99 | "zmm4h", "zmm5h", "zmm6h", "zmm7h" | |
100 | }; | |
101 | ||
27087b7f | 102 | static const char * const i386_k_names[] = |
01f9f808 MS |
103 | { |
104 | "k0", "k1", "k2", "k3", | |
105 | "k4", "k5", "k6", "k7" | |
106 | }; | |
107 | ||
27087b7f | 108 | static const char * const i386_ymm_names[] = |
c131fcee L |
109 | { |
110 | "ymm0", "ymm1", "ymm2", "ymm3", | |
111 | "ymm4", "ymm5", "ymm6", "ymm7", | |
112 | }; | |
113 | ||
27087b7f | 114 | static const char * const i386_ymmh_names[] = |
c131fcee L |
115 | { |
116 | "ymm0h", "ymm1h", "ymm2h", "ymm3h", | |
117 | "ymm4h", "ymm5h", "ymm6h", "ymm7h", | |
118 | }; | |
119 | ||
27087b7f | 120 | static const char * const i386_mpx_names[] = |
1dbcd68c WT |
121 | { |
122 | "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" | |
123 | }; | |
124 | ||
27087b7f | 125 | static const char * const i386_pkeys_names[] = |
51547df6 MS |
126 | { |
127 | "pkru" | |
128 | }; | |
129 | ||
1dbcd68c WT |
130 | /* Register names for MPX pseudo-registers. */ |
131 | ||
27087b7f | 132 | static const char * const i386_bnd_names[] = |
1dbcd68c WT |
133 | { |
134 | "bnd0", "bnd1", "bnd2", "bnd3" | |
135 | }; | |
136 | ||
c4fc7f1b | 137 | /* Register names for MMX pseudo-registers. */ |
28fc6740 | 138 | |
27087b7f | 139 | static const char * const i386_mmx_names[] = |
28fc6740 AC |
140 | { |
141 | "mm0", "mm1", "mm2", "mm3", | |
142 | "mm4", "mm5", "mm6", "mm7" | |
143 | }; | |
c40e1eab | 144 | |
1ba53b71 L |
145 | /* Register names for byte pseudo-registers. */ |
146 | ||
27087b7f | 147 | static const char * const i386_byte_names[] = |
1ba53b71 L |
148 | { |
149 | "al", "cl", "dl", "bl", | |
150 | "ah", "ch", "dh", "bh" | |
151 | }; | |
152 | ||
153 | /* Register names for word pseudo-registers. */ | |
154 | ||
27087b7f | 155 | static const char * const i386_word_names[] = |
1ba53b71 L |
156 | { |
157 | "ax", "cx", "dx", "bx", | |
9cad29ac | 158 | "", "bp", "si", "di" |
1ba53b71 L |
159 | }; |
160 | ||
01f9f808 MS |
161 | /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have |
162 | 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition, | |
163 | we have 16 upper ZMM regs that have to be handled differently. */ | |
164 | ||
165 | const int num_lower_zmm_regs = 16; | |
166 | ||
1ba53b71 | 167 | /* MMX register? */ |
c40e1eab | 168 | |
28fc6740 | 169 | static int |
5716833c | 170 | i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum) |
28fc6740 | 171 | { |
08106042 | 172 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1ba53b71 | 173 | int mm0_regnum = tdep->mm0_regnum; |
5716833c MK |
174 | |
175 | if (mm0_regnum < 0) | |
176 | return 0; | |
177 | ||
1ba53b71 L |
178 | regnum -= mm0_regnum; |
179 | return regnum >= 0 && regnum < tdep->num_mmx_regs; | |
180 | } | |
181 | ||
182 | /* Byte register? */ | |
183 | ||
184 | int | |
185 | i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum) | |
186 | { | |
08106042 | 187 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1ba53b71 L |
188 | |
189 | regnum -= tdep->al_regnum; | |
190 | return regnum >= 0 && regnum < tdep->num_byte_regs; | |
191 | } | |
192 | ||
193 | /* Word register? */ | |
194 | ||
195 | int | |
196 | i386_word_regnum_p (struct gdbarch *gdbarch, int regnum) | |
197 | { | |
08106042 | 198 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1ba53b71 L |
199 | |
200 | regnum -= tdep->ax_regnum; | |
201 | return regnum >= 0 && regnum < tdep->num_word_regs; | |
202 | } | |
203 | ||
204 | /* Dword register? */ | |
205 | ||
206 | int | |
207 | i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum) | |
208 | { | |
08106042 | 209 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1ba53b71 L |
210 | int eax_regnum = tdep->eax_regnum; |
211 | ||
212 | if (eax_regnum < 0) | |
213 | return 0; | |
214 | ||
215 | regnum -= eax_regnum; | |
216 | return regnum >= 0 && regnum < tdep->num_dword_regs; | |
28fc6740 AC |
217 | } |
218 | ||
01f9f808 MS |
219 | /* AVX512 register? */ |
220 | ||
221 | int | |
222 | i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum) | |
223 | { | |
08106042 | 224 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
01f9f808 MS |
225 | int zmm0h_regnum = tdep->zmm0h_regnum; |
226 | ||
227 | if (zmm0h_regnum < 0) | |
228 | return 0; | |
229 | ||
230 | regnum -= zmm0h_regnum; | |
231 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
232 | } | |
233 | ||
234 | int | |
235 | i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
236 | { | |
08106042 | 237 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
01f9f808 MS |
238 | int zmm0_regnum = tdep->zmm0_regnum; |
239 | ||
240 | if (zmm0_regnum < 0) | |
241 | return 0; | |
242 | ||
243 | regnum -= zmm0_regnum; | |
244 | return regnum >= 0 && regnum < tdep->num_zmm_regs; | |
245 | } | |
246 | ||
247 | int | |
248 | i386_k_regnum_p (struct gdbarch *gdbarch, int regnum) | |
249 | { | |
08106042 | 250 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
01f9f808 MS |
251 | int k0_regnum = tdep->k0_regnum; |
252 | ||
253 | if (k0_regnum < 0) | |
254 | return 0; | |
255 | ||
256 | regnum -= k0_regnum; | |
257 | return regnum >= 0 && regnum < I387_NUM_K_REGS; | |
258 | } | |
259 | ||
9191d390 | 260 | static int |
c131fcee L |
261 | i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum) |
262 | { | |
08106042 | 263 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
c131fcee L |
264 | int ymm0h_regnum = tdep->ymm0h_regnum; |
265 | ||
266 | if (ymm0h_regnum < 0) | |
267 | return 0; | |
268 | ||
269 | regnum -= ymm0h_regnum; | |
270 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
271 | } | |
272 | ||
273 | /* AVX register? */ | |
274 | ||
275 | int | |
276 | i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
277 | { | |
08106042 | 278 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
c131fcee L |
279 | int ymm0_regnum = tdep->ymm0_regnum; |
280 | ||
281 | if (ymm0_regnum < 0) | |
282 | return 0; | |
283 | ||
284 | regnum -= ymm0_regnum; | |
285 | return regnum >= 0 && regnum < tdep->num_ymm_regs; | |
286 | } | |
287 | ||
01f9f808 MS |
288 | static int |
289 | i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
290 | { | |
08106042 | 291 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
01f9f808 MS |
292 | int ymm16h_regnum = tdep->ymm16h_regnum; |
293 | ||
294 | if (ymm16h_regnum < 0) | |
295 | return 0; | |
296 | ||
297 | regnum -= ymm16h_regnum; | |
298 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
299 | } | |
300 | ||
301 | int | |
302 | i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
303 | { | |
08106042 | 304 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
01f9f808 MS |
305 | int ymm16_regnum = tdep->ymm16_regnum; |
306 | ||
307 | if (ymm16_regnum < 0) | |
308 | return 0; | |
309 | ||
310 | regnum -= ymm16_regnum; | |
311 | return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs; | |
312 | } | |
313 | ||
1dbcd68c WT |
314 | /* BND register? */ |
315 | ||
316 | int | |
317 | i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum) | |
318 | { | |
08106042 | 319 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1dbcd68c WT |
320 | int bnd0_regnum = tdep->bnd0_regnum; |
321 | ||
322 | if (bnd0_regnum < 0) | |
323 | return 0; | |
324 | ||
325 | regnum -= bnd0_regnum; | |
326 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
327 | } | |
328 | ||
5716833c | 329 | /* SSE register? */ |
23a34459 | 330 | |
c131fcee L |
331 | int |
332 | i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 333 | { |
08106042 | 334 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
c131fcee | 335 | int num_xmm_regs = I387_NUM_XMM_REGS (tdep); |
5716833c | 336 | |
c131fcee | 337 | if (num_xmm_regs == 0) |
5716833c MK |
338 | return 0; |
339 | ||
c131fcee L |
340 | regnum -= I387_XMM0_REGNUM (tdep); |
341 | return regnum >= 0 && regnum < num_xmm_regs; | |
23a34459 AC |
342 | } |
343 | ||
01f9f808 MS |
344 | /* XMM_512 register? */ |
345 | ||
346 | int | |
347 | i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum) | |
348 | { | |
08106042 | 349 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
01f9f808 MS |
350 | int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep); |
351 | ||
352 | if (num_xmm_avx512_regs == 0) | |
353 | return 0; | |
354 | ||
355 | regnum -= I387_XMM16_REGNUM (tdep); | |
356 | return regnum >= 0 && regnum < num_xmm_avx512_regs; | |
357 | } | |
358 | ||
5716833c MK |
359 | static int |
360 | i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
23a34459 | 361 | { |
08106042 | 362 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
5716833c | 363 | |
20a6ec49 | 364 | if (I387_NUM_XMM_REGS (tdep) == 0) |
5716833c MK |
365 | return 0; |
366 | ||
20a6ec49 | 367 | return (regnum == I387_MXCSR_REGNUM (tdep)); |
23a34459 AC |
368 | } |
369 | ||
5716833c | 370 | /* FP register? */ |
23a34459 AC |
371 | |
372 | int | |
20a6ec49 | 373 | i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 374 | { |
08106042 | 375 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
20a6ec49 MD |
376 | |
377 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
378 | return 0; |
379 | ||
20a6ec49 MD |
380 | return (I387_ST0_REGNUM (tdep) <= regnum |
381 | && regnum < I387_FCTRL_REGNUM (tdep)); | |
23a34459 AC |
382 | } |
383 | ||
384 | int | |
20a6ec49 | 385 | i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum) |
23a34459 | 386 | { |
08106042 | 387 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
20a6ec49 MD |
388 | |
389 | if (I387_ST0_REGNUM (tdep) < 0) | |
5716833c MK |
390 | return 0; |
391 | ||
20a6ec49 MD |
392 | return (I387_FCTRL_REGNUM (tdep) <= regnum |
393 | && regnum < I387_XMM0_REGNUM (tdep)); | |
23a34459 AC |
394 | } |
395 | ||
1dbcd68c WT |
396 | /* BNDr (raw) register? */ |
397 | ||
398 | static int | |
399 | i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum) | |
400 | { | |
08106042 | 401 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1dbcd68c WT |
402 | |
403 | if (I387_BND0R_REGNUM (tdep) < 0) | |
404 | return 0; | |
405 | ||
406 | regnum -= tdep->bnd0r_regnum; | |
407 | return regnum >= 0 && regnum < I387_NUM_BND_REGS; | |
408 | } | |
409 | ||
410 | /* BND control register? */ | |
411 | ||
412 | static int | |
413 | i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum) | |
414 | { | |
08106042 | 415 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1dbcd68c WT |
416 | |
417 | if (I387_BNDCFGU_REGNUM (tdep) < 0) | |
418 | return 0; | |
419 | ||
420 | regnum -= I387_BNDCFGU_REGNUM (tdep); | |
421 | return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS; | |
422 | } | |
423 | ||
51547df6 MS |
424 | /* PKRU register? */ |
425 | ||
426 | bool | |
427 | i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum) | |
428 | { | |
08106042 | 429 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
51547df6 MS |
430 | int pkru_regnum = tdep->pkru_regnum; |
431 | ||
432 | if (pkru_regnum < 0) | |
433 | return false; | |
434 | ||
435 | regnum -= pkru_regnum; | |
436 | return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS; | |
437 | } | |
438 | ||
c131fcee L |
439 | /* Return the name of register REGNUM, or the empty string if it is |
440 | an anonymous register. */ | |
441 | ||
442 | static const char * | |
443 | i386_register_name (struct gdbarch *gdbarch, int regnum) | |
444 | { | |
445 | /* Hide the upper YMM registers. */ | |
446 | if (i386_ymmh_regnum_p (gdbarch, regnum)) | |
447 | return ""; | |
448 | ||
01f9f808 MS |
449 | /* Hide the upper YMM16-31 registers. */ |
450 | if (i386_ymmh_avx512_regnum_p (gdbarch, regnum)) | |
451 | return ""; | |
452 | ||
453 | /* Hide the upper ZMM registers. */ | |
454 | if (i386_zmmh_regnum_p (gdbarch, regnum)) | |
455 | return ""; | |
456 | ||
c131fcee L |
457 | return tdesc_register_name (gdbarch, regnum); |
458 | } | |
459 | ||
30b0e2d8 | 460 | /* Return the name of register REGNUM. */ |
fc633446 | 461 | |
1ba53b71 | 462 | const char * |
90884b2b | 463 | i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum) |
fc633446 | 464 | { |
08106042 | 465 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1dbcd68c WT |
466 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
467 | return i386_bnd_names[regnum - tdep->bnd0_regnum]; | |
1ba53b71 L |
468 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
469 | return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)]; | |
c131fcee L |
470 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
471 | return i386_ymm_names[regnum - tdep->ymm0_regnum]; | |
01f9f808 MS |
472 | else if (i386_zmm_regnum_p (gdbarch, regnum)) |
473 | return i386_zmm_names[regnum - tdep->zmm0_regnum]; | |
1ba53b71 L |
474 | else if (i386_byte_regnum_p (gdbarch, regnum)) |
475 | return i386_byte_names[regnum - tdep->al_regnum]; | |
476 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
477 | return i386_word_names[regnum - tdep->ax_regnum]; | |
478 | ||
f34652de | 479 | internal_error (_("invalid regnum")); |
fc633446 MK |
480 | } |
481 | ||
c4fc7f1b | 482 | /* Convert a dbx register number REG to the appropriate register |
85540d8c MK |
483 | number used by GDB. */ |
484 | ||
8201327c | 485 | static int |
d3f73121 | 486 | i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 487 | { |
08106042 | 488 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
20a6ec49 | 489 | |
c4fc7f1b MK |
490 | /* This implements what GCC calls the "default" register map |
491 | (dbx_register_map[]). */ | |
492 | ||
85540d8c MK |
493 | if (reg >= 0 && reg <= 7) |
494 | { | |
9872ad24 | 495 | /* General-purpose registers. The debug info calls %ebp |
dda83cd7 | 496 | register 4, and %esp register 5. */ |
9872ad24 | 497 | if (reg == 4) |
dda83cd7 | 498 | return 5; |
9872ad24 | 499 | else if (reg == 5) |
dda83cd7 | 500 | return 4; |
9872ad24 | 501 | else return reg; |
85540d8c MK |
502 | } |
503 | else if (reg >= 12 && reg <= 19) | |
504 | { | |
505 | /* Floating-point registers. */ | |
20a6ec49 | 506 | return reg - 12 + I387_ST0_REGNUM (tdep); |
85540d8c MK |
507 | } |
508 | else if (reg >= 21 && reg <= 28) | |
509 | { | |
510 | /* SSE registers. */ | |
c131fcee L |
511 | int ymm0_regnum = tdep->ymm0_regnum; |
512 | ||
513 | if (ymm0_regnum >= 0 | |
514 | && i386_xmm_regnum_p (gdbarch, reg)) | |
515 | return reg - 21 + ymm0_regnum; | |
516 | else | |
517 | return reg - 21 + I387_XMM0_REGNUM (tdep); | |
85540d8c MK |
518 | } |
519 | else if (reg >= 29 && reg <= 36) | |
520 | { | |
521 | /* MMX registers. */ | |
20a6ec49 | 522 | return reg - 29 + I387_MM0_REGNUM (tdep); |
85540d8c MK |
523 | } |
524 | ||
525 | /* This will hopefully provoke a warning. */ | |
f6efe3f8 | 526 | return gdbarch_num_cooked_regs (gdbarch); |
85540d8c MK |
527 | } |
528 | ||
0fde2c53 | 529 | /* Convert SVR4 DWARF register number REG to the appropriate register number |
c4fc7f1b | 530 | used by GDB. */ |
85540d8c | 531 | |
8201327c | 532 | static int |
0fde2c53 | 533 | i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
85540d8c | 534 | { |
08106042 | 535 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
20a6ec49 | 536 | |
c4fc7f1b MK |
537 | /* This implements the GCC register map that tries to be compatible |
538 | with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */ | |
539 | ||
540 | /* The SVR4 register numbering includes %eip and %eflags, and | |
85540d8c MK |
541 | numbers the floating point registers differently. */ |
542 | if (reg >= 0 && reg <= 9) | |
543 | { | |
acd5c798 | 544 | /* General-purpose registers. */ |
85540d8c MK |
545 | return reg; |
546 | } | |
547 | else if (reg >= 11 && reg <= 18) | |
548 | { | |
549 | /* Floating-point registers. */ | |
20a6ec49 | 550 | return reg - 11 + I387_ST0_REGNUM (tdep); |
85540d8c | 551 | } |
c6f4c129 | 552 | else if (reg >= 21 && reg <= 36) |
85540d8c | 553 | { |
c4fc7f1b | 554 | /* The SSE and MMX registers have the same numbers as with dbx. */ |
d3f73121 | 555 | return i386_dbx_reg_to_regnum (gdbarch, reg); |
85540d8c MK |
556 | } |
557 | ||
c6f4c129 JB |
558 | switch (reg) |
559 | { | |
20a6ec49 MD |
560 | case 37: return I387_FCTRL_REGNUM (tdep); |
561 | case 38: return I387_FSTAT_REGNUM (tdep); | |
562 | case 39: return I387_MXCSR_REGNUM (tdep); | |
c6f4c129 JB |
563 | case 40: return I386_ES_REGNUM; |
564 | case 41: return I386_CS_REGNUM; | |
565 | case 42: return I386_SS_REGNUM; | |
566 | case 43: return I386_DS_REGNUM; | |
567 | case 44: return I386_FS_REGNUM; | |
568 | case 45: return I386_GS_REGNUM; | |
569 | } | |
570 | ||
0fde2c53 DE |
571 | return -1; |
572 | } | |
573 | ||
574 | /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return | |
575 | num_regs + num_pseudo_regs for other debug formats. */ | |
576 | ||
8f10c932 | 577 | int |
0fde2c53 DE |
578 | i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg) |
579 | { | |
580 | int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg); | |
581 | ||
582 | if (regnum == -1) | |
f6efe3f8 | 583 | return gdbarch_num_cooked_regs (gdbarch); |
0fde2c53 | 584 | return regnum; |
85540d8c | 585 | } |
5716833c | 586 | |
fc338970 | 587 | \f |
917317f4 | 588 | |
fc338970 MK |
589 | /* This is the variable that is set with "set disassembly-flavor", and |
590 | its legitimate values. */ | |
53904c9e AC |
591 | static const char att_flavor[] = "att"; |
592 | static const char intel_flavor[] = "intel"; | |
40478521 | 593 | static const char *const valid_flavors[] = |
c5aa993b | 594 | { |
c906108c SS |
595 | att_flavor, |
596 | intel_flavor, | |
597 | NULL | |
598 | }; | |
53904c9e | 599 | static const char *disassembly_flavor = att_flavor; |
acd5c798 | 600 | \f |
c906108c | 601 | |
acd5c798 MK |
602 | /* Use the program counter to determine the contents and size of a |
603 | breakpoint instruction. Return a pointer to a string of bytes that | |
604 | encode a breakpoint instruction, store the length of the string in | |
605 | *LEN and optionally adjust *PC to point to the correct memory | |
606 | location for inserting the breakpoint. | |
c906108c | 607 | |
acd5c798 MK |
608 | On the i386 we have a single breakpoint that fits in a single byte |
609 | and can be inserted anywhere. | |
c906108c | 610 | |
acd5c798 | 611 | This function is 64-bit safe. */ |
63c0089f | 612 | |
04180708 YQ |
613 | constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */ |
614 | ||
615 | typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint; | |
63c0089f | 616 | |
237fc4c9 PA |
617 | \f |
618 | /* Displaced instruction handling. */ | |
619 | ||
1903f0e6 DE |
620 | /* Skip the legacy instruction prefixes in INSN. |
621 | Not all prefixes are valid for any particular insn | |
622 | but we needn't care, the insn will fault if it's invalid. | |
623 | The result is a pointer to the first opcode byte, | |
624 | or NULL if we run off the end of the buffer. */ | |
625 | ||
626 | static gdb_byte * | |
627 | i386_skip_prefixes (gdb_byte *insn, size_t max_len) | |
628 | { | |
629 | gdb_byte *end = insn + max_len; | |
630 | ||
631 | while (insn < end) | |
632 | { | |
633 | switch (*insn) | |
634 | { | |
635 | case DATA_PREFIX_OPCODE: | |
636 | case ADDR_PREFIX_OPCODE: | |
637 | case CS_PREFIX_OPCODE: | |
638 | case DS_PREFIX_OPCODE: | |
639 | case ES_PREFIX_OPCODE: | |
640 | case FS_PREFIX_OPCODE: | |
641 | case GS_PREFIX_OPCODE: | |
642 | case SS_PREFIX_OPCODE: | |
643 | case LOCK_PREFIX_OPCODE: | |
644 | case REPE_PREFIX_OPCODE: | |
645 | case REPNE_PREFIX_OPCODE: | |
646 | ++insn; | |
647 | continue; | |
648 | default: | |
649 | return insn; | |
650 | } | |
651 | } | |
652 | ||
653 | return NULL; | |
654 | } | |
237fc4c9 PA |
655 | |
656 | static int | |
1903f0e6 | 657 | i386_absolute_jmp_p (const gdb_byte *insn) |
237fc4c9 | 658 | { |
1777feb0 | 659 | /* jmp far (absolute address in operand). */ |
237fc4c9 PA |
660 | if (insn[0] == 0xea) |
661 | return 1; | |
662 | ||
663 | if (insn[0] == 0xff) | |
664 | { | |
1777feb0 | 665 | /* jump near, absolute indirect (/4). */ |
237fc4c9 | 666 | if ((insn[1] & 0x38) == 0x20) |
dda83cd7 | 667 | return 1; |
237fc4c9 | 668 | |
1777feb0 | 669 | /* jump far, absolute indirect (/5). */ |
237fc4c9 | 670 | if ((insn[1] & 0x38) == 0x28) |
dda83cd7 | 671 | return 1; |
237fc4c9 PA |
672 | } |
673 | ||
674 | return 0; | |
675 | } | |
676 | ||
c2170eef MM |
677 | /* Return non-zero if INSN is a jump, zero otherwise. */ |
678 | ||
679 | static int | |
680 | i386_jmp_p (const gdb_byte *insn) | |
681 | { | |
682 | /* jump short, relative. */ | |
683 | if (insn[0] == 0xeb) | |
684 | return 1; | |
685 | ||
686 | /* jump near, relative. */ | |
687 | if (insn[0] == 0xe9) | |
688 | return 1; | |
689 | ||
690 | return i386_absolute_jmp_p (insn); | |
691 | } | |
692 | ||
237fc4c9 | 693 | static int |
1903f0e6 | 694 | i386_absolute_call_p (const gdb_byte *insn) |
237fc4c9 | 695 | { |
1777feb0 | 696 | /* call far, absolute. */ |
237fc4c9 PA |
697 | if (insn[0] == 0x9a) |
698 | return 1; | |
699 | ||
700 | if (insn[0] == 0xff) | |
701 | { | |
1777feb0 | 702 | /* Call near, absolute indirect (/2). */ |
237fc4c9 | 703 | if ((insn[1] & 0x38) == 0x10) |
dda83cd7 | 704 | return 1; |
237fc4c9 | 705 | |
1777feb0 | 706 | /* Call far, absolute indirect (/3). */ |
237fc4c9 | 707 | if ((insn[1] & 0x38) == 0x18) |
dda83cd7 | 708 | return 1; |
237fc4c9 PA |
709 | } |
710 | ||
711 | return 0; | |
712 | } | |
713 | ||
714 | static int | |
1903f0e6 | 715 | i386_ret_p (const gdb_byte *insn) |
237fc4c9 PA |
716 | { |
717 | switch (insn[0]) | |
718 | { | |
1777feb0 | 719 | case 0xc2: /* ret near, pop N bytes. */ |
237fc4c9 | 720 | case 0xc3: /* ret near */ |
1777feb0 | 721 | case 0xca: /* ret far, pop N bytes. */ |
237fc4c9 PA |
722 | case 0xcb: /* ret far */ |
723 | case 0xcf: /* iret */ | |
724 | return 1; | |
725 | ||
726 | default: | |
727 | return 0; | |
728 | } | |
729 | } | |
730 | ||
731 | static int | |
1903f0e6 | 732 | i386_call_p (const gdb_byte *insn) |
237fc4c9 PA |
733 | { |
734 | if (i386_absolute_call_p (insn)) | |
735 | return 1; | |
736 | ||
1777feb0 | 737 | /* call near, relative. */ |
237fc4c9 PA |
738 | if (insn[0] == 0xe8) |
739 | return 1; | |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
237fc4c9 PA |
744 | /* Return non-zero if INSN is a system call, and set *LENGTHP to its |
745 | length in bytes. Otherwise, return zero. */ | |
1903f0e6 | 746 | |
237fc4c9 | 747 | static int |
b55078be | 748 | i386_syscall_p (const gdb_byte *insn, int *lengthp) |
237fc4c9 | 749 | { |
9a7f938f JK |
750 | /* Is it 'int $0x80'? */ |
751 | if ((insn[0] == 0xcd && insn[1] == 0x80) | |
752 | /* Or is it 'sysenter'? */ | |
753 | || (insn[0] == 0x0f && insn[1] == 0x34) | |
754 | /* Or is it 'syscall'? */ | |
755 | || (insn[0] == 0x0f && insn[1] == 0x05)) | |
237fc4c9 PA |
756 | { |
757 | *lengthp = 2; | |
758 | return 1; | |
759 | } | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
c2170eef MM |
764 | /* The gdbarch insn_is_call method. */ |
765 | ||
766 | static int | |
767 | i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) | |
768 | { | |
769 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
770 | ||
771 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
772 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
773 | ||
774 | return i386_call_p (insn); | |
775 | } | |
776 | ||
777 | /* The gdbarch insn_is_ret method. */ | |
778 | ||
779 | static int | |
780 | i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) | |
781 | { | |
782 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
783 | ||
784 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
785 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
786 | ||
787 | return i386_ret_p (insn); | |
788 | } | |
789 | ||
790 | /* The gdbarch insn_is_jump method. */ | |
791 | ||
792 | static int | |
793 | i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) | |
794 | { | |
795 | gdb_byte buf[I386_MAX_INSN_LEN], *insn; | |
796 | ||
797 | read_code (addr, buf, I386_MAX_INSN_LEN); | |
798 | insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN); | |
799 | ||
800 | return i386_jmp_p (insn); | |
801 | } | |
802 | ||
c2508e90 | 803 | /* Some kernels may run one past a syscall insn, so we have to cope. */ |
b55078be | 804 | |
1152d984 | 805 | displaced_step_copy_insn_closure_up |
b55078be DE |
806 | i386_displaced_step_copy_insn (struct gdbarch *gdbarch, |
807 | CORE_ADDR from, CORE_ADDR to, | |
808 | struct regcache *regs) | |
809 | { | |
810 | size_t len = gdbarch_max_insn_length (gdbarch); | |
1152d984 SM |
811 | std::unique_ptr<i386_displaced_step_copy_insn_closure> closure |
812 | (new i386_displaced_step_copy_insn_closure (len)); | |
cfba9872 | 813 | gdb_byte *buf = closure->buf.data (); |
b55078be DE |
814 | |
815 | read_memory (from, buf, len); | |
816 | ||
817 | /* GDB may get control back after the insn after the syscall. | |
818 | Presumably this is a kernel bug. | |
819 | If this is a syscall, make sure there's a nop afterwards. */ | |
820 | { | |
821 | int syscall_length; | |
822 | gdb_byte *insn; | |
823 | ||
824 | insn = i386_skip_prefixes (buf, len); | |
825 | if (insn != NULL && i386_syscall_p (insn, &syscall_length)) | |
826 | insn[syscall_length] = NOP_OPCODE; | |
827 | } | |
828 | ||
829 | write_memory (to, buf, len); | |
830 | ||
136821d9 | 831 | displaced_debug_printf ("%s->%s: %s", |
dda83cd7 | 832 | paddress (gdbarch, from), paddress (gdbarch, to), |
136821d9 | 833 | displaced_step_dump_bytes (buf, len).c_str ()); |
b55078be | 834 | |
6d0cf446 | 835 | /* This is a work around for a problem with g++ 4.8. */ |
1152d984 | 836 | return displaced_step_copy_insn_closure_up (closure.release ()); |
b55078be DE |
837 | } |
838 | ||
237fc4c9 PA |
839 | /* Fix up the state of registers and memory after having single-stepped |
840 | a displaced instruction. */ | |
1903f0e6 | 841 | |
237fc4c9 PA |
842 | void |
843 | i386_displaced_step_fixup (struct gdbarch *gdbarch, | |
1152d984 | 844 | struct displaced_step_copy_insn_closure *closure_, |
dda83cd7 SM |
845 | CORE_ADDR from, CORE_ADDR to, |
846 | struct regcache *regs) | |
237fc4c9 | 847 | { |
e17a4113 UW |
848 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
849 | ||
237fc4c9 PA |
850 | /* The offset we applied to the instruction's address. |
851 | This could well be negative (when viewed as a signed 32-bit | |
852 | value), but ULONGEST won't reflect that, so take care when | |
853 | applying it. */ | |
854 | ULONGEST insn_offset = to - from; | |
855 | ||
1152d984 SM |
856 | i386_displaced_step_copy_insn_closure *closure |
857 | = (i386_displaced_step_copy_insn_closure *) closure_; | |
cfba9872 | 858 | gdb_byte *insn = closure->buf.data (); |
1903f0e6 DE |
859 | /* The start of the insn, needed in case we see some prefixes. */ |
860 | gdb_byte *insn_start = insn; | |
237fc4c9 | 861 | |
136821d9 SM |
862 | displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...", |
863 | paddress (gdbarch, from), paddress (gdbarch, to), | |
864 | insn[0], insn[1]); | |
237fc4c9 PA |
865 | |
866 | /* The list of issues to contend with here is taken from | |
867 | resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20. | |
868 | Yay for Free Software! */ | |
869 | ||
870 | /* Relocate the %eip, if necessary. */ | |
871 | ||
1903f0e6 DE |
872 | /* The instruction recognizers we use assume any leading prefixes |
873 | have been skipped. */ | |
874 | { | |
875 | /* This is the size of the buffer in closure. */ | |
876 | size_t max_insn_len = gdbarch_max_insn_length (gdbarch); | |
877 | gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len); | |
878 | /* If there are too many prefixes, just ignore the insn. | |
879 | It will fault when run. */ | |
880 | if (opcode != NULL) | |
881 | insn = opcode; | |
882 | } | |
883 | ||
237fc4c9 PA |
884 | /* Except in the case of absolute or indirect jump or call |
885 | instructions, or a return instruction, the new eip is relative to | |
886 | the displaced instruction; make it relative. Well, signal | |
887 | handler returns don't need relocation either, but we use the | |
888 | value of %eip to recognize those; see below. */ | |
889 | if (! i386_absolute_jmp_p (insn) | |
890 | && ! i386_absolute_call_p (insn) | |
891 | && ! i386_ret_p (insn)) | |
892 | { | |
893 | ULONGEST orig_eip; | |
b55078be | 894 | int insn_len; |
237fc4c9 PA |
895 | |
896 | regcache_cooked_read_unsigned (regs, I386_EIP_REGNUM, &orig_eip); | |
897 | ||
898 | /* A signal trampoline system call changes the %eip, resuming | |
dda83cd7 SM |
899 | execution of the main program after the signal handler has |
900 | returned. That makes them like 'return' instructions; we | |
901 | shouldn't relocate %eip. | |
902 | ||
903 | But most system calls don't, and we do need to relocate %eip. | |
904 | ||
905 | Our heuristic for distinguishing these cases: if stepping | |
906 | over the system call instruction left control directly after | |
907 | the instruction, the we relocate --- control almost certainly | |
908 | doesn't belong in the displaced copy. Otherwise, we assume | |
909 | the instruction has put control where it belongs, and leave | |
910 | it unrelocated. Goodness help us if there are PC-relative | |
911 | system calls. */ | |
237fc4c9 | 912 | if (i386_syscall_p (insn, &insn_len) |
dda83cd7 | 913 | && orig_eip != to + (insn - insn_start) + insn_len |
b55078be DE |
914 | /* GDB can get control back after the insn after the syscall. |
915 | Presumably this is a kernel bug. | |
916 | i386_displaced_step_copy_insn ensures its a nop, | |
917 | we add one to the length for it. */ | |
136821d9 SM |
918 | && orig_eip != to + (insn - insn_start) + insn_len + 1) |
919 | displaced_debug_printf ("syscall changed %%eip; not relocating"); | |
237fc4c9 | 920 | else |
dda83cd7 SM |
921 | { |
922 | ULONGEST eip = (orig_eip - insn_offset) & 0xffffffffUL; | |
237fc4c9 | 923 | |
1903f0e6 DE |
924 | /* If we just stepped over a breakpoint insn, we don't backup |
925 | the pc on purpose; this is to match behaviour without | |
926 | stepping. */ | |
237fc4c9 | 927 | |
dda83cd7 | 928 | regcache_cooked_write_unsigned (regs, I386_EIP_REGNUM, eip); |
237fc4c9 | 929 | |
136821d9 SM |
930 | displaced_debug_printf ("relocated %%eip from %s to %s", |
931 | paddress (gdbarch, orig_eip), | |
932 | paddress (gdbarch, eip)); | |
dda83cd7 | 933 | } |
237fc4c9 PA |
934 | } |
935 | ||
936 | /* If the instruction was PUSHFL, then the TF bit will be set in the | |
937 | pushed value, and should be cleared. We'll leave this for later, | |
938 | since GDB already messes up the TF flag when stepping over a | |
939 | pushfl. */ | |
940 | ||
941 | /* If the instruction was a call, the return address now atop the | |
942 | stack is the address following the copied instruction. We need | |
943 | to make it the address following the original instruction. */ | |
944 | if (i386_call_p (insn)) | |
945 | { | |
946 | ULONGEST esp; | |
947 | ULONGEST retaddr; | |
948 | const ULONGEST retaddr_len = 4; | |
949 | ||
950 | regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp); | |
b75f0b83 | 951 | retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order); |
237fc4c9 | 952 | retaddr = (retaddr - insn_offset) & 0xffffffffUL; |
e17a4113 | 953 | write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr); |
237fc4c9 | 954 | |
136821d9 SM |
955 | displaced_debug_printf ("relocated return addr at %s to %s", |
956 | paddress (gdbarch, esp), | |
957 | paddress (gdbarch, retaddr)); | |
237fc4c9 PA |
958 | } |
959 | } | |
dde08ee1 PA |
960 | |
961 | static void | |
962 | append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) | |
963 | { | |
964 | target_write_memory (*to, buf, len); | |
965 | *to += len; | |
966 | } | |
967 | ||
968 | static void | |
969 | i386_relocate_instruction (struct gdbarch *gdbarch, | |
970 | CORE_ADDR *to, CORE_ADDR oldloc) | |
971 | { | |
972 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
973 | gdb_byte buf[I386_MAX_INSN_LEN]; | |
974 | int offset = 0, rel32, newrel; | |
975 | int insn_length; | |
976 | gdb_byte *insn = buf; | |
977 | ||
978 | read_memory (oldloc, buf, I386_MAX_INSN_LEN); | |
979 | ||
980 | insn_length = gdb_buffered_insn_length (gdbarch, insn, | |
981 | I386_MAX_INSN_LEN, oldloc); | |
982 | ||
983 | /* Get past the prefixes. */ | |
984 | insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN); | |
985 | ||
986 | /* Adjust calls with 32-bit relative addresses as push/jump, with | |
987 | the address pushed being the location where the original call in | |
988 | the user program would return to. */ | |
989 | if (insn[0] == 0xe8) | |
990 | { | |
991 | gdb_byte push_buf[16]; | |
992 | unsigned int ret_addr; | |
993 | ||
994 | /* Where "ret" in the original code will return to. */ | |
995 | ret_addr = oldloc + insn_length; | |
1777feb0 | 996 | push_buf[0] = 0x68; /* pushq $... */ |
144db827 | 997 | store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr); |
dde08ee1 PA |
998 | /* Push the push. */ |
999 | append_insns (to, 5, push_buf); | |
1000 | ||
1001 | /* Convert the relative call to a relative jump. */ | |
1002 | insn[0] = 0xe9; | |
1003 | ||
1004 | /* Adjust the destination offset. */ | |
1005 | rel32 = extract_signed_integer (insn + 1, 4, byte_order); | |
1006 | newrel = (oldloc - *to) + rel32; | |
f4a1794a KY |
1007 | store_signed_integer (insn + 1, 4, byte_order, newrel); |
1008 | ||
136821d9 SM |
1009 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1010 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1011 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1012 | |
1013 | /* Write the adjusted jump into its displaced location. */ | |
1014 | append_insns (to, 5, insn); | |
1015 | return; | |
1016 | } | |
1017 | ||
1018 | /* Adjust jumps with 32-bit relative addresses. Calls are already | |
1019 | handled above. */ | |
1020 | if (insn[0] == 0xe9) | |
1021 | offset = 1; | |
1022 | /* Adjust conditional jumps. */ | |
1023 | else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80) | |
1024 | offset = 2; | |
1025 | ||
1026 | if (offset) | |
1027 | { | |
1028 | rel32 = extract_signed_integer (insn + offset, 4, byte_order); | |
1029 | newrel = (oldloc - *to) + rel32; | |
f4a1794a | 1030 | store_signed_integer (insn + offset, 4, byte_order, newrel); |
136821d9 SM |
1031 | displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s", |
1032 | hex_string (rel32), paddress (gdbarch, oldloc), | |
1033 | hex_string (newrel), paddress (gdbarch, *to)); | |
dde08ee1 PA |
1034 | } |
1035 | ||
1036 | /* Write the adjusted instructions into their displaced | |
1037 | location. */ | |
1038 | append_insns (to, insn_length, buf); | |
1039 | } | |
1040 | ||
fc338970 | 1041 | \f |
acd5c798 MK |
1042 | #ifdef I386_REGNO_TO_SYMMETRY |
1043 | #error "The Sequent Symmetry is no longer supported." | |
1044 | #endif | |
c906108c | 1045 | |
acd5c798 MK |
1046 | /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi |
1047 | and %esp "belong" to the calling function. Therefore these | |
1048 | registers should be saved if they're going to be modified. */ | |
c906108c | 1049 | |
acd5c798 MK |
1050 | /* The maximum number of saved registers. This should include all |
1051 | registers mentioned above, and %eip. */ | |
a3386186 | 1052 | #define I386_NUM_SAVED_REGS I386_NUM_GREGS |
acd5c798 MK |
1053 | |
1054 | struct i386_frame_cache | |
c906108c | 1055 | { |
acd5c798 MK |
1056 | /* Base address. */ |
1057 | CORE_ADDR base; | |
8fbca658 | 1058 | int base_p; |
772562f8 | 1059 | LONGEST sp_offset; |
acd5c798 MK |
1060 | CORE_ADDR pc; |
1061 | ||
fd13a04a AC |
1062 | /* Saved registers. */ |
1063 | CORE_ADDR saved_regs[I386_NUM_SAVED_REGS]; | |
acd5c798 | 1064 | CORE_ADDR saved_sp; |
e0c62198 | 1065 | int saved_sp_reg; |
acd5c798 MK |
1066 | int pc_in_eax; |
1067 | ||
1068 | /* Stack space reserved for local variables. */ | |
1069 | long locals; | |
1070 | }; | |
1071 | ||
1072 | /* Allocate and initialize a frame cache. */ | |
1073 | ||
1074 | static struct i386_frame_cache * | |
fd13a04a | 1075 | i386_alloc_frame_cache (void) |
acd5c798 MK |
1076 | { |
1077 | struct i386_frame_cache *cache; | |
1078 | int i; | |
1079 | ||
1080 | cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache); | |
1081 | ||
1082 | /* Base address. */ | |
8fbca658 | 1083 | cache->base_p = 0; |
acd5c798 MK |
1084 | cache->base = 0; |
1085 | cache->sp_offset = -4; | |
1086 | cache->pc = 0; | |
1087 | ||
fd13a04a AC |
1088 | /* Saved registers. We initialize these to -1 since zero is a valid |
1089 | offset (that's where %ebp is supposed to be stored). */ | |
1090 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
1091 | cache->saved_regs[i] = -1; | |
acd5c798 | 1092 | cache->saved_sp = 0; |
e0c62198 | 1093 | cache->saved_sp_reg = -1; |
acd5c798 MK |
1094 | cache->pc_in_eax = 0; |
1095 | ||
1096 | /* Frameless until proven otherwise. */ | |
1097 | cache->locals = -1; | |
1098 | ||
1099 | return cache; | |
1100 | } | |
c906108c | 1101 | |
acd5c798 MK |
1102 | /* If the instruction at PC is a jump, return the address of its |
1103 | target. Otherwise, return PC. */ | |
c906108c | 1104 | |
acd5c798 | 1105 | static CORE_ADDR |
e17a4113 | 1106 | i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc) |
acd5c798 | 1107 | { |
e17a4113 | 1108 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 1109 | gdb_byte op; |
acd5c798 MK |
1110 | long delta = 0; |
1111 | int data16 = 0; | |
c906108c | 1112 | |
0865b04a | 1113 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1114 | return pc; |
1115 | ||
acd5c798 | 1116 | if (op == 0x66) |
c906108c | 1117 | { |
c906108c | 1118 | data16 = 1; |
0865b04a YQ |
1119 | |
1120 | op = read_code_unsigned_integer (pc + 1, 1, byte_order); | |
c906108c SS |
1121 | } |
1122 | ||
acd5c798 | 1123 | switch (op) |
c906108c SS |
1124 | { |
1125 | case 0xe9: | |
fc338970 | 1126 | /* Relative jump: if data16 == 0, disp32, else disp16. */ |
c906108c SS |
1127 | if (data16) |
1128 | { | |
e17a4113 | 1129 | delta = read_memory_integer (pc + 2, 2, byte_order); |
c906108c | 1130 | |
fc338970 | 1131 | /* Include the size of the jmp instruction (including the |
dda83cd7 | 1132 | 0x66 prefix). */ |
acd5c798 | 1133 | delta += 4; |
c906108c SS |
1134 | } |
1135 | else | |
1136 | { | |
e17a4113 | 1137 | delta = read_memory_integer (pc + 1, 4, byte_order); |
c906108c | 1138 | |
acd5c798 MK |
1139 | /* Include the size of the jmp instruction. */ |
1140 | delta += 5; | |
c906108c SS |
1141 | } |
1142 | break; | |
1143 | case 0xeb: | |
fc338970 | 1144 | /* Relative jump, disp8 (ignore data16). */ |
e17a4113 | 1145 | delta = read_memory_integer (pc + data16 + 1, 1, byte_order); |
c906108c | 1146 | |
acd5c798 | 1147 | delta += data16 + 2; |
c906108c SS |
1148 | break; |
1149 | } | |
c906108c | 1150 | |
acd5c798 MK |
1151 | return pc + delta; |
1152 | } | |
fc338970 | 1153 | |
acd5c798 MK |
1154 | /* Check whether PC points at a prologue for a function returning a |
1155 | structure or union. If so, it updates CACHE and returns the | |
1156 | address of the first instruction after the code sequence that | |
1157 | removes the "hidden" argument from the stack or CURRENT_PC, | |
1158 | whichever is smaller. Otherwise, return PC. */ | |
c906108c | 1159 | |
acd5c798 MK |
1160 | static CORE_ADDR |
1161 | i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc, | |
1162 | struct i386_frame_cache *cache) | |
c906108c | 1163 | { |
acd5c798 MK |
1164 | /* Functions that return a structure or union start with: |
1165 | ||
dda83cd7 SM |
1166 | popl %eax 0x58 |
1167 | xchgl %eax, (%esp) 0x87 0x04 0x24 | |
acd5c798 MK |
1168 | or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00 |
1169 | ||
1170 | (the System V compiler puts out the second `xchg' instruction, | |
1171 | and the assembler doesn't try to optimize it, so the 'sib' form | |
1172 | gets generated). This sequence is used to get the address of the | |
1173 | return buffer for a function that returns a structure. */ | |
63c0089f MK |
1174 | static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 }; |
1175 | static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 }; | |
1176 | gdb_byte buf[4]; | |
1177 | gdb_byte op; | |
c906108c | 1178 | |
acd5c798 MK |
1179 | if (current_pc <= pc) |
1180 | return pc; | |
1181 | ||
0865b04a | 1182 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1183 | return pc; |
c906108c | 1184 | |
acd5c798 MK |
1185 | if (op != 0x58) /* popl %eax */ |
1186 | return pc; | |
c906108c | 1187 | |
0865b04a | 1188 | if (target_read_code (pc + 1, buf, 4)) |
3dcabaa8 MS |
1189 | return pc; |
1190 | ||
acd5c798 MK |
1191 | if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0) |
1192 | return pc; | |
c906108c | 1193 | |
acd5c798 | 1194 | if (current_pc == pc) |
c906108c | 1195 | { |
acd5c798 MK |
1196 | cache->sp_offset += 4; |
1197 | return current_pc; | |
c906108c SS |
1198 | } |
1199 | ||
acd5c798 | 1200 | if (current_pc == pc + 1) |
c906108c | 1201 | { |
acd5c798 MK |
1202 | cache->pc_in_eax = 1; |
1203 | return current_pc; | |
1204 | } | |
1205 | ||
1206 | if (buf[1] == proto1[1]) | |
1207 | return pc + 4; | |
1208 | else | |
1209 | return pc + 5; | |
1210 | } | |
1211 | ||
1212 | static CORE_ADDR | |
1213 | i386_skip_probe (CORE_ADDR pc) | |
1214 | { | |
1215 | /* A function may start with | |
fc338970 | 1216 | |
dda83cd7 SM |
1217 | pushl constant |
1218 | call _probe | |
acd5c798 | 1219 | addl $4, %esp |
fc338970 | 1220 | |
acd5c798 MK |
1221 | followed by |
1222 | ||
dda83cd7 | 1223 | pushl %ebp |
fc338970 | 1224 | |
acd5c798 | 1225 | etc. */ |
63c0089f MK |
1226 | gdb_byte buf[8]; |
1227 | gdb_byte op; | |
fc338970 | 1228 | |
0865b04a | 1229 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1230 | return pc; |
acd5c798 MK |
1231 | |
1232 | if (op == 0x68 || op == 0x6a) | |
1233 | { | |
1234 | int delta; | |
c906108c | 1235 | |
acd5c798 MK |
1236 | /* Skip past the `pushl' instruction; it has either a one-byte or a |
1237 | four-byte operand, depending on the opcode. */ | |
c906108c | 1238 | if (op == 0x68) |
acd5c798 | 1239 | delta = 5; |
c906108c | 1240 | else |
acd5c798 | 1241 | delta = 2; |
c906108c | 1242 | |
acd5c798 MK |
1243 | /* Read the following 8 bytes, which should be `call _probe' (6 |
1244 | bytes) followed by `addl $4,%esp' (2 bytes). */ | |
1245 | read_memory (pc + delta, buf, sizeof (buf)); | |
c906108c | 1246 | if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4) |
acd5c798 | 1247 | pc += delta + sizeof (buf); |
c906108c SS |
1248 | } |
1249 | ||
acd5c798 MK |
1250 | return pc; |
1251 | } | |
1252 | ||
92dd43fa MK |
1253 | /* GCC 4.1 and later, can put code in the prologue to realign the |
1254 | stack pointer. Check whether PC points to such code, and update | |
1255 | CACHE accordingly. Return the first instruction after the code | |
1256 | sequence or CURRENT_PC, whichever is smaller. If we don't | |
1257 | recognize the code, return PC. */ | |
1258 | ||
1259 | static CORE_ADDR | |
1260 | i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, | |
1261 | struct i386_frame_cache *cache) | |
1262 | { | |
e0c62198 L |
1263 | /* There are 2 code sequences to re-align stack before the frame |
1264 | gets set up: | |
1265 | ||
1266 | 1. Use a caller-saved saved register: | |
1267 | ||
1268 | leal 4(%esp), %reg | |
1269 | andl $-XXX, %esp | |
1270 | pushl -4(%reg) | |
1271 | ||
1272 | 2. Use a callee-saved saved register: | |
1273 | ||
1274 | pushl %reg | |
1275 | leal 8(%esp), %reg | |
1276 | andl $-XXX, %esp | |
1277 | pushl -4(%reg) | |
1278 | ||
1279 | "andl $-XXX, %esp" can be either 3 bytes or 6 bytes: | |
1280 | ||
24b21115 SM |
1281 | 0x83 0xe4 0xf0 andl $-16, %esp |
1282 | 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp | |
e0c62198 L |
1283 | */ |
1284 | ||
1285 | gdb_byte buf[14]; | |
1286 | int reg; | |
1287 | int offset, offset_and; | |
1288 | static int regnums[8] = { | |
1289 | I386_EAX_REGNUM, /* %eax */ | |
1290 | I386_ECX_REGNUM, /* %ecx */ | |
1291 | I386_EDX_REGNUM, /* %edx */ | |
1292 | I386_EBX_REGNUM, /* %ebx */ | |
1293 | I386_ESP_REGNUM, /* %esp */ | |
1294 | I386_EBP_REGNUM, /* %ebp */ | |
1295 | I386_ESI_REGNUM, /* %esi */ | |
1296 | I386_EDI_REGNUM /* %edi */ | |
92dd43fa | 1297 | }; |
92dd43fa | 1298 | |
0865b04a | 1299 | if (target_read_code (pc, buf, sizeof buf)) |
e0c62198 L |
1300 | return pc; |
1301 | ||
1302 | /* Check caller-saved saved register. The first instruction has | |
1303 | to be "leal 4(%esp), %reg". */ | |
1304 | if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4) | |
1305 | { | |
1306 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1307 | if ((buf[1] & 0xc7) != 0x44) | |
1308 | return pc; | |
1309 | ||
1310 | /* REG has register number. */ | |
1311 | reg = (buf[1] >> 3) & 7; | |
1312 | offset = 4; | |
1313 | } | |
1314 | else | |
1315 | { | |
1316 | /* Check callee-saved saved register. The first instruction | |
1317 | has to be "pushl %reg". */ | |
1318 | if ((buf[0] & 0xf8) != 0x50) | |
1319 | return pc; | |
1320 | ||
1321 | /* Get register. */ | |
1322 | reg = buf[0] & 0x7; | |
1323 | ||
1324 | /* The next instruction has to be "leal 8(%esp), %reg". */ | |
1325 | if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8) | |
1326 | return pc; | |
1327 | ||
1328 | /* MOD must be binary 10 and R/M must be binary 100. */ | |
1329 | if ((buf[2] & 0xc7) != 0x44) | |
1330 | return pc; | |
1331 | ||
1332 | /* REG has register number. Registers in pushl and leal have to | |
1333 | be the same. */ | |
1334 | if (reg != ((buf[2] >> 3) & 7)) | |
1335 | return pc; | |
1336 | ||
1337 | offset = 5; | |
1338 | } | |
1339 | ||
1340 | /* Rigister can't be %esp nor %ebp. */ | |
1341 | if (reg == 4 || reg == 5) | |
1342 | return pc; | |
1343 | ||
1344 | /* The next instruction has to be "andl $-XXX, %esp". */ | |
1345 | if (buf[offset + 1] != 0xe4 | |
1346 | || (buf[offset] != 0x81 && buf[offset] != 0x83)) | |
1347 | return pc; | |
1348 | ||
1349 | offset_and = offset; | |
1350 | offset += buf[offset] == 0x81 ? 6 : 3; | |
1351 | ||
1352 | /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is | |
1353 | 0xfc. REG must be binary 110 and MOD must be binary 01. */ | |
1354 | if (buf[offset] != 0xff | |
1355 | || buf[offset + 2] != 0xfc | |
1356 | || (buf[offset + 1] & 0xf8) != 0x70) | |
1357 | return pc; | |
1358 | ||
1359 | /* R/M has register. Registers in leal and pushl have to be the | |
1360 | same. */ | |
1361 | if (reg != (buf[offset + 1] & 7)) | |
92dd43fa MK |
1362 | return pc; |
1363 | ||
e0c62198 L |
1364 | if (current_pc > pc + offset_and) |
1365 | cache->saved_sp_reg = regnums[reg]; | |
92dd43fa | 1366 | |
325fac50 | 1367 | return std::min (pc + offset + 3, current_pc); |
92dd43fa MK |
1368 | } |
1369 | ||
37bdc87e | 1370 | /* Maximum instruction length we need to handle. */ |
237fc4c9 | 1371 | #define I386_MAX_MATCHED_INSN_LEN 6 |
37bdc87e MK |
1372 | |
1373 | /* Instruction description. */ | |
1374 | struct i386_insn | |
1375 | { | |
1376 | size_t len; | |
237fc4c9 PA |
1377 | gdb_byte insn[I386_MAX_MATCHED_INSN_LEN]; |
1378 | gdb_byte mask[I386_MAX_MATCHED_INSN_LEN]; | |
37bdc87e MK |
1379 | }; |
1380 | ||
a3fcb948 | 1381 | /* Return whether instruction at PC matches PATTERN. */ |
37bdc87e | 1382 | |
a3fcb948 JG |
1383 | static int |
1384 | i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern) | |
37bdc87e | 1385 | { |
63c0089f | 1386 | gdb_byte op; |
37bdc87e | 1387 | |
0865b04a | 1388 | if (target_read_code (pc, &op, 1)) |
a3fcb948 | 1389 | return 0; |
37bdc87e | 1390 | |
a3fcb948 | 1391 | if ((op & pattern.mask[0]) == pattern.insn[0]) |
37bdc87e | 1392 | { |
a3fcb948 JG |
1393 | gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1]; |
1394 | int insn_matched = 1; | |
1395 | size_t i; | |
37bdc87e | 1396 | |
a3fcb948 JG |
1397 | gdb_assert (pattern.len > 1); |
1398 | gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN); | |
3dcabaa8 | 1399 | |
0865b04a | 1400 | if (target_read_code (pc + 1, buf, pattern.len - 1)) |
a3fcb948 | 1401 | return 0; |
613e8135 | 1402 | |
a3fcb948 JG |
1403 | for (i = 1; i < pattern.len; i++) |
1404 | { | |
1405 | if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i]) | |
1406 | insn_matched = 0; | |
37bdc87e | 1407 | } |
a3fcb948 JG |
1408 | return insn_matched; |
1409 | } | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | /* Search for the instruction at PC in the list INSN_PATTERNS. Return | |
1414 | the first instruction description that matches. Otherwise, return | |
1415 | NULL. */ | |
1416 | ||
1417 | static struct i386_insn * | |
1418 | i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1419 | { | |
1420 | struct i386_insn *pattern; | |
1421 | ||
1422 | for (pattern = insn_patterns; pattern->len > 0; pattern++) | |
1423 | { | |
1424 | if (i386_match_pattern (pc, *pattern)) | |
1425 | return pattern; | |
37bdc87e MK |
1426 | } |
1427 | ||
1428 | return NULL; | |
1429 | } | |
1430 | ||
a3fcb948 JG |
1431 | /* Return whether PC points inside a sequence of instructions that |
1432 | matches INSN_PATTERNS. */ | |
1433 | ||
1434 | static int | |
1435 | i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns) | |
1436 | { | |
1437 | CORE_ADDR current_pc; | |
1438 | int ix, i; | |
a3fcb948 JG |
1439 | struct i386_insn *insn; |
1440 | ||
1441 | insn = i386_match_insn (pc, insn_patterns); | |
1442 | if (insn == NULL) | |
1443 | return 0; | |
1444 | ||
8bbdd3f4 | 1445 | current_pc = pc; |
a3fcb948 JG |
1446 | ix = insn - insn_patterns; |
1447 | for (i = ix - 1; i >= 0; i--) | |
1448 | { | |
8bbdd3f4 MK |
1449 | current_pc -= insn_patterns[i].len; |
1450 | ||
a3fcb948 JG |
1451 | if (!i386_match_pattern (current_pc, insn_patterns[i])) |
1452 | return 0; | |
a3fcb948 JG |
1453 | } |
1454 | ||
1455 | current_pc = pc + insn->len; | |
1456 | for (insn = insn_patterns + ix + 1; insn->len > 0; insn++) | |
1457 | { | |
1458 | if (!i386_match_pattern (current_pc, *insn)) | |
1459 | return 0; | |
1460 | ||
1461 | current_pc += insn->len; | |
1462 | } | |
1463 | ||
1464 | return 1; | |
1465 | } | |
1466 | ||
37bdc87e MK |
1467 | /* Some special instructions that might be migrated by GCC into the |
1468 | part of the prologue that sets up the new stack frame. Because the | |
1469 | stack frame hasn't been setup yet, no registers have been saved | |
1470 | yet, and only the scratch registers %eax, %ecx and %edx can be | |
1471 | touched. */ | |
1472 | ||
6bd434d6 | 1473 | static i386_insn i386_frame_setup_skip_insns[] = |
37bdc87e | 1474 | { |
1777feb0 | 1475 | /* Check for `movb imm8, r' and `movl imm32, r'. |
37bdc87e MK |
1476 | |
1477 | ??? Should we handle 16-bit operand-sizes here? */ | |
1478 | ||
1479 | /* `movb imm8, %al' and `movb imm8, %ah' */ | |
1480 | /* `movb imm8, %cl' and `movb imm8, %ch' */ | |
1481 | { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } }, | |
1482 | /* `movb imm8, %dl' and `movb imm8, %dh' */ | |
1483 | { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } }, | |
1484 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
1485 | { 5, { 0xb8 }, { 0xfe } }, | |
1486 | /* `movl imm32, %edx' */ | |
1487 | { 5, { 0xba }, { 0xff } }, | |
1488 | ||
1489 | /* Check for `mov imm32, r32'. Note that there is an alternative | |
1490 | encoding for `mov m32, %eax'. | |
1491 | ||
85102364 | 1492 | ??? Should we handle SIB addressing here? |
37bdc87e MK |
1493 | ??? Should we handle 16-bit operand-sizes here? */ |
1494 | ||
1495 | /* `movl m32, %eax' */ | |
1496 | { 5, { 0xa1 }, { 0xff } }, | |
1497 | /* `movl m32, %eax' and `mov; m32, %ecx' */ | |
1498 | { 6, { 0x89, 0x05 }, {0xff, 0xf7 } }, | |
1499 | /* `movl m32, %edx' */ | |
1500 | { 6, { 0x89, 0x15 }, {0xff, 0xff } }, | |
1501 | ||
1502 | /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'. | |
1503 | Because of the symmetry, there are actually two ways to encode | |
1504 | these instructions; opcode bytes 0x29 and 0x2b for `subl' and | |
1505 | opcode bytes 0x31 and 0x33 for `xorl'. */ | |
1506 | ||
1507 | /* `subl %eax, %eax' */ | |
1508 | { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } }, | |
1509 | /* `subl %ecx, %ecx' */ | |
1510 | { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } }, | |
1511 | /* `subl %edx, %edx' */ | |
1512 | { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } }, | |
1513 | /* `xorl %eax, %eax' */ | |
1514 | { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } }, | |
1515 | /* `xorl %ecx, %ecx' */ | |
1516 | { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } }, | |
1517 | /* `xorl %edx, %edx' */ | |
1518 | { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } }, | |
1519 | { 0 } | |
1520 | }; | |
1521 | ||
14f9473c VC |
1522 | /* Check whether PC points to an endbr32 instruction. */ |
1523 | static CORE_ADDR | |
1524 | i386_skip_endbr (CORE_ADDR pc) | |
1525 | { | |
1526 | static const gdb_byte endbr32[] = { 0xf3, 0x0f, 0x1e, 0xfb }; | |
1527 | ||
1528 | gdb_byte buf[sizeof (endbr32)]; | |
1529 | ||
1530 | /* Stop there if we can't read the code */ | |
1531 | if (target_read_code (pc, buf, sizeof (endbr32))) | |
1532 | return pc; | |
1533 | ||
1534 | /* If the instruction isn't an endbr32, stop */ | |
1535 | if (memcmp (buf, endbr32, sizeof (endbr32)) != 0) | |
1536 | return pc; | |
1537 | ||
1538 | return pc + sizeof (endbr32); | |
1539 | } | |
e11481da PM |
1540 | |
1541 | /* Check whether PC points to a no-op instruction. */ | |
1542 | static CORE_ADDR | |
1543 | i386_skip_noop (CORE_ADDR pc) | |
1544 | { | |
1545 | gdb_byte op; | |
1546 | int check = 1; | |
1547 | ||
0865b04a | 1548 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1549 | return pc; |
e11481da PM |
1550 | |
1551 | while (check) | |
1552 | { | |
1553 | check = 0; | |
1554 | /* Ignore `nop' instruction. */ | |
1555 | if (op == 0x90) | |
1556 | { | |
1557 | pc += 1; | |
0865b04a | 1558 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1559 | return pc; |
e11481da PM |
1560 | check = 1; |
1561 | } | |
1562 | /* Ignore no-op instruction `mov %edi, %edi'. | |
1563 | Microsoft system dlls often start with | |
1564 | a `mov %edi,%edi' instruction. | |
1565 | The 5 bytes before the function start are | |
1566 | filled with `nop' instructions. | |
1567 | This pattern can be used for hot-patching: | |
1568 | The `mov %edi, %edi' instruction can be replaced by a | |
1569 | near jump to the location of the 5 `nop' instructions | |
1570 | which can be replaced by a 32-bit jump to anywhere | |
1571 | in the 32-bit address space. */ | |
1572 | ||
1573 | else if (op == 0x8b) | |
1574 | { | |
0865b04a | 1575 | if (target_read_code (pc + 1, &op, 1)) |
3dcabaa8 MS |
1576 | return pc; |
1577 | ||
e11481da PM |
1578 | if (op == 0xff) |
1579 | { | |
1580 | pc += 2; | |
0865b04a | 1581 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 MS |
1582 | return pc; |
1583 | ||
e11481da PM |
1584 | check = 1; |
1585 | } | |
1586 | } | |
1587 | } | |
1588 | return pc; | |
1589 | } | |
1590 | ||
acd5c798 MK |
1591 | /* Check whether PC points at a code that sets up a new stack frame. |
1592 | If so, it updates CACHE and returns the address of the first | |
37bdc87e MK |
1593 | instruction after the sequence that sets up the frame or LIMIT, |
1594 | whichever is smaller. If we don't recognize the code, return PC. */ | |
acd5c798 MK |
1595 | |
1596 | static CORE_ADDR | |
e17a4113 UW |
1597 | i386_analyze_frame_setup (struct gdbarch *gdbarch, |
1598 | CORE_ADDR pc, CORE_ADDR limit, | |
acd5c798 MK |
1599 | struct i386_frame_cache *cache) |
1600 | { | |
e17a4113 | 1601 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
37bdc87e | 1602 | struct i386_insn *insn; |
63c0089f | 1603 | gdb_byte op; |
26604a34 | 1604 | int skip = 0; |
acd5c798 | 1605 | |
37bdc87e MK |
1606 | if (limit <= pc) |
1607 | return limit; | |
acd5c798 | 1608 | |
0865b04a | 1609 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1610 | return pc; |
acd5c798 | 1611 | |
c906108c | 1612 | if (op == 0x55) /* pushl %ebp */ |
c5aa993b | 1613 | { |
acd5c798 MK |
1614 | /* Take into account that we've executed the `pushl %ebp' that |
1615 | starts this instruction sequence. */ | |
fd13a04a | 1616 | cache->saved_regs[I386_EBP_REGNUM] = 0; |
acd5c798 | 1617 | cache->sp_offset += 4; |
37bdc87e | 1618 | pc++; |
acd5c798 MK |
1619 | |
1620 | /* If that's all, return now. */ | |
37bdc87e MK |
1621 | if (limit <= pc) |
1622 | return limit; | |
26604a34 | 1623 | |
b4632131 | 1624 | /* Check for some special instructions that might be migrated by |
37bdc87e MK |
1625 | GCC into the prologue and skip them. At this point in the |
1626 | prologue, code should only touch the scratch registers %eax, | |
30baf67b | 1627 | %ecx and %edx, so while the number of possibilities is sheer, |
37bdc87e | 1628 | it is limited. |
5daa5b4e | 1629 | |
26604a34 MK |
1630 | Make sure we only skip these instructions if we later see the |
1631 | `movl %esp, %ebp' that actually sets up the frame. */ | |
37bdc87e | 1632 | while (pc + skip < limit) |
26604a34 | 1633 | { |
37bdc87e MK |
1634 | insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns); |
1635 | if (insn == NULL) | |
1636 | break; | |
b4632131 | 1637 | |
37bdc87e | 1638 | skip += insn->len; |
26604a34 MK |
1639 | } |
1640 | ||
37bdc87e MK |
1641 | /* If that's all, return now. */ |
1642 | if (limit <= pc + skip) | |
1643 | return limit; | |
1644 | ||
0865b04a | 1645 | if (target_read_code (pc + skip, &op, 1)) |
3dcabaa8 | 1646 | return pc + skip; |
37bdc87e | 1647 | |
30f8135b YQ |
1648 | /* The i386 prologue looks like |
1649 | ||
1650 | push %ebp | |
1651 | mov %esp,%ebp | |
1652 | sub $0x10,%esp | |
1653 | ||
1654 | and a different prologue can be generated for atom. | |
1655 | ||
1656 | push %ebp | |
1657 | lea (%esp),%ebp | |
1658 | lea -0x10(%esp),%esp | |
1659 | ||
1660 | We handle both of them here. */ | |
1661 | ||
acd5c798 | 1662 | switch (op) |
c906108c | 1663 | { |
30f8135b | 1664 | /* Check for `movl %esp, %ebp' -- can be written in two ways. */ |
c906108c | 1665 | case 0x8b: |
0865b04a | 1666 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1667 | != 0xec) |
37bdc87e | 1668 | return pc; |
30f8135b | 1669 | pc += (skip + 2); |
c906108c SS |
1670 | break; |
1671 | case 0x89: | |
0865b04a | 1672 | if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order) |
e17a4113 | 1673 | != 0xe5) |
37bdc87e | 1674 | return pc; |
30f8135b YQ |
1675 | pc += (skip + 2); |
1676 | break; | |
1677 | case 0x8d: /* Check for 'lea (%ebp), %ebp'. */ | |
0865b04a | 1678 | if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order) |
30f8135b YQ |
1679 | != 0x242c) |
1680 | return pc; | |
1681 | pc += (skip + 3); | |
c906108c SS |
1682 | break; |
1683 | default: | |
37bdc87e | 1684 | return pc; |
c906108c | 1685 | } |
acd5c798 | 1686 | |
26604a34 MK |
1687 | /* OK, we actually have a frame. We just don't know how large |
1688 | it is yet. Set its size to zero. We'll adjust it if | |
1689 | necessary. We also now commit to skipping the special | |
1690 | instructions mentioned before. */ | |
acd5c798 MK |
1691 | cache->locals = 0; |
1692 | ||
1693 | /* If that's all, return now. */ | |
37bdc87e MK |
1694 | if (limit <= pc) |
1695 | return limit; | |
acd5c798 | 1696 | |
fc338970 MK |
1697 | /* Check for stack adjustment |
1698 | ||
acd5c798 | 1699 | subl $XXX, %esp |
30f8135b YQ |
1700 | or |
1701 | lea -XXX(%esp),%esp | |
fc338970 | 1702 | |
fd35795f | 1703 | NOTE: You can't subtract a 16-bit immediate from a 32-bit |
fc338970 | 1704 | reg, so we don't have to worry about a data16 prefix. */ |
0865b04a | 1705 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1706 | return pc; |
c906108c SS |
1707 | if (op == 0x83) |
1708 | { | |
fd35795f | 1709 | /* `subl' with 8-bit immediate. */ |
0865b04a | 1710 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1711 | /* Some instruction starting with 0x83 other than `subl'. */ |
37bdc87e | 1712 | return pc; |
acd5c798 | 1713 | |
37bdc87e MK |
1714 | /* `subl' with signed 8-bit immediate (though it wouldn't |
1715 | make sense to be negative). */ | |
0865b04a | 1716 | cache->locals = read_code_integer (pc + 2, 1, byte_order); |
37bdc87e | 1717 | return pc + 3; |
c906108c SS |
1718 | } |
1719 | else if (op == 0x81) | |
1720 | { | |
fd35795f | 1721 | /* Maybe it is `subl' with a 32-bit immediate. */ |
0865b04a | 1722 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec) |
fc338970 | 1723 | /* Some instruction starting with 0x81 other than `subl'. */ |
37bdc87e | 1724 | return pc; |
acd5c798 | 1725 | |
fd35795f | 1726 | /* It is `subl' with a 32-bit immediate. */ |
0865b04a | 1727 | cache->locals = read_code_integer (pc + 2, 4, byte_order); |
37bdc87e | 1728 | return pc + 6; |
c906108c | 1729 | } |
30f8135b YQ |
1730 | else if (op == 0x8d) |
1731 | { | |
1732 | /* The ModR/M byte is 0x64. */ | |
0865b04a | 1733 | if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64) |
30f8135b YQ |
1734 | return pc; |
1735 | /* 'lea' with 8-bit displacement. */ | |
0865b04a | 1736 | cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order); |
30f8135b YQ |
1737 | return pc + 4; |
1738 | } | |
c906108c SS |
1739 | else |
1740 | { | |
30f8135b | 1741 | /* Some instruction other than `subl' nor 'lea'. */ |
37bdc87e | 1742 | return pc; |
c906108c SS |
1743 | } |
1744 | } | |
37bdc87e | 1745 | else if (op == 0xc8) /* enter */ |
c906108c | 1746 | { |
0865b04a | 1747 | cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order); |
acd5c798 | 1748 | return pc + 4; |
c906108c | 1749 | } |
21d0e8a4 | 1750 | |
acd5c798 | 1751 | return pc; |
21d0e8a4 MK |
1752 | } |
1753 | ||
acd5c798 MK |
1754 | /* Check whether PC points at code that saves registers on the stack. |
1755 | If so, it updates CACHE and returns the address of the first | |
1756 | instruction after the register saves or CURRENT_PC, whichever is | |
1757 | smaller. Otherwise, return PC. */ | |
6bff26de MK |
1758 | |
1759 | static CORE_ADDR | |
acd5c798 MK |
1760 | i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc, |
1761 | struct i386_frame_cache *cache) | |
6bff26de | 1762 | { |
99ab4326 | 1763 | CORE_ADDR offset = 0; |
63c0089f | 1764 | gdb_byte op; |
99ab4326 | 1765 | int i; |
c0d1d883 | 1766 | |
99ab4326 MK |
1767 | if (cache->locals > 0) |
1768 | offset -= cache->locals; | |
1769 | for (i = 0; i < 8 && pc < current_pc; i++) | |
1770 | { | |
0865b04a | 1771 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1772 | return pc; |
99ab4326 MK |
1773 | if (op < 0x50 || op > 0x57) |
1774 | break; | |
0d17c81d | 1775 | |
99ab4326 MK |
1776 | offset -= 4; |
1777 | cache->saved_regs[op - 0x50] = offset; | |
1778 | cache->sp_offset += 4; | |
1779 | pc++; | |
6bff26de MK |
1780 | } |
1781 | ||
acd5c798 | 1782 | return pc; |
22797942 AC |
1783 | } |
1784 | ||
acd5c798 MK |
1785 | /* Do a full analysis of the prologue at PC and update CACHE |
1786 | accordingly. Bail out early if CURRENT_PC is reached. Return the | |
1787 | address where the analysis stopped. | |
ed84f6c1 | 1788 | |
fc338970 MK |
1789 | We handle these cases: |
1790 | ||
1791 | The startup sequence can be at the start of the function, or the | |
1792 | function can start with a branch to startup code at the end. | |
1793 | ||
1794 | %ebp can be set up with either the 'enter' instruction, or "pushl | |
1795 | %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was | |
1796 | once used in the System V compiler). | |
1797 | ||
1798 | Local space is allocated just below the saved %ebp by either the | |
fd35795f MK |
1799 | 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a |
1800 | 16-bit unsigned argument for space to allocate, and the 'addl' | |
1801 | instruction could have either a signed byte, or 32-bit immediate. | |
fc338970 MK |
1802 | |
1803 | Next, the registers used by this function are pushed. With the | |
1804 | System V compiler they will always be in the order: %edi, %esi, | |
1805 | %ebx (and sometimes a harmless bug causes it to also save but not | |
1806 | restore %eax); however, the code below is willing to see the pushes | |
1807 | in any order, and will handle up to 8 of them. | |
1808 | ||
1809 | If the setup sequence is at the end of the function, then the next | |
1810 | instruction will be a branch back to the start. */ | |
c906108c | 1811 | |
acd5c798 | 1812 | static CORE_ADDR |
e17a4113 UW |
1813 | i386_analyze_prologue (struct gdbarch *gdbarch, |
1814 | CORE_ADDR pc, CORE_ADDR current_pc, | |
acd5c798 | 1815 | struct i386_frame_cache *cache) |
c906108c | 1816 | { |
14f9473c | 1817 | pc = i386_skip_endbr (pc); |
e11481da | 1818 | pc = i386_skip_noop (pc); |
e17a4113 | 1819 | pc = i386_follow_jump (gdbarch, pc); |
acd5c798 MK |
1820 | pc = i386_analyze_struct_return (pc, current_pc, cache); |
1821 | pc = i386_skip_probe (pc); | |
92dd43fa | 1822 | pc = i386_analyze_stack_align (pc, current_pc, cache); |
e17a4113 | 1823 | pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache); |
acd5c798 | 1824 | return i386_analyze_register_saves (pc, current_pc, cache); |
c906108c SS |
1825 | } |
1826 | ||
fc338970 | 1827 | /* Return PC of first real instruction. */ |
c906108c | 1828 | |
3a1e71e3 | 1829 | static CORE_ADDR |
6093d2eb | 1830 | i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) |
c906108c | 1831 | { |
e17a4113 UW |
1832 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
1833 | ||
63c0089f | 1834 | static gdb_byte pic_pat[6] = |
acd5c798 MK |
1835 | { |
1836 | 0xe8, 0, 0, 0, 0, /* call 0x0 */ | |
1837 | 0x5b, /* popl %ebx */ | |
c5aa993b | 1838 | }; |
acd5c798 MK |
1839 | struct i386_frame_cache cache; |
1840 | CORE_ADDR pc; | |
63c0089f | 1841 | gdb_byte op; |
acd5c798 | 1842 | int i; |
56bf0743 | 1843 | CORE_ADDR func_addr; |
4e879fc2 | 1844 | |
56bf0743 KB |
1845 | if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL)) |
1846 | { | |
1847 | CORE_ADDR post_prologue_pc | |
1848 | = skip_prologue_using_sal (gdbarch, func_addr); | |
43f3e411 | 1849 | struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); |
56bf0743 | 1850 | |
c2fd7fae | 1851 | /* LLVM backend (Clang/Flang) always emits a line note before the |
16e311ab FW |
1852 | prologue and another one after. We trust clang and newer Intel |
1853 | compilers to emit usable line notes. */ | |
56bf0743 | 1854 | if (post_prologue_pc |
43f3e411 | 1855 | && (cust != NULL |
ab5f850e SM |
1856 | && cust->producer () != NULL |
1857 | && (producer_is_llvm (cust->producer ()) | |
1858 | || producer_is_icc_ge_19 (cust->producer ())))) | |
16e311ab | 1859 | return std::max (start_pc, post_prologue_pc); |
56bf0743 KB |
1860 | } |
1861 | ||
e0f33b1f | 1862 | cache.locals = -1; |
e17a4113 | 1863 | pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache); |
acd5c798 MK |
1864 | if (cache.locals < 0) |
1865 | return start_pc; | |
c5aa993b | 1866 | |
acd5c798 | 1867 | /* Found valid frame setup. */ |
c906108c | 1868 | |
fc338970 MK |
1869 | /* The native cc on SVR4 in -K PIC mode inserts the following code |
1870 | to get the address of the global offset table (GOT) into register | |
acd5c798 MK |
1871 | %ebx: |
1872 | ||
dda83cd7 | 1873 | call 0x0 |
fc338970 | 1874 | popl %ebx |
dda83cd7 SM |
1875 | movl %ebx,x(%ebp) (optional) |
1876 | addl y,%ebx | |
fc338970 | 1877 | |
c906108c SS |
1878 | This code is with the rest of the prologue (at the end of the |
1879 | function), so we have to skip it to get to the first real | |
1880 | instruction at the start of the function. */ | |
c5aa993b | 1881 | |
c906108c SS |
1882 | for (i = 0; i < 6; i++) |
1883 | { | |
0865b04a | 1884 | if (target_read_code (pc + i, &op, 1)) |
3dcabaa8 MS |
1885 | return pc; |
1886 | ||
c5aa993b | 1887 | if (pic_pat[i] != op) |
c906108c SS |
1888 | break; |
1889 | } | |
1890 | if (i == 6) | |
1891 | { | |
acd5c798 MK |
1892 | int delta = 6; |
1893 | ||
0865b04a | 1894 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1895 | return pc; |
c906108c | 1896 | |
c5aa993b | 1897 | if (op == 0x89) /* movl %ebx, x(%ebp) */ |
c906108c | 1898 | { |
0865b04a | 1899 | op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order); |
acd5c798 | 1900 | |
fc338970 | 1901 | if (op == 0x5d) /* One byte offset from %ebp. */ |
acd5c798 | 1902 | delta += 3; |
fc338970 | 1903 | else if (op == 0x9d) /* Four byte offset from %ebp. */ |
acd5c798 | 1904 | delta += 6; |
fc338970 | 1905 | else /* Unexpected instruction. */ |
acd5c798 MK |
1906 | delta = 0; |
1907 | ||
dda83cd7 | 1908 | if (target_read_code (pc + delta, &op, 1)) |
3dcabaa8 | 1909 | return pc; |
c906108c | 1910 | } |
acd5c798 | 1911 | |
c5aa993b | 1912 | /* addl y,%ebx */ |
acd5c798 | 1913 | if (delta > 0 && op == 0x81 |
0865b04a | 1914 | && read_code_unsigned_integer (pc + delta + 1, 1, byte_order) |
e17a4113 | 1915 | == 0xc3) |
c906108c | 1916 | { |
acd5c798 | 1917 | pc += delta + 6; |
c906108c SS |
1918 | } |
1919 | } | |
c5aa993b | 1920 | |
e63bbc88 MK |
1921 | /* If the function starts with a branch (to startup code at the end) |
1922 | the last instruction should bring us back to the first | |
1923 | instruction of the real code. */ | |
e17a4113 UW |
1924 | if (i386_follow_jump (gdbarch, start_pc) != start_pc) |
1925 | pc = i386_follow_jump (gdbarch, pc); | |
e63bbc88 MK |
1926 | |
1927 | return pc; | |
c906108c SS |
1928 | } |
1929 | ||
4309257c PM |
1930 | /* Check that the code pointed to by PC corresponds to a call to |
1931 | __main, skip it if so. Return PC otherwise. */ | |
1932 | ||
1933 | CORE_ADDR | |
1934 | i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
1935 | { | |
e17a4113 | 1936 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4309257c PM |
1937 | gdb_byte op; |
1938 | ||
0865b04a | 1939 | if (target_read_code (pc, &op, 1)) |
3dcabaa8 | 1940 | return pc; |
4309257c PM |
1941 | if (op == 0xe8) |
1942 | { | |
1943 | gdb_byte buf[4]; | |
1944 | ||
0865b04a | 1945 | if (target_read_code (pc + 1, buf, sizeof buf) == 0) |
24b21115 | 1946 | { |
4309257c PM |
1947 | /* Make sure address is computed correctly as a 32bit |
1948 | integer even if CORE_ADDR is 64 bit wide. */ | |
24b21115 SM |
1949 | struct bound_minimal_symbol s; |
1950 | CORE_ADDR call_dest; | |
4309257c | 1951 | |
e17a4113 | 1952 | call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order); |
4309257c | 1953 | call_dest = call_dest & 0xffffffffU; |
24b21115 SM |
1954 | s = lookup_minimal_symbol_by_pc (call_dest); |
1955 | if (s.minsym != NULL | |
1956 | && s.minsym->linkage_name () != NULL | |
1957 | && strcmp (s.minsym->linkage_name (), "__main") == 0) | |
1958 | pc += 5; | |
1959 | } | |
4309257c PM |
1960 | } |
1961 | ||
1962 | return pc; | |
1963 | } | |
1964 | ||
acd5c798 | 1965 | /* This function is 64-bit safe. */ |
93924b6b | 1966 | |
acd5c798 | 1967 | static CORE_ADDR |
bd2b40ac | 1968 | i386_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) |
93924b6b | 1969 | { |
63c0089f | 1970 | gdb_byte buf[8]; |
acd5c798 | 1971 | |
875f8d0e | 1972 | frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf); |
0dfff4cb | 1973 | return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr); |
93924b6b | 1974 | } |
acd5c798 | 1975 | \f |
93924b6b | 1976 | |
acd5c798 | 1977 | /* Normal frames. */ |
c5aa993b | 1978 | |
8fbca658 | 1979 | static void |
bd2b40ac | 1980 | i386_frame_cache_1 (frame_info_ptr this_frame, |
8fbca658 | 1981 | struct i386_frame_cache *cache) |
a7769679 | 1982 | { |
e17a4113 UW |
1983 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1984 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 1985 | gdb_byte buf[4]; |
acd5c798 MK |
1986 | int i; |
1987 | ||
8fbca658 | 1988 | cache->pc = get_frame_func (this_frame); |
acd5c798 MK |
1989 | |
1990 | /* In principle, for normal frames, %ebp holds the frame pointer, | |
1991 | which holds the base address for the current stack frame. | |
1992 | However, for functions that don't need it, the frame pointer is | |
1993 | optional. For these "frameless" functions the frame pointer is | |
1994 | actually the frame pointer of the calling frame. Signal | |
1995 | trampolines are just a special case of a "frameless" function. | |
1996 | They (usually) share their frame pointer with the frame that was | |
1997 | in progress when the signal occurred. */ | |
1998 | ||
10458914 | 1999 | get_frame_register (this_frame, I386_EBP_REGNUM, buf); |
e17a4113 | 2000 | cache->base = extract_unsigned_integer (buf, 4, byte_order); |
acd5c798 | 2001 | if (cache->base == 0) |
620fa63a PA |
2002 | { |
2003 | cache->base_p = 1; | |
2004 | return; | |
2005 | } | |
acd5c798 MK |
2006 | |
2007 | /* For normal frames, %eip is stored at 4(%ebp). */ | |
fd13a04a | 2008 | cache->saved_regs[I386_EIP_REGNUM] = 4; |
acd5c798 | 2009 | |
acd5c798 | 2010 | if (cache->pc != 0) |
e17a4113 UW |
2011 | i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame), |
2012 | cache); | |
acd5c798 MK |
2013 | |
2014 | if (cache->locals < 0) | |
2015 | { | |
2016 | /* We didn't find a valid frame, which means that CACHE->base | |
2017 | currently holds the frame pointer for our calling frame. If | |
2018 | we're at the start of a function, or somewhere half-way its | |
2019 | prologue, the function's frame probably hasn't been fully | |
2020 | setup yet. Try to reconstruct the base address for the stack | |
2021 | frame by looking at the stack pointer. For truly "frameless" | |
2022 | functions this might work too. */ | |
2023 | ||
e0c62198 | 2024 | if (cache->saved_sp_reg != -1) |
92dd43fa | 2025 | { |
8fbca658 PA |
2026 | /* Saved stack pointer has been saved. */ |
2027 | get_frame_register (this_frame, cache->saved_sp_reg, buf); | |
2028 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); | |
2029 | ||
92dd43fa MK |
2030 | /* We're halfway aligning the stack. */ |
2031 | cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4; | |
2032 | cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4; | |
2033 | ||
2034 | /* This will be added back below. */ | |
2035 | cache->saved_regs[I386_EIP_REGNUM] -= cache->base; | |
2036 | } | |
7618e12b | 2037 | else if (cache->pc != 0 |
0865b04a | 2038 | || target_read_code (get_frame_pc (this_frame), buf, 1)) |
92dd43fa | 2039 | { |
7618e12b DJ |
2040 | /* We're in a known function, but did not find a frame |
2041 | setup. Assume that the function does not use %ebp. | |
2042 | Alternatively, we may have jumped to an invalid | |
2043 | address; in that case there is definitely no new | |
2044 | frame in %ebp. */ | |
10458914 | 2045 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 UW |
2046 | cache->base = extract_unsigned_integer (buf, 4, byte_order) |
2047 | + cache->sp_offset; | |
92dd43fa | 2048 | } |
7618e12b DJ |
2049 | else |
2050 | /* We're in an unknown function. We could not find the start | |
2051 | of the function to analyze the prologue; our best option is | |
2052 | to assume a typical frame layout with the caller's %ebp | |
2053 | saved. */ | |
2054 | cache->saved_regs[I386_EBP_REGNUM] = 0; | |
acd5c798 MK |
2055 | } |
2056 | ||
8fbca658 PA |
2057 | if (cache->saved_sp_reg != -1) |
2058 | { | |
2059 | /* Saved stack pointer has been saved (but the SAVED_SP_REG | |
2060 | register may be unavailable). */ | |
2061 | if (cache->saved_sp == 0 | |
ca9d61b9 JB |
2062 | && deprecated_frame_register_read (this_frame, |
2063 | cache->saved_sp_reg, buf)) | |
8fbca658 PA |
2064 | cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order); |
2065 | } | |
acd5c798 MK |
2066 | /* Now that we have the base address for the stack frame we can |
2067 | calculate the value of %esp in the calling frame. */ | |
8fbca658 | 2068 | else if (cache->saved_sp == 0) |
92dd43fa | 2069 | cache->saved_sp = cache->base + 8; |
a7769679 | 2070 | |
acd5c798 MK |
2071 | /* Adjust all the saved registers such that they contain addresses |
2072 | instead of offsets. */ | |
2073 | for (i = 0; i < I386_NUM_SAVED_REGS; i++) | |
fd13a04a AC |
2074 | if (cache->saved_regs[i] != -1) |
2075 | cache->saved_regs[i] += cache->base; | |
acd5c798 | 2076 | |
8fbca658 PA |
2077 | cache->base_p = 1; |
2078 | } | |
2079 | ||
2080 | static struct i386_frame_cache * | |
bd2b40ac | 2081 | i386_frame_cache (frame_info_ptr this_frame, void **this_cache) |
8fbca658 | 2082 | { |
8fbca658 PA |
2083 | struct i386_frame_cache *cache; |
2084 | ||
2085 | if (*this_cache) | |
9a3c8263 | 2086 | return (struct i386_frame_cache *) *this_cache; |
8fbca658 PA |
2087 | |
2088 | cache = i386_alloc_frame_cache (); | |
2089 | *this_cache = cache; | |
2090 | ||
a70b8144 | 2091 | try |
8fbca658 PA |
2092 | { |
2093 | i386_frame_cache_1 (this_frame, cache); | |
2094 | } | |
230d2906 | 2095 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2096 | { |
2097 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2098 | throw; |
7556d4a4 | 2099 | } |
8fbca658 | 2100 | |
acd5c798 | 2101 | return cache; |
a7769679 MK |
2102 | } |
2103 | ||
3a1e71e3 | 2104 | static void |
bd2b40ac | 2105 | i386_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
acd5c798 | 2106 | struct frame_id *this_id) |
c906108c | 2107 | { |
10458914 | 2108 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 | 2109 | |
5ce0145d PA |
2110 | if (!cache->base_p) |
2111 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); | |
2112 | else if (cache->base == 0) | |
2113 | { | |
2114 | /* This marks the outermost frame. */ | |
2115 | } | |
2116 | else | |
2117 | { | |
2118 | /* See the end of i386_push_dummy_call. */ | |
2119 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
2120 | } | |
acd5c798 MK |
2121 | } |
2122 | ||
8fbca658 | 2123 | static enum unwind_stop_reason |
bd2b40ac | 2124 | i386_frame_unwind_stop_reason (frame_info_ptr this_frame, |
8fbca658 PA |
2125 | void **this_cache) |
2126 | { | |
2127 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); | |
2128 | ||
2129 | if (!cache->base_p) | |
2130 | return UNWIND_UNAVAILABLE; | |
2131 | ||
2132 | /* This marks the outermost frame. */ | |
2133 | if (cache->base == 0) | |
2134 | return UNWIND_OUTERMOST; | |
2135 | ||
2136 | return UNWIND_NO_REASON; | |
2137 | } | |
2138 | ||
10458914 | 2139 | static struct value * |
bd2b40ac | 2140 | i386_frame_prev_register (frame_info_ptr this_frame, void **this_cache, |
10458914 | 2141 | int regnum) |
acd5c798 | 2142 | { |
10458914 | 2143 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2144 | |
2145 | gdb_assert (regnum >= 0); | |
2146 | ||
2147 | /* The System V ABI says that: | |
2148 | ||
2149 | "The flags register contains the system flags, such as the | |
2150 | direction flag and the carry flag. The direction flag must be | |
2151 | set to the forward (that is, zero) direction before entry and | |
2152 | upon exit from a function. Other user flags have no specified | |
2153 | role in the standard calling sequence and are not preserved." | |
2154 | ||
2155 | To guarantee the "upon exit" part of that statement we fake a | |
2156 | saved flags register that has its direction flag cleared. | |
2157 | ||
2158 | Note that GCC doesn't seem to rely on the fact that the direction | |
2159 | flag is cleared after a function return; it always explicitly | |
2160 | clears the flag before operations where it matters. | |
2161 | ||
2162 | FIXME: kettenis/20030316: I'm not quite sure whether this is the | |
2163 | right thing to do. The way we fake the flags register here makes | |
2164 | it impossible to change it. */ | |
2165 | ||
2166 | if (regnum == I386_EFLAGS_REGNUM) | |
2167 | { | |
10458914 | 2168 | ULONGEST val; |
c5aa993b | 2169 | |
10458914 DJ |
2170 | val = get_frame_register_unsigned (this_frame, regnum); |
2171 | val &= ~(1 << 10); | |
2172 | return frame_unwind_got_constant (this_frame, regnum, val); | |
acd5c798 | 2173 | } |
1211c4e4 | 2174 | |
acd5c798 | 2175 | if (regnum == I386_EIP_REGNUM && cache->pc_in_eax) |
10458914 | 2176 | return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM); |
acd5c798 | 2177 | |
fcf250e2 UW |
2178 | if (regnum == I386_ESP_REGNUM |
2179 | && (cache->saved_sp != 0 || cache->saved_sp_reg != -1)) | |
8fbca658 PA |
2180 | { |
2181 | /* If the SP has been saved, but we don't know where, then this | |
2182 | means that SAVED_SP_REG register was found unavailable back | |
2183 | when we built the cache. */ | |
fcf250e2 | 2184 | if (cache->saved_sp == 0) |
8fbca658 PA |
2185 | return frame_unwind_got_register (this_frame, regnum, |
2186 | cache->saved_sp_reg); | |
2187 | else | |
2188 | return frame_unwind_got_constant (this_frame, regnum, | |
2189 | cache->saved_sp); | |
2190 | } | |
acd5c798 | 2191 | |
fd13a04a | 2192 | if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) |
10458914 DJ |
2193 | return frame_unwind_got_memory (this_frame, regnum, |
2194 | cache->saved_regs[regnum]); | |
fd13a04a | 2195 | |
10458914 | 2196 | return frame_unwind_got_register (this_frame, regnum, regnum); |
acd5c798 MK |
2197 | } |
2198 | ||
2199 | static const struct frame_unwind i386_frame_unwind = | |
2200 | { | |
a154d838 | 2201 | "i386 prologue", |
acd5c798 | 2202 | NORMAL_FRAME, |
8fbca658 | 2203 | i386_frame_unwind_stop_reason, |
acd5c798 | 2204 | i386_frame_this_id, |
10458914 DJ |
2205 | i386_frame_prev_register, |
2206 | NULL, | |
2207 | default_frame_sniffer | |
acd5c798 | 2208 | }; |
06da04c6 MS |
2209 | |
2210 | /* Normal frames, but in a function epilogue. */ | |
2211 | ||
c9cf6e20 MG |
2212 | /* Implement the stack_frame_destroyed_p gdbarch method. |
2213 | ||
2214 | The epilogue is defined here as the 'ret' instruction, which will | |
06da04c6 MS |
2215 | follow any instruction such as 'leave' or 'pop %ebp' that destroys |
2216 | the function's stack frame. */ | |
2217 | ||
2218 | static int | |
c9cf6e20 | 2219 | i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) |
06da04c6 MS |
2220 | { |
2221 | gdb_byte insn; | |
e0d00bc7 | 2222 | |
cb911672 | 2223 | if (compunit_epilogue_unwind_valid (find_pc_compunit_symtab (pc))) |
e0d00bc7 | 2224 | return 0; |
06da04c6 MS |
2225 | |
2226 | if (target_read_memory (pc, &insn, 1)) | |
2227 | return 0; /* Can't read memory at pc. */ | |
2228 | ||
2229 | if (insn != 0xc3) /* 'ret' instruction. */ | |
2230 | return 0; | |
2231 | ||
2232 | return 1; | |
2233 | } | |
2234 | ||
2235 | static int | |
2236 | i386_epilogue_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 2237 | frame_info_ptr this_frame, |
06da04c6 MS |
2238 | void **this_prologue_cache) |
2239 | { | |
2240 | if (frame_relative_level (this_frame) == 0) | |
c9cf6e20 MG |
2241 | return i386_stack_frame_destroyed_p (get_frame_arch (this_frame), |
2242 | get_frame_pc (this_frame)); | |
06da04c6 MS |
2243 | else |
2244 | return 0; | |
2245 | } | |
2246 | ||
2247 | static struct i386_frame_cache * | |
bd2b40ac | 2248 | i386_epilogue_frame_cache (frame_info_ptr this_frame, void **this_cache) |
06da04c6 | 2249 | { |
06da04c6 | 2250 | struct i386_frame_cache *cache; |
0d6c2135 | 2251 | CORE_ADDR sp; |
06da04c6 MS |
2252 | |
2253 | if (*this_cache) | |
9a3c8263 | 2254 | return (struct i386_frame_cache *) *this_cache; |
06da04c6 MS |
2255 | |
2256 | cache = i386_alloc_frame_cache (); | |
2257 | *this_cache = cache; | |
2258 | ||
a70b8144 | 2259 | try |
8fbca658 | 2260 | { |
0d6c2135 | 2261 | cache->pc = get_frame_func (this_frame); |
06da04c6 | 2262 | |
0d6c2135 MK |
2263 | /* At this point the stack looks as if we just entered the |
2264 | function, with the return address at the top of the | |
2265 | stack. */ | |
2266 | sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM); | |
2267 | cache->base = sp + cache->sp_offset; | |
8fbca658 | 2268 | cache->saved_sp = cache->base + 8; |
8fbca658 | 2269 | cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4; |
06da04c6 | 2270 | |
8fbca658 PA |
2271 | cache->base_p = 1; |
2272 | } | |
230d2906 | 2273 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2274 | { |
2275 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2276 | throw; |
7556d4a4 | 2277 | } |
06da04c6 MS |
2278 | |
2279 | return cache; | |
2280 | } | |
2281 | ||
8fbca658 | 2282 | static enum unwind_stop_reason |
bd2b40ac | 2283 | i386_epilogue_frame_unwind_stop_reason (frame_info_ptr this_frame, |
8fbca658 PA |
2284 | void **this_cache) |
2285 | { | |
0d6c2135 MK |
2286 | struct i386_frame_cache *cache = |
2287 | i386_epilogue_frame_cache (this_frame, this_cache); | |
8fbca658 PA |
2288 | |
2289 | if (!cache->base_p) | |
2290 | return UNWIND_UNAVAILABLE; | |
2291 | ||
2292 | return UNWIND_NO_REASON; | |
2293 | } | |
2294 | ||
06da04c6 | 2295 | static void |
bd2b40ac | 2296 | i386_epilogue_frame_this_id (frame_info_ptr this_frame, |
06da04c6 MS |
2297 | void **this_cache, |
2298 | struct frame_id *this_id) | |
2299 | { | |
0d6c2135 MK |
2300 | struct i386_frame_cache *cache = |
2301 | i386_epilogue_frame_cache (this_frame, this_cache); | |
06da04c6 | 2302 | |
8fbca658 | 2303 | if (!cache->base_p) |
5ce0145d PA |
2304 | (*this_id) = frame_id_build_unavailable_stack (cache->pc); |
2305 | else | |
2306 | (*this_id) = frame_id_build (cache->base + 8, cache->pc); | |
06da04c6 MS |
2307 | } |
2308 | ||
0d6c2135 | 2309 | static struct value * |
bd2b40ac | 2310 | i386_epilogue_frame_prev_register (frame_info_ptr this_frame, |
0d6c2135 MK |
2311 | void **this_cache, int regnum) |
2312 | { | |
2313 | /* Make sure we've initialized the cache. */ | |
2314 | i386_epilogue_frame_cache (this_frame, this_cache); | |
2315 | ||
2316 | return i386_frame_prev_register (this_frame, this_cache, regnum); | |
2317 | } | |
2318 | ||
06da04c6 MS |
2319 | static const struct frame_unwind i386_epilogue_frame_unwind = |
2320 | { | |
a154d838 | 2321 | "i386 epilogue", |
06da04c6 | 2322 | NORMAL_FRAME, |
8fbca658 | 2323 | i386_epilogue_frame_unwind_stop_reason, |
06da04c6 | 2324 | i386_epilogue_frame_this_id, |
0d6c2135 | 2325 | i386_epilogue_frame_prev_register, |
06da04c6 MS |
2326 | NULL, |
2327 | i386_epilogue_frame_sniffer | |
2328 | }; | |
acd5c798 MK |
2329 | \f |
2330 | ||
a3fcb948 JG |
2331 | /* Stack-based trampolines. */ |
2332 | ||
2333 | /* These trampolines are used on cross x86 targets, when taking the | |
2334 | address of a nested function. When executing these trampolines, | |
2335 | no stack frame is set up, so we are in a similar situation as in | |
2336 | epilogues and i386_epilogue_frame_this_id can be re-used. */ | |
2337 | ||
2338 | /* Static chain passed in register. */ | |
2339 | ||
6bd434d6 | 2340 | static i386_insn i386_tramp_chain_in_reg_insns[] = |
a3fcb948 JG |
2341 | { |
2342 | /* `movl imm32, %eax' and `movl imm32, %ecx' */ | |
2343 | { 5, { 0xb8 }, { 0xfe } }, | |
2344 | ||
2345 | /* `jmp imm32' */ | |
2346 | { 5, { 0xe9 }, { 0xff } }, | |
2347 | ||
2348 | {0} | |
2349 | }; | |
2350 | ||
2351 | /* Static chain passed on stack (when regparm=3). */ | |
2352 | ||
6bd434d6 | 2353 | static i386_insn i386_tramp_chain_on_stack_insns[] = |
a3fcb948 JG |
2354 | { |
2355 | /* `push imm32' */ | |
2356 | { 5, { 0x68 }, { 0xff } }, | |
2357 | ||
2358 | /* `jmp imm32' */ | |
2359 | { 5, { 0xe9 }, { 0xff } }, | |
2360 | ||
2361 | {0} | |
2362 | }; | |
2363 | ||
2364 | /* Return whether PC points inside a stack trampoline. */ | |
2365 | ||
2366 | static int | |
6df81a63 | 2367 | i386_in_stack_tramp_p (CORE_ADDR pc) |
a3fcb948 JG |
2368 | { |
2369 | gdb_byte insn; | |
2c02bd72 | 2370 | const char *name; |
a3fcb948 JG |
2371 | |
2372 | /* A stack trampoline is detected if no name is associated | |
2373 | to the current pc and if it points inside a trampoline | |
2374 | sequence. */ | |
2375 | ||
2376 | find_pc_partial_function (pc, &name, NULL, NULL); | |
2377 | if (name) | |
2378 | return 0; | |
2379 | ||
2380 | if (target_read_memory (pc, &insn, 1)) | |
2381 | return 0; | |
2382 | ||
2383 | if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns) | |
2384 | && !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns)) | |
2385 | return 0; | |
2386 | ||
2387 | return 1; | |
2388 | } | |
2389 | ||
2390 | static int | |
2391 | i386_stack_tramp_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 2392 | frame_info_ptr this_frame, |
0d6c2135 | 2393 | void **this_cache) |
a3fcb948 JG |
2394 | { |
2395 | if (frame_relative_level (this_frame) == 0) | |
6df81a63 | 2396 | return i386_in_stack_tramp_p (get_frame_pc (this_frame)); |
a3fcb948 JG |
2397 | else |
2398 | return 0; | |
2399 | } | |
2400 | ||
2401 | static const struct frame_unwind i386_stack_tramp_frame_unwind = | |
2402 | { | |
a154d838 | 2403 | "i386 stack tramp", |
a3fcb948 JG |
2404 | NORMAL_FRAME, |
2405 | i386_epilogue_frame_unwind_stop_reason, | |
2406 | i386_epilogue_frame_this_id, | |
0d6c2135 | 2407 | i386_epilogue_frame_prev_register, |
a3fcb948 JG |
2408 | NULL, |
2409 | i386_stack_tramp_frame_sniffer | |
2410 | }; | |
2411 | \f | |
6710bf39 SS |
2412 | /* Generate a bytecode expression to get the value of the saved PC. */ |
2413 | ||
2414 | static void | |
2415 | i386_gen_return_address (struct gdbarch *gdbarch, | |
2416 | struct agent_expr *ax, struct axs_value *value, | |
2417 | CORE_ADDR scope) | |
2418 | { | |
2419 | /* The following sequence assumes the traditional use of the base | |
2420 | register. */ | |
2421 | ax_reg (ax, I386_EBP_REGNUM); | |
2422 | ax_const_l (ax, 4); | |
2423 | ax_simple (ax, aop_add); | |
2424 | value->type = register_type (gdbarch, I386_EIP_REGNUM); | |
2425 | value->kind = axs_lvalue_memory; | |
2426 | } | |
2427 | \f | |
a3fcb948 | 2428 | |
acd5c798 MK |
2429 | /* Signal trampolines. */ |
2430 | ||
2431 | static struct i386_frame_cache * | |
bd2b40ac | 2432 | i386_sigtramp_frame_cache (frame_info_ptr this_frame, void **this_cache) |
acd5c798 | 2433 | { |
e17a4113 | 2434 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
08106042 | 2435 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
e17a4113 | 2436 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
acd5c798 | 2437 | struct i386_frame_cache *cache; |
acd5c798 | 2438 | CORE_ADDR addr; |
63c0089f | 2439 | gdb_byte buf[4]; |
acd5c798 MK |
2440 | |
2441 | if (*this_cache) | |
9a3c8263 | 2442 | return (struct i386_frame_cache *) *this_cache; |
acd5c798 | 2443 | |
fd13a04a | 2444 | cache = i386_alloc_frame_cache (); |
acd5c798 | 2445 | |
a70b8144 | 2446 | try |
a3386186 | 2447 | { |
8fbca658 PA |
2448 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
2449 | cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4; | |
a3386186 | 2450 | |
8fbca658 PA |
2451 | addr = tdep->sigcontext_addr (this_frame); |
2452 | if (tdep->sc_reg_offset) | |
2453 | { | |
2454 | int i; | |
a3386186 | 2455 | |
8fbca658 PA |
2456 | gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS); |
2457 | ||
2458 | for (i = 0; i < tdep->sc_num_regs; i++) | |
2459 | if (tdep->sc_reg_offset[i] != -1) | |
2460 | cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; | |
2461 | } | |
2462 | else | |
2463 | { | |
2464 | cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset; | |
2465 | cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset; | |
2466 | } | |
2467 | ||
2468 | cache->base_p = 1; | |
a3386186 | 2469 | } |
230d2906 | 2470 | catch (const gdb_exception_error &ex) |
7556d4a4 PA |
2471 | { |
2472 | if (ex.error != NOT_AVAILABLE_ERROR) | |
eedc3f4f | 2473 | throw; |
7556d4a4 | 2474 | } |
acd5c798 MK |
2475 | |
2476 | *this_cache = cache; | |
2477 | return cache; | |
2478 | } | |
2479 | ||
8fbca658 | 2480 | static enum unwind_stop_reason |
bd2b40ac | 2481 | i386_sigtramp_frame_unwind_stop_reason (frame_info_ptr this_frame, |
8fbca658 PA |
2482 | void **this_cache) |
2483 | { | |
2484 | struct i386_frame_cache *cache = | |
2485 | i386_sigtramp_frame_cache (this_frame, this_cache); | |
2486 | ||
2487 | if (!cache->base_p) | |
2488 | return UNWIND_UNAVAILABLE; | |
2489 | ||
2490 | return UNWIND_NO_REASON; | |
2491 | } | |
2492 | ||
acd5c798 | 2493 | static void |
bd2b40ac | 2494 | i386_sigtramp_frame_this_id (frame_info_ptr this_frame, void **this_cache, |
acd5c798 MK |
2495 | struct frame_id *this_id) |
2496 | { | |
2497 | struct i386_frame_cache *cache = | |
10458914 | 2498 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2499 | |
8fbca658 | 2500 | if (!cache->base_p) |
5ce0145d PA |
2501 | (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); |
2502 | else | |
2503 | { | |
2504 | /* See the end of i386_push_dummy_call. */ | |
2505 | (*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame)); | |
2506 | } | |
acd5c798 MK |
2507 | } |
2508 | ||
10458914 | 2509 | static struct value * |
bd2b40ac | 2510 | i386_sigtramp_frame_prev_register (frame_info_ptr this_frame, |
10458914 | 2511 | void **this_cache, int regnum) |
acd5c798 MK |
2512 | { |
2513 | /* Make sure we've initialized the cache. */ | |
10458914 | 2514 | i386_sigtramp_frame_cache (this_frame, this_cache); |
acd5c798 | 2515 | |
10458914 | 2516 | return i386_frame_prev_register (this_frame, this_cache, regnum); |
c906108c | 2517 | } |
c0d1d883 | 2518 | |
10458914 DJ |
2519 | static int |
2520 | i386_sigtramp_frame_sniffer (const struct frame_unwind *self, | |
bd2b40ac | 2521 | frame_info_ptr this_frame, |
10458914 | 2522 | void **this_prologue_cache) |
acd5c798 | 2523 | { |
345bd07c | 2524 | gdbarch *arch = get_frame_arch (this_frame); |
08106042 | 2525 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
acd5c798 | 2526 | |
911bc6ee MK |
2527 | /* We shouldn't even bother if we don't have a sigcontext_addr |
2528 | handler. */ | |
2529 | if (tdep->sigcontext_addr == NULL) | |
10458914 | 2530 | return 0; |
1c3545ae | 2531 | |
911bc6ee MK |
2532 | if (tdep->sigtramp_p != NULL) |
2533 | { | |
10458914 DJ |
2534 | if (tdep->sigtramp_p (this_frame)) |
2535 | return 1; | |
911bc6ee MK |
2536 | } |
2537 | ||
2538 | if (tdep->sigtramp_start != 0) | |
2539 | { | |
10458914 | 2540 | CORE_ADDR pc = get_frame_pc (this_frame); |
911bc6ee MK |
2541 | |
2542 | gdb_assert (tdep->sigtramp_end != 0); | |
2543 | if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) | |
10458914 | 2544 | return 1; |
911bc6ee | 2545 | } |
acd5c798 | 2546 | |
10458914 | 2547 | return 0; |
acd5c798 | 2548 | } |
10458914 DJ |
2549 | |
2550 | static const struct frame_unwind i386_sigtramp_frame_unwind = | |
2551 | { | |
a154d838 | 2552 | "i386 sigtramp", |
10458914 | 2553 | SIGTRAMP_FRAME, |
8fbca658 | 2554 | i386_sigtramp_frame_unwind_stop_reason, |
10458914 DJ |
2555 | i386_sigtramp_frame_this_id, |
2556 | i386_sigtramp_frame_prev_register, | |
2557 | NULL, | |
2558 | i386_sigtramp_frame_sniffer | |
2559 | }; | |
acd5c798 MK |
2560 | \f |
2561 | ||
2562 | static CORE_ADDR | |
bd2b40ac | 2563 | i386_frame_base_address (frame_info_ptr this_frame, void **this_cache) |
acd5c798 | 2564 | { |
10458914 | 2565 | struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache); |
acd5c798 MK |
2566 | |
2567 | return cache->base; | |
2568 | } | |
2569 | ||
2570 | static const struct frame_base i386_frame_base = | |
2571 | { | |
2572 | &i386_frame_unwind, | |
2573 | i386_frame_base_address, | |
2574 | i386_frame_base_address, | |
2575 | i386_frame_base_address | |
2576 | }; | |
2577 | ||
acd5c798 | 2578 | static struct frame_id |
bd2b40ac | 2579 | i386_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) |
acd5c798 | 2580 | { |
acd5c798 MK |
2581 | CORE_ADDR fp; |
2582 | ||
10458914 | 2583 | fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM); |
acd5c798 | 2584 | |
3e210248 | 2585 | /* See the end of i386_push_dummy_call. */ |
10458914 | 2586 | return frame_id_build (fp + 8, get_frame_pc (this_frame)); |
c0d1d883 | 2587 | } |
e04e5beb JM |
2588 | |
2589 | /* _Decimal128 function return values need 16-byte alignment on the | |
2590 | stack. */ | |
2591 | ||
2592 | static CORE_ADDR | |
2593 | i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
2594 | { | |
2595 | return sp & -(CORE_ADDR)16; | |
2596 | } | |
fc338970 | 2597 | \f |
c906108c | 2598 | |
fc338970 MK |
2599 | /* Figure out where the longjmp will land. Slurp the args out of the |
2600 | stack. We expect the first arg to be a pointer to the jmp_buf | |
8201327c | 2601 | structure from which we extract the address that we will land at. |
28bcfd30 | 2602 | This address is copied into PC. This routine returns non-zero on |
436675d3 | 2603 | success. */ |
c906108c | 2604 | |
8201327c | 2605 | static int |
bd2b40ac | 2606 | i386_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) |
c906108c | 2607 | { |
436675d3 | 2608 | gdb_byte buf[4]; |
c906108c | 2609 | CORE_ADDR sp, jb_addr; |
20a6ec49 | 2610 | struct gdbarch *gdbarch = get_frame_arch (frame); |
e17a4113 | 2611 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
08106042 | 2612 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
345bd07c | 2613 | int jb_pc_offset = tdep->jb_pc_offset; |
c906108c | 2614 | |
8201327c MK |
2615 | /* If JB_PC_OFFSET is -1, we have no way to find out where the |
2616 | longjmp will land. */ | |
2617 | if (jb_pc_offset == -1) | |
c906108c SS |
2618 | return 0; |
2619 | ||
436675d3 | 2620 | get_frame_register (frame, I386_ESP_REGNUM, buf); |
e17a4113 | 2621 | sp = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2622 | if (target_read_memory (sp + 4, buf, 4)) |
c906108c SS |
2623 | return 0; |
2624 | ||
e17a4113 | 2625 | jb_addr = extract_unsigned_integer (buf, 4, byte_order); |
436675d3 | 2626 | if (target_read_memory (jb_addr + jb_pc_offset, buf, 4)) |
8201327c | 2627 | return 0; |
c906108c | 2628 | |
e17a4113 | 2629 | *pc = extract_unsigned_integer (buf, 4, byte_order); |
c906108c SS |
2630 | return 1; |
2631 | } | |
fc338970 | 2632 | \f |
c906108c | 2633 | |
7ccc1c74 JM |
2634 | /* Check whether TYPE must be 16-byte-aligned when passed as a |
2635 | function argument. 16-byte vectors, _Decimal128 and structures or | |
2636 | unions containing such types must be 16-byte-aligned; other | |
2637 | arguments are 4-byte-aligned. */ | |
2638 | ||
2639 | static int | |
2640 | i386_16_byte_align_p (struct type *type) | |
2641 | { | |
2642 | type = check_typedef (type); | |
78134374 | 2643 | if ((type->code () == TYPE_CODE_DECFLOAT |
bd63c870 | 2644 | || (type->code () == TYPE_CODE_ARRAY && type->is_vector ())) |
df86565b | 2645 | && type->length () == 16) |
7ccc1c74 | 2646 | return 1; |
78134374 | 2647 | if (type->code () == TYPE_CODE_ARRAY) |
27710edb | 2648 | return i386_16_byte_align_p (type->target_type ()); |
78134374 SM |
2649 | if (type->code () == TYPE_CODE_STRUCT |
2650 | || type->code () == TYPE_CODE_UNION) | |
7ccc1c74 JM |
2651 | { |
2652 | int i; | |
1f704f76 | 2653 | for (i = 0; i < type->num_fields (); i++) |
7ccc1c74 | 2654 | { |
b6a6aa07 TV |
2655 | if (field_is_static (&type->field (i))) |
2656 | continue; | |
940da03e | 2657 | if (i386_16_byte_align_p (type->field (i).type ())) |
7ccc1c74 JM |
2658 | return 1; |
2659 | } | |
2660 | } | |
2661 | return 0; | |
2662 | } | |
2663 | ||
a9b8d892 JK |
2664 | /* Implementation for set_gdbarch_push_dummy_code. */ |
2665 | ||
2666 | static CORE_ADDR | |
2667 | i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, | |
2668 | struct value **args, int nargs, struct type *value_type, | |
2669 | CORE_ADDR *real_pc, CORE_ADDR *bp_addr, | |
2670 | struct regcache *regcache) | |
2671 | { | |
2672 | /* Use 0xcc breakpoint - 1 byte. */ | |
2673 | *bp_addr = sp - 1; | |
2674 | *real_pc = funaddr; | |
2675 | ||
2676 | /* Keep the stack aligned. */ | |
2677 | return sp - 16; | |
2678 | } | |
2679 | ||
627c7fb8 HD |
2680 | /* The "push_dummy_call" gdbarch method, optionally with the thiscall |
2681 | calling convention. */ | |
2682 | ||
2683 | CORE_ADDR | |
2684 | i386_thiscall_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2685 | struct regcache *regcache, CORE_ADDR bp_addr, | |
2686 | int nargs, struct value **args, CORE_ADDR sp, | |
2687 | function_call_return_method return_method, | |
2688 | CORE_ADDR struct_addr, bool thiscall) | |
22f8ba57 | 2689 | { |
e17a4113 | 2690 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
63c0089f | 2691 | gdb_byte buf[4]; |
acd5c798 | 2692 | int i; |
7ccc1c74 JM |
2693 | int write_pass; |
2694 | int args_space = 0; | |
acd5c798 | 2695 | |
4a612d6f WT |
2696 | /* BND registers can be in arbitrary values at the moment of the |
2697 | inferior call. This can cause boundary violations that are not | |
2698 | due to a real bug or even desired by the user. The best to be done | |
2699 | is set the BND registers to allow access to the whole memory, INIT | |
2700 | state, before pushing the inferior call. */ | |
2701 | i387_reset_bnd_regs (gdbarch, regcache); | |
2702 | ||
7ccc1c74 JM |
2703 | /* Determine the total space required for arguments and struct |
2704 | return address in a first pass (allowing for 16-byte-aligned | |
2705 | arguments), then push arguments in a second pass. */ | |
2706 | ||
2707 | for (write_pass = 0; write_pass < 2; write_pass++) | |
22f8ba57 | 2708 | { |
7ccc1c74 | 2709 | int args_space_used = 0; |
7ccc1c74 | 2710 | |
cf84fa6b | 2711 | if (return_method == return_method_struct) |
7ccc1c74 JM |
2712 | { |
2713 | if (write_pass) | |
2714 | { | |
2715 | /* Push value address. */ | |
e17a4113 | 2716 | store_unsigned_integer (buf, 4, byte_order, struct_addr); |
7ccc1c74 JM |
2717 | write_memory (sp, buf, 4); |
2718 | args_space_used += 4; | |
2719 | } | |
2720 | else | |
2721 | args_space += 4; | |
2722 | } | |
2723 | ||
627c7fb8 | 2724 | for (i = thiscall ? 1 : 0; i < nargs; i++) |
7ccc1c74 | 2725 | { |
463b870d | 2726 | int len = args[i]->enclosing_type ()->length (); |
acd5c798 | 2727 | |
7ccc1c74 JM |
2728 | if (write_pass) |
2729 | { | |
463b870d | 2730 | if (i386_16_byte_align_p (args[i]->enclosing_type ())) |
7ccc1c74 | 2731 | args_space_used = align_up (args_space_used, 16); |
acd5c798 | 2732 | |
7ccc1c74 | 2733 | write_memory (sp + args_space_used, |
efaf1ae0 | 2734 | args[i]->contents_all ().data (), len); |
7ccc1c74 | 2735 | /* The System V ABI says that: |
acd5c798 | 2736 | |
7ccc1c74 JM |
2737 | "An argument's size is increased, if necessary, to make it a |
2738 | multiple of [32-bit] words. This may require tail padding, | |
2739 | depending on the size of the argument." | |
22f8ba57 | 2740 | |
7ccc1c74 JM |
2741 | This makes sure the stack stays word-aligned. */ |
2742 | args_space_used += align_up (len, 4); | |
2743 | } | |
2744 | else | |
2745 | { | |
463b870d | 2746 | if (i386_16_byte_align_p (args[i]->enclosing_type ())) |
284c5a60 | 2747 | args_space = align_up (args_space, 16); |
7ccc1c74 JM |
2748 | args_space += align_up (len, 4); |
2749 | } | |
2750 | } | |
2751 | ||
2752 | if (!write_pass) | |
2753 | { | |
7ccc1c74 | 2754 | sp -= args_space; |
284c5a60 MK |
2755 | |
2756 | /* The original System V ABI only requires word alignment, | |
2757 | but modern incarnations need 16-byte alignment in order | |
2758 | to support SSE. Since wasting a few bytes here isn't | |
2759 | harmful we unconditionally enforce 16-byte alignment. */ | |
2760 | sp &= ~0xf; | |
7ccc1c74 | 2761 | } |
22f8ba57 MK |
2762 | } |
2763 | ||
acd5c798 MK |
2764 | /* Store return address. */ |
2765 | sp -= 4; | |
e17a4113 | 2766 | store_unsigned_integer (buf, 4, byte_order, bp_addr); |
acd5c798 MK |
2767 | write_memory (sp, buf, 4); |
2768 | ||
2769 | /* Finally, update the stack pointer... */ | |
e17a4113 | 2770 | store_unsigned_integer (buf, 4, byte_order, sp); |
b66f5587 | 2771 | regcache->cooked_write (I386_ESP_REGNUM, buf); |
acd5c798 MK |
2772 | |
2773 | /* ...and fake a frame pointer. */ | |
b66f5587 | 2774 | regcache->cooked_write (I386_EBP_REGNUM, buf); |
acd5c798 | 2775 | |
627c7fb8 HD |
2776 | /* The 'this' pointer needs to be in ECX. */ |
2777 | if (thiscall) | |
50888e42 | 2778 | regcache->cooked_write (I386_ECX_REGNUM, |
efaf1ae0 | 2779 | args[0]->contents_all ().data ()); |
627c7fb8 | 2780 | |
545e49f5 TV |
2781 | /* If the PLT is position-independent, the SYSTEM V ABI requires %ebx to be |
2782 | set to the address of the GOT when doing a call to a PLT address. | |
2783 | Note that we do not try to determine whether the PLT is | |
2784 | position-independent, we just set the register regardless. */ | |
2785 | CORE_ADDR func_addr = find_function_addr (function, nullptr, nullptr); | |
2786 | if (in_plt_section (func_addr)) | |
2787 | { | |
2788 | struct objfile *objf = nullptr; | |
2789 | asection *asect = nullptr; | |
2790 | obj_section *osect = nullptr; | |
2791 | ||
2792 | /* Get object file containing func_addr. */ | |
2793 | obj_section *func_section = find_pc_section (func_addr); | |
2794 | if (func_section != nullptr) | |
2795 | objf = func_section->objfile; | |
2796 | ||
2797 | if (objf != nullptr) | |
2798 | { | |
2799 | /* Get corresponding .got.plt or .got section. */ | |
98badbfd | 2800 | asect = bfd_get_section_by_name (objf->obfd.get (), ".got.plt"); |
545e49f5 | 2801 | if (asect == nullptr) |
98badbfd | 2802 | asect = bfd_get_section_by_name (objf->obfd.get (), ".got"); |
545e49f5 TV |
2803 | } |
2804 | ||
2805 | if (asect != nullptr) | |
2806 | /* Translate asection to obj_section. */ | |
98badbfd TT |
2807 | osect = maint_obj_section_from_bfd_section (objf->obfd.get (), |
2808 | asect, objf); | |
545e49f5 TV |
2809 | |
2810 | if (osect != nullptr) | |
2811 | { | |
2812 | /* Store the section address in %ebx. */ | |
2813 | store_unsigned_integer (buf, 4, byte_order, osect->addr ()); | |
2814 | regcache->cooked_write (I386_EBX_REGNUM, buf); | |
2815 | } | |
2816 | else | |
2817 | { | |
2818 | /* If we would only do this for a position-independent PLT, it would | |
2819 | make sense to issue a warning here. */ | |
2820 | } | |
2821 | } | |
2822 | ||
3e210248 AC |
2823 | /* MarkK wrote: This "+ 8" is all over the place: |
2824 | (i386_frame_this_id, i386_sigtramp_frame_this_id, | |
10458914 | 2825 | i386_dummy_id). It's there, since all frame unwinders for |
3e210248 | 2826 | a given target have to agree (within a certain margin) on the |
a45ae3ed UW |
2827 | definition of the stack address of a frame. Otherwise frame id |
2828 | comparison might not work correctly. Since DWARF2/GCC uses the | |
3e210248 AC |
2829 | stack address *before* the function call as a frame's CFA. On |
2830 | the i386, when %ebp is used as a frame pointer, the offset | |
2831 | between the contents %ebp and the CFA as defined by GCC. */ | |
2832 | return sp + 8; | |
22f8ba57 MK |
2833 | } |
2834 | ||
627c7fb8 HD |
2835 | /* Implement the "push_dummy_call" gdbarch method. */ |
2836 | ||
2837 | static CORE_ADDR | |
2838 | i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
2839 | struct regcache *regcache, CORE_ADDR bp_addr, int nargs, | |
2840 | struct value **args, CORE_ADDR sp, | |
2841 | function_call_return_method return_method, | |
2842 | CORE_ADDR struct_addr) | |
2843 | { | |
2844 | return i386_thiscall_push_dummy_call (gdbarch, function, regcache, bp_addr, | |
2845 | nargs, args, sp, return_method, | |
2846 | struct_addr, false); | |
2847 | } | |
2848 | ||
1a309862 MK |
2849 | /* These registers are used for returning integers (and on some |
2850 | targets also for returning `struct' and `union' values when their | |
ef9dff19 | 2851 | size and alignment match an integer type). */ |
acd5c798 MK |
2852 | #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */ |
2853 | #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */ | |
1a309862 | 2854 | |
c5e656c1 MK |
2855 | /* Read, for architecture GDBARCH, a function return value of TYPE |
2856 | from REGCACHE, and copy that into VALBUF. */ | |
1a309862 | 2857 | |
3a1e71e3 | 2858 | static void |
c5e656c1 | 2859 | i386_extract_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2860 | struct regcache *regcache, gdb_byte *valbuf) |
c906108c | 2861 | { |
08106042 | 2862 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
df86565b | 2863 | int len = type->length (); |
63c0089f | 2864 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
1a309862 | 2865 | |
0b99a660 FW |
2866 | /* _Float16 and _Float16 _Complex values are returned via xmm0. */ |
2867 | if (((type->code () == TYPE_CODE_FLT) && len == 2) | |
2868 | || ((type->code () == TYPE_CODE_COMPLEX) && len == 4)) | |
2869 | { | |
2870 | regcache->raw_read (I387_XMM0_REGNUM (tdep), valbuf); | |
2871 | return; | |
2872 | } | |
2873 | else if (type->code () == TYPE_CODE_FLT) | |
c906108c | 2874 | { |
5716833c | 2875 | if (tdep->st0_regnum < 0) |
1a309862 | 2876 | { |
8a3fe4f8 | 2877 | warning (_("Cannot find floating-point return value.")); |
1a309862 | 2878 | memset (valbuf, 0, len); |
ef9dff19 | 2879 | return; |
1a309862 MK |
2880 | } |
2881 | ||
c6ba6f0d MK |
2882 | /* Floating-point return values can be found in %st(0). Convert |
2883 | its contents to the desired type. This is probably not | |
2884 | exactly how it would happen on the target itself, but it is | |
2885 | the best we can do. */ | |
0b883586 | 2886 | regcache->raw_read (I386_ST0_REGNUM, buf); |
3b2ca824 | 2887 | target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type); |
c906108c SS |
2888 | } |
2889 | else | |
c5aa993b | 2890 | { |
875f8d0e UW |
2891 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2892 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
d4f3574e SS |
2893 | |
2894 | if (len <= low_size) | |
00f8375e | 2895 | { |
0b883586 | 2896 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e MK |
2897 | memcpy (valbuf, buf, len); |
2898 | } | |
d4f3574e SS |
2899 | else if (len <= (low_size + high_size)) |
2900 | { | |
0b883586 | 2901 | regcache->raw_read (LOW_RETURN_REGNUM, buf); |
00f8375e | 2902 | memcpy (valbuf, buf, low_size); |
0b883586 | 2903 | regcache->raw_read (HIGH_RETURN_REGNUM, buf); |
63c0089f | 2904 | memcpy (valbuf + low_size, buf, len - low_size); |
d4f3574e SS |
2905 | } |
2906 | else | |
f34652de | 2907 | internal_error (_("Cannot extract return value of %d bytes long."), |
1777feb0 | 2908 | len); |
c906108c SS |
2909 | } |
2910 | } | |
2911 | ||
c5e656c1 MK |
2912 | /* Write, for architecture GDBARCH, a function return value of TYPE |
2913 | from VALBUF into REGCACHE. */ | |
ef9dff19 | 2914 | |
3a1e71e3 | 2915 | static void |
c5e656c1 | 2916 | i386_store_return_value (struct gdbarch *gdbarch, struct type *type, |
63c0089f | 2917 | struct regcache *regcache, const gdb_byte *valbuf) |
ef9dff19 | 2918 | { |
08106042 | 2919 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
df86565b | 2920 | int len = type->length (); |
ef9dff19 | 2921 | |
78134374 | 2922 | if (type->code () == TYPE_CODE_FLT) |
ef9dff19 | 2923 | { |
3d7f4f49 | 2924 | ULONGEST fstat; |
63c0089f | 2925 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
ccb945b8 | 2926 | |
5716833c | 2927 | if (tdep->st0_regnum < 0) |
ef9dff19 | 2928 | { |
8a3fe4f8 | 2929 | warning (_("Cannot set floating-point return value.")); |
ef9dff19 MK |
2930 | return; |
2931 | } | |
2932 | ||
635b0cc1 | 2933 | /* Returning floating-point values is a bit tricky. Apart from |
dda83cd7 SM |
2934 | storing the return value in %st(0), we have to simulate the |
2935 | state of the FPU at function return point. */ | |
635b0cc1 | 2936 | |
c6ba6f0d MK |
2937 | /* Convert the value found in VALBUF to the extended |
2938 | floating-point format used by the FPU. This is probably | |
2939 | not exactly how it would happen on the target itself, but | |
2940 | it is the best we can do. */ | |
3b2ca824 | 2941 | target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch)); |
10eaee5f | 2942 | regcache->raw_write (I386_ST0_REGNUM, buf); |
ccb945b8 | 2943 | |
635b0cc1 | 2944 | /* Set the top of the floating-point register stack to 7. The |
dda83cd7 SM |
2945 | actual value doesn't really matter, but 7 is what a normal |
2946 | function return would end up with if the program started out | |
2947 | with a freshly initialized FPU. */ | |
20a6ec49 | 2948 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
ccb945b8 | 2949 | fstat |= (7 << 11); |
20a6ec49 | 2950 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
ccb945b8 | 2951 | |
635b0cc1 | 2952 | /* Mark %st(1) through %st(7) as empty. Since we set the top of |
dda83cd7 SM |
2953 | the floating-point register stack to 7, the appropriate value |
2954 | for the tag word is 0x3fff. */ | |
20a6ec49 | 2955 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
ef9dff19 MK |
2956 | } |
2957 | else | |
2958 | { | |
875f8d0e UW |
2959 | int low_size = register_size (gdbarch, LOW_RETURN_REGNUM); |
2960 | int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM); | |
ef9dff19 MK |
2961 | |
2962 | if (len <= low_size) | |
4f0420fd | 2963 | regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf); |
ef9dff19 MK |
2964 | else if (len <= (low_size + high_size)) |
2965 | { | |
10eaee5f | 2966 | regcache->raw_write (LOW_RETURN_REGNUM, valbuf); |
4f0420fd SM |
2967 | regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size, |
2968 | valbuf + low_size); | |
ef9dff19 MK |
2969 | } |
2970 | else | |
f34652de | 2971 | internal_error (_("Cannot store return value of %d bytes long."), len); |
ef9dff19 MK |
2972 | } |
2973 | } | |
fc338970 | 2974 | \f |
ef9dff19 | 2975 | |
8201327c MK |
2976 | /* This is the variable that is set with "set struct-convention", and |
2977 | its legitimate values. */ | |
2978 | static const char default_struct_convention[] = "default"; | |
2979 | static const char pcc_struct_convention[] = "pcc"; | |
2980 | static const char reg_struct_convention[] = "reg"; | |
40478521 | 2981 | static const char *const valid_conventions[] = |
8201327c MK |
2982 | { |
2983 | default_struct_convention, | |
2984 | pcc_struct_convention, | |
2985 | reg_struct_convention, | |
2986 | NULL | |
2987 | }; | |
2988 | static const char *struct_convention = default_struct_convention; | |
2989 | ||
0e4377e1 JB |
2990 | /* Return non-zero if TYPE, which is assumed to be a structure, |
2991 | a union type, or an array type, should be returned in registers | |
2992 | for architecture GDBARCH. */ | |
c5e656c1 | 2993 | |
8201327c | 2994 | static int |
c5e656c1 | 2995 | i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type) |
8201327c | 2996 | { |
08106042 | 2997 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
78134374 | 2998 | enum type_code code = type->code (); |
df86565b | 2999 | int len = type->length (); |
8201327c | 3000 | |
0e4377e1 | 3001 | gdb_assert (code == TYPE_CODE_STRUCT |
dda83cd7 SM |
3002 | || code == TYPE_CODE_UNION |
3003 | || code == TYPE_CODE_ARRAY); | |
c5e656c1 MK |
3004 | |
3005 | if (struct_convention == pcc_struct_convention | |
3006 | || (struct_convention == default_struct_convention | |
911627e7 TT |
3007 | && tdep->struct_return == pcc_struct_return) |
3008 | || TYPE_HAS_DYNAMIC_LENGTH (type)) | |
c5e656c1 MK |
3009 | return 0; |
3010 | ||
9edde48e MK |
3011 | /* Structures consisting of a single `float', `double' or 'long |
3012 | double' member are returned in %st(0). */ | |
1f704f76 | 3013 | if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) |
9edde48e | 3014 | { |
940da03e | 3015 | type = check_typedef (type->field (0).type ()); |
78134374 | 3016 | if (type->code () == TYPE_CODE_FLT) |
9edde48e MK |
3017 | return (len == 4 || len == 8 || len == 12); |
3018 | } | |
3019 | ||
c5e656c1 MK |
3020 | return (len == 1 || len == 2 || len == 4 || len == 8); |
3021 | } | |
3022 | ||
3023 | /* Determine, for architecture GDBARCH, how a return value of TYPE | |
3024 | should be returned. If it is supposed to be returned in registers, | |
3025 | and READBUF is non-zero, read the appropriate value from REGCACHE, | |
3026 | and copy it into READBUF. If WRITEBUF is non-zero, write the value | |
3027 | from WRITEBUF into REGCACHE. */ | |
3028 | ||
3029 | static enum return_value_convention | |
6a3a010b | 3030 | i386_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 | 3031 | struct type *type, struct regcache *regcache, |
5cb0f2d5 | 3032 | struct value **read_value, const gdb_byte *writebuf) |
c5e656c1 | 3033 | { |
78134374 | 3034 | enum type_code code = type->code (); |
c5e656c1 | 3035 | |
5daa78cc TJB |
3036 | if (((code == TYPE_CODE_STRUCT |
3037 | || code == TYPE_CODE_UNION | |
3038 | || code == TYPE_CODE_ARRAY) | |
3039 | && !i386_reg_struct_return_p (gdbarch, type)) | |
405feb71 | 3040 | /* Complex double and long double uses the struct return convention. */ |
df86565b SM |
3041 | || (code == TYPE_CODE_COMPLEX && type->length () == 16) |
3042 | || (code == TYPE_CODE_COMPLEX && type->length () == 24) | |
5daa78cc | 3043 | /* 128-bit decimal float uses the struct return convention. */ |
df86565b | 3044 | || (code == TYPE_CODE_DECFLOAT && type->length () == 16)) |
31db7b6c MK |
3045 | { |
3046 | /* The System V ABI says that: | |
3047 | ||
3048 | "A function that returns a structure or union also sets %eax | |
3049 | to the value of the original address of the caller's area | |
3050 | before it returns. Thus when the caller receives control | |
3051 | again, the address of the returned object resides in register | |
3052 | %eax and can be used to access the object." | |
3053 | ||
3054 | So the ABI guarantees that we can always find the return | |
3055 | value just after the function has returned. */ | |
3056 | ||
0e4377e1 | 3057 | /* Note that the ABI doesn't mention functions returning arrays, |
dda83cd7 SM |
3058 | which is something possible in certain languages such as Ada. |
3059 | In this case, the value is returned as if it was wrapped in | |
3060 | a record, so the convention applied to records also applies | |
3061 | to arrays. */ | |
0e4377e1 | 3062 | |
911627e7 | 3063 | if (read_value != nullptr) |
31db7b6c MK |
3064 | { |
3065 | ULONGEST addr; | |
3066 | ||
3067 | regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr); | |
911627e7 | 3068 | *read_value = value_at_non_lval (type, addr); |
31db7b6c MK |
3069 | } |
3070 | ||
3071 | return RETURN_VALUE_ABI_RETURNS_ADDRESS; | |
3072 | } | |
c5e656c1 MK |
3073 | |
3074 | /* This special case is for structures consisting of a single | |
9edde48e MK |
3075 | `float', `double' or 'long double' member. These structures are |
3076 | returned in %st(0). For these structures, we call ourselves | |
3077 | recursively, changing TYPE into the type of the first member of | |
3078 | the structure. Since that should work for all structures that | |
3079 | have only one member, we don't bother to check the member's type | |
3080 | here. */ | |
1f704f76 | 3081 | if (code == TYPE_CODE_STRUCT && type->num_fields () == 1) |
c5e656c1 | 3082 | { |
5cb0f2d5 TT |
3083 | struct type *inner_type = check_typedef (type->field (0).type ()); |
3084 | enum return_value_convention result | |
3085 | = i386_return_value (gdbarch, function, inner_type, regcache, | |
3086 | read_value, writebuf); | |
3087 | if (read_value != nullptr) | |
81ae560c | 3088 | (*read_value)->deprecated_set_type (type); |
5cb0f2d5 | 3089 | return result; |
c5e656c1 MK |
3090 | } |
3091 | ||
911627e7 TT |
3092 | if (read_value != nullptr) |
3093 | { | |
317c3ed9 | 3094 | *read_value = value::allocate (type); |
911627e7 | 3095 | i386_extract_return_value (gdbarch, type, regcache, |
bbe912ba | 3096 | (*read_value)->contents_raw ().data ()); |
911627e7 | 3097 | } |
c5e656c1 MK |
3098 | if (writebuf) |
3099 | i386_store_return_value (gdbarch, type, regcache, writebuf); | |
8201327c | 3100 | |
c5e656c1 | 3101 | return RETURN_VALUE_REGISTER_CONVENTION; |
8201327c MK |
3102 | } |
3103 | \f | |
3104 | ||
27067745 UW |
3105 | struct type * |
3106 | i387_ext_type (struct gdbarch *gdbarch) | |
3107 | { | |
08106042 | 3108 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
27067745 UW |
3109 | |
3110 | if (!tdep->i387_ext_type) | |
90884b2b L |
3111 | { |
3112 | tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext"); | |
3113 | gdb_assert (tdep->i387_ext_type != NULL); | |
3114 | } | |
27067745 UW |
3115 | |
3116 | return tdep->i387_ext_type; | |
3117 | } | |
3118 | ||
1dbcd68c WT |
3119 | /* Construct type for pseudo BND registers. We can't use |
3120 | tdesc_find_type since a complement of one value has to be used | |
3121 | to describe the upper bound. */ | |
3122 | ||
3123 | static struct type * | |
3124 | i386_bnd_type (struct gdbarch *gdbarch) | |
3125 | { | |
08106042 | 3126 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1dbcd68c WT |
3127 | |
3128 | ||
3129 | if (!tdep->i386_bnd_type) | |
3130 | { | |
870f88f7 | 3131 | struct type *t; |
1dbcd68c WT |
3132 | const struct builtin_type *bt = builtin_type (gdbarch); |
3133 | ||
3134 | /* The type we're building is described bellow: */ | |
3135 | #if 0 | |
3136 | struct __bound128 | |
3137 | { | |
3138 | void *lbound; | |
3139 | void *ubound; /* One complement of raw ubound field. */ | |
3140 | }; | |
3141 | #endif | |
3142 | ||
3143 | t = arch_composite_type (gdbarch, | |
3144 | "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT); | |
3145 | ||
3146 | append_composite_type_field (t, "lbound", bt->builtin_data_ptr); | |
3147 | append_composite_type_field (t, "ubound", bt->builtin_data_ptr); | |
3148 | ||
d0e39ea2 | 3149 | t->set_name ("builtin_type_bound128"); |
1dbcd68c WT |
3150 | tdep->i386_bnd_type = t; |
3151 | } | |
3152 | ||
3153 | return tdep->i386_bnd_type; | |
3154 | } | |
3155 | ||
01f9f808 MS |
3156 | /* Construct vector type for pseudo ZMM registers. We can't use |
3157 | tdesc_find_type since ZMM isn't described in target description. */ | |
3158 | ||
3159 | static struct type * | |
3160 | i386_zmm_type (struct gdbarch *gdbarch) | |
3161 | { | |
08106042 | 3162 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
01f9f808 MS |
3163 | |
3164 | if (!tdep->i386_zmm_type) | |
3165 | { | |
3166 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3167 | ||
3168 | /* The type we're building is this: */ | |
3169 | #if 0 | |
3170 | union __gdb_builtin_type_vec512i | |
3171 | { | |
1347d111 FW |
3172 | int128_t v4_int128[4]; |
3173 | int64_t v8_int64[8]; | |
3174 | int32_t v16_int32[16]; | |
3175 | int16_t v32_int16[32]; | |
3176 | int8_t v64_int8[64]; | |
3177 | double v8_double[8]; | |
3178 | float v16_float[16]; | |
8661f70c | 3179 | float16_t v32_half[32]; |
2a67f09d | 3180 | bfloat16_t v32_bfloat16[32]; |
01f9f808 MS |
3181 | }; |
3182 | #endif | |
3183 | ||
3184 | struct type *t; | |
3185 | ||
3186 | t = arch_composite_type (gdbarch, | |
3187 | "__gdb_builtin_type_vec512i", TYPE_CODE_UNION); | |
2a67f09d FW |
3188 | append_composite_type_field (t, "v32_bfloat16", |
3189 | init_vector_type (bt->builtin_bfloat16, 32)); | |
8661f70c FW |
3190 | append_composite_type_field (t, "v32_half", |
3191 | init_vector_type (bt->builtin_half, 32)); | |
01f9f808 MS |
3192 | append_composite_type_field (t, "v16_float", |
3193 | init_vector_type (bt->builtin_float, 16)); | |
3194 | append_composite_type_field (t, "v8_double", | |
3195 | init_vector_type (bt->builtin_double, 8)); | |
3196 | append_composite_type_field (t, "v64_int8", | |
3197 | init_vector_type (bt->builtin_int8, 64)); | |
3198 | append_composite_type_field (t, "v32_int16", | |
3199 | init_vector_type (bt->builtin_int16, 32)); | |
3200 | append_composite_type_field (t, "v16_int32", | |
3201 | init_vector_type (bt->builtin_int32, 16)); | |
3202 | append_composite_type_field (t, "v8_int64", | |
3203 | init_vector_type (bt->builtin_int64, 8)); | |
3204 | append_composite_type_field (t, "v4_int128", | |
3205 | init_vector_type (bt->builtin_int128, 4)); | |
3206 | ||
2062087b | 3207 | t->set_is_vector (true); |
d0e39ea2 | 3208 | t->set_name ("builtin_type_vec512i"); |
01f9f808 MS |
3209 | tdep->i386_zmm_type = t; |
3210 | } | |
3211 | ||
3212 | return tdep->i386_zmm_type; | |
3213 | } | |
3214 | ||
c131fcee L |
3215 | /* Construct vector type for pseudo YMM registers. We can't use |
3216 | tdesc_find_type since YMM isn't described in target description. */ | |
3217 | ||
3218 | static struct type * | |
3219 | i386_ymm_type (struct gdbarch *gdbarch) | |
3220 | { | |
08106042 | 3221 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
c131fcee L |
3222 | |
3223 | if (!tdep->i386_ymm_type) | |
3224 | { | |
3225 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3226 | ||
3227 | /* The type we're building is this: */ | |
3228 | #if 0 | |
3229 | union __gdb_builtin_type_vec256i | |
3230 | { | |
dda83cd7 SM |
3231 | int128_t v2_int128[2]; |
3232 | int64_t v4_int64[4]; | |
3233 | int32_t v8_int32[8]; | |
3234 | int16_t v16_int16[16]; | |
3235 | int8_t v32_int8[32]; | |
3236 | double v4_double[4]; | |
3237 | float v8_float[8]; | |
8661f70c | 3238 | float16_t v16_half[16]; |
dda83cd7 | 3239 | bfloat16_t v16_bfloat16[16]; |
c131fcee L |
3240 | }; |
3241 | #endif | |
3242 | ||
3243 | struct type *t; | |
3244 | ||
3245 | t = arch_composite_type (gdbarch, | |
3246 | "__gdb_builtin_type_vec256i", TYPE_CODE_UNION); | |
2a67f09d FW |
3247 | append_composite_type_field (t, "v16_bfloat16", |
3248 | init_vector_type (bt->builtin_bfloat16, 16)); | |
8661f70c FW |
3249 | append_composite_type_field (t, "v16_half", |
3250 | init_vector_type (bt->builtin_half, 16)); | |
c131fcee L |
3251 | append_composite_type_field (t, "v8_float", |
3252 | init_vector_type (bt->builtin_float, 8)); | |
3253 | append_composite_type_field (t, "v4_double", | |
3254 | init_vector_type (bt->builtin_double, 4)); | |
3255 | append_composite_type_field (t, "v32_int8", | |
3256 | init_vector_type (bt->builtin_int8, 32)); | |
3257 | append_composite_type_field (t, "v16_int16", | |
3258 | init_vector_type (bt->builtin_int16, 16)); | |
3259 | append_composite_type_field (t, "v8_int32", | |
3260 | init_vector_type (bt->builtin_int32, 8)); | |
3261 | append_composite_type_field (t, "v4_int64", | |
3262 | init_vector_type (bt->builtin_int64, 4)); | |
3263 | append_composite_type_field (t, "v2_int128", | |
3264 | init_vector_type (bt->builtin_int128, 2)); | |
3265 | ||
2062087b | 3266 | t->set_is_vector (true); |
d0e39ea2 | 3267 | t->set_name ("builtin_type_vec256i"); |
c131fcee L |
3268 | tdep->i386_ymm_type = t; |
3269 | } | |
3270 | ||
3271 | return tdep->i386_ymm_type; | |
3272 | } | |
3273 | ||
794ac428 | 3274 | /* Construct vector type for MMX registers. */ |
90884b2b | 3275 | static struct type * |
794ac428 UW |
3276 | i386_mmx_type (struct gdbarch *gdbarch) |
3277 | { | |
08106042 | 3278 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
794ac428 UW |
3279 | |
3280 | if (!tdep->i386_mmx_type) | |
3281 | { | |
df4df182 UW |
3282 | const struct builtin_type *bt = builtin_type (gdbarch); |
3283 | ||
794ac428 UW |
3284 | /* The type we're building is this: */ |
3285 | #if 0 | |
3286 | union __gdb_builtin_type_vec64i | |
3287 | { | |
dda83cd7 SM |
3288 | int64_t uint64; |
3289 | int32_t v2_int32[2]; | |
3290 | int16_t v4_int16[4]; | |
3291 | int8_t v8_int8[8]; | |
794ac428 UW |
3292 | }; |
3293 | #endif | |
3294 | ||
3295 | struct type *t; | |
3296 | ||
e9bb382b UW |
3297 | t = arch_composite_type (gdbarch, |
3298 | "__gdb_builtin_type_vec64i", TYPE_CODE_UNION); | |
df4df182 UW |
3299 | |
3300 | append_composite_type_field (t, "uint64", bt->builtin_int64); | |
794ac428 | 3301 | append_composite_type_field (t, "v2_int32", |
df4df182 | 3302 | init_vector_type (bt->builtin_int32, 2)); |
794ac428 | 3303 | append_composite_type_field (t, "v4_int16", |
df4df182 | 3304 | init_vector_type (bt->builtin_int16, 4)); |
794ac428 | 3305 | append_composite_type_field (t, "v8_int8", |
df4df182 | 3306 | init_vector_type (bt->builtin_int8, 8)); |
794ac428 | 3307 | |
2062087b | 3308 | t->set_is_vector (true); |
d0e39ea2 | 3309 | t->set_name ("builtin_type_vec64i"); |
794ac428 UW |
3310 | tdep->i386_mmx_type = t; |
3311 | } | |
3312 | ||
3313 | return tdep->i386_mmx_type; | |
3314 | } | |
3315 | ||
d7a0d72c | 3316 | /* Return the GDB type object for the "standard" data type of data in |
1777feb0 | 3317 | register REGNUM. */ |
d7a0d72c | 3318 | |
fff4548b | 3319 | struct type * |
90884b2b | 3320 | i386_pseudo_register_type (struct gdbarch *gdbarch, int regnum) |
d7a0d72c | 3321 | { |
1dbcd68c WT |
3322 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3323 | return i386_bnd_type (gdbarch); | |
1ba53b71 L |
3324 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
3325 | return i386_mmx_type (gdbarch); | |
c131fcee L |
3326 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
3327 | return i386_ymm_type (gdbarch); | |
01f9f808 MS |
3328 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3329 | return i386_ymm_type (gdbarch); | |
3330 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3331 | return i386_zmm_type (gdbarch); | |
1ba53b71 L |
3332 | else |
3333 | { | |
3334 | const struct builtin_type *bt = builtin_type (gdbarch); | |
3335 | if (i386_byte_regnum_p (gdbarch, regnum)) | |
3336 | return bt->builtin_int8; | |
3337 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3338 | return bt->builtin_int16; | |
3339 | else if (i386_dword_regnum_p (gdbarch, regnum)) | |
3340 | return bt->builtin_int32; | |
01f9f808 MS |
3341 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3342 | return bt->builtin_int64; | |
1ba53b71 L |
3343 | } |
3344 | ||
f34652de | 3345 | internal_error (_("invalid regnum")); |
d7a0d72c MK |
3346 | } |
3347 | ||
28fc6740 | 3348 | /* Map a cooked register onto a raw register or memory. For the i386, |
acd5c798 | 3349 | the MMX registers need to be mapped onto floating point registers. */ |
28fc6740 AC |
3350 | |
3351 | static int | |
849d0ba8 | 3352 | i386_mmx_regnum_to_fp_regnum (readable_regcache *regcache, int regnum) |
28fc6740 | 3353 | { |
345bd07c | 3354 | gdbarch *arch = regcache->arch (); |
08106042 | 3355 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
5716833c | 3356 | int mmxreg, fpreg; |
28fc6740 AC |
3357 | ULONGEST fstat; |
3358 | int tos; | |
c86c27af | 3359 | |
5716833c | 3360 | mmxreg = regnum - tdep->mm0_regnum; |
03f50fc8 | 3361 | regcache->raw_read (I387_FSTAT_REGNUM (tdep), &fstat); |
28fc6740 | 3362 | tos = (fstat >> 11) & 0x7; |
5716833c MK |
3363 | fpreg = (mmxreg + tos) % 8; |
3364 | ||
20a6ec49 | 3365 | return (I387_ST0_REGNUM (tdep) + fpreg); |
28fc6740 AC |
3366 | } |
3367 | ||
3543a589 TT |
3368 | /* A helper function for us by i386_pseudo_register_read_value and |
3369 | amd64_pseudo_register_read_value. It does all the work but reads | |
3370 | the data into an already-allocated value. */ | |
3371 | ||
3372 | void | |
3373 | i386_pseudo_register_read_into_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3374 | readable_regcache *regcache, |
3543a589 TT |
3375 | int regnum, |
3376 | struct value *result_value) | |
28fc6740 | 3377 | { |
975c21ab | 3378 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
05d1431c | 3379 | enum register_status status; |
bbe912ba | 3380 | gdb_byte *buf = result_value->contents_raw ().data (); |
1ba53b71 | 3381 | |
5716833c | 3382 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3383 | { |
c86c27af MK |
3384 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3385 | ||
28fc6740 | 3386 | /* Extract (always little endian). */ |
03f50fc8 | 3387 | status = regcache->raw_read (fpnum, raw_buf); |
05d1431c | 3388 | if (status != REG_VALID) |
d00664db TT |
3389 | result_value->mark_bytes_unavailable (0, |
3390 | result_value->type ()->length ()); | |
3543a589 TT |
3391 | else |
3392 | memcpy (buf, raw_buf, register_size (gdbarch, regnum)); | |
28fc6740 AC |
3393 | } |
3394 | else | |
1ba53b71 | 3395 | { |
08106042 | 3396 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1dbcd68c WT |
3397 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3398 | { | |
3399 | regnum -= tdep->bnd0_regnum; | |
1ba53b71 | 3400 | |
1dbcd68c | 3401 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3402 | status = regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3403 | raw_buf); | |
1dbcd68c | 3404 | if (status != REG_VALID) |
d00664db | 3405 | result_value->mark_bytes_unavailable (0, 16); |
1dbcd68c WT |
3406 | else |
3407 | { | |
3408 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); | |
3409 | LONGEST upper, lower; | |
df86565b | 3410 | int size = builtin_type (gdbarch)->builtin_data_ptr->length (); |
1dbcd68c WT |
3411 | |
3412 | lower = extract_unsigned_integer (raw_buf, 8, byte_order); | |
3413 | upper = extract_unsigned_integer (raw_buf + 8, 8, byte_order); | |
3414 | upper = ~upper; | |
3415 | ||
3416 | memcpy (buf, &lower, size); | |
3417 | memcpy (buf + size, &upper, size); | |
3418 | } | |
3419 | } | |
01f9f808 MS |
3420 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3421 | { | |
3422 | regnum -= tdep->k0_regnum; | |
3423 | ||
3424 | /* Extract (always little endian). */ | |
03f50fc8 | 3425 | status = regcache->raw_read (tdep->k0_regnum + regnum, raw_buf); |
01f9f808 | 3426 | if (status != REG_VALID) |
d00664db | 3427 | result_value->mark_bytes_unavailable (0, 8); |
01f9f808 MS |
3428 | else |
3429 | memcpy (buf, raw_buf, 8); | |
3430 | } | |
3431 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3432 | { | |
3433 | regnum -= tdep->zmm0_regnum; | |
3434 | ||
3435 | if (regnum < num_lower_zmm_regs) | |
3436 | { | |
3437 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3438 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3439 | raw_buf); | |
01f9f808 | 3440 | if (status != REG_VALID) |
d00664db | 3441 | result_value->mark_bytes_unavailable (0, 16); |
01f9f808 MS |
3442 | else |
3443 | memcpy (buf, raw_buf, 16); | |
3444 | ||
3445 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3446 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3447 | raw_buf); | |
01f9f808 | 3448 | if (status != REG_VALID) |
d00664db | 3449 | result_value->mark_bytes_unavailable (16, 16); |
01f9f808 MS |
3450 | else |
3451 | memcpy (buf + 16, raw_buf, 16); | |
3452 | } | |
3453 | else | |
3454 | { | |
3455 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3456 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum |
3457 | - num_lower_zmm_regs, | |
3458 | raw_buf); | |
01f9f808 | 3459 | if (status != REG_VALID) |
d00664db | 3460 | result_value->mark_bytes_unavailable (0, 16); |
01f9f808 MS |
3461 | else |
3462 | memcpy (buf, raw_buf, 16); | |
3463 | ||
3464 | /* Extract (always little endian). Read upper 128bits. */ | |
03f50fc8 YQ |
3465 | status = regcache->raw_read (I387_YMM16H_REGNUM (tdep) + regnum |
3466 | - num_lower_zmm_regs, | |
3467 | raw_buf); | |
01f9f808 | 3468 | if (status != REG_VALID) |
d00664db | 3469 | result_value->mark_bytes_unavailable (16, 16); |
01f9f808 MS |
3470 | else |
3471 | memcpy (buf + 16, raw_buf, 16); | |
3472 | } | |
3473 | ||
3474 | /* Read upper 256bits. */ | |
03f50fc8 YQ |
3475 | status = regcache->raw_read (tdep->zmm0h_regnum + regnum, |
3476 | raw_buf); | |
01f9f808 | 3477 | if (status != REG_VALID) |
d00664db | 3478 | result_value->mark_bytes_unavailable (32, 32); |
01f9f808 MS |
3479 | else |
3480 | memcpy (buf + 32, raw_buf, 32); | |
3481 | } | |
1dbcd68c | 3482 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3483 | { |
3484 | regnum -= tdep->ymm0_regnum; | |
3485 | ||
1777feb0 | 3486 | /* Extract (always little endian). Read lower 128bits. */ |
03f50fc8 YQ |
3487 | status = regcache->raw_read (I387_XMM0_REGNUM (tdep) + regnum, |
3488 | raw_buf); | |
05d1431c | 3489 | if (status != REG_VALID) |
d00664db | 3490 | result_value->mark_bytes_unavailable (0, 16); |
3543a589 TT |
3491 | else |
3492 | memcpy (buf, raw_buf, 16); | |
c131fcee | 3493 | /* Read upper 128bits. */ |
03f50fc8 YQ |
3494 | status = regcache->raw_read (tdep->ymm0h_regnum + regnum, |
3495 | raw_buf); | |
05d1431c | 3496 | if (status != REG_VALID) |
d00664db | 3497 | result_value->mark_bytes_unavailable (16, 32); |
3543a589 TT |
3498 | else |
3499 | memcpy (buf + 16, raw_buf, 16); | |
c131fcee | 3500 | } |
01f9f808 MS |
3501 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3502 | { | |
3503 | regnum -= tdep->ymm16_regnum; | |
3504 | /* Extract (always little endian). Read lower 128bits. */ | |
03f50fc8 YQ |
3505 | status = regcache->raw_read (I387_XMM16_REGNUM (tdep) + regnum, |
3506 | raw_buf); | |
01f9f808 | 3507 | if (status != REG_VALID) |
d00664db | 3508 | result_value->mark_bytes_unavailable (0, 16); |
01f9f808 MS |
3509 | else |
3510 | memcpy (buf, raw_buf, 16); | |
3511 | /* Read upper 128bits. */ | |
03f50fc8 YQ |
3512 | status = regcache->raw_read (tdep->ymm16h_regnum + regnum, |
3513 | raw_buf); | |
01f9f808 | 3514 | if (status != REG_VALID) |
d00664db | 3515 | result_value->mark_bytes_unavailable (16, 16); |
01f9f808 MS |
3516 | else |
3517 | memcpy (buf + 16, raw_buf, 16); | |
3518 | } | |
c131fcee | 3519 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3520 | { |
3521 | int gpnum = regnum - tdep->ax_regnum; | |
3522 | ||
3523 | /* Extract (always little endian). */ | |
03f50fc8 | 3524 | status = regcache->raw_read (gpnum, raw_buf); |
05d1431c | 3525 | if (status != REG_VALID) |
d00664db TT |
3526 | result_value->mark_bytes_unavailable (0, |
3527 | result_value->type ()->length ()); | |
3543a589 TT |
3528 | else |
3529 | memcpy (buf, raw_buf, 2); | |
1ba53b71 L |
3530 | } |
3531 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3532 | { | |
1ba53b71 L |
3533 | int gpnum = regnum - tdep->al_regnum; |
3534 | ||
3535 | /* Extract (always little endian). We read both lower and | |
3536 | upper registers. */ | |
03f50fc8 | 3537 | status = regcache->raw_read (gpnum % 4, raw_buf); |
05d1431c | 3538 | if (status != REG_VALID) |
d00664db TT |
3539 | result_value->mark_bytes_unavailable (0, |
3540 | result_value->type ()->length ()); | |
3543a589 | 3541 | else if (gpnum >= 4) |
1ba53b71 L |
3542 | memcpy (buf, raw_buf + 1, 1); |
3543 | else | |
3544 | memcpy (buf, raw_buf, 1); | |
3545 | } | |
3546 | else | |
f34652de | 3547 | internal_error (_("invalid regnum")); |
1ba53b71 | 3548 | } |
3543a589 TT |
3549 | } |
3550 | ||
3551 | static struct value * | |
3552 | i386_pseudo_register_read_value (struct gdbarch *gdbarch, | |
849d0ba8 | 3553 | readable_regcache *regcache, |
3543a589 TT |
3554 | int regnum) |
3555 | { | |
3556 | struct value *result; | |
3557 | ||
317c3ed9 | 3558 | result = value::allocate (register_type (gdbarch, regnum)); |
6f9c9d71 | 3559 | result->set_lval (lval_register); |
3543a589 TT |
3560 | VALUE_REGNUM (result) = regnum; |
3561 | ||
3562 | i386_pseudo_register_read_into_value (gdbarch, regcache, regnum, result); | |
05d1431c | 3563 | |
3543a589 | 3564 | return result; |
28fc6740 AC |
3565 | } |
3566 | ||
1ba53b71 | 3567 | void |
28fc6740 | 3568 | i386_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, |
42835c2b | 3569 | int regnum, const gdb_byte *buf) |
28fc6740 | 3570 | { |
975c21ab | 3571 | gdb_byte raw_buf[I386_MAX_REGISTER_SIZE]; |
1ba53b71 | 3572 | |
5716833c | 3573 | if (i386_mmx_regnum_p (gdbarch, regnum)) |
28fc6740 | 3574 | { |
c86c27af MK |
3575 | int fpnum = i386_mmx_regnum_to_fp_regnum (regcache, regnum); |
3576 | ||
28fc6740 | 3577 | /* Read ... */ |
0b883586 | 3578 | regcache->raw_read (fpnum, raw_buf); |
28fc6740 | 3579 | /* ... Modify ... (always little endian). */ |
1ba53b71 | 3580 | memcpy (raw_buf, buf, register_size (gdbarch, regnum)); |
28fc6740 | 3581 | /* ... Write. */ |
10eaee5f | 3582 | regcache->raw_write (fpnum, raw_buf); |
28fc6740 AC |
3583 | } |
3584 | else | |
1ba53b71 | 3585 | { |
08106042 | 3586 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1ba53b71 | 3587 | |
1dbcd68c WT |
3588 | if (i386_bnd_regnum_p (gdbarch, regnum)) |
3589 | { | |
3590 | ULONGEST upper, lower; | |
df86565b | 3591 | int size = builtin_type (gdbarch)->builtin_data_ptr->length (); |
1dbcd68c WT |
3592 | enum bfd_endian byte_order = gdbarch_byte_order (target_gdbarch ()); |
3593 | ||
3594 | /* New values from input value. */ | |
3595 | regnum -= tdep->bnd0_regnum; | |
3596 | lower = extract_unsigned_integer (buf, size, byte_order); | |
3597 | upper = extract_unsigned_integer (buf + size, size, byte_order); | |
3598 | ||
3599 | /* Fetching register buffer. */ | |
0b883586 SM |
3600 | regcache->raw_read (I387_BND0R_REGNUM (tdep) + regnum, |
3601 | raw_buf); | |
1dbcd68c WT |
3602 | |
3603 | upper = ~upper; | |
3604 | ||
3605 | /* Set register bits. */ | |
3606 | memcpy (raw_buf, &lower, 8); | |
3607 | memcpy (raw_buf + 8, &upper, 8); | |
3608 | ||
10eaee5f | 3609 | regcache->raw_write (I387_BND0R_REGNUM (tdep) + regnum, raw_buf); |
1dbcd68c | 3610 | } |
01f9f808 MS |
3611 | else if (i386_k_regnum_p (gdbarch, regnum)) |
3612 | { | |
3613 | regnum -= tdep->k0_regnum; | |
3614 | ||
10eaee5f | 3615 | regcache->raw_write (tdep->k0_regnum + regnum, buf); |
01f9f808 MS |
3616 | } |
3617 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3618 | { | |
3619 | regnum -= tdep->zmm0_regnum; | |
3620 | ||
3621 | if (regnum < num_lower_zmm_regs) | |
3622 | { | |
3623 | /* Write lower 128bits. */ | |
10eaee5f | 3624 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3625 | /* Write upper 128bits. */ |
10eaee5f | 3626 | regcache->raw_write (I387_YMM0_REGNUM (tdep) + regnum, buf + 16); |
01f9f808 MS |
3627 | } |
3628 | else | |
3629 | { | |
3630 | /* Write lower 128bits. */ | |
10eaee5f SM |
3631 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum |
3632 | - num_lower_zmm_regs, buf); | |
01f9f808 | 3633 | /* Write upper 128bits. */ |
10eaee5f SM |
3634 | regcache->raw_write (I387_YMM16H_REGNUM (tdep) + regnum |
3635 | - num_lower_zmm_regs, buf + 16); | |
01f9f808 MS |
3636 | } |
3637 | /* Write upper 256bits. */ | |
10eaee5f | 3638 | regcache->raw_write (tdep->zmm0h_regnum + regnum, buf + 32); |
01f9f808 | 3639 | } |
1dbcd68c | 3640 | else if (i386_ymm_regnum_p (gdbarch, regnum)) |
c131fcee L |
3641 | { |
3642 | regnum -= tdep->ymm0_regnum; | |
3643 | ||
3644 | /* ... Write lower 128bits. */ | |
10eaee5f | 3645 | regcache->raw_write (I387_XMM0_REGNUM (tdep) + regnum, buf); |
c131fcee | 3646 | /* ... Write upper 128bits. */ |
10eaee5f | 3647 | regcache->raw_write (tdep->ymm0h_regnum + regnum, buf + 16); |
c131fcee | 3648 | } |
01f9f808 MS |
3649 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) |
3650 | { | |
3651 | regnum -= tdep->ymm16_regnum; | |
3652 | ||
3653 | /* ... Write lower 128bits. */ | |
10eaee5f | 3654 | regcache->raw_write (I387_XMM16_REGNUM (tdep) + regnum, buf); |
01f9f808 | 3655 | /* ... Write upper 128bits. */ |
10eaee5f | 3656 | regcache->raw_write (tdep->ymm16h_regnum + regnum, buf + 16); |
01f9f808 | 3657 | } |
c131fcee | 3658 | else if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
3659 | { |
3660 | int gpnum = regnum - tdep->ax_regnum; | |
3661 | ||
3662 | /* Read ... */ | |
0b883586 | 3663 | regcache->raw_read (gpnum, raw_buf); |
1ba53b71 L |
3664 | /* ... Modify ... (always little endian). */ |
3665 | memcpy (raw_buf, buf, 2); | |
3666 | /* ... Write. */ | |
10eaee5f | 3667 | regcache->raw_write (gpnum, raw_buf); |
1ba53b71 L |
3668 | } |
3669 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3670 | { | |
1ba53b71 L |
3671 | int gpnum = regnum - tdep->al_regnum; |
3672 | ||
3673 | /* Read ... We read both lower and upper registers. */ | |
0b883586 | 3674 | regcache->raw_read (gpnum % 4, raw_buf); |
1ba53b71 L |
3675 | /* ... Modify ... (always little endian). */ |
3676 | if (gpnum >= 4) | |
3677 | memcpy (raw_buf + 1, buf, 1); | |
3678 | else | |
3679 | memcpy (raw_buf, buf, 1); | |
3680 | /* ... Write. */ | |
10eaee5f | 3681 | regcache->raw_write (gpnum % 4, raw_buf); |
1ba53b71 L |
3682 | } |
3683 | else | |
f34652de | 3684 | internal_error (_("invalid regnum")); |
1ba53b71 | 3685 | } |
28fc6740 | 3686 | } |
62e5fd57 MK |
3687 | |
3688 | /* Implement the 'ax_pseudo_register_collect' gdbarch method. */ | |
3689 | ||
3690 | int | |
3691 | i386_ax_pseudo_register_collect (struct gdbarch *gdbarch, | |
3692 | struct agent_expr *ax, int regnum) | |
3693 | { | |
08106042 | 3694 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
62e5fd57 MK |
3695 | |
3696 | if (i386_mmx_regnum_p (gdbarch, regnum)) | |
3697 | { | |
3698 | /* MMX to FPU register mapping depends on current TOS. Let's just | |
3699 | not care and collect everything... */ | |
3700 | int i; | |
3701 | ||
3702 | ax_reg_mask (ax, I387_FSTAT_REGNUM (tdep)); | |
3703 | for (i = 0; i < 8; i++) | |
3704 | ax_reg_mask (ax, I387_ST0_REGNUM (tdep) + i); | |
3705 | return 0; | |
3706 | } | |
3707 | else if (i386_bnd_regnum_p (gdbarch, regnum)) | |
3708 | { | |
3709 | regnum -= tdep->bnd0_regnum; | |
3710 | ax_reg_mask (ax, I387_BND0R_REGNUM (tdep) + regnum); | |
3711 | return 0; | |
3712 | } | |
3713 | else if (i386_k_regnum_p (gdbarch, regnum)) | |
3714 | { | |
3715 | regnum -= tdep->k0_regnum; | |
3716 | ax_reg_mask (ax, tdep->k0_regnum + regnum); | |
3717 | return 0; | |
3718 | } | |
3719 | else if (i386_zmm_regnum_p (gdbarch, regnum)) | |
3720 | { | |
3721 | regnum -= tdep->zmm0_regnum; | |
3722 | if (regnum < num_lower_zmm_regs) | |
3723 | { | |
3724 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3725 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3726 | } | |
3727 | else | |
3728 | { | |
3729 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum | |
3730 | - num_lower_zmm_regs); | |
3731 | ax_reg_mask (ax, I387_YMM16H_REGNUM (tdep) + regnum | |
3732 | - num_lower_zmm_regs); | |
3733 | } | |
3734 | ax_reg_mask (ax, tdep->zmm0h_regnum + regnum); | |
3735 | return 0; | |
3736 | } | |
3737 | else if (i386_ymm_regnum_p (gdbarch, regnum)) | |
3738 | { | |
3739 | regnum -= tdep->ymm0_regnum; | |
3740 | ax_reg_mask (ax, I387_XMM0_REGNUM (tdep) + regnum); | |
3741 | ax_reg_mask (ax, tdep->ymm0h_regnum + regnum); | |
3742 | return 0; | |
3743 | } | |
3744 | else if (i386_ymm_avx512_regnum_p (gdbarch, regnum)) | |
3745 | { | |
3746 | regnum -= tdep->ymm16_regnum; | |
3747 | ax_reg_mask (ax, I387_XMM16_REGNUM (tdep) + regnum); | |
3748 | ax_reg_mask (ax, tdep->ymm16h_regnum + regnum); | |
3749 | return 0; | |
3750 | } | |
3751 | else if (i386_word_regnum_p (gdbarch, regnum)) | |
3752 | { | |
3753 | int gpnum = regnum - tdep->ax_regnum; | |
3754 | ||
3755 | ax_reg_mask (ax, gpnum); | |
3756 | return 0; | |
3757 | } | |
3758 | else if (i386_byte_regnum_p (gdbarch, regnum)) | |
3759 | { | |
3760 | int gpnum = regnum - tdep->al_regnum; | |
3761 | ||
3762 | ax_reg_mask (ax, gpnum % 4); | |
3763 | return 0; | |
3764 | } | |
3765 | else | |
f34652de | 3766 | internal_error (_("invalid regnum")); |
62e5fd57 MK |
3767 | return 1; |
3768 | } | |
ff2e87ac AC |
3769 | \f |
3770 | ||
ff2e87ac AC |
3771 | /* Return the register number of the register allocated by GCC after |
3772 | REGNUM, or -1 if there is no such register. */ | |
3773 | ||
3774 | static int | |
3775 | i386_next_regnum (int regnum) | |
3776 | { | |
3777 | /* GCC allocates the registers in the order: | |
3778 | ||
3779 | %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ... | |
3780 | ||
3781 | Since storing a variable in %esp doesn't make any sense we return | |
3782 | -1 for %ebp and for %esp itself. */ | |
3783 | static int next_regnum[] = | |
3784 | { | |
3785 | I386_EDX_REGNUM, /* Slot for %eax. */ | |
3786 | I386_EBX_REGNUM, /* Slot for %ecx. */ | |
3787 | I386_ECX_REGNUM, /* Slot for %edx. */ | |
3788 | I386_ESI_REGNUM, /* Slot for %ebx. */ | |
3789 | -1, -1, /* Slots for %esp and %ebp. */ | |
3790 | I386_EDI_REGNUM, /* Slot for %esi. */ | |
3791 | I386_EBP_REGNUM /* Slot for %edi. */ | |
3792 | }; | |
3793 | ||
de5b9bb9 | 3794 | if (regnum >= 0 && regnum < sizeof (next_regnum) / sizeof (next_regnum[0])) |
ff2e87ac | 3795 | return next_regnum[regnum]; |
28fc6740 | 3796 | |
ff2e87ac AC |
3797 | return -1; |
3798 | } | |
3799 | ||
3800 | /* Return nonzero if a value of type TYPE stored in register REGNUM | |
3801 | needs any special handling. */ | |
d7a0d72c | 3802 | |
3a1e71e3 | 3803 | static int |
1777feb0 MS |
3804 | i386_convert_register_p (struct gdbarch *gdbarch, |
3805 | int regnum, struct type *type) | |
d7a0d72c | 3806 | { |
df86565b | 3807 | int len = type->length (); |
de5b9bb9 | 3808 | |
ff2e87ac AC |
3809 | /* Values may be spread across multiple registers. Most debugging |
3810 | formats aren't expressive enough to specify the locations, so | |
3811 | some heuristics is involved. Right now we only handle types that | |
de5b9bb9 MK |
3812 | have a length that is a multiple of the word size, since GCC |
3813 | doesn't seem to put any other types into registers. */ | |
3814 | if (len > 4 && len % 4 == 0) | |
3815 | { | |
3816 | int last_regnum = regnum; | |
3817 | ||
3818 | while (len > 4) | |
3819 | { | |
3820 | last_regnum = i386_next_regnum (last_regnum); | |
3821 | len -= 4; | |
3822 | } | |
3823 | ||
3824 | if (last_regnum != -1) | |
3825 | return 1; | |
3826 | } | |
ff2e87ac | 3827 | |
0abe36f5 | 3828 | return i387_convert_register_p (gdbarch, regnum, type); |
d7a0d72c MK |
3829 | } |
3830 | ||
ff2e87ac AC |
3831 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
3832 | return its contents in TO. */ | |
ac27f131 | 3833 | |
8dccd430 | 3834 | static int |
bd2b40ac | 3835 | i386_register_to_value (frame_info_ptr frame, int regnum, |
8dccd430 PA |
3836 | struct type *type, gdb_byte *to, |
3837 | int *optimizedp, int *unavailablep) | |
ac27f131 | 3838 | { |
20a6ec49 | 3839 | struct gdbarch *gdbarch = get_frame_arch (frame); |
df86565b | 3840 | int len = type->length (); |
de5b9bb9 | 3841 | |
20a6ec49 | 3842 | if (i386_fp_regnum_p (gdbarch, regnum)) |
8dccd430 PA |
3843 | return i387_register_to_value (frame, regnum, type, to, |
3844 | optimizedp, unavailablep); | |
ff2e87ac | 3845 | |
fd35795f | 3846 | /* Read a value spread across multiple registers. */ |
de5b9bb9 MK |
3847 | |
3848 | gdb_assert (len > 4 && len % 4 == 0); | |
3d261580 | 3849 | |
de5b9bb9 MK |
3850 | while (len > 0) |
3851 | { | |
3852 | gdb_assert (regnum != -1); | |
20a6ec49 | 3853 | gdb_assert (register_size (gdbarch, regnum) == 4); |
d532c08f | 3854 | |
8dccd430 | 3855 | if (!get_frame_register_bytes (frame, regnum, 0, |
bdec2917 LM |
3856 | gdb::make_array_view (to, |
3857 | register_size (gdbarch, | |
3858 | regnum)), | |
3859 | optimizedp, unavailablep)) | |
8dccd430 PA |
3860 | return 0; |
3861 | ||
de5b9bb9 MK |
3862 | regnum = i386_next_regnum (regnum); |
3863 | len -= 4; | |
42835c2b | 3864 | to += 4; |
de5b9bb9 | 3865 | } |
8dccd430 PA |
3866 | |
3867 | *optimizedp = *unavailablep = 0; | |
3868 | return 1; | |
ac27f131 MK |
3869 | } |
3870 | ||
ff2e87ac AC |
3871 | /* Write the contents FROM of a value of type TYPE into register |
3872 | REGNUM in frame FRAME. */ | |
ac27f131 | 3873 | |
3a1e71e3 | 3874 | static void |
bd2b40ac | 3875 | i386_value_to_register (frame_info_ptr frame, int regnum, |
42835c2b | 3876 | struct type *type, const gdb_byte *from) |
ac27f131 | 3877 | { |
df86565b | 3878 | int len = type->length (); |
de5b9bb9 | 3879 | |
20a6ec49 | 3880 | if (i386_fp_regnum_p (get_frame_arch (frame), regnum)) |
c6ba6f0d | 3881 | { |
d532c08f MK |
3882 | i387_value_to_register (frame, regnum, type, from); |
3883 | return; | |
3884 | } | |
3d261580 | 3885 | |
fd35795f | 3886 | /* Write a value spread across multiple registers. */ |
de5b9bb9 MK |
3887 | |
3888 | gdb_assert (len > 4 && len % 4 == 0); | |
ff2e87ac | 3889 | |
de5b9bb9 MK |
3890 | while (len > 0) |
3891 | { | |
3892 | gdb_assert (regnum != -1); | |
875f8d0e | 3893 | gdb_assert (register_size (get_frame_arch (frame), regnum) == 4); |
d532c08f | 3894 | |
42835c2b | 3895 | put_frame_register (frame, regnum, from); |
de5b9bb9 MK |
3896 | regnum = i386_next_regnum (regnum); |
3897 | len -= 4; | |
42835c2b | 3898 | from += 4; |
de5b9bb9 | 3899 | } |
ac27f131 | 3900 | } |
ff2e87ac | 3901 | \f |
7fdafb5a MK |
3902 | /* Supply register REGNUM from the buffer specified by GREGS and LEN |
3903 | in the general-purpose register set REGSET to register cache | |
3904 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
ff2e87ac | 3905 | |
20187ed5 | 3906 | void |
473f17b0 MK |
3907 | i386_supply_gregset (const struct regset *regset, struct regcache *regcache, |
3908 | int regnum, const void *gregs, size_t len) | |
3909 | { | |
ac7936df | 3910 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3911 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
9a3c8263 | 3912 | const gdb_byte *regs = (const gdb_byte *) gregs; |
473f17b0 MK |
3913 | int i; |
3914 | ||
1528345d | 3915 | gdb_assert (len >= tdep->sizeof_gregset); |
473f17b0 MK |
3916 | |
3917 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3918 | { | |
3919 | if ((regnum == i || regnum == -1) | |
3920 | && tdep->gregset_reg_offset[i] != -1) | |
73e1c03f | 3921 | regcache->raw_supply (i, regs + tdep->gregset_reg_offset[i]); |
473f17b0 MK |
3922 | } |
3923 | } | |
3924 | ||
7fdafb5a MK |
3925 | /* Collect register REGNUM from the register cache REGCACHE and store |
3926 | it in the buffer specified by GREGS and LEN as described by the | |
3927 | general-purpose register set REGSET. If REGNUM is -1, do this for | |
3928 | all registers in REGSET. */ | |
3929 | ||
ecc37a5a | 3930 | static void |
7fdafb5a MK |
3931 | i386_collect_gregset (const struct regset *regset, |
3932 | const struct regcache *regcache, | |
3933 | int regnum, void *gregs, size_t len) | |
3934 | { | |
ac7936df | 3935 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3936 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
9a3c8263 | 3937 | gdb_byte *regs = (gdb_byte *) gregs; |
7fdafb5a MK |
3938 | int i; |
3939 | ||
1528345d | 3940 | gdb_assert (len >= tdep->sizeof_gregset); |
7fdafb5a MK |
3941 | |
3942 | for (i = 0; i < tdep->gregset_num_regs; i++) | |
3943 | { | |
3944 | if ((regnum == i || regnum == -1) | |
3945 | && tdep->gregset_reg_offset[i] != -1) | |
34a79281 | 3946 | regcache->raw_collect (i, regs + tdep->gregset_reg_offset[i]); |
7fdafb5a MK |
3947 | } |
3948 | } | |
3949 | ||
3950 | /* Supply register REGNUM from the buffer specified by FPREGS and LEN | |
3951 | in the floating-point register set REGSET to register cache | |
3952 | REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ | |
473f17b0 MK |
3953 | |
3954 | static void | |
3955 | i386_supply_fpregset (const struct regset *regset, struct regcache *regcache, | |
3956 | int regnum, const void *fpregs, size_t len) | |
3957 | { | |
ac7936df | 3958 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3959 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
473f17b0 | 3960 | |
66a72d25 MK |
3961 | if (len == I387_SIZEOF_FXSAVE) |
3962 | { | |
3963 | i387_supply_fxsave (regcache, regnum, fpregs); | |
3964 | return; | |
3965 | } | |
3966 | ||
1528345d | 3967 | gdb_assert (len >= tdep->sizeof_fpregset); |
473f17b0 MK |
3968 | i387_supply_fsave (regcache, regnum, fpregs); |
3969 | } | |
8446b36a | 3970 | |
2f305df1 MK |
3971 | /* Collect register REGNUM from the register cache REGCACHE and store |
3972 | it in the buffer specified by FPREGS and LEN as described by the | |
3973 | floating-point register set REGSET. If REGNUM is -1, do this for | |
3974 | all registers in REGSET. */ | |
7fdafb5a MK |
3975 | |
3976 | static void | |
3977 | i386_collect_fpregset (const struct regset *regset, | |
3978 | const struct regcache *regcache, | |
3979 | int regnum, void *fpregs, size_t len) | |
3980 | { | |
ac7936df | 3981 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 3982 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
7fdafb5a MK |
3983 | |
3984 | if (len == I387_SIZEOF_FXSAVE) | |
3985 | { | |
3986 | i387_collect_fxsave (regcache, regnum, fpregs); | |
3987 | return; | |
3988 | } | |
3989 | ||
1528345d | 3990 | gdb_assert (len >= tdep->sizeof_fpregset); |
7fdafb5a MK |
3991 | i387_collect_fsave (regcache, regnum, fpregs); |
3992 | } | |
3993 | ||
ecc37a5a AA |
3994 | /* Register set definitions. */ |
3995 | ||
3996 | const struct regset i386_gregset = | |
3997 | { | |
3998 | NULL, i386_supply_gregset, i386_collect_gregset | |
3999 | }; | |
4000 | ||
8f0435f7 | 4001 | const struct regset i386_fpregset = |
ecc37a5a AA |
4002 | { |
4003 | NULL, i386_supply_fpregset, i386_collect_fpregset | |
4004 | }; | |
4005 | ||
490496c3 | 4006 | /* Default iterator over core file register note sections. */ |
8446b36a | 4007 | |
490496c3 AA |
4008 | void |
4009 | i386_iterate_over_regset_sections (struct gdbarch *gdbarch, | |
4010 | iterate_over_regset_sections_cb *cb, | |
4011 | void *cb_data, | |
4012 | const struct regcache *regcache) | |
8446b36a | 4013 | { |
08106042 | 4014 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
8446b36a | 4015 | |
a616bb94 AH |
4016 | cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, &i386_gregset, NULL, |
4017 | cb_data); | |
490496c3 | 4018 | if (tdep->sizeof_fpregset) |
a616bb94 AH |
4019 | cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, |
4020 | NULL, cb_data); | |
8446b36a | 4021 | } |
473f17b0 | 4022 | \f |
fc338970 | 4023 | |
fc338970 | 4024 | /* Stuff for WIN32 PE style DLL's but is pretty generic really. */ |
c906108c SS |
4025 | |
4026 | CORE_ADDR | |
bd2b40ac | 4027 | i386_pe_skip_trampoline_code (frame_info_ptr frame, |
e17a4113 | 4028 | CORE_ADDR pc, char *name) |
c906108c | 4029 | { |
e17a4113 UW |
4030 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4031 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
4032 | ||
4033 | /* jmp *(dest) */ | |
4034 | if (pc && read_memory_unsigned_integer (pc, 2, byte_order) == 0x25ff) | |
c906108c | 4035 | { |
e17a4113 UW |
4036 | unsigned long indirect = |
4037 | read_memory_unsigned_integer (pc + 2, 4, byte_order); | |
c906108c | 4038 | struct minimal_symbol *indsym = |
7cbd4a93 | 4039 | indirect ? lookup_minimal_symbol_by_pc (indirect).minsym : 0; |
c9d95fa3 | 4040 | const char *symname = indsym ? indsym->linkage_name () : 0; |
c906108c | 4041 | |
c5aa993b | 4042 | if (symname) |
c906108c | 4043 | { |
61012eef GB |
4044 | if (startswith (symname, "__imp_") |
4045 | || startswith (symname, "_imp_")) | |
e17a4113 UW |
4046 | return name ? 1 : |
4047 | read_memory_unsigned_integer (indirect, 4, byte_order); | |
c906108c SS |
4048 | } |
4049 | } | |
fc338970 | 4050 | return 0; /* Not a trampoline. */ |
c906108c | 4051 | } |
fc338970 MK |
4052 | \f |
4053 | ||
10458914 DJ |
4054 | /* Return whether the THIS_FRAME corresponds to a sigtramp |
4055 | routine. */ | |
8201327c | 4056 | |
4bd207ef | 4057 | int |
bd2b40ac | 4058 | i386_sigtramp_p (frame_info_ptr this_frame) |
8201327c | 4059 | { |
10458914 | 4060 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 4061 | const char *name; |
911bc6ee MK |
4062 | |
4063 | find_pc_partial_function (pc, &name, NULL, NULL); | |
8201327c MK |
4064 | return (name && strcmp ("_sigtramp", name) == 0); |
4065 | } | |
4066 | \f | |
4067 | ||
fc338970 MK |
4068 | /* We have two flavours of disassembly. The machinery on this page |
4069 | deals with switching between those. */ | |
c906108c SS |
4070 | |
4071 | static int | |
a89aa300 | 4072 | i386_print_insn (bfd_vma pc, struct disassemble_info *info) |
c906108c | 4073 | { |
5e3397bb MK |
4074 | gdb_assert (disassembly_flavor == att_flavor |
4075 | || disassembly_flavor == intel_flavor); | |
4076 | ||
f995bbe8 | 4077 | info->disassembler_options = disassembly_flavor; |
5e3397bb | 4078 | |
6394c606 | 4079 | return default_print_insn (pc, info); |
7a292a7a | 4080 | } |
fc338970 | 4081 | \f |
3ce1502b | 4082 | |
8201327c MK |
4083 | /* There are a few i386 architecture variants that differ only |
4084 | slightly from the generic i386 target. For now, we don't give them | |
4085 | their own source file, but include them here. As a consequence, | |
4086 | they'll always be included. */ | |
3ce1502b | 4087 | |
8201327c | 4088 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4089 | |
10458914 DJ |
4090 | /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp |
4091 | routine. */ | |
911bc6ee | 4092 | |
8201327c | 4093 | static int |
bd2b40ac | 4094 | i386_svr4_sigtramp_p (frame_info_ptr this_frame) |
d2a7c97a | 4095 | { |
10458914 | 4096 | CORE_ADDR pc = get_frame_pc (this_frame); |
2c02bd72 | 4097 | const char *name; |
911bc6ee | 4098 | |
05b4bd79 | 4099 | /* The origin of these symbols is currently unknown. */ |
911bc6ee | 4100 | find_pc_partial_function (pc, &name, NULL, NULL); |
8201327c | 4101 | return (name && (strcmp ("_sigreturn", name) == 0 |
8201327c MK |
4102 | || strcmp ("sigvechandler", name) == 0)); |
4103 | } | |
d2a7c97a | 4104 | |
10458914 DJ |
4105 | /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the |
4106 | address of the associated sigcontext (ucontext) structure. */ | |
3ce1502b | 4107 | |
3a1e71e3 | 4108 | static CORE_ADDR |
bd2b40ac | 4109 | i386_svr4_sigcontext_addr (frame_info_ptr this_frame) |
8201327c | 4110 | { |
e17a4113 UW |
4111 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
4112 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
63c0089f | 4113 | gdb_byte buf[4]; |
acd5c798 | 4114 | CORE_ADDR sp; |
3ce1502b | 4115 | |
10458914 | 4116 | get_frame_register (this_frame, I386_ESP_REGNUM, buf); |
e17a4113 | 4117 | sp = extract_unsigned_integer (buf, 4, byte_order); |
21d0e8a4 | 4118 | |
e17a4113 | 4119 | return read_memory_unsigned_integer (sp + 8, 4, byte_order); |
8201327c | 4120 | } |
55aa24fb SDJ |
4121 | |
4122 | \f | |
4123 | ||
4124 | /* Implementation of `gdbarch_stap_is_single_operand', as defined in | |
4125 | gdbarch.h. */ | |
4126 | ||
4127 | int | |
4128 | i386_stap_is_single_operand (struct gdbarch *gdbarch, const char *s) | |
4129 | { | |
4130 | return (*s == '$' /* Literal number. */ | |
4131 | || (isdigit (*s) && s[1] == '(' && s[2] == '%') /* Displacement. */ | |
4132 | || (*s == '(' && s[1] == '%') /* Register indirection. */ | |
4133 | || (*s == '%' && isalpha (s[1]))); /* Register access. */ | |
4134 | } | |
4135 | ||
5acfdbae SDJ |
4136 | /* Helper function for i386_stap_parse_special_token. |
4137 | ||
4138 | This function parses operands of the form `-8+3+1(%rbp)', which | |
4139 | must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'. | |
4140 | ||
af2d9bee | 4141 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4142 | otherwise. */ |
4143 | ||
4c5e7a93 | 4144 | static expr::operation_up |
5acfdbae SDJ |
4145 | i386_stap_parse_special_token_triplet (struct gdbarch *gdbarch, |
4146 | struct stap_parse_info *p) | |
4147 | { | |
4148 | const char *s = p->arg; | |
4149 | ||
4150 | if (isdigit (*s) || *s == '-' || *s == '+') | |
4151 | { | |
af2d9bee | 4152 | bool got_minus[3]; |
5acfdbae SDJ |
4153 | int i; |
4154 | long displacements[3]; | |
4155 | const char *start; | |
5acfdbae | 4156 | int len; |
5acfdbae SDJ |
4157 | char *endp; |
4158 | ||
af2d9bee | 4159 | got_minus[0] = false; |
5acfdbae SDJ |
4160 | if (*s == '+') |
4161 | ++s; | |
4162 | else if (*s == '-') | |
4163 | { | |
4164 | ++s; | |
af2d9bee | 4165 | got_minus[0] = true; |
5acfdbae SDJ |
4166 | } |
4167 | ||
d7b30f67 | 4168 | if (!isdigit ((unsigned char) *s)) |
4c5e7a93 | 4169 | return {}; |
d7b30f67 | 4170 | |
5acfdbae SDJ |
4171 | displacements[0] = strtol (s, &endp, 10); |
4172 | s = endp; | |
4173 | ||
4174 | if (*s != '+' && *s != '-') | |
4175 | { | |
4176 | /* We are not dealing with a triplet. */ | |
4c5e7a93 | 4177 | return {}; |
5acfdbae SDJ |
4178 | } |
4179 | ||
af2d9bee | 4180 | got_minus[1] = false; |
5acfdbae SDJ |
4181 | if (*s == '+') |
4182 | ++s; | |
4183 | else | |
4184 | { | |
4185 | ++s; | |
af2d9bee | 4186 | got_minus[1] = true; |
5acfdbae SDJ |
4187 | } |
4188 | ||
d7b30f67 | 4189 | if (!isdigit ((unsigned char) *s)) |
4c5e7a93 | 4190 | return {}; |
d7b30f67 | 4191 | |
5acfdbae SDJ |
4192 | displacements[1] = strtol (s, &endp, 10); |
4193 | s = endp; | |
4194 | ||
4195 | if (*s != '+' && *s != '-') | |
4196 | { | |
4197 | /* We are not dealing with a triplet. */ | |
4c5e7a93 | 4198 | return {}; |
5acfdbae SDJ |
4199 | } |
4200 | ||
af2d9bee | 4201 | got_minus[2] = false; |
5acfdbae SDJ |
4202 | if (*s == '+') |
4203 | ++s; | |
4204 | else | |
4205 | { | |
4206 | ++s; | |
af2d9bee | 4207 | got_minus[2] = true; |
5acfdbae SDJ |
4208 | } |
4209 | ||
d7b30f67 | 4210 | if (!isdigit ((unsigned char) *s)) |
4c5e7a93 | 4211 | return {}; |
d7b30f67 | 4212 | |
5acfdbae SDJ |
4213 | displacements[2] = strtol (s, &endp, 10); |
4214 | s = endp; | |
4215 | ||
4216 | if (*s != '(' || s[1] != '%') | |
4c5e7a93 | 4217 | return {}; |
5acfdbae SDJ |
4218 | |
4219 | s += 2; | |
4220 | start = s; | |
4221 | ||
4222 | while (isalnum (*s)) | |
4223 | ++s; | |
4224 | ||
4225 | if (*s++ != ')') | |
4c5e7a93 | 4226 | return {}; |
5acfdbae | 4227 | |
d7b30f67 | 4228 | len = s - start - 1; |
4c5e7a93 | 4229 | std::string regname (start, len); |
5acfdbae | 4230 | |
4c5e7a93 | 4231 | if (user_reg_map_name_to_regnum (gdbarch, regname.c_str (), len) == -1) |
5acfdbae | 4232 | error (_("Invalid register name `%s' on expression `%s'."), |
4c5e7a93 | 4233 | regname.c_str (), p->saved_arg); |
5acfdbae | 4234 | |
4c5e7a93 | 4235 | LONGEST value = 0; |
5acfdbae SDJ |
4236 | for (i = 0; i < 3; i++) |
4237 | { | |
4c5e7a93 | 4238 | LONGEST this_val = displacements[i]; |
5acfdbae | 4239 | if (got_minus[i]) |
4c5e7a93 TT |
4240 | this_val = -this_val; |
4241 | value += this_val; | |
5acfdbae SDJ |
4242 | } |
4243 | ||
4c5e7a93 | 4244 | p->arg = s; |
5acfdbae | 4245 | |
4c5e7a93 | 4246 | using namespace expr; |
5acfdbae | 4247 | |
4c5e7a93 TT |
4248 | struct type *long_type = builtin_type (gdbarch)->builtin_long; |
4249 | operation_up offset | |
4250 | = make_operation<long_const_operation> (long_type, value); | |
5acfdbae | 4251 | |
4c5e7a93 TT |
4252 | operation_up reg |
4253 | = make_operation<register_operation> (std::move (regname)); | |
4254 | struct type *void_ptr = builtin_type (gdbarch)->builtin_data_ptr; | |
4255 | reg = make_operation<unop_cast_operation> (std::move (reg), void_ptr); | |
5acfdbae | 4256 | |
4c5e7a93 TT |
4257 | operation_up sum |
4258 | = make_operation<add_operation> (std::move (reg), std::move (offset)); | |
4259 | struct type *arg_ptr_type = lookup_pointer_type (p->arg_type); | |
4260 | sum = make_operation<unop_cast_operation> (std::move (sum), | |
4261 | arg_ptr_type); | |
4262 | return make_operation<unop_ind_operation> (std::move (sum)); | |
5acfdbae SDJ |
4263 | } |
4264 | ||
4c5e7a93 | 4265 | return {}; |
5acfdbae SDJ |
4266 | } |
4267 | ||
4268 | /* Helper function for i386_stap_parse_special_token. | |
4269 | ||
4270 | This function parses operands of the form `register base + | |
4271 | (register index * size) + offset', as represented in | |
4272 | `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4273 | ||
af2d9bee | 4274 | Return true if the operand was parsed successfully, false |
5acfdbae SDJ |
4275 | otherwise. */ |
4276 | ||
4c5e7a93 | 4277 | static expr::operation_up |
5acfdbae SDJ |
4278 | i386_stap_parse_special_token_three_arg_disp (struct gdbarch *gdbarch, |
4279 | struct stap_parse_info *p) | |
4280 | { | |
4281 | const char *s = p->arg; | |
4282 | ||
4283 | if (isdigit (*s) || *s == '(' || *s == '-' || *s == '+') | |
4284 | { | |
af2d9bee | 4285 | bool offset_minus = false; |
5acfdbae | 4286 | long offset = 0; |
af2d9bee | 4287 | bool size_minus = false; |
5acfdbae SDJ |
4288 | long size = 0; |
4289 | const char *start; | |
5acfdbae | 4290 | int len_base; |
5acfdbae | 4291 | int len_index; |
5acfdbae SDJ |
4292 | |
4293 | if (*s == '+') | |
4294 | ++s; | |
4295 | else if (*s == '-') | |
4296 | { | |
4297 | ++s; | |
af2d9bee | 4298 | offset_minus = true; |
5acfdbae SDJ |
4299 | } |
4300 | ||
4301 | if (offset_minus && !isdigit (*s)) | |
4c5e7a93 | 4302 | return {}; |
5acfdbae SDJ |
4303 | |
4304 | if (isdigit (*s)) | |
4305 | { | |
4306 | char *endp; | |
4307 | ||
4308 | offset = strtol (s, &endp, 10); | |
4309 | s = endp; | |
4310 | } | |
4311 | ||
4312 | if (*s != '(' || s[1] != '%') | |
4c5e7a93 | 4313 | return {}; |
5acfdbae SDJ |
4314 | |
4315 | s += 2; | |
4316 | start = s; | |
4317 | ||
4318 | while (isalnum (*s)) | |
4319 | ++s; | |
4320 | ||
4321 | if (*s != ',' || s[1] != '%') | |
4c5e7a93 | 4322 | return {}; |
5acfdbae SDJ |
4323 | |
4324 | len_base = s - start; | |
4c5e7a93 | 4325 | std::string base (start, len_base); |
5acfdbae | 4326 | |
4c5e7a93 | 4327 | if (user_reg_map_name_to_regnum (gdbarch, base.c_str (), len_base) == -1) |
5acfdbae | 4328 | error (_("Invalid register name `%s' on expression `%s'."), |
4c5e7a93 | 4329 | base.c_str (), p->saved_arg); |
5acfdbae SDJ |
4330 | |
4331 | s += 2; | |
4332 | start = s; | |
4333 | ||
4334 | while (isalnum (*s)) | |
4335 | ++s; | |
4336 | ||
4337 | len_index = s - start; | |
4c5e7a93 | 4338 | std::string index (start, len_index); |
5acfdbae | 4339 | |
4c5e7a93 TT |
4340 | if (user_reg_map_name_to_regnum (gdbarch, index.c_str (), |
4341 | len_index) == -1) | |
5acfdbae | 4342 | error (_("Invalid register name `%s' on expression `%s'."), |
4c5e7a93 | 4343 | index.c_str (), p->saved_arg); |
5acfdbae SDJ |
4344 | |
4345 | if (*s != ',' && *s != ')') | |
4c5e7a93 | 4346 | return {}; |
5acfdbae SDJ |
4347 | |
4348 | if (*s == ',') | |
4349 | { | |
4350 | char *endp; | |
4351 | ||
4352 | ++s; | |
4353 | if (*s == '+') | |
4354 | ++s; | |
4355 | else if (*s == '-') | |
4356 | { | |
4357 | ++s; | |
af2d9bee | 4358 | size_minus = true; |
5acfdbae SDJ |
4359 | } |
4360 | ||
4361 | size = strtol (s, &endp, 10); | |
4362 | s = endp; | |
4363 | ||
4364 | if (*s != ')') | |
4c5e7a93 | 4365 | return {}; |
5acfdbae SDJ |
4366 | } |
4367 | ||
4368 | ++s; | |
4c5e7a93 TT |
4369 | p->arg = s; |
4370 | ||
4371 | using namespace expr; | |
4372 | ||
4373 | struct type *long_type = builtin_type (gdbarch)->builtin_long; | |
4374 | operation_up reg = make_operation<register_operation> (std::move (base)); | |
5acfdbae | 4375 | |
4c5e7a93 | 4376 | if (offset != 0) |
5acfdbae | 4377 | { |
5acfdbae | 4378 | if (offset_minus) |
4c5e7a93 TT |
4379 | offset = -offset; |
4380 | operation_up value | |
4381 | = make_operation<long_const_operation> (long_type, offset); | |
4382 | reg = make_operation<add_operation> (std::move (reg), | |
4383 | std::move (value)); | |
5acfdbae SDJ |
4384 | } |
4385 | ||
4c5e7a93 TT |
4386 | operation_up ind_reg |
4387 | = make_operation<register_operation> (std::move (index)); | |
5acfdbae | 4388 | |
4c5e7a93 | 4389 | if (size != 0) |
5acfdbae | 4390 | { |
5acfdbae | 4391 | if (size_minus) |
4c5e7a93 TT |
4392 | size = -size; |
4393 | operation_up value | |
4394 | = make_operation<long_const_operation> (long_type, size); | |
4395 | ind_reg = make_operation<mul_operation> (std::move (ind_reg), | |
4396 | std::move (value)); | |
5acfdbae SDJ |
4397 | } |
4398 | ||
4c5e7a93 TT |
4399 | operation_up sum |
4400 | = make_operation<add_operation> (std::move (reg), | |
4401 | std::move (ind_reg)); | |
5acfdbae | 4402 | |
4c5e7a93 TT |
4403 | struct type *arg_ptr_type = lookup_pointer_type (p->arg_type); |
4404 | sum = make_operation<unop_cast_operation> (std::move (sum), | |
4405 | arg_ptr_type); | |
4406 | return make_operation<unop_ind_operation> (std::move (sum)); | |
5acfdbae SDJ |
4407 | } |
4408 | ||
4c5e7a93 | 4409 | return {}; |
5acfdbae SDJ |
4410 | } |
4411 | ||
55aa24fb SDJ |
4412 | /* Implementation of `gdbarch_stap_parse_special_token', as defined in |
4413 | gdbarch.h. */ | |
4414 | ||
4c5e7a93 | 4415 | expr::operation_up |
55aa24fb SDJ |
4416 | i386_stap_parse_special_token (struct gdbarch *gdbarch, |
4417 | struct stap_parse_info *p) | |
4418 | { | |
55aa24fb SDJ |
4419 | /* The special tokens to be parsed here are: |
4420 | ||
4421 | - `register base + (register index * size) + offset', as represented | |
4422 | in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'. | |
4423 | ||
4424 | - Operands of the form `-8+3+1(%rbp)', which must be interpreted as | |
4425 | `*(-8 + 3 - 1 + (void *) $eax)'. */ | |
4426 | ||
4c5e7a93 TT |
4427 | expr::operation_up result |
4428 | = i386_stap_parse_special_token_triplet (gdbarch, p); | |
55aa24fb | 4429 | |
4c5e7a93 TT |
4430 | if (result == nullptr) |
4431 | result = i386_stap_parse_special_token_three_arg_disp (gdbarch, p); | |
55aa24fb | 4432 | |
4c5e7a93 | 4433 | return result; |
55aa24fb SDJ |
4434 | } |
4435 | ||
7d7571f0 SDJ |
4436 | /* Implementation of 'gdbarch_stap_adjust_register', as defined in |
4437 | gdbarch.h. */ | |
4438 | ||
6b78c3f8 | 4439 | static std::string |
7d7571f0 | 4440 | i386_stap_adjust_register (struct gdbarch *gdbarch, struct stap_parse_info *p, |
6b78c3f8 | 4441 | const std::string ®name, int regnum) |
7d7571f0 SDJ |
4442 | { |
4443 | static const std::unordered_set<std::string> reg_assoc | |
4444 | = { "ax", "bx", "cx", "dx", | |
4445 | "si", "di", "bp", "sp" }; | |
4446 | ||
6b78c3f8 AB |
4447 | /* If we are dealing with a register whose size is less than the size |
4448 | specified by the "[-]N@" prefix, and it is one of the registers that | |
4449 | we know has an extended variant available, then use the extended | |
4450 | version of the register instead. */ | |
df86565b | 4451 | if (register_size (gdbarch, regnum) < p->arg_type->length () |
6b78c3f8 AB |
4452 | && reg_assoc.find (regname) != reg_assoc.end ()) |
4453 | return "e" + regname; | |
7d7571f0 | 4454 | |
6b78c3f8 AB |
4455 | /* Otherwise, just use the requested register. */ |
4456 | return regname; | |
7d7571f0 SDJ |
4457 | } |
4458 | ||
8201327c | 4459 | \f |
3ce1502b | 4460 | |
ac04f72b TT |
4461 | /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always |
4462 | also supplies -m64 or -m32 by gdbarch_gcc_target_options. */ | |
4463 | ||
4464 | static const char * | |
4465 | i386_gnu_triplet_regexp (struct gdbarch *gdbarch) | |
4466 | { | |
4467 | return "(x86_64|i.86)"; | |
4468 | } | |
4469 | ||
4470 | \f | |
4471 | ||
1d509aa6 MM |
4472 | /* Implement the "in_indirect_branch_thunk" gdbarch function. */ |
4473 | ||
4474 | static bool | |
4475 | i386_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) | |
4476 | { | |
4477 | return x86_in_indirect_branch_thunk (pc, i386_register_names, | |
4478 | I386_EAX_REGNUM, I386_EIP_REGNUM); | |
4479 | } | |
4480 | ||
8201327c | 4481 | /* Generic ELF. */ |
d2a7c97a | 4482 | |
8201327c MK |
4483 | void |
4484 | i386_elf_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4485 | { | |
05c0465e SDJ |
4486 | static const char *const stap_integer_prefixes[] = { "$", NULL }; |
4487 | static const char *const stap_register_prefixes[] = { "%", NULL }; | |
4488 | static const char *const stap_register_indirection_prefixes[] = { "(", | |
4489 | NULL }; | |
4490 | static const char *const stap_register_indirection_suffixes[] = { ")", | |
4491 | NULL }; | |
4492 | ||
c4fc7f1b MK |
4493 | /* We typically use stabs-in-ELF with the SVR4 register numbering. */ |
4494 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_svr4_reg_to_regnum); | |
55aa24fb SDJ |
4495 | |
4496 | /* Registering SystemTap handlers. */ | |
05c0465e SDJ |
4497 | set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); |
4498 | set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); | |
4499 | set_gdbarch_stap_register_indirection_prefixes (gdbarch, | |
4500 | stap_register_indirection_prefixes); | |
4501 | set_gdbarch_stap_register_indirection_suffixes (gdbarch, | |
4502 | stap_register_indirection_suffixes); | |
55aa24fb SDJ |
4503 | set_gdbarch_stap_is_single_operand (gdbarch, |
4504 | i386_stap_is_single_operand); | |
4505 | set_gdbarch_stap_parse_special_token (gdbarch, | |
4506 | i386_stap_parse_special_token); | |
7d7571f0 SDJ |
4507 | set_gdbarch_stap_adjust_register (gdbarch, |
4508 | i386_stap_adjust_register); | |
1d509aa6 MM |
4509 | |
4510 | set_gdbarch_in_indirect_branch_thunk (gdbarch, | |
4511 | i386_in_indirect_branch_thunk); | |
8201327c | 4512 | } |
3ce1502b | 4513 | |
8201327c | 4514 | /* System V Release 4 (SVR4). */ |
3ce1502b | 4515 | |
8201327c MK |
4516 | void |
4517 | i386_svr4_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) | |
4518 | { | |
08106042 | 4519 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
3ce1502b | 4520 | |
8201327c MK |
4521 | /* System V Release 4 uses ELF. */ |
4522 | i386_elf_init_abi (info, gdbarch); | |
3ce1502b | 4523 | |
dfe01d39 | 4524 | /* System V Release 4 has shared libraries. */ |
dfe01d39 MK |
4525 | set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); |
4526 | ||
911bc6ee | 4527 | tdep->sigtramp_p = i386_svr4_sigtramp_p; |
21d0e8a4 | 4528 | tdep->sigcontext_addr = i386_svr4_sigcontext_addr; |
acd5c798 MK |
4529 | tdep->sc_pc_offset = 36 + 14 * 4; |
4530 | tdep->sc_sp_offset = 36 + 17 * 4; | |
3ce1502b | 4531 | |
8201327c | 4532 | tdep->jb_pc_offset = 20; |
3ce1502b MK |
4533 | } |
4534 | ||
8201327c | 4535 | \f |
2acceee2 | 4536 | |
38c968cf AC |
4537 | /* i386 register groups. In addition to the normal groups, add "mmx" |
4538 | and "sse". */ | |
4539 | ||
e7fe1011 AB |
4540 | static const reggroup *i386_sse_reggroup; |
4541 | static const reggroup *i386_mmx_reggroup; | |
38c968cf AC |
4542 | |
4543 | static void | |
4544 | i386_init_reggroups (void) | |
4545 | { | |
4546 | i386_sse_reggroup = reggroup_new ("sse", USER_REGGROUP); | |
4547 | i386_mmx_reggroup = reggroup_new ("mmx", USER_REGGROUP); | |
4548 | } | |
4549 | ||
4550 | static void | |
4551 | i386_add_reggroups (struct gdbarch *gdbarch) | |
4552 | { | |
4553 | reggroup_add (gdbarch, i386_sse_reggroup); | |
4554 | reggroup_add (gdbarch, i386_mmx_reggroup); | |
38c968cf AC |
4555 | } |
4556 | ||
4557 | int | |
4558 | i386_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 4559 | const struct reggroup *group) |
38c968cf | 4560 | { |
08106042 | 4561 | const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
c131fcee | 4562 | int fp_regnum_p, mmx_regnum_p, xmm_regnum_p, mxcsr_regnum_p, |
01f9f808 | 4563 | ymm_regnum_p, ymmh_regnum_p, ymm_avx512_regnum_p, ymmh_avx512_regnum_p, |
798a7429 SM |
4564 | bndr_regnum_p, bnd_regnum_p, zmm_regnum_p, zmmh_regnum_p, |
4565 | mpx_ctrl_regnum_p, xmm_avx512_regnum_p, | |
51547df6 | 4566 | avx512_p, avx_p, sse_p, pkru_regnum_p; |
acd5c798 | 4567 | |
1ba53b71 L |
4568 | /* Don't include pseudo registers, except for MMX, in any register |
4569 | groups. */ | |
c131fcee | 4570 | if (i386_byte_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4571 | return 0; |
4572 | ||
c131fcee | 4573 | if (i386_word_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4574 | return 0; |
4575 | ||
c131fcee | 4576 | if (i386_dword_regnum_p (gdbarch, regnum)) |
1ba53b71 L |
4577 | return 0; |
4578 | ||
4579 | mmx_regnum_p = i386_mmx_regnum_p (gdbarch, regnum); | |
38c968cf AC |
4580 | if (group == i386_mmx_reggroup) |
4581 | return mmx_regnum_p; | |
1ba53b71 | 4582 | |
51547df6 | 4583 | pkru_regnum_p = i386_pkru_regnum_p(gdbarch, regnum); |
c131fcee | 4584 | xmm_regnum_p = i386_xmm_regnum_p (gdbarch, regnum); |
01f9f808 | 4585 | xmm_avx512_regnum_p = i386_xmm_avx512_regnum_p (gdbarch, regnum); |
c131fcee | 4586 | mxcsr_regnum_p = i386_mxcsr_regnum_p (gdbarch, regnum); |
38c968cf | 4587 | if (group == i386_sse_reggroup) |
01f9f808 | 4588 | return xmm_regnum_p || xmm_avx512_regnum_p || mxcsr_regnum_p; |
c131fcee L |
4589 | |
4590 | ymm_regnum_p = i386_ymm_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4591 | ymm_avx512_regnum_p = i386_ymm_avx512_regnum_p (gdbarch, regnum); |
4592 | zmm_regnum_p = i386_zmm_regnum_p (gdbarch, regnum); | |
4593 | ||
22049425 MS |
4594 | avx512_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
4595 | == X86_XSTATE_AVX_AVX512_MASK); | |
4596 | avx_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) | |
df7e5265 | 4597 | == X86_XSTATE_AVX_MASK) && !avx512_p; |
22049425 | 4598 | sse_p = ((tdep->xcr0 & X86_XSTATE_AVX_AVX512_MASK) |
df7e5265 | 4599 | == X86_XSTATE_SSE_MASK) && !avx512_p && ! avx_p; |
01f9f808 | 4600 | |
38c968cf | 4601 | if (group == vector_reggroup) |
c131fcee | 4602 | return (mmx_regnum_p |
01f9f808 MS |
4603 | || (zmm_regnum_p && avx512_p) |
4604 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && avx_p) | |
4605 | || ((xmm_regnum_p || xmm_avx512_regnum_p) && sse_p) | |
4606 | || mxcsr_regnum_p); | |
1ba53b71 L |
4607 | |
4608 | fp_regnum_p = (i386_fp_regnum_p (gdbarch, regnum) | |
4609 | || i386_fpc_regnum_p (gdbarch, regnum)); | |
38c968cf AC |
4610 | if (group == float_reggroup) |
4611 | return fp_regnum_p; | |
1ba53b71 | 4612 | |
c131fcee L |
4613 | /* For "info reg all", don't include upper YMM registers nor XMM |
4614 | registers when AVX is supported. */ | |
4615 | ymmh_regnum_p = i386_ymmh_regnum_p (gdbarch, regnum); | |
01f9f808 MS |
4616 | ymmh_avx512_regnum_p = i386_ymmh_avx512_regnum_p (gdbarch, regnum); |
4617 | zmmh_regnum_p = i386_zmmh_regnum_p (gdbarch, regnum); | |
c131fcee | 4618 | if (group == all_reggroup |
01f9f808 MS |
4619 | && (((xmm_regnum_p || xmm_avx512_regnum_p) && !sse_p) |
4620 | || ((ymm_regnum_p || ymm_avx512_regnum_p) && !avx_p) | |
4621 | || ymmh_regnum_p | |
4622 | || ymmh_avx512_regnum_p | |
4623 | || zmmh_regnum_p)) | |
c131fcee L |
4624 | return 0; |
4625 | ||
1dbcd68c WT |
4626 | bnd_regnum_p = i386_bnd_regnum_p (gdbarch, regnum); |
4627 | if (group == all_reggroup | |
df7e5265 | 4628 | && ((bnd_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4629 | return bnd_regnum_p; |
4630 | ||
4631 | bndr_regnum_p = i386_bndr_regnum_p (gdbarch, regnum); | |
4632 | if (group == all_reggroup | |
df7e5265 | 4633 | && ((bndr_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4634 | return 0; |
4635 | ||
4636 | mpx_ctrl_regnum_p = i386_mpx_ctrl_regnum_p (gdbarch, regnum); | |
4637 | if (group == all_reggroup | |
df7e5265 | 4638 | && ((mpx_ctrl_regnum_p && (tdep->xcr0 & X86_XSTATE_MPX_MASK)))) |
1dbcd68c WT |
4639 | return mpx_ctrl_regnum_p; |
4640 | ||
38c968cf | 4641 | if (group == general_reggroup) |
1ba53b71 L |
4642 | return (!fp_regnum_p |
4643 | && !mmx_regnum_p | |
c131fcee L |
4644 | && !mxcsr_regnum_p |
4645 | && !xmm_regnum_p | |
01f9f808 | 4646 | && !xmm_avx512_regnum_p |
c131fcee | 4647 | && !ymm_regnum_p |
1dbcd68c | 4648 | && !ymmh_regnum_p |
01f9f808 MS |
4649 | && !ymm_avx512_regnum_p |
4650 | && !ymmh_avx512_regnum_p | |
1dbcd68c WT |
4651 | && !bndr_regnum_p |
4652 | && !bnd_regnum_p | |
01f9f808 MS |
4653 | && !mpx_ctrl_regnum_p |
4654 | && !zmm_regnum_p | |
51547df6 MS |
4655 | && !zmmh_regnum_p |
4656 | && !pkru_regnum_p); | |
acd5c798 | 4657 | |
38c968cf AC |
4658 | return default_register_reggroup_p (gdbarch, regnum, group); |
4659 | } | |
38c968cf | 4660 | \f |
acd5c798 | 4661 | |
f837910f MK |
4662 | /* Get the ARGIth function argument for the current function. */ |
4663 | ||
42c466d7 | 4664 | static CORE_ADDR |
bd2b40ac | 4665 | i386_fetch_pointer_argument (frame_info_ptr frame, int argi, |
143985b7 AF |
4666 | struct type *type) |
4667 | { | |
e17a4113 UW |
4668 | struct gdbarch *gdbarch = get_frame_arch (frame); |
4669 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
f4644a3f | 4670 | CORE_ADDR sp = get_frame_register_unsigned (frame, I386_ESP_REGNUM); |
e17a4113 | 4671 | return read_memory_unsigned_integer (sp + (4 * (argi + 1)), 4, byte_order); |
143985b7 AF |
4672 | } |
4673 | ||
7ad10968 HZ |
4674 | #define PREFIX_REPZ 0x01 |
4675 | #define PREFIX_REPNZ 0x02 | |
4676 | #define PREFIX_LOCK 0x04 | |
4677 | #define PREFIX_DATA 0x08 | |
4678 | #define PREFIX_ADDR 0x10 | |
473f17b0 | 4679 | |
7ad10968 HZ |
4680 | /* operand size */ |
4681 | enum | |
4682 | { | |
4683 | OT_BYTE = 0, | |
4684 | OT_WORD, | |
4685 | OT_LONG, | |
cf648174 | 4686 | OT_QUAD, |
a3c4230a | 4687 | OT_DQUAD, |
7ad10968 | 4688 | }; |
473f17b0 | 4689 | |
7ad10968 HZ |
4690 | /* i386 arith/logic operations */ |
4691 | enum | |
4692 | { | |
4693 | OP_ADDL, | |
4694 | OP_ORL, | |
4695 | OP_ADCL, | |
4696 | OP_SBBL, | |
4697 | OP_ANDL, | |
4698 | OP_SUBL, | |
4699 | OP_XORL, | |
4700 | OP_CMPL, | |
4701 | }; | |
5716833c | 4702 | |
7ad10968 HZ |
4703 | struct i386_record_s |
4704 | { | |
cf648174 | 4705 | struct gdbarch *gdbarch; |
7ad10968 | 4706 | struct regcache *regcache; |
df61f520 | 4707 | CORE_ADDR orig_addr; |
7ad10968 HZ |
4708 | CORE_ADDR addr; |
4709 | int aflag; | |
4710 | int dflag; | |
4711 | int override; | |
4712 | uint8_t modrm; | |
4713 | uint8_t mod, reg, rm; | |
4714 | int ot; | |
cf648174 HZ |
4715 | uint8_t rex_x; |
4716 | uint8_t rex_b; | |
4717 | int rip_offset; | |
4718 | int popl_esp_hack; | |
4719 | const int *regmap; | |
7ad10968 | 4720 | }; |
5716833c | 4721 | |
99c1624c PA |
4722 | /* Parse the "modrm" part of the memory address irp->addr points at. |
4723 | Returns -1 if something goes wrong, 0 otherwise. */ | |
5716833c | 4724 | |
7ad10968 HZ |
4725 | static int |
4726 | i386_record_modrm (struct i386_record_s *irp) | |
4727 | { | |
cf648174 | 4728 | struct gdbarch *gdbarch = irp->gdbarch; |
5af949e3 | 4729 | |
4ffa4fc7 PA |
4730 | if (record_read_memory (gdbarch, irp->addr, &irp->modrm, 1)) |
4731 | return -1; | |
4732 | ||
7ad10968 HZ |
4733 | irp->addr++; |
4734 | irp->mod = (irp->modrm >> 6) & 3; | |
4735 | irp->reg = (irp->modrm >> 3) & 7; | |
4736 | irp->rm = irp->modrm & 7; | |
5716833c | 4737 | |
7ad10968 HZ |
4738 | return 0; |
4739 | } | |
d2a7c97a | 4740 | |
99c1624c PA |
4741 | /* Extract the memory address that the current instruction writes to, |
4742 | and return it in *ADDR. Return -1 if something goes wrong. */ | |
8201327c | 4743 | |
7ad10968 | 4744 | static int |
cf648174 | 4745 | i386_record_lea_modrm_addr (struct i386_record_s *irp, uint64_t *addr) |
7ad10968 | 4746 | { |
cf648174 | 4747 | struct gdbarch *gdbarch = irp->gdbarch; |
60a1502a MS |
4748 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
4749 | gdb_byte buf[4]; | |
4750 | ULONGEST offset64; | |
21d0e8a4 | 4751 | |
7ad10968 | 4752 | *addr = 0; |
1e87984a | 4753 | if (irp->aflag || irp->regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 4754 | { |
1e87984a | 4755 | /* 32/64 bits */ |
7ad10968 HZ |
4756 | int havesib = 0; |
4757 | uint8_t scale = 0; | |
648d0c8b | 4758 | uint8_t byte; |
7ad10968 HZ |
4759 | uint8_t index = 0; |
4760 | uint8_t base = irp->rm; | |
896fb97d | 4761 | |
7ad10968 HZ |
4762 | if (base == 4) |
4763 | { | |
4764 | havesib = 1; | |
4ffa4fc7 PA |
4765 | if (record_read_memory (gdbarch, irp->addr, &byte, 1)) |
4766 | return -1; | |
7ad10968 | 4767 | irp->addr++; |
648d0c8b MS |
4768 | scale = (byte >> 6) & 3; |
4769 | index = ((byte >> 3) & 7) | irp->rex_x; | |
4770 | base = (byte & 7); | |
7ad10968 | 4771 | } |
cf648174 | 4772 | base |= irp->rex_b; |
21d0e8a4 | 4773 | |
7ad10968 HZ |
4774 | switch (irp->mod) |
4775 | { | |
4776 | case 0: | |
4777 | if ((base & 7) == 5) | |
4778 | { | |
4779 | base = 0xff; | |
4ffa4fc7 PA |
4780 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4781 | return -1; | |
7ad10968 | 4782 | irp->addr += 4; |
60a1502a | 4783 | *addr = extract_signed_integer (buf, 4, byte_order); |
cf648174 HZ |
4784 | if (irp->regmap[X86_RECORD_R8_REGNUM] && !havesib) |
4785 | *addr += irp->addr + irp->rip_offset; | |
7ad10968 | 4786 | } |
7ad10968 HZ |
4787 | break; |
4788 | case 1: | |
4ffa4fc7 PA |
4789 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4790 | return -1; | |
7ad10968 | 4791 | irp->addr++; |
60a1502a | 4792 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4793 | break; |
4794 | case 2: | |
4ffa4fc7 PA |
4795 | if (record_read_memory (gdbarch, irp->addr, buf, 4)) |
4796 | return -1; | |
60a1502a | 4797 | *addr = extract_signed_integer (buf, 4, byte_order); |
7ad10968 HZ |
4798 | irp->addr += 4; |
4799 | break; | |
4800 | } | |
356a6b3e | 4801 | |
60a1502a | 4802 | offset64 = 0; |
7ad10968 | 4803 | if (base != 0xff) |
dda83cd7 | 4804 | { |
cf648174 HZ |
4805 | if (base == 4 && irp->popl_esp_hack) |
4806 | *addr += irp->popl_esp_hack; | |
4807 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[base], | |
dda83cd7 | 4808 | &offset64); |
7ad10968 | 4809 | } |
cf648174 | 4810 | if (irp->aflag == 2) |
dda83cd7 | 4811 | { |
60a1502a | 4812 | *addr += offset64; |
dda83cd7 | 4813 | } |
cf648174 | 4814 | else |
dda83cd7 | 4815 | *addr = (uint32_t) (offset64 + *addr); |
c4fc7f1b | 4816 | |
7ad10968 HZ |
4817 | if (havesib && (index != 4 || scale != 0)) |
4818 | { | |
cf648174 | 4819 | regcache_raw_read_unsigned (irp->regcache, irp->regmap[index], |
dda83cd7 | 4820 | &offset64); |
cf648174 | 4821 | if (irp->aflag == 2) |
60a1502a | 4822 | *addr += offset64 << scale; |
cf648174 | 4823 | else |
60a1502a | 4824 | *addr = (uint32_t) (*addr + (offset64 << scale)); |
7ad10968 | 4825 | } |
e85596e0 L |
4826 | |
4827 | if (!irp->aflag) | |
4828 | { | |
4829 | /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend | |
4830 | address from 32-bit to 64-bit. */ | |
4831 | *addr = (uint32_t) *addr; | |
4832 | } | |
7ad10968 HZ |
4833 | } |
4834 | else | |
4835 | { | |
4836 | /* 16 bits */ | |
4837 | switch (irp->mod) | |
4838 | { | |
4839 | case 0: | |
4840 | if (irp->rm == 6) | |
4841 | { | |
4ffa4fc7 PA |
4842 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4843 | return -1; | |
7ad10968 | 4844 | irp->addr += 2; |
60a1502a | 4845 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4846 | irp->rm = 0; |
4847 | goto no_rm; | |
4848 | } | |
7ad10968 HZ |
4849 | break; |
4850 | case 1: | |
4ffa4fc7 PA |
4851 | if (record_read_memory (gdbarch, irp->addr, buf, 1)) |
4852 | return -1; | |
7ad10968 | 4853 | irp->addr++; |
60a1502a | 4854 | *addr = (int8_t) buf[0]; |
7ad10968 HZ |
4855 | break; |
4856 | case 2: | |
4ffa4fc7 PA |
4857 | if (record_read_memory (gdbarch, irp->addr, buf, 2)) |
4858 | return -1; | |
7ad10968 | 4859 | irp->addr += 2; |
60a1502a | 4860 | *addr = extract_signed_integer (buf, 2, byte_order); |
7ad10968 HZ |
4861 | break; |
4862 | } | |
c4fc7f1b | 4863 | |
7ad10968 HZ |
4864 | switch (irp->rm) |
4865 | { | |
4866 | case 0: | |
cf648174 HZ |
4867 | regcache_raw_read_unsigned (irp->regcache, |
4868 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4869 | &offset64); |
60a1502a | 4870 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4871 | regcache_raw_read_unsigned (irp->regcache, |
4872 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4873 | &offset64); |
60a1502a | 4874 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4875 | break; |
4876 | case 1: | |
cf648174 HZ |
4877 | regcache_raw_read_unsigned (irp->regcache, |
4878 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4879 | &offset64); |
60a1502a | 4880 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4881 | regcache_raw_read_unsigned (irp->regcache, |
4882 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4883 | &offset64); |
60a1502a | 4884 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4885 | break; |
4886 | case 2: | |
cf648174 HZ |
4887 | regcache_raw_read_unsigned (irp->regcache, |
4888 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4889 | &offset64); |
60a1502a | 4890 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4891 | regcache_raw_read_unsigned (irp->regcache, |
4892 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4893 | &offset64); |
60a1502a | 4894 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4895 | break; |
4896 | case 3: | |
cf648174 HZ |
4897 | regcache_raw_read_unsigned (irp->regcache, |
4898 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4899 | &offset64); |
60a1502a | 4900 | *addr = (uint32_t) (*addr + offset64); |
cf648174 HZ |
4901 | regcache_raw_read_unsigned (irp->regcache, |
4902 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4903 | &offset64); |
60a1502a | 4904 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4905 | break; |
4906 | case 4: | |
cf648174 HZ |
4907 | regcache_raw_read_unsigned (irp->regcache, |
4908 | irp->regmap[X86_RECORD_RESI_REGNUM], | |
dda83cd7 | 4909 | &offset64); |
60a1502a | 4910 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4911 | break; |
4912 | case 5: | |
cf648174 HZ |
4913 | regcache_raw_read_unsigned (irp->regcache, |
4914 | irp->regmap[X86_RECORD_REDI_REGNUM], | |
dda83cd7 | 4915 | &offset64); |
60a1502a | 4916 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4917 | break; |
4918 | case 6: | |
cf648174 HZ |
4919 | regcache_raw_read_unsigned (irp->regcache, |
4920 | irp->regmap[X86_RECORD_REBP_REGNUM], | |
dda83cd7 | 4921 | &offset64); |
60a1502a | 4922 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4923 | break; |
4924 | case 7: | |
cf648174 HZ |
4925 | regcache_raw_read_unsigned (irp->regcache, |
4926 | irp->regmap[X86_RECORD_REBX_REGNUM], | |
dda83cd7 | 4927 | &offset64); |
60a1502a | 4928 | *addr = (uint32_t) (*addr + offset64); |
7ad10968 HZ |
4929 | break; |
4930 | } | |
4931 | *addr &= 0xffff; | |
4932 | } | |
c4fc7f1b | 4933 | |
01fe1b41 | 4934 | no_rm: |
7ad10968 HZ |
4935 | return 0; |
4936 | } | |
c4fc7f1b | 4937 | |
99c1624c PA |
4938 | /* Record the address and contents of the memory that will be changed |
4939 | by the current instruction. Return -1 if something goes wrong, 0 | |
4940 | otherwise. */ | |
356a6b3e | 4941 | |
7ad10968 HZ |
4942 | static int |
4943 | i386_record_lea_modrm (struct i386_record_s *irp) | |
4944 | { | |
cf648174 HZ |
4945 | struct gdbarch *gdbarch = irp->gdbarch; |
4946 | uint64_t addr; | |
356a6b3e | 4947 | |
d7877f7e | 4948 | if (irp->override >= 0) |
7ad10968 | 4949 | { |
25ea693b | 4950 | if (record_full_memory_query) |
dda83cd7 SM |
4951 | { |
4952 | if (yquery (_("\ | |
bb08c432 HZ |
4953 | Process record ignores the memory change of instruction at address %s\n\ |
4954 | because it can't get the value of the segment register.\n\ | |
4955 | Do you want to stop the program?"), | |
dda83cd7 | 4956 | paddress (gdbarch, irp->orig_addr))) |
651ce16a | 4957 | return -1; |
dda83cd7 | 4958 | } |
bb08c432 | 4959 | |
7ad10968 HZ |
4960 | return 0; |
4961 | } | |
61113f8b | 4962 | |
7ad10968 HZ |
4963 | if (i386_record_lea_modrm_addr (irp, &addr)) |
4964 | return -1; | |
96297dab | 4965 | |
25ea693b | 4966 | if (record_full_arch_list_add_mem (addr, 1 << irp->ot)) |
7ad10968 | 4967 | return -1; |
a62cc96e | 4968 | |
7ad10968 HZ |
4969 | return 0; |
4970 | } | |
b6197528 | 4971 | |
99c1624c PA |
4972 | /* Record the effects of a push operation. Return -1 if something |
4973 | goes wrong, 0 otherwise. */ | |
cf648174 HZ |
4974 | |
4975 | static int | |
4976 | i386_record_push (struct i386_record_s *irp, int size) | |
4977 | { | |
648d0c8b | 4978 | ULONGEST addr; |
cf648174 | 4979 | |
25ea693b MM |
4980 | if (record_full_arch_list_add_reg (irp->regcache, |
4981 | irp->regmap[X86_RECORD_RESP_REGNUM])) | |
cf648174 HZ |
4982 | return -1; |
4983 | regcache_raw_read_unsigned (irp->regcache, | |
4984 | irp->regmap[X86_RECORD_RESP_REGNUM], | |
648d0c8b | 4985 | &addr); |
25ea693b | 4986 | if (record_full_arch_list_add_mem ((CORE_ADDR) addr - size, size)) |
cf648174 HZ |
4987 | return -1; |
4988 | ||
4989 | return 0; | |
4990 | } | |
4991 | ||
0289bdd7 MS |
4992 | |
4993 | /* Defines contents to record. */ | |
4994 | #define I386_SAVE_FPU_REGS 0xfffd | |
4995 | #define I386_SAVE_FPU_ENV 0xfffe | |
4996 | #define I386_SAVE_FPU_ENV_REG_STACK 0xffff | |
4997 | ||
99c1624c PA |
4998 | /* Record the values of the floating point registers which will be |
4999 | changed by the current instruction. Returns -1 if something is | |
5000 | wrong, 0 otherwise. */ | |
0289bdd7 MS |
5001 | |
5002 | static int i386_record_floats (struct gdbarch *gdbarch, | |
dda83cd7 SM |
5003 | struct i386_record_s *ir, |
5004 | uint32_t iregnum) | |
0289bdd7 | 5005 | { |
08106042 | 5006 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
0289bdd7 MS |
5007 | int i; |
5008 | ||
5009 | /* Oza: Because of floating point insn push/pop of fpu stack is going to | |
5010 | happen. Currently we store st0-st7 registers, but we need not store all | |
5011 | registers all the time, in future we use ftag register and record only | |
5012 | those who are not marked as an empty. */ | |
5013 | ||
5014 | if (I386_SAVE_FPU_REGS == iregnum) | |
5015 | { | |
5016 | for (i = I387_ST0_REGNUM (tdep); i <= I387_ST0_REGNUM (tdep) + 7; i++) | |
dda83cd7 SM |
5017 | { |
5018 | if (record_full_arch_list_add_reg (ir->regcache, i)) | |
5019 | return -1; | |
5020 | } | |
0289bdd7 MS |
5021 | } |
5022 | else if (I386_SAVE_FPU_ENV == iregnum) | |
5023 | { | |
5024 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5025 | { | |
25ea693b | 5026 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
dda83cd7 | 5027 | return -1; |
0289bdd7 MS |
5028 | } |
5029 | } | |
5030 | else if (I386_SAVE_FPU_ENV_REG_STACK == iregnum) | |
5031 | { | |
5032 | for (i = I387_ST0_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
dda83cd7 SM |
5033 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
5034 | return -1; | |
0289bdd7 MS |
5035 | } |
5036 | else if ((iregnum >= I387_ST0_REGNUM (tdep)) && | |
dda83cd7 | 5037 | (iregnum <= I387_FOP_REGNUM (tdep))) |
0289bdd7 | 5038 | { |
25ea693b | 5039 | if (record_full_arch_list_add_reg (ir->regcache,iregnum)) |
dda83cd7 | 5040 | return -1; |
0289bdd7 MS |
5041 | } |
5042 | else | |
5043 | { | |
5044 | /* Parameter error. */ | |
5045 | return -1; | |
5046 | } | |
5047 | if(I386_SAVE_FPU_ENV != iregnum) | |
5048 | { | |
5049 | for (i = I387_FCTRL_REGNUM (tdep); i <= I387_FOP_REGNUM (tdep); i++) | |
5050 | { | |
25ea693b | 5051 | if (record_full_arch_list_add_reg (ir->regcache, i)) |
dda83cd7 | 5052 | return -1; |
0289bdd7 MS |
5053 | } |
5054 | } | |
5055 | return 0; | |
5056 | } | |
5057 | ||
99c1624c PA |
5058 | /* Parse the current instruction, and record the values of the |
5059 | registers and memory that will be changed by the current | |
5060 | instruction. Returns -1 if something goes wrong, 0 otherwise. */ | |
8201327c | 5061 | |
25ea693b MM |
5062 | #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \ |
5063 | record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)]) | |
cf648174 | 5064 | |
a6b808b4 | 5065 | int |
7ad10968 | 5066 | i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache, |
648d0c8b | 5067 | CORE_ADDR input_addr) |
7ad10968 | 5068 | { |
60a1502a | 5069 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
7ad10968 | 5070 | int prefixes = 0; |
580879fc | 5071 | int regnum = 0; |
425b824a | 5072 | uint32_t opcode; |
f4644a3f | 5073 | uint8_t opcode8; |
648d0c8b | 5074 | ULONGEST addr; |
975c21ab | 5075 | gdb_byte buf[I386_MAX_REGISTER_SIZE]; |
7ad10968 | 5076 | struct i386_record_s ir; |
08106042 | 5077 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
cf648174 HZ |
5078 | uint8_t rex_w = -1; |
5079 | uint8_t rex_r = 0; | |
7ad10968 | 5080 | |
8408d274 | 5081 | memset (&ir, 0, sizeof (struct i386_record_s)); |
7ad10968 | 5082 | ir.regcache = regcache; |
648d0c8b MS |
5083 | ir.addr = input_addr; |
5084 | ir.orig_addr = input_addr; | |
7ad10968 HZ |
5085 | ir.aflag = 1; |
5086 | ir.dflag = 1; | |
cf648174 HZ |
5087 | ir.override = -1; |
5088 | ir.popl_esp_hack = 0; | |
a3c4230a | 5089 | ir.regmap = tdep->record_regmap; |
cf648174 | 5090 | ir.gdbarch = gdbarch; |
7ad10968 HZ |
5091 | |
5092 | if (record_debug > 1) | |
6cb06a8c TT |
5093 | gdb_printf (gdb_stdlog, "Process record: i386_process_record " |
5094 | "addr = %s\n", | |
5095 | paddress (gdbarch, ir.addr)); | |
7ad10968 HZ |
5096 | |
5097 | /* prefixes */ | |
5098 | while (1) | |
5099 | { | |
4ffa4fc7 PA |
5100 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5101 | return -1; | |
7ad10968 | 5102 | ir.addr++; |
425b824a | 5103 | switch (opcode8) /* Instruction prefixes */ |
7ad10968 | 5104 | { |
01fe1b41 | 5105 | case REPE_PREFIX_OPCODE: |
7ad10968 HZ |
5106 | prefixes |= PREFIX_REPZ; |
5107 | break; | |
01fe1b41 | 5108 | case REPNE_PREFIX_OPCODE: |
7ad10968 HZ |
5109 | prefixes |= PREFIX_REPNZ; |
5110 | break; | |
01fe1b41 | 5111 | case LOCK_PREFIX_OPCODE: |
7ad10968 HZ |
5112 | prefixes |= PREFIX_LOCK; |
5113 | break; | |
01fe1b41 | 5114 | case CS_PREFIX_OPCODE: |
cf648174 | 5115 | ir.override = X86_RECORD_CS_REGNUM; |
7ad10968 | 5116 | break; |
01fe1b41 | 5117 | case SS_PREFIX_OPCODE: |
cf648174 | 5118 | ir.override = X86_RECORD_SS_REGNUM; |
7ad10968 | 5119 | break; |
01fe1b41 | 5120 | case DS_PREFIX_OPCODE: |
cf648174 | 5121 | ir.override = X86_RECORD_DS_REGNUM; |
7ad10968 | 5122 | break; |
01fe1b41 | 5123 | case ES_PREFIX_OPCODE: |
cf648174 | 5124 | ir.override = X86_RECORD_ES_REGNUM; |
7ad10968 | 5125 | break; |
01fe1b41 | 5126 | case FS_PREFIX_OPCODE: |
cf648174 | 5127 | ir.override = X86_RECORD_FS_REGNUM; |
7ad10968 | 5128 | break; |
01fe1b41 | 5129 | case GS_PREFIX_OPCODE: |
cf648174 | 5130 | ir.override = X86_RECORD_GS_REGNUM; |
7ad10968 | 5131 | break; |
01fe1b41 | 5132 | case DATA_PREFIX_OPCODE: |
7ad10968 HZ |
5133 | prefixes |= PREFIX_DATA; |
5134 | break; | |
01fe1b41 | 5135 | case ADDR_PREFIX_OPCODE: |
7ad10968 HZ |
5136 | prefixes |= PREFIX_ADDR; |
5137 | break; | |
dda83cd7 SM |
5138 | case 0x40: /* i386 inc %eax */ |
5139 | case 0x41: /* i386 inc %ecx */ | |
5140 | case 0x42: /* i386 inc %edx */ | |
5141 | case 0x43: /* i386 inc %ebx */ | |
5142 | case 0x44: /* i386 inc %esp */ | |
5143 | case 0x45: /* i386 inc %ebp */ | |
5144 | case 0x46: /* i386 inc %esi */ | |
5145 | case 0x47: /* i386 inc %edi */ | |
5146 | case 0x48: /* i386 dec %eax */ | |
5147 | case 0x49: /* i386 dec %ecx */ | |
5148 | case 0x4a: /* i386 dec %edx */ | |
5149 | case 0x4b: /* i386 dec %ebx */ | |
5150 | case 0x4c: /* i386 dec %esp */ | |
5151 | case 0x4d: /* i386 dec %ebp */ | |
5152 | case 0x4e: /* i386 dec %esi */ | |
5153 | case 0x4f: /* i386 dec %edi */ | |
5154 | if (ir.regmap[X86_RECORD_R8_REGNUM]) /* 64 bit target */ | |
5155 | { | |
5156 | /* REX */ | |
5157 | rex_w = (opcode8 >> 3) & 1; | |
5158 | rex_r = (opcode8 & 0x4) << 1; | |
5159 | ir.rex_x = (opcode8 & 0x2) << 2; | |
5160 | ir.rex_b = (opcode8 & 0x1) << 3; | |
5161 | } | |
d691bec7 MS |
5162 | else /* 32 bit target */ |
5163 | goto out_prefixes; | |
dda83cd7 | 5164 | break; |
7ad10968 HZ |
5165 | default: |
5166 | goto out_prefixes; | |
5167 | break; | |
5168 | } | |
5169 | } | |
01fe1b41 | 5170 | out_prefixes: |
cf648174 HZ |
5171 | if (ir.regmap[X86_RECORD_R8_REGNUM] && rex_w == 1) |
5172 | { | |
5173 | ir.dflag = 2; | |
5174 | } | |
5175 | else | |
5176 | { | |
5177 | if (prefixes & PREFIX_DATA) | |
dda83cd7 | 5178 | ir.dflag ^= 1; |
cf648174 | 5179 | } |
7ad10968 HZ |
5180 | if (prefixes & PREFIX_ADDR) |
5181 | ir.aflag ^= 1; | |
cf648174 HZ |
5182 | else if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5183 | ir.aflag = 2; | |
7ad10968 | 5184 | |
1777feb0 | 5185 | /* Now check op code. */ |
425b824a | 5186 | opcode = (uint32_t) opcode8; |
01fe1b41 | 5187 | reswitch: |
7ad10968 HZ |
5188 | switch (opcode) |
5189 | { | |
5190 | case 0x0f: | |
4ffa4fc7 PA |
5191 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
5192 | return -1; | |
7ad10968 | 5193 | ir.addr++; |
a3c4230a | 5194 | opcode = (uint32_t) opcode8 | 0x0f00; |
7ad10968 HZ |
5195 | goto reswitch; |
5196 | break; | |
93924b6b | 5197 | |
a38bba38 | 5198 | case 0x00: /* arith & logic */ |
7ad10968 HZ |
5199 | case 0x01: |
5200 | case 0x02: | |
5201 | case 0x03: | |
5202 | case 0x04: | |
5203 | case 0x05: | |
5204 | case 0x08: | |
5205 | case 0x09: | |
5206 | case 0x0a: | |
5207 | case 0x0b: | |
5208 | case 0x0c: | |
5209 | case 0x0d: | |
5210 | case 0x10: | |
5211 | case 0x11: | |
5212 | case 0x12: | |
5213 | case 0x13: | |
5214 | case 0x14: | |
5215 | case 0x15: | |
5216 | case 0x18: | |
5217 | case 0x19: | |
5218 | case 0x1a: | |
5219 | case 0x1b: | |
5220 | case 0x1c: | |
5221 | case 0x1d: | |
5222 | case 0x20: | |
5223 | case 0x21: | |
5224 | case 0x22: | |
5225 | case 0x23: | |
5226 | case 0x24: | |
5227 | case 0x25: | |
5228 | case 0x28: | |
5229 | case 0x29: | |
5230 | case 0x2a: | |
5231 | case 0x2b: | |
5232 | case 0x2c: | |
5233 | case 0x2d: | |
5234 | case 0x30: | |
5235 | case 0x31: | |
5236 | case 0x32: | |
5237 | case 0x33: | |
5238 | case 0x34: | |
5239 | case 0x35: | |
5240 | case 0x38: | |
5241 | case 0x39: | |
5242 | case 0x3a: | |
5243 | case 0x3b: | |
5244 | case 0x3c: | |
5245 | case 0x3d: | |
5246 | if (((opcode >> 3) & 7) != OP_CMPL) | |
5247 | { | |
5248 | if ((opcode & 1) == 0) | |
5249 | ir.ot = OT_BYTE; | |
5250 | else | |
5251 | ir.ot = ir.dflag + OT_WORD; | |
93924b6b | 5252 | |
7ad10968 HZ |
5253 | switch ((opcode >> 1) & 3) |
5254 | { | |
a38bba38 | 5255 | case 0: /* OP Ev, Gv */ |
7ad10968 HZ |
5256 | if (i386_record_modrm (&ir)) |
5257 | return -1; | |
5258 | if (ir.mod != 3) | |
5259 | { | |
5260 | if (i386_record_lea_modrm (&ir)) | |
5261 | return -1; | |
5262 | } | |
5263 | else | |
5264 | { | |
dda83cd7 | 5265 | ir.rm |= ir.rex_b; |
cf648174 | 5266 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5267 | ir.rm &= 0x3; |
25ea693b | 5268 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5269 | } |
5270 | break; | |
a38bba38 | 5271 | case 1: /* OP Gv, Ev */ |
7ad10968 HZ |
5272 | if (i386_record_modrm (&ir)) |
5273 | return -1; | |
dda83cd7 | 5274 | ir.reg |= rex_r; |
cf648174 | 5275 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5276 | ir.reg &= 0x3; |
25ea693b | 5277 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5278 | break; |
a38bba38 | 5279 | case 2: /* OP A, Iv */ |
25ea693b | 5280 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5281 | break; |
5282 | } | |
5283 | } | |
25ea693b | 5284 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5285 | break; |
42fdc8df | 5286 | |
a38bba38 | 5287 | case 0x80: /* GRP1 */ |
7ad10968 HZ |
5288 | case 0x81: |
5289 | case 0x82: | |
5290 | case 0x83: | |
5291 | if (i386_record_modrm (&ir)) | |
5292 | return -1; | |
8201327c | 5293 | |
7ad10968 HZ |
5294 | if (ir.reg != OP_CMPL) |
5295 | { | |
5296 | if ((opcode & 1) == 0) | |
5297 | ir.ot = OT_BYTE; | |
5298 | else | |
5299 | ir.ot = ir.dflag + OT_WORD; | |
28fc6740 | 5300 | |
7ad10968 HZ |
5301 | if (ir.mod != 3) |
5302 | { | |
dda83cd7 SM |
5303 | if (opcode == 0x83) |
5304 | ir.rip_offset = 1; | |
5305 | else | |
5306 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); | |
7ad10968 HZ |
5307 | if (i386_record_lea_modrm (&ir)) |
5308 | return -1; | |
5309 | } | |
5310 | else | |
25ea693b | 5311 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 | 5312 | } |
25ea693b | 5313 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5314 | break; |
5e3397bb | 5315 | |
a38bba38 | 5316 | case 0x40: /* inc */ |
7ad10968 HZ |
5317 | case 0x41: |
5318 | case 0x42: | |
5319 | case 0x43: | |
5320 | case 0x44: | |
5321 | case 0x45: | |
5322 | case 0x46: | |
5323 | case 0x47: | |
a38bba38 MS |
5324 | |
5325 | case 0x48: /* dec */ | |
7ad10968 HZ |
5326 | case 0x49: |
5327 | case 0x4a: | |
5328 | case 0x4b: | |
5329 | case 0x4c: | |
5330 | case 0x4d: | |
5331 | case 0x4e: | |
5332 | case 0x4f: | |
a38bba38 | 5333 | |
25ea693b MM |
5334 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 7); |
5335 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 | 5336 | break; |
acd5c798 | 5337 | |
a38bba38 | 5338 | case 0xf6: /* GRP3 */ |
7ad10968 HZ |
5339 | case 0xf7: |
5340 | if ((opcode & 1) == 0) | |
5341 | ir.ot = OT_BYTE; | |
5342 | else | |
5343 | ir.ot = ir.dflag + OT_WORD; | |
5344 | if (i386_record_modrm (&ir)) | |
5345 | return -1; | |
acd5c798 | 5346 | |
cf648174 | 5347 | if (ir.mod != 3 && ir.reg == 0) |
dda83cd7 | 5348 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
cf648174 | 5349 | |
7ad10968 HZ |
5350 | switch (ir.reg) |
5351 | { | |
a38bba38 | 5352 | case 0: /* test */ |
25ea693b | 5353 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5354 | break; |
a38bba38 MS |
5355 | case 2: /* not */ |
5356 | case 3: /* neg */ | |
7ad10968 HZ |
5357 | if (ir.mod != 3) |
5358 | { | |
5359 | if (i386_record_lea_modrm (&ir)) | |
5360 | return -1; | |
5361 | } | |
5362 | else | |
5363 | { | |
dda83cd7 | 5364 | ir.rm |= ir.rex_b; |
cf648174 | 5365 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5366 | ir.rm &= 0x3; |
25ea693b | 5367 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5368 | } |
a38bba38 | 5369 | if (ir.reg == 3) /* neg */ |
25ea693b | 5370 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5371 | break; |
a38bba38 MS |
5372 | case 4: /* mul */ |
5373 | case 5: /* imul */ | |
5374 | case 6: /* div */ | |
5375 | case 7: /* idiv */ | |
25ea693b | 5376 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 | 5377 | if (ir.ot != OT_BYTE) |
25ea693b MM |
5378 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); |
5379 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5380 | break; |
5381 | default: | |
5382 | ir.addr -= 2; | |
5383 | opcode = opcode << 8 | ir.modrm; | |
5384 | goto no_support; | |
5385 | break; | |
5386 | } | |
5387 | break; | |
5388 | ||
a38bba38 MS |
5389 | case 0xfe: /* GRP4 */ |
5390 | case 0xff: /* GRP5 */ | |
7ad10968 HZ |
5391 | if (i386_record_modrm (&ir)) |
5392 | return -1; | |
5393 | if (ir.reg >= 2 && opcode == 0xfe) | |
5394 | { | |
5395 | ir.addr -= 2; | |
5396 | opcode = opcode << 8 | ir.modrm; | |
5397 | goto no_support; | |
5398 | } | |
7ad10968 HZ |
5399 | switch (ir.reg) |
5400 | { | |
a38bba38 MS |
5401 | case 0: /* inc */ |
5402 | case 1: /* dec */ | |
dda83cd7 | 5403 | if ((opcode & 1) == 0) |
cf648174 | 5404 | ir.ot = OT_BYTE; |
dda83cd7 | 5405 | else |
cf648174 | 5406 | ir.ot = ir.dflag + OT_WORD; |
7ad10968 HZ |
5407 | if (ir.mod != 3) |
5408 | { | |
5409 | if (i386_record_lea_modrm (&ir)) | |
5410 | return -1; | |
5411 | } | |
5412 | else | |
5413 | { | |
cf648174 HZ |
5414 | ir.rm |= ir.rex_b; |
5415 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5416 | ir.rm &= 0x3; |
25ea693b | 5417 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5418 | } |
25ea693b | 5419 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5420 | break; |
a38bba38 | 5421 | case 2: /* call */ |
dda83cd7 SM |
5422 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5423 | ir.dflag = 2; | |
cf648174 | 5424 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5425 | return -1; |
25ea693b | 5426 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5427 | break; |
a38bba38 | 5428 | case 3: /* lcall */ |
25ea693b | 5429 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 5430 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 | 5431 | return -1; |
25ea693b | 5432 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 5433 | break; |
a38bba38 MS |
5434 | case 4: /* jmp */ |
5435 | case 5: /* ljmp */ | |
25ea693b | 5436 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 5437 | break; |
a38bba38 | 5438 | case 6: /* push */ |
dda83cd7 SM |
5439 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
5440 | ir.dflag = 2; | |
cf648174 HZ |
5441 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
5442 | return -1; | |
7ad10968 HZ |
5443 | break; |
5444 | default: | |
5445 | ir.addr -= 2; | |
5446 | opcode = opcode << 8 | ir.modrm; | |
5447 | goto no_support; | |
5448 | break; | |
5449 | } | |
5450 | break; | |
5451 | ||
a38bba38 | 5452 | case 0x84: /* test */ |
7ad10968 HZ |
5453 | case 0x85: |
5454 | case 0xa8: | |
5455 | case 0xa9: | |
25ea693b | 5456 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5457 | break; |
5458 | ||
a38bba38 | 5459 | case 0x98: /* CWDE/CBW */ |
25ea693b | 5460 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5461 | break; |
5462 | ||
a38bba38 | 5463 | case 0x99: /* CDQ/CWD */ |
25ea693b MM |
5464 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5465 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5466 | break; |
5467 | ||
a38bba38 | 5468 | case 0x0faf: /* imul */ |
7ad10968 HZ |
5469 | case 0x69: |
5470 | case 0x6b: | |
5471 | ir.ot = ir.dflag + OT_WORD; | |
5472 | if (i386_record_modrm (&ir)) | |
5473 | return -1; | |
cf648174 | 5474 | if (opcode == 0x69) |
dda83cd7 | 5475 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
cf648174 | 5476 | else if (opcode == 0x6b) |
dda83cd7 | 5477 | ir.rip_offset = 1; |
cf648174 HZ |
5478 | ir.reg |= rex_r; |
5479 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5480 | ir.reg &= 0x3; |
25ea693b MM |
5481 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
5482 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5483 | break; |
5484 | ||
a38bba38 | 5485 | case 0x0fc0: /* xadd */ |
7ad10968 HZ |
5486 | case 0x0fc1: |
5487 | if ((opcode & 1) == 0) | |
5488 | ir.ot = OT_BYTE; | |
5489 | else | |
5490 | ir.ot = ir.dflag + OT_WORD; | |
5491 | if (i386_record_modrm (&ir)) | |
5492 | return -1; | |
cf648174 | 5493 | ir.reg |= rex_r; |
7ad10968 HZ |
5494 | if (ir.mod == 3) |
5495 | { | |
cf648174 | 5496 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5497 | ir.reg &= 0x3; |
25ea693b | 5498 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5499 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5500 | ir.rm &= 0x3; |
25ea693b | 5501 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5502 | } |
5503 | else | |
5504 | { | |
5505 | if (i386_record_lea_modrm (&ir)) | |
5506 | return -1; | |
cf648174 | 5507 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5508 | ir.reg &= 0x3; |
25ea693b | 5509 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 | 5510 | } |
25ea693b | 5511 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5512 | break; |
5513 | ||
a38bba38 | 5514 | case 0x0fb0: /* cmpxchg */ |
7ad10968 HZ |
5515 | case 0x0fb1: |
5516 | if ((opcode & 1) == 0) | |
5517 | ir.ot = OT_BYTE; | |
5518 | else | |
5519 | ir.ot = ir.dflag + OT_WORD; | |
5520 | if (i386_record_modrm (&ir)) | |
5521 | return -1; | |
5522 | if (ir.mod == 3) | |
5523 | { | |
dda83cd7 | 5524 | ir.reg |= rex_r; |
25ea693b | 5525 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
cf648174 | 5526 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
7ad10968 | 5527 | ir.reg &= 0x3; |
25ea693b | 5528 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5529 | } |
5530 | else | |
5531 | { | |
25ea693b | 5532 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5533 | if (i386_record_lea_modrm (&ir)) |
5534 | return -1; | |
5535 | } | |
25ea693b | 5536 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5537 | break; |
5538 | ||
20b477a7 | 5539 | case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */ |
7ad10968 HZ |
5540 | if (i386_record_modrm (&ir)) |
5541 | return -1; | |
5542 | if (ir.mod == 3) | |
5543 | { | |
20b477a7 LM |
5544 | /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as |
5545 | an extended opcode. rdrand has bits 110 (/6) and rdseed | |
5546 | has bits 111 (/7). */ | |
5547 | if (ir.reg == 6 || ir.reg == 7) | |
5548 | { | |
5549 | /* The storage register is described by the 3 R/M bits, but the | |
5550 | REX.B prefix may be used to give access to registers | |
5551 | R8~R15. In this case ir.rex_b + R/M will give us the register | |
5552 | in the range R8~R15. | |
5553 | ||
5554 | REX.W may also be used to access 64-bit registers, but we | |
5555 | already record entire registers and not just partial bits | |
5556 | of them. */ | |
5557 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm); | |
5558 | /* These instructions also set conditional bits. */ | |
5559 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
5560 | break; | |
5561 | } | |
5562 | else | |
5563 | { | |
5564 | /* We don't handle this particular instruction yet. */ | |
5565 | ir.addr -= 2; | |
5566 | opcode = opcode << 8 | ir.modrm; | |
5567 | goto no_support; | |
5568 | } | |
7ad10968 | 5569 | } |
25ea693b MM |
5570 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5571 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
5572 | if (i386_record_lea_modrm (&ir)) |
5573 | return -1; | |
25ea693b | 5574 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
5575 | break; |
5576 | ||
a38bba38 | 5577 | case 0x50: /* push */ |
7ad10968 HZ |
5578 | case 0x51: |
5579 | case 0x52: | |
5580 | case 0x53: | |
5581 | case 0x54: | |
5582 | case 0x55: | |
5583 | case 0x56: | |
5584 | case 0x57: | |
5585 | case 0x68: | |
5586 | case 0x6a: | |
cf648174 | 5587 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 5588 | ir.dflag = 2; |
cf648174 HZ |
5589 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
5590 | return -1; | |
5591 | break; | |
5592 | ||
a38bba38 MS |
5593 | case 0x06: /* push es */ |
5594 | case 0x0e: /* push cs */ | |
5595 | case 0x16: /* push ss */ | |
5596 | case 0x1e: /* push ds */ | |
cf648174 | 5597 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5598 | { |
cf648174 HZ |
5599 | ir.addr -= 1; |
5600 | goto no_support; | |
5601 | } | |
5602 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
5603 | return -1; | |
5604 | break; | |
5605 | ||
a38bba38 MS |
5606 | case 0x0fa0: /* push fs */ |
5607 | case 0x0fa8: /* push gs */ | |
cf648174 | 5608 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5609 | { |
cf648174 HZ |
5610 | ir.addr -= 2; |
5611 | goto no_support; | |
5612 | } | |
5613 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) | |
7ad10968 | 5614 | return -1; |
cf648174 HZ |
5615 | break; |
5616 | ||
a38bba38 | 5617 | case 0x60: /* pusha */ |
cf648174 | 5618 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5619 | { |
cf648174 HZ |
5620 | ir.addr -= 1; |
5621 | goto no_support; | |
5622 | } | |
5623 | if (i386_record_push (&ir, 1 << (ir.dflag + 4))) | |
7ad10968 HZ |
5624 | return -1; |
5625 | break; | |
5626 | ||
a38bba38 | 5627 | case 0x58: /* pop */ |
7ad10968 HZ |
5628 | case 0x59: |
5629 | case 0x5a: | |
5630 | case 0x5b: | |
5631 | case 0x5c: | |
5632 | case 0x5d: | |
5633 | case 0x5e: | |
5634 | case 0x5f: | |
25ea693b MM |
5635 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5636 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); | |
7ad10968 HZ |
5637 | break; |
5638 | ||
a38bba38 | 5639 | case 0x61: /* popa */ |
cf648174 | 5640 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5641 | { |
cf648174 HZ |
5642 | ir.addr -= 1; |
5643 | goto no_support; | |
7ad10968 | 5644 | } |
425b824a MS |
5645 | for (regnum = X86_RECORD_REAX_REGNUM; |
5646 | regnum <= X86_RECORD_REDI_REGNUM; | |
5647 | regnum++) | |
25ea693b | 5648 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
7ad10968 HZ |
5649 | break; |
5650 | ||
a38bba38 | 5651 | case 0x8f: /* pop */ |
cf648174 HZ |
5652 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
5653 | ir.ot = ir.dflag ? OT_QUAD : OT_WORD; | |
5654 | else | |
dda83cd7 | 5655 | ir.ot = ir.dflag + OT_WORD; |
7ad10968 HZ |
5656 | if (i386_record_modrm (&ir)) |
5657 | return -1; | |
5658 | if (ir.mod == 3) | |
25ea693b | 5659 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
5660 | else |
5661 | { | |
dda83cd7 | 5662 | ir.popl_esp_hack = 1 << ir.ot; |
7ad10968 HZ |
5663 | if (i386_record_lea_modrm (&ir)) |
5664 | return -1; | |
5665 | } | |
25ea693b | 5666 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
7ad10968 HZ |
5667 | break; |
5668 | ||
a38bba38 | 5669 | case 0xc8: /* enter */ |
25ea693b | 5670 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); |
cf648174 | 5671 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 5672 | ir.dflag = 2; |
cf648174 | 5673 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
7ad10968 HZ |
5674 | return -1; |
5675 | break; | |
5676 | ||
a38bba38 | 5677 | case 0xc9: /* leave */ |
25ea693b MM |
5678 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5679 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7ad10968 HZ |
5680 | break; |
5681 | ||
a38bba38 | 5682 | case 0x07: /* pop es */ |
cf648174 | 5683 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5684 | { |
cf648174 HZ |
5685 | ir.addr -= 1; |
5686 | goto no_support; | |
5687 | } | |
25ea693b MM |
5688 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5689 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM); | |
5690 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5691 | break; |
5692 | ||
a38bba38 | 5693 | case 0x17: /* pop ss */ |
cf648174 | 5694 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5695 | { |
cf648174 HZ |
5696 | ir.addr -= 1; |
5697 | goto no_support; | |
5698 | } | |
25ea693b MM |
5699 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5700 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM); | |
5701 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5702 | break; |
5703 | ||
a38bba38 | 5704 | case 0x1f: /* pop ds */ |
cf648174 | 5705 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5706 | { |
cf648174 HZ |
5707 | ir.addr -= 1; |
5708 | goto no_support; | |
5709 | } | |
25ea693b MM |
5710 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5711 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM); | |
5712 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5713 | break; |
5714 | ||
a38bba38 | 5715 | case 0x0fa1: /* pop fs */ |
25ea693b MM |
5716 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5717 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM); | |
5718 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5719 | break; |
5720 | ||
a38bba38 | 5721 | case 0x0fa9: /* pop gs */ |
25ea693b MM |
5722 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
5723 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); | |
5724 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5725 | break; |
5726 | ||
a38bba38 | 5727 | case 0x88: /* mov */ |
7ad10968 HZ |
5728 | case 0x89: |
5729 | case 0xc6: | |
5730 | case 0xc7: | |
5731 | if ((opcode & 1) == 0) | |
5732 | ir.ot = OT_BYTE; | |
5733 | else | |
5734 | ir.ot = ir.dflag + OT_WORD; | |
5735 | ||
5736 | if (i386_record_modrm (&ir)) | |
5737 | return -1; | |
5738 | ||
5739 | if (ir.mod != 3) | |
5740 | { | |
dda83cd7 | 5741 | if (opcode == 0xc6 || opcode == 0xc7) |
cf648174 | 5742 | ir.rip_offset = (ir.ot > OT_LONG) ? 4 : (1 << ir.ot); |
7ad10968 HZ |
5743 | if (i386_record_lea_modrm (&ir)) |
5744 | return -1; | |
5745 | } | |
5746 | else | |
5747 | { | |
dda83cd7 | 5748 | if (opcode == 0xc6 || opcode == 0xc7) |
cf648174 HZ |
5749 | ir.rm |= ir.rex_b; |
5750 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5751 | ir.rm &= 0x3; |
25ea693b | 5752 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 5753 | } |
7ad10968 | 5754 | break; |
cf648174 | 5755 | |
a38bba38 | 5756 | case 0x8a: /* mov */ |
7ad10968 HZ |
5757 | case 0x8b: |
5758 | if ((opcode & 1) == 0) | |
5759 | ir.ot = OT_BYTE; | |
5760 | else | |
5761 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5762 | if (i386_record_modrm (&ir)) |
5763 | return -1; | |
cf648174 HZ |
5764 | ir.reg |= rex_r; |
5765 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5766 | ir.reg &= 0x3; |
25ea693b | 5767 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
cf648174 | 5768 | break; |
7ad10968 | 5769 | |
a38bba38 | 5770 | case 0x8c: /* mov seg */ |
cf648174 | 5771 | if (i386_record_modrm (&ir)) |
7ad10968 | 5772 | return -1; |
cf648174 HZ |
5773 | if (ir.reg > 5) |
5774 | { | |
5775 | ir.addr -= 2; | |
5776 | opcode = opcode << 8 | ir.modrm; | |
5777 | goto no_support; | |
5778 | } | |
5779 | ||
5780 | if (ir.mod == 3) | |
25ea693b | 5781 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
cf648174 HZ |
5782 | else |
5783 | { | |
5784 | ir.ot = OT_WORD; | |
5785 | if (i386_record_lea_modrm (&ir)) | |
5786 | return -1; | |
5787 | } | |
7ad10968 HZ |
5788 | break; |
5789 | ||
a38bba38 | 5790 | case 0x8e: /* mov seg */ |
7ad10968 HZ |
5791 | if (i386_record_modrm (&ir)) |
5792 | return -1; | |
7ad10968 HZ |
5793 | switch (ir.reg) |
5794 | { | |
5795 | case 0: | |
425b824a | 5796 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 HZ |
5797 | break; |
5798 | case 2: | |
425b824a | 5799 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 HZ |
5800 | break; |
5801 | case 3: | |
425b824a | 5802 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 HZ |
5803 | break; |
5804 | case 4: | |
425b824a | 5805 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 HZ |
5806 | break; |
5807 | case 5: | |
425b824a | 5808 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5809 | break; |
5810 | default: | |
5811 | ir.addr -= 2; | |
5812 | opcode = opcode << 8 | ir.modrm; | |
5813 | goto no_support; | |
5814 | break; | |
5815 | } | |
25ea693b MM |
5816 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
5817 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
5818 | break; |
5819 | ||
a38bba38 MS |
5820 | case 0x0fb6: /* movzbS */ |
5821 | case 0x0fb7: /* movzwS */ | |
5822 | case 0x0fbe: /* movsbS */ | |
5823 | case 0x0fbf: /* movswS */ | |
7ad10968 HZ |
5824 | if (i386_record_modrm (&ir)) |
5825 | return -1; | |
25ea693b | 5826 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7ad10968 HZ |
5827 | break; |
5828 | ||
a38bba38 | 5829 | case 0x8d: /* lea */ |
7ad10968 HZ |
5830 | if (i386_record_modrm (&ir)) |
5831 | return -1; | |
5832 | if (ir.mod == 3) | |
5833 | { | |
5834 | ir.addr -= 2; | |
5835 | opcode = opcode << 8 | ir.modrm; | |
5836 | goto no_support; | |
5837 | } | |
7ad10968 | 5838 | ir.ot = ir.dflag; |
cf648174 HZ |
5839 | ir.reg |= rex_r; |
5840 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5841 | ir.reg &= 0x3; |
25ea693b | 5842 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5843 | break; |
5844 | ||
a38bba38 | 5845 | case 0xa0: /* mov EAX */ |
7ad10968 | 5846 | case 0xa1: |
a38bba38 MS |
5847 | |
5848 | case 0xd7: /* xlat */ | |
25ea693b | 5849 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7ad10968 HZ |
5850 | break; |
5851 | ||
a38bba38 | 5852 | case 0xa2: /* mov EAX */ |
7ad10968 | 5853 | case 0xa3: |
d7877f7e | 5854 | if (ir.override >= 0) |
dda83cd7 SM |
5855 | { |
5856 | if (record_full_memory_query) | |
5857 | { | |
5858 | if (yquery (_("\ | |
bb08c432 HZ |
5859 | Process record ignores the memory change of instruction at address %s\n\ |
5860 | because it can't get the value of the segment register.\n\ | |
5861 | Do you want to stop the program?"), | |
dda83cd7 SM |
5862 | paddress (gdbarch, ir.orig_addr))) |
5863 | return -1; | |
5864 | } | |
cf648174 HZ |
5865 | } |
5866 | else | |
5867 | { | |
dda83cd7 | 5868 | if ((opcode & 1) == 0) |
cf648174 HZ |
5869 | ir.ot = OT_BYTE; |
5870 | else | |
5871 | ir.ot = ir.dflag + OT_WORD; | |
5872 | if (ir.aflag == 2) | |
5873 | { | |
dda83cd7 | 5874 | if (record_read_memory (gdbarch, ir.addr, buf, 8)) |
4ffa4fc7 | 5875 | return -1; |
cf648174 | 5876 | ir.addr += 8; |
60a1502a | 5877 | addr = extract_unsigned_integer (buf, 8, byte_order); |
cf648174 | 5878 | } |
dda83cd7 | 5879 | else if (ir.aflag) |
cf648174 | 5880 | { |
dda83cd7 | 5881 | if (record_read_memory (gdbarch, ir.addr, buf, 4)) |
4ffa4fc7 | 5882 | return -1; |
cf648174 | 5883 | ir.addr += 4; |
dda83cd7 | 5884 | addr = extract_unsigned_integer (buf, 4, byte_order); |
cf648174 | 5885 | } |
dda83cd7 | 5886 | else |
cf648174 | 5887 | { |
dda83cd7 | 5888 | if (record_read_memory (gdbarch, ir.addr, buf, 2)) |
4ffa4fc7 | 5889 | return -1; |
cf648174 | 5890 | ir.addr += 2; |
dda83cd7 | 5891 | addr = extract_unsigned_integer (buf, 2, byte_order); |
cf648174 | 5892 | } |
25ea693b | 5893 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) |
cf648174 | 5894 | return -1; |
dda83cd7 | 5895 | } |
7ad10968 HZ |
5896 | break; |
5897 | ||
a38bba38 | 5898 | case 0xb0: /* mov R, Ib */ |
7ad10968 HZ |
5899 | case 0xb1: |
5900 | case 0xb2: | |
5901 | case 0xb3: | |
5902 | case 0xb4: | |
5903 | case 0xb5: | |
5904 | case 0xb6: | |
5905 | case 0xb7: | |
25ea693b MM |
5906 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir.regmap[X86_RECORD_R8_REGNUM]) |
5907 | ? ((opcode & 0x7) | ir.rex_b) | |
5908 | : ((opcode & 0x7) & 0x3)); | |
7ad10968 HZ |
5909 | break; |
5910 | ||
a38bba38 | 5911 | case 0xb8: /* mov R, Iv */ |
7ad10968 HZ |
5912 | case 0xb9: |
5913 | case 0xba: | |
5914 | case 0xbb: | |
5915 | case 0xbc: | |
5916 | case 0xbd: | |
5917 | case 0xbe: | |
5918 | case 0xbf: | |
25ea693b | 5919 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 0x7) | ir.rex_b); |
7ad10968 HZ |
5920 | break; |
5921 | ||
a38bba38 | 5922 | case 0x91: /* xchg R, EAX */ |
7ad10968 HZ |
5923 | case 0x92: |
5924 | case 0x93: | |
5925 | case 0x94: | |
5926 | case 0x95: | |
5927 | case 0x96: | |
5928 | case 0x97: | |
25ea693b MM |
5929 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
5930 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode & 0x7); | |
7ad10968 HZ |
5931 | break; |
5932 | ||
a38bba38 | 5933 | case 0x86: /* xchg Ev, Gv */ |
7ad10968 HZ |
5934 | case 0x87: |
5935 | if ((opcode & 1) == 0) | |
5936 | ir.ot = OT_BYTE; | |
5937 | else | |
5938 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
5939 | if (i386_record_modrm (&ir)) |
5940 | return -1; | |
7ad10968 HZ |
5941 | if (ir.mod == 3) |
5942 | { | |
86839d38 | 5943 | ir.rm |= ir.rex_b; |
cf648174 HZ |
5944 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) |
5945 | ir.rm &= 0x3; | |
25ea693b | 5946 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 HZ |
5947 | } |
5948 | else | |
5949 | { | |
5950 | if (i386_record_lea_modrm (&ir)) | |
5951 | return -1; | |
5952 | } | |
cf648174 HZ |
5953 | ir.reg |= rex_r; |
5954 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 5955 | ir.reg &= 0x3; |
25ea693b | 5956 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
5957 | break; |
5958 | ||
a38bba38 MS |
5959 | case 0xc4: /* les Gv */ |
5960 | case 0xc5: /* lds Gv */ | |
cf648174 | 5961 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 5962 | { |
cf648174 HZ |
5963 | ir.addr -= 1; |
5964 | goto no_support; | |
5965 | } | |
d3f323f3 | 5966 | /* FALLTHROUGH */ |
a38bba38 MS |
5967 | case 0x0fb2: /* lss Gv */ |
5968 | case 0x0fb4: /* lfs Gv */ | |
5969 | case 0x0fb5: /* lgs Gv */ | |
7ad10968 HZ |
5970 | if (i386_record_modrm (&ir)) |
5971 | return -1; | |
5972 | if (ir.mod == 3) | |
5973 | { | |
5974 | if (opcode > 0xff) | |
5975 | ir.addr -= 3; | |
5976 | else | |
5977 | ir.addr -= 2; | |
5978 | opcode = opcode << 8 | ir.modrm; | |
5979 | goto no_support; | |
5980 | } | |
7ad10968 HZ |
5981 | switch (opcode) |
5982 | { | |
a38bba38 | 5983 | case 0xc4: /* les Gv */ |
425b824a | 5984 | regnum = X86_RECORD_ES_REGNUM; |
7ad10968 | 5985 | break; |
a38bba38 | 5986 | case 0xc5: /* lds Gv */ |
425b824a | 5987 | regnum = X86_RECORD_DS_REGNUM; |
7ad10968 | 5988 | break; |
a38bba38 | 5989 | case 0x0fb2: /* lss Gv */ |
425b824a | 5990 | regnum = X86_RECORD_SS_REGNUM; |
7ad10968 | 5991 | break; |
a38bba38 | 5992 | case 0x0fb4: /* lfs Gv */ |
425b824a | 5993 | regnum = X86_RECORD_FS_REGNUM; |
7ad10968 | 5994 | break; |
a38bba38 | 5995 | case 0x0fb5: /* lgs Gv */ |
425b824a | 5996 | regnum = X86_RECORD_GS_REGNUM; |
7ad10968 HZ |
5997 | break; |
5998 | } | |
25ea693b MM |
5999 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum); |
6000 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
6001 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6002 | break; |
6003 | ||
a38bba38 | 6004 | case 0xc0: /* shifts */ |
7ad10968 HZ |
6005 | case 0xc1: |
6006 | case 0xd0: | |
6007 | case 0xd1: | |
6008 | case 0xd2: | |
6009 | case 0xd3: | |
6010 | if ((opcode & 1) == 0) | |
6011 | ir.ot = OT_BYTE; | |
6012 | else | |
6013 | ir.ot = ir.dflag + OT_WORD; | |
7ad10968 HZ |
6014 | if (i386_record_modrm (&ir)) |
6015 | return -1; | |
7ad10968 HZ |
6016 | if (ir.mod != 3 && (opcode == 0xd2 || opcode == 0xd3)) |
6017 | { | |
6018 | if (i386_record_lea_modrm (&ir)) | |
6019 | return -1; | |
6020 | } | |
6021 | else | |
6022 | { | |
cf648174 HZ |
6023 | ir.rm |= ir.rex_b; |
6024 | if (ir.ot == OT_BYTE && !ir.regmap[X86_RECORD_R8_REGNUM]) | |
7ad10968 | 6025 | ir.rm &= 0x3; |
25ea693b | 6026 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm); |
7ad10968 | 6027 | } |
25ea693b | 6028 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6029 | break; |
6030 | ||
6031 | case 0x0fa4: | |
6032 | case 0x0fa5: | |
6033 | case 0x0fac: | |
6034 | case 0x0fad: | |
6035 | if (i386_record_modrm (&ir)) | |
6036 | return -1; | |
6037 | if (ir.mod == 3) | |
6038 | { | |
25ea693b | 6039 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm)) |
7ad10968 HZ |
6040 | return -1; |
6041 | } | |
6042 | else | |
6043 | { | |
6044 | if (i386_record_lea_modrm (&ir)) | |
6045 | return -1; | |
6046 | } | |
6047 | break; | |
6048 | ||
a38bba38 | 6049 | case 0xd8: /* Floats. */ |
7ad10968 HZ |
6050 | case 0xd9: |
6051 | case 0xda: | |
6052 | case 0xdb: | |
6053 | case 0xdc: | |
6054 | case 0xdd: | |
6055 | case 0xde: | |
6056 | case 0xdf: | |
6057 | if (i386_record_modrm (&ir)) | |
6058 | return -1; | |
6059 | ir.reg |= ((opcode & 7) << 3); | |
6060 | if (ir.mod != 3) | |
6061 | { | |
1777feb0 | 6062 | /* Memory. */ |
955db0c0 | 6063 | uint64_t addr64; |
7ad10968 | 6064 | |
955db0c0 | 6065 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 HZ |
6066 | return -1; |
6067 | switch (ir.reg) | |
6068 | { | |
7ad10968 | 6069 | case 0x02: |
dda83cd7 SM |
6070 | case 0x12: |
6071 | case 0x22: | |
6072 | case 0x32: | |
0289bdd7 | 6073 | /* For fcom, ficom nothing to do. */ |
dda83cd7 | 6074 | break; |
7ad10968 | 6075 | case 0x03: |
dda83cd7 SM |
6076 | case 0x13: |
6077 | case 0x23: | |
6078 | case 0x33: | |
0289bdd7 | 6079 | /* For fcomp, ficomp pop FPU stack, store all. */ |
dda83cd7 SM |
6080 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6081 | return -1; | |
6082 | break; | |
6083 | case 0x00: | |
6084 | case 0x01: | |
7ad10968 HZ |
6085 | case 0x04: |
6086 | case 0x05: | |
6087 | case 0x06: | |
6088 | case 0x07: | |
6089 | case 0x10: | |
6090 | case 0x11: | |
7ad10968 HZ |
6091 | case 0x14: |
6092 | case 0x15: | |
6093 | case 0x16: | |
6094 | case 0x17: | |
6095 | case 0x20: | |
6096 | case 0x21: | |
7ad10968 HZ |
6097 | case 0x24: |
6098 | case 0x25: | |
6099 | case 0x26: | |
6100 | case 0x27: | |
6101 | case 0x30: | |
6102 | case 0x31: | |
7ad10968 HZ |
6103 | case 0x34: |
6104 | case 0x35: | |
6105 | case 0x36: | |
6106 | case 0x37: | |
dda83cd7 SM |
6107 | /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul, |
6108 | fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension | |
6109 | of code, always affects st(0) register. */ | |
6110 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6111 | return -1; | |
7ad10968 HZ |
6112 | break; |
6113 | case 0x08: | |
6114 | case 0x0a: | |
6115 | case 0x0b: | |
6116 | case 0x18: | |
6117 | case 0x19: | |
6118 | case 0x1a: | |
6119 | case 0x1b: | |
dda83cd7 | 6120 | case 0x1d: |
7ad10968 HZ |
6121 | case 0x28: |
6122 | case 0x29: | |
6123 | case 0x2a: | |
6124 | case 0x2b: | |
6125 | case 0x38: | |
6126 | case 0x39: | |
6127 | case 0x3a: | |
6128 | case 0x3b: | |
dda83cd7 SM |
6129 | case 0x3c: |
6130 | case 0x3d: | |
7ad10968 HZ |
6131 | switch (ir.reg & 7) |
6132 | { | |
6133 | case 0: | |
0289bdd7 MS |
6134 | /* Handling fld, fild. */ |
6135 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6136 | return -1; | |
7ad10968 HZ |
6137 | break; |
6138 | case 1: | |
6139 | switch (ir.reg >> 4) | |
6140 | { | |
6141 | case 0: | |
25ea693b | 6142 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 HZ |
6143 | return -1; |
6144 | break; | |
6145 | case 2: | |
25ea693b | 6146 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 HZ |
6147 | return -1; |
6148 | break; | |
6149 | case 3: | |
0289bdd7 | 6150 | break; |
7ad10968 | 6151 | default: |
25ea693b | 6152 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6153 | return -1; |
6154 | break; | |
6155 | } | |
6156 | break; | |
6157 | default: | |
6158 | switch (ir.reg >> 4) | |
6159 | { | |
6160 | case 0: | |
25ea693b | 6161 | if (record_full_arch_list_add_mem (addr64, 4)) |
0289bdd7 MS |
6162 | return -1; |
6163 | if (3 == (ir.reg & 7)) | |
6164 | { | |
6165 | /* For fstp m32fp. */ | |
6166 | if (i386_record_floats (gdbarch, &ir, | |
6167 | I386_SAVE_FPU_REGS)) | |
6168 | return -1; | |
6169 | } | |
6170 | break; | |
7ad10968 | 6171 | case 1: |
25ea693b | 6172 | if (record_full_arch_list_add_mem (addr64, 4)) |
7ad10968 | 6173 | return -1; |
0289bdd7 MS |
6174 | if ((3 == (ir.reg & 7)) |
6175 | || (5 == (ir.reg & 7)) | |
6176 | || (7 == (ir.reg & 7))) | |
6177 | { | |
6178 | /* For fstp insn. */ | |
6179 | if (i386_record_floats (gdbarch, &ir, | |
6180 | I386_SAVE_FPU_REGS)) | |
6181 | return -1; | |
6182 | } | |
7ad10968 HZ |
6183 | break; |
6184 | case 2: | |
25ea693b | 6185 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6186 | return -1; |
0289bdd7 MS |
6187 | if (3 == (ir.reg & 7)) |
6188 | { | |
6189 | /* For fstp m64fp. */ | |
6190 | if (i386_record_floats (gdbarch, &ir, | |
6191 | I386_SAVE_FPU_REGS)) | |
6192 | return -1; | |
6193 | } | |
7ad10968 HZ |
6194 | break; |
6195 | case 3: | |
0289bdd7 MS |
6196 | if ((3 <= (ir.reg & 7)) && (6 <= (ir.reg & 7))) |
6197 | { | |
6198 | /* For fistp, fbld, fild, fbstp. */ | |
6199 | if (i386_record_floats (gdbarch, &ir, | |
6200 | I386_SAVE_FPU_REGS)) | |
6201 | return -1; | |
6202 | } | |
6203 | /* Fall through */ | |
7ad10968 | 6204 | default: |
25ea693b | 6205 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 HZ |
6206 | return -1; |
6207 | break; | |
6208 | } | |
6209 | break; | |
6210 | } | |
6211 | break; | |
6212 | case 0x0c: | |
dda83cd7 SM |
6213 | /* Insn fldenv. */ |
6214 | if (i386_record_floats (gdbarch, &ir, | |
6215 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6216 | return -1; | |
6217 | break; | |
7ad10968 | 6218 | case 0x0d: |
dda83cd7 SM |
6219 | /* Insn fldcw. */ |
6220 | if (i386_record_floats (gdbarch, &ir, I387_FCTRL_REGNUM (tdep))) | |
6221 | return -1; | |
6222 | break; | |
7ad10968 | 6223 | case 0x2c: |
dda83cd7 SM |
6224 | /* Insn frstor. */ |
6225 | if (i386_record_floats (gdbarch, &ir, | |
6226 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6227 | return -1; | |
7ad10968 HZ |
6228 | break; |
6229 | case 0x0e: | |
6230 | if (ir.dflag) | |
6231 | { | |
25ea693b | 6232 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 HZ |
6233 | return -1; |
6234 | } | |
6235 | else | |
6236 | { | |
25ea693b | 6237 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 HZ |
6238 | return -1; |
6239 | } | |
6240 | break; | |
6241 | case 0x0f: | |
6242 | case 0x2f: | |
25ea693b | 6243 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 6244 | return -1; |
dda83cd7 SM |
6245 | /* Insn fstp, fbstp. */ |
6246 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6247 | return -1; | |
7ad10968 HZ |
6248 | break; |
6249 | case 0x1f: | |
6250 | case 0x3e: | |
25ea693b | 6251 | if (record_full_arch_list_add_mem (addr64, 10)) |
7ad10968 HZ |
6252 | return -1; |
6253 | break; | |
6254 | case 0x2e: | |
6255 | if (ir.dflag) | |
6256 | { | |
25ea693b | 6257 | if (record_full_arch_list_add_mem (addr64, 28)) |
7ad10968 | 6258 | return -1; |
955db0c0 | 6259 | addr64 += 28; |
7ad10968 HZ |
6260 | } |
6261 | else | |
6262 | { | |
25ea693b | 6263 | if (record_full_arch_list_add_mem (addr64, 14)) |
7ad10968 | 6264 | return -1; |
955db0c0 | 6265 | addr64 += 14; |
7ad10968 | 6266 | } |
25ea693b | 6267 | if (record_full_arch_list_add_mem (addr64, 80)) |
7ad10968 | 6268 | return -1; |
0289bdd7 MS |
6269 | /* Insn fsave. */ |
6270 | if (i386_record_floats (gdbarch, &ir, | |
6271 | I386_SAVE_FPU_ENV_REG_STACK)) | |
6272 | return -1; | |
7ad10968 HZ |
6273 | break; |
6274 | case 0x3f: | |
25ea693b | 6275 | if (record_full_arch_list_add_mem (addr64, 8)) |
7ad10968 | 6276 | return -1; |
0289bdd7 MS |
6277 | /* Insn fistp. */ |
6278 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) | |
6279 | return -1; | |
7ad10968 HZ |
6280 | break; |
6281 | default: | |
6282 | ir.addr -= 2; | |
6283 | opcode = opcode << 8 | ir.modrm; | |
6284 | goto no_support; | |
6285 | break; | |
6286 | } | |
6287 | } | |
0289bdd7 MS |
6288 | /* Opcode is an extension of modR/M byte. */ |
6289 | else | |
dda83cd7 | 6290 | { |
0289bdd7 MS |
6291 | switch (opcode) |
6292 | { | |
6293 | case 0xd8: | |
6294 | if (i386_record_floats (gdbarch, &ir, I387_ST0_REGNUM (tdep))) | |
6295 | return -1; | |
6296 | break; | |
6297 | case 0xd9: | |
6298 | if (0x0c == (ir.modrm >> 4)) | |
6299 | { | |
6300 | if ((ir.modrm & 0x0f) <= 7) | |
6301 | { | |
6302 | if (i386_record_floats (gdbarch, &ir, | |
6303 | I386_SAVE_FPU_REGS)) | |
6304 | return -1; | |
6305 | } | |
dda83cd7 | 6306 | else |
0289bdd7 MS |
6307 | { |
6308 | if (i386_record_floats (gdbarch, &ir, | |
6309 | I387_ST0_REGNUM (tdep))) | |
6310 | return -1; | |
6311 | /* If only st(0) is changing, then we have already | |
6312 | recorded. */ | |
6313 | if ((ir.modrm & 0x0f) - 0x08) | |
6314 | { | |
6315 | if (i386_record_floats (gdbarch, &ir, | |
6316 | I387_ST0_REGNUM (tdep) + | |
6317 | ((ir.modrm & 0x0f) - 0x08))) | |
6318 | return -1; | |
6319 | } | |
6320 | } | |
6321 | } | |
dda83cd7 SM |
6322 | else |
6323 | { | |
0289bdd7 MS |
6324 | switch (ir.modrm) |
6325 | { | |
6326 | case 0xe0: | |
6327 | case 0xe1: | |
6328 | case 0xf0: | |
6329 | case 0xf5: | |
6330 | case 0xf8: | |
6331 | case 0xfa: | |
6332 | case 0xfc: | |
6333 | case 0xfe: | |
6334 | case 0xff: | |
6335 | if (i386_record_floats (gdbarch, &ir, | |
6336 | I387_ST0_REGNUM (tdep))) | |
6337 | return -1; | |
6338 | break; | |
6339 | case 0xf1: | |
6340 | case 0xf2: | |
6341 | case 0xf3: | |
6342 | case 0xf4: | |
6343 | case 0xf6: | |
6344 | case 0xf7: | |
6345 | case 0xe8: | |
6346 | case 0xe9: | |
6347 | case 0xea: | |
6348 | case 0xeb: | |
6349 | case 0xec: | |
6350 | case 0xed: | |
6351 | case 0xee: | |
6352 | case 0xf9: | |
6353 | case 0xfb: | |
6354 | if (i386_record_floats (gdbarch, &ir, | |
6355 | I386_SAVE_FPU_REGS)) | |
6356 | return -1; | |
6357 | break; | |
6358 | case 0xfd: | |
6359 | if (i386_record_floats (gdbarch, &ir, | |
6360 | I387_ST0_REGNUM (tdep))) | |
6361 | return -1; | |
6362 | if (i386_record_floats (gdbarch, &ir, | |
6363 | I387_ST0_REGNUM (tdep) + 1)) | |
6364 | return -1; | |
6365 | break; | |
6366 | } | |
6367 | } | |
dda83cd7 SM |
6368 | break; |
6369 | case 0xda: | |
6370 | if (0xe9 == ir.modrm) | |
6371 | { | |
0289bdd7 MS |
6372 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6373 | return -1; | |
dda83cd7 SM |
6374 | } |
6375 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6376 | { | |
0289bdd7 MS |
6377 | if (i386_record_floats (gdbarch, &ir, |
6378 | I387_ST0_REGNUM (tdep))) | |
6379 | return -1; | |
6380 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6381 | { | |
6382 | if (i386_record_floats (gdbarch, &ir, | |
6383 | I387_ST0_REGNUM (tdep) + | |
6384 | (ir.modrm & 0x0f))) | |
6385 | return -1; | |
6386 | } | |
6387 | else if ((ir.modrm & 0x0f) - 0x08) | |
6388 | { | |
6389 | if (i386_record_floats (gdbarch, &ir, | |
6390 | I387_ST0_REGNUM (tdep) + | |
6391 | ((ir.modrm & 0x0f) - 0x08))) | |
6392 | return -1; | |
6393 | } | |
dda83cd7 SM |
6394 | } |
6395 | break; | |
6396 | case 0xdb: | |
6397 | if (0xe3 == ir.modrm) | |
6398 | { | |
0289bdd7 MS |
6399 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_ENV)) |
6400 | return -1; | |
dda83cd7 SM |
6401 | } |
6402 | else if ((0x0c == ir.modrm >> 4) || (0x0d == ir.modrm >> 4)) | |
6403 | { | |
0289bdd7 MS |
6404 | if (i386_record_floats (gdbarch, &ir, |
6405 | I387_ST0_REGNUM (tdep))) | |
6406 | return -1; | |
6407 | if (((ir.modrm & 0x0f) > 0) && ((ir.modrm & 0x0f) <= 7)) | |
6408 | { | |
6409 | if (i386_record_floats (gdbarch, &ir, | |
6410 | I387_ST0_REGNUM (tdep) + | |
6411 | (ir.modrm & 0x0f))) | |
6412 | return -1; | |
6413 | } | |
6414 | else if ((ir.modrm & 0x0f) - 0x08) | |
6415 | { | |
6416 | if (i386_record_floats (gdbarch, &ir, | |
6417 | I387_ST0_REGNUM (tdep) + | |
6418 | ((ir.modrm & 0x0f) - 0x08))) | |
6419 | return -1; | |
6420 | } | |
dda83cd7 SM |
6421 | } |
6422 | break; | |
6423 | case 0xdc: | |
6424 | if ((0x0c == ir.modrm >> 4) | |
0289bdd7 MS |
6425 | || (0x0d == ir.modrm >> 4) |
6426 | || (0x0f == ir.modrm >> 4)) | |
dda83cd7 | 6427 | { |
0289bdd7 MS |
6428 | if ((ir.modrm & 0x0f) <= 7) |
6429 | { | |
6430 | if (i386_record_floats (gdbarch, &ir, | |
6431 | I387_ST0_REGNUM (tdep) + | |
6432 | (ir.modrm & 0x0f))) | |
6433 | return -1; | |
6434 | } | |
6435 | else | |
6436 | { | |
6437 | if (i386_record_floats (gdbarch, &ir, | |
6438 | I387_ST0_REGNUM (tdep) + | |
6439 | ((ir.modrm & 0x0f) - 0x08))) | |
6440 | return -1; | |
6441 | } | |
dda83cd7 | 6442 | } |
0289bdd7 | 6443 | break; |
dda83cd7 SM |
6444 | case 0xdd: |
6445 | if (0x0c == ir.modrm >> 4) | |
6446 | { | |
6447 | if (i386_record_floats (gdbarch, &ir, | |
6448 | I387_FTAG_REGNUM (tdep))) | |
6449 | return -1; | |
6450 | } | |
6451 | else if ((0x0d == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6452 | { | |
6453 | if ((ir.modrm & 0x0f) <= 7) | |
6454 | { | |
0289bdd7 MS |
6455 | if (i386_record_floats (gdbarch, &ir, |
6456 | I387_ST0_REGNUM (tdep) + | |
6457 | (ir.modrm & 0x0f))) | |
6458 | return -1; | |
dda83cd7 SM |
6459 | } |
6460 | else | |
6461 | { | |
6462 | if (i386_record_floats (gdbarch, &ir, | |
0289bdd7 | 6463 | I386_SAVE_FPU_REGS)) |
dda83cd7 SM |
6464 | return -1; |
6465 | } | |
6466 | } | |
6467 | break; | |
6468 | case 0xde: | |
6469 | if ((0x0c == ir.modrm >> 4) | |
0289bdd7 MS |
6470 | || (0x0e == ir.modrm >> 4) |
6471 | || (0x0f == ir.modrm >> 4) | |
6472 | || (0xd9 == ir.modrm)) | |
dda83cd7 | 6473 | { |
0289bdd7 MS |
6474 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6475 | return -1; | |
dda83cd7 SM |
6476 | } |
6477 | break; | |
6478 | case 0xdf: | |
6479 | if (0xe0 == ir.modrm) | |
6480 | { | |
25ea693b MM |
6481 | if (record_full_arch_list_add_reg (ir.regcache, |
6482 | I386_EAX_REGNUM)) | |
0289bdd7 | 6483 | return -1; |
dda83cd7 SM |
6484 | } |
6485 | else if ((0x0f == ir.modrm >> 4) || (0x0e == ir.modrm >> 4)) | |
6486 | { | |
0289bdd7 MS |
6487 | if (i386_record_floats (gdbarch, &ir, I386_SAVE_FPU_REGS)) |
6488 | return -1; | |
dda83cd7 SM |
6489 | } |
6490 | break; | |
0289bdd7 MS |
6491 | } |
6492 | } | |
7ad10968 | 6493 | break; |
7ad10968 | 6494 | /* string ops */ |
a38bba38 | 6495 | case 0xa4: /* movsS */ |
7ad10968 | 6496 | case 0xa5: |
a38bba38 | 6497 | case 0xaa: /* stosS */ |
7ad10968 | 6498 | case 0xab: |
a38bba38 | 6499 | case 0x6c: /* insS */ |
7ad10968 | 6500 | case 0x6d: |
cf648174 | 6501 | regcache_raw_read_unsigned (ir.regcache, |
dda83cd7 SM |
6502 | ir.regmap[X86_RECORD_RECX_REGNUM], |
6503 | &addr); | |
648d0c8b | 6504 | if (addr) |
dda83cd7 SM |
6505 | { |
6506 | ULONGEST es, ds; | |
77d7dc92 | 6507 | |
dda83cd7 | 6508 | if ((opcode & 1) == 0) |
77d7dc92 | 6509 | ir.ot = OT_BYTE; |
dda83cd7 | 6510 | else |
77d7dc92 | 6511 | ir.ot = ir.dflag + OT_WORD; |
dda83cd7 SM |
6512 | regcache_raw_read_unsigned (ir.regcache, |
6513 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
6514 | &addr); | |
6515 | ||
6516 | regcache_raw_read_unsigned (ir.regcache, | |
6517 | ir.regmap[X86_RECORD_ES_REGNUM], | |
6518 | &es); | |
6519 | regcache_raw_read_unsigned (ir.regcache, | |
6520 | ir.regmap[X86_RECORD_DS_REGNUM], | |
6521 | &ds); | |
6522 | if (ir.aflag && (es != ds)) | |
6523 | { | |
6524 | /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */ | |
6525 | if (record_full_memory_query) | |
6526 | { | |
6527 | if (yquery (_("\ | |
bb08c432 HZ |
6528 | Process record ignores the memory change of instruction at address %s\n\ |
6529 | because it can't get the value of the segment register.\n\ | |
6530 | Do you want to stop the program?"), | |
dda83cd7 SM |
6531 | paddress (gdbarch, ir.orig_addr))) |
6532 | return -1; | |
6533 | } | |
6534 | } | |
6535 | else | |
6536 | { | |
6537 | if (record_full_arch_list_add_mem (addr, 1 << ir.ot)) | |
6538 | return -1; | |
6539 | } | |
6540 | ||
6541 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) | |
6542 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
6543 | if (opcode == 0xa4 || opcode == 0xa5) | |
6544 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
6545 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
6546 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
77d7dc92 | 6547 | } |
cf648174 | 6548 | break; |
7ad10968 | 6549 | |
a38bba38 | 6550 | case 0xa6: /* cmpsS */ |
cf648174 | 6551 | case 0xa7: |
25ea693b MM |
6552 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
6553 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
cf648174 | 6554 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6555 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6556 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6557 | break; |
6558 | ||
a38bba38 | 6559 | case 0xac: /* lodsS */ |
7ad10968 | 6560 | case 0xad: |
25ea693b MM |
6561 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6562 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7ad10968 | 6563 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6564 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6565 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6566 | break; |
6567 | ||
a38bba38 | 6568 | case 0xae: /* scasS */ |
7ad10968 | 6569 | case 0xaf: |
25ea693b | 6570 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); |
7ad10968 | 6571 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6572 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6573 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6574 | break; |
6575 | ||
a38bba38 | 6576 | case 0x6e: /* outsS */ |
cf648174 | 6577 | case 0x6f: |
25ea693b | 6578 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); |
7ad10968 | 6579 | if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) |
dda83cd7 | 6580 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
25ea693b | 6581 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6582 | break; |
6583 | ||
a38bba38 | 6584 | case 0xe4: /* port I/O */ |
7ad10968 HZ |
6585 | case 0xe5: |
6586 | case 0xec: | |
6587 | case 0xed: | |
25ea693b MM |
6588 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6589 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6590 | break; |
6591 | ||
6592 | case 0xe6: | |
6593 | case 0xe7: | |
6594 | case 0xee: | |
6595 | case 0xef: | |
6596 | break; | |
6597 | ||
6598 | /* control */ | |
a38bba38 MS |
6599 | case 0xc2: /* ret im */ |
6600 | case 0xc3: /* ret */ | |
25ea693b MM |
6601 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6602 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
cf648174 HZ |
6603 | break; |
6604 | ||
a38bba38 MS |
6605 | case 0xca: /* lret im */ |
6606 | case 0xcb: /* lret */ | |
6607 | case 0xcf: /* iret */ | |
25ea693b MM |
6608 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
6609 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
6610 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6611 | break; |
6612 | ||
a38bba38 | 6613 | case 0xe8: /* call im */ |
cf648174 | 6614 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 6615 | ir.dflag = 2; |
cf648174 | 6616 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6617 | return -1; |
7ad10968 HZ |
6618 | break; |
6619 | ||
a38bba38 | 6620 | case 0x9a: /* lcall im */ |
cf648174 | 6621 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6622 | { |
6623 | ir.addr -= 1; | |
6624 | goto no_support; | |
6625 | } | |
25ea693b | 6626 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM); |
cf648174 | 6627 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6628 | return -1; |
7ad10968 HZ |
6629 | break; |
6630 | ||
a38bba38 MS |
6631 | case 0xe9: /* jmp im */ |
6632 | case 0xea: /* ljmp im */ | |
6633 | case 0xeb: /* jmp Jb */ | |
6634 | case 0x70: /* jcc Jb */ | |
7ad10968 HZ |
6635 | case 0x71: |
6636 | case 0x72: | |
6637 | case 0x73: | |
6638 | case 0x74: | |
6639 | case 0x75: | |
6640 | case 0x76: | |
6641 | case 0x77: | |
6642 | case 0x78: | |
6643 | case 0x79: | |
6644 | case 0x7a: | |
6645 | case 0x7b: | |
6646 | case 0x7c: | |
6647 | case 0x7d: | |
6648 | case 0x7e: | |
6649 | case 0x7f: | |
a38bba38 | 6650 | case 0x0f80: /* jcc Jv */ |
7ad10968 HZ |
6651 | case 0x0f81: |
6652 | case 0x0f82: | |
6653 | case 0x0f83: | |
6654 | case 0x0f84: | |
6655 | case 0x0f85: | |
6656 | case 0x0f86: | |
6657 | case 0x0f87: | |
6658 | case 0x0f88: | |
6659 | case 0x0f89: | |
6660 | case 0x0f8a: | |
6661 | case 0x0f8b: | |
6662 | case 0x0f8c: | |
6663 | case 0x0f8d: | |
6664 | case 0x0f8e: | |
6665 | case 0x0f8f: | |
6666 | break; | |
6667 | ||
a38bba38 | 6668 | case 0x0f90: /* setcc Gv */ |
7ad10968 HZ |
6669 | case 0x0f91: |
6670 | case 0x0f92: | |
6671 | case 0x0f93: | |
6672 | case 0x0f94: | |
6673 | case 0x0f95: | |
6674 | case 0x0f96: | |
6675 | case 0x0f97: | |
6676 | case 0x0f98: | |
6677 | case 0x0f99: | |
6678 | case 0x0f9a: | |
6679 | case 0x0f9b: | |
6680 | case 0x0f9c: | |
6681 | case 0x0f9d: | |
6682 | case 0x0f9e: | |
6683 | case 0x0f9f: | |
25ea693b | 6684 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6685 | ir.ot = OT_BYTE; |
6686 | if (i386_record_modrm (&ir)) | |
6687 | return -1; | |
6688 | if (ir.mod == 3) | |
dda83cd7 | 6689 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b ? (ir.rm | ir.rex_b) |
25ea693b | 6690 | : (ir.rm & 0x3)); |
7ad10968 HZ |
6691 | else |
6692 | { | |
6693 | if (i386_record_lea_modrm (&ir)) | |
6694 | return -1; | |
6695 | } | |
6696 | break; | |
6697 | ||
a38bba38 | 6698 | case 0x0f40: /* cmov Gv, Ev */ |
7ad10968 HZ |
6699 | case 0x0f41: |
6700 | case 0x0f42: | |
6701 | case 0x0f43: | |
6702 | case 0x0f44: | |
6703 | case 0x0f45: | |
6704 | case 0x0f46: | |
6705 | case 0x0f47: | |
6706 | case 0x0f48: | |
6707 | case 0x0f49: | |
6708 | case 0x0f4a: | |
6709 | case 0x0f4b: | |
6710 | case 0x0f4c: | |
6711 | case 0x0f4d: | |
6712 | case 0x0f4e: | |
6713 | case 0x0f4f: | |
6714 | if (i386_record_modrm (&ir)) | |
6715 | return -1; | |
cf648174 | 6716 | ir.reg |= rex_r; |
7ad10968 HZ |
6717 | if (ir.dflag == OT_BYTE) |
6718 | ir.reg &= 0x3; | |
25ea693b | 6719 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
7ad10968 HZ |
6720 | break; |
6721 | ||
6722 | /* flags */ | |
a38bba38 | 6723 | case 0x9c: /* pushf */ |
25ea693b | 6724 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 6725 | if (ir.regmap[X86_RECORD_R8_REGNUM] && ir.dflag) |
dda83cd7 | 6726 | ir.dflag = 2; |
cf648174 | 6727 | if (i386_record_push (&ir, 1 << (ir.dflag + 1))) |
dda83cd7 | 6728 | return -1; |
7ad10968 HZ |
6729 | break; |
6730 | ||
a38bba38 | 6731 | case 0x9d: /* popf */ |
25ea693b MM |
6732 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); |
6733 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6734 | break; |
6735 | ||
a38bba38 | 6736 | case 0x9e: /* sahf */ |
cf648174 | 6737 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6738 | { |
6739 | ir.addr -= 1; | |
6740 | goto no_support; | |
6741 | } | |
d3f323f3 | 6742 | /* FALLTHROUGH */ |
a38bba38 MS |
6743 | case 0xf5: /* cmc */ |
6744 | case 0xf8: /* clc */ | |
6745 | case 0xf9: /* stc */ | |
6746 | case 0xfc: /* cld */ | |
6747 | case 0xfd: /* std */ | |
25ea693b | 6748 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6749 | break; |
6750 | ||
a38bba38 | 6751 | case 0x9f: /* lahf */ |
cf648174 | 6752 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6753 | { |
6754 | ir.addr -= 1; | |
6755 | goto no_support; | |
6756 | } | |
25ea693b MM |
6757 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
6758 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7ad10968 HZ |
6759 | break; |
6760 | ||
6761 | /* bit operations */ | |
a38bba38 | 6762 | case 0x0fba: /* bt/bts/btr/btc Gv, im */ |
7ad10968 HZ |
6763 | ir.ot = ir.dflag + OT_WORD; |
6764 | if (i386_record_modrm (&ir)) | |
6765 | return -1; | |
6766 | if (ir.reg < 4) | |
6767 | { | |
cf648174 | 6768 | ir.addr -= 2; |
7ad10968 HZ |
6769 | opcode = opcode << 8 | ir.modrm; |
6770 | goto no_support; | |
6771 | } | |
cf648174 | 6772 | if (ir.reg != 4) |
7ad10968 | 6773 | { |
dda83cd7 SM |
6774 | if (ir.mod == 3) |
6775 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
7ad10968 HZ |
6776 | else |
6777 | { | |
cf648174 | 6778 | if (i386_record_lea_modrm (&ir)) |
7ad10968 HZ |
6779 | return -1; |
6780 | } | |
6781 | } | |
25ea693b | 6782 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6783 | break; |
6784 | ||
a38bba38 | 6785 | case 0x0fa3: /* bt Gv, Ev */ |
25ea693b | 6786 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
6787 | break; |
6788 | ||
a38bba38 MS |
6789 | case 0x0fab: /* bts */ |
6790 | case 0x0fb3: /* btr */ | |
6791 | case 0x0fbb: /* btc */ | |
cf648174 HZ |
6792 | ir.ot = ir.dflag + OT_WORD; |
6793 | if (i386_record_modrm (&ir)) | |
dda83cd7 | 6794 | return -1; |
cf648174 | 6795 | if (ir.mod == 3) |
dda83cd7 | 6796 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
cf648174 | 6797 | else |
dda83cd7 SM |
6798 | { |
6799 | uint64_t addr64; | |
6800 | if (i386_record_lea_modrm_addr (&ir, &addr64)) | |
6801 | return -1; | |
6802 | regcache_raw_read_unsigned (ir.regcache, | |
6803 | ir.regmap[ir.reg | rex_r], | |
6804 | &addr); | |
6805 | switch (ir.dflag) | |
6806 | { | |
6807 | case 0: | |
6808 | addr64 += ((int16_t) addr >> 4) << 4; | |
6809 | break; | |
6810 | case 1: | |
6811 | addr64 += ((int32_t) addr >> 5) << 5; | |
6812 | break; | |
6813 | case 2: | |
6814 | addr64 += ((int64_t) addr >> 6) << 6; | |
6815 | break; | |
6816 | } | |
6817 | if (record_full_arch_list_add_mem (addr64, 1 << ir.ot)) | |
6818 | return -1; | |
6819 | if (i386_record_lea_modrm (&ir)) | |
6820 | return -1; | |
6821 | } | |
25ea693b | 6822 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
6823 | break; |
6824 | ||
a38bba38 MS |
6825 | case 0x0fbc: /* bsf */ |
6826 | case 0x0fbd: /* bsr */ | |
25ea693b MM |
6827 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
6828 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6829 | break; |
6830 | ||
6831 | /* bcd */ | |
a38bba38 MS |
6832 | case 0x27: /* daa */ |
6833 | case 0x2f: /* das */ | |
6834 | case 0x37: /* aaa */ | |
6835 | case 0x3f: /* aas */ | |
6836 | case 0xd4: /* aam */ | |
6837 | case 0xd5: /* aad */ | |
cf648174 | 6838 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6839 | { |
6840 | ir.addr -= 1; | |
6841 | goto no_support; | |
6842 | } | |
25ea693b MM |
6843 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6844 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6845 | break; |
6846 | ||
6847 | /* misc */ | |
a38bba38 | 6848 | case 0x90: /* nop */ |
7ad10968 HZ |
6849 | if (prefixes & PREFIX_LOCK) |
6850 | { | |
6851 | ir.addr -= 1; | |
6852 | goto no_support; | |
6853 | } | |
6854 | break; | |
6855 | ||
a38bba38 | 6856 | case 0x9b: /* fwait */ |
4ffa4fc7 PA |
6857 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
6858 | return -1; | |
425b824a | 6859 | opcode = (uint32_t) opcode8; |
0289bdd7 MS |
6860 | ir.addr++; |
6861 | goto reswitch; | |
7ad10968 HZ |
6862 | break; |
6863 | ||
7ad10968 | 6864 | /* XXX */ |
a38bba38 | 6865 | case 0xcc: /* int3 */ |
6cb06a8c TT |
6866 | gdb_printf (gdb_stderr, |
6867 | _("Process record does not support instruction " | |
6868 | "int3.\n")); | |
7ad10968 HZ |
6869 | ir.addr -= 1; |
6870 | goto no_support; | |
6871 | break; | |
6872 | ||
7ad10968 | 6873 | /* XXX */ |
a38bba38 | 6874 | case 0xcd: /* int */ |
7ad10968 HZ |
6875 | { |
6876 | int ret; | |
425b824a | 6877 | uint8_t interrupt; |
4ffa4fc7 PA |
6878 | if (record_read_memory (gdbarch, ir.addr, &interrupt, 1)) |
6879 | return -1; | |
7ad10968 | 6880 | ir.addr++; |
425b824a | 6881 | if (interrupt != 0x80 |
a3c4230a | 6882 | || tdep->i386_intx80_record == NULL) |
7ad10968 | 6883 | { |
6cb06a8c TT |
6884 | gdb_printf (gdb_stderr, |
6885 | _("Process record does not support " | |
6886 | "instruction int 0x%02x.\n"), | |
6887 | interrupt); | |
7ad10968 HZ |
6888 | ir.addr -= 2; |
6889 | goto no_support; | |
6890 | } | |
a3c4230a | 6891 | ret = tdep->i386_intx80_record (ir.regcache); |
7ad10968 HZ |
6892 | if (ret) |
6893 | return ret; | |
6894 | } | |
6895 | break; | |
6896 | ||
7ad10968 | 6897 | /* XXX */ |
a38bba38 | 6898 | case 0xce: /* into */ |
6cb06a8c TT |
6899 | gdb_printf (gdb_stderr, |
6900 | _("Process record does not support " | |
6901 | "instruction into.\n")); | |
7ad10968 HZ |
6902 | ir.addr -= 1; |
6903 | goto no_support; | |
6904 | break; | |
6905 | ||
a38bba38 MS |
6906 | case 0xfa: /* cli */ |
6907 | case 0xfb: /* sti */ | |
7ad10968 HZ |
6908 | break; |
6909 | ||
a38bba38 | 6910 | case 0x62: /* bound */ |
6cb06a8c TT |
6911 | gdb_printf (gdb_stderr, |
6912 | _("Process record does not support " | |
6913 | "instruction bound.\n")); | |
7ad10968 HZ |
6914 | ir.addr -= 1; |
6915 | goto no_support; | |
6916 | break; | |
6917 | ||
a38bba38 | 6918 | case 0x0fc8: /* bswap reg */ |
7ad10968 HZ |
6919 | case 0x0fc9: |
6920 | case 0x0fca: | |
6921 | case 0x0fcb: | |
6922 | case 0x0fcc: | |
6923 | case 0x0fcd: | |
6924 | case 0x0fce: | |
6925 | case 0x0fcf: | |
25ea693b | 6926 | I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode & 7) | ir.rex_b); |
7ad10968 HZ |
6927 | break; |
6928 | ||
a38bba38 | 6929 | case 0xd6: /* salc */ |
cf648174 | 6930 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
6931 | { |
6932 | ir.addr -= 1; | |
6933 | goto no_support; | |
6934 | } | |
25ea693b MM |
6935 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6936 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6937 | break; |
6938 | ||
a38bba38 MS |
6939 | case 0xe0: /* loopnz */ |
6940 | case 0xe1: /* loopz */ | |
6941 | case 0xe2: /* loop */ | |
6942 | case 0xe3: /* jecxz */ | |
25ea693b MM |
6943 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); |
6944 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
6945 | break; |
6946 | ||
a38bba38 | 6947 | case 0x0f30: /* wrmsr */ |
6cb06a8c TT |
6948 | gdb_printf (gdb_stderr, |
6949 | _("Process record does not support " | |
6950 | "instruction wrmsr.\n")); | |
7ad10968 HZ |
6951 | ir.addr -= 2; |
6952 | goto no_support; | |
6953 | break; | |
6954 | ||
a38bba38 | 6955 | case 0x0f32: /* rdmsr */ |
6cb06a8c TT |
6956 | gdb_printf (gdb_stderr, |
6957 | _("Process record does not support " | |
6958 | "instruction rdmsr.\n")); | |
7ad10968 HZ |
6959 | ir.addr -= 2; |
6960 | goto no_support; | |
6961 | break; | |
6962 | ||
a38bba38 | 6963 | case 0x0f31: /* rdtsc */ |
25ea693b MM |
6964 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
6965 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7ad10968 HZ |
6966 | break; |
6967 | ||
a38bba38 | 6968 | case 0x0f34: /* sysenter */ |
7ad10968 HZ |
6969 | { |
6970 | int ret; | |
dda83cd7 SM |
6971 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
6972 | { | |
6973 | ir.addr -= 2; | |
6974 | goto no_support; | |
6975 | } | |
a3c4230a | 6976 | if (tdep->i386_sysenter_record == NULL) |
7ad10968 | 6977 | { |
6cb06a8c TT |
6978 | gdb_printf (gdb_stderr, |
6979 | _("Process record does not support " | |
6980 | "instruction sysenter.\n")); | |
7ad10968 HZ |
6981 | ir.addr -= 2; |
6982 | goto no_support; | |
6983 | } | |
a3c4230a | 6984 | ret = tdep->i386_sysenter_record (ir.regcache); |
7ad10968 HZ |
6985 | if (ret) |
6986 | return ret; | |
6987 | } | |
6988 | break; | |
6989 | ||
a38bba38 | 6990 | case 0x0f35: /* sysexit */ |
6cb06a8c TT |
6991 | gdb_printf (gdb_stderr, |
6992 | _("Process record does not support " | |
6993 | "instruction sysexit.\n")); | |
7ad10968 HZ |
6994 | ir.addr -= 2; |
6995 | goto no_support; | |
6996 | break; | |
6997 | ||
a38bba38 | 6998 | case 0x0f05: /* syscall */ |
cf648174 HZ |
6999 | { |
7000 | int ret; | |
a3c4230a | 7001 | if (tdep->i386_syscall_record == NULL) |
cf648174 | 7002 | { |
6cb06a8c TT |
7003 | gdb_printf (gdb_stderr, |
7004 | _("Process record does not support " | |
7005 | "instruction syscall.\n")); | |
cf648174 HZ |
7006 | ir.addr -= 2; |
7007 | goto no_support; | |
7008 | } | |
a3c4230a | 7009 | ret = tdep->i386_syscall_record (ir.regcache); |
cf648174 HZ |
7010 | if (ret) |
7011 | return ret; | |
7012 | } | |
7013 | break; | |
7014 | ||
a38bba38 | 7015 | case 0x0f07: /* sysret */ |
6cb06a8c TT |
7016 | gdb_printf (gdb_stderr, |
7017 | _("Process record does not support " | |
7018 | "instruction sysret.\n")); | |
cf648174 HZ |
7019 | ir.addr -= 2; |
7020 | goto no_support; | |
7021 | break; | |
7022 | ||
a38bba38 | 7023 | case 0x0fa2: /* cpuid */ |
25ea693b MM |
7024 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7025 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7026 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7027 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7ad10968 HZ |
7028 | break; |
7029 | ||
a38bba38 | 7030 | case 0xf4: /* hlt */ |
6cb06a8c TT |
7031 | gdb_printf (gdb_stderr, |
7032 | _("Process record does not support " | |
7033 | "instruction hlt.\n")); | |
7ad10968 HZ |
7034 | ir.addr -= 1; |
7035 | goto no_support; | |
7036 | break; | |
7037 | ||
7038 | case 0x0f00: | |
7039 | if (i386_record_modrm (&ir)) | |
7040 | return -1; | |
7041 | switch (ir.reg) | |
7042 | { | |
a38bba38 MS |
7043 | case 0: /* sldt */ |
7044 | case 1: /* str */ | |
7ad10968 | 7045 | if (ir.mod == 3) |
dda83cd7 | 7046 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7047 | else |
7048 | { | |
7049 | ir.ot = OT_WORD; | |
7050 | if (i386_record_lea_modrm (&ir)) | |
7051 | return -1; | |
7052 | } | |
7053 | break; | |
a38bba38 MS |
7054 | case 2: /* lldt */ |
7055 | case 3: /* ltr */ | |
7ad10968 | 7056 | break; |
a38bba38 MS |
7057 | case 4: /* verr */ |
7058 | case 5: /* verw */ | |
dda83cd7 | 7059 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7060 | break; |
7061 | default: | |
7062 | ir.addr -= 3; | |
7063 | opcode = opcode << 8 | ir.modrm; | |
7064 | goto no_support; | |
7065 | break; | |
7066 | } | |
7067 | break; | |
7068 | ||
7069 | case 0x0f01: | |
7070 | if (i386_record_modrm (&ir)) | |
7071 | return -1; | |
7072 | switch (ir.reg) | |
7073 | { | |
a38bba38 | 7074 | case 0: /* sgdt */ |
7ad10968 | 7075 | { |
955db0c0 | 7076 | uint64_t addr64; |
7ad10968 HZ |
7077 | |
7078 | if (ir.mod == 3) | |
7079 | { | |
7080 | ir.addr -= 3; | |
7081 | opcode = opcode << 8 | ir.modrm; | |
7082 | goto no_support; | |
7083 | } | |
d7877f7e | 7084 | if (ir.override >= 0) |
7ad10968 | 7085 | { |
dda83cd7 SM |
7086 | if (record_full_memory_query) |
7087 | { | |
7088 | if (yquery (_("\ | |
bb08c432 HZ |
7089 | Process record ignores the memory change of instruction at address %s\n\ |
7090 | because it can't get the value of the segment register.\n\ | |
7091 | Do you want to stop the program?"), | |
dda83cd7 | 7092 | paddress (gdbarch, ir.orig_addr))) |
651ce16a | 7093 | return -1; |
dda83cd7 | 7094 | } |
7ad10968 HZ |
7095 | } |
7096 | else | |
7097 | { | |
955db0c0 | 7098 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7099 | return -1; |
25ea693b | 7100 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7101 | return -1; |
955db0c0 | 7102 | addr64 += 2; |
dda83cd7 SM |
7103 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7104 | { | |
7105 | if (record_full_arch_list_add_mem (addr64, 8)) | |
cf648174 | 7106 | return -1; |
dda83cd7 SM |
7107 | } |
7108 | else | |
7109 | { | |
7110 | if (record_full_arch_list_add_mem (addr64, 4)) | |
cf648174 | 7111 | return -1; |
dda83cd7 | 7112 | } |
7ad10968 HZ |
7113 | } |
7114 | } | |
7115 | break; | |
7116 | case 1: | |
7117 | if (ir.mod == 3) | |
7118 | { | |
7119 | switch (ir.rm) | |
7120 | { | |
a38bba38 | 7121 | case 0: /* monitor */ |
7ad10968 | 7122 | break; |
a38bba38 | 7123 | case 1: /* mwait */ |
25ea693b | 7124 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7125 | break; |
7126 | default: | |
7127 | ir.addr -= 3; | |
7128 | opcode = opcode << 8 | ir.modrm; | |
7129 | goto no_support; | |
7130 | break; | |
7131 | } | |
7132 | } | |
7133 | else | |
7134 | { | |
7135 | /* sidt */ | |
d7877f7e | 7136 | if (ir.override >= 0) |
7ad10968 | 7137 | { |
dda83cd7 SM |
7138 | if (record_full_memory_query) |
7139 | { | |
7140 | if (yquery (_("\ | |
bb08c432 HZ |
7141 | Process record ignores the memory change of instruction at address %s\n\ |
7142 | because it can't get the value of the segment register.\n\ | |
7143 | Do you want to stop the program?"), | |
dda83cd7 SM |
7144 | paddress (gdbarch, ir.orig_addr))) |
7145 | return -1; | |
7146 | } | |
7ad10968 HZ |
7147 | } |
7148 | else | |
7149 | { | |
955db0c0 | 7150 | uint64_t addr64; |
7ad10968 | 7151 | |
955db0c0 | 7152 | if (i386_record_lea_modrm_addr (&ir, &addr64)) |
7ad10968 | 7153 | return -1; |
25ea693b | 7154 | if (record_full_arch_list_add_mem (addr64, 2)) |
7ad10968 | 7155 | return -1; |
955db0c0 | 7156 | addr64 += 2; |
dda83cd7 SM |
7157 | if (ir.regmap[X86_RECORD_R8_REGNUM]) |
7158 | { | |
7159 | if (record_full_arch_list_add_mem (addr64, 8)) | |
7160 | return -1; | |
7161 | } | |
7162 | else | |
7163 | { | |
7164 | if (record_full_arch_list_add_mem (addr64, 4)) | |
7165 | return -1; | |
7166 | } | |
7ad10968 HZ |
7167 | } |
7168 | } | |
7169 | break; | |
a38bba38 | 7170 | case 2: /* lgdt */ |
3800e645 MS |
7171 | if (ir.mod == 3) |
7172 | { | |
7173 | /* xgetbv */ | |
7174 | if (ir.rm == 0) | |
7175 | { | |
25ea693b MM |
7176 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); |
7177 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
3800e645 MS |
7178 | break; |
7179 | } | |
7180 | /* xsetbv */ | |
7181 | else if (ir.rm == 1) | |
7182 | break; | |
7183 | } | |
da0e1563 | 7184 | /* Fall through. */ |
a38bba38 | 7185 | case 3: /* lidt */ |
7ad10968 HZ |
7186 | if (ir.mod == 3) |
7187 | { | |
7188 | ir.addr -= 3; | |
7189 | opcode = opcode << 8 | ir.modrm; | |
7190 | goto no_support; | |
7191 | } | |
7192 | break; | |
a38bba38 | 7193 | case 4: /* smsw */ |
7ad10968 HZ |
7194 | if (ir.mod == 3) |
7195 | { | |
25ea693b | 7196 | if (record_full_arch_list_add_reg (ir.regcache, ir.rm | ir.rex_b)) |
7ad10968 HZ |
7197 | return -1; |
7198 | } | |
7199 | else | |
7200 | { | |
7201 | ir.ot = OT_WORD; | |
7202 | if (i386_record_lea_modrm (&ir)) | |
7203 | return -1; | |
7204 | } | |
25ea693b | 7205 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7206 | break; |
a38bba38 | 7207 | case 6: /* lmsw */ |
25ea693b | 7208 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 | 7209 | break; |
a38bba38 | 7210 | case 7: /* invlpg */ |
cf648174 HZ |
7211 | if (ir.mod == 3) |
7212 | { | |
7213 | if (ir.rm == 0 && ir.regmap[X86_RECORD_R8_REGNUM]) | |
dda83cd7 | 7214 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM); |
cf648174 | 7215 | else |
dda83cd7 SM |
7216 | { |
7217 | ir.addr -= 3; | |
7218 | opcode = opcode << 8 | ir.modrm; | |
7219 | goto no_support; | |
7220 | } | |
cf648174 HZ |
7221 | } |
7222 | else | |
25ea693b | 7223 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
cf648174 HZ |
7224 | break; |
7225 | default: | |
7226 | ir.addr -= 3; | |
7227 | opcode = opcode << 8 | ir.modrm; | |
7228 | goto no_support; | |
7ad10968 HZ |
7229 | break; |
7230 | } | |
7231 | break; | |
7232 | ||
a38bba38 MS |
7233 | case 0x0f08: /* invd */ |
7234 | case 0x0f09: /* wbinvd */ | |
7ad10968 HZ |
7235 | break; |
7236 | ||
a38bba38 | 7237 | case 0x63: /* arpl */ |
7ad10968 HZ |
7238 | if (i386_record_modrm (&ir)) |
7239 | return -1; | |
cf648174 | 7240 | if (ir.mod == 3 || ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 SM |
7241 | { |
7242 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.regmap[X86_RECORD_R8_REGNUM] | |
25ea693b | 7243 | ? (ir.reg | rex_r) : ir.rm); |
dda83cd7 | 7244 | } |
7ad10968 | 7245 | else |
dda83cd7 SM |
7246 | { |
7247 | ir.ot = ir.dflag ? OT_LONG : OT_WORD; | |
7248 | if (i386_record_lea_modrm (&ir)) | |
7249 | return -1; | |
7250 | } | |
cf648174 | 7251 | if (!ir.regmap[X86_RECORD_R8_REGNUM]) |
dda83cd7 | 7252 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7253 | break; |
7254 | ||
a38bba38 MS |
7255 | case 0x0f02: /* lar */ |
7256 | case 0x0f03: /* lsl */ | |
7ad10968 HZ |
7257 | if (i386_record_modrm (&ir)) |
7258 | return -1; | |
25ea693b MM |
7259 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); |
7260 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7ad10968 HZ |
7261 | break; |
7262 | ||
7263 | case 0x0f18: | |
cf648174 HZ |
7264 | if (i386_record_modrm (&ir)) |
7265 | return -1; | |
7266 | if (ir.mod == 3 && ir.reg == 3) | |
dda83cd7 | 7267 | { |
cf648174 HZ |
7268 | ir.addr -= 3; |
7269 | opcode = opcode << 8 | ir.modrm; | |
7270 | goto no_support; | |
7271 | } | |
7ad10968 HZ |
7272 | break; |
7273 | ||
7ad10968 HZ |
7274 | case 0x0f19: |
7275 | case 0x0f1a: | |
7276 | case 0x0f1b: | |
7277 | case 0x0f1c: | |
7278 | case 0x0f1d: | |
7279 | case 0x0f1e: | |
7280 | case 0x0f1f: | |
a38bba38 | 7281 | /* nop (multi byte) */ |
7ad10968 HZ |
7282 | break; |
7283 | ||
a38bba38 MS |
7284 | case 0x0f20: /* mov reg, crN */ |
7285 | case 0x0f22: /* mov crN, reg */ | |
7ad10968 HZ |
7286 | if (i386_record_modrm (&ir)) |
7287 | return -1; | |
7288 | if ((ir.modrm & 0xc0) != 0xc0) | |
7289 | { | |
cf648174 | 7290 | ir.addr -= 3; |
7ad10968 HZ |
7291 | opcode = opcode << 8 | ir.modrm; |
7292 | goto no_support; | |
7293 | } | |
7294 | switch (ir.reg) | |
7295 | { | |
7296 | case 0: | |
7297 | case 2: | |
7298 | case 3: | |
7299 | case 4: | |
7300 | case 8: | |
7301 | if (opcode & 2) | |
25ea693b | 7302 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7303 | else |
dda83cd7 | 7304 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7305 | break; |
7306 | default: | |
cf648174 | 7307 | ir.addr -= 3; |
7ad10968 HZ |
7308 | opcode = opcode << 8 | ir.modrm; |
7309 | goto no_support; | |
7310 | break; | |
7311 | } | |
7312 | break; | |
7313 | ||
a38bba38 MS |
7314 | case 0x0f21: /* mov reg, drN */ |
7315 | case 0x0f23: /* mov drN, reg */ | |
7ad10968 HZ |
7316 | if (i386_record_modrm (&ir)) |
7317 | return -1; | |
7318 | if ((ir.modrm & 0xc0) != 0xc0 || ir.reg == 4 | |
7319 | || ir.reg == 5 || ir.reg >= 8) | |
7320 | { | |
cf648174 | 7321 | ir.addr -= 3; |
7ad10968 HZ |
7322 | opcode = opcode << 8 | ir.modrm; |
7323 | goto no_support; | |
7324 | } | |
7325 | if (opcode & 2) | |
dda83cd7 | 7326 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 | 7327 | else |
25ea693b | 7328 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); |
7ad10968 HZ |
7329 | break; |
7330 | ||
a38bba38 | 7331 | case 0x0f06: /* clts */ |
25ea693b | 7332 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7ad10968 HZ |
7333 | break; |
7334 | ||
a3c4230a HZ |
7335 | /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */ |
7336 | ||
7337 | case 0x0f0d: /* 3DNow! prefetch */ | |
7338 | break; | |
7339 | ||
7340 | case 0x0f0e: /* 3DNow! femms */ | |
7341 | case 0x0f77: /* emms */ | |
7342 | if (i386_fpc_regnum_p (gdbarch, I387_FTAG_REGNUM(tdep))) | |
dda83cd7 | 7343 | goto no_support; |
25ea693b | 7344 | record_full_arch_list_add_reg (ir.regcache, I387_FTAG_REGNUM(tdep)); |
a3c4230a HZ |
7345 | break; |
7346 | ||
7347 | case 0x0f0f: /* 3DNow! data */ | |
7348 | if (i386_record_modrm (&ir)) | |
7349 | return -1; | |
4ffa4fc7 PA |
7350 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) |
7351 | return -1; | |
a3c4230a HZ |
7352 | ir.addr++; |
7353 | switch (opcode8) | |
dda83cd7 SM |
7354 | { |
7355 | case 0x0c: /* 3DNow! pi2fw */ | |
7356 | case 0x0d: /* 3DNow! pi2fd */ | |
7357 | case 0x1c: /* 3DNow! pf2iw */ | |
7358 | case 0x1d: /* 3DNow! pf2id */ | |
7359 | case 0x8a: /* 3DNow! pfnacc */ | |
7360 | case 0x8e: /* 3DNow! pfpnacc */ | |
7361 | case 0x90: /* 3DNow! pfcmpge */ | |
7362 | case 0x94: /* 3DNow! pfmin */ | |
7363 | case 0x96: /* 3DNow! pfrcp */ | |
7364 | case 0x97: /* 3DNow! pfrsqrt */ | |
7365 | case 0x9a: /* 3DNow! pfsub */ | |
7366 | case 0x9e: /* 3DNow! pfadd */ | |
7367 | case 0xa0: /* 3DNow! pfcmpgt */ | |
7368 | case 0xa4: /* 3DNow! pfmax */ | |
7369 | case 0xa6: /* 3DNow! pfrcpit1 */ | |
7370 | case 0xa7: /* 3DNow! pfrsqit1 */ | |
7371 | case 0xaa: /* 3DNow! pfsubr */ | |
7372 | case 0xae: /* 3DNow! pfacc */ | |
7373 | case 0xb0: /* 3DNow! pfcmpeq */ | |
7374 | case 0xb4: /* 3DNow! pfmul */ | |
7375 | case 0xb6: /* 3DNow! pfrcpit2 */ | |
7376 | case 0xb7: /* 3DNow! pmulhrw */ | |
7377 | case 0xbb: /* 3DNow! pswapd */ | |
7378 | case 0xbf: /* 3DNow! pavgusb */ | |
7379 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
7380 | goto no_support_3dnow_data; | |
7381 | record_full_arch_list_add_reg (ir.regcache, ir.reg); | |
7382 | break; | |
7383 | ||
7384 | default: | |
a3c4230a | 7385 | no_support_3dnow_data: |
dda83cd7 SM |
7386 | opcode = (opcode << 8) | opcode8; |
7387 | goto no_support; | |
7388 | break; | |
7389 | } | |
a3c4230a HZ |
7390 | break; |
7391 | ||
7392 | case 0x0faa: /* rsm */ | |
25ea693b MM |
7393 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
7394 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM); | |
7395 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM); | |
7396 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM); | |
7397 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM); | |
7398 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM); | |
7399 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM); | |
7400 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM); | |
7401 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM); | |
a3c4230a HZ |
7402 | break; |
7403 | ||
7404 | case 0x0fae: | |
7405 | if (i386_record_modrm (&ir)) | |
7406 | return -1; | |
7407 | switch(ir.reg) | |
dda83cd7 SM |
7408 | { |
7409 | case 0: /* fxsave */ | |
7410 | { | |
7411 | uint64_t tmpu64; | |
a3c4230a | 7412 | |
dda83cd7 | 7413 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a HZ |
7414 | if (i386_record_lea_modrm_addr (&ir, &tmpu64)) |
7415 | return -1; | |
dda83cd7 SM |
7416 | if (record_full_arch_list_add_mem (tmpu64, 512)) |
7417 | return -1; | |
7418 | } | |
7419 | break; | |
a3c4230a | 7420 | |
dda83cd7 SM |
7421 | case 1: /* fxrstor */ |
7422 | { | |
7423 | int i; | |
a3c4230a | 7424 | |
dda83cd7 | 7425 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); |
a3c4230a | 7426 | |
dda83cd7 SM |
7427 | for (i = I387_MM0_REGNUM (tdep); |
7428 | i386_mmx_regnum_p (gdbarch, i); i++) | |
7429 | record_full_arch_list_add_reg (ir.regcache, i); | |
a3c4230a | 7430 | |
dda83cd7 SM |
7431 | for (i = I387_XMM0_REGNUM (tdep); |
7432 | i386_xmm_regnum_p (gdbarch, i); i++) | |
7433 | record_full_arch_list_add_reg (ir.regcache, i); | |
a3c4230a | 7434 | |
dda83cd7 SM |
7435 | if (i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) |
7436 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7437 | I387_MXCSR_REGNUM(tdep)); |
a3c4230a | 7438 | |
dda83cd7 SM |
7439 | for (i = I387_ST0_REGNUM (tdep); |
7440 | i386_fp_regnum_p (gdbarch, i); i++) | |
7441 | record_full_arch_list_add_reg (ir.regcache, i); | |
7442 | ||
7443 | for (i = I387_FCTRL_REGNUM (tdep); | |
7444 | i386_fpc_regnum_p (gdbarch, i); i++) | |
7445 | record_full_arch_list_add_reg (ir.regcache, i); | |
7446 | } | |
7447 | break; | |
7448 | ||
7449 | case 2: /* ldmxcsr */ | |
7450 | if (!i386_mxcsr_regnum_p (gdbarch, I387_MXCSR_REGNUM(tdep))) | |
7451 | goto no_support; | |
7452 | record_full_arch_list_add_reg (ir.regcache, I387_MXCSR_REGNUM(tdep)); | |
7453 | break; | |
7454 | ||
7455 | case 3: /* stmxcsr */ | |
7456 | ir.ot = OT_LONG; | |
7457 | if (i386_record_lea_modrm (&ir)) | |
7458 | return -1; | |
7459 | break; | |
7460 | ||
7461 | case 5: /* lfence */ | |
7462 | case 6: /* mfence */ | |
7463 | case 7: /* sfence clflush */ | |
7464 | break; | |
7465 | ||
7466 | default: | |
7467 | opcode = (opcode << 8) | ir.modrm; | |
7468 | goto no_support; | |
7469 | break; | |
7470 | } | |
a3c4230a HZ |
7471 | break; |
7472 | ||
7473 | case 0x0fc3: /* movnti */ | |
7474 | ir.ot = (ir.dflag == 2) ? OT_QUAD : OT_LONG; | |
7475 | if (i386_record_modrm (&ir)) | |
7476 | return -1; | |
7477 | if (ir.mod == 3) | |
dda83cd7 | 7478 | goto no_support; |
a3c4230a HZ |
7479 | ir.reg |= rex_r; |
7480 | if (i386_record_lea_modrm (&ir)) | |
dda83cd7 | 7481 | return -1; |
a3c4230a HZ |
7482 | break; |
7483 | ||
7484 | /* Add prefix to opcode. */ | |
7485 | case 0x0f10: | |
7486 | case 0x0f11: | |
7487 | case 0x0f12: | |
7488 | case 0x0f13: | |
7489 | case 0x0f14: | |
7490 | case 0x0f15: | |
7491 | case 0x0f16: | |
7492 | case 0x0f17: | |
7493 | case 0x0f28: | |
7494 | case 0x0f29: | |
7495 | case 0x0f2a: | |
7496 | case 0x0f2b: | |
7497 | case 0x0f2c: | |
7498 | case 0x0f2d: | |
7499 | case 0x0f2e: | |
7500 | case 0x0f2f: | |
7501 | case 0x0f38: | |
7502 | case 0x0f39: | |
7503 | case 0x0f3a: | |
7504 | case 0x0f50: | |
7505 | case 0x0f51: | |
7506 | case 0x0f52: | |
7507 | case 0x0f53: | |
7508 | case 0x0f54: | |
7509 | case 0x0f55: | |
7510 | case 0x0f56: | |
7511 | case 0x0f57: | |
7512 | case 0x0f58: | |
7513 | case 0x0f59: | |
7514 | case 0x0f5a: | |
7515 | case 0x0f5b: | |
7516 | case 0x0f5c: | |
7517 | case 0x0f5d: | |
7518 | case 0x0f5e: | |
7519 | case 0x0f5f: | |
7520 | case 0x0f60: | |
7521 | case 0x0f61: | |
7522 | case 0x0f62: | |
7523 | case 0x0f63: | |
7524 | case 0x0f64: | |
7525 | case 0x0f65: | |
7526 | case 0x0f66: | |
7527 | case 0x0f67: | |
7528 | case 0x0f68: | |
7529 | case 0x0f69: | |
7530 | case 0x0f6a: | |
7531 | case 0x0f6b: | |
7532 | case 0x0f6c: | |
7533 | case 0x0f6d: | |
7534 | case 0x0f6e: | |
7535 | case 0x0f6f: | |
7536 | case 0x0f70: | |
7537 | case 0x0f71: | |
7538 | case 0x0f72: | |
7539 | case 0x0f73: | |
7540 | case 0x0f74: | |
7541 | case 0x0f75: | |
7542 | case 0x0f76: | |
7543 | case 0x0f7c: | |
7544 | case 0x0f7d: | |
7545 | case 0x0f7e: | |
7546 | case 0x0f7f: | |
7547 | case 0x0fb8: | |
7548 | case 0x0fc2: | |
7549 | case 0x0fc4: | |
7550 | case 0x0fc5: | |
7551 | case 0x0fc6: | |
7552 | case 0x0fd0: | |
7553 | case 0x0fd1: | |
7554 | case 0x0fd2: | |
7555 | case 0x0fd3: | |
7556 | case 0x0fd4: | |
7557 | case 0x0fd5: | |
7558 | case 0x0fd6: | |
7559 | case 0x0fd7: | |
7560 | case 0x0fd8: | |
7561 | case 0x0fd9: | |
7562 | case 0x0fda: | |
7563 | case 0x0fdb: | |
7564 | case 0x0fdc: | |
7565 | case 0x0fdd: | |
7566 | case 0x0fde: | |
7567 | case 0x0fdf: | |
7568 | case 0x0fe0: | |
7569 | case 0x0fe1: | |
7570 | case 0x0fe2: | |
7571 | case 0x0fe3: | |
7572 | case 0x0fe4: | |
7573 | case 0x0fe5: | |
7574 | case 0x0fe6: | |
7575 | case 0x0fe7: | |
7576 | case 0x0fe8: | |
7577 | case 0x0fe9: | |
7578 | case 0x0fea: | |
7579 | case 0x0feb: | |
7580 | case 0x0fec: | |
7581 | case 0x0fed: | |
7582 | case 0x0fee: | |
7583 | case 0x0fef: | |
7584 | case 0x0ff0: | |
7585 | case 0x0ff1: | |
7586 | case 0x0ff2: | |
7587 | case 0x0ff3: | |
7588 | case 0x0ff4: | |
7589 | case 0x0ff5: | |
7590 | case 0x0ff6: | |
7591 | case 0x0ff7: | |
7592 | case 0x0ff8: | |
7593 | case 0x0ff9: | |
7594 | case 0x0ffa: | |
7595 | case 0x0ffb: | |
7596 | case 0x0ffc: | |
7597 | case 0x0ffd: | |
7598 | case 0x0ffe: | |
f9fda3f5 L |
7599 | /* Mask out PREFIX_ADDR. */ |
7600 | switch ((prefixes & ~PREFIX_ADDR)) | |
dda83cd7 SM |
7601 | { |
7602 | case PREFIX_REPNZ: | |
7603 | opcode |= 0xf20000; | |
7604 | break; | |
7605 | case PREFIX_DATA: | |
7606 | opcode |= 0x660000; | |
7607 | break; | |
7608 | case PREFIX_REPZ: | |
7609 | opcode |= 0xf30000; | |
7610 | break; | |
7611 | } | |
a3c4230a HZ |
7612 | reswitch_prefix_add: |
7613 | switch (opcode) | |
dda83cd7 SM |
7614 | { |
7615 | case 0x0f38: | |
7616 | case 0x660f38: | |
7617 | case 0xf20f38: | |
7618 | case 0x0f3a: | |
7619 | case 0x660f3a: | |
7620 | if (record_read_memory (gdbarch, ir.addr, &opcode8, 1)) | |
4ffa4fc7 | 7621 | return -1; |
dda83cd7 SM |
7622 | ir.addr++; |
7623 | opcode = (uint32_t) opcode8 | opcode << 8; | |
7624 | goto reswitch_prefix_add; | |
7625 | break; | |
7626 | ||
7627 | case 0x0f10: /* movups */ | |
7628 | case 0x660f10: /* movupd */ | |
7629 | case 0xf30f10: /* movss */ | |
7630 | case 0xf20f10: /* movsd */ | |
7631 | case 0x0f12: /* movlps */ | |
7632 | case 0x660f12: /* movlpd */ | |
7633 | case 0xf30f12: /* movsldup */ | |
7634 | case 0xf20f12: /* movddup */ | |
7635 | case 0x0f14: /* unpcklps */ | |
7636 | case 0x660f14: /* unpcklpd */ | |
7637 | case 0x0f15: /* unpckhps */ | |
7638 | case 0x660f15: /* unpckhpd */ | |
7639 | case 0x0f16: /* movhps */ | |
7640 | case 0x660f16: /* movhpd */ | |
7641 | case 0xf30f16: /* movshdup */ | |
7642 | case 0x0f28: /* movaps */ | |
7643 | case 0x660f28: /* movapd */ | |
7644 | case 0x0f2a: /* cvtpi2ps */ | |
7645 | case 0x660f2a: /* cvtpi2pd */ | |
7646 | case 0xf30f2a: /* cvtsi2ss */ | |
7647 | case 0xf20f2a: /* cvtsi2sd */ | |
7648 | case 0x0f2c: /* cvttps2pi */ | |
7649 | case 0x660f2c: /* cvttpd2pi */ | |
7650 | case 0x0f2d: /* cvtps2pi */ | |
7651 | case 0x660f2d: /* cvtpd2pi */ | |
7652 | case 0x660f3800: /* pshufb */ | |
7653 | case 0x660f3801: /* phaddw */ | |
7654 | case 0x660f3802: /* phaddd */ | |
7655 | case 0x660f3803: /* phaddsw */ | |
7656 | case 0x660f3804: /* pmaddubsw */ | |
7657 | case 0x660f3805: /* phsubw */ | |
7658 | case 0x660f3806: /* phsubd */ | |
7659 | case 0x660f3807: /* phsubsw */ | |
7660 | case 0x660f3808: /* psignb */ | |
7661 | case 0x660f3809: /* psignw */ | |
7662 | case 0x660f380a: /* psignd */ | |
7663 | case 0x660f380b: /* pmulhrsw */ | |
7664 | case 0x660f3810: /* pblendvb */ | |
7665 | case 0x660f3814: /* blendvps */ | |
7666 | case 0x660f3815: /* blendvpd */ | |
7667 | case 0x660f381c: /* pabsb */ | |
7668 | case 0x660f381d: /* pabsw */ | |
7669 | case 0x660f381e: /* pabsd */ | |
7670 | case 0x660f3820: /* pmovsxbw */ | |
7671 | case 0x660f3821: /* pmovsxbd */ | |
7672 | case 0x660f3822: /* pmovsxbq */ | |
7673 | case 0x660f3823: /* pmovsxwd */ | |
7674 | case 0x660f3824: /* pmovsxwq */ | |
7675 | case 0x660f3825: /* pmovsxdq */ | |
7676 | case 0x660f3828: /* pmuldq */ | |
7677 | case 0x660f3829: /* pcmpeqq */ | |
7678 | case 0x660f382a: /* movntdqa */ | |
7679 | case 0x660f3a08: /* roundps */ | |
7680 | case 0x660f3a09: /* roundpd */ | |
7681 | case 0x660f3a0a: /* roundss */ | |
7682 | case 0x660f3a0b: /* roundsd */ | |
7683 | case 0x660f3a0c: /* blendps */ | |
7684 | case 0x660f3a0d: /* blendpd */ | |
7685 | case 0x660f3a0e: /* pblendw */ | |
7686 | case 0x660f3a0f: /* palignr */ | |
7687 | case 0x660f3a20: /* pinsrb */ | |
7688 | case 0x660f3a21: /* insertps */ | |
7689 | case 0x660f3a22: /* pinsrd pinsrq */ | |
7690 | case 0x660f3a40: /* dpps */ | |
7691 | case 0x660f3a41: /* dppd */ | |
7692 | case 0x660f3a42: /* mpsadbw */ | |
7693 | case 0x660f3a60: /* pcmpestrm */ | |
7694 | case 0x660f3a61: /* pcmpestri */ | |
7695 | case 0x660f3a62: /* pcmpistrm */ | |
7696 | case 0x660f3a63: /* pcmpistri */ | |
7697 | case 0x0f51: /* sqrtps */ | |
7698 | case 0x660f51: /* sqrtpd */ | |
7699 | case 0xf20f51: /* sqrtsd */ | |
7700 | case 0xf30f51: /* sqrtss */ | |
7701 | case 0x0f52: /* rsqrtps */ | |
7702 | case 0xf30f52: /* rsqrtss */ | |
7703 | case 0x0f53: /* rcpps */ | |
7704 | case 0xf30f53: /* rcpss */ | |
7705 | case 0x0f54: /* andps */ | |
7706 | case 0x660f54: /* andpd */ | |
7707 | case 0x0f55: /* andnps */ | |
7708 | case 0x660f55: /* andnpd */ | |
7709 | case 0x0f56: /* orps */ | |
7710 | case 0x660f56: /* orpd */ | |
7711 | case 0x0f57: /* xorps */ | |
7712 | case 0x660f57: /* xorpd */ | |
7713 | case 0x0f58: /* addps */ | |
7714 | case 0x660f58: /* addpd */ | |
7715 | case 0xf20f58: /* addsd */ | |
7716 | case 0xf30f58: /* addss */ | |
7717 | case 0x0f59: /* mulps */ | |
7718 | case 0x660f59: /* mulpd */ | |
7719 | case 0xf20f59: /* mulsd */ | |
7720 | case 0xf30f59: /* mulss */ | |
7721 | case 0x0f5a: /* cvtps2pd */ | |
7722 | case 0x660f5a: /* cvtpd2ps */ | |
7723 | case 0xf20f5a: /* cvtsd2ss */ | |
7724 | case 0xf30f5a: /* cvtss2sd */ | |
7725 | case 0x0f5b: /* cvtdq2ps */ | |
7726 | case 0x660f5b: /* cvtps2dq */ | |
7727 | case 0xf30f5b: /* cvttps2dq */ | |
7728 | case 0x0f5c: /* subps */ | |
7729 | case 0x660f5c: /* subpd */ | |
7730 | case 0xf20f5c: /* subsd */ | |
7731 | case 0xf30f5c: /* subss */ | |
7732 | case 0x0f5d: /* minps */ | |
7733 | case 0x660f5d: /* minpd */ | |
7734 | case 0xf20f5d: /* minsd */ | |
7735 | case 0xf30f5d: /* minss */ | |
7736 | case 0x0f5e: /* divps */ | |
7737 | case 0x660f5e: /* divpd */ | |
7738 | case 0xf20f5e: /* divsd */ | |
7739 | case 0xf30f5e: /* divss */ | |
7740 | case 0x0f5f: /* maxps */ | |
7741 | case 0x660f5f: /* maxpd */ | |
7742 | case 0xf20f5f: /* maxsd */ | |
7743 | case 0xf30f5f: /* maxss */ | |
7744 | case 0x660f60: /* punpcklbw */ | |
7745 | case 0x660f61: /* punpcklwd */ | |
7746 | case 0x660f62: /* punpckldq */ | |
7747 | case 0x660f63: /* packsswb */ | |
7748 | case 0x660f64: /* pcmpgtb */ | |
7749 | case 0x660f65: /* pcmpgtw */ | |
7750 | case 0x660f66: /* pcmpgtd */ | |
7751 | case 0x660f67: /* packuswb */ | |
7752 | case 0x660f68: /* punpckhbw */ | |
7753 | case 0x660f69: /* punpckhwd */ | |
7754 | case 0x660f6a: /* punpckhdq */ | |
7755 | case 0x660f6b: /* packssdw */ | |
7756 | case 0x660f6c: /* punpcklqdq */ | |
7757 | case 0x660f6d: /* punpckhqdq */ | |
7758 | case 0x660f6e: /* movd */ | |
7759 | case 0x660f6f: /* movdqa */ | |
7760 | case 0xf30f6f: /* movdqu */ | |
7761 | case 0x660f70: /* pshufd */ | |
7762 | case 0xf20f70: /* pshuflw */ | |
7763 | case 0xf30f70: /* pshufhw */ | |
7764 | case 0x660f74: /* pcmpeqb */ | |
7765 | case 0x660f75: /* pcmpeqw */ | |
7766 | case 0x660f76: /* pcmpeqd */ | |
7767 | case 0x660f7c: /* haddpd */ | |
7768 | case 0xf20f7c: /* haddps */ | |
7769 | case 0x660f7d: /* hsubpd */ | |
7770 | case 0xf20f7d: /* hsubps */ | |
7771 | case 0xf30f7e: /* movq */ | |
7772 | case 0x0fc2: /* cmpps */ | |
7773 | case 0x660fc2: /* cmppd */ | |
7774 | case 0xf20fc2: /* cmpsd */ | |
7775 | case 0xf30fc2: /* cmpss */ | |
7776 | case 0x660fc4: /* pinsrw */ | |
7777 | case 0x0fc6: /* shufps */ | |
7778 | case 0x660fc6: /* shufpd */ | |
7779 | case 0x660fd0: /* addsubpd */ | |
7780 | case 0xf20fd0: /* addsubps */ | |
7781 | case 0x660fd1: /* psrlw */ | |
7782 | case 0x660fd2: /* psrld */ | |
7783 | case 0x660fd3: /* psrlq */ | |
7784 | case 0x660fd4: /* paddq */ | |
7785 | case 0x660fd5: /* pmullw */ | |
7786 | case 0xf30fd6: /* movq2dq */ | |
7787 | case 0x660fd8: /* psubusb */ | |
7788 | case 0x660fd9: /* psubusw */ | |
7789 | case 0x660fda: /* pminub */ | |
7790 | case 0x660fdb: /* pand */ | |
7791 | case 0x660fdc: /* paddusb */ | |
7792 | case 0x660fdd: /* paddusw */ | |
7793 | case 0x660fde: /* pmaxub */ | |
7794 | case 0x660fdf: /* pandn */ | |
7795 | case 0x660fe0: /* pavgb */ | |
7796 | case 0x660fe1: /* psraw */ | |
7797 | case 0x660fe2: /* psrad */ | |
7798 | case 0x660fe3: /* pavgw */ | |
7799 | case 0x660fe4: /* pmulhuw */ | |
7800 | case 0x660fe5: /* pmulhw */ | |
7801 | case 0x660fe6: /* cvttpd2dq */ | |
7802 | case 0xf20fe6: /* cvtpd2dq */ | |
7803 | case 0xf30fe6: /* cvtdq2pd */ | |
7804 | case 0x660fe8: /* psubsb */ | |
7805 | case 0x660fe9: /* psubsw */ | |
7806 | case 0x660fea: /* pminsw */ | |
7807 | case 0x660feb: /* por */ | |
7808 | case 0x660fec: /* paddsb */ | |
7809 | case 0x660fed: /* paddsw */ | |
7810 | case 0x660fee: /* pmaxsw */ | |
7811 | case 0x660fef: /* pxor */ | |
7812 | case 0xf20ff0: /* lddqu */ | |
7813 | case 0x660ff1: /* psllw */ | |
7814 | case 0x660ff2: /* pslld */ | |
7815 | case 0x660ff3: /* psllq */ | |
7816 | case 0x660ff4: /* pmuludq */ | |
7817 | case 0x660ff5: /* pmaddwd */ | |
7818 | case 0x660ff6: /* psadbw */ | |
7819 | case 0x660ff8: /* psubb */ | |
7820 | case 0x660ff9: /* psubw */ | |
7821 | case 0x660ffa: /* psubd */ | |
7822 | case 0x660ffb: /* psubq */ | |
7823 | case 0x660ffc: /* paddb */ | |
7824 | case 0x660ffd: /* paddw */ | |
7825 | case 0x660ffe: /* paddd */ | |
7826 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7827 | return -1; |
dda83cd7 SM |
7828 | ir.reg |= rex_r; |
7829 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.reg)) | |
7830 | goto no_support; | |
7831 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7832 | I387_XMM0_REGNUM (tdep) + ir.reg); |
dda83cd7 SM |
7833 | if ((opcode & 0xfffffffc) == 0x660f3a60) |
7834 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
7835 | break; | |
7836 | ||
7837 | case 0x0f11: /* movups */ | |
7838 | case 0x660f11: /* movupd */ | |
7839 | case 0xf30f11: /* movss */ | |
7840 | case 0xf20f11: /* movsd */ | |
7841 | case 0x0f13: /* movlps */ | |
7842 | case 0x660f13: /* movlpd */ | |
7843 | case 0x0f17: /* movhps */ | |
7844 | case 0x660f17: /* movhpd */ | |
7845 | case 0x0f29: /* movaps */ | |
7846 | case 0x660f29: /* movapd */ | |
7847 | case 0x660f3a14: /* pextrb */ | |
7848 | case 0x660f3a15: /* pextrw */ | |
7849 | case 0x660f3a16: /* pextrd pextrq */ | |
7850 | case 0x660f3a17: /* extractps */ | |
7851 | case 0x660f7f: /* movdqa */ | |
7852 | case 0xf30f7f: /* movdqu */ | |
7853 | if (i386_record_modrm (&ir)) | |
a3c4230a | 7854 | return -1; |
dda83cd7 SM |
7855 | if (ir.mod == 3) |
7856 | { | |
7857 | if (opcode == 0x0f13 || opcode == 0x660f13 | |
7858 | || opcode == 0x0f17 || opcode == 0x660f17) | |
7859 | goto no_support; | |
7860 | ir.rm |= ir.rex_b; | |
7861 | if (!i386_xmm_regnum_p (gdbarch, | |
1777feb0 | 7862 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
dda83cd7 SM |
7863 | goto no_support; |
7864 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 7865 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
7866 | } |
7867 | else | |
7868 | { | |
7869 | switch (opcode) | |
7870 | { | |
7871 | case 0x660f3a14: | |
7872 | ir.ot = OT_BYTE; | |
7873 | break; | |
7874 | case 0x660f3a15: | |
7875 | ir.ot = OT_WORD; | |
7876 | break; | |
7877 | case 0x660f3a16: | |
7878 | ir.ot = OT_LONG; | |
7879 | break; | |
7880 | case 0x660f3a17: | |
7881 | ir.ot = OT_QUAD; | |
7882 | break; | |
7883 | default: | |
7884 | ir.ot = OT_DQUAD; | |
7885 | break; | |
7886 | } | |
7887 | if (i386_record_lea_modrm (&ir)) | |
7888 | return -1; | |
7889 | } | |
7890 | break; | |
7891 | ||
7892 | case 0x0f2b: /* movntps */ | |
7893 | case 0x660f2b: /* movntpd */ | |
7894 | case 0x0fe7: /* movntq */ | |
7895 | case 0x660fe7: /* movntdq */ | |
7896 | if (ir.mod == 3) | |
7897 | goto no_support; | |
7898 | if (opcode == 0x0fe7) | |
7899 | ir.ot = OT_QUAD; | |
7900 | else | |
7901 | ir.ot = OT_DQUAD; | |
7902 | if (i386_record_lea_modrm (&ir)) | |
a3c4230a | 7903 | return -1; |
dda83cd7 SM |
7904 | break; |
7905 | ||
7906 | case 0xf30f2c: /* cvttss2si */ | |
7907 | case 0xf20f2c: /* cvttsd2si */ | |
7908 | case 0xf30f2d: /* cvtss2si */ | |
7909 | case 0xf20f2d: /* cvtsd2si */ | |
7910 | case 0xf20f38f0: /* crc32 */ | |
7911 | case 0xf20f38f1: /* crc32 */ | |
7912 | case 0x0f50: /* movmskps */ | |
7913 | case 0x660f50: /* movmskpd */ | |
7914 | case 0x0fc5: /* pextrw */ | |
7915 | case 0x660fc5: /* pextrw */ | |
7916 | case 0x0fd7: /* pmovmskb */ | |
7917 | case 0x660fd7: /* pmovmskb */ | |
7918 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg | rex_r); | |
7919 | break; | |
7920 | ||
7921 | case 0x0f3800: /* pshufb */ | |
7922 | case 0x0f3801: /* phaddw */ | |
7923 | case 0x0f3802: /* phaddd */ | |
7924 | case 0x0f3803: /* phaddsw */ | |
7925 | case 0x0f3804: /* pmaddubsw */ | |
7926 | case 0x0f3805: /* phsubw */ | |
7927 | case 0x0f3806: /* phsubd */ | |
7928 | case 0x0f3807: /* phsubsw */ | |
7929 | case 0x0f3808: /* psignb */ | |
7930 | case 0x0f3809: /* psignw */ | |
7931 | case 0x0f380a: /* psignd */ | |
7932 | case 0x0f380b: /* pmulhrsw */ | |
7933 | case 0x0f381c: /* pabsb */ | |
7934 | case 0x0f381d: /* pabsw */ | |
7935 | case 0x0f381e: /* pabsd */ | |
7936 | case 0x0f382b: /* packusdw */ | |
7937 | case 0x0f3830: /* pmovzxbw */ | |
7938 | case 0x0f3831: /* pmovzxbd */ | |
7939 | case 0x0f3832: /* pmovzxbq */ | |
7940 | case 0x0f3833: /* pmovzxwd */ | |
7941 | case 0x0f3834: /* pmovzxwq */ | |
7942 | case 0x0f3835: /* pmovzxdq */ | |
7943 | case 0x0f3837: /* pcmpgtq */ | |
7944 | case 0x0f3838: /* pminsb */ | |
7945 | case 0x0f3839: /* pminsd */ | |
7946 | case 0x0f383a: /* pminuw */ | |
7947 | case 0x0f383b: /* pminud */ | |
7948 | case 0x0f383c: /* pmaxsb */ | |
7949 | case 0x0f383d: /* pmaxsd */ | |
7950 | case 0x0f383e: /* pmaxuw */ | |
7951 | case 0x0f383f: /* pmaxud */ | |
7952 | case 0x0f3840: /* pmulld */ | |
7953 | case 0x0f3841: /* phminposuw */ | |
7954 | case 0x0f3a0f: /* palignr */ | |
7955 | case 0x0f60: /* punpcklbw */ | |
7956 | case 0x0f61: /* punpcklwd */ | |
7957 | case 0x0f62: /* punpckldq */ | |
7958 | case 0x0f63: /* packsswb */ | |
7959 | case 0x0f64: /* pcmpgtb */ | |
7960 | case 0x0f65: /* pcmpgtw */ | |
7961 | case 0x0f66: /* pcmpgtd */ | |
7962 | case 0x0f67: /* packuswb */ | |
7963 | case 0x0f68: /* punpckhbw */ | |
7964 | case 0x0f69: /* punpckhwd */ | |
7965 | case 0x0f6a: /* punpckhdq */ | |
7966 | case 0x0f6b: /* packssdw */ | |
7967 | case 0x0f6e: /* movd */ | |
7968 | case 0x0f6f: /* movq */ | |
7969 | case 0x0f70: /* pshufw */ | |
7970 | case 0x0f74: /* pcmpeqb */ | |
7971 | case 0x0f75: /* pcmpeqw */ | |
7972 | case 0x0f76: /* pcmpeqd */ | |
7973 | case 0x0fc4: /* pinsrw */ | |
7974 | case 0x0fd1: /* psrlw */ | |
7975 | case 0x0fd2: /* psrld */ | |
7976 | case 0x0fd3: /* psrlq */ | |
7977 | case 0x0fd4: /* paddq */ | |
7978 | case 0x0fd5: /* pmullw */ | |
7979 | case 0xf20fd6: /* movdq2q */ | |
7980 | case 0x0fd8: /* psubusb */ | |
7981 | case 0x0fd9: /* psubusw */ | |
7982 | case 0x0fda: /* pminub */ | |
7983 | case 0x0fdb: /* pand */ | |
7984 | case 0x0fdc: /* paddusb */ | |
7985 | case 0x0fdd: /* paddusw */ | |
7986 | case 0x0fde: /* pmaxub */ | |
7987 | case 0x0fdf: /* pandn */ | |
7988 | case 0x0fe0: /* pavgb */ | |
7989 | case 0x0fe1: /* psraw */ | |
7990 | case 0x0fe2: /* psrad */ | |
7991 | case 0x0fe3: /* pavgw */ | |
7992 | case 0x0fe4: /* pmulhuw */ | |
7993 | case 0x0fe5: /* pmulhw */ | |
7994 | case 0x0fe8: /* psubsb */ | |
7995 | case 0x0fe9: /* psubsw */ | |
7996 | case 0x0fea: /* pminsw */ | |
7997 | case 0x0feb: /* por */ | |
7998 | case 0x0fec: /* paddsb */ | |
7999 | case 0x0fed: /* paddsw */ | |
8000 | case 0x0fee: /* pmaxsw */ | |
8001 | case 0x0fef: /* pxor */ | |
8002 | case 0x0ff1: /* psllw */ | |
8003 | case 0x0ff2: /* pslld */ | |
8004 | case 0x0ff3: /* psllq */ | |
8005 | case 0x0ff4: /* pmuludq */ | |
8006 | case 0x0ff5: /* pmaddwd */ | |
8007 | case 0x0ff6: /* psadbw */ | |
8008 | case 0x0ff8: /* psubb */ | |
8009 | case 0x0ff9: /* psubw */ | |
8010 | case 0x0ffa: /* psubd */ | |
8011 | case 0x0ffb: /* psubq */ | |
8012 | case 0x0ffc: /* paddb */ | |
8013 | case 0x0ffd: /* paddw */ | |
8014 | case 0x0ffe: /* paddd */ | |
8015 | if (i386_record_modrm (&ir)) | |
8016 | return -1; | |
8017 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.reg)) | |
8018 | goto no_support; | |
8019 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8020 | I387_MM0_REGNUM (tdep) + ir.reg); |
dda83cd7 | 8021 | break; |
a3c4230a | 8022 | |
dda83cd7 SM |
8023 | case 0x0f71: /* psllw */ |
8024 | case 0x0f72: /* pslld */ | |
8025 | case 0x0f73: /* psllq */ | |
8026 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8027 | return -1; |
dda83cd7 SM |
8028 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) |
8029 | goto no_support; | |
8030 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8031 | I387_MM0_REGNUM (tdep) + ir.rm); |
dda83cd7 | 8032 | break; |
a3c4230a | 8033 | |
dda83cd7 SM |
8034 | case 0x660f71: /* psllw */ |
8035 | case 0x660f72: /* pslld */ | |
8036 | case 0x660f73: /* psllq */ | |
8037 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8038 | return -1; |
dda83cd7 SM |
8039 | ir.rm |= ir.rex_b; |
8040 | if (!i386_xmm_regnum_p (gdbarch, I387_XMM0_REGNUM (tdep) + ir.rm)) | |
8041 | goto no_support; | |
8042 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8043 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 | 8044 | break; |
a3c4230a | 8045 | |
dda83cd7 SM |
8046 | case 0x0f7e: /* movd */ |
8047 | case 0x660f7e: /* movd */ | |
8048 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8049 | return -1; |
dda83cd7 SM |
8050 | if (ir.mod == 3) |
8051 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rm | ir.rex_b); | |
8052 | else | |
8053 | { | |
8054 | if (ir.dflag == 2) | |
8055 | ir.ot = OT_QUAD; | |
8056 | else | |
8057 | ir.ot = OT_LONG; | |
8058 | if (i386_record_lea_modrm (&ir)) | |
8059 | return -1; | |
8060 | } | |
8061 | break; | |
8062 | ||
8063 | case 0x0f7f: /* movq */ | |
8064 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8065 | return -1; |
dda83cd7 SM |
8066 | if (ir.mod == 3) |
8067 | { | |
8068 | if (!i386_mmx_regnum_p (gdbarch, I387_MM0_REGNUM (tdep) + ir.rm)) | |
8069 | goto no_support; | |
8070 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8071 | I387_MM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
8072 | } |
8073 | else | |
8074 | { | |
8075 | ir.ot = OT_QUAD; | |
8076 | if (i386_record_lea_modrm (&ir)) | |
8077 | return -1; | |
8078 | } | |
8079 | break; | |
8080 | ||
8081 | case 0xf30fb8: /* popcnt */ | |
8082 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8083 | return -1; |
dda83cd7 SM |
8084 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.reg); |
8085 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
8086 | break; | |
a3c4230a | 8087 | |
dda83cd7 SM |
8088 | case 0x660fd6: /* movq */ |
8089 | if (i386_record_modrm (&ir)) | |
a3c4230a | 8090 | return -1; |
dda83cd7 SM |
8091 | if (ir.mod == 3) |
8092 | { | |
8093 | ir.rm |= ir.rex_b; | |
8094 | if (!i386_xmm_regnum_p (gdbarch, | |
1777feb0 | 8095 | I387_XMM0_REGNUM (tdep) + ir.rm)) |
dda83cd7 SM |
8096 | goto no_support; |
8097 | record_full_arch_list_add_reg (ir.regcache, | |
25ea693b | 8098 | I387_XMM0_REGNUM (tdep) + ir.rm); |
dda83cd7 SM |
8099 | } |
8100 | else | |
8101 | { | |
8102 | ir.ot = OT_QUAD; | |
8103 | if (i386_record_lea_modrm (&ir)) | |
8104 | return -1; | |
8105 | } | |
8106 | break; | |
8107 | ||
8108 | case 0x660f3817: /* ptest */ | |
8109 | case 0x0f2e: /* ucomiss */ | |
8110 | case 0x660f2e: /* ucomisd */ | |
8111 | case 0x0f2f: /* comiss */ | |
8112 | case 0x660f2f: /* comisd */ | |
8113 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM); | |
8114 | break; | |
8115 | ||
8116 | case 0x0ff7: /* maskmovq */ | |
8117 | regcache_raw_read_unsigned (ir.regcache, | |
8118 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8119 | &addr); | |
8120 | if (record_full_arch_list_add_mem (addr, 64)) | |
8121 | return -1; | |
8122 | break; | |
8123 | ||
8124 | case 0x660ff7: /* maskmovdqu */ | |
8125 | regcache_raw_read_unsigned (ir.regcache, | |
8126 | ir.regmap[X86_RECORD_REDI_REGNUM], | |
8127 | &addr); | |
8128 | if (record_full_arch_list_add_mem (addr, 128)) | |
8129 | return -1; | |
8130 | break; | |
8131 | ||
8132 | default: | |
8133 | goto no_support; | |
8134 | break; | |
8135 | } | |
a3c4230a | 8136 | break; |
7ad10968 HZ |
8137 | |
8138 | default: | |
7ad10968 HZ |
8139 | goto no_support; |
8140 | break; | |
8141 | } | |
8142 | ||
cf648174 | 8143 | /* In the future, maybe still need to deal with need_dasm. */ |
25ea693b MM |
8144 | I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM); |
8145 | if (record_full_arch_list_add_end ()) | |
7ad10968 HZ |
8146 | return -1; |
8147 | ||
8148 | return 0; | |
8149 | ||
01fe1b41 | 8150 | no_support: |
6cb06a8c TT |
8151 | gdb_printf (gdb_stderr, |
8152 | _("Process record does not support instruction 0x%02x " | |
8153 | "at address %s.\n"), | |
8154 | (unsigned int) (opcode), | |
8155 | paddress (gdbarch, ir.orig_addr)); | |
7ad10968 HZ |
8156 | return -1; |
8157 | } | |
8158 | ||
cf648174 HZ |
8159 | static const int i386_record_regmap[] = |
8160 | { | |
8161 | I386_EAX_REGNUM, I386_ECX_REGNUM, I386_EDX_REGNUM, I386_EBX_REGNUM, | |
8162 | I386_ESP_REGNUM, I386_EBP_REGNUM, I386_ESI_REGNUM, I386_EDI_REGNUM, | |
8163 | 0, 0, 0, 0, 0, 0, 0, 0, | |
8164 | I386_EIP_REGNUM, I386_EFLAGS_REGNUM, I386_CS_REGNUM, I386_SS_REGNUM, | |
8165 | I386_DS_REGNUM, I386_ES_REGNUM, I386_FS_REGNUM, I386_GS_REGNUM | |
8166 | }; | |
8167 | ||
7a697b8d | 8168 | /* Check that the given address appears suitable for a fast |
405f8e94 | 8169 | tracepoint, which on x86-64 means that we need an instruction of at |
7a697b8d SS |
8170 | least 5 bytes, so that we can overwrite it with a 4-byte-offset |
8171 | jump and not have to worry about program jumps to an address in the | |
405f8e94 SS |
8172 | middle of the tracepoint jump. On x86, it may be possible to use |
8173 | 4-byte jumps with a 2-byte offset to a trampoline located in the | |
8174 | bottom 64 KiB of memory. Returns 1 if OK, and writes a size | |
7a697b8d SS |
8175 | of instruction to replace, and 0 if not, plus an explanatory |
8176 | string. */ | |
8177 | ||
8178 | static int | |
6b940e6a | 8179 | i386_fast_tracepoint_valid_at (struct gdbarch *gdbarch, CORE_ADDR addr, |
281d762b | 8180 | std::string *msg) |
7a697b8d SS |
8181 | { |
8182 | int len, jumplen; | |
7a697b8d | 8183 | |
405f8e94 SS |
8184 | /* Ask the target for the minimum instruction length supported. */ |
8185 | jumplen = target_get_min_fast_tracepoint_insn_len (); | |
8186 | ||
8187 | if (jumplen < 0) | |
8188 | { | |
8189 | /* If the target does not support the get_min_fast_tracepoint_insn_len | |
8190 | operation, assume that fast tracepoints will always be implemented | |
8191 | using 4-byte relative jumps on both x86 and x86-64. */ | |
8192 | jumplen = 5; | |
8193 | } | |
8194 | else if (jumplen == 0) | |
8195 | { | |
8196 | /* If the target does support get_min_fast_tracepoint_insn_len but | |
8197 | returns zero, then the IPA has not loaded yet. In this case, | |
8198 | we optimistically assume that truncated 2-byte relative jumps | |
8199 | will be available on x86, and compensate later if this assumption | |
8200 | turns out to be incorrect. On x86-64 architectures, 4-byte relative | |
8201 | jumps will always be used. */ | |
8202 | jumplen = (register_size (gdbarch, 0) == 8) ? 5 : 4; | |
8203 | } | |
7a697b8d | 8204 | |
7a697b8d | 8205 | /* Check for fit. */ |
be85ce7d | 8206 | len = gdb_insn_length (gdbarch, addr); |
405f8e94 | 8207 | |
7a697b8d SS |
8208 | if (len < jumplen) |
8209 | { | |
8210 | /* Return a bit of target-specific detail to add to the caller's | |
8211 | generic failure message. */ | |
8212 | if (msg) | |
281d762b TT |
8213 | *msg = string_printf (_("; instruction is only %d bytes long, " |
8214 | "need at least %d bytes for the jump"), | |
8215 | len, jumplen); | |
7a697b8d SS |
8216 | return 0; |
8217 | } | |
405f8e94 SS |
8218 | else |
8219 | { | |
8220 | if (msg) | |
281d762b | 8221 | msg->clear (); |
405f8e94 SS |
8222 | return 1; |
8223 | } | |
7a697b8d SS |
8224 | } |
8225 | ||
00d5215e UW |
8226 | /* Return a floating-point format for a floating-point variable of |
8227 | length LEN in bits. If non-NULL, NAME is the name of its type. | |
8228 | If no suitable type is found, return NULL. */ | |
8229 | ||
cb8c24b6 | 8230 | static const struct floatformat ** |
00d5215e UW |
8231 | i386_floatformat_for_type (struct gdbarch *gdbarch, |
8232 | const char *name, int len) | |
8233 | { | |
8234 | if (len == 128 && name) | |
8235 | if (strcmp (name, "__float128") == 0 | |
8236 | || strcmp (name, "_Float128") == 0 | |
34d11c68 AB |
8237 | || strcmp (name, "complex _Float128") == 0 |
8238 | || strcmp (name, "complex(kind=16)") == 0 | |
ecbc5c4f | 8239 | || strcmp (name, "COMPLEX(16)") == 0 |
8d624a9d FW |
8240 | || strcmp (name, "complex*32") == 0 |
8241 | || strcmp (name, "COMPLEX*32") == 0 | |
e56798df AKS |
8242 | || strcmp (name, "quad complex") == 0 |
8243 | || strcmp (name, "real(kind=16)") == 0 | |
8d624a9d | 8244 | || strcmp (name, "real*16") == 0 |
ecbc5c4f FW |
8245 | || strcmp (name, "REAL*16") == 0 |
8246 | || strcmp (name, "REAL(16)") == 0) | |
552f1157 | 8247 | return floatformats_ieee_quad; |
00d5215e UW |
8248 | |
8249 | return default_floatformat_for_type (gdbarch, name, len); | |
8250 | } | |
8251 | ||
90884b2b | 8252 | static int |
345bd07c | 8253 | i386_validate_tdesc_p (i386_gdbarch_tdep *tdep, |
90884b2b L |
8254 | struct tdesc_arch_data *tdesc_data) |
8255 | { | |
8256 | const struct target_desc *tdesc = tdep->tdesc; | |
c131fcee | 8257 | const struct tdesc_feature *feature_core; |
01f9f808 MS |
8258 | |
8259 | const struct tdesc_feature *feature_sse, *feature_avx, *feature_mpx, | |
1163a4b7 | 8260 | *feature_avx512, *feature_pkeys, *feature_segments; |
90884b2b L |
8261 | int i, num_regs, valid_p; |
8262 | ||
8263 | if (! tdesc_has_registers (tdesc)) | |
8264 | return 0; | |
8265 | ||
8266 | /* Get core registers. */ | |
8267 | feature_core = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.core"); | |
3a13a53b L |
8268 | if (feature_core == NULL) |
8269 | return 0; | |
90884b2b L |
8270 | |
8271 | /* Get SSE registers. */ | |
c131fcee | 8272 | feature_sse = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.sse"); |
90884b2b | 8273 | |
c131fcee L |
8274 | /* Try AVX registers. */ |
8275 | feature_avx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx"); | |
8276 | ||
1dbcd68c WT |
8277 | /* Try MPX registers. */ |
8278 | feature_mpx = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx"); | |
8279 | ||
01f9f808 MS |
8280 | /* Try AVX512 registers. */ |
8281 | feature_avx512 = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.avx512"); | |
8282 | ||
1163a4b7 JB |
8283 | /* Try segment base registers. */ |
8284 | feature_segments = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.segments"); | |
8285 | ||
51547df6 MS |
8286 | /* Try PKEYS */ |
8287 | feature_pkeys = tdesc_find_feature (tdesc, "org.gnu.gdb.i386.pkeys"); | |
8288 | ||
90884b2b L |
8289 | valid_p = 1; |
8290 | ||
c131fcee | 8291 | /* The XCR0 bits. */ |
01f9f808 MS |
8292 | if (feature_avx512) |
8293 | { | |
8294 | /* AVX512 register description requires AVX register description. */ | |
8295 | if (!feature_avx) | |
8296 | return 0; | |
8297 | ||
a1fa17ee | 8298 | tdep->xcr0 = X86_XSTATE_AVX_AVX512_MASK; |
01f9f808 MS |
8299 | |
8300 | /* It may have been set by OSABI initialization function. */ | |
8301 | if (tdep->k0_regnum < 0) | |
8302 | { | |
8303 | tdep->k_register_names = i386_k_names; | |
8304 | tdep->k0_regnum = I386_K0_REGNUM; | |
8305 | } | |
8306 | ||
8307 | for (i = 0; i < I387_NUM_K_REGS; i++) | |
8308 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8309 | tdep->k0_regnum + i, | |
8310 | i386_k_names[i]); | |
8311 | ||
8312 | if (tdep->num_zmm_regs == 0) | |
8313 | { | |
8314 | tdep->zmmh_register_names = i386_zmmh_names; | |
8315 | tdep->num_zmm_regs = 8; | |
8316 | tdep->zmm0h_regnum = I386_ZMM0H_REGNUM; | |
8317 | } | |
8318 | ||
8319 | for (i = 0; i < tdep->num_zmm_regs; i++) | |
8320 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8321 | tdep->zmm0h_regnum + i, | |
8322 | tdep->zmmh_register_names[i]); | |
8323 | ||
8324 | for (i = 0; i < tdep->num_xmm_avx512_regs; i++) | |
8325 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8326 | tdep->xmm16_regnum + i, | |
8327 | tdep->xmm_avx512_register_names[i]); | |
8328 | ||
8329 | for (i = 0; i < tdep->num_ymm_avx512_regs; i++) | |
8330 | valid_p &= tdesc_numbered_register (feature_avx512, tdesc_data, | |
8331 | tdep->ymm16h_regnum + i, | |
8332 | tdep->ymm16h_register_names[i]); | |
8333 | } | |
c131fcee L |
8334 | if (feature_avx) |
8335 | { | |
3a13a53b L |
8336 | /* AVX register description requires SSE register description. */ |
8337 | if (!feature_sse) | |
8338 | return 0; | |
8339 | ||
01f9f808 | 8340 | if (!feature_avx512) |
df7e5265 | 8341 | tdep->xcr0 = X86_XSTATE_AVX_MASK; |
c131fcee L |
8342 | |
8343 | /* It may have been set by OSABI initialization function. */ | |
8344 | if (tdep->num_ymm_regs == 0) | |
8345 | { | |
8346 | tdep->ymmh_register_names = i386_ymmh_names; | |
8347 | tdep->num_ymm_regs = 8; | |
8348 | tdep->ymm0h_regnum = I386_YMM0H_REGNUM; | |
8349 | } | |
8350 | ||
8351 | for (i = 0; i < tdep->num_ymm_regs; i++) | |
8352 | valid_p &= tdesc_numbered_register (feature_avx, tdesc_data, | |
8353 | tdep->ymm0h_regnum + i, | |
8354 | tdep->ymmh_register_names[i]); | |
8355 | } | |
3a13a53b | 8356 | else if (feature_sse) |
df7e5265 | 8357 | tdep->xcr0 = X86_XSTATE_SSE_MASK; |
3a13a53b L |
8358 | else |
8359 | { | |
df7e5265 | 8360 | tdep->xcr0 = X86_XSTATE_X87_MASK; |
3a13a53b L |
8361 | tdep->num_xmm_regs = 0; |
8362 | } | |
c131fcee | 8363 | |
90884b2b L |
8364 | num_regs = tdep->num_core_regs; |
8365 | for (i = 0; i < num_regs; i++) | |
8366 | valid_p &= tdesc_numbered_register (feature_core, tdesc_data, i, | |
8367 | tdep->register_names[i]); | |
8368 | ||
3a13a53b L |
8369 | if (feature_sse) |
8370 | { | |
8371 | /* Need to include %mxcsr, so add one. */ | |
8372 | num_regs += tdep->num_xmm_regs + 1; | |
8373 | for (; i < num_regs; i++) | |
8374 | valid_p &= tdesc_numbered_register (feature_sse, tdesc_data, i, | |
8375 | tdep->register_names[i]); | |
8376 | } | |
90884b2b | 8377 | |
1dbcd68c WT |
8378 | if (feature_mpx) |
8379 | { | |
df7e5265 | 8380 | tdep->xcr0 |= X86_XSTATE_MPX_MASK; |
1dbcd68c WT |
8381 | |
8382 | if (tdep->bnd0r_regnum < 0) | |
8383 | { | |
8384 | tdep->mpx_register_names = i386_mpx_names; | |
8385 | tdep->bnd0r_regnum = I386_BND0R_REGNUM; | |
8386 | tdep->bndcfgu_regnum = I386_BNDCFGU_REGNUM; | |
8387 | } | |
8388 | ||
8389 | for (i = 0; i < I387_NUM_MPX_REGS; i++) | |
8390 | valid_p &= tdesc_numbered_register (feature_mpx, tdesc_data, | |
8391 | I387_BND0R_REGNUM (tdep) + i, | |
8392 | tdep->mpx_register_names[i]); | |
8393 | } | |
8394 | ||
1163a4b7 JB |
8395 | if (feature_segments) |
8396 | { | |
8397 | if (tdep->fsbase_regnum < 0) | |
8398 | tdep->fsbase_regnum = I386_FSBASE_REGNUM; | |
8399 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8400 | tdep->fsbase_regnum, "fs_base"); | |
8401 | valid_p &= tdesc_numbered_register (feature_segments, tdesc_data, | |
8402 | tdep->fsbase_regnum + 1, "gs_base"); | |
8403 | } | |
8404 | ||
51547df6 MS |
8405 | if (feature_pkeys) |
8406 | { | |
8407 | tdep->xcr0 |= X86_XSTATE_PKRU; | |
8408 | if (tdep->pkru_regnum < 0) | |
8409 | { | |
8410 | tdep->pkeys_register_names = i386_pkeys_names; | |
8411 | tdep->pkru_regnum = I386_PKRU_REGNUM; | |
8412 | tdep->num_pkeys_regs = 1; | |
8413 | } | |
8414 | ||
8415 | for (i = 0; i < I387_NUM_PKEYS_REGS; i++) | |
8416 | valid_p &= tdesc_numbered_register (feature_pkeys, tdesc_data, | |
8417 | I387_PKRU_REGNUM (tdep) + i, | |
8418 | tdep->pkeys_register_names[i]); | |
8419 | } | |
8420 | ||
90884b2b L |
8421 | return valid_p; |
8422 | } | |
8423 | ||
2b4424c3 TT |
8424 | \f |
8425 | ||
8426 | /* Implement the type_align gdbarch function. */ | |
8427 | ||
8428 | static ULONGEST | |
8429 | i386_type_align (struct gdbarch *gdbarch, struct type *type) | |
8430 | { | |
8431 | type = check_typedef (type); | |
8432 | ||
8433 | if (gdbarch_ptr_bit (gdbarch) == 32) | |
8434 | { | |
78134374 SM |
8435 | if ((type->code () == TYPE_CODE_INT |
8436 | || type->code () == TYPE_CODE_FLT) | |
df86565b | 8437 | && type->length () > 4) |
2b4424c3 TT |
8438 | return 4; |
8439 | ||
8440 | /* Handle x86's funny long double. */ | |
78134374 | 8441 | if (type->code () == TYPE_CODE_FLT |
df86565b | 8442 | && gdbarch_long_double_bit (gdbarch) == type->length () * 8) |
2b4424c3 TT |
8443 | return 4; |
8444 | } | |
8445 | ||
5561fc30 | 8446 | return 0; |
2b4424c3 TT |
8447 | } |
8448 | ||
7ad10968 | 8449 | \f |
ad9eb1fd DE |
8450 | /* Note: This is called for both i386 and amd64. */ |
8451 | ||
7ad10968 HZ |
8452 | static struct gdbarch * |
8453 | i386_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
8454 | { | |
90884b2b | 8455 | const struct target_desc *tdesc; |
1ba53b71 | 8456 | int mm0_regnum; |
c131fcee | 8457 | int ymm0_regnum; |
1dbcd68c WT |
8458 | int bnd0_regnum; |
8459 | int num_bnd_cooked; | |
7ad10968 HZ |
8460 | |
8461 | /* If there is already a candidate, use it. */ | |
8462 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
8463 | if (arches != NULL) | |
8464 | return arches->gdbarch; | |
8465 | ||
ad9eb1fd | 8466 | /* Allocate space for the new architecture. Assume i386 for now. */ |
2b16913c SM |
8467 | gdbarch *gdbarch |
8468 | = gdbarch_alloc (&info, gdbarch_tdep_up (new i386_gdbarch_tdep)); | |
8469 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); | |
7ad10968 HZ |
8470 | |
8471 | /* General-purpose registers. */ | |
7ad10968 HZ |
8472 | tdep->gregset_reg_offset = NULL; |
8473 | tdep->gregset_num_regs = I386_NUM_GREGS; | |
8474 | tdep->sizeof_gregset = 0; | |
8475 | ||
8476 | /* Floating-point registers. */ | |
7ad10968 | 8477 | tdep->sizeof_fpregset = I387_SIZEOF_FSAVE; |
8f0435f7 | 8478 | tdep->fpregset = &i386_fpregset; |
7ad10968 HZ |
8479 | |
8480 | /* The default settings include the FPU registers, the MMX registers | |
8481 | and the SSE registers. This can be overridden for a specific ABI | |
8482 | by adjusting the members `st0_regnum', `mm0_regnum' and | |
8483 | `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers | |
3a13a53b | 8484 | will show up in the output of "info all-registers". */ |
7ad10968 HZ |
8485 | |
8486 | tdep->st0_regnum = I386_ST0_REGNUM; | |
8487 | ||
7ad10968 HZ |
8488 | /* I386_NUM_XREGS includes %mxcsr, so substract one. */ |
8489 | tdep->num_xmm_regs = I386_NUM_XREGS - 1; | |
8490 | ||
8491 | tdep->jb_pc_offset = -1; | |
8492 | tdep->struct_return = pcc_struct_return; | |
8493 | tdep->sigtramp_start = 0; | |
8494 | tdep->sigtramp_end = 0; | |
8495 | tdep->sigtramp_p = i386_sigtramp_p; | |
8496 | tdep->sigcontext_addr = NULL; | |
8497 | tdep->sc_reg_offset = NULL; | |
8498 | tdep->sc_pc_offset = -1; | |
8499 | tdep->sc_sp_offset = -1; | |
8500 | ||
c131fcee L |
8501 | tdep->xsave_xcr0_offset = -1; |
8502 | ||
cf648174 HZ |
8503 | tdep->record_regmap = i386_record_regmap; |
8504 | ||
2b4424c3 | 8505 | set_gdbarch_type_align (gdbarch, i386_type_align); |
205c306f | 8506 | |
7ad10968 HZ |
8507 | /* The format used for `long double' on almost all i386 targets is |
8508 | the i387 extended floating-point format. In fact, of all targets | |
8509 | in the GCC 2.95 tree, only OSF/1 does it different, and insists | |
8510 | on having a `long double' that's not `long' at all. */ | |
8511 | set_gdbarch_long_double_format (gdbarch, floatformats_i387_ext); | |
8512 | ||
8513 | /* Although the i387 extended floating-point has only 80 significant | |
8514 | bits, a `long double' actually takes up 96, probably to enforce | |
8515 | alignment. */ | |
8516 | set_gdbarch_long_double_bit (gdbarch, 96); | |
8517 | ||
2a67f09d FW |
8518 | /* Support of bfloat16 format. */ |
8519 | set_gdbarch_bfloat16_format (gdbarch, floatformats_bfloat16); | |
8520 | ||
00d5215e UW |
8521 | /* Support for floating-point data type variants. */ |
8522 | set_gdbarch_floatformat_for_type (gdbarch, i386_floatformat_for_type); | |
8523 | ||
7ad10968 HZ |
8524 | /* Register numbers of various important registers. */ |
8525 | set_gdbarch_sp_regnum (gdbarch, I386_ESP_REGNUM); /* %esp */ | |
8526 | set_gdbarch_pc_regnum (gdbarch, I386_EIP_REGNUM); /* %eip */ | |
8527 | set_gdbarch_ps_regnum (gdbarch, I386_EFLAGS_REGNUM); /* %eflags */ | |
8528 | set_gdbarch_fp0_regnum (gdbarch, I386_ST0_REGNUM); /* %st(0) */ | |
8529 | ||
8530 | /* NOTE: kettenis/20040418: GCC does have two possible register | |
8531 | numbering schemes on the i386: dbx and SVR4. These schemes | |
8532 | differ in how they number %ebp, %esp, %eflags, and the | |
8533 | floating-point registers, and are implemented by the arrays | |
8534 | dbx_register_map[] and svr4_dbx_register_map in | |
8535 | gcc/config/i386.c. GCC also defines a third numbering scheme in | |
8536 | gcc/config/i386.c, which it designates as the "default" register | |
8537 | map used in 64bit mode. This last register numbering scheme is | |
8538 | implemented in dbx64_register_map, and is used for AMD64; see | |
8539 | amd64-tdep.c. | |
8540 | ||
8541 | Currently, each GCC i386 target always uses the same register | |
8542 | numbering scheme across all its supported debugging formats | |
8543 | i.e. SDB (COFF), stabs and DWARF 2. This is because | |
8544 | gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the | |
8545 | DBX_REGISTER_NUMBER macro which is defined by each target's | |
8546 | respective config header in a manner independent of the requested | |
8547 | output debugging format. | |
8548 | ||
8549 | This does not match the arrangement below, which presumes that | |
8550 | the SDB and stabs numbering schemes differ from the DWARF and | |
8551 | DWARF 2 ones. The reason for this arrangement is that it is | |
8552 | likely to get the numbering scheme for the target's | |
8553 | default/native debug format right. For targets where GCC is the | |
8554 | native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for | |
8555 | targets where the native toolchain uses a different numbering | |
8556 | scheme for a particular debug format (stabs-in-ELF on Solaris) | |
8557 | the defaults below will have to be overridden, like | |
8558 | i386_elf_init_abi() does. */ | |
8559 | ||
8560 | /* Use the dbx register numbering scheme for stabs and COFF. */ | |
8561 | set_gdbarch_stab_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8562 | set_gdbarch_sdb_reg_to_regnum (gdbarch, i386_dbx_reg_to_regnum); | |
8563 | ||
8564 | /* Use the SVR4 register numbering scheme for DWARF 2. */ | |
0fde2c53 | 8565 | set_gdbarch_dwarf2_reg_to_regnum (gdbarch, i386_svr4_dwarf_reg_to_regnum); |
7ad10968 HZ |
8566 | |
8567 | /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to | |
8568 | be in use on any of the supported i386 targets. */ | |
8569 | ||
8570 | set_gdbarch_print_float_info (gdbarch, i387_print_float_info); | |
8571 | ||
8572 | set_gdbarch_get_longjmp_target (gdbarch, i386_get_longjmp_target); | |
8573 | ||
8574 | /* Call dummy code. */ | |
a9b8d892 JK |
8575 | set_gdbarch_call_dummy_location (gdbarch, ON_STACK); |
8576 | set_gdbarch_push_dummy_code (gdbarch, i386_push_dummy_code); | |
7ad10968 | 8577 | set_gdbarch_push_dummy_call (gdbarch, i386_push_dummy_call); |
e04e5beb | 8578 | set_gdbarch_frame_align (gdbarch, i386_frame_align); |
7ad10968 HZ |
8579 | |
8580 | set_gdbarch_convert_register_p (gdbarch, i386_convert_register_p); | |
8581 | set_gdbarch_register_to_value (gdbarch, i386_register_to_value); | |
8582 | set_gdbarch_value_to_register (gdbarch, i386_value_to_register); | |
8583 | ||
5cb0f2d5 | 8584 | set_gdbarch_return_value_as_value (gdbarch, i386_return_value); |
7ad10968 HZ |
8585 | |
8586 | set_gdbarch_skip_prologue (gdbarch, i386_skip_prologue); | |
8587 | ||
8588 | /* Stack grows downward. */ | |
8589 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
8590 | ||
04180708 YQ |
8591 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, i386_breakpoint::kind_from_pc); |
8592 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, i386_breakpoint::bp_from_kind); | |
8593 | ||
7ad10968 HZ |
8594 | set_gdbarch_decr_pc_after_break (gdbarch, 1); |
8595 | set_gdbarch_max_insn_length (gdbarch, I386_MAX_INSN_LEN); | |
8596 | ||
8597 | set_gdbarch_frame_args_skip (gdbarch, 8); | |
8598 | ||
7ad10968 HZ |
8599 | set_gdbarch_print_insn (gdbarch, i386_print_insn); |
8600 | ||
8601 | set_gdbarch_dummy_id (gdbarch, i386_dummy_id); | |
8602 | ||
8603 | set_gdbarch_unwind_pc (gdbarch, i386_unwind_pc); | |
8604 | ||
8605 | /* Add the i386 register groups. */ | |
8606 | i386_add_reggroups (gdbarch); | |
90884b2b | 8607 | tdep->register_reggroup_p = i386_register_reggroup_p; |
38c968cf | 8608 | |
143985b7 AF |
8609 | /* Helper for function argument information. */ |
8610 | set_gdbarch_fetch_pointer_argument (gdbarch, i386_fetch_pointer_argument); | |
8611 | ||
06da04c6 | 8612 | /* Hook the function epilogue frame unwinder. This unwinder is |
0d6c2135 MK |
8613 | appended to the list first, so that it supercedes the DWARF |
8614 | unwinder in function epilogues (where the DWARF unwinder | |
06da04c6 | 8615 | currently fails). */ |
af0d0f34 TV |
8616 | if (info.bfd_arch_info->bits_per_word == 32) |
8617 | frame_unwind_append_unwinder (gdbarch, &i386_epilogue_frame_unwind); | |
06da04c6 MS |
8618 | |
8619 | /* Hook in the DWARF CFI frame unwinder. This unwinder is appended | |
0d6c2135 | 8620 | to the list before the prologue-based unwinders, so that DWARF |
06da04c6 | 8621 | CFI info will be used if it is available. */ |
10458914 | 8622 | dwarf2_append_unwinders (gdbarch); |
6405b0a6 | 8623 | |
acd5c798 | 8624 | frame_base_set_default (gdbarch, &i386_frame_base); |
6c0e89ed | 8625 | |
1ba53b71 | 8626 | /* Pseudo registers may be changed by amd64_init_abi. */ |
3543a589 TT |
8627 | set_gdbarch_pseudo_register_read_value (gdbarch, |
8628 | i386_pseudo_register_read_value); | |
90884b2b | 8629 | set_gdbarch_pseudo_register_write (gdbarch, i386_pseudo_register_write); |
62e5fd57 MK |
8630 | set_gdbarch_ax_pseudo_register_collect (gdbarch, |
8631 | i386_ax_pseudo_register_collect); | |
90884b2b L |
8632 | |
8633 | set_tdesc_pseudo_register_type (gdbarch, i386_pseudo_register_type); | |
8634 | set_tdesc_pseudo_register_name (gdbarch, i386_pseudo_register_name); | |
8635 | ||
c131fcee L |
8636 | /* Override the normal target description method to make the AVX |
8637 | upper halves anonymous. */ | |
8638 | set_gdbarch_register_name (gdbarch, i386_register_name); | |
8639 | ||
8640 | /* Even though the default ABI only includes general-purpose registers, | |
8641 | floating-point registers and the SSE registers, we have to leave a | |
01f9f808 | 8642 | gap for the upper AVX, MPX and AVX512 registers. */ |
1163a4b7 | 8643 | set_gdbarch_num_regs (gdbarch, I386_NUM_REGS); |
90884b2b | 8644 | |
ac04f72b TT |
8645 | set_gdbarch_gnu_triplet_regexp (gdbarch, i386_gnu_triplet_regexp); |
8646 | ||
90884b2b L |
8647 | /* Get the x86 target description from INFO. */ |
8648 | tdesc = info.target_desc; | |
8649 | if (! tdesc_has_registers (tdesc)) | |
1163a4b7 | 8650 | tdesc = i386_target_description (X86_XSTATE_SSE_MASK, false); |
90884b2b L |
8651 | tdep->tdesc = tdesc; |
8652 | ||
8653 | tdep->num_core_regs = I386_NUM_GREGS + I387_NUM_REGS; | |
8654 | tdep->register_names = i386_register_names; | |
8655 | ||
c131fcee L |
8656 | /* No upper YMM registers. */ |
8657 | tdep->ymmh_register_names = NULL; | |
8658 | tdep->ymm0h_regnum = -1; | |
8659 | ||
01f9f808 MS |
8660 | /* No upper ZMM registers. */ |
8661 | tdep->zmmh_register_names = NULL; | |
8662 | tdep->zmm0h_regnum = -1; | |
8663 | ||
8664 | /* No high XMM registers. */ | |
8665 | tdep->xmm_avx512_register_names = NULL; | |
8666 | tdep->xmm16_regnum = -1; | |
8667 | ||
8668 | /* No upper YMM16-31 registers. */ | |
8669 | tdep->ymm16h_register_names = NULL; | |
8670 | tdep->ymm16h_regnum = -1; | |
8671 | ||
1ba53b71 L |
8672 | tdep->num_byte_regs = 8; |
8673 | tdep->num_word_regs = 8; | |
8674 | tdep->num_dword_regs = 0; | |
8675 | tdep->num_mmx_regs = 8; | |
c131fcee | 8676 | tdep->num_ymm_regs = 0; |
1ba53b71 | 8677 | |
1dbcd68c WT |
8678 | /* No MPX registers. */ |
8679 | tdep->bnd0r_regnum = -1; | |
8680 | tdep->bndcfgu_regnum = -1; | |
8681 | ||
01f9f808 MS |
8682 | /* No AVX512 registers. */ |
8683 | tdep->k0_regnum = -1; | |
8684 | tdep->num_zmm_regs = 0; | |
8685 | tdep->num_ymm_avx512_regs = 0; | |
8686 | tdep->num_xmm_avx512_regs = 0; | |
8687 | ||
51547df6 MS |
8688 | /* No PKEYS registers */ |
8689 | tdep->pkru_regnum = -1; | |
8690 | tdep->num_pkeys_regs = 0; | |
8691 | ||
1163a4b7 JB |
8692 | /* No segment base registers. */ |
8693 | tdep->fsbase_regnum = -1; | |
8694 | ||
c1e1314d | 8695 | tdesc_arch_data_up tdesc_data = tdesc_data_alloc (); |
90884b2b | 8696 | |
dde08ee1 PA |
8697 | set_gdbarch_relocate_instruction (gdbarch, i386_relocate_instruction); |
8698 | ||
6710bf39 SS |
8699 | set_gdbarch_gen_return_address (gdbarch, i386_gen_return_address); |
8700 | ||
c2170eef MM |
8701 | set_gdbarch_insn_is_call (gdbarch, i386_insn_is_call); |
8702 | set_gdbarch_insn_is_ret (gdbarch, i386_insn_is_ret); | |
8703 | set_gdbarch_insn_is_jump (gdbarch, i386_insn_is_jump); | |
8704 | ||
ad9eb1fd DE |
8705 | /* Hook in ABI-specific overrides, if they have been registered. |
8706 | Note: If INFO specifies a 64 bit arch, this is where we turn | |
8707 | a 32-bit i386 into a 64-bit amd64. */ | |
c1e1314d | 8708 | info.tdesc_data = tdesc_data.get (); |
4be87837 | 8709 | gdbarch_init_osabi (info, gdbarch); |
3ce1502b | 8710 | |
c1e1314d | 8711 | if (!i386_validate_tdesc_p (tdep, tdesc_data.get ())) |
c131fcee | 8712 | { |
c131fcee L |
8713 | gdbarch_free (gdbarch); |
8714 | return NULL; | |
8715 | } | |
8716 | ||
1dbcd68c WT |
8717 | num_bnd_cooked = (tdep->bnd0r_regnum > 0 ? I387_NUM_BND_REGS : 0); |
8718 | ||
1ba53b71 L |
8719 | /* Wire in pseudo registers. Number of pseudo registers may be |
8720 | changed. */ | |
8721 | set_gdbarch_num_pseudo_regs (gdbarch, (tdep->num_byte_regs | |
8722 | + tdep->num_word_regs | |
8723 | + tdep->num_dword_regs | |
c131fcee | 8724 | + tdep->num_mmx_regs |
1dbcd68c | 8725 | + tdep->num_ymm_regs |
01f9f808 MS |
8726 | + num_bnd_cooked |
8727 | + tdep->num_ymm_avx512_regs | |
8728 | + tdep->num_zmm_regs)); | |
1ba53b71 | 8729 | |
90884b2b L |
8730 | /* Target description may be changed. */ |
8731 | tdesc = tdep->tdesc; | |
8732 | ||
c1e1314d | 8733 | tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); |
90884b2b L |
8734 | |
8735 | /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */ | |
8736 | set_gdbarch_register_reggroup_p (gdbarch, tdep->register_reggroup_p); | |
8737 | ||
1ba53b71 L |
8738 | /* Make %al the first pseudo-register. */ |
8739 | tdep->al_regnum = gdbarch_num_regs (gdbarch); | |
8740 | tdep->ax_regnum = tdep->al_regnum + tdep->num_byte_regs; | |
8741 | ||
c131fcee | 8742 | ymm0_regnum = tdep->ax_regnum + tdep->num_word_regs; |
1ba53b71 L |
8743 | if (tdep->num_dword_regs) |
8744 | { | |
1c6272a6 | 8745 | /* Support dword pseudo-register if it hasn't been disabled. */ |
c131fcee L |
8746 | tdep->eax_regnum = ymm0_regnum; |
8747 | ymm0_regnum += tdep->num_dword_regs; | |
1ba53b71 L |
8748 | } |
8749 | else | |
8750 | tdep->eax_regnum = -1; | |
8751 | ||
c131fcee L |
8752 | mm0_regnum = ymm0_regnum; |
8753 | if (tdep->num_ymm_regs) | |
8754 | { | |
1c6272a6 | 8755 | /* Support YMM pseudo-register if it is available. */ |
c131fcee L |
8756 | tdep->ymm0_regnum = ymm0_regnum; |
8757 | mm0_regnum += tdep->num_ymm_regs; | |
8758 | } | |
8759 | else | |
8760 | tdep->ymm0_regnum = -1; | |
8761 | ||
01f9f808 MS |
8762 | if (tdep->num_ymm_avx512_regs) |
8763 | { | |
8764 | /* Support YMM16-31 pseudo registers if available. */ | |
8765 | tdep->ymm16_regnum = mm0_regnum; | |
8766 | mm0_regnum += tdep->num_ymm_avx512_regs; | |
8767 | } | |
8768 | else | |
8769 | tdep->ymm16_regnum = -1; | |
8770 | ||
8771 | if (tdep->num_zmm_regs) | |
8772 | { | |
8773 | /* Support ZMM pseudo-register if it is available. */ | |
8774 | tdep->zmm0_regnum = mm0_regnum; | |
8775 | mm0_regnum += tdep->num_zmm_regs; | |
8776 | } | |
8777 | else | |
8778 | tdep->zmm0_regnum = -1; | |
8779 | ||
1dbcd68c | 8780 | bnd0_regnum = mm0_regnum; |
1ba53b71 L |
8781 | if (tdep->num_mmx_regs != 0) |
8782 | { | |
1c6272a6 | 8783 | /* Support MMX pseudo-register if MMX hasn't been disabled. */ |
1ba53b71 | 8784 | tdep->mm0_regnum = mm0_regnum; |
1dbcd68c | 8785 | bnd0_regnum += tdep->num_mmx_regs; |
1ba53b71 L |
8786 | } |
8787 | else | |
8788 | tdep->mm0_regnum = -1; | |
8789 | ||
1dbcd68c WT |
8790 | if (tdep->bnd0r_regnum > 0) |
8791 | tdep->bnd0_regnum = bnd0_regnum; | |
8792 | else | |
8793 | tdep-> bnd0_regnum = -1; | |
8794 | ||
06da04c6 | 8795 | /* Hook in the legacy prologue-based unwinders last (fallback). */ |
af0d0f34 TV |
8796 | if (info.bfd_arch_info->bits_per_word == 32) |
8797 | { | |
8798 | frame_unwind_append_unwinder (gdbarch, &i386_stack_tramp_frame_unwind); | |
8799 | frame_unwind_append_unwinder (gdbarch, &i386_sigtramp_frame_unwind); | |
8800 | frame_unwind_append_unwinder (gdbarch, &i386_frame_unwind); | |
8801 | } | |
acd5c798 | 8802 | |
8446b36a MK |
8803 | /* If we have a register mapping, enable the generic core file |
8804 | support, unless it has already been enabled. */ | |
8805 | if (tdep->gregset_reg_offset | |
8f0435f7 | 8806 | && !gdbarch_iterate_over_regset_sections_p (gdbarch)) |
490496c3 AA |
8807 | set_gdbarch_iterate_over_regset_sections |
8808 | (gdbarch, i386_iterate_over_regset_sections); | |
8446b36a | 8809 | |
7a697b8d SS |
8810 | set_gdbarch_fast_tracepoint_valid_at (gdbarch, |
8811 | i386_fast_tracepoint_valid_at); | |
8812 | ||
a62cc96e AC |
8813 | return gdbarch; |
8814 | } | |
8815 | ||
8201327c MK |
8816 | \f |
8817 | ||
97de3545 JB |
8818 | /* Return the target description for a specified XSAVE feature mask. */ |
8819 | ||
8820 | const struct target_desc * | |
1163a4b7 | 8821 | i386_target_description (uint64_t xcr0, bool segments) |
97de3545 | 8822 | { |
22916b07 | 8823 | static target_desc *i386_tdescs \ |
1163a4b7 | 8824 | [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; |
22916b07 YQ |
8825 | target_desc **tdesc; |
8826 | ||
8827 | tdesc = &i386_tdescs[(xcr0 & X86_XSTATE_SSE) ? 1 : 0] | |
8828 | [(xcr0 & X86_XSTATE_AVX) ? 1 : 0] | |
8829 | [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] | |
8830 | [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] | |
1163a4b7 JB |
8831 | [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] |
8832 | [segments ? 1 : 0]; | |
22916b07 YQ |
8833 | |
8834 | if (*tdesc == NULL) | |
1163a4b7 | 8835 | *tdesc = i386_create_target_description (xcr0, false, segments); |
22916b07 YQ |
8836 | |
8837 | return *tdesc; | |
97de3545 JB |
8838 | } |
8839 | ||
29c1c244 WT |
8840 | #define MPX_BASE_MASK (~(ULONGEST) 0xfff) |
8841 | ||
8842 | /* Find the bound directory base address. */ | |
8843 | ||
8844 | static unsigned long | |
8845 | i386_mpx_bd_base (void) | |
8846 | { | |
8847 | struct regcache *rcache; | |
29c1c244 WT |
8848 | ULONGEST ret; |
8849 | enum register_status regstatus; | |
29c1c244 WT |
8850 | |
8851 | rcache = get_current_regcache (); | |
345bd07c | 8852 | gdbarch *arch = rcache->arch (); |
08106042 | 8853 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
29c1c244 WT |
8854 | |
8855 | regstatus = regcache_raw_read_unsigned (rcache, tdep->bndcfgu_regnum, &ret); | |
8856 | ||
8857 | if (regstatus != REG_VALID) | |
8858 | error (_("BNDCFGU register invalid, read status %d."), regstatus); | |
8859 | ||
8860 | return ret & MPX_BASE_MASK; | |
8861 | } | |
8862 | ||
012b3a21 | 8863 | int |
29c1c244 WT |
8864 | i386_mpx_enabled (void) |
8865 | { | |
345bd07c | 8866 | gdbarch *arch = get_current_arch (); |
08106042 | 8867 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
29c1c244 WT |
8868 | const struct target_desc *tdesc = tdep->tdesc; |
8869 | ||
8870 | return (tdesc_find_feature (tdesc, "org.gnu.gdb.i386.mpx") != NULL); | |
8871 | } | |
8872 | ||
8873 | #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */ | |
8874 | #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */ | |
8875 | #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */ | |
8876 | #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */ | |
8877 | ||
8878 | /* Find the bound table entry given the pointer location and the base | |
8879 | address of the table. */ | |
8880 | ||
8881 | static CORE_ADDR | |
8882 | i386_mpx_get_bt_entry (CORE_ADDR ptr, CORE_ADDR bd_base) | |
8883 | { | |
8884 | CORE_ADDR offset1; | |
8885 | CORE_ADDR offset2; | |
8886 | CORE_ADDR mpx_bd_mask, bd_ptr_r_shift, bd_ptr_l_shift; | |
8887 | CORE_ADDR bt_mask, bt_select_r_shift, bt_select_l_shift; | |
8888 | CORE_ADDR bd_entry_addr; | |
8889 | CORE_ADDR bt_addr; | |
8890 | CORE_ADDR bd_entry; | |
8891 | struct gdbarch *gdbarch = get_current_arch (); | |
8892 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8893 | ||
8894 | ||
8895 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8896 | { | |
966f0aef | 8897 | mpx_bd_mask = (CORE_ADDR) MPX_BD_MASK; |
29c1c244 WT |
8898 | bd_ptr_r_shift = 20; |
8899 | bd_ptr_l_shift = 3; | |
8900 | bt_select_r_shift = 3; | |
8901 | bt_select_l_shift = 5; | |
966f0aef WT |
8902 | bt_mask = (CORE_ADDR) MPX_BT_MASK; |
8903 | ||
8904 | if ( sizeof (CORE_ADDR) == 4) | |
e00b3c9b WT |
8905 | error (_("bound table examination not supported\ |
8906 | for 64-bit process with 32-bit GDB")); | |
29c1c244 WT |
8907 | } |
8908 | else | |
8909 | { | |
8910 | mpx_bd_mask = MPX_BD_MASK_32; | |
8911 | bd_ptr_r_shift = 12; | |
8912 | bd_ptr_l_shift = 2; | |
8913 | bt_select_r_shift = 2; | |
8914 | bt_select_l_shift = 4; | |
8915 | bt_mask = MPX_BT_MASK_32; | |
8916 | } | |
8917 | ||
8918 | offset1 = ((ptr & mpx_bd_mask) >> bd_ptr_r_shift) << bd_ptr_l_shift; | |
8919 | bd_entry_addr = bd_base + offset1; | |
8920 | bd_entry = read_memory_typed_address (bd_entry_addr, data_ptr_type); | |
8921 | ||
8922 | if ((bd_entry & 0x1) == 0) | |
8923 | error (_("Invalid bounds directory entry at %s."), | |
8924 | paddress (get_current_arch (), bd_entry_addr)); | |
8925 | ||
8926 | /* Clearing status bit. */ | |
8927 | bd_entry--; | |
8928 | bt_addr = bd_entry & ~bt_select_r_shift; | |
8929 | offset2 = ((ptr & bt_mask) >> bt_select_r_shift) << bt_select_l_shift; | |
8930 | ||
8931 | return bt_addr + offset2; | |
8932 | } | |
8933 | ||
8934 | /* Print routine for the mpx bounds. */ | |
8935 | ||
8936 | static void | |
8937 | i386_mpx_print_bounds (const CORE_ADDR bt_entry[4]) | |
8938 | { | |
8939 | struct ui_out *uiout = current_uiout; | |
34f8ac9f | 8940 | LONGEST size; |
29c1c244 WT |
8941 | struct gdbarch *gdbarch = get_current_arch (); |
8942 | CORE_ADDR onecompl = ~((CORE_ADDR) 0); | |
8943 | int bounds_in_map = ((~bt_entry[1] == 0 && bt_entry[0] == onecompl) ? 1 : 0); | |
8944 | ||
8945 | if (bounds_in_map == 1) | |
8946 | { | |
112e8700 SM |
8947 | uiout->text ("Null bounds on map:"); |
8948 | uiout->text (" pointer value = "); | |
8949 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
8950 | uiout->text ("."); | |
8951 | uiout->text ("\n"); | |
29c1c244 WT |
8952 | } |
8953 | else | |
8954 | { | |
112e8700 SM |
8955 | uiout->text ("{lbound = "); |
8956 | uiout->field_core_addr ("lower-bound", gdbarch, bt_entry[0]); | |
8957 | uiout->text (", ubound = "); | |
29c1c244 WT |
8958 | |
8959 | /* The upper bound is stored in 1's complement. */ | |
112e8700 SM |
8960 | uiout->field_core_addr ("upper-bound", gdbarch, ~bt_entry[1]); |
8961 | uiout->text ("}: pointer value = "); | |
8962 | uiout->field_core_addr ("pointer-value", gdbarch, bt_entry[2]); | |
29c1c244 WT |
8963 | |
8964 | if (gdbarch_ptr_bit (gdbarch) == 64) | |
8965 | size = ( (~(int64_t) bt_entry[1]) - (int64_t) bt_entry[0]); | |
8966 | else | |
8967 | size = ( ~((int32_t) bt_entry[1]) - (int32_t) bt_entry[0]); | |
8968 | ||
8969 | /* In case the bounds are 0x0 and 0xffff... the difference will be -1. | |
8970 | -1 represents in this sense full memory access, and there is no need | |
8971 | one to the size. */ | |
8972 | ||
8973 | size = (size > -1 ? size + 1 : size); | |
112e8700 | 8974 | uiout->text (", size = "); |
33eca680 | 8975 | uiout->field_string ("size", plongest (size)); |
29c1c244 | 8976 | |
112e8700 SM |
8977 | uiout->text (", metadata = "); |
8978 | uiout->field_core_addr ("metadata", gdbarch, bt_entry[3]); | |
8979 | uiout->text ("\n"); | |
29c1c244 WT |
8980 | } |
8981 | } | |
8982 | ||
8983 | /* Implement the command "show mpx bound". */ | |
8984 | ||
8985 | static void | |
c4a3e68e | 8986 | i386_mpx_info_bounds (const char *args, int from_tty) |
29c1c244 WT |
8987 | { |
8988 | CORE_ADDR bd_base = 0; | |
8989 | CORE_ADDR addr; | |
8990 | CORE_ADDR bt_entry_addr = 0; | |
8991 | CORE_ADDR bt_entry[4]; | |
8992 | int i; | |
8993 | struct gdbarch *gdbarch = get_current_arch (); | |
8994 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
8995 | ||
ae71e7b5 MR |
8996 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
8997 | || !i386_mpx_enabled ()) | |
118ca224 | 8998 | { |
6cb06a8c TT |
8999 | gdb_printf (_("Intel Memory Protection Extensions not " |
9000 | "supported on this target.\n")); | |
118ca224 PP |
9001 | return; |
9002 | } | |
29c1c244 WT |
9003 | |
9004 | if (args == NULL) | |
118ca224 | 9005 | { |
6cb06a8c | 9006 | gdb_printf (_("Address of pointer variable expected.\n")); |
118ca224 PP |
9007 | return; |
9008 | } | |
29c1c244 WT |
9009 | |
9010 | addr = parse_and_eval_address (args); | |
9011 | ||
9012 | bd_base = i386_mpx_bd_base (); | |
9013 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
9014 | ||
9015 | memset (bt_entry, 0, sizeof (bt_entry)); | |
9016 | ||
9017 | for (i = 0; i < 4; i++) | |
9018 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
df86565b | 9019 | + i * data_ptr_type->length (), |
29c1c244 WT |
9020 | data_ptr_type); |
9021 | ||
9022 | i386_mpx_print_bounds (bt_entry); | |
9023 | } | |
9024 | ||
9025 | /* Implement the command "set mpx bound". */ | |
9026 | ||
9027 | static void | |
c4a3e68e | 9028 | i386_mpx_set_bounds (const char *args, int from_tty) |
29c1c244 WT |
9029 | { |
9030 | CORE_ADDR bd_base = 0; | |
9031 | CORE_ADDR addr, lower, upper; | |
9032 | CORE_ADDR bt_entry_addr = 0; | |
9033 | CORE_ADDR bt_entry[2]; | |
9034 | const char *input = args; | |
9035 | int i; | |
9036 | struct gdbarch *gdbarch = get_current_arch (); | |
9037 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
9038 | struct type *data_ptr_type = builtin_type (gdbarch)->builtin_data_ptr; | |
9039 | ||
ae71e7b5 MR |
9040 | if (gdbarch_bfd_arch_info (gdbarch)->arch != bfd_arch_i386 |
9041 | || !i386_mpx_enabled ()) | |
bc504a31 | 9042 | error (_("Intel Memory Protection Extensions not supported\ |
29c1c244 WT |
9043 | on this target.")); |
9044 | ||
9045 | if (args == NULL) | |
9046 | error (_("Pointer value expected.")); | |
9047 | ||
9048 | addr = value_as_address (parse_to_comma_and_eval (&input)); | |
9049 | ||
9050 | if (input[0] == ',') | |
9051 | ++input; | |
9052 | if (input[0] == '\0') | |
9053 | error (_("wrong number of arguments: missing lower and upper bound.")); | |
9054 | lower = value_as_address (parse_to_comma_and_eval (&input)); | |
9055 | ||
9056 | if (input[0] == ',') | |
9057 | ++input; | |
9058 | if (input[0] == '\0') | |
9059 | error (_("Wrong number of arguments; Missing upper bound.")); | |
9060 | upper = value_as_address (parse_to_comma_and_eval (&input)); | |
9061 | ||
9062 | bd_base = i386_mpx_bd_base (); | |
9063 | bt_entry_addr = i386_mpx_get_bt_entry (addr, bd_base); | |
9064 | for (i = 0; i < 2; i++) | |
9065 | bt_entry[i] = read_memory_typed_address (bt_entry_addr | |
df86565b | 9066 | + i * data_ptr_type->length (), |
29c1c244 WT |
9067 | data_ptr_type); |
9068 | bt_entry[0] = (uint64_t) lower; | |
9069 | bt_entry[1] = ~(uint64_t) upper; | |
9070 | ||
9071 | for (i = 0; i < 2; i++) | |
132874d7 | 9072 | write_memory_unsigned_integer (bt_entry_addr |
df86565b SM |
9073 | + i * data_ptr_type->length (), |
9074 | data_ptr_type->length (), byte_order, | |
29c1c244 WT |
9075 | bt_entry[i]); |
9076 | } | |
9077 | ||
9078 | static struct cmd_list_element *mpx_set_cmdlist, *mpx_show_cmdlist; | |
9079 | ||
6c265988 | 9080 | void _initialize_i386_tdep (); |
c906108c | 9081 | void |
6c265988 | 9082 | _initialize_i386_tdep () |
c906108c | 9083 | { |
ec29a63c | 9084 | gdbarch_register (bfd_arch_i386, i386_gdbarch_init); |
a62cc96e | 9085 | |
fc338970 | 9086 | /* Add the variable that controls the disassembly flavor. */ |
7ab04401 AC |
9087 | add_setshow_enum_cmd ("disassembly-flavor", no_class, valid_flavors, |
9088 | &disassembly_flavor, _("\ | |
9089 | Set the disassembly flavor."), _("\ | |
9090 | Show the disassembly flavor."), _("\ | |
9091 | The valid values are \"att\" and \"intel\", and the default value is \"att\"."), | |
9092 | NULL, | |
9093 | NULL, /* FIXME: i18n: */ | |
9094 | &setlist, &showlist); | |
8201327c MK |
9095 | |
9096 | /* Add the variable that controls the convention for returning | |
9097 | structs. */ | |
7ab04401 AC |
9098 | add_setshow_enum_cmd ("struct-convention", no_class, valid_conventions, |
9099 | &struct_convention, _("\ | |
9100 | Set the convention for returning small structs."), _("\ | |
9101 | Show the convention for returning small structs."), _("\ | |
9102 | Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\ | |
9103 | is \"default\"."), | |
9104 | NULL, | |
9105 | NULL, /* FIXME: i18n: */ | |
9106 | &setlist, &showlist); | |
8201327c | 9107 | |
f54bdb6d | 9108 | /* Add "mpx" prefix for the set and show commands. */ |
29c1c244 | 9109 | |
f54bdb6d SM |
9110 | add_setshow_prefix_cmd |
9111 | ("mpx", class_support, | |
9112 | _("Set Intel Memory Protection Extensions specific variables."), | |
9113 | _("Show Intel Memory Protection Extensions specific variables."), | |
9114 | &mpx_set_cmdlist, &mpx_show_cmdlist, &setlist, &showlist); | |
29c1c244 WT |
9115 | |
9116 | /* Add "bound" command for the show mpx commands list. */ | |
9117 | ||
9118 | add_cmd ("bound", no_class, i386_mpx_info_bounds, | |
9119 | "Show the memory bounds for a given array/pointer storage\ | |
9120 | in the bound table.", | |
9121 | &mpx_show_cmdlist); | |
9122 | ||
9123 | /* Add "bound" command for the set mpx commands list. */ | |
9124 | ||
9125 | add_cmd ("bound", no_class, i386_mpx_set_bounds, | |
9126 | "Set the memory bounds for a given array/pointer storage\ | |
9127 | in the bound table.", | |
9128 | &mpx_set_cmdlist); | |
9129 | ||
05816f70 | 9130 | gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_SVR4, |
8201327c | 9131 | i386_svr4_init_abi); |
38c968cf | 9132 | |
209bd28e | 9133 | /* Initialize the i386-specific register groups. */ |
38c968cf | 9134 | i386_init_reggroups (); |
90884b2b | 9135 | |
c8d5aac9 L |
9136 | /* Tell remote stub that we support XML target description. */ |
9137 | register_remote_support_xml ("i386"); | |
c906108c | 9138 | } |