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Commit | Line | Data |
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c906108c | 1 | /* Intel 387 floating point stuff. |
38edeab8 | 2 | |
213516ef | 3 | Copyright (C) 1988-2023 Free Software Foundation, Inc. |
c906108c | 4 | |
c5aa993b | 5 | This file is part of GDB. |
c906108c | 6 | |
c5aa993b JM |
7 | This program is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
a9762ec7 | 9 | the Free Software Foundation; either version 3 of the License, or |
c5aa993b | 10 | (at your option) any later version. |
c906108c | 11 | |
c5aa993b JM |
12 | This program is distributed in the hope that it will be useful, |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
c906108c | 16 | |
c5aa993b | 17 | You should have received a copy of the GNU General Public License |
a9762ec7 | 18 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ |
c906108c SS |
19 | |
20 | #include "defs.h" | |
21 | #include "frame.h" | |
786a90bb | 22 | #include "gdbcore.h" |
c906108c SS |
23 | #include "inferior.h" |
24 | #include "language.h" | |
4e052eda | 25 | #include "regcache.h" |
f69fdf9b | 26 | #include "target-float.h" |
786a90bb MK |
27 | #include "value.h" |
28 | ||
9a82579f | 29 | #include "i386-tdep.h" |
42c466d7 | 30 | #include "i387-tdep.h" |
268a13a5 | 31 | #include "gdbsupport/x86-xstate.h" |
c906108c | 32 | |
de57eccd | 33 | /* Print the floating point number specified by RAW. */ |
786a90bb | 34 | |
de57eccd | 35 | static void |
27067745 UW |
36 | print_i387_value (struct gdbarch *gdbarch, |
37 | const gdb_byte *raw, struct ui_file *file) | |
de57eccd | 38 | { |
de57eccd JM |
39 | /* We try to print 19 digits. The last digit may or may not contain |
40 | garbage, but we'd better print one too many. We need enough room | |
41 | to print the value, 1 position for the sign, 1 for the decimal | |
42 | point, 19 for the digits and 6 for the exponent adds up to 27. */ | |
f69fdf9b UW |
43 | const struct type *type = i387_ext_type (gdbarch); |
44 | std::string str = target_float_to_string (raw, type, " %-+27.19g"); | |
6cb06a8c | 45 | gdb_printf (file, "%s", str.c_str ()); |
de57eccd JM |
46 | } |
47 | ||
48 | /* Print the classification for the register contents RAW. */ | |
786a90bb | 49 | |
de57eccd | 50 | static void |
27067745 UW |
51 | print_i387_ext (struct gdbarch *gdbarch, |
52 | const gdb_byte *raw, struct ui_file *file) | |
de57eccd JM |
53 | { |
54 | int sign; | |
55 | int integer; | |
56 | unsigned int exponent; | |
57 | unsigned long fraction[2]; | |
58 | ||
59 | sign = raw[9] & 0x80; | |
60 | integer = raw[7] & 0x80; | |
61 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); | |
62 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); | |
63 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) | |
64 | | (raw[5] << 8) | raw[4]); | |
65 | ||
66 | if (exponent == 0x7fff && integer) | |
67 | { | |
68 | if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000) | |
69 | /* Infinity. */ | |
6cb06a8c | 70 | gdb_printf (file, " %cInf", (sign ? '-' : '+')); |
de57eccd JM |
71 | else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000) |
72 | /* Real Indefinite (QNaN). */ | |
0426ad51 | 73 | gdb_puts (" Real Indefinite (QNaN)", file); |
de57eccd JM |
74 | else if (fraction[1] & 0x40000000) |
75 | /* QNaN. */ | |
0426ad51 | 76 | gdb_puts (" QNaN", file); |
de57eccd JM |
77 | else |
78 | /* SNaN. */ | |
0426ad51 | 79 | gdb_puts (" SNaN", file); |
de57eccd JM |
80 | } |
81 | else if (exponent < 0x7fff && exponent > 0x0000 && integer) | |
82 | /* Normal. */ | |
27067745 | 83 | print_i387_value (gdbarch, raw, file); |
de57eccd JM |
84 | else if (exponent == 0x0000) |
85 | { | |
86 | /* Denormal or zero. */ | |
27067745 | 87 | print_i387_value (gdbarch, raw, file); |
de57eccd JM |
88 | |
89 | if (integer) | |
90 | /* Pseudo-denormal. */ | |
0426ad51 | 91 | gdb_puts (" Pseudo-denormal", file); |
de57eccd JM |
92 | else if (fraction[0] || fraction[1]) |
93 | /* Denormal. */ | |
0426ad51 | 94 | gdb_puts (" Denormal", file); |
de57eccd JM |
95 | } |
96 | else | |
97 | /* Unsupported. */ | |
0426ad51 | 98 | gdb_puts (" Unsupported", file); |
de57eccd JM |
99 | } |
100 | ||
ad5f7d6e PA |
101 | /* Print the status word STATUS. If STATUS_P is false, then STATUS |
102 | was unavailable. */ | |
786a90bb | 103 | |
de57eccd | 104 | static void |
ad5f7d6e PA |
105 | print_i387_status_word (int status_p, |
106 | unsigned int status, struct ui_file *file) | |
de57eccd | 107 | { |
6cb06a8c | 108 | gdb_printf (file, "Status Word: "); |
ad5f7d6e PA |
109 | if (!status_p) |
110 | { | |
6cb06a8c | 111 | gdb_printf (file, "%s\n", _("<unavailable>")); |
ad5f7d6e PA |
112 | return; |
113 | } | |
114 | ||
6cb06a8c | 115 | gdb_printf (file, "%s", hex_string_custom (status, 4)); |
0426ad51 | 116 | gdb_puts (" ", file); |
6cb06a8c TT |
117 | gdb_printf (file, " %s", (status & 0x0001) ? "IE" : " "); |
118 | gdb_printf (file, " %s", (status & 0x0002) ? "DE" : " "); | |
119 | gdb_printf (file, " %s", (status & 0x0004) ? "ZE" : " "); | |
120 | gdb_printf (file, " %s", (status & 0x0008) ? "OE" : " "); | |
121 | gdb_printf (file, " %s", (status & 0x0010) ? "UE" : " "); | |
122 | gdb_printf (file, " %s", (status & 0x0020) ? "PE" : " "); | |
0426ad51 | 123 | gdb_puts (" ", file); |
6cb06a8c | 124 | gdb_printf (file, " %s", (status & 0x0080) ? "ES" : " "); |
0426ad51 | 125 | gdb_puts (" ", file); |
6cb06a8c | 126 | gdb_printf (file, " %s", (status & 0x0040) ? "SF" : " "); |
0426ad51 | 127 | gdb_puts (" ", file); |
6cb06a8c TT |
128 | gdb_printf (file, " %s", (status & 0x0100) ? "C0" : " "); |
129 | gdb_printf (file, " %s", (status & 0x0200) ? "C1" : " "); | |
130 | gdb_printf (file, " %s", (status & 0x0400) ? "C2" : " "); | |
131 | gdb_printf (file, " %s", (status & 0x4000) ? "C3" : " "); | |
61113f8b | 132 | |
0426ad51 | 133 | gdb_puts ("\n", file); |
61113f8b | 134 | |
6cb06a8c TT |
135 | gdb_printf (file, |
136 | " TOP: %d\n", ((status >> 11) & 7)); | |
de57eccd JM |
137 | } |
138 | ||
ad5f7d6e PA |
139 | /* Print the control word CONTROL. If CONTROL_P is false, then |
140 | CONTROL was unavailable. */ | |
786a90bb | 141 | |
de57eccd | 142 | static void |
ad5f7d6e PA |
143 | print_i387_control_word (int control_p, |
144 | unsigned int control, struct ui_file *file) | |
de57eccd | 145 | { |
6cb06a8c | 146 | gdb_printf (file, "Control Word: "); |
ad5f7d6e PA |
147 | if (!control_p) |
148 | { | |
6cb06a8c | 149 | gdb_printf (file, "%s\n", _("<unavailable>")); |
ad5f7d6e PA |
150 | return; |
151 | } | |
152 | ||
6cb06a8c | 153 | gdb_printf (file, "%s", hex_string_custom (control, 4)); |
0426ad51 | 154 | gdb_puts (" ", file); |
6cb06a8c TT |
155 | gdb_printf (file, " %s", (control & 0x0001) ? "IM" : " "); |
156 | gdb_printf (file, " %s", (control & 0x0002) ? "DM" : " "); | |
157 | gdb_printf (file, " %s", (control & 0x0004) ? "ZM" : " "); | |
158 | gdb_printf (file, " %s", (control & 0x0008) ? "OM" : " "); | |
159 | gdb_printf (file, " %s", (control & 0x0010) ? "UM" : " "); | |
160 | gdb_printf (file, " %s", (control & 0x0020) ? "PM" : " "); | |
de57eccd | 161 | |
0426ad51 | 162 | gdb_puts ("\n", file); |
de57eccd | 163 | |
0426ad51 | 164 | gdb_puts (" PC: ", file); |
de57eccd JM |
165 | switch ((control >> 8) & 3) |
166 | { | |
167 | case 0: | |
0426ad51 | 168 | gdb_puts ("Single Precision (24-bits)\n", file); |
de57eccd JM |
169 | break; |
170 | case 1: | |
0426ad51 | 171 | gdb_puts ("Reserved\n", file); |
de57eccd JM |
172 | break; |
173 | case 2: | |
0426ad51 | 174 | gdb_puts ("Double Precision (53-bits)\n", file); |
de57eccd JM |
175 | break; |
176 | case 3: | |
0426ad51 | 177 | gdb_puts ("Extended Precision (64-bits)\n", file); |
de57eccd JM |
178 | break; |
179 | } | |
180 | ||
0426ad51 | 181 | gdb_puts (" RC: ", file); |
de57eccd JM |
182 | switch ((control >> 10) & 3) |
183 | { | |
184 | case 0: | |
0426ad51 | 185 | gdb_puts ("Round to nearest\n", file); |
de57eccd JM |
186 | break; |
187 | case 1: | |
0426ad51 | 188 | gdb_puts ("Round down\n", file); |
de57eccd JM |
189 | break; |
190 | case 2: | |
0426ad51 | 191 | gdb_puts ("Round up\n", file); |
de57eccd JM |
192 | break; |
193 | case 3: | |
0426ad51 | 194 | gdb_puts ("Round toward zero\n", file); |
de57eccd JM |
195 | break; |
196 | } | |
197 | } | |
198 | ||
9b949a49 | 199 | /* Print out the i387 floating point state. Note that we ignore FRAME |
7d8d2918 MK |
200 | in the code below. That's OK since floating-point registers are |
201 | never saved on the stack. */ | |
202 | ||
de57eccd | 203 | void |
61113f8b | 204 | i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, |
bd2b40ac | 205 | frame_info_ptr frame, const char *args) |
de57eccd | 206 | { |
08106042 | 207 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
1d70089a | 208 | ULONGEST fctrl; |
ad5f7d6e | 209 | int fctrl_p; |
1d70089a | 210 | ULONGEST fstat; |
ad5f7d6e | 211 | int fstat_p; |
1d70089a | 212 | ULONGEST ftag; |
ad5f7d6e | 213 | int ftag_p; |
1d70089a | 214 | ULONGEST fiseg; |
ad5f7d6e | 215 | int fiseg_p; |
1d70089a | 216 | ULONGEST fioff; |
ad5f7d6e | 217 | int fioff_p; |
1d70089a | 218 | ULONGEST foseg; |
ad5f7d6e | 219 | int foseg_p; |
1d70089a | 220 | ULONGEST fooff; |
ad5f7d6e | 221 | int fooff_p; |
1d70089a | 222 | ULONGEST fop; |
ad5f7d6e | 223 | int fop_p; |
de57eccd JM |
224 | int fpreg; |
225 | int top; | |
226 | ||
5716833c MK |
227 | gdb_assert (gdbarch == get_frame_arch (frame)); |
228 | ||
ad5f7d6e PA |
229 | fctrl_p = read_frame_register_unsigned (frame, |
230 | I387_FCTRL_REGNUM (tdep), &fctrl); | |
231 | fstat_p = read_frame_register_unsigned (frame, | |
232 | I387_FSTAT_REGNUM (tdep), &fstat); | |
233 | ftag_p = read_frame_register_unsigned (frame, | |
234 | I387_FTAG_REGNUM (tdep), &ftag); | |
235 | fiseg_p = read_frame_register_unsigned (frame, | |
236 | I387_FISEG_REGNUM (tdep), &fiseg); | |
237 | fioff_p = read_frame_register_unsigned (frame, | |
238 | I387_FIOFF_REGNUM (tdep), &fioff); | |
239 | foseg_p = read_frame_register_unsigned (frame, | |
240 | I387_FOSEG_REGNUM (tdep), &foseg); | |
241 | fooff_p = read_frame_register_unsigned (frame, | |
242 | I387_FOOFF_REGNUM (tdep), &fooff); | |
243 | fop_p = read_frame_register_unsigned (frame, | |
244 | I387_FOP_REGNUM (tdep), &fop); | |
245 | ||
246 | if (fstat_p) | |
de57eccd | 247 | { |
ad5f7d6e | 248 | top = ((fstat >> 11) & 7); |
de57eccd | 249 | |
ad5f7d6e | 250 | for (fpreg = 7; fpreg >= 0; fpreg--) |
de57eccd | 251 | { |
ad5f7d6e PA |
252 | struct value *regval; |
253 | int regnum; | |
254 | int i; | |
255 | int tag = -1; | |
256 | ||
6cb06a8c | 257 | gdb_printf (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg); |
ad5f7d6e PA |
258 | |
259 | if (ftag_p) | |
260 | { | |
261 | tag = (ftag >> (fpreg * 2)) & 3; | |
262 | ||
263 | switch (tag) | |
264 | { | |
265 | case 0: | |
0426ad51 | 266 | gdb_puts ("Valid ", file); |
ad5f7d6e PA |
267 | break; |
268 | case 1: | |
0426ad51 | 269 | gdb_puts ("Zero ", file); |
ad5f7d6e PA |
270 | break; |
271 | case 2: | |
0426ad51 | 272 | gdb_puts ("Special ", file); |
ad5f7d6e PA |
273 | break; |
274 | case 3: | |
0426ad51 | 275 | gdb_puts ("Empty ", file); |
ad5f7d6e PA |
276 | break; |
277 | } | |
278 | } | |
279 | else | |
0426ad51 | 280 | gdb_puts ("Unknown ", file); |
ad5f7d6e PA |
281 | |
282 | regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep); | |
283 | regval = get_frame_register_value (frame, regnum); | |
284 | ||
d00664db | 285 | if (regval->entirely_available ()) |
ad5f7d6e | 286 | { |
efaf1ae0 | 287 | const gdb_byte *raw = regval->contents ().data (); |
ad5f7d6e | 288 | |
0426ad51 | 289 | gdb_puts ("0x", file); |
ad5f7d6e | 290 | for (i = 9; i >= 0; i--) |
6cb06a8c | 291 | gdb_printf (file, "%02x", raw[i]); |
ad5f7d6e PA |
292 | |
293 | if (tag != -1 && tag != 3) | |
294 | print_i387_ext (gdbarch, raw, file); | |
295 | } | |
296 | else | |
6cb06a8c | 297 | gdb_printf (file, "%s", _("<unavailable>")); |
ad5f7d6e | 298 | |
0426ad51 | 299 | gdb_puts ("\n", file); |
de57eccd | 300 | } |
de57eccd JM |
301 | } |
302 | ||
0426ad51 | 303 | gdb_puts ("\n", file); |
ad5f7d6e PA |
304 | print_i387_status_word (fstat_p, fstat, file); |
305 | print_i387_control_word (fctrl_p, fctrl, file); | |
6cb06a8c TT |
306 | gdb_printf (file, "Tag Word: %s\n", |
307 | ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>")); | |
308 | gdb_printf (file, "Instruction Pointer: %s:", | |
309 | fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>")); | |
310 | gdb_printf (file, "%s\n", | |
311 | fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>")); | |
312 | gdb_printf (file, "Operand Pointer: %s:", | |
313 | foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>")); | |
314 | gdb_printf (file, "%s\n", | |
315 | fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>")); | |
316 | gdb_printf (file, "Opcode: %s\n", | |
317 | fop_p | |
318 | ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4)) | |
319 | : _("<unavailable>")); | |
de57eccd | 320 | } |
d532c08f MK |
321 | \f |
322 | ||
83acabca DJ |
323 | /* Return nonzero if a value of type TYPE stored in register REGNUM |
324 | needs any special handling. */ | |
325 | ||
326 | int | |
1777feb0 MS |
327 | i387_convert_register_p (struct gdbarch *gdbarch, int regnum, |
328 | struct type *type) | |
83acabca | 329 | { |
20a6ec49 | 330 | if (i386_fp_regnum_p (gdbarch, regnum)) |
83acabca DJ |
331 | { |
332 | /* Floating point registers must be converted unless we are | |
8c8f9122 YQ |
333 | accessing them in their hardware type or TYPE is not float. */ |
334 | if (type == i387_ext_type (gdbarch) | |
78134374 | 335 | || type->code () != TYPE_CODE_FLT) |
83acabca DJ |
336 | return 0; |
337 | else | |
338 | return 1; | |
339 | } | |
340 | ||
341 | return 0; | |
342 | } | |
343 | ||
d532c08f MK |
344 | /* Read a value of type TYPE from register REGNUM in frame FRAME, and |
345 | return its contents in TO. */ | |
346 | ||
8dccd430 | 347 | int |
bd2b40ac | 348 | i387_register_to_value (frame_info_ptr frame, int regnum, |
8dccd430 PA |
349 | struct type *type, gdb_byte *to, |
350 | int *optimizedp, int *unavailablep) | |
d532c08f | 351 | { |
27067745 | 352 | struct gdbarch *gdbarch = get_frame_arch (frame); |
b4ad899f | 353 | gdb_byte from[I386_MAX_REGISTER_SIZE]; |
d532c08f | 354 | |
27067745 | 355 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
d532c08f MK |
356 | |
357 | /* We only support floating-point values. */ | |
78134374 | 358 | if (type->code () != TYPE_CODE_FLT) |
d532c08f | 359 | { |
8a3fe4f8 AC |
360 | warning (_("Cannot convert floating-point register value " |
361 | "to non-floating-point type.")); | |
8dccd430 PA |
362 | *optimizedp = *unavailablep = 0; |
363 | return 0; | |
d532c08f MK |
364 | } |
365 | ||
83acabca | 366 | /* Convert to TYPE. */ |
d8e07dda | 367 | if (!get_frame_register_bytes (frame, regnum, 0, |
bdec2917 LM |
368 | gdb::make_array_view (from, |
369 | register_size (gdbarch, | |
370 | regnum)), | |
371 | optimizedp, unavailablep)) | |
8dccd430 PA |
372 | return 0; |
373 | ||
3b2ca824 | 374 | target_float_convert (from, i387_ext_type (gdbarch), to, type); |
8dccd430 PA |
375 | *optimizedp = *unavailablep = 0; |
376 | return 1; | |
d532c08f MK |
377 | } |
378 | ||
379 | /* Write the contents FROM of a value of type TYPE into register | |
380 | REGNUM in frame FRAME. */ | |
381 | ||
382 | void | |
bd2b40ac | 383 | i387_value_to_register (frame_info_ptr frame, int regnum, |
42835c2b | 384 | struct type *type, const gdb_byte *from) |
d532c08f | 385 | { |
27067745 | 386 | struct gdbarch *gdbarch = get_frame_arch (frame); |
b4ad899f | 387 | gdb_byte to[I386_MAX_REGISTER_SIZE]; |
d532c08f | 388 | |
27067745 | 389 | gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); |
d532c08f MK |
390 | |
391 | /* We only support floating-point values. */ | |
78134374 | 392 | if (type->code () != TYPE_CODE_FLT) |
d532c08f | 393 | { |
8a3fe4f8 AC |
394 | warning (_("Cannot convert non-floating-point type " |
395 | "to floating-point register value.")); | |
d532c08f MK |
396 | return; |
397 | } | |
398 | ||
83acabca | 399 | /* Convert from TYPE. */ |
3b2ca824 | 400 | target_float_convert (from, type, to, i387_ext_type (gdbarch)); |
d532c08f MK |
401 | put_frame_register (frame, regnum, to); |
402 | } | |
403 | \f | |
e750d25e | 404 | |
786a90bb | 405 | /* Handle FSAVE and FXSAVE formats. */ |
e750d25e JT |
406 | |
407 | /* At fsave_offset[REGNUM] you'll find the offset to the location in | |
408 | the data structure used by the "fsave" instruction where GDB | |
409 | register REGNUM is stored. */ | |
410 | ||
411 | static int fsave_offset[] = | |
412 | { | |
5716833c MK |
413 | 28 + 0 * 10, /* %st(0) ... */ |
414 | 28 + 1 * 10, | |
415 | 28 + 2 * 10, | |
416 | 28 + 3 * 10, | |
417 | 28 + 4 * 10, | |
418 | 28 + 5 * 10, | |
419 | 28 + 6 * 10, | |
420 | 28 + 7 * 10, /* ... %st(7). */ | |
421 | 0, /* `fctrl' (16 bits). */ | |
422 | 4, /* `fstat' (16 bits). */ | |
423 | 8, /* `ftag' (16 bits). */ | |
424 | 16, /* `fiseg' (16 bits). */ | |
425 | 12, /* `fioff'. */ | |
426 | 24, /* `foseg' (16 bits). */ | |
427 | 20, /* `fooff'. */ | |
428 | 18 /* `fop' (bottom 11 bits). */ | |
e750d25e JT |
429 | }; |
430 | ||
20a6ec49 MD |
431 | #define FSAVE_ADDR(tdep, fsave, regnum) \ |
432 | (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)]) | |
e750d25e JT |
433 | \f |
434 | ||
41d041d6 MK |
435 | /* Fill register REGNUM in REGCACHE with the appropriate value from |
436 | *FSAVE. This function masks off any of the reserved bits in | |
437 | *FSAVE. */ | |
e750d25e JT |
438 | |
439 | void | |
41d041d6 | 440 | i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) |
e750d25e | 441 | { |
ac7936df | 442 | struct gdbarch *gdbarch = regcache->arch (); |
08106042 | 443 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
e17a4113 | 444 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
9a3c8263 | 445 | const gdb_byte *regs = (const gdb_byte *) fsave; |
e750d25e JT |
446 | int i; |
447 | ||
5716833c MK |
448 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
449 | ||
20a6ec49 | 450 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
ed504bdf MK |
451 | if (regnum == -1 || regnum == i) |
452 | { | |
453 | if (fsave == NULL) | |
454 | { | |
73e1c03f | 455 | regcache->raw_supply (i, NULL); |
5716833c | 456 | continue; |
ed504bdf MK |
457 | } |
458 | ||
459 | /* Most of the FPU control registers occupy only 16 bits in the | |
460 | fsave area. Give those a special treatment. */ | |
20a6ec49 MD |
461 | if (i >= I387_FCTRL_REGNUM (tdep) |
462 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
ed504bdf | 463 | { |
b4ad899f | 464 | gdb_byte val[4]; |
ed504bdf | 465 | |
20a6ec49 | 466 | memcpy (val, FSAVE_ADDR (tdep, regs, i), 2); |
ed504bdf | 467 | val[2] = val[3] = 0; |
20a6ec49 | 468 | if (i == I387_FOP_REGNUM (tdep)) |
ed504bdf | 469 | val[1] &= ((1 << 3) - 1); |
73e1c03f | 470 | regcache->raw_supply (i, val); |
ed504bdf MK |
471 | } |
472 | else | |
73e1c03f | 473 | regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i)); |
ed504bdf | 474 | } |
b87bc0d8 MK |
475 | |
476 | /* Provide dummy values for the SSE registers. */ | |
20a6ec49 | 477 | for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
b87bc0d8 | 478 | if (regnum == -1 || regnum == i) |
73e1c03f | 479 | regcache->raw_supply (i, NULL); |
20a6ec49 | 480 | if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep)) |
b87bc0d8 | 481 | { |
b4ad899f | 482 | gdb_byte buf[4]; |
b87bc0d8 | 483 | |
8ee22052 | 484 | store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); |
73e1c03f | 485 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); |
b87bc0d8 | 486 | } |
e750d25e JT |
487 | } |
488 | ||
489 | /* Fill register REGNUM (if it is a floating-point register) in *FSAVE | |
63b6c53f MK |
490 | with the value from REGCACHE. If REGNUM is -1, do this for all |
491 | registers. This function doesn't touch any of the reserved bits in | |
492 | *FSAVE. */ | |
e750d25e JT |
493 | |
494 | void | |
63b6c53f | 495 | i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) |
e750d25e | 496 | { |
345bd07c | 497 | gdbarch *arch = regcache->arch (); |
08106042 | 498 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
9a3c8263 | 499 | gdb_byte *regs = (gdb_byte *) fsave; |
e750d25e JT |
500 | int i; |
501 | ||
5716833c MK |
502 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
503 | ||
20a6ec49 | 504 | for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) |
e750d25e JT |
505 | if (regnum == -1 || regnum == i) |
506 | { | |
507 | /* Most of the FPU control registers occupy only 16 bits in | |
dda83cd7 | 508 | the fsave area. Give those a special treatment. */ |
20a6ec49 MD |
509 | if (i >= I387_FCTRL_REGNUM (tdep) |
510 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
e750d25e | 511 | { |
b4ad899f | 512 | gdb_byte buf[4]; |
e750d25e | 513 | |
34a79281 | 514 | regcache->raw_collect (i, buf); |
e750d25e | 515 | |
20a6ec49 | 516 | if (i == I387_FOP_REGNUM (tdep)) |
e750d25e JT |
517 | { |
518 | /* The opcode occupies only 11 bits. Make sure we | |
dda83cd7 | 519 | don't touch the other bits. */ |
e750d25e | 520 | buf[1] &= ((1 << 3) - 1); |
20a6ec49 | 521 | buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
e750d25e | 522 | } |
20a6ec49 | 523 | memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2); |
e750d25e JT |
524 | } |
525 | else | |
34a79281 | 526 | regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i)); |
e750d25e JT |
527 | } |
528 | } | |
529 | \f | |
530 | ||
531 | /* At fxsave_offset[REGNUM] you'll find the offset to the location in | |
532 | the data structure used by the "fxsave" instruction where GDB | |
533 | register REGNUM is stored. */ | |
534 | ||
535 | static int fxsave_offset[] = | |
536 | { | |
5716833c | 537 | 32, /* %st(0) through ... */ |
e750d25e JT |
538 | 48, |
539 | 64, | |
540 | 80, | |
541 | 96, | |
542 | 112, | |
543 | 128, | |
5716833c MK |
544 | 144, /* ... %st(7) (80 bits each). */ |
545 | 0, /* `fctrl' (16 bits). */ | |
546 | 2, /* `fstat' (16 bits). */ | |
547 | 4, /* `ftag' (16 bits). */ | |
548 | 12, /* `fiseg' (16 bits). */ | |
549 | 8, /* `fioff'. */ | |
550 | 20, /* `foseg' (16 bits). */ | |
551 | 16, /* `fooff'. */ | |
552 | 6, /* `fop' (bottom 11 bits). */ | |
553 | 160 + 0 * 16, /* %xmm0 through ... */ | |
04c8243f MK |
554 | 160 + 1 * 16, |
555 | 160 + 2 * 16, | |
556 | 160 + 3 * 16, | |
557 | 160 + 4 * 16, | |
558 | 160 + 5 * 16, | |
559 | 160 + 6 * 16, | |
560 | 160 + 7 * 16, | |
561 | 160 + 8 * 16, | |
562 | 160 + 9 * 16, | |
563 | 160 + 10 * 16, | |
564 | 160 + 11 * 16, | |
565 | 160 + 12 * 16, | |
566 | 160 + 13 * 16, | |
567 | 160 + 14 * 16, | |
5716833c | 568 | 160 + 15 * 16, /* ... %xmm15 (128 bits each). */ |
e750d25e JT |
569 | }; |
570 | ||
20a6ec49 MD |
571 | #define FXSAVE_ADDR(tdep, fxsave, regnum) \ |
572 | (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)]) | |
5716833c MK |
573 | |
574 | /* We made an unfortunate choice in putting %mxcsr after the SSE | |
575 | registers %xmm0-%xmm7 instead of before, since it makes supporting | |
576 | the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we | |
577 | don't include the offset for %mxcsr here above. */ | |
578 | ||
579 | #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24) | |
e750d25e | 580 | |
b4ad899f | 581 | static int i387_tag (const gdb_byte *raw); |
e750d25e JT |
582 | \f |
583 | ||
41d041d6 | 584 | /* Fill register REGNUM in REGCACHE with the appropriate |
ed504bdf MK |
585 | floating-point or SSE register value from *FXSAVE. This function |
586 | masks off any of the reserved bits in *FXSAVE. */ | |
e750d25e JT |
587 | |
588 | void | |
41d041d6 | 589 | i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) |
e750d25e | 590 | { |
345bd07c | 591 | gdbarch *arch = regcache->arch (); |
08106042 | 592 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
9a3c8263 | 593 | const gdb_byte *regs = (const gdb_byte *) fxsave; |
5716833c MK |
594 | int i; |
595 | ||
596 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
597 | gdb_assert (tdep->num_xmm_regs > 0); | |
dff95cc7 | 598 | |
20a6ec49 | 599 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
ed504bdf MK |
600 | if (regnum == -1 || regnum == i) |
601 | { | |
5716833c | 602 | if (regs == NULL) |
ed504bdf | 603 | { |
73e1c03f | 604 | regcache->raw_supply (i, NULL); |
ed504bdf MK |
605 | continue; |
606 | } | |
932bb524 | 607 | |
ed504bdf MK |
608 | /* Most of the FPU control registers occupy only 16 bits in |
609 | the fxsave area. Give those a special treatment. */ | |
20a6ec49 MD |
610 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
611 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
ed504bdf | 612 | { |
b4ad899f | 613 | gdb_byte val[4]; |
ed504bdf | 614 | |
20a6ec49 | 615 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); |
ed504bdf | 616 | val[2] = val[3] = 0; |
20a6ec49 | 617 | if (i == I387_FOP_REGNUM (tdep)) |
ed504bdf | 618 | val[1] &= ((1 << 3) - 1); |
20a6ec49 | 619 | else if (i== I387_FTAG_REGNUM (tdep)) |
ed504bdf MK |
620 | { |
621 | /* The fxsave area contains a simplified version of | |
622 | the tag word. We have to look at the actual 80-bit | |
623 | FP data to recreate the traditional i387 tag word. */ | |
624 | ||
625 | unsigned long ftag = 0; | |
626 | int fpreg; | |
627 | int top; | |
628 | ||
20a6ec49 MD |
629 | top = ((FXSAVE_ADDR (tdep, regs, |
630 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); | |
5716833c | 631 | top &= 0x7; |
ed504bdf MK |
632 | |
633 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
634 | { | |
635 | int tag; | |
636 | ||
637 | if (val[0] & (1 << fpreg)) | |
638 | { | |
6d5e094a | 639 | int thisreg = (fpreg + 8 - top) % 8 |
dda83cd7 | 640 | + I387_ST0_REGNUM (tdep); |
6d5e094a | 641 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); |
ed504bdf MK |
642 | } |
643 | else | |
644 | tag = 3; /* Empty */ | |
645 | ||
646 | ftag |= tag << (2 * fpreg); | |
647 | } | |
648 | val[0] = ftag & 0xff; | |
649 | val[1] = (ftag >> 8) & 0xff; | |
650 | } | |
73e1c03f | 651 | regcache->raw_supply (i, val); |
ed504bdf MK |
652 | } |
653 | else | |
73e1c03f | 654 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
ed504bdf | 655 | } |
5716833c | 656 | |
20a6ec49 | 657 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) |
5716833c MK |
658 | { |
659 | if (regs == NULL) | |
73e1c03f | 660 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL); |
5716833c | 661 | else |
73e1c03f | 662 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), |
5716833c MK |
663 | FXSAVE_MXCSR_ADDR (regs)); |
664 | } | |
e750d25e JT |
665 | } |
666 | ||
667 | /* Fill register REGNUM (if it is a floating-point or SSE register) in | |
80571bff MK |
668 | *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for |
669 | all registers. This function doesn't touch any of the reserved | |
670 | bits in *FXSAVE. */ | |
e750d25e JT |
671 | |
672 | void | |
80571bff | 673 | i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) |
e750d25e | 674 | { |
345bd07c | 675 | gdbarch *arch = regcache->arch (); |
08106042 | 676 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); |
9a3c8263 | 677 | gdb_byte *regs = (gdb_byte *) fxsave; |
5716833c MK |
678 | int i; |
679 | ||
680 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
681 | gdb_assert (tdep->num_xmm_regs > 0); | |
dff95cc7 | 682 | |
20a6ec49 | 683 | for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) |
e750d25e JT |
684 | if (regnum == -1 || regnum == i) |
685 | { | |
686 | /* Most of the FPU control registers occupy only 16 bits in | |
dda83cd7 | 687 | the fxsave area. Give those a special treatment. */ |
20a6ec49 MD |
688 | if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) |
689 | && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) | |
e750d25e | 690 | { |
b4ad899f | 691 | gdb_byte buf[4]; |
e750d25e | 692 | |
34a79281 | 693 | regcache->raw_collect (i, buf); |
e750d25e | 694 | |
31aeac78 L |
695 | if (i == I387_FOP_REGNUM (tdep)) |
696 | { | |
697 | /* The opcode occupies only 11 bits. Make sure we | |
dda83cd7 | 698 | don't touch the other bits. */ |
31aeac78 L |
699 | buf[1] &= ((1 << 3) - 1); |
700 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); | |
701 | } | |
702 | else if (i == I387_FTAG_REGNUM (tdep)) | |
703 | { | |
704 | /* Converting back is much easier. */ | |
705 | ||
706 | unsigned short ftag; | |
707 | int fpreg; | |
708 | ||
709 | ftag = (buf[1] << 8) | buf[0]; | |
710 | buf[0] = 0; | |
711 | buf[1] = 0; | |
712 | ||
713 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
714 | { | |
715 | int tag = (ftag >> (fpreg * 2)) & 3; | |
716 | ||
717 | if (tag != 3) | |
718 | buf[0] |= (1 << fpreg); | |
719 | } | |
720 | } | |
721 | memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); | |
722 | } | |
723 | else | |
34a79281 | 724 | regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i)); |
31aeac78 L |
725 | } |
726 | ||
727 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) | |
34a79281 | 728 | regcache->raw_collect (I387_MXCSR_REGNUM (tdep), |
31aeac78 L |
729 | FXSAVE_MXCSR_ADDR (regs)); |
730 | } | |
731 | ||
732 | /* `xstate_bv' is at byte offset 512. */ | |
733 | #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512) | |
734 | ||
8938f531 JB |
735 | /* At xsave_avxh_offset[REGNUM] you'll find the relative offset within |
736 | the AVX region of the XSAVE extended state where the upper 128bits | |
737 | of GDB register YMM0 + REGNUM is stored. */ | |
31aeac78 L |
738 | |
739 | static int xsave_avxh_offset[] = | |
740 | { | |
8938f531 JB |
741 | 0 * 16, /* Upper 128bit of %ymm0 through ... */ |
742 | 1 * 16, | |
743 | 2 * 16, | |
744 | 3 * 16, | |
745 | 4 * 16, | |
746 | 5 * 16, | |
747 | 6 * 16, | |
748 | 7 * 16, | |
749 | 8 * 16, | |
750 | 9 * 16, | |
751 | 10 * 16, | |
752 | 11 * 16, | |
753 | 12 * 16, | |
754 | 13 * 16, | |
755 | 14 * 16, | |
756 | 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ | |
31aeac78 L |
757 | }; |
758 | ||
8938f531 JB |
759 | #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ |
760 | (xsave + (tdep)->xsave_layout.avx_offset \ | |
761 | + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) | |
01f9f808 | 762 | |
8938f531 JB |
763 | /* At xsave_ymm_avx512_offset[REGNUM] you'll find the relative offset |
764 | within the ZMM region of the XSAVE extended state where the second | |
765 | 128bits of GDB register YMM16 + REGNUM is stored. */ | |
01f9f808 MS |
766 | |
767 | static int xsave_ymm_avx512_offset[] = | |
768 | { | |
8938f531 JB |
769 | 16 + 0 * 64, /* %ymm16 through... */ |
770 | 16 + 1 * 64, | |
771 | 16 + 2 * 64, | |
772 | 16 + 3 * 64, | |
773 | 16 + 4 * 64, | |
774 | 16 + 5 * 64, | |
775 | 16 + 6 * 64, | |
776 | 16 + 7 * 64, | |
777 | 16 + 8 * 64, | |
778 | 16 + 9 * 64, | |
779 | 16 + 10 * 64, | |
780 | 16 + 11 * 64, | |
781 | 16 + 12 * 64, | |
782 | 16 + 13 * 64, | |
783 | 16 + 14 * 64, | |
784 | 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ | |
01f9f808 MS |
785 | }; |
786 | ||
8938f531 JB |
787 | #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ |
788 | (xsave + (tdep)->xsave_layout.zmm_offset \ | |
789 | + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) | |
790 | ||
791 | /* At xsave_xmm_avx512_offset[REGNUM] you'll find the relative offset | |
792 | within the ZMM region of the XSAVE extended state where the first | |
793 | 128bits of GDB register XMM16 + REGNUM is stored. */ | |
01f9f808 MS |
794 | |
795 | static int xsave_xmm_avx512_offset[] = | |
1dbcd68c | 796 | { |
8938f531 JB |
797 | 0 * 64, /* %xmm16 through... */ |
798 | 1 * 64, | |
799 | 2 * 64, | |
800 | 3 * 64, | |
801 | 4 * 64, | |
802 | 5 * 64, | |
803 | 6 * 64, | |
804 | 7 * 64, | |
805 | 8 * 64, | |
806 | 9 * 64, | |
807 | 10 * 64, | |
808 | 11 * 64, | |
809 | 12 * 64, | |
810 | 13 * 64, | |
811 | 14 * 64, | |
812 | 15 * 64 /* ... %xmm31 (128 bits each). */ | |
01f9f808 MS |
813 | }; |
814 | ||
8938f531 JB |
815 | #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ |
816 | (xsave + (tdep)->xsave_layout.zmm_offset \ | |
817 | + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) | |
818 | ||
819 | /* At xsave_bndregs_offset[REGNUM] you'll find the relative offset | |
820 | within the BNDREGS region of the XSAVE extended state where the GDB | |
821 | register BND0R + REGNUM is stored. */ | |
01f9f808 | 822 | |
8938f531 JB |
823 | static int xsave_bndregs_offset[] = { |
824 | 0 * 16, /* bnd0r...bnd3r registers. */ | |
825 | 1 * 16, | |
826 | 2 * 16, | |
827 | 3 * 16 | |
1dbcd68c WT |
828 | }; |
829 | ||
8938f531 JB |
830 | #define XSAVE_BNDREGS_ADDR(tdep, xsave, regnum) \ |
831 | (xsave + (tdep)->xsave_layout.bndregs_offset \ | |
832 | + xsave_bndregs_offset[regnum - I387_BND0R_REGNUM (tdep)]) | |
833 | ||
834 | static int xsave_bndcfg_offset[] = { | |
835 | 0 * 8, /* bndcfg ... bndstatus. */ | |
836 | 1 * 8, | |
837 | }; | |
1dbcd68c | 838 | |
8938f531 JB |
839 | #define XSAVE_BNDCFG_ADDR(tdep, xsave, regnum) \ |
840 | (xsave + (tdep)->xsave_layout.bndcfg_offset \ | |
841 | + xsave_bndcfg_offset[regnum - I387_BNDCFGU_REGNUM (tdep)]) | |
842 | ||
843 | /* At xsave_avx512_k_offset[REGNUM] you'll find the relative offset | |
844 | within the K region of the XSAVE extended state where the AVX512 | |
845 | opmask register K0 + REGNUM is stored. */ | |
01f9f808 MS |
846 | |
847 | static int xsave_avx512_k_offset[] = | |
848 | { | |
8938f531 JB |
849 | 0 * 8, /* %k0 through... */ |
850 | 1 * 8, | |
851 | 2 * 8, | |
852 | 3 * 8, | |
853 | 4 * 8, | |
854 | 5 * 8, | |
855 | 6 * 8, | |
856 | 7 * 8 /* %k7 (64 bits each). */ | |
857 | }; | |
858 | ||
859 | #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ | |
860 | (xsave + (tdep)->xsave_layout.k_offset \ | |
861 | + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) | |
862 | ||
863 | ||
864 | /* At xsave_avx512_zmm0_h_offset[REGNUM] you find the relative offset | |
865 | within the ZMM_H region of the XSAVE extended state where the upper | |
866 | 256bits of the GDB register ZMM0 + REGNUM is stored. */ | |
867 | ||
868 | static int xsave_avx512_zmm0_h_offset[] = | |
869 | { | |
870 | 0 * 32, /* Upper 256bit of %zmmh0 through... */ | |
871 | 1 * 32, | |
872 | 2 * 32, | |
873 | 3 * 32, | |
874 | 4 * 32, | |
875 | 5 * 32, | |
876 | 6 * 32, | |
877 | 7 * 32, | |
878 | 8 * 32, | |
879 | 9 * 32, | |
880 | 10 * 32, | |
881 | 11 * 32, | |
882 | 12 * 32, | |
883 | 13 * 32, | |
884 | 14 * 32, | |
885 | 15 * 32 /* Upper 256bit of... %zmmh15 (256 bits each). */ | |
01f9f808 MS |
886 | }; |
887 | ||
8938f531 JB |
888 | #define XSAVE_AVX512_ZMM0_H_ADDR(tdep, xsave, regnum) \ |
889 | (xsave + (tdep)->xsave_layout.zmm_h_offset \ | |
890 | + xsave_avx512_zmm0_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) | |
01f9f808 | 891 | |
8938f531 JB |
892 | /* At xsave_avx512_zmm16_h_offset[REGNUM] you find the relative offset |
893 | within the ZMM_H region of the XSAVE extended state where the upper | |
894 | 256bits of the GDB register ZMM16 + REGNUM is stored. */ | |
01f9f808 | 895 | |
8938f531 | 896 | static int xsave_avx512_zmm16_h_offset[] = |
01f9f808 | 897 | { |
8938f531 JB |
898 | 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ |
899 | 32 + 1 * 64, | |
900 | 32 + 2 * 64, | |
901 | 32 + 3 * 64, | |
902 | 32 + 4 * 64, | |
903 | 32 + 5 * 64, | |
904 | 32 + 6 * 64, | |
905 | 32 + 7 * 64, | |
906 | 32 + 8 * 64, | |
907 | 32 + 9 * 64, | |
908 | 32 + 10 * 64, | |
909 | 32 + 11 * 64, | |
910 | 32 + 12 * 64, | |
911 | 32 + 13 * 64, | |
912 | 32 + 14 * 64, | |
913 | 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ | |
01f9f808 MS |
914 | }; |
915 | ||
8938f531 JB |
916 | #define XSAVE_AVX512_ZMM16_H_ADDR(tdep, xsave, regnum) \ |
917 | (xsave + (tdep)->xsave_layout.zmm_offset \ | |
918 | + xsave_avx512_zmm16_h_offset[regnum - I387_ZMM16H_REGNUM (tdep)]) | |
01f9f808 | 919 | |
8938f531 JB |
920 | /* At xsave_pkeys_offset[REGNUM] you'll find the relative offset |
921 | within the PKEYS region of the XSAVE extended state where the PKRU | |
922 | register is stored. */ | |
51547df6 MS |
923 | |
924 | static int xsave_pkeys_offset[] = | |
925 | { | |
8938f531 | 926 | 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by |
51547df6 MS |
927 | instructions and applications). */ |
928 | }; | |
929 | ||
8938f531 JB |
930 | #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ |
931 | (xsave + (tdep)->xsave_layout.pkru_offset \ | |
932 | + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) | |
51547df6 | 933 | |
8ee22052 | 934 | |
c689d1fe JB |
935 | /* See i387-tdep.h. */ |
936 | ||
937 | bool | |
938 | i387_guess_xsave_layout (uint64_t xcr0, size_t xsave_size, | |
939 | x86_xsave_layout &layout) | |
940 | { | |
941 | if (HAS_PKRU (xcr0) && xsave_size == 2696) | |
942 | { | |
943 | /* Intel CPUs supporting PKRU. */ | |
944 | layout.avx_offset = 576; | |
945 | layout.bndregs_offset = 960; | |
946 | layout.bndcfg_offset = 1024; | |
947 | layout.k_offset = 1088; | |
948 | layout.zmm_h_offset = 1152; | |
949 | layout.zmm_offset = 1664; | |
950 | layout.pkru_offset = 2688; | |
951 | } | |
952 | else if (HAS_PKRU (xcr0) && xsave_size == 2440) | |
953 | { | |
954 | /* AMD CPUs supporting PKRU. */ | |
955 | layout.avx_offset = 576; | |
956 | layout.k_offset = 832; | |
957 | layout.zmm_h_offset = 896; | |
958 | layout.zmm_offset = 1408; | |
959 | layout.pkru_offset = 2432; | |
960 | } | |
961 | else if (HAS_AVX512 (xcr0) && xsave_size == 2688) | |
962 | { | |
963 | /* Intel CPUs supporting AVX512. */ | |
964 | layout.avx_offset = 576; | |
965 | layout.bndregs_offset = 960; | |
966 | layout.bndcfg_offset = 1024; | |
967 | layout.k_offset = 1088; | |
968 | layout.zmm_h_offset = 1152; | |
969 | layout.zmm_offset = 1664; | |
970 | } | |
971 | else if (HAS_MPX (xcr0) && xsave_size == 1088) | |
972 | { | |
973 | /* Intel CPUs supporting MPX. */ | |
974 | layout.avx_offset = 576; | |
975 | layout.bndregs_offset = 960; | |
976 | layout.bndcfg_offset = 1024; | |
977 | } | |
978 | else if (HAS_AVX (xcr0) && xsave_size == 832) | |
979 | { | |
980 | /* Intel and AMD CPUs supporting AVX. */ | |
981 | layout.avx_offset = 576; | |
982 | } | |
983 | else | |
984 | return false; | |
985 | ||
986 | layout.sizeof_xsave = xsave_size; | |
987 | return true; | |
988 | } | |
989 | ||
8ee22052 AB |
990 | /* Extract from XSAVE a bitset of the features that are available on the |
991 | target, but which have not yet been enabled. */ | |
992 | ||
993 | ULONGEST | |
994 | i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave) | |
995 | { | |
996 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); | |
997 | const gdb_byte *regs = (const gdb_byte *) xsave; | |
08106042 | 998 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
8ee22052 AB |
999 | |
1000 | /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */ | |
1001 | ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), | |
1002 | 8, byte_order); | |
1003 | ||
1004 | /* Clear part in vector registers if its bit in xstat_bv is zero. */ | |
1005 | ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0; | |
1006 | ||
1007 | return clear_bv; | |
1008 | } | |
1009 | ||
31aeac78 L |
1010 | /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ |
1011 | ||
1012 | void | |
1013 | i387_supply_xsave (struct regcache *regcache, int regnum, | |
1014 | const void *xsave) | |
1015 | { | |
ac7936df | 1016 | struct gdbarch *gdbarch = regcache->arch (); |
8ee22052 | 1017 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
08106042 | 1018 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
9a3c8263 | 1019 | const gdb_byte *regs = (const gdb_byte *) xsave; |
31aeac78 | 1020 | int i; |
b5420128 JB |
1021 | /* In 64-bit mode the split between "low" and "high" ZMM registers is at |
1022 | ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all. | |
1023 | Precalculate the number to be used for the split point, with the all | |
1024 | registers in the "low" portion outside of 64-bit mode. */ | |
1025 | unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) | |
1026 | + std::min (tdep->num_zmm_regs, 16); | |
ff6527bb | 1027 | ULONGEST clear_bv; |
975c21ab | 1028 | static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 }; |
31aeac78 L |
1029 | enum |
1030 | { | |
1031 | none = 0x0, | |
1032 | x87 = 0x1, | |
1033 | sse = 0x2, | |
1034 | avxh = 0x4, | |
8938f531 JB |
1035 | bndregs = 0x8, |
1036 | bndcfg = 0x10, | |
1037 | avx512_k = 0x20, | |
1038 | avx512_zmm0_h = 0x40, | |
1039 | avx512_zmm16_h = 0x80, | |
1040 | avx512_ymmh_avx512 = 0x100, | |
1041 | avx512_xmm_avx512 = 0x200, | |
1042 | pkeys = 0x400, | |
1043 | all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h | |
1044 | | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys | |
31aeac78 L |
1045 | } regclass; |
1046 | ||
275418ae | 1047 | gdb_assert (regs != NULL); |
31aeac78 L |
1048 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); |
1049 | gdb_assert (tdep->num_xmm_regs > 0); | |
1050 | ||
1051 | if (regnum == -1) | |
1052 | regclass = all; | |
51547df6 MS |
1053 | else if (regnum >= I387_PKRU_REGNUM (tdep) |
1054 | && regnum < I387_PKEYSEND_REGNUM (tdep)) | |
1055 | regclass = pkeys; | |
01f9f808 | 1056 | else if (regnum >= I387_ZMM0H_REGNUM (tdep) |
8938f531 JB |
1057 | && regnum < I387_ZMM16H_REGNUM (tdep)) |
1058 | regclass = avx512_zmm0_h; | |
1059 | else if (regnum >= I387_ZMM16H_REGNUM (tdep) | |
01f9f808 | 1060 | && regnum < I387_ZMMENDH_REGNUM (tdep)) |
8938f531 | 1061 | regclass = avx512_zmm16_h; |
01f9f808 MS |
1062 | else if (regnum >= I387_K0_REGNUM (tdep) |
1063 | && regnum < I387_KEND_REGNUM (tdep)) | |
1064 | regclass = avx512_k; | |
1065 | else if (regnum >= I387_YMM16H_REGNUM (tdep) | |
1066 | && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) | |
1067 | regclass = avx512_ymmh_avx512; | |
1068 | else if (regnum >= I387_XMM16_REGNUM (tdep) | |
1069 | && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) | |
1070 | regclass = avx512_xmm_avx512; | |
31aeac78 L |
1071 | else if (regnum >= I387_YMM0H_REGNUM (tdep) |
1072 | && regnum < I387_YMMENDH_REGNUM (tdep)) | |
1073 | regclass = avxh; | |
1dbcd68c | 1074 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
8938f531 JB |
1075 | && regnum < I387_BNDCFGU_REGNUM (tdep)) |
1076 | regclass = bndregs; | |
1077 | else if (regnum >= I387_BNDCFGU_REGNUM (tdep) | |
1dbcd68c | 1078 | && regnum < I387_MPXEND_REGNUM (tdep)) |
8938f531 | 1079 | regclass = bndcfg; |
01f9f808 | 1080 | else if (regnum >= I387_XMM0_REGNUM (tdep) |
31aeac78 L |
1081 | && regnum < I387_MXCSR_REGNUM (tdep)) |
1082 | regclass = sse; | |
1083 | else if (regnum >= I387_ST0_REGNUM (tdep) | |
1084 | && regnum < I387_FCTRL_REGNUM (tdep)) | |
1085 | regclass = x87; | |
1086 | else | |
1087 | regclass = none; | |
1088 | ||
8ee22052 | 1089 | clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); |
31aeac78 | 1090 | |
b4d36fb8 PA |
1091 | /* With the delayed xsave mechanism, in between the program |
1092 | starting, and the program accessing the vector registers for the | |
1093 | first time, the register's values are invalid. The kernel | |
1094 | initializes register states to zero when they are set the first | |
1095 | time in a program. This means that from the user-space programs' | |
1096 | perspective, it's the same as if the registers have always been | |
1097 | zero from the start of the program. Therefore, the debugger | |
275418ae | 1098 | should provide the same illusion to the user. */ |
b4d36fb8 | 1099 | |
31aeac78 L |
1100 | switch (regclass) |
1101 | { | |
1102 | case none: | |
1103 | break; | |
1104 | ||
51547df6 MS |
1105 | case pkeys: |
1106 | if ((clear_bv & X86_XSTATE_PKRU)) | |
73e1c03f | 1107 | regcache->raw_supply (regnum, zero); |
51547df6 | 1108 | else |
73e1c03f | 1109 | regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum)); |
51547df6 MS |
1110 | return; |
1111 | ||
8938f531 JB |
1112 | case avx512_zmm0_h: |
1113 | if ((clear_bv & X86_XSTATE_ZMM_H)) | |
1114 | regcache->raw_supply (regnum, zero); | |
1115 | else | |
1116 | regcache->raw_supply (regnum, | |
1117 | XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum)); | |
1118 | return; | |
1119 | ||
1120 | case avx512_zmm16_h: | |
1121 | if ((clear_bv & X86_XSTATE_ZMM)) | |
73e1c03f | 1122 | regcache->raw_supply (regnum, zero); |
01f9f808 | 1123 | else |
73e1c03f | 1124 | regcache->raw_supply (regnum, |
8938f531 | 1125 | XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum)); |
01f9f808 MS |
1126 | return; |
1127 | ||
1128 | case avx512_k: | |
df7e5265 | 1129 | if ((clear_bv & X86_XSTATE_K)) |
73e1c03f | 1130 | regcache->raw_supply (regnum, zero); |
01f9f808 | 1131 | else |
73e1c03f | 1132 | regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum)); |
01f9f808 MS |
1133 | return; |
1134 | ||
1135 | case avx512_ymmh_avx512: | |
df7e5265 | 1136 | if ((clear_bv & X86_XSTATE_ZMM)) |
73e1c03f | 1137 | regcache->raw_supply (regnum, zero); |
01f9f808 | 1138 | else |
73e1c03f SM |
1139 | regcache->raw_supply (regnum, |
1140 | XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum)); | |
01f9f808 MS |
1141 | return; |
1142 | ||
1143 | case avx512_xmm_avx512: | |
df7e5265 | 1144 | if ((clear_bv & X86_XSTATE_ZMM)) |
73e1c03f | 1145 | regcache->raw_supply (regnum, zero); |
01f9f808 | 1146 | else |
73e1c03f SM |
1147 | regcache->raw_supply (regnum, |
1148 | XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum)); | |
01f9f808 MS |
1149 | return; |
1150 | ||
31aeac78 | 1151 | case avxh: |
df7e5265 | 1152 | if ((clear_bv & X86_XSTATE_AVX)) |
73e1c03f | 1153 | regcache->raw_supply (regnum, zero); |
31aeac78 | 1154 | else |
73e1c03f | 1155 | regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum)); |
31aeac78 L |
1156 | return; |
1157 | ||
8938f531 JB |
1158 | case bndcfg: |
1159 | if ((clear_bv & X86_XSTATE_BNDCFG)) | |
1160 | regcache->raw_supply (regnum, zero); | |
1161 | else | |
1162 | regcache->raw_supply (regnum, XSAVE_BNDCFG_ADDR (tdep, regs, regnum)); | |
1163 | return; | |
1164 | ||
1165 | case bndregs: | |
df7e5265 | 1166 | if ((clear_bv & X86_XSTATE_BNDREGS)) |
73e1c03f | 1167 | regcache->raw_supply (regnum, zero); |
1dbcd68c | 1168 | else |
8938f531 | 1169 | regcache->raw_supply (regnum, XSAVE_BNDREGS_ADDR (tdep, regs, regnum)); |
1dbcd68c WT |
1170 | return; |
1171 | ||
31aeac78 | 1172 | case sse: |
df7e5265 | 1173 | if ((clear_bv & X86_XSTATE_SSE)) |
73e1c03f | 1174 | regcache->raw_supply (regnum, zero); |
31aeac78 | 1175 | else |
73e1c03f | 1176 | regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); |
31aeac78 L |
1177 | return; |
1178 | ||
1179 | case x87: | |
df7e5265 | 1180 | if ((clear_bv & X86_XSTATE_X87)) |
73e1c03f | 1181 | regcache->raw_supply (regnum, zero); |
31aeac78 | 1182 | else |
73e1c03f | 1183 | regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); |
31aeac78 L |
1184 | return; |
1185 | ||
1186 | case all: | |
51547df6 MS |
1187 | /* Handle PKEYS registers. */ |
1188 | if ((tdep->xcr0 & X86_XSTATE_PKRU)) | |
1189 | { | |
1190 | if ((clear_bv & X86_XSTATE_PKRU)) | |
1191 | { | |
1192 | for (i = I387_PKRU_REGNUM (tdep); | |
1193 | i < I387_PKEYSEND_REGNUM (tdep); | |
1194 | i++) | |
73e1c03f | 1195 | regcache->raw_supply (i, zero); |
51547df6 MS |
1196 | } |
1197 | else | |
1198 | { | |
1199 | for (i = I387_PKRU_REGNUM (tdep); | |
1200 | i < I387_PKEYSEND_REGNUM (tdep); | |
1201 | i++) | |
73e1c03f | 1202 | regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i)); |
51547df6 MS |
1203 | } |
1204 | } | |
1205 | ||
b5420128 JB |
1206 | /* Handle the upper halves of the low 8/16 ZMM registers. */ |
1207 | if ((tdep->xcr0 & X86_XSTATE_ZMM_H)) | |
01f9f808 | 1208 | { |
b5420128 | 1209 | if ((clear_bv & X86_XSTATE_ZMM_H)) |
01f9f808 | 1210 | { |
b5420128 | 1211 | for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) |
73e1c03f | 1212 | regcache->raw_supply (i, zero); |
01f9f808 MS |
1213 | } |
1214 | else | |
1215 | { | |
b5420128 | 1216 | for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) |
73e1c03f | 1217 | regcache->raw_supply (i, |
8938f531 | 1218 | XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i)); |
01f9f808 MS |
1219 | } |
1220 | } | |
1221 | ||
1222 | /* Handle AVX512 OpMask registers. */ | |
df7e5265 | 1223 | if ((tdep->xcr0 & X86_XSTATE_K)) |
01f9f808 | 1224 | { |
df7e5265 | 1225 | if ((clear_bv & X86_XSTATE_K)) |
01f9f808 MS |
1226 | { |
1227 | for (i = I387_K0_REGNUM (tdep); | |
1228 | i < I387_KEND_REGNUM (tdep); | |
1229 | i++) | |
73e1c03f | 1230 | regcache->raw_supply (i, zero); |
01f9f808 MS |
1231 | } |
1232 | else | |
1233 | { | |
1234 | for (i = I387_K0_REGNUM (tdep); | |
1235 | i < I387_KEND_REGNUM (tdep); | |
1236 | i++) | |
73e1c03f | 1237 | regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i)); |
01f9f808 MS |
1238 | } |
1239 | } | |
1240 | ||
b5420128 | 1241 | /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */ |
df7e5265 | 1242 | if ((tdep->xcr0 & X86_XSTATE_ZMM)) |
01f9f808 | 1243 | { |
df7e5265 | 1244 | if ((clear_bv & X86_XSTATE_ZMM)) |
01f9f808 | 1245 | { |
8938f531 JB |
1246 | for (i = I387_ZMM16H_REGNUM (tdep); |
1247 | i < I387_ZMMENDH_REGNUM (tdep); i++) | |
b5420128 | 1248 | regcache->raw_supply (i, zero); |
01f9f808 MS |
1249 | for (i = I387_YMM16H_REGNUM (tdep); |
1250 | i < I387_YMMH_AVX512_END_REGNUM (tdep); | |
1251 | i++) | |
73e1c03f | 1252 | regcache->raw_supply (i, zero); |
01f9f808 MS |
1253 | for (i = I387_XMM16_REGNUM (tdep); |
1254 | i < I387_XMM_AVX512_END_REGNUM (tdep); | |
1255 | i++) | |
73e1c03f | 1256 | regcache->raw_supply (i, zero); |
01f9f808 MS |
1257 | } |
1258 | else | |
1259 | { | |
8938f531 JB |
1260 | for (i = I387_ZMM16H_REGNUM (tdep); |
1261 | i < I387_ZMMENDH_REGNUM (tdep); i++) | |
b5420128 | 1262 | regcache->raw_supply (i, |
8938f531 | 1263 | XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i)); |
01f9f808 MS |
1264 | for (i = I387_YMM16H_REGNUM (tdep); |
1265 | i < I387_YMMH_AVX512_END_REGNUM (tdep); | |
1266 | i++) | |
73e1c03f | 1267 | regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i)); |
01f9f808 MS |
1268 | for (i = I387_XMM16_REGNUM (tdep); |
1269 | i < I387_XMM_AVX512_END_REGNUM (tdep); | |
1270 | i++) | |
73e1c03f | 1271 | regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i)); |
01f9f808 MS |
1272 | } |
1273 | } | |
86d31898 | 1274 | /* Handle the upper YMM registers. */ |
df7e5265 | 1275 | if ((tdep->xcr0 & X86_XSTATE_AVX)) |
31aeac78 | 1276 | { |
df7e5265 | 1277 | if ((clear_bv & X86_XSTATE_AVX)) |
b4d36fb8 PA |
1278 | { |
1279 | for (i = I387_YMM0H_REGNUM (tdep); | |
1280 | i < I387_YMMENDH_REGNUM (tdep); | |
1281 | i++) | |
73e1c03f | 1282 | regcache->raw_supply (i, zero); |
b4d36fb8 | 1283 | } |
31aeac78 | 1284 | else |
31aeac78 | 1285 | { |
b4d36fb8 PA |
1286 | for (i = I387_YMM0H_REGNUM (tdep); |
1287 | i < I387_YMMENDH_REGNUM (tdep); | |
1288 | i++) | |
73e1c03f | 1289 | regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i)); |
31aeac78 L |
1290 | } |
1291 | } | |
1292 | ||
1dbcd68c | 1293 | /* Handle the MPX registers. */ |
df7e5265 | 1294 | if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) |
1dbcd68c | 1295 | { |
df7e5265 | 1296 | if (clear_bv & X86_XSTATE_BNDREGS) |
1dbcd68c WT |
1297 | { |
1298 | for (i = I387_BND0R_REGNUM (tdep); | |
1299 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
73e1c03f | 1300 | regcache->raw_supply (i, zero); |
1dbcd68c WT |
1301 | } |
1302 | else | |
1303 | { | |
1304 | for (i = I387_BND0R_REGNUM (tdep); | |
1305 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
8938f531 | 1306 | regcache->raw_supply (i, XSAVE_BNDREGS_ADDR (tdep, regs, i)); |
1dbcd68c WT |
1307 | } |
1308 | } | |
1309 | ||
1310 | /* Handle the MPX registers. */ | |
df7e5265 | 1311 | if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) |
1dbcd68c | 1312 | { |
df7e5265 | 1313 | if (clear_bv & X86_XSTATE_BNDCFG) |
1dbcd68c WT |
1314 | { |
1315 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1316 | i < I387_MPXEND_REGNUM (tdep); i++) | |
73e1c03f | 1317 | regcache->raw_supply (i, zero); |
1dbcd68c WT |
1318 | } |
1319 | else | |
1320 | { | |
1321 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1322 | i < I387_MPXEND_REGNUM (tdep); i++) | |
8938f531 | 1323 | regcache->raw_supply (i, XSAVE_BNDCFG_ADDR (tdep, regs, i)); |
1dbcd68c WT |
1324 | } |
1325 | } | |
1326 | ||
31aeac78 | 1327 | /* Handle the XMM registers. */ |
df7e5265 | 1328 | if ((tdep->xcr0 & X86_XSTATE_SSE)) |
31aeac78 | 1329 | { |
df7e5265 | 1330 | if ((clear_bv & X86_XSTATE_SSE)) |
b4d36fb8 PA |
1331 | { |
1332 | for (i = I387_XMM0_REGNUM (tdep); | |
1333 | i < I387_MXCSR_REGNUM (tdep); | |
1334 | i++) | |
73e1c03f | 1335 | regcache->raw_supply (i, zero); |
b4d36fb8 | 1336 | } |
31aeac78 | 1337 | else |
31aeac78 | 1338 | { |
b4d36fb8 PA |
1339 | for (i = I387_XMM0_REGNUM (tdep); |
1340 | i < I387_MXCSR_REGNUM (tdep); i++) | |
73e1c03f | 1341 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
31aeac78 L |
1342 | } |
1343 | } | |
1344 | ||
1345 | /* Handle the x87 registers. */ | |
df7e5265 | 1346 | if ((tdep->xcr0 & X86_XSTATE_X87)) |
31aeac78 | 1347 | { |
df7e5265 | 1348 | if ((clear_bv & X86_XSTATE_X87)) |
b4d36fb8 PA |
1349 | { |
1350 | for (i = I387_ST0_REGNUM (tdep); | |
1351 | i < I387_FCTRL_REGNUM (tdep); | |
1352 | i++) | |
73e1c03f | 1353 | regcache->raw_supply (i, zero); |
b4d36fb8 | 1354 | } |
31aeac78 | 1355 | else |
31aeac78 | 1356 | { |
b4d36fb8 PA |
1357 | for (i = I387_ST0_REGNUM (tdep); |
1358 | i < I387_FCTRL_REGNUM (tdep); | |
1359 | i++) | |
73e1c03f | 1360 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
31aeac78 L |
1361 | } |
1362 | } | |
1363 | break; | |
1364 | } | |
1365 | ||
1366 | /* Only handle x87 control registers. */ | |
1367 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) | |
1368 | if (regnum == -1 || regnum == i) | |
1369 | { | |
8ee22052 AB |
1370 | if (clear_bv & X86_XSTATE_X87) |
1371 | { | |
1372 | if (i == I387_FCTRL_REGNUM (tdep)) | |
1373 | { | |
1374 | gdb_byte buf[4]; | |
1375 | ||
1376 | store_unsigned_integer (buf, 4, byte_order, | |
1377 | I387_FCTRL_INIT_VAL); | |
73e1c03f | 1378 | regcache->raw_supply (i, buf); |
8ee22052 AB |
1379 | } |
1380 | else if (i == I387_FTAG_REGNUM (tdep)) | |
1381 | { | |
1382 | gdb_byte buf[4]; | |
1383 | ||
1384 | store_unsigned_integer (buf, 4, byte_order, 0xffff); | |
73e1c03f | 1385 | regcache->raw_supply (i, buf); |
8ee22052 AB |
1386 | } |
1387 | else | |
73e1c03f | 1388 | regcache->raw_supply (i, zero); |
8ee22052 | 1389 | } |
31aeac78 L |
1390 | /* Most of the FPU control registers occupy only 16 bits in |
1391 | the xsave extended state. Give those a special treatment. */ | |
8ee22052 AB |
1392 | else if (i != I387_FIOFF_REGNUM (tdep) |
1393 | && i != I387_FOOFF_REGNUM (tdep)) | |
31aeac78 L |
1394 | { |
1395 | gdb_byte val[4]; | |
1396 | ||
1397 | memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); | |
1398 | val[2] = val[3] = 0; | |
1399 | if (i == I387_FOP_REGNUM (tdep)) | |
1400 | val[1] &= ((1 << 3) - 1); | |
8ee22052 | 1401 | else if (i == I387_FTAG_REGNUM (tdep)) |
31aeac78 L |
1402 | { |
1403 | /* The fxsave area contains a simplified version of | |
1404 | the tag word. We have to look at the actual 80-bit | |
1405 | FP data to recreate the traditional i387 tag word. */ | |
1406 | ||
1407 | unsigned long ftag = 0; | |
1408 | int fpreg; | |
1409 | int top; | |
1410 | ||
1411 | top = ((FXSAVE_ADDR (tdep, regs, | |
1412 | I387_FSTAT_REGNUM (tdep)))[1] >> 3); | |
1413 | top &= 0x7; | |
1414 | ||
1415 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
1416 | { | |
1417 | int tag; | |
1418 | ||
1419 | if (val[0] & (1 << fpreg)) | |
1420 | { | |
e5b3d7d6 | 1421 | int thisreg = (fpreg + 8 - top) % 8 |
31aeac78 | 1422 | + I387_ST0_REGNUM (tdep); |
e5b3d7d6 | 1423 | tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); |
31aeac78 L |
1424 | } |
1425 | else | |
1426 | tag = 3; /* Empty */ | |
1427 | ||
1428 | ftag |= tag << (2 * fpreg); | |
1429 | } | |
1430 | val[0] = ftag & 0xff; | |
1431 | val[1] = (ftag >> 8) & 0xff; | |
1432 | } | |
73e1c03f | 1433 | regcache->raw_supply (i, val); |
31aeac78 | 1434 | } |
8ee22052 | 1435 | else |
73e1c03f | 1436 | regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); |
31aeac78 L |
1437 | } |
1438 | ||
1439 | if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) | |
8ee22052 AB |
1440 | { |
1441 | /* The MXCSR register is placed into the xsave buffer if either the | |
1442 | AVX or SSE features are enabled. */ | |
1443 | if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) | |
1444 | == (X86_XSTATE_AVX | X86_XSTATE_SSE)) | |
1445 | { | |
1446 | gdb_byte buf[4]; | |
1447 | ||
1448 | store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); | |
73e1c03f | 1449 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); |
8ee22052 AB |
1450 | } |
1451 | else | |
73e1c03f SM |
1452 | regcache->raw_supply (I387_MXCSR_REGNUM (tdep), |
1453 | FXSAVE_MXCSR_ADDR (regs)); | |
8ee22052 | 1454 | } |
31aeac78 L |
1455 | } |
1456 | ||
1457 | /* Similar to i387_collect_fxsave, but use XSAVE extended state. */ | |
1458 | ||
1459 | void | |
1460 | i387_collect_xsave (const struct regcache *regcache, int regnum, | |
1461 | void *xsave, int gcore) | |
1462 | { | |
ac7936df | 1463 | struct gdbarch *gdbarch = regcache->arch (); |
8ee22052 | 1464 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
08106042 | 1465 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
8ee22052 AB |
1466 | gdb_byte *p, *regs = (gdb_byte *) xsave; |
1467 | gdb_byte raw[I386_MAX_REGISTER_SIZE]; | |
1468 | ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0; | |
35f1fea3 | 1469 | unsigned int i; |
b5420128 JB |
1470 | /* See the comment in i387_supply_xsave(). */ |
1471 | unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) | |
1472 | + std::min (tdep->num_zmm_regs, 16); | |
31aeac78 L |
1473 | enum |
1474 | { | |
8ee22052 AB |
1475 | x87_ctrl_or_mxcsr = 0x1, |
1476 | x87 = 0x2, | |
1477 | sse = 0x4, | |
1478 | avxh = 0x8, | |
8938f531 JB |
1479 | bndregs = 0x10, |
1480 | bndcfg = 0x20, | |
1481 | avx512_k = 0x40, | |
1482 | avx512_zmm0_h = 0x80, | |
1483 | avx512_zmm16_h = 0x100, | |
1484 | avx512_ymmh_avx512 = 0x200, | |
1485 | avx512_xmm_avx512 = 0x400, | |
1486 | pkeys = 0x800, | |
1487 | all = x87 | sse | avxh | bndregs | bndcfg | avx512_k | avx512_zmm0_h | |
1488 | | avx512_zmm16_h | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys | |
31aeac78 L |
1489 | } regclass; |
1490 | ||
1491 | gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); | |
1492 | gdb_assert (tdep->num_xmm_regs > 0); | |
1493 | ||
1494 | if (regnum == -1) | |
1495 | regclass = all; | |
51547df6 MS |
1496 | else if (regnum >= I387_PKRU_REGNUM (tdep) |
1497 | && regnum < I387_PKEYSEND_REGNUM (tdep)) | |
1498 | regclass = pkeys; | |
01f9f808 | 1499 | else if (regnum >= I387_ZMM0H_REGNUM (tdep) |
8938f531 JB |
1500 | && regnum < I387_ZMM16H_REGNUM (tdep)) |
1501 | regclass = avx512_zmm0_h; | |
1502 | else if (regnum >= I387_ZMM16H_REGNUM (tdep) | |
01f9f808 | 1503 | && regnum < I387_ZMMENDH_REGNUM (tdep)) |
8938f531 | 1504 | regclass = avx512_zmm16_h; |
01f9f808 MS |
1505 | else if (regnum >= I387_K0_REGNUM (tdep) |
1506 | && regnum < I387_KEND_REGNUM (tdep)) | |
1507 | regclass = avx512_k; | |
1508 | else if (regnum >= I387_YMM16H_REGNUM (tdep) | |
1509 | && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) | |
1510 | regclass = avx512_ymmh_avx512; | |
1511 | else if (regnum >= I387_XMM16_REGNUM (tdep) | |
1512 | && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) | |
1513 | regclass = avx512_xmm_avx512; | |
31aeac78 L |
1514 | else if (regnum >= I387_YMM0H_REGNUM (tdep) |
1515 | && regnum < I387_YMMENDH_REGNUM (tdep)) | |
1516 | regclass = avxh; | |
1dbcd68c | 1517 | else if (regnum >= I387_BND0R_REGNUM (tdep) |
8938f531 JB |
1518 | && regnum < I387_BNDCFGU_REGNUM (tdep)) |
1519 | regclass = bndregs; | |
1520 | else if (regnum >= I387_BNDCFGU_REGNUM (tdep) | |
1dbcd68c | 1521 | && regnum < I387_MPXEND_REGNUM (tdep)) |
8938f531 | 1522 | regclass = bndcfg; |
1dbcd68c | 1523 | else if (regnum >= I387_XMM0_REGNUM (tdep) |
31aeac78 L |
1524 | && regnum < I387_MXCSR_REGNUM (tdep)) |
1525 | regclass = sse; | |
1526 | else if (regnum >= I387_ST0_REGNUM (tdep) | |
1527 | && regnum < I387_FCTRL_REGNUM (tdep)) | |
1528 | regclass = x87; | |
8ee22052 AB |
1529 | else if ((regnum >= I387_FCTRL_REGNUM (tdep) |
1530 | && regnum < I387_XMM0_REGNUM (tdep)) | |
1531 | || regnum == I387_MXCSR_REGNUM (tdep)) | |
1532 | regclass = x87_ctrl_or_mxcsr; | |
31aeac78 | 1533 | else |
f34652de | 1534 | internal_error (_("invalid i387 regnum %d"), regnum); |
31aeac78 L |
1535 | |
1536 | if (gcore) | |
1537 | { | |
1538 | /* Clear XSAVE extended state. */ | |
8938f531 | 1539 | memset (regs, 0, tdep->xsave_layout.sizeof_xsave); |
31aeac78 L |
1540 | |
1541 | /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ | |
1542 | if (tdep->xsave_xcr0_offset != -1) | |
1543 | memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8); | |
1544 | memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8); | |
1545 | } | |
1546 | ||
8ee22052 AB |
1547 | /* The supported bits in `xstat_bv' are 8 bytes. */ |
1548 | initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), | |
1549 | 8, byte_order); | |
1550 | clear_bv = (~(initial_xstate_bv)) & tdep->xcr0; | |
1551 | ||
1552 | /* The XSAVE buffer was filled lazily by the kernel. Only those | |
1553 | features that are enabled were written into the buffer, disabled | |
1554 | features left the buffer uninitialised. In order to identify if any | |
1555 | registers have changed we will be comparing the register cache | |
1556 | version to the version in the XSAVE buffer, it is important then that | |
1557 | at this point we initialise to the default values any features in | |
1558 | XSAVE that are not yet initialised. | |
1559 | ||
1560 | This could be made more efficient, we know which features (from | |
1561 | REGNUM) we will be potentially updating, and could limit ourselves to | |
1562 | only clearing that feature. However, the extra complexity does not | |
1563 | seem justified at this point. */ | |
1564 | if (clear_bv) | |
31aeac78 | 1565 | { |
8ee22052 AB |
1566 | if ((clear_bv & X86_XSTATE_PKRU)) |
1567 | for (i = I387_PKRU_REGNUM (tdep); | |
1568 | i < I387_PKEYSEND_REGNUM (tdep); i++) | |
1569 | memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4); | |
31aeac78 | 1570 | |
8ee22052 AB |
1571 | if ((clear_bv & X86_XSTATE_BNDREGS)) |
1572 | for (i = I387_BND0R_REGNUM (tdep); | |
1573 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
8938f531 | 1574 | memset (XSAVE_BNDREGS_ADDR (tdep, regs, i), 0, 16); |
51547df6 | 1575 | |
8ee22052 AB |
1576 | if ((clear_bv & X86_XSTATE_BNDCFG)) |
1577 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1578 | i < I387_MPXEND_REGNUM (tdep); i++) | |
8938f531 | 1579 | memset (XSAVE_BNDCFG_ADDR (tdep, regs, i), 0, 8); |
1dbcd68c | 1580 | |
b5420128 JB |
1581 | if ((clear_bv & X86_XSTATE_ZMM_H)) |
1582 | for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) | |
8938f531 | 1583 | memset (XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i), 0, 32); |
1dbcd68c | 1584 | |
8ee22052 AB |
1585 | if ((clear_bv & X86_XSTATE_K)) |
1586 | for (i = I387_K0_REGNUM (tdep); | |
1587 | i < I387_KEND_REGNUM (tdep); i++) | |
1588 | memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8); | |
01f9f808 | 1589 | |
8ee22052 AB |
1590 | if ((clear_bv & X86_XSTATE_ZMM)) |
1591 | { | |
8938f531 JB |
1592 | for (i = I387_ZMM16H_REGNUM (tdep); i < I387_ZMMENDH_REGNUM (tdep); |
1593 | i++) | |
1594 | memset (XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i), 0, 32); | |
8ee22052 AB |
1595 | for (i = I387_YMM16H_REGNUM (tdep); |
1596 | i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) | |
1597 | memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); | |
1598 | for (i = I387_XMM16_REGNUM (tdep); | |
1599 | i < I387_XMM_AVX512_END_REGNUM (tdep); i++) | |
1600 | memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16); | |
1601 | } | |
01f9f808 | 1602 | |
8ee22052 AB |
1603 | if ((clear_bv & X86_XSTATE_AVX)) |
1604 | for (i = I387_YMM0H_REGNUM (tdep); | |
1605 | i < I387_YMMENDH_REGNUM (tdep); i++) | |
1606 | memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); | |
01f9f808 | 1607 | |
8ee22052 AB |
1608 | if ((clear_bv & X86_XSTATE_SSE)) |
1609 | for (i = I387_XMM0_REGNUM (tdep); | |
1610 | i < I387_MXCSR_REGNUM (tdep); i++) | |
1611 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); | |
1612 | ||
1613 | /* The mxcsr register is written into the xsave buffer if either AVX | |
1614 | or SSE is enabled, so only clear it if both of those features | |
1615 | require clearing. */ | |
1616 | if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) | |
1617 | == (X86_XSTATE_AVX | X86_XSTATE_SSE)) | |
cf4912ae | 1618 | store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order, |
8ee22052 | 1619 | I387_MXCSR_INIT_VAL); |
31aeac78 | 1620 | |
8ee22052 AB |
1621 | if ((clear_bv & X86_XSTATE_X87)) |
1622 | { | |
1623 | for (i = I387_ST0_REGNUM (tdep); | |
1624 | i < I387_FCTRL_REGNUM (tdep); i++) | |
1625 | memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); | |
31aeac78 | 1626 | |
8ee22052 AB |
1627 | for (i = I387_FCTRL_REGNUM (tdep); |
1628 | i < I387_XMM0_REGNUM (tdep); i++) | |
1629 | { | |
1630 | if (i == I387_FCTRL_REGNUM (tdep)) | |
1631 | store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2, | |
1632 | byte_order, I387_FCTRL_INIT_VAL); | |
1633 | else | |
1634 | memset (FXSAVE_ADDR (tdep, regs, i), 0, | |
1635 | regcache_register_size (regcache, i)); | |
1636 | } | |
31aeac78 | 1637 | } |
8ee22052 | 1638 | } |
31aeac78 | 1639 | |
8ee22052 AB |
1640 | if (regclass == all) |
1641 | { | |
1642 | /* Check if any PKEYS registers are changed. */ | |
1643 | if ((tdep->xcr0 & X86_XSTATE_PKRU)) | |
1644 | for (i = I387_PKRU_REGNUM (tdep); | |
1645 | i < I387_PKEYSEND_REGNUM (tdep); i++) | |
1646 | { | |
34a79281 | 1647 | regcache->raw_collect (i, raw); |
8ee22052 AB |
1648 | p = XSAVE_PKEYS_ADDR (tdep, regs, i); |
1649 | if (memcmp (raw, p, 4) != 0) | |
51547df6 | 1650 | { |
8ee22052 AB |
1651 | xstate_bv |= X86_XSTATE_PKRU; |
1652 | memcpy (p, raw, 4); | |
51547df6 | 1653 | } |
8ee22052 | 1654 | } |
51547df6 | 1655 | |
8ee22052 | 1656 | /* Check if any ZMMH registers are changed. */ |
8938f531 JB |
1657 | if ((tdep->xcr0 & X86_XSTATE_ZMM)) |
1658 | for (i = I387_ZMM16H_REGNUM (tdep); | |
8ee22052 AB |
1659 | i < I387_ZMMENDH_REGNUM (tdep); i++) |
1660 | { | |
34a79281 | 1661 | regcache->raw_collect (i, raw); |
8938f531 | 1662 | p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, i); |
8ee22052 | 1663 | if (memcmp (raw, p, 32) != 0) |
01f9f808 | 1664 | { |
8938f531 JB |
1665 | xstate_bv |= X86_XSTATE_ZMM; |
1666 | memcpy (p, raw, 32); | |
1667 | } | |
1668 | } | |
1669 | ||
1670 | if ((tdep->xcr0 & X86_XSTATE_ZMM_H)) | |
1671 | for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) | |
1672 | { | |
1673 | regcache->raw_collect (i, raw); | |
1674 | p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, i); | |
1675 | if (memcmp (raw, p, 32) != 0) | |
1676 | { | |
1677 | xstate_bv |= X86_XSTATE_ZMM_H; | |
8ee22052 | 1678 | memcpy (p, raw, 32); |
01f9f808 | 1679 | } |
8ee22052 | 1680 | } |
01f9f808 | 1681 | |
8ee22052 AB |
1682 | /* Check if any K registers are changed. */ |
1683 | if ((tdep->xcr0 & X86_XSTATE_K)) | |
1684 | for (i = I387_K0_REGNUM (tdep); | |
1685 | i < I387_KEND_REGNUM (tdep); i++) | |
1686 | { | |
34a79281 | 1687 | regcache->raw_collect (i, raw); |
8ee22052 AB |
1688 | p = XSAVE_AVX512_K_ADDR (tdep, regs, i); |
1689 | if (memcmp (raw, p, 8) != 0) | |
01f9f808 | 1690 | { |
8ee22052 AB |
1691 | xstate_bv |= X86_XSTATE_K; |
1692 | memcpy (p, raw, 8); | |
01f9f808 | 1693 | } |
8ee22052 | 1694 | } |
01f9f808 | 1695 | |
8ee22052 AB |
1696 | /* Check if any XMM or upper YMM registers are changed. */ |
1697 | if ((tdep->xcr0 & X86_XSTATE_ZMM)) | |
1698 | { | |
1699 | for (i = I387_YMM16H_REGNUM (tdep); | |
1700 | i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) | |
01f9f808 | 1701 | { |
34a79281 | 1702 | regcache->raw_collect (i, raw); |
8ee22052 AB |
1703 | p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i); |
1704 | if (memcmp (raw, p, 16) != 0) | |
01f9f808 | 1705 | { |
8ee22052 AB |
1706 | xstate_bv |= X86_XSTATE_ZMM; |
1707 | memcpy (p, raw, 16); | |
01f9f808 | 1708 | } |
8ee22052 AB |
1709 | } |
1710 | for (i = I387_XMM16_REGNUM (tdep); | |
1711 | i < I387_XMM_AVX512_END_REGNUM (tdep); i++) | |
1712 | { | |
34a79281 | 1713 | regcache->raw_collect (i, raw); |
8ee22052 AB |
1714 | p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i); |
1715 | if (memcmp (raw, p, 16) != 0) | |
01f9f808 | 1716 | { |
8ee22052 AB |
1717 | xstate_bv |= X86_XSTATE_ZMM; |
1718 | memcpy (p, raw, 16); | |
01f9f808 MS |
1719 | } |
1720 | } | |
8ee22052 | 1721 | } |
01f9f808 | 1722 | |
8ee22052 AB |
1723 | /* Check if any upper MPX registers are changed. */ |
1724 | if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) | |
1725 | for (i = I387_BND0R_REGNUM (tdep); | |
1726 | i < I387_BNDCFGU_REGNUM (tdep); i++) | |
1727 | { | |
34a79281 | 1728 | regcache->raw_collect (i, raw); |
8938f531 | 1729 | p = XSAVE_BNDREGS_ADDR (tdep, regs, i); |
8ee22052 | 1730 | if (memcmp (raw, p, 16)) |
31aeac78 | 1731 | { |
8ee22052 AB |
1732 | xstate_bv |= X86_XSTATE_BNDREGS; |
1733 | memcpy (p, raw, 16); | |
31aeac78 | 1734 | } |
8ee22052 AB |
1735 | } |
1736 | ||
1737 | /* Check if any upper MPX registers are changed. */ | |
1738 | if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) | |
1739 | for (i = I387_BNDCFGU_REGNUM (tdep); | |
1740 | i < I387_MPXEND_REGNUM (tdep); i++) | |
1741 | { | |
34a79281 | 1742 | regcache->raw_collect (i, raw); |
8938f531 | 1743 | p = XSAVE_BNDCFG_ADDR (tdep, regs, i); |
8ee22052 | 1744 | if (memcmp (raw, p, 8)) |
1dbcd68c | 1745 | { |
8ee22052 AB |
1746 | xstate_bv |= X86_XSTATE_BNDCFG; |
1747 | memcpy (p, raw, 8); | |
1dbcd68c | 1748 | } |
8ee22052 | 1749 | } |
1dbcd68c | 1750 | |
8ee22052 AB |
1751 | /* Check if any upper YMM registers are changed. */ |
1752 | if ((tdep->xcr0 & X86_XSTATE_AVX)) | |
1753 | for (i = I387_YMM0H_REGNUM (tdep); | |
1754 | i < I387_YMMENDH_REGNUM (tdep); i++) | |
1755 | { | |
34a79281 | 1756 | regcache->raw_collect (i, raw); |
8ee22052 AB |
1757 | p = XSAVE_AVXH_ADDR (tdep, regs, i); |
1758 | if (memcmp (raw, p, 16)) | |
1dbcd68c | 1759 | { |
8ee22052 AB |
1760 | xstate_bv |= X86_XSTATE_AVX; |
1761 | memcpy (p, raw, 16); | |
1dbcd68c | 1762 | } |
8ee22052 | 1763 | } |
31aeac78 | 1764 | |
8ee22052 AB |
1765 | /* Check if any SSE registers are changed. */ |
1766 | if ((tdep->xcr0 & X86_XSTATE_SSE)) | |
1767 | for (i = I387_XMM0_REGNUM (tdep); | |
1768 | i < I387_MXCSR_REGNUM (tdep); i++) | |
1769 | { | |
34a79281 | 1770 | regcache->raw_collect (i, raw); |
8ee22052 AB |
1771 | p = FXSAVE_ADDR (tdep, regs, i); |
1772 | if (memcmp (raw, p, 16)) | |
31aeac78 | 1773 | { |
8ee22052 AB |
1774 | xstate_bv |= X86_XSTATE_SSE; |
1775 | memcpy (p, raw, 16); | |
31aeac78 | 1776 | } |
8ee22052 | 1777 | } |
31aeac78 | 1778 | |
8ee22052 AB |
1779 | if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE)) |
1780 | { | |
1781 | i = I387_MXCSR_REGNUM (tdep); | |
34a79281 | 1782 | regcache->raw_collect (i, raw); |
cf4912ae | 1783 | p = FXSAVE_MXCSR_ADDR (regs); |
8ee22052 AB |
1784 | if (memcmp (raw, p, 4)) |
1785 | { | |
1786 | /* Now, we need to mark one of either SSE of AVX as enabled. | |
1787 | We could pick either. What we do is check to see if one | |
1788 | of the features is already enabled, if it is then we leave | |
1789 | it at that, otherwise we pick SSE. */ | |
1790 | if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0) | |
1791 | xstate_bv |= X86_XSTATE_SSE; | |
1792 | memcpy (p, raw, 4); | |
1793 | } | |
1794 | } | |
1795 | ||
1796 | /* Check if any X87 registers are changed. Only the non-control | |
1797 | registers are handled here, the control registers are all handled | |
1798 | later on in this function. */ | |
1799 | if ((tdep->xcr0 & X86_XSTATE_X87)) | |
1800 | for (i = I387_ST0_REGNUM (tdep); | |
1801 | i < I387_FCTRL_REGNUM (tdep); i++) | |
1802 | { | |
34a79281 | 1803 | regcache->raw_collect (i, raw); |
8ee22052 AB |
1804 | p = FXSAVE_ADDR (tdep, regs, i); |
1805 | if (memcmp (raw, p, 10)) | |
31aeac78 | 1806 | { |
8ee22052 AB |
1807 | xstate_bv |= X86_XSTATE_X87; |
1808 | memcpy (p, raw, 10); | |
31aeac78 | 1809 | } |
8ee22052 AB |
1810 | } |
1811 | } | |
1812 | else | |
1813 | { | |
1814 | /* Check if REGNUM is changed. */ | |
34a79281 | 1815 | regcache->raw_collect (regnum, raw); |
31aeac78 | 1816 | |
8ee22052 AB |
1817 | switch (regclass) |
1818 | { | |
1819 | default: | |
f34652de | 1820 | internal_error (_("invalid i387 regclass")); |
8ee22052 AB |
1821 | |
1822 | case pkeys: | |
1823 | /* This is a PKEYS register. */ | |
1824 | p = XSAVE_PKEYS_ADDR (tdep, regs, regnum); | |
1825 | if (memcmp (raw, p, 4) != 0) | |
31aeac78 | 1826 | { |
8ee22052 AB |
1827 | xstate_bv |= X86_XSTATE_PKRU; |
1828 | memcpy (p, raw, 4); | |
1829 | } | |
1830 | break; | |
01f9f808 | 1831 | |
8938f531 JB |
1832 | case avx512_zmm16_h: |
1833 | /* This is a ZMM16-31 register. */ | |
1834 | p = XSAVE_AVX512_ZMM16_H_ADDR (tdep, regs, regnum); | |
8ee22052 AB |
1835 | if (memcmp (raw, p, 32) != 0) |
1836 | { | |
8938f531 | 1837 | xstate_bv |= X86_XSTATE_ZMM; |
8ee22052 AB |
1838 | memcpy (p, raw, 32); |
1839 | } | |
1840 | break; | |
8938f531 JB |
1841 | |
1842 | case avx512_zmm0_h: | |
1843 | /* This is a ZMM0-15 register. */ | |
1844 | p = XSAVE_AVX512_ZMM0_H_ADDR (tdep, regs, regnum); | |
1845 | if (memcmp (raw, p, 32) != 0) | |
1846 | { | |
1847 | xstate_bv |= X86_XSTATE_ZMM_H; | |
1848 | memcpy (p, raw, 32); | |
1849 | } | |
1850 | break; | |
1851 | ||
8ee22052 AB |
1852 | case avx512_k: |
1853 | /* This is a AVX512 mask register. */ | |
1854 | p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum); | |
1855 | if (memcmp (raw, p, 8) != 0) | |
1856 | { | |
1857 | xstate_bv |= X86_XSTATE_K; | |
1858 | memcpy (p, raw, 8); | |
1859 | } | |
1860 | break; | |
01f9f808 | 1861 | |
8ee22052 AB |
1862 | case avx512_ymmh_avx512: |
1863 | /* This is an upper YMM16-31 register. */ | |
1864 | p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum); | |
1865 | if (memcmp (raw, p, 16) != 0) | |
1866 | { | |
1867 | xstate_bv |= X86_XSTATE_ZMM; | |
1868 | memcpy (p, raw, 16); | |
1869 | } | |
1870 | break; | |
01f9f808 | 1871 | |
8ee22052 AB |
1872 | case avx512_xmm_avx512: |
1873 | /* This is an upper XMM16-31 register. */ | |
1874 | p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum); | |
1875 | if (memcmp (raw, p, 16) != 0) | |
1876 | { | |
1877 | xstate_bv |= X86_XSTATE_ZMM; | |
1878 | memcpy (p, raw, 16); | |
1879 | } | |
1880 | break; | |
31aeac78 | 1881 | |
8ee22052 AB |
1882 | case avxh: |
1883 | /* This is an upper YMM register. */ | |
1884 | p = XSAVE_AVXH_ADDR (tdep, regs, regnum); | |
1885 | if (memcmp (raw, p, 16)) | |
1886 | { | |
1887 | xstate_bv |= X86_XSTATE_AVX; | |
1888 | memcpy (p, raw, 16); | |
1889 | } | |
1890 | break; | |
1dbcd68c | 1891 | |
8938f531 JB |
1892 | case bndregs: |
1893 | regcache->raw_collect (regnum, raw); | |
1894 | p = XSAVE_BNDREGS_ADDR (tdep, regs, regnum); | |
1895 | if (memcmp (raw, p, 16)) | |
8ee22052 | 1896 | { |
8938f531 JB |
1897 | xstate_bv |= X86_XSTATE_BNDREGS; |
1898 | memcpy (p, raw, 16); | |
8ee22052 AB |
1899 | } |
1900 | break; | |
31aeac78 | 1901 | |
8938f531 JB |
1902 | case bndcfg: |
1903 | p = XSAVE_BNDCFG_ADDR (tdep, regs, regnum); | |
1904 | xstate_bv |= X86_XSTATE_BNDCFG; | |
1905 | memcpy (p, raw, 8); | |
1906 | break; | |
1907 | ||
8ee22052 AB |
1908 | case sse: |
1909 | /* This is an SSE register. */ | |
1910 | p = FXSAVE_ADDR (tdep, regs, regnum); | |
1911 | if (memcmp (raw, p, 16)) | |
1912 | { | |
1913 | xstate_bv |= X86_XSTATE_SSE; | |
1914 | memcpy (p, raw, 16); | |
31aeac78 | 1915 | } |
8ee22052 | 1916 | break; |
40936b0d | 1917 | |
8ee22052 AB |
1918 | case x87: |
1919 | /* This is an x87 register. */ | |
1920 | p = FXSAVE_ADDR (tdep, regs, regnum); | |
1921 | if (memcmp (raw, p, 10)) | |
1922 | { | |
1923 | xstate_bv |= X86_XSTATE_X87; | |
1924 | memcpy (p, raw, 10); | |
1925 | } | |
1926 | break; | |
40936b0d | 1927 | |
8ee22052 AB |
1928 | case x87_ctrl_or_mxcsr: |
1929 | /* We only handle MXCSR here. All other x87 control registers | |
1930 | are handled separately below. */ | |
1931 | if (regnum == I387_MXCSR_REGNUM (tdep)) | |
31aeac78 | 1932 | { |
8ee22052 AB |
1933 | p = FXSAVE_MXCSR_ADDR (regs); |
1934 | if (memcmp (raw, p, 2)) | |
1935 | { | |
1936 | /* We're only setting MXCSR, so check the initial state | |
1937 | to see if either of AVX or SSE are already enabled. | |
1938 | If they are then we'll attribute this changed MXCSR to | |
1939 | that feature. If neither feature is enabled, then | |
1940 | we'll attribute this change to the SSE feature. */ | |
1941 | xstate_bv |= (initial_xstate_bv | |
1942 | & (X86_XSTATE_AVX | X86_XSTATE_SSE)); | |
1943 | if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0) | |
1944 | xstate_bv |= X86_XSTATE_SSE; | |
1945 | memcpy (p, raw, 2); | |
1946 | } | |
31aeac78 | 1947 | } |
40936b0d | 1948 | } |
31aeac78 L |
1949 | } |
1950 | ||
1951 | /* Only handle x87 control registers. */ | |
1952 | for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) | |
1953 | if (regnum == -1 || regnum == i) | |
1954 | { | |
1955 | /* Most of the FPU control registers occupy only 16 bits in | |
1956 | the xsave extended state. Give those a special treatment. */ | |
1957 | if (i != I387_FIOFF_REGNUM (tdep) | |
1958 | && i != I387_FOOFF_REGNUM (tdep)) | |
1959 | { | |
1960 | gdb_byte buf[4]; | |
1961 | ||
34a79281 | 1962 | regcache->raw_collect (i, buf); |
31aeac78 | 1963 | |
20a6ec49 | 1964 | if (i == I387_FOP_REGNUM (tdep)) |
e750d25e JT |
1965 | { |
1966 | /* The opcode occupies only 11 bits. Make sure we | |
40936b0d | 1967 | don't touch the other bits. */ |
e750d25e | 1968 | buf[1] &= ((1 << 3) - 1); |
20a6ec49 | 1969 | buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); |
e750d25e | 1970 | } |
20a6ec49 | 1971 | else if (i == I387_FTAG_REGNUM (tdep)) |
e750d25e JT |
1972 | { |
1973 | /* Converting back is much easier. */ | |
1974 | ||
1975 | unsigned short ftag; | |
1976 | int fpreg; | |
1977 | ||
1978 | ftag = (buf[1] << 8) | buf[0]; | |
1979 | buf[0] = 0; | |
1980 | buf[1] = 0; | |
1981 | ||
1982 | for (fpreg = 7; fpreg >= 0; fpreg--) | |
1983 | { | |
1984 | int tag = (ftag >> (fpreg * 2)) & 3; | |
1985 | ||
1986 | if (tag != 3) | |
1987 | buf[0] |= (1 << fpreg); | |
1988 | } | |
1989 | } | |
8ee22052 AB |
1990 | p = FXSAVE_ADDR (tdep, regs, i); |
1991 | if (memcmp (p, buf, 2)) | |
1992 | { | |
1993 | xstate_bv |= X86_XSTATE_X87; | |
1994 | memcpy (p, buf, 2); | |
1995 | } | |
e750d25e JT |
1996 | } |
1997 | else | |
8ee22052 AB |
1998 | { |
1999 | int regsize; | |
2000 | ||
34a79281 | 2001 | regcache->raw_collect (i, raw); |
8ee22052 AB |
2002 | regsize = regcache_register_size (regcache, i); |
2003 | p = FXSAVE_ADDR (tdep, regs, i); | |
2004 | if (memcmp (raw, p, regsize)) | |
2005 | { | |
2006 | xstate_bv |= X86_XSTATE_X87; | |
2007 | memcpy (p, raw, regsize); | |
2008 | } | |
2009 | } | |
e750d25e | 2010 | } |
5716833c | 2011 | |
8ee22052 AB |
2012 | /* Update the corresponding bits in `xstate_bv' if any |
2013 | registers are changed. */ | |
2014 | if (xstate_bv) | |
2015 | { | |
2016 | /* The supported bits in `xstat_bv' are 8 bytes. */ | |
2017 | initial_xstate_bv |= xstate_bv; | |
2018 | store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), | |
2019 | 8, byte_order, | |
2020 | initial_xstate_bv); | |
2021 | } | |
e750d25e JT |
2022 | } |
2023 | ||
2024 | /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in | |
2025 | *RAW. */ | |
2026 | ||
2027 | static int | |
b4ad899f | 2028 | i387_tag (const gdb_byte *raw) |
e750d25e JT |
2029 | { |
2030 | int integer; | |
2031 | unsigned int exponent; | |
2032 | unsigned long fraction[2]; | |
2033 | ||
2034 | integer = raw[7] & 0x80; | |
2035 | exponent = (((raw[9] & 0x7f) << 8) | raw[8]); | |
2036 | fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); | |
2037 | fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) | |
2038 | | (raw[5] << 8) | raw[4]); | |
2039 | ||
2040 | if (exponent == 0x7fff) | |
2041 | { | |
2042 | /* Special. */ | |
2043 | return (2); | |
2044 | } | |
2045 | else if (exponent == 0x0000) | |
2046 | { | |
2047 | if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer) | |
2048 | { | |
2049 | /* Zero. */ | |
2050 | return (1); | |
2051 | } | |
2052 | else | |
2053 | { | |
2054 | /* Special. */ | |
2055 | return (2); | |
2056 | } | |
2057 | } | |
2058 | else | |
2059 | { | |
2060 | if (integer) | |
2061 | { | |
2062 | /* Valid. */ | |
2063 | return (0); | |
2064 | } | |
2065 | else | |
2066 | { | |
2067 | /* Special. */ | |
2068 | return (2); | |
2069 | } | |
2070 | } | |
2071 | } | |
efb1c01c MK |
2072 | |
2073 | /* Prepare the FPU stack in REGCACHE for a function return. */ | |
2074 | ||
2075 | void | |
2076 | i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache) | |
2077 | { | |
08106042 | 2078 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
efb1c01c MK |
2079 | ULONGEST fstat; |
2080 | ||
efb1c01c MK |
2081 | /* Set the top of the floating-point register stack to 7. The |
2082 | actual value doesn't really matter, but 7 is what a normal | |
2083 | function return would end up with if the program started out with | |
2084 | a freshly initialized FPU. */ | |
20a6ec49 | 2085 | regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); |
efb1c01c | 2086 | fstat |= (7 << 11); |
20a6ec49 | 2087 | regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); |
efb1c01c MK |
2088 | |
2089 | /* Mark %st(1) through %st(7) as empty. Since we set the top of the | |
2090 | floating-point register stack to 7, the appropriate value for the | |
2091 | tag word is 0x3fff. */ | |
20a6ec49 | 2092 | regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); |
efb1c01c | 2093 | |
efb1c01c | 2094 | } |
4a612d6f WT |
2095 | |
2096 | /* See i387-tdep.h. */ | |
2097 | ||
2098 | void | |
2099 | i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache) | |
2100 | { | |
08106042 | 2101 | i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); |
4a612d6f WT |
2102 | |
2103 | if (I387_BND0R_REGNUM (tdep) > 0) | |
2104 | { | |
2105 | gdb_byte bnd_buf[16]; | |
2106 | ||
2107 | memset (bnd_buf, 0, 16); | |
2108 | for (int i = 0; i < I387_NUM_BND_REGS; i++) | |
10eaee5f | 2109 | regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf); |
4a612d6f WT |
2110 | } |
2111 | } |