]>
Commit | Line | Data |
---|---|---|
c28c63d8 JB |
1 | /* Target-dependent code for Lattice Mico32 processor, for GDB. |
2 | Contributed by Jon Beniston <jon@beniston.com> | |
3 | ||
1d506c26 | 4 | Copyright (C) 2009-2024 Free Software Foundation, Inc. |
c28c63d8 JB |
5 | |
6 | This file is part of GDB. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
20 | ||
ec452525 | 21 | #include "extract-store-integer.h" |
c28c63d8 JB |
22 | #include "frame.h" |
23 | #include "frame-unwind.h" | |
24 | #include "frame-base.h" | |
25 | #include "inferior.h" | |
26 | #include "dis-asm.h" | |
27 | #include "symfile.h" | |
28 | #include "remote.h" | |
29 | #include "gdbcore.h" | |
d026e67e | 30 | #include "sim/sim-lm32.h" |
c28c63d8 JB |
31 | #include "arch-utils.h" |
32 | #include "regcache.h" | |
33 | #include "trad-frame.h" | |
34 | #include "reggroups.h" | |
325fac50 | 35 | #include <algorithm> |
76eb8ef1 | 36 | #include "gdbarch.h" |
c28c63d8 | 37 | |
883d90a0 TV |
38 | /* Make cgen names unique to prevent ODR conflicts with other targets. */ |
39 | #define GDB_CGEN_REMAP_PREFIX lm32 | |
40 | #include "cgen-remap.h" | |
41 | #include "opcodes/lm32-desc.h" | |
42 | ||
c28c63d8 JB |
43 | /* Macros to extract fields from an instruction. */ |
44 | #define LM32_OPCODE(insn) ((insn >> 26) & 0x3f) | |
45 | #define LM32_REG0(insn) ((insn >> 21) & 0x1f) | |
46 | #define LM32_REG1(insn) ((insn >> 16) & 0x1f) | |
47 | #define LM32_REG2(insn) ((insn >> 11) & 0x1f) | |
48 | #define LM32_IMM16(insn) ((((long)insn & 0xffff) << 16) >> 16) | |
49 | ||
ab25d9bb | 50 | struct lm32_gdbarch_tdep : gdbarch_tdep_base |
c28c63d8 | 51 | { |
1777feb0 | 52 | /* gdbarch target dependent data here. Currently unused for LM32. */ |
c28c63d8 JB |
53 | }; |
54 | ||
55 | struct lm32_frame_cache | |
56 | { | |
57 | /* The frame's base. Used when constructing a frame ID. */ | |
58 | CORE_ADDR base; | |
59 | CORE_ADDR pc; | |
60 | /* Size of frame. */ | |
61 | int size; | |
62 | /* Table indicating the location of each and every register. */ | |
098caef4 | 63 | trad_frame_saved_reg *saved_regs; |
c28c63d8 JB |
64 | }; |
65 | ||
c28c63d8 JB |
66 | /* Return whether a given register is in a given group. */ |
67 | ||
68 | static int | |
69 | lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 70 | const struct reggroup *group) |
c28c63d8 JB |
71 | { |
72 | if (group == general_reggroup) | |
73 | return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM)) | |
74 | || (regnum == SIM_LM32_PC_REGNUM); | |
75 | else if (group == system_reggroup) | |
aa370940 | 76 | return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM)) |
c28c63d8 JB |
77 | || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM)); |
78 | return default_register_reggroup_p (gdbarch, regnum, group); | |
79 | } | |
80 | ||
81 | /* Return a name that corresponds to the given register number. */ | |
82 | ||
83 | static const char * | |
84 | lm32_register_name (struct gdbarch *gdbarch, int reg_nr) | |
85 | { | |
a121b7c1 | 86 | static const char *register_names[] = { |
c28c63d8 JB |
87 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", |
88 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
89 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
90 | "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba", | |
91 | "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP" | |
92 | }; | |
93 | ||
69f6730d | 94 | static_assert (ARRAY_SIZE (register_names) == SIM_LM32_NUM_REGS); |
9b9e61c7 | 95 | return register_names[reg_nr]; |
c28c63d8 JB |
96 | } |
97 | ||
98 | /* Return type of register. */ | |
99 | ||
100 | static struct type * | |
101 | lm32_register_type (struct gdbarch *gdbarch, int reg_nr) | |
102 | { | |
df4df182 | 103 | return builtin_type (gdbarch)->builtin_int32; |
c28c63d8 JB |
104 | } |
105 | ||
106 | /* Return non-zero if a register can't be written. */ | |
107 | ||
108 | static int | |
109 | lm32_cannot_store_register (struct gdbarch *gdbarch, int regno) | |
110 | { | |
111 | return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM); | |
112 | } | |
113 | ||
114 | /* Analyze a function's prologue. */ | |
115 | ||
116 | static CORE_ADDR | |
e17a4113 UW |
117 | lm32_analyze_prologue (struct gdbarch *gdbarch, |
118 | CORE_ADDR pc, CORE_ADDR limit, | |
c28c63d8 JB |
119 | struct lm32_frame_cache *info) |
120 | { | |
e17a4113 | 121 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 JB |
122 | unsigned long instruction; |
123 | ||
124 | /* Keep reading though instructions, until we come across an instruction | |
125 | that isn't likely to be part of the prologue. */ | |
126 | info->size = 0; | |
127 | for (; pc < limit; pc += 4) | |
128 | { | |
129 | ||
130 | /* Read an instruction. */ | |
e17a4113 | 131 | instruction = read_memory_integer (pc, 4, byte_order); |
c28c63d8 JB |
132 | |
133 | if ((LM32_OPCODE (instruction) == OP_SW) | |
134 | && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM)) | |
135 | { | |
1777feb0 | 136 | /* Any stack displaced store is likely part of the prologue. |
c28c63d8 JB |
137 | Record that the register is being saved, and the offset |
138 | into the stack. */ | |
098caef4 | 139 | info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction)); |
c28c63d8 JB |
140 | } |
141 | else if ((LM32_OPCODE (instruction) == OP_ADDI) | |
142 | && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM)) | |
143 | { | |
1777feb0 | 144 | /* An add to the SP is likely to be part of the prologue. |
c28c63d8 JB |
145 | Adjust stack size by whatever the instruction adds to the sp. */ |
146 | info->size -= LM32_IMM16 (instruction); | |
147 | } | |
148 | else if ( /* add fp,fp,sp */ | |
149 | ((LM32_OPCODE (instruction) == OP_ADD) | |
150 | && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM) | |
151 | && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM) | |
152 | && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM)) | |
153 | /* mv fp,imm */ | |
154 | || ((LM32_OPCODE (instruction) == OP_ADDI) | |
155 | && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM) | |
156 | && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM))) | |
157 | { | |
158 | /* Likely to be in the prologue for functions that require | |
159 | a frame pointer. */ | |
160 | } | |
161 | else | |
162 | { | |
1777feb0 MS |
163 | /* Any other instruction is likely not to be part of the |
164 | prologue. */ | |
c28c63d8 JB |
165 | break; |
166 | } | |
167 | } | |
168 | ||
169 | return pc; | |
170 | } | |
171 | ||
172 | /* Return PC of first non prologue instruction, for the function at the | |
173 | specified address. */ | |
174 | ||
175 | static CORE_ADDR | |
176 | lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) | |
177 | { | |
178 | CORE_ADDR func_addr, limit_pc; | |
c28c63d8 | 179 | struct lm32_frame_cache frame_info; |
098caef4 | 180 | trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS]; |
c28c63d8 JB |
181 | |
182 | /* See if we can determine the end of the prologue via the symbol table. | |
183 | If so, then return either PC, or the PC after the prologue, whichever | |
184 | is greater. */ | |
185 | if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) | |
186 | { | |
d80b854b UW |
187 | CORE_ADDR post_prologue_pc |
188 | = skip_prologue_using_sal (gdbarch, func_addr); | |
c28c63d8 | 189 | if (post_prologue_pc != 0) |
325fac50 | 190 | return std::max (pc, post_prologue_pc); |
c28c63d8 JB |
191 | } |
192 | ||
193 | /* Can't determine prologue from the symbol table, need to examine | |
194 | instructions. */ | |
195 | ||
196 | /* Find an upper limit on the function prologue using the debug | |
197 | information. If the debug information could not be used to provide | |
198 | that bound, then use an arbitrary large number as the upper bound. */ | |
d80b854b | 199 | limit_pc = skip_prologue_using_sal (gdbarch, pc); |
c28c63d8 JB |
200 | if (limit_pc == 0) |
201 | limit_pc = pc + 100; /* Magic. */ | |
202 | ||
203 | frame_info.saved_regs = saved_regs; | |
e17a4113 | 204 | return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info); |
c28c63d8 JB |
205 | } |
206 | ||
207 | /* Create a breakpoint instruction. */ | |
04180708 | 208 | constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 }; |
c28c63d8 | 209 | |
04180708 | 210 | typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint; |
c28c63d8 | 211 | |
c28c63d8 JB |
212 | |
213 | /* Setup registers and stack for faking a call to a function in the | |
214 | inferior. */ | |
215 | ||
216 | static CORE_ADDR | |
217 | lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, | |
218 | struct regcache *regcache, CORE_ADDR bp_addr, | |
219 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
220 | function_call_return_method return_method, |
221 | CORE_ADDR struct_addr) | |
c28c63d8 | 222 | { |
e17a4113 | 223 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 JB |
224 | int first_arg_reg = SIM_LM32_R1_REGNUM; |
225 | int num_arg_regs = 8; | |
226 | int i; | |
227 | ||
228 | /* Set the return address. */ | |
229 | regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr); | |
230 | ||
231 | /* If we're returning a large struct, a pointer to the address to | |
232 | store it at is passed as a first hidden parameter. */ | |
cf84fa6b | 233 | if (return_method == return_method_struct) |
c28c63d8 JB |
234 | { |
235 | regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr); | |
236 | first_arg_reg++; | |
237 | num_arg_regs--; | |
238 | sp -= 4; | |
239 | } | |
240 | ||
241 | /* Setup parameters. */ | |
242 | for (i = 0; i < nargs; i++) | |
243 | { | |
244 | struct value *arg = args[i]; | |
d0c97917 | 245 | struct type *arg_type = check_typedef (arg->type ()); |
c28c63d8 | 246 | gdb_byte *contents; |
c28c63d8 JB |
247 | ULONGEST val; |
248 | ||
249 | /* Promote small integer types to int. */ | |
78134374 | 250 | switch (arg_type->code ()) |
c28c63d8 JB |
251 | { |
252 | case TYPE_CODE_INT: | |
253 | case TYPE_CODE_BOOL: | |
254 | case TYPE_CODE_CHAR: | |
255 | case TYPE_CODE_RANGE: | |
256 | case TYPE_CODE_ENUM: | |
df86565b | 257 | if (arg_type->length () < 4) |
c28c63d8 | 258 | { |
df4df182 | 259 | arg_type = builtin_type (gdbarch)->builtin_int32; |
c28c63d8 JB |
260 | arg = value_cast (arg_type, arg); |
261 | } | |
262 | break; | |
263 | } | |
264 | ||
265 | /* FIXME: Handle structures. */ | |
266 | ||
efaf1ae0 | 267 | contents = (gdb_byte *) arg->contents ().data (); |
df86565b | 268 | val = extract_unsigned_integer (contents, arg_type->length (), |
744a8059 | 269 | byte_order); |
c28c63d8 JB |
270 | |
271 | /* First num_arg_regs parameters are passed by registers, | |
dda83cd7 | 272 | and the rest are passed on the stack. */ |
c28c63d8 JB |
273 | if (i < num_arg_regs) |
274 | regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val); | |
275 | else | |
276 | { | |
df86565b | 277 | write_memory_unsigned_integer (sp, arg_type->length (), byte_order, |
4666fec3 | 278 | val); |
c28c63d8 JB |
279 | sp -= 4; |
280 | } | |
281 | } | |
282 | ||
283 | /* Update stack pointer. */ | |
284 | regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp); | |
285 | ||
286 | /* Return adjusted stack pointer. */ | |
287 | return sp; | |
288 | } | |
289 | ||
290 | /* Extract return value after calling a function in the inferior. */ | |
291 | ||
292 | static void | |
293 | lm32_extract_return_value (struct type *type, struct regcache *regcache, | |
294 | gdb_byte *valbuf) | |
295 | { | |
ac7936df | 296 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 297 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 JB |
298 | ULONGEST l; |
299 | CORE_ADDR return_buffer; | |
300 | ||
78134374 SM |
301 | if (type->code () != TYPE_CODE_STRUCT |
302 | && type->code () != TYPE_CODE_UNION | |
df86565b | 303 | && type->code () != TYPE_CODE_ARRAY && type->length () <= 4) |
c28c63d8 JB |
304 | { |
305 | /* Return value is returned in a single register. */ | |
306 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); | |
df86565b | 307 | store_unsigned_integer (valbuf, type->length (), byte_order, l); |
c28c63d8 | 308 | } |
df86565b | 309 | else if ((type->code () == TYPE_CODE_INT) && (type->length () == 8)) |
c28c63d8 JB |
310 | { |
311 | /* 64-bit values are returned in a register pair. */ | |
312 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); | |
313 | memcpy (valbuf, &l, 4); | |
314 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l); | |
315 | memcpy (valbuf + 4, &l, 4); | |
316 | } | |
317 | else | |
318 | { | |
1777feb0 | 319 | /* Aggregate types greater than a single register are returned |
dda83cd7 | 320 | in memory. FIXME: Unless they are only 2 regs?. */ |
c28c63d8 JB |
321 | regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l); |
322 | return_buffer = l; | |
df86565b | 323 | read_memory (return_buffer, valbuf, type->length ()); |
c28c63d8 JB |
324 | } |
325 | } | |
326 | ||
327 | /* Write into appropriate registers a function return value of type | |
328 | TYPE, given in virtual format. */ | |
329 | static void | |
330 | lm32_store_return_value (struct type *type, struct regcache *regcache, | |
331 | const gdb_byte *valbuf) | |
332 | { | |
ac7936df | 333 | struct gdbarch *gdbarch = regcache->arch (); |
e17a4113 | 334 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
c28c63d8 | 335 | ULONGEST val; |
df86565b | 336 | int len = type->length (); |
c28c63d8 | 337 | |
bad43aa5 | 338 | if (len <= 4) |
c28c63d8 | 339 | { |
bad43aa5 | 340 | val = extract_unsigned_integer (valbuf, len, byte_order); |
c28c63d8 JB |
341 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val); |
342 | } | |
bad43aa5 | 343 | else if (len <= 8) |
c28c63d8 | 344 | { |
e17a4113 | 345 | val = extract_unsigned_integer (valbuf, 4, byte_order); |
c28c63d8 | 346 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val); |
bad43aa5 | 347 | val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order); |
c28c63d8 JB |
348 | regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val); |
349 | } | |
350 | else | |
351 | error (_("lm32_store_return_value: type length too large.")); | |
352 | } | |
353 | ||
354 | /* Determine whether a functions return value is in a register or memory. */ | |
355 | static enum return_value_convention | |
6a3a010b | 356 | lm32_return_value (struct gdbarch *gdbarch, struct value *function, |
c28c63d8 JB |
357 | struct type *valtype, struct regcache *regcache, |
358 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
359 | { | |
78134374 | 360 | enum type_code code = valtype->code (); |
c28c63d8 JB |
361 | |
362 | if (code == TYPE_CODE_STRUCT | |
363 | || code == TYPE_CODE_UNION | |
df86565b | 364 | || code == TYPE_CODE_ARRAY || valtype->length () > 8) |
c28c63d8 JB |
365 | return RETURN_VALUE_STRUCT_CONVENTION; |
366 | ||
367 | if (readbuf) | |
368 | lm32_extract_return_value (valtype, regcache, readbuf); | |
369 | if (writebuf) | |
370 | lm32_store_return_value (valtype, regcache, writebuf); | |
371 | ||
372 | return RETURN_VALUE_REGISTER_CONVENTION; | |
373 | } | |
374 | ||
c28c63d8 JB |
375 | /* Put here the code to store, into fi->saved_regs, the addresses of |
376 | the saved registers of frame described by FRAME_INFO. This | |
377 | includes special registers such as pc and fp saved in special ways | |
378 | in the stack frame. sp is even more special: the address we return | |
379 | for it IS the sp for the next frame. */ | |
380 | ||
381 | static struct lm32_frame_cache * | |
8480a37e | 382 | lm32_frame_cache (const frame_info_ptr &this_frame, void **this_prologue_cache) |
c28c63d8 | 383 | { |
c28c63d8 JB |
384 | CORE_ADDR current_pc; |
385 | ULONGEST prev_sp; | |
386 | ULONGEST this_base; | |
387 | struct lm32_frame_cache *info; | |
c28c63d8 | 388 | int i; |
c28c63d8 JB |
389 | |
390 | if ((*this_prologue_cache)) | |
9a3c8263 | 391 | return (struct lm32_frame_cache *) (*this_prologue_cache); |
c28c63d8 JB |
392 | |
393 | info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache); | |
394 | (*this_prologue_cache) = info; | |
395 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); | |
396 | ||
397 | info->pc = get_frame_func (this_frame); | |
398 | current_pc = get_frame_pc (this_frame); | |
e17a4113 UW |
399 | lm32_analyze_prologue (get_frame_arch (this_frame), |
400 | info->pc, current_pc, info); | |
c28c63d8 JB |
401 | |
402 | /* Compute the frame's base, and the previous frame's SP. */ | |
403 | this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM); | |
404 | prev_sp = this_base + info->size; | |
405 | info->base = this_base; | |
406 | ||
407 | /* Convert callee save offsets into addresses. */ | |
408 | for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) | |
409 | { | |
a9a87d35 | 410 | if (info->saved_regs[i].is_addr ()) |
098caef4 | 411 | info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ()); |
c28c63d8 JB |
412 | } |
413 | ||
414 | /* The call instruction moves the caller's PC in the callee's RA register. | |
415 | Since this is an unwind, do the reverse. Copy the location of RA register | |
416 | into PC (the address / regnum) so that a request for PC will be | |
417 | converted into a request for the RA register. */ | |
418 | info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM]; | |
419 | ||
1777feb0 MS |
420 | /* The previous frame's SP needed to be computed. Save the computed |
421 | value. */ | |
a9a87d35 | 422 | info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp); |
c28c63d8 JB |
423 | |
424 | return info; | |
425 | } | |
426 | ||
427 | static void | |
8480a37e | 428 | lm32_frame_this_id (const frame_info_ptr &this_frame, void **this_cache, |
c28c63d8 JB |
429 | struct frame_id *this_id) |
430 | { | |
431 | struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache); | |
432 | ||
433 | /* This marks the outermost frame. */ | |
434 | if (cache->base == 0) | |
435 | return; | |
436 | ||
437 | (*this_id) = frame_id_build (cache->base, cache->pc); | |
438 | } | |
439 | ||
440 | static struct value * | |
8480a37e | 441 | lm32_frame_prev_register (const frame_info_ptr &this_frame, |
c28c63d8 JB |
442 | void **this_prologue_cache, int regnum) |
443 | { | |
444 | struct lm32_frame_cache *info; | |
445 | ||
446 | info = lm32_frame_cache (this_frame, this_prologue_cache); | |
447 | return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); | |
448 | } | |
449 | ||
450 | static const struct frame_unwind lm32_frame_unwind = { | |
a154d838 | 451 | "lm32 prologue", |
c28c63d8 | 452 | NORMAL_FRAME, |
8fbca658 | 453 | default_frame_unwind_stop_reason, |
c28c63d8 JB |
454 | lm32_frame_this_id, |
455 | lm32_frame_prev_register, | |
456 | NULL, | |
457 | default_frame_sniffer | |
458 | }; | |
459 | ||
460 | static CORE_ADDR | |
8480a37e | 461 | lm32_frame_base_address (const frame_info_ptr &this_frame, void **this_cache) |
c28c63d8 JB |
462 | { |
463 | struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache); | |
464 | ||
465 | return info->base; | |
466 | } | |
467 | ||
468 | static const struct frame_base lm32_frame_base = { | |
469 | &lm32_frame_unwind, | |
470 | lm32_frame_base_address, | |
471 | lm32_frame_base_address, | |
472 | lm32_frame_base_address | |
473 | }; | |
474 | ||
475 | static CORE_ADDR | |
476 | lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) | |
477 | { | |
478 | /* Align to the size of an instruction (so that they can safely be | |
479 | pushed onto the stack. */ | |
480 | return sp & ~3; | |
481 | } | |
482 | ||
483 | static struct gdbarch * | |
484 | lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) | |
485 | { | |
c28c63d8 JB |
486 | /* If there is already a candidate, use it. */ |
487 | arches = gdbarch_list_lookup_by_info (arches, &info); | |
488 | if (arches != NULL) | |
489 | return arches->gdbarch; | |
490 | ||
491 | /* None found, create a new architecture from the information provided. */ | |
2b16913c SM |
492 | gdbarch *gdbarch |
493 | = gdbarch_alloc (&info, gdbarch_tdep_up (new lm32_gdbarch_tdep)); | |
c28c63d8 JB |
494 | |
495 | /* Type sizes. */ | |
496 | set_gdbarch_short_bit (gdbarch, 16); | |
497 | set_gdbarch_int_bit (gdbarch, 32); | |
498 | set_gdbarch_long_bit (gdbarch, 32); | |
499 | set_gdbarch_long_long_bit (gdbarch, 64); | |
500 | set_gdbarch_float_bit (gdbarch, 32); | |
501 | set_gdbarch_double_bit (gdbarch, 64); | |
502 | set_gdbarch_long_double_bit (gdbarch, 64); | |
503 | set_gdbarch_ptr_bit (gdbarch, 32); | |
504 | ||
505 | /* Register info. */ | |
506 | set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS); | |
507 | set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM); | |
508 | set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM); | |
509 | set_gdbarch_register_name (gdbarch, lm32_register_name); | |
510 | set_gdbarch_register_type (gdbarch, lm32_register_type); | |
511 | set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register); | |
512 | ||
513 | /* Frame info. */ | |
514 | set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue); | |
515 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
516 | set_gdbarch_decr_pc_after_break (gdbarch, 0); | |
517 | set_gdbarch_frame_args_skip (gdbarch, 0); | |
518 | ||
519 | /* Frame unwinding. */ | |
520 | set_gdbarch_frame_align (gdbarch, lm32_frame_align); | |
521 | frame_base_set_default (gdbarch, &lm32_frame_base); | |
c28c63d8 JB |
522 | frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind); |
523 | ||
524 | /* Breakpoints. */ | |
04180708 YQ |
525 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc); |
526 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind); | |
c28c63d8 JB |
527 | set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); |
528 | ||
529 | /* Calling functions in the inferior. */ | |
530 | set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call); | |
531 | set_gdbarch_return_value (gdbarch, lm32_return_value); | |
532 | ||
c28c63d8 JB |
533 | set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p); |
534 | ||
535 | return gdbarch; | |
536 | } | |
537 | ||
6c265988 | 538 | void _initialize_lm32_tdep (); |
c28c63d8 | 539 | void |
6c265988 | 540 | _initialize_lm32_tdep () |
c28c63d8 | 541 | { |
ec29a63c | 542 | gdbarch_register (bfd_arch_lm32, lm32_gdbarch_init); |
c28c63d8 | 543 | } |