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908f682f | 1 | /* Target-dependent code for Motorola 68HC11 & 68HC12 |
931aecf5 | 2 | |
213516ef | 3 | Copyright (C) 1999-2023 Free Software Foundation, Inc. |
931aecf5 | 4 | |
ffe1f3ee | 5 | Contributed by Stephane Carrez, stcarrez@nerim.fr |
78073dd8 | 6 | |
a9762ec7 JB |
7 | This file is part of GDB. |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 3 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program. If not, see <http://www.gnu.org/licenses/>. */ | |
78073dd8 | 21 | |
78073dd8 | 22 | |
82c230c2 SC |
23 | #include "defs.h" |
24 | #include "frame.h" | |
1ea653ae SC |
25 | #include "frame-unwind.h" |
26 | #include "frame-base.h" | |
82ca8957 | 27 | #include "dwarf2/frame.h" |
1ea653ae | 28 | #include "trad-frame.h" |
82c230c2 SC |
29 | #include "symtab.h" |
30 | #include "gdbtypes.h" | |
31 | #include "gdbcmd.h" | |
32 | #include "gdbcore.h" | |
82c230c2 SC |
33 | #include "value.h" |
34 | #include "inferior.h" | |
35 | #include "dis-asm.h" | |
36 | #include "symfile.h" | |
37 | #include "objfiles.h" | |
38 | #include "arch-utils.h" | |
4e052eda | 39 | #include "regcache.h" |
b631436b | 40 | #include "reggroups.h" |
76eb8ef1 | 41 | #include "gdbarch.h" |
78073dd8 | 42 | |
82c230c2 SC |
43 | #include "target.h" |
44 | #include "opcode/m68hc11.h" | |
81967506 SC |
45 | #include "elf/m68hc11.h" |
46 | #include "elf-bfd.h" | |
78073dd8 | 47 | |
7df11f59 SC |
48 | /* Macros for setting and testing a bit in a minimal symbol. |
49 | For 68HC11/68HC12 we have two flags that tell which return | |
50 | type the function is using. This is used for prologue and frame | |
51 | analysis to compute correct stack frame layout. | |
52 | ||
53 | The MSB of the minimal symbol's "info" field is used for this purpose. | |
7df11f59 SC |
54 | |
55 | MSYMBOL_SET_RTC Actually sets the "RTC" bit. | |
56 | MSYMBOL_SET_RTI Actually sets the "RTI" bit. | |
57 | MSYMBOL_IS_RTC Tests the "RTC" bit in a minimal symbol. | |
f594e5e9 | 58 | MSYMBOL_IS_RTI Tests the "RTC" bit in a minimal symbol. */ |
7df11f59 | 59 | |
025bb325 | 60 | #define MSYMBOL_SET_RTC(msym) \ |
e165fcef | 61 | (msym)->set_target_flag_1 (true) |
7df11f59 | 62 | |
025bb325 | 63 | #define MSYMBOL_SET_RTI(msym) \ |
e165fcef | 64 | (msym)->set_target_flag_2 (true) |
7df11f59 SC |
65 | |
66 | #define MSYMBOL_IS_RTC(msym) \ | |
e165fcef | 67 | (msym)->target_flag_1 () |
7df11f59 SC |
68 | |
69 | #define MSYMBOL_IS_RTI(msym) \ | |
e165fcef | 70 | (msym)->target_flag_2 () |
7df11f59 | 71 | |
7df11f59 SC |
72 | enum insn_return_kind { |
73 | RETURN_RTS, | |
74 | RETURN_RTC, | |
75 | RETURN_RTI | |
76 | }; | |
77 | ||
78 | ||
7157eed4 | 79 | /* Register numbers of various important registers. */ |
78073dd8 | 80 | |
82c230c2 SC |
81 | #define HARD_X_REGNUM 0 |
82 | #define HARD_D_REGNUM 1 | |
83 | #define HARD_Y_REGNUM 2 | |
84 | #define HARD_SP_REGNUM 3 | |
85 | #define HARD_PC_REGNUM 4 | |
86 | ||
87 | #define HARD_A_REGNUM 5 | |
88 | #define HARD_B_REGNUM 6 | |
89 | #define HARD_CCR_REGNUM 7 | |
5706502a SC |
90 | |
91 | /* 68HC12 page number register. | |
92 | Note: to keep a compatibility with gcc register naming, we must | |
93 | not have to rename FP and other soft registers. The page register | |
f57d151a | 94 | is a real hard register and must therefore be counted by gdbarch_num_regs. |
5706502a SC |
95 | For this it has the same number as Z register (which is not used). */ |
96 | #define HARD_PAGE_REGNUM 8 | |
97 | #define M68HC11_LAST_HARD_REG (HARD_PAGE_REGNUM) | |
82c230c2 SC |
98 | |
99 | /* Z is replaced by X or Y by gcc during machine reorg. | |
100 | ??? There is no way to get it and even know whether | |
101 | it's in X or Y or in ZS. */ | |
102 | #define SOFT_Z_REGNUM 8 | |
103 | ||
104 | /* Soft registers. These registers are special. There are treated | |
105 | like normal hard registers by gcc and gdb (ie, within dwarf2 info). | |
106 | They are physically located in memory. */ | |
107 | #define SOFT_FP_REGNUM 9 | |
108 | #define SOFT_TMP_REGNUM 10 | |
109 | #define SOFT_ZS_REGNUM 11 | |
110 | #define SOFT_XY_REGNUM 12 | |
f91a8b6b SC |
111 | #define SOFT_UNUSED_REGNUM 13 |
112 | #define SOFT_D1_REGNUM 14 | |
82c230c2 SC |
113 | #define SOFT_D32_REGNUM (SOFT_D1_REGNUM+31) |
114 | #define M68HC11_MAX_SOFT_REGS 32 | |
115 | ||
a714b0d6 | 116 | #define M68HC11_NUM_REGS (M68HC11_LAST_HARD_REG + 1) |
82c230c2 SC |
117 | #define M68HC11_NUM_PSEUDO_REGS (M68HC11_MAX_SOFT_REGS+5) |
118 | #define M68HC11_ALL_REGS (M68HC11_NUM_REGS+M68HC11_NUM_PSEUDO_REGS) | |
119 | ||
120 | #define M68HC11_REG_SIZE (2) | |
121 | ||
548bcbec SC |
122 | #define M68HC12_NUM_REGS (9) |
123 | #define M68HC12_NUM_PSEUDO_REGS ((M68HC11_MAX_SOFT_REGS+5)+1-1) | |
124 | #define M68HC12_HARD_PC_REGNUM (SOFT_D32_REGNUM+1) | |
125 | ||
908f682f | 126 | struct insn_sequence; |
ab25d9bb | 127 | struct m68gc11_gdbarch_tdep : gdbarch_tdep_base |
82c230c2 | 128 | { |
5d1a66bd SC |
129 | /* Stack pointer correction value. For 68hc11, the stack pointer points |
130 | to the next push location. An offset of 1 must be applied to obtain | |
131 | the address where the last value is saved. For 68hc12, the stack | |
132 | pointer points to the last value pushed. No offset is necessary. */ | |
345bd07c | 133 | int stack_correction = 0; |
908f682f SC |
134 | |
135 | /* Description of instructions in the prologue. */ | |
345bd07c | 136 | struct insn_sequence *prologue = nullptr; |
81967506 | 137 | |
7df11f59 SC |
138 | /* True if the page memory bank register is available |
139 | and must be used. */ | |
345bd07c | 140 | int use_page_register = 0; |
7df11f59 | 141 | |
81967506 | 142 | /* ELF flags for ABI. */ |
345bd07c | 143 | int elf_flags = 0; |
82c230c2 SC |
144 | }; |
145 | ||
345bd07c SM |
146 | static int |
147 | stack_correction (gdbarch *arch) | |
148 | { | |
08106042 | 149 | m68gc11_gdbarch_tdep *tdep = gdbarch_tdep<m68gc11_gdbarch_tdep> (arch); |
345bd07c SM |
150 | return tdep->stack_correction; |
151 | } | |
152 | ||
153 | static int | |
154 | use_page_register (gdbarch *arch) | |
155 | { | |
08106042 | 156 | m68gc11_gdbarch_tdep *tdep = gdbarch_tdep<m68gc11_gdbarch_tdep> (arch); |
345bd07c SM |
157 | return tdep->stack_correction; |
158 | } | |
5d1a66bd | 159 | |
1ea653ae SC |
160 | struct m68hc11_unwind_cache |
161 | { | |
162 | /* The previous frame's inner most stack address. Used as this | |
163 | frame ID's stack_addr. */ | |
164 | CORE_ADDR prev_sp; | |
165 | /* The frame's base, optionally used by the high-level debug info. */ | |
166 | CORE_ADDR base; | |
167 | CORE_ADDR pc; | |
168 | int size; | |
169 | int prologue_type; | |
170 | CORE_ADDR return_pc; | |
171 | CORE_ADDR sp_offset; | |
172 | int frameless; | |
173 | enum insn_return_kind return_kind; | |
174 | ||
175 | /* Table indicating the location of each and every register. */ | |
098caef4 | 176 | trad_frame_saved_reg *saved_regs; |
1ea653ae SC |
177 | }; |
178 | ||
82c230c2 SC |
179 | /* Table of registers for 68HC11. This includes the hard registers |
180 | and the soft registers used by GCC. */ | |
a121b7c1 | 181 | static const char * |
82c230c2 SC |
182 | m68hc11_register_names[] = |
183 | { | |
184 | "x", "d", "y", "sp", "pc", "a", "b", | |
5706502a | 185 | "ccr", "page", "frame","tmp", "zs", "xy", 0, |
82c230c2 SC |
186 | "d1", "d2", "d3", "d4", "d5", "d6", "d7", |
187 | "d8", "d9", "d10", "d11", "d12", "d13", "d14", | |
188 | "d15", "d16", "d17", "d18", "d19", "d20", "d21", | |
189 | "d22", "d23", "d24", "d25", "d26", "d27", "d28", | |
190 | "d29", "d30", "d31", "d32" | |
191 | }; | |
78073dd8 | 192 | |
82c230c2 SC |
193 | struct m68hc11_soft_reg |
194 | { | |
195 | const char *name; | |
196 | CORE_ADDR addr; | |
197 | }; | |
78073dd8 | 198 | |
82c230c2 | 199 | static struct m68hc11_soft_reg soft_regs[M68HC11_ALL_REGS]; |
78073dd8 | 200 | |
82c230c2 | 201 | #define M68HC11_FP_ADDR soft_regs[SOFT_FP_REGNUM].addr |
78073dd8 | 202 | |
82c230c2 SC |
203 | static int soft_min_addr; |
204 | static int soft_max_addr; | |
205 | static int soft_reg_initialized = 0; | |
78073dd8 | 206 | |
82c230c2 SC |
207 | /* Look in the symbol table for the address of a pseudo register |
208 | in memory. If we don't find it, pretend the register is not used | |
209 | and not available. */ | |
210 | static void | |
211 | m68hc11_get_register_info (struct m68hc11_soft_reg *reg, const char *name) | |
212 | { | |
3b7344d5 | 213 | struct bound_minimal_symbol msymbol; |
78073dd8 | 214 | |
82c230c2 | 215 | msymbol = lookup_minimal_symbol (name, NULL, NULL); |
3b7344d5 | 216 | if (msymbol.minsym) |
82c230c2 | 217 | { |
4aeddc50 | 218 | reg->addr = msymbol.value_address (); |
82c230c2 SC |
219 | reg->name = xstrdup (name); |
220 | ||
221 | /* Keep track of the address range for soft registers. */ | |
222 | if (reg->addr < (CORE_ADDR) soft_min_addr) | |
dda83cd7 | 223 | soft_min_addr = reg->addr; |
82c230c2 | 224 | if (reg->addr > (CORE_ADDR) soft_max_addr) |
dda83cd7 | 225 | soft_max_addr = reg->addr; |
82c230c2 SC |
226 | } |
227 | else | |
228 | { | |
229 | reg->name = 0; | |
230 | reg->addr = 0; | |
231 | } | |
232 | } | |
78073dd8 | 233 | |
82c230c2 SC |
234 | /* Initialize the table of soft register addresses according |
235 | to the symbol table. */ | |
236 | static void | |
237 | m68hc11_initialize_register_info (void) | |
238 | { | |
239 | int i; | |
78073dd8 | 240 | |
82c230c2 SC |
241 | if (soft_reg_initialized) |
242 | return; | |
243 | ||
244 | soft_min_addr = INT_MAX; | |
245 | soft_max_addr = 0; | |
246 | for (i = 0; i < M68HC11_ALL_REGS; i++) | |
247 | { | |
248 | soft_regs[i].name = 0; | |
249 | } | |
250 | ||
251 | m68hc11_get_register_info (&soft_regs[SOFT_FP_REGNUM], "_.frame"); | |
252 | m68hc11_get_register_info (&soft_regs[SOFT_TMP_REGNUM], "_.tmp"); | |
253 | m68hc11_get_register_info (&soft_regs[SOFT_ZS_REGNUM], "_.z"); | |
254 | soft_regs[SOFT_Z_REGNUM] = soft_regs[SOFT_ZS_REGNUM]; | |
255 | m68hc11_get_register_info (&soft_regs[SOFT_XY_REGNUM], "_.xy"); | |
78073dd8 | 256 | |
82c230c2 SC |
257 | for (i = SOFT_D1_REGNUM; i < M68HC11_MAX_SOFT_REGS; i++) |
258 | { | |
259 | char buf[10]; | |
78073dd8 | 260 | |
08850b56 | 261 | xsnprintf (buf, sizeof (buf), "_.d%d", i - SOFT_D1_REGNUM + 1); |
82c230c2 SC |
262 | m68hc11_get_register_info (&soft_regs[i], buf); |
263 | } | |
78073dd8 | 264 | |
82c230c2 | 265 | if (soft_regs[SOFT_FP_REGNUM].name == 0) |
8a3fe4f8 AC |
266 | warning (_("No frame soft register found in the symbol table.\n" |
267 | "Stack backtrace will not work.")); | |
82c230c2 SC |
268 | soft_reg_initialized = 1; |
269 | } | |
78073dd8 | 270 | |
82c230c2 SC |
271 | /* Given an address in memory, return the soft register number if |
272 | that address corresponds to a soft register. Returns -1 if not. */ | |
273 | static int | |
274 | m68hc11_which_soft_register (CORE_ADDR addr) | |
275 | { | |
276 | int i; | |
277 | ||
278 | if (addr < soft_min_addr || addr > soft_max_addr) | |
279 | return -1; | |
280 | ||
281 | for (i = SOFT_FP_REGNUM; i < M68HC11_ALL_REGS; i++) | |
282 | { | |
283 | if (soft_regs[i].name && soft_regs[i].addr == addr) | |
dda83cd7 | 284 | return i; |
82c230c2 SC |
285 | } |
286 | return -1; | |
287 | } | |
78073dd8 | 288 | |
82c230c2 SC |
289 | /* Fetch a pseudo register. The 68hc11 soft registers are treated like |
290 | pseudo registers. They are located in memory. Translate the register | |
291 | fetch into a memory read. */ | |
05d1431c | 292 | static enum register_status |
46ce284d | 293 | m68hc11_pseudo_register_read (struct gdbarch *gdbarch, |
849d0ba8 | 294 | readable_regcache *regcache, |
ff1e98b9 | 295 | int regno, gdb_byte *buf) |
82c230c2 | 296 | { |
e17a4113 UW |
297 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
298 | ||
548bcbec SC |
299 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
300 | addressing mode. */ | |
301 | if (regno == M68HC12_HARD_PC_REGNUM) | |
302 | { | |
4db73d49 | 303 | ULONGEST pc; |
df4df182 | 304 | const int regsize = 4; |
05d1431c | 305 | enum register_status status; |
548bcbec | 306 | |
11f57cb6 | 307 | status = regcache->cooked_read (HARD_PC_REGNUM, &pc); |
05d1431c PA |
308 | if (status != REG_VALID) |
309 | return status; | |
548bcbec | 310 | if (pc >= 0x8000 && pc < 0xc000) |
dda83cd7 SM |
311 | { |
312 | ULONGEST page; | |
4db73d49 | 313 | |
11f57cb6 | 314 | regcache->cooked_read (HARD_PAGE_REGNUM, &page); |
dda83cd7 SM |
315 | pc -= 0x8000; |
316 | pc += (page << 14); | |
317 | pc += 0x1000000; | |
318 | } | |
e17a4113 | 319 | store_unsigned_integer (buf, regsize, byte_order, pc); |
05d1431c | 320 | return REG_VALID; |
548bcbec SC |
321 | } |
322 | ||
82c230c2 SC |
323 | m68hc11_initialize_register_info (); |
324 | ||
325 | /* Fetch a soft register: translate into a memory read. */ | |
326 | if (soft_regs[regno].name) | |
327 | { | |
328 | target_read_memory (soft_regs[regno].addr, buf, 2); | |
329 | } | |
330 | else | |
331 | { | |
332 | memset (buf, 0, 2); | |
333 | } | |
05d1431c PA |
334 | |
335 | return REG_VALID; | |
82c230c2 | 336 | } |
78073dd8 | 337 | |
82c230c2 SC |
338 | /* Store a pseudo register. Translate the register store |
339 | into a memory write. */ | |
340 | static void | |
46ce284d AC |
341 | m68hc11_pseudo_register_write (struct gdbarch *gdbarch, |
342 | struct regcache *regcache, | |
ff1e98b9 | 343 | int regno, const gdb_byte *buf) |
82c230c2 | 344 | { |
e17a4113 UW |
345 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
346 | ||
548bcbec SC |
347 | /* The PC is a pseudo reg only for 68HC12 with the memory bank |
348 | addressing mode. */ | |
349 | if (regno == M68HC12_HARD_PC_REGNUM) | |
350 | { | |
df4df182 | 351 | const int regsize = 4; |
224c3ddb | 352 | gdb_byte *tmp = (gdb_byte *) alloca (regsize); |
548bcbec SC |
353 | CORE_ADDR pc; |
354 | ||
355 | memcpy (tmp, buf, regsize); | |
e17a4113 | 356 | pc = extract_unsigned_integer (tmp, regsize, byte_order); |
548bcbec | 357 | if (pc >= 0x1000000) |
dda83cd7 SM |
358 | { |
359 | pc -= 0x1000000; | |
360 | regcache_cooked_write_unsigned (regcache, HARD_PAGE_REGNUM, | |
361 | (pc >> 14) & 0x0ff); | |
362 | pc &= 0x03fff; | |
363 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, | |
364 | pc + 0x8000); | |
365 | } | |
548bcbec | 366 | else |
dda83cd7 | 367 | regcache_cooked_write_unsigned (regcache, HARD_PC_REGNUM, pc); |
548bcbec SC |
368 | return; |
369 | } | |
370 | ||
82c230c2 | 371 | m68hc11_initialize_register_info (); |
78073dd8 | 372 | |
82c230c2 SC |
373 | /* Store a soft register: translate into a memory write. */ |
374 | if (soft_regs[regno].name) | |
375 | { | |
46ce284d | 376 | const int regsize = 2; |
224c3ddb | 377 | gdb_byte *tmp = (gdb_byte *) alloca (regsize); |
46ce284d AC |
378 | memcpy (tmp, buf, regsize); |
379 | target_write_memory (soft_regs[regno].addr, tmp, regsize); | |
82c230c2 SC |
380 | } |
381 | } | |
78073dd8 | 382 | |
fa88f677 | 383 | static const char * |
d93859e2 | 384 | m68hc11_register_name (struct gdbarch *gdbarch, int reg_nr) |
78073dd8 | 385 | { |
345bd07c | 386 | if (reg_nr == M68HC12_HARD_PC_REGNUM && use_page_register (gdbarch)) |
548bcbec | 387 | return "pc"; |
345bd07c SM |
388 | |
389 | if (reg_nr == HARD_PC_REGNUM && use_page_register (gdbarch)) | |
548bcbec | 390 | return "ppc"; |
345bd07c | 391 | |
82c230c2 | 392 | if (reg_nr >= M68HC11_ALL_REGS) |
9b9e61c7 | 393 | return ""; |
82c230c2 | 394 | |
65760afb SC |
395 | m68hc11_initialize_register_info (); |
396 | ||
82c230c2 SC |
397 | /* If we don't know the address of a soft register, pretend it |
398 | does not exist. */ | |
399 | if (reg_nr > M68HC11_LAST_HARD_REG && soft_regs[reg_nr].name == 0) | |
9a972b54 | 400 | return ""; |
345bd07c | 401 | |
82c230c2 SC |
402 | return m68hc11_register_names[reg_nr]; |
403 | } | |
78073dd8 | 404 | |
04180708 | 405 | constexpr gdb_byte m68hc11_break_insn[] = {0x0}; |
78073dd8 | 406 | |
04180708 | 407 | typedef BP_MANIPULATION (m68hc11_break_insn) m68hc11_breakpoint; |
908f682f | 408 | \f |
025bb325 | 409 | /* 68HC11 & 68HC12 prologue analysis. */ |
908f682f | 410 | |
908f682f SC |
411 | #define MAX_CODES 12 |
412 | ||
413 | /* 68HC11 opcodes. */ | |
414 | #undef M6811_OP_PAGE2 | |
b94a41a1 SC |
415 | #define M6811_OP_PAGE2 (0x18) |
416 | #define M6811_OP_LDX (0xde) | |
417 | #define M6811_OP_LDX_EXT (0xfe) | |
418 | #define M6811_OP_PSHX (0x3c) | |
419 | #define M6811_OP_STS (0x9f) | |
420 | #define M6811_OP_STS_EXT (0xbf) | |
421 | #define M6811_OP_TSX (0x30) | |
422 | #define M6811_OP_XGDX (0x8f) | |
423 | #define M6811_OP_ADDD (0xc3) | |
424 | #define M6811_OP_TXS (0x35) | |
425 | #define M6811_OP_DES (0x34) | |
908f682f SC |
426 | |
427 | /* 68HC12 opcodes. */ | |
b94a41a1 SC |
428 | #define M6812_OP_PAGE2 (0x18) |
429 | #define M6812_OP_MOVW (0x01) | |
430 | #define M6812_PB_PSHW (0xae) | |
431 | #define M6812_OP_STS (0x5f) | |
432 | #define M6812_OP_STS_EXT (0x7f) | |
433 | #define M6812_OP_LEAS (0x1b) | |
434 | #define M6812_OP_PSHX (0x34) | |
435 | #define M6812_OP_PSHY (0x35) | |
908f682f SC |
436 | |
437 | /* Operand extraction. */ | |
438 | #define OP_DIRECT (0x100) /* 8-byte direct addressing. */ | |
439 | #define OP_IMM_LOW (0x200) /* Low part of 16-bit constant/address. */ | |
440 | #define OP_IMM_HIGH (0x300) /* High part of 16-bit constant/address. */ | |
441 | #define OP_PBYTE (0x400) /* 68HC12 indexed operand. */ | |
442 | ||
443 | /* Identification of the sequence. */ | |
444 | enum m6811_seq_type | |
445 | { | |
446 | P_LAST = 0, | |
447 | P_SAVE_REG, /* Save a register on the stack. */ | |
448 | P_SET_FRAME, /* Setup the frame pointer. */ | |
449 | P_LOCAL_1, /* Allocate 1 byte for locals. */ | |
450 | P_LOCAL_2, /* Allocate 2 bytes for locals. */ | |
451 | P_LOCAL_N /* Allocate N bytes for locals. */ | |
452 | }; | |
453 | ||
454 | struct insn_sequence { | |
455 | enum m6811_seq_type type; | |
456 | unsigned length; | |
457 | unsigned short code[MAX_CODES]; | |
458 | }; | |
459 | ||
460 | /* Sequence of instructions in the 68HC11 function prologue. */ | |
461 | static struct insn_sequence m6811_prologue[] = { | |
462 | /* Sequences to save a soft-register. */ | |
463 | { P_SAVE_REG, 3, { M6811_OP_LDX, OP_DIRECT, | |
dda83cd7 | 464 | M6811_OP_PSHX } }, |
908f682f | 465 | { P_SAVE_REG, 5, { M6811_OP_PAGE2, M6811_OP_LDX, OP_DIRECT, |
dda83cd7 | 466 | M6811_OP_PAGE2, M6811_OP_PSHX } }, |
b94a41a1 | 467 | { P_SAVE_REG, 4, { M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, |
dda83cd7 | 468 | M6811_OP_PSHX } }, |
b94a41a1 | 469 | { P_SAVE_REG, 6, { M6811_OP_PAGE2, M6811_OP_LDX_EXT, OP_IMM_HIGH, OP_IMM_LOW, |
dda83cd7 | 470 | M6811_OP_PAGE2, M6811_OP_PSHX } }, |
908f682f SC |
471 | |
472 | /* Sequences to allocate local variables. */ | |
473 | { P_LOCAL_N, 7, { M6811_OP_TSX, | |
dda83cd7 SM |
474 | M6811_OP_XGDX, |
475 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
476 | M6811_OP_XGDX, | |
477 | M6811_OP_TXS } }, | |
908f682f | 478 | { P_LOCAL_N, 11, { M6811_OP_PAGE2, M6811_OP_TSX, |
dda83cd7 SM |
479 | M6811_OP_PAGE2, M6811_OP_XGDX, |
480 | M6811_OP_ADDD, OP_IMM_HIGH, OP_IMM_LOW, | |
481 | M6811_OP_PAGE2, M6811_OP_XGDX, | |
482 | M6811_OP_PAGE2, M6811_OP_TXS } }, | |
908f682f SC |
483 | { P_LOCAL_1, 1, { M6811_OP_DES } }, |
484 | { P_LOCAL_2, 1, { M6811_OP_PSHX } }, | |
485 | { P_LOCAL_2, 2, { M6811_OP_PAGE2, M6811_OP_PSHX } }, | |
486 | ||
487 | /* Initialize the frame pointer. */ | |
488 | { P_SET_FRAME, 2, { M6811_OP_STS, OP_DIRECT } }, | |
b94a41a1 | 489 | { P_SET_FRAME, 3, { M6811_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, |
908f682f SC |
490 | { P_LAST, 0, { 0 } } |
491 | }; | |
492 | ||
493 | ||
494 | /* Sequence of instructions in the 68HC12 function prologue. */ | |
495 | static struct insn_sequence m6812_prologue[] = { | |
496 | { P_SAVE_REG, 5, { M6812_OP_PAGE2, M6812_OP_MOVW, M6812_PB_PSHW, | |
dda83cd7 | 497 | OP_IMM_HIGH, OP_IMM_LOW } }, |
b94a41a1 SC |
498 | { P_SET_FRAME, 2, { M6812_OP_STS, OP_DIRECT } }, |
499 | { P_SET_FRAME, 3, { M6812_OP_STS_EXT, OP_IMM_HIGH, OP_IMM_LOW } }, | |
908f682f | 500 | { P_LOCAL_N, 2, { M6812_OP_LEAS, OP_PBYTE } }, |
ffe1f3ee SC |
501 | { P_LOCAL_2, 1, { M6812_OP_PSHX } }, |
502 | { P_LOCAL_2, 1, { M6812_OP_PSHY } }, | |
908f682f SC |
503 | { P_LAST, 0 } |
504 | }; | |
505 | ||
506 | ||
507 | /* Analyze the sequence of instructions starting at the given address. | |
508 | Returns a pointer to the sequence when it is recognized and | |
c8a7f6ac | 509 | the optional value (constant/address) associated with it. */ |
908f682f | 510 | static struct insn_sequence * |
e17a4113 UW |
511 | m68hc11_analyze_instruction (struct gdbarch *gdbarch, |
512 | struct insn_sequence *seq, CORE_ADDR pc, | |
dda83cd7 | 513 | CORE_ADDR *val) |
908f682f | 514 | { |
e17a4113 | 515 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
908f682f SC |
516 | unsigned char buffer[MAX_CODES]; |
517 | unsigned bufsize; | |
518 | unsigned j; | |
519 | CORE_ADDR cur_val; | |
520 | short v = 0; | |
521 | ||
522 | bufsize = 0; | |
523 | for (; seq->type != P_LAST; seq++) | |
524 | { | |
525 | cur_val = 0; | |
526 | for (j = 0; j < seq->length; j++) | |
dda83cd7 SM |
527 | { |
528 | if (bufsize < j + 1) | |
529 | { | |
530 | buffer[bufsize] = read_memory_unsigned_integer (pc + bufsize, | |
531 | 1, byte_order); | |
532 | bufsize++; | |
533 | } | |
534 | /* Continue while we match the opcode. */ | |
535 | if (seq->code[j] == buffer[j]) | |
536 | continue; | |
537 | ||
538 | if ((seq->code[j] & 0xf00) == 0) | |
539 | break; | |
540 | ||
541 | /* Extract a sequence parameter (address or constant). */ | |
542 | switch (seq->code[j]) | |
543 | { | |
544 | case OP_DIRECT: | |
545 | cur_val = (CORE_ADDR) buffer[j]; | |
546 | break; | |
547 | ||
548 | case OP_IMM_HIGH: | |
549 | cur_val = cur_val & 0x0ff; | |
550 | cur_val |= (buffer[j] << 8); | |
551 | break; | |
552 | ||
553 | case OP_IMM_LOW: | |
554 | cur_val &= 0x0ff00; | |
555 | cur_val |= buffer[j]; | |
556 | break; | |
557 | ||
558 | case OP_PBYTE: | |
559 | if ((buffer[j] & 0xE0) == 0x80) | |
560 | { | |
561 | v = buffer[j] & 0x1f; | |
562 | if (v & 0x10) | |
563 | v |= 0xfff0; | |
564 | } | |
565 | else if ((buffer[j] & 0xfe) == 0xf0) | |
566 | { | |
567 | v = read_memory_unsigned_integer (pc + j + 1, 1, byte_order); | |
568 | if (buffer[j] & 1) | |
569 | v |= 0xff00; | |
570 | } | |
571 | else if (buffer[j] == 0xf2) | |
572 | { | |
573 | v = read_memory_unsigned_integer (pc + j + 1, 2, byte_order); | |
574 | } | |
575 | cur_val = v; | |
576 | break; | |
577 | } | |
578 | } | |
908f682f SC |
579 | |
580 | /* We have a full match. */ | |
581 | if (j == seq->length) | |
dda83cd7 SM |
582 | { |
583 | *val = cur_val; | |
584 | return seq; | |
585 | } | |
908f682f SC |
586 | } |
587 | return 0; | |
588 | } | |
589 | ||
7df11f59 SC |
590 | /* Return the instruction that the function at the PC is using. */ |
591 | static enum insn_return_kind | |
592 | m68hc11_get_return_insn (CORE_ADDR pc) | |
593 | { | |
7cbd4a93 | 594 | struct bound_minimal_symbol sym; |
7df11f59 SC |
595 | |
596 | /* A flag indicating that this is a STO_M68HC12_FAR or STO_M68HC12_INTERRUPT | |
597 | function is stored by elfread.c in the high bit of the info field. | |
598 | Use this to decide which instruction the function uses to return. */ | |
599 | sym = lookup_minimal_symbol_by_pc (pc); | |
7cbd4a93 | 600 | if (sym.minsym == 0) |
7df11f59 SC |
601 | return RETURN_RTS; |
602 | ||
7cbd4a93 | 603 | if (MSYMBOL_IS_RTC (sym.minsym)) |
7df11f59 | 604 | return RETURN_RTC; |
7cbd4a93 | 605 | else if (MSYMBOL_IS_RTI (sym.minsym)) |
7df11f59 SC |
606 | return RETURN_RTI; |
607 | else | |
608 | return RETURN_RTS; | |
609 | } | |
610 | ||
78073dd8 AC |
611 | /* Analyze the function prologue to find some information |
612 | about the function: | |
613 | - the PC of the first line (for m68hc11_skip_prologue) | |
614 | - the offset of the previous frame saved address (from current frame) | |
615 | - the soft registers which are pushed. */ | |
1ea653ae | 616 | static CORE_ADDR |
be8626e0 MD |
617 | m68hc11_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, |
618 | CORE_ADDR current_pc, struct m68hc11_unwind_cache *info) | |
78073dd8 | 619 | { |
1ea653ae | 620 | LONGEST save_addr; |
78073dd8 | 621 | CORE_ADDR func_end; |
78073dd8 AC |
622 | int size; |
623 | int found_frame_point; | |
82c230c2 | 624 | int saved_reg; |
908f682f SC |
625 | int done = 0; |
626 | struct insn_sequence *seq_table; | |
1ea653ae SC |
627 | |
628 | info->size = 0; | |
629 | info->sp_offset = 0; | |
630 | if (pc >= current_pc) | |
631 | return current_pc; | |
632 | ||
78073dd8 AC |
633 | size = 0; |
634 | ||
82c230c2 | 635 | m68hc11_initialize_register_info (); |
1ea653ae | 636 | if (pc == 0) |
78073dd8 | 637 | { |
1ea653ae SC |
638 | info->size = 0; |
639 | return pc; | |
78073dd8 AC |
640 | } |
641 | ||
08106042 | 642 | m68gc11_gdbarch_tdep *tdep = gdbarch_tdep<m68gc11_gdbarch_tdep> (gdbarch); |
345bd07c | 643 | seq_table = tdep->prologue; |
908f682f | 644 | |
78073dd8 AC |
645 | /* The 68hc11 stack is as follows: |
646 | ||
647 | ||
648 | | | | |
649 | +-----------+ | |
650 | | | | |
651 | | args | | |
652 | | | | |
653 | +-----------+ | |
654 | | PC-return | | |
655 | +-----------+ | |
656 | | Old frame | | |
657 | +-----------+ | |
658 | | | | |
659 | | Locals | | |
660 | | | | |
661 | +-----------+ <--- current frame | |
662 | | | | |
663 | ||
664 | With most processors (like 68K) the previous frame can be computed | |
665 | easily because it is always at a fixed offset (see link/unlink). | |
666 | That is, locals are accessed with negative offsets, arguments are | |
667 | accessed with positive ones. Since 68hc11 only supports offsets | |
668 | in the range [0..255], the frame is defined at the bottom of | |
669 | locals (see picture). | |
670 | ||
671 | The purpose of the analysis made here is to find out the size | |
672 | of locals in this function. An alternative to this is to use | |
673 | DWARF2 info. This would be better but I don't know how to | |
674 | access dwarf2 debug from this function. | |
675 | ||
676 | Walk from the function entry point to the point where we save | |
677 | the frame. While walking instructions, compute the size of bytes | |
678 | which are pushed. This gives us the index to access the previous | |
679 | frame. | |
680 | ||
681 | We limit the search to 128 bytes so that the algorithm is bounded | |
682 | in case of random and wrong code. We also stop and abort if | |
683 | we find an instruction which is not supposed to appear in the | |
025bb325 MS |
684 | prologue (as generated by gcc 2.95, 2.96). */ |
685 | ||
78073dd8 | 686 | func_end = pc + 128; |
78073dd8 | 687 | found_frame_point = 0; |
1ea653ae SC |
688 | info->size = 0; |
689 | save_addr = 0; | |
908f682f | 690 | while (!done && pc + 2 < func_end) |
78073dd8 | 691 | { |
908f682f SC |
692 | struct insn_sequence *seq; |
693 | CORE_ADDR val; | |
1ea653ae | 694 | |
e17a4113 | 695 | seq = m68hc11_analyze_instruction (gdbarch, seq_table, pc, &val); |
908f682f | 696 | if (seq == 0) |
dda83cd7 | 697 | break; |
78073dd8 | 698 | |
c8a7f6ac | 699 | /* If we are within the instruction group, we can't advance the |
dda83cd7 SM |
700 | pc nor the stack offset. Otherwise the caller's stack computed |
701 | from the current stack can be wrong. */ | |
c8a7f6ac | 702 | if (pc + seq->length > current_pc) |
dda83cd7 | 703 | break; |
c8a7f6ac SC |
704 | |
705 | pc = pc + seq->length; | |
908f682f | 706 | if (seq->type == P_SAVE_REG) |
dda83cd7 SM |
707 | { |
708 | if (found_frame_point) | |
709 | { | |
710 | saved_reg = m68hc11_which_soft_register (val); | |
711 | if (saved_reg < 0) | |
712 | break; | |
713 | ||
714 | save_addr -= 2; | |
715 | if (info->saved_regs) | |
098caef4 | 716 | info->saved_regs[saved_reg].set_addr (save_addr); |
dda83cd7 SM |
717 | } |
718 | else | |
719 | { | |
720 | size += 2; | |
721 | } | |
722 | } | |
908f682f | 723 | else if (seq->type == P_SET_FRAME) |
dda83cd7 SM |
724 | { |
725 | found_frame_point = 1; | |
726 | info->size = size; | |
727 | } | |
908f682f | 728 | else if (seq->type == P_LOCAL_1) |
dda83cd7 SM |
729 | { |
730 | size += 1; | |
731 | } | |
908f682f | 732 | else if (seq->type == P_LOCAL_2) |
dda83cd7 SM |
733 | { |
734 | size += 2; | |
735 | } | |
908f682f | 736 | else if (seq->type == P_LOCAL_N) |
dda83cd7 SM |
737 | { |
738 | /* Stack pointer is decremented for the allocation. */ | |
739 | if (val & 0x8000) | |
740 | size -= (int) (val) | 0xffff0000; | |
741 | else | |
742 | size -= val; | |
743 | } | |
78073dd8 | 744 | } |
1ea653ae SC |
745 | if (found_frame_point == 0) |
746 | info->sp_offset = size; | |
747 | else | |
748 | info->sp_offset = -1; | |
749 | return pc; | |
78073dd8 AC |
750 | } |
751 | ||
82c230c2 | 752 | static CORE_ADDR |
6093d2eb | 753 | m68hc11_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) |
78073dd8 AC |
754 | { |
755 | CORE_ADDR func_addr, func_end; | |
756 | struct symtab_and_line sal; | |
1ea653ae | 757 | struct m68hc11_unwind_cache tmp_cache = { 0 }; |
78073dd8 | 758 | |
82c230c2 SC |
759 | /* If we have line debugging information, then the end of the |
760 | prologue should be the first assembly instruction of the | |
78073dd8 AC |
761 | first source line. */ |
762 | if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) | |
763 | { | |
764 | sal = find_pc_line (func_addr, 0); | |
765 | if (sal.end && sal.end < func_end) | |
766 | return sal.end; | |
767 | } | |
768 | ||
be8626e0 | 769 | pc = m68hc11_scan_prologue (gdbarch, pc, (CORE_ADDR) -1, &tmp_cache); |
78073dd8 AC |
770 | return pc; |
771 | } | |
772 | ||
1ea653ae SC |
773 | /* Put here the code to store, into fi->saved_regs, the addresses of |
774 | the saved registers of frame described by FRAME_INFO. This | |
775 | includes special registers such as pc and fp saved in special ways | |
776 | in the stack frame. sp is even more special: the address we return | |
025bb325 | 777 | for it IS the sp for the next frame. */ |
1ea653ae | 778 | |
63807e1d | 779 | static struct m68hc11_unwind_cache * |
bd2b40ac | 780 | m68hc11_frame_unwind_cache (frame_info_ptr this_frame, |
dda83cd7 | 781 | void **this_prologue_cache) |
1ea653ae | 782 | { |
94afd7a6 | 783 | struct gdbarch *gdbarch = get_frame_arch (this_frame); |
1ea653ae SC |
784 | ULONGEST prev_sp; |
785 | ULONGEST this_base; | |
786 | struct m68hc11_unwind_cache *info; | |
787 | CORE_ADDR current_pc; | |
788 | int i; | |
789 | ||
790 | if ((*this_prologue_cache)) | |
9a3c8263 | 791 | return (struct m68hc11_unwind_cache *) (*this_prologue_cache); |
1ea653ae SC |
792 | |
793 | info = FRAME_OBSTACK_ZALLOC (struct m68hc11_unwind_cache); | |
794 | (*this_prologue_cache) = info; | |
94afd7a6 | 795 | info->saved_regs = trad_frame_alloc_saved_regs (this_frame); |
1ea653ae | 796 | |
94afd7a6 | 797 | info->pc = get_frame_func (this_frame); |
1ea653ae SC |
798 | |
799 | info->size = 0; | |
800 | info->return_kind = m68hc11_get_return_insn (info->pc); | |
801 | ||
802 | /* The SP was moved to the FP. This indicates that a new frame | |
803 | was created. Get THIS frame's FP value by unwinding it from | |
804 | the next frame. */ | |
94afd7a6 | 805 | this_base = get_frame_register_unsigned (this_frame, SOFT_FP_REGNUM); |
1ea653ae SC |
806 | if (this_base == 0) |
807 | { | |
808 | info->base = 0; | |
809 | return info; | |
810 | } | |
811 | ||
94afd7a6 | 812 | current_pc = get_frame_pc (this_frame); |
1ea653ae | 813 | if (info->pc != 0) |
be8626e0 | 814 | m68hc11_scan_prologue (gdbarch, info->pc, current_pc, info); |
1ea653ae | 815 | |
098caef4 | 816 | info->saved_regs[HARD_PC_REGNUM].set_addr (info->size); |
1ea653ae SC |
817 | |
818 | if (info->sp_offset != (CORE_ADDR) -1) | |
819 | { | |
098caef4 | 820 | info->saved_regs[HARD_PC_REGNUM].set_addr (info->sp_offset); |
94afd7a6 | 821 | this_base = get_frame_register_unsigned (this_frame, HARD_SP_REGNUM); |
1ea653ae | 822 | prev_sp = this_base + info->sp_offset + 2; |
345bd07c | 823 | this_base += stack_correction (gdbarch); |
1ea653ae SC |
824 | } |
825 | else | |
826 | { | |
827 | /* The FP points at the last saved register. Adjust the FP back | |
dda83cd7 | 828 | to before the first saved register giving the SP. */ |
1ea653ae SC |
829 | prev_sp = this_base + info->size + 2; |
830 | ||
345bd07c | 831 | this_base += stack_correction (gdbarch); |
1ea653ae | 832 | if (soft_regs[SOFT_FP_REGNUM].name) |
098caef4 | 833 | info->saved_regs[SOFT_FP_REGNUM].set_addr (info->size - 2); |
1ea653ae SC |
834 | } |
835 | ||
836 | if (info->return_kind == RETURN_RTC) | |
837 | { | |
838 | prev_sp += 1; | |
098caef4 LM |
839 | info->saved_regs[HARD_PAGE_REGNUM].set_addr (info->size); |
840 | info->saved_regs[HARD_PC_REGNUM].set_addr (info->size + 1); | |
1ea653ae SC |
841 | } |
842 | else if (info->return_kind == RETURN_RTI) | |
843 | { | |
844 | prev_sp += 7; | |
098caef4 LM |
845 | info->saved_regs[HARD_CCR_REGNUM].set_addr (info->size); |
846 | info->saved_regs[HARD_D_REGNUM].set_addr (info->size + 1); | |
847 | info->saved_regs[HARD_X_REGNUM].set_addr (info->size + 3); | |
848 | info->saved_regs[HARD_Y_REGNUM].set_addr (info->size + 5); | |
849 | info->saved_regs[HARD_PC_REGNUM].set_addr (info->size + 7); | |
1ea653ae SC |
850 | } |
851 | ||
852 | /* Add 1 here to adjust for the post-decrement nature of the push | |
025bb325 | 853 | instruction. */ |
1ea653ae SC |
854 | info->prev_sp = prev_sp; |
855 | ||
856 | info->base = this_base; | |
857 | ||
858 | /* Adjust all the saved registers so that they contain addresses and not | |
859 | offsets. */ | |
f6efe3f8 | 860 | for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++) |
a9a87d35 | 861 | if (info->saved_regs[i].is_addr ()) |
1ea653ae | 862 | { |
098caef4 | 863 | info->saved_regs[i].set_addr (info->saved_regs[i].addr () + this_base); |
1ea653ae SC |
864 | } |
865 | ||
866 | /* The previous frame's SP needed to be computed. Save the computed | |
867 | value. */ | |
a9a87d35 | 868 | info->saved_regs[HARD_SP_REGNUM].set_value (info->prev_sp); |
1ea653ae SC |
869 | |
870 | return info; | |
871 | } | |
872 | ||
873 | /* Given a GDB frame, determine the address of the calling function's | |
874 | frame. This will be used to create a new GDB frame struct. */ | |
875 | ||
876 | static void | |
bd2b40ac | 877 | m68hc11_frame_this_id (frame_info_ptr this_frame, |
dda83cd7 SM |
878 | void **this_prologue_cache, |
879 | struct frame_id *this_id) | |
1ea653ae SC |
880 | { |
881 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 882 | = m68hc11_frame_unwind_cache (this_frame, this_prologue_cache); |
1ea653ae SC |
883 | CORE_ADDR base; |
884 | CORE_ADDR func; | |
885 | struct frame_id id; | |
886 | ||
887 | /* The FUNC is easy. */ | |
94afd7a6 | 888 | func = get_frame_func (this_frame); |
1ea653ae | 889 | |
1ea653ae SC |
890 | /* Hopefully the prologue analysis either correctly determined the |
891 | frame's base (which is the SP from the previous frame), or set | |
892 | that base to "NULL". */ | |
893 | base = info->prev_sp; | |
894 | if (base == 0) | |
895 | return; | |
896 | ||
897 | id = frame_id_build (base, func); | |
1ea653ae SC |
898 | (*this_id) = id; |
899 | } | |
900 | ||
94afd7a6 | 901 | static struct value * |
bd2b40ac | 902 | m68hc11_frame_prev_register (frame_info_ptr this_frame, |
dda83cd7 | 903 | void **this_prologue_cache, int regnum) |
1ea653ae | 904 | { |
94afd7a6 | 905 | struct value *value; |
1ea653ae | 906 | struct m68hc11_unwind_cache *info |
94afd7a6 | 907 | = m68hc11_frame_unwind_cache (this_frame, this_prologue_cache); |
1ea653ae | 908 | |
94afd7a6 | 909 | value = trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); |
1ea653ae | 910 | |
94afd7a6 UW |
911 | /* Take into account the 68HC12 specific call (PC + page). */ |
912 | if (regnum == HARD_PC_REGNUM | |
913 | && info->return_kind == RETURN_RTC | |
345bd07c | 914 | && use_page_register (get_frame_arch (this_frame))) |
1ea653ae | 915 | { |
94afd7a6 UW |
916 | CORE_ADDR pc = value_as_long (value); |
917 | if (pc >= 0x08000 && pc < 0x0c000) | |
dda83cd7 SM |
918 | { |
919 | CORE_ADDR page; | |
1ea653ae | 920 | |
94afd7a6 | 921 | release_value (value); |
94afd7a6 UW |
922 | |
923 | value = trad_frame_get_prev_register (this_frame, info->saved_regs, | |
924 | HARD_PAGE_REGNUM); | |
925 | page = value_as_long (value); | |
926 | release_value (value); | |
94afd7a6 | 927 | |
dda83cd7 SM |
928 | pc -= 0x08000; |
929 | pc += ((page & 0x0ff) << 14); | |
930 | pc += 0x1000000; | |
94afd7a6 UW |
931 | |
932 | return frame_unwind_got_constant (this_frame, regnum, pc); | |
dda83cd7 | 933 | } |
1ea653ae | 934 | } |
94afd7a6 UW |
935 | |
936 | return value; | |
1ea653ae SC |
937 | } |
938 | ||
939 | static const struct frame_unwind m68hc11_frame_unwind = { | |
a154d838 | 940 | "m68hc11 prologue", |
1ea653ae | 941 | NORMAL_FRAME, |
8fbca658 | 942 | default_frame_unwind_stop_reason, |
1ea653ae | 943 | m68hc11_frame_this_id, |
94afd7a6 UW |
944 | m68hc11_frame_prev_register, |
945 | NULL, | |
946 | default_frame_sniffer | |
1ea653ae SC |
947 | }; |
948 | ||
1ea653ae | 949 | static CORE_ADDR |
bd2b40ac | 950 | m68hc11_frame_base_address (frame_info_ptr this_frame, void **this_cache) |
1ea653ae SC |
951 | { |
952 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 953 | = m68hc11_frame_unwind_cache (this_frame, this_cache); |
1ea653ae SC |
954 | |
955 | return info->base; | |
956 | } | |
957 | ||
958 | static CORE_ADDR | |
bd2b40ac | 959 | m68hc11_frame_args_address (frame_info_ptr this_frame, void **this_cache) |
1ea653ae SC |
960 | { |
961 | CORE_ADDR addr; | |
962 | struct m68hc11_unwind_cache *info | |
94afd7a6 | 963 | = m68hc11_frame_unwind_cache (this_frame, this_cache); |
1ea653ae SC |
964 | |
965 | addr = info->base + info->size; | |
966 | if (info->return_kind == RETURN_RTC) | |
967 | addr += 1; | |
968 | else if (info->return_kind == RETURN_RTI) | |
969 | addr += 7; | |
970 | ||
971 | return addr; | |
972 | } | |
973 | ||
974 | static const struct frame_base m68hc11_frame_base = { | |
975 | &m68hc11_frame_unwind, | |
976 | m68hc11_frame_base_address, | |
977 | m68hc11_frame_base_address, | |
978 | m68hc11_frame_args_address | |
979 | }; | |
980 | ||
94afd7a6 UW |
981 | /* Assuming THIS_FRAME is a dummy, return the frame ID of that dummy |
982 | frame. The frame ID's base needs to match the TOS value saved by | |
983 | save_dummy_frame_tos(), and the PC match the dummy frame's breakpoint. */ | |
1ea653ae SC |
984 | |
985 | static struct frame_id | |
bd2b40ac | 986 | m68hc11_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) |
1ea653ae SC |
987 | { |
988 | ULONGEST tos; | |
94afd7a6 | 989 | CORE_ADDR pc = get_frame_pc (this_frame); |
1ea653ae | 990 | |
94afd7a6 | 991 | tos = get_frame_register_unsigned (this_frame, SOFT_FP_REGNUM); |
1ea653ae SC |
992 | tos += 2; |
993 | return frame_id_build (tos, pc); | |
994 | } | |
78073dd8 | 995 | |
e286caf2 SC |
996 | \f |
997 | /* Get and print the register from the given frame. */ | |
78073dd8 | 998 | static void |
e286caf2 | 999 | m68hc11_print_register (struct gdbarch *gdbarch, struct ui_file *file, |
bd2b40ac | 1000 | frame_info_ptr frame, int regno) |
78073dd8 | 1001 | { |
e286caf2 SC |
1002 | LONGEST rval; |
1003 | ||
1004 | if (regno == HARD_PC_REGNUM || regno == HARD_SP_REGNUM | |
1005 | || regno == SOFT_FP_REGNUM || regno == M68HC12_HARD_PC_REGNUM) | |
7f5f525d | 1006 | rval = get_frame_register_unsigned (frame, regno); |
e286caf2 | 1007 | else |
7f5f525d | 1008 | rval = get_frame_register_signed (frame, regno); |
e286caf2 SC |
1009 | |
1010 | if (regno == HARD_A_REGNUM || regno == HARD_B_REGNUM | |
1011 | || regno == HARD_CCR_REGNUM || regno == HARD_PAGE_REGNUM) | |
7df11f59 | 1012 | { |
6cb06a8c | 1013 | gdb_printf (file, "0x%02x ", (unsigned char) rval); |
e286caf2 | 1014 | if (regno != HARD_CCR_REGNUM) |
dda83cd7 | 1015 | print_longest (file, 'd', 1, rval); |
7df11f59 | 1016 | } |
e286caf2 SC |
1017 | else |
1018 | { | |
345bd07c | 1019 | m68gc11_gdbarch_tdep *tdep |
08106042 | 1020 | = gdbarch_tdep<m68gc11_gdbarch_tdep> (gdbarch); |
345bd07c SM |
1021 | |
1022 | if (regno == HARD_PC_REGNUM && tdep->use_page_register) | |
dda83cd7 SM |
1023 | { |
1024 | ULONGEST page; | |
7df11f59 | 1025 | |
dda83cd7 | 1026 | page = get_frame_register_unsigned (frame, HARD_PAGE_REGNUM); |
6cb06a8c TT |
1027 | gdb_printf (file, "0x%02x:%04x ", (unsigned) page, |
1028 | (unsigned) rval); | |
dda83cd7 | 1029 | } |
e286caf2 | 1030 | else |
dda83cd7 | 1031 | { |
6cb06a8c | 1032 | gdb_printf (file, "0x%04x ", (unsigned) rval); |
dda83cd7 SM |
1033 | if (regno != HARD_PC_REGNUM && regno != HARD_SP_REGNUM |
1034 | && regno != SOFT_FP_REGNUM && regno != M68HC12_HARD_PC_REGNUM) | |
1035 | print_longest (file, 'd', 1, rval); | |
1036 | } | |
e286caf2 SC |
1037 | } |
1038 | ||
1039 | if (regno == HARD_CCR_REGNUM) | |
78073dd8 | 1040 | { |
e286caf2 SC |
1041 | /* CCR register */ |
1042 | int C, Z, N, V; | |
1043 | unsigned char l = rval & 0xff; | |
1044 | ||
6cb06a8c TT |
1045 | gdb_printf (file, "%c%c%c%c%c%c%c%c ", |
1046 | l & M6811_S_BIT ? 'S' : '-', | |
1047 | l & M6811_X_BIT ? 'X' : '-', | |
1048 | l & M6811_H_BIT ? 'H' : '-', | |
1049 | l & M6811_I_BIT ? 'I' : '-', | |
1050 | l & M6811_N_BIT ? 'N' : '-', | |
1051 | l & M6811_Z_BIT ? 'Z' : '-', | |
1052 | l & M6811_V_BIT ? 'V' : '-', | |
1053 | l & M6811_C_BIT ? 'C' : '-'); | |
e286caf2 SC |
1054 | N = (l & M6811_N_BIT) != 0; |
1055 | Z = (l & M6811_Z_BIT) != 0; | |
1056 | V = (l & M6811_V_BIT) != 0; | |
1057 | C = (l & M6811_C_BIT) != 0; | |
1058 | ||
025bb325 | 1059 | /* Print flags following the h8300. */ |
e286caf2 | 1060 | if ((C | Z) == 0) |
6cb06a8c | 1061 | gdb_printf (file, "u> "); |
e286caf2 | 1062 | else if ((C | Z) == 1) |
6cb06a8c | 1063 | gdb_printf (file, "u<= "); |
e286caf2 | 1064 | else if (C == 0) |
6cb06a8c | 1065 | gdb_printf (file, "u< "); |
e286caf2 SC |
1066 | |
1067 | if (Z == 0) | |
6cb06a8c | 1068 | gdb_printf (file, "!= "); |
e286caf2 | 1069 | else |
6cb06a8c | 1070 | gdb_printf (file, "== "); |
e286caf2 SC |
1071 | |
1072 | if ((N ^ V) == 0) | |
6cb06a8c | 1073 | gdb_printf (file, ">= "); |
e286caf2 | 1074 | else |
6cb06a8c | 1075 | gdb_printf (file, "< "); |
e286caf2 SC |
1076 | |
1077 | if ((Z | (N ^ V)) == 0) | |
6cb06a8c | 1078 | gdb_printf (file, "> "); |
78073dd8 | 1079 | else |
6cb06a8c | 1080 | gdb_printf (file, "<= "); |
78073dd8 | 1081 | } |
e286caf2 SC |
1082 | } |
1083 | ||
1084 | /* Same as 'info reg' but prints the registers in a different way. */ | |
1085 | static void | |
1086 | m68hc11_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, | |
bd2b40ac | 1087 | frame_info_ptr frame, int regno, int cpregs) |
e286caf2 SC |
1088 | { |
1089 | if (regno >= 0) | |
1090 | { | |
1091 | const char *name = gdbarch_register_name (gdbarch, regno); | |
1092 | ||
637b2f86 | 1093 | if (*name == '\0') |
dda83cd7 | 1094 | return; |
e286caf2 | 1095 | |
6cb06a8c | 1096 | gdb_printf (file, "%-10s ", name); |
e286caf2 | 1097 | m68hc11_print_register (gdbarch, file, frame, regno); |
6cb06a8c | 1098 | gdb_printf (file, "\n"); |
e286caf2 SC |
1099 | } |
1100 | else | |
1101 | { | |
1102 | int i, nr; | |
1103 | ||
6cb06a8c | 1104 | gdb_printf (file, "PC="); |
e286caf2 SC |
1105 | m68hc11_print_register (gdbarch, file, frame, HARD_PC_REGNUM); |
1106 | ||
6cb06a8c | 1107 | gdb_printf (file, " SP="); |
e286caf2 SC |
1108 | m68hc11_print_register (gdbarch, file, frame, HARD_SP_REGNUM); |
1109 | ||
6cb06a8c | 1110 | gdb_printf (file, " FP="); |
e286caf2 SC |
1111 | m68hc11_print_register (gdbarch, file, frame, SOFT_FP_REGNUM); |
1112 | ||
6cb06a8c | 1113 | gdb_printf (file, "\nCCR="); |
e286caf2 SC |
1114 | m68hc11_print_register (gdbarch, file, frame, HARD_CCR_REGNUM); |
1115 | ||
6cb06a8c | 1116 | gdb_printf (file, "\nD="); |
e286caf2 SC |
1117 | m68hc11_print_register (gdbarch, file, frame, HARD_D_REGNUM); |
1118 | ||
6cb06a8c | 1119 | gdb_printf (file, " X="); |
e286caf2 SC |
1120 | m68hc11_print_register (gdbarch, file, frame, HARD_X_REGNUM); |
1121 | ||
6cb06a8c | 1122 | gdb_printf (file, " Y="); |
e286caf2 SC |
1123 | m68hc11_print_register (gdbarch, file, frame, HARD_Y_REGNUM); |
1124 | ||
08106042 | 1125 | m68gc11_gdbarch_tdep *tdep = gdbarch_tdep<m68gc11_gdbarch_tdep> (gdbarch); |
345bd07c SM |
1126 | |
1127 | if (tdep->use_page_register) | |
dda83cd7 | 1128 | { |
6cb06a8c | 1129 | gdb_printf (file, "\nPage="); |
dda83cd7 SM |
1130 | m68hc11_print_register (gdbarch, file, frame, HARD_PAGE_REGNUM); |
1131 | } | |
6cb06a8c | 1132 | gdb_printf (file, "\n"); |
e286caf2 SC |
1133 | |
1134 | nr = 0; | |
1135 | for (i = SOFT_D1_REGNUM; i < M68HC11_ALL_REGS; i++) | |
dda83cd7 SM |
1136 | { |
1137 | /* Skip registers which are not defined in the symbol table. */ | |
1138 | if (soft_regs[i].name == 0) | |
1139 | continue; | |
1140 | ||
6cb06a8c | 1141 | gdb_printf (file, "D%d=", i - SOFT_D1_REGNUM + 1); |
dda83cd7 SM |
1142 | m68hc11_print_register (gdbarch, file, frame, i); |
1143 | nr++; | |
1144 | if ((nr % 8) == 7) | |
6cb06a8c | 1145 | gdb_printf (file, "\n"); |
dda83cd7 | 1146 | else |
6cb06a8c | 1147 | gdb_printf (file, " "); |
dda83cd7 | 1148 | } |
e286caf2 | 1149 | if (nr && (nr % 8) != 7) |
6cb06a8c | 1150 | gdb_printf (file, "\n"); |
e286caf2 SC |
1151 | } |
1152 | } | |
1153 | ||
82c230c2 | 1154 | static CORE_ADDR |
7d9b040b | 1155 | m68hc11_push_dummy_call (struct gdbarch *gdbarch, struct value *function, |
dda83cd7 SM |
1156 | struct regcache *regcache, CORE_ADDR bp_addr, |
1157 | int nargs, struct value **args, CORE_ADDR sp, | |
cf84fa6b AH |
1158 | function_call_return_method return_method, |
1159 | CORE_ADDR struct_addr) | |
78073dd8 | 1160 | { |
e17a4113 | 1161 | enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); |
82c230c2 SC |
1162 | int argnum; |
1163 | int first_stack_argnum; | |
82c230c2 | 1164 | struct type *type; |
948f8e3d | 1165 | const gdb_byte *val; |
e362b510 | 1166 | gdb_byte buf[2]; |
82c230c2 | 1167 | |
82c230c2 | 1168 | first_stack_argnum = 0; |
cf84fa6b AH |
1169 | if (return_method == return_method_struct) |
1170 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, struct_addr); | |
82c230c2 SC |
1171 | else if (nargs > 0) |
1172 | { | |
d0c97917 | 1173 | type = args[0]->type (); |
3dc990bf | 1174 | |
82c230c2 | 1175 | /* First argument is passed in D and X registers. */ |
df86565b | 1176 | if (type->length () <= 4) |
dda83cd7 SM |
1177 | { |
1178 | ULONGEST v; | |
3dc990bf | 1179 | |
efaf1ae0 | 1180 | v = extract_unsigned_integer (args[0]->contents ().data (), |
df86565b | 1181 | type->length (), byte_order); |
dda83cd7 SM |
1182 | first_stack_argnum = 1; |
1183 | ||
1184 | regcache_cooked_write_unsigned (regcache, HARD_D_REGNUM, v); | |
df86565b | 1185 | if (type->length () > 2) |
dda83cd7 SM |
1186 | { |
1187 | v >>= 16; | |
1188 | regcache_cooked_write_unsigned (regcache, HARD_X_REGNUM, v); | |
1189 | } | |
1190 | } | |
82c230c2 | 1191 | } |
82c230c2 | 1192 | |
3dc990bf | 1193 | for (argnum = nargs - 1; argnum >= first_stack_argnum; argnum--) |
82c230c2 | 1194 | { |
d0c97917 | 1195 | type = args[argnum]->type (); |
82c230c2 | 1196 | |
df86565b | 1197 | if (type->length () & 1) |
dda83cd7 SM |
1198 | { |
1199 | static gdb_byte zero = 0; | |
22df305e | 1200 | |
dda83cd7 SM |
1201 | sp--; |
1202 | write_memory (sp, &zero, 1); | |
1203 | } | |
efaf1ae0 | 1204 | val = args[argnum]->contents ().data (); |
df86565b SM |
1205 | sp -= type->length (); |
1206 | write_memory (sp, val, type->length ()); | |
82c230c2 | 1207 | } |
3dc990bf SC |
1208 | |
1209 | /* Store return address. */ | |
1210 | sp -= 2; | |
e17a4113 | 1211 | store_unsigned_integer (buf, 2, byte_order, bp_addr); |
3dc990bf SC |
1212 | write_memory (sp, buf, 2); |
1213 | ||
1214 | /* Finally, update the stack pointer... */ | |
345bd07c | 1215 | sp -= stack_correction (gdbarch); |
3dc990bf SC |
1216 | regcache_cooked_write_unsigned (regcache, HARD_SP_REGNUM, sp); |
1217 | ||
1218 | /* ...and fake a frame pointer. */ | |
1219 | regcache_cooked_write_unsigned (regcache, SOFT_FP_REGNUM, sp); | |
1220 | ||
1221 | /* DWARF2/GCC uses the stack address *before* the function call as a | |
1222 | frame's CFA. */ | |
1223 | return sp + 2; | |
78073dd8 AC |
1224 | } |
1225 | ||
1226 | ||
4db73d49 SC |
1227 | /* Return the GDB type object for the "standard" data type |
1228 | of data in register N. */ | |
1229 | ||
82c230c2 | 1230 | static struct type * |
4db73d49 | 1231 | m68hc11_register_type (struct gdbarch *gdbarch, int reg_nr) |
82c230c2 | 1232 | { |
5706502a SC |
1233 | switch (reg_nr) |
1234 | { | |
1235 | case HARD_PAGE_REGNUM: | |
1236 | case HARD_A_REGNUM: | |
1237 | case HARD_B_REGNUM: | |
1238 | case HARD_CCR_REGNUM: | |
df4df182 | 1239 | return builtin_type (gdbarch)->builtin_uint8; |
5706502a | 1240 | |
548bcbec | 1241 | case M68HC12_HARD_PC_REGNUM: |
df4df182 | 1242 | return builtin_type (gdbarch)->builtin_uint32; |
548bcbec | 1243 | |
5706502a | 1244 | default: |
df4df182 | 1245 | return builtin_type (gdbarch)->builtin_uint16; |
5706502a | 1246 | } |
82c230c2 SC |
1247 | } |
1248 | ||
82c230c2 | 1249 | static void |
4db73d49 | 1250 | m68hc11_store_return_value (struct type *type, struct regcache *regcache, |
dda83cd7 | 1251 | const gdb_byte *valbuf) |
82c230c2 | 1252 | { |
22df305e SC |
1253 | int len; |
1254 | ||
df86565b | 1255 | len = type->length (); |
22df305e SC |
1256 | |
1257 | /* First argument is passed in D and X registers. */ | |
4db73d49 | 1258 | if (len <= 2) |
4f0420fd | 1259 | regcache->raw_write_part (HARD_D_REGNUM, 2 - len, len, valbuf); |
4db73d49 | 1260 | else if (len <= 4) |
22df305e | 1261 | { |
4f0420fd | 1262 | regcache->raw_write_part (HARD_X_REGNUM, 4 - len, len - 2, valbuf); |
10eaee5f | 1263 | regcache->raw_write (HARD_D_REGNUM, valbuf + (len - 2)); |
22df305e SC |
1264 | } |
1265 | else | |
8a3fe4f8 | 1266 | error (_("return of value > 4 is not supported.")); |
82c230c2 SC |
1267 | } |
1268 | ||
1269 | ||
ef2b8fcd | 1270 | /* Given a return value in `regcache' with a type `type', |
78073dd8 AC |
1271 | extract and copy its value into `valbuf'. */ |
1272 | ||
82c230c2 | 1273 | static void |
ef2b8fcd | 1274 | m68hc11_extract_return_value (struct type *type, struct regcache *regcache, |
dda83cd7 | 1275 | void *valbuf) |
78073dd8 | 1276 | { |
e362b510 | 1277 | gdb_byte buf[M68HC11_REG_SIZE]; |
ef2b8fcd | 1278 | |
0b883586 | 1279 | regcache->raw_read (HARD_D_REGNUM, buf); |
df86565b | 1280 | switch (type->length ()) |
82c230c2 | 1281 | { |
22df305e | 1282 | case 1: |
ef2b8fcd | 1283 | memcpy (valbuf, buf + 1, 1); |
22df305e | 1284 | break; |
ef2b8fcd | 1285 | |
22df305e | 1286 | case 2: |
ef2b8fcd | 1287 | memcpy (valbuf, buf, 2); |
22df305e | 1288 | break; |
ef2b8fcd | 1289 | |
22df305e | 1290 | case 3: |
ef2b8fcd | 1291 | memcpy ((char*) valbuf + 1, buf, 2); |
0b883586 | 1292 | regcache->raw_read (HARD_X_REGNUM, buf); |
ef2b8fcd | 1293 | memcpy (valbuf, buf + 1, 1); |
22df305e | 1294 | break; |
ef2b8fcd | 1295 | |
22df305e | 1296 | case 4: |
ef2b8fcd | 1297 | memcpy ((char*) valbuf + 2, buf, 2); |
0b883586 | 1298 | regcache->raw_read (HARD_X_REGNUM, buf); |
ef2b8fcd | 1299 | memcpy (valbuf, buf, 2); |
22df305e SC |
1300 | break; |
1301 | ||
1302 | default: | |
8a3fe4f8 | 1303 | error (_("bad size for return value")); |
82c230c2 SC |
1304 | } |
1305 | } | |
1306 | ||
63807e1d | 1307 | static enum return_value_convention |
6a3a010b | 1308 | m68hc11_return_value (struct gdbarch *gdbarch, struct value *function, |
c055b101 CV |
1309 | struct type *valtype, struct regcache *regcache, |
1310 | gdb_byte *readbuf, const gdb_byte *writebuf) | |
82c230c2 | 1311 | { |
78134374 SM |
1312 | if (valtype->code () == TYPE_CODE_STRUCT |
1313 | || valtype->code () == TYPE_CODE_UNION | |
1314 | || valtype->code () == TYPE_CODE_ARRAY | |
df86565b | 1315 | || valtype->length () > 4) |
97092415 AC |
1316 | return RETURN_VALUE_STRUCT_CONVENTION; |
1317 | else | |
1318 | { | |
1319 | if (readbuf != NULL) | |
1320 | m68hc11_extract_return_value (valtype, regcache, readbuf); | |
1321 | if (writebuf != NULL) | |
1322 | m68hc11_store_return_value (valtype, regcache, writebuf); | |
1323 | return RETURN_VALUE_REGISTER_CONVENTION; | |
1324 | } | |
82c230c2 SC |
1325 | } |
1326 | ||
7df11f59 SC |
1327 | /* Test whether the ELF symbol corresponds to a function using rtc or |
1328 | rti to return. */ | |
1329 | ||
1330 | static void | |
1331 | m68hc11_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) | |
1332 | { | |
1333 | unsigned char flags; | |
1334 | ||
1335 | flags = ((elf_symbol_type *)sym)->internal_elf_sym.st_other; | |
1336 | if (flags & STO_M68HC12_FAR) | |
1337 | MSYMBOL_SET_RTC (msym); | |
1338 | if (flags & STO_M68HC12_INTERRUPT) | |
1339 | MSYMBOL_SET_RTI (msym); | |
1340 | } | |
b631436b SC |
1341 | \f |
1342 | ||
1343 | /* 68HC11/68HC12 register groups. | |
1344 | Identify real hard registers and soft registers used by gcc. */ | |
1345 | ||
e7fe1011 AB |
1346 | static const reggroup *m68hc11_soft_reggroup; |
1347 | static const reggroup *m68hc11_hard_reggroup; | |
b631436b SC |
1348 | |
1349 | static void | |
1350 | m68hc11_init_reggroups (void) | |
1351 | { | |
1352 | m68hc11_hard_reggroup = reggroup_new ("hard", USER_REGGROUP); | |
1353 | m68hc11_soft_reggroup = reggroup_new ("soft", USER_REGGROUP); | |
1354 | } | |
1355 | ||
1356 | static void | |
1357 | m68hc11_add_reggroups (struct gdbarch *gdbarch) | |
1358 | { | |
1359 | reggroup_add (gdbarch, m68hc11_hard_reggroup); | |
1360 | reggroup_add (gdbarch, m68hc11_soft_reggroup); | |
b631436b SC |
1361 | } |
1362 | ||
1363 | static int | |
1364 | m68hc11_register_reggroup_p (struct gdbarch *gdbarch, int regnum, | |
dbf5d61b | 1365 | const struct reggroup *group) |
b631436b SC |
1366 | { |
1367 | /* We must save the real hard register as well as gcc | |
1368 | soft registers including the frame pointer. */ | |
1369 | if (group == save_reggroup || group == restore_reggroup) | |
1370 | { | |
1371 | return (regnum <= gdbarch_num_regs (gdbarch) | |
dda83cd7 SM |
1372 | || ((regnum == SOFT_FP_REGNUM |
1373 | || regnum == SOFT_TMP_REGNUM | |
1374 | || regnum == SOFT_ZS_REGNUM | |
1375 | || regnum == SOFT_XY_REGNUM) | |
1376 | && m68hc11_register_name (gdbarch, regnum))); | |
b631436b SC |
1377 | } |
1378 | ||
1379 | /* Group to identify gcc soft registers (d1..dN). */ | |
1380 | if (group == m68hc11_soft_reggroup) | |
1381 | { | |
d93859e2 UW |
1382 | return regnum >= SOFT_D1_REGNUM |
1383 | && m68hc11_register_name (gdbarch, regnum); | |
b631436b SC |
1384 | } |
1385 | ||
1386 | if (group == m68hc11_hard_reggroup) | |
1387 | { | |
1388 | return regnum == HARD_PC_REGNUM || regnum == HARD_SP_REGNUM | |
dda83cd7 SM |
1389 | || regnum == HARD_X_REGNUM || regnum == HARD_D_REGNUM |
1390 | || regnum == HARD_Y_REGNUM || regnum == HARD_CCR_REGNUM; | |
b631436b SC |
1391 | } |
1392 | return default_register_reggroup_p (gdbarch, regnum, group); | |
1393 | } | |
1394 | ||
82c230c2 SC |
1395 | static struct gdbarch * |
1396 | m68hc11_gdbarch_init (struct gdbarch_info info, | |
dda83cd7 | 1397 | struct gdbarch_list *arches) |
82c230c2 | 1398 | { |
81967506 | 1399 | int elf_flags; |
82c230c2 SC |
1400 | |
1401 | soft_reg_initialized = 0; | |
81967506 SC |
1402 | |
1403 | /* Extract the elf_flags if available. */ | |
1404 | if (info.abfd != NULL | |
1405 | && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) | |
1406 | elf_flags = elf_elfheader (info.abfd)->e_flags; | |
1407 | else | |
1408 | elf_flags = 0; | |
1409 | ||
025bb325 | 1410 | /* Try to find a pre-existing architecture. */ |
82c230c2 SC |
1411 | for (arches = gdbarch_list_lookup_by_info (arches, &info); |
1412 | arches != NULL; | |
1413 | arches = gdbarch_list_lookup_by_info (arches->next, &info)) | |
1414 | { | |
345bd07c | 1415 | m68gc11_gdbarch_tdep *tdep |
08106042 | 1416 | = gdbarch_tdep<m68gc11_gdbarch_tdep> (arches->gdbarch); |
345bd07c SM |
1417 | |
1418 | if (tdep->elf_flags != elf_flags) | |
81967506 SC |
1419 | continue; |
1420 | ||
82c230c2 SC |
1421 | return arches->gdbarch; |
1422 | } | |
1423 | ||
025bb325 | 1424 | /* Need a new architecture. Fill in a target specific vector. */ |
2b16913c SM |
1425 | gdbarch *gdbarch |
1426 | = gdbarch_alloc (&info, gdbarch_tdep_up (new m68gc11_gdbarch_tdep)); | |
1427 | m68gc11_gdbarch_tdep *tdep = gdbarch_tdep<m68gc11_gdbarch_tdep> (gdbarch); | |
1428 | ||
81967506 | 1429 | tdep->elf_flags = elf_flags; |
ed99b3d0 | 1430 | |
5d1a66bd SC |
1431 | switch (info.bfd_arch_info->arch) |
1432 | { | |
1433 | case bfd_arch_m68hc11: | |
1434 | tdep->stack_correction = 1; | |
7df11f59 | 1435 | tdep->use_page_register = 0; |
908f682f | 1436 | tdep->prologue = m6811_prologue; |
548bcbec SC |
1437 | set_gdbarch_addr_bit (gdbarch, 16); |
1438 | set_gdbarch_num_pseudo_regs (gdbarch, M68HC11_NUM_PSEUDO_REGS); | |
1439 | set_gdbarch_pc_regnum (gdbarch, HARD_PC_REGNUM); | |
1440 | set_gdbarch_num_regs (gdbarch, M68HC11_NUM_REGS); | |
5d1a66bd | 1441 | break; |
82c230c2 | 1442 | |
5d1a66bd SC |
1443 | case bfd_arch_m68hc12: |
1444 | tdep->stack_correction = 0; | |
7df11f59 | 1445 | tdep->use_page_register = elf_flags & E_M68HC12_BANKS; |
908f682f | 1446 | tdep->prologue = m6812_prologue; |
548bcbec SC |
1447 | set_gdbarch_addr_bit (gdbarch, elf_flags & E_M68HC12_BANKS ? 32 : 16); |
1448 | set_gdbarch_num_pseudo_regs (gdbarch, | |
dda83cd7 SM |
1449 | elf_flags & E_M68HC12_BANKS |
1450 | ? M68HC12_NUM_PSEUDO_REGS | |
1451 | : M68HC11_NUM_PSEUDO_REGS); | |
548bcbec | 1452 | set_gdbarch_pc_regnum (gdbarch, elf_flags & E_M68HC12_BANKS |
dda83cd7 | 1453 | ? M68HC12_HARD_PC_REGNUM : HARD_PC_REGNUM); |
548bcbec | 1454 | set_gdbarch_num_regs (gdbarch, elf_flags & E_M68HC12_BANKS |
dda83cd7 | 1455 | ? M68HC12_NUM_REGS : M68HC11_NUM_REGS); |
5d1a66bd SC |
1456 | break; |
1457 | ||
1458 | default: | |
1459 | break; | |
1460 | } | |
7d32ba20 SC |
1461 | |
1462 | /* Initially set everything according to the ABI. | |
1463 | Use 16-bit integers since it will be the case for most | |
1464 | programs. The size of these types should normally be set | |
1465 | according to the dwarf2 debug information. */ | |
82c230c2 | 1466 | set_gdbarch_short_bit (gdbarch, 16); |
81967506 | 1467 | set_gdbarch_int_bit (gdbarch, elf_flags & E_M68HC11_I32 ? 32 : 16); |
82c230c2 | 1468 | set_gdbarch_float_bit (gdbarch, 32); |
f92589cb TS |
1469 | if (elf_flags & E_M68HC11_F64) |
1470 | { | |
1471 | set_gdbarch_double_bit (gdbarch, 64); | |
1472 | set_gdbarch_double_format (gdbarch, floatformats_ieee_double); | |
1473 | } | |
1474 | else | |
1475 | { | |
1476 | set_gdbarch_double_bit (gdbarch, 32); | |
1477 | set_gdbarch_double_format (gdbarch, floatformats_ieee_single); | |
1478 | } | |
2417dd25 | 1479 | set_gdbarch_long_double_bit (gdbarch, 64); |
82c230c2 SC |
1480 | set_gdbarch_long_bit (gdbarch, 32); |
1481 | set_gdbarch_ptr_bit (gdbarch, 16); | |
1482 | set_gdbarch_long_long_bit (gdbarch, 64); | |
1483 | ||
b2a02dda SC |
1484 | /* Characters are unsigned. */ |
1485 | set_gdbarch_char_signed (gdbarch, 0); | |
1486 | ||
82c230c2 SC |
1487 | /* Set register info. */ |
1488 | set_gdbarch_fp0_regnum (gdbarch, -1); | |
82c230c2 | 1489 | |
82c230c2 | 1490 | set_gdbarch_sp_regnum (gdbarch, HARD_SP_REGNUM); |
82c230c2 | 1491 | set_gdbarch_register_name (gdbarch, m68hc11_register_name); |
4db73d49 | 1492 | set_gdbarch_register_type (gdbarch, m68hc11_register_type); |
46ce284d AC |
1493 | set_gdbarch_pseudo_register_read (gdbarch, m68hc11_pseudo_register_read); |
1494 | set_gdbarch_pseudo_register_write (gdbarch, m68hc11_pseudo_register_write); | |
82c230c2 | 1495 | |
3dc990bf SC |
1496 | set_gdbarch_push_dummy_call (gdbarch, m68hc11_push_dummy_call); |
1497 | ||
97092415 | 1498 | set_gdbarch_return_value (gdbarch, m68hc11_return_value); |
82c230c2 SC |
1499 | set_gdbarch_skip_prologue (gdbarch, m68hc11_skip_prologue); |
1500 | set_gdbarch_inner_than (gdbarch, core_addr_lessthan); | |
04180708 YQ |
1501 | set_gdbarch_breakpoint_kind_from_pc (gdbarch, |
1502 | m68hc11_breakpoint::kind_from_pc); | |
1503 | set_gdbarch_sw_breakpoint_from_kind (gdbarch, | |
1504 | m68hc11_breakpoint::bp_from_kind); | |
82c230c2 | 1505 | |
b631436b SC |
1506 | m68hc11_add_reggroups (gdbarch); |
1507 | set_gdbarch_register_reggroup_p (gdbarch, m68hc11_register_reggroup_p); | |
e286caf2 | 1508 | set_gdbarch_print_registers_info (gdbarch, m68hc11_print_registers_info); |
b631436b | 1509 | |
1ea653ae | 1510 | /* Hook in the DWARF CFI frame unwinder. */ |
94afd7a6 | 1511 | dwarf2_append_unwinders (gdbarch); |
1ea653ae | 1512 | |
94afd7a6 | 1513 | frame_unwind_append_unwinder (gdbarch, &m68hc11_frame_unwind); |
1ea653ae SC |
1514 | frame_base_set_default (gdbarch, &m68hc11_frame_base); |
1515 | ||
1516 | /* Methods for saving / extracting a dummy frame's ID. The ID's | |
1517 | stack address must match the SP value returned by | |
1518 | PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ | |
94afd7a6 | 1519 | set_gdbarch_dummy_id (gdbarch, m68hc11_dummy_id); |
1ea653ae | 1520 | |
7df11f59 SC |
1521 | /* Minsymbol frobbing. */ |
1522 | set_gdbarch_elf_make_msymbol_special (gdbarch, | |
dda83cd7 | 1523 | m68hc11_elf_make_msymbol_special); |
7df11f59 | 1524 | |
82c230c2 | 1525 | set_gdbarch_believe_pcc_promotion (gdbarch, 1); |
82c230c2 SC |
1526 | |
1527 | return gdbarch; | |
78073dd8 AC |
1528 | } |
1529 | ||
6c265988 | 1530 | void _initialize_m68hc11_tdep (); |
78073dd8 | 1531 | void |
6c265988 | 1532 | _initialize_m68hc11_tdep () |
78073dd8 | 1533 | { |
ec29a63c TT |
1534 | gdbarch_register (bfd_arch_m68hc11, m68hc11_gdbarch_init); |
1535 | gdbarch_register (bfd_arch_m68hc12, m68hc11_gdbarch_init); | |
b631436b | 1536 | m68hc11_init_reggroups (); |
78073dd8 AC |
1537 | } |
1538 |